1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
284 #define UNCOND_JUMP 2
288 #define SMALL16 (SMALL|CODE16)
290 #define BIG16 (BIG|CODE16)
294 #define INLINE __inline__
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table
[] =
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
345 static const arch_entry cpu_arch
[] = {
347 {"i186", Cpu086
|Cpu186
},
348 {"i286", Cpu086
|Cpu186
|Cpu286
},
349 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
350 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
351 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
352 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
353 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
354 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
355 {"pentium4", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuP4
|CpuMMX
|CpuSSE
|CpuSSE2
},
356 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
357 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
358 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
|CpuSSE2
},
363 i386_align_code (fragP
, count
)
367 /* Various efficient no-op patterns for aligning code labels.
368 Note: Don't try to assemble the instructions in the comments.
369 0L and 0w are not legal. */
370 static const char f32_1
[] =
372 static const char f32_2
[] =
373 {0x89,0xf6}; /* movl %esi,%esi */
374 static const char f32_3
[] =
375 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
376 static const char f32_4
[] =
377 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
378 static const char f32_5
[] =
380 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
381 static const char f32_6
[] =
382 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
383 static const char f32_7
[] =
384 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
385 static const char f32_8
[] =
387 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
388 static const char f32_9
[] =
389 {0x89,0xf6, /* movl %esi,%esi */
390 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
391 static const char f32_10
[] =
392 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
393 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
394 static const char f32_11
[] =
395 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
396 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
397 static const char f32_12
[] =
398 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
399 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
400 static const char f32_13
[] =
401 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
402 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
403 static const char f32_14
[] =
404 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
405 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
406 static const char f32_15
[] =
407 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
408 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
409 static const char f16_3
[] =
410 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
411 static const char f16_4
[] =
412 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
413 static const char f16_5
[] =
415 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
416 static const char f16_6
[] =
417 {0x89,0xf6, /* mov %si,%si */
418 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
419 static const char f16_7
[] =
420 {0x8d,0x74,0x00, /* lea 0(%si),%si */
421 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
422 static const char f16_8
[] =
423 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
424 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
425 static const char *const f32_patt
[] = {
426 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
427 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
429 static const char *const f16_patt
[] = {
430 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
431 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
434 /* ??? We can't use these fillers for x86_64, since they often kills the
435 upper halves. Solve later. */
436 if (flag_code
== CODE_64BIT
)
439 if (count
> 0 && count
<= 15)
441 if (flag_code
== CODE_16BIT
)
443 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
444 f16_patt
[count
- 1], count
);
446 /* Adjust jump offset. */
447 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
450 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
451 f32_patt
[count
- 1], count
);
452 fragP
->fr_var
= count
;
456 static char *output_invalid
PARAMS ((int c
));
457 static int i386_operand
PARAMS ((char *operand_string
));
458 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
459 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
463 static void s_bss
PARAMS ((int));
466 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
468 static INLINE
unsigned int
469 mode_from_disp_size (t
)
472 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
476 fits_in_signed_byte (num
)
479 return (num
>= -128) && (num
<= 127);
483 fits_in_unsigned_byte (num
)
486 return (num
& 0xff) == num
;
490 fits_in_unsigned_word (num
)
493 return (num
& 0xffff) == num
;
497 fits_in_signed_word (num
)
500 return (-32768 <= num
) && (num
<= 32767);
503 fits_in_signed_long (num
)
504 offsetT num ATTRIBUTE_UNUSED
;
509 return (!(((offsetT
) -1 << 31) & num
)
510 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
512 } /* fits_in_signed_long() */
514 fits_in_unsigned_long (num
)
515 offsetT num ATTRIBUTE_UNUSED
;
520 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
522 } /* fits_in_unsigned_long() */
525 smallest_imm_type (num
)
528 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
529 && !(cpu_arch_flags
& (CpuUnknown
)))
531 /* This code is disabled on the 486 because all the Imm1 forms
532 in the opcode table are slower on the i486. They're the
533 versions with the implicitly specified single-position
534 displacement, which has another syntax if you really want to
537 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
539 return (fits_in_signed_byte (num
)
540 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
541 : fits_in_unsigned_byte (num
)
542 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
543 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
544 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
545 : fits_in_signed_long (num
)
546 ? (Imm32
| Imm32S
| Imm64
)
547 : fits_in_unsigned_long (num
)
553 offset_in_range (val
, size
)
561 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
562 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
563 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
565 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
570 /* If BFD64, sign extend val. */
571 if (!use_rela_relocations
)
572 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
573 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
575 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
577 char buf1
[40], buf2
[40];
579 sprint_value (buf1
, val
);
580 sprint_value (buf2
, val
& mask
);
581 as_warn (_("%s shortened to %s"), buf1
, buf2
);
586 /* Returns 0 if attempting to add a prefix where one from the same
587 class already exists, 1 if non rep/repne added, 2 if rep/repne
596 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
604 case CS_PREFIX_OPCODE
:
605 case DS_PREFIX_OPCODE
:
606 case ES_PREFIX_OPCODE
:
607 case FS_PREFIX_OPCODE
:
608 case GS_PREFIX_OPCODE
:
609 case SS_PREFIX_OPCODE
:
613 case REPNE_PREFIX_OPCODE
:
614 case REPE_PREFIX_OPCODE
:
617 case LOCK_PREFIX_OPCODE
:
625 case ADDR_PREFIX_OPCODE
:
629 case DATA_PREFIX_OPCODE
:
636 as_bad (_("same type of prefix used twice"));
641 i
.prefix
[q
] = prefix
;
646 set_code_flag (value
)
650 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
651 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
652 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
654 as_bad (_("64bit mode not supported on this CPU."));
656 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
658 as_bad (_("32bit mode not supported on this CPU."));
664 set_16bit_gcc_code_flag (new_code_flag
)
667 flag_code
= new_code_flag
;
668 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
669 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
674 set_intel_syntax (syntax_flag
)
677 /* Find out if register prefixing is specified. */
678 int ask_naked_reg
= 0;
681 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
683 char *string
= input_line_pointer
;
684 int e
= get_symbol_end ();
686 if (strcmp (string
, "prefix") == 0)
688 else if (strcmp (string
, "noprefix") == 0)
691 as_bad (_("bad argument to syntax directive."));
692 *input_line_pointer
= e
;
694 demand_empty_rest_of_line ();
696 intel_syntax
= syntax_flag
;
698 if (ask_naked_reg
== 0)
701 allow_naked_reg
= (intel_syntax
702 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
704 /* Conservative default. */
709 allow_naked_reg
= (ask_naked_reg
< 0);
714 int dummy ATTRIBUTE_UNUSED
;
718 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
720 char *string
= input_line_pointer
;
721 int e
= get_symbol_end ();
724 for (i
= 0; cpu_arch
[i
].name
; i
++)
726 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
728 cpu_arch_name
= cpu_arch
[i
].name
;
729 cpu_arch_flags
= cpu_arch
[i
].flags
| (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
733 if (!cpu_arch
[i
].name
)
734 as_bad (_("no such architecture: `%s'"), string
);
736 *input_line_pointer
= e
;
739 as_bad (_("missing cpu architecture"));
741 demand_empty_rest_of_line ();
744 const pseudo_typeS md_pseudo_table
[] =
746 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
747 {"align", s_align_bytes
, 0},
749 {"align", s_align_ptwo
, 0},
751 {"arch", set_cpu_arch
, 0},
755 {"ffloat", float_cons
, 'f'},
756 {"dfloat", float_cons
, 'd'},
757 {"tfloat", float_cons
, 'x'},
759 {"noopt", s_ignore
, 0},
760 {"optim", s_ignore
, 0},
761 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
762 {"code16", set_code_flag
, CODE_16BIT
},
763 {"code32", set_code_flag
, CODE_32BIT
},
764 {"code64", set_code_flag
, CODE_64BIT
},
765 {"intel_syntax", set_intel_syntax
, 1},
766 {"att_syntax", set_intel_syntax
, 0},
767 {"file", dwarf2_directive_file
, 0},
768 {"loc", dwarf2_directive_loc
, 0},
772 /* For interface with expression (). */
773 extern char *input_line_pointer
;
775 /* Hash table for instruction mnemonic lookup. */
776 static struct hash_control
*op_hash
;
778 /* Hash table for register lookup. */
779 static struct hash_control
*reg_hash
;
785 if (!strcmp (default_arch
, "x86_64"))
786 return bfd_mach_x86_64
;
787 else if (!strcmp (default_arch
, "i386"))
788 return bfd_mach_i386_i386
;
790 as_fatal (_("Unknown architecture"));
797 const char *hash_err
;
799 /* Initialize op_hash hash table. */
800 op_hash
= hash_new ();
803 register const template *optab
;
804 register templates
*core_optab
;
806 /* Setup for loop. */
808 core_optab
= (templates
*) xmalloc (sizeof (templates
));
809 core_optab
->start
= optab
;
814 if (optab
->name
== NULL
815 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
817 /* different name --> ship out current template list;
818 add to hash table; & begin anew. */
819 core_optab
->end
= optab
;
820 hash_err
= hash_insert (op_hash
,
825 as_fatal (_("Internal Error: Can't hash %s: %s"),
829 if (optab
->name
== NULL
)
831 core_optab
= (templates
*) xmalloc (sizeof (templates
));
832 core_optab
->start
= optab
;
837 /* Initialize reg_hash hash table. */
838 reg_hash
= hash_new ();
840 register const reg_entry
*regtab
;
842 for (regtab
= i386_regtab
;
843 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
846 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
848 as_fatal (_("Internal Error: Can't hash %s: %s"),
854 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
859 for (c
= 0; c
< 256; c
++)
864 mnemonic_chars
[c
] = c
;
865 register_chars
[c
] = c
;
866 operand_chars
[c
] = c
;
868 else if (islower (c
))
870 mnemonic_chars
[c
] = c
;
871 register_chars
[c
] = c
;
872 operand_chars
[c
] = c
;
874 else if (isupper (c
))
876 mnemonic_chars
[c
] = tolower (c
);
877 register_chars
[c
] = mnemonic_chars
[c
];
878 operand_chars
[c
] = c
;
881 if (isalpha (c
) || isdigit (c
))
882 identifier_chars
[c
] = c
;
885 identifier_chars
[c
] = c
;
886 operand_chars
[c
] = c
;
891 identifier_chars
['@'] = '@';
893 digit_chars
['-'] = '-';
894 identifier_chars
['_'] = '_';
895 identifier_chars
['.'] = '.';
897 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
898 operand_chars
[(unsigned char) *p
] = *p
;
901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
902 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
904 record_alignment (text_section
, 2);
905 record_alignment (data_section
, 2);
906 record_alignment (bss_section
, 2);
912 i386_print_statistics (file
)
915 hash_print_statistics (file
, "i386 opcode", op_hash
);
916 hash_print_statistics (file
, "i386 register", reg_hash
);
921 /* Debugging routines for md_assemble. */
922 static void pi
PARAMS ((char *, i386_insn
*));
923 static void pte
PARAMS ((template *));
924 static void pt
PARAMS ((unsigned int));
925 static void pe
PARAMS ((expressionS
*));
926 static void ps
PARAMS ((symbolS
*));
935 fprintf (stdout
, "%s: template ", line
);
937 fprintf (stdout
, " address: base %s index %s scale %x\n",
938 x
->base_reg
? x
->base_reg
->reg_name
: "none",
939 x
->index_reg
? x
->index_reg
->reg_name
: "none",
940 x
->log2_scale_factor
);
941 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
942 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
943 fprintf (stdout
, " sib: base %x index %x scale %x\n",
944 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
945 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
946 x
->rex
.mode64
, x
->rex
.extX
, x
->rex
.extY
, x
->rex
.extZ
);
947 for (i
= 0; i
< x
->operands
; i
++)
949 fprintf (stdout
, " #%d: ", i
+ 1);
951 fprintf (stdout
, "\n");
953 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
954 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
955 if (x
->types
[i
] & Imm
)
957 if (x
->types
[i
] & Disp
)
967 fprintf (stdout
, " %d operands ", t
->operands
);
968 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
969 if (t
->extension_opcode
!= None
)
970 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
971 if (t
->opcode_modifier
& D
)
972 fprintf (stdout
, "D");
973 if (t
->opcode_modifier
& W
)
974 fprintf (stdout
, "W");
975 fprintf (stdout
, "\n");
976 for (i
= 0; i
< t
->operands
; i
++)
978 fprintf (stdout
, " #%d type ", i
+ 1);
979 pt (t
->operand_types
[i
]);
980 fprintf (stdout
, "\n");
988 fprintf (stdout
, " operation %d\n", e
->X_op
);
989 fprintf (stdout
, " add_number %ld (%lx)\n",
990 (long) e
->X_add_number
, (long) e
->X_add_number
);
993 fprintf (stdout
, " add_symbol ");
994 ps (e
->X_add_symbol
);
995 fprintf (stdout
, "\n");
999 fprintf (stdout
, " op_symbol ");
1000 ps (e
->X_op_symbol
);
1001 fprintf (stdout
, "\n");
1009 fprintf (stdout
, "%s type %s%s",
1011 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
1012 segment_name (S_GET_SEGMENT (s
)));
1034 { BaseIndex
, "BaseIndex" },
1038 { Disp32S
, "d32s" },
1040 { InOutPortReg
, "InOutPortReg" },
1041 { ShiftCount
, "ShiftCount" },
1042 { Control
, "control reg" },
1043 { Test
, "test reg" },
1044 { Debug
, "debug reg" },
1045 { FloatReg
, "FReg" },
1046 { FloatAcc
, "FAcc" },
1050 { JumpAbsolute
, "Jump Absolute" },
1061 register struct type_name
*ty
;
1063 for (ty
= type_names
; ty
->mask
; ty
++)
1065 fprintf (stdout
, "%s, ", ty
->tname
);
1069 #endif /* DEBUG386 */
1072 tc_i386_force_relocation (fixp
)
1075 #ifdef BFD_ASSEMBLER
1076 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1077 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1082 return fixp
->fx_r_type
== 7;
1086 #ifdef BFD_ASSEMBLER
1088 static bfd_reloc_code_real_type
1089 reloc (size
, pcrel
, sign
, other
)
1093 bfd_reloc_code_real_type other
;
1095 if (other
!= NO_RELOC
)
1101 as_bad (_("There are no unsigned pc-relative relocations"));
1104 case 1: return BFD_RELOC_8_PCREL
;
1105 case 2: return BFD_RELOC_16_PCREL
;
1106 case 4: return BFD_RELOC_32_PCREL
;
1108 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1115 case 4: return BFD_RELOC_X86_64_32S
;
1120 case 1: return BFD_RELOC_8
;
1121 case 2: return BFD_RELOC_16
;
1122 case 4: return BFD_RELOC_32
;
1123 case 8: return BFD_RELOC_64
;
1125 as_bad (_("can not do %s %d byte relocation"),
1126 sign
? "signed" : "unsigned", size
);
1130 return BFD_RELOC_NONE
;
1133 /* Here we decide which fixups can be adjusted to make them relative to
1134 the beginning of the section instead of the symbol. Basically we need
1135 to make sure that the dynamic relocations are done correctly, so in
1136 some cases we force the original symbol to be used. */
1139 tc_i386_fix_adjustable (fixP
)
1142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1143 /* Prevent all adjustments to global symbols, or else dynamic
1144 linking will not work correctly. */
1145 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1146 || S_IS_WEAK (fixP
->fx_addsy
))
1149 /* adjust_reloc_syms doesn't know about the GOT. */
1150 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1151 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1152 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1153 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1154 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1155 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1156 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1161 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1162 #define BFD_RELOC_16 0
1163 #define BFD_RELOC_32 0
1164 #define BFD_RELOC_16_PCREL 0
1165 #define BFD_RELOC_32_PCREL 0
1166 #define BFD_RELOC_386_PLT32 0
1167 #define BFD_RELOC_386_GOT32 0
1168 #define BFD_RELOC_386_GOTOFF 0
1169 #define BFD_RELOC_X86_64_PLT32 0
1170 #define BFD_RELOC_X86_64_GOT32 0
1171 #define BFD_RELOC_X86_64_GOTPCREL 0
1174 static int intel_float_operand
PARAMS ((char *mnemonic
));
1177 intel_float_operand (mnemonic
)
1180 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1183 if (mnemonic
[0] == 'f')
1189 /* This is the guts of the machine-dependent assembler. LINE points to a
1190 machine dependent instruction. This function is supposed to emit
1191 the frags/bytes it assembles to. */
1197 /* Points to template once we've found it. */
1200 /* Count the size of the instruction generated. */
1205 char mnemonic
[MAX_MNEM_SIZE
];
1207 /* Initialize globals. */
1208 memset (&i
, '\0', sizeof (i
));
1209 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1210 i
.disp_reloc
[j
] = NO_RELOC
;
1211 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1212 memset (im_expressions
, '\0', sizeof (im_expressions
));
1213 save_stack_p
= save_stack
;
1215 /* First parse an instruction mnemonic & call i386_operand for the operands.
1216 We assume that the scrubber has arranged it so that line[0] is the valid
1217 start of a (possibly prefixed) mnemonic. */
1220 char *token_start
= l
;
1223 /* Non-zero if we found a prefix only acceptable with string insns. */
1224 const char *expecting_string_instruction
= NULL
;
1229 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1232 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1234 as_bad (_("no such instruction: `%s'"), token_start
);
1239 if (!is_space_char (*l
)
1240 && *l
!= END_OF_INSN
1241 && *l
!= PREFIX_SEPARATOR
)
1243 as_bad (_("invalid character %s in mnemonic"),
1244 output_invalid (*l
));
1247 if (token_start
== l
)
1249 if (*l
== PREFIX_SEPARATOR
)
1250 as_bad (_("expecting prefix; got nothing"));
1252 as_bad (_("expecting mnemonic; got nothing"));
1256 /* Look up instruction (or prefix) via hash table. */
1257 current_templates
= hash_find (op_hash
, mnemonic
);
1259 if (*l
!= END_OF_INSN
1260 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1261 && current_templates
1262 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1264 /* If we are in 16-bit mode, do not allow addr16 or data16.
1265 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1266 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1267 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1268 ^ (flag_code
== CODE_16BIT
)))
1270 as_bad (_("redundant %s prefix"),
1271 current_templates
->start
->name
);
1274 /* Add prefix, checking for repeated prefixes. */
1275 switch (add_prefix (current_templates
->start
->base_opcode
))
1280 expecting_string_instruction
= current_templates
->start
->name
;
1283 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1290 if (!current_templates
)
1292 /* See if we can get a match by trimming off a suffix. */
1295 case WORD_MNEM_SUFFIX
:
1296 case BYTE_MNEM_SUFFIX
:
1297 case QWORD_MNEM_SUFFIX
:
1298 i
.suffix
= mnem_p
[-1];
1300 current_templates
= hash_find (op_hash
, mnemonic
);
1302 case SHORT_MNEM_SUFFIX
:
1303 case LONG_MNEM_SUFFIX
:
1306 i
.suffix
= mnem_p
[-1];
1308 current_templates
= hash_find (op_hash
, mnemonic
);
1316 if (intel_float_operand (mnemonic
))
1317 i
.suffix
= SHORT_MNEM_SUFFIX
;
1319 i
.suffix
= LONG_MNEM_SUFFIX
;
1321 current_templates
= hash_find (op_hash
, mnemonic
);
1325 if (!current_templates
)
1327 as_bad (_("no such instruction: `%s'"), token_start
);
1332 /* Check if instruction is supported on specified architecture. */
1333 if (cpu_arch_flags
!= 0)
1335 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1336 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1338 as_warn (_("`%s' is not supported on `%s'"),
1339 current_templates
->start
->name
, cpu_arch_name
);
1341 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1343 as_warn (_("use .code16 to ensure correct addressing mode"));
1347 /* Check for rep/repne without a string instruction. */
1348 if (expecting_string_instruction
1349 && !(current_templates
->start
->opcode_modifier
& IsString
))
1351 as_bad (_("expecting string instruction after `%s'"),
1352 expecting_string_instruction
);
1356 /* There may be operands to parse. */
1357 if (*l
!= END_OF_INSN
)
1359 /* 1 if operand is pending after ','. */
1360 unsigned int expecting_operand
= 0;
1362 /* Non-zero if operand parens not balanced. */
1363 unsigned int paren_not_balanced
;
1367 /* Skip optional white space before operand. */
1368 if (is_space_char (*l
))
1370 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1372 as_bad (_("invalid character %s before operand %d"),
1373 output_invalid (*l
),
1377 token_start
= l
; /* after white space */
1378 paren_not_balanced
= 0;
1379 while (paren_not_balanced
|| *l
!= ',')
1381 if (*l
== END_OF_INSN
)
1383 if (paren_not_balanced
)
1386 as_bad (_("unbalanced parenthesis in operand %d."),
1389 as_bad (_("unbalanced brackets in operand %d."),
1394 break; /* we are done */
1396 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1398 as_bad (_("invalid character %s in operand %d"),
1399 output_invalid (*l
),
1406 ++paren_not_balanced
;
1408 --paren_not_balanced
;
1413 ++paren_not_balanced
;
1415 --paren_not_balanced
;
1419 if (l
!= token_start
)
1420 { /* Yes, we've read in another operand. */
1421 unsigned int operand_ok
;
1422 this_operand
= i
.operands
++;
1423 if (i
.operands
> MAX_OPERANDS
)
1425 as_bad (_("spurious operands; (%d operands/instruction max)"),
1429 /* Now parse operand adding info to 'i' as we go along. */
1430 END_STRING_AND_SAVE (l
);
1434 i386_intel_operand (token_start
,
1435 intel_float_operand (mnemonic
));
1437 operand_ok
= i386_operand (token_start
);
1439 RESTORE_END_STRING (l
);
1445 if (expecting_operand
)
1447 expecting_operand_after_comma
:
1448 as_bad (_("expecting operand after ','; got nothing"));
1453 as_bad (_("expecting operand before ','; got nothing"));
1458 /* Now *l must be either ',' or END_OF_INSN. */
1461 if (*++l
== END_OF_INSN
)
1463 /* Just skip it, if it's \n complain. */
1464 goto expecting_operand_after_comma
;
1466 expecting_operand
= 1;
1469 while (*l
!= END_OF_INSN
);
1473 /* Now we've parsed the mnemonic into a set of templates, and have the
1476 Next, we find a template that matches the given insn,
1477 making sure the overlap of the given operands types is consistent
1478 with the template operand types. */
1480 #define MATCH(overlap, given, template) \
1481 ((overlap & ~JumpAbsolute) \
1482 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1484 /* If given types r0 and r1 are registers they must be of the same type
1485 unless the expected operand type register overlap is null.
1486 Note that Acc in a template matches every size of reg. */
1487 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1488 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1489 ((g0) & Reg) == ((g1) & Reg) || \
1490 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1493 register unsigned int overlap0
, overlap1
;
1494 unsigned int overlap2
;
1495 unsigned int found_reverse_match
;
1498 /* All intel opcodes have reversed operands except for "bound" and
1499 "enter". We also don't reverse intersegment "jmp" and "call"
1500 instructions with 2 immediate operands so that the immediate segment
1501 precedes the offset, as it does when in AT&T mode. "enter" and the
1502 intersegment "jmp" and "call" instructions are the only ones that
1503 have two immediate operands. */
1504 if (intel_syntax
&& i
.operands
> 1
1505 && (strcmp (mnemonic
, "bound") != 0)
1506 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1508 union i386_op temp_op
;
1509 unsigned int temp_type
;
1510 #ifdef BFD_ASSEMBLER
1511 enum bfd_reloc_code_real temp_reloc
;
1518 if (i
.operands
== 2)
1523 else if (i
.operands
== 3)
1528 temp_type
= i
.types
[xchg2
];
1529 i
.types
[xchg2
] = i
.types
[xchg1
];
1530 i
.types
[xchg1
] = temp_type
;
1531 temp_op
= i
.op
[xchg2
];
1532 i
.op
[xchg2
] = i
.op
[xchg1
];
1533 i
.op
[xchg1
] = temp_op
;
1534 temp_reloc
= i
.disp_reloc
[xchg2
];
1535 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1536 i
.disp_reloc
[xchg1
] = temp_reloc
;
1538 if (i
.mem_operands
== 2)
1540 const seg_entry
*temp_seg
;
1541 temp_seg
= i
.seg
[0];
1542 i
.seg
[0] = i
.seg
[1];
1543 i
.seg
[1] = temp_seg
;
1549 /* Try to ensure constant immediates are represented in the smallest
1551 char guess_suffix
= 0;
1555 guess_suffix
= i
.suffix
;
1556 else if (i
.reg_operands
)
1558 /* Figure out a suffix from the last register operand specified.
1559 We can't do this properly yet, ie. excluding InOutPortReg,
1560 but the following works for instructions with immediates.
1561 In any case, we can't set i.suffix yet. */
1562 for (op
= i
.operands
; --op
>= 0;)
1563 if (i
.types
[op
] & Reg
)
1565 if (i
.types
[op
] & Reg8
)
1566 guess_suffix
= BYTE_MNEM_SUFFIX
;
1567 else if (i
.types
[op
] & Reg16
)
1568 guess_suffix
= WORD_MNEM_SUFFIX
;
1569 else if (i
.types
[op
] & Reg32
)
1570 guess_suffix
= LONG_MNEM_SUFFIX
;
1571 else if (i
.types
[op
] & Reg64
)
1572 guess_suffix
= QWORD_MNEM_SUFFIX
;
1576 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1577 guess_suffix
= WORD_MNEM_SUFFIX
;
1579 for (op
= i
.operands
; --op
>= 0;)
1580 if (i
.types
[op
] & Imm
)
1582 switch (i
.op
[op
].imms
->X_op
)
1585 /* If a suffix is given, this operand may be shortened. */
1586 switch (guess_suffix
)
1588 case LONG_MNEM_SUFFIX
:
1589 i
.types
[op
] |= Imm32
| Imm64
;
1591 case WORD_MNEM_SUFFIX
:
1592 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1594 case BYTE_MNEM_SUFFIX
:
1595 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1599 /* If this operand is at most 16 bits, convert it
1600 to a signed 16 bit number before trying to see
1601 whether it will fit in an even smaller size.
1602 This allows a 16-bit operand such as $0xffe0 to
1603 be recognised as within Imm8S range. */
1604 if ((i
.types
[op
] & Imm16
)
1605 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
1607 i
.op
[op
].imms
->X_add_number
=
1608 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1610 if ((i
.types
[op
] & Imm32
)
1611 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1613 i
.op
[op
].imms
->X_add_number
=
1614 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1616 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1617 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1618 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1619 i
.types
[op
] &= ~Imm32
;
1624 /* Symbols and expressions. */
1626 /* Convert symbolic operand to proper sizes for matching. */
1627 switch (guess_suffix
)
1629 case QWORD_MNEM_SUFFIX
:
1630 i
.types
[op
] = Imm64
| Imm32S
;
1632 case LONG_MNEM_SUFFIX
:
1633 i
.types
[op
] = Imm32
| Imm64
;
1635 case WORD_MNEM_SUFFIX
:
1636 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1639 case BYTE_MNEM_SUFFIX
:
1640 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1649 if (i
.disp_operands
)
1651 /* Try to use the smallest displacement type too. */
1654 for (op
= i
.operands
; --op
>= 0;)
1655 if ((i
.types
[op
] & Disp
)
1656 && i
.op
[op
].imms
->X_op
== O_constant
)
1658 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1660 if (i
.types
[op
] & Disp16
)
1662 /* We know this operand is at most 16 bits, so
1663 convert to a signed 16 bit number before trying
1664 to see whether it will fit in an even smaller
1667 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1669 else if (i
.types
[op
] & Disp32
)
1671 /* We know this operand is at most 32 bits, so convert to a
1672 signed 32 bit number before trying to see whether it will
1673 fit in an even smaller size. */
1674 disp
&= (((offsetT
) 2 << 31) - 1);
1675 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1677 if (flag_code
== CODE_64BIT
)
1679 if (fits_in_signed_long (disp
))
1680 i
.types
[op
] |= Disp32S
;
1681 if (fits_in_unsigned_long (disp
))
1682 i
.types
[op
] |= Disp32
;
1684 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1685 && fits_in_signed_byte (disp
))
1686 i
.types
[op
] |= Disp8
;
1693 found_reverse_match
= 0;
1694 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1696 : (i
.suffix
== WORD_MNEM_SUFFIX
1698 : (i
.suffix
== SHORT_MNEM_SUFFIX
1700 : (i
.suffix
== LONG_MNEM_SUFFIX
1702 : (i
.suffix
== QWORD_MNEM_SUFFIX
1704 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1706 for (t
= current_templates
->start
;
1707 t
< current_templates
->end
;
1710 /* Must have right number of operands. */
1711 if (i
.operands
!= t
->operands
)
1714 /* Check the suffix, except for some instructions in intel mode. */
1715 if ((t
->opcode_modifier
& suffix_check
)
1717 && (t
->opcode_modifier
& IgnoreSize
))
1719 && t
->base_opcode
== 0xd9
1720 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1721 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1724 /* Do not verify operands when there are none. */
1725 else if (!t
->operands
)
1727 if (t
->cpu_flags
& ~cpu_arch_flags
)
1729 /* We've found a match; break out of loop. */
1733 overlap0
= i
.types
[0] & t
->operand_types
[0];
1734 switch (t
->operands
)
1737 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1742 overlap1
= i
.types
[1] & t
->operand_types
[1];
1743 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1744 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1745 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1746 t
->operand_types
[0],
1747 overlap1
, i
.types
[1],
1748 t
->operand_types
[1]))
1750 /* Check if other direction is valid ... */
1751 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1754 /* Try reversing direction of operands. */
1755 overlap0
= i
.types
[0] & t
->operand_types
[1];
1756 overlap1
= i
.types
[1] & t
->operand_types
[0];
1757 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1758 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1759 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1760 t
->operand_types
[1],
1761 overlap1
, i
.types
[1],
1762 t
->operand_types
[0]))
1764 /* Does not match either direction. */
1767 /* found_reverse_match holds which of D or FloatDR
1769 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1771 /* Found a forward 2 operand match here. */
1772 else if (t
->operands
== 3)
1774 /* Here we make use of the fact that there are no
1775 reverse match 3 operand instructions, and all 3
1776 operand instructions only need to be checked for
1777 register consistency between operands 2 and 3. */
1778 overlap2
= i
.types
[2] & t
->operand_types
[2];
1779 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1780 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1781 t
->operand_types
[1],
1782 overlap2
, i
.types
[2],
1783 t
->operand_types
[2]))
1787 /* Found either forward/reverse 2 or 3 operand match here:
1788 slip through to break. */
1790 if (t
->cpu_flags
& ~cpu_arch_flags
)
1792 found_reverse_match
= 0;
1795 /* We've found a match; break out of loop. */
1798 if (t
== current_templates
->end
)
1800 /* We found no match. */
1801 as_bad (_("suffix or operands invalid for `%s'"),
1802 current_templates
->start
->name
);
1806 if (!quiet_warnings
)
1809 && ((i
.types
[0] & JumpAbsolute
)
1810 != (t
->operand_types
[0] & JumpAbsolute
)))
1812 as_warn (_("indirect %s without `*'"), t
->name
);
1815 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1816 == (IsPrefix
|IgnoreSize
))
1818 /* Warn them that a data or address size prefix doesn't
1819 affect assembly of the next line of code. */
1820 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1824 /* Copy the template we found. */
1826 if (found_reverse_match
)
1828 /* If we found a reverse match we must alter the opcode
1829 direction bit. found_reverse_match holds bits to change
1830 (different for int & float insns). */
1832 i
.tm
.base_opcode
^= found_reverse_match
;
1834 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1835 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1838 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1841 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1842 i
.tm
.base_opcode
^= FloatR
;
1844 if (i
.tm
.opcode_modifier
& FWait
)
1845 if (! add_prefix (FWAIT_OPCODE
))
1848 /* Check string instruction segment overrides. */
1849 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1851 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1852 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1854 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1856 as_bad (_("`%s' operand %d must use `%%es' segment"),
1861 /* There's only ever one segment override allowed per instruction.
1862 This instruction possibly has a legal segment override on the
1863 second operand, so copy the segment to where non-string
1864 instructions store it, allowing common code. */
1865 i
.seg
[0] = i
.seg
[1];
1867 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1869 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1871 as_bad (_("`%s' operand %d must use `%%es' segment"),
1879 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1882 for (op
= i
.operands
; --op
>= 0;)
1883 if ((i
.types
[op
] & Reg
)
1884 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1886 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1887 i
.op
[op
].regs
->reg_name
);
1892 /* If matched instruction specifies an explicit instruction mnemonic
1894 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1896 if (i
.tm
.opcode_modifier
& Size16
)
1897 i
.suffix
= WORD_MNEM_SUFFIX
;
1898 else if (i
.tm
.opcode_modifier
& Size64
)
1899 i
.suffix
= QWORD_MNEM_SUFFIX
;
1901 i
.suffix
= LONG_MNEM_SUFFIX
;
1903 else if (i
.reg_operands
)
1905 /* If there's no instruction mnemonic suffix we try to invent one
1906 based on register operands. */
1909 /* We take i.suffix from the last register operand specified,
1910 Destination register type is more significant than source
1913 for (op
= i
.operands
; --op
>= 0;)
1914 if ((i
.types
[op
] & Reg
)
1915 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1917 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1918 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1919 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1924 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1927 for (op
= i
.operands
; --op
>= 0;)
1929 /* If this is an eight bit register, it's OK. If it's
1930 the 16 or 32 bit version of an eight bit register,
1931 we will just use the low portion, and that's OK too. */
1932 if (i
.types
[op
] & Reg8
)
1935 /* movzx and movsx should not generate this warning. */
1937 && (i
.tm
.base_opcode
== 0xfb7
1938 || i
.tm
.base_opcode
== 0xfb6
1939 || i
.tm
.base_opcode
== 0x63
1940 || i
.tm
.base_opcode
== 0xfbe
1941 || i
.tm
.base_opcode
== 0xfbf))
1944 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1946 /* Check that the template allows eight bit regs
1947 This kills insns such as `orb $1,%edx', which
1948 maybe should be allowed. */
1949 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1953 /* Prohibit these changes in the 64bit mode, since
1954 the lowering is more complicated. */
1955 if (flag_code
== CODE_64BIT
1956 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1957 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1958 i
.op
[op
].regs
->reg_name
,
1960 #if REGISTER_WARNINGS
1962 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1963 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1964 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1965 i
.op
[op
].regs
->reg_name
,
1970 /* Any other register is bad. */
1971 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1973 | Control
| Debug
| Test
1974 | FloatReg
| FloatAcc
))
1976 as_bad (_("`%%%s' not allowed with `%s%c'"),
1977 i
.op
[op
].regs
->reg_name
,
1984 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1988 for (op
= i
.operands
; --op
>= 0;)
1989 /* Reject eight bit registers, except where the template
1990 requires them. (eg. movzb) */
1991 if ((i
.types
[op
] & Reg8
) != 0
1992 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1994 as_bad (_("`%%%s' not allowed with `%s%c'"),
1995 i
.op
[op
].regs
->reg_name
,
2000 /* Warn if the e prefix on a general reg is missing. */
2001 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2002 && (i
.types
[op
] & Reg16
) != 0
2003 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2005 /* Prohibit these changes in the 64bit mode, since
2006 the lowering is more complicated. */
2007 if (flag_code
== CODE_64BIT
)
2008 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2009 i
.op
[op
].regs
->reg_name
,
2011 #if REGISTER_WARNINGS
2013 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2014 (i
.op
[op
].regs
+ 8)->reg_name
,
2015 i
.op
[op
].regs
->reg_name
,
2019 /* Warn if the r prefix on a general reg is missing. */
2020 else if ((i
.types
[op
] & Reg64
) != 0
2021 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2023 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2024 i
.op
[op
].regs
->reg_name
,
2028 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2032 for (op
= i
.operands
; --op
>= 0; )
2033 /* Reject eight bit registers, except where the template
2034 requires them. (eg. movzb) */
2035 if ((i
.types
[op
] & Reg8
) != 0
2036 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2038 as_bad (_("`%%%s' not allowed with `%s%c'"),
2039 i
.op
[op
].regs
->reg_name
,
2044 /* Warn if the e prefix on a general reg is missing. */
2045 else if (((i
.types
[op
] & Reg16
) != 0
2046 || (i
.types
[op
] & Reg32
) != 0)
2047 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2049 /* Prohibit these changes in the 64bit mode, since
2050 the lowering is more complicated. */
2051 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2052 i
.op
[op
].regs
->reg_name
,
2056 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2059 for (op
= i
.operands
; --op
>= 0;)
2060 /* Reject eight bit registers, except where the template
2061 requires them. (eg. movzb) */
2062 if ((i
.types
[op
] & Reg8
) != 0
2063 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2065 as_bad (_("`%%%s' not allowed with `%s%c'"),
2066 i
.op
[op
].regs
->reg_name
,
2071 /* Warn if the e prefix on a general reg is present. */
2072 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2073 && (i
.types
[op
] & Reg32
) != 0
2074 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2076 /* Prohibit these changes in the 64bit mode, since
2077 the lowering is more complicated. */
2078 if (flag_code
== CODE_64BIT
)
2079 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2080 i
.op
[op
].regs
->reg_name
,
2083 #if REGISTER_WARNINGS
2084 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2085 (i
.op
[op
].regs
- 8)->reg_name
,
2086 i
.op
[op
].regs
->reg_name
,
2091 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2092 /* Do nothing if the instruction is going to ignore the prefix. */
2097 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2099 i
.suffix
= stackop_size
;
2101 /* Make still unresolved immediate matches conform to size of immediate
2102 given in i.suffix. Note: overlap2 cannot be an immediate! */
2103 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2104 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2105 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2106 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2110 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2111 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2112 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2114 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2115 || overlap0
== (Imm16
| Imm32
)
2116 || overlap0
== (Imm16
| Imm32S
))
2119 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2121 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2122 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2123 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2125 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2129 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2130 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2131 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2132 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2136 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2137 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2138 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2140 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2141 || overlap1
== (Imm16
| Imm32
)
2142 || overlap1
== (Imm16
| Imm32S
))
2145 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2147 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2148 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2149 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2151 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2155 assert ((overlap2
& Imm
) == 0);
2157 i
.types
[0] = overlap0
;
2158 if (overlap0
& ImplicitRegister
)
2160 if (overlap0
& Imm1
)
2161 i
.imm_operands
= 0; /* kludge for shift insns. */
2163 i
.types
[1] = overlap1
;
2164 if (overlap1
& ImplicitRegister
)
2167 i
.types
[2] = overlap2
;
2168 if (overlap2
& ImplicitRegister
)
2171 /* Finalize opcode. First, we change the opcode based on the operand
2172 size given by i.suffix: We need not change things for byte insns. */
2174 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2176 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2180 /* For movzx and movsx, need to check the register type. */
2182 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2183 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2185 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2187 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2188 if (!add_prefix (prefix
))
2192 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2194 /* It's not a byte, select word/dword operation. */
2195 if (i
.tm
.opcode_modifier
& W
)
2197 if (i
.tm
.opcode_modifier
& ShortForm
)
2198 i
.tm
.base_opcode
|= 8;
2200 i
.tm
.base_opcode
|= 1;
2202 /* Now select between word & dword operations via the operand
2203 size prefix, except for instructions that will ignore this
2205 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2206 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2207 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2209 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2210 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2211 prefix
= ADDR_PREFIX_OPCODE
;
2213 if (! add_prefix (prefix
))
2217 /* Set mode64 for an operand. */
2218 if (i
.suffix
== QWORD_MNEM_SUFFIX
2219 && !(i
.tm
.opcode_modifier
& NoRex64
))
2222 if (flag_code
< CODE_64BIT
)
2224 as_bad (_("64bit operations available only in 64bit modes."));
2229 /* Size floating point instruction. */
2230 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2232 if (i
.tm
.opcode_modifier
& FloatMF
)
2233 i
.tm
.base_opcode
^= 4;
2237 if (i
.tm
.opcode_modifier
& ImmExt
)
2239 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2240 opcode suffix which is coded in the same place as an 8-bit
2241 immediate field would be. Here we fake an 8-bit immediate
2242 operand from the opcode suffix stored in tm.extension_opcode. */
2246 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2248 exp
= &im_expressions
[i
.imm_operands
++];
2249 i
.op
[i
.operands
].imms
= exp
;
2250 i
.types
[i
.operands
++] = Imm8
;
2251 exp
->X_op
= O_constant
;
2252 exp
->X_add_number
= i
.tm
.extension_opcode
;
2253 i
.tm
.extension_opcode
= None
;
2256 /* For insns with operands there are more diddles to do to the opcode. */
2259 /* Default segment register this instruction will use
2260 for memory accesses. 0 means unknown.
2261 This is only for optimizing out unnecessary segment overrides. */
2262 const seg_entry
*default_seg
= 0;
2264 /* The imul $imm, %reg instruction is converted into
2265 imul $imm, %reg, %reg, and the clr %reg instruction
2266 is converted into xor %reg, %reg. */
2267 if (i
.tm
.opcode_modifier
& regKludge
)
2269 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2270 /* Pretend we saw the extra register operand. */
2271 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2272 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2273 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2277 if (i
.tm
.opcode_modifier
& ShortForm
)
2279 /* The register or float register operand is in operand 0 or 1. */
2280 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2281 /* Register goes in low 3 bits of opcode. */
2282 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2283 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2285 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2287 /* Warn about some common errors, but press on regardless.
2288 The first case can be generated by gcc (<= 2.8.1). */
2289 if (i
.operands
== 2)
2291 /* Reversed arguments on faddp, fsubp, etc. */
2292 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2293 i
.op
[1].regs
->reg_name
,
2294 i
.op
[0].regs
->reg_name
);
2298 /* Extraneous `l' suffix on fp insn. */
2299 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2300 i
.op
[0].regs
->reg_name
);
2304 else if (i
.tm
.opcode_modifier
& Modrm
)
2306 /* The opcode is completed (modulo i.tm.extension_opcode which
2307 must be put into the modrm byte).
2308 Now, we make the modrm & index base bytes based on all the
2309 info we've collected. */
2311 /* i.reg_operands MUST be the number of real register operands;
2312 implicit registers do not count. */
2313 if (i
.reg_operands
== 2)
2315 unsigned int source
, dest
;
2316 source
= ((i
.types
[0]
2317 & (Reg
| RegMMX
| RegXMM
2319 | Control
| Debug
| Test
))
2324 /* One of the register operands will be encoded in the
2325 i.tm.reg field, the other in the combined i.tm.mode
2326 and i.tm.regmem fields. If no form of this
2327 instruction supports a memory destination operand,
2328 then we assume the source operand may sometimes be
2329 a memory operand and so we need to store the
2330 destination in the i.rm.reg field. */
2331 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2333 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2334 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2335 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2337 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2342 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2343 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2344 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2346 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2351 { /* If it's not 2 reg operands... */
2354 unsigned int fake_zero_displacement
= 0;
2355 unsigned int op
= ((i
.types
[0] & AnyMem
)
2357 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2364 if (! i
.disp_operands
)
2365 fake_zero_displacement
= 1;
2368 /* Operand is just <disp> */
2369 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2371 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2372 i
.types
[op
] &= ~Disp
;
2373 i
.types
[op
] |= Disp16
;
2375 else if (flag_code
!= CODE_64BIT
)
2377 i
.rm
.regmem
= NO_BASE_REGISTER
;
2378 i
.types
[op
] &= ~Disp
;
2379 i
.types
[op
] |= Disp32
;
2383 /* 64bit mode overwrites the 32bit
2384 absolute addressing by RIP relative
2385 addressing and absolute addressing
2386 is encoded by one of the redundant
2389 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2390 i
.sib
.base
= NO_BASE_REGISTER
;
2391 i
.sib
.index
= NO_INDEX_REGISTER
;
2392 i
.types
[op
] &= ~Disp
;
2393 i
.types
[op
] |= Disp32S
;
2396 else /* ! i.base_reg && i.index_reg */
2398 i
.sib
.index
= i
.index_reg
->reg_num
;
2399 i
.sib
.base
= NO_BASE_REGISTER
;
2400 i
.sib
.scale
= i
.log2_scale_factor
;
2401 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2402 i
.types
[op
] &= ~Disp
;
2403 if (flag_code
!= CODE_64BIT
)
2404 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2406 i
.types
[op
] |= Disp32S
;
2407 if (i
.index_reg
->reg_flags
& RegRex
)
2411 /* RIP addressing for 64bit mode. */
2412 else if (i
.base_reg
->reg_type
== BaseIndex
)
2414 i
.rm
.regmem
= NO_BASE_REGISTER
;
2415 i
.types
[op
] &= ~Disp
;
2416 i
.types
[op
] |= Disp32S
;
2417 i
.flags
[op
] = Operand_PCrel
;
2419 else if (i
.base_reg
->reg_type
& Reg16
)
2421 switch (i
.base_reg
->reg_num
)
2426 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2427 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2434 if ((i
.types
[op
] & Disp
) == 0)
2436 /* fake (%bp) into 0(%bp) */
2437 i
.types
[op
] |= Disp8
;
2438 fake_zero_displacement
= 1;
2441 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2442 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2444 default: /* (%si) -> 4 or (%di) -> 5 */
2445 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2447 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2449 else /* i.base_reg and 32/64 bit mode */
2451 if (flag_code
== CODE_64BIT
2452 && (i
.types
[op
] & Disp
))
2454 if (i
.types
[op
] & Disp8
)
2455 i
.types
[op
] = Disp8
| Disp32S
;
2457 i
.types
[op
] = Disp32S
;
2459 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2460 if (i
.base_reg
->reg_flags
& RegRex
)
2462 i
.sib
.base
= i
.base_reg
->reg_num
;
2463 /* x86-64 ignores REX prefix bit here to avoid
2464 decoder complications. */
2465 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2468 if (i
.disp_operands
== 0)
2470 fake_zero_displacement
= 1;
2471 i
.types
[op
] |= Disp8
;
2474 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2478 i
.sib
.scale
= i
.log2_scale_factor
;
2481 /* <disp>(%esp) becomes two byte modrm
2482 with no index register. We've already
2483 stored the code for esp in i.rm.regmem
2484 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2485 base register besides %esp will not use
2486 the extra modrm byte. */
2487 i
.sib
.index
= NO_INDEX_REGISTER
;
2488 #if ! SCALE1_WHEN_NO_INDEX
2489 /* Another case where we force the second
2491 if (i
.log2_scale_factor
)
2492 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2497 i
.sib
.index
= i
.index_reg
->reg_num
;
2498 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2499 if (i
.index_reg
->reg_flags
& RegRex
)
2502 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2505 if (fake_zero_displacement
)
2507 /* Fakes a zero displacement assuming that i.types[op]
2508 holds the correct displacement size. */
2511 assert (i
.op
[op
].disps
== 0);
2512 exp
= &disp_expressions
[i
.disp_operands
++];
2513 i
.op
[op
].disps
= exp
;
2514 exp
->X_op
= O_constant
;
2515 exp
->X_add_number
= 0;
2516 exp
->X_add_symbol
= (symbolS
*) 0;
2517 exp
->X_op_symbol
= (symbolS
*) 0;
2521 /* Fill in i.rm.reg or i.rm.regmem field with register
2522 operand (if any) based on i.tm.extension_opcode.
2523 Again, we must be careful to make sure that
2524 segment/control/debug/test/MMX registers are coded
2525 into the i.rm.reg field. */
2530 & (Reg
| RegMMX
| RegXMM
2532 | Control
| Debug
| Test
))
2535 & (Reg
| RegMMX
| RegXMM
2537 | Control
| Debug
| Test
))
2540 /* If there is an extension opcode to put here, the
2541 register number must be put into the regmem field. */
2542 if (i
.tm
.extension_opcode
!= None
)
2544 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2545 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2550 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2551 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2555 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2556 we must set it to 3 to indicate this is a register
2557 operand in the regmem field. */
2558 if (!i
.mem_operands
)
2562 /* Fill in i.rm.reg field with extension opcode (if any). */
2563 if (i
.tm
.extension_opcode
!= None
)
2564 i
.rm
.reg
= i
.tm
.extension_opcode
;
2567 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2569 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2570 && i
.op
[0].regs
->reg_num
== 1)
2572 as_bad (_("you can't `pop %%cs'"));
2575 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2576 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2579 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2583 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2585 /* For the string instructions that allow a segment override
2586 on one of their operands, the default segment is ds. */
2590 /* If a segment was explicitly specified,
2591 and the specified segment is not the default,
2592 use an opcode prefix to select it.
2593 If we never figured out what the default segment is,
2594 then default_seg will be zero at this point,
2595 and the specified segment prefix will always be used. */
2596 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2598 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2602 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2604 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2605 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2609 /* Handle conversion of 'int $3' --> special int3 insn. */
2610 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2612 i
.tm
.base_opcode
= INT3_OPCODE
;
2616 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2617 && i
.op
[0].disps
->X_op
== O_constant
)
2619 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2620 the absolute address given by the constant. Since ix86 jumps and
2621 calls are pc relative, we need to generate a reloc. */
2622 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2623 i
.op
[0].disps
->X_op
= O_symbol
;
2626 if (i
.tm
.opcode_modifier
& Rex64
)
2629 /* For 8bit registers we would need an empty rex prefix.
2630 Also in the case instruction is already having prefix,
2631 we need to convert old registers to new ones. */
2633 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2634 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2635 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2636 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2640 for (x
= 0; x
< 2; x
++)
2642 /* Look for 8bit operand that does use old registers. */
2643 if (i
.types
[x
] & Reg8
2644 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2646 /* In case it is "hi" register, give up. */
2647 if (i
.op
[x
].regs
->reg_num
> 3)
2648 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2649 i
.op
[x
].regs
->reg_name
);
2651 /* Otherwise it is equivalent to the extended register.
2652 Since the encoding don't change this is merely cosmetical
2653 cleanup for debug output. */
2655 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2660 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2662 | (i
.rex
.mode64
? 8 : 0)
2663 | (i
.rex
.extX
? 4 : 0)
2664 | (i
.rex
.extY
? 2 : 0)
2665 | (i
.rex
.extZ
? 1 : 0));
2667 /* We are ready to output the insn. */
2672 if (i
.tm
.opcode_modifier
& Jump
)
2679 if (flag_code
== CODE_16BIT
)
2683 if (i
.prefix
[DATA_PREFIX
])
2689 if (i
.prefix
[REX_PREFIX
])
2699 if (i
.prefixes
!= 0 && !intel_syntax
)
2700 as_warn (_("skipping prefixes on this instruction"));
2702 /* It's always a symbol; End frag & setup for relax.
2703 Make sure there is enough room in this frag for the largest
2704 instruction we may generate in md_convert_frag. This is 2
2705 bytes for the opcode and room for the prefix and largest
2707 frag_grow (prefix
+ 2 + size
);
2708 insn_size
+= prefix
+ 1;
2709 /* Prefix and 1 opcode byte go in fr_fix. */
2710 p
= frag_more (prefix
+ 1);
2711 if (i
.prefix
[DATA_PREFIX
])
2712 *p
++ = DATA_PREFIX_OPCODE
;
2713 if (i
.prefix
[REX_PREFIX
])
2714 *p
++ = i
.prefix
[REX_PREFIX
];
2715 *p
= i
.tm
.base_opcode
;
2716 /* 1 possible extra opcode + displacement go in var part.
2717 Pass reloc in fr_var. */
2718 frag_var (rs_machine_dependent
,
2721 ((unsigned char) *p
== JUMP_PC_RELATIVE
2722 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2723 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2724 i
.op
[0].disps
->X_add_symbol
,
2725 i
.op
[0].disps
->X_add_number
,
2728 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2732 if (i
.tm
.opcode_modifier
& JumpByte
)
2734 /* This is a loop or jecxz type instruction. */
2736 if (i
.prefix
[ADDR_PREFIX
])
2739 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2748 if (flag_code
== CODE_16BIT
)
2751 if (i
.prefix
[DATA_PREFIX
])
2754 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2764 if (i
.prefix
[REX_PREFIX
])
2766 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2771 if (i
.prefixes
!= 0 && !intel_syntax
)
2772 as_warn (_("skipping prefixes on this instruction"));
2774 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2776 insn_size
+= 1 + size
;
2777 p
= frag_more (1 + size
);
2781 /* Opcode can be at most two bytes. */
2782 insn_size
+= 2 + size
;
2783 p
= frag_more (2 + size
);
2784 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2786 *p
++ = i
.tm
.base_opcode
& 0xff;
2788 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2789 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2791 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2798 if (flag_code
== CODE_16BIT
)
2802 if (i
.prefix
[DATA_PREFIX
])
2808 if (i
.prefix
[REX_PREFIX
])
2818 if (i
.prefixes
!= 0 && !intel_syntax
)
2819 as_warn (_("skipping prefixes on this instruction"));
2821 /* 1 opcode; 2 segment; offset */
2822 insn_size
+= prefix
+ 1 + 2 + size
;
2823 p
= frag_more (prefix
+ 1 + 2 + size
);
2825 if (i
.prefix
[DATA_PREFIX
])
2826 *p
++ = DATA_PREFIX_OPCODE
;
2828 if (i
.prefix
[REX_PREFIX
])
2829 *p
++ = i
.prefix
[REX_PREFIX
];
2831 *p
++ = i
.tm
.base_opcode
;
2832 if (i
.op
[1].imms
->X_op
== O_constant
)
2834 offsetT n
= i
.op
[1].imms
->X_add_number
;
2837 && !fits_in_unsigned_word (n
)
2838 && !fits_in_signed_word (n
))
2840 as_bad (_("16-bit jump out of range"));
2843 md_number_to_chars (p
, n
, size
);
2846 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2847 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2848 if (i
.op
[0].imms
->X_op
!= O_constant
)
2849 as_bad (_("can't handle non absolute segment in `%s'"),
2851 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2855 /* Output normal instructions here. */
2858 /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third
2859 byte for the SSE instructions to specify prefix they require. */
2860 if (i
.tm
.base_opcode
& 0xff0000)
2861 add_prefix ((i
.tm
.base_opcode
>> 16) & 0xff);
2863 /* The prefix bytes. */
2865 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2872 md_number_to_chars (p
, (valueT
) *q
, 1);
2876 /* Now the opcode; be careful about word order here! */
2877 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2880 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2886 /* Put out high byte first: can't use md_number_to_chars! */
2887 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2888 *p
= i
.tm
.base_opcode
& 0xff;
2891 /* Now the modrm byte and sib byte (if present). */
2892 if (i
.tm
.opcode_modifier
& Modrm
)
2896 md_number_to_chars (p
,
2897 (valueT
) (i
.rm
.regmem
<< 0
2901 /* If i.rm.regmem == ESP (4)
2902 && i.rm.mode != (Register mode)
2904 ==> need second modrm byte. */
2905 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2907 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2911 md_number_to_chars (p
,
2912 (valueT
) (i
.sib
.base
<< 0
2914 | i
.sib
.scale
<< 6),
2919 if (i
.disp_operands
)
2921 register unsigned int n
;
2923 for (n
= 0; n
< i
.operands
; n
++)
2925 if (i
.types
[n
] & Disp
)
2927 if (i
.op
[n
].disps
->X_op
== O_constant
)
2933 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2936 if (i
.types
[n
] & Disp8
)
2938 if (i
.types
[n
] & Disp64
)
2941 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2944 p
= frag_more (size
);
2945 md_number_to_chars (p
, val
, size
);
2951 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2953 /* The PC relative address is computed relative
2954 to the instruction boundary, so in case immediate
2955 fields follows, we need to adjust the value. */
2956 if (pcrel
&& i
.imm_operands
)
2959 register unsigned int n1
;
2961 for (n1
= 0; n1
< i
.operands
; n1
++)
2962 if (i
.types
[n1
] & Imm
)
2964 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2967 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2969 if (i
.types
[n1
] & Imm64
)
2974 /* We should find the immediate. */
2975 if (n1
== i
.operands
)
2977 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2980 if (i
.types
[n
] & Disp32S
)
2983 if (i
.types
[n
] & (Disp16
| Disp64
))
2986 if (i
.types
[n
] & Disp64
)
2991 p
= frag_more (size
);
2992 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2993 i
.op
[n
].disps
, pcrel
,
2994 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
3000 /* Output immediate. */
3003 register unsigned int n
;
3005 for (n
= 0; n
< i
.operands
; n
++)
3007 if (i
.types
[n
] & Imm
)
3009 if (i
.op
[n
].imms
->X_op
== O_constant
)
3015 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3018 if (i
.types
[n
] & (Imm8
| Imm8S
))
3020 else if (i
.types
[n
] & Imm64
)
3023 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3026 p
= frag_more (size
);
3027 md_number_to_chars (p
, val
, size
);
3031 /* Not absolute_section.
3032 Need a 32-bit fixup (don't support 8bit
3033 non-absolute imms). Try to support other
3035 #ifdef BFD_ASSEMBLER
3036 enum bfd_reloc_code_real reloc_type
;
3043 if ((i
.types
[n
] & (Imm32S
))
3044 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3046 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3049 if (i
.types
[n
] & (Imm8
| Imm8S
))
3051 if (i
.types
[n
] & Imm64
)
3056 p
= frag_more (size
);
3057 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3058 #ifdef BFD_ASSEMBLER
3059 if (reloc_type
== BFD_RELOC_32
3061 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3062 && (i
.op
[n
].imms
->X_op
== O_symbol
3063 || (i
.op
[n
].imms
->X_op
== O_add
3064 && ((symbol_get_value_expression
3065 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3068 /* We don't support dynamic linking on x86-64 yet. */
3069 if (flag_code
== CODE_64BIT
)
3071 reloc_type
= BFD_RELOC_386_GOTPC
;
3072 i
.op
[n
].imms
->X_add_number
+= 3;
3075 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3076 i
.op
[n
].imms
, 0, reloc_type
);
3083 dwarf2_emit_insn (insn_size
);
3090 #endif /* DEBUG386 */
3094 static int i386_immediate
PARAMS ((char *));
3097 i386_immediate (imm_start
)
3100 char *save_input_line_pointer
;
3104 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3106 as_bad (_("only 1 or 2 immediate operands are allowed"));
3110 exp
= &im_expressions
[i
.imm_operands
++];
3111 i
.op
[this_operand
].imms
= exp
;
3113 if (is_space_char (*imm_start
))
3116 save_input_line_pointer
= input_line_pointer
;
3117 input_line_pointer
= imm_start
;
3121 /* We can have operands of the form
3122 <symbol>@GOTOFF+<nnn>
3123 Take the easy way out here and copy everything
3124 into a temporary buffer... */
3127 cp
= strchr (input_line_pointer
, '@');
3134 /* GOT relocations are not supported in 16 bit mode. */
3135 if (flag_code
== CODE_16BIT
)
3136 as_bad (_("GOT relocations not supported in 16 bit mode"));
3138 if (GOT_symbol
== NULL
)
3139 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3141 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3143 if (flag_code
== CODE_64BIT
)
3144 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3146 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3149 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3151 if (flag_code
== CODE_64BIT
)
3152 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3153 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3156 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3158 if (flag_code
== CODE_64BIT
)
3159 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3161 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3164 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3166 if (flag_code
== CODE_64BIT
)
3167 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3169 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3173 as_bad (_("bad reloc specifier in expression"));
3175 /* Replace the relocation token with ' ', so that errors like
3176 foo@GOTOFF1 will be detected. */
3177 first
= cp
- input_line_pointer
;
3178 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3179 memcpy (tmpbuf
, input_line_pointer
, first
);
3180 tmpbuf
[first
] = ' ';
3181 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3182 input_line_pointer
= tmpbuf
;
3187 exp_seg
= expression (exp
);
3190 if (*input_line_pointer
)
3191 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3193 input_line_pointer
= save_input_line_pointer
;
3195 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3197 /* Missing or bad expr becomes absolute 0. */
3198 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3200 exp
->X_op
= O_constant
;
3201 exp
->X_add_number
= 0;
3202 exp
->X_add_symbol
= (symbolS
*) 0;
3203 exp
->X_op_symbol
= (symbolS
*) 0;
3205 else if (exp
->X_op
== O_constant
)
3207 /* Size it properly later. */
3208 i
.types
[this_operand
] |= Imm64
;
3209 /* If BFD64, sign extend val. */
3210 if (!use_rela_relocations
)
3211 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3212 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3214 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3216 #ifdef BFD_ASSEMBLER
3217 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3219 && exp_seg
!= text_section
3220 && exp_seg
!= data_section
3221 && exp_seg
!= bss_section
3222 && exp_seg
!= undefined_section
3223 #ifdef BFD_ASSEMBLER
3224 && !bfd_is_com_section (exp_seg
)
3228 #ifdef BFD_ASSEMBLER
3229 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3231 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3238 /* This is an address. The size of the address will be
3239 determined later, depending on destination register,
3240 suffix, or the default for the section. */
3241 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3247 static int i386_scale
PARAMS ((char *));
3253 if (!isdigit (*scale
))
3260 i
.log2_scale_factor
= 0;
3263 i
.log2_scale_factor
= 1;
3266 i
.log2_scale_factor
= 2;
3269 i
.log2_scale_factor
= 3;
3273 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3277 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3279 as_warn (_("scale factor of %d without an index register"),
3280 1 << i
.log2_scale_factor
);
3281 #if SCALE1_WHEN_NO_INDEX
3282 i
.log2_scale_factor
= 0;
3288 static int i386_displacement
PARAMS ((char *, char *));
3291 i386_displacement (disp_start
, disp_end
)
3295 register expressionS
*exp
;
3297 char *save_input_line_pointer
;
3298 int bigdisp
= Disp32
;
3300 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3302 if (flag_code
== CODE_64BIT
)
3304 i
.types
[this_operand
] |= bigdisp
;
3306 exp
= &disp_expressions
[i
.disp_operands
];
3307 i
.op
[this_operand
].disps
= exp
;
3309 save_input_line_pointer
= input_line_pointer
;
3310 input_line_pointer
= disp_start
;
3311 END_STRING_AND_SAVE (disp_end
);
3313 #ifndef GCC_ASM_O_HACK
3314 #define GCC_ASM_O_HACK 0
3317 END_STRING_AND_SAVE (disp_end
+ 1);
3318 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3319 && displacement_string_end
[-1] == '+')
3321 /* This hack is to avoid a warning when using the "o"
3322 constraint within gcc asm statements.
3325 #define _set_tssldt_desc(n,addr,limit,type) \
3326 __asm__ __volatile__ ( \
3328 "movw %w1,2+%0\n\t" \
3330 "movb %b1,4+%0\n\t" \
3331 "movb %4,5+%0\n\t" \
3332 "movb $0,6+%0\n\t" \
3333 "movb %h1,7+%0\n\t" \
3335 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3337 This works great except that the output assembler ends
3338 up looking a bit weird if it turns out that there is
3339 no offset. You end up producing code that looks like:
3352 So here we provide the missing zero. */
3354 *displacement_string_end
= '0';
3359 /* We can have operands of the form
3360 <symbol>@GOTOFF+<nnn>
3361 Take the easy way out here and copy everything
3362 into a temporary buffer... */
3365 cp
= strchr (input_line_pointer
, '@');
3372 /* GOT relocations are not supported in 16 bit mode. */
3373 if (flag_code
== CODE_16BIT
)
3374 as_bad (_("GOT relocations not supported in 16 bit mode"));
3376 if (GOT_symbol
== NULL
)
3377 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3379 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3381 if (flag_code
== CODE_64BIT
)
3382 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3384 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3387 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3389 if (flag_code
== CODE_64BIT
)
3390 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3391 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3394 else if (strncmp (cp
+ 1, "GOTPCREL", 8) == 0)
3396 if (flag_code
!= CODE_64BIT
)
3397 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3398 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3401 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3403 if (flag_code
== CODE_64BIT
)
3404 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3406 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3410 as_bad (_("bad reloc specifier in expression"));
3412 /* Replace the relocation token with ' ', so that errors like
3413 foo@GOTOFF1 will be detected. */
3414 first
= cp
- input_line_pointer
;
3415 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3416 memcpy (tmpbuf
, input_line_pointer
, first
);
3417 tmpbuf
[first
] = ' ';
3418 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3419 input_line_pointer
= tmpbuf
;
3424 exp_seg
= expression (exp
);
3426 #ifdef BFD_ASSEMBLER
3427 /* We do this to make sure that the section symbol is in
3428 the symbol table. We will ultimately change the relocation
3429 to be relative to the beginning of the section. */
3430 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3431 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3433 if (S_IS_LOCAL (exp
->X_add_symbol
)
3434 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3435 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3436 assert (exp
->X_op
== O_symbol
);
3437 exp
->X_op
= O_subtract
;
3438 exp
->X_op_symbol
= GOT_symbol
;
3439 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3444 if (*input_line_pointer
)
3445 as_bad (_("ignoring junk `%s' after expression"),
3446 input_line_pointer
);
3448 RESTORE_END_STRING (disp_end
+ 1);
3450 RESTORE_END_STRING (disp_end
);
3451 input_line_pointer
= save_input_line_pointer
;
3453 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3455 /* Missing or bad expr becomes absolute 0. */
3456 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3458 exp
->X_op
= O_constant
;
3459 exp
->X_add_number
= 0;
3460 exp
->X_add_symbol
= (symbolS
*) 0;
3461 exp
->X_op_symbol
= (symbolS
*) 0;
3464 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3465 if (exp
->X_op
!= O_constant
3466 #ifdef BFD_ASSEMBLER
3467 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3469 && exp_seg
!= text_section
3470 && exp_seg
!= data_section
3471 && exp_seg
!= bss_section
3472 && exp_seg
!= undefined_section
)
3474 #ifdef BFD_ASSEMBLER
3475 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3477 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3482 else if (flag_code
== CODE_64BIT
)
3483 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3487 static int i386_index_check
PARAMS ((const char *));
3489 /* Make sure the memory operand we've been dealt is valid.
3490 Return 1 on success, 0 on a failure. */
3493 i386_index_check (operand_string
)
3494 const char *operand_string
;
3497 #if INFER_ADDR_PREFIX
3503 if (flag_code
== CODE_64BIT
)
3507 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3508 && (i
.base_reg
->reg_type
!= BaseIndex
3511 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3512 != (Reg64
|BaseIndex
))))
3517 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3521 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3522 != (Reg16
|BaseIndex
)))
3524 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3525 != (Reg16
|BaseIndex
))
3527 && i
.base_reg
->reg_num
< 6
3528 && i
.index_reg
->reg_num
>= 6
3529 && i
.log2_scale_factor
== 0))))
3536 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3538 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3539 != (Reg32
|BaseIndex
))))
3545 #if INFER_ADDR_PREFIX
3546 if (flag_code
!= CODE_64BIT
3547 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3549 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3551 /* Change the size of any displacement too. At most one of
3552 Disp16 or Disp32 is set.
3553 FIXME. There doesn't seem to be any real need for separate
3554 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3555 Removing them would probably clean up the code quite a lot. */
3556 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3557 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3562 as_bad (_("`%s' is not a valid base/index expression"),
3566 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3568 flag_code_names
[flag_code
]);
3574 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3578 i386_operand (operand_string
)
3579 char *operand_string
;
3583 char *op_string
= operand_string
;
3585 if (is_space_char (*op_string
))
3588 /* We check for an absolute prefix (differentiating,
3589 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3590 if (*op_string
== ABSOLUTE_PREFIX
)
3593 if (is_space_char (*op_string
))
3595 i
.types
[this_operand
] |= JumpAbsolute
;
3598 /* Check if operand is a register. */
3599 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3600 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3602 /* Check for a segment override by searching for ':' after a
3603 segment register. */
3605 if (is_space_char (*op_string
))
3607 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3612 i
.seg
[i
.mem_operands
] = &es
;
3615 i
.seg
[i
.mem_operands
] = &cs
;
3618 i
.seg
[i
.mem_operands
] = &ss
;
3621 i
.seg
[i
.mem_operands
] = &ds
;
3624 i
.seg
[i
.mem_operands
] = &fs
;
3627 i
.seg
[i
.mem_operands
] = &gs
;
3631 /* Skip the ':' and whitespace. */
3633 if (is_space_char (*op_string
))
3636 if (!is_digit_char (*op_string
)
3637 && !is_identifier_char (*op_string
)
3638 && *op_string
!= '('
3639 && *op_string
!= ABSOLUTE_PREFIX
)
3641 as_bad (_("bad memory operand `%s'"), op_string
);
3644 /* Handle case of %es:*foo. */
3645 if (*op_string
== ABSOLUTE_PREFIX
)
3648 if (is_space_char (*op_string
))
3650 i
.types
[this_operand
] |= JumpAbsolute
;
3652 goto do_memory_reference
;
3656 as_bad (_("junk `%s' after register"), op_string
);
3659 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3660 i
.op
[this_operand
].regs
= r
;
3663 else if (*op_string
== REGISTER_PREFIX
)
3665 as_bad (_("bad register name `%s'"), op_string
);
3668 else if (*op_string
== IMMEDIATE_PREFIX
)
3671 if (i
.types
[this_operand
] & JumpAbsolute
)
3673 as_bad (_("immediate operand illegal with absolute jump"));
3676 if (!i386_immediate (op_string
))
3679 else if (is_digit_char (*op_string
)
3680 || is_identifier_char (*op_string
)
3681 || *op_string
== '(')
3683 /* This is a memory reference of some sort. */
3686 /* Start and end of displacement string expression (if found). */
3687 char *displacement_string_start
;
3688 char *displacement_string_end
;
3690 do_memory_reference
:
3691 if ((i
.mem_operands
== 1
3692 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3693 || i
.mem_operands
== 2)
3695 as_bad (_("too many memory references for `%s'"),
3696 current_templates
->start
->name
);
3700 /* Check for base index form. We detect the base index form by
3701 looking for an ')' at the end of the operand, searching
3702 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3704 base_string
= op_string
+ strlen (op_string
);
3707 if (is_space_char (*base_string
))
3710 /* If we only have a displacement, set-up for it to be parsed later. */
3711 displacement_string_start
= op_string
;
3712 displacement_string_end
= base_string
+ 1;
3714 if (*base_string
== ')')
3717 unsigned int parens_balanced
= 1;
3718 /* We've already checked that the number of left & right ()'s are
3719 equal, so this loop will not be infinite. */
3723 if (*base_string
== ')')
3725 if (*base_string
== '(')
3728 while (parens_balanced
);
3730 temp_string
= base_string
;
3732 /* Skip past '(' and whitespace. */
3734 if (is_space_char (*base_string
))
3737 if (*base_string
== ','
3738 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3739 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3741 displacement_string_end
= temp_string
;
3743 i
.types
[this_operand
] |= BaseIndex
;
3747 base_string
= end_op
;
3748 if (is_space_char (*base_string
))
3752 /* There may be an index reg or scale factor here. */
3753 if (*base_string
== ',')
3756 if (is_space_char (*base_string
))
3759 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3760 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3762 base_string
= end_op
;
3763 if (is_space_char (*base_string
))
3765 if (*base_string
== ',')
3768 if (is_space_char (*base_string
))
3771 else if (*base_string
!= ')')
3773 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3778 else if (*base_string
== REGISTER_PREFIX
)
3780 as_bad (_("bad register name `%s'"), base_string
);
3784 /* Check for scale factor. */
3785 if (isdigit ((unsigned char) *base_string
))
3787 if (!i386_scale (base_string
))
3791 if (is_space_char (*base_string
))
3793 if (*base_string
!= ')')
3795 as_bad (_("expecting `)' after scale factor in `%s'"),
3800 else if (!i
.index_reg
)
3802 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3807 else if (*base_string
!= ')')
3809 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3814 else if (*base_string
== REGISTER_PREFIX
)
3816 as_bad (_("bad register name `%s'"), base_string
);
3821 /* If there's an expression beginning the operand, parse it,
3822 assuming displacement_string_start and
3823 displacement_string_end are meaningful. */
3824 if (displacement_string_start
!= displacement_string_end
)
3826 if (!i386_displacement (displacement_string_start
,
3827 displacement_string_end
))
3831 /* Special case for (%dx) while doing input/output op. */
3833 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3835 && i
.log2_scale_factor
== 0
3836 && i
.seg
[i
.mem_operands
] == 0
3837 && (i
.types
[this_operand
] & Disp
) == 0)
3839 i
.types
[this_operand
] = InOutPortReg
;
3843 if (i386_index_check (operand_string
) == 0)
3849 /* It's not a memory operand; argh! */
3850 as_bad (_("invalid char %s beginning operand %d `%s'"),
3851 output_invalid (*op_string
),
3856 return 1; /* Normal return. */
3859 /* md_estimate_size_before_relax()
3861 Called just before relax() for rs_machine_dependent frags. The x86
3862 assembler uses these frags to handle variable size jump
3865 Any symbol that is now undefined will not become defined.
3866 Return the correct fr_subtype in the frag.
3867 Return the initial "guess for variable size of frag" to caller.
3868 The guess is actually the growth beyond the fixed part. Whatever
3869 we do to grow the fixed or variable part contributes to our
3873 md_estimate_size_before_relax (fragP
, segment
)
3874 register fragS
*fragP
;
3875 register segT segment
;
3877 /* We've already got fragP->fr_subtype right; all we have to do is
3878 check for un-relaxable symbols. On an ELF system, we can't relax
3879 an externally visible symbol, because it may be overridden by a
3881 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3882 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3883 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3884 || S_IS_WEAK (fragP
->fr_symbol
)
3888 /* Symbol is undefined in this segment, or we need to keep a
3889 reloc so that weak symbols can be overridden. */
3890 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3891 #ifdef BFD_ASSEMBLER
3892 enum bfd_reloc_code_real reloc_type
;
3896 unsigned char *opcode
;
3899 if (fragP
->fr_var
!= NO_RELOC
)
3900 reloc_type
= fragP
->fr_var
;
3902 reloc_type
= BFD_RELOC_16_PCREL
;
3904 reloc_type
= BFD_RELOC_32_PCREL
;
3906 old_fr_fix
= fragP
->fr_fix
;
3907 opcode
= (unsigned char *) fragP
->fr_opcode
;
3911 case JUMP_PC_RELATIVE
:
3912 /* Make jmp (0xeb) a dword displacement jump. */
3914 fragP
->fr_fix
+= size
;
3915 fix_new (fragP
, old_fr_fix
, size
,
3917 fragP
->fr_offset
, 1,
3922 /* This changes the byte-displacement jump 0x7N
3923 to the dword-displacement jump 0x0f,0x8N. */
3924 opcode
[1] = opcode
[0] + 0x10;
3925 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3926 /* We've added an opcode byte. */
3927 fragP
->fr_fix
+= 1 + size
;
3928 fix_new (fragP
, old_fr_fix
+ 1, size
,
3930 fragP
->fr_offset
, 1,
3935 return fragP
->fr_fix
- old_fr_fix
;
3937 /* Guess a short jump. */
3941 /* Called after relax() is finished.
3943 In: Address of frag.
3944 fr_type == rs_machine_dependent.
3945 fr_subtype is what the address relaxed to.
3947 Out: Any fixSs and constants are set up.
3948 Caller will turn frag into a ".space 0". */
3950 #ifndef BFD_ASSEMBLER
3952 md_convert_frag (headers
, sec
, fragP
)
3953 object_headers
*headers ATTRIBUTE_UNUSED
;
3954 segT sec ATTRIBUTE_UNUSED
;
3955 register fragS
*fragP
;
3958 md_convert_frag (abfd
, sec
, fragP
)
3959 bfd
*abfd ATTRIBUTE_UNUSED
;
3960 segT sec ATTRIBUTE_UNUSED
;
3961 register fragS
*fragP
;
3964 register unsigned char *opcode
;
3965 unsigned char *where_to_put_displacement
= NULL
;
3966 offsetT target_address
;
3967 offsetT opcode_address
;
3968 unsigned int extension
= 0;
3969 offsetT displacement_from_opcode_start
;
3971 opcode
= (unsigned char *) fragP
->fr_opcode
;
3973 /* Address we want to reach in file space. */
3974 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3975 #ifdef BFD_ASSEMBLER
3976 /* Not needed otherwise? */
3977 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3980 /* Address opcode resides at in file space. */
3981 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3983 /* Displacement from opcode start to fill into instruction. */
3984 displacement_from_opcode_start
= target_address
- opcode_address
;
3986 switch (fragP
->fr_subtype
)
3988 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3989 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3990 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3991 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3992 /* Don't have to change opcode. */
3993 extension
= 1; /* 1 opcode + 1 displacement */
3994 where_to_put_displacement
= &opcode
[1];
3997 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3998 extension
= 5; /* 2 opcode + 4 displacement */
3999 opcode
[1] = opcode
[0] + 0x10;
4000 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4001 where_to_put_displacement
= &opcode
[2];
4004 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
4005 extension
= 4; /* 1 opcode + 4 displacement */
4007 where_to_put_displacement
= &opcode
[1];
4010 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
4011 extension
= 3; /* 2 opcode + 2 displacement */
4012 opcode
[1] = opcode
[0] + 0x10;
4013 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
4014 where_to_put_displacement
= &opcode
[2];
4017 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
4018 extension
= 2; /* 1 opcode + 2 displacement */
4020 where_to_put_displacement
= &opcode
[1];
4024 BAD_CASE (fragP
->fr_subtype
);
4027 /* Now put displacement after opcode. */
4028 md_number_to_chars ((char *) where_to_put_displacement
,
4029 (valueT
) (displacement_from_opcode_start
- extension
),
4030 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4031 fragP
->fr_fix
+= extension
;
4034 /* Size of byte displacement jmp. */
4035 int md_short_jump_size
= 2;
4037 /* Size of dword displacement jmp. */
4038 int md_long_jump_size
= 5;
4040 /* Size of relocation record. */
4041 const int md_reloc_size
= 8;
4044 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4046 addressT from_addr
, to_addr
;
4047 fragS
*frag ATTRIBUTE_UNUSED
;
4048 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4052 offset
= to_addr
- (from_addr
+ 2);
4053 /* Opcode for byte-disp jump. */
4054 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4055 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4059 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4061 addressT from_addr
, to_addr
;
4062 fragS
*frag ATTRIBUTE_UNUSED
;
4063 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4067 offset
= to_addr
- (from_addr
+ 5);
4068 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4069 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4072 /* Apply a fixup (fixS) to segment data, once it has been determined
4073 by our caller that we have all the info we need to fix it up.
4075 On the 386, immediates, displacements, and data pointers are all in
4076 the same (little-endian) format, so we don't need to care about which
4080 md_apply_fix3 (fixP
, valp
, seg
)
4081 /* The fix we're to put in. */
4084 /* Pointer to the value of the bits. */
4087 /* Segment fix is from. */
4088 segT seg ATTRIBUTE_UNUSED
;
4090 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4091 valueT value
= *valp
;
4093 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4096 switch (fixP
->fx_r_type
)
4102 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4105 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4108 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4113 /* This is a hack. There should be a better way to handle this.
4114 This covers for the fact that bfd_install_relocation will
4115 subtract the current location (for partial_inplace, PC relative
4116 relocations); see more below. */
4117 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4118 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4119 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4123 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4125 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4128 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4131 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4133 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4136 || (symbol_section_p (fixP
->fx_addsy
)
4137 && fseg
!= absolute_section
))
4138 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4139 && ! S_IS_WEAK (fixP
->fx_addsy
)
4140 && S_IS_DEFINED (fixP
->fx_addsy
)
4141 && ! S_IS_COMMON (fixP
->fx_addsy
))
4143 /* Yes, we add the values in twice. This is because
4144 bfd_perform_relocation subtracts them out again. I think
4145 bfd_perform_relocation is broken, but I don't dare change
4147 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4151 #if defined (OBJ_COFF) && defined (TE_PE)
4152 /* For some reason, the PE format does not store a section
4153 address offset for a PC relative symbol. */
4154 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4155 value
+= md_pcrel_from (fixP
);
4159 /* Fix a few things - the dynamic linker expects certain values here,
4160 and we must not dissappoint it. */
4161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4162 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4164 switch (fixP
->fx_r_type
)
4166 case BFD_RELOC_386_PLT32
:
4167 case BFD_RELOC_X86_64_PLT32
:
4168 /* Make the jump instruction point to the address of the operand. At
4169 runtime we merely add the offset to the actual PLT entry. */
4172 case BFD_RELOC_386_GOTPC
:
4174 /* This is tough to explain. We end up with this one if we have
4175 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4176 * here is to obtain the absolute address of the GOT, and it is strongly
4177 * preferable from a performance point of view to avoid using a runtime
4178 * relocation for this. The actual sequence of instructions often look
4184 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4186 * The call and pop essentially return the absolute address of
4187 * the label .L66 and store it in %ebx. The linker itself will
4188 * ultimately change the first operand of the addl so that %ebx points to
4189 * the GOT, but to keep things simple, the .o file must have this operand
4190 * set so that it generates not the absolute address of .L66, but the
4191 * absolute address of itself. This allows the linker itself simply
4192 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4193 * added in, and the addend of the relocation is stored in the operand
4194 * field for the instruction itself.
4196 * Our job here is to fix the operand so that it would add the correct
4197 * offset so that %ebx would point to itself. The thing that is tricky is
4198 * that .-.L66 will point to the beginning of the instruction, so we need
4199 * to further modify the operand so that it will point to itself.
4200 * There are other cases where you have something like:
4202 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4204 * and here no correction would be required. Internally in the assembler
4205 * we treat operands of this form as not being pcrel since the '.' is
4206 * explicitly mentioned, and I wonder whether it would simplify matters
4207 * to do it this way. Who knows. In earlier versions of the PIC patches,
4208 * the pcrel_adjust field was used to store the correction, but since the
4209 * expression is not pcrel, I felt it would be confusing to do it this
4214 case BFD_RELOC_386_GOT32
:
4215 case BFD_RELOC_X86_64_GOT32
:
4216 value
= 0; /* Fully resolved at runtime. No addend. */
4218 case BFD_RELOC_386_GOTOFF
:
4219 case BFD_RELOC_X86_64_GOTPCREL
:
4222 case BFD_RELOC_VTABLE_INHERIT
:
4223 case BFD_RELOC_VTABLE_ENTRY
:
4230 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4232 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4234 #ifndef BFD_ASSEMBLER
4235 md_number_to_chars (p
, value
, fixP
->fx_size
);
4237 /* Are we finished with this relocation now? */
4238 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4240 else if (use_rela_relocations
)
4242 fixP
->fx_no_overflow
= 1;
4245 md_number_to_chars (p
, value
, fixP
->fx_size
);
4251 #define MAX_LITTLENUMS 6
4253 /* Turn the string pointed to by litP into a floating point constant
4254 of type TYPE, and emit the appropriate bytes. The number of
4255 LITTLENUMS emitted is stored in *SIZEP. An error message is
4256 returned, or NULL on OK. */
4259 md_atof (type
, litP
, sizeP
)
4265 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4266 LITTLENUM_TYPE
*wordP
;
4288 return _("Bad call to md_atof ()");
4290 t
= atof_ieee (input_line_pointer
, type
, words
);
4292 input_line_pointer
= t
;
4294 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4295 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4296 the bigendian 386. */
4297 for (wordP
= words
+ prec
- 1; prec
--;)
4299 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4300 litP
+= sizeof (LITTLENUM_TYPE
);
4305 char output_invalid_buf
[8];
4312 sprintf (output_invalid_buf
, "'%c'", c
);
4314 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4315 return output_invalid_buf
;
4318 /* REG_STRING starts *before* REGISTER_PREFIX. */
4320 static const reg_entry
*
4321 parse_register (reg_string
, end_op
)
4325 char *s
= reg_string
;
4327 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4330 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4331 if (*s
== REGISTER_PREFIX
)
4334 if (is_space_char (*s
))
4338 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4340 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4341 return (const reg_entry
*) NULL
;
4345 /* For naked regs, make sure that we are not dealing with an identifier.
4346 This prevents confusing an identifier like `eax_var' with register
4348 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4349 return (const reg_entry
*) NULL
;
4353 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4355 /* Handle floating point regs, allowing spaces in the (i) part. */
4356 if (r
== i386_regtab
/* %st is first entry of table */)
4358 if (is_space_char (*s
))
4363 if (is_space_char (*s
))
4365 if (*s
>= '0' && *s
<= '7')
4367 r
= &i386_float_regtab
[*s
- '0'];
4369 if (is_space_char (*s
))
4377 /* We have "%st(" then garbage. */
4378 return (const reg_entry
*) NULL
;
4385 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4386 const char *md_shortopts
= "kVQ:sq";
4388 const char *md_shortopts
= "q";
4391 struct option md_longopts
[] = {
4392 #define OPTION_32 (OPTION_MD_BASE + 0)
4393 {"32", no_argument
, NULL
, OPTION_32
},
4394 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4395 #define OPTION_64 (OPTION_MD_BASE + 1)
4396 {"64", no_argument
, NULL
, OPTION_64
},
4398 {NULL
, no_argument
, NULL
, 0}
4400 size_t md_longopts_size
= sizeof (md_longopts
);
4403 md_parse_option (c
, arg
)
4405 char *arg ATTRIBUTE_UNUSED
;
4413 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4414 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4415 should be emitted or not. FIXME: Not implemented. */
4419 /* -V: SVR4 argument to print version ID. */
4421 print_version_id ();
4424 /* -k: Ignore for FreeBSD compatibility. */
4429 /* -s: On i386 Solaris, this tells the native assembler to use
4430 .stab instead of .stab.excl. We always use .stab anyhow. */
4435 const char **list
, **l
;
4437 list
= bfd_target_list ();
4438 for (l
= list
; *l
!= NULL
; l
++)
4439 if (strcmp (*l
, "elf64-x86-64") == 0)
4441 default_arch
= "x86_64";
4445 as_fatal (_("No compiled in support for x86_64"));
4452 default_arch
= "i386";
4462 md_show_usage (stream
)
4465 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4466 fprintf (stream
, _("\
4468 -V print assembler version number\n\
4470 -q quieten some warnings\n\
4473 fprintf (stream
, _("\
4474 -q quieten some warnings\n"));
4478 #ifdef BFD_ASSEMBLER
4479 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4480 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4482 /* Pick the target format to use. */
4485 i386_target_format ()
4487 if (!strcmp (default_arch
, "x86_64"))
4488 set_code_flag (CODE_64BIT
);
4489 else if (!strcmp (default_arch
, "i386"))
4490 set_code_flag (CODE_32BIT
);
4492 as_fatal (_("Unknown architecture"));
4493 switch (OUTPUT_FLAVOR
)
4495 #ifdef OBJ_MAYBE_AOUT
4496 case bfd_target_aout_flavour
:
4497 return AOUT_TARGET_FORMAT
;
4499 #ifdef OBJ_MAYBE_COFF
4500 case bfd_target_coff_flavour
:
4503 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4504 case bfd_target_elf_flavour
:
4506 if (flag_code
== CODE_64BIT
)
4507 use_rela_relocations
= 1;
4508 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4517 #endif /* OBJ_MAYBE_ more than one */
4518 #endif /* BFD_ASSEMBLER */
4521 md_undefined_symbol (name
)
4524 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4525 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4526 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4527 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4531 if (symbol_find (name
))
4532 as_bad (_("GOT already in symbol table"));
4533 GOT_symbol
= symbol_new (name
, undefined_section
,
4534 (valueT
) 0, &zero_address_frag
);
4541 /* Round up a section size to the appropriate boundary. */
4544 md_section_align (segment
, size
)
4545 segT segment ATTRIBUTE_UNUSED
;
4548 #ifdef BFD_ASSEMBLER
4549 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4550 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4552 /* For a.out, force the section size to be aligned. If we don't do
4553 this, BFD will align it for us, but it will not write out the
4554 final bytes of the section. This may be a bug in BFD, but it is
4555 easier to fix it here since that is how the other a.out targets
4559 align
= bfd_get_section_alignment (stdoutput
, segment
);
4560 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4568 /* On the i386, PC-relative offsets are relative to the start of the
4569 next instruction. That is, the address of the offset, plus its
4570 size, since the offset is always the last part of the insn. */
4573 md_pcrel_from (fixP
)
4576 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4583 int ignore ATTRIBUTE_UNUSED
;
4587 temp
= get_absolute_expression ();
4588 subseg_set (bss_section
, (subsegT
) temp
);
4589 demand_empty_rest_of_line ();
4594 #ifdef BFD_ASSEMBLER
4597 i386_validate_fix (fixp
)
4600 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4602 /* GOTOFF relocation are nonsense in 64bit mode. */
4603 if (flag_code
== CODE_64BIT
)
4605 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4611 tc_gen_reloc (section
, fixp
)
4612 asection
*section ATTRIBUTE_UNUSED
;
4616 bfd_reloc_code_real_type code
;
4618 switch (fixp
->fx_r_type
)
4620 case BFD_RELOC_X86_64_PLT32
:
4621 case BFD_RELOC_X86_64_GOT32
:
4622 case BFD_RELOC_X86_64_GOTPCREL
:
4623 case BFD_RELOC_386_PLT32
:
4624 case BFD_RELOC_386_GOT32
:
4625 case BFD_RELOC_386_GOTOFF
:
4626 case BFD_RELOC_386_GOTPC
:
4627 case BFD_RELOC_X86_64_32S
:
4629 case BFD_RELOC_VTABLE_ENTRY
:
4630 case BFD_RELOC_VTABLE_INHERIT
:
4631 code
= fixp
->fx_r_type
;
4636 switch (fixp
->fx_size
)
4639 as_bad (_("can not do %d byte pc-relative relocation"),
4641 code
= BFD_RELOC_32_PCREL
;
4643 case 1: code
= BFD_RELOC_8_PCREL
; break;
4644 case 2: code
= BFD_RELOC_16_PCREL
; break;
4645 case 4: code
= BFD_RELOC_32_PCREL
; break;
4650 switch (fixp
->fx_size
)
4653 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4654 code
= BFD_RELOC_32
;
4656 case 1: code
= BFD_RELOC_8
; break;
4657 case 2: code
= BFD_RELOC_16
; break;
4658 case 4: code
= BFD_RELOC_32
; break;
4659 case 8: code
= BFD_RELOC_64
; break;
4665 if (code
== BFD_RELOC_32
4667 && fixp
->fx_addsy
== GOT_symbol
)
4669 /* We don't support GOTPC on 64bit targets. */
4670 if (flag_code
== CODE_64BIT
)
4672 code
= BFD_RELOC_386_GOTPC
;
4675 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4676 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4677 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4679 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4680 if (!use_rela_relocations
)
4682 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4683 vtable entry to be used in the relocation's section offset. */
4684 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4685 rel
->address
= fixp
->fx_offset
;
4688 rel
->addend
= fixp
->fx_addnumber
;
4692 /* Use the rela in 64bit mode. */
4695 rel
->addend
= fixp
->fx_offset
;
4697 /* Ohhh, this is ugly. The problem is that if this is a local global
4698 symbol, the relocation will entirely be performed at link time, not
4699 at assembly time. bfd_perform_reloc doesn't know about this sort
4700 of thing, and as a result we need to fake it out here. */
4701 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4702 && !S_IS_COMMON (fixp
->fx_addsy
))
4703 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4706 rel
->addend
-= fixp
->fx_size
;
4709 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4710 if (rel
->howto
== NULL
)
4712 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4713 _("cannot represent relocation type %s"),
4714 bfd_get_reloc_code_name (code
));
4715 /* Set howto to a garbage value so that we can keep going. */
4716 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4717 assert (rel
->howto
!= NULL
);
4723 #else /* ! BFD_ASSEMBLER */
4725 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4727 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4730 relax_addressT segment_address_in_file
;
4732 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4733 Out: GNU LD relocation length code: 0, 1, or 2. */
4735 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4738 know (fixP
->fx_addsy
!= NULL
);
4740 md_number_to_chars (where
,
4741 (valueT
) (fixP
->fx_frag
->fr_address
4742 + fixP
->fx_where
- segment_address_in_file
),
4745 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4746 ? S_GET_TYPE (fixP
->fx_addsy
)
4747 : fixP
->fx_addsy
->sy_number
);
4749 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4750 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4751 where
[4] = r_symbolnum
& 0x0ff;
4752 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4753 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4754 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4757 #endif /* OBJ_AOUT or OBJ_BOUT. */
4759 #if defined (I386COFF)
4762 tc_coff_fix2rtype (fixP
)
4765 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4768 return (fixP
->fx_pcrel
?
4769 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4770 fixP
->fx_size
== 2 ? R_PCRWORD
:
4772 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4773 fixP
->fx_size
== 2 ? R_RELWORD
:
4778 tc_coff_sizemachdep (frag
)
4782 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4787 #endif /* I386COFF */
4789 #endif /* ! BFD_ASSEMBLER */
4791 /* Parse operands using Intel syntax. This implements a recursive descent
4792 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4795 FIXME: We do not recognize the full operand grammar defined in the MASM
4796 documentation. In particular, all the structure/union and
4797 high-level macro operands are missing.
4799 Uppercase words are terminals, lower case words are non-terminals.
4800 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4801 bars '|' denote choices. Most grammar productions are implemented in
4802 functions called 'intel_<production>'.
4804 Initial production is 'expr'.
4810 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4812 constant digits [[ radixOverride ]]
4814 dataType BYTE | WORD | DWORD | QWORD | XWORD
4847 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4848 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4850 hexdigit a | b | c | d | e | f
4851 | A | B | C | D | E | F
4861 register specialRegister
4865 segmentRegister CS | DS | ES | FS | GS | SS
4867 specialRegister CR0 | CR2 | CR3
4868 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4869 | TR3 | TR4 | TR5 | TR6 | TR7
4871 We simplify the grammar in obvious places (e.g., register parsing is
4872 done by calling parse_register) and eliminate immediate left recursion
4873 to implement a recursive-descent parser.
4913 /* Parsing structure for the intel syntax parser. Used to implement the
4914 semantic actions for the operand grammar. */
4915 struct intel_parser_s
4917 char *op_string
; /* The string being parsed. */
4918 int got_a_float
; /* Whether the operand is a float. */
4919 int op_modifier
; /* Operand modifier. */
4920 int is_mem
; /* 1 if operand is memory reference. */
4921 const reg_entry
*reg
; /* Last register reference found. */
4922 char *disp
; /* Displacement string being built. */
4925 static struct intel_parser_s intel_parser
;
4927 /* Token structure for parsing intel syntax. */
4930 int code
; /* Token code. */
4931 const reg_entry
*reg
; /* Register entry for register tokens. */
4932 char *str
; /* String representation. */
4935 static struct intel_token cur_token
, prev_token
;
4937 /* Token codes for the intel parser. Since T_SHORT is already used
4938 by COFF, undefine it first to prevent a warning. */
4953 /* Prototypes for intel parser functions. */
4954 static int intel_match_token
PARAMS ((int code
));
4955 static void intel_get_token
PARAMS ((void));
4956 static void intel_putback_token
PARAMS ((void));
4957 static int intel_expr
PARAMS ((void));
4958 static int intel_e05
PARAMS ((void));
4959 static int intel_e05_1
PARAMS ((void));
4960 static int intel_e06
PARAMS ((void));
4961 static int intel_e06_1
PARAMS ((void));
4962 static int intel_e09
PARAMS ((void));
4963 static int intel_e09_1
PARAMS ((void));
4964 static int intel_e10
PARAMS ((void));
4965 static int intel_e10_1
PARAMS ((void));
4966 static int intel_e11
PARAMS ((void));
4969 i386_intel_operand (operand_string
, got_a_float
)
4970 char *operand_string
;
4976 /* Initialize token holders. */
4977 cur_token
.code
= prev_token
.code
= T_NIL
;
4978 cur_token
.reg
= prev_token
.reg
= NULL
;
4979 cur_token
.str
= prev_token
.str
= NULL
;
4981 /* Initialize parser structure. */
4982 p
= intel_parser
.op_string
= (char *) malloc (strlen (operand_string
) + 1);
4985 strcpy (intel_parser
.op_string
, operand_string
);
4986 intel_parser
.got_a_float
= got_a_float
;
4987 intel_parser
.op_modifier
= -1;
4988 intel_parser
.is_mem
= 0;
4989 intel_parser
.reg
= NULL
;
4990 intel_parser
.disp
= (char *) malloc (strlen (operand_string
) + 1);
4991 if (intel_parser
.disp
== NULL
)
4993 intel_parser
.disp
[0] = '\0';
4995 /* Read the first token and start the parser. */
4997 ret
= intel_expr ();
5001 /* If we found a memory reference, hand it over to i386_displacement
5002 to fill in the rest of the operand fields. */
5003 if (intel_parser
.is_mem
)
5005 if ((i
.mem_operands
== 1
5006 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
5007 || i
.mem_operands
== 2)
5009 as_bad (_("too many memory references for '%s'"),
5010 current_templates
->start
->name
);
5015 char *s
= intel_parser
.disp
;
5018 /* Add the displacement expression. */
5020 ret
= i386_displacement (s
, s
+ strlen (s
))
5021 && i386_index_check (s
);
5025 /* Constant and OFFSET expressions are handled by i386_immediate. */
5026 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5027 || intel_parser
.reg
== NULL
)
5028 ret
= i386_immediate (intel_parser
.disp
);
5032 free (intel_parser
.disp
);
5042 /* expr SHORT e05 */
5043 if (cur_token
.code
== T_SHORT
)
5045 intel_parser
.op_modifier
= SHORT
;
5046 intel_match_token (T_SHORT
);
5048 return (intel_e05 ());
5053 return intel_e05 ();
5063 return (intel_e06 () && intel_e05_1 ());
5069 /* e05' addOp e06 e05' */
5070 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5072 strcat (intel_parser
.disp
, cur_token
.str
);
5073 intel_match_token (cur_token
.code
);
5075 return (intel_e06 () && intel_e05_1 ());
5090 return (intel_e09 () && intel_e06_1 ());
5096 /* e06' mulOp e09 e06' */
5097 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5099 strcat (intel_parser
.disp
, cur_token
.str
);
5100 intel_match_token (cur_token
.code
);
5102 return (intel_e09 () && intel_e06_1 ());
5110 /* e09 OFFSET e10 e09'
5119 /* e09 OFFSET e10 e09' */
5120 if (cur_token
.code
== T_OFFSET
)
5122 intel_parser
.is_mem
= 0;
5123 intel_parser
.op_modifier
= OFFSET_FLAT
;
5124 intel_match_token (T_OFFSET
);
5126 return (intel_e10 () && intel_e09_1 ());
5131 return (intel_e10 () && intel_e09_1 ());
5137 /* e09' PTR e10 e09' */
5138 if (cur_token
.code
== T_PTR
)
5140 if (prev_token
.code
== T_BYTE
)
5141 i
.suffix
= BYTE_MNEM_SUFFIX
;
5143 else if (prev_token
.code
== T_WORD
)
5145 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5146 i
.suffix
= SHORT_MNEM_SUFFIX
;
5148 i
.suffix
= WORD_MNEM_SUFFIX
;
5151 else if (prev_token
.code
== T_DWORD
)
5153 if (intel_parser
.got_a_float
== 1) /* "f..." */
5154 i
.suffix
= SHORT_MNEM_SUFFIX
;
5156 i
.suffix
= LONG_MNEM_SUFFIX
;
5159 else if (prev_token
.code
== T_QWORD
)
5161 if (intel_parser
.got_a_float
== 1) /* "f..." */
5162 i
.suffix
= LONG_MNEM_SUFFIX
;
5164 i
.suffix
= QWORD_MNEM_SUFFIX
;
5167 else if (prev_token
.code
== T_XWORD
)
5168 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5172 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5176 intel_match_token (T_PTR
);
5178 return (intel_e10 () && intel_e09_1 ());
5181 /* e09 : e10 e09' */
5182 else if (cur_token
.code
== ':')
5184 /* Mark as a memory operand only if it's not already known to be an
5185 offset expression. */
5186 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5187 intel_parser
.is_mem
= 1;
5189 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5204 return (intel_e11 () && intel_e10_1 ());
5210 /* e10' [ expr ] e10' */
5211 if (cur_token
.code
== '[')
5213 intel_match_token ('[');
5215 /* Mark as a memory operand only if it's not already known to be an
5216 offset expression. If it's an offset expression, we need to keep
5218 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5219 intel_parser
.is_mem
= 1;
5221 strcat (intel_parser
.disp
, "[");
5223 /* Add a '+' to the displacement string if necessary. */
5224 if (*intel_parser
.disp
!= '\0'
5225 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5226 strcat (intel_parser
.disp
, "+");
5228 if (intel_expr () && intel_match_token (']'))
5230 /* Preserve brackets when the operand is an offset expression. */
5231 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5232 strcat (intel_parser
.disp
, "]");
5234 return intel_e10_1 ();
5261 if (cur_token
.code
== '(')
5263 intel_match_token ('(');
5264 strcat (intel_parser
.disp
, "(");
5266 if (intel_expr () && intel_match_token (')'))
5268 strcat (intel_parser
.disp
, ")");
5276 else if (cur_token
.code
== '[')
5278 intel_match_token ('[');
5280 /* Mark as a memory operand only if it's not already known to be an
5281 offset expression. If it's an offset expression, we need to keep
5283 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5284 intel_parser
.is_mem
= 1;
5286 strcat (intel_parser
.disp
, "[");
5288 /* Operands for jump/call inside brackets denote absolute addresses. */
5289 if (current_templates
->start
->opcode_modifier
& Jump
5290 || current_templates
->start
->opcode_modifier
& JumpDword
5291 || current_templates
->start
->opcode_modifier
& JumpByte
5292 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5293 i
.types
[this_operand
] |= JumpAbsolute
;
5295 /* Add a '+' to the displacement string if necessary. */
5296 if (*intel_parser
.disp
!= '\0'
5297 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5298 strcat (intel_parser
.disp
, "+");
5300 if (intel_expr () && intel_match_token (']'))
5302 /* Preserve brackets when the operand is an offset expression. */
5303 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5304 strcat (intel_parser
.disp
, "]");
5317 else if (cur_token
.code
== T_BYTE
5318 || cur_token
.code
== T_WORD
5319 || cur_token
.code
== T_DWORD
5320 || cur_token
.code
== T_QWORD
5321 || cur_token
.code
== T_XWORD
)
5323 intel_match_token (cur_token
.code
);
5330 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5332 strcat (intel_parser
.disp
, cur_token
.str
);
5333 intel_match_token (cur_token
.code
);
5335 /* Mark as a memory operand only if it's not already known to be an
5336 offset expression. */
5337 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5338 intel_parser
.is_mem
= 1;
5344 else if (cur_token
.code
== T_REG
)
5346 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5348 intel_match_token (T_REG
);
5350 /* Check for segment change. */
5351 if (cur_token
.code
== ':')
5353 if (reg
->reg_type
& (SReg2
| SReg3
))
5355 switch (reg
->reg_num
)
5358 i
.seg
[i
.mem_operands
] = &es
;
5361 i
.seg
[i
.mem_operands
] = &cs
;
5364 i
.seg
[i
.mem_operands
] = &ss
;
5367 i
.seg
[i
.mem_operands
] = &ds
;
5370 i
.seg
[i
.mem_operands
] = &fs
;
5373 i
.seg
[i
.mem_operands
] = &gs
;
5379 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5384 /* Not a segment register. Check for register scaling. */
5385 else if (cur_token
.code
== '*')
5387 if (!intel_parser
.is_mem
)
5389 as_bad (_("Register scaling only allowed in memory operands."));
5393 /* What follows must be a valid scale. */
5394 if (intel_match_token ('*')
5395 && strchr ("01248", *cur_token
.str
))
5398 i
.types
[this_operand
] |= BaseIndex
;
5400 /* Set the scale after setting the register (otherwise,
5401 i386_scale will complain) */
5402 i386_scale (cur_token
.str
);
5403 intel_match_token (T_CONST
);
5407 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5413 /* No scaling. If this is a memory operand, the register is either a
5414 base register (first occurrence) or an index register (second
5416 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5418 if (i
.base_reg
&& i
.index_reg
)
5420 as_bad (_("Too many register references in memory operand.\n"));
5424 if (i
.base_reg
== NULL
)
5429 i
.types
[this_operand
] |= BaseIndex
;
5432 /* Offset modifier. Add the register to the displacement string to be
5433 parsed as an immediate expression after we're done. */
5434 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5435 strcat (intel_parser
.disp
, reg
->reg_name
);
5437 /* It's neither base nor index nor offset. */
5440 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5441 i
.op
[this_operand
].regs
= reg
;
5445 /* Since registers are not part of the displacement string (except
5446 when we're parsing offset operands), we may need to remove any
5447 preceding '+' from the displacement string. */
5448 if (*intel_parser
.disp
!= '\0'
5449 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5451 char *s
= intel_parser
.disp
;
5452 s
+= strlen (s
) - 1;
5461 else if (cur_token
.code
== T_ID
)
5463 /* Add the identifier to the displacement string. */
5464 strcat (intel_parser
.disp
, cur_token
.str
);
5465 intel_match_token (T_ID
);
5467 /* The identifier represents a memory reference only if it's not
5468 preceded by an offset modifier. */
5469 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5470 intel_parser
.is_mem
= 1;
5476 else if (cur_token
.code
== T_CONST
5477 || cur_token
.code
== '-'
5478 || cur_token
.code
== '+')
5482 /* Allow constants that start with `+' or `-'. */
5483 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5485 strcat (intel_parser
.disp
, cur_token
.str
);
5486 intel_match_token (cur_token
.code
);
5487 if (cur_token
.code
!= T_CONST
)
5489 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5495 save_str
= (char *) malloc (strlen (cur_token
.str
) + 1);
5496 if (save_str
== NULL
)
5498 strcpy (save_str
, cur_token
.str
);
5500 /* Get the next token to check for register scaling. */
5501 intel_match_token (cur_token
.code
);
5503 /* Check if this constant is a scaling factor for an index register. */
5504 if (cur_token
.code
== '*')
5506 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5508 if (!intel_parser
.is_mem
)
5510 as_bad (_("Register scaling only allowed in memory operands."));
5514 /* The constant is followed by `* reg', so it must be
5516 if (strchr ("01248", *save_str
))
5518 i
.index_reg
= cur_token
.reg
;
5519 i
.types
[this_operand
] |= BaseIndex
;
5521 /* Set the scale after setting the register (otherwise,
5522 i386_scale will complain) */
5523 i386_scale (save_str
);
5524 intel_match_token (T_REG
);
5526 /* Since registers are not part of the displacement
5527 string, we may need to remove any preceding '+' from
5528 the displacement string. */
5529 if (*intel_parser
.disp
!= '\0')
5531 char *s
= intel_parser
.disp
;
5532 s
+= strlen (s
) - 1;
5545 /* The constant was not used for register scaling. Since we have
5546 already consumed the token following `*' we now need to put it
5547 back in the stream. */
5549 intel_putback_token ();
5552 /* Add the constant to the displacement string. */
5553 strcat (intel_parser
.disp
, save_str
);
5559 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5563 /* Match the given token against cur_token. If they match, read the next
5564 token from the operand string. */
5566 intel_match_token (code
)
5569 if (cur_token
.code
== code
)
5576 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5581 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5586 const reg_entry
*reg
;
5587 struct intel_token new_token
;
5589 new_token
.code
= T_NIL
;
5590 new_token
.reg
= NULL
;
5591 new_token
.str
= NULL
;
5593 /* Free the memory allocated to the previous token and move
5594 cur_token to prev_token. */
5596 free (prev_token
.str
);
5598 prev_token
= cur_token
;
5600 /* Skip whitespace. */
5601 while (is_space_char (*intel_parser
.op_string
))
5602 intel_parser
.op_string
++;
5604 /* Return an empty token if we find nothing else on the line. */
5605 if (*intel_parser
.op_string
== '\0')
5607 cur_token
= new_token
;
5611 /* The new token cannot be larger than the remainder of the operand
5613 new_token
.str
= (char *) malloc (strlen (intel_parser
.op_string
) + 1);
5614 if (new_token
.str
== NULL
)
5616 new_token
.str
[0] = '\0';
5618 if (strchr ("0123456789", *intel_parser
.op_string
))
5620 char *p
= new_token
.str
;
5621 char *q
= intel_parser
.op_string
;
5622 new_token
.code
= T_CONST
;
5624 /* Allow any kind of identifier char to encompass floating point and
5625 hexadecimal numbers. */
5626 while (is_identifier_char (*q
))
5630 /* Recognize special symbol names [0-9][bf]. */
5631 if (strlen (intel_parser
.op_string
) == 2
5632 && (intel_parser
.op_string
[1] == 'b'
5633 || intel_parser
.op_string
[1] == 'f'))
5634 new_token
.code
= T_ID
;
5637 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5639 new_token
.code
= *intel_parser
.op_string
;
5640 new_token
.str
[0] = *intel_parser
.op_string
;
5641 new_token
.str
[1] = '\0';
5644 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5645 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5647 new_token
.code
= T_REG
;
5648 new_token
.reg
= reg
;
5650 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5652 new_token
.str
[0] = REGISTER_PREFIX
;
5653 new_token
.str
[1] = '\0';
5656 strcat (new_token
.str
, reg
->reg_name
);
5659 else if (is_identifier_char (*intel_parser
.op_string
))
5661 char *p
= new_token
.str
;
5662 char *q
= intel_parser
.op_string
;
5664 /* A '.' or '$' followed by an identifier char is an identifier.
5665 Otherwise, it's operator '.' followed by an expression. */
5666 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5668 new_token
.code
= *q
;
5669 new_token
.str
[0] = *q
;
5670 new_token
.str
[1] = '\0';
5674 while (is_identifier_char (*q
) || *q
== '@')
5678 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5679 new_token
.code
= T_BYTE
;
5681 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5682 new_token
.code
= T_WORD
;
5684 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5685 new_token
.code
= T_DWORD
;
5687 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5688 new_token
.code
= T_QWORD
;
5690 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5691 new_token
.code
= T_XWORD
;
5693 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5694 new_token
.code
= T_PTR
;
5696 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5697 new_token
.code
= T_SHORT
;
5699 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5701 new_token
.code
= T_OFFSET
;
5703 /* ??? This is not mentioned in the MASM grammar but gcc
5704 makes use of it with -mintel-syntax. OFFSET may be
5705 followed by FLAT: */
5706 if (strncasecmp (q
, " FLAT:", 6) == 0)
5707 strcat (new_token
.str
, " FLAT:");
5710 /* ??? This is not mentioned in the MASM grammar. */
5711 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5712 new_token
.code
= T_OFFSET
;
5715 new_token
.code
= T_ID
;
5720 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5722 intel_parser
.op_string
+= strlen (new_token
.str
);
5723 cur_token
= new_token
;
5726 /* Put cur_token back into the token stream and make cur_token point to
5729 intel_putback_token ()
5731 intel_parser
.op_string
-= strlen (cur_token
.str
);
5732 free (cur_token
.str
);
5733 cur_token
= prev_token
;
5735 /* Forget prev_token. */
5736 prev_token
.code
= T_NIL
;
5737 prev_token
.reg
= NULL
;
5738 prev_token
.str
= NULL
;