1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template
*start
;
103 const insn_template
*end
;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem
; /* codes register or memory operand */
111 unsigned int reg
; /* codes register operand (or extended opcode) */
112 unsigned int mode
; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte
;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name
; /* arch name */
132 unsigned int len
; /* arch string length */
133 enum processor_type type
; /* arch type */
134 i386_cpu_flags flags
; /* cpu feature flags */
135 unsigned int skip
; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name
; /* arch name */
143 unsigned int len
; /* arch string length */
144 i386_cpu_flags flags
; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c
);
161 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
163 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS
*);
168 static int i386_intel_parse_name (const char *, expressionS
*);
169 static const reg_entry
*parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template
*match_template (void);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry
*build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS
*, offsetT
);
188 static void output_disp (fragS
*, offsetT
);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
196 static const char *default_arch
= DEFAULT_ARCH
;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op
;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry
*mask
;
220 unsigned int zeroing
;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op
;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op
;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes
[4];
246 /* Destination or source register specifier. */
247 const reg_entry
*register_specifier
;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry
*regs
;
262 operand_size_mismatch
,
263 operand_type_mismatch
,
264 register_type_mismatch
,
265 number_of_operands_mismatch
,
266 invalid_instruction_suffix
,
269 unsupported_with_intel_mnemonic
,
272 invalid_vsib_address
,
273 invalid_vector_register_set
,
274 unsupported_vector_index_register
,
275 unsupported_broadcast
,
276 broadcast_not_on_src_operand
,
279 mask_not_on_destination
,
282 rc_sae_operand_not_last_imm
,
283 invalid_register_operand
,
289 /* TM holds the template for the insn were currently assembling. */
292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
296 /* OPERANDS gives the number of given operands. */
297 unsigned int operands
;
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
302 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
304 /* TYPES [i] is the type (see above #defines) which tells us how to
305 use OP[i] for the corresponding operand. */
306 i386_operand_type types
[MAX_OPERANDS
];
308 /* Displacement expression, immediate expression, or register for each
310 union i386_op op
[MAX_OPERANDS
];
312 /* Flags for operands. */
313 unsigned int flags
[MAX_OPERANDS
];
314 #define Operand_PCrel 1
316 /* Relocation type for operand */
317 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry
*base_reg
;
322 const reg_entry
*index_reg
;
323 unsigned int log2_scale_factor
;
325 /* SEG gives the seg_entries of this insn. They are zero unless
326 explicit segment overrides are given. */
327 const seg_entry
*seg
[2];
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes
;
332 unsigned char prefix
[MAX_PREFIXES
];
334 /* RM and SIB are the modrm byte and the sib byte where the
335 addressing modes of this insn are encoded. */
342 /* Masking attributes. */
343 struct Mask_Operation
*mask
;
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation
*rounding
;
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation
*broadcast
;
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift
;
354 /* Swap operand in encoding. */
355 unsigned int swap_operand
;
357 /* Prefer 8bit or 32bit displacement in encoding. */
360 disp_encoding_default
= 0,
366 const char *rep_prefix
;
369 const char *hle_prefix
;
371 /* Have BND prefix. */
372 const char *bnd_prefix
;
374 /* Need VREX to support upper 16 registers. */
378 enum i386_error error
;
381 typedef struct _i386_insn i386_insn
;
383 /* Link RC type with corresponding string, that'll be looked for in
392 static const struct RC_name RC_NamesTable
[] =
394 { rne
, STRING_COMMA_LEN ("rn-sae") },
395 { rd
, STRING_COMMA_LEN ("rd-sae") },
396 { ru
, STRING_COMMA_LEN ("ru-sae") },
397 { rz
, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly
, STRING_COMMA_LEN ("sae") },
401 /* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
403 const char extra_symbol_chars
[] = "*%-([{"
412 #if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
414 && !defined (TE_GNU) \
415 && !defined (TE_LINUX) \
416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
418 && !defined (TE_FreeBSD) \
419 && !defined (TE_DragonFly) \
420 && !defined (TE_NetBSD)))
421 /* This array holds the chars that always start a comment. If the
422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424 const char *i386_comment_chars
= "#/";
425 #define SVR4_COMMENT_CHARS 1
426 #define PREFIX_SEPARATOR '\\'
429 const char *i386_comment_chars
= "#";
430 #define PREFIX_SEPARATOR '/'
433 /* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
437 first line of the input file. This is because the compiler outputs
438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
440 '/' isn't otherwise defined. */
441 const char line_comment_chars
[] = "#/";
443 const char line_separator_chars
[] = ";";
445 /* Chars that can be used to separate mant from exp in floating point
447 const char EXP_CHARS
[] = "eE";
449 /* Chars that mean this number is a floating point constant
452 const char FLT_CHARS
[] = "fFdDxX";
454 /* Tables for lexical analysis. */
455 static char mnemonic_chars
[256];
456 static char register_chars
[256];
457 static char operand_chars
[256];
458 static char identifier_chars
[256];
459 static char digit_chars
[256];
461 /* Lexical macros. */
462 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463 #define is_operand_char(x) (operand_chars[(unsigned char) x])
464 #define is_register_char(x) (register_chars[(unsigned char) x])
465 #define is_space_char(x) ((x) == ' ')
466 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467 #define is_digit_char(x) (digit_chars[(unsigned char) x])
469 /* All non-digit non-letter characters that may occur in an operand. */
470 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
472 /* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
475 assembler instruction). */
476 static char save_stack
[32];
477 static char *save_stack_p
;
478 #define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480 #define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
483 /* The instruction we're assembling. */
486 /* Possible templates for current insn. */
487 static const templates
*current_templates
;
489 /* Per instruction expressionS buffers: max displacements & immediates. */
490 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
491 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
493 /* Current operand we are working on. */
494 static int this_operand
= -1;
496 /* We support four different modes. FLAG_CODE variable is used to distinguish
504 static enum flag_code flag_code
;
505 static unsigned int object_64bit
;
506 static unsigned int disallow_64bit_reloc
;
507 static int use_rela_relocations
= 0;
509 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
513 /* The ELF ABI to use. */
521 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
524 #if defined (TE_PE) || defined (TE_PEP)
525 /* Use big object file format. */
526 static int use_big_obj
= 0;
529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530 /* 1 if generating code for a shared library. */
531 static int shared
= 0;
534 /* 1 for intel syntax,
536 static int intel_syntax
= 0;
538 /* 1 for Intel64 ISA,
542 /* 1 for intel mnemonic,
543 0 if att mnemonic. */
544 static int intel_mnemonic
= !SYSV386_COMPAT
;
546 /* 1 if support old (<= 2.8.1) versions of gcc. */
547 static int old_gcc
= OLDGCC_COMPAT
;
549 /* 1 if pseudo registers are permitted. */
550 static int allow_pseudo_reg
= 0;
552 /* 1 if register prefix % not required. */
553 static int allow_naked_reg
= 0;
555 /* 1 if the assembler should add BND prefix for all control-tranferring
556 instructions supporting it, even if this prefix wasn't specified
558 static int add_bnd_prefix
= 0;
560 /* 1 if pseudo index register, eiz/riz, is allowed . */
561 static int allow_index_reg
= 0;
563 /* 1 if the assembler should ignore LOCK prefix, even if it was
564 specified explicitly. */
565 static int omit_lock_prefix
= 0;
567 /* 1 if the assembler should encode lfence, mfence, and sfence as
568 "lock addl $0, (%{re}sp)". */
569 static int avoid_fence
= 0;
571 /* 1 if the assembler should generate relax relocations. */
573 static int generate_relax_relocations
574 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
576 static enum check_kind
582 sse_check
, operand_check
= check_warning
;
584 /* Register prefix used for error message. */
585 static const char *register_prefix
= "%";
587 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
588 leave, push, and pop instructions so that gcc has the same stack
589 frame as in 32 bit mode. */
590 static char stackop_size
= '\0';
592 /* Non-zero to optimize code alignment. */
593 int optimize_align_code
= 1;
595 /* Non-zero to quieten some warnings. */
596 static int quiet_warnings
= 0;
599 static const char *cpu_arch_name
= NULL
;
600 static char *cpu_sub_arch_name
= NULL
;
602 /* CPU feature flags. */
603 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
605 /* If we have selected a cpu we are generating instructions for. */
606 static int cpu_arch_tune_set
= 0;
608 /* Cpu we are generating instructions for. */
609 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
611 /* CPU feature flags of cpu we are generating instructions for. */
612 static i386_cpu_flags cpu_arch_tune_flags
;
614 /* CPU instruction set architecture used. */
615 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
617 /* CPU feature flags of instruction set architecture used. */
618 i386_cpu_flags cpu_arch_isa_flags
;
620 /* If set, conditional jumps are not automatically promoted to handle
621 larger than a byte offset. */
622 static unsigned int no_cond_jump_promotion
= 0;
624 /* Encode SSE instructions with VEX prefix. */
625 static unsigned int sse2avx
;
627 /* Encode scalar AVX instructions with specific vector length. */
634 /* Encode scalar EVEX LIG instructions with specific vector length. */
642 /* Encode EVEX WIG instructions with specific evex.w. */
649 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
650 static enum rc_type evexrcig
= rne
;
652 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
653 static symbolS
*GOT_symbol
;
655 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
656 unsigned int x86_dwarf2_return_column
;
658 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
659 int x86_cie_data_alignment
;
661 /* Interface to relax_segment.
662 There are 3 major relax states for 386 jump insns because the
663 different types of jumps add different sizes to frags when we're
664 figuring out what sort of jump to choose to reach a given label. */
667 #define UNCOND_JUMP 0
669 #define COND_JUMP86 2
674 #define SMALL16 (SMALL | CODE16)
676 #define BIG16 (BIG | CODE16)
680 #define INLINE __inline__
686 #define ENCODE_RELAX_STATE(type, size) \
687 ((relax_substateT) (((type) << 2) | (size)))
688 #define TYPE_FROM_RELAX_STATE(s) \
690 #define DISP_SIZE_FROM_RELAX_STATE(s) \
691 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
693 /* This table is used by relax_frag to promote short jumps to long
694 ones where necessary. SMALL (short) jumps may be promoted to BIG
695 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
696 don't allow a short jump in a 32 bit code segment to be promoted to
697 a 16 bit offset jump because it's slower (requires data size
698 prefix), and doesn't work, unless the destination is in the bottom
699 64k of the code segment (The top 16 bits of eip are zeroed). */
701 const relax_typeS md_relax_table
[] =
704 1) most positive reach of this state,
705 2) most negative reach of this state,
706 3) how many bytes this mode will have in the variable part of the frag
707 4) which index into the table to try if we can't fit into this one. */
709 /* UNCOND_JUMP states. */
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
712 /* dword jmp adds 4 bytes to frag:
713 0 extra opcode bytes, 4 displacement bytes. */
715 /* word jmp adds 2 byte2 to frag:
716 0 extra opcode bytes, 2 displacement bytes. */
719 /* COND_JUMP states. */
720 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
721 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
722 /* dword conditionals adds 5 bytes to frag:
723 1 extra opcode byte, 4 displacement bytes. */
725 /* word conditionals add 3 bytes to frag:
726 1 extra opcode byte, 2 displacement bytes. */
729 /* COND_JUMP86 states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
732 /* dword conditionals adds 5 bytes to frag:
733 1 extra opcode byte, 4 displacement bytes. */
735 /* word conditionals add 4 bytes to frag:
736 1 displacement byte and a 3 byte long branch insn. */
740 static const arch_entry cpu_arch
[] =
742 /* Do not replace the first two entries - i386_target_format()
743 relies on them being there in this order. */
744 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
745 CPU_GENERIC32_FLAGS
, 0 },
746 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
747 CPU_GENERIC64_FLAGS
, 0 },
748 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
750 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
752 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
754 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
756 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
758 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
760 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
762 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
764 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
765 CPU_PENTIUMPRO_FLAGS
, 0 },
766 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
768 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
770 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
772 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
774 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
775 CPU_NOCONA_FLAGS
, 0 },
776 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
778 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
780 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
781 CPU_CORE2_FLAGS
, 1 },
782 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
783 CPU_CORE2_FLAGS
, 0 },
784 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
785 CPU_COREI7_FLAGS
, 0 },
786 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
788 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM
,
790 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU
,
791 CPU_IAMCU_FLAGS
, 0 },
792 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
794 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
796 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
797 CPU_ATHLON_FLAGS
, 0 },
798 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
800 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
802 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
804 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
805 CPU_AMDFAM10_FLAGS
, 0 },
806 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD
,
807 CPU_BDVER1_FLAGS
, 0 },
808 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD
,
809 CPU_BDVER2_FLAGS
, 0 },
810 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD
,
811 CPU_BDVER3_FLAGS
, 0 },
812 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD
,
813 CPU_BDVER4_FLAGS
, 0 },
814 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER
,
815 CPU_ZNVER1_FLAGS
, 0 },
816 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT
,
817 CPU_BTVER1_FLAGS
, 0 },
818 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT
,
819 CPU_BTVER2_FLAGS
, 0 },
820 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
822 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
824 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
826 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
828 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
830 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
832 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
834 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
835 CPU_SSSE3_FLAGS
, 0 },
836 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
837 CPU_SSE4_1_FLAGS
, 0 },
838 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
839 CPU_SSE4_2_FLAGS
, 0 },
840 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
841 CPU_SSE4_2_FLAGS
, 0 },
842 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
844 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN
,
846 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN
,
847 CPU_AVX512F_FLAGS
, 0 },
848 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN
,
849 CPU_AVX512CD_FLAGS
, 0 },
850 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN
,
851 CPU_AVX512ER_FLAGS
, 0 },
852 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN
,
853 CPU_AVX512PF_FLAGS
, 0 },
854 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN
,
855 CPU_AVX512DQ_FLAGS
, 0 },
856 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN
,
857 CPU_AVX512BW_FLAGS
, 0 },
858 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN
,
859 CPU_AVX512VL_FLAGS
, 0 },
860 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
862 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN
,
863 CPU_VMFUNC_FLAGS
, 0 },
864 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
866 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
867 CPU_XSAVE_FLAGS
, 0 },
868 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
869 CPU_XSAVEOPT_FLAGS
, 0 },
870 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN
,
871 CPU_XSAVEC_FLAGS
, 0 },
872 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN
,
873 CPU_XSAVES_FLAGS
, 0 },
874 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
876 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
877 CPU_PCLMUL_FLAGS
, 0 },
878 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
879 CPU_PCLMUL_FLAGS
, 1 },
880 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
881 CPU_FSGSBASE_FLAGS
, 0 },
882 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
883 CPU_RDRND_FLAGS
, 0 },
884 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
886 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN
,
888 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
890 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
892 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
894 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
896 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
897 CPU_MOVBE_FLAGS
, 0 },
898 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN
,
900 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
902 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN
,
903 CPU_LZCNT_FLAGS
, 0 },
904 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN
,
906 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN
,
908 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN
,
909 CPU_INVPCID_FLAGS
, 0 },
910 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
911 CPU_CLFLUSH_FLAGS
, 0 },
912 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
914 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
915 CPU_SYSCALL_FLAGS
, 0 },
916 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
917 CPU_RDTSCP_FLAGS
, 0 },
918 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
919 CPU_3DNOW_FLAGS
, 0 },
920 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
921 CPU_3DNOWA_FLAGS
, 0 },
922 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
923 CPU_PADLOCK_FLAGS
, 0 },
924 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
926 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
928 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
929 CPU_SSE4A_FLAGS
, 0 },
930 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
932 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
934 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
936 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN
,
938 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN
,
939 CPU_RDSEED_FLAGS
, 0 },
940 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN
,
941 CPU_PRFCHW_FLAGS
, 0 },
942 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN
,
944 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN
,
946 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN
,
948 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN
,
949 CPU_CLFLUSHOPT_FLAGS
, 0 },
950 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN
,
951 CPU_PREFETCHWT1_FLAGS
, 0 },
952 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN
,
954 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN
,
956 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN
,
957 CPU_PCOMMIT_FLAGS
, 0 },
958 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN
,
959 CPU_AVX512IFMA_FLAGS
, 0 },
960 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN
,
961 CPU_AVX512VBMI_FLAGS
, 0 },
962 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN
,
963 CPU_CLZERO_FLAGS
, 0 },
964 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN
,
965 CPU_MWAITX_FLAGS
, 0 },
966 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN
,
967 CPU_OSPKE_FLAGS
, 0 },
968 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN
,
969 CPU_RDPID_FLAGS
, 0 },
972 static const noarch_entry cpu_noarch
[] =
974 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS
},
975 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS
},
976 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS
},
977 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS
},
981 /* Like s_lcomm_internal in gas/read.c but the alignment string
982 is allowed to be optional. */
985 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
992 && *input_line_pointer
== ',')
994 align
= parse_align (needs_align
- 1);
996 if (align
== (addressT
) -1)
1011 bss_alloc (symbolP
, size
, align
);
1016 pe_lcomm (int needs_align
)
1018 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1022 const pseudo_typeS md_pseudo_table
[] =
1024 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1025 {"align", s_align_bytes
, 0},
1027 {"align", s_align_ptwo
, 0},
1029 {"arch", set_cpu_arch
, 0},
1033 {"lcomm", pe_lcomm
, 1},
1035 {"ffloat", float_cons
, 'f'},
1036 {"dfloat", float_cons
, 'd'},
1037 {"tfloat", float_cons
, 'x'},
1039 {"slong", signed_cons
, 4},
1040 {"noopt", s_ignore
, 0},
1041 {"optim", s_ignore
, 0},
1042 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1043 {"code16", set_code_flag
, CODE_16BIT
},
1044 {"code32", set_code_flag
, CODE_32BIT
},
1045 {"code64", set_code_flag
, CODE_64BIT
},
1046 {"intel_syntax", set_intel_syntax
, 1},
1047 {"att_syntax", set_intel_syntax
, 0},
1048 {"intel_mnemonic", set_intel_mnemonic
, 1},
1049 {"att_mnemonic", set_intel_mnemonic
, 0},
1050 {"allow_index_reg", set_allow_index_reg
, 1},
1051 {"disallow_index_reg", set_allow_index_reg
, 0},
1052 {"sse_check", set_check
, 0},
1053 {"operand_check", set_check
, 1},
1054 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1055 {"largecomm", handle_large_common
, 0},
1057 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
1058 {"loc", dwarf2_directive_loc
, 0},
1059 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1062 {"secrel32", pe_directive_secrel
, 0},
1067 /* For interface with expression (). */
1068 extern char *input_line_pointer
;
1070 /* Hash table for instruction mnemonic lookup. */
1071 static struct hash_control
*op_hash
;
1073 /* Hash table for register lookup. */
1074 static struct hash_control
*reg_hash
;
1077 i386_align_code (fragS
*fragP
, int count
)
1079 /* Various efficient no-op patterns for aligning code labels.
1080 Note: Don't try to assemble the instructions in the comments.
1081 0L and 0w are not legal. */
1082 static const unsigned char f32_1
[] =
1084 static const unsigned char f32_2
[] =
1085 {0x66,0x90}; /* xchg %ax,%ax */
1086 static const unsigned char f32_3
[] =
1087 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1088 static const unsigned char f32_4
[] =
1089 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1090 static const unsigned char f32_5
[] =
1092 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1093 static const unsigned char f32_6
[] =
1094 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1095 static const unsigned char f32_7
[] =
1096 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1097 static const unsigned char f32_8
[] =
1099 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1100 static const unsigned char f32_9
[] =
1101 {0x89,0xf6, /* movl %esi,%esi */
1102 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1103 static const unsigned char f32_10
[] =
1104 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1105 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1106 static const unsigned char f32_11
[] =
1107 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1108 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1109 static const unsigned char f32_12
[] =
1110 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1111 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1112 static const unsigned char f32_13
[] =
1113 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1114 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1115 static const unsigned char f32_14
[] =
1116 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1117 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1118 static const unsigned char f16_3
[] =
1119 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1120 static const unsigned char f16_4
[] =
1121 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1122 static const unsigned char f16_5
[] =
1124 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1125 static const unsigned char f16_6
[] =
1126 {0x89,0xf6, /* mov %si,%si */
1127 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1128 static const unsigned char f16_7
[] =
1129 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1130 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1131 static const unsigned char f16_8
[] =
1132 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1133 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1134 static const unsigned char jump_31
[] =
1135 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1136 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1137 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1138 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1139 static const unsigned char *const f32_patt
[] = {
1140 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
1141 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
1143 static const unsigned char *const f16_patt
[] = {
1144 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
1146 /* nopl (%[re]ax) */
1147 static const unsigned char alt_3
[] =
1149 /* nopl 0(%[re]ax) */
1150 static const unsigned char alt_4
[] =
1151 {0x0f,0x1f,0x40,0x00};
1152 /* nopl 0(%[re]ax,%[re]ax,1) */
1153 static const unsigned char alt_5
[] =
1154 {0x0f,0x1f,0x44,0x00,0x00};
1155 /* nopw 0(%[re]ax,%[re]ax,1) */
1156 static const unsigned char alt_6
[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1158 /* nopl 0L(%[re]ax) */
1159 static const unsigned char alt_7
[] =
1160 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1161 /* nopl 0L(%[re]ax,%[re]ax,1) */
1162 static const unsigned char alt_8
[] =
1163 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1164 /* nopw 0L(%[re]ax,%[re]ax,1) */
1165 static const unsigned char alt_9
[] =
1166 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1167 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1168 static const unsigned char alt_10
[] =
1169 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1170 static const unsigned char *const alt_patt
[] = {
1171 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1175 /* Only align for at least a positive non-zero boundary. */
1176 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1179 /* We need to decide which NOP sequence to use for 32bit and
1180 64bit. When -mtune= is used:
1182 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1183 PROCESSOR_GENERIC32, f32_patt will be used.
1184 2. For the rest, alt_patt will be used.
1186 When -mtune= isn't used, alt_patt will be used if
1187 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1190 When -march= or .arch is used, we can't use anything beyond
1191 cpu_arch_isa_flags. */
1193 if (flag_code
== CODE_16BIT
)
1197 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1199 /* Adjust jump offset. */
1200 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1203 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1204 f16_patt
[count
- 1], count
);
1208 const unsigned char *const *patt
= NULL
;
1210 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1212 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1213 switch (cpu_arch_tune
)
1215 case PROCESSOR_UNKNOWN
:
1216 /* We use cpu_arch_isa_flags to check if we SHOULD
1217 optimize with nops. */
1218 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1223 case PROCESSOR_PENTIUM4
:
1224 case PROCESSOR_NOCONA
:
1225 case PROCESSOR_CORE
:
1226 case PROCESSOR_CORE2
:
1227 case PROCESSOR_COREI7
:
1228 case PROCESSOR_L1OM
:
1229 case PROCESSOR_K1OM
:
1230 case PROCESSOR_GENERIC64
:
1232 case PROCESSOR_ATHLON
:
1234 case PROCESSOR_AMDFAM10
:
1236 case PROCESSOR_ZNVER
:
1240 case PROCESSOR_I386
:
1241 case PROCESSOR_I486
:
1242 case PROCESSOR_PENTIUM
:
1243 case PROCESSOR_PENTIUMPRO
:
1244 case PROCESSOR_IAMCU
:
1245 case PROCESSOR_GENERIC32
:
1252 switch (fragP
->tc_frag_data
.tune
)
1254 case PROCESSOR_UNKNOWN
:
1255 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1256 PROCESSOR_UNKNOWN. */
1260 case PROCESSOR_I386
:
1261 case PROCESSOR_I486
:
1262 case PROCESSOR_PENTIUM
:
1263 case PROCESSOR_IAMCU
:
1265 case PROCESSOR_ATHLON
:
1267 case PROCESSOR_AMDFAM10
:
1269 case PROCESSOR_ZNVER
:
1271 case PROCESSOR_GENERIC32
:
1272 /* We use cpu_arch_isa_flags to check if we CAN optimize
1274 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1279 case PROCESSOR_PENTIUMPRO
:
1280 case PROCESSOR_PENTIUM4
:
1281 case PROCESSOR_NOCONA
:
1282 case PROCESSOR_CORE
:
1283 case PROCESSOR_CORE2
:
1284 case PROCESSOR_COREI7
:
1285 case PROCESSOR_L1OM
:
1286 case PROCESSOR_K1OM
:
1287 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1292 case PROCESSOR_GENERIC64
:
1298 if (patt
== f32_patt
)
1300 /* If the padding is less than 15 bytes, we use the normal
1301 ones. Otherwise, we use a jump instruction and adjust
1305 /* For 64bit, the limit is 3 bytes. */
1306 if (flag_code
== CODE_64BIT
1307 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1312 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1313 patt
[count
- 1], count
);
1316 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1318 /* Adjust jump offset. */
1319 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1324 /* Maximum length of an instruction is 10 byte. If the
1325 padding is greater than 10 bytes and we don't use jump,
1326 we have to break it into smaller pieces. */
1327 int padding
= count
;
1328 while (padding
> 10)
1331 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1336 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1337 patt
[padding
- 1], padding
);
1340 fragP
->fr_var
= count
;
1344 operand_type_all_zero (const union i386_operand_type
*x
)
1346 switch (ARRAY_SIZE(x
->array
))
1355 return !x
->array
[0];
1362 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1364 switch (ARRAY_SIZE(x
->array
))
1379 operand_type_equal (const union i386_operand_type
*x
,
1380 const union i386_operand_type
*y
)
1382 switch (ARRAY_SIZE(x
->array
))
1385 if (x
->array
[2] != y
->array
[2])
1388 if (x
->array
[1] != y
->array
[1])
1391 return x
->array
[0] == y
->array
[0];
1399 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1401 switch (ARRAY_SIZE(x
->array
))
1410 return !x
->array
[0];
1417 cpu_flags_equal (const union i386_cpu_flags
*x
,
1418 const union i386_cpu_flags
*y
)
1420 switch (ARRAY_SIZE(x
->array
))
1423 if (x
->array
[2] != y
->array
[2])
1426 if (x
->array
[1] != y
->array
[1])
1429 return x
->array
[0] == y
->array
[0];
1437 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1439 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1440 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1443 static INLINE i386_cpu_flags
1444 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1446 switch (ARRAY_SIZE (x
.array
))
1449 x
.array
[2] &= y
.array
[2];
1451 x
.array
[1] &= y
.array
[1];
1453 x
.array
[0] &= y
.array
[0];
1461 static INLINE i386_cpu_flags
1462 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1464 switch (ARRAY_SIZE (x
.array
))
1467 x
.array
[2] |= y
.array
[2];
1469 x
.array
[1] |= y
.array
[1];
1471 x
.array
[0] |= y
.array
[0];
1479 static INLINE i386_cpu_flags
1480 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1482 switch (ARRAY_SIZE (x
.array
))
1485 x
.array
[2] &= ~y
.array
[2];
1487 x
.array
[1] &= ~y
.array
[1];
1489 x
.array
[0] &= ~y
.array
[0];
1498 valid_iamcu_cpu_flags (const i386_cpu_flags
*flags
)
1500 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
1502 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_COMPAT_FLAGS
;
1503 i386_cpu_flags compat_flags
;
1504 compat_flags
= cpu_flags_and_not (*flags
, iamcu_flags
);
1505 return cpu_flags_all_zero (&compat_flags
);
1511 #define CPU_FLAGS_ARCH_MATCH 0x1
1512 #define CPU_FLAGS_64BIT_MATCH 0x2
1513 #define CPU_FLAGS_AES_MATCH 0x4
1514 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1515 #define CPU_FLAGS_AVX_MATCH 0x10
1517 #define CPU_FLAGS_32BIT_MATCH \
1518 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1519 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1520 #define CPU_FLAGS_PERFECT_MATCH \
1521 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1523 /* Return CPU flags match bits. */
1526 cpu_flags_match (const insn_template
*t
)
1528 i386_cpu_flags x
= t
->cpu_flags
;
1529 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1531 x
.bitfield
.cpu64
= 0;
1532 x
.bitfield
.cpuno64
= 0;
1534 if (cpu_flags_all_zero (&x
))
1536 /* This instruction is available on all archs. */
1537 match
|= CPU_FLAGS_32BIT_MATCH
;
1541 /* This instruction is available only on some archs. */
1542 i386_cpu_flags cpu
= cpu_arch_flags
;
1544 /* Set cpuamd64 and cpuintel64 here since they may be changed by
1546 cpu_arch_flags
.bitfield
.cpuamd64
= !intel64
;
1547 cpu_arch_flags
.bitfield
.cpuintel64
= intel64
;
1549 cpu
= cpu_flags_and (x
, cpu
);
1550 if (!cpu_flags_all_zero (&cpu
))
1552 if (x
.bitfield
.cpuavx
)
1554 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1555 if (cpu
.bitfield
.cpuavx
)
1557 /* Check SSE2AVX. */
1558 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1560 match
|= (CPU_FLAGS_ARCH_MATCH
1561 | CPU_FLAGS_AVX_MATCH
);
1563 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1564 match
|= CPU_FLAGS_AES_MATCH
;
1566 if (!x
.bitfield
.cpupclmul
1567 || cpu
.bitfield
.cpupclmul
)
1568 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1572 match
|= CPU_FLAGS_ARCH_MATCH
;
1574 else if (x
.bitfield
.cpuavx512vl
)
1576 /* Match AVX512VL. */
1577 if (cpu
.bitfield
.cpuavx512vl
)
1579 /* Need another match. */
1580 cpu
.bitfield
.cpuavx512vl
= 0;
1581 if (!cpu_flags_all_zero (&cpu
))
1582 match
|= CPU_FLAGS_32BIT_MATCH
;
1584 match
|= CPU_FLAGS_ARCH_MATCH
;
1587 match
|= CPU_FLAGS_ARCH_MATCH
;
1590 match
|= CPU_FLAGS_32BIT_MATCH
;
1596 static INLINE i386_operand_type
1597 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1599 switch (ARRAY_SIZE (x
.array
))
1602 x
.array
[2] &= y
.array
[2];
1604 x
.array
[1] &= y
.array
[1];
1606 x
.array
[0] &= y
.array
[0];
1614 static INLINE i386_operand_type
1615 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1617 switch (ARRAY_SIZE (x
.array
))
1620 x
.array
[2] |= y
.array
[2];
1622 x
.array
[1] |= y
.array
[1];
1624 x
.array
[0] |= y
.array
[0];
1632 static INLINE i386_operand_type
1633 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1635 switch (ARRAY_SIZE (x
.array
))
1638 x
.array
[2] ^= y
.array
[2];
1640 x
.array
[1] ^= y
.array
[1];
1642 x
.array
[0] ^= y
.array
[0];
1650 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1651 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1652 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1653 static const i386_operand_type inoutportreg
1654 = OPERAND_TYPE_INOUTPORTREG
;
1655 static const i386_operand_type reg16_inoutportreg
1656 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1657 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1658 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1659 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1660 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1661 static const i386_operand_type anydisp
1662 = OPERAND_TYPE_ANYDISP
;
1663 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1664 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1665 static const i386_operand_type regzmm
= OPERAND_TYPE_REGZMM
;
1666 static const i386_operand_type regmask
= OPERAND_TYPE_REGMASK
;
1667 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1668 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1669 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1670 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1671 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1672 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1673 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1674 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1675 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1676 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1687 operand_type_check (i386_operand_type t
, enum operand_type c
)
1692 return (t
.bitfield
.reg8
1695 || t
.bitfield
.reg64
);
1698 return (t
.bitfield
.imm8
1702 || t
.bitfield
.imm32s
1703 || t
.bitfield
.imm64
);
1706 return (t
.bitfield
.disp8
1707 || t
.bitfield
.disp16
1708 || t
.bitfield
.disp32
1709 || t
.bitfield
.disp32s
1710 || t
.bitfield
.disp64
);
1713 return (t
.bitfield
.disp8
1714 || t
.bitfield
.disp16
1715 || t
.bitfield
.disp32
1716 || t
.bitfield
.disp32s
1717 || t
.bitfield
.disp64
1718 || t
.bitfield
.baseindex
);
1727 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1728 operand J for instruction template T. */
1731 match_reg_size (const insn_template
*t
, unsigned int j
)
1733 return !((i
.types
[j
].bitfield
.byte
1734 && !t
->operand_types
[j
].bitfield
.byte
)
1735 || (i
.types
[j
].bitfield
.word
1736 && !t
->operand_types
[j
].bitfield
.word
)
1737 || (i
.types
[j
].bitfield
.dword
1738 && !t
->operand_types
[j
].bitfield
.dword
)
1739 || (i
.types
[j
].bitfield
.qword
1740 && !t
->operand_types
[j
].bitfield
.qword
));
1743 /* Return 1 if there is no conflict in any size on operand J for
1744 instruction template T. */
1747 match_mem_size (const insn_template
*t
, unsigned int j
)
1749 return (match_reg_size (t
, j
)
1750 && !((i
.types
[j
].bitfield
.unspecified
1752 && !t
->operand_types
[j
].bitfield
.unspecified
)
1753 || (i
.types
[j
].bitfield
.fword
1754 && !t
->operand_types
[j
].bitfield
.fword
)
1755 || (i
.types
[j
].bitfield
.tbyte
1756 && !t
->operand_types
[j
].bitfield
.tbyte
)
1757 || (i
.types
[j
].bitfield
.xmmword
1758 && !t
->operand_types
[j
].bitfield
.xmmword
)
1759 || (i
.types
[j
].bitfield
.ymmword
1760 && !t
->operand_types
[j
].bitfield
.ymmword
)
1761 || (i
.types
[j
].bitfield
.zmmword
1762 && !t
->operand_types
[j
].bitfield
.zmmword
)));
1765 /* Return 1 if there is no size conflict on any operands for
1766 instruction template T. */
1769 operand_size_match (const insn_template
*t
)
1774 /* Don't check jump instructions. */
1775 if (t
->opcode_modifier
.jump
1776 || t
->opcode_modifier
.jumpbyte
1777 || t
->opcode_modifier
.jumpdword
1778 || t
->opcode_modifier
.jumpintersegment
)
1781 /* Check memory and accumulator operand size. */
1782 for (j
= 0; j
< i
.operands
; j
++)
1784 if (t
->operand_types
[j
].bitfield
.anysize
)
1787 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1793 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1802 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1805 i
.error
= operand_size_mismatch
;
1809 /* Check reverse. */
1810 gas_assert (i
.operands
== 2);
1813 for (j
= 0; j
< 2; j
++)
1815 if (t
->operand_types
[j
].bitfield
.acc
1816 && !match_reg_size (t
, j
? 0 : 1))
1819 if (i
.types
[j
].bitfield
.mem
1820 && !match_mem_size (t
, j
? 0 : 1))
1828 operand_type_match (i386_operand_type overlap
,
1829 i386_operand_type given
)
1831 i386_operand_type temp
= overlap
;
1833 temp
.bitfield
.jumpabsolute
= 0;
1834 temp
.bitfield
.unspecified
= 0;
1835 temp
.bitfield
.byte
= 0;
1836 temp
.bitfield
.word
= 0;
1837 temp
.bitfield
.dword
= 0;
1838 temp
.bitfield
.fword
= 0;
1839 temp
.bitfield
.qword
= 0;
1840 temp
.bitfield
.tbyte
= 0;
1841 temp
.bitfield
.xmmword
= 0;
1842 temp
.bitfield
.ymmword
= 0;
1843 temp
.bitfield
.zmmword
= 0;
1844 if (operand_type_all_zero (&temp
))
1847 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1848 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1852 i
.error
= operand_type_mismatch
;
1856 /* If given types g0 and g1 are registers they must be of the same type
1857 unless the expected operand type register overlap is null.
1858 Note that Acc in a template matches every size of reg. */
1861 operand_type_register_match (i386_operand_type m0
,
1862 i386_operand_type g0
,
1863 i386_operand_type t0
,
1864 i386_operand_type m1
,
1865 i386_operand_type g1
,
1866 i386_operand_type t1
)
1868 if (!operand_type_check (g0
, reg
))
1871 if (!operand_type_check (g1
, reg
))
1874 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1875 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1876 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1877 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1880 if (m0
.bitfield
.acc
)
1882 t0
.bitfield
.reg8
= 1;
1883 t0
.bitfield
.reg16
= 1;
1884 t0
.bitfield
.reg32
= 1;
1885 t0
.bitfield
.reg64
= 1;
1888 if (m1
.bitfield
.acc
)
1890 t1
.bitfield
.reg8
= 1;
1891 t1
.bitfield
.reg16
= 1;
1892 t1
.bitfield
.reg32
= 1;
1893 t1
.bitfield
.reg64
= 1;
1896 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1897 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1898 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1899 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1902 i
.error
= register_type_mismatch
;
1907 static INLINE
unsigned int
1908 register_number (const reg_entry
*r
)
1910 unsigned int nr
= r
->reg_num
;
1912 if (r
->reg_flags
& RegRex
)
1915 if (r
->reg_flags
& RegVRex
)
1921 static INLINE
unsigned int
1922 mode_from_disp_size (i386_operand_type t
)
1924 if (t
.bitfield
.disp8
|| t
.bitfield
.vec_disp8
)
1926 else if (t
.bitfield
.disp16
1927 || t
.bitfield
.disp32
1928 || t
.bitfield
.disp32s
)
1935 fits_in_signed_byte (addressT num
)
1937 return num
+ 0x80 <= 0xff;
1941 fits_in_unsigned_byte (addressT num
)
1947 fits_in_unsigned_word (addressT num
)
1949 return num
<= 0xffff;
1953 fits_in_signed_word (addressT num
)
1955 return num
+ 0x8000 <= 0xffff;
1959 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
1964 return num
+ 0x80000000 <= 0xffffffff;
1966 } /* fits_in_signed_long() */
1969 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
1974 return num
<= 0xffffffff;
1976 } /* fits_in_unsigned_long() */
1979 fits_in_vec_disp8 (offsetT num
)
1981 int shift
= i
.memshift
;
1987 mask
= (1 << shift
) - 1;
1989 /* Return 0 if NUM isn't properly aligned. */
1993 /* Check if NUM will fit in 8bit after shift. */
1994 return fits_in_signed_byte (num
>> shift
);
1998 fits_in_imm4 (offsetT num
)
2000 return (num
& 0xf) == num
;
2003 static i386_operand_type
2004 smallest_imm_type (offsetT num
)
2006 i386_operand_type t
;
2008 operand_type_set (&t
, 0);
2009 t
.bitfield
.imm64
= 1;
2011 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2013 /* This code is disabled on the 486 because all the Imm1 forms
2014 in the opcode table are slower on the i486. They're the
2015 versions with the implicitly specified single-position
2016 displacement, which has another syntax if you really want to
2018 t
.bitfield
.imm1
= 1;
2019 t
.bitfield
.imm8
= 1;
2020 t
.bitfield
.imm8s
= 1;
2021 t
.bitfield
.imm16
= 1;
2022 t
.bitfield
.imm32
= 1;
2023 t
.bitfield
.imm32s
= 1;
2025 else if (fits_in_signed_byte (num
))
2027 t
.bitfield
.imm8
= 1;
2028 t
.bitfield
.imm8s
= 1;
2029 t
.bitfield
.imm16
= 1;
2030 t
.bitfield
.imm32
= 1;
2031 t
.bitfield
.imm32s
= 1;
2033 else if (fits_in_unsigned_byte (num
))
2035 t
.bitfield
.imm8
= 1;
2036 t
.bitfield
.imm16
= 1;
2037 t
.bitfield
.imm32
= 1;
2038 t
.bitfield
.imm32s
= 1;
2040 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2042 t
.bitfield
.imm16
= 1;
2043 t
.bitfield
.imm32
= 1;
2044 t
.bitfield
.imm32s
= 1;
2046 else if (fits_in_signed_long (num
))
2048 t
.bitfield
.imm32
= 1;
2049 t
.bitfield
.imm32s
= 1;
2051 else if (fits_in_unsigned_long (num
))
2052 t
.bitfield
.imm32
= 1;
2058 offset_in_range (offsetT val
, int size
)
2064 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2065 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2066 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
2068 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
2074 /* If BFD64, sign extend val for 32bit address mode. */
2075 if (flag_code
!= CODE_64BIT
2076 || i
.prefix
[ADDR_PREFIX
])
2077 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
2078 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2081 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
2083 char buf1
[40], buf2
[40];
2085 sprint_value (buf1
, val
);
2086 sprint_value (buf2
, val
& mask
);
2087 as_warn (_("%s shortened to %s"), buf1
, buf2
);
2101 a. PREFIX_EXIST if attempting to add a prefix where one from the
2102 same class already exists.
2103 b. PREFIX_LOCK if lock prefix is added.
2104 c. PREFIX_REP if rep/repne prefix is added.
2105 d. PREFIX_OTHER if other prefix is added.
2108 static enum PREFIX_GROUP
2109 add_prefix (unsigned int prefix
)
2111 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2114 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2115 && flag_code
== CODE_64BIT
)
2117 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2118 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
2119 && (prefix
& (REX_R
| REX_X
| REX_B
))))
2130 case CS_PREFIX_OPCODE
:
2131 case DS_PREFIX_OPCODE
:
2132 case ES_PREFIX_OPCODE
:
2133 case FS_PREFIX_OPCODE
:
2134 case GS_PREFIX_OPCODE
:
2135 case SS_PREFIX_OPCODE
:
2139 case REPNE_PREFIX_OPCODE
:
2140 case REPE_PREFIX_OPCODE
:
2145 case LOCK_PREFIX_OPCODE
:
2154 case ADDR_PREFIX_OPCODE
:
2158 case DATA_PREFIX_OPCODE
:
2162 if (i
.prefix
[q
] != 0)
2170 i
.prefix
[q
] |= prefix
;
2173 as_bad (_("same type of prefix used twice"));
2179 update_code_flag (int value
, int check
)
2181 PRINTF_LIKE ((*as_error
));
2183 flag_code
= (enum flag_code
) value
;
2184 if (flag_code
== CODE_64BIT
)
2186 cpu_arch_flags
.bitfield
.cpu64
= 1;
2187 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2191 cpu_arch_flags
.bitfield
.cpu64
= 0;
2192 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2194 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
2197 as_error
= as_fatal
;
2200 (*as_error
) (_("64bit mode not supported on `%s'."),
2201 cpu_arch_name
? cpu_arch_name
: default_arch
);
2203 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2206 as_error
= as_fatal
;
2209 (*as_error
) (_("32bit mode not supported on `%s'."),
2210 cpu_arch_name
? cpu_arch_name
: default_arch
);
2212 stackop_size
= '\0';
2216 set_code_flag (int value
)
2218 update_code_flag (value
, 0);
2222 set_16bit_gcc_code_flag (int new_code_flag
)
2224 flag_code
= (enum flag_code
) new_code_flag
;
2225 if (flag_code
!= CODE_16BIT
)
2227 cpu_arch_flags
.bitfield
.cpu64
= 0;
2228 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2229 stackop_size
= LONG_MNEM_SUFFIX
;
2233 set_intel_syntax (int syntax_flag
)
2235 /* Find out if register prefixing is specified. */
2236 int ask_naked_reg
= 0;
2239 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2242 int e
= get_symbol_name (&string
);
2244 if (strcmp (string
, "prefix") == 0)
2246 else if (strcmp (string
, "noprefix") == 0)
2249 as_bad (_("bad argument to syntax directive."));
2250 (void) restore_line_pointer (e
);
2252 demand_empty_rest_of_line ();
2254 intel_syntax
= syntax_flag
;
2256 if (ask_naked_reg
== 0)
2257 allow_naked_reg
= (intel_syntax
2258 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2260 allow_naked_reg
= (ask_naked_reg
< 0);
2262 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2264 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2265 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2266 register_prefix
= allow_naked_reg
? "" : "%";
2270 set_intel_mnemonic (int mnemonic_flag
)
2272 intel_mnemonic
= mnemonic_flag
;
2276 set_allow_index_reg (int flag
)
2278 allow_index_reg
= flag
;
2282 set_check (int what
)
2284 enum check_kind
*kind
;
2289 kind
= &operand_check
;
2300 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2303 int e
= get_symbol_name (&string
);
2305 if (strcmp (string
, "none") == 0)
2307 else if (strcmp (string
, "warning") == 0)
2308 *kind
= check_warning
;
2309 else if (strcmp (string
, "error") == 0)
2310 *kind
= check_error
;
2312 as_bad (_("bad argument to %s_check directive."), str
);
2313 (void) restore_line_pointer (e
);
2316 as_bad (_("missing argument for %s_check directive"), str
);
2318 demand_empty_rest_of_line ();
2322 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2323 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2325 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2326 static const char *arch
;
2328 /* Intel LIOM is only supported on ELF. */
2334 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2335 use default_arch. */
2336 arch
= cpu_arch_name
;
2338 arch
= default_arch
;
2341 /* If we are targeting Intel MCU, we must enable it. */
2342 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_IAMCU
2343 || new_flag
.bitfield
.cpuiamcu
)
2346 /* If we are targeting Intel L1OM, we must enable it. */
2347 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2348 || new_flag
.bitfield
.cpul1om
)
2351 /* If we are targeting Intel K1OM, we must enable it. */
2352 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_K1OM
2353 || new_flag
.bitfield
.cpuk1om
)
2356 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2361 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2365 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2368 int e
= get_symbol_name (&string
);
2370 i386_cpu_flags flags
;
2372 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2374 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2376 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2380 cpu_arch_name
= cpu_arch
[j
].name
;
2381 cpu_sub_arch_name
= NULL
;
2382 cpu_arch_flags
= cpu_arch
[j
].flags
;
2383 if (flag_code
== CODE_64BIT
)
2385 cpu_arch_flags
.bitfield
.cpu64
= 1;
2386 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2390 cpu_arch_flags
.bitfield
.cpu64
= 0;
2391 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2393 cpu_arch_isa
= cpu_arch
[j
].type
;
2394 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2395 if (!cpu_arch_tune_set
)
2397 cpu_arch_tune
= cpu_arch_isa
;
2398 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2403 flags
= cpu_flags_or (cpu_arch_flags
,
2406 if (!valid_iamcu_cpu_flags (&flags
))
2407 as_fatal (_("`%s' isn't valid for Intel MCU"),
2409 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2411 if (cpu_sub_arch_name
)
2413 char *name
= cpu_sub_arch_name
;
2414 cpu_sub_arch_name
= concat (name
,
2416 (const char *) NULL
);
2420 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2421 cpu_arch_flags
= flags
;
2422 cpu_arch_isa_flags
= flags
;
2424 (void) restore_line_pointer (e
);
2425 demand_empty_rest_of_line ();
2430 if (*string
== '.' && j
>= ARRAY_SIZE (cpu_arch
))
2432 /* Disable an ISA entension. */
2433 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
2434 if (strcmp (string
+ 1, cpu_noarch
[j
].name
) == 0)
2436 flags
= cpu_flags_and_not (cpu_arch_flags
,
2437 cpu_noarch
[j
].flags
);
2438 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2440 if (cpu_sub_arch_name
)
2442 char *name
= cpu_sub_arch_name
;
2443 cpu_sub_arch_name
= concat (name
, string
,
2444 (const char *) NULL
);
2448 cpu_sub_arch_name
= xstrdup (string
);
2449 cpu_arch_flags
= flags
;
2450 cpu_arch_isa_flags
= flags
;
2452 (void) restore_line_pointer (e
);
2453 demand_empty_rest_of_line ();
2457 j
= ARRAY_SIZE (cpu_arch
);
2460 if (j
>= ARRAY_SIZE (cpu_arch
))
2461 as_bad (_("no such architecture: `%s'"), string
);
2463 *input_line_pointer
= e
;
2466 as_bad (_("missing cpu architecture"));
2468 no_cond_jump_promotion
= 0;
2469 if (*input_line_pointer
== ','
2470 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2475 ++input_line_pointer
;
2476 e
= get_symbol_name (&string
);
2478 if (strcmp (string
, "nojumps") == 0)
2479 no_cond_jump_promotion
= 1;
2480 else if (strcmp (string
, "jumps") == 0)
2483 as_bad (_("no such architecture modifier: `%s'"), string
);
2485 (void) restore_line_pointer (e
);
2488 demand_empty_rest_of_line ();
2491 enum bfd_architecture
2494 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2496 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2497 || flag_code
!= CODE_64BIT
)
2498 as_fatal (_("Intel L1OM is 64bit ELF only"));
2499 return bfd_arch_l1om
;
2501 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2503 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2504 || flag_code
!= CODE_64BIT
)
2505 as_fatal (_("Intel K1OM is 64bit ELF only"));
2506 return bfd_arch_k1om
;
2508 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2510 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2511 || flag_code
== CODE_64BIT
)
2512 as_fatal (_("Intel MCU is 32bit ELF only"));
2513 return bfd_arch_iamcu
;
2516 return bfd_arch_i386
;
2522 if (!strncmp (default_arch
, "x86_64", 6))
2524 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2526 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2527 || default_arch
[6] != '\0')
2528 as_fatal (_("Intel L1OM is 64bit ELF only"));
2529 return bfd_mach_l1om
;
2531 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
2533 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2534 || default_arch
[6] != '\0')
2535 as_fatal (_("Intel K1OM is 64bit ELF only"));
2536 return bfd_mach_k1om
;
2538 else if (default_arch
[6] == '\0')
2539 return bfd_mach_x86_64
;
2541 return bfd_mach_x64_32
;
2543 else if (!strcmp (default_arch
, "i386")
2544 || !strcmp (default_arch
, "iamcu"))
2546 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
2548 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2549 as_fatal (_("Intel MCU is 32bit ELF only"));
2550 return bfd_mach_i386_iamcu
;
2553 return bfd_mach_i386_i386
;
2556 as_fatal (_("unknown architecture"));
2562 const char *hash_err
;
2564 /* Initialize op_hash hash table. */
2565 op_hash
= hash_new ();
2568 const insn_template
*optab
;
2569 templates
*core_optab
;
2571 /* Setup for loop. */
2573 core_optab
= XNEW (templates
);
2574 core_optab
->start
= optab
;
2579 if (optab
->name
== NULL
2580 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2582 /* different name --> ship out current template list;
2583 add to hash table; & begin anew. */
2584 core_optab
->end
= optab
;
2585 hash_err
= hash_insert (op_hash
,
2587 (void *) core_optab
);
2590 as_fatal (_("can't hash %s: %s"),
2594 if (optab
->name
== NULL
)
2596 core_optab
= XNEW (templates
);
2597 core_optab
->start
= optab
;
2602 /* Initialize reg_hash hash table. */
2603 reg_hash
= hash_new ();
2605 const reg_entry
*regtab
;
2606 unsigned int regtab_size
= i386_regtab_size
;
2608 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2610 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2612 as_fatal (_("can't hash %s: %s"),
2618 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2623 for (c
= 0; c
< 256; c
++)
2628 mnemonic_chars
[c
] = c
;
2629 register_chars
[c
] = c
;
2630 operand_chars
[c
] = c
;
2632 else if (ISLOWER (c
))
2634 mnemonic_chars
[c
] = c
;
2635 register_chars
[c
] = c
;
2636 operand_chars
[c
] = c
;
2638 else if (ISUPPER (c
))
2640 mnemonic_chars
[c
] = TOLOWER (c
);
2641 register_chars
[c
] = mnemonic_chars
[c
];
2642 operand_chars
[c
] = c
;
2644 else if (c
== '{' || c
== '}')
2645 operand_chars
[c
] = c
;
2647 if (ISALPHA (c
) || ISDIGIT (c
))
2648 identifier_chars
[c
] = c
;
2651 identifier_chars
[c
] = c
;
2652 operand_chars
[c
] = c
;
2657 identifier_chars
['@'] = '@';
2660 identifier_chars
['?'] = '?';
2661 operand_chars
['?'] = '?';
2663 digit_chars
['-'] = '-';
2664 mnemonic_chars
['_'] = '_';
2665 mnemonic_chars
['-'] = '-';
2666 mnemonic_chars
['.'] = '.';
2667 identifier_chars
['_'] = '_';
2668 identifier_chars
['.'] = '.';
2670 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2671 operand_chars
[(unsigned char) *p
] = *p
;
2674 if (flag_code
== CODE_64BIT
)
2676 #if defined (OBJ_COFF) && defined (TE_PE)
2677 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2680 x86_dwarf2_return_column
= 16;
2682 x86_cie_data_alignment
= -8;
2686 x86_dwarf2_return_column
= 8;
2687 x86_cie_data_alignment
= -4;
2692 i386_print_statistics (FILE *file
)
2694 hash_print_statistics (file
, "i386 opcode", op_hash
);
2695 hash_print_statistics (file
, "i386 register", reg_hash
);
2700 /* Debugging routines for md_assemble. */
2701 static void pte (insn_template
*);
2702 static void pt (i386_operand_type
);
2703 static void pe (expressionS
*);
2704 static void ps (symbolS
*);
2707 pi (char *line
, i386_insn
*x
)
2711 fprintf (stdout
, "%s: template ", line
);
2713 fprintf (stdout
, " address: base %s index %s scale %x\n",
2714 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2715 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2716 x
->log2_scale_factor
);
2717 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2718 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2719 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2720 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2721 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2722 (x
->rex
& REX_W
) != 0,
2723 (x
->rex
& REX_R
) != 0,
2724 (x
->rex
& REX_X
) != 0,
2725 (x
->rex
& REX_B
) != 0);
2726 for (j
= 0; j
< x
->operands
; j
++)
2728 fprintf (stdout
, " #%d: ", j
+ 1);
2730 fprintf (stdout
, "\n");
2731 if (x
->types
[j
].bitfield
.reg8
2732 || x
->types
[j
].bitfield
.reg16
2733 || x
->types
[j
].bitfield
.reg32
2734 || x
->types
[j
].bitfield
.reg64
2735 || x
->types
[j
].bitfield
.regmmx
2736 || x
->types
[j
].bitfield
.regxmm
2737 || x
->types
[j
].bitfield
.regymm
2738 || x
->types
[j
].bitfield
.regzmm
2739 || x
->types
[j
].bitfield
.sreg2
2740 || x
->types
[j
].bitfield
.sreg3
2741 || x
->types
[j
].bitfield
.control
2742 || x
->types
[j
].bitfield
.debug
2743 || x
->types
[j
].bitfield
.test
)
2744 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2745 if (operand_type_check (x
->types
[j
], imm
))
2747 if (operand_type_check (x
->types
[j
], disp
))
2748 pe (x
->op
[j
].disps
);
2753 pte (insn_template
*t
)
2756 fprintf (stdout
, " %d operands ", t
->operands
);
2757 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2758 if (t
->extension_opcode
!= None
)
2759 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2760 if (t
->opcode_modifier
.d
)
2761 fprintf (stdout
, "D");
2762 if (t
->opcode_modifier
.w
)
2763 fprintf (stdout
, "W");
2764 fprintf (stdout
, "\n");
2765 for (j
= 0; j
< t
->operands
; j
++)
2767 fprintf (stdout
, " #%d type ", j
+ 1);
2768 pt (t
->operand_types
[j
]);
2769 fprintf (stdout
, "\n");
2776 fprintf (stdout
, " operation %d\n", e
->X_op
);
2777 fprintf (stdout
, " add_number %ld (%lx)\n",
2778 (long) e
->X_add_number
, (long) e
->X_add_number
);
2779 if (e
->X_add_symbol
)
2781 fprintf (stdout
, " add_symbol ");
2782 ps (e
->X_add_symbol
);
2783 fprintf (stdout
, "\n");
2787 fprintf (stdout
, " op_symbol ");
2788 ps (e
->X_op_symbol
);
2789 fprintf (stdout
, "\n");
2796 fprintf (stdout
, "%s type %s%s",
2798 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2799 segment_name (S_GET_SEGMENT (s
)));
2802 static struct type_name
2804 i386_operand_type mask
;
2807 const type_names
[] =
2809 { OPERAND_TYPE_REG8
, "r8" },
2810 { OPERAND_TYPE_REG16
, "r16" },
2811 { OPERAND_TYPE_REG32
, "r32" },
2812 { OPERAND_TYPE_REG64
, "r64" },
2813 { OPERAND_TYPE_IMM8
, "i8" },
2814 { OPERAND_TYPE_IMM8
, "i8s" },
2815 { OPERAND_TYPE_IMM16
, "i16" },
2816 { OPERAND_TYPE_IMM32
, "i32" },
2817 { OPERAND_TYPE_IMM32S
, "i32s" },
2818 { OPERAND_TYPE_IMM64
, "i64" },
2819 { OPERAND_TYPE_IMM1
, "i1" },
2820 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2821 { OPERAND_TYPE_DISP8
, "d8" },
2822 { OPERAND_TYPE_DISP16
, "d16" },
2823 { OPERAND_TYPE_DISP32
, "d32" },
2824 { OPERAND_TYPE_DISP32S
, "d32s" },
2825 { OPERAND_TYPE_DISP64
, "d64" },
2826 { OPERAND_TYPE_VEC_DISP8
, "Vector d8" },
2827 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2828 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2829 { OPERAND_TYPE_CONTROL
, "control reg" },
2830 { OPERAND_TYPE_TEST
, "test reg" },
2831 { OPERAND_TYPE_DEBUG
, "debug reg" },
2832 { OPERAND_TYPE_FLOATREG
, "FReg" },
2833 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2834 { OPERAND_TYPE_SREG2
, "SReg2" },
2835 { OPERAND_TYPE_SREG3
, "SReg3" },
2836 { OPERAND_TYPE_ACC
, "Acc" },
2837 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2838 { OPERAND_TYPE_REGMMX
, "rMMX" },
2839 { OPERAND_TYPE_REGXMM
, "rXMM" },
2840 { OPERAND_TYPE_REGYMM
, "rYMM" },
2841 { OPERAND_TYPE_REGZMM
, "rZMM" },
2842 { OPERAND_TYPE_REGMASK
, "Mask reg" },
2843 { OPERAND_TYPE_ESSEG
, "es" },
2847 pt (i386_operand_type t
)
2850 i386_operand_type a
;
2852 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2854 a
= operand_type_and (t
, type_names
[j
].mask
);
2855 if (!operand_type_all_zero (&a
))
2856 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2861 #endif /* DEBUG386 */
2863 static bfd_reloc_code_real_type
2864 reloc (unsigned int size
,
2867 bfd_reloc_code_real_type other
)
2869 if (other
!= NO_RELOC
)
2871 reloc_howto_type
*rel
;
2876 case BFD_RELOC_X86_64_GOT32
:
2877 return BFD_RELOC_X86_64_GOT64
;
2879 case BFD_RELOC_X86_64_GOTPLT64
:
2880 return BFD_RELOC_X86_64_GOTPLT64
;
2882 case BFD_RELOC_X86_64_PLTOFF64
:
2883 return BFD_RELOC_X86_64_PLTOFF64
;
2885 case BFD_RELOC_X86_64_GOTPC32
:
2886 other
= BFD_RELOC_X86_64_GOTPC64
;
2888 case BFD_RELOC_X86_64_GOTPCREL
:
2889 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2891 case BFD_RELOC_X86_64_TPOFF32
:
2892 other
= BFD_RELOC_X86_64_TPOFF64
;
2894 case BFD_RELOC_X86_64_DTPOFF32
:
2895 other
= BFD_RELOC_X86_64_DTPOFF64
;
2901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2902 if (other
== BFD_RELOC_SIZE32
)
2905 other
= BFD_RELOC_SIZE64
;
2908 as_bad (_("there are no pc-relative size relocations"));
2914 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2915 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2918 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2920 as_bad (_("unknown relocation (%u)"), other
);
2921 else if (size
!= bfd_get_reloc_size (rel
))
2922 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2923 bfd_get_reloc_size (rel
),
2925 else if (pcrel
&& !rel
->pc_relative
)
2926 as_bad (_("non-pc-relative relocation for pc-relative field"));
2927 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2929 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2931 as_bad (_("relocated field and relocation type differ in signedness"));
2940 as_bad (_("there are no unsigned pc-relative relocations"));
2943 case 1: return BFD_RELOC_8_PCREL
;
2944 case 2: return BFD_RELOC_16_PCREL
;
2945 case 4: return BFD_RELOC_32_PCREL
;
2946 case 8: return BFD_RELOC_64_PCREL
;
2948 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2955 case 4: return BFD_RELOC_X86_64_32S
;
2960 case 1: return BFD_RELOC_8
;
2961 case 2: return BFD_RELOC_16
;
2962 case 4: return BFD_RELOC_32
;
2963 case 8: return BFD_RELOC_64
;
2965 as_bad (_("cannot do %s %u byte relocation"),
2966 sign
> 0 ? "signed" : "unsigned", size
);
2972 /* Here we decide which fixups can be adjusted to make them relative to
2973 the beginning of the section instead of the symbol. Basically we need
2974 to make sure that the dynamic relocations are done correctly, so in
2975 some cases we force the original symbol to be used. */
2978 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2980 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2984 /* Don't adjust pc-relative references to merge sections in 64-bit
2986 if (use_rela_relocations
2987 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2991 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2992 and changed later by validate_fix. */
2993 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2994 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2997 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2998 for size relocations. */
2999 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3000 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3001 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3002 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
3003 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3004 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3005 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3006 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3007 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3008 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3009 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3010 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3011 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3012 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3013 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3014 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3015 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
3016 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3017 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3018 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3019 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3020 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3021 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3022 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3023 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3024 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3025 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3026 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3027 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3028 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3029 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3030 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3031 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3038 intel_float_operand (const char *mnemonic
)
3040 /* Note that the value returned is meaningful only for opcodes with (memory)
3041 operands, hence the code here is free to improperly handle opcodes that
3042 have no operands (for better performance and smaller code). */
3044 if (mnemonic
[0] != 'f')
3045 return 0; /* non-math */
3047 switch (mnemonic
[1])
3049 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3050 the fs segment override prefix not currently handled because no
3051 call path can make opcodes without operands get here */
3053 return 2 /* integer op */;
3055 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3056 return 3; /* fldcw/fldenv */
3059 if (mnemonic
[2] != 'o' /* fnop */)
3060 return 3; /* non-waiting control op */
3063 if (mnemonic
[2] == 's')
3064 return 3; /* frstor/frstpm */
3067 if (mnemonic
[2] == 'a')
3068 return 3; /* fsave */
3069 if (mnemonic
[2] == 't')
3071 switch (mnemonic
[3])
3073 case 'c': /* fstcw */
3074 case 'd': /* fstdw */
3075 case 'e': /* fstenv */
3076 case 's': /* fsts[gw] */
3082 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3083 return 0; /* fxsave/fxrstor are not really math ops */
3090 /* Build the VEX prefix. */
3093 build_vex_prefix (const insn_template
*t
)
3095 unsigned int register_specifier
;
3096 unsigned int implied_prefix
;
3097 unsigned int vector_length
;
3099 /* Check register specifier. */
3100 if (i
.vex
.register_specifier
)
3102 register_specifier
=
3103 ~register_number (i
.vex
.register_specifier
) & 0xf;
3104 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3107 register_specifier
= 0xf;
3109 /* Use 2-byte VEX prefix by swappping destination and source
3112 && i
.operands
== i
.reg_operands
3113 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3114 && i
.tm
.opcode_modifier
.s
3117 unsigned int xchg
= i
.operands
- 1;
3118 union i386_op temp_op
;
3119 i386_operand_type temp_type
;
3121 temp_type
= i
.types
[xchg
];
3122 i
.types
[xchg
] = i
.types
[0];
3123 i
.types
[0] = temp_type
;
3124 temp_op
= i
.op
[xchg
];
3125 i
.op
[xchg
] = i
.op
[0];
3128 gas_assert (i
.rm
.mode
== 3);
3132 i
.rm
.regmem
= i
.rm
.reg
;
3135 /* Use the next insn. */
3139 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3140 vector_length
= avxscalar
;
3142 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
3144 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3149 case DATA_PREFIX_OPCODE
:
3152 case REPE_PREFIX_OPCODE
:
3155 case REPNE_PREFIX_OPCODE
:
3162 /* Use 2-byte VEX prefix if possible. */
3163 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
3164 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
3165 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3167 /* 2-byte VEX prefix. */
3171 i
.vex
.bytes
[0] = 0xc5;
3173 /* Check the REX.R bit. */
3174 r
= (i
.rex
& REX_R
) ? 0 : 1;
3175 i
.vex
.bytes
[1] = (r
<< 7
3176 | register_specifier
<< 3
3177 | vector_length
<< 2
3182 /* 3-byte VEX prefix. */
3187 switch (i
.tm
.opcode_modifier
.vexopcode
)
3191 i
.vex
.bytes
[0] = 0xc4;
3195 i
.vex
.bytes
[0] = 0xc4;
3199 i
.vex
.bytes
[0] = 0xc4;
3203 i
.vex
.bytes
[0] = 0x8f;
3207 i
.vex
.bytes
[0] = 0x8f;
3211 i
.vex
.bytes
[0] = 0x8f;
3217 /* The high 3 bits of the second VEX byte are 1's compliment
3218 of RXB bits from REX. */
3219 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3221 /* Check the REX.W bit. */
3222 w
= (i
.rex
& REX_W
) ? 1 : 0;
3223 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3226 i
.vex
.bytes
[2] = (w
<< 7
3227 | register_specifier
<< 3
3228 | vector_length
<< 2
3233 /* Build the EVEX prefix. */
3236 build_evex_prefix (void)
3238 unsigned int register_specifier
;
3239 unsigned int implied_prefix
;
3241 rex_byte vrex_used
= 0;
3243 /* Check register specifier. */
3244 if (i
.vex
.register_specifier
)
3246 gas_assert ((i
.vrex
& REX_X
) == 0);
3248 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3249 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3250 register_specifier
+= 8;
3251 /* The upper 16 registers are encoded in the fourth byte of the
3253 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3254 i
.vex
.bytes
[3] = 0x8;
3255 register_specifier
= ~register_specifier
& 0xf;
3259 register_specifier
= 0xf;
3261 /* Encode upper 16 vector index register in the fourth byte of
3263 if (!(i
.vrex
& REX_X
))
3264 i
.vex
.bytes
[3] = 0x8;
3269 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
3274 case DATA_PREFIX_OPCODE
:
3277 case REPE_PREFIX_OPCODE
:
3280 case REPNE_PREFIX_OPCODE
:
3287 /* 4 byte EVEX prefix. */
3289 i
.vex
.bytes
[0] = 0x62;
3292 switch (i
.tm
.opcode_modifier
.vexopcode
)
3308 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3310 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
3312 /* The fifth bit of the second EVEX byte is 1's compliment of the
3313 REX_R bit in VREX. */
3314 if (!(i
.vrex
& REX_R
))
3315 i
.vex
.bytes
[1] |= 0x10;
3319 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3321 /* When all operands are registers, the REX_X bit in REX is not
3322 used. We reuse it to encode the upper 16 registers, which is
3323 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3324 as 1's compliment. */
3325 if ((i
.vrex
& REX_B
))
3328 i
.vex
.bytes
[1] &= ~0x40;
3332 /* EVEX instructions shouldn't need the REX prefix. */
3333 i
.vrex
&= ~vrex_used
;
3334 gas_assert (i
.vrex
== 0);
3336 /* Check the REX.W bit. */
3337 w
= (i
.rex
& REX_W
) ? 1 : 0;
3338 if (i
.tm
.opcode_modifier
.vexw
)
3340 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
3343 /* If w is not set it means we are dealing with WIG instruction. */
3346 if (evexwig
== evexw1
)
3350 /* Encode the U bit. */
3351 implied_prefix
|= 0x4;
3353 /* The third byte of the EVEX prefix. */
3354 i
.vex
.bytes
[2] = (w
<< 7 | register_specifier
<< 3 | implied_prefix
);
3356 /* The fourth byte of the EVEX prefix. */
3357 /* The zeroing-masking bit. */
3358 if (i
.mask
&& i
.mask
->zeroing
)
3359 i
.vex
.bytes
[3] |= 0x80;
3361 /* Don't always set the broadcast bit if there is no RC. */
3364 /* Encode the vector length. */
3365 unsigned int vec_length
;
3367 switch (i
.tm
.opcode_modifier
.evex
)
3369 case EVEXLIG
: /* LL' is ignored */
3370 vec_length
= evexlig
<< 5;
3373 vec_length
= 0 << 5;
3376 vec_length
= 1 << 5;
3379 vec_length
= 2 << 5;
3385 i
.vex
.bytes
[3] |= vec_length
;
3386 /* Encode the broadcast bit. */
3388 i
.vex
.bytes
[3] |= 0x10;
3392 if (i
.rounding
->type
!= saeonly
)
3393 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
->type
<< 5);
3395 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
3398 if (i
.mask
&& i
.mask
->mask
)
3399 i
.vex
.bytes
[3] |= i
.mask
->mask
->reg_num
;
3403 process_immext (void)
3407 if ((i
.tm
.cpu_flags
.bitfield
.cpusse3
|| i
.tm
.cpu_flags
.bitfield
.cpusvme
)
3410 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3411 with an opcode suffix which is coded in the same place as an
3412 8-bit immediate field would be.
3413 Here we check those operands and remove them afterwards. */
3416 for (x
= 0; x
< i
.operands
; x
++)
3417 if (register_number (i
.op
[x
].regs
) != x
)
3418 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3419 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
3425 if (i
.tm
.cpu_flags
.bitfield
.cpumwaitx
&& i
.operands
> 0)
3427 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3428 suffix which is coded in the same place as an 8-bit immediate
3430 Here we check those operands and remove them afterwards. */
3433 if (i
.operands
!= 3)
3436 for (x
= 0; x
< 2; x
++)
3437 if (register_number (i
.op
[x
].regs
) != x
)
3438 goto bad_register_operand
;
3440 /* Check for third operand for mwaitx/monitorx insn. */
3441 if (register_number (i
.op
[x
].regs
)
3442 != (x
+ (i
.tm
.extension_opcode
== 0xfb)))
3444 bad_register_operand
:
3445 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3446 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+1,
3453 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3454 which is coded in the same place as an 8-bit immediate field
3455 would be. Here we fake an 8-bit immediate operand from the
3456 opcode suffix stored in tm.extension_opcode.
3458 AVX instructions also use this encoding, for some of
3459 3 argument instructions. */
3461 gas_assert (i
.imm_operands
<= 1
3463 || ((i
.tm
.opcode_modifier
.vex
3464 || i
.tm
.opcode_modifier
.evex
)
3465 && i
.operands
<= 4)));
3467 exp
= &im_expressions
[i
.imm_operands
++];
3468 i
.op
[i
.operands
].imms
= exp
;
3469 i
.types
[i
.operands
] = imm8
;
3471 exp
->X_op
= O_constant
;
3472 exp
->X_add_number
= i
.tm
.extension_opcode
;
3473 i
.tm
.extension_opcode
= None
;
3480 switch (i
.tm
.opcode_modifier
.hleprefixok
)
3485 as_bad (_("invalid instruction `%s' after `%s'"),
3486 i
.tm
.name
, i
.hle_prefix
);
3489 if (i
.prefix
[LOCK_PREFIX
])
3491 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
3495 case HLEPrefixRelease
:
3496 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
3498 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3502 if (i
.mem_operands
== 0
3503 || !operand_type_check (i
.types
[i
.operands
- 1], anymem
))
3505 as_bad (_("memory destination needed for instruction `%s'"
3506 " after `xrelease'"), i
.tm
.name
);
3513 /* This is the guts of the machine-dependent assembler. LINE points to a
3514 machine dependent instruction. This function is supposed to emit
3515 the frags/bytes it assembles to. */
3518 md_assemble (char *line
)
3521 char mnemonic
[MAX_MNEM_SIZE
];
3522 const insn_template
*t
;
3524 /* Initialize globals. */
3525 memset (&i
, '\0', sizeof (i
));
3526 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3527 i
.reloc
[j
] = NO_RELOC
;
3528 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
3529 memset (im_expressions
, '\0', sizeof (im_expressions
));
3530 save_stack_p
= save_stack
;
3532 /* First parse an instruction mnemonic & call i386_operand for the operands.
3533 We assume that the scrubber has arranged it so that line[0] is the valid
3534 start of a (possibly prefixed) mnemonic. */
3536 line
= parse_insn (line
, mnemonic
);
3540 line
= parse_operands (line
, mnemonic
);
3545 /* Now we've parsed the mnemonic into a set of templates, and have the
3546 operands at hand. */
3548 /* All intel opcodes have reversed operands except for "bound" and
3549 "enter". We also don't reverse intersegment "jmp" and "call"
3550 instructions with 2 immediate operands so that the immediate segment
3551 precedes the offset, as it does when in AT&T mode. */
3554 && (strcmp (mnemonic
, "bound") != 0)
3555 && (strcmp (mnemonic
, "invlpga") != 0)
3556 && !(operand_type_check (i
.types
[0], imm
)
3557 && operand_type_check (i
.types
[1], imm
)))
3560 /* The order of the immediates should be reversed
3561 for 2 immediates extrq and insertq instructions */
3562 if (i
.imm_operands
== 2
3563 && (strcmp (mnemonic
, "extrq") == 0
3564 || strcmp (mnemonic
, "insertq") == 0))
3565 swap_2_operands (0, 1);
3570 /* Don't optimize displacement for movabs since it only takes 64bit
3573 && i
.disp_encoding
!= disp_encoding_32bit
3574 && (flag_code
!= CODE_64BIT
3575 || strcmp (mnemonic
, "movabs") != 0))
3578 /* Next, we find a template that matches the given insn,
3579 making sure the overlap of the given operands types is consistent
3580 with the template operand types. */
3582 if (!(t
= match_template ()))
3585 if (sse_check
!= check_none
3586 && !i
.tm
.opcode_modifier
.noavx
3587 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3588 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3589 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3590 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3591 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3592 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3594 (sse_check
== check_warning
3596 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3599 /* Zap movzx and movsx suffix. The suffix has been set from
3600 "word ptr" or "byte ptr" on the source operand in Intel syntax
3601 or extracted from mnemonic in AT&T syntax. But we'll use
3602 the destination register to choose the suffix for encoding. */
3603 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3605 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3606 there is no suffix, the default will be byte extension. */
3607 if (i
.reg_operands
!= 2
3610 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3615 if (i
.tm
.opcode_modifier
.fwait
)
3616 if (!add_prefix (FWAIT_OPCODE
))
3619 /* Check if REP prefix is OK. */
3620 if (i
.rep_prefix
&& !i
.tm
.opcode_modifier
.repprefixok
)
3622 as_bad (_("invalid instruction `%s' after `%s'"),
3623 i
.tm
.name
, i
.rep_prefix
);
3627 /* Check for lock without a lockable instruction. Destination operand
3628 must be memory unless it is xchg (0x86). */
3629 if (i
.prefix
[LOCK_PREFIX
]
3630 && (!i
.tm
.opcode_modifier
.islockable
3631 || i
.mem_operands
== 0
3632 || (i
.tm
.base_opcode
!= 0x86
3633 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3635 as_bad (_("expecting lockable instruction after `lock'"));
3639 /* Check if HLE prefix is OK. */
3640 if (i
.hle_prefix
&& !check_hle ())
3643 /* Check BND prefix. */
3644 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
3645 as_bad (_("expecting valid branch instruction after `bnd'"));
3647 if (i
.tm
.cpu_flags
.bitfield
.cpumpx
3648 && flag_code
== CODE_64BIT
3649 && i
.prefix
[ADDR_PREFIX
])
3650 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3652 /* Insert BND prefix. */
3654 && i
.tm
.opcode_modifier
.bndprefixok
3655 && !i
.prefix
[BND_PREFIX
])
3656 add_prefix (BND_PREFIX_OPCODE
);
3658 /* Check string instruction segment overrides. */
3659 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3661 if (!check_string ())
3663 i
.disp_operands
= 0;
3666 if (!process_suffix ())
3669 /* Update operand types. */
3670 for (j
= 0; j
< i
.operands
; j
++)
3671 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3673 /* Make still unresolved immediate matches conform to size of immediate
3674 given in i.suffix. */
3675 if (!finalize_imm ())
3678 if (i
.types
[0].bitfield
.imm1
)
3679 i
.imm_operands
= 0; /* kludge for shift insns. */
3681 /* We only need to check those implicit registers for instructions
3682 with 3 operands or less. */
3683 if (i
.operands
<= 3)
3684 for (j
= 0; j
< i
.operands
; j
++)
3685 if (i
.types
[j
].bitfield
.inoutportreg
3686 || i
.types
[j
].bitfield
.shiftcount
3687 || i
.types
[j
].bitfield
.acc
3688 || i
.types
[j
].bitfield
.floatacc
)
3691 /* ImmExt should be processed after SSE2AVX. */
3692 if (!i
.tm
.opcode_modifier
.sse2avx
3693 && i
.tm
.opcode_modifier
.immext
)
3696 /* For insns with operands there are more diddles to do to the opcode. */
3699 if (!process_operands ())
3702 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3704 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3705 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3708 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
3710 if (flag_code
== CODE_16BIT
)
3712 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3717 if (i
.tm
.opcode_modifier
.vex
)
3718 build_vex_prefix (t
);
3720 build_evex_prefix ();
3723 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3724 instructions may define INT_OPCODE as well, so avoid this corner
3725 case for those instructions that use MODRM. */
3726 if (i
.tm
.base_opcode
== INT_OPCODE
3727 && !i
.tm
.opcode_modifier
.modrm
3728 && i
.op
[0].imms
->X_add_number
== 3)
3730 i
.tm
.base_opcode
= INT3_OPCODE
;
3734 if ((i
.tm
.opcode_modifier
.jump
3735 || i
.tm
.opcode_modifier
.jumpbyte
3736 || i
.tm
.opcode_modifier
.jumpdword
)
3737 && i
.op
[0].disps
->X_op
== O_constant
)
3739 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3740 the absolute address given by the constant. Since ix86 jumps and
3741 calls are pc relative, we need to generate a reloc. */
3742 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3743 i
.op
[0].disps
->X_op
= O_symbol
;
3746 if (i
.tm
.opcode_modifier
.rex64
)
3749 /* For 8 bit registers we need an empty rex prefix. Also if the
3750 instruction already has a prefix, we need to convert old
3751 registers to new ones. */
3753 if ((i
.types
[0].bitfield
.reg8
3754 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3755 || (i
.types
[1].bitfield
.reg8
3756 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3757 || ((i
.types
[0].bitfield
.reg8
3758 || i
.types
[1].bitfield
.reg8
)
3763 i
.rex
|= REX_OPCODE
;
3764 for (x
= 0; x
< 2; x
++)
3766 /* Look for 8 bit operand that uses old registers. */
3767 if (i
.types
[x
].bitfield
.reg8
3768 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3770 /* In case it is "hi" register, give up. */
3771 if (i
.op
[x
].regs
->reg_num
> 3)
3772 as_bad (_("can't encode register '%s%s' in an "
3773 "instruction requiring REX prefix."),
3774 register_prefix
, i
.op
[x
].regs
->reg_name
);
3776 /* Otherwise it is equivalent to the extended register.
3777 Since the encoding doesn't change this is merely
3778 cosmetic cleanup for debug output. */
3780 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3786 add_prefix (REX_OPCODE
| i
.rex
);
3788 /* We are ready to output the insn. */
3793 parse_insn (char *line
, char *mnemonic
)
3796 char *token_start
= l
;
3799 const insn_template
*t
;
3805 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3810 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3812 as_bad (_("no such instruction: `%s'"), token_start
);
3817 if (!is_space_char (*l
)
3818 && *l
!= END_OF_INSN
3820 || (*l
!= PREFIX_SEPARATOR
3823 as_bad (_("invalid character %s in mnemonic"),
3824 output_invalid (*l
));
3827 if (token_start
== l
)
3829 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3830 as_bad (_("expecting prefix; got nothing"));
3832 as_bad (_("expecting mnemonic; got nothing"));
3836 /* Look up instruction (or prefix) via hash table. */
3837 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3839 if (*l
!= END_OF_INSN
3840 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3841 && current_templates
3842 && current_templates
->start
->opcode_modifier
.isprefix
)
3844 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3846 as_bad ((flag_code
!= CODE_64BIT
3847 ? _("`%s' is only supported in 64-bit mode")
3848 : _("`%s' is not supported in 64-bit mode")),
3849 current_templates
->start
->name
);
3852 /* If we are in 16-bit mode, do not allow addr16 or data16.
3853 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3854 if ((current_templates
->start
->opcode_modifier
.size16
3855 || current_templates
->start
->opcode_modifier
.size32
)
3856 && flag_code
!= CODE_64BIT
3857 && (current_templates
->start
->opcode_modifier
.size32
3858 ^ (flag_code
== CODE_16BIT
)))
3860 as_bad (_("redundant %s prefix"),
3861 current_templates
->start
->name
);
3864 /* Add prefix, checking for repeated prefixes. */
3865 switch (add_prefix (current_templates
->start
->base_opcode
))
3870 if (current_templates
->start
->cpu_flags
.bitfield
.cpuhle
)
3871 i
.hle_prefix
= current_templates
->start
->name
;
3872 else if (current_templates
->start
->cpu_flags
.bitfield
.cpumpx
)
3873 i
.bnd_prefix
= current_templates
->start
->name
;
3875 i
.rep_prefix
= current_templates
->start
->name
;
3880 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3887 if (!current_templates
)
3889 /* Check if we should swap operand or force 32bit displacement in
3891 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3893 else if (mnem_p
- 3 == dot_p
3896 i
.disp_encoding
= disp_encoding_8bit
;
3897 else if (mnem_p
- 4 == dot_p
3901 i
.disp_encoding
= disp_encoding_32bit
;
3906 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3909 if (!current_templates
)
3912 /* See if we can get a match by trimming off a suffix. */
3915 case WORD_MNEM_SUFFIX
:
3916 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3917 i
.suffix
= SHORT_MNEM_SUFFIX
;
3919 case BYTE_MNEM_SUFFIX
:
3920 case QWORD_MNEM_SUFFIX
:
3921 i
.suffix
= mnem_p
[-1];
3923 current_templates
= (const templates
*) hash_find (op_hash
,
3926 case SHORT_MNEM_SUFFIX
:
3927 case LONG_MNEM_SUFFIX
:
3930 i
.suffix
= mnem_p
[-1];
3932 current_templates
= (const templates
*) hash_find (op_hash
,
3941 if (intel_float_operand (mnemonic
) == 1)
3942 i
.suffix
= SHORT_MNEM_SUFFIX
;
3944 i
.suffix
= LONG_MNEM_SUFFIX
;
3946 current_templates
= (const templates
*) hash_find (op_hash
,
3951 if (!current_templates
)
3953 as_bad (_("no such instruction: `%s'"), token_start
);
3958 if (current_templates
->start
->opcode_modifier
.jump
3959 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3961 /* Check for a branch hint. We allow ",pt" and ",pn" for
3962 predict taken and predict not taken respectively.
3963 I'm not sure that branch hints actually do anything on loop
3964 and jcxz insns (JumpByte) for current Pentium4 chips. They
3965 may work in the future and it doesn't hurt to accept them
3967 if (l
[0] == ',' && l
[1] == 'p')
3971 if (!add_prefix (DS_PREFIX_OPCODE
))
3975 else if (l
[2] == 'n')
3977 if (!add_prefix (CS_PREFIX_OPCODE
))
3983 /* Any other comma loses. */
3986 as_bad (_("invalid character %s in mnemonic"),
3987 output_invalid (*l
));
3991 /* Check if instruction is supported on specified architecture. */
3993 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3995 supported
|= cpu_flags_match (t
);
3996 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
4000 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
4002 as_bad (flag_code
== CODE_64BIT
4003 ? _("`%s' is not supported in 64-bit mode")
4004 : _("`%s' is only supported in 64-bit mode"),
4005 current_templates
->start
->name
);
4008 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
4010 as_bad (_("`%s' is not supported on `%s%s'"),
4011 current_templates
->start
->name
,
4012 cpu_arch_name
? cpu_arch_name
: default_arch
,
4013 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
4018 if (!cpu_arch_flags
.bitfield
.cpui386
4019 && (flag_code
!= CODE_16BIT
))
4021 as_warn (_("use .code16 to ensure correct addressing mode"));
4028 parse_operands (char *l
, const char *mnemonic
)
4032 /* 1 if operand is pending after ','. */
4033 unsigned int expecting_operand
= 0;
4035 /* Non-zero if operand parens not balanced. */
4036 unsigned int paren_not_balanced
;
4038 while (*l
!= END_OF_INSN
)
4040 /* Skip optional white space before operand. */
4041 if (is_space_char (*l
))
4043 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
4045 as_bad (_("invalid character %s before operand %d"),
4046 output_invalid (*l
),
4050 token_start
= l
; /* After white space. */
4051 paren_not_balanced
= 0;
4052 while (paren_not_balanced
|| *l
!= ',')
4054 if (*l
== END_OF_INSN
)
4056 if (paren_not_balanced
)
4059 as_bad (_("unbalanced parenthesis in operand %d."),
4062 as_bad (_("unbalanced brackets in operand %d."),
4067 break; /* we are done */
4069 else if (!is_operand_char (*l
) && !is_space_char (*l
) && *l
!= '"')
4071 as_bad (_("invalid character %s in operand %d"),
4072 output_invalid (*l
),
4079 ++paren_not_balanced
;
4081 --paren_not_balanced
;
4086 ++paren_not_balanced
;
4088 --paren_not_balanced
;
4092 if (l
!= token_start
)
4093 { /* Yes, we've read in another operand. */
4094 unsigned int operand_ok
;
4095 this_operand
= i
.operands
++;
4096 i
.types
[this_operand
].bitfield
.unspecified
= 1;
4097 if (i
.operands
> MAX_OPERANDS
)
4099 as_bad (_("spurious operands; (%d operands/instruction max)"),
4103 /* Now parse operand adding info to 'i' as we go along. */
4104 END_STRING_AND_SAVE (l
);
4108 i386_intel_operand (token_start
,
4109 intel_float_operand (mnemonic
));
4111 operand_ok
= i386_att_operand (token_start
);
4113 RESTORE_END_STRING (l
);
4119 if (expecting_operand
)
4121 expecting_operand_after_comma
:
4122 as_bad (_("expecting operand after ','; got nothing"));
4127 as_bad (_("expecting operand before ','; got nothing"));
4132 /* Now *l must be either ',' or END_OF_INSN. */
4135 if (*++l
== END_OF_INSN
)
4137 /* Just skip it, if it's \n complain. */
4138 goto expecting_operand_after_comma
;
4140 expecting_operand
= 1;
4147 swap_2_operands (int xchg1
, int xchg2
)
4149 union i386_op temp_op
;
4150 i386_operand_type temp_type
;
4151 enum bfd_reloc_code_real temp_reloc
;
4153 temp_type
= i
.types
[xchg2
];
4154 i
.types
[xchg2
] = i
.types
[xchg1
];
4155 i
.types
[xchg1
] = temp_type
;
4156 temp_op
= i
.op
[xchg2
];
4157 i
.op
[xchg2
] = i
.op
[xchg1
];
4158 i
.op
[xchg1
] = temp_op
;
4159 temp_reloc
= i
.reloc
[xchg2
];
4160 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
4161 i
.reloc
[xchg1
] = temp_reloc
;
4165 if (i
.mask
->operand
== xchg1
)
4166 i
.mask
->operand
= xchg2
;
4167 else if (i
.mask
->operand
== xchg2
)
4168 i
.mask
->operand
= xchg1
;
4172 if (i
.broadcast
->operand
== xchg1
)
4173 i
.broadcast
->operand
= xchg2
;
4174 else if (i
.broadcast
->operand
== xchg2
)
4175 i
.broadcast
->operand
= xchg1
;
4179 if (i
.rounding
->operand
== xchg1
)
4180 i
.rounding
->operand
= xchg2
;
4181 else if (i
.rounding
->operand
== xchg2
)
4182 i
.rounding
->operand
= xchg1
;
4187 swap_operands (void)
4193 swap_2_operands (1, i
.operands
- 2);
4196 swap_2_operands (0, i
.operands
- 1);
4202 if (i
.mem_operands
== 2)
4204 const seg_entry
*temp_seg
;
4205 temp_seg
= i
.seg
[0];
4206 i
.seg
[0] = i
.seg
[1];
4207 i
.seg
[1] = temp_seg
;
4211 /* Try to ensure constant immediates are represented in the smallest
4216 char guess_suffix
= 0;
4220 guess_suffix
= i
.suffix
;
4221 else if (i
.reg_operands
)
4223 /* Figure out a suffix from the last register operand specified.
4224 We can't do this properly yet, ie. excluding InOutPortReg,
4225 but the following works for instructions with immediates.
4226 In any case, we can't set i.suffix yet. */
4227 for (op
= i
.operands
; --op
>= 0;)
4228 if (i
.types
[op
].bitfield
.reg8
)
4230 guess_suffix
= BYTE_MNEM_SUFFIX
;
4233 else if (i
.types
[op
].bitfield
.reg16
)
4235 guess_suffix
= WORD_MNEM_SUFFIX
;
4238 else if (i
.types
[op
].bitfield
.reg32
)
4240 guess_suffix
= LONG_MNEM_SUFFIX
;
4243 else if (i
.types
[op
].bitfield
.reg64
)
4245 guess_suffix
= QWORD_MNEM_SUFFIX
;
4249 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4250 guess_suffix
= WORD_MNEM_SUFFIX
;
4252 for (op
= i
.operands
; --op
>= 0;)
4253 if (operand_type_check (i
.types
[op
], imm
))
4255 switch (i
.op
[op
].imms
->X_op
)
4258 /* If a suffix is given, this operand may be shortened. */
4259 switch (guess_suffix
)
4261 case LONG_MNEM_SUFFIX
:
4262 i
.types
[op
].bitfield
.imm32
= 1;
4263 i
.types
[op
].bitfield
.imm64
= 1;
4265 case WORD_MNEM_SUFFIX
:
4266 i
.types
[op
].bitfield
.imm16
= 1;
4267 i
.types
[op
].bitfield
.imm32
= 1;
4268 i
.types
[op
].bitfield
.imm32s
= 1;
4269 i
.types
[op
].bitfield
.imm64
= 1;
4271 case BYTE_MNEM_SUFFIX
:
4272 i
.types
[op
].bitfield
.imm8
= 1;
4273 i
.types
[op
].bitfield
.imm8s
= 1;
4274 i
.types
[op
].bitfield
.imm16
= 1;
4275 i
.types
[op
].bitfield
.imm32
= 1;
4276 i
.types
[op
].bitfield
.imm32s
= 1;
4277 i
.types
[op
].bitfield
.imm64
= 1;
4281 /* If this operand is at most 16 bits, convert it
4282 to a signed 16 bit number before trying to see
4283 whether it will fit in an even smaller size.
4284 This allows a 16-bit operand such as $0xffe0 to
4285 be recognised as within Imm8S range. */
4286 if ((i
.types
[op
].bitfield
.imm16
)
4287 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
4289 i
.op
[op
].imms
->X_add_number
=
4290 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
4293 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4294 if ((i
.types
[op
].bitfield
.imm32
)
4295 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
4298 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
4299 ^ ((offsetT
) 1 << 31))
4300 - ((offsetT
) 1 << 31));
4304 = operand_type_or (i
.types
[op
],
4305 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
4307 /* We must avoid matching of Imm32 templates when 64bit
4308 only immediate is available. */
4309 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
4310 i
.types
[op
].bitfield
.imm32
= 0;
4317 /* Symbols and expressions. */
4319 /* Convert symbolic operand to proper sizes for matching, but don't
4320 prevent matching a set of insns that only supports sizes other
4321 than those matching the insn suffix. */
4323 i386_operand_type mask
, allowed
;
4324 const insn_template
*t
;
4326 operand_type_set (&mask
, 0);
4327 operand_type_set (&allowed
, 0);
4329 for (t
= current_templates
->start
;
4330 t
< current_templates
->end
;
4332 allowed
= operand_type_or (allowed
,
4333 t
->operand_types
[op
]);
4334 switch (guess_suffix
)
4336 case QWORD_MNEM_SUFFIX
:
4337 mask
.bitfield
.imm64
= 1;
4338 mask
.bitfield
.imm32s
= 1;
4340 case LONG_MNEM_SUFFIX
:
4341 mask
.bitfield
.imm32
= 1;
4343 case WORD_MNEM_SUFFIX
:
4344 mask
.bitfield
.imm16
= 1;
4346 case BYTE_MNEM_SUFFIX
:
4347 mask
.bitfield
.imm8
= 1;
4352 allowed
= operand_type_and (mask
, allowed
);
4353 if (!operand_type_all_zero (&allowed
))
4354 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
4361 /* Try to use the smallest displacement type too. */
4363 optimize_disp (void)
4367 for (op
= i
.operands
; --op
>= 0;)
4368 if (operand_type_check (i
.types
[op
], disp
))
4370 if (i
.op
[op
].disps
->X_op
== O_constant
)
4372 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
4374 if (i
.types
[op
].bitfield
.disp16
4375 && (op_disp
& ~(offsetT
) 0xffff) == 0)
4377 /* If this operand is at most 16 bits, convert
4378 to a signed 16 bit number and don't use 64bit
4380 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
4381 i
.types
[op
].bitfield
.disp64
= 0;
4384 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4385 if (i
.types
[op
].bitfield
.disp32
4386 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
4388 /* If this operand is at most 32 bits, convert
4389 to a signed 32 bit number and don't use 64bit
4391 op_disp
&= (((offsetT
) 2 << 31) - 1);
4392 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
4393 i
.types
[op
].bitfield
.disp64
= 0;
4396 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
4398 i
.types
[op
].bitfield
.disp8
= 0;
4399 i
.types
[op
].bitfield
.disp16
= 0;
4400 i
.types
[op
].bitfield
.disp32
= 0;
4401 i
.types
[op
].bitfield
.disp32s
= 0;
4402 i
.types
[op
].bitfield
.disp64
= 0;
4406 else if (flag_code
== CODE_64BIT
)
4408 if (fits_in_signed_long (op_disp
))
4410 i
.types
[op
].bitfield
.disp64
= 0;
4411 i
.types
[op
].bitfield
.disp32s
= 1;
4413 if (i
.prefix
[ADDR_PREFIX
]
4414 && fits_in_unsigned_long (op_disp
))
4415 i
.types
[op
].bitfield
.disp32
= 1;
4417 if ((i
.types
[op
].bitfield
.disp32
4418 || i
.types
[op
].bitfield
.disp32s
4419 || i
.types
[op
].bitfield
.disp16
)
4420 && fits_in_signed_byte (op_disp
))
4421 i
.types
[op
].bitfield
.disp8
= 1;
4423 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
4424 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
4426 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
4427 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
4428 i
.types
[op
].bitfield
.disp8
= 0;
4429 i
.types
[op
].bitfield
.disp16
= 0;
4430 i
.types
[op
].bitfield
.disp32
= 0;
4431 i
.types
[op
].bitfield
.disp32s
= 0;
4432 i
.types
[op
].bitfield
.disp64
= 0;
4435 /* We only support 64bit displacement on constants. */
4436 i
.types
[op
].bitfield
.disp64
= 0;
4440 /* Check if operands are valid for the instruction. */
4443 check_VecOperands (const insn_template
*t
)
4447 /* Without VSIB byte, we can't have a vector register for index. */
4448 if (!t
->opcode_modifier
.vecsib
4450 && (i
.index_reg
->reg_type
.bitfield
.regxmm
4451 || i
.index_reg
->reg_type
.bitfield
.regymm
4452 || i
.index_reg
->reg_type
.bitfield
.regzmm
))
4454 i
.error
= unsupported_vector_index_register
;
4458 /* Check if default mask is allowed. */
4459 if (t
->opcode_modifier
.nodefmask
4460 && (!i
.mask
|| i
.mask
->mask
->reg_num
== 0))
4462 i
.error
= no_default_mask
;
4466 /* For VSIB byte, we need a vector register for index, and all vector
4467 registers must be distinct. */
4468 if (t
->opcode_modifier
.vecsib
)
4471 || !((t
->opcode_modifier
.vecsib
== VecSIB128
4472 && i
.index_reg
->reg_type
.bitfield
.regxmm
)
4473 || (t
->opcode_modifier
.vecsib
== VecSIB256
4474 && i
.index_reg
->reg_type
.bitfield
.regymm
)
4475 || (t
->opcode_modifier
.vecsib
== VecSIB512
4476 && i
.index_reg
->reg_type
.bitfield
.regzmm
)))
4478 i
.error
= invalid_vsib_address
;
4482 gas_assert (i
.reg_operands
== 2 || i
.mask
);
4483 if (i
.reg_operands
== 2 && !i
.mask
)
4485 gas_assert (i
.types
[0].bitfield
.regxmm
4486 || i
.types
[0].bitfield
.regymm
);
4487 gas_assert (i
.types
[2].bitfield
.regxmm
4488 || i
.types
[2].bitfield
.regymm
);
4489 if (operand_check
== check_none
)
4491 if (register_number (i
.op
[0].regs
)
4492 != register_number (i
.index_reg
)
4493 && register_number (i
.op
[2].regs
)
4494 != register_number (i
.index_reg
)
4495 && register_number (i
.op
[0].regs
)
4496 != register_number (i
.op
[2].regs
))
4498 if (operand_check
== check_error
)
4500 i
.error
= invalid_vector_register_set
;
4503 as_warn (_("mask, index, and destination registers should be distinct"));
4505 else if (i
.reg_operands
== 1 && i
.mask
)
4507 if ((i
.types
[1].bitfield
.regymm
4508 || i
.types
[1].bitfield
.regzmm
)
4509 && (register_number (i
.op
[1].regs
)
4510 == register_number (i
.index_reg
)))
4512 if (operand_check
== check_error
)
4514 i
.error
= invalid_vector_register_set
;
4517 if (operand_check
!= check_none
)
4518 as_warn (_("index and destination registers should be distinct"));
4523 /* Check if broadcast is supported by the instruction and is applied
4524 to the memory operand. */
4527 int broadcasted_opnd_size
;
4529 /* Check if specified broadcast is supported in this instruction,
4530 and it's applied to memory operand of DWORD or QWORD type,
4531 depending on VecESize. */
4532 if (i
.broadcast
->type
!= t
->opcode_modifier
.broadcast
4533 || !i
.types
[i
.broadcast
->operand
].bitfield
.mem
4534 || (t
->opcode_modifier
.vecesize
== 0
4535 && !i
.types
[i
.broadcast
->operand
].bitfield
.dword
4536 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
)
4537 || (t
->opcode_modifier
.vecesize
== 1
4538 && !i
.types
[i
.broadcast
->operand
].bitfield
.qword
4539 && !i
.types
[i
.broadcast
->operand
].bitfield
.unspecified
))
4542 broadcasted_opnd_size
= t
->opcode_modifier
.vecesize
? 64 : 32;
4543 if (i
.broadcast
->type
== BROADCAST_1TO16
)
4544 broadcasted_opnd_size
<<= 4; /* Broadcast 1to16. */
4545 else if (i
.broadcast
->type
== BROADCAST_1TO8
)
4546 broadcasted_opnd_size
<<= 3; /* Broadcast 1to8. */
4547 else if (i
.broadcast
->type
== BROADCAST_1TO4
)
4548 broadcasted_opnd_size
<<= 2; /* Broadcast 1to4. */
4549 else if (i
.broadcast
->type
== BROADCAST_1TO2
)
4550 broadcasted_opnd_size
<<= 1; /* Broadcast 1to2. */
4554 if ((broadcasted_opnd_size
== 256
4555 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.ymmword
)
4556 || (broadcasted_opnd_size
== 512
4557 && !t
->operand_types
[i
.broadcast
->operand
].bitfield
.zmmword
))
4560 i
.error
= unsupported_broadcast
;
4564 /* If broadcast is supported in this instruction, we need to check if
4565 operand of one-element size isn't specified without broadcast. */
4566 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
4568 /* Find memory operand. */
4569 for (op
= 0; op
< i
.operands
; op
++)
4570 if (operand_type_check (i
.types
[op
], anymem
))
4572 gas_assert (op
< i
.operands
);
4573 /* Check size of the memory operand. */
4574 if ((t
->opcode_modifier
.vecesize
== 0
4575 && i
.types
[op
].bitfield
.dword
)
4576 || (t
->opcode_modifier
.vecesize
== 1
4577 && i
.types
[op
].bitfield
.qword
))
4579 i
.error
= broadcast_needed
;
4584 /* Check if requested masking is supported. */
4586 && (!t
->opcode_modifier
.masking
4588 && t
->opcode_modifier
.masking
== MERGING_MASKING
)))
4590 i
.error
= unsupported_masking
;
4594 /* Check if masking is applied to dest operand. */
4595 if (i
.mask
&& (i
.mask
->operand
!= (int) (i
.operands
- 1)))
4597 i
.error
= mask_not_on_destination
;
4604 if ((i
.rounding
->type
!= saeonly
4605 && !t
->opcode_modifier
.staticrounding
)
4606 || (i
.rounding
->type
== saeonly
4607 && (t
->opcode_modifier
.staticrounding
4608 || !t
->opcode_modifier
.sae
)))
4610 i
.error
= unsupported_rc_sae
;
4613 /* If the instruction has several immediate operands and one of
4614 them is rounding, the rounding operand should be the last
4615 immediate operand. */
4616 if (i
.imm_operands
> 1
4617 && i
.rounding
->operand
!= (int) (i
.imm_operands
- 1))
4619 i
.error
= rc_sae_operand_not_last_imm
;
4624 /* Check vector Disp8 operand. */
4625 if (t
->opcode_modifier
.disp8memshift
)
4628 i
.memshift
= t
->opcode_modifier
.vecesize
? 3 : 2;
4630 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
4632 for (op
= 0; op
< i
.operands
; op
++)
4633 if (operand_type_check (i
.types
[op
], disp
)
4634 && i
.op
[op
].disps
->X_op
== O_constant
)
4636 offsetT value
= i
.op
[op
].disps
->X_add_number
;
4638 = (i
.disp_encoding
!= disp_encoding_32bit
4639 && fits_in_vec_disp8 (value
));
4640 if (t
->operand_types
[op
].bitfield
.vec_disp8
)
4643 i
.types
[op
].bitfield
.vec_disp8
= 1;
4646 /* Vector insn can only have Vec_Disp8/Disp32 in
4647 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4649 i
.types
[op
].bitfield
.disp8
= 0;
4650 if (flag_code
!= CODE_16BIT
)
4651 i
.types
[op
].bitfield
.disp16
= 0;
4654 else if (flag_code
!= CODE_16BIT
)
4656 /* One form of this instruction supports vector Disp8.
4657 Try vector Disp8 if we need to use Disp32. */
4658 if (vec_disp8_ok
&& !fits_in_signed_byte (value
))
4660 i
.error
= try_vector_disp8
;
4672 /* Check if operands are valid for the instruction. Update VEX
4676 VEX_check_operands (const insn_template
*t
)
4678 /* VREX is only valid with EVEX prefix. */
4679 if (i
.need_vrex
&& !t
->opcode_modifier
.evex
)
4681 i
.error
= invalid_register_operand
;
4685 if (!t
->opcode_modifier
.vex
)
4688 /* Only check VEX_Imm4, which must be the first operand. */
4689 if (t
->operand_types
[0].bitfield
.vec_imm4
)
4691 if (i
.op
[0].imms
->X_op
!= O_constant
4692 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
4698 /* Turn off Imm8 so that update_imm won't complain. */
4699 i
.types
[0] = vec_imm4
;
4705 static const insn_template
*
4706 match_template (void)
4708 /* Points to template once we've found it. */
4709 const insn_template
*t
;
4710 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
4711 i386_operand_type overlap4
;
4712 unsigned int found_reverse_match
;
4713 i386_opcode_modifier suffix_check
;
4714 i386_operand_type operand_types
[MAX_OPERANDS
];
4715 int addr_prefix_disp
;
4717 unsigned int found_cpu_match
;
4718 unsigned int check_register
;
4719 enum i386_error specific_error
= 0;
4721 #if MAX_OPERANDS != 5
4722 # error "MAX_OPERANDS must be 5."
4725 found_reverse_match
= 0;
4726 addr_prefix_disp
= -1;
4728 memset (&suffix_check
, 0, sizeof (suffix_check
));
4729 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4730 suffix_check
.no_bsuf
= 1;
4731 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4732 suffix_check
.no_wsuf
= 1;
4733 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
4734 suffix_check
.no_ssuf
= 1;
4735 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4736 suffix_check
.no_lsuf
= 1;
4737 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4738 suffix_check
.no_qsuf
= 1;
4739 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
4740 suffix_check
.no_ldsuf
= 1;
4742 /* Must have right number of operands. */
4743 i
.error
= number_of_operands_mismatch
;
4745 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
4747 addr_prefix_disp
= -1;
4749 if (i
.operands
!= t
->operands
)
4752 /* Check processor support. */
4753 i
.error
= unsupported
;
4754 found_cpu_match
= (cpu_flags_match (t
)
4755 == CPU_FLAGS_PERFECT_MATCH
);
4756 if (!found_cpu_match
)
4759 /* Check old gcc support. */
4760 i
.error
= old_gcc_only
;
4761 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
4764 /* Check AT&T mnemonic. */
4765 i
.error
= unsupported_with_intel_mnemonic
;
4766 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
4769 /* Check AT&T/Intel syntax. */
4770 i
.error
= unsupported_syntax
;
4771 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
4772 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
4775 /* Check the suffix, except for some instructions in intel mode. */
4776 i
.error
= invalid_instruction_suffix
;
4777 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
4778 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
4779 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
4780 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
4781 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
4782 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
4783 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
4786 if (!operand_size_match (t
))
4789 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4790 operand_types
[j
] = t
->operand_types
[j
];
4792 /* In general, don't allow 64-bit operands in 32-bit mode. */
4793 if (i
.suffix
== QWORD_MNEM_SUFFIX
4794 && flag_code
!= CODE_64BIT
4796 ? (!t
->opcode_modifier
.ignoresize
4797 && !intel_float_operand (t
->name
))
4798 : intel_float_operand (t
->name
) != 2)
4799 && ((!operand_types
[0].bitfield
.regmmx
4800 && !operand_types
[0].bitfield
.regxmm
4801 && !operand_types
[0].bitfield
.regymm
4802 && !operand_types
[0].bitfield
.regzmm
)
4803 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4804 && operand_types
[t
->operands
> 1].bitfield
.regxmm
4805 && operand_types
[t
->operands
> 1].bitfield
.regymm
4806 && operand_types
[t
->operands
> 1].bitfield
.regzmm
))
4807 && (t
->base_opcode
!= 0x0fc7
4808 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
4811 /* In general, don't allow 32-bit operands on pre-386. */
4812 else if (i
.suffix
== LONG_MNEM_SUFFIX
4813 && !cpu_arch_flags
.bitfield
.cpui386
4815 ? (!t
->opcode_modifier
.ignoresize
4816 && !intel_float_operand (t
->name
))
4817 : intel_float_operand (t
->name
) != 2)
4818 && ((!operand_types
[0].bitfield
.regmmx
4819 && !operand_types
[0].bitfield
.regxmm
)
4820 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
4821 && operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
4824 /* Do not verify operands when there are none. */
4828 /* We've found a match; break out of loop. */
4832 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4833 into Disp32/Disp16/Disp32 operand. */
4834 if (i
.prefix
[ADDR_PREFIX
] != 0)
4836 /* There should be only one Disp operand. */
4840 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4842 if (operand_types
[j
].bitfield
.disp16
)
4844 addr_prefix_disp
= j
;
4845 operand_types
[j
].bitfield
.disp32
= 1;
4846 operand_types
[j
].bitfield
.disp16
= 0;
4852 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4854 if (operand_types
[j
].bitfield
.disp32
)
4856 addr_prefix_disp
= j
;
4857 operand_types
[j
].bitfield
.disp32
= 0;
4858 operand_types
[j
].bitfield
.disp16
= 1;
4864 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4866 if (operand_types
[j
].bitfield
.disp64
)
4868 addr_prefix_disp
= j
;
4869 operand_types
[j
].bitfield
.disp64
= 0;
4870 operand_types
[j
].bitfield
.disp32
= 1;
4878 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4879 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
&& t
->base_opcode
== 0xa0)
4882 /* We check register size if needed. */
4883 check_register
= t
->opcode_modifier
.checkregsize
;
4884 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4885 switch (t
->operands
)
4888 if (!operand_type_match (overlap0
, i
.types
[0]))
4892 /* xchg %eax, %eax is a special case. It is an aliase for nop
4893 only in 32bit mode and we can use opcode 0x90. In 64bit
4894 mode, we can't use 0x90 for xchg %eax, %eax since it should
4895 zero-extend %eax to %rax. */
4896 if (flag_code
== CODE_64BIT
4897 && t
->base_opcode
== 0x90
4898 && operand_type_equal (&i
.types
[0], &acc32
)
4899 && operand_type_equal (&i
.types
[1], &acc32
))
4903 /* If we swap operand in encoding, we either match
4904 the next one or reverse direction of operands. */
4905 if (t
->opcode_modifier
.s
)
4907 else if (t
->opcode_modifier
.d
)
4912 /* If we swap operand in encoding, we match the next one. */
4913 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4917 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4918 if (!operand_type_match (overlap0
, i
.types
[0])
4919 || !operand_type_match (overlap1
, i
.types
[1])
4921 && !operand_type_register_match (overlap0
, i
.types
[0],
4923 overlap1
, i
.types
[1],
4926 /* Check if other direction is valid ... */
4927 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4931 /* Try reversing direction of operands. */
4932 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4933 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4934 if (!operand_type_match (overlap0
, i
.types
[0])
4935 || !operand_type_match (overlap1
, i
.types
[1])
4937 && !operand_type_register_match (overlap0
,
4944 /* Does not match either direction. */
4947 /* found_reverse_match holds which of D or FloatDR
4949 if (t
->opcode_modifier
.d
)
4950 found_reverse_match
= Opcode_D
;
4951 else if (t
->opcode_modifier
.floatd
)
4952 found_reverse_match
= Opcode_FloatD
;
4954 found_reverse_match
= 0;
4955 if (t
->opcode_modifier
.floatr
)
4956 found_reverse_match
|= Opcode_FloatR
;
4960 /* Found a forward 2 operand match here. */
4961 switch (t
->operands
)
4964 overlap4
= operand_type_and (i
.types
[4],
4967 overlap3
= operand_type_and (i
.types
[3],
4970 overlap2
= operand_type_and (i
.types
[2],
4975 switch (t
->operands
)
4978 if (!operand_type_match (overlap4
, i
.types
[4])
4979 || !operand_type_register_match (overlap3
,
4987 if (!operand_type_match (overlap3
, i
.types
[3])
4989 && !operand_type_register_match (overlap2
,
4997 /* Here we make use of the fact that there are no
4998 reverse match 3 operand instructions, and all 3
4999 operand instructions only need to be checked for
5000 register consistency between operands 2 and 3. */
5001 if (!operand_type_match (overlap2
, i
.types
[2])
5003 && !operand_type_register_match (overlap1
,
5013 /* Found either forward/reverse 2, 3 or 4 operand match here:
5014 slip through to break. */
5016 if (!found_cpu_match
)
5018 found_reverse_match
= 0;
5022 /* Check if vector and VEX operands are valid. */
5023 if (check_VecOperands (t
) || VEX_check_operands (t
))
5025 specific_error
= i
.error
;
5029 /* We've found a match; break out of loop. */
5033 if (t
== current_templates
->end
)
5035 /* We found no match. */
5036 const char *err_msg
;
5037 switch (specific_error
? specific_error
: i
.error
)
5041 case operand_size_mismatch
:
5042 err_msg
= _("operand size mismatch");
5044 case operand_type_mismatch
:
5045 err_msg
= _("operand type mismatch");
5047 case register_type_mismatch
:
5048 err_msg
= _("register type mismatch");
5050 case number_of_operands_mismatch
:
5051 err_msg
= _("number of operands mismatch");
5053 case invalid_instruction_suffix
:
5054 err_msg
= _("invalid instruction suffix");
5057 err_msg
= _("constant doesn't fit in 4 bits");
5060 err_msg
= _("only supported with old gcc");
5062 case unsupported_with_intel_mnemonic
:
5063 err_msg
= _("unsupported with Intel mnemonic");
5065 case unsupported_syntax
:
5066 err_msg
= _("unsupported syntax");
5069 as_bad (_("unsupported instruction `%s'"),
5070 current_templates
->start
->name
);
5072 case invalid_vsib_address
:
5073 err_msg
= _("invalid VSIB address");
5075 case invalid_vector_register_set
:
5076 err_msg
= _("mask, index, and destination registers must be distinct");
5078 case unsupported_vector_index_register
:
5079 err_msg
= _("unsupported vector index register");
5081 case unsupported_broadcast
:
5082 err_msg
= _("unsupported broadcast");
5084 case broadcast_not_on_src_operand
:
5085 err_msg
= _("broadcast not on source memory operand");
5087 case broadcast_needed
:
5088 err_msg
= _("broadcast is needed for operand of such type");
5090 case unsupported_masking
:
5091 err_msg
= _("unsupported masking");
5093 case mask_not_on_destination
:
5094 err_msg
= _("mask not on destination operand");
5096 case no_default_mask
:
5097 err_msg
= _("default mask isn't allowed");
5099 case unsupported_rc_sae
:
5100 err_msg
= _("unsupported static rounding/sae");
5102 case rc_sae_operand_not_last_imm
:
5104 err_msg
= _("RC/SAE operand must precede immediate operands");
5106 err_msg
= _("RC/SAE operand must follow immediate operands");
5108 case invalid_register_operand
:
5109 err_msg
= _("invalid register operand");
5112 as_bad (_("%s for `%s'"), err_msg
,
5113 current_templates
->start
->name
);
5117 if (!quiet_warnings
)
5120 && (i
.types
[0].bitfield
.jumpabsolute
5121 != operand_types
[0].bitfield
.jumpabsolute
))
5123 as_warn (_("indirect %s without `*'"), t
->name
);
5126 if (t
->opcode_modifier
.isprefix
5127 && t
->opcode_modifier
.ignoresize
)
5129 /* Warn them that a data or address size prefix doesn't
5130 affect assembly of the next line of code. */
5131 as_warn (_("stand-alone `%s' prefix"), t
->name
);
5135 /* Copy the template we found. */
5138 if (addr_prefix_disp
!= -1)
5139 i
.tm
.operand_types
[addr_prefix_disp
]
5140 = operand_types
[addr_prefix_disp
];
5142 if (found_reverse_match
)
5144 /* If we found a reverse match we must alter the opcode
5145 direction bit. found_reverse_match holds bits to change
5146 (different for int & float insns). */
5148 i
.tm
.base_opcode
^= found_reverse_match
;
5150 i
.tm
.operand_types
[0] = operand_types
[1];
5151 i
.tm
.operand_types
[1] = operand_types
[0];
5160 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
5161 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
5163 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
5165 as_bad (_("`%s' operand %d must use `%ses' segment"),
5171 /* There's only ever one segment override allowed per instruction.
5172 This instruction possibly has a legal segment override on the
5173 second operand, so copy the segment to where non-string
5174 instructions store it, allowing common code. */
5175 i
.seg
[0] = i
.seg
[1];
5177 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
5179 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
5181 as_bad (_("`%s' operand %d must use `%ses' segment"),
5192 process_suffix (void)
5194 /* If matched instruction specifies an explicit instruction mnemonic
5196 if (i
.tm
.opcode_modifier
.size16
)
5197 i
.suffix
= WORD_MNEM_SUFFIX
;
5198 else if (i
.tm
.opcode_modifier
.size32
)
5199 i
.suffix
= LONG_MNEM_SUFFIX
;
5200 else if (i
.tm
.opcode_modifier
.size64
)
5201 i
.suffix
= QWORD_MNEM_SUFFIX
;
5202 else if (i
.reg_operands
)
5204 /* If there's no instruction mnemonic suffix we try to invent one
5205 based on register operands. */
5208 /* We take i.suffix from the last register operand specified,
5209 Destination register type is more significant than source
5210 register type. crc32 in SSE4.2 prefers source register
5212 if (i
.tm
.base_opcode
== 0xf20f38f1)
5214 if (i
.types
[0].bitfield
.reg16
)
5215 i
.suffix
= WORD_MNEM_SUFFIX
;
5216 else if (i
.types
[0].bitfield
.reg32
)
5217 i
.suffix
= LONG_MNEM_SUFFIX
;
5218 else if (i
.types
[0].bitfield
.reg64
)
5219 i
.suffix
= QWORD_MNEM_SUFFIX
;
5221 else if (i
.tm
.base_opcode
== 0xf20f38f0)
5223 if (i
.types
[0].bitfield
.reg8
)
5224 i
.suffix
= BYTE_MNEM_SUFFIX
;
5231 if (i
.tm
.base_opcode
== 0xf20f38f1
5232 || i
.tm
.base_opcode
== 0xf20f38f0)
5234 /* We have to know the operand size for crc32. */
5235 as_bad (_("ambiguous memory operand size for `%s`"),
5240 for (op
= i
.operands
; --op
>= 0;)
5241 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5243 if (i
.types
[op
].bitfield
.reg8
)
5245 i
.suffix
= BYTE_MNEM_SUFFIX
;
5248 else if (i
.types
[op
].bitfield
.reg16
)
5250 i
.suffix
= WORD_MNEM_SUFFIX
;
5253 else if (i
.types
[op
].bitfield
.reg32
)
5255 i
.suffix
= LONG_MNEM_SUFFIX
;
5258 else if (i
.types
[op
].bitfield
.reg64
)
5260 i
.suffix
= QWORD_MNEM_SUFFIX
;
5266 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5269 && i
.tm
.opcode_modifier
.ignoresize
5270 && i
.tm
.opcode_modifier
.no_bsuf
)
5272 else if (!check_byte_reg ())
5275 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
5278 && i
.tm
.opcode_modifier
.ignoresize
5279 && i
.tm
.opcode_modifier
.no_lsuf
)
5281 else if (!check_long_reg ())
5284 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5287 && i
.tm
.opcode_modifier
.ignoresize
5288 && i
.tm
.opcode_modifier
.no_qsuf
)
5290 else if (!check_qword_reg ())
5293 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5296 && i
.tm
.opcode_modifier
.ignoresize
5297 && i
.tm
.opcode_modifier
.no_wsuf
)
5299 else if (!check_word_reg ())
5302 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
5303 || i
.suffix
== YMMWORD_MNEM_SUFFIX
5304 || i
.suffix
== ZMMWORD_MNEM_SUFFIX
)
5306 /* Skip if the instruction has x/y/z suffix. match_template
5307 should check if it is a valid suffix. */
5309 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
5310 /* Do nothing if the instruction is going to ignore the prefix. */
5315 else if (i
.tm
.opcode_modifier
.defaultsize
5317 /* exclude fldenv/frstor/fsave/fstenv */
5318 && i
.tm
.opcode_modifier
.no_ssuf
)
5320 i
.suffix
= stackop_size
;
5322 else if (intel_syntax
5324 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
5325 || i
.tm
.opcode_modifier
.jumpbyte
5326 || i
.tm
.opcode_modifier
.jumpintersegment
5327 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
5328 && i
.tm
.extension_opcode
<= 3)))
5333 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5335 i
.suffix
= QWORD_MNEM_SUFFIX
;
5339 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5340 i
.suffix
= LONG_MNEM_SUFFIX
;
5343 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5344 i
.suffix
= WORD_MNEM_SUFFIX
;
5353 if (i
.tm
.opcode_modifier
.w
)
5355 as_bad (_("no instruction mnemonic suffix given and "
5356 "no register operands; can't size instruction"));
5362 unsigned int suffixes
;
5364 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
5365 if (!i
.tm
.opcode_modifier
.no_wsuf
)
5367 if (!i
.tm
.opcode_modifier
.no_lsuf
)
5369 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
5371 if (!i
.tm
.opcode_modifier
.no_ssuf
)
5373 if (!i
.tm
.opcode_modifier
.no_qsuf
)
5376 /* There are more than suffix matches. */
5377 if (i
.tm
.opcode_modifier
.w
5378 || ((suffixes
& (suffixes
- 1))
5379 && !i
.tm
.opcode_modifier
.defaultsize
5380 && !i
.tm
.opcode_modifier
.ignoresize
))
5382 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
5388 /* Change the opcode based on the operand size given by i.suffix;
5389 We don't need to change things for byte insns. */
5392 && i
.suffix
!= BYTE_MNEM_SUFFIX
5393 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
5394 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
5395 && i
.suffix
!= ZMMWORD_MNEM_SUFFIX
)
5397 /* It's not a byte, select word/dword operation. */
5398 if (i
.tm
.opcode_modifier
.w
)
5400 if (i
.tm
.opcode_modifier
.shortform
)
5401 i
.tm
.base_opcode
|= 8;
5403 i
.tm
.base_opcode
|= 1;
5406 /* Now select between word & dword operations via the operand
5407 size prefix, except for instructions that will ignore this
5409 if (i
.tm
.opcode_modifier
.addrprefixop0
)
5411 /* The address size override prefix changes the size of the
5413 if ((flag_code
== CODE_32BIT
5414 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
5415 || (flag_code
!= CODE_32BIT
5416 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
5417 if (!add_prefix (ADDR_PREFIX_OPCODE
))
5420 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
5421 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
5422 && !i
.tm
.opcode_modifier
.ignoresize
5423 && !i
.tm
.opcode_modifier
.floatmf
5424 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
5425 || (flag_code
== CODE_64BIT
5426 && i
.tm
.opcode_modifier
.jumpbyte
)))
5428 unsigned int prefix
= DATA_PREFIX_OPCODE
;
5430 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
5431 prefix
= ADDR_PREFIX_OPCODE
;
5433 if (!add_prefix (prefix
))
5437 /* Set mode64 for an operand. */
5438 if (i
.suffix
== QWORD_MNEM_SUFFIX
5439 && flag_code
== CODE_64BIT
5440 && !i
.tm
.opcode_modifier
.norex64
)
5442 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5443 need rex64. cmpxchg8b is also a special case. */
5444 if (! (i
.operands
== 2
5445 && i
.tm
.base_opcode
== 0x90
5446 && i
.tm
.extension_opcode
== None
5447 && operand_type_equal (&i
.types
[0], &acc64
)
5448 && operand_type_equal (&i
.types
[1], &acc64
))
5449 && ! (i
.operands
== 1
5450 && i
.tm
.base_opcode
== 0xfc7
5451 && i
.tm
.extension_opcode
== 1
5452 && !operand_type_check (i
.types
[0], reg
)
5453 && operand_type_check (i
.types
[0], anymem
)))
5457 /* Size floating point instruction. */
5458 if (i
.suffix
== LONG_MNEM_SUFFIX
)
5459 if (i
.tm
.opcode_modifier
.floatmf
)
5460 i
.tm
.base_opcode
^= 4;
5467 check_byte_reg (void)
5471 for (op
= i
.operands
; --op
>= 0;)
5473 /* If this is an eight bit register, it's OK. If it's the 16 or
5474 32 bit version of an eight bit register, we will just use the
5475 low portion, and that's OK too. */
5476 if (i
.types
[op
].bitfield
.reg8
)
5479 /* I/O port address operands are OK too. */
5480 if (i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
5483 /* crc32 doesn't generate this warning. */
5484 if (i
.tm
.base_opcode
== 0xf20f38f0)
5487 if ((i
.types
[op
].bitfield
.reg16
5488 || i
.types
[op
].bitfield
.reg32
5489 || i
.types
[op
].bitfield
.reg64
)
5490 && i
.op
[op
].regs
->reg_num
< 4
5491 /* Prohibit these changes in 64bit mode, since the lowering
5492 would be more complicated. */
5493 && flag_code
!= CODE_64BIT
)
5495 #if REGISTER_WARNINGS
5496 if (!quiet_warnings
)
5497 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5499 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
5500 ? REGNAM_AL
- REGNAM_AX
5501 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
5503 i
.op
[op
].regs
->reg_name
,
5508 /* Any other register is bad. */
5509 if (i
.types
[op
].bitfield
.reg16
5510 || i
.types
[op
].bitfield
.reg32
5511 || i
.types
[op
].bitfield
.reg64
5512 || i
.types
[op
].bitfield
.regmmx
5513 || i
.types
[op
].bitfield
.regxmm
5514 || i
.types
[op
].bitfield
.regymm
5515 || i
.types
[op
].bitfield
.regzmm
5516 || i
.types
[op
].bitfield
.sreg2
5517 || i
.types
[op
].bitfield
.sreg3
5518 || i
.types
[op
].bitfield
.control
5519 || i
.types
[op
].bitfield
.debug
5520 || i
.types
[op
].bitfield
.test
5521 || i
.types
[op
].bitfield
.floatreg
5522 || i
.types
[op
].bitfield
.floatacc
)
5524 as_bad (_("`%s%s' not allowed with `%s%c'"),
5526 i
.op
[op
].regs
->reg_name
,
5536 check_long_reg (void)
5540 for (op
= i
.operands
; --op
>= 0;)
5541 /* Reject eight bit registers, except where the template requires
5542 them. (eg. movzb) */
5543 if (i
.types
[op
].bitfield
.reg8
5544 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5545 || i
.tm
.operand_types
[op
].bitfield
.reg32
5546 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5548 as_bad (_("`%s%s' not allowed with `%s%c'"),
5550 i
.op
[op
].regs
->reg_name
,
5555 /* Warn if the e prefix on a general reg is missing. */
5556 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5557 && i
.types
[op
].bitfield
.reg16
5558 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5559 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5561 /* Prohibit these changes in the 64bit mode, since the
5562 lowering is more complicated. */
5563 if (flag_code
== CODE_64BIT
)
5565 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5566 register_prefix
, i
.op
[op
].regs
->reg_name
,
5570 #if REGISTER_WARNINGS
5571 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5573 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
5574 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5577 /* Warn if the r prefix on a general reg is present. */
5578 else if (i
.types
[op
].bitfield
.reg64
5579 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5580 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5583 && i
.tm
.opcode_modifier
.toqword
5584 && !i
.types
[0].bitfield
.regxmm
)
5586 /* Convert to QWORD. We want REX byte. */
5587 i
.suffix
= QWORD_MNEM_SUFFIX
;
5591 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5592 register_prefix
, i
.op
[op
].regs
->reg_name
,
5601 check_qword_reg (void)
5605 for (op
= i
.operands
; --op
>= 0; )
5606 /* Reject eight bit registers, except where the template requires
5607 them. (eg. movzb) */
5608 if (i
.types
[op
].bitfield
.reg8
5609 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5610 || i
.tm
.operand_types
[op
].bitfield
.reg32
5611 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5613 as_bad (_("`%s%s' not allowed with `%s%c'"),
5615 i
.op
[op
].regs
->reg_name
,
5620 /* Warn if the r prefix on a general reg is missing. */
5621 else if ((i
.types
[op
].bitfield
.reg16
5622 || i
.types
[op
].bitfield
.reg32
)
5623 && (i
.tm
.operand_types
[op
].bitfield
.reg32
5624 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5626 /* Prohibit these changes in the 64bit mode, since the
5627 lowering is more complicated. */
5629 && i
.tm
.opcode_modifier
.todword
5630 && !i
.types
[0].bitfield
.regxmm
)
5632 /* Convert to DWORD. We don't want REX byte. */
5633 i
.suffix
= LONG_MNEM_SUFFIX
;
5637 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5638 register_prefix
, i
.op
[op
].regs
->reg_name
,
5647 check_word_reg (void)
5650 for (op
= i
.operands
; --op
>= 0;)
5651 /* Reject eight bit registers, except where the template requires
5652 them. (eg. movzb) */
5653 if (i
.types
[op
].bitfield
.reg8
5654 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5655 || i
.tm
.operand_types
[op
].bitfield
.reg32
5656 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5658 as_bad (_("`%s%s' not allowed with `%s%c'"),
5660 i
.op
[op
].regs
->reg_name
,
5665 /* Warn if the e or r prefix on a general reg is present. */
5666 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
5667 && (i
.types
[op
].bitfield
.reg32
5668 || i
.types
[op
].bitfield
.reg64
)
5669 && (i
.tm
.operand_types
[op
].bitfield
.reg16
5670 || i
.tm
.operand_types
[op
].bitfield
.acc
))
5672 /* Prohibit these changes in the 64bit mode, since the
5673 lowering is more complicated. */
5674 if (flag_code
== CODE_64BIT
)
5676 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5677 register_prefix
, i
.op
[op
].regs
->reg_name
,
5681 #if REGISTER_WARNINGS
5682 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5684 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
5685 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
5692 update_imm (unsigned int j
)
5694 i386_operand_type overlap
= i
.types
[j
];
5695 if ((overlap
.bitfield
.imm8
5696 || overlap
.bitfield
.imm8s
5697 || overlap
.bitfield
.imm16
5698 || overlap
.bitfield
.imm32
5699 || overlap
.bitfield
.imm32s
5700 || overlap
.bitfield
.imm64
)
5701 && !operand_type_equal (&overlap
, &imm8
)
5702 && !operand_type_equal (&overlap
, &imm8s
)
5703 && !operand_type_equal (&overlap
, &imm16
)
5704 && !operand_type_equal (&overlap
, &imm32
)
5705 && !operand_type_equal (&overlap
, &imm32s
)
5706 && !operand_type_equal (&overlap
, &imm64
))
5710 i386_operand_type temp
;
5712 operand_type_set (&temp
, 0);
5713 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
5715 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
5716 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
5718 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
5719 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
5720 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
5722 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
5723 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
5726 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
5729 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
5730 || operand_type_equal (&overlap
, &imm16_32
)
5731 || operand_type_equal (&overlap
, &imm16_32s
))
5733 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
5738 if (!operand_type_equal (&overlap
, &imm8
)
5739 && !operand_type_equal (&overlap
, &imm8s
)
5740 && !operand_type_equal (&overlap
, &imm16
)
5741 && !operand_type_equal (&overlap
, &imm32
)
5742 && !operand_type_equal (&overlap
, &imm32s
)
5743 && !operand_type_equal (&overlap
, &imm64
))
5745 as_bad (_("no instruction mnemonic suffix given; "
5746 "can't determine immediate size"));
5750 i
.types
[j
] = overlap
;
5760 /* Update the first 2 immediate operands. */
5761 n
= i
.operands
> 2 ? 2 : i
.operands
;
5764 for (j
= 0; j
< n
; j
++)
5765 if (update_imm (j
) == 0)
5768 /* The 3rd operand can't be immediate operand. */
5769 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
5776 bad_implicit_operand (int xmm
)
5778 const char *ireg
= xmm
? "xmm0" : "ymm0";
5781 as_bad (_("the last operand of `%s' must be `%s%s'"),
5782 i
.tm
.name
, register_prefix
, ireg
);
5784 as_bad (_("the first operand of `%s' must be `%s%s'"),
5785 i
.tm
.name
, register_prefix
, ireg
);
5790 process_operands (void)
5792 /* Default segment register this instruction will use for memory
5793 accesses. 0 means unknown. This is only for optimizing out
5794 unnecessary segment overrides. */
5795 const seg_entry
*default_seg
= 0;
5797 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
5799 unsigned int dupl
= i
.operands
;
5800 unsigned int dest
= dupl
- 1;
5803 /* The destination must be an xmm register. */
5804 gas_assert (i
.reg_operands
5805 && MAX_OPERANDS
> dupl
5806 && operand_type_equal (&i
.types
[dest
], ®xmm
));
5808 if (i
.tm
.opcode_modifier
.firstxmm0
)
5810 /* The first operand is implicit and must be xmm0. */
5811 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
5812 if (register_number (i
.op
[0].regs
) != 0)
5813 return bad_implicit_operand (1);
5815 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
5817 /* Keep xmm0 for instructions with VEX prefix and 3
5823 /* We remove the first xmm0 and keep the number of
5824 operands unchanged, which in fact duplicates the
5826 for (j
= 1; j
< i
.operands
; j
++)
5828 i
.op
[j
- 1] = i
.op
[j
];
5829 i
.types
[j
- 1] = i
.types
[j
];
5830 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5834 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
5836 gas_assert ((MAX_OPERANDS
- 1) > dupl
5837 && (i
.tm
.opcode_modifier
.vexsources
5840 /* Add the implicit xmm0 for instructions with VEX prefix
5842 for (j
= i
.operands
; j
> 0; j
--)
5844 i
.op
[j
] = i
.op
[j
- 1];
5845 i
.types
[j
] = i
.types
[j
- 1];
5846 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
5849 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
5850 i
.types
[0] = regxmm
;
5851 i
.tm
.operand_types
[0] = regxmm
;
5854 i
.reg_operands
+= 2;
5859 i
.op
[dupl
] = i
.op
[dest
];
5860 i
.types
[dupl
] = i
.types
[dest
];
5861 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5870 i
.op
[dupl
] = i
.op
[dest
];
5871 i
.types
[dupl
] = i
.types
[dest
];
5872 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
5875 if (i
.tm
.opcode_modifier
.immext
)
5878 else if (i
.tm
.opcode_modifier
.firstxmm0
)
5882 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5883 gas_assert (i
.reg_operands
5884 && (operand_type_equal (&i
.types
[0], ®xmm
)
5885 || operand_type_equal (&i
.types
[0], ®ymm
)
5886 || operand_type_equal (&i
.types
[0], ®zmm
)));
5887 if (register_number (i
.op
[0].regs
) != 0)
5888 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5890 for (j
= 1; j
< i
.operands
; j
++)
5892 i
.op
[j
- 1] = i
.op
[j
];
5893 i
.types
[j
- 1] = i
.types
[j
];
5895 /* We need to adjust fields in i.tm since they are used by
5896 build_modrm_byte. */
5897 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5904 else if (i
.tm
.opcode_modifier
.regkludge
)
5906 /* The imul $imm, %reg instruction is converted into
5907 imul $imm, %reg, %reg, and the clr %reg instruction
5908 is converted into xor %reg, %reg. */
5910 unsigned int first_reg_op
;
5912 if (operand_type_check (i
.types
[0], reg
))
5916 /* Pretend we saw the extra register operand. */
5917 gas_assert (i
.reg_operands
== 1
5918 && i
.op
[first_reg_op
+ 1].regs
== 0);
5919 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5920 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5925 if (i
.tm
.opcode_modifier
.shortform
)
5927 if (i
.types
[0].bitfield
.sreg2
5928 || i
.types
[0].bitfield
.sreg3
)
5930 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5931 && i
.op
[0].regs
->reg_num
== 1)
5933 as_bad (_("you can't `pop %scs'"), register_prefix
);
5936 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5937 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5942 /* The register or float register operand is in operand
5946 if (i
.types
[0].bitfield
.floatreg
5947 || operand_type_check (i
.types
[0], reg
))
5951 /* Register goes in low 3 bits of opcode. */
5952 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5953 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5955 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5957 /* Warn about some common errors, but press on regardless.
5958 The first case can be generated by gcc (<= 2.8.1). */
5959 if (i
.operands
== 2)
5961 /* Reversed arguments on faddp, fsubp, etc. */
5962 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5963 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5964 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5968 /* Extraneous `l' suffix on fp insn. */
5969 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5970 register_prefix
, i
.op
[0].regs
->reg_name
);
5975 else if (i
.tm
.opcode_modifier
.modrm
)
5977 /* The opcode is completed (modulo i.tm.extension_opcode which
5978 must be put into the modrm byte). Now, we make the modrm and
5979 index base bytes based on all the info we've collected. */
5981 default_seg
= build_modrm_byte ();
5983 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5987 else if (i
.tm
.opcode_modifier
.isstring
)
5989 /* For the string instructions that allow a segment override
5990 on one of their operands, the default segment is ds. */
5994 if (i
.tm
.base_opcode
== 0x8d /* lea */
5997 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5999 /* If a segment was explicitly specified, and the specified segment
6000 is not the default, use an opcode prefix to select it. If we
6001 never figured out what the default segment is, then default_seg
6002 will be zero at this point, and the specified segment prefix will
6004 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
6006 if (!add_prefix (i
.seg
[0]->seg_prefix
))
6012 static const seg_entry
*
6013 build_modrm_byte (void)
6015 const seg_entry
*default_seg
= 0;
6016 unsigned int source
, dest
;
6019 /* The first operand of instructions with VEX prefix and 3 sources
6020 must be VEX_Imm4. */
6021 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
6024 unsigned int nds
, reg_slot
;
6027 if (i
.tm
.opcode_modifier
.veximmext
6028 && i
.tm
.opcode_modifier
.immext
)
6030 dest
= i
.operands
- 2;
6031 gas_assert (dest
== 3);
6034 dest
= i
.operands
- 1;
6037 /* There are 2 kinds of instructions:
6038 1. 5 operands: 4 register operands or 3 register operands
6039 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6040 VexW0 or VexW1. The destination must be either XMM, YMM or
6042 2. 4 operands: 4 register operands or 3 register operands
6043 plus 1 memory operand, VexXDS, and VexImmExt */
6044 gas_assert ((i
.reg_operands
== 4
6045 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
6046 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6047 && (i
.tm
.opcode_modifier
.veximmext
6048 || (i
.imm_operands
== 1
6049 && i
.types
[0].bitfield
.vec_imm4
6050 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
6051 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6052 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
6053 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)
6054 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®zmm
)))));
6056 if (i
.imm_operands
== 0)
6058 /* When there is no immediate operand, generate an 8bit
6059 immediate operand to encode the first operand. */
6060 exp
= &im_expressions
[i
.imm_operands
++];
6061 i
.op
[i
.operands
].imms
= exp
;
6062 i
.types
[i
.operands
] = imm8
;
6064 /* If VexW1 is set, the first operand is the source and
6065 the second operand is encoded in the immediate operand. */
6066 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
6077 /* FMA swaps REG and NDS. */
6078 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
6086 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6088 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6090 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6092 exp
->X_op
= O_constant
;
6093 exp
->X_add_number
= register_number (i
.op
[reg_slot
].regs
) << 4;
6094 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6098 unsigned int imm_slot
;
6100 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6102 /* If VexW0 is set, the third operand is the source and
6103 the second operand is encoded in the immediate
6110 /* VexW1 is set, the second operand is the source and
6111 the third operand is encoded in the immediate
6117 if (i
.tm
.opcode_modifier
.immext
)
6119 /* When ImmExt is set, the immdiate byte is the last
6121 imm_slot
= i
.operands
- 1;
6129 /* Turn on Imm8 so that output_imm will generate it. */
6130 i
.types
[imm_slot
].bitfield
.imm8
= 1;
6133 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6135 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6137 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
6139 i
.op
[imm_slot
].imms
->X_add_number
6140 |= register_number (i
.op
[reg_slot
].regs
) << 4;
6141 gas_assert ((i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
) == 0);
6144 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
6145 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6147 || operand_type_equal (&i
.tm
.operand_types
[nds
],
6149 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
6154 /* i.reg_operands MUST be the number of real register operands;
6155 implicit registers do not count. If there are 3 register
6156 operands, it must be a instruction with VexNDS. For a
6157 instruction with VexNDD, the destination register is encoded
6158 in VEX prefix. If there are 4 register operands, it must be
6159 a instruction with VEX prefix and 3 sources. */
6160 if (i
.mem_operands
== 0
6161 && ((i
.reg_operands
== 2
6162 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
6163 || (i
.reg_operands
== 3
6164 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6165 || (i
.reg_operands
== 4 && vex_3_sources
)))
6173 /* When there are 3 operands, one of them may be immediate,
6174 which may be the first or the last operand. Otherwise,
6175 the first operand must be shift count register (cl) or it
6176 is an instruction with VexNDS. */
6177 gas_assert (i
.imm_operands
== 1
6178 || (i
.imm_operands
== 0
6179 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6180 || i
.types
[0].bitfield
.shiftcount
)));
6181 if (operand_type_check (i
.types
[0], imm
)
6182 || i
.types
[0].bitfield
.shiftcount
)
6188 /* When there are 4 operands, the first two must be 8bit
6189 immediate operands. The source operand will be the 3rd
6192 For instructions with VexNDS, if the first operand
6193 an imm8, the source operand is the 2nd one. If the last
6194 operand is imm8, the source operand is the first one. */
6195 gas_assert ((i
.imm_operands
== 2
6196 && i
.types
[0].bitfield
.imm8
6197 && i
.types
[1].bitfield
.imm8
)
6198 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
6199 && i
.imm_operands
== 1
6200 && (i
.types
[0].bitfield
.imm8
6201 || i
.types
[i
.operands
- 1].bitfield
.imm8
6203 if (i
.imm_operands
== 2)
6207 if (i
.types
[0].bitfield
.imm8
)
6214 if (i
.tm
.opcode_modifier
.evex
)
6216 /* For EVEX instructions, when there are 5 operands, the
6217 first one must be immediate operand. If the second one
6218 is immediate operand, the source operand is the 3th
6219 one. If the last one is immediate operand, the source
6220 operand is the 2nd one. */
6221 gas_assert (i
.imm_operands
== 2
6222 && i
.tm
.opcode_modifier
.sae
6223 && operand_type_check (i
.types
[0], imm
));
6224 if (operand_type_check (i
.types
[1], imm
))
6226 else if (operand_type_check (i
.types
[4], imm
))
6240 /* RC/SAE operand could be between DEST and SRC. That happens
6241 when one operand is GPR and the other one is XMM/YMM/ZMM
6243 if (i
.rounding
&& i
.rounding
->operand
== (int) dest
)
6246 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6248 /* For instructions with VexNDS, the register-only source
6249 operand must be 32/64bit integer, XMM, YMM or ZMM
6250 register. It is encoded in VEX prefix. We need to
6251 clear RegMem bit before calling operand_type_equal. */
6253 i386_operand_type op
;
6256 /* Check register-only source operand when two source
6257 operands are swapped. */
6258 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
6259 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
6267 op
= i
.tm
.operand_types
[vvvv
];
6268 op
.bitfield
.regmem
= 0;
6269 if ((dest
+ 1) >= i
.operands
6270 || (!op
.bitfield
.reg32
6271 && op
.bitfield
.reg64
6272 && !operand_type_equal (&op
, ®xmm
)
6273 && !operand_type_equal (&op
, ®ymm
)
6274 && !operand_type_equal (&op
, ®zmm
)
6275 && !operand_type_equal (&op
, ®mask
)))
6277 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
6283 /* One of the register operands will be encoded in the i.tm.reg
6284 field, the other in the combined i.tm.mode and i.tm.regmem
6285 fields. If no form of this instruction supports a memory
6286 destination operand, then we assume the source operand may
6287 sometimes be a memory operand and so we need to store the
6288 destination in the i.rm.reg field. */
6289 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
6290 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
6292 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
6293 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
6294 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6296 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6298 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6300 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6305 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
6306 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
6307 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
6309 if ((i
.op
[dest
].regs
->reg_flags
& RegVRex
) != 0)
6311 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
6313 if ((i
.op
[source
].regs
->reg_flags
& RegVRex
) != 0)
6316 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
6318 if (!i
.types
[0].bitfield
.control
6319 && !i
.types
[1].bitfield
.control
)
6321 i
.rex
&= ~(REX_R
| REX_B
);
6322 add_prefix (LOCK_PREFIX_OPCODE
);
6326 { /* If it's not 2 reg operands... */
6331 unsigned int fake_zero_displacement
= 0;
6334 for (op
= 0; op
< i
.operands
; op
++)
6335 if (operand_type_check (i
.types
[op
], anymem
))
6337 gas_assert (op
< i
.operands
);
6339 if (i
.tm
.opcode_modifier
.vecsib
)
6341 if (i
.index_reg
->reg_num
== RegEiz
6342 || i
.index_reg
->reg_num
== RegRiz
)
6345 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6348 i
.sib
.base
= NO_BASE_REGISTER
;
6349 i
.sib
.scale
= i
.log2_scale_factor
;
6350 /* No Vec_Disp8 if there is no base. */
6351 i
.types
[op
].bitfield
.vec_disp8
= 0;
6352 i
.types
[op
].bitfield
.disp8
= 0;
6353 i
.types
[op
].bitfield
.disp16
= 0;
6354 i
.types
[op
].bitfield
.disp64
= 0;
6355 if (flag_code
!= CODE_64BIT
)
6357 /* Must be 32 bit */
6358 i
.types
[op
].bitfield
.disp32
= 1;
6359 i
.types
[op
].bitfield
.disp32s
= 0;
6363 i
.types
[op
].bitfield
.disp32
= 0;
6364 i
.types
[op
].bitfield
.disp32s
= 1;
6367 i
.sib
.index
= i
.index_reg
->reg_num
;
6368 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6370 if ((i
.index_reg
->reg_flags
& RegVRex
) != 0)
6376 if (i
.base_reg
== 0)
6379 if (!i
.disp_operands
)
6381 fake_zero_displacement
= 1;
6382 /* Instructions with VSIB byte need 32bit displacement
6383 if there is no base register. */
6384 if (i
.tm
.opcode_modifier
.vecsib
)
6385 i
.types
[op
].bitfield
.disp32
= 1;
6387 if (i
.index_reg
== 0)
6389 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6390 /* Operand is just <disp> */
6391 if (flag_code
== CODE_64BIT
)
6393 /* 64bit mode overwrites the 32bit absolute
6394 addressing by RIP relative addressing and
6395 absolute addressing is encoded by one of the
6396 redundant SIB forms. */
6397 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6398 i
.sib
.base
= NO_BASE_REGISTER
;
6399 i
.sib
.index
= NO_INDEX_REGISTER
;
6400 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
6401 ? disp32s
: disp32
);
6403 else if ((flag_code
== CODE_16BIT
)
6404 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6406 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
6407 i
.types
[op
] = disp16
;
6411 i
.rm
.regmem
= NO_BASE_REGISTER
;
6412 i
.types
[op
] = disp32
;
6415 else if (!i
.tm
.opcode_modifier
.vecsib
)
6417 /* !i.base_reg && i.index_reg */
6418 if (i
.index_reg
->reg_num
== RegEiz
6419 || i
.index_reg
->reg_num
== RegRiz
)
6420 i
.sib
.index
= NO_INDEX_REGISTER
;
6422 i
.sib
.index
= i
.index_reg
->reg_num
;
6423 i
.sib
.base
= NO_BASE_REGISTER
;
6424 i
.sib
.scale
= i
.log2_scale_factor
;
6425 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6426 /* No Vec_Disp8 if there is no base. */
6427 i
.types
[op
].bitfield
.vec_disp8
= 0;
6428 i
.types
[op
].bitfield
.disp8
= 0;
6429 i
.types
[op
].bitfield
.disp16
= 0;
6430 i
.types
[op
].bitfield
.disp64
= 0;
6431 if (flag_code
!= CODE_64BIT
)
6433 /* Must be 32 bit */
6434 i
.types
[op
].bitfield
.disp32
= 1;
6435 i
.types
[op
].bitfield
.disp32s
= 0;
6439 i
.types
[op
].bitfield
.disp32
= 0;
6440 i
.types
[op
].bitfield
.disp32s
= 1;
6442 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6446 /* RIP addressing for 64bit mode. */
6447 else if (i
.base_reg
->reg_num
== RegRip
||
6448 i
.base_reg
->reg_num
== RegEip
)
6450 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6451 i
.rm
.regmem
= NO_BASE_REGISTER
;
6452 i
.types
[op
].bitfield
.disp8
= 0;
6453 i
.types
[op
].bitfield
.disp16
= 0;
6454 i
.types
[op
].bitfield
.disp32
= 0;
6455 i
.types
[op
].bitfield
.disp32s
= 1;
6456 i
.types
[op
].bitfield
.disp64
= 0;
6457 i
.types
[op
].bitfield
.vec_disp8
= 0;
6458 i
.flags
[op
] |= Operand_PCrel
;
6459 if (! i
.disp_operands
)
6460 fake_zero_displacement
= 1;
6462 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
6464 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6465 switch (i
.base_reg
->reg_num
)
6468 if (i
.index_reg
== 0)
6470 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6471 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
6475 if (i
.index_reg
== 0)
6478 if (operand_type_check (i
.types
[op
], disp
) == 0)
6480 /* fake (%bp) into 0(%bp) */
6481 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6482 i
.types
[op
].bitfield
.vec_disp8
= 1;
6484 i
.types
[op
].bitfield
.disp8
= 1;
6485 fake_zero_displacement
= 1;
6488 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6489 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
6491 default: /* (%si) -> 4 or (%di) -> 5 */
6492 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
6494 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6496 else /* i.base_reg and 32/64 bit mode */
6498 if (flag_code
== CODE_64BIT
6499 && operand_type_check (i
.types
[op
], disp
))
6501 i386_operand_type temp
;
6502 operand_type_set (&temp
, 0);
6503 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
6504 temp
.bitfield
.vec_disp8
6505 = i
.types
[op
].bitfield
.vec_disp8
;
6507 if (i
.prefix
[ADDR_PREFIX
] == 0)
6508 i
.types
[op
].bitfield
.disp32s
= 1;
6510 i
.types
[op
].bitfield
.disp32
= 1;
6513 if (!i
.tm
.opcode_modifier
.vecsib
)
6514 i
.rm
.regmem
= i
.base_reg
->reg_num
;
6515 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
6517 i
.sib
.base
= i
.base_reg
->reg_num
;
6518 /* x86-64 ignores REX prefix bit here to avoid decoder
6520 if (!(i
.base_reg
->reg_flags
& RegRex
)
6521 && (i
.base_reg
->reg_num
== EBP_REG_NUM
6522 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
6524 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
6526 fake_zero_displacement
= 1;
6527 if (i
.tm
.operand_types
[op
].bitfield
.vec_disp8
)
6528 i
.types
[op
].bitfield
.vec_disp8
= 1;
6530 i
.types
[op
].bitfield
.disp8
= 1;
6532 i
.sib
.scale
= i
.log2_scale_factor
;
6533 if (i
.index_reg
== 0)
6535 gas_assert (!i
.tm
.opcode_modifier
.vecsib
);
6536 /* <disp>(%esp) becomes two byte modrm with no index
6537 register. We've already stored the code for esp
6538 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6539 Any base register besides %esp will not use the
6540 extra modrm byte. */
6541 i
.sib
.index
= NO_INDEX_REGISTER
;
6543 else if (!i
.tm
.opcode_modifier
.vecsib
)
6545 if (i
.index_reg
->reg_num
== RegEiz
6546 || i
.index_reg
->reg_num
== RegRiz
)
6547 i
.sib
.index
= NO_INDEX_REGISTER
;
6549 i
.sib
.index
= i
.index_reg
->reg_num
;
6550 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
6551 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
6556 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6557 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
6561 if (!fake_zero_displacement
6565 fake_zero_displacement
= 1;
6566 if (i
.disp_encoding
== disp_encoding_8bit
)
6567 i
.types
[op
].bitfield
.disp8
= 1;
6569 i
.types
[op
].bitfield
.disp32
= 1;
6571 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
6575 if (fake_zero_displacement
)
6577 /* Fakes a zero displacement assuming that i.types[op]
6578 holds the correct displacement size. */
6581 gas_assert (i
.op
[op
].disps
== 0);
6582 exp
= &disp_expressions
[i
.disp_operands
++];
6583 i
.op
[op
].disps
= exp
;
6584 exp
->X_op
= O_constant
;
6585 exp
->X_add_number
= 0;
6586 exp
->X_add_symbol
= (symbolS
*) 0;
6587 exp
->X_op_symbol
= (symbolS
*) 0;
6595 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
6597 if (operand_type_check (i
.types
[0], imm
))
6598 i
.vex
.register_specifier
= NULL
;
6601 /* VEX.vvvv encodes one of the sources when the first
6602 operand is not an immediate. */
6603 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6604 i
.vex
.register_specifier
= i
.op
[0].regs
;
6606 i
.vex
.register_specifier
= i
.op
[1].regs
;
6609 /* Destination is a XMM register encoded in the ModRM.reg
6611 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
6612 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
6615 /* ModRM.rm and VEX.B encodes the other source. */
6616 if (!i
.mem_operands
)
6620 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
6621 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6623 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
6625 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6629 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
6631 i
.vex
.register_specifier
= i
.op
[2].regs
;
6632 if (!i
.mem_operands
)
6635 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
6636 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
6640 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6641 (if any) based on i.tm.extension_opcode. Again, we must be
6642 careful to make sure that segment/control/debug/test/MMX
6643 registers are coded into the i.rm.reg field. */
6644 else if (i
.reg_operands
)
6647 unsigned int vex_reg
= ~0;
6649 for (op
= 0; op
< i
.operands
; op
++)
6650 if (i
.types
[op
].bitfield
.reg8
6651 || i
.types
[op
].bitfield
.reg16
6652 || i
.types
[op
].bitfield
.reg32
6653 || i
.types
[op
].bitfield
.reg64
6654 || i
.types
[op
].bitfield
.regmmx
6655 || i
.types
[op
].bitfield
.regxmm
6656 || i
.types
[op
].bitfield
.regymm
6657 || i
.types
[op
].bitfield
.regbnd
6658 || i
.types
[op
].bitfield
.regzmm
6659 || i
.types
[op
].bitfield
.regmask
6660 || i
.types
[op
].bitfield
.sreg2
6661 || i
.types
[op
].bitfield
.sreg3
6662 || i
.types
[op
].bitfield
.control
6663 || i
.types
[op
].bitfield
.debug
6664 || i
.types
[op
].bitfield
.test
)
6669 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
6671 /* For instructions with VexNDS, the register-only
6672 source operand is encoded in VEX prefix. */
6673 gas_assert (mem
!= (unsigned int) ~0);
6678 gas_assert (op
< i
.operands
);
6682 /* Check register-only source operand when two source
6683 operands are swapped. */
6684 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
6685 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
6689 gas_assert (mem
== (vex_reg
+ 1)
6690 && op
< i
.operands
);
6695 gas_assert (vex_reg
< i
.operands
);
6699 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
6701 /* For instructions with VexNDD, the register destination
6702 is encoded in VEX prefix. */
6703 if (i
.mem_operands
== 0)
6705 /* There is no memory operand. */
6706 gas_assert ((op
+ 2) == i
.operands
);
6711 /* There are only 2 operands. */
6712 gas_assert (op
< 2 && i
.operands
== 2);
6717 gas_assert (op
< i
.operands
);
6719 if (vex_reg
!= (unsigned int) ~0)
6721 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
6723 if (type
->bitfield
.reg32
!= 1
6724 && type
->bitfield
.reg64
!= 1
6725 && !operand_type_equal (type
, ®xmm
)
6726 && !operand_type_equal (type
, ®ymm
)
6727 && !operand_type_equal (type
, ®zmm
)
6728 && !operand_type_equal (type
, ®mask
))
6731 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
6734 /* Don't set OP operand twice. */
6737 /* If there is an extension opcode to put here, the
6738 register number must be put into the regmem field. */
6739 if (i
.tm
.extension_opcode
!= None
)
6741 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
6742 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6744 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6749 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
6750 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
6752 if ((i
.op
[op
].regs
->reg_flags
& RegVRex
) != 0)
6757 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6758 must set it to 3 to indicate this is a register operand
6759 in the regmem field. */
6760 if (!i
.mem_operands
)
6764 /* Fill in i.rm.reg field with extension opcode (if any). */
6765 if (i
.tm
.extension_opcode
!= None
)
6766 i
.rm
.reg
= i
.tm
.extension_opcode
;
6772 output_branch (void)
6778 relax_substateT subtype
;
6782 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
6783 size
= i
.disp_encoding
== disp_encoding_32bit
? BIG
: SMALL
;
6786 if (i
.prefix
[DATA_PREFIX
] != 0)
6792 /* Pentium4 branch hints. */
6793 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6794 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6799 if (i
.prefix
[REX_PREFIX
] != 0)
6805 /* BND prefixed jump. */
6806 if (i
.prefix
[BND_PREFIX
] != 0)
6808 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6812 if (i
.prefixes
!= 0 && !intel_syntax
)
6813 as_warn (_("skipping prefixes on this instruction"));
6815 /* It's always a symbol; End frag & setup for relax.
6816 Make sure there is enough room in this frag for the largest
6817 instruction we may generate in md_convert_frag. This is 2
6818 bytes for the opcode and room for the prefix and largest
6820 frag_grow (prefix
+ 2 + 4);
6821 /* Prefix and 1 opcode byte go in fr_fix. */
6822 p
= frag_more (prefix
+ 1);
6823 if (i
.prefix
[DATA_PREFIX
] != 0)
6824 *p
++ = DATA_PREFIX_OPCODE
;
6825 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
6826 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
6827 *p
++ = i
.prefix
[SEG_PREFIX
];
6828 if (i
.prefix
[REX_PREFIX
] != 0)
6829 *p
++ = i
.prefix
[REX_PREFIX
];
6830 *p
= i
.tm
.base_opcode
;
6832 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
6833 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
6834 else if (cpu_arch_flags
.bitfield
.cpui386
)
6835 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
6837 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
6840 sym
= i
.op
[0].disps
->X_add_symbol
;
6841 off
= i
.op
[0].disps
->X_add_number
;
6843 if (i
.op
[0].disps
->X_op
!= O_constant
6844 && i
.op
[0].disps
->X_op
!= O_symbol
)
6846 /* Handle complex expressions. */
6847 sym
= make_expr_symbol (i
.op
[0].disps
);
6851 /* 1 possible extra opcode + 4 byte displacement go in var part.
6852 Pass reloc in fr_var. */
6853 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
6863 if (i
.tm
.opcode_modifier
.jumpbyte
)
6865 /* This is a loop or jecxz type instruction. */
6867 if (i
.prefix
[ADDR_PREFIX
] != 0)
6869 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
6872 /* Pentium4 branch hints. */
6873 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
6874 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
6876 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
6885 if (flag_code
== CODE_16BIT
)
6888 if (i
.prefix
[DATA_PREFIX
] != 0)
6890 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
6900 if (i
.prefix
[REX_PREFIX
] != 0)
6902 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
6906 /* BND prefixed jump. */
6907 if (i
.prefix
[BND_PREFIX
] != 0)
6909 FRAG_APPEND_1_CHAR (i
.prefix
[BND_PREFIX
]);
6913 if (i
.prefixes
!= 0 && !intel_syntax
)
6914 as_warn (_("skipping prefixes on this instruction"));
6916 p
= frag_more (i
.tm
.opcode_length
+ size
);
6917 switch (i
.tm
.opcode_length
)
6920 *p
++ = i
.tm
.base_opcode
>> 8;
6922 *p
++ = i
.tm
.base_opcode
;
6928 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6929 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
6931 /* All jumps handled here are signed, but don't use a signed limit
6932 check for 32 and 16 bit jumps as we want to allow wrap around at
6933 4G and 64k respectively. */
6935 fixP
->fx_signed
= 1;
6939 output_interseg_jump (void)
6947 if (flag_code
== CODE_16BIT
)
6951 if (i
.prefix
[DATA_PREFIX
] != 0)
6957 if (i
.prefix
[REX_PREFIX
] != 0)
6967 if (i
.prefixes
!= 0 && !intel_syntax
)
6968 as_warn (_("skipping prefixes on this instruction"));
6970 /* 1 opcode; 2 segment; offset */
6971 p
= frag_more (prefix
+ 1 + 2 + size
);
6973 if (i
.prefix
[DATA_PREFIX
] != 0)
6974 *p
++ = DATA_PREFIX_OPCODE
;
6976 if (i
.prefix
[REX_PREFIX
] != 0)
6977 *p
++ = i
.prefix
[REX_PREFIX
];
6979 *p
++ = i
.tm
.base_opcode
;
6980 if (i
.op
[1].imms
->X_op
== O_constant
)
6982 offsetT n
= i
.op
[1].imms
->X_add_number
;
6985 && !fits_in_unsigned_word (n
)
6986 && !fits_in_signed_word (n
))
6988 as_bad (_("16-bit jump out of range"));
6991 md_number_to_chars (p
, n
, size
);
6994 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6995 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
6996 if (i
.op
[0].imms
->X_op
!= O_constant
)
6997 as_bad (_("can't handle non absolute segment in `%s'"),
6999 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
7005 fragS
*insn_start_frag
;
7006 offsetT insn_start_off
;
7008 /* Tie dwarf2 debug info to the address at the start of the insn.
7009 We can't do this after the insn has been output as the current
7010 frag may have been closed off. eg. by frag_var. */
7011 dwarf2_emit_insn (0);
7013 insn_start_frag
= frag_now
;
7014 insn_start_off
= frag_now_fix ();
7017 if (i
.tm
.opcode_modifier
.jump
)
7019 else if (i
.tm
.opcode_modifier
.jumpbyte
7020 || i
.tm
.opcode_modifier
.jumpdword
)
7022 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
7023 output_interseg_jump ();
7026 /* Output normal instructions here. */
7030 unsigned int prefix
;
7033 && i
.tm
.base_opcode
== 0xfae
7035 && i
.imm_operands
== 1
7036 && (i
.op
[0].imms
->X_add_number
== 0xe8
7037 || i
.op
[0].imms
->X_add_number
== 0xf0
7038 || i
.op
[0].imms
->X_add_number
== 0xf8))
7040 /* Encode lfence, mfence, and sfence as
7041 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7042 offsetT val
= 0x240483f0ULL
;
7044 md_number_to_chars (p
, val
, 5);
7048 /* Some processors fail on LOCK prefix. This options makes
7049 assembler ignore LOCK prefix and serves as a workaround. */
7050 if (omit_lock_prefix
)
7052 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
)
7054 i
.prefix
[LOCK_PREFIX
] = 0;
7057 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7058 don't need the explicit prefix. */
7059 if (!i
.tm
.opcode_modifier
.vex
&& !i
.tm
.opcode_modifier
.evex
)
7061 switch (i
.tm
.opcode_length
)
7064 if (i
.tm
.base_opcode
& 0xff000000)
7066 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
7071 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
7073 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
7074 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
7077 if (prefix
!= REPE_PREFIX_OPCODE
7078 || (i
.prefix
[REP_PREFIX
]
7079 != REPE_PREFIX_OPCODE
))
7080 add_prefix (prefix
);
7083 add_prefix (prefix
);
7092 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7093 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7094 R_X86_64_GOTTPOFF relocation so that linker can safely
7095 perform IE->LE optimization. */
7096 if (x86_elf_abi
== X86_64_X32_ABI
7098 && i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
7099 && i
.prefix
[REX_PREFIX
] == 0)
7100 add_prefix (REX_OPCODE
);
7103 /* The prefix bytes. */
7104 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
7106 FRAG_APPEND_1_CHAR (*q
);
7110 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
7115 /* REX byte is encoded in VEX prefix. */
7119 FRAG_APPEND_1_CHAR (*q
);
7122 /* There should be no other prefixes for instructions
7127 /* For EVEX instructions i.vrex should become 0 after
7128 build_evex_prefix. For VEX instructions upper 16 registers
7129 aren't available, so VREX should be 0. */
7132 /* Now the VEX prefix. */
7133 p
= frag_more (i
.vex
.length
);
7134 for (j
= 0; j
< i
.vex
.length
; j
++)
7135 p
[j
] = i
.vex
.bytes
[j
];
7138 /* Now the opcode; be careful about word order here! */
7139 if (i
.tm
.opcode_length
== 1)
7141 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
7145 switch (i
.tm
.opcode_length
)
7149 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
7150 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7154 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
7164 /* Put out high byte first: can't use md_number_to_chars! */
7165 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
7166 *p
= i
.tm
.base_opcode
& 0xff;
7169 /* Now the modrm byte and sib byte (if present). */
7170 if (i
.tm
.opcode_modifier
.modrm
)
7172 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
7175 /* If i.rm.regmem == ESP (4)
7176 && i.rm.mode != (Register mode)
7178 ==> need second modrm byte. */
7179 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
7181 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
7182 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
7184 | i
.sib
.scale
<< 6));
7187 if (i
.disp_operands
)
7188 output_disp (insn_start_frag
, insn_start_off
);
7191 output_imm (insn_start_frag
, insn_start_off
);
7197 pi ("" /*line*/, &i
);
7199 #endif /* DEBUG386 */
7202 /* Return the size of the displacement operand N. */
7205 disp_size (unsigned int n
)
7209 /* Vec_Disp8 has to be 8bit. */
7210 if (i
.types
[n
].bitfield
.vec_disp8
)
7212 else if (i
.types
[n
].bitfield
.disp64
)
7214 else if (i
.types
[n
].bitfield
.disp8
)
7216 else if (i
.types
[n
].bitfield
.disp16
)
7221 /* Return the size of the immediate operand N. */
7224 imm_size (unsigned int n
)
7227 if (i
.types
[n
].bitfield
.imm64
)
7229 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
7231 else if (i
.types
[n
].bitfield
.imm16
)
7237 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
7242 for (n
= 0; n
< i
.operands
; n
++)
7244 if (i
.types
[n
].bitfield
.vec_disp8
7245 || operand_type_check (i
.types
[n
], disp
))
7247 if (i
.op
[n
].disps
->X_op
== O_constant
)
7249 int size
= disp_size (n
);
7250 offsetT val
= i
.op
[n
].disps
->X_add_number
;
7252 if (i
.types
[n
].bitfield
.vec_disp8
)
7254 val
= offset_in_range (val
, size
);
7255 p
= frag_more (size
);
7256 md_number_to_chars (p
, val
, size
);
7260 enum bfd_reloc_code_real reloc_type
;
7261 int size
= disp_size (n
);
7262 int sign
= i
.types
[n
].bitfield
.disp32s
;
7263 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
7266 /* We can't have 8 bit displacement here. */
7267 gas_assert (!i
.types
[n
].bitfield
.disp8
);
7269 /* The PC relative address is computed relative
7270 to the instruction boundary, so in case immediate
7271 fields follows, we need to adjust the value. */
7272 if (pcrel
&& i
.imm_operands
)
7277 for (n1
= 0; n1
< i
.operands
; n1
++)
7278 if (operand_type_check (i
.types
[n1
], imm
))
7280 /* Only one immediate is allowed for PC
7281 relative address. */
7282 gas_assert (sz
== 0);
7284 i
.op
[n
].disps
->X_add_number
-= sz
;
7286 /* We should find the immediate. */
7287 gas_assert (sz
!= 0);
7290 p
= frag_more (size
);
7291 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
7293 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
7294 && (((reloc_type
== BFD_RELOC_32
7295 || reloc_type
== BFD_RELOC_X86_64_32S
7296 || (reloc_type
== BFD_RELOC_64
7298 && (i
.op
[n
].disps
->X_op
== O_symbol
7299 || (i
.op
[n
].disps
->X_op
== O_add
7300 && ((symbol_get_value_expression
7301 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
7303 || reloc_type
== BFD_RELOC_32_PCREL
))
7307 if (insn_start_frag
== frag_now
)
7308 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7313 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7314 for (fr
= insn_start_frag
->fr_next
;
7315 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7317 add
+= p
- frag_now
->fr_literal
;
7322 reloc_type
= BFD_RELOC_386_GOTPC
;
7323 i
.op
[n
].imms
->X_add_number
+= add
;
7325 else if (reloc_type
== BFD_RELOC_64
)
7326 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7328 /* Don't do the adjustment for x86-64, as there
7329 the pcrel addressing is relative to the _next_
7330 insn, and that is taken care of in other code. */
7331 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7333 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
7334 size
, i
.op
[n
].disps
, pcrel
,
7336 /* Check for "call/jmp *mem", "mov mem, %reg",
7337 "test %reg, mem" and "binop mem, %reg" where binop
7338 is one of adc, add, and, cmp, or, sbb, sub, xor
7339 instructions. Always generate R_386_GOT32X for
7340 "sym*GOT" operand in 32-bit mode. */
7341 if ((generate_relax_relocations
7344 && i
.rm
.regmem
== 5))
7346 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
7347 && ((i
.operands
== 1
7348 && i
.tm
.base_opcode
== 0xff
7349 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
7351 && (i
.tm
.base_opcode
== 0x8b
7352 || i
.tm
.base_opcode
== 0x85
7353 || (i
.tm
.base_opcode
& 0xc7) == 0x03))))
7357 fixP
->fx_tcbit
= i
.rex
!= 0;
7359 && (i
.base_reg
->reg_num
== RegRip
7360 || i
.base_reg
->reg_num
== RegEip
))
7361 fixP
->fx_tcbit2
= 1;
7364 fixP
->fx_tcbit2
= 1;
7372 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
7377 for (n
= 0; n
< i
.operands
; n
++)
7379 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7380 if (i
.rounding
&& (int) n
== i
.rounding
->operand
)
7383 if (operand_type_check (i
.types
[n
], imm
))
7385 if (i
.op
[n
].imms
->X_op
== O_constant
)
7387 int size
= imm_size (n
);
7390 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
7392 p
= frag_more (size
);
7393 md_number_to_chars (p
, val
, size
);
7397 /* Not absolute_section.
7398 Need a 32-bit fixup (don't support 8bit
7399 non-absolute imms). Try to support other
7401 enum bfd_reloc_code_real reloc_type
;
7402 int size
= imm_size (n
);
7405 if (i
.types
[n
].bitfield
.imm32s
7406 && (i
.suffix
== QWORD_MNEM_SUFFIX
7407 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
7412 p
= frag_more (size
);
7413 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
7415 /* This is tough to explain. We end up with this one if we
7416 * have operands that look like
7417 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7418 * obtain the absolute address of the GOT, and it is strongly
7419 * preferable from a performance point of view to avoid using
7420 * a runtime relocation for this. The actual sequence of
7421 * instructions often look something like:
7426 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7428 * The call and pop essentially return the absolute address
7429 * of the label .L66 and store it in %ebx. The linker itself
7430 * will ultimately change the first operand of the addl so
7431 * that %ebx points to the GOT, but to keep things simple, the
7432 * .o file must have this operand set so that it generates not
7433 * the absolute address of .L66, but the absolute address of
7434 * itself. This allows the linker itself simply treat a GOTPC
7435 * relocation as asking for a pcrel offset to the GOT to be
7436 * added in, and the addend of the relocation is stored in the
7437 * operand field for the instruction itself.
7439 * Our job here is to fix the operand so that it would add
7440 * the correct offset so that %ebx would point to itself. The
7441 * thing that is tricky is that .-.L66 will point to the
7442 * beginning of the instruction, so we need to further modify
7443 * the operand so that it will point to itself. There are
7444 * other cases where you have something like:
7446 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7448 * and here no correction would be required. Internally in
7449 * the assembler we treat operands of this form as not being
7450 * pcrel since the '.' is explicitly mentioned, and I wonder
7451 * whether it would simplify matters to do it this way. Who
7452 * knows. In earlier versions of the PIC patches, the
7453 * pcrel_adjust field was used to store the correction, but
7454 * since the expression is not pcrel, I felt it would be
7455 * confusing to do it this way. */
7457 if ((reloc_type
== BFD_RELOC_32
7458 || reloc_type
== BFD_RELOC_X86_64_32S
7459 || reloc_type
== BFD_RELOC_64
)
7461 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
7462 && (i
.op
[n
].imms
->X_op
== O_symbol
7463 || (i
.op
[n
].imms
->X_op
== O_add
7464 && ((symbol_get_value_expression
7465 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
7470 if (insn_start_frag
== frag_now
)
7471 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
7476 add
= insn_start_frag
->fr_fix
- insn_start_off
;
7477 for (fr
= insn_start_frag
->fr_next
;
7478 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
7480 add
+= p
- frag_now
->fr_literal
;
7484 reloc_type
= BFD_RELOC_386_GOTPC
;
7486 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
7488 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
7489 i
.op
[n
].imms
->X_add_number
+= add
;
7491 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
7492 i
.op
[n
].imms
, 0, reloc_type
);
7498 /* x86_cons_fix_new is called via the expression parsing code when a
7499 reloc is needed. We use this hook to get the correct .got reloc. */
7500 static int cons_sign
= -1;
7503 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
7504 expressionS
*exp
, bfd_reloc_code_real_type r
)
7506 r
= reloc (len
, 0, cons_sign
, r
);
7509 if (exp
->X_op
== O_secrel
)
7511 exp
->X_op
= O_symbol
;
7512 r
= BFD_RELOC_32_SECREL
;
7516 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
7519 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7520 purpose of the `.dc.a' internal pseudo-op. */
7523 x86_address_bytes (void)
7525 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
7527 return stdoutput
->arch_info
->bits_per_address
/ 8;
7530 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7532 # define lex_got(reloc, adjust, types) NULL
7534 /* Parse operands of the form
7535 <symbol>@GOTOFF+<nnn>
7536 and similar .plt or .got references.
7538 If we find one, set up the correct relocation in RELOC and copy the
7539 input string, minus the `@GOTOFF' into a malloc'd buffer for
7540 parsing by the calling routine. Return this buffer, and if ADJUST
7541 is non-null set it to the length of the string we removed from the
7542 input line. Otherwise return NULL. */
7544 lex_got (enum bfd_reloc_code_real
*rel
,
7546 i386_operand_type
*types
)
7548 /* Some of the relocations depend on the size of what field is to
7549 be relocated. But in our callers i386_immediate and i386_displacement
7550 we don't yet know the operand size (this will be set by insn
7551 matching). Hence we record the word32 relocation here,
7552 and adjust the reloc according to the real size in reloc(). */
7553 static const struct {
7556 const enum bfd_reloc_code_real rel
[2];
7557 const i386_operand_type types64
;
7559 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7560 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
7562 OPERAND_TYPE_IMM32_64
},
7564 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
7565 BFD_RELOC_X86_64_PLTOFF64
},
7566 OPERAND_TYPE_IMM64
},
7567 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
7568 BFD_RELOC_X86_64_PLT32
},
7569 OPERAND_TYPE_IMM32_32S_DISP32
},
7570 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
7571 BFD_RELOC_X86_64_GOTPLT64
},
7572 OPERAND_TYPE_IMM64_DISP64
},
7573 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
7574 BFD_RELOC_X86_64_GOTOFF64
},
7575 OPERAND_TYPE_IMM64_DISP64
},
7576 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
7577 BFD_RELOC_X86_64_GOTPCREL
},
7578 OPERAND_TYPE_IMM32_32S_DISP32
},
7579 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
7580 BFD_RELOC_X86_64_TLSGD
},
7581 OPERAND_TYPE_IMM32_32S_DISP32
},
7582 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
7583 _dummy_first_bfd_reloc_code_real
},
7584 OPERAND_TYPE_NONE
},
7585 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
7586 BFD_RELOC_X86_64_TLSLD
},
7587 OPERAND_TYPE_IMM32_32S_DISP32
},
7588 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
7589 BFD_RELOC_X86_64_GOTTPOFF
},
7590 OPERAND_TYPE_IMM32_32S_DISP32
},
7591 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
7592 BFD_RELOC_X86_64_TPOFF32
},
7593 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7594 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
7595 _dummy_first_bfd_reloc_code_real
},
7596 OPERAND_TYPE_NONE
},
7597 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
7598 BFD_RELOC_X86_64_DTPOFF32
},
7599 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7600 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
7601 _dummy_first_bfd_reloc_code_real
},
7602 OPERAND_TYPE_NONE
},
7603 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
7604 _dummy_first_bfd_reloc_code_real
},
7605 OPERAND_TYPE_NONE
},
7606 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
7607 BFD_RELOC_X86_64_GOT32
},
7608 OPERAND_TYPE_IMM32_32S_64_DISP32
},
7609 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
7610 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
7611 OPERAND_TYPE_IMM32_32S_DISP32
},
7612 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
7613 BFD_RELOC_X86_64_TLSDESC_CALL
},
7614 OPERAND_TYPE_IMM32_32S_DISP32
},
7619 #if defined (OBJ_MAYBE_ELF)
7624 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7625 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7628 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7630 int len
= gotrel
[j
].len
;
7631 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7633 if (gotrel
[j
].rel
[object_64bit
] != 0)
7636 char *tmpbuf
, *past_reloc
;
7638 *rel
= gotrel
[j
].rel
[object_64bit
];
7642 if (flag_code
!= CODE_64BIT
)
7644 types
->bitfield
.imm32
= 1;
7645 types
->bitfield
.disp32
= 1;
7648 *types
= gotrel
[j
].types64
;
7651 if (j
!= 0 && GOT_symbol
== NULL
)
7652 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
7654 /* The length of the first part of our input line. */
7655 first
= cp
- input_line_pointer
;
7657 /* The second part goes from after the reloc token until
7658 (and including) an end_of_line char or comma. */
7659 past_reloc
= cp
+ 1 + len
;
7661 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7663 second
= cp
+ 1 - past_reloc
;
7665 /* Allocate and copy string. The trailing NUL shouldn't
7666 be necessary, but be safe. */
7667 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7668 memcpy (tmpbuf
, input_line_pointer
, first
);
7669 if (second
!= 0 && *past_reloc
!= ' ')
7670 /* Replace the relocation token with ' ', so that
7671 errors like foo@GOTOFF1 will be detected. */
7672 tmpbuf
[first
++] = ' ';
7674 /* Increment length by 1 if the relocation token is
7679 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7680 tmpbuf
[first
+ second
] = '\0';
7684 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7685 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7690 /* Might be a symbol version string. Don't as_bad here. */
7699 /* Parse operands of the form
7700 <symbol>@SECREL32+<nnn>
7702 If we find one, set up the correct relocation in RELOC and copy the
7703 input string, minus the `@SECREL32' into a malloc'd buffer for
7704 parsing by the calling routine. Return this buffer, and if ADJUST
7705 is non-null set it to the length of the string we removed from the
7706 input line. Otherwise return NULL.
7708 This function is copied from the ELF version above adjusted for PE targets. */
7711 lex_got (enum bfd_reloc_code_real
*rel ATTRIBUTE_UNUSED
,
7712 int *adjust ATTRIBUTE_UNUSED
,
7713 i386_operand_type
*types
)
7719 const enum bfd_reloc_code_real rel
[2];
7720 const i386_operand_type types64
;
7724 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
7725 BFD_RELOC_32_SECREL
},
7726 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
7732 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
7733 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
7736 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
7738 int len
= gotrel
[j
].len
;
7740 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
7742 if (gotrel
[j
].rel
[object_64bit
] != 0)
7745 char *tmpbuf
, *past_reloc
;
7747 *rel
= gotrel
[j
].rel
[object_64bit
];
7753 if (flag_code
!= CODE_64BIT
)
7755 types
->bitfield
.imm32
= 1;
7756 types
->bitfield
.disp32
= 1;
7759 *types
= gotrel
[j
].types64
;
7762 /* The length of the first part of our input line. */
7763 first
= cp
- input_line_pointer
;
7765 /* The second part goes from after the reloc token until
7766 (and including) an end_of_line char or comma. */
7767 past_reloc
= cp
+ 1 + len
;
7769 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
7771 second
= cp
+ 1 - past_reloc
;
7773 /* Allocate and copy string. The trailing NUL shouldn't
7774 be necessary, but be safe. */
7775 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
7776 memcpy (tmpbuf
, input_line_pointer
, first
);
7777 if (second
!= 0 && *past_reloc
!= ' ')
7778 /* Replace the relocation token with ' ', so that
7779 errors like foo@SECLREL321 will be detected. */
7780 tmpbuf
[first
++] = ' ';
7781 memcpy (tmpbuf
+ first
, past_reloc
, second
);
7782 tmpbuf
[first
+ second
] = '\0';
7786 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7787 gotrel
[j
].str
, 1 << (5 + object_64bit
));
7792 /* Might be a symbol version string. Don't as_bad here. */
7798 bfd_reloc_code_real_type
7799 x86_cons (expressionS
*exp
, int size
)
7801 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
7803 intel_syntax
= -intel_syntax
;
7806 if (size
== 4 || (object_64bit
&& size
== 8))
7808 /* Handle @GOTOFF and the like in an expression. */
7810 char *gotfree_input_line
;
7813 save
= input_line_pointer
;
7814 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
7815 if (gotfree_input_line
)
7816 input_line_pointer
= gotfree_input_line
;
7820 if (gotfree_input_line
)
7822 /* expression () has merrily parsed up to the end of line,
7823 or a comma - in the wrong buffer. Transfer how far
7824 input_line_pointer has moved to the right buffer. */
7825 input_line_pointer
= (save
7826 + (input_line_pointer
- gotfree_input_line
)
7828 free (gotfree_input_line
);
7829 if (exp
->X_op
== O_constant
7830 || exp
->X_op
== O_absent
7831 || exp
->X_op
== O_illegal
7832 || exp
->X_op
== O_register
7833 || exp
->X_op
== O_big
)
7835 char c
= *input_line_pointer
;
7836 *input_line_pointer
= 0;
7837 as_bad (_("missing or invalid expression `%s'"), save
);
7838 *input_line_pointer
= c
;
7845 intel_syntax
= -intel_syntax
;
7848 i386_intel_simplify (exp
);
7854 signed_cons (int size
)
7856 if (flag_code
== CODE_64BIT
)
7864 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
7871 if (exp
.X_op
== O_symbol
)
7872 exp
.X_op
= O_secrel
;
7874 emit_expr (&exp
, 4);
7876 while (*input_line_pointer
++ == ',');
7878 input_line_pointer
--;
7879 demand_empty_rest_of_line ();
7883 /* Handle Vector operations. */
7886 check_VecOperations (char *op_string
, char *op_end
)
7888 const reg_entry
*mask
;
7893 && (op_end
== NULL
|| op_string
< op_end
))
7896 if (*op_string
== '{')
7900 /* Check broadcasts. */
7901 if (strncmp (op_string
, "1to", 3) == 0)
7906 goto duplicated_vec_op
;
7909 if (*op_string
== '8')
7910 bcst_type
= BROADCAST_1TO8
;
7911 else if (*op_string
== '4')
7912 bcst_type
= BROADCAST_1TO4
;
7913 else if (*op_string
== '2')
7914 bcst_type
= BROADCAST_1TO2
;
7915 else if (*op_string
== '1'
7916 && *(op_string
+1) == '6')
7918 bcst_type
= BROADCAST_1TO16
;
7923 as_bad (_("Unsupported broadcast: `%s'"), saved
);
7928 broadcast_op
.type
= bcst_type
;
7929 broadcast_op
.operand
= this_operand
;
7930 i
.broadcast
= &broadcast_op
;
7932 /* Check masking operation. */
7933 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
7935 /* k0 can't be used for write mask. */
7936 if (mask
->reg_num
== 0)
7938 as_bad (_("`%s' can't be used for write mask"),
7945 mask_op
.mask
= mask
;
7946 mask_op
.zeroing
= 0;
7947 mask_op
.operand
= this_operand
;
7953 goto duplicated_vec_op
;
7955 i
.mask
->mask
= mask
;
7957 /* Only "{z}" is allowed here. No need to check
7958 zeroing mask explicitly. */
7959 if (i
.mask
->operand
!= this_operand
)
7961 as_bad (_("invalid write mask `%s'"), saved
);
7968 /* Check zeroing-flag for masking operation. */
7969 else if (*op_string
== 'z')
7973 mask_op
.mask
= NULL
;
7974 mask_op
.zeroing
= 1;
7975 mask_op
.operand
= this_operand
;
7980 if (i
.mask
->zeroing
)
7983 as_bad (_("duplicated `%s'"), saved
);
7987 i
.mask
->zeroing
= 1;
7989 /* Only "{%k}" is allowed here. No need to check mask
7990 register explicitly. */
7991 if (i
.mask
->operand
!= this_operand
)
7993 as_bad (_("invalid zeroing-masking `%s'"),
8002 goto unknown_vec_op
;
8004 if (*op_string
!= '}')
8006 as_bad (_("missing `}' in `%s'"), saved
);
8013 /* We don't know this one. */
8014 as_bad (_("unknown vector operation: `%s'"), saved
);
8022 i386_immediate (char *imm_start
)
8024 char *save_input_line_pointer
;
8025 char *gotfree_input_line
;
8028 i386_operand_type types
;
8030 operand_type_set (&types
, ~0);
8032 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
8034 as_bad (_("at most %d immediate operands are allowed"),
8035 MAX_IMMEDIATE_OPERANDS
);
8039 exp
= &im_expressions
[i
.imm_operands
++];
8040 i
.op
[this_operand
].imms
= exp
;
8042 if (is_space_char (*imm_start
))
8045 save_input_line_pointer
= input_line_pointer
;
8046 input_line_pointer
= imm_start
;
8048 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8049 if (gotfree_input_line
)
8050 input_line_pointer
= gotfree_input_line
;
8052 exp_seg
= expression (exp
);
8056 /* Handle vector operations. */
8057 if (*input_line_pointer
== '{')
8059 input_line_pointer
= check_VecOperations (input_line_pointer
,
8061 if (input_line_pointer
== NULL
)
8065 if (*input_line_pointer
)
8066 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8068 input_line_pointer
= save_input_line_pointer
;
8069 if (gotfree_input_line
)
8071 free (gotfree_input_line
);
8073 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8074 exp
->X_op
= O_illegal
;
8077 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
8081 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8082 i386_operand_type types
, const char *imm_start
)
8084 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
8087 as_bad (_("missing or invalid immediate expression `%s'"),
8091 else if (exp
->X_op
== O_constant
)
8093 /* Size it properly later. */
8094 i
.types
[this_operand
].bitfield
.imm64
= 1;
8095 /* If not 64bit, sign extend val. */
8096 if (flag_code
!= CODE_64BIT
8097 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
8099 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
8101 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8102 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
8103 && exp_seg
!= absolute_section
8104 && exp_seg
!= text_section
8105 && exp_seg
!= data_section
8106 && exp_seg
!= bss_section
8107 && exp_seg
!= undefined_section
8108 && !bfd_is_com_section (exp_seg
))
8110 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8114 else if (!intel_syntax
&& exp_seg
== reg_section
)
8117 as_bad (_("illegal immediate register operand %s"), imm_start
);
8122 /* This is an address. The size of the address will be
8123 determined later, depending on destination register,
8124 suffix, or the default for the section. */
8125 i
.types
[this_operand
].bitfield
.imm8
= 1;
8126 i
.types
[this_operand
].bitfield
.imm16
= 1;
8127 i
.types
[this_operand
].bitfield
.imm32
= 1;
8128 i
.types
[this_operand
].bitfield
.imm32s
= 1;
8129 i
.types
[this_operand
].bitfield
.imm64
= 1;
8130 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8138 i386_scale (char *scale
)
8141 char *save
= input_line_pointer
;
8143 input_line_pointer
= scale
;
8144 val
= get_absolute_expression ();
8149 i
.log2_scale_factor
= 0;
8152 i
.log2_scale_factor
= 1;
8155 i
.log2_scale_factor
= 2;
8158 i
.log2_scale_factor
= 3;
8162 char sep
= *input_line_pointer
;
8164 *input_line_pointer
= '\0';
8165 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8167 *input_line_pointer
= sep
;
8168 input_line_pointer
= save
;
8172 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
8174 as_warn (_("scale factor of %d without an index register"),
8175 1 << i
.log2_scale_factor
);
8176 i
.log2_scale_factor
= 0;
8178 scale
= input_line_pointer
;
8179 input_line_pointer
= save
;
8184 i386_displacement (char *disp_start
, char *disp_end
)
8188 char *save_input_line_pointer
;
8189 char *gotfree_input_line
;
8191 i386_operand_type bigdisp
, types
= anydisp
;
8194 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
8196 as_bad (_("at most %d displacement operands are allowed"),
8197 MAX_MEMORY_OPERANDS
);
8201 operand_type_set (&bigdisp
, 0);
8202 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
8203 || (!current_templates
->start
->opcode_modifier
.jump
8204 && !current_templates
->start
->opcode_modifier
.jumpdword
))
8206 bigdisp
.bitfield
.disp32
= 1;
8207 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
8208 if (flag_code
== CODE_64BIT
)
8212 bigdisp
.bitfield
.disp32s
= 1;
8213 bigdisp
.bitfield
.disp64
= 1;
8216 else if ((flag_code
== CODE_16BIT
) ^ override
)
8218 bigdisp
.bitfield
.disp32
= 0;
8219 bigdisp
.bitfield
.disp16
= 1;
8224 /* For PC-relative branches, the width of the displacement
8225 is dependent upon data size, not address size. */
8226 override
= (i
.prefix
[DATA_PREFIX
] != 0);
8227 if (flag_code
== CODE_64BIT
)
8229 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
8230 bigdisp
.bitfield
.disp16
= 1;
8233 bigdisp
.bitfield
.disp32
= 1;
8234 bigdisp
.bitfield
.disp32s
= 1;
8240 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
8242 : LONG_MNEM_SUFFIX
));
8243 bigdisp
.bitfield
.disp32
= 1;
8244 if ((flag_code
== CODE_16BIT
) ^ override
)
8246 bigdisp
.bitfield
.disp32
= 0;
8247 bigdisp
.bitfield
.disp16
= 1;
8251 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8254 exp
= &disp_expressions
[i
.disp_operands
];
8255 i
.op
[this_operand
].disps
= exp
;
8257 save_input_line_pointer
= input_line_pointer
;
8258 input_line_pointer
= disp_start
;
8259 END_STRING_AND_SAVE (disp_end
);
8261 #ifndef GCC_ASM_O_HACK
8262 #define GCC_ASM_O_HACK 0
8265 END_STRING_AND_SAVE (disp_end
+ 1);
8266 if (i
.types
[this_operand
].bitfield
.baseIndex
8267 && displacement_string_end
[-1] == '+')
8269 /* This hack is to avoid a warning when using the "o"
8270 constraint within gcc asm statements.
8273 #define _set_tssldt_desc(n,addr,limit,type) \
8274 __asm__ __volatile__ ( \
8276 "movw %w1,2+%0\n\t" \
8278 "movb %b1,4+%0\n\t" \
8279 "movb %4,5+%0\n\t" \
8280 "movb $0,6+%0\n\t" \
8281 "movb %h1,7+%0\n\t" \
8283 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8285 This works great except that the output assembler ends
8286 up looking a bit weird if it turns out that there is
8287 no offset. You end up producing code that looks like:
8300 So here we provide the missing zero. */
8302 *displacement_string_end
= '0';
8305 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
8306 if (gotfree_input_line
)
8307 input_line_pointer
= gotfree_input_line
;
8309 exp_seg
= expression (exp
);
8312 if (*input_line_pointer
)
8313 as_bad (_("junk `%s' after expression"), input_line_pointer
);
8315 RESTORE_END_STRING (disp_end
+ 1);
8317 input_line_pointer
= save_input_line_pointer
;
8318 if (gotfree_input_line
)
8320 free (gotfree_input_line
);
8322 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
8323 exp
->X_op
= O_illegal
;
8326 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
8328 RESTORE_END_STRING (disp_end
);
8334 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
8335 i386_operand_type types
, const char *disp_start
)
8337 i386_operand_type bigdisp
;
8340 /* We do this to make sure that the section symbol is in
8341 the symbol table. We will ultimately change the relocation
8342 to be relative to the beginning of the section. */
8343 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
8344 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
8345 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8347 if (exp
->X_op
!= O_symbol
)
8350 if (S_IS_LOCAL (exp
->X_add_symbol
)
8351 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
8352 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
8353 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
8354 exp
->X_op
= O_subtract
;
8355 exp
->X_op_symbol
= GOT_symbol
;
8356 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
8357 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
8358 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
8359 i
.reloc
[this_operand
] = BFD_RELOC_64
;
8361 i
.reloc
[this_operand
] = BFD_RELOC_32
;
8364 else if (exp
->X_op
== O_absent
8365 || exp
->X_op
== O_illegal
8366 || exp
->X_op
== O_big
)
8369 as_bad (_("missing or invalid displacement expression `%s'"),
8374 else if (flag_code
== CODE_64BIT
8375 && !i
.prefix
[ADDR_PREFIX
]
8376 && exp
->X_op
== O_constant
)
8378 /* Since displacement is signed extended to 64bit, don't allow
8379 disp32 and turn off disp32s if they are out of range. */
8380 i
.types
[this_operand
].bitfield
.disp32
= 0;
8381 if (!fits_in_signed_long (exp
->X_add_number
))
8383 i
.types
[this_operand
].bitfield
.disp32s
= 0;
8384 if (i
.types
[this_operand
].bitfield
.baseindex
)
8386 as_bad (_("0x%lx out range of signed 32bit displacement"),
8387 (long) exp
->X_add_number
);
8393 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8394 else if (exp
->X_op
!= O_constant
8395 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
8396 && exp_seg
!= absolute_section
8397 && exp_seg
!= text_section
8398 && exp_seg
!= data_section
8399 && exp_seg
!= bss_section
8400 && exp_seg
!= undefined_section
8401 && !bfd_is_com_section (exp_seg
))
8403 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
8408 /* Check if this is a displacement only operand. */
8409 bigdisp
= i
.types
[this_operand
];
8410 bigdisp
.bitfield
.disp8
= 0;
8411 bigdisp
.bitfield
.disp16
= 0;
8412 bigdisp
.bitfield
.disp32
= 0;
8413 bigdisp
.bitfield
.disp32s
= 0;
8414 bigdisp
.bitfield
.disp64
= 0;
8415 if (operand_type_all_zero (&bigdisp
))
8416 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
8422 /* Make sure the memory operand we've been dealt is valid.
8423 Return 1 on success, 0 on a failure. */
8426 i386_index_check (const char *operand_string
)
8428 const char *kind
= "base/index";
8429 enum flag_code addr_mode
;
8431 if (i
.prefix
[ADDR_PREFIX
])
8432 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
8435 addr_mode
= flag_code
;
8437 #if INFER_ADDR_PREFIX
8438 if (i
.mem_operands
== 0)
8440 /* Infer address prefix from the first memory operand. */
8441 const reg_entry
*addr_reg
= i
.base_reg
;
8443 if (addr_reg
== NULL
)
8444 addr_reg
= i
.index_reg
;
8448 if (addr_reg
->reg_num
== RegEip
8449 || addr_reg
->reg_num
== RegEiz
8450 || addr_reg
->reg_type
.bitfield
.reg32
)
8451 addr_mode
= CODE_32BIT
;
8452 else if (flag_code
!= CODE_64BIT
8453 && addr_reg
->reg_type
.bitfield
.reg16
)
8454 addr_mode
= CODE_16BIT
;
8456 if (addr_mode
!= flag_code
)
8458 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
8460 /* Change the size of any displacement too. At most one
8461 of Disp16 or Disp32 is set.
8462 FIXME. There doesn't seem to be any real need for
8463 separate Disp16 and Disp32 flags. The same goes for
8464 Imm16 and Imm32. Removing them would probably clean
8465 up the code quite a lot. */
8466 if (flag_code
!= CODE_64BIT
8467 && (i
.types
[this_operand
].bitfield
.disp16
8468 || i
.types
[this_operand
].bitfield
.disp32
))
8469 i
.types
[this_operand
]
8470 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
8477 if (current_templates
->start
->opcode_modifier
.isstring
8478 && !current_templates
->start
->opcode_modifier
.immext
8479 && (current_templates
->end
[-1].opcode_modifier
.isstring
8482 /* Memory operands of string insns are special in that they only allow
8483 a single register (rDI, rSI, or rBX) as their memory address. */
8484 const reg_entry
*expected_reg
;
8485 static const char *di_si
[][2] =
8491 static const char *bx
[] = { "ebx", "bx", "rbx" };
8493 kind
= "string address";
8495 if (current_templates
->start
->opcode_modifier
.w
)
8497 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
8499 if (!type
.bitfield
.baseindex
8500 || ((!i
.mem_operands
!= !intel_syntax
)
8501 && current_templates
->end
[-1].operand_types
[1]
8502 .bitfield
.baseindex
))
8503 type
= current_templates
->end
[-1].operand_types
[1];
8504 expected_reg
= hash_find (reg_hash
,
8505 di_si
[addr_mode
][type
.bitfield
.esseg
]);
8509 expected_reg
= hash_find (reg_hash
, bx
[addr_mode
]);
8511 if (i
.base_reg
!= expected_reg
8513 || operand_type_check (i
.types
[this_operand
], disp
))
8515 /* The second memory operand must have the same size as
8519 && !((addr_mode
== CODE_64BIT
8520 && i
.base_reg
->reg_type
.bitfield
.reg64
)
8521 || (addr_mode
== CODE_32BIT
8522 ? i
.base_reg
->reg_type
.bitfield
.reg32
8523 : i
.base_reg
->reg_type
.bitfield
.reg16
)))
8526 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8528 intel_syntax
? '[' : '(',
8530 expected_reg
->reg_name
,
8531 intel_syntax
? ']' : ')');
8538 as_bad (_("`%s' is not a valid %s expression"),
8539 operand_string
, kind
);
8544 if (addr_mode
!= CODE_16BIT
)
8546 /* 32-bit/64-bit checks. */
8548 && (addr_mode
== CODE_64BIT
8549 ? !i
.base_reg
->reg_type
.bitfield
.reg64
8550 : !i
.base_reg
->reg_type
.bitfield
.reg32
)
8552 || (i
.base_reg
->reg_num
8553 != (addr_mode
== CODE_64BIT
? RegRip
: RegEip
))))
8555 && !i
.index_reg
->reg_type
.bitfield
.regxmm
8556 && !i
.index_reg
->reg_type
.bitfield
.regymm
8557 && !i
.index_reg
->reg_type
.bitfield
.regzmm
8558 && ((addr_mode
== CODE_64BIT
8559 ? !(i
.index_reg
->reg_type
.bitfield
.reg64
8560 || i
.index_reg
->reg_num
== RegRiz
)
8561 : !(i
.index_reg
->reg_type
.bitfield
.reg32
8562 || i
.index_reg
->reg_num
== RegEiz
))
8563 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
8568 /* 16-bit checks. */
8570 && (!i
.base_reg
->reg_type
.bitfield
.reg16
8571 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
8573 && (!i
.index_reg
->reg_type
.bitfield
.reg16
8574 || !i
.index_reg
->reg_type
.bitfield
.baseindex
8576 && i
.base_reg
->reg_num
< 6
8577 && i
.index_reg
->reg_num
>= 6
8578 && i
.log2_scale_factor
== 0))))
8585 /* Handle vector immediates. */
8588 RC_SAE_immediate (const char *imm_start
)
8590 unsigned int match_found
, j
;
8591 const char *pstr
= imm_start
;
8599 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
8601 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
8605 rc_op
.type
= RC_NamesTable
[j
].type
;
8606 rc_op
.operand
= this_operand
;
8607 i
.rounding
= &rc_op
;
8611 as_bad (_("duplicated `%s'"), imm_start
);
8614 pstr
+= RC_NamesTable
[j
].len
;
8624 as_bad (_("Missing '}': '%s'"), imm_start
);
8627 /* RC/SAE immediate string should contain nothing more. */;
8630 as_bad (_("Junk after '}': '%s'"), imm_start
);
8634 exp
= &im_expressions
[i
.imm_operands
++];
8635 i
.op
[this_operand
].imms
= exp
;
8637 exp
->X_op
= O_constant
;
8638 exp
->X_add_number
= 0;
8639 exp
->X_add_symbol
= (symbolS
*) 0;
8640 exp
->X_op_symbol
= (symbolS
*) 0;
8642 i
.types
[this_operand
].bitfield
.imm8
= 1;
8646 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8650 i386_att_operand (char *operand_string
)
8654 char *op_string
= operand_string
;
8656 if (is_space_char (*op_string
))
8659 /* We check for an absolute prefix (differentiating,
8660 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8661 if (*op_string
== ABSOLUTE_PREFIX
)
8664 if (is_space_char (*op_string
))
8666 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8669 /* Check if operand is a register. */
8670 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
8672 i386_operand_type temp
;
8674 /* Check for a segment override by searching for ':' after a
8675 segment register. */
8677 if (is_space_char (*op_string
))
8679 if (*op_string
== ':'
8680 && (r
->reg_type
.bitfield
.sreg2
8681 || r
->reg_type
.bitfield
.sreg3
))
8686 i
.seg
[i
.mem_operands
] = &es
;
8689 i
.seg
[i
.mem_operands
] = &cs
;
8692 i
.seg
[i
.mem_operands
] = &ss
;
8695 i
.seg
[i
.mem_operands
] = &ds
;
8698 i
.seg
[i
.mem_operands
] = &fs
;
8701 i
.seg
[i
.mem_operands
] = &gs
;
8705 /* Skip the ':' and whitespace. */
8707 if (is_space_char (*op_string
))
8710 if (!is_digit_char (*op_string
)
8711 && !is_identifier_char (*op_string
)
8712 && *op_string
!= '('
8713 && *op_string
!= ABSOLUTE_PREFIX
)
8715 as_bad (_("bad memory operand `%s'"), op_string
);
8718 /* Handle case of %es:*foo. */
8719 if (*op_string
== ABSOLUTE_PREFIX
)
8722 if (is_space_char (*op_string
))
8724 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
8726 goto do_memory_reference
;
8729 /* Handle vector operations. */
8730 if (*op_string
== '{')
8732 op_string
= check_VecOperations (op_string
, NULL
);
8733 if (op_string
== NULL
)
8739 as_bad (_("junk `%s' after register"), op_string
);
8743 temp
.bitfield
.baseindex
= 0;
8744 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
8746 i
.types
[this_operand
].bitfield
.unspecified
= 0;
8747 i
.op
[this_operand
].regs
= r
;
8750 else if (*op_string
== REGISTER_PREFIX
)
8752 as_bad (_("bad register name `%s'"), op_string
);
8755 else if (*op_string
== IMMEDIATE_PREFIX
)
8758 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
8760 as_bad (_("immediate operand illegal with absolute jump"));
8763 if (!i386_immediate (op_string
))
8766 else if (RC_SAE_immediate (operand_string
))
8768 /* If it is a RC or SAE immediate, do nothing. */
8771 else if (is_digit_char (*op_string
)
8772 || is_identifier_char (*op_string
)
8773 || *op_string
== '"'
8774 || *op_string
== '(')
8776 /* This is a memory reference of some sort. */
8779 /* Start and end of displacement string expression (if found). */
8780 char *displacement_string_start
;
8781 char *displacement_string_end
;
8784 do_memory_reference
:
8785 if ((i
.mem_operands
== 1
8786 && !current_templates
->start
->opcode_modifier
.isstring
)
8787 || i
.mem_operands
== 2)
8789 as_bad (_("too many memory references for `%s'"),
8790 current_templates
->start
->name
);
8794 /* Check for base index form. We detect the base index form by
8795 looking for an ')' at the end of the operand, searching
8796 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8798 base_string
= op_string
+ strlen (op_string
);
8800 /* Handle vector operations. */
8801 vop_start
= strchr (op_string
, '{');
8802 if (vop_start
&& vop_start
< base_string
)
8804 if (check_VecOperations (vop_start
, base_string
) == NULL
)
8806 base_string
= vop_start
;
8810 if (is_space_char (*base_string
))
8813 /* If we only have a displacement, set-up for it to be parsed later. */
8814 displacement_string_start
= op_string
;
8815 displacement_string_end
= base_string
+ 1;
8817 if (*base_string
== ')')
8820 unsigned int parens_balanced
= 1;
8821 /* We've already checked that the number of left & right ()'s are
8822 equal, so this loop will not be infinite. */
8826 if (*base_string
== ')')
8828 if (*base_string
== '(')
8831 while (parens_balanced
);
8833 temp_string
= base_string
;
8835 /* Skip past '(' and whitespace. */
8837 if (is_space_char (*base_string
))
8840 if (*base_string
== ','
8841 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
8844 displacement_string_end
= temp_string
;
8846 i
.types
[this_operand
].bitfield
.baseindex
= 1;
8850 base_string
= end_op
;
8851 if (is_space_char (*base_string
))
8855 /* There may be an index reg or scale factor here. */
8856 if (*base_string
== ',')
8859 if (is_space_char (*base_string
))
8862 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
8865 base_string
= end_op
;
8866 if (is_space_char (*base_string
))
8868 if (*base_string
== ',')
8871 if (is_space_char (*base_string
))
8874 else if (*base_string
!= ')')
8876 as_bad (_("expecting `,' or `)' "
8877 "after index register in `%s'"),
8882 else if (*base_string
== REGISTER_PREFIX
)
8884 end_op
= strchr (base_string
, ',');
8887 as_bad (_("bad register name `%s'"), base_string
);
8891 /* Check for scale factor. */
8892 if (*base_string
!= ')')
8894 char *end_scale
= i386_scale (base_string
);
8899 base_string
= end_scale
;
8900 if (is_space_char (*base_string
))
8902 if (*base_string
!= ')')
8904 as_bad (_("expecting `)' "
8905 "after scale factor in `%s'"),
8910 else if (!i
.index_reg
)
8912 as_bad (_("expecting index register or scale factor "
8913 "after `,'; got '%c'"),
8918 else if (*base_string
!= ')')
8920 as_bad (_("expecting `,' or `)' "
8921 "after base register in `%s'"),
8926 else if (*base_string
== REGISTER_PREFIX
)
8928 end_op
= strchr (base_string
, ',');
8931 as_bad (_("bad register name `%s'"), base_string
);
8936 /* If there's an expression beginning the operand, parse it,
8937 assuming displacement_string_start and
8938 displacement_string_end are meaningful. */
8939 if (displacement_string_start
!= displacement_string_end
)
8941 if (!i386_displacement (displacement_string_start
,
8942 displacement_string_end
))
8946 /* Special case for (%dx) while doing input/output op. */
8948 && operand_type_equal (&i
.base_reg
->reg_type
,
8949 ®16_inoutportreg
)
8951 && i
.log2_scale_factor
== 0
8952 && i
.seg
[i
.mem_operands
] == 0
8953 && !operand_type_check (i
.types
[this_operand
], disp
))
8955 i
.types
[this_operand
] = inoutportreg
;
8959 if (i386_index_check (operand_string
) == 0)
8961 i
.types
[this_operand
].bitfield
.mem
= 1;
8966 /* It's not a memory operand; argh! */
8967 as_bad (_("invalid char %s beginning operand %d `%s'"),
8968 output_invalid (*op_string
),
8973 return 1; /* Normal return. */
8976 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8977 that an rs_machine_dependent frag may reach. */
8980 i386_frag_max_var (fragS
*frag
)
8982 /* The only relaxable frags are for jumps.
8983 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8984 gas_assert (frag
->fr_type
== rs_machine_dependent
);
8985 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
8988 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8990 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
8992 /* STT_GNU_IFUNC symbol must go through PLT. */
8993 if ((symbol_get_bfdsym (fr_symbol
)->flags
8994 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
8997 if (!S_IS_EXTERNAL (fr_symbol
))
8998 /* Symbol may be weak or local. */
8999 return !S_IS_WEAK (fr_symbol
);
9001 /* Global symbols with non-default visibility can't be preempted. */
9002 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
9005 if (fr_var
!= NO_RELOC
)
9006 switch ((enum bfd_reloc_code_real
) fr_var
)
9008 case BFD_RELOC_386_PLT32
:
9009 case BFD_RELOC_X86_64_PLT32
:
9010 /* Symbol with PLT relocatin may be preempted. */
9016 /* Global symbols with default visibility in a shared library may be
9017 preempted by another definition. */
9022 /* md_estimate_size_before_relax()
9024 Called just before relax() for rs_machine_dependent frags. The x86
9025 assembler uses these frags to handle variable size jump
9028 Any symbol that is now undefined will not become defined.
9029 Return the correct fr_subtype in the frag.
9030 Return the initial "guess for variable size of frag" to caller.
9031 The guess is actually the growth beyond the fixed part. Whatever
9032 we do to grow the fixed or variable part contributes to our
9036 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
9038 /* We've already got fragP->fr_subtype right; all we have to do is
9039 check for un-relaxable symbols. On an ELF system, we can't relax
9040 an externally visible symbol, because it may be overridden by a
9042 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
9043 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9045 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
9048 #if defined (OBJ_COFF) && defined (TE_PE)
9049 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
9050 && S_IS_WEAK (fragP
->fr_symbol
))
9054 /* Symbol is undefined in this segment, or we need to keep a
9055 reloc so that weak symbols can be overridden. */
9056 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
9057 enum bfd_reloc_code_real reloc_type
;
9058 unsigned char *opcode
;
9061 if (fragP
->fr_var
!= NO_RELOC
)
9062 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
9064 reloc_type
= BFD_RELOC_16_PCREL
;
9066 reloc_type
= BFD_RELOC_32_PCREL
;
9068 old_fr_fix
= fragP
->fr_fix
;
9069 opcode
= (unsigned char *) fragP
->fr_opcode
;
9071 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
9074 /* Make jmp (0xeb) a (d)word displacement jump. */
9076 fragP
->fr_fix
+= size
;
9077 fix_new (fragP
, old_fr_fix
, size
,
9079 fragP
->fr_offset
, 1,
9085 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
9087 /* Negate the condition, and branch past an
9088 unconditional jump. */
9091 /* Insert an unconditional jump. */
9093 /* We added two extra opcode bytes, and have a two byte
9095 fragP
->fr_fix
+= 2 + 2;
9096 fix_new (fragP
, old_fr_fix
+ 2, 2,
9098 fragP
->fr_offset
, 1,
9105 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
9110 fixP
= fix_new (fragP
, old_fr_fix
, 1,
9112 fragP
->fr_offset
, 1,
9114 fixP
->fx_signed
= 1;
9118 /* This changes the byte-displacement jump 0x7N
9119 to the (d)word-displacement jump 0x0f,0x8N. */
9120 opcode
[1] = opcode
[0] + 0x10;
9121 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9122 /* We've added an opcode byte. */
9123 fragP
->fr_fix
+= 1 + size
;
9124 fix_new (fragP
, old_fr_fix
+ 1, size
,
9126 fragP
->fr_offset
, 1,
9131 BAD_CASE (fragP
->fr_subtype
);
9135 return fragP
->fr_fix
- old_fr_fix
;
9138 /* Guess size depending on current relax state. Initially the relax
9139 state will correspond to a short jump and we return 1, because
9140 the variable part of the frag (the branch offset) is one byte
9141 long. However, we can relax a section more than once and in that
9142 case we must either set fr_subtype back to the unrelaxed state,
9143 or return the value for the appropriate branch. */
9144 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
9147 /* Called after relax() is finished.
9149 In: Address of frag.
9150 fr_type == rs_machine_dependent.
9151 fr_subtype is what the address relaxed to.
9153 Out: Any fixSs and constants are set up.
9154 Caller will turn frag into a ".space 0". */
9157 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
9160 unsigned char *opcode
;
9161 unsigned char *where_to_put_displacement
= NULL
;
9162 offsetT target_address
;
9163 offsetT opcode_address
;
9164 unsigned int extension
= 0;
9165 offsetT displacement_from_opcode_start
;
9167 opcode
= (unsigned char *) fragP
->fr_opcode
;
9169 /* Address we want to reach in file space. */
9170 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
9172 /* Address opcode resides at in file space. */
9173 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
9175 /* Displacement from opcode start to fill into instruction. */
9176 displacement_from_opcode_start
= target_address
- opcode_address
;
9178 if ((fragP
->fr_subtype
& BIG
) == 0)
9180 /* Don't have to change opcode. */
9181 extension
= 1; /* 1 opcode + 1 displacement */
9182 where_to_put_displacement
= &opcode
[1];
9186 if (no_cond_jump_promotion
9187 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
9188 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
9189 _("long jump required"));
9191 switch (fragP
->fr_subtype
)
9193 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
9194 extension
= 4; /* 1 opcode + 4 displacement */
9196 where_to_put_displacement
= &opcode
[1];
9199 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
9200 extension
= 2; /* 1 opcode + 2 displacement */
9202 where_to_put_displacement
= &opcode
[1];
9205 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
9206 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
9207 extension
= 5; /* 2 opcode + 4 displacement */
9208 opcode
[1] = opcode
[0] + 0x10;
9209 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9210 where_to_put_displacement
= &opcode
[2];
9213 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
9214 extension
= 3; /* 2 opcode + 2 displacement */
9215 opcode
[1] = opcode
[0] + 0x10;
9216 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
9217 where_to_put_displacement
= &opcode
[2];
9220 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
9225 where_to_put_displacement
= &opcode
[3];
9229 BAD_CASE (fragP
->fr_subtype
);
9234 /* If size if less then four we are sure that the operand fits,
9235 but if it's 4, then it could be that the displacement is larger
9237 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
9239 && ((addressT
) (displacement_from_opcode_start
- extension
9240 + ((addressT
) 1 << 31))
9241 > (((addressT
) 2 << 31) - 1)))
9243 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
9244 _("jump target out of range"));
9245 /* Make us emit 0. */
9246 displacement_from_opcode_start
= extension
;
9248 /* Now put displacement after opcode. */
9249 md_number_to_chars ((char *) where_to_put_displacement
,
9250 (valueT
) (displacement_from_opcode_start
- extension
),
9251 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
9252 fragP
->fr_fix
+= extension
;
9255 /* Apply a fixup (fixP) to segment data, once it has been determined
9256 by our caller that we have all the info we need to fix it up.
9258 Parameter valP is the pointer to the value of the bits.
9260 On the 386, immediates, displacements, and data pointers are all in
9261 the same (little-endian) format, so we don't need to care about which
9265 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
9267 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
9268 valueT value
= *valP
;
9270 #if !defined (TE_Mach)
9273 switch (fixP
->fx_r_type
)
9279 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
9282 case BFD_RELOC_X86_64_32S
:
9283 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
9286 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
9289 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
9294 if (fixP
->fx_addsy
!= NULL
9295 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
9296 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
9297 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
9298 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
9299 && !use_rela_relocations
)
9301 /* This is a hack. There should be a better way to handle this.
9302 This covers for the fact that bfd_install_relocation will
9303 subtract the current location (for partial_inplace, PC relative
9304 relocations); see more below. */
9308 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
9311 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9313 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9316 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
9319 || (symbol_section_p (fixP
->fx_addsy
)
9320 && sym_seg
!= absolute_section
))
9321 && !generic_force_reloc (fixP
))
9323 /* Yes, we add the values in twice. This is because
9324 bfd_install_relocation subtracts them out again. I think
9325 bfd_install_relocation is broken, but I don't dare change
9327 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9331 #if defined (OBJ_COFF) && defined (TE_PE)
9332 /* For some reason, the PE format does not store a
9333 section address offset for a PC relative symbol. */
9334 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
9335 || S_IS_WEAK (fixP
->fx_addsy
))
9336 value
+= md_pcrel_from (fixP
);
9339 #if defined (OBJ_COFF) && defined (TE_PE)
9340 if (fixP
->fx_addsy
!= NULL
9341 && S_IS_WEAK (fixP
->fx_addsy
)
9342 /* PR 16858: Do not modify weak function references. */
9343 && ! fixP
->fx_pcrel
)
9345 #if !defined (TE_PEP)
9346 /* For x86 PE weak function symbols are neither PC-relative
9347 nor do they set S_IS_FUNCTION. So the only reliable way
9348 to detect them is to check the flags of their containing
9350 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
9351 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
9355 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9359 /* Fix a few things - the dynamic linker expects certain values here,
9360 and we must not disappoint it. */
9361 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9362 if (IS_ELF
&& fixP
->fx_addsy
)
9363 switch (fixP
->fx_r_type
)
9365 case BFD_RELOC_386_PLT32
:
9366 case BFD_RELOC_X86_64_PLT32
:
9367 /* Make the jump instruction point to the address of the operand. At
9368 runtime we merely add the offset to the actual PLT entry. */
9372 case BFD_RELOC_386_TLS_GD
:
9373 case BFD_RELOC_386_TLS_LDM
:
9374 case BFD_RELOC_386_TLS_IE_32
:
9375 case BFD_RELOC_386_TLS_IE
:
9376 case BFD_RELOC_386_TLS_GOTIE
:
9377 case BFD_RELOC_386_TLS_GOTDESC
:
9378 case BFD_RELOC_X86_64_TLSGD
:
9379 case BFD_RELOC_X86_64_TLSLD
:
9380 case BFD_RELOC_X86_64_GOTTPOFF
:
9381 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
9382 value
= 0; /* Fully resolved at runtime. No addend. */
9384 case BFD_RELOC_386_TLS_LE
:
9385 case BFD_RELOC_386_TLS_LDO_32
:
9386 case BFD_RELOC_386_TLS_LE_32
:
9387 case BFD_RELOC_X86_64_DTPOFF32
:
9388 case BFD_RELOC_X86_64_DTPOFF64
:
9389 case BFD_RELOC_X86_64_TPOFF32
:
9390 case BFD_RELOC_X86_64_TPOFF64
:
9391 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9394 case BFD_RELOC_386_TLS_DESC_CALL
:
9395 case BFD_RELOC_X86_64_TLSDESC_CALL
:
9396 value
= 0; /* Fully resolved at runtime. No addend. */
9397 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
9401 case BFD_RELOC_VTABLE_INHERIT
:
9402 case BFD_RELOC_VTABLE_ENTRY
:
9409 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9411 #endif /* !defined (TE_Mach) */
9413 /* Are we finished with this relocation now? */
9414 if (fixP
->fx_addsy
== NULL
)
9416 #if defined (OBJ_COFF) && defined (TE_PE)
9417 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
9420 /* Remember value for tc_gen_reloc. */
9421 fixP
->fx_addnumber
= value
;
9422 /* Clear out the frag for now. */
9426 else if (use_rela_relocations
)
9428 fixP
->fx_no_overflow
= 1;
9429 /* Remember value for tc_gen_reloc. */
9430 fixP
->fx_addnumber
= value
;
9434 md_number_to_chars (p
, value
, fixP
->fx_size
);
9438 md_atof (int type
, char *litP
, int *sizeP
)
9440 /* This outputs the LITTLENUMs in REVERSE order;
9441 in accord with the bigendian 386. */
9442 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
9445 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
9448 output_invalid (int c
)
9451 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9454 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
9455 "(0x%x)", (unsigned char) c
);
9456 return output_invalid_buf
;
9459 /* REG_STRING starts *before* REGISTER_PREFIX. */
9461 static const reg_entry
*
9462 parse_real_register (char *reg_string
, char **end_op
)
9464 char *s
= reg_string
;
9466 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
9469 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9470 if (*s
== REGISTER_PREFIX
)
9473 if (is_space_char (*s
))
9477 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
9479 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
9480 return (const reg_entry
*) NULL
;
9484 /* For naked regs, make sure that we are not dealing with an identifier.
9485 This prevents confusing an identifier like `eax_var' with register
9487 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
9488 return (const reg_entry
*) NULL
;
9492 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
9494 /* Handle floating point regs, allowing spaces in the (i) part. */
9495 if (r
== i386_regtab
/* %st is first entry of table */)
9497 if (is_space_char (*s
))
9502 if (is_space_char (*s
))
9504 if (*s
>= '0' && *s
<= '7')
9508 if (is_space_char (*s
))
9513 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
9518 /* We have "%st(" then garbage. */
9519 return (const reg_entry
*) NULL
;
9523 if (r
== NULL
|| allow_pseudo_reg
)
9526 if (operand_type_all_zero (&r
->reg_type
))
9527 return (const reg_entry
*) NULL
;
9529 if ((r
->reg_type
.bitfield
.reg32
9530 || r
->reg_type
.bitfield
.sreg3
9531 || r
->reg_type
.bitfield
.control
9532 || r
->reg_type
.bitfield
.debug
9533 || r
->reg_type
.bitfield
.test
)
9534 && !cpu_arch_flags
.bitfield
.cpui386
)
9535 return (const reg_entry
*) NULL
;
9537 if (r
->reg_type
.bitfield
.floatreg
9538 && !cpu_arch_flags
.bitfield
.cpu8087
9539 && !cpu_arch_flags
.bitfield
.cpu287
9540 && !cpu_arch_flags
.bitfield
.cpu387
)
9541 return (const reg_entry
*) NULL
;
9543 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
9544 return (const reg_entry
*) NULL
;
9546 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
9547 return (const reg_entry
*) NULL
;
9549 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
9550 return (const reg_entry
*) NULL
;
9552 if ((r
->reg_type
.bitfield
.regzmm
|| r
->reg_type
.bitfield
.regmask
)
9553 && !cpu_arch_flags
.bitfield
.cpuavx512f
)
9554 return (const reg_entry
*) NULL
;
9556 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9557 if (!allow_index_reg
9558 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
9559 return (const reg_entry
*) NULL
;
9561 /* Upper 16 vector register is only available with VREX in 64bit
9563 if ((r
->reg_flags
& RegVRex
))
9565 if (!cpu_arch_flags
.bitfield
.cpuvrex
9566 || flag_code
!= CODE_64BIT
)
9567 return (const reg_entry
*) NULL
;
9572 if (((r
->reg_flags
& (RegRex64
| RegRex
))
9573 || r
->reg_type
.bitfield
.reg64
)
9574 && (!cpu_arch_flags
.bitfield
.cpulm
9575 || !operand_type_equal (&r
->reg_type
, &control
))
9576 && flag_code
!= CODE_64BIT
)
9577 return (const reg_entry
*) NULL
;
9579 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
9580 return (const reg_entry
*) NULL
;
9585 /* REG_STRING starts *before* REGISTER_PREFIX. */
9587 static const reg_entry
*
9588 parse_register (char *reg_string
, char **end_op
)
9592 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
9593 r
= parse_real_register (reg_string
, end_op
);
9598 char *save
= input_line_pointer
;
9602 input_line_pointer
= reg_string
;
9603 c
= get_symbol_name (®_string
);
9604 symbolP
= symbol_find (reg_string
);
9605 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
9607 const expressionS
*e
= symbol_get_value_expression (symbolP
);
9609 know (e
->X_op
== O_register
);
9610 know (e
->X_add_number
>= 0
9611 && (valueT
) e
->X_add_number
< i386_regtab_size
);
9612 r
= i386_regtab
+ e
->X_add_number
;
9613 if ((r
->reg_flags
& RegVRex
))
9615 *end_op
= input_line_pointer
;
9617 *input_line_pointer
= c
;
9618 input_line_pointer
= save
;
9624 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
9627 char *end
= input_line_pointer
;
9630 r
= parse_register (name
, &input_line_pointer
);
9631 if (r
&& end
<= input_line_pointer
)
9633 *nextcharP
= *input_line_pointer
;
9634 *input_line_pointer
= 0;
9635 e
->X_op
= O_register
;
9636 e
->X_add_number
= r
- i386_regtab
;
9639 input_line_pointer
= end
;
9641 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
9645 md_operand (expressionS
*e
)
9650 switch (*input_line_pointer
)
9652 case REGISTER_PREFIX
:
9653 r
= parse_real_register (input_line_pointer
, &end
);
9656 e
->X_op
= O_register
;
9657 e
->X_add_number
= r
- i386_regtab
;
9658 input_line_pointer
= end
;
9663 gas_assert (intel_syntax
);
9664 end
= input_line_pointer
++;
9666 if (*input_line_pointer
== ']')
9668 ++input_line_pointer
;
9669 e
->X_op_symbol
= make_expr_symbol (e
);
9670 e
->X_add_symbol
= NULL
;
9671 e
->X_add_number
= 0;
9677 input_line_pointer
= end
;
9684 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9685 const char *md_shortopts
= "kVQ:sqn";
9687 const char *md_shortopts
= "qn";
9690 #define OPTION_32 (OPTION_MD_BASE + 0)
9691 #define OPTION_64 (OPTION_MD_BASE + 1)
9692 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9693 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9694 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9695 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9696 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9697 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9698 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9699 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9700 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9701 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9702 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9703 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9704 #define OPTION_X32 (OPTION_MD_BASE + 14)
9705 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9706 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9707 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9708 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9709 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9710 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9711 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9712 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9713 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9714 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
9715 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
9717 struct option md_longopts
[] =
9719 {"32", no_argument
, NULL
, OPTION_32
},
9720 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9721 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9722 {"64", no_argument
, NULL
, OPTION_64
},
9724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9725 {"x32", no_argument
, NULL
, OPTION_X32
},
9726 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
9728 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
9729 {"march", required_argument
, NULL
, OPTION_MARCH
},
9730 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9731 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
9732 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
9733 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
9734 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
9735 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
9736 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
9737 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
9738 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
9739 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
9740 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
9741 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
9742 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
9743 # if defined (TE_PE) || defined (TE_PEP)
9744 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
9746 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
9747 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
9748 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
9749 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
9750 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
9751 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
9752 {NULL
, no_argument
, NULL
, 0}
9754 size_t md_longopts_size
= sizeof (md_longopts
);
9757 md_parse_option (int c
, const char *arg
)
9760 char *arch
, *next
, *saved
;
9765 optimize_align_code
= 0;
9772 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9773 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9774 should be emitted or not. FIXME: Not implemented. */
9778 /* -V: SVR4 argument to print version ID. */
9780 print_version_id ();
9783 /* -k: Ignore for FreeBSD compatibility. */
9788 /* -s: On i386 Solaris, this tells the native assembler to use
9789 .stab instead of .stab.excl. We always use .stab anyhow. */
9792 case OPTION_MSHARED
:
9796 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9797 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9800 const char **list
, **l
;
9802 list
= bfd_target_list ();
9803 for (l
= list
; *l
!= NULL
; l
++)
9804 if (CONST_STRNEQ (*l
, "elf64-x86-64")
9805 || strcmp (*l
, "coff-x86-64") == 0
9806 || strcmp (*l
, "pe-x86-64") == 0
9807 || strcmp (*l
, "pei-x86-64") == 0
9808 || strcmp (*l
, "mach-o-x86-64") == 0)
9810 default_arch
= "x86_64";
9814 as_fatal (_("no compiled in support for x86_64"));
9820 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9824 const char **list
, **l
;
9826 list
= bfd_target_list ();
9827 for (l
= list
; *l
!= NULL
; l
++)
9828 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
9830 default_arch
= "x86_64:32";
9834 as_fatal (_("no compiled in support for 32bit x86_64"));
9838 as_fatal (_("32bit x86_64 is only supported for ELF"));
9843 default_arch
= "i386";
9847 #ifdef SVR4_COMMENT_CHARS
9852 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
9854 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
9858 i386_comment_chars
= n
;
9864 saved
= xstrdup (arg
);
9866 /* Allow -march=+nosse. */
9872 as_fatal (_("invalid -march= option: `%s'"), arg
);
9873 next
= strchr (arch
, '+');
9876 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9878 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
9881 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
9884 cpu_arch_name
= cpu_arch
[j
].name
;
9885 cpu_sub_arch_name
= NULL
;
9886 cpu_arch_flags
= cpu_arch
[j
].flags
;
9887 cpu_arch_isa
= cpu_arch
[j
].type
;
9888 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
9889 if (!cpu_arch_tune_set
)
9891 cpu_arch_tune
= cpu_arch_isa
;
9892 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
9896 else if (*cpu_arch
[j
].name
== '.'
9897 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
9899 /* ISA entension. */
9900 i386_cpu_flags flags
;
9902 flags
= cpu_flags_or (cpu_arch_flags
,
9905 if (!valid_iamcu_cpu_flags (&flags
))
9906 as_fatal (_("`%s' isn't valid for Intel MCU"), arch
);
9907 else if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9909 if (cpu_sub_arch_name
)
9911 char *name
= cpu_sub_arch_name
;
9912 cpu_sub_arch_name
= concat (name
,
9914 (const char *) NULL
);
9918 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
9919 cpu_arch_flags
= flags
;
9920 cpu_arch_isa_flags
= flags
;
9926 if (j
>= ARRAY_SIZE (cpu_arch
))
9928 /* Disable an ISA entension. */
9929 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
9930 if (strcmp (arch
, cpu_noarch
[j
].name
) == 0)
9932 i386_cpu_flags flags
;
9934 flags
= cpu_flags_and_not (cpu_arch_flags
,
9935 cpu_noarch
[j
].flags
);
9936 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
9938 if (cpu_sub_arch_name
)
9940 char *name
= cpu_sub_arch_name
;
9941 cpu_sub_arch_name
= concat (arch
,
9942 (const char *) NULL
);
9946 cpu_sub_arch_name
= xstrdup (arch
);
9947 cpu_arch_flags
= flags
;
9948 cpu_arch_isa_flags
= flags
;
9953 if (j
>= ARRAY_SIZE (cpu_noarch
))
9954 j
= ARRAY_SIZE (cpu_arch
);
9957 if (j
>= ARRAY_SIZE (cpu_arch
))
9958 as_fatal (_("invalid -march= option: `%s'"), arg
);
9962 while (next
!= NULL
);
9968 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9969 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
9971 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
9973 cpu_arch_tune_set
= 1;
9974 cpu_arch_tune
= cpu_arch
[j
].type
;
9975 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
9979 if (j
>= ARRAY_SIZE (cpu_arch
))
9980 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
9983 case OPTION_MMNEMONIC
:
9984 if (strcasecmp (arg
, "att") == 0)
9986 else if (strcasecmp (arg
, "intel") == 0)
9989 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
9992 case OPTION_MSYNTAX
:
9993 if (strcasecmp (arg
, "att") == 0)
9995 else if (strcasecmp (arg
, "intel") == 0)
9998 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
10001 case OPTION_MINDEX_REG
:
10002 allow_index_reg
= 1;
10005 case OPTION_MNAKED_REG
:
10006 allow_naked_reg
= 1;
10009 case OPTION_MOLD_GCC
:
10013 case OPTION_MSSE2AVX
:
10017 case OPTION_MSSE_CHECK
:
10018 if (strcasecmp (arg
, "error") == 0)
10019 sse_check
= check_error
;
10020 else if (strcasecmp (arg
, "warning") == 0)
10021 sse_check
= check_warning
;
10022 else if (strcasecmp (arg
, "none") == 0)
10023 sse_check
= check_none
;
10025 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
10028 case OPTION_MOPERAND_CHECK
:
10029 if (strcasecmp (arg
, "error") == 0)
10030 operand_check
= check_error
;
10031 else if (strcasecmp (arg
, "warning") == 0)
10032 operand_check
= check_warning
;
10033 else if (strcasecmp (arg
, "none") == 0)
10034 operand_check
= check_none
;
10036 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
10039 case OPTION_MAVXSCALAR
:
10040 if (strcasecmp (arg
, "128") == 0)
10041 avxscalar
= vex128
;
10042 else if (strcasecmp (arg
, "256") == 0)
10043 avxscalar
= vex256
;
10045 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
10048 case OPTION_MADD_BND_PREFIX
:
10049 add_bnd_prefix
= 1;
10052 case OPTION_MEVEXLIG
:
10053 if (strcmp (arg
, "128") == 0)
10054 evexlig
= evexl128
;
10055 else if (strcmp (arg
, "256") == 0)
10056 evexlig
= evexl256
;
10057 else if (strcmp (arg
, "512") == 0)
10058 evexlig
= evexl512
;
10060 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
10063 case OPTION_MEVEXRCIG
:
10064 if (strcmp (arg
, "rne") == 0)
10066 else if (strcmp (arg
, "rd") == 0)
10068 else if (strcmp (arg
, "ru") == 0)
10070 else if (strcmp (arg
, "rz") == 0)
10073 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
10076 case OPTION_MEVEXWIG
:
10077 if (strcmp (arg
, "0") == 0)
10079 else if (strcmp (arg
, "1") == 0)
10082 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
10085 # if defined (TE_PE) || defined (TE_PEP)
10086 case OPTION_MBIG_OBJ
:
10091 case OPTION_MOMIT_LOCK_PREFIX
:
10092 if (strcasecmp (arg
, "yes") == 0)
10093 omit_lock_prefix
= 1;
10094 else if (strcasecmp (arg
, "no") == 0)
10095 omit_lock_prefix
= 0;
10097 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
10100 case OPTION_MFENCE_AS_LOCK_ADD
:
10101 if (strcasecmp (arg
, "yes") == 0)
10103 else if (strcasecmp (arg
, "no") == 0)
10106 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
10109 case OPTION_MRELAX_RELOCATIONS
:
10110 if (strcasecmp (arg
, "yes") == 0)
10111 generate_relax_relocations
= 1;
10112 else if (strcasecmp (arg
, "no") == 0)
10113 generate_relax_relocations
= 0;
10115 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
10118 case OPTION_MAMD64
:
10122 case OPTION_MINTEL64
:
10132 #define MESSAGE_TEMPLATE \
10136 output_message (FILE *stream
, char *p
, char *message
, char *start
,
10137 int *left_p
, const char *name
, int len
)
10139 int size
= sizeof (MESSAGE_TEMPLATE
);
10140 int left
= *left_p
;
10142 /* Reserve 2 spaces for ", " or ",\0" */
10145 /* Check if there is any room. */
10153 p
= mempcpy (p
, name
, len
);
10157 /* Output the current message now and start a new one. */
10160 fprintf (stream
, "%s\n", message
);
10162 left
= size
- (start
- message
) - len
- 2;
10164 gas_assert (left
>= 0);
10166 p
= mempcpy (p
, name
, len
);
10174 show_arch (FILE *stream
, int ext
, int check
)
10176 static char message
[] = MESSAGE_TEMPLATE
;
10177 char *start
= message
+ 27;
10179 int size
= sizeof (MESSAGE_TEMPLATE
);
10186 left
= size
- (start
- message
);
10187 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
10189 /* Should it be skipped? */
10190 if (cpu_arch
[j
].skip
)
10193 name
= cpu_arch
[j
].name
;
10194 len
= cpu_arch
[j
].len
;
10197 /* It is an extension. Skip if we aren't asked to show it. */
10208 /* It is an processor. Skip if we show only extension. */
10211 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
10213 /* It is an impossible processor - skip. */
10217 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
10220 /* Display disabled extensions. */
10222 for (j
= 0; j
< ARRAY_SIZE (cpu_noarch
); j
++)
10224 name
= cpu_noarch
[j
].name
;
10225 len
= cpu_noarch
[j
].len
;
10226 p
= output_message (stream
, p
, message
, start
, &left
, name
,
10231 fprintf (stream
, "%s\n", message
);
10235 md_show_usage (FILE *stream
)
10237 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10238 fprintf (stream
, _("\
10240 -V print assembler version number\n\
10243 fprintf (stream
, _("\
10244 -n Do not optimize code alignment\n\
10245 -q quieten some warnings\n"));
10246 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10247 fprintf (stream
, _("\
10250 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10251 || defined (TE_PE) || defined (TE_PEP))
10252 fprintf (stream
, _("\
10253 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10255 #ifdef SVR4_COMMENT_CHARS
10256 fprintf (stream
, _("\
10257 --divide do not treat `/' as a comment character\n"));
10259 fprintf (stream
, _("\
10260 --divide ignored\n"));
10262 fprintf (stream
, _("\
10263 -march=CPU[,+EXTENSION...]\n\
10264 generate code for CPU and EXTENSION, CPU is one of:\n"));
10265 show_arch (stream
, 0, 1);
10266 fprintf (stream
, _("\
10267 EXTENSION is combination of:\n"));
10268 show_arch (stream
, 1, 0);
10269 fprintf (stream
, _("\
10270 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10271 show_arch (stream
, 0, 0);
10272 fprintf (stream
, _("\
10273 -msse2avx encode SSE instructions with VEX prefix\n"));
10274 fprintf (stream
, _("\
10275 -msse-check=[none|error|warning]\n\
10276 check SSE instructions\n"));
10277 fprintf (stream
, _("\
10278 -moperand-check=[none|error|warning]\n\
10279 check operand combinations for validity\n"));
10280 fprintf (stream
, _("\
10281 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10283 fprintf (stream
, _("\
10284 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10286 fprintf (stream
, _("\
10287 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10288 for EVEX.W bit ignored instructions\n"));
10289 fprintf (stream
, _("\
10290 -mevexrcig=[rne|rd|ru|rz]\n\
10291 encode EVEX instructions with specific EVEX.RC value\n\
10292 for SAE-only ignored instructions\n"));
10293 fprintf (stream
, _("\
10294 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10295 fprintf (stream
, _("\
10296 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10297 fprintf (stream
, _("\
10298 -mindex-reg support pseudo index registers\n"));
10299 fprintf (stream
, _("\
10300 -mnaked-reg don't require `%%' prefix for registers\n"));
10301 fprintf (stream
, _("\
10302 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10303 fprintf (stream
, _("\
10304 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10305 fprintf (stream
, _("\
10306 -mshared disable branch optimization for shared code\n"));
10307 # if defined (TE_PE) || defined (TE_PEP)
10308 fprintf (stream
, _("\
10309 -mbig-obj generate big object files\n"));
10311 fprintf (stream
, _("\
10312 -momit-lock-prefix=[no|yes]\n\
10313 strip all lock prefixes\n"));
10314 fprintf (stream
, _("\
10315 -mfence-as-lock-add=[no|yes]\n\
10316 encode lfence, mfence and sfence as\n\
10317 lock addl $0x0, (%%{re}sp)\n"));
10318 fprintf (stream
, _("\
10319 -mrelax-relocations=[no|yes]\n\
10320 generate relax relocations\n"));
10321 fprintf (stream
, _("\
10322 -mamd64 accept only AMD64 ISA\n"));
10323 fprintf (stream
, _("\
10324 -mintel64 accept only Intel64 ISA\n"));
10327 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10328 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10329 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10331 /* Pick the target format to use. */
10334 i386_target_format (void)
10336 if (!strncmp (default_arch
, "x86_64", 6))
10338 update_code_flag (CODE_64BIT
, 1);
10339 if (default_arch
[6] == '\0')
10340 x86_elf_abi
= X86_64_ABI
;
10342 x86_elf_abi
= X86_64_X32_ABI
;
10344 else if (!strcmp (default_arch
, "i386"))
10345 update_code_flag (CODE_32BIT
, 1);
10346 else if (!strcmp (default_arch
, "iamcu"))
10348 update_code_flag (CODE_32BIT
, 1);
10349 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
10351 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
10352 cpu_arch_name
= "iamcu";
10353 cpu_sub_arch_name
= NULL
;
10354 cpu_arch_flags
= iamcu_flags
;
10355 cpu_arch_isa
= PROCESSOR_IAMCU
;
10356 cpu_arch_isa_flags
= iamcu_flags
;
10357 if (!cpu_arch_tune_set
)
10359 cpu_arch_tune
= cpu_arch_isa
;
10360 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
10364 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10368 as_fatal (_("unknown architecture"));
10370 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
10371 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10372 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
10373 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
10375 switch (OUTPUT_FLAVOR
)
10377 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10378 case bfd_target_aout_flavour
:
10379 return AOUT_TARGET_FORMAT
;
10381 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10382 # if defined (TE_PE) || defined (TE_PEP)
10383 case bfd_target_coff_flavour
:
10384 if (flag_code
== CODE_64BIT
)
10385 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
10388 # elif defined (TE_GO32)
10389 case bfd_target_coff_flavour
:
10390 return "coff-go32";
10392 case bfd_target_coff_flavour
:
10393 return "coff-i386";
10396 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10397 case bfd_target_elf_flavour
:
10399 const char *format
;
10401 switch (x86_elf_abi
)
10404 format
= ELF_TARGET_FORMAT
;
10407 use_rela_relocations
= 1;
10409 format
= ELF_TARGET_FORMAT64
;
10411 case X86_64_X32_ABI
:
10412 use_rela_relocations
= 1;
10414 disallow_64bit_reloc
= 1;
10415 format
= ELF_TARGET_FORMAT32
;
10418 if (cpu_arch_isa
== PROCESSOR_L1OM
)
10420 if (x86_elf_abi
!= X86_64_ABI
)
10421 as_fatal (_("Intel L1OM is 64bit only"));
10422 return ELF_TARGET_L1OM_FORMAT
;
10424 else if (cpu_arch_isa
== PROCESSOR_K1OM
)
10426 if (x86_elf_abi
!= X86_64_ABI
)
10427 as_fatal (_("Intel K1OM is 64bit only"));
10428 return ELF_TARGET_K1OM_FORMAT
;
10430 else if (cpu_arch_isa
== PROCESSOR_IAMCU
)
10432 if (x86_elf_abi
!= I386_ABI
)
10433 as_fatal (_("Intel MCU is 32bit only"));
10434 return ELF_TARGET_IAMCU_FORMAT
;
10440 #if defined (OBJ_MACH_O)
10441 case bfd_target_mach_o_flavour
:
10442 if (flag_code
== CODE_64BIT
)
10444 use_rela_relocations
= 1;
10446 return "mach-o-x86-64";
10449 return "mach-o-i386";
10457 #endif /* OBJ_MAYBE_ more than one */
10460 md_undefined_symbol (char *name
)
10462 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
10463 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
10464 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
10465 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
10469 if (symbol_find (name
))
10470 as_bad (_("GOT already in symbol table"));
10471 GOT_symbol
= symbol_new (name
, undefined_section
,
10472 (valueT
) 0, &zero_address_frag
);
10479 /* Round up a section size to the appropriate boundary. */
10482 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
10484 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10485 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
10487 /* For a.out, force the section size to be aligned. If we don't do
10488 this, BFD will align it for us, but it will not write out the
10489 final bytes of the section. This may be a bug in BFD, but it is
10490 easier to fix it here since that is how the other a.out targets
10494 align
= bfd_get_section_alignment (stdoutput
, segment
);
10495 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
10502 /* On the i386, PC-relative offsets are relative to the start of the
10503 next instruction. That is, the address of the offset, plus its
10504 size, since the offset is always the last part of the insn. */
10507 md_pcrel_from (fixS
*fixP
)
10509 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10515 s_bss (int ignore ATTRIBUTE_UNUSED
)
10519 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10521 obj_elf_section_change_hook ();
10523 temp
= get_absolute_expression ();
10524 subseg_set (bss_section
, (subsegT
) temp
);
10525 demand_empty_rest_of_line ();
10531 i386_validate_fix (fixS
*fixp
)
10533 if (fixp
->fx_subsy
)
10535 if (fixp
->fx_subsy
== GOT_symbol
)
10537 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
10541 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10542 if (fixp
->fx_tcbit2
)
10543 fixp
->fx_r_type
= (fixp
->fx_tcbit
10544 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10545 : BFD_RELOC_X86_64_GOTPCRELX
);
10548 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
10553 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
10555 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
10557 fixp
->fx_subsy
= 0;
10560 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10561 else if (!object_64bit
)
10563 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
10564 && fixp
->fx_tcbit2
)
10565 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
10571 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
10574 bfd_reloc_code_real_type code
;
10576 switch (fixp
->fx_r_type
)
10578 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10579 case BFD_RELOC_SIZE32
:
10580 case BFD_RELOC_SIZE64
:
10581 if (S_IS_DEFINED (fixp
->fx_addsy
)
10582 && !S_IS_EXTERNAL (fixp
->fx_addsy
))
10584 /* Resolve size relocation against local symbol to size of
10585 the symbol plus addend. */
10586 valueT value
= S_GET_SIZE (fixp
->fx_addsy
) + fixp
->fx_offset
;
10587 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
10588 && !fits_in_unsigned_long (value
))
10589 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10590 _("symbol size computation overflow"));
10591 fixp
->fx_addsy
= NULL
;
10592 fixp
->fx_subsy
= NULL
;
10593 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
10598 case BFD_RELOC_X86_64_PLT32
:
10599 case BFD_RELOC_X86_64_GOT32
:
10600 case BFD_RELOC_X86_64_GOTPCREL
:
10601 case BFD_RELOC_X86_64_GOTPCRELX
:
10602 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10603 case BFD_RELOC_386_PLT32
:
10604 case BFD_RELOC_386_GOT32
:
10605 case BFD_RELOC_386_GOT32X
:
10606 case BFD_RELOC_386_GOTOFF
:
10607 case BFD_RELOC_386_GOTPC
:
10608 case BFD_RELOC_386_TLS_GD
:
10609 case BFD_RELOC_386_TLS_LDM
:
10610 case BFD_RELOC_386_TLS_LDO_32
:
10611 case BFD_RELOC_386_TLS_IE_32
:
10612 case BFD_RELOC_386_TLS_IE
:
10613 case BFD_RELOC_386_TLS_GOTIE
:
10614 case BFD_RELOC_386_TLS_LE_32
:
10615 case BFD_RELOC_386_TLS_LE
:
10616 case BFD_RELOC_386_TLS_GOTDESC
:
10617 case BFD_RELOC_386_TLS_DESC_CALL
:
10618 case BFD_RELOC_X86_64_TLSGD
:
10619 case BFD_RELOC_X86_64_TLSLD
:
10620 case BFD_RELOC_X86_64_DTPOFF32
:
10621 case BFD_RELOC_X86_64_DTPOFF64
:
10622 case BFD_RELOC_X86_64_GOTTPOFF
:
10623 case BFD_RELOC_X86_64_TPOFF32
:
10624 case BFD_RELOC_X86_64_TPOFF64
:
10625 case BFD_RELOC_X86_64_GOTOFF64
:
10626 case BFD_RELOC_X86_64_GOTPC32
:
10627 case BFD_RELOC_X86_64_GOT64
:
10628 case BFD_RELOC_X86_64_GOTPCREL64
:
10629 case BFD_RELOC_X86_64_GOTPC64
:
10630 case BFD_RELOC_X86_64_GOTPLT64
:
10631 case BFD_RELOC_X86_64_PLTOFF64
:
10632 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10633 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10634 case BFD_RELOC_RVA
:
10635 case BFD_RELOC_VTABLE_ENTRY
:
10636 case BFD_RELOC_VTABLE_INHERIT
:
10638 case BFD_RELOC_32_SECREL
:
10640 code
= fixp
->fx_r_type
;
10642 case BFD_RELOC_X86_64_32S
:
10643 if (!fixp
->fx_pcrel
)
10645 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10646 code
= fixp
->fx_r_type
;
10650 if (fixp
->fx_pcrel
)
10652 switch (fixp
->fx_size
)
10655 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10656 _("can not do %d byte pc-relative relocation"),
10658 code
= BFD_RELOC_32_PCREL
;
10660 case 1: code
= BFD_RELOC_8_PCREL
; break;
10661 case 2: code
= BFD_RELOC_16_PCREL
; break;
10662 case 4: code
= BFD_RELOC_32_PCREL
; break;
10664 case 8: code
= BFD_RELOC_64_PCREL
; break;
10670 switch (fixp
->fx_size
)
10673 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10674 _("can not do %d byte relocation"),
10676 code
= BFD_RELOC_32
;
10678 case 1: code
= BFD_RELOC_8
; break;
10679 case 2: code
= BFD_RELOC_16
; break;
10680 case 4: code
= BFD_RELOC_32
; break;
10682 case 8: code
= BFD_RELOC_64
; break;
10689 if ((code
== BFD_RELOC_32
10690 || code
== BFD_RELOC_32_PCREL
10691 || code
== BFD_RELOC_X86_64_32S
)
10693 && fixp
->fx_addsy
== GOT_symbol
)
10696 code
= BFD_RELOC_386_GOTPC
;
10698 code
= BFD_RELOC_X86_64_GOTPC32
;
10700 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
10702 && fixp
->fx_addsy
== GOT_symbol
)
10704 code
= BFD_RELOC_X86_64_GOTPC64
;
10707 rel
= XNEW (arelent
);
10708 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
10709 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10711 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10713 if (!use_rela_relocations
)
10715 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10716 vtable entry to be used in the relocation's section offset. */
10717 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10718 rel
->address
= fixp
->fx_offset
;
10719 #if defined (OBJ_COFF) && defined (TE_PE)
10720 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
10721 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
10726 /* Use the rela in 64bit mode. */
10729 if (disallow_64bit_reloc
)
10732 case BFD_RELOC_X86_64_DTPOFF64
:
10733 case BFD_RELOC_X86_64_TPOFF64
:
10734 case BFD_RELOC_64_PCREL
:
10735 case BFD_RELOC_X86_64_GOTOFF64
:
10736 case BFD_RELOC_X86_64_GOT64
:
10737 case BFD_RELOC_X86_64_GOTPCREL64
:
10738 case BFD_RELOC_X86_64_GOTPC64
:
10739 case BFD_RELOC_X86_64_GOTPLT64
:
10740 case BFD_RELOC_X86_64_PLTOFF64
:
10741 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10742 _("cannot represent relocation type %s in x32 mode"),
10743 bfd_get_reloc_code_name (code
));
10749 if (!fixp
->fx_pcrel
)
10750 rel
->addend
= fixp
->fx_offset
;
10754 case BFD_RELOC_X86_64_PLT32
:
10755 case BFD_RELOC_X86_64_GOT32
:
10756 case BFD_RELOC_X86_64_GOTPCREL
:
10757 case BFD_RELOC_X86_64_GOTPCRELX
:
10758 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
10759 case BFD_RELOC_X86_64_TLSGD
:
10760 case BFD_RELOC_X86_64_TLSLD
:
10761 case BFD_RELOC_X86_64_GOTTPOFF
:
10762 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10763 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10764 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
10767 rel
->addend
= (section
->vma
10769 + fixp
->fx_addnumber
10770 + md_pcrel_from (fixp
));
10775 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10776 if (rel
->howto
== NULL
)
10778 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10779 _("cannot represent relocation type %s"),
10780 bfd_get_reloc_code_name (code
));
10781 /* Set howto to a garbage value so that we can keep going. */
10782 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
10783 gas_assert (rel
->howto
!= NULL
);
10789 #include "tc-i386-intel.c"
10792 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
10794 int saved_naked_reg
;
10795 char saved_register_dot
;
10797 saved_naked_reg
= allow_naked_reg
;
10798 allow_naked_reg
= 1;
10799 saved_register_dot
= register_chars
['.'];
10800 register_chars
['.'] = '.';
10801 allow_pseudo_reg
= 1;
10802 expression_and_evaluate (exp
);
10803 allow_pseudo_reg
= 0;
10804 register_chars
['.'] = saved_register_dot
;
10805 allow_naked_reg
= saved_naked_reg
;
10807 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10809 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10811 exp
->X_op
= O_constant
;
10812 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10813 .dw2_regnum
[flag_code
>> 1];
10816 exp
->X_op
= O_illegal
;
10821 tc_x86_frame_initial_instructions (void)
10823 static unsigned int sp_regno
[2];
10825 if (!sp_regno
[flag_code
>> 1])
10827 char *saved_input
= input_line_pointer
;
10828 char sp
[][4] = {"esp", "rsp"};
10831 input_line_pointer
= sp
[flag_code
>> 1];
10832 tc_x86_parse_to_dw2regnum (&exp
);
10833 gas_assert (exp
.X_op
== O_constant
);
10834 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10835 input_line_pointer
= saved_input
;
10838 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10839 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10843 x86_dwarf2_addr_size (void)
10845 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10846 if (x86_elf_abi
== X86_64_X32_ABI
)
10849 return bfd_arch_bits_per_address (stdoutput
) / 8;
10853 i386_elf_section_type (const char *str
, size_t len
)
10855 if (flag_code
== CODE_64BIT
10856 && len
== sizeof ("unwind") - 1
10857 && strncmp (str
, "unwind", 6) == 0)
10858 return SHT_X86_64_UNWIND
;
10865 i386_solaris_fix_up_eh_frame (segT sec
)
10867 if (flag_code
== CODE_64BIT
)
10868 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10874 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10878 exp
.X_op
= O_secrel
;
10879 exp
.X_add_symbol
= symbol
;
10880 exp
.X_add_number
= 0;
10881 emit_expr (&exp
, size
);
10885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10886 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10889 x86_64_section_letter (int letter
, const char **ptr_msg
)
10891 if (flag_code
== CODE_64BIT
)
10894 return SHF_X86_64_LARGE
;
10896 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10899 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
10904 x86_64_section_word (char *str
, size_t len
)
10906 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10907 return SHF_X86_64_LARGE
;
10913 handle_large_common (int small ATTRIBUTE_UNUSED
)
10915 if (flag_code
!= CODE_64BIT
)
10917 s_comm_internal (0, elf_common_parse
);
10918 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10922 static segT lbss_section
;
10923 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10924 asection
*saved_bss_section
= bss_section
;
10926 if (lbss_section
== NULL
)
10928 flagword applicable
;
10929 segT seg
= now_seg
;
10930 subsegT subseg
= now_subseg
;
10932 /* The .lbss section is for local .largecomm symbols. */
10933 lbss_section
= subseg_new (".lbss", 0);
10934 applicable
= bfd_applicable_section_flags (stdoutput
);
10935 bfd_set_section_flags (stdoutput
, lbss_section
,
10936 applicable
& SEC_ALLOC
);
10937 seg_info (lbss_section
)->bss
= 1;
10939 subseg_set (seg
, subseg
);
10942 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10943 bss_section
= lbss_section
;
10945 s_comm_internal (0, elf_common_parse
);
10947 elf_com_section_ptr
= saved_com_section_ptr
;
10948 bss_section
= saved_bss_section
;
10951 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */