1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 x86_64 support by Jan Hubicka (jh@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
55 static int fits_in_signed_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
57 static int fits_in_unsigned_word
PARAMS ((offsetT
));
58 static int fits_in_signed_word
PARAMS ((offsetT
));
59 static int fits_in_unsigned_long
PARAMS ((offsetT
));
60 static int fits_in_signed_long
PARAMS ((offsetT
));
61 static int smallest_imm_type
PARAMS ((offsetT
));
62 static offsetT offset_in_range
PARAMS ((offsetT
, int));
63 static int add_prefix
PARAMS ((unsigned int));
64 static void set_code_flag
PARAMS ((int));
65 static void set_16bit_gcc_code_flag
PARAMS ((int));
66 static void set_intel_syntax
PARAMS ((int));
67 static void set_cpu_arch
PARAMS ((int));
70 static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, int, bfd_reloc_code_real_type
));
75 #define DEFAULT_ARCH "i386"
77 static char *default_arch
= DEFAULT_ARCH
;
79 /* 'md_assemble ()' gathers together information and puts it into a
86 const reg_entry
*regs
;
91 /* TM holds the template for the insn were currently assembling. */
94 /* SUFFIX holds the instruction mnemonic suffix if given.
95 (e.g. 'l' for 'movl') */
98 /* OPERANDS gives the number of given operands. */
99 unsigned int operands
;
101 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
102 of given register, displacement, memory operands and immediate
104 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
106 /* TYPES [i] is the type (see above #defines) which tells us how to
107 use OP[i] for the corresponding operand. */
108 unsigned int types
[MAX_OPERANDS
];
110 /* Displacement expression, immediate expression, or register for each
112 union i386_op op
[MAX_OPERANDS
];
114 /* Flags for operands. */
115 unsigned int flags
[MAX_OPERANDS
];
116 #define Operand_PCrel 1
118 /* Relocation type for operand */
120 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
122 int disp_reloc
[MAX_OPERANDS
];
125 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
126 the base index byte below. */
127 const reg_entry
*base_reg
;
128 const reg_entry
*index_reg
;
129 unsigned int log2_scale_factor
;
131 /* SEG gives the seg_entries of this insn. They are zero unless
132 explicit segment overrides are given. */
133 const seg_entry
*seg
[2];
135 /* PREFIX holds all the given prefix opcodes (usually null).
136 PREFIXES is the number of prefix opcodes. */
137 unsigned int prefixes
;
138 unsigned char prefix
[MAX_PREFIXES
];
140 /* RM and SIB are the modrm byte and the sib byte where the
141 addressing modes of this insn are encoded. */
148 typedef struct _i386_insn i386_insn
;
150 /* List of chars besides those in app.c:symbol_chars that can start an
151 operand. Used to prevent the scrubber eating vital white-space. */
153 const char extra_symbol_chars
[] = "*%-(@";
155 const char extra_symbol_chars
[] = "*%-(";
158 /* This array holds the chars that always start a comment. If the
159 pre-processor is disabled, these aren't very useful. */
160 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
161 /* Putting '/' here makes it impossible to use the divide operator.
162 However, we need it for compatibility with SVR4 systems. */
163 const char comment_chars
[] = "#/";
164 #define PREFIX_SEPARATOR '\\'
166 const char comment_chars
[] = "#";
167 #define PREFIX_SEPARATOR '/'
170 /* This array holds the chars that only start a comment at the beginning of
171 a line. If the line seems to have the form '# 123 filename'
172 .line and .file directives will appear in the pre-processed output.
173 Note that input_file.c hand checks for '#' at the beginning of the
174 first line of the input file. This is because the compiler outputs
175 #NO_APP at the beginning of its output.
176 Also note that comments started like this one will always work if
177 '/' isn't otherwise defined. */
178 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
179 const char line_comment_chars
[] = "";
181 const char line_comment_chars
[] = "/";
184 const char line_separator_chars
[] = ";";
186 /* Chars that can be used to separate mant from exp in floating point
188 const char EXP_CHARS
[] = "eE";
190 /* Chars that mean this number is a floating point constant
193 const char FLT_CHARS
[] = "fFdDxX";
195 /* Tables for lexical analysis. */
196 static char mnemonic_chars
[256];
197 static char register_chars
[256];
198 static char operand_chars
[256];
199 static char identifier_chars
[256];
200 static char digit_chars
[256];
202 /* Lexical macros. */
203 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
204 #define is_operand_char(x) (operand_chars[(unsigned char) x])
205 #define is_register_char(x) (register_chars[(unsigned char) x])
206 #define is_space_char(x) ((x) == ' ')
207 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
208 #define is_digit_char(x) (digit_chars[(unsigned char) x])
210 /* All non-digit non-letter charcters that may occur in an operand. */
211 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
213 /* md_assemble() always leaves the strings it's passed unaltered. To
214 effect this we maintain a stack of saved characters that we've smashed
215 with '\0's (indicating end of strings for various sub-fields of the
216 assembler instruction). */
217 static char save_stack
[32];
218 static char *save_stack_p
;
219 #define END_STRING_AND_SAVE(s) \
220 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
221 #define RESTORE_END_STRING(s) \
222 do { *(s) = *--save_stack_p; } while (0)
224 /* The instruction we're assembling. */
227 /* Possible templates for current insn. */
228 static const templates
*current_templates
;
230 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
231 static expressionS disp_expressions
[2], im_expressions
[2];
233 /* Current operand we are working on. */
234 static int this_operand
;
236 /* We support four different modes. FLAG_CODE variable is used to distinguish
244 static enum flag_code flag_code
;
245 static int use_rela_relocations
= 0;
247 /* The names used to print error messages. */
248 static const char *flag_code_names
[] =
255 /* 1 for intel syntax,
257 static int intel_syntax
= 0;
259 /* 1 if register prefix % not required. */
260 static int allow_naked_reg
= 0;
262 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
263 leave, push, and pop instructions so that gcc has the same stack
264 frame as in 32 bit mode. */
265 static char stackop_size
= '\0';
267 /* Non-zero to quieten some warnings. */
268 static int quiet_warnings
= 0;
271 static const char *cpu_arch_name
= NULL
;
273 /* CPU feature flags. */
274 static unsigned int cpu_arch_flags
= CpuUnknownFlags
|CpuNo64
;
276 /* Interface to relax_segment.
277 There are 2 relax states for 386 jump insns: one for conditional &
278 one for unconditional jumps. This is because these two types of
279 jumps add different sizes to frags when we're figuring out what
280 sort of jump to choose to reach a given label. */
284 #define UNCOND_JUMP 2
288 #define SMALL16 (SMALL|CODE16)
290 #define BIG16 (BIG|CODE16)
294 #define INLINE __inline__
300 #define ENCODE_RELAX_STATE(type,size) \
301 ((relax_substateT) ((type<<2) | (size)))
302 #define SIZE_FROM_RELAX_STATE(s) \
303 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
305 /* This table is used by relax_frag to promote short jumps to long
306 ones where necessary. SMALL (short) jumps may be promoted to BIG
307 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
308 don't allow a short jump in a 32 bit code segment to be promoted to
309 a 16 bit offset jump because it's slower (requires data size
310 prefix), and doesn't work, unless the destination is in the bottom
311 64k of the code segment (The top 16 bits of eip are zeroed). */
313 const relax_typeS md_relax_table
[] =
316 1) most positive reach of this state,
317 2) most negative reach of this state,
318 3) how many bytes this mode will add to the size of the current frag
319 4) which index into the table to try if we can't fit into this one. */
325 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
326 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
327 /* dword conditionals adds 4 bytes to frag:
328 1 extra opcode byte, 3 extra displacement bytes. */
330 /* word conditionals add 2 bytes to frag:
331 1 extra opcode byte, 1 extra displacement byte. */
334 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
335 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
336 /* dword jmp adds 3 bytes to frag:
337 0 extra opcode bytes, 3 extra displacement bytes. */
339 /* word jmp adds 1 byte to frag:
340 0 extra opcode bytes, 1 extra displacement byte. */
345 static const arch_entry cpu_arch
[] = {
347 {"i186", Cpu086
|Cpu186
},
348 {"i286", Cpu086
|Cpu186
|Cpu286
},
349 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
350 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
351 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
352 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
353 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
354 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
355 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuK6
|CpuMMX
|Cpu3dnow
},
356 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuMMX
|Cpu3dnow
},
357 {"sledgehammer",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuK6
|CpuAthlon
|CpuSledgehammer
|CpuMMX
|Cpu3dnow
|CpuSSE
},
362 i386_align_code (fragP
, count
)
366 /* Various efficient no-op patterns for aligning code labels.
367 Note: Don't try to assemble the instructions in the comments.
368 0L and 0w are not legal. */
369 static const char f32_1
[] =
371 static const char f32_2
[] =
372 {0x89,0xf6}; /* movl %esi,%esi */
373 static const char f32_3
[] =
374 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
375 static const char f32_4
[] =
376 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
377 static const char f32_5
[] =
379 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
380 static const char f32_6
[] =
381 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
382 static const char f32_7
[] =
383 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
384 static const char f32_8
[] =
386 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
387 static const char f32_9
[] =
388 {0x89,0xf6, /* movl %esi,%esi */
389 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
390 static const char f32_10
[] =
391 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
392 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
393 static const char f32_11
[] =
394 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
395 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
396 static const char f32_12
[] =
397 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
398 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
399 static const char f32_13
[] =
400 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
401 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
402 static const char f32_14
[] =
403 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
404 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
405 static const char f32_15
[] =
406 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
407 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
408 static const char f16_3
[] =
409 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
410 static const char f16_4
[] =
411 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
412 static const char f16_5
[] =
414 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
415 static const char f16_6
[] =
416 {0x89,0xf6, /* mov %si,%si */
417 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
418 static const char f16_7
[] =
419 {0x8d,0x74,0x00, /* lea 0(%si),%si */
420 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
421 static const char f16_8
[] =
422 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
423 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
424 static const char *const f32_patt
[] = {
425 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
426 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
428 static const char *const f16_patt
[] = {
429 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
430 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
433 /* ??? We can't use these fillers for x86_64, since they often kills the
434 upper halves. Solve later. */
435 if (flag_code
== CODE_64BIT
)
438 if (count
> 0 && count
<= 15)
440 if (flag_code
== CODE_16BIT
)
442 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
443 f16_patt
[count
- 1], count
);
445 /* Adjust jump offset. */
446 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
449 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
450 f32_patt
[count
- 1], count
);
451 fragP
->fr_var
= count
;
455 static char *output_invalid
PARAMS ((int c
));
456 static int i386_operand
PARAMS ((char *operand_string
));
457 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
458 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
462 static void s_bss
PARAMS ((int));
465 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
467 static INLINE
unsigned int
468 mode_from_disp_size (t
)
471 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
| Disp32S
)) ? 2 : 0;
475 fits_in_signed_byte (num
)
478 return (num
>= -128) && (num
<= 127);
482 fits_in_unsigned_byte (num
)
485 return (num
& 0xff) == num
;
489 fits_in_unsigned_word (num
)
492 return (num
& 0xffff) == num
;
496 fits_in_signed_word (num
)
499 return (-32768 <= num
) && (num
<= 32767);
502 fits_in_signed_long (num
)
503 offsetT num ATTRIBUTE_UNUSED
;
508 return (!(((offsetT
) -1 << 31) & num
)
509 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
511 } /* fits_in_signed_long() */
513 fits_in_unsigned_long (num
)
514 offsetT num ATTRIBUTE_UNUSED
;
519 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
521 } /* fits_in_unsigned_long() */
524 smallest_imm_type (num
)
527 if (cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
| CpuNo64
)
528 && !(cpu_arch_flags
& (CpuUnknown
)))
530 /* This code is disabled on the 486 because all the Imm1 forms
531 in the opcode table are slower on the i486. They're the
532 versions with the implicitly specified single-position
533 displacement, which has another syntax if you really want to
536 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
| Imm64
;
538 return (fits_in_signed_byte (num
)
539 ? (Imm8S
| Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
540 : fits_in_unsigned_byte (num
)
541 ? (Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
)
542 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
543 ? (Imm16
| Imm32
| Imm32S
| Imm64
)
544 : fits_in_signed_long (num
)
545 ? (Imm32
| Imm32S
| Imm64
)
546 : fits_in_unsigned_long (num
)
552 offset_in_range (val
, size
)
560 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
561 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
562 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
564 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
569 /* If BFD64, sign extend val. */
570 if (!use_rela_relocations
)
571 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
572 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
574 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
576 char buf1
[40], buf2
[40];
578 sprint_value (buf1
, val
);
579 sprint_value (buf2
, val
& mask
);
580 as_warn (_("%s shortened to %s"), buf1
, buf2
);
585 /* Returns 0 if attempting to add a prefix where one from the same
586 class already exists, 1 if non rep/repne added, 2 if rep/repne
595 if (prefix
>= 0x40 && prefix
< 0x50 && flag_code
== CODE_64BIT
)
603 case CS_PREFIX_OPCODE
:
604 case DS_PREFIX_OPCODE
:
605 case ES_PREFIX_OPCODE
:
606 case FS_PREFIX_OPCODE
:
607 case GS_PREFIX_OPCODE
:
608 case SS_PREFIX_OPCODE
:
612 case REPNE_PREFIX_OPCODE
:
613 case REPE_PREFIX_OPCODE
:
616 case LOCK_PREFIX_OPCODE
:
624 case ADDR_PREFIX_OPCODE
:
628 case DATA_PREFIX_OPCODE
:
635 as_bad (_("same type of prefix used twice"));
640 i
.prefix
[q
] = prefix
;
645 set_code_flag (value
)
649 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
650 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
651 if (value
== CODE_64BIT
&& !(cpu_arch_flags
& CpuSledgehammer
))
653 as_bad (_("64bit mode not supported on this CPU."));
655 if (value
== CODE_32BIT
&& !(cpu_arch_flags
& Cpu386
))
657 as_bad (_("32bit mode not supported on this CPU."));
663 set_16bit_gcc_code_flag (new_code_flag
)
666 flag_code
= new_code_flag
;
667 cpu_arch_flags
&= ~(Cpu64
| CpuNo64
);
668 cpu_arch_flags
|= (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
673 set_intel_syntax (syntax_flag
)
676 /* Find out if register prefixing is specified. */
677 int ask_naked_reg
= 0;
680 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
682 char *string
= input_line_pointer
;
683 int e
= get_symbol_end ();
685 if (strcmp (string
, "prefix") == 0)
687 else if (strcmp (string
, "noprefix") == 0)
690 as_bad (_("bad argument to syntax directive."));
691 *input_line_pointer
= e
;
693 demand_empty_rest_of_line ();
695 intel_syntax
= syntax_flag
;
697 if (ask_naked_reg
== 0)
700 allow_naked_reg
= (intel_syntax
701 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
703 /* Conservative default. */
708 allow_naked_reg
= (ask_naked_reg
< 0);
713 int dummy ATTRIBUTE_UNUSED
;
717 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
719 char *string
= input_line_pointer
;
720 int e
= get_symbol_end ();
723 for (i
= 0; cpu_arch
[i
].name
; i
++)
725 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
727 cpu_arch_name
= cpu_arch
[i
].name
;
728 cpu_arch_flags
= cpu_arch
[i
].flags
| (flag_code
== CODE_64BIT
? Cpu64
: CpuNo64
);
732 if (!cpu_arch
[i
].name
)
733 as_bad (_("no such architecture: `%s'"), string
);
735 *input_line_pointer
= e
;
738 as_bad (_("missing cpu architecture"));
740 demand_empty_rest_of_line ();
743 const pseudo_typeS md_pseudo_table
[] =
745 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
746 {"align", s_align_bytes
, 0},
748 {"align", s_align_ptwo
, 0},
750 {"arch", set_cpu_arch
, 0},
754 {"ffloat", float_cons
, 'f'},
755 {"dfloat", float_cons
, 'd'},
756 {"tfloat", float_cons
, 'x'},
758 {"noopt", s_ignore
, 0},
759 {"optim", s_ignore
, 0},
760 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
761 {"code16", set_code_flag
, CODE_16BIT
},
762 {"code32", set_code_flag
, CODE_32BIT
},
763 {"code64", set_code_flag
, CODE_64BIT
},
764 {"intel_syntax", set_intel_syntax
, 1},
765 {"att_syntax", set_intel_syntax
, 0},
766 {"file", dwarf2_directive_file
, 0},
767 {"loc", dwarf2_directive_loc
, 0},
771 /* For interface with expression (). */
772 extern char *input_line_pointer
;
774 /* Hash table for instruction mnemonic lookup. */
775 static struct hash_control
*op_hash
;
777 /* Hash table for register lookup. */
778 static struct hash_control
*reg_hash
;
783 const char *hash_err
;
785 /* Initialize op_hash hash table. */
786 op_hash
= hash_new ();
789 register const template *optab
;
790 register templates
*core_optab
;
792 /* Setup for loop. */
794 core_optab
= (templates
*) xmalloc (sizeof (templates
));
795 core_optab
->start
= optab
;
800 if (optab
->name
== NULL
801 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
803 /* different name --> ship out current template list;
804 add to hash table; & begin anew. */
805 core_optab
->end
= optab
;
806 hash_err
= hash_insert (op_hash
,
811 as_fatal (_("Internal Error: Can't hash %s: %s"),
815 if (optab
->name
== NULL
)
817 core_optab
= (templates
*) xmalloc (sizeof (templates
));
818 core_optab
->start
= optab
;
823 /* Initialize reg_hash hash table. */
824 reg_hash
= hash_new ();
826 register const reg_entry
*regtab
;
828 for (regtab
= i386_regtab
;
829 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
832 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
834 as_fatal (_("Internal Error: Can't hash %s: %s"),
840 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
845 for (c
= 0; c
< 256; c
++)
850 mnemonic_chars
[c
] = c
;
851 register_chars
[c
] = c
;
852 operand_chars
[c
] = c
;
854 else if (islower (c
))
856 mnemonic_chars
[c
] = c
;
857 register_chars
[c
] = c
;
858 operand_chars
[c
] = c
;
860 else if (isupper (c
))
862 mnemonic_chars
[c
] = tolower (c
);
863 register_chars
[c
] = mnemonic_chars
[c
];
864 operand_chars
[c
] = c
;
867 if (isalpha (c
) || isdigit (c
))
868 identifier_chars
[c
] = c
;
871 identifier_chars
[c
] = c
;
872 operand_chars
[c
] = c
;
877 identifier_chars
['@'] = '@';
879 digit_chars
['-'] = '-';
880 identifier_chars
['_'] = '_';
881 identifier_chars
['.'] = '.';
883 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
884 operand_chars
[(unsigned char) *p
] = *p
;
887 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
888 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
890 record_alignment (text_section
, 2);
891 record_alignment (data_section
, 2);
892 record_alignment (bss_section
, 2);
898 i386_print_statistics (file
)
901 hash_print_statistics (file
, "i386 opcode", op_hash
);
902 hash_print_statistics (file
, "i386 register", reg_hash
);
907 /* Debugging routines for md_assemble. */
908 static void pi
PARAMS ((char *, i386_insn
*));
909 static void pte
PARAMS ((template *));
910 static void pt
PARAMS ((unsigned int));
911 static void pe
PARAMS ((expressionS
*));
912 static void ps
PARAMS ((symbolS
*));
919 register template *p
;
922 fprintf (stdout
, "%s: template ", line
);
924 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
925 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
926 fprintf (stdout
, " base %x index %x scale %x\n",
927 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
928 for (i
= 0; i
< x
->operands
; i
++)
930 fprintf (stdout
, " #%d: ", i
+ 1);
932 fprintf (stdout
, "\n");
934 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
935 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
936 if (x
->types
[i
] & Imm
)
938 if (x
->types
[i
] & Disp
)
948 fprintf (stdout
, " %d operands ", t
->operands
);
949 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
950 if (t
->extension_opcode
!= None
)
951 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
952 if (t
->opcode_modifier
& D
)
953 fprintf (stdout
, "D");
954 if (t
->opcode_modifier
& W
)
955 fprintf (stdout
, "W");
956 fprintf (stdout
, "\n");
957 for (i
= 0; i
< t
->operands
; i
++)
959 fprintf (stdout
, " #%d type ", i
+ 1);
960 pt (t
->operand_types
[i
]);
961 fprintf (stdout
, "\n");
969 fprintf (stdout
, " operation %d\n", e
->X_op
);
970 fprintf (stdout
, " add_number %ld (%lx)\n",
971 (long) e
->X_add_number
, (long) e
->X_add_number
);
974 fprintf (stdout
, " add_symbol ");
975 ps (e
->X_add_symbol
);
976 fprintf (stdout
, "\n");
980 fprintf (stdout
, " op_symbol ");
982 fprintf (stdout
, "\n");
990 fprintf (stdout
, "%s type %s%s",
992 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
993 segment_name (S_GET_SEGMENT (s
)));
1012 { BaseIndex
, "BaseIndex" },
1016 { InOutPortReg
, "InOutPortReg" },
1017 { ShiftCount
, "ShiftCount" },
1018 { Control
, "control reg" },
1019 { Test
, "test reg" },
1020 { Debug
, "debug reg" },
1021 { FloatReg
, "FReg" },
1022 { FloatAcc
, "FAcc" },
1026 { JumpAbsolute
, "Jump Absolute" },
1037 register struct type_name
*ty
;
1041 fprintf (stdout
, _("Unknown"));
1045 for (ty
= type_names
; ty
->mask
; ty
++)
1047 fprintf (stdout
, "%s, ", ty
->tname
);
1052 #endif /* DEBUG386 */
1055 tc_i386_force_relocation (fixp
)
1058 #ifdef BFD_ASSEMBLER
1059 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1060 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1065 return fixp
->fx_r_type
== 7;
1069 #ifdef BFD_ASSEMBLER
1071 static bfd_reloc_code_real_type
1072 reloc (size
, pcrel
, sign
, other
)
1076 bfd_reloc_code_real_type other
;
1078 if (other
!= NO_RELOC
)
1084 as_bad(_("There are no unsigned pc-relative relocations"));
1087 case 1: return BFD_RELOC_8_PCREL
;
1088 case 2: return BFD_RELOC_16_PCREL
;
1089 case 4: return BFD_RELOC_32_PCREL
;
1091 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1098 case 4: return BFD_RELOC_X86_64_32S
;
1103 case 1: return BFD_RELOC_8
;
1104 case 2: return BFD_RELOC_16
;
1105 case 4: return BFD_RELOC_32
;
1106 case 8: return BFD_RELOC_64
;
1108 as_bad (_("can not do %s %d byte relocation"),
1109 sign
? "signed" : "unsigned", size
);
1113 return BFD_RELOC_NONE
;
1116 /* Here we decide which fixups can be adjusted to make them relative to
1117 the beginning of the section instead of the symbol. Basically we need
1118 to make sure that the dynamic relocations are done correctly, so in
1119 some cases we force the original symbol to be used. */
1122 tc_i386_fix_adjustable (fixP
)
1125 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1126 /* Prevent all adjustments to global symbols, or else dynamic
1127 linking will not work correctly. */
1128 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1129 || S_IS_WEAK (fixP
->fx_addsy
))
1132 /* adjust_reloc_syms doesn't know about the GOT. */
1133 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1134 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1135 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1136 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
1137 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
1138 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1139 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1144 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1145 #define BFD_RELOC_16 0
1146 #define BFD_RELOC_32 0
1147 #define BFD_RELOC_16_PCREL 0
1148 #define BFD_RELOC_32_PCREL 0
1149 #define BFD_RELOC_386_PLT32 0
1150 #define BFD_RELOC_386_GOT32 0
1151 #define BFD_RELOC_386_GOTOFF 0
1152 #define BFD_RELOC_X86_64_PLT32 0
1153 #define BFD_RELOC_X86_64_GOT32 0
1154 #define BFD_RELOC_X86_64_GOTPCREL 0
1157 static int intel_float_operand
PARAMS ((char *mnemonic
));
1160 intel_float_operand (mnemonic
)
1163 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1166 if (mnemonic
[0] == 'f')
1172 /* This is the guts of the machine-dependent assembler. LINE points to a
1173 machine dependent instruction. This function is supposed to emit
1174 the frags/bytes it assembles to. */
1180 /* Points to template once we've found it. */
1183 /* Count the size of the instruction generated. */
1188 char mnemonic
[MAX_MNEM_SIZE
];
1190 /* Initialize globals. */
1191 memset (&i
, '\0', sizeof (i
));
1192 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1193 i
.disp_reloc
[j
] = NO_RELOC
;
1194 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1195 memset (im_expressions
, '\0', sizeof (im_expressions
));
1196 save_stack_p
= save_stack
;
1198 /* First parse an instruction mnemonic & call i386_operand for the operands.
1199 We assume that the scrubber has arranged it so that line[0] is the valid
1200 start of a (possibly prefixed) mnemonic. */
1203 char *token_start
= l
;
1206 /* Non-zero if we found a prefix only acceptable with string insns. */
1207 const char *expecting_string_instruction
= NULL
;
1212 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1215 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1217 as_bad (_("no such instruction: `%s'"), token_start
);
1222 if (!is_space_char (*l
)
1223 && *l
!= END_OF_INSN
1224 && *l
!= PREFIX_SEPARATOR
)
1226 as_bad (_("invalid character %s in mnemonic"),
1227 output_invalid (*l
));
1230 if (token_start
== l
)
1232 if (*l
== PREFIX_SEPARATOR
)
1233 as_bad (_("expecting prefix; got nothing"));
1235 as_bad (_("expecting mnemonic; got nothing"));
1239 /* Look up instruction (or prefix) via hash table. */
1240 current_templates
= hash_find (op_hash
, mnemonic
);
1242 if (*l
!= END_OF_INSN
1243 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1244 && current_templates
1245 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1247 /* If we are in 16-bit mode, do not allow addr16 or data16.
1248 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1249 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1250 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1251 ^ (flag_code
== CODE_16BIT
)))
1253 as_bad (_("redundant %s prefix"),
1254 current_templates
->start
->name
);
1257 /* Add prefix, checking for repeated prefixes. */
1258 switch (add_prefix (current_templates
->start
->base_opcode
))
1263 expecting_string_instruction
= current_templates
->start
->name
;
1266 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1273 if (!current_templates
)
1275 /* See if we can get a match by trimming off a suffix. */
1278 case WORD_MNEM_SUFFIX
:
1279 case BYTE_MNEM_SUFFIX
:
1280 case QWORD_MNEM_SUFFIX
:
1281 i
.suffix
= mnem_p
[-1];
1283 current_templates
= hash_find (op_hash
, mnemonic
);
1285 case SHORT_MNEM_SUFFIX
:
1286 case LONG_MNEM_SUFFIX
:
1289 i
.suffix
= mnem_p
[-1];
1291 current_templates
= hash_find (op_hash
, mnemonic
);
1299 if (intel_float_operand (mnemonic
))
1300 i
.suffix
= SHORT_MNEM_SUFFIX
;
1302 i
.suffix
= LONG_MNEM_SUFFIX
;
1304 current_templates
= hash_find (op_hash
, mnemonic
);
1308 if (!current_templates
)
1310 as_bad (_("no such instruction: `%s'"), token_start
);
1315 /* Check if instruction is supported on specified architecture. */
1316 if (cpu_arch_flags
!= 0)
1318 if ((current_templates
->start
->cpu_flags
& ~(Cpu64
| CpuNo64
))
1319 & ~(cpu_arch_flags
& ~(Cpu64
| CpuNo64
)))
1321 as_warn (_("`%s' is not supported on `%s'"),
1322 current_templates
->start
->name
, cpu_arch_name
);
1324 else if ((Cpu386
& ~cpu_arch_flags
) && (flag_code
!= CODE_16BIT
))
1326 as_warn (_("use .code16 to ensure correct addressing mode"));
1330 /* Check for rep/repne without a string instruction. */
1331 if (expecting_string_instruction
1332 && !(current_templates
->start
->opcode_modifier
& IsString
))
1334 as_bad (_("expecting string instruction after `%s'"),
1335 expecting_string_instruction
);
1339 /* There may be operands to parse. */
1340 if (*l
!= END_OF_INSN
)
1342 /* 1 if operand is pending after ','. */
1343 unsigned int expecting_operand
= 0;
1345 /* Non-zero if operand parens not balanced. */
1346 unsigned int paren_not_balanced
;
1350 /* Skip optional white space before operand. */
1351 if (is_space_char (*l
))
1353 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1355 as_bad (_("invalid character %s before operand %d"),
1356 output_invalid (*l
),
1360 token_start
= l
; /* after white space */
1361 paren_not_balanced
= 0;
1362 while (paren_not_balanced
|| *l
!= ',')
1364 if (*l
== END_OF_INSN
)
1366 if (paren_not_balanced
)
1369 as_bad (_("unbalanced parenthesis in operand %d."),
1372 as_bad (_("unbalanced brackets in operand %d."),
1377 break; /* we are done */
1379 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1381 as_bad (_("invalid character %s in operand %d"),
1382 output_invalid (*l
),
1389 ++paren_not_balanced
;
1391 --paren_not_balanced
;
1396 ++paren_not_balanced
;
1398 --paren_not_balanced
;
1402 if (l
!= token_start
)
1403 { /* Yes, we've read in another operand. */
1404 unsigned int operand_ok
;
1405 this_operand
= i
.operands
++;
1406 if (i
.operands
> MAX_OPERANDS
)
1408 as_bad (_("spurious operands; (%d operands/instruction max)"),
1412 /* Now parse operand adding info to 'i' as we go along. */
1413 END_STRING_AND_SAVE (l
);
1417 i386_intel_operand (token_start
,
1418 intel_float_operand (mnemonic
));
1420 operand_ok
= i386_operand (token_start
);
1422 RESTORE_END_STRING (l
);
1428 if (expecting_operand
)
1430 expecting_operand_after_comma
:
1431 as_bad (_("expecting operand after ','; got nothing"));
1436 as_bad (_("expecting operand before ','; got nothing"));
1441 /* Now *l must be either ',' or END_OF_INSN. */
1444 if (*++l
== END_OF_INSN
)
1446 /* Just skip it, if it's \n complain. */
1447 goto expecting_operand_after_comma
;
1449 expecting_operand
= 1;
1452 while (*l
!= END_OF_INSN
);
1456 /* Now we've parsed the mnemonic into a set of templates, and have the
1459 Next, we find a template that matches the given insn,
1460 making sure the overlap of the given operands types is consistent
1461 with the template operand types. */
1463 #define MATCH(overlap, given, template) \
1464 ((overlap & ~JumpAbsolute) \
1465 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1467 /* If given types r0 and r1 are registers they must be of the same type
1468 unless the expected operand type register overlap is null.
1469 Note that Acc in a template matches every size of reg. */
1470 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1471 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1472 ((g0) & Reg) == ((g1) & Reg) || \
1473 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1476 register unsigned int overlap0
, overlap1
;
1477 unsigned int overlap2
;
1478 unsigned int found_reverse_match
;
1481 /* All intel opcodes have reversed operands except for "bound" and
1482 "enter". We also don't reverse intersegment "jmp" and "call"
1483 instructions with 2 immediate operands so that the immediate segment
1484 precedes the offset, as it does when in AT&T mode. "enter" and the
1485 intersegment "jmp" and "call" instructions are the only ones that
1486 have two immediate operands. */
1487 if (intel_syntax
&& i
.operands
> 1
1488 && (strcmp (mnemonic
, "bound") != 0)
1489 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1491 union i386_op temp_op
;
1492 unsigned int temp_type
;
1493 #ifdef BFD_ASSEMBLER
1494 enum bfd_reloc_code_real temp_reloc
;
1501 if (i
.operands
== 2)
1506 else if (i
.operands
== 3)
1511 temp_type
= i
.types
[xchg2
];
1512 i
.types
[xchg2
] = i
.types
[xchg1
];
1513 i
.types
[xchg1
] = temp_type
;
1514 temp_op
= i
.op
[xchg2
];
1515 i
.op
[xchg2
] = i
.op
[xchg1
];
1516 i
.op
[xchg1
] = temp_op
;
1517 temp_reloc
= i
.disp_reloc
[xchg2
];
1518 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1519 i
.disp_reloc
[xchg1
] = temp_reloc
;
1521 if (i
.mem_operands
== 2)
1523 const seg_entry
*temp_seg
;
1524 temp_seg
= i
.seg
[0];
1525 i
.seg
[0] = i
.seg
[1];
1526 i
.seg
[1] = temp_seg
;
1532 /* Try to ensure constant immediates are represented in the smallest
1534 char guess_suffix
= 0;
1538 guess_suffix
= i
.suffix
;
1539 else if (i
.reg_operands
)
1541 /* Figure out a suffix from the last register operand specified.
1542 We can't do this properly yet, ie. excluding InOutPortReg,
1543 but the following works for instructions with immediates.
1544 In any case, we can't set i.suffix yet. */
1545 for (op
= i
.operands
; --op
>= 0;)
1546 if (i
.types
[op
] & Reg
)
1548 if (i
.types
[op
] & Reg8
)
1549 guess_suffix
= BYTE_MNEM_SUFFIX
;
1550 else if (i
.types
[op
] & Reg16
)
1551 guess_suffix
= WORD_MNEM_SUFFIX
;
1552 else if (i
.types
[op
] & Reg32
)
1553 guess_suffix
= LONG_MNEM_SUFFIX
;
1554 else if (i
.types
[op
] & Reg64
)
1555 guess_suffix
= QWORD_MNEM_SUFFIX
;
1559 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
1560 guess_suffix
= WORD_MNEM_SUFFIX
;
1562 for (op
= i
.operands
; --op
>= 0;)
1563 if (i
.types
[op
] & Imm
)
1565 switch (i
.op
[op
].imms
->X_op
)
1568 /* If a suffix is given, this operand may be shortened. */
1569 switch (guess_suffix
)
1571 case LONG_MNEM_SUFFIX
:
1572 i
.types
[op
] |= Imm32
| Imm64
;
1574 case WORD_MNEM_SUFFIX
:
1575 i
.types
[op
] |= Imm16
| Imm32S
| Imm32
| Imm64
;
1577 case BYTE_MNEM_SUFFIX
:
1578 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
| Imm32S
| Imm32
| Imm64
;
1582 /* If this operand is at most 16 bits, convert it to a
1583 signed 16 bit number before trying to see whether it will
1584 fit in an even smaller size. This allows a 16-bit operand
1585 such as $0xffe0 to be recognised as within Imm8S range. */
1586 if ((i
.types
[op
] & Imm16
)
1587 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1589 i
.op
[op
].imms
->X_add_number
=
1590 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1592 if ((i
.types
[op
] & Imm32
)
1593 && (i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1)) == 0)
1595 i
.op
[op
].imms
->X_add_number
=
1596 (i
.op
[op
].imms
->X_add_number
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1598 i
.types
[op
] |= smallest_imm_type (i
.op
[op
].imms
->X_add_number
);
1599 /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
1600 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
1601 i
.types
[op
] &= ~Imm32
;
1606 /* Symbols and expressions. */
1608 /* Convert symbolic operand to proper sizes for matching. */
1609 switch (guess_suffix
)
1611 case QWORD_MNEM_SUFFIX
:
1612 i
.types
[op
] = Imm64
| Imm32S
;
1614 case LONG_MNEM_SUFFIX
:
1615 i
.types
[op
] = Imm32
| Imm64
;
1617 case WORD_MNEM_SUFFIX
:
1618 i
.types
[op
] = Imm16
| Imm32
| Imm64
;
1621 case BYTE_MNEM_SUFFIX
:
1622 i
.types
[op
] = Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
;
1631 if (i
.disp_operands
)
1633 /* Try to use the smallest displacement type too. */
1636 for (op
= i
.operands
; --op
>= 0;)
1637 if ((i
.types
[op
] & Disp
)
1638 && i
.op
[op
].imms
->X_op
== O_constant
)
1640 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1642 if (i
.types
[op
] & Disp16
)
1644 /* We know this operand is at most 16 bits, so
1645 convert to a signed 16 bit number before trying
1646 to see whether it will fit in an even smaller
1649 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1651 else if (i
.types
[op
] & Disp32
)
1653 /* We know this operand is at most 32 bits, so convert to a
1654 signed 32 bit number before trying to see whether it will
1655 fit in an even smaller size. */
1656 disp
&= (((offsetT
) 2 << 31) - 1);
1657 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
1659 if (flag_code
== CODE_64BIT
)
1661 if (fits_in_signed_long (disp
))
1662 i
.types
[op
] |= Disp32S
;
1663 if (fits_in_unsigned_long (disp
))
1664 i
.types
[op
] |= Disp32
;
1666 if ((i
.types
[op
] & (Disp32
| Disp32S
| Disp16
))
1667 && fits_in_signed_byte (disp
))
1668 i
.types
[op
] |= Disp8
;
1675 found_reverse_match
= 0;
1676 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1678 : (i
.suffix
== WORD_MNEM_SUFFIX
1680 : (i
.suffix
== SHORT_MNEM_SUFFIX
1682 : (i
.suffix
== LONG_MNEM_SUFFIX
1684 : (i
.suffix
== QWORD_MNEM_SUFFIX
1686 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0))))));
1688 for (t
= current_templates
->start
;
1689 t
< current_templates
->end
;
1692 /* Must have right number of operands. */
1693 if (i
.operands
!= t
->operands
)
1696 /* Check the suffix, except for some instructions in intel mode. */
1697 if ((t
->opcode_modifier
& suffix_check
)
1699 && (t
->opcode_modifier
& IgnoreSize
))
1701 && t
->base_opcode
== 0xd9
1702 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1703 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1706 else if (!t
->operands
)
1707 /* 0 operands always matches. */
1710 overlap0
= i
.types
[0] & t
->operand_types
[0];
1711 switch (t
->operands
)
1714 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1719 overlap1
= i
.types
[1] & t
->operand_types
[1];
1720 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1721 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1722 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1723 t
->operand_types
[0],
1724 overlap1
, i
.types
[1],
1725 t
->operand_types
[1]))
1727 /* Check if other direction is valid ... */
1728 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1731 /* Try reversing direction of operands. */
1732 overlap0
= i
.types
[0] & t
->operand_types
[1];
1733 overlap1
= i
.types
[1] & t
->operand_types
[0];
1734 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1735 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1736 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1737 t
->operand_types
[1],
1738 overlap1
, i
.types
[1],
1739 t
->operand_types
[0]))
1741 /* Does not match either direction. */
1744 /* found_reverse_match holds which of D or FloatDR
1746 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1748 /* Found a forward 2 operand match here. */
1749 else if (t
->operands
== 3)
1751 /* Here we make use of the fact that there are no
1752 reverse match 3 operand instructions, and all 3
1753 operand instructions only need to be checked for
1754 register consistency between operands 2 and 3. */
1755 overlap2
= i
.types
[2] & t
->operand_types
[2];
1756 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1757 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1758 t
->operand_types
[1],
1759 overlap2
, i
.types
[2],
1760 t
->operand_types
[2]))
1764 /* Found either forward/reverse 2 or 3 operand match here:
1765 slip through to break. */
1767 if (t
->cpu_flags
& ~cpu_arch_flags
)
1769 found_reverse_match
= 0;
1772 /* We've found a match; break out of loop. */
1775 if (t
== current_templates
->end
)
1777 /* We found no match. */
1778 as_bad (_("suffix or operands invalid for `%s'"),
1779 current_templates
->start
->name
);
1783 if (!quiet_warnings
)
1786 && ((i
.types
[0] & JumpAbsolute
)
1787 != (t
->operand_types
[0] & JumpAbsolute
)))
1789 as_warn (_("indirect %s without `*'"), t
->name
);
1792 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1793 == (IsPrefix
|IgnoreSize
))
1795 /* Warn them that a data or address size prefix doesn't
1796 affect assembly of the next line of code. */
1797 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1801 /* Copy the template we found. */
1803 if (found_reverse_match
)
1805 /* If we found a reverse match we must alter the opcode
1806 direction bit. found_reverse_match holds bits to change
1807 (different for int & float insns). */
1809 i
.tm
.base_opcode
^= found_reverse_match
;
1811 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1812 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1815 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1818 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1819 i
.tm
.base_opcode
^= FloatR
;
1821 if (i
.tm
.opcode_modifier
& FWait
)
1822 if (! add_prefix (FWAIT_OPCODE
))
1825 /* Check string instruction segment overrides. */
1826 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1828 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1829 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1831 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1833 as_bad (_("`%s' operand %d must use `%%es' segment"),
1838 /* There's only ever one segment override allowed per instruction.
1839 This instruction possibly has a legal segment override on the
1840 second operand, so copy the segment to where non-string
1841 instructions store it, allowing common code. */
1842 i
.seg
[0] = i
.seg
[1];
1844 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1846 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1848 as_bad (_("`%s' operand %d must use `%%es' segment"),
1856 if (i
.reg_operands
&& flag_code
< CODE_64BIT
)
1859 for (op
= i
.operands
; --op
>= 0; )
1860 if ((i
.types
[op
] & Reg
)
1861 && (i
.op
[op
].regs
->reg_flags
& (RegRex64
|RegRex
)))
1862 as_bad (_("Extended register `%%%s' available only in 64bit mode."),
1863 i
.op
[op
].regs
->reg_name
);
1866 /* If matched instruction specifies an explicit instruction mnemonic
1868 if (i
.tm
.opcode_modifier
& (Size16
| Size32
| Size64
))
1870 if (i
.tm
.opcode_modifier
& Size16
)
1871 i
.suffix
= WORD_MNEM_SUFFIX
;
1872 else if (i
.tm
.opcode_modifier
& Size64
)
1873 i
.suffix
= QWORD_MNEM_SUFFIX
;
1875 i
.suffix
= LONG_MNEM_SUFFIX
;
1877 else if (i
.reg_operands
)
1879 /* If there's no instruction mnemonic suffix we try to invent one
1880 based on register operands. */
1883 /* We take i.suffix from the last register operand specified,
1884 Destination register type is more significant than source
1887 for (op
= i
.operands
; --op
>= 0;)
1888 if ((i
.types
[op
] & Reg
)
1889 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1891 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1892 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1893 (i
.types
[op
] & Reg64
) ? QWORD_MNEM_SUFFIX
:
1898 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1901 for (op
= i
.operands
; --op
>= 0;)
1903 /* If this is an eight bit register, it's OK. If it's
1904 the 16 or 32 bit version of an eight bit register,
1905 we will just use the low portion, and that's OK too. */
1906 if (i
.types
[op
] & Reg8
)
1909 /* movzx and movsx should not generate this warning. */
1911 && (i
.tm
.base_opcode
== 0xfb7
1912 || i
.tm
.base_opcode
== 0xfb6
1913 || i
.tm
.base_opcode
== 0x63
1914 || i
.tm
.base_opcode
== 0xfbe
1915 || i
.tm
.base_opcode
== 0xfbf))
1918 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1920 /* Check that the template allows eight bit regs
1921 This kills insns such as `orb $1,%edx', which
1922 maybe should be allowed. */
1923 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1927 /* Prohibit these changes in the 64bit mode, since
1928 the lowering is more complicated. */
1929 if (flag_code
== CODE_64BIT
1930 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1931 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1932 i
.op
[op
].regs
->reg_name
,
1934 #if REGISTER_WARNINGS
1936 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1937 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1938 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1939 i
.op
[op
].regs
->reg_name
,
1944 /* Any other register is bad. */
1945 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1947 | Control
| Debug
| Test
1948 | FloatReg
| FloatAcc
))
1950 as_bad (_("`%%%s' not allowed with `%s%c'"),
1951 i
.op
[op
].regs
->reg_name
,
1958 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1962 for (op
= i
.operands
; --op
>= 0;)
1963 /* Reject eight bit registers, except where the template
1964 requires them. (eg. movzb) */
1965 if ((i
.types
[op
] & Reg8
) != 0
1966 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1968 as_bad (_("`%%%s' not allowed with `%s%c'"),
1969 i
.op
[op
].regs
->reg_name
,
1974 /* Warn if the e prefix on a general reg is missing. */
1975 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
1976 && (i
.types
[op
] & Reg16
) != 0
1977 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1979 /* Prohibit these changes in the 64bit mode, since
1980 the lowering is more complicated. */
1981 if (flag_code
== CODE_64BIT
)
1982 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1983 i
.op
[op
].regs
->reg_name
,
1985 #if REGISTER_WARNINGS
1987 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1988 (i
.op
[op
].regs
+ 8)->reg_name
,
1989 i
.op
[op
].regs
->reg_name
,
1993 /* Warn if the r prefix on a general reg is missing. */
1994 else if ((i
.types
[op
] & Reg64
) != 0
1995 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1997 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
1998 i
.op
[op
].regs
->reg_name
,
2002 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
2005 if (flag_code
< CODE_64BIT
)
2006 as_bad (_("64bit operations available only in 64bit modes."));
2008 for (op
= i
.operands
; --op
>= 0; )
2009 /* Reject eight bit registers, except where the template
2010 requires them. (eg. movzb) */
2011 if ((i
.types
[op
] & Reg8
) != 0
2012 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2014 as_bad (_("`%%%s' not allowed with `%s%c'"),
2015 i
.op
[op
].regs
->reg_name
,
2020 /* Warn if the e prefix on a general reg is missing. */
2021 else if (((i
.types
[op
] & Reg16
) != 0
2022 || (i
.types
[op
] & Reg32
) != 0)
2023 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
2025 /* Prohibit these changes in the 64bit mode, since
2026 the lowering is more complicated. */
2027 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2028 i
.op
[op
].regs
->reg_name
,
2032 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
2035 for (op
= i
.operands
; --op
>= 0;)
2036 /* Reject eight bit registers, except where the template
2037 requires them. (eg. movzb) */
2038 if ((i
.types
[op
] & Reg8
) != 0
2039 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
2041 as_bad (_("`%%%s' not allowed with `%s%c'"),
2042 i
.op
[op
].regs
->reg_name
,
2047 /* Warn if the e prefix on a general reg is present. */
2048 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
2049 && (i
.types
[op
] & Reg32
) != 0
2050 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
2052 /* Prohibit these changes in the 64bit mode, since
2053 the lowering is more complicated. */
2054 if (flag_code
== CODE_64BIT
)
2055 as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
2056 i
.op
[op
].regs
->reg_name
,
2059 #if REGISTER_WARNINGS
2060 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2061 (i
.op
[op
].regs
- 8)->reg_name
,
2062 i
.op
[op
].regs
->reg_name
,
2067 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
2068 /* Do nothing if the instruction is going to ignore the prefix. */
2073 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
2075 i
.suffix
= stackop_size
;
2077 /* Make still unresolved immediate matches conform to size of immediate
2078 given in i.suffix. Note: overlap2 cannot be an immediate! */
2079 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
| Imm32S
))
2080 && overlap0
!= Imm8
&& overlap0
!= Imm8S
2081 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2082 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2086 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2087 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2088 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2090 else if (overlap0
== (Imm16
| Imm32S
| Imm32
)
2091 || overlap0
== (Imm16
| Imm32
)
2092 || overlap0
== (Imm16
| Imm32S
))
2095 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2097 if (overlap0
!= Imm8
&& overlap0
!= Imm8S
2098 && overlap0
!= Imm16
&& overlap0
!= Imm32S
2099 && overlap0
!= Imm32
&& overlap0
!= Imm64
)
2101 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2105 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32S
| Imm32
))
2106 && overlap1
!= Imm8
&& overlap1
!= Imm8S
2107 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2108 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2112 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
2113 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
:
2114 (i
.suffix
== QWORD_MNEM_SUFFIX
? Imm64
| Imm32S
: Imm32
)));
2116 else if (overlap1
== (Imm16
| Imm32
| Imm32S
)
2117 || overlap1
== (Imm16
| Imm32
)
2118 || overlap1
== (Imm16
| Imm32S
))
2121 ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32S
;
2123 if (overlap1
!= Imm8
&& overlap1
!= Imm8S
2124 && overlap1
!= Imm16
&& overlap1
!= Imm32S
2125 && overlap1
!= Imm32
&& overlap1
!= Imm64
)
2127 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1
, i
.suffix
);
2131 assert ((overlap2
& Imm
) == 0);
2133 i
.types
[0] = overlap0
;
2134 if (overlap0
& ImplicitRegister
)
2136 if (overlap0
& Imm1
)
2137 i
.imm_operands
= 0; /* kludge for shift insns. */
2139 i
.types
[1] = overlap1
;
2140 if (overlap1
& ImplicitRegister
)
2143 i
.types
[2] = overlap2
;
2144 if (overlap2
& ImplicitRegister
)
2147 /* Finalize opcode. First, we change the opcode based on the operand
2148 size given by i.suffix: We need not change things for byte insns. */
2150 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
2152 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2156 /* For movzx and movsx, need to check the register type. */
2158 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
2159 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
2161 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2163 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
2164 if (!add_prefix (prefix
))
2168 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
2170 /* It's not a byte, select word/dword operation. */
2171 if (i
.tm
.opcode_modifier
& W
)
2173 if (i
.tm
.opcode_modifier
& ShortForm
)
2174 i
.tm
.base_opcode
|= 8;
2176 i
.tm
.base_opcode
|= 1;
2178 /* Now select between word & dword operations via the operand
2179 size prefix, except for instructions that will ignore this
2181 if (i
.suffix
!= QWORD_MNEM_SUFFIX
2182 && (i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
2183 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
2185 unsigned int prefix
= DATA_PREFIX_OPCODE
;
2186 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
2187 prefix
= ADDR_PREFIX_OPCODE
;
2189 if (! add_prefix (prefix
))
2193 /* Set mode64 for an operand. */
2194 if (i
.suffix
== QWORD_MNEM_SUFFIX
2195 && !(i
.tm
.opcode_modifier
& NoRex64
))
2198 /* Size floating point instruction. */
2199 if (i
.suffix
== LONG_MNEM_SUFFIX
)
2201 if (i
.tm
.opcode_modifier
& FloatMF
)
2202 i
.tm
.base_opcode
^= 4;
2206 if (i
.tm
.opcode_modifier
& ImmExt
)
2208 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2209 opcode suffix which is coded in the same place as an 8-bit
2210 immediate field would be. Here we fake an 8-bit immediate
2211 operand from the opcode suffix stored in tm.extension_opcode. */
2215 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
2217 exp
= &im_expressions
[i
.imm_operands
++];
2218 i
.op
[i
.operands
].imms
= exp
;
2219 i
.types
[i
.operands
++] = Imm8
;
2220 exp
->X_op
= O_constant
;
2221 exp
->X_add_number
= i
.tm
.extension_opcode
;
2222 i
.tm
.extension_opcode
= None
;
2225 /* For insns with operands there are more diddles to do to the opcode. */
2228 /* Default segment register this instruction will use
2229 for memory accesses. 0 means unknown.
2230 This is only for optimizing out unnecessary segment overrides. */
2231 const seg_entry
*default_seg
= 0;
2233 /* The imul $imm, %reg instruction is converted into
2234 imul $imm, %reg, %reg, and the clr %reg instruction
2235 is converted into xor %reg, %reg. */
2236 if (i
.tm
.opcode_modifier
& regKludge
)
2238 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
2239 /* Pretend we saw the extra register operand. */
2240 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
2241 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
2242 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
2246 if (i
.tm
.opcode_modifier
& ShortForm
)
2248 /* The register or float register operand is in operand 0 or 1. */
2249 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
2250 /* Register goes in low 3 bits of opcode. */
2251 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
2252 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2254 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2256 /* Warn about some common errors, but press on regardless.
2257 The first case can be generated by gcc (<= 2.8.1). */
2258 if (i
.operands
== 2)
2260 /* Reversed arguments on faddp, fsubp, etc. */
2261 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2262 i
.op
[1].regs
->reg_name
,
2263 i
.op
[0].regs
->reg_name
);
2267 /* Extraneous `l' suffix on fp insn. */
2268 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2269 i
.op
[0].regs
->reg_name
);
2273 else if (i
.tm
.opcode_modifier
& Modrm
)
2275 /* The opcode is completed (modulo i.tm.extension_opcode which
2276 must be put into the modrm byte).
2277 Now, we make the modrm & index base bytes based on all the
2278 info we've collected. */
2280 /* i.reg_operands MUST be the number of real register operands;
2281 implicit registers do not count. */
2282 if (i
.reg_operands
== 2)
2284 unsigned int source
, dest
;
2285 source
= ((i
.types
[0]
2286 & (Reg
| RegMMX
| RegXMM
2288 | Control
| Debug
| Test
))
2293 /* One of the register operands will be encoded in the
2294 i.tm.reg field, the other in the combined i.tm.mode
2295 and i.tm.regmem fields. If no form of this
2296 instruction supports a memory destination operand,
2297 then we assume the source operand may sometimes be
2298 a memory operand and so we need to store the
2299 destination in the i.rm.reg field. */
2300 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2302 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2303 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2304 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2306 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2311 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2312 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2313 if (i
.op
[dest
].regs
->reg_flags
& RegRex
)
2315 if (i
.op
[source
].regs
->reg_flags
& RegRex
)
2320 { /* If it's not 2 reg operands... */
2323 unsigned int fake_zero_displacement
= 0;
2324 unsigned int op
= ((i
.types
[0] & AnyMem
)
2326 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2333 if (! i
.disp_operands
)
2334 fake_zero_displacement
= 1;
2337 /* Operand is just <disp> */
2338 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
2340 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2341 i
.types
[op
] &= ~Disp
;
2342 i
.types
[op
] |= Disp16
;
2344 else if (flag_code
!= CODE_64BIT
)
2346 i
.rm
.regmem
= NO_BASE_REGISTER
;
2347 i
.types
[op
] &= ~Disp
;
2348 i
.types
[op
] |= Disp32
;
2352 /* 64bit mode overwrites the 32bit absolute addressing
2353 by RIP relative addressing and absolute addressing
2354 is encoded by one of the redundant SIB forms. */
2356 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2357 i
.sib
.base
= NO_BASE_REGISTER
;
2358 i
.sib
.index
= NO_INDEX_REGISTER
;
2359 i
.types
[op
] &= ~Disp
;
2360 i
.types
[op
] |= Disp32S
;
2363 else /* ! i.base_reg && i.index_reg */
2365 i
.sib
.index
= i
.index_reg
->reg_num
;
2366 i
.sib
.base
= NO_BASE_REGISTER
;
2367 i
.sib
.scale
= i
.log2_scale_factor
;
2368 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2369 i
.types
[op
] &= ~Disp
;
2370 if (flag_code
!= CODE_64BIT
)
2371 i
.types
[op
] |= Disp32
; /* Must be 32 bit */
2373 i
.types
[op
] |= Disp32S
;
2374 if (i
.index_reg
->reg_flags
& RegRex
)
2378 /* RIP addressing for 64bit mode. */
2379 else if (i
.base_reg
->reg_type
== BaseIndex
)
2381 i
.rm
.regmem
= NO_BASE_REGISTER
;
2382 i
.types
[op
] &= ~Disp
;
2383 i
.types
[op
] |= Disp32S
;
2384 i
.flags
[op
] = Operand_PCrel
;
2386 else if (i
.base_reg
->reg_type
& Reg16
)
2388 switch (i
.base_reg
->reg_num
)
2393 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2394 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2401 if ((i
.types
[op
] & Disp
) == 0)
2403 /* fake (%bp) into 0(%bp) */
2404 i
.types
[op
] |= Disp8
;
2405 fake_zero_displacement
= 1;
2408 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2409 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2411 default: /* (%si) -> 4 or (%di) -> 5 */
2412 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2414 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2416 else /* i.base_reg and 32/64 bit mode */
2418 if (flag_code
== CODE_64BIT
2419 && (i
.types
[op
] & Disp
))
2421 if (i
.types
[op
] & Disp8
)
2422 i
.types
[op
] = Disp8
| Disp32S
;
2424 i
.types
[op
] = Disp32S
;
2426 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2427 if (i
.base_reg
->reg_flags
& RegRex
)
2429 i
.sib
.base
= i
.base_reg
->reg_num
;
2430 /* x86-64 ignores REX prefix bit here to avoid
2431 decoder complications. */
2432 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
2435 if (i
.disp_operands
== 0)
2437 fake_zero_displacement
= 1;
2438 i
.types
[op
] |= Disp8
;
2441 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2445 i
.sib
.scale
= i
.log2_scale_factor
;
2448 /* <disp>(%esp) becomes two byte modrm
2449 with no index register. We've already
2450 stored the code for esp in i.rm.regmem
2451 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2452 base register besides %esp will not use
2453 the extra modrm byte. */
2454 i
.sib
.index
= NO_INDEX_REGISTER
;
2455 #if ! SCALE1_WHEN_NO_INDEX
2456 /* Another case where we force the second
2458 if (i
.log2_scale_factor
)
2459 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2464 i
.sib
.index
= i
.index_reg
->reg_num
;
2465 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2466 if (i
.index_reg
->reg_flags
& RegRex
)
2469 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2472 if (fake_zero_displacement
)
2474 /* Fakes a zero displacement assuming that i.types[op]
2475 holds the correct displacement size. */
2478 assert (i
.op
[op
].disps
== 0);
2479 exp
= &disp_expressions
[i
.disp_operands
++];
2480 i
.op
[op
].disps
= exp
;
2481 exp
->X_op
= O_constant
;
2482 exp
->X_add_number
= 0;
2483 exp
->X_add_symbol
= (symbolS
*) 0;
2484 exp
->X_op_symbol
= (symbolS
*) 0;
2488 /* Fill in i.rm.reg or i.rm.regmem field with register
2489 operand (if any) based on i.tm.extension_opcode.
2490 Again, we must be careful to make sure that
2491 segment/control/debug/test/MMX registers are coded
2492 into the i.rm.reg field. */
2497 & (Reg
| RegMMX
| RegXMM
2499 | Control
| Debug
| Test
))
2502 & (Reg
| RegMMX
| RegXMM
2504 | Control
| Debug
| Test
))
2507 /* If there is an extension opcode to put here, the
2508 register number must be put into the regmem field. */
2509 if (i
.tm
.extension_opcode
!= None
)
2511 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2512 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2517 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2518 if (i
.op
[op
].regs
->reg_flags
& RegRex
)
2522 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2523 we must set it to 3 to indicate this is a register
2524 operand in the regmem field. */
2525 if (!i
.mem_operands
)
2529 /* Fill in i.rm.reg field with extension opcode (if any). */
2530 if (i
.tm
.extension_opcode
!= None
)
2531 i
.rm
.reg
= i
.tm
.extension_opcode
;
2534 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2536 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2537 && i
.op
[0].regs
->reg_num
== 1)
2539 as_bad (_("you can't `pop %%cs'"));
2542 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2543 if (i
.op
[0].regs
->reg_flags
& RegRex
)
2546 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2550 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2552 /* For the string instructions that allow a segment override
2553 on one of their operands, the default segment is ds. */
2557 /* If a segment was explicitly specified,
2558 and the specified segment is not the default,
2559 use an opcode prefix to select it.
2560 If we never figured out what the default segment is,
2561 then default_seg will be zero at this point,
2562 and the specified segment prefix will always be used. */
2563 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2565 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2569 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2571 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2572 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2576 /* Handle conversion of 'int $3' --> special int3 insn. */
2577 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2579 i
.tm
.base_opcode
= INT3_OPCODE
;
2583 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2584 && i
.op
[0].disps
->X_op
== O_constant
)
2586 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2587 the absolute address given by the constant. Since ix86 jumps and
2588 calls are pc relative, we need to generate a reloc. */
2589 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2590 i
.op
[0].disps
->X_op
= O_symbol
;
2593 if (i
.tm
.opcode_modifier
& Rex64
)
2596 /* For 8bit registers we would need an empty rex prefix.
2597 Also in the case instruction is already having prefix,
2598 we need to convert old registers to new ones. */
2600 if (((i
.types
[0] & Reg8
) && (i
.op
[0].regs
->reg_flags
& RegRex64
))
2601 || ((i
.types
[1] & Reg8
) && (i
.op
[1].regs
->reg_flags
& RegRex64
))
2602 || ((i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2603 && ((i
.types
[0] & Reg8
) || (i
.types
[1] & Reg8
))))
2607 for (x
= 0; x
< 2; x
++)
2609 /* Look for 8bit operand that does use old registers. */
2610 if (i
.types
[x
] & Reg8
2611 && !(i
.op
[x
].regs
->reg_flags
& RegRex64
))
2613 /* In case it is "hi" register, give up. */
2614 if (i
.op
[x
].regs
->reg_num
> 3)
2615 as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"),
2616 i
.op
[x
].regs
->reg_name
);
2618 /* Otherwise it is equivalent to the extended register.
2619 Since the encoding don't change this is merely cosmetical
2620 cleanup for debug output. */
2622 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2627 if (i
.rex
.mode64
|| i
.rex
.extX
|| i
.rex
.extY
|| i
.rex
.extZ
|| i
.rex
.empty
)
2629 | (i
.rex
.mode64
? 8 : 0)
2630 | (i
.rex
.extX
? 4 : 0)
2631 | (i
.rex
.extY
? 2 : 0)
2632 | (i
.rex
.extZ
? 1 : 0));
2634 /* We are ready to output the insn. */
2639 if (i
.tm
.opcode_modifier
& Jump
)
2646 if (flag_code
== CODE_16BIT
)
2650 if (i
.prefix
[DATA_PREFIX
])
2656 if (i
.prefix
[REX_PREFIX
])
2666 if (i
.prefixes
!= 0 && !intel_syntax
)
2667 as_warn (_("skipping prefixes on this instruction"));
2669 /* It's always a symbol; End frag & setup for relax.
2670 Make sure there is enough room in this frag for the largest
2671 instruction we may generate in md_convert_frag. This is 2
2672 bytes for the opcode and room for the prefix and largest
2674 frag_grow (prefix
+ 2 + size
);
2675 insn_size
+= prefix
+ 1;
2676 /* Prefix and 1 opcode byte go in fr_fix. */
2677 p
= frag_more (prefix
+ 1);
2678 if (i
.prefix
[DATA_PREFIX
])
2679 *p
++ = DATA_PREFIX_OPCODE
;
2680 if (i
.prefix
[REX_PREFIX
])
2681 *p
++ = i
.prefix
[REX_PREFIX
];
2682 *p
= i
.tm
.base_opcode
;
2683 /* 1 possible extra opcode + displacement go in var part.
2684 Pass reloc in fr_var. */
2685 frag_var (rs_machine_dependent
,
2688 ((unsigned char) *p
== JUMP_PC_RELATIVE
2689 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2690 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2691 i
.op
[0].disps
->X_add_symbol
,
2692 i
.op
[0].disps
->X_add_number
,
2695 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2699 if (i
.tm
.opcode_modifier
& JumpByte
)
2701 /* This is a loop or jecxz type instruction. */
2703 if (i
.prefix
[ADDR_PREFIX
])
2706 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2715 if (flag_code
== CODE_16BIT
)
2718 if (i
.prefix
[DATA_PREFIX
])
2721 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2731 if (i
.prefix
[REX_PREFIX
])
2733 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
2738 if (i
.prefixes
!= 0 && !intel_syntax
)
2739 as_warn (_("skipping prefixes on this instruction"));
2741 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2743 insn_size
+= 1 + size
;
2744 p
= frag_more (1 + size
);
2748 /* Opcode can be at most two bytes. */
2749 insn_size
+= 2 + size
;
2750 p
= frag_more (2 + size
);
2751 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2753 *p
++ = i
.tm
.base_opcode
& 0xff;
2755 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2756 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.disp_reloc
[0]));
2758 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2765 if (flag_code
== CODE_16BIT
)
2769 if (i
.prefix
[DATA_PREFIX
])
2775 if (i
.prefix
[REX_PREFIX
])
2785 if (i
.prefixes
!= 0 && !intel_syntax
)
2786 as_warn (_("skipping prefixes on this instruction"));
2788 /* 1 opcode; 2 segment; offset */
2789 insn_size
+= prefix
+ 1 + 2 + size
;
2790 p
= frag_more (prefix
+ 1 + 2 + size
);
2792 if (i
.prefix
[DATA_PREFIX
])
2793 *p
++ = DATA_PREFIX_OPCODE
;
2795 if (i
.prefix
[REX_PREFIX
])
2796 *p
++ = i
.prefix
[REX_PREFIX
];
2798 *p
++ = i
.tm
.base_opcode
;
2799 if (i
.op
[1].imms
->X_op
== O_constant
)
2801 offsetT n
= i
.op
[1].imms
->X_add_number
;
2804 && !fits_in_unsigned_word (n
)
2805 && !fits_in_signed_word (n
))
2807 as_bad (_("16-bit jump out of range"));
2810 md_number_to_chars (p
, n
, size
);
2813 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2814 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.disp_reloc
[0]));
2815 if (i
.op
[0].imms
->X_op
!= O_constant
)
2816 as_bad (_("can't handle non absolute segment in `%s'"),
2818 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2822 /* Output normal instructions here. */
2825 /* The prefix bytes. */
2827 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2834 md_number_to_chars (p
, (valueT
) *q
, 1);
2838 /* Now the opcode; be careful about word order here! */
2839 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2842 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2844 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2848 /* Put out high byte first: can't use md_number_to_chars! */
2849 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2850 *p
= i
.tm
.base_opcode
& 0xff;
2853 { /* Opcode is either 3 or 4 bytes. */
2854 if (i
.tm
.base_opcode
& 0xff000000)
2858 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2865 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2866 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2867 *p
= (i
.tm
.base_opcode
) & 0xff;
2870 /* Now the modrm byte and sib byte (if present). */
2871 if (i
.tm
.opcode_modifier
& Modrm
)
2875 md_number_to_chars (p
,
2876 (valueT
) (i
.rm
.regmem
<< 0
2880 /* If i.rm.regmem == ESP (4)
2881 && i.rm.mode != (Register mode)
2883 ==> need second modrm byte. */
2884 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2886 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2890 md_number_to_chars (p
,
2891 (valueT
) (i
.sib
.base
<< 0
2893 | i
.sib
.scale
<< 6),
2898 if (i
.disp_operands
)
2900 register unsigned int n
;
2902 for (n
= 0; n
< i
.operands
; n
++)
2904 if (i
.types
[n
] & Disp
)
2906 if (i
.op
[n
].disps
->X_op
== O_constant
)
2912 if (i
.types
[n
] & (Disp8
| Disp16
| Disp64
))
2915 if (i
.types
[n
] & Disp8
)
2917 if (i
.types
[n
] & Disp64
)
2920 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2923 p
= frag_more (size
);
2924 md_number_to_chars (p
, val
, size
);
2930 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
2932 /* The PC relative address is computed relative
2933 to the instruction boundary, so in case immediate
2934 fields follows, we need to adjust the value. */
2935 if (pcrel
&& i
.imm_operands
)
2938 register unsigned int n1
;
2940 for (n1
= 0; n1
< i
.operands
; n1
++)
2941 if (i
.types
[n1
] & Imm
)
2943 if (i
.types
[n1
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2946 if (i
.types
[n1
] & (Imm8
| Imm8S
))
2948 if (i
.types
[n1
] & Imm64
)
2953 /* We should find the immediate. */
2954 if (n1
== i
.operands
)
2956 i
.op
[n
].disps
->X_add_number
-= imm_size
;
2959 if (i
.types
[n
] & Disp32S
)
2962 if (i
.types
[n
] & (Disp16
| Disp64
))
2965 if (i
.types
[n
] & Disp64
)
2970 p
= frag_more (size
);
2971 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2972 i
.op
[n
].disps
, pcrel
,
2973 reloc (size
, pcrel
, sign
, i
.disp_reloc
[n
]));
2979 /* Output immediate. */
2982 register unsigned int n
;
2984 for (n
= 0; n
< i
.operands
; n
++)
2986 if (i
.types
[n
] & Imm
)
2988 if (i
.op
[n
].imms
->X_op
== O_constant
)
2994 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
2997 if (i
.types
[n
] & (Imm8
| Imm8S
))
2999 else if (i
.types
[n
] & Imm64
)
3002 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
3005 p
= frag_more (size
);
3006 md_number_to_chars (p
, val
, size
);
3010 /* Not absolute_section.
3011 Need a 32-bit fixup (don't support 8bit
3012 non-absolute imms). Try to support other
3014 #ifdef BFD_ASSEMBLER
3015 enum bfd_reloc_code_real reloc_type
;
3022 if ((i
.types
[n
] & (Imm32S
))
3023 && i
.suffix
== QWORD_MNEM_SUFFIX
)
3025 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
| Imm64
))
3028 if (i
.types
[n
] & (Imm8
| Imm8S
))
3030 if (i
.types
[n
] & Imm64
)
3035 p
= frag_more (size
);
3036 reloc_type
= reloc (size
, 0, sign
, i
.disp_reloc
[0]);
3037 #ifdef BFD_ASSEMBLER
3038 if (reloc_type
== BFD_RELOC_32
3040 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
3041 && (i
.op
[n
].imms
->X_op
== O_symbol
3042 || (i
.op
[n
].imms
->X_op
== O_add
3043 && ((symbol_get_value_expression
3044 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
3047 /* We don't support dynamic linking on x86-64 yet. */
3048 if (flag_code
== CODE_64BIT
)
3050 reloc_type
= BFD_RELOC_386_GOTPC
;
3051 i
.op
[n
].imms
->X_add_number
+= 3;
3054 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
3055 i
.op
[n
].imms
, 0, reloc_type
);
3062 dwarf2_emit_insn (insn_size
);
3069 #endif /* DEBUG386 */
3073 static int i386_immediate
PARAMS ((char *));
3076 i386_immediate (imm_start
)
3079 char *save_input_line_pointer
;
3083 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
3085 as_bad (_("only 1 or 2 immediate operands are allowed"));
3089 exp
= &im_expressions
[i
.imm_operands
++];
3090 i
.op
[this_operand
].imms
= exp
;
3092 if (is_space_char (*imm_start
))
3095 save_input_line_pointer
= input_line_pointer
;
3096 input_line_pointer
= imm_start
;
3100 /* We can have operands of the form
3101 <symbol>@GOTOFF+<nnn>
3102 Take the easy way out here and copy everything
3103 into a temporary buffer... */
3106 cp
= strchr (input_line_pointer
, '@');
3113 /* GOT relocations are not supported in 16 bit mode. */
3114 if (flag_code
== CODE_16BIT
)
3115 as_bad (_("GOT relocations not supported in 16 bit mode"));
3117 if (GOT_symbol
== NULL
)
3118 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3120 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3122 if (flag_code
== CODE_64BIT
)
3123 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3125 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3128 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3130 if (flag_code
== CODE_64BIT
)
3131 as_bad ("GOTOFF relocations are unsupported in 64bit mode.");
3132 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3135 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3137 if (flag_code
== CODE_64BIT
)
3138 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3140 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3143 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3145 if (flag_code
== CODE_64BIT
)
3146 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3148 as_bad ("GOTPCREL relocations are supported only in 64bit mode.");
3152 as_bad (_("bad reloc specifier in expression"));
3154 /* Replace the relocation token with ' ', so that errors like
3155 foo@GOTOFF1 will be detected. */
3156 first
= cp
- input_line_pointer
;
3157 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3158 memcpy (tmpbuf
, input_line_pointer
, first
);
3159 tmpbuf
[first
] = ' ';
3160 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3161 input_line_pointer
= tmpbuf
;
3166 exp_seg
= expression (exp
);
3169 if (*input_line_pointer
)
3170 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
3172 input_line_pointer
= save_input_line_pointer
;
3174 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3176 /* Missing or bad expr becomes absolute 0. */
3177 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3179 exp
->X_op
= O_constant
;
3180 exp
->X_add_number
= 0;
3181 exp
->X_add_symbol
= (symbolS
*) 0;
3182 exp
->X_op_symbol
= (symbolS
*) 0;
3184 else if (exp
->X_op
== O_constant
)
3186 /* Size it properly later. */
3187 i
.types
[this_operand
] |= Imm64
;
3188 /* If BFD64, sign extend val. */
3189 if (!use_rela_relocations
)
3190 if ((exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
3191 exp
->X_add_number
= (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
3193 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3195 #ifdef BFD_ASSEMBLER
3196 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3198 && exp_seg
!= text_section
3199 && exp_seg
!= data_section
3200 && exp_seg
!= bss_section
3201 && exp_seg
!= undefined_section
3202 #ifdef BFD_ASSEMBLER
3203 && !bfd_is_com_section (exp_seg
)
3207 #ifdef BFD_ASSEMBLER
3208 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3210 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3217 /* This is an address. The size of the address will be
3218 determined later, depending on destination register,
3219 suffix, or the default for the section. */
3220 i
.types
[this_operand
] |= Imm8
| Imm16
| Imm32
| Imm32S
| Imm64
;
3226 static int i386_scale
PARAMS ((char *));
3232 if (!isdigit (*scale
))
3239 i
.log2_scale_factor
= 0;
3242 i
.log2_scale_factor
= 1;
3245 i
.log2_scale_factor
= 2;
3248 i
.log2_scale_factor
= 3;
3252 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3256 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
3258 as_warn (_("scale factor of %d without an index register"),
3259 1 << i
.log2_scale_factor
);
3260 #if SCALE1_WHEN_NO_INDEX
3261 i
.log2_scale_factor
= 0;
3267 static int i386_displacement
PARAMS ((char *, char *));
3270 i386_displacement (disp_start
, disp_end
)
3274 register expressionS
*exp
;
3276 char *save_input_line_pointer
;
3277 int bigdisp
= Disp32
;
3279 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3281 if (flag_code
== CODE_64BIT
)
3283 i
.types
[this_operand
] |= bigdisp
;
3285 exp
= &disp_expressions
[i
.disp_operands
];
3286 i
.op
[this_operand
].disps
= exp
;
3288 save_input_line_pointer
= input_line_pointer
;
3289 input_line_pointer
= disp_start
;
3290 END_STRING_AND_SAVE (disp_end
);
3292 #ifndef GCC_ASM_O_HACK
3293 #define GCC_ASM_O_HACK 0
3296 END_STRING_AND_SAVE (disp_end
+ 1);
3297 if ((i
.types
[this_operand
] & BaseIndex
) != 0
3298 && displacement_string_end
[-1] == '+')
3300 /* This hack is to avoid a warning when using the "o"
3301 constraint within gcc asm statements.
3304 #define _set_tssldt_desc(n,addr,limit,type) \
3305 __asm__ __volatile__ ( \
3307 "movw %w1,2+%0\n\t" \
3309 "movb %b1,4+%0\n\t" \
3310 "movb %4,5+%0\n\t" \
3311 "movb $0,6+%0\n\t" \
3312 "movb %h1,7+%0\n\t" \
3314 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3316 This works great except that the output assembler ends
3317 up looking a bit weird if it turns out that there is
3318 no offset. You end up producing code that looks like:
3331 So here we provide the missing zero. */
3333 *displacement_string_end
= '0';
3338 /* We can have operands of the form
3339 <symbol>@GOTOFF+<nnn>
3340 Take the easy way out here and copy everything
3341 into a temporary buffer... */
3344 cp
= strchr (input_line_pointer
, '@');
3351 /* GOT relocations are not supported in 16 bit mode. */
3352 if (flag_code
== CODE_16BIT
)
3353 as_bad (_("GOT relocations not supported in 16 bit mode"));
3355 if (GOT_symbol
== NULL
)
3356 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
3358 if (strncmp (cp
+ 1, "PLT", 3) == 0)
3360 if (flag_code
== CODE_64BIT
)
3361 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_PLT32
;
3363 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
3366 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
3368 if (flag_code
== CODE_64BIT
)
3369 as_bad ("GOTOFF relocation is not supported in 64bit mode.");
3370 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
3373 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
3375 if (flag_code
== CODE_64BIT
)
3376 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOT32
;
3378 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
3381 else if (strncmp (cp
+ 1, "GOTPCREL", 3) == 0)
3383 if (flag_code
!= CODE_64BIT
)
3384 as_bad ("GOTPCREL relocation is supported only in 64bit mode.");
3385 i
.disp_reloc
[this_operand
] = BFD_RELOC_X86_64_GOTPCREL
;
3389 as_bad (_("bad reloc specifier in expression"));
3391 /* Replace the relocation token with ' ', so that errors like
3392 foo@GOTOFF1 will be detected. */
3393 first
= cp
- input_line_pointer
;
3394 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
3395 memcpy (tmpbuf
, input_line_pointer
, first
);
3396 tmpbuf
[first
] = ' ';
3397 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
3398 input_line_pointer
= tmpbuf
;
3403 exp_seg
= expression (exp
);
3405 #ifdef BFD_ASSEMBLER
3406 /* We do this to make sure that the section symbol is in
3407 the symbol table. We will ultimately change the relocation
3408 to be relative to the beginning of the section. */
3409 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
3410 || i
.disp_reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
3412 if (S_IS_LOCAL(exp
->X_add_symbol
)
3413 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
3414 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
3415 assert (exp
->X_op
== O_symbol
);
3416 exp
->X_op
= O_subtract
;
3417 exp
->X_op_symbol
= GOT_symbol
;
3418 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
3423 if (*input_line_pointer
)
3424 as_bad (_("ignoring junk `%s' after expression"),
3425 input_line_pointer
);
3427 RESTORE_END_STRING (disp_end
+ 1);
3429 RESTORE_END_STRING (disp_end
);
3430 input_line_pointer
= save_input_line_pointer
;
3432 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
3434 /* Missing or bad expr becomes absolute 0. */
3435 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3437 exp
->X_op
= O_constant
;
3438 exp
->X_add_number
= 0;
3439 exp
->X_add_symbol
= (symbolS
*) 0;
3440 exp
->X_op_symbol
= (symbolS
*) 0;
3443 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3444 if (exp
->X_op
!= O_constant
3445 #ifdef BFD_ASSEMBLER
3446 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
3448 && exp_seg
!= text_section
3449 && exp_seg
!= data_section
3450 && exp_seg
!= bss_section
3451 && exp_seg
!= undefined_section
)
3453 #ifdef BFD_ASSEMBLER
3454 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
3456 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3461 else if (flag_code
== CODE_64BIT
)
3462 i
.types
[this_operand
] |= Disp32S
| Disp32
;
3466 static int i386_index_check
PARAMS((const char *));
3468 /* Make sure the memory operand we've been dealt is valid.
3469 Return 1 on success, 0 on a failure. */
3472 i386_index_check (operand_string
)
3473 const char *operand_string
;
3476 #if INFER_ADDR_PREFIX
3482 if (flag_code
== CODE_64BIT
)
3486 && ((i
.base_reg
->reg_type
& Reg64
) == 0)
3487 && (i
.base_reg
->reg_type
!= BaseIndex
3490 && ((i
.index_reg
->reg_type
& (Reg64
|BaseIndex
))
3491 != (Reg64
|BaseIndex
))))
3496 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
3500 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
|RegRex
))
3501 != (Reg16
|BaseIndex
)))
3503 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3504 != (Reg16
|BaseIndex
))
3506 && i
.base_reg
->reg_num
< 6
3507 && i
.index_reg
->reg_num
>= 6
3508 && i
.log2_scale_factor
== 0))))
3515 && (i
.base_reg
->reg_type
& (Reg32
| RegRex
)) != Reg32
)
3517 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
|RegRex
))
3518 != (Reg32
|BaseIndex
))))
3524 #if INFER_ADDR_PREFIX
3525 if (flag_code
!= CODE_64BIT
3526 && i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3528 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3530 /* Change the size of any displacement too. At most one of
3531 Disp16 or Disp32 is set.
3532 FIXME. There doesn't seem to be any real need for separate
3533 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3534 Removing them would probably clean up the code quite a lot. */
3535 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3536 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3541 as_bad (_("`%s' is not a valid base/index expression"),
3545 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3547 flag_code_names
[flag_code
]);
3553 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3557 i386_operand (operand_string
)
3558 char *operand_string
;
3562 char *op_string
= operand_string
;
3564 if (is_space_char (*op_string
))
3567 /* We check for an absolute prefix (differentiating,
3568 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3569 if (*op_string
== ABSOLUTE_PREFIX
)
3572 if (is_space_char (*op_string
))
3574 i
.types
[this_operand
] |= JumpAbsolute
;
3577 /* Check if operand is a register. */
3578 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3579 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3581 /* Check for a segment override by searching for ':' after a
3582 segment register. */
3584 if (is_space_char (*op_string
))
3586 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3591 i
.seg
[i
.mem_operands
] = &es
;
3594 i
.seg
[i
.mem_operands
] = &cs
;
3597 i
.seg
[i
.mem_operands
] = &ss
;
3600 i
.seg
[i
.mem_operands
] = &ds
;
3603 i
.seg
[i
.mem_operands
] = &fs
;
3606 i
.seg
[i
.mem_operands
] = &gs
;
3610 /* Skip the ':' and whitespace. */
3612 if (is_space_char (*op_string
))
3615 if (!is_digit_char (*op_string
)
3616 && !is_identifier_char (*op_string
)
3617 && *op_string
!= '('
3618 && *op_string
!= ABSOLUTE_PREFIX
)
3620 as_bad (_("bad memory operand `%s'"), op_string
);
3623 /* Handle case of %es:*foo. */
3624 if (*op_string
== ABSOLUTE_PREFIX
)
3627 if (is_space_char (*op_string
))
3629 i
.types
[this_operand
] |= JumpAbsolute
;
3631 goto do_memory_reference
;
3635 as_bad (_("junk `%s' after register"), op_string
);
3638 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3639 i
.op
[this_operand
].regs
= r
;
3642 else if (*op_string
== REGISTER_PREFIX
)
3644 as_bad (_("bad register name `%s'"), op_string
);
3647 else if (*op_string
== IMMEDIATE_PREFIX
)
3650 if (i
.types
[this_operand
] & JumpAbsolute
)
3652 as_bad (_("immediate operand illegal with absolute jump"));
3655 if (!i386_immediate (op_string
))
3658 else if (is_digit_char (*op_string
)
3659 || is_identifier_char (*op_string
)
3660 || *op_string
== '(' )
3662 /* This is a memory reference of some sort. */
3665 /* Start and end of displacement string expression (if found). */
3666 char *displacement_string_start
;
3667 char *displacement_string_end
;
3669 do_memory_reference
:
3670 if ((i
.mem_operands
== 1
3671 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3672 || i
.mem_operands
== 2)
3674 as_bad (_("too many memory references for `%s'"),
3675 current_templates
->start
->name
);
3679 /* Check for base index form. We detect the base index form by
3680 looking for an ')' at the end of the operand, searching
3681 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3683 base_string
= op_string
+ strlen (op_string
);
3686 if (is_space_char (*base_string
))
3689 /* If we only have a displacement, set-up for it to be parsed later. */
3690 displacement_string_start
= op_string
;
3691 displacement_string_end
= base_string
+ 1;
3693 if (*base_string
== ')')
3696 unsigned int parens_balanced
= 1;
3697 /* We've already checked that the number of left & right ()'s are
3698 equal, so this loop will not be infinite. */
3702 if (*base_string
== ')')
3704 if (*base_string
== '(')
3707 while (parens_balanced
);
3709 temp_string
= base_string
;
3711 /* Skip past '(' and whitespace. */
3713 if (is_space_char (*base_string
))
3716 if (*base_string
== ','
3717 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3718 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3720 displacement_string_end
= temp_string
;
3722 i
.types
[this_operand
] |= BaseIndex
;
3726 base_string
= end_op
;
3727 if (is_space_char (*base_string
))
3731 /* There may be an index reg or scale factor here. */
3732 if (*base_string
== ',')
3735 if (is_space_char (*base_string
))
3738 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3739 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3741 base_string
= end_op
;
3742 if (is_space_char (*base_string
))
3744 if (*base_string
== ',')
3747 if (is_space_char (*base_string
))
3750 else if (*base_string
!= ')' )
3752 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3757 else if (*base_string
== REGISTER_PREFIX
)
3759 as_bad (_("bad register name `%s'"), base_string
);
3763 /* Check for scale factor. */
3764 if (isdigit ((unsigned char) *base_string
))
3766 if (!i386_scale (base_string
))
3770 if (is_space_char (*base_string
))
3772 if (*base_string
!= ')')
3774 as_bad (_("expecting `)' after scale factor in `%s'"),
3779 else if (!i
.index_reg
)
3781 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3786 else if (*base_string
!= ')')
3788 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3793 else if (*base_string
== REGISTER_PREFIX
)
3795 as_bad (_("bad register name `%s'"), base_string
);
3800 /* If there's an expression beginning the operand, parse it,
3801 assuming displacement_string_start and
3802 displacement_string_end are meaningful. */
3803 if (displacement_string_start
!= displacement_string_end
)
3805 if (!i386_displacement (displacement_string_start
,
3806 displacement_string_end
))
3810 /* Special case for (%dx) while doing input/output op. */
3812 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3814 && i
.log2_scale_factor
== 0
3815 && i
.seg
[i
.mem_operands
] == 0
3816 && (i
.types
[this_operand
] & Disp
) == 0)
3818 i
.types
[this_operand
] = InOutPortReg
;
3822 if (i386_index_check (operand_string
) == 0)
3828 /* It's not a memory operand; argh! */
3829 as_bad (_("invalid char %s beginning operand %d `%s'"),
3830 output_invalid (*op_string
),
3835 return 1; /* Normal return. */
3838 /* md_estimate_size_before_relax()
3840 Called just before relax() for rs_machine_dependent frags. The x86
3841 assembler uses these frags to handle variable size jump
3844 Any symbol that is now undefined will not become defined.
3845 Return the correct fr_subtype in the frag.
3846 Return the initial "guess for variable size of frag" to caller.
3847 The guess is actually the growth beyond the fixed part. Whatever
3848 we do to grow the fixed or variable part contributes to our
3852 md_estimate_size_before_relax (fragP
, segment
)
3853 register fragS
*fragP
;
3854 register segT segment
;
3856 /* We've already got fragP->fr_subtype right; all we have to do is
3857 check for un-relaxable symbols. On an ELF system, we can't relax
3858 an externally visible symbol, because it may be overridden by a
3860 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3861 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3862 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3863 || S_IS_WEAK (fragP
->fr_symbol
)
3867 /* Symbol is undefined in this segment, or we need to keep a
3868 reloc so that weak symbols can be overridden. */
3869 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3870 #ifdef BFD_ASSEMBLER
3871 enum bfd_reloc_code_real reloc_type
;
3875 unsigned char *opcode
;
3878 if (fragP
->fr_var
!= NO_RELOC
)
3879 reloc_type
= fragP
->fr_var
;
3881 reloc_type
= BFD_RELOC_16_PCREL
;
3883 reloc_type
= BFD_RELOC_32_PCREL
;
3885 old_fr_fix
= fragP
->fr_fix
;
3886 opcode
= (unsigned char *) fragP
->fr_opcode
;
3890 case JUMP_PC_RELATIVE
:
3891 /* Make jmp (0xeb) a dword displacement jump. */
3893 fragP
->fr_fix
+= size
;
3894 fix_new (fragP
, old_fr_fix
, size
,
3896 fragP
->fr_offset
, 1,
3901 /* This changes the byte-displacement jump 0x7N
3902 to the dword-displacement jump 0x0f,0x8N. */
3903 opcode
[1] = opcode
[0] + 0x10;
3904 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3905 /* We've added an opcode byte. */
3906 fragP
->fr_fix
+= 1 + size
;
3907 fix_new (fragP
, old_fr_fix
+ 1, size
,
3909 fragP
->fr_offset
, 1,
3914 return fragP
->fr_fix
- old_fr_fix
;
3916 /* Guess a short jump. */
3920 /* Called after relax() is finished.
3922 In: Address of frag.
3923 fr_type == rs_machine_dependent.
3924 fr_subtype is what the address relaxed to.
3926 Out: Any fixSs and constants are set up.
3927 Caller will turn frag into a ".space 0". */
3929 #ifndef BFD_ASSEMBLER
3931 md_convert_frag (headers
, sec
, fragP
)
3932 object_headers
*headers ATTRIBUTE_UNUSED
;
3933 segT sec ATTRIBUTE_UNUSED
;
3934 register fragS
*fragP
;
3937 md_convert_frag (abfd
, sec
, fragP
)
3938 bfd
*abfd ATTRIBUTE_UNUSED
;
3939 segT sec ATTRIBUTE_UNUSED
;
3940 register fragS
*fragP
;
3943 register unsigned char *opcode
;
3944 unsigned char *where_to_put_displacement
= NULL
;
3945 offsetT target_address
;
3946 offsetT opcode_address
;
3947 unsigned int extension
= 0;
3948 offsetT displacement_from_opcode_start
;
3950 opcode
= (unsigned char *) fragP
->fr_opcode
;
3952 /* Address we want to reach in file space. */
3953 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3954 #ifdef BFD_ASSEMBLER
3955 /* Not needed otherwise? */
3956 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3959 /* Address opcode resides at in file space. */
3960 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3962 /* Displacement from opcode start to fill into instruction. */
3963 displacement_from_opcode_start
= target_address
- opcode_address
;
3965 switch (fragP
->fr_subtype
)
3967 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3968 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3969 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3970 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3971 /* Don't have to change opcode. */
3972 extension
= 1; /* 1 opcode + 1 displacement */
3973 where_to_put_displacement
= &opcode
[1];
3976 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3977 extension
= 5; /* 2 opcode + 4 displacement */
3978 opcode
[1] = opcode
[0] + 0x10;
3979 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3980 where_to_put_displacement
= &opcode
[2];
3983 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3984 extension
= 4; /* 1 opcode + 4 displacement */
3986 where_to_put_displacement
= &opcode
[1];
3989 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3990 extension
= 3; /* 2 opcode + 2 displacement */
3991 opcode
[1] = opcode
[0] + 0x10;
3992 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3993 where_to_put_displacement
= &opcode
[2];
3996 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3997 extension
= 2; /* 1 opcode + 2 displacement */
3999 where_to_put_displacement
= &opcode
[1];
4003 BAD_CASE (fragP
->fr_subtype
);
4006 /* Now put displacement after opcode. */
4007 md_number_to_chars ((char *) where_to_put_displacement
,
4008 (valueT
) (displacement_from_opcode_start
- extension
),
4009 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
4010 fragP
->fr_fix
+= extension
;
4013 /* Size of byte displacement jmp. */
4014 int md_short_jump_size
= 2;
4016 /* Size of dword displacement jmp. */
4017 int md_long_jump_size
= 5;
4019 /* Size of relocation record. */
4020 const int md_reloc_size
= 8;
4023 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4025 addressT from_addr
, to_addr
;
4026 fragS
*frag ATTRIBUTE_UNUSED
;
4027 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4031 offset
= to_addr
- (from_addr
+ 2);
4032 /* Opcode for byte-disp jump. */
4033 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
4034 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
4038 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4040 addressT from_addr
, to_addr
;
4041 fragS
*frag ATTRIBUTE_UNUSED
;
4042 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
4046 offset
= to_addr
- (from_addr
+ 5);
4047 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
4048 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
4051 /* Apply a fixup (fixS) to segment data, once it has been determined
4052 by our caller that we have all the info we need to fix it up.
4054 On the 386, immediates, displacements, and data pointers are all in
4055 the same (little-endian) format, so we don't need to care about which
4059 md_apply_fix3 (fixP
, valp
, seg
)
4060 /* The fix we're to put in. */
4063 /* Pointer to the value of the bits. */
4066 /* Segment fix is from. */
4067 segT seg ATTRIBUTE_UNUSED
;
4069 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4070 valueT value
= *valp
;
4072 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4075 switch (fixP
->fx_r_type
)
4081 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
4084 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
4087 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
4092 /* This is a hack. There should be a better way to handle this.
4093 This covers for the fact that bfd_install_relocation will
4094 subtract the current location (for partial_inplace, PC relative
4095 relocations); see more below. */
4096 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
4097 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
4098 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4102 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4104 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
4107 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4109 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4110 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
4112 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
4115 || (symbol_section_p (fixP
->fx_addsy
)
4116 && fseg
!= absolute_section
))
4117 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
4118 && ! S_IS_WEAK (fixP
->fx_addsy
)
4119 && S_IS_DEFINED (fixP
->fx_addsy
)
4120 && ! S_IS_COMMON (fixP
->fx_addsy
))
4122 /* Yes, we add the values in twice. This is because
4123 bfd_perform_relocation subtracts them out again. I think
4124 bfd_perform_relocation is broken, but I don't dare change
4126 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4130 #if defined (OBJ_COFF) && defined (TE_PE)
4131 /* For some reason, the PE format does not store a section
4132 address offset for a PC relative symbol. */
4133 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
4134 value
+= md_pcrel_from (fixP
);
4138 /* Fix a few things - the dynamic linker expects certain values here,
4139 and we must not dissappoint it. */
4140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4141 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
4143 switch (fixP
->fx_r_type
)
4145 case BFD_RELOC_386_PLT32
:
4146 case BFD_RELOC_X86_64_PLT32
:
4147 /* Make the jump instruction point to the address of the operand. At
4148 runtime we merely add the offset to the actual PLT entry. */
4151 case BFD_RELOC_386_GOTPC
:
4153 /* This is tough to explain. We end up with this one if we have
4154 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4155 * here is to obtain the absolute address of the GOT, and it is strongly
4156 * preferable from a performance point of view to avoid using a runtime
4157 * relocation for this. The actual sequence of instructions often look
4163 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4165 * The call and pop essentially return the absolute address of
4166 * the label .L66 and store it in %ebx. The linker itself will
4167 * ultimately change the first operand of the addl so that %ebx points to
4168 * the GOT, but to keep things simple, the .o file must have this operand
4169 * set so that it generates not the absolute address of .L66, but the
4170 * absolute address of itself. This allows the linker itself simply
4171 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4172 * added in, and the addend of the relocation is stored in the operand
4173 * field for the instruction itself.
4175 * Our job here is to fix the operand so that it would add the correct
4176 * offset so that %ebx would point to itself. The thing that is tricky is
4177 * that .-.L66 will point to the beginning of the instruction, so we need
4178 * to further modify the operand so that it will point to itself.
4179 * There are other cases where you have something like:
4181 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4183 * and here no correction would be required. Internally in the assembler
4184 * we treat operands of this form as not being pcrel since the '.' is
4185 * explicitly mentioned, and I wonder whether it would simplify matters
4186 * to do it this way. Who knows. In earlier versions of the PIC patches,
4187 * the pcrel_adjust field was used to store the correction, but since the
4188 * expression is not pcrel, I felt it would be confusing to do it this
4193 case BFD_RELOC_386_GOT32
:
4194 case BFD_RELOC_X86_64_GOT32
:
4195 value
= 0; /* Fully resolved at runtime. No addend. */
4197 case BFD_RELOC_386_GOTOFF
:
4198 case BFD_RELOC_X86_64_GOTPCREL
:
4201 case BFD_RELOC_VTABLE_INHERIT
:
4202 case BFD_RELOC_VTABLE_ENTRY
:
4209 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4211 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4213 #ifndef BFD_ASSEMBLER
4214 md_number_to_chars (p
, value
, fixP
->fx_size
);
4216 /* Are we finished with this relocation now? */
4217 if (fixP
->fx_addsy
== 0 && fixP
->fx_pcrel
== 0)
4219 else if (use_rela_relocations
)
4221 fixP
->fx_no_overflow
= 1;
4224 md_number_to_chars (p
, value
, fixP
->fx_size
);
4230 #define MAX_LITTLENUMS 6
4232 /* Turn the string pointed to by litP into a floating point constant
4233 of type TYPE, and emit the appropriate bytes. The number of
4234 LITTLENUMS emitted is stored in *SIZEP. An error message is
4235 returned, or NULL on OK. */
4238 md_atof (type
, litP
, sizeP
)
4244 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4245 LITTLENUM_TYPE
*wordP
;
4267 return _("Bad call to md_atof ()");
4269 t
= atof_ieee (input_line_pointer
, type
, words
);
4271 input_line_pointer
= t
;
4273 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
4274 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4275 the bigendian 386. */
4276 for (wordP
= words
+ prec
- 1; prec
--;)
4278 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
4279 litP
+= sizeof (LITTLENUM_TYPE
);
4284 char output_invalid_buf
[8];
4291 sprintf (output_invalid_buf
, "'%c'", c
);
4293 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
4294 return output_invalid_buf
;
4297 /* REG_STRING starts *before* REGISTER_PREFIX. */
4299 static const reg_entry
*
4300 parse_register (reg_string
, end_op
)
4304 char *s
= reg_string
;
4306 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
4309 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4310 if (*s
== REGISTER_PREFIX
)
4313 if (is_space_char (*s
))
4317 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
4319 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
4320 return (const reg_entry
*) NULL
;
4324 /* For naked regs, make sure that we are not dealing with an identifier.
4325 This prevents confusing an identifier like `eax_var' with register
4327 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
4328 return (const reg_entry
*) NULL
;
4332 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
4334 /* Handle floating point regs, allowing spaces in the (i) part. */
4335 if (r
== i386_regtab
/* %st is first entry of table */)
4337 if (is_space_char (*s
))
4342 if (is_space_char (*s
))
4344 if (*s
>= '0' && *s
<= '7')
4346 r
= &i386_float_regtab
[*s
- '0'];
4348 if (is_space_char (*s
))
4356 /* We have "%st(" then garbage. */
4357 return (const reg_entry
*) NULL
;
4364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4365 const char *md_shortopts
= "kVQ:sq";
4367 const char *md_shortopts
= "q";
4369 struct option md_longopts
[] = {
4370 #define OPTION_32 (OPTION_MD_BASE + 0)
4371 {"32", no_argument
, NULL
, OPTION_32
},
4372 #define OPTION_64 (OPTION_MD_BASE + 1)
4373 {"64", no_argument
, NULL
, OPTION_64
},
4374 {NULL
, no_argument
, NULL
, 0}
4376 size_t md_longopts_size
= sizeof (md_longopts
);
4379 md_parse_option (c
, arg
)
4381 char *arg ATTRIBUTE_UNUSED
;
4389 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4390 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4391 should be emitted or not. FIXME: Not implemented. */
4395 /* -V: SVR4 argument to print version ID. */
4397 print_version_id ();
4400 /* -k: Ignore for FreeBSD compatibility. */
4405 /* -s: On i386 Solaris, this tells the native assembler to use
4406 .stab instead of .stab.excl. We always use .stab anyhow. */
4413 const char **list
, **l
;
4415 default_arch
= c
== OPTION_32
? "i386" : "x86_64";
4416 list
= bfd_target_list ();
4417 for (l
= list
; *l
!= NULL
; l
++)
4421 if (strcmp (*l
, "elf32-i386") == 0)
4426 if (strcmp (*l
, "elf64-x86-64") == 0)
4431 as_fatal (_("No compiled in support for %d bit object file format"),
4432 c
== OPTION_32
? 32 : 64);
4445 md_show_usage (stream
)
4448 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4449 fprintf (stream
, _("\
4451 -V print assembler version number\n\
4453 -q quieten some warnings\n\
4456 fprintf (stream
, _("\
4457 -q quieten some warnings\n"));
4461 #ifdef BFD_ASSEMBLER
4462 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4463 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4465 /* Pick the target format to use. */
4468 i386_target_format ()
4470 if (!strcmp (default_arch
, "x86_64"))
4471 set_code_flag (CODE_64BIT
);
4472 else if (!strcmp (default_arch
, "i386"))
4473 set_code_flag (CODE_32BIT
);
4475 as_fatal (_("Unknown architecture"));
4476 switch (OUTPUT_FLAVOR
)
4478 #ifdef OBJ_MAYBE_AOUT
4479 case bfd_target_aout_flavour
:
4480 return AOUT_TARGET_FORMAT
;
4482 #ifdef OBJ_MAYBE_COFF
4483 case bfd_target_coff_flavour
:
4486 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4487 case bfd_target_elf_flavour
:
4489 if (flag_code
== CODE_64BIT
)
4490 use_rela_relocations
= 1;
4491 return flag_code
== CODE_64BIT
? "elf64-x86-64" : "elf32-i386";
4500 #endif /* OBJ_MAYBE_ more than one */
4501 #endif /* BFD_ASSEMBLER */
4504 md_undefined_symbol (name
)
4507 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
4508 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
4509 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
4510 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
4514 if (symbol_find (name
))
4515 as_bad (_("GOT already in symbol table"));
4516 GOT_symbol
= symbol_new (name
, undefined_section
,
4517 (valueT
) 0, &zero_address_frag
);
4524 /* Round up a section size to the appropriate boundary. */
4527 md_section_align (segment
, size
)
4528 segT segment ATTRIBUTE_UNUSED
;
4531 #ifdef BFD_ASSEMBLER
4532 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4533 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
4535 /* For a.out, force the section size to be aligned. If we don't do
4536 this, BFD will align it for us, but it will not write out the
4537 final bytes of the section. This may be a bug in BFD, but it is
4538 easier to fix it here since that is how the other a.out targets
4542 align
= bfd_get_section_alignment (stdoutput
, segment
);
4543 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4551 /* On the i386, PC-relative offsets are relative to the start of the
4552 next instruction. That is, the address of the offset, plus its
4553 size, since the offset is always the last part of the insn. */
4556 md_pcrel_from (fixP
)
4559 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4566 int ignore ATTRIBUTE_UNUSED
;
4570 temp
= get_absolute_expression ();
4571 subseg_set (bss_section
, (subsegT
) temp
);
4572 demand_empty_rest_of_line ();
4577 #ifdef BFD_ASSEMBLER
4580 i386_validate_fix (fixp
)
4583 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4585 /* GOTOFF relocation are nonsense in 64bit mode. */
4586 if (flag_code
== CODE_64BIT
)
4588 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4594 tc_gen_reloc (section
, fixp
)
4595 asection
*section ATTRIBUTE_UNUSED
;
4599 bfd_reloc_code_real_type code
;
4601 switch (fixp
->fx_r_type
)
4603 case BFD_RELOC_X86_64_PLT32
:
4604 case BFD_RELOC_X86_64_GOT32
:
4605 case BFD_RELOC_X86_64_GOTPCREL
:
4606 case BFD_RELOC_386_PLT32
:
4607 case BFD_RELOC_386_GOT32
:
4608 case BFD_RELOC_386_GOTOFF
:
4609 case BFD_RELOC_386_GOTPC
:
4610 case BFD_RELOC_X86_64_32S
:
4612 case BFD_RELOC_VTABLE_ENTRY
:
4613 case BFD_RELOC_VTABLE_INHERIT
:
4614 code
= fixp
->fx_r_type
;
4619 switch (fixp
->fx_size
)
4622 as_bad (_("can not do %d byte pc-relative relocation"),
4624 code
= BFD_RELOC_32_PCREL
;
4626 case 1: code
= BFD_RELOC_8_PCREL
; break;
4627 case 2: code
= BFD_RELOC_16_PCREL
; break;
4628 case 4: code
= BFD_RELOC_32_PCREL
; break;
4633 switch (fixp
->fx_size
)
4636 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4637 code
= BFD_RELOC_32
;
4639 case 1: code
= BFD_RELOC_8
; break;
4640 case 2: code
= BFD_RELOC_16
; break;
4641 case 4: code
= BFD_RELOC_32
; break;
4642 case 8: code
= BFD_RELOC_64
; break;
4648 if (code
== BFD_RELOC_32
4650 && fixp
->fx_addsy
== GOT_symbol
)
4652 /* We don't support GOTPC on 64bit targets. */
4653 if (flag_code
== CODE_64BIT
)
4655 code
= BFD_RELOC_386_GOTPC
;
4658 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4659 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4660 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4662 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4663 if (!use_rela_relocations
)
4665 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4666 vtable entry to be used in the relocation's section offset. */
4667 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4668 rel
->address
= fixp
->fx_offset
;
4671 rel
->addend
= fixp
->fx_addnumber
;
4675 /* Use the rela in 64bit mode. */
4678 rel
->addend
= fixp
->fx_offset
;
4680 /* Ohhh, this is ugly. The problem is that if this is a local global
4681 symbol, the relocation will entirely be performed at link time, not
4682 at assembly time. bfd_perform_reloc doesn't know about this sort
4683 of thing, and as a result we need to fake it out here. */
4684 if ((S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
))
4685 && !S_IS_COMMON(fixp
->fx_addsy
))
4686 rel
->addend
-= symbol_get_bfdsym (fixp
->fx_addsy
)->value
;
4689 rel
->addend
-= fixp
->fx_size
;
4693 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4694 if (rel
->howto
== NULL
)
4696 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4697 _("cannot represent relocation type %s"),
4698 bfd_get_reloc_code_name (code
));
4699 /* Set howto to a garbage value so that we can keep going. */
4700 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4701 assert (rel
->howto
!= NULL
);
4707 #else /* ! BFD_ASSEMBLER */
4709 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4711 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4714 relax_addressT segment_address_in_file
;
4716 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4717 Out: GNU LD relocation length code: 0, 1, or 2. */
4719 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4722 know (fixP
->fx_addsy
!= NULL
);
4724 md_number_to_chars (where
,
4725 (valueT
) (fixP
->fx_frag
->fr_address
4726 + fixP
->fx_where
- segment_address_in_file
),
4729 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4730 ? S_GET_TYPE (fixP
->fx_addsy
)
4731 : fixP
->fx_addsy
->sy_number
);
4733 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4734 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4735 where
[4] = r_symbolnum
& 0x0ff;
4736 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4737 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4738 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4741 #endif /* OBJ_AOUT or OBJ_BOUT. */
4743 #if defined (I386COFF)
4746 tc_coff_fix2rtype (fixP
)
4749 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4752 return (fixP
->fx_pcrel
?
4753 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4754 fixP
->fx_size
== 2 ? R_PCRWORD
:
4756 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4757 fixP
->fx_size
== 2 ? R_RELWORD
:
4762 tc_coff_sizemachdep (frag
)
4766 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4771 #endif /* I386COFF */
4773 #endif /* ! BFD_ASSEMBLER */
4775 /* Parse operands using Intel syntax. This implements a recursive descent
4776 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4779 FIXME: We do not recognize the full operand grammar defined in the MASM
4780 documentation. In particular, all the structure/union and
4781 high-level macro operands are missing.
4783 Uppercase words are terminals, lower case words are non-terminals.
4784 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4785 bars '|' denote choices. Most grammar productions are implemented in
4786 functions called 'intel_<production>'.
4788 Initial production is 'expr'.
4794 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4796 constant digits [[ radixOverride ]]
4798 dataType BYTE | WORD | DWORD | QWORD | XWORD
4831 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4832 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4834 hexdigit a | b | c | d | e | f
4835 | A | B | C | D | E | F
4845 register specialRegister
4849 segmentRegister CS | DS | ES | FS | GS | SS
4851 specialRegister CR0 | CR2 | CR3
4852 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4853 | TR3 | TR4 | TR5 | TR6 | TR7
4855 We simplify the grammar in obvious places (e.g., register parsing is
4856 done by calling parse_register) and eliminate immediate left recursion
4857 to implement a recursive-descent parser.
4897 /* Parsing structure for the intel syntax parser. Used to implement the
4898 semantic actions for the operand grammar. */
4899 struct intel_parser_s
4901 char *op_string
; /* The string being parsed. */
4902 int got_a_float
; /* Whether the operand is a float. */
4903 int op_modifier
; /* Operand modifier. */
4904 int is_mem
; /* 1 if operand is memory reference. */
4905 const reg_entry
*reg
; /* Last register reference found. */
4906 char *disp
; /* Displacement string being built. */
4909 static struct intel_parser_s intel_parser
;
4911 /* Token structure for parsing intel syntax. */
4914 int code
; /* Token code. */
4915 const reg_entry
*reg
; /* Register entry for register tokens. */
4916 char *str
; /* String representation. */
4919 static struct intel_token cur_token
, prev_token
;
4922 /* Token codes for the intel parser. Since T_SHORT is already used
4923 by COFF, undefine it first to prevent a warning. */
4938 /* Prototypes for intel parser functions. */
4939 static int intel_match_token
PARAMS ((int code
));
4940 static void intel_get_token
PARAMS ((void));
4941 static void intel_putback_token
PARAMS ((void));
4942 static int intel_expr
PARAMS ((void));
4943 static int intel_e05
PARAMS ((void));
4944 static int intel_e05_1
PARAMS ((void));
4945 static int intel_e06
PARAMS ((void));
4946 static int intel_e06_1
PARAMS ((void));
4947 static int intel_e09
PARAMS ((void));
4948 static int intel_e09_1
PARAMS ((void));
4949 static int intel_e10
PARAMS ((void));
4950 static int intel_e10_1
PARAMS ((void));
4951 static int intel_e11
PARAMS ((void));
4954 i386_intel_operand (operand_string
, got_a_float
)
4955 char *operand_string
;
4961 /* Initialize token holders. */
4962 cur_token
.code
= prev_token
.code
= T_NIL
;
4963 cur_token
.reg
= prev_token
.reg
= NULL
;
4964 cur_token
.str
= prev_token
.str
= NULL
;
4966 /* Initialize parser structure. */
4967 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4970 strcpy (intel_parser
.op_string
, operand_string
);
4971 intel_parser
.got_a_float
= got_a_float
;
4972 intel_parser
.op_modifier
= -1;
4973 intel_parser
.is_mem
= 0;
4974 intel_parser
.reg
= NULL
;
4975 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4976 if (intel_parser
.disp
== NULL
)
4978 intel_parser
.disp
[0] = '\0';
4980 /* Read the first token and start the parser. */
4982 ret
= intel_expr ();
4986 /* If we found a memory reference, hand it over to i386_displacement
4987 to fill in the rest of the operand fields. */
4988 if (intel_parser
.is_mem
)
4990 if ((i
.mem_operands
== 1
4991 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4992 || i
.mem_operands
== 2)
4994 as_bad (_("too many memory references for '%s'"),
4995 current_templates
->start
->name
);
5000 char *s
= intel_parser
.disp
;
5003 /* Add the displacement expression. */
5005 ret
= i386_displacement (s
, s
+ strlen (s
))
5006 && i386_index_check (s
);
5010 /* Constant and OFFSET expressions are handled by i386_immediate. */
5011 else if (intel_parser
.op_modifier
== OFFSET_FLAT
5012 || intel_parser
.reg
== NULL
)
5013 ret
= i386_immediate (intel_parser
.disp
);
5017 free (intel_parser
.disp
);
5027 /* expr SHORT e05 */
5028 if (cur_token
.code
== T_SHORT
)
5030 intel_parser
.op_modifier
= SHORT
;
5031 intel_match_token (T_SHORT
);
5033 return (intel_e05 ());
5038 return intel_e05 ();
5048 return (intel_e06 () && intel_e05_1 ());
5054 /* e05' addOp e06 e05' */
5055 if (cur_token
.code
== '+' || cur_token
.code
== '-')
5057 strcat (intel_parser
.disp
, cur_token
.str
);
5058 intel_match_token (cur_token
.code
);
5060 return (intel_e06 () && intel_e05_1 ());
5075 return (intel_e09 () && intel_e06_1 ());
5081 /* e06' mulOp e09 e06' */
5082 if (cur_token
.code
== '*' || cur_token
.code
== '/')
5084 strcat (intel_parser
.disp
, cur_token
.str
);
5085 intel_match_token (cur_token
.code
);
5087 return (intel_e09 () && intel_e06_1 ());
5095 /* e09 OFFSET e10 e09'
5104 /* e09 OFFSET e10 e09' */
5105 if (cur_token
.code
== T_OFFSET
)
5107 intel_parser
.is_mem
= 0;
5108 intel_parser
.op_modifier
= OFFSET_FLAT
;
5109 intel_match_token (T_OFFSET
);
5111 return (intel_e10 () && intel_e09_1 ());
5116 return (intel_e10 () && intel_e09_1 ());
5122 /* e09' PTR e10 e09' */
5123 if (cur_token
.code
== T_PTR
)
5125 if (prev_token
.code
== T_BYTE
)
5126 i
.suffix
= BYTE_MNEM_SUFFIX
;
5128 else if (prev_token
.code
== T_WORD
)
5130 if (intel_parser
.got_a_float
== 2) /* "fi..." */
5131 i
.suffix
= SHORT_MNEM_SUFFIX
;
5133 i
.suffix
= WORD_MNEM_SUFFIX
;
5136 else if (prev_token
.code
== T_DWORD
)
5138 if (intel_parser
.got_a_float
== 1) /* "f..." */
5139 i
.suffix
= SHORT_MNEM_SUFFIX
;
5141 i
.suffix
= LONG_MNEM_SUFFIX
;
5144 else if (prev_token
.code
== T_QWORD
)
5146 if (intel_parser
.got_a_float
== 1) /* "f..." */
5147 i
.suffix
= LONG_MNEM_SUFFIX
;
5149 i
.suffix
= QWORD_MNEM_SUFFIX
;
5152 else if (prev_token
.code
== T_XWORD
)
5153 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
5157 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
5161 intel_match_token (T_PTR
);
5163 return (intel_e10 () && intel_e09_1 ());
5166 /* e09 : e10 e09' */
5167 else if (cur_token
.code
== ':')
5169 /* Mark as a memory operand only if it's not already known to be an
5170 offset expression. */
5171 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5172 intel_parser
.is_mem
= 1;
5174 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5189 return (intel_e11 () && intel_e10_1 ());
5195 /* e10' [ expr ] e10' */
5196 if (cur_token
.code
== '[')
5198 intel_match_token ('[');
5200 /* Mark as a memory operand only if it's not already known to be an
5201 offset expression. If it's an offset expression, we need to keep
5203 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5204 intel_parser
.is_mem
= 1;
5206 strcat (intel_parser
.disp
, "[");
5208 /* Add a '+' to the displacement string if necessary. */
5209 if (*intel_parser
.disp
!= '\0'
5210 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5211 strcat (intel_parser
.disp
, "+");
5213 if (intel_expr () && intel_match_token (']'))
5215 /* Preserve brackets when the operand is an offset expression. */
5216 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5217 strcat (intel_parser
.disp
, "]");
5219 return intel_e10_1 ();
5246 if (cur_token
.code
== '(')
5248 intel_match_token ('(');
5249 strcat (intel_parser
.disp
, "(");
5251 if (intel_expr () && intel_match_token (')'))
5253 strcat (intel_parser
.disp
, ")");
5261 else if (cur_token
.code
== '[')
5263 intel_match_token ('[');
5265 /* Mark as a memory operand only if it's not already known to be an
5266 offset expression. If it's an offset expression, we need to keep
5268 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5269 intel_parser
.is_mem
= 1;
5271 strcat (intel_parser
.disp
, "[");
5273 /* Operands for jump/call inside brackets denote absolute addresses. */
5274 if (current_templates
->start
->opcode_modifier
& Jump
5275 || current_templates
->start
->opcode_modifier
& JumpDword
5276 || current_templates
->start
->opcode_modifier
& JumpByte
5277 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
5278 i
.types
[this_operand
] |= JumpAbsolute
;
5280 /* Add a '+' to the displacement string if necessary. */
5281 if (*intel_parser
.disp
!= '\0'
5282 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
5283 strcat (intel_parser
.disp
, "+");
5285 if (intel_expr () && intel_match_token (']'))
5287 /* Preserve brackets when the operand is an offset expression. */
5288 if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5289 strcat (intel_parser
.disp
, "]");
5302 else if (cur_token
.code
== T_BYTE
5303 || cur_token
.code
== T_WORD
5304 || cur_token
.code
== T_DWORD
5305 || cur_token
.code
== T_QWORD
5306 || cur_token
.code
== T_XWORD
)
5308 intel_match_token (cur_token
.code
);
5315 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
5317 strcat (intel_parser
.disp
, cur_token
.str
);
5318 intel_match_token (cur_token
.code
);
5320 /* Mark as a memory operand only if it's not already known to be an
5321 offset expression. */
5322 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5323 intel_parser
.is_mem
= 1;
5329 else if (cur_token
.code
== T_REG
)
5331 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
5333 intel_match_token (T_REG
);
5335 /* Check for segment change. */
5336 if (cur_token
.code
== ':')
5338 if (reg
->reg_type
& (SReg2
| SReg3
))
5340 switch (reg
->reg_num
)
5343 i
.seg
[i
.mem_operands
] = &es
;
5346 i
.seg
[i
.mem_operands
] = &cs
;
5349 i
.seg
[i
.mem_operands
] = &ss
;
5352 i
.seg
[i
.mem_operands
] = &ds
;
5355 i
.seg
[i
.mem_operands
] = &fs
;
5358 i
.seg
[i
.mem_operands
] = &gs
;
5364 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
5369 /* Not a segment register. Check for register scaling. */
5370 else if (cur_token
.code
== '*')
5372 if (!intel_parser
.is_mem
)
5374 as_bad (_("Register scaling only allowed in memory operands."));
5378 /* What follows must be a valid scale. */
5379 if (intel_match_token ('*')
5380 && strchr ("01248", *cur_token
.str
))
5383 i
.types
[this_operand
] |= BaseIndex
;
5385 /* Set the scale after setting the register (otherwise,
5386 i386_scale will complain) */
5387 i386_scale (cur_token
.str
);
5388 intel_match_token (T_CONST
);
5392 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5398 /* No scaling. If this is a memory operand, the register is either a
5399 base register (first occurrence) or an index register (second
5401 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
5403 if (i
.base_reg
&& i
.index_reg
)
5405 as_bad (_("Too many register references in memory operand.\n"));
5409 if (i
.base_reg
== NULL
)
5414 i
.types
[this_operand
] |= BaseIndex
;
5417 /* Offset modifier. Add the register to the displacement string to be
5418 parsed as an immediate expression after we're done. */
5419 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
5420 strcat (intel_parser
.disp
, reg
->reg_name
);
5422 /* It's neither base nor index nor offset. */
5425 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
5426 i
.op
[this_operand
].regs
= reg
;
5430 /* Since registers are not part of the displacement string (except
5431 when we're parsing offset operands), we may need to remove any
5432 preceding '+' from the displacement string. */
5433 if (*intel_parser
.disp
!= '\0'
5434 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
5436 char *s
= intel_parser
.disp
;
5437 s
+= strlen (s
) - 1;
5446 else if (cur_token
.code
== T_ID
)
5448 /* Add the identifier to the displacement string. */
5449 strcat (intel_parser
.disp
, cur_token
.str
);
5450 intel_match_token (T_ID
);
5452 /* The identifier represents a memory reference only if it's not
5453 preceded by an offset modifier. */
5454 if (intel_parser
.op_modifier
!= OFFSET_FLAT
)
5455 intel_parser
.is_mem
= 1;
5461 else if (cur_token
.code
== T_CONST
5462 || cur_token
.code
== '-'
5463 || cur_token
.code
== '+')
5467 /* Allow constants that start with `+' or `-'. */
5468 if (cur_token
.code
== '-' || cur_token
.code
== '+')
5470 strcat (intel_parser
.disp
, cur_token
.str
);
5471 intel_match_token (cur_token
.code
);
5472 if (cur_token
.code
!= T_CONST
)
5474 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5480 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
5481 if (save_str
== NULL
)
5483 strcpy (save_str
, cur_token
.str
);
5485 /* Get the next token to check for register scaling. */
5486 intel_match_token (cur_token
.code
);
5488 /* Check if this constant is a scaling factor for an index register. */
5489 if (cur_token
.code
== '*')
5491 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
5493 if (!intel_parser
.is_mem
)
5495 as_bad (_("Register scaling only allowed in memory operands."));
5499 /* The constant is followed by `* reg', so it must be
5501 if (strchr ("01248", *save_str
))
5503 i
.index_reg
= cur_token
.reg
;
5504 i
.types
[this_operand
] |= BaseIndex
;
5506 /* Set the scale after setting the register (otherwise,
5507 i386_scale will complain) */
5508 i386_scale (save_str
);
5509 intel_match_token (T_REG
);
5511 /* Since registers are not part of the displacement
5512 string, we may need to remove any preceding '+' from
5513 the displacement string. */
5514 if (*intel_parser
.disp
!= '\0')
5516 char *s
= intel_parser
.disp
;
5517 s
+= strlen (s
) - 1;
5530 /* The constant was not used for register scaling. Since we have
5531 already consumed the token following `*' we now need to put it
5532 back in the stream. */
5534 intel_putback_token ();
5537 /* Add the constant to the displacement string. */
5538 strcat (intel_parser
.disp
, save_str
);
5544 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
5548 /* Match the given token against cur_token. If they match, read the next
5549 token from the operand string. */
5551 intel_match_token (code
)
5554 if (cur_token
.code
== code
)
5561 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
5566 /* Read a new token from intel_parser.op_string and store it in cur_token. */
5571 const reg_entry
*reg
;
5572 struct intel_token new_token
;
5574 new_token
.code
= T_NIL
;
5575 new_token
.reg
= NULL
;
5576 new_token
.str
= NULL
;
5578 /* Free the memory allocated to the previous token and move
5579 cur_token to prev_token. */
5581 free (prev_token
.str
);
5583 prev_token
= cur_token
;
5585 /* Skip whitespace. */
5586 while (is_space_char (*intel_parser
.op_string
))
5587 intel_parser
.op_string
++;
5589 /* Return an empty token if we find nothing else on the line. */
5590 if (*intel_parser
.op_string
== '\0')
5592 cur_token
= new_token
;
5596 /* The new token cannot be larger than the remainder of the operand
5598 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
5599 if (new_token
.str
== NULL
)
5601 new_token
.str
[0] = '\0';
5603 if (strchr ("0123456789", *intel_parser
.op_string
))
5605 char *p
= new_token
.str
;
5606 char *q
= intel_parser
.op_string
;
5607 new_token
.code
= T_CONST
;
5609 /* Allow any kind of identifier char to encompass floating point and
5610 hexadecimal numbers. */
5611 while (is_identifier_char (*q
))
5615 /* Recognize special symbol names [0-9][bf]. */
5616 if (strlen (intel_parser
.op_string
) == 2
5617 && (intel_parser
.op_string
[1] == 'b'
5618 || intel_parser
.op_string
[1] == 'f'))
5619 new_token
.code
= T_ID
;
5622 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5624 new_token
.code
= *intel_parser
.op_string
;
5625 new_token
.str
[0] = *intel_parser
.op_string
;
5626 new_token
.str
[1] = '\0';
5629 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5630 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5632 new_token
.code
= T_REG
;
5633 new_token
.reg
= reg
;
5635 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5637 new_token
.str
[0] = REGISTER_PREFIX
;
5638 new_token
.str
[1] = '\0';
5641 strcat (new_token
.str
, reg
->reg_name
);
5644 else if (is_identifier_char (*intel_parser
.op_string
))
5646 char *p
= new_token
.str
;
5647 char *q
= intel_parser
.op_string
;
5649 /* A '.' or '$' followed by an identifier char is an identifier.
5650 Otherwise, it's operator '.' followed by an expression. */
5651 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5653 new_token
.code
= *q
;
5654 new_token
.str
[0] = *q
;
5655 new_token
.str
[1] = '\0';
5659 while (is_identifier_char (*q
) || *q
== '@')
5663 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5664 new_token
.code
= T_BYTE
;
5666 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5667 new_token
.code
= T_WORD
;
5669 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5670 new_token
.code
= T_DWORD
;
5672 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5673 new_token
.code
= T_QWORD
;
5675 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5676 new_token
.code
= T_XWORD
;
5678 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5679 new_token
.code
= T_PTR
;
5681 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5682 new_token
.code
= T_SHORT
;
5684 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5686 new_token
.code
= T_OFFSET
;
5688 /* ??? This is not mentioned in the MASM grammar but gcc
5689 makes use of it with -mintel-syntax. OFFSET may be
5690 followed by FLAT: */
5691 if (strncasecmp (q
, " FLAT:", 6) == 0)
5692 strcat (new_token
.str
, " FLAT:");
5695 /* ??? This is not mentioned in the MASM grammar. */
5696 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5697 new_token
.code
= T_OFFSET
;
5700 new_token
.code
= T_ID
;
5705 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5707 intel_parser
.op_string
+= strlen (new_token
.str
);
5708 cur_token
= new_token
;
5711 /* Put cur_token back into the token stream and make cur_token point to
5714 intel_putback_token ()
5716 intel_parser
.op_string
-= strlen (cur_token
.str
);
5717 free (cur_token
.str
);
5718 cur_token
= prev_token
;
5720 /* Forget prev_token. */
5721 prev_token
.code
= T_NIL
;
5722 prev_token
.reg
= NULL
;
5723 prev_token
.str
= NULL
;