1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Intel 80386 machine specific gas.
23 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
24 Bugs & suggestions are completely welcome. This is free software.
25 Please help us make it better. */
31 #include "dwarf2dbg.h"
32 #include "opcode/i386.h"
34 #ifndef REGISTER_WARNINGS
35 #define REGISTER_WARNINGS 1
38 #ifndef INFER_ADDR_PREFIX
39 #define INFER_ADDR_PREFIX 1
42 #ifndef SCALE1_WHEN_NO_INDEX
43 /* Specifying a scale factor besides 1 when there is no index is
44 futile. eg. `mov (%ebx,2),%al' does exactly the same as
45 `mov (%ebx),%al'. To slavishly follow what the programmer
46 specified, set SCALE1_WHEN_NO_INDEX to 0. */
47 #define SCALE1_WHEN_NO_INDEX 1
53 static unsigned int mode_from_disp_size
PARAMS ((unsigned int));
54 static int fits_in_signed_byte
PARAMS ((offsetT
));
55 static int fits_in_unsigned_byte
PARAMS ((offsetT
));
56 static int fits_in_unsigned_word
PARAMS ((offsetT
));
57 static int fits_in_signed_word
PARAMS ((offsetT
));
58 static int smallest_imm_type
PARAMS ((offsetT
));
59 static offsetT offset_in_range
PARAMS ((offsetT
, int));
60 static int add_prefix
PARAMS ((unsigned int));
61 static void set_16bit_code_flag
PARAMS ((int));
62 static void set_16bit_gcc_code_flag
PARAMS ((int));
63 static void set_intel_syntax
PARAMS ((int));
64 static void set_cpu_arch
PARAMS ((int));
67 static bfd_reloc_code_real_type reloc
68 PARAMS ((int, int, bfd_reloc_code_real_type
));
71 /* 'md_assemble ()' gathers together information and puts it into a
78 const reg_entry
*regs
;
83 /* TM holds the template for the insn were currently assembling. */
86 /* SUFFIX holds the instruction mnemonic suffix if given.
87 (e.g. 'l' for 'movl') */
90 /* OPERANDS gives the number of given operands. */
91 unsigned int operands
;
93 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
94 of given register, displacement, memory operands and immediate
96 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
98 /* TYPES [i] is the type (see above #defines) which tells us how to
99 use OP[i] for the corresponding operand. */
100 unsigned int types
[MAX_OPERANDS
];
102 /* Displacement expression, immediate expression, or register for each
104 union i386_op op
[MAX_OPERANDS
];
106 /* Relocation type for operand */
108 enum bfd_reloc_code_real disp_reloc
[MAX_OPERANDS
];
110 int disp_reloc
[MAX_OPERANDS
];
113 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
114 the base index byte below. */
115 const reg_entry
*base_reg
;
116 const reg_entry
*index_reg
;
117 unsigned int log2_scale_factor
;
119 /* SEG gives the seg_entries of this insn. They are zero unless
120 explicit segment overrides are given. */
121 const seg_entry
*seg
[2];
123 /* PREFIX holds all the given prefix opcodes (usually null).
124 PREFIXES is the number of prefix opcodes. */
125 unsigned int prefixes
;
126 unsigned char prefix
[MAX_PREFIXES
];
128 /* RM and SIB are the modrm byte and the sib byte where the
129 addressing modes of this insn are encoded. */
135 typedef struct _i386_insn i386_insn
;
137 /* List of chars besides those in app.c:symbol_chars that can start an
138 operand. Used to prevent the scrubber eating vital white-space. */
140 const char extra_symbol_chars
[] = "*%-(@";
142 const char extra_symbol_chars
[] = "*%-(";
145 /* This array holds the chars that always start a comment. If the
146 pre-processor is disabled, these aren't very useful. */
147 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
148 /* Putting '/' here makes it impossible to use the divide operator.
149 However, we need it for compatibility with SVR4 systems. */
150 const char comment_chars
[] = "#/";
151 #define PREFIX_SEPARATOR '\\'
153 const char comment_chars
[] = "#";
154 #define PREFIX_SEPARATOR '/'
157 /* This array holds the chars that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output.
160 Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output.
163 Also note that comments started like this one will always work if
164 '/' isn't otherwise defined. */
165 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
166 const char line_comment_chars
[] = "";
168 const char line_comment_chars
[] = "/";
171 const char line_separator_chars
[] = ";";
173 /* Chars that can be used to separate mant from exp in floating point
175 const char EXP_CHARS
[] = "eE";
177 /* Chars that mean this number is a floating point constant
180 const char FLT_CHARS
[] = "fFdDxX";
182 /* Tables for lexical analysis. */
183 static char mnemonic_chars
[256];
184 static char register_chars
[256];
185 static char operand_chars
[256];
186 static char identifier_chars
[256];
187 static char digit_chars
[256];
189 /* Lexical macros. */
190 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
191 #define is_operand_char(x) (operand_chars[(unsigned char) x])
192 #define is_register_char(x) (register_chars[(unsigned char) x])
193 #define is_space_char(x) ((x) == ' ')
194 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
195 #define is_digit_char(x) (digit_chars[(unsigned char) x])
197 /* All non-digit non-letter charcters that may occur in an operand. */
198 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
200 /* md_assemble() always leaves the strings it's passed unaltered. To
201 effect this we maintain a stack of saved characters that we've smashed
202 with '\0's (indicating end of strings for various sub-fields of the
203 assembler instruction). */
204 static char save_stack
[32];
205 static char *save_stack_p
;
206 #define END_STRING_AND_SAVE(s) \
207 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
208 #define RESTORE_END_STRING(s) \
209 do { *(s) = *--save_stack_p; } while (0)
211 /* The instruction we're assembling. */
214 /* Possible templates for current insn. */
215 static const templates
*current_templates
;
217 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
218 static expressionS disp_expressions
[2], im_expressions
[2];
220 /* Current operand we are working on. */
221 static int this_operand
;
223 /* 1 if we're writing 16-bit code,
225 static int flag_16bit_code
;
227 /* 1 for intel syntax,
229 static int intel_syntax
= 0;
231 /* 1 if register prefix % not required. */
232 static int allow_naked_reg
= 0;
234 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
235 leave, push, and pop instructions so that gcc has the same stack
236 frame as in 32 bit mode. */
237 static char stackop_size
= '\0';
239 /* Non-zero to quieten some warnings. */
240 static int quiet_warnings
= 0;
243 static const char *cpu_arch_name
= NULL
;
245 /* CPU feature flags. */
246 static unsigned int cpu_arch_flags
= 0;
248 /* Interface to relax_segment.
249 There are 2 relax states for 386 jump insns: one for conditional &
250 one for unconditional jumps. This is because these two types of
251 jumps add different sizes to frags when we're figuring out what
252 sort of jump to choose to reach a given label. */
256 #define UNCOND_JUMP 2
260 #define SMALL16 (SMALL|CODE16)
262 #define BIG16 (BIG|CODE16)
266 #define INLINE __inline__
272 #define ENCODE_RELAX_STATE(type,size) \
273 ((relax_substateT) ((type<<2) | (size)))
274 #define SIZE_FROM_RELAX_STATE(s) \
275 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
277 /* This table is used by relax_frag to promote short jumps to long
278 ones where necessary. SMALL (short) jumps may be promoted to BIG
279 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
280 don't allow a short jump in a 32 bit code segment to be promoted to
281 a 16 bit offset jump because it's slower (requires data size
282 prefix), and doesn't work, unless the destination is in the bottom
283 64k of the code segment (The top 16 bits of eip are zeroed). */
285 const relax_typeS md_relax_table
[] =
288 1) most positive reach of this state,
289 2) most negative reach of this state,
290 3) how many bytes this mode will add to the size of the current frag
291 4) which index into the table to try if we can't fit into this one. */
297 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
298 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
299 /* dword conditionals adds 4 bytes to frag:
300 1 extra opcode byte, 3 extra displacement bytes. */
302 /* word conditionals add 2 bytes to frag:
303 1 extra opcode byte, 1 extra displacement byte. */
306 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
307 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
308 /* dword jmp adds 3 bytes to frag:
309 0 extra opcode bytes, 3 extra displacement bytes. */
311 /* word jmp adds 1 byte to frag:
312 0 extra opcode bytes, 1 extra displacement byte. */
317 static const arch_entry cpu_arch
[] = {
319 {"i186", Cpu086
|Cpu186
},
320 {"i286", Cpu086
|Cpu186
|Cpu286
},
321 {"i386", Cpu086
|Cpu186
|Cpu286
|Cpu386
},
322 {"i486", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
},
323 {"i586", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
324 {"i686", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
325 {"pentium", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
},
326 {"pentiumpro",Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|CpuSSE
},
327 {"k6", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|CpuMMX
|Cpu3dnow
},
328 {"athlon", Cpu086
|Cpu186
|Cpu286
|Cpu386
|Cpu486
|Cpu586
|Cpu686
|CpuMMX
|Cpu3dnow
},
333 i386_align_code (fragP
, count
)
337 /* Various efficient no-op patterns for aligning code labels.
338 Note: Don't try to assemble the instructions in the comments.
339 0L and 0w are not legal. */
340 static const char f32_1
[] =
342 static const char f32_2
[] =
343 {0x89,0xf6}; /* movl %esi,%esi */
344 static const char f32_3
[] =
345 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
346 static const char f32_4
[] =
347 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
348 static const char f32_5
[] =
350 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
351 static const char f32_6
[] =
352 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
353 static const char f32_7
[] =
354 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
355 static const char f32_8
[] =
357 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
358 static const char f32_9
[] =
359 {0x89,0xf6, /* movl %esi,%esi */
360 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
361 static const char f32_10
[] =
362 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
363 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
364 static const char f32_11
[] =
365 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
366 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
367 static const char f32_12
[] =
368 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
369 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
370 static const char f32_13
[] =
371 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
372 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
373 static const char f32_14
[] =
374 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
375 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
376 static const char f32_15
[] =
377 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
378 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
379 static const char f16_3
[] =
380 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
381 static const char f16_4
[] =
382 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
383 static const char f16_5
[] =
385 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
386 static const char f16_6
[] =
387 {0x89,0xf6, /* mov %si,%si */
388 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
389 static const char f16_7
[] =
390 {0x8d,0x74,0x00, /* lea 0(%si),%si */
391 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
392 static const char f16_8
[] =
393 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
394 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
395 static const char *const f32_patt
[] = {
396 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
397 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
, f32_15
399 static const char *const f16_patt
[] = {
400 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
,
401 f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
, f32_15
404 if (count
> 0 && count
<= 15)
408 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
409 f16_patt
[count
- 1], count
);
411 /* Adjust jump offset. */
412 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
415 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
416 f32_patt
[count
- 1], count
);
417 fragP
->fr_var
= count
;
421 static char *output_invalid
PARAMS ((int c
));
422 static int i386_operand
PARAMS ((char *operand_string
));
423 static int i386_intel_operand
PARAMS ((char *operand_string
, int got_a_float
));
424 static const reg_entry
*parse_register
PARAMS ((char *reg_string
,
428 static void s_bss
PARAMS ((int));
431 symbolS
*GOT_symbol
; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
433 static INLINE
unsigned int
434 mode_from_disp_size (t
)
437 return (t
& Disp8
) ? 1 : (t
& (Disp16
| Disp32
)) ? 2 : 0;
441 fits_in_signed_byte (num
)
444 return (num
>= -128) && (num
<= 127);
448 fits_in_unsigned_byte (num
)
451 return (num
& 0xff) == num
;
455 fits_in_unsigned_word (num
)
458 return (num
& 0xffff) == num
;
462 fits_in_signed_word (num
)
465 return (-32768 <= num
) && (num
<= 32767);
469 smallest_imm_type (num
)
472 if (cpu_arch_flags
!= 0
473 && cpu_arch_flags
!= (Cpu086
| Cpu186
| Cpu286
| Cpu386
| Cpu486
))
475 /* This code is disabled on the 486 because all the Imm1 forms
476 in the opcode table are slower on the i486. They're the
477 versions with the implicitly specified single-position
478 displacement, which has another syntax if you really want to
481 return Imm1
| Imm8
| Imm8S
| Imm16
| Imm32
;
483 return (fits_in_signed_byte (num
)
484 ? (Imm8S
| Imm8
| Imm16
| Imm32
)
485 : fits_in_unsigned_byte (num
)
486 ? (Imm8
| Imm16
| Imm32
)
487 : (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
493 offset_in_range (val
, size
)
501 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
502 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
503 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
507 /* If BFD64, sign extend val. */
508 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
509 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
511 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
513 char buf1
[40], buf2
[40];
515 sprint_value (buf1
, val
);
516 sprint_value (buf2
, val
& mask
);
517 as_warn (_("%s shortened to %s"), buf1
, buf2
);
522 /* Returns 0 if attempting to add a prefix where one from the same
523 class already exists, 1 if non rep/repne added, 2 if rep/repne
537 case CS_PREFIX_OPCODE
:
538 case DS_PREFIX_OPCODE
:
539 case ES_PREFIX_OPCODE
:
540 case FS_PREFIX_OPCODE
:
541 case GS_PREFIX_OPCODE
:
542 case SS_PREFIX_OPCODE
:
546 case REPNE_PREFIX_OPCODE
:
547 case REPE_PREFIX_OPCODE
:
550 case LOCK_PREFIX_OPCODE
:
558 case ADDR_PREFIX_OPCODE
:
562 case DATA_PREFIX_OPCODE
:
569 as_bad (_("same type of prefix used twice"));
574 i
.prefix
[q
] = prefix
;
579 set_16bit_code_flag (new_16bit_code_flag
)
580 int new_16bit_code_flag
;
582 flag_16bit_code
= new_16bit_code_flag
;
587 set_16bit_gcc_code_flag (new_16bit_code_flag
)
588 int new_16bit_code_flag
;
590 flag_16bit_code
= new_16bit_code_flag
;
591 stackop_size
= new_16bit_code_flag
? 'l' : '\0';
595 set_intel_syntax (syntax_flag
)
598 /* Find out if register prefixing is specified. */
599 int ask_naked_reg
= 0;
602 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
604 char *string
= input_line_pointer
;
605 int e
= get_symbol_end ();
607 if (strcmp (string
, "prefix") == 0)
609 else if (strcmp (string
, "noprefix") == 0)
612 as_bad (_("bad argument to syntax directive."));
613 *input_line_pointer
= e
;
615 demand_empty_rest_of_line ();
617 intel_syntax
= syntax_flag
;
619 if (ask_naked_reg
== 0)
622 allow_naked_reg
= (intel_syntax
623 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
625 /* Conservative default. */
630 allow_naked_reg
= (ask_naked_reg
< 0);
635 int dummy ATTRIBUTE_UNUSED
;
639 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
641 char *string
= input_line_pointer
;
642 int e
= get_symbol_end ();
645 for (i
= 0; cpu_arch
[i
].name
; i
++)
647 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
649 cpu_arch_name
= cpu_arch
[i
].name
;
650 cpu_arch_flags
= cpu_arch
[i
].flags
;
654 if (!cpu_arch
[i
].name
)
655 as_bad (_("no such architecture: `%s'"), string
);
657 *input_line_pointer
= e
;
660 as_bad (_("missing cpu architecture"));
662 demand_empty_rest_of_line ();
665 const pseudo_typeS md_pseudo_table
[] =
667 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
668 {"align", s_align_bytes
, 0},
670 {"align", s_align_ptwo
, 0},
672 {"arch", set_cpu_arch
, 0},
676 {"ffloat", float_cons
, 'f'},
677 {"dfloat", float_cons
, 'd'},
678 {"tfloat", float_cons
, 'x'},
680 {"noopt", s_ignore
, 0},
681 {"optim", s_ignore
, 0},
682 {"code16gcc", set_16bit_gcc_code_flag
, 1},
683 {"code16", set_16bit_code_flag
, 1},
684 {"code32", set_16bit_code_flag
, 0},
685 {"intel_syntax", set_intel_syntax
, 1},
686 {"att_syntax", set_intel_syntax
, 0},
687 {"file", dwarf2_directive_file
, 0},
688 {"loc", dwarf2_directive_loc
, 0},
692 /* For interface with expression (). */
693 extern char *input_line_pointer
;
695 /* Hash table for instruction mnemonic lookup. */
696 static struct hash_control
*op_hash
;
698 /* Hash table for register lookup. */
699 static struct hash_control
*reg_hash
;
704 const char *hash_err
;
706 /* Initialize op_hash hash table. */
707 op_hash
= hash_new ();
710 register const template *optab
;
711 register templates
*core_optab
;
713 /* Setup for loop. */
715 core_optab
= (templates
*) xmalloc (sizeof (templates
));
716 core_optab
->start
= optab
;
721 if (optab
->name
== NULL
722 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
724 /* different name --> ship out current template list;
725 add to hash table; & begin anew. */
726 core_optab
->end
= optab
;
727 hash_err
= hash_insert (op_hash
,
733 as_fatal (_("Internal Error: Can't hash %s: %s"),
737 if (optab
->name
== NULL
)
739 core_optab
= (templates
*) xmalloc (sizeof (templates
));
740 core_optab
->start
= optab
;
745 /* Initialize reg_hash hash table. */
746 reg_hash
= hash_new ();
748 register const reg_entry
*regtab
;
750 for (regtab
= i386_regtab
;
751 regtab
< i386_regtab
+ sizeof (i386_regtab
) / sizeof (i386_regtab
[0]);
754 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (PTR
) regtab
);
760 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
765 for (c
= 0; c
< 256; c
++)
770 mnemonic_chars
[c
] = c
;
771 register_chars
[c
] = c
;
772 operand_chars
[c
] = c
;
774 else if (islower (c
))
776 mnemonic_chars
[c
] = c
;
777 register_chars
[c
] = c
;
778 operand_chars
[c
] = c
;
780 else if (isupper (c
))
782 mnemonic_chars
[c
] = tolower (c
);
783 register_chars
[c
] = mnemonic_chars
[c
];
784 operand_chars
[c
] = c
;
787 if (isalpha (c
) || isdigit (c
))
788 identifier_chars
[c
] = c
;
791 identifier_chars
[c
] = c
;
792 operand_chars
[c
] = c
;
797 identifier_chars
['@'] = '@';
799 digit_chars
['-'] = '-';
800 identifier_chars
['_'] = '_';
801 identifier_chars
['.'] = '.';
803 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
804 operand_chars
[(unsigned char) *p
] = *p
;
807 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
808 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
810 record_alignment (text_section
, 2);
811 record_alignment (data_section
, 2);
812 record_alignment (bss_section
, 2);
818 i386_print_statistics (file
)
821 hash_print_statistics (file
, "i386 opcode", op_hash
);
822 hash_print_statistics (file
, "i386 register", reg_hash
);
827 /* Debugging routines for md_assemble. */
828 static void pi
PARAMS ((char *, i386_insn
*));
829 static void pte
PARAMS ((template *));
830 static void pt
PARAMS ((unsigned int));
831 static void pe
PARAMS ((expressionS
*));
832 static void ps
PARAMS ((symbolS
*));
839 register template *p
;
842 fprintf (stdout
, "%s: template ", line
);
844 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x",
845 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
846 fprintf (stdout
, " base %x index %x scale %x\n",
847 x
->bi
.base
, x
->bi
.index
, x
->bi
.scale
);
848 for (i
= 0; i
< x
->operands
; i
++)
850 fprintf (stdout
, " #%d: ", i
+ 1);
852 fprintf (stdout
, "\n");
854 & (Reg
| SReg2
| SReg3
| Control
| Debug
| Test
| RegMMX
| RegXMM
))
855 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
856 if (x
->types
[i
] & Imm
)
858 if (x
->types
[i
] & Disp
)
868 fprintf (stdout
, " %d operands ", t
->operands
);
869 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
870 if (t
->extension_opcode
!= None
)
871 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
872 if (t
->opcode_modifier
& D
)
873 fprintf (stdout
, "D");
874 if (t
->opcode_modifier
& W
)
875 fprintf (stdout
, "W");
876 fprintf (stdout
, "\n");
877 for (i
= 0; i
< t
->operands
; i
++)
879 fprintf (stdout
, " #%d type ", i
+ 1);
880 pt (t
->operand_types
[i
]);
881 fprintf (stdout
, "\n");
889 fprintf (stdout
, " operation %d\n", e
->X_op
);
890 fprintf (stdout
, " add_number %ld (%lx)\n",
891 (long) e
->X_add_number
, (long) e
->X_add_number
);
894 fprintf (stdout
, " add_symbol ");
895 ps (e
->X_add_symbol
);
896 fprintf (stdout
, "\n");
900 fprintf (stdout
, " op_symbol ");
902 fprintf (stdout
, "\n");
910 fprintf (stdout
, "%s type %s%s",
912 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
913 segment_name (S_GET_SEGMENT (s
)));
932 { BaseIndex
, "BaseIndex" },
936 { InOutPortReg
, "InOutPortReg" },
937 { ShiftCount
, "ShiftCount" },
938 { Control
, "control reg" },
939 { Test
, "test reg" },
940 { Debug
, "debug reg" },
941 { FloatReg
, "FReg" },
942 { FloatAcc
, "FAcc" },
946 { JumpAbsolute
, "Jump Absolute" },
957 register struct type_name
*ty
;
961 fprintf (stdout
, _("Unknown"));
965 for (ty
= type_names
; ty
->mask
; ty
++)
967 fprintf (stdout
, "%s, ", ty
->tname
);
972 #endif /* DEBUG386 */
975 tc_i386_force_relocation (fixp
)
979 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
980 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
985 return fixp
->fx_r_type
== 7;
990 static bfd_reloc_code_real_type reloc
991 PARAMS ((int, int, bfd_reloc_code_real_type
));
993 static bfd_reloc_code_real_type
994 reloc (size
, pcrel
, other
)
997 bfd_reloc_code_real_type other
;
999 if (other
!= NO_RELOC
)
1006 case 1: return BFD_RELOC_8_PCREL
;
1007 case 2: return BFD_RELOC_16_PCREL
;
1008 case 4: return BFD_RELOC_32_PCREL
;
1010 as_bad (_("can not do %d byte pc-relative relocation"), size
);
1016 case 1: return BFD_RELOC_8
;
1017 case 2: return BFD_RELOC_16
;
1018 case 4: return BFD_RELOC_32
;
1020 as_bad (_("can not do %d byte relocation"), size
);
1023 return BFD_RELOC_NONE
;
1026 /* Here we decide which fixups can be adjusted to make them relative to
1027 the beginning of the section instead of the symbol. Basically we need
1028 to make sure that the dynamic relocations are done correctly, so in
1029 some cases we force the original symbol to be used. */
1032 tc_i386_fix_adjustable (fixP
)
1035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1036 /* Prevent all adjustments to global symbols, or else dynamic
1037 linking will not work correctly. */
1038 if (S_IS_EXTERNAL (fixP
->fx_addsy
)
1039 || S_IS_WEAK (fixP
->fx_addsy
))
1042 /* adjust_reloc_syms doesn't know about the GOT. */
1043 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
1044 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
1045 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
1046 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1047 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1052 #define reloc(SIZE,PCREL,OTHER) 0
1053 #define BFD_RELOC_16 0
1054 #define BFD_RELOC_32 0
1055 #define BFD_RELOC_16_PCREL 0
1056 #define BFD_RELOC_32_PCREL 0
1057 #define BFD_RELOC_386_PLT32 0
1058 #define BFD_RELOC_386_GOT32 0
1059 #define BFD_RELOC_386_GOTOFF 0
1062 static int intel_float_operand
PARAMS ((char *mnemonic
));
1065 intel_float_operand (mnemonic
)
1068 if (mnemonic
[0] == 'f' && mnemonic
[1] == 'i')
1071 if (mnemonic
[0] == 'f')
1077 /* This is the guts of the machine-dependent assembler. LINE points to a
1078 machine dependent instruction. This function is supposed to emit
1079 the frags/bytes it assembles to. */
1085 /* Points to template once we've found it. */
1088 /* Count the size of the instruction generated. */
1093 char mnemonic
[MAX_MNEM_SIZE
];
1095 /* Initialize globals. */
1096 memset (&i
, '\0', sizeof (i
));
1097 for (j
= 0; j
< MAX_OPERANDS
; j
++)
1098 i
.disp_reloc
[j
] = NO_RELOC
;
1099 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
1100 memset (im_expressions
, '\0', sizeof (im_expressions
));
1101 save_stack_p
= save_stack
;
1103 /* First parse an instruction mnemonic & call i386_operand for the operands.
1104 We assume that the scrubber has arranged it so that line[0] is the valid
1105 start of a (possibly prefixed) mnemonic. */
1108 char *token_start
= l
;
1111 /* Non-zero if we found a prefix only acceptable with string insns. */
1112 const char *expecting_string_instruction
= NULL
;
1117 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
1120 if (mnem_p
>= mnemonic
+ sizeof (mnemonic
))
1122 as_bad (_("no such instruction: `%s'"), token_start
);
1127 if (!is_space_char (*l
)
1128 && *l
!= END_OF_INSN
1129 && *l
!= PREFIX_SEPARATOR
)
1131 as_bad (_("invalid character %s in mnemonic"),
1132 output_invalid (*l
));
1135 if (token_start
== l
)
1137 if (*l
== PREFIX_SEPARATOR
)
1138 as_bad (_("expecting prefix; got nothing"));
1140 as_bad (_("expecting mnemonic; got nothing"));
1144 /* Look up instruction (or prefix) via hash table. */
1145 current_templates
= hash_find (op_hash
, mnemonic
);
1147 if (*l
!= END_OF_INSN
1148 && (! is_space_char (*l
) || l
[1] != END_OF_INSN
)
1149 && current_templates
1150 && (current_templates
->start
->opcode_modifier
& IsPrefix
))
1152 /* If we are in 16-bit mode, do not allow addr16 or data16.
1153 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1154 if ((current_templates
->start
->opcode_modifier
& (Size16
| Size32
))
1155 && (((current_templates
->start
->opcode_modifier
& Size32
) != 0)
1158 as_bad (_("redundant %s prefix"),
1159 current_templates
->start
->name
);
1162 /* Add prefix, checking for repeated prefixes. */
1163 switch (add_prefix (current_templates
->start
->base_opcode
))
1168 expecting_string_instruction
= current_templates
->start
->name
;
1171 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1178 if (!current_templates
)
1180 /* See if we can get a match by trimming off a suffix. */
1183 case WORD_MNEM_SUFFIX
:
1184 case BYTE_MNEM_SUFFIX
:
1185 i
.suffix
= mnem_p
[-1];
1187 current_templates
= hash_find (op_hash
, mnemonic
);
1189 case SHORT_MNEM_SUFFIX
:
1190 case LONG_MNEM_SUFFIX
:
1193 i
.suffix
= mnem_p
[-1];
1195 current_templates
= hash_find (op_hash
, mnemonic
);
1203 if (intel_float_operand (mnemonic
))
1204 i
.suffix
= SHORT_MNEM_SUFFIX
;
1206 i
.suffix
= LONG_MNEM_SUFFIX
;
1208 current_templates
= hash_find (op_hash
, mnemonic
);
1212 if (!current_templates
)
1214 as_bad (_("no such instruction: `%s'"), token_start
);
1219 /* Check if instruction is supported on specified architecture. */
1220 if (cpu_arch_flags
!= 0)
1222 if (current_templates
->start
->cpu_flags
& ~cpu_arch_flags
)
1224 as_warn (_("`%s' is not supported on `%s'"),
1225 current_templates
->start
->name
, cpu_arch_name
);
1227 else if ((Cpu386
& ~cpu_arch_flags
) && !flag_16bit_code
)
1229 as_warn (_("use .code16 to ensure correct addressing mode"));
1233 /* Check for rep/repne without a string instruction. */
1234 if (expecting_string_instruction
1235 && !(current_templates
->start
->opcode_modifier
& IsString
))
1237 as_bad (_("expecting string instruction after `%s'"),
1238 expecting_string_instruction
);
1242 /* There may be operands to parse. */
1243 if (*l
!= END_OF_INSN
)
1245 /* 1 if operand is pending after ','. */
1246 unsigned int expecting_operand
= 0;
1248 /* Non-zero if operand parens not balanced. */
1249 unsigned int paren_not_balanced
;
1253 /* Skip optional white space before operand. */
1254 if (is_space_char (*l
))
1256 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
1258 as_bad (_("invalid character %s before operand %d"),
1259 output_invalid (*l
),
1263 token_start
= l
; /* after white space */
1264 paren_not_balanced
= 0;
1265 while (paren_not_balanced
|| *l
!= ',')
1267 if (*l
== END_OF_INSN
)
1269 if (paren_not_balanced
)
1272 as_bad (_("unbalanced parenthesis in operand %d."),
1275 as_bad (_("unbalanced brackets in operand %d."),
1280 break; /* we are done */
1282 else if (!is_operand_char (*l
) && !is_space_char (*l
))
1284 as_bad (_("invalid character %s in operand %d"),
1285 output_invalid (*l
),
1292 ++paren_not_balanced
;
1294 --paren_not_balanced
;
1299 ++paren_not_balanced
;
1301 --paren_not_balanced
;
1305 if (l
!= token_start
)
1306 { /* Yes, we've read in another operand. */
1307 unsigned int operand_ok
;
1308 this_operand
= i
.operands
++;
1309 if (i
.operands
> MAX_OPERANDS
)
1311 as_bad (_("spurious operands; (%d operands/instruction max)"),
1315 /* Now parse operand adding info to 'i' as we go along. */
1316 END_STRING_AND_SAVE (l
);
1320 i386_intel_operand (token_start
,
1321 intel_float_operand (mnemonic
));
1323 operand_ok
= i386_operand (token_start
);
1325 RESTORE_END_STRING (l
);
1331 if (expecting_operand
)
1333 expecting_operand_after_comma
:
1334 as_bad (_("expecting operand after ','; got nothing"));
1339 as_bad (_("expecting operand before ','; got nothing"));
1344 /* Now *l must be either ',' or END_OF_INSN. */
1347 if (*++l
== END_OF_INSN
)
1349 /* Just skip it, if it's \n complain. */
1350 goto expecting_operand_after_comma
;
1352 expecting_operand
= 1;
1355 while (*l
!= END_OF_INSN
);
1359 /* Now we've parsed the mnemonic into a set of templates, and have the
1362 Next, we find a template that matches the given insn,
1363 making sure the overlap of the given operands types is consistent
1364 with the template operand types. */
1366 #define MATCH(overlap, given, template) \
1367 ((overlap & ~JumpAbsolute) \
1368 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1370 /* If given types r0 and r1 are registers they must be of the same type
1371 unless the expected operand type register overlap is null.
1372 Note that Acc in a template matches every size of reg. */
1373 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1374 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1375 ((g0) & Reg) == ((g1) & Reg) || \
1376 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1379 register unsigned int overlap0
, overlap1
;
1380 unsigned int overlap2
;
1381 unsigned int found_reverse_match
;
1384 /* All intel opcodes have reversed operands except for "bound" and
1385 "enter". We also don't reverse intersegment "jmp" and "call"
1386 instructions with 2 immediate operands so that the immediate segment
1387 precedes the offset, as it does when in AT&T mode. "enter" and the
1388 intersegment "jmp" and "call" instructions are the only ones that
1389 have two immediate operands. */
1390 if (intel_syntax
&& i
.operands
> 1
1391 && (strcmp (mnemonic
, "bound") != 0)
1392 && !((i
.types
[0] & Imm
) && (i
.types
[1] & Imm
)))
1394 union i386_op temp_op
;
1395 unsigned int temp_type
;
1396 #ifdef BFD_ASSEMBLER
1397 enum bfd_reloc_code_real temp_disp_reloc
;
1399 int temp_disp_reloc
;
1404 if (i
.operands
== 2)
1409 else if (i
.operands
== 3)
1414 temp_type
= i
.types
[xchg2
];
1415 i
.types
[xchg2
] = i
.types
[xchg1
];
1416 i
.types
[xchg1
] = temp_type
;
1417 temp_op
= i
.op
[xchg2
];
1418 i
.op
[xchg2
] = i
.op
[xchg1
];
1419 i
.op
[xchg1
] = temp_op
;
1420 temp_disp_reloc
= i
.disp_reloc
[xchg2
];
1421 i
.disp_reloc
[xchg2
] = i
.disp_reloc
[xchg1
];
1422 i
.disp_reloc
[xchg1
] = temp_disp_reloc
;
1424 if (i
.mem_operands
== 2)
1426 const seg_entry
*temp_seg
;
1427 temp_seg
= i
.seg
[0];
1428 i
.seg
[0] = i
.seg
[1];
1429 i
.seg
[1] = temp_seg
;
1435 /* Try to ensure constant immediates are represented in the smallest
1437 char guess_suffix
= 0;
1441 guess_suffix
= i
.suffix
;
1442 else if (i
.reg_operands
)
1444 /* Figure out a suffix from the last register operand specified.
1445 We can't do this properly yet, ie. excluding InOutPortReg,
1446 but the following works for instructions with immediates.
1447 In any case, we can't set i.suffix yet. */
1448 for (op
= i
.operands
; --op
>= 0;)
1449 if (i
.types
[op
] & Reg
)
1451 if (i
.types
[op
] & Reg8
)
1452 guess_suffix
= BYTE_MNEM_SUFFIX
;
1453 else if (i
.types
[op
] & Reg16
)
1454 guess_suffix
= WORD_MNEM_SUFFIX
;
1458 else if (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0))
1459 guess_suffix
= WORD_MNEM_SUFFIX
;
1461 for (op
= i
.operands
; --op
>= 0;)
1462 if ((i
.types
[op
] & Imm
)
1463 && i
.op
[op
].imms
->X_op
== O_constant
)
1465 /* If a suffix is given, this operand may be shortened. */
1466 switch (guess_suffix
)
1468 case WORD_MNEM_SUFFIX
:
1469 i
.types
[op
] |= Imm16
;
1471 case BYTE_MNEM_SUFFIX
:
1472 i
.types
[op
] |= Imm16
| Imm8
| Imm8S
;
1476 /* If this operand is at most 16 bits, convert it to a
1477 signed 16 bit number before trying to see whether it will
1478 fit in an even smaller size. This allows a 16-bit operand
1479 such as $0xffe0 to be recognised as within Imm8S range. */
1480 if ((i
.types
[op
] & Imm16
)
1481 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
)0xffff) == 0)
1483 i
.op
[op
].imms
->X_add_number
=
1484 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
1486 i
.types
[op
] |= smallest_imm_type ((long) i
.op
[op
].imms
->X_add_number
);
1490 if (i
.disp_operands
)
1492 /* Try to use the smallest displacement type too. */
1495 for (op
= i
.operands
; --op
>= 0;)
1496 if ((i
.types
[op
] & Disp
)
1497 && i
.op
[op
].imms
->X_op
== O_constant
)
1499 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
1501 if (i
.types
[op
] & Disp16
)
1503 /* We know this operand is at most 16 bits, so
1504 convert to a signed 16 bit number before trying
1505 to see whether it will fit in an even smaller
1508 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
1510 if (fits_in_signed_byte (disp
))
1511 i
.types
[op
] |= Disp8
;
1518 found_reverse_match
= 0;
1519 suffix_check
= (i
.suffix
== BYTE_MNEM_SUFFIX
1521 : (i
.suffix
== WORD_MNEM_SUFFIX
1523 : (i
.suffix
== SHORT_MNEM_SUFFIX
1525 : (i
.suffix
== LONG_MNEM_SUFFIX
1527 : (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
? No_xSuf
: 0)))));
1529 for (t
= current_templates
->start
;
1530 t
< current_templates
->end
;
1533 /* Must have right number of operands. */
1534 if (i
.operands
!= t
->operands
)
1537 /* Check the suffix, except for some instructions in intel mode. */
1538 if ((t
->opcode_modifier
& suffix_check
)
1540 && (t
->opcode_modifier
& IgnoreSize
))
1542 && t
->base_opcode
== 0xd9
1543 && (t
->extension_opcode
== 5 /* 0xd9,5 "fldcw" */
1544 || t
->extension_opcode
== 7))) /* 0xd9,7 "f{n}stcw" */
1547 else if (!t
->operands
)
1548 /* 0 operands always matches. */
1551 overlap0
= i
.types
[0] & t
->operand_types
[0];
1552 switch (t
->operands
)
1555 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0]))
1560 overlap1
= i
.types
[1] & t
->operand_types
[1];
1561 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[0])
1562 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[1])
1563 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1564 t
->operand_types
[0],
1565 overlap1
, i
.types
[1],
1566 t
->operand_types
[1]))
1568 /* Check if other direction is valid ... */
1569 if ((t
->opcode_modifier
& (D
|FloatD
)) == 0)
1572 /* Try reversing direction of operands. */
1573 overlap0
= i
.types
[0] & t
->operand_types
[1];
1574 overlap1
= i
.types
[1] & t
->operand_types
[0];
1575 if (!MATCH (overlap0
, i
.types
[0], t
->operand_types
[1])
1576 || !MATCH (overlap1
, i
.types
[1], t
->operand_types
[0])
1577 || !CONSISTENT_REGISTER_MATCH (overlap0
, i
.types
[0],
1578 t
->operand_types
[1],
1579 overlap1
, i
.types
[1],
1580 t
->operand_types
[0]))
1582 /* Does not match either direction. */
1585 /* found_reverse_match holds which of D or FloatDR
1587 found_reverse_match
= t
->opcode_modifier
& (D
|FloatDR
);
1590 /* Found a forward 2 operand match here. */
1591 if (t
->operands
== 3)
1593 /* Here we make use of the fact that there are no
1594 reverse match 3 operand instructions, and all 3
1595 operand instructions only need to be checked for
1596 register consistency between operands 2 and 3. */
1597 overlap2
= i
.types
[2] & t
->operand_types
[2];
1598 if (!MATCH (overlap2
, i
.types
[2], t
->operand_types
[2])
1599 || !CONSISTENT_REGISTER_MATCH (overlap1
, i
.types
[1],
1600 t
->operand_types
[1],
1601 overlap2
, i
.types
[2],
1602 t
->operand_types
[2]))
1606 /* Found either forward/reverse 2 or 3 operand match here:
1607 slip through to break. */
1609 /* We've found a match; break out of loop. */
1612 if (t
== current_templates
->end
)
1614 /* We found no match. */
1615 as_bad (_("suffix or operands invalid for `%s'"),
1616 current_templates
->start
->name
);
1620 if (!quiet_warnings
)
1623 && ((i
.types
[0] & JumpAbsolute
)
1624 != (t
->operand_types
[0] & JumpAbsolute
)))
1626 as_warn (_("indirect %s without `*'"), t
->name
);
1629 if ((t
->opcode_modifier
& (IsPrefix
|IgnoreSize
))
1630 == (IsPrefix
|IgnoreSize
))
1632 /* Warn them that a data or address size prefix doesn't
1633 affect assembly of the next line of code. */
1634 as_warn (_("stand-alone `%s' prefix"), t
->name
);
1638 /* Copy the template we found. */
1640 if (found_reverse_match
)
1642 /* If we found a reverse match we must alter the opcode
1643 direction bit. found_reverse_match holds bits to change
1644 (different for int & float insns). */
1646 i
.tm
.base_opcode
^= found_reverse_match
;
1648 i
.tm
.operand_types
[0] = t
->operand_types
[1];
1649 i
.tm
.operand_types
[1] = t
->operand_types
[0];
1652 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1655 && (i
.tm
.base_opcode
& 0xfffffde0) == 0xdce0)
1656 i
.tm
.base_opcode
^= FloatR
;
1658 if (i
.tm
.opcode_modifier
& FWait
)
1659 if (! add_prefix (FWAIT_OPCODE
))
1662 /* Check string instruction segment overrides. */
1663 if ((i
.tm
.opcode_modifier
& IsString
) != 0 && i
.mem_operands
!= 0)
1665 int mem_op
= (i
.types
[0] & AnyMem
) ? 0 : 1;
1666 if ((i
.tm
.operand_types
[mem_op
] & EsSeg
) != 0)
1668 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
1670 as_bad (_("`%s' operand %d must use `%%es' segment"),
1675 /* There's only ever one segment override allowed per instruction.
1676 This instruction possibly has a legal segment override on the
1677 second operand, so copy the segment to where non-string
1678 instructions store it, allowing common code. */
1679 i
.seg
[0] = i
.seg
[1];
1681 else if ((i
.tm
.operand_types
[mem_op
+ 1] & EsSeg
) != 0)
1683 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
1685 as_bad (_("`%s' operand %d must use `%%es' segment"),
1693 /* If matched instruction specifies an explicit instruction mnemonic
1695 if (i
.tm
.opcode_modifier
& (Size16
| Size32
))
1697 if (i
.tm
.opcode_modifier
& Size16
)
1698 i
.suffix
= WORD_MNEM_SUFFIX
;
1700 i
.suffix
= LONG_MNEM_SUFFIX
;
1702 else if (i
.reg_operands
)
1704 /* If there's no instruction mnemonic suffix we try to invent one
1705 based on register operands. */
1708 /* We take i.suffix from the last register operand specified,
1709 Destination register type is more significant than source
1712 for (op
= i
.operands
; --op
>= 0;)
1713 if ((i
.types
[op
] & Reg
)
1714 && !(i
.tm
.operand_types
[op
] & InOutPortReg
))
1716 i
.suffix
= ((i
.types
[op
] & Reg8
) ? BYTE_MNEM_SUFFIX
:
1717 (i
.types
[op
] & Reg16
) ? WORD_MNEM_SUFFIX
:
1722 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
1725 for (op
= i
.operands
; --op
>= 0;)
1727 /* If this is an eight bit register, it's OK. If it's
1728 the 16 or 32 bit version of an eight bit register,
1729 we will just use the low portion, and that's OK too. */
1730 if (i
.types
[op
] & Reg8
)
1733 /* movzx and movsx should not generate this warning. */
1735 && (i
.tm
.base_opcode
== 0xfb7
1736 || i
.tm
.base_opcode
== 0xfb6
1737 || i
.tm
.base_opcode
== 0xfbe
1738 || i
.tm
.base_opcode
== 0xfbf))
1741 if ((i
.types
[op
] & WordReg
) && i
.op
[op
].regs
->reg_num
< 4
1743 /* Check that the template allows eight bit regs
1744 This kills insns such as `orb $1,%edx', which
1745 maybe should be allowed. */
1746 && (i
.tm
.operand_types
[op
] & (Reg8
|InOutPortReg
))
1750 #if REGISTER_WARNINGS
1752 && (i
.tm
.operand_types
[op
] & InOutPortReg
) == 0)
1753 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1754 (i
.op
[op
].regs
- (i
.types
[op
] & Reg16
? 8 : 16))->reg_name
,
1755 i
.op
[op
].regs
->reg_name
,
1760 /* Any other register is bad. */
1761 if (i
.types
[op
] & (Reg
| RegMMX
| RegXMM
1763 | Control
| Debug
| Test
1764 | FloatReg
| FloatAcc
))
1766 as_bad (_("`%%%s' not allowed with `%s%c'"),
1767 i
.op
[op
].regs
->reg_name
,
1774 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
1778 for (op
= i
.operands
; --op
>= 0;)
1779 /* Reject eight bit registers, except where the template
1780 requires them. (eg. movzb) */
1781 if ((i
.types
[op
] & Reg8
) != 0
1782 && (i
.tm
.operand_types
[op
] & (Reg16
| Reg32
| Acc
)) != 0)
1784 as_bad (_("`%%%s' not allowed with `%s%c'"),
1785 i
.op
[op
].regs
->reg_name
,
1790 #if REGISTER_WARNINGS
1791 /* Warn if the e prefix on a general reg is missing. */
1792 else if (!quiet_warnings
1793 && (i
.types
[op
] & Reg16
) != 0
1794 && (i
.tm
.operand_types
[op
] & (Reg32
|Acc
)) != 0)
1796 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1797 (i
.op
[op
].regs
+ 8)->reg_name
,
1798 i
.op
[op
].regs
->reg_name
,
1803 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
1806 for (op
= i
.operands
; --op
>= 0;)
1807 /* Reject eight bit registers, except where the template
1808 requires them. (eg. movzb) */
1809 if ((i
.types
[op
] & Reg8
) != 0
1810 && (i
.tm
.operand_types
[op
] & (Reg16
|Reg32
|Acc
)) != 0)
1812 as_bad (_("`%%%s' not allowed with `%s%c'"),
1813 i
.op
[op
].regs
->reg_name
,
1818 #if REGISTER_WARNINGS
1819 /* Warn if the e prefix on a general reg is present. */
1820 else if (!quiet_warnings
1821 && (i
.types
[op
] & Reg32
) != 0
1822 && (i
.tm
.operand_types
[op
] & (Reg16
|Acc
)) != 0)
1824 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1825 (i
.op
[op
].regs
- 8)->reg_name
,
1826 i
.op
[op
].regs
->reg_name
,
1831 else if (intel_syntax
&& (i
.tm
.opcode_modifier
& IgnoreSize
))
1832 /* Do nothing if the instruction is going to ignore the prefix. */
1837 else if ((i
.tm
.opcode_modifier
& DefaultSize
) && !i
.suffix
)
1839 i
.suffix
= stackop_size
;
1842 /* Make still unresolved immediate matches conform to size of immediate
1843 given in i.suffix. Note: overlap2 cannot be an immediate! */
1844 if ((overlap0
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1845 && overlap0
!= Imm8
&& overlap0
!= Imm8S
1846 && overlap0
!= Imm16
&& overlap0
!= Imm32
)
1850 overlap0
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1851 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1853 else if (overlap0
== (Imm16
| Imm32
))
1856 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1860 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1864 if ((overlap1
& (Imm8
| Imm8S
| Imm16
| Imm32
))
1865 && overlap1
!= Imm8
&& overlap1
!= Imm8S
1866 && overlap1
!= Imm16
&& overlap1
!= Imm32
)
1870 overlap1
&= (i
.suffix
== BYTE_MNEM_SUFFIX
? (Imm8
| Imm8S
) :
1871 (i
.suffix
== WORD_MNEM_SUFFIX
? Imm16
: Imm32
));
1873 else if (overlap1
== (Imm16
| Imm32
))
1876 (flag_16bit_code
^ (i
.prefix
[DATA_PREFIX
] != 0)) ? Imm16
: Imm32
;
1880 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1884 assert ((overlap2
& Imm
) == 0);
1886 i
.types
[0] = overlap0
;
1887 if (overlap0
& ImplicitRegister
)
1889 if (overlap0
& Imm1
)
1890 i
.imm_operands
= 0; /* kludge for shift insns. */
1892 i
.types
[1] = overlap1
;
1893 if (overlap1
& ImplicitRegister
)
1896 i
.types
[2] = overlap2
;
1897 if (overlap2
& ImplicitRegister
)
1900 /* Finalize opcode. First, we change the opcode based on the operand
1901 size given by i.suffix: We need not change things for byte insns. */
1903 if (!i
.suffix
&& (i
.tm
.opcode_modifier
& W
))
1905 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1909 /* For movzx and movsx, need to check the register type. */
1911 && (i
.tm
.base_opcode
== 0xfb6 || i
.tm
.base_opcode
== 0xfbe))
1912 if (i
.suffix
&& i
.suffix
== BYTE_MNEM_SUFFIX
)
1914 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1916 if ((i
.op
[1].regs
->reg_type
& Reg16
) != 0)
1917 if (!add_prefix (prefix
))
1921 if (i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
1923 /* It's not a byte, select word/dword operation. */
1924 if (i
.tm
.opcode_modifier
& W
)
1926 if (i
.tm
.opcode_modifier
& ShortForm
)
1927 i
.tm
.base_opcode
|= 8;
1929 i
.tm
.base_opcode
|= 1;
1931 /* Now select between word & dword operations via the operand
1932 size prefix, except for instructions that will ignore this
1934 if ((i
.suffix
== LONG_MNEM_SUFFIX
) == flag_16bit_code
1935 && !(i
.tm
.opcode_modifier
& IgnoreSize
))
1937 unsigned int prefix
= DATA_PREFIX_OPCODE
;
1938 if (i
.tm
.opcode_modifier
& JumpByte
) /* jcxz, loop */
1939 prefix
= ADDR_PREFIX_OPCODE
;
1941 if (! add_prefix (prefix
))
1944 /* Size floating point instruction. */
1945 if (i
.suffix
== LONG_MNEM_SUFFIX
)
1947 if (i
.tm
.opcode_modifier
& FloatMF
)
1948 i
.tm
.base_opcode
^= 4;
1952 if (i
.tm
.opcode_modifier
& ImmExt
)
1954 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1955 opcode suffix which is coded in the same place as an 8-bit
1956 immediate field would be. Here we fake an 8-bit immediate
1957 operand from the opcode suffix stored in tm.extension_opcode. */
1961 assert (i
.imm_operands
== 0 && i
.operands
<= 2 && 2 < MAX_OPERANDS
);
1963 exp
= &im_expressions
[i
.imm_operands
++];
1964 i
.op
[i
.operands
].imms
= exp
;
1965 i
.types
[i
.operands
++] = Imm8
;
1966 exp
->X_op
= O_constant
;
1967 exp
->X_add_number
= i
.tm
.extension_opcode
;
1968 i
.tm
.extension_opcode
= None
;
1971 /* For insns with operands there are more diddles to do to the opcode. */
1974 /* Default segment register this instruction will use
1975 for memory accesses. 0 means unknown.
1976 This is only for optimizing out unnecessary segment overrides. */
1977 const seg_entry
*default_seg
= 0;
1979 /* The imul $imm, %reg instruction is converted into
1980 imul $imm, %reg, %reg, and the clr %reg instruction
1981 is converted into xor %reg, %reg. */
1982 if (i
.tm
.opcode_modifier
& regKludge
)
1984 unsigned int first_reg_op
= (i
.types
[0] & Reg
) ? 0 : 1;
1985 /* Pretend we saw the extra register operand. */
1986 assert (i
.op
[first_reg_op
+ 1].regs
== 0);
1987 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
1988 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
1992 if (i
.tm
.opcode_modifier
& ShortForm
)
1994 /* The register or float register operand is in operand 0 or 1. */
1995 unsigned int op
= (i
.types
[0] & (Reg
| FloatReg
)) ? 0 : 1;
1996 /* Register goes in low 3 bits of opcode. */
1997 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
1998 if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2000 /* Warn about some common errors, but press on regardless.
2001 The first case can be generated by gcc (<= 2.8.1). */
2002 if (i
.operands
== 2)
2004 /* Reversed arguments on faddp, fsubp, etc. */
2005 as_warn (_("translating to `%s %%%s,%%%s'"), i
.tm
.name
,
2006 i
.op
[1].regs
->reg_name
,
2007 i
.op
[0].regs
->reg_name
);
2011 /* Extraneous `l' suffix on fp insn. */
2012 as_warn (_("translating to `%s %%%s'"), i
.tm
.name
,
2013 i
.op
[0].regs
->reg_name
);
2017 else if (i
.tm
.opcode_modifier
& Modrm
)
2019 /* The opcode is completed (modulo i.tm.extension_opcode which
2020 must be put into the modrm byte).
2021 Now, we make the modrm & index base bytes based on all the
2022 info we've collected. */
2024 /* i.reg_operands MUST be the number of real register operands;
2025 implicit registers do not count. */
2026 if (i
.reg_operands
== 2)
2028 unsigned int source
, dest
;
2029 source
= ((i
.types
[0]
2030 & (Reg
| RegMMX
| RegXMM
2032 | Control
| Debug
| Test
))
2037 /* One of the register operands will be encoded in the
2038 i.tm.reg field, the other in the combined i.tm.mode
2039 and i.tm.regmem fields. If no form of this
2040 instruction supports a memory destination operand,
2041 then we assume the source operand may sometimes be
2042 a memory operand and so we need to store the
2043 destination in the i.rm.reg field. */
2044 if ((i
.tm
.operand_types
[dest
] & AnyMem
) == 0)
2046 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
2047 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
2051 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
2052 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
2056 { /* If it's not 2 reg operands... */
2059 unsigned int fake_zero_displacement
= 0;
2060 unsigned int op
= ((i
.types
[0] & AnyMem
)
2062 : (i
.types
[1] & AnyMem
) ? 1 : 2);
2069 if (! i
.disp_operands
)
2070 fake_zero_displacement
= 1;
2073 /* Operand is just <disp> */
2074 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2076 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
2077 i
.types
[op
] &= ~Disp
;
2078 i
.types
[op
] |= Disp16
;
2082 i
.rm
.regmem
= NO_BASE_REGISTER
;
2083 i
.types
[op
] &= ~Disp
;
2084 i
.types
[op
] |= Disp32
;
2087 else /* ! i.base_reg && i.index_reg */
2089 i
.sib
.index
= i
.index_reg
->reg_num
;
2090 i
.sib
.base
= NO_BASE_REGISTER
;
2091 i
.sib
.scale
= i
.log2_scale_factor
;
2092 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2093 i
.types
[op
] &= ~Disp
;
2094 i
.types
[op
] |= Disp32
; /* Must be 32 bit. */
2097 else if (i
.base_reg
->reg_type
& Reg16
)
2099 switch (i
.base_reg
->reg_num
)
2104 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2105 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
2112 if ((i
.types
[op
] & Disp
) == 0)
2114 /* fake (%bp) into 0(%bp) */
2115 i
.types
[op
] |= Disp8
;
2116 fake_zero_displacement
= 1;
2119 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2120 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
2122 default: /* (%si) -> 4 or (%di) -> 5 */
2123 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
2125 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2127 else /* i.base_reg and 32 bit mode */
2129 i
.rm
.regmem
= i
.base_reg
->reg_num
;
2130 i
.sib
.base
= i
.base_reg
->reg_num
;
2131 if (i
.base_reg
->reg_num
== EBP_REG_NUM
)
2134 if (i
.disp_operands
== 0)
2136 fake_zero_displacement
= 1;
2137 i
.types
[op
] |= Disp8
;
2140 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
2144 i
.sib
.scale
= i
.log2_scale_factor
;
2147 /* <disp>(%esp) becomes two byte modrm
2148 with no index register. We've already
2149 stored the code for esp in i.rm.regmem
2150 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2151 base register besides %esp will not use
2152 the extra modrm byte. */
2153 i
.sib
.index
= NO_INDEX_REGISTER
;
2154 #if ! SCALE1_WHEN_NO_INDEX
2155 /* Another case where we force the second
2157 if (i
.log2_scale_factor
)
2158 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2163 i
.sib
.index
= i
.index_reg
->reg_num
;
2164 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
2166 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
2169 if (fake_zero_displacement
)
2171 /* Fakes a zero displacement assuming that i.types[op]
2172 holds the correct displacement size. */
2175 assert (i
.op
[op
].disps
== 0);
2176 exp
= &disp_expressions
[i
.disp_operands
++];
2177 i
.op
[op
].disps
= exp
;
2178 exp
->X_op
= O_constant
;
2179 exp
->X_add_number
= 0;
2180 exp
->X_add_symbol
= (symbolS
*) 0;
2181 exp
->X_op_symbol
= (symbolS
*) 0;
2185 /* Fill in i.rm.reg or i.rm.regmem field with register
2186 operand (if any) based on i.tm.extension_opcode.
2187 Again, we must be careful to make sure that
2188 segment/control/debug/test/MMX registers are coded
2189 into the i.rm.reg field. */
2194 & (Reg
| RegMMX
| RegXMM
2196 | Control
| Debug
| Test
))
2199 & (Reg
| RegMMX
| RegXMM
2201 | Control
| Debug
| Test
))
2204 /* If there is an extension opcode to put here, the
2205 register number must be put into the regmem field. */
2206 if (i
.tm
.extension_opcode
!= None
)
2207 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
2209 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
2211 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2212 we must set it to 3 to indicate this is a register
2213 operand in the regmem field. */
2214 if (!i
.mem_operands
)
2218 /* Fill in i.rm.reg field with extension opcode (if any). */
2219 if (i
.tm
.extension_opcode
!= None
)
2220 i
.rm
.reg
= i
.tm
.extension_opcode
;
2223 else if (i
.tm
.opcode_modifier
& (Seg2ShortForm
| Seg3ShortForm
))
2225 if (i
.tm
.base_opcode
== POP_SEG_SHORT
2226 && i
.op
[0].regs
->reg_num
== 1)
2228 as_bad (_("you can't `pop %%cs'"));
2231 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
2233 else if ((i
.tm
.base_opcode
& ~(D
|W
)) == MOV_AX_DISP32
)
2237 else if ((i
.tm
.opcode_modifier
& IsString
) != 0)
2239 /* For the string instructions that allow a segment override
2240 on one of their operands, the default segment is ds. */
2244 /* If a segment was explicitly specified,
2245 and the specified segment is not the default,
2246 use an opcode prefix to select it.
2247 If we never figured out what the default segment is,
2248 then default_seg will be zero at this point,
2249 and the specified segment prefix will always be used. */
2250 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
2252 if (! add_prefix (i
.seg
[0]->seg_prefix
))
2256 else if (!quiet_warnings
&& (i
.tm
.opcode_modifier
& Ugh
) != 0)
2258 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2259 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2263 /* Handle conversion of 'int $3' --> special int3 insn. */
2264 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2266 i
.tm
.base_opcode
= INT3_OPCODE
;
2270 if ((i
.tm
.opcode_modifier
& (Jump
| JumpByte
| JumpDword
))
2271 && i
.op
[0].disps
->X_op
== O_constant
)
2273 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2274 the absolute address given by the constant. Since ix86 jumps and
2275 calls are pc relative, we need to generate a reloc. */
2276 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2277 i
.op
[0].disps
->X_op
= O_symbol
;
2280 /* We are ready to output the insn. */
2285 if (i
.tm
.opcode_modifier
& Jump
)
2292 if (flag_16bit_code
)
2296 if (i
.prefix
[DATA_PREFIX
])
2307 if (i
.prefixes
!= 0 && !intel_syntax
)
2308 as_warn (_("skipping prefixes on this instruction"));
2310 /* It's always a symbol; End frag & setup for relax.
2311 Make sure there is enough room in this frag for the largest
2312 instruction we may generate in md_convert_frag. This is 2
2313 bytes for the opcode and room for the prefix and largest
2315 frag_grow (prefix
+ 2 + size
);
2316 insn_size
+= prefix
+ 1;
2317 /* Prefix and 1 opcode byte go in fr_fix. */
2318 p
= frag_more (prefix
+ 1);
2320 *p
++ = DATA_PREFIX_OPCODE
;
2321 *p
= i
.tm
.base_opcode
;
2322 /* 1 possible extra opcode + displacement go in var part.
2323 Pass reloc in fr_var. */
2324 frag_var (rs_machine_dependent
,
2327 ((unsigned char) *p
== JUMP_PC_RELATIVE
2328 ? ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
) | code16
2329 : ENCODE_RELAX_STATE (COND_JUMP
, SMALL
) | code16
),
2330 i
.op
[0].disps
->X_add_symbol
,
2331 i
.op
[0].disps
->X_add_number
,
2334 else if (i
.tm
.opcode_modifier
& (JumpByte
| JumpDword
))
2338 if (i
.tm
.opcode_modifier
& JumpByte
)
2340 /* This is a loop or jecxz type instruction. */
2342 if (i
.prefix
[ADDR_PREFIX
])
2345 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
2354 if (flag_16bit_code
)
2357 if (i
.prefix
[DATA_PREFIX
])
2360 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
2370 if (i
.prefixes
!= 0 && !intel_syntax
)
2371 as_warn (_("skipping prefixes on this instruction"));
2373 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2375 insn_size
+= 1 + size
;
2376 p
= frag_more (1 + size
);
2380 /* Opcode can be at most two bytes. */
2381 insn_size
+= 2 + size
;
2382 p
= frag_more (2 + size
);
2383 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2385 *p
++ = i
.tm
.base_opcode
& 0xff;
2387 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2388 i
.op
[0].disps
, 1, reloc (size
, 1, i
.disp_reloc
[0]));
2390 else if (i
.tm
.opcode_modifier
& JumpInterSegment
)
2397 if (flag_16bit_code
)
2401 if (i
.prefix
[DATA_PREFIX
])
2412 if (i
.prefixes
!= 0 && !intel_syntax
)
2413 as_warn (_("skipping prefixes on this instruction"));
2415 /* 1 opcode; 2 segment; offset */
2416 insn_size
+= prefix
+ 1 + 2 + size
;
2417 p
= frag_more (prefix
+ 1 + 2 + size
);
2419 *p
++ = DATA_PREFIX_OPCODE
;
2420 *p
++ = i
.tm
.base_opcode
;
2421 if (i
.op
[1].imms
->X_op
== O_constant
)
2423 offsetT n
= i
.op
[1].imms
->X_add_number
;
2426 && !fits_in_unsigned_word (n
)
2427 && !fits_in_signed_word (n
))
2429 as_bad (_("16-bit jump out of range"));
2432 md_number_to_chars (p
, n
, size
);
2435 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2436 i
.op
[1].imms
, 0, reloc (size
, 0, i
.disp_reloc
[0]));
2437 if (i
.op
[0].imms
->X_op
!= O_constant
)
2438 as_bad (_("can't handle non absolute segment in `%s'"),
2440 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
2444 /* Output normal instructions here. */
2447 /* The prefix bytes. */
2449 q
< i
.prefix
+ sizeof (i
.prefix
) / sizeof (i
.prefix
[0]);
2456 md_number_to_chars (p
, (valueT
) *q
, 1);
2460 /* Now the opcode; be careful about word order here! */
2461 if (fits_in_unsigned_byte (i
.tm
.base_opcode
))
2464 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
2466 else if (fits_in_unsigned_word (i
.tm
.base_opcode
))
2470 /* Put out high byte first: can't use md_number_to_chars! */
2471 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2472 *p
= i
.tm
.base_opcode
& 0xff;
2475 { /* Opcode is either 3 or 4 bytes. */
2476 if (i
.tm
.base_opcode
& 0xff000000)
2480 *p
++ = (i
.tm
.base_opcode
>> 24) & 0xff;
2487 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
2488 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
2489 *p
= (i
.tm
.base_opcode
) & 0xff;
2492 /* Now the modrm byte and sib byte (if present). */
2493 if (i
.tm
.opcode_modifier
& Modrm
)
2497 md_number_to_chars (p
,
2498 (valueT
) (i
.rm
.regmem
<< 0
2502 /* If i.rm.regmem == ESP (4)
2503 && i.rm.mode != (Register mode)
2505 ==> need second modrm byte. */
2506 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
2508 && !(i
.base_reg
&& (i
.base_reg
->reg_type
& Reg16
) != 0))
2512 md_number_to_chars (p
,
2513 (valueT
) (i
.sib
.base
<< 0
2515 | i
.sib
.scale
<< 6),
2520 if (i
.disp_operands
)
2522 register unsigned int n
;
2524 for (n
= 0; n
< i
.operands
; n
++)
2526 if (i
.types
[n
] & Disp
)
2528 if (i
.op
[n
].disps
->X_op
== O_constant
)
2534 if (i
.types
[n
] & (Disp8
| Disp16
))
2537 if (i
.types
[n
] & Disp8
)
2540 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
2543 p
= frag_more (size
);
2544 md_number_to_chars (p
, val
, size
);
2550 if (i
.types
[n
] & Disp16
)
2554 p
= frag_more (size
);
2555 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2557 reloc (size
, 0, i
.disp_reloc
[n
]));
2563 /* Output immediate. */
2566 register unsigned int n
;
2568 for (n
= 0; n
< i
.operands
; n
++)
2570 if (i
.types
[n
] & Imm
)
2572 if (i
.op
[n
].imms
->X_op
== O_constant
)
2578 if (i
.types
[n
] & (Imm8
| Imm8S
| Imm16
))
2581 if (i
.types
[n
] & (Imm8
| Imm8S
))
2584 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
2587 p
= frag_more (size
);
2588 md_number_to_chars (p
, val
, size
);
2592 /* Not absolute_section.
2593 Need a 32-bit fixup (don't support 8bit
2594 non-absolute imms). Try to support other
2596 #ifdef BFD_ASSEMBLER
2597 enum bfd_reloc_code_real reloc_type
;
2603 if (i
.types
[n
] & Imm16
)
2605 else if (i
.types
[n
] & (Imm8
| Imm8S
))
2609 p
= frag_more (size
);
2610 reloc_type
= reloc (size
, 0, i
.disp_reloc
[0]);
2611 #ifdef BFD_ASSEMBLER
2612 if (reloc_type
== BFD_RELOC_32
2614 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
2615 && (i
.op
[n
].imms
->X_op
== O_symbol
2616 || (i
.op
[n
].imms
->X_op
== O_add
2617 && ((symbol_get_value_expression
2618 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
2621 reloc_type
= BFD_RELOC_386_GOTPC
;
2622 i
.op
[n
].imms
->X_add_number
+= 3;
2625 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
2626 i
.op
[n
].imms
, 0, reloc_type
);
2633 dwarf2_emit_insn (insn_size
);
2640 #endif /* DEBUG386 */
2644 static int i386_immediate
PARAMS ((char *));
2647 i386_immediate (imm_start
)
2650 char *save_input_line_pointer
;
2654 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
2656 as_bad (_("only 1 or 2 immediate operands are allowed"));
2660 exp
= &im_expressions
[i
.imm_operands
++];
2661 i
.op
[this_operand
].imms
= exp
;
2663 if (is_space_char (*imm_start
))
2666 save_input_line_pointer
= input_line_pointer
;
2667 input_line_pointer
= imm_start
;
2671 /* We can have operands of the form
2672 <symbol>@GOTOFF+<nnn>
2673 Take the easy way out here and copy everything
2674 into a temporary buffer... */
2677 cp
= strchr (input_line_pointer
, '@');
2684 /* GOT relocations are not supported in 16 bit mode. */
2685 if (flag_16bit_code
)
2686 as_bad (_("GOT relocations not supported in 16 bit mode"));
2688 if (GOT_symbol
== NULL
)
2689 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2691 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2693 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2696 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2698 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2701 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2703 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2707 as_bad (_("bad reloc specifier in expression"));
2709 /* Replace the relocation token with ' ', so that errors like
2710 foo@GOTOFF1 will be detected. */
2711 first
= cp
- input_line_pointer
;
2712 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2713 memcpy (tmpbuf
, input_line_pointer
, first
);
2714 tmpbuf
[first
] = ' ';
2715 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2716 input_line_pointer
= tmpbuf
;
2721 exp_seg
= expression (exp
);
2724 if (*input_line_pointer
)
2725 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer
);
2727 input_line_pointer
= save_input_line_pointer
;
2729 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2731 /* Missing or bad expr becomes absolute 0. */
2732 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2734 exp
->X_op
= O_constant
;
2735 exp
->X_add_number
= 0;
2736 exp
->X_add_symbol
= (symbolS
*) 0;
2737 exp
->X_op_symbol
= (symbolS
*) 0;
2740 if (exp
->X_op
== O_constant
)
2742 /* Size it properly later. */
2743 i
.types
[this_operand
] |= Imm32
;
2745 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2747 #ifdef BFD_ASSEMBLER
2748 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2750 && exp_seg
!= text_section
2751 && exp_seg
!= data_section
2752 && exp_seg
!= bss_section
2753 && exp_seg
!= undefined_section
2754 #ifdef BFD_ASSEMBLER
2755 && !bfd_is_com_section (exp_seg
)
2759 #ifdef BFD_ASSEMBLER
2760 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2762 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
2769 /* This is an address. The size of the address will be
2770 determined later, depending on destination register,
2771 suffix, or the default for the section. We exclude
2772 Imm8S here so that `push $foo' and other instructions
2773 with an Imm8S form will use Imm16 or Imm32. */
2774 i
.types
[this_operand
] |= (Imm8
| Imm16
| Imm32
);
2780 static int i386_scale
PARAMS ((char *));
2786 if (!isdigit (*scale
))
2793 i
.log2_scale_factor
= 0;
2796 i
.log2_scale_factor
= 1;
2799 i
.log2_scale_factor
= 2;
2802 i
.log2_scale_factor
= 3;
2806 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2810 if (i
.log2_scale_factor
!= 0 && ! i
.index_reg
)
2812 as_warn (_("scale factor of %d without an index register"),
2813 1 << i
.log2_scale_factor
);
2814 #if SCALE1_WHEN_NO_INDEX
2815 i
.log2_scale_factor
= 0;
2821 static int i386_displacement
PARAMS ((char *, char *));
2824 i386_displacement (disp_start
, disp_end
)
2828 register expressionS
*exp
;
2830 char *save_input_line_pointer
;
2831 int bigdisp
= Disp32
;
2833 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0))
2835 i
.types
[this_operand
] |= bigdisp
;
2837 exp
= &disp_expressions
[i
.disp_operands
];
2838 i
.op
[this_operand
].disps
= exp
;
2840 save_input_line_pointer
= input_line_pointer
;
2841 input_line_pointer
= disp_start
;
2842 END_STRING_AND_SAVE (disp_end
);
2844 #ifndef GCC_ASM_O_HACK
2845 #define GCC_ASM_O_HACK 0
2848 END_STRING_AND_SAVE (disp_end
+ 1);
2849 if ((i
.types
[this_operand
] & BaseIndex
) != 0
2850 && displacement_string_end
[-1] == '+')
2852 /* This hack is to avoid a warning when using the "o"
2853 constraint within gcc asm statements.
2856 #define _set_tssldt_desc(n,addr,limit,type) \
2857 __asm__ __volatile__ ( \
2859 "movw %w1,2+%0\n\t" \
2861 "movb %b1,4+%0\n\t" \
2862 "movb %4,5+%0\n\t" \
2863 "movb $0,6+%0\n\t" \
2864 "movb %h1,7+%0\n\t" \
2866 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2868 This works great except that the output assembler ends
2869 up looking a bit weird if it turns out that there is
2870 no offset. You end up producing code that looks like:
2883 So here we provide the missing zero. */
2885 *displacement_string_end
= '0';
2890 /* We can have operands of the form
2891 <symbol>@GOTOFF+<nnn>
2892 Take the easy way out here and copy everything
2893 into a temporary buffer... */
2896 cp
= strchr (input_line_pointer
, '@');
2903 /* GOT relocations are not supported in 16 bit mode. */
2904 if (flag_16bit_code
)
2905 as_bad (_("GOT relocations not supported in 16 bit mode"));
2907 if (GOT_symbol
== NULL
)
2908 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
2910 if (strncmp (cp
+ 1, "PLT", 3) == 0)
2912 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_PLT32
;
2915 else if (strncmp (cp
+ 1, "GOTOFF", 6) == 0)
2917 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOTOFF
;
2920 else if (strncmp (cp
+ 1, "GOT", 3) == 0)
2922 i
.disp_reloc
[this_operand
] = BFD_RELOC_386_GOT32
;
2926 as_bad (_("bad reloc specifier in expression"));
2928 /* Replace the relocation token with ' ', so that errors like
2929 foo@GOTOFF1 will be detected. */
2930 first
= cp
- input_line_pointer
;
2931 tmpbuf
= (char *) alloca (strlen (input_line_pointer
));
2932 memcpy (tmpbuf
, input_line_pointer
, first
);
2933 tmpbuf
[first
] = ' ';
2934 strcpy (tmpbuf
+ first
+ 1, cp
+ 1 + len
);
2935 input_line_pointer
= tmpbuf
;
2940 exp_seg
= expression (exp
);
2942 #ifdef BFD_ASSEMBLER
2943 /* We do this to make sure that the section symbol is in
2944 the symbol table. We will ultimately change the relocation
2945 to be relative to the beginning of the section. */
2946 if (i
.disp_reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
)
2948 if (S_IS_LOCAL(exp
->X_add_symbol
)
2949 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
2950 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
2951 assert (exp
->X_op
== O_symbol
);
2952 exp
->X_op
= O_subtract
;
2953 exp
->X_op_symbol
= GOT_symbol
;
2954 i
.disp_reloc
[this_operand
] = BFD_RELOC_32
;
2959 if (*input_line_pointer
)
2960 as_bad (_("ignoring junk `%s' after expression"),
2961 input_line_pointer
);
2963 RESTORE_END_STRING (disp_end
+ 1);
2965 RESTORE_END_STRING (disp_end
);
2966 input_line_pointer
= save_input_line_pointer
;
2968 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_big
)
2970 /* Missing or bad expr becomes absolute 0. */
2971 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2973 exp
->X_op
= O_constant
;
2974 exp
->X_add_number
= 0;
2975 exp
->X_add_symbol
= (symbolS
*) 0;
2976 exp
->X_op_symbol
= (symbolS
*) 0;
2979 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2980 if (exp
->X_op
!= O_constant
2981 #ifdef BFD_ASSEMBLER
2982 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
2984 && exp_seg
!= text_section
2985 && exp_seg
!= data_section
2986 && exp_seg
!= bss_section
2987 && exp_seg
!= undefined_section
)
2989 #ifdef BFD_ASSEMBLER
2990 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
2992 as_bad (_("unimplemented segment type %d in operand"), exp_seg
);
3000 static int i386_index_check
PARAMS((const char *));
3002 /* Make sure the memory operand we've been dealt is valid.
3003 Return 1 on success, 0 on a failure. */
3006 i386_index_check (operand_string
)
3007 const char *operand_string
;
3009 #if INFER_ADDR_PREFIX
3014 if (flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0)
3015 /* 16 bit mode checks. */
3017 && ((i
.base_reg
->reg_type
& (Reg16
|BaseIndex
))
3018 != (Reg16
|BaseIndex
)))
3020 && (((i
.index_reg
->reg_type
& (Reg16
|BaseIndex
))
3021 != (Reg16
|BaseIndex
))
3023 && i
.base_reg
->reg_num
< 6
3024 && i
.index_reg
->reg_num
>= 6
3025 && i
.log2_scale_factor
== 0))))
3026 /* 32 bit mode checks. */
3028 && (i
.base_reg
->reg_type
& Reg32
) == 0)
3030 && ((i
.index_reg
->reg_type
& (Reg32
|BaseIndex
))
3031 != (Reg32
|BaseIndex
)))))
3033 #if INFER_ADDR_PREFIX
3034 if (i
.prefix
[ADDR_PREFIX
] == 0 && stackop_size
!= '\0')
3036 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
3038 /* Change the size of any displacement too. At most one of
3039 Disp16 or Disp32 is set.
3040 FIXME. There doesn't seem to be any real need for separate
3041 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3042 Removing them would probably clean up the code quite a lot. */
3043 if (i
.types
[this_operand
] & (Disp16
|Disp32
))
3044 i
.types
[this_operand
] ^= (Disp16
|Disp32
);
3049 as_bad (_("`%s' is not a valid base/index expression"),
3053 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3055 flag_16bit_code
^ (i
.prefix
[ADDR_PREFIX
] != 0) ? "16" : "32");
3061 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3065 i386_operand (operand_string
)
3066 char *operand_string
;
3070 char *op_string
= operand_string
;
3072 if (is_space_char (*op_string
))
3075 /* We check for an absolute prefix (differentiating,
3076 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3077 if (*op_string
== ABSOLUTE_PREFIX
)
3080 if (is_space_char (*op_string
))
3082 i
.types
[this_operand
] |= JumpAbsolute
;
3085 /* Check if operand is a register. */
3086 if ((*op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3087 && (r
= parse_register (op_string
, &end_op
)) != NULL
)
3089 /* Check for a segment override by searching for ':' after a
3090 segment register. */
3092 if (is_space_char (*op_string
))
3094 if (*op_string
== ':' && (r
->reg_type
& (SReg2
| SReg3
)))
3099 i
.seg
[i
.mem_operands
] = &es
;
3102 i
.seg
[i
.mem_operands
] = &cs
;
3105 i
.seg
[i
.mem_operands
] = &ss
;
3108 i
.seg
[i
.mem_operands
] = &ds
;
3111 i
.seg
[i
.mem_operands
] = &fs
;
3114 i
.seg
[i
.mem_operands
] = &gs
;
3118 /* Skip the ':' and whitespace. */
3120 if (is_space_char (*op_string
))
3123 if (!is_digit_char (*op_string
)
3124 && !is_identifier_char (*op_string
)
3125 && *op_string
!= '('
3126 && *op_string
!= ABSOLUTE_PREFIX
)
3128 as_bad (_("bad memory operand `%s'"), op_string
);
3131 /* Handle case of %es:*foo. */
3132 if (*op_string
== ABSOLUTE_PREFIX
)
3135 if (is_space_char (*op_string
))
3137 i
.types
[this_operand
] |= JumpAbsolute
;
3139 goto do_memory_reference
;
3143 as_bad (_("junk `%s' after register"), op_string
);
3146 i
.types
[this_operand
] |= r
->reg_type
& ~BaseIndex
;
3147 i
.op
[this_operand
].regs
= r
;
3150 else if (*op_string
== REGISTER_PREFIX
)
3152 as_bad (_("bad register name `%s'"), op_string
);
3155 else if (*op_string
== IMMEDIATE_PREFIX
)
3158 if (i
.types
[this_operand
] & JumpAbsolute
)
3160 as_bad (_("immediate operand illegal with absolute jump"));
3163 if (!i386_immediate (op_string
))
3166 else if (is_digit_char (*op_string
)
3167 || is_identifier_char (*op_string
)
3168 || *op_string
== '(' )
3170 /* This is a memory reference of some sort. */
3173 /* Start and end of displacement string expression (if found). */
3174 char *displacement_string_start
;
3175 char *displacement_string_end
;
3177 do_memory_reference
:
3178 if ((i
.mem_operands
== 1
3179 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
3180 || i
.mem_operands
== 2)
3182 as_bad (_("too many memory references for `%s'"),
3183 current_templates
->start
->name
);
3187 /* Check for base index form. We detect the base index form by
3188 looking for an ')' at the end of the operand, searching
3189 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3191 base_string
= op_string
+ strlen (op_string
);
3194 if (is_space_char (*base_string
))
3197 /* If we only have a displacement, set-up for it to be parsed later. */
3198 displacement_string_start
= op_string
;
3199 displacement_string_end
= base_string
+ 1;
3201 if (*base_string
== ')')
3204 unsigned int parens_balanced
= 1;
3205 /* We've already checked that the number of left & right ()'s are
3206 equal, so this loop will not be infinite. */
3210 if (*base_string
== ')')
3212 if (*base_string
== '(')
3215 while (parens_balanced
);
3217 temp_string
= base_string
;
3219 /* Skip past '(' and whitespace. */
3221 if (is_space_char (*base_string
))
3224 if (*base_string
== ','
3225 || ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3226 && (i
.base_reg
= parse_register (base_string
, &end_op
)) != NULL
))
3228 displacement_string_end
= temp_string
;
3230 i
.types
[this_operand
] |= BaseIndex
;
3234 base_string
= end_op
;
3235 if (is_space_char (*base_string
))
3239 /* There may be an index reg or scale factor here. */
3240 if (*base_string
== ',')
3243 if (is_space_char (*base_string
))
3246 if ((*base_string
== REGISTER_PREFIX
|| allow_naked_reg
)
3247 && (i
.index_reg
= parse_register (base_string
, &end_op
)) != NULL
)
3249 base_string
= end_op
;
3250 if (is_space_char (*base_string
))
3252 if (*base_string
== ',')
3255 if (is_space_char (*base_string
))
3258 else if (*base_string
!= ')' )
3260 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3265 else if (*base_string
== REGISTER_PREFIX
)
3267 as_bad (_("bad register name `%s'"), base_string
);
3271 /* Check for scale factor. */
3272 if (isdigit ((unsigned char) *base_string
))
3274 if (!i386_scale (base_string
))
3278 if (is_space_char (*base_string
))
3280 if (*base_string
!= ')')
3282 as_bad (_("expecting `)' after scale factor in `%s'"),
3287 else if (!i
.index_reg
)
3289 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3294 else if (*base_string
!= ')')
3296 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3301 else if (*base_string
== REGISTER_PREFIX
)
3303 as_bad (_("bad register name `%s'"), base_string
);
3308 /* If there's an expression beginning the operand, parse it,
3309 assuming displacement_string_start and
3310 displacement_string_end are meaningful. */
3311 if (displacement_string_start
!= displacement_string_end
)
3313 if (!i386_displacement (displacement_string_start
,
3314 displacement_string_end
))
3318 /* Special case for (%dx) while doing input/output op. */
3320 && i
.base_reg
->reg_type
== (Reg16
| InOutPortReg
)
3322 && i
.log2_scale_factor
== 0
3323 && i
.seg
[i
.mem_operands
] == 0
3324 && (i
.types
[this_operand
] & Disp
) == 0)
3326 i
.types
[this_operand
] = InOutPortReg
;
3330 if (i386_index_check (operand_string
) == 0)
3336 /* It's not a memory operand; argh! */
3337 as_bad (_("invalid char %s beginning operand %d `%s'"),
3338 output_invalid (*op_string
),
3343 return 1; /* Normal return. */
3346 /* md_estimate_size_before_relax()
3348 Called just before relax() for rs_machine_dependent frags. The x86
3349 assembler uses these frags to handle variable size jump
3352 Any symbol that is now undefined will not become defined.
3353 Return the correct fr_subtype in the frag.
3354 Return the initial "guess for variable size of frag" to caller.
3355 The guess is actually the growth beyond the fixed part. Whatever
3356 we do to grow the fixed or variable part contributes to our
3360 md_estimate_size_before_relax (fragP
, segment
)
3361 register fragS
*fragP
;
3362 register segT segment
;
3364 /* We've already got fragP->fr_subtype right; all we have to do is
3365 check for un-relaxable symbols. On an ELF system, we can't relax
3366 an externally visible symbol, because it may be overridden by a
3368 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
3369 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3370 || S_IS_EXTERNAL (fragP
->fr_symbol
)
3371 || S_IS_WEAK (fragP
->fr_symbol
)
3375 /* Symbol is undefined in this segment, or we need to keep a
3376 reloc so that weak symbols can be overridden. */
3377 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
3378 #ifdef BFD_ASSEMBLER
3379 enum bfd_reloc_code_real reloc_type
;
3383 unsigned char *opcode
;
3386 if (fragP
->fr_var
!= NO_RELOC
)
3387 reloc_type
= fragP
->fr_var
;
3389 reloc_type
= BFD_RELOC_16_PCREL
;
3391 reloc_type
= BFD_RELOC_32_PCREL
;
3393 old_fr_fix
= fragP
->fr_fix
;
3394 opcode
= (unsigned char *) fragP
->fr_opcode
;
3398 case JUMP_PC_RELATIVE
:
3399 /* Make jmp (0xeb) a dword displacement jump. */
3401 fragP
->fr_fix
+= size
;
3402 fix_new (fragP
, old_fr_fix
, size
,
3404 fragP
->fr_offset
, 1,
3409 /* This changes the byte-displacement jump 0x7N
3410 to the dword-displacement jump 0x0f,0x8N. */
3411 opcode
[1] = opcode
[0] + 0x10;
3412 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3413 /* We've added an opcode byte. */
3414 fragP
->fr_fix
+= 1 + size
;
3415 fix_new (fragP
, old_fr_fix
+ 1, size
,
3417 fragP
->fr_offset
, 1,
3422 return fragP
->fr_fix
- old_fr_fix
;
3424 /* Guess a short jump. */
3428 /* Called after relax() is finished.
3430 In: Address of frag.
3431 fr_type == rs_machine_dependent.
3432 fr_subtype is what the address relaxed to.
3434 Out: Any fixSs and constants are set up.
3435 Caller will turn frag into a ".space 0". */
3437 #ifndef BFD_ASSEMBLER
3439 md_convert_frag (headers
, sec
, fragP
)
3440 object_headers
*headers ATTRIBUTE_UNUSED
;
3441 segT sec ATTRIBUTE_UNUSED
;
3442 register fragS
*fragP
;
3445 md_convert_frag (abfd
, sec
, fragP
)
3446 bfd
*abfd ATTRIBUTE_UNUSED
;
3447 segT sec ATTRIBUTE_UNUSED
;
3448 register fragS
*fragP
;
3451 register unsigned char *opcode
;
3452 unsigned char *where_to_put_displacement
= NULL
;
3453 offsetT target_address
;
3454 offsetT opcode_address
;
3455 unsigned int extension
= 0;
3456 offsetT displacement_from_opcode_start
;
3458 opcode
= (unsigned char *) fragP
->fr_opcode
;
3460 /* Address we want to reach in file space. */
3461 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
3462 #ifdef BFD_ASSEMBLER
3463 /* Not needed otherwise? */
3464 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
3467 /* Address opcode resides at in file space. */
3468 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
3470 /* Displacement from opcode start to fill into instruction. */
3471 displacement_from_opcode_start
= target_address
- opcode_address
;
3473 switch (fragP
->fr_subtype
)
3475 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL
):
3476 case ENCODE_RELAX_STATE (COND_JUMP
, SMALL16
):
3477 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
):
3478 case ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL16
):
3479 /* Don't have to change opcode. */
3480 extension
= 1; /* 1 opcode + 1 displacement */
3481 where_to_put_displacement
= &opcode
[1];
3484 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
3485 extension
= 5; /* 2 opcode + 4 displacement */
3486 opcode
[1] = opcode
[0] + 0x10;
3487 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3488 where_to_put_displacement
= &opcode
[2];
3491 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
3492 extension
= 4; /* 1 opcode + 4 displacement */
3494 where_to_put_displacement
= &opcode
[1];
3497 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
3498 extension
= 3; /* 2 opcode + 2 displacement */
3499 opcode
[1] = opcode
[0] + 0x10;
3500 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
3501 where_to_put_displacement
= &opcode
[2];
3504 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
3505 extension
= 2; /* 1 opcode + 2 displacement */
3507 where_to_put_displacement
= &opcode
[1];
3511 BAD_CASE (fragP
->fr_subtype
);
3514 /* Now put displacement after opcode. */
3515 md_number_to_chars ((char *) where_to_put_displacement
,
3516 (valueT
) (displacement_from_opcode_start
- extension
),
3517 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
3518 fragP
->fr_fix
+= extension
;
3521 /* Size of byte displacement jmp. */
3522 int md_short_jump_size
= 2;
3524 /* Size of dword displacement jmp. */
3525 int md_long_jump_size
= 5;
3527 /* Size of relocation record. */
3528 const int md_reloc_size
= 8;
3531 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3533 addressT from_addr
, to_addr
;
3534 fragS
*frag ATTRIBUTE_UNUSED
;
3535 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3539 offset
= to_addr
- (from_addr
+ 2);
3540 /* Opcode for byte-disp jump. */
3541 md_number_to_chars (ptr
, (valueT
) 0xeb, 1);
3542 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 1);
3546 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
3548 addressT from_addr
, to_addr
;
3549 fragS
*frag ATTRIBUTE_UNUSED
;
3550 symbolS
*to_symbol ATTRIBUTE_UNUSED
;
3554 offset
= to_addr
- (from_addr
+ 5);
3555 md_number_to_chars (ptr
, (valueT
) 0xe9, 1);
3556 md_number_to_chars (ptr
+ 1, (valueT
) offset
, 4);
3559 /* Apply a fixup (fixS) to segment data, once it has been determined
3560 by our caller that we have all the info we need to fix it up.
3562 On the 386, immediates, displacements, and data pointers are all in
3563 the same (little-endian) format, so we don't need to care about which
3567 md_apply_fix3 (fixP
, valp
, seg
)
3568 /* The fix we're to put in. */
3571 /* Pointer to the value of the bits. */
3574 /* Segment fix is from. */
3575 segT seg ATTRIBUTE_UNUSED
;
3577 register char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3578 valueT value
= *valp
;
3580 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
3583 switch (fixP
->fx_r_type
)
3589 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
3592 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
3595 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
3600 /* This is a hack. There should be a better way to handle this.
3601 This covers for the fact that bfd_install_relocation will
3602 subtract the current location (for partial_inplace, PC relative
3603 relocations); see more below. */
3604 if ((fixP
->fx_r_type
== BFD_RELOC_32_PCREL
3605 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
3606 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
3610 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3612 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
3615 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3617 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3618 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
3620 segT fseg
= S_GET_SEGMENT (fixP
->fx_addsy
);
3623 || (symbol_section_p (fixP
->fx_addsy
)
3624 && fseg
!= absolute_section
))
3625 && ! S_IS_EXTERNAL (fixP
->fx_addsy
)
3626 && ! S_IS_WEAK (fixP
->fx_addsy
)
3627 && S_IS_DEFINED (fixP
->fx_addsy
)
3628 && ! S_IS_COMMON (fixP
->fx_addsy
))
3630 /* Yes, we add the values in twice. This is because
3631 bfd_perform_relocation subtracts them out again. I think
3632 bfd_perform_relocation is broken, but I don't dare change
3634 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3638 #if defined (OBJ_COFF) && defined (TE_PE)
3639 /* For some reason, the PE format does not store a section
3640 address offset for a PC relative symbol. */
3641 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
3642 value
+= md_pcrel_from (fixP
);
3646 /* Fix a few things - the dynamic linker expects certain values here,
3647 and we must not dissappoint it. */
3648 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3649 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
3651 switch (fixP
->fx_r_type
)
3653 case BFD_RELOC_386_PLT32
:
3654 /* Make the jump instruction point to the address of the operand. At
3655 runtime we merely add the offset to the actual PLT entry. */
3658 case BFD_RELOC_386_GOTPC
:
3660 /* This is tough to explain. We end up with this one if we have
3661 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
3662 * here is to obtain the absolute address of the GOT, and it is strongly
3663 * preferable from a performance point of view to avoid using a runtime
3664 * relocation for this. The actual sequence of instructions often look
3670 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3672 * The call and pop essentially return the absolute address of
3673 * the label .L66 and store it in %ebx. The linker itself will
3674 * ultimately change the first operand of the addl so that %ebx points to
3675 * the GOT, but to keep things simple, the .o file must have this operand
3676 * set so that it generates not the absolute address of .L66, but the
3677 * absolute address of itself. This allows the linker itself simply
3678 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
3679 * added in, and the addend of the relocation is stored in the operand
3680 * field for the instruction itself.
3682 * Our job here is to fix the operand so that it would add the correct
3683 * offset so that %ebx would point to itself. The thing that is tricky is
3684 * that .-.L66 will point to the beginning of the instruction, so we need
3685 * to further modify the operand so that it will point to itself.
3686 * There are other cases where you have something like:
3688 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3690 * and here no correction would be required. Internally in the assembler
3691 * we treat operands of this form as not being pcrel since the '.' is
3692 * explicitly mentioned, and I wonder whether it would simplify matters
3693 * to do it this way. Who knows. In earlier versions of the PIC patches,
3694 * the pcrel_adjust field was used to store the correction, but since the
3695 * expression is not pcrel, I felt it would be confusing to do it this
3700 case BFD_RELOC_386_GOT32
:
3701 value
= 0; /* Fully resolved at runtime. No addend. */
3703 case BFD_RELOC_386_GOTOFF
:
3706 case BFD_RELOC_VTABLE_INHERIT
:
3707 case BFD_RELOC_VTABLE_ENTRY
:
3714 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
3716 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3717 md_number_to_chars (p
, value
, fixP
->fx_size
);
3722 #define MAX_LITTLENUMS 6
3724 /* Turn the string pointed to by litP into a floating point constant
3725 of type TYPE, and emit the appropriate bytes. The number of
3726 LITTLENUMS emitted is stored in *SIZEP. An error message is
3727 returned, or NULL on OK. */
3730 md_atof (type
, litP
, sizeP
)
3736 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3737 LITTLENUM_TYPE
*wordP
;
3759 return _("Bad call to md_atof ()");
3761 t
= atof_ieee (input_line_pointer
, type
, words
);
3763 input_line_pointer
= t
;
3765 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3766 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
3767 the bigendian 386. */
3768 for (wordP
= words
+ prec
- 1; prec
--;)
3770 md_number_to_chars (litP
, (valueT
) (*wordP
--), sizeof (LITTLENUM_TYPE
));
3771 litP
+= sizeof (LITTLENUM_TYPE
);
3776 char output_invalid_buf
[8];
3783 sprintf (output_invalid_buf
, "'%c'", c
);
3785 sprintf (output_invalid_buf
, "(0x%x)", (unsigned) c
);
3786 return output_invalid_buf
;
3789 /* REG_STRING starts *before* REGISTER_PREFIX. */
3791 static const reg_entry
*
3792 parse_register (reg_string
, end_op
)
3796 char *s
= reg_string
;
3798 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
3801 /* Skip possible REGISTER_PREFIX and possible whitespace. */
3802 if (*s
== REGISTER_PREFIX
)
3805 if (is_space_char (*s
))
3809 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
3811 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
3812 return (const reg_entry
*) NULL
;
3816 /* For naked regs, make sure that we are not dealing with an identifier.
3817 This prevents confusing an identifier like `eax_var' with register
3819 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
3820 return (const reg_entry
*) NULL
;
3824 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
3826 /* Handle floating point regs, allowing spaces in the (i) part. */
3827 if (r
== i386_regtab
/* %st is first entry of table */)
3829 if (is_space_char (*s
))
3834 if (is_space_char (*s
))
3836 if (*s
>= '0' && *s
<= '7')
3838 r
= &i386_float_regtab
[*s
- '0'];
3840 if (is_space_char (*s
))
3848 /* We have "%st(" then garbage. */
3849 return (const reg_entry
*) NULL
;
3856 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3857 const char *md_shortopts
= "kVQ:sq";
3859 const char *md_shortopts
= "q";
3861 struct option md_longopts
[] = {
3862 {NULL
, no_argument
, NULL
, 0}
3864 size_t md_longopts_size
= sizeof (md_longopts
);
3867 md_parse_option (c
, arg
)
3869 char *arg ATTRIBUTE_UNUSED
;
3877 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3878 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
3879 should be emitted or not. FIXME: Not implemented. */
3883 /* -V: SVR4 argument to print version ID. */
3885 print_version_id ();
3888 /* -k: Ignore for FreeBSD compatibility. */
3893 /* -s: On i386 Solaris, this tells the native assembler to use
3894 .stab instead of .stab.excl. We always use .stab anyhow. */
3905 md_show_usage (stream
)
3908 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3909 fprintf (stream
, _("\
3911 -V print assembler version number\n\
3913 -q quieten some warnings\n\
3916 fprintf (stream
, _("\
3917 -q quieten some warnings\n"));
3921 #ifdef BFD_ASSEMBLER
3922 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
3923 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
3924 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
3926 /* Pick the target format to use. */
3929 i386_target_format ()
3931 switch (OUTPUT_FLAVOR
)
3933 #ifdef OBJ_MAYBE_AOUT
3934 case bfd_target_aout_flavour
:
3935 return AOUT_TARGET_FORMAT
;
3937 #ifdef OBJ_MAYBE_COFF
3938 case bfd_target_coff_flavour
:
3941 #ifdef OBJ_MAYBE_ELF
3942 case bfd_target_elf_flavour
:
3943 return "elf32-i386";
3951 #endif /* OBJ_MAYBE_ more than one */
3952 #endif /* BFD_ASSEMBLER */
3955 md_undefined_symbol (name
)
3958 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
3959 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
3960 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
3961 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
3965 if (symbol_find (name
))
3966 as_bad (_("GOT already in symbol table"));
3967 GOT_symbol
= symbol_new (name
, undefined_section
,
3968 (valueT
) 0, &zero_address_frag
);
3975 /* Round up a section size to the appropriate boundary. */
3978 md_section_align (segment
, size
)
3979 segT segment ATTRIBUTE_UNUSED
;
3982 #ifdef BFD_ASSEMBLER
3983 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3984 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
3986 /* For a.out, force the section size to be aligned. If we don't do
3987 this, BFD will align it for us, but it will not write out the
3988 final bytes of the section. This may be a bug in BFD, but it is
3989 easier to fix it here since that is how the other a.out targets
3993 align
= bfd_get_section_alignment (stdoutput
, segment
);
3994 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
4002 /* On the i386, PC-relative offsets are relative to the start of the
4003 next instruction. That is, the address of the offset, plus its
4004 size, since the offset is always the last part of the insn. */
4007 md_pcrel_from (fixP
)
4010 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4017 int ignore ATTRIBUTE_UNUSED
;
4021 temp
= get_absolute_expression ();
4022 subseg_set (bss_section
, (subsegT
) temp
);
4023 demand_empty_rest_of_line ();
4028 #ifdef BFD_ASSEMBLER
4031 i386_validate_fix (fixp
)
4034 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
4036 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
4042 tc_gen_reloc (section
, fixp
)
4043 asection
*section ATTRIBUTE_UNUSED
;
4047 bfd_reloc_code_real_type code
;
4049 switch (fixp
->fx_r_type
)
4051 case BFD_RELOC_386_PLT32
:
4052 case BFD_RELOC_386_GOT32
:
4053 case BFD_RELOC_386_GOTOFF
:
4054 case BFD_RELOC_386_GOTPC
:
4056 case BFD_RELOC_VTABLE_ENTRY
:
4057 case BFD_RELOC_VTABLE_INHERIT
:
4058 code
= fixp
->fx_r_type
;
4063 switch (fixp
->fx_size
)
4066 as_bad (_("can not do %d byte pc-relative relocation"),
4068 code
= BFD_RELOC_32_PCREL
;
4070 case 1: code
= BFD_RELOC_8_PCREL
; break;
4071 case 2: code
= BFD_RELOC_16_PCREL
; break;
4072 case 4: code
= BFD_RELOC_32_PCREL
; break;
4077 switch (fixp
->fx_size
)
4080 as_bad (_("can not do %d byte relocation"), fixp
->fx_size
);
4081 code
= BFD_RELOC_32
;
4083 case 1: code
= BFD_RELOC_8
; break;
4084 case 2: code
= BFD_RELOC_16
; break;
4085 case 4: code
= BFD_RELOC_32
; break;
4091 if (code
== BFD_RELOC_32
4093 && fixp
->fx_addsy
== GOT_symbol
)
4094 code
= BFD_RELOC_386_GOTPC
;
4096 rel
= (arelent
*) xmalloc (sizeof (arelent
));
4097 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
4098 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
4100 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4101 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4102 vtable entry to be used in the relocation's section offset. */
4103 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4104 rel
->address
= fixp
->fx_offset
;
4107 rel
->addend
= fixp
->fx_addnumber
;
4111 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
4112 if (rel
->howto
== NULL
)
4114 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
4115 _("cannot represent relocation type %s"),
4116 bfd_get_reloc_code_name (code
));
4117 /* Set howto to a garbage value so that we can keep going. */
4118 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
4119 assert (rel
->howto
!= NULL
);
4125 #else /* ! BFD_ASSEMBLER */
4127 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4129 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4132 relax_addressT segment_address_in_file
;
4134 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
4135 Out: GNU LD relocation length code: 0, 1, or 2. */
4137 static const unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
4140 know (fixP
->fx_addsy
!= NULL
);
4142 md_number_to_chars (where
,
4143 (valueT
) (fixP
->fx_frag
->fr_address
4144 + fixP
->fx_where
- segment_address_in_file
),
4147 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4148 ? S_GET_TYPE (fixP
->fx_addsy
)
4149 : fixP
->fx_addsy
->sy_number
);
4151 where
[6] = (r_symbolnum
>> 16) & 0x0ff;
4152 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4153 where
[4] = r_symbolnum
& 0x0ff;
4154 where
[7] = ((((!S_IS_DEFINED (fixP
->fx_addsy
)) << 3) & 0x08)
4155 | ((nbytes_r_length
[fixP
->fx_size
] << 1) & 0x06)
4156 | (((fixP
->fx_pcrel
<< 0) & 0x01) & 0x0f));
4159 #endif /* OBJ_AOUT or OBJ_BOUT. */
4161 #if defined (I386COFF)
4164 tc_coff_fix2rtype (fixP
)
4167 if (fixP
->fx_r_type
== R_IMAGEBASE
)
4170 return (fixP
->fx_pcrel
?
4171 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
4172 fixP
->fx_size
== 2 ? R_PCRWORD
:
4174 (fixP
->fx_size
== 1 ? R_RELBYTE
:
4175 fixP
->fx_size
== 2 ? R_RELWORD
:
4180 tc_coff_sizemachdep (frag
)
4184 return (frag
->fr_next
->fr_address
- frag
->fr_address
);
4189 #endif /* I386COFF */
4191 #endif /* ! BFD_ASSEMBLER */
4193 /* Parse operands using Intel syntax. This implements a recursive descent
4194 parser based on the BNF grammar published in Appendix B of the MASM 6.1
4197 FIXME: We do not recognize the full operand grammar defined in the MASM
4198 documentation. In particular, all the structure/union and
4199 high-level macro operands are missing.
4201 Uppercase words are terminals, lower case words are non-terminals.
4202 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
4203 bars '|' denote choices. Most grammar productions are implemented in
4204 functions called 'intel_<production>'.
4206 Initial production is 'expr'.
4212 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
4214 constant digits [[ radixOverride ]]
4216 dataType BYTE | WORD | DWORD | QWORD | XWORD
4249 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
4250 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
4252 hexdigit a | b | c | d | e | f
4253 | A | B | C | D | E | F
4263 register specialRegister
4267 segmentRegister CS | DS | ES | FS | GS | SS
4269 specialRegister CR0 | CR2 | CR3
4270 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
4271 | TR3 | TR4 | TR5 | TR6 | TR7
4273 We simplify the grammar in obvious places (e.g., register parsing is
4274 done by calling parse_register) and eliminate immediate left recursion
4275 to implement a recursive-descent parser.
4315 /* Parsing structure for the intel syntax parser. Used to implement the
4316 semantic actions for the operand grammar. */
4317 struct intel_parser_s
4319 char *op_string
; /* The string being parsed. */
4320 int got_a_float
; /* Whether the operand is a float. */
4321 int op_modifier
; /* Operand modifier. */
4322 int is_mem
; /* 1 if operand is memory reference. */
4323 const reg_entry
*reg
; /* Last register reference found. */
4324 char *disp
; /* Displacement string being built. */
4327 static struct intel_parser_s intel_parser
;
4329 /* Token structure for parsing intel syntax. */
4332 int code
; /* Token code. */
4333 const reg_entry
*reg
; /* Register entry for register tokens. */
4334 char *str
; /* String representation. */
4337 static struct intel_token cur_token
, prev_token
;
4340 /* Token codes for the intel parser. Since T_SHORT is already used
4341 by COFF, undefine it first to prevent a warning. */
4356 /* Prototypes for intel parser functions. */
4357 static int intel_match_token
PARAMS ((int code
));
4358 static void intel_get_token
PARAMS ((void));
4359 static void intel_putback_token
PARAMS ((void));
4360 static int intel_expr
PARAMS ((void));
4361 static int intel_e05
PARAMS ((void));
4362 static int intel_e05_1
PARAMS ((void));
4363 static int intel_e06
PARAMS ((void));
4364 static int intel_e06_1
PARAMS ((void));
4365 static int intel_e09
PARAMS ((void));
4366 static int intel_e09_1
PARAMS ((void));
4367 static int intel_e10
PARAMS ((void));
4368 static int intel_e10_1
PARAMS ((void));
4369 static int intel_e11
PARAMS ((void));
4372 i386_intel_operand (operand_string
, got_a_float
)
4373 char *operand_string
;
4379 /* Initialize token holders. */
4380 cur_token
.code
= prev_token
.code
= T_NIL
;
4381 cur_token
.reg
= prev_token
.reg
= NULL
;
4382 cur_token
.str
= prev_token
.str
= NULL
;
4384 /* Initialize parser structure. */
4385 p
= intel_parser
.op_string
= (char *)malloc (strlen (operand_string
) + 1);
4388 strcpy (intel_parser
.op_string
, operand_string
);
4389 intel_parser
.got_a_float
= got_a_float
;
4390 intel_parser
.op_modifier
= -1;
4391 intel_parser
.is_mem
= 0;
4392 intel_parser
.reg
= NULL
;
4393 intel_parser
.disp
= (char *)malloc (strlen (operand_string
) + 1);
4394 if (intel_parser
.disp
== NULL
)
4396 intel_parser
.disp
[0] = '\0';
4398 /* Read the first token and start the parser. */
4400 ret
= intel_expr ();
4404 /* If we found a memory reference, hand it over to i386_displacement
4405 to fill in the rest of the operand fields. */
4406 if (intel_parser
.is_mem
)
4408 if ((i
.mem_operands
== 1
4409 && (current_templates
->start
->opcode_modifier
& IsString
) == 0)
4410 || i
.mem_operands
== 2)
4412 as_bad (_("too many memory references for '%s'"),
4413 current_templates
->start
->name
);
4418 char *s
= intel_parser
.disp
;
4421 /* Add the displacement expression. */
4423 ret
= i386_displacement (s
, s
+ strlen (s
))
4424 && i386_index_check (s
);
4428 /* Constant and OFFSET expressions are handled by i386_immediate. */
4429 else if (intel_parser
.op_modifier
== OFFSET_FLAT
4430 || intel_parser
.reg
== NULL
)
4431 ret
= i386_immediate (intel_parser
.disp
);
4435 free (intel_parser
.disp
);
4445 /* expr SHORT e05 */
4446 if (cur_token
.code
== T_SHORT
)
4448 intel_parser
.op_modifier
= SHORT
;
4449 intel_match_token (T_SHORT
);
4451 return (intel_e05 ());
4456 return intel_e05 ();
4466 return (intel_e06 () && intel_e05_1 ());
4472 /* e05' addOp e06 e05' */
4473 if (cur_token
.code
== '+' || cur_token
.code
== '-')
4475 strcat (intel_parser
.disp
, cur_token
.str
);
4476 intel_match_token (cur_token
.code
);
4478 return (intel_e06 () && intel_e05_1 ());
4493 return (intel_e09 () && intel_e06_1 ());
4499 /* e06' mulOp e09 e06' */
4500 if (cur_token
.code
== '*' || cur_token
.code
== '/')
4502 strcat (intel_parser
.disp
, cur_token
.str
);
4503 intel_match_token (cur_token
.code
);
4505 return (intel_e09 () && intel_e06_1 ());
4513 /* e09 OFFSET e10 e09'
4522 /* e09 OFFSET e10 e09' */
4523 if (cur_token
.code
== T_OFFSET
)
4525 intel_parser
.is_mem
= 0;
4526 intel_parser
.op_modifier
= OFFSET_FLAT
;
4527 intel_match_token (T_OFFSET
);
4529 return (intel_e10 () && intel_e09_1 ());
4534 return (intel_e10 () && intel_e09_1 ());
4540 /* e09' PTR e10 e09' */
4541 if (cur_token
.code
== T_PTR
)
4543 if (prev_token
.code
== T_BYTE
)
4544 i
.suffix
= BYTE_MNEM_SUFFIX
;
4546 else if (prev_token
.code
== T_WORD
)
4548 if (intel_parser
.got_a_float
== 2) /* "fi..." */
4549 i
.suffix
= SHORT_MNEM_SUFFIX
;
4551 i
.suffix
= WORD_MNEM_SUFFIX
;
4554 else if (prev_token
.code
== T_DWORD
)
4556 if (intel_parser
.got_a_float
== 1) /* "f..." */
4557 i
.suffix
= SHORT_MNEM_SUFFIX
;
4559 i
.suffix
= LONG_MNEM_SUFFIX
;
4562 else if (prev_token
.code
== T_QWORD
)
4564 if (intel_parser
.got_a_float
== 1) /* "f..." */
4565 i
.suffix
= LONG_MNEM_SUFFIX
;
4568 as_bad (_("operand modifier `%s' supported only for i387 operations\n"),
4574 else if (prev_token
.code
== T_XWORD
)
4575 i
.suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
4579 as_bad (_("Unknown operand modifier `%s'\n"), prev_token
.str
);
4583 intel_match_token (T_PTR
);
4585 return (intel_e10 () && intel_e09_1 ());
4588 /* e09 : e10 e09' */
4589 else if (cur_token
.code
== ':')
4591 intel_parser
.is_mem
= 1;
4593 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
4608 return (intel_e11 () && intel_e10_1 ());
4614 /* e10' [ expr ] e10' */
4615 if (cur_token
.code
== '[')
4617 intel_match_token ('[');
4618 intel_parser
.is_mem
= 1;
4620 /* Add a '+' to the displacement string if necessary. */
4621 if (*intel_parser
.disp
!= '\0')
4622 strcat (intel_parser
.disp
, "+");
4624 return (intel_expr () && intel_match_token (']') && intel_e10_1 ());
4648 if (cur_token
.code
== '(')
4650 intel_match_token ('(');
4651 strcat (intel_parser
.disp
, "(");
4653 if (intel_expr () && intel_match_token (')'))
4655 strcat (intel_parser
.disp
, ")");
4663 else if (cur_token
.code
== '[')
4665 intel_match_token ('[');
4666 intel_parser
.is_mem
= 1;
4668 /* Operands for jump/call inside brackets denote absolute addresses. */
4669 if (current_templates
->start
->opcode_modifier
& Jump
4670 || current_templates
->start
->opcode_modifier
& JumpDword
4671 || current_templates
->start
->opcode_modifier
& JumpByte
4672 || current_templates
->start
->opcode_modifier
& JumpInterSegment
)
4673 i
.types
[this_operand
] |= JumpAbsolute
;
4675 /* Add a '+' to the displacement string if necessary. */
4676 if (*intel_parser
.disp
!= '\0')
4677 strcat (intel_parser
.disp
, "+");
4679 return (intel_expr () && intel_match_token (']'));
4687 else if (cur_token
.code
== T_BYTE
4688 || cur_token
.code
== T_WORD
4689 || cur_token
.code
== T_DWORD
4690 || cur_token
.code
== T_QWORD
4691 || cur_token
.code
== T_XWORD
)
4693 intel_match_token (cur_token
.code
);
4700 else if (cur_token
.code
== '$' || cur_token
.code
== '.')
4702 strcat (intel_parser
.disp
, cur_token
.str
);
4703 intel_match_token (cur_token
.code
);
4704 intel_parser
.is_mem
= 1;
4710 else if (cur_token
.code
== T_REG
)
4712 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
4714 intel_match_token (T_REG
);
4716 /* Check for segment change. */
4717 if (cur_token
.code
== ':')
4719 if (reg
->reg_type
& (SReg2
| SReg3
))
4721 switch (reg
->reg_num
)
4724 i
.seg
[i
.mem_operands
] = &es
;
4727 i
.seg
[i
.mem_operands
] = &cs
;
4730 i
.seg
[i
.mem_operands
] = &ss
;
4733 i
.seg
[i
.mem_operands
] = &ds
;
4736 i
.seg
[i
.mem_operands
] = &fs
;
4739 i
.seg
[i
.mem_operands
] = &gs
;
4745 as_bad (_("`%s' is not a valid segment register"), reg
->reg_name
);
4750 /* Not a segment register. Check for register scaling. */
4751 else if (cur_token
.code
== '*')
4753 if (!intel_parser
.is_mem
)
4755 as_bad (_("Register scaling only allowed in memory operands."));
4759 /* What follows must be a valid scale. */
4760 if (intel_match_token ('*')
4761 && strchr ("01248", *cur_token
.str
))
4764 i
.types
[this_operand
] |= BaseIndex
;
4766 /* Set the scale after setting the register (otherwise,
4767 i386_scale will complain) */
4768 i386_scale (cur_token
.str
);
4769 intel_match_token (T_CONST
);
4773 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4779 /* No scaling. If this is a memory operand, the register is either a
4780 base register (first occurrence) or an index register (second
4782 else if (intel_parser
.is_mem
&& !(reg
->reg_type
& (SReg2
| SReg3
)))
4784 if (i
.base_reg
&& i
.index_reg
)
4786 as_bad (_("Too many register references in memory operand.\n"));
4790 if (i
.base_reg
== NULL
)
4795 i
.types
[this_operand
] |= BaseIndex
;
4798 /* Offset modifier. Add the register to the displacement string to be
4799 parsed as an immediate expression after we're done. */
4800 else if (intel_parser
.op_modifier
== OFFSET_FLAT
)
4801 strcat (intel_parser
.disp
, reg
->reg_name
);
4803 /* It's neither base nor index nor offset. */
4806 i
.types
[this_operand
] |= reg
->reg_type
& ~BaseIndex
;
4807 i
.op
[this_operand
].regs
= reg
;
4811 /* Since registers are not part of the displacement string (except
4812 when we're parsing offset operands), we may need to remove any
4813 preceding '+' from the displacement string. */
4814 if (*intel_parser
.disp
!= '\0'
4815 && intel_parser
.op_modifier
!= OFFSET_FLAT
)
4817 char *s
= intel_parser
.disp
;
4818 s
+= strlen (s
) - 1;
4827 else if (cur_token
.code
== T_ID
)
4829 /* Add the identifier to the displacement string. */
4830 strcat (intel_parser
.disp
, cur_token
.str
);
4831 intel_match_token (T_ID
);
4833 /* The identifier represents a memory reference only if it's not
4834 preceded by an offset modifier. */
4835 if (intel_parser
.op_modifier
!= OFFSET_FLAT
4836 && intel_parser
.op_modifier
!= FLAT
)
4837 intel_parser
.is_mem
= 1;
4843 else if (cur_token
.code
== T_CONST
4844 || cur_token
.code
== '-'
4845 || cur_token
.code
== '+')
4849 /* Allow constants that start with `+' or `-'. */
4850 if (cur_token
.code
== '-' || cur_token
.code
== '+')
4852 strcat (intel_parser
.disp
, cur_token
.str
);
4853 intel_match_token (cur_token
.code
);
4854 if (cur_token
.code
!= T_CONST
)
4856 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
4862 save_str
= (char *)malloc (strlen (cur_token
.str
) + 1);
4863 if (save_str
== NULL
)
4865 strcpy (save_str
, cur_token
.str
);
4867 /* Get the next token to check for register scaling. */
4868 intel_match_token (cur_token
.code
);
4870 /* Check if this constant is a scaling factor for an index register. */
4871 if (cur_token
.code
== '*')
4873 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
4875 if (!intel_parser
.is_mem
)
4877 as_bad (_("Register scaling only allowed in memory operands."));
4881 /* The constant is followed by `* reg', so it must be
4883 if (strchr ("01248", *save_str
))
4885 i
.index_reg
= cur_token
.reg
;
4886 i
.types
[this_operand
] |= BaseIndex
;
4888 /* Set the scale after setting the register (otherwise,
4889 i386_scale will complain) */
4890 i386_scale (save_str
);
4891 intel_match_token (T_REG
);
4893 /* Since registers are not part of the displacement
4894 string, we may need to remove any preceding '+' from
4895 the displacement string. */
4896 if (*intel_parser
.disp
!= '\0')
4898 char *s
= intel_parser
.disp
;
4899 s
+= strlen (s
) - 1;
4912 /* The constant was not used for register scaling. Since we have
4913 already consumed the token following `*' we now need to put it
4914 back in the stream. */
4916 intel_putback_token ();
4919 /* Add the constant to the displacement string. */
4920 strcat (intel_parser
.disp
, save_str
);
4926 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
4930 /* Match the given token against cur_token. If they match, read the next
4931 token from the operand string. */
4933 intel_match_token (code
)
4936 if (cur_token
.code
== code
)
4943 as_bad (_("Unexpected token `%s'\n"), cur_token
.str
);
4948 /* Read a new token from intel_parser.op_string and store it in cur_token. */
4953 const reg_entry
*reg
;
4954 struct intel_token new_token
;
4956 new_token
.code
= T_NIL
;
4957 new_token
.reg
= NULL
;
4958 new_token
.str
= NULL
;
4960 /* Free the memory allocated to the previous token and move
4961 cur_token to prev_token. */
4963 free (prev_token
.str
);
4965 prev_token
= cur_token
;
4967 /* Skip whitespace. */
4968 while (is_space_char (*intel_parser
.op_string
))
4969 intel_parser
.op_string
++;
4971 /* Return an empty token if we find nothing else on the line. */
4972 if (*intel_parser
.op_string
== '\0')
4974 cur_token
= new_token
;
4978 /* The new token cannot be larger than the remainder of the operand
4980 new_token
.str
= (char *)malloc (strlen (intel_parser
.op_string
) + 1);
4981 if (new_token
.str
== NULL
)
4983 new_token
.str
[0] = '\0';
4985 if (strchr ("0123456789", *intel_parser
.op_string
))
4987 char *p
= new_token
.str
;
4988 char *q
= intel_parser
.op_string
;
4989 new_token
.code
= T_CONST
;
4991 /* Allow any kind of identifier char to encompass floating point and
4992 hexadecimal numbers. */
4993 while (is_identifier_char (*q
))
4997 /* Recognize special symbol names [0-9][bf]. */
4998 if (strlen (intel_parser
.op_string
) == 2
4999 && (intel_parser
.op_string
[1] == 'b'
5000 || intel_parser
.op_string
[1] == 'f'))
5001 new_token
.code
= T_ID
;
5004 else if (strchr ("+-/*:[]()", *intel_parser
.op_string
))
5006 new_token
.code
= *intel_parser
.op_string
;
5007 new_token
.str
[0] = *intel_parser
.op_string
;
5008 new_token
.str
[1] = '\0';
5011 else if ((*intel_parser
.op_string
== REGISTER_PREFIX
|| allow_naked_reg
)
5012 && ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
))
5014 new_token
.code
= T_REG
;
5015 new_token
.reg
= reg
;
5017 if (*intel_parser
.op_string
== REGISTER_PREFIX
)
5019 new_token
.str
[0] = REGISTER_PREFIX
;
5020 new_token
.str
[1] = '\0';
5023 strcat (new_token
.str
, reg
->reg_name
);
5026 else if (is_identifier_char (*intel_parser
.op_string
))
5028 char *p
= new_token
.str
;
5029 char *q
= intel_parser
.op_string
;
5031 /* A '.' or '$' followed by an identifier char is an identifier.
5032 Otherwise, it's operator '.' followed by an expression. */
5033 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
5035 new_token
.code
= *q
;
5036 new_token
.str
[0] = *q
;
5037 new_token
.str
[1] = '\0';
5041 while (is_identifier_char (*q
) || *q
== '@')
5045 if (strcasecmp (new_token
.str
, "BYTE") == 0)
5046 new_token
.code
= T_BYTE
;
5048 else if (strcasecmp (new_token
.str
, "WORD") == 0)
5049 new_token
.code
= T_WORD
;
5051 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
5052 new_token
.code
= T_DWORD
;
5054 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
5055 new_token
.code
= T_QWORD
;
5057 else if (strcasecmp (new_token
.str
, "XWORD") == 0)
5058 new_token
.code
= T_XWORD
;
5060 else if (strcasecmp (new_token
.str
, "PTR") == 0)
5061 new_token
.code
= T_PTR
;
5063 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
5064 new_token
.code
= T_SHORT
;
5066 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
5068 new_token
.code
= T_OFFSET
;
5070 /* ??? This is not mentioned in the MASM grammar but gcc
5071 makes use of it with -mintel-syntax. OFFSET may be
5072 followed by FLAT: */
5073 if (strncasecmp (q
, " FLAT:", 6) == 0)
5074 strcat (new_token
.str
, " FLAT:");
5077 /* ??? This is not mentioned in the MASM grammar. */
5078 else if (strcasecmp (new_token
.str
, "FLAT") == 0)
5079 new_token
.code
= T_OFFSET
;
5082 new_token
.code
= T_ID
;
5087 as_bad (_("Unrecognized token `%s'\n"), intel_parser
.op_string
);
5089 intel_parser
.op_string
+= strlen (new_token
.str
);
5090 cur_token
= new_token
;
5093 /* Put cur_token back into the token stream and make cur_token point to
5096 intel_putback_token ()
5098 intel_parser
.op_string
-= strlen (cur_token
.str
);
5099 free (cur_token
.str
);
5100 cur_token
= prev_token
;
5102 /* Forget prev_token. */
5103 prev_token
.code
= T_NIL
;
5104 prev_token
.reg
= NULL
;
5105 prev_token
.str
= NULL
;