1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2023 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "gen-sframe.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37 #include "opcodes/i386-mnem.h"
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
85 #define END_OF_INSN '\0'
87 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
89 /* This matches the C -> StaticRounding alias in the opcode table. */
90 #define commutative staticrounding
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
:8; /* arch string length */
132 bool skip
:1; /* show_arch should skip this. */
133 enum processor_type type
; /* arch type */
134 enum { vsz_none
, vsz_set
, vsz_reset
} vsz
; /* vector size control */
135 i386_cpu_flags enable
; /* cpu feature enable flags */
136 i386_cpu_flags disable
; /* cpu feature disable flags */
140 static void update_code_flag (int, int);
141 static void s_insn (int);
142 static void set_code_flag (int);
143 static void set_16bit_gcc_code_flag (int);
144 static void set_intel_syntax (int);
145 static void set_intel_mnemonic (int);
146 static void set_allow_index_reg (int);
147 static void set_check (int);
148 static void set_cpu_arch (int);
150 static void pe_directive_secrel (int);
151 static void pe_directive_secidx (int);
153 static void signed_cons (int);
154 static char *output_invalid (int c
);
155 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
157 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
159 static int i386_att_operand (char *);
160 static int i386_intel_operand (char *, int);
161 static int i386_intel_simplify (expressionS
*);
162 static int i386_intel_parse_name (const char *, expressionS
*);
163 static const reg_entry
*parse_register (const char *, char **);
164 static const char *parse_insn (const char *, char *, bool);
165 static char *parse_operands (char *, const char *);
166 static void swap_operands (void);
167 static void swap_2_operands (unsigned int, unsigned int);
168 static enum flag_code
i386_addressing_mode (void);
169 static void optimize_imm (void);
170 static bool optimize_disp (const insn_template
*t
);
171 static const insn_template
*match_template (char);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const reg_entry
*build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS
*, offsetT
);
183 static void output_disp (fragS
*, offsetT
);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
190 /* GNU_PROPERTY_X86_ISA_1_USED. */
191 static unsigned int x86_isa_1_used
;
192 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
193 static unsigned int x86_feature_2_used
;
194 /* Generate x86 used ISA and feature properties. */
195 static unsigned int x86_used_note
= DEFAULT_X86_USED_NOTE
;
198 static const char *default_arch
= DEFAULT_ARCH
;
200 /* parse_register() returns this when a register alias cannot be used. */
201 static const reg_entry bad_reg
= { "<bad>", OPERAND_TYPE_NONE
, 0, 0,
202 { Dw2Inval
, Dw2Inval
} };
204 static const reg_entry
*reg_eax
;
205 static const reg_entry
*reg_ds
;
206 static const reg_entry
*reg_es
;
207 static const reg_entry
*reg_ss
;
208 static const reg_entry
*reg_st0
;
209 static const reg_entry
*reg_k0
;
214 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
215 unsigned char bytes
[4];
217 /* Destination or source register specifier. */
218 const reg_entry
*register_specifier
;
221 /* 'md_assemble ()' gathers together information and puts it into a
228 const reg_entry
*regs
;
233 no_error
, /* Must be first. */
234 operand_size_mismatch
,
235 operand_type_mismatch
,
236 register_type_mismatch
,
237 number_of_operands_mismatch
,
238 invalid_instruction_suffix
,
240 unsupported_with_intel_mnemonic
,
246 invalid_vsib_address
,
247 invalid_vector_register_set
,
248 invalid_tmm_register_set
,
249 invalid_dest_and_src_register_set
,
250 unsupported_vector_index_register
,
251 unsupported_broadcast
,
254 mask_not_on_destination
,
257 invalid_register_operand
,
262 /* TM holds the template for the insn were currently assembling. */
265 /* SUFFIX holds the instruction size suffix for byte, word, dword
266 or qword, if given. */
269 /* OPCODE_LENGTH holds the number of base opcode bytes. */
270 unsigned char opcode_length
;
272 /* OPERANDS gives the number of given operands. */
273 unsigned int operands
;
275 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
276 of given register, displacement, memory operands and immediate
278 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
280 /* TYPES [i] is the type (see above #defines) which tells us how to
281 use OP[i] for the corresponding operand. */
282 i386_operand_type types
[MAX_OPERANDS
];
284 /* Displacement expression, immediate expression, or register for each
286 union i386_op op
[MAX_OPERANDS
];
288 /* Flags for operands. */
289 unsigned int flags
[MAX_OPERANDS
];
290 #define Operand_PCrel 1
291 #define Operand_Mem 2
292 #define Operand_Signed 4 /* .insn only */
294 /* Relocation type for operand */
295 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
297 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
298 the base index byte below. */
299 const reg_entry
*base_reg
;
300 const reg_entry
*index_reg
;
301 unsigned int log2_scale_factor
;
303 /* SEG gives the seg_entries of this insn. They are zero unless
304 explicit segment overrides are given. */
305 const reg_entry
*seg
[2];
307 /* PREFIX holds all the given prefix opcodes (usually null).
308 PREFIXES is the number of prefix opcodes. */
309 unsigned int prefixes
;
310 unsigned char prefix
[MAX_PREFIXES
];
312 /* .insn allows for reserved opcode spaces. */
313 unsigned char insn_opcode_space
;
315 /* .insn also allows (requires) specifying immediate size. */
316 unsigned char imm_bits
[MAX_OPERANDS
];
318 /* Register is in low 3 bits of opcode. */
321 /* The operand to a branch insn indicates an absolute branch. */
324 /* The operand to a branch insn indicates a far branch. */
327 /* There is a memory operand of (%dx) which should be only used
328 with input/output instructions. */
329 bool input_output_operand
;
331 /* Extended states. */
339 xstate_ymm
= 1 << 2 | xstate_xmm
,
341 xstate_zmm
= 1 << 3 | xstate_ymm
,
344 /* Use MASK state. */
348 /* Has GOTPC or TLS relocation. */
349 bool has_gotpc_tls_reloc
;
351 /* RM and SIB are the modrm byte and the sib byte where the
352 addressing modes of this insn are encoded. */
359 /* Masking attributes.
361 The struct describes masking, applied to OPERAND in the instruction.
362 REG is a pointer to the corresponding mask register. ZEROING tells
363 whether merging or zeroing mask is used. */
364 struct Mask_Operation
366 const reg_entry
*reg
;
367 unsigned int zeroing
;
368 /* The operand where this operation is associated. */
369 unsigned int operand
;
372 /* Rounding control and SAE attributes. */
384 /* In Intel syntax the operand modifier form is supposed to be used, but
385 we continue to accept the immediate forms as well. */
389 /* Broadcasting attributes.
391 The struct describes broadcasting, applied to OPERAND. TYPE is
392 expresses the broadcast factor. */
393 struct Broadcast_Operation
395 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
398 /* Index of broadcasted operand. */
399 unsigned int operand
;
401 /* Number of bytes to broadcast. */
405 /* Compressed disp8*N attribute. */
406 unsigned int memshift
;
408 /* Prefer load or store in encoding. */
411 dir_encoding_default
= 0,
417 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
420 disp_encoding_default
= 0,
426 /* Prefer the REX byte in encoding. */
429 /* Disable instruction size optimization. */
432 /* How to encode vector instructions. */
435 vex_encoding_default
= 0,
443 const char *rep_prefix
;
446 const char *hle_prefix
;
448 /* Have BND prefix. */
449 const char *bnd_prefix
;
451 /* Have NOTRACK prefix. */
452 const char *notrack_prefix
;
455 enum i386_error error
;
458 typedef struct _i386_insn i386_insn
;
460 /* Link RC type with corresponding string, that'll be looked for in
469 static const struct RC_name RC_NamesTable
[] =
471 { rne
, STRING_COMMA_LEN ("rn-sae") },
472 { rd
, STRING_COMMA_LEN ("rd-sae") },
473 { ru
, STRING_COMMA_LEN ("ru-sae") },
474 { rz
, STRING_COMMA_LEN ("rz-sae") },
475 { saeonly
, STRING_COMMA_LEN ("sae") },
478 /* To be indexed by segment register number. */
479 static const unsigned char i386_seg_prefixes
[] = {
488 /* List of chars besides those in app.c:symbol_chars that can start an
489 operand. Used to prevent the scrubber eating vital white-space. */
490 const char extra_symbol_chars
[] = "*%-([{}"
499 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
500 && !defined (TE_GNU) \
501 && !defined (TE_LINUX) \
502 && !defined (TE_Haiku) \
503 && !defined (TE_FreeBSD) \
504 && !defined (TE_DragonFly) \
505 && !defined (TE_NetBSD))
506 /* This array holds the chars that always start a comment. If the
507 pre-processor is disabled, these aren't very useful. The option
508 --divide will remove '/' from this list. */
509 const char *i386_comment_chars
= "#/";
510 #define SVR4_COMMENT_CHARS 1
511 #define PREFIX_SEPARATOR '\\'
514 const char *i386_comment_chars
= "#";
515 #define PREFIX_SEPARATOR '/'
518 /* This array holds the chars that only start a comment at the beginning of
519 a line. If the line seems to have the form '# 123 filename'
520 .line and .file directives will appear in the pre-processed output.
521 Note that input_file.c hand checks for '#' at the beginning of the
522 first line of the input file. This is because the compiler outputs
523 #NO_APP at the beginning of its output.
524 Also note that comments started like this one will always work if
525 '/' isn't otherwise defined. */
526 const char line_comment_chars
[] = "#/";
528 const char line_separator_chars
[] = ";";
530 /* Chars that can be used to separate mant from exp in floating point
532 const char EXP_CHARS
[] = "eE";
534 /* Chars that mean this number is a floating point constant
537 const char FLT_CHARS
[] = "fFdDxXhHbB";
539 /* Tables for lexical analysis. */
540 static char mnemonic_chars
[256];
541 static char register_chars
[256];
542 static char operand_chars
[256];
544 /* Lexical macros. */
545 #define is_operand_char(x) (operand_chars[(unsigned char) x])
546 #define is_register_char(x) (register_chars[(unsigned char) x])
547 #define is_space_char(x) ((x) == ' ')
549 /* All non-digit non-letter characters that may occur in an operand and
550 which aren't already in extra_symbol_chars[]. */
551 static const char operand_special_chars
[] = "$+,)._~/<>|&^!=:@]";
553 /* md_assemble() always leaves the strings it's passed unaltered. To
554 effect this we maintain a stack of saved characters that we've smashed
555 with '\0's (indicating end of strings for various sub-fields of the
556 assembler instruction). */
557 static char save_stack
[32];
558 static char *save_stack_p
;
559 #define END_STRING_AND_SAVE(s) \
560 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
561 #define RESTORE_END_STRING(s) \
562 do { *(s) = *--save_stack_p; } while (0)
564 /* The instruction we're assembling. */
567 /* Possible templates for current insn. */
568 static const templates
*current_templates
;
570 /* Per instruction expressionS buffers: max displacements & immediates. */
571 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
572 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
574 /* Current operand we are working on. */
575 static int this_operand
= -1;
577 /* Are we processing a .insn directive? */
578 #define dot_insn() (i.tm.mnem_off == MN__insn)
580 /* We support four different modes. FLAG_CODE variable is used to distinguish
588 static enum flag_code flag_code
;
589 static unsigned int object_64bit
;
590 static unsigned int disallow_64bit_reloc
;
591 static int use_rela_relocations
= 0;
592 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
593 static const char *tls_get_addr
;
595 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
596 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
597 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
599 /* The ELF ABI to use. */
607 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
610 #if defined (TE_PE) || defined (TE_PEP)
611 /* Use big object file format. */
612 static int use_big_obj
= 0;
615 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
616 /* 1 if generating code for a shared library. */
617 static int shared
= 0;
619 unsigned int x86_sframe_cfa_sp_reg
;
620 /* The other CFA base register for SFrame stack trace info. */
621 unsigned int x86_sframe_cfa_fp_reg
;
622 unsigned int x86_sframe_cfa_ra_reg
;
626 /* 1 for intel syntax,
628 static int intel_syntax
= 0;
630 static enum x86_64_isa
632 amd64
= 1, /* AMD64 ISA. */
633 intel64
/* Intel64 ISA. */
636 /* 1 for intel mnemonic,
637 0 if att mnemonic. */
638 static int intel_mnemonic
= !SYSV386_COMPAT
;
640 /* 1 if pseudo registers are permitted. */
641 static int allow_pseudo_reg
= 0;
643 /* 1 if register prefix % not required. */
644 static int allow_naked_reg
= 0;
646 /* 1 if the assembler should add BND prefix for all control-transferring
647 instructions supporting it, even if this prefix wasn't specified
649 static int add_bnd_prefix
= 0;
651 /* 1 if pseudo index register, eiz/riz, is allowed . */
652 static int allow_index_reg
= 0;
654 /* 1 if the assembler should ignore LOCK prefix, even if it was
655 specified explicitly. */
656 static int omit_lock_prefix
= 0;
658 /* 1 if the assembler should encode lfence, mfence, and sfence as
659 "lock addl $0, (%{re}sp)". */
660 static int avoid_fence
= 0;
662 /* 1 if lfence should be inserted after every load. */
663 static int lfence_after_load
= 0;
665 /* Non-zero if lfence should be inserted before indirect branch. */
666 static enum lfence_before_indirect_branch_kind
668 lfence_branch_none
= 0,
669 lfence_branch_register
,
670 lfence_branch_memory
,
673 lfence_before_indirect_branch
;
675 /* Non-zero if lfence should be inserted before ret. */
676 static enum lfence_before_ret_kind
678 lfence_before_ret_none
= 0,
679 lfence_before_ret_not
,
680 lfence_before_ret_or
,
681 lfence_before_ret_shl
685 /* Types of previous instruction is .byte or prefix. */
700 /* 1 if the assembler should generate relax relocations. */
702 static int generate_relax_relocations
703 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
;
705 static enum check_kind
711 sse_check
, operand_check
= check_warning
;
713 /* Non-zero if branches should be aligned within power of 2 boundary. */
714 static int align_branch_power
= 0;
716 /* Types of branches to align. */
717 enum align_branch_kind
719 align_branch_none
= 0,
720 align_branch_jcc
= 1,
721 align_branch_fused
= 2,
722 align_branch_jmp
= 3,
723 align_branch_call
= 4,
724 align_branch_indirect
= 5,
728 /* Type bits of branches to align. */
729 enum align_branch_bit
731 align_branch_jcc_bit
= 1 << align_branch_jcc
,
732 align_branch_fused_bit
= 1 << align_branch_fused
,
733 align_branch_jmp_bit
= 1 << align_branch_jmp
,
734 align_branch_call_bit
= 1 << align_branch_call
,
735 align_branch_indirect_bit
= 1 << align_branch_indirect
,
736 align_branch_ret_bit
= 1 << align_branch_ret
739 static unsigned int align_branch
= (align_branch_jcc_bit
740 | align_branch_fused_bit
741 | align_branch_jmp_bit
);
743 /* Types of condition jump used by macro-fusion. */
746 mf_jcc_jo
= 0, /* base opcode 0x70 */
747 mf_jcc_jc
, /* base opcode 0x72 */
748 mf_jcc_je
, /* base opcode 0x74 */
749 mf_jcc_jna
, /* base opcode 0x76 */
750 mf_jcc_js
, /* base opcode 0x78 */
751 mf_jcc_jp
, /* base opcode 0x7a */
752 mf_jcc_jl
, /* base opcode 0x7c */
753 mf_jcc_jle
, /* base opcode 0x7e */
756 /* Types of compare flag-modifying insntructions used by macro-fusion. */
759 mf_cmp_test_and
, /* test/cmp */
760 mf_cmp_alu_cmp
, /* add/sub/cmp */
761 mf_cmp_incdec
/* inc/dec */
764 /* The maximum padding size for fused jcc. CMP like instruction can
765 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
767 #define MAX_FUSED_JCC_PADDING_SIZE 20
769 /* The maximum number of prefixes added for an instruction. */
770 static unsigned int align_branch_prefix_size
= 5;
773 1. Clear the REX_W bit with register operand if possible.
774 2. Above plus use 128bit vector instruction to clear the full vector
777 static int optimize
= 0;
780 1. Clear the REX_W bit with register operand if possible.
781 2. Above plus use 128bit vector instruction to clear the full vector
783 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
786 static int optimize_for_space
= 0;
788 /* Register prefix used for error message. */
789 static const char *register_prefix
= "%";
791 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
792 leave, push, and pop instructions so that gcc has the same stack
793 frame as in 32 bit mode. */
794 static char stackop_size
= '\0';
796 /* Non-zero to optimize code alignment. */
797 int optimize_align_code
= 1;
799 /* Non-zero to quieten some warnings. */
800 static int quiet_warnings
= 0;
802 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
803 static bool pre_386_16bit_warned
;
806 static const char *cpu_arch_name
= NULL
;
807 static char *cpu_sub_arch_name
= NULL
;
809 /* CPU feature flags. */
810 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
812 /* If we have selected a cpu we are generating instructions for. */
813 static int cpu_arch_tune_set
= 0;
815 /* Cpu we are generating instructions for. */
816 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
818 /* CPU feature flags of cpu we are generating instructions for. */
819 static i386_cpu_flags cpu_arch_tune_flags
;
821 /* CPU instruction set architecture used. */
822 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
824 /* CPU feature flags of instruction set architecture used. */
825 i386_cpu_flags cpu_arch_isa_flags
;
827 /* If set, conditional jumps are not automatically promoted to handle
828 larger than a byte offset. */
829 static bool no_cond_jump_promotion
= false;
831 /* This will be set from an expression parser hook if there's any
832 applicable operator involved in an expression. */
835 expr_operator_present
,
839 /* Encode SSE instructions with VEX prefix. */
840 static unsigned int sse2avx
;
842 /* Encode aligned vector move as unaligned vector move. */
843 static unsigned int use_unaligned_vector_move
;
845 /* Maximum permitted vector size. */
846 #define VSZ_DEFAULT VSZ512
847 static unsigned int vector_size
= VSZ_DEFAULT
;
849 /* Encode scalar AVX instructions with specific vector length. */
856 /* Encode VEX WIG instructions with specific vex.w. */
863 /* Encode scalar EVEX LIG instructions with specific vector length. */
871 /* Encode EVEX WIG instructions with specific evex.w. */
878 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
879 static enum rc_type evexrcig
= rne
;
881 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
882 static symbolS
*GOT_symbol
;
884 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
885 unsigned int x86_dwarf2_return_column
;
887 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
888 int x86_cie_data_alignment
;
890 /* Interface to relax_segment.
891 There are 3 major relax states for 386 jump insns because the
892 different types of jumps add different sizes to frags when we're
893 figuring out what sort of jump to choose to reach a given label.
895 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
896 branches which are handled by md_estimate_size_before_relax() and
897 i386_generic_table_relax_frag(). */
900 #define UNCOND_JUMP 0
902 #define COND_JUMP86 2
903 #define BRANCH_PADDING 3
904 #define BRANCH_PREFIX 4
905 #define FUSED_JCC_PADDING 5
910 #define SMALL16 (SMALL | CODE16)
912 #define BIG16 (BIG | CODE16)
916 #define INLINE __inline__
922 #define ENCODE_RELAX_STATE(type, size) \
923 ((relax_substateT) (((type) << 2) | (size)))
924 #define TYPE_FROM_RELAX_STATE(s) \
926 #define DISP_SIZE_FROM_RELAX_STATE(s) \
927 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
929 /* This table is used by relax_frag to promote short jumps to long
930 ones where necessary. SMALL (short) jumps may be promoted to BIG
931 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
932 don't allow a short jump in a 32 bit code segment to be promoted to
933 a 16 bit offset jump because it's slower (requires data size
934 prefix), and doesn't work, unless the destination is in the bottom
935 64k of the code segment (The top 16 bits of eip are zeroed). */
937 const relax_typeS md_relax_table
[] =
940 1) most positive reach of this state,
941 2) most negative reach of this state,
942 3) how many bytes this mode will have in the variable part of the frag
943 4) which index into the table to try if we can't fit into this one. */
945 /* UNCOND_JUMP states. */
946 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
947 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
948 /* dword jmp adds 4 bytes to frag:
949 0 extra opcode bytes, 4 displacement bytes. */
951 /* word jmp adds 2 byte2 to frag:
952 0 extra opcode bytes, 2 displacement bytes. */
955 /* COND_JUMP states. */
956 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
957 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
958 /* dword conditionals adds 5 bytes to frag:
959 1 extra opcode byte, 4 displacement bytes. */
961 /* word conditionals add 3 bytes to frag:
962 1 extra opcode byte, 2 displacement bytes. */
965 /* COND_JUMP86 states. */
966 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
967 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
968 /* dword conditionals adds 5 bytes to frag:
969 1 extra opcode byte, 4 displacement bytes. */
971 /* word conditionals add 4 bytes to frag:
972 1 displacement byte and a 3 byte long branch insn. */
976 #define ARCH(n, t, f, s) \
977 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
979 #define SUBARCH(n, e, d, s) \
980 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
981 CPU_ ## d ## _FLAGS }
982 #define VECARCH(n, e, d, v) \
983 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
984 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
986 static const arch_entry cpu_arch
[] =
988 /* Do not replace the first two entries - i386_target_format() and
989 set_cpu_arch() rely on them being there in this order. */
990 ARCH (generic32
, GENERIC32
, GENERIC32
, false),
991 ARCH (generic64
, GENERIC64
, GENERIC64
, false),
992 ARCH (i8086
, UNKNOWN
, NONE
, false),
993 ARCH (i186
, UNKNOWN
, 186, false),
994 ARCH (i286
, UNKNOWN
, 286, false),
995 ARCH (i386
, I386
, 386, false),
996 ARCH (i486
, I486
, 486, false),
997 ARCH (i586
, PENTIUM
, 586, false),
998 ARCH (i686
, PENTIUMPRO
, 686, false),
999 ARCH (pentium
, PENTIUM
, 586, false),
1000 ARCH (pentiumpro
, PENTIUMPRO
, PENTIUMPRO
, false),
1001 ARCH (pentiumii
, PENTIUMPRO
, P2
, false),
1002 ARCH (pentiumiii
, PENTIUMPRO
, P3
, false),
1003 ARCH (pentium4
, PENTIUM4
, P4
, false),
1004 ARCH (prescott
, NOCONA
, CORE
, false),
1005 ARCH (nocona
, NOCONA
, NOCONA
, false),
1006 ARCH (yonah
, CORE
, CORE
, true),
1007 ARCH (core
, CORE
, CORE
, false),
1008 ARCH (merom
, CORE2
, CORE2
, true),
1009 ARCH (core2
, CORE2
, CORE2
, false),
1010 ARCH (corei7
, COREI7
, COREI7
, false),
1011 ARCH (iamcu
, IAMCU
, IAMCU
, false),
1012 ARCH (k6
, K6
, K6
, false),
1013 ARCH (k6_2
, K6
, K6_2
, false),
1014 ARCH (athlon
, ATHLON
, ATHLON
, false),
1015 ARCH (sledgehammer
, K8
, K8
, true),
1016 ARCH (opteron
, K8
, K8
, false),
1017 ARCH (k8
, K8
, K8
, false),
1018 ARCH (amdfam10
, AMDFAM10
, AMDFAM10
, false),
1019 ARCH (bdver1
, BD
, BDVER1
, false),
1020 ARCH (bdver2
, BD
, BDVER2
, false),
1021 ARCH (bdver3
, BD
, BDVER3
, false),
1022 ARCH (bdver4
, BD
, BDVER4
, false),
1023 ARCH (znver1
, ZNVER
, ZNVER1
, false),
1024 ARCH (znver2
, ZNVER
, ZNVER2
, false),
1025 ARCH (znver3
, ZNVER
, ZNVER3
, false),
1026 ARCH (znver4
, ZNVER
, ZNVER4
, false),
1027 ARCH (btver1
, BT
, BTVER1
, false),
1028 ARCH (btver2
, BT
, BTVER2
, false),
1030 SUBARCH (8087, 8087, ANY_8087
, false),
1031 SUBARCH (87, NONE
, ANY_8087
, false), /* Disable only! */
1032 SUBARCH (287, 287, ANY_287
, false),
1033 SUBARCH (387, 387, ANY_387
, false),
1034 SUBARCH (687, 687, ANY_687
, false),
1035 SUBARCH (cmov
, CMOV
, CMOV
, false),
1036 SUBARCH (fxsr
, FXSR
, ANY_FXSR
, false),
1037 SUBARCH (mmx
, MMX
, ANY_MMX
, false),
1038 SUBARCH (sse
, SSE
, ANY_SSE
, false),
1039 SUBARCH (sse2
, SSE2
, ANY_SSE2
, false),
1040 SUBARCH (sse3
, SSE3
, ANY_SSE3
, false),
1041 SUBARCH (sse4a
, SSE4A
, ANY_SSE4A
, false),
1042 SUBARCH (ssse3
, SSSE3
, ANY_SSSE3
, false),
1043 SUBARCH (sse4
.1
, SSE4_1
, ANY_SSE4_1
, false),
1044 SUBARCH (sse4
.2
, SSE4_2
, ANY_SSE4_2
, false),
1045 SUBARCH (sse4
, SSE4_2
, ANY_SSE4_1
, false),
1046 VECARCH (avx
, AVX
, ANY_AVX
, reset
),
1047 VECARCH (avx2
, AVX2
, ANY_AVX2
, reset
),
1048 VECARCH (avx512f
, AVX512F
, ANY_AVX512F
, reset
),
1049 VECARCH (avx512cd
, AVX512CD
, ANY_AVX512CD
, reset
),
1050 VECARCH (avx512er
, AVX512ER
, ANY_AVX512ER
, reset
),
1051 VECARCH (avx512pf
, AVX512PF
, ANY_AVX512PF
, reset
),
1052 VECARCH (avx512dq
, AVX512DQ
, ANY_AVX512DQ
, reset
),
1053 VECARCH (avx512bw
, AVX512BW
, ANY_AVX512BW
, reset
),
1054 VECARCH (avx512vl
, AVX512VL
, ANY_AVX512VL
, reset
),
1055 SUBARCH (monitor
, MONITOR
, MONITOR
, false),
1056 SUBARCH (vmx
, VMX
, ANY_VMX
, false),
1057 SUBARCH (vmfunc
, VMFUNC
, ANY_VMFUNC
, false),
1058 SUBARCH (smx
, SMX
, SMX
, false),
1059 SUBARCH (xsave
, XSAVE
, ANY_XSAVE
, false),
1060 SUBARCH (xsaveopt
, XSAVEOPT
, ANY_XSAVEOPT
, false),
1061 SUBARCH (xsavec
, XSAVEC
, ANY_XSAVEC
, false),
1062 SUBARCH (xsaves
, XSAVES
, ANY_XSAVES
, false),
1063 SUBARCH (aes
, AES
, ANY_AES
, false),
1064 SUBARCH (pclmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, false),
1065 SUBARCH (clmul
, PCLMULQDQ
, ANY_PCLMULQDQ
, true),
1066 SUBARCH (fsgsbase
, FSGSBASE
, FSGSBASE
, false),
1067 SUBARCH (rdrnd
, RDRND
, RDRND
, false),
1068 SUBARCH (f16c
, F16C
, ANY_F16C
, false),
1069 SUBARCH (bmi2
, BMI2
, BMI2
, false),
1070 SUBARCH (fma
, FMA
, ANY_FMA
, false),
1071 SUBARCH (fma4
, FMA4
, ANY_FMA4
, false),
1072 SUBARCH (xop
, XOP
, ANY_XOP
, false),
1073 SUBARCH (lwp
, LWP
, ANY_LWP
, false),
1074 SUBARCH (movbe
, MOVBE
, MOVBE
, false),
1075 SUBARCH (cx16
, CX16
, CX16
, false),
1076 SUBARCH (lahf_sahf
, LAHF_SAHF
, LAHF_SAHF
, false),
1077 SUBARCH (ept
, EPT
, ANY_EPT
, false),
1078 SUBARCH (lzcnt
, LZCNT
, LZCNT
, false),
1079 SUBARCH (popcnt
, POPCNT
, POPCNT
, false),
1080 SUBARCH (hle
, HLE
, HLE
, false),
1081 SUBARCH (rtm
, RTM
, ANY_RTM
, false),
1082 SUBARCH (tsx
, TSX
, TSX
, false),
1083 SUBARCH (invpcid
, INVPCID
, INVPCID
, false),
1084 SUBARCH (clflush
, CLFLUSH
, CLFLUSH
, false),
1085 SUBARCH (nop
, NOP
, NOP
, false),
1086 SUBARCH (syscall
, SYSCALL
, SYSCALL
, false),
1087 SUBARCH (rdtscp
, RDTSCP
, RDTSCP
, false),
1088 SUBARCH (3dnow
, 3DNOW
, ANY_3DNOW
, false),
1089 SUBARCH (3dnowa
, 3DNOWA
, ANY_3DNOWA
, false),
1090 SUBARCH (padlock
, PADLOCK
, PADLOCK
, false),
1091 SUBARCH (pacifica
, SVME
, ANY_SVME
, true),
1092 SUBARCH (svme
, SVME
, ANY_SVME
, false),
1093 SUBARCH (abm
, ABM
, ABM
, false),
1094 SUBARCH (bmi
, BMI
, BMI
, false),
1095 SUBARCH (tbm
, TBM
, TBM
, false),
1096 SUBARCH (adx
, ADX
, ADX
, false),
1097 SUBARCH (rdseed
, RDSEED
, RDSEED
, false),
1098 SUBARCH (prfchw
, PRFCHW
, PRFCHW
, false),
1099 SUBARCH (smap
, SMAP
, SMAP
, false),
1100 SUBARCH (mpx
, MPX
, ANY_MPX
, false),
1101 SUBARCH (sha
, SHA
, ANY_SHA
, false),
1102 SUBARCH (clflushopt
, CLFLUSHOPT
, CLFLUSHOPT
, false),
1103 SUBARCH (prefetchwt1
, PREFETCHWT1
, PREFETCHWT1
, false),
1104 SUBARCH (se1
, SE1
, SE1
, false),
1105 SUBARCH (clwb
, CLWB
, CLWB
, false),
1106 VECARCH (avx512ifma
, AVX512IFMA
, ANY_AVX512IFMA
, reset
),
1107 VECARCH (avx512vbmi
, AVX512VBMI
, ANY_AVX512VBMI
, reset
),
1108 VECARCH (avx512_4fmaps
, AVX512_4FMAPS
, ANY_AVX512_4FMAPS
, reset
),
1109 VECARCH (avx512_4vnniw
, AVX512_4VNNIW
, ANY_AVX512_4VNNIW
, reset
),
1110 VECARCH (avx512_vpopcntdq
, AVX512_VPOPCNTDQ
, ANY_AVX512_VPOPCNTDQ
, reset
),
1111 VECARCH (avx512_vbmi2
, AVX512_VBMI2
, ANY_AVX512_VBMI2
, reset
),
1112 VECARCH (avx512_vnni
, AVX512_VNNI
, ANY_AVX512_VNNI
, reset
),
1113 VECARCH (avx512_bitalg
, AVX512_BITALG
, ANY_AVX512_BITALG
, reset
),
1114 VECARCH (avx_vnni
, AVX_VNNI
, ANY_AVX_VNNI
, reset
),
1115 SUBARCH (clzero
, CLZERO
, CLZERO
, false),
1116 SUBARCH (mwaitx
, MWAITX
, MWAITX
, false),
1117 SUBARCH (ospke
, OSPKE
, ANY_OSPKE
, false),
1118 SUBARCH (rdpid
, RDPID
, RDPID
, false),
1119 SUBARCH (ptwrite
, PTWRITE
, PTWRITE
, false),
1120 SUBARCH (ibt
, IBT
, IBT
, false),
1121 SUBARCH (shstk
, SHSTK
, SHSTK
, false),
1122 SUBARCH (gfni
, GFNI
, ANY_GFNI
, false),
1123 VECARCH (vaes
, VAES
, ANY_VAES
, reset
),
1124 VECARCH (vpclmulqdq
, VPCLMULQDQ
, ANY_VPCLMULQDQ
, reset
),
1125 SUBARCH (wbnoinvd
, WBNOINVD
, WBNOINVD
, false),
1126 SUBARCH (pconfig
, PCONFIG
, PCONFIG
, false),
1127 SUBARCH (waitpkg
, WAITPKG
, WAITPKG
, false),
1128 SUBARCH (cldemote
, CLDEMOTE
, CLDEMOTE
, false),
1129 SUBARCH (amx_int8
, AMX_INT8
, ANY_AMX_INT8
, false),
1130 SUBARCH (amx_bf16
, AMX_BF16
, ANY_AMX_BF16
, false),
1131 SUBARCH (amx_fp16
, AMX_FP16
, ANY_AMX_FP16
, false),
1132 SUBARCH (amx_complex
, AMX_COMPLEX
, ANY_AMX_COMPLEX
, false),
1133 SUBARCH (amx_tile
, AMX_TILE
, ANY_AMX_TILE
, false),
1134 SUBARCH (movdiri
, MOVDIRI
, MOVDIRI
, false),
1135 SUBARCH (movdir64b
, MOVDIR64B
, MOVDIR64B
, false),
1136 VECARCH (avx512_bf16
, AVX512_BF16
, ANY_AVX512_BF16
, reset
),
1137 VECARCH (avx512_vp2intersect
, AVX512_VP2INTERSECT
,
1138 ANY_AVX512_VP2INTERSECT
, reset
),
1139 SUBARCH (tdx
, TDX
, TDX
, false),
1140 SUBARCH (enqcmd
, ENQCMD
, ENQCMD
, false),
1141 SUBARCH (serialize
, SERIALIZE
, SERIALIZE
, false),
1142 SUBARCH (rdpru
, RDPRU
, RDPRU
, false),
1143 SUBARCH (mcommit
, MCOMMIT
, MCOMMIT
, false),
1144 SUBARCH (sev_es
, SEV_ES
, ANY_SEV_ES
, false),
1145 SUBARCH (tsxldtrk
, TSXLDTRK
, ANY_TSXLDTRK
, false),
1146 SUBARCH (kl
, KL
, ANY_KL
, false),
1147 SUBARCH (widekl
, WIDEKL
, ANY_WIDEKL
, false),
1148 SUBARCH (uintr
, UINTR
, UINTR
, false),
1149 SUBARCH (hreset
, HRESET
, HRESET
, false),
1150 VECARCH (avx512_fp16
, AVX512_FP16
, ANY_AVX512_FP16
, reset
),
1151 SUBARCH (prefetchi
, PREFETCHI
, PREFETCHI
, false),
1152 VECARCH (avx_ifma
, AVX_IFMA
, ANY_AVX_IFMA
, reset
),
1153 VECARCH (avx_vnni_int8
, AVX_VNNI_INT8
, ANY_AVX_VNNI_INT8
, reset
),
1154 SUBARCH (cmpccxadd
, CMPCCXADD
, CMPCCXADD
, false),
1155 SUBARCH (wrmsrns
, WRMSRNS
, WRMSRNS
, false),
1156 SUBARCH (msrlist
, MSRLIST
, MSRLIST
, false),
1157 VECARCH (avx_ne_convert
, AVX_NE_CONVERT
, ANY_AVX_NE_CONVERT
, reset
),
1158 SUBARCH (rao_int
, RAO_INT
, RAO_INT
, false),
1159 SUBARCH (rmpquery
, RMPQUERY
, ANY_RMPQUERY
, false),
1160 SUBARCH (fred
, FRED
, ANY_FRED
, false),
1161 SUBARCH (lkgs
, LKGS
, ANY_LKGS
, false),
1162 VECARCH (avx_vnni_int16
, AVX_VNNI_INT16
, ANY_AVX_VNNI_INT16
, reset
),
1163 VECARCH (sha512
, SHA512
, ANY_SHA512
, reset
),
1164 VECARCH (sm3
, SM3
, ANY_SM3
, reset
),
1165 VECARCH (sm4
, SM4
, ANY_SM4
, reset
),
1166 SUBARCH (pbndkb
, PBNDKB
, PBNDKB
, false),
1167 VECARCH (avx10
.1
, AVX10_1
, ANY_AVX512F
, set
),
1174 /* Like s_lcomm_internal in gas/read.c but the alignment string
1175 is allowed to be optional. */
1178 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
1185 && *input_line_pointer
== ',')
1187 align
= parse_align (needs_align
- 1);
1189 if (align
== (addressT
) -1)
1204 bss_alloc (symbolP
, size
, align
);
1209 pe_lcomm (int needs_align
)
1211 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
1215 const pseudo_typeS md_pseudo_table
[] =
1217 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1218 {"align", s_align_bytes
, 0},
1220 {"align", s_align_ptwo
, 0},
1222 {"arch", set_cpu_arch
, 0},
1226 {"lcomm", pe_lcomm
, 1},
1228 {"ffloat", float_cons
, 'f'},
1229 {"dfloat", float_cons
, 'd'},
1230 {"tfloat", float_cons
, 'x'},
1231 {"hfloat", float_cons
, 'h'},
1232 {"bfloat16", float_cons
, 'b'},
1234 {"slong", signed_cons
, 4},
1235 {"insn", s_insn
, 0},
1236 {"noopt", s_ignore
, 0},
1237 {"optim", s_ignore
, 0},
1238 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
1239 {"code16", set_code_flag
, CODE_16BIT
},
1240 {"code32", set_code_flag
, CODE_32BIT
},
1242 {"code64", set_code_flag
, CODE_64BIT
},
1244 {"intel_syntax", set_intel_syntax
, 1},
1245 {"att_syntax", set_intel_syntax
, 0},
1246 {"intel_mnemonic", set_intel_mnemonic
, 1},
1247 {"att_mnemonic", set_intel_mnemonic
, 0},
1248 {"allow_index_reg", set_allow_index_reg
, 1},
1249 {"disallow_index_reg", set_allow_index_reg
, 0},
1250 {"sse_check", set_check
, 0},
1251 {"operand_check", set_check
, 1},
1252 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1253 {"largecomm", handle_large_common
, 0},
1255 {"file", dwarf2_directive_file
, 0},
1256 {"loc", dwarf2_directive_loc
, 0},
1257 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
1260 {"secrel32", pe_directive_secrel
, 0},
1261 {"secidx", pe_directive_secidx
, 0},
1266 /* For interface with expression (). */
1267 extern char *input_line_pointer
;
1269 /* Hash table for instruction mnemonic lookup. */
1270 static htab_t op_hash
;
1272 /* Hash table for register lookup. */
1273 static htab_t reg_hash
;
1275 /* Various efficient no-op patterns for aligning code labels.
1276 Note: Don't try to assemble the instructions in the comments.
1277 0L and 0w are not legal. */
1278 static const unsigned char f32_1
[] =
1280 static const unsigned char f32_2
[] =
1281 {0x66,0x90}; /* xchg %ax,%ax */
1282 static const unsigned char f32_3
[] =
1283 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1284 static const unsigned char f32_4
[] =
1285 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1286 static const unsigned char f32_6
[] =
1287 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1288 static const unsigned char f32_7
[] =
1289 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1290 static const unsigned char f16_3
[] =
1291 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1292 static const unsigned char f16_4
[] =
1293 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1294 static const unsigned char jump_disp8
[] =
1295 {0xeb}; /* jmp disp8 */
1296 static const unsigned char jump32_disp32
[] =
1297 {0xe9}; /* jmp disp32 */
1298 static const unsigned char jump16_disp32
[] =
1299 {0x66,0xe9}; /* jmp disp32 */
1300 /* 32-bit NOPs patterns. */
1301 static const unsigned char *const f32_patt
[] = {
1302 f32_1
, f32_2
, f32_3
, f32_4
, NULL
, f32_6
, f32_7
1304 /* 16-bit NOPs patterns. */
1305 static const unsigned char *const f16_patt
[] = {
1306 f32_1
, f32_2
, f16_3
, f16_4
1308 /* nopl (%[re]ax) */
1309 static const unsigned char alt_3
[] =
1311 /* nopl 0(%[re]ax) */
1312 static const unsigned char alt_4
[] =
1313 {0x0f,0x1f,0x40,0x00};
1314 /* nopl 0(%[re]ax,%[re]ax,1) */
1315 static const unsigned char alt_5
[] =
1316 {0x0f,0x1f,0x44,0x00,0x00};
1317 /* nopw 0(%[re]ax,%[re]ax,1) */
1318 static const unsigned char alt_6
[] =
1319 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1320 /* nopl 0L(%[re]ax) */
1321 static const unsigned char alt_7
[] =
1322 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1323 /* nopl 0L(%[re]ax,%[re]ax,1) */
1324 static const unsigned char alt_8
[] =
1325 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1326 /* nopw 0L(%[re]ax,%[re]ax,1) */
1327 static const unsigned char alt_9
[] =
1328 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1329 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1330 static const unsigned char alt_10
[] =
1331 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1332 /* data16 nopw %cs:0L(%eax,%eax,1) */
1333 static const unsigned char alt_11
[] =
1334 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1335 /* 32-bit and 64-bit NOPs patterns. */
1336 static const unsigned char *const alt_patt
[] = {
1337 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1338 alt_9
, alt_10
, alt_11
1341 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1342 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1345 i386_output_nops (char *where
, const unsigned char *const *patt
,
1346 int count
, int max_single_nop_size
)
1349 /* Place the longer NOP first. */
1352 const unsigned char *nops
;
1354 if (max_single_nop_size
< 1)
1356 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1357 max_single_nop_size
);
1361 nops
= patt
[max_single_nop_size
- 1];
1363 /* Use the smaller one if the requsted one isn't available. */
1366 max_single_nop_size
--;
1367 nops
= patt
[max_single_nop_size
- 1];
1370 last
= count
% max_single_nop_size
;
1373 for (offset
= 0; offset
< count
; offset
+= max_single_nop_size
)
1374 memcpy (where
+ offset
, nops
, max_single_nop_size
);
1378 nops
= patt
[last
- 1];
1381 /* Use the smaller one plus one-byte NOP if the needed one
1384 nops
= patt
[last
- 1];
1385 memcpy (where
+ offset
, nops
, last
);
1386 where
[offset
+ last
] = *patt
[0];
1389 memcpy (where
+ offset
, nops
, last
);
1394 fits_in_imm7 (offsetT num
)
1396 return (num
& 0x7f) == num
;
1400 fits_in_imm31 (offsetT num
)
1402 return (num
& 0x7fffffff) == num
;
1405 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1406 single NOP instruction LIMIT. */
1409 i386_generate_nops (fragS
*fragP
, char *where
, offsetT count
, int limit
)
1411 const unsigned char *const *patt
= NULL
;
1412 int max_single_nop_size
;
1413 /* Maximum number of NOPs before switching to jump over NOPs. */
1414 int max_number_of_nops
;
1416 switch (fragP
->fr_type
)
1421 case rs_machine_dependent
:
1422 /* Allow NOP padding for jumps and calls. */
1423 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
1424 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
1431 /* We need to decide which NOP sequence to use for 32bit and
1432 64bit. When -mtune= is used:
1434 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1435 PROCESSOR_GENERIC32, f32_patt will be used.
1436 2. For the rest, alt_patt will be used.
1438 When -mtune= isn't used, alt_patt will be used if
1439 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1442 When -march= or .arch is used, we can't use anything beyond
1443 cpu_arch_isa_flags. */
1445 if (flag_code
== CODE_16BIT
)
1448 max_single_nop_size
= sizeof (f16_patt
) / sizeof (f16_patt
[0]);
1449 /* Limit number of NOPs to 2 in 16-bit mode. */
1450 max_number_of_nops
= 2;
1454 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1456 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1457 switch (cpu_arch_tune
)
1459 case PROCESSOR_UNKNOWN
:
1460 /* We use cpu_arch_isa_flags to check if we SHOULD
1461 optimize with nops. */
1462 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1467 case PROCESSOR_PENTIUM4
:
1468 case PROCESSOR_NOCONA
:
1469 case PROCESSOR_CORE
:
1470 case PROCESSOR_CORE2
:
1471 case PROCESSOR_COREI7
:
1472 case PROCESSOR_GENERIC64
:
1474 case PROCESSOR_ATHLON
:
1476 case PROCESSOR_AMDFAM10
:
1478 case PROCESSOR_ZNVER
:
1482 case PROCESSOR_I386
:
1483 case PROCESSOR_I486
:
1484 case PROCESSOR_PENTIUM
:
1485 case PROCESSOR_PENTIUMPRO
:
1486 case PROCESSOR_IAMCU
:
1487 case PROCESSOR_GENERIC32
:
1490 case PROCESSOR_NONE
:
1496 switch (fragP
->tc_frag_data
.tune
)
1498 case PROCESSOR_UNKNOWN
:
1499 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1500 PROCESSOR_UNKNOWN. */
1504 case PROCESSOR_I386
:
1505 case PROCESSOR_I486
:
1506 case PROCESSOR_PENTIUM
:
1507 case PROCESSOR_IAMCU
:
1509 case PROCESSOR_ATHLON
:
1511 case PROCESSOR_AMDFAM10
:
1513 case PROCESSOR_ZNVER
:
1515 case PROCESSOR_GENERIC32
:
1516 /* We use cpu_arch_isa_flags to check if we CAN optimize
1518 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1523 case PROCESSOR_PENTIUMPRO
:
1524 case PROCESSOR_PENTIUM4
:
1525 case PROCESSOR_NOCONA
:
1526 case PROCESSOR_CORE
:
1527 case PROCESSOR_CORE2
:
1528 case PROCESSOR_COREI7
:
1529 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1534 case PROCESSOR_GENERIC64
:
1537 case PROCESSOR_NONE
:
1542 if (patt
== f32_patt
)
1544 max_single_nop_size
= sizeof (f32_patt
) / sizeof (f32_patt
[0]);
1545 /* Limit number of NOPs to 2 for older processors. */
1546 max_number_of_nops
= 2;
1550 max_single_nop_size
= sizeof (alt_patt
) / sizeof (alt_patt
[0]);
1551 /* Limit number of NOPs to 7 for newer processors. */
1552 max_number_of_nops
= 7;
1557 limit
= max_single_nop_size
;
1559 if (fragP
->fr_type
== rs_fill_nop
)
1561 /* Output NOPs for .nop directive. */
1562 if (limit
> max_single_nop_size
)
1564 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1565 _("invalid single nop size: %d "
1566 "(expect within [0, %d])"),
1567 limit
, max_single_nop_size
);
1571 else if (fragP
->fr_type
!= rs_machine_dependent
)
1572 fragP
->fr_var
= count
;
1574 if ((count
/ max_single_nop_size
) > max_number_of_nops
)
1576 /* Generate jump over NOPs. */
1577 offsetT disp
= count
- 2;
1578 if (fits_in_imm7 (disp
))
1580 /* Use "jmp disp8" if possible. */
1582 where
[0] = jump_disp8
[0];
1588 unsigned int size_of_jump
;
1590 if (flag_code
== CODE_16BIT
)
1592 where
[0] = jump16_disp32
[0];
1593 where
[1] = jump16_disp32
[1];
1598 where
[0] = jump32_disp32
[0];
1602 count
-= size_of_jump
+ 4;
1603 if (!fits_in_imm31 (count
))
1605 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
1606 _("jump over nop padding out of range"));
1610 md_number_to_chars (where
+ size_of_jump
, count
, 4);
1611 where
+= size_of_jump
+ 4;
1615 /* Generate multiple NOPs. */
1616 i386_output_nops (where
, patt
, count
, limit
);
1620 operand_type_all_zero (const union i386_operand_type
*x
)
1622 switch (ARRAY_SIZE(x
->array
))
1633 return !x
->array
[0];
1640 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1642 switch (ARRAY_SIZE(x
->array
))
1658 x
->bitfield
.class = ClassNone
;
1659 x
->bitfield
.instance
= InstanceNone
;
1663 operand_type_equal (const union i386_operand_type
*x
,
1664 const union i386_operand_type
*y
)
1666 switch (ARRAY_SIZE(x
->array
))
1669 if (x
->array
[2] != y
->array
[2])
1673 if (x
->array
[1] != y
->array
[1])
1677 return x
->array
[0] == y
->array
[0];
1685 is_cpu (const insn_template
*t
, enum i386_cpu cpu
)
1689 case Cpu287
: return t
->cpu
.bitfield
.cpu287
;
1690 case Cpu387
: return t
->cpu
.bitfield
.cpu387
;
1691 case Cpu3dnow
: return t
->cpu
.bitfield
.cpu3dnow
;
1692 case Cpu3dnowA
: return t
->cpu
.bitfield
.cpu3dnowa
;
1693 case CpuAVX
: return t
->cpu
.bitfield
.cpuavx
;
1694 case CpuHLE
: return t
->cpu
.bitfield
.cpuhle
;
1695 case CpuAVX512F
: return t
->cpu
.bitfield
.cpuavx512f
;
1696 case CpuAVX512VL
: return t
->cpu
.bitfield
.cpuavx512vl
;
1697 case Cpu64
: return t
->cpu
.bitfield
.cpu64
;
1698 case CpuNo64
: return t
->cpu
.bitfield
.cpuno64
;
1700 gas_assert (cpu
< CpuAttrEnums
);
1702 return t
->cpu
.bitfield
.isa
== cpu
+ 1u;
1705 static i386_cpu_flags
cpu_flags_from_attr (i386_cpu_attr a
)
1707 const unsigned int bps
= sizeof (a
.array
[0]) * CHAR_BIT
;
1708 i386_cpu_flags f
= { .array
[0] = 0 };
1710 switch (ARRAY_SIZE(a
.array
))
1713 f
.array
[CpuAttrEnums
/ bps
]
1714 |= (a
.array
[0] >> CpuIsaBits
) << (CpuAttrEnums
% bps
);
1715 if (CpuAttrEnums
% bps
> CpuIsaBits
)
1716 f
.array
[CpuAttrEnums
/ bps
+ 1]
1717 = (a
.array
[0] >> CpuIsaBits
) >> (bps
- CpuAttrEnums
% bps
);
1724 f
.array
[(a
.bitfield
.isa
- 1) / bps
] |= 1u << ((a
.bitfield
.isa
- 1) % bps
);
1730 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1732 switch (ARRAY_SIZE(x
->array
))
1751 return !x
->array
[0];
1758 cpu_flags_equal (const union i386_cpu_flags
*x
,
1759 const union i386_cpu_flags
*y
)
1761 switch (ARRAY_SIZE(x
->array
))
1764 if (x
->array
[4] != y
->array
[4])
1768 if (x
->array
[3] != y
->array
[3])
1772 if (x
->array
[2] != y
->array
[2])
1776 if (x
->array
[1] != y
->array
[1])
1780 return x
->array
[0] == y
->array
[0];
1788 cpu_flags_check_cpu64 (const insn_template
*t
)
1790 return flag_code
== CODE_64BIT
1791 ? !t
->cpu
.bitfield
.cpuno64
1792 : !t
->cpu
.bitfield
.cpu64
;
1795 static INLINE i386_cpu_flags
1796 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1798 switch (ARRAY_SIZE (x
.array
))
1801 x
.array
[4] &= y
.array
[4];
1804 x
.array
[3] &= y
.array
[3];
1807 x
.array
[2] &= y
.array
[2];
1810 x
.array
[1] &= y
.array
[1];
1813 x
.array
[0] &= y
.array
[0];
1821 static INLINE i386_cpu_flags
1822 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1824 switch (ARRAY_SIZE (x
.array
))
1827 x
.array
[4] |= y
.array
[4];
1830 x
.array
[3] |= y
.array
[3];
1833 x
.array
[2] |= y
.array
[2];
1836 x
.array
[1] |= y
.array
[1];
1839 x
.array
[0] |= y
.array
[0];
1847 static INLINE i386_cpu_flags
1848 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1850 switch (ARRAY_SIZE (x
.array
))
1853 x
.array
[4] &= ~y
.array
[4];
1856 x
.array
[3] &= ~y
.array
[3];
1859 x
.array
[2] &= ~y
.array
[2];
1862 x
.array
[1] &= ~y
.array
[1];
1865 x
.array
[0] &= ~y
.array
[0];
1873 static const i386_cpu_flags avx512
= CPU_ANY_AVX512F_FLAGS
;
1875 #define CPU_FLAGS_ARCH_MATCH 0x1
1876 #define CPU_FLAGS_64BIT_MATCH 0x2
1878 #define CPU_FLAGS_PERFECT_MATCH \
1879 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1881 /* Return CPU flags match bits. */
1884 cpu_flags_match (const insn_template
*t
)
1886 i386_cpu_flags x
= cpu_flags_from_attr (t
->cpu
);
1887 int match
= cpu_flags_check_cpu64 (t
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1889 x
.bitfield
.cpu64
= 0;
1890 x
.bitfield
.cpuno64
= 0;
1892 if (cpu_flags_all_zero (&x
))
1894 /* This instruction is available on all archs. */
1895 match
|= CPU_FLAGS_ARCH_MATCH
;
1899 /* This instruction is available only on some archs. */
1900 i386_cpu_flags cpu
= cpu_arch_flags
;
1902 /* AVX512VL is no standalone feature - match it and then strip it. */
1903 if (x
.bitfield
.cpuavx512vl
&& !cpu
.bitfield
.cpuavx512vl
)
1905 x
.bitfield
.cpuavx512vl
= 0;
1907 /* AVX and AVX2 present at the same time express an operand size
1908 dependency - strip AVX2 for the purposes here. The operand size
1909 dependent check occurs in check_vecOperands(). */
1910 if (x
.bitfield
.cpuavx
&& x
.bitfield
.cpuavx2
)
1911 x
.bitfield
.cpuavx2
= 0;
1913 cpu
= cpu_flags_and (x
, cpu
);
1914 if (!cpu_flags_all_zero (&cpu
))
1916 if (x
.bitfield
.cpuavx
)
1918 /* We need to check a few extra flags with AVX. */
1919 if (cpu
.bitfield
.cpuavx
1920 && (!t
->opcode_modifier
.sse2avx
1921 || (sse2avx
&& !i
.prefix
[DATA_PREFIX
]))
1922 && (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1923 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1924 && (!x
.bitfield
.cpupclmulqdq
|| cpu
.bitfield
.cpupclmulqdq
))
1925 match
|= CPU_FLAGS_ARCH_MATCH
;
1927 else if (x
.bitfield
.cpuavx512f
)
1929 /* We need to check a few extra flags with AVX512F. */
1930 if (cpu
.bitfield
.cpuavx512f
1931 && (!x
.bitfield
.cpugfni
|| cpu
.bitfield
.cpugfni
)
1932 && (!x
.bitfield
.cpuvaes
|| cpu
.bitfield
.cpuvaes
)
1933 && (!x
.bitfield
.cpuvpclmulqdq
|| cpu
.bitfield
.cpuvpclmulqdq
))
1934 match
|= CPU_FLAGS_ARCH_MATCH
;
1937 match
|= CPU_FLAGS_ARCH_MATCH
;
1943 static INLINE i386_operand_type
1944 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1946 if (x
.bitfield
.class != y
.bitfield
.class)
1947 x
.bitfield
.class = ClassNone
;
1948 if (x
.bitfield
.instance
!= y
.bitfield
.instance
)
1949 x
.bitfield
.instance
= InstanceNone
;
1951 switch (ARRAY_SIZE (x
.array
))
1954 x
.array
[2] &= y
.array
[2];
1957 x
.array
[1] &= y
.array
[1];
1960 x
.array
[0] &= y
.array
[0];
1968 static INLINE i386_operand_type
1969 operand_type_and_not (i386_operand_type x
, i386_operand_type y
)
1971 gas_assert (y
.bitfield
.class == ClassNone
);
1972 gas_assert (y
.bitfield
.instance
== InstanceNone
);
1974 switch (ARRAY_SIZE (x
.array
))
1977 x
.array
[2] &= ~y
.array
[2];
1980 x
.array
[1] &= ~y
.array
[1];
1983 x
.array
[0] &= ~y
.array
[0];
1991 static INLINE i386_operand_type
1992 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1994 gas_assert (x
.bitfield
.class == ClassNone
||
1995 y
.bitfield
.class == ClassNone
||
1996 x
.bitfield
.class == y
.bitfield
.class);
1997 gas_assert (x
.bitfield
.instance
== InstanceNone
||
1998 y
.bitfield
.instance
== InstanceNone
||
1999 x
.bitfield
.instance
== y
.bitfield
.instance
);
2001 switch (ARRAY_SIZE (x
.array
))
2004 x
.array
[2] |= y
.array
[2];
2007 x
.array
[1] |= y
.array
[1];
2010 x
.array
[0] |= y
.array
[0];
2018 static INLINE i386_operand_type
2019 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
2021 gas_assert (y
.bitfield
.class == ClassNone
);
2022 gas_assert (y
.bitfield
.instance
== InstanceNone
);
2024 switch (ARRAY_SIZE (x
.array
))
2027 x
.array
[2] ^= y
.array
[2];
2030 x
.array
[1] ^= y
.array
[1];
2033 x
.array
[0] ^= y
.array
[0];
2041 static const i386_operand_type anydisp
= {
2042 .bitfield
= { .disp8
= 1, .disp16
= 1, .disp32
= 1, .disp64
= 1 }
2054 operand_type_check (i386_operand_type t
, enum operand_type c
)
2059 return t
.bitfield
.class == Reg
;
2062 return (t
.bitfield
.imm8
2066 || t
.bitfield
.imm32s
2067 || t
.bitfield
.imm64
);
2070 return (t
.bitfield
.disp8
2071 || t
.bitfield
.disp16
2072 || t
.bitfield
.disp32
2073 || t
.bitfield
.disp64
);
2076 return (t
.bitfield
.disp8
2077 || t
.bitfield
.disp16
2078 || t
.bitfield
.disp32
2079 || t
.bitfield
.disp64
2080 || t
.bitfield
.baseindex
);
2089 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2090 between operand GIVEN and opeand WANTED for instruction template T. */
2093 match_operand_size (const insn_template
*t
, unsigned int wanted
,
2096 return !((i
.types
[given
].bitfield
.byte
2097 && !t
->operand_types
[wanted
].bitfield
.byte
)
2098 || (i
.types
[given
].bitfield
.word
2099 && !t
->operand_types
[wanted
].bitfield
.word
)
2100 || (i
.types
[given
].bitfield
.dword
2101 && !t
->operand_types
[wanted
].bitfield
.dword
)
2102 || (i
.types
[given
].bitfield
.qword
2103 && (!t
->operand_types
[wanted
].bitfield
.qword
2104 /* Don't allow 64-bit (memory) operands outside of 64-bit
2105 mode, when they're used where a 64-bit GPR could also
2106 be used. Checking is needed for Intel Syntax only. */
2108 && flag_code
!= CODE_64BIT
2109 && (t
->operand_types
[wanted
].bitfield
.class == Reg
2110 || t
->operand_types
[wanted
].bitfield
.class == Accum
2111 || t
->opcode_modifier
.isstring
))))
2112 || (i
.types
[given
].bitfield
.tbyte
2113 && !t
->operand_types
[wanted
].bitfield
.tbyte
));
2116 /* Return 1 if there is no conflict in SIMD register between operand
2117 GIVEN and opeand WANTED for instruction template T. */
2120 match_simd_size (const insn_template
*t
, unsigned int wanted
,
2123 return !((i
.types
[given
].bitfield
.xmmword
2124 && !t
->operand_types
[wanted
].bitfield
.xmmword
)
2125 || (i
.types
[given
].bitfield
.ymmword
2126 && !t
->operand_types
[wanted
].bitfield
.ymmword
)
2127 || (i
.types
[given
].bitfield
.zmmword
2128 && !t
->operand_types
[wanted
].bitfield
.zmmword
)
2129 || (i
.types
[given
].bitfield
.tmmword
2130 && !t
->operand_types
[wanted
].bitfield
.tmmword
));
2133 /* Return 1 if there is no conflict in any size between operand GIVEN
2134 and opeand WANTED for instruction template T. */
2137 match_mem_size (const insn_template
*t
, unsigned int wanted
,
2140 return (match_operand_size (t
, wanted
, given
)
2141 && !((i
.types
[given
].bitfield
.unspecified
2142 && !i
.broadcast
.type
2143 && !i
.broadcast
.bytes
2144 && !t
->operand_types
[wanted
].bitfield
.unspecified
)
2145 || (i
.types
[given
].bitfield
.fword
2146 && !t
->operand_types
[wanted
].bitfield
.fword
)
2147 /* For scalar opcode templates to allow register and memory
2148 operands at the same time, some special casing is needed
2149 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2150 down-conversion vpmov*. */
2151 || ((t
->operand_types
[wanted
].bitfield
.class == RegSIMD
2152 && t
->operand_types
[wanted
].bitfield
.byte
2153 + t
->operand_types
[wanted
].bitfield
.word
2154 + t
->operand_types
[wanted
].bitfield
.dword
2155 + t
->operand_types
[wanted
].bitfield
.qword
2156 > !!t
->opcode_modifier
.broadcast
)
2157 ? (i
.types
[given
].bitfield
.xmmword
2158 || i
.types
[given
].bitfield
.ymmword
2159 || i
.types
[given
].bitfield
.zmmword
)
2160 : !match_simd_size(t
, wanted
, given
))));
2163 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2164 operands for instruction template T, and it has MATCH_REVERSE set if there
2165 is no size conflict on any operands for the template with operands reversed
2166 (and the template allows for reversing in the first place). */
2168 #define MATCH_STRAIGHT 1
2169 #define MATCH_REVERSE 2
2171 static INLINE
unsigned int
2172 operand_size_match (const insn_template
*t
)
2174 unsigned int j
, match
= MATCH_STRAIGHT
;
2176 /* Don't check non-absolute jump instructions. */
2177 if (t
->opcode_modifier
.jump
2178 && t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
2181 /* Check memory and accumulator operand size. */
2182 for (j
= 0; j
< i
.operands
; j
++)
2184 if (i
.types
[j
].bitfield
.class != Reg
2185 && i
.types
[j
].bitfield
.class != RegSIMD
2186 && t
->opcode_modifier
.operandconstraint
== ANY_SIZE
)
2189 if (t
->operand_types
[j
].bitfield
.class == Reg
2190 && !match_operand_size (t
, j
, j
))
2196 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2197 && !match_simd_size (t
, j
, j
))
2203 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2204 && (!match_operand_size (t
, j
, j
) || !match_simd_size (t
, j
, j
)))
2210 if ((i
.flags
[j
] & Operand_Mem
) && !match_mem_size (t
, j
, j
))
2217 if (!t
->opcode_modifier
.d
)
2220 /* Check reverse. */
2221 gas_assert (i
.operands
>= 2);
2223 for (j
= 0; j
< i
.operands
; j
++)
2225 unsigned int given
= i
.operands
- j
- 1;
2227 /* For FMA4 and XOP insns VEX.W controls just the first two
2228 register operands. */
2229 if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
2230 given
= j
< 2 ? 1 - j
: j
;
2232 if (t
->operand_types
[j
].bitfield
.class == Reg
2233 && !match_operand_size (t
, j
, given
))
2236 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
2237 && !match_simd_size (t
, j
, given
))
2240 if (t
->operand_types
[j
].bitfield
.instance
== Accum
2241 && (!match_operand_size (t
, j
, given
)
2242 || !match_simd_size (t
, j
, given
)))
2245 if ((i
.flags
[given
] & Operand_Mem
) && !match_mem_size (t
, j
, given
))
2249 return match
| MATCH_REVERSE
;
2253 operand_type_match (i386_operand_type overlap
,
2254 i386_operand_type given
)
2256 i386_operand_type temp
= overlap
;
2258 temp
.bitfield
.unspecified
= 0;
2259 temp
.bitfield
.byte
= 0;
2260 temp
.bitfield
.word
= 0;
2261 temp
.bitfield
.dword
= 0;
2262 temp
.bitfield
.fword
= 0;
2263 temp
.bitfield
.qword
= 0;
2264 temp
.bitfield
.tbyte
= 0;
2265 temp
.bitfield
.xmmword
= 0;
2266 temp
.bitfield
.ymmword
= 0;
2267 temp
.bitfield
.zmmword
= 0;
2268 temp
.bitfield
.tmmword
= 0;
2269 if (operand_type_all_zero (&temp
))
2272 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
)
2276 i
.error
= operand_type_mismatch
;
2280 /* If given types g0 and g1 are registers they must be of the same type
2281 unless the expected operand type register overlap is null.
2282 Intel syntax sized memory operands are also checked here. */
2285 operand_type_register_match (i386_operand_type g0
,
2286 i386_operand_type t0
,
2287 i386_operand_type g1
,
2288 i386_operand_type t1
)
2290 if (g0
.bitfield
.class != Reg
2291 && g0
.bitfield
.class != RegSIMD
2292 && (g0
.bitfield
.unspecified
2293 || !operand_type_check (g0
, anymem
)))
2296 if (g1
.bitfield
.class != Reg
2297 && g1
.bitfield
.class != RegSIMD
2298 && (g1
.bitfield
.unspecified
2299 || !operand_type_check (g1
, anymem
)))
2302 if (g0
.bitfield
.byte
== g1
.bitfield
.byte
2303 && g0
.bitfield
.word
== g1
.bitfield
.word
2304 && g0
.bitfield
.dword
== g1
.bitfield
.dword
2305 && g0
.bitfield
.qword
== g1
.bitfield
.qword
2306 && g0
.bitfield
.xmmword
== g1
.bitfield
.xmmword
2307 && g0
.bitfield
.ymmword
== g1
.bitfield
.ymmword
2308 && g0
.bitfield
.zmmword
== g1
.bitfield
.zmmword
)
2311 /* If expectations overlap in no more than a single size, all is fine. */
2312 g0
= operand_type_and (t0
, t1
);
2313 if (g0
.bitfield
.byte
2317 + g0
.bitfield
.xmmword
2318 + g0
.bitfield
.ymmword
2319 + g0
.bitfield
.zmmword
<= 1)
2322 i
.error
= register_type_mismatch
;
2327 static INLINE
unsigned int
2328 register_number (const reg_entry
*r
)
2330 unsigned int nr
= r
->reg_num
;
2332 if (r
->reg_flags
& RegRex
)
2335 if (r
->reg_flags
& RegVRex
)
2341 static INLINE
unsigned int
2342 mode_from_disp_size (i386_operand_type t
)
2344 if (t
.bitfield
.disp8
)
2346 else if (t
.bitfield
.disp16
2347 || t
.bitfield
.disp32
)
2354 fits_in_signed_byte (addressT num
)
2356 return num
+ 0x80 <= 0xff;
2360 fits_in_unsigned_byte (addressT num
)
2366 fits_in_unsigned_word (addressT num
)
2368 return num
<= 0xffff;
2372 fits_in_signed_word (addressT num
)
2374 return num
+ 0x8000 <= 0xffff;
2378 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED
)
2383 return num
+ 0x80000000 <= 0xffffffff;
2385 } /* fits_in_signed_long() */
2388 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED
)
2393 return num
<= 0xffffffff;
2395 } /* fits_in_unsigned_long() */
2397 static INLINE valueT
extend_to_32bit_address (addressT num
)
2400 if (fits_in_unsigned_long(num
))
2401 return (num
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
2403 if (!fits_in_signed_long (num
))
2404 return num
& 0xffffffff;
2411 fits_in_disp8 (offsetT num
)
2413 int shift
= i
.memshift
;
2419 mask
= (1 << shift
) - 1;
2421 /* Return 0 if NUM isn't properly aligned. */
2425 /* Check if NUM will fit in 8bit after shift. */
2426 return fits_in_signed_byte (num
>> shift
);
2430 fits_in_imm4 (offsetT num
)
2432 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2433 return (num
& (i
.vec_encoding
!= vex_encoding_evex
? 0xf : 7)) == num
;
2436 static i386_operand_type
2437 smallest_imm_type (offsetT num
)
2439 i386_operand_type t
;
2441 operand_type_set (&t
, 0);
2442 t
.bitfield
.imm64
= 1;
2444 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
2446 /* This code is disabled on the 486 because all the Imm1 forms
2447 in the opcode table are slower on the i486. They're the
2448 versions with the implicitly specified single-position
2449 displacement, which has another syntax if you really want to
2451 t
.bitfield
.imm1
= 1;
2452 t
.bitfield
.imm8
= 1;
2453 t
.bitfield
.imm8s
= 1;
2454 t
.bitfield
.imm16
= 1;
2455 t
.bitfield
.imm32
= 1;
2456 t
.bitfield
.imm32s
= 1;
2458 else if (fits_in_signed_byte (num
))
2460 if (fits_in_unsigned_byte (num
))
2461 t
.bitfield
.imm8
= 1;
2462 t
.bitfield
.imm8s
= 1;
2463 t
.bitfield
.imm16
= 1;
2464 t
.bitfield
.imm32
= 1;
2465 t
.bitfield
.imm32s
= 1;
2467 else if (fits_in_unsigned_byte (num
))
2469 t
.bitfield
.imm8
= 1;
2470 t
.bitfield
.imm16
= 1;
2471 t
.bitfield
.imm32
= 1;
2472 t
.bitfield
.imm32s
= 1;
2474 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
2476 t
.bitfield
.imm16
= 1;
2477 t
.bitfield
.imm32
= 1;
2478 t
.bitfield
.imm32s
= 1;
2480 else if (fits_in_signed_long (num
))
2482 t
.bitfield
.imm32
= 1;
2483 t
.bitfield
.imm32s
= 1;
2485 else if (fits_in_unsigned_long (num
))
2486 t
.bitfield
.imm32
= 1;
2492 offset_in_range (offsetT val
, int size
)
2498 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
2499 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
2501 case 4: mask
= ((addressT
) 1 << 32) - 1; break;
2503 case sizeof (val
): return val
;
2507 if ((val
& ~mask
) != 0 && (-val
& ~mask
) != 0)
2508 as_warn (_("0x%" PRIx64
" shortened to 0x%" PRIx64
),
2509 (uint64_t) val
, (uint64_t) (val
& mask
));
2514 static INLINE
const char *insn_name (const insn_template
*t
)
2516 return &i386_mnemonics
[t
->mnem_off
];
2529 a. PREFIX_EXIST if attempting to add a prefix where one from the
2530 same class already exists.
2531 b. PREFIX_LOCK if lock prefix is added.
2532 c. PREFIX_REP if rep/repne prefix is added.
2533 d. PREFIX_DS if ds prefix is added.
2534 e. PREFIX_OTHER if other prefix is added.
2537 static enum PREFIX_GROUP
2538 add_prefix (unsigned int prefix
)
2540 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
2543 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
2544 && flag_code
== CODE_64BIT
)
2546 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
2547 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_R
)
2548 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_X
)
2549 || (i
.prefix
[REX_PREFIX
] & prefix
& REX_B
))
2560 case DS_PREFIX_OPCODE
:
2563 case CS_PREFIX_OPCODE
:
2564 case ES_PREFIX_OPCODE
:
2565 case FS_PREFIX_OPCODE
:
2566 case GS_PREFIX_OPCODE
:
2567 case SS_PREFIX_OPCODE
:
2571 case REPNE_PREFIX_OPCODE
:
2572 case REPE_PREFIX_OPCODE
:
2577 case LOCK_PREFIX_OPCODE
:
2586 case ADDR_PREFIX_OPCODE
:
2590 case DATA_PREFIX_OPCODE
:
2594 if (i
.prefix
[q
] != 0)
2602 i
.prefix
[q
] |= prefix
;
2605 as_bad (_("same type of prefix used twice"));
2611 update_code_flag (int value
, int check
)
2613 PRINTF_LIKE ((*as_error
)) = check
? as_fatal
: as_bad
;
2615 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpu64
)
2617 as_error (_("64bit mode not supported on `%s'."),
2618 cpu_arch_name
? cpu_arch_name
: default_arch
);
2622 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
2624 as_error (_("32bit mode not supported on `%s'."),
2625 cpu_arch_name
? cpu_arch_name
: default_arch
);
2629 flag_code
= (enum flag_code
) value
;
2631 stackop_size
= '\0';
2635 set_code_flag (int value
)
2637 update_code_flag (value
, 0);
2641 set_16bit_gcc_code_flag (int new_code_flag
)
2643 flag_code
= (enum flag_code
) new_code_flag
;
2644 if (flag_code
!= CODE_16BIT
)
2646 stackop_size
= LONG_MNEM_SUFFIX
;
2650 set_intel_syntax (int syntax_flag
)
2652 /* Find out if register prefixing is specified. */
2653 int ask_naked_reg
= 0;
2656 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2659 int e
= get_symbol_name (&string
);
2661 if (strcmp (string
, "prefix") == 0)
2663 else if (strcmp (string
, "noprefix") == 0)
2666 as_bad (_("bad argument to syntax directive."));
2667 (void) restore_line_pointer (e
);
2669 demand_empty_rest_of_line ();
2671 intel_syntax
= syntax_flag
;
2673 if (ask_naked_reg
== 0)
2674 allow_naked_reg
= (intel_syntax
2675 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2677 allow_naked_reg
= (ask_naked_reg
< 0);
2679 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2681 register_prefix
= allow_naked_reg
? "" : "%";
2685 set_intel_mnemonic (int mnemonic_flag
)
2687 intel_mnemonic
= mnemonic_flag
;
2691 set_allow_index_reg (int flag
)
2693 allow_index_reg
= flag
;
2697 set_check (int what
)
2699 enum check_kind
*kind
;
2704 kind
= &operand_check
;
2715 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2718 int e
= get_symbol_name (&string
);
2720 if (strcmp (string
, "none") == 0)
2722 else if (strcmp (string
, "warning") == 0)
2723 *kind
= check_warning
;
2724 else if (strcmp (string
, "error") == 0)
2725 *kind
= check_error
;
2727 as_bad (_("bad argument to %s_check directive."), str
);
2728 (void) restore_line_pointer (e
);
2731 as_bad (_("missing argument for %s_check directive"), str
);
2733 demand_empty_rest_of_line ();
2737 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2738 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2740 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2741 static const char *arch
;
2743 /* Intel MCU is only supported on ELF. */
2749 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2750 use default_arch. */
2751 arch
= cpu_arch_name
;
2753 arch
= default_arch
;
2756 /* If we are targeting Intel MCU, we must enable it. */
2757 if ((get_elf_backend_data (stdoutput
)->elf_machine_code
== EM_IAMCU
)
2758 == new_flag
.bitfield
.cpuiamcu
)
2761 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2766 extend_cpu_sub_arch_name (const char *name
)
2768 if (cpu_sub_arch_name
)
2769 cpu_sub_arch_name
= reconcat (cpu_sub_arch_name
, cpu_sub_arch_name
,
2770 ".", name
, (const char *) NULL
);
2772 cpu_sub_arch_name
= concat (".", name
, (const char *) NULL
);
2776 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2778 typedef struct arch_stack_entry
2780 const struct arch_stack_entry
*prev
;
2783 i386_cpu_flags flags
;
2784 i386_cpu_flags isa_flags
;
2785 enum processor_type isa
;
2786 enum flag_code flag_code
;
2787 unsigned int vector_size
;
2789 bool no_cond_jump_promotion
;
2791 static const arch_stack_entry
*arch_stack_top
;
2796 i386_cpu_flags flags
;
2800 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
2802 as_bad (_("missing cpu architecture"));
2803 input_line_pointer
++;
2807 e
= get_symbol_name (&s
);
2810 if (strcmp (string
, "push") == 0)
2812 arch_stack_entry
*top
= XNEW (arch_stack_entry
);
2814 top
->name
= cpu_arch_name
;
2815 if (cpu_sub_arch_name
)
2816 top
->sub_name
= xstrdup (cpu_sub_arch_name
);
2818 top
->sub_name
= NULL
;
2819 top
->flags
= cpu_arch_flags
;
2820 top
->isa
= cpu_arch_isa
;
2821 top
->isa_flags
= cpu_arch_isa_flags
;
2822 top
->flag_code
= flag_code
;
2823 top
->vector_size
= vector_size
;
2824 top
->stackop_size
= stackop_size
;
2825 top
->no_cond_jump_promotion
= no_cond_jump_promotion
;
2827 top
->prev
= arch_stack_top
;
2828 arch_stack_top
= top
;
2830 (void) restore_line_pointer (e
);
2831 demand_empty_rest_of_line ();
2835 if (strcmp (string
, "pop") == 0)
2837 const arch_stack_entry
*top
= arch_stack_top
;
2840 as_bad (_(".arch stack is empty"));
2841 else if (top
->flag_code
!= flag_code
2842 || top
->stackop_size
!= stackop_size
)
2844 static const unsigned int bits
[] = {
2850 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2851 bits
[top
->flag_code
],
2852 top
->stackop_size
== LONG_MNEM_SUFFIX
? "gcc" : "");
2856 arch_stack_top
= top
->prev
;
2858 cpu_arch_name
= top
->name
;
2859 free (cpu_sub_arch_name
);
2860 cpu_sub_arch_name
= top
->sub_name
;
2861 cpu_arch_flags
= top
->flags
;
2862 cpu_arch_isa
= top
->isa
;
2863 cpu_arch_isa_flags
= top
->isa_flags
;
2864 vector_size
= top
->vector_size
;
2865 no_cond_jump_promotion
= top
->no_cond_jump_promotion
;
2870 (void) restore_line_pointer (e
);
2871 demand_empty_rest_of_line ();
2875 if (strcmp (string
, "default") == 0)
2877 if (strcmp (default_arch
, "iamcu") == 0)
2878 string
= default_arch
;
2881 static const i386_cpu_flags cpu_unknown_flags
= CPU_UNKNOWN_FLAGS
;
2883 cpu_arch_name
= NULL
;
2884 free (cpu_sub_arch_name
);
2885 cpu_sub_arch_name
= NULL
;
2886 cpu_arch_flags
= cpu_unknown_flags
;
2887 cpu_arch_isa
= PROCESSOR_UNKNOWN
;
2888 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
2889 if (!cpu_arch_tune_set
)
2891 cpu_arch_tune
= cpu_arch_isa
;
2892 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2895 vector_size
= VSZ_DEFAULT
;
2897 j
= ARRAY_SIZE (cpu_arch
) + 1;
2901 for (; j
< ARRAY_SIZE (cpu_arch
); j
++)
2903 if (strcmp (string
+ (*string
== '.'), cpu_arch
[j
].name
) == 0
2904 && (*string
== '.') == (cpu_arch
[j
].type
== PROCESSOR_NONE
))
2908 check_cpu_arch_compatible (string
, cpu_arch
[j
].enable
);
2910 if (flag_code
== CODE_64BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpu64
)
2912 as_bad (_("64bit mode not supported on `%s'."),
2914 (void) restore_line_pointer (e
);
2915 ignore_rest_of_line ();
2919 if (flag_code
== CODE_32BIT
&& !cpu_arch
[j
].enable
.bitfield
.cpui386
)
2921 as_bad (_("32bit mode not supported on `%s'."),
2923 (void) restore_line_pointer (e
);
2924 ignore_rest_of_line ();
2928 cpu_arch_name
= cpu_arch
[j
].name
;
2929 free (cpu_sub_arch_name
);
2930 cpu_sub_arch_name
= NULL
;
2931 cpu_arch_flags
= cpu_arch
[j
].enable
;
2932 cpu_arch_isa
= cpu_arch
[j
].type
;
2933 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
2934 if (!cpu_arch_tune_set
)
2936 cpu_arch_tune
= cpu_arch_isa
;
2937 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2940 vector_size
= VSZ_DEFAULT
;
2942 pre_386_16bit_warned
= false;
2946 if (cpu_flags_all_zero (&cpu_arch
[j
].enable
))
2949 flags
= cpu_flags_or (cpu_arch_flags
, cpu_arch
[j
].enable
);
2951 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2953 extend_cpu_sub_arch_name (string
+ 1);
2954 cpu_arch_flags
= flags
;
2955 cpu_arch_isa_flags
= flags
;
2959 = cpu_flags_or (cpu_arch_isa_flags
, cpu_arch
[j
].enable
);
2961 (void) restore_line_pointer (e
);
2963 switch (cpu_arch
[j
].vsz
)
2969 #ifdef SVR4_COMMENT_CHARS
2970 if (*input_line_pointer
== ':' || *input_line_pointer
== '/')
2972 if (*input_line_pointer
== '/')
2975 ++input_line_pointer
;
2976 switch (get_absolute_expression ())
2978 case 512: vector_size
= VSZ512
; break;
2979 case 256: vector_size
= VSZ256
; break;
2980 case 128: vector_size
= VSZ128
; break;
2982 as_bad (_("Unrecognized vector size specifier"));
2983 ignore_rest_of_line ();
2990 vector_size
= VSZ_DEFAULT
;
2994 demand_empty_rest_of_line ();
2999 if (startswith (string
, ".no") && j
>= ARRAY_SIZE (cpu_arch
))
3001 /* Disable an ISA extension. */
3002 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
3003 if (cpu_arch
[j
].type
== PROCESSOR_NONE
3004 && strcmp (string
+ 3, cpu_arch
[j
].name
) == 0)
3006 flags
= cpu_flags_and_not (cpu_arch_flags
, cpu_arch
[j
].disable
);
3007 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
3009 extend_cpu_sub_arch_name (string
+ 1);
3010 cpu_arch_flags
= flags
;
3011 cpu_arch_isa_flags
= flags
;
3014 if (cpu_arch
[j
].vsz
== vsz_set
)
3015 vector_size
= VSZ_DEFAULT
;
3017 (void) restore_line_pointer (e
);
3018 demand_empty_rest_of_line ();
3023 if (j
== ARRAY_SIZE (cpu_arch
))
3024 as_bad (_("no such architecture: `%s'"), string
);
3026 *input_line_pointer
= e
;
3028 no_cond_jump_promotion
= 0;
3029 if (*input_line_pointer
== ','
3030 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
3032 ++input_line_pointer
;
3033 e
= get_symbol_name (&s
);
3036 if (strcmp (string
, "nojumps") == 0)
3037 no_cond_jump_promotion
= 1;
3038 else if (strcmp (string
, "jumps") == 0)
3041 as_bad (_("no such architecture modifier: `%s'"), string
);
3043 (void) restore_line_pointer (e
);
3046 demand_empty_rest_of_line ();
3049 enum bfd_architecture
3052 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3054 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
3055 || flag_code
== CODE_64BIT
)
3056 as_fatal (_("Intel MCU is 32bit ELF only"));
3057 return bfd_arch_iamcu
;
3060 return bfd_arch_i386
;
3066 if (startswith (default_arch
, "x86_64"))
3068 if (default_arch
[6] == '\0')
3069 return bfd_mach_x86_64
;
3071 return bfd_mach_x64_32
;
3073 else if (!strcmp (default_arch
, "i386")
3074 || !strcmp (default_arch
, "iamcu"))
3076 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
3078 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
3079 as_fatal (_("Intel MCU is 32bit ELF only"));
3080 return bfd_mach_i386_iamcu
;
3083 return bfd_mach_i386_i386
;
3086 as_fatal (_("unknown architecture"));
3089 #include "opcodes/i386-tbl.h"
3094 /* Support pseudo prefixes like {disp32}. */
3095 lex_type
['{'] = LEX_BEGIN_NAME
;
3097 /* Initialize op_hash hash table. */
3098 op_hash
= str_htab_create ();
3101 const insn_template
*const *sets
= i386_op_sets
;
3102 const insn_template
*const *end
= sets
+ ARRAY_SIZE (i386_op_sets
) - 1;
3104 /* Type checks to compensate for the conversion through void * which
3105 occurs during hash table insertion / lookup. */
3106 (void) sizeof (sets
== ¤t_templates
->start
);
3107 (void) sizeof (end
== ¤t_templates
->end
);
3108 for (; sets
< end
; ++sets
)
3109 if (str_hash_insert (op_hash
, insn_name (*sets
), sets
, 0))
3110 as_fatal (_("duplicate %s"), insn_name (*sets
));
3113 /* Initialize reg_hash hash table. */
3114 reg_hash
= str_htab_create ();
3116 const reg_entry
*regtab
;
3117 unsigned int regtab_size
= i386_regtab_size
;
3119 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
3121 switch (regtab
->reg_type
.bitfield
.class)
3124 if (regtab
->reg_type
.bitfield
.dword
)
3126 if (regtab
->reg_type
.bitfield
.instance
== Accum
)
3129 else if (regtab
->reg_type
.bitfield
.tbyte
)
3131 /* There's no point inserting st(<N>) in the hash table, as
3132 parentheses aren't included in register_chars[] anyway. */
3133 if (regtab
->reg_type
.bitfield
.instance
!= Accum
)
3140 switch (regtab
->reg_num
)
3142 case 0: reg_es
= regtab
; break;
3143 case 2: reg_ss
= regtab
; break;
3144 case 3: reg_ds
= regtab
; break;
3149 if (!regtab
->reg_num
)
3154 if (str_hash_insert (reg_hash
, regtab
->reg_name
, regtab
, 0) != NULL
)
3155 as_fatal (_("duplicate %s"), regtab
->reg_name
);
3159 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3164 for (c
= 0; c
< 256; c
++)
3166 if (ISDIGIT (c
) || ISLOWER (c
))
3168 mnemonic_chars
[c
] = c
;
3169 register_chars
[c
] = c
;
3170 operand_chars
[c
] = c
;
3172 else if (ISUPPER (c
))
3174 mnemonic_chars
[c
] = TOLOWER (c
);
3175 register_chars
[c
] = mnemonic_chars
[c
];
3176 operand_chars
[c
] = c
;
3178 #ifdef SVR4_COMMENT_CHARS
3179 else if (c
== '\\' && strchr (i386_comment_chars
, '/'))
3180 operand_chars
[c
] = c
;
3184 operand_chars
[c
] = c
;
3187 mnemonic_chars
['_'] = '_';
3188 mnemonic_chars
['-'] = '-';
3189 mnemonic_chars
['.'] = '.';
3191 for (p
= extra_symbol_chars
; *p
!= '\0'; p
++)
3192 operand_chars
[(unsigned char) *p
] = *p
;
3193 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
3194 operand_chars
[(unsigned char) *p
] = *p
;
3197 if (flag_code
== CODE_64BIT
)
3199 #if defined (OBJ_COFF) && defined (TE_PE)
3200 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
3203 x86_dwarf2_return_column
= 16;
3205 x86_cie_data_alignment
= -8;
3206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3207 x86_sframe_cfa_sp_reg
= 7;
3208 x86_sframe_cfa_fp_reg
= 6;
3213 x86_dwarf2_return_column
= 8;
3214 x86_cie_data_alignment
= -4;
3217 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3218 can be turned into BRANCH_PREFIX frag. */
3219 if (align_branch_prefix_size
> MAX_FUSED_JCC_PADDING_SIZE
)
3224 i386_print_statistics (FILE *file
)
3226 htab_print_statistics (file
, "i386 opcode", op_hash
);
3227 htab_print_statistics (file
, "i386 register", reg_hash
);
3233 htab_delete (op_hash
);
3234 htab_delete (reg_hash
);
3239 /* Debugging routines for md_assemble. */
3240 static void pte (insn_template
*);
3241 static void pt (i386_operand_type
);
3242 static void pe (expressionS
*);
3243 static void ps (symbolS
*);
3246 pi (const char *line
, i386_insn
*x
)
3250 fprintf (stdout
, "%s: template ", line
);
3252 fprintf (stdout
, " address: base %s index %s scale %x\n",
3253 x
->base_reg
? x
->base_reg
->reg_name
: "none",
3254 x
->index_reg
? x
->index_reg
->reg_name
: "none",
3255 x
->log2_scale_factor
);
3256 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
3257 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
3258 fprintf (stdout
, " sib: base %x index %x scale %x\n",
3259 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
3260 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
3261 (x
->rex
& REX_W
) != 0,
3262 (x
->rex
& REX_R
) != 0,
3263 (x
->rex
& REX_X
) != 0,
3264 (x
->rex
& REX_B
) != 0);
3265 for (j
= 0; j
< x
->operands
; j
++)
3267 fprintf (stdout
, " #%d: ", j
+ 1);
3269 fprintf (stdout
, "\n");
3270 if (x
->types
[j
].bitfield
.class == Reg
3271 || x
->types
[j
].bitfield
.class == RegMMX
3272 || x
->types
[j
].bitfield
.class == RegSIMD
3273 || x
->types
[j
].bitfield
.class == RegMask
3274 || x
->types
[j
].bitfield
.class == SReg
3275 || x
->types
[j
].bitfield
.class == RegCR
3276 || x
->types
[j
].bitfield
.class == RegDR
3277 || x
->types
[j
].bitfield
.class == RegTR
3278 || x
->types
[j
].bitfield
.class == RegBND
)
3279 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
3280 if (operand_type_check (x
->types
[j
], imm
))
3282 if (operand_type_check (x
->types
[j
], disp
))
3283 pe (x
->op
[j
].disps
);
3288 pte (insn_template
*t
)
3290 static const unsigned char opc_pfx
[] = { 0, 0x66, 0xf3, 0xf2 };
3291 static const char *const opc_spc
[] = {
3292 NULL
, "0f", "0f38", "0f3a", NULL
, "evexmap5", "evexmap6", NULL
,
3293 "XOP08", "XOP09", "XOP0A",
3297 fprintf (stdout
, " %d operands ", t
->operands
);
3298 if (opc_pfx
[t
->opcode_modifier
.opcodeprefix
])
3299 fprintf (stdout
, "pfx %x ", opc_pfx
[t
->opcode_modifier
.opcodeprefix
]);
3300 if (opc_spc
[t
->opcode_space
])
3301 fprintf (stdout
, "space %s ", opc_spc
[t
->opcode_space
]);
3302 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
3303 if (t
->extension_opcode
!= None
)
3304 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
3305 if (t
->opcode_modifier
.d
)
3306 fprintf (stdout
, "D");
3307 if (t
->opcode_modifier
.w
)
3308 fprintf (stdout
, "W");
3309 fprintf (stdout
, "\n");
3310 for (j
= 0; j
< t
->operands
; j
++)
3312 fprintf (stdout
, " #%d type ", j
+ 1);
3313 pt (t
->operand_types
[j
]);
3314 fprintf (stdout
, "\n");
3321 fprintf (stdout
, " operation %d\n", e
->X_op
);
3322 fprintf (stdout
, " add_number %" PRId64
" (%" PRIx64
")\n",
3323 (int64_t) e
->X_add_number
, (uint64_t) (valueT
) e
->X_add_number
);
3324 if (e
->X_add_symbol
)
3326 fprintf (stdout
, " add_symbol ");
3327 ps (e
->X_add_symbol
);
3328 fprintf (stdout
, "\n");
3332 fprintf (stdout
, " op_symbol ");
3333 ps (e
->X_op_symbol
);
3334 fprintf (stdout
, "\n");
3341 fprintf (stdout
, "%s type %s%s",
3343 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
3344 segment_name (S_GET_SEGMENT (s
)));
3347 static struct type_name
3349 i386_operand_type mask
;
3352 const type_names
[] =
3354 { { .bitfield
= { .class = Reg
, .byte
= 1 } }, "r8" },
3355 { { .bitfield
= { .class = Reg
, .word
= 1 } }, "r16" },
3356 { { .bitfield
= { .class = Reg
, .dword
= 1 } }, "r32" },
3357 { { .bitfield
= { .class = Reg
, .qword
= 1 } }, "r64" },
3358 { { .bitfield
= { .instance
= Accum
, .byte
= 1 } }, "acc8" },
3359 { { .bitfield
= { .instance
= Accum
, .word
= 1 } }, "acc16" },
3360 { { .bitfield
= { .instance
= Accum
, .dword
= 1 } }, "acc32" },
3361 { { .bitfield
= { .instance
= Accum
, .qword
= 1 } }, "acc64" },
3362 { { .bitfield
= { .imm8
= 1 } }, "i8" },
3363 { { .bitfield
= { .imm8s
= 1 } }, "i8s" },
3364 { { .bitfield
= { .imm16
= 1 } }, "i16" },
3365 { { .bitfield
= { .imm32
= 1 } }, "i32" },
3366 { { .bitfield
= { .imm32s
= 1 } }, "i32s" },
3367 { { .bitfield
= { .imm64
= 1 } }, "i64" },
3368 { { .bitfield
= { .imm1
= 1 } }, "i1" },
3369 { { .bitfield
= { .baseindex
= 1 } }, "BaseIndex" },
3370 { { .bitfield
= { .disp8
= 1 } }, "d8" },
3371 { { .bitfield
= { .disp16
= 1 } }, "d16" },
3372 { { .bitfield
= { .disp32
= 1 } }, "d32" },
3373 { { .bitfield
= { .disp64
= 1 } }, "d64" },
3374 { { .bitfield
= { .instance
= RegD
, .word
= 1 } }, "InOutPortReg" },
3375 { { .bitfield
= { .instance
= RegC
, .byte
= 1 } }, "ShiftCount" },
3376 { { .bitfield
= { .class = RegCR
} }, "control reg" },
3377 { { .bitfield
= { .class = RegTR
} }, "test reg" },
3378 { { .bitfield
= { .class = RegDR
} }, "debug reg" },
3379 { { .bitfield
= { .class = Reg
, .tbyte
= 1 } }, "FReg" },
3380 { { .bitfield
= { .instance
= Accum
, .tbyte
= 1 } }, "FAcc" },
3381 { { .bitfield
= { .class = SReg
} }, "SReg" },
3382 { { .bitfield
= { .class = RegMMX
} }, "rMMX" },
3383 { { .bitfield
= { .class = RegSIMD
, .xmmword
= 1 } }, "rXMM" },
3384 { { .bitfield
= { .class = RegSIMD
, .ymmword
= 1 } }, "rYMM" },
3385 { { .bitfield
= { .class = RegSIMD
, .zmmword
= 1 } }, "rZMM" },
3386 { { .bitfield
= { .class = RegSIMD
, .tmmword
= 1 } }, "rTMM" },
3387 { { .bitfield
= { .class = RegMask
} }, "Mask reg" },
3391 pt (i386_operand_type t
)
3394 i386_operand_type a
;
3396 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
3398 a
= operand_type_and (t
, type_names
[j
].mask
);
3399 if (operand_type_equal (&a
, &type_names
[j
].mask
))
3400 fprintf (stdout
, "%s, ", type_names
[j
].name
);
3405 #endif /* DEBUG386 */
3407 static bfd_reloc_code_real_type
3408 reloc (unsigned int size
,
3411 bfd_reloc_code_real_type other
)
3413 if (other
!= NO_RELOC
)
3415 reloc_howto_type
*rel
;
3420 case BFD_RELOC_X86_64_GOT32
:
3421 return BFD_RELOC_X86_64_GOT64
;
3423 case BFD_RELOC_X86_64_GOTPLT64
:
3424 return BFD_RELOC_X86_64_GOTPLT64
;
3426 case BFD_RELOC_X86_64_PLTOFF64
:
3427 return BFD_RELOC_X86_64_PLTOFF64
;
3429 case BFD_RELOC_X86_64_GOTPC32
:
3430 other
= BFD_RELOC_X86_64_GOTPC64
;
3432 case BFD_RELOC_X86_64_GOTPCREL
:
3433 other
= BFD_RELOC_X86_64_GOTPCREL64
;
3435 case BFD_RELOC_X86_64_TPOFF32
:
3436 other
= BFD_RELOC_X86_64_TPOFF64
;
3438 case BFD_RELOC_X86_64_DTPOFF32
:
3439 other
= BFD_RELOC_X86_64_DTPOFF64
;
3445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3446 if (other
== BFD_RELOC_SIZE32
)
3449 other
= BFD_RELOC_SIZE64
;
3452 as_bad (_("there are no pc-relative size relocations"));
3458 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3459 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
3462 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
3464 as_bad (_("unknown relocation (%u)"), other
);
3465 else if (size
!= bfd_get_reloc_size (rel
))
3466 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3467 bfd_get_reloc_size (rel
),
3469 else if (pcrel
&& !rel
->pc_relative
)
3470 as_bad (_("non-pc-relative relocation for pc-relative field"));
3471 else if ((rel
->complain_on_overflow
== complain_overflow_signed
3473 || (rel
->complain_on_overflow
== complain_overflow_unsigned
3475 as_bad (_("relocated field and relocation type differ in signedness"));
3484 as_bad (_("there are no unsigned pc-relative relocations"));
3487 case 1: return BFD_RELOC_8_PCREL
;
3488 case 2: return BFD_RELOC_16_PCREL
;
3489 case 4: return BFD_RELOC_32_PCREL
;
3490 case 8: return BFD_RELOC_64_PCREL
;
3492 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
3499 case 4: return BFD_RELOC_X86_64_32S
;
3504 case 1: return BFD_RELOC_8
;
3505 case 2: return BFD_RELOC_16
;
3506 case 4: return BFD_RELOC_32
;
3507 case 8: return BFD_RELOC_64
;
3509 as_bad (_("cannot do %s %u byte relocation"),
3510 sign
> 0 ? "signed" : "unsigned", size
);
3516 /* Here we decide which fixups can be adjusted to make them relative to
3517 the beginning of the section instead of the symbol. Basically we need
3518 to make sure that the dynamic relocations are done correctly, so in
3519 some cases we force the original symbol to be used. */
3522 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
3524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3528 /* Don't adjust pc-relative references to merge sections in 64-bit
3530 if (use_rela_relocations
3531 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
3535 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3536 and changed later by validate_fix. */
3537 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
3538 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
3541 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3542 for size relocations. */
3543 if (fixP
->fx_r_type
== BFD_RELOC_SIZE32
3544 || fixP
->fx_r_type
== BFD_RELOC_SIZE64
3545 || fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
3546 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
3547 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32X
3548 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
3549 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
3550 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
3551 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
3552 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
3553 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
3554 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
3555 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
3556 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
3557 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
3558 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
3559 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
3560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCRELX
3561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_REX_GOTPCRELX
3562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
3563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
3564 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
3565 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
3566 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
3567 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
3568 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
3569 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
3570 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
3571 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
3572 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
3573 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3580 want_disp32 (const insn_template
*t
)
3582 return flag_code
!= CODE_64BIT
3583 || i
.prefix
[ADDR_PREFIX
]
3584 || (t
->mnem_off
== MN_lea
3585 && (!i
.types
[1].bitfield
.qword
3586 || t
->opcode_modifier
.size
== SIZE32
));
3590 intel_float_operand (const char *mnemonic
)
3592 /* Note that the value returned is meaningful only for opcodes with (memory)
3593 operands, hence the code here is free to improperly handle opcodes that
3594 have no operands (for better performance and smaller code). */
3596 if (mnemonic
[0] != 'f')
3597 return 0; /* non-math */
3599 switch (mnemonic
[1])
3601 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3602 the fs segment override prefix not currently handled because no
3603 call path can make opcodes without operands get here */
3605 return 2 /* integer op */;
3607 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
3608 return 3; /* fldcw/fldenv */
3611 if (mnemonic
[2] != 'o' /* fnop */)
3612 return 3; /* non-waiting control op */
3615 if (mnemonic
[2] == 's')
3616 return 3; /* frstor/frstpm */
3619 if (mnemonic
[2] == 'a')
3620 return 3; /* fsave */
3621 if (mnemonic
[2] == 't')
3623 switch (mnemonic
[3])
3625 case 'c': /* fstcw */
3626 case 'd': /* fstdw */
3627 case 'e': /* fstenv */
3628 case 's': /* fsts[gw] */
3634 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
3635 return 0; /* fxsave/fxrstor are not really math ops */
3643 install_template (const insn_template
*t
)
3649 /* Note that for pseudo prefixes this produces a length of 1. But for them
3650 the length isn't interesting at all. */
3651 for (l
= 1; l
< 4; ++l
)
3652 if (!(t
->base_opcode
>> (8 * l
)))
3655 i
.opcode_length
= l
;
3658 /* Build the VEX prefix. */
3661 build_vex_prefix (const insn_template
*t
)
3663 unsigned int register_specifier
;
3664 unsigned int vector_length
;
3667 /* Check register specifier. */
3668 if (i
.vex
.register_specifier
)
3670 register_specifier
=
3671 ~register_number (i
.vex
.register_specifier
) & 0xf;
3672 gas_assert ((i
.vex
.register_specifier
->reg_flags
& RegVRex
) == 0);
3675 register_specifier
= 0xf;
3677 /* Use 2-byte VEX prefix by swapping destination and source operand
3678 if there are more than 1 register operand. */
3679 if (i
.reg_operands
> 1
3680 && i
.vec_encoding
!= vex_encoding_vex3
3681 && i
.dir_encoding
== dir_encoding_default
3682 && i
.operands
== i
.reg_operands
3683 && operand_type_equal (&i
.types
[0], &i
.types
[i
.operands
- 1])
3684 && i
.tm
.opcode_space
== SPACE_0F
3685 && (i
.tm
.opcode_modifier
.load
|| i
.tm
.opcode_modifier
.d
)
3690 swap_2_operands (0, i
.operands
- 1);
3692 gas_assert (i
.rm
.mode
== 3);
3696 i
.rm
.regmem
= i
.rm
.reg
;
3699 if (i
.tm
.opcode_modifier
.d
)
3700 i
.tm
.base_opcode
^= (i
.tm
.base_opcode
& 0xee) != 0x6e
3701 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
3702 else /* Use the next insn. */
3703 install_template (&t
[1]);
3706 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3707 are no memory operands and at least 3 register ones. */
3708 if (i
.reg_operands
>= 3
3709 && i
.vec_encoding
!= vex_encoding_vex3
3710 && i
.reg_operands
== i
.operands
- i
.imm_operands
3711 && i
.tm
.opcode_modifier
.vex
3712 && i
.tm
.opcode_modifier
.commutative
3713 && (i
.tm
.opcode_modifier
.sse2avx
3714 || (optimize
> 1 && !i
.no_optimize
))
3716 && i
.vex
.register_specifier
3717 && !(i
.vex
.register_specifier
->reg_flags
& RegRex
))
3719 unsigned int xchg
= i
.operands
- i
.reg_operands
;
3721 gas_assert (i
.tm
.opcode_space
== SPACE_0F
);
3722 gas_assert (!i
.tm
.opcode_modifier
.sae
);
3723 gas_assert (operand_type_equal (&i
.types
[i
.operands
- 2],
3724 &i
.types
[i
.operands
- 3]));
3725 gas_assert (i
.rm
.mode
== 3);
3727 swap_2_operands (xchg
, xchg
+ 1);
3730 xchg
= i
.rm
.regmem
| 8;
3731 i
.rm
.regmem
= ~register_specifier
& 0xf;
3732 gas_assert (!(i
.rm
.regmem
& 8));
3733 i
.vex
.register_specifier
+= xchg
- i
.rm
.regmem
;
3734 register_specifier
= ~xchg
& 0xf;
3737 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
3738 vector_length
= avxscalar
;
3739 else if (i
.tm
.opcode_modifier
.vex
== VEX256
)
3741 else if (dot_insn () && i
.tm
.opcode_modifier
.vex
== VEX128
)
3747 /* Determine vector length from the last multi-length vector
3750 for (op
= t
->operands
; op
--;)
3751 if (t
->operand_types
[op
].bitfield
.xmmword
3752 && t
->operand_types
[op
].bitfield
.ymmword
3753 && i
.types
[op
].bitfield
.ymmword
)
3760 /* Check the REX.W bit and VEXW. */
3761 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3762 w
= (vexwig
== vexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3763 else if (i
.tm
.opcode_modifier
.vexw
)
3764 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3766 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: vexwig
== vexw1
) ? 1 : 0;
3768 /* Use 2-byte VEX prefix if possible. */
3770 && i
.vec_encoding
!= vex_encoding_vex3
3771 && i
.tm
.opcode_space
== SPACE_0F
3772 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
3774 /* 2-byte VEX prefix. */
3778 i
.vex
.bytes
[0] = 0xc5;
3780 /* Check the REX.R bit. */
3781 r
= (i
.rex
& REX_R
) ? 0 : 1;
3782 i
.vex
.bytes
[1] = (r
<< 7
3783 | register_specifier
<< 3
3784 | vector_length
<< 2
3785 | i
.tm
.opcode_modifier
.opcodeprefix
);
3789 /* 3-byte VEX prefix. */
3792 switch (i
.tm
.opcode_space
)
3797 i
.vex
.bytes
[0] = 0xc4;
3802 i
.vex
.bytes
[0] = 0x8f;
3808 /* The high 3 bits of the second VEX byte are 1's compliment
3809 of RXB bits from REX. */
3810 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3811 | (!dot_insn () ? i
.tm
.opcode_space
3812 : i
.insn_opcode_space
);
3814 i
.vex
.bytes
[2] = (w
<< 7
3815 | register_specifier
<< 3
3816 | vector_length
<< 2
3817 | i
.tm
.opcode_modifier
.opcodeprefix
);
3822 is_evex_encoding (const insn_template
*t
)
3824 return t
->opcode_modifier
.evex
|| t
->opcode_modifier
.disp8memshift
3825 || t
->opcode_modifier
.broadcast
|| t
->opcode_modifier
.masking
3826 || t
->opcode_modifier
.sae
;
3830 is_any_vex_encoding (const insn_template
*t
)
3832 return t
->opcode_modifier
.vex
|| is_evex_encoding (t
);
3836 get_broadcast_bytes (const insn_template
*t
, bool diag
)
3838 unsigned int op
, bytes
;
3839 const i386_operand_type
*types
;
3841 if (i
.broadcast
.type
)
3842 return (1 << (t
->opcode_modifier
.broadcast
- 1)) * i
.broadcast
.type
;
3844 gas_assert (intel_syntax
);
3846 for (op
= 0; op
< t
->operands
; ++op
)
3847 if (t
->operand_types
[op
].bitfield
.baseindex
)
3850 gas_assert (op
< t
->operands
);
3852 if (t
->opcode_modifier
.evex
3853 && t
->opcode_modifier
.evex
!= EVEXDYN
)
3854 switch (i
.broadcast
.bytes
)
3857 if (t
->operand_types
[op
].bitfield
.word
)
3861 if (t
->operand_types
[op
].bitfield
.dword
)
3865 if (t
->operand_types
[op
].bitfield
.qword
)
3869 if (t
->operand_types
[op
].bitfield
.xmmword
)
3871 if (t
->operand_types
[op
].bitfield
.ymmword
)
3873 if (t
->operand_types
[op
].bitfield
.zmmword
)
3880 gas_assert (op
+ 1 < t
->operands
);
3882 if (t
->operand_types
[op
+ 1].bitfield
.xmmword
3883 + t
->operand_types
[op
+ 1].bitfield
.ymmword
3884 + t
->operand_types
[op
+ 1].bitfield
.zmmword
> 1)
3886 types
= &i
.types
[op
+ 1];
3889 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
3890 types
= &t
->operand_types
[op
];
3892 if (types
->bitfield
.zmmword
)
3894 else if (types
->bitfield
.ymmword
)
3900 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
3901 insn_name (t
), bytes
* 8);
3906 /* Build the EVEX prefix. */
3909 build_evex_prefix (void)
3911 unsigned int register_specifier
, w
;
3912 rex_byte vrex_used
= 0;
3914 /* Check register specifier. */
3915 if (i
.vex
.register_specifier
)
3917 gas_assert ((i
.vrex
& REX_X
) == 0);
3919 register_specifier
= i
.vex
.register_specifier
->reg_num
;
3920 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
3921 register_specifier
+= 8;
3922 /* The upper 16 registers are encoded in the fourth byte of the
3924 if (!(i
.vex
.register_specifier
->reg_flags
& RegVRex
))
3925 i
.vex
.bytes
[3] = 0x8;
3926 register_specifier
= ~register_specifier
& 0xf;
3930 register_specifier
= 0xf;
3932 /* Encode upper 16 vector index register in the fourth byte of
3934 if (!(i
.vrex
& REX_X
))
3935 i
.vex
.bytes
[3] = 0x8;
3940 /* 4 byte EVEX prefix. */
3942 i
.vex
.bytes
[0] = 0x62;
3944 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3946 gas_assert (i
.tm
.opcode_space
>= SPACE_0F
);
3947 gas_assert (i
.tm
.opcode_space
<= SPACE_EVEXMAP6
);
3948 i
.vex
.bytes
[1] = ((~i
.rex
& 7) << 5)
3949 | (!dot_insn () ? i
.tm
.opcode_space
3950 : i
.insn_opcode_space
);
3952 /* The fifth bit of the second EVEX byte is 1's compliment of the
3953 REX_R bit in VREX. */
3954 if (!(i
.vrex
& REX_R
))
3955 i
.vex
.bytes
[1] |= 0x10;
3959 if ((i
.reg_operands
+ i
.imm_operands
) == i
.operands
)
3961 /* When all operands are registers, the REX_X bit in REX is not
3962 used. We reuse it to encode the upper 16 registers, which is
3963 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3964 as 1's compliment. */
3965 if ((i
.vrex
& REX_B
))
3968 i
.vex
.bytes
[1] &= ~0x40;
3972 /* EVEX instructions shouldn't need the REX prefix. */
3973 i
.vrex
&= ~vrex_used
;
3974 gas_assert (i
.vrex
== 0);
3976 /* Check the REX.W bit and VEXW. */
3977 if (i
.tm
.opcode_modifier
.vexw
== VEXWIG
)
3978 w
= (evexwig
== evexw1
|| (i
.rex
& REX_W
)) ? 1 : 0;
3979 else if (i
.tm
.opcode_modifier
.vexw
)
3980 w
= i
.tm
.opcode_modifier
.vexw
== VEXW1
? 1 : 0;
3982 w
= (flag_code
== CODE_64BIT
? i
.rex
& REX_W
: evexwig
== evexw1
) ? 1 : 0;
3984 /* The third byte of the EVEX prefix. */
3985 i
.vex
.bytes
[2] = ((w
<< 7)
3986 | (register_specifier
<< 3)
3987 | 4 /* Encode the U bit. */
3988 | i
.tm
.opcode_modifier
.opcodeprefix
);
3990 /* The fourth byte of the EVEX prefix. */
3991 /* The zeroing-masking bit. */
3992 if (i
.mask
.reg
&& i
.mask
.zeroing
)
3993 i
.vex
.bytes
[3] |= 0x80;
3995 /* Don't always set the broadcast bit if there is no RC. */
3996 if (i
.rounding
.type
== rc_none
)
3998 /* Encode the vector length. */
3999 unsigned int vec_length
;
4001 if (!i
.tm
.opcode_modifier
.evex
4002 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
4006 /* Determine vector length from the last multi-length vector
4008 for (op
= i
.operands
; op
--;)
4009 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
4010 + i
.tm
.operand_types
[op
].bitfield
.ymmword
4011 + i
.tm
.operand_types
[op
].bitfield
.zmmword
> 1)
4013 if (i
.types
[op
].bitfield
.zmmword
)
4015 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4018 else if (i
.types
[op
].bitfield
.ymmword
)
4020 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4023 else if (i
.types
[op
].bitfield
.xmmword
)
4025 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4028 else if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
4029 && op
== i
.broadcast
.operand
)
4031 switch (get_broadcast_bytes (&i
.tm
, true))
4034 i
.tm
.opcode_modifier
.evex
= EVEX512
;
4037 i
.tm
.opcode_modifier
.evex
= EVEX256
;
4040 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4049 if (op
>= MAX_OPERANDS
)
4053 switch (i
.tm
.opcode_modifier
.evex
)
4055 case EVEXLIG
: /* LL' is ignored */
4056 vec_length
= evexlig
<< 5;
4059 vec_length
= 0 << 5;
4062 vec_length
= 1 << 5;
4065 vec_length
= 2 << 5;
4070 vec_length
= 3 << 5;
4078 i
.vex
.bytes
[3] |= vec_length
;
4079 /* Encode the broadcast bit. */
4080 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
4081 i
.vex
.bytes
[3] |= 0x10;
4083 else if (i
.rounding
.type
!= saeonly
)
4084 i
.vex
.bytes
[3] |= 0x10 | (i
.rounding
.type
<< 5);
4086 i
.vex
.bytes
[3] |= 0x10 | (evexrcig
<< 5);
4089 i
.vex
.bytes
[3] |= i
.mask
.reg
->reg_num
;
4093 process_immext (void)
4097 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4098 which is coded in the same place as an 8-bit immediate field
4099 would be. Here we fake an 8-bit immediate operand from the
4100 opcode suffix stored in tm.extension_opcode.
4102 AVX instructions also use this encoding, for some of
4103 3 argument instructions. */
4105 gas_assert (i
.imm_operands
<= 1
4107 || (is_any_vex_encoding (&i
.tm
)
4108 && i
.operands
<= 4)));
4110 exp
= &im_expressions
[i
.imm_operands
++];
4111 i
.op
[i
.operands
].imms
= exp
;
4112 i
.types
[i
.operands
].bitfield
.imm8
= 1;
4114 exp
->X_op
= O_constant
;
4115 exp
->X_add_number
= i
.tm
.extension_opcode
;
4116 i
.tm
.extension_opcode
= None
;
4123 switch (i
.tm
.opcode_modifier
.prefixok
)
4131 as_bad (_("invalid instruction `%s' after `%s'"),
4132 insn_name (&i
.tm
), i
.hle_prefix
);
4135 if (i
.prefix
[LOCK_PREFIX
])
4137 as_bad (_("missing `lock' with `%s'"), i
.hle_prefix
);
4141 case PrefixHLERelease
:
4142 if (i
.prefix
[HLE_PREFIX
] != XRELEASE_PREFIX_OPCODE
)
4144 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4148 if (i
.mem_operands
== 0 || !(i
.flags
[i
.operands
- 1] & Operand_Mem
))
4150 as_bad (_("memory destination needed for instruction `%s'"
4151 " after `xrelease'"), insn_name (&i
.tm
));
4158 /* Encode aligned vector move as unaligned vector move. */
4161 encode_with_unaligned_vector_move (void)
4163 switch (i
.tm
.base_opcode
)
4165 case 0x28: /* Load instructions. */
4166 case 0x29: /* Store instructions. */
4167 /* movaps/movapd/vmovaps/vmovapd. */
4168 if (i
.tm
.opcode_space
== SPACE_0F
4169 && i
.tm
.opcode_modifier
.opcodeprefix
<= PREFIX_0X66
)
4170 i
.tm
.base_opcode
= 0x10 | (i
.tm
.base_opcode
& 1);
4172 case 0x6f: /* Load instructions. */
4173 case 0x7f: /* Store instructions. */
4174 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4175 if (i
.tm
.opcode_space
== SPACE_0F
4176 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0X66
)
4177 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4184 /* Try the shortest encoding by shortening operand size. */
4187 optimize_encoding (void)
4191 if (i
.tm
.mnem_off
== MN_lea
)
4194 lea symbol, %rN -> mov $symbol, %rN
4195 lea (%rM), %rN -> mov %rM, %rN
4196 lea (,%rM,1), %rN -> mov %rM, %rN
4198 and in 32-bit mode for 16-bit addressing
4200 lea (%rM), %rN -> movzx %rM, %rN
4202 and in 64-bit mode zap 32-bit addressing in favor of using a
4203 32-bit (or less) destination.
4205 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
4207 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4208 i
.tm
.opcode_modifier
.size
= SIZE32
;
4209 i
.prefix
[ADDR_PREFIX
] = 0;
4212 if (!i
.index_reg
&& !i
.base_reg
)
4215 lea symbol, %rN -> mov $symbol, %rN
4217 if (flag_code
== CODE_64BIT
)
4219 /* Don't transform a relocation to a 16-bit one. */
4221 && i
.op
[0].disps
->X_op
!= O_constant
4222 && i
.op
[1].regs
->reg_type
.bitfield
.word
)
4225 if (!i
.op
[1].regs
->reg_type
.bitfield
.qword
4226 || i
.tm
.opcode_modifier
.size
== SIZE32
)
4228 i
.tm
.base_opcode
= 0xb8;
4229 i
.tm
.opcode_modifier
.modrm
= 0;
4230 if (!i
.op
[1].regs
->reg_type
.bitfield
.word
)
4231 i
.types
[0].bitfield
.imm32
= 1;
4234 i
.tm
.opcode_modifier
.size
= SIZE16
;
4235 i
.types
[0].bitfield
.imm16
= 1;
4240 /* Subject to further optimization below. */
4241 i
.tm
.base_opcode
= 0xc7;
4242 i
.tm
.extension_opcode
= 0;
4243 i
.types
[0].bitfield
.imm32s
= 1;
4244 i
.types
[0].bitfield
.baseindex
= 0;
4247 /* Outside of 64-bit mode address and operand sizes have to match if
4248 a relocation is involved, as otherwise we wouldn't (currently) or
4249 even couldn't express the relocation correctly. */
4250 else if (i
.op
[0].disps
4251 && i
.op
[0].disps
->X_op
!= O_constant
4252 && ((!i
.prefix
[ADDR_PREFIX
])
4253 != (flag_code
== CODE_32BIT
4254 ? i
.op
[1].regs
->reg_type
.bitfield
.dword
4255 : i
.op
[1].regs
->reg_type
.bitfield
.word
)))
4257 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4258 destination is going to grow encoding size. */
4259 else if (flag_code
== CODE_16BIT
4260 && (optimize
<= 1 || optimize_for_space
)
4261 && !i
.prefix
[ADDR_PREFIX
]
4262 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4266 i
.tm
.base_opcode
= 0xb8;
4267 i
.tm
.opcode_modifier
.modrm
= 0;
4268 if (i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4269 i
.types
[0].bitfield
.imm32
= 1;
4271 i
.types
[0].bitfield
.imm16
= 1;
4274 && i
.op
[0].disps
->X_op
== O_constant
4275 && i
.op
[1].regs
->reg_type
.bitfield
.dword
4276 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4278 && (!i
.prefix
[ADDR_PREFIX
]) != (flag_code
== CODE_32BIT
))
4279 i
.op
[0].disps
->X_add_number
&= 0xffff;
4282 i
.tm
.operand_types
[0] = i
.types
[0];
4286 i
.op
[0].imms
= &im_expressions
[0];
4287 i
.op
[0].imms
->X_op
= O_absent
;
4290 else if (i
.op
[0].disps
4291 && (i
.op
[0].disps
->X_op
!= O_constant
4292 || i
.op
[0].disps
->X_add_number
))
4297 lea (%rM), %rN -> mov %rM, %rN
4298 lea (,%rM,1), %rN -> mov %rM, %rN
4299 lea (%rM), %rN -> movzx %rM, %rN
4301 const reg_entry
*addr_reg
;
4303 if (!i
.index_reg
&& i
.base_reg
->reg_num
!= RegIP
)
4304 addr_reg
= i
.base_reg
;
4305 else if (!i
.base_reg
4306 && i
.index_reg
->reg_num
!= RegIZ
4307 && !i
.log2_scale_factor
)
4308 addr_reg
= i
.index_reg
;
4312 if (addr_reg
->reg_type
.bitfield
.word
4313 && i
.op
[1].regs
->reg_type
.bitfield
.dword
)
4315 if (flag_code
!= CODE_32BIT
)
4317 i
.tm
.opcode_space
= SPACE_0F
;
4318 i
.tm
.base_opcode
= 0xb7;
4321 i
.tm
.base_opcode
= 0x8b;
4323 if (addr_reg
->reg_type
.bitfield
.dword
4324 && i
.op
[1].regs
->reg_type
.bitfield
.qword
)
4325 i
.tm
.opcode_modifier
.size
= SIZE32
;
4327 i
.op
[0].regs
= addr_reg
;
4332 i
.disp_operands
= 0;
4333 i
.prefix
[ADDR_PREFIX
] = 0;
4334 i
.prefix
[SEG_PREFIX
] = 0;
4338 if (optimize_for_space
4339 && i
.tm
.mnem_off
== MN_test
4340 && i
.reg_operands
== 1
4341 && i
.imm_operands
== 1
4342 && !i
.types
[1].bitfield
.byte
4343 && i
.op
[0].imms
->X_op
== O_constant
4344 && fits_in_imm7 (i
.op
[0].imms
->X_add_number
))
4347 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4349 unsigned int base_regnum
= i
.op
[1].regs
->reg_num
;
4350 if (flag_code
== CODE_64BIT
|| base_regnum
< 4)
4352 i
.types
[1].bitfield
.byte
= 1;
4353 /* Ignore the suffix. */
4355 /* Convert to byte registers. */
4356 if (i
.types
[1].bitfield
.word
)
4358 else if (i
.types
[1].bitfield
.dword
)
4362 if (!(i
.op
[1].regs
->reg_flags
& RegRex
) && base_regnum
< 4)
4367 else if (flag_code
== CODE_64BIT
4368 && i
.tm
.opcode_space
== SPACE_BASE
4369 && ((i
.types
[1].bitfield
.qword
4370 && i
.reg_operands
== 1
4371 && i
.imm_operands
== 1
4372 && i
.op
[0].imms
->X_op
== O_constant
4373 && ((i
.tm
.base_opcode
== 0xb8
4374 && i
.tm
.extension_opcode
== None
4375 && fits_in_unsigned_long (i
.op
[0].imms
->X_add_number
))
4376 || (fits_in_imm31 (i
.op
[0].imms
->X_add_number
)
4377 && (i
.tm
.base_opcode
== 0x24
4378 || (i
.tm
.base_opcode
== 0x80
4379 && i
.tm
.extension_opcode
== 0x4)
4380 || i
.tm
.mnem_off
== MN_test
4381 || ((i
.tm
.base_opcode
| 1) == 0xc7
4382 && i
.tm
.extension_opcode
== 0x0)))
4383 || (fits_in_imm7 (i
.op
[0].imms
->X_add_number
)
4384 && i
.tm
.base_opcode
== 0x83
4385 && i
.tm
.extension_opcode
== 0x4)))
4386 || (i
.types
[0].bitfield
.qword
4387 && ((i
.reg_operands
== 2
4388 && i
.op
[0].regs
== i
.op
[1].regs
4389 && (i
.tm
.mnem_off
== MN_xor
4390 || i
.tm
.mnem_off
== MN_sub
))
4391 || i
.tm
.mnem_off
== MN_clr
))))
4394 andq $imm31, %r64 -> andl $imm31, %r32
4395 andq $imm7, %r64 -> andl $imm7, %r32
4396 testq $imm31, %r64 -> testl $imm31, %r32
4397 xorq %r64, %r64 -> xorl %r32, %r32
4398 subq %r64, %r64 -> subl %r32, %r32
4399 movq $imm31, %r64 -> movl $imm31, %r32
4400 movq $imm32, %r64 -> movl $imm32, %r32
4402 i
.tm
.opcode_modifier
.size
= SIZE32
;
4405 i
.types
[0].bitfield
.imm32
= 1;
4406 i
.types
[0].bitfield
.imm32s
= 0;
4407 i
.types
[0].bitfield
.imm64
= 0;
4411 i
.types
[0].bitfield
.dword
= 1;
4412 i
.types
[0].bitfield
.qword
= 0;
4414 i
.types
[1].bitfield
.dword
= 1;
4415 i
.types
[1].bitfield
.qword
= 0;
4416 if (i
.tm
.mnem_off
== MN_mov
|| i
.tm
.mnem_off
== MN_lea
)
4419 movq $imm31, %r64 -> movl $imm31, %r32
4420 movq $imm32, %r64 -> movl $imm32, %r32
4422 i
.tm
.operand_types
[0].bitfield
.imm32
= 1;
4423 i
.tm
.operand_types
[0].bitfield
.imm32s
= 0;
4424 i
.tm
.operand_types
[0].bitfield
.imm64
= 0;
4425 if ((i
.tm
.base_opcode
| 1) == 0xc7)
4428 movq $imm31, %r64 -> movl $imm31, %r32
4430 i
.tm
.base_opcode
= 0xb8;
4431 i
.tm
.extension_opcode
= None
;
4432 i
.tm
.opcode_modifier
.w
= 0;
4433 i
.tm
.opcode_modifier
.modrm
= 0;
4437 else if (optimize
> 1
4438 && !optimize_for_space
4439 && i
.reg_operands
== 2
4440 && i
.op
[0].regs
== i
.op
[1].regs
4441 && (i
.tm
.mnem_off
== MN_and
|| i
.tm
.mnem_off
== MN_or
)
4442 && (flag_code
!= CODE_64BIT
|| !i
.types
[0].bitfield
.dword
))
4445 andb %rN, %rN -> testb %rN, %rN
4446 andw %rN, %rN -> testw %rN, %rN
4447 andq %rN, %rN -> testq %rN, %rN
4448 orb %rN, %rN -> testb %rN, %rN
4449 orw %rN, %rN -> testw %rN, %rN
4450 orq %rN, %rN -> testq %rN, %rN
4452 and outside of 64-bit mode
4454 andl %rN, %rN -> testl %rN, %rN
4455 orl %rN, %rN -> testl %rN, %rN
4457 i
.tm
.base_opcode
= 0x84 | (i
.tm
.base_opcode
& 1);
4459 else if (i
.tm
.base_opcode
== 0xba
4460 && i
.tm
.opcode_space
== SPACE_0F
4461 && i
.reg_operands
== 1
4462 && i
.op
[0].imms
->X_op
== O_constant
4463 && i
.op
[0].imms
->X_add_number
>= 0)
4466 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4467 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4468 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4470 With <BT> one of bts, btr, and bts also:
4471 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4472 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4477 if (i
.tm
.extension_opcode
!= 4)
4479 if (i
.types
[1].bitfield
.qword
4480 && i
.op
[0].imms
->X_add_number
< 32
4481 && !(i
.op
[1].regs
->reg_flags
& RegRex
))
4482 i
.tm
.opcode_modifier
.size
= SIZE32
;
4485 if (i
.types
[1].bitfield
.word
4486 && i
.op
[0].imms
->X_add_number
< 16)
4487 i
.tm
.opcode_modifier
.size
= SIZE32
;
4490 if (i
.op
[0].imms
->X_add_number
< 16)
4491 i
.tm
.opcode_modifier
.size
= SIZE16
;
4495 else if (i
.reg_operands
== 3
4496 && i
.op
[0].regs
== i
.op
[1].regs
4497 && !i
.types
[2].bitfield
.xmmword
4498 && (i
.tm
.opcode_modifier
.vex
4499 || ((!i
.mask
.reg
|| i
.mask
.zeroing
)
4500 && is_evex_encoding (&i
.tm
)
4501 && (i
.vec_encoding
!= vex_encoding_evex
4502 || cpu_arch_isa_flags
.bitfield
.cpuavx512vl
4503 || is_cpu (&i
.tm
, CpuAVX512VL
)
4504 || (i
.tm
.operand_types
[2].bitfield
.zmmword
4505 && i
.types
[2].bitfield
.ymmword
))))
4506 && i
.tm
.opcode_space
== SPACE_0F
4507 && ((i
.tm
.base_opcode
| 2) == 0x57
4508 || i
.tm
.base_opcode
== 0xdf
4509 || i
.tm
.base_opcode
== 0xef
4510 || (i
.tm
.base_opcode
| 3) == 0xfb
4511 || i
.tm
.base_opcode
== 0x42
4512 || i
.tm
.base_opcode
== 0x47))
4515 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4517 EVEX VOP %zmmM, %zmmM, %zmmN
4518 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4519 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4520 EVEX VOP %ymmM, %ymmM, %ymmN
4521 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4522 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4523 VEX VOP %ymmM, %ymmM, %ymmN
4524 -> VEX VOP %xmmM, %xmmM, %xmmN
4525 VOP, one of vpandn and vpxor:
4526 VEX VOP %ymmM, %ymmM, %ymmN
4527 -> VEX VOP %xmmM, %xmmM, %xmmN
4528 VOP, one of vpandnd and vpandnq:
4529 EVEX VOP %zmmM, %zmmM, %zmmN
4530 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4531 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4532 EVEX VOP %ymmM, %ymmM, %ymmN
4533 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4534 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4535 VOP, one of vpxord and vpxorq:
4536 EVEX VOP %zmmM, %zmmM, %zmmN
4537 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4538 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4539 EVEX VOP %ymmM, %ymmM, %ymmN
4540 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4541 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4542 VOP, one of kxord and kxorq:
4543 VEX VOP %kM, %kM, %kN
4544 -> VEX kxorw %kM, %kM, %kN
4545 VOP, one of kandnd and kandnq:
4546 VEX VOP %kM, %kM, %kN
4547 -> VEX kandnw %kM, %kM, %kN
4549 if (is_evex_encoding (&i
.tm
))
4551 if (i
.vec_encoding
!= vex_encoding_evex
)
4553 i
.tm
.opcode_modifier
.vex
= VEX128
;
4554 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4555 i
.tm
.opcode_modifier
.evex
= 0;
4557 else if (optimize
> 1)
4558 i
.tm
.opcode_modifier
.evex
= EVEX128
;
4562 else if (i
.tm
.operand_types
[0].bitfield
.class == RegMask
)
4564 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_NONE
;
4565 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4568 i
.tm
.opcode_modifier
.vex
= VEX128
;
4570 if (i
.tm
.opcode_modifier
.vex
)
4571 for (j
= 0; j
< 3; j
++)
4573 i
.types
[j
].bitfield
.xmmword
= 1;
4574 i
.types
[j
].bitfield
.ymmword
= 0;
4577 else if (i
.vec_encoding
!= vex_encoding_evex
4578 && !i
.types
[0].bitfield
.zmmword
4579 && !i
.types
[1].bitfield
.zmmword
4581 && !i
.broadcast
.type
4582 && !i
.broadcast
.bytes
4583 && is_evex_encoding (&i
.tm
)
4584 && ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4585 || (i
.tm
.base_opcode
& ~4) == 0xdb
4586 || (i
.tm
.base_opcode
& ~4) == 0xeb)
4587 && i
.tm
.extension_opcode
== None
)
4590 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4591 vmovdqu32 and vmovdqu64:
4592 EVEX VOP %xmmM, %xmmN
4593 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4594 EVEX VOP %ymmM, %ymmN
4595 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4597 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4599 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4601 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4603 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4604 VOP, one of vpand, vpandn, vpor, vpxor:
4605 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4606 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4607 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4608 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4609 EVEX VOP{d,q} mem, %xmmM, %xmmN
4610 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4611 EVEX VOP{d,q} mem, %ymmM, %ymmN
4612 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4614 for (j
= 0; j
< i
.operands
; j
++)
4615 if (operand_type_check (i
.types
[j
], disp
)
4616 && i
.op
[j
].disps
->X_op
== O_constant
)
4618 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4619 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4620 bytes, we choose EVEX Disp8 over VEX Disp32. */
4621 int evex_disp8
, vex_disp8
;
4622 unsigned int memshift
= i
.memshift
;
4623 offsetT n
= i
.op
[j
].disps
->X_add_number
;
4625 evex_disp8
= fits_in_disp8 (n
);
4627 vex_disp8
= fits_in_disp8 (n
);
4628 if (evex_disp8
!= vex_disp8
)
4630 i
.memshift
= memshift
;
4634 i
.types
[j
].bitfield
.disp8
= vex_disp8
;
4637 if ((i
.tm
.base_opcode
& ~Opcode_SIMD_IntD
) == 0x6f
4638 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_0XF2
)
4639 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
4640 i
.tm
.opcode_modifier
.vex
4641 = i
.types
[0].bitfield
.ymmword
? VEX256
: VEX128
;
4642 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
4643 /* VPAND, VPOR, and VPXOR are commutative. */
4644 if (i
.reg_operands
== 3 && i
.tm
.base_opcode
!= 0xdf)
4645 i
.tm
.opcode_modifier
.commutative
= 1;
4646 i
.tm
.opcode_modifier
.evex
= 0;
4647 i
.tm
.opcode_modifier
.masking
= 0;
4648 i
.tm
.opcode_modifier
.broadcast
= 0;
4649 i
.tm
.opcode_modifier
.disp8memshift
= 0;
4652 i
.types
[j
].bitfield
.disp8
4653 = fits_in_disp8 (i
.op
[j
].disps
->X_add_number
);
4655 else if (optimize_for_space
4656 && i
.tm
.base_opcode
== 0x29
4657 && i
.tm
.opcode_space
== SPACE_0F38
4658 && i
.operands
== i
.reg_operands
4659 && i
.op
[0].regs
== i
.op
[1].regs
4660 && (!i
.tm
.opcode_modifier
.vex
4661 || !(i
.op
[0].regs
->reg_flags
& RegRex
))
4662 && !is_evex_encoding (&i
.tm
))
4665 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4666 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4667 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4669 i
.tm
.opcode_space
= SPACE_0F
;
4670 i
.tm
.base_opcode
= 0x76;
4672 else if (((i
.tm
.base_opcode
>= 0x64
4673 && i
.tm
.base_opcode
<= 0x66
4674 && i
.tm
.opcode_space
== SPACE_0F
)
4675 || (i
.tm
.base_opcode
== 0x37
4676 && i
.tm
.opcode_space
== SPACE_0F38
))
4677 && i
.operands
== i
.reg_operands
4678 && i
.op
[0].regs
== i
.op
[1].regs
4679 && !is_evex_encoding (&i
.tm
))
4682 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4683 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4684 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4685 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4686 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4687 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4689 i
.tm
.opcode_space
= SPACE_0F
;
4690 i
.tm
.base_opcode
= 0xef;
4691 if (i
.tm
.opcode_modifier
.vex
&& (i
.op
[0].regs
->reg_flags
& RegRex
))
4693 if (i
.operands
== 2)
4695 gas_assert (i
.tm
.opcode_modifier
.sse2avx
);
4701 i
.op
[2].regs
= i
.op
[0].regs
;
4702 i
.types
[2] = i
.types
[0];
4703 i
.flags
[2] = i
.flags
[0];
4704 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4706 i
.tm
.opcode_modifier
.sse2avx
= 0;
4708 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
+ 8;
4709 i
.op
[1].regs
= i
.op
[0].regs
;
4712 else if (optimize_for_space
4713 && i
.tm
.base_opcode
== 0x59
4714 && i
.tm
.opcode_space
== SPACE_0F38
4715 && i
.operands
== i
.reg_operands
4716 && i
.tm
.opcode_modifier
.vex
4717 && !(i
.op
[0].regs
->reg_flags
& RegRex
)
4718 && i
.op
[0].regs
->reg_type
.bitfield
.xmmword
4719 && i
.vec_encoding
!= vex_encoding_vex3
)
4722 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4724 i
.tm
.opcode_space
= SPACE_0F
;
4725 i
.tm
.base_opcode
= 0x6c;
4726 i
.tm
.opcode_modifier
.vexvvvv
= 1;
4732 i
.op
[2].regs
= i
.op
[0].regs
;
4733 i
.types
[2] = i
.types
[0];
4734 i
.flags
[2] = i
.flags
[0];
4735 i
.tm
.operand_types
[2] = i
.tm
.operand_types
[0];
4737 swap_2_operands (1, 2);
4741 /* Return non-zero for load instruction. */
4747 int any_vex_p
= is_any_vex_encoding (&i
.tm
);
4748 unsigned int base_opcode
= i
.tm
.base_opcode
| 1;
4752 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
4753 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
4754 if (i
.tm
.opcode_modifier
.operandconstraint
== ANY_SIZE
)
4758 if (i
.tm
.mnem_off
== MN_pop
)
4762 if (i
.tm
.opcode_space
== SPACE_BASE
)
4765 if (i
.tm
.base_opcode
== 0x9d
4766 || i
.tm
.base_opcode
== 0x61)
4769 /* movs, cmps, lods, scas. */
4770 if ((i
.tm
.base_opcode
| 0xb) == 0xaf)
4774 if (base_opcode
== 0x6f
4775 || i
.tm
.base_opcode
== 0xd7)
4777 /* NB: For AMD-specific insns with implicit memory operands,
4778 they're intentionally not covered. */
4781 /* No memory operand. */
4782 if (!i
.mem_operands
)
4787 if (i
.tm
.mnem_off
== MN_vldmxcsr
)
4790 else if (i
.tm
.opcode_space
== SPACE_BASE
)
4792 /* test, not, neg, mul, imul, div, idiv. */
4793 if (base_opcode
== 0xf7 && i
.tm
.extension_opcode
!= 1)
4797 if (base_opcode
== 0xff && i
.tm
.extension_opcode
<= 1)
4800 /* add, or, adc, sbb, and, sub, xor, cmp. */
4801 if (i
.tm
.base_opcode
>= 0x80 && i
.tm
.base_opcode
<= 0x83)
4804 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
4805 if ((base_opcode
== 0xc1 || (base_opcode
| 2) == 0xd3)
4806 && i
.tm
.extension_opcode
!= 6)
4809 /* Check for x87 instructions. */
4810 if ((base_opcode
| 6) == 0xdf)
4812 /* Skip fst, fstp, fstenv, fstcw. */
4813 if (i
.tm
.base_opcode
== 0xd9
4814 && (i
.tm
.extension_opcode
== 2
4815 || i
.tm
.extension_opcode
== 3
4816 || i
.tm
.extension_opcode
== 6
4817 || i
.tm
.extension_opcode
== 7))
4820 /* Skip fisttp, fist, fistp, fstp. */
4821 if (i
.tm
.base_opcode
== 0xdb
4822 && (i
.tm
.extension_opcode
== 1
4823 || i
.tm
.extension_opcode
== 2
4824 || i
.tm
.extension_opcode
== 3
4825 || i
.tm
.extension_opcode
== 7))
4828 /* Skip fisttp, fst, fstp, fsave, fstsw. */
4829 if (i
.tm
.base_opcode
== 0xdd
4830 && (i
.tm
.extension_opcode
== 1
4831 || i
.tm
.extension_opcode
== 2
4832 || i
.tm
.extension_opcode
== 3
4833 || i
.tm
.extension_opcode
== 6
4834 || i
.tm
.extension_opcode
== 7))
4837 /* Skip fisttp, fist, fistp, fbstp, fistp. */
4838 if (i
.tm
.base_opcode
== 0xdf
4839 && (i
.tm
.extension_opcode
== 1
4840 || i
.tm
.extension_opcode
== 2
4841 || i
.tm
.extension_opcode
== 3
4842 || i
.tm
.extension_opcode
== 6
4843 || i
.tm
.extension_opcode
== 7))
4849 else if (i
.tm
.opcode_space
== SPACE_0F
)
4851 /* bt, bts, btr, btc. */
4852 if (i
.tm
.base_opcode
== 0xba
4853 && (i
.tm
.extension_opcode
| 3) == 7)
4856 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
4857 if (i
.tm
.base_opcode
== 0xc7
4858 && i
.tm
.opcode_modifier
.opcodeprefix
== PREFIX_NONE
4859 && (i
.tm
.extension_opcode
== 1 || i
.tm
.extension_opcode
== 3
4860 || i
.tm
.extension_opcode
== 6))
4863 /* fxrstor, ldmxcsr, xrstor. */
4864 if (i
.tm
.base_opcode
== 0xae
4865 && (i
.tm
.extension_opcode
== 1
4866 || i
.tm
.extension_opcode
== 2
4867 || i
.tm
.extension_opcode
== 5))
4870 /* lgdt, lidt, lmsw. */
4871 if (i
.tm
.base_opcode
== 0x01
4872 && (i
.tm
.extension_opcode
== 2
4873 || i
.tm
.extension_opcode
== 3
4874 || i
.tm
.extension_opcode
== 6))
4878 dest
= i
.operands
- 1;
4880 /* Check fake imm8 operand and 3 source operands. */
4881 if ((i
.tm
.opcode_modifier
.immext
4882 || i
.reg_operands
+ i
.mem_operands
== 4)
4883 && i
.types
[dest
].bitfield
.imm8
)
4886 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
4887 if (i
.tm
.opcode_space
== SPACE_BASE
4888 && ((base_opcode
| 0x38) == 0x39
4889 || (base_opcode
| 2) == 0x87))
4892 if (i
.tm
.mnem_off
== MN_xadd
)
4895 /* Check for load instruction. */
4896 return (i
.types
[dest
].bitfield
.class != ClassNone
4897 || i
.types
[dest
].bitfield
.instance
== Accum
);
4900 /* Output lfence, 0xfaee8, after instruction. */
4903 insert_lfence_after (void)
4905 if (lfence_after_load
&& load_insn_p ())
4907 /* There are also two REP string instructions that require
4908 special treatment. Specifically, the compare string (CMPS)
4909 and scan string (SCAS) instructions set EFLAGS in a manner
4910 that depends on the data being compared/scanned. When used
4911 with a REP prefix, the number of iterations may therefore
4912 vary depending on this data. If the data is a program secret
4913 chosen by the adversary using an LVI method,
4914 then this data-dependent behavior may leak some aspect
4916 if (((i
.tm
.base_opcode
| 0x9) == 0xaf)
4917 && i
.prefix
[REP_PREFIX
])
4919 as_warn (_("`%s` changes flags which would affect control flow behavior"),
4922 char *p
= frag_more (3);
4929 /* Output lfence, 0xfaee8, before instruction. */
4932 insert_lfence_before (void)
4936 if (i
.tm
.opcode_space
!= SPACE_BASE
)
4939 if (i
.tm
.base_opcode
== 0xff
4940 && (i
.tm
.extension_opcode
== 2 || i
.tm
.extension_opcode
== 4))
4942 /* Insert lfence before indirect branch if needed. */
4944 if (lfence_before_indirect_branch
== lfence_branch_none
)
4947 if (i
.operands
!= 1)
4950 if (i
.reg_operands
== 1)
4952 /* Indirect branch via register. Don't insert lfence with
4953 -mlfence-after-load=yes. */
4954 if (lfence_after_load
4955 || lfence_before_indirect_branch
== lfence_branch_memory
)
4958 else if (i
.mem_operands
== 1
4959 && lfence_before_indirect_branch
!= lfence_branch_register
)
4961 as_warn (_("indirect `%s` with memory operand should be avoided"),
4968 if (last_insn
.kind
!= last_insn_other
4969 && last_insn
.seg
== now_seg
)
4971 as_warn_where (last_insn
.file
, last_insn
.line
,
4972 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
4973 last_insn
.name
, insn_name (&i
.tm
));
4984 /* Output or/not/shl and lfence before near ret. */
4985 if (lfence_before_ret
!= lfence_before_ret_none
4986 && (i
.tm
.base_opcode
| 1) == 0xc3)
4988 if (last_insn
.kind
!= last_insn_other
4989 && last_insn
.seg
== now_seg
)
4991 as_warn_where (last_insn
.file
, last_insn
.line
,
4992 _("`%s` skips -mlfence-before-ret on `%s`"),
4993 last_insn
.name
, insn_name (&i
.tm
));
4997 /* Near ret ingore operand size override under CPU64. */
4998 char prefix
= flag_code
== CODE_64BIT
5000 : i
.prefix
[DATA_PREFIX
] ? 0x66 : 0x0;
5002 if (lfence_before_ret
== lfence_before_ret_not
)
5004 /* not: 0xf71424, may add prefix
5005 for operand size override or 64-bit code. */
5006 p
= frag_more ((prefix
? 2 : 0) + 6 + 3);
5020 p
= frag_more ((prefix
? 1 : 0) + 4 + 3);
5023 if (lfence_before_ret
== lfence_before_ret_or
)
5025 /* or: 0x830c2400, may add prefix
5026 for operand size override or 64-bit code. */
5032 /* shl: 0xc1242400, may add prefix
5033 for operand size override or 64-bit code. */
5048 /* Shared helper for md_assemble() and s_insn(). */
5049 static void init_globals (void)
5053 memset (&i
, '\0', sizeof (i
));
5054 i
.rounding
.type
= rc_none
;
5055 for (j
= 0; j
< MAX_OPERANDS
; j
++)
5056 i
.reloc
[j
] = NO_RELOC
;
5057 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
5058 memset (im_expressions
, '\0', sizeof (im_expressions
));
5059 save_stack_p
= save_stack
;
5062 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5063 parsing pass. Instead of introducing a rarely use new insn attribute this
5064 utilizes a common pattern between affected templates. It is deemed
5065 acceptable that this will lead to unnecessary pass 2 preparations in a
5066 limited set of cases. */
5067 static INLINE
bool may_need_pass2 (const insn_template
*t
)
5069 return t
->opcode_modifier
.sse2avx
5070 /* Note that all SSE2AVX templates have at least one operand. */
5071 ? t
->operand_types
[t
->operands
- 1].bitfield
.class == RegSIMD
5072 : (t
->opcode_space
== SPACE_0F
5073 && (t
->base_opcode
| 1) == 0xbf)
5074 || (t
->opcode_space
== SPACE_BASE
5075 && t
->base_opcode
== 0x63);
5078 /* This is the guts of the machine-dependent assembler. LINE points to a
5079 machine dependent instruction. This function is supposed to emit
5080 the frags/bytes it assembles to. */
5083 md_assemble (char *line
)
5086 char mnemonic
[MAX_MNEM_SIZE
], mnem_suffix
= 0, *copy
= NULL
;
5087 const char *end
, *pass1_mnem
= NULL
;
5088 enum i386_error pass1_err
= 0;
5089 const insn_template
*t
;
5091 /* Initialize globals. */
5092 current_templates
= NULL
;
5096 /* First parse an instruction mnemonic & call i386_operand for the operands.
5097 We assume that the scrubber has arranged it so that line[0] is the valid
5098 start of a (possibly prefixed) mnemonic. */
5100 end
= parse_insn (line
, mnemonic
, false);
5103 if (pass1_mnem
!= NULL
)
5105 if (i
.error
!= no_error
)
5107 gas_assert (current_templates
!= NULL
);
5108 if (may_need_pass2 (current_templates
->start
) && !i
.suffix
)
5110 /* No point in trying a 2nd pass - it'll only find the same suffix
5112 mnem_suffix
= i
.suffix
;
5117 t
= current_templates
->start
;
5118 if (may_need_pass2 (t
))
5120 /* Make a copy of the full line in case we need to retry. */
5121 copy
= xstrdup (line
);
5124 mnem_suffix
= i
.suffix
;
5126 line
= parse_operands (line
, mnemonic
);
5134 /* Now we've parsed the mnemonic into a set of templates, and have the
5135 operands at hand. */
5137 /* All Intel opcodes have reversed operands except for "bound", "enter",
5138 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
5139 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
5140 intersegment "jmp" and "call" instructions with 2 immediate operands so
5141 that the immediate segment precedes the offset consistently in Intel and
5145 && (t
->mnem_off
!= MN_bound
)
5146 && !startswith (mnemonic
, "invlpg")
5147 && !startswith (mnemonic
, "monitor")
5148 && !startswith (mnemonic
, "mwait")
5149 && (t
->mnem_off
!= MN_pvalidate
)
5150 && !startswith (mnemonic
, "rmp")
5151 && (t
->mnem_off
!= MN_tpause
)
5152 && (t
->mnem_off
!= MN_umwait
)
5153 && !(i
.operands
== 2
5154 && operand_type_check (i
.types
[0], imm
)
5155 && operand_type_check (i
.types
[1], imm
)))
5158 /* The order of the immediates should be reversed
5159 for 2 immediates extrq and insertq instructions */
5160 if (i
.imm_operands
== 2
5161 && (t
->mnem_off
== MN_extrq
|| t
->mnem_off
== MN_insertq
))
5162 swap_2_operands (0, 1);
5167 if (i
.disp_operands
&& !optimize_disp (t
))
5170 /* Next, we find a template that matches the given insn,
5171 making sure the overlap of the given operands types is consistent
5172 with the template operand types. */
5174 if (!(t
= match_template (mnem_suffix
)))
5176 const char *err_msg
;
5178 if (copy
&& !mnem_suffix
)
5183 pass1_err
= i
.error
;
5184 pass1_mnem
= insn_name (current_templates
->start
);
5188 /* If a non-/only-64bit template (group) was found in pass 1, and if
5189 _some_ template (group) was found in pass 2, squash pass 1's
5191 if (pass1_err
== unsupported_64bit
)
5197 switch (pass1_mnem
? pass1_err
: i
.error
)
5201 case operand_size_mismatch
:
5202 err_msg
= _("operand size mismatch");
5204 case operand_type_mismatch
:
5205 err_msg
= _("operand type mismatch");
5207 case register_type_mismatch
:
5208 err_msg
= _("register type mismatch");
5210 case number_of_operands_mismatch
:
5211 err_msg
= _("number of operands mismatch");
5213 case invalid_instruction_suffix
:
5214 err_msg
= _("invalid instruction suffix");
5217 err_msg
= _("constant doesn't fit in 4 bits");
5219 case unsupported_with_intel_mnemonic
:
5220 err_msg
= _("unsupported with Intel mnemonic");
5222 case unsupported_syntax
:
5223 err_msg
= _("unsupported syntax");
5226 as_bad (_("unsupported instruction `%s'"),
5227 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5229 case unsupported_on_arch
:
5230 as_bad (_("`%s' is not supported on `%s%s'"),
5231 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5232 cpu_arch_name
? cpu_arch_name
: default_arch
,
5233 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
5235 case unsupported_64bit
:
5236 if (ISLOWER (mnem_suffix
))
5238 if (flag_code
== CODE_64BIT
)
5239 as_bad (_("`%s%c' is not supported in 64-bit mode"),
5240 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5243 as_bad (_("`%s%c' is only supported in 64-bit mode"),
5244 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
),
5249 if (flag_code
== CODE_64BIT
)
5250 as_bad (_("`%s' is not supported in 64-bit mode"),
5251 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5253 as_bad (_("`%s' is only supported in 64-bit mode"),
5254 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5257 case invalid_sib_address
:
5258 err_msg
= _("invalid SIB address");
5260 case invalid_vsib_address
:
5261 err_msg
= _("invalid VSIB address");
5263 case invalid_vector_register_set
:
5264 err_msg
= _("mask, index, and destination registers must be distinct");
5266 case invalid_tmm_register_set
:
5267 err_msg
= _("all tmm registers must be distinct");
5269 case invalid_dest_and_src_register_set
:
5270 err_msg
= _("destination and source registers must be distinct");
5272 case unsupported_vector_index_register
:
5273 err_msg
= _("unsupported vector index register");
5275 case unsupported_broadcast
:
5276 err_msg
= _("unsupported broadcast");
5278 case broadcast_needed
:
5279 err_msg
= _("broadcast is needed for operand of such type");
5281 case unsupported_masking
:
5282 err_msg
= _("unsupported masking");
5284 case mask_not_on_destination
:
5285 err_msg
= _("mask not on destination operand");
5287 case no_default_mask
:
5288 err_msg
= _("default mask isn't allowed");
5290 case unsupported_rc_sae
:
5291 err_msg
= _("unsupported static rounding/sae");
5293 case invalid_register_operand
:
5294 err_msg
= _("invalid register operand");
5297 as_bad (_("%s for `%s'"), err_msg
,
5298 pass1_mnem
? pass1_mnem
: insn_name (current_templates
->start
));
5304 if (sse_check
!= check_none
5305 /* The opcode space check isn't strictly needed; it's there only to
5306 bypass the logic below when easily possible. */
5307 && t
->opcode_space
>= SPACE_0F
5308 && t
->opcode_space
<= SPACE_0F3A
5309 && !is_cpu (&i
.tm
, CpuSSE4a
)
5310 && !is_any_vex_encoding (t
))
5314 for (j
= 0; j
< t
->operands
; ++j
)
5316 if (t
->operand_types
[j
].bitfield
.class == RegMMX
)
5318 if (t
->operand_types
[j
].bitfield
.class == RegSIMD
)
5322 if (j
>= t
->operands
&& simd
)
5323 (sse_check
== check_warning
5325 : as_bad
) (_("SSE instruction `%s' is used"), insn_name (&i
.tm
));
5328 if (i
.tm
.opcode_modifier
.fwait
)
5329 if (!add_prefix (FWAIT_OPCODE
))
5332 /* Check if REP prefix is OK. */
5333 if (i
.rep_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixRep
)
5335 as_bad (_("invalid instruction `%s' after `%s'"),
5336 insn_name (&i
.tm
), i
.rep_prefix
);
5340 /* Check for lock without a lockable instruction. Destination operand
5341 must be memory unless it is xchg (0x86). */
5342 if (i
.prefix
[LOCK_PREFIX
])
5344 if (i
.tm
.opcode_modifier
.prefixok
< PrefixLock
5345 || i
.mem_operands
== 0
5346 || (i
.tm
.base_opcode
!= 0x86
5347 && !(i
.flags
[i
.operands
- 1] & Operand_Mem
)))
5349 as_bad (_("expecting lockable instruction after `lock'"));
5353 /* Zap the redundant prefix from XCHG when optimizing. */
5354 if (i
.tm
.base_opcode
== 0x86 && optimize
&& !i
.no_optimize
)
5355 i
.prefix
[LOCK_PREFIX
] = 0;
5358 if (is_any_vex_encoding (&i
.tm
)
5359 || i
.tm
.operand_types
[i
.imm_operands
].bitfield
.class >= RegMMX
5360 || i
.tm
.operand_types
[i
.imm_operands
+ 1].bitfield
.class >= RegMMX
)
5362 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
5363 if (i
.prefix
[DATA_PREFIX
])
5365 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i
.tm
));
5369 /* Don't allow e.g. KMOV in TLS code sequences. */
5370 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
5373 case BFD_RELOC_386_TLS_GOTIE
:
5374 case BFD_RELOC_386_TLS_LE_32
:
5375 case BFD_RELOC_X86_64_GOTTPOFF
:
5376 case BFD_RELOC_X86_64_TLSLD
:
5377 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i
.tm
));
5384 /* Check if HLE prefix is OK. */
5385 if (i
.hle_prefix
&& !check_hle ())
5388 /* Check BND prefix. */
5389 if (i
.bnd_prefix
&& !i
.tm
.opcode_modifier
.bndprefixok
)
5390 as_bad (_("expecting valid branch instruction after `bnd'"));
5392 /* Check NOTRACK prefix. */
5393 if (i
.notrack_prefix
&& i
.tm
.opcode_modifier
.prefixok
!= PrefixNoTrack
)
5394 as_bad (_("expecting indirect branch instruction after `notrack'"));
5396 if (is_cpu (&i
.tm
, CpuMPX
))
5398 if (flag_code
== CODE_64BIT
&& i
.prefix
[ADDR_PREFIX
])
5399 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
5400 else if (flag_code
!= CODE_16BIT
5401 ? i
.prefix
[ADDR_PREFIX
]
5402 : i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
5403 as_bad (_("16-bit address isn't allowed in MPX instructions"));
5406 /* Insert BND prefix. */
5407 if (add_bnd_prefix
&& i
.tm
.opcode_modifier
.bndprefixok
)
5409 if (!i
.prefix
[BND_PREFIX
])
5410 add_prefix (BND_PREFIX_OPCODE
);
5411 else if (i
.prefix
[BND_PREFIX
] != BND_PREFIX_OPCODE
)
5413 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
5414 i
.prefix
[BND_PREFIX
] = BND_PREFIX_OPCODE
;
5418 /* Check string instruction segment overrides. */
5419 if (i
.tm
.opcode_modifier
.isstring
>= IS_STRING_ES_OP0
)
5421 gas_assert (i
.mem_operands
);
5422 if (!check_string ())
5424 i
.disp_operands
= 0;
5427 /* The memory operand of (%dx) should be only used with input/output
5428 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
5429 if (i
.input_output_operand
5430 && ((i
.tm
.base_opcode
| 0x82) != 0xee
5431 || i
.tm
.opcode_space
!= SPACE_BASE
))
5433 as_bad (_("input/output port address isn't allowed with `%s'"),
5438 if (optimize
&& !i
.no_optimize
&& i
.tm
.opcode_modifier
.optimize
)
5439 optimize_encoding ();
5441 if (use_unaligned_vector_move
)
5442 encode_with_unaligned_vector_move ();
5444 if (!process_suffix ())
5447 /* Check if IP-relative addressing requirements can be satisfied. */
5448 if (is_cpu (&i
.tm
, CpuPREFETCHI
)
5449 && !(i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
))
5450 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i
.tm
));
5452 /* Update operand types and check extended states. */
5453 for (j
= 0; j
< i
.operands
; j
++)
5455 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
5456 switch (i
.tm
.operand_types
[j
].bitfield
.class)
5461 i
.xstate
|= xstate_mmx
;
5464 i
.xstate
|= xstate_mask
;
5467 if (i
.tm
.operand_types
[j
].bitfield
.tmmword
)
5468 i
.xstate
|= xstate_tmm
;
5469 else if (i
.tm
.operand_types
[j
].bitfield
.zmmword
5470 && vector_size
>= VSZ512
)
5471 i
.xstate
|= xstate_zmm
;
5472 else if (i
.tm
.operand_types
[j
].bitfield
.ymmword
5473 && vector_size
>= VSZ256
)
5474 i
.xstate
|= xstate_ymm
;
5475 else if (i
.tm
.operand_types
[j
].bitfield
.xmmword
)
5476 i
.xstate
|= xstate_xmm
;
5481 /* Make still unresolved immediate matches conform to size of immediate
5482 given in i.suffix. */
5483 if (!finalize_imm ())
5486 if (i
.types
[0].bitfield
.imm1
)
5487 i
.imm_operands
= 0; /* kludge for shift insns. */
5489 /* For insns with operands there are more diddles to do to the opcode. */
5492 if (!process_operands ())
5495 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
5497 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
5498 as_warn (_("translating to `%sp'"), insn_name (&i
.tm
));
5501 if (is_any_vex_encoding (&i
.tm
))
5503 if (!cpu_arch_flags
.bitfield
.cpui286
)
5505 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
5510 /* Check for explicit REX prefix. */
5511 if (i
.prefix
[REX_PREFIX
] || i
.rex_encoding
)
5513 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i
.tm
));
5517 if (i
.tm
.opcode_modifier
.vex
)
5518 build_vex_prefix (t
);
5520 build_evex_prefix ();
5522 /* The individual REX.RXBW bits got consumed. */
5523 i
.rex
&= REX_OPCODE
;
5526 /* Handle conversion of 'int $3' --> special int3 insn. */
5527 if (i
.tm
.mnem_off
== MN_int
5528 && i
.op
[0].imms
->X_add_number
== 3)
5530 i
.tm
.base_opcode
= INT3_OPCODE
;
5534 if ((i
.tm
.opcode_modifier
.jump
== JUMP
5535 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
5536 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
5537 && i
.op
[0].disps
->X_op
== O_constant
)
5539 /* Convert "jmp constant" (and "call constant") to a jump (call) to
5540 the absolute address given by the constant. Since ix86 jumps and
5541 calls are pc relative, we need to generate a reloc. */
5542 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
5543 i
.op
[0].disps
->X_op
= O_symbol
;
5546 /* For 8 bit registers we need an empty rex prefix. Also if the
5547 instruction already has a prefix, we need to convert old
5548 registers to new ones. */
5550 if ((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
5551 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
5552 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
5553 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
5554 || (((i
.types
[0].bitfield
.class == Reg
&& i
.types
[0].bitfield
.byte
)
5555 || (i
.types
[1].bitfield
.class == Reg
&& i
.types
[1].bitfield
.byte
))
5560 i
.rex
|= REX_OPCODE
;
5561 for (x
= 0; x
< 2; x
++)
5563 /* Look for 8 bit operand that uses old registers. */
5564 if (i
.types
[x
].bitfield
.class == Reg
&& i
.types
[x
].bitfield
.byte
5565 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
5567 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5568 /* In case it is "hi" register, give up. */
5569 if (i
.op
[x
].regs
->reg_num
> 3)
5570 as_bad (_("can't encode register '%s%s' in an "
5571 "instruction requiring REX prefix."),
5572 register_prefix
, i
.op
[x
].regs
->reg_name
);
5574 /* Otherwise it is equivalent to the extended register.
5575 Since the encoding doesn't change this is merely
5576 cosmetic cleanup for debug output. */
5578 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
5583 if (i
.rex
== 0 && i
.rex_encoding
)
5585 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
5586 that uses legacy register. If it is "hi" register, don't add
5587 the REX_OPCODE byte. */
5589 for (x
= 0; x
< 2; x
++)
5590 if (i
.types
[x
].bitfield
.class == Reg
5591 && i
.types
[x
].bitfield
.byte
5592 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0
5593 && i
.op
[x
].regs
->reg_num
> 3)
5595 gas_assert (!(i
.op
[x
].regs
->reg_flags
& RegRex
));
5596 i
.rex_encoding
= false;
5605 add_prefix (REX_OPCODE
| i
.rex
);
5607 insert_lfence_before ();
5609 /* We are ready to output the insn. */
5612 insert_lfence_after ();
5614 last_insn
.seg
= now_seg
;
5616 if (i
.tm
.opcode_modifier
.isprefix
)
5618 last_insn
.kind
= last_insn_prefix
;
5619 last_insn
.name
= insn_name (&i
.tm
);
5620 last_insn
.file
= as_where (&last_insn
.line
);
5623 last_insn
.kind
= last_insn_other
;
5626 /* The Q suffix is generally valid only in 64-bit mode, with very few
5627 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
5628 and fisttp only one of their two templates is matched below: That's
5629 sufficient since other relevant attributes are the same between both
5630 respective templates. */
5631 static INLINE
bool q_suffix_allowed(const insn_template
*t
)
5633 return flag_code
== CODE_64BIT
5634 || (t
->opcode_space
== SPACE_BASE
5635 && t
->base_opcode
== 0xdf
5636 && (t
->extension_opcode
& 1)) /* fild / fistp / fisttp */
5637 || t
->mnem_off
== MN_cmpxchg8b
;
5641 parse_insn (const char *line
, char *mnemonic
, bool prefix_only
)
5643 const char *l
= line
, *token_start
= l
;
5645 bool pass1
= !current_templates
;
5647 const insn_template
*t
;
5653 /* Pseudo-prefixes start with an opening figure brace. */
5654 if ((*mnem_p
= *l
) == '{')
5659 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
5664 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5667 as_bad (_("no such instruction: `%s'"), token_start
);
5672 /* Pseudo-prefixes end with a closing figure brace. */
5673 if (*mnemonic
== '{' && *l
== '}')
5676 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
5680 /* Point l at the closing brace if there's no other separator. */
5681 if (*l
!= END_OF_INSN
&& !is_space_char (*l
)
5682 && *l
!= PREFIX_SEPARATOR
)
5685 else if (!is_space_char (*l
)
5686 && *l
!= END_OF_INSN
5688 || (*l
!= PREFIX_SEPARATOR
&& *l
!= ',')))
5692 as_bad (_("invalid character %s in mnemonic"),
5693 output_invalid (*l
));
5696 if (token_start
== l
)
5698 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
5699 as_bad (_("expecting prefix; got nothing"));
5701 as_bad (_("expecting mnemonic; got nothing"));
5705 /* Look up instruction (or prefix) via hash table. */
5706 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5708 if (*l
!= END_OF_INSN
5709 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
5710 && current_templates
5711 && current_templates
->start
->opcode_modifier
.isprefix
)
5713 if (!cpu_flags_check_cpu64 (current_templates
->start
))
5715 as_bad ((flag_code
!= CODE_64BIT
5716 ? _("`%s' is only supported in 64-bit mode")
5717 : _("`%s' is not supported in 64-bit mode")),
5718 insn_name (current_templates
->start
));
5721 /* If we are in 16-bit mode, do not allow addr16 or data16.
5722 Similarly, in 32-bit mode, do not allow addr32 or data32. */
5723 if ((current_templates
->start
->opcode_modifier
.size
== SIZE16
5724 || current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5725 && flag_code
!= CODE_64BIT
5726 && ((current_templates
->start
->opcode_modifier
.size
== SIZE32
)
5727 ^ (flag_code
== CODE_16BIT
)))
5729 as_bad (_("redundant %s prefix"),
5730 insn_name (current_templates
->start
));
5734 if (current_templates
->start
->base_opcode
== PSEUDO_PREFIX
)
5736 /* Handle pseudo prefixes. */
5737 switch (current_templates
->start
->extension_opcode
)
5741 i
.disp_encoding
= disp_encoding_8bit
;
5745 i
.disp_encoding
= disp_encoding_16bit
;
5749 i
.disp_encoding
= disp_encoding_32bit
;
5753 i
.dir_encoding
= dir_encoding_load
;
5757 i
.dir_encoding
= dir_encoding_store
;
5761 i
.vec_encoding
= vex_encoding_vex
;
5765 i
.vec_encoding
= vex_encoding_vex3
;
5769 i
.vec_encoding
= vex_encoding_evex
;
5773 i
.rex_encoding
= true;
5775 case Prefix_NoOptimize
:
5777 i
.no_optimize
= true;
5785 /* Add prefix, checking for repeated prefixes. */
5786 switch (add_prefix (current_templates
->start
->base_opcode
))
5791 if (is_cpu (current_templates
->start
, CpuIBT
))
5792 i
.notrack_prefix
= insn_name (current_templates
->start
);
5795 if (is_cpu (current_templates
->start
, CpuHLE
))
5796 i
.hle_prefix
= insn_name (current_templates
->start
);
5797 else if (is_cpu (current_templates
->start
, CpuMPX
))
5798 i
.bnd_prefix
= insn_name (current_templates
->start
);
5800 i
.rep_prefix
= insn_name (current_templates
->start
);
5806 /* Skip past PREFIX_SEPARATOR and reset token_start. */
5816 if (!current_templates
)
5818 /* Deprecated functionality (new code should use pseudo-prefixes instead):
5819 Check if we should swap operand or force 32bit displacement in
5821 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
5822 i
.dir_encoding
= dir_encoding_swap
;
5823 else if (mnem_p
- 3 == dot_p
5826 i
.disp_encoding
= disp_encoding_8bit
;
5827 else if (mnem_p
- 4 == dot_p
5831 i
.disp_encoding
= disp_encoding_32bit
;
5836 current_templates
= (const templates
*) str_hash_find (op_hash
, mnemonic
);
5839 if (!current_templates
|| !pass1
)
5841 current_templates
= NULL
;
5844 if (mnem_p
> mnemonic
)
5846 /* See if we can get a match by trimming off a suffix. */
5849 case WORD_MNEM_SUFFIX
:
5850 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
5851 i
.suffix
= SHORT_MNEM_SUFFIX
;
5854 case BYTE_MNEM_SUFFIX
:
5855 case QWORD_MNEM_SUFFIX
:
5856 i
.suffix
= mnem_p
[-1];
5859 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5861 case SHORT_MNEM_SUFFIX
:
5862 case LONG_MNEM_SUFFIX
:
5865 i
.suffix
= mnem_p
[-1];
5868 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5876 if (intel_float_operand (mnemonic
) == 1)
5877 i
.suffix
= SHORT_MNEM_SUFFIX
;
5879 i
.suffix
= LONG_MNEM_SUFFIX
;
5882 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5884 /* For compatibility reasons accept MOVSD and CMPSD without
5885 operands even in AT&T mode. */
5886 else if (*l
== END_OF_INSN
5887 || (is_space_char (*l
) && l
[1] == END_OF_INSN
))
5891 = (const templates
*) str_hash_find (op_hash
, mnemonic
);
5892 if (current_templates
!= NULL
5894 && (current_templates
->start
->base_opcode
| 2) == 0xa6
5895 && current_templates
->start
->opcode_space
5897 && mnem_p
[-2] == 's')
5899 as_warn (_("found `%sd'; assuming `%sl' was meant"),
5900 mnemonic
, mnemonic
);
5901 i
.suffix
= LONG_MNEM_SUFFIX
;
5905 current_templates
= NULL
;
5913 if (!current_templates
)
5916 as_bad (_("no such instruction: `%s'"), token_start
);
5921 if (current_templates
->start
->opcode_modifier
.jump
== JUMP
5922 || current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
5924 /* Check for a branch hint. We allow ",pt" and ",pn" for
5925 predict taken and predict not taken respectively.
5926 I'm not sure that branch hints actually do anything on loop
5927 and jcxz insns (JumpByte) for current Pentium4 chips. They
5928 may work in the future and it doesn't hurt to accept them
5930 if (l
[0] == ',' && l
[1] == 'p')
5934 if (!add_prefix (DS_PREFIX_OPCODE
))
5938 else if (l
[2] == 'n')
5940 if (!add_prefix (CS_PREFIX_OPCODE
))
5946 /* Any other comma loses. */
5949 as_bad (_("invalid character %s in mnemonic"),
5950 output_invalid (*l
));
5954 /* Check if instruction is supported on specified architecture. */
5956 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
5958 supported
|= cpu_flags_match (t
);
5960 if (i
.suffix
== QWORD_MNEM_SUFFIX
&& !q_suffix_allowed (t
))
5961 supported
&= ~CPU_FLAGS_64BIT_MATCH
;
5963 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
5969 if (supported
& CPU_FLAGS_64BIT_MATCH
)
5970 i
.error
= unsupported_on_arch
;
5972 i
.error
= unsupported_64bit
;
5979 parse_operands (char *l
, const char *mnemonic
)
5983 /* 1 if operand is pending after ','. */
5984 unsigned int expecting_operand
= 0;
5986 while (*l
!= END_OF_INSN
)
5988 /* Non-zero if operand parens not balanced. */
5989 unsigned int paren_not_balanced
= 0;
5990 /* True if inside double quotes. */
5991 bool in_quotes
= false;
5993 /* Skip optional white space before operand. */
5994 if (is_space_char (*l
))
5996 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
&& *l
!= '"')
5998 as_bad (_("invalid character %s before operand %d"),
5999 output_invalid (*l
),
6003 token_start
= l
; /* After white space. */
6004 while (in_quotes
|| paren_not_balanced
|| *l
!= ',')
6006 if (*l
== END_OF_INSN
)
6010 as_bad (_("unbalanced double quotes in operand %d."),
6014 if (paren_not_balanced
)
6016 know (!intel_syntax
);
6017 as_bad (_("unbalanced parenthesis in operand %d."),
6022 break; /* we are done */
6024 else if (*l
== '\\' && l
[1] == '"')
6027 in_quotes
= !in_quotes
;
6028 else if (!in_quotes
&& !is_operand_char (*l
) && !is_space_char (*l
))
6030 as_bad (_("invalid character %s in operand %d"),
6031 output_invalid (*l
),
6035 if (!intel_syntax
&& !in_quotes
)
6038 ++paren_not_balanced
;
6040 --paren_not_balanced
;
6044 if (l
!= token_start
)
6045 { /* Yes, we've read in another operand. */
6046 unsigned int operand_ok
;
6047 this_operand
= i
.operands
++;
6048 if (i
.operands
> MAX_OPERANDS
)
6050 as_bad (_("spurious operands; (%d operands/instruction max)"),
6054 i
.types
[this_operand
].bitfield
.unspecified
= 1;
6055 /* Now parse operand adding info to 'i' as we go along. */
6056 END_STRING_AND_SAVE (l
);
6058 if (i
.mem_operands
> 1)
6060 as_bad (_("too many memory references for `%s'"),
6067 i386_intel_operand (token_start
,
6068 intel_float_operand (mnemonic
));
6070 operand_ok
= i386_att_operand (token_start
);
6072 RESTORE_END_STRING (l
);
6078 if (expecting_operand
)
6080 expecting_operand_after_comma
:
6081 as_bad (_("expecting operand after ','; got nothing"));
6086 as_bad (_("expecting operand before ','; got nothing"));
6091 /* Now *l must be either ',' or END_OF_INSN. */
6094 if (*++l
== END_OF_INSN
)
6096 /* Just skip it, if it's \n complain. */
6097 goto expecting_operand_after_comma
;
6099 expecting_operand
= 1;
6106 swap_2_operands (unsigned int xchg1
, unsigned int xchg2
)
6108 union i386_op temp_op
;
6109 i386_operand_type temp_type
;
6110 unsigned int temp_flags
;
6111 enum bfd_reloc_code_real temp_reloc
;
6113 temp_type
= i
.types
[xchg2
];
6114 i
.types
[xchg2
] = i
.types
[xchg1
];
6115 i
.types
[xchg1
] = temp_type
;
6117 temp_flags
= i
.flags
[xchg2
];
6118 i
.flags
[xchg2
] = i
.flags
[xchg1
];
6119 i
.flags
[xchg1
] = temp_flags
;
6121 temp_op
= i
.op
[xchg2
];
6122 i
.op
[xchg2
] = i
.op
[xchg1
];
6123 i
.op
[xchg1
] = temp_op
;
6125 temp_reloc
= i
.reloc
[xchg2
];
6126 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
6127 i
.reloc
[xchg1
] = temp_reloc
;
6129 temp_flags
= i
.imm_bits
[xchg2
];
6130 i
.imm_bits
[xchg2
] = i
.imm_bits
[xchg1
];
6131 i
.imm_bits
[xchg1
] = temp_flags
;
6135 if (i
.mask
.operand
== xchg1
)
6136 i
.mask
.operand
= xchg2
;
6137 else if (i
.mask
.operand
== xchg2
)
6138 i
.mask
.operand
= xchg1
;
6140 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6142 if (i
.broadcast
.operand
== xchg1
)
6143 i
.broadcast
.operand
= xchg2
;
6144 else if (i
.broadcast
.operand
== xchg2
)
6145 i
.broadcast
.operand
= xchg1
;
6150 swap_operands (void)
6156 swap_2_operands (1, i
.operands
- 2);
6160 swap_2_operands (0, i
.operands
- 1);
6166 if (i
.mem_operands
== 2)
6168 const reg_entry
*temp_seg
;
6169 temp_seg
= i
.seg
[0];
6170 i
.seg
[0] = i
.seg
[1];
6171 i
.seg
[1] = temp_seg
;
6175 /* Try to ensure constant immediates are represented in the smallest
6180 char guess_suffix
= 0;
6184 guess_suffix
= i
.suffix
;
6185 else if (i
.reg_operands
)
6187 /* Figure out a suffix from the last register operand specified.
6188 We can't do this properly yet, i.e. excluding special register
6189 instances, but the following works for instructions with
6190 immediates. In any case, we can't set i.suffix yet. */
6191 for (op
= i
.operands
; --op
>= 0;)
6192 if (i
.types
[op
].bitfield
.class != Reg
)
6194 else if (i
.types
[op
].bitfield
.byte
)
6196 guess_suffix
= BYTE_MNEM_SUFFIX
;
6199 else if (i
.types
[op
].bitfield
.word
)
6201 guess_suffix
= WORD_MNEM_SUFFIX
;
6204 else if (i
.types
[op
].bitfield
.dword
)
6206 guess_suffix
= LONG_MNEM_SUFFIX
;
6209 else if (i
.types
[op
].bitfield
.qword
)
6211 guess_suffix
= QWORD_MNEM_SUFFIX
;
6215 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
6216 guess_suffix
= WORD_MNEM_SUFFIX
;
6217 else if (flag_code
!= CODE_64BIT
6218 || (!(i
.prefix
[REX_PREFIX
] & REX_W
)
6219 /* A more generic (but also more involved) way of dealing
6220 with the special case(s) would be to go look for
6221 DefaultSize attributes on any of the templates. */
6222 && current_templates
->start
->mnem_off
!= MN_push
))
6223 guess_suffix
= LONG_MNEM_SUFFIX
;
6225 for (op
= i
.operands
; --op
>= 0;)
6226 if (operand_type_check (i
.types
[op
], imm
))
6228 switch (i
.op
[op
].imms
->X_op
)
6231 /* If a suffix is given, this operand may be shortened. */
6232 switch (guess_suffix
)
6234 case LONG_MNEM_SUFFIX
:
6235 i
.types
[op
].bitfield
.imm32
= 1;
6236 i
.types
[op
].bitfield
.imm64
= 1;
6238 case WORD_MNEM_SUFFIX
:
6239 i
.types
[op
].bitfield
.imm16
= 1;
6240 i
.types
[op
].bitfield
.imm32
= 1;
6241 i
.types
[op
].bitfield
.imm32s
= 1;
6242 i
.types
[op
].bitfield
.imm64
= 1;
6244 case BYTE_MNEM_SUFFIX
:
6245 i
.types
[op
].bitfield
.imm8
= 1;
6246 i
.types
[op
].bitfield
.imm8s
= 1;
6247 i
.types
[op
].bitfield
.imm16
= 1;
6248 i
.types
[op
].bitfield
.imm32
= 1;
6249 i
.types
[op
].bitfield
.imm32s
= 1;
6250 i
.types
[op
].bitfield
.imm64
= 1;
6254 /* If this operand is at most 16 bits, convert it
6255 to a signed 16 bit number before trying to see
6256 whether it will fit in an even smaller size.
6257 This allows a 16-bit operand such as $0xffe0 to
6258 be recognised as within Imm8S range. */
6259 if ((i
.types
[op
].bitfield
.imm16
)
6260 && fits_in_unsigned_word (i
.op
[op
].imms
->X_add_number
))
6262 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6263 ^ 0x8000) - 0x8000);
6266 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
6267 if ((i
.types
[op
].bitfield
.imm32
)
6268 && fits_in_unsigned_long (i
.op
[op
].imms
->X_add_number
))
6270 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
6271 ^ ((offsetT
) 1 << 31))
6272 - ((offsetT
) 1 << 31));
6276 = operand_type_or (i
.types
[op
],
6277 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
6279 /* We must avoid matching of Imm32 templates when 64bit
6280 only immediate is available. */
6281 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
6282 i
.types
[op
].bitfield
.imm32
= 0;
6289 /* Symbols and expressions. */
6291 /* Convert symbolic operand to proper sizes for matching, but don't
6292 prevent matching a set of insns that only supports sizes other
6293 than those matching the insn suffix. */
6295 i386_operand_type mask
, allowed
;
6296 const insn_template
*t
= current_templates
->start
;
6298 operand_type_set (&mask
, 0);
6299 switch (guess_suffix
)
6301 case QWORD_MNEM_SUFFIX
:
6302 mask
.bitfield
.imm64
= 1;
6303 mask
.bitfield
.imm32s
= 1;
6305 case LONG_MNEM_SUFFIX
:
6306 mask
.bitfield
.imm32
= 1;
6308 case WORD_MNEM_SUFFIX
:
6309 mask
.bitfield
.imm16
= 1;
6311 case BYTE_MNEM_SUFFIX
:
6312 mask
.bitfield
.imm8
= 1;
6318 allowed
= operand_type_and (t
->operand_types
[op
], mask
);
6319 while (++t
< current_templates
->end
)
6321 allowed
= operand_type_or (allowed
, t
->operand_types
[op
]);
6322 allowed
= operand_type_and (allowed
, mask
);
6325 if (!operand_type_all_zero (&allowed
))
6326 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
6333 /* Try to use the smallest displacement type too. */
6335 optimize_disp (const insn_template
*t
)
6339 if (!want_disp32 (t
)
6340 && (!t
->opcode_modifier
.jump
6341 || i
.jumpabsolute
|| i
.types
[0].bitfield
.baseindex
))
6343 for (op
= 0; op
< i
.operands
; ++op
)
6345 const expressionS
*exp
= i
.op
[op
].disps
;
6347 if (!operand_type_check (i
.types
[op
], disp
))
6350 if (exp
->X_op
!= O_constant
)
6353 /* Since displacement is signed extended to 64bit, don't allow
6354 disp32 if it is out of range. */
6355 if (fits_in_signed_long (exp
->X_add_number
))
6358 i
.types
[op
].bitfield
.disp32
= 0;
6359 if (i
.types
[op
].bitfield
.baseindex
)
6361 as_bad (_("0x%" PRIx64
" out of range of signed 32bit displacement"),
6362 (uint64_t) exp
->X_add_number
);
6368 /* Don't optimize displacement for movabs since it only takes 64bit
6370 if (i
.disp_encoding
> disp_encoding_8bit
6371 || (flag_code
== CODE_64BIT
&& t
->mnem_off
== MN_movabs
))
6374 for (op
= i
.operands
; op
-- > 0;)
6375 if (operand_type_check (i
.types
[op
], disp
))
6377 if (i
.op
[op
].disps
->X_op
== O_constant
)
6379 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
6381 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
6383 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6384 i
.op
[op
].disps
= NULL
;
6389 if (i
.types
[op
].bitfield
.disp16
6390 && fits_in_unsigned_word (op_disp
))
6392 /* If this operand is at most 16 bits, convert
6393 to a signed 16 bit number and don't use 64bit
6395 op_disp
= ((op_disp
^ 0x8000) - 0x8000);
6396 i
.types
[op
].bitfield
.disp64
= 0;
6400 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
6401 if ((flag_code
!= CODE_64BIT
6402 ? i
.types
[op
].bitfield
.disp32
6404 && (!t
->opcode_modifier
.jump
6405 || i
.jumpabsolute
|| i
.types
[op
].bitfield
.baseindex
))
6406 && fits_in_unsigned_long (op_disp
))
6408 /* If this operand is at most 32 bits, convert
6409 to a signed 32 bit number and don't use 64bit
6411 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
6412 i
.types
[op
].bitfield
.disp64
= 0;
6413 i
.types
[op
].bitfield
.disp32
= 1;
6416 if (flag_code
== CODE_64BIT
&& fits_in_signed_long (op_disp
))
6418 i
.types
[op
].bitfield
.disp64
= 0;
6419 i
.types
[op
].bitfield
.disp32
= 1;
6422 if ((i
.types
[op
].bitfield
.disp32
6423 || i
.types
[op
].bitfield
.disp16
)
6424 && fits_in_disp8 (op_disp
))
6425 i
.types
[op
].bitfield
.disp8
= 1;
6427 i
.op
[op
].disps
->X_add_number
= op_disp
;
6429 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
6430 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
6432 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
6433 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
6434 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
6437 /* We only support 64bit displacement on constants. */
6438 i
.types
[op
].bitfield
.disp64
= 0;
6444 /* Return 1 if there is a match in broadcast bytes between operand
6445 GIVEN and instruction template T. */
6448 match_broadcast_size (const insn_template
*t
, unsigned int given
)
6450 return ((t
->opcode_modifier
.broadcast
== BYTE_BROADCAST
6451 && i
.types
[given
].bitfield
.byte
)
6452 || (t
->opcode_modifier
.broadcast
== WORD_BROADCAST
6453 && i
.types
[given
].bitfield
.word
)
6454 || (t
->opcode_modifier
.broadcast
== DWORD_BROADCAST
6455 && i
.types
[given
].bitfield
.dword
)
6456 || (t
->opcode_modifier
.broadcast
== QWORD_BROADCAST
6457 && i
.types
[given
].bitfield
.qword
));
6460 /* Check if operands are valid for the instruction. */
6463 check_VecOperands (const insn_template
*t
)
6468 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
6469 any one operand are implicity requiring AVX512VL support if the actual
6470 operand size is YMMword or XMMword. Since this function runs after
6471 template matching, there's no need to check for YMMword/XMMword in
6473 cpu
= cpu_flags_and (cpu_flags_from_attr (t
->cpu
), avx512
);
6474 if (!cpu_flags_all_zero (&cpu
)
6475 && !is_cpu (t
, CpuAVX512VL
)
6476 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
6478 for (op
= 0; op
< t
->operands
; ++op
)
6480 if (t
->operand_types
[op
].bitfield
.zmmword
6481 && (i
.types
[op
].bitfield
.ymmword
6482 || i
.types
[op
].bitfield
.xmmword
))
6484 i
.error
= unsupported
;
6490 /* Somewhat similarly, templates specifying both AVX and AVX2 are
6491 requiring AVX2 support if the actual operand size is YMMword. */
6492 if (is_cpu (t
, CpuAVX
) && is_cpu (t
, CpuAVX2
)
6493 && !cpu_arch_flags
.bitfield
.cpuavx2
)
6495 for (op
= 0; op
< t
->operands
; ++op
)
6497 if (t
->operand_types
[op
].bitfield
.xmmword
6498 && i
.types
[op
].bitfield
.ymmword
)
6500 i
.error
= unsupported
;
6506 /* Without VSIB byte, we can't have a vector register for index. */
6507 if (!t
->opcode_modifier
.sib
6509 && (i
.index_reg
->reg_type
.bitfield
.xmmword
6510 || i
.index_reg
->reg_type
.bitfield
.ymmword
6511 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
6513 i
.error
= unsupported_vector_index_register
;
6517 /* Check if default mask is allowed. */
6518 if (t
->opcode_modifier
.operandconstraint
== NO_DEFAULT_MASK
6519 && (!i
.mask
.reg
|| i
.mask
.reg
->reg_num
== 0))
6521 i
.error
= no_default_mask
;
6525 /* For VSIB byte, we need a vector register for index, and all vector
6526 registers must be distinct. */
6527 if (t
->opcode_modifier
.sib
&& t
->opcode_modifier
.sib
!= SIBMEM
)
6530 || !((t
->opcode_modifier
.sib
== VECSIB128
6531 && i
.index_reg
->reg_type
.bitfield
.xmmword
)
6532 || (t
->opcode_modifier
.sib
== VECSIB256
6533 && i
.index_reg
->reg_type
.bitfield
.ymmword
)
6534 || (t
->opcode_modifier
.sib
== VECSIB512
6535 && i
.index_reg
->reg_type
.bitfield
.zmmword
)))
6537 i
.error
= invalid_vsib_address
;
6541 gas_assert (i
.reg_operands
== 2 || i
.mask
.reg
);
6542 if (i
.reg_operands
== 2 && !i
.mask
.reg
)
6544 gas_assert (i
.types
[0].bitfield
.class == RegSIMD
);
6545 gas_assert (i
.types
[0].bitfield
.xmmword
6546 || i
.types
[0].bitfield
.ymmword
);
6547 gas_assert (i
.types
[2].bitfield
.class == RegSIMD
);
6548 gas_assert (i
.types
[2].bitfield
.xmmword
6549 || i
.types
[2].bitfield
.ymmword
);
6550 if (operand_check
== check_none
)
6552 if (register_number (i
.op
[0].regs
)
6553 != register_number (i
.index_reg
)
6554 && register_number (i
.op
[2].regs
)
6555 != register_number (i
.index_reg
)
6556 && register_number (i
.op
[0].regs
)
6557 != register_number (i
.op
[2].regs
))
6559 if (operand_check
== check_error
)
6561 i
.error
= invalid_vector_register_set
;
6564 as_warn (_("mask, index, and destination registers should be distinct"));
6566 else if (i
.reg_operands
== 1 && i
.mask
.reg
)
6568 if (i
.types
[1].bitfield
.class == RegSIMD
6569 && (i
.types
[1].bitfield
.xmmword
6570 || i
.types
[1].bitfield
.ymmword
6571 || i
.types
[1].bitfield
.zmmword
)
6572 && (register_number (i
.op
[1].regs
)
6573 == register_number (i
.index_reg
)))
6575 if (operand_check
== check_error
)
6577 i
.error
= invalid_vector_register_set
;
6580 if (operand_check
!= check_none
)
6581 as_warn (_("index and destination registers should be distinct"));
6586 /* For AMX instructions with 3 TMM register operands, all operands
6587 must be distinct. */
6588 if (i
.reg_operands
== 3
6589 && t
->operand_types
[0].bitfield
.tmmword
6590 && (i
.op
[0].regs
== i
.op
[1].regs
6591 || i
.op
[0].regs
== i
.op
[2].regs
6592 || i
.op
[1].regs
== i
.op
[2].regs
))
6594 i
.error
= invalid_tmm_register_set
;
6598 /* For some special instructions require that destination must be distinct
6599 from source registers. */
6600 if (t
->opcode_modifier
.operandconstraint
== DISTINCT_DEST
)
6602 unsigned int dest_reg
= i
.operands
- 1;
6604 know (i
.operands
>= 3);
6606 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
6607 if (i
.op
[dest_reg
- 1].regs
== i
.op
[dest_reg
].regs
6608 || (i
.reg_operands
> 2
6609 && i
.op
[dest_reg
- 2].regs
== i
.op
[dest_reg
].regs
))
6611 i
.error
= invalid_dest_and_src_register_set
;
6616 /* Check if broadcast is supported by the instruction and is applied
6617 to the memory operand. */
6618 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6620 i386_operand_type type
, overlap
;
6622 /* Check if specified broadcast is supported in this instruction,
6623 and its broadcast bytes match the memory operand. */
6624 op
= i
.broadcast
.operand
;
6625 if (!t
->opcode_modifier
.broadcast
6626 || !(i
.flags
[op
] & Operand_Mem
)
6627 || (!i
.types
[op
].bitfield
.unspecified
6628 && !match_broadcast_size (t
, op
)))
6631 i
.error
= unsupported_broadcast
;
6635 operand_type_set (&type
, 0);
6636 switch (get_broadcast_bytes (t
, false))
6639 type
.bitfield
.word
= 1;
6642 type
.bitfield
.dword
= 1;
6645 type
.bitfield
.qword
= 1;
6648 type
.bitfield
.xmmword
= 1;
6651 if (vector_size
< VSZ256
)
6653 type
.bitfield
.ymmword
= 1;
6656 if (vector_size
< VSZ512
)
6658 type
.bitfield
.zmmword
= 1;
6664 overlap
= operand_type_and (type
, t
->operand_types
[op
]);
6665 if (t
->operand_types
[op
].bitfield
.class == RegSIMD
6666 && t
->operand_types
[op
].bitfield
.byte
6667 + t
->operand_types
[op
].bitfield
.word
6668 + t
->operand_types
[op
].bitfield
.dword
6669 + t
->operand_types
[op
].bitfield
.qword
> 1)
6671 overlap
.bitfield
.xmmword
= 0;
6672 overlap
.bitfield
.ymmword
= 0;
6673 overlap
.bitfield
.zmmword
= 0;
6675 if (operand_type_all_zero (&overlap
))
6678 if (t
->opcode_modifier
.checkoperandsize
)
6682 type
.bitfield
.baseindex
= 1;
6683 for (j
= 0; j
< i
.operands
; ++j
)
6686 && !operand_type_register_match(i
.types
[j
],
6687 t
->operand_types
[j
],
6689 t
->operand_types
[op
]))
6694 /* If broadcast is supported in this instruction, we need to check if
6695 operand of one-element size isn't specified without broadcast. */
6696 else if (t
->opcode_modifier
.broadcast
&& i
.mem_operands
)
6698 /* Find memory operand. */
6699 for (op
= 0; op
< i
.operands
; op
++)
6700 if (i
.flags
[op
] & Operand_Mem
)
6702 gas_assert (op
< i
.operands
);
6703 /* Check size of the memory operand. */
6704 if (match_broadcast_size (t
, op
))
6706 i
.error
= broadcast_needed
;
6711 op
= MAX_OPERANDS
- 1; /* Avoid uninitialized variable warning. */
6713 /* Check if requested masking is supported. */
6716 if (!t
->opcode_modifier
.masking
)
6718 i
.error
= unsupported_masking
;
6722 /* Common rules for masking:
6723 - mask register destinations permit only zeroing-masking, without
6724 that actually being expressed by a {z} operand suffix or EVEX.z,
6725 - memory destinations allow only merging-masking,
6726 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
6729 && (t
->operand_types
[t
->operands
- 1].bitfield
.class == RegMask
6730 || (i
.flags
[t
->operands
- 1] & Operand_Mem
)
6731 || t
->opcode_modifier
.sib
))
6733 i
.error
= unsupported_masking
;
6738 /* Check if masking is applied to dest operand. */
6739 if (i
.mask
.reg
&& (i
.mask
.operand
!= i
.operands
- 1))
6741 i
.error
= mask_not_on_destination
;
6746 if (i
.rounding
.type
!= rc_none
)
6748 if (!t
->opcode_modifier
.sae
6749 || ((i
.rounding
.type
!= saeonly
) != t
->opcode_modifier
.staticrounding
)
6752 i
.error
= unsupported_rc_sae
;
6756 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
6758 if (t
->opcode_modifier
.evex
!= EVEXLIG
)
6760 for (op
= 0; op
< t
->operands
; ++op
)
6761 if (i
.types
[op
].bitfield
.zmmword
)
6763 if (op
>= t
->operands
)
6765 i
.error
= operand_size_mismatch
;
6771 /* Check the special Imm4 cases; must be the first operand. */
6772 if (is_cpu (t
, CpuXOP
) && t
->operands
== 5)
6774 if (i
.op
[0].imms
->X_op
!= O_constant
6775 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
6781 /* Turn off Imm<N> so that update_imm won't complain. */
6782 operand_type_set (&i
.types
[0], 0);
6785 /* Check vector Disp8 operand. */
6786 if (t
->opcode_modifier
.disp8memshift
6787 && i
.disp_encoding
<= disp_encoding_8bit
)
6789 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
6790 i
.memshift
= t
->opcode_modifier
.broadcast
- 1;
6791 else if (t
->opcode_modifier
.disp8memshift
!= DISP8_SHIFT_VL
)
6792 i
.memshift
= t
->opcode_modifier
.disp8memshift
;
6795 const i386_operand_type
*type
= NULL
, *fallback
= NULL
;
6798 for (op
= 0; op
< i
.operands
; op
++)
6799 if (i
.flags
[op
] & Operand_Mem
)
6801 if (t
->opcode_modifier
.evex
== EVEXLIG
)
6802 i
.memshift
= 2 + (i
.suffix
== QWORD_MNEM_SUFFIX
);
6803 else if (t
->operand_types
[op
].bitfield
.xmmword
6804 + t
->operand_types
[op
].bitfield
.ymmword
6805 + t
->operand_types
[op
].bitfield
.zmmword
<= 1)
6806 type
= &t
->operand_types
[op
];
6807 else if (!i
.types
[op
].bitfield
.unspecified
)
6808 type
= &i
.types
[op
];
6809 else /* Ambiguities get resolved elsewhere. */
6810 fallback
= &t
->operand_types
[op
];
6812 else if (i
.types
[op
].bitfield
.class == RegSIMD
6813 && t
->opcode_modifier
.evex
!= EVEXLIG
)
6815 if (i
.types
[op
].bitfield
.zmmword
)
6817 else if (i
.types
[op
].bitfield
.ymmword
&& i
.memshift
< 5)
6819 else if (i
.types
[op
].bitfield
.xmmword
&& i
.memshift
< 4)
6823 if (!type
&& !i
.memshift
)
6827 if (type
->bitfield
.zmmword
)
6829 else if (type
->bitfield
.ymmword
)
6831 else if (type
->bitfield
.xmmword
)
6835 /* For the check in fits_in_disp8(). */
6836 if (i
.memshift
== 0)
6840 for (op
= 0; op
< i
.operands
; op
++)
6841 if (operand_type_check (i
.types
[op
], disp
)
6842 && i
.op
[op
].disps
->X_op
== O_constant
)
6844 if (fits_in_disp8 (i
.op
[op
].disps
->X_add_number
))
6846 i
.types
[op
].bitfield
.disp8
= 1;
6849 i
.types
[op
].bitfield
.disp8
= 0;
6858 /* Check if encoding requirements are met by the instruction. */
6861 VEX_check_encoding (const insn_template
*t
)
6863 if (i
.vec_encoding
== vex_encoding_error
)
6865 i
.error
= unsupported
;
6869 /* Vector size restrictions. */
6870 if ((vector_size
< VSZ512
6871 && (t
->opcode_modifier
.evex
== EVEX512
6872 || t
->opcode_modifier
.vsz
>= VSZ512
))
6873 || (vector_size
< VSZ256
6874 && (t
->opcode_modifier
.evex
== EVEX256
6875 || t
->opcode_modifier
.vex
== VEX256
6876 || t
->opcode_modifier
.vsz
>= VSZ256
)))
6878 i
.error
= unsupported
;
6882 if (i
.vec_encoding
== vex_encoding_evex
)
6884 /* This instruction must be encoded with EVEX prefix. */
6885 if (!is_evex_encoding (t
))
6887 i
.error
= unsupported
;
6893 if (!t
->opcode_modifier
.vex
)
6895 /* This instruction template doesn't have VEX prefix. */
6896 if (i
.vec_encoding
!= vex_encoding_default
)
6898 i
.error
= unsupported
;
6907 /* Helper function for the progress() macro in match_template(). */
6908 static INLINE
enum i386_error
progress (enum i386_error
new,
6909 enum i386_error last
,
6910 unsigned int line
, unsigned int *line_p
)
6912 if (line
<= *line_p
)
6918 static const insn_template
*
6919 match_template (char mnem_suffix
)
6921 /* Points to template once we've found it. */
6922 const insn_template
*t
;
6923 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
6924 i386_operand_type overlap4
;
6925 unsigned int found_reverse_match
;
6926 i386_operand_type operand_types
[MAX_OPERANDS
];
6927 int addr_prefix_disp
;
6928 unsigned int j
, size_match
, check_register
, errline
= __LINE__
;
6929 enum i386_error specific_error
= number_of_operands_mismatch
;
6930 #define progress(err) progress (err, specific_error, __LINE__, &errline)
6932 #if MAX_OPERANDS != 5
6933 # error "MAX_OPERANDS must be 5."
6936 found_reverse_match
= 0;
6937 addr_prefix_disp
= -1;
6939 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
6941 addr_prefix_disp
= -1;
6942 found_reverse_match
= 0;
6944 /* Must have right number of operands. */
6945 if (i
.operands
!= t
->operands
)
6948 /* Check processor support. */
6949 specific_error
= progress (unsupported
);
6950 if (cpu_flags_match (t
) != CPU_FLAGS_PERFECT_MATCH
)
6953 /* Check AT&T mnemonic. */
6954 specific_error
= progress (unsupported_with_intel_mnemonic
);
6955 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
6958 /* Check AT&T/Intel syntax. */
6959 specific_error
= progress (unsupported_syntax
);
6960 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
6961 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
6964 /* Check Intel64/AMD64 ISA. */
6968 /* Default: Don't accept Intel64. */
6969 if (t
->opcode_modifier
.isa64
== INTEL64
)
6973 /* -mamd64: Don't accept Intel64 and Intel64 only. */
6974 if (t
->opcode_modifier
.isa64
>= INTEL64
)
6978 /* -mintel64: Don't accept AMD64. */
6979 if (t
->opcode_modifier
.isa64
== AMD64
&& flag_code
== CODE_64BIT
)
6984 /* Check the suffix. */
6985 specific_error
= progress (invalid_instruction_suffix
);
6986 if ((t
->opcode_modifier
.no_bsuf
&& mnem_suffix
== BYTE_MNEM_SUFFIX
)
6987 || (t
->opcode_modifier
.no_wsuf
&& mnem_suffix
== WORD_MNEM_SUFFIX
)
6988 || (t
->opcode_modifier
.no_lsuf
&& mnem_suffix
== LONG_MNEM_SUFFIX
)
6989 || (t
->opcode_modifier
.no_ssuf
&& mnem_suffix
== SHORT_MNEM_SUFFIX
)
6990 || (t
->opcode_modifier
.no_qsuf
&& mnem_suffix
== QWORD_MNEM_SUFFIX
))
6993 specific_error
= progress (operand_size_mismatch
);
6994 size_match
= operand_size_match (t
);
6998 /* This is intentionally not
7000 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
7002 as the case of a missing * on the operand is accepted (perhaps with
7003 a warning, issued further down). */
7004 specific_error
= progress (operand_type_mismatch
);
7005 if (i
.jumpabsolute
&& t
->opcode_modifier
.jump
!= JUMP_ABSOLUTE
)
7008 /* In Intel syntax, normally we can check for memory operand size when
7009 there is no mnemonic suffix. But jmp and call have 2 different
7010 encodings with Dword memory operand size. Skip the "near" one
7011 (permitting a register operand) when "far" was requested. */
7013 && t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
7014 && t
->operand_types
[0].bitfield
.class == Reg
)
7017 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7018 operand_types
[j
] = t
->operand_types
[j
];
7020 /* In general, don't allow 32-bit operands on pre-386. */
7021 specific_error
= progress (mnem_suffix
? invalid_instruction_suffix
7022 : operand_size_mismatch
);
7023 j
= i
.imm_operands
+ (t
->operands
> i
.imm_operands
+ 1);
7024 if (i
.suffix
== LONG_MNEM_SUFFIX
7025 && !cpu_arch_flags
.bitfield
.cpui386
7027 ? (t
->opcode_modifier
.mnemonicsize
!= IGNORESIZE
7028 && !intel_float_operand (insn_name (t
)))
7029 : intel_float_operand (insn_name (t
)) != 2)
7030 && (t
->operands
== i
.imm_operands
7031 || (operand_types
[i
.imm_operands
].bitfield
.class != RegMMX
7032 && operand_types
[i
.imm_operands
].bitfield
.class != RegSIMD
7033 && operand_types
[i
.imm_operands
].bitfield
.class != RegMask
)
7034 || (operand_types
[j
].bitfield
.class != RegMMX
7035 && operand_types
[j
].bitfield
.class != RegSIMD
7036 && operand_types
[j
].bitfield
.class != RegMask
))
7037 && !t
->opcode_modifier
.sib
)
7040 /* Do not verify operands when there are none. */
7043 if (VEX_check_encoding (t
))
7045 specific_error
= progress (i
.error
);
7049 /* We've found a match; break out of loop. */
7053 if (!t
->opcode_modifier
.jump
7054 || t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)
7056 /* There should be only one Disp operand. */
7057 for (j
= 0; j
< MAX_OPERANDS
; j
++)
7058 if (operand_type_check (operand_types
[j
], disp
))
7060 if (j
< MAX_OPERANDS
)
7062 bool override
= (i
.prefix
[ADDR_PREFIX
] != 0);
7064 addr_prefix_disp
= j
;
7066 /* Address size prefix will turn Disp64 operand into Disp32 and
7067 Disp32/Disp16 one into Disp16/Disp32 respectively. */
7071 override
= !override
;
7074 if (operand_types
[j
].bitfield
.disp32
7075 && operand_types
[j
].bitfield
.disp16
)
7077 operand_types
[j
].bitfield
.disp16
= override
;
7078 operand_types
[j
].bitfield
.disp32
= !override
;
7080 gas_assert (!operand_types
[j
].bitfield
.disp64
);
7084 if (operand_types
[j
].bitfield
.disp64
)
7086 gas_assert (!operand_types
[j
].bitfield
.disp32
);
7087 operand_types
[j
].bitfield
.disp32
= override
;
7088 operand_types
[j
].bitfield
.disp64
= !override
;
7090 operand_types
[j
].bitfield
.disp16
= 0;
7096 /* We check register size if needed. */
7097 if (t
->opcode_modifier
.checkoperandsize
)
7099 check_register
= (1 << t
->operands
) - 1;
7100 if (i
.broadcast
.type
|| i
.broadcast
.bytes
)
7101 check_register
&= ~(1 << i
.broadcast
.operand
);
7106 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
7107 switch (t
->operands
)
7110 if (!operand_type_match (overlap0
, i
.types
[0]))
7113 /* Allow the ModR/M encoding to be requested by using the {load} or
7114 {store} pseudo prefix on an applicable insn. */
7115 if (!t
->opcode_modifier
.modrm
7116 && i
.reg_operands
== 1
7117 && ((i
.dir_encoding
== dir_encoding_load
7118 && t
->mnem_off
!= MN_pop
)
7119 || (i
.dir_encoding
== dir_encoding_store
7120 && t
->mnem_off
!= MN_push
))
7122 && t
->mnem_off
!= MN_bswap
)
7127 /* xchg %eax, %eax is a special case. It is an alias for nop
7128 only in 32bit mode and we can use opcode 0x90. In 64bit
7129 mode, we can't use 0x90 for xchg %eax, %eax since it should
7130 zero-extend %eax to %rax. */
7131 if (t
->base_opcode
== 0x90
7132 && t
->opcode_space
== SPACE_BASE
)
7134 if (flag_code
== CODE_64BIT
7135 && i
.types
[0].bitfield
.instance
== Accum
7136 && i
.types
[0].bitfield
.dword
7137 && i
.types
[1].bitfield
.instance
== Accum
)
7140 /* Allow the ModR/M encoding to be requested by using the
7141 {load} or {store} pseudo prefix. */
7142 if (i
.dir_encoding
== dir_encoding_load
7143 || i
.dir_encoding
== dir_encoding_store
)
7147 if (t
->base_opcode
== MOV_AX_DISP32
7148 && t
->opcode_space
== SPACE_BASE
7149 && t
->mnem_off
!= MN_movabs
)
7151 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
7152 if (i
.reloc
[0] == BFD_RELOC_386_GOT32
)
7155 /* xrelease mov %eax, <disp> is another special case. It must not
7156 match the accumulator-only encoding of mov. */
7160 /* Allow the ModR/M encoding to be requested by using a suitable
7161 {load} or {store} pseudo prefix. */
7162 if (i
.dir_encoding
== (i
.types
[0].bitfield
.instance
== Accum
7163 ? dir_encoding_store
7164 : dir_encoding_load
)
7165 && !i
.types
[0].bitfield
.disp64
7166 && !i
.types
[1].bitfield
.disp64
)
7170 /* Allow the ModR/M encoding to be requested by using the {load} or
7171 {store} pseudo prefix on an applicable insn. */
7172 if (!t
->opcode_modifier
.modrm
7173 && i
.reg_operands
== 1
7174 && i
.imm_operands
== 1
7175 && (i
.dir_encoding
== dir_encoding_load
7176 || i
.dir_encoding
== dir_encoding_store
)
7177 && t
->opcode_space
== SPACE_BASE
)
7179 if (t
->base_opcode
== 0xb0 /* mov $imm, %reg */
7180 && i
.dir_encoding
== dir_encoding_store
)
7183 if ((t
->base_opcode
| 0x38) == 0x3c /* <alu> $imm, %acc */
7184 && (t
->base_opcode
!= 0x3c /* cmp $imm, %acc */
7185 || i
.dir_encoding
== dir_encoding_load
))
7188 if (t
->base_opcode
== 0xa8 /* test $imm, %acc */
7189 && i
.dir_encoding
== dir_encoding_load
)
7195 if (!(size_match
& MATCH_STRAIGHT
))
7197 /* Reverse direction of operands if swapping is possible in the first
7198 place (operands need to be symmetric) and
7199 - the load form is requested, and the template is a store form,
7200 - the store form is requested, and the template is a load form,
7201 - the non-default (swapped) form is requested. */
7202 overlap1
= operand_type_and (operand_types
[0], operand_types
[1]);
7203 if (t
->opcode_modifier
.d
&& i
.reg_operands
== i
.operands
7204 && !operand_type_all_zero (&overlap1
))
7205 switch (i
.dir_encoding
)
7207 case dir_encoding_load
:
7208 if (operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7209 || t
->opcode_modifier
.regmem
)
7213 case dir_encoding_store
:
7214 if (!operand_type_check (operand_types
[i
.operands
- 1], anymem
)
7215 && !t
->opcode_modifier
.regmem
)
7219 case dir_encoding_swap
:
7222 case dir_encoding_default
:
7225 /* If we want store form, we skip the current load. */
7226 if ((i
.dir_encoding
== dir_encoding_store
7227 || i
.dir_encoding
== dir_encoding_swap
)
7228 && i
.mem_operands
== 0
7229 && t
->opcode_modifier
.load
)
7234 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
7235 if (!operand_type_match (overlap0
, i
.types
[0])
7236 || !operand_type_match (overlap1
, i
.types
[1])
7237 || ((check_register
& 3) == 3
7238 && !operand_type_register_match (i
.types
[0],
7243 specific_error
= progress (i
.error
);
7245 /* Check if other direction is valid ... */
7246 if (!t
->opcode_modifier
.d
)
7250 if (!(size_match
& MATCH_REVERSE
))
7252 /* Try reversing direction of operands. */
7253 j
= is_cpu (t
, CpuFMA4
)
7254 || is_cpu (t
, CpuXOP
) ? 1 : i
.operands
- 1;
7255 overlap0
= operand_type_and (i
.types
[0], operand_types
[j
]);
7256 overlap1
= operand_type_and (i
.types
[j
], operand_types
[0]);
7257 overlap2
= operand_type_and (i
.types
[1], operand_types
[1]);
7258 gas_assert (t
->operands
!= 3 || !check_register
);
7259 if (!operand_type_match (overlap0
, i
.types
[0])
7260 || !operand_type_match (overlap1
, i
.types
[j
])
7261 || (t
->operands
== 3
7262 && !operand_type_match (overlap2
, i
.types
[1]))
7264 && !operand_type_register_match (i
.types
[0],
7269 /* Does not match either direction. */
7270 specific_error
= progress (i
.error
);
7273 /* found_reverse_match holds which variant of D
7275 if (!t
->opcode_modifier
.d
)
7276 found_reverse_match
= 0;
7277 else if (operand_types
[0].bitfield
.tbyte
)
7279 if (t
->opcode_modifier
.operandconstraint
!= UGH
)
7280 found_reverse_match
= Opcode_FloatD
;
7282 found_reverse_match
= ~0;
7283 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
7284 if ((t
->extension_opcode
& 4)
7285 && (intel_syntax
|| intel_mnemonic
))
7286 found_reverse_match
|= Opcode_FloatR
;
7288 else if (is_cpu (t
, CpuFMA4
) || is_cpu (t
, CpuXOP
))
7290 found_reverse_match
= Opcode_VexW
;
7291 goto check_operands_345
;
7293 else if (t
->opcode_space
!= SPACE_BASE
7294 && (t
->opcode_space
!= SPACE_0F
7295 /* MOV to/from CR/DR/TR, as an exception, follow
7296 the base opcode space encoding model. */
7297 || (t
->base_opcode
| 7) != 0x27))
7298 found_reverse_match
= (t
->base_opcode
& 0xee) != 0x6e
7299 ? Opcode_ExtD
: Opcode_SIMD_IntD
;
7300 else if (!t
->opcode_modifier
.commutative
)
7301 found_reverse_match
= Opcode_D
;
7303 found_reverse_match
= ~0;
7307 /* Found a forward 2 operand match here. */
7309 switch (t
->operands
)
7312 overlap4
= operand_type_and (i
.types
[4], operand_types
[4]);
7313 if (!operand_type_match (overlap4
, i
.types
[4])
7314 || !operand_type_register_match (i
.types
[3],
7319 specific_error
= progress (i
.error
);
7324 overlap3
= operand_type_and (i
.types
[3], operand_types
[3]);
7325 if (!operand_type_match (overlap3
, i
.types
[3])
7326 || ((check_register
& 0xa) == 0xa
7327 && !operand_type_register_match (i
.types
[1],
7331 || ((check_register
& 0xc) == 0xc
7332 && !operand_type_register_match (i
.types
[2],
7337 specific_error
= progress (i
.error
);
7342 overlap2
= operand_type_and (i
.types
[2], operand_types
[2]);
7343 if (!operand_type_match (overlap2
, i
.types
[2])
7344 || ((check_register
& 5) == 5
7345 && !operand_type_register_match (i
.types
[0],
7349 || ((check_register
& 6) == 6
7350 && !operand_type_register_match (i
.types
[1],
7355 specific_error
= progress (i
.error
);
7361 /* Found either forward/reverse 2, 3 or 4 operand match here:
7362 slip through to break. */
7365 /* Check if VEX/EVEX encoding requirements can be satisfied. */
7366 if (VEX_check_encoding (t
))
7368 specific_error
= progress (i
.error
);
7372 /* Check if vector operands are valid. */
7373 if (check_VecOperands (t
))
7375 specific_error
= progress (i
.error
);
7379 /* We've found a match; break out of loop. */
7385 if (t
== current_templates
->end
)
7387 /* We found no match. */
7388 i
.error
= specific_error
;
7392 if (!quiet_warnings
)
7395 && (i
.jumpabsolute
!= (t
->opcode_modifier
.jump
== JUMP_ABSOLUTE
)))
7396 as_warn (_("indirect %s without `*'"), insn_name (t
));
7398 if (t
->opcode_modifier
.isprefix
7399 && t
->opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7401 /* Warn them that a data or address size prefix doesn't
7402 affect assembly of the next line of code. */
7403 as_warn (_("stand-alone `%s' prefix"), insn_name (t
));
7407 /* Copy the template we found. */
7408 install_template (t
);
7410 if (addr_prefix_disp
!= -1)
7411 i
.tm
.operand_types
[addr_prefix_disp
]
7412 = operand_types
[addr_prefix_disp
];
7414 switch (found_reverse_match
)
7420 case Opcode_FloatR
| Opcode_FloatD
:
7421 i
.tm
.extension_opcode
^= Opcode_FloatR
>> 3;
7422 found_reverse_match
&= Opcode_FloatD
;
7426 /* If we found a reverse match we must alter the opcode direction
7427 bit and clear/flip the regmem modifier one. found_reverse_match
7428 holds bits to change (different for int & float insns). */
7430 i
.tm
.base_opcode
^= found_reverse_match
;
7432 /* Certain SIMD insns have their load forms specified in the opcode
7433 table, and hence we need to _set_ RegMem instead of clearing it.
7434 We need to avoid setting the bit though on insns like KMOVW. */
7435 i
.tm
.opcode_modifier
.regmem
7436 = i
.tm
.opcode_modifier
.modrm
&& i
.tm
.opcode_modifier
.d
7437 && i
.tm
.operands
> 2U - i
.tm
.opcode_modifier
.sse2avx
7438 && !i
.tm
.opcode_modifier
.regmem
;
7442 i
.tm
.operand_types
[0] = operand_types
[i
.operands
- 1];
7443 i
.tm
.operand_types
[i
.operands
- 1] = operand_types
[0];
7447 /* Only the first two register operands need reversing, alongside
7449 i
.tm
.opcode_modifier
.vexw
^= VEXW0
^ VEXW1
;
7451 j
= i
.tm
.operand_types
[0].bitfield
.imm8
;
7452 i
.tm
.operand_types
[j
] = operand_types
[j
+ 1];
7453 i
.tm
.operand_types
[j
+ 1] = operand_types
[j
];
7463 unsigned int es_op
= i
.tm
.opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
7464 unsigned int op
= i
.tm
.operand_types
[0].bitfield
.baseindex
? es_op
: 0;
7466 if (i
.seg
[op
] != NULL
&& i
.seg
[op
] != reg_es
)
7468 as_bad (_("`%s' operand %u must use `%ses' segment"),
7470 intel_syntax
? i
.tm
.operands
- es_op
: es_op
+ 1,
7475 /* There's only ever one segment override allowed per instruction.
7476 This instruction possibly has a legal segment override on the
7477 second operand, so copy the segment to where non-string
7478 instructions store it, allowing common code. */
7479 i
.seg
[op
] = i
.seg
[1];
7485 process_suffix (void)
7487 bool is_movx
= false;
7489 /* If matched instruction specifies an explicit instruction mnemonic
7491 if (i
.tm
.opcode_modifier
.size
== SIZE16
)
7492 i
.suffix
= WORD_MNEM_SUFFIX
;
7493 else if (i
.tm
.opcode_modifier
.size
== SIZE32
)
7494 i
.suffix
= LONG_MNEM_SUFFIX
;
7495 else if (i
.tm
.opcode_modifier
.size
== SIZE64
)
7496 i
.suffix
= QWORD_MNEM_SUFFIX
;
7497 else if (i
.reg_operands
7498 && (i
.operands
> 1 || i
.types
[0].bitfield
.class == Reg
)
7499 && i
.tm
.opcode_modifier
.operandconstraint
!= ADDR_PREFIX_OP_REG
)
7501 unsigned int numop
= i
.operands
;
7504 is_movx
= (i
.tm
.opcode_space
== SPACE_0F
7505 && (i
.tm
.base_opcode
| 8) == 0xbe)
7506 || (i
.tm
.opcode_space
== SPACE_BASE
7507 && i
.tm
.base_opcode
== 0x63
7508 && is_cpu (&i
.tm
, Cpu64
));
7510 /* movsx/movzx want only their source operand considered here, for the
7511 ambiguity checking below. The suffix will be replaced afterwards
7512 to represent the destination (register). */
7513 if (is_movx
&& (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63))
7516 /* crc32 needs REX.W set regardless of suffix / source operand size. */
7517 if (i
.tm
.mnem_off
== MN_crc32
&& i
.tm
.operand_types
[1].bitfield
.qword
)
7520 /* If there's no instruction mnemonic suffix we try to invent one
7521 based on GPR operands. */
7524 /* We take i.suffix from the last register operand specified,
7525 Destination register type is more significant than source
7526 register type. crc32 in SSE4.2 prefers source register
7528 unsigned int op
= i
.tm
.mnem_off
== MN_crc32
? 1 : i
.operands
;
7531 if (i
.tm
.operand_types
[op
].bitfield
.instance
== InstanceNone
7532 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
7534 if (i
.types
[op
].bitfield
.class != Reg
)
7536 if (i
.types
[op
].bitfield
.byte
)
7537 i
.suffix
= BYTE_MNEM_SUFFIX
;
7538 else if (i
.types
[op
].bitfield
.word
)
7539 i
.suffix
= WORD_MNEM_SUFFIX
;
7540 else if (i
.types
[op
].bitfield
.dword
)
7541 i
.suffix
= LONG_MNEM_SUFFIX
;
7542 else if (i
.types
[op
].bitfield
.qword
)
7543 i
.suffix
= QWORD_MNEM_SUFFIX
;
7549 /* As an exception, movsx/movzx silently default to a byte source
7551 if (is_movx
&& i
.tm
.opcode_modifier
.w
&& !i
.suffix
&& !intel_syntax
)
7552 i
.suffix
= BYTE_MNEM_SUFFIX
;
7554 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
7556 if (!check_byte_reg ())
7559 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
7561 if (!check_long_reg ())
7564 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
7566 if (!check_qword_reg ())
7569 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
7571 if (!check_word_reg ())
7574 else if (intel_syntax
7575 && i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
7576 /* Do nothing if the instruction is going to ignore the prefix. */
7581 /* Undo the movsx/movzx change done above. */
7584 else if (i
.tm
.opcode_modifier
.mnemonicsize
== DEFAULTSIZE
7587 i
.suffix
= stackop_size
;
7588 if (stackop_size
== LONG_MNEM_SUFFIX
)
7590 /* stackop_size is set to LONG_MNEM_SUFFIX for the
7591 .code16gcc directive to support 16-bit mode with
7592 32-bit address. For IRET without a suffix, generate
7593 16-bit IRET (opcode 0xcf) to return from an interrupt
7595 if (i
.tm
.base_opcode
== 0xcf)
7597 i
.suffix
= WORD_MNEM_SUFFIX
;
7598 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
7600 /* Warn about changed behavior for segment register push/pop. */
7601 else if ((i
.tm
.base_opcode
| 1) == 0x07)
7602 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
7607 && (i
.tm
.opcode_modifier
.jump
== JUMP_ABSOLUTE
7608 || i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7609 || i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
7610 || (i
.tm
.opcode_space
== SPACE_0F
7611 && i
.tm
.base_opcode
== 0x01 /* [ls][gi]dt */
7612 && i
.tm
.extension_opcode
<= 3)))
7617 if (!i
.tm
.opcode_modifier
.no_qsuf
)
7619 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
7620 || i
.tm
.opcode_modifier
.no_lsuf
)
7621 i
.suffix
= QWORD_MNEM_SUFFIX
;
7626 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7627 i
.suffix
= LONG_MNEM_SUFFIX
;
7630 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7631 i
.suffix
= WORD_MNEM_SUFFIX
;
7637 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7638 /* Also cover lret/retf/iret in 64-bit mode. */
7639 || (flag_code
== CODE_64BIT
7640 && !i
.tm
.opcode_modifier
.no_lsuf
7641 && !i
.tm
.opcode_modifier
.no_qsuf
))
7642 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7643 /* Explicit sizing prefixes are assumed to disambiguate insns. */
7644 && !i
.prefix
[DATA_PREFIX
] && !(i
.prefix
[REX_PREFIX
] & REX_W
)
7645 /* Accept FLDENV et al without suffix. */
7646 && (i
.tm
.opcode_modifier
.no_ssuf
|| i
.tm
.opcode_modifier
.floatmf
))
7648 unsigned int suffixes
, evex
= 0;
7650 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
7651 if (!i
.tm
.opcode_modifier
.no_wsuf
)
7653 if (!i
.tm
.opcode_modifier
.no_lsuf
)
7655 if (!i
.tm
.opcode_modifier
.no_ssuf
)
7657 if (flag_code
== CODE_64BIT
&& !i
.tm
.opcode_modifier
.no_qsuf
)
7660 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
7661 also suitable for AT&T syntax mode, it was requested that this be
7662 restricted to just Intel syntax. */
7663 if (intel_syntax
&& is_any_vex_encoding (&i
.tm
)
7664 && !i
.broadcast
.type
&& !i
.broadcast
.bytes
)
7668 for (op
= 0; op
< i
.tm
.operands
; ++op
)
7670 if (vector_size
< VSZ512
)
7672 i
.tm
.operand_types
[op
].bitfield
.zmmword
= 0;
7673 if (vector_size
< VSZ256
)
7675 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7676 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7677 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7678 || (!i
.tm
.opcode_modifier
.evex
7679 && is_evex_encoding (&i
.tm
))))
7680 i
.tm
.opcode_modifier
.evex
= EVEX128
;
7682 else if (i
.tm
.operand_types
[op
].bitfield
.ymmword
7683 && !i
.tm
.operand_types
[op
].bitfield
.xmmword
7684 && (i
.tm
.opcode_modifier
.evex
== EVEXDYN
7685 || (!i
.tm
.opcode_modifier
.evex
7686 && is_evex_encoding (&i
.tm
))))
7687 i
.tm
.opcode_modifier
.evex
= EVEX256
;
7689 else if (is_evex_encoding (&i
.tm
)
7690 && !cpu_arch_flags
.bitfield
.cpuavx512vl
)
7692 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7693 i
.tm
.operand_types
[op
].bitfield
.xmmword
= 0;
7694 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7695 i
.tm
.operand_types
[op
].bitfield
.ymmword
= 0;
7696 if (!i
.tm
.opcode_modifier
.evex
7697 || i
.tm
.opcode_modifier
.evex
== EVEXDYN
)
7698 i
.tm
.opcode_modifier
.evex
= EVEX512
;
7701 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
7702 + i
.tm
.operand_types
[op
].bitfield
.ymmword
7703 + i
.tm
.operand_types
[op
].bitfield
.zmmword
< 2)
7706 /* Any properly sized operand disambiguates the insn. */
7707 if (i
.types
[op
].bitfield
.xmmword
7708 || i
.types
[op
].bitfield
.ymmword
7709 || i
.types
[op
].bitfield
.zmmword
)
7711 suffixes
&= ~(7 << 6);
7716 if ((i
.flags
[op
] & Operand_Mem
)
7717 && i
.tm
.operand_types
[op
].bitfield
.unspecified
)
7719 if (i
.tm
.operand_types
[op
].bitfield
.xmmword
)
7721 if (i
.tm
.operand_types
[op
].bitfield
.ymmword
)
7723 if (i
.tm
.operand_types
[op
].bitfield
.zmmword
)
7725 if (is_evex_encoding (&i
.tm
))
7731 /* Are multiple suffixes / operand sizes allowed? */
7732 if (suffixes
& (suffixes
- 1))
7735 && (i
.tm
.opcode_modifier
.mnemonicsize
!= DEFAULTSIZE
7736 || operand_check
== check_error
))
7738 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i
.tm
));
7741 if (operand_check
== check_error
)
7743 as_bad (_("no instruction mnemonic suffix given and "
7744 "no register operands; can't size `%s'"), insn_name (&i
.tm
));
7747 if (operand_check
== check_warning
)
7748 as_warn (_("%s; using default for `%s'"),
7750 ? _("ambiguous operand size")
7751 : _("no instruction mnemonic suffix given and "
7752 "no register operands"),
7755 if (i
.tm
.opcode_modifier
.floatmf
)
7756 i
.suffix
= SHORT_MNEM_SUFFIX
;
7758 /* handled below */;
7760 i
.tm
.opcode_modifier
.evex
= evex
;
7761 else if (flag_code
== CODE_16BIT
)
7762 i
.suffix
= WORD_MNEM_SUFFIX
;
7763 else if (!i
.tm
.opcode_modifier
.no_lsuf
)
7764 i
.suffix
= LONG_MNEM_SUFFIX
;
7766 i
.suffix
= QWORD_MNEM_SUFFIX
;
7772 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
7773 In AT&T syntax, if there is no suffix (warned about above), the default
7774 will be byte extension. */
7775 if (i
.tm
.opcode_modifier
.w
&& i
.suffix
&& i
.suffix
!= BYTE_MNEM_SUFFIX
)
7776 i
.tm
.base_opcode
|= 1;
7778 /* For further processing, the suffix should represent the destination
7779 (register). This is already the case when one was used with
7780 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
7781 no suffix to begin with. */
7782 if (i
.tm
.opcode_modifier
.w
|| i
.tm
.base_opcode
== 0x63 || !i
.suffix
)
7784 if (i
.types
[1].bitfield
.word
)
7785 i
.suffix
= WORD_MNEM_SUFFIX
;
7786 else if (i
.types
[1].bitfield
.qword
)
7787 i
.suffix
= QWORD_MNEM_SUFFIX
;
7789 i
.suffix
= LONG_MNEM_SUFFIX
;
7791 i
.tm
.opcode_modifier
.w
= 0;
7795 if (!i
.tm
.opcode_modifier
.modrm
&& i
.reg_operands
&& i
.tm
.operands
< 3)
7796 i
.short_form
= (i
.tm
.operand_types
[0].bitfield
.class == Reg
)
7797 != (i
.tm
.operand_types
[1].bitfield
.class == Reg
);
7799 /* Change the opcode based on the operand size given by i.suffix. */
7802 /* Size floating point instruction. */
7803 case LONG_MNEM_SUFFIX
:
7804 if (i
.tm
.opcode_modifier
.floatmf
)
7806 i
.tm
.base_opcode
^= 4;
7810 case WORD_MNEM_SUFFIX
:
7811 case QWORD_MNEM_SUFFIX
:
7812 /* It's not a byte, select word/dword operation. */
7813 if (i
.tm
.opcode_modifier
.w
)
7816 i
.tm
.base_opcode
|= 8;
7818 i
.tm
.base_opcode
|= 1;
7821 case SHORT_MNEM_SUFFIX
:
7822 /* Now select between word & dword operations via the operand
7823 size prefix, except for instructions that will ignore this
7825 if (i
.suffix
!= QWORD_MNEM_SUFFIX
7826 && i
.tm
.opcode_modifier
.mnemonicsize
!= IGNORESIZE
7827 && !i
.tm
.opcode_modifier
.floatmf
7828 && !is_any_vex_encoding (&i
.tm
)
7829 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
7830 || (flag_code
== CODE_64BIT
7831 && i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)))
7833 unsigned int prefix
= DATA_PREFIX_OPCODE
;
7835 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
) /* jcxz, loop */
7836 prefix
= ADDR_PREFIX_OPCODE
;
7838 if (!add_prefix (prefix
))
7842 /* Set mode64 for an operand. */
7843 if (i
.suffix
== QWORD_MNEM_SUFFIX
7844 && flag_code
== CODE_64BIT
7845 && !i
.tm
.opcode_modifier
.norex64
7846 && !i
.tm
.opcode_modifier
.vexw
7847 /* Special case for xchg %rax,%rax. It is NOP and doesn't
7849 && ! (i
.operands
== 2
7850 && i
.tm
.base_opcode
== 0x90
7851 && i
.tm
.opcode_space
== SPACE_BASE
7852 && i
.types
[0].bitfield
.instance
== Accum
7853 && i
.types
[0].bitfield
.qword
7854 && i
.types
[1].bitfield
.instance
== Accum
))
7860 /* Select word/dword/qword operation with explicit data sizing prefix
7861 when there are no suitable register operands. */
7862 if (i
.tm
.opcode_modifier
.w
7863 && (i
.prefix
[DATA_PREFIX
] || (i
.prefix
[REX_PREFIX
] & REX_W
))
7865 || (i
.reg_operands
== 1
7867 && (i
.tm
.operand_types
[0].bitfield
.instance
== RegC
7869 || i
.tm
.operand_types
[0].bitfield
.instance
== RegD
7870 || i
.tm
.operand_types
[1].bitfield
.instance
== RegD
7871 || i
.tm
.mnem_off
== MN_crc32
))))
7872 i
.tm
.base_opcode
|= 1;
7876 if (i
.tm
.opcode_modifier
.operandconstraint
== ADDR_PREFIX_OP_REG
)
7878 gas_assert (!i
.suffix
);
7879 gas_assert (i
.reg_operands
);
7881 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
7884 /* The address size override prefix changes the size of the
7886 if (flag_code
== CODE_64BIT
7887 && i
.op
[0].regs
->reg_type
.bitfield
.word
)
7889 as_bad (_("16-bit addressing unavailable for `%s'"),
7894 if ((flag_code
== CODE_32BIT
7895 ? i
.op
[0].regs
->reg_type
.bitfield
.word
7896 : i
.op
[0].regs
->reg_type
.bitfield
.dword
)
7897 && !add_prefix (ADDR_PREFIX_OPCODE
))
7902 /* Check invalid register operand when the address size override
7903 prefix changes the size of register operands. */
7905 enum { need_word
, need_dword
, need_qword
} need
;
7907 /* Check the register operand for the address size prefix if
7908 the memory operand has no real registers, like symbol, DISP
7909 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
7910 if (i
.mem_operands
== 1
7911 && i
.reg_operands
== 1
7913 && i
.types
[1].bitfield
.class == Reg
7914 && (flag_code
== CODE_32BIT
7915 ? i
.op
[1].regs
->reg_type
.bitfield
.word
7916 : i
.op
[1].regs
->reg_type
.bitfield
.dword
)
7917 && ((i
.base_reg
== NULL
&& i
.index_reg
== NULL
)
7918 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7919 || (x86_elf_abi
== X86_64_X32_ABI
7921 && i
.base_reg
->reg_num
== RegIP
7922 && i
.base_reg
->reg_type
.bitfield
.qword
))
7926 && !add_prefix (ADDR_PREFIX_OPCODE
))
7929 if (flag_code
== CODE_32BIT
)
7930 need
= i
.prefix
[ADDR_PREFIX
] ? need_word
: need_dword
;
7931 else if (i
.prefix
[ADDR_PREFIX
])
7934 need
= flag_code
== CODE_64BIT
? need_qword
: need_word
;
7936 for (op
= 0; op
< i
.operands
; op
++)
7938 if (i
.types
[op
].bitfield
.class != Reg
)
7944 if (i
.op
[op
].regs
->reg_type
.bitfield
.word
)
7948 if (i
.op
[op
].regs
->reg_type
.bitfield
.dword
)
7952 if (i
.op
[op
].regs
->reg_type
.bitfield
.qword
)
7957 as_bad (_("invalid register operand size for `%s'"),
7968 check_byte_reg (void)
7972 for (op
= i
.operands
; --op
>= 0;)
7974 /* Skip non-register operands. */
7975 if (i
.types
[op
].bitfield
.class != Reg
)
7978 /* If this is an eight bit register, it's OK. If it's the 16 or
7979 32 bit version of an eight bit register, we will just use the
7980 low portion, and that's OK too. */
7981 if (i
.types
[op
].bitfield
.byte
)
7984 /* I/O port address operands are OK too. */
7985 if (i
.tm
.operand_types
[op
].bitfield
.instance
== RegD
7986 && i
.tm
.operand_types
[op
].bitfield
.word
)
7989 /* crc32 only wants its source operand checked here. */
7990 if (i
.tm
.mnem_off
== MN_crc32
&& op
!= 0)
7993 /* Any other register is bad. */
7994 as_bad (_("`%s%s' not allowed with `%s%c'"),
7995 register_prefix
, i
.op
[op
].regs
->reg_name
,
7996 insn_name (&i
.tm
), i
.suffix
);
8003 check_long_reg (void)
8007 for (op
= i
.operands
; --op
>= 0;)
8008 /* Skip non-register operands. */
8009 if (i
.types
[op
].bitfield
.class != Reg
)
8011 /* Reject eight bit registers, except where the template requires
8012 them. (eg. movzb) */
8013 else if (i
.types
[op
].bitfield
.byte
8014 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8015 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8016 && (i
.tm
.operand_types
[op
].bitfield
.word
8017 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8019 as_bad (_("`%s%s' not allowed with `%s%c'"),
8021 i
.op
[op
].regs
->reg_name
,
8026 /* Error if the e prefix on a general reg is missing. */
8027 else if (i
.types
[op
].bitfield
.word
8028 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8029 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8030 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8032 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8033 register_prefix
, i
.op
[op
].regs
->reg_name
,
8037 /* Warn if the r prefix on a general reg is present. */
8038 else if (i
.types
[op
].bitfield
.qword
8039 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8040 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8041 && i
.tm
.operand_types
[op
].bitfield
.dword
)
8043 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8044 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8051 check_qword_reg (void)
8055 for (op
= i
.operands
; --op
>= 0; )
8056 /* Skip non-register operands. */
8057 if (i
.types
[op
].bitfield
.class != Reg
)
8059 /* Reject eight bit registers, except where the template requires
8060 them. (eg. movzb) */
8061 else if (i
.types
[op
].bitfield
.byte
8062 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8063 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8064 && (i
.tm
.operand_types
[op
].bitfield
.word
8065 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8067 as_bad (_("`%s%s' not allowed with `%s%c'"),
8069 i
.op
[op
].regs
->reg_name
,
8074 /* Warn if the r prefix on a general reg is missing. */
8075 else if ((i
.types
[op
].bitfield
.word
8076 || i
.types
[op
].bitfield
.dword
)
8077 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8078 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8079 && i
.tm
.operand_types
[op
].bitfield
.qword
)
8081 /* Prohibit these changes in the 64bit mode, since the
8082 lowering is more complicated. */
8083 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8084 register_prefix
, i
.op
[op
].regs
->reg_name
, i
.suffix
);
8091 check_word_reg (void)
8094 for (op
= i
.operands
; --op
>= 0;)
8095 /* Skip non-register operands. */
8096 if (i
.types
[op
].bitfield
.class != Reg
)
8098 /* Reject eight bit registers, except where the template requires
8099 them. (eg. movzb) */
8100 else if (i
.types
[op
].bitfield
.byte
8101 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8102 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8103 && (i
.tm
.operand_types
[op
].bitfield
.word
8104 || i
.tm
.operand_types
[op
].bitfield
.dword
))
8106 as_bad (_("`%s%s' not allowed with `%s%c'"),
8108 i
.op
[op
].regs
->reg_name
,
8113 /* Error if the e or r prefix on a general reg is present. */
8114 else if ((i
.types
[op
].bitfield
.dword
8115 || i
.types
[op
].bitfield
.qword
)
8116 && (i
.tm
.operand_types
[op
].bitfield
.class == Reg
8117 || i
.tm
.operand_types
[op
].bitfield
.instance
== Accum
)
8118 && i
.tm
.operand_types
[op
].bitfield
.word
)
8120 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
8121 register_prefix
, i
.op
[op
].regs
->reg_name
,
8129 update_imm (unsigned int j
)
8131 i386_operand_type overlap
= i
.types
[j
];
8133 if (i
.tm
.operand_types
[j
].bitfield
.imm8
8134 && i
.tm
.operand_types
[j
].bitfield
.imm8s
8135 && overlap
.bitfield
.imm8
&& overlap
.bitfield
.imm8s
)
8137 /* This combination is used on 8-bit immediates where e.g. $~0 is
8138 desirable to permit. We're past operand type matching, so simply
8139 put things back in the shape they were before introducing the
8140 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
8141 overlap
.bitfield
.imm8s
= 0;
8144 if (overlap
.bitfield
.imm8
8145 + overlap
.bitfield
.imm8s
8146 + overlap
.bitfield
.imm16
8147 + overlap
.bitfield
.imm32
8148 + overlap
.bitfield
.imm32s
8149 + overlap
.bitfield
.imm64
> 1)
8151 static const i386_operand_type imm16
= { .bitfield
= { .imm16
= 1 } };
8152 static const i386_operand_type imm32
= { .bitfield
= { .imm32
= 1 } };
8153 static const i386_operand_type imm32s
= { .bitfield
= { .imm32s
= 1 } };
8154 static const i386_operand_type imm16_32
= { .bitfield
=
8155 { .imm16
= 1, .imm32
= 1 }
8157 static const i386_operand_type imm16_32s
= { .bitfield
=
8158 { .imm16
= 1, .imm32s
= 1 }
8160 static const i386_operand_type imm16_32_32s
= { .bitfield
=
8161 { .imm16
= 1, .imm32
= 1, .imm32s
= 1 }
8166 i386_operand_type temp
;
8168 operand_type_set (&temp
, 0);
8169 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
8171 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
8172 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
8174 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
8175 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
8176 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
8178 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
8179 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
8182 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
8185 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
8186 || operand_type_equal (&overlap
, &imm16_32
)
8187 || operand_type_equal (&overlap
, &imm16_32s
))
8189 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
8194 else if (i
.prefix
[REX_PREFIX
] & REX_W
)
8195 overlap
= operand_type_and (overlap
, imm32s
);
8196 else if (i
.prefix
[DATA_PREFIX
])
8197 overlap
= operand_type_and (overlap
,
8198 flag_code
!= CODE_16BIT
? imm16
: imm32
);
8199 if (overlap
.bitfield
.imm8
8200 + overlap
.bitfield
.imm8s
8201 + overlap
.bitfield
.imm16
8202 + overlap
.bitfield
.imm32
8203 + overlap
.bitfield
.imm32s
8204 + overlap
.bitfield
.imm64
!= 1)
8206 as_bad (_("no instruction mnemonic suffix given; "
8207 "can't determine immediate size"));
8211 i
.types
[j
] = overlap
;
8221 /* Update the first 2 immediate operands. */
8222 n
= i
.operands
> 2 ? 2 : i
.operands
;
8225 for (j
= 0; j
< n
; j
++)
8226 if (update_imm (j
) == 0)
8229 /* The 3rd operand can't be immediate operand. */
8230 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
8236 static INLINE
void set_rex_vrex (const reg_entry
*r
, unsigned int rex_bit
,
8239 if (r
->reg_flags
& RegRex
)
8241 if (i
.rex
& rex_bit
)
8242 as_bad (_("same type of prefix used twice"));
8245 else if (do_sse2avx
&& (i
.rex
& rex_bit
) && i
.vex
.register_specifier
)
8247 gas_assert (i
.vex
.register_specifier
== r
);
8248 i
.vex
.register_specifier
+= 8;
8251 if (r
->reg_flags
& RegVRex
)
8256 process_operands (void)
8258 /* Default segment register this instruction will use for memory
8259 accesses. 0 means unknown. This is only for optimizing out
8260 unnecessary segment overrides. */
8261 const reg_entry
*default_seg
= NULL
;
8263 /* We only need to check those implicit registers for instructions
8264 with 3 operands or less. */
8265 if (i
.operands
<= 3)
8266 for (unsigned int j
= 0; j
< i
.operands
; j
++)
8267 if (i
.types
[j
].bitfield
.instance
!= InstanceNone
)
8270 if (i
.tm
.opcode_modifier
.sse2avx
)
8272 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
8274 i
.rex
|= i
.prefix
[REX_PREFIX
] & (REX_W
| REX_R
| REX_X
| REX_B
);
8275 i
.prefix
[REX_PREFIX
] = 0;
8278 /* ImmExt should be processed after SSE2AVX. */
8279 else if (i
.tm
.opcode_modifier
.immext
)
8282 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
8283 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
8284 new destination operand here, while converting the source one to register
8286 if (i
.tm
.mnem_off
== MN_tilezero
)
8288 i
.op
[1].regs
= i
.op
[0].regs
;
8289 i
.op
[0].regs
-= i
.op
[0].regs
->reg_num
;
8290 i
.types
[1] = i
.types
[0];
8291 i
.tm
.operand_types
[1] = i
.tm
.operand_types
[0];
8292 i
.flags
[1] = i
.flags
[0];
8298 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
8300 static const i386_operand_type regxmm
= {
8301 .bitfield
= { .class = RegSIMD
, .xmmword
= 1 }
8303 unsigned int dupl
= i
.operands
;
8304 unsigned int dest
= dupl
- 1;
8307 /* The destination must be an xmm register. */
8308 gas_assert (i
.reg_operands
8309 && MAX_OPERANDS
> dupl
8310 && operand_type_equal (&i
.types
[dest
], ®xmm
));
8312 if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8313 && i
.tm
.operand_types
[0].bitfield
.xmmword
)
8315 /* Keep xmm0 for instructions with VEX prefix and 3
8317 i
.tm
.operand_types
[0].bitfield
.instance
= InstanceNone
;
8318 i
.tm
.operand_types
[0].bitfield
.class = RegSIMD
;
8323 if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_1ST_XMM0
)
8325 gas_assert ((MAX_OPERANDS
- 1) > dupl
);
8327 /* Add the implicit xmm0 for instructions with VEX prefix
8329 for (j
= i
.operands
; j
> 0; j
--)
8331 i
.op
[j
] = i
.op
[j
- 1];
8332 i
.types
[j
] = i
.types
[j
- 1];
8333 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
8334 i
.flags
[j
] = i
.flags
[j
- 1];
8337 = (const reg_entry
*) str_hash_find (reg_hash
, "xmm0");
8338 i
.types
[0] = regxmm
;
8339 i
.tm
.operand_types
[0] = regxmm
;
8342 i
.reg_operands
+= 2;
8347 i
.op
[dupl
] = i
.op
[dest
];
8348 i
.types
[dupl
] = i
.types
[dest
];
8349 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8350 i
.flags
[dupl
] = i
.flags
[dest
];
8359 i
.op
[dupl
] = i
.op
[dest
];
8360 i
.types
[dupl
] = i
.types
[dest
];
8361 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
8362 i
.flags
[dupl
] = i
.flags
[dest
];
8365 if (i
.tm
.opcode_modifier
.immext
)
8368 else if (i
.tm
.operand_types
[0].bitfield
.instance
== Accum
8369 && i
.tm
.opcode_modifier
.modrm
)
8373 for (j
= 1; j
< i
.operands
; j
++)
8375 i
.op
[j
- 1] = i
.op
[j
];
8376 i
.types
[j
- 1] = i
.types
[j
];
8378 /* We need to adjust fields in i.tm since they are used by
8379 build_modrm_byte. */
8380 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
8382 i
.flags
[j
- 1] = i
.flags
[j
];
8385 /* No adjustment to i.reg_operands: This was already done at the top
8390 else if (i
.tm
.opcode_modifier
.operandconstraint
== IMPLICIT_QUAD_GROUP
)
8392 unsigned int regnum
, first_reg_in_group
, last_reg_in_group
;
8394 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
8395 gas_assert (i
.operands
>= 2 && i
.types
[1].bitfield
.class == RegSIMD
);
8396 regnum
= register_number (i
.op
[1].regs
);
8397 first_reg_in_group
= regnum
& ~3;
8398 last_reg_in_group
= first_reg_in_group
+ 3;
8399 if (regnum
!= first_reg_in_group
)
8400 as_warn (_("source register `%s%s' implicitly denotes"
8401 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
8402 register_prefix
, i
.op
[1].regs
->reg_name
,
8403 register_prefix
, i
.op
[1].regs
->reg_name
, first_reg_in_group
,
8404 register_prefix
, i
.op
[1].regs
->reg_name
, last_reg_in_group
,
8407 else if (i
.tm
.opcode_modifier
.operandconstraint
== REG_KLUDGE
)
8409 /* The imul $imm, %reg instruction is converted into
8410 imul $imm, %reg, %reg, and the clr %reg instruction
8411 is converted into xor %reg, %reg. */
8413 unsigned int first_reg_op
;
8415 if (operand_type_check (i
.types
[0], reg
))
8419 /* Pretend we saw the extra register operand. */
8420 gas_assert (i
.reg_operands
== 1
8421 && i
.op
[first_reg_op
+ 1].regs
== 0);
8422 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
8423 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
8428 if (i
.tm
.opcode_modifier
.modrm
)
8430 /* The opcode is completed (modulo i.tm.extension_opcode which
8431 must be put into the modrm byte). Now, we make the modrm and
8432 index base bytes based on all the info we've collected. */
8434 default_seg
= build_modrm_byte ();
8436 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.operandconstraint
== UGH
)
8438 /* Warn about some common errors, but press on regardless. */
8439 if (i
.operands
== 2)
8441 /* Reversed arguments on faddp or fmulp. */
8442 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i
.tm
),
8443 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
8444 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
8446 else if (i
.tm
.opcode_modifier
.mnemonicsize
== IGNORESIZE
)
8448 /* Extraneous `l' suffix on fp insn. */
8449 as_warn (_("translating to `%s %s%s'"), insn_name (&i
.tm
),
8450 register_prefix
, i
.op
[0].regs
->reg_name
);
8454 else if (i
.types
[0].bitfield
.class == SReg
&& !dot_insn ())
8456 if (flag_code
!= CODE_64BIT
8457 ? i
.tm
.base_opcode
== POP_SEG_SHORT
8458 && i
.op
[0].regs
->reg_num
== 1
8459 : (i
.tm
.base_opcode
| 1) == (POP_SEG386_SHORT
& 0xff)
8460 && i
.op
[0].regs
->reg_num
< 4)
8462 as_bad (_("you can't `%s %s%s'"),
8463 insn_name (&i
.tm
), register_prefix
, i
.op
[0].regs
->reg_name
);
8466 if (i
.op
[0].regs
->reg_num
> 3
8467 && i
.tm
.opcode_space
== SPACE_BASE
)
8469 i
.tm
.base_opcode
^= (POP_SEG_SHORT
^ POP_SEG386_SHORT
) & 0xff;
8470 i
.tm
.opcode_space
= SPACE_0F
;
8472 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
8474 else if (i
.tm
.opcode_space
== SPACE_BASE
8475 && (i
.tm
.base_opcode
& ~3) == MOV_AX_DISP32
)
8477 default_seg
= reg_ds
;
8479 else if (i
.tm
.opcode_modifier
.isstring
)
8481 /* For the string instructions that allow a segment override
8482 on one of their operands, the default segment is ds. */
8483 default_seg
= reg_ds
;
8485 else if (i
.short_form
)
8487 /* The register operand is in the 1st or 2nd non-immediate operand. */
8488 const reg_entry
*r
= i
.op
[i
.imm_operands
].regs
;
8491 && r
->reg_type
.bitfield
.instance
== Accum
8492 && i
.op
[i
.imm_operands
+ 1].regs
)
8493 r
= i
.op
[i
.imm_operands
+ 1].regs
;
8494 /* Register goes in low 3 bits of opcode. */
8495 i
.tm
.base_opcode
|= r
->reg_num
;
8496 set_rex_vrex (r
, REX_B
, false);
8498 if (dot_insn () && i
.reg_operands
== 2)
8500 gas_assert (is_any_vex_encoding (&i
.tm
)
8501 || i
.vec_encoding
!= vex_encoding_default
);
8502 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8505 else if (i
.reg_operands
== 1
8506 && !i
.flags
[i
.operands
- 1]
8507 && i
.tm
.operand_types
[i
.operands
- 1].bitfield
.instance
8510 gas_assert (is_any_vex_encoding (&i
.tm
)
8511 || i
.vec_encoding
!= vex_encoding_default
);
8512 i
.vex
.register_specifier
= i
.op
[i
.operands
- 1].regs
;
8515 if ((i
.seg
[0] || i
.prefix
[SEG_PREFIX
])
8516 && i
.tm
.mnem_off
== MN_lea
)
8518 if (!quiet_warnings
)
8519 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i
.tm
));
8520 if (optimize
&& !i
.no_optimize
)
8523 i
.prefix
[SEG_PREFIX
] = 0;
8527 /* If a segment was explicitly specified, and the specified segment
8528 is neither the default nor the one already recorded from a prefix,
8529 use an opcode prefix to select it. If we never figured out what
8530 the default segment is, then default_seg will be zero at this
8531 point, and the specified segment prefix will always be used. */
8533 && i
.seg
[0] != default_seg
8534 && i386_seg_prefixes
[i
.seg
[0]->reg_num
] != i
.prefix
[SEG_PREFIX
])
8536 if (!add_prefix (i386_seg_prefixes
[i
.seg
[0]->reg_num
]))
8542 static const reg_entry
*
8543 build_modrm_byte (void)
8545 const reg_entry
*default_seg
= NULL
;
8546 unsigned int source
= i
.imm_operands
- i
.tm
.opcode_modifier
.immext
8547 /* Compensate for kludge in md_assemble(). */
8548 + i
.tm
.operand_types
[0].bitfield
.imm1
;
8549 unsigned int dest
= i
.operands
- 1 - i
.tm
.opcode_modifier
.immext
;
8550 unsigned int v
, op
, reg_slot
= ~0;
8552 /* Accumulator (in particular %st), shift count (%cl), and alike need
8553 to be skipped just like immediate operands do. */
8554 if (i
.tm
.operand_types
[source
].bitfield
.instance
)
8556 while (i
.tm
.operand_types
[dest
].bitfield
.instance
)
8559 for (op
= source
; op
< i
.operands
; ++op
)
8560 if (i
.tm
.operand_types
[op
].bitfield
.baseindex
)
8563 if (i
.reg_operands
+ i
.mem_operands
+ (i
.tm
.extension_opcode
!= None
) == 4)
8567 /* There are 2 kinds of instructions:
8568 1. 5 operands: 4 register operands or 3 register operands
8569 plus 1 memory operand plus one Imm4 operand, VexXDS, and
8570 VexW0 or VexW1. The destination must be either XMM, YMM or
8572 2. 4 operands: 4 register operands or 3 register operands
8573 plus 1 memory operand, with VexXDS.
8574 3. Other equivalent combinations when coming from s_insn(). */
8575 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
8576 && i
.tm
.opcode_modifier
.vexw
);
8577 gas_assert (dot_insn ()
8578 || i
.tm
.operand_types
[dest
].bitfield
.class == RegSIMD
);
8580 /* Of the first two non-immediate operands the one with the template
8581 not allowing for a memory one is encoded in the immediate operand. */
8583 reg_slot
= source
+ 1;
8585 reg_slot
= source
++;
8589 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class == RegSIMD
);
8590 gas_assert (!(i
.op
[reg_slot
].regs
->reg_flags
& RegVRex
));
8593 gas_assert (i
.tm
.operand_types
[reg_slot
].bitfield
.class != ClassNone
);
8595 if (i
.imm_operands
== 0)
8597 /* When there is no immediate operand, generate an 8bit
8598 immediate operand to encode the first operand. */
8599 exp
= &im_expressions
[i
.imm_operands
++];
8600 i
.op
[i
.operands
].imms
= exp
;
8601 i
.types
[i
.operands
].bitfield
.imm8
= 1;
8604 exp
->X_op
= O_constant
;
8608 gas_assert (i
.imm_operands
== 1);
8609 gas_assert (fits_in_imm4 (i
.op
[0].imms
->X_add_number
));
8610 gas_assert (!i
.tm
.opcode_modifier
.immext
);
8612 /* Turn on Imm8 again so that output_imm will generate it. */
8613 i
.types
[0].bitfield
.imm8
= 1;
8617 exp
->X_add_number
|= register_number (i
.op
[reg_slot
].regs
)
8618 << (3 + !(is_evex_encoding (&i
.tm
)
8619 || i
.vec_encoding
== vex_encoding_evex
));
8622 for (v
= source
+ 1; v
< dest
; ++v
)
8627 if (i
.tm
.extension_opcode
!= None
)
8633 gas_assert (source
< dest
);
8634 if (i
.tm
.opcode_modifier
.operandconstraint
== SWAP_SOURCES
8637 unsigned int tmp
= source
;
8643 if (v
< MAX_OPERANDS
)
8645 gas_assert (i
.tm
.opcode_modifier
.vexvvvv
);
8646 i
.vex
.register_specifier
= i
.op
[v
].regs
;
8649 if (op
< i
.operands
)
8653 unsigned int fake_zero_displacement
= 0;
8655 gas_assert (i
.flags
[op
] & Operand_Mem
);
8657 if (i
.tm
.opcode_modifier
.sib
)
8659 /* The index register of VSIB shouldn't be RegIZ. */
8660 if (i
.tm
.opcode_modifier
.sib
!= SIBMEM
8661 && i
.index_reg
->reg_num
== RegIZ
)
8664 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8667 i
.sib
.base
= NO_BASE_REGISTER
;
8668 i
.sib
.scale
= i
.log2_scale_factor
;
8669 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8670 i
.types
[op
].bitfield
.disp32
= 1;
8673 /* Since the mandatory SIB always has index register, so
8674 the code logic remains unchanged. The non-mandatory SIB
8675 without index register is allowed and will be handled
8679 if (i
.index_reg
->reg_num
== RegIZ
)
8680 i
.sib
.index
= NO_INDEX_REGISTER
;
8682 i
.sib
.index
= i
.index_reg
->reg_num
;
8683 set_rex_vrex (i
.index_reg
, REX_X
, false);
8687 default_seg
= reg_ds
;
8689 if (i
.base_reg
== 0)
8692 if (!i
.disp_operands
)
8693 fake_zero_displacement
= 1;
8694 if (i
.index_reg
== 0)
8696 /* Both check for VSIB and mandatory non-vector SIB. */
8697 gas_assert (!i
.tm
.opcode_modifier
.sib
8698 || i
.tm
.opcode_modifier
.sib
== SIBMEM
);
8699 /* Operand is just <disp> */
8700 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8701 if (flag_code
== CODE_64BIT
)
8703 /* 64bit mode overwrites the 32bit absolute
8704 addressing by RIP relative addressing and
8705 absolute addressing is encoded by one of the
8706 redundant SIB forms. */
8707 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8708 i
.sib
.base
= NO_BASE_REGISTER
;
8709 i
.sib
.index
= NO_INDEX_REGISTER
;
8710 i
.types
[op
].bitfield
.disp32
= 1;
8712 else if ((flag_code
== CODE_16BIT
)
8713 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
8715 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
8716 i
.types
[op
].bitfield
.disp16
= 1;
8720 i
.rm
.regmem
= NO_BASE_REGISTER
;
8721 i
.types
[op
].bitfield
.disp32
= 1;
8724 else if (!i
.tm
.opcode_modifier
.sib
)
8726 /* !i.base_reg && i.index_reg */
8727 if (i
.index_reg
->reg_num
== RegIZ
)
8728 i
.sib
.index
= NO_INDEX_REGISTER
;
8730 i
.sib
.index
= i
.index_reg
->reg_num
;
8731 i
.sib
.base
= NO_BASE_REGISTER
;
8732 i
.sib
.scale
= i
.log2_scale_factor
;
8733 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8734 i
.types
[op
] = operand_type_and_not (i
.types
[op
], anydisp
);
8735 i
.types
[op
].bitfield
.disp32
= 1;
8736 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8740 /* RIP addressing for 64bit mode. */
8741 else if (i
.base_reg
->reg_num
== RegIP
)
8743 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8744 i
.rm
.regmem
= NO_BASE_REGISTER
;
8745 i
.types
[op
].bitfield
.disp8
= 0;
8746 i
.types
[op
].bitfield
.disp16
= 0;
8747 i
.types
[op
].bitfield
.disp32
= 1;
8748 i
.types
[op
].bitfield
.disp64
= 0;
8749 i
.flags
[op
] |= Operand_PCrel
;
8750 if (! i
.disp_operands
)
8751 fake_zero_displacement
= 1;
8753 else if (i
.base_reg
->reg_type
.bitfield
.word
)
8755 gas_assert (!i
.tm
.opcode_modifier
.sib
);
8756 switch (i
.base_reg
->reg_num
)
8759 if (i
.index_reg
== 0)
8761 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
8762 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
8765 default_seg
= reg_ss
;
8766 if (i
.index_reg
== 0)
8769 if (operand_type_check (i
.types
[op
], disp
) == 0)
8771 /* fake (%bp) into 0(%bp) */
8772 if (i
.disp_encoding
== disp_encoding_16bit
)
8773 i
.types
[op
].bitfield
.disp16
= 1;
8775 i
.types
[op
].bitfield
.disp8
= 1;
8776 fake_zero_displacement
= 1;
8779 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
8780 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
8782 default: /* (%si) -> 4 or (%di) -> 5 */
8783 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
8785 if (!fake_zero_displacement
8789 fake_zero_displacement
= 1;
8790 if (i
.disp_encoding
== disp_encoding_8bit
)
8791 i
.types
[op
].bitfield
.disp8
= 1;
8793 i
.types
[op
].bitfield
.disp16
= 1;
8795 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8797 else /* i.base_reg and 32/64 bit mode */
8799 if (operand_type_check (i
.types
[op
], disp
))
8801 i
.types
[op
].bitfield
.disp16
= 0;
8802 i
.types
[op
].bitfield
.disp64
= 0;
8803 i
.types
[op
].bitfield
.disp32
= 1;
8806 if (!i
.tm
.opcode_modifier
.sib
)
8807 i
.rm
.regmem
= i
.base_reg
->reg_num
;
8808 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
8810 i
.sib
.base
= i
.base_reg
->reg_num
;
8811 /* x86-64 ignores REX prefix bit here to avoid decoder
8813 if (!(i
.base_reg
->reg_flags
& RegRex
)
8814 && (i
.base_reg
->reg_num
== EBP_REG_NUM
8815 || i
.base_reg
->reg_num
== ESP_REG_NUM
))
8816 default_seg
= reg_ss
;
8817 if (i
.base_reg
->reg_num
== 5 && i
.disp_operands
== 0)
8819 fake_zero_displacement
= 1;
8820 if (i
.disp_encoding
== disp_encoding_32bit
)
8821 i
.types
[op
].bitfield
.disp32
= 1;
8823 i
.types
[op
].bitfield
.disp8
= 1;
8825 i
.sib
.scale
= i
.log2_scale_factor
;
8826 if (i
.index_reg
== 0)
8828 /* Only check for VSIB. */
8829 gas_assert (i
.tm
.opcode_modifier
.sib
!= VECSIB128
8830 && i
.tm
.opcode_modifier
.sib
!= VECSIB256
8831 && i
.tm
.opcode_modifier
.sib
!= VECSIB512
);
8833 /* <disp>(%esp) becomes two byte modrm with no index
8834 register. We've already stored the code for esp
8835 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
8836 Any base register besides %esp will not use the
8837 extra modrm byte. */
8838 i
.sib
.index
= NO_INDEX_REGISTER
;
8840 else if (!i
.tm
.opcode_modifier
.sib
)
8842 if (i
.index_reg
->reg_num
== RegIZ
)
8843 i
.sib
.index
= NO_INDEX_REGISTER
;
8845 i
.sib
.index
= i
.index_reg
->reg_num
;
8846 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
8847 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
8852 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
8853 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
8857 if (!fake_zero_displacement
8861 fake_zero_displacement
= 1;
8862 if (i
.disp_encoding
== disp_encoding_8bit
)
8863 i
.types
[op
].bitfield
.disp8
= 1;
8865 i
.types
[op
].bitfield
.disp32
= 1;
8867 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
8871 if (fake_zero_displacement
)
8873 /* Fakes a zero displacement assuming that i.types[op]
8874 holds the correct displacement size. */
8877 gas_assert (i
.op
[op
].disps
== 0);
8878 exp
= &disp_expressions
[i
.disp_operands
++];
8879 i
.op
[op
].disps
= exp
;
8880 exp
->X_op
= O_constant
;
8881 exp
->X_add_number
= 0;
8882 exp
->X_add_symbol
= (symbolS
*) 0;
8883 exp
->X_op_symbol
= (symbolS
*) 0;
8889 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
8890 set_rex_vrex (i
.op
[op
].regs
, REX_B
, false);
8901 if (!i
.tm
.opcode_modifier
.regmem
)
8903 gas_assert (source
< MAX_OPERANDS
);
8904 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
8905 set_rex_vrex (i
.op
[source
].regs
, REX_B
,
8906 dest
>= MAX_OPERANDS
&& i
.tm
.opcode_modifier
.sse2avx
);
8911 gas_assert (dest
< MAX_OPERANDS
);
8912 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
8913 set_rex_vrex (i
.op
[dest
].regs
, REX_B
, i
.tm
.opcode_modifier
.sse2avx
);
8918 /* Fill in i.rm.reg field with extension opcode (if any) or the
8919 appropriate register. */
8920 if (i
.tm
.extension_opcode
!= None
)
8921 i
.rm
.reg
= i
.tm
.extension_opcode
;
8922 else if (!i
.tm
.opcode_modifier
.regmem
&& dest
< MAX_OPERANDS
)
8924 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
8925 set_rex_vrex (i
.op
[dest
].regs
, REX_R
, i
.tm
.opcode_modifier
.sse2avx
);
8929 gas_assert (source
< MAX_OPERANDS
);
8930 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
8931 set_rex_vrex (i
.op
[source
].regs
, REX_R
, false);
8934 if (flag_code
!= CODE_64BIT
&& (i
.rex
& REX_R
))
8936 gas_assert (i
.types
[!i
.tm
.opcode_modifier
.regmem
].bitfield
.class == RegCR
);
8938 add_prefix (LOCK_PREFIX_OPCODE
);
8945 frag_opcode_byte (unsigned char byte
)
8947 if (now_seg
!= absolute_section
)
8948 FRAG_APPEND_1_CHAR (byte
);
8950 ++abs_section_offset
;
8954 flip_code16 (unsigned int code16
)
8956 gas_assert (i
.tm
.operands
== 1);
8958 return !(i
.prefix
[REX_PREFIX
] & REX_W
)
8959 && (code16
? i
.tm
.operand_types
[0].bitfield
.disp32
8960 : i
.tm
.operand_types
[0].bitfield
.disp16
)
8965 output_branch (void)
8971 relax_substateT subtype
;
8975 if (now_seg
== absolute_section
)
8977 as_bad (_("relaxable branches not supported in absolute section"));
8981 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
8982 size
= i
.disp_encoding
> disp_encoding_8bit
? BIG
: SMALL
;
8985 if (i
.prefix
[DATA_PREFIX
] != 0)
8989 code16
^= flip_code16(code16
);
8991 /* Pentium4 branch hints. */
8992 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
8993 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
8998 if (i
.prefix
[REX_PREFIX
] != 0)
9004 /* BND prefixed jump. */
9005 if (i
.prefix
[BND_PREFIX
] != 0)
9011 if (i
.prefixes
!= 0)
9012 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9014 /* It's always a symbol; End frag & setup for relax.
9015 Make sure there is enough room in this frag for the largest
9016 instruction we may generate in md_convert_frag. This is 2
9017 bytes for the opcode and room for the prefix and largest
9019 frag_grow (prefix
+ 2 + 4);
9020 /* Prefix and 1 opcode byte go in fr_fix. */
9021 p
= frag_more (prefix
+ 1);
9022 if (i
.prefix
[DATA_PREFIX
] != 0)
9023 *p
++ = DATA_PREFIX_OPCODE
;
9024 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
9025 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
9026 *p
++ = i
.prefix
[SEG_PREFIX
];
9027 if (i
.prefix
[BND_PREFIX
] != 0)
9028 *p
++ = BND_PREFIX_OPCODE
;
9029 if (i
.prefix
[REX_PREFIX
] != 0)
9030 *p
++ = i
.prefix
[REX_PREFIX
];
9031 *p
= i
.tm
.base_opcode
;
9033 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
9034 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
9035 else if (cpu_arch_flags
.bitfield
.cpui386
)
9036 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
9038 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
9041 sym
= i
.op
[0].disps
->X_add_symbol
;
9042 off
= i
.op
[0].disps
->X_add_number
;
9044 if (i
.op
[0].disps
->X_op
!= O_constant
9045 && i
.op
[0].disps
->X_op
!= O_symbol
)
9047 /* Handle complex expressions. */
9048 sym
= make_expr_symbol (i
.op
[0].disps
);
9052 frag_now
->tc_frag_data
.code64
= flag_code
== CODE_64BIT
;
9054 /* 1 possible extra opcode + 4 byte displacement go in var part.
9055 Pass reloc in fr_var. */
9056 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
9059 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9060 /* Return TRUE iff PLT32 relocation should be used for branching to
9064 need_plt32_p (symbolS
*s
)
9066 /* PLT32 relocation is ELF only. */
9071 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
9072 krtld support it. */
9076 /* Since there is no need to prepare for PLT branch on x86-64, we
9077 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
9078 be used as a marker for 32-bit PC-relative branches. */
9085 /* Weak or undefined symbol need PLT32 relocation. */
9086 if (S_IS_WEAK (s
) || !S_IS_DEFINED (s
))
9089 /* Non-global symbol doesn't need PLT32 relocation. */
9090 if (! S_IS_EXTERNAL (s
))
9093 /* Other global symbols need PLT32 relocation. NB: Symbol with
9094 non-default visibilities are treated as normal global symbol
9095 so that PLT32 relocation can be used as a marker for 32-bit
9096 PC-relative branches. It is useful for linker relaxation. */
9107 bfd_reloc_code_real_type jump_reloc
= i
.reloc
[0];
9109 if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
)
9111 /* This is a loop or jecxz type instruction. */
9113 if (i
.prefix
[ADDR_PREFIX
] != 0)
9115 frag_opcode_byte (ADDR_PREFIX_OPCODE
);
9118 /* Pentium4 branch hints. */
9119 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
9120 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
9122 frag_opcode_byte (i
.prefix
[SEG_PREFIX
]);
9131 if (flag_code
== CODE_16BIT
)
9134 if (i
.prefix
[DATA_PREFIX
] != 0)
9136 frag_opcode_byte (DATA_PREFIX_OPCODE
);
9138 code16
^= flip_code16(code16
);
9146 /* BND prefixed jump. */
9147 if (i
.prefix
[BND_PREFIX
] != 0)
9149 frag_opcode_byte (i
.prefix
[BND_PREFIX
]);
9153 if (i
.prefix
[REX_PREFIX
] != 0)
9155 frag_opcode_byte (i
.prefix
[REX_PREFIX
]);
9159 if (i
.prefixes
!= 0)
9160 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9162 if (now_seg
== absolute_section
)
9164 abs_section_offset
+= i
.opcode_length
+ size
;
9168 p
= frag_more (i
.opcode_length
+ size
);
9169 switch (i
.opcode_length
)
9172 *p
++ = i
.tm
.base_opcode
>> 8;
9175 *p
++ = i
.tm
.base_opcode
;
9181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9182 if (flag_code
== CODE_64BIT
&& size
== 4
9183 && jump_reloc
== NO_RELOC
&& i
.op
[0].disps
->X_add_number
== 0
9184 && need_plt32_p (i
.op
[0].disps
->X_add_symbol
))
9185 jump_reloc
= BFD_RELOC_X86_64_PLT32
;
9188 jump_reloc
= reloc (size
, 1, 1, jump_reloc
);
9190 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9191 i
.op
[0].disps
, 1, jump_reloc
);
9193 /* All jumps handled here are signed, but don't unconditionally use a
9194 signed limit check for 32 and 16 bit jumps as we want to allow wrap
9195 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
9200 fixP
->fx_signed
= 1;
9204 if (i
.tm
.mnem_off
== MN_xbegin
)
9205 fixP
->fx_signed
= 1;
9209 if (flag_code
== CODE_64BIT
)
9210 fixP
->fx_signed
= 1;
9216 output_interseg_jump (void)
9224 if (flag_code
== CODE_16BIT
)
9228 if (i
.prefix
[DATA_PREFIX
] != 0)
9235 gas_assert (!i
.prefix
[REX_PREFIX
]);
9241 if (i
.prefixes
!= 0)
9242 as_warn (_("skipping prefixes on `%s'"), insn_name (&i
.tm
));
9244 if (now_seg
== absolute_section
)
9246 abs_section_offset
+= prefix
+ 1 + 2 + size
;
9250 /* 1 opcode; 2 segment; offset */
9251 p
= frag_more (prefix
+ 1 + 2 + size
);
9253 if (i
.prefix
[DATA_PREFIX
] != 0)
9254 *p
++ = DATA_PREFIX_OPCODE
;
9256 if (i
.prefix
[REX_PREFIX
] != 0)
9257 *p
++ = i
.prefix
[REX_PREFIX
];
9259 *p
++ = i
.tm
.base_opcode
;
9260 if (i
.op
[1].imms
->X_op
== O_constant
)
9262 offsetT n
= i
.op
[1].imms
->X_add_number
;
9265 && !fits_in_unsigned_word (n
)
9266 && !fits_in_signed_word (n
))
9268 as_bad (_("16-bit jump out of range"));
9271 md_number_to_chars (p
, n
, size
);
9274 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
9275 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
9278 if (i
.op
[0].imms
->X_op
== O_constant
)
9279 md_number_to_chars (p
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
9281 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 2,
9282 i
.op
[0].imms
, 0, reloc (2, 0, 0, i
.reloc
[0]));
9285 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9290 asection
*seg
= now_seg
;
9291 subsegT subseg
= now_subseg
;
9293 unsigned int alignment
, align_size_1
;
9294 unsigned int isa_1_descsz
, feature_2_descsz
, descsz
;
9295 unsigned int isa_1_descsz_raw
, feature_2_descsz_raw
;
9296 unsigned int padding
;
9298 if (!IS_ELF
|| !x86_used_note
)
9301 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X86
;
9303 /* The .note.gnu.property section layout:
9305 Field Length Contents
9308 n_descsz 4 The note descriptor size
9309 n_type 4 NT_GNU_PROPERTY_TYPE_0
9311 n_desc n_descsz The program property array
9315 /* Create the .note.gnu.property section. */
9316 sec
= subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME
, 0);
9317 bfd_set_section_flags (sec
,
9324 if (get_elf_backend_data (stdoutput
)->s
->elfclass
== ELFCLASS64
)
9335 bfd_set_section_alignment (sec
, alignment
);
9336 elf_section_type (sec
) = SHT_NOTE
;
9338 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
9340 isa_1_descsz_raw
= 4 + 4 + 4;
9341 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
9342 isa_1_descsz
= (isa_1_descsz_raw
+ align_size_1
) & ~align_size_1
;
9344 feature_2_descsz_raw
= isa_1_descsz
;
9345 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
9347 feature_2_descsz_raw
+= 4 + 4 + 4;
9348 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
9349 feature_2_descsz
= ((feature_2_descsz_raw
+ align_size_1
)
9352 descsz
= feature_2_descsz
;
9353 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
9354 p
= frag_more (4 + 4 + 4 + 4 + descsz
);
9356 /* Write n_namsz. */
9357 md_number_to_chars (p
, (valueT
) 4, 4);
9359 /* Write n_descsz. */
9360 md_number_to_chars (p
+ 4, (valueT
) descsz
, 4);
9363 md_number_to_chars (p
+ 4 * 2, (valueT
) NT_GNU_PROPERTY_TYPE_0
, 4);
9366 memcpy (p
+ 4 * 3, "GNU", 4);
9368 /* Write 4-byte type. */
9369 md_number_to_chars (p
+ 4 * 4,
9370 (valueT
) GNU_PROPERTY_X86_ISA_1_USED
, 4);
9372 /* Write 4-byte data size. */
9373 md_number_to_chars (p
+ 4 * 5, (valueT
) 4, 4);
9375 /* Write 4-byte data. */
9376 md_number_to_chars (p
+ 4 * 6, (valueT
) x86_isa_1_used
, 4);
9378 /* Zero out paddings. */
9379 padding
= isa_1_descsz
- isa_1_descsz_raw
;
9381 memset (p
+ 4 * 7, 0, padding
);
9383 /* Write 4-byte type. */
9384 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 4,
9385 (valueT
) GNU_PROPERTY_X86_FEATURE_2_USED
, 4);
9387 /* Write 4-byte data size. */
9388 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 5, (valueT
) 4, 4);
9390 /* Write 4-byte data. */
9391 md_number_to_chars (p
+ isa_1_descsz
+ 4 * 6,
9392 (valueT
) x86_feature_2_used
, 4);
9394 /* Zero out paddings. */
9395 padding
= feature_2_descsz
- feature_2_descsz_raw
;
9397 memset (p
+ isa_1_descsz
+ 4 * 7, 0, padding
);
9399 /* We probably can't restore the current segment, for there likely
9402 subseg_set (seg
, subseg
);
9406 x86_support_sframe_p (void)
9408 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
9409 return (x86_elf_abi
== X86_64_ABI
);
9413 x86_sframe_ra_tracking_p (void)
9415 /* In AMD64, return address is always stored on the stack at a fixed offset
9416 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
9417 Do not track explicitly via an SFrame Frame Row Entry. */
9422 x86_sframe_cfa_ra_offset (void)
9424 gas_assert (x86_elf_abi
== X86_64_ABI
);
9425 return (offsetT
) -8;
9429 x86_sframe_get_abi_arch (void)
9431 unsigned char sframe_abi_arch
= 0;
9433 if (x86_support_sframe_p ())
9435 gas_assert (!target_big_endian
);
9436 sframe_abi_arch
= SFRAME_ABI_AMD64_ENDIAN_LITTLE
;
9439 return sframe_abi_arch
;
9445 encoding_length (const fragS
*start_frag
, offsetT start_off
,
9446 const char *frag_now_ptr
)
9448 unsigned int len
= 0;
9450 if (start_frag
!= frag_now
)
9452 const fragS
*fr
= start_frag
;
9457 } while (fr
&& fr
!= frag_now
);
9460 return len
- start_off
+ (frag_now_ptr
- frag_now
->fr_literal
);
9463 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
9464 be macro-fused with conditional jumps.
9465 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
9466 or is one of the following format:
9479 maybe_fused_with_jcc_p (enum mf_cmp_kind
* mf_cmp_p
)
9481 /* No RIP address. */
9482 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
9485 /* No opcodes outside of base encoding space. */
9486 if (i
.tm
.opcode_space
!= SPACE_BASE
)
9489 /* add, sub without add/sub m, imm. */
9490 if (i
.tm
.base_opcode
<= 5
9491 || (i
.tm
.base_opcode
>= 0x28 && i
.tm
.base_opcode
<= 0x2d)
9492 || ((i
.tm
.base_opcode
| 3) == 0x83
9493 && (i
.tm
.extension_opcode
== 0x5
9494 || i
.tm
.extension_opcode
== 0x0)))
9496 *mf_cmp_p
= mf_cmp_alu_cmp
;
9497 return !(i
.mem_operands
&& i
.imm_operands
);
9500 /* and without and m, imm. */
9501 if ((i
.tm
.base_opcode
>= 0x20 && i
.tm
.base_opcode
<= 0x25)
9502 || ((i
.tm
.base_opcode
| 3) == 0x83
9503 && i
.tm
.extension_opcode
== 0x4))
9505 *mf_cmp_p
= mf_cmp_test_and
;
9506 return !(i
.mem_operands
&& i
.imm_operands
);
9509 /* test without test m imm. */
9510 if ((i
.tm
.base_opcode
| 1) == 0x85
9511 || (i
.tm
.base_opcode
| 1) == 0xa9
9512 || ((i
.tm
.base_opcode
| 1) == 0xf7
9513 && i
.tm
.extension_opcode
== 0))
9515 *mf_cmp_p
= mf_cmp_test_and
;
9516 return !(i
.mem_operands
&& i
.imm_operands
);
9519 /* cmp without cmp m, imm. */
9520 if ((i
.tm
.base_opcode
>= 0x38 && i
.tm
.base_opcode
<= 0x3d)
9521 || ((i
.tm
.base_opcode
| 3) == 0x83
9522 && (i
.tm
.extension_opcode
== 0x7)))
9524 *mf_cmp_p
= mf_cmp_alu_cmp
;
9525 return !(i
.mem_operands
&& i
.imm_operands
);
9528 /* inc, dec without inc/dec m. */
9529 if ((is_cpu (&i
.tm
, CpuNo64
)
9530 && (i
.tm
.base_opcode
| 0xf) == 0x4f)
9531 || ((i
.tm
.base_opcode
| 1) == 0xff
9532 && i
.tm
.extension_opcode
<= 0x1))
9534 *mf_cmp_p
= mf_cmp_incdec
;
9535 return !i
.mem_operands
;
9541 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
9544 add_fused_jcc_padding_frag_p (enum mf_cmp_kind
* mf_cmp_p
)
9546 /* NB: Don't work with COND_JUMP86 without i386. */
9547 if (!align_branch_power
9548 || now_seg
== absolute_section
9549 || !cpu_arch_flags
.bitfield
.cpui386
9550 || !(align_branch
& align_branch_fused_bit
))
9553 if (maybe_fused_with_jcc_p (mf_cmp_p
))
9555 if (last_insn
.kind
== last_insn_other
9556 || last_insn
.seg
!= now_seg
)
9559 as_warn_where (last_insn
.file
, last_insn
.line
,
9560 _("`%s` skips -malign-branch-boundary on `%s`"),
9561 last_insn
.name
, insn_name (&i
.tm
));
9567 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
9570 add_branch_prefix_frag_p (void)
9572 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
9573 to PadLock instructions since they include prefixes in opcode. */
9574 if (!align_branch_power
9575 || !align_branch_prefix_size
9576 || now_seg
== absolute_section
9577 || is_cpu (&i
.tm
, CpuPadLock
)
9578 || !cpu_arch_flags
.bitfield
.cpui386
)
9581 /* Don't add prefix if it is a prefix or there is no operand in case
9582 that segment prefix is special. */
9583 if (!i
.operands
|| i
.tm
.opcode_modifier
.isprefix
)
9586 if (last_insn
.kind
== last_insn_other
9587 || last_insn
.seg
!= now_seg
)
9591 as_warn_where (last_insn
.file
, last_insn
.line
,
9592 _("`%s` skips -malign-branch-boundary on `%s`"),
9593 last_insn
.name
, insn_name (&i
.tm
));
9598 /* Return 1 if a BRANCH_PADDING frag should be generated. */
9601 add_branch_padding_frag_p (enum align_branch_kind
*branch_p
,
9602 enum mf_jcc_kind
*mf_jcc_p
)
9606 /* NB: Don't work with COND_JUMP86 without i386. */
9607 if (!align_branch_power
9608 || now_seg
== absolute_section
9609 || !cpu_arch_flags
.bitfield
.cpui386
9610 || i
.tm
.opcode_space
!= SPACE_BASE
)
9615 /* Check for jcc and direct jmp. */
9616 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9618 if (i
.tm
.base_opcode
== JUMP_PC_RELATIVE
)
9620 *branch_p
= align_branch_jmp
;
9621 add_padding
= align_branch
& align_branch_jmp_bit
;
9625 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
9626 igore the lowest bit. */
9627 *mf_jcc_p
= (i
.tm
.base_opcode
& 0x0e) >> 1;
9628 *branch_p
= align_branch_jcc
;
9629 if ((align_branch
& align_branch_jcc_bit
))
9633 else if ((i
.tm
.base_opcode
| 1) == 0xc3)
9636 *branch_p
= align_branch_ret
;
9637 if ((align_branch
& align_branch_ret_bit
))
9642 /* Check for indirect jmp, direct and indirect calls. */
9643 if (i
.tm
.base_opcode
== 0xe8)
9646 *branch_p
= align_branch_call
;
9647 if ((align_branch
& align_branch_call_bit
))
9650 else if (i
.tm
.base_opcode
== 0xff
9651 && (i
.tm
.extension_opcode
== 2
9652 || i
.tm
.extension_opcode
== 4))
9654 /* Indirect call and jmp. */
9655 *branch_p
= align_branch_indirect
;
9656 if ((align_branch
& align_branch_indirect_bit
))
9663 && (i
.op
[0].disps
->X_op
== O_symbol
9664 || (i
.op
[0].disps
->X_op
== O_subtract
9665 && i
.op
[0].disps
->X_op_symbol
== GOT_symbol
)))
9667 symbolS
*s
= i
.op
[0].disps
->X_add_symbol
;
9668 /* No padding to call to global or undefined tls_get_addr. */
9669 if ((S_IS_EXTERNAL (s
) || !S_IS_DEFINED (s
))
9670 && strcmp (S_GET_NAME (s
), tls_get_addr
) == 0)
9676 && last_insn
.kind
!= last_insn_other
9677 && last_insn
.seg
== now_seg
)
9680 as_warn_where (last_insn
.file
, last_insn
.line
,
9681 _("`%s` skips -malign-branch-boundary on `%s`"),
9682 last_insn
.name
, insn_name (&i
.tm
));
9692 fragS
*insn_start_frag
;
9693 offsetT insn_start_off
;
9694 fragS
*fragP
= NULL
;
9695 enum align_branch_kind branch
= align_branch_none
;
9696 /* The initializer is arbitrary just to avoid uninitialized error.
9697 it's actually either assigned in add_branch_padding_frag_p
9698 or never be used. */
9699 enum mf_jcc_kind mf_jcc
= mf_jcc_jo
;
9701 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9702 if (IS_ELF
&& x86_used_note
&& now_seg
!= absolute_section
)
9704 if ((i
.xstate
& xstate_tmm
) == xstate_tmm
9705 || is_cpu (&i
.tm
, CpuAMX_TILE
))
9706 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_TMM
;
9708 if (is_cpu (&i
.tm
, Cpu8087
)
9709 || is_cpu (&i
.tm
, Cpu287
)
9710 || is_cpu (&i
.tm
, Cpu387
)
9711 || is_cpu (&i
.tm
, Cpu687
)
9712 || is_cpu (&i
.tm
, CpuFISTTP
))
9713 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_X87
;
9715 if ((i
.xstate
& xstate_mmx
)
9716 || i
.tm
.mnem_off
== MN_emms
9717 || i
.tm
.mnem_off
== MN_femms
)
9718 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MMX
;
9722 if (i
.index_reg
->reg_type
.bitfield
.zmmword
)
9723 i
.xstate
|= xstate_zmm
;
9724 else if (i
.index_reg
->reg_type
.bitfield
.ymmword
)
9725 i
.xstate
|= xstate_ymm
;
9726 else if (i
.index_reg
->reg_type
.bitfield
.xmmword
)
9727 i
.xstate
|= xstate_xmm
;
9730 /* vzeroall / vzeroupper */
9731 if (i
.tm
.base_opcode
== 0x77 && is_cpu (&i
.tm
, CpuAVX
))
9732 i
.xstate
|= xstate_ymm
;
9734 if ((i
.xstate
& xstate_xmm
)
9735 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
9736 || (i
.tm
.base_opcode
== 0xae
9737 && (is_cpu (&i
.tm
, CpuSSE
)
9738 || is_cpu (&i
.tm
, CpuAVX
)))
9739 || is_cpu (&i
.tm
, CpuWideKL
)
9740 || is_cpu (&i
.tm
, CpuKL
))
9741 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XMM
;
9743 if ((i
.xstate
& xstate_ymm
) == xstate_ymm
)
9744 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_YMM
;
9745 if ((i
.xstate
& xstate_zmm
) == xstate_zmm
)
9746 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_ZMM
;
9747 if (i
.mask
.reg
|| (i
.xstate
& xstate_mask
) == xstate_mask
)
9748 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_MASK
;
9749 if (is_cpu (&i
.tm
, CpuFXSR
))
9750 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_FXSR
;
9751 if (is_cpu (&i
.tm
, CpuXsave
))
9752 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVE
;
9753 if (is_cpu (&i
.tm
, CpuXsaveopt
))
9754 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
;
9755 if (is_cpu (&i
.tm
, CpuXSAVEC
))
9756 x86_feature_2_used
|= GNU_PROPERTY_X86_FEATURE_2_XSAVEC
;
9758 if (x86_feature_2_used
9759 || is_cpu (&i
.tm
, CpuCMOV
)
9760 || is_cpu (&i
.tm
, CpuSYSCALL
)
9761 || i
.tm
.mnem_off
== MN_cmpxchg8b
)
9762 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_BASELINE
;
9763 if (is_cpu (&i
.tm
, CpuSSE3
)
9764 || is_cpu (&i
.tm
, CpuSSSE3
)
9765 || is_cpu (&i
.tm
, CpuSSE4_1
)
9766 || is_cpu (&i
.tm
, CpuSSE4_2
)
9767 || is_cpu (&i
.tm
, CpuCX16
)
9768 || is_cpu (&i
.tm
, CpuPOPCNT
)
9769 /* LAHF-SAHF insns in 64-bit mode. */
9770 || (flag_code
== CODE_64BIT
9771 && (i
.tm
.base_opcode
| 1) == 0x9f
9772 && i
.tm
.opcode_space
== SPACE_BASE
))
9773 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V2
;
9774 if (is_cpu (&i
.tm
, CpuAVX
)
9775 || is_cpu (&i
.tm
, CpuAVX2
)
9776 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
9777 XOP, FMA4, LPW, TBM, and AMX. */
9778 || (i
.tm
.opcode_modifier
.vex
9779 && !is_cpu (&i
.tm
, CpuAVX512F
)
9780 && !is_cpu (&i
.tm
, CpuAVX512BW
)
9781 && !is_cpu (&i
.tm
, CpuAVX512DQ
)
9782 && !is_cpu (&i
.tm
, CpuXOP
)
9783 && !is_cpu (&i
.tm
, CpuFMA4
)
9784 && !is_cpu (&i
.tm
, CpuLWP
)
9785 && !is_cpu (&i
.tm
, CpuTBM
)
9786 && !(x86_feature_2_used
& GNU_PROPERTY_X86_FEATURE_2_TMM
))
9787 || is_cpu (&i
.tm
, CpuF16C
)
9788 || is_cpu (&i
.tm
, CpuFMA
)
9789 || is_cpu (&i
.tm
, CpuLZCNT
)
9790 || is_cpu (&i
.tm
, CpuMovbe
)
9791 || is_cpu (&i
.tm
, CpuXSAVES
)
9792 || (x86_feature_2_used
9793 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
9794 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
9795 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC
)) != 0)
9796 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V3
;
9797 if (is_cpu (&i
.tm
, CpuAVX512F
)
9798 || is_cpu (&i
.tm
, CpuAVX512BW
)
9799 || is_cpu (&i
.tm
, CpuAVX512DQ
)
9800 || is_cpu (&i
.tm
, CpuAVX512VL
)
9801 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
9802 AVX512-4FMAPS, and AVX512-4VNNIW. */
9803 || (i
.tm
.opcode_modifier
.evex
9804 && !is_cpu (&i
.tm
, CpuAVX512ER
)
9805 && !is_cpu (&i
.tm
, CpuAVX512PF
)
9806 && !is_cpu (&i
.tm
, CpuAVX512_4FMAPS
)
9807 && !is_cpu (&i
.tm
, CpuAVX512_4VNNIW
)))
9808 x86_isa_1_used
|= GNU_PROPERTY_X86_ISA_1_V4
;
9812 /* Tie dwarf2 debug info to the address at the start of the insn.
9813 We can't do this after the insn has been output as the current
9814 frag may have been closed off. eg. by frag_var. */
9815 dwarf2_emit_insn (0);
9817 insn_start_frag
= frag_now
;
9818 insn_start_off
= frag_now_fix ();
9820 if (add_branch_padding_frag_p (&branch
, &mf_jcc
))
9823 /* Branch can be 8 bytes. Leave some room for prefixes. */
9824 unsigned int max_branch_padding_size
= 14;
9826 /* Align section to boundary. */
9827 record_alignment (now_seg
, align_branch_power
);
9829 /* Make room for padding. */
9830 frag_grow (max_branch_padding_size
);
9832 /* Start of the padding. */
9837 frag_var (rs_machine_dependent
, max_branch_padding_size
, 0,
9838 ENCODE_RELAX_STATE (BRANCH_PADDING
, 0),
9841 fragP
->tc_frag_data
.mf_type
= mf_jcc
;
9842 fragP
->tc_frag_data
.branch_type
= branch
;
9843 fragP
->tc_frag_data
.max_bytes
= max_branch_padding_size
;
9846 if (!cpu_arch_flags
.bitfield
.cpui386
&& (flag_code
!= CODE_16BIT
)
9847 && !pre_386_16bit_warned
)
9849 as_warn (_("use .code16 to ensure correct addressing mode"));
9850 pre_386_16bit_warned
= true;
9854 if (i
.tm
.opcode_modifier
.jump
== JUMP
)
9856 else if (i
.tm
.opcode_modifier
.jump
== JUMP_BYTE
9857 || i
.tm
.opcode_modifier
.jump
== JUMP_DWORD
)
9859 else if (i
.tm
.opcode_modifier
.jump
== JUMP_INTERSEGMENT
)
9860 output_interseg_jump ();
9863 /* Output normal instructions here. */
9867 enum mf_cmp_kind mf_cmp
;
9870 && (i
.tm
.base_opcode
== 0xaee8
9871 || i
.tm
.base_opcode
== 0xaef0
9872 || i
.tm
.base_opcode
== 0xaef8))
9874 /* Encode lfence, mfence, and sfence as
9875 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
9876 if (flag_code
== CODE_16BIT
)
9877 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i
.tm
));
9878 else if (omit_lock_prefix
)
9879 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
9881 else if (now_seg
!= absolute_section
)
9883 offsetT val
= 0x240483f0ULL
;
9886 md_number_to_chars (p
, val
, 5);
9889 abs_section_offset
+= 5;
9893 /* Some processors fail on LOCK prefix. This options makes
9894 assembler ignore LOCK prefix and serves as a workaround. */
9895 if (omit_lock_prefix
)
9897 if (i
.tm
.base_opcode
== LOCK_PREFIX_OPCODE
9898 && i
.tm
.opcode_modifier
.isprefix
)
9900 i
.prefix
[LOCK_PREFIX
] = 0;
9904 /* Skip if this is a branch. */
9906 else if (add_fused_jcc_padding_frag_p (&mf_cmp
))
9908 /* Make room for padding. */
9909 frag_grow (MAX_FUSED_JCC_PADDING_SIZE
);
9914 frag_var (rs_machine_dependent
, MAX_FUSED_JCC_PADDING_SIZE
, 0,
9915 ENCODE_RELAX_STATE (FUSED_JCC_PADDING
, 0),
9918 fragP
->tc_frag_data
.mf_type
= mf_cmp
;
9919 fragP
->tc_frag_data
.branch_type
= align_branch_fused
;
9920 fragP
->tc_frag_data
.max_bytes
= MAX_FUSED_JCC_PADDING_SIZE
;
9922 else if (add_branch_prefix_frag_p ())
9924 unsigned int max_prefix_size
= align_branch_prefix_size
;
9926 /* Make room for padding. */
9927 frag_grow (max_prefix_size
);
9932 frag_var (rs_machine_dependent
, max_prefix_size
, 0,
9933 ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0),
9936 fragP
->tc_frag_data
.max_bytes
= max_prefix_size
;
9939 /* Since the VEX/EVEX prefix contains the implicit prefix, we
9940 don't need the explicit prefix. */
9941 if (!is_any_vex_encoding (&i
.tm
))
9943 switch (i
.tm
.opcode_modifier
.opcodeprefix
)
9952 if (!is_cpu (&i
.tm
, CpuPadLock
)
9953 || (i
.prefix
[REP_PREFIX
] != 0xf3))
9957 switch (i
.opcode_length
)
9962 /* Check for pseudo prefixes. */
9963 if (!i
.tm
.opcode_modifier
.isprefix
|| i
.tm
.base_opcode
)
9965 as_bad_where (insn_start_frag
->fr_file
,
9966 insn_start_frag
->fr_line
,
9967 _("pseudo prefix without instruction"));
9977 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9978 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
9979 R_X86_64_GOTTPOFF relocation so that linker can safely
9980 perform IE->LE optimization. A dummy REX_OPCODE prefix
9981 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
9982 relocation for GDesc -> IE/LE optimization. */
9983 if (x86_elf_abi
== X86_64_X32_ABI
9985 && (i
.reloc
[0] == BFD_RELOC_X86_64_GOTTPOFF
9986 || i
.reloc
[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC
)
9987 && i
.prefix
[REX_PREFIX
] == 0)
9988 add_prefix (REX_OPCODE
);
9991 /* The prefix bytes. */
9992 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
9994 frag_opcode_byte (*q
);
9998 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
10004 frag_opcode_byte (*q
);
10007 /* There should be no other prefixes for instructions
10008 with VEX prefix. */
10012 /* For EVEX instructions i.vrex should become 0 after
10013 build_evex_prefix. For VEX instructions upper 16 registers
10014 aren't available, so VREX should be 0. */
10017 /* Now the VEX prefix. */
10018 if (now_seg
!= absolute_section
)
10020 p
= frag_more (i
.vex
.length
);
10021 for (j
= 0; j
< i
.vex
.length
; j
++)
10022 p
[j
] = i
.vex
.bytes
[j
];
10025 abs_section_offset
+= i
.vex
.length
;
10028 /* Now the opcode; be careful about word order here! */
10029 j
= i
.opcode_length
;
10031 switch (i
.tm
.opcode_space
)
10046 if (now_seg
== absolute_section
)
10047 abs_section_offset
+= j
;
10050 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
10056 && i
.tm
.opcode_space
!= SPACE_BASE
)
10059 if (i
.tm
.opcode_space
!= SPACE_0F
)
10060 *p
++ = i
.tm
.opcode_space
== SPACE_0F38
10064 switch (i
.opcode_length
)
10067 /* Put out high byte first: can't use md_number_to_chars! */
10068 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
10069 /* Fall through. */
10071 *p
= i
.tm
.base_opcode
& 0xff;
10080 /* Now the modrm byte and sib byte (if present). */
10081 if (i
.tm
.opcode_modifier
.modrm
)
10083 frag_opcode_byte ((i
.rm
.regmem
<< 0)
10085 | (i
.rm
.mode
<< 6));
10086 /* If i.rm.regmem == ESP (4)
10087 && i.rm.mode != (Register mode)
10089 ==> need second modrm byte. */
10090 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
10092 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.word
))
10093 frag_opcode_byte ((i
.sib
.base
<< 0)
10094 | (i
.sib
.index
<< 3)
10095 | (i
.sib
.scale
<< 6));
10098 if (i
.disp_operands
)
10099 output_disp (insn_start_frag
, insn_start_off
);
10101 if (i
.imm_operands
)
10102 output_imm (insn_start_frag
, insn_start_off
);
10105 * frag_now_fix () returning plain abs_section_offset when we're in the
10106 * absolute section, and abs_section_offset not getting updated as data
10107 * gets added to the frag breaks the logic below.
10109 if (now_seg
!= absolute_section
)
10111 j
= encoding_length (insn_start_frag
, insn_start_off
, frag_more (0));
10113 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
10117 /* NB: Don't add prefix with GOTPC relocation since
10118 output_disp() above depends on the fixed encoding
10119 length. Can't add prefix with TLS relocation since
10120 it breaks TLS linker optimization. */
10121 unsigned int max
= i
.has_gotpc_tls_reloc
? 0 : 15 - j
;
10122 /* Prefix count on the current instruction. */
10123 unsigned int count
= i
.vex
.length
;
10125 for (k
= 0; k
< ARRAY_SIZE (i
.prefix
); k
++)
10126 /* REX byte is encoded in VEX/EVEX prefix. */
10127 if (i
.prefix
[k
] && (k
!= REX_PREFIX
|| !i
.vex
.length
))
10130 /* Count prefixes for extended opcode maps. */
10132 switch (i
.tm
.opcode_space
)
10147 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
10150 /* Set the maximum prefix size in BRANCH_PREFIX
10152 if (fragP
->tc_frag_data
.max_bytes
> max
)
10153 fragP
->tc_frag_data
.max_bytes
= max
;
10154 if (fragP
->tc_frag_data
.max_bytes
> count
)
10155 fragP
->tc_frag_data
.max_bytes
-= count
;
10157 fragP
->tc_frag_data
.max_bytes
= 0;
10161 /* Remember the maximum prefix size in FUSED_JCC_PADDING
10163 unsigned int max_prefix_size
;
10164 if (align_branch_prefix_size
> max
)
10165 max_prefix_size
= max
;
10167 max_prefix_size
= align_branch_prefix_size
;
10168 if (max_prefix_size
> count
)
10169 fragP
->tc_frag_data
.max_prefix_length
10170 = max_prefix_size
- count
;
10173 /* Use existing segment prefix if possible. Use CS
10174 segment prefix in 64-bit mode. In 32-bit mode, use SS
10175 segment prefix with ESP/EBP base register and use DS
10176 segment prefix without ESP/EBP base register. */
10177 if (i
.prefix
[SEG_PREFIX
])
10178 fragP
->tc_frag_data
.default_prefix
= i
.prefix
[SEG_PREFIX
];
10179 else if (flag_code
== CODE_64BIT
)
10180 fragP
->tc_frag_data
.default_prefix
= CS_PREFIX_OPCODE
;
10181 else if (i
.base_reg
10182 && (i
.base_reg
->reg_num
== 4
10183 || i
.base_reg
->reg_num
== 5))
10184 fragP
->tc_frag_data
.default_prefix
= SS_PREFIX_OPCODE
;
10186 fragP
->tc_frag_data
.default_prefix
= DS_PREFIX_OPCODE
;
10191 /* NB: Don't work with COND_JUMP86 without i386. */
10192 if (align_branch_power
10193 && now_seg
!= absolute_section
10194 && cpu_arch_flags
.bitfield
.cpui386
)
10196 /* Terminate each frag so that we can add prefix and check for
10198 frag_wane (frag_now
);
10205 pi ("" /*line*/, &i
);
10207 #endif /* DEBUG386 */
10210 /* Return the size of the displacement operand N. */
10213 disp_size (unsigned int n
)
10217 if (i
.types
[n
].bitfield
.disp64
)
10219 else if (i
.types
[n
].bitfield
.disp8
)
10221 else if (i
.types
[n
].bitfield
.disp16
)
10226 /* Return the size of the immediate operand N. */
10229 imm_size (unsigned int n
)
10232 if (i
.types
[n
].bitfield
.imm64
)
10234 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
10236 else if (i
.types
[n
].bitfield
.imm16
)
10242 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
10247 for (n
= 0; n
< i
.operands
; n
++)
10249 if (operand_type_check (i
.types
[n
], disp
))
10251 int size
= disp_size (n
);
10253 if (now_seg
== absolute_section
)
10254 abs_section_offset
+= size
;
10255 else if (i
.op
[n
].disps
->X_op
== O_constant
)
10257 offsetT val
= i
.op
[n
].disps
->X_add_number
;
10259 val
= offset_in_range (val
>> (size
== 1 ? i
.memshift
: 0),
10261 p
= frag_more (size
);
10262 md_number_to_chars (p
, val
, size
);
10266 enum bfd_reloc_code_real reloc_type
;
10267 bool pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
10268 bool sign
= (flag_code
== CODE_64BIT
&& size
== 4
10269 && (!want_disp32 (&i
.tm
)
10270 || (i
.tm
.opcode_modifier
.jump
&& !i
.jumpabsolute
10271 && !i
.types
[n
].bitfield
.baseindex
)))
10275 /* We can't have 8 bit displacement here. */
10276 gas_assert (!i
.types
[n
].bitfield
.disp8
);
10278 /* The PC relative address is computed relative
10279 to the instruction boundary, so in case immediate
10280 fields follows, we need to adjust the value. */
10281 if (pcrel
&& i
.imm_operands
)
10286 for (n1
= 0; n1
< i
.operands
; n1
++)
10287 if (operand_type_check (i
.types
[n1
], imm
))
10289 /* Only one immediate is allowed for PC
10290 relative address, except with .insn. */
10291 gas_assert (sz
== 0 || dot_insn ());
10292 sz
+= imm_size (n1
);
10294 /* We should find at least one immediate. */
10295 gas_assert (sz
!= 0);
10296 i
.op
[n
].disps
->X_add_number
-= sz
;
10299 p
= frag_more (size
);
10300 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
10302 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
10303 && (((reloc_type
== BFD_RELOC_32
10304 || reloc_type
== BFD_RELOC_X86_64_32S
10305 || (reloc_type
== BFD_RELOC_64
10307 && (i
.op
[n
].disps
->X_op
== O_symbol
10308 || (i
.op
[n
].disps
->X_op
== O_add
10309 && ((symbol_get_value_expression
10310 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
10312 || reloc_type
== BFD_RELOC_32_PCREL
))
10316 reloc_type
= BFD_RELOC_386_GOTPC
;
10317 i
.has_gotpc_tls_reloc
= true;
10318 i
.op
[n
].disps
->X_add_number
+=
10319 encoding_length (insn_start_frag
, insn_start_off
, p
);
10321 else if (reloc_type
== BFD_RELOC_64
)
10322 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10324 /* Don't do the adjustment for x86-64, as there
10325 the pcrel addressing is relative to the _next_
10326 insn, and that is taken care of in other code. */
10327 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10329 else if (align_branch_power
)
10331 switch (reloc_type
)
10333 case BFD_RELOC_386_TLS_GD
:
10334 case BFD_RELOC_386_TLS_LDM
:
10335 case BFD_RELOC_386_TLS_IE
:
10336 case BFD_RELOC_386_TLS_IE_32
:
10337 case BFD_RELOC_386_TLS_GOTIE
:
10338 case BFD_RELOC_386_TLS_GOTDESC
:
10339 case BFD_RELOC_386_TLS_DESC_CALL
:
10340 case BFD_RELOC_X86_64_TLSGD
:
10341 case BFD_RELOC_X86_64_TLSLD
:
10342 case BFD_RELOC_X86_64_GOTTPOFF
:
10343 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
10344 case BFD_RELOC_X86_64_TLSDESC_CALL
:
10345 i
.has_gotpc_tls_reloc
= true;
10350 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
,
10351 size
, i
.op
[n
].disps
, pcrel
,
10354 if (flag_code
== CODE_64BIT
&& size
== 4 && pcrel
10355 && !i
.prefix
[ADDR_PREFIX
])
10356 fixP
->fx_signed
= 1;
10358 /* Check for "call/jmp *mem", "mov mem, %reg",
10359 "test %reg, mem" and "binop mem, %reg" where binop
10360 is one of adc, add, and, cmp, or, sbb, sub, xor
10361 instructions without data prefix. Always generate
10362 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
10363 if (i
.prefix
[DATA_PREFIX
] == 0
10364 && (generate_relax_relocations
10367 && i
.rm
.regmem
== 5))
10369 || (i
.rm
.mode
== 0 && i
.rm
.regmem
== 5))
10370 && i
.tm
.opcode_space
== SPACE_BASE
10371 && ((i
.operands
== 1
10372 && i
.tm
.base_opcode
== 0xff
10373 && (i
.rm
.reg
== 2 || i
.rm
.reg
== 4))
10374 || (i
.operands
== 2
10375 && (i
.tm
.base_opcode
== 0x8b
10376 || i
.tm
.base_opcode
== 0x85
10377 || (i
.tm
.base_opcode
& ~0x38) == 0x03))))
10381 fixP
->fx_tcbit
= i
.rex
!= 0;
10383 && (i
.base_reg
->reg_num
== RegIP
))
10384 fixP
->fx_tcbit2
= 1;
10387 fixP
->fx_tcbit2
= 1;
10395 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
10400 for (n
= 0; n
< i
.operands
; n
++)
10402 if (operand_type_check (i
.types
[n
], imm
))
10404 int size
= imm_size (n
);
10406 if (now_seg
== absolute_section
)
10407 abs_section_offset
+= size
;
10408 else if (i
.op
[n
].imms
->X_op
== O_constant
)
10412 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
10414 p
= frag_more (size
);
10415 md_number_to_chars (p
, val
, size
);
10419 /* Not absolute_section.
10420 Need a 32-bit fixup (don't support 8bit
10421 non-absolute imms). Try to support other
10423 enum bfd_reloc_code_real reloc_type
;
10426 if (i
.types
[n
].bitfield
.imm32s
10427 && (i
.suffix
== QWORD_MNEM_SUFFIX
10428 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)
10434 p
= frag_more (size
);
10435 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
10437 /* This is tough to explain. We end up with this one if we
10438 * have operands that look like
10439 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
10440 * obtain the absolute address of the GOT, and it is strongly
10441 * preferable from a performance point of view to avoid using
10442 * a runtime relocation for this. The actual sequence of
10443 * instructions often look something like:
10448 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
10450 * The call and pop essentially return the absolute address
10451 * of the label .L66 and store it in %ebx. The linker itself
10452 * will ultimately change the first operand of the addl so
10453 * that %ebx points to the GOT, but to keep things simple, the
10454 * .o file must have this operand set so that it generates not
10455 * the absolute address of .L66, but the absolute address of
10456 * itself. This allows the linker itself simply treat a GOTPC
10457 * relocation as asking for a pcrel offset to the GOT to be
10458 * added in, and the addend of the relocation is stored in the
10459 * operand field for the instruction itself.
10461 * Our job here is to fix the operand so that it would add
10462 * the correct offset so that %ebx would point to itself. The
10463 * thing that is tricky is that .-.L66 will point to the
10464 * beginning of the instruction, so we need to further modify
10465 * the operand so that it will point to itself. There are
10466 * other cases where you have something like:
10468 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
10470 * and here no correction would be required. Internally in
10471 * the assembler we treat operands of this form as not being
10472 * pcrel since the '.' is explicitly mentioned, and I wonder
10473 * whether it would simplify matters to do it this way. Who
10474 * knows. In earlier versions of the PIC patches, the
10475 * pcrel_adjust field was used to store the correction, but
10476 * since the expression is not pcrel, I felt it would be
10477 * confusing to do it this way. */
10479 if ((reloc_type
== BFD_RELOC_32
10480 || reloc_type
== BFD_RELOC_X86_64_32S
10481 || reloc_type
== BFD_RELOC_64
)
10483 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
10484 && (i
.op
[n
].imms
->X_op
== O_symbol
10485 || (i
.op
[n
].imms
->X_op
== O_add
10486 && ((symbol_get_value_expression
10487 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
10491 reloc_type
= BFD_RELOC_386_GOTPC
;
10492 else if (size
== 4)
10493 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
10494 else if (size
== 8)
10495 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
10496 i
.has_gotpc_tls_reloc
= true;
10497 i
.op
[n
].imms
->X_add_number
+=
10498 encoding_length (insn_start_frag
, insn_start_off
, p
);
10500 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
10501 i
.op
[n
].imms
, 0, reloc_type
);
10507 /* x86_cons_fix_new is called via the expression parsing code when a
10508 reloc is needed. We use this hook to get the correct .got reloc. */
10509 static int cons_sign
= -1;
10512 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
10513 expressionS
*exp
, bfd_reloc_code_real_type r
)
10515 r
= reloc (len
, 0, cons_sign
, r
);
10518 if (exp
->X_op
== O_secrel
)
10520 exp
->X_op
= O_symbol
;
10521 r
= BFD_RELOC_32_SECREL
;
10523 else if (exp
->X_op
== O_secidx
)
10524 r
= BFD_RELOC_16_SECIDX
;
10527 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
10530 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
10531 purpose of the `.dc.a' internal pseudo-op. */
10534 x86_address_bytes (void)
10536 if ((stdoutput
->arch_info
->mach
& bfd_mach_x64_32
))
10538 return stdoutput
->arch_info
->bits_per_address
/ 8;
10541 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
10542 || defined (LEX_AT)) && !defined (TE_PE)
10543 # define lex_got(reloc, adjust, types) NULL
10545 /* Parse operands of the form
10546 <symbol>@GOTOFF+<nnn>
10547 and similar .plt or .got references.
10549 If we find one, set up the correct relocation in RELOC and copy the
10550 input string, minus the `@GOTOFF' into a malloc'd buffer for
10551 parsing by the calling routine. Return this buffer, and if ADJUST
10552 is non-null set it to the length of the string we removed from the
10553 input line. Otherwise return NULL. */
10555 lex_got (enum bfd_reloc_code_real
*rel
,
10557 i386_operand_type
*types
)
10559 /* Some of the relocations depend on the size of what field is to
10560 be relocated. But in our callers i386_immediate and i386_displacement
10561 we don't yet know the operand size (this will be set by insn
10562 matching). Hence we record the word32 relocation here,
10563 and adjust the reloc according to the real size in reloc(). */
10564 static const struct
10568 const enum bfd_reloc_code_real rel
[2];
10569 const i386_operand_type types64
;
10570 bool need_GOT_symbol
;
10575 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
10576 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
10577 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
10578 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
10579 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
10580 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
10581 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
10582 { .imm64 = 1, .disp64 = 1 } }
10585 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10586 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32
,
10587 BFD_RELOC_SIZE32
},
10588 { .bitfield
= { .imm32
= 1, .imm64
= 1 } }, false },
10590 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
10591 BFD_RELOC_X86_64_PLTOFF64
},
10592 { .bitfield
= { .imm64
= 1 } }, true },
10593 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
10594 BFD_RELOC_X86_64_PLT32
},
10595 OPERAND_TYPE_IMM32_32S_DISP32
, false },
10596 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
10597 BFD_RELOC_X86_64_GOTPLT64
},
10598 OPERAND_TYPE_IMM64_DISP64
, true },
10599 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
10600 BFD_RELOC_X86_64_GOTOFF64
},
10601 OPERAND_TYPE_IMM64_DISP64
, true },
10602 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
10603 BFD_RELOC_X86_64_GOTPCREL
},
10604 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10605 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
10606 BFD_RELOC_X86_64_TLSGD
},
10607 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10608 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
10609 _dummy_first_bfd_reloc_code_real
},
10610 OPERAND_TYPE_NONE
, true },
10611 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
10612 BFD_RELOC_X86_64_TLSLD
},
10613 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10614 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
10615 BFD_RELOC_X86_64_GOTTPOFF
},
10616 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10617 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
10618 BFD_RELOC_X86_64_TPOFF32
},
10619 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10620 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
10621 _dummy_first_bfd_reloc_code_real
},
10622 OPERAND_TYPE_NONE
, true },
10623 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
10624 BFD_RELOC_X86_64_DTPOFF32
},
10625 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, true },
10626 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
10627 _dummy_first_bfd_reloc_code_real
},
10628 OPERAND_TYPE_NONE
, true },
10629 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
10630 _dummy_first_bfd_reloc_code_real
},
10631 OPERAND_TYPE_NONE
, true },
10632 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
10633 BFD_RELOC_X86_64_GOT32
},
10634 OPERAND_TYPE_IMM32_32S_64_DISP32
, true },
10635 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
10636 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
10637 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10638 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
10639 BFD_RELOC_X86_64_TLSDESC_CALL
},
10640 OPERAND_TYPE_IMM32_32S_DISP32
, true },
10642 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL
,
10643 BFD_RELOC_32_SECREL
},
10644 OPERAND_TYPE_IMM32_32S_64_DISP32_64
, false },
10647 #undef OPERAND_TYPE_IMM32_32S_DISP32
10648 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
10649 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
10650 #undef OPERAND_TYPE_IMM64_DISP64
10656 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
10661 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
10662 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
10665 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
10667 int len
= gotrel
[j
].len
;
10668 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
10670 if (gotrel
[j
].rel
[object_64bit
] != 0)
10673 char *tmpbuf
, *past_reloc
;
10675 *rel
= gotrel
[j
].rel
[object_64bit
];
10679 if (flag_code
!= CODE_64BIT
)
10681 types
->bitfield
.imm32
= 1;
10682 types
->bitfield
.disp32
= 1;
10685 *types
= gotrel
[j
].types64
;
10688 if (gotrel
[j
].need_GOT_symbol
&& GOT_symbol
== NULL
)
10689 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
10691 /* The length of the first part of our input line. */
10692 first
= cp
- input_line_pointer
;
10694 /* The second part goes from after the reloc token until
10695 (and including) an end_of_line char or comma. */
10696 past_reloc
= cp
+ 1 + len
;
10698 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
10700 second
= cp
+ 1 - past_reloc
;
10702 /* Allocate and copy string. The trailing NUL shouldn't
10703 be necessary, but be safe. */
10704 tmpbuf
= XNEWVEC (char, first
+ second
+ 2);
10705 memcpy (tmpbuf
, input_line_pointer
, first
);
10706 if (second
!= 0 && *past_reloc
!= ' ')
10707 /* Replace the relocation token with ' ', so that
10708 errors like foo@GOTOFF1 will be detected. */
10709 tmpbuf
[first
++] = ' ';
10711 /* Increment length by 1 if the relocation token is
10716 memcpy (tmpbuf
+ first
, past_reloc
, second
);
10717 tmpbuf
[first
+ second
] = '\0';
10721 as_bad (_("@%s reloc is not supported with %d-bit output format"),
10722 gotrel
[j
].str
, 1 << (5 + object_64bit
));
10727 /* Might be a symbol version string. Don't as_bad here. */
10732 bfd_reloc_code_real_type
10733 x86_cons (expressionS
*exp
, int size
)
10735 bfd_reloc_code_real_type got_reloc
= NO_RELOC
;
10737 intel_syntax
= -intel_syntax
;
10739 expr_mode
= expr_operator_none
;
10741 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
10742 && !defined (LEX_AT)) \
10744 if (size
== 4 || (object_64bit
&& size
== 8))
10746 /* Handle @GOTOFF and the like in an expression. */
10748 char *gotfree_input_line
;
10751 save
= input_line_pointer
;
10752 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
10753 if (gotfree_input_line
)
10754 input_line_pointer
= gotfree_input_line
;
10758 if (gotfree_input_line
)
10760 /* expression () has merrily parsed up to the end of line,
10761 or a comma - in the wrong buffer. Transfer how far
10762 input_line_pointer has moved to the right buffer. */
10763 input_line_pointer
= (save
10764 + (input_line_pointer
- gotfree_input_line
)
10766 free (gotfree_input_line
);
10767 if (exp
->X_op
== O_constant
10768 || exp
->X_op
== O_absent
10769 || exp
->X_op
== O_illegal
10770 || exp
->X_op
== O_register
10771 || exp
->X_op
== O_big
)
10773 char c
= *input_line_pointer
;
10774 *input_line_pointer
= 0;
10775 as_bad (_("missing or invalid expression `%s'"), save
);
10776 *input_line_pointer
= c
;
10778 else if ((got_reloc
== BFD_RELOC_386_PLT32
10779 || got_reloc
== BFD_RELOC_X86_64_PLT32
)
10780 && exp
->X_op
!= O_symbol
)
10782 char c
= *input_line_pointer
;
10783 *input_line_pointer
= 0;
10784 as_bad (_("invalid PLT expression `%s'"), save
);
10785 *input_line_pointer
= c
;
10793 intel_syntax
= -intel_syntax
;
10796 i386_intel_simplify (exp
);
10798 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
10799 if (size
<= 4 && expr_mode
== expr_operator_present
10800 && exp
->X_op
== O_constant
&& !object_64bit
)
10801 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
10807 signed_cons (int size
)
10816 s_insn (int dummy ATTRIBUTE_UNUSED
)
10818 char mnemonic
[MAX_MNEM_SIZE
], *line
= input_line_pointer
, *ptr
;
10819 char *saved_ilp
= find_end_of_line (line
, false), saved_char
;
10823 bool vex
= false, xop
= false, evex
= false;
10824 static const templates tt
= { &i
.tm
, &i
.tm
+ 1 };
10828 saved_char
= *saved_ilp
;
10831 end
= parse_insn (line
, mnemonic
, true);
10835 *saved_ilp
= saved_char
;
10836 ignore_rest_of_line ();
10840 line
+= end
- line
;
10842 current_templates
= &tt
;
10843 i
.tm
.mnem_off
= MN__insn
;
10844 i
.tm
.extension_opcode
= None
;
10846 if (startswith (line
, "VEX")
10847 && (line
[3] == '.' || is_space_char (line
[3])))
10852 else if (startswith (line
, "XOP") && ISDIGIT (line
[3]))
10855 unsigned long n
= strtoul (line
+ 3, &e
, 16);
10857 if (e
== line
+ 5 && n
>= 0x08 && n
<= 0x1f
10858 && (*e
== '.' || is_space_char (*e
)))
10861 /* Arrange for build_vex_prefix() to emit 0x8f. */
10862 i
.tm
.opcode_space
= SPACE_XOP08
;
10863 i
.insn_opcode_space
= n
;
10867 else if (startswith (line
, "EVEX")
10868 && (line
[4] == '.' || is_space_char (line
[4])))
10875 ? i
.vec_encoding
== vex_encoding_evex
10877 ? i
.vec_encoding
== vex_encoding_vex
10878 || i
.vec_encoding
== vex_encoding_vex3
10879 : i
.vec_encoding
!= vex_encoding_default
)
10881 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
10885 if (line
> end
&& i
.vec_encoding
== vex_encoding_default
)
10886 i
.vec_encoding
= evex
? vex_encoding_evex
: vex_encoding_vex
;
10888 if (i
.vec_encoding
!= vex_encoding_default
)
10890 /* Only address size and segment override prefixes are permitted with
10891 VEX/XOP/EVEX encodings. */
10892 const unsigned char *p
= i
.prefix
;
10894 for (j
= 0; j
< ARRAY_SIZE (i
.prefix
); ++j
, ++p
)
10905 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
10911 if (line
> end
&& *line
== '.')
10913 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
10921 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10923 i
.tm
.opcode_modifier
.vex
= VEX128
;
10928 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10930 i
.tm
.opcode_modifier
.vex
= VEX256
;
10935 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10940 i
.tm
.opcode_modifier
.evex
= EVEX_L3
;
10944 if (line
[3] == 'G')
10947 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
10949 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
10955 if (i
.tm
.opcode_modifier
.vex
|| i
.tm
.opcode_modifier
.evex
)
10960 if (line
[2] == '2' && line
[3] == '8')
10963 i
.tm
.opcode_modifier
.evex
= EVEX128
;
10965 i
.tm
.opcode_modifier
.vex
= VEX128
;
10971 if (line
[2] == '5' && line
[3] == '6')
10974 i
.tm
.opcode_modifier
.evex
= EVEX256
;
10976 i
.tm
.opcode_modifier
.vex
= VEX256
;
10982 if (evex
&& line
[2] == '1' && line
[3] == '2')
10984 i
.tm
.opcode_modifier
.evex
= EVEX512
;
10991 if (line
> end
&& *line
== '.')
10993 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
10997 if (line
[2] == 'P')
11002 if (line
[2] == '6')
11004 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0X66
;
11009 case 'F': case 'f':
11010 if (line
[2] == '3')
11012 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF3
;
11015 else if (line
[2] == '2')
11017 i
.tm
.opcode_modifier
.opcodeprefix
= PREFIX_0XF2
;
11024 if (line
> end
&& !xop
&& *line
== '.')
11026 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
11030 if (TOUPPER (line
[2]) != 'F')
11032 if (line
[3] == '.' || is_space_char (line
[3]))
11034 i
.insn_opcode_space
= SPACE_0F
;
11037 else if (line
[3] == '3'
11038 && (line
[4] == '8' || TOUPPER (line
[4]) == 'A')
11039 && (line
[5] == '.' || is_space_char (line
[5])))
11041 i
.insn_opcode_space
= line
[4] == '8' ? SPACE_0F38
: SPACE_0F3A
;
11047 if (ISDIGIT (line
[2]) && line
[2] != '0')
11050 unsigned long n
= strtoul (line
+ 2, &e
, 10);
11052 if (n
<= (evex
? 15 : 31)
11053 && (*e
== '.' || is_space_char (*e
)))
11055 i
.insn_opcode_space
= n
;
11063 if (line
> end
&& *line
== '.' && line
[1] == 'W')
11065 /* VEX.W, XOP.W, EVEX.W */
11069 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11073 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11077 if (line
[3] == 'G')
11079 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11085 if (i
.tm
.opcode_modifier
.vexw
)
11089 if (line
> end
&& *line
&& !is_space_char (*line
))
11091 /* Improve diagnostic a little. */
11092 if (*line
== '.' && line
[1] && !is_space_char (line
[1]))
11097 /* Before processing the opcode expression, find trailing "+r" or
11098 "/<digit>" specifiers. */
11099 for (ptr
= line
; ; ++ptr
)
11104 ptr
= strpbrk (ptr
, "+/,");
11105 if (ptr
== NULL
|| *ptr
== ',')
11108 if (*ptr
== '+' && ptr
[1] == 'r'
11109 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11113 i
.short_form
= true;
11117 if (*ptr
== '/' && ISDIGIT (ptr
[1])
11118 && (n
= strtoul (ptr
+ 1, &e
, 8)) < 8
11120 && (ptr
[2] == ',' || (is_space_char (ptr
[2]) && ptr
[3] == ',')))
11124 i
.tm
.extension_opcode
= n
;
11125 i
.tm
.opcode_modifier
.modrm
= 1;
11130 input_line_pointer
= line
;
11131 val
= get_absolute_expression ();
11132 line
= input_line_pointer
;
11134 if (i
.short_form
&& (val
& 7))
11135 as_warn ("`+r' assumes low three opcode bits to be clear");
11137 for (j
= 1; j
< sizeof(val
); ++j
)
11138 if (!(val
>> (j
* 8)))
11141 /* Trim off a prefix if present. */
11142 if (j
> 1 && !vex
&& !xop
&& !evex
)
11144 uint8_t byte
= val
>> ((j
- 1) * 8);
11148 case DATA_PREFIX_OPCODE
:
11149 case REPE_PREFIX_OPCODE
:
11150 case REPNE_PREFIX_OPCODE
:
11151 if (!add_prefix (byte
))
11153 val
&= ((uint64_t)1 << (--j
* 8)) - 1;
11158 /* Trim off encoding space. */
11159 if (j
> 1 && !i
.insn_opcode_space
&& (val
>> ((j
- 1) * 8)) == 0x0f)
11161 uint8_t byte
= val
>> ((--j
- 1) * 8);
11163 i
.insn_opcode_space
= SPACE_0F
;
11164 switch (byte
& -(j
> 1))
11167 i
.insn_opcode_space
= SPACE_0F38
;
11171 i
.insn_opcode_space
= SPACE_0F3A
;
11175 i
.tm
.opcode_space
= i
.insn_opcode_space
;
11176 val
&= ((uint64_t)1 << (j
* 8)) - 1;
11178 if (!i
.tm
.opcode_space
&& (vex
|| evex
))
11179 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
11180 Also avoid hitting abort() there or in build_evex_prefix(). */
11181 i
.tm
.opcode_space
= i
.insn_opcode_space
== SPACE_0F
? SPACE_0F
11186 as_bad (_("opcode residual (%#"PRIx64
") too wide"), (uint64_t) val
);
11189 i
.opcode_length
= j
;
11191 /* Handle operands, if any. */
11194 i386_operand_type combined
;
11195 expressionS
*disp_exp
= NULL
;
11200 ptr
= parse_operands (line
+ 1, &i386_mnemonics
[MN__insn
]);
11208 as_bad (_("expecting operand after ','; got nothing"));
11212 if (i
.mem_operands
> 1)
11214 as_bad (_("too many memory references for `%s'"),
11215 &i386_mnemonics
[MN__insn
]);
11219 /* Are we to emit ModR/M encoding? */
11222 || i
.reg_operands
> (i
.vec_encoding
!= vex_encoding_default
)
11223 || i
.tm
.extension_opcode
!= None
))
11224 i
.tm
.opcode_modifier
.modrm
= 1;
11226 if (!i
.tm
.opcode_modifier
.modrm
11228 > i
.short_form
+ 0U + (i
.vec_encoding
!= vex_encoding_default
)
11229 || i
.mem_operands
))
11231 as_bad (_("too many register/memory operands"));
11235 /* Enforce certain constraints on operands. */
11236 switch (i
.reg_operands
+ i
.mem_operands
11237 + (i
.tm
.extension_opcode
!= None
))
11242 as_bad (_("too few register/memory operands"));
11245 /* Fall through. */
11247 if (i
.tm
.opcode_modifier
.modrm
)
11249 as_bad (_("too few register/memory operands"));
11259 && (i
.op
[0].imms
->X_op
!= O_constant
11260 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
)))
11262 as_bad (_("constant doesn't fit in %d bits"), evex
? 3 : 4);
11265 /* Fall through. */
11267 if (i
.vec_encoding
!= vex_encoding_default
)
11269 i
.tm
.opcode_modifier
.vexvvvv
= 1;
11272 /* Fall through. */
11274 as_bad (_("too many register/memory operands"));
11278 /* Bring operands into canonical order (imm, mem, reg). */
11283 for (j
= 1; j
< i
.operands
; ++j
)
11285 if ((!operand_type_check (i
.types
[j
- 1], imm
)
11286 && operand_type_check (i
.types
[j
], imm
))
11287 || (i
.types
[j
- 1].bitfield
.class != ClassNone
11288 && i
.types
[j
].bitfield
.class == ClassNone
))
11290 swap_2_operands (j
- 1, j
);
11297 /* For Intel syntax swap the order of register operands. */
11299 switch (i
.reg_operands
)
11306 swap_2_operands (i
.imm_operands
+ i
.mem_operands
+ 1, i
.operands
- 2);
11307 /* Fall through. */
11310 swap_2_operands (i
.imm_operands
+ i
.mem_operands
, i
.operands
- 1);
11317 /* Enforce constraints when using VSIB. */
11319 && (i
.index_reg
->reg_type
.bitfield
.xmmword
11320 || i
.index_reg
->reg_type
.bitfield
.ymmword
11321 || i
.index_reg
->reg_type
.bitfield
.zmmword
))
11323 if (i
.vec_encoding
== vex_encoding_default
)
11325 as_bad (_("VSIB unavailable with legacy encoding"));
11329 if (i
.vec_encoding
== vex_encoding_evex
11330 && i
.reg_operands
> 1)
11332 /* We could allow two register operands, encoding the 2nd one in
11333 an 8-bit immediate like for 4-register-operand insns, but that
11334 would require ugly fiddling with process_operands() and/or
11335 build_modrm_byte(). */
11336 as_bad (_("too many register operands with VSIB"));
11340 i
.tm
.opcode_modifier
.sib
= 1;
11343 /* Establish operand size encoding. */
11344 operand_type_set (&combined
, 0);
11346 for (j
= i
.imm_operands
; j
< i
.operands
; ++j
)
11348 i
.types
[j
].bitfield
.instance
= InstanceNone
;
11350 if (operand_type_check (i
.types
[j
], disp
))
11352 i
.types
[j
].bitfield
.baseindex
= 1;
11353 disp_exp
= i
.op
[j
].disps
;
11356 if (evex
&& i
.types
[j
].bitfield
.baseindex
)
11358 unsigned int n
= i
.memshift
;
11360 if (i
.types
[j
].bitfield
.byte
)
11362 else if (i
.types
[j
].bitfield
.word
)
11364 else if (i
.types
[j
].bitfield
.dword
)
11366 else if (i
.types
[j
].bitfield
.qword
)
11368 else if (i
.types
[j
].bitfield
.xmmword
)
11370 else if (i
.types
[j
].bitfield
.ymmword
)
11372 else if (i
.types
[j
].bitfield
.zmmword
)
11375 if (i
.memshift
< 32 && n
!= i
.memshift
)
11376 as_warn ("conflicting memory operand size specifiers");
11380 if ((i
.broadcast
.type
|| i
.broadcast
.bytes
)
11381 && j
== i
.broadcast
.operand
)
11384 combined
= operand_type_or (combined
, i
.types
[j
]);
11385 combined
.bitfield
.class = ClassNone
;
11388 switch ((i
.broadcast
.type
? i
.broadcast
.type
: 1)
11389 << (i
.memshift
< 32 ? i
.memshift
: 0))
11391 case 64: combined
.bitfield
.zmmword
= 1; break;
11392 case 32: combined
.bitfield
.ymmword
= 1; break;
11393 case 16: combined
.bitfield
.xmmword
= 1; break;
11394 case 8: combined
.bitfield
.qword
= 1; break;
11395 case 4: combined
.bitfield
.dword
= 1; break;
11398 if (i
.vec_encoding
== vex_encoding_default
)
11400 if (flag_code
== CODE_64BIT
&& combined
.bitfield
.qword
)
11402 else if ((flag_code
== CODE_16BIT
? combined
.bitfield
.dword
11403 : combined
.bitfield
.word
)
11404 && !add_prefix (DATA_PREFIX_OPCODE
))
11407 else if (!i
.tm
.opcode_modifier
.vexw
)
11409 if (flag_code
== CODE_64BIT
)
11411 if (combined
.bitfield
.qword
)
11412 i
.tm
.opcode_modifier
.vexw
= VEXW1
;
11413 else if (combined
.bitfield
.dword
)
11414 i
.tm
.opcode_modifier
.vexw
= VEXW0
;
11417 if (!i
.tm
.opcode_modifier
.vexw
)
11418 i
.tm
.opcode_modifier
.vexw
= VEXWIG
;
11423 if (!i
.tm
.opcode_modifier
.vex
)
11425 if (combined
.bitfield
.ymmword
)
11426 i
.tm
.opcode_modifier
.vex
= VEX256
;
11427 else if (combined
.bitfield
.xmmword
)
11428 i
.tm
.opcode_modifier
.vex
= VEX128
;
11433 if (!i
.tm
.opcode_modifier
.evex
)
11435 /* Do _not_ consider AVX512VL here. */
11436 if (i
.rounding
.type
!= rc_none
|| combined
.bitfield
.zmmword
)
11437 i
.tm
.opcode_modifier
.evex
= EVEX512
;
11438 else if (combined
.bitfield
.ymmword
)
11439 i
.tm
.opcode_modifier
.evex
= EVEX256
;
11440 else if (combined
.bitfield
.xmmword
)
11441 i
.tm
.opcode_modifier
.evex
= EVEX128
;
11444 if (i
.memshift
>= 32)
11446 unsigned int n
= 0;
11448 switch (i
.tm
.opcode_modifier
.evex
)
11450 case EVEX512
: n
= 64; break;
11451 case EVEX256
: n
= 32; break;
11452 case EVEX128
: n
= 16; break;
11455 if (i
.broadcast
.type
)
11456 n
/= i
.broadcast
.type
;
11459 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11461 else if (disp_exp
!= NULL
&& disp_exp
->X_op
== O_constant
11462 && disp_exp
->X_add_number
!= 0
11463 && i
.disp_encoding
!= disp_encoding_32bit
)
11465 if (!quiet_warnings
)
11466 as_warn ("cannot determine memory operand size");
11467 i
.disp_encoding
= disp_encoding_32bit
;
11472 if (i
.memshift
>= 32)
11475 i
.vec_encoding
= vex_encoding_error
;
11477 if (i
.disp_operands
&& !optimize_disp (&i
.tm
))
11480 /* Establish size for immediate operands. */
11481 for (j
= 0; j
< i
.imm_operands
; ++j
)
11483 expressionS
*expP
= i
.op
[j
].imms
;
11485 gas_assert (operand_type_check (i
.types
[j
], imm
));
11486 operand_type_set (&i
.types
[j
], 0);
11488 if (i
.imm_bits
[j
] > 32)
11489 i
.types
[j
].bitfield
.imm64
= 1;
11490 else if (i
.imm_bits
[j
] > 16)
11492 if (flag_code
== CODE_64BIT
&& (i
.flags
[j
] & Operand_Signed
))
11493 i
.types
[j
].bitfield
.imm32s
= 1;
11495 i
.types
[j
].bitfield
.imm32
= 1;
11497 else if (i
.imm_bits
[j
] > 8)
11498 i
.types
[j
].bitfield
.imm16
= 1;
11499 else if (i
.imm_bits
[j
] > 0)
11501 if (i
.flags
[j
] & Operand_Signed
)
11502 i
.types
[j
].bitfield
.imm8s
= 1;
11504 i
.types
[j
].bitfield
.imm8
= 1;
11506 else if (expP
->X_op
== O_constant
)
11508 i
.types
[j
] = smallest_imm_type (expP
->X_add_number
);
11509 i
.types
[j
].bitfield
.imm1
= 0;
11510 /* Oddly enough imm_size() checks imm64 first, so the bit needs
11511 zapping since smallest_imm_type() sets it unconditionally. */
11512 if (flag_code
!= CODE_64BIT
)
11514 i
.types
[j
].bitfield
.imm64
= 0;
11515 i
.types
[j
].bitfield
.imm32s
= 0;
11516 i
.types
[j
].bitfield
.imm32
= 1;
11518 else if (i
.types
[j
].bitfield
.imm32
|| i
.types
[j
].bitfield
.imm32s
)
11519 i
.types
[j
].bitfield
.imm64
= 0;
11522 /* Non-constant expressions are sized heuristically. */
11525 case CODE_64BIT
: i
.types
[j
].bitfield
.imm32s
= 1; break;
11526 case CODE_32BIT
: i
.types
[j
].bitfield
.imm32
= 1; break;
11527 case CODE_16BIT
: i
.types
[j
].bitfield
.imm16
= 1; break;
11531 for (j
= 0; j
< i
.operands
; ++j
)
11532 i
.tm
.operand_types
[j
] = i
.types
[j
];
11534 process_operands ();
11537 /* Don't set opcode until after processing operands, to avoid any
11538 potential special casing there. */
11539 i
.tm
.base_opcode
|= val
;
11541 if (i
.vec_encoding
== vex_encoding_error
11542 || (i
.vec_encoding
!= vex_encoding_evex
11543 ? i
.broadcast
.type
|| i
.broadcast
.bytes
11544 || i
.rounding
.type
!= rc_none
11546 : (i
.broadcast
.type
|| i
.broadcast
.bytes
)
11547 && i
.rounding
.type
!= rc_none
))
11549 as_bad (_("conflicting .insn operands"));
11555 if (!i
.tm
.opcode_modifier
.vex
)
11556 i
.tm
.opcode_modifier
.vex
= VEXScalar
; /* LIG */
11558 build_vex_prefix (NULL
);
11559 i
.rex
&= REX_OPCODE
;
11563 if (!i
.tm
.opcode_modifier
.evex
)
11564 i
.tm
.opcode_modifier
.evex
= EVEXLIG
;
11566 build_evex_prefix ();
11567 i
.rex
&= REX_OPCODE
;
11569 else if (i
.rex
!= 0)
11570 add_prefix (REX_OPCODE
| i
.rex
);
11575 *saved_ilp
= saved_char
;
11576 input_line_pointer
= line
;
11578 demand_empty_rest_of_line ();
11580 /* Make sure dot_insn() won't yield "true" anymore. */
11586 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
11593 if (exp
.X_op
== O_symbol
)
11594 exp
.X_op
= O_secrel
;
11596 emit_expr (&exp
, 4);
11598 while (*input_line_pointer
++ == ',');
11600 input_line_pointer
--;
11601 demand_empty_rest_of_line ();
11605 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED
)
11612 if (exp
.X_op
== O_symbol
)
11613 exp
.X_op
= O_secidx
;
11615 emit_expr (&exp
, 2);
11617 while (*input_line_pointer
++ == ',');
11619 input_line_pointer
--;
11620 demand_empty_rest_of_line ();
11624 /* Handle Rounding Control / SAE specifiers. */
11627 RC_SAE_specifier (const char *pstr
)
11631 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); j
++)
11633 if (!strncmp (pstr
, RC_NamesTable
[j
].name
, RC_NamesTable
[j
].len
))
11635 if (i
.rounding
.type
!= rc_none
)
11637 as_bad (_("duplicated `{%s}'"), RC_NamesTable
[j
].name
);
11641 i
.rounding
.type
= RC_NamesTable
[j
].type
;
11643 return (char *)(pstr
+ RC_NamesTable
[j
].len
);
11650 /* Handle Vector operations. */
11653 check_VecOperations (char *op_string
)
11655 const reg_entry
*mask
;
11662 if (*op_string
== '{')
11666 /* Check broadcasts. */
11667 if (startswith (op_string
, "1to"))
11669 unsigned int bcst_type
;
11671 if (i
.broadcast
.type
)
11672 goto duplicated_vec_op
;
11675 if (*op_string
== '8')
11677 else if (*op_string
== '4')
11679 else if (*op_string
== '2')
11681 else if (*op_string
== '1'
11682 && *(op_string
+1) == '6')
11687 else if (*op_string
== '3'
11688 && *(op_string
+1) == '2')
11695 as_bad (_("Unsupported broadcast: `%s'"), saved
);
11700 i
.broadcast
.type
= bcst_type
;
11701 i
.broadcast
.operand
= this_operand
;
11703 /* For .insn a data size specifier may be appended. */
11704 if (dot_insn () && *op_string
== ':')
11705 goto dot_insn_modifier
;
11707 /* Check .insn special cases. */
11708 else if (dot_insn () && *op_string
== ':')
11711 switch (op_string
[1])
11716 if (i
.memshift
< 32)
11717 goto duplicated_vec_op
;
11719 n
= strtoul (op_string
+ 2, &end_op
, 0);
11721 for (i
.memshift
= 0; !(n
& 1); n
>>= 1)
11723 if (i
.memshift
< 32 && n
== 1)
11724 op_string
= end_op
;
11727 case 's': case 'u':
11728 /* This isn't really a "vector" operation, but a sign/size
11729 specifier for immediate operands of .insn. Note that AT&T
11730 syntax handles the same in i386_immediate(). */
11734 if (i
.imm_bits
[this_operand
])
11735 goto duplicated_vec_op
;
11737 n
= strtoul (op_string
+ 2, &end_op
, 0);
11738 if (n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11740 i
.imm_bits
[this_operand
] = n
;
11741 if (op_string
[1] == 's')
11742 i
.flags
[this_operand
] |= Operand_Signed
;
11743 op_string
= end_op
;
11748 /* Check masking operation. */
11749 else if ((mask
= parse_register (op_string
, &end_op
)) != NULL
)
11751 if (mask
== &bad_reg
)
11754 /* k0 can't be used for write mask. */
11755 if (mask
->reg_type
.bitfield
.class != RegMask
|| !mask
->reg_num
)
11757 as_bad (_("`%s%s' can't be used for write mask"),
11758 register_prefix
, mask
->reg_name
);
11765 i
.mask
.operand
= this_operand
;
11767 else if (i
.mask
.reg
->reg_num
)
11768 goto duplicated_vec_op
;
11773 /* Only "{z}" is allowed here. No need to check
11774 zeroing mask explicitly. */
11775 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11777 as_bad (_("invalid write mask `%s'"), saved
);
11782 op_string
= end_op
;
11784 /* Check zeroing-flag for masking operation. */
11785 else if (*op_string
== 'z')
11789 i
.mask
.reg
= reg_k0
;
11790 i
.mask
.zeroing
= 1;
11791 i
.mask
.operand
= this_operand
;
11795 if (i
.mask
.zeroing
)
11798 as_bad (_("duplicated `%s'"), saved
);
11802 i
.mask
.zeroing
= 1;
11804 /* Only "{%k}" is allowed here. No need to check mask
11805 register explicitly. */
11806 if (i
.mask
.operand
!= (unsigned int) this_operand
)
11808 as_bad (_("invalid zeroing-masking `%s'"),
11816 else if (intel_syntax
11817 && (op_string
= RC_SAE_specifier (op_string
)) != NULL
)
11818 i
.rounding
.modifier
= true;
11820 goto unknown_vec_op
;
11822 if (*op_string
!= '}')
11824 as_bad (_("missing `}' in `%s'"), saved
);
11829 /* Strip whitespace since the addition of pseudo prefixes
11830 changed how the scrubber treats '{'. */
11831 if (is_space_char (*op_string
))
11837 /* We don't know this one. */
11838 as_bad (_("unknown vector operation: `%s'"), saved
);
11842 if (i
.mask
.reg
&& i
.mask
.zeroing
&& !i
.mask
.reg
->reg_num
)
11844 as_bad (_("zeroing-masking only allowed with write mask"));
11852 i386_immediate (char *imm_start
)
11854 char *save_input_line_pointer
;
11855 char *gotfree_input_line
;
11858 i386_operand_type types
;
11860 operand_type_set (&types
, ~0);
11862 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
11864 as_bad (_("at most %d immediate operands are allowed"),
11865 MAX_IMMEDIATE_OPERANDS
);
11869 exp
= &im_expressions
[i
.imm_operands
++];
11870 i
.op
[this_operand
].imms
= exp
;
11872 if (is_space_char (*imm_start
))
11875 save_input_line_pointer
= input_line_pointer
;
11876 input_line_pointer
= imm_start
;
11878 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
11879 if (gotfree_input_line
)
11880 input_line_pointer
= gotfree_input_line
;
11882 expr_mode
= expr_operator_none
;
11883 exp_seg
= expression (exp
);
11885 /* For .insn immediates there may be a size specifier. */
11886 if (dot_insn () && *input_line_pointer
== '{' && input_line_pointer
[1] == ':'
11887 && (input_line_pointer
[2] == 's' || input_line_pointer
[2] == 'u'))
11890 unsigned long n
= strtoul (input_line_pointer
+ 3, &e
, 0);
11892 if (*e
== '}' && n
&& n
<= (flag_code
== CODE_64BIT
? 64 : 32))
11894 i
.imm_bits
[this_operand
] = n
;
11895 if (input_line_pointer
[2] == 's')
11896 i
.flags
[this_operand
] |= Operand_Signed
;
11897 input_line_pointer
= e
+ 1;
11901 SKIP_WHITESPACE ();
11902 if (*input_line_pointer
)
11903 as_bad (_("junk `%s' after expression"), input_line_pointer
);
11905 input_line_pointer
= save_input_line_pointer
;
11906 if (gotfree_input_line
)
11908 free (gotfree_input_line
);
11910 if (exp
->X_op
== O_constant
)
11911 exp
->X_op
= O_illegal
;
11914 if (exp_seg
== reg_section
)
11916 as_bad (_("illegal immediate register operand %s"), imm_start
);
11920 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
11924 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
11925 i386_operand_type types
, const char *imm_start
)
11927 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
11930 as_bad (_("missing or invalid immediate expression `%s'"),
11934 else if (exp
->X_op
== O_constant
)
11936 /* Size it properly later. */
11937 i
.types
[this_operand
].bitfield
.imm64
= 1;
11939 /* If not 64bit, sign/zero extend val, to account for wraparound
11941 if (expr_mode
== expr_operator_present
11942 && flag_code
!= CODE_64BIT
&& !object_64bit
)
11943 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
11945 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11946 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
11947 && exp_seg
!= absolute_section
11948 && exp_seg
!= text_section
11949 && exp_seg
!= data_section
11950 && exp_seg
!= bss_section
11951 && exp_seg
!= undefined_section
11952 && !bfd_is_com_section (exp_seg
))
11954 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
11960 /* This is an address. The size of the address will be
11961 determined later, depending on destination register,
11962 suffix, or the default for the section. */
11963 i
.types
[this_operand
].bitfield
.imm8
= 1;
11964 i
.types
[this_operand
].bitfield
.imm16
= 1;
11965 i
.types
[this_operand
].bitfield
.imm32
= 1;
11966 i
.types
[this_operand
].bitfield
.imm32s
= 1;
11967 i
.types
[this_operand
].bitfield
.imm64
= 1;
11968 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
11976 i386_scale (char *scale
)
11979 char *save
= input_line_pointer
;
11981 input_line_pointer
= scale
;
11982 val
= get_absolute_expression ();
11987 i
.log2_scale_factor
= 0;
11990 i
.log2_scale_factor
= 1;
11993 i
.log2_scale_factor
= 2;
11996 i
.log2_scale_factor
= 3;
12000 char sep
= *input_line_pointer
;
12002 *input_line_pointer
= '\0';
12003 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
12005 *input_line_pointer
= sep
;
12006 input_line_pointer
= save
;
12010 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
12012 as_warn (_("scale factor of %d without an index register"),
12013 1 << i
.log2_scale_factor
);
12014 i
.log2_scale_factor
= 0;
12016 scale
= input_line_pointer
;
12017 input_line_pointer
= save
;
12022 i386_displacement (char *disp_start
, char *disp_end
)
12026 char *save_input_line_pointer
;
12027 char *gotfree_input_line
;
12029 i386_operand_type bigdisp
, types
= anydisp
;
12032 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
12034 as_bad (_("at most %d displacement operands are allowed"),
12035 MAX_MEMORY_OPERANDS
);
12039 operand_type_set (&bigdisp
, 0);
12041 || i
.types
[this_operand
].bitfield
.baseindex
12042 || (current_templates
->start
->opcode_modifier
.jump
!= JUMP
12043 && current_templates
->start
->opcode_modifier
.jump
!= JUMP_DWORD
))
12045 i386_addressing_mode ();
12046 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
12047 if (flag_code
== CODE_64BIT
)
12049 bigdisp
.bitfield
.disp32
= 1;
12051 bigdisp
.bitfield
.disp64
= 1;
12053 else if ((flag_code
== CODE_16BIT
) ^ override
)
12054 bigdisp
.bitfield
.disp16
= 1;
12056 bigdisp
.bitfield
.disp32
= 1;
12060 /* For PC-relative branches, the width of the displacement may be
12061 dependent upon data size, but is never dependent upon address size.
12062 Also make sure to not unintentionally match against a non-PC-relative
12063 branch template. */
12064 static templates aux_templates
;
12065 const insn_template
*t
= current_templates
->start
;
12066 bool has_intel64
= false;
12068 aux_templates
.start
= t
;
12069 while (++t
< current_templates
->end
)
12071 if (t
->opcode_modifier
.jump
12072 != current_templates
->start
->opcode_modifier
.jump
)
12074 if ((t
->opcode_modifier
.isa64
>= INTEL64
))
12075 has_intel64
= true;
12077 if (t
< current_templates
->end
)
12079 aux_templates
.end
= t
;
12080 current_templates
= &aux_templates
;
12083 override
= (i
.prefix
[DATA_PREFIX
] != 0);
12084 if (flag_code
== CODE_64BIT
)
12086 if ((override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
12087 && (!intel64
|| !has_intel64
))
12088 bigdisp
.bitfield
.disp16
= 1;
12090 bigdisp
.bitfield
.disp32
= 1;
12095 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
12097 : LONG_MNEM_SUFFIX
));
12098 bigdisp
.bitfield
.disp32
= 1;
12099 if ((flag_code
== CODE_16BIT
) ^ override
)
12101 bigdisp
.bitfield
.disp32
= 0;
12102 bigdisp
.bitfield
.disp16
= 1;
12106 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12109 exp
= &disp_expressions
[i
.disp_operands
];
12110 i
.op
[this_operand
].disps
= exp
;
12112 save_input_line_pointer
= input_line_pointer
;
12113 input_line_pointer
= disp_start
;
12114 END_STRING_AND_SAVE (disp_end
);
12116 #ifndef GCC_ASM_O_HACK
12117 #define GCC_ASM_O_HACK 0
12120 END_STRING_AND_SAVE (disp_end
+ 1);
12121 if (i
.types
[this_operand
].bitfield
.baseIndex
12122 && displacement_string_end
[-1] == '+')
12124 /* This hack is to avoid a warning when using the "o"
12125 constraint within gcc asm statements.
12128 #define _set_tssldt_desc(n,addr,limit,type) \
12129 __asm__ __volatile__ ( \
12130 "movw %w2,%0\n\t" \
12131 "movw %w1,2+%0\n\t" \
12132 "rorl $16,%1\n\t" \
12133 "movb %b1,4+%0\n\t" \
12134 "movb %4,5+%0\n\t" \
12135 "movb $0,6+%0\n\t" \
12136 "movb %h1,7+%0\n\t" \
12138 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
12140 This works great except that the output assembler ends
12141 up looking a bit weird if it turns out that there is
12142 no offset. You end up producing code that looks like:
12155 So here we provide the missing zero. */
12157 *displacement_string_end
= '0';
12160 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
12161 if (gotfree_input_line
)
12162 input_line_pointer
= gotfree_input_line
;
12164 expr_mode
= expr_operator_none
;
12165 exp_seg
= expression (exp
);
12167 SKIP_WHITESPACE ();
12168 if (*input_line_pointer
)
12169 as_bad (_("junk `%s' after expression"), input_line_pointer
);
12171 RESTORE_END_STRING (disp_end
+ 1);
12173 input_line_pointer
= save_input_line_pointer
;
12174 if (gotfree_input_line
)
12176 free (gotfree_input_line
);
12178 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
12179 exp
->X_op
= O_illegal
;
12182 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
12184 RESTORE_END_STRING (disp_end
);
12190 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
12191 i386_operand_type types
, const char *disp_start
)
12195 /* We do this to make sure that the section symbol is in
12196 the symbol table. We will ultimately change the relocation
12197 to be relative to the beginning of the section. */
12198 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
12199 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
12200 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12202 if (exp
->X_op
!= O_symbol
)
12205 if (S_IS_LOCAL (exp
->X_add_symbol
)
12206 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
12207 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
12208 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
12209 exp
->X_op
= O_subtract
;
12210 exp
->X_op_symbol
= GOT_symbol
;
12211 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
12212 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
12213 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
12214 i
.reloc
[this_operand
] = BFD_RELOC_64
;
12216 i
.reloc
[this_operand
] = BFD_RELOC_32
;
12219 else if (exp
->X_op
== O_absent
12220 || exp
->X_op
== O_illegal
12221 || exp
->X_op
== O_big
)
12224 as_bad (_("missing or invalid displacement expression `%s'"),
12229 else if (exp
->X_op
== O_constant
)
12231 /* Sizing gets taken care of by optimize_disp().
12233 If not 64bit, sign/zero extend val, to account for wraparound
12235 if (expr_mode
== expr_operator_present
12236 && flag_code
!= CODE_64BIT
&& !object_64bit
)
12237 exp
->X_add_number
= extend_to_32bit_address (exp
->X_add_number
);
12240 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
12241 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
12242 && exp_seg
!= absolute_section
12243 && exp_seg
!= text_section
12244 && exp_seg
!= data_section
12245 && exp_seg
!= bss_section
12246 && exp_seg
!= undefined_section
12247 && !bfd_is_com_section (exp_seg
))
12249 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
12254 else if (current_templates
->start
->opcode_modifier
.jump
== JUMP_BYTE
)
12255 i
.types
[this_operand
].bitfield
.disp8
= 1;
12257 /* Check if this is a displacement only operand. */
12258 if (!i
.types
[this_operand
].bitfield
.baseindex
)
12259 i
.types
[this_operand
] =
12260 operand_type_or (operand_type_and_not (i
.types
[this_operand
], anydisp
),
12261 operand_type_and (i
.types
[this_operand
], types
));
12266 /* Return the active addressing mode, taking address override and
12267 registers forming the address into consideration. Update the
12268 address override prefix if necessary. */
12270 static enum flag_code
12271 i386_addressing_mode (void)
12273 enum flag_code addr_mode
;
12275 if (i
.prefix
[ADDR_PREFIX
])
12276 addr_mode
= flag_code
== CODE_32BIT
? CODE_16BIT
: CODE_32BIT
;
12277 else if (flag_code
== CODE_16BIT
12278 && is_cpu (current_templates
->start
, CpuMPX
)
12279 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
12280 from md_assemble() by "is not a valid base/index expression"
12281 when there is a base and/or index. */
12282 && !i
.types
[this_operand
].bitfield
.baseindex
)
12284 /* MPX insn memory operands with neither base nor index must be forced
12285 to use 32-bit addressing in 16-bit mode. */
12286 addr_mode
= CODE_32BIT
;
12287 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12289 gas_assert (!i
.types
[this_operand
].bitfield
.disp16
);
12290 gas_assert (!i
.types
[this_operand
].bitfield
.disp32
);
12294 addr_mode
= flag_code
;
12296 #if INFER_ADDR_PREFIX
12297 if (i
.mem_operands
== 0)
12299 /* Infer address prefix from the first memory operand. */
12300 const reg_entry
*addr_reg
= i
.base_reg
;
12302 if (addr_reg
== NULL
)
12303 addr_reg
= i
.index_reg
;
12307 if (addr_reg
->reg_type
.bitfield
.dword
)
12308 addr_mode
= CODE_32BIT
;
12309 else if (flag_code
!= CODE_64BIT
12310 && addr_reg
->reg_type
.bitfield
.word
)
12311 addr_mode
= CODE_16BIT
;
12313 if (addr_mode
!= flag_code
)
12315 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
12317 /* Change the size of any displacement too. At most one
12318 of Disp16 or Disp32 is set.
12319 FIXME. There doesn't seem to be any real need for
12320 separate Disp16 and Disp32 flags. The same goes for
12321 Imm16 and Imm32. Removing them would probably clean
12322 up the code quite a lot. */
12323 if (flag_code
!= CODE_64BIT
12324 && (i
.types
[this_operand
].bitfield
.disp16
12325 || i
.types
[this_operand
].bitfield
.disp32
))
12327 static const i386_operand_type disp16_32
= {
12328 .bitfield
= { .disp16
= 1, .disp32
= 1 }
12331 i
.types
[this_operand
]
12332 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
12343 /* Make sure the memory operand we've been dealt is valid.
12344 Return 1 on success, 0 on a failure. */
12347 i386_index_check (const char *operand_string
)
12349 const char *kind
= "base/index";
12350 enum flag_code addr_mode
= i386_addressing_mode ();
12351 const insn_template
*t
= current_templates
->end
- 1;
12353 if (t
->opcode_modifier
.isstring
)
12355 /* Memory operands of string insns are special in that they only allow
12356 a single register (rDI, rSI, or rBX) as their memory address. */
12357 const reg_entry
*expected_reg
;
12358 static const char di_si
[][2][4] =
12364 static const char bx
[][4] = { "ebx", "bx", "rbx" };
12366 kind
= "string address";
12368 if (t
->opcode_modifier
.prefixok
== PrefixRep
)
12370 int es_op
= t
->opcode_modifier
.isstring
- IS_STRING_ES_OP0
;
12373 if (!t
->operand_types
[0].bitfield
.baseindex
12374 || ((!i
.mem_operands
!= !intel_syntax
)
12375 && t
->operand_types
[1].bitfield
.baseindex
))
12378 = (const reg_entry
*) str_hash_find (reg_hash
,
12379 di_si
[addr_mode
][op
== es_op
]);
12383 = (const reg_entry
*)str_hash_find (reg_hash
, bx
[addr_mode
]);
12385 if (i
.base_reg
!= expected_reg
12387 || operand_type_check (i
.types
[this_operand
], disp
))
12389 /* The second memory operand must have the same size as
12393 && !((addr_mode
== CODE_64BIT
12394 && i
.base_reg
->reg_type
.bitfield
.qword
)
12395 || (addr_mode
== CODE_32BIT
12396 ? i
.base_reg
->reg_type
.bitfield
.dword
12397 : i
.base_reg
->reg_type
.bitfield
.word
)))
12400 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
12402 intel_syntax
? '[' : '(',
12404 expected_reg
->reg_name
,
12405 intel_syntax
? ']' : ')');
12412 as_bad (_("`%s' is not a valid %s expression"),
12413 operand_string
, kind
);
12418 t
= current_templates
->start
;
12420 if (addr_mode
!= CODE_16BIT
)
12422 /* 32-bit/64-bit checks. */
12423 if (i
.disp_encoding
== disp_encoding_16bit
)
12426 as_bad (_("invalid `%s' prefix"),
12427 addr_mode
== CODE_16BIT
? "{disp32}" : "{disp16}");
12432 && ((addr_mode
== CODE_64BIT
12433 ? !i
.base_reg
->reg_type
.bitfield
.qword
12434 : !i
.base_reg
->reg_type
.bitfield
.dword
)
12435 || (i
.index_reg
&& i
.base_reg
->reg_num
== RegIP
)
12436 || i
.base_reg
->reg_num
== RegIZ
))
12438 && !i
.index_reg
->reg_type
.bitfield
.xmmword
12439 && !i
.index_reg
->reg_type
.bitfield
.ymmword
12440 && !i
.index_reg
->reg_type
.bitfield
.zmmword
12441 && ((addr_mode
== CODE_64BIT
12442 ? !i
.index_reg
->reg_type
.bitfield
.qword
12443 : !i
.index_reg
->reg_type
.bitfield
.dword
)
12444 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
12447 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
12448 if (t
->mnem_off
== MN_bndmk
12449 || t
->mnem_off
== MN_bndldx
12450 || t
->mnem_off
== MN_bndstx
12451 || t
->opcode_modifier
.sib
== SIBMEM
)
12453 /* They cannot use RIP-relative addressing. */
12454 if (i
.base_reg
&& i
.base_reg
->reg_num
== RegIP
)
12456 as_bad (_("`%s' cannot be used here"), operand_string
);
12460 /* bndldx and bndstx ignore their scale factor. */
12461 if ((t
->mnem_off
== MN_bndldx
|| t
->mnem_off
== MN_bndstx
)
12462 && i
.log2_scale_factor
)
12463 as_warn (_("register scaling is being ignored here"));
12468 /* 16-bit checks. */
12469 if (i
.disp_encoding
== disp_encoding_32bit
)
12473 && (!i
.base_reg
->reg_type
.bitfield
.word
12474 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
12476 && (!i
.index_reg
->reg_type
.bitfield
.word
12477 || !i
.index_reg
->reg_type
.bitfield
.baseindex
12479 && i
.base_reg
->reg_num
< 6
12480 && i
.index_reg
->reg_num
>= 6
12481 && i
.log2_scale_factor
== 0))))
12488 /* Handle vector immediates. */
12491 RC_SAE_immediate (const char *imm_start
)
12493 const char *pstr
= imm_start
;
12498 pstr
= RC_SAE_specifier (pstr
+ 1);
12502 if (*pstr
++ != '}')
12504 as_bad (_("Missing '}': '%s'"), imm_start
);
12507 /* RC/SAE immediate string should contain nothing more. */;
12510 as_bad (_("Junk after '}': '%s'"), imm_start
);
12514 /* Internally this doesn't count as an operand. */
12520 static INLINE
bool starts_memory_operand (char c
)
12523 || is_name_beginner (c
)
12524 || strchr ("([\"+-!~", c
);
12527 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
12531 i386_att_operand (char *operand_string
)
12533 const reg_entry
*r
;
12535 char *op_string
= operand_string
;
12537 if (is_space_char (*op_string
))
12540 /* We check for an absolute prefix (differentiating,
12541 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
12542 if (*op_string
== ABSOLUTE_PREFIX
12543 && current_templates
->start
->opcode_modifier
.jump
)
12546 if (is_space_char (*op_string
))
12548 i
.jumpabsolute
= true;
12551 /* Check if operand is a register. */
12552 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
12554 i386_operand_type temp
;
12559 /* Check for a segment override by searching for ':' after a
12560 segment register. */
12561 op_string
= end_op
;
12562 if (is_space_char (*op_string
))
12564 if (*op_string
== ':' && r
->reg_type
.bitfield
.class == SReg
)
12566 i
.seg
[i
.mem_operands
] = r
;
12568 /* Skip the ':' and whitespace. */
12570 if (is_space_char (*op_string
))
12573 /* Handle case of %es:*foo. */
12574 if (!i
.jumpabsolute
&& *op_string
== ABSOLUTE_PREFIX
12575 && current_templates
->start
->opcode_modifier
.jump
)
12578 if (is_space_char (*op_string
))
12580 i
.jumpabsolute
= true;
12583 if (!starts_memory_operand (*op_string
))
12585 as_bad (_("bad memory operand `%s'"), op_string
);
12588 goto do_memory_reference
;
12591 /* Handle vector operations. */
12592 if (*op_string
== '{')
12594 op_string
= check_VecOperations (op_string
);
12595 if (op_string
== NULL
)
12601 as_bad (_("junk `%s' after register"), op_string
);
12605 /* Reject pseudo registers for .insn. */
12606 if (dot_insn () && r
->reg_type
.bitfield
.class == ClassNone
)
12608 as_bad (_("`%s%s' cannot be used here"),
12609 register_prefix
, r
->reg_name
);
12613 temp
= r
->reg_type
;
12614 temp
.bitfield
.baseindex
= 0;
12615 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
12617 i
.types
[this_operand
].bitfield
.unspecified
= 0;
12618 i
.op
[this_operand
].regs
= r
;
12621 /* A GPR may follow an RC or SAE immediate only if a (vector) register
12622 operand was also present earlier on. */
12623 if (i
.rounding
.type
!= rc_none
&& temp
.bitfield
.class == Reg
12624 && i
.reg_operands
== 1)
12628 for (j
= 0; j
< ARRAY_SIZE (RC_NamesTable
); ++j
)
12629 if (i
.rounding
.type
== RC_NamesTable
[j
].type
)
12631 as_bad (_("`%s': misplaced `{%s}'"),
12632 insn_name (current_templates
->start
), RC_NamesTable
[j
].name
);
12636 else if (*op_string
== REGISTER_PREFIX
)
12638 as_bad (_("bad register name `%s'"), op_string
);
12641 else if (*op_string
== IMMEDIATE_PREFIX
)
12644 if (i
.jumpabsolute
)
12646 as_bad (_("immediate operand illegal with absolute jump"));
12649 if (!i386_immediate (op_string
))
12651 if (i
.rounding
.type
!= rc_none
)
12653 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
12654 insn_name (current_templates
->start
));
12658 else if (RC_SAE_immediate (operand_string
))
12660 /* If it is a RC or SAE immediate, do the necessary placement check:
12661 Only another immediate or a GPR may precede it. */
12662 if (i
.mem_operands
|| i
.reg_operands
+ i
.imm_operands
> 1
12663 || (i
.reg_operands
== 1
12664 && i
.op
[0].regs
->reg_type
.bitfield
.class != Reg
))
12666 as_bad (_("`%s': misplaced `%s'"),
12667 insn_name (current_templates
->start
), operand_string
);
12671 else if (starts_memory_operand (*op_string
))
12673 /* This is a memory reference of some sort. */
12676 /* Start and end of displacement string expression (if found). */
12677 char *displacement_string_start
;
12678 char *displacement_string_end
;
12680 do_memory_reference
:
12681 /* Check for base index form. We detect the base index form by
12682 looking for an ')' at the end of the operand, searching
12683 for the '(' matching it, and finding a REGISTER_PREFIX or ','
12685 base_string
= op_string
+ strlen (op_string
);
12687 /* Handle vector operations. */
12689 if (is_space_char (*base_string
))
12692 if (*base_string
== '}')
12694 char *vop_start
= NULL
;
12696 while (base_string
-- > op_string
)
12698 if (*base_string
== '"')
12700 if (*base_string
!= '{')
12703 vop_start
= base_string
;
12706 if (is_space_char (*base_string
))
12709 if (*base_string
!= '}')
12717 as_bad (_("unbalanced figure braces"));
12721 if (check_VecOperations (vop_start
) == NULL
)
12725 /* If we only have a displacement, set-up for it to be parsed later. */
12726 displacement_string_start
= op_string
;
12727 displacement_string_end
= base_string
+ 1;
12729 if (*base_string
== ')')
12732 unsigned int parens_not_balanced
= 0;
12733 bool in_quotes
= false;
12735 /* We've already checked that the number of left & right ()'s are
12736 equal, and that there's a matching set of double quotes. */
12737 end_op
= base_string
;
12738 for (temp_string
= op_string
; temp_string
< end_op
; temp_string
++)
12740 if (*temp_string
== '\\' && temp_string
[1] == '"')
12742 else if (*temp_string
== '"')
12743 in_quotes
= !in_quotes
;
12744 else if (!in_quotes
)
12746 if (*temp_string
== '(' && !parens_not_balanced
++)
12747 base_string
= temp_string
;
12748 if (*temp_string
== ')')
12749 --parens_not_balanced
;
12753 temp_string
= base_string
;
12755 /* Skip past '(' and whitespace. */
12756 gas_assert (*base_string
== '(');
12758 if (is_space_char (*base_string
))
12761 if (*base_string
== ','
12762 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
12765 displacement_string_end
= temp_string
;
12767 i
.types
[this_operand
].bitfield
.baseindex
= 1;
12771 if (i
.base_reg
== &bad_reg
)
12773 base_string
= end_op
;
12774 if (is_space_char (*base_string
))
12778 /* There may be an index reg or scale factor here. */
12779 if (*base_string
== ',')
12782 if (is_space_char (*base_string
))
12785 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
12788 if (i
.index_reg
== &bad_reg
)
12790 base_string
= end_op
;
12791 if (is_space_char (*base_string
))
12793 if (*base_string
== ',')
12796 if (is_space_char (*base_string
))
12799 else if (*base_string
!= ')')
12801 as_bad (_("expecting `,' or `)' "
12802 "after index register in `%s'"),
12807 else if (*base_string
== REGISTER_PREFIX
)
12809 end_op
= strchr (base_string
, ',');
12812 as_bad (_("bad register name `%s'"), base_string
);
12816 /* Check for scale factor. */
12817 if (*base_string
!= ')')
12819 char *end_scale
= i386_scale (base_string
);
12824 base_string
= end_scale
;
12825 if (is_space_char (*base_string
))
12827 if (*base_string
!= ')')
12829 as_bad (_("expecting `)' "
12830 "after scale factor in `%s'"),
12835 else if (!i
.index_reg
)
12837 as_bad (_("expecting index register or scale factor "
12838 "after `,'; got '%c'"),
12843 else if (*base_string
!= ')')
12845 as_bad (_("expecting `,' or `)' "
12846 "after base register in `%s'"),
12851 else if (*base_string
== REGISTER_PREFIX
)
12853 end_op
= strchr (base_string
, ',');
12856 as_bad (_("bad register name `%s'"), base_string
);
12861 /* If there's an expression beginning the operand, parse it,
12862 assuming displacement_string_start and
12863 displacement_string_end are meaningful. */
12864 if (displacement_string_start
!= displacement_string_end
)
12866 if (!i386_displacement (displacement_string_start
,
12867 displacement_string_end
))
12871 /* Special case for (%dx) while doing input/output op. */
12873 && i
.base_reg
->reg_type
.bitfield
.instance
== RegD
12874 && i
.base_reg
->reg_type
.bitfield
.word
12875 && i
.index_reg
== 0
12876 && i
.log2_scale_factor
== 0
12877 && i
.seg
[i
.mem_operands
] == 0
12878 && !operand_type_check (i
.types
[this_operand
], disp
))
12880 i
.types
[this_operand
] = i
.base_reg
->reg_type
;
12881 i
.input_output_operand
= true;
12885 if (i386_index_check (operand_string
) == 0)
12887 i
.flags
[this_operand
] |= Operand_Mem
;
12892 /* It's not a memory operand; argh! */
12893 as_bad (_("invalid char %s beginning operand %d `%s'"),
12894 output_invalid (*op_string
),
12899 return 1; /* Normal return. */
12902 /* Calculate the maximum variable size (i.e., excluding fr_fix)
12903 that an rs_machine_dependent frag may reach. */
12906 i386_frag_max_var (fragS
*frag
)
12908 /* The only relaxable frags are for jumps.
12909 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
12910 gas_assert (frag
->fr_type
== rs_machine_dependent
);
12911 return TYPE_FROM_RELAX_STATE (frag
->fr_subtype
) == UNCOND_JUMP
? 4 : 5;
12914 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12916 elf_symbol_resolved_in_segment_p (symbolS
*fr_symbol
, offsetT fr_var
)
12918 /* STT_GNU_IFUNC symbol must go through PLT. */
12919 if ((symbol_get_bfdsym (fr_symbol
)->flags
12920 & BSF_GNU_INDIRECT_FUNCTION
) != 0)
12923 if (!S_IS_EXTERNAL (fr_symbol
))
12924 /* Symbol may be weak or local. */
12925 return !S_IS_WEAK (fr_symbol
);
12927 /* Global symbols with non-default visibility can't be preempted. */
12928 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol
)) != STV_DEFAULT
)
12931 if (fr_var
!= NO_RELOC
)
12932 switch ((enum bfd_reloc_code_real
) fr_var
)
12934 case BFD_RELOC_386_PLT32
:
12935 case BFD_RELOC_X86_64_PLT32
:
12936 /* Symbol with PLT relocation may be preempted. */
12942 /* Global symbols with default visibility in a shared library may be
12943 preempted by another definition. */
12948 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
12949 Note also work for Skylake and Cascadelake.
12950 ---------------------------------------------------------------------
12951 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
12952 | ------ | ----------- | ------- | -------- |
12954 | Jno | N | N | Y |
12955 | Jc/Jb | Y | N | Y |
12956 | Jae/Jnb | Y | N | Y |
12957 | Je/Jz | Y | Y | Y |
12958 | Jne/Jnz | Y | Y | Y |
12959 | Jna/Jbe | Y | N | Y |
12960 | Ja/Jnbe | Y | N | Y |
12962 | Jns | N | N | Y |
12963 | Jp/Jpe | N | N | Y |
12964 | Jnp/Jpo | N | N | Y |
12965 | Jl/Jnge | Y | Y | Y |
12966 | Jge/Jnl | Y | Y | Y |
12967 | Jle/Jng | Y | Y | Y |
12968 | Jg/Jnle | Y | Y | Y |
12969 --------------------------------------------------------------------- */
12971 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp
, enum mf_jcc_kind mf_jcc
)
12973 if (mf_cmp
== mf_cmp_alu_cmp
)
12974 return ((mf_jcc
>= mf_jcc_jc
&& mf_jcc
<= mf_jcc_jna
)
12975 || mf_jcc
== mf_jcc_jl
|| mf_jcc
== mf_jcc_jle
);
12976 if (mf_cmp
== mf_cmp_incdec
)
12977 return (mf_jcc
== mf_jcc_je
|| mf_jcc
== mf_jcc_jl
12978 || mf_jcc
== mf_jcc_jle
);
12979 if (mf_cmp
== mf_cmp_test_and
)
12984 /* Return the next non-empty frag. */
12987 i386_next_non_empty_frag (fragS
*fragP
)
12989 /* There may be a frag with a ".fill 0" when there is no room in
12990 the current frag for frag_grow in output_insn. */
12991 for (fragP
= fragP
->fr_next
;
12993 && fragP
->fr_type
== rs_fill
12994 && fragP
->fr_fix
== 0);
12995 fragP
= fragP
->fr_next
)
13000 /* Return the next jcc frag after BRANCH_PADDING. */
13003 i386_next_fusible_jcc_frag (fragS
*maybe_cmp_fragP
, fragS
*pad_fragP
)
13005 fragS
*branch_fragP
;
13009 if (pad_fragP
->fr_type
== rs_machine_dependent
13010 && (TYPE_FROM_RELAX_STATE (pad_fragP
->fr_subtype
)
13011 == BRANCH_PADDING
))
13013 branch_fragP
= i386_next_non_empty_frag (pad_fragP
);
13014 if (branch_fragP
->fr_type
!= rs_machine_dependent
)
13016 if (TYPE_FROM_RELAX_STATE (branch_fragP
->fr_subtype
) == COND_JUMP
13017 && i386_macro_fusible_p (maybe_cmp_fragP
->tc_frag_data
.mf_type
,
13018 pad_fragP
->tc_frag_data
.mf_type
))
13019 return branch_fragP
;
13025 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
13028 i386_classify_machine_dependent_frag (fragS
*fragP
)
13032 fragS
*branch_fragP
;
13034 unsigned int max_prefix_length
;
13036 if (fragP
->tc_frag_data
.classified
)
13039 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
13040 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
13041 for (next_fragP
= fragP
;
13042 next_fragP
!= NULL
;
13043 next_fragP
= next_fragP
->fr_next
)
13045 next_fragP
->tc_frag_data
.classified
= 1;
13046 if (next_fragP
->fr_type
== rs_machine_dependent
)
13047 switch (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
))
13049 case BRANCH_PADDING
:
13050 /* The BRANCH_PADDING frag must be followed by a branch
13052 branch_fragP
= i386_next_non_empty_frag (next_fragP
);
13053 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13055 case FUSED_JCC_PADDING
:
13056 /* Check if this is a fused jcc:
13058 CMP like instruction
13062 cmp_fragP
= i386_next_non_empty_frag (next_fragP
);
13063 pad_fragP
= i386_next_non_empty_frag (cmp_fragP
);
13064 branch_fragP
= i386_next_fusible_jcc_frag (next_fragP
, pad_fragP
);
13067 /* The BRANCH_PADDING frag is merged with the
13068 FUSED_JCC_PADDING frag. */
13069 next_fragP
->tc_frag_data
.u
.branch_fragP
= branch_fragP
;
13070 /* CMP like instruction size. */
13071 next_fragP
->tc_frag_data
.cmp_size
= cmp_fragP
->fr_fix
;
13072 frag_wane (pad_fragP
);
13073 /* Skip to branch_fragP. */
13074 next_fragP
= branch_fragP
;
13076 else if (next_fragP
->tc_frag_data
.max_prefix_length
)
13078 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
13080 next_fragP
->fr_subtype
13081 = ENCODE_RELAX_STATE (BRANCH_PREFIX
, 0);
13082 next_fragP
->tc_frag_data
.max_bytes
13083 = next_fragP
->tc_frag_data
.max_prefix_length
;
13084 /* This will be updated in the BRANCH_PREFIX scan. */
13085 next_fragP
->tc_frag_data
.max_prefix_length
= 0;
13088 frag_wane (next_fragP
);
13093 /* Stop if there is no BRANCH_PREFIX. */
13094 if (!align_branch_prefix_size
)
13097 /* Scan for BRANCH_PREFIX. */
13098 for (; fragP
!= NULL
; fragP
= fragP
->fr_next
)
13100 if (fragP
->fr_type
!= rs_machine_dependent
13101 || (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13105 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
13106 COND_JUMP_PREFIX. */
13107 max_prefix_length
= 0;
13108 for (next_fragP
= fragP
;
13109 next_fragP
!= NULL
;
13110 next_fragP
= next_fragP
->fr_next
)
13112 if (next_fragP
->fr_type
== rs_fill
)
13113 /* Skip rs_fill frags. */
13115 else if (next_fragP
->fr_type
!= rs_machine_dependent
)
13116 /* Stop for all other frags. */
13119 /* rs_machine_dependent frags. */
13120 if (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13123 /* Count BRANCH_PREFIX frags. */
13124 if (max_prefix_length
>= MAX_FUSED_JCC_PADDING_SIZE
)
13126 max_prefix_length
= MAX_FUSED_JCC_PADDING_SIZE
;
13127 frag_wane (next_fragP
);
13131 += next_fragP
->tc_frag_data
.max_bytes
;
13133 else if ((TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13135 || (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13136 == FUSED_JCC_PADDING
))
13138 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
13139 fragP
->tc_frag_data
.u
.padding_fragP
= next_fragP
;
13143 /* Stop for other rs_machine_dependent frags. */
13147 fragP
->tc_frag_data
.max_prefix_length
= max_prefix_length
;
13149 /* Skip to the next frag. */
13150 fragP
= next_fragP
;
13154 /* Compute padding size for
13157 CMP like instruction
13159 COND_JUMP/UNCOND_JUMP
13164 COND_JUMP/UNCOND_JUMP
13168 i386_branch_padding_size (fragS
*fragP
, offsetT address
)
13170 unsigned int offset
, size
, padding_size
;
13171 fragS
*branch_fragP
= fragP
->tc_frag_data
.u
.branch_fragP
;
13173 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
13175 address
= fragP
->fr_address
;
13176 address
+= fragP
->fr_fix
;
13178 /* CMP like instrunction size. */
13179 size
= fragP
->tc_frag_data
.cmp_size
;
13181 /* The base size of the branch frag. */
13182 size
+= branch_fragP
->fr_fix
;
13184 /* Add opcode and displacement bytes for the rs_machine_dependent
13186 if (branch_fragP
->fr_type
== rs_machine_dependent
)
13187 size
+= md_relax_table
[branch_fragP
->fr_subtype
].rlx_length
;
13189 /* Check if branch is within boundary and doesn't end at the last
13191 offset
= address
& ((1U << align_branch_power
) - 1);
13192 if ((offset
+ size
) >= (1U << align_branch_power
))
13193 /* Padding needed to avoid crossing boundary. */
13194 padding_size
= (1U << align_branch_power
) - offset
;
13196 /* No padding needed. */
13199 /* The return value may be saved in tc_frag_data.length which is
13201 if (!fits_in_unsigned_byte (padding_size
))
13204 return padding_size
;
13207 /* i386_generic_table_relax_frag()
13209 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
13210 grow/shrink padding to align branch frags. Hand others to
13214 i386_generic_table_relax_frag (segT segment
, fragS
*fragP
, long stretch
)
13216 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13217 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13219 long padding_size
= i386_branch_padding_size (fragP
, 0);
13220 long grow
= padding_size
- fragP
->tc_frag_data
.length
;
13222 /* When the BRANCH_PREFIX frag is used, the computed address
13223 must match the actual address and there should be no padding. */
13224 if (fragP
->tc_frag_data
.padding_address
13225 && (fragP
->tc_frag_data
.padding_address
!= fragP
->fr_address
13229 /* Update the padding size. */
13231 fragP
->tc_frag_data
.length
= padding_size
;
13235 else if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13237 fragS
*padding_fragP
, *next_fragP
;
13238 long padding_size
, left_size
, last_size
;
13240 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13241 if (!padding_fragP
)
13242 /* Use the padding set by the leading BRANCH_PREFIX frag. */
13243 return (fragP
->tc_frag_data
.length
13244 - fragP
->tc_frag_data
.last_length
);
13246 /* Compute the relative address of the padding frag in the very
13247 first time where the BRANCH_PREFIX frag sizes are zero. */
13248 if (!fragP
->tc_frag_data
.padding_address
)
13249 fragP
->tc_frag_data
.padding_address
13250 = padding_fragP
->fr_address
- (fragP
->fr_address
- stretch
);
13252 /* First update the last length from the previous interation. */
13253 left_size
= fragP
->tc_frag_data
.prefix_length
;
13254 for (next_fragP
= fragP
;
13255 next_fragP
!= padding_fragP
;
13256 next_fragP
= next_fragP
->fr_next
)
13257 if (next_fragP
->fr_type
== rs_machine_dependent
13258 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13263 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13267 if (max
> left_size
)
13272 next_fragP
->tc_frag_data
.last_length
= size
;
13276 next_fragP
->tc_frag_data
.last_length
= 0;
13279 /* Check the padding size for the padding frag. */
13280 padding_size
= i386_branch_padding_size
13281 (padding_fragP
, (fragP
->fr_address
13282 + fragP
->tc_frag_data
.padding_address
));
13284 last_size
= fragP
->tc_frag_data
.prefix_length
;
13285 /* Check if there is change from the last interation. */
13286 if (padding_size
== last_size
)
13288 /* Update the expected address of the padding frag. */
13289 padding_fragP
->tc_frag_data
.padding_address
13290 = (fragP
->fr_address
+ padding_size
13291 + fragP
->tc_frag_data
.padding_address
);
13295 if (padding_size
> fragP
->tc_frag_data
.max_prefix_length
)
13297 /* No padding if there is no sufficient room. Clear the
13298 expected address of the padding frag. */
13299 padding_fragP
->tc_frag_data
.padding_address
= 0;
13303 /* Store the expected address of the padding frag. */
13304 padding_fragP
->tc_frag_data
.padding_address
13305 = (fragP
->fr_address
+ padding_size
13306 + fragP
->tc_frag_data
.padding_address
);
13308 fragP
->tc_frag_data
.prefix_length
= padding_size
;
13310 /* Update the length for the current interation. */
13311 left_size
= padding_size
;
13312 for (next_fragP
= fragP
;
13313 next_fragP
!= padding_fragP
;
13314 next_fragP
= next_fragP
->fr_next
)
13315 if (next_fragP
->fr_type
== rs_machine_dependent
13316 && (TYPE_FROM_RELAX_STATE (next_fragP
->fr_subtype
)
13321 int max
= next_fragP
->tc_frag_data
.max_bytes
;
13325 if (max
> left_size
)
13330 next_fragP
->tc_frag_data
.length
= size
;
13334 next_fragP
->tc_frag_data
.length
= 0;
13337 return (fragP
->tc_frag_data
.length
13338 - fragP
->tc_frag_data
.last_length
);
13340 return relax_frag (segment
, fragP
, stretch
);
13343 /* md_estimate_size_before_relax()
13345 Called just before relax() for rs_machine_dependent frags. The x86
13346 assembler uses these frags to handle variable size jump
13349 Any symbol that is now undefined will not become defined.
13350 Return the correct fr_subtype in the frag.
13351 Return the initial "guess for variable size of frag" to caller.
13352 The guess is actually the growth beyond the fixed part. Whatever
13353 we do to grow the fixed or variable part contributes to our
13357 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
13359 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13360 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
13361 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
)
13363 i386_classify_machine_dependent_frag (fragP
);
13364 return fragP
->tc_frag_data
.length
;
13367 /* We've already got fragP->fr_subtype right; all we have to do is
13368 check for un-relaxable symbols. On an ELF system, we can't relax
13369 an externally visible symbol, because it may be overridden by a
13371 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
13372 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13374 && !elf_symbol_resolved_in_segment_p (fragP
->fr_symbol
,
13377 #if defined (OBJ_COFF) && defined (TE_PE)
13378 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
13379 && S_IS_WEAK (fragP
->fr_symbol
))
13383 /* Symbol is undefined in this segment, or we need to keep a
13384 reloc so that weak symbols can be overridden. */
13385 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
13386 enum bfd_reloc_code_real reloc_type
;
13387 unsigned char *opcode
;
13391 if (fragP
->fr_var
!= NO_RELOC
)
13392 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
13393 else if (size
== 2)
13394 reloc_type
= BFD_RELOC_16_PCREL
;
13395 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13396 else if (fragP
->tc_frag_data
.code64
&& fragP
->fr_offset
== 0
13397 && need_plt32_p (fragP
->fr_symbol
))
13398 reloc_type
= BFD_RELOC_X86_64_PLT32
;
13401 reloc_type
= BFD_RELOC_32_PCREL
;
13403 old_fr_fix
= fragP
->fr_fix
;
13404 opcode
= (unsigned char *) fragP
->fr_opcode
;
13406 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
13409 /* Make jmp (0xeb) a (d)word displacement jump. */
13411 fragP
->fr_fix
+= size
;
13412 fixP
= fix_new (fragP
, old_fr_fix
, size
,
13414 fragP
->fr_offset
, 1,
13420 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
13422 /* Negate the condition, and branch past an
13423 unconditional jump. */
13426 /* Insert an unconditional jump. */
13428 /* We added two extra opcode bytes, and have a two byte
13430 fragP
->fr_fix
+= 2 + 2;
13431 fix_new (fragP
, old_fr_fix
+ 2, 2,
13433 fragP
->fr_offset
, 1,
13437 /* Fall through. */
13440 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
13442 fragP
->fr_fix
+= 1;
13443 fixP
= fix_new (fragP
, old_fr_fix
, 1,
13445 fragP
->fr_offset
, 1,
13446 BFD_RELOC_8_PCREL
);
13447 fixP
->fx_signed
= 1;
13451 /* This changes the byte-displacement jump 0x7N
13452 to the (d)word-displacement jump 0x0f,0x8N. */
13453 opcode
[1] = opcode
[0] + 0x10;
13454 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13455 /* We've added an opcode byte. */
13456 fragP
->fr_fix
+= 1 + size
;
13457 fixP
= fix_new (fragP
, old_fr_fix
+ 1, size
,
13459 fragP
->fr_offset
, 1,
13464 BAD_CASE (fragP
->fr_subtype
);
13468 /* All jumps handled here are signed, but don't unconditionally use a
13469 signed limit check for 32 and 16 bit jumps as we want to allow wrap
13470 around at 4G (outside of 64-bit mode) and 64k. */
13471 if (size
== 4 && flag_code
== CODE_64BIT
)
13472 fixP
->fx_signed
= 1;
13475 return fragP
->fr_fix
- old_fr_fix
;
13478 /* Guess size depending on current relax state. Initially the relax
13479 state will correspond to a short jump and we return 1, because
13480 the variable part of the frag (the branch offset) is one byte
13481 long. However, we can relax a section more than once and in that
13482 case we must either set fr_subtype back to the unrelaxed state,
13483 or return the value for the appropriate branch. */
13484 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
13487 /* Called after relax() is finished.
13489 In: Address of frag.
13490 fr_type == rs_machine_dependent.
13491 fr_subtype is what the address relaxed to.
13493 Out: Any fixSs and constants are set up.
13494 Caller will turn frag into a ".space 0". */
13497 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT sec ATTRIBUTE_UNUSED
,
13500 unsigned char *opcode
;
13501 unsigned char *where_to_put_displacement
= NULL
;
13502 offsetT target_address
;
13503 offsetT opcode_address
;
13504 unsigned int extension
= 0;
13505 offsetT displacement_from_opcode_start
;
13507 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PADDING
13508 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == FUSED_JCC_PADDING
13509 || TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13511 /* Generate nop padding. */
13512 unsigned int size
= fragP
->tc_frag_data
.length
;
13515 if (size
> fragP
->tc_frag_data
.max_bytes
)
13521 const char *branch
= "branch";
13522 const char *prefix
= "";
13523 fragS
*padding_fragP
;
13524 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
)
13527 padding_fragP
= fragP
->tc_frag_data
.u
.padding_fragP
;
13528 switch (fragP
->tc_frag_data
.default_prefix
)
13533 case CS_PREFIX_OPCODE
:
13536 case DS_PREFIX_OPCODE
:
13539 case ES_PREFIX_OPCODE
:
13542 case FS_PREFIX_OPCODE
:
13545 case GS_PREFIX_OPCODE
:
13548 case SS_PREFIX_OPCODE
:
13553 msg
= _("%s:%u: add %d%s at 0x%llx to align "
13554 "%s within %d-byte boundary\n");
13556 msg
= _("%s:%u: add additional %d%s at 0x%llx to "
13557 "align %s within %d-byte boundary\n");
13561 padding_fragP
= fragP
;
13562 msg
= _("%s:%u: add %d%s-byte nop at 0x%llx to align "
13563 "%s within %d-byte boundary\n");
13567 switch (padding_fragP
->tc_frag_data
.branch_type
)
13569 case align_branch_jcc
:
13572 case align_branch_fused
:
13573 branch
= "fused jcc";
13575 case align_branch_jmp
:
13578 case align_branch_call
:
13581 case align_branch_indirect
:
13582 branch
= "indiret branch";
13584 case align_branch_ret
:
13591 fprintf (stdout
, msg
,
13592 fragP
->fr_file
, fragP
->fr_line
, size
, prefix
,
13593 (long long) fragP
->fr_address
, branch
,
13594 1 << align_branch_power
);
13596 if (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) == BRANCH_PREFIX
)
13597 memset (fragP
->fr_opcode
,
13598 fragP
->tc_frag_data
.default_prefix
, size
);
13600 i386_generate_nops (fragP
, (char *) fragP
->fr_opcode
,
13602 fragP
->fr_fix
+= size
;
13607 opcode
= (unsigned char *) fragP
->fr_opcode
;
13609 /* Address we want to reach in file space. */
13610 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
13612 /* Address opcode resides at in file space. */
13613 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
13615 /* Displacement from opcode start to fill into instruction. */
13616 displacement_from_opcode_start
= target_address
- opcode_address
;
13618 if ((fragP
->fr_subtype
& BIG
) == 0)
13620 /* Don't have to change opcode. */
13621 extension
= 1; /* 1 opcode + 1 displacement */
13622 where_to_put_displacement
= &opcode
[1];
13626 if (no_cond_jump_promotion
13627 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
13628 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
13629 _("long jump required"));
13631 switch (fragP
->fr_subtype
)
13633 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
13634 extension
= 4; /* 1 opcode + 4 displacement */
13636 where_to_put_displacement
= &opcode
[1];
13639 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
13640 extension
= 2; /* 1 opcode + 2 displacement */
13642 where_to_put_displacement
= &opcode
[1];
13645 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
13646 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
13647 extension
= 5; /* 2 opcode + 4 displacement */
13648 opcode
[1] = opcode
[0] + 0x10;
13649 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13650 where_to_put_displacement
= &opcode
[2];
13653 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
13654 extension
= 3; /* 2 opcode + 2 displacement */
13655 opcode
[1] = opcode
[0] + 0x10;
13656 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
13657 where_to_put_displacement
= &opcode
[2];
13660 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
13665 where_to_put_displacement
= &opcode
[3];
13669 BAD_CASE (fragP
->fr_subtype
);
13674 /* If size if less then four we are sure that the operand fits,
13675 but if it's 4, then it could be that the displacement is larger
13677 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
13679 && ((addressT
) (displacement_from_opcode_start
- extension
13680 + ((addressT
) 1 << 31))
13681 > (((addressT
) 2 << 31) - 1)))
13683 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
13684 _("jump target out of range"));
13685 /* Make us emit 0. */
13686 displacement_from_opcode_start
= extension
;
13688 /* Now put displacement after opcode. */
13689 md_number_to_chars ((char *) where_to_put_displacement
,
13690 (valueT
) (displacement_from_opcode_start
- extension
),
13691 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
13692 fragP
->fr_fix
+= extension
;
13695 /* Apply a fixup (fixP) to segment data, once it has been determined
13696 by our caller that we have all the info we need to fix it up.
13698 Parameter valP is the pointer to the value of the bits.
13700 On the 386, immediates, displacements, and data pointers are all in
13701 the same (little-endian) format, so we don't need to care about which
13702 we are handling. */
13705 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
13707 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
13708 valueT value
= *valP
;
13710 #if !defined (TE_Mach)
13711 if (fixP
->fx_pcrel
)
13713 switch (fixP
->fx_r_type
)
13719 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
13722 case BFD_RELOC_X86_64_32S
:
13723 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
13726 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
13729 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
13734 if (fixP
->fx_addsy
!= NULL
13735 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
13736 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
13737 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
13738 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
13739 && !use_rela_relocations
)
13741 /* This is a hack. There should be a better way to handle this.
13742 This covers for the fact that bfd_install_relocation will
13743 subtract the current location (for partial_inplace, PC relative
13744 relocations); see more below. */
13748 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
13751 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13756 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
13758 if ((sym_seg
== seg
13759 || (symbol_section_p (fixP
->fx_addsy
)
13760 && sym_seg
!= absolute_section
))
13761 && !generic_force_reloc (fixP
))
13763 /* Yes, we add the values in twice. This is because
13764 bfd_install_relocation subtracts them out again. I think
13765 bfd_install_relocation is broken, but I don't dare change
13767 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
13771 #if defined (OBJ_COFF) && defined (TE_PE)
13772 /* For some reason, the PE format does not store a
13773 section address offset for a PC relative symbol. */
13774 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
13775 || S_IS_WEAK (fixP
->fx_addsy
))
13776 value
+= md_pcrel_from (fixP
);
13779 #if defined (OBJ_COFF) && defined (TE_PE)
13780 if (fixP
->fx_addsy
!= NULL
13781 && S_IS_WEAK (fixP
->fx_addsy
)
13782 /* PR 16858: Do not modify weak function references. */
13783 && ! fixP
->fx_pcrel
)
13785 #if !defined (TE_PEP)
13786 /* For x86 PE weak function symbols are neither PC-relative
13787 nor do they set S_IS_FUNCTION. So the only reliable way
13788 to detect them is to check the flags of their containing
13790 if (S_GET_SEGMENT (fixP
->fx_addsy
) != NULL
13791 && S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_CODE
)
13795 value
-= S_GET_VALUE (fixP
->fx_addsy
);
13799 /* Fix a few things - the dynamic linker expects certain values here,
13800 and we must not disappoint it. */
13801 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13802 if (IS_ELF
&& fixP
->fx_addsy
)
13803 switch (fixP
->fx_r_type
)
13805 case BFD_RELOC_386_PLT32
:
13806 case BFD_RELOC_X86_64_PLT32
:
13807 /* Make the jump instruction point to the address of the operand.
13808 At runtime we merely add the offset to the actual PLT entry.
13809 NB: Subtract the offset size only for jump instructions. */
13810 if (fixP
->fx_pcrel
)
13814 case BFD_RELOC_386_TLS_GD
:
13815 case BFD_RELOC_386_TLS_LDM
:
13816 case BFD_RELOC_386_TLS_IE_32
:
13817 case BFD_RELOC_386_TLS_IE
:
13818 case BFD_RELOC_386_TLS_GOTIE
:
13819 case BFD_RELOC_386_TLS_GOTDESC
:
13820 case BFD_RELOC_X86_64_TLSGD
:
13821 case BFD_RELOC_X86_64_TLSLD
:
13822 case BFD_RELOC_X86_64_GOTTPOFF
:
13823 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
13824 value
= 0; /* Fully resolved at runtime. No addend. */
13826 case BFD_RELOC_386_TLS_LE
:
13827 case BFD_RELOC_386_TLS_LDO_32
:
13828 case BFD_RELOC_386_TLS_LE_32
:
13829 case BFD_RELOC_X86_64_DTPOFF32
:
13830 case BFD_RELOC_X86_64_DTPOFF64
:
13831 case BFD_RELOC_X86_64_TPOFF32
:
13832 case BFD_RELOC_X86_64_TPOFF64
:
13833 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13836 case BFD_RELOC_386_TLS_DESC_CALL
:
13837 case BFD_RELOC_X86_64_TLSDESC_CALL
:
13838 value
= 0; /* Fully resolved at runtime. No addend. */
13839 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
13843 case BFD_RELOC_VTABLE_INHERIT
:
13844 case BFD_RELOC_VTABLE_ENTRY
:
13851 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
13853 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13855 value
= extend_to_32bit_address (value
);
13858 #endif /* !defined (TE_Mach) */
13860 /* Are we finished with this relocation now? */
13861 if (fixP
->fx_addsy
== NULL
)
13864 switch (fixP
->fx_r_type
)
13866 case BFD_RELOC_X86_64_32S
:
13867 fixP
->fx_signed
= 1;
13874 #if defined (OBJ_COFF) && defined (TE_PE)
13875 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
13878 /* Remember value for tc_gen_reloc. */
13879 fixP
->fx_addnumber
= value
;
13880 /* Clear out the frag for now. */
13884 else if (use_rela_relocations
)
13886 if (!disallow_64bit_reloc
|| fixP
->fx_r_type
== NO_RELOC
)
13887 fixP
->fx_no_overflow
= 1;
13888 /* Remember value for tc_gen_reloc. */
13889 fixP
->fx_addnumber
= value
;
13893 md_number_to_chars (p
, value
, fixP
->fx_size
);
13897 md_atof (int type
, char *litP
, int *sizeP
)
13899 /* This outputs the LITTLENUMs in REVERSE order;
13900 in accord with the bigendian 386. */
13901 return ieee_md_atof (type
, litP
, sizeP
, false);
13904 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
13907 output_invalid (int c
)
13910 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13913 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
13914 "(0x%x)", (unsigned char) c
);
13915 return output_invalid_buf
;
13918 /* Verify that @r can be used in the current context. */
13920 static bool check_register (const reg_entry
*r
)
13922 if (allow_pseudo_reg
)
13925 if (operand_type_all_zero (&r
->reg_type
))
13928 if ((r
->reg_type
.bitfield
.dword
13929 || (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
> 3)
13930 || r
->reg_type
.bitfield
.class == RegCR
13931 || r
->reg_type
.bitfield
.class == RegDR
)
13932 && !cpu_arch_flags
.bitfield
.cpui386
)
13935 if (r
->reg_type
.bitfield
.class == RegTR
13936 && (flag_code
== CODE_64BIT
13937 || !cpu_arch_flags
.bitfield
.cpui386
13938 || cpu_arch_isa_flags
.bitfield
.cpui586
13939 || cpu_arch_isa_flags
.bitfield
.cpui686
))
13942 if (r
->reg_type
.bitfield
.class == RegMMX
&& !cpu_arch_flags
.bitfield
.cpummx
)
13945 if (!cpu_arch_flags
.bitfield
.cpuavx512f
)
13947 if (r
->reg_type
.bitfield
.zmmword
13948 || r
->reg_type
.bitfield
.class == RegMask
)
13951 if (!cpu_arch_flags
.bitfield
.cpuavx
)
13953 if (r
->reg_type
.bitfield
.ymmword
)
13956 if (!cpu_arch_flags
.bitfield
.cpusse
&& r
->reg_type
.bitfield
.xmmword
)
13961 if (vector_size
< VSZ512
&& r
->reg_type
.bitfield
.zmmword
)
13964 if (vector_size
< VSZ256
&& r
->reg_type
.bitfield
.ymmword
)
13967 if (r
->reg_type
.bitfield
.tmmword
13968 && (!cpu_arch_flags
.bitfield
.cpuamx_tile
13969 || flag_code
!= CODE_64BIT
))
13972 if (r
->reg_type
.bitfield
.class == RegBND
&& !cpu_arch_flags
.bitfield
.cpumpx
)
13975 /* Don't allow fake index register unless allow_index_reg isn't 0. */
13976 if (!allow_index_reg
&& r
->reg_num
== RegIZ
)
13979 /* Upper 16 vector registers are only available with VREX in 64bit
13980 mode, and require EVEX encoding. */
13981 if (r
->reg_flags
& RegVRex
)
13983 if (!cpu_arch_flags
.bitfield
.cpuavx512f
13984 || flag_code
!= CODE_64BIT
)
13987 if (i
.vec_encoding
== vex_encoding_default
)
13988 i
.vec_encoding
= vex_encoding_evex
;
13989 else if (i
.vec_encoding
!= vex_encoding_evex
)
13990 i
.vec_encoding
= vex_encoding_error
;
13993 if (((r
->reg_flags
& (RegRex64
| RegRex
)) || r
->reg_type
.bitfield
.qword
)
13994 && (!cpu_arch_flags
.bitfield
.cpu64
13995 || r
->reg_type
.bitfield
.class != RegCR
13997 && flag_code
!= CODE_64BIT
)
14000 if (r
->reg_type
.bitfield
.class == SReg
&& r
->reg_num
== RegFlat
14007 /* REG_STRING starts *before* REGISTER_PREFIX. */
14009 static const reg_entry
*
14010 parse_real_register (const char *reg_string
, char **end_op
)
14012 const char *s
= reg_string
;
14014 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
14015 const reg_entry
*r
;
14017 /* Skip possible REGISTER_PREFIX and possible whitespace. */
14018 if (*s
== REGISTER_PREFIX
)
14021 if (is_space_char (*s
))
14024 p
= reg_name_given
;
14025 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
14027 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
14028 return (const reg_entry
*) NULL
;
14032 if (is_part_of_name (*s
))
14033 return (const reg_entry
*) NULL
;
14035 *end_op
= (char *) s
;
14037 r
= (const reg_entry
*) str_hash_find (reg_hash
, reg_name_given
);
14039 /* Handle floating point regs, allowing spaces in the (i) part. */
14042 if (!cpu_arch_flags
.bitfield
.cpu8087
14043 && !cpu_arch_flags
.bitfield
.cpu287
14044 && !cpu_arch_flags
.bitfield
.cpu387
14045 && !allow_pseudo_reg
)
14046 return (const reg_entry
*) NULL
;
14048 if (is_space_char (*s
))
14053 if (is_space_char (*s
))
14055 if (*s
>= '0' && *s
<= '7')
14057 int fpr
= *s
- '0';
14059 if (is_space_char (*s
))
14063 *end_op
= (char *) s
+ 1;
14064 know (r
[fpr
].reg_num
== fpr
);
14068 /* We have "%st(" then garbage. */
14069 return (const reg_entry
*) NULL
;
14073 return r
&& check_register (r
) ? r
: NULL
;
14076 /* REG_STRING starts *before* REGISTER_PREFIX. */
14078 static const reg_entry
*
14079 parse_register (const char *reg_string
, char **end_op
)
14081 const reg_entry
*r
;
14083 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
14084 r
= parse_real_register (reg_string
, end_op
);
14089 char *save
= input_line_pointer
;
14090 char *buf
= xstrdup (reg_string
), *name
;
14093 input_line_pointer
= buf
;
14094 get_symbol_name (&name
);
14095 symbolP
= symbol_find (name
);
14096 while (symbolP
&& symbol_equated_p (symbolP
))
14098 const expressionS
*e
= symbol_get_value_expression(symbolP
);
14100 if (e
->X_add_number
)
14102 symbolP
= e
->X_add_symbol
;
14104 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
14106 const expressionS
*e
= symbol_get_value_expression (symbolP
);
14108 if (e
->X_op
== O_register
)
14110 know (e
->X_add_number
>= 0
14111 && (valueT
) e
->X_add_number
< i386_regtab_size
);
14112 r
= i386_regtab
+ e
->X_add_number
;
14113 *end_op
= (char *) reg_string
+ (input_line_pointer
- buf
);
14115 if (r
&& !check_register (r
))
14117 as_bad (_("register '%s%s' cannot be used here"),
14118 register_prefix
, r
->reg_name
);
14122 input_line_pointer
= save
;
14129 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
14131 const reg_entry
*r
= NULL
;
14132 char *end
= input_line_pointer
;
14134 /* We only know the terminating character here. It being double quote could
14135 be the closing one of a quoted symbol name, or an opening one from a
14136 following string (or another quoted symbol name). Since the latter can't
14137 be valid syntax for anything, bailing in either case is good enough. */
14138 if (*nextcharP
== '"')
14142 if (*name
== REGISTER_PREFIX
|| allow_naked_reg
)
14143 r
= parse_real_register (name
, &input_line_pointer
);
14144 if (r
&& end
<= input_line_pointer
)
14146 *nextcharP
= *input_line_pointer
;
14147 *input_line_pointer
= 0;
14148 e
->X_op
= O_register
;
14149 e
->X_add_number
= r
- i386_regtab
;
14152 input_line_pointer
= end
;
14154 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
14158 md_operand (expressionS
*e
)
14161 const reg_entry
*r
;
14163 switch (*input_line_pointer
)
14165 case REGISTER_PREFIX
:
14166 r
= parse_real_register (input_line_pointer
, &end
);
14169 e
->X_op
= O_register
;
14170 e
->X_add_number
= r
- i386_regtab
;
14171 input_line_pointer
= end
;
14176 gas_assert (intel_syntax
);
14177 end
= input_line_pointer
++;
14179 if (*input_line_pointer
== ']')
14181 ++input_line_pointer
;
14182 e
->X_op_symbol
= make_expr_symbol (e
);
14183 e
->X_add_symbol
= NULL
;
14184 e
->X_add_number
= 0;
14189 e
->X_op
= O_absent
;
14190 input_line_pointer
= end
;
14197 /* To maintain consistency with !BFD64 builds of gas record, whether any
14198 (binary) operator was involved in an expression. As expressions are
14199 evaluated in only 32 bits when !BFD64, we use this to decide whether to
14200 truncate results. */
14201 bool i386_record_operator (operatorT op
,
14202 const expressionS
*left
,
14203 const expressionS
*right
)
14205 if (op
== O_absent
)
14210 /* Since the expression parser applies unary operators fine to bignum
14211 operands, we don't need to be concerned of respective operands not
14212 fitting in 32 bits. */
14213 if (right
->X_op
== O_constant
&& right
->X_unsigned
14214 && !fits_in_unsigned_long (right
->X_add_number
))
14217 /* This isn't entirely right: The pattern can also result when constant
14218 expressions are folded (e.g. 0xffffffff + 1). */
14219 else if ((left
->X_op
== O_constant
&& left
->X_unsigned
14220 && !fits_in_unsigned_long (left
->X_add_number
))
14221 || (right
->X_op
== O_constant
&& right
->X_unsigned
14222 && !fits_in_unsigned_long (right
->X_add_number
)))
14223 expr_mode
= expr_large_value
;
14225 if (expr_mode
!= expr_large_value
)
14226 expr_mode
= expr_operator_present
;
14232 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14233 const char *md_shortopts
= "kVQ:sqnO::";
14235 const char *md_shortopts
= "qnO::";
14238 #define OPTION_32 (OPTION_MD_BASE + 0)
14239 #define OPTION_64 (OPTION_MD_BASE + 1)
14240 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
14241 #define OPTION_MARCH (OPTION_MD_BASE + 3)
14242 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
14243 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
14244 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
14245 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
14246 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
14247 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
14248 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
14249 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
14250 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
14251 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
14252 #define OPTION_X32 (OPTION_MD_BASE + 14)
14253 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
14254 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
14255 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
14256 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
14257 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
14258 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
14259 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
14260 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
14261 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
14262 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
14263 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
14264 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
14265 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
14266 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
14267 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
14268 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
14269 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
14270 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
14271 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
14272 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
14274 struct option md_longopts
[] =
14276 {"32", no_argument
, NULL
, OPTION_32
},
14277 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14278 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14279 {"64", no_argument
, NULL
, OPTION_64
},
14281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14282 {"x32", no_argument
, NULL
, OPTION_X32
},
14283 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
14284 {"mx86-used-note", required_argument
, NULL
, OPTION_X86_USED_NOTE
},
14286 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
14287 {"march", required_argument
, NULL
, OPTION_MARCH
},
14288 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
14289 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
14290 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
14291 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
14292 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
14293 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
14294 {"muse-unaligned-vector-move", no_argument
, NULL
, OPTION_MUSE_UNALIGNED_VECTOR_MOVE
},
14295 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
14296 {"moperand-check", required_argument
, NULL
, OPTION_MOPERAND_CHECK
},
14297 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
14298 {"mvexwig", required_argument
, NULL
, OPTION_MVEXWIG
},
14299 {"madd-bnd-prefix", no_argument
, NULL
, OPTION_MADD_BND_PREFIX
},
14300 {"mevexlig", required_argument
, NULL
, OPTION_MEVEXLIG
},
14301 {"mevexwig", required_argument
, NULL
, OPTION_MEVEXWIG
},
14302 # if defined (TE_PE) || defined (TE_PEP)
14303 {"mbig-obj", no_argument
, NULL
, OPTION_MBIG_OBJ
},
14305 {"momit-lock-prefix", required_argument
, NULL
, OPTION_MOMIT_LOCK_PREFIX
},
14306 {"mfence-as-lock-add", required_argument
, NULL
, OPTION_MFENCE_AS_LOCK_ADD
},
14307 {"mrelax-relocations", required_argument
, NULL
, OPTION_MRELAX_RELOCATIONS
},
14308 {"mevexrcig", required_argument
, NULL
, OPTION_MEVEXRCIG
},
14309 {"malign-branch-boundary", required_argument
, NULL
, OPTION_MALIGN_BRANCH_BOUNDARY
},
14310 {"malign-branch-prefix-size", required_argument
, NULL
, OPTION_MALIGN_BRANCH_PREFIX_SIZE
},
14311 {"malign-branch", required_argument
, NULL
, OPTION_MALIGN_BRANCH
},
14312 {"mbranches-within-32B-boundaries", no_argument
, NULL
, OPTION_MBRANCHES_WITH_32B_BOUNDARIES
},
14313 {"mlfence-after-load", required_argument
, NULL
, OPTION_MLFENCE_AFTER_LOAD
},
14314 {"mlfence-before-indirect-branch", required_argument
, NULL
,
14315 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
},
14316 {"mlfence-before-ret", required_argument
, NULL
, OPTION_MLFENCE_BEFORE_RET
},
14317 {"mamd64", no_argument
, NULL
, OPTION_MAMD64
},
14318 {"mintel64", no_argument
, NULL
, OPTION_MINTEL64
},
14319 {NULL
, no_argument
, NULL
, 0}
14321 size_t md_longopts_size
= sizeof (md_longopts
);
14324 md_parse_option (int c
, const char *arg
)
14327 char *arch
, *next
, *saved
, *type
;
14332 optimize_align_code
= 0;
14336 quiet_warnings
= 1;
14339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14340 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
14341 should be emitted or not. FIXME: Not implemented. */
14343 if ((arg
[0] != 'y' && arg
[0] != 'n') || arg
[1])
14347 /* -V: SVR4 argument to print version ID. */
14349 print_version_id ();
14352 /* -k: Ignore for FreeBSD compatibility. */
14357 /* -s: On i386 Solaris, this tells the native assembler to use
14358 .stab instead of .stab.excl. We always use .stab anyhow. */
14361 case OPTION_MSHARED
:
14365 case OPTION_X86_USED_NOTE
:
14366 if (strcasecmp (arg
, "yes") == 0)
14368 else if (strcasecmp (arg
, "no") == 0)
14371 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg
);
14376 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
14377 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
14380 const char **list
, **l
;
14382 list
= bfd_target_list ();
14383 for (l
= list
; *l
!= NULL
; l
++)
14384 if (startswith (*l
, "elf64-x86-64")
14385 || strcmp (*l
, "coff-x86-64") == 0
14386 || strcmp (*l
, "pe-x86-64") == 0
14387 || strcmp (*l
, "pei-x86-64") == 0
14388 || strcmp (*l
, "mach-o-x86-64") == 0)
14390 default_arch
= "x86_64";
14394 as_fatal (_("no compiled in support for x86_64"));
14400 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14404 const char **list
, **l
;
14406 list
= bfd_target_list ();
14407 for (l
= list
; *l
!= NULL
; l
++)
14408 if (startswith (*l
, "elf32-x86-64"))
14410 default_arch
= "x86_64:32";
14414 as_fatal (_("no compiled in support for 32bit x86_64"));
14418 as_fatal (_("32bit x86_64 is only supported for ELF"));
14424 const char **list
, **l
;
14426 list
= bfd_target_list ();
14427 for (l
= list
; *l
!= NULL
; l
++)
14428 if (strstr (*l
, "-i386")
14429 || strstr (*l
, "-go32"))
14431 default_arch
= "i386";
14435 as_fatal (_("no compiled in support for ix86"));
14440 case OPTION_DIVIDE
:
14441 #ifdef SVR4_COMMENT_CHARS
14446 n
= XNEWVEC (char, strlen (i386_comment_chars
) + 1);
14448 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
14452 i386_comment_chars
= n
;
14458 saved
= xstrdup (arg
);
14460 /* Allow -march=+nosse. */
14468 as_fatal (_("invalid -march= option: `%s'"), arg
);
14469 next
= strchr (arch
, '+');
14472 vsz
= strchr (arch
, '/');
14475 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14477 if (vsz
&& cpu_arch
[j
].vsz
!= vsz_set
)
14480 if (arch
== saved
&& cpu_arch
[j
].type
!= PROCESSOR_NONE
14481 && strcmp (arch
, cpu_arch
[j
].name
) == 0)
14484 if (! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14487 cpu_arch_name
= cpu_arch
[j
].name
;
14488 free (cpu_sub_arch_name
);
14489 cpu_sub_arch_name
= NULL
;
14490 cpu_arch_flags
= cpu_arch
[j
].enable
;
14491 cpu_arch_isa
= cpu_arch
[j
].type
;
14492 cpu_arch_isa_flags
= cpu_arch
[j
].enable
;
14493 if (!cpu_arch_tune_set
)
14495 cpu_arch_tune
= cpu_arch_isa
;
14496 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
14498 vector_size
= VSZ_DEFAULT
;
14501 else if (cpu_arch
[j
].type
== PROCESSOR_NONE
14502 && strcmp (arch
, cpu_arch
[j
].name
) == 0
14503 && !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14505 /* ISA extension. */
14506 i386_cpu_flags flags
;
14508 flags
= cpu_flags_or (cpu_arch_flags
,
14509 cpu_arch
[j
].enable
);
14511 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14513 extend_cpu_sub_arch_name (arch
);
14514 cpu_arch_flags
= flags
;
14515 cpu_arch_isa_flags
= flags
;
14519 = cpu_flags_or (cpu_arch_isa_flags
,
14520 cpu_arch
[j
].enable
);
14522 switch (cpu_arch
[j
].vsz
)
14531 unsigned long val
= strtoul (vsz
, &end
, 0);
14537 case 512: vector_size
= VSZ512
; break;
14538 case 256: vector_size
= VSZ256
; break;
14539 case 128: vector_size
= VSZ128
; break;
14541 as_warn (_("Unrecognized vector size specifier ignored"));
14546 /* Fall through. */
14548 vector_size
= VSZ_DEFAULT
;
14556 if (j
>= ARRAY_SIZE (cpu_arch
) && startswith (arch
, "no"))
14558 /* Disable an ISA extension. */
14559 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14560 if (cpu_arch
[j
].type
== PROCESSOR_NONE
14561 && strcmp (arch
+ 2, cpu_arch
[j
].name
) == 0)
14563 i386_cpu_flags flags
;
14565 flags
= cpu_flags_and_not (cpu_arch_flags
,
14566 cpu_arch
[j
].disable
);
14567 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
14569 extend_cpu_sub_arch_name (arch
);
14570 cpu_arch_flags
= flags
;
14571 cpu_arch_isa_flags
= flags
;
14573 if (cpu_arch
[j
].vsz
== vsz_set
)
14574 vector_size
= VSZ_DEFAULT
;
14579 if (j
>= ARRAY_SIZE (cpu_arch
))
14580 as_fatal (_("invalid -march= option: `%s'"), arg
);
14584 while (next
!= NULL
);
14590 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14591 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14593 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
14594 && strcmp (arg
, cpu_arch
[j
].name
) == 0)
14596 cpu_arch_tune_set
= 1;
14597 cpu_arch_tune
= cpu_arch
[j
].type
;
14598 cpu_arch_tune_flags
= cpu_arch
[j
].enable
;
14602 if (j
>= ARRAY_SIZE (cpu_arch
))
14603 as_fatal (_("invalid -mtune= option: `%s'"), arg
);
14606 case OPTION_MMNEMONIC
:
14607 if (strcasecmp (arg
, "att") == 0)
14608 intel_mnemonic
= 0;
14609 else if (strcasecmp (arg
, "intel") == 0)
14610 intel_mnemonic
= 1;
14612 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg
);
14615 case OPTION_MSYNTAX
:
14616 if (strcasecmp (arg
, "att") == 0)
14618 else if (strcasecmp (arg
, "intel") == 0)
14621 as_fatal (_("invalid -msyntax= option: `%s'"), arg
);
14624 case OPTION_MINDEX_REG
:
14625 allow_index_reg
= 1;
14628 case OPTION_MNAKED_REG
:
14629 allow_naked_reg
= 1;
14632 case OPTION_MSSE2AVX
:
14636 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE
:
14637 use_unaligned_vector_move
= 1;
14640 case OPTION_MSSE_CHECK
:
14641 if (strcasecmp (arg
, "error") == 0)
14642 sse_check
= check_error
;
14643 else if (strcasecmp (arg
, "warning") == 0)
14644 sse_check
= check_warning
;
14645 else if (strcasecmp (arg
, "none") == 0)
14646 sse_check
= check_none
;
14648 as_fatal (_("invalid -msse-check= option: `%s'"), arg
);
14651 case OPTION_MOPERAND_CHECK
:
14652 if (strcasecmp (arg
, "error") == 0)
14653 operand_check
= check_error
;
14654 else if (strcasecmp (arg
, "warning") == 0)
14655 operand_check
= check_warning
;
14656 else if (strcasecmp (arg
, "none") == 0)
14657 operand_check
= check_none
;
14659 as_fatal (_("invalid -moperand-check= option: `%s'"), arg
);
14662 case OPTION_MAVXSCALAR
:
14663 if (strcasecmp (arg
, "128") == 0)
14664 avxscalar
= vex128
;
14665 else if (strcasecmp (arg
, "256") == 0)
14666 avxscalar
= vex256
;
14668 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg
);
14671 case OPTION_MVEXWIG
:
14672 if (strcmp (arg
, "0") == 0)
14674 else if (strcmp (arg
, "1") == 0)
14677 as_fatal (_("invalid -mvexwig= option: `%s'"), arg
);
14680 case OPTION_MADD_BND_PREFIX
:
14681 add_bnd_prefix
= 1;
14684 case OPTION_MEVEXLIG
:
14685 if (strcmp (arg
, "128") == 0)
14686 evexlig
= evexl128
;
14687 else if (strcmp (arg
, "256") == 0)
14688 evexlig
= evexl256
;
14689 else if (strcmp (arg
, "512") == 0)
14690 evexlig
= evexl512
;
14692 as_fatal (_("invalid -mevexlig= option: `%s'"), arg
);
14695 case OPTION_MEVEXRCIG
:
14696 if (strcmp (arg
, "rne") == 0)
14698 else if (strcmp (arg
, "rd") == 0)
14700 else if (strcmp (arg
, "ru") == 0)
14702 else if (strcmp (arg
, "rz") == 0)
14705 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg
);
14708 case OPTION_MEVEXWIG
:
14709 if (strcmp (arg
, "0") == 0)
14711 else if (strcmp (arg
, "1") == 0)
14714 as_fatal (_("invalid -mevexwig= option: `%s'"), arg
);
14717 # if defined (TE_PE) || defined (TE_PEP)
14718 case OPTION_MBIG_OBJ
:
14723 case OPTION_MOMIT_LOCK_PREFIX
:
14724 if (strcasecmp (arg
, "yes") == 0)
14725 omit_lock_prefix
= 1;
14726 else if (strcasecmp (arg
, "no") == 0)
14727 omit_lock_prefix
= 0;
14729 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg
);
14732 case OPTION_MFENCE_AS_LOCK_ADD
:
14733 if (strcasecmp (arg
, "yes") == 0)
14735 else if (strcasecmp (arg
, "no") == 0)
14738 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg
);
14741 case OPTION_MLFENCE_AFTER_LOAD
:
14742 if (strcasecmp (arg
, "yes") == 0)
14743 lfence_after_load
= 1;
14744 else if (strcasecmp (arg
, "no") == 0)
14745 lfence_after_load
= 0;
14747 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg
);
14750 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH
:
14751 if (strcasecmp (arg
, "all") == 0)
14753 lfence_before_indirect_branch
= lfence_branch_all
;
14754 if (lfence_before_ret
== lfence_before_ret_none
)
14755 lfence_before_ret
= lfence_before_ret_shl
;
14757 else if (strcasecmp (arg
, "memory") == 0)
14758 lfence_before_indirect_branch
= lfence_branch_memory
;
14759 else if (strcasecmp (arg
, "register") == 0)
14760 lfence_before_indirect_branch
= lfence_branch_register
;
14761 else if (strcasecmp (arg
, "none") == 0)
14762 lfence_before_indirect_branch
= lfence_branch_none
;
14764 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
14768 case OPTION_MLFENCE_BEFORE_RET
:
14769 if (strcasecmp (arg
, "or") == 0)
14770 lfence_before_ret
= lfence_before_ret_or
;
14771 else if (strcasecmp (arg
, "not") == 0)
14772 lfence_before_ret
= lfence_before_ret_not
;
14773 else if (strcasecmp (arg
, "shl") == 0 || strcasecmp (arg
, "yes") == 0)
14774 lfence_before_ret
= lfence_before_ret_shl
;
14775 else if (strcasecmp (arg
, "none") == 0)
14776 lfence_before_ret
= lfence_before_ret_none
;
14778 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
14782 case OPTION_MRELAX_RELOCATIONS
:
14783 if (strcasecmp (arg
, "yes") == 0)
14784 generate_relax_relocations
= 1;
14785 else if (strcasecmp (arg
, "no") == 0)
14786 generate_relax_relocations
= 0;
14788 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg
);
14791 case OPTION_MALIGN_BRANCH_BOUNDARY
:
14794 long int align
= strtoul (arg
, &end
, 0);
14799 align_branch_power
= 0;
14802 else if (align
>= 16)
14805 for (align_power
= 0;
14807 align
>>= 1, align_power
++)
14809 /* Limit alignment power to 31. */
14810 if (align
== 1 && align_power
< 32)
14812 align_branch_power
= align_power
;
14817 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg
);
14821 case OPTION_MALIGN_BRANCH_PREFIX_SIZE
:
14824 int align
= strtoul (arg
, &end
, 0);
14825 /* Some processors only support 5 prefixes. */
14826 if (*end
== '\0' && align
>= 0 && align
< 6)
14828 align_branch_prefix_size
= align
;
14831 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
14836 case OPTION_MALIGN_BRANCH
:
14838 saved
= xstrdup (arg
);
14842 next
= strchr (type
, '+');
14845 if (strcasecmp (type
, "jcc") == 0)
14846 align_branch
|= align_branch_jcc_bit
;
14847 else if (strcasecmp (type
, "fused") == 0)
14848 align_branch
|= align_branch_fused_bit
;
14849 else if (strcasecmp (type
, "jmp") == 0)
14850 align_branch
|= align_branch_jmp_bit
;
14851 else if (strcasecmp (type
, "call") == 0)
14852 align_branch
|= align_branch_call_bit
;
14853 else if (strcasecmp (type
, "ret") == 0)
14854 align_branch
|= align_branch_ret_bit
;
14855 else if (strcasecmp (type
, "indirect") == 0)
14856 align_branch
|= align_branch_indirect_bit
;
14858 as_fatal (_("invalid -malign-branch= option: `%s'"), arg
);
14861 while (next
!= NULL
);
14865 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES
:
14866 align_branch_power
= 5;
14867 align_branch_prefix_size
= 5;
14868 align_branch
= (align_branch_jcc_bit
14869 | align_branch_fused_bit
14870 | align_branch_jmp_bit
);
14873 case OPTION_MAMD64
:
14877 case OPTION_MINTEL64
:
14885 /* Turn off -Os. */
14886 optimize_for_space
= 0;
14888 else if (*arg
== 's')
14890 optimize_for_space
= 1;
14891 /* Turn on all encoding optimizations. */
14892 optimize
= INT_MAX
;
14896 optimize
= atoi (arg
);
14897 /* Turn off -Os. */
14898 optimize_for_space
= 0;
14908 #define MESSAGE_TEMPLATE \
14912 output_message (FILE *stream
, char *p
, char *message
, char *start
,
14913 int *left_p
, const char *name
, int len
)
14915 int size
= sizeof (MESSAGE_TEMPLATE
);
14916 int left
= *left_p
;
14918 /* Reserve 2 spaces for ", " or ",\0" */
14921 /* Check if there is any room. */
14929 p
= mempcpy (p
, name
, len
);
14933 /* Output the current message now and start a new one. */
14936 fprintf (stream
, "%s\n", message
);
14938 left
= size
- (start
- message
) - len
- 2;
14940 gas_assert (left
>= 0);
14942 p
= mempcpy (p
, name
, len
);
14950 show_arch (FILE *stream
, int ext
, int check
)
14952 static char message
[] = MESSAGE_TEMPLATE
;
14953 char *start
= message
+ 27;
14955 int size
= sizeof (MESSAGE_TEMPLATE
);
14962 left
= size
- (start
- message
);
14966 p
= output_message (stream
, p
, message
, start
, &left
,
14967 STRING_COMMA_LEN ("default"));
14968 p
= output_message (stream
, p
, message
, start
, &left
,
14969 STRING_COMMA_LEN ("push"));
14970 p
= output_message (stream
, p
, message
, start
, &left
,
14971 STRING_COMMA_LEN ("pop"));
14974 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
14976 /* Should it be skipped? */
14977 if (cpu_arch
[j
].skip
)
14980 name
= cpu_arch
[j
].name
;
14981 len
= cpu_arch
[j
].len
;
14982 if (cpu_arch
[j
].type
== PROCESSOR_NONE
)
14984 /* It is an extension. Skip if we aren't asked to show it. */
14985 if (!ext
|| cpu_flags_all_zero (&cpu_arch
[j
].enable
))
14990 /* It is an processor. Skip if we show only extension. */
14993 else if (check
&& ! cpu_arch
[j
].enable
.bitfield
.cpui386
)
14995 /* It is an impossible processor - skip. */
14999 p
= output_message (stream
, p
, message
, start
, &left
, name
, len
);
15002 /* Display disabled extensions. */
15004 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
15008 if (cpu_arch
[j
].type
!= PROCESSOR_NONE
15009 || !cpu_flags_all_zero (&cpu_arch
[j
].enable
))
15011 str
= xasprintf ("no%s", cpu_arch
[j
].name
);
15012 p
= output_message (stream
, p
, message
, start
, &left
, str
,
15018 fprintf (stream
, "%s\n", message
);
15022 md_show_usage (FILE *stream
)
15024 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15025 fprintf (stream
, _("\
15026 -Qy, -Qn ignored\n\
15027 -V print assembler version number\n\
15030 fprintf (stream
, _("\
15031 -n do not optimize code alignment\n\
15032 -O{012s} attempt some code optimizations\n\
15033 -q quieten some warnings\n"));
15034 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15035 fprintf (stream
, _("\
15039 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15040 fprintf (stream
, _("\
15041 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
15042 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
15043 fprintf (stream
, _("\
15044 --32/--64 generate 32bit/64bit object\n"));
15047 #ifdef SVR4_COMMENT_CHARS
15048 fprintf (stream
, _("\
15049 --divide do not treat `/' as a comment character\n"));
15051 fprintf (stream
, _("\
15052 --divide ignored\n"));
15054 fprintf (stream
, _("\
15055 -march=CPU[,+EXTENSION...]\n\
15056 generate code for CPU and EXTENSION, CPU is one of:\n"));
15057 show_arch (stream
, 0, 1);
15058 fprintf (stream
, _("\
15059 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
15060 show_arch (stream
, 1, 0);
15061 fprintf (stream
, _("\
15062 -mtune=CPU optimize for CPU, CPU is one of:\n"));
15063 show_arch (stream
, 0, 0);
15064 fprintf (stream
, _("\
15065 -msse2avx encode SSE instructions with VEX prefix\n"));
15066 fprintf (stream
, _("\
15067 -muse-unaligned-vector-move\n\
15068 encode aligned vector move as unaligned vector move\n"));
15069 fprintf (stream
, _("\
15070 -msse-check=[none|error|warning] (default: warning)\n\
15071 check SSE instructions\n"));
15072 fprintf (stream
, _("\
15073 -moperand-check=[none|error|warning] (default: warning)\n\
15074 check operand combinations for validity\n"));
15075 fprintf (stream
, _("\
15076 -mavxscalar=[128|256] (default: 128)\n\
15077 encode scalar AVX instructions with specific vector\n\
15079 fprintf (stream
, _("\
15080 -mvexwig=[0|1] (default: 0)\n\
15081 encode VEX instructions with specific VEX.W value\n\
15082 for VEX.W bit ignored instructions\n"));
15083 fprintf (stream
, _("\
15084 -mevexlig=[128|256|512] (default: 128)\n\
15085 encode scalar EVEX instructions with specific vector\n\
15087 fprintf (stream
, _("\
15088 -mevexwig=[0|1] (default: 0)\n\
15089 encode EVEX instructions with specific EVEX.W value\n\
15090 for EVEX.W bit ignored instructions\n"));
15091 fprintf (stream
, _("\
15092 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
15093 encode EVEX instructions with specific EVEX.RC value\n\
15094 for SAE-only ignored instructions\n"));
15095 fprintf (stream
, _("\
15096 -mmnemonic=[att|intel] "));
15097 if (SYSV386_COMPAT
)
15098 fprintf (stream
, _("(default: att)\n"));
15100 fprintf (stream
, _("(default: intel)\n"));
15101 fprintf (stream
, _("\
15102 use AT&T/Intel mnemonic\n"));
15103 fprintf (stream
, _("\
15104 -msyntax=[att|intel] (default: att)\n\
15105 use AT&T/Intel syntax\n"));
15106 fprintf (stream
, _("\
15107 -mindex-reg support pseudo index registers\n"));
15108 fprintf (stream
, _("\
15109 -mnaked-reg don't require `%%' prefix for registers\n"));
15110 fprintf (stream
, _("\
15111 -madd-bnd-prefix add BND prefix for all valid branches\n"));
15112 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15113 fprintf (stream
, _("\
15114 -mshared disable branch optimization for shared code\n"));
15115 fprintf (stream
, _("\
15116 -mx86-used-note=[no|yes] "));
15117 if (DEFAULT_X86_USED_NOTE
)
15118 fprintf (stream
, _("(default: yes)\n"));
15120 fprintf (stream
, _("(default: no)\n"));
15121 fprintf (stream
, _("\
15122 generate x86 used ISA and feature properties\n"));
15124 #if defined (TE_PE) || defined (TE_PEP)
15125 fprintf (stream
, _("\
15126 -mbig-obj generate big object files\n"));
15128 fprintf (stream
, _("\
15129 -momit-lock-prefix=[no|yes] (default: no)\n\
15130 strip all lock prefixes\n"));
15131 fprintf (stream
, _("\
15132 -mfence-as-lock-add=[no|yes] (default: no)\n\
15133 encode lfence, mfence and sfence as\n\
15134 lock addl $0x0, (%%{re}sp)\n"));
15135 fprintf (stream
, _("\
15136 -mrelax-relocations=[no|yes] "));
15137 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS
)
15138 fprintf (stream
, _("(default: yes)\n"));
15140 fprintf (stream
, _("(default: no)\n"));
15141 fprintf (stream
, _("\
15142 generate relax relocations\n"));
15143 fprintf (stream
, _("\
15144 -malign-branch-boundary=NUM (default: 0)\n\
15145 align branches within NUM byte boundary\n"));
15146 fprintf (stream
, _("\
15147 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
15148 TYPE is combination of jcc, fused, jmp, call, ret,\n\
15150 specify types of branches to align\n"));
15151 fprintf (stream
, _("\
15152 -malign-branch-prefix-size=NUM (default: 5)\n\
15153 align branches with NUM prefixes per instruction\n"));
15154 fprintf (stream
, _("\
15155 -mbranches-within-32B-boundaries\n\
15156 align branches within 32 byte boundary\n"));
15157 fprintf (stream
, _("\
15158 -mlfence-after-load=[no|yes] (default: no)\n\
15159 generate lfence after load\n"));
15160 fprintf (stream
, _("\
15161 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
15162 generate lfence before indirect near branch\n"));
15163 fprintf (stream
, _("\
15164 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
15165 generate lfence before ret\n"));
15166 fprintf (stream
, _("\
15167 -mamd64 accept only AMD64 ISA [default]\n"));
15168 fprintf (stream
, _("\
15169 -mintel64 accept only Intel64 ISA\n"));
15172 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
15173 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15174 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15176 /* Pick the target format to use. */
15179 i386_target_format (void)
15181 if (startswith (default_arch
, "x86_64"))
15183 update_code_flag (CODE_64BIT
, 1);
15184 if (default_arch
[6] == '\0')
15185 x86_elf_abi
= X86_64_ABI
;
15187 x86_elf_abi
= X86_64_X32_ABI
;
15189 else if (!strcmp (default_arch
, "i386"))
15190 update_code_flag (CODE_32BIT
, 1);
15191 else if (!strcmp (default_arch
, "iamcu"))
15193 update_code_flag (CODE_32BIT
, 1);
15194 if (cpu_arch_isa
== PROCESSOR_UNKNOWN
)
15196 static const i386_cpu_flags iamcu_flags
= CPU_IAMCU_FLAGS
;
15197 cpu_arch_name
= "iamcu";
15198 free (cpu_sub_arch_name
);
15199 cpu_sub_arch_name
= NULL
;
15200 cpu_arch_flags
= iamcu_flags
;
15201 cpu_arch_isa
= PROCESSOR_IAMCU
;
15202 cpu_arch_isa_flags
= iamcu_flags
;
15203 if (!cpu_arch_tune_set
)
15205 cpu_arch_tune
= cpu_arch_isa
;
15206 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
15209 else if (cpu_arch_isa
!= PROCESSOR_IAMCU
)
15210 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
15214 as_fatal (_("unknown architecture"));
15216 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
15217 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15218 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
15219 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].enable
;
15221 switch (OUTPUT_FLAVOR
)
15223 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
15224 case bfd_target_aout_flavour
:
15225 return AOUT_TARGET_FORMAT
;
15227 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
15228 # if defined (TE_PE) || defined (TE_PEP)
15229 case bfd_target_coff_flavour
:
15230 if (flag_code
== CODE_64BIT
)
15233 return use_big_obj
? "pe-bigobj-x86-64" : "pe-x86-64";
15235 return use_big_obj
? "pe-bigobj-i386" : "pe-i386";
15236 # elif defined (TE_GO32)
15237 case bfd_target_coff_flavour
:
15238 return "coff-go32";
15240 case bfd_target_coff_flavour
:
15241 return "coff-i386";
15244 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15245 case bfd_target_elf_flavour
:
15247 const char *format
;
15249 switch (x86_elf_abi
)
15252 format
= ELF_TARGET_FORMAT
;
15254 tls_get_addr
= "___tls_get_addr";
15258 use_rela_relocations
= 1;
15261 tls_get_addr
= "__tls_get_addr";
15263 format
= ELF_TARGET_FORMAT64
;
15265 case X86_64_X32_ABI
:
15266 use_rela_relocations
= 1;
15269 tls_get_addr
= "__tls_get_addr";
15271 disallow_64bit_reloc
= 1;
15272 format
= ELF_TARGET_FORMAT32
;
15275 if (cpu_arch_isa
== PROCESSOR_IAMCU
)
15277 if (x86_elf_abi
!= I386_ABI
)
15278 as_fatal (_("Intel MCU is 32bit only"));
15279 return ELF_TARGET_IAMCU_FORMAT
;
15285 #if defined (OBJ_MACH_O)
15286 case bfd_target_mach_o_flavour
:
15287 if (flag_code
== CODE_64BIT
)
15289 use_rela_relocations
= 1;
15291 return "mach-o-x86-64";
15294 return "mach-o-i386";
15302 #endif /* OBJ_MAYBE_ more than one */
15305 md_undefined_symbol (char *name
)
15307 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
15308 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
15309 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
15310 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
15314 if (symbol_find (name
))
15315 as_bad (_("GOT already in symbol table"));
15316 GOT_symbol
= symbol_new (name
, undefined_section
,
15317 &zero_address_frag
, 0);
15324 /* Round up a section size to the appropriate boundary. */
15327 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
15329 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
15330 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
15332 /* For a.out, force the section size to be aligned. If we don't do
15333 this, BFD will align it for us, but it will not write out the
15334 final bytes of the section. This may be a bug in BFD, but it is
15335 easier to fix it here since that is how the other a.out targets
15339 align
= bfd_section_alignment (segment
);
15340 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
15347 /* On the i386, PC-relative offsets are relative to the start of the
15348 next instruction. That is, the address of the offset, plus its
15349 size, since the offset is always the last part of the insn. */
15352 md_pcrel_from (fixS
*fixP
)
15354 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15360 s_bss (int ignore ATTRIBUTE_UNUSED
)
15364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15366 obj_elf_section_change_hook ();
15368 temp
= get_absolute_expression ();
15369 subseg_set (bss_section
, (subsegT
) temp
);
15370 demand_empty_rest_of_line ();
15375 /* Remember constant directive. */
15378 i386_cons_align (int ignore ATTRIBUTE_UNUSED
)
15380 if (last_insn
.kind
!= last_insn_directive
15381 && (bfd_section_flags (now_seg
) & SEC_CODE
))
15383 last_insn
.seg
= now_seg
;
15384 last_insn
.kind
= last_insn_directive
;
15385 last_insn
.name
= "constant directive";
15386 last_insn
.file
= as_where (&last_insn
.line
);
15387 if (lfence_before_ret
!= lfence_before_ret_none
)
15389 if (lfence_before_indirect_branch
!= lfence_branch_none
)
15390 as_warn (_("constant directive skips -mlfence-before-ret "
15391 "and -mlfence-before-indirect-branch"));
15393 as_warn (_("constant directive skips -mlfence-before-ret"));
15395 else if (lfence_before_indirect_branch
!= lfence_branch_none
)
15396 as_warn (_("constant directive skips -mlfence-before-indirect-branch"));
15401 i386_validate_fix (fixS
*fixp
)
15403 if (fixp
->fx_addsy
&& S_GET_SEGMENT(fixp
->fx_addsy
) == reg_section
)
15405 reloc_howto_type
*howto
;
15407 howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
15408 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15409 _("invalid %s relocation against register"),
15410 howto
? howto
->name
: "<unknown>");
15414 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15415 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15416 || fixp
->fx_r_type
== BFD_RELOC_SIZE64
)
15417 return IS_ELF
&& fixp
->fx_addsy
15418 && (!S_IS_DEFINED (fixp
->fx_addsy
)
15419 || S_IS_EXTERNAL (fixp
->fx_addsy
));
15422 if (fixp
->fx_subsy
)
15424 if (fixp
->fx_subsy
== GOT_symbol
)
15426 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
15430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15431 if (fixp
->fx_tcbit2
)
15432 fixp
->fx_r_type
= (fixp
->fx_tcbit
15433 ? BFD_RELOC_X86_64_REX_GOTPCRELX
15434 : BFD_RELOC_X86_64_GOTPCRELX
);
15437 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
15442 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
15444 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
15446 fixp
->fx_subsy
= 0;
15449 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15452 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
15453 to section. Since PLT32 relocation must be against symbols,
15454 turn such PLT32 relocation into PC32 relocation. */
15456 && (fixp
->fx_r_type
== BFD_RELOC_386_PLT32
15457 || fixp
->fx_r_type
== BFD_RELOC_X86_64_PLT32
)
15458 && symbol_section_p (fixp
->fx_addsy
))
15459 fixp
->fx_r_type
= BFD_RELOC_32_PCREL
;
15462 if (fixp
->fx_r_type
== BFD_RELOC_386_GOT32
15463 && fixp
->fx_tcbit2
)
15464 fixp
->fx_r_type
= BFD_RELOC_386_GOT32X
;
15473 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
15476 bfd_reloc_code_real_type code
;
15478 switch (fixp
->fx_r_type
)
15480 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15483 case BFD_RELOC_SIZE32
:
15484 case BFD_RELOC_SIZE64
:
15486 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))
15487 && (!fixp
->fx_subsy
15488 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))))
15489 sym
= fixp
->fx_addsy
;
15490 else if (fixp
->fx_subsy
15491 && !bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_subsy
))
15492 && (!fixp
->fx_addsy
15493 || bfd_is_abs_section (S_GET_SEGMENT (fixp
->fx_addsy
))))
15494 sym
= fixp
->fx_subsy
;
15497 if (IS_ELF
&& sym
&& S_IS_DEFINED (sym
) && !S_IS_EXTERNAL (sym
))
15499 /* Resolve size relocation against local symbol to size of
15500 the symbol plus addend. */
15501 valueT value
= S_GET_SIZE (sym
);
15503 if (symbol_get_bfdsym (sym
)->flags
& BSF_SECTION_SYM
)
15504 value
= bfd_section_size (S_GET_SEGMENT (sym
));
15505 if (sym
== fixp
->fx_subsy
)
15508 if (fixp
->fx_addsy
)
15509 value
+= S_GET_VALUE (fixp
->fx_addsy
);
15511 else if (fixp
->fx_subsy
)
15512 value
-= S_GET_VALUE (fixp
->fx_subsy
);
15513 value
+= fixp
->fx_offset
;
15514 if (fixp
->fx_r_type
== BFD_RELOC_SIZE32
15516 && !fits_in_unsigned_long (value
))
15517 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15518 _("symbol size computation overflow"));
15519 fixp
->fx_addsy
= NULL
;
15520 fixp
->fx_subsy
= NULL
;
15521 md_apply_fix (fixp
, (valueT
*) &value
, NULL
);
15524 if (!fixp
->fx_addsy
|| fixp
->fx_subsy
)
15526 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15527 "unsupported expression involving @size");
15531 /* Fall through. */
15533 case BFD_RELOC_X86_64_PLT32
:
15534 case BFD_RELOC_X86_64_GOT32
:
15535 case BFD_RELOC_X86_64_GOTPCREL
:
15536 case BFD_RELOC_X86_64_GOTPCRELX
:
15537 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15538 case BFD_RELOC_386_PLT32
:
15539 case BFD_RELOC_386_GOT32
:
15540 case BFD_RELOC_386_GOT32X
:
15541 case BFD_RELOC_386_GOTOFF
:
15542 case BFD_RELOC_386_GOTPC
:
15543 case BFD_RELOC_386_TLS_GD
:
15544 case BFD_RELOC_386_TLS_LDM
:
15545 case BFD_RELOC_386_TLS_LDO_32
:
15546 case BFD_RELOC_386_TLS_IE_32
:
15547 case BFD_RELOC_386_TLS_IE
:
15548 case BFD_RELOC_386_TLS_GOTIE
:
15549 case BFD_RELOC_386_TLS_LE_32
:
15550 case BFD_RELOC_386_TLS_LE
:
15551 case BFD_RELOC_386_TLS_GOTDESC
:
15552 case BFD_RELOC_386_TLS_DESC_CALL
:
15553 case BFD_RELOC_X86_64_TLSGD
:
15554 case BFD_RELOC_X86_64_TLSLD
:
15555 case BFD_RELOC_X86_64_DTPOFF32
:
15556 case BFD_RELOC_X86_64_DTPOFF64
:
15557 case BFD_RELOC_X86_64_GOTTPOFF
:
15558 case BFD_RELOC_X86_64_TPOFF32
:
15559 case BFD_RELOC_X86_64_TPOFF64
:
15560 case BFD_RELOC_X86_64_GOTOFF64
:
15561 case BFD_RELOC_X86_64_GOTPC32
:
15562 case BFD_RELOC_X86_64_GOT64
:
15563 case BFD_RELOC_X86_64_GOTPCREL64
:
15564 case BFD_RELOC_X86_64_GOTPC64
:
15565 case BFD_RELOC_X86_64_GOTPLT64
:
15566 case BFD_RELOC_X86_64_PLTOFF64
:
15567 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15568 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15569 case BFD_RELOC_RVA
:
15570 case BFD_RELOC_VTABLE_ENTRY
:
15571 case BFD_RELOC_VTABLE_INHERIT
:
15573 case BFD_RELOC_32_SECREL
:
15574 case BFD_RELOC_16_SECIDX
:
15576 code
= fixp
->fx_r_type
;
15578 case BFD_RELOC_X86_64_32S
:
15579 if (!fixp
->fx_pcrel
)
15581 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
15582 code
= fixp
->fx_r_type
;
15585 /* Fall through. */
15587 if (fixp
->fx_pcrel
)
15589 switch (fixp
->fx_size
)
15592 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15593 _("can not do %d byte pc-relative relocation"),
15595 code
= BFD_RELOC_32_PCREL
;
15597 case 1: code
= BFD_RELOC_8_PCREL
; break;
15598 case 2: code
= BFD_RELOC_16_PCREL
; break;
15599 case 4: code
= BFD_RELOC_32_PCREL
; break;
15601 case 8: code
= BFD_RELOC_64_PCREL
; break;
15607 switch (fixp
->fx_size
)
15610 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15611 _("can not do %d byte relocation"),
15613 code
= BFD_RELOC_32
;
15615 case 1: code
= BFD_RELOC_8
; break;
15616 case 2: code
= BFD_RELOC_16
; break;
15617 case 4: code
= BFD_RELOC_32
; break;
15619 case 8: code
= BFD_RELOC_64
; break;
15626 if ((code
== BFD_RELOC_32
15627 || code
== BFD_RELOC_32_PCREL
15628 || code
== BFD_RELOC_X86_64_32S
)
15630 && fixp
->fx_addsy
== GOT_symbol
)
15633 code
= BFD_RELOC_386_GOTPC
;
15635 code
= BFD_RELOC_X86_64_GOTPC32
;
15637 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
15639 && fixp
->fx_addsy
== GOT_symbol
)
15641 code
= BFD_RELOC_X86_64_GOTPC64
;
15644 rel
= XNEW (arelent
);
15645 rel
->sym_ptr_ptr
= XNEW (asymbol
*);
15646 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
15648 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
15650 if (!use_rela_relocations
)
15652 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
15653 vtable entry to be used in the relocation's section offset. */
15654 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
15655 rel
->address
= fixp
->fx_offset
;
15656 #if defined (OBJ_COFF) && defined (TE_PE)
15657 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
15658 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
15663 /* Use the rela in 64bit mode. */
15666 if (disallow_64bit_reloc
)
15669 case BFD_RELOC_X86_64_DTPOFF64
:
15670 case BFD_RELOC_X86_64_TPOFF64
:
15671 case BFD_RELOC_64_PCREL
:
15672 case BFD_RELOC_X86_64_GOTOFF64
:
15673 case BFD_RELOC_X86_64_GOT64
:
15674 case BFD_RELOC_X86_64_GOTPCREL64
:
15675 case BFD_RELOC_X86_64_GOTPC64
:
15676 case BFD_RELOC_X86_64_GOTPLT64
:
15677 case BFD_RELOC_X86_64_PLTOFF64
:
15678 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15679 _("cannot represent relocation type %s in x32 mode"),
15680 bfd_get_reloc_code_name (code
));
15686 if (!fixp
->fx_pcrel
)
15687 rel
->addend
= fixp
->fx_offset
;
15691 case BFD_RELOC_X86_64_PLT32
:
15692 case BFD_RELOC_X86_64_GOT32
:
15693 case BFD_RELOC_X86_64_GOTPCREL
:
15694 case BFD_RELOC_X86_64_GOTPCRELX
:
15695 case BFD_RELOC_X86_64_REX_GOTPCRELX
:
15696 case BFD_RELOC_X86_64_TLSGD
:
15697 case BFD_RELOC_X86_64_TLSLD
:
15698 case BFD_RELOC_X86_64_GOTTPOFF
:
15699 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
15700 case BFD_RELOC_X86_64_TLSDESC_CALL
:
15701 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
15704 rel
->addend
= (section
->vma
15706 + fixp
->fx_addnumber
15707 + md_pcrel_from (fixp
));
15712 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
15713 if (rel
->howto
== NULL
)
15715 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
15716 _("cannot represent relocation type %s"),
15717 bfd_get_reloc_code_name (code
));
15718 /* Set howto to a garbage value so that we can keep going. */
15719 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
15720 gas_assert (rel
->howto
!= NULL
);
15726 #include "tc-i386-intel.c"
15729 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
15731 int saved_naked_reg
;
15732 char saved_register_dot
;
15734 saved_naked_reg
= allow_naked_reg
;
15735 allow_naked_reg
= 1;
15736 saved_register_dot
= register_chars
['.'];
15737 register_chars
['.'] = '.';
15738 allow_pseudo_reg
= 1;
15739 expression_and_evaluate (exp
);
15740 allow_pseudo_reg
= 0;
15741 register_chars
['.'] = saved_register_dot
;
15742 allow_naked_reg
= saved_naked_reg
;
15744 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
15746 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
15748 exp
->X_op
= O_constant
;
15749 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
15750 .dw2_regnum
[flag_code
>> 1];
15753 exp
->X_op
= O_illegal
;
15758 tc_x86_frame_initial_instructions (void)
15760 static unsigned int sp_regno
[2];
15762 if (!sp_regno
[flag_code
>> 1])
15764 char *saved_input
= input_line_pointer
;
15765 char sp
[][4] = {"esp", "rsp"};
15768 input_line_pointer
= sp
[flag_code
>> 1];
15769 tc_x86_parse_to_dw2regnum (&exp
);
15770 gas_assert (exp
.X_op
== O_constant
);
15771 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
15772 input_line_pointer
= saved_input
;
15775 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
15776 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
15780 x86_dwarf2_addr_size (void)
15782 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
15783 if (x86_elf_abi
== X86_64_X32_ABI
)
15786 return bfd_arch_bits_per_address (stdoutput
) / 8;
15790 i386_elf_section_type (const char *str
, size_t len
)
15792 if (flag_code
== CODE_64BIT
15793 && len
== sizeof ("unwind") - 1
15794 && startswith (str
, "unwind"))
15795 return SHT_X86_64_UNWIND
;
15802 i386_solaris_fix_up_eh_frame (segT sec
)
15804 if (flag_code
== CODE_64BIT
)
15805 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
15811 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
15815 exp
.X_op
= O_secrel
;
15816 exp
.X_add_symbol
= symbol
;
15817 exp
.X_add_number
= 0;
15818 emit_expr (&exp
, size
);
15822 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15823 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
15826 x86_64_section_letter (int letter
, const char **ptr_msg
)
15828 if (flag_code
== CODE_64BIT
)
15831 return SHF_X86_64_LARGE
;
15833 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
15836 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
15841 handle_large_common (int small ATTRIBUTE_UNUSED
)
15843 if (flag_code
!= CODE_64BIT
)
15845 s_comm_internal (0, elf_common_parse
);
15846 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
15850 static segT lbss_section
;
15851 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
15852 asection
*saved_bss_section
= bss_section
;
15854 if (lbss_section
== NULL
)
15856 flagword applicable
;
15857 segT seg
= now_seg
;
15858 subsegT subseg
= now_subseg
;
15860 /* The .lbss section is for local .largecomm symbols. */
15861 lbss_section
= subseg_new (".lbss", 0);
15862 applicable
= bfd_applicable_section_flags (stdoutput
);
15863 bfd_set_section_flags (lbss_section
, applicable
& SEC_ALLOC
);
15864 seg_info (lbss_section
)->bss
= 1;
15866 subseg_set (seg
, subseg
);
15869 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
15870 bss_section
= lbss_section
;
15872 s_comm_internal (0, elf_common_parse
);
15874 elf_com_section_ptr
= saved_com_section_ptr
;
15875 bss_section
= saved_bss_section
;
15878 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */