gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
   3    Free Software Foundation.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #ifndef TC_I386
  23 #define TC_I386 1
  24
  25 #ifdef ANSI_PROTOTYPES
  26 struct fix;
  27 #endif
  28
  29 #define TARGET_BYTES_BIG_ENDIAN 0
  30
  31 #ifdef TE_LYNX
  32 #define TARGET_FORMAT           "coff-i386-lynx"
  33 #endif
  34
  35 #ifdef BFD_ASSEMBLER
  36 /* This is used to determine relocation types in tc-i386.c.  The first
  37    parameter is the current relocation type, the second one is the desired
  38    type.  The idea is that if the original type is already some kind of PIC
  39    relocation, we leave it alone, otherwise we give it the desired type */
  40
  41 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
  42 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
  43
  44 #if defined (OBJ_ELF) || defined (OBJ_COFF) || defined (TE_PE)
  45 /* This arranges for gas/write.c to not apply a relocation if
  46    tc_fix_adjustable() says it is not adjustable.  */
  47 #define TC_FIX_ADJUSTABLE(fixP) tc_fix_adjustable (fixP)
  48 #endif
  49
  50 /* This is the relocation type for direct references to GLOBAL_OFFSET_TABLE.
  51  * It comes up in complicated expressions such as
  52  * _GLOBAL_OFFSET_TABLE_+[.-.L284], which cannot be expressed normally with
  53  * the regular expressions.  The fixup specified here when used at runtime
  54  * implies that we should add the address of the GOT to the specified location,
  55  * and as a result we have simplified the expression into something we can use.
  56  */
  57 #define TC_RELOC_GLOBAL_OFFSET_TABLE BFD_RELOC_386_GOTPC
  58
  59 /* This expression evaluates to false if the relocation is for a local object
  60    for which we still want to do the relocation at runtime.  True if we
  61    are willing to perform this relocation while building the .o file.
  62    This is only used for pcrel relocations, so GOTOFF does not need to be
  63    checked here.  I am not sure if some of the others are ever used with
  64    pcrel, but it is easier to be safe than sorry. */
  65
  66 #define TC_RELOC_RTSYM_LOC_FIXUP(FIX)                           \
  67   ((FIX)->fx_r_type != BFD_RELOC_386_PLT32                      \
  68    && (FIX)->fx_r_type != BFD_RELOC_386_GOT32                   \
  69    && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC                   \
  70    && ((FIX)->fx_addsy == NULL                                  \
  71        || (! S_IS_EXTERNAL ((FIX)->fx_addsy)                    \
  72            && ! S_IS_WEAK ((FIX)->fx_addsy)                     \
  73            && S_IS_DEFINED ((FIX)->fx_addsy)                    \
  74            && ! S_IS_COMMON ((FIX)->fx_addsy))))
  75
  76 #define TARGET_ARCH             bfd_arch_i386
  77
  78 #ifdef TE_NetBSD
  79 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  80 #endif
  81 #ifdef TE_386BSD
  82 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  83 #endif
  84 #ifdef TE_LINUX
  85 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  86 #endif
  87 #ifdef TE_Mach
  88 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  89 #endif
  90 #ifdef TE_DYNIX
  91 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  92 #endif
  93 #ifndef AOUT_TARGET_FORMAT
  94 #define AOUT_TARGET_FORMAT      "a.out-i386"
  95 #endif
  96
  97 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
  98      || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
  99      || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
 100 extern const char *i386_target_format PARAMS ((void));
 101 #define TARGET_FORMAT i386_target_format ()
 102 #else
 103 #ifdef OBJ_ELF
 104 #define TARGET_FORMAT           "elf32-i386"
 105 #endif
 106 #ifdef OBJ_AOUT
 107 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
 108 #endif
 109 #endif
 110
 111 #else /* ! BFD_ASSEMBLER */
 112
 113 /* COFF STUFF */
 114
 115 #define COFF_MAGIC I386MAGIC
 116 #define BFD_ARCH bfd_arch_i386
 117 #define COFF_FLAGS F_AR32WR
 118 #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
 119 #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
 120 extern short tc_coff_fix2rtype PARAMS ((struct fix *));
 121 #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
 122 extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
 123
 124 #ifdef TE_GO32
 125 /* DJGPP now expects some sections to be 2**4 aligned.  */
 126 #define SUB_SEGMENT_ALIGN(SEG)                                          \
 127   ((strcmp (obj_segment_name (SEG), ".text") == 0                       \
 128     || strcmp (obj_segment_name (SEG), ".data") == 0                    \
 129     || strcmp (obj_segment_name (SEG), ".bss") == 0                     \
 130     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0     \
 131     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0     \
 132     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0)    \
 133    ? 4                                                                  \
 134    : 2)
 135 #else
 136 #define SUB_SEGMENT_ALIGN(SEG) 2
 137 #endif
 138
 139 #define TC_RVA_RELOC 7
 140 /* Need this for PIC relocations */
 141 #define NEED_FX_R_TYPE
 142
 143
 144 #ifdef TE_386BSD
 145 /* The BSDI linker apparently rejects objects with a machine type of
 146    M_386 (100).  */
 147 #define AOUT_MACHTYPE 0
 148 #else
 149 #define AOUT_MACHTYPE 100
 150 #endif
 151
 152 #undef REVERSE_SORT_RELOCS
 153
 154 #endif /* ! BFD_ASSEMBLER */
 155
 156 #define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
 157 extern int tc_i386_force_relocation PARAMS ((struct fix *));
 158
 159 #ifdef BFD_ASSEMBLER
 160 #define NO_RELOC BFD_RELOC_NONE
 161 #else
 162 #define NO_RELOC 0
 163 #endif
 164 #define tc_coff_symbol_emit_hook(a)     ;       /* not used */
 165
 166 #ifndef BFD_ASSEMBLER
 167 #ifndef OBJ_AOUT
 168 #ifndef TE_PE
 169 #ifndef TE_GO32
 170 /* Local labels starts with .L */
 171 #define LOCAL_LABEL(name) (name[0] == '.' \
 172                  && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
 173 #endif
 174 #endif
 175 #endif
 176 #endif
 177
 178 #define LOCAL_LABELS_FB 1
 179
 180 #define tc_aout_pre_write_hook(x)       {;}     /* not used */
 181 #define tc_crawl_symbol_chain(a)        {;}     /* not used */
 182 #define tc_headers_hook(a)              {;}     /* not used */
 183
 184 extern const char extra_symbol_chars[];
 185 #define tc_symbol_chars extra_symbol_chars
 186
 187 #define MAX_OPERANDS 3          /* max operands per insn */
 188 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
 189 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
 190
 191 /* Prefixes will be emitted in the order defined below.
 192    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 193    instruction, and so must come before any prefixes. */
 194 #define WAIT_PREFIX     0
 195 #define LOCKREP_PREFIX  1
 196 #define ADDR_PREFIX     2
 197 #define DATA_PREFIX     3
 198 #define SEG_PREFIX      4
 199 #define MAX_PREFIXES    5       /* max prefixes per opcode */
 200
 201 /* we define the syntax here (modulo base,index,scale syntax) */
 202 #define REGISTER_PREFIX '%'
 203 #define IMMEDIATE_PREFIX '$'
 204 #define ABSOLUTE_PREFIX '*'
 205
 206 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 207 #define NOP_OPCODE (char) 0x90
 208
 209 /* register numbers */
 210 #define EBP_REG_NUM 5
 211 #define ESP_REG_NUM 4
 212
 213 /* modrm_byte.regmem for twobyte escape */
 214 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 215 /* index_base_byte.index for no index register addressing */
 216 #define NO_INDEX_REGISTER ESP_REG_NUM
 217 /* index_base_byte.base for no base register addressing */
 218 #define NO_BASE_REGISTER EBP_REG_NUM
 219 #define NO_BASE_REGISTER_16 6
 220
 221 /* these are the instruction mnemonic suffixes.  */
 222 #define WORD_MNEM_SUFFIX  'w'
 223 #define BYTE_MNEM_SUFFIX  'b'
 224 #define SHORT_MNEM_SUFFIX 's'
 225 #define LONG_MNEM_SUFFIX  'l'
 226 /* Intel Syntax */
 227 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 228 /* Intel Syntax */
 229 #define DWORD_MNEM_SUFFIX 'd'
 230
 231 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 232 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 233 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 234
 235 #define END_OF_INSN '\0'
 236
 237 /* Intel Syntax */
 238 /* Values 0-4 map onto scale factor */
 239 #define BYTE_PTR     0
 240 #define WORD_PTR     1
 241 #define DWORD_PTR    2
 242 #define QWORD_PTR    3
 243 #define XWORD_PTR    4
 244 #define SHORT        5
 245 #define OFFSET_FLAT  6
 246 #define FLAT         7
 247 #define NONE_FOUND   8
 248
 249
 250 typedef struct
 251 {
 252   /* instruction name sans width suffix ("mov" for movl insns) */
 253   char *name;
 254
 255   /* how many operands */
 256   unsigned int operands;
 257
 258   /* base_opcode is the fundamental opcode byte without optional
 259      prefix(es).  */
 260   unsigned int base_opcode;
 261
 262   /* extension_opcode is the 3 bit extension for group <n> insns.
 263      This field is also used to store the 8-bit opcode suffix for the
 264      AMD 3DNow! instructions.
 265      If this template has no extension opcode (the usual case) use None */
 266   unsigned int extension_opcode;
 267 #define None 0xffff             /* If no extension_opcode is possible. */
 268
 269   /* cpu feature flags */
 270   unsigned int cpu_flags;
 271 #define Cpu086            0x1   /* Any old cpu will do, 0 does the same */
 272 #define Cpu186            0x2   /* i186 or better required */
 273 #define Cpu286            0x4   /* i286 or better required */
 274 #define Cpu386            0x8   /* i386 or better required */
 275 #define Cpu486           0x10   /* i486 or better required */
 276 #define Cpu586           0x20   /* i585 or better required */
 277 #define Cpu686           0x40   /* i686 or better required */
 278 #define CpuMMX           0x80   /* MMX support required */
 279 #define CpuSSE          0x100   /* Streaming SIMD extensions required */
 280 #define Cpu3dnow        0x200   /* 3dnow! support required */
 281
 282   /* the bits in opcode_modifier are used to generate the final opcode from
 283      the base_opcode.  These bits also are used to detect alternate forms of
 284      the same instruction */
 285   unsigned int opcode_modifier;
 286
 287   /* opcode_modifier bits: */
 288 #define W                  0x1  /* set if operands can be words or dwords
 289                                    encoded the canonical way */
 290 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 291                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 292 #define Modrm              0x4
 293 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 294 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 295 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 296 #define Jump              0x40  /* special case for jump insns. */
 297 #define JumpDword         0x80  /* call and jump */
 298 #define JumpByte         0x100  /* loop and jecxz */
 299 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 300 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 301 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 302 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns. */
 303 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 304 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 305 #define IgnoreSize      0x8000  /* instruction ignores operand size prefix */
 306 #define DefaultSize    0x10000  /* default insn size depends on mode */
 307 #define No_bSuf        0x20000  /* b suffix on instruction illegal */
 308 #define No_wSuf        0x40000  /* w suffix on instruction illegal */
 309 #define No_lSuf        0x80000  /* l suffix on instruction illegal */
 310 #define No_sSuf       0x100000  /* s suffix on instruction illegal */
 311 #define No_dSuf       0x200000  /* d suffix on instruction illegal */
 312 #define No_xSuf       0x400000  /* x suffix on instruction illegal */
 313 #define FWait         0x800000  /* instruction needs FWAIT */
 314 #define IsString     0x1000000  /* quick test for string instructions */
 315 #define regKludge    0x2000000  /* fake an extra reg operand for clr, imul */
 316 #define IsPrefix     0x4000000  /* opcode is a prefix */
 317 #define ImmExt       0x8000000  /* instruction has extension in 8 bit imm */
 318 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 319
 320   /* operand_types[i] describes the type of operand i.  This is made
 321      by OR'ing together all of the possible type masks.  (e.g.
 322      'operand_types[i] = Reg|Imm' specifies that operand i can be
 323      either a register or an immediate operand.  */
 324   unsigned int operand_types[3];
 325
 326   /* operand_types[i] bits */
 327   /* register */
 328 #define Reg8               0x1  /* 8 bit reg */
 329 #define Reg16              0x2  /* 16 bit reg */
 330 #define Reg32              0x4  /* 32 bit reg */
 331   /* immediate */
 332 #define Imm8               0x8  /* 8 bit immediate */
 333 #define Imm8S             0x10  /* 8 bit immediate sign extended */
 334 #define Imm16             0x20  /* 16 bit immediate */
 335 #define Imm32             0x40  /* 32 bit immediate */
 336 #define Imm1              0x80  /* 1 bit immediate */
 337   /* memory */
 338 #define BaseIndex        0x100
 339   /* Disp8,16,32 are used in different ways, depending on the
 340      instruction.  For jumps, they specify the size of the PC relative
 341      displacement, for baseindex type instructions, they specify the
 342      size of the offset relative to the base register, and for memory
 343      offset instructions such as `mov 1234,%al' they specify the size of
 344      the offset relative to the segment base.  */
 345 #define Disp8            0x200  /* 8 bit displacement */
 346 #define Disp16           0x400  /* 16 bit displacement */
 347 #define Disp32           0x800  /* 32 bit displacement */
 348   /* specials */
 349 #define InOutPortReg    0x1000  /* register to hold in/out port addr = dx */
 350 #define ShiftCount      0x2000  /* register to hold shift cound = cl */
 351 #define Control         0x4000  /* Control register */
 352 #define Debug           0x8000  /* Debug register */
 353 #define Test           0x10000  /* Test register */
 354 #define FloatReg       0x20000  /* Float register */
 355 #define FloatAcc       0x40000  /* Float stack top %st(0) */
 356 #define SReg2          0x80000  /* 2 bit segment register */
 357 #define SReg3         0x100000  /* 3 bit segment register */
 358 #define Acc           0x200000  /* Accumulator %al or %ax or %eax */
 359 #define JumpAbsolute  0x400000
 360 #define RegMMX        0x800000  /* MMX register */
 361 #define RegXMM       0x1000000  /* XMM registers in PIII */
 362 #define EsSeg        0x2000000  /* String insn operand with fixed es segment */
 363   /* InvMem is for instructions with a modrm byte that only allow a
 364      general register encoding in the i.tm.mode and i.tm.regmem fields,
 365      eg. control reg moves.  They really ought to support a memory form,
 366      but don't, so we add an InvMem flag to the register operand to
 367      indicate that it should be encoded in the i.tm.regmem field.  */
 368 #define InvMem       0x4000000
 369
 370 #define Reg     (Reg8|Reg16|Reg32)      /* gen'l register */
 371 #define WordReg (Reg16|Reg32)
 372 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 373 #define Imm     (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
 374 #define Disp    (Disp8|Disp16|Disp32)   /* General displacement */
 375 #define AnyMem  (Disp|BaseIndex|InvMem) /* General memory */
 376   /* The following aliases are defined because the opcode table
 377      carefully specifies the allowed memory types for each instruction.
 378      At the moment we can only tell a memory reference size by the
 379      instruction suffix, so there's not much point in defining Mem8,
 380      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 381      the suffix directly to check memory operands.  */
 382 #define LLongMem AnyMem         /* 64 bits (or more) */
 383 #define LongMem AnyMem          /* 32 bit memory ref */
 384 #define ShortMem AnyMem         /* 16 bit memory ref */
 385 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 386 #define ByteMem AnyMem          /* 8 bit memory ref */
 387 }
 388 template;
 389
 390 /*
 391   'templates' is for grouping together 'template' structures for opcodes
 392   of the same name.  This is only used for storing the insns in the grand
 393   ole hash table of insns.
 394   The templates themselves start at START and range up to (but not including)
 395   END.
 396   */
 397 typedef struct
 398 {
 399   const template *start;
 400   const template *end;
 401 }
 402 templates;
 403
 404 /* these are for register name --> number & type hash lookup */
 405 typedef struct
 406 {
 407   char *reg_name;
 408   unsigned int reg_type;
 409   unsigned int reg_num;
 410 }
 411 reg_entry;
 412
 413 typedef struct
 414 {
 415   char *seg_name;
 416   unsigned int seg_prefix;
 417 }
 418 seg_entry;
 419
 420 /* 386 operand encoding bytes:  see 386 book for details of this. */
 421 typedef struct
 422 {
 423   unsigned int regmem;  /* codes register or memory operand */
 424   unsigned int reg;     /* codes register operand (or extended opcode) */
 425   unsigned int mode;    /* how to interpret regmem & reg */
 426 }
 427 modrm_byte;
 428
 429 /* 386 opcode byte to code indirect addressing. */
 430 typedef struct
 431 {
 432   unsigned base;
 433   unsigned index;
 434   unsigned scale;
 435 }
 436 sib_byte;
 437
 438 /* x86 arch names and features */
 439 typedef struct
 440 {
 441   const char *name;     /* arch name */
 442   unsigned int flags;   /* cpu feature flags */
 443 }
 444 arch_entry;
 445
 446 /* The name of the global offset table generated by the compiler. Allow
 447    this to be overridden if need be. */
 448 #ifndef GLOBAL_OFFSET_TABLE_NAME
 449 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 450 #endif
 451
 452 #ifdef BFD_ASSEMBLER
 453 void i386_validate_fix PARAMS ((struct fix *));
 454 #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
 455 #endif
 456
 457 #endif /* TC_I386 */
 458
 459 #define md_operand(x)
 460
 461 extern const struct relax_type md_relax_table[];
 462 #define TC_GENERIC_RELAX_TABLE md_relax_table
 463
 464 #define md_do_align(n, fill, len, max, around)                          \
 465 if ((n) && !need_pass_2                                                 \
 466     && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1))         \
 467     && subseg_text_p (now_seg))                                         \
 468   {                                                                     \
 469     char *p;                                                            \
 470     p = frag_var (rs_align_code, 15, 1, (relax_substateT) max,          \
 471                   (symbolS *) 0, (offsetT) (n), (char *) 0);            \
 472     *p = 0x90;                                                          \
 473     goto around;                                                        \
 474   }
 475
 476 extern void i386_align_code PARAMS ((fragS *, int));
 477
 478 #define HANDLE_ALIGN(fragP)                                             \
 479 if (fragP->fr_type == rs_align_code)                                    \
 480   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 481                            - fragP->fr_address                          \
 482                            - fragP->fr_fix));
 483
 484 /* call md_apply_fix3 with segment instead of md_apply_fix */
 485 #define MD_APPLY_FIX3
 486
 487 void i386_print_statistics PARAMS ((FILE *));
 488 #define tc_print_statistics i386_print_statistics
 489
 490 #define md_number_to_chars number_to_chars_littleendian
 491
 492 #ifdef SCO_ELF
 493 #define tc_init_after_args() sco_id ()
 494 extern void sco_id PARAMS ((void));
 495 #endif
 496
 497 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 498
 499 /* end of tc-i386.h */