gas/config/tc-i386.h

   1 /* tc-i386.h -- Header file for tc-i386.c
   2    Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
   3    Free Software Foundation.
   4
   5    This file is part of GAS, the GNU Assembler.
   6
   7    GAS is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2, or (at your option)
  10    any later version.
  11
  12    GAS is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #ifndef TC_I386
  23 #define TC_I386 1
  24
  25 #ifdef ANSI_PROTOTYPES
  26 struct fix;
  27 #endif
  28
  29 #define TARGET_BYTES_BIG_ENDIAN 0
  30
  31 #ifdef TE_LYNX
  32 #define TARGET_FORMAT           "coff-i386-lynx"
  33 #endif
  34
  35 #ifdef BFD_ASSEMBLER
  36 /* This is used to determine relocation types in tc-i386.c.  The first
  37    parameter is the current relocation type, the second one is the desired
  38    type.  The idea is that if the original type is already some kind of PIC
  39    relocation, we leave it alone, otherwise we give it the desired type */
  40
  41 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
  42 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
  43
  44 #if (defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) || defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)) && !defined (TE_PE)
  45 /* This arranges for gas/write.c to not apply a relocation if
  46    tc_fix_adjustable() says it is not adjustable.
  47    The "! symbol_used_in_reloc_p" test is there specifically to cover
  48    the case of non-global symbols in linkonce sections.  It's the
  49    generally correct thing to do though;  If a reloc is going to be
  50    emitted against a symbol then we don't want to adjust the fixup by
  51    applying the reloc during assembly.  The reloc will be applied by
  52    the linker during final link.  */
  53 #define TC_FIX_ADJUSTABLE(fixP) \
  54   (! symbol_used_in_reloc_p ((fixP)->fx_addsy) && tc_fix_adjustable (fixP))
  55 #endif
  56
  57 /* This expression evaluates to false if the relocation is for a local object
  58    for which we still want to do the relocation at runtime.  True if we
  59    are willing to perform this relocation while building the .o file.
  60    This is only used for pcrel relocations, so GOTOFF does not need to be
  61    checked here.  I am not sure if some of the others are ever used with
  62    pcrel, but it is easier to be safe than sorry.  */
  63
  64 #define TC_RELOC_RTSYM_LOC_FIXUP(FIX)                           \
  65   ((FIX)->fx_r_type != BFD_RELOC_386_PLT32                      \
  66    && (FIX)->fx_r_type != BFD_RELOC_386_GOT32                   \
  67    && (FIX)->fx_r_type != BFD_RELOC_386_GOTPC                   \
  68    && ((FIX)->fx_addsy == NULL                                  \
  69        || (! S_IS_EXTERNAL ((FIX)->fx_addsy)                    \
  70            && ! S_IS_WEAK ((FIX)->fx_addsy)                     \
  71            && S_IS_DEFINED ((FIX)->fx_addsy)                    \
  72            && ! S_IS_COMMON ((FIX)->fx_addsy))))
  73
  74 #define TARGET_ARCH             bfd_arch_i386
  75 #define TARGET_MACH             (i386_mach ())
  76 extern unsigned long i386_mach PARAMS ((void));
  77
  78 #ifdef TE_NetBSD
  79 #define AOUT_TARGET_FORMAT      "a.out-i386-netbsd"
  80 #endif
  81 #ifdef TE_386BSD
  82 #define AOUT_TARGET_FORMAT      "a.out-i386-bsd"
  83 #endif
  84 #ifdef TE_LINUX
  85 #define AOUT_TARGET_FORMAT      "a.out-i386-linux"
  86 #endif
  87 #ifdef TE_Mach
  88 #define AOUT_TARGET_FORMAT      "a.out-mach3"
  89 #endif
  90 #ifdef TE_DYNIX
  91 #define AOUT_TARGET_FORMAT      "a.out-i386-dynix"
  92 #endif
  93 #ifndef AOUT_TARGET_FORMAT
  94 #define AOUT_TARGET_FORMAT      "a.out-i386"
  95 #endif
  96
  97 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
  98      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
  99 extern const char *i386_target_format PARAMS ((void));
 100 #define TARGET_FORMAT i386_target_format ()
 101 #else
 102 #ifdef OBJ_ELF
 103 #define TARGET_FORMAT           "elf32-i386"
 104 #endif
 105 #ifdef OBJ_AOUT
 106 #define TARGET_FORMAT           AOUT_TARGET_FORMAT
 107 #endif
 108 #endif
 109
 110 #else /* ! BFD_ASSEMBLER */
 111
 112 /* COFF STUFF */
 113
 114 #define COFF_MAGIC I386MAGIC
 115 #define BFD_ARCH bfd_arch_i386
 116 #define COFF_FLAGS F_AR32WR
 117 #define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
 118 #define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
 119 extern short tc_coff_fix2rtype PARAMS ((struct fix *));
 120 #define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
 121 extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
 122
 123 #ifdef TE_GO32
 124 /* DJGPP now expects some sections to be 2**4 aligned.  */
 125 #define SUB_SEGMENT_ALIGN(SEG)                                          \
 126   ((strcmp (obj_segment_name (SEG), ".text") == 0                       \
 127     || strcmp (obj_segment_name (SEG), ".data") == 0                    \
 128     || strcmp (obj_segment_name (SEG), ".bss") == 0                     \
 129     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0     \
 130     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0     \
 131     || strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0)    \
 132    ? 4                                                                  \
 133    : 2)
 134 #else
 135 #define SUB_SEGMENT_ALIGN(SEG) 2
 136 #endif
 137
 138 #define TC_RVA_RELOC 7
 139 /* Need this for PIC relocations */
 140 #define NEED_FX_R_TYPE
 141
 142 #ifdef TE_386BSD
 143 /* The BSDI linker apparently rejects objects with a machine type of
 144    M_386 (100).  */
 145 #define AOUT_MACHTYPE 0
 146 #else
 147 #define AOUT_MACHTYPE 100
 148 #endif
 149
 150 #undef REVERSE_SORT_RELOCS
 151
 152 #endif /* ! BFD_ASSEMBLER */
 153
 154 #define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
 155 extern int tc_i386_force_relocation PARAMS ((struct fix *));
 156
 157 #ifdef BFD_ASSEMBLER
 158 #define NO_RELOC BFD_RELOC_NONE
 159 #else
 160 #define NO_RELOC 0
 161 #endif
 162 #define tc_coff_symbol_emit_hook(a)     ;       /* not used */
 163
 164 #ifndef BFD_ASSEMBLER
 165 #ifndef OBJ_AOUT
 166 #ifndef TE_PE
 167 #ifndef TE_GO32
 168 /* Local labels starts with .L */
 169 #define LOCAL_LABEL(name) (name[0] == '.' \
 170                  && (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
 171 #endif
 172 #endif
 173 #endif
 174 #endif
 175
 176 #define LOCAL_LABELS_FB 1
 177
 178 #define tc_aout_pre_write_hook(x)       {;}     /* not used */
 179 #define tc_crawl_symbol_chain(a)        {;}     /* not used */
 180 #define tc_headers_hook(a)              {;}     /* not used */
 181
 182 extern const char extra_symbol_chars[];
 183 #define tc_symbol_chars extra_symbol_chars
 184
 185 #define MAX_OPERANDS 3          /* max operands per insn */
 186 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
 187 #define MAX_MEMORY_OPERANDS 2   /* max memory refs per insn (string ops) */
 188
 189 /* Prefixes will be emitted in the order defined below.
 190    WAIT_PREFIX must be the first prefix since FWAIT is really is an
 191    instruction, and so must come before any prefixes.  */
 192 #define WAIT_PREFIX     0
 193 #define LOCKREP_PREFIX  1
 194 #define ADDR_PREFIX     2
 195 #define DATA_PREFIX     3
 196 #define SEG_PREFIX      4
 197 #define REX_PREFIX      5       /* must come last.  */
 198 #define MAX_PREFIXES    6       /* max prefixes per opcode */
 199
 200 /* we define the syntax here (modulo base,index,scale syntax) */
 201 #define REGISTER_PREFIX '%'
 202 #define IMMEDIATE_PREFIX '$'
 203 #define ABSOLUTE_PREFIX '*'
 204
 205 #define TWO_BYTE_OPCODE_ESCAPE 0x0f
 206 #define NOP_OPCODE (char) 0x90
 207
 208 /* register numbers */
 209 #define EBP_REG_NUM 5
 210 #define ESP_REG_NUM 4
 211
 212 /* modrm_byte.regmem for twobyte escape */
 213 #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM
 214 /* index_base_byte.index for no index register addressing */
 215 #define NO_INDEX_REGISTER ESP_REG_NUM
 216 /* index_base_byte.base for no base register addressing */
 217 #define NO_BASE_REGISTER EBP_REG_NUM
 218 #define NO_BASE_REGISTER_16 6
 219
 220 /* these are the instruction mnemonic suffixes.  */
 221 #define WORD_MNEM_SUFFIX  'w'
 222 #define BYTE_MNEM_SUFFIX  'b'
 223 #define SHORT_MNEM_SUFFIX 's'
 224 #define LONG_MNEM_SUFFIX  'l'
 225 #define QWORD_MNEM_SUFFIX  'q'
 226 /* Intel Syntax */
 227 #define LONG_DOUBLE_MNEM_SUFFIX 'x'
 228
 229 /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
 230 #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
 231 #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG)
 232
 233 #define END_OF_INSN '\0'
 234
 235 /* Intel Syntax */
 236 /* Values 0-4 map onto scale factor */
 237 #define BYTE_PTR     0
 238 #define WORD_PTR     1
 239 #define DWORD_PTR    2
 240 #define QWORD_PTR    3
 241 #define XWORD_PTR    4
 242 #define SHORT        5
 243 #define OFFSET_FLAT  6
 244 #define FLAT         7
 245 #define NONE_FOUND   8
 246
 247 typedef struct
 248 {
 249   /* instruction name sans width suffix ("mov" for movl insns) */
 250   char *name;
 251
 252   /* how many operands */
 253   unsigned int operands;
 254
 255   /* base_opcode is the fundamental opcode byte without optional
 256      prefix(es).  */
 257   unsigned int base_opcode;
 258
 259   /* extension_opcode is the 3 bit extension for group <n> insns.
 260      This field is also used to store the 8-bit opcode suffix for the
 261      AMD 3DNow! instructions.
 262      If this template has no extension opcode (the usual case) use None */
 263   unsigned int extension_opcode;
 264 #define None 0xffff             /* If no extension_opcode is possible.  */
 265
 266   /* cpu feature flags */
 267   unsigned int cpu_flags;
 268 #define Cpu086            0x1   /* Any old cpu will do, 0 does the same */
 269 #define Cpu186            0x2   /* i186 or better required */
 270 #define Cpu286            0x4   /* i286 or better required */
 271 #define Cpu386            0x8   /* i386 or better required */
 272 #define Cpu486           0x10   /* i486 or better required */
 273 #define Cpu586           0x20   /* i585 or better required */
 274 #define Cpu686           0x40   /* i686 or better required */
 275 #define CpuP4            0x80   /* Pentium4 or better required */
 276 #define CpuK6           0x100   /* AMD K6 or better required*/
 277 #define CpuAthlon       0x200   /* AMD Athlon or better required*/
 278 #define CpuSledgehammer 0x400   /* Sledgehammer or better required */
 279 #define CpuMMX          0x800   /* MMX support required */
 280 #define CpuSSE         0x1000   /* Streaming SIMD extensions required */
 281 #define CpuSSE2        0x2000   /* Streaming SIMD extensions 2 required */
 282 #define Cpu3dnow       0x4000   /* 3dnow! support required */
 283 #define CpuUnknown     0x8000   /* The CPU is unknown,  be on the safe side.  */
 284
 285   /* These flags are set by gas depending on the flag_code.  */
 286 #define Cpu64        0x4000000   /* 64bit support required  */
 287 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 288
 289   /* The default value for unknown CPUs - enable all features to avoid problems.  */
 290 #define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|Cpu3dnow|CpuK6|CpuAthlon)
 291
 292   /* the bits in opcode_modifier are used to generate the final opcode from
 293      the base_opcode.  These bits also are used to detect alternate forms of
 294      the same instruction */
 295   unsigned int opcode_modifier;
 296
 297   /* opcode_modifier bits: */
 298 #define W                  0x1  /* set if operands can be words or dwords
 299                                    encoded the canonical way */
 300 #define D                  0x2  /* D = 0 if Reg --> Regmem;
 301                                    D = 1 if Regmem --> Reg:    MUST BE 0x2 */
 302 #define Modrm              0x4
 303 #define FloatR             0x8  /* src/dest swap for floats:   MUST BE 0x8 */
 304 #define ShortForm         0x10  /* register is in low 3 bits of opcode */
 305 #define FloatMF           0x20  /* FP insn memory format bit, sized by 0x4 */
 306 #define Jump              0x40  /* special case for jump insns.  */
 307 #define JumpDword         0x80  /* call and jump */
 308 #define JumpByte         0x100  /* loop and jecxz */
 309 #define JumpInterSegment 0x200  /* special case for intersegment leaps/calls */
 310 #define FloatD           0x400  /* direction for float insns:  MUST BE 0x400 */
 311 #define Seg2ShortForm    0x800  /* encoding of load segment reg insns */
 312 #define Seg3ShortForm   0x1000  /* fs/gs segment register insns.  */
 313 #define Size16          0x2000  /* needs size prefix if in 32-bit mode */
 314 #define Size32          0x4000  /* needs size prefix if in 16-bit mode */
 315 #define Size64          0x8000  /* needs size prefix if in 16-bit mode */
 316 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
 317 #define DefaultSize    0x20000  /* default insn size depends on mode */
 318 #define No_bSuf        0x40000  /* b suffix on instruction illegal */
 319 #define No_wSuf        0x80000  /* w suffix on instruction illegal */
 320 #define No_lSuf       0x100000  /* l suffix on instruction illegal */
 321 #define No_sSuf       0x200000  /* s suffix on instruction illegal */
 322 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
 323 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
 324 #define FWait        0x1000000  /* instruction needs FWAIT */
 325 #define IsString     0x2000000  /* quick test for string instructions */
 326 #define regKludge    0x4000000  /* fake an extra reg operand for clr, imul */
 327 #define IsPrefix     0x8000000  /* opcode is a prefix */
 328 #define ImmExt      0x10000000  /* instruction has extension in 8 bit imm */
 329 #define NoRex64     0x20000000  /* instruction don't need Rex64 prefix.  */
 330 #define Rex64       0x40000000  /* instruction require Rex64 prefix.  */
 331 #define Ugh         0x80000000  /* deprecated fp insn, gets a warning */
 332
 333   /* operand_types[i] describes the type of operand i.  This is made
 334      by OR'ing together all of the possible type masks.  (e.g.
 335      'operand_types[i] = Reg|Imm' specifies that operand i can be
 336      either a register or an immediate operand.  */
 337   unsigned int operand_types[3];
 338
 339   /* operand_types[i] bits */
 340   /* register */
 341 #define Reg8               0x1  /* 8 bit reg */
 342 #define Reg16              0x2  /* 16 bit reg */
 343 #define Reg32              0x4  /* 32 bit reg */
 344 #define Reg64              0x8  /* 64 bit reg */
 345   /* immediate */
 346 #define Imm8              0x10  /* 8 bit immediate */
 347 #define Imm8S             0x20  /* 8 bit immediate sign extended */
 348 #define Imm16             0x40  /* 16 bit immediate */
 349 #define Imm32             0x80  /* 32 bit immediate */
 350 #define Imm32S           0x100  /* 32 bit immediate sign extended */
 351 #define Imm64            0x200  /* 64 bit immediate */
 352 #define Imm1             0x400  /* 1 bit immediate */
 353   /* memory */
 354 #define BaseIndex        0x800
 355   /* Disp8,16,32 are used in different ways, depending on the
 356      instruction.  For jumps, they specify the size of the PC relative
 357      displacement, for baseindex type instructions, they specify the
 358      size of the offset relative to the base register, and for memory
 359      offset instructions such as `mov 1234,%al' they specify the size of
 360      the offset relative to the segment base.  */
 361 #define Disp8           0x1000  /* 8 bit displacement */
 362 #define Disp16          0x2000  /* 16 bit displacement */
 363 #define Disp32          0x4000  /* 32 bit displacement */
 364 #define Disp32S         0x8000  /* 32 bit signed displacement */
 365 #define Disp64         0x10000  /* 64 bit displacement */
 366   /* specials */
 367 #define InOutPortReg   0x20000  /* register to hold in/out port addr = dx */
 368 #define ShiftCount     0x40000  /* register to hold shift cound = cl */
 369 #define Control        0x80000  /* Control register */
 370 #define Debug         0x100000  /* Debug register */
 371 #define Test          0x200000  /* Test register */
 372 #define FloatReg      0x400000  /* Float register */
 373 #define FloatAcc      0x800000  /* Float stack top %st(0) */
 374 #define SReg2        0x1000000  /* 2 bit segment register */
 375 #define SReg3        0x2000000  /* 3 bit segment register */
 376 #define Acc          0x4000000  /* Accumulator %al or %ax or %eax */
 377 #define JumpAbsolute 0x8000000
 378 #define RegMMX      0x10000000  /* MMX register */
 379 #define RegXMM      0x20000000  /* XMM registers in PIII */
 380 #define EsSeg       0x40000000  /* String insn operand with fixed es segment */
 381
 382   /* InvMem is for instructions with a modrm byte that only allow a
 383      general register encoding in the i.tm.mode and i.tm.regmem fields,
 384      eg. control reg moves.  They really ought to support a memory form,
 385      but don't, so we add an InvMem flag to the register operand to
 386      indicate that it should be encoded in the i.tm.regmem field.  */
 387 #define InvMem      0x80000000
 388
 389 #define Reg     (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
 390 #define WordReg (Reg16|Reg32|Reg64)
 391 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
 392 #define Imm     (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
 393 #define EncImm  (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
 394 #define Disp    (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
 395 #define AnyMem  (Disp8|Disp16|Disp32|Disp32S|BaseIndex|InvMem)  /* General memory */
 396   /* The following aliases are defined because the opcode table
 397      carefully specifies the allowed memory types for each instruction.
 398      At the moment we can only tell a memory reference size by the
 399      instruction suffix, so there's not much point in defining Mem8,
 400      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
 401      the suffix directly to check memory operands.  */
 402 #define LLongMem AnyMem         /* 64 bits (or more) */
 403 #define LongMem AnyMem          /* 32 bit memory ref */
 404 #define ShortMem AnyMem         /* 16 bit memory ref */
 405 #define WordMem AnyMem          /* 16 or 32 bit memory ref */
 406 #define ByteMem AnyMem          /* 8 bit memory ref */
 407 }
 408 template;
 409
 410 /*
 411   'templates' is for grouping together 'template' structures for opcodes
 412   of the same name.  This is only used for storing the insns in the grand
 413   ole hash table of insns.
 414   The templates themselves start at START and range up to (but not including)
 415   END.
 416   */
 417 typedef struct
 418 {
 419   const template *start;
 420   const template *end;
 421 }
 422 templates;
 423
 424 /* these are for register name --> number & type hash lookup */
 425 typedef struct
 426 {
 427   char *reg_name;
 428   unsigned int reg_type;
 429   unsigned int reg_flags;
 430 #define RegRex      0x1  /* Extended register.  */
 431 #define RegRex64    0x2  /* Extended 8 bit register.  */
 432   unsigned int reg_num;
 433 }
 434 reg_entry;
 435
 436 typedef struct
 437 {
 438   char *seg_name;
 439   unsigned int seg_prefix;
 440 }
 441 seg_entry;
 442
 443 /* 386 operand encoding bytes:  see 386 book for details of this.  */
 444 typedef struct
 445 {
 446   unsigned int regmem;  /* codes register or memory operand */
 447   unsigned int reg;     /* codes register operand (or extended opcode) */
 448   unsigned int mode;    /* how to interpret regmem & reg */
 449 }
 450 modrm_byte;
 451
 452 /* x86-64 extension prefix.  */
 453 typedef struct
 454   {
 455     unsigned int mode64;
 456     unsigned int extX;          /* Used to extend modrm reg field.  */
 457     unsigned int extY;          /* Used to extend SIB index field.  */
 458     unsigned int extZ;          /* Used to extend modrm reg/mem, SIB base, modrm base fields.  */
 459     unsigned int empty;         /* Used to old-style byte registers to new style.  */
 460   }
 461 rex_byte;
 462
 463 /* 386 opcode byte to code indirect addressing.  */
 464 typedef struct
 465 {
 466   unsigned base;
 467   unsigned index;
 468   unsigned scale;
 469 }
 470 sib_byte;
 471
 472 /* x86 arch names and features */
 473 typedef struct
 474 {
 475   const char *name;     /* arch name */
 476   unsigned int flags;   /* cpu feature flags */
 477 }
 478 arch_entry;
 479
 480 /* The name of the global offset table generated by the compiler. Allow
 481    this to be overridden if need be.  */
 482 #ifndef GLOBAL_OFFSET_TABLE_NAME
 483 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 484 #endif
 485
 486 #ifdef BFD_ASSEMBLER
 487 void i386_validate_fix PARAMS ((struct fix *));
 488 #define TC_VALIDATE_FIX(FIXP,SEGTYPE,SKIP) i386_validate_fix(FIXP)
 489 #endif
 490
 491 #endif /* TC_I386 */
 492
 493 #define md_operand(x)
 494
 495 extern const struct relax_type md_relax_table[];
 496 #define TC_GENERIC_RELAX_TABLE md_relax_table
 497
 498 #define md_do_align(n, fill, len, max, around)                          \
 499 if ((n) && !need_pass_2                                                 \
 500     && (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1))         \
 501     && subseg_text_p (now_seg))                                         \
 502   {                                                                     \
 503     frag_align_code ((n), (max));                                       \
 504     goto around;                                                        \
 505   }
 506
 507 #define MAX_MEM_FOR_RS_ALIGN_CODE  15
 508
 509 extern void i386_align_code PARAMS ((fragS *, int));
 510
 511 #define HANDLE_ALIGN(fragP)                                             \
 512 if (fragP->fr_type == rs_align_code)                                    \
 513   i386_align_code (fragP, (fragP->fr_next->fr_address                   \
 514                            - fragP->fr_address                          \
 515                            - fragP->fr_fix));
 516
 517 /* call md_apply_fix3 with segment instead of md_apply_fix */
 518 #define MD_APPLY_FIX3
 519
 520 void i386_print_statistics PARAMS ((FILE *));
 521 #define tc_print_statistics i386_print_statistics
 522
 523 #define md_number_to_chars number_to_chars_littleendian
 524
 525 #ifdef SCO_ELF
 526 #define tc_init_after_args() sco_id ()
 527 extern void sco_id PARAMS ((void));
 528 #endif
 529
 530 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */