1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix
*next
;
137 extern int target_big_endian
;
139 /* Characters which always start a comment. */
140 const char comment_chars
[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars
[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars
[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS
[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts
= "m:N:x::";
161 struct option md_longopts
[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
169 size_t md_longopts_size
= sizeof (md_longopts
);
173 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
174 struct hash_control
*reg_hash
; /* register name hash table */
175 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
176 struct hash_control
*const_hash
; /* constant hash table */
177 struct hash_control
*entry_hash
; /* code entry hint hash table */
179 symbolS
*regsym
[REG_NUM
];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
190 explicit_mode
: 1, /* which mode we're in */
191 default_explicit_mode
: 1, /* which mode is the default */
192 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
199 int num_slots_in_use
;
203 end_of_insn_group
: 1,
204 manual_bundling_on
: 1,
205 manual_bundling_off
: 1;
206 signed char user_template
; /* user-selected template, if any */
207 unsigned char qp_regno
; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
214 bfd_reloc_code_real_type code
;
215 enum ia64_opnd opnd
; /* type of operand in need of fix */
216 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
217 expressionS expr
; /* the value to be inserted */
219 fixup
[2]; /* at most two fixups per insn */
220 struct ia64_opcode
*idesc
;
221 struct label_fix
*label_fixups
;
222 struct label_fix
*tag_fixups
;
223 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
226 unsigned int src_line
;
227 struct dwarf2_line_info debug_line
;
235 struct dynreg
*next
; /* next dynamic register */
237 unsigned short base
; /* the base register number */
238 unsigned short num_regs
; /* # of registers in this set */
240 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
242 flagword flags
; /* ELF-header flags */
245 unsigned hint
:1; /* is this hint currently valid? */
246 bfd_vma offset
; /* mem.offset offset */
247 bfd_vma base
; /* mem.offset base */
250 int path
; /* number of alt. entry points seen */
251 const char **entry_labels
; /* labels of all alternate paths in
252 the current DV-checking block. */
253 int maxpaths
; /* size currently allocated for
255 /* Support for hardware errata workarounds. */
257 /* Record data about the last three insn groups. */
260 /* B-step workaround.
261 For each predicate register, this is set if the corresponding insn
262 group conditionally sets this register with one of the affected
265 /* B-step workaround.
266 For each general register, this is set if the corresponding insn
267 a) is conditional one one of the predicate registers for which
268 P_REG_SET is 1 in the corresponding entry of the previous group,
269 b) sets this general register with one of the affected
271 int g_reg_set_conditionally
[128];
277 /* application registers: */
283 #define AR_BSPSTORE 18
298 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
299 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
300 {"ar.rsc", 16}, {"ar.bsp", 17},
301 {"ar.bspstore", 18}, {"ar.rnat", 19},
302 {"ar.fcr", 21}, {"ar.eflag", 24},
303 {"ar.csd", 25}, {"ar.ssd", 26},
304 {"ar.cflg", 27}, {"ar.fsr", 28},
305 {"ar.fir", 29}, {"ar.fdr", 30},
306 {"ar.ccv", 32}, {"ar.unat", 36},
307 {"ar.fpsr", 40}, {"ar.itc", 44},
308 {"ar.pfs", 64}, {"ar.lc", 65},
329 /* control registers: */
371 static const struct const_desc
378 /* PSR constant masks: */
381 {"psr.be", ((valueT
) 1) << 1},
382 {"psr.up", ((valueT
) 1) << 2},
383 {"psr.ac", ((valueT
) 1) << 3},
384 {"psr.mfl", ((valueT
) 1) << 4},
385 {"psr.mfh", ((valueT
) 1) << 5},
387 {"psr.ic", ((valueT
) 1) << 13},
388 {"psr.i", ((valueT
) 1) << 14},
389 {"psr.pk", ((valueT
) 1) << 15},
391 {"psr.dt", ((valueT
) 1) << 17},
392 {"psr.dfl", ((valueT
) 1) << 18},
393 {"psr.dfh", ((valueT
) 1) << 19},
394 {"psr.sp", ((valueT
) 1) << 20},
395 {"psr.pp", ((valueT
) 1) << 21},
396 {"psr.di", ((valueT
) 1) << 22},
397 {"psr.si", ((valueT
) 1) << 23},
398 {"psr.db", ((valueT
) 1) << 24},
399 {"psr.lp", ((valueT
) 1) << 25},
400 {"psr.tb", ((valueT
) 1) << 26},
401 {"psr.rt", ((valueT
) 1) << 27},
402 /* 28-31: reserved */
403 /* 32-33: cpl (current privilege level) */
404 {"psr.is", ((valueT
) 1) << 34},
405 {"psr.mc", ((valueT
) 1) << 35},
406 {"psr.it", ((valueT
) 1) << 36},
407 {"psr.id", ((valueT
) 1) << 37},
408 {"psr.da", ((valueT
) 1) << 38},
409 {"psr.dd", ((valueT
) 1) << 39},
410 {"psr.ss", ((valueT
) 1) << 40},
411 /* 41-42: ri (restart instruction) */
412 {"psr.ed", ((valueT
) 1) << 43},
413 {"psr.bn", ((valueT
) 1) << 44},
416 /* indirect register-sets/memory: */
425 { "CPUID", IND_CPUID
},
426 { "cpuid", IND_CPUID
},
438 /* Pseudo functions used to indicate relocation types (these functions
439 start with an at sign (@). */
461 /* reloc pseudo functions (these must come first!): */
462 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
463 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
464 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
465 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
466 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
467 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
468 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
469 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
470 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
472 /* mbtype4 constants: */
473 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
474 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
475 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
476 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
477 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
479 /* fclass constants: */
480 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
481 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
482 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
483 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
484 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
485 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
486 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
487 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
488 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
490 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
492 /* unwind-related constants: */
493 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
494 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
495 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
497 /* unwind-related registers: */
498 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
501 /* 41-bit nop opcodes (one per unit): */
502 static const bfd_vma nop
[IA64_NUM_UNITS
] =
504 0x0000000000LL
, /* NIL => break 0 */
505 0x0008000000LL
, /* I-unit nop */
506 0x0008000000LL
, /* M-unit nop */
507 0x4000000000LL
, /* B-unit nop */
508 0x0008000000LL
, /* F-unit nop */
509 0x0008000000LL
, /* L-"unit" nop */
510 0x0008000000LL
, /* X-unit nop */
513 /* Can't be `const' as it's passed to input routines (which have the
514 habit of setting temporary sentinels. */
515 static char special_section_name
[][20] =
517 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
518 {".IA_64.unwind"}, {".IA_64.unwind_info"}
521 /* The best template for a particular sequence of up to three
523 #define N IA64_NUM_TYPES
524 static unsigned char best_template
[N
][N
][N
];
527 /* Resource dependencies currently in effect */
529 int depind
; /* dependency index */
530 const struct ia64_dependency
*dependency
; /* actual dependency */
531 unsigned specific
:1, /* is this a specific bit/regno? */
532 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
533 int index
; /* specific regno/bit within dependency */
534 int note
; /* optional qualifying note (0 if none) */
538 int insn_srlz
; /* current insn serialization state */
539 int data_srlz
; /* current data serialization state */
540 int qp_regno
; /* qualifying predicate for this usage */
541 char *file
; /* what file marked this dependency */
542 unsigned int line
; /* what line marked this dependency */
543 struct mem_offset mem_offset
; /* optional memory offset hint */
544 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
545 int path
; /* corresponding code entry index */
547 static int regdepslen
= 0;
548 static int regdepstotlen
= 0;
549 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
550 static const char *dv_sem
[] = { "none", "implied", "impliedf",
551 "data", "instr", "specific", "stop", "other" };
552 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
554 /* Current state of PR mutexation */
555 static struct qpmutex
{
558 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
559 static int qp_mutexeslen
= 0;
560 static int qp_mutexestotlen
= 0;
561 static valueT qp_safe_across_calls
= 0;
563 /* Current state of PR implications */
564 static struct qp_imply
{
567 unsigned p2_branched
:1;
569 } *qp_implies
= NULL
;
570 static int qp_implieslen
= 0;
571 static int qp_impliestotlen
= 0;
573 /* Keep track of static GR values so that indirect register usage can
574 sometimes be tracked. */
579 } gr_values
[128] = {{ 1, 0, 0 }};
581 /* These are the routines required to output the various types of
584 /* A slot_number is a frag address plus the slot index (0-2). We use the
585 frag address here so that if there is a section switch in the middle of
586 a function, then instructions emitted to a different section are not
587 counted. Since there may be more than one frag for a function, this
588 means we also need to keep track of which frag this address belongs to
589 so we can compute inter-frag distances. This also nicely solves the
590 problem with nops emitted for align directives, which can't easily be
591 counted, but can easily be derived from frag sizes. */
593 typedef struct unw_rec_list
{
595 unsigned long slot_number
;
597 struct unw_rec_list
*next
;
600 #define SLOT_NUM_NOT_SET (unsigned)-1
604 unsigned long next_slot_number
;
605 fragS
*next_slot_frag
;
607 /* Maintain a list of unwind entries for the current function. */
611 /* Any unwind entires that should be attached to the current slot
612 that an insn is being constructed for. */
613 unw_rec_list
*current_entry
;
615 /* These are used to create the unwind table entry for this function. */
618 symbolS
*info
; /* pointer to unwind info */
619 symbolS
*personality_routine
;
621 subsegT saved_text_subseg
;
622 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
624 /* TRUE if processing unwind directives in a prologue region. */
627 unsigned int prologue_count
; /* number of .prologues seen so far */
630 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
632 /* Forward delarations: */
633 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
634 static void set_section
PARAMS ((char *name
));
635 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
636 unsigned int, unsigned int));
637 static void dot_radix
PARAMS ((int));
638 static void dot_special_section
PARAMS ((int));
639 static void dot_proc
PARAMS ((int));
640 static void dot_fframe
PARAMS ((int));
641 static void dot_vframe
PARAMS ((int));
642 static void dot_vframesp
PARAMS ((int));
643 static void dot_vframepsp
PARAMS ((int));
644 static void dot_save
PARAMS ((int));
645 static void dot_restore
PARAMS ((int));
646 static void dot_restorereg
PARAMS ((int));
647 static void dot_restorereg_p
PARAMS ((int));
648 static void dot_handlerdata
PARAMS ((int));
649 static void dot_unwentry
PARAMS ((int));
650 static void dot_altrp
PARAMS ((int));
651 static void dot_savemem
PARAMS ((int));
652 static void dot_saveg
PARAMS ((int));
653 static void dot_savef
PARAMS ((int));
654 static void dot_saveb
PARAMS ((int));
655 static void dot_savegf
PARAMS ((int));
656 static void dot_spill
PARAMS ((int));
657 static void dot_spillreg
PARAMS ((int));
658 static void dot_spillmem
PARAMS ((int));
659 static void dot_spillreg_p
PARAMS ((int));
660 static void dot_spillmem_p
PARAMS ((int));
661 static void dot_label_state
PARAMS ((int));
662 static void dot_copy_state
PARAMS ((int));
663 static void dot_unwabi
PARAMS ((int));
664 static void dot_personality
PARAMS ((int));
665 static void dot_body
PARAMS ((int));
666 static void dot_prologue
PARAMS ((int));
667 static void dot_endp
PARAMS ((int));
668 static void dot_template
PARAMS ((int));
669 static void dot_regstk
PARAMS ((int));
670 static void dot_rot
PARAMS ((int));
671 static void dot_byteorder
PARAMS ((int));
672 static void dot_psr
PARAMS ((int));
673 static void dot_alias
PARAMS ((int));
674 static void dot_ln
PARAMS ((int));
675 static char *parse_section_name
PARAMS ((void));
676 static void dot_xdata
PARAMS ((int));
677 static void stmt_float_cons
PARAMS ((int));
678 static void stmt_cons_ua
PARAMS ((int));
679 static void dot_xfloat_cons
PARAMS ((int));
680 static void dot_xstringer
PARAMS ((int));
681 static void dot_xdata_ua
PARAMS ((int));
682 static void dot_xfloat_cons_ua
PARAMS ((int));
683 static void print_prmask
PARAMS ((valueT mask
));
684 static void dot_pred_rel
PARAMS ((int));
685 static void dot_reg_val
PARAMS ((int));
686 static void dot_dv_mode
PARAMS ((int));
687 static void dot_entry
PARAMS ((int));
688 static void dot_mem_offset
PARAMS ((int));
689 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
690 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
691 static void declare_register_set
PARAMS ((const char *, int, int));
692 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
693 static int operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
694 int index
, expressionS
*e
));
695 static int parse_operand
PARAMS ((expressionS
*e
));
696 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
697 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
698 static void emit_one_bundle
PARAMS ((void));
699 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
700 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
701 bfd_reloc_code_real_type r_type
));
702 static void insn_group_break
PARAMS ((int, int, int));
703 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
704 struct rsrc
*, int depind
, int path
));
705 static void add_qp_mutex
PARAMS((valueT mask
));
706 static void add_qp_imply
PARAMS((int p1
, int p2
));
707 static void clear_qp_branch_flag
PARAMS((valueT mask
));
708 static void clear_qp_mutex
PARAMS((valueT mask
));
709 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
710 static void clear_register_values
PARAMS ((void));
711 static void print_dependency
PARAMS ((const char *action
, int depind
));
712 static void instruction_serialization
PARAMS ((void));
713 static void data_serialization
PARAMS ((void));
714 static void remove_marked_resource
PARAMS ((struct rsrc
*));
715 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
716 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
717 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
718 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
719 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
720 struct ia64_opcode
*, int, struct rsrc
[], int, int));
721 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
722 static void check_dependencies
PARAMS((struct ia64_opcode
*));
723 static void mark_resources
PARAMS((struct ia64_opcode
*));
724 static void update_dependencies
PARAMS((struct ia64_opcode
*));
725 static void note_register_values
PARAMS((struct ia64_opcode
*));
726 static int qp_mutex
PARAMS ((int, int, int));
727 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
728 static void output_vbyte_mem
PARAMS ((int, char *, char *));
729 static void count_output
PARAMS ((int, char *, char *));
730 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
731 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
732 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
733 static void output_P1_format
PARAMS ((vbyte_func
, int));
734 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
735 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
736 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
737 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
738 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
739 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
740 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
741 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
742 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
743 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
744 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
745 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
746 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
747 static char format_ab_reg
PARAMS ((int, int));
748 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
750 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
751 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
753 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
754 static void free_list_records
PARAMS ((unw_rec_list
*));
755 static unw_rec_list
*output_prologue
PARAMS ((void));
756 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
757 static unw_rec_list
*output_body
PARAMS ((void));
758 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
759 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
760 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
761 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
762 static unw_rec_list
*output_rp_when
PARAMS ((void));
763 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
764 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
765 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
766 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
767 static unw_rec_list
*output_pfs_when
PARAMS ((void));
768 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
769 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
770 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
771 static unw_rec_list
*output_preds_when
PARAMS ((void));
772 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
773 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
774 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
775 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
776 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
777 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
778 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
779 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
780 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
781 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
782 static unw_rec_list
*output_unat_when
PARAMS ((void));
783 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
784 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
785 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
786 static unw_rec_list
*output_lc_when
PARAMS ((void));
787 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
788 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
789 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
790 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
791 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
792 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
793 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
794 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
795 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
796 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
797 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
798 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
799 static unw_rec_list
*output_bsp_when
PARAMS ((void));
800 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
801 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
802 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
803 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
804 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
805 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
806 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
807 static unw_rec_list
*output_rnat_when
PARAMS ((void));
808 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
809 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
810 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
811 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
812 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
813 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
814 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
815 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
816 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
817 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
819 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
821 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
823 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
824 unsigned int, unsigned int));
825 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
826 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
827 static int calc_record_size
PARAMS ((unw_rec_list
*));
828 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
829 static int count_bits
PARAMS ((unsigned long));
830 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
831 unsigned long, fragS
*));
832 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
833 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
834 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
835 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
836 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
837 static int generate_unwind_image
PARAMS ((const char *));
839 /* Build the unwind section name by appending the (possibly stripped)
840 text section NAME to the unwind PREFIX. The resulting string
841 pointer is assigned to RESULT. The string is allocated on the
842 stack, so this must be a macro... */
843 #define make_unw_section_name(special, text_name, result) \
845 char *_prefix = special_section_name[special]; \
846 size_t _prefix_len = strlen (_prefix), _text_len = strlen (text_name); \
847 char *_result = alloca (_prefix_len + _text_len + 1); \
848 memcpy(_result, _prefix, _prefix_len); \
849 memcpy(_result + _prefix_len, text_name, _text_len); \
850 _result[_prefix_len + _text_len] = '\0'; \
855 /* Determine if application register REGNUM resides in the integer
856 unit (as opposed to the memory unit). */
858 ar_is_in_integer_unit (reg
)
863 return (reg
== 64 /* pfs */
864 || reg
== 65 /* lc */
865 || reg
== 66 /* ec */
866 /* ??? ias accepts and puts these in the integer unit. */
867 || (reg
>= 112 && reg
<= 127));
870 /* Switch to section NAME and create section if necessary. It's
871 rather ugly that we have to manipulate input_line_pointer but I
872 don't see any other way to accomplish the same thing without
873 changing obj-elf.c (which may be the Right Thing, in the end). */
878 char *saved_input_line_pointer
;
880 saved_input_line_pointer
= input_line_pointer
;
881 input_line_pointer
= name
;
883 input_line_pointer
= saved_input_line_pointer
;
886 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
889 ia64_elf_section_flags (flags
, attr
, type
)
891 int attr
, type ATTRIBUTE_UNUSED
;
893 if (attr
& SHF_IA_64_SHORT
)
894 flags
|= SEC_SMALL_DATA
;
899 ia64_elf_section_type (str
, len
)
903 len
= sizeof (ELF_STRING_ia64_unwind_info
) - 1;
904 if (strncmp (str
, ELF_STRING_ia64_unwind_info
, len
) == 0)
907 len
= sizeof (ELF_STRING_ia64_unwind
) - 1;
908 if (strncmp (str
, ELF_STRING_ia64_unwind
, len
) == 0)
909 return SHT_IA_64_UNWIND
;
915 set_regstack (ins
, locs
, outs
, rots
)
916 unsigned int ins
, locs
, outs
, rots
;
921 sof
= ins
+ locs
+ outs
;
924 as_bad ("Size of frame exceeds maximum of 96 registers");
929 as_warn ("Size of rotating registers exceeds frame size");
932 md
.in
.base
= REG_GR
+ 32;
933 md
.loc
.base
= md
.in
.base
+ ins
;
934 md
.out
.base
= md
.loc
.base
+ locs
;
936 md
.in
.num_regs
= ins
;
937 md
.loc
.num_regs
= locs
;
938 md
.out
.num_regs
= outs
;
939 md
.rot
.num_regs
= rots
;
946 struct label_fix
*lfix
;
948 subsegT saved_subseg
;
951 if (!md
.last_text_seg
)
955 saved_subseg
= now_subseg
;
957 subseg_set (md
.last_text_seg
, 0);
959 while (md
.num_slots_in_use
> 0)
960 emit_one_bundle (); /* force out queued instructions */
962 /* In case there are labels following the last instruction, resolve
964 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
966 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
967 symbol_set_frag (lfix
->sym
, frag_now
);
969 CURR_SLOT
.label_fixups
= 0;
970 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
972 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
973 symbol_set_frag (lfix
->sym
, frag_now
);
975 CURR_SLOT
.tag_fixups
= 0;
977 /* In case there are unwind directives following the last instruction,
978 resolve those now. We only handle body and prologue directives here.
979 Give an error for others. */
980 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
982 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
983 || ptr
->r
.type
== body
)
985 ptr
->slot_number
= (unsigned long) frag_more (0);
986 ptr
->slot_frag
= frag_now
;
989 as_bad (_("Unwind directive not followed by an instruction."));
991 unwind
.current_entry
= NULL
;
993 subseg_set (saved_seg
, saved_subseg
);
995 if (md
.qp
.X_op
== O_register
)
996 as_bad ("qualifying predicate not followed by instruction");
1000 ia64_do_align (nbytes
)
1003 char *saved_input_line_pointer
= input_line_pointer
;
1005 input_line_pointer
= "";
1006 s_align_bytes (nbytes
);
1007 input_line_pointer
= saved_input_line_pointer
;
1011 ia64_cons_align (nbytes
)
1016 char *saved_input_line_pointer
= input_line_pointer
;
1017 input_line_pointer
= "";
1018 s_align_bytes (nbytes
);
1019 input_line_pointer
= saved_input_line_pointer
;
1023 /* Output COUNT bytes to a memory location. */
1024 static unsigned char *vbyte_mem_ptr
= NULL
;
1027 output_vbyte_mem (count
, ptr
, comment
)
1030 char *comment ATTRIBUTE_UNUSED
;
1033 if (vbyte_mem_ptr
== NULL
)
1038 for (x
= 0; x
< count
; x
++)
1039 *(vbyte_mem_ptr
++) = ptr
[x
];
1042 /* Count the number of bytes required for records. */
1043 static int vbyte_count
= 0;
1045 count_output (count
, ptr
, comment
)
1047 char *ptr ATTRIBUTE_UNUSED
;
1048 char *comment ATTRIBUTE_UNUSED
;
1050 vbyte_count
+= count
;
1054 output_R1_format (f
, rtype
, rlen
)
1056 unw_record_type rtype
;
1063 output_R3_format (f
, rtype
, rlen
);
1069 else if (rtype
!= prologue
)
1070 as_bad ("record type is not valid");
1072 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1073 (*f
) (1, &byte
, NULL
);
1077 output_R2_format (f
, mask
, grsave
, rlen
)
1084 mask
= (mask
& 0x0f);
1085 grsave
= (grsave
& 0x7f);
1087 bytes
[0] = (UNW_R2
| (mask
>> 1));
1088 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1089 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1090 (*f
) (count
, bytes
, NULL
);
1094 output_R3_format (f
, rtype
, rlen
)
1096 unw_record_type rtype
;
1103 output_R1_format (f
, rtype
, rlen
);
1109 else if (rtype
!= prologue
)
1110 as_bad ("record type is not valid");
1111 bytes
[0] = (UNW_R3
| r
);
1112 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1113 (*f
) (count
+ 1, bytes
, NULL
);
1117 output_P1_format (f
, brmask
)
1122 byte
= UNW_P1
| (brmask
& 0x1f);
1123 (*f
) (1, &byte
, NULL
);
1127 output_P2_format (f
, brmask
, gr
)
1133 brmask
= (brmask
& 0x1f);
1134 bytes
[0] = UNW_P2
| (brmask
>> 1);
1135 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1136 (*f
) (2, bytes
, NULL
);
1140 output_P3_format (f
, rtype
, reg
)
1142 unw_record_type rtype
;
1187 as_bad ("Invalid record type for P3 format.");
1189 bytes
[0] = (UNW_P3
| (r
>> 1));
1190 bytes
[1] = (((r
& 1) << 7) | reg
);
1191 (*f
) (2, bytes
, NULL
);
1195 output_P4_format (f
, imask
, imask_size
)
1197 unsigned char *imask
;
1198 unsigned long imask_size
;
1201 (*f
) (imask_size
, imask
, NULL
);
1205 output_P5_format (f
, grmask
, frmask
)
1208 unsigned long frmask
;
1211 grmask
= (grmask
& 0x0f);
1214 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1215 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1216 bytes
[3] = (frmask
& 0x000000ff);
1217 (*f
) (4, bytes
, NULL
);
1221 output_P6_format (f
, rtype
, rmask
)
1223 unw_record_type rtype
;
1229 if (rtype
== gr_mem
)
1231 else if (rtype
!= fr_mem
)
1232 as_bad ("Invalid record type for format P6");
1233 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1234 (*f
) (1, &byte
, NULL
);
1238 output_P7_format (f
, rtype
, w1
, w2
)
1240 unw_record_type rtype
;
1247 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1252 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1302 bytes
[0] = (UNW_P7
| r
);
1303 (*f
) (count
, bytes
, NULL
);
1307 output_P8_format (f
, rtype
, t
)
1309 unw_record_type rtype
;
1348 case bspstore_psprel
:
1351 case bspstore_sprel
:
1363 case priunat_when_gr
:
1366 case priunat_psprel
:
1372 case priunat_when_mem
:
1379 count
+= output_leb128 (bytes
+ 2, t
, 0);
1380 (*f
) (count
, bytes
, NULL
);
1384 output_P9_format (f
, grmask
, gr
)
1391 bytes
[1] = (grmask
& 0x0f);
1392 bytes
[2] = (gr
& 0x7f);
1393 (*f
) (3, bytes
, NULL
);
1397 output_P10_format (f
, abi
, context
)
1404 bytes
[1] = (abi
& 0xff);
1405 bytes
[2] = (context
& 0xff);
1406 (*f
) (3, bytes
, NULL
);
1410 output_B1_format (f
, rtype
, label
)
1412 unw_record_type rtype
;
1413 unsigned long label
;
1419 output_B4_format (f
, rtype
, label
);
1422 if (rtype
== copy_state
)
1424 else if (rtype
!= label_state
)
1425 as_bad ("Invalid record type for format B1");
1427 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1428 (*f
) (1, &byte
, NULL
);
1432 output_B2_format (f
, ecount
, t
)
1434 unsigned long ecount
;
1441 output_B3_format (f
, ecount
, t
);
1444 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1445 count
+= output_leb128 (bytes
+ 1, t
, 0);
1446 (*f
) (count
, bytes
, NULL
);
1450 output_B3_format (f
, ecount
, t
)
1452 unsigned long ecount
;
1459 output_B2_format (f
, ecount
, t
);
1463 count
+= output_leb128 (bytes
+ 1, t
, 0);
1464 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1465 (*f
) (count
, bytes
, NULL
);
1469 output_B4_format (f
, rtype
, label
)
1471 unw_record_type rtype
;
1472 unsigned long label
;
1479 output_B1_format (f
, rtype
, label
);
1483 if (rtype
== copy_state
)
1485 else if (rtype
!= label_state
)
1486 as_bad ("Invalid record type for format B1");
1488 bytes
[0] = (UNW_B4
| (r
<< 3));
1489 count
+= output_leb128 (bytes
+ 1, label
, 0);
1490 (*f
) (count
, bytes
, NULL
);
1494 format_ab_reg (ab
, reg
)
1501 ret
= (ab
<< 5) | reg
;
1506 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1508 unw_record_type rtype
;
1518 if (rtype
== spill_sprel
)
1520 else if (rtype
!= spill_psprel
)
1521 as_bad ("Invalid record type for format X1");
1522 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1523 count
+= output_leb128 (bytes
+ 2, t
, 0);
1524 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1525 (*f
) (count
, bytes
, NULL
);
1529 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1538 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1539 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1540 count
+= output_leb128 (bytes
+ 3, t
, 0);
1541 (*f
) (count
, bytes
, NULL
);
1545 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1547 unw_record_type rtype
;
1558 if (rtype
== spill_sprel_p
)
1560 else if (rtype
!= spill_psprel_p
)
1561 as_bad ("Invalid record type for format X3");
1562 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1563 bytes
[2] = format_ab_reg (ab
, reg
);
1564 count
+= output_leb128 (bytes
+ 3, t
, 0);
1565 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1566 (*f
) (count
, bytes
, NULL
);
1570 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1580 bytes
[1] = (qp
& 0x3f);
1581 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1582 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1583 count
+= output_leb128 (bytes
+ 4, t
, 0);
1584 (*f
) (count
, bytes
, NULL
);
1587 /* This function allocates a record list structure, and initializes fields. */
1589 static unw_rec_list
*
1590 alloc_record (unw_record_type t
)
1593 ptr
= xmalloc (sizeof (*ptr
));
1595 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1600 /* This function frees an entire list of record structures. */
1603 free_list_records (unw_rec_list
*first
)
1606 for (ptr
= first
; ptr
!= NULL
;)
1608 unw_rec_list
*tmp
= ptr
;
1610 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1611 && tmp
->r
.record
.r
.mask
.i
)
1612 free (tmp
->r
.record
.r
.mask
.i
);
1619 static unw_rec_list
*
1622 unw_rec_list
*ptr
= alloc_record (prologue
);
1623 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1627 static unw_rec_list
*
1628 output_prologue_gr (saved_mask
, reg
)
1629 unsigned int saved_mask
;
1632 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1633 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1634 ptr
->r
.record
.r
.grmask
= saved_mask
;
1635 ptr
->r
.record
.r
.grsave
= reg
;
1639 static unw_rec_list
*
1642 unw_rec_list
*ptr
= alloc_record (body
);
1646 static unw_rec_list
*
1647 output_mem_stack_f (size
)
1650 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1651 ptr
->r
.record
.p
.size
= size
;
1655 static unw_rec_list
*
1656 output_mem_stack_v ()
1658 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1662 static unw_rec_list
*
1666 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1667 ptr
->r
.record
.p
.gr
= gr
;
1671 static unw_rec_list
*
1672 output_psp_sprel (offset
)
1673 unsigned int offset
;
1675 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1676 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1680 static unw_rec_list
*
1683 unw_rec_list
*ptr
= alloc_record (rp_when
);
1687 static unw_rec_list
*
1691 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1692 ptr
->r
.record
.p
.gr
= gr
;
1696 static unw_rec_list
*
1700 unw_rec_list
*ptr
= alloc_record (rp_br
);
1701 ptr
->r
.record
.p
.br
= br
;
1705 static unw_rec_list
*
1706 output_rp_psprel (offset
)
1707 unsigned int offset
;
1709 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1710 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1714 static unw_rec_list
*
1715 output_rp_sprel (offset
)
1716 unsigned int offset
;
1718 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1719 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1723 static unw_rec_list
*
1726 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1730 static unw_rec_list
*
1734 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1735 ptr
->r
.record
.p
.gr
= gr
;
1739 static unw_rec_list
*
1740 output_pfs_psprel (offset
)
1741 unsigned int offset
;
1743 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1744 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1748 static unw_rec_list
*
1749 output_pfs_sprel (offset
)
1750 unsigned int offset
;
1752 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1753 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1757 static unw_rec_list
*
1758 output_preds_when ()
1760 unw_rec_list
*ptr
= alloc_record (preds_when
);
1764 static unw_rec_list
*
1765 output_preds_gr (gr
)
1768 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1769 ptr
->r
.record
.p
.gr
= gr
;
1773 static unw_rec_list
*
1774 output_preds_psprel (offset
)
1775 unsigned int offset
;
1777 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1778 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1782 static unw_rec_list
*
1783 output_preds_sprel (offset
)
1784 unsigned int offset
;
1786 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1787 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1791 static unw_rec_list
*
1792 output_fr_mem (mask
)
1795 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1796 ptr
->r
.record
.p
.rmask
= mask
;
1800 static unw_rec_list
*
1801 output_frgr_mem (gr_mask
, fr_mask
)
1802 unsigned int gr_mask
;
1803 unsigned int fr_mask
;
1805 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1806 ptr
->r
.record
.p
.grmask
= gr_mask
;
1807 ptr
->r
.record
.p
.frmask
= fr_mask
;
1811 static unw_rec_list
*
1812 output_gr_gr (mask
, reg
)
1816 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1817 ptr
->r
.record
.p
.grmask
= mask
;
1818 ptr
->r
.record
.p
.gr
= reg
;
1822 static unw_rec_list
*
1823 output_gr_mem (mask
)
1826 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1827 ptr
->r
.record
.p
.rmask
= mask
;
1831 static unw_rec_list
*
1832 output_br_mem (unsigned int mask
)
1834 unw_rec_list
*ptr
= alloc_record (br_mem
);
1835 ptr
->r
.record
.p
.brmask
= mask
;
1839 static unw_rec_list
*
1840 output_br_gr (save_mask
, reg
)
1841 unsigned int save_mask
;
1844 unw_rec_list
*ptr
= alloc_record (br_gr
);
1845 ptr
->r
.record
.p
.brmask
= save_mask
;
1846 ptr
->r
.record
.p
.gr
= reg
;
1850 static unw_rec_list
*
1851 output_spill_base (offset
)
1852 unsigned int offset
;
1854 unw_rec_list
*ptr
= alloc_record (spill_base
);
1855 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1859 static unw_rec_list
*
1862 unw_rec_list
*ptr
= alloc_record (unat_when
);
1866 static unw_rec_list
*
1870 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1871 ptr
->r
.record
.p
.gr
= gr
;
1875 static unw_rec_list
*
1876 output_unat_psprel (offset
)
1877 unsigned int offset
;
1879 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1880 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1884 static unw_rec_list
*
1885 output_unat_sprel (offset
)
1886 unsigned int offset
;
1888 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1889 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1893 static unw_rec_list
*
1896 unw_rec_list
*ptr
= alloc_record (lc_when
);
1900 static unw_rec_list
*
1904 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1905 ptr
->r
.record
.p
.gr
= gr
;
1909 static unw_rec_list
*
1910 output_lc_psprel (offset
)
1911 unsigned int offset
;
1913 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1914 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1918 static unw_rec_list
*
1919 output_lc_sprel (offset
)
1920 unsigned int offset
;
1922 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1923 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1927 static unw_rec_list
*
1930 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1934 static unw_rec_list
*
1938 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1939 ptr
->r
.record
.p
.gr
= gr
;
1943 static unw_rec_list
*
1944 output_fpsr_psprel (offset
)
1945 unsigned int offset
;
1947 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1948 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1952 static unw_rec_list
*
1953 output_fpsr_sprel (offset
)
1954 unsigned int offset
;
1956 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1957 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1961 static unw_rec_list
*
1962 output_priunat_when_gr ()
1964 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1968 static unw_rec_list
*
1969 output_priunat_when_mem ()
1971 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1975 static unw_rec_list
*
1976 output_priunat_gr (gr
)
1979 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1980 ptr
->r
.record
.p
.gr
= gr
;
1984 static unw_rec_list
*
1985 output_priunat_psprel (offset
)
1986 unsigned int offset
;
1988 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1989 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1993 static unw_rec_list
*
1994 output_priunat_sprel (offset
)
1995 unsigned int offset
;
1997 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
1998 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2002 static unw_rec_list
*
2005 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2009 static unw_rec_list
*
2013 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2014 ptr
->r
.record
.p
.gr
= gr
;
2018 static unw_rec_list
*
2019 output_bsp_psprel (offset
)
2020 unsigned int offset
;
2022 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2023 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2027 static unw_rec_list
*
2028 output_bsp_sprel (offset
)
2029 unsigned int offset
;
2031 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2032 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2036 static unw_rec_list
*
2037 output_bspstore_when ()
2039 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2043 static unw_rec_list
*
2044 output_bspstore_gr (gr
)
2047 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2048 ptr
->r
.record
.p
.gr
= gr
;
2052 static unw_rec_list
*
2053 output_bspstore_psprel (offset
)
2054 unsigned int offset
;
2056 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2057 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2061 static unw_rec_list
*
2062 output_bspstore_sprel (offset
)
2063 unsigned int offset
;
2065 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2066 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2070 static unw_rec_list
*
2073 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2077 static unw_rec_list
*
2081 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2082 ptr
->r
.record
.p
.gr
= gr
;
2086 static unw_rec_list
*
2087 output_rnat_psprel (offset
)
2088 unsigned int offset
;
2090 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2091 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2095 static unw_rec_list
*
2096 output_rnat_sprel (offset
)
2097 unsigned int offset
;
2099 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2100 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2104 static unw_rec_list
*
2105 output_unwabi (abi
, context
)
2107 unsigned long context
;
2109 unw_rec_list
*ptr
= alloc_record (unwabi
);
2110 ptr
->r
.record
.p
.abi
= abi
;
2111 ptr
->r
.record
.p
.context
= context
;
2115 static unw_rec_list
*
2116 output_epilogue (unsigned long ecount
)
2118 unw_rec_list
*ptr
= alloc_record (epilogue
);
2119 ptr
->r
.record
.b
.ecount
= ecount
;
2123 static unw_rec_list
*
2124 output_label_state (unsigned long label
)
2126 unw_rec_list
*ptr
= alloc_record (label_state
);
2127 ptr
->r
.record
.b
.label
= label
;
2131 static unw_rec_list
*
2132 output_copy_state (unsigned long label
)
2134 unw_rec_list
*ptr
= alloc_record (copy_state
);
2135 ptr
->r
.record
.b
.label
= label
;
2139 static unw_rec_list
*
2140 output_spill_psprel (ab
, reg
, offset
)
2143 unsigned int offset
;
2145 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2146 ptr
->r
.record
.x
.ab
= ab
;
2147 ptr
->r
.record
.x
.reg
= reg
;
2148 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2152 static unw_rec_list
*
2153 output_spill_sprel (ab
, reg
, offset
)
2156 unsigned int offset
;
2158 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2159 ptr
->r
.record
.x
.ab
= ab
;
2160 ptr
->r
.record
.x
.reg
= reg
;
2161 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2165 static unw_rec_list
*
2166 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2169 unsigned int offset
;
2170 unsigned int predicate
;
2172 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2173 ptr
->r
.record
.x
.ab
= ab
;
2174 ptr
->r
.record
.x
.reg
= reg
;
2175 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2176 ptr
->r
.record
.x
.qp
= predicate
;
2180 static unw_rec_list
*
2181 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2184 unsigned int offset
;
2185 unsigned int predicate
;
2187 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2188 ptr
->r
.record
.x
.ab
= ab
;
2189 ptr
->r
.record
.x
.reg
= reg
;
2190 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2191 ptr
->r
.record
.x
.qp
= predicate
;
2195 static unw_rec_list
*
2196 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2199 unsigned int targ_reg
;
2202 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2203 ptr
->r
.record
.x
.ab
= ab
;
2204 ptr
->r
.record
.x
.reg
= reg
;
2205 ptr
->r
.record
.x
.treg
= targ_reg
;
2206 ptr
->r
.record
.x
.xy
= xy
;
2210 static unw_rec_list
*
2211 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2214 unsigned int targ_reg
;
2216 unsigned int predicate
;
2218 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2219 ptr
->r
.record
.x
.ab
= ab
;
2220 ptr
->r
.record
.x
.reg
= reg
;
2221 ptr
->r
.record
.x
.treg
= targ_reg
;
2222 ptr
->r
.record
.x
.xy
= xy
;
2223 ptr
->r
.record
.x
.qp
= predicate
;
2227 /* Given a unw_rec_list process the correct format with the
2228 specified function. */
2231 process_one_record (ptr
, f
)
2235 unsigned long fr_mask
, gr_mask
;
2237 switch (ptr
->r
.type
)
2243 /* These are taken care of by prologue/prologue_gr. */
2248 if (ptr
->r
.type
== prologue_gr
)
2249 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2250 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2252 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2254 /* Output descriptor(s) for union of register spills (if any). */
2255 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2256 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2259 if ((fr_mask
& ~0xfUL
) == 0)
2260 output_P6_format (f
, fr_mem
, fr_mask
);
2263 output_P5_format (f
, gr_mask
, fr_mask
);
2268 output_P6_format (f
, gr_mem
, gr_mask
);
2269 if (ptr
->r
.record
.r
.mask
.br_mem
)
2270 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2272 /* output imask descriptor if necessary: */
2273 if (ptr
->r
.record
.r
.mask
.i
)
2274 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2275 ptr
->r
.record
.r
.imask_size
);
2279 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2283 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2284 ptr
->r
.record
.p
.size
);
2297 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2300 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2303 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2311 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2320 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2330 case bspstore_sprel
:
2332 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2335 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2338 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2341 as_bad ("spill_mask record unimplemented.");
2343 case priunat_when_gr
:
2344 case priunat_when_mem
:
2348 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2350 case priunat_psprel
:
2352 case bspstore_psprel
:
2354 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2357 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2360 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2364 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2367 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2368 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2369 ptr
->r
.record
.x
.pspoff
);
2372 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2373 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2374 ptr
->r
.record
.x
.spoff
);
2377 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2378 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2379 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2381 case spill_psprel_p
:
2382 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2383 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2384 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2387 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2388 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2389 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2392 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2393 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2394 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2398 as_bad ("record_type_not_valid");
2403 /* Given a unw_rec_list list, process all the records with
2404 the specified function. */
2406 process_unw_records (list
, f
)
2411 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2412 process_one_record (ptr
, f
);
2415 /* Determine the size of a record list in bytes. */
2417 calc_record_size (list
)
2421 process_unw_records (list
, count_output
);
2425 /* Update IMASK bitmask to reflect the fact that one or more registers
2426 of type TYPE are saved starting at instruction with index T. If N
2427 bits are set in REGMASK, it is assumed that instructions T through
2428 T+N-1 save these registers.
2432 1: instruction saves next fp reg
2433 2: instruction saves next general reg
2434 3: instruction saves next branch reg */
2436 set_imask (region
, regmask
, t
, type
)
2437 unw_rec_list
*region
;
2438 unsigned long regmask
;
2442 unsigned char *imask
;
2443 unsigned long imask_size
;
2447 imask
= region
->r
.record
.r
.mask
.i
;
2448 imask_size
= region
->r
.record
.r
.imask_size
;
2451 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2452 imask
= xmalloc (imask_size
);
2453 memset (imask
, 0, imask_size
);
2455 region
->r
.record
.r
.imask_size
= imask_size
;
2456 region
->r
.record
.r
.mask
.i
= imask
;
2460 pos
= 2 * (3 - t
% 4);
2463 if (i
>= imask_size
)
2465 as_bad ("Ignoring attempt to spill beyond end of region");
2469 imask
[i
] |= (type
& 0x3) << pos
;
2471 regmask
&= (regmask
- 1);
2482 count_bits (unsigned long mask
)
2494 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2495 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2496 containing FIRST_ADDR. */
2499 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2500 unsigned long slot_addr
;
2502 unsigned long first_addr
;
2505 unsigned long index
= 0;
2507 /* First time we are called, the initial address and frag are invalid. */
2508 if (first_addr
== 0)
2511 /* If the two addresses are in different frags, then we need to add in
2512 the remaining size of this frag, and then the entire size of intermediate
2514 while (slot_frag
!= first_frag
)
2516 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2518 /* Add in the full size of the frag converted to instruction slots. */
2519 index
+= 3 * (first_frag
->fr_fix
>> 4);
2520 /* Subtract away the initial part before first_addr. */
2521 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2522 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2524 /* Move to the beginning of the next frag. */
2525 first_frag
= first_frag
->fr_next
;
2526 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2529 /* Add in the used part of the last frag. */
2530 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2531 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2535 /* Optimize unwind record directives. */
2537 static unw_rec_list
*
2538 optimize_unw_records (list
)
2544 /* If the only unwind record is ".prologue" or ".prologue" followed
2545 by ".body", then we can optimize the unwind directives away. */
2546 if (list
->r
.type
== prologue
2547 && (list
->next
== NULL
2548 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2554 /* Given a complete record list, process any records which have
2555 unresolved fields, (ie length counts for a prologue). After
2556 this has been run, all neccessary information should be available
2557 within each record to generate an image. */
2560 fixup_unw_records (list
)
2563 unw_rec_list
*ptr
, *region
= 0;
2564 unsigned long first_addr
= 0, rlen
= 0, t
;
2565 fragS
*first_frag
= 0;
2567 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2569 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2570 as_bad (" Insn slot not set in unwind record.");
2571 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2572 first_addr
, first_frag
);
2573 switch (ptr
->r
.type
)
2580 int size
, dir_len
= 0;
2581 unsigned long last_addr
;
2584 first_addr
= ptr
->slot_number
;
2585 first_frag
= ptr
->slot_frag
;
2586 ptr
->slot_number
= 0;
2587 /* Find either the next body/prologue start, or the end of
2588 the list, and determine the size of the region. */
2589 last_addr
= unwind
.next_slot_number
;
2590 last_frag
= unwind
.next_slot_frag
;
2591 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2592 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2593 || last
->r
.type
== body
)
2595 last_addr
= last
->slot_number
;
2596 last_frag
= last
->slot_frag
;
2599 else if (!last
->next
)
2601 /* In the absence of an explicit .body directive,
2602 the prologue ends after the last instruction
2603 covered by an unwind directive. */
2604 if (ptr
->r
.type
!= body
)
2606 last_addr
= last
->slot_number
;
2607 last_frag
= last
->slot_frag
;
2608 switch (last
->r
.type
)
2611 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2612 + count_bits (last
->r
.record
.p
.grmask
));
2616 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2620 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2623 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2632 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2634 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2639 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2650 case priunat_when_gr
:
2651 case priunat_when_mem
:
2655 ptr
->r
.record
.p
.t
= t
;
2663 case spill_psprel_p
:
2664 ptr
->r
.record
.x
.t
= t
;
2670 as_bad ("frgr_mem record before region record!\n");
2673 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2674 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2675 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2676 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2681 as_bad ("fr_mem record before region record!\n");
2684 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2685 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2690 as_bad ("gr_mem record before region record!\n");
2693 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2694 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2699 as_bad ("br_mem record before region record!\n");
2702 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2703 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2709 as_bad ("gr_gr record before region record!\n");
2712 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2717 as_bad ("br_gr record before region record!\n");
2720 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2729 /* Generate an unwind image from a record list. Returns the number of
2730 bytes in the resulting image. The memory image itselof is returned
2731 in the 'ptr' parameter. */
2733 output_unw_records (list
, ptr
)
2737 int size
, x
, extra
= 0;
2742 list
= optimize_unw_records (list
);
2743 fixup_unw_records (list
);
2744 size
= calc_record_size (list
);
2746 /* pad to 8 byte boundry. */
2751 if (size
> 0 || unwind
.force_unwind_entry
)
2753 unwind
.force_unwind_entry
= 0;
2755 /* Add 8 for the header + 8 more bytes for the personality offset. */
2756 mem
= xmalloc (size
+ extra
+ 16);
2758 vbyte_mem_ptr
= mem
+ 8;
2759 /* Clear the padding area and personality. */
2760 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2761 /* Initialize the header area. */
2762 md_number_to_chars (mem
,
2763 (((bfd_vma
) 1 << 48) /* version */
2764 | (unwind
.personality_routine
2765 ? ((bfd_vma
) 3 << 32) /* U & E handler flags */
2767 | ((size
+ extra
) / 8)), /* length (dwords) */
2770 process_unw_records (list
, output_vbyte_mem
);
2780 convert_expr_to_ab_reg (e
, ab
, regp
)
2787 if (e
->X_op
!= O_register
)
2790 reg
= e
->X_add_number
;
2791 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2794 *regp
= reg
- REG_GR
;
2796 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2797 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2800 *regp
= reg
- REG_FR
;
2802 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2805 *regp
= reg
- REG_BR
;
2812 case REG_PR
: *regp
= 0; break;
2813 case REG_PSP
: *regp
= 1; break;
2814 case REG_PRIUNAT
: *regp
= 2; break;
2815 case REG_BR
+ 0: *regp
= 3; break;
2816 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2817 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2818 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2819 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2820 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2821 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2822 case REG_AR
+ AR_LC
: *regp
= 10; break;
2832 convert_expr_to_xy_reg (e
, xy
, regp
)
2839 if (e
->X_op
!= O_register
)
2842 reg
= e
->X_add_number
;
2844 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2847 *regp
= reg
- REG_GR
;
2849 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2852 *regp
= reg
- REG_FR
;
2854 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2857 *regp
= reg
- REG_BR
;
2866 int dummy ATTRIBUTE_UNUSED
;
2871 radix
= *input_line_pointer
++;
2873 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2875 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2876 ignore_rest_of_line ();
2881 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2883 dot_special_section (which
)
2886 set_section ((char *) special_section_name
[which
]);
2890 add_unwind_entry (ptr
)
2894 unwind
.tail
->next
= ptr
;
2899 /* The current entry can in fact be a chain of unwind entries. */
2900 if (unwind
.current_entry
== NULL
)
2901 unwind
.current_entry
= ptr
;
2906 int dummy ATTRIBUTE_UNUSED
;
2912 if (e
.X_op
!= O_constant
)
2913 as_bad ("Operand to .fframe must be a constant");
2915 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2920 int dummy ATTRIBUTE_UNUSED
;
2926 reg
= e
.X_add_number
- REG_GR
;
2927 if (e
.X_op
== O_register
&& reg
< 128)
2929 add_unwind_entry (output_mem_stack_v ());
2930 if (! (unwind
.prologue_mask
& 2))
2931 add_unwind_entry (output_psp_gr (reg
));
2934 as_bad ("First operand to .vframe must be a general register");
2938 dot_vframesp (dummy
)
2939 int dummy ATTRIBUTE_UNUSED
;
2944 if (e
.X_op
== O_constant
)
2946 add_unwind_entry (output_mem_stack_v ());
2947 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2950 as_bad ("First operand to .vframesp must be a general register");
2954 dot_vframepsp (dummy
)
2955 int dummy ATTRIBUTE_UNUSED
;
2960 if (e
.X_op
== O_constant
)
2962 add_unwind_entry (output_mem_stack_v ());
2963 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2966 as_bad ("First operand to .vframepsp must be a general register");
2971 int dummy ATTRIBUTE_UNUSED
;
2977 sep
= parse_operand (&e1
);
2979 as_bad ("No second operand to .save");
2980 sep
= parse_operand (&e2
);
2982 reg1
= e1
.X_add_number
;
2983 reg2
= e2
.X_add_number
- REG_GR
;
2985 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2986 if (e1
.X_op
== O_register
)
2988 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
2992 case REG_AR
+ AR_BSP
:
2993 add_unwind_entry (output_bsp_when ());
2994 add_unwind_entry (output_bsp_gr (reg2
));
2996 case REG_AR
+ AR_BSPSTORE
:
2997 add_unwind_entry (output_bspstore_when ());
2998 add_unwind_entry (output_bspstore_gr (reg2
));
3000 case REG_AR
+ AR_RNAT
:
3001 add_unwind_entry (output_rnat_when ());
3002 add_unwind_entry (output_rnat_gr (reg2
));
3004 case REG_AR
+ AR_UNAT
:
3005 add_unwind_entry (output_unat_when ());
3006 add_unwind_entry (output_unat_gr (reg2
));
3008 case REG_AR
+ AR_FPSR
:
3009 add_unwind_entry (output_fpsr_when ());
3010 add_unwind_entry (output_fpsr_gr (reg2
));
3012 case REG_AR
+ AR_PFS
:
3013 add_unwind_entry (output_pfs_when ());
3014 if (! (unwind
.prologue_mask
& 4))
3015 add_unwind_entry (output_pfs_gr (reg2
));
3017 case REG_AR
+ AR_LC
:
3018 add_unwind_entry (output_lc_when ());
3019 add_unwind_entry (output_lc_gr (reg2
));
3022 add_unwind_entry (output_rp_when ());
3023 if (! (unwind
.prologue_mask
& 8))
3024 add_unwind_entry (output_rp_gr (reg2
));
3027 add_unwind_entry (output_preds_when ());
3028 if (! (unwind
.prologue_mask
& 1))
3029 add_unwind_entry (output_preds_gr (reg2
));
3032 add_unwind_entry (output_priunat_when_gr ());
3033 add_unwind_entry (output_priunat_gr (reg2
));
3036 as_bad ("First operand not a valid register");
3040 as_bad (" Second operand not a valid register");
3043 as_bad ("First operand not a register");
3048 int dummy ATTRIBUTE_UNUSED
;
3051 unsigned long ecount
; /* # of _additional_ regions to pop */
3054 sep
= parse_operand (&e1
);
3055 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3057 as_bad ("First operand to .restore must be stack pointer (sp)");
3063 parse_operand (&e2
);
3064 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3066 as_bad ("Second operand to .restore must be a constant >= 0");
3069 ecount
= e2
.X_add_number
;
3072 ecount
= unwind
.prologue_count
- 1;
3073 add_unwind_entry (output_epilogue (ecount
));
3075 if (ecount
< unwind
.prologue_count
)
3076 unwind
.prologue_count
-= ecount
+ 1;
3078 unwind
.prologue_count
= 0;
3082 dot_restorereg (dummy
)
3083 int dummy ATTRIBUTE_UNUSED
;
3085 unsigned int ab
, reg
;
3090 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3092 as_bad ("First operand to .restorereg must be a preserved register");
3095 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3099 dot_restorereg_p (dummy
)
3100 int dummy ATTRIBUTE_UNUSED
;
3102 unsigned int qp
, ab
, reg
;
3106 sep
= parse_operand (&e1
);
3109 as_bad ("No second operand to .restorereg.p");
3113 parse_operand (&e2
);
3115 qp
= e1
.X_add_number
- REG_P
;
3116 if (e1
.X_op
!= O_register
|| qp
> 63)
3118 as_bad ("First operand to .restorereg.p must be a predicate");
3122 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3124 as_bad ("Second operand to .restorereg.p must be a preserved register");
3127 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3131 generate_unwind_image (text_name
)
3132 const char *text_name
;
3135 unsigned char *unw_rec
;
3137 /* Force out pending instructions, to make sure all unwind records have
3138 a valid slot_number field. */
3139 ia64_flush_insns ();
3141 /* Generate the unwind record. */
3142 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3144 as_bad ("Unwind record is not a multiple of 8 bytes.");
3146 /* If there are unwind records, switch sections, and output the info. */
3149 unsigned char *where
;
3153 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3154 set_section (sec_name
);
3155 bfd_set_section_flags (stdoutput
, now_seg
,
3156 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3158 /* Make sure the section has 8 byte alignment. */
3159 record_alignment (now_seg
, 3);
3161 /* Set expression which points to start of unwind descriptor area. */
3162 unwind
.info
= expr_build_dot ();
3164 where
= (unsigned char *) frag_more (size
);
3166 /* Issue a label for this address, and keep track of it to put it
3167 in the unwind section. */
3169 /* Copy the information from the unwind record into this section. The
3170 data is already in the correct byte order. */
3171 memcpy (where
, unw_rec
, size
);
3173 /* Add the personality address to the image. */
3174 if (unwind
.personality_routine
!= 0)
3176 exp
.X_op
= O_symbol
;
3177 exp
.X_add_symbol
= unwind
.personality_routine
;
3178 exp
.X_add_number
= 0;
3179 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
3180 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
3181 unwind
.personality_routine
= 0;
3185 free_list_records (unwind
.list
);
3186 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3192 dot_handlerdata (dummy
)
3193 int dummy ATTRIBUTE_UNUSED
;
3195 const char *text_name
= segment_name (now_seg
);
3197 /* If text section name starts with ".text" (which it should),
3198 strip this prefix off. */
3199 if (strcmp (text_name
, ".text") == 0)
3202 unwind
.force_unwind_entry
= 1;
3204 /* Remember which segment we're in so we can switch back after .endp */
3205 unwind
.saved_text_seg
= now_seg
;
3206 unwind
.saved_text_subseg
= now_subseg
;
3208 /* Generate unwind info into unwind-info section and then leave that
3209 section as the currently active one so dataXX directives go into
3210 the language specific data area of the unwind info block. */
3211 generate_unwind_image (text_name
);
3212 demand_empty_rest_of_line ();
3216 dot_unwentry (dummy
)
3217 int dummy ATTRIBUTE_UNUSED
;
3219 unwind
.force_unwind_entry
= 1;
3220 demand_empty_rest_of_line ();
3225 int dummy ATTRIBUTE_UNUSED
;
3231 reg
= e
.X_add_number
- REG_BR
;
3232 if (e
.X_op
== O_register
&& reg
< 8)
3233 add_unwind_entry (output_rp_br (reg
));
3235 as_bad ("First operand not a valid branch register");
3239 dot_savemem (psprel
)
3246 sep
= parse_operand (&e1
);
3248 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3249 sep
= parse_operand (&e2
);
3251 reg1
= e1
.X_add_number
;
3252 val
= e2
.X_add_number
;
3254 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3255 if (e1
.X_op
== O_register
)
3257 if (e2
.X_op
== O_constant
)
3261 case REG_AR
+ AR_BSP
:
3262 add_unwind_entry (output_bsp_when ());
3263 add_unwind_entry ((psprel
3265 : output_bsp_sprel
) (val
));
3267 case REG_AR
+ AR_BSPSTORE
:
3268 add_unwind_entry (output_bspstore_when ());
3269 add_unwind_entry ((psprel
3270 ? output_bspstore_psprel
3271 : output_bspstore_sprel
) (val
));
3273 case REG_AR
+ AR_RNAT
:
3274 add_unwind_entry (output_rnat_when ());
3275 add_unwind_entry ((psprel
3276 ? output_rnat_psprel
3277 : output_rnat_sprel
) (val
));
3279 case REG_AR
+ AR_UNAT
:
3280 add_unwind_entry (output_unat_when ());
3281 add_unwind_entry ((psprel
3282 ? output_unat_psprel
3283 : output_unat_sprel
) (val
));
3285 case REG_AR
+ AR_FPSR
:
3286 add_unwind_entry (output_fpsr_when ());
3287 add_unwind_entry ((psprel
3288 ? output_fpsr_psprel
3289 : output_fpsr_sprel
) (val
));
3291 case REG_AR
+ AR_PFS
:
3292 add_unwind_entry (output_pfs_when ());
3293 add_unwind_entry ((psprel
3295 : output_pfs_sprel
) (val
));
3297 case REG_AR
+ AR_LC
:
3298 add_unwind_entry (output_lc_when ());
3299 add_unwind_entry ((psprel
3301 : output_lc_sprel
) (val
));
3304 add_unwind_entry (output_rp_when ());
3305 add_unwind_entry ((psprel
3307 : output_rp_sprel
) (val
));
3310 add_unwind_entry (output_preds_when ());
3311 add_unwind_entry ((psprel
3312 ? output_preds_psprel
3313 : output_preds_sprel
) (val
));
3316 add_unwind_entry (output_priunat_when_mem ());
3317 add_unwind_entry ((psprel
3318 ? output_priunat_psprel
3319 : output_priunat_sprel
) (val
));
3322 as_bad ("First operand not a valid register");
3326 as_bad (" Second operand not a valid constant");
3329 as_bad ("First operand not a register");
3334 int dummy ATTRIBUTE_UNUSED
;
3338 sep
= parse_operand (&e1
);
3340 parse_operand (&e2
);
3342 if (e1
.X_op
!= O_constant
)
3343 as_bad ("First operand to .save.g must be a constant.");
3346 int grmask
= e1
.X_add_number
;
3348 add_unwind_entry (output_gr_mem (grmask
));
3351 int reg
= e2
.X_add_number
- REG_GR
;
3352 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3353 add_unwind_entry (output_gr_gr (grmask
, reg
));
3355 as_bad ("Second operand is an invalid register.");
3362 int dummy ATTRIBUTE_UNUSED
;
3366 sep
= parse_operand (&e1
);
3368 if (e1
.X_op
!= O_constant
)
3369 as_bad ("Operand to .save.f must be a constant.");
3371 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3376 int dummy ATTRIBUTE_UNUSED
;
3383 sep
= parse_operand (&e1
);
3384 if (e1
.X_op
!= O_constant
)
3386 as_bad ("First operand to .save.b must be a constant.");
3389 brmask
= e1
.X_add_number
;
3393 sep
= parse_operand (&e2
);
3394 reg
= e2
.X_add_number
- REG_GR
;
3395 if (e2
.X_op
!= O_register
|| reg
> 127)
3397 as_bad ("Second operand to .save.b must be a general register.");
3400 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3403 add_unwind_entry (output_br_mem (brmask
));
3405 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3406 ignore_rest_of_line ();
3411 int dummy ATTRIBUTE_UNUSED
;
3415 sep
= parse_operand (&e1
);
3417 parse_operand (&e2
);
3419 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3420 as_bad ("Both operands of .save.gf must be constants.");
3423 int grmask
= e1
.X_add_number
;
3424 int frmask
= e2
.X_add_number
;
3425 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3431 int dummy ATTRIBUTE_UNUSED
;
3436 sep
= parse_operand (&e
);
3437 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3438 ignore_rest_of_line ();
3440 if (e
.X_op
!= O_constant
)
3441 as_bad ("Operand to .spill must be a constant");
3443 add_unwind_entry (output_spill_base (e
.X_add_number
));
3447 dot_spillreg (dummy
)
3448 int dummy ATTRIBUTE_UNUSED
;
3450 int sep
, ab
, xy
, reg
, treg
;
3453 sep
= parse_operand (&e1
);
3456 as_bad ("No second operand to .spillreg");
3460 parse_operand (&e2
);
3462 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3464 as_bad ("First operand to .spillreg must be a preserved register");
3468 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3470 as_bad ("Second operand to .spillreg must be a register");
3474 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3478 dot_spillmem (psprel
)
3484 sep
= parse_operand (&e1
);
3487 as_bad ("Second operand missing");
3491 parse_operand (&e2
);
3493 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3495 as_bad ("First operand to .spill%s must be a preserved register",
3496 psprel
? "psp" : "sp");
3500 if (e2
.X_op
!= O_constant
)
3502 as_bad ("Second operand to .spill%s must be a constant",
3503 psprel
? "psp" : "sp");
3508 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3510 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3514 dot_spillreg_p (dummy
)
3515 int dummy ATTRIBUTE_UNUSED
;
3517 int sep
, ab
, xy
, reg
, treg
;
3518 expressionS e1
, e2
, e3
;
3521 sep
= parse_operand (&e1
);
3524 as_bad ("No second and third operand to .spillreg.p");
3528 sep
= parse_operand (&e2
);
3531 as_bad ("No third operand to .spillreg.p");
3535 parse_operand (&e3
);
3537 qp
= e1
.X_add_number
- REG_P
;
3539 if (e1
.X_op
!= O_register
|| qp
> 63)
3541 as_bad ("First operand to .spillreg.p must be a predicate");
3545 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3547 as_bad ("Second operand to .spillreg.p must be a preserved register");
3551 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3553 as_bad ("Third operand to .spillreg.p must be a register");
3557 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3561 dot_spillmem_p (psprel
)
3564 expressionS e1
, e2
, e3
;
3568 sep
= parse_operand (&e1
);
3571 as_bad ("Second operand missing");
3575 parse_operand (&e2
);
3578 as_bad ("Second operand missing");
3582 parse_operand (&e3
);
3584 qp
= e1
.X_add_number
- REG_P
;
3585 if (e1
.X_op
!= O_register
|| qp
> 63)
3587 as_bad ("First operand to .spill%s_p must be a predicate",
3588 psprel
? "psp" : "sp");
3592 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3594 as_bad ("Second operand to .spill%s_p must be a preserved register",
3595 psprel
? "psp" : "sp");
3599 if (e3
.X_op
!= O_constant
)
3601 as_bad ("Third operand to .spill%s_p must be a constant",
3602 psprel
? "psp" : "sp");
3607 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3609 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3613 dot_label_state (dummy
)
3614 int dummy ATTRIBUTE_UNUSED
;
3619 if (e
.X_op
!= O_constant
)
3621 as_bad ("Operand to .label_state must be a constant");
3624 add_unwind_entry (output_label_state (e
.X_add_number
));
3628 dot_copy_state (dummy
)
3629 int dummy ATTRIBUTE_UNUSED
;
3634 if (e
.X_op
!= O_constant
)
3636 as_bad ("Operand to .copy_state must be a constant");
3639 add_unwind_entry (output_copy_state (e
.X_add_number
));
3644 int dummy ATTRIBUTE_UNUSED
;
3649 sep
= parse_operand (&e1
);
3652 as_bad ("Second operand to .unwabi missing");
3655 sep
= parse_operand (&e2
);
3656 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3657 ignore_rest_of_line ();
3659 if (e1
.X_op
!= O_constant
)
3661 as_bad ("First operand to .unwabi must be a constant");
3665 if (e2
.X_op
!= O_constant
)
3667 as_bad ("Second operand to .unwabi must be a constant");
3671 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3675 dot_personality (dummy
)
3676 int dummy ATTRIBUTE_UNUSED
;
3680 name
= input_line_pointer
;
3681 c
= get_symbol_end ();
3682 p
= input_line_pointer
;
3683 unwind
.personality_routine
= symbol_find_or_make (name
);
3684 unwind
.force_unwind_entry
= 1;
3687 demand_empty_rest_of_line ();
3692 int dummy ATTRIBUTE_UNUSED
;
3697 unwind
.proc_start
= expr_build_dot ();
3698 /* Parse names of main and alternate entry points and mark them as
3699 function symbols: */
3703 name
= input_line_pointer
;
3704 c
= get_symbol_end ();
3705 p
= input_line_pointer
;
3706 sym
= symbol_find_or_make (name
);
3707 if (unwind
.proc_start
== 0)
3709 unwind
.proc_start
= sym
;
3711 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3714 if (*input_line_pointer
!= ',')
3716 ++input_line_pointer
;
3718 demand_empty_rest_of_line ();
3721 unwind
.prologue_count
= 0;
3722 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3723 unwind
.personality_routine
= 0;
3728 int dummy ATTRIBUTE_UNUSED
;
3730 unwind
.prologue
= 0;
3731 unwind
.prologue_mask
= 0;
3733 add_unwind_entry (output_body ());
3734 demand_empty_rest_of_line ();
3738 dot_prologue (dummy
)
3739 int dummy ATTRIBUTE_UNUSED
;
3742 int mask
= 0, grsave
= 0;
3744 if (!is_it_end_of_statement ())
3747 sep
= parse_operand (&e1
);
3749 as_bad ("No second operand to .prologue");
3750 sep
= parse_operand (&e2
);
3751 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3752 ignore_rest_of_line ();
3754 if (e1
.X_op
== O_constant
)
3756 mask
= e1
.X_add_number
;
3758 if (e2
.X_op
== O_constant
)
3759 grsave
= e2
.X_add_number
;
3760 else if (e2
.X_op
== O_register
3761 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3764 as_bad ("Second operand not a constant or general register");
3766 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3769 as_bad ("First operand not a constant");
3772 add_unwind_entry (output_prologue ());
3774 unwind
.prologue
= 1;
3775 unwind
.prologue_mask
= mask
;
3776 ++unwind
.prologue_count
;
3781 int dummy ATTRIBUTE_UNUSED
;
3785 int bytes_per_address
;
3788 subsegT saved_subseg
;
3789 const char *sec_name
, *text_name
;
3791 if (unwind
.saved_text_seg
)
3793 saved_seg
= unwind
.saved_text_seg
;
3794 saved_subseg
= unwind
.saved_text_subseg
;
3795 unwind
.saved_text_seg
= NULL
;
3799 saved_seg
= now_seg
;
3800 saved_subseg
= now_subseg
;
3804 Use a slightly ugly scheme to derive the unwind section names from
3805 the text section name:
3807 text sect. unwind table sect.
3808 name: name: comments:
3809 ---------- ----------------- --------------------------------
3811 .text.foo .IA_64.unwind.text.foo
3812 .foo .IA_64.unwind.foo
3813 _info .IA_64.unwind_info gas issues error message (ditto)
3814 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
3816 This mapping is done so that:
3818 (a) An object file with unwind info only in .text will use
3819 unwind section names .IA_64.unwind and .IA_64.unwind_info.
3820 This follows the letter of the ABI and also ensures backwards
3821 compatibility with older toolchains.
3823 (b) An object file with unwind info in multiple text sections
3824 will use separate unwind sections for each text section.
3825 This allows us to properly set the "sh_info" and "sh_link"
3826 fields in SHT_IA_64_UNWIND as required by the ABI and also
3827 lets GNU ld support programs with multiple segments
3828 containing unwind info (as might be the case for certain
3829 embedded applications).
3831 (c) An error is issued if there would be a name clash.
3833 text_name
= segment_name (saved_seg
);
3834 if (strncmp (text_name
, "_info", 5) == 0)
3836 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
3838 ignore_rest_of_line ();
3841 if (strcmp (text_name
, ".text") == 0)
3845 demand_empty_rest_of_line ();
3847 insn_group_break (1, 0, 0);
3849 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
3851 generate_unwind_image (text_name
);
3853 if (unwind
.info
|| unwind
.force_unwind_entry
)
3855 subseg_set (md
.last_text_seg
, 0);
3856 unwind
.proc_end
= expr_build_dot ();
3858 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
3859 set_section ((char *) sec_name
);
3860 bfd_set_section_flags (stdoutput
, now_seg
,
3861 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3863 /* Make sure the section has 8 byte alignment. */
3864 record_alignment (now_seg
, 3);
3866 ptr
= frag_more (24);
3867 where
= frag_now_fix () - 24;
3868 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
3870 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3871 e
.X_op
= O_pseudo_fixup
;
3872 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3874 e
.X_add_symbol
= unwind
.proc_start
;
3875 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
3877 e
.X_op
= O_pseudo_fixup
;
3878 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3880 e
.X_add_symbol
= unwind
.proc_end
;
3881 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
3882 bytes_per_address
, &e
);
3886 e
.X_op
= O_pseudo_fixup
;
3887 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3889 e
.X_add_symbol
= unwind
.info
;
3890 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
3891 bytes_per_address
, &e
);
3894 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
3898 subseg_set (saved_seg
, saved_subseg
);
3899 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3903 dot_template (template)
3906 CURR_SLOT
.user_template
= template;
3911 int dummy ATTRIBUTE_UNUSED
;
3913 int ins
, locs
, outs
, rots
;
3915 if (is_it_end_of_statement ())
3916 ins
= locs
= outs
= rots
= 0;
3919 ins
= get_absolute_expression ();
3920 if (*input_line_pointer
++ != ',')
3922 locs
= get_absolute_expression ();
3923 if (*input_line_pointer
++ != ',')
3925 outs
= get_absolute_expression ();
3926 if (*input_line_pointer
++ != ',')
3928 rots
= get_absolute_expression ();
3930 set_regstack (ins
, locs
, outs
, rots
);
3934 as_bad ("Comma expected");
3935 ignore_rest_of_line ();
3942 unsigned num_regs
, num_alloced
= 0;
3943 struct dynreg
**drpp
, *dr
;
3944 int ch
, base_reg
= 0;
3950 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3951 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3952 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3956 /* First, remove existing names from hash table. */
3957 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3959 hash_delete (md
.dynreg_hash
, dr
->name
);
3963 drpp
= &md
.dynreg
[type
];
3966 start
= input_line_pointer
;
3967 ch
= get_symbol_end ();
3968 *input_line_pointer
= ch
;
3969 len
= (input_line_pointer
- start
);
3972 if (*input_line_pointer
!= '[')
3974 as_bad ("Expected '['");
3977 ++input_line_pointer
; /* skip '[' */
3979 num_regs
= get_absolute_expression ();
3981 if (*input_line_pointer
++ != ']')
3983 as_bad ("Expected ']'");
3988 num_alloced
+= num_regs
;
3992 if (num_alloced
> md
.rot
.num_regs
)
3994 as_bad ("Used more than the declared %d rotating registers",
4000 if (num_alloced
> 96)
4002 as_bad ("Used more than the available 96 rotating registers");
4007 if (num_alloced
> 48)
4009 as_bad ("Used more than the available 48 rotating registers");
4018 name
= obstack_alloc (¬es
, len
+ 1);
4019 memcpy (name
, start
, len
);
4024 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4025 memset (*drpp
, 0, sizeof (*dr
));
4030 dr
->num_regs
= num_regs
;
4031 dr
->base
= base_reg
;
4033 base_reg
+= num_regs
;
4035 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4037 as_bad ("Attempt to redefine register set `%s'", name
);
4041 if (*input_line_pointer
!= ',')
4043 ++input_line_pointer
; /* skip comma */
4046 demand_empty_rest_of_line ();
4050 ignore_rest_of_line ();
4054 dot_byteorder (byteorder
)
4057 target_big_endian
= byteorder
;
4062 int dummy ATTRIBUTE_UNUSED
;
4069 option
= input_line_pointer
;
4070 ch
= get_symbol_end ();
4071 if (strcmp (option
, "lsb") == 0)
4072 md
.flags
&= ~EF_IA_64_BE
;
4073 else if (strcmp (option
, "msb") == 0)
4074 md
.flags
|= EF_IA_64_BE
;
4075 else if (strcmp (option
, "abi32") == 0)
4076 md
.flags
&= ~EF_IA_64_ABI64
;
4077 else if (strcmp (option
, "abi64") == 0)
4078 md
.flags
|= EF_IA_64_ABI64
;
4080 as_bad ("Unknown psr option `%s'", option
);
4081 *input_line_pointer
= ch
;
4084 if (*input_line_pointer
!= ',')
4087 ++input_line_pointer
;
4090 demand_empty_rest_of_line ();
4095 int dummy ATTRIBUTE_UNUSED
;
4097 as_bad (".alias not implemented yet");
4102 int dummy ATTRIBUTE_UNUSED
;
4104 new_logical_line (0, get_absolute_expression ());
4105 demand_empty_rest_of_line ();
4109 parse_section_name ()
4115 if (*input_line_pointer
!= '"')
4117 as_bad ("Missing section name");
4118 ignore_rest_of_line ();
4121 name
= demand_copy_C_string (&len
);
4124 ignore_rest_of_line ();
4128 if (*input_line_pointer
!= ',')
4130 as_bad ("Comma expected after section name");
4131 ignore_rest_of_line ();
4134 ++input_line_pointer
; /* skip comma */
4142 char *name
= parse_section_name ();
4148 obj_elf_previous (0);
4151 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4154 stmt_float_cons (kind
)
4161 case 'd': size
= 8; break;
4162 case 'x': size
= 10; break;
4169 ia64_do_align (size
);
4177 int saved_auto_align
= md
.auto_align
;
4181 md
.auto_align
= saved_auto_align
;
4185 dot_xfloat_cons (kind
)
4188 char *name
= parse_section_name ();
4193 stmt_float_cons (kind
);
4194 obj_elf_previous (0);
4198 dot_xstringer (zero
)
4201 char *name
= parse_section_name ();
4207 obj_elf_previous (0);
4214 int saved_auto_align
= md
.auto_align
;
4215 char *name
= parse_section_name ();
4222 md
.auto_align
= saved_auto_align
;
4223 obj_elf_previous (0);
4227 dot_xfloat_cons_ua (kind
)
4230 int saved_auto_align
= md
.auto_align
;
4231 char *name
= parse_section_name ();
4237 stmt_float_cons (kind
);
4238 md
.auto_align
= saved_auto_align
;
4239 obj_elf_previous (0);
4242 /* .reg.val <regname>,value */
4246 int dummy ATTRIBUTE_UNUSED
;
4251 if (reg
.X_op
!= O_register
)
4253 as_bad (_("Register name expected"));
4254 ignore_rest_of_line ();
4256 else if (*input_line_pointer
++ != ',')
4258 as_bad (_("Comma expected"));
4259 ignore_rest_of_line ();
4263 valueT value
= get_absolute_expression ();
4264 int regno
= reg
.X_add_number
;
4265 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4266 as_warn (_("Register value annotation ignored"));
4269 gr_values
[regno
- REG_GR
].known
= 1;
4270 gr_values
[regno
- REG_GR
].value
= value
;
4271 gr_values
[regno
- REG_GR
].path
= md
.path
;
4274 demand_empty_rest_of_line ();
4277 /* select dv checking mode
4282 A stop is inserted when changing modes
4289 if (md
.manual_bundling
)
4290 as_warn (_("Directive invalid within a bundle"));
4292 if (type
== 'E' || type
== 'A')
4293 md
.mode_explicitly_set
= 0;
4295 md
.mode_explicitly_set
= 1;
4302 if (md
.explicit_mode
)
4303 insn_group_break (1, 0, 0);
4304 md
.explicit_mode
= 0;
4308 if (!md
.explicit_mode
)
4309 insn_group_break (1, 0, 0);
4310 md
.explicit_mode
= 1;
4314 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4315 insn_group_break (1, 0, 0);
4316 md
.explicit_mode
= md
.default_explicit_mode
;
4317 md
.mode_explicitly_set
= 0;
4328 for (regno
= 0; regno
< 64; regno
++)
4330 if (mask
& ((valueT
) 1 << regno
))
4332 fprintf (stderr
, "%s p%d", comma
, regno
);
4339 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4340 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4341 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4342 .pred.safe_across_calls p1 [, p2 [,...]]
4351 int p1
= -1, p2
= -1;
4355 if (*input_line_pointer
!= '"')
4357 as_bad (_("Missing predicate relation type"));
4358 ignore_rest_of_line ();
4364 char *form
= demand_copy_C_string (&len
);
4365 if (strcmp (form
, "mutex") == 0)
4367 else if (strcmp (form
, "clear") == 0)
4369 else if (strcmp (form
, "imply") == 0)
4373 as_bad (_("Unrecognized predicate relation type"));
4374 ignore_rest_of_line ();
4378 if (*input_line_pointer
== ',')
4379 ++input_line_pointer
;
4389 if (toupper (*input_line_pointer
) != 'P'
4390 || (regno
= atoi (++input_line_pointer
)) < 0
4393 as_bad (_("Predicate register expected"));
4394 ignore_rest_of_line ();
4397 while (isdigit (*input_line_pointer
))
4398 ++input_line_pointer
;
4405 as_warn (_("Duplicate predicate register ignored"));
4408 /* See if it's a range. */
4409 if (*input_line_pointer
== '-')
4412 ++input_line_pointer
;
4414 if (toupper (*input_line_pointer
) != 'P'
4415 || (regno
= atoi (++input_line_pointer
)) < 0
4418 as_bad (_("Predicate register expected"));
4419 ignore_rest_of_line ();
4422 while (isdigit (*input_line_pointer
))
4423 ++input_line_pointer
;
4427 as_bad (_("Bad register range"));
4428 ignore_rest_of_line ();
4439 if (*input_line_pointer
!= ',')
4441 ++input_line_pointer
;
4450 clear_qp_mutex (mask
);
4451 clear_qp_implies (mask
, (valueT
) 0);
4454 if (count
!= 2 || p1
== -1 || p2
== -1)
4455 as_bad (_("Predicate source and target required"));
4456 else if (p1
== 0 || p2
== 0)
4457 as_bad (_("Use of p0 is not valid in this context"));
4459 add_qp_imply (p1
, p2
);
4464 as_bad (_("At least two PR arguments expected"));
4469 as_bad (_("Use of p0 is not valid in this context"));
4472 add_qp_mutex (mask
);
4475 /* note that we don't override any existing relations */
4478 as_bad (_("At least one PR argument expected"));
4483 fprintf (stderr
, "Safe across calls: ");
4484 print_prmask (mask
);
4485 fprintf (stderr
, "\n");
4487 qp_safe_across_calls
= mask
;
4490 demand_empty_rest_of_line ();
4493 /* .entry label [, label [, ...]]
4494 Hint to DV code that the given labels are to be considered entry points.
4495 Otherwise, only global labels are considered entry points. */
4499 int dummy ATTRIBUTE_UNUSED
;
4508 name
= input_line_pointer
;
4509 c
= get_symbol_end ();
4510 symbolP
= symbol_find_or_make (name
);
4512 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4514 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4517 *input_line_pointer
= c
;
4519 c
= *input_line_pointer
;
4522 input_line_pointer
++;
4524 if (*input_line_pointer
== '\n')
4530 demand_empty_rest_of_line ();
4533 /* .mem.offset offset, base
4534 "base" is used to distinguish between offsets from a different base. */
4537 dot_mem_offset (dummy
)
4538 int dummy ATTRIBUTE_UNUSED
;
4540 md
.mem_offset
.hint
= 1;
4541 md
.mem_offset
.offset
= get_absolute_expression ();
4542 if (*input_line_pointer
!= ',')
4544 as_bad (_("Comma expected"));
4545 ignore_rest_of_line ();
4548 ++input_line_pointer
;
4549 md
.mem_offset
.base
= get_absolute_expression ();
4550 demand_empty_rest_of_line ();
4553 /* ia64-specific pseudo-ops: */
4554 const pseudo_typeS md_pseudo_table
[] =
4556 { "radix", dot_radix
, 0 },
4557 { "lcomm", s_lcomm_bytes
, 1 },
4558 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4559 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4560 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4561 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4562 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4563 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4564 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4565 { "proc", dot_proc
, 0 },
4566 { "body", dot_body
, 0 },
4567 { "prologue", dot_prologue
, 0 },
4568 { "endp", dot_endp
, 0 },
4569 { "file", dwarf2_directive_file
, 0 },
4570 { "loc", dwarf2_directive_loc
, 0 },
4572 { "fframe", dot_fframe
, 0 },
4573 { "vframe", dot_vframe
, 0 },
4574 { "vframesp", dot_vframesp
, 0 },
4575 { "vframepsp", dot_vframepsp
, 0 },
4576 { "save", dot_save
, 0 },
4577 { "restore", dot_restore
, 0 },
4578 { "restorereg", dot_restorereg
, 0 },
4579 { "restorereg.p", dot_restorereg_p
, 0 },
4580 { "handlerdata", dot_handlerdata
, 0 },
4581 { "unwentry", dot_unwentry
, 0 },
4582 { "altrp", dot_altrp
, 0 },
4583 { "savesp", dot_savemem
, 0 },
4584 { "savepsp", dot_savemem
, 1 },
4585 { "save.g", dot_saveg
, 0 },
4586 { "save.f", dot_savef
, 0 },
4587 { "save.b", dot_saveb
, 0 },
4588 { "save.gf", dot_savegf
, 0 },
4589 { "spill", dot_spill
, 0 },
4590 { "spillreg", dot_spillreg
, 0 },
4591 { "spillsp", dot_spillmem
, 0 },
4592 { "spillpsp", dot_spillmem
, 1 },
4593 { "spillreg.p", dot_spillreg_p
, 0 },
4594 { "spillsp.p", dot_spillmem_p
, 0 },
4595 { "spillpsp.p", dot_spillmem_p
, 1 },
4596 { "label_state", dot_label_state
, 0 },
4597 { "copy_state", dot_copy_state
, 0 },
4598 { "unwabi", dot_unwabi
, 0 },
4599 { "personality", dot_personality
, 0 },
4601 { "estate", dot_estate
, 0 },
4603 { "mii", dot_template
, 0x0 },
4604 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4605 { "mlx", dot_template
, 0x2 },
4606 { "mmi", dot_template
, 0x4 },
4607 { "mfi", dot_template
, 0x6 },
4608 { "mmf", dot_template
, 0x7 },
4609 { "mib", dot_template
, 0x8 },
4610 { "mbb", dot_template
, 0x9 },
4611 { "bbb", dot_template
, 0xb },
4612 { "mmb", dot_template
, 0xc },
4613 { "mfb", dot_template
, 0xe },
4615 { "lb", dot_scope
, 0 },
4616 { "le", dot_scope
, 1 },
4618 { "align", s_align_bytes
, 0 },
4619 { "regstk", dot_regstk
, 0 },
4620 { "rotr", dot_rot
, DYNREG_GR
},
4621 { "rotf", dot_rot
, DYNREG_FR
},
4622 { "rotp", dot_rot
, DYNREG_PR
},
4623 { "lsb", dot_byteorder
, 0 },
4624 { "msb", dot_byteorder
, 1 },
4625 { "psr", dot_psr
, 0 },
4626 { "alias", dot_alias
, 0 },
4627 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4629 { "xdata1", dot_xdata
, 1 },
4630 { "xdata2", dot_xdata
, 2 },
4631 { "xdata4", dot_xdata
, 4 },
4632 { "xdata8", dot_xdata
, 8 },
4633 { "xreal4", dot_xfloat_cons
, 'f' },
4634 { "xreal8", dot_xfloat_cons
, 'd' },
4635 { "xreal10", dot_xfloat_cons
, 'x' },
4636 { "xstring", dot_xstringer
, 0 },
4637 { "xstringz", dot_xstringer
, 1 },
4639 /* unaligned versions: */
4640 { "xdata2.ua", dot_xdata_ua
, 2 },
4641 { "xdata4.ua", dot_xdata_ua
, 4 },
4642 { "xdata8.ua", dot_xdata_ua
, 8 },
4643 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4644 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4645 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4647 /* annotations/DV checking support */
4648 { "entry", dot_entry
, 0 },
4649 { "mem.offset", dot_mem_offset
, 0 },
4650 { "pred.rel", dot_pred_rel
, 0 },
4651 { "pred.rel.clear", dot_pred_rel
, 'c' },
4652 { "pred.rel.imply", dot_pred_rel
, 'i' },
4653 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4654 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4655 { "reg.val", dot_reg_val
, 0 },
4656 { "auto", dot_dv_mode
, 'a' },
4657 { "explicit", dot_dv_mode
, 'e' },
4658 { "default", dot_dv_mode
, 'd' },
4663 static const struct pseudo_opcode
4666 void (*handler
) (int);
4671 /* these are more like pseudo-ops, but don't start with a dot */
4672 { "data1", cons
, 1 },
4673 { "data2", cons
, 2 },
4674 { "data4", cons
, 4 },
4675 { "data8", cons
, 8 },
4676 { "real4", stmt_float_cons
, 'f' },
4677 { "real8", stmt_float_cons
, 'd' },
4678 { "real10", stmt_float_cons
, 'x' },
4679 { "string", stringer
, 0 },
4680 { "stringz", stringer
, 1 },
4682 /* unaligned versions: */
4683 { "data2.ua", stmt_cons_ua
, 2 },
4684 { "data4.ua", stmt_cons_ua
, 4 },
4685 { "data8.ua", stmt_cons_ua
, 8 },
4686 { "real4.ua", float_cons
, 'f' },
4687 { "real8.ua", float_cons
, 'd' },
4688 { "real10.ua", float_cons
, 'x' },
4691 /* Declare a register by creating a symbol for it and entering it in
4692 the symbol table. */
4695 declare_register (name
, regnum
)
4702 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4704 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4706 as_fatal ("Inserting \"%s\" into register table failed: %s",
4713 declare_register_set (prefix
, num_regs
, base_regnum
)
4721 for (i
= 0; i
< num_regs
; ++i
)
4723 sprintf (name
, "%s%u", prefix
, i
);
4724 declare_register (name
, base_regnum
+ i
);
4729 operand_width (opnd
)
4730 enum ia64_opnd opnd
;
4732 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4733 unsigned int bits
= 0;
4737 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4738 bits
+= odesc
->field
[i
].bits
;
4744 operand_match (idesc
, index
, e
)
4745 const struct ia64_opcode
*idesc
;
4749 enum ia64_opnd opnd
= idesc
->operands
[index
];
4750 int bits
, relocatable
= 0;
4751 struct insn_fix
*fix
;
4758 case IA64_OPND_AR_CCV
:
4759 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4763 case IA64_OPND_AR_PFS
:
4764 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4769 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4774 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4779 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4783 case IA64_OPND_PR_ROT
:
4784 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4789 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4793 case IA64_OPND_PSR_L
:
4794 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4798 case IA64_OPND_PSR_UM
:
4799 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4804 if (e
->X_op
== O_constant
&& e
->X_add_number
== 1)
4809 if (e
->X_op
== O_constant
&& e
->X_add_number
== 8)
4814 if (e
->X_op
== O_constant
&& e
->X_add_number
== 16)
4818 /* register operands: */
4821 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4822 && e
->X_add_number
< REG_AR
+ 128)
4828 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4829 && e
->X_add_number
< REG_BR
+ 8)
4834 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4835 && e
->X_add_number
< REG_CR
+ 128)
4843 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4844 && e
->X_add_number
< REG_FR
+ 128)
4850 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4851 && e
->X_add_number
< REG_P
+ 64)
4858 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4859 && e
->X_add_number
< REG_GR
+ 128)
4863 case IA64_OPND_R3_2
:
4864 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4865 && e
->X_add_number
< REG_GR
+ 4)
4869 /* indirect operands: */
4870 case IA64_OPND_CPUID_R3
:
4871 case IA64_OPND_DBR_R3
:
4872 case IA64_OPND_DTR_R3
:
4873 case IA64_OPND_ITR_R3
:
4874 case IA64_OPND_IBR_R3
:
4875 case IA64_OPND_MSR_R3
:
4876 case IA64_OPND_PKR_R3
:
4877 case IA64_OPND_PMC_R3
:
4878 case IA64_OPND_PMD_R3
:
4879 case IA64_OPND_RR_R3
:
4880 if (e
->X_op
== O_index
&& e
->X_op_symbol
4881 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4882 == opnd
- IA64_OPND_CPUID_R3
))
4887 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4891 /* immediate operands: */
4892 case IA64_OPND_CNT2a
:
4893 case IA64_OPND_LEN4
:
4894 case IA64_OPND_LEN6
:
4895 bits
= operand_width (idesc
->operands
[index
]);
4896 if (e
->X_op
== O_constant
4897 && (bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4901 case IA64_OPND_CNT2b
:
4902 if (e
->X_op
== O_constant
4903 && (bfd_vma
) (e
->X_add_number
- 1) < 3)
4907 case IA64_OPND_CNT2c
:
4908 val
= e
->X_add_number
;
4909 if (e
->X_op
== O_constant
4910 && (val
== 0 || val
== 7 || val
== 15 || val
== 16))
4915 /* SOR must be an integer multiple of 8 */
4916 if (e
->X_add_number
& 0x7)
4920 if (e
->X_op
== O_constant
&&
4921 (bfd_vma
) e
->X_add_number
<= 96)
4925 case IA64_OPND_IMMU62
:
4926 if (e
->X_op
== O_constant
)
4928 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4933 /* FIXME -- need 62-bit relocation type */
4934 as_bad (_("62-bit relocation not yet implemented"));
4938 case IA64_OPND_IMMU64
:
4939 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4940 || e
->X_op
== O_subtract
)
4942 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4943 fix
->code
= BFD_RELOC_IA64_IMM64
;
4944 if (e
->X_op
!= O_subtract
)
4946 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4947 if (e
->X_op
== O_pseudo_fixup
)
4951 fix
->opnd
= idesc
->operands
[index
];
4954 ++CURR_SLOT
.num_fixups
;
4957 else if (e
->X_op
== O_constant
)
4961 case IA64_OPND_CCNT5
:
4962 case IA64_OPND_CNT5
:
4963 case IA64_OPND_CNT6
:
4964 case IA64_OPND_CPOS6a
:
4965 case IA64_OPND_CPOS6b
:
4966 case IA64_OPND_CPOS6c
:
4967 case IA64_OPND_IMMU2
:
4968 case IA64_OPND_IMMU7a
:
4969 case IA64_OPND_IMMU7b
:
4970 case IA64_OPND_IMMU21
:
4971 case IA64_OPND_IMMU24
:
4972 case IA64_OPND_MBTYPE4
:
4973 case IA64_OPND_MHTYPE8
:
4974 case IA64_OPND_POS6
:
4975 bits
= operand_width (idesc
->operands
[index
]);
4976 if (e
->X_op
== O_constant
4977 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4981 case IA64_OPND_IMMU9
:
4982 bits
= operand_width (idesc
->operands
[index
]);
4983 if (e
->X_op
== O_constant
4984 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4986 int lobits
= e
->X_add_number
& 0x3;
4987 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
4988 e
->X_add_number
|= (bfd_vma
) 0x3;
4993 case IA64_OPND_IMM44
:
4994 /* least 16 bits must be zero */
4995 if ((e
->X_add_number
& 0xffff) != 0)
4996 as_warn (_("lower 16 bits of mask ignored"));
4998 if (e
->X_op
== O_constant
4999 && ((e
->X_add_number
>= 0
5000 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5001 || (e
->X_add_number
< 0
5002 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5005 if (e
->X_add_number
>= 0
5006 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5008 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5014 case IA64_OPND_IMM17
:
5015 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5016 if (e
->X_op
== O_constant
5017 && ((e
->X_add_number
>= 0
5018 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5019 || (e
->X_add_number
< 0
5020 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5023 if (e
->X_add_number
>= 0
5024 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5026 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5032 case IA64_OPND_IMM14
:
5033 case IA64_OPND_IMM22
:
5035 case IA64_OPND_IMM1
:
5036 case IA64_OPND_IMM8
:
5037 case IA64_OPND_IMM8U4
:
5038 case IA64_OPND_IMM8M1
:
5039 case IA64_OPND_IMM8M1U4
:
5040 case IA64_OPND_IMM8M1U8
:
5041 case IA64_OPND_IMM9a
:
5042 case IA64_OPND_IMM9b
:
5043 bits
= operand_width (idesc
->operands
[index
]);
5044 if (relocatable
&& (e
->X_op
== O_symbol
5045 || e
->X_op
== O_subtract
5046 || e
->X_op
== O_pseudo_fixup
))
5048 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5050 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5051 fix
->code
= BFD_RELOC_IA64_IMM14
;
5053 fix
->code
= BFD_RELOC_IA64_IMM22
;
5055 if (e
->X_op
!= O_subtract
)
5057 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5058 if (e
->X_op
== O_pseudo_fixup
)
5062 fix
->opnd
= idesc
->operands
[index
];
5065 ++CURR_SLOT
.num_fixups
;
5068 else if (e
->X_op
!= O_constant
5069 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5072 if (opnd
== IA64_OPND_IMM8M1U4
)
5074 /* Zero is not valid for unsigned compares that take an adjusted
5075 constant immediate range. */
5076 if (e
->X_add_number
== 0)
5079 /* Sign-extend 32-bit unsigned numbers, so that the following range
5080 checks will work. */
5081 val
= e
->X_add_number
;
5082 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5083 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5084 val
= ((val
<< 32) >> 32);
5086 /* Check for 0x100000000. This is valid because
5087 0x100000000-1 is the same as ((uint32_t) -1). */
5088 if (val
== ((bfd_signed_vma
) 1 << 32))
5093 else if (opnd
== IA64_OPND_IMM8M1U8
)
5095 /* Zero is not valid for unsigned compares that take an adjusted
5096 constant immediate range. */
5097 if (e
->X_add_number
== 0)
5100 /* Check for 0x10000000000000000. */
5101 if (e
->X_op
== O_big
)
5103 if (generic_bignum
[0] == 0
5104 && generic_bignum
[1] == 0
5105 && generic_bignum
[2] == 0
5106 && generic_bignum
[3] == 0
5107 && generic_bignum
[4] == 1)
5113 val
= e
->X_add_number
- 1;
5115 else if (opnd
== IA64_OPND_IMM8M1
)
5116 val
= e
->X_add_number
- 1;
5117 else if (opnd
== IA64_OPND_IMM8U4
)
5119 /* Sign-extend 32-bit unsigned numbers, so that the following range
5120 checks will work. */
5121 val
= e
->X_add_number
;
5122 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5123 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5124 val
= ((val
<< 32) >> 32);
5127 val
= e
->X_add_number
;
5129 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5130 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5134 case IA64_OPND_INC3
:
5135 /* +/- 1, 4, 8, 16 */
5136 val
= e
->X_add_number
;
5139 if (e
->X_op
== O_constant
5140 && (val
== 1 || val
== 4 || val
== 8 || val
== 16))
5144 case IA64_OPND_TGT25
:
5145 case IA64_OPND_TGT25b
:
5146 case IA64_OPND_TGT25c
:
5147 case IA64_OPND_TGT64
:
5148 if (e
->X_op
== O_symbol
)
5150 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5151 if (opnd
== IA64_OPND_TGT25
)
5152 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5153 else if (opnd
== IA64_OPND_TGT25b
)
5154 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5155 else if (opnd
== IA64_OPND_TGT25c
)
5156 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5157 else if (opnd
== IA64_OPND_TGT64
)
5158 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5162 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5163 fix
->opnd
= idesc
->operands
[index
];
5166 ++CURR_SLOT
.num_fixups
;
5169 case IA64_OPND_TAG13
:
5170 case IA64_OPND_TAG13b
:
5177 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5178 /* There are no external relocs for TAG13/TAG13b fields, so we
5179 create a dummy reloc. This will not live past md_apply_fix3. */
5180 fix
->code
= BFD_RELOC_UNUSED
;
5181 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5182 fix
->opnd
= idesc
->operands
[index
];
5185 ++CURR_SLOT
.num_fixups
;
5205 memset (e
, 0, sizeof (*e
));
5208 if (*input_line_pointer
!= '}')
5210 sep
= *input_line_pointer
++;
5214 if (!md
.manual_bundling
)
5215 as_warn ("Found '}' when manual bundling is off");
5217 CURR_SLOT
.manual_bundling_off
= 1;
5218 md
.manual_bundling
= 0;
5224 /* Returns the next entry in the opcode table that matches the one in
5225 IDESC, and frees the entry in IDESC. If no matching entry is
5226 found, NULL is returned instead. */
5228 static struct ia64_opcode
*
5229 get_next_opcode (struct ia64_opcode
*idesc
)
5231 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5232 ia64_free_opcode (idesc
);
5236 /* Parse the operands for the opcode and find the opcode variant that
5237 matches the specified operands, or NULL if no match is possible. */
5239 static struct ia64_opcode
*
5240 parse_operands (idesc
)
5241 struct ia64_opcode
*idesc
;
5243 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5245 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5247 char *first_arg
= 0, *end
, *saved_input_pointer
;
5250 assert (strlen (idesc
->name
) <= 128);
5252 strcpy (mnemonic
, idesc
->name
);
5253 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5255 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5256 can't parse the first operand until we have parsed the
5257 remaining operands of the "alloc" instruction. */
5259 first_arg
= input_line_pointer
;
5260 end
= strchr (input_line_pointer
, '=');
5263 as_bad ("Expected separator `='");
5266 input_line_pointer
= end
+ 1;
5271 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5273 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5274 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5279 if (sep
!= '=' && sep
!= ',')
5284 if (num_outputs
> 0)
5285 as_bad ("Duplicate equal sign (=) in instruction");
5287 num_outputs
= i
+ 1;
5292 as_bad ("Illegal operand separator `%c'", sep
);
5296 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5298 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5299 know (strcmp (idesc
->name
, "alloc") == 0);
5300 if (num_operands
== 5 /* first_arg not included in this count! */
5301 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5302 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5303 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5304 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5306 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5307 CURR_SLOT
.opnd
[3].X_add_number
,
5308 CURR_SLOT
.opnd
[4].X_add_number
,
5309 CURR_SLOT
.opnd
[5].X_add_number
);
5311 /* now we can parse the first arg: */
5312 saved_input_pointer
= input_line_pointer
;
5313 input_line_pointer
= first_arg
;
5314 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5316 --num_outputs
; /* force error */
5317 input_line_pointer
= saved_input_pointer
;
5319 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5320 CURR_SLOT
.opnd
[3].X_add_number
5321 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5322 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5326 highest_unmatched_operand
= 0;
5327 expected_operand
= idesc
->operands
[0];
5328 for (; idesc
; idesc
= get_next_opcode (idesc
))
5330 if (num_outputs
!= idesc
->num_outputs
)
5331 continue; /* mismatch in # of outputs */
5333 CURR_SLOT
.num_fixups
= 0;
5334 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5335 if (!operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
))
5338 if (i
!= num_operands
)
5340 if (i
> highest_unmatched_operand
)
5342 highest_unmatched_operand
= i
;
5343 expected_operand
= idesc
->operands
[i
];
5348 if (num_operands
< NELEMS (idesc
->operands
)
5349 && idesc
->operands
[num_operands
])
5350 continue; /* mismatch in number of arguments */
5356 if (expected_operand
)
5357 as_bad ("Operand %u of `%s' should be %s",
5358 highest_unmatched_operand
+ 1, mnemonic
,
5359 elf64_ia64_operands
[expected_operand
].desc
);
5361 as_bad ("Operand mismatch");
5367 /* Keep track of state necessary to determine whether a NOP is necessary
5368 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5369 detect a case where additional NOPs may be necessary. */
5371 errata_nop_necessary_p (slot
, insn_unit
)
5373 enum ia64_unit insn_unit
;
5376 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5377 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5378 struct ia64_opcode
*idesc
= slot
->idesc
;
5380 /* Test whether this could be the first insn in a problematic sequence. */
5381 if (insn_unit
== IA64_UNIT_F
)
5383 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5384 if (idesc
->operands
[i
] == IA64_OPND_P1
5385 || idesc
->operands
[i
] == IA64_OPND_P2
)
5387 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5388 /* Ignore invalid operands; they generate errors elsewhere. */
5391 this_group
->p_reg_set
[regno
] = 1;
5395 /* Test whether this could be the second insn in a problematic sequence. */
5396 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5397 && prev_group
->p_reg_set
[slot
->qp_regno
])
5399 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5400 if (idesc
->operands
[i
] == IA64_OPND_R1
5401 || idesc
->operands
[i
] == IA64_OPND_R2
5402 || idesc
->operands
[i
] == IA64_OPND_R3
)
5404 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5405 /* Ignore invalid operands; they generate errors elsewhere. */
5408 if (strncmp (idesc
->name
, "add", 3) != 0
5409 && strncmp (idesc
->name
, "sub", 3) != 0
5410 && strncmp (idesc
->name
, "shladd", 6) != 0
5411 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5412 this_group
->g_reg_set_conditionally
[regno
] = 1;
5416 /* Test whether this could be the third insn in a problematic sequence. */
5417 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5419 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5420 idesc
->operands
[i
] == IA64_OPND_R3
5421 /* For mov indirect. */
5422 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5423 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5424 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5425 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5426 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5427 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5428 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5429 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5431 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5432 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5433 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5434 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5436 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5437 /* Ignore invalid operands; they generate errors elsewhere. */
5440 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5442 if (strcmp (idesc
->name
, "fc") != 0
5443 && strcmp (idesc
->name
, "tak") != 0
5444 && strcmp (idesc
->name
, "thash") != 0
5445 && strcmp (idesc
->name
, "tpa") != 0
5446 && strcmp (idesc
->name
, "ttag") != 0
5447 && strncmp (idesc
->name
, "ptr", 3) != 0
5448 && strncmp (idesc
->name
, "ptc", 3) != 0
5449 && strncmp (idesc
->name
, "probe", 5) != 0)
5452 if (prev_group
->g_reg_set_conditionally
[regno
])
5460 build_insn (slot
, insnp
)
5464 const struct ia64_operand
*odesc
, *o2desc
;
5465 struct ia64_opcode
*idesc
= slot
->idesc
;
5466 bfd_signed_vma insn
, val
;
5470 insn
= idesc
->opcode
| slot
->qp_regno
;
5472 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5474 if (slot
->opnd
[i
].X_op
== O_register
5475 || slot
->opnd
[i
].X_op
== O_constant
5476 || slot
->opnd
[i
].X_op
== O_index
)
5477 val
= slot
->opnd
[i
].X_add_number
;
5478 else if (slot
->opnd
[i
].X_op
== O_big
)
5480 /* This must be the value 0x10000000000000000. */
5481 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5487 switch (idesc
->operands
[i
])
5489 case IA64_OPND_IMMU64
:
5490 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5491 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5492 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5493 | (((val
>> 63) & 0x1) << 36));
5496 case IA64_OPND_IMMU62
:
5497 val
&= 0x3fffffffffffffffULL
;
5498 if (val
!= slot
->opnd
[i
].X_add_number
)
5499 as_warn (_("Value truncated to 62 bits"));
5500 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5501 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5504 case IA64_OPND_TGT64
:
5506 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5507 insn
|= ((((val
>> 59) & 0x1) << 36)
5508 | (((val
>> 0) & 0xfffff) << 13));
5539 case IA64_OPND_R3_2
:
5540 case IA64_OPND_CPUID_R3
:
5541 case IA64_OPND_DBR_R3
:
5542 case IA64_OPND_DTR_R3
:
5543 case IA64_OPND_ITR_R3
:
5544 case IA64_OPND_IBR_R3
:
5546 case IA64_OPND_MSR_R3
:
5547 case IA64_OPND_PKR_R3
:
5548 case IA64_OPND_PMC_R3
:
5549 case IA64_OPND_PMD_R3
:
5550 case IA64_OPND_RR_R3
:
5558 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5559 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5561 as_bad_where (slot
->src_file
, slot
->src_line
,
5562 "Bad operand value: %s", err
);
5563 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5565 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5566 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5568 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5569 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5571 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5572 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5573 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5575 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5576 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5586 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5587 unsigned int manual_bundling
= 0;
5588 enum ia64_unit required_unit
, insn_unit
= 0;
5589 enum ia64_insn_type type
[3], insn_type
;
5590 unsigned int template, orig_template
;
5591 bfd_vma insn
[3] = { -1, -1, -1 };
5592 struct ia64_opcode
*idesc
;
5593 int end_of_insn_group
= 0, user_template
= -1;
5594 int n
, i
, j
, first
, curr
;
5596 bfd_vma t0
= 0, t1
= 0;
5597 struct label_fix
*lfix
;
5598 struct insn_fix
*ifix
;
5603 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5604 know (first
>= 0 & first
< NUM_SLOTS
);
5605 n
= MIN (3, md
.num_slots_in_use
);
5607 /* Determine template: user user_template if specified, best match
5610 if (md
.slot
[first
].user_template
>= 0)
5611 user_template
= template = md
.slot
[first
].user_template
;
5614 /* Auto select appropriate template. */
5615 memset (type
, 0, sizeof (type
));
5617 for (i
= 0; i
< n
; ++i
)
5619 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5621 type
[i
] = md
.slot
[curr
].idesc
->type
;
5622 curr
= (curr
+ 1) % NUM_SLOTS
;
5624 template = best_template
[type
[0]][type
[1]][type
[2]];
5627 /* initialize instructions with appropriate nops: */
5628 for (i
= 0; i
< 3; ++i
)
5629 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5633 /* now fill in slots with as many insns as possible: */
5635 idesc
= md
.slot
[curr
].idesc
;
5636 end_of_insn_group
= 0;
5637 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5639 /* Set the slot number for prologue/body records now as those
5640 refer to the current point, not the point after the
5641 instruction has been issued: */
5642 /* Don't try to delete prologue/body records here, as that will cause
5643 them to also be deleted from the master list of unwind records. */
5644 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5645 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5646 || ptr
->r
.type
== body
)
5648 ptr
->slot_number
= (unsigned long) f
+ i
;
5649 ptr
->slot_frag
= frag_now
;
5652 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5654 if (manual_bundling
&& i
!= 2)
5655 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5656 "`%s' must be last in bundle", idesc
->name
);
5660 if (idesc
->flags
& IA64_OPCODE_LAST
)
5663 unsigned int required_template
;
5665 /* If we need a stop bit after an M slot, our only choice is
5666 template 5 (M;;MI). If we need a stop bit after a B
5667 slot, our only choice is to place it at the end of the
5668 bundle, because the only available templates are MIB,
5669 MBB, BBB, MMB, and MFB. We don't handle anything other
5670 than M and B slots because these are the only kind of
5671 instructions that can have the IA64_OPCODE_LAST bit set. */
5672 required_template
= template;
5673 switch (idesc
->type
)
5677 required_template
= 5;
5685 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5686 "Internal error: don't know how to force %s to end"
5687 "of instruction group", idesc
->name
);
5691 if (manual_bundling
&& i
!= required_slot
)
5692 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5693 "`%s' must be last in instruction group",
5695 if (required_slot
< i
)
5696 /* Can't fit this instruction. */
5700 if (required_template
!= template)
5702 /* If we switch the template, we need to reset the NOPs
5703 after slot i. The slot-types of the instructions ahead
5704 of i never change, so we don't need to worry about
5705 changing NOPs in front of this slot. */
5706 for (j
= i
; j
< 3; ++j
)
5707 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5709 template = required_template
;
5711 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5713 if (manual_bundling_on
)
5714 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5715 "Label must be first in a bundle");
5716 /* This insn must go into the first slot of a bundle. */
5720 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5721 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5723 if (manual_bundling_on
)
5726 manual_bundling
= 1;
5728 break; /* need to start a new bundle */
5731 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5733 /* We need an instruction group boundary in the middle of a
5734 bundle. See if we can switch to an other template with
5735 an appropriate boundary. */
5737 orig_template
= template;
5738 if (i
== 1 && (user_template
== 4
5739 || (user_template
< 0
5740 && (ia64_templ_desc
[template].exec_unit
[0]
5744 end_of_insn_group
= 0;
5746 else if (i
== 2 && (user_template
== 0
5747 || (user_template
< 0
5748 && (ia64_templ_desc
[template].exec_unit
[1]
5750 /* This test makes sure we don't switch the template if
5751 the next instruction is one that needs to be first in
5752 an instruction group. Since all those instructions are
5753 in the M group, there is no way such an instruction can
5754 fit in this bundle even if we switch the template. The
5755 reason we have to check for this is that otherwise we
5756 may end up generating "MI;;I M.." which has the deadly
5757 effect that the second M instruction is no longer the
5758 first in the bundle! --davidm 99/12/16 */
5759 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5762 end_of_insn_group
= 0;
5764 else if (curr
!= first
)
5765 /* can't fit this insn */
5768 if (template != orig_template
)
5769 /* if we switch the template, we need to reset the NOPs
5770 after slot i. The slot-types of the instructions ahead
5771 of i never change, so we don't need to worry about
5772 changing NOPs in front of this slot. */
5773 for (j
= i
; j
< 3; ++j
)
5774 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5776 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5778 /* resolve dynamic opcodes such as "break" and "nop": */
5779 if (idesc
->type
== IA64_TYPE_DYN
)
5781 if ((strcmp (idesc
->name
, "nop") == 0)
5782 || (strcmp (idesc
->name
, "break") == 0))
5783 insn_unit
= required_unit
;
5784 else if (strcmp (idesc
->name
, "chk.s") == 0)
5786 insn_unit
= IA64_UNIT_M
;
5787 if (required_unit
== IA64_UNIT_I
)
5788 insn_unit
= IA64_UNIT_I
;
5791 as_fatal ("emit_one_bundle: unexpected dynamic op");
5793 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5794 ia64_free_opcode (idesc
);
5795 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5797 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5802 insn_type
= idesc
->type
;
5803 insn_unit
= IA64_UNIT_NIL
;
5807 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5808 insn_unit
= required_unit
;
5810 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5811 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5812 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5813 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5814 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5819 if (insn_unit
!= required_unit
)
5821 if (required_unit
== IA64_UNIT_L
5822 && insn_unit
== IA64_UNIT_I
5823 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5825 /* we got ourselves an MLX template but the current
5826 instruction isn't an X-unit, or an I-unit instruction
5827 that can go into the X slot of an MLX template. Duh. */
5828 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5830 as_bad_where (md
.slot
[curr
].src_file
,
5831 md
.slot
[curr
].src_line
,
5832 "`%s' can't go in X slot of "
5833 "MLX template", idesc
->name
);
5834 /* drop this insn so we don't livelock: */
5835 --md
.num_slots_in_use
;
5839 continue; /* try next slot */
5845 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
5846 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5849 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
5850 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
5852 build_insn (md
.slot
+ curr
, insn
+ i
);
5854 /* Set slot counts for non prologue/body unwind records. */
5855 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5856 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5857 && ptr
->r
.type
!= body
)
5859 ptr
->slot_number
= (unsigned long) f
+ i
;
5860 ptr
->slot_frag
= frag_now
;
5862 md
.slot
[curr
].unwind_record
= NULL
;
5864 if (required_unit
== IA64_UNIT_L
)
5867 /* skip one slot for long/X-unit instructions */
5870 --md
.num_slots_in_use
;
5872 /* now is a good time to fix up the labels for this insn: */
5873 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5875 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5876 symbol_set_frag (lfix
->sym
, frag_now
);
5878 /* and fix up the tags also. */
5879 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
5881 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
5882 symbol_set_frag (lfix
->sym
, frag_now
);
5885 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5887 ifix
= md
.slot
[curr
].fixup
+ j
;
5888 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
5889 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5890 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5891 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
5892 fix
->fx_file
= md
.slot
[curr
].src_file
;
5893 fix
->fx_line
= md
.slot
[curr
].src_line
;
5896 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
5898 if (end_of_insn_group
)
5900 md
.group_idx
= (md
.group_idx
+ 1) % 3;
5901 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
5905 ia64_free_opcode (md
.slot
[curr
].idesc
);
5906 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
5907 md
.slot
[curr
].user_template
= -1;
5909 if (manual_bundling_off
)
5911 manual_bundling
= 0;
5914 curr
= (curr
+ 1) % NUM_SLOTS
;
5915 idesc
= md
.slot
[curr
].idesc
;
5917 if (manual_bundling
)
5919 if (md
.num_slots_in_use
> 0)
5920 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5921 "`%s' does not fit into %s template",
5922 idesc
->name
, ia64_templ_desc
[template].name
);
5924 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5925 "Missing '}' at end of file");
5927 know (md
.num_slots_in_use
< NUM_SLOTS
);
5929 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
5930 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
5932 number_to_chars_littleendian (f
+ 0, t0
, 8);
5933 number_to_chars_littleendian (f
+ 8, t1
, 8);
5935 unwind
.next_slot_number
= (unsigned long) f
+ 16;
5936 unwind
.next_slot_frag
= frag_now
;
5940 md_parse_option (c
, arg
)
5946 /* Switches from the Intel assembler. */
5948 if (strcmp (arg
, "ilp64") == 0
5949 || strcmp (arg
, "lp64") == 0
5950 || strcmp (arg
, "p64") == 0)
5952 md
.flags
|= EF_IA_64_ABI64
;
5954 else if (strcmp (arg
, "ilp32") == 0)
5956 md
.flags
&= ~EF_IA_64_ABI64
;
5958 else if (strcmp (arg
, "le") == 0)
5960 md
.flags
&= ~EF_IA_64_BE
;
5962 else if (strcmp (arg
, "be") == 0)
5964 md
.flags
|= EF_IA_64_BE
;
5971 if (strcmp (arg
, "so") == 0)
5973 /* Suppress signon message. */
5975 else if (strcmp (arg
, "pi") == 0)
5977 /* Reject privileged instructions. FIXME */
5979 else if (strcmp (arg
, "us") == 0)
5981 /* Allow union of signed and unsigned range. FIXME */
5983 else if (strcmp (arg
, "close_fcalls") == 0)
5985 /* Do not resolve global function calls. */
5992 /* temp[="prefix"] Insert temporary labels into the object file
5993 symbol table prefixed by "prefix".
5994 Default prefix is ":temp:".
5999 /* indirect=<tgt> Assume unannotated indirect branches behavior
6000 according to <tgt> --
6001 exit: branch out from the current context (default)
6002 labels: all labels in context may be branch targets
6004 if (strncmp (arg
, "indirect=", 9) != 0)
6009 /* -X conflicts with an ignored option, use -x instead */
6011 if (!arg
|| strcmp (arg
, "explicit") == 0)
6013 /* set default mode to explicit */
6014 md
.default_explicit_mode
= 1;
6017 else if (strcmp (arg
, "auto") == 0)
6019 md
.default_explicit_mode
= 0;
6021 else if (strcmp (arg
, "debug") == 0)
6025 else if (strcmp (arg
, "debugx") == 0)
6027 md
.default_explicit_mode
= 1;
6032 as_bad (_("Unrecognized option '-x%s'"), arg
);
6037 /* nops Print nops statistics. */
6040 /* GNU specific switches for gcc. */
6041 case OPTION_MCONSTANT_GP
:
6042 md
.flags
|= EF_IA_64_CONS_GP
;
6045 case OPTION_MAUTO_PIC
:
6046 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6057 md_show_usage (stream
)
6062 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6063 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6064 -x | -xexplicit turn on dependency violation checking (default)\n\
6065 -xauto automagically remove dependency violations\n\
6066 -xdebug debug dependency violation checker\n"),
6070 /* Return true if TYPE fits in TEMPL at SLOT. */
6073 match (int templ
, int type
, int slot
)
6075 enum ia64_unit unit
;
6078 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6081 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6083 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6085 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6086 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6087 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6088 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6089 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6090 default: result
= 0; break;
6095 /* Add a bit of extra goodness if a nop of type F or B would fit
6096 in TEMPL at SLOT. */
6099 extra_goodness (int templ
, int slot
)
6101 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6103 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6108 /* This function is called once, at assembler startup time. It sets
6109 up all the tables, etc. that the MD part of the assembler will need
6110 that can be determined before arguments are parsed. */
6114 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6119 md
.explicit_mode
= md
.default_explicit_mode
;
6121 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6123 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6124 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6125 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6126 &zero_address_frag
);
6128 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6129 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6130 &zero_address_frag
);
6132 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6133 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6134 &zero_address_frag
);
6136 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6137 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6138 &zero_address_frag
);
6140 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6141 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6142 &zero_address_frag
);
6144 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6145 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6146 &zero_address_frag
);
6148 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6149 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6150 &zero_address_frag
);
6152 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6153 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6154 &zero_address_frag
);
6156 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6157 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6158 &zero_address_frag
);
6160 /* Compute the table of best templates. We compute goodness as a
6161 base 4 value, in which each match counts for 3, each F counts
6162 for 2, each B counts for 1. This should maximize the number of
6163 F and B nops in the chosen bundles, which is good because these
6164 pipelines are least likely to be overcommitted. */
6165 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6166 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6167 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6170 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6173 if (match (t
, i
, 0))
6175 if (match (t
, j
, 1))
6177 if (match (t
, k
, 2))
6178 goodness
= 3 + 3 + 3;
6180 goodness
= 3 + 3 + extra_goodness (t
, 2);
6182 else if (match (t
, j
, 2))
6183 goodness
= 3 + 3 + extra_goodness (t
, 1);
6187 goodness
+= extra_goodness (t
, 1);
6188 goodness
+= extra_goodness (t
, 2);
6191 else if (match (t
, i
, 1))
6193 if (match (t
, j
, 2))
6196 goodness
= 3 + extra_goodness (t
, 2);
6198 else if (match (t
, i
, 2))
6199 goodness
= 3 + extra_goodness (t
, 1);
6201 if (goodness
> best
)
6204 best_template
[i
][j
][k
] = t
;
6209 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6210 md
.slot
[i
].user_template
= -1;
6212 md
.pseudo_hash
= hash_new ();
6213 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6215 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6216 (void *) (pseudo_opcode
+ i
));
6218 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6219 pseudo_opcode
[i
].name
, err
);
6222 md
.reg_hash
= hash_new ();
6223 md
.dynreg_hash
= hash_new ();
6224 md
.const_hash
= hash_new ();
6225 md
.entry_hash
= hash_new ();
6227 /* general registers: */
6230 for (i
= 0; i
< total
; ++i
)
6232 sprintf (name
, "r%d", i
- REG_GR
);
6233 md
.regsym
[i
] = declare_register (name
, i
);
6236 /* floating point registers: */
6238 for (; i
< total
; ++i
)
6240 sprintf (name
, "f%d", i
- REG_FR
);
6241 md
.regsym
[i
] = declare_register (name
, i
);
6244 /* application registers: */
6247 for (; i
< total
; ++i
)
6249 sprintf (name
, "ar%d", i
- REG_AR
);
6250 md
.regsym
[i
] = declare_register (name
, i
);
6253 /* control registers: */
6256 for (; i
< total
; ++i
)
6258 sprintf (name
, "cr%d", i
- REG_CR
);
6259 md
.regsym
[i
] = declare_register (name
, i
);
6262 /* predicate registers: */
6264 for (; i
< total
; ++i
)
6266 sprintf (name
, "p%d", i
- REG_P
);
6267 md
.regsym
[i
] = declare_register (name
, i
);
6270 /* branch registers: */
6272 for (; i
< total
; ++i
)
6274 sprintf (name
, "b%d", i
- REG_BR
);
6275 md
.regsym
[i
] = declare_register (name
, i
);
6278 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6279 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6280 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6281 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6282 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6283 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6284 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6286 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6288 regnum
= indirect_reg
[i
].regnum
;
6289 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6292 /* define synonyms for application registers: */
6293 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6294 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6295 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6297 /* define synonyms for control registers: */
6298 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6299 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6300 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6302 declare_register ("gp", REG_GR
+ 1);
6303 declare_register ("sp", REG_GR
+ 12);
6304 declare_register ("rp", REG_BR
+ 0);
6306 /* pseudo-registers used to specify unwind info: */
6307 declare_register ("psp", REG_PSP
);
6309 declare_register_set ("ret", 4, REG_GR
+ 8);
6310 declare_register_set ("farg", 8, REG_FR
+ 8);
6311 declare_register_set ("fret", 8, REG_FR
+ 8);
6313 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6315 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6316 (PTR
) (const_bits
+ i
));
6318 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6322 /* Set the architecture and machine depending on defaults and command line
6324 if (md
.flags
& EF_IA_64_ABI64
)
6325 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6327 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6330 as_warn (_("Could not set architecture and machine"));
6332 md
.mem_offset
.hint
= 0;
6335 md
.entry_labels
= NULL
;
6338 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6339 because that is called after md_parse_option which is where we do the
6340 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6341 default endianness. */
6344 ia64_init (argc
, argv
)
6345 int argc ATTRIBUTE_UNUSED
;
6346 char **argv ATTRIBUTE_UNUSED
;
6348 md
.flags
= EF_IA_64_ABI64
;
6349 if (TARGET_BYTES_BIG_ENDIAN
)
6350 md
.flags
|= EF_IA_64_BE
;
6353 /* Return a string for the target object file format. */
6356 ia64_target_format ()
6358 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6360 if (md
.flags
& EF_IA_64_BE
)
6362 if (md
.flags
& EF_IA_64_ABI64
)
6363 return "elf64-ia64-big";
6365 return "elf32-ia64-big";
6369 if (md
.flags
& EF_IA_64_ABI64
)
6370 return "elf64-ia64-little";
6372 return "elf32-ia64-little";
6376 return "unknown-format";
6380 ia64_end_of_source ()
6382 /* terminate insn group upon reaching end of file: */
6383 insn_group_break (1, 0, 0);
6385 /* emits slots we haven't written yet: */
6386 ia64_flush_insns ();
6388 bfd_set_private_flags (stdoutput
, md
.flags
);
6390 md
.mem_offset
.hint
= 0;
6396 if (md
.qp
.X_op
== O_register
)
6397 as_bad ("qualifying predicate not followed by instruction");
6398 md
.qp
.X_op
= O_absent
;
6400 if (ignore_input ())
6403 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6405 if (md
.detect_dv
&& !md
.explicit_mode
)
6406 as_warn (_("Explicit stops are ignored in auto mode"));
6408 insn_group_break (1, 0, 0);
6412 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6414 static int defining_tag
= 0;
6417 ia64_unrecognized_line (ch
)
6423 expression (&md
.qp
);
6424 if (*input_line_pointer
++ != ')')
6426 as_bad ("Expected ')'");
6429 if (md
.qp
.X_op
!= O_register
)
6431 as_bad ("Qualifying predicate expected");
6434 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6436 as_bad ("Predicate register expected");
6442 if (md
.manual_bundling
)
6443 as_warn ("Found '{' when manual bundling is already turned on");
6445 CURR_SLOT
.manual_bundling_on
= 1;
6446 md
.manual_bundling
= 1;
6448 /* Bundling is only acceptable in explicit mode
6449 or when in default automatic mode. */
6450 if (md
.detect_dv
&& !md
.explicit_mode
)
6452 if (!md
.mode_explicitly_set
6453 && !md
.default_explicit_mode
)
6456 as_warn (_("Found '{' after explicit switch to automatic mode"));
6461 if (!md
.manual_bundling
)
6462 as_warn ("Found '}' when manual bundling is off");
6464 PREV_SLOT
.manual_bundling_off
= 1;
6465 md
.manual_bundling
= 0;
6467 /* switch back to automatic mode, if applicable */
6470 && !md
.mode_explicitly_set
6471 && !md
.default_explicit_mode
)
6474 /* Allow '{' to follow on the same line. We also allow ";;", but that
6475 happens automatically because ';' is an end of line marker. */
6477 if (input_line_pointer
[0] == '{')
6479 input_line_pointer
++;
6480 return ia64_unrecognized_line ('{');
6483 demand_empty_rest_of_line ();
6492 if (md
.qp
.X_op
== O_register
)
6494 as_bad ("Tag must come before qualifying predicate.");
6497 s
= input_line_pointer
;
6498 c
= get_symbol_end ();
6501 /* Put ':' back for error messages' sake. */
6502 *input_line_pointer
++ = ':';
6503 as_bad ("Expected ':'");
6509 /* Put ':' back for error messages' sake. */
6510 *input_line_pointer
++ = ':';
6511 if (*input_line_pointer
++ != ']')
6513 as_bad ("Expected ']'");
6518 as_bad ("Tag name expected");
6528 /* Not a valid line. */
6533 ia64_frob_label (sym
)
6536 struct label_fix
*fix
;
6538 /* Tags need special handling since they are not bundle breaks like
6542 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6544 fix
->next
= CURR_SLOT
.tag_fixups
;
6545 CURR_SLOT
.tag_fixups
= fix
;
6550 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6552 md
.last_text_seg
= now_seg
;
6553 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6555 fix
->next
= CURR_SLOT
.label_fixups
;
6556 CURR_SLOT
.label_fixups
= fix
;
6558 /* Keep track of how many code entry points we've seen. */
6559 if (md
.path
== md
.maxpaths
)
6562 md
.entry_labels
= (const char **)
6563 xrealloc ((void *) md
.entry_labels
,
6564 md
.maxpaths
* sizeof (char *));
6566 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6571 ia64_flush_pending_output ()
6573 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6575 /* ??? This causes many unnecessary stop bits to be emitted.
6576 Unfortunately, it isn't clear if it is safe to remove this. */
6577 insn_group_break (1, 0, 0);
6578 ia64_flush_insns ();
6582 /* Do ia64-specific expression optimization. All that's done here is
6583 to transform index expressions that are either due to the indexing
6584 of rotating registers or due to the indexing of indirect register
6587 ia64_optimize_expr (l
, op
, r
)
6596 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6598 num_regs
= (l
->X_add_number
>> 16);
6599 if ((unsigned) r
->X_add_number
>= num_regs
)
6602 as_bad ("No current frame");
6604 as_bad ("Index out of range 0..%u", num_regs
- 1);
6605 r
->X_add_number
= 0;
6607 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6610 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6612 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6613 || l
->X_add_number
== IND_MEM
)
6615 as_bad ("Indirect register set name expected");
6616 l
->X_add_number
= IND_CPUID
;
6619 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6620 l
->X_add_number
= r
->X_add_number
;
6628 ia64_parse_name (name
, e
)
6632 struct const_desc
*cdesc
;
6633 struct dynreg
*dr
= 0;
6634 unsigned int regnum
;
6638 /* first see if NAME is a known register name: */
6639 sym
= hash_find (md
.reg_hash
, name
);
6642 e
->X_op
= O_register
;
6643 e
->X_add_number
= S_GET_VALUE (sym
);
6647 cdesc
= hash_find (md
.const_hash
, name
);
6650 e
->X_op
= O_constant
;
6651 e
->X_add_number
= cdesc
->value
;
6655 /* check for inN, locN, or outN: */
6659 if (name
[1] == 'n' && isdigit (name
[2]))
6667 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6675 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6688 /* The name is inN, locN, or outN; parse the register number. */
6689 regnum
= strtoul (name
, &end
, 10);
6690 if (end
> name
&& *end
== '\0')
6692 if ((unsigned) regnum
>= dr
->num_regs
)
6695 as_bad ("No current frame");
6697 as_bad ("Register number out of range 0..%u",
6701 e
->X_op
= O_register
;
6702 e
->X_add_number
= dr
->base
+ regnum
;
6707 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6709 /* We've got ourselves the name of a rotating register set.
6710 Store the base register number in the low 16 bits of
6711 X_add_number and the size of the register set in the top 16
6713 e
->X_op
= O_register
;
6714 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6720 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6723 ia64_canonicalize_symbol_name (name
)
6726 size_t len
= strlen (name
);
6727 if (len
> 1 && name
[len
- 1] == '#')
6728 name
[len
- 1] = '\0';
6733 is_conditional_branch (idesc
)
6734 struct ia64_opcode
*idesc
;
6736 return (strncmp (idesc
->name
, "br", 2) == 0
6737 && (strcmp (idesc
->name
, "br") == 0
6738 || strncmp (idesc
->name
, "br.cond", 7) == 0
6739 || strncmp (idesc
->name
, "br.call", 7) == 0
6740 || strncmp (idesc
->name
, "br.ret", 6) == 0
6741 || strcmp (idesc
->name
, "brl") == 0
6742 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6743 || strncmp (idesc
->name
, "brl.call", 7) == 0
6744 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6747 /* Return whether the given opcode is a taken branch. If there's any doubt,
6751 is_taken_branch (idesc
)
6752 struct ia64_opcode
*idesc
;
6754 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6755 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6758 /* Return whether the given opcode is an interruption or rfi. If there's any
6759 doubt, returns zero. */
6762 is_interruption_or_rfi (idesc
)
6763 struct ia64_opcode
*idesc
;
6765 if (strcmp (idesc
->name
, "rfi") == 0)
6770 /* Returns the index of the given dependency in the opcode's list of chks, or
6771 -1 if there is no dependency. */
6774 depends_on (depind
, idesc
)
6776 struct ia64_opcode
*idesc
;
6779 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6780 for (i
= 0; i
< dep
->nchks
; i
++)
6782 if (depind
== DEP (dep
->chks
[i
]))
6788 /* Determine a set of specific resources used for a particular resource
6789 class. Returns the number of specific resources identified For those
6790 cases which are not determinable statically, the resource returned is
6793 Meanings of value in 'NOTE':
6794 1) only read/write when the register number is explicitly encoded in the
6796 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6797 accesses CFM when qualifying predicate is in the rotating region.
6798 3) general register value is used to specify an indirect register; not
6799 determinable statically.
6800 4) only read the given resource when bits 7:0 of the indirect index
6801 register value does not match the register number of the resource; not
6802 determinable statically.
6803 5) all rules are implementation specific.
6804 6) only when both the index specified by the reader and the index specified
6805 by the writer have the same value in bits 63:61; not determinable
6807 7) only access the specified resource when the corresponding mask bit is
6809 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6810 only read when these insns reference FR2-31
6811 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6812 written when these insns write FR32-127
6813 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6815 11) The target predicates are written independently of PR[qp], but source
6816 registers are only read if PR[qp] is true. Since the state of PR[qp]
6817 cannot statically be determined, all source registers are marked used.
6818 12) This insn only reads the specified predicate register when that
6819 register is the PR[qp].
6820 13) This reference to ld-c only applies to teh GR whose value is loaded
6821 with data returned from memory, not the post-incremented address register.
6822 14) The RSE resource includes the implementation-specific RSE internal
6823 state resources. At least one (and possibly more) of these resources are
6824 read by each instruction listed in IC:rse-readers. At least one (and
6825 possibly more) of these resources are written by each insn listed in
6827 15+16) Represents reserved instructions, which the assembler does not
6830 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6831 this code; there are no dependency violations based on memory access.
6834 #define MAX_SPECS 256
6839 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6840 const struct ia64_dependency
*dep
;
6841 struct ia64_opcode
*idesc
;
6842 int type
; /* is this a DV chk or a DV reg? */
6843 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6844 int note
; /* resource note for this insn's usage */
6845 int path
; /* which execution path to examine */
6852 if (dep
->mode
== IA64_DV_WAW
6853 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6854 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6857 /* template for any resources we identify */
6858 tmpl
.dependency
= dep
;
6860 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6861 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6862 tmpl
.link_to_qp_branch
= 1;
6863 tmpl
.mem_offset
.hint
= 0;
6866 tmpl
.cmp_type
= CMP_NONE
;
6869 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6870 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6871 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6873 /* we don't need to track these */
6874 if (dep
->semantics
== IA64_DVS_NONE
)
6877 switch (dep
->specifier
)
6882 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6884 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6885 if (regno
>= 0 && regno
<= 7)
6887 specs
[count
] = tmpl
;
6888 specs
[count
++].index
= regno
;
6894 for (i
= 0; i
< 8; i
++)
6896 specs
[count
] = tmpl
;
6897 specs
[count
++].index
= i
;
6906 case IA64_RS_AR_UNAT
:
6907 /* This is a mov =AR or mov AR= instruction. */
6908 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6910 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6911 if (regno
== AR_UNAT
)
6913 specs
[count
++] = tmpl
;
6918 /* This is a spill/fill, or other instruction that modifies the
6921 /* Unless we can determine the specific bits used, mark the whole
6922 thing; bits 8:3 of the memory address indicate the bit used in
6923 UNAT. The .mem.offset hint may be used to eliminate a small
6924 subset of conflicts. */
6925 specs
[count
] = tmpl
;
6926 if (md
.mem_offset
.hint
)
6929 fprintf (stderr
, " Using hint for spill/fill\n");
6930 /* The index isn't actually used, just set it to something
6931 approximating the bit index. */
6932 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
6933 specs
[count
].mem_offset
.hint
= 1;
6934 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
6935 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
6939 specs
[count
++].specific
= 0;
6947 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6949 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6950 if ((regno
>= 8 && regno
<= 15)
6951 || (regno
>= 20 && regno
<= 23)
6952 || (regno
>= 31 && regno
<= 39)
6953 || (regno
>= 41 && regno
<= 47)
6954 || (regno
>= 67 && regno
<= 111))
6956 specs
[count
] = tmpl
;
6957 specs
[count
++].index
= regno
;
6970 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6972 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6973 if ((regno
>= 48 && regno
<= 63)
6974 || (regno
>= 112 && regno
<= 127))
6976 specs
[count
] = tmpl
;
6977 specs
[count
++].index
= regno
;
6983 for (i
= 48; i
< 64; i
++)
6985 specs
[count
] = tmpl
;
6986 specs
[count
++].index
= i
;
6988 for (i
= 112; i
< 128; i
++)
6990 specs
[count
] = tmpl
;
6991 specs
[count
++].index
= i
;
7009 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7010 if (idesc
->operands
[i
] == IA64_OPND_B1
7011 || idesc
->operands
[i
] == IA64_OPND_B2
)
7013 specs
[count
] = tmpl
;
7014 specs
[count
++].index
=
7015 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7020 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
7021 if (idesc
->operands
[i
] == IA64_OPND_B1
7022 || idesc
->operands
[i
] == IA64_OPND_B2
)
7024 specs
[count
] = tmpl
;
7025 specs
[count
++].index
=
7026 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7032 case IA64_RS_CPUID
: /* four or more registers */
7035 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7037 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7038 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7041 specs
[count
] = tmpl
;
7042 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7046 specs
[count
] = tmpl
;
7047 specs
[count
++].specific
= 0;
7057 case IA64_RS_DBR
: /* four or more registers */
7060 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7062 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7063 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7066 specs
[count
] = tmpl
;
7067 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7071 specs
[count
] = tmpl
;
7072 specs
[count
++].specific
= 0;
7076 else if (note
== 0 && !rsrc_write
)
7078 specs
[count
] = tmpl
;
7079 specs
[count
++].specific
= 0;
7087 case IA64_RS_IBR
: /* four or more registers */
7090 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7092 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7093 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7096 specs
[count
] = tmpl
;
7097 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7101 specs
[count
] = tmpl
;
7102 specs
[count
++].specific
= 0;
7115 /* These are implementation specific. Force all references to
7116 conflict with all other references. */
7117 specs
[count
] = tmpl
;
7118 specs
[count
++].specific
= 0;
7126 case IA64_RS_PKR
: /* 16 or more registers */
7127 if (note
== 3 || note
== 4)
7129 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7131 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7132 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7137 specs
[count
] = tmpl
;
7138 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7141 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7143 /* Uses all registers *except* the one in R3. */
7144 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7146 specs
[count
] = tmpl
;
7147 specs
[count
++].index
= i
;
7153 specs
[count
] = tmpl
;
7154 specs
[count
++].specific
= 0;
7161 specs
[count
] = tmpl
;
7162 specs
[count
++].specific
= 0;
7166 case IA64_RS_PMC
: /* four or more registers */
7169 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7170 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7173 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7175 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7176 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7179 specs
[count
] = tmpl
;
7180 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7184 specs
[count
] = tmpl
;
7185 specs
[count
++].specific
= 0;
7195 case IA64_RS_PMD
: /* four or more registers */
7198 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7200 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7201 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7204 specs
[count
] = tmpl
;
7205 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7209 specs
[count
] = tmpl
;
7210 specs
[count
++].specific
= 0;
7220 case IA64_RS_RR
: /* eight registers */
7223 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7225 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7226 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7229 specs
[count
] = tmpl
;
7230 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7234 specs
[count
] = tmpl
;
7235 specs
[count
++].specific
= 0;
7239 else if (note
== 0 && !rsrc_write
)
7241 specs
[count
] = tmpl
;
7242 specs
[count
++].specific
= 0;
7250 case IA64_RS_CR_IRR
:
7253 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7254 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7256 && idesc
->operands
[1] == IA64_OPND_CR3
7259 for (i
= 0; i
< 4; i
++)
7261 specs
[count
] = tmpl
;
7262 specs
[count
++].index
= CR_IRR0
+ i
;
7268 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7269 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7271 && regno
<= CR_IRR3
)
7273 specs
[count
] = tmpl
;
7274 specs
[count
++].index
= regno
;
7283 case IA64_RS_CR_LRR
:
7290 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7291 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7292 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7294 specs
[count
] = tmpl
;
7295 specs
[count
++].index
= regno
;
7303 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7305 specs
[count
] = tmpl
;
7306 specs
[count
++].index
=
7307 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7322 else if (rsrc_write
)
7324 if (dep
->specifier
== IA64_RS_FRb
7325 && idesc
->operands
[0] == IA64_OPND_F1
)
7327 specs
[count
] = tmpl
;
7328 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7333 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7335 if (idesc
->operands
[i
] == IA64_OPND_F2
7336 || idesc
->operands
[i
] == IA64_OPND_F3
7337 || idesc
->operands
[i
] == IA64_OPND_F4
)
7339 specs
[count
] = tmpl
;
7340 specs
[count
++].index
=
7341 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7350 /* This reference applies only to the GR whose value is loaded with
7351 data returned from memory. */
7352 specs
[count
] = tmpl
;
7353 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7359 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7360 if (idesc
->operands
[i
] == IA64_OPND_R1
7361 || idesc
->operands
[i
] == IA64_OPND_R2
7362 || idesc
->operands
[i
] == IA64_OPND_R3
)
7364 specs
[count
] = tmpl
;
7365 specs
[count
++].index
=
7366 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7368 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7369 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7370 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7372 specs
[count
] = tmpl
;
7373 specs
[count
++].index
=
7374 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7379 /* Look for anything that reads a GR. */
7380 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7382 if (idesc
->operands
[i
] == IA64_OPND_MR3
7383 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7384 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7385 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7386 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7387 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7388 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7389 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7390 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7391 || ((i
>= idesc
->num_outputs
)
7392 && (idesc
->operands
[i
] == IA64_OPND_R1
7393 || idesc
->operands
[i
] == IA64_OPND_R2
7394 || idesc
->operands
[i
] == IA64_OPND_R3
7395 /* addl source register. */
7396 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7398 specs
[count
] = tmpl
;
7399 specs
[count
++].index
=
7400 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7411 /* This is the same as IA64_RS_PRr, except that the register range is
7412 from 1 - 15, and there are no rotating register reads/writes here. */
7416 for (i
= 1; i
< 16; i
++)
7418 specs
[count
] = tmpl
;
7419 specs
[count
++].index
= i
;
7425 /* Mark only those registers indicated by the mask. */
7428 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7429 for (i
= 1; i
< 16; i
++)
7430 if (mask
& ((valueT
) 1 << i
))
7432 specs
[count
] = tmpl
;
7433 specs
[count
++].index
= i
;
7441 else if (note
== 11) /* note 11 implies note 1 as well */
7445 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7447 if (idesc
->operands
[i
] == IA64_OPND_P1
7448 || idesc
->operands
[i
] == IA64_OPND_P2
)
7450 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7451 if (regno
>= 1 && regno
< 16)
7453 specs
[count
] = tmpl
;
7454 specs
[count
++].index
= regno
;
7464 else if (note
== 12)
7466 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7468 specs
[count
] = tmpl
;
7469 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7476 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7477 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7478 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7479 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7481 if ((idesc
->operands
[0] == IA64_OPND_P1
7482 || idesc
->operands
[0] == IA64_OPND_P2
)
7483 && p1
>= 1 && p1
< 16)
7485 specs
[count
] = tmpl
;
7486 specs
[count
].cmp_type
=
7487 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7488 specs
[count
++].index
= p1
;
7490 if ((idesc
->operands
[1] == IA64_OPND_P1
7491 || idesc
->operands
[1] == IA64_OPND_P2
)
7492 && p2
>= 1 && p2
< 16)
7494 specs
[count
] = tmpl
;
7495 specs
[count
].cmp_type
=
7496 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7497 specs
[count
++].index
= p2
;
7502 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7504 specs
[count
] = tmpl
;
7505 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7507 if (idesc
->operands
[1] == IA64_OPND_PR
)
7509 for (i
= 1; i
< 16; i
++)
7511 specs
[count
] = tmpl
;
7512 specs
[count
++].index
= i
;
7523 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7524 simplified cases of this. */
7528 for (i
= 16; i
< 63; i
++)
7530 specs
[count
] = tmpl
;
7531 specs
[count
++].index
= i
;
7537 /* Mark only those registers indicated by the mask. */
7539 && idesc
->operands
[0] == IA64_OPND_PR
)
7541 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7542 if (mask
& ((valueT
) 1<<16))
7543 for (i
= 16; i
< 63; i
++)
7545 specs
[count
] = tmpl
;
7546 specs
[count
++].index
= i
;
7550 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7552 for (i
= 16; i
< 63; i
++)
7554 specs
[count
] = tmpl
;
7555 specs
[count
++].index
= i
;
7563 else if (note
== 11) /* note 11 implies note 1 as well */
7567 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7569 if (idesc
->operands
[i
] == IA64_OPND_P1
7570 || idesc
->operands
[i
] == IA64_OPND_P2
)
7572 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7573 if (regno
>= 16 && regno
< 63)
7575 specs
[count
] = tmpl
;
7576 specs
[count
++].index
= regno
;
7586 else if (note
== 12)
7588 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7590 specs
[count
] = tmpl
;
7591 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7598 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7599 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7600 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
7601 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
7603 if ((idesc
->operands
[0] == IA64_OPND_P1
7604 || idesc
->operands
[0] == IA64_OPND_P2
)
7605 && p1
>= 16 && p1
< 63)
7607 specs
[count
] = tmpl
;
7608 specs
[count
].cmp_type
=
7609 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7610 specs
[count
++].index
= p1
;
7612 if ((idesc
->operands
[1] == IA64_OPND_P1
7613 || idesc
->operands
[1] == IA64_OPND_P2
)
7614 && p2
>= 16 && p2
< 63)
7616 specs
[count
] = tmpl
;
7617 specs
[count
].cmp_type
=
7618 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7619 specs
[count
++].index
= p2
;
7624 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
7626 specs
[count
] = tmpl
;
7627 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7629 if (idesc
->operands
[1] == IA64_OPND_PR
)
7631 for (i
= 16; i
< 63; i
++)
7633 specs
[count
] = tmpl
;
7634 specs
[count
++].index
= i
;
7646 /* Verify that the instruction is using the PSR bit indicated in
7650 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7652 if (dep
->regindex
< 6)
7654 specs
[count
++] = tmpl
;
7657 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7659 if (dep
->regindex
< 32
7660 || dep
->regindex
== 35
7661 || dep
->regindex
== 36
7662 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7664 specs
[count
++] = tmpl
;
7667 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7669 if (dep
->regindex
< 32
7670 || dep
->regindex
== 35
7671 || dep
->regindex
== 36
7672 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7674 specs
[count
++] = tmpl
;
7679 /* Several PSR bits have very specific dependencies. */
7680 switch (dep
->regindex
)
7683 specs
[count
++] = tmpl
;
7688 specs
[count
++] = tmpl
;
7692 /* Only certain CR accesses use PSR.ic */
7693 if (idesc
->operands
[0] == IA64_OPND_CR3
7694 || idesc
->operands
[1] == IA64_OPND_CR3
)
7697 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7700 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7715 specs
[count
++] = tmpl
;
7724 specs
[count
++] = tmpl
;
7728 /* Only some AR accesses use cpl */
7729 if (idesc
->operands
[0] == IA64_OPND_AR3
7730 || idesc
->operands
[1] == IA64_OPND_AR3
)
7733 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7736 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7743 && regno
<= AR_K7
))))
7745 specs
[count
++] = tmpl
;
7750 specs
[count
++] = tmpl
;
7760 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7762 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7768 if (mask
& ((valueT
) 1 << dep
->regindex
))
7770 specs
[count
++] = tmpl
;
7775 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7776 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7777 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7778 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7780 if (idesc
->operands
[i
] == IA64_OPND_F1
7781 || idesc
->operands
[i
] == IA64_OPND_F2
7782 || idesc
->operands
[i
] == IA64_OPND_F3
7783 || idesc
->operands
[i
] == IA64_OPND_F4
)
7785 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7786 if (reg
>= min
&& reg
<= max
)
7788 specs
[count
++] = tmpl
;
7795 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7796 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7797 /* mfh is read on writes to FR32-127; mfl is read on writes to
7799 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7801 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7803 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7804 if (reg
>= min
&& reg
<= max
)
7806 specs
[count
++] = tmpl
;
7811 else if (note
== 10)
7813 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7815 if (idesc
->operands
[i
] == IA64_OPND_R1
7816 || idesc
->operands
[i
] == IA64_OPND_R2
7817 || idesc
->operands
[i
] == IA64_OPND_R3
)
7819 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7820 if (regno
>= 16 && regno
<= 31)
7822 specs
[count
++] = tmpl
;
7833 case IA64_RS_AR_FPSR
:
7834 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7836 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7837 if (regno
== AR_FPSR
)
7839 specs
[count
++] = tmpl
;
7844 specs
[count
++] = tmpl
;
7849 /* Handle all AR[REG] resources */
7850 if (note
== 0 || note
== 1)
7852 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7853 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7854 && regno
== dep
->regindex
)
7856 specs
[count
++] = tmpl
;
7858 /* other AR[REG] resources may be affected by AR accesses */
7859 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7862 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7863 switch (dep
->regindex
)
7869 if (regno
== AR_BSPSTORE
)
7871 specs
[count
++] = tmpl
;
7875 (regno
== AR_BSPSTORE
7876 || regno
== AR_RNAT
))
7878 specs
[count
++] = tmpl
;
7883 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7886 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
7887 switch (dep
->regindex
)
7892 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
7894 specs
[count
++] = tmpl
;
7901 specs
[count
++] = tmpl
;
7911 /* Handle all CR[REG] resources */
7912 if (note
== 0 || note
== 1)
7914 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7916 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7917 if (regno
== dep
->regindex
)
7919 specs
[count
++] = tmpl
;
7921 else if (!rsrc_write
)
7923 /* Reads from CR[IVR] affect other resources. */
7924 if (regno
== CR_IVR
)
7926 if ((dep
->regindex
>= CR_IRR0
7927 && dep
->regindex
<= CR_IRR3
)
7928 || dep
->regindex
== CR_TPR
)
7930 specs
[count
++] = tmpl
;
7937 specs
[count
++] = tmpl
;
7946 case IA64_RS_INSERVICE
:
7947 /* look for write of EOI (67) or read of IVR (65) */
7948 if ((idesc
->operands
[0] == IA64_OPND_CR3
7949 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
7950 || (idesc
->operands
[1] == IA64_OPND_CR3
7951 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
7953 specs
[count
++] = tmpl
;
7960 specs
[count
++] = tmpl
;
7971 specs
[count
++] = tmpl
;
7975 /* Check if any of the registers accessed are in the rotating region.
7976 mov to/from pr accesses CFM only when qp_regno is in the rotating
7978 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7980 if (idesc
->operands
[i
] == IA64_OPND_R1
7981 || idesc
->operands
[i
] == IA64_OPND_R2
7982 || idesc
->operands
[i
] == IA64_OPND_R3
)
7984 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7985 /* Assumes that md.rot.num_regs is always valid */
7986 if (md
.rot
.num_regs
> 0
7988 && num
< 31 + md
.rot
.num_regs
)
7990 specs
[count
] = tmpl
;
7991 specs
[count
++].specific
= 0;
7994 else if (idesc
->operands
[i
] == IA64_OPND_F1
7995 || idesc
->operands
[i
] == IA64_OPND_F2
7996 || idesc
->operands
[i
] == IA64_OPND_F3
7997 || idesc
->operands
[i
] == IA64_OPND_F4
)
7999 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8002 specs
[count
] = tmpl
;
8003 specs
[count
++].specific
= 0;
8006 else if (idesc
->operands
[i
] == IA64_OPND_P1
8007 || idesc
->operands
[i
] == IA64_OPND_P2
)
8009 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8012 specs
[count
] = tmpl
;
8013 specs
[count
++].specific
= 0;
8017 if (CURR_SLOT
.qp_regno
> 15)
8019 specs
[count
] = tmpl
;
8020 specs
[count
++].specific
= 0;
8025 /* This is the same as IA64_RS_PRr, except simplified to account for
8026 the fact that there is only one register. */
8030 specs
[count
++] = tmpl
;
8035 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8036 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8037 if (mask
& ((valueT
) 1 << 63))
8038 specs
[count
++] = tmpl
;
8040 else if (note
== 11)
8042 if ((idesc
->operands
[0] == IA64_OPND_P1
8043 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8044 || (idesc
->operands
[1] == IA64_OPND_P2
8045 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8047 specs
[count
++] = tmpl
;
8050 else if (note
== 12)
8052 if (CURR_SLOT
.qp_regno
== 63)
8054 specs
[count
++] = tmpl
;
8061 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8062 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8063 int or_andcm
= strstr(idesc
->name
, "or.andcm") != NULL
;
8064 int and_orcm
= strstr(idesc
->name
, "and.orcm") != NULL
;
8067 && (idesc
->operands
[0] == IA64_OPND_P1
8068 || idesc
->operands
[0] == IA64_OPND_P2
))
8070 specs
[count
] = tmpl
;
8071 specs
[count
++].cmp_type
=
8072 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8075 && (idesc
->operands
[1] == IA64_OPND_P1
8076 || idesc
->operands
[1] == IA64_OPND_P2
))
8078 specs
[count
] = tmpl
;
8079 specs
[count
++].cmp_type
=
8080 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8085 if (CURR_SLOT
.qp_regno
== 63)
8087 specs
[count
++] = tmpl
;
8098 /* FIXME we can identify some individual RSE written resources, but RSE
8099 read resources have not yet been completely identified, so for now
8100 treat RSE as a single resource */
8101 if (strncmp (idesc
->name
, "mov", 3) == 0)
8105 if (idesc
->operands
[0] == IA64_OPND_AR3
8106 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8108 specs
[count
] = tmpl
;
8109 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8114 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8116 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8117 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8119 specs
[count
++] = tmpl
;
8122 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8124 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8125 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8126 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8128 specs
[count
++] = tmpl
;
8135 specs
[count
++] = tmpl
;
8140 /* FIXME -- do any of these need to be non-specific? */
8141 specs
[count
++] = tmpl
;
8145 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8152 /* Clear branch flags on marked resources. This breaks the link between the
8153 QP of the marking instruction and a subsequent branch on the same QP. */
8156 clear_qp_branch_flag (mask
)
8160 for (i
= 0; i
< regdepslen
; i
++)
8162 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8163 if ((bit
& mask
) != 0)
8165 regdeps
[i
].link_to_qp_branch
= 0;
8170 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8172 Any changes to a PR clears the mutex relations which include that PR. */
8175 clear_qp_mutex (mask
)
8181 while (i
< qp_mutexeslen
)
8183 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8187 fprintf (stderr
, " Clearing mutex relation");
8188 print_prmask (qp_mutexes
[i
].prmask
);
8189 fprintf (stderr
, "\n");
8191 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8198 /* Clear implies relations which contain PRs in the given masks.
8199 P1_MASK indicates the source of the implies relation, while P2_MASK
8200 indicates the implied PR. */
8203 clear_qp_implies (p1_mask
, p2_mask
)
8210 while (i
< qp_implieslen
)
8212 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8213 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8216 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8217 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8218 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8225 /* Add the PRs specified to the list of implied relations. */
8228 add_qp_imply (p1
, p2
)
8235 /* p0 is not meaningful here. */
8236 if (p1
== 0 || p2
== 0)
8242 /* If it exists already, ignore it. */
8243 for (i
= 0; i
< qp_implieslen
; i
++)
8245 if (qp_implies
[i
].p1
== p1
8246 && qp_implies
[i
].p2
== p2
8247 && qp_implies
[i
].path
== md
.path
8248 && !qp_implies
[i
].p2_branched
)
8252 if (qp_implieslen
== qp_impliestotlen
)
8254 qp_impliestotlen
+= 20;
8255 qp_implies
= (struct qp_imply
*)
8256 xrealloc ((void *) qp_implies
,
8257 qp_impliestotlen
* sizeof (struct qp_imply
));
8260 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8261 qp_implies
[qp_implieslen
].p1
= p1
;
8262 qp_implies
[qp_implieslen
].p2
= p2
;
8263 qp_implies
[qp_implieslen
].path
= md
.path
;
8264 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8266 /* Add in the implied transitive relations; for everything that p2 implies,
8267 make p1 imply that, too; for everything that implies p1, make it imply p2
8269 for (i
= 0; i
< qp_implieslen
; i
++)
8271 if (qp_implies
[i
].p1
== p2
)
8272 add_qp_imply (p1
, qp_implies
[i
].p2
);
8273 if (qp_implies
[i
].p2
== p1
)
8274 add_qp_imply (qp_implies
[i
].p1
, p2
);
8276 /* Add in mutex relations implied by this implies relation; for each mutex
8277 relation containing p2, duplicate it and replace p2 with p1. */
8278 bit
= (valueT
) 1 << p1
;
8279 mask
= (valueT
) 1 << p2
;
8280 for (i
= 0; i
< qp_mutexeslen
; i
++)
8282 if (qp_mutexes
[i
].prmask
& mask
)
8283 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8287 /* Add the PRs specified in the mask to the mutex list; this means that only
8288 one of the PRs can be true at any time. PR0 should never be included in
8298 if (qp_mutexeslen
== qp_mutexestotlen
)
8300 qp_mutexestotlen
+= 20;
8301 qp_mutexes
= (struct qpmutex
*)
8302 xrealloc ((void *) qp_mutexes
,
8303 qp_mutexestotlen
* sizeof (struct qpmutex
));
8307 fprintf (stderr
, " Registering mutex on");
8308 print_prmask (mask
);
8309 fprintf (stderr
, "\n");
8311 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8312 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8316 clear_register_values ()
8320 fprintf (stderr
, " Clearing register values\n");
8321 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8322 gr_values
[i
].known
= 0;
8325 /* Keep track of register values/changes which affect DV tracking.
8327 optimization note: should add a flag to classes of insns where otherwise we
8328 have to examine a group of strings to identify them. */
8331 note_register_values (idesc
)
8332 struct ia64_opcode
*idesc
;
8334 valueT qp_changemask
= 0;
8337 /* Invalidate values for registers being written to. */
8338 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8340 if (idesc
->operands
[i
] == IA64_OPND_R1
8341 || idesc
->operands
[i
] == IA64_OPND_R2
8342 || idesc
->operands
[i
] == IA64_OPND_R3
)
8344 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8345 if (regno
> 0 && regno
< NELEMS (gr_values
))
8346 gr_values
[regno
].known
= 0;
8348 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8350 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8351 if (regno
> 0 && regno
< 4)
8352 gr_values
[regno
].known
= 0;
8354 else if (idesc
->operands
[i
] == IA64_OPND_P1
8355 || idesc
->operands
[i
] == IA64_OPND_P2
)
8357 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8358 qp_changemask
|= (valueT
) 1 << regno
;
8360 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8362 if (idesc
->operands
[2] & (valueT
) 0x10000)
8363 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8365 qp_changemask
= idesc
->operands
[2];
8368 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8370 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8371 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8373 qp_changemask
= idesc
->operands
[1];
8374 qp_changemask
&= ~(valueT
) 0xFFFF;
8379 /* Always clear qp branch flags on any PR change. */
8380 /* FIXME there may be exceptions for certain compares. */
8381 clear_qp_branch_flag (qp_changemask
);
8383 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8384 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8386 qp_changemask
|= ~(valueT
) 0xFFFF;
8387 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8389 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8390 gr_values
[i
].known
= 0;
8392 clear_qp_mutex (qp_changemask
);
8393 clear_qp_implies (qp_changemask
, qp_changemask
);
8395 /* After a call, all register values are undefined, except those marked
8397 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8398 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8400 /* FIXME keep GR values which are marked as "safe_across_calls" */
8401 clear_register_values ();
8402 clear_qp_mutex (~qp_safe_across_calls
);
8403 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8404 clear_qp_branch_flag (~qp_safe_across_calls
);
8406 else if (is_interruption_or_rfi (idesc
)
8407 || is_taken_branch (idesc
))
8409 clear_register_values ();
8410 clear_qp_mutex (~(valueT
) 0);
8411 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8413 /* Look for mutex and implies relations. */
8414 else if ((idesc
->operands
[0] == IA64_OPND_P1
8415 || idesc
->operands
[0] == IA64_OPND_P2
)
8416 && (idesc
->operands
[1] == IA64_OPND_P1
8417 || idesc
->operands
[1] == IA64_OPND_P2
))
8419 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8420 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8421 valueT p1mask
= (valueT
) 1 << p1
;
8422 valueT p2mask
= (valueT
) 1 << p2
;
8424 /* If one of the PRs is PR0, we can't really do anything. */
8425 if (p1
== 0 || p2
== 0)
8428 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8430 /* In general, clear mutexes and implies which include P1 or P2,
8431 with the following exceptions. */
8432 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
8434 add_qp_mutex (p1mask
| p2mask
);
8435 clear_qp_implies (p2mask
, p1mask
);
8437 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
8439 add_qp_mutex (p1mask
| p2mask
);
8440 clear_qp_implies (p1mask
, p2mask
);
8442 else if (strstr (idesc
->name
, ".and") != NULL
)
8444 clear_qp_implies (0, p1mask
| p2mask
);
8446 else if (strstr (idesc
->name
, ".or") != NULL
)
8448 clear_qp_mutex (p1mask
| p2mask
);
8449 clear_qp_implies (p1mask
| p2mask
, 0);
8453 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8454 if (strstr (idesc
->name
, ".unc") != NULL
)
8456 add_qp_mutex (p1mask
| p2mask
);
8457 if (CURR_SLOT
.qp_regno
!= 0)
8459 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8460 CURR_SLOT
.qp_regno
);
8461 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8462 CURR_SLOT
.qp_regno
);
8465 else if (CURR_SLOT
.qp_regno
== 0)
8467 add_qp_mutex (p1mask
| p2mask
);
8471 clear_qp_mutex (p1mask
| p2mask
);
8475 /* Look for mov imm insns into GRs. */
8476 else if (idesc
->operands
[0] == IA64_OPND_R1
8477 && (idesc
->operands
[1] == IA64_OPND_IMM22
8478 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8479 && (strcmp (idesc
->name
, "mov") == 0
8480 || strcmp (idesc
->name
, "movl") == 0))
8482 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8483 if (regno
> 0 && regno
< NELEMS (gr_values
))
8485 gr_values
[regno
].known
= 1;
8486 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8487 gr_values
[regno
].path
= md
.path
;
8490 fprintf (stderr
, " Know gr%d = ", regno
);
8491 fprintf_vma (stderr
, gr_values
[regno
].value
);
8492 fputs ("\n", stderr
);
8498 clear_qp_mutex (qp_changemask
);
8499 clear_qp_implies (qp_changemask
, qp_changemask
);
8503 /* Return whether the given predicate registers are currently mutex. */
8506 qp_mutex (p1
, p2
, path
)
8516 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8517 for (i
= 0; i
< qp_mutexeslen
; i
++)
8519 if (qp_mutexes
[i
].path
>= path
8520 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8527 /* Return whether the given resource is in the given insn's list of chks
8528 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8532 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8534 struct ia64_opcode
*idesc
;
8539 struct rsrc specs
[MAX_SPECS
];
8542 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8543 we don't need to check. One exception is note 11, which indicates that
8544 target predicates are written regardless of PR[qp]. */
8545 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8549 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
8552 /* UNAT checking is a bit more specific than other resources */
8553 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
8554 && specs
[count
].mem_offset
.hint
8555 && rs
->mem_offset
.hint
)
8557 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
8559 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
8560 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
8567 /* Skip apparent PR write conflicts where both writes are an AND or both
8568 writes are an OR. */
8569 if (rs
->dependency
->specifier
== IA64_RS_PR
8570 || rs
->dependency
->specifier
== IA64_RS_PRr
8571 || rs
->dependency
->specifier
== IA64_RS_PR63
)
8573 if (specs
[count
].cmp_type
!= CMP_NONE
8574 && specs
[count
].cmp_type
== rs
->cmp_type
)
8577 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
8578 dv_mode
[rs
->dependency
->mode
],
8579 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8580 specs
[count
].index
: 63);
8585 " %s on parallel compare conflict %s vs %s on PR%d\n",
8586 dv_mode
[rs
->dependency
->mode
],
8587 dv_cmp_type
[rs
->cmp_type
],
8588 dv_cmp_type
[specs
[count
].cmp_type
],
8589 rs
->dependency
->specifier
!= IA64_RS_PR63
?
8590 specs
[count
].index
: 63);
8594 /* If either resource is not specific, conservatively assume a conflict
8596 if (!specs
[count
].specific
|| !rs
->specific
)
8598 else if (specs
[count
].index
== rs
->index
)
8603 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
8609 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
8610 insert a stop to create the break. Update all resource dependencies
8611 appropriately. If QP_REGNO is non-zero, only apply the break to resources
8612 which use the same QP_REGNO and have the link_to_qp_branch flag set.
8613 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
8617 insn_group_break (insert_stop
, qp_regno
, save_current
)
8624 if (insert_stop
&& md
.num_slots_in_use
> 0)
8625 PREV_SLOT
.end_of_insn_group
= 1;
8629 fprintf (stderr
, " Insn group break%s",
8630 (insert_stop
? " (w/stop)" : ""));
8632 fprintf (stderr
, " effective for QP=%d", qp_regno
);
8633 fprintf (stderr
, "\n");
8637 while (i
< regdepslen
)
8639 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
8642 && regdeps
[i
].qp_regno
!= qp_regno
)
8649 && CURR_SLOT
.src_file
== regdeps
[i
].file
8650 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
8656 /* clear dependencies which are automatically cleared by a stop, or
8657 those that have reached the appropriate state of insn serialization */
8658 if (dep
->semantics
== IA64_DVS_IMPLIED
8659 || dep
->semantics
== IA64_DVS_IMPLIEDF
8660 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
8662 print_dependency ("Removing", i
);
8663 regdeps
[i
] = regdeps
[--regdepslen
];
8667 if (dep
->semantics
== IA64_DVS_DATA
8668 || dep
->semantics
== IA64_DVS_INSTR
8669 || dep
->semantics
== IA64_DVS_SPECIFIC
)
8671 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
8672 regdeps
[i
].insn_srlz
= STATE_STOP
;
8673 if (regdeps
[i
].data_srlz
== STATE_NONE
)
8674 regdeps
[i
].data_srlz
= STATE_STOP
;
8681 /* Add the given resource usage spec to the list of active dependencies. */
8684 mark_resource (idesc
, dep
, spec
, depind
, path
)
8685 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
8686 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
8691 if (regdepslen
== regdepstotlen
)
8693 regdepstotlen
+= 20;
8694 regdeps
= (struct rsrc
*)
8695 xrealloc ((void *) regdeps
,
8696 regdepstotlen
* sizeof (struct rsrc
));
8699 regdeps
[regdepslen
] = *spec
;
8700 regdeps
[regdepslen
].depind
= depind
;
8701 regdeps
[regdepslen
].path
= path
;
8702 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8703 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8705 print_dependency ("Adding", regdepslen
);
8711 print_dependency (action
, depind
)
8717 fprintf (stderr
, " %s %s '%s'",
8718 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8719 (regdeps
[depind
].dependency
)->name
);
8720 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8721 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8722 if (regdeps
[depind
].mem_offset
.hint
)
8724 fputs (" ", stderr
);
8725 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
8726 fputs ("+", stderr
);
8727 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
8729 fprintf (stderr
, "\n");
8734 instruction_serialization ()
8738 fprintf (stderr
, " Instruction serialization\n");
8739 for (i
= 0; i
< regdepslen
; i
++)
8740 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8741 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8745 data_serialization ()
8749 fprintf (stderr
, " Data serialization\n");
8750 while (i
< regdepslen
)
8752 if (regdeps
[i
].data_srlz
== STATE_STOP
8753 /* Note: as of 991210, all "other" dependencies are cleared by a
8754 data serialization. This might change with new tables */
8755 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8757 print_dependency ("Removing", i
);
8758 regdeps
[i
] = regdeps
[--regdepslen
];
8765 /* Insert stops and serializations as needed to avoid DVs. */
8768 remove_marked_resource (rs
)
8771 switch (rs
->dependency
->semantics
)
8773 case IA64_DVS_SPECIFIC
:
8775 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8776 /* ...fall through... */
8777 case IA64_DVS_INSTR
:
8779 fprintf (stderr
, "Inserting instr serialization\n");
8780 if (rs
->insn_srlz
< STATE_STOP
)
8781 insn_group_break (1, 0, 0);
8782 if (rs
->insn_srlz
< STATE_SRLZ
)
8784 int oldqp
= CURR_SLOT
.qp_regno
;
8785 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8786 /* Manually jam a srlz.i insn into the stream */
8787 CURR_SLOT
.qp_regno
= 0;
8788 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8789 instruction_serialization ();
8790 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8791 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8793 CURR_SLOT
.qp_regno
= oldqp
;
8794 CURR_SLOT
.idesc
= oldidesc
;
8796 insn_group_break (1, 0, 0);
8798 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8799 "other" types of DV are eliminated
8800 by a data serialization */
8803 fprintf (stderr
, "Inserting data serialization\n");
8804 if (rs
->data_srlz
< STATE_STOP
)
8805 insn_group_break (1, 0, 0);
8807 int oldqp
= CURR_SLOT
.qp_regno
;
8808 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8809 /* Manually jam a srlz.d insn into the stream */
8810 CURR_SLOT
.qp_regno
= 0;
8811 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8812 data_serialization ();
8813 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8814 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8816 CURR_SLOT
.qp_regno
= oldqp
;
8817 CURR_SLOT
.idesc
= oldidesc
;
8820 case IA64_DVS_IMPLIED
:
8821 case IA64_DVS_IMPLIEDF
:
8823 fprintf (stderr
, "Inserting stop\n");
8824 insn_group_break (1, 0, 0);
8831 /* Check the resources used by the given opcode against the current dependency
8834 The check is run once for each execution path encountered. In this case,
8835 a unique execution path is the sequence of instructions following a code
8836 entry point, e.g. the following has three execution paths, one starting
8837 at L0, one at L1, and one at L2.
8846 check_dependencies (idesc
)
8847 struct ia64_opcode
*idesc
;
8849 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8853 /* Note that the number of marked resources may change within the
8854 loop if in auto mode. */
8856 while (i
< regdepslen
)
8858 struct rsrc
*rs
= ®deps
[i
];
8859 const struct ia64_dependency
*dep
= rs
->dependency
;
8864 if (dep
->semantics
== IA64_DVS_NONE
8865 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8871 note
= NOTE (opdeps
->chks
[chkind
]);
8873 /* Check this resource against each execution path seen thus far. */
8874 for (path
= 0; path
<= md
.path
; path
++)
8878 /* If the dependency wasn't on the path being checked, ignore it. */
8879 if (rs
->path
< path
)
8882 /* If the QP for this insn implies a QP which has branched, don't
8883 bother checking. Ed. NOTE: I don't think this check is terribly
8884 useful; what's the point of generating code which will only be
8885 reached if its QP is zero?
8886 This code was specifically inserted to handle the following code,
8887 based on notes from Intel's DV checking code, where p1 implies p2.
8893 if (CURR_SLOT
.qp_regno
!= 0)
8897 for (implies
= 0; implies
< qp_implieslen
; implies
++)
8899 if (qp_implies
[implies
].path
>= path
8900 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
8901 && qp_implies
[implies
].p2_branched
)
8911 if ((matchtype
= resources_match (rs
, idesc
, note
,
8912 CURR_SLOT
.qp_regno
, path
)) != 0)
8915 char pathmsg
[256] = "";
8916 char indexmsg
[256] = "";
8917 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
8920 sprintf (pathmsg
, " when entry is at label '%s'",
8921 md
.entry_labels
[path
- 1]);
8922 if (rs
->specific
&& rs
->index
!= 0)
8923 sprintf (indexmsg
, ", specific resource number is %d",
8925 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8927 (certain
? "violates" : "may violate"),
8928 dv_mode
[dep
->mode
], dep
->name
,
8929 dv_sem
[dep
->semantics
],
8932 if (md
.explicit_mode
)
8934 as_warn ("%s", msg
);
8936 as_warn (_("Only the first path encountering the conflict "
8938 as_warn_where (rs
->file
, rs
->line
,
8939 _("This is the location of the "
8940 "conflicting usage"));
8941 /* Don't bother checking other paths, to avoid duplicating
8948 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
8950 remove_marked_resource (rs
);
8952 /* since the set of dependencies has changed, start over */
8953 /* FIXME -- since we're removing dvs as we go, we
8954 probably don't really need to start over... */
8967 /* Register new dependencies based on the given opcode. */
8970 mark_resources (idesc
)
8971 struct ia64_opcode
*idesc
;
8974 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8975 int add_only_qp_reads
= 0;
8977 /* A conditional branch only uses its resources if it is taken; if it is
8978 taken, we stop following that path. The other branch types effectively
8979 *always* write their resources. If it's not taken, register only QP
8981 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
8983 add_only_qp_reads
= 1;
8987 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
8989 for (i
= 0; i
< opdeps
->nregs
; i
++)
8991 const struct ia64_dependency
*dep
;
8992 struct rsrc specs
[MAX_SPECS
];
8997 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
8998 note
= NOTE (opdeps
->regs
[i
]);
9000 if (add_only_qp_reads
9001 && !(dep
->mode
== IA64_DV_WAR
9002 && (dep
->specifier
== IA64_RS_PR
9003 || dep
->specifier
== IA64_RS_PRr
9004 || dep
->specifier
== IA64_RS_PR63
)))
9007 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9010 if (md
.debug_dv
&& !count
)
9011 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9012 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9017 mark_resource (idesc
, dep
, &specs
[count
],
9018 DEP (opdeps
->regs
[i
]), md
.path
);
9021 /* The execution path may affect register values, which may in turn
9022 affect which indirect-access resources are accessed. */
9023 switch (dep
->specifier
)
9035 for (path
= 0; path
< md
.path
; path
++)
9037 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9039 mark_resource (idesc
, dep
, &specs
[count
],
9040 DEP (opdeps
->regs
[i
]), path
);
9047 /* Remove dependencies when they no longer apply. */
9050 update_dependencies (idesc
)
9051 struct ia64_opcode
*idesc
;
9055 if (strcmp (idesc
->name
, "srlz.i") == 0)
9057 instruction_serialization ();
9059 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9061 data_serialization ();
9063 else if (is_interruption_or_rfi (idesc
)
9064 || is_taken_branch (idesc
))
9066 /* Although technically the taken branch doesn't clear dependencies
9067 which require a srlz.[id], we don't follow the branch; the next
9068 instruction is assumed to start with a clean slate. */
9072 else if (is_conditional_branch (idesc
)
9073 && CURR_SLOT
.qp_regno
!= 0)
9075 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9077 for (i
= 0; i
< qp_implieslen
; i
++)
9079 /* If the conditional branch's predicate is implied by the predicate
9080 in an existing dependency, remove that dependency. */
9081 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9084 /* Note that this implied predicate takes a branch so that if
9085 a later insn generates a DV but its predicate implies this
9086 one, we can avoid the false DV warning. */
9087 qp_implies
[i
].p2_branched
= 1;
9088 while (depind
< regdepslen
)
9090 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9092 print_dependency ("Removing", depind
);
9093 regdeps
[depind
] = regdeps
[--regdepslen
];
9100 /* Any marked resources which have this same predicate should be
9101 cleared, provided that the QP hasn't been modified between the
9102 marking instruction and the branch. */
9105 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9110 while (i
< regdepslen
)
9112 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9113 && regdeps
[i
].link_to_qp_branch
9114 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9115 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9117 /* Treat like a taken branch */
9118 print_dependency ("Removing", i
);
9119 regdeps
[i
] = regdeps
[--regdepslen
];
9128 /* Examine the current instruction for dependency violations. */
9132 struct ia64_opcode
*idesc
;
9136 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9137 idesc
->name
, CURR_SLOT
.src_line
,
9138 idesc
->dependencies
->nchks
,
9139 idesc
->dependencies
->nregs
);
9142 /* Look through the list of currently marked resources; if the current
9143 instruction has the dependency in its chks list which uses that resource,
9144 check against the specific resources used. */
9145 check_dependencies (idesc
);
9147 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9148 then add them to the list of marked resources. */
9149 mark_resources (idesc
);
9151 /* There are several types of dependency semantics, and each has its own
9152 requirements for being cleared
9154 Instruction serialization (insns separated by interruption, rfi, or
9155 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9157 Data serialization (instruction serialization, or writer + srlz.d +
9158 reader, where writer and srlz.d are in separate groups) clears
9159 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9160 always be the case).
9162 Instruction group break (groups separated by stop, taken branch,
9163 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9165 update_dependencies (idesc
);
9167 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9168 warning. Keep track of as many as possible that are useful. */
9169 note_register_values (idesc
);
9171 /* We don't need or want this anymore. */
9172 md
.mem_offset
.hint
= 0;
9177 /* Translate one line of assembly. Pseudo ops and labels do not show
9183 char *saved_input_line_pointer
, *mnemonic
;
9184 const struct pseudo_opcode
*pdesc
;
9185 struct ia64_opcode
*idesc
;
9186 unsigned char qp_regno
;
9190 saved_input_line_pointer
= input_line_pointer
;
9191 input_line_pointer
= str
;
9193 /* extract the opcode (mnemonic): */
9195 mnemonic
= input_line_pointer
;
9196 ch
= get_symbol_end ();
9197 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9200 *input_line_pointer
= ch
;
9201 (*pdesc
->handler
) (pdesc
->arg
);
9205 /* Find the instruction descriptor matching the arguments. */
9207 idesc
= ia64_find_opcode (mnemonic
);
9208 *input_line_pointer
= ch
;
9211 as_bad ("Unknown opcode `%s'", mnemonic
);
9215 idesc
= parse_operands (idesc
);
9219 /* Handle the dynamic ops we can handle now: */
9220 if (idesc
->type
== IA64_TYPE_DYN
)
9222 if (strcmp (idesc
->name
, "add") == 0)
9224 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9225 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9229 ia64_free_opcode (idesc
);
9230 idesc
= ia64_find_opcode (mnemonic
);
9232 know (!idesc
->next
);
9235 else if (strcmp (idesc
->name
, "mov") == 0)
9237 enum ia64_opnd opnd1
, opnd2
;
9240 opnd1
= idesc
->operands
[0];
9241 opnd2
= idesc
->operands
[1];
9242 if (opnd1
== IA64_OPND_AR3
)
9244 else if (opnd2
== IA64_OPND_AR3
)
9248 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9249 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9253 ia64_free_opcode (idesc
);
9254 idesc
= ia64_find_opcode (mnemonic
);
9255 while (idesc
!= NULL
9256 && (idesc
->operands
[0] != opnd1
9257 || idesc
->operands
[1] != opnd2
))
9258 idesc
= get_next_opcode (idesc
);
9263 if (md
.qp
.X_op
== O_register
)
9265 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9266 md
.qp
.X_op
= O_absent
;
9269 flags
= idesc
->flags
;
9271 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9272 insn_group_break (1, 0, 0);
9274 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9276 as_bad ("`%s' cannot be predicated", idesc
->name
);
9280 /* Build the instruction. */
9281 CURR_SLOT
.qp_regno
= qp_regno
;
9282 CURR_SLOT
.idesc
= idesc
;
9283 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9284 dwarf2_where (&CURR_SLOT
.debug_line
);
9286 /* Add unwind entry, if there is one. */
9287 if (unwind
.current_entry
)
9289 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9290 unwind
.current_entry
= NULL
;
9293 /* Check for dependency violations. */
9297 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9298 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9301 if ((flags
& IA64_OPCODE_LAST
) != 0)
9302 insn_group_break (1, 0, 0);
9304 md
.last_text_seg
= now_seg
;
9307 input_line_pointer
= saved_input_line_pointer
;
9310 /* Called when symbol NAME cannot be found in the symbol table.
9311 Should be used for dynamic valued symbols only. */
9314 md_undefined_symbol (name
)
9315 char *name ATTRIBUTE_UNUSED
;
9320 /* Called for any expression that can not be recognized. When the
9321 function is called, `input_line_pointer' will point to the start of
9328 enum pseudo_type pseudo_type
;
9333 switch (*input_line_pointer
)
9336 /* Find what relocation pseudo-function we're dealing with. */
9338 ch
= *++input_line_pointer
;
9339 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9340 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9342 len
= strlen (pseudo_func
[i
].name
);
9343 if (strncmp (pseudo_func
[i
].name
+ 1,
9344 input_line_pointer
+ 1, len
- 1) == 0
9345 && !is_part_of_name (input_line_pointer
[len
]))
9347 input_line_pointer
+= len
;
9348 pseudo_type
= pseudo_func
[i
].type
;
9352 switch (pseudo_type
)
9354 case PSEUDO_FUNC_RELOC
:
9356 if (*input_line_pointer
!= '(')
9358 as_bad ("Expected '('");
9362 ++input_line_pointer
;
9364 if (*input_line_pointer
++ != ')')
9366 as_bad ("Missing ')'");
9369 if (e
->X_op
!= O_symbol
)
9371 if (e
->X_op
!= O_pseudo_fixup
)
9373 as_bad ("Not a symbolic expression");
9376 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9377 && i
== FUNC_LT_RELATIVE
)
9378 i
= FUNC_LT_FPTR_RELATIVE
;
9381 as_bad ("Illegal combination of relocation functions");
9385 /* Make sure gas doesn't get rid of local symbols that are used
9387 e
->X_op
= O_pseudo_fixup
;
9388 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9391 case PSEUDO_FUNC_CONST
:
9392 e
->X_op
= O_constant
;
9393 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9396 case PSEUDO_FUNC_REG
:
9397 e
->X_op
= O_register
;
9398 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9402 name
= input_line_pointer
- 1;
9404 as_bad ("Unknown pseudo function `%s'", name
);
9410 ++input_line_pointer
;
9412 if (*input_line_pointer
!= ']')
9414 as_bad ("Closing bracket misssing");
9419 if (e
->X_op
!= O_register
)
9420 as_bad ("Register expected as index");
9422 ++input_line_pointer
;
9433 ignore_rest_of_line ();
9436 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9437 a section symbol plus some offset. For relocs involving @fptr(),
9438 directives we don't want such adjustments since we need to have the
9439 original symbol's name in the reloc. */
9441 ia64_fix_adjustable (fix
)
9444 /* Prevent all adjustments to global symbols */
9445 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9448 switch (fix
->fx_r_type
)
9450 case BFD_RELOC_IA64_FPTR64I
:
9451 case BFD_RELOC_IA64_FPTR32MSB
:
9452 case BFD_RELOC_IA64_FPTR32LSB
:
9453 case BFD_RELOC_IA64_FPTR64MSB
:
9454 case BFD_RELOC_IA64_FPTR64LSB
:
9455 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9456 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9466 ia64_force_relocation (fix
)
9469 switch (fix
->fx_r_type
)
9471 case BFD_RELOC_IA64_FPTR64I
:
9472 case BFD_RELOC_IA64_FPTR32MSB
:
9473 case BFD_RELOC_IA64_FPTR32LSB
:
9474 case BFD_RELOC_IA64_FPTR64MSB
:
9475 case BFD_RELOC_IA64_FPTR64LSB
:
9477 case BFD_RELOC_IA64_LTOFF22
:
9478 case BFD_RELOC_IA64_LTOFF64I
:
9479 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9480 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9481 case BFD_RELOC_IA64_PLTOFF22
:
9482 case BFD_RELOC_IA64_PLTOFF64I
:
9483 case BFD_RELOC_IA64_PLTOFF64MSB
:
9484 case BFD_RELOC_IA64_PLTOFF64LSB
:
9493 /* Decide from what point a pc-relative relocation is relative to,
9494 relative to the pc-relative fixup. Er, relatively speaking. */
9496 ia64_pcrel_from_section (fix
, sec
)
9500 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9502 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9508 /* This is called whenever some data item (not an instruction) needs a
9509 fixup. We pick the right reloc code depending on the byteorder
9510 currently in effect. */
9512 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9518 bfd_reloc_code_real_type code
;
9523 /* There are no reloc for 8 and 16 bit quantities, but we allow
9524 them here since they will work fine as long as the expression
9525 is fully defined at the end of the pass over the source file. */
9526 case 1: code
= BFD_RELOC_8
; break;
9527 case 2: code
= BFD_RELOC_16
; break;
9529 if (target_big_endian
)
9530 code
= BFD_RELOC_IA64_DIR32MSB
;
9532 code
= BFD_RELOC_IA64_DIR32LSB
;
9536 if (target_big_endian
)
9537 code
= BFD_RELOC_IA64_DIR64MSB
;
9539 code
= BFD_RELOC_IA64_DIR64LSB
;
9543 as_bad ("Unsupported fixup size %d", nbytes
);
9544 ignore_rest_of_line ();
9547 if (exp
->X_op
== O_pseudo_fixup
)
9550 exp
->X_op
= O_symbol
;
9551 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
9553 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
9554 /* We need to store the byte order in effect in case we're going
9555 to fix an 8 or 16 bit relocation (for which there no real
9556 relocs available). See md_apply_fix(). */
9557 fix
->tc_fix_data
.bigendian
= target_big_endian
;
9560 /* Return the actual relocation we wish to associate with the pseudo
9561 reloc described by SYM and R_TYPE. SYM should be one of the
9562 symbols in the pseudo_func array, or NULL. */
9564 static bfd_reloc_code_real_type
9565 ia64_gen_real_reloc_type (sym
, r_type
)
9567 bfd_reloc_code_real_type r_type
;
9569 bfd_reloc_code_real_type
new = 0;
9576 switch (S_GET_VALUE (sym
))
9578 case FUNC_FPTR_RELATIVE
:
9581 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
9582 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
9583 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
9584 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
9585 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
9590 case FUNC_GP_RELATIVE
:
9593 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
9594 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
9595 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
9596 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
9597 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
9598 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
9603 case FUNC_LT_RELATIVE
:
9606 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
9607 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
9612 case FUNC_PC_RELATIVE
:
9615 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
9616 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
9617 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
9618 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
9619 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
9620 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
9625 case FUNC_PLT_RELATIVE
:
9628 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
9629 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
9630 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
9631 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
9636 case FUNC_SEC_RELATIVE
:
9639 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
9640 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
9641 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
9642 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
9647 case FUNC_SEG_RELATIVE
:
9650 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
9651 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
9652 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
9653 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
9658 case FUNC_LTV_RELATIVE
:
9661 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
9662 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
9663 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
9664 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
9669 case FUNC_LT_FPTR_RELATIVE
:
9672 case BFD_RELOC_IA64_IMM22
:
9673 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
9674 case BFD_RELOC_IA64_IMM64
:
9675 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
9683 /* Hmmmm. Should this ever occur? */
9690 /* Here is where generate the appropriate reloc for pseudo relocation
9693 ia64_validate_fix (fix
)
9696 switch (fix
->fx_r_type
)
9698 case BFD_RELOC_IA64_FPTR64I
:
9699 case BFD_RELOC_IA64_FPTR32MSB
:
9700 case BFD_RELOC_IA64_FPTR64LSB
:
9701 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9702 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9703 if (fix
->fx_offset
!= 0)
9704 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9705 "No addend allowed in @fptr() relocation");
9715 fix_insn (fix
, odesc
, value
)
9717 const struct ia64_operand
*odesc
;
9720 bfd_vma insn
[3], t0
, t1
, control_bits
;
9725 slot
= fix
->fx_where
& 0x3;
9726 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9728 /* Bundles are always in little-endian byte order */
9729 t0
= bfd_getl64 (fixpos
);
9730 t1
= bfd_getl64 (fixpos
+ 8);
9731 control_bits
= t0
& 0x1f;
9732 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9733 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9734 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9737 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9739 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9740 insn
[2] |= (((value
& 0x7f) << 13)
9741 | (((value
>> 7) & 0x1ff) << 27)
9742 | (((value
>> 16) & 0x1f) << 22)
9743 | (((value
>> 21) & 0x1) << 21)
9744 | (((value
>> 63) & 0x1) << 36));
9746 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9748 if (value
& ~0x3fffffffffffffffULL
)
9749 err
= "integer operand out of range";
9750 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9751 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9753 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9756 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9757 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9758 | (((value
>> 0) & 0xfffff) << 13));
9761 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9764 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9766 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9767 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9768 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
9769 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
9772 /* Attempt to simplify or even eliminate a fixup. The return value is
9773 ignored; perhaps it was once meaningful, but now it is historical.
9774 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9776 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9779 md_apply_fix3 (fix
, valuep
, seg
)
9782 segT seg ATTRIBUTE_UNUSED
;
9785 valueT value
= *valuep
;
9788 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9792 switch (fix
->fx_r_type
)
9794 case BFD_RELOC_IA64_DIR32MSB
:
9795 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9799 case BFD_RELOC_IA64_DIR32LSB
:
9800 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9804 case BFD_RELOC_IA64_DIR64MSB
:
9805 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9809 case BFD_RELOC_IA64_DIR64LSB
:
9810 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9820 if (fix
->fx_r_type
== (int) BFD_RELOC_UNUSED
)
9822 /* This must be a TAG13 or TAG13b operand. There are no external
9823 relocs defined for them, so we must give an error. */
9824 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9825 "%s must have a constant value",
9826 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9831 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9832 work. There should be a better way to handle this. */
9834 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9836 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9838 if (fix
->tc_fix_data
.bigendian
)
9839 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9841 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9847 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9854 /* Generate the BFD reloc to be stuck in the object file from the
9855 fixup used internally in the assembler. */
9858 tc_gen_reloc (sec
, fixp
)
9859 asection
*sec ATTRIBUTE_UNUSED
;
9864 reloc
= xmalloc (sizeof (*reloc
));
9865 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9866 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9867 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9868 reloc
->addend
= fixp
->fx_offset
;
9869 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9873 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9874 "Cannot represent %s relocation in object file",
9875 bfd_get_reloc_code_name (fixp
->fx_r_type
));
9880 /* Turn a string in input_line_pointer into a floating point constant
9881 of type TYPE, and store the appropriate bytes in *LIT. The number
9882 of LITTLENUMS emitted is stored in *SIZE. An error message is
9883 returned, or NULL on OK. */
9885 #define MAX_LITTLENUMS 5
9888 md_atof (type
, lit
, size
)
9893 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
9894 LITTLENUM_TYPE
*word
;
9924 return "Bad call to MD_ATOF()";
9926 t
= atof_ieee (input_line_pointer
, type
, words
);
9928 input_line_pointer
= t
;
9929 *size
= prec
* sizeof (LITTLENUM_TYPE
);
9931 for (word
= words
+ prec
- 1; prec
--;)
9933 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
9934 lit
+= sizeof (LITTLENUM_TYPE
);
9939 /* Round up a section's size to the appropriate boundary. */
9941 md_section_align (seg
, size
)
9945 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9946 valueT mask
= ((valueT
) 1 << align
) - 1;
9948 return (size
+ mask
) & ~mask
;
9951 /* Handle ia64 specific semantics of the align directive. */
9954 ia64_md_do_align (n
, fill
, len
, max
)
9955 int n ATTRIBUTE_UNUSED
;
9956 const char *fill ATTRIBUTE_UNUSED
;
9957 int len ATTRIBUTE_UNUSED
;
9958 int max ATTRIBUTE_UNUSED
;
9960 if (subseg_text_p (now_seg
))
9961 ia64_flush_insns ();
9964 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9965 of an rs_align_code fragment. */
9968 ia64_handle_align (fragp
)
9971 /* Use mfi bundle of nops with no stop bits. */
9972 static const unsigned char be_nop
[]
9973 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9974 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9975 static const unsigned char le_nop
[]
9976 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9977 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9982 if (fragp
->fr_type
!= rs_align_code
)
9985 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
9986 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
9988 /* Make sure we are on a 16-byte boundary, in case someone has been
9989 putting data into a text section. */
9992 int fix
= bytes
& 15;
9996 fragp
->fr_fix
+= fix
;
9999 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10000 fragp
->fr_var
= 16;