1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright (C) 1998, 1999, 2000 Free Software Foundation.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "dwarf2dbg.h"
49 #include "opcode/ia64.h"
53 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
54 #define MIN(a,b) ((a) < (b) ? (a) : (b))
57 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
58 #define CURR_SLOT md.slot[md.curr_slot]
60 #define O_pseudo_fixup (O_max + 1)
64 SPECIAL_SECTION_BSS
= 0,
66 SPECIAL_SECTION_SDATA
,
67 SPECIAL_SECTION_RODATA
,
68 SPECIAL_SECTION_COMMENT
,
69 SPECIAL_SECTION_UNWIND
,
70 SPECIAL_SECTION_UNWIND_INFO
83 FUNC_LT_FPTR_RELATIVE
,
89 REG_FR
= (REG_GR
+ 128),
90 REG_AR
= (REG_FR
+ 128),
91 REG_CR
= (REG_AR
+ 128),
92 REG_P
= (REG_CR
+ 128),
93 REG_BR
= (REG_P
+ 64),
94 REG_IP
= (REG_BR
+ 8),
101 /* The following are pseudo-registers for use by gas only. */
113 /* The following pseudo-registers are used for unwind directives only: */
121 DYNREG_GR
= 0, /* dynamic general purpose register */
122 DYNREG_FR
, /* dynamic floating point register */
123 DYNREG_PR
, /* dynamic predicate register */
127 /* On the ia64, we can't know the address of a text label until the
128 instructions are packed into a bundle. To handle this, we keep
129 track of the list of labels that appear in front of each
133 struct label_fix
*next
;
137 extern int target_big_endian
;
139 /* Characters which always start a comment. */
140 const char comment_chars
[] = "";
142 /* Characters which start a comment at the beginning of a line. */
143 const char line_comment_chars
[] = "#";
145 /* Characters which may be used to separate multiple commands on a
147 const char line_separator_chars
[] = ";";
149 /* Characters which are used to indicate an exponent in a floating
151 const char EXP_CHARS
[] = "eE";
153 /* Characters which mean that a number is a floating point constant,
155 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
157 /* ia64-specific option processing: */
159 const char *md_shortopts
= "M:N:x::";
161 struct option md_longopts
[] =
163 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
164 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
165 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
166 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
169 size_t md_longopts_size
= sizeof (md_longopts
);
173 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
174 struct hash_control
*reg_hash
; /* register name hash table */
175 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
176 struct hash_control
*const_hash
; /* constant hash table */
177 struct hash_control
*entry_hash
; /* code entry hint hash table */
179 symbolS
*regsym
[REG_NUM
];
181 /* If X_op is != O_absent, the registername for the instruction's
182 qualifying predicate. If NULL, p0 is assumed for instructions
183 that are predicatable. */
190 explicit_mode
: 1, /* which mode we're in */
191 default_explicit_mode
: 1, /* which mode is the default */
192 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
195 /* Each bundle consists of up to three instructions. We keep
196 track of four most recent instructions so we can correctly set
197 the end_of_insn_group for the last instruction in a bundle. */
199 int num_slots_in_use
;
203 end_of_insn_group
: 1,
204 manual_bundling_on
: 1,
205 manual_bundling_off
: 1;
206 signed char user_template
; /* user-selected template, if any */
207 unsigned char qp_regno
; /* qualifying predicate */
208 /* This duplicates a good fraction of "struct fix" but we
209 can't use a "struct fix" instead since we can't call
210 fix_new_exp() until we know the address of the instruction. */
214 bfd_reloc_code_real_type code
;
215 enum ia64_opnd opnd
; /* type of operand in need of fix */
216 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
217 expressionS expr
; /* the value to be inserted */
219 fixup
[2]; /* at most two fixups per insn */
220 struct ia64_opcode
*idesc
;
221 struct label_fix
*label_fixups
;
222 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
225 unsigned int src_line
;
226 struct dwarf2_line_info debug_line
;
234 struct dynreg
*next
; /* next dynamic register */
236 unsigned short base
; /* the base register number */
237 unsigned short num_regs
; /* # of registers in this set */
239 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
241 flagword flags
; /* ELF-header flags */
244 unsigned hint
:1; /* is this hint currently valid? */
245 bfd_vma offset
; /* mem.offset offset */
246 bfd_vma base
; /* mem.offset base */
249 int path
; /* number of alt. entry points seen */
250 const char **entry_labels
; /* labels of all alternate paths in
251 the current DV-checking block. */
252 int maxpaths
; /* size currently allocated for
257 /* application registers: */
263 #define AR_BSPSTORE 18
278 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
279 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
280 {"ar.rsc", 16}, {"ar.bsp", 17},
281 {"ar.bspstore", 18}, {"ar.rnat", 19},
282 {"ar.fcr", 21}, {"ar.eflag", 24},
283 {"ar.csd", 25}, {"ar.ssd", 26},
284 {"ar.cflg", 27}, {"ar.fsr", 28},
285 {"ar.fir", 29}, {"ar.fdr", 30},
286 {"ar.ccv", 32}, {"ar.unat", 36},
287 {"ar.fpsr", 40}, {"ar.itc", 44},
288 {"ar.pfs", 64}, {"ar.lc", 65},
309 /* control registers: */
351 static const struct const_desc
358 /* PSR constant masks: */
361 {"psr.be", ((valueT
) 1) << 1},
362 {"psr.up", ((valueT
) 1) << 2},
363 {"psr.ac", ((valueT
) 1) << 3},
364 {"psr.mfl", ((valueT
) 1) << 4},
365 {"psr.mfh", ((valueT
) 1) << 5},
367 {"psr.ic", ((valueT
) 1) << 13},
368 {"psr.i", ((valueT
) 1) << 14},
369 {"psr.pk", ((valueT
) 1) << 15},
371 {"psr.dt", ((valueT
) 1) << 17},
372 {"psr.dfl", ((valueT
) 1) << 18},
373 {"psr.dfh", ((valueT
) 1) << 19},
374 {"psr.sp", ((valueT
) 1) << 20},
375 {"psr.pp", ((valueT
) 1) << 21},
376 {"psr.di", ((valueT
) 1) << 22},
377 {"psr.si", ((valueT
) 1) << 23},
378 {"psr.db", ((valueT
) 1) << 24},
379 {"psr.lp", ((valueT
) 1) << 25},
380 {"psr.tb", ((valueT
) 1) << 26},
381 {"psr.rt", ((valueT
) 1) << 27},
382 /* 28-31: reserved */
383 /* 32-33: cpl (current privilege level) */
384 {"psr.is", ((valueT
) 1) << 34},
385 {"psr.mc", ((valueT
) 1) << 35},
386 {"psr.it", ((valueT
) 1) << 36},
387 {"psr.id", ((valueT
) 1) << 37},
388 {"psr.da", ((valueT
) 1) << 38},
389 {"psr.dd", ((valueT
) 1) << 39},
390 {"psr.ss", ((valueT
) 1) << 40},
391 /* 41-42: ri (restart instruction) */
392 {"psr.ed", ((valueT
) 1) << 43},
393 {"psr.bn", ((valueT
) 1) << 44},
396 /* indirect register-sets/memory: */
405 { "CPUID", IND_CPUID
},
406 { "cpuid", IND_CPUID
},
418 /* Pseudo functions used to indicate relocation types (these functions
419 start with an at sign (@). */
441 /* reloc pseudo functions (these must come first!): */
442 { "fptr", PSEUDO_FUNC_RELOC
},
443 { "gprel", PSEUDO_FUNC_RELOC
},
444 { "ltoff", PSEUDO_FUNC_RELOC
},
445 { "pcrel", PSEUDO_FUNC_RELOC
},
446 { "pltoff", PSEUDO_FUNC_RELOC
},
447 { "secrel", PSEUDO_FUNC_RELOC
},
448 { "segrel", PSEUDO_FUNC_RELOC
},
449 { "ltv", PSEUDO_FUNC_RELOC
},
450 { 0, }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
452 /* mbtype4 constants: */
453 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
454 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
455 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
456 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
457 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
459 /* fclass constants: */
460 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
461 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
462 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
463 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
464 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
465 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
466 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
467 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
468 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
470 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
472 /* unwind-related constants: */
473 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
474 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
475 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
477 /* unwind-related registers: */
478 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
481 /* 41-bit nop opcodes (one per unit): */
482 static const bfd_vma nop
[IA64_NUM_UNITS
] =
484 0x0000000000LL
, /* NIL => break 0 */
485 0x0008000000LL
, /* I-unit nop */
486 0x0008000000LL
, /* M-unit nop */
487 0x4000000000LL
, /* B-unit nop */
488 0x0008000000LL
, /* F-unit nop */
489 0x0008000000LL
, /* L-"unit" nop */
490 0x0008000000LL
, /* X-unit nop */
493 /* Can't be `const' as it's passed to input routines (which have the
494 habit of setting temporary sentinels. */
495 static char special_section_name
[][20] =
497 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
498 {".IA_64.unwind"}, {".IA_64.unwind_info"}
501 /* The best template for a particular sequence of up to three
503 #define N IA64_NUM_TYPES
504 static unsigned char best_template
[N
][N
][N
];
507 /* Resource dependencies currently in effect */
509 int depind
; /* dependency index */
510 const struct ia64_dependency
*dependency
; /* actual dependency */
511 unsigned specific
:1, /* is this a specific bit/regno? */
512 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
513 int index
; /* specific regno/bit within dependency */
514 int note
; /* optional qualifying note (0 if none) */
518 int insn_srlz
; /* current insn serialization state */
519 int data_srlz
; /* current data serialization state */
520 int qp_regno
; /* qualifying predicate for this usage */
521 char *file
; /* what file marked this dependency */
522 int line
; /* what line marked this dependency */
523 struct mem_offset mem_offset
; /* optional memory offset hint */
524 int path
; /* corresponding code entry index */
526 static int regdepslen
= 0;
527 static int regdepstotlen
= 0;
528 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
529 static const char *dv_sem
[] = { "none", "implied", "impliedf",
530 "data", "instr", "specific", "other" };
532 /* Current state of PR mutexation */
533 static struct qpmutex
{
536 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
537 static int qp_mutexeslen
= 0;
538 static int qp_mutexestotlen
= 0;
539 static valueT qp_safe_across_calls
= 0;
541 /* Current state of PR implications */
542 static struct qp_imply
{
545 unsigned p2_branched
:1;
547 } *qp_implies
= NULL
;
548 static int qp_implieslen
= 0;
549 static int qp_impliestotlen
= 0;
551 /* Keep track of static GR values so that indirect register usage can
552 sometimes be tracked. */
557 } gr_values
[128] = {{ 1, 0 }};
559 /* These are the routines required to output the various types of
562 typedef struct unw_rec_list
{
564 unsigned long slot_number
;
565 struct unw_rec_list
*next
;
568 #define SLOT_NUM_NOT_SET -1
572 unsigned long next_slot_number
;
574 /* Maintain a list of unwind entries for the current function. */
578 /* Any unwind entires that should be attached to the current slot
579 that an insn is being constructed for. */
580 unw_rec_list
*current_entry
;
582 /* These are used to create the unwind table entry for this function. */
585 symbolS
*info
; /* pointer to unwind info */
586 symbolS
*personality_routine
;
588 /* TRUE if processing unwind directives in a prologue region. */
593 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
595 /* Forward delarations: */
596 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
597 static void set_section
PARAMS ((char *name
));
598 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
599 unsigned int, unsigned int));
600 static void dot_radix
PARAMS ((int));
601 static void dot_special_section
PARAMS ((int));
602 static void dot_proc
PARAMS ((int));
603 static void dot_fframe
PARAMS ((int));
604 static void dot_vframe
PARAMS ((int));
605 static void dot_vframesp
PARAMS ((int));
606 static void dot_vframepsp
PARAMS ((int));
607 static void dot_save
PARAMS ((int));
608 static void dot_restore
PARAMS ((int));
609 static void dot_restorereg
PARAMS ((int));
610 static void dot_restorereg_p
PARAMS ((int));
611 static void dot_handlerdata
PARAMS ((int));
612 static void dot_unwentry
PARAMS ((int));
613 static void dot_altrp
PARAMS ((int));
614 static void dot_savemem
PARAMS ((int));
615 static void dot_saveg
PARAMS ((int));
616 static void dot_savef
PARAMS ((int));
617 static void dot_saveb
PARAMS ((int));
618 static void dot_savegf
PARAMS ((int));
619 static void dot_spill
PARAMS ((int));
620 static void dot_spillreg
PARAMS ((int));
621 static void dot_spillmem
PARAMS ((int));
622 static void dot_spillreg_p
PARAMS ((int));
623 static void dot_spillmem_p
PARAMS ((int));
624 static void dot_label_state
PARAMS ((int));
625 static void dot_copy_state
PARAMS ((int));
626 static void dot_unwabi
PARAMS ((int));
627 static void dot_personality
PARAMS ((int));
628 static void dot_body
PARAMS ((int));
629 static void dot_prologue
PARAMS ((int));
630 static void dot_endp
PARAMS ((int));
631 static void dot_template
PARAMS ((int));
632 static void dot_regstk
PARAMS ((int));
633 static void dot_rot
PARAMS ((int));
634 static void dot_byteorder
PARAMS ((int));
635 static void dot_psr
PARAMS ((int));
636 static void dot_alias
PARAMS ((int));
637 static void dot_ln
PARAMS ((int));
638 static char *parse_section_name
PARAMS ((void));
639 static void dot_xdata
PARAMS ((int));
640 static void stmt_float_cons
PARAMS ((int));
641 static void stmt_cons_ua
PARAMS ((int));
642 static void dot_xfloat_cons
PARAMS ((int));
643 static void dot_xstringer
PARAMS ((int));
644 static void dot_xdata_ua
PARAMS ((int));
645 static void dot_xfloat_cons_ua
PARAMS ((int));
646 static void print_prmask
PARAMS ((valueT mask
));
647 static void dot_pred_rel
PARAMS ((int));
648 static void dot_reg_val
PARAMS ((int));
649 static void dot_dv_mode
PARAMS ((int));
650 static void dot_entry
PARAMS ((int));
651 static void dot_mem_offset
PARAMS ((int));
652 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
653 static symbolS
* declare_register
PARAMS ((const char *name
, int regnum
));
654 static void declare_register_set
PARAMS ((const char *, int, int));
655 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
656 static int operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
657 int index
, expressionS
*e
));
658 static int parse_operand
PARAMS ((expressionS
*e
));
659 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
660 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
661 static void emit_one_bundle
PARAMS ((void));
662 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
663 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
664 bfd_reloc_code_real_type r_type
));
665 static void insn_group_break
PARAMS ((int, int, int));
666 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
667 struct rsrc
*, int depind
, int path
));
668 static void add_qp_mutex
PARAMS((valueT mask
));
669 static void add_qp_imply
PARAMS((int p1
, int p2
));
670 static void clear_qp_branch_flag
PARAMS((valueT mask
));
671 static void clear_qp_mutex
PARAMS((valueT mask
));
672 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
673 static void clear_register_values
PARAMS ((void));
674 static void print_dependency
PARAMS ((const char *action
, int depind
));
675 static void instruction_serialization
PARAMS ((void));
676 static void data_serialization
PARAMS ((void));
677 static void remove_marked_resource
PARAMS ((struct rsrc
*));
678 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
679 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
680 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
681 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
682 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
683 struct ia64_opcode
*, int, struct rsrc
[], int, int));
684 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
685 static void check_dependencies
PARAMS((struct ia64_opcode
*));
686 static void mark_resources
PARAMS((struct ia64_opcode
*));
687 static void update_dependencies
PARAMS((struct ia64_opcode
*));
688 static void note_register_values
PARAMS((struct ia64_opcode
*));
689 static int qp_mutex
PARAMS ((int, int, int));
690 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
691 static void output_vbyte_mem
PARAMS ((int, char *, char *));
692 static void count_output
PARAMS ((int, char *, char *));
693 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
694 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
695 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
696 static void output_P1_format
PARAMS ((vbyte_func
, int));
697 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
698 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
699 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
700 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
701 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
702 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
703 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
704 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
705 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
706 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
707 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
708 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
709 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
710 static char format_ab_reg
PARAMS ((int, int));
711 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
713 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
714 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
716 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
717 static void free_list_records
PARAMS ((unw_rec_list
*));
718 static unw_rec_list
*output_prologue
PARAMS ((void));
719 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
720 static unw_rec_list
*output_body
PARAMS ((void));
721 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
722 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
723 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
724 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
725 static unw_rec_list
*output_rp_when
PARAMS ((void));
726 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
727 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
728 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
729 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
730 static unw_rec_list
*output_pfs_when
PARAMS ((void));
731 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
732 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
733 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
734 static unw_rec_list
*output_preds_when
PARAMS ((void));
735 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
736 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
737 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
738 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
739 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
740 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
741 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
742 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
743 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
744 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
745 static unw_rec_list
*output_unat_when
PARAMS ((void));
746 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
747 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
748 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
749 static unw_rec_list
*output_lc_when
PARAMS ((void));
750 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
751 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
752 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
753 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
754 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
755 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
756 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
757 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
758 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
759 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
760 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
761 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
762 static unw_rec_list
*output_bsp_when
PARAMS ((void));
763 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
764 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
765 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
766 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
767 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
768 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
769 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
770 static unw_rec_list
*output_rnat_when
PARAMS ((void));
771 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
772 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
773 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
774 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
775 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
776 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
777 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
778 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
779 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
780 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
782 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
784 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
786 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
787 unsigned int, unsigned int));
788 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
789 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
790 static int calc_record_size
PARAMS ((unw_rec_list
*));
791 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
792 static int count_bits
PARAMS ((unsigned long));
793 static unsigned long slot_index
PARAMS ((unsigned long, unsigned long));
794 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
795 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
796 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
797 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
798 static int generate_unwind_image
PARAMS ((void));
800 /* Determine if application register REGNUM resides in the integer
801 unit (as opposed to the memory unit). */
803 ar_is_in_integer_unit (reg
)
808 return (reg
== 64 /* pfs */
809 || reg
== 65 /* lc */
810 || reg
== 66 /* ec */
811 /* ??? ias accepts and puts these in the integer unit. */
812 || (reg
>= 112 && reg
<= 127));
815 /* Switch to section NAME and create section if necessary. It's
816 rather ugly that we have to manipulate input_line_pointer but I
817 don't see any other way to accomplish the same thing without
818 changing obj-elf.c (which may be the Right Thing, in the end). */
823 char *saved_input_line_pointer
;
825 saved_input_line_pointer
= input_line_pointer
;
826 input_line_pointer
= name
;
828 input_line_pointer
= saved_input_line_pointer
;
831 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
834 ia64_elf_section_flags (flags
, attr
, type
)
838 if (attr
& SHF_IA_64_SHORT
)
839 flags
|= SEC_SMALL_DATA
;
844 set_regstack (ins
, locs
, outs
, rots
)
845 unsigned int ins
, locs
, outs
, rots
;
847 unsigned int sof
; /* size of frame */
849 sof
= ins
+ locs
+ outs
;
852 as_bad ("Size of frame exceeds maximum of 96 registers");
857 as_warn ("Size of rotating registers exceeds frame size");
860 md
.in
.base
= REG_GR
+ 32;
861 md
.loc
.base
= md
.in
.base
+ ins
;
862 md
.out
.base
= md
.loc
.base
+ locs
;
864 md
.in
.num_regs
= ins
;
865 md
.loc
.num_regs
= locs
;
866 md
.out
.num_regs
= outs
;
867 md
.rot
.num_regs
= rots
;
874 struct label_fix
*lfix
;
876 subsegT saved_subseg
;
878 if (!md
.last_text_seg
)
882 saved_subseg
= now_subseg
;
884 subseg_set (md
.last_text_seg
, 0);
886 while (md
.num_slots_in_use
> 0)
887 emit_one_bundle (); /* force out queued instructions */
889 /* In case there are labels following the last instruction, resolve
891 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
893 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
894 symbol_set_frag (lfix
->sym
, frag_now
);
896 CURR_SLOT
.label_fixups
= 0;
898 subseg_set (saved_seg
, saved_subseg
);
902 ia64_do_align (nbytes
)
905 char *saved_input_line_pointer
= input_line_pointer
;
907 input_line_pointer
= "";
908 s_align_bytes (nbytes
);
909 input_line_pointer
= saved_input_line_pointer
;
913 ia64_cons_align (nbytes
)
918 char *saved_input_line_pointer
= input_line_pointer
;
919 input_line_pointer
= "";
920 s_align_bytes (nbytes
);
921 input_line_pointer
= saved_input_line_pointer
;
925 /* Output COUNT bytes to a memory location. */
926 static unsigned char *vbyte_mem_ptr
= NULL
;
929 output_vbyte_mem (count
, ptr
, comment
)
935 if (vbyte_mem_ptr
== NULL
)
940 for (x
= 0; x
< count
; x
++)
941 *(vbyte_mem_ptr
++) = ptr
[x
];
944 /* Count the number of bytes required for records. */
945 static int vbyte_count
= 0;
947 count_output (count
, ptr
, comment
)
952 vbyte_count
+= count
;
956 output_R1_format (f
, rtype
, rlen
)
958 unw_record_type rtype
;
965 output_R3_format (f
, rtype
, rlen
);
971 else if (rtype
!= prologue
)
972 as_bad ("record type is not valid");
974 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
975 (*f
) (1, &byte
, NULL
);
979 output_R2_format (f
, mask
, grsave
, rlen
)
986 mask
= (mask
& 0x0f);
987 grsave
= (grsave
& 0x7f);
989 bytes
[0] = (UNW_R2
| (mask
>> 1));
990 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
991 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
992 (*f
) (count
, bytes
, NULL
);
996 output_R3_format (f
, rtype
, rlen
)
998 unw_record_type rtype
;
1005 output_R1_format (f
, rtype
, rlen
);
1011 else if (rtype
!= prologue
)
1012 as_bad ("record type is not valid");
1013 bytes
[0] = (UNW_R3
| r
);
1014 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1015 (*f
) (count
+ 1, bytes
, NULL
);
1019 output_P1_format (f
, brmask
)
1024 byte
= UNW_P1
| (brmask
& 0x1f);
1025 (*f
) (1, &byte
, NULL
);
1029 output_P2_format (f
, brmask
, gr
)
1035 brmask
= (brmask
& 0x1f);
1036 bytes
[0] = UNW_P2
| (brmask
>> 1);
1037 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1038 (*f
) (2, bytes
, NULL
);
1042 output_P3_format (f
, rtype
, reg
)
1044 unw_record_type rtype
;
1089 as_bad ("Invalid record type for P3 format.");
1091 bytes
[0] = (UNW_P3
| (r
>> 1));
1092 bytes
[1] = (((r
& 1) << 7) | reg
);
1093 (*f
) (2, bytes
, NULL
);
1098 output_P4_format (f
, imask
, imask_size
)
1100 unsigned char *imask
;
1101 unsigned long imask_size
;
1104 (*f
) (imask_size
, imask
, NULL
);
1108 output_P5_format (f
, grmask
, frmask
)
1111 unsigned long frmask
;
1114 grmask
= (grmask
& 0x0f);
1117 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1118 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1119 bytes
[3] = (frmask
& 0x000000ff);
1120 (*f
) (4, bytes
, NULL
);
1124 output_P6_format (f
, rtype
, rmask
)
1126 unw_record_type rtype
;
1132 if (rtype
== gr_mem
)
1134 else if (rtype
!= fr_mem
)
1135 as_bad ("Invalid record type for format P6");
1136 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1137 (*f
) (1, &byte
, NULL
);
1141 output_P7_format (f
, rtype
, w1
, w2
)
1143 unw_record_type rtype
;
1150 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1155 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1205 bytes
[0] = (UNW_P7
| r
);
1206 (*f
) (count
, bytes
, NULL
);
1210 output_P8_format (f
, rtype
, t
)
1212 unw_record_type rtype
;
1251 case bspstore_psprel
:
1254 case bspstore_sprel
:
1266 case priunat_when_gr
:
1269 case priunat_psprel
:
1275 case priunat_when_mem
:
1282 count
+= output_leb128 (bytes
+ 2, t
, 0);
1283 (*f
) (count
, bytes
, NULL
);
1287 output_P9_format (f
, grmask
, gr
)
1294 bytes
[1] = (grmask
& 0x0f);
1295 bytes
[2] = (gr
& 0x7f);
1296 (*f
) (3, bytes
, NULL
);
1300 output_P10_format (f
, abi
, context
)
1307 bytes
[1] = (abi
& 0xff);
1308 bytes
[2] = (context
& 0xff);
1309 (*f
) (3, bytes
, NULL
);
1313 output_B1_format (f
, rtype
, label
)
1315 unw_record_type rtype
;
1316 unsigned long label
;
1322 output_B4_format (f
, rtype
, label
);
1325 if (rtype
== copy_state
)
1327 else if (rtype
!= label_state
)
1328 as_bad ("Invalid record type for format B1");
1330 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1331 (*f
) (1, &byte
, NULL
);
1335 output_B2_format (f
, ecount
, t
)
1337 unsigned long ecount
;
1344 output_B3_format (f
, ecount
, t
);
1347 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1348 count
+= output_leb128 (bytes
+ 1, t
, 0);
1349 (*f
) (count
, bytes
, NULL
);
1353 output_B3_format (f
, ecount
, t
)
1355 unsigned long ecount
;
1362 output_B2_format (f
, ecount
, t
);
1366 count
+= output_leb128 (bytes
+ 1, t
, 0);
1367 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1368 (*f
) (count
, bytes
, NULL
);
1372 output_B4_format (f
, rtype
, label
)
1374 unw_record_type rtype
;
1375 unsigned long label
;
1382 output_B1_format (f
, rtype
, label
);
1386 if (rtype
== copy_state
)
1388 else if (rtype
!= label_state
)
1389 as_bad ("Invalid record type for format B1");
1391 bytes
[0] = (UNW_B4
| (r
<< 3));
1392 count
+= output_leb128 (bytes
+ 1, label
, 0);
1393 (*f
) (count
, bytes
, NULL
);
1397 format_ab_reg (ab
, reg
)
1404 ret
= (ab
<< 5) | reg
;
1409 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1411 unw_record_type rtype
;
1421 if (rtype
== spill_sprel
)
1423 else if (rtype
!= spill_psprel
)
1424 as_bad ("Invalid record type for format X1");
1425 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1426 count
+= output_leb128 (bytes
+ 2, t
, 0);
1427 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1428 (*f
) (count
, bytes
, NULL
);
1432 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1441 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1442 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1443 count
+= output_leb128 (bytes
+ 3, t
, 0);
1444 (*f
) (count
, bytes
, NULL
);
1448 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1450 unw_record_type rtype
;
1461 if (rtype
== spill_sprel_p
)
1463 else if (rtype
!= spill_psprel_p
)
1464 as_bad ("Invalid record type for format X3");
1465 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1466 bytes
[2] = format_ab_reg (ab
, reg
);
1467 count
+= output_leb128 (bytes
+ 3, t
, 0);
1468 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1469 (*f
) (count
, bytes
, NULL
);
1473 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1483 bytes
[1] = (qp
& 0x3f);
1484 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1485 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1486 count
+= output_leb128 (bytes
+ 4, t
, 0);
1487 (*f
) (count
, bytes
, NULL
);
1490 /* This function allocates a record list structure, and initializes fields. */
1491 static unw_rec_list
*
1492 alloc_record (unw_record_type t
)
1495 ptr
= xmalloc (sizeof (*ptr
));
1497 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1502 /* This function frees an entire list of record structures. */
1504 free_list_records (unw_rec_list
*first
)
1507 for (ptr
= first
; ptr
!= NULL
; )
1509 unw_rec_list
*tmp
= ptr
;
1511 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1512 && tmp
->r
.record
.r
.mask
.i
)
1513 free (tmp
->r
.record
.r
.mask
.i
);
1520 static unw_rec_list
*
1523 unw_rec_list
*ptr
= alloc_record (prologue
);
1524 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1528 static unw_rec_list
*
1529 output_prologue_gr (saved_mask
, reg
)
1530 unsigned int saved_mask
;
1533 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1534 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1535 ptr
->r
.record
.r
.grmask
= saved_mask
;
1536 ptr
->r
.record
.r
.grsave
= reg
;
1540 static unw_rec_list
*
1543 unw_rec_list
*ptr
= alloc_record (body
);
1547 static unw_rec_list
*
1548 output_mem_stack_f (size
)
1551 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1552 ptr
->r
.record
.p
.size
= size
;
1556 static unw_rec_list
*
1557 output_mem_stack_v ()
1559 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1563 static unw_rec_list
*
1567 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1568 ptr
->r
.record
.p
.gr
= gr
;
1572 static unw_rec_list
*
1573 output_psp_sprel (offset
)
1574 unsigned int offset
;
1576 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1577 ptr
->r
.record
.p
.spoff
= offset
/4;
1581 static unw_rec_list
*
1584 unw_rec_list
*ptr
= alloc_record (rp_when
);
1588 static unw_rec_list
*
1592 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1593 ptr
->r
.record
.p
.gr
= gr
;
1597 static unw_rec_list
*
1601 unw_rec_list
*ptr
= alloc_record (rp_br
);
1602 ptr
->r
.record
.p
.br
= br
;
1606 static unw_rec_list
*
1607 output_rp_psprel (offset
)
1608 unsigned int offset
;
1610 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1611 ptr
->r
.record
.p
.pspoff
= offset
/4;
1615 static unw_rec_list
*
1616 output_rp_sprel (offset
)
1617 unsigned int offset
;
1619 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1620 ptr
->r
.record
.p
.spoff
= offset
/4;
1624 static unw_rec_list
*
1627 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1631 static unw_rec_list
*
1635 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1636 ptr
->r
.record
.p
.gr
= gr
;
1640 static unw_rec_list
*
1641 output_pfs_psprel (offset
)
1642 unsigned int offset
;
1644 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1645 ptr
->r
.record
.p
.pspoff
= offset
/4;
1649 static unw_rec_list
*
1650 output_pfs_sprel (offset
)
1651 unsigned int offset
;
1653 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1654 ptr
->r
.record
.p
.spoff
= offset
/4;
1658 static unw_rec_list
*
1659 output_preds_when ()
1661 unw_rec_list
*ptr
= alloc_record (preds_when
);
1665 static unw_rec_list
*
1666 output_preds_gr (gr
)
1669 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1670 ptr
->r
.record
.p
.gr
= gr
;
1674 static unw_rec_list
*
1675 output_preds_psprel (offset
)
1676 unsigned int offset
;
1678 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1679 ptr
->r
.record
.p
.pspoff
= offset
/4;
1683 static unw_rec_list
*
1684 output_preds_sprel (offset
)
1685 unsigned int offset
;
1687 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1688 ptr
->r
.record
.p
.spoff
= offset
/4;
1692 static unw_rec_list
*
1693 output_fr_mem (mask
)
1696 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1697 ptr
->r
.record
.p
.rmask
= mask
;
1701 static unw_rec_list
*
1702 output_frgr_mem (gr_mask
, fr_mask
)
1703 unsigned int gr_mask
;
1704 unsigned int fr_mask
;
1706 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1707 ptr
->r
.record
.p
.grmask
= gr_mask
;
1708 ptr
->r
.record
.p
.frmask
= fr_mask
;
1712 static unw_rec_list
*
1713 output_gr_gr (mask
, reg
)
1717 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1718 ptr
->r
.record
.p
.grmask
= mask
;
1719 ptr
->r
.record
.p
.gr
= reg
;
1723 static unw_rec_list
*
1724 output_gr_mem (mask
)
1727 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1728 ptr
->r
.record
.p
.rmask
= mask
;
1732 static unw_rec_list
*
1733 output_br_mem (unsigned int mask
)
1735 unw_rec_list
*ptr
= alloc_record (br_mem
);
1736 ptr
->r
.record
.p
.brmask
= mask
;
1740 static unw_rec_list
*
1741 output_br_gr (save_mask
, reg
)
1742 unsigned int save_mask
;
1745 unw_rec_list
*ptr
= alloc_record (br_gr
);
1746 ptr
->r
.record
.p
.brmask
= save_mask
;
1747 ptr
->r
.record
.p
.gr
= reg
;
1751 static unw_rec_list
*
1752 output_spill_base (offset
)
1753 unsigned int offset
;
1755 unw_rec_list
*ptr
= alloc_record (spill_base
);
1756 ptr
->r
.record
.p
.pspoff
= offset
/4;
1760 static unw_rec_list
*
1763 unw_rec_list
*ptr
= alloc_record (unat_when
);
1767 static unw_rec_list
*
1771 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1772 ptr
->r
.record
.p
.gr
= gr
;
1776 static unw_rec_list
*
1777 output_unat_psprel (offset
)
1778 unsigned int offset
;
1780 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1781 ptr
->r
.record
.p
.pspoff
= offset
/4;
1785 static unw_rec_list
*
1786 output_unat_sprel (offset
)
1787 unsigned int offset
;
1789 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1790 ptr
->r
.record
.p
.spoff
= offset
/4;
1794 static unw_rec_list
*
1797 unw_rec_list
*ptr
= alloc_record (lc_when
);
1801 static unw_rec_list
*
1805 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1806 ptr
->r
.record
.p
.gr
= gr
;
1810 static unw_rec_list
*
1811 output_lc_psprel (offset
)
1812 unsigned int offset
;
1814 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1815 ptr
->r
.record
.p
.pspoff
= offset
/4;
1819 static unw_rec_list
*
1820 output_lc_sprel (offset
)
1821 unsigned int offset
;
1823 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
1824 ptr
->r
.record
.p
.spoff
= offset
/4;
1828 static unw_rec_list
*
1831 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
1835 static unw_rec_list
*
1839 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
1840 ptr
->r
.record
.p
.gr
= gr
;
1844 static unw_rec_list
*
1845 output_fpsr_psprel (offset
)
1846 unsigned int offset
;
1848 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
1849 ptr
->r
.record
.p
.pspoff
= offset
/4;
1853 static unw_rec_list
*
1854 output_fpsr_sprel (offset
)
1855 unsigned int offset
;
1857 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
1858 ptr
->r
.record
.p
.spoff
= offset
/4;
1862 static unw_rec_list
*
1863 output_priunat_when_gr ()
1865 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
1869 static unw_rec_list
*
1870 output_priunat_when_mem ()
1872 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
1876 static unw_rec_list
*
1877 output_priunat_gr (gr
)
1880 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
1881 ptr
->r
.record
.p
.gr
= gr
;
1885 static unw_rec_list
*
1886 output_priunat_psprel (offset
)
1887 unsigned int offset
;
1889 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
1890 ptr
->r
.record
.p
.pspoff
= offset
/4;
1894 static unw_rec_list
*
1895 output_priunat_sprel (offset
)
1896 unsigned int offset
;
1898 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
1899 ptr
->r
.record
.p
.spoff
= offset
/4;
1903 static unw_rec_list
*
1906 unw_rec_list
*ptr
= alloc_record (bsp_when
);
1910 static unw_rec_list
*
1914 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
1915 ptr
->r
.record
.p
.gr
= gr
;
1919 static unw_rec_list
*
1920 output_bsp_psprel (offset
)
1921 unsigned int offset
;
1923 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
1924 ptr
->r
.record
.p
.pspoff
= offset
/4;
1928 static unw_rec_list
*
1929 output_bsp_sprel (offset
)
1930 unsigned int offset
;
1932 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
1933 ptr
->r
.record
.p
.spoff
= offset
/4;
1937 static unw_rec_list
*
1938 output_bspstore_when ()
1940 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
1944 static unw_rec_list
*
1945 output_bspstore_gr (gr
)
1948 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
1949 ptr
->r
.record
.p
.gr
= gr
;
1953 static unw_rec_list
*
1954 output_bspstore_psprel (offset
)
1955 unsigned int offset
;
1957 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
1958 ptr
->r
.record
.p
.pspoff
= offset
/4;
1962 static unw_rec_list
*
1963 output_bspstore_sprel (offset
)
1964 unsigned int offset
;
1966 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
1967 ptr
->r
.record
.p
.spoff
= offset
/4;
1971 static unw_rec_list
*
1974 unw_rec_list
*ptr
= alloc_record (rnat_when
);
1978 static unw_rec_list
*
1982 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
1983 ptr
->r
.record
.p
.gr
= gr
;
1987 static unw_rec_list
*
1988 output_rnat_psprel (offset
)
1989 unsigned int offset
;
1991 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
1992 ptr
->r
.record
.p
.pspoff
= offset
/4;
1996 static unw_rec_list
*
1997 output_rnat_sprel (offset
)
1998 unsigned int offset
;
2000 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2001 ptr
->r
.record
.p
.spoff
= offset
/4;
2005 static unw_rec_list
*
2006 output_unwabi (abi
, context
)
2008 unsigned long context
;
2010 unw_rec_list
*ptr
= alloc_record (unwabi
);
2011 ptr
->r
.record
.p
.abi
= abi
;
2012 ptr
->r
.record
.p
.context
= context
;
2016 static unw_rec_list
*
2017 output_epilogue (unsigned long ecount
)
2019 unw_rec_list
*ptr
= alloc_record (epilogue
);
2020 ptr
->r
.record
.b
.ecount
= ecount
;
2024 static unw_rec_list
*
2025 output_label_state (unsigned long label
)
2027 unw_rec_list
*ptr
= alloc_record (label_state
);
2028 ptr
->r
.record
.b
.label
= label
;
2032 static unw_rec_list
*
2033 output_copy_state (unsigned long label
)
2035 unw_rec_list
*ptr
= alloc_record (copy_state
);
2036 ptr
->r
.record
.b
.label
= label
;
2040 static unw_rec_list
*
2041 output_spill_psprel (ab
, reg
, offset
)
2044 unsigned int offset
;
2046 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2047 ptr
->r
.record
.x
.ab
= ab
;
2048 ptr
->r
.record
.x
.reg
= reg
;
2049 ptr
->r
.record
.x
.pspoff
= offset
/4;
2053 static unw_rec_list
*
2054 output_spill_sprel (ab
, reg
, offset
)
2057 unsigned int offset
;
2059 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2060 ptr
->r
.record
.x
.ab
= ab
;
2061 ptr
->r
.record
.x
.reg
= reg
;
2062 ptr
->r
.record
.x
.spoff
= offset
/4;
2066 static unw_rec_list
*
2067 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2070 unsigned int offset
;
2071 unsigned int predicate
;
2073 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2074 ptr
->r
.record
.x
.ab
= ab
;
2075 ptr
->r
.record
.x
.reg
= reg
;
2076 ptr
->r
.record
.x
.pspoff
= offset
/4;
2077 ptr
->r
.record
.x
.qp
= predicate
;
2081 static unw_rec_list
*
2082 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2085 unsigned int offset
;
2086 unsigned int predicate
;
2088 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2089 ptr
->r
.record
.x
.ab
= ab
;
2090 ptr
->r
.record
.x
.reg
= reg
;
2091 ptr
->r
.record
.x
.spoff
= offset
/4;
2092 ptr
->r
.record
.x
.qp
= predicate
;
2096 static unw_rec_list
*
2097 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2100 unsigned int targ_reg
;
2103 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2104 ptr
->r
.record
.x
.ab
= ab
;
2105 ptr
->r
.record
.x
.reg
= reg
;
2106 ptr
->r
.record
.x
.treg
= targ_reg
;
2107 ptr
->r
.record
.x
.xy
= xy
;
2111 static unw_rec_list
*
2112 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2115 unsigned int targ_reg
;
2117 unsigned int predicate
;
2119 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2120 ptr
->r
.record
.x
.ab
= ab
;
2121 ptr
->r
.record
.x
.reg
= reg
;
2122 ptr
->r
.record
.x
.treg
= targ_reg
;
2123 ptr
->r
.record
.x
.xy
= xy
;
2124 ptr
->r
.record
.x
.qp
= predicate
;
2128 /* Given a unw_rec_list process the correct format with the
2129 specified function. */
2131 process_one_record (ptr
, f
)
2135 unsigned long fr_mask
, gr_mask
;
2137 switch (ptr
->r
.type
)
2143 /* these are taken care of by prologue/prologue_gr */
2148 if (ptr
->r
.type
== prologue_gr
)
2149 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2150 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2152 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2154 /* output descriptor(s) for union of register spills (if any): */
2155 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2156 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2159 if ((fr_mask
& ~0xfUL
) == 0)
2160 output_P6_format (f
, fr_mem
, fr_mask
);
2163 output_P5_format (f
, gr_mask
, fr_mask
);
2168 output_P6_format (f
, gr_mem
, gr_mask
);
2169 if (ptr
->r
.record
.r
.mask
.br_mem
)
2170 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2172 /* output imask descriptor if necessary: */
2173 if (ptr
->r
.record
.r
.mask
.i
)
2174 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2175 ptr
->r
.record
.r
.imask_size
);
2179 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2183 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2184 ptr
->r
.record
.p
.size
);
2197 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2200 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2203 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2211 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2220 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2230 case bspstore_sprel
:
2232 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2235 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2238 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2241 as_bad ("spill_mask record unimplemented.");
2243 case priunat_when_gr
:
2244 case priunat_when_mem
:
2248 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2250 case priunat_psprel
:
2252 case bspstore_psprel
:
2254 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2257 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2260 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2264 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2267 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2268 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2269 ptr
->r
.record
.x
.pspoff
);
2272 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2273 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2274 ptr
->r
.record
.x
.spoff
);
2277 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2278 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2279 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2281 case spill_psprel_p
:
2282 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2283 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2284 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2287 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2288 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2289 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2292 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2293 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2294 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2298 as_bad ("record_type_not_valid");
2303 /* Given a unw_rec_list list, process all the records with
2304 the specified function. */
2306 process_unw_records (list
, f
)
2311 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2312 process_one_record (ptr
, f
);
2315 /* Determine the size of a record list in bytes. */
2317 calc_record_size (list
)
2321 process_unw_records (list
, count_output
);
2325 /* Update IMASK bitmask to reflect the fact that one or more registers
2326 of type TYPE are saved starting at instruction with index T. If N
2327 bits are set in REGMASK, it is assumed that instructions T through
2328 T+N-1 save these registers.
2332 1: instruction saves next fp reg
2333 2: instruction saves next general reg
2334 3: instruction saves next branch reg */
2336 set_imask (region
, regmask
, t
, type
)
2337 unw_rec_list
*region
;
2338 unsigned long regmask
;
2342 unsigned char *imask
;
2343 unsigned long imask_size
;
2347 imask
= region
->r
.record
.r
.mask
.i
;
2348 imask_size
= region
->r
.record
.r
.imask_size
;
2351 imask_size
= (region
->r
.record
.r
.rlen
*2 + 7)/8 + 1;
2352 imask
= xmalloc (imask_size
);
2353 memset (imask
, 0, imask_size
);
2355 region
->r
.record
.r
.imask_size
= imask_size
;
2356 region
->r
.record
.r
.mask
.i
= imask
;
2363 if (i
>= imask_size
)
2365 as_bad ("Ignoring attempt to spill beyond end of region");
2369 imask
[i
] |= (type
& 0x3) << pos
;
2371 regmask
&= (regmask
- 1);
2382 count_bits (unsigned long mask
)
2395 slot_index (unsigned long slot_addr
, unsigned long first_addr
)
2397 return (3*((slot_addr
>> 4) - (first_addr
>> 4))
2398 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2401 /* Given a complete record list, process any records which have
2402 unresolved fields, (ie length counts for a prologue). After
2403 this has been run, all neccessary information should be available
2404 within each record to generate an image. */
2406 fixup_unw_records (list
)
2409 unw_rec_list
*ptr
, *region
= 0;
2410 unsigned long first_addr
= 0, rlen
= 0, t
;
2412 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2414 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2415 as_bad (" Insn slot not set in unwind record.");
2416 t
= slot_index (ptr
->slot_number
, first_addr
);
2417 switch (ptr
->r
.type
)
2424 int size
, dir_len
= 0;
2425 unsigned long last_addr
;
2427 first_addr
= ptr
->slot_number
;
2428 ptr
->slot_number
= 0;
2429 /* Find either the next body/prologue start, or the end of
2430 the list, and determine the size of the region. */
2431 last_addr
= unwind
.next_slot_number
;
2432 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2433 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2434 || last
->r
.type
== body
)
2436 last_addr
= last
->slot_number
;
2439 else if (!last
->next
)
2441 /* In the absence of an explicit .body directive,
2442 the prologue ends after the last instruction
2443 covered by an unwind directive. */
2444 if (ptr
->r
.type
!= body
)
2446 last_addr
= last
->slot_number
;
2447 switch (last
->r
.type
)
2450 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2451 + count_bits (last
->r
.record
.p
.grmask
));
2455 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2459 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2462 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2471 size
= slot_index (last_addr
, first_addr
) + dir_len
;
2472 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2477 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2488 case priunat_when_gr
:
2489 case priunat_when_mem
:
2493 ptr
->r
.record
.p
.t
= t
;
2501 case spill_psprel_p
:
2502 ptr
->r
.record
.x
.t
= t
;
2508 as_bad ("frgr_mem record before region record!\n");
2511 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2512 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2513 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2514 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2519 as_bad ("fr_mem record before region record!\n");
2522 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2523 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2528 as_bad ("gr_mem record before region record!\n");
2531 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2532 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2537 as_bad ("br_mem record before region record!\n");
2540 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2541 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2547 as_bad ("gr_gr record before region record!\n");
2550 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2555 as_bad ("br_gr record before region record!\n");
2558 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2567 /* Generate an unwind image from a record list. Returns the number of
2568 bytes in the resulting image. The memory image itselof is returned
2569 in the 'ptr' parameter. */
2571 output_unw_records (list
, ptr
)
2575 int size
, x
, extra
= 0;
2578 fixup_unw_records (list
);
2579 size
= calc_record_size (list
);
2581 /* pad to 8 byte boundry. */
2585 /* Add 8 for the header + 8 more bytes for the personality offset. */
2586 mem
= xmalloc (size
+ extra
+ 16);
2588 vbyte_mem_ptr
= mem
+ 8;
2589 /* Clear the padding area and personality. */
2590 memset (mem
+ 8 + size
, 0 , extra
+ 8);
2591 /* Initialize the header area. */
2592 md_number_to_chars (mem
, ( ((bfd_vma
) 1 << 48) /* version */
2593 | ((bfd_vma
) 3 << 32) /* U & E handler flags */
2594 | ((size
+ extra
) / 8)), /* length (dwords) */
2597 process_unw_records (list
, output_vbyte_mem
);
2600 return size
+ extra
+ 16;
2604 convert_expr_to_ab_reg (e
, ab
, regp
)
2611 if (e
->X_op
!= O_register
)
2614 reg
= e
->X_add_number
;
2615 if (reg
>= REG_GR
+ 4 && reg
<= REG_GR
+ 7)
2618 *regp
= reg
- REG_GR
;
2620 else if ((reg
>= REG_FR
+ 2 && reg
<= REG_FR
+ 5)
2621 || (reg
>= REG_FR
+ 16 && reg
<= REG_FR
+ 31))
2624 *regp
= reg
- REG_FR
;
2626 else if (reg
>= REG_BR
+ 1 && reg
<= REG_BR
+ 5)
2629 *regp
= reg
- REG_BR
;
2636 case REG_PR
: *regp
= 0; break;
2637 case REG_PSP
: *regp
= 1; break;
2638 case REG_PRIUNAT
: *regp
= 2; break;
2639 case REG_BR
+ 0: *regp
= 3; break;
2640 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2641 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2642 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2643 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2644 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2645 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2646 case REG_AR
+ AR_LC
: *regp
= 10; break;
2656 convert_expr_to_xy_reg (e
, xy
, regp
)
2663 if (e
->X_op
!= O_register
)
2666 reg
= e
->X_add_number
;
2668 if (reg
>= REG_GR
&& reg
<= REG_GR
+ 127)
2671 *regp
= reg
- REG_GR
;
2673 else if (reg
>= REG_FR
&& reg
<= REG_FR
+ 127)
2676 *regp
= reg
- REG_FR
;
2678 else if (reg
>= REG_BR
&& reg
<= REG_BR
+ 7)
2681 *regp
= reg
- REG_BR
;
2695 radix
= *input_line_pointer
++;
2697 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2699 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2700 ignore_rest_of_line ();
2705 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2707 dot_special_section (which
)
2710 set_section ((char *) special_section_name
[which
]);
2714 add_unwind_entry (ptr
)
2718 unwind
.tail
->next
= ptr
;
2723 /* The current entry can in fact be a chain of unwind entries. */
2724 if (unwind
.current_entry
== NULL
)
2725 unwind
.current_entry
= ptr
;
2736 if (e
.X_op
!= O_constant
)
2737 as_bad ("Operand to .fframe must be a constant");
2739 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
2750 reg
= e
.X_add_number
- REG_GR
;
2751 if (e
.X_op
== O_register
&& reg
< 128)
2753 add_unwind_entry (output_mem_stack_v ());
2754 if (! (unwind
.prologue_mask
& 2))
2755 add_unwind_entry (output_psp_gr (reg
));
2758 as_bad ("First operand to .vframe must be a general register");
2762 dot_vframesp (dummy
)
2768 if (e
.X_op
== O_constant
)
2770 add_unwind_entry (output_mem_stack_v ());
2771 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2774 as_bad ("First operand to .vframesp must be a general register");
2778 dot_vframepsp (dummy
)
2784 if (e
.X_op
== O_constant
)
2786 add_unwind_entry (output_mem_stack_v ());
2787 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
2790 as_bad ("First operand to .vframepsp must be a general register");
2801 sep
= parse_operand (&e1
);
2803 as_bad ("No second operand to .save");
2804 sep
= parse_operand (&e2
);
2806 reg1
= e1
.X_add_number
;
2807 reg2
= e2
.X_add_number
- REG_GR
;
2809 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
2810 if (e1
.X_op
== O_register
)
2812 if (e2
.X_op
== O_register
&& reg2
>=0 && reg2
< 128)
2816 case REG_AR
+ AR_BSP
:
2817 add_unwind_entry (output_bsp_when ());
2818 add_unwind_entry (output_bsp_gr (reg2
));
2820 case REG_AR
+ AR_BSPSTORE
:
2821 add_unwind_entry (output_bspstore_when ());
2822 add_unwind_entry (output_bspstore_gr (reg2
));
2824 case REG_AR
+ AR_RNAT
:
2825 add_unwind_entry (output_rnat_when ());
2826 add_unwind_entry (output_rnat_gr (reg2
));
2828 case REG_AR
+AR_UNAT
:
2829 add_unwind_entry (output_unat_when ());
2830 add_unwind_entry (output_unat_gr (reg2
));
2832 case REG_AR
+AR_FPSR
:
2833 add_unwind_entry (output_fpsr_when ());
2834 add_unwind_entry (output_fpsr_gr (reg2
));
2837 add_unwind_entry (output_pfs_when ());
2838 if (! (unwind
.prologue_mask
& 4))
2839 add_unwind_entry (output_pfs_gr (reg2
));
2842 add_unwind_entry (output_lc_when ());
2843 add_unwind_entry (output_lc_gr (reg2
));
2846 add_unwind_entry (output_rp_when ());
2847 if (! (unwind
.prologue_mask
& 8))
2848 add_unwind_entry (output_rp_gr (reg2
));
2851 add_unwind_entry (output_preds_when ());
2852 if (! (unwind
.prologue_mask
& 1))
2853 add_unwind_entry (output_preds_gr (reg2
));
2856 add_unwind_entry (output_priunat_when_gr ());
2857 add_unwind_entry (output_priunat_gr (reg2
));
2860 as_bad ("First operand not a valid register");
2864 as_bad (" Second operand not a valid register");
2867 as_bad ("First operand not a register");
2875 unsigned long ecount
= 0;
2878 sep
= parse_operand (&e1
);
2879 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
2881 as_bad ("First operand to .restore must be stack pointer (sp)");
2887 parse_operand (&e2
);
2888 if (e1
.X_op
!= O_constant
)
2890 as_bad ("Second operand to .restore must be constant");
2895 add_unwind_entry (output_epilogue (ecount
));
2899 dot_restorereg (dummy
)
2902 unsigned int ab
, reg
;
2907 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
2909 as_bad ("First operand to .restorereg must be a preserved register");
2912 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
2916 dot_restorereg_p (dummy
)
2919 unsigned int qp
, ab
, reg
;
2923 sep
= parse_operand (&e1
);
2926 as_bad ("No second operand to .restorereg.p");
2930 parse_operand (&e2
);
2932 qp
= e1
.X_add_number
- REG_P
;
2933 if (e1
.X_op
!= O_register
|| qp
> 63)
2935 as_bad ("First operand to .restorereg.p must be a predicate");
2939 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
2941 as_bad ("Second operand to .restorereg.p must be a preserved register");
2944 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
2948 generate_unwind_image ()
2951 unsigned char *unw_rec
;
2953 /* Force out pending instructions, to make sure all unwind records have
2954 a valid slot_number field. */
2955 ia64_flush_insns ();
2957 /* Generate the unwind record. */
2958 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
2960 as_bad ("Unwind record is not a multiple of 8 bytes.");
2962 /* If there are unwind records, switch sections, and output the info. */
2965 unsigned char *where
;
2967 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND_INFO
]);
2969 /* Set expression which points to start of unwind descriptor area. */
2970 unwind
.info
= expr_build_dot ();
2972 where
= (unsigned char *)frag_more (size
);
2974 /* Issue a label for this address, and keep track of it to put it
2975 in the unwind section. */
2977 /* Copy the information from the unwind record into this section. The
2978 data is already in the correct byte order. */
2979 memcpy (where
, unw_rec
, size
);
2980 /* Add the personality address to the image. */
2981 if (unwind
.personality_routine
!= 0)
2983 exp
.X_op
= O_symbol
;
2984 exp
.X_add_symbol
= unwind
.personality_routine
;
2985 exp
.X_add_number
= 0;
2986 fix_new_exp (frag_now
, frag_now_fix () - 8, 8,
2987 &exp
, 0, BFD_RELOC_IA64_LTOFF_FPTR64LSB
);
2988 unwind
.personality_routine
= 0;
2990 obj_elf_previous (0);
2993 free_list_records (unwind
.list
);
2994 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3000 dot_handlerdata (dummy
)
3003 generate_unwind_image ();
3004 demand_empty_rest_of_line ();
3008 dot_unwentry (dummy
)
3011 demand_empty_rest_of_line ();
3022 reg
= e
.X_add_number
- REG_BR
;
3023 if (e
.X_op
== O_register
&& reg
< 8)
3024 add_unwind_entry (output_rp_br (reg
));
3026 as_bad ("First operand not a valid branch register");
3030 dot_savemem (psprel
)
3037 sep
= parse_operand (&e1
);
3039 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3040 sep
= parse_operand (&e2
);
3042 reg1
= e1
.X_add_number
;
3043 val
= e2
.X_add_number
;
3045 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3046 if (e1
.X_op
== O_register
)
3048 if (e2
.X_op
== O_constant
)
3052 case REG_AR
+ AR_BSP
:
3053 add_unwind_entry (output_bsp_when ());
3054 add_unwind_entry ((psprel
3056 : output_bsp_sprel
) (val
));
3058 case REG_AR
+ AR_BSPSTORE
:
3059 add_unwind_entry (output_bspstore_when ());
3060 add_unwind_entry ((psprel
3061 ? output_bspstore_psprel
3062 : output_bspstore_sprel
) (val
));
3064 case REG_AR
+ AR_RNAT
:
3065 add_unwind_entry (output_rnat_when ());
3066 add_unwind_entry ((psprel
3067 ? output_rnat_psprel
3068 : output_rnat_sprel
) (val
));
3070 case REG_AR
+ AR_UNAT
:
3071 add_unwind_entry (output_unat_when ());
3072 add_unwind_entry ((psprel
3073 ? output_unat_psprel
3074 : output_unat_sprel
) (val
));
3076 case REG_AR
+ AR_FPSR
:
3077 add_unwind_entry (output_fpsr_when ());
3078 add_unwind_entry ((psprel
3079 ? output_fpsr_psprel
3080 : output_fpsr_sprel
) (val
));
3082 case REG_AR
+ AR_PFS
:
3083 add_unwind_entry (output_pfs_when ());
3084 add_unwind_entry ((psprel
3086 : output_pfs_sprel
) (val
));
3088 case REG_AR
+ AR_LC
:
3089 add_unwind_entry (output_lc_when ());
3090 add_unwind_entry ((psprel
3092 : output_lc_sprel
) (val
));
3095 add_unwind_entry (output_rp_when ());
3096 add_unwind_entry ((psprel
3098 : output_rp_sprel
) (val
));
3101 add_unwind_entry (output_preds_when ());
3102 add_unwind_entry ((psprel
3103 ? output_preds_psprel
3104 : output_preds_sprel
) (val
));
3107 add_unwind_entry (output_priunat_when_mem ());
3108 add_unwind_entry ((psprel
3109 ? output_priunat_psprel
3110 : output_priunat_sprel
) (val
));
3113 as_bad ("First operand not a valid register");
3117 as_bad (" Second operand not a valid constant");
3120 as_bad ("First operand not a register");
3129 sep
= parse_operand (&e1
);
3131 parse_operand (&e2
);
3133 if (e1
.X_op
!= O_constant
)
3134 as_bad ("First operand to .save.g must be a constant.");
3137 int grmask
= e1
.X_add_number
;
3139 add_unwind_entry (output_gr_mem (grmask
));
3142 int reg
= e2
.X_add_number
- REG_GR
;
3143 if (e2
.X_op
== O_register
&& reg
>=0 && reg
< 128)
3144 add_unwind_entry (output_gr_gr (grmask
, reg
));
3146 as_bad ("Second operand is an invalid register.");
3157 sep
= parse_operand (&e1
);
3159 if (e1
.X_op
!= O_constant
)
3160 as_bad ("Operand to .save.f must be a constant.");
3162 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3174 sep
= parse_operand (&e1
);
3175 if (e1
.X_op
!= O_constant
)
3177 as_bad ("First operand to .save.b must be a constant.");
3180 brmask
= e1
.X_add_number
;
3184 sep
= parse_operand (&e2
);
3185 reg
= e2
.X_add_number
- REG_GR
;
3186 if (e2
.X_op
!= O_register
|| reg
> 127)
3188 as_bad ("Second operand to .save.b must be a general register.");
3191 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3194 add_unwind_entry (output_br_mem (brmask
));
3196 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3197 ignore_rest_of_line ();
3206 sep
= parse_operand (&e1
);
3208 parse_operand (&e2
);
3210 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3211 as_bad ("Both operands of .save.gf must be constants.");
3214 int grmask
= e1
.X_add_number
;
3215 int frmask
= e2
.X_add_number
;
3216 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3227 sep
= parse_operand (&e
);
3228 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3229 ignore_rest_of_line ();
3231 if (e
.X_op
!= O_constant
)
3232 as_bad ("Operand to .spill must be a constant");
3234 add_unwind_entry (output_spill_base (e
.X_add_number
));
3238 dot_spillreg (dummy
)
3241 int sep
, ab
, xy
, reg
, treg
;
3244 sep
= parse_operand (&e1
);
3247 as_bad ("No second operand to .spillreg");
3251 parse_operand (&e2
);
3253 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3255 as_bad ("First operand to .spillreg must be a preserved register");
3259 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3261 as_bad ("Second operand to .spillreg must be a register");
3265 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3269 dot_spillmem (psprel
)
3275 sep
= parse_operand (&e1
);
3278 as_bad ("Second operand missing");
3282 parse_operand (&e2
);
3284 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3286 as_bad ("First operand to .spill%s must be a preserved register",
3287 psprel
? "psp" : "sp");
3291 if (e2
.X_op
!= O_constant
)
3293 as_bad ("Second operand to .spill%s must be a constant",
3294 psprel
? "psp" : "sp");
3299 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3301 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3305 dot_spillreg_p (dummy
)
3308 int sep
, ab
, xy
, reg
, treg
;
3309 expressionS e1
, e2
, e3
;
3312 sep
= parse_operand (&e1
);
3315 as_bad ("No second and third operand to .spillreg.p");
3319 sep
= parse_operand (&e2
);
3322 as_bad ("No third operand to .spillreg.p");
3326 parse_operand (&e3
);
3328 qp
= e1
.X_add_number
- REG_P
;
3330 if (e1
.X_op
!= O_register
|| qp
> 63)
3332 as_bad ("First operand to .spillreg.p must be a predicate");
3336 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3338 as_bad ("Second operand to .spillreg.p must be a preserved register");
3342 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3344 as_bad ("Third operand to .spillreg.p must be a register");
3348 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3352 dot_spillmem_p (psprel
)
3355 expressionS e1
, e2
, e3
;
3359 sep
= parse_operand (&e1
);
3362 as_bad ("Second operand missing");
3366 parse_operand (&e2
);
3369 as_bad ("Second operand missing");
3373 parse_operand (&e3
);
3375 qp
= e1
.X_add_number
- REG_P
;
3376 if (e1
.X_op
!= O_register
|| qp
> 63)
3378 as_bad ("First operand to .spill%s_p must be a predicate",
3379 psprel
? "psp" : "sp");
3383 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3385 as_bad ("Second operand to .spill%s_p must be a preserved register",
3386 psprel
? "psp" : "sp");
3390 if (e3
.X_op
!= O_constant
)
3392 as_bad ("Third operand to .spill%s_p must be a constant",
3393 psprel
? "psp" : "sp");
3398 add_unwind_entry (output_spill_psprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3400 add_unwind_entry (output_spill_sprel_p (qp
, ab
, reg
, e3
.X_add_number
));
3404 dot_label_state (dummy
)
3410 if (e
.X_op
!= O_constant
)
3412 as_bad ("Operand to .label_state must be a constant");
3415 add_unwind_entry (output_label_state (e
.X_add_number
));
3419 dot_copy_state (dummy
)
3425 if (e
.X_op
!= O_constant
)
3427 as_bad ("Operand to .copy_state must be a constant");
3430 add_unwind_entry (output_copy_state (e
.X_add_number
));
3440 sep
= parse_operand (&e1
);
3443 as_bad ("Second operand to .unwabi missing");
3446 sep
= parse_operand (&e2
);
3447 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3448 ignore_rest_of_line ();
3450 if (e1
.X_op
!= O_constant
)
3452 as_bad ("First operand to .unwabi must be a constant");
3456 if (e2
.X_op
!= O_constant
)
3458 as_bad ("Second operand to .unwabi must be a constant");
3462 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3466 dot_personality (dummy
)
3471 name
= input_line_pointer
;
3472 c
= get_symbol_end ();
3473 p
= input_line_pointer
;
3474 unwind
.personality_routine
= symbol_find_or_make (name
);
3477 demand_empty_rest_of_line ();
3487 unwind
.proc_start
= expr_build_dot ();
3488 /* Parse names of main and alternate entry points and mark them as
3489 function symbols: */
3493 name
= input_line_pointer
;
3494 c
= get_symbol_end ();
3495 p
= input_line_pointer
;
3496 sym
= symbol_find_or_make (name
);
3497 if (unwind
.proc_start
== 0)
3499 unwind
.proc_start
= sym
;
3501 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3504 if (*input_line_pointer
!= ',')
3506 ++input_line_pointer
;
3508 demand_empty_rest_of_line ();
3511 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3512 unwind
.personality_routine
= 0;
3519 unwind
.prologue
= 0;
3520 unwind
.prologue_mask
= 0;
3522 add_unwind_entry (output_body ());
3523 demand_empty_rest_of_line ();
3527 dot_prologue (dummy
)
3531 int mask
= 0, grsave
;
3533 if (!is_it_end_of_statement ())
3536 sep
= parse_operand (&e1
);
3538 as_bad ("No second operand to .prologue");
3539 sep
= parse_operand (&e2
);
3540 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3541 ignore_rest_of_line ();
3543 if (e1
.X_op
== O_constant
)
3545 mask
= e1
.X_add_number
;
3547 if (e2
.X_op
== O_constant
)
3548 grsave
= e2
.X_add_number
;
3549 else if (e2
.X_op
== O_register
3550 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3553 as_bad ("Second operand not a constant or general register");
3555 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3558 as_bad ("First operand not a constant");
3561 add_unwind_entry (output_prologue ());
3563 unwind
.prologue
= 1;
3564 unwind
.prologue_mask
= mask
;
3575 subsegT saved_subseg
;
3577 saved_seg
= now_seg
;
3578 saved_subseg
= now_subseg
;
3581 demand_empty_rest_of_line ();
3583 insn_group_break (1, 0, 0);
3585 /* If there was a .handlerdata, we haven't generated an image yet. */
3586 if (unwind
.info
== 0)
3588 generate_unwind_image ();
3591 subseg_set (md
.last_text_seg
, 0);
3592 unwind
.proc_end
= expr_build_dot ();
3594 set_section ((char *) special_section_name
[SPECIAL_SECTION_UNWIND
]);
3595 ptr
= frag_more (24);
3596 where
= frag_now_fix () - 24;
3598 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
3599 e
.X_op
= O_pseudo_fixup
;
3600 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3602 e
.X_add_symbol
= unwind
.proc_start
;
3603 ia64_cons_fix_new (frag_now
, where
, 8, &e
);
3605 e
.X_op
= O_pseudo_fixup
;
3606 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3608 e
.X_add_symbol
= unwind
.proc_end
;
3609 ia64_cons_fix_new (frag_now
, where
+ 8, 8, &e
);
3611 if (unwind
.info
!= 0)
3613 e
.X_op
= O_pseudo_fixup
;
3614 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
3616 e
.X_add_symbol
= unwind
.info
;
3617 ia64_cons_fix_new (frag_now
, where
+ 16, 8, &e
);
3620 md_number_to_chars (ptr
+ 16, 0, 8);
3622 subseg_set (saved_seg
, saved_subseg
);
3623 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
3627 dot_template (template)
3630 CURR_SLOT
.user_template
= template;
3637 int ins
, locs
, outs
, rots
;
3639 if (is_it_end_of_statement ())
3640 ins
= locs
= outs
= rots
= 0;
3643 ins
= get_absolute_expression ();
3644 if (*input_line_pointer
++ != ',')
3646 locs
= get_absolute_expression ();
3647 if (*input_line_pointer
++ != ',')
3649 outs
= get_absolute_expression ();
3650 if (*input_line_pointer
++ != ',')
3652 rots
= get_absolute_expression ();
3654 set_regstack (ins
, locs
, outs
, rots
);
3658 as_bad ("Comma expected");
3659 ignore_rest_of_line ();
3666 unsigned num_regs
, num_alloced
= 0;
3667 struct dynreg
**drpp
, *dr
;
3668 int ch
, base_reg
= 0;
3674 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
3675 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
3676 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
3680 /* first, remove existing names from hash table: */
3681 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
3683 hash_delete (md
.dynreg_hash
, dr
->name
);
3687 drpp
= &md
.dynreg
[type
];
3690 start
= input_line_pointer
;
3691 ch
= get_symbol_end ();
3692 *input_line_pointer
= ch
;
3693 len
= (input_line_pointer
- start
);
3696 if (*input_line_pointer
!= '[')
3698 as_bad ("Expected '['");
3701 ++input_line_pointer
; /* skip '[' */
3703 num_regs
= get_absolute_expression ();
3705 if (*input_line_pointer
++ != ']')
3707 as_bad ("Expected ']'");
3712 num_alloced
+= num_regs
;
3716 if (num_alloced
> md
.rot
.num_regs
)
3718 as_bad ("Used more than the declared %d rotating registers",
3724 if (num_alloced
> 96)
3726 as_bad ("Used more than the available 96 rotating registers");
3731 if (num_alloced
> 48)
3733 as_bad ("Used more than the available 48 rotating registers");
3742 name
= obstack_alloc (¬es
, len
+ 1);
3743 memcpy (name
, start
, len
);
3748 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
3749 memset (*drpp
, 0, sizeof (*dr
));
3754 dr
->num_regs
= num_regs
;
3755 dr
->base
= base_reg
;
3757 base_reg
+= num_regs
;
3759 if (hash_insert (md
.dynreg_hash
, name
, dr
))
3761 as_bad ("Attempt to redefine register set `%s'", name
);
3765 if (*input_line_pointer
!= ',')
3767 ++input_line_pointer
; /* skip comma */
3770 demand_empty_rest_of_line ();
3774 ignore_rest_of_line ();
3778 dot_byteorder (byteorder
)
3781 target_big_endian
= byteorder
;
3793 option
= input_line_pointer
;
3794 ch
= get_symbol_end ();
3795 if (strcmp (option
, "lsb") == 0)
3796 md
.flags
&= ~EF_IA_64_BE
;
3797 else if (strcmp (option
, "msb") == 0)
3798 md
.flags
|= EF_IA_64_BE
;
3799 else if (strcmp (option
, "abi32") == 0)
3800 md
.flags
&= ~EF_IA_64_ABI64
;
3801 else if (strcmp (option
, "abi64") == 0)
3802 md
.flags
|= EF_IA_64_ABI64
;
3804 as_bad ("Unknown psr option `%s'", option
);
3805 *input_line_pointer
= ch
;
3808 if (*input_line_pointer
!= ',')
3811 ++input_line_pointer
;
3814 demand_empty_rest_of_line ();
3821 as_bad (".alias not implemented yet");
3828 new_logical_line (0, get_absolute_expression ());
3829 demand_empty_rest_of_line ();
3833 parse_section_name ()
3839 if (*input_line_pointer
!= '"')
3841 as_bad ("Missing section name");
3842 ignore_rest_of_line ();
3845 name
= demand_copy_C_string (&len
);
3848 ignore_rest_of_line ();
3852 if (*input_line_pointer
!= ',')
3854 as_bad ("Comma expected after section name");
3855 ignore_rest_of_line ();
3858 ++input_line_pointer
; /* skip comma */
3866 char *name
= parse_section_name ();
3872 obj_elf_previous (0);
3875 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
3877 stmt_float_cons (kind
)
3884 case 'd': size
= 8; break;
3885 case 'x': size
= 10; break;
3892 ia64_do_align (size
);
3900 int saved_auto_align
= md
.auto_align
;
3904 md
.auto_align
= saved_auto_align
;
3908 dot_xfloat_cons (kind
)
3911 char *name
= parse_section_name ();
3916 stmt_float_cons (kind
);
3917 obj_elf_previous (0);
3921 dot_xstringer (zero
)
3924 char *name
= parse_section_name ();
3930 obj_elf_previous (0);
3937 int saved_auto_align
= md
.auto_align
;
3938 char *name
= parse_section_name ();
3945 md
.auto_align
= saved_auto_align
;
3946 obj_elf_previous (0);
3950 dot_xfloat_cons_ua (kind
)
3953 int saved_auto_align
= md
.auto_align
;
3954 char *name
= parse_section_name ();
3960 stmt_float_cons (kind
);
3961 md
.auto_align
= saved_auto_align
;
3962 obj_elf_previous (0);
3965 /* .reg.val <regname>,value */
3973 if (reg
.X_op
!= O_register
)
3975 as_bad (_("Register name expected"));
3976 ignore_rest_of_line ();
3978 else if (*input_line_pointer
++ != ',')
3980 as_bad (_("Comma expected"));
3981 ignore_rest_of_line ();
3985 valueT value
= get_absolute_expression ();
3986 int regno
= reg
.X_add_number
;
3987 if (regno
< REG_GR
|| regno
> REG_GR
+128)
3988 as_warn (_("Register value annotation ignored"));
3991 gr_values
[regno
-REG_GR
].known
= 1;
3992 gr_values
[regno
-REG_GR
].value
= value
;
3993 gr_values
[regno
-REG_GR
].path
= md
.path
;
3996 demand_empty_rest_of_line ();
3999 /* select dv checking mode
4004 A stop is inserted when changing modes
4010 if (md
.manual_bundling
)
4011 as_warn (_("Directive invalid within a bundle"));
4013 if (type
== 'E' || type
== 'A')
4014 md
.mode_explicitly_set
= 0;
4016 md
.mode_explicitly_set
= 1;
4023 if (md
.explicit_mode
)
4024 insn_group_break (1, 0, 0);
4025 md
.explicit_mode
= 0;
4029 if (!md
.explicit_mode
)
4030 insn_group_break (1, 0, 0);
4031 md
.explicit_mode
= 1;
4035 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4036 insn_group_break (1, 0, 0);
4037 md
.explicit_mode
= md
.default_explicit_mode
;
4038 md
.mode_explicitly_set
= 0;
4049 for (regno
= 0;regno
< 64;regno
++)
4051 if (mask
& ((valueT
)1<<regno
))
4053 fprintf (stderr
, "%s p%d", comma
, regno
);
4060 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4061 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4062 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4063 .pred.safe_across_calls p1 [, p2 [,...]]
4071 int p1
= -1, p2
= -1;
4075 if (*input_line_pointer
!= '"')
4077 as_bad (_("Missing predicate relation type"));
4078 ignore_rest_of_line ();
4084 char *form
= demand_copy_C_string (&len
);
4085 if (strcmp (form
, "mutex") == 0)
4087 else if (strcmp (form
, "clear") == 0)
4089 else if (strcmp (form
, "imply") == 0)
4093 as_bad (_("Unrecognized predicate relation type"));
4094 ignore_rest_of_line ();
4098 if (*input_line_pointer
== ',')
4099 ++input_line_pointer
;
4109 if (toupper (*input_line_pointer
) != 'P'
4110 || (regno
= atoi (++input_line_pointer
)) < 0
4113 as_bad (_("Predicate register expected"));
4114 ignore_rest_of_line ();
4117 while (isdigit (*input_line_pointer
))
4118 ++input_line_pointer
;
4125 as_warn (_("Duplicate predicate register ignored"));
4126 mask
|= bit
; count
++;
4127 /* see if it's a range */
4128 if (*input_line_pointer
== '-')
4131 ++input_line_pointer
;
4133 if (toupper (*input_line_pointer
) != 'P'
4134 || (regno
= atoi (++input_line_pointer
)) < 0
4137 as_bad (_("Predicate register expected"));
4138 ignore_rest_of_line ();
4141 while (isdigit (*input_line_pointer
))
4142 ++input_line_pointer
;
4146 as_bad (_("Bad register range"));
4147 ignore_rest_of_line ();
4153 mask
|= bit
; count
++;
4157 if (*input_line_pointer
!= ',')
4159 ++input_line_pointer
;
4168 clear_qp_mutex (mask
);
4169 clear_qp_implies (mask
, (valueT
)0);
4172 if (count
!= 2 || p1
== -1 || p2
== -1)
4173 as_bad (_("Predicate source and target required"));
4174 else if (p1
== 0 || p2
== 0)
4175 as_bad (_("Use of p0 is not valid in this context"));
4177 add_qp_imply (p1
, p2
);
4182 as_bad (_("At least two PR arguments expected"));
4187 as_bad (_("Use of p0 is not valid in this context"));
4190 add_qp_mutex (mask
);
4193 /* note that we don't override any existing relations */
4196 as_bad (_("At least one PR argument expected"));
4201 fprintf (stderr
, "Safe across calls: ");
4202 print_prmask (mask
);
4203 fprintf (stderr
, "\n");
4205 qp_safe_across_calls
= mask
;
4208 demand_empty_rest_of_line ();
4211 /* .entry label [, label [, ...]]
4212 Hint to DV code that the given labels are to be considered entry points.
4213 Otherwise, only global labels are considered entry points.
4226 name
= input_line_pointer
;
4227 c
= get_symbol_end ();
4228 symbolP
= symbol_find_or_make (name
);
4230 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4232 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4235 *input_line_pointer
= c
;
4237 c
= *input_line_pointer
;
4240 input_line_pointer
++;
4242 if (*input_line_pointer
== '\n')
4248 demand_empty_rest_of_line ();
4251 /* .mem.offset offset, base
4252 "base" is used to distinguish between offsets from a different base.
4255 dot_mem_offset (dummy
)
4258 md
.mem_offset
.hint
= 1;
4259 md
.mem_offset
.offset
= get_absolute_expression ();
4260 if (*input_line_pointer
!= ',')
4262 as_bad (_("Comma expected"));
4263 ignore_rest_of_line ();
4266 ++input_line_pointer
;
4267 md
.mem_offset
.base
= get_absolute_expression ();
4268 demand_empty_rest_of_line ();
4271 /* ia64-specific pseudo-ops: */
4272 const pseudo_typeS md_pseudo_table
[] =
4274 { "radix", dot_radix
, 0 },
4275 { "lcomm", s_lcomm_bytes
, 1 },
4276 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4277 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4278 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4279 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4280 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4281 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4282 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4283 { "proc", dot_proc
, 0 },
4284 { "body", dot_body
, 0 },
4285 { "prologue", dot_prologue
, 0 },
4286 { "endp", dot_endp
},
4287 { "file", dwarf2_directive_file
},
4288 { "loc", dwarf2_directive_loc
},
4290 { "fframe", dot_fframe
},
4291 { "vframe", dot_vframe
},
4292 { "vframesp", dot_vframesp
},
4293 { "vframepsp", dot_vframepsp
},
4294 { "save", dot_save
},
4295 { "restore", dot_restore
},
4296 { "restorereg", dot_restorereg
},
4297 { "restorereg.p", dot_restorereg_p
},
4298 { "handlerdata", dot_handlerdata
},
4299 { "unwentry", dot_unwentry
},
4300 { "altrp", dot_altrp
},
4301 { "savesp", dot_savemem
, 0 },
4302 { "savepsp", dot_savemem
, 1 },
4303 { "save.g", dot_saveg
},
4304 { "save.f", dot_savef
},
4305 { "save.b", dot_saveb
},
4306 { "save.gf", dot_savegf
},
4307 { "spill", dot_spill
},
4308 { "spillreg", dot_spillreg
},
4309 { "spillsp", dot_spillmem
, 0 },
4310 { "spillpsp", dot_spillmem
, 1 },
4311 { "spillreg.p", dot_spillreg_p
},
4312 { "spillsp.p", dot_spillmem_p
, 0 },
4313 { "spillpsp.p", dot_spillmem_p
, 1 },
4314 { "label_state", dot_label_state
},
4315 { "copy_state", dot_copy_state
},
4316 { "unwabi", dot_unwabi
},
4317 { "personality", dot_personality
},
4319 { "estate", dot_estate
},
4321 { "mii", dot_template
, 0x0 },
4322 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4323 { "mlx", dot_template
, 0x2 },
4324 { "mmi", dot_template
, 0x4 },
4325 { "mfi", dot_template
, 0x6 },
4326 { "mmf", dot_template
, 0x7 },
4327 { "mib", dot_template
, 0x8 },
4328 { "mbb", dot_template
, 0x9 },
4329 { "bbb", dot_template
, 0xb },
4330 { "mmb", dot_template
, 0xc },
4331 { "mfb", dot_template
, 0xe },
4333 { "lb", dot_scope
, 0 },
4334 { "le", dot_scope
, 1 },
4336 { "align", s_align_bytes
, 0 },
4337 { "regstk", dot_regstk
, 0 },
4338 { "rotr", dot_rot
, DYNREG_GR
},
4339 { "rotf", dot_rot
, DYNREG_FR
},
4340 { "rotp", dot_rot
, DYNREG_PR
},
4341 { "lsb", dot_byteorder
, 0 },
4342 { "msb", dot_byteorder
, 1 },
4343 { "psr", dot_psr
, 0 },
4344 { "alias", dot_alias
, 0 },
4345 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4347 { "xdata1", dot_xdata
, 1 },
4348 { "xdata2", dot_xdata
, 2 },
4349 { "xdata4", dot_xdata
, 4 },
4350 { "xdata8", dot_xdata
, 8 },
4351 { "xreal4", dot_xfloat_cons
, 'f' },
4352 { "xreal8", dot_xfloat_cons
, 'd' },
4353 { "xreal10", dot_xfloat_cons
, 'x' },
4354 { "xstring", dot_xstringer
, 0 },
4355 { "xstringz", dot_xstringer
, 1 },
4357 /* unaligned versions: */
4358 { "xdata2.ua", dot_xdata_ua
, 2 },
4359 { "xdata4.ua", dot_xdata_ua
, 4 },
4360 { "xdata8.ua", dot_xdata_ua
, 8 },
4361 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4362 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4363 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4365 /* annotations/DV checking support */
4366 { "entry", dot_entry
, 0 },
4367 { "mem.offset", dot_mem_offset
},
4368 { "pred.rel", dot_pred_rel
, 0 },
4369 { "pred.rel.clear", dot_pred_rel
, 'c' },
4370 { "pred.rel.imply", dot_pred_rel
, 'i' },
4371 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4372 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4373 { "reg.val", dot_reg_val
},
4374 { "auto", dot_dv_mode
, 'a' },
4375 { "explicit", dot_dv_mode
, 'e' },
4376 { "default", dot_dv_mode
, 'd' },
4381 static const struct pseudo_opcode
4384 void (*handler
) (int);
4389 /* these are more like pseudo-ops, but don't start with a dot */
4390 { "data1", cons
, 1 },
4391 { "data2", cons
, 2 },
4392 { "data4", cons
, 4 },
4393 { "data8", cons
, 8 },
4394 { "real4", stmt_float_cons
, 'f' },
4395 { "real8", stmt_float_cons
, 'd' },
4396 { "real10", stmt_float_cons
, 'x' },
4397 { "string", stringer
, 0 },
4398 { "stringz", stringer
, 1 },
4400 /* unaligned versions: */
4401 { "data2.ua", stmt_cons_ua
, 2 },
4402 { "data4.ua", stmt_cons_ua
, 4 },
4403 { "data8.ua", stmt_cons_ua
, 8 },
4404 { "real4.ua", float_cons
, 'f' },
4405 { "real8.ua", float_cons
, 'd' },
4406 { "real10.ua", float_cons
, 'x' },
4409 /* Declare a register by creating a symbol for it and entering it in
4410 the symbol table. */
4412 declare_register (name
, regnum
)
4419 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4421 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4423 as_fatal ("Inserting \"%s\" into register table failed: %s",
4430 declare_register_set (prefix
, num_regs
, base_regnum
)
4438 for (i
= 0; i
< num_regs
; ++i
)
4440 sprintf (name
, "%s%u", prefix
, i
);
4441 declare_register (name
, base_regnum
+ i
);
4446 operand_width (opnd
)
4447 enum ia64_opnd opnd
;
4449 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4450 unsigned int bits
= 0;
4454 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4455 bits
+= odesc
->field
[i
].bits
;
4461 operand_match (idesc
, index
, e
)
4462 const struct ia64_opcode
*idesc
;
4466 enum ia64_opnd opnd
= idesc
->operands
[index
];
4467 int bits
, relocatable
= 0;
4468 struct insn_fix
*fix
;
4475 case IA64_OPND_AR_CCV
:
4476 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
4480 case IA64_OPND_AR_PFS
:
4481 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
4486 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
4491 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
4496 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
4500 case IA64_OPND_PR_ROT
:
4501 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
4506 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
4510 case IA64_OPND_PSR_L
:
4511 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
4515 case IA64_OPND_PSR_UM
:
4516 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
4521 if (e
->X_op
== O_constant
&& e
->X_add_number
== 1)
4526 if (e
->X_op
== O_constant
&& e
->X_add_number
== 8)
4531 if (e
->X_op
== O_constant
&& e
->X_add_number
== 16)
4535 /* register operands: */
4538 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
4539 && e
->X_add_number
< REG_AR
+ 128)
4545 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
4546 && e
->X_add_number
< REG_BR
+ 8)
4551 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
4552 && e
->X_add_number
< REG_CR
+ 128)
4560 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
4561 && e
->X_add_number
< REG_FR
+ 128)
4567 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
4568 && e
->X_add_number
< REG_P
+ 64)
4575 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4576 && e
->X_add_number
< REG_GR
+ 128)
4580 case IA64_OPND_R3_2
:
4581 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
4582 && e
->X_add_number
< REG_GR
+ 4)
4586 /* indirect operands: */
4587 case IA64_OPND_CPUID_R3
:
4588 case IA64_OPND_DBR_R3
:
4589 case IA64_OPND_DTR_R3
:
4590 case IA64_OPND_ITR_R3
:
4591 case IA64_OPND_IBR_R3
:
4592 case IA64_OPND_MSR_R3
:
4593 case IA64_OPND_PKR_R3
:
4594 case IA64_OPND_PMC_R3
:
4595 case IA64_OPND_PMD_R3
:
4596 case IA64_OPND_RR_R3
:
4597 if (e
->X_op
== O_index
&& e
->X_op_symbol
4598 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
4599 == opnd
- IA64_OPND_CPUID_R3
))
4604 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
4608 /* immediate operands: */
4609 case IA64_OPND_CNT2a
:
4610 case IA64_OPND_LEN4
:
4611 case IA64_OPND_LEN6
:
4612 bits
= operand_width (idesc
->operands
[index
]);
4613 if (e
->X_op
== O_constant
4614 && (bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
4618 case IA64_OPND_CNT2b
:
4619 if (e
->X_op
== O_constant
4620 && (bfd_vma
) (e
->X_add_number
- 1) < 3)
4624 case IA64_OPND_CNT2c
:
4625 val
= e
->X_add_number
;
4626 if (e
->X_op
== O_constant
4627 && (val
== 0 || val
== 7 || val
== 15 || val
== 16))
4632 /* SOR must be an integer multiple of 8 */
4633 if (e
->X_add_number
& 0x7)
4637 if (e
->X_op
== O_constant
&&
4638 (bfd_vma
) e
->X_add_number
<= 96)
4642 case IA64_OPND_IMMU62
:
4643 if (e
->X_op
== O_constant
)
4645 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
4650 /* FIXME -- need 62-bit relocation type */
4651 as_bad (_("62-bit relocation not yet implemented"));
4655 case IA64_OPND_IMMU64
:
4656 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
4657 || e
->X_op
== O_subtract
)
4659 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4660 fix
->code
= BFD_RELOC_IA64_IMM64
;
4661 if (e
->X_op
!= O_subtract
)
4663 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4664 if (e
->X_op
== O_pseudo_fixup
)
4668 fix
->opnd
= idesc
->operands
[index
];
4671 ++CURR_SLOT
.num_fixups
;
4674 else if (e
->X_op
== O_constant
)
4678 case IA64_OPND_CCNT5
:
4679 case IA64_OPND_CNT5
:
4680 case IA64_OPND_CNT6
:
4681 case IA64_OPND_CPOS6a
:
4682 case IA64_OPND_CPOS6b
:
4683 case IA64_OPND_CPOS6c
:
4684 case IA64_OPND_IMMU2
:
4685 case IA64_OPND_IMMU7a
:
4686 case IA64_OPND_IMMU7b
:
4687 case IA64_OPND_IMMU21
:
4688 case IA64_OPND_IMMU24
:
4689 case IA64_OPND_MBTYPE4
:
4690 case IA64_OPND_MHTYPE8
:
4691 case IA64_OPND_POS6
:
4692 bits
= operand_width (idesc
->operands
[index
]);
4693 if (e
->X_op
== O_constant
4694 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4698 case IA64_OPND_IMMU9
:
4699 bits
= operand_width (idesc
->operands
[index
]);
4700 if (e
->X_op
== O_constant
4701 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
4703 int lobits
= e
->X_add_number
& 0x3;
4704 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
4705 e
->X_add_number
|= (bfd_vma
)0x3;
4710 case IA64_OPND_IMM44
:
4711 /* least 16 bits must be zero */
4712 if ((e
->X_add_number
& 0xffff) != 0)
4713 as_warn (_("lower 16 bits of mask ignored"));
4715 if (e
->X_op
== O_constant
4716 && ((e
->X_add_number
>= 0
4717 && e
->X_add_number
< ((bfd_vma
) 1 << 44))
4718 || (e
->X_add_number
< 0
4719 && -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
4722 if (e
->X_add_number
>= 0
4723 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
4725 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
4731 case IA64_OPND_IMM17
:
4732 /* bit 0 is a don't care (pr0 is hardwired to 1) */
4733 if (e
->X_op
== O_constant
4734 && ((e
->X_add_number
>= 0
4735 && e
->X_add_number
< ((bfd_vma
) 1 << 17))
4736 || (e
->X_add_number
< 0
4737 && -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
4740 if (e
->X_add_number
>= 0
4741 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
4743 e
->X_add_number
|= ~(((bfd_vma
)1 << 17) - 1);
4749 case IA64_OPND_IMM14
:
4750 case IA64_OPND_IMM22
:
4752 case IA64_OPND_IMM1
:
4753 case IA64_OPND_IMM8
:
4754 case IA64_OPND_IMM8U4
:
4755 case IA64_OPND_IMM8M1
:
4756 case IA64_OPND_IMM8M1U4
:
4757 case IA64_OPND_IMM8M1U8
:
4758 case IA64_OPND_IMM9a
:
4759 case IA64_OPND_IMM9b
:
4760 bits
= operand_width (idesc
->operands
[index
]);
4761 if (relocatable
&& (e
->X_op
== O_symbol
4762 || e
->X_op
== O_subtract
4763 || e
->X_op
== O_pseudo_fixup
))
4765 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4767 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
4768 fix
->code
= BFD_RELOC_IA64_IMM14
;
4770 fix
->code
= BFD_RELOC_IA64_IMM22
;
4772 if (e
->X_op
!= O_subtract
)
4774 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4775 if (e
->X_op
== O_pseudo_fixup
)
4779 fix
->opnd
= idesc
->operands
[index
];
4782 ++CURR_SLOT
.num_fixups
;
4785 else if (e
->X_op
!= O_constant
4786 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
4789 if (opnd
== IA64_OPND_IMM8M1U4
)
4791 /* Zero is not valid for unsigned compares that take an adjusted
4792 constant immediate range. */
4793 if (e
->X_add_number
== 0)
4796 /* Sign-extend 32-bit unsigned numbers, so that the following range
4797 checks will work. */
4798 val
= e
->X_add_number
;
4799 if (((val
& (~(bfd_vma
)0 << 32)) == 0)
4800 && ((val
& ((bfd_vma
)1 << 31)) != 0))
4801 val
= ((val
<< 32) >> 32);
4803 /* Check for 0x100000000. This is valid because
4804 0x100000000-1 is the same as ((uint32_t) -1). */
4805 if (val
== ((bfd_signed_vma
) 1 << 32))
4810 else if (opnd
== IA64_OPND_IMM8M1U8
)
4812 /* Zero is not valid for unsigned compares that take an adjusted
4813 constant immediate range. */
4814 if (e
->X_add_number
== 0)
4817 /* Check for 0x10000000000000000. */
4818 if (e
->X_op
== O_big
)
4820 if (generic_bignum
[0] == 0
4821 && generic_bignum
[1] == 0
4822 && generic_bignum
[2] == 0
4823 && generic_bignum
[3] == 0
4824 && generic_bignum
[4] == 1)
4830 val
= e
->X_add_number
- 1;
4832 else if (opnd
== IA64_OPND_IMM8M1
)
4833 val
= e
->X_add_number
- 1;
4834 else if (opnd
== IA64_OPND_IMM8U4
)
4836 /* Sign-extend 32-bit unsigned numbers, so that the following range
4837 checks will work. */
4838 val
= e
->X_add_number
;
4839 if (((val
& (~(bfd_vma
)0 << 32)) == 0)
4840 && ((val
& ((bfd_vma
)1 << 31)) != 0))
4841 val
= ((val
<< 32) >> 32);
4844 val
= e
->X_add_number
;
4846 if ((val
>= 0 && val
< ((bfd_vma
) 1 << (bits
- 1)))
4847 || (val
< 0 && -val
<= ((bfd_vma
) 1 << (bits
- 1))))
4851 case IA64_OPND_INC3
:
4852 /* +/- 1, 4, 8, 16 */
4853 val
= e
->X_add_number
;
4856 if (e
->X_op
== O_constant
4857 && (val
== 1 || val
== 4 || val
== 8 || val
== 16))
4861 case IA64_OPND_TGT25
:
4862 case IA64_OPND_TGT25b
:
4863 case IA64_OPND_TGT25c
:
4864 case IA64_OPND_TGT64
:
4865 if (e
->X_op
== O_symbol
)
4867 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4868 if (opnd
== IA64_OPND_TGT25
)
4869 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
4870 else if (opnd
== IA64_OPND_TGT25b
)
4871 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
4872 else if (opnd
== IA64_OPND_TGT25c
)
4873 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
4874 else if (opnd
== IA64_OPND_TGT64
)
4875 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
4879 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
4880 fix
->opnd
= idesc
->operands
[index
];
4883 ++CURR_SLOT
.num_fixups
;
4886 case IA64_OPND_TAG13
:
4887 case IA64_OPND_TAG13b
:
4894 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
4895 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, 0);
4896 fix
->opnd
= idesc
->operands
[index
];
4899 ++CURR_SLOT
.num_fixups
;
4919 memset (e
, 0, sizeof (*e
));
4922 if (*input_line_pointer
!= '}')
4924 sep
= *input_line_pointer
++;
4928 if (!md
.manual_bundling
)
4929 as_warn ("Found '}' when manual bundling is off");
4931 CURR_SLOT
.manual_bundling_off
= 1;
4932 md
.manual_bundling
= 0;
4938 /* Returns the next entry in the opcode table that matches the one in
4939 IDESC, and frees the entry in IDESC. If no matching entry is
4940 found, NULL is returned instead. */
4942 static struct ia64_opcode
*
4943 get_next_opcode (struct ia64_opcode
*idesc
)
4945 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
4946 ia64_free_opcode (idesc
);
4950 /* Parse the operands for the opcode and find the opcode variant that
4951 matches the specified operands, or NULL if no match is possible. */
4952 static struct ia64_opcode
*
4953 parse_operands (idesc
)
4954 struct ia64_opcode
*idesc
;
4956 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
4958 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
4960 char *first_arg
= 0, *end
, *saved_input_pointer
;
4963 assert (strlen (idesc
->name
) <= 128);
4965 strcpy (mnemonic
, idesc
->name
);
4966 if (idesc
->operands
[2] == IA64_OPND_SOF
)
4968 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
4969 can't parse the first operand until we have parsed the
4970 remaining operands of the "alloc" instruction. */
4972 first_arg
= input_line_pointer
;
4973 end
= strchr (input_line_pointer
, '=');
4976 as_bad ("Expected separator `='");
4979 input_line_pointer
= end
+ 1;
4984 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
4986 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
4987 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
4992 if (sep
!= '=' && sep
!= ',')
4997 if (num_outputs
> 0)
4998 as_bad ("Duplicate equal sign (=) in instruction");
5000 num_outputs
= i
+ 1;
5005 as_bad ("Illegal operand separator `%c'", sep
);
5009 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5011 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5012 know (strcmp (idesc
->name
, "alloc") == 0);
5013 if (num_operands
== 5 /* first_arg not included in this count! */
5014 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5015 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5016 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5017 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5019 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5020 CURR_SLOT
.opnd
[3].X_add_number
,
5021 CURR_SLOT
.opnd
[4].X_add_number
,
5022 CURR_SLOT
.opnd
[5].X_add_number
);
5024 /* now we can parse the first arg: */
5025 saved_input_pointer
= input_line_pointer
;
5026 input_line_pointer
= first_arg
;
5027 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5029 --num_outputs
; /* force error */
5030 input_line_pointer
= saved_input_pointer
;
5032 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5033 CURR_SLOT
.opnd
[3].X_add_number
5034 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5035 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5039 highest_unmatched_operand
= 0;
5040 expected_operand
= idesc
->operands
[0];
5041 for (; idesc
; idesc
= get_next_opcode (idesc
))
5043 if (num_outputs
!= idesc
->num_outputs
)
5044 continue; /* mismatch in # of outputs */
5046 CURR_SLOT
.num_fixups
= 0;
5047 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5048 if (!operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
))
5051 if (i
!= num_operands
)
5053 if (i
> highest_unmatched_operand
)
5055 highest_unmatched_operand
= i
;
5056 expected_operand
= idesc
->operands
[i
];
5061 if (num_operands
< NELEMS (idesc
->operands
)
5062 && idesc
->operands
[num_operands
])
5063 continue; /* mismatch in number of arguments */
5069 if (expected_operand
)
5070 as_bad ("Operand %u of `%s' should be %s",
5071 highest_unmatched_operand
+ 1, mnemonic
,
5072 elf64_ia64_operands
[expected_operand
].desc
);
5074 as_bad ("Operand mismatch");
5081 build_insn (slot
, insnp
)
5085 const struct ia64_operand
*odesc
, *o2desc
;
5086 struct ia64_opcode
*idesc
= slot
->idesc
;
5087 bfd_signed_vma insn
, val
;
5091 insn
= idesc
->opcode
| slot
->qp_regno
;
5093 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5095 if (slot
->opnd
[i
].X_op
== O_register
5096 || slot
->opnd
[i
].X_op
== O_constant
5097 || slot
->opnd
[i
].X_op
== O_index
)
5098 val
= slot
->opnd
[i
].X_add_number
;
5099 else if (slot
->opnd
[i
].X_op
== O_big
)
5101 /* This must be the value 0x10000000000000000. */
5102 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5108 switch (idesc
->operands
[i
])
5110 case IA64_OPND_IMMU64
:
5111 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5112 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5113 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5114 | (((val
>> 63) & 0x1) << 36));
5117 case IA64_OPND_IMMU62
:
5118 val
&= 0x3fffffffffffffffULL
;
5119 if (val
!= slot
->opnd
[i
].X_add_number
)
5120 as_warn (_("Value truncated to 62 bits"));
5121 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5122 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5125 case IA64_OPND_TGT64
:
5127 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5128 insn
|= ((((val
>> 59) & 0x1) << 36)
5129 | (((val
>> 0) & 0xfffff) << 13));
5160 case IA64_OPND_R3_2
:
5161 case IA64_OPND_CPUID_R3
:
5162 case IA64_OPND_DBR_R3
:
5163 case IA64_OPND_DTR_R3
:
5164 case IA64_OPND_ITR_R3
:
5165 case IA64_OPND_IBR_R3
:
5167 case IA64_OPND_MSR_R3
:
5168 case IA64_OPND_PKR_R3
:
5169 case IA64_OPND_PMC_R3
:
5170 case IA64_OPND_PMD_R3
:
5171 case IA64_OPND_RR_R3
:
5179 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5180 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5182 as_bad_where (slot
->src_file
, slot
->src_line
,
5183 "Bad operand value: %s", err
);
5184 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5186 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5187 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5189 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5190 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5192 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5193 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5194 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5196 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5197 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5207 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5208 unsigned int manual_bundling
= 0;
5209 enum ia64_unit required_unit
, insn_unit
= 0;
5210 enum ia64_insn_type type
[3], insn_type
;
5211 unsigned int template, orig_template
;
5212 bfd_vma insn
[3] = {-1, -1, -1};
5213 struct ia64_opcode
*idesc
;
5214 int end_of_insn_group
= 0, user_template
= -1;
5215 int n
, i
, j
, first
, curr
;
5216 unw_rec_list
*ptr
, *prev
;
5217 bfd_vma t0
= 0, t1
= 0;
5218 struct label_fix
*lfix
;
5219 struct insn_fix
*ifix
;
5224 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5225 know (first
>= 0 & first
< NUM_SLOTS
);
5226 n
= MIN (3, md
.num_slots_in_use
);
5228 /* Determine template: user user_template if specified, best match
5231 if (md
.slot
[first
].user_template
>= 0)
5232 user_template
= template = md
.slot
[first
].user_template
;
5235 /* auto select appropriate template */
5236 memset (type
, 0, sizeof (type
));
5238 for (i
= 0; i
< n
; ++i
)
5240 type
[i
] = md
.slot
[curr
].idesc
->type
;
5241 curr
= (curr
+ 1) % NUM_SLOTS
;
5243 template = best_template
[type
[0]][type
[1]][type
[2]];
5246 /* initialize instructions with appropriate nops: */
5247 for (i
= 0; i
< 3; ++i
)
5248 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5252 /* now fill in slots with as many insns as possible: */
5254 idesc
= md
.slot
[curr
].idesc
;
5255 end_of_insn_group
= 0;
5256 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5258 /* Set the slot number for prologue/body records now as those
5259 refer to the current point, not the point after the
5260 instruction has been issued: */
5261 /* Don't try to delete prologue/body records here, as that will cause
5262 them to also be deleted from the master list of unwind records. */
5263 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5264 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
5265 || ptr
->r
.type
== body
)
5266 ptr
->slot_number
= (unsigned long) f
+ i
;
5268 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
5270 if (manual_bundling
&& i
!= 2)
5271 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5272 "`%s' must be last in bundle", idesc
->name
);
5276 if (idesc
->flags
& IA64_OPCODE_LAST
)
5278 int required_slot
, required_template
;
5280 /* If we need a stop bit after an M slot, our only choice is
5281 template 5 (M;;MI). If we need a stop bit after a B
5282 slot, our only choice is to place it at the end of the
5283 bundle, because the only available templates are MIB,
5284 MBB, BBB, MMB, and MFB. We don't handle anything other
5285 than M and B slots because these are the only kind of
5286 instructions that can have the IA64_OPCODE_LAST bit set. */
5287 required_template
= template;
5288 switch (idesc
->type
)
5292 required_template
= 5;
5300 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5301 "Internal error: don't know how to force %s to end"
5302 "of instruction group", idesc
->name
);
5306 if (manual_bundling
&& i
!= required_slot
)
5307 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5308 "`%s' must be last in instruction group",
5310 if (required_slot
< i
)
5311 /* Can't fit this instruction. */
5315 if (required_template
!= template)
5317 /* If we switch the template, we need to reset the NOPs
5318 after slot i. The slot-types of the instructions ahead
5319 of i never change, so we don't need to worry about
5320 changing NOPs in front of this slot. */
5321 for (j
= i
; j
< 3; ++j
)
5322 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
5324 template = required_template
;
5326 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
5328 if (manual_bundling_on
)
5329 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5330 "Label must be first in a bundle");
5331 /* This insn must go into the first slot of a bundle. */
5335 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
5336 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
5338 if (manual_bundling_on
)
5341 manual_bundling
= 1;
5343 break; /* need to start a new bundle */
5346 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
5348 /* We need an instruction group boundary in the middle of a
5349 bundle. See if we can switch to an other template with
5350 an appropriate boundary. */
5352 orig_template
= template;
5353 if (i
== 1 && (user_template
== 4
5354 || (user_template
< 0
5355 && (ia64_templ_desc
[template].exec_unit
[0]
5359 end_of_insn_group
= 0;
5361 else if (i
== 2 && (user_template
== 0
5362 || (user_template
< 0
5363 && (ia64_templ_desc
[template].exec_unit
[1]
5365 /* This test makes sure we don't switch the template if
5366 the next instruction is one that needs to be first in
5367 an instruction group. Since all those instructions are
5368 in the M group, there is no way such an instruction can
5369 fit in this bundle even if we switch the template. The
5370 reason we have to check for this is that otherwise we
5371 may end up generating "MI;;I M.." which has the deadly
5372 effect that the second M instruction is no longer the
5373 first in the bundle! --davidm 99/12/16 */
5374 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
5377 end_of_insn_group
= 0;
5379 else if (curr
!= first
)
5380 /* can't fit this insn */
5383 if (template != orig_template
)
5384 /* if we switch the template, we need to reset the NOPs
5385 after slot i. The slot-types of the instructions ahead
5386 of i never change, so we don't need to worry about
5387 changing NOPs in front of this slot. */
5388 for (j
= i
; j
< 3; ++j
)
5389 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
5391 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
5393 /* resolve dynamic opcodes such as "break" and "nop": */
5394 if (idesc
->type
== IA64_TYPE_DYN
)
5396 if ((strcmp (idesc
->name
, "nop") == 0)
5397 || (strcmp (idesc
->name
, "break") == 0))
5398 insn_unit
= required_unit
;
5399 else if (strcmp (idesc
->name
, "chk.s") == 0)
5401 insn_unit
= IA64_UNIT_M
;
5402 if (required_unit
== IA64_UNIT_I
)
5403 insn_unit
= IA64_UNIT_I
;
5406 as_fatal ("emit_one_bundle: unexpected dynamic op");
5408 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
5409 ia64_free_opcode (idesc
);
5410 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
5412 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
5417 insn_type
= idesc
->type
;
5418 insn_unit
= IA64_UNIT_NIL
;
5422 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
5423 insn_unit
= required_unit
;
5425 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
5426 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
5427 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
5428 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
5429 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
5434 if (insn_unit
!= required_unit
)
5436 if (required_unit
== IA64_UNIT_L
5437 && insn_unit
== IA64_UNIT_I
5438 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
5440 /* we got ourselves an MLX template but the current
5441 instruction isn't an X-unit, or an I-unit instruction
5442 that can go into the X slot of an MLX template. Duh. */
5443 if (md
.num_slots_in_use
>= NUM_SLOTS
)
5445 as_bad_where (md
.slot
[curr
].src_file
,
5446 md
.slot
[curr
].src_line
,
5447 "`%s' can't go in X slot of "
5448 "MLX template", idesc
->name
);
5449 /* drop this insn so we don't livelock: */
5450 --md
.num_slots_in_use
;
5454 continue; /* try next slot */
5457 if (debug_type
== DEBUG_DWARF2
)
5461 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + 1*i
;
5462 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
5465 build_insn (md
.slot
+ curr
, insn
+ i
);
5467 /* Set slot counts for non prologue/body unwind records. */
5468 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
5469 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
5470 && ptr
->r
.type
!= body
)
5471 ptr
->slot_number
= (unsigned long) f
+ i
;
5472 md
.slot
[curr
].unwind_record
= NULL
;
5473 unwind
.next_slot_number
= (unsigned long) f
+ i
+ ((i
== 2)?(0x10-2):1);
5475 if (required_unit
== IA64_UNIT_L
)
5478 /* skip one slot for long/X-unit instructions */
5481 --md
.num_slots_in_use
;
5483 /* now is a good time to fix up the labels for this insn: */
5484 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
5486 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
5487 symbol_set_frag (lfix
->sym
, frag_now
);
5490 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
5492 ifix
= md
.slot
[curr
].fixup
+ j
;
5493 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 4,
5494 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
5495 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
5496 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
5497 fix
->fx_file
= md
.slot
[curr
].src_file
;
5498 fix
->fx_line
= md
.slot
[curr
].src_line
;
5501 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
5504 ia64_free_opcode (md
.slot
[curr
].idesc
);
5505 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
5506 md
.slot
[curr
].user_template
= -1;
5508 if (manual_bundling_off
)
5510 manual_bundling
= 0;
5513 curr
= (curr
+ 1) % NUM_SLOTS
;
5514 idesc
= md
.slot
[curr
].idesc
;
5516 if (manual_bundling
)
5518 if (md
.num_slots_in_use
> 0)
5519 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5520 "`%s' does not fit into %s template",
5521 idesc
->name
, ia64_templ_desc
[template].name
);
5523 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
5524 "Missing '}' at end of file");
5526 know (md
.num_slots_in_use
< NUM_SLOTS
);
5528 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
5529 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
5531 md_number_to_chars (f
+ 0, t0
, 8);
5532 md_number_to_chars (f
+ 8, t1
, 8);
5536 md_parse_option (c
, arg
)
5542 /* Switches from the Intel assembler. */
5544 if (strcmp (arg
, "ilp64") == 0
5545 || strcmp (arg
, "lp64") == 0
5546 || strcmp (arg
, "p64") == 0)
5548 md
.flags
|= EF_IA_64_ABI64
;
5550 else if (strcmp (arg
, "ilp32") == 0)
5552 md
.flags
&= ~EF_IA_64_ABI64
;
5554 else if (strcmp (arg
, "le") == 0)
5556 md
.flags
&= ~EF_IA_64_BE
;
5558 else if (strcmp (arg
, "be") == 0)
5560 md
.flags
|= EF_IA_64_BE
;
5567 if (strcmp (arg
, "so") == 0)
5569 /* Suppress signon message. */
5571 else if (strcmp (arg
, "pi") == 0)
5573 /* Reject privileged instructions. FIXME */
5575 else if (strcmp (arg
, "us") == 0)
5577 /* Allow union of signed and unsigned range. FIXME */
5579 else if (strcmp (arg
, "close_fcalls") == 0)
5581 /* Do not resolve global function calls. */
5588 /* temp[="prefix"] Insert temporary labels into the object file
5589 symbol table prefixed by "prefix".
5590 Default prefix is ":temp:".
5595 /* ??? Conflicts with gas' listing option. */
5596 /* indirect=<tgt> Assume unannotated indirect branches behavior
5597 according to <tgt> --
5598 exit: branch out from the current context (default)
5599 labels: all labels in context may be branch targets
5604 /* -X conflicts with an ignored option, use -x instead */
5606 if (!arg
|| strcmp (arg
, "explicit") == 0)
5608 /* set default mode to explicit */
5609 md
.default_explicit_mode
= 1;
5612 else if (strcmp (arg
, "auto") == 0)
5614 md
.default_explicit_mode
= 0;
5616 else if (strcmp (arg
, "debug") == 0)
5620 else if (strcmp (arg
, "debugx") == 0)
5622 md
.default_explicit_mode
= 1;
5627 as_bad (_("Unrecognized option '-x%s'"), arg
);
5632 /* nops Print nops statistics. */
5635 /* GNU specific switches for gcc. */
5636 case OPTION_MCONSTANT_GP
:
5637 md
.flags
|= EF_IA_64_CONS_GP
;
5640 case OPTION_MAUTO_PIC
:
5641 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
5652 md_show_usage (stream
)
5657 -Milp32|-Milp64|-Mlp64|-Mp64 select data model (default -Mlp64)\n\
5658 -Mle | -Mbe select little- or big-endian byte order (default -Mle)\n\
5659 -x | -xexplicit turn on dependency violation checking (default)\n\
5660 -xauto automagically remove dependency violations\n\
5661 -xdebug debug dependency violation checker\n"),
5666 match (int templ
, int type
, int slot
)
5668 enum ia64_unit unit
;
5671 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
5674 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
5676 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
5678 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
5679 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
5680 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
5681 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
5682 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
5683 default: result
= 0; break;
5688 /* This function is called once, at assembler startup time. It sets
5689 up all the tables, etc. that the MD part of the assembler will need
5690 that can be determined before arguments are parsed. */
5694 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
;
5699 md
.explicit_mode
= md
.default_explicit_mode
;
5701 bfd_set_section_alignment (stdoutput
, text_section
, 4);
5703 target_big_endian
= 0;
5704 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
5705 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
5706 &zero_address_frag
);
5708 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
5709 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
5710 &zero_address_frag
);
5712 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
5713 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
5714 &zero_address_frag
);
5716 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
5717 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
5718 &zero_address_frag
);
5720 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
5721 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
5722 &zero_address_frag
);
5724 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
5725 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
5726 &zero_address_frag
);
5728 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
5729 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
5730 &zero_address_frag
);
5732 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
5733 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
5734 &zero_address_frag
);
5736 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
5737 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
5738 &zero_address_frag
);
5740 /* compute the table of best templates: */
5741 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
5742 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
5743 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
5746 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
5749 if (match (t
, i
, 0))
5751 if (match (t
, j
, 1))
5753 if (match (t
, k
, 2))
5758 else if (match (t
, j
, 2))
5763 else if (match (t
, i
, 1))
5765 if (match (t
, j
, 2))
5770 else if (match (t
, i
, 2))
5773 if (goodness
> best
)
5776 best_template
[i
][j
][k
] = t
;
5781 for (i
= 0; i
< NUM_SLOTS
; ++i
)
5782 md
.slot
[i
].user_template
= -1;
5784 md
.pseudo_hash
= hash_new ();
5785 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
5787 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
5788 (void *) (pseudo_opcode
+ i
));
5790 as_fatal ("ia64.md_begin: can't hash `%s': %s",
5791 pseudo_opcode
[i
].name
, err
);
5794 md
.reg_hash
= hash_new ();
5795 md
.dynreg_hash
= hash_new ();
5796 md
.const_hash
= hash_new ();
5797 md
.entry_hash
= hash_new ();
5799 /* general registers: */
5802 for (i
= 0; i
< total
; ++i
)
5804 sprintf (name
, "r%d", i
- REG_GR
);
5805 md
.regsym
[i
] = declare_register (name
, i
);
5808 /* floating point registers: */
5810 for (; i
< total
; ++i
)
5812 sprintf (name
, "f%d", i
- REG_FR
);
5813 md
.regsym
[i
] = declare_register (name
, i
);
5816 /* application registers: */
5819 for (; i
< total
; ++i
)
5821 sprintf (name
, "ar%d", i
- REG_AR
);
5822 md
.regsym
[i
] = declare_register (name
, i
);
5825 /* control registers: */
5828 for (; i
< total
; ++i
)
5830 sprintf (name
, "cr%d", i
- REG_CR
);
5831 md
.regsym
[i
] = declare_register (name
, i
);
5834 /* predicate registers: */
5836 for (; i
< total
; ++i
)
5838 sprintf (name
, "p%d", i
- REG_P
);
5839 md
.regsym
[i
] = declare_register (name
, i
);
5842 /* branch registers: */
5844 for (; i
< total
; ++i
)
5846 sprintf (name
, "b%d", i
- REG_BR
);
5847 md
.regsym
[i
] = declare_register (name
, i
);
5850 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
5851 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
5852 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
5853 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
5854 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
5855 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
5856 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
5858 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
5860 regnum
= indirect_reg
[i
].regnum
;
5861 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
5864 /* define synonyms for application registers: */
5865 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
5866 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
5867 REG_AR
+ ar
[i
- REG_AR
].regnum
);
5869 /* define synonyms for control registers: */
5870 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
5871 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
5872 REG_CR
+ cr
[i
- REG_CR
].regnum
);
5874 declare_register ("gp", REG_GR
+ 1);
5875 declare_register ("sp", REG_GR
+ 12);
5876 declare_register ("rp", REG_BR
+ 0);
5878 /* pseudo-registers used to specify unwind info: */
5879 declare_register ("psp", REG_PSP
);
5881 declare_register_set ("ret", 4, REG_GR
+ 8);
5882 declare_register_set ("farg", 8, REG_FR
+ 8);
5883 declare_register_set ("fret", 8, REG_FR
+ 8);
5885 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
5887 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
5888 (PTR
) (const_bits
+ i
));
5890 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
5894 /* Default to 64-bit mode. */
5895 /* ??? This overrides the -M options, but they aren't working anyways. */
5896 md
.flags
|= EF_IA_64_ABI64
;
5898 md
.mem_offset
.hint
= 0;
5901 md
.entry_labels
= NULL
;
5905 ia64_end_of_source ()
5907 /* terminate insn group upon reaching end of file: */
5908 insn_group_break (1, 0, 0);
5910 /* emits slots we haven't written yet: */
5911 ia64_flush_insns ();
5913 bfd_set_private_flags (stdoutput
, md
.flags
);
5915 if (debug_type
== DEBUG_DWARF2
)
5918 md
.mem_offset
.hint
= 0;
5924 md
.qp
.X_op
= O_absent
;
5926 if (ignore_input ())
5929 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
5931 if (md
.detect_dv
&& !md
.explicit_mode
)
5932 as_warn (_("Explicit stops are ignored in auto mode"));
5934 insn_group_break (1, 0, 0);
5939 ia64_unrecognized_line (ch
)
5945 expression (&md
.qp
);
5946 if (*input_line_pointer
++ != ')')
5948 as_bad ("Expected ')'");
5951 if (md
.qp
.X_op
!= O_register
)
5953 as_bad ("Qualifying predicate expected");
5956 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
5958 as_bad ("Predicate register expected");
5964 if (md
.manual_bundling
)
5965 as_warn ("Found '{' when manual bundling is already turned on");
5967 CURR_SLOT
.manual_bundling_on
= 1;
5968 md
.manual_bundling
= 1;
5970 /* bundling is only acceptable in explicit mode
5971 or when in default automatic mode */
5972 if (md
.detect_dv
&& !md
.explicit_mode
)
5974 if (!md
.mode_explicitly_set
5975 && !md
.default_explicit_mode
)
5978 as_warn (_("Found '{' after explicit switch to automatic mode"));
5983 if (!md
.manual_bundling
)
5984 as_warn ("Found '}' when manual bundling is off");
5986 PREV_SLOT
.manual_bundling_off
= 1;
5987 md
.manual_bundling
= 0;
5989 /* switch back to automatic mode, if applicable */
5992 && !md
.mode_explicitly_set
5993 && !md
.default_explicit_mode
)
5996 /* Allow '{' to follow on the same line. We also allow ";;", but that
5997 happens automatically because ';' is an end of line marker. */
5999 if (input_line_pointer
[0] == '{')
6001 input_line_pointer
++;
6002 return ia64_unrecognized_line ('{');
6005 demand_empty_rest_of_line ();
6011 return 0; /* not a valid line */
6015 ia64_frob_label (sym
)
6018 struct label_fix
*fix
;
6020 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6022 md
.last_text_seg
= now_seg
;
6023 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6025 fix
->next
= CURR_SLOT
.label_fixups
;
6026 CURR_SLOT
.label_fixups
= fix
;
6028 /* keep track of how many code entry points we've seen */
6029 if (md
.path
== md
.maxpaths
)
6032 md
.entry_labels
= (const char **)
6033 xrealloc ((void *)md
.entry_labels
, md
.maxpaths
* sizeof (char *));
6035 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6040 ia64_flush_pending_output ()
6042 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6044 /* ??? This causes many unnecessary stop bits to be emitted.
6045 Unfortunately, it isn't clear if it is safe to remove this. */
6046 insn_group_break (1, 0, 0);
6047 ia64_flush_insns ();
6051 /* Do ia64-specific expression optimization. All that's done here is
6052 to transform index expressions that are either due to the indexing
6053 of rotating registers or due to the indexing of indirect register
6056 ia64_optimize_expr (l
, op
, r
)
6065 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
6067 num_regs
= (l
->X_add_number
>> 16);
6068 if ((unsigned) r
->X_add_number
>= num_regs
)
6071 as_bad ("No current frame");
6073 as_bad ("Index out of range 0..%u", num_regs
- 1);
6074 r
->X_add_number
= 0;
6076 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
6079 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
6081 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
6082 || l
->X_add_number
== IND_MEM
)
6084 as_bad ("Indirect register set name expected");
6085 l
->X_add_number
= IND_CPUID
;
6088 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
6089 l
->X_add_number
= r
->X_add_number
;
6097 ia64_parse_name (name
, e
)
6101 struct const_desc
*cdesc
;
6102 struct dynreg
*dr
= 0;
6103 unsigned int regnum
;
6107 /* first see if NAME is a known register name: */
6108 sym
= hash_find (md
.reg_hash
, name
);
6111 e
->X_op
= O_register
;
6112 e
->X_add_number
= S_GET_VALUE (sym
);
6116 cdesc
= hash_find (md
.const_hash
, name
);
6119 e
->X_op
= O_constant
;
6120 e
->X_add_number
= cdesc
->value
;
6124 /* check for inN, locN, or outN: */
6128 if (name
[1] == 'n' && isdigit (name
[2]))
6136 if (name
[1] == 'o' && name
[2] == 'c' && isdigit (name
[3]))
6144 if (name
[1] == 'u' && name
[2] == 't' && isdigit (name
[3]))
6157 /* the name is inN, locN, or outN; parse the register number: */
6158 regnum
= strtoul (name
, &end
, 10);
6159 if (end
> name
&& *end
== '\0')
6161 if ((unsigned) regnum
>= dr
->num_regs
)
6164 as_bad ("No current frame");
6166 as_bad ("Register number out of range 0..%u", dr
->num_regs
-1);
6169 e
->X_op
= O_register
;
6170 e
->X_add_number
= dr
->base
+ regnum
;
6175 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
6177 /* We've got ourselves the name of a rotating register set.
6178 Store the base register number in the low 16 bits of
6179 X_add_number and the size of the register set in the top 16
6181 e
->X_op
= O_register
;
6182 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
6188 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
6191 ia64_canonicalize_symbol_name (name
)
6194 size_t len
= strlen(name
);
6195 if (len
> 1 && name
[len
-1] == '#')
6201 is_conditional_branch (idesc
)
6202 struct ia64_opcode
*idesc
;
6204 return (strncmp (idesc
->name
, "br", 2) == 0
6205 && (strcmp (idesc
->name
, "br") == 0
6206 || strncmp (idesc
->name
, "br.cond", 7) == 0
6207 || strncmp (idesc
->name
, "br.call", 7) == 0
6208 || strncmp (idesc
->name
, "br.ret", 6) == 0
6209 || strcmp (idesc
->name
, "brl") == 0
6210 || strncmp (idesc
->name
, "brl.cond", 7) == 0
6211 || strncmp (idesc
->name
, "brl.call", 7) == 0
6212 || strncmp (idesc
->name
, "brl.ret", 6) == 0));
6215 /* Return whether the given opcode is a taken branch. If there's any doubt,
6218 is_taken_branch (idesc
)
6219 struct ia64_opcode
*idesc
;
6221 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
6222 || strncmp (idesc
->name
, "br.ia", 5) == 0);
6225 /* Return whether the given opcode is an interruption or rfi. If there's any
6226 doubt, returns zero */
6228 is_interruption_or_rfi (idesc
)
6229 struct ia64_opcode
*idesc
;
6231 if (strcmp (idesc
->name
, "rfi") == 0)
6236 /* Returns the index of the given dependency in the opcode's list of chks, or
6237 -1 if there is no dependency. */
6239 depends_on (depind
, idesc
)
6241 struct ia64_opcode
*idesc
;
6244 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
6245 for (i
= 0;i
< dep
->nchks
; i
++)
6247 if (depind
== DEP(dep
->chks
[i
]))
6253 /* Determine a set of specific resources used for a particular resource
6254 class. Returns the number of specific resources identified For those
6255 cases which are not determinable statically, the resource returned is
6258 Meanings of value in 'NOTE':
6259 1) only read/write when the register number is explicitly encoded in the
6261 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
6262 accesses CFM when qualifying predicate is in the rotating region.
6263 3) general register value is used to specify an indirect register; not
6264 determinable statically.
6265 4) only read the given resource when bits 7:0 of the indirect index
6266 register value does not match the register number of the resource; not
6267 determinable statically.
6268 5) all rules are implementation specific.
6269 6) only when both the index specified by the reader and the index specified
6270 by the writer have the same value in bits 63:61; not determinable
6272 7) only access the specified resource when the corresponding mask bit is
6274 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
6275 only read when these insns reference FR2-31
6276 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
6277 written when these insns write FR32-127
6278 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
6280 11) The target predicates are written independently of PR[qp], but source
6281 registers are only read if PR[qp] is true. Since the state of PR[qp]
6282 cannot statically be determined, all source registers are marked used.
6283 12) This insn only reads the specified predicate register when that
6284 register is the PR[qp].
6285 13) This reference to ld-c only applies to teh GR whose value is loaded
6286 with data returned from memory, not the post-incremented address register.
6287 14) The RSE resource includes the implementation-specific RSE internal
6288 state resources. At least one (and possibly more) of these resources are
6289 read by each instruction listed in IC:rse-readers. At least one (and
6290 possibly more) of these resources are written by each insn listed in
6292 15+16) Represents reserved instructions, which the assembler does not
6295 Memory resources (i.e. locations in memory) are *not* marked or tracked by
6296 this code; there are no dependency violations based on memory access.
6300 #define MAX_SPECS 256
6305 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
6306 const struct ia64_dependency
*dep
;
6307 struct ia64_opcode
*idesc
;
6308 int type
; /* is this a DV chk or a DV reg? */
6309 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
6310 int note
; /* resource note for this insn's usage */
6311 int path
; /* which execution path to examine */
6318 if (dep
->mode
== IA64_DV_WAW
6319 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
6320 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
6323 /* template for any resources we identify */
6324 tmpl
.dependency
= dep
;
6326 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
6327 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
6328 tmpl
.link_to_qp_branch
= 1;
6329 tmpl
.mem_offset
.hint
= 0;
6334 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
6335 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
6336 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
6338 /* we don't need to track these */
6339 if (dep
->semantics
== IA64_DVS_NONE
)
6342 switch (dep
->specifier
)
6347 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6349 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6350 if (regno
>= 0 && regno
<= 7)
6352 specs
[count
] = tmpl
;
6353 specs
[count
++].index
= regno
;
6361 specs
[count
] = tmpl
;
6362 specs
[count
++].index
= i
;
6371 case IA64_RS_AR_UNAT
:
6372 /* This is a mov =AR or mov AR= instruction. */
6373 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6375 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6376 if (regno
== AR_UNAT
)
6378 specs
[count
++] = tmpl
;
6383 /* This is a spill/fill, or other instruction that modifies the
6386 /* Unless we can determine the specific bits used, mark the whole
6387 thing; bits 8:3 of the memory address indicate the bit used in
6388 UNAT. The .mem.offset hint may be used to eliminate a small
6389 subset of conflicts. */
6390 specs
[count
] = tmpl
;
6391 if (md
.mem_offset
.hint
)
6394 fprintf (stderr
, " Using hint for spill/fill\n");
6395 /* the index isn't actually used, just set it to something
6396 approximating the bit index */
6397 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
6398 specs
[count
].mem_offset
.hint
= 1;
6399 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
6400 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
6404 specs
[count
++].specific
= 0;
6412 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6414 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6415 if ((regno
>= 8 && regno
<= 15)
6416 || (regno
>= 20 && regno
<= 23)
6417 || (regno
>= 31 && regno
<= 39)
6418 || (regno
>= 41 && regno
<= 47)
6419 || (regno
>= 67 && regno
<= 111))
6421 specs
[count
] = tmpl
;
6422 specs
[count
++].index
= regno
;
6435 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
6437 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
6438 if ((regno
>= 48 && regno
<= 63)
6439 || (regno
>= 112 && regno
<= 127))
6441 specs
[count
] = tmpl
;
6442 specs
[count
++].index
= regno
;
6448 for (i
=48;i
< 64;i
++)
6450 specs
[count
] = tmpl
;
6451 specs
[count
++].index
= i
;
6453 for (i
=112;i
< 128;i
++)
6455 specs
[count
] = tmpl
;
6456 specs
[count
++].index
= i
;
6474 for (i
=0;i
< idesc
->num_outputs
;i
++)
6475 if (idesc
->operands
[i
] == IA64_OPND_B1
6476 || idesc
->operands
[i
] == IA64_OPND_B2
)
6478 specs
[count
] = tmpl
;
6479 specs
[count
++].index
=
6480 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6485 for (i
= idesc
->num_outputs
;i
< NELEMS(idesc
->operands
);i
++)
6486 if (idesc
->operands
[i
] == IA64_OPND_B1
6487 || idesc
->operands
[i
] == IA64_OPND_B2
)
6489 specs
[count
] = tmpl
;
6490 specs
[count
++].index
=
6491 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
6497 case IA64_RS_CPUID
: /* four or more registers */
6500 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
6502 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6503 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6506 specs
[count
] = tmpl
;
6507 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6511 specs
[count
] = tmpl
;
6512 specs
[count
++].specific
= 0;
6522 case IA64_RS_DBR
: /* four or more registers */
6525 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
6527 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6528 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6531 specs
[count
] = tmpl
;
6532 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6536 specs
[count
] = tmpl
;
6537 specs
[count
++].specific
= 0;
6541 else if (note
== 0 && !rsrc_write
)
6543 specs
[count
] = tmpl
;
6544 specs
[count
++].specific
= 0;
6552 case IA64_RS_IBR
: /* four or more registers */
6555 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
6557 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6558 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6561 specs
[count
] = tmpl
;
6562 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6566 specs
[count
] = tmpl
;
6567 specs
[count
++].specific
= 0;
6580 /* These are implementation specific. Force all references to
6581 conflict with all other references. */
6582 specs
[count
] = tmpl
;
6583 specs
[count
++].specific
= 0;
6591 case IA64_RS_PKR
: /* 16 or more registers */
6592 if (note
== 3 || note
== 4)
6594 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
6596 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6597 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6602 specs
[count
] = tmpl
;
6603 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6605 else for (i
=0;i
< NELEMS(gr_values
);i
++)
6607 /* uses all registers *except* the one in R3 */
6608 if (i
!= (gr_values
[regno
].value
& 0xFF))
6610 specs
[count
] = tmpl
;
6611 specs
[count
++].index
= i
;
6617 specs
[count
] = tmpl
;
6618 specs
[count
++].specific
= 0;
6625 specs
[count
] = tmpl
;
6626 specs
[count
++].specific
= 0;
6630 case IA64_RS_PMC
: /* four or more registers */
6633 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
6634 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
6637 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
6639 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
6640 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6643 specs
[count
] = tmpl
;
6644 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6648 specs
[count
] = tmpl
;
6649 specs
[count
++].specific
= 0;
6659 case IA64_RS_PMD
: /* four or more registers */
6662 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
6664 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6665 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6668 specs
[count
] = tmpl
;
6669 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
6673 specs
[count
] = tmpl
;
6674 specs
[count
++].specific
= 0;
6684 case IA64_RS_RR
: /* eight registers */
6687 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
6689 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
6690 if (regno
>= 0 && regno
< NELEMS(gr_values
)
6693 specs
[count
] = tmpl
;
6694 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
6698 specs
[count
] = tmpl
;
6699 specs
[count
++].specific
= 0;
6703 else if (note
== 0 && !rsrc_write
)
6705 specs
[count
] = tmpl
;
6706 specs
[count
++].specific
= 0;
6714 case IA64_RS_CR_IRR
:
6717 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
6718 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
6720 && idesc
->operands
[1] == IA64_OPND_CR3
6725 specs
[count
] = tmpl
;
6726 specs
[count
++].index
= CR_IRR0
+ i
;
6732 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6733 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
6735 && regno
<= CR_IRR3
)
6737 specs
[count
] = tmpl
;
6738 specs
[count
++].index
= regno
;
6747 case IA64_RS_CR_LRR
:
6754 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6755 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
6756 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
6758 specs
[count
] = tmpl
;
6759 specs
[count
++].index
= regno
;
6767 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
6769 specs
[count
] = tmpl
;
6770 specs
[count
++].index
=
6771 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
6786 else if (rsrc_write
)
6788 if (dep
->specifier
== IA64_RS_FRb
6789 && idesc
->operands
[0] == IA64_OPND_F1
)
6791 specs
[count
] = tmpl
;
6792 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
6797 for (i
=idesc
->num_outputs
;i
< NELEMS(idesc
->operands
);i
++)
6799 if (idesc
->operands
[i
] == IA64_OPND_F2
6800 || idesc
->operands
[i
] == IA64_OPND_F3
6801 || idesc
->operands
[i
] == IA64_OPND_F4
)
6803 specs
[count
] = tmpl
;
6804 specs
[count
++].index
=
6805 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
6814 /* This reference applies only to the GR whose value is loaded with
6815 data returned from memory */
6816 specs
[count
] = tmpl
;
6817 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
6823 for (i
= 0; i
< idesc
->num_outputs
; i
++)
6824 if (idesc
->operands
[i
] == IA64_OPND_R1
6825 || idesc
->operands
[i
] == IA64_OPND_R2
6826 || idesc
->operands
[i
] == IA64_OPND_R3
)
6828 specs
[count
] = tmpl
;
6829 specs
[count
++].index
=
6830 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6832 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
6833 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
6834 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
6836 specs
[count
] = tmpl
;
6837 specs
[count
++].index
=
6838 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6843 /* Look for anything that reads a GR */
6844 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
6846 if (idesc
->operands
[i
] == IA64_OPND_MR3
6847 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
6848 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
6849 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
6850 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
6851 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
6852 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
6853 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
6854 || idesc
->operands
[i
] == IA64_OPND_RR_R3
6855 || ((i
>= idesc
->num_outputs
)
6856 && (idesc
->operands
[i
] == IA64_OPND_R1
6857 || idesc
->operands
[i
] == IA64_OPND_R2
6858 || idesc
->operands
[i
] == IA64_OPND_R3
6859 /* addl source register. */
6860 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
6862 specs
[count
] = tmpl
;
6863 specs
[count
++].index
=
6864 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
6878 if (idesc
->operands
[0] == IA64_OPND_PR_ROT
)
6880 for (i
=16;i
< 63;i
++)
6882 specs
[count
] = tmpl
;
6883 specs
[count
++].index
= i
;
6888 for (i
=1;i
< 63;i
++)
6890 specs
[count
] = tmpl
;
6891 specs
[count
++].index
= i
;
6898 /* mark only those registers indicated by the mask */
6900 && idesc
->operands
[0] == IA64_OPND_PR
)
6902 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
6903 if (mask
& ((valueT
)1<<16))
6904 mask
|= ~(valueT
)0xffff;
6905 for (i
=1;i
< 63;i
++)
6907 if (mask
& ((valueT
)1<<i
))
6909 specs
[count
] = tmpl
;
6910 specs
[count
++].index
= i
;
6915 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
6917 for (i
=16;i
< 63;i
++)
6919 specs
[count
] = tmpl
;
6920 specs
[count
++].index
= i
;
6928 else if (note
== 11) /* note 11 implies note 1 as well */
6932 for (i
=0;i
< idesc
->num_outputs
;i
++)
6934 if (idesc
->operands
[i
] == IA64_OPND_P1
6935 || idesc
->operands
[i
] == IA64_OPND_P2
)
6937 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
6940 specs
[count
] = tmpl
;
6941 specs
[count
++].index
= regno
;
6951 else if (note
== 12)
6953 if (CURR_SLOT
.qp_regno
!= 0)
6955 specs
[count
] = tmpl
;
6956 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
6963 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
6964 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
6965 if ((idesc
->operands
[0] == IA64_OPND_P1
6966 || idesc
->operands
[0] == IA64_OPND_P2
)
6967 && p1
!= 0 && p1
!= 63)
6969 specs
[count
] = tmpl
;
6970 specs
[count
++].index
= p1
;
6972 if ((idesc
->operands
[1] == IA64_OPND_P1
6973 || idesc
->operands
[1] == IA64_OPND_P2
)
6974 && p2
!= 0 && p2
!= 63)
6976 specs
[count
] = tmpl
;
6977 specs
[count
++].index
= p2
;
6982 if (CURR_SLOT
.qp_regno
!= 0)
6984 specs
[count
] = tmpl
;
6985 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
6987 if (idesc
->operands
[1] == IA64_OPND_PR
)
6989 for (i
=1;i
< 63;i
++)
6991 specs
[count
] = tmpl
;
6992 specs
[count
++].index
= i
;
7004 /* Verify that the instruction is using the PSR bit indicated in
7008 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
7010 if (dep
->regindex
< 6)
7012 specs
[count
++] = tmpl
;
7015 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
7017 if (dep
->regindex
< 32
7018 || dep
->regindex
== 35
7019 || dep
->regindex
== 36
7020 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
7022 specs
[count
++] = tmpl
;
7025 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
7027 if (dep
->regindex
< 32
7028 || dep
->regindex
== 35
7029 || dep
->regindex
== 36
7030 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
7032 specs
[count
++] = tmpl
;
7037 /* Several PSR bits have very specific dependencies. */
7038 switch (dep
->regindex
)
7041 specs
[count
++] = tmpl
;
7046 specs
[count
++] = tmpl
;
7050 /* Only certain CR accesses use PSR.ic */
7051 if (idesc
->operands
[0] == IA64_OPND_CR3
7052 || idesc
->operands
[1] == IA64_OPND_CR3
)
7055 ((idesc
->operands
[0] == IA64_OPND_CR3
)
7058 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
7073 specs
[count
++] = tmpl
;
7082 specs
[count
++] = tmpl
;
7086 /* Only some AR accesses use cpl */
7087 if (idesc
->operands
[0] == IA64_OPND_AR3
7088 || idesc
->operands
[1] == IA64_OPND_AR3
)
7091 ((idesc
->operands
[0] == IA64_OPND_AR3
)
7094 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
7101 && regno
<= AR_K7
))))
7103 specs
[count
++] = tmpl
;
7108 specs
[count
++] = tmpl
;
7118 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
7120 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
7126 if (mask
& ((valueT
)1<<dep
->regindex
))
7128 specs
[count
++] = tmpl
;
7133 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
7134 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
7135 /* dfh is read on FR32-127; dfl is read on FR2-31 */
7136 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7138 if (idesc
->operands
[i
] == IA64_OPND_F1
7139 || idesc
->operands
[i
] == IA64_OPND_F2
7140 || idesc
->operands
[i
] == IA64_OPND_F3
7141 || idesc
->operands
[i
] == IA64_OPND_F4
)
7143 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7144 if (reg
>= min
&& reg
<= max
)
7146 specs
[count
++] = tmpl
;
7153 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
7154 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
7155 /* mfh is read on writes to FR32-127; mfl is read on writes to
7157 for (i
=0;i
< idesc
->num_outputs
;i
++)
7159 if (idesc
->operands
[i
] == IA64_OPND_F1
)
7161 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7162 if (reg
>= min
&& reg
<= max
)
7164 specs
[count
++] = tmpl
;
7169 else if (note
== 10)
7171 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7173 if (idesc
->operands
[i
] == IA64_OPND_R1
7174 || idesc
->operands
[i
] == IA64_OPND_R2
7175 || idesc
->operands
[i
] == IA64_OPND_R3
)
7177 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7178 if (regno
>= 16 && regno
<= 31)
7180 specs
[count
++] = tmpl
;
7191 case IA64_RS_AR_FPSR
:
7192 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7194 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7195 if (regno
== AR_FPSR
)
7197 specs
[count
++] = tmpl
;
7202 specs
[count
++] = tmpl
;
7207 /* Handle all AR[REG] resources */
7208 if (note
== 0 || note
== 1)
7210 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7211 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
7212 && regno
== dep
->regindex
)
7214 specs
[count
++] = tmpl
;
7216 /* other AR[REG] resources may be affected by AR accesses */
7217 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
7220 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
7221 switch (dep
->regindex
)
7227 if (regno
== AR_BSPSTORE
)
7229 specs
[count
++] = tmpl
;
7233 (regno
== AR_BSPSTORE
7234 || regno
== AR_RNAT
))
7236 specs
[count
++] = tmpl
;
7241 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7244 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
7245 switch (dep
->regindex
)
7250 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
7252 specs
[count
++] = tmpl
;
7259 specs
[count
++] = tmpl
;
7269 /* Handle all CR[REG] resources */
7270 if (note
== 0 || note
== 1)
7272 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7274 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7275 if (regno
== dep
->regindex
)
7277 specs
[count
++] = tmpl
;
7279 else if (!rsrc_write
)
7281 /* Reads from CR[IVR] affect other resources. */
7282 if (regno
== CR_IVR
)
7284 if ((dep
->regindex
>= CR_IRR0
7285 && dep
->regindex
<= CR_IRR3
)
7286 || dep
->regindex
== CR_TPR
)
7288 specs
[count
++] = tmpl
;
7295 specs
[count
++] = tmpl
;
7304 case IA64_RS_INSERVICE
:
7305 /* look for write of EOI (67) or read of IVR (65) */
7306 if ((idesc
->operands
[0] == IA64_OPND_CR3
7307 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
7308 || (idesc
->operands
[1] == IA64_OPND_CR3
7309 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
7311 specs
[count
++] = tmpl
;
7318 specs
[count
++] = tmpl
;
7329 specs
[count
++] = tmpl
;
7333 /* Check if any of the registers accessed are in the rotating region.
7334 mov to/from pr accesses CFM only when qp_regno is in the rotating
7336 for (i
=0;i
< NELEMS(idesc
->operands
);i
++)
7338 if (idesc
->operands
[i
] == IA64_OPND_R1
7339 || idesc
->operands
[i
] == IA64_OPND_R2
7340 || idesc
->operands
[i
] == IA64_OPND_R3
)
7342 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7343 /* Assumes that md.rot.num_regs is always valid */
7344 if (md
.rot
.num_regs
> 0
7346 && num
< 31 + md
.rot
.num_regs
)
7348 specs
[count
] = tmpl
;
7349 specs
[count
++].specific
= 0;
7352 else if (idesc
->operands
[i
] == IA64_OPND_F1
7353 || idesc
->operands
[i
] == IA64_OPND_F2
7354 || idesc
->operands
[i
] == IA64_OPND_F3
7355 || idesc
->operands
[i
] == IA64_OPND_F4
)
7357 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7360 specs
[count
] = tmpl
;
7361 specs
[count
++].specific
= 0;
7364 else if (idesc
->operands
[i
] == IA64_OPND_P1
7365 || idesc
->operands
[i
] == IA64_OPND_P2
)
7367 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7370 specs
[count
] = tmpl
;
7371 specs
[count
++].specific
= 0;
7375 if (CURR_SLOT
.qp_regno
> 15)
7377 specs
[count
] = tmpl
;
7378 specs
[count
++].specific
= 0;
7386 specs
[count
++] = tmpl
;
7388 else if (note
== 11)
7390 if ((idesc
->operands
[0] == IA64_OPND_P1
7391 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
7392 || (idesc
->operands
[1] == IA64_OPND_P2
7393 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
7395 specs
[count
++] = tmpl
;
7398 else if (note
== 12)
7400 if (CURR_SLOT
.qp_regno
== 63)
7402 specs
[count
++] = tmpl
;
7408 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
7409 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7410 if (mask
& ((valueT
)1<<63))
7412 specs
[count
++] = tmpl
;
7419 for (i
=0;i
< idesc
->num_outputs
;i
++)
7420 if ((idesc
->operands
[i
] == IA64_OPND_P1
7421 || idesc
->operands
[i
] == IA64_OPND_P2
)
7422 && CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
== 63)
7424 specs
[count
++] = tmpl
;
7429 if (CURR_SLOT
.qp_regno
== 63)
7431 specs
[count
++] = tmpl
;
7442 /* FIXME we can identify some individual RSE written resources, but RSE
7443 read resources have not yet been completely identified, so for now
7444 treat RSE as a single resource */
7445 if (strncmp (idesc
->name
, "mov", 3) == 0)
7449 if (idesc
->operands
[0] == IA64_OPND_AR3
7450 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
7452 specs
[count
] = tmpl
;
7453 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
7458 if (idesc
->operands
[0] == IA64_OPND_AR3
)
7460 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
7461 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
7463 specs
[count
++] = tmpl
;
7466 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
7468 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
7469 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
7470 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
7472 specs
[count
++] = tmpl
;
7479 specs
[count
++] = tmpl
;
7484 /* FIXME -- do any of these need to be non-specific? */
7485 specs
[count
++] = tmpl
;
7489 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
7496 /* Clear branch flags on marked resources. This breaks the link between the
7497 QP of the marking instruction and a subsequent branch on the same QP.
7500 clear_qp_branch_flag (mask
)
7504 for (i
= 0;i
< regdepslen
;i
++)
7506 valueT bit
= ((valueT
)1 << regdeps
[i
].qp_regno
);
7507 if ((bit
& mask
) != 0)
7509 regdeps
[i
].link_to_qp_branch
= 0;
7514 /* Remove any mutexes which contain any of the PRs indicated in the mask.
7516 Any changes to a PR clears the mutex relations which include that PR.
7519 clear_qp_mutex (mask
)
7525 while (i
< qp_mutexeslen
)
7527 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
7531 fprintf (stderr
, " Clearing mutex relation");
7532 print_prmask (qp_mutexes
[i
].prmask
);
7533 fprintf (stderr
, "\n");
7535 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
7542 /* Clear implies relations which contain PRs in the given masks.
7543 P1_MASK indicates the source of the implies relation, while P2_MASK
7544 indicates the implied PR.
7547 clear_qp_implies (p1_mask
, p2_mask
)
7554 while (i
< qp_implieslen
)
7556 if ((((valueT
)1 << qp_implies
[i
].p1
) & p1_mask
) != 0
7557 || (((valueT
)1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
7560 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
7561 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
7562 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
7569 /* add the PRs specified to the list of implied relations */
7571 add_qp_imply (p1
, p2
)
7578 /* p0 is not meaningful here */
7579 if (p1
== 0 || p2
== 0)
7585 /* if it exists already, ignore it */
7586 for (i
=0;i
< qp_implieslen
;i
++)
7588 if (qp_implies
[i
].p1
== p1
7589 && qp_implies
[i
].p2
== p2
7590 && qp_implies
[i
].path
== md
.path
7591 && !qp_implies
[i
].p2_branched
)
7595 if (qp_implieslen
== qp_impliestotlen
)
7597 qp_impliestotlen
+= 20;
7598 qp_implies
= (struct qp_imply
*)
7599 xrealloc ((void *)qp_implies
,
7600 qp_impliestotlen
* sizeof (struct qp_imply
));
7603 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
7604 qp_implies
[qp_implieslen
].p1
= p1
;
7605 qp_implies
[qp_implieslen
].p2
= p2
;
7606 qp_implies
[qp_implieslen
].path
= md
.path
;
7607 qp_implies
[qp_implieslen
++].p2_branched
= 0;
7609 /* Add in the implied transitive relations; for everything that p2 implies,
7610 make p1 imply that, too; for everything that implies p1, make it imply p2
7612 for (i
=0;i
< qp_implieslen
;i
++)
7614 if (qp_implies
[i
].p1
== p2
)
7615 add_qp_imply (p1
, qp_implies
[i
].p2
);
7616 if (qp_implies
[i
].p2
== p1
)
7617 add_qp_imply (qp_implies
[i
].p1
, p2
);
7619 /* Add in mutex relations implied by this implies relation; for each mutex
7620 relation containing p2, duplicate it and replace p2 with p1. */
7621 bit
= (valueT
)1 << p1
;
7622 mask
= (valueT
)1 << p2
;
7623 for (i
=0;i
< qp_mutexeslen
;i
++)
7625 if (qp_mutexes
[i
].prmask
& mask
)
7626 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
7631 /* Add the PRs specified in the mask to the mutex list; this means that only
7632 one of the PRs can be true at any time. PR0 should never be included in
7641 if (qp_mutexeslen
== qp_mutexestotlen
)
7643 qp_mutexestotlen
+= 20;
7644 qp_mutexes
= (struct qpmutex
*)
7645 xrealloc ((void *)qp_mutexes
,
7646 qp_mutexestotlen
* sizeof (struct qpmutex
));
7650 fprintf (stderr
, " Registering mutex on");
7651 print_prmask (mask
);
7652 fprintf (stderr
, "\n");
7654 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
7655 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
7659 clear_register_values ()
7663 fprintf (stderr
, " Clearing register values\n");
7664 for (i
=1;i
< NELEMS(gr_values
);i
++)
7665 gr_values
[i
].known
= 0;
7668 /* Keep track of register values/changes which affect DV tracking.
7670 optimization note: should add a flag to classes of insns where otherwise we
7671 have to examine a group of strings to identify them.
7675 note_register_values (idesc
)
7676 struct ia64_opcode
*idesc
;
7678 valueT qp_changemask
= 0;
7681 /* invalidate values for registers being written to */
7682 for (i
=0;i
< idesc
->num_outputs
;i
++)
7684 if (idesc
->operands
[i
] == IA64_OPND_R1
7685 || idesc
->operands
[i
] == IA64_OPND_R2
7686 || idesc
->operands
[i
] == IA64_OPND_R3
)
7688 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7689 if (regno
> 0 && regno
< NELEMS(gr_values
))
7690 gr_values
[regno
].known
= 0;
7692 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
7694 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7695 if (regno
> 0 && regno
< 4)
7696 gr_values
[regno
].known
= 0;
7698 else if (idesc
->operands
[i
] == IA64_OPND_P1
7699 || idesc
->operands
[i
] == IA64_OPND_P2
)
7701 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7702 qp_changemask
|= (valueT
)1 << regno
;
7704 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
7706 if (idesc
->operands
[2] & (valueT
)0x10000)
7707 qp_changemask
= ~(valueT
)0x1FFFF | idesc
->operands
[2];
7709 qp_changemask
= idesc
->operands
[2];
7712 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
7714 if (idesc
->operands
[1] & ((valueT
)1 << 43))
7715 qp_changemask
= ~(valueT
)0xFFFFFFFFFFF | idesc
->operands
[1];
7717 qp_changemask
= idesc
->operands
[1];
7718 qp_changemask
&= ~(valueT
)0xFFFF;
7723 /* Always clear qp branch flags on any PR change */
7724 /* FIXME there may be exceptions for certain compares */
7725 clear_qp_branch_flag (qp_changemask
);
7727 /* invalidate rotating registers on insns which affect RRBs in CFM */
7728 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
7730 qp_changemask
|= ~(valueT
)0xFFFF;
7731 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
7733 for (i
=32;i
< 32+md
.rot
.num_regs
;i
++)
7734 gr_values
[i
].known
= 0;
7736 clear_qp_mutex (qp_changemask
);
7737 clear_qp_implies (qp_changemask
, qp_changemask
);
7739 /* after a call, all register values are undefined, except those marked
7741 else if (strncmp (idesc
->name
, "br.call", 6) == 0
7742 || strncmp (idesc
->name
, "brl.call", 7) == 0)
7744 // FIXME keep GR values which are marked as "safe_across_calls"
7745 clear_register_values ();
7746 clear_qp_mutex (~qp_safe_across_calls
);
7747 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
7748 clear_qp_branch_flag (~qp_safe_across_calls
);
7750 else if (is_interruption_or_rfi (idesc
)
7751 || is_taken_branch (idesc
))
7753 clear_register_values ();
7754 clear_qp_mutex (~(valueT
)0);
7755 clear_qp_implies (~(valueT
)0, ~(valueT
)0);
7757 /* Look for mutex and implies relations */
7758 else if ((idesc
->operands
[0] == IA64_OPND_P1
7759 || idesc
->operands
[0] == IA64_OPND_P2
)
7760 && (idesc
->operands
[1] == IA64_OPND_P1
7761 || idesc
->operands
[1] == IA64_OPND_P2
))
7763 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7764 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7765 valueT p1mask
= (valueT
)1 << p1
;
7766 valueT p2mask
= (valueT
)1 << p2
;
7768 /* if one of the PRs is PR0, we can't really do anything */
7769 if (p1
== 0 || p2
== 0)
7772 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
7774 /* In general, clear mutexes and implies which include P1 or P2,
7775 with the following exceptions */
7776 else if (strstr (idesc
->name
, ".or.andcm") != NULL
)
7778 add_qp_mutex (p1mask
| p2mask
);
7779 clear_qp_implies (p2mask
, p1mask
);
7781 else if (strstr (idesc
->name
, ".and.orcm") != NULL
)
7783 add_qp_mutex (p1mask
| p2mask
);
7784 clear_qp_implies (p1mask
, p2mask
);
7786 else if (strstr (idesc
->name
, ".and") != NULL
)
7788 clear_qp_implies (0, p1mask
| p2mask
);
7790 else if (strstr (idesc
->name
, ".or") != NULL
)
7792 clear_qp_mutex (p1mask
| p2mask
);
7793 clear_qp_implies (p1mask
| p2mask
, 0);
7797 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
7798 if (strstr (idesc
->name
, ".unc") != NULL
)
7800 add_qp_mutex (p1mask
| p2mask
);
7801 if (CURR_SLOT
.qp_regno
!= 0)
7803 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
7804 CURR_SLOT
.qp_regno
);
7805 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
7806 CURR_SLOT
.qp_regno
);
7809 else if (CURR_SLOT
.qp_regno
== 0)
7811 add_qp_mutex (p1mask
| p2mask
);
7815 clear_qp_mutex (p1mask
| p2mask
);
7819 /* Look for mov imm insns into GRs */
7820 else if (idesc
->operands
[0] == IA64_OPND_R1
7821 && (idesc
->operands
[1] == IA64_OPND_IMM22
7822 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
7823 && (strcmp(idesc
->name
, "mov") == 0
7824 || strcmp(idesc
->name
, "movl") == 0))
7826 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7827 if (regno
> 0 && regno
< NELEMS(gr_values
))
7829 gr_values
[regno
].known
= 1;
7830 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
7831 gr_values
[regno
].path
= md
.path
;
7833 fprintf (stderr
, " Know gr%d = 0x%llx\n",
7834 regno
, gr_values
[regno
].value
);
7839 clear_qp_mutex (qp_changemask
);
7840 clear_qp_implies (qp_changemask
, qp_changemask
);
7844 /* Return whether the given predicate registers are currently mutex */
7846 qp_mutex (p1
, p2
, path
)
7856 mask
= ((valueT
)1<<p1
) | (valueT
)1<<p2
;
7857 for (i
=0;i
< qp_mutexeslen
;i
++)
7859 if (qp_mutexes
[i
].path
>= path
7860 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
7867 /* Return whether the given resource is in the given insn's list of chks
7868 Return 1 if the conflict is absolutely determined, 2 if it's a potential
7872 resources_match (rs
, idesc
, note
, qp_regno
, path
)
7874 struct ia64_opcode
*idesc
;
7879 struct rsrc specs
[MAX_SPECS
];
7882 /* If the marked resource's qp_regno and the given qp_regno are mutex,
7883 we don't need to check. One exception is note 11, which indicates that
7884 target predicates are written regardless of PR[qp]. */
7885 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
7889 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
7892 /* UNAT checking is a bit more specific than other resources */
7893 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
7894 && specs
[count
].mem_offset
.hint
7895 && rs
->mem_offset
.hint
)
7897 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
7899 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
7900 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
7907 /* If either resource is not specific, conservatively assume a conflict
7909 if (!specs
[count
].specific
|| !rs
->specific
)
7911 else if (specs
[count
].index
== rs
->index
)
7916 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
7922 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
7923 insert a stop to create the break. Update all resource dependencies
7924 appropriately. If QP_REGNO is non-zero, only apply the break to resources
7925 which use the same QP_REGNO and have the link_to_qp_branch flag set.
7926 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
7931 insn_group_break (insert_stop
, qp_regno
, save_current
)
7938 if (insert_stop
&& md
.num_slots_in_use
> 0)
7939 PREV_SLOT
.end_of_insn_group
= 1;
7943 fprintf (stderr
, " Insn group break%s",
7944 (insert_stop
? " (w/stop)" : ""));
7946 fprintf (stderr
, " effective for QP=%d", qp_regno
);
7947 fprintf (stderr
, "\n");
7951 while (i
< regdepslen
)
7953 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
7956 && regdeps
[i
].qp_regno
!= qp_regno
)
7963 && CURR_SLOT
.src_file
== regdeps
[i
].file
7964 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
7970 /* clear dependencies which are automatically cleared by a stop, or
7971 those that have reached the appropriate state of insn serialization */
7972 if (dep
->semantics
== IA64_DVS_IMPLIED
7973 || dep
->semantics
== IA64_DVS_IMPLIEDF
7974 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
7976 print_dependency ("Removing", i
);
7977 regdeps
[i
] = regdeps
[--regdepslen
];
7981 if (dep
->semantics
== IA64_DVS_DATA
7982 || dep
->semantics
== IA64_DVS_INSTR
7983 || dep
->semantics
== IA64_DVS_SPECIFIC
)
7985 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
7986 regdeps
[i
].insn_srlz
= STATE_STOP
;
7987 if (regdeps
[i
].data_srlz
== STATE_NONE
)
7988 regdeps
[i
].data_srlz
= STATE_STOP
;
7995 /* Add the given resource usage spec to the list of active dependencies */
7997 mark_resource (idesc
, dep
, spec
, depind
, path
)
7998 struct ia64_opcode
*idesc
;
7999 const struct ia64_dependency
*dep
;
8004 if (regdepslen
== regdepstotlen
)
8006 regdepstotlen
+= 20;
8007 regdeps
= (struct rsrc
*)
8008 xrealloc ((void *)regdeps
,
8009 regdepstotlen
* sizeof(struct rsrc
));
8012 regdeps
[regdepslen
] = *spec
;
8013 regdeps
[regdepslen
].depind
= depind
;
8014 regdeps
[regdepslen
].path
= path
;
8015 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
8016 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
8018 print_dependency ("Adding", regdepslen
);
8024 print_dependency (action
, depind
)
8030 fprintf (stderr
, " %s %s '%s'",
8031 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
8032 (regdeps
[depind
].dependency
)->name
);
8033 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
8034 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
8035 if (regdeps
[depind
].mem_offset
.hint
)
8036 fprintf (stderr
, " 0x%llx+0x%llx",
8037 regdeps
[depind
].mem_offset
.base
,
8038 regdeps
[depind
].mem_offset
.offset
);
8039 fprintf (stderr
, "\n");
8044 instruction_serialization ()
8048 fprintf (stderr
, " Instruction serialization\n");
8049 for (i
=0;i
< regdepslen
;i
++)
8050 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
8051 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
8055 data_serialization ()
8059 fprintf (stderr
, " Data serialization\n");
8060 while (i
< regdepslen
)
8062 if (regdeps
[i
].data_srlz
== STATE_STOP
8063 /* Note: as of 991210, all "other" dependencies are cleared by a
8064 data serialization. This might change with new tables */
8065 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
8067 print_dependency ("Removing", i
);
8068 regdeps
[i
] = regdeps
[--regdepslen
];
8075 /* Insert stops and serializations as needed to avoid DVs */
8077 remove_marked_resource (rs
)
8080 switch (rs
->dependency
->semantics
)
8082 case IA64_DVS_SPECIFIC
:
8084 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
8085 /* ...fall through... */
8086 case IA64_DVS_INSTR
:
8088 fprintf (stderr
, "Inserting instr serialization\n");
8089 if (rs
->insn_srlz
< STATE_STOP
)
8090 insn_group_break (1, 0, 0);
8091 if (rs
->insn_srlz
< STATE_SRLZ
)
8093 int oldqp
= CURR_SLOT
.qp_regno
;
8094 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8095 /* Manually jam a srlz.i insn into the stream */
8096 CURR_SLOT
.qp_regno
= 0;
8097 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
8098 instruction_serialization ();
8099 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8100 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8102 CURR_SLOT
.qp_regno
= oldqp
;
8103 CURR_SLOT
.idesc
= oldidesc
;
8105 insn_group_break (1, 0, 0);
8107 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
8108 "other" types of DV are eliminated
8109 by a data serialization */
8112 fprintf (stderr
, "Inserting data serialization\n");
8113 if (rs
->data_srlz
< STATE_STOP
)
8114 insn_group_break (1, 0, 0);
8116 int oldqp
= CURR_SLOT
.qp_regno
;
8117 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
8118 /* Manually jam a srlz.d insn into the stream */
8119 CURR_SLOT
.qp_regno
= 0;
8120 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
8121 data_serialization ();
8122 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8123 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8125 CURR_SLOT
.qp_regno
= oldqp
;
8126 CURR_SLOT
.idesc
= oldidesc
;
8129 case IA64_DVS_IMPLIED
:
8130 case IA64_DVS_IMPLIEDF
:
8132 fprintf (stderr
, "Inserting stop\n");
8133 insn_group_break (1, 0, 0);
8140 /* Check the resources used by the given opcode against the current dependency
8143 The check is run once for each execution path encountered. In this case,
8144 a unique execution path is the sequence of instructions following a code
8145 entry point, e.g. the following has three execution paths, one starting
8146 at L0, one at L1, and one at L2.
8154 check_dependencies (idesc
)
8155 struct ia64_opcode
*idesc
;
8157 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8161 /* Note that the number of marked resources may change within the
8162 loop if in auto mode. */
8164 while (i
< regdepslen
)
8166 struct rsrc
*rs
= ®deps
[i
];
8167 const struct ia64_dependency
*dep
= rs
->dependency
;
8172 if (dep
->semantics
== IA64_DVS_NONE
8173 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
8178 note
= NOTE(opdeps
->chks
[chkind
]);
8180 /* Check this resource against each execution path seen thus far */
8181 for (path
=0;path
<= md
.path
;path
++)
8185 /* If the dependency wasn't on the path being checked, ignore it */
8186 if (rs
->path
< path
)
8189 /* If the QP for this insn implies a QP which has branched, don't
8190 bother checking. Ed. NOTE: I don't think this check is terribly
8191 useful; what's the point of generating code which will only be
8192 reached if its QP is zero?
8193 This code was specifically inserted to handle the following code,
8194 based on notes from Intel's DV checking code, where p1 implies p2.
8201 if (CURR_SLOT
.qp_regno
!= 0)
8205 for (implies
=0;implies
< qp_implieslen
;implies
++)
8207 if (qp_implies
[implies
].path
>= path
8208 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
8209 && qp_implies
[implies
].p2_branched
)
8219 if ((matchtype
= resources_match (rs
, idesc
, note
,
8220 CURR_SLOT
.qp_regno
, path
)) != 0)
8223 char pathmsg
[256] = "";
8224 char indexmsg
[256] = "";
8225 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
8228 sprintf (pathmsg
, " when entry is at label '%s'",
8229 md
.entry_labels
[path
-1]);
8230 if (rs
->specific
&& rs
->index
!= 0)
8231 sprintf (indexmsg
, ", specific resource number is %d",
8233 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
8235 (certain
? "violates" : "may violate"),
8236 dv_mode
[dep
->mode
], dep
->name
,
8237 dv_sem
[dep
->semantics
],
8240 if (md
.explicit_mode
)
8242 as_warn ("%s", msg
);
8244 as_warn (_("Only the first path encountering the conflict "
8246 as_warn_where (rs
->file
, rs
->line
,
8247 _("This is the location of the "
8248 "conflicting usage"));
8249 /* Don't bother checking other paths, to avoid duplicating
8256 fprintf(stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
8258 remove_marked_resource (rs
);
8260 /* since the set of dependencies has changed, start over */
8261 /* FIXME -- since we're removing dvs as we go, we
8262 probably don't really need to start over... */
8275 /* register new dependencies based on the given opcode */
8277 mark_resources (idesc
)
8278 struct ia64_opcode
*idesc
;
8281 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
8282 int add_only_qp_reads
= 0;
8284 /* A conditional branch only uses its resources if it is taken; if it is
8285 taken, we stop following that path. The other branch types effectively
8286 *always* write their resources. If it's not taken, register only QP
8288 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
8290 add_only_qp_reads
= 1;
8294 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
8296 for (i
=0;i
< opdeps
->nregs
;i
++)
8298 const struct ia64_dependency
*dep
;
8299 struct rsrc specs
[MAX_SPECS
];
8304 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
8305 note
= NOTE(opdeps
->regs
[i
]);
8307 if (add_only_qp_reads
8308 && !(dep
->mode
== IA64_DV_WAR
8309 && (dep
->specifier
== IA64_RS_PR
8310 || dep
->specifier
== IA64_RS_PR63
)))
8313 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
8316 if (md
.debug_dv
&& !count
)
8317 fprintf (stderr
, " No %s %s usage found (path %d)\n",
8318 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
8323 mark_resource (idesc
, dep
, &specs
[count
],
8324 DEP(opdeps
->regs
[i
]), md
.path
);
8327 /* The execution path may affect register values, which may in turn
8328 affect which indirect-access resources are accessed. */
8329 switch (dep
->specifier
)
8341 for (path
=0;path
< md
.path
;path
++)
8343 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
8345 mark_resource (idesc
, dep
, &specs
[count
],
8346 DEP(opdeps
->regs
[i
]), path
);
8353 /* remove dependencies when they no longer apply */
8355 update_dependencies (idesc
)
8356 struct ia64_opcode
*idesc
;
8360 if (strcmp (idesc
->name
, "srlz.i") == 0)
8362 instruction_serialization ();
8364 else if (strcmp (idesc
->name
, "srlz.d") == 0)
8366 data_serialization ();
8368 else if (is_interruption_or_rfi (idesc
)
8369 || is_taken_branch (idesc
))
8371 /* although technically the taken branch doesn't clear dependencies
8372 which require a srlz.[id], we don't follow the branch; the next
8373 instruction is assumed to start with a clean slate */
8377 else if (is_conditional_branch (idesc
)
8378 && CURR_SLOT
.qp_regno
!= 0)
8380 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
8382 for (i
=0;i
< qp_implieslen
;i
++)
8384 /* if the conditional branch's predicate is implied by the predicate
8385 in an existing dependency, remove that dependency */
8386 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
8389 /* note that this implied predicate takes a branch so that if
8390 a later insn generates a DV but its predicate implies this
8391 one, we can avoid the false DV warning */
8392 qp_implies
[i
].p2_branched
= 1;
8393 while (depind
< regdepslen
)
8395 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
8397 print_dependency ("Removing", depind
);
8398 regdeps
[depind
] = regdeps
[--regdepslen
];
8405 /* Any marked resources which have this same predicate should be
8406 cleared, provided that the QP hasn't been modified between the
8407 marking instruction and the branch.
8411 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
8416 while (i
< regdepslen
)
8418 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
8419 && regdeps
[i
].link_to_qp_branch
8420 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
8421 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
8423 /* Treat like a taken branch */
8424 print_dependency ("Removing", i
);
8425 regdeps
[i
] = regdeps
[--regdepslen
];
8434 /* Examine the current instruction for dependency violations. */
8437 struct ia64_opcode
*idesc
;
8441 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
8442 idesc
->name
, CURR_SLOT
.src_line
,
8443 idesc
->dependencies
->nchks
,
8444 idesc
->dependencies
->nregs
);
8447 /* Look through the list of currently marked resources; if the current
8448 instruction has the dependency in its chks list which uses that resource,
8449 check against the specific resources used.
8451 check_dependencies (idesc
);
8454 Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
8455 then add them to the list of marked resources.
8457 mark_resources (idesc
);
8459 /* There are several types of dependency semantics, and each has its own
8460 requirements for being cleared
8462 Instruction serialization (insns separated by interruption, rfi, or
8463 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
8465 Data serialization (instruction serialization, or writer + srlz.d +
8466 reader, where writer and srlz.d are in separate groups) clears
8467 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
8468 always be the case).
8470 Instruction group break (groups separated by stop, taken branch,
8471 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
8473 update_dependencies (idesc
);
8475 /* Sometimes, knowing a register value allows us to avoid giving a false DV
8476 warning. Keep track of as many as possible that are useful. */
8477 note_register_values (idesc
);
8479 /* We don't need or want this anymore. */
8480 md
.mem_offset
.hint
= 0;
8485 /* Translate one line of assembly. Pseudo ops and labels do not show
8491 char *saved_input_line_pointer
, *mnemonic
;
8492 const struct pseudo_opcode
*pdesc
;
8493 struct ia64_opcode
*idesc
;
8494 unsigned char qp_regno
;
8498 saved_input_line_pointer
= input_line_pointer
;
8499 input_line_pointer
= str
;
8501 /* extract the opcode (mnemonic): */
8503 mnemonic
= input_line_pointer
;
8504 ch
= get_symbol_end ();
8505 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
8508 *input_line_pointer
= ch
;
8509 (*pdesc
->handler
) (pdesc
->arg
);
8513 /* find the instruction descriptor matching the arguments: */
8515 idesc
= ia64_find_opcode (mnemonic
);
8516 *input_line_pointer
= ch
;
8519 as_bad ("Unknown opcode `%s'", mnemonic
);
8523 idesc
= parse_operands (idesc
);
8527 /* Handle the dynamic ops we can handle now: */
8528 if (idesc
->type
== IA64_TYPE_DYN
)
8530 if (strcmp (idesc
->name
, "add") == 0)
8532 if (CURR_SLOT
.opnd
[2].X_op
== O_register
8533 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
8537 ia64_free_opcode (idesc
);
8538 idesc
= ia64_find_opcode (mnemonic
);
8540 know (!idesc
->next
);
8543 else if (strcmp (idesc
->name
, "mov") == 0)
8545 enum ia64_opnd opnd1
, opnd2
;
8548 opnd1
= idesc
->operands
[0];
8549 opnd2
= idesc
->operands
[1];
8550 if (opnd1
== IA64_OPND_AR3
)
8552 else if (opnd2
== IA64_OPND_AR3
)
8556 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
8557 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
8561 ia64_free_opcode (idesc
);
8562 idesc
= ia64_find_opcode (mnemonic
);
8563 while (idesc
!= NULL
8564 && (idesc
->operands
[0] != opnd1
8565 || idesc
->operands
[1] != opnd2
))
8566 idesc
= get_next_opcode (idesc
);
8571 if (md
.qp
.X_op
== O_register
)
8572 qp_regno
= md
.qp
.X_add_number
- REG_P
;
8574 flags
= idesc
->flags
;
8576 if ((flags
& IA64_OPCODE_FIRST
) != 0)
8577 insn_group_break (1, 0, 0);
8579 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
8581 as_bad ("`%s' cannot be predicated", idesc
->name
);
8585 /* build the instruction: */
8586 CURR_SLOT
.qp_regno
= qp_regno
;
8587 CURR_SLOT
.idesc
= idesc
;
8588 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
8589 if (debug_type
== DEBUG_DWARF2
)
8590 dwarf2_where (&CURR_SLOT
.debug_line
);
8592 /* Add unwind entry, if there is one. */
8593 if (unwind
.current_entry
)
8595 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
8596 unwind
.current_entry
= NULL
;
8599 /* check for dependency violations */
8603 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
8604 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
8607 if ((flags
& IA64_OPCODE_LAST
) != 0)
8608 insn_group_break (1, 0, 0);
8610 md
.last_text_seg
= now_seg
;
8613 input_line_pointer
= saved_input_line_pointer
;
8616 /* Called when symbol NAME cannot be found in the symbol table.
8617 Should be used for dynamic valued symbols only. */
8619 md_undefined_symbol (name
)
8625 /* Called for any expression that can not be recognized. When the
8626 function is called, `input_line_pointer' will point to the start of
8632 enum pseudo_type pseudo_type
;
8637 switch (*input_line_pointer
)
8640 /* find what relocation pseudo-function we're dealing with: */
8642 ch
= *++input_line_pointer
;
8643 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
8644 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
8646 len
= strlen (pseudo_func
[i
].name
);
8647 if (strncmp (pseudo_func
[i
].name
+ 1,
8648 input_line_pointer
+ 1, len
- 1) == 0
8649 && !is_part_of_name (input_line_pointer
[len
]))
8651 input_line_pointer
+= len
;
8652 pseudo_type
= pseudo_func
[i
].type
;
8656 switch (pseudo_type
)
8658 case PSEUDO_FUNC_RELOC
:
8660 if (*input_line_pointer
!= '(')
8662 as_bad ("Expected '('");
8665 ++input_line_pointer
; /* skip '(' */
8667 if (*input_line_pointer
++ != ')')
8669 as_bad ("Missing ')'");
8672 if (e
->X_op
!= O_symbol
)
8674 if (e
->X_op
!= O_pseudo_fixup
)
8676 as_bad ("Not a symbolic expression");
8679 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
8680 && i
== FUNC_LT_RELATIVE
)
8681 i
= FUNC_LT_FPTR_RELATIVE
;
8684 as_bad ("Illegal combination of relocation functions");
8688 /* make sure gas doesn't get rid of local symbols that are used
8690 e
->X_op
= O_pseudo_fixup
;
8691 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
8694 case PSEUDO_FUNC_CONST
:
8695 e
->X_op
= O_constant
;
8696 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
8699 case PSEUDO_FUNC_REG
:
8700 e
->X_op
= O_register
;
8701 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
8705 name
= input_line_pointer
- 1;
8707 as_bad ("Unknown pseudo function `%s'", name
);
8713 ++input_line_pointer
;
8715 if (*input_line_pointer
!= ']')
8717 as_bad ("Closing bracket misssing");
8722 if (e
->X_op
!= O_register
)
8723 as_bad ("Register expected as index");
8725 ++input_line_pointer
;
8736 ignore_rest_of_line ();
8739 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
8740 a section symbol plus some offset. For relocs involving @fptr(),
8741 directives we don't want such adjustments since we need to have the
8742 original symbol's name in the reloc. */
8744 ia64_fix_adjustable (fix
)
8747 /* Prevent all adjustments to global symbols */
8748 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
8751 switch (fix
->fx_r_type
)
8753 case BFD_RELOC_IA64_FPTR64I
:
8754 case BFD_RELOC_IA64_FPTR32MSB
:
8755 case BFD_RELOC_IA64_FPTR32LSB
:
8756 case BFD_RELOC_IA64_FPTR64MSB
:
8757 case BFD_RELOC_IA64_FPTR64LSB
:
8758 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8759 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8769 ia64_force_relocation (fix
)
8772 switch (fix
->fx_r_type
)
8774 case BFD_RELOC_IA64_FPTR64I
:
8775 case BFD_RELOC_IA64_FPTR32MSB
:
8776 case BFD_RELOC_IA64_FPTR32LSB
:
8777 case BFD_RELOC_IA64_FPTR64MSB
:
8778 case BFD_RELOC_IA64_FPTR64LSB
:
8780 case BFD_RELOC_IA64_LTOFF22
:
8781 case BFD_RELOC_IA64_LTOFF64I
:
8782 case BFD_RELOC_IA64_LTOFF_FPTR22
:
8783 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
8784 case BFD_RELOC_IA64_PLTOFF22
:
8785 case BFD_RELOC_IA64_PLTOFF64I
:
8786 case BFD_RELOC_IA64_PLTOFF64MSB
:
8787 case BFD_RELOC_IA64_PLTOFF64LSB
:
8796 /* Decide from what point a pc-relative relocation is relative to,
8797 relative to the pc-relative fixup. Er, relatively speaking. */
8799 ia64_pcrel_from_section (fix
, sec
)
8803 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
8805 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
8811 /* This is called whenever some data item (not an instruction) needs a
8812 fixup. We pick the right reloc code depending on the byteorder
8813 currently in effect. */
8815 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
8821 bfd_reloc_code_real_type code
;
8826 /* There are no reloc for 8 and 16 bit quantities, but we allow
8827 them here since they will work fine as long as the expression
8828 is fully defined at the end of the pass over the source file. */
8829 case 1: code
= BFD_RELOC_8
; break;
8830 case 2: code
= BFD_RELOC_16
; break;
8832 if (target_big_endian
)
8833 code
= BFD_RELOC_IA64_DIR32MSB
;
8835 code
= BFD_RELOC_IA64_DIR32LSB
;
8839 if (target_big_endian
)
8840 code
= BFD_RELOC_IA64_DIR64MSB
;
8842 code
= BFD_RELOC_IA64_DIR64LSB
;
8846 as_bad ("Unsupported fixup size %d", nbytes
);
8847 ignore_rest_of_line ();
8850 if (exp
->X_op
== O_pseudo_fixup
)
8853 exp
->X_op
= O_symbol
;
8854 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
8856 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
8857 /* We need to store the byte order in effect in case we're going
8858 to fix an 8 or 16 bit relocation (for which there no real
8859 relocs available). See md_apply_fix(). */
8860 fix
->tc_fix_data
.bigendian
= target_big_endian
;
8863 /* Return the actual relocation we wish to associate with the pseudo
8864 reloc described by SYM and R_TYPE. SYM should be one of the
8865 symbols in the pseudo_func array, or NULL. */
8867 static bfd_reloc_code_real_type
8868 ia64_gen_real_reloc_type (sym
, r_type
)
8870 bfd_reloc_code_real_type r_type
;
8872 bfd_reloc_code_real_type
new = 0;
8879 switch (S_GET_VALUE (sym
))
8881 case FUNC_FPTR_RELATIVE
:
8884 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
8885 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
8886 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
8887 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
8888 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
8893 case FUNC_GP_RELATIVE
:
8896 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
8897 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
8898 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
8899 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
8900 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
8901 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
8906 case FUNC_LT_RELATIVE
:
8909 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
8910 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
8915 case FUNC_PC_RELATIVE
:
8918 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
8919 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
8920 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
8921 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
8922 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
8923 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
8928 case FUNC_PLT_RELATIVE
:
8931 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
8932 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
8933 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
8934 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
8939 case FUNC_SEC_RELATIVE
:
8942 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
8943 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
8944 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
8945 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
8950 case FUNC_SEG_RELATIVE
:
8953 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
8954 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
8955 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
8956 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
8961 case FUNC_LTV_RELATIVE
:
8964 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
8965 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
8966 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
8967 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
8972 case FUNC_LT_FPTR_RELATIVE
:
8975 case BFD_RELOC_IA64_IMM22
:
8976 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
8977 case BFD_RELOC_IA64_IMM64
:
8978 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
8986 /* Hmmmm. Should this ever occur? */
8993 /* Here is where generate the appropriate reloc for pseudo relocation
8996 ia64_validate_fix (fix
)
8999 switch (fix
->fx_r_type
)
9001 case BFD_RELOC_IA64_FPTR64I
:
9002 case BFD_RELOC_IA64_FPTR32MSB
:
9003 case BFD_RELOC_IA64_FPTR64LSB
:
9004 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9005 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9006 if (fix
->fx_offset
!= 0)
9007 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9008 "No addend allowed in @fptr() relocation");
9018 fix_insn (fix
, odesc
, value
)
9020 const struct ia64_operand
*odesc
;
9023 bfd_vma insn
[3], t0
, t1
, control_bits
;
9028 slot
= fix
->fx_where
& 0x3;
9029 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
9031 /* Bundles are always in little-endian byte order */
9032 t0
= bfd_getl64 (fixpos
);
9033 t1
= bfd_getl64 (fixpos
+ 8);
9034 control_bits
= t0
& 0x1f;
9035 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
9036 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
9037 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
9040 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
9042 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
9043 insn
[2] |= (((value
& 0x7f) << 13)
9044 | (((value
>> 7) & 0x1ff) << 27)
9045 | (((value
>> 16) & 0x1f) << 22)
9046 | (((value
>> 21) & 0x1) << 21)
9047 | (((value
>> 63) & 0x1) << 36));
9049 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
9051 if (value
& ~0x3fffffffffffffffULL
)
9052 err
= "integer operand out of range";
9053 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
9054 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
9056 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
9059 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
9060 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
9061 | (((value
>> 0) & 0xfffff) << 13));
9064 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
9067 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
9069 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
9070 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
9071 md_number_to_chars (fixpos
+ 0, t0
, 8);
9072 md_number_to_chars (fixpos
+ 8, t1
, 8);
9075 /* Attempt to simplify or even eliminate a fixup. The return value is
9076 ignored; perhaps it was once meaningful, but now it is historical.
9077 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
9079 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
9082 md_apply_fix3 (fix
, valuep
, seg
)
9088 valueT value
= *valuep
;
9091 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
9095 switch (fix
->fx_r_type
)
9097 case BFD_RELOC_IA64_DIR32MSB
:
9098 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
9102 case BFD_RELOC_IA64_DIR32LSB
:
9103 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
9107 case BFD_RELOC_IA64_DIR64MSB
:
9108 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
9112 case BFD_RELOC_IA64_DIR64LSB
:
9113 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
9123 switch (fix
->fx_r_type
)
9126 as_bad_where (fix
->fx_file
, fix
->fx_line
,
9127 "%s must have a constant value",
9128 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
9135 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
9136 work. There should be a better way to handle this. */
9138 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
9140 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
9142 if (fix
->tc_fix_data
.bigendian
)
9143 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
9145 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
9151 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
9158 /* Generate the BFD reloc to be stuck in the object file from the
9159 fixup used internally in the assembler. */
9161 tc_gen_reloc (sec
, fixp
)
9167 reloc
= xmalloc (sizeof (*reloc
));
9168 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
9169 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
9170 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9171 reloc
->addend
= fixp
->fx_offset
;
9172 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
9176 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9177 "Cannot represent %s relocation in object file",
9178 bfd_get_reloc_code_name (fixp
->fx_r_type
));
9183 /* Turn a string in input_line_pointer into a floating point constant
9184 of type TYPE, and store the appropriate bytes in *LIT. The number
9185 of LITTLENUMS emitted is stored in *SIZE. An error message is
9186 returned, or NULL on OK. */
9188 #define MAX_LITTLENUMS 5
9191 md_atof (type
, lit
, size
)
9196 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
9197 LITTLENUM_TYPE
*word
;
9227 return "Bad call to MD_ATOF()";
9229 t
= atof_ieee (input_line_pointer
, type
, words
);
9231 input_line_pointer
= t
;
9232 *size
= prec
* sizeof (LITTLENUM_TYPE
);
9234 for (word
= words
+ prec
- 1; prec
--;)
9236 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
9237 lit
+= sizeof (LITTLENUM_TYPE
);
9242 /* Round up a section's size to the appropriate boundary. */
9244 md_section_align (seg
, size
)
9248 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9249 valueT mask
= ((valueT
)1 << align
) - 1;
9251 return (size
+ mask
) & ~mask
;
9254 /* Handle ia64 specific semantics of the align directive. */
9257 ia64_md_do_align (n
, fill
, len
, max
)
9263 /* Fill any pending bundle with nops. */
9264 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
9265 ia64_flush_insns ();
9267 /* When we align code in a text section, emit a bundle of 3 nops instead of
9268 zero bytes. We can only do this if a multiple of 16 bytes was requested.
9269 N is log base 2 of the requested alignment. */
9271 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
9274 /* Use mfi bundle of nops with no stop bits. */
9275 static const unsigned char be_nop
[]
9276 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
9277 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
9278 static const unsigned char le_nop
[]
9279 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
9280 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
9282 /* Make sure we are on a 16-byte boundary, in case someone has been
9283 putting data into a text section. */
9284 frag_align (4, 0, 0);
9286 if (target_big_endian
)
9287 frag_align_pattern (n
, be_nop
, 16, max
);
9289 frag_align_pattern (n
, le_nop
, 16, max
);