1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "safe-ctype.h"
47 #include "dwarf2dbg.h"
50 #include "opcode/ia64.h"
54 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
55 #define MIN(a,b) ((a) < (b) ? (a) : (b))
58 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
59 #define CURR_SLOT md.slot[md.curr_slot]
61 #define O_pseudo_fixup (O_max + 1)
65 /* IA-64 ABI section pseudo-ops. */
66 SPECIAL_SECTION_BSS
= 0,
68 SPECIAL_SECTION_SDATA
,
69 SPECIAL_SECTION_RODATA
,
70 SPECIAL_SECTION_COMMENT
,
71 SPECIAL_SECTION_UNWIND
,
72 SPECIAL_SECTION_UNWIND_INFO
,
73 /* HPUX specific section pseudo-ops. */
74 SPECIAL_SECTION_INIT_ARRAY
,
75 SPECIAL_SECTION_FINI_ARRAY
,
88 FUNC_LT_FPTR_RELATIVE
,
95 REG_FR
= (REG_GR
+ 128),
96 REG_AR
= (REG_FR
+ 128),
97 REG_CR
= (REG_AR
+ 128),
98 REG_P
= (REG_CR
+ 128),
99 REG_BR
= (REG_P
+ 64),
100 REG_IP
= (REG_BR
+ 8),
107 /* The following are pseudo-registers for use by gas only. */
119 /* The following pseudo-registers are used for unwind directives only: */
127 DYNREG_GR
= 0, /* dynamic general purpose register */
128 DYNREG_FR
, /* dynamic floating point register */
129 DYNREG_PR
, /* dynamic predicate register */
133 enum operand_match_result
136 OPERAND_OUT_OF_RANGE
,
140 /* On the ia64, we can't know the address of a text label until the
141 instructions are packed into a bundle. To handle this, we keep
142 track of the list of labels that appear in front of each
146 struct label_fix
*next
;
150 extern int target_big_endian
;
152 /* Characters which always start a comment. */
153 const char comment_chars
[] = "";
155 /* Characters which start a comment at the beginning of a line. */
156 const char line_comment_chars
[] = "#";
158 /* Characters which may be used to separate multiple commands on a
160 const char line_separator_chars
[] = ";";
162 /* Characters which are used to indicate an exponent in a floating
164 const char EXP_CHARS
[] = "eE";
166 /* Characters which mean that a number is a floating point constant,
168 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
170 /* ia64-specific option processing: */
172 const char *md_shortopts
= "m:N:x::";
174 struct option md_longopts
[] =
176 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
177 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
178 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
179 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
182 size_t md_longopts_size
= sizeof (md_longopts
);
186 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
187 struct hash_control
*reg_hash
; /* register name hash table */
188 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
189 struct hash_control
*const_hash
; /* constant hash table */
190 struct hash_control
*entry_hash
; /* code entry hint hash table */
192 symbolS
*regsym
[REG_NUM
];
194 /* If X_op is != O_absent, the registername for the instruction's
195 qualifying predicate. If NULL, p0 is assumed for instructions
196 that are predicatable. */
203 explicit_mode
: 1, /* which mode we're in */
204 default_explicit_mode
: 1, /* which mode is the default */
205 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
207 keep_pending_output
: 1;
209 /* Each bundle consists of up to three instructions. We keep
210 track of four most recent instructions so we can correctly set
211 the end_of_insn_group for the last instruction in a bundle. */
213 int num_slots_in_use
;
217 end_of_insn_group
: 1,
218 manual_bundling_on
: 1,
219 manual_bundling_off
: 1;
220 signed char user_template
; /* user-selected template, if any */
221 unsigned char qp_regno
; /* qualifying predicate */
222 /* This duplicates a good fraction of "struct fix" but we
223 can't use a "struct fix" instead since we can't call
224 fix_new_exp() until we know the address of the instruction. */
228 bfd_reloc_code_real_type code
;
229 enum ia64_opnd opnd
; /* type of operand in need of fix */
230 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
231 expressionS expr
; /* the value to be inserted */
233 fixup
[2]; /* at most two fixups per insn */
234 struct ia64_opcode
*idesc
;
235 struct label_fix
*label_fixups
;
236 struct label_fix
*tag_fixups
;
237 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
240 unsigned int src_line
;
241 struct dwarf2_line_info debug_line
;
249 struct dynreg
*next
; /* next dynamic register */
251 unsigned short base
; /* the base register number */
252 unsigned short num_regs
; /* # of registers in this set */
254 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
256 flagword flags
; /* ELF-header flags */
259 unsigned hint
:1; /* is this hint currently valid? */
260 bfd_vma offset
; /* mem.offset offset */
261 bfd_vma base
; /* mem.offset base */
264 int path
; /* number of alt. entry points seen */
265 const char **entry_labels
; /* labels of all alternate paths in
266 the current DV-checking block. */
267 int maxpaths
; /* size currently allocated for
269 /* Support for hardware errata workarounds. */
271 /* Record data about the last three insn groups. */
274 /* B-step workaround.
275 For each predicate register, this is set if the corresponding insn
276 group conditionally sets this register with one of the affected
279 /* B-step workaround.
280 For each general register, this is set if the corresponding insn
281 a) is conditional one one of the predicate registers for which
282 P_REG_SET is 1 in the corresponding entry of the previous group,
283 b) sets this general register with one of the affected
285 int g_reg_set_conditionally
[128];
289 int pointer_size
; /* size in bytes of a pointer */
290 int pointer_size_shift
; /* shift size of a pointer for alignment */
294 /* application registers: */
300 #define AR_BSPSTORE 18
315 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
316 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
317 {"ar.rsc", 16}, {"ar.bsp", 17},
318 {"ar.bspstore", 18}, {"ar.rnat", 19},
319 {"ar.fcr", 21}, {"ar.eflag", 24},
320 {"ar.csd", 25}, {"ar.ssd", 26},
321 {"ar.cflg", 27}, {"ar.fsr", 28},
322 {"ar.fir", 29}, {"ar.fdr", 30},
323 {"ar.ccv", 32}, {"ar.unat", 36},
324 {"ar.fpsr", 40}, {"ar.itc", 44},
325 {"ar.pfs", 64}, {"ar.lc", 65},
346 /* control registers: */
388 static const struct const_desc
395 /* PSR constant masks: */
398 {"psr.be", ((valueT
) 1) << 1},
399 {"psr.up", ((valueT
) 1) << 2},
400 {"psr.ac", ((valueT
) 1) << 3},
401 {"psr.mfl", ((valueT
) 1) << 4},
402 {"psr.mfh", ((valueT
) 1) << 5},
404 {"psr.ic", ((valueT
) 1) << 13},
405 {"psr.i", ((valueT
) 1) << 14},
406 {"psr.pk", ((valueT
) 1) << 15},
408 {"psr.dt", ((valueT
) 1) << 17},
409 {"psr.dfl", ((valueT
) 1) << 18},
410 {"psr.dfh", ((valueT
) 1) << 19},
411 {"psr.sp", ((valueT
) 1) << 20},
412 {"psr.pp", ((valueT
) 1) << 21},
413 {"psr.di", ((valueT
) 1) << 22},
414 {"psr.si", ((valueT
) 1) << 23},
415 {"psr.db", ((valueT
) 1) << 24},
416 {"psr.lp", ((valueT
) 1) << 25},
417 {"psr.tb", ((valueT
) 1) << 26},
418 {"psr.rt", ((valueT
) 1) << 27},
419 /* 28-31: reserved */
420 /* 32-33: cpl (current privilege level) */
421 {"psr.is", ((valueT
) 1) << 34},
422 {"psr.mc", ((valueT
) 1) << 35},
423 {"psr.it", ((valueT
) 1) << 36},
424 {"psr.id", ((valueT
) 1) << 37},
425 {"psr.da", ((valueT
) 1) << 38},
426 {"psr.dd", ((valueT
) 1) << 39},
427 {"psr.ss", ((valueT
) 1) << 40},
428 /* 41-42: ri (restart instruction) */
429 {"psr.ed", ((valueT
) 1) << 43},
430 {"psr.bn", ((valueT
) 1) << 44},
433 /* indirect register-sets/memory: */
442 { "CPUID", IND_CPUID
},
443 { "cpuid", IND_CPUID
},
455 /* Pseudo functions used to indicate relocation types (these functions
456 start with an at sign (@). */
478 /* reloc pseudo functions (these must come first!): */
479 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
480 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
481 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
482 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
483 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
484 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
485 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
486 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
487 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
488 { "iplt", PSEUDO_FUNC_RELOC
, { 0 } },
490 /* mbtype4 constants: */
491 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
492 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
493 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
494 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
495 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
497 /* fclass constants: */
498 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
499 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
500 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
501 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
502 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
503 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
504 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
505 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
506 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
508 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
510 /* unwind-related constants: */
511 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
512 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
513 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
515 /* unwind-related registers: */
516 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
519 /* 41-bit nop opcodes (one per unit): */
520 static const bfd_vma nop
[IA64_NUM_UNITS
] =
522 0x0000000000LL
, /* NIL => break 0 */
523 0x0008000000LL
, /* I-unit nop */
524 0x0008000000LL
, /* M-unit nop */
525 0x4000000000LL
, /* B-unit nop */
526 0x0008000000LL
, /* F-unit nop */
527 0x0008000000LL
, /* L-"unit" nop */
528 0x0008000000LL
, /* X-unit nop */
531 /* Can't be `const' as it's passed to input routines (which have the
532 habit of setting temporary sentinels. */
533 static char special_section_name
[][20] =
535 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
536 {".IA_64.unwind"}, {".IA_64.unwind_info"},
537 {".init_array"}, {".fini_array"}
540 static char *special_linkonce_name
[] =
542 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
545 /* The best template for a particular sequence of up to three
547 #define N IA64_NUM_TYPES
548 static unsigned char best_template
[N
][N
][N
];
551 /* Resource dependencies currently in effect */
553 int depind
; /* dependency index */
554 const struct ia64_dependency
*dependency
; /* actual dependency */
555 unsigned specific
:1, /* is this a specific bit/regno? */
556 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
557 int index
; /* specific regno/bit within dependency */
558 int note
; /* optional qualifying note (0 if none) */
562 int insn_srlz
; /* current insn serialization state */
563 int data_srlz
; /* current data serialization state */
564 int qp_regno
; /* qualifying predicate for this usage */
565 char *file
; /* what file marked this dependency */
566 unsigned int line
; /* what line marked this dependency */
567 struct mem_offset mem_offset
; /* optional memory offset hint */
568 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
569 int path
; /* corresponding code entry index */
571 static int regdepslen
= 0;
572 static int regdepstotlen
= 0;
573 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
574 static const char *dv_sem
[] = { "none", "implied", "impliedf",
575 "data", "instr", "specific", "stop", "other" };
576 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
578 /* Current state of PR mutexation */
579 static struct qpmutex
{
582 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
583 static int qp_mutexeslen
= 0;
584 static int qp_mutexestotlen
= 0;
585 static valueT qp_safe_across_calls
= 0;
587 /* Current state of PR implications */
588 static struct qp_imply
{
591 unsigned p2_branched
:1;
593 } *qp_implies
= NULL
;
594 static int qp_implieslen
= 0;
595 static int qp_impliestotlen
= 0;
597 /* Keep track of static GR values so that indirect register usage can
598 sometimes be tracked. */
603 } gr_values
[128] = {{ 1, 0, 0 }};
605 /* These are the routines required to output the various types of
608 /* A slot_number is a frag address plus the slot index (0-2). We use the
609 frag address here so that if there is a section switch in the middle of
610 a function, then instructions emitted to a different section are not
611 counted. Since there may be more than one frag for a function, this
612 means we also need to keep track of which frag this address belongs to
613 so we can compute inter-frag distances. This also nicely solves the
614 problem with nops emitted for align directives, which can't easily be
615 counted, but can easily be derived from frag sizes. */
617 typedef struct unw_rec_list
{
619 unsigned long slot_number
;
621 struct unw_rec_list
*next
;
624 #define SLOT_NUM_NOT_SET (unsigned)-1
626 /* Linked list of saved prologue counts. A very poor
627 implementation of a map from label numbers to prologue counts. */
628 typedef struct label_prologue_count
630 struct label_prologue_count
*next
;
631 unsigned long label_number
;
632 unsigned int prologue_count
;
633 } label_prologue_count
;
637 unsigned long next_slot_number
;
638 fragS
*next_slot_frag
;
640 /* Maintain a list of unwind entries for the current function. */
644 /* Any unwind entires that should be attached to the current slot
645 that an insn is being constructed for. */
646 unw_rec_list
*current_entry
;
648 /* These are used to create the unwind table entry for this function. */
651 symbolS
*info
; /* pointer to unwind info */
652 symbolS
*personality_routine
;
654 subsegT saved_text_subseg
;
655 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
657 /* TRUE if processing unwind directives in a prologue region. */
660 unsigned int prologue_count
; /* number of .prologues seen so far */
661 /* Prologue counts at previous .label_state directives. */
662 struct label_prologue_count
* saved_prologue_counts
;
665 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
667 /* Forward delarations: */
668 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
669 static void set_section
PARAMS ((char *name
));
670 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
671 unsigned int, unsigned int));
672 static void dot_radix
PARAMS ((int));
673 static void dot_special_section
PARAMS ((int));
674 static void dot_proc
PARAMS ((int));
675 static void dot_fframe
PARAMS ((int));
676 static void dot_vframe
PARAMS ((int));
677 static void dot_vframesp
PARAMS ((int));
678 static void dot_vframepsp
PARAMS ((int));
679 static void dot_save
PARAMS ((int));
680 static void dot_restore
PARAMS ((int));
681 static void dot_restorereg
PARAMS ((int));
682 static void dot_restorereg_p
PARAMS ((int));
683 static void dot_handlerdata
PARAMS ((int));
684 static void dot_unwentry
PARAMS ((int));
685 static void dot_altrp
PARAMS ((int));
686 static void dot_savemem
PARAMS ((int));
687 static void dot_saveg
PARAMS ((int));
688 static void dot_savef
PARAMS ((int));
689 static void dot_saveb
PARAMS ((int));
690 static void dot_savegf
PARAMS ((int));
691 static void dot_spill
PARAMS ((int));
692 static void dot_spillreg
PARAMS ((int));
693 static void dot_spillmem
PARAMS ((int));
694 static void dot_spillreg_p
PARAMS ((int));
695 static void dot_spillmem_p
PARAMS ((int));
696 static void dot_label_state
PARAMS ((int));
697 static void dot_copy_state
PARAMS ((int));
698 static void dot_unwabi
PARAMS ((int));
699 static void dot_personality
PARAMS ((int));
700 static void dot_body
PARAMS ((int));
701 static void dot_prologue
PARAMS ((int));
702 static void dot_endp
PARAMS ((int));
703 static void dot_template
PARAMS ((int));
704 static void dot_regstk
PARAMS ((int));
705 static void dot_rot
PARAMS ((int));
706 static void dot_byteorder
PARAMS ((int));
707 static void dot_psr
PARAMS ((int));
708 static void dot_alias
PARAMS ((int));
709 static void dot_ln
PARAMS ((int));
710 static char *parse_section_name
PARAMS ((void));
711 static void dot_xdata
PARAMS ((int));
712 static void stmt_float_cons
PARAMS ((int));
713 static void stmt_cons_ua
PARAMS ((int));
714 static void dot_xfloat_cons
PARAMS ((int));
715 static void dot_xstringer
PARAMS ((int));
716 static void dot_xdata_ua
PARAMS ((int));
717 static void dot_xfloat_cons_ua
PARAMS ((int));
718 static void print_prmask
PARAMS ((valueT mask
));
719 static void dot_pred_rel
PARAMS ((int));
720 static void dot_reg_val
PARAMS ((int));
721 static void dot_dv_mode
PARAMS ((int));
722 static void dot_entry
PARAMS ((int));
723 static void dot_mem_offset
PARAMS ((int));
724 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
725 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
726 static void declare_register_set
PARAMS ((const char *, int, int));
727 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
728 static enum operand_match_result operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
731 static int parse_operand
PARAMS ((expressionS
*e
));
732 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
733 static int errata_nop_necessary_p
PARAMS ((struct slot
*, enum ia64_unit
));
734 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
735 static void emit_one_bundle
PARAMS ((void));
736 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
737 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
738 bfd_reloc_code_real_type r_type
));
739 static void insn_group_break
PARAMS ((int, int, int));
740 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
741 struct rsrc
*, int depind
, int path
));
742 static void add_qp_mutex
PARAMS((valueT mask
));
743 static void add_qp_imply
PARAMS((int p1
, int p2
));
744 static void clear_qp_branch_flag
PARAMS((valueT mask
));
745 static void clear_qp_mutex
PARAMS((valueT mask
));
746 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
747 static int has_suffix_p
PARAMS((const char *, const char *));
748 static void clear_register_values
PARAMS ((void));
749 static void print_dependency
PARAMS ((const char *action
, int depind
));
750 static void instruction_serialization
PARAMS ((void));
751 static void data_serialization
PARAMS ((void));
752 static void remove_marked_resource
PARAMS ((struct rsrc
*));
753 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
754 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
755 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
756 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
757 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
758 struct ia64_opcode
*, int, struct rsrc
[], int, int));
759 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
760 static void check_dependencies
PARAMS((struct ia64_opcode
*));
761 static void mark_resources
PARAMS((struct ia64_opcode
*));
762 static void update_dependencies
PARAMS((struct ia64_opcode
*));
763 static void note_register_values
PARAMS((struct ia64_opcode
*));
764 static int qp_mutex
PARAMS ((int, int, int));
765 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
766 static void output_vbyte_mem
PARAMS ((int, char *, char *));
767 static void count_output
PARAMS ((int, char *, char *));
768 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
769 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
770 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
771 static void output_P1_format
PARAMS ((vbyte_func
, int));
772 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
773 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
774 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
775 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
776 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
777 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
778 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
779 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
780 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
781 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
782 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
783 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
784 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
785 static char format_ab_reg
PARAMS ((int, int));
786 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
788 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
789 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
791 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
792 static void free_list_records
PARAMS ((unw_rec_list
*));
793 static unw_rec_list
*output_prologue
PARAMS ((void));
794 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
795 static unw_rec_list
*output_body
PARAMS ((void));
796 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
797 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
798 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
799 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
800 static unw_rec_list
*output_rp_when
PARAMS ((void));
801 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
802 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
803 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
804 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
805 static unw_rec_list
*output_pfs_when
PARAMS ((void));
806 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
807 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
808 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
809 static unw_rec_list
*output_preds_when
PARAMS ((void));
810 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
811 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
812 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
813 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
814 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
815 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
816 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
817 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
818 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
819 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
820 static unw_rec_list
*output_unat_when
PARAMS ((void));
821 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
822 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
823 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
824 static unw_rec_list
*output_lc_when
PARAMS ((void));
825 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
826 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
827 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
828 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
829 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
830 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
831 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
832 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
833 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
834 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
835 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
836 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
837 static unw_rec_list
*output_bsp_when
PARAMS ((void));
838 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
839 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
840 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
841 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
842 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
843 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
844 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
845 static unw_rec_list
*output_rnat_when
PARAMS ((void));
846 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
847 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
848 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
849 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
850 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
851 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
852 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
853 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
854 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
855 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
857 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
859 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
861 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
862 unsigned int, unsigned int));
863 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
864 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
865 static int calc_record_size
PARAMS ((unw_rec_list
*));
866 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
867 static int count_bits
PARAMS ((unsigned long));
868 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
869 unsigned long, fragS
*));
870 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
871 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
872 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
873 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
874 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
875 static int generate_unwind_image
PARAMS ((const char *));
876 static unsigned int get_saved_prologue_count
PARAMS ((unsigned long));
877 static void save_prologue_count
PARAMS ((unsigned long, unsigned int));
878 static void free_saved_prologue_counts
PARAMS ((void));
880 /* Build the unwind section name by appending the (possibly stripped)
881 text section NAME to the unwind PREFIX. The resulting string
882 pointer is assigned to RESULT. The string is allocated on the
883 stack, so this must be a macro... */
884 #define make_unw_section_name(special, text_name, result) \
886 const char *_prefix = special_section_name[special]; \
887 const char *_suffix = text_name; \
888 size_t _prefix_len, _suffix_len; \
890 if (strncmp (text_name, ".gnu.linkonce.t.", \
891 sizeof (".gnu.linkonce.t.") - 1) == 0) \
893 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
894 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
896 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
897 _result = alloca (_prefix_len + _suffix_len + 1); \
898 memcpy (_result, _prefix, _prefix_len); \
899 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
900 _result[_prefix_len + _suffix_len] = '\0'; \
905 /* Determine if application register REGNUM resides in the integer
906 unit (as opposed to the memory unit). */
908 ar_is_in_integer_unit (reg
)
913 return (reg
== 64 /* pfs */
914 || reg
== 65 /* lc */
915 || reg
== 66 /* ec */
916 /* ??? ias accepts and puts these in the integer unit. */
917 || (reg
>= 112 && reg
<= 127));
920 /* Switch to section NAME and create section if necessary. It's
921 rather ugly that we have to manipulate input_line_pointer but I
922 don't see any other way to accomplish the same thing without
923 changing obj-elf.c (which may be the Right Thing, in the end). */
928 char *saved_input_line_pointer
;
930 saved_input_line_pointer
= input_line_pointer
;
931 input_line_pointer
= name
;
933 input_line_pointer
= saved_input_line_pointer
;
936 /* Map 's' to SHF_IA_64_SHORT. */
939 ia64_elf_section_letter (letter
, ptr_msg
)
944 return SHF_IA_64_SHORT
;
946 *ptr_msg
= _("Bad .section directive: want a,s,w,x,M,S in string");
950 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
953 ia64_elf_section_flags (flags
, attr
, type
)
955 int attr
, type ATTRIBUTE_UNUSED
;
957 if (attr
& SHF_IA_64_SHORT
)
958 flags
|= SEC_SMALL_DATA
;
963 ia64_elf_section_type (str
, len
)
967 #define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0))
969 if (STREQ (ELF_STRING_ia64_unwind_info
))
972 if (STREQ (ELF_STRING_ia64_unwind_info_once
))
975 if (STREQ (ELF_STRING_ia64_unwind
))
976 return SHT_IA_64_UNWIND
;
978 if (STREQ (ELF_STRING_ia64_unwind_once
))
979 return SHT_IA_64_UNWIND
;
981 if (STREQ ("init_array"))
982 return SHT_INIT_ARRAY
;
984 if (STREQ ("fini_array"))
985 return SHT_FINI_ARRAY
;
992 set_regstack (ins
, locs
, outs
, rots
)
993 unsigned int ins
, locs
, outs
, rots
;
998 sof
= ins
+ locs
+ outs
;
1001 as_bad ("Size of frame exceeds maximum of 96 registers");
1006 as_warn ("Size of rotating registers exceeds frame size");
1009 md
.in
.base
= REG_GR
+ 32;
1010 md
.loc
.base
= md
.in
.base
+ ins
;
1011 md
.out
.base
= md
.loc
.base
+ locs
;
1013 md
.in
.num_regs
= ins
;
1014 md
.loc
.num_regs
= locs
;
1015 md
.out
.num_regs
= outs
;
1016 md
.rot
.num_regs
= rots
;
1023 struct label_fix
*lfix
;
1025 subsegT saved_subseg
;
1028 if (!md
.last_text_seg
)
1031 saved_seg
= now_seg
;
1032 saved_subseg
= now_subseg
;
1034 subseg_set (md
.last_text_seg
, 0);
1036 while (md
.num_slots_in_use
> 0)
1037 emit_one_bundle (); /* force out queued instructions */
1039 /* In case there are labels following the last instruction, resolve
1041 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
1043 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1044 symbol_set_frag (lfix
->sym
, frag_now
);
1046 CURR_SLOT
.label_fixups
= 0;
1047 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
1049 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1050 symbol_set_frag (lfix
->sym
, frag_now
);
1052 CURR_SLOT
.tag_fixups
= 0;
1054 /* In case there are unwind directives following the last instruction,
1055 resolve those now. We only handle body and prologue directives here.
1056 Give an error for others. */
1057 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
1059 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
1060 || ptr
->r
.type
== body
)
1062 ptr
->slot_number
= (unsigned long) frag_more (0);
1063 ptr
->slot_frag
= frag_now
;
1066 as_bad (_("Unwind directive not followed by an instruction."));
1068 unwind
.current_entry
= NULL
;
1070 subseg_set (saved_seg
, saved_subseg
);
1072 if (md
.qp
.X_op
== O_register
)
1073 as_bad ("qualifying predicate not followed by instruction");
1077 ia64_do_align (nbytes
)
1080 char *saved_input_line_pointer
= input_line_pointer
;
1082 input_line_pointer
= "";
1083 s_align_bytes (nbytes
);
1084 input_line_pointer
= saved_input_line_pointer
;
1088 ia64_cons_align (nbytes
)
1093 char *saved_input_line_pointer
= input_line_pointer
;
1094 input_line_pointer
= "";
1095 s_align_bytes (nbytes
);
1096 input_line_pointer
= saved_input_line_pointer
;
1100 /* Output COUNT bytes to a memory location. */
1101 static unsigned char *vbyte_mem_ptr
= NULL
;
1104 output_vbyte_mem (count
, ptr
, comment
)
1107 char *comment ATTRIBUTE_UNUSED
;
1110 if (vbyte_mem_ptr
== NULL
)
1115 for (x
= 0; x
< count
; x
++)
1116 *(vbyte_mem_ptr
++) = ptr
[x
];
1119 /* Count the number of bytes required for records. */
1120 static int vbyte_count
= 0;
1122 count_output (count
, ptr
, comment
)
1124 char *ptr ATTRIBUTE_UNUSED
;
1125 char *comment ATTRIBUTE_UNUSED
;
1127 vbyte_count
+= count
;
1131 output_R1_format (f
, rtype
, rlen
)
1133 unw_record_type rtype
;
1140 output_R3_format (f
, rtype
, rlen
);
1146 else if (rtype
!= prologue
)
1147 as_bad ("record type is not valid");
1149 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1150 (*f
) (1, &byte
, NULL
);
1154 output_R2_format (f
, mask
, grsave
, rlen
)
1161 mask
= (mask
& 0x0f);
1162 grsave
= (grsave
& 0x7f);
1164 bytes
[0] = (UNW_R2
| (mask
>> 1));
1165 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1166 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1167 (*f
) (count
, bytes
, NULL
);
1171 output_R3_format (f
, rtype
, rlen
)
1173 unw_record_type rtype
;
1180 output_R1_format (f
, rtype
, rlen
);
1186 else if (rtype
!= prologue
)
1187 as_bad ("record type is not valid");
1188 bytes
[0] = (UNW_R3
| r
);
1189 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1190 (*f
) (count
+ 1, bytes
, NULL
);
1194 output_P1_format (f
, brmask
)
1199 byte
= UNW_P1
| (brmask
& 0x1f);
1200 (*f
) (1, &byte
, NULL
);
1204 output_P2_format (f
, brmask
, gr
)
1210 brmask
= (brmask
& 0x1f);
1211 bytes
[0] = UNW_P2
| (brmask
>> 1);
1212 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1213 (*f
) (2, bytes
, NULL
);
1217 output_P3_format (f
, rtype
, reg
)
1219 unw_record_type rtype
;
1264 as_bad ("Invalid record type for P3 format.");
1266 bytes
[0] = (UNW_P3
| (r
>> 1));
1267 bytes
[1] = (((r
& 1) << 7) | reg
);
1268 (*f
) (2, bytes
, NULL
);
1272 output_P4_format (f
, imask
, imask_size
)
1274 unsigned char *imask
;
1275 unsigned long imask_size
;
1278 (*f
) (imask_size
, imask
, NULL
);
1282 output_P5_format (f
, grmask
, frmask
)
1285 unsigned long frmask
;
1288 grmask
= (grmask
& 0x0f);
1291 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1292 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1293 bytes
[3] = (frmask
& 0x000000ff);
1294 (*f
) (4, bytes
, NULL
);
1298 output_P6_format (f
, rtype
, rmask
)
1300 unw_record_type rtype
;
1306 if (rtype
== gr_mem
)
1308 else if (rtype
!= fr_mem
)
1309 as_bad ("Invalid record type for format P6");
1310 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1311 (*f
) (1, &byte
, NULL
);
1315 output_P7_format (f
, rtype
, w1
, w2
)
1317 unw_record_type rtype
;
1324 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1329 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1379 bytes
[0] = (UNW_P7
| r
);
1380 (*f
) (count
, bytes
, NULL
);
1384 output_P8_format (f
, rtype
, t
)
1386 unw_record_type rtype
;
1425 case bspstore_psprel
:
1428 case bspstore_sprel
:
1440 case priunat_when_gr
:
1443 case priunat_psprel
:
1449 case priunat_when_mem
:
1456 count
+= output_leb128 (bytes
+ 2, t
, 0);
1457 (*f
) (count
, bytes
, NULL
);
1461 output_P9_format (f
, grmask
, gr
)
1468 bytes
[1] = (grmask
& 0x0f);
1469 bytes
[2] = (gr
& 0x7f);
1470 (*f
) (3, bytes
, NULL
);
1474 output_P10_format (f
, abi
, context
)
1481 bytes
[1] = (abi
& 0xff);
1482 bytes
[2] = (context
& 0xff);
1483 (*f
) (3, bytes
, NULL
);
1487 output_B1_format (f
, rtype
, label
)
1489 unw_record_type rtype
;
1490 unsigned long label
;
1496 output_B4_format (f
, rtype
, label
);
1499 if (rtype
== copy_state
)
1501 else if (rtype
!= label_state
)
1502 as_bad ("Invalid record type for format B1");
1504 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1505 (*f
) (1, &byte
, NULL
);
1509 output_B2_format (f
, ecount
, t
)
1511 unsigned long ecount
;
1518 output_B3_format (f
, ecount
, t
);
1521 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1522 count
+= output_leb128 (bytes
+ 1, t
, 0);
1523 (*f
) (count
, bytes
, NULL
);
1527 output_B3_format (f
, ecount
, t
)
1529 unsigned long ecount
;
1536 output_B2_format (f
, ecount
, t
);
1540 count
+= output_leb128 (bytes
+ 1, t
, 0);
1541 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1542 (*f
) (count
, bytes
, NULL
);
1546 output_B4_format (f
, rtype
, label
)
1548 unw_record_type rtype
;
1549 unsigned long label
;
1556 output_B1_format (f
, rtype
, label
);
1560 if (rtype
== copy_state
)
1562 else if (rtype
!= label_state
)
1563 as_bad ("Invalid record type for format B1");
1565 bytes
[0] = (UNW_B4
| (r
<< 3));
1566 count
+= output_leb128 (bytes
+ 1, label
, 0);
1567 (*f
) (count
, bytes
, NULL
);
1571 format_ab_reg (ab
, reg
)
1578 ret
= (ab
<< 5) | reg
;
1583 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1585 unw_record_type rtype
;
1595 if (rtype
== spill_sprel
)
1597 else if (rtype
!= spill_psprel
)
1598 as_bad ("Invalid record type for format X1");
1599 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1600 count
+= output_leb128 (bytes
+ 2, t
, 0);
1601 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1602 (*f
) (count
, bytes
, NULL
);
1606 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1615 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1616 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1617 count
+= output_leb128 (bytes
+ 3, t
, 0);
1618 (*f
) (count
, bytes
, NULL
);
1622 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1624 unw_record_type rtype
;
1635 if (rtype
== spill_sprel_p
)
1637 else if (rtype
!= spill_psprel_p
)
1638 as_bad ("Invalid record type for format X3");
1639 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1640 bytes
[2] = format_ab_reg (ab
, reg
);
1641 count
+= output_leb128 (bytes
+ 3, t
, 0);
1642 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1643 (*f
) (count
, bytes
, NULL
);
1647 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1657 bytes
[1] = (qp
& 0x3f);
1658 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1659 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1660 count
+= output_leb128 (bytes
+ 4, t
, 0);
1661 (*f
) (count
, bytes
, NULL
);
1664 /* This function allocates a record list structure, and initializes fields. */
1666 static unw_rec_list
*
1667 alloc_record (unw_record_type t
)
1670 ptr
= xmalloc (sizeof (*ptr
));
1672 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1677 /* This function frees an entire list of record structures. */
1680 free_list_records (unw_rec_list
*first
)
1683 for (ptr
= first
; ptr
!= NULL
;)
1685 unw_rec_list
*tmp
= ptr
;
1687 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1688 && tmp
->r
.record
.r
.mask
.i
)
1689 free (tmp
->r
.record
.r
.mask
.i
);
1696 static unw_rec_list
*
1699 unw_rec_list
*ptr
= alloc_record (prologue
);
1700 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1704 static unw_rec_list
*
1705 output_prologue_gr (saved_mask
, reg
)
1706 unsigned int saved_mask
;
1709 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1710 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1711 ptr
->r
.record
.r
.grmask
= saved_mask
;
1712 ptr
->r
.record
.r
.grsave
= reg
;
1716 static unw_rec_list
*
1719 unw_rec_list
*ptr
= alloc_record (body
);
1723 static unw_rec_list
*
1724 output_mem_stack_f (size
)
1727 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1728 ptr
->r
.record
.p
.size
= size
;
1732 static unw_rec_list
*
1733 output_mem_stack_v ()
1735 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1739 static unw_rec_list
*
1743 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1744 ptr
->r
.record
.p
.gr
= gr
;
1748 static unw_rec_list
*
1749 output_psp_sprel (offset
)
1750 unsigned int offset
;
1752 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1753 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1757 static unw_rec_list
*
1760 unw_rec_list
*ptr
= alloc_record (rp_when
);
1764 static unw_rec_list
*
1768 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1769 ptr
->r
.record
.p
.gr
= gr
;
1773 static unw_rec_list
*
1777 unw_rec_list
*ptr
= alloc_record (rp_br
);
1778 ptr
->r
.record
.p
.br
= br
;
1782 static unw_rec_list
*
1783 output_rp_psprel (offset
)
1784 unsigned int offset
;
1786 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1787 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1791 static unw_rec_list
*
1792 output_rp_sprel (offset
)
1793 unsigned int offset
;
1795 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1796 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1800 static unw_rec_list
*
1803 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1807 static unw_rec_list
*
1811 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1812 ptr
->r
.record
.p
.gr
= gr
;
1816 static unw_rec_list
*
1817 output_pfs_psprel (offset
)
1818 unsigned int offset
;
1820 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1821 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1825 static unw_rec_list
*
1826 output_pfs_sprel (offset
)
1827 unsigned int offset
;
1829 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1830 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1834 static unw_rec_list
*
1835 output_preds_when ()
1837 unw_rec_list
*ptr
= alloc_record (preds_when
);
1841 static unw_rec_list
*
1842 output_preds_gr (gr
)
1845 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1846 ptr
->r
.record
.p
.gr
= gr
;
1850 static unw_rec_list
*
1851 output_preds_psprel (offset
)
1852 unsigned int offset
;
1854 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1855 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1859 static unw_rec_list
*
1860 output_preds_sprel (offset
)
1861 unsigned int offset
;
1863 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1864 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1868 static unw_rec_list
*
1869 output_fr_mem (mask
)
1872 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1873 ptr
->r
.record
.p
.rmask
= mask
;
1877 static unw_rec_list
*
1878 output_frgr_mem (gr_mask
, fr_mask
)
1879 unsigned int gr_mask
;
1880 unsigned int fr_mask
;
1882 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1883 ptr
->r
.record
.p
.grmask
= gr_mask
;
1884 ptr
->r
.record
.p
.frmask
= fr_mask
;
1888 static unw_rec_list
*
1889 output_gr_gr (mask
, reg
)
1893 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1894 ptr
->r
.record
.p
.grmask
= mask
;
1895 ptr
->r
.record
.p
.gr
= reg
;
1899 static unw_rec_list
*
1900 output_gr_mem (mask
)
1903 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1904 ptr
->r
.record
.p
.rmask
= mask
;
1908 static unw_rec_list
*
1909 output_br_mem (unsigned int mask
)
1911 unw_rec_list
*ptr
= alloc_record (br_mem
);
1912 ptr
->r
.record
.p
.brmask
= mask
;
1916 static unw_rec_list
*
1917 output_br_gr (save_mask
, reg
)
1918 unsigned int save_mask
;
1921 unw_rec_list
*ptr
= alloc_record (br_gr
);
1922 ptr
->r
.record
.p
.brmask
= save_mask
;
1923 ptr
->r
.record
.p
.gr
= reg
;
1927 static unw_rec_list
*
1928 output_spill_base (offset
)
1929 unsigned int offset
;
1931 unw_rec_list
*ptr
= alloc_record (spill_base
);
1932 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1936 static unw_rec_list
*
1939 unw_rec_list
*ptr
= alloc_record (unat_when
);
1943 static unw_rec_list
*
1947 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1948 ptr
->r
.record
.p
.gr
= gr
;
1952 static unw_rec_list
*
1953 output_unat_psprel (offset
)
1954 unsigned int offset
;
1956 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1957 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1961 static unw_rec_list
*
1962 output_unat_sprel (offset
)
1963 unsigned int offset
;
1965 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1966 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1970 static unw_rec_list
*
1973 unw_rec_list
*ptr
= alloc_record (lc_when
);
1977 static unw_rec_list
*
1981 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1982 ptr
->r
.record
.p
.gr
= gr
;
1986 static unw_rec_list
*
1987 output_lc_psprel (offset
)
1988 unsigned int offset
;
1990 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
1991 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1995 static unw_rec_list
*
1996 output_lc_sprel (offset
)
1997 unsigned int offset
;
1999 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
2000 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2004 static unw_rec_list
*
2007 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
2011 static unw_rec_list
*
2015 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
2016 ptr
->r
.record
.p
.gr
= gr
;
2020 static unw_rec_list
*
2021 output_fpsr_psprel (offset
)
2022 unsigned int offset
;
2024 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
2025 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2029 static unw_rec_list
*
2030 output_fpsr_sprel (offset
)
2031 unsigned int offset
;
2033 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
2034 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2038 static unw_rec_list
*
2039 output_priunat_when_gr ()
2041 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
2045 static unw_rec_list
*
2046 output_priunat_when_mem ()
2048 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
2052 static unw_rec_list
*
2053 output_priunat_gr (gr
)
2056 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
2057 ptr
->r
.record
.p
.gr
= gr
;
2061 static unw_rec_list
*
2062 output_priunat_psprel (offset
)
2063 unsigned int offset
;
2065 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
2066 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2070 static unw_rec_list
*
2071 output_priunat_sprel (offset
)
2072 unsigned int offset
;
2074 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
2075 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2079 static unw_rec_list
*
2082 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2086 static unw_rec_list
*
2090 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2091 ptr
->r
.record
.p
.gr
= gr
;
2095 static unw_rec_list
*
2096 output_bsp_psprel (offset
)
2097 unsigned int offset
;
2099 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2100 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2104 static unw_rec_list
*
2105 output_bsp_sprel (offset
)
2106 unsigned int offset
;
2108 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2109 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2113 static unw_rec_list
*
2114 output_bspstore_when ()
2116 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2120 static unw_rec_list
*
2121 output_bspstore_gr (gr
)
2124 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2125 ptr
->r
.record
.p
.gr
= gr
;
2129 static unw_rec_list
*
2130 output_bspstore_psprel (offset
)
2131 unsigned int offset
;
2133 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2134 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2138 static unw_rec_list
*
2139 output_bspstore_sprel (offset
)
2140 unsigned int offset
;
2142 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2143 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2147 static unw_rec_list
*
2150 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2154 static unw_rec_list
*
2158 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2159 ptr
->r
.record
.p
.gr
= gr
;
2163 static unw_rec_list
*
2164 output_rnat_psprel (offset
)
2165 unsigned int offset
;
2167 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2168 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2172 static unw_rec_list
*
2173 output_rnat_sprel (offset
)
2174 unsigned int offset
;
2176 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2177 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2181 static unw_rec_list
*
2182 output_unwabi (abi
, context
)
2184 unsigned long context
;
2186 unw_rec_list
*ptr
= alloc_record (unwabi
);
2187 ptr
->r
.record
.p
.abi
= abi
;
2188 ptr
->r
.record
.p
.context
= context
;
2192 static unw_rec_list
*
2193 output_epilogue (unsigned long ecount
)
2195 unw_rec_list
*ptr
= alloc_record (epilogue
);
2196 ptr
->r
.record
.b
.ecount
= ecount
;
2200 static unw_rec_list
*
2201 output_label_state (unsigned long label
)
2203 unw_rec_list
*ptr
= alloc_record (label_state
);
2204 ptr
->r
.record
.b
.label
= label
;
2208 static unw_rec_list
*
2209 output_copy_state (unsigned long label
)
2211 unw_rec_list
*ptr
= alloc_record (copy_state
);
2212 ptr
->r
.record
.b
.label
= label
;
2216 static unw_rec_list
*
2217 output_spill_psprel (ab
, reg
, offset
)
2220 unsigned int offset
;
2222 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2223 ptr
->r
.record
.x
.ab
= ab
;
2224 ptr
->r
.record
.x
.reg
= reg
;
2225 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2229 static unw_rec_list
*
2230 output_spill_sprel (ab
, reg
, offset
)
2233 unsigned int offset
;
2235 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2236 ptr
->r
.record
.x
.ab
= ab
;
2237 ptr
->r
.record
.x
.reg
= reg
;
2238 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2242 static unw_rec_list
*
2243 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2246 unsigned int offset
;
2247 unsigned int predicate
;
2249 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2250 ptr
->r
.record
.x
.ab
= ab
;
2251 ptr
->r
.record
.x
.reg
= reg
;
2252 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2253 ptr
->r
.record
.x
.qp
= predicate
;
2257 static unw_rec_list
*
2258 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2261 unsigned int offset
;
2262 unsigned int predicate
;
2264 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2265 ptr
->r
.record
.x
.ab
= ab
;
2266 ptr
->r
.record
.x
.reg
= reg
;
2267 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2268 ptr
->r
.record
.x
.qp
= predicate
;
2272 static unw_rec_list
*
2273 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2276 unsigned int targ_reg
;
2279 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2280 ptr
->r
.record
.x
.ab
= ab
;
2281 ptr
->r
.record
.x
.reg
= reg
;
2282 ptr
->r
.record
.x
.treg
= targ_reg
;
2283 ptr
->r
.record
.x
.xy
= xy
;
2287 static unw_rec_list
*
2288 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2291 unsigned int targ_reg
;
2293 unsigned int predicate
;
2295 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2296 ptr
->r
.record
.x
.ab
= ab
;
2297 ptr
->r
.record
.x
.reg
= reg
;
2298 ptr
->r
.record
.x
.treg
= targ_reg
;
2299 ptr
->r
.record
.x
.xy
= xy
;
2300 ptr
->r
.record
.x
.qp
= predicate
;
2304 /* Given a unw_rec_list process the correct format with the
2305 specified function. */
2308 process_one_record (ptr
, f
)
2312 unsigned long fr_mask
, gr_mask
;
2314 switch (ptr
->r
.type
)
2320 /* These are taken care of by prologue/prologue_gr. */
2325 if (ptr
->r
.type
== prologue_gr
)
2326 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2327 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2329 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2331 /* Output descriptor(s) for union of register spills (if any). */
2332 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2333 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2336 if ((fr_mask
& ~0xfUL
) == 0)
2337 output_P6_format (f
, fr_mem
, fr_mask
);
2340 output_P5_format (f
, gr_mask
, fr_mask
);
2345 output_P6_format (f
, gr_mem
, gr_mask
);
2346 if (ptr
->r
.record
.r
.mask
.br_mem
)
2347 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2349 /* output imask descriptor if necessary: */
2350 if (ptr
->r
.record
.r
.mask
.i
)
2351 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2352 ptr
->r
.record
.r
.imask_size
);
2356 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2360 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2361 ptr
->r
.record
.p
.size
);
2374 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2377 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2380 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2388 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2397 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2407 case bspstore_sprel
:
2409 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2412 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2415 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2418 as_bad ("spill_mask record unimplemented.");
2420 case priunat_when_gr
:
2421 case priunat_when_mem
:
2425 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2427 case priunat_psprel
:
2429 case bspstore_psprel
:
2431 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2434 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2437 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2441 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2444 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2445 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2446 ptr
->r
.record
.x
.pspoff
);
2449 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2450 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2451 ptr
->r
.record
.x
.spoff
);
2454 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2455 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2456 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2458 case spill_psprel_p
:
2459 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2460 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2461 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2464 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2465 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2466 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2469 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2470 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2471 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2475 as_bad ("record_type_not_valid");
2480 /* Given a unw_rec_list list, process all the records with
2481 the specified function. */
2483 process_unw_records (list
, f
)
2488 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2489 process_one_record (ptr
, f
);
2492 /* Determine the size of a record list in bytes. */
2494 calc_record_size (list
)
2498 process_unw_records (list
, count_output
);
2502 /* Update IMASK bitmask to reflect the fact that one or more registers
2503 of type TYPE are saved starting at instruction with index T. If N
2504 bits are set in REGMASK, it is assumed that instructions T through
2505 T+N-1 save these registers.
2509 1: instruction saves next fp reg
2510 2: instruction saves next general reg
2511 3: instruction saves next branch reg */
2513 set_imask (region
, regmask
, t
, type
)
2514 unw_rec_list
*region
;
2515 unsigned long regmask
;
2519 unsigned char *imask
;
2520 unsigned long imask_size
;
2524 imask
= region
->r
.record
.r
.mask
.i
;
2525 imask_size
= region
->r
.record
.r
.imask_size
;
2528 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2529 imask
= xmalloc (imask_size
);
2530 memset (imask
, 0, imask_size
);
2532 region
->r
.record
.r
.imask_size
= imask_size
;
2533 region
->r
.record
.r
.mask
.i
= imask
;
2537 pos
= 2 * (3 - t
% 4);
2540 if (i
>= imask_size
)
2542 as_bad ("Ignoring attempt to spill beyond end of region");
2546 imask
[i
] |= (type
& 0x3) << pos
;
2548 regmask
&= (regmask
- 1);
2559 count_bits (unsigned long mask
)
2571 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2572 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2573 containing FIRST_ADDR. */
2576 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2577 unsigned long slot_addr
;
2579 unsigned long first_addr
;
2582 unsigned long index
= 0;
2584 /* First time we are called, the initial address and frag are invalid. */
2585 if (first_addr
== 0)
2588 /* If the two addresses are in different frags, then we need to add in
2589 the remaining size of this frag, and then the entire size of intermediate
2591 while (slot_frag
!= first_frag
)
2593 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2595 /* Add in the full size of the frag converted to instruction slots. */
2596 index
+= 3 * (first_frag
->fr_fix
>> 4);
2597 /* Subtract away the initial part before first_addr. */
2598 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2599 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2601 /* Move to the beginning of the next frag. */
2602 first_frag
= first_frag
->fr_next
;
2603 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2606 /* Add in the used part of the last frag. */
2607 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2608 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2612 /* Optimize unwind record directives. */
2614 static unw_rec_list
*
2615 optimize_unw_records (list
)
2621 /* If the only unwind record is ".prologue" or ".prologue" followed
2622 by ".body", then we can optimize the unwind directives away. */
2623 if (list
->r
.type
== prologue
2624 && (list
->next
== NULL
2625 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2631 /* Given a complete record list, process any records which have
2632 unresolved fields, (ie length counts for a prologue). After
2633 this has been run, all neccessary information should be available
2634 within each record to generate an image. */
2637 fixup_unw_records (list
)
2640 unw_rec_list
*ptr
, *region
= 0;
2641 unsigned long first_addr
= 0, rlen
= 0, t
;
2642 fragS
*first_frag
= 0;
2644 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2646 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2647 as_bad (" Insn slot not set in unwind record.");
2648 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2649 first_addr
, first_frag
);
2650 switch (ptr
->r
.type
)
2657 int size
, dir_len
= 0;
2658 unsigned long last_addr
;
2661 first_addr
= ptr
->slot_number
;
2662 first_frag
= ptr
->slot_frag
;
2663 ptr
->slot_number
= 0;
2664 /* Find either the next body/prologue start, or the end of
2665 the list, and determine the size of the region. */
2666 last_addr
= unwind
.next_slot_number
;
2667 last_frag
= unwind
.next_slot_frag
;
2668 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2669 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2670 || last
->r
.type
== body
)
2672 last_addr
= last
->slot_number
;
2673 last_frag
= last
->slot_frag
;
2676 else if (!last
->next
)
2678 /* In the absence of an explicit .body directive,
2679 the prologue ends after the last instruction
2680 covered by an unwind directive. */
2681 if (ptr
->r
.type
!= body
)
2683 last_addr
= last
->slot_number
;
2684 last_frag
= last
->slot_frag
;
2685 switch (last
->r
.type
)
2688 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2689 + count_bits (last
->r
.record
.p
.grmask
));
2693 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2697 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2700 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2709 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2711 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2716 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2727 case priunat_when_gr
:
2728 case priunat_when_mem
:
2732 ptr
->r
.record
.p
.t
= t
;
2740 case spill_psprel_p
:
2741 ptr
->r
.record
.x
.t
= t
;
2747 as_bad ("frgr_mem record before region record!\n");
2750 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2751 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2752 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2753 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2758 as_bad ("fr_mem record before region record!\n");
2761 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2762 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2767 as_bad ("gr_mem record before region record!\n");
2770 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2771 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2776 as_bad ("br_mem record before region record!\n");
2779 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2780 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2786 as_bad ("gr_gr record before region record!\n");
2789 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2794 as_bad ("br_gr record before region record!\n");
2797 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2806 /* Helper routine for output_unw_records. Emits the header for the unwind
2810 setup_unwind_header (int size
, unsigned char **mem
)
2815 /* pad to pointer-size boundry. */
2816 x
= size
% md
.pointer_size
;
2818 extra
= md
.pointer_size
- x
;
2820 /* Add 8 for the header + a pointer for the
2821 personality offset. */
2822 *mem
= xmalloc (size
+ extra
+ 8 + md
.pointer_size
);
2824 /* Clear the padding area and personality. */
2825 memset (*mem
+ 8 + size
, 0 , extra
+ md
.pointer_size
);
2827 /* Initialize the header area. */
2828 if (unwind
.personality_routine
)
2830 if (md
.flags
& EF_IA_64_ABI64
)
2831 flag_value
= (bfd_vma
) 3 << 32;
2833 /* 32-bit unwind info block. */
2834 flag_value
= (bfd_vma
) 0x1003 << 32;
2839 md_number_to_chars (*mem
, (((bfd_vma
) 1 << 48) /* Version. */
2840 | flag_value
/* U & E handler flags. */
2841 | ((size
+ extra
) / md
.pointer_size
)), /* Length. */
2847 /* Generate an unwind image from a record list. Returns the number of
2848 bytes in the resulting image. The memory image itselof is returned
2849 in the 'ptr' parameter. */
2851 output_unw_records (list
, ptr
)
2860 list
= optimize_unw_records (list
);
2861 fixup_unw_records (list
);
2862 size
= calc_record_size (list
);
2864 if (size
> 0 || unwind
.force_unwind_entry
)
2866 unwind
.force_unwind_entry
= 0;
2867 extra
= setup_unwind_header (size
, &mem
);
2869 vbyte_mem_ptr
= mem
+ 8;
2870 process_unw_records (list
, output_vbyte_mem
);
2874 size
+= extra
+ 8 + md
.pointer_size
;
2880 convert_expr_to_ab_reg (e
, ab
, regp
)
2887 if (e
->X_op
!= O_register
)
2890 reg
= e
->X_add_number
;
2891 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2894 *regp
= reg
- REG_GR
;
2896 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2897 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2900 *regp
= reg
- REG_FR
;
2902 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2905 *regp
= reg
- REG_BR
;
2912 case REG_PR
: *regp
= 0; break;
2913 case REG_PSP
: *regp
= 1; break;
2914 case REG_PRIUNAT
: *regp
= 2; break;
2915 case REG_BR
+ 0: *regp
= 3; break;
2916 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2917 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2918 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2919 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2920 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2921 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2922 case REG_AR
+ AR_LC
: *regp
= 10; break;
2932 convert_expr_to_xy_reg (e
, xy
, regp
)
2939 if (e
->X_op
!= O_register
)
2942 reg
= e
->X_add_number
;
2944 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2947 *regp
= reg
- REG_GR
;
2949 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2952 *regp
= reg
- REG_FR
;
2954 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2957 *regp
= reg
- REG_BR
;
2966 int dummy ATTRIBUTE_UNUSED
;
2971 radix
= *input_line_pointer
++;
2973 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2975 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2976 ignore_rest_of_line ();
2981 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
2983 dot_special_section (which
)
2986 set_section ((char *) special_section_name
[which
]);
2990 add_unwind_entry (ptr
)
2994 unwind
.tail
->next
= ptr
;
2999 /* The current entry can in fact be a chain of unwind entries. */
3000 if (unwind
.current_entry
== NULL
)
3001 unwind
.current_entry
= ptr
;
3006 int dummy ATTRIBUTE_UNUSED
;
3012 if (e
.X_op
!= O_constant
)
3013 as_bad ("Operand to .fframe must be a constant");
3015 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
3020 int dummy ATTRIBUTE_UNUSED
;
3026 reg
= e
.X_add_number
- REG_GR
;
3027 if (e
.X_op
== O_register
&& reg
< 128)
3029 add_unwind_entry (output_mem_stack_v ());
3030 if (! (unwind
.prologue_mask
& 2))
3031 add_unwind_entry (output_psp_gr (reg
));
3034 as_bad ("First operand to .vframe must be a general register");
3038 dot_vframesp (dummy
)
3039 int dummy ATTRIBUTE_UNUSED
;
3044 if (e
.X_op
== O_constant
)
3046 add_unwind_entry (output_mem_stack_v ());
3047 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3050 as_bad ("First operand to .vframesp must be a general register");
3054 dot_vframepsp (dummy
)
3055 int dummy ATTRIBUTE_UNUSED
;
3060 if (e
.X_op
== O_constant
)
3062 add_unwind_entry (output_mem_stack_v ());
3063 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3066 as_bad ("First operand to .vframepsp must be a general register");
3071 int dummy ATTRIBUTE_UNUSED
;
3077 sep
= parse_operand (&e1
);
3079 as_bad ("No second operand to .save");
3080 sep
= parse_operand (&e2
);
3082 reg1
= e1
.X_add_number
;
3083 reg2
= e2
.X_add_number
- REG_GR
;
3085 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3086 if (e1
.X_op
== O_register
)
3088 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
3092 case REG_AR
+ AR_BSP
:
3093 add_unwind_entry (output_bsp_when ());
3094 add_unwind_entry (output_bsp_gr (reg2
));
3096 case REG_AR
+ AR_BSPSTORE
:
3097 add_unwind_entry (output_bspstore_when ());
3098 add_unwind_entry (output_bspstore_gr (reg2
));
3100 case REG_AR
+ AR_RNAT
:
3101 add_unwind_entry (output_rnat_when ());
3102 add_unwind_entry (output_rnat_gr (reg2
));
3104 case REG_AR
+ AR_UNAT
:
3105 add_unwind_entry (output_unat_when ());
3106 add_unwind_entry (output_unat_gr (reg2
));
3108 case REG_AR
+ AR_FPSR
:
3109 add_unwind_entry (output_fpsr_when ());
3110 add_unwind_entry (output_fpsr_gr (reg2
));
3112 case REG_AR
+ AR_PFS
:
3113 add_unwind_entry (output_pfs_when ());
3114 if (! (unwind
.prologue_mask
& 4))
3115 add_unwind_entry (output_pfs_gr (reg2
));
3117 case REG_AR
+ AR_LC
:
3118 add_unwind_entry (output_lc_when ());
3119 add_unwind_entry (output_lc_gr (reg2
));
3122 add_unwind_entry (output_rp_when ());
3123 if (! (unwind
.prologue_mask
& 8))
3124 add_unwind_entry (output_rp_gr (reg2
));
3127 add_unwind_entry (output_preds_when ());
3128 if (! (unwind
.prologue_mask
& 1))
3129 add_unwind_entry (output_preds_gr (reg2
));
3132 add_unwind_entry (output_priunat_when_gr ());
3133 add_unwind_entry (output_priunat_gr (reg2
));
3136 as_bad ("First operand not a valid register");
3140 as_bad (" Second operand not a valid register");
3143 as_bad ("First operand not a register");
3148 int dummy ATTRIBUTE_UNUSED
;
3151 unsigned long ecount
; /* # of _additional_ regions to pop */
3154 sep
= parse_operand (&e1
);
3155 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3157 as_bad ("First operand to .restore must be stack pointer (sp)");
3163 parse_operand (&e2
);
3164 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3166 as_bad ("Second operand to .restore must be a constant >= 0");
3169 ecount
= e2
.X_add_number
;
3172 ecount
= unwind
.prologue_count
- 1;
3174 if (ecount
>= unwind
.prologue_count
)
3176 as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)",
3177 ecount
+ 1, unwind
.prologue_count
);
3181 add_unwind_entry (output_epilogue (ecount
));
3183 if (ecount
< unwind
.prologue_count
)
3184 unwind
.prologue_count
-= ecount
+ 1;
3186 unwind
.prologue_count
= 0;
3190 dot_restorereg (dummy
)
3191 int dummy ATTRIBUTE_UNUSED
;
3193 unsigned int ab
, reg
;
3198 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3200 as_bad ("First operand to .restorereg must be a preserved register");
3203 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3207 dot_restorereg_p (dummy
)
3208 int dummy ATTRIBUTE_UNUSED
;
3210 unsigned int qp
, ab
, reg
;
3214 sep
= parse_operand (&e1
);
3217 as_bad ("No second operand to .restorereg.p");
3221 parse_operand (&e2
);
3223 qp
= e1
.X_add_number
- REG_P
;
3224 if (e1
.X_op
!= O_register
|| qp
> 63)
3226 as_bad ("First operand to .restorereg.p must be a predicate");
3230 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3232 as_bad ("Second operand to .restorereg.p must be a preserved register");
3235 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3239 generate_unwind_image (text_name
)
3240 const char *text_name
;
3243 unsigned char *unw_rec
;
3245 /* Force out pending instructions, to make sure all unwind records have
3246 a valid slot_number field. */
3247 ia64_flush_insns ();
3249 /* Generate the unwind record. */
3250 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3251 if (size
% md
.pointer_size
!= 0)
3252 as_bad ("Unwind record is not a multiple of %d bytes.", md
.pointer_size
);
3254 /* If there are unwind records, switch sections, and output the info. */
3257 unsigned char *where
;
3260 bfd_reloc_code_real_type reloc
;
3262 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3263 set_section (sec_name
);
3264 bfd_set_section_flags (stdoutput
, now_seg
,
3265 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3267 /* Make sure the section has 4 byte alignment for ILP32 and
3268 8 byte alignment for LP64. */
3269 frag_align (md
.pointer_size_shift
, 0, 0);
3270 record_alignment (now_seg
, md
.pointer_size_shift
);
3272 /* Set expression which points to start of unwind descriptor area. */
3273 unwind
.info
= expr_build_dot ();
3275 where
= (unsigned char *) frag_more (size
);
3277 /* Issue a label for this address, and keep track of it to put it
3278 in the unwind section. */
3280 /* Copy the information from the unwind record into this section. The
3281 data is already in the correct byte order. */
3282 memcpy (where
, unw_rec
, size
);
3284 /* Add the personality address to the image. */
3285 if (unwind
.personality_routine
!= 0)
3287 exp
.X_op
= O_symbol
;
3288 exp
.X_add_symbol
= unwind
.personality_routine
;
3289 exp
.X_add_number
= 0;
3291 if (md
.flags
& EF_IA_64_BE
)
3293 if (md
.flags
& EF_IA_64_ABI64
)
3294 reloc
= BFD_RELOC_IA64_LTOFF_FPTR64MSB
;
3296 reloc
= BFD_RELOC_IA64_LTOFF_FPTR32MSB
;
3300 if (md
.flags
& EF_IA_64_ABI64
)
3301 reloc
= BFD_RELOC_IA64_LTOFF_FPTR64LSB
;
3303 reloc
= BFD_RELOC_IA64_LTOFF_FPTR32LSB
;
3306 fix_new_exp (frag_now
, frag_now_fix () - md
.pointer_size
,
3307 md
.pointer_size
, & exp
, 0, reloc
);
3308 unwind
.personality_routine
= 0;
3312 free_list_records (unwind
.list
);
3313 free_saved_prologue_counts ();
3314 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3320 dot_handlerdata (dummy
)
3321 int dummy ATTRIBUTE_UNUSED
;
3323 const char *text_name
= segment_name (now_seg
);
3325 /* If text section name starts with ".text" (which it should),
3326 strip this prefix off. */
3327 if (strcmp (text_name
, ".text") == 0)
3330 unwind
.force_unwind_entry
= 1;
3332 /* Remember which segment we're in so we can switch back after .endp */
3333 unwind
.saved_text_seg
= now_seg
;
3334 unwind
.saved_text_subseg
= now_subseg
;
3336 /* Generate unwind info into unwind-info section and then leave that
3337 section as the currently active one so dataXX directives go into
3338 the language specific data area of the unwind info block. */
3339 generate_unwind_image (text_name
);
3340 demand_empty_rest_of_line ();
3344 dot_unwentry (dummy
)
3345 int dummy ATTRIBUTE_UNUSED
;
3347 unwind
.force_unwind_entry
= 1;
3348 demand_empty_rest_of_line ();
3353 int dummy ATTRIBUTE_UNUSED
;
3359 reg
= e
.X_add_number
- REG_BR
;
3360 if (e
.X_op
== O_register
&& reg
< 8)
3361 add_unwind_entry (output_rp_br (reg
));
3363 as_bad ("First operand not a valid branch register");
3367 dot_savemem (psprel
)
3374 sep
= parse_operand (&e1
);
3376 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3377 sep
= parse_operand (&e2
);
3379 reg1
= e1
.X_add_number
;
3380 val
= e2
.X_add_number
;
3382 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3383 if (e1
.X_op
== O_register
)
3385 if (e2
.X_op
== O_constant
)
3389 case REG_AR
+ AR_BSP
:
3390 add_unwind_entry (output_bsp_when ());
3391 add_unwind_entry ((psprel
3393 : output_bsp_sprel
) (val
));
3395 case REG_AR
+ AR_BSPSTORE
:
3396 add_unwind_entry (output_bspstore_when ());
3397 add_unwind_entry ((psprel
3398 ? output_bspstore_psprel
3399 : output_bspstore_sprel
) (val
));
3401 case REG_AR
+ AR_RNAT
:
3402 add_unwind_entry (output_rnat_when ());
3403 add_unwind_entry ((psprel
3404 ? output_rnat_psprel
3405 : output_rnat_sprel
) (val
));
3407 case REG_AR
+ AR_UNAT
:
3408 add_unwind_entry (output_unat_when ());
3409 add_unwind_entry ((psprel
3410 ? output_unat_psprel
3411 : output_unat_sprel
) (val
));
3413 case REG_AR
+ AR_FPSR
:
3414 add_unwind_entry (output_fpsr_when ());
3415 add_unwind_entry ((psprel
3416 ? output_fpsr_psprel
3417 : output_fpsr_sprel
) (val
));
3419 case REG_AR
+ AR_PFS
:
3420 add_unwind_entry (output_pfs_when ());
3421 add_unwind_entry ((psprel
3423 : output_pfs_sprel
) (val
));
3425 case REG_AR
+ AR_LC
:
3426 add_unwind_entry (output_lc_when ());
3427 add_unwind_entry ((psprel
3429 : output_lc_sprel
) (val
));
3432 add_unwind_entry (output_rp_when ());
3433 add_unwind_entry ((psprel
3435 : output_rp_sprel
) (val
));
3438 add_unwind_entry (output_preds_when ());
3439 add_unwind_entry ((psprel
3440 ? output_preds_psprel
3441 : output_preds_sprel
) (val
));
3444 add_unwind_entry (output_priunat_when_mem ());
3445 add_unwind_entry ((psprel
3446 ? output_priunat_psprel
3447 : output_priunat_sprel
) (val
));
3450 as_bad ("First operand not a valid register");
3454 as_bad (" Second operand not a valid constant");
3457 as_bad ("First operand not a register");
3462 int dummy ATTRIBUTE_UNUSED
;
3466 sep
= parse_operand (&e1
);
3468 parse_operand (&e2
);
3470 if (e1
.X_op
!= O_constant
)
3471 as_bad ("First operand to .save.g must be a constant.");
3474 int grmask
= e1
.X_add_number
;
3476 add_unwind_entry (output_gr_mem (grmask
));
3479 int reg
= e2
.X_add_number
- REG_GR
;
3480 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3481 add_unwind_entry (output_gr_gr (grmask
, reg
));
3483 as_bad ("Second operand is an invalid register.");
3490 int dummy ATTRIBUTE_UNUSED
;
3494 sep
= parse_operand (&e1
);
3496 if (e1
.X_op
!= O_constant
)
3497 as_bad ("Operand to .save.f must be a constant.");
3499 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3504 int dummy ATTRIBUTE_UNUSED
;
3511 sep
= parse_operand (&e1
);
3512 if (e1
.X_op
!= O_constant
)
3514 as_bad ("First operand to .save.b must be a constant.");
3517 brmask
= e1
.X_add_number
;
3521 sep
= parse_operand (&e2
);
3522 reg
= e2
.X_add_number
- REG_GR
;
3523 if (e2
.X_op
!= O_register
|| reg
> 127)
3525 as_bad ("Second operand to .save.b must be a general register.");
3528 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3531 add_unwind_entry (output_br_mem (brmask
));
3533 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3534 ignore_rest_of_line ();
3539 int dummy ATTRIBUTE_UNUSED
;
3543 sep
= parse_operand (&e1
);
3545 parse_operand (&e2
);
3547 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3548 as_bad ("Both operands of .save.gf must be constants.");
3551 int grmask
= e1
.X_add_number
;
3552 int frmask
= e2
.X_add_number
;
3553 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3559 int dummy ATTRIBUTE_UNUSED
;
3564 sep
= parse_operand (&e
);
3565 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3566 ignore_rest_of_line ();
3568 if (e
.X_op
!= O_constant
)
3569 as_bad ("Operand to .spill must be a constant");
3571 add_unwind_entry (output_spill_base (e
.X_add_number
));
3575 dot_spillreg (dummy
)
3576 int dummy ATTRIBUTE_UNUSED
;
3578 int sep
, ab
, xy
, reg
, treg
;
3581 sep
= parse_operand (&e1
);
3584 as_bad ("No second operand to .spillreg");
3588 parse_operand (&e2
);
3590 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3592 as_bad ("First operand to .spillreg must be a preserved register");
3596 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3598 as_bad ("Second operand to .spillreg must be a register");
3602 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3606 dot_spillmem (psprel
)
3612 sep
= parse_operand (&e1
);
3615 as_bad ("Second operand missing");
3619 parse_operand (&e2
);
3621 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3623 as_bad ("First operand to .spill%s must be a preserved register",
3624 psprel
? "psp" : "sp");
3628 if (e2
.X_op
!= O_constant
)
3630 as_bad ("Second operand to .spill%s must be a constant",
3631 psprel
? "psp" : "sp");
3636 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3638 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3642 dot_spillreg_p (dummy
)
3643 int dummy ATTRIBUTE_UNUSED
;
3645 int sep
, ab
, xy
, reg
, treg
;
3646 expressionS e1
, e2
, e3
;
3649 sep
= parse_operand (&e1
);
3652 as_bad ("No second and third operand to .spillreg.p");
3656 sep
= parse_operand (&e2
);
3659 as_bad ("No third operand to .spillreg.p");
3663 parse_operand (&e3
);
3665 qp
= e1
.X_add_number
- REG_P
;
3667 if (e1
.X_op
!= O_register
|| qp
> 63)
3669 as_bad ("First operand to .spillreg.p must be a predicate");
3673 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3675 as_bad ("Second operand to .spillreg.p must be a preserved register");
3679 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3681 as_bad ("Third operand to .spillreg.p must be a register");
3685 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3689 dot_spillmem_p (psprel
)
3692 expressionS e1
, e2
, e3
;
3696 sep
= parse_operand (&e1
);
3699 as_bad ("Second operand missing");
3703 parse_operand (&e2
);
3706 as_bad ("Second operand missing");
3710 parse_operand (&e3
);
3712 qp
= e1
.X_add_number
- REG_P
;
3713 if (e1
.X_op
!= O_register
|| qp
> 63)
3715 as_bad ("First operand to .spill%s_p must be a predicate",
3716 psprel
? "psp" : "sp");
3720 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3722 as_bad ("Second operand to .spill%s_p must be a preserved register",
3723 psprel
? "psp" : "sp");
3727 if (e3
.X_op
!= O_constant
)
3729 as_bad ("Third operand to .spill%s_p must be a constant",
3730 psprel
? "psp" : "sp");
3735 add_unwind_entry (output_spill_psprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3737 add_unwind_entry (output_spill_sprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3741 get_saved_prologue_count (lbl
)
3744 label_prologue_count
*lpc
= unwind
.saved_prologue_counts
;
3746 while (lpc
!= NULL
&& lpc
->label_number
!= lbl
)
3750 return lpc
->prologue_count
;
3752 as_bad ("Missing .label_state %ld", lbl
);
3757 save_prologue_count (lbl
, count
)
3761 label_prologue_count
*lpc
= unwind
.saved_prologue_counts
;
3763 while (lpc
!= NULL
&& lpc
->label_number
!= lbl
)
3767 lpc
->prologue_count
= count
;
3770 label_prologue_count
* new_lpc
= xmalloc (sizeof (* new_lpc
));
3772 new_lpc
->next
= unwind
.saved_prologue_counts
;
3773 new_lpc
->label_number
= lbl
;
3774 new_lpc
->prologue_count
= count
;
3775 unwind
.saved_prologue_counts
= new_lpc
;
3780 free_saved_prologue_counts ()
3782 label_prologue_count
* lpc
= unwind
.saved_prologue_counts
;
3783 label_prologue_count
* next
;
3792 unwind
.saved_prologue_counts
= NULL
;
3796 dot_label_state (dummy
)
3797 int dummy ATTRIBUTE_UNUSED
;
3802 if (e
.X_op
!= O_constant
)
3804 as_bad ("Operand to .label_state must be a constant");
3807 add_unwind_entry (output_label_state (e
.X_add_number
));
3808 save_prologue_count (e
.X_add_number
, unwind
.prologue_count
);
3812 dot_copy_state (dummy
)
3813 int dummy ATTRIBUTE_UNUSED
;
3818 if (e
.X_op
!= O_constant
)
3820 as_bad ("Operand to .copy_state must be a constant");
3823 add_unwind_entry (output_copy_state (e
.X_add_number
));
3824 unwind
.prologue_count
= get_saved_prologue_count (e
.X_add_number
);
3829 int dummy ATTRIBUTE_UNUSED
;
3834 sep
= parse_operand (&e1
);
3837 as_bad ("Second operand to .unwabi missing");
3840 sep
= parse_operand (&e2
);
3841 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3842 ignore_rest_of_line ();
3844 if (e1
.X_op
!= O_constant
)
3846 as_bad ("First operand to .unwabi must be a constant");
3850 if (e2
.X_op
!= O_constant
)
3852 as_bad ("Second operand to .unwabi must be a constant");
3856 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3860 dot_personality (dummy
)
3861 int dummy ATTRIBUTE_UNUSED
;
3865 name
= input_line_pointer
;
3866 c
= get_symbol_end ();
3867 p
= input_line_pointer
;
3868 unwind
.personality_routine
= symbol_find_or_make (name
);
3869 unwind
.force_unwind_entry
= 1;
3872 demand_empty_rest_of_line ();
3877 int dummy ATTRIBUTE_UNUSED
;
3882 unwind
.proc_start
= expr_build_dot ();
3883 /* Parse names of main and alternate entry points and mark them as
3884 function symbols: */
3888 name
= input_line_pointer
;
3889 c
= get_symbol_end ();
3890 p
= input_line_pointer
;
3891 sym
= symbol_find_or_make (name
);
3892 if (unwind
.proc_start
== 0)
3894 unwind
.proc_start
= sym
;
3896 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3899 if (*input_line_pointer
!= ',')
3901 ++input_line_pointer
;
3903 demand_empty_rest_of_line ();
3906 unwind
.prologue_count
= 0;
3907 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3908 unwind
.personality_routine
= 0;
3913 int dummy ATTRIBUTE_UNUSED
;
3915 unwind
.prologue
= 0;
3916 unwind
.prologue_mask
= 0;
3918 add_unwind_entry (output_body ());
3919 demand_empty_rest_of_line ();
3923 dot_prologue (dummy
)
3924 int dummy ATTRIBUTE_UNUSED
;
3927 int mask
= 0, grsave
= 0;
3929 if (!is_it_end_of_statement ())
3932 sep
= parse_operand (&e1
);
3934 as_bad ("No second operand to .prologue");
3935 sep
= parse_operand (&e2
);
3936 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3937 ignore_rest_of_line ();
3939 if (e1
.X_op
== O_constant
)
3941 mask
= e1
.X_add_number
;
3943 if (e2
.X_op
== O_constant
)
3944 grsave
= e2
.X_add_number
;
3945 else if (e2
.X_op
== O_register
3946 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3949 as_bad ("Second operand not a constant or general register");
3951 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3954 as_bad ("First operand not a constant");
3957 add_unwind_entry (output_prologue ());
3959 unwind
.prologue
= 1;
3960 unwind
.prologue_mask
= mask
;
3961 ++unwind
.prologue_count
;
3966 int dummy ATTRIBUTE_UNUSED
;
3970 int bytes_per_address
;
3973 subsegT saved_subseg
;
3974 const char *sec_name
, *text_name
;
3978 if (unwind
.saved_text_seg
)
3980 saved_seg
= unwind
.saved_text_seg
;
3981 saved_subseg
= unwind
.saved_text_subseg
;
3982 unwind
.saved_text_seg
= NULL
;
3986 saved_seg
= now_seg
;
3987 saved_subseg
= now_subseg
;
3991 Use a slightly ugly scheme to derive the unwind section names from
3992 the text section name:
3994 text sect. unwind table sect.
3995 name: name: comments:
3996 ---------- ----------------- --------------------------------
3998 .text.foo .IA_64.unwind.text.foo
3999 .foo .IA_64.unwind.foo
4001 .gnu.linkonce.ia64unw.foo
4002 _info .IA_64.unwind_info gas issues error message (ditto)
4003 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
4005 This mapping is done so that:
4007 (a) An object file with unwind info only in .text will use
4008 unwind section names .IA_64.unwind and .IA_64.unwind_info.
4009 This follows the letter of the ABI and also ensures backwards
4010 compatibility with older toolchains.
4012 (b) An object file with unwind info in multiple text sections
4013 will use separate unwind sections for each text section.
4014 This allows us to properly set the "sh_info" and "sh_link"
4015 fields in SHT_IA_64_UNWIND as required by the ABI and also
4016 lets GNU ld support programs with multiple segments
4017 containing unwind info (as might be the case for certain
4018 embedded applications).
4020 (c) An error is issued if there would be a name clash.
4022 text_name
= segment_name (saved_seg
);
4023 if (strncmp (text_name
, "_info", 5) == 0)
4025 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
4027 ignore_rest_of_line ();
4030 if (strcmp (text_name
, ".text") == 0)
4033 insn_group_break (1, 0, 0);
4035 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
4037 generate_unwind_image (text_name
);
4039 if (unwind
.info
|| unwind
.force_unwind_entry
)
4041 subseg_set (md
.last_text_seg
, 0);
4042 unwind
.proc_end
= expr_build_dot ();
4044 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
4045 set_section ((char *) sec_name
);
4046 bfd_set_section_flags (stdoutput
, now_seg
,
4047 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
4049 /* Make sure that section has 4 byte alignment for ILP32 and
4050 8 byte alignment for LP64. */
4051 record_alignment (now_seg
, md
.pointer_size_shift
);
4053 /* Need space for 3 pointers for procedure start, procedure end,
4055 ptr
= frag_more (3 * md
.pointer_size
);
4056 where
= frag_now_fix () - (3 * md
.pointer_size
);
4057 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
4059 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
4060 e
.X_op
= O_pseudo_fixup
;
4061 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4063 e
.X_add_symbol
= unwind
.proc_start
;
4064 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
4066 e
.X_op
= O_pseudo_fixup
;
4067 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4069 e
.X_add_symbol
= unwind
.proc_end
;
4070 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
4071 bytes_per_address
, &e
);
4075 e
.X_op
= O_pseudo_fixup
;
4076 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4078 e
.X_add_symbol
= unwind
.info
;
4079 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
4080 bytes_per_address
, &e
);
4083 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
4087 subseg_set (saved_seg
, saved_subseg
);
4089 /* Parse names of main and alternate entry points and set symbol sizes. */
4093 name
= input_line_pointer
;
4094 c
= get_symbol_end ();
4095 p
= input_line_pointer
;
4096 sym
= symbol_find (name
);
4097 if (sym
&& unwind
.proc_start
4098 && (symbol_get_bfdsym (sym
)->flags
& BSF_FUNCTION
)
4099 && S_GET_SIZE (sym
) == 0 && symbol_get_obj (sym
)->size
== NULL
)
4101 fragS
*fr
= symbol_get_frag (unwind
.proc_start
);
4102 fragS
*frag
= symbol_get_frag (sym
);
4104 /* Check whether the function label is at or beyond last
4106 while (fr
&& fr
!= frag
)
4110 if (frag
== frag_now
&& SEG_NORMAL (now_seg
))
4111 S_SET_SIZE (sym
, frag_now_fix () - S_GET_VALUE (sym
));
4114 symbol_get_obj (sym
)->size
=
4115 (expressionS
*) xmalloc (sizeof (expressionS
));
4116 symbol_get_obj (sym
)->size
->X_op
= O_subtract
;
4117 symbol_get_obj (sym
)->size
->X_add_symbol
4118 = symbol_new (FAKE_LABEL_NAME
, now_seg
,
4119 frag_now_fix (), frag_now
);
4120 symbol_get_obj (sym
)->size
->X_op_symbol
= sym
;
4121 symbol_get_obj (sym
)->size
->X_add_number
= 0;
4127 if (*input_line_pointer
!= ',')
4129 ++input_line_pointer
;
4131 demand_empty_rest_of_line ();
4132 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
4136 dot_template (template)
4139 CURR_SLOT
.user_template
= template;
4144 int dummy ATTRIBUTE_UNUSED
;
4146 int ins
, locs
, outs
, rots
;
4148 if (is_it_end_of_statement ())
4149 ins
= locs
= outs
= rots
= 0;
4152 ins
= get_absolute_expression ();
4153 if (*input_line_pointer
++ != ',')
4155 locs
= get_absolute_expression ();
4156 if (*input_line_pointer
++ != ',')
4158 outs
= get_absolute_expression ();
4159 if (*input_line_pointer
++ != ',')
4161 rots
= get_absolute_expression ();
4163 set_regstack (ins
, locs
, outs
, rots
);
4167 as_bad ("Comma expected");
4168 ignore_rest_of_line ();
4175 unsigned num_regs
, num_alloced
= 0;
4176 struct dynreg
**drpp
, *dr
;
4177 int ch
, base_reg
= 0;
4183 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
4184 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
4185 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
4189 /* First, remove existing names from hash table. */
4190 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
4192 hash_delete (md
.dynreg_hash
, dr
->name
);
4196 drpp
= &md
.dynreg
[type
];
4199 start
= input_line_pointer
;
4200 ch
= get_symbol_end ();
4201 *input_line_pointer
= ch
;
4202 len
= (input_line_pointer
- start
);
4205 if (*input_line_pointer
!= '[')
4207 as_bad ("Expected '['");
4210 ++input_line_pointer
; /* skip '[' */
4212 num_regs
= get_absolute_expression ();
4214 if (*input_line_pointer
++ != ']')
4216 as_bad ("Expected ']'");
4221 num_alloced
+= num_regs
;
4225 if (num_alloced
> md
.rot
.num_regs
)
4227 as_bad ("Used more than the declared %d rotating registers",
4233 if (num_alloced
> 96)
4235 as_bad ("Used more than the available 96 rotating registers");
4240 if (num_alloced
> 48)
4242 as_bad ("Used more than the available 48 rotating registers");
4251 name
= obstack_alloc (¬es
, len
+ 1);
4252 memcpy (name
, start
, len
);
4257 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4258 memset (*drpp
, 0, sizeof (*dr
));
4263 dr
->num_regs
= num_regs
;
4264 dr
->base
= base_reg
;
4266 base_reg
+= num_regs
;
4268 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4270 as_bad ("Attempt to redefine register set `%s'", name
);
4274 if (*input_line_pointer
!= ',')
4276 ++input_line_pointer
; /* skip comma */
4279 demand_empty_rest_of_line ();
4283 ignore_rest_of_line ();
4287 dot_byteorder (byteorder
)
4290 target_big_endian
= byteorder
;
4295 int dummy ATTRIBUTE_UNUSED
;
4302 option
= input_line_pointer
;
4303 ch
= get_symbol_end ();
4304 if (strcmp (option
, "lsb") == 0)
4305 md
.flags
&= ~EF_IA_64_BE
;
4306 else if (strcmp (option
, "msb") == 0)
4307 md
.flags
|= EF_IA_64_BE
;
4308 else if (strcmp (option
, "abi32") == 0)
4309 md
.flags
&= ~EF_IA_64_ABI64
;
4310 else if (strcmp (option
, "abi64") == 0)
4311 md
.flags
|= EF_IA_64_ABI64
;
4313 as_bad ("Unknown psr option `%s'", option
);
4314 *input_line_pointer
= ch
;
4317 if (*input_line_pointer
!= ',')
4320 ++input_line_pointer
;
4323 demand_empty_rest_of_line ();
4328 int dummy ATTRIBUTE_UNUSED
;
4330 as_bad (".alias not implemented yet");
4335 int dummy ATTRIBUTE_UNUSED
;
4337 new_logical_line (0, get_absolute_expression ());
4338 demand_empty_rest_of_line ();
4342 parse_section_name ()
4348 if (*input_line_pointer
!= '"')
4350 as_bad ("Missing section name");
4351 ignore_rest_of_line ();
4354 name
= demand_copy_C_string (&len
);
4357 ignore_rest_of_line ();
4361 if (*input_line_pointer
!= ',')
4363 as_bad ("Comma expected after section name");
4364 ignore_rest_of_line ();
4367 ++input_line_pointer
; /* skip comma */
4375 char *name
= parse_section_name ();
4379 md
.keep_pending_output
= 1;
4382 obj_elf_previous (0);
4383 md
.keep_pending_output
= 0;
4386 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4389 stmt_float_cons (kind
)
4396 case 'd': size
= 8; break;
4397 case 'x': size
= 10; break;
4404 ia64_do_align (size
);
4412 int saved_auto_align
= md
.auto_align
;
4416 md
.auto_align
= saved_auto_align
;
4420 dot_xfloat_cons (kind
)
4423 char *name
= parse_section_name ();
4427 md
.keep_pending_output
= 1;
4429 stmt_float_cons (kind
);
4430 obj_elf_previous (0);
4431 md
.keep_pending_output
= 0;
4435 dot_xstringer (zero
)
4438 char *name
= parse_section_name ();
4442 md
.keep_pending_output
= 1;
4445 obj_elf_previous (0);
4446 md
.keep_pending_output
= 0;
4453 int saved_auto_align
= md
.auto_align
;
4454 char *name
= parse_section_name ();
4458 md
.keep_pending_output
= 1;
4462 md
.auto_align
= saved_auto_align
;
4463 obj_elf_previous (0);
4464 md
.keep_pending_output
= 0;
4468 dot_xfloat_cons_ua (kind
)
4471 int saved_auto_align
= md
.auto_align
;
4472 char *name
= parse_section_name ();
4476 md
.keep_pending_output
= 1;
4479 stmt_float_cons (kind
);
4480 md
.auto_align
= saved_auto_align
;
4481 obj_elf_previous (0);
4482 md
.keep_pending_output
= 0;
4485 /* .reg.val <regname>,value */
4489 int dummy ATTRIBUTE_UNUSED
;
4494 if (reg
.X_op
!= O_register
)
4496 as_bad (_("Register name expected"));
4497 ignore_rest_of_line ();
4499 else if (*input_line_pointer
++ != ',')
4501 as_bad (_("Comma expected"));
4502 ignore_rest_of_line ();
4506 valueT value
= get_absolute_expression ();
4507 int regno
= reg
.X_add_number
;
4508 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4509 as_warn (_("Register value annotation ignored"));
4512 gr_values
[regno
- REG_GR
].known
= 1;
4513 gr_values
[regno
- REG_GR
].value
= value
;
4514 gr_values
[regno
- REG_GR
].path
= md
.path
;
4517 demand_empty_rest_of_line ();
4520 /* select dv checking mode
4525 A stop is inserted when changing modes
4532 if (md
.manual_bundling
)
4533 as_warn (_("Directive invalid within a bundle"));
4535 if (type
== 'E' || type
== 'A')
4536 md
.mode_explicitly_set
= 0;
4538 md
.mode_explicitly_set
= 1;
4545 if (md
.explicit_mode
)
4546 insn_group_break (1, 0, 0);
4547 md
.explicit_mode
= 0;
4551 if (!md
.explicit_mode
)
4552 insn_group_break (1, 0, 0);
4553 md
.explicit_mode
= 1;
4557 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4558 insn_group_break (1, 0, 0);
4559 md
.explicit_mode
= md
.default_explicit_mode
;
4560 md
.mode_explicitly_set
= 0;
4571 for (regno
= 0; regno
< 64; regno
++)
4573 if (mask
& ((valueT
) 1 << regno
))
4575 fprintf (stderr
, "%s p%d", comma
, regno
);
4582 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4583 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4584 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4585 .pred.safe_across_calls p1 [, p2 [,...]]
4594 int p1
= -1, p2
= -1;
4598 if (*input_line_pointer
!= '"')
4600 as_bad (_("Missing predicate relation type"));
4601 ignore_rest_of_line ();
4607 char *form
= demand_copy_C_string (&len
);
4608 if (strcmp (form
, "mutex") == 0)
4610 else if (strcmp (form
, "clear") == 0)
4612 else if (strcmp (form
, "imply") == 0)
4616 as_bad (_("Unrecognized predicate relation type"));
4617 ignore_rest_of_line ();
4621 if (*input_line_pointer
== ',')
4622 ++input_line_pointer
;
4632 if (TOUPPER (*input_line_pointer
) != 'P'
4633 || (regno
= atoi (++input_line_pointer
)) < 0
4636 as_bad (_("Predicate register expected"));
4637 ignore_rest_of_line ();
4640 while (ISDIGIT (*input_line_pointer
))
4641 ++input_line_pointer
;
4648 as_warn (_("Duplicate predicate register ignored"));
4651 /* See if it's a range. */
4652 if (*input_line_pointer
== '-')
4655 ++input_line_pointer
;
4657 if (TOUPPER (*input_line_pointer
) != 'P'
4658 || (regno
= atoi (++input_line_pointer
)) < 0
4661 as_bad (_("Predicate register expected"));
4662 ignore_rest_of_line ();
4665 while (ISDIGIT (*input_line_pointer
))
4666 ++input_line_pointer
;
4670 as_bad (_("Bad register range"));
4671 ignore_rest_of_line ();
4682 if (*input_line_pointer
!= ',')
4684 ++input_line_pointer
;
4693 clear_qp_mutex (mask
);
4694 clear_qp_implies (mask
, (valueT
) 0);
4697 if (count
!= 2 || p1
== -1 || p2
== -1)
4698 as_bad (_("Predicate source and target required"));
4699 else if (p1
== 0 || p2
== 0)
4700 as_bad (_("Use of p0 is not valid in this context"));
4702 add_qp_imply (p1
, p2
);
4707 as_bad (_("At least two PR arguments expected"));
4712 as_bad (_("Use of p0 is not valid in this context"));
4715 add_qp_mutex (mask
);
4718 /* note that we don't override any existing relations */
4721 as_bad (_("At least one PR argument expected"));
4726 fprintf (stderr
, "Safe across calls: ");
4727 print_prmask (mask
);
4728 fprintf (stderr
, "\n");
4730 qp_safe_across_calls
= mask
;
4733 demand_empty_rest_of_line ();
4736 /* .entry label [, label [, ...]]
4737 Hint to DV code that the given labels are to be considered entry points.
4738 Otherwise, only global labels are considered entry points. */
4742 int dummy ATTRIBUTE_UNUSED
;
4751 name
= input_line_pointer
;
4752 c
= get_symbol_end ();
4753 symbolP
= symbol_find_or_make (name
);
4755 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4757 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4760 *input_line_pointer
= c
;
4762 c
= *input_line_pointer
;
4765 input_line_pointer
++;
4767 if (*input_line_pointer
== '\n')
4773 demand_empty_rest_of_line ();
4776 /* .mem.offset offset, base
4777 "base" is used to distinguish between offsets from a different base. */
4780 dot_mem_offset (dummy
)
4781 int dummy ATTRIBUTE_UNUSED
;
4783 md
.mem_offset
.hint
= 1;
4784 md
.mem_offset
.offset
= get_absolute_expression ();
4785 if (*input_line_pointer
!= ',')
4787 as_bad (_("Comma expected"));
4788 ignore_rest_of_line ();
4791 ++input_line_pointer
;
4792 md
.mem_offset
.base
= get_absolute_expression ();
4793 demand_empty_rest_of_line ();
4796 /* ia64-specific pseudo-ops: */
4797 const pseudo_typeS md_pseudo_table
[] =
4799 { "radix", dot_radix
, 0 },
4800 { "lcomm", s_lcomm_bytes
, 1 },
4801 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4802 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4803 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4804 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4805 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4806 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4807 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4808 { "init_array", dot_special_section
, SPECIAL_SECTION_INIT_ARRAY
},
4809 { "fini_array", dot_special_section
, SPECIAL_SECTION_FINI_ARRAY
},
4810 { "proc", dot_proc
, 0 },
4811 { "body", dot_body
, 0 },
4812 { "prologue", dot_prologue
, 0 },
4813 { "endp", dot_endp
, 0 },
4814 { "file", dwarf2_directive_file
, 0 },
4815 { "loc", dwarf2_directive_loc
, 0 },
4817 { "fframe", dot_fframe
, 0 },
4818 { "vframe", dot_vframe
, 0 },
4819 { "vframesp", dot_vframesp
, 0 },
4820 { "vframepsp", dot_vframepsp
, 0 },
4821 { "save", dot_save
, 0 },
4822 { "restore", dot_restore
, 0 },
4823 { "restorereg", dot_restorereg
, 0 },
4824 { "restorereg.p", dot_restorereg_p
, 0 },
4825 { "handlerdata", dot_handlerdata
, 0 },
4826 { "unwentry", dot_unwentry
, 0 },
4827 { "altrp", dot_altrp
, 0 },
4828 { "savesp", dot_savemem
, 0 },
4829 { "savepsp", dot_savemem
, 1 },
4830 { "save.g", dot_saveg
, 0 },
4831 { "save.f", dot_savef
, 0 },
4832 { "save.b", dot_saveb
, 0 },
4833 { "save.gf", dot_savegf
, 0 },
4834 { "spill", dot_spill
, 0 },
4835 { "spillreg", dot_spillreg
, 0 },
4836 { "spillsp", dot_spillmem
, 0 },
4837 { "spillpsp", dot_spillmem
, 1 },
4838 { "spillreg.p", dot_spillreg_p
, 0 },
4839 { "spillsp.p", dot_spillmem_p
, 0 },
4840 { "spillpsp.p", dot_spillmem_p
, 1 },
4841 { "label_state", dot_label_state
, 0 },
4842 { "copy_state", dot_copy_state
, 0 },
4843 { "unwabi", dot_unwabi
, 0 },
4844 { "personality", dot_personality
, 0 },
4846 { "estate", dot_estate
, 0 },
4848 { "mii", dot_template
, 0x0 },
4849 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4850 { "mlx", dot_template
, 0x2 },
4851 { "mmi", dot_template
, 0x4 },
4852 { "mfi", dot_template
, 0x6 },
4853 { "mmf", dot_template
, 0x7 },
4854 { "mib", dot_template
, 0x8 },
4855 { "mbb", dot_template
, 0x9 },
4856 { "bbb", dot_template
, 0xb },
4857 { "mmb", dot_template
, 0xc },
4858 { "mfb", dot_template
, 0xe },
4860 { "lb", dot_scope
, 0 },
4861 { "le", dot_scope
, 1 },
4863 { "align", s_align_bytes
, 0 },
4864 { "regstk", dot_regstk
, 0 },
4865 { "rotr", dot_rot
, DYNREG_GR
},
4866 { "rotf", dot_rot
, DYNREG_FR
},
4867 { "rotp", dot_rot
, DYNREG_PR
},
4868 { "lsb", dot_byteorder
, 0 },
4869 { "msb", dot_byteorder
, 1 },
4870 { "psr", dot_psr
, 0 },
4871 { "alias", dot_alias
, 0 },
4872 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4874 { "xdata1", dot_xdata
, 1 },
4875 { "xdata2", dot_xdata
, 2 },
4876 { "xdata4", dot_xdata
, 4 },
4877 { "xdata8", dot_xdata
, 8 },
4878 { "xreal4", dot_xfloat_cons
, 'f' },
4879 { "xreal8", dot_xfloat_cons
, 'd' },
4880 { "xreal10", dot_xfloat_cons
, 'x' },
4881 { "xstring", dot_xstringer
, 0 },
4882 { "xstringz", dot_xstringer
, 1 },
4884 /* unaligned versions: */
4885 { "xdata2.ua", dot_xdata_ua
, 2 },
4886 { "xdata4.ua", dot_xdata_ua
, 4 },
4887 { "xdata8.ua", dot_xdata_ua
, 8 },
4888 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4889 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4890 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4892 /* annotations/DV checking support */
4893 { "entry", dot_entry
, 0 },
4894 { "mem.offset", dot_mem_offset
, 0 },
4895 { "pred.rel", dot_pred_rel
, 0 },
4896 { "pred.rel.clear", dot_pred_rel
, 'c' },
4897 { "pred.rel.imply", dot_pred_rel
, 'i' },
4898 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4899 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4900 { "reg.val", dot_reg_val
, 0 },
4901 { "auto", dot_dv_mode
, 'a' },
4902 { "explicit", dot_dv_mode
, 'e' },
4903 { "default", dot_dv_mode
, 'd' },
4905 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4906 IA-64 aligns data allocation pseudo-ops by default, so we have to
4907 tell it that these ones are supposed to be unaligned. Long term,
4908 should rewrite so that only IA-64 specific data allocation pseudo-ops
4909 are aligned by default. */
4910 {"2byte", stmt_cons_ua
, 2},
4911 {"4byte", stmt_cons_ua
, 4},
4912 {"8byte", stmt_cons_ua
, 8},
4917 static const struct pseudo_opcode
4920 void (*handler
) (int);
4925 /* these are more like pseudo-ops, but don't start with a dot */
4926 { "data1", cons
, 1 },
4927 { "data2", cons
, 2 },
4928 { "data4", cons
, 4 },
4929 { "data8", cons
, 8 },
4930 { "data16", cons
, 16 },
4931 { "real4", stmt_float_cons
, 'f' },
4932 { "real8", stmt_float_cons
, 'd' },
4933 { "real10", stmt_float_cons
, 'x' },
4934 { "string", stringer
, 0 },
4935 { "stringz", stringer
, 1 },
4937 /* unaligned versions: */
4938 { "data2.ua", stmt_cons_ua
, 2 },
4939 { "data4.ua", stmt_cons_ua
, 4 },
4940 { "data8.ua", stmt_cons_ua
, 8 },
4941 { "data16.ua", stmt_cons_ua
, 16 },
4942 { "real4.ua", float_cons
, 'f' },
4943 { "real8.ua", float_cons
, 'd' },
4944 { "real10.ua", float_cons
, 'x' },
4947 /* Declare a register by creating a symbol for it and entering it in
4948 the symbol table. */
4951 declare_register (name
, regnum
)
4958 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4960 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4962 as_fatal ("Inserting \"%s\" into register table failed: %s",
4969 declare_register_set (prefix
, num_regs
, base_regnum
)
4977 for (i
= 0; i
< num_regs
; ++i
)
4979 sprintf (name
, "%s%u", prefix
, i
);
4980 declare_register (name
, base_regnum
+ i
);
4985 operand_width (opnd
)
4986 enum ia64_opnd opnd
;
4988 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
4989 unsigned int bits
= 0;
4993 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
4994 bits
+= odesc
->field
[i
].bits
;
4999 static enum operand_match_result
5000 operand_match (idesc
, index
, e
)
5001 const struct ia64_opcode
*idesc
;
5005 enum ia64_opnd opnd
= idesc
->operands
[index
];
5006 int bits
, relocatable
= 0;
5007 struct insn_fix
*fix
;
5014 case IA64_OPND_AR_CCV
:
5015 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
5016 return OPERAND_MATCH
;
5019 case IA64_OPND_AR_PFS
:
5020 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
5021 return OPERAND_MATCH
;
5025 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
5026 return OPERAND_MATCH
;
5030 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
5031 return OPERAND_MATCH
;
5035 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
5036 return OPERAND_MATCH
;
5039 case IA64_OPND_PR_ROT
:
5040 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
5041 return OPERAND_MATCH
;
5045 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
5046 return OPERAND_MATCH
;
5049 case IA64_OPND_PSR_L
:
5050 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
5051 return OPERAND_MATCH
;
5054 case IA64_OPND_PSR_UM
:
5055 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
5056 return OPERAND_MATCH
;
5060 if (e
->X_op
== O_constant
)
5062 if (e
->X_add_number
== 1)
5063 return OPERAND_MATCH
;
5065 return OPERAND_OUT_OF_RANGE
;
5070 if (e
->X_op
== O_constant
)
5072 if (e
->X_add_number
== 8)
5073 return OPERAND_MATCH
;
5075 return OPERAND_OUT_OF_RANGE
;
5080 if (e
->X_op
== O_constant
)
5082 if (e
->X_add_number
== 16)
5083 return OPERAND_MATCH
;
5085 return OPERAND_OUT_OF_RANGE
;
5089 /* register operands: */
5092 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
5093 && e
->X_add_number
< REG_AR
+ 128)
5094 return OPERAND_MATCH
;
5099 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
5100 && e
->X_add_number
< REG_BR
+ 8)
5101 return OPERAND_MATCH
;
5105 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
5106 && e
->X_add_number
< REG_CR
+ 128)
5107 return OPERAND_MATCH
;
5114 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
5115 && e
->X_add_number
< REG_FR
+ 128)
5116 return OPERAND_MATCH
;
5121 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
5122 && e
->X_add_number
< REG_P
+ 64)
5123 return OPERAND_MATCH
;
5129 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
5130 && e
->X_add_number
< REG_GR
+ 128)
5131 return OPERAND_MATCH
;
5134 case IA64_OPND_R3_2
:
5135 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
)
5137 if (e
->X_add_number
< REG_GR
+ 4)
5138 return OPERAND_MATCH
;
5139 else if (e
->X_add_number
< REG_GR
+ 128)
5140 return OPERAND_OUT_OF_RANGE
;
5144 /* indirect operands: */
5145 case IA64_OPND_CPUID_R3
:
5146 case IA64_OPND_DBR_R3
:
5147 case IA64_OPND_DTR_R3
:
5148 case IA64_OPND_ITR_R3
:
5149 case IA64_OPND_IBR_R3
:
5150 case IA64_OPND_MSR_R3
:
5151 case IA64_OPND_PKR_R3
:
5152 case IA64_OPND_PMC_R3
:
5153 case IA64_OPND_PMD_R3
:
5154 case IA64_OPND_RR_R3
:
5155 if (e
->X_op
== O_index
&& e
->X_op_symbol
5156 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
5157 == opnd
- IA64_OPND_CPUID_R3
))
5158 return OPERAND_MATCH
;
5162 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
5163 return OPERAND_MATCH
;
5166 /* immediate operands: */
5167 case IA64_OPND_CNT2a
:
5168 case IA64_OPND_LEN4
:
5169 case IA64_OPND_LEN6
:
5170 bits
= operand_width (idesc
->operands
[index
]);
5171 if (e
->X_op
== O_constant
)
5173 if ((bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
5174 return OPERAND_MATCH
;
5176 return OPERAND_OUT_OF_RANGE
;
5180 case IA64_OPND_CNT2b
:
5181 if (e
->X_op
== O_constant
)
5183 if ((bfd_vma
) (e
->X_add_number
- 1) < 3)
5184 return OPERAND_MATCH
;
5186 return OPERAND_OUT_OF_RANGE
;
5190 case IA64_OPND_CNT2c
:
5191 val
= e
->X_add_number
;
5192 if (e
->X_op
== O_constant
)
5194 if ((val
== 0 || val
== 7 || val
== 15 || val
== 16))
5195 return OPERAND_MATCH
;
5197 return OPERAND_OUT_OF_RANGE
;
5202 /* SOR must be an integer multiple of 8 */
5203 if (e
->X_op
== O_constant
&& e
->X_add_number
& 0x7)
5204 return OPERAND_OUT_OF_RANGE
;
5207 if (e
->X_op
== O_constant
)
5209 if ((bfd_vma
) e
->X_add_number
<= 96)
5210 return OPERAND_MATCH
;
5212 return OPERAND_OUT_OF_RANGE
;
5216 case IA64_OPND_IMMU62
:
5217 if (e
->X_op
== O_constant
)
5219 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
5220 return OPERAND_MATCH
;
5222 return OPERAND_OUT_OF_RANGE
;
5226 /* FIXME -- need 62-bit relocation type */
5227 as_bad (_("62-bit relocation not yet implemented"));
5231 case IA64_OPND_IMMU64
:
5232 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
5233 || e
->X_op
== O_subtract
)
5235 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5236 fix
->code
= BFD_RELOC_IA64_IMM64
;
5237 if (e
->X_op
!= O_subtract
)
5239 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5240 if (e
->X_op
== O_pseudo_fixup
)
5244 fix
->opnd
= idesc
->operands
[index
];
5247 ++CURR_SLOT
.num_fixups
;
5248 return OPERAND_MATCH
;
5250 else if (e
->X_op
== O_constant
)
5251 return OPERAND_MATCH
;
5254 case IA64_OPND_CCNT5
:
5255 case IA64_OPND_CNT5
:
5256 case IA64_OPND_CNT6
:
5257 case IA64_OPND_CPOS6a
:
5258 case IA64_OPND_CPOS6b
:
5259 case IA64_OPND_CPOS6c
:
5260 case IA64_OPND_IMMU2
:
5261 case IA64_OPND_IMMU7a
:
5262 case IA64_OPND_IMMU7b
:
5263 case IA64_OPND_IMMU21
:
5264 case IA64_OPND_IMMU24
:
5265 case IA64_OPND_MBTYPE4
:
5266 case IA64_OPND_MHTYPE8
:
5267 case IA64_OPND_POS6
:
5268 bits
= operand_width (idesc
->operands
[index
]);
5269 if (e
->X_op
== O_constant
)
5271 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5272 return OPERAND_MATCH
;
5274 return OPERAND_OUT_OF_RANGE
;
5278 case IA64_OPND_IMMU9
:
5279 bits
= operand_width (idesc
->operands
[index
]);
5280 if (e
->X_op
== O_constant
)
5282 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5284 int lobits
= e
->X_add_number
& 0x3;
5285 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
5286 e
->X_add_number
|= (bfd_vma
) 0x3;
5287 return OPERAND_MATCH
;
5290 return OPERAND_OUT_OF_RANGE
;
5294 case IA64_OPND_IMM44
:
5295 /* least 16 bits must be zero */
5296 if ((e
->X_add_number
& 0xffff) != 0)
5297 /* XXX technically, this is wrong: we should not be issuing warning
5298 messages until we're sure this instruction pattern is going to
5300 as_warn (_("lower 16 bits of mask ignored"));
5302 if (e
->X_op
== O_constant
)
5304 if (((e
->X_add_number
>= 0
5305 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5306 || (e
->X_add_number
< 0
5307 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5310 if (e
->X_add_number
>= 0
5311 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5313 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5315 return OPERAND_MATCH
;
5318 return OPERAND_OUT_OF_RANGE
;
5322 case IA64_OPND_IMM17
:
5323 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5324 if (e
->X_op
== O_constant
)
5326 if (((e
->X_add_number
>= 0
5327 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5328 || (e
->X_add_number
< 0
5329 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5332 if (e
->X_add_number
>= 0
5333 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5335 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5337 return OPERAND_MATCH
;
5340 return OPERAND_OUT_OF_RANGE
;
5344 case IA64_OPND_IMM14
:
5345 case IA64_OPND_IMM22
:
5347 case IA64_OPND_IMM1
:
5348 case IA64_OPND_IMM8
:
5349 case IA64_OPND_IMM8U4
:
5350 case IA64_OPND_IMM8M1
:
5351 case IA64_OPND_IMM8M1U4
:
5352 case IA64_OPND_IMM8M1U8
:
5353 case IA64_OPND_IMM9a
:
5354 case IA64_OPND_IMM9b
:
5355 bits
= operand_width (idesc
->operands
[index
]);
5356 if (relocatable
&& (e
->X_op
== O_symbol
5357 || e
->X_op
== O_subtract
5358 || e
->X_op
== O_pseudo_fixup
))
5360 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5362 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5363 fix
->code
= BFD_RELOC_IA64_IMM14
;
5365 fix
->code
= BFD_RELOC_IA64_IMM22
;
5367 if (e
->X_op
!= O_subtract
)
5369 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5370 if (e
->X_op
== O_pseudo_fixup
)
5374 fix
->opnd
= idesc
->operands
[index
];
5377 ++CURR_SLOT
.num_fixups
;
5378 return OPERAND_MATCH
;
5380 else if (e
->X_op
!= O_constant
5381 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5382 return OPERAND_MISMATCH
;
5384 if (opnd
== IA64_OPND_IMM8M1U4
)
5386 /* Zero is not valid for unsigned compares that take an adjusted
5387 constant immediate range. */
5388 if (e
->X_add_number
== 0)
5389 return OPERAND_OUT_OF_RANGE
;
5391 /* Sign-extend 32-bit unsigned numbers, so that the following range
5392 checks will work. */
5393 val
= e
->X_add_number
;
5394 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5395 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5396 val
= ((val
<< 32) >> 32);
5398 /* Check for 0x100000000. This is valid because
5399 0x100000000-1 is the same as ((uint32_t) -1). */
5400 if (val
== ((bfd_signed_vma
) 1 << 32))
5401 return OPERAND_MATCH
;
5405 else if (opnd
== IA64_OPND_IMM8M1U8
)
5407 /* Zero is not valid for unsigned compares that take an adjusted
5408 constant immediate range. */
5409 if (e
->X_add_number
== 0)
5410 return OPERAND_OUT_OF_RANGE
;
5412 /* Check for 0x10000000000000000. */
5413 if (e
->X_op
== O_big
)
5415 if (generic_bignum
[0] == 0
5416 && generic_bignum
[1] == 0
5417 && generic_bignum
[2] == 0
5418 && generic_bignum
[3] == 0
5419 && generic_bignum
[4] == 1)
5420 return OPERAND_MATCH
;
5422 return OPERAND_OUT_OF_RANGE
;
5425 val
= e
->X_add_number
- 1;
5427 else if (opnd
== IA64_OPND_IMM8M1
)
5428 val
= e
->X_add_number
- 1;
5429 else if (opnd
== IA64_OPND_IMM8U4
)
5431 /* Sign-extend 32-bit unsigned numbers, so that the following range
5432 checks will work. */
5433 val
= e
->X_add_number
;
5434 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5435 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5436 val
= ((val
<< 32) >> 32);
5439 val
= e
->X_add_number
;
5441 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5442 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5443 return OPERAND_MATCH
;
5445 return OPERAND_OUT_OF_RANGE
;
5447 case IA64_OPND_INC3
:
5448 /* +/- 1, 4, 8, 16 */
5449 val
= e
->X_add_number
;
5452 if (e
->X_op
== O_constant
)
5454 if ((val
== 1 || val
== 4 || val
== 8 || val
== 16))
5455 return OPERAND_MATCH
;
5457 return OPERAND_OUT_OF_RANGE
;
5461 case IA64_OPND_TGT25
:
5462 case IA64_OPND_TGT25b
:
5463 case IA64_OPND_TGT25c
:
5464 case IA64_OPND_TGT64
:
5465 if (e
->X_op
== O_symbol
)
5467 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5468 if (opnd
== IA64_OPND_TGT25
)
5469 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5470 else if (opnd
== IA64_OPND_TGT25b
)
5471 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5472 else if (opnd
== IA64_OPND_TGT25c
)
5473 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5474 else if (opnd
== IA64_OPND_TGT64
)
5475 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5479 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5480 fix
->opnd
= idesc
->operands
[index
];
5483 ++CURR_SLOT
.num_fixups
;
5484 return OPERAND_MATCH
;
5486 case IA64_OPND_TAG13
:
5487 case IA64_OPND_TAG13b
:
5491 return OPERAND_MATCH
;
5494 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5495 /* There are no external relocs for TAG13/TAG13b fields, so we
5496 create a dummy reloc. This will not live past md_apply_fix3. */
5497 fix
->code
= BFD_RELOC_UNUSED
;
5498 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5499 fix
->opnd
= idesc
->operands
[index
];
5502 ++CURR_SLOT
.num_fixups
;
5503 return OPERAND_MATCH
;
5513 return OPERAND_MISMATCH
;
5522 memset (e
, 0, sizeof (*e
));
5525 if (*input_line_pointer
!= '}')
5527 sep
= *input_line_pointer
++;
5531 if (!md
.manual_bundling
)
5532 as_warn ("Found '}' when manual bundling is off");
5534 CURR_SLOT
.manual_bundling_off
= 1;
5535 md
.manual_bundling
= 0;
5541 /* Returns the next entry in the opcode table that matches the one in
5542 IDESC, and frees the entry in IDESC. If no matching entry is
5543 found, NULL is returned instead. */
5545 static struct ia64_opcode
*
5546 get_next_opcode (struct ia64_opcode
*idesc
)
5548 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5549 ia64_free_opcode (idesc
);
5553 /* Parse the operands for the opcode and find the opcode variant that
5554 matches the specified operands, or NULL if no match is possible. */
5556 static struct ia64_opcode
*
5557 parse_operands (idesc
)
5558 struct ia64_opcode
*idesc
;
5560 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5561 int error_pos
, out_of_range_pos
, curr_out_of_range_pos
, sep
= 0;
5562 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5563 enum operand_match_result result
;
5565 char *first_arg
= 0, *end
, *saved_input_pointer
;
5568 assert (strlen (idesc
->name
) <= 128);
5570 strcpy (mnemonic
, idesc
->name
);
5571 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5573 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5574 can't parse the first operand until we have parsed the
5575 remaining operands of the "alloc" instruction. */
5577 first_arg
= input_line_pointer
;
5578 end
= strchr (input_line_pointer
, '=');
5581 as_bad ("Expected separator `='");
5584 input_line_pointer
= end
+ 1;
5589 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5591 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5592 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5597 if (sep
!= '=' && sep
!= ',')
5602 if (num_outputs
> 0)
5603 as_bad ("Duplicate equal sign (=) in instruction");
5605 num_outputs
= i
+ 1;
5610 as_bad ("Illegal operand separator `%c'", sep
);
5614 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5616 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5617 know (strcmp (idesc
->name
, "alloc") == 0);
5618 if (num_operands
== 5 /* first_arg not included in this count! */
5619 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5620 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5621 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5622 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5624 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5625 CURR_SLOT
.opnd
[3].X_add_number
,
5626 CURR_SLOT
.opnd
[4].X_add_number
,
5627 CURR_SLOT
.opnd
[5].X_add_number
);
5629 /* now we can parse the first arg: */
5630 saved_input_pointer
= input_line_pointer
;
5631 input_line_pointer
= first_arg
;
5632 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5634 --num_outputs
; /* force error */
5635 input_line_pointer
= saved_input_pointer
;
5637 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5638 CURR_SLOT
.opnd
[3].X_add_number
5639 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5640 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5644 highest_unmatched_operand
= 0;
5645 curr_out_of_range_pos
= -1;
5647 expected_operand
= idesc
->operands
[0];
5648 for (; idesc
; idesc
= get_next_opcode (idesc
))
5650 if (num_outputs
!= idesc
->num_outputs
)
5651 continue; /* mismatch in # of outputs */
5653 CURR_SLOT
.num_fixups
= 0;
5655 /* Try to match all operands. If we see an out-of-range operand,
5656 then continue trying to match the rest of the operands, since if
5657 the rest match, then this idesc will give the best error message. */
5659 out_of_range_pos
= -1;
5660 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5662 result
= operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
);
5663 if (result
!= OPERAND_MATCH
)
5665 if (result
!= OPERAND_OUT_OF_RANGE
)
5667 if (out_of_range_pos
< 0)
5668 /* remember position of the first out-of-range operand: */
5669 out_of_range_pos
= i
;
5673 /* If we did not match all operands, or if at least one operand was
5674 out-of-range, then this idesc does not match. Keep track of which
5675 idesc matched the most operands before failing. If we have two
5676 idescs that failed at the same position, and one had an out-of-range
5677 operand, then prefer the out-of-range operand. Thus if we have
5678 "add r0=0x1000000,r1" we get an error saying the constant is out
5679 of range instead of an error saying that the constant should have been
5682 if (i
!= num_operands
|| out_of_range_pos
>= 0)
5684 if (i
> highest_unmatched_operand
5685 || (i
== highest_unmatched_operand
5686 && out_of_range_pos
> curr_out_of_range_pos
))
5688 highest_unmatched_operand
= i
;
5689 if (out_of_range_pos
>= 0)
5691 expected_operand
= idesc
->operands
[out_of_range_pos
];
5692 error_pos
= out_of_range_pos
;
5696 expected_operand
= idesc
->operands
[i
];
5699 curr_out_of_range_pos
= out_of_range_pos
;
5704 if (num_operands
< NELEMS (idesc
->operands
)
5705 && idesc
->operands
[num_operands
])
5706 continue; /* mismatch in number of arguments */
5712 if (expected_operand
)
5713 as_bad ("Operand %u of `%s' should be %s",
5714 error_pos
+ 1, mnemonic
,
5715 elf64_ia64_operands
[expected_operand
].desc
);
5717 as_bad ("Operand mismatch");
5723 /* Keep track of state necessary to determine whether a NOP is necessary
5724 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5725 detect a case where additional NOPs may be necessary. */
5727 errata_nop_necessary_p (slot
, insn_unit
)
5729 enum ia64_unit insn_unit
;
5732 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5733 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5734 struct ia64_opcode
*idesc
= slot
->idesc
;
5736 /* Test whether this could be the first insn in a problematic sequence. */
5737 if (insn_unit
== IA64_UNIT_F
)
5739 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5740 if (idesc
->operands
[i
] == IA64_OPND_P1
5741 || idesc
->operands
[i
] == IA64_OPND_P2
)
5743 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5744 /* Ignore invalid operands; they generate errors elsewhere. */
5747 this_group
->p_reg_set
[regno
] = 1;
5751 /* Test whether this could be the second insn in a problematic sequence. */
5752 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5753 && prev_group
->p_reg_set
[slot
->qp_regno
])
5755 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5756 if (idesc
->operands
[i
] == IA64_OPND_R1
5757 || idesc
->operands
[i
] == IA64_OPND_R2
5758 || idesc
->operands
[i
] == IA64_OPND_R3
)
5760 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5761 /* Ignore invalid operands; they generate errors elsewhere. */
5764 if (strncmp (idesc
->name
, "add", 3) != 0
5765 && strncmp (idesc
->name
, "sub", 3) != 0
5766 && strncmp (idesc
->name
, "shladd", 6) != 0
5767 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5768 this_group
->g_reg_set_conditionally
[regno
] = 1;
5772 /* Test whether this could be the third insn in a problematic sequence. */
5773 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5775 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5776 idesc
->operands
[i
] == IA64_OPND_R3
5777 /* For mov indirect. */
5778 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5779 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5780 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5781 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5782 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5783 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5784 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5785 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5787 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5788 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5789 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5790 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5792 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5793 /* Ignore invalid operands; they generate errors elsewhere. */
5796 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5798 if (strcmp (idesc
->name
, "fc") != 0
5799 && strcmp (idesc
->name
, "tak") != 0
5800 && strcmp (idesc
->name
, "thash") != 0
5801 && strcmp (idesc
->name
, "tpa") != 0
5802 && strcmp (idesc
->name
, "ttag") != 0
5803 && strncmp (idesc
->name
, "ptr", 3) != 0
5804 && strncmp (idesc
->name
, "ptc", 3) != 0
5805 && strncmp (idesc
->name
, "probe", 5) != 0)
5808 if (prev_group
->g_reg_set_conditionally
[regno
])
5816 build_insn (slot
, insnp
)
5820 const struct ia64_operand
*odesc
, *o2desc
;
5821 struct ia64_opcode
*idesc
= slot
->idesc
;
5822 bfd_signed_vma insn
, val
;
5826 insn
= idesc
->opcode
| slot
->qp_regno
;
5828 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5830 if (slot
->opnd
[i
].X_op
== O_register
5831 || slot
->opnd
[i
].X_op
== O_constant
5832 || slot
->opnd
[i
].X_op
== O_index
)
5833 val
= slot
->opnd
[i
].X_add_number
;
5834 else if (slot
->opnd
[i
].X_op
== O_big
)
5836 /* This must be the value 0x10000000000000000. */
5837 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5843 switch (idesc
->operands
[i
])
5845 case IA64_OPND_IMMU64
:
5846 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5847 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5848 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5849 | (((val
>> 63) & 0x1) << 36));
5852 case IA64_OPND_IMMU62
:
5853 val
&= 0x3fffffffffffffffULL
;
5854 if (val
!= slot
->opnd
[i
].X_add_number
)
5855 as_warn (_("Value truncated to 62 bits"));
5856 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5857 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5860 case IA64_OPND_TGT64
:
5862 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5863 insn
|= ((((val
>> 59) & 0x1) << 36)
5864 | (((val
>> 0) & 0xfffff) << 13));
5895 case IA64_OPND_R3_2
:
5896 case IA64_OPND_CPUID_R3
:
5897 case IA64_OPND_DBR_R3
:
5898 case IA64_OPND_DTR_R3
:
5899 case IA64_OPND_ITR_R3
:
5900 case IA64_OPND_IBR_R3
:
5902 case IA64_OPND_MSR_R3
:
5903 case IA64_OPND_PKR_R3
:
5904 case IA64_OPND_PMC_R3
:
5905 case IA64_OPND_PMD_R3
:
5906 case IA64_OPND_RR_R3
:
5914 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5915 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5917 as_bad_where (slot
->src_file
, slot
->src_line
,
5918 "Bad operand value: %s", err
);
5919 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5921 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5922 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5924 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5925 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5927 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5928 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5929 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5931 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5932 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5942 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5943 unsigned int manual_bundling
= 0;
5944 enum ia64_unit required_unit
, insn_unit
= 0;
5945 enum ia64_insn_type type
[3], insn_type
;
5946 unsigned int template, orig_template
;
5947 bfd_vma insn
[3] = { -1, -1, -1 };
5948 struct ia64_opcode
*idesc
;
5949 int end_of_insn_group
= 0, user_template
= -1;
5950 int n
, i
, j
, first
, curr
;
5952 bfd_vma t0
= 0, t1
= 0;
5953 struct label_fix
*lfix
;
5954 struct insn_fix
*ifix
;
5959 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5960 know (first
>= 0 & first
< NUM_SLOTS
);
5961 n
= MIN (3, md
.num_slots_in_use
);
5963 /* Determine template: user user_template if specified, best match
5966 if (md
.slot
[first
].user_template
>= 0)
5967 user_template
= template = md
.slot
[first
].user_template
;
5970 /* Auto select appropriate template. */
5971 memset (type
, 0, sizeof (type
));
5973 for (i
= 0; i
< n
; ++i
)
5975 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
5977 type
[i
] = md
.slot
[curr
].idesc
->type
;
5978 curr
= (curr
+ 1) % NUM_SLOTS
;
5980 template = best_template
[type
[0]][type
[1]][type
[2]];
5983 /* initialize instructions with appropriate nops: */
5984 for (i
= 0; i
< 3; ++i
)
5985 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
5989 /* now fill in slots with as many insns as possible: */
5991 idesc
= md
.slot
[curr
].idesc
;
5992 end_of_insn_group
= 0;
5993 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
5995 /* Set the slot number for prologue/body records now as those
5996 refer to the current point, not the point after the
5997 instruction has been issued: */
5998 /* Don't try to delete prologue/body records here, as that will cause
5999 them to also be deleted from the master list of unwind records. */
6000 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6001 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
6002 || ptr
->r
.type
== body
)
6004 ptr
->slot_number
= (unsigned long) f
+ i
;
6005 ptr
->slot_frag
= frag_now
;
6008 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
6010 if (manual_bundling
&& i
!= 2)
6011 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6012 "`%s' must be last in bundle", idesc
->name
);
6016 if (idesc
->flags
& IA64_OPCODE_LAST
)
6019 unsigned int required_template
;
6021 /* If we need a stop bit after an M slot, our only choice is
6022 template 5 (M;;MI). If we need a stop bit after a B
6023 slot, our only choice is to place it at the end of the
6024 bundle, because the only available templates are MIB,
6025 MBB, BBB, MMB, and MFB. We don't handle anything other
6026 than M and B slots because these are the only kind of
6027 instructions that can have the IA64_OPCODE_LAST bit set. */
6028 required_template
= template;
6029 switch (idesc
->type
)
6033 required_template
= 5;
6041 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6042 "Internal error: don't know how to force %s to end"
6043 "of instruction group", idesc
->name
);
6047 if (manual_bundling
&& i
!= required_slot
)
6048 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6049 "`%s' must be last in instruction group",
6051 if (required_slot
< i
)
6052 /* Can't fit this instruction. */
6056 if (required_template
!= template)
6058 /* If we switch the template, we need to reset the NOPs
6059 after slot i. The slot-types of the instructions ahead
6060 of i never change, so we don't need to worry about
6061 changing NOPs in front of this slot. */
6062 for (j
= i
; j
< 3; ++j
)
6063 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
6065 template = required_template
;
6067 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
6069 if (manual_bundling_on
)
6070 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6071 "Label must be first in a bundle");
6072 /* This insn must go into the first slot of a bundle. */
6076 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
6077 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
6079 if (manual_bundling_on
)
6082 manual_bundling
= 1;
6084 break; /* need to start a new bundle */
6087 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
6089 /* We need an instruction group boundary in the middle of a
6090 bundle. See if we can switch to an other template with
6091 an appropriate boundary. */
6093 orig_template
= template;
6094 if (i
== 1 && (user_template
== 4
6095 || (user_template
< 0
6096 && (ia64_templ_desc
[template].exec_unit
[0]
6100 end_of_insn_group
= 0;
6102 else if (i
== 2 && (user_template
== 0
6103 || (user_template
< 0
6104 && (ia64_templ_desc
[template].exec_unit
[1]
6106 /* This test makes sure we don't switch the template if
6107 the next instruction is one that needs to be first in
6108 an instruction group. Since all those instructions are
6109 in the M group, there is no way such an instruction can
6110 fit in this bundle even if we switch the template. The
6111 reason we have to check for this is that otherwise we
6112 may end up generating "MI;;I M.." which has the deadly
6113 effect that the second M instruction is no longer the
6114 first in the bundle! --davidm 99/12/16 */
6115 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
6118 end_of_insn_group
= 0;
6120 else if (curr
!= first
)
6121 /* can't fit this insn */
6124 if (template != orig_template
)
6125 /* if we switch the template, we need to reset the NOPs
6126 after slot i. The slot-types of the instructions ahead
6127 of i never change, so we don't need to worry about
6128 changing NOPs in front of this slot. */
6129 for (j
= i
; j
< 3; ++j
)
6130 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
6132 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
6134 /* resolve dynamic opcodes such as "break" and "nop": */
6135 if (idesc
->type
== IA64_TYPE_DYN
)
6137 if ((strcmp (idesc
->name
, "nop") == 0)
6138 || (strcmp (idesc
->name
, "break") == 0))
6139 insn_unit
= required_unit
;
6140 else if (strcmp (idesc
->name
, "chk.s") == 0)
6142 insn_unit
= IA64_UNIT_M
;
6143 if (required_unit
== IA64_UNIT_I
)
6144 insn_unit
= IA64_UNIT_I
;
6147 as_fatal ("emit_one_bundle: unexpected dynamic op");
6149 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
6150 ia64_free_opcode (idesc
);
6151 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
6153 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
6158 insn_type
= idesc
->type
;
6159 insn_unit
= IA64_UNIT_NIL
;
6163 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
6164 insn_unit
= required_unit
;
6166 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
6167 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
6168 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
6169 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
6170 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
6175 if (insn_unit
!= required_unit
)
6177 if (required_unit
== IA64_UNIT_L
6178 && insn_unit
== IA64_UNIT_I
6179 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
6181 /* we got ourselves an MLX template but the current
6182 instruction isn't an X-unit, or an I-unit instruction
6183 that can go into the X slot of an MLX template. Duh. */
6184 if (md
.num_slots_in_use
>= NUM_SLOTS
)
6186 as_bad_where (md
.slot
[curr
].src_file
,
6187 md
.slot
[curr
].src_line
,
6188 "`%s' can't go in X slot of "
6189 "MLX template", idesc
->name
);
6190 /* drop this insn so we don't livelock: */
6191 --md
.num_slots_in_use
;
6195 continue; /* try next slot */
6201 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
6202 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
6205 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
6206 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6208 build_insn (md
.slot
+ curr
, insn
+ i
);
6210 /* Set slot counts for non prologue/body unwind records. */
6211 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6212 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
6213 && ptr
->r
.type
!= body
)
6215 ptr
->slot_number
= (unsigned long) f
+ i
;
6216 ptr
->slot_frag
= frag_now
;
6218 md
.slot
[curr
].unwind_record
= NULL
;
6220 if (required_unit
== IA64_UNIT_L
)
6223 /* skip one slot for long/X-unit instructions */
6226 --md
.num_slots_in_use
;
6228 /* now is a good time to fix up the labels for this insn: */
6229 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
6231 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
6232 symbol_set_frag (lfix
->sym
, frag_now
);
6234 /* and fix up the tags also. */
6235 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
6237 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
6238 symbol_set_frag (lfix
->sym
, frag_now
);
6241 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
6243 ifix
= md
.slot
[curr
].fixup
+ j
;
6244 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
6245 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
6246 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
6247 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
6248 fix
->fx_file
= md
.slot
[curr
].src_file
;
6249 fix
->fx_line
= md
.slot
[curr
].src_line
;
6252 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
6254 if (end_of_insn_group
)
6256 md
.group_idx
= (md
.group_idx
+ 1) % 3;
6257 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
6261 ia64_free_opcode (md
.slot
[curr
].idesc
);
6262 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
6263 md
.slot
[curr
].user_template
= -1;
6265 if (manual_bundling_off
)
6267 manual_bundling
= 0;
6270 curr
= (curr
+ 1) % NUM_SLOTS
;
6271 idesc
= md
.slot
[curr
].idesc
;
6273 if (manual_bundling
)
6275 if (md
.num_slots_in_use
> 0)
6276 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6277 "`%s' does not fit into %s template",
6278 idesc
->name
, ia64_templ_desc
[template].name
);
6280 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6281 "Missing '}' at end of file");
6283 know (md
.num_slots_in_use
< NUM_SLOTS
);
6285 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
6286 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
6288 number_to_chars_littleendian (f
+ 0, t0
, 8);
6289 number_to_chars_littleendian (f
+ 8, t1
, 8);
6291 unwind
.next_slot_number
= (unsigned long) f
+ 16;
6292 unwind
.next_slot_frag
= frag_now
;
6296 md_parse_option (c
, arg
)
6303 /* Switches from the Intel assembler. */
6305 if (strcmp (arg
, "ilp64") == 0
6306 || strcmp (arg
, "lp64") == 0
6307 || strcmp (arg
, "p64") == 0)
6309 md
.flags
|= EF_IA_64_ABI64
;
6311 else if (strcmp (arg
, "ilp32") == 0)
6313 md
.flags
&= ~EF_IA_64_ABI64
;
6315 else if (strcmp (arg
, "le") == 0)
6317 md
.flags
&= ~EF_IA_64_BE
;
6319 else if (strcmp (arg
, "be") == 0)
6321 md
.flags
|= EF_IA_64_BE
;
6328 if (strcmp (arg
, "so") == 0)
6330 /* Suppress signon message. */
6332 else if (strcmp (arg
, "pi") == 0)
6334 /* Reject privileged instructions. FIXME */
6336 else if (strcmp (arg
, "us") == 0)
6338 /* Allow union of signed and unsigned range. FIXME */
6340 else if (strcmp (arg
, "close_fcalls") == 0)
6342 /* Do not resolve global function calls. */
6349 /* temp[="prefix"] Insert temporary labels into the object file
6350 symbol table prefixed by "prefix".
6351 Default prefix is ":temp:".
6356 /* indirect=<tgt> Assume unannotated indirect branches behavior
6357 according to <tgt> --
6358 exit: branch out from the current context (default)
6359 labels: all labels in context may be branch targets
6361 if (strncmp (arg
, "indirect=", 9) != 0)
6366 /* -X conflicts with an ignored option, use -x instead */
6368 if (!arg
|| strcmp (arg
, "explicit") == 0)
6370 /* set default mode to explicit */
6371 md
.default_explicit_mode
= 1;
6374 else if (strcmp (arg
, "auto") == 0)
6376 md
.default_explicit_mode
= 0;
6378 else if (strcmp (arg
, "debug") == 0)
6382 else if (strcmp (arg
, "debugx") == 0)
6384 md
.default_explicit_mode
= 1;
6389 as_bad (_("Unrecognized option '-x%s'"), arg
);
6394 /* nops Print nops statistics. */
6397 /* GNU specific switches for gcc. */
6398 case OPTION_MCONSTANT_GP
:
6399 md
.flags
|= EF_IA_64_CONS_GP
;
6402 case OPTION_MAUTO_PIC
:
6403 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6414 md_show_usage (stream
)
6419 --mconstant-gp mark output file as using the constant-GP model\n\
6420 (sets ELF header flag EF_IA_64_CONS_GP)\n\
6421 --mauto-pic mark output file as using the constant-GP model\n\
6422 without function descriptors (sets ELF header flag\n\
6423 EF_IA_64_NOFUNCDESC_CONS_GP)\n\
6424 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6425 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6426 -x | -xexplicit turn on dependency violation checking (default)\n\
6427 -xauto automagically remove dependency violations\n\
6428 -xdebug debug dependency violation checker\n"),
6433 ia64_after_parse_args ()
6435 if (debug_type
== DEBUG_STABS
)
6436 as_fatal (_("--gstabs is not supported for ia64"));
6439 /* Return true if TYPE fits in TEMPL at SLOT. */
6442 match (int templ
, int type
, int slot
)
6444 enum ia64_unit unit
;
6447 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6450 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6452 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6454 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6455 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6456 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6457 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6458 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6459 default: result
= 0; break;
6464 /* Add a bit of extra goodness if a nop of type F or B would fit
6465 in TEMPL at SLOT. */
6468 extra_goodness (int templ
, int slot
)
6470 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6472 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6477 /* This function is called once, at assembler startup time. It sets
6478 up all the tables, etc. that the MD part of the assembler will need
6479 that can be determined before arguments are parsed. */
6483 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6488 md
.explicit_mode
= md
.default_explicit_mode
;
6490 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6492 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6493 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6494 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6495 &zero_address_frag
);
6497 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6498 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6499 &zero_address_frag
);
6501 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6502 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6503 &zero_address_frag
);
6505 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6506 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6507 &zero_address_frag
);
6509 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6510 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6511 &zero_address_frag
);
6513 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6514 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6515 &zero_address_frag
);
6517 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6518 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6519 &zero_address_frag
);
6521 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6522 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6523 &zero_address_frag
);
6525 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6526 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6527 &zero_address_frag
);
6529 pseudo_func
[FUNC_IPLT_RELOC
].u
.sym
=
6530 symbol_new (".<iplt>", undefined_section
, FUNC_IPLT_RELOC
,
6531 &zero_address_frag
);
6533 /* Compute the table of best templates. We compute goodness as a
6534 base 4 value, in which each match counts for 3, each F counts
6535 for 2, each B counts for 1. This should maximize the number of
6536 F and B nops in the chosen bundles, which is good because these
6537 pipelines are least likely to be overcommitted. */
6538 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6539 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6540 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6543 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6546 if (match (t
, i
, 0))
6548 if (match (t
, j
, 1))
6550 if (match (t
, k
, 2))
6551 goodness
= 3 + 3 + 3;
6553 goodness
= 3 + 3 + extra_goodness (t
, 2);
6555 else if (match (t
, j
, 2))
6556 goodness
= 3 + 3 + extra_goodness (t
, 1);
6560 goodness
+= extra_goodness (t
, 1);
6561 goodness
+= extra_goodness (t
, 2);
6564 else if (match (t
, i
, 1))
6566 if (match (t
, j
, 2))
6569 goodness
= 3 + extra_goodness (t
, 2);
6571 else if (match (t
, i
, 2))
6572 goodness
= 3 + extra_goodness (t
, 1);
6574 if (goodness
> best
)
6577 best_template
[i
][j
][k
] = t
;
6582 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6583 md
.slot
[i
].user_template
= -1;
6585 md
.pseudo_hash
= hash_new ();
6586 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6588 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6589 (void *) (pseudo_opcode
+ i
));
6591 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6592 pseudo_opcode
[i
].name
, err
);
6595 md
.reg_hash
= hash_new ();
6596 md
.dynreg_hash
= hash_new ();
6597 md
.const_hash
= hash_new ();
6598 md
.entry_hash
= hash_new ();
6600 /* general registers: */
6603 for (i
= 0; i
< total
; ++i
)
6605 sprintf (name
, "r%d", i
- REG_GR
);
6606 md
.regsym
[i
] = declare_register (name
, i
);
6609 /* floating point registers: */
6611 for (; i
< total
; ++i
)
6613 sprintf (name
, "f%d", i
- REG_FR
);
6614 md
.regsym
[i
] = declare_register (name
, i
);
6617 /* application registers: */
6620 for (; i
< total
; ++i
)
6622 sprintf (name
, "ar%d", i
- REG_AR
);
6623 md
.regsym
[i
] = declare_register (name
, i
);
6626 /* control registers: */
6629 for (; i
< total
; ++i
)
6631 sprintf (name
, "cr%d", i
- REG_CR
);
6632 md
.regsym
[i
] = declare_register (name
, i
);
6635 /* predicate registers: */
6637 for (; i
< total
; ++i
)
6639 sprintf (name
, "p%d", i
- REG_P
);
6640 md
.regsym
[i
] = declare_register (name
, i
);
6643 /* branch registers: */
6645 for (; i
< total
; ++i
)
6647 sprintf (name
, "b%d", i
- REG_BR
);
6648 md
.regsym
[i
] = declare_register (name
, i
);
6651 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6652 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6653 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6654 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6655 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6656 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6657 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6659 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6661 regnum
= indirect_reg
[i
].regnum
;
6662 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6665 /* define synonyms for application registers: */
6666 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6667 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6668 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6670 /* define synonyms for control registers: */
6671 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6672 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6673 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6675 declare_register ("gp", REG_GR
+ 1);
6676 declare_register ("sp", REG_GR
+ 12);
6677 declare_register ("rp", REG_BR
+ 0);
6679 /* pseudo-registers used to specify unwind info: */
6680 declare_register ("psp", REG_PSP
);
6682 declare_register_set ("ret", 4, REG_GR
+ 8);
6683 declare_register_set ("farg", 8, REG_FR
+ 8);
6684 declare_register_set ("fret", 8, REG_FR
+ 8);
6686 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6688 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6689 (PTR
) (const_bits
+ i
));
6691 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6695 /* Set the architecture and machine depending on defaults and command line
6697 if (md
.flags
& EF_IA_64_ABI64
)
6698 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6700 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6703 as_warn (_("Could not set architecture and machine"));
6705 /* Set the pointer size and pointer shift size depending on md.flags */
6707 if (md
.flags
& EF_IA_64_ABI64
)
6709 md
.pointer_size
= 8; /* pointers are 8 bytes */
6710 md
.pointer_size_shift
= 3; /* alignment is 8 bytes = 2^2 */
6714 md
.pointer_size
= 4; /* pointers are 4 bytes */
6715 md
.pointer_size_shift
= 2; /* alignment is 4 bytes = 2^2 */
6718 md
.mem_offset
.hint
= 0;
6721 md
.entry_labels
= NULL
;
6724 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6725 because that is called after md_parse_option which is where we do the
6726 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6727 default endianness. */
6730 ia64_init (argc
, argv
)
6731 int argc ATTRIBUTE_UNUSED
;
6732 char **argv ATTRIBUTE_UNUSED
;
6734 md
.flags
= MD_FLAGS_DEFAULT
;
6737 /* Return a string for the target object file format. */
6740 ia64_target_format ()
6742 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6744 if (md
.flags
& EF_IA_64_BE
)
6746 if (md
.flags
& EF_IA_64_ABI64
)
6747 #if defined(TE_AIX50)
6748 return "elf64-ia64-aix-big";
6749 #elif defined(TE_HPUX)
6750 return "elf64-ia64-hpux-big";
6752 return "elf64-ia64-big";
6755 #if defined(TE_AIX50)
6756 return "elf32-ia64-aix-big";
6757 #elif defined(TE_HPUX)
6758 return "elf32-ia64-hpux-big";
6760 return "elf32-ia64-big";
6765 if (md
.flags
& EF_IA_64_ABI64
)
6767 return "elf64-ia64-aix-little";
6769 return "elf64-ia64-little";
6773 return "elf32-ia64-aix-little";
6775 return "elf32-ia64-little";
6780 return "unknown-format";
6784 ia64_end_of_source ()
6786 /* terminate insn group upon reaching end of file: */
6787 insn_group_break (1, 0, 0);
6789 /* emits slots we haven't written yet: */
6790 ia64_flush_insns ();
6792 bfd_set_private_flags (stdoutput
, md
.flags
);
6794 md
.mem_offset
.hint
= 0;
6800 if (md
.qp
.X_op
== O_register
)
6801 as_bad ("qualifying predicate not followed by instruction");
6802 md
.qp
.X_op
= O_absent
;
6804 if (ignore_input ())
6807 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6809 if (md
.detect_dv
&& !md
.explicit_mode
)
6810 as_warn (_("Explicit stops are ignored in auto mode"));
6812 insn_group_break (1, 0, 0);
6816 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6818 static int defining_tag
= 0;
6821 ia64_unrecognized_line (ch
)
6827 expression (&md
.qp
);
6828 if (*input_line_pointer
++ != ')')
6830 as_bad ("Expected ')'");
6833 if (md
.qp
.X_op
!= O_register
)
6835 as_bad ("Qualifying predicate expected");
6838 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6840 as_bad ("Predicate register expected");
6846 if (md
.manual_bundling
)
6847 as_warn ("Found '{' when manual bundling is already turned on");
6849 CURR_SLOT
.manual_bundling_on
= 1;
6850 md
.manual_bundling
= 1;
6852 /* Bundling is only acceptable in explicit mode
6853 or when in default automatic mode. */
6854 if (md
.detect_dv
&& !md
.explicit_mode
)
6856 if (!md
.mode_explicitly_set
6857 && !md
.default_explicit_mode
)
6860 as_warn (_("Found '{' after explicit switch to automatic mode"));
6865 if (!md
.manual_bundling
)
6866 as_warn ("Found '}' when manual bundling is off");
6868 PREV_SLOT
.manual_bundling_off
= 1;
6869 md
.manual_bundling
= 0;
6871 /* switch back to automatic mode, if applicable */
6874 && !md
.mode_explicitly_set
6875 && !md
.default_explicit_mode
)
6878 /* Allow '{' to follow on the same line. We also allow ";;", but that
6879 happens automatically because ';' is an end of line marker. */
6881 if (input_line_pointer
[0] == '{')
6883 input_line_pointer
++;
6884 return ia64_unrecognized_line ('{');
6887 demand_empty_rest_of_line ();
6897 if (md
.qp
.X_op
== O_register
)
6899 as_bad ("Tag must come before qualifying predicate.");
6903 /* This implements just enough of read_a_source_file in read.c to
6904 recognize labels. */
6905 if (is_name_beginner (*input_line_pointer
))
6907 s
= input_line_pointer
;
6908 c
= get_symbol_end ();
6910 else if (LOCAL_LABELS_FB
6911 && ISDIGIT (*input_line_pointer
))
6914 while (ISDIGIT (*input_line_pointer
))
6915 temp
= (temp
* 10) + *input_line_pointer
++ - '0';
6916 fb_label_instance_inc (temp
);
6917 s
= fb_label_name (temp
, 0);
6918 c
= *input_line_pointer
;
6927 /* Put ':' back for error messages' sake. */
6928 *input_line_pointer
++ = ':';
6929 as_bad ("Expected ':'");
6936 /* Put ':' back for error messages' sake. */
6937 *input_line_pointer
++ = ':';
6938 if (*input_line_pointer
++ != ']')
6940 as_bad ("Expected ']'");
6945 as_bad ("Tag name expected");
6955 /* Not a valid line. */
6960 ia64_frob_label (sym
)
6963 struct label_fix
*fix
;
6965 /* Tags need special handling since they are not bundle breaks like
6969 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6971 fix
->next
= CURR_SLOT
.tag_fixups
;
6972 CURR_SLOT
.tag_fixups
= fix
;
6977 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
6979 md
.last_text_seg
= now_seg
;
6980 fix
= obstack_alloc (¬es
, sizeof (*fix
));
6982 fix
->next
= CURR_SLOT
.label_fixups
;
6983 CURR_SLOT
.label_fixups
= fix
;
6985 /* Keep track of how many code entry points we've seen. */
6986 if (md
.path
== md
.maxpaths
)
6989 md
.entry_labels
= (const char **)
6990 xrealloc ((void *) md
.entry_labels
,
6991 md
.maxpaths
* sizeof (char *));
6993 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
6998 ia64_flush_pending_output ()
7000 if (!md
.keep_pending_output
7001 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
7003 /* ??? This causes many unnecessary stop bits to be emitted.
7004 Unfortunately, it isn't clear if it is safe to remove this. */
7005 insn_group_break (1, 0, 0);
7006 ia64_flush_insns ();
7010 /* Do ia64-specific expression optimization. All that's done here is
7011 to transform index expressions that are either due to the indexing
7012 of rotating registers or due to the indexing of indirect register
7015 ia64_optimize_expr (l
, op
, r
)
7024 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
7026 num_regs
= (l
->X_add_number
>> 16);
7027 if ((unsigned) r
->X_add_number
>= num_regs
)
7030 as_bad ("No current frame");
7032 as_bad ("Index out of range 0..%u", num_regs
- 1);
7033 r
->X_add_number
= 0;
7035 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
7038 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
7040 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
7041 || l
->X_add_number
== IND_MEM
)
7043 as_bad ("Indirect register set name expected");
7044 l
->X_add_number
= IND_CPUID
;
7047 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
7048 l
->X_add_number
= r
->X_add_number
;
7056 ia64_parse_name (name
, e
)
7060 struct const_desc
*cdesc
;
7061 struct dynreg
*dr
= 0;
7062 unsigned int regnum
;
7066 /* first see if NAME is a known register name: */
7067 sym
= hash_find (md
.reg_hash
, name
);
7070 e
->X_op
= O_register
;
7071 e
->X_add_number
= S_GET_VALUE (sym
);
7075 cdesc
= hash_find (md
.const_hash
, name
);
7078 e
->X_op
= O_constant
;
7079 e
->X_add_number
= cdesc
->value
;
7083 /* check for inN, locN, or outN: */
7087 if (name
[1] == 'n' && ISDIGIT (name
[2]))
7095 if (name
[1] == 'o' && name
[2] == 'c' && ISDIGIT (name
[3]))
7103 if (name
[1] == 'u' && name
[2] == 't' && ISDIGIT (name
[3]))
7116 /* The name is inN, locN, or outN; parse the register number. */
7117 regnum
= strtoul (name
, &end
, 10);
7118 if (end
> name
&& *end
== '\0')
7120 if ((unsigned) regnum
>= dr
->num_regs
)
7123 as_bad ("No current frame");
7125 as_bad ("Register number out of range 0..%u",
7129 e
->X_op
= O_register
;
7130 e
->X_add_number
= dr
->base
+ regnum
;
7135 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
7137 /* We've got ourselves the name of a rotating register set.
7138 Store the base register number in the low 16 bits of
7139 X_add_number and the size of the register set in the top 16
7141 e
->X_op
= O_register
;
7142 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
7148 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7151 ia64_canonicalize_symbol_name (name
)
7154 size_t len
= strlen (name
);
7155 if (len
> 1 && name
[len
- 1] == '#')
7156 name
[len
- 1] = '\0';
7160 /* Return true if idesc is a conditional branch instruction. This excludes
7161 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7162 because they always read/write resources regardless of the value of the
7163 qualifying predicate. br.ia must always use p0, and hence is always
7164 taken. Thus this function returns true for branches which can fall
7165 through, and which use no resources if they do fall through. */
7168 is_conditional_branch (idesc
)
7169 struct ia64_opcode
*idesc
;
7171 /* br is a conditional branch. Everything that starts with br. except
7172 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7173 Everything that starts with brl is a conditional branch. */
7174 return (idesc
->name
[0] == 'b' && idesc
->name
[1] == 'r'
7175 && (idesc
->name
[2] == '\0'
7176 || (idesc
->name
[2] == '.' && idesc
->name
[3] != 'i'
7177 && idesc
->name
[3] != 'c' && idesc
->name
[3] != 'w')
7178 || idesc
->name
[2] == 'l'
7179 /* br.cond, br.call, br.clr */
7180 || (idesc
->name
[2] == '.' && idesc
->name
[3] == 'c'
7181 && (idesc
->name
[4] == 'a' || idesc
->name
[4] == 'o'
7182 || (idesc
->name
[4] == 'l' && idesc
->name
[5] == 'r')))));
7185 /* Return whether the given opcode is a taken branch. If there's any doubt,
7189 is_taken_branch (idesc
)
7190 struct ia64_opcode
*idesc
;
7192 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
7193 || strncmp (idesc
->name
, "br.ia", 5) == 0);
7196 /* Return whether the given opcode is an interruption or rfi. If there's any
7197 doubt, returns zero. */
7200 is_interruption_or_rfi (idesc
)
7201 struct ia64_opcode
*idesc
;
7203 if (strcmp (idesc
->name
, "rfi") == 0)
7208 /* Returns the index of the given dependency in the opcode's list of chks, or
7209 -1 if there is no dependency. */
7212 depends_on (depind
, idesc
)
7214 struct ia64_opcode
*idesc
;
7217 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
7218 for (i
= 0; i
< dep
->nchks
; i
++)
7220 if (depind
== DEP (dep
->chks
[i
]))
7226 /* Determine a set of specific resources used for a particular resource
7227 class. Returns the number of specific resources identified For those
7228 cases which are not determinable statically, the resource returned is
7231 Meanings of value in 'NOTE':
7232 1) only read/write when the register number is explicitly encoded in the
7234 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
7235 accesses CFM when qualifying predicate is in the rotating region.
7236 3) general register value is used to specify an indirect register; not
7237 determinable statically.
7238 4) only read the given resource when bits 7:0 of the indirect index
7239 register value does not match the register number of the resource; not
7240 determinable statically.
7241 5) all rules are implementation specific.
7242 6) only when both the index specified by the reader and the index specified
7243 by the writer have the same value in bits 63:61; not determinable
7245 7) only access the specified resource when the corresponding mask bit is
7247 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7248 only read when these insns reference FR2-31
7249 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7250 written when these insns write FR32-127
7251 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7253 11) The target predicates are written independently of PR[qp], but source
7254 registers are only read if PR[qp] is true. Since the state of PR[qp]
7255 cannot statically be determined, all source registers are marked used.
7256 12) This insn only reads the specified predicate register when that
7257 register is the PR[qp].
7258 13) This reference to ld-c only applies to teh GR whose value is loaded
7259 with data returned from memory, not the post-incremented address register.
7260 14) The RSE resource includes the implementation-specific RSE internal
7261 state resources. At least one (and possibly more) of these resources are
7262 read by each instruction listed in IC:rse-readers. At least one (and
7263 possibly more) of these resources are written by each insn listed in
7265 15+16) Represents reserved instructions, which the assembler does not
7268 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7269 this code; there are no dependency violations based on memory access.
7272 #define MAX_SPECS 256
7277 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
7278 const struct ia64_dependency
*dep
;
7279 struct ia64_opcode
*idesc
;
7280 int type
; /* is this a DV chk or a DV reg? */
7281 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
7282 int note
; /* resource note for this insn's usage */
7283 int path
; /* which execution path to examine */
7290 if (dep
->mode
== IA64_DV_WAW
7291 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
7292 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
7295 /* template for any resources we identify */
7296 tmpl
.dependency
= dep
;
7298 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
7299 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
7300 tmpl
.link_to_qp_branch
= 1;
7301 tmpl
.mem_offset
.hint
= 0;
7304 tmpl
.cmp_type
= CMP_NONE
;
7307 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7308 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7309 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7311 /* we don't need to track these */
7312 if (dep
->semantics
== IA64_DVS_NONE
)
7315 switch (dep
->specifier
)
7320 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7322 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7323 if (regno
>= 0 && regno
<= 7)
7325 specs
[count
] = tmpl
;
7326 specs
[count
++].index
= regno
;
7332 for (i
= 0; i
< 8; i
++)
7334 specs
[count
] = tmpl
;
7335 specs
[count
++].index
= i
;
7344 case IA64_RS_AR_UNAT
:
7345 /* This is a mov =AR or mov AR= instruction. */
7346 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7348 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7349 if (regno
== AR_UNAT
)
7351 specs
[count
++] = tmpl
;
7356 /* This is a spill/fill, or other instruction that modifies the
7359 /* Unless we can determine the specific bits used, mark the whole
7360 thing; bits 8:3 of the memory address indicate the bit used in
7361 UNAT. The .mem.offset hint may be used to eliminate a small
7362 subset of conflicts. */
7363 specs
[count
] = tmpl
;
7364 if (md
.mem_offset
.hint
)
7367 fprintf (stderr
, " Using hint for spill/fill\n");
7368 /* The index isn't actually used, just set it to something
7369 approximating the bit index. */
7370 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
7371 specs
[count
].mem_offset
.hint
= 1;
7372 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
7373 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
7377 specs
[count
++].specific
= 0;
7385 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7387 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7388 if ((regno
>= 8 && regno
<= 15)
7389 || (regno
>= 20 && regno
<= 23)
7390 || (regno
>= 31 && regno
<= 39)
7391 || (regno
>= 41 && regno
<= 47)
7392 || (regno
>= 67 && regno
<= 111))
7394 specs
[count
] = tmpl
;
7395 specs
[count
++].index
= regno
;
7408 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7410 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7411 if ((regno
>= 48 && regno
<= 63)
7412 || (regno
>= 112 && regno
<= 127))
7414 specs
[count
] = tmpl
;
7415 specs
[count
++].index
= regno
;
7421 for (i
= 48; i
< 64; i
++)
7423 specs
[count
] = tmpl
;
7424 specs
[count
++].index
= i
;
7426 for (i
= 112; i
< 128; i
++)
7428 specs
[count
] = tmpl
;
7429 specs
[count
++].index
= i
;
7447 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7448 if (idesc
->operands
[i
] == IA64_OPND_B1
7449 || idesc
->operands
[i
] == IA64_OPND_B2
)
7451 specs
[count
] = tmpl
;
7452 specs
[count
++].index
=
7453 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7458 for (i
= idesc
->num_outputs
;i
< NELEMS (idesc
->operands
); i
++)
7459 if (idesc
->operands
[i
] == IA64_OPND_B1
7460 || idesc
->operands
[i
] == IA64_OPND_B2
)
7462 specs
[count
] = tmpl
;
7463 specs
[count
++].index
=
7464 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7470 case IA64_RS_CPUID
: /* four or more registers */
7473 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7475 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7476 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7479 specs
[count
] = tmpl
;
7480 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7484 specs
[count
] = tmpl
;
7485 specs
[count
++].specific
= 0;
7495 case IA64_RS_DBR
: /* four or more registers */
7498 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7500 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7501 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7504 specs
[count
] = tmpl
;
7505 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7509 specs
[count
] = tmpl
;
7510 specs
[count
++].specific
= 0;
7514 else if (note
== 0 && !rsrc_write
)
7516 specs
[count
] = tmpl
;
7517 specs
[count
++].specific
= 0;
7525 case IA64_RS_IBR
: /* four or more registers */
7528 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7530 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7531 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7534 specs
[count
] = tmpl
;
7535 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7539 specs
[count
] = tmpl
;
7540 specs
[count
++].specific
= 0;
7553 /* These are implementation specific. Force all references to
7554 conflict with all other references. */
7555 specs
[count
] = tmpl
;
7556 specs
[count
++].specific
= 0;
7564 case IA64_RS_PKR
: /* 16 or more registers */
7565 if (note
== 3 || note
== 4)
7567 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7569 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7570 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7575 specs
[count
] = tmpl
;
7576 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7579 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7581 /* Uses all registers *except* the one in R3. */
7582 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7584 specs
[count
] = tmpl
;
7585 specs
[count
++].index
= i
;
7591 specs
[count
] = tmpl
;
7592 specs
[count
++].specific
= 0;
7599 specs
[count
] = tmpl
;
7600 specs
[count
++].specific
= 0;
7604 case IA64_RS_PMC
: /* four or more registers */
7607 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7608 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7611 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7613 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7614 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7617 specs
[count
] = tmpl
;
7618 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7622 specs
[count
] = tmpl
;
7623 specs
[count
++].specific
= 0;
7633 case IA64_RS_PMD
: /* four or more registers */
7636 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7638 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7639 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7642 specs
[count
] = tmpl
;
7643 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7647 specs
[count
] = tmpl
;
7648 specs
[count
++].specific
= 0;
7658 case IA64_RS_RR
: /* eight registers */
7661 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7663 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7664 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7667 specs
[count
] = tmpl
;
7668 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7672 specs
[count
] = tmpl
;
7673 specs
[count
++].specific
= 0;
7677 else if (note
== 0 && !rsrc_write
)
7679 specs
[count
] = tmpl
;
7680 specs
[count
++].specific
= 0;
7688 case IA64_RS_CR_IRR
:
7691 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7692 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7694 && idesc
->operands
[1] == IA64_OPND_CR3
7697 for (i
= 0; i
< 4; i
++)
7699 specs
[count
] = tmpl
;
7700 specs
[count
++].index
= CR_IRR0
+ i
;
7706 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7707 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7709 && regno
<= CR_IRR3
)
7711 specs
[count
] = tmpl
;
7712 specs
[count
++].index
= regno
;
7721 case IA64_RS_CR_LRR
:
7728 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7729 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7730 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7732 specs
[count
] = tmpl
;
7733 specs
[count
++].index
= regno
;
7741 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7743 specs
[count
] = tmpl
;
7744 specs
[count
++].index
=
7745 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7760 else if (rsrc_write
)
7762 if (dep
->specifier
== IA64_RS_FRb
7763 && idesc
->operands
[0] == IA64_OPND_F1
)
7765 specs
[count
] = tmpl
;
7766 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7771 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7773 if (idesc
->operands
[i
] == IA64_OPND_F2
7774 || idesc
->operands
[i
] == IA64_OPND_F3
7775 || idesc
->operands
[i
] == IA64_OPND_F4
)
7777 specs
[count
] = tmpl
;
7778 specs
[count
++].index
=
7779 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7788 /* This reference applies only to the GR whose value is loaded with
7789 data returned from memory. */
7790 specs
[count
] = tmpl
;
7791 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7797 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7798 if (idesc
->operands
[i
] == IA64_OPND_R1
7799 || idesc
->operands
[i
] == IA64_OPND_R2
7800 || idesc
->operands
[i
] == IA64_OPND_R3
)
7802 specs
[count
] = tmpl
;
7803 specs
[count
++].index
=
7804 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7806 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7807 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7808 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7810 specs
[count
] = tmpl
;
7811 specs
[count
++].index
=
7812 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7817 /* Look for anything that reads a GR. */
7818 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7820 if (idesc
->operands
[i
] == IA64_OPND_MR3
7821 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7822 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7823 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7824 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7825 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7826 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7827 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7828 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7829 || ((i
>= idesc
->num_outputs
)
7830 && (idesc
->operands
[i
] == IA64_OPND_R1
7831 || idesc
->operands
[i
] == IA64_OPND_R2
7832 || idesc
->operands
[i
] == IA64_OPND_R3
7833 /* addl source register. */
7834 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7836 specs
[count
] = tmpl
;
7837 specs
[count
++].index
=
7838 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7849 /* This is the same as IA64_RS_PRr, except that the register range is
7850 from 1 - 15, and there are no rotating register reads/writes here. */
7854 for (i
= 1; i
< 16; i
++)
7856 specs
[count
] = tmpl
;
7857 specs
[count
++].index
= i
;
7863 /* Mark only those registers indicated by the mask. */
7866 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7867 for (i
= 1; i
< 16; i
++)
7868 if (mask
& ((valueT
) 1 << i
))
7870 specs
[count
] = tmpl
;
7871 specs
[count
++].index
= i
;
7879 else if (note
== 11) /* note 11 implies note 1 as well */
7883 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7885 if (idesc
->operands
[i
] == IA64_OPND_P1
7886 || idesc
->operands
[i
] == IA64_OPND_P2
)
7888 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7889 if (regno
>= 1 && regno
< 16)
7891 specs
[count
] = tmpl
;
7892 specs
[count
++].index
= regno
;
7902 else if (note
== 12)
7904 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7906 specs
[count
] = tmpl
;
7907 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7914 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7915 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7916 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7917 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7919 if ((idesc
->operands
[0] == IA64_OPND_P1
7920 || idesc
->operands
[0] == IA64_OPND_P2
)
7921 && p1
>= 1 && p1
< 16)
7923 specs
[count
] = tmpl
;
7924 specs
[count
].cmp_type
=
7925 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7926 specs
[count
++].index
= p1
;
7928 if ((idesc
->operands
[1] == IA64_OPND_P1
7929 || idesc
->operands
[1] == IA64_OPND_P2
)
7930 && p2
>= 1 && p2
< 16)
7932 specs
[count
] = tmpl
;
7933 specs
[count
].cmp_type
=
7934 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7935 specs
[count
++].index
= p2
;
7940 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7942 specs
[count
] = tmpl
;
7943 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7945 if (idesc
->operands
[1] == IA64_OPND_PR
)
7947 for (i
= 1; i
< 16; i
++)
7949 specs
[count
] = tmpl
;
7950 specs
[count
++].index
= i
;
7961 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
7962 simplified cases of this. */
7966 for (i
= 16; i
< 63; i
++)
7968 specs
[count
] = tmpl
;
7969 specs
[count
++].index
= i
;
7975 /* Mark only those registers indicated by the mask. */
7977 && idesc
->operands
[0] == IA64_OPND_PR
)
7979 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7980 if (mask
& ((valueT
) 1<<16))
7981 for (i
= 16; i
< 63; i
++)
7983 specs
[count
] = tmpl
;
7984 specs
[count
++].index
= i
;
7988 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
7990 for (i
= 16; i
< 63; i
++)
7992 specs
[count
] = tmpl
;
7993 specs
[count
++].index
= i
;
8001 else if (note
== 11) /* note 11 implies note 1 as well */
8005 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8007 if (idesc
->operands
[i
] == IA64_OPND_P1
8008 || idesc
->operands
[i
] == IA64_OPND_P2
)
8010 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8011 if (regno
>= 16 && regno
< 63)
8013 specs
[count
] = tmpl
;
8014 specs
[count
++].index
= regno
;
8024 else if (note
== 12)
8026 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
8028 specs
[count
] = tmpl
;
8029 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8036 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8037 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8038 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8039 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8041 if ((idesc
->operands
[0] == IA64_OPND_P1
8042 || idesc
->operands
[0] == IA64_OPND_P2
)
8043 && p1
>= 16 && p1
< 63)
8045 specs
[count
] = tmpl
;
8046 specs
[count
].cmp_type
=
8047 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8048 specs
[count
++].index
= p1
;
8050 if ((idesc
->operands
[1] == IA64_OPND_P1
8051 || idesc
->operands
[1] == IA64_OPND_P2
)
8052 && p2
>= 16 && p2
< 63)
8054 specs
[count
] = tmpl
;
8055 specs
[count
].cmp_type
=
8056 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8057 specs
[count
++].index
= p2
;
8062 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
8064 specs
[count
] = tmpl
;
8065 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8067 if (idesc
->operands
[1] == IA64_OPND_PR
)
8069 for (i
= 16; i
< 63; i
++)
8071 specs
[count
] = tmpl
;
8072 specs
[count
++].index
= i
;
8084 /* Verify that the instruction is using the PSR bit indicated in
8088 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
8090 if (dep
->regindex
< 6)
8092 specs
[count
++] = tmpl
;
8095 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
8097 if (dep
->regindex
< 32
8098 || dep
->regindex
== 35
8099 || dep
->regindex
== 36
8100 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
8102 specs
[count
++] = tmpl
;
8105 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
8107 if (dep
->regindex
< 32
8108 || dep
->regindex
== 35
8109 || dep
->regindex
== 36
8110 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
8112 specs
[count
++] = tmpl
;
8117 /* Several PSR bits have very specific dependencies. */
8118 switch (dep
->regindex
)
8121 specs
[count
++] = tmpl
;
8126 specs
[count
++] = tmpl
;
8130 /* Only certain CR accesses use PSR.ic */
8131 if (idesc
->operands
[0] == IA64_OPND_CR3
8132 || idesc
->operands
[1] == IA64_OPND_CR3
)
8135 ((idesc
->operands
[0] == IA64_OPND_CR3
)
8138 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
8153 specs
[count
++] = tmpl
;
8162 specs
[count
++] = tmpl
;
8166 /* Only some AR accesses use cpl */
8167 if (idesc
->operands
[0] == IA64_OPND_AR3
8168 || idesc
->operands
[1] == IA64_OPND_AR3
)
8171 ((idesc
->operands
[0] == IA64_OPND_AR3
)
8174 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
8181 && regno
<= AR_K7
))))
8183 specs
[count
++] = tmpl
;
8188 specs
[count
++] = tmpl
;
8198 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
8200 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
8206 if (mask
& ((valueT
) 1 << dep
->regindex
))
8208 specs
[count
++] = tmpl
;
8213 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
8214 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
8215 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8216 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8218 if (idesc
->operands
[i
] == IA64_OPND_F1
8219 || idesc
->operands
[i
] == IA64_OPND_F2
8220 || idesc
->operands
[i
] == IA64_OPND_F3
8221 || idesc
->operands
[i
] == IA64_OPND_F4
)
8223 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8224 if (reg
>= min
&& reg
<= max
)
8226 specs
[count
++] = tmpl
;
8233 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
8234 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
8235 /* mfh is read on writes to FR32-127; mfl is read on writes to
8237 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8239 if (idesc
->operands
[i
] == IA64_OPND_F1
)
8241 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8242 if (reg
>= min
&& reg
<= max
)
8244 specs
[count
++] = tmpl
;
8249 else if (note
== 10)
8251 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8253 if (idesc
->operands
[i
] == IA64_OPND_R1
8254 || idesc
->operands
[i
] == IA64_OPND_R2
8255 || idesc
->operands
[i
] == IA64_OPND_R3
)
8257 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8258 if (regno
>= 16 && regno
<= 31)
8260 specs
[count
++] = tmpl
;
8271 case IA64_RS_AR_FPSR
:
8272 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
8274 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8275 if (regno
== AR_FPSR
)
8277 specs
[count
++] = tmpl
;
8282 specs
[count
++] = tmpl
;
8287 /* Handle all AR[REG] resources */
8288 if (note
== 0 || note
== 1)
8290 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8291 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
8292 && regno
== dep
->regindex
)
8294 specs
[count
++] = tmpl
;
8296 /* other AR[REG] resources may be affected by AR accesses */
8297 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
8300 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
8301 switch (dep
->regindex
)
8307 if (regno
== AR_BSPSTORE
)
8309 specs
[count
++] = tmpl
;
8313 (regno
== AR_BSPSTORE
8314 || regno
== AR_RNAT
))
8316 specs
[count
++] = tmpl
;
8321 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8324 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
8325 switch (dep
->regindex
)
8330 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
8332 specs
[count
++] = tmpl
;
8339 specs
[count
++] = tmpl
;
8349 /* Handle all CR[REG] resources */
8350 if (note
== 0 || note
== 1)
8352 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
8354 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
8355 if (regno
== dep
->regindex
)
8357 specs
[count
++] = tmpl
;
8359 else if (!rsrc_write
)
8361 /* Reads from CR[IVR] affect other resources. */
8362 if (regno
== CR_IVR
)
8364 if ((dep
->regindex
>= CR_IRR0
8365 && dep
->regindex
<= CR_IRR3
)
8366 || dep
->regindex
== CR_TPR
)
8368 specs
[count
++] = tmpl
;
8375 specs
[count
++] = tmpl
;
8384 case IA64_RS_INSERVICE
:
8385 /* look for write of EOI (67) or read of IVR (65) */
8386 if ((idesc
->operands
[0] == IA64_OPND_CR3
8387 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
8388 || (idesc
->operands
[1] == IA64_OPND_CR3
8389 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
8391 specs
[count
++] = tmpl
;
8398 specs
[count
++] = tmpl
;
8409 specs
[count
++] = tmpl
;
8413 /* Check if any of the registers accessed are in the rotating region.
8414 mov to/from pr accesses CFM only when qp_regno is in the rotating
8416 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8418 if (idesc
->operands
[i
] == IA64_OPND_R1
8419 || idesc
->operands
[i
] == IA64_OPND_R2
8420 || idesc
->operands
[i
] == IA64_OPND_R3
)
8422 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8423 /* Assumes that md.rot.num_regs is always valid */
8424 if (md
.rot
.num_regs
> 0
8426 && num
< 31 + md
.rot
.num_regs
)
8428 specs
[count
] = tmpl
;
8429 specs
[count
++].specific
= 0;
8432 else if (idesc
->operands
[i
] == IA64_OPND_F1
8433 || idesc
->operands
[i
] == IA64_OPND_F2
8434 || idesc
->operands
[i
] == IA64_OPND_F3
8435 || idesc
->operands
[i
] == IA64_OPND_F4
)
8437 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8440 specs
[count
] = tmpl
;
8441 specs
[count
++].specific
= 0;
8444 else if (idesc
->operands
[i
] == IA64_OPND_P1
8445 || idesc
->operands
[i
] == IA64_OPND_P2
)
8447 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8450 specs
[count
] = tmpl
;
8451 specs
[count
++].specific
= 0;
8455 if (CURR_SLOT
.qp_regno
> 15)
8457 specs
[count
] = tmpl
;
8458 specs
[count
++].specific
= 0;
8463 /* This is the same as IA64_RS_PRr, except simplified to account for
8464 the fact that there is only one register. */
8468 specs
[count
++] = tmpl
;
8473 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8474 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8475 if (mask
& ((valueT
) 1 << 63))
8476 specs
[count
++] = tmpl
;
8478 else if (note
== 11)
8480 if ((idesc
->operands
[0] == IA64_OPND_P1
8481 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8482 || (idesc
->operands
[1] == IA64_OPND_P2
8483 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8485 specs
[count
++] = tmpl
;
8488 else if (note
== 12)
8490 if (CURR_SLOT
.qp_regno
== 63)
8492 specs
[count
++] = tmpl
;
8499 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8500 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8501 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8502 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8505 && (idesc
->operands
[0] == IA64_OPND_P1
8506 || idesc
->operands
[0] == IA64_OPND_P2
))
8508 specs
[count
] = tmpl
;
8509 specs
[count
++].cmp_type
=
8510 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8513 && (idesc
->operands
[1] == IA64_OPND_P1
8514 || idesc
->operands
[1] == IA64_OPND_P2
))
8516 specs
[count
] = tmpl
;
8517 specs
[count
++].cmp_type
=
8518 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8523 if (CURR_SLOT
.qp_regno
== 63)
8525 specs
[count
++] = tmpl
;
8536 /* FIXME we can identify some individual RSE written resources, but RSE
8537 read resources have not yet been completely identified, so for now
8538 treat RSE as a single resource */
8539 if (strncmp (idesc
->name
, "mov", 3) == 0)
8543 if (idesc
->operands
[0] == IA64_OPND_AR3
8544 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8546 specs
[count
] = tmpl
;
8547 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8552 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8554 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8555 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8557 specs
[count
++] = tmpl
;
8560 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8562 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8563 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8564 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8566 specs
[count
++] = tmpl
;
8573 specs
[count
++] = tmpl
;
8578 /* FIXME -- do any of these need to be non-specific? */
8579 specs
[count
++] = tmpl
;
8583 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8590 /* Clear branch flags on marked resources. This breaks the link between the
8591 QP of the marking instruction and a subsequent branch on the same QP. */
8594 clear_qp_branch_flag (mask
)
8598 for (i
= 0; i
< regdepslen
; i
++)
8600 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8601 if ((bit
& mask
) != 0)
8603 regdeps
[i
].link_to_qp_branch
= 0;
8608 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8610 Any changes to a PR clears the mutex relations which include that PR. */
8613 clear_qp_mutex (mask
)
8619 while (i
< qp_mutexeslen
)
8621 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8625 fprintf (stderr
, " Clearing mutex relation");
8626 print_prmask (qp_mutexes
[i
].prmask
);
8627 fprintf (stderr
, "\n");
8629 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8636 /* Clear implies relations which contain PRs in the given masks.
8637 P1_MASK indicates the source of the implies relation, while P2_MASK
8638 indicates the implied PR. */
8641 clear_qp_implies (p1_mask
, p2_mask
)
8648 while (i
< qp_implieslen
)
8650 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8651 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8654 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8655 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8656 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8663 /* Add the PRs specified to the list of implied relations. */
8666 add_qp_imply (p1
, p2
)
8673 /* p0 is not meaningful here. */
8674 if (p1
== 0 || p2
== 0)
8680 /* If it exists already, ignore it. */
8681 for (i
= 0; i
< qp_implieslen
; i
++)
8683 if (qp_implies
[i
].p1
== p1
8684 && qp_implies
[i
].p2
== p2
8685 && qp_implies
[i
].path
== md
.path
8686 && !qp_implies
[i
].p2_branched
)
8690 if (qp_implieslen
== qp_impliestotlen
)
8692 qp_impliestotlen
+= 20;
8693 qp_implies
= (struct qp_imply
*)
8694 xrealloc ((void *) qp_implies
,
8695 qp_impliestotlen
* sizeof (struct qp_imply
));
8698 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8699 qp_implies
[qp_implieslen
].p1
= p1
;
8700 qp_implies
[qp_implieslen
].p2
= p2
;
8701 qp_implies
[qp_implieslen
].path
= md
.path
;
8702 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8704 /* Add in the implied transitive relations; for everything that p2 implies,
8705 make p1 imply that, too; for everything that implies p1, make it imply p2
8707 for (i
= 0; i
< qp_implieslen
; i
++)
8709 if (qp_implies
[i
].p1
== p2
)
8710 add_qp_imply (p1
, qp_implies
[i
].p2
);
8711 if (qp_implies
[i
].p2
== p1
)
8712 add_qp_imply (qp_implies
[i
].p1
, p2
);
8714 /* Add in mutex relations implied by this implies relation; for each mutex
8715 relation containing p2, duplicate it and replace p2 with p1. */
8716 bit
= (valueT
) 1 << p1
;
8717 mask
= (valueT
) 1 << p2
;
8718 for (i
= 0; i
< qp_mutexeslen
; i
++)
8720 if (qp_mutexes
[i
].prmask
& mask
)
8721 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8725 /* Add the PRs specified in the mask to the mutex list; this means that only
8726 one of the PRs can be true at any time. PR0 should never be included in
8736 if (qp_mutexeslen
== qp_mutexestotlen
)
8738 qp_mutexestotlen
+= 20;
8739 qp_mutexes
= (struct qpmutex
*)
8740 xrealloc ((void *) qp_mutexes
,
8741 qp_mutexestotlen
* sizeof (struct qpmutex
));
8745 fprintf (stderr
, " Registering mutex on");
8746 print_prmask (mask
);
8747 fprintf (stderr
, "\n");
8749 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8750 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8754 has_suffix_p (name
, suffix
)
8758 size_t namelen
= strlen (name
);
8759 size_t sufflen
= strlen (suffix
);
8761 if (namelen
<= sufflen
)
8763 return strcmp (name
+ namelen
- sufflen
, suffix
) == 0;
8767 clear_register_values ()
8771 fprintf (stderr
, " Clearing register values\n");
8772 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8773 gr_values
[i
].known
= 0;
8776 /* Keep track of register values/changes which affect DV tracking.
8778 optimization note: should add a flag to classes of insns where otherwise we
8779 have to examine a group of strings to identify them. */
8782 note_register_values (idesc
)
8783 struct ia64_opcode
*idesc
;
8785 valueT qp_changemask
= 0;
8788 /* Invalidate values for registers being written to. */
8789 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8791 if (idesc
->operands
[i
] == IA64_OPND_R1
8792 || idesc
->operands
[i
] == IA64_OPND_R2
8793 || idesc
->operands
[i
] == IA64_OPND_R3
)
8795 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8796 if (regno
> 0 && regno
< NELEMS (gr_values
))
8797 gr_values
[regno
].known
= 0;
8799 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8801 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8802 if (regno
> 0 && regno
< 4)
8803 gr_values
[regno
].known
= 0;
8805 else if (idesc
->operands
[i
] == IA64_OPND_P1
8806 || idesc
->operands
[i
] == IA64_OPND_P2
)
8808 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8809 qp_changemask
|= (valueT
) 1 << regno
;
8811 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8813 if (idesc
->operands
[2] & (valueT
) 0x10000)
8814 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8816 qp_changemask
= idesc
->operands
[2];
8819 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8821 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8822 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8824 qp_changemask
= idesc
->operands
[1];
8825 qp_changemask
&= ~(valueT
) 0xFFFF;
8830 /* Always clear qp branch flags on any PR change. */
8831 /* FIXME there may be exceptions for certain compares. */
8832 clear_qp_branch_flag (qp_changemask
);
8834 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8835 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8837 qp_changemask
|= ~(valueT
) 0xFFFF;
8838 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8840 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8841 gr_values
[i
].known
= 0;
8843 clear_qp_mutex (qp_changemask
);
8844 clear_qp_implies (qp_changemask
, qp_changemask
);
8846 /* After a call, all register values are undefined, except those marked
8848 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8849 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8851 /* FIXME keep GR values which are marked as "safe_across_calls" */
8852 clear_register_values ();
8853 clear_qp_mutex (~qp_safe_across_calls
);
8854 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8855 clear_qp_branch_flag (~qp_safe_across_calls
);
8857 else if (is_interruption_or_rfi (idesc
)
8858 || is_taken_branch (idesc
))
8860 clear_register_values ();
8861 clear_qp_mutex (~(valueT
) 0);
8862 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8864 /* Look for mutex and implies relations. */
8865 else if ((idesc
->operands
[0] == IA64_OPND_P1
8866 || idesc
->operands
[0] == IA64_OPND_P2
)
8867 && (idesc
->operands
[1] == IA64_OPND_P1
8868 || idesc
->operands
[1] == IA64_OPND_P2
))
8870 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8871 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8872 valueT p1mask
= (valueT
) 1 << p1
;
8873 valueT p2mask
= (valueT
) 1 << p2
;
8875 /* If one of the PRs is PR0, we can't really do anything. */
8876 if (p1
== 0 || p2
== 0)
8879 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8881 /* In general, clear mutexes and implies which include P1 or P2,
8882 with the following exceptions. */
8883 else if (has_suffix_p (idesc
->name
, ".or.andcm")
8884 || has_suffix_p (idesc
->name
, ".and.orcm"))
8886 add_qp_mutex (p1mask
| p2mask
);
8887 clear_qp_implies (p2mask
, p1mask
);
8889 else if (has_suffix_p (idesc
->name
, ".andcm")
8890 || has_suffix_p (idesc
->name
, ".and"))
8892 clear_qp_implies (0, p1mask
| p2mask
);
8894 else if (has_suffix_p (idesc
->name
, ".orcm")
8895 || has_suffix_p (idesc
->name
, ".or"))
8897 clear_qp_mutex (p1mask
| p2mask
);
8898 clear_qp_implies (p1mask
| p2mask
, 0);
8902 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8903 if (has_suffix_p (idesc
->name
, ".unc"))
8905 add_qp_mutex (p1mask
| p2mask
);
8906 if (CURR_SLOT
.qp_regno
!= 0)
8908 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8909 CURR_SLOT
.qp_regno
);
8910 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8911 CURR_SLOT
.qp_regno
);
8914 else if (CURR_SLOT
.qp_regno
== 0)
8916 add_qp_mutex (p1mask
| p2mask
);
8920 clear_qp_mutex (p1mask
| p2mask
);
8924 /* Look for mov imm insns into GRs. */
8925 else if (idesc
->operands
[0] == IA64_OPND_R1
8926 && (idesc
->operands
[1] == IA64_OPND_IMM22
8927 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8928 && (strcmp (idesc
->name
, "mov") == 0
8929 || strcmp (idesc
->name
, "movl") == 0))
8931 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8932 if (regno
> 0 && regno
< NELEMS (gr_values
))
8934 gr_values
[regno
].known
= 1;
8935 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8936 gr_values
[regno
].path
= md
.path
;
8939 fprintf (stderr
, " Know gr%d = ", regno
);
8940 fprintf_vma (stderr
, gr_values
[regno
].value
);
8941 fputs ("\n", stderr
);
8947 clear_qp_mutex (qp_changemask
);
8948 clear_qp_implies (qp_changemask
, qp_changemask
);
8952 /* Return whether the given predicate registers are currently mutex. */
8955 qp_mutex (p1
, p2
, path
)
8965 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
8966 for (i
= 0; i
< qp_mutexeslen
; i
++)
8968 if (qp_mutexes
[i
].path
>= path
8969 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
8976 /* Return whether the given resource is in the given insn's list of chks
8977 Return 1 if the conflict is absolutely determined, 2 if it's a potential
8981 resources_match (rs
, idesc
, note
, qp_regno
, path
)
8983 struct ia64_opcode
*idesc
;
8988 struct rsrc specs
[MAX_SPECS
];
8991 /* If the marked resource's qp_regno and the given qp_regno are mutex,
8992 we don't need to check. One exception is note 11, which indicates that
8993 target predicates are written regardless of PR[qp]. */
8994 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
8998 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
9001 /* UNAT checking is a bit more specific than other resources */
9002 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
9003 && specs
[count
].mem_offset
.hint
9004 && rs
->mem_offset
.hint
)
9006 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
9008 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
9009 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
9016 /* Skip apparent PR write conflicts where both writes are an AND or both
9017 writes are an OR. */
9018 if (rs
->dependency
->specifier
== IA64_RS_PR
9019 || rs
->dependency
->specifier
== IA64_RS_PRr
9020 || rs
->dependency
->specifier
== IA64_RS_PR63
)
9022 if (specs
[count
].cmp_type
!= CMP_NONE
9023 && specs
[count
].cmp_type
== rs
->cmp_type
)
9026 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
9027 dv_mode
[rs
->dependency
->mode
],
9028 rs
->dependency
->specifier
!= IA64_RS_PR63
?
9029 specs
[count
].index
: 63);
9034 " %s on parallel compare conflict %s vs %s on PR%d\n",
9035 dv_mode
[rs
->dependency
->mode
],
9036 dv_cmp_type
[rs
->cmp_type
],
9037 dv_cmp_type
[specs
[count
].cmp_type
],
9038 rs
->dependency
->specifier
!= IA64_RS_PR63
?
9039 specs
[count
].index
: 63);
9043 /* If either resource is not specific, conservatively assume a conflict
9045 if (!specs
[count
].specific
|| !rs
->specific
)
9047 else if (specs
[count
].index
== rs
->index
)
9052 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
9058 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
9059 insert a stop to create the break. Update all resource dependencies
9060 appropriately. If QP_REGNO is non-zero, only apply the break to resources
9061 which use the same QP_REGNO and have the link_to_qp_branch flag set.
9062 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
9066 insn_group_break (insert_stop
, qp_regno
, save_current
)
9073 if (insert_stop
&& md
.num_slots_in_use
> 0)
9074 PREV_SLOT
.end_of_insn_group
= 1;
9078 fprintf (stderr
, " Insn group break%s",
9079 (insert_stop
? " (w/stop)" : ""));
9081 fprintf (stderr
, " effective for QP=%d", qp_regno
);
9082 fprintf (stderr
, "\n");
9086 while (i
< regdepslen
)
9088 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
9091 && regdeps
[i
].qp_regno
!= qp_regno
)
9098 && CURR_SLOT
.src_file
== regdeps
[i
].file
9099 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
9105 /* clear dependencies which are automatically cleared by a stop, or
9106 those that have reached the appropriate state of insn serialization */
9107 if (dep
->semantics
== IA64_DVS_IMPLIED
9108 || dep
->semantics
== IA64_DVS_IMPLIEDF
9109 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
9111 print_dependency ("Removing", i
);
9112 regdeps
[i
] = regdeps
[--regdepslen
];
9116 if (dep
->semantics
== IA64_DVS_DATA
9117 || dep
->semantics
== IA64_DVS_INSTR
9118 || dep
->semantics
== IA64_DVS_SPECIFIC
)
9120 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
9121 regdeps
[i
].insn_srlz
= STATE_STOP
;
9122 if (regdeps
[i
].data_srlz
== STATE_NONE
)
9123 regdeps
[i
].data_srlz
= STATE_STOP
;
9130 /* Add the given resource usage spec to the list of active dependencies. */
9133 mark_resource (idesc
, dep
, spec
, depind
, path
)
9134 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
9135 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
9140 if (regdepslen
== regdepstotlen
)
9142 regdepstotlen
+= 20;
9143 regdeps
= (struct rsrc
*)
9144 xrealloc ((void *) regdeps
,
9145 regdepstotlen
* sizeof (struct rsrc
));
9148 regdeps
[regdepslen
] = *spec
;
9149 regdeps
[regdepslen
].depind
= depind
;
9150 regdeps
[regdepslen
].path
= path
;
9151 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
9152 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
9154 print_dependency ("Adding", regdepslen
);
9160 print_dependency (action
, depind
)
9166 fprintf (stderr
, " %s %s '%s'",
9167 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
9168 (regdeps
[depind
].dependency
)->name
);
9169 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
9170 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
9171 if (regdeps
[depind
].mem_offset
.hint
)
9173 fputs (" ", stderr
);
9174 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
9175 fputs ("+", stderr
);
9176 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
9178 fprintf (stderr
, "\n");
9183 instruction_serialization ()
9187 fprintf (stderr
, " Instruction serialization\n");
9188 for (i
= 0; i
< regdepslen
; i
++)
9189 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
9190 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
9194 data_serialization ()
9198 fprintf (stderr
, " Data serialization\n");
9199 while (i
< regdepslen
)
9201 if (regdeps
[i
].data_srlz
== STATE_STOP
9202 /* Note: as of 991210, all "other" dependencies are cleared by a
9203 data serialization. This might change with new tables */
9204 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
9206 print_dependency ("Removing", i
);
9207 regdeps
[i
] = regdeps
[--regdepslen
];
9214 /* Insert stops and serializations as needed to avoid DVs. */
9217 remove_marked_resource (rs
)
9220 switch (rs
->dependency
->semantics
)
9222 case IA64_DVS_SPECIFIC
:
9224 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
9225 /* ...fall through... */
9226 case IA64_DVS_INSTR
:
9228 fprintf (stderr
, "Inserting instr serialization\n");
9229 if (rs
->insn_srlz
< STATE_STOP
)
9230 insn_group_break (1, 0, 0);
9231 if (rs
->insn_srlz
< STATE_SRLZ
)
9233 int oldqp
= CURR_SLOT
.qp_regno
;
9234 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9235 /* Manually jam a srlz.i insn into the stream */
9236 CURR_SLOT
.qp_regno
= 0;
9237 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
9238 instruction_serialization ();
9239 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9240 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9242 CURR_SLOT
.qp_regno
= oldqp
;
9243 CURR_SLOT
.idesc
= oldidesc
;
9245 insn_group_break (1, 0, 0);
9247 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
9248 "other" types of DV are eliminated
9249 by a data serialization */
9252 fprintf (stderr
, "Inserting data serialization\n");
9253 if (rs
->data_srlz
< STATE_STOP
)
9254 insn_group_break (1, 0, 0);
9256 int oldqp
= CURR_SLOT
.qp_regno
;
9257 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9258 /* Manually jam a srlz.d insn into the stream */
9259 CURR_SLOT
.qp_regno
= 0;
9260 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
9261 data_serialization ();
9262 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9263 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9265 CURR_SLOT
.qp_regno
= oldqp
;
9266 CURR_SLOT
.idesc
= oldidesc
;
9269 case IA64_DVS_IMPLIED
:
9270 case IA64_DVS_IMPLIEDF
:
9272 fprintf (stderr
, "Inserting stop\n");
9273 insn_group_break (1, 0, 0);
9280 /* Check the resources used by the given opcode against the current dependency
9283 The check is run once for each execution path encountered. In this case,
9284 a unique execution path is the sequence of instructions following a code
9285 entry point, e.g. the following has three execution paths, one starting
9286 at L0, one at L1, and one at L2.
9295 check_dependencies (idesc
)
9296 struct ia64_opcode
*idesc
;
9298 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9302 /* Note that the number of marked resources may change within the
9303 loop if in auto mode. */
9305 while (i
< regdepslen
)
9307 struct rsrc
*rs
= ®deps
[i
];
9308 const struct ia64_dependency
*dep
= rs
->dependency
;
9313 if (dep
->semantics
== IA64_DVS_NONE
9314 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
9320 note
= NOTE (opdeps
->chks
[chkind
]);
9322 /* Check this resource against each execution path seen thus far. */
9323 for (path
= 0; path
<= md
.path
; path
++)
9327 /* If the dependency wasn't on the path being checked, ignore it. */
9328 if (rs
->path
< path
)
9331 /* If the QP for this insn implies a QP which has branched, don't
9332 bother checking. Ed. NOTE: I don't think this check is terribly
9333 useful; what's the point of generating code which will only be
9334 reached if its QP is zero?
9335 This code was specifically inserted to handle the following code,
9336 based on notes from Intel's DV checking code, where p1 implies p2.
9342 if (CURR_SLOT
.qp_regno
!= 0)
9346 for (implies
= 0; implies
< qp_implieslen
; implies
++)
9348 if (qp_implies
[implies
].path
>= path
9349 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
9350 && qp_implies
[implies
].p2_branched
)
9360 if ((matchtype
= resources_match (rs
, idesc
, note
,
9361 CURR_SLOT
.qp_regno
, path
)) != 0)
9364 char pathmsg
[256] = "";
9365 char indexmsg
[256] = "";
9366 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
9369 sprintf (pathmsg
, " when entry is at label '%s'",
9370 md
.entry_labels
[path
- 1]);
9371 if (rs
->specific
&& rs
->index
!= 0)
9372 sprintf (indexmsg
, ", specific resource number is %d",
9374 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9376 (certain
? "violates" : "may violate"),
9377 dv_mode
[dep
->mode
], dep
->name
,
9378 dv_sem
[dep
->semantics
],
9381 if (md
.explicit_mode
)
9383 as_warn ("%s", msg
);
9385 as_warn (_("Only the first path encountering the conflict "
9387 as_warn_where (rs
->file
, rs
->line
,
9388 _("This is the location of the "
9389 "conflicting usage"));
9390 /* Don't bother checking other paths, to avoid duplicating
9397 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
9399 remove_marked_resource (rs
);
9401 /* since the set of dependencies has changed, start over */
9402 /* FIXME -- since we're removing dvs as we go, we
9403 probably don't really need to start over... */
9416 /* Register new dependencies based on the given opcode. */
9419 mark_resources (idesc
)
9420 struct ia64_opcode
*idesc
;
9423 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9424 int add_only_qp_reads
= 0;
9426 /* A conditional branch only uses its resources if it is taken; if it is
9427 taken, we stop following that path. The other branch types effectively
9428 *always* write their resources. If it's not taken, register only QP
9430 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
9432 add_only_qp_reads
= 1;
9436 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
9438 for (i
= 0; i
< opdeps
->nregs
; i
++)
9440 const struct ia64_dependency
*dep
;
9441 struct rsrc specs
[MAX_SPECS
];
9446 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
9447 note
= NOTE (opdeps
->regs
[i
]);
9449 if (add_only_qp_reads
9450 && !(dep
->mode
== IA64_DV_WAR
9451 && (dep
->specifier
== IA64_RS_PR
9452 || dep
->specifier
== IA64_RS_PRr
9453 || dep
->specifier
== IA64_RS_PR63
)))
9456 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9459 if (md
.debug_dv
&& !count
)
9460 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9461 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9466 mark_resource (idesc
, dep
, &specs
[count
],
9467 DEP (opdeps
->regs
[i
]), md
.path
);
9470 /* The execution path may affect register values, which may in turn
9471 affect which indirect-access resources are accessed. */
9472 switch (dep
->specifier
)
9484 for (path
= 0; path
< md
.path
; path
++)
9486 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9488 mark_resource (idesc
, dep
, &specs
[count
],
9489 DEP (opdeps
->regs
[i
]), path
);
9496 /* Remove dependencies when they no longer apply. */
9499 update_dependencies (idesc
)
9500 struct ia64_opcode
*idesc
;
9504 if (strcmp (idesc
->name
, "srlz.i") == 0)
9506 instruction_serialization ();
9508 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9510 data_serialization ();
9512 else if (is_interruption_or_rfi (idesc
)
9513 || is_taken_branch (idesc
))
9515 /* Although technically the taken branch doesn't clear dependencies
9516 which require a srlz.[id], we don't follow the branch; the next
9517 instruction is assumed to start with a clean slate. */
9521 else if (is_conditional_branch (idesc
)
9522 && CURR_SLOT
.qp_regno
!= 0)
9524 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9526 for (i
= 0; i
< qp_implieslen
; i
++)
9528 /* If the conditional branch's predicate is implied by the predicate
9529 in an existing dependency, remove that dependency. */
9530 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9533 /* Note that this implied predicate takes a branch so that if
9534 a later insn generates a DV but its predicate implies this
9535 one, we can avoid the false DV warning. */
9536 qp_implies
[i
].p2_branched
= 1;
9537 while (depind
< regdepslen
)
9539 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9541 print_dependency ("Removing", depind
);
9542 regdeps
[depind
] = regdeps
[--regdepslen
];
9549 /* Any marked resources which have this same predicate should be
9550 cleared, provided that the QP hasn't been modified between the
9551 marking instruction and the branch. */
9554 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9559 while (i
< regdepslen
)
9561 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9562 && regdeps
[i
].link_to_qp_branch
9563 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9564 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9566 /* Treat like a taken branch */
9567 print_dependency ("Removing", i
);
9568 regdeps
[i
] = regdeps
[--regdepslen
];
9577 /* Examine the current instruction for dependency violations. */
9581 struct ia64_opcode
*idesc
;
9585 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9586 idesc
->name
, CURR_SLOT
.src_line
,
9587 idesc
->dependencies
->nchks
,
9588 idesc
->dependencies
->nregs
);
9591 /* Look through the list of currently marked resources; if the current
9592 instruction has the dependency in its chks list which uses that resource,
9593 check against the specific resources used. */
9594 check_dependencies (idesc
);
9596 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9597 then add them to the list of marked resources. */
9598 mark_resources (idesc
);
9600 /* There are several types of dependency semantics, and each has its own
9601 requirements for being cleared
9603 Instruction serialization (insns separated by interruption, rfi, or
9604 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9606 Data serialization (instruction serialization, or writer + srlz.d +
9607 reader, where writer and srlz.d are in separate groups) clears
9608 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9609 always be the case).
9611 Instruction group break (groups separated by stop, taken branch,
9612 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9614 update_dependencies (idesc
);
9616 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9617 warning. Keep track of as many as possible that are useful. */
9618 note_register_values (idesc
);
9620 /* We don't need or want this anymore. */
9621 md
.mem_offset
.hint
= 0;
9626 /* Translate one line of assembly. Pseudo ops and labels do not show
9632 char *saved_input_line_pointer
, *mnemonic
;
9633 const struct pseudo_opcode
*pdesc
;
9634 struct ia64_opcode
*idesc
;
9635 unsigned char qp_regno
;
9639 saved_input_line_pointer
= input_line_pointer
;
9640 input_line_pointer
= str
;
9642 /* extract the opcode (mnemonic): */
9644 mnemonic
= input_line_pointer
;
9645 ch
= get_symbol_end ();
9646 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9649 *input_line_pointer
= ch
;
9650 (*pdesc
->handler
) (pdesc
->arg
);
9654 /* Find the instruction descriptor matching the arguments. */
9656 idesc
= ia64_find_opcode (mnemonic
);
9657 *input_line_pointer
= ch
;
9660 as_bad ("Unknown opcode `%s'", mnemonic
);
9664 idesc
= parse_operands (idesc
);
9668 /* Handle the dynamic ops we can handle now: */
9669 if (idesc
->type
== IA64_TYPE_DYN
)
9671 if (strcmp (idesc
->name
, "add") == 0)
9673 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9674 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9678 ia64_free_opcode (idesc
);
9679 idesc
= ia64_find_opcode (mnemonic
);
9681 know (!idesc
->next
);
9684 else if (strcmp (idesc
->name
, "mov") == 0)
9686 enum ia64_opnd opnd1
, opnd2
;
9689 opnd1
= idesc
->operands
[0];
9690 opnd2
= idesc
->operands
[1];
9691 if (opnd1
== IA64_OPND_AR3
)
9693 else if (opnd2
== IA64_OPND_AR3
)
9697 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9698 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9702 ia64_free_opcode (idesc
);
9703 idesc
= ia64_find_opcode (mnemonic
);
9704 while (idesc
!= NULL
9705 && (idesc
->operands
[0] != opnd1
9706 || idesc
->operands
[1] != opnd2
))
9707 idesc
= get_next_opcode (idesc
);
9712 if (md
.qp
.X_op
== O_register
)
9714 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9715 md
.qp
.X_op
= O_absent
;
9718 flags
= idesc
->flags
;
9720 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9721 insn_group_break (1, 0, 0);
9723 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9725 as_bad ("`%s' cannot be predicated", idesc
->name
);
9729 /* Build the instruction. */
9730 CURR_SLOT
.qp_regno
= qp_regno
;
9731 CURR_SLOT
.idesc
= idesc
;
9732 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9733 dwarf2_where (&CURR_SLOT
.debug_line
);
9735 /* Add unwind entry, if there is one. */
9736 if (unwind
.current_entry
)
9738 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9739 unwind
.current_entry
= NULL
;
9742 /* Check for dependency violations. */
9746 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9747 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9750 if ((flags
& IA64_OPCODE_LAST
) != 0)
9751 insn_group_break (1, 0, 0);
9753 md
.last_text_seg
= now_seg
;
9756 input_line_pointer
= saved_input_line_pointer
;
9759 /* Called when symbol NAME cannot be found in the symbol table.
9760 Should be used for dynamic valued symbols only. */
9763 md_undefined_symbol (name
)
9764 char *name ATTRIBUTE_UNUSED
;
9769 /* Called for any expression that can not be recognized. When the
9770 function is called, `input_line_pointer' will point to the start of
9777 enum pseudo_type pseudo_type
;
9782 switch (*input_line_pointer
)
9785 /* Find what relocation pseudo-function we're dealing with. */
9787 ch
= *++input_line_pointer
;
9788 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9789 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9791 len
= strlen (pseudo_func
[i
].name
);
9792 if (strncmp (pseudo_func
[i
].name
+ 1,
9793 input_line_pointer
+ 1, len
- 1) == 0
9794 && !is_part_of_name (input_line_pointer
[len
]))
9796 input_line_pointer
+= len
;
9797 pseudo_type
= pseudo_func
[i
].type
;
9801 switch (pseudo_type
)
9803 case PSEUDO_FUNC_RELOC
:
9805 if (*input_line_pointer
!= '(')
9807 as_bad ("Expected '('");
9811 ++input_line_pointer
;
9813 if (*input_line_pointer
++ != ')')
9815 as_bad ("Missing ')'");
9818 if (e
->X_op
!= O_symbol
)
9820 if (e
->X_op
!= O_pseudo_fixup
)
9822 as_bad ("Not a symbolic expression");
9825 if (S_GET_VALUE (e
->X_op_symbol
) == FUNC_FPTR_RELATIVE
9826 && i
== FUNC_LT_RELATIVE
)
9827 i
= FUNC_LT_FPTR_RELATIVE
;
9830 as_bad ("Illegal combination of relocation functions");
9834 /* Make sure gas doesn't get rid of local symbols that are used
9836 e
->X_op
= O_pseudo_fixup
;
9837 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9840 case PSEUDO_FUNC_CONST
:
9841 e
->X_op
= O_constant
;
9842 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9845 case PSEUDO_FUNC_REG
:
9846 e
->X_op
= O_register
;
9847 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9851 name
= input_line_pointer
- 1;
9853 as_bad ("Unknown pseudo function `%s'", name
);
9859 ++input_line_pointer
;
9861 if (*input_line_pointer
!= ']')
9863 as_bad ("Closing bracket misssing");
9868 if (e
->X_op
!= O_register
)
9869 as_bad ("Register expected as index");
9871 ++input_line_pointer
;
9882 ignore_rest_of_line ();
9885 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9886 a section symbol plus some offset. For relocs involving @fptr(),
9887 directives we don't want such adjustments since we need to have the
9888 original symbol's name in the reloc. */
9890 ia64_fix_adjustable (fix
)
9893 /* Prevent all adjustments to global symbols */
9894 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9897 switch (fix
->fx_r_type
)
9899 case BFD_RELOC_IA64_FPTR64I
:
9900 case BFD_RELOC_IA64_FPTR32MSB
:
9901 case BFD_RELOC_IA64_FPTR32LSB
:
9902 case BFD_RELOC_IA64_FPTR64MSB
:
9903 case BFD_RELOC_IA64_FPTR64LSB
:
9904 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9905 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9915 ia64_force_relocation (fix
)
9918 switch (fix
->fx_r_type
)
9920 case BFD_RELOC_IA64_FPTR64I
:
9921 case BFD_RELOC_IA64_FPTR32MSB
:
9922 case BFD_RELOC_IA64_FPTR32LSB
:
9923 case BFD_RELOC_IA64_FPTR64MSB
:
9924 case BFD_RELOC_IA64_FPTR64LSB
:
9926 case BFD_RELOC_IA64_LTOFF22
:
9927 case BFD_RELOC_IA64_LTOFF64I
:
9928 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9929 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9930 case BFD_RELOC_IA64_PLTOFF22
:
9931 case BFD_RELOC_IA64_PLTOFF64I
:
9932 case BFD_RELOC_IA64_PLTOFF64MSB
:
9933 case BFD_RELOC_IA64_PLTOFF64LSB
:
9942 /* Decide from what point a pc-relative relocation is relative to,
9943 relative to the pc-relative fixup. Er, relatively speaking. */
9945 ia64_pcrel_from_section (fix
, sec
)
9949 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
9951 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
9957 /* This is called whenever some data item (not an instruction) needs a
9958 fixup. We pick the right reloc code depending on the byteorder
9959 currently in effect. */
9961 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
9967 bfd_reloc_code_real_type code
;
9972 /* There are no reloc for 8 and 16 bit quantities, but we allow
9973 them here since they will work fine as long as the expression
9974 is fully defined at the end of the pass over the source file. */
9975 case 1: code
= BFD_RELOC_8
; break;
9976 case 2: code
= BFD_RELOC_16
; break;
9978 if (target_big_endian
)
9979 code
= BFD_RELOC_IA64_DIR32MSB
;
9981 code
= BFD_RELOC_IA64_DIR32LSB
;
9985 if (target_big_endian
)
9986 code
= BFD_RELOC_IA64_DIR64MSB
;
9988 code
= BFD_RELOC_IA64_DIR64LSB
;
9992 if (exp
->X_op
== O_pseudo_fixup
9994 && S_GET_VALUE (exp
->X_op_symbol
) == FUNC_IPLT_RELOC
)
9996 if (target_big_endian
)
9997 code
= BFD_RELOC_IA64_IPLTMSB
;
9999 code
= BFD_RELOC_IA64_IPLTLSB
;
10001 exp
->X_op
= O_symbol
;
10007 as_bad ("Unsupported fixup size %d", nbytes
);
10008 ignore_rest_of_line ();
10011 if (exp
->X_op
== O_pseudo_fixup
)
10014 exp
->X_op
= O_symbol
;
10015 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
10018 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
10019 /* We need to store the byte order in effect in case we're going
10020 to fix an 8 or 16 bit relocation (for which there no real
10021 relocs available). See md_apply_fix3(). */
10022 fix
->tc_fix_data
.bigendian
= target_big_endian
;
10025 /* Return the actual relocation we wish to associate with the pseudo
10026 reloc described by SYM and R_TYPE. SYM should be one of the
10027 symbols in the pseudo_func array, or NULL. */
10029 static bfd_reloc_code_real_type
10030 ia64_gen_real_reloc_type (sym
, r_type
)
10031 struct symbol
*sym
;
10032 bfd_reloc_code_real_type r_type
;
10034 bfd_reloc_code_real_type
new = 0;
10041 switch (S_GET_VALUE (sym
))
10043 case FUNC_FPTR_RELATIVE
:
10046 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
10047 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
10048 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
10049 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
10050 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
10055 case FUNC_GP_RELATIVE
:
10058 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
10059 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
10060 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
10061 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
10062 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
10063 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
10068 case FUNC_LT_RELATIVE
:
10071 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
10072 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
10077 case FUNC_PC_RELATIVE
:
10080 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
10081 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
10082 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
10083 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
10084 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
10085 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
10090 case FUNC_PLT_RELATIVE
:
10093 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
10094 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
10095 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
10096 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
10101 case FUNC_SEC_RELATIVE
:
10104 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
10105 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
10106 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
10107 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
10112 case FUNC_SEG_RELATIVE
:
10115 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
10116 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
10117 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
10118 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
10123 case FUNC_LTV_RELATIVE
:
10126 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
10127 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
10128 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
10129 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
10134 case FUNC_LT_FPTR_RELATIVE
:
10137 case BFD_RELOC_IA64_IMM22
:
10138 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
10139 case BFD_RELOC_IA64_IMM64
:
10140 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
10146 case FUNC_IPLT_RELOC
:
10152 /* Hmmmm. Should this ever occur? */
10159 /* Here is where generate the appropriate reloc for pseudo relocation
10162 ia64_validate_fix (fix
)
10165 switch (fix
->fx_r_type
)
10167 case BFD_RELOC_IA64_FPTR64I
:
10168 case BFD_RELOC_IA64_FPTR32MSB
:
10169 case BFD_RELOC_IA64_FPTR64LSB
:
10170 case BFD_RELOC_IA64_LTOFF_FPTR22
:
10171 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
10172 if (fix
->fx_offset
!= 0)
10173 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10174 "No addend allowed in @fptr() relocation");
10184 fix_insn (fix
, odesc
, value
)
10186 const struct ia64_operand
*odesc
;
10189 bfd_vma insn
[3], t0
, t1
, control_bits
;
10194 slot
= fix
->fx_where
& 0x3;
10195 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
10197 /* Bundles are always in little-endian byte order */
10198 t0
= bfd_getl64 (fixpos
);
10199 t1
= bfd_getl64 (fixpos
+ 8);
10200 control_bits
= t0
& 0x1f;
10201 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
10202 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
10203 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
10206 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
10208 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
10209 insn
[2] |= (((value
& 0x7f) << 13)
10210 | (((value
>> 7) & 0x1ff) << 27)
10211 | (((value
>> 16) & 0x1f) << 22)
10212 | (((value
>> 21) & 0x1) << 21)
10213 | (((value
>> 63) & 0x1) << 36));
10215 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
10217 if (value
& ~0x3fffffffffffffffULL
)
10218 err
= "integer operand out of range";
10219 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
10220 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
10222 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
10225 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
10226 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
10227 | (((value
>> 0) & 0xfffff) << 13));
10230 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
10233 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
10235 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
10236 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
10237 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
10238 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
10241 /* Attempt to simplify or even eliminate a fixup. The return value is
10242 ignored; perhaps it was once meaningful, but now it is historical.
10243 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10245 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
10249 md_apply_fix3 (fix
, valP
, seg
)
10252 segT seg ATTRIBUTE_UNUSED
;
10255 valueT value
= * valP
;
10258 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
10262 switch (fix
->fx_r_type
)
10264 case BFD_RELOC_IA64_DIR32MSB
:
10265 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
10269 case BFD_RELOC_IA64_DIR32LSB
:
10270 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
10274 case BFD_RELOC_IA64_DIR64MSB
:
10275 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
10279 case BFD_RELOC_IA64_DIR64LSB
:
10280 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
10290 if (fix
->fx_r_type
== (int) BFD_RELOC_UNUSED
)
10292 /* This must be a TAG13 or TAG13b operand. There are no external
10293 relocs defined for them, so we must give an error. */
10294 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10295 "%s must have a constant value",
10296 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
10301 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
10302 work. There should be a better way to handle this. */
10304 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
10306 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
10308 if (fix
->tc_fix_data
.bigendian
)
10309 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
10311 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
10316 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
10321 /* Generate the BFD reloc to be stuck in the object file from the
10322 fixup used internally in the assembler. */
10325 tc_gen_reloc (sec
, fixp
)
10326 asection
*sec ATTRIBUTE_UNUSED
;
10331 reloc
= xmalloc (sizeof (*reloc
));
10332 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10333 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10334 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10335 reloc
->addend
= fixp
->fx_offset
;
10336 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
10340 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10341 "Cannot represent %s relocation in object file",
10342 bfd_get_reloc_code_name (fixp
->fx_r_type
));
10347 /* Turn a string in input_line_pointer into a floating point constant
10348 of type TYPE, and store the appropriate bytes in *LIT. The number
10349 of LITTLENUMS emitted is stored in *SIZE. An error message is
10350 returned, or NULL on OK. */
10352 #define MAX_LITTLENUMS 5
10355 md_atof (type
, lit
, size
)
10360 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
10361 LITTLENUM_TYPE
*word
;
10391 return "Bad call to MD_ATOF()";
10393 t
= atof_ieee (input_line_pointer
, type
, words
);
10395 input_line_pointer
= t
;
10396 *size
= prec
* sizeof (LITTLENUM_TYPE
);
10398 for (word
= words
+ prec
- 1; prec
--;)
10400 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
10401 lit
+= sizeof (LITTLENUM_TYPE
);
10406 /* Round up a section's size to the appropriate boundary. */
10408 md_section_align (seg
, size
)
10412 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10413 valueT mask
= ((valueT
) 1 << align
) - 1;
10415 return (size
+ mask
) & ~mask
;
10418 /* Handle ia64 specific semantics of the align directive. */
10421 ia64_md_do_align (n
, fill
, len
, max
)
10422 int n ATTRIBUTE_UNUSED
;
10423 const char *fill ATTRIBUTE_UNUSED
;
10424 int len ATTRIBUTE_UNUSED
;
10425 int max ATTRIBUTE_UNUSED
;
10427 if (subseg_text_p (now_seg
))
10428 ia64_flush_insns ();
10431 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10432 of an rs_align_code fragment. */
10435 ia64_handle_align (fragp
)
10438 /* Use mfi bundle of nops with no stop bits. */
10439 static const unsigned char be_nop
[]
10440 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10441 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10442 static const unsigned char le_nop
[]
10443 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10444 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10449 if (fragp
->fr_type
!= rs_align_code
)
10452 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
10453 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
10455 /* Make sure we are on a 16-byte boundary, in case someone has been
10456 putting data into a text section. */
10459 int fix
= bytes
& 15;
10460 memset (p
, 0, fix
);
10463 fragp
->fr_fix
+= fix
;
10466 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10467 fragp
->fr_var
= 16;