1 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
2 Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
35 - labels are wrong if automatic alignment is introduced
36 (e.g., checkout the second real10 definition in test-data.s)
38 <reg>.safe_across_calls and any other DV-related directives I don't
39 have documentation for.
40 verify mod-sched-brs reads/writes are checked/marked (and other
46 #include "safe-ctype.h"
47 #include "dwarf2dbg.h"
50 #include "opcode/ia64.h"
54 #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0])))
55 #define MIN(a,b) ((a) < (b) ? (a) : (b))
58 #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS]
59 #define CURR_SLOT md.slot[md.curr_slot]
61 #define O_pseudo_fixup (O_max + 1)
65 /* IA-64 ABI section pseudo-ops. */
66 SPECIAL_SECTION_BSS
= 0,
68 SPECIAL_SECTION_SDATA
,
69 SPECIAL_SECTION_RODATA
,
70 SPECIAL_SECTION_COMMENT
,
71 SPECIAL_SECTION_UNWIND
,
72 SPECIAL_SECTION_UNWIND_INFO
,
73 /* HPUX specific section pseudo-ops. */
74 SPECIAL_SECTION_INIT_ARRAY
,
75 SPECIAL_SECTION_FINI_ARRAY
,
91 FUNC_LT_FPTR_RELATIVE
,
101 REG_FR
= (REG_GR
+ 128),
102 REG_AR
= (REG_FR
+ 128),
103 REG_CR
= (REG_AR
+ 128),
104 REG_P
= (REG_CR
+ 128),
105 REG_BR
= (REG_P
+ 64),
106 REG_IP
= (REG_BR
+ 8),
113 /* The following are pseudo-registers for use by gas only. */
125 /* The following pseudo-registers are used for unwind directives only: */
133 DYNREG_GR
= 0, /* dynamic general purpose register */
134 DYNREG_FR
, /* dynamic floating point register */
135 DYNREG_PR
, /* dynamic predicate register */
139 enum operand_match_result
142 OPERAND_OUT_OF_RANGE
,
146 /* On the ia64, we can't know the address of a text label until the
147 instructions are packed into a bundle. To handle this, we keep
148 track of the list of labels that appear in front of each
152 struct label_fix
*next
;
156 extern int target_big_endian
;
158 /* Characters which always start a comment. */
159 const char comment_chars
[] = "";
161 /* Characters which start a comment at the beginning of a line. */
162 const char line_comment_chars
[] = "#";
164 /* Characters which may be used to separate multiple commands on a
166 const char line_separator_chars
[] = ";";
168 /* Characters which are used to indicate an exponent in a floating
170 const char EXP_CHARS
[] = "eE";
172 /* Characters which mean that a number is a floating point constant,
174 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
176 /* ia64-specific option processing: */
178 const char *md_shortopts
= "m:N:x::";
180 struct option md_longopts
[] =
182 #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1)
183 {"mconstant-gp", no_argument
, NULL
, OPTION_MCONSTANT_GP
},
184 #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2)
185 {"mauto-pic", no_argument
, NULL
, OPTION_MAUTO_PIC
}
188 size_t md_longopts_size
= sizeof (md_longopts
);
192 struct hash_control
*pseudo_hash
; /* pseudo opcode hash table */
193 struct hash_control
*reg_hash
; /* register name hash table */
194 struct hash_control
*dynreg_hash
; /* dynamic register hash table */
195 struct hash_control
*const_hash
; /* constant hash table */
196 struct hash_control
*entry_hash
; /* code entry hint hash table */
198 symbolS
*regsym
[REG_NUM
];
200 /* If X_op is != O_absent, the registername for the instruction's
201 qualifying predicate. If NULL, p0 is assumed for instructions
202 that are predicatable. */
209 explicit_mode
: 1, /* which mode we're in */
210 default_explicit_mode
: 1, /* which mode is the default */
211 mode_explicitly_set
: 1, /* was the current mode explicitly set? */
213 keep_pending_output
: 1;
215 /* Each bundle consists of up to three instructions. We keep
216 track of four most recent instructions so we can correctly set
217 the end_of_insn_group for the last instruction in a bundle. */
219 int num_slots_in_use
;
223 end_of_insn_group
: 1,
224 manual_bundling_on
: 1,
225 manual_bundling_off
: 1;
226 signed char user_template
; /* user-selected template, if any */
227 unsigned char qp_regno
; /* qualifying predicate */
228 /* This duplicates a good fraction of "struct fix" but we
229 can't use a "struct fix" instead since we can't call
230 fix_new_exp() until we know the address of the instruction. */
234 bfd_reloc_code_real_type code
;
235 enum ia64_opnd opnd
; /* type of operand in need of fix */
236 unsigned int is_pcrel
: 1; /* is operand pc-relative? */
237 expressionS expr
; /* the value to be inserted */
239 fixup
[2]; /* at most two fixups per insn */
240 struct ia64_opcode
*idesc
;
241 struct label_fix
*label_fixups
;
242 struct label_fix
*tag_fixups
;
243 struct unw_rec_list
*unwind_record
; /* Unwind directive. */
246 unsigned int src_line
;
247 struct dwarf2_line_info debug_line
;
255 struct dynreg
*next
; /* next dynamic register */
257 unsigned short base
; /* the base register number */
258 unsigned short num_regs
; /* # of registers in this set */
260 *dynreg
[DYNREG_NUM_TYPES
], in
, loc
, out
, rot
;
262 flagword flags
; /* ELF-header flags */
265 unsigned hint
:1; /* is this hint currently valid? */
266 bfd_vma offset
; /* mem.offset offset */
267 bfd_vma base
; /* mem.offset base */
270 int path
; /* number of alt. entry points seen */
271 const char **entry_labels
; /* labels of all alternate paths in
272 the current DV-checking block. */
273 int maxpaths
; /* size currently allocated for
275 /* Support for hardware errata workarounds. */
277 /* Record data about the last three insn groups. */
280 /* B-step workaround.
281 For each predicate register, this is set if the corresponding insn
282 group conditionally sets this register with one of the affected
285 /* B-step workaround.
286 For each general register, this is set if the corresponding insn
287 a) is conditional one one of the predicate registers for which
288 P_REG_SET is 1 in the corresponding entry of the previous group,
289 b) sets this general register with one of the affected
291 int g_reg_set_conditionally
[128];
295 int pointer_size
; /* size in bytes of a pointer */
296 int pointer_size_shift
; /* shift size of a pointer for alignment */
300 /* application registers: */
306 #define AR_BSPSTORE 18
321 {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
322 {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
323 {"ar.rsc", 16}, {"ar.bsp", 17},
324 {"ar.bspstore", 18}, {"ar.rnat", 19},
325 {"ar.fcr", 21}, {"ar.eflag", 24},
326 {"ar.csd", 25}, {"ar.ssd", 26},
327 {"ar.cflg", 27}, {"ar.fsr", 28},
328 {"ar.fir", 29}, {"ar.fdr", 30},
329 {"ar.ccv", 32}, {"ar.unat", 36},
330 {"ar.fpsr", 40}, {"ar.itc", 44},
331 {"ar.pfs", 64}, {"ar.lc", 65},
352 /* control registers: */
394 static const struct const_desc
401 /* PSR constant masks: */
404 {"psr.be", ((valueT
) 1) << 1},
405 {"psr.up", ((valueT
) 1) << 2},
406 {"psr.ac", ((valueT
) 1) << 3},
407 {"psr.mfl", ((valueT
) 1) << 4},
408 {"psr.mfh", ((valueT
) 1) << 5},
410 {"psr.ic", ((valueT
) 1) << 13},
411 {"psr.i", ((valueT
) 1) << 14},
412 {"psr.pk", ((valueT
) 1) << 15},
414 {"psr.dt", ((valueT
) 1) << 17},
415 {"psr.dfl", ((valueT
) 1) << 18},
416 {"psr.dfh", ((valueT
) 1) << 19},
417 {"psr.sp", ((valueT
) 1) << 20},
418 {"psr.pp", ((valueT
) 1) << 21},
419 {"psr.di", ((valueT
) 1) << 22},
420 {"psr.si", ((valueT
) 1) << 23},
421 {"psr.db", ((valueT
) 1) << 24},
422 {"psr.lp", ((valueT
) 1) << 25},
423 {"psr.tb", ((valueT
) 1) << 26},
424 {"psr.rt", ((valueT
) 1) << 27},
425 /* 28-31: reserved */
426 /* 32-33: cpl (current privilege level) */
427 {"psr.is", ((valueT
) 1) << 34},
428 {"psr.mc", ((valueT
) 1) << 35},
429 {"psr.it", ((valueT
) 1) << 36},
430 {"psr.id", ((valueT
) 1) << 37},
431 {"psr.da", ((valueT
) 1) << 38},
432 {"psr.dd", ((valueT
) 1) << 39},
433 {"psr.ss", ((valueT
) 1) << 40},
434 /* 41-42: ri (restart instruction) */
435 {"psr.ed", ((valueT
) 1) << 43},
436 {"psr.bn", ((valueT
) 1) << 44},
439 /* indirect register-sets/memory: */
448 { "CPUID", IND_CPUID
},
449 { "cpuid", IND_CPUID
},
461 /* Pseudo functions used to indicate relocation types (these functions
462 start with an at sign (@). */
484 /* reloc pseudo functions (these must come first!): */
485 { "dtpmod", PSEUDO_FUNC_RELOC
, { 0 } },
486 { "dtprel", PSEUDO_FUNC_RELOC
, { 0 } },
487 { "fptr", PSEUDO_FUNC_RELOC
, { 0 } },
488 { "gprel", PSEUDO_FUNC_RELOC
, { 0 } },
489 { "ltoff", PSEUDO_FUNC_RELOC
, { 0 } },
490 { "pcrel", PSEUDO_FUNC_RELOC
, { 0 } },
491 { "pltoff", PSEUDO_FUNC_RELOC
, { 0 } },
492 { "secrel", PSEUDO_FUNC_RELOC
, { 0 } },
493 { "segrel", PSEUDO_FUNC_RELOC
, { 0 } },
494 { "tprel", PSEUDO_FUNC_RELOC
, { 0 } },
495 { "ltv", PSEUDO_FUNC_RELOC
, { 0 } },
496 { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */
497 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */
498 { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */
499 { "", 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */
500 { "iplt", PSEUDO_FUNC_RELOC
, { 0 } },
502 /* mbtype4 constants: */
503 { "alt", PSEUDO_FUNC_CONST
, { 0xa } },
504 { "brcst", PSEUDO_FUNC_CONST
, { 0x0 } },
505 { "mix", PSEUDO_FUNC_CONST
, { 0x8 } },
506 { "rev", PSEUDO_FUNC_CONST
, { 0xb } },
507 { "shuf", PSEUDO_FUNC_CONST
, { 0x9 } },
509 /* fclass constants: */
510 { "nat", PSEUDO_FUNC_CONST
, { 0x100 } },
511 { "qnan", PSEUDO_FUNC_CONST
, { 0x080 } },
512 { "snan", PSEUDO_FUNC_CONST
, { 0x040 } },
513 { "pos", PSEUDO_FUNC_CONST
, { 0x001 } },
514 { "neg", PSEUDO_FUNC_CONST
, { 0x002 } },
515 { "zero", PSEUDO_FUNC_CONST
, { 0x004 } },
516 { "unorm", PSEUDO_FUNC_CONST
, { 0x008 } },
517 { "norm", PSEUDO_FUNC_CONST
, { 0x010 } },
518 { "inf", PSEUDO_FUNC_CONST
, { 0x020 } },
520 { "natval", PSEUDO_FUNC_CONST
, { 0x100 } }, /* old usage */
522 /* hint constants: */
523 { "pause", PSEUDO_FUNC_CONST
, { 0x0 } },
525 /* unwind-related constants: */
526 { "svr4", PSEUDO_FUNC_CONST
, { 0 } },
527 { "hpux", PSEUDO_FUNC_CONST
, { 1 } },
528 { "nt", PSEUDO_FUNC_CONST
, { 2 } },
530 /* unwind-related registers: */
531 { "priunat",PSEUDO_FUNC_REG
, { REG_PRIUNAT
} }
534 /* 41-bit nop opcodes (one per unit): */
535 static const bfd_vma nop
[IA64_NUM_UNITS
] =
537 0x0000000000LL
, /* NIL => break 0 */
538 0x0008000000LL
, /* I-unit nop */
539 0x0008000000LL
, /* M-unit nop */
540 0x4000000000LL
, /* B-unit nop */
541 0x0008000000LL
, /* F-unit nop */
542 0x0008000000LL
, /* L-"unit" nop */
543 0x0008000000LL
, /* X-unit nop */
546 /* Can't be `const' as it's passed to input routines (which have the
547 habit of setting temporary sentinels. */
548 static char special_section_name
[][20] =
550 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"},
551 {".IA_64.unwind"}, {".IA_64.unwind_info"},
552 {".init_array"}, {".fini_array"}
555 static char *special_linkonce_name
[] =
557 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
560 /* The best template for a particular sequence of up to three
562 #define N IA64_NUM_TYPES
563 static unsigned char best_template
[N
][N
][N
];
566 /* Resource dependencies currently in effect */
568 int depind
; /* dependency index */
569 const struct ia64_dependency
*dependency
; /* actual dependency */
570 unsigned specific
:1, /* is this a specific bit/regno? */
571 link_to_qp_branch
:1; /* will a branch on the same QP clear it?*/
572 int index
; /* specific regno/bit within dependency */
573 int note
; /* optional qualifying note (0 if none) */
577 int insn_srlz
; /* current insn serialization state */
578 int data_srlz
; /* current data serialization state */
579 int qp_regno
; /* qualifying predicate for this usage */
580 char *file
; /* what file marked this dependency */
581 unsigned int line
; /* what line marked this dependency */
582 struct mem_offset mem_offset
; /* optional memory offset hint */
583 enum { CMP_NONE
, CMP_OR
, CMP_AND
} cmp_type
; /* OR or AND compare? */
584 int path
; /* corresponding code entry index */
586 static int regdepslen
= 0;
587 static int regdepstotlen
= 0;
588 static const char *dv_mode
[] = { "RAW", "WAW", "WAR" };
589 static const char *dv_sem
[] = { "none", "implied", "impliedf",
590 "data", "instr", "specific", "stop", "other" };
591 static const char *dv_cmp_type
[] = { "none", "OR", "AND" };
593 /* Current state of PR mutexation */
594 static struct qpmutex
{
597 } *qp_mutexes
= NULL
; /* QP mutex bitmasks */
598 static int qp_mutexeslen
= 0;
599 static int qp_mutexestotlen
= 0;
600 static valueT qp_safe_across_calls
= 0;
602 /* Current state of PR implications */
603 static struct qp_imply
{
606 unsigned p2_branched
:1;
608 } *qp_implies
= NULL
;
609 static int qp_implieslen
= 0;
610 static int qp_impliestotlen
= 0;
612 /* Keep track of static GR values so that indirect register usage can
613 sometimes be tracked. */
618 } gr_values
[128] = {{ 1, 0, 0 }};
620 /* These are the routines required to output the various types of
623 /* A slot_number is a frag address plus the slot index (0-2). We use the
624 frag address here so that if there is a section switch in the middle of
625 a function, then instructions emitted to a different section are not
626 counted. Since there may be more than one frag for a function, this
627 means we also need to keep track of which frag this address belongs to
628 so we can compute inter-frag distances. This also nicely solves the
629 problem with nops emitted for align directives, which can't easily be
630 counted, but can easily be derived from frag sizes. */
632 typedef struct unw_rec_list
{
634 unsigned long slot_number
;
636 struct unw_rec_list
*next
;
639 #define SLOT_NUM_NOT_SET (unsigned)-1
641 /* Linked list of saved prologue counts. A very poor
642 implementation of a map from label numbers to prologue counts. */
643 typedef struct label_prologue_count
645 struct label_prologue_count
*next
;
646 unsigned long label_number
;
647 unsigned int prologue_count
;
648 } label_prologue_count
;
652 unsigned long next_slot_number
;
653 fragS
*next_slot_frag
;
655 /* Maintain a list of unwind entries for the current function. */
659 /* Any unwind entires that should be attached to the current slot
660 that an insn is being constructed for. */
661 unw_rec_list
*current_entry
;
663 /* These are used to create the unwind table entry for this function. */
666 symbolS
*info
; /* pointer to unwind info */
667 symbolS
*personality_routine
;
669 subsegT saved_text_subseg
;
670 unsigned int force_unwind_entry
: 1; /* force generation of unwind entry? */
672 /* TRUE if processing unwind directives in a prologue region. */
675 unsigned int prologue_count
; /* number of .prologues seen so far */
676 /* Prologue counts at previous .label_state directives. */
677 struct label_prologue_count
* saved_prologue_counts
;
680 typedef void (*vbyte_func
) PARAMS ((int, char *, char *));
682 /* Forward delarations: */
683 static int ar_is_in_integer_unit
PARAMS ((int regnum
));
684 static void set_section
PARAMS ((char *name
));
685 static unsigned int set_regstack
PARAMS ((unsigned int, unsigned int,
686 unsigned int, unsigned int));
687 static void dot_radix
PARAMS ((int));
688 static void dot_special_section
PARAMS ((int));
689 static void dot_proc
PARAMS ((int));
690 static void dot_fframe
PARAMS ((int));
691 static void dot_vframe
PARAMS ((int));
692 static void dot_vframesp
PARAMS ((int));
693 static void dot_vframepsp
PARAMS ((int));
694 static void dot_save
PARAMS ((int));
695 static void dot_restore
PARAMS ((int));
696 static void dot_restorereg
PARAMS ((int));
697 static void dot_restorereg_p
PARAMS ((int));
698 static void dot_handlerdata
PARAMS ((int));
699 static void dot_unwentry
PARAMS ((int));
700 static void dot_altrp
PARAMS ((int));
701 static void dot_savemem
PARAMS ((int));
702 static void dot_saveg
PARAMS ((int));
703 static void dot_savef
PARAMS ((int));
704 static void dot_saveb
PARAMS ((int));
705 static void dot_savegf
PARAMS ((int));
706 static void dot_spill
PARAMS ((int));
707 static void dot_spillreg
PARAMS ((int));
708 static void dot_spillmem
PARAMS ((int));
709 static void dot_spillreg_p
PARAMS ((int));
710 static void dot_spillmem_p
PARAMS ((int));
711 static void dot_label_state
PARAMS ((int));
712 static void dot_copy_state
PARAMS ((int));
713 static void dot_unwabi
PARAMS ((int));
714 static void dot_personality
PARAMS ((int));
715 static void dot_body
PARAMS ((int));
716 static void dot_prologue
PARAMS ((int));
717 static void dot_endp
PARAMS ((int));
718 static void dot_template
PARAMS ((int));
719 static void dot_regstk
PARAMS ((int));
720 static void dot_rot
PARAMS ((int));
721 static void dot_byteorder
PARAMS ((int));
722 static void dot_psr
PARAMS ((int));
723 static void dot_alias
PARAMS ((int));
724 static void dot_ln
PARAMS ((int));
725 static char *parse_section_name
PARAMS ((void));
726 static void dot_xdata
PARAMS ((int));
727 static void stmt_float_cons
PARAMS ((int));
728 static void stmt_cons_ua
PARAMS ((int));
729 static void dot_xfloat_cons
PARAMS ((int));
730 static void dot_xstringer
PARAMS ((int));
731 static void dot_xdata_ua
PARAMS ((int));
732 static void dot_xfloat_cons_ua
PARAMS ((int));
733 static void print_prmask
PARAMS ((valueT mask
));
734 static void dot_pred_rel
PARAMS ((int));
735 static void dot_reg_val
PARAMS ((int));
736 static void dot_dv_mode
PARAMS ((int));
737 static void dot_entry
PARAMS ((int));
738 static void dot_mem_offset
PARAMS ((int));
739 static void add_unwind_entry
PARAMS((unw_rec_list
*ptr
));
740 static symbolS
*declare_register
PARAMS ((const char *name
, int regnum
));
741 static void declare_register_set
PARAMS ((const char *, int, int));
742 static unsigned int operand_width
PARAMS ((enum ia64_opnd
));
743 static enum operand_match_result operand_match
PARAMS ((const struct ia64_opcode
*idesc
,
746 static int parse_operand
PARAMS ((expressionS
*e
));
747 static struct ia64_opcode
* parse_operands
PARAMS ((struct ia64_opcode
*));
748 static int errata_nop_necessary_p
PARAMS ((struct slot
*, enum ia64_unit
));
749 static void build_insn
PARAMS ((struct slot
*, bfd_vma
*));
750 static void emit_one_bundle
PARAMS ((void));
751 static void fix_insn
PARAMS ((fixS
*, const struct ia64_operand
*, valueT
));
752 static bfd_reloc_code_real_type ia64_gen_real_reloc_type
PARAMS ((struct symbol
*sym
,
753 bfd_reloc_code_real_type r_type
));
754 static void insn_group_break
PARAMS ((int, int, int));
755 static void mark_resource
PARAMS ((struct ia64_opcode
*, const struct ia64_dependency
*,
756 struct rsrc
*, int depind
, int path
));
757 static void add_qp_mutex
PARAMS((valueT mask
));
758 static void add_qp_imply
PARAMS((int p1
, int p2
));
759 static void clear_qp_branch_flag
PARAMS((valueT mask
));
760 static void clear_qp_mutex
PARAMS((valueT mask
));
761 static void clear_qp_implies
PARAMS((valueT p1_mask
, valueT p2_mask
));
762 static int has_suffix_p
PARAMS((const char *, const char *));
763 static void clear_register_values
PARAMS ((void));
764 static void print_dependency
PARAMS ((const char *action
, int depind
));
765 static void instruction_serialization
PARAMS ((void));
766 static void data_serialization
PARAMS ((void));
767 static void remove_marked_resource
PARAMS ((struct rsrc
*));
768 static int is_conditional_branch
PARAMS ((struct ia64_opcode
*));
769 static int is_taken_branch
PARAMS ((struct ia64_opcode
*));
770 static int is_interruption_or_rfi
PARAMS ((struct ia64_opcode
*));
771 static int depends_on
PARAMS ((int, struct ia64_opcode
*));
772 static int specify_resource
PARAMS ((const struct ia64_dependency
*,
773 struct ia64_opcode
*, int, struct rsrc
[], int, int));
774 static int check_dv
PARAMS((struct ia64_opcode
*idesc
));
775 static void check_dependencies
PARAMS((struct ia64_opcode
*));
776 static void mark_resources
PARAMS((struct ia64_opcode
*));
777 static void update_dependencies
PARAMS((struct ia64_opcode
*));
778 static void note_register_values
PARAMS((struct ia64_opcode
*));
779 static int qp_mutex
PARAMS ((int, int, int));
780 static int resources_match
PARAMS ((struct rsrc
*, struct ia64_opcode
*, int, int, int));
781 static void output_vbyte_mem
PARAMS ((int, char *, char *));
782 static void count_output
PARAMS ((int, char *, char *));
783 static void output_R1_format
PARAMS ((vbyte_func
, unw_record_type
, int));
784 static void output_R2_format
PARAMS ((vbyte_func
, int, int, unsigned long));
785 static void output_R3_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
786 static void output_P1_format
PARAMS ((vbyte_func
, int));
787 static void output_P2_format
PARAMS ((vbyte_func
, int, int));
788 static void output_P3_format
PARAMS ((vbyte_func
, unw_record_type
, int));
789 static void output_P4_format
PARAMS ((vbyte_func
, unsigned char *, unsigned long));
790 static void output_P5_format
PARAMS ((vbyte_func
, int, unsigned long));
791 static void output_P6_format
PARAMS ((vbyte_func
, unw_record_type
, int));
792 static void output_P7_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long, unsigned long));
793 static void output_P8_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
794 static void output_P9_format
PARAMS ((vbyte_func
, int, int));
795 static void output_P10_format
PARAMS ((vbyte_func
, int, int));
796 static void output_B1_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
797 static void output_B2_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
798 static void output_B3_format
PARAMS ((vbyte_func
, unsigned long, unsigned long));
799 static void output_B4_format
PARAMS ((vbyte_func
, unw_record_type
, unsigned long));
800 static char format_ab_reg
PARAMS ((int, int));
801 static void output_X1_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, unsigned long,
803 static void output_X2_format
PARAMS ((vbyte_func
, int, int, int, int, int, unsigned long));
804 static void output_X3_format
PARAMS ((vbyte_func
, unw_record_type
, int, int, int, unsigned long,
806 static void output_X4_format
PARAMS ((vbyte_func
, int, int, int, int, int, int, unsigned long));
807 static void free_list_records
PARAMS ((unw_rec_list
*));
808 static unw_rec_list
*output_prologue
PARAMS ((void));
809 static unw_rec_list
*output_prologue_gr
PARAMS ((unsigned int, unsigned int));
810 static unw_rec_list
*output_body
PARAMS ((void));
811 static unw_rec_list
*output_mem_stack_f
PARAMS ((unsigned int));
812 static unw_rec_list
*output_mem_stack_v
PARAMS ((void));
813 static unw_rec_list
*output_psp_gr
PARAMS ((unsigned int));
814 static unw_rec_list
*output_psp_sprel
PARAMS ((unsigned int));
815 static unw_rec_list
*output_rp_when
PARAMS ((void));
816 static unw_rec_list
*output_rp_gr
PARAMS ((unsigned int));
817 static unw_rec_list
*output_rp_br
PARAMS ((unsigned int));
818 static unw_rec_list
*output_rp_psprel
PARAMS ((unsigned int));
819 static unw_rec_list
*output_rp_sprel
PARAMS ((unsigned int));
820 static unw_rec_list
*output_pfs_when
PARAMS ((void));
821 static unw_rec_list
*output_pfs_gr
PARAMS ((unsigned int));
822 static unw_rec_list
*output_pfs_psprel
PARAMS ((unsigned int));
823 static unw_rec_list
*output_pfs_sprel
PARAMS ((unsigned int));
824 static unw_rec_list
*output_preds_when
PARAMS ((void));
825 static unw_rec_list
*output_preds_gr
PARAMS ((unsigned int));
826 static unw_rec_list
*output_preds_psprel
PARAMS ((unsigned int));
827 static unw_rec_list
*output_preds_sprel
PARAMS ((unsigned int));
828 static unw_rec_list
*output_fr_mem
PARAMS ((unsigned int));
829 static unw_rec_list
*output_frgr_mem
PARAMS ((unsigned int, unsigned int));
830 static unw_rec_list
*output_gr_gr
PARAMS ((unsigned int, unsigned int));
831 static unw_rec_list
*output_gr_mem
PARAMS ((unsigned int));
832 static unw_rec_list
*output_br_mem
PARAMS ((unsigned int));
833 static unw_rec_list
*output_br_gr
PARAMS ((unsigned int, unsigned int));
834 static unw_rec_list
*output_spill_base
PARAMS ((unsigned int));
835 static unw_rec_list
*output_unat_when
PARAMS ((void));
836 static unw_rec_list
*output_unat_gr
PARAMS ((unsigned int));
837 static unw_rec_list
*output_unat_psprel
PARAMS ((unsigned int));
838 static unw_rec_list
*output_unat_sprel
PARAMS ((unsigned int));
839 static unw_rec_list
*output_lc_when
PARAMS ((void));
840 static unw_rec_list
*output_lc_gr
PARAMS ((unsigned int));
841 static unw_rec_list
*output_lc_psprel
PARAMS ((unsigned int));
842 static unw_rec_list
*output_lc_sprel
PARAMS ((unsigned int));
843 static unw_rec_list
*output_fpsr_when
PARAMS ((void));
844 static unw_rec_list
*output_fpsr_gr
PARAMS ((unsigned int));
845 static unw_rec_list
*output_fpsr_psprel
PARAMS ((unsigned int));
846 static unw_rec_list
*output_fpsr_sprel
PARAMS ((unsigned int));
847 static unw_rec_list
*output_priunat_when_gr
PARAMS ((void));
848 static unw_rec_list
*output_priunat_when_mem
PARAMS ((void));
849 static unw_rec_list
*output_priunat_gr
PARAMS ((unsigned int));
850 static unw_rec_list
*output_priunat_psprel
PARAMS ((unsigned int));
851 static unw_rec_list
*output_priunat_sprel
PARAMS ((unsigned int));
852 static unw_rec_list
*output_bsp_when
PARAMS ((void));
853 static unw_rec_list
*output_bsp_gr
PARAMS ((unsigned int));
854 static unw_rec_list
*output_bsp_psprel
PARAMS ((unsigned int));
855 static unw_rec_list
*output_bsp_sprel
PARAMS ((unsigned int));
856 static unw_rec_list
*output_bspstore_when
PARAMS ((void));
857 static unw_rec_list
*output_bspstore_gr
PARAMS ((unsigned int));
858 static unw_rec_list
*output_bspstore_psprel
PARAMS ((unsigned int));
859 static unw_rec_list
*output_bspstore_sprel
PARAMS ((unsigned int));
860 static unw_rec_list
*output_rnat_when
PARAMS ((void));
861 static unw_rec_list
*output_rnat_gr
PARAMS ((unsigned int));
862 static unw_rec_list
*output_rnat_psprel
PARAMS ((unsigned int));
863 static unw_rec_list
*output_rnat_sprel
PARAMS ((unsigned int));
864 static unw_rec_list
*output_unwabi
PARAMS ((unsigned long, unsigned long));
865 static unw_rec_list
*output_epilogue
PARAMS ((unsigned long));
866 static unw_rec_list
*output_label_state
PARAMS ((unsigned long));
867 static unw_rec_list
*output_copy_state
PARAMS ((unsigned long));
868 static unw_rec_list
*output_spill_psprel
PARAMS ((unsigned int, unsigned int, unsigned int));
869 static unw_rec_list
*output_spill_sprel
PARAMS ((unsigned int, unsigned int, unsigned int));
870 static unw_rec_list
*output_spill_psprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
872 static unw_rec_list
*output_spill_sprel_p
PARAMS ((unsigned int, unsigned int, unsigned int,
874 static unw_rec_list
*output_spill_reg
PARAMS ((unsigned int, unsigned int, unsigned int,
876 static unw_rec_list
*output_spill_reg_p
PARAMS ((unsigned int, unsigned int, unsigned int,
877 unsigned int, unsigned int));
878 static void process_one_record
PARAMS ((unw_rec_list
*, vbyte_func
));
879 static void process_unw_records
PARAMS ((unw_rec_list
*, vbyte_func
));
880 static int calc_record_size
PARAMS ((unw_rec_list
*));
881 static void set_imask
PARAMS ((unw_rec_list
*, unsigned long, unsigned long, unsigned int));
882 static int count_bits
PARAMS ((unsigned long));
883 static unsigned long slot_index
PARAMS ((unsigned long, fragS
*,
884 unsigned long, fragS
*));
885 static unw_rec_list
*optimize_unw_records
PARAMS ((unw_rec_list
*));
886 static void fixup_unw_records
PARAMS ((unw_rec_list
*));
887 static int output_unw_records
PARAMS ((unw_rec_list
*, void **));
888 static int convert_expr_to_ab_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
889 static int convert_expr_to_xy_reg
PARAMS ((expressionS
*, unsigned int *, unsigned int *));
890 static int generate_unwind_image
PARAMS ((const char *));
891 static unsigned int get_saved_prologue_count
PARAMS ((unsigned long));
892 static void save_prologue_count
PARAMS ((unsigned long, unsigned int));
893 static void free_saved_prologue_counts
PARAMS ((void));
895 /* Build the unwind section name by appending the (possibly stripped)
896 text section NAME to the unwind PREFIX. The resulting string
897 pointer is assigned to RESULT. The string is allocated on the
898 stack, so this must be a macro... */
899 #define make_unw_section_name(special, text_name, result) \
901 const char *_prefix = special_section_name[special]; \
902 const char *_suffix = text_name; \
903 size_t _prefix_len, _suffix_len; \
905 if (strncmp (text_name, ".gnu.linkonce.t.", \
906 sizeof (".gnu.linkonce.t.") - 1) == 0) \
908 _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
909 _suffix += sizeof (".gnu.linkonce.t.") - 1; \
911 _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \
912 _result = alloca (_prefix_len + _suffix_len + 1); \
913 memcpy (_result, _prefix, _prefix_len); \
914 memcpy (_result + _prefix_len, _suffix, _suffix_len); \
915 _result[_prefix_len + _suffix_len] = '\0'; \
920 /* Determine if application register REGNUM resides in the integer
921 unit (as opposed to the memory unit). */
923 ar_is_in_integer_unit (reg
)
928 return (reg
== 64 /* pfs */
929 || reg
== 65 /* lc */
930 || reg
== 66 /* ec */
931 /* ??? ias accepts and puts these in the integer unit. */
932 || (reg
>= 112 && reg
<= 127));
935 /* Switch to section NAME and create section if necessary. It's
936 rather ugly that we have to manipulate input_line_pointer but I
937 don't see any other way to accomplish the same thing without
938 changing obj-elf.c (which may be the Right Thing, in the end). */
943 char *saved_input_line_pointer
;
945 saved_input_line_pointer
= input_line_pointer
;
946 input_line_pointer
= name
;
948 input_line_pointer
= saved_input_line_pointer
;
951 /* Map 's' to SHF_IA_64_SHORT. */
954 ia64_elf_section_letter (letter
, ptr_msg
)
959 return SHF_IA_64_SHORT
;
961 *ptr_msg
= _("Bad .section directive: want a,s,w,x,M,S,G,T in string");
965 /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */
968 ia64_elf_section_flags (flags
, attr
, type
)
970 int attr
, type ATTRIBUTE_UNUSED
;
972 if (attr
& SHF_IA_64_SHORT
)
973 flags
|= SEC_SMALL_DATA
;
978 ia64_elf_section_type (str
, len
)
982 #define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0))
984 if (STREQ (ELF_STRING_ia64_unwind_info
))
987 if (STREQ (ELF_STRING_ia64_unwind_info_once
))
990 if (STREQ (ELF_STRING_ia64_unwind
))
991 return SHT_IA_64_UNWIND
;
993 if (STREQ (ELF_STRING_ia64_unwind_once
))
994 return SHT_IA_64_UNWIND
;
996 if (STREQ ("init_array"))
997 return SHT_INIT_ARRAY
;
999 if (STREQ ("fini_array"))
1000 return SHT_FINI_ARRAY
;
1007 set_regstack (ins
, locs
, outs
, rots
)
1008 unsigned int ins
, locs
, outs
, rots
;
1010 /* Size of frame. */
1013 sof
= ins
+ locs
+ outs
;
1016 as_bad ("Size of frame exceeds maximum of 96 registers");
1021 as_warn ("Size of rotating registers exceeds frame size");
1024 md
.in
.base
= REG_GR
+ 32;
1025 md
.loc
.base
= md
.in
.base
+ ins
;
1026 md
.out
.base
= md
.loc
.base
+ locs
;
1028 md
.in
.num_regs
= ins
;
1029 md
.loc
.num_regs
= locs
;
1030 md
.out
.num_regs
= outs
;
1031 md
.rot
.num_regs
= rots
;
1038 struct label_fix
*lfix
;
1040 subsegT saved_subseg
;
1043 if (!md
.last_text_seg
)
1046 saved_seg
= now_seg
;
1047 saved_subseg
= now_subseg
;
1049 subseg_set (md
.last_text_seg
, 0);
1051 while (md
.num_slots_in_use
> 0)
1052 emit_one_bundle (); /* force out queued instructions */
1054 /* In case there are labels following the last instruction, resolve
1056 for (lfix
= CURR_SLOT
.label_fixups
; lfix
; lfix
= lfix
->next
)
1058 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1059 symbol_set_frag (lfix
->sym
, frag_now
);
1061 CURR_SLOT
.label_fixups
= 0;
1062 for (lfix
= CURR_SLOT
.tag_fixups
; lfix
; lfix
= lfix
->next
)
1064 S_SET_VALUE (lfix
->sym
, frag_now_fix ());
1065 symbol_set_frag (lfix
->sym
, frag_now
);
1067 CURR_SLOT
.tag_fixups
= 0;
1069 /* In case there are unwind directives following the last instruction,
1070 resolve those now. We only handle body and prologue directives here.
1071 Give an error for others. */
1072 for (ptr
= unwind
.current_entry
; ptr
; ptr
= ptr
->next
)
1074 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
1075 || ptr
->r
.type
== body
)
1077 ptr
->slot_number
= (unsigned long) frag_more (0);
1078 ptr
->slot_frag
= frag_now
;
1081 as_bad (_("Unwind directive not followed by an instruction."));
1083 unwind
.current_entry
= NULL
;
1085 subseg_set (saved_seg
, saved_subseg
);
1087 if (md
.qp
.X_op
== O_register
)
1088 as_bad ("qualifying predicate not followed by instruction");
1092 ia64_do_align (nbytes
)
1095 char *saved_input_line_pointer
= input_line_pointer
;
1097 input_line_pointer
= "";
1098 s_align_bytes (nbytes
);
1099 input_line_pointer
= saved_input_line_pointer
;
1103 ia64_cons_align (nbytes
)
1108 char *saved_input_line_pointer
= input_line_pointer
;
1109 input_line_pointer
= "";
1110 s_align_bytes (nbytes
);
1111 input_line_pointer
= saved_input_line_pointer
;
1115 /* Output COUNT bytes to a memory location. */
1116 static unsigned char *vbyte_mem_ptr
= NULL
;
1119 output_vbyte_mem (count
, ptr
, comment
)
1122 char *comment ATTRIBUTE_UNUSED
;
1125 if (vbyte_mem_ptr
== NULL
)
1130 for (x
= 0; x
< count
; x
++)
1131 *(vbyte_mem_ptr
++) = ptr
[x
];
1134 /* Count the number of bytes required for records. */
1135 static int vbyte_count
= 0;
1137 count_output (count
, ptr
, comment
)
1139 char *ptr ATTRIBUTE_UNUSED
;
1140 char *comment ATTRIBUTE_UNUSED
;
1142 vbyte_count
+= count
;
1146 output_R1_format (f
, rtype
, rlen
)
1148 unw_record_type rtype
;
1155 output_R3_format (f
, rtype
, rlen
);
1161 else if (rtype
!= prologue
)
1162 as_bad ("record type is not valid");
1164 byte
= UNW_R1
| (r
<< 5) | (rlen
& 0x1f);
1165 (*f
) (1, &byte
, NULL
);
1169 output_R2_format (f
, mask
, grsave
, rlen
)
1176 mask
= (mask
& 0x0f);
1177 grsave
= (grsave
& 0x7f);
1179 bytes
[0] = (UNW_R2
| (mask
>> 1));
1180 bytes
[1] = (((mask
& 0x01) << 7) | grsave
);
1181 count
+= output_leb128 (bytes
+ 2, rlen
, 0);
1182 (*f
) (count
, bytes
, NULL
);
1186 output_R3_format (f
, rtype
, rlen
)
1188 unw_record_type rtype
;
1195 output_R1_format (f
, rtype
, rlen
);
1201 else if (rtype
!= prologue
)
1202 as_bad ("record type is not valid");
1203 bytes
[0] = (UNW_R3
| r
);
1204 count
= output_leb128 (bytes
+ 1, rlen
, 0);
1205 (*f
) (count
+ 1, bytes
, NULL
);
1209 output_P1_format (f
, brmask
)
1214 byte
= UNW_P1
| (brmask
& 0x1f);
1215 (*f
) (1, &byte
, NULL
);
1219 output_P2_format (f
, brmask
, gr
)
1225 brmask
= (brmask
& 0x1f);
1226 bytes
[0] = UNW_P2
| (brmask
>> 1);
1227 bytes
[1] = (((brmask
& 1) << 7) | gr
);
1228 (*f
) (2, bytes
, NULL
);
1232 output_P3_format (f
, rtype
, reg
)
1234 unw_record_type rtype
;
1279 as_bad ("Invalid record type for P3 format.");
1281 bytes
[0] = (UNW_P3
| (r
>> 1));
1282 bytes
[1] = (((r
& 1) << 7) | reg
);
1283 (*f
) (2, bytes
, NULL
);
1287 output_P4_format (f
, imask
, imask_size
)
1289 unsigned char *imask
;
1290 unsigned long imask_size
;
1293 (*f
) (imask_size
, imask
, NULL
);
1297 output_P5_format (f
, grmask
, frmask
)
1300 unsigned long frmask
;
1303 grmask
= (grmask
& 0x0f);
1306 bytes
[1] = ((grmask
<< 4) | ((frmask
& 0x000f0000) >> 16));
1307 bytes
[2] = ((frmask
& 0x0000ff00) >> 8);
1308 bytes
[3] = (frmask
& 0x000000ff);
1309 (*f
) (4, bytes
, NULL
);
1313 output_P6_format (f
, rtype
, rmask
)
1315 unw_record_type rtype
;
1321 if (rtype
== gr_mem
)
1323 else if (rtype
!= fr_mem
)
1324 as_bad ("Invalid record type for format P6");
1325 byte
= (UNW_P6
| (r
<< 4) | (rmask
& 0x0f));
1326 (*f
) (1, &byte
, NULL
);
1330 output_P7_format (f
, rtype
, w1
, w2
)
1332 unw_record_type rtype
;
1339 count
+= output_leb128 (bytes
+ 1, w1
, 0);
1344 count
+= output_leb128 (bytes
+ count
, w2
>> 4, 0);
1394 bytes
[0] = (UNW_P7
| r
);
1395 (*f
) (count
, bytes
, NULL
);
1399 output_P8_format (f
, rtype
, t
)
1401 unw_record_type rtype
;
1440 case bspstore_psprel
:
1443 case bspstore_sprel
:
1455 case priunat_when_gr
:
1458 case priunat_psprel
:
1464 case priunat_when_mem
:
1471 count
+= output_leb128 (bytes
+ 2, t
, 0);
1472 (*f
) (count
, bytes
, NULL
);
1476 output_P9_format (f
, grmask
, gr
)
1483 bytes
[1] = (grmask
& 0x0f);
1484 bytes
[2] = (gr
& 0x7f);
1485 (*f
) (3, bytes
, NULL
);
1489 output_P10_format (f
, abi
, context
)
1496 bytes
[1] = (abi
& 0xff);
1497 bytes
[2] = (context
& 0xff);
1498 (*f
) (3, bytes
, NULL
);
1502 output_B1_format (f
, rtype
, label
)
1504 unw_record_type rtype
;
1505 unsigned long label
;
1511 output_B4_format (f
, rtype
, label
);
1514 if (rtype
== copy_state
)
1516 else if (rtype
!= label_state
)
1517 as_bad ("Invalid record type for format B1");
1519 byte
= (UNW_B1
| (r
<< 5) | (label
& 0x1f));
1520 (*f
) (1, &byte
, NULL
);
1524 output_B2_format (f
, ecount
, t
)
1526 unsigned long ecount
;
1533 output_B3_format (f
, ecount
, t
);
1536 bytes
[0] = (UNW_B2
| (ecount
& 0x1f));
1537 count
+= output_leb128 (bytes
+ 1, t
, 0);
1538 (*f
) (count
, bytes
, NULL
);
1542 output_B3_format (f
, ecount
, t
)
1544 unsigned long ecount
;
1551 output_B2_format (f
, ecount
, t
);
1555 count
+= output_leb128 (bytes
+ 1, t
, 0);
1556 count
+= output_leb128 (bytes
+ count
, ecount
, 0);
1557 (*f
) (count
, bytes
, NULL
);
1561 output_B4_format (f
, rtype
, label
)
1563 unw_record_type rtype
;
1564 unsigned long label
;
1571 output_B1_format (f
, rtype
, label
);
1575 if (rtype
== copy_state
)
1577 else if (rtype
!= label_state
)
1578 as_bad ("Invalid record type for format B1");
1580 bytes
[0] = (UNW_B4
| (r
<< 3));
1581 count
+= output_leb128 (bytes
+ 1, label
, 0);
1582 (*f
) (count
, bytes
, NULL
);
1586 format_ab_reg (ab
, reg
)
1593 ret
= (ab
<< 5) | reg
;
1598 output_X1_format (f
, rtype
, ab
, reg
, t
, w1
)
1600 unw_record_type rtype
;
1610 if (rtype
== spill_sprel
)
1612 else if (rtype
!= spill_psprel
)
1613 as_bad ("Invalid record type for format X1");
1614 bytes
[1] = ((r
<< 7) | format_ab_reg (ab
, reg
));
1615 count
+= output_leb128 (bytes
+ 2, t
, 0);
1616 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1617 (*f
) (count
, bytes
, NULL
);
1621 output_X2_format (f
, ab
, reg
, x
, y
, treg
, t
)
1630 bytes
[1] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1631 bytes
[2] = (((y
& 1) << 7) | (treg
& 0x7f));
1632 count
+= output_leb128 (bytes
+ 3, t
, 0);
1633 (*f
) (count
, bytes
, NULL
);
1637 output_X3_format (f
, rtype
, qp
, ab
, reg
, t
, w1
)
1639 unw_record_type rtype
;
1650 if (rtype
== spill_sprel_p
)
1652 else if (rtype
!= spill_psprel_p
)
1653 as_bad ("Invalid record type for format X3");
1654 bytes
[1] = ((r
<< 7) | (qp
& 0x3f));
1655 bytes
[2] = format_ab_reg (ab
, reg
);
1656 count
+= output_leb128 (bytes
+ 3, t
, 0);
1657 count
+= output_leb128 (bytes
+ count
, w1
, 0);
1658 (*f
) (count
, bytes
, NULL
);
1662 output_X4_format (f
, qp
, ab
, reg
, x
, y
, treg
, t
)
1672 bytes
[1] = (qp
& 0x3f);
1673 bytes
[2] = (((x
& 1) << 7) | format_ab_reg (ab
, reg
));
1674 bytes
[3] = (((y
& 1) << 7) | (treg
& 0x7f));
1675 count
+= output_leb128 (bytes
+ 4, t
, 0);
1676 (*f
) (count
, bytes
, NULL
);
1679 /* This function allocates a record list structure, and initializes fields. */
1681 static unw_rec_list
*
1682 alloc_record (unw_record_type t
)
1685 ptr
= xmalloc (sizeof (*ptr
));
1687 ptr
->slot_number
= SLOT_NUM_NOT_SET
;
1692 /* This function frees an entire list of record structures. */
1695 free_list_records (unw_rec_list
*first
)
1698 for (ptr
= first
; ptr
!= NULL
;)
1700 unw_rec_list
*tmp
= ptr
;
1702 if ((tmp
->r
.type
== prologue
|| tmp
->r
.type
== prologue_gr
)
1703 && tmp
->r
.record
.r
.mask
.i
)
1704 free (tmp
->r
.record
.r
.mask
.i
);
1711 static unw_rec_list
*
1714 unw_rec_list
*ptr
= alloc_record (prologue
);
1715 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1719 static unw_rec_list
*
1720 output_prologue_gr (saved_mask
, reg
)
1721 unsigned int saved_mask
;
1724 unw_rec_list
*ptr
= alloc_record (prologue_gr
);
1725 memset (&ptr
->r
.record
.r
.mask
, 0, sizeof (ptr
->r
.record
.r
.mask
));
1726 ptr
->r
.record
.r
.grmask
= saved_mask
;
1727 ptr
->r
.record
.r
.grsave
= reg
;
1731 static unw_rec_list
*
1734 unw_rec_list
*ptr
= alloc_record (body
);
1738 static unw_rec_list
*
1739 output_mem_stack_f (size
)
1742 unw_rec_list
*ptr
= alloc_record (mem_stack_f
);
1743 ptr
->r
.record
.p
.size
= size
;
1747 static unw_rec_list
*
1748 output_mem_stack_v ()
1750 unw_rec_list
*ptr
= alloc_record (mem_stack_v
);
1754 static unw_rec_list
*
1758 unw_rec_list
*ptr
= alloc_record (psp_gr
);
1759 ptr
->r
.record
.p
.gr
= gr
;
1763 static unw_rec_list
*
1764 output_psp_sprel (offset
)
1765 unsigned int offset
;
1767 unw_rec_list
*ptr
= alloc_record (psp_sprel
);
1768 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1772 static unw_rec_list
*
1775 unw_rec_list
*ptr
= alloc_record (rp_when
);
1779 static unw_rec_list
*
1783 unw_rec_list
*ptr
= alloc_record (rp_gr
);
1784 ptr
->r
.record
.p
.gr
= gr
;
1788 static unw_rec_list
*
1792 unw_rec_list
*ptr
= alloc_record (rp_br
);
1793 ptr
->r
.record
.p
.br
= br
;
1797 static unw_rec_list
*
1798 output_rp_psprel (offset
)
1799 unsigned int offset
;
1801 unw_rec_list
*ptr
= alloc_record (rp_psprel
);
1802 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1806 static unw_rec_list
*
1807 output_rp_sprel (offset
)
1808 unsigned int offset
;
1810 unw_rec_list
*ptr
= alloc_record (rp_sprel
);
1811 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1815 static unw_rec_list
*
1818 unw_rec_list
*ptr
= alloc_record (pfs_when
);
1822 static unw_rec_list
*
1826 unw_rec_list
*ptr
= alloc_record (pfs_gr
);
1827 ptr
->r
.record
.p
.gr
= gr
;
1831 static unw_rec_list
*
1832 output_pfs_psprel (offset
)
1833 unsigned int offset
;
1835 unw_rec_list
*ptr
= alloc_record (pfs_psprel
);
1836 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1840 static unw_rec_list
*
1841 output_pfs_sprel (offset
)
1842 unsigned int offset
;
1844 unw_rec_list
*ptr
= alloc_record (pfs_sprel
);
1845 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1849 static unw_rec_list
*
1850 output_preds_when ()
1852 unw_rec_list
*ptr
= alloc_record (preds_when
);
1856 static unw_rec_list
*
1857 output_preds_gr (gr
)
1860 unw_rec_list
*ptr
= alloc_record (preds_gr
);
1861 ptr
->r
.record
.p
.gr
= gr
;
1865 static unw_rec_list
*
1866 output_preds_psprel (offset
)
1867 unsigned int offset
;
1869 unw_rec_list
*ptr
= alloc_record (preds_psprel
);
1870 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1874 static unw_rec_list
*
1875 output_preds_sprel (offset
)
1876 unsigned int offset
;
1878 unw_rec_list
*ptr
= alloc_record (preds_sprel
);
1879 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1883 static unw_rec_list
*
1884 output_fr_mem (mask
)
1887 unw_rec_list
*ptr
= alloc_record (fr_mem
);
1888 ptr
->r
.record
.p
.rmask
= mask
;
1892 static unw_rec_list
*
1893 output_frgr_mem (gr_mask
, fr_mask
)
1894 unsigned int gr_mask
;
1895 unsigned int fr_mask
;
1897 unw_rec_list
*ptr
= alloc_record (frgr_mem
);
1898 ptr
->r
.record
.p
.grmask
= gr_mask
;
1899 ptr
->r
.record
.p
.frmask
= fr_mask
;
1903 static unw_rec_list
*
1904 output_gr_gr (mask
, reg
)
1908 unw_rec_list
*ptr
= alloc_record (gr_gr
);
1909 ptr
->r
.record
.p
.grmask
= mask
;
1910 ptr
->r
.record
.p
.gr
= reg
;
1914 static unw_rec_list
*
1915 output_gr_mem (mask
)
1918 unw_rec_list
*ptr
= alloc_record (gr_mem
);
1919 ptr
->r
.record
.p
.rmask
= mask
;
1923 static unw_rec_list
*
1924 output_br_mem (unsigned int mask
)
1926 unw_rec_list
*ptr
= alloc_record (br_mem
);
1927 ptr
->r
.record
.p
.brmask
= mask
;
1931 static unw_rec_list
*
1932 output_br_gr (save_mask
, reg
)
1933 unsigned int save_mask
;
1936 unw_rec_list
*ptr
= alloc_record (br_gr
);
1937 ptr
->r
.record
.p
.brmask
= save_mask
;
1938 ptr
->r
.record
.p
.gr
= reg
;
1942 static unw_rec_list
*
1943 output_spill_base (offset
)
1944 unsigned int offset
;
1946 unw_rec_list
*ptr
= alloc_record (spill_base
);
1947 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1951 static unw_rec_list
*
1954 unw_rec_list
*ptr
= alloc_record (unat_when
);
1958 static unw_rec_list
*
1962 unw_rec_list
*ptr
= alloc_record (unat_gr
);
1963 ptr
->r
.record
.p
.gr
= gr
;
1967 static unw_rec_list
*
1968 output_unat_psprel (offset
)
1969 unsigned int offset
;
1971 unw_rec_list
*ptr
= alloc_record (unat_psprel
);
1972 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
1976 static unw_rec_list
*
1977 output_unat_sprel (offset
)
1978 unsigned int offset
;
1980 unw_rec_list
*ptr
= alloc_record (unat_sprel
);
1981 ptr
->r
.record
.p
.spoff
= offset
/ 4;
1985 static unw_rec_list
*
1988 unw_rec_list
*ptr
= alloc_record (lc_when
);
1992 static unw_rec_list
*
1996 unw_rec_list
*ptr
= alloc_record (lc_gr
);
1997 ptr
->r
.record
.p
.gr
= gr
;
2001 static unw_rec_list
*
2002 output_lc_psprel (offset
)
2003 unsigned int offset
;
2005 unw_rec_list
*ptr
= alloc_record (lc_psprel
);
2006 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2010 static unw_rec_list
*
2011 output_lc_sprel (offset
)
2012 unsigned int offset
;
2014 unw_rec_list
*ptr
= alloc_record (lc_sprel
);
2015 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2019 static unw_rec_list
*
2022 unw_rec_list
*ptr
= alloc_record (fpsr_when
);
2026 static unw_rec_list
*
2030 unw_rec_list
*ptr
= alloc_record (fpsr_gr
);
2031 ptr
->r
.record
.p
.gr
= gr
;
2035 static unw_rec_list
*
2036 output_fpsr_psprel (offset
)
2037 unsigned int offset
;
2039 unw_rec_list
*ptr
= alloc_record (fpsr_psprel
);
2040 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2044 static unw_rec_list
*
2045 output_fpsr_sprel (offset
)
2046 unsigned int offset
;
2048 unw_rec_list
*ptr
= alloc_record (fpsr_sprel
);
2049 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2053 static unw_rec_list
*
2054 output_priunat_when_gr ()
2056 unw_rec_list
*ptr
= alloc_record (priunat_when_gr
);
2060 static unw_rec_list
*
2061 output_priunat_when_mem ()
2063 unw_rec_list
*ptr
= alloc_record (priunat_when_mem
);
2067 static unw_rec_list
*
2068 output_priunat_gr (gr
)
2071 unw_rec_list
*ptr
= alloc_record (priunat_gr
);
2072 ptr
->r
.record
.p
.gr
= gr
;
2076 static unw_rec_list
*
2077 output_priunat_psprel (offset
)
2078 unsigned int offset
;
2080 unw_rec_list
*ptr
= alloc_record (priunat_psprel
);
2081 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2085 static unw_rec_list
*
2086 output_priunat_sprel (offset
)
2087 unsigned int offset
;
2089 unw_rec_list
*ptr
= alloc_record (priunat_sprel
);
2090 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2094 static unw_rec_list
*
2097 unw_rec_list
*ptr
= alloc_record (bsp_when
);
2101 static unw_rec_list
*
2105 unw_rec_list
*ptr
= alloc_record (bsp_gr
);
2106 ptr
->r
.record
.p
.gr
= gr
;
2110 static unw_rec_list
*
2111 output_bsp_psprel (offset
)
2112 unsigned int offset
;
2114 unw_rec_list
*ptr
= alloc_record (bsp_psprel
);
2115 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2119 static unw_rec_list
*
2120 output_bsp_sprel (offset
)
2121 unsigned int offset
;
2123 unw_rec_list
*ptr
= alloc_record (bsp_sprel
);
2124 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2128 static unw_rec_list
*
2129 output_bspstore_when ()
2131 unw_rec_list
*ptr
= alloc_record (bspstore_when
);
2135 static unw_rec_list
*
2136 output_bspstore_gr (gr
)
2139 unw_rec_list
*ptr
= alloc_record (bspstore_gr
);
2140 ptr
->r
.record
.p
.gr
= gr
;
2144 static unw_rec_list
*
2145 output_bspstore_psprel (offset
)
2146 unsigned int offset
;
2148 unw_rec_list
*ptr
= alloc_record (bspstore_psprel
);
2149 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2153 static unw_rec_list
*
2154 output_bspstore_sprel (offset
)
2155 unsigned int offset
;
2157 unw_rec_list
*ptr
= alloc_record (bspstore_sprel
);
2158 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2162 static unw_rec_list
*
2165 unw_rec_list
*ptr
= alloc_record (rnat_when
);
2169 static unw_rec_list
*
2173 unw_rec_list
*ptr
= alloc_record (rnat_gr
);
2174 ptr
->r
.record
.p
.gr
= gr
;
2178 static unw_rec_list
*
2179 output_rnat_psprel (offset
)
2180 unsigned int offset
;
2182 unw_rec_list
*ptr
= alloc_record (rnat_psprel
);
2183 ptr
->r
.record
.p
.pspoff
= offset
/ 4;
2187 static unw_rec_list
*
2188 output_rnat_sprel (offset
)
2189 unsigned int offset
;
2191 unw_rec_list
*ptr
= alloc_record (rnat_sprel
);
2192 ptr
->r
.record
.p
.spoff
= offset
/ 4;
2196 static unw_rec_list
*
2197 output_unwabi (abi
, context
)
2199 unsigned long context
;
2201 unw_rec_list
*ptr
= alloc_record (unwabi
);
2202 ptr
->r
.record
.p
.abi
= abi
;
2203 ptr
->r
.record
.p
.context
= context
;
2207 static unw_rec_list
*
2208 output_epilogue (unsigned long ecount
)
2210 unw_rec_list
*ptr
= alloc_record (epilogue
);
2211 ptr
->r
.record
.b
.ecount
= ecount
;
2215 static unw_rec_list
*
2216 output_label_state (unsigned long label
)
2218 unw_rec_list
*ptr
= alloc_record (label_state
);
2219 ptr
->r
.record
.b
.label
= label
;
2223 static unw_rec_list
*
2224 output_copy_state (unsigned long label
)
2226 unw_rec_list
*ptr
= alloc_record (copy_state
);
2227 ptr
->r
.record
.b
.label
= label
;
2231 static unw_rec_list
*
2232 output_spill_psprel (ab
, reg
, offset
)
2235 unsigned int offset
;
2237 unw_rec_list
*ptr
= alloc_record (spill_psprel
);
2238 ptr
->r
.record
.x
.ab
= ab
;
2239 ptr
->r
.record
.x
.reg
= reg
;
2240 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2244 static unw_rec_list
*
2245 output_spill_sprel (ab
, reg
, offset
)
2248 unsigned int offset
;
2250 unw_rec_list
*ptr
= alloc_record (spill_sprel
);
2251 ptr
->r
.record
.x
.ab
= ab
;
2252 ptr
->r
.record
.x
.reg
= reg
;
2253 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2257 static unw_rec_list
*
2258 output_spill_psprel_p (ab
, reg
, offset
, predicate
)
2261 unsigned int offset
;
2262 unsigned int predicate
;
2264 unw_rec_list
*ptr
= alloc_record (spill_psprel_p
);
2265 ptr
->r
.record
.x
.ab
= ab
;
2266 ptr
->r
.record
.x
.reg
= reg
;
2267 ptr
->r
.record
.x
.pspoff
= offset
/ 4;
2268 ptr
->r
.record
.x
.qp
= predicate
;
2272 static unw_rec_list
*
2273 output_spill_sprel_p (ab
, reg
, offset
, predicate
)
2276 unsigned int offset
;
2277 unsigned int predicate
;
2279 unw_rec_list
*ptr
= alloc_record (spill_sprel_p
);
2280 ptr
->r
.record
.x
.ab
= ab
;
2281 ptr
->r
.record
.x
.reg
= reg
;
2282 ptr
->r
.record
.x
.spoff
= offset
/ 4;
2283 ptr
->r
.record
.x
.qp
= predicate
;
2287 static unw_rec_list
*
2288 output_spill_reg (ab
, reg
, targ_reg
, xy
)
2291 unsigned int targ_reg
;
2294 unw_rec_list
*ptr
= alloc_record (spill_reg
);
2295 ptr
->r
.record
.x
.ab
= ab
;
2296 ptr
->r
.record
.x
.reg
= reg
;
2297 ptr
->r
.record
.x
.treg
= targ_reg
;
2298 ptr
->r
.record
.x
.xy
= xy
;
2302 static unw_rec_list
*
2303 output_spill_reg_p (ab
, reg
, targ_reg
, xy
, predicate
)
2306 unsigned int targ_reg
;
2308 unsigned int predicate
;
2310 unw_rec_list
*ptr
= alloc_record (spill_reg_p
);
2311 ptr
->r
.record
.x
.ab
= ab
;
2312 ptr
->r
.record
.x
.reg
= reg
;
2313 ptr
->r
.record
.x
.treg
= targ_reg
;
2314 ptr
->r
.record
.x
.xy
= xy
;
2315 ptr
->r
.record
.x
.qp
= predicate
;
2319 /* Given a unw_rec_list process the correct format with the
2320 specified function. */
2323 process_one_record (ptr
, f
)
2327 unsigned long fr_mask
, gr_mask
;
2329 switch (ptr
->r
.type
)
2335 /* These are taken care of by prologue/prologue_gr. */
2340 if (ptr
->r
.type
== prologue_gr
)
2341 output_R2_format (f
, ptr
->r
.record
.r
.grmask
,
2342 ptr
->r
.record
.r
.grsave
, ptr
->r
.record
.r
.rlen
);
2344 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2346 /* Output descriptor(s) for union of register spills (if any). */
2347 gr_mask
= ptr
->r
.record
.r
.mask
.gr_mem
;
2348 fr_mask
= ptr
->r
.record
.r
.mask
.fr_mem
;
2351 if ((fr_mask
& ~0xfUL
) == 0)
2352 output_P6_format (f
, fr_mem
, fr_mask
);
2355 output_P5_format (f
, gr_mask
, fr_mask
);
2360 output_P6_format (f
, gr_mem
, gr_mask
);
2361 if (ptr
->r
.record
.r
.mask
.br_mem
)
2362 output_P1_format (f
, ptr
->r
.record
.r
.mask
.br_mem
);
2364 /* output imask descriptor if necessary: */
2365 if (ptr
->r
.record
.r
.mask
.i
)
2366 output_P4_format (f
, ptr
->r
.record
.r
.mask
.i
,
2367 ptr
->r
.record
.r
.imask_size
);
2371 output_R1_format (f
, ptr
->r
.type
, ptr
->r
.record
.r
.rlen
);
2375 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
,
2376 ptr
->r
.record
.p
.size
);
2389 output_P3_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.gr
);
2392 output_P3_format (f
, rp_br
, ptr
->r
.record
.p
.br
);
2395 output_P7_format (f
, psp_sprel
, ptr
->r
.record
.p
.spoff
, 0);
2403 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
, 0);
2412 output_P7_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
, 0);
2422 case bspstore_sprel
:
2424 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.spoff
);
2427 output_P9_format (f
, ptr
->r
.record
.p
.grmask
, ptr
->r
.record
.p
.gr
);
2430 output_P2_format (f
, ptr
->r
.record
.p
.brmask
, ptr
->r
.record
.p
.gr
);
2433 as_bad ("spill_mask record unimplemented.");
2435 case priunat_when_gr
:
2436 case priunat_when_mem
:
2440 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.t
);
2442 case priunat_psprel
:
2444 case bspstore_psprel
:
2446 output_P8_format (f
, ptr
->r
.type
, ptr
->r
.record
.p
.pspoff
);
2449 output_P10_format (f
, ptr
->r
.record
.p
.abi
, ptr
->r
.record
.p
.context
);
2452 output_B3_format (f
, ptr
->r
.record
.b
.ecount
, ptr
->r
.record
.b
.t
);
2456 output_B4_format (f
, ptr
->r
.type
, ptr
->r
.record
.b
.label
);
2459 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2460 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2461 ptr
->r
.record
.x
.pspoff
);
2464 output_X1_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.ab
,
2465 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.t
,
2466 ptr
->r
.record
.x
.spoff
);
2469 output_X2_format (f
, ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2470 ptr
->r
.record
.x
.xy
>> 1, ptr
->r
.record
.x
.xy
,
2471 ptr
->r
.record
.x
.treg
, ptr
->r
.record
.x
.t
);
2473 case spill_psprel_p
:
2474 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2475 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2476 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.pspoff
);
2479 output_X3_format (f
, ptr
->r
.type
, ptr
->r
.record
.x
.qp
,
2480 ptr
->r
.record
.x
.ab
, ptr
->r
.record
.x
.reg
,
2481 ptr
->r
.record
.x
.t
, ptr
->r
.record
.x
.spoff
);
2484 output_X4_format (f
, ptr
->r
.record
.x
.qp
, ptr
->r
.record
.x
.ab
,
2485 ptr
->r
.record
.x
.reg
, ptr
->r
.record
.x
.xy
>> 1,
2486 ptr
->r
.record
.x
.xy
, ptr
->r
.record
.x
.treg
,
2490 as_bad ("record_type_not_valid");
2495 /* Given a unw_rec_list list, process all the records with
2496 the specified function. */
2498 process_unw_records (list
, f
)
2503 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2504 process_one_record (ptr
, f
);
2507 /* Determine the size of a record list in bytes. */
2509 calc_record_size (list
)
2513 process_unw_records (list
, count_output
);
2517 /* Update IMASK bitmask to reflect the fact that one or more registers
2518 of type TYPE are saved starting at instruction with index T. If N
2519 bits are set in REGMASK, it is assumed that instructions T through
2520 T+N-1 save these registers.
2524 1: instruction saves next fp reg
2525 2: instruction saves next general reg
2526 3: instruction saves next branch reg */
2528 set_imask (region
, regmask
, t
, type
)
2529 unw_rec_list
*region
;
2530 unsigned long regmask
;
2534 unsigned char *imask
;
2535 unsigned long imask_size
;
2539 imask
= region
->r
.record
.r
.mask
.i
;
2540 imask_size
= region
->r
.record
.r
.imask_size
;
2543 imask_size
= (region
->r
.record
.r
.rlen
* 2 + 7) / 8 + 1;
2544 imask
= xmalloc (imask_size
);
2545 memset (imask
, 0, imask_size
);
2547 region
->r
.record
.r
.imask_size
= imask_size
;
2548 region
->r
.record
.r
.mask
.i
= imask
;
2552 pos
= 2 * (3 - t
% 4);
2555 if (i
>= imask_size
)
2557 as_bad ("Ignoring attempt to spill beyond end of region");
2561 imask
[i
] |= (type
& 0x3) << pos
;
2563 regmask
&= (regmask
- 1);
2574 count_bits (unsigned long mask
)
2586 /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR.
2587 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag
2588 containing FIRST_ADDR. */
2591 slot_index (slot_addr
, slot_frag
, first_addr
, first_frag
)
2592 unsigned long slot_addr
;
2594 unsigned long first_addr
;
2597 unsigned long index
= 0;
2599 /* First time we are called, the initial address and frag are invalid. */
2600 if (first_addr
== 0)
2603 /* If the two addresses are in different frags, then we need to add in
2604 the remaining size of this frag, and then the entire size of intermediate
2606 while (slot_frag
!= first_frag
)
2608 unsigned long start_addr
= (unsigned long) &first_frag
->fr_literal
;
2610 /* Add in the full size of the frag converted to instruction slots. */
2611 index
+= 3 * (first_frag
->fr_fix
>> 4);
2612 /* Subtract away the initial part before first_addr. */
2613 index
-= (3 * ((first_addr
>> 4) - (start_addr
>> 4))
2614 + ((first_addr
& 0x3) - (start_addr
& 0x3)));
2616 /* Move to the beginning of the next frag. */
2617 first_frag
= first_frag
->fr_next
;
2618 first_addr
= (unsigned long) &first_frag
->fr_literal
;
2621 /* Add in the used part of the last frag. */
2622 index
+= (3 * ((slot_addr
>> 4) - (first_addr
>> 4))
2623 + ((slot_addr
& 0x3) - (first_addr
& 0x3)));
2627 /* Optimize unwind record directives. */
2629 static unw_rec_list
*
2630 optimize_unw_records (list
)
2636 /* If the only unwind record is ".prologue" or ".prologue" followed
2637 by ".body", then we can optimize the unwind directives away. */
2638 if (list
->r
.type
== prologue
2639 && (list
->next
== NULL
2640 || (list
->next
->r
.type
== body
&& list
->next
->next
== NULL
)))
2646 /* Given a complete record list, process any records which have
2647 unresolved fields, (ie length counts for a prologue). After
2648 this has been run, all neccessary information should be available
2649 within each record to generate an image. */
2652 fixup_unw_records (list
)
2655 unw_rec_list
*ptr
, *region
= 0;
2656 unsigned long first_addr
= 0, rlen
= 0, t
;
2657 fragS
*first_frag
= 0;
2659 for (ptr
= list
; ptr
; ptr
= ptr
->next
)
2661 if (ptr
->slot_number
== SLOT_NUM_NOT_SET
)
2662 as_bad (" Insn slot not set in unwind record.");
2663 t
= slot_index (ptr
->slot_number
, ptr
->slot_frag
,
2664 first_addr
, first_frag
);
2665 switch (ptr
->r
.type
)
2672 int size
, dir_len
= 0;
2673 unsigned long last_addr
;
2676 first_addr
= ptr
->slot_number
;
2677 first_frag
= ptr
->slot_frag
;
2678 ptr
->slot_number
= 0;
2679 /* Find either the next body/prologue start, or the end of
2680 the list, and determine the size of the region. */
2681 last_addr
= unwind
.next_slot_number
;
2682 last_frag
= unwind
.next_slot_frag
;
2683 for (last
= ptr
->next
; last
!= NULL
; last
= last
->next
)
2684 if (last
->r
.type
== prologue
|| last
->r
.type
== prologue_gr
2685 || last
->r
.type
== body
)
2687 last_addr
= last
->slot_number
;
2688 last_frag
= last
->slot_frag
;
2691 else if (!last
->next
)
2693 /* In the absence of an explicit .body directive,
2694 the prologue ends after the last instruction
2695 covered by an unwind directive. */
2696 if (ptr
->r
.type
!= body
)
2698 last_addr
= last
->slot_number
;
2699 last_frag
= last
->slot_frag
;
2700 switch (last
->r
.type
)
2703 dir_len
= (count_bits (last
->r
.record
.p
.frmask
)
2704 + count_bits (last
->r
.record
.p
.grmask
));
2708 dir_len
+= count_bits (last
->r
.record
.p
.rmask
);
2712 dir_len
+= count_bits (last
->r
.record
.p
.brmask
);
2715 dir_len
+= count_bits (last
->r
.record
.p
.grmask
);
2724 size
= (slot_index (last_addr
, last_frag
, first_addr
, first_frag
)
2726 rlen
= ptr
->r
.record
.r
.rlen
= size
;
2727 if (ptr
->r
.type
== body
)
2728 /* End of region. */
2735 ptr
->r
.record
.b
.t
= rlen
- 1 - t
;
2746 case priunat_when_gr
:
2747 case priunat_when_mem
:
2751 ptr
->r
.record
.p
.t
= t
;
2759 case spill_psprel_p
:
2760 ptr
->r
.record
.x
.t
= t
;
2766 as_bad ("frgr_mem record before region record!\n");
2769 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.frmask
;
2770 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.grmask
;
2771 set_imask (region
, ptr
->r
.record
.p
.frmask
, t
, 1);
2772 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2777 as_bad ("fr_mem record before region record!\n");
2780 region
->r
.record
.r
.mask
.fr_mem
|= ptr
->r
.record
.p
.rmask
;
2781 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 1);
2786 as_bad ("gr_mem record before region record!\n");
2789 region
->r
.record
.r
.mask
.gr_mem
|= ptr
->r
.record
.p
.rmask
;
2790 set_imask (region
, ptr
->r
.record
.p
.rmask
, t
, 2);
2795 as_bad ("br_mem record before region record!\n");
2798 region
->r
.record
.r
.mask
.br_mem
|= ptr
->r
.record
.p
.brmask
;
2799 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2805 as_bad ("gr_gr record before region record!\n");
2808 set_imask (region
, ptr
->r
.record
.p
.grmask
, t
, 2);
2813 as_bad ("br_gr record before region record!\n");
2816 set_imask (region
, ptr
->r
.record
.p
.brmask
, t
, 3);
2825 /* Helper routine for output_unw_records. Emits the header for the unwind
2829 setup_unwind_header (int size
, unsigned char **mem
)
2834 /* pad to pointer-size boundry. */
2835 x
= size
% md
.pointer_size
;
2837 extra
= md
.pointer_size
- x
;
2839 /* Add 8 for the header + a pointer for the
2840 personality offset. */
2841 *mem
= xmalloc (size
+ extra
+ 8 + md
.pointer_size
);
2843 /* Clear the padding area and personality. */
2844 memset (*mem
+ 8 + size
, 0, extra
+ md
.pointer_size
);
2846 /* Initialize the header area. */
2847 if (unwind
.personality_routine
)
2849 if (md
.flags
& EF_IA_64_ABI64
)
2850 flag_value
= (bfd_vma
) 3 << 32;
2852 /* 32-bit unwind info block. */
2853 flag_value
= (bfd_vma
) 0x1003 << 32;
2858 md_number_to_chars (*mem
, (((bfd_vma
) 1 << 48) /* Version. */
2859 | flag_value
/* U & E handler flags. */
2860 | ((size
+ extra
) / md
.pointer_size
)), /* Length. */
2866 /* Generate an unwind image from a record list. Returns the number of
2867 bytes in the resulting image. The memory image itselof is returned
2868 in the 'ptr' parameter. */
2870 output_unw_records (list
, ptr
)
2879 list
= optimize_unw_records (list
);
2880 fixup_unw_records (list
);
2881 size
= calc_record_size (list
);
2883 if (size
> 0 || unwind
.force_unwind_entry
)
2885 unwind
.force_unwind_entry
= 0;
2886 extra
= setup_unwind_header (size
, &mem
);
2888 vbyte_mem_ptr
= mem
+ 8;
2889 process_unw_records (list
, output_vbyte_mem
);
2893 size
+= extra
+ 8 + md
.pointer_size
;
2899 convert_expr_to_ab_reg (e
, ab
, regp
)
2906 if (e
->X_op
!= O_register
)
2909 reg
= e
->X_add_number
;
2910 if (reg
>= (REG_GR
+ 4) && reg
<= (REG_GR
+ 7))
2913 *regp
= reg
- REG_GR
;
2915 else if ((reg
>= (REG_FR
+ 2) && reg
<= (REG_FR
+ 5))
2916 || (reg
>= (REG_FR
+ 16) && reg
<= (REG_FR
+ 31)))
2919 *regp
= reg
- REG_FR
;
2921 else if (reg
>= (REG_BR
+ 1) && reg
<= (REG_BR
+ 5))
2924 *regp
= reg
- REG_BR
;
2931 case REG_PR
: *regp
= 0; break;
2932 case REG_PSP
: *regp
= 1; break;
2933 case REG_PRIUNAT
: *regp
= 2; break;
2934 case REG_BR
+ 0: *regp
= 3; break;
2935 case REG_AR
+ AR_BSP
: *regp
= 4; break;
2936 case REG_AR
+ AR_BSPSTORE
: *regp
= 5; break;
2937 case REG_AR
+ AR_RNAT
: *regp
= 6; break;
2938 case REG_AR
+ AR_UNAT
: *regp
= 7; break;
2939 case REG_AR
+ AR_FPSR
: *regp
= 8; break;
2940 case REG_AR
+ AR_PFS
: *regp
= 9; break;
2941 case REG_AR
+ AR_LC
: *regp
= 10; break;
2951 convert_expr_to_xy_reg (e
, xy
, regp
)
2958 if (e
->X_op
!= O_register
)
2961 reg
= e
->X_add_number
;
2963 if (/* reg >= REG_GR && */ reg
<= (REG_GR
+ 127))
2966 *regp
= reg
- REG_GR
;
2968 else if (reg
>= REG_FR
&& reg
<= (REG_FR
+ 127))
2971 *regp
= reg
- REG_FR
;
2973 else if (reg
>= REG_BR
&& reg
<= (REG_BR
+ 7))
2976 *regp
= reg
- REG_BR
;
2985 int dummy ATTRIBUTE_UNUSED
;
2990 radix
= *input_line_pointer
++;
2992 if (radix
!= 'C' && !is_end_of_line
[(unsigned char) radix
])
2994 as_bad ("Radix `%c' unsupported", *input_line_pointer
);
2995 ignore_rest_of_line ();
3000 /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */
3002 dot_special_section (which
)
3005 set_section ((char *) special_section_name
[which
]);
3009 add_unwind_entry (ptr
)
3013 unwind
.tail
->next
= ptr
;
3018 /* The current entry can in fact be a chain of unwind entries. */
3019 if (unwind
.current_entry
== NULL
)
3020 unwind
.current_entry
= ptr
;
3025 int dummy ATTRIBUTE_UNUSED
;
3031 if (e
.X_op
!= O_constant
)
3032 as_bad ("Operand to .fframe must be a constant");
3034 add_unwind_entry (output_mem_stack_f (e
.X_add_number
));
3039 int dummy ATTRIBUTE_UNUSED
;
3045 reg
= e
.X_add_number
- REG_GR
;
3046 if (e
.X_op
== O_register
&& reg
< 128)
3048 add_unwind_entry (output_mem_stack_v ());
3049 if (! (unwind
.prologue_mask
& 2))
3050 add_unwind_entry (output_psp_gr (reg
));
3053 as_bad ("First operand to .vframe must be a general register");
3057 dot_vframesp (dummy
)
3058 int dummy ATTRIBUTE_UNUSED
;
3063 if (e
.X_op
== O_constant
)
3065 add_unwind_entry (output_mem_stack_v ());
3066 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3069 as_bad ("First operand to .vframesp must be a general register");
3073 dot_vframepsp (dummy
)
3074 int dummy ATTRIBUTE_UNUSED
;
3079 if (e
.X_op
== O_constant
)
3081 add_unwind_entry (output_mem_stack_v ());
3082 add_unwind_entry (output_psp_sprel (e
.X_add_number
));
3085 as_bad ("First operand to .vframepsp must be a general register");
3090 int dummy ATTRIBUTE_UNUSED
;
3096 sep
= parse_operand (&e1
);
3098 as_bad ("No second operand to .save");
3099 sep
= parse_operand (&e2
);
3101 reg1
= e1
.X_add_number
;
3102 reg2
= e2
.X_add_number
- REG_GR
;
3104 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3105 if (e1
.X_op
== O_register
)
3107 if (e2
.X_op
== O_register
&& reg2
>= 0 && reg2
< 128)
3111 case REG_AR
+ AR_BSP
:
3112 add_unwind_entry (output_bsp_when ());
3113 add_unwind_entry (output_bsp_gr (reg2
));
3115 case REG_AR
+ AR_BSPSTORE
:
3116 add_unwind_entry (output_bspstore_when ());
3117 add_unwind_entry (output_bspstore_gr (reg2
));
3119 case REG_AR
+ AR_RNAT
:
3120 add_unwind_entry (output_rnat_when ());
3121 add_unwind_entry (output_rnat_gr (reg2
));
3123 case REG_AR
+ AR_UNAT
:
3124 add_unwind_entry (output_unat_when ());
3125 add_unwind_entry (output_unat_gr (reg2
));
3127 case REG_AR
+ AR_FPSR
:
3128 add_unwind_entry (output_fpsr_when ());
3129 add_unwind_entry (output_fpsr_gr (reg2
));
3131 case REG_AR
+ AR_PFS
:
3132 add_unwind_entry (output_pfs_when ());
3133 if (! (unwind
.prologue_mask
& 4))
3134 add_unwind_entry (output_pfs_gr (reg2
));
3136 case REG_AR
+ AR_LC
:
3137 add_unwind_entry (output_lc_when ());
3138 add_unwind_entry (output_lc_gr (reg2
));
3141 add_unwind_entry (output_rp_when ());
3142 if (! (unwind
.prologue_mask
& 8))
3143 add_unwind_entry (output_rp_gr (reg2
));
3146 add_unwind_entry (output_preds_when ());
3147 if (! (unwind
.prologue_mask
& 1))
3148 add_unwind_entry (output_preds_gr (reg2
));
3151 add_unwind_entry (output_priunat_when_gr ());
3152 add_unwind_entry (output_priunat_gr (reg2
));
3155 as_bad ("First operand not a valid register");
3159 as_bad (" Second operand not a valid register");
3162 as_bad ("First operand not a register");
3167 int dummy ATTRIBUTE_UNUSED
;
3170 unsigned long ecount
; /* # of _additional_ regions to pop */
3173 sep
= parse_operand (&e1
);
3174 if (e1
.X_op
!= O_register
|| e1
.X_add_number
!= REG_GR
+ 12)
3176 as_bad ("First operand to .restore must be stack pointer (sp)");
3182 parse_operand (&e2
);
3183 if (e2
.X_op
!= O_constant
|| e2
.X_add_number
< 0)
3185 as_bad ("Second operand to .restore must be a constant >= 0");
3188 ecount
= e2
.X_add_number
;
3191 ecount
= unwind
.prologue_count
- 1;
3193 if (ecount
>= unwind
.prologue_count
)
3195 as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)",
3196 ecount
+ 1, unwind
.prologue_count
);
3200 add_unwind_entry (output_epilogue (ecount
));
3202 if (ecount
< unwind
.prologue_count
)
3203 unwind
.prologue_count
-= ecount
+ 1;
3205 unwind
.prologue_count
= 0;
3209 dot_restorereg (dummy
)
3210 int dummy ATTRIBUTE_UNUSED
;
3212 unsigned int ab
, reg
;
3217 if (!convert_expr_to_ab_reg (&e
, &ab
, ®
))
3219 as_bad ("First operand to .restorereg must be a preserved register");
3222 add_unwind_entry (output_spill_reg (ab
, reg
, 0, 0));
3226 dot_restorereg_p (dummy
)
3227 int dummy ATTRIBUTE_UNUSED
;
3229 unsigned int qp
, ab
, reg
;
3233 sep
= parse_operand (&e1
);
3236 as_bad ("No second operand to .restorereg.p");
3240 parse_operand (&e2
);
3242 qp
= e1
.X_add_number
- REG_P
;
3243 if (e1
.X_op
!= O_register
|| qp
> 63)
3245 as_bad ("First operand to .restorereg.p must be a predicate");
3249 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3251 as_bad ("Second operand to .restorereg.p must be a preserved register");
3254 add_unwind_entry (output_spill_reg_p (ab
, reg
, 0, 0, qp
));
3258 generate_unwind_image (text_name
)
3259 const char *text_name
;
3262 unsigned char *unw_rec
;
3264 /* Force out pending instructions, to make sure all unwind records have
3265 a valid slot_number field. */
3266 ia64_flush_insns ();
3268 /* Generate the unwind record. */
3269 size
= output_unw_records (unwind
.list
, (void **) &unw_rec
);
3270 if (size
% md
.pointer_size
!= 0)
3271 as_bad ("Unwind record is not a multiple of %d bytes.", md
.pointer_size
);
3273 /* If there are unwind records, switch sections, and output the info. */
3276 unsigned char *where
;
3279 bfd_reloc_code_real_type reloc
;
3281 make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO
, text_name
, sec_name
);
3282 set_section (sec_name
);
3283 bfd_set_section_flags (stdoutput
, now_seg
,
3284 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
3286 /* Make sure the section has 4 byte alignment for ILP32 and
3287 8 byte alignment for LP64. */
3288 frag_align (md
.pointer_size_shift
, 0, 0);
3289 record_alignment (now_seg
, md
.pointer_size_shift
);
3291 /* Set expression which points to start of unwind descriptor area. */
3292 unwind
.info
= expr_build_dot ();
3294 where
= (unsigned char *) frag_more (size
);
3296 /* Issue a label for this address, and keep track of it to put it
3297 in the unwind section. */
3299 /* Copy the information from the unwind record into this section. The
3300 data is already in the correct byte order. */
3301 memcpy (where
, unw_rec
, size
);
3303 /* Add the personality address to the image. */
3304 if (unwind
.personality_routine
!= 0)
3306 exp
.X_op
= O_symbol
;
3307 exp
.X_add_symbol
= unwind
.personality_routine
;
3308 exp
.X_add_number
= 0;
3310 if (md
.flags
& EF_IA_64_BE
)
3312 if (md
.flags
& EF_IA_64_ABI64
)
3313 reloc
= BFD_RELOC_IA64_LTOFF_FPTR64MSB
;
3315 reloc
= BFD_RELOC_IA64_LTOFF_FPTR32MSB
;
3319 if (md
.flags
& EF_IA_64_ABI64
)
3320 reloc
= BFD_RELOC_IA64_LTOFF_FPTR64LSB
;
3322 reloc
= BFD_RELOC_IA64_LTOFF_FPTR32LSB
;
3325 fix_new_exp (frag_now
, frag_now_fix () - md
.pointer_size
,
3326 md
.pointer_size
, &exp
, 0, reloc
);
3327 unwind
.personality_routine
= 0;
3331 free_list_records (unwind
.list
);
3332 free_saved_prologue_counts ();
3333 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3339 dot_handlerdata (dummy
)
3340 int dummy ATTRIBUTE_UNUSED
;
3342 const char *text_name
= segment_name (now_seg
);
3344 /* If text section name starts with ".text" (which it should),
3345 strip this prefix off. */
3346 if (strcmp (text_name
, ".text") == 0)
3349 unwind
.force_unwind_entry
= 1;
3351 /* Remember which segment we're in so we can switch back after .endp */
3352 unwind
.saved_text_seg
= now_seg
;
3353 unwind
.saved_text_subseg
= now_subseg
;
3355 /* Generate unwind info into unwind-info section and then leave that
3356 section as the currently active one so dataXX directives go into
3357 the language specific data area of the unwind info block. */
3358 generate_unwind_image (text_name
);
3359 demand_empty_rest_of_line ();
3363 dot_unwentry (dummy
)
3364 int dummy ATTRIBUTE_UNUSED
;
3366 unwind
.force_unwind_entry
= 1;
3367 demand_empty_rest_of_line ();
3372 int dummy ATTRIBUTE_UNUSED
;
3378 reg
= e
.X_add_number
- REG_BR
;
3379 if (e
.X_op
== O_register
&& reg
< 8)
3380 add_unwind_entry (output_rp_br (reg
));
3382 as_bad ("First operand not a valid branch register");
3386 dot_savemem (psprel
)
3393 sep
= parse_operand (&e1
);
3395 as_bad ("No second operand to .save%ssp", psprel
? "p" : "");
3396 sep
= parse_operand (&e2
);
3398 reg1
= e1
.X_add_number
;
3399 val
= e2
.X_add_number
;
3401 /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
3402 if (e1
.X_op
== O_register
)
3404 if (e2
.X_op
== O_constant
)
3408 case REG_AR
+ AR_BSP
:
3409 add_unwind_entry (output_bsp_when ());
3410 add_unwind_entry ((psprel
3412 : output_bsp_sprel
) (val
));
3414 case REG_AR
+ AR_BSPSTORE
:
3415 add_unwind_entry (output_bspstore_when ());
3416 add_unwind_entry ((psprel
3417 ? output_bspstore_psprel
3418 : output_bspstore_sprel
) (val
));
3420 case REG_AR
+ AR_RNAT
:
3421 add_unwind_entry (output_rnat_when ());
3422 add_unwind_entry ((psprel
3423 ? output_rnat_psprel
3424 : output_rnat_sprel
) (val
));
3426 case REG_AR
+ AR_UNAT
:
3427 add_unwind_entry (output_unat_when ());
3428 add_unwind_entry ((psprel
3429 ? output_unat_psprel
3430 : output_unat_sprel
) (val
));
3432 case REG_AR
+ AR_FPSR
:
3433 add_unwind_entry (output_fpsr_when ());
3434 add_unwind_entry ((psprel
3435 ? output_fpsr_psprel
3436 : output_fpsr_sprel
) (val
));
3438 case REG_AR
+ AR_PFS
:
3439 add_unwind_entry (output_pfs_when ());
3440 add_unwind_entry ((psprel
3442 : output_pfs_sprel
) (val
));
3444 case REG_AR
+ AR_LC
:
3445 add_unwind_entry (output_lc_when ());
3446 add_unwind_entry ((psprel
3448 : output_lc_sprel
) (val
));
3451 add_unwind_entry (output_rp_when ());
3452 add_unwind_entry ((psprel
3454 : output_rp_sprel
) (val
));
3457 add_unwind_entry (output_preds_when ());
3458 add_unwind_entry ((psprel
3459 ? output_preds_psprel
3460 : output_preds_sprel
) (val
));
3463 add_unwind_entry (output_priunat_when_mem ());
3464 add_unwind_entry ((psprel
3465 ? output_priunat_psprel
3466 : output_priunat_sprel
) (val
));
3469 as_bad ("First operand not a valid register");
3473 as_bad (" Second operand not a valid constant");
3476 as_bad ("First operand not a register");
3481 int dummy ATTRIBUTE_UNUSED
;
3485 sep
= parse_operand (&e1
);
3487 parse_operand (&e2
);
3489 if (e1
.X_op
!= O_constant
)
3490 as_bad ("First operand to .save.g must be a constant.");
3493 int grmask
= e1
.X_add_number
;
3495 add_unwind_entry (output_gr_mem (grmask
));
3498 int reg
= e2
.X_add_number
- REG_GR
;
3499 if (e2
.X_op
== O_register
&& reg
>= 0 && reg
< 128)
3500 add_unwind_entry (output_gr_gr (grmask
, reg
));
3502 as_bad ("Second operand is an invalid register.");
3509 int dummy ATTRIBUTE_UNUSED
;
3513 sep
= parse_operand (&e1
);
3515 if (e1
.X_op
!= O_constant
)
3516 as_bad ("Operand to .save.f must be a constant.");
3518 add_unwind_entry (output_fr_mem (e1
.X_add_number
));
3523 int dummy ATTRIBUTE_UNUSED
;
3530 sep
= parse_operand (&e1
);
3531 if (e1
.X_op
!= O_constant
)
3533 as_bad ("First operand to .save.b must be a constant.");
3536 brmask
= e1
.X_add_number
;
3540 sep
= parse_operand (&e2
);
3541 reg
= e2
.X_add_number
- REG_GR
;
3542 if (e2
.X_op
!= O_register
|| reg
> 127)
3544 as_bad ("Second operand to .save.b must be a general register.");
3547 add_unwind_entry (output_br_gr (brmask
, e2
.X_add_number
));
3550 add_unwind_entry (output_br_mem (brmask
));
3552 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3553 ignore_rest_of_line ();
3558 int dummy ATTRIBUTE_UNUSED
;
3562 sep
= parse_operand (&e1
);
3564 parse_operand (&e2
);
3566 if (e1
.X_op
!= O_constant
|| sep
!= ',' || e2
.X_op
!= O_constant
)
3567 as_bad ("Both operands of .save.gf must be constants.");
3570 int grmask
= e1
.X_add_number
;
3571 int frmask
= e2
.X_add_number
;
3572 add_unwind_entry (output_frgr_mem (grmask
, frmask
));
3578 int dummy ATTRIBUTE_UNUSED
;
3583 sep
= parse_operand (&e
);
3584 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3585 ignore_rest_of_line ();
3587 if (e
.X_op
!= O_constant
)
3588 as_bad ("Operand to .spill must be a constant");
3590 add_unwind_entry (output_spill_base (e
.X_add_number
));
3594 dot_spillreg (dummy
)
3595 int dummy ATTRIBUTE_UNUSED
;
3597 int sep
, ab
, xy
, reg
, treg
;
3600 sep
= parse_operand (&e1
);
3603 as_bad ("No second operand to .spillreg");
3607 parse_operand (&e2
);
3609 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3611 as_bad ("First operand to .spillreg must be a preserved register");
3615 if (!convert_expr_to_xy_reg (&e2
, &xy
, &treg
))
3617 as_bad ("Second operand to .spillreg must be a register");
3621 add_unwind_entry (output_spill_reg (ab
, reg
, treg
, xy
));
3625 dot_spillmem (psprel
)
3631 sep
= parse_operand (&e1
);
3634 as_bad ("Second operand missing");
3638 parse_operand (&e2
);
3640 if (!convert_expr_to_ab_reg (&e1
, &ab
, ®
))
3642 as_bad ("First operand to .spill%s must be a preserved register",
3643 psprel
? "psp" : "sp");
3647 if (e2
.X_op
!= O_constant
)
3649 as_bad ("Second operand to .spill%s must be a constant",
3650 psprel
? "psp" : "sp");
3655 add_unwind_entry (output_spill_psprel (ab
, reg
, e2
.X_add_number
));
3657 add_unwind_entry (output_spill_sprel (ab
, reg
, e2
.X_add_number
));
3661 dot_spillreg_p (dummy
)
3662 int dummy ATTRIBUTE_UNUSED
;
3664 int sep
, ab
, xy
, reg
, treg
;
3665 expressionS e1
, e2
, e3
;
3668 sep
= parse_operand (&e1
);
3671 as_bad ("No second and third operand to .spillreg.p");
3675 sep
= parse_operand (&e2
);
3678 as_bad ("No third operand to .spillreg.p");
3682 parse_operand (&e3
);
3684 qp
= e1
.X_add_number
- REG_P
;
3686 if (e1
.X_op
!= O_register
|| qp
> 63)
3688 as_bad ("First operand to .spillreg.p must be a predicate");
3692 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3694 as_bad ("Second operand to .spillreg.p must be a preserved register");
3698 if (!convert_expr_to_xy_reg (&e3
, &xy
, &treg
))
3700 as_bad ("Third operand to .spillreg.p must be a register");
3704 add_unwind_entry (output_spill_reg_p (ab
, reg
, treg
, xy
, qp
));
3708 dot_spillmem_p (psprel
)
3711 expressionS e1
, e2
, e3
;
3715 sep
= parse_operand (&e1
);
3718 as_bad ("Second operand missing");
3722 parse_operand (&e2
);
3725 as_bad ("Second operand missing");
3729 parse_operand (&e3
);
3731 qp
= e1
.X_add_number
- REG_P
;
3732 if (e1
.X_op
!= O_register
|| qp
> 63)
3734 as_bad ("First operand to .spill%s_p must be a predicate",
3735 psprel
? "psp" : "sp");
3739 if (!convert_expr_to_ab_reg (&e2
, &ab
, ®
))
3741 as_bad ("Second operand to .spill%s_p must be a preserved register",
3742 psprel
? "psp" : "sp");
3746 if (e3
.X_op
!= O_constant
)
3748 as_bad ("Third operand to .spill%s_p must be a constant",
3749 psprel
? "psp" : "sp");
3754 add_unwind_entry (output_spill_psprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3756 add_unwind_entry (output_spill_sprel_p (ab
, reg
, e3
.X_add_number
, qp
));
3760 get_saved_prologue_count (lbl
)
3763 label_prologue_count
*lpc
= unwind
.saved_prologue_counts
;
3765 while (lpc
!= NULL
&& lpc
->label_number
!= lbl
)
3769 return lpc
->prologue_count
;
3771 as_bad ("Missing .label_state %ld", lbl
);
3776 save_prologue_count (lbl
, count
)
3780 label_prologue_count
*lpc
= unwind
.saved_prologue_counts
;
3782 while (lpc
!= NULL
&& lpc
->label_number
!= lbl
)
3786 lpc
->prologue_count
= count
;
3789 label_prologue_count
*new_lpc
= xmalloc (sizeof (* new_lpc
));
3791 new_lpc
->next
= unwind
.saved_prologue_counts
;
3792 new_lpc
->label_number
= lbl
;
3793 new_lpc
->prologue_count
= count
;
3794 unwind
.saved_prologue_counts
= new_lpc
;
3799 free_saved_prologue_counts ()
3801 label_prologue_count
*lpc
= unwind
.saved_prologue_counts
;
3802 label_prologue_count
*next
;
3811 unwind
.saved_prologue_counts
= NULL
;
3815 dot_label_state (dummy
)
3816 int dummy ATTRIBUTE_UNUSED
;
3821 if (e
.X_op
!= O_constant
)
3823 as_bad ("Operand to .label_state must be a constant");
3826 add_unwind_entry (output_label_state (e
.X_add_number
));
3827 save_prologue_count (e
.X_add_number
, unwind
.prologue_count
);
3831 dot_copy_state (dummy
)
3832 int dummy ATTRIBUTE_UNUSED
;
3837 if (e
.X_op
!= O_constant
)
3839 as_bad ("Operand to .copy_state must be a constant");
3842 add_unwind_entry (output_copy_state (e
.X_add_number
));
3843 unwind
.prologue_count
= get_saved_prologue_count (e
.X_add_number
);
3848 int dummy ATTRIBUTE_UNUSED
;
3853 sep
= parse_operand (&e1
);
3856 as_bad ("Second operand to .unwabi missing");
3859 sep
= parse_operand (&e2
);
3860 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3861 ignore_rest_of_line ();
3863 if (e1
.X_op
!= O_constant
)
3865 as_bad ("First operand to .unwabi must be a constant");
3869 if (e2
.X_op
!= O_constant
)
3871 as_bad ("Second operand to .unwabi must be a constant");
3875 add_unwind_entry (output_unwabi (e1
.X_add_number
, e2
.X_add_number
));
3879 dot_personality (dummy
)
3880 int dummy ATTRIBUTE_UNUSED
;
3884 name
= input_line_pointer
;
3885 c
= get_symbol_end ();
3886 p
= input_line_pointer
;
3887 unwind
.personality_routine
= symbol_find_or_make (name
);
3888 unwind
.force_unwind_entry
= 1;
3891 demand_empty_rest_of_line ();
3896 int dummy ATTRIBUTE_UNUSED
;
3901 unwind
.proc_start
= expr_build_dot ();
3902 /* Parse names of main and alternate entry points and mark them as
3903 function symbols: */
3907 name
= input_line_pointer
;
3908 c
= get_symbol_end ();
3909 p
= input_line_pointer
;
3910 sym
= symbol_find_or_make (name
);
3911 if (unwind
.proc_start
== 0)
3913 unwind
.proc_start
= sym
;
3915 symbol_get_bfdsym (sym
)->flags
|= BSF_FUNCTION
;
3918 if (*input_line_pointer
!= ',')
3920 ++input_line_pointer
;
3922 demand_empty_rest_of_line ();
3925 unwind
.prologue_count
= 0;
3926 unwind
.list
= unwind
.tail
= unwind
.current_entry
= NULL
;
3927 unwind
.personality_routine
= 0;
3932 int dummy ATTRIBUTE_UNUSED
;
3934 unwind
.prologue
= 0;
3935 unwind
.prologue_mask
= 0;
3937 add_unwind_entry (output_body ());
3938 demand_empty_rest_of_line ();
3942 dot_prologue (dummy
)
3943 int dummy ATTRIBUTE_UNUSED
;
3946 int mask
= 0, grsave
= 0;
3948 if (!is_it_end_of_statement ())
3951 sep
= parse_operand (&e1
);
3953 as_bad ("No second operand to .prologue");
3954 sep
= parse_operand (&e2
);
3955 if (!is_end_of_line
[sep
] && !is_it_end_of_statement ())
3956 ignore_rest_of_line ();
3958 if (e1
.X_op
== O_constant
)
3960 mask
= e1
.X_add_number
;
3962 if (e2
.X_op
== O_constant
)
3963 grsave
= e2
.X_add_number
;
3964 else if (e2
.X_op
== O_register
3965 && (grsave
= e2
.X_add_number
- REG_GR
) < 128)
3968 as_bad ("Second operand not a constant or general register");
3970 add_unwind_entry (output_prologue_gr (mask
, grsave
));
3973 as_bad ("First operand not a constant");
3976 add_unwind_entry (output_prologue ());
3978 unwind
.prologue
= 1;
3979 unwind
.prologue_mask
= mask
;
3980 ++unwind
.prologue_count
;
3985 int dummy ATTRIBUTE_UNUSED
;
3989 int bytes_per_address
;
3992 subsegT saved_subseg
;
3993 const char *sec_name
, *text_name
;
3997 if (unwind
.saved_text_seg
)
3999 saved_seg
= unwind
.saved_text_seg
;
4000 saved_subseg
= unwind
.saved_text_subseg
;
4001 unwind
.saved_text_seg
= NULL
;
4005 saved_seg
= now_seg
;
4006 saved_subseg
= now_subseg
;
4010 Use a slightly ugly scheme to derive the unwind section names from
4011 the text section name:
4013 text sect. unwind table sect.
4014 name: name: comments:
4015 ---------- ----------------- --------------------------------
4017 .text.foo .IA_64.unwind.text.foo
4018 .foo .IA_64.unwind.foo
4020 .gnu.linkonce.ia64unw.foo
4021 _info .IA_64.unwind_info gas issues error message (ditto)
4022 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto)
4024 This mapping is done so that:
4026 (a) An object file with unwind info only in .text will use
4027 unwind section names .IA_64.unwind and .IA_64.unwind_info.
4028 This follows the letter of the ABI and also ensures backwards
4029 compatibility with older toolchains.
4031 (b) An object file with unwind info in multiple text sections
4032 will use separate unwind sections for each text section.
4033 This allows us to properly set the "sh_info" and "sh_link"
4034 fields in SHT_IA_64_UNWIND as required by the ABI and also
4035 lets GNU ld support programs with multiple segments
4036 containing unwind info (as might be the case for certain
4037 embedded applications).
4039 (c) An error is issued if there would be a name clash.
4041 text_name
= segment_name (saved_seg
);
4042 if (strncmp (text_name
, "_info", 5) == 0)
4044 as_bad ("Illegal section name `%s' (causes unwind section name clash)",
4046 ignore_rest_of_line ();
4049 if (strcmp (text_name
, ".text") == 0)
4052 insn_group_break (1, 0, 0);
4054 /* If there wasn't a .handlerdata, we haven't generated an image yet. */
4056 generate_unwind_image (text_name
);
4058 if (unwind
.info
|| unwind
.force_unwind_entry
)
4060 subseg_set (md
.last_text_seg
, 0);
4061 unwind
.proc_end
= expr_build_dot ();
4063 make_unw_section_name (SPECIAL_SECTION_UNWIND
, text_name
, sec_name
);
4064 set_section ((char *) sec_name
);
4065 bfd_set_section_flags (stdoutput
, now_seg
,
4066 SEC_LOAD
| SEC_ALLOC
| SEC_READONLY
);
4068 /* Make sure that section has 4 byte alignment for ILP32 and
4069 8 byte alignment for LP64. */
4070 record_alignment (now_seg
, md
.pointer_size_shift
);
4072 /* Need space for 3 pointers for procedure start, procedure end,
4074 ptr
= frag_more (3 * md
.pointer_size
);
4075 where
= frag_now_fix () - (3 * md
.pointer_size
);
4076 bytes_per_address
= bfd_arch_bits_per_address (stdoutput
) / 8;
4078 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */
4079 e
.X_op
= O_pseudo_fixup
;
4080 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4082 e
.X_add_symbol
= unwind
.proc_start
;
4083 ia64_cons_fix_new (frag_now
, where
, bytes_per_address
, &e
);
4085 e
.X_op
= O_pseudo_fixup
;
4086 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4088 e
.X_add_symbol
= unwind
.proc_end
;
4089 ia64_cons_fix_new (frag_now
, where
+ bytes_per_address
,
4090 bytes_per_address
, &e
);
4094 e
.X_op
= O_pseudo_fixup
;
4095 e
.X_op_symbol
= pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
;
4097 e
.X_add_symbol
= unwind
.info
;
4098 ia64_cons_fix_new (frag_now
, where
+ (bytes_per_address
* 2),
4099 bytes_per_address
, &e
);
4102 md_number_to_chars (ptr
+ (bytes_per_address
* 2), 0,
4106 subseg_set (saved_seg
, saved_subseg
);
4108 /* Parse names of main and alternate entry points and set symbol sizes. */
4112 name
= input_line_pointer
;
4113 c
= get_symbol_end ();
4114 p
= input_line_pointer
;
4115 sym
= symbol_find (name
);
4116 if (sym
&& unwind
.proc_start
4117 && (symbol_get_bfdsym (sym
)->flags
& BSF_FUNCTION
)
4118 && S_GET_SIZE (sym
) == 0 && symbol_get_obj (sym
)->size
== NULL
)
4120 fragS
*fr
= symbol_get_frag (unwind
.proc_start
);
4121 fragS
*frag
= symbol_get_frag (sym
);
4123 /* Check whether the function label is at or beyond last
4125 while (fr
&& fr
!= frag
)
4129 if (frag
== frag_now
&& SEG_NORMAL (now_seg
))
4130 S_SET_SIZE (sym
, frag_now_fix () - S_GET_VALUE (sym
));
4133 symbol_get_obj (sym
)->size
=
4134 (expressionS
*) xmalloc (sizeof (expressionS
));
4135 symbol_get_obj (sym
)->size
->X_op
= O_subtract
;
4136 symbol_get_obj (sym
)->size
->X_add_symbol
4137 = symbol_new (FAKE_LABEL_NAME
, now_seg
,
4138 frag_now_fix (), frag_now
);
4139 symbol_get_obj (sym
)->size
->X_op_symbol
= sym
;
4140 symbol_get_obj (sym
)->size
->X_add_number
= 0;
4146 if (*input_line_pointer
!= ',')
4148 ++input_line_pointer
;
4150 demand_empty_rest_of_line ();
4151 unwind
.proc_start
= unwind
.proc_end
= unwind
.info
= 0;
4155 dot_template (template)
4158 CURR_SLOT
.user_template
= template;
4163 int dummy ATTRIBUTE_UNUSED
;
4165 int ins
, locs
, outs
, rots
;
4167 if (is_it_end_of_statement ())
4168 ins
= locs
= outs
= rots
= 0;
4171 ins
= get_absolute_expression ();
4172 if (*input_line_pointer
++ != ',')
4174 locs
= get_absolute_expression ();
4175 if (*input_line_pointer
++ != ',')
4177 outs
= get_absolute_expression ();
4178 if (*input_line_pointer
++ != ',')
4180 rots
= get_absolute_expression ();
4182 set_regstack (ins
, locs
, outs
, rots
);
4186 as_bad ("Comma expected");
4187 ignore_rest_of_line ();
4194 unsigned num_regs
, num_alloced
= 0;
4195 struct dynreg
**drpp
, *dr
;
4196 int ch
, base_reg
= 0;
4202 case DYNREG_GR
: base_reg
= REG_GR
+ 32; break;
4203 case DYNREG_FR
: base_reg
= REG_FR
+ 32; break;
4204 case DYNREG_PR
: base_reg
= REG_P
+ 16; break;
4208 /* First, remove existing names from hash table. */
4209 for (dr
= md
.dynreg
[type
]; dr
&& dr
->num_regs
; dr
= dr
->next
)
4211 hash_delete (md
.dynreg_hash
, dr
->name
);
4215 drpp
= &md
.dynreg
[type
];
4218 start
= input_line_pointer
;
4219 ch
= get_symbol_end ();
4220 *input_line_pointer
= ch
;
4221 len
= (input_line_pointer
- start
);
4224 if (*input_line_pointer
!= '[')
4226 as_bad ("Expected '['");
4229 ++input_line_pointer
; /* skip '[' */
4231 num_regs
= get_absolute_expression ();
4233 if (*input_line_pointer
++ != ']')
4235 as_bad ("Expected ']'");
4240 num_alloced
+= num_regs
;
4244 if (num_alloced
> md
.rot
.num_regs
)
4246 as_bad ("Used more than the declared %d rotating registers",
4252 if (num_alloced
> 96)
4254 as_bad ("Used more than the available 96 rotating registers");
4259 if (num_alloced
> 48)
4261 as_bad ("Used more than the available 48 rotating registers");
4270 name
= obstack_alloc (¬es
, len
+ 1);
4271 memcpy (name
, start
, len
);
4276 *drpp
= obstack_alloc (¬es
, sizeof (*dr
));
4277 memset (*drpp
, 0, sizeof (*dr
));
4282 dr
->num_regs
= num_regs
;
4283 dr
->base
= base_reg
;
4285 base_reg
+= num_regs
;
4287 if (hash_insert (md
.dynreg_hash
, name
, dr
))
4289 as_bad ("Attempt to redefine register set `%s'", name
);
4293 if (*input_line_pointer
!= ',')
4295 ++input_line_pointer
; /* skip comma */
4298 demand_empty_rest_of_line ();
4302 ignore_rest_of_line ();
4306 dot_byteorder (byteorder
)
4309 target_big_endian
= byteorder
;
4314 int dummy ATTRIBUTE_UNUSED
;
4321 option
= input_line_pointer
;
4322 ch
= get_symbol_end ();
4323 if (strcmp (option
, "lsb") == 0)
4324 md
.flags
&= ~EF_IA_64_BE
;
4325 else if (strcmp (option
, "msb") == 0)
4326 md
.flags
|= EF_IA_64_BE
;
4327 else if (strcmp (option
, "abi32") == 0)
4328 md
.flags
&= ~EF_IA_64_ABI64
;
4329 else if (strcmp (option
, "abi64") == 0)
4330 md
.flags
|= EF_IA_64_ABI64
;
4332 as_bad ("Unknown psr option `%s'", option
);
4333 *input_line_pointer
= ch
;
4336 if (*input_line_pointer
!= ',')
4339 ++input_line_pointer
;
4342 demand_empty_rest_of_line ();
4347 int dummy ATTRIBUTE_UNUSED
;
4349 as_bad (".alias not implemented yet");
4354 int dummy ATTRIBUTE_UNUSED
;
4356 new_logical_line (0, get_absolute_expression ());
4357 demand_empty_rest_of_line ();
4361 parse_section_name ()
4367 if (*input_line_pointer
!= '"')
4369 as_bad ("Missing section name");
4370 ignore_rest_of_line ();
4373 name
= demand_copy_C_string (&len
);
4376 ignore_rest_of_line ();
4380 if (*input_line_pointer
!= ',')
4382 as_bad ("Comma expected after section name");
4383 ignore_rest_of_line ();
4386 ++input_line_pointer
; /* skip comma */
4394 char *name
= parse_section_name ();
4398 md
.keep_pending_output
= 1;
4401 obj_elf_previous (0);
4402 md
.keep_pending_output
= 0;
4405 /* Why doesn't float_cons() call md_cons_align() the way cons() does? */
4408 stmt_float_cons (kind
)
4415 case 'd': size
= 8; break;
4416 case 'x': size
= 10; break;
4423 ia64_do_align (size
);
4431 int saved_auto_align
= md
.auto_align
;
4435 md
.auto_align
= saved_auto_align
;
4439 dot_xfloat_cons (kind
)
4442 char *name
= parse_section_name ();
4446 md
.keep_pending_output
= 1;
4448 stmt_float_cons (kind
);
4449 obj_elf_previous (0);
4450 md
.keep_pending_output
= 0;
4454 dot_xstringer (zero
)
4457 char *name
= parse_section_name ();
4461 md
.keep_pending_output
= 1;
4464 obj_elf_previous (0);
4465 md
.keep_pending_output
= 0;
4472 int saved_auto_align
= md
.auto_align
;
4473 char *name
= parse_section_name ();
4477 md
.keep_pending_output
= 1;
4481 md
.auto_align
= saved_auto_align
;
4482 obj_elf_previous (0);
4483 md
.keep_pending_output
= 0;
4487 dot_xfloat_cons_ua (kind
)
4490 int saved_auto_align
= md
.auto_align
;
4491 char *name
= parse_section_name ();
4495 md
.keep_pending_output
= 1;
4498 stmt_float_cons (kind
);
4499 md
.auto_align
= saved_auto_align
;
4500 obj_elf_previous (0);
4501 md
.keep_pending_output
= 0;
4504 /* .reg.val <regname>,value */
4508 int dummy ATTRIBUTE_UNUSED
;
4513 if (reg
.X_op
!= O_register
)
4515 as_bad (_("Register name expected"));
4516 ignore_rest_of_line ();
4518 else if (*input_line_pointer
++ != ',')
4520 as_bad (_("Comma expected"));
4521 ignore_rest_of_line ();
4525 valueT value
= get_absolute_expression ();
4526 int regno
= reg
.X_add_number
;
4527 if (regno
< REG_GR
|| regno
> REG_GR
+ 128)
4528 as_warn (_("Register value annotation ignored"));
4531 gr_values
[regno
- REG_GR
].known
= 1;
4532 gr_values
[regno
- REG_GR
].value
= value
;
4533 gr_values
[regno
- REG_GR
].path
= md
.path
;
4536 demand_empty_rest_of_line ();
4539 /* select dv checking mode
4544 A stop is inserted when changing modes
4551 if (md
.manual_bundling
)
4552 as_warn (_("Directive invalid within a bundle"));
4554 if (type
== 'E' || type
== 'A')
4555 md
.mode_explicitly_set
= 0;
4557 md
.mode_explicitly_set
= 1;
4564 if (md
.explicit_mode
)
4565 insn_group_break (1, 0, 0);
4566 md
.explicit_mode
= 0;
4570 if (!md
.explicit_mode
)
4571 insn_group_break (1, 0, 0);
4572 md
.explicit_mode
= 1;
4576 if (md
.explicit_mode
!= md
.default_explicit_mode
)
4577 insn_group_break (1, 0, 0);
4578 md
.explicit_mode
= md
.default_explicit_mode
;
4579 md
.mode_explicitly_set
= 0;
4590 for (regno
= 0; regno
< 64; regno
++)
4592 if (mask
& ((valueT
) 1 << regno
))
4594 fprintf (stderr
, "%s p%d", comma
, regno
);
4601 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear")
4602 .pred.rel.imply p1, p2 (also .pred.rel "imply")
4603 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex")
4604 .pred.safe_across_calls p1 [, p2 [,...]]
4613 int p1
= -1, p2
= -1;
4617 if (*input_line_pointer
!= '"')
4619 as_bad (_("Missing predicate relation type"));
4620 ignore_rest_of_line ();
4626 char *form
= demand_copy_C_string (&len
);
4627 if (strcmp (form
, "mutex") == 0)
4629 else if (strcmp (form
, "clear") == 0)
4631 else if (strcmp (form
, "imply") == 0)
4635 as_bad (_("Unrecognized predicate relation type"));
4636 ignore_rest_of_line ();
4640 if (*input_line_pointer
== ',')
4641 ++input_line_pointer
;
4651 if (TOUPPER (*input_line_pointer
) != 'P'
4652 || (regno
= atoi (++input_line_pointer
)) < 0
4655 as_bad (_("Predicate register expected"));
4656 ignore_rest_of_line ();
4659 while (ISDIGIT (*input_line_pointer
))
4660 ++input_line_pointer
;
4667 as_warn (_("Duplicate predicate register ignored"));
4670 /* See if it's a range. */
4671 if (*input_line_pointer
== '-')
4674 ++input_line_pointer
;
4676 if (TOUPPER (*input_line_pointer
) != 'P'
4677 || (regno
= atoi (++input_line_pointer
)) < 0
4680 as_bad (_("Predicate register expected"));
4681 ignore_rest_of_line ();
4684 while (ISDIGIT (*input_line_pointer
))
4685 ++input_line_pointer
;
4689 as_bad (_("Bad register range"));
4690 ignore_rest_of_line ();
4701 if (*input_line_pointer
!= ',')
4703 ++input_line_pointer
;
4712 clear_qp_mutex (mask
);
4713 clear_qp_implies (mask
, (valueT
) 0);
4716 if (count
!= 2 || p1
== -1 || p2
== -1)
4717 as_bad (_("Predicate source and target required"));
4718 else if (p1
== 0 || p2
== 0)
4719 as_bad (_("Use of p0 is not valid in this context"));
4721 add_qp_imply (p1
, p2
);
4726 as_bad (_("At least two PR arguments expected"));
4731 as_bad (_("Use of p0 is not valid in this context"));
4734 add_qp_mutex (mask
);
4737 /* note that we don't override any existing relations */
4740 as_bad (_("At least one PR argument expected"));
4745 fprintf (stderr
, "Safe across calls: ");
4746 print_prmask (mask
);
4747 fprintf (stderr
, "\n");
4749 qp_safe_across_calls
= mask
;
4752 demand_empty_rest_of_line ();
4755 /* .entry label [, label [, ...]]
4756 Hint to DV code that the given labels are to be considered entry points.
4757 Otherwise, only global labels are considered entry points. */
4761 int dummy ATTRIBUTE_UNUSED
;
4770 name
= input_line_pointer
;
4771 c
= get_symbol_end ();
4772 symbolP
= symbol_find_or_make (name
);
4774 err
= hash_insert (md
.entry_hash
, S_GET_NAME (symbolP
), (PTR
) symbolP
);
4776 as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"),
4779 *input_line_pointer
= c
;
4781 c
= *input_line_pointer
;
4784 input_line_pointer
++;
4786 if (*input_line_pointer
== '\n')
4792 demand_empty_rest_of_line ();
4795 /* .mem.offset offset, base
4796 "base" is used to distinguish between offsets from a different base. */
4799 dot_mem_offset (dummy
)
4800 int dummy ATTRIBUTE_UNUSED
;
4802 md
.mem_offset
.hint
= 1;
4803 md
.mem_offset
.offset
= get_absolute_expression ();
4804 if (*input_line_pointer
!= ',')
4806 as_bad (_("Comma expected"));
4807 ignore_rest_of_line ();
4810 ++input_line_pointer
;
4811 md
.mem_offset
.base
= get_absolute_expression ();
4812 demand_empty_rest_of_line ();
4815 /* ia64-specific pseudo-ops: */
4816 const pseudo_typeS md_pseudo_table
[] =
4818 { "radix", dot_radix
, 0 },
4819 { "lcomm", s_lcomm_bytes
, 1 },
4820 { "bss", dot_special_section
, SPECIAL_SECTION_BSS
},
4821 { "sbss", dot_special_section
, SPECIAL_SECTION_SBSS
},
4822 { "sdata", dot_special_section
, SPECIAL_SECTION_SDATA
},
4823 { "rodata", dot_special_section
, SPECIAL_SECTION_RODATA
},
4824 { "comment", dot_special_section
, SPECIAL_SECTION_COMMENT
},
4825 { "ia_64.unwind", dot_special_section
, SPECIAL_SECTION_UNWIND
},
4826 { "ia_64.unwind_info", dot_special_section
, SPECIAL_SECTION_UNWIND_INFO
},
4827 { "init_array", dot_special_section
, SPECIAL_SECTION_INIT_ARRAY
},
4828 { "fini_array", dot_special_section
, SPECIAL_SECTION_FINI_ARRAY
},
4829 { "proc", dot_proc
, 0 },
4830 { "body", dot_body
, 0 },
4831 { "prologue", dot_prologue
, 0 },
4832 { "endp", dot_endp
, 0 },
4833 { "file", (void (*) PARAMS ((int))) dwarf2_directive_file
, 0 },
4834 { "loc", dwarf2_directive_loc
, 0 },
4836 { "fframe", dot_fframe
, 0 },
4837 { "vframe", dot_vframe
, 0 },
4838 { "vframesp", dot_vframesp
, 0 },
4839 { "vframepsp", dot_vframepsp
, 0 },
4840 { "save", dot_save
, 0 },
4841 { "restore", dot_restore
, 0 },
4842 { "restorereg", dot_restorereg
, 0 },
4843 { "restorereg.p", dot_restorereg_p
, 0 },
4844 { "handlerdata", dot_handlerdata
, 0 },
4845 { "unwentry", dot_unwentry
, 0 },
4846 { "altrp", dot_altrp
, 0 },
4847 { "savesp", dot_savemem
, 0 },
4848 { "savepsp", dot_savemem
, 1 },
4849 { "save.g", dot_saveg
, 0 },
4850 { "save.f", dot_savef
, 0 },
4851 { "save.b", dot_saveb
, 0 },
4852 { "save.gf", dot_savegf
, 0 },
4853 { "spill", dot_spill
, 0 },
4854 { "spillreg", dot_spillreg
, 0 },
4855 { "spillsp", dot_spillmem
, 0 },
4856 { "spillpsp", dot_spillmem
, 1 },
4857 { "spillreg.p", dot_spillreg_p
, 0 },
4858 { "spillsp.p", dot_spillmem_p
, 0 },
4859 { "spillpsp.p", dot_spillmem_p
, 1 },
4860 { "label_state", dot_label_state
, 0 },
4861 { "copy_state", dot_copy_state
, 0 },
4862 { "unwabi", dot_unwabi
, 0 },
4863 { "personality", dot_personality
, 0 },
4865 { "estate", dot_estate
, 0 },
4867 { "mii", dot_template
, 0x0 },
4868 { "mli", dot_template
, 0x2 }, /* old format, for compatibility */
4869 { "mlx", dot_template
, 0x2 },
4870 { "mmi", dot_template
, 0x4 },
4871 { "mfi", dot_template
, 0x6 },
4872 { "mmf", dot_template
, 0x7 },
4873 { "mib", dot_template
, 0x8 },
4874 { "mbb", dot_template
, 0x9 },
4875 { "bbb", dot_template
, 0xb },
4876 { "mmb", dot_template
, 0xc },
4877 { "mfb", dot_template
, 0xe },
4879 { "lb", dot_scope
, 0 },
4880 { "le", dot_scope
, 1 },
4882 { "align", s_align_bytes
, 0 },
4883 { "regstk", dot_regstk
, 0 },
4884 { "rotr", dot_rot
, DYNREG_GR
},
4885 { "rotf", dot_rot
, DYNREG_FR
},
4886 { "rotp", dot_rot
, DYNREG_PR
},
4887 { "lsb", dot_byteorder
, 0 },
4888 { "msb", dot_byteorder
, 1 },
4889 { "psr", dot_psr
, 0 },
4890 { "alias", dot_alias
, 0 },
4891 { "ln", dot_ln
, 0 }, /* source line info (for debugging) */
4893 { "xdata1", dot_xdata
, 1 },
4894 { "xdata2", dot_xdata
, 2 },
4895 { "xdata4", dot_xdata
, 4 },
4896 { "xdata8", dot_xdata
, 8 },
4897 { "xreal4", dot_xfloat_cons
, 'f' },
4898 { "xreal8", dot_xfloat_cons
, 'd' },
4899 { "xreal10", dot_xfloat_cons
, 'x' },
4900 { "xstring", dot_xstringer
, 0 },
4901 { "xstringz", dot_xstringer
, 1 },
4903 /* unaligned versions: */
4904 { "xdata2.ua", dot_xdata_ua
, 2 },
4905 { "xdata4.ua", dot_xdata_ua
, 4 },
4906 { "xdata8.ua", dot_xdata_ua
, 8 },
4907 { "xreal4.ua", dot_xfloat_cons_ua
, 'f' },
4908 { "xreal8.ua", dot_xfloat_cons_ua
, 'd' },
4909 { "xreal10.ua", dot_xfloat_cons_ua
, 'x' },
4911 /* annotations/DV checking support */
4912 { "entry", dot_entry
, 0 },
4913 { "mem.offset", dot_mem_offset
, 0 },
4914 { "pred.rel", dot_pred_rel
, 0 },
4915 { "pred.rel.clear", dot_pred_rel
, 'c' },
4916 { "pred.rel.imply", dot_pred_rel
, 'i' },
4917 { "pred.rel.mutex", dot_pred_rel
, 'm' },
4918 { "pred.safe_across_calls", dot_pred_rel
, 's' },
4919 { "reg.val", dot_reg_val
, 0 },
4920 { "auto", dot_dv_mode
, 'a' },
4921 { "explicit", dot_dv_mode
, 'e' },
4922 { "default", dot_dv_mode
, 'd' },
4924 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work.
4925 IA-64 aligns data allocation pseudo-ops by default, so we have to
4926 tell it that these ones are supposed to be unaligned. Long term,
4927 should rewrite so that only IA-64 specific data allocation pseudo-ops
4928 are aligned by default. */
4929 {"2byte", stmt_cons_ua
, 2},
4930 {"4byte", stmt_cons_ua
, 4},
4931 {"8byte", stmt_cons_ua
, 8},
4936 static const struct pseudo_opcode
4939 void (*handler
) (int);
4944 /* these are more like pseudo-ops, but don't start with a dot */
4945 { "data1", cons
, 1 },
4946 { "data2", cons
, 2 },
4947 { "data4", cons
, 4 },
4948 { "data8", cons
, 8 },
4949 { "data16", cons
, 16 },
4950 { "real4", stmt_float_cons
, 'f' },
4951 { "real8", stmt_float_cons
, 'd' },
4952 { "real10", stmt_float_cons
, 'x' },
4953 { "string", stringer
, 0 },
4954 { "stringz", stringer
, 1 },
4956 /* unaligned versions: */
4957 { "data2.ua", stmt_cons_ua
, 2 },
4958 { "data4.ua", stmt_cons_ua
, 4 },
4959 { "data8.ua", stmt_cons_ua
, 8 },
4960 { "data16.ua", stmt_cons_ua
, 16 },
4961 { "real4.ua", float_cons
, 'f' },
4962 { "real8.ua", float_cons
, 'd' },
4963 { "real10.ua", float_cons
, 'x' },
4966 /* Declare a register by creating a symbol for it and entering it in
4967 the symbol table. */
4970 declare_register (name
, regnum
)
4977 sym
= symbol_new (name
, reg_section
, regnum
, &zero_address_frag
);
4979 err
= hash_insert (md
.reg_hash
, S_GET_NAME (sym
), (PTR
) sym
);
4981 as_fatal ("Inserting \"%s\" into register table failed: %s",
4988 declare_register_set (prefix
, num_regs
, base_regnum
)
4996 for (i
= 0; i
< num_regs
; ++i
)
4998 sprintf (name
, "%s%u", prefix
, i
);
4999 declare_register (name
, base_regnum
+ i
);
5004 operand_width (opnd
)
5005 enum ia64_opnd opnd
;
5007 const struct ia64_operand
*odesc
= &elf64_ia64_operands
[opnd
];
5008 unsigned int bits
= 0;
5012 for (i
= 0; i
< NELEMS (odesc
->field
) && odesc
->field
[i
].bits
; ++i
)
5013 bits
+= odesc
->field
[i
].bits
;
5018 static enum operand_match_result
5019 operand_match (idesc
, index
, e
)
5020 const struct ia64_opcode
*idesc
;
5024 enum ia64_opnd opnd
= idesc
->operands
[index
];
5025 int bits
, relocatable
= 0;
5026 struct insn_fix
*fix
;
5033 case IA64_OPND_AR_CCV
:
5034 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 32)
5035 return OPERAND_MATCH
;
5038 case IA64_OPND_AR_CSD
:
5039 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 25)
5040 return OPERAND_MATCH
;
5043 case IA64_OPND_AR_PFS
:
5044 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_AR
+ 64)
5045 return OPERAND_MATCH
;
5049 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_GR
+ 0)
5050 return OPERAND_MATCH
;
5054 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_IP
)
5055 return OPERAND_MATCH
;
5059 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR
)
5060 return OPERAND_MATCH
;
5063 case IA64_OPND_PR_ROT
:
5064 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PR_ROT
)
5065 return OPERAND_MATCH
;
5069 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR
)
5070 return OPERAND_MATCH
;
5073 case IA64_OPND_PSR_L
:
5074 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_L
)
5075 return OPERAND_MATCH
;
5078 case IA64_OPND_PSR_UM
:
5079 if (e
->X_op
== O_register
&& e
->X_add_number
== REG_PSR_UM
)
5080 return OPERAND_MATCH
;
5084 if (e
->X_op
== O_constant
)
5086 if (e
->X_add_number
== 1)
5087 return OPERAND_MATCH
;
5089 return OPERAND_OUT_OF_RANGE
;
5094 if (e
->X_op
== O_constant
)
5096 if (e
->X_add_number
== 8)
5097 return OPERAND_MATCH
;
5099 return OPERAND_OUT_OF_RANGE
;
5104 if (e
->X_op
== O_constant
)
5106 if (e
->X_add_number
== 16)
5107 return OPERAND_MATCH
;
5109 return OPERAND_OUT_OF_RANGE
;
5113 /* register operands: */
5116 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_AR
5117 && e
->X_add_number
< REG_AR
+ 128)
5118 return OPERAND_MATCH
;
5123 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_BR
5124 && e
->X_add_number
< REG_BR
+ 8)
5125 return OPERAND_MATCH
;
5129 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_CR
5130 && e
->X_add_number
< REG_CR
+ 128)
5131 return OPERAND_MATCH
;
5138 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_FR
5139 && e
->X_add_number
< REG_FR
+ 128)
5140 return OPERAND_MATCH
;
5145 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_P
5146 && e
->X_add_number
< REG_P
+ 64)
5147 return OPERAND_MATCH
;
5153 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
5154 && e
->X_add_number
< REG_GR
+ 128)
5155 return OPERAND_MATCH
;
5158 case IA64_OPND_R3_2
:
5159 if (e
->X_op
== O_register
&& e
->X_add_number
>= REG_GR
)
5161 if (e
->X_add_number
< REG_GR
+ 4)
5162 return OPERAND_MATCH
;
5163 else if (e
->X_add_number
< REG_GR
+ 128)
5164 return OPERAND_OUT_OF_RANGE
;
5168 /* indirect operands: */
5169 case IA64_OPND_CPUID_R3
:
5170 case IA64_OPND_DBR_R3
:
5171 case IA64_OPND_DTR_R3
:
5172 case IA64_OPND_ITR_R3
:
5173 case IA64_OPND_IBR_R3
:
5174 case IA64_OPND_MSR_R3
:
5175 case IA64_OPND_PKR_R3
:
5176 case IA64_OPND_PMC_R3
:
5177 case IA64_OPND_PMD_R3
:
5178 case IA64_OPND_RR_R3
:
5179 if (e
->X_op
== O_index
&& e
->X_op_symbol
5180 && (S_GET_VALUE (e
->X_op_symbol
) - IND_CPUID
5181 == opnd
- IA64_OPND_CPUID_R3
))
5182 return OPERAND_MATCH
;
5186 if (e
->X_op
== O_index
&& !e
->X_op_symbol
)
5187 return OPERAND_MATCH
;
5190 /* immediate operands: */
5191 case IA64_OPND_CNT2a
:
5192 case IA64_OPND_LEN4
:
5193 case IA64_OPND_LEN6
:
5194 bits
= operand_width (idesc
->operands
[index
]);
5195 if (e
->X_op
== O_constant
)
5197 if ((bfd_vma
) (e
->X_add_number
- 1) < ((bfd_vma
) 1 << bits
))
5198 return OPERAND_MATCH
;
5200 return OPERAND_OUT_OF_RANGE
;
5204 case IA64_OPND_CNT2b
:
5205 if (e
->X_op
== O_constant
)
5207 if ((bfd_vma
) (e
->X_add_number
- 1) < 3)
5208 return OPERAND_MATCH
;
5210 return OPERAND_OUT_OF_RANGE
;
5214 case IA64_OPND_CNT2c
:
5215 val
= e
->X_add_number
;
5216 if (e
->X_op
== O_constant
)
5218 if ((val
== 0 || val
== 7 || val
== 15 || val
== 16))
5219 return OPERAND_MATCH
;
5221 return OPERAND_OUT_OF_RANGE
;
5226 /* SOR must be an integer multiple of 8 */
5227 if (e
->X_op
== O_constant
&& e
->X_add_number
& 0x7)
5228 return OPERAND_OUT_OF_RANGE
;
5231 if (e
->X_op
== O_constant
)
5233 if ((bfd_vma
) e
->X_add_number
<= 96)
5234 return OPERAND_MATCH
;
5236 return OPERAND_OUT_OF_RANGE
;
5240 case IA64_OPND_IMMU62
:
5241 if (e
->X_op
== O_constant
)
5243 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 62))
5244 return OPERAND_MATCH
;
5246 return OPERAND_OUT_OF_RANGE
;
5250 /* FIXME -- need 62-bit relocation type */
5251 as_bad (_("62-bit relocation not yet implemented"));
5255 case IA64_OPND_IMMU64
:
5256 if (e
->X_op
== O_symbol
|| e
->X_op
== O_pseudo_fixup
5257 || e
->X_op
== O_subtract
)
5259 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5260 fix
->code
= BFD_RELOC_IA64_IMM64
;
5261 if (e
->X_op
!= O_subtract
)
5263 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5264 if (e
->X_op
== O_pseudo_fixup
)
5268 fix
->opnd
= idesc
->operands
[index
];
5271 ++CURR_SLOT
.num_fixups
;
5272 return OPERAND_MATCH
;
5274 else if (e
->X_op
== O_constant
)
5275 return OPERAND_MATCH
;
5278 case IA64_OPND_CCNT5
:
5279 case IA64_OPND_CNT5
:
5280 case IA64_OPND_CNT6
:
5281 case IA64_OPND_CPOS6a
:
5282 case IA64_OPND_CPOS6b
:
5283 case IA64_OPND_CPOS6c
:
5284 case IA64_OPND_IMMU2
:
5285 case IA64_OPND_IMMU7a
:
5286 case IA64_OPND_IMMU7b
:
5287 case IA64_OPND_IMMU21
:
5288 case IA64_OPND_IMMU24
:
5289 case IA64_OPND_MBTYPE4
:
5290 case IA64_OPND_MHTYPE8
:
5291 case IA64_OPND_POS6
:
5292 bits
= operand_width (idesc
->operands
[index
]);
5293 if (e
->X_op
== O_constant
)
5295 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5296 return OPERAND_MATCH
;
5298 return OPERAND_OUT_OF_RANGE
;
5302 case IA64_OPND_IMMU9
:
5303 bits
= operand_width (idesc
->operands
[index
]);
5304 if (e
->X_op
== O_constant
)
5306 if ((bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << bits
))
5308 int lobits
= e
->X_add_number
& 0x3;
5309 if (((bfd_vma
) e
->X_add_number
& 0x3C) != 0 && lobits
== 0)
5310 e
->X_add_number
|= (bfd_vma
) 0x3;
5311 return OPERAND_MATCH
;
5314 return OPERAND_OUT_OF_RANGE
;
5318 case IA64_OPND_IMM44
:
5319 /* least 16 bits must be zero */
5320 if ((e
->X_add_number
& 0xffff) != 0)
5321 /* XXX technically, this is wrong: we should not be issuing warning
5322 messages until we're sure this instruction pattern is going to
5324 as_warn (_("lower 16 bits of mask ignored"));
5326 if (e
->X_op
== O_constant
)
5328 if (((e
->X_add_number
>= 0
5329 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 44))
5330 || (e
->X_add_number
< 0
5331 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 44))))
5334 if (e
->X_add_number
>= 0
5335 && (e
->X_add_number
& ((bfd_vma
) 1 << 43)) != 0)
5337 e
->X_add_number
|= ~(((bfd_vma
) 1 << 44) - 1);
5339 return OPERAND_MATCH
;
5342 return OPERAND_OUT_OF_RANGE
;
5346 case IA64_OPND_IMM17
:
5347 /* bit 0 is a don't care (pr0 is hardwired to 1) */
5348 if (e
->X_op
== O_constant
)
5350 if (((e
->X_add_number
>= 0
5351 && (bfd_vma
) e
->X_add_number
< ((bfd_vma
) 1 << 17))
5352 || (e
->X_add_number
< 0
5353 && (bfd_vma
) -e
->X_add_number
<= ((bfd_vma
) 1 << 17))))
5356 if (e
->X_add_number
>= 0
5357 && (e
->X_add_number
& ((bfd_vma
) 1 << 16)) != 0)
5359 e
->X_add_number
|= ~(((bfd_vma
) 1 << 17) - 1);
5361 return OPERAND_MATCH
;
5364 return OPERAND_OUT_OF_RANGE
;
5368 case IA64_OPND_IMM14
:
5369 case IA64_OPND_IMM22
:
5371 case IA64_OPND_IMM1
:
5372 case IA64_OPND_IMM8
:
5373 case IA64_OPND_IMM8U4
:
5374 case IA64_OPND_IMM8M1
:
5375 case IA64_OPND_IMM8M1U4
:
5376 case IA64_OPND_IMM8M1U8
:
5377 case IA64_OPND_IMM9a
:
5378 case IA64_OPND_IMM9b
:
5379 bits
= operand_width (idesc
->operands
[index
]);
5380 if (relocatable
&& (e
->X_op
== O_symbol
5381 || e
->X_op
== O_subtract
5382 || e
->X_op
== O_pseudo_fixup
))
5384 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5386 if (idesc
->operands
[index
] == IA64_OPND_IMM14
)
5387 fix
->code
= BFD_RELOC_IA64_IMM14
;
5389 fix
->code
= BFD_RELOC_IA64_IMM22
;
5391 if (e
->X_op
!= O_subtract
)
5393 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5394 if (e
->X_op
== O_pseudo_fixup
)
5398 fix
->opnd
= idesc
->operands
[index
];
5401 ++CURR_SLOT
.num_fixups
;
5402 return OPERAND_MATCH
;
5404 else if (e
->X_op
!= O_constant
5405 && ! (e
->X_op
== O_big
&& opnd
== IA64_OPND_IMM8M1U8
))
5406 return OPERAND_MISMATCH
;
5408 if (opnd
== IA64_OPND_IMM8M1U4
)
5410 /* Zero is not valid for unsigned compares that take an adjusted
5411 constant immediate range. */
5412 if (e
->X_add_number
== 0)
5413 return OPERAND_OUT_OF_RANGE
;
5415 /* Sign-extend 32-bit unsigned numbers, so that the following range
5416 checks will work. */
5417 val
= e
->X_add_number
;
5418 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5419 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5420 val
= ((val
<< 32) >> 32);
5422 /* Check for 0x100000000. This is valid because
5423 0x100000000-1 is the same as ((uint32_t) -1). */
5424 if (val
== ((bfd_signed_vma
) 1 << 32))
5425 return OPERAND_MATCH
;
5429 else if (opnd
== IA64_OPND_IMM8M1U8
)
5431 /* Zero is not valid for unsigned compares that take an adjusted
5432 constant immediate range. */
5433 if (e
->X_add_number
== 0)
5434 return OPERAND_OUT_OF_RANGE
;
5436 /* Check for 0x10000000000000000. */
5437 if (e
->X_op
== O_big
)
5439 if (generic_bignum
[0] == 0
5440 && generic_bignum
[1] == 0
5441 && generic_bignum
[2] == 0
5442 && generic_bignum
[3] == 0
5443 && generic_bignum
[4] == 1)
5444 return OPERAND_MATCH
;
5446 return OPERAND_OUT_OF_RANGE
;
5449 val
= e
->X_add_number
- 1;
5451 else if (opnd
== IA64_OPND_IMM8M1
)
5452 val
= e
->X_add_number
- 1;
5453 else if (opnd
== IA64_OPND_IMM8U4
)
5455 /* Sign-extend 32-bit unsigned numbers, so that the following range
5456 checks will work. */
5457 val
= e
->X_add_number
;
5458 if (((val
& (~(bfd_vma
) 0 << 32)) == 0)
5459 && ((val
& ((bfd_vma
) 1 << 31)) != 0))
5460 val
= ((val
<< 32) >> 32);
5463 val
= e
->X_add_number
;
5465 if ((val
>= 0 && (bfd_vma
) val
< ((bfd_vma
) 1 << (bits
- 1)))
5466 || (val
< 0 && (bfd_vma
) -val
<= ((bfd_vma
) 1 << (bits
- 1))))
5467 return OPERAND_MATCH
;
5469 return OPERAND_OUT_OF_RANGE
;
5471 case IA64_OPND_INC3
:
5472 /* +/- 1, 4, 8, 16 */
5473 val
= e
->X_add_number
;
5476 if (e
->X_op
== O_constant
)
5478 if ((val
== 1 || val
== 4 || val
== 8 || val
== 16))
5479 return OPERAND_MATCH
;
5481 return OPERAND_OUT_OF_RANGE
;
5485 case IA64_OPND_TGT25
:
5486 case IA64_OPND_TGT25b
:
5487 case IA64_OPND_TGT25c
:
5488 case IA64_OPND_TGT64
:
5489 if (e
->X_op
== O_symbol
)
5491 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5492 if (opnd
== IA64_OPND_TGT25
)
5493 fix
->code
= BFD_RELOC_IA64_PCREL21F
;
5494 else if (opnd
== IA64_OPND_TGT25b
)
5495 fix
->code
= BFD_RELOC_IA64_PCREL21M
;
5496 else if (opnd
== IA64_OPND_TGT25c
)
5497 fix
->code
= BFD_RELOC_IA64_PCREL21B
;
5498 else if (opnd
== IA64_OPND_TGT64
)
5499 fix
->code
= BFD_RELOC_IA64_PCREL60B
;
5503 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5504 fix
->opnd
= idesc
->operands
[index
];
5507 ++CURR_SLOT
.num_fixups
;
5508 return OPERAND_MATCH
;
5510 case IA64_OPND_TAG13
:
5511 case IA64_OPND_TAG13b
:
5515 return OPERAND_MATCH
;
5518 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5519 /* There are no external relocs for TAG13/TAG13b fields, so we
5520 create a dummy reloc. This will not live past md_apply_fix3. */
5521 fix
->code
= BFD_RELOC_UNUSED
;
5522 fix
->code
= ia64_gen_real_reloc_type (e
->X_op_symbol
, fix
->code
);
5523 fix
->opnd
= idesc
->operands
[index
];
5526 ++CURR_SLOT
.num_fixups
;
5527 return OPERAND_MATCH
;
5534 case IA64_OPND_LDXMOV
:
5535 fix
= CURR_SLOT
.fixup
+ CURR_SLOT
.num_fixups
;
5536 fix
->code
= BFD_RELOC_IA64_LDXMOV
;
5537 fix
->opnd
= idesc
->operands
[index
];
5540 ++CURR_SLOT
.num_fixups
;
5541 return OPERAND_MATCH
;
5546 return OPERAND_MISMATCH
;
5555 memset (e
, 0, sizeof (*e
));
5558 if (*input_line_pointer
!= '}')
5560 sep
= *input_line_pointer
++;
5564 if (!md
.manual_bundling
)
5565 as_warn ("Found '}' when manual bundling is off");
5567 CURR_SLOT
.manual_bundling_off
= 1;
5568 md
.manual_bundling
= 0;
5574 /* Returns the next entry in the opcode table that matches the one in
5575 IDESC, and frees the entry in IDESC. If no matching entry is
5576 found, NULL is returned instead. */
5578 static struct ia64_opcode
*
5579 get_next_opcode (struct ia64_opcode
*idesc
)
5581 struct ia64_opcode
*next
= ia64_find_next_opcode (idesc
);
5582 ia64_free_opcode (idesc
);
5586 /* Parse the operands for the opcode and find the opcode variant that
5587 matches the specified operands, or NULL if no match is possible. */
5589 static struct ia64_opcode
*
5590 parse_operands (idesc
)
5591 struct ia64_opcode
*idesc
;
5593 int i
= 0, highest_unmatched_operand
, num_operands
= 0, num_outputs
= 0;
5594 int error_pos
, out_of_range_pos
, curr_out_of_range_pos
, sep
= 0;
5595 enum ia64_opnd expected_operand
= IA64_OPND_NIL
;
5596 enum operand_match_result result
;
5598 char *first_arg
= 0, *end
, *saved_input_pointer
;
5601 assert (strlen (idesc
->name
) <= 128);
5603 strcpy (mnemonic
, idesc
->name
);
5604 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5606 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
5607 can't parse the first operand until we have parsed the
5608 remaining operands of the "alloc" instruction. */
5610 first_arg
= input_line_pointer
;
5611 end
= strchr (input_line_pointer
, '=');
5614 as_bad ("Expected separator `='");
5617 input_line_pointer
= end
+ 1;
5622 for (; i
< NELEMS (CURR_SLOT
.opnd
); ++i
)
5624 sep
= parse_operand (CURR_SLOT
.opnd
+ i
);
5625 if (CURR_SLOT
.opnd
[i
].X_op
== O_absent
)
5630 if (sep
!= '=' && sep
!= ',')
5635 if (num_outputs
> 0)
5636 as_bad ("Duplicate equal sign (=) in instruction");
5638 num_outputs
= i
+ 1;
5643 as_bad ("Illegal operand separator `%c'", sep
);
5647 if (idesc
->operands
[2] == IA64_OPND_SOF
)
5649 /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
5650 know (strcmp (idesc
->name
, "alloc") == 0);
5651 if (num_operands
== 5 /* first_arg not included in this count! */
5652 && CURR_SLOT
.opnd
[2].X_op
== O_constant
5653 && CURR_SLOT
.opnd
[3].X_op
== O_constant
5654 && CURR_SLOT
.opnd
[4].X_op
== O_constant
5655 && CURR_SLOT
.opnd
[5].X_op
== O_constant
)
5657 sof
= set_regstack (CURR_SLOT
.opnd
[2].X_add_number
,
5658 CURR_SLOT
.opnd
[3].X_add_number
,
5659 CURR_SLOT
.opnd
[4].X_add_number
,
5660 CURR_SLOT
.opnd
[5].X_add_number
);
5662 /* now we can parse the first arg: */
5663 saved_input_pointer
= input_line_pointer
;
5664 input_line_pointer
= first_arg
;
5665 sep
= parse_operand (CURR_SLOT
.opnd
+ 0);
5667 --num_outputs
; /* force error */
5668 input_line_pointer
= saved_input_pointer
;
5670 CURR_SLOT
.opnd
[2].X_add_number
= sof
;
5671 CURR_SLOT
.opnd
[3].X_add_number
5672 = sof
- CURR_SLOT
.opnd
[4].X_add_number
;
5673 CURR_SLOT
.opnd
[4] = CURR_SLOT
.opnd
[5];
5677 highest_unmatched_operand
= 0;
5678 curr_out_of_range_pos
= -1;
5680 expected_operand
= idesc
->operands
[0];
5681 for (; idesc
; idesc
= get_next_opcode (idesc
))
5683 if (num_outputs
!= idesc
->num_outputs
)
5684 continue; /* mismatch in # of outputs */
5686 CURR_SLOT
.num_fixups
= 0;
5688 /* Try to match all operands. If we see an out-of-range operand,
5689 then continue trying to match the rest of the operands, since if
5690 the rest match, then this idesc will give the best error message. */
5692 out_of_range_pos
= -1;
5693 for (i
= 0; i
< num_operands
&& idesc
->operands
[i
]; ++i
)
5695 result
= operand_match (idesc
, i
, CURR_SLOT
.opnd
+ i
);
5696 if (result
!= OPERAND_MATCH
)
5698 if (result
!= OPERAND_OUT_OF_RANGE
)
5700 if (out_of_range_pos
< 0)
5701 /* remember position of the first out-of-range operand: */
5702 out_of_range_pos
= i
;
5706 /* If we did not match all operands, or if at least one operand was
5707 out-of-range, then this idesc does not match. Keep track of which
5708 idesc matched the most operands before failing. If we have two
5709 idescs that failed at the same position, and one had an out-of-range
5710 operand, then prefer the out-of-range operand. Thus if we have
5711 "add r0=0x1000000,r1" we get an error saying the constant is out
5712 of range instead of an error saying that the constant should have been
5715 if (i
!= num_operands
|| out_of_range_pos
>= 0)
5717 if (i
> highest_unmatched_operand
5718 || (i
== highest_unmatched_operand
5719 && out_of_range_pos
> curr_out_of_range_pos
))
5721 highest_unmatched_operand
= i
;
5722 if (out_of_range_pos
>= 0)
5724 expected_operand
= idesc
->operands
[out_of_range_pos
];
5725 error_pos
= out_of_range_pos
;
5729 expected_operand
= idesc
->operands
[i
];
5732 curr_out_of_range_pos
= out_of_range_pos
;
5737 if (num_operands
< NELEMS (idesc
->operands
)
5738 && idesc
->operands
[num_operands
])
5739 continue; /* mismatch in number of arguments */
5745 if (expected_operand
)
5746 as_bad ("Operand %u of `%s' should be %s",
5747 error_pos
+ 1, mnemonic
,
5748 elf64_ia64_operands
[expected_operand
].desc
);
5750 as_bad ("Operand mismatch");
5756 /* Keep track of state necessary to determine whether a NOP is necessary
5757 to avoid an erratum in A and B step Itanium chips, and return 1 if we
5758 detect a case where additional NOPs may be necessary. */
5760 errata_nop_necessary_p (slot
, insn_unit
)
5762 enum ia64_unit insn_unit
;
5765 struct group
*this_group
= md
.last_groups
+ md
.group_idx
;
5766 struct group
*prev_group
= md
.last_groups
+ (md
.group_idx
+ 2) % 3;
5767 struct ia64_opcode
*idesc
= slot
->idesc
;
5769 /* Test whether this could be the first insn in a problematic sequence. */
5770 if (insn_unit
== IA64_UNIT_F
)
5772 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5773 if (idesc
->operands
[i
] == IA64_OPND_P1
5774 || idesc
->operands
[i
] == IA64_OPND_P2
)
5776 int regno
= slot
->opnd
[i
].X_add_number
- REG_P
;
5777 /* Ignore invalid operands; they generate errors elsewhere. */
5780 this_group
->p_reg_set
[regno
] = 1;
5784 /* Test whether this could be the second insn in a problematic sequence. */
5785 if (insn_unit
== IA64_UNIT_M
&& slot
->qp_regno
> 0
5786 && prev_group
->p_reg_set
[slot
->qp_regno
])
5788 for (i
= 0; i
< idesc
->num_outputs
; i
++)
5789 if (idesc
->operands
[i
] == IA64_OPND_R1
5790 || idesc
->operands
[i
] == IA64_OPND_R2
5791 || idesc
->operands
[i
] == IA64_OPND_R3
)
5793 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5794 /* Ignore invalid operands; they generate errors elsewhere. */
5797 if (strncmp (idesc
->name
, "add", 3) != 0
5798 && strncmp (idesc
->name
, "sub", 3) != 0
5799 && strncmp (idesc
->name
, "shladd", 6) != 0
5800 && (idesc
->flags
& IA64_OPCODE_POSTINC
) == 0)
5801 this_group
->g_reg_set_conditionally
[regno
] = 1;
5805 /* Test whether this could be the third insn in a problematic sequence. */
5806 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; i
++)
5808 if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */
5809 idesc
->operands
[i
] == IA64_OPND_R3
5810 /* For mov indirect. */
5811 || idesc
->operands
[i
] == IA64_OPND_RR_R3
5812 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
5813 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
5814 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
5815 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
5816 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
5817 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
5818 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
5820 || idesc
->operands
[i
] == IA64_OPND_ITR_R3
5821 || idesc
->operands
[i
] == IA64_OPND_DTR_R3
5822 /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */
5823 || idesc
->operands
[i
] == IA64_OPND_MR3
)
5825 int regno
= slot
->opnd
[i
].X_add_number
- REG_GR
;
5826 /* Ignore invalid operands; they generate errors elsewhere. */
5829 if (idesc
->operands
[i
] == IA64_OPND_R3
)
5831 if (strcmp (idesc
->name
, "fc") != 0
5832 && strcmp (idesc
->name
, "tak") != 0
5833 && strcmp (idesc
->name
, "thash") != 0
5834 && strcmp (idesc
->name
, "tpa") != 0
5835 && strcmp (idesc
->name
, "ttag") != 0
5836 && strncmp (idesc
->name
, "ptr", 3) != 0
5837 && strncmp (idesc
->name
, "ptc", 3) != 0
5838 && strncmp (idesc
->name
, "probe", 5) != 0)
5841 if (prev_group
->g_reg_set_conditionally
[regno
])
5849 build_insn (slot
, insnp
)
5853 const struct ia64_operand
*odesc
, *o2desc
;
5854 struct ia64_opcode
*idesc
= slot
->idesc
;
5855 bfd_signed_vma insn
, val
;
5859 insn
= idesc
->opcode
| slot
->qp_regno
;
5861 for (i
= 0; i
< NELEMS (idesc
->operands
) && idesc
->operands
[i
]; ++i
)
5863 if (slot
->opnd
[i
].X_op
== O_register
5864 || slot
->opnd
[i
].X_op
== O_constant
5865 || slot
->opnd
[i
].X_op
== O_index
)
5866 val
= slot
->opnd
[i
].X_add_number
;
5867 else if (slot
->opnd
[i
].X_op
== O_big
)
5869 /* This must be the value 0x10000000000000000. */
5870 assert (idesc
->operands
[i
] == IA64_OPND_IMM8M1U8
);
5876 switch (idesc
->operands
[i
])
5878 case IA64_OPND_IMMU64
:
5879 *insnp
++ = (val
>> 22) & 0x1ffffffffffLL
;
5880 insn
|= (((val
& 0x7f) << 13) | (((val
>> 7) & 0x1ff) << 27)
5881 | (((val
>> 16) & 0x1f) << 22) | (((val
>> 21) & 0x1) << 21)
5882 | (((val
>> 63) & 0x1) << 36));
5885 case IA64_OPND_IMMU62
:
5886 val
&= 0x3fffffffffffffffULL
;
5887 if (val
!= slot
->opnd
[i
].X_add_number
)
5888 as_warn (_("Value truncated to 62 bits"));
5889 *insnp
++ = (val
>> 21) & 0x1ffffffffffLL
;
5890 insn
|= (((val
& 0xfffff) << 6) | (((val
>> 20) & 0x1) << 36));
5893 case IA64_OPND_TGT64
:
5895 *insnp
++ = ((val
>> 20) & 0x7fffffffffLL
) << 2;
5896 insn
|= ((((val
>> 59) & 0x1) << 36)
5897 | (((val
>> 0) & 0xfffff) << 13));
5928 case IA64_OPND_R3_2
:
5929 case IA64_OPND_CPUID_R3
:
5930 case IA64_OPND_DBR_R3
:
5931 case IA64_OPND_DTR_R3
:
5932 case IA64_OPND_ITR_R3
:
5933 case IA64_OPND_IBR_R3
:
5935 case IA64_OPND_MSR_R3
:
5936 case IA64_OPND_PKR_R3
:
5937 case IA64_OPND_PMC_R3
:
5938 case IA64_OPND_PMD_R3
:
5939 case IA64_OPND_RR_R3
:
5947 odesc
= elf64_ia64_operands
+ idesc
->operands
[i
];
5948 err
= (*odesc
->insert
) (odesc
, val
, &insn
);
5950 as_bad_where (slot
->src_file
, slot
->src_line
,
5951 "Bad operand value: %s", err
);
5952 if (idesc
->flags
& IA64_OPCODE_PSEUDO
)
5954 if ((idesc
->flags
& IA64_OPCODE_F2_EQ_F3
)
5955 && odesc
== elf64_ia64_operands
+ IA64_OPND_F3
)
5957 o2desc
= elf64_ia64_operands
+ IA64_OPND_F2
;
5958 (*o2desc
->insert
) (o2desc
, val
, &insn
);
5960 if ((idesc
->flags
& IA64_OPCODE_LEN_EQ_64MCNT
)
5961 && (odesc
== elf64_ia64_operands
+ IA64_OPND_CPOS6a
5962 || odesc
== elf64_ia64_operands
+ IA64_OPND_POS6
))
5964 o2desc
= elf64_ia64_operands
+ IA64_OPND_LEN6
;
5965 (*o2desc
->insert
) (o2desc
, 64 - val
, &insn
);
5975 unsigned int manual_bundling_on
= 0, manual_bundling_off
= 0;
5976 unsigned int manual_bundling
= 0;
5977 enum ia64_unit required_unit
, insn_unit
= 0;
5978 enum ia64_insn_type type
[3], insn_type
;
5979 unsigned int template, orig_template
;
5980 bfd_vma insn
[3] = { -1, -1, -1 };
5981 struct ia64_opcode
*idesc
;
5982 int end_of_insn_group
= 0, user_template
= -1;
5983 int n
, i
, j
, first
, curr
;
5985 bfd_vma t0
= 0, t1
= 0;
5986 struct label_fix
*lfix
;
5987 struct insn_fix
*ifix
;
5992 first
= (md
.curr_slot
+ NUM_SLOTS
- md
.num_slots_in_use
) % NUM_SLOTS
;
5993 know (first
>= 0 & first
< NUM_SLOTS
);
5994 n
= MIN (3, md
.num_slots_in_use
);
5996 /* Determine template: user user_template if specified, best match
5999 if (md
.slot
[first
].user_template
>= 0)
6000 user_template
= template = md
.slot
[first
].user_template
;
6003 /* Auto select appropriate template. */
6004 memset (type
, 0, sizeof (type
));
6006 for (i
= 0; i
< n
; ++i
)
6008 if (md
.slot
[curr
].label_fixups
&& i
!= 0)
6010 type
[i
] = md
.slot
[curr
].idesc
->type
;
6011 curr
= (curr
+ 1) % NUM_SLOTS
;
6013 template = best_template
[type
[0]][type
[1]][type
[2]];
6016 /* initialize instructions with appropriate nops: */
6017 for (i
= 0; i
< 3; ++i
)
6018 insn
[i
] = nop
[ia64_templ_desc
[template].exec_unit
[i
]];
6022 /* now fill in slots with as many insns as possible: */
6024 idesc
= md
.slot
[curr
].idesc
;
6025 end_of_insn_group
= 0;
6026 for (i
= 0; i
< 3 && md
.num_slots_in_use
> 0; ++i
)
6028 /* Set the slot number for prologue/body records now as those
6029 refer to the current point, not the point after the
6030 instruction has been issued: */
6031 /* Don't try to delete prologue/body records here, as that will cause
6032 them to also be deleted from the master list of unwind records. */
6033 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6034 if (ptr
->r
.type
== prologue
|| ptr
->r
.type
== prologue_gr
6035 || ptr
->r
.type
== body
)
6037 ptr
->slot_number
= (unsigned long) f
+ i
;
6038 ptr
->slot_frag
= frag_now
;
6041 if (idesc
->flags
& IA64_OPCODE_SLOT2
)
6043 if (manual_bundling
&& i
!= 2)
6044 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6045 "`%s' must be last in bundle", idesc
->name
);
6049 if (idesc
->flags
& IA64_OPCODE_LAST
)
6052 unsigned int required_template
;
6054 /* If we need a stop bit after an M slot, our only choice is
6055 template 5 (M;;MI). If we need a stop bit after a B
6056 slot, our only choice is to place it at the end of the
6057 bundle, because the only available templates are MIB,
6058 MBB, BBB, MMB, and MFB. We don't handle anything other
6059 than M and B slots because these are the only kind of
6060 instructions that can have the IA64_OPCODE_LAST bit set. */
6061 required_template
= template;
6062 switch (idesc
->type
)
6066 required_template
= 5;
6074 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6075 "Internal error: don't know how to force %s to end"
6076 "of instruction group", idesc
->name
);
6080 if (manual_bundling
&& i
!= required_slot
)
6081 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6082 "`%s' must be last in instruction group",
6084 if (required_slot
< i
)
6085 /* Can't fit this instruction. */
6089 if (required_template
!= template)
6091 /* If we switch the template, we need to reset the NOPs
6092 after slot i. The slot-types of the instructions ahead
6093 of i never change, so we don't need to worry about
6094 changing NOPs in front of this slot. */
6095 for (j
= i
; j
< 3; ++j
)
6096 insn
[j
] = nop
[ia64_templ_desc
[required_template
].exec_unit
[j
]];
6098 template = required_template
;
6100 if (curr
!= first
&& md
.slot
[curr
].label_fixups
)
6102 if (manual_bundling_on
)
6103 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6104 "Label must be first in a bundle");
6105 /* This insn must go into the first slot of a bundle. */
6109 manual_bundling_on
= md
.slot
[curr
].manual_bundling_on
;
6110 manual_bundling_off
= md
.slot
[curr
].manual_bundling_off
;
6112 if (manual_bundling_on
)
6115 manual_bundling
= 1;
6117 break; /* need to start a new bundle */
6120 if (end_of_insn_group
&& md
.num_slots_in_use
>= 1)
6122 /* We need an instruction group boundary in the middle of a
6123 bundle. See if we can switch to an other template with
6124 an appropriate boundary. */
6126 orig_template
= template;
6127 if (i
== 1 && (user_template
== 4
6128 || (user_template
< 0
6129 && (ia64_templ_desc
[template].exec_unit
[0]
6133 end_of_insn_group
= 0;
6135 else if (i
== 2 && (user_template
== 0
6136 || (user_template
< 0
6137 && (ia64_templ_desc
[template].exec_unit
[1]
6139 /* This test makes sure we don't switch the template if
6140 the next instruction is one that needs to be first in
6141 an instruction group. Since all those instructions are
6142 in the M group, there is no way such an instruction can
6143 fit in this bundle even if we switch the template. The
6144 reason we have to check for this is that otherwise we
6145 may end up generating "MI;;I M.." which has the deadly
6146 effect that the second M instruction is no longer the
6147 first in the bundle! --davidm 99/12/16 */
6148 && (idesc
->flags
& IA64_OPCODE_FIRST
) == 0)
6151 end_of_insn_group
= 0;
6153 else if (curr
!= first
)
6154 /* can't fit this insn */
6157 if (template != orig_template
)
6158 /* if we switch the template, we need to reset the NOPs
6159 after slot i. The slot-types of the instructions ahead
6160 of i never change, so we don't need to worry about
6161 changing NOPs in front of this slot. */
6162 for (j
= i
; j
< 3; ++j
)
6163 insn
[j
] = nop
[ia64_templ_desc
[template].exec_unit
[j
]];
6165 required_unit
= ia64_templ_desc
[template].exec_unit
[i
];
6167 /* resolve dynamic opcodes such as "break", "hint", and "nop": */
6168 if (idesc
->type
== IA64_TYPE_DYN
)
6170 if ((strcmp (idesc
->name
, "nop") == 0)
6171 || (strcmp (idesc
->name
, "hint") == 0)
6172 || (strcmp (idesc
->name
, "break") == 0))
6173 insn_unit
= required_unit
;
6174 else if (strcmp (idesc
->name
, "chk.s") == 0)
6176 insn_unit
= IA64_UNIT_M
;
6177 if (required_unit
== IA64_UNIT_I
)
6178 insn_unit
= IA64_UNIT_I
;
6181 as_fatal ("emit_one_bundle: unexpected dynamic op");
6183 sprintf (mnemonic
, "%s.%c", idesc
->name
, "?imbf??"[insn_unit
]);
6184 ia64_free_opcode (idesc
);
6185 md
.slot
[curr
].idesc
= idesc
= ia64_find_opcode (mnemonic
);
6187 know (!idesc
->next
); /* no resolved dynamic ops have collisions */
6192 insn_type
= idesc
->type
;
6193 insn_unit
= IA64_UNIT_NIL
;
6197 if (required_unit
== IA64_UNIT_I
|| required_unit
== IA64_UNIT_M
)
6198 insn_unit
= required_unit
;
6200 case IA64_TYPE_X
: insn_unit
= IA64_UNIT_L
; break;
6201 case IA64_TYPE_I
: insn_unit
= IA64_UNIT_I
; break;
6202 case IA64_TYPE_M
: insn_unit
= IA64_UNIT_M
; break;
6203 case IA64_TYPE_B
: insn_unit
= IA64_UNIT_B
; break;
6204 case IA64_TYPE_F
: insn_unit
= IA64_UNIT_F
; break;
6209 if (insn_unit
!= required_unit
)
6211 if (required_unit
== IA64_UNIT_L
6212 && insn_unit
== IA64_UNIT_I
6213 && !(idesc
->flags
& IA64_OPCODE_X_IN_MLX
))
6215 /* we got ourselves an MLX template but the current
6216 instruction isn't an X-unit, or an I-unit instruction
6217 that can go into the X slot of an MLX template. Duh. */
6218 if (md
.num_slots_in_use
>= NUM_SLOTS
)
6220 as_bad_where (md
.slot
[curr
].src_file
,
6221 md
.slot
[curr
].src_line
,
6222 "`%s' can't go in X slot of "
6223 "MLX template", idesc
->name
);
6224 /* drop this insn so we don't livelock: */
6225 --md
.num_slots_in_use
;
6229 continue; /* try next slot */
6235 addr
= frag_now
->fr_address
+ frag_now_fix () - 16 + i
;
6236 dwarf2_gen_line_info (addr
, &md
.slot
[curr
].debug_line
);
6239 if (errata_nop_necessary_p (md
.slot
+ curr
, insn_unit
))
6240 as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
6242 build_insn (md
.slot
+ curr
, insn
+ i
);
6244 /* Set slot counts for non prologue/body unwind records. */
6245 for (ptr
= md
.slot
[curr
].unwind_record
; ptr
; ptr
= ptr
->next
)
6246 if (ptr
->r
.type
!= prologue
&& ptr
->r
.type
!= prologue_gr
6247 && ptr
->r
.type
!= body
)
6249 ptr
->slot_number
= (unsigned long) f
+ i
;
6250 ptr
->slot_frag
= frag_now
;
6252 md
.slot
[curr
].unwind_record
= NULL
;
6254 if (required_unit
== IA64_UNIT_L
)
6257 /* skip one slot for long/X-unit instructions */
6260 --md
.num_slots_in_use
;
6262 /* now is a good time to fix up the labels for this insn: */
6263 for (lfix
= md
.slot
[curr
].label_fixups
; lfix
; lfix
= lfix
->next
)
6265 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16);
6266 symbol_set_frag (lfix
->sym
, frag_now
);
6268 /* and fix up the tags also. */
6269 for (lfix
= md
.slot
[curr
].tag_fixups
; lfix
; lfix
= lfix
->next
)
6271 S_SET_VALUE (lfix
->sym
, frag_now_fix () - 16 + i
);
6272 symbol_set_frag (lfix
->sym
, frag_now
);
6275 for (j
= 0; j
< md
.slot
[curr
].num_fixups
; ++j
)
6277 ifix
= md
.slot
[curr
].fixup
+ j
;
6278 fix
= fix_new_exp (frag_now
, frag_now_fix () - 16 + i
, 8,
6279 &ifix
->expr
, ifix
->is_pcrel
, ifix
->code
);
6280 fix
->tc_fix_data
.opnd
= ifix
->opnd
;
6281 fix
->fx_plt
= (fix
->fx_r_type
== BFD_RELOC_IA64_PLTOFF22
);
6282 fix
->fx_file
= md
.slot
[curr
].src_file
;
6283 fix
->fx_line
= md
.slot
[curr
].src_line
;
6286 end_of_insn_group
= md
.slot
[curr
].end_of_insn_group
;
6288 if (end_of_insn_group
)
6290 md
.group_idx
= (md
.group_idx
+ 1) % 3;
6291 memset (md
.last_groups
+ md
.group_idx
, 0, sizeof md
.last_groups
[0]);
6295 ia64_free_opcode (md
.slot
[curr
].idesc
);
6296 memset (md
.slot
+ curr
, 0, sizeof (md
.slot
[curr
]));
6297 md
.slot
[curr
].user_template
= -1;
6299 if (manual_bundling_off
)
6301 manual_bundling
= 0;
6304 curr
= (curr
+ 1) % NUM_SLOTS
;
6305 idesc
= md
.slot
[curr
].idesc
;
6307 if (manual_bundling
)
6309 if (md
.num_slots_in_use
> 0)
6310 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6311 "`%s' does not fit into %s template",
6312 idesc
->name
, ia64_templ_desc
[template].name
);
6314 as_bad_where (md
.slot
[curr
].src_file
, md
.slot
[curr
].src_line
,
6315 "Missing '}' at end of file");
6317 know (md
.num_slots_in_use
< NUM_SLOTS
);
6319 t0
= end_of_insn_group
| (template << 1) | (insn
[0] << 5) | (insn
[1] << 46);
6320 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
6322 number_to_chars_littleendian (f
+ 0, t0
, 8);
6323 number_to_chars_littleendian (f
+ 8, t1
, 8);
6325 unwind
.next_slot_number
= (unsigned long) f
+ 16;
6326 unwind
.next_slot_frag
= frag_now
;
6330 md_parse_option (c
, arg
)
6337 /* Switches from the Intel assembler. */
6339 if (strcmp (arg
, "ilp64") == 0
6340 || strcmp (arg
, "lp64") == 0
6341 || strcmp (arg
, "p64") == 0)
6343 md
.flags
|= EF_IA_64_ABI64
;
6345 else if (strcmp (arg
, "ilp32") == 0)
6347 md
.flags
&= ~EF_IA_64_ABI64
;
6349 else if (strcmp (arg
, "le") == 0)
6351 md
.flags
&= ~EF_IA_64_BE
;
6353 else if (strcmp (arg
, "be") == 0)
6355 md
.flags
|= EF_IA_64_BE
;
6362 if (strcmp (arg
, "so") == 0)
6364 /* Suppress signon message. */
6366 else if (strcmp (arg
, "pi") == 0)
6368 /* Reject privileged instructions. FIXME */
6370 else if (strcmp (arg
, "us") == 0)
6372 /* Allow union of signed and unsigned range. FIXME */
6374 else if (strcmp (arg
, "close_fcalls") == 0)
6376 /* Do not resolve global function calls. */
6383 /* temp[="prefix"] Insert temporary labels into the object file
6384 symbol table prefixed by "prefix".
6385 Default prefix is ":temp:".
6390 /* indirect=<tgt> Assume unannotated indirect branches behavior
6391 according to <tgt> --
6392 exit: branch out from the current context (default)
6393 labels: all labels in context may be branch targets
6395 if (strncmp (arg
, "indirect=", 9) != 0)
6400 /* -X conflicts with an ignored option, use -x instead */
6402 if (!arg
|| strcmp (arg
, "explicit") == 0)
6404 /* set default mode to explicit */
6405 md
.default_explicit_mode
= 1;
6408 else if (strcmp (arg
, "auto") == 0)
6410 md
.default_explicit_mode
= 0;
6412 else if (strcmp (arg
, "debug") == 0)
6416 else if (strcmp (arg
, "debugx") == 0)
6418 md
.default_explicit_mode
= 1;
6423 as_bad (_("Unrecognized option '-x%s'"), arg
);
6428 /* nops Print nops statistics. */
6431 /* GNU specific switches for gcc. */
6432 case OPTION_MCONSTANT_GP
:
6433 md
.flags
|= EF_IA_64_CONS_GP
;
6436 case OPTION_MAUTO_PIC
:
6437 md
.flags
|= EF_IA_64_NOFUNCDESC_CONS_GP
;
6448 md_show_usage (stream
)
6453 --mconstant-gp mark output file as using the constant-GP model\n\
6454 (sets ELF header flag EF_IA_64_CONS_GP)\n\
6455 --mauto-pic mark output file as using the constant-GP model\n\
6456 without function descriptors (sets ELF header flag\n\
6457 EF_IA_64_NOFUNCDESC_CONS_GP)\n\
6458 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\
6459 -mle | -mbe select little- or big-endian byte order (default -mle)\n\
6460 -x | -xexplicit turn on dependency violation checking (default)\n\
6461 -xauto automagically remove dependency violations\n\
6462 -xdebug debug dependency violation checker\n"),
6467 ia64_after_parse_args ()
6469 if (debug_type
== DEBUG_STABS
)
6470 as_fatal (_("--gstabs is not supported for ia64"));
6473 /* Return true if TYPE fits in TEMPL at SLOT. */
6476 match (int templ
, int type
, int slot
)
6478 enum ia64_unit unit
;
6481 unit
= ia64_templ_desc
[templ
].exec_unit
[slot
];
6484 case IA64_TYPE_DYN
: result
= 1; break; /* for nop and break */
6486 result
= (unit
== IA64_UNIT_I
|| unit
== IA64_UNIT_M
);
6488 case IA64_TYPE_X
: result
= (unit
== IA64_UNIT_L
); break;
6489 case IA64_TYPE_I
: result
= (unit
== IA64_UNIT_I
); break;
6490 case IA64_TYPE_M
: result
= (unit
== IA64_UNIT_M
); break;
6491 case IA64_TYPE_B
: result
= (unit
== IA64_UNIT_B
); break;
6492 case IA64_TYPE_F
: result
= (unit
== IA64_UNIT_F
); break;
6493 default: result
= 0; break;
6498 /* Add a bit of extra goodness if a nop of type F or B would fit
6499 in TEMPL at SLOT. */
6502 extra_goodness (int templ
, int slot
)
6504 if (slot
== 1 && match (templ
, IA64_TYPE_F
, slot
))
6506 if (slot
== 2 && match (templ
, IA64_TYPE_B
, slot
))
6511 /* This function is called once, at assembler startup time. It sets
6512 up all the tables, etc. that the MD part of the assembler will need
6513 that can be determined before arguments are parsed. */
6517 int i
, j
, k
, t
, total
, ar_base
, cr_base
, goodness
, best
, regnum
, ok
;
6522 md
.explicit_mode
= md
.default_explicit_mode
;
6524 bfd_set_section_alignment (stdoutput
, text_section
, 4);
6526 target_big_endian
= TARGET_BYTES_BIG_ENDIAN
;
6527 pseudo_func
[FUNC_DTP_MODULE
].u
.sym
=
6528 symbol_new (".<dtpmod>", undefined_section
, FUNC_DTP_MODULE
,
6529 &zero_address_frag
);
6531 pseudo_func
[FUNC_DTP_RELATIVE
].u
.sym
=
6532 symbol_new (".<dtprel>", undefined_section
, FUNC_DTP_RELATIVE
,
6533 &zero_address_frag
);
6535 pseudo_func
[FUNC_FPTR_RELATIVE
].u
.sym
=
6536 symbol_new (".<fptr>", undefined_section
, FUNC_FPTR_RELATIVE
,
6537 &zero_address_frag
);
6539 pseudo_func
[FUNC_GP_RELATIVE
].u
.sym
=
6540 symbol_new (".<gprel>", undefined_section
, FUNC_GP_RELATIVE
,
6541 &zero_address_frag
);
6543 pseudo_func
[FUNC_LT_RELATIVE
].u
.sym
=
6544 symbol_new (".<ltoff>", undefined_section
, FUNC_LT_RELATIVE
,
6545 &zero_address_frag
);
6547 pseudo_func
[FUNC_PC_RELATIVE
].u
.sym
=
6548 symbol_new (".<pcrel>", undefined_section
, FUNC_PC_RELATIVE
,
6549 &zero_address_frag
);
6551 pseudo_func
[FUNC_PLT_RELATIVE
].u
.sym
=
6552 symbol_new (".<pltoff>", undefined_section
, FUNC_PLT_RELATIVE
,
6553 &zero_address_frag
);
6555 pseudo_func
[FUNC_SEC_RELATIVE
].u
.sym
=
6556 symbol_new (".<secrel>", undefined_section
, FUNC_SEC_RELATIVE
,
6557 &zero_address_frag
);
6559 pseudo_func
[FUNC_SEG_RELATIVE
].u
.sym
=
6560 symbol_new (".<segrel>", undefined_section
, FUNC_SEG_RELATIVE
,
6561 &zero_address_frag
);
6563 pseudo_func
[FUNC_TP_RELATIVE
].u
.sym
=
6564 symbol_new (".<tprel>", undefined_section
, FUNC_TP_RELATIVE
,
6565 &zero_address_frag
);
6567 pseudo_func
[FUNC_LTV_RELATIVE
].u
.sym
=
6568 symbol_new (".<ltv>", undefined_section
, FUNC_LTV_RELATIVE
,
6569 &zero_address_frag
);
6571 pseudo_func
[FUNC_LT_FPTR_RELATIVE
].u
.sym
=
6572 symbol_new (".<ltoff.fptr>", undefined_section
, FUNC_LT_FPTR_RELATIVE
,
6573 &zero_address_frag
);
6575 pseudo_func
[FUNC_LT_DTP_MODULE
].u
.sym
=
6576 symbol_new (".<ltoff.dtpmod>", undefined_section
, FUNC_LT_DTP_MODULE
,
6577 &zero_address_frag
);
6579 pseudo_func
[FUNC_LT_DTP_RELATIVE
].u
.sym
=
6580 symbol_new (".<ltoff.dptrel>", undefined_section
, FUNC_LT_DTP_RELATIVE
,
6581 &zero_address_frag
);
6583 pseudo_func
[FUNC_LT_TP_RELATIVE
].u
.sym
=
6584 symbol_new (".<ltoff.tprel>", undefined_section
, FUNC_LT_TP_RELATIVE
,
6585 &zero_address_frag
);
6587 pseudo_func
[FUNC_IPLT_RELOC
].u
.sym
=
6588 symbol_new (".<iplt>", undefined_section
, FUNC_IPLT_RELOC
,
6589 &zero_address_frag
);
6591 /* Compute the table of best templates. We compute goodness as a
6592 base 4 value, in which each match counts for 3, each F counts
6593 for 2, each B counts for 1. This should maximize the number of
6594 F and B nops in the chosen bundles, which is good because these
6595 pipelines are least likely to be overcommitted. */
6596 for (i
= 0; i
< IA64_NUM_TYPES
; ++i
)
6597 for (j
= 0; j
< IA64_NUM_TYPES
; ++j
)
6598 for (k
= 0; k
< IA64_NUM_TYPES
; ++k
)
6601 for (t
= 0; t
< NELEMS (ia64_templ_desc
); ++t
)
6604 if (match (t
, i
, 0))
6606 if (match (t
, j
, 1))
6608 if (match (t
, k
, 2))
6609 goodness
= 3 + 3 + 3;
6611 goodness
= 3 + 3 + extra_goodness (t
, 2);
6613 else if (match (t
, j
, 2))
6614 goodness
= 3 + 3 + extra_goodness (t
, 1);
6618 goodness
+= extra_goodness (t
, 1);
6619 goodness
+= extra_goodness (t
, 2);
6622 else if (match (t
, i
, 1))
6624 if (match (t
, j
, 2))
6627 goodness
= 3 + extra_goodness (t
, 2);
6629 else if (match (t
, i
, 2))
6630 goodness
= 3 + extra_goodness (t
, 1);
6632 if (goodness
> best
)
6635 best_template
[i
][j
][k
] = t
;
6640 for (i
= 0; i
< NUM_SLOTS
; ++i
)
6641 md
.slot
[i
].user_template
= -1;
6643 md
.pseudo_hash
= hash_new ();
6644 for (i
= 0; i
< NELEMS (pseudo_opcode
); ++i
)
6646 err
= hash_insert (md
.pseudo_hash
, pseudo_opcode
[i
].name
,
6647 (void *) (pseudo_opcode
+ i
));
6649 as_fatal ("ia64.md_begin: can't hash `%s': %s",
6650 pseudo_opcode
[i
].name
, err
);
6653 md
.reg_hash
= hash_new ();
6654 md
.dynreg_hash
= hash_new ();
6655 md
.const_hash
= hash_new ();
6656 md
.entry_hash
= hash_new ();
6658 /* general registers: */
6661 for (i
= 0; i
< total
; ++i
)
6663 sprintf (name
, "r%d", i
- REG_GR
);
6664 md
.regsym
[i
] = declare_register (name
, i
);
6667 /* floating point registers: */
6669 for (; i
< total
; ++i
)
6671 sprintf (name
, "f%d", i
- REG_FR
);
6672 md
.regsym
[i
] = declare_register (name
, i
);
6675 /* application registers: */
6678 for (; i
< total
; ++i
)
6680 sprintf (name
, "ar%d", i
- REG_AR
);
6681 md
.regsym
[i
] = declare_register (name
, i
);
6684 /* control registers: */
6687 for (; i
< total
; ++i
)
6689 sprintf (name
, "cr%d", i
- REG_CR
);
6690 md
.regsym
[i
] = declare_register (name
, i
);
6693 /* predicate registers: */
6695 for (; i
< total
; ++i
)
6697 sprintf (name
, "p%d", i
- REG_P
);
6698 md
.regsym
[i
] = declare_register (name
, i
);
6701 /* branch registers: */
6703 for (; i
< total
; ++i
)
6705 sprintf (name
, "b%d", i
- REG_BR
);
6706 md
.regsym
[i
] = declare_register (name
, i
);
6709 md
.regsym
[REG_IP
] = declare_register ("ip", REG_IP
);
6710 md
.regsym
[REG_CFM
] = declare_register ("cfm", REG_CFM
);
6711 md
.regsym
[REG_PR
] = declare_register ("pr", REG_PR
);
6712 md
.regsym
[REG_PR_ROT
] = declare_register ("pr.rot", REG_PR_ROT
);
6713 md
.regsym
[REG_PSR
] = declare_register ("psr", REG_PSR
);
6714 md
.regsym
[REG_PSR_L
] = declare_register ("psr.l", REG_PSR_L
);
6715 md
.regsym
[REG_PSR_UM
] = declare_register ("psr.um", REG_PSR_UM
);
6717 for (i
= 0; i
< NELEMS (indirect_reg
); ++i
)
6719 regnum
= indirect_reg
[i
].regnum
;
6720 md
.regsym
[regnum
] = declare_register (indirect_reg
[i
].name
, regnum
);
6723 /* define synonyms for application registers: */
6724 for (i
= REG_AR
; i
< REG_AR
+ NELEMS (ar
); ++i
)
6725 md
.regsym
[i
] = declare_register (ar
[i
- REG_AR
].name
,
6726 REG_AR
+ ar
[i
- REG_AR
].regnum
);
6728 /* define synonyms for control registers: */
6729 for (i
= REG_CR
; i
< REG_CR
+ NELEMS (cr
); ++i
)
6730 md
.regsym
[i
] = declare_register (cr
[i
- REG_CR
].name
,
6731 REG_CR
+ cr
[i
- REG_CR
].regnum
);
6733 declare_register ("gp", REG_GR
+ 1);
6734 declare_register ("sp", REG_GR
+ 12);
6735 declare_register ("rp", REG_BR
+ 0);
6737 /* pseudo-registers used to specify unwind info: */
6738 declare_register ("psp", REG_PSP
);
6740 declare_register_set ("ret", 4, REG_GR
+ 8);
6741 declare_register_set ("farg", 8, REG_FR
+ 8);
6742 declare_register_set ("fret", 8, REG_FR
+ 8);
6744 for (i
= 0; i
< NELEMS (const_bits
); ++i
)
6746 err
= hash_insert (md
.const_hash
, const_bits
[i
].name
,
6747 (PTR
) (const_bits
+ i
));
6749 as_fatal ("Inserting \"%s\" into constant hash table failed: %s",
6753 /* Set the architecture and machine depending on defaults and command line
6755 if (md
.flags
& EF_IA_64_ABI64
)
6756 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf64
);
6758 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_ia64
, bfd_mach_ia64_elf32
);
6761 as_warn (_("Could not set architecture and machine"));
6763 /* Set the pointer size and pointer shift size depending on md.flags */
6765 if (md
.flags
& EF_IA_64_ABI64
)
6767 md
.pointer_size
= 8; /* pointers are 8 bytes */
6768 md
.pointer_size_shift
= 3; /* alignment is 8 bytes = 2^2 */
6772 md
.pointer_size
= 4; /* pointers are 4 bytes */
6773 md
.pointer_size_shift
= 2; /* alignment is 4 bytes = 2^2 */
6776 md
.mem_offset
.hint
= 0;
6779 md
.entry_labels
= NULL
;
6782 /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin
6783 because that is called after md_parse_option which is where we do the
6784 dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the
6785 default endianness. */
6788 ia64_init (argc
, argv
)
6789 int argc ATTRIBUTE_UNUSED
;
6790 char **argv ATTRIBUTE_UNUSED
;
6792 md
.flags
= MD_FLAGS_DEFAULT
;
6795 /* Return a string for the target object file format. */
6798 ia64_target_format ()
6800 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6802 if (md
.flags
& EF_IA_64_BE
)
6804 if (md
.flags
& EF_IA_64_ABI64
)
6805 #if defined(TE_AIX50)
6806 return "elf64-ia64-aix-big";
6807 #elif defined(TE_HPUX)
6808 return "elf64-ia64-hpux-big";
6810 return "elf64-ia64-big";
6813 #if defined(TE_AIX50)
6814 return "elf32-ia64-aix-big";
6815 #elif defined(TE_HPUX)
6816 return "elf32-ia64-hpux-big";
6818 return "elf32-ia64-big";
6823 if (md
.flags
& EF_IA_64_ABI64
)
6825 return "elf64-ia64-aix-little";
6827 return "elf64-ia64-little";
6831 return "elf32-ia64-aix-little";
6833 return "elf32-ia64-little";
6838 return "unknown-format";
6842 ia64_end_of_source ()
6844 /* terminate insn group upon reaching end of file: */
6845 insn_group_break (1, 0, 0);
6847 /* emits slots we haven't written yet: */
6848 ia64_flush_insns ();
6850 bfd_set_private_flags (stdoutput
, md
.flags
);
6852 md
.mem_offset
.hint
= 0;
6858 if (md
.qp
.X_op
== O_register
)
6859 as_bad ("qualifying predicate not followed by instruction");
6860 md
.qp
.X_op
= O_absent
;
6862 if (ignore_input ())
6865 if (input_line_pointer
[0] == ';' && input_line_pointer
[-1] == ';')
6867 if (md
.detect_dv
&& !md
.explicit_mode
)
6868 as_warn (_("Explicit stops are ignored in auto mode"));
6870 insn_group_break (1, 0, 0);
6874 /* This is a hook for ia64_frob_label, so that it can distinguish tags from
6876 static int defining_tag
= 0;
6879 ia64_unrecognized_line (ch
)
6885 expression (&md
.qp
);
6886 if (*input_line_pointer
++ != ')')
6888 as_bad ("Expected ')'");
6891 if (md
.qp
.X_op
!= O_register
)
6893 as_bad ("Qualifying predicate expected");
6896 if (md
.qp
.X_add_number
< REG_P
|| md
.qp
.X_add_number
>= REG_P
+ 64)
6898 as_bad ("Predicate register expected");
6904 if (md
.manual_bundling
)
6905 as_warn ("Found '{' when manual bundling is already turned on");
6907 CURR_SLOT
.manual_bundling_on
= 1;
6908 md
.manual_bundling
= 1;
6910 /* Bundling is only acceptable in explicit mode
6911 or when in default automatic mode. */
6912 if (md
.detect_dv
&& !md
.explicit_mode
)
6914 if (!md
.mode_explicitly_set
6915 && !md
.default_explicit_mode
)
6918 as_warn (_("Found '{' after explicit switch to automatic mode"));
6923 if (!md
.manual_bundling
)
6924 as_warn ("Found '}' when manual bundling is off");
6926 PREV_SLOT
.manual_bundling_off
= 1;
6927 md
.manual_bundling
= 0;
6929 /* switch back to automatic mode, if applicable */
6932 && !md
.mode_explicitly_set
6933 && !md
.default_explicit_mode
)
6936 /* Allow '{' to follow on the same line. We also allow ";;", but that
6937 happens automatically because ';' is an end of line marker. */
6939 if (input_line_pointer
[0] == '{')
6941 input_line_pointer
++;
6942 return ia64_unrecognized_line ('{');
6945 demand_empty_rest_of_line ();
6955 if (md
.qp
.X_op
== O_register
)
6957 as_bad ("Tag must come before qualifying predicate.");
6961 /* This implements just enough of read_a_source_file in read.c to
6962 recognize labels. */
6963 if (is_name_beginner (*input_line_pointer
))
6965 s
= input_line_pointer
;
6966 c
= get_symbol_end ();
6968 else if (LOCAL_LABELS_FB
6969 && ISDIGIT (*input_line_pointer
))
6972 while (ISDIGIT (*input_line_pointer
))
6973 temp
= (temp
* 10) + *input_line_pointer
++ - '0';
6974 fb_label_instance_inc (temp
);
6975 s
= fb_label_name (temp
, 0);
6976 c
= *input_line_pointer
;
6985 /* Put ':' back for error messages' sake. */
6986 *input_line_pointer
++ = ':';
6987 as_bad ("Expected ':'");
6994 /* Put ':' back for error messages' sake. */
6995 *input_line_pointer
++ = ':';
6996 if (*input_line_pointer
++ != ']')
6998 as_bad ("Expected ']'");
7003 as_bad ("Tag name expected");
7013 /* Not a valid line. */
7018 ia64_frob_label (sym
)
7021 struct label_fix
*fix
;
7023 /* Tags need special handling since they are not bundle breaks like
7027 fix
= obstack_alloc (¬es
, sizeof (*fix
));
7029 fix
->next
= CURR_SLOT
.tag_fixups
;
7030 CURR_SLOT
.tag_fixups
= fix
;
7035 if (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
7037 md
.last_text_seg
= now_seg
;
7038 fix
= obstack_alloc (¬es
, sizeof (*fix
));
7040 fix
->next
= CURR_SLOT
.label_fixups
;
7041 CURR_SLOT
.label_fixups
= fix
;
7043 /* Keep track of how many code entry points we've seen. */
7044 if (md
.path
== md
.maxpaths
)
7047 md
.entry_labels
= (const char **)
7048 xrealloc ((void *) md
.entry_labels
,
7049 md
.maxpaths
* sizeof (char *));
7051 md
.entry_labels
[md
.path
++] = S_GET_NAME (sym
);
7056 ia64_flush_pending_output ()
7058 if (!md
.keep_pending_output
7059 && bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
)
7061 /* ??? This causes many unnecessary stop bits to be emitted.
7062 Unfortunately, it isn't clear if it is safe to remove this. */
7063 insn_group_break (1, 0, 0);
7064 ia64_flush_insns ();
7068 /* Do ia64-specific expression optimization. All that's done here is
7069 to transform index expressions that are either due to the indexing
7070 of rotating registers or due to the indexing of indirect register
7073 ia64_optimize_expr (l
, op
, r
)
7082 if (l
->X_op
== O_register
&& r
->X_op
== O_constant
)
7084 num_regs
= (l
->X_add_number
>> 16);
7085 if ((unsigned) r
->X_add_number
>= num_regs
)
7088 as_bad ("No current frame");
7090 as_bad ("Index out of range 0..%u", num_regs
- 1);
7091 r
->X_add_number
= 0;
7093 l
->X_add_number
= (l
->X_add_number
& 0xffff) + r
->X_add_number
;
7096 else if (l
->X_op
== O_register
&& r
->X_op
== O_register
)
7098 if (l
->X_add_number
< IND_CPUID
|| l
->X_add_number
> IND_RR
7099 || l
->X_add_number
== IND_MEM
)
7101 as_bad ("Indirect register set name expected");
7102 l
->X_add_number
= IND_CPUID
;
7105 l
->X_op_symbol
= md
.regsym
[l
->X_add_number
];
7106 l
->X_add_number
= r
->X_add_number
;
7114 ia64_parse_name (name
, e
)
7118 struct const_desc
*cdesc
;
7119 struct dynreg
*dr
= 0;
7120 unsigned int regnum
;
7124 /* first see if NAME is a known register name: */
7125 sym
= hash_find (md
.reg_hash
, name
);
7128 e
->X_op
= O_register
;
7129 e
->X_add_number
= S_GET_VALUE (sym
);
7133 cdesc
= hash_find (md
.const_hash
, name
);
7136 e
->X_op
= O_constant
;
7137 e
->X_add_number
= cdesc
->value
;
7141 /* check for inN, locN, or outN: */
7145 if (name
[1] == 'n' && ISDIGIT (name
[2]))
7153 if (name
[1] == 'o' && name
[2] == 'c' && ISDIGIT (name
[3]))
7161 if (name
[1] == 'u' && name
[2] == 't' && ISDIGIT (name
[3]))
7174 /* The name is inN, locN, or outN; parse the register number. */
7175 regnum
= strtoul (name
, &end
, 10);
7176 if (end
> name
&& *end
== '\0')
7178 if ((unsigned) regnum
>= dr
->num_regs
)
7181 as_bad ("No current frame");
7183 as_bad ("Register number out of range 0..%u",
7187 e
->X_op
= O_register
;
7188 e
->X_add_number
= dr
->base
+ regnum
;
7193 if ((dr
= hash_find (md
.dynreg_hash
, name
)))
7195 /* We've got ourselves the name of a rotating register set.
7196 Store the base register number in the low 16 bits of
7197 X_add_number and the size of the register set in the top 16
7199 e
->X_op
= O_register
;
7200 e
->X_add_number
= dr
->base
| (dr
->num_regs
<< 16);
7206 /* Remove the '#' suffix that indicates a symbol as opposed to a register. */
7209 ia64_canonicalize_symbol_name (name
)
7212 size_t len
= strlen (name
);
7213 if (len
> 1 && name
[len
- 1] == '#')
7214 name
[len
- 1] = '\0';
7218 /* Return true if idesc is a conditional branch instruction. This excludes
7219 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded
7220 because they always read/write resources regardless of the value of the
7221 qualifying predicate. br.ia must always use p0, and hence is always
7222 taken. Thus this function returns true for branches which can fall
7223 through, and which use no resources if they do fall through. */
7226 is_conditional_branch (idesc
)
7227 struct ia64_opcode
*idesc
;
7229 /* br is a conditional branch. Everything that starts with br. except
7230 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch.
7231 Everything that starts with brl is a conditional branch. */
7232 return (idesc
->name
[0] == 'b' && idesc
->name
[1] == 'r'
7233 && (idesc
->name
[2] == '\0'
7234 || (idesc
->name
[2] == '.' && idesc
->name
[3] != 'i'
7235 && idesc
->name
[3] != 'c' && idesc
->name
[3] != 'w')
7236 || idesc
->name
[2] == 'l'
7237 /* br.cond, br.call, br.clr */
7238 || (idesc
->name
[2] == '.' && idesc
->name
[3] == 'c'
7239 && (idesc
->name
[4] == 'a' || idesc
->name
[4] == 'o'
7240 || (idesc
->name
[4] == 'l' && idesc
->name
[5] == 'r')))));
7243 /* Return whether the given opcode is a taken branch. If there's any doubt,
7247 is_taken_branch (idesc
)
7248 struct ia64_opcode
*idesc
;
7250 return ((is_conditional_branch (idesc
) && CURR_SLOT
.qp_regno
== 0)
7251 || strncmp (idesc
->name
, "br.ia", 5) == 0);
7254 /* Return whether the given opcode is an interruption or rfi. If there's any
7255 doubt, returns zero. */
7258 is_interruption_or_rfi (idesc
)
7259 struct ia64_opcode
*idesc
;
7261 if (strcmp (idesc
->name
, "rfi") == 0)
7266 /* Returns the index of the given dependency in the opcode's list of chks, or
7267 -1 if there is no dependency. */
7270 depends_on (depind
, idesc
)
7272 struct ia64_opcode
*idesc
;
7275 const struct ia64_opcode_dependency
*dep
= idesc
->dependencies
;
7276 for (i
= 0; i
< dep
->nchks
; i
++)
7278 if (depind
== DEP (dep
->chks
[i
]))
7284 /* Determine a set of specific resources used for a particular resource
7285 class. Returns the number of specific resources identified For those
7286 cases which are not determinable statically, the resource returned is
7289 Meanings of value in 'NOTE':
7290 1) only read/write when the register number is explicitly encoded in the
7292 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only
7293 accesses CFM when qualifying predicate is in the rotating region.
7294 3) general register value is used to specify an indirect register; not
7295 determinable statically.
7296 4) only read the given resource when bits 7:0 of the indirect index
7297 register value does not match the register number of the resource; not
7298 determinable statically.
7299 5) all rules are implementation specific.
7300 6) only when both the index specified by the reader and the index specified
7301 by the writer have the same value in bits 63:61; not determinable
7303 7) only access the specified resource when the corresponding mask bit is
7305 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is
7306 only read when these insns reference FR2-31
7307 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only
7308 written when these insns write FR32-127
7309 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the
7311 11) The target predicates are written independently of PR[qp], but source
7312 registers are only read if PR[qp] is true. Since the state of PR[qp]
7313 cannot statically be determined, all source registers are marked used.
7314 12) This insn only reads the specified predicate register when that
7315 register is the PR[qp].
7316 13) This reference to ld-c only applies to teh GR whose value is loaded
7317 with data returned from memory, not the post-incremented address register.
7318 14) The RSE resource includes the implementation-specific RSE internal
7319 state resources. At least one (and possibly more) of these resources are
7320 read by each instruction listed in IC:rse-readers. At least one (and
7321 possibly more) of these resources are written by each insn listed in
7323 15+16) Represents reserved instructions, which the assembler does not
7326 Memory resources (i.e. locations in memory) are *not* marked or tracked by
7327 this code; there are no dependency violations based on memory access.
7330 #define MAX_SPECS 256
7335 specify_resource (dep
, idesc
, type
, specs
, note
, path
)
7336 const struct ia64_dependency
*dep
;
7337 struct ia64_opcode
*idesc
;
7338 int type
; /* is this a DV chk or a DV reg? */
7339 struct rsrc specs
[MAX_SPECS
]; /* returned specific resources */
7340 int note
; /* resource note for this insn's usage */
7341 int path
; /* which execution path to examine */
7348 if (dep
->mode
== IA64_DV_WAW
7349 || (dep
->mode
== IA64_DV_RAW
&& type
== DV_REG
)
7350 || (dep
->mode
== IA64_DV_WAR
&& type
== DV_CHK
))
7353 /* template for any resources we identify */
7354 tmpl
.dependency
= dep
;
7356 tmpl
.insn_srlz
= tmpl
.data_srlz
= 0;
7357 tmpl
.qp_regno
= CURR_SLOT
.qp_regno
;
7358 tmpl
.link_to_qp_branch
= 1;
7359 tmpl
.mem_offset
.hint
= 0;
7362 tmpl
.cmp_type
= CMP_NONE
;
7365 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
7366 dep->name, idesc->name, (rsrc_write?"write":"read"), note)
7367 #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path)
7369 /* we don't need to track these */
7370 if (dep
->semantics
== IA64_DVS_NONE
)
7373 switch (dep
->specifier
)
7378 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7380 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7381 if (regno
>= 0 && regno
<= 7)
7383 specs
[count
] = tmpl
;
7384 specs
[count
++].index
= regno
;
7390 for (i
= 0; i
< 8; i
++)
7392 specs
[count
] = tmpl
;
7393 specs
[count
++].index
= i
;
7402 case IA64_RS_AR_UNAT
:
7403 /* This is a mov =AR or mov AR= instruction. */
7404 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7406 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7407 if (regno
== AR_UNAT
)
7409 specs
[count
++] = tmpl
;
7414 /* This is a spill/fill, or other instruction that modifies the
7417 /* Unless we can determine the specific bits used, mark the whole
7418 thing; bits 8:3 of the memory address indicate the bit used in
7419 UNAT. The .mem.offset hint may be used to eliminate a small
7420 subset of conflicts. */
7421 specs
[count
] = tmpl
;
7422 if (md
.mem_offset
.hint
)
7425 fprintf (stderr
, " Using hint for spill/fill\n");
7426 /* The index isn't actually used, just set it to something
7427 approximating the bit index. */
7428 specs
[count
].index
= (md
.mem_offset
.offset
>> 3) & 0x3F;
7429 specs
[count
].mem_offset
.hint
= 1;
7430 specs
[count
].mem_offset
.offset
= md
.mem_offset
.offset
;
7431 specs
[count
++].mem_offset
.base
= md
.mem_offset
.base
;
7435 specs
[count
++].specific
= 0;
7443 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7445 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7446 if ((regno
>= 8 && regno
<= 15)
7447 || (regno
>= 20 && regno
<= 23)
7448 || (regno
>= 31 && regno
<= 39)
7449 || (regno
>= 41 && regno
<= 47)
7450 || (regno
>= 67 && regno
<= 111))
7452 specs
[count
] = tmpl
;
7453 specs
[count
++].index
= regno
;
7466 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
7468 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
7469 if ((regno
>= 48 && regno
<= 63)
7470 || (regno
>= 112 && regno
<= 127))
7472 specs
[count
] = tmpl
;
7473 specs
[count
++].index
= regno
;
7479 for (i
= 48; i
< 64; i
++)
7481 specs
[count
] = tmpl
;
7482 specs
[count
++].index
= i
;
7484 for (i
= 112; i
< 128; i
++)
7486 specs
[count
] = tmpl
;
7487 specs
[count
++].index
= i
;
7505 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7506 if (idesc
->operands
[i
] == IA64_OPND_B1
7507 || idesc
->operands
[i
] == IA64_OPND_B2
)
7509 specs
[count
] = tmpl
;
7510 specs
[count
++].index
=
7511 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7516 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7517 if (idesc
->operands
[i
] == IA64_OPND_B1
7518 || idesc
->operands
[i
] == IA64_OPND_B2
)
7520 specs
[count
] = tmpl
;
7521 specs
[count
++].index
=
7522 CURR_SLOT
.opnd
[i
].X_add_number
- REG_BR
;
7528 case IA64_RS_CPUID
: /* four or more registers */
7531 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CPUID_R3
)
7533 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7534 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7537 specs
[count
] = tmpl
;
7538 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7542 specs
[count
] = tmpl
;
7543 specs
[count
++].specific
= 0;
7553 case IA64_RS_DBR
: /* four or more registers */
7556 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_DBR_R3
)
7558 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7559 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7562 specs
[count
] = tmpl
;
7563 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7567 specs
[count
] = tmpl
;
7568 specs
[count
++].specific
= 0;
7572 else if (note
== 0 && !rsrc_write
)
7574 specs
[count
] = tmpl
;
7575 specs
[count
++].specific
= 0;
7583 case IA64_RS_IBR
: /* four or more registers */
7586 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_IBR_R3
)
7588 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7589 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7592 specs
[count
] = tmpl
;
7593 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7597 specs
[count
] = tmpl
;
7598 specs
[count
++].specific
= 0;
7611 /* These are implementation specific. Force all references to
7612 conflict with all other references. */
7613 specs
[count
] = tmpl
;
7614 specs
[count
++].specific
= 0;
7622 case IA64_RS_PKR
: /* 16 or more registers */
7623 if (note
== 3 || note
== 4)
7625 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PKR_R3
)
7627 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7628 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7633 specs
[count
] = tmpl
;
7634 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7637 for (i
= 0; i
< NELEMS (gr_values
); i
++)
7639 /* Uses all registers *except* the one in R3. */
7640 if ((unsigned)i
!= (gr_values
[regno
].value
& 0xFF))
7642 specs
[count
] = tmpl
;
7643 specs
[count
++].index
= i
;
7649 specs
[count
] = tmpl
;
7650 specs
[count
++].specific
= 0;
7657 specs
[count
] = tmpl
;
7658 specs
[count
++].specific
= 0;
7662 case IA64_RS_PMC
: /* four or more registers */
7665 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMC_R3
7666 || (!rsrc_write
&& idesc
->operands
[1] == IA64_OPND_PMD_R3
))
7669 int index
= ((idesc
->operands
[1] == IA64_OPND_R3
&& !rsrc_write
)
7671 int regno
= CURR_SLOT
.opnd
[index
].X_add_number
- REG_GR
;
7672 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7675 specs
[count
] = tmpl
;
7676 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7680 specs
[count
] = tmpl
;
7681 specs
[count
++].specific
= 0;
7691 case IA64_RS_PMD
: /* four or more registers */
7694 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PMD_R3
)
7696 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7697 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7700 specs
[count
] = tmpl
;
7701 specs
[count
++].index
= gr_values
[regno
].value
& 0xFF;
7705 specs
[count
] = tmpl
;
7706 specs
[count
++].specific
= 0;
7716 case IA64_RS_RR
: /* eight registers */
7719 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_RR_R3
)
7721 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_GR
;
7722 if (regno
>= 0 && regno
< NELEMS (gr_values
)
7725 specs
[count
] = tmpl
;
7726 specs
[count
++].index
= (gr_values
[regno
].value
>> 61) & 0x7;
7730 specs
[count
] = tmpl
;
7731 specs
[count
++].specific
= 0;
7735 else if (note
== 0 && !rsrc_write
)
7737 specs
[count
] = tmpl
;
7738 specs
[count
++].specific
= 0;
7746 case IA64_RS_CR_IRR
:
7749 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */
7750 int regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
;
7752 && idesc
->operands
[1] == IA64_OPND_CR3
7755 for (i
= 0; i
< 4; i
++)
7757 specs
[count
] = tmpl
;
7758 specs
[count
++].index
= CR_IRR0
+ i
;
7764 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7765 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7767 && regno
<= CR_IRR3
)
7769 specs
[count
] = tmpl
;
7770 specs
[count
++].index
= regno
;
7779 case IA64_RS_CR_LRR
:
7786 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7787 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
7788 && (regno
== CR_LRR0
|| regno
== CR_LRR1
))
7790 specs
[count
] = tmpl
;
7791 specs
[count
++].index
= regno
;
7799 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
7801 specs
[count
] = tmpl
;
7802 specs
[count
++].index
=
7803 CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
7818 else if (rsrc_write
)
7820 if (dep
->specifier
== IA64_RS_FRb
7821 && idesc
->operands
[0] == IA64_OPND_F1
)
7823 specs
[count
] = tmpl
;
7824 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_FR
;
7829 for (i
= idesc
->num_outputs
; i
< NELEMS (idesc
->operands
); i
++)
7831 if (idesc
->operands
[i
] == IA64_OPND_F2
7832 || idesc
->operands
[i
] == IA64_OPND_F3
7833 || idesc
->operands
[i
] == IA64_OPND_F4
)
7835 specs
[count
] = tmpl
;
7836 specs
[count
++].index
=
7837 CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
7846 /* This reference applies only to the GR whose value is loaded with
7847 data returned from memory. */
7848 specs
[count
] = tmpl
;
7849 specs
[count
++].index
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
7855 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7856 if (idesc
->operands
[i
] == IA64_OPND_R1
7857 || idesc
->operands
[i
] == IA64_OPND_R2
7858 || idesc
->operands
[i
] == IA64_OPND_R3
)
7860 specs
[count
] = tmpl
;
7861 specs
[count
++].index
=
7862 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7864 if (idesc
->flags
& IA64_OPCODE_POSTINC
)
7865 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7866 if (idesc
->operands
[i
] == IA64_OPND_MR3
)
7868 specs
[count
] = tmpl
;
7869 specs
[count
++].index
=
7870 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7875 /* Look for anything that reads a GR. */
7876 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
7878 if (idesc
->operands
[i
] == IA64_OPND_MR3
7879 || idesc
->operands
[i
] == IA64_OPND_CPUID_R3
7880 || idesc
->operands
[i
] == IA64_OPND_DBR_R3
7881 || idesc
->operands
[i
] == IA64_OPND_IBR_R3
7882 || idesc
->operands
[i
] == IA64_OPND_MSR_R3
7883 || idesc
->operands
[i
] == IA64_OPND_PKR_R3
7884 || idesc
->operands
[i
] == IA64_OPND_PMC_R3
7885 || idesc
->operands
[i
] == IA64_OPND_PMD_R3
7886 || idesc
->operands
[i
] == IA64_OPND_RR_R3
7887 || ((i
>= idesc
->num_outputs
)
7888 && (idesc
->operands
[i
] == IA64_OPND_R1
7889 || idesc
->operands
[i
] == IA64_OPND_R2
7890 || idesc
->operands
[i
] == IA64_OPND_R3
7891 /* addl source register. */
7892 || idesc
->operands
[i
] == IA64_OPND_R3_2
)))
7894 specs
[count
] = tmpl
;
7895 specs
[count
++].index
=
7896 CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
7907 /* This is the same as IA64_RS_PRr, except that the register range is
7908 from 1 - 15, and there are no rotating register reads/writes here. */
7912 for (i
= 1; i
< 16; i
++)
7914 specs
[count
] = tmpl
;
7915 specs
[count
++].index
= i
;
7921 /* Mark only those registers indicated by the mask. */
7924 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
7925 for (i
= 1; i
< 16; i
++)
7926 if (mask
& ((valueT
) 1 << i
))
7928 specs
[count
] = tmpl
;
7929 specs
[count
++].index
= i
;
7937 else if (note
== 11) /* note 11 implies note 1 as well */
7941 for (i
= 0; i
< idesc
->num_outputs
; i
++)
7943 if (idesc
->operands
[i
] == IA64_OPND_P1
7944 || idesc
->operands
[i
] == IA64_OPND_P2
)
7946 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
7947 if (regno
>= 1 && regno
< 16)
7949 specs
[count
] = tmpl
;
7950 specs
[count
++].index
= regno
;
7960 else if (note
== 12)
7962 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
7964 specs
[count
] = tmpl
;
7965 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
7972 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
7973 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
7974 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
7975 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
7977 if ((idesc
->operands
[0] == IA64_OPND_P1
7978 || idesc
->operands
[0] == IA64_OPND_P2
)
7979 && p1
>= 1 && p1
< 16)
7981 specs
[count
] = tmpl
;
7982 specs
[count
].cmp_type
=
7983 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
7984 specs
[count
++].index
= p1
;
7986 if ((idesc
->operands
[1] == IA64_OPND_P1
7987 || idesc
->operands
[1] == IA64_OPND_P2
)
7988 && p2
>= 1 && p2
< 16)
7990 specs
[count
] = tmpl
;
7991 specs
[count
].cmp_type
=
7992 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
7993 specs
[count
++].index
= p2
;
7998 if (CURR_SLOT
.qp_regno
>= 1 && CURR_SLOT
.qp_regno
< 16)
8000 specs
[count
] = tmpl
;
8001 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8003 if (idesc
->operands
[1] == IA64_OPND_PR
)
8005 for (i
= 1; i
< 16; i
++)
8007 specs
[count
] = tmpl
;
8008 specs
[count
++].index
= i
;
8019 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are
8020 simplified cases of this. */
8024 for (i
= 16; i
< 63; i
++)
8026 specs
[count
] = tmpl
;
8027 specs
[count
++].index
= i
;
8033 /* Mark only those registers indicated by the mask. */
8035 && idesc
->operands
[0] == IA64_OPND_PR
)
8037 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8038 if (mask
& ((valueT
) 1 << 16))
8039 for (i
= 16; i
< 63; i
++)
8041 specs
[count
] = tmpl
;
8042 specs
[count
++].index
= i
;
8046 && idesc
->operands
[0] == IA64_OPND_PR_ROT
)
8048 for (i
= 16; i
< 63; i
++)
8050 specs
[count
] = tmpl
;
8051 specs
[count
++].index
= i
;
8059 else if (note
== 11) /* note 11 implies note 1 as well */
8063 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8065 if (idesc
->operands
[i
] == IA64_OPND_P1
8066 || idesc
->operands
[i
] == IA64_OPND_P2
)
8068 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8069 if (regno
>= 16 && regno
< 63)
8071 specs
[count
] = tmpl
;
8072 specs
[count
++].index
= regno
;
8082 else if (note
== 12)
8084 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
8086 specs
[count
] = tmpl
;
8087 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8094 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8095 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8096 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8097 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8099 if ((idesc
->operands
[0] == IA64_OPND_P1
8100 || idesc
->operands
[0] == IA64_OPND_P2
)
8101 && p1
>= 16 && p1
< 63)
8103 specs
[count
] = tmpl
;
8104 specs
[count
].cmp_type
=
8105 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8106 specs
[count
++].index
= p1
;
8108 if ((idesc
->operands
[1] == IA64_OPND_P1
8109 || idesc
->operands
[1] == IA64_OPND_P2
)
8110 && p2
>= 16 && p2
< 63)
8112 specs
[count
] = tmpl
;
8113 specs
[count
].cmp_type
=
8114 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8115 specs
[count
++].index
= p2
;
8120 if (CURR_SLOT
.qp_regno
>= 16 && CURR_SLOT
.qp_regno
< 63)
8122 specs
[count
] = tmpl
;
8123 specs
[count
++].index
= CURR_SLOT
.qp_regno
;
8125 if (idesc
->operands
[1] == IA64_OPND_PR
)
8127 for (i
= 16; i
< 63; i
++)
8129 specs
[count
] = tmpl
;
8130 specs
[count
++].index
= i
;
8142 /* Verify that the instruction is using the PSR bit indicated in
8146 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_UM
)
8148 if (dep
->regindex
< 6)
8150 specs
[count
++] = tmpl
;
8153 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR
)
8155 if (dep
->regindex
< 32
8156 || dep
->regindex
== 35
8157 || dep
->regindex
== 36
8158 || (!rsrc_write
&& dep
->regindex
== PSR_CPL
))
8160 specs
[count
++] = tmpl
;
8163 else if (idesc
->operands
[!rsrc_write
] == IA64_OPND_PSR_L
)
8165 if (dep
->regindex
< 32
8166 || dep
->regindex
== 35
8167 || dep
->regindex
== 36
8168 || (rsrc_write
&& dep
->regindex
== PSR_CPL
))
8170 specs
[count
++] = tmpl
;
8175 /* Several PSR bits have very specific dependencies. */
8176 switch (dep
->regindex
)
8179 specs
[count
++] = tmpl
;
8184 specs
[count
++] = tmpl
;
8188 /* Only certain CR accesses use PSR.ic */
8189 if (idesc
->operands
[0] == IA64_OPND_CR3
8190 || idesc
->operands
[1] == IA64_OPND_CR3
)
8193 ((idesc
->operands
[0] == IA64_OPND_CR3
)
8196 CURR_SLOT
.opnd
[index
].X_add_number
- REG_CR
;
8211 specs
[count
++] = tmpl
;
8220 specs
[count
++] = tmpl
;
8224 /* Only some AR accesses use cpl */
8225 if (idesc
->operands
[0] == IA64_OPND_AR3
8226 || idesc
->operands
[1] == IA64_OPND_AR3
)
8229 ((idesc
->operands
[0] == IA64_OPND_AR3
)
8232 CURR_SLOT
.opnd
[index
].X_add_number
- REG_AR
;
8239 && regno
<= AR_K7
))))
8241 specs
[count
++] = tmpl
;
8246 specs
[count
++] = tmpl
;
8256 if (idesc
->operands
[0] == IA64_OPND_IMMU24
)
8258 mask
= CURR_SLOT
.opnd
[0].X_add_number
;
8264 if (mask
& ((valueT
) 1 << dep
->regindex
))
8266 specs
[count
++] = tmpl
;
8271 int min
= dep
->regindex
== PSR_DFL
? 2 : 32;
8272 int max
= dep
->regindex
== PSR_DFL
? 31 : 127;
8273 /* dfh is read on FR32-127; dfl is read on FR2-31 */
8274 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8276 if (idesc
->operands
[i
] == IA64_OPND_F1
8277 || idesc
->operands
[i
] == IA64_OPND_F2
8278 || idesc
->operands
[i
] == IA64_OPND_F3
8279 || idesc
->operands
[i
] == IA64_OPND_F4
)
8281 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8282 if (reg
>= min
&& reg
<= max
)
8284 specs
[count
++] = tmpl
;
8291 int min
= dep
->regindex
== PSR_MFL
? 2 : 32;
8292 int max
= dep
->regindex
== PSR_MFL
? 31 : 127;
8293 /* mfh is read on writes to FR32-127; mfl is read on writes to
8295 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8297 if (idesc
->operands
[i
] == IA64_OPND_F1
)
8299 int reg
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8300 if (reg
>= min
&& reg
<= max
)
8302 specs
[count
++] = tmpl
;
8307 else if (note
== 10)
8309 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8311 if (idesc
->operands
[i
] == IA64_OPND_R1
8312 || idesc
->operands
[i
] == IA64_OPND_R2
8313 || idesc
->operands
[i
] == IA64_OPND_R3
)
8315 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8316 if (regno
>= 16 && regno
<= 31)
8318 specs
[count
++] = tmpl
;
8329 case IA64_RS_AR_FPSR
:
8330 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
)
8332 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8333 if (regno
== AR_FPSR
)
8335 specs
[count
++] = tmpl
;
8340 specs
[count
++] = tmpl
;
8345 /* Handle all AR[REG] resources */
8346 if (note
== 0 || note
== 1)
8348 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_AR
;
8349 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_AR3
8350 && regno
== dep
->regindex
)
8352 specs
[count
++] = tmpl
;
8354 /* other AR[REG] resources may be affected by AR accesses */
8355 else if (idesc
->operands
[0] == IA64_OPND_AR3
)
8358 regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
;
8359 switch (dep
->regindex
)
8365 if (regno
== AR_BSPSTORE
)
8367 specs
[count
++] = tmpl
;
8371 (regno
== AR_BSPSTORE
8372 || regno
== AR_RNAT
))
8374 specs
[count
++] = tmpl
;
8379 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8382 regno
= CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
;
8383 switch (dep
->regindex
)
8388 if (regno
== AR_BSPSTORE
|| regno
== AR_RNAT
)
8390 specs
[count
++] = tmpl
;
8397 specs
[count
++] = tmpl
;
8407 /* Handle all CR[REG] resources */
8408 if (note
== 0 || note
== 1)
8410 if (idesc
->operands
[!rsrc_write
] == IA64_OPND_CR3
)
8412 int regno
= CURR_SLOT
.opnd
[!rsrc_write
].X_add_number
- REG_CR
;
8413 if (regno
== dep
->regindex
)
8415 specs
[count
++] = tmpl
;
8417 else if (!rsrc_write
)
8419 /* Reads from CR[IVR] affect other resources. */
8420 if (regno
== CR_IVR
)
8422 if ((dep
->regindex
>= CR_IRR0
8423 && dep
->regindex
<= CR_IRR3
)
8424 || dep
->regindex
== CR_TPR
)
8426 specs
[count
++] = tmpl
;
8433 specs
[count
++] = tmpl
;
8442 case IA64_RS_INSERVICE
:
8443 /* look for write of EOI (67) or read of IVR (65) */
8444 if ((idesc
->operands
[0] == IA64_OPND_CR3
8445 && CURR_SLOT
.opnd
[0].X_add_number
- REG_CR
== CR_EOI
)
8446 || (idesc
->operands
[1] == IA64_OPND_CR3
8447 && CURR_SLOT
.opnd
[1].X_add_number
- REG_CR
== CR_IVR
))
8449 specs
[count
++] = tmpl
;
8456 specs
[count
++] = tmpl
;
8467 specs
[count
++] = tmpl
;
8471 /* Check if any of the registers accessed are in the rotating region.
8472 mov to/from pr accesses CFM only when qp_regno is in the rotating
8474 for (i
= 0; i
< NELEMS (idesc
->operands
); i
++)
8476 if (idesc
->operands
[i
] == IA64_OPND_R1
8477 || idesc
->operands
[i
] == IA64_OPND_R2
8478 || idesc
->operands
[i
] == IA64_OPND_R3
)
8480 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8481 /* Assumes that md.rot.num_regs is always valid */
8482 if (md
.rot
.num_regs
> 0
8484 && num
< 31 + md
.rot
.num_regs
)
8486 specs
[count
] = tmpl
;
8487 specs
[count
++].specific
= 0;
8490 else if (idesc
->operands
[i
] == IA64_OPND_F1
8491 || idesc
->operands
[i
] == IA64_OPND_F2
8492 || idesc
->operands
[i
] == IA64_OPND_F3
8493 || idesc
->operands
[i
] == IA64_OPND_F4
)
8495 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_FR
;
8498 specs
[count
] = tmpl
;
8499 specs
[count
++].specific
= 0;
8502 else if (idesc
->operands
[i
] == IA64_OPND_P1
8503 || idesc
->operands
[i
] == IA64_OPND_P2
)
8505 int num
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8508 specs
[count
] = tmpl
;
8509 specs
[count
++].specific
= 0;
8513 if (CURR_SLOT
.qp_regno
> 15)
8515 specs
[count
] = tmpl
;
8516 specs
[count
++].specific
= 0;
8521 /* This is the same as IA64_RS_PRr, except simplified to account for
8522 the fact that there is only one register. */
8526 specs
[count
++] = tmpl
;
8531 if (idesc
->operands
[2] == IA64_OPND_IMM17
)
8532 mask
= CURR_SLOT
.opnd
[2].X_add_number
;
8533 if (mask
& ((valueT
) 1 << 63))
8534 specs
[count
++] = tmpl
;
8536 else if (note
== 11)
8538 if ((idesc
->operands
[0] == IA64_OPND_P1
8539 && CURR_SLOT
.opnd
[0].X_add_number
- REG_P
== 63)
8540 || (idesc
->operands
[1] == IA64_OPND_P2
8541 && CURR_SLOT
.opnd
[1].X_add_number
- REG_P
== 63))
8543 specs
[count
++] = tmpl
;
8546 else if (note
== 12)
8548 if (CURR_SLOT
.qp_regno
== 63)
8550 specs
[count
++] = tmpl
;
8557 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8558 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8559 int or_andcm
= strstr (idesc
->name
, "or.andcm") != NULL
;
8560 int and_orcm
= strstr (idesc
->name
, "and.orcm") != NULL
;
8563 && (idesc
->operands
[0] == IA64_OPND_P1
8564 || idesc
->operands
[0] == IA64_OPND_P2
))
8566 specs
[count
] = tmpl
;
8567 specs
[count
++].cmp_type
=
8568 (or_andcm
? CMP_OR
: (and_orcm
? CMP_AND
: CMP_NONE
));
8571 && (idesc
->operands
[1] == IA64_OPND_P1
8572 || idesc
->operands
[1] == IA64_OPND_P2
))
8574 specs
[count
] = tmpl
;
8575 specs
[count
++].cmp_type
=
8576 (or_andcm
? CMP_AND
: (and_orcm
? CMP_OR
: CMP_NONE
));
8581 if (CURR_SLOT
.qp_regno
== 63)
8583 specs
[count
++] = tmpl
;
8594 /* FIXME we can identify some individual RSE written resources, but RSE
8595 read resources have not yet been completely identified, so for now
8596 treat RSE as a single resource */
8597 if (strncmp (idesc
->name
, "mov", 3) == 0)
8601 if (idesc
->operands
[0] == IA64_OPND_AR3
8602 && CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
)
8604 specs
[count
] = tmpl
;
8605 specs
[count
++].index
= 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
8610 if (idesc
->operands
[0] == IA64_OPND_AR3
)
8612 if (CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_BSPSTORE
8613 || CURR_SLOT
.opnd
[0].X_add_number
- REG_AR
== AR_RNAT
)
8615 specs
[count
++] = tmpl
;
8618 else if (idesc
->operands
[1] == IA64_OPND_AR3
)
8620 if (CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSP
8621 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_BSPSTORE
8622 || CURR_SLOT
.opnd
[1].X_add_number
- REG_AR
== AR_RNAT
)
8624 specs
[count
++] = tmpl
;
8631 specs
[count
++] = tmpl
;
8636 /* FIXME -- do any of these need to be non-specific? */
8637 specs
[count
++] = tmpl
;
8641 as_bad (_("Unrecognized dependency specifier %d\n"), dep
->specifier
);
8648 /* Clear branch flags on marked resources. This breaks the link between the
8649 QP of the marking instruction and a subsequent branch on the same QP. */
8652 clear_qp_branch_flag (mask
)
8656 for (i
= 0; i
< regdepslen
; i
++)
8658 valueT bit
= ((valueT
) 1 << regdeps
[i
].qp_regno
);
8659 if ((bit
& mask
) != 0)
8661 regdeps
[i
].link_to_qp_branch
= 0;
8666 /* Remove any mutexes which contain any of the PRs indicated in the mask.
8668 Any changes to a PR clears the mutex relations which include that PR. */
8671 clear_qp_mutex (mask
)
8677 while (i
< qp_mutexeslen
)
8679 if ((qp_mutexes
[i
].prmask
& mask
) != 0)
8683 fprintf (stderr
, " Clearing mutex relation");
8684 print_prmask (qp_mutexes
[i
].prmask
);
8685 fprintf (stderr
, "\n");
8687 qp_mutexes
[i
] = qp_mutexes
[--qp_mutexeslen
];
8694 /* Clear implies relations which contain PRs in the given masks.
8695 P1_MASK indicates the source of the implies relation, while P2_MASK
8696 indicates the implied PR. */
8699 clear_qp_implies (p1_mask
, p2_mask
)
8706 while (i
< qp_implieslen
)
8708 if ((((valueT
) 1 << qp_implies
[i
].p1
) & p1_mask
) != 0
8709 || (((valueT
) 1 << qp_implies
[i
].p2
) & p2_mask
) != 0)
8712 fprintf (stderr
, "Clearing implied relation PR%d->PR%d\n",
8713 qp_implies
[i
].p1
, qp_implies
[i
].p2
);
8714 qp_implies
[i
] = qp_implies
[--qp_implieslen
];
8721 /* Add the PRs specified to the list of implied relations. */
8724 add_qp_imply (p1
, p2
)
8731 /* p0 is not meaningful here. */
8732 if (p1
== 0 || p2
== 0)
8738 /* If it exists already, ignore it. */
8739 for (i
= 0; i
< qp_implieslen
; i
++)
8741 if (qp_implies
[i
].p1
== p1
8742 && qp_implies
[i
].p2
== p2
8743 && qp_implies
[i
].path
== md
.path
8744 && !qp_implies
[i
].p2_branched
)
8748 if (qp_implieslen
== qp_impliestotlen
)
8750 qp_impliestotlen
+= 20;
8751 qp_implies
= (struct qp_imply
*)
8752 xrealloc ((void *) qp_implies
,
8753 qp_impliestotlen
* sizeof (struct qp_imply
));
8756 fprintf (stderr
, " Registering PR%d implies PR%d\n", p1
, p2
);
8757 qp_implies
[qp_implieslen
].p1
= p1
;
8758 qp_implies
[qp_implieslen
].p2
= p2
;
8759 qp_implies
[qp_implieslen
].path
= md
.path
;
8760 qp_implies
[qp_implieslen
++].p2_branched
= 0;
8762 /* Add in the implied transitive relations; for everything that p2 implies,
8763 make p1 imply that, too; for everything that implies p1, make it imply p2
8765 for (i
= 0; i
< qp_implieslen
; i
++)
8767 if (qp_implies
[i
].p1
== p2
)
8768 add_qp_imply (p1
, qp_implies
[i
].p2
);
8769 if (qp_implies
[i
].p2
== p1
)
8770 add_qp_imply (qp_implies
[i
].p1
, p2
);
8772 /* Add in mutex relations implied by this implies relation; for each mutex
8773 relation containing p2, duplicate it and replace p2 with p1. */
8774 bit
= (valueT
) 1 << p1
;
8775 mask
= (valueT
) 1 << p2
;
8776 for (i
= 0; i
< qp_mutexeslen
; i
++)
8778 if (qp_mutexes
[i
].prmask
& mask
)
8779 add_qp_mutex ((qp_mutexes
[i
].prmask
& ~mask
) | bit
);
8783 /* Add the PRs specified in the mask to the mutex list; this means that only
8784 one of the PRs can be true at any time. PR0 should never be included in
8794 if (qp_mutexeslen
== qp_mutexestotlen
)
8796 qp_mutexestotlen
+= 20;
8797 qp_mutexes
= (struct qpmutex
*)
8798 xrealloc ((void *) qp_mutexes
,
8799 qp_mutexestotlen
* sizeof (struct qpmutex
));
8803 fprintf (stderr
, " Registering mutex on");
8804 print_prmask (mask
);
8805 fprintf (stderr
, "\n");
8807 qp_mutexes
[qp_mutexeslen
].path
= md
.path
;
8808 qp_mutexes
[qp_mutexeslen
++].prmask
= mask
;
8812 has_suffix_p (name
, suffix
)
8816 size_t namelen
= strlen (name
);
8817 size_t sufflen
= strlen (suffix
);
8819 if (namelen
<= sufflen
)
8821 return strcmp (name
+ namelen
- sufflen
, suffix
) == 0;
8825 clear_register_values ()
8829 fprintf (stderr
, " Clearing register values\n");
8830 for (i
= 1; i
< NELEMS (gr_values
); i
++)
8831 gr_values
[i
].known
= 0;
8834 /* Keep track of register values/changes which affect DV tracking.
8836 optimization note: should add a flag to classes of insns where otherwise we
8837 have to examine a group of strings to identify them. */
8840 note_register_values (idesc
)
8841 struct ia64_opcode
*idesc
;
8843 valueT qp_changemask
= 0;
8846 /* Invalidate values for registers being written to. */
8847 for (i
= 0; i
< idesc
->num_outputs
; i
++)
8849 if (idesc
->operands
[i
] == IA64_OPND_R1
8850 || idesc
->operands
[i
] == IA64_OPND_R2
8851 || idesc
->operands
[i
] == IA64_OPND_R3
)
8853 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8854 if (regno
> 0 && regno
< NELEMS (gr_values
))
8855 gr_values
[regno
].known
= 0;
8857 else if (idesc
->operands
[i
] == IA64_OPND_R3_2
)
8859 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_GR
;
8860 if (regno
> 0 && regno
< 4)
8861 gr_values
[regno
].known
= 0;
8863 else if (idesc
->operands
[i
] == IA64_OPND_P1
8864 || idesc
->operands
[i
] == IA64_OPND_P2
)
8866 int regno
= CURR_SLOT
.opnd
[i
].X_add_number
- REG_P
;
8867 qp_changemask
|= (valueT
) 1 << regno
;
8869 else if (idesc
->operands
[i
] == IA64_OPND_PR
)
8871 if (idesc
->operands
[2] & (valueT
) 0x10000)
8872 qp_changemask
= ~(valueT
) 0x1FFFF | idesc
->operands
[2];
8874 qp_changemask
= idesc
->operands
[2];
8877 else if (idesc
->operands
[i
] == IA64_OPND_PR_ROT
)
8879 if (idesc
->operands
[1] & ((valueT
) 1 << 43))
8880 qp_changemask
= ~(valueT
) 0xFFFFFFFFFFF | idesc
->operands
[1];
8882 qp_changemask
= idesc
->operands
[1];
8883 qp_changemask
&= ~(valueT
) 0xFFFF;
8888 /* Always clear qp branch flags on any PR change. */
8889 /* FIXME there may be exceptions for certain compares. */
8890 clear_qp_branch_flag (qp_changemask
);
8892 /* Invalidate rotating registers on insns which affect RRBs in CFM. */
8893 if (idesc
->flags
& IA64_OPCODE_MOD_RRBS
)
8895 qp_changemask
|= ~(valueT
) 0xFFFF;
8896 if (strcmp (idesc
->name
, "clrrrb.pr") != 0)
8898 for (i
= 32; i
< 32 + md
.rot
.num_regs
; i
++)
8899 gr_values
[i
].known
= 0;
8901 clear_qp_mutex (qp_changemask
);
8902 clear_qp_implies (qp_changemask
, qp_changemask
);
8904 /* After a call, all register values are undefined, except those marked
8906 else if (strncmp (idesc
->name
, "br.call", 6) == 0
8907 || strncmp (idesc
->name
, "brl.call", 7) == 0)
8909 /* FIXME keep GR values which are marked as "safe_across_calls" */
8910 clear_register_values ();
8911 clear_qp_mutex (~qp_safe_across_calls
);
8912 clear_qp_implies (~qp_safe_across_calls
, ~qp_safe_across_calls
);
8913 clear_qp_branch_flag (~qp_safe_across_calls
);
8915 else if (is_interruption_or_rfi (idesc
)
8916 || is_taken_branch (idesc
))
8918 clear_register_values ();
8919 clear_qp_mutex (~(valueT
) 0);
8920 clear_qp_implies (~(valueT
) 0, ~(valueT
) 0);
8922 /* Look for mutex and implies relations. */
8923 else if ((idesc
->operands
[0] == IA64_OPND_P1
8924 || idesc
->operands
[0] == IA64_OPND_P2
)
8925 && (idesc
->operands
[1] == IA64_OPND_P1
8926 || idesc
->operands
[1] == IA64_OPND_P2
))
8928 int p1
= CURR_SLOT
.opnd
[0].X_add_number
- REG_P
;
8929 int p2
= CURR_SLOT
.opnd
[1].X_add_number
- REG_P
;
8930 valueT p1mask
= (valueT
) 1 << p1
;
8931 valueT p2mask
= (valueT
) 1 << p2
;
8933 /* If one of the PRs is PR0, we can't really do anything. */
8934 if (p1
== 0 || p2
== 0)
8937 fprintf (stderr
, " Ignoring PRs due to inclusion of p0\n");
8939 /* In general, clear mutexes and implies which include P1 or P2,
8940 with the following exceptions. */
8941 else if (has_suffix_p (idesc
->name
, ".or.andcm")
8942 || has_suffix_p (idesc
->name
, ".and.orcm"))
8944 add_qp_mutex (p1mask
| p2mask
);
8945 clear_qp_implies (p2mask
, p1mask
);
8947 else if (has_suffix_p (idesc
->name
, ".andcm")
8948 || has_suffix_p (idesc
->name
, ".and"))
8950 clear_qp_implies (0, p1mask
| p2mask
);
8952 else if (has_suffix_p (idesc
->name
, ".orcm")
8953 || has_suffix_p (idesc
->name
, ".or"))
8955 clear_qp_mutex (p1mask
| p2mask
);
8956 clear_qp_implies (p1mask
| p2mask
, 0);
8960 clear_qp_implies (p1mask
| p2mask
, p1mask
| p2mask
);
8961 if (has_suffix_p (idesc
->name
, ".unc"))
8963 add_qp_mutex (p1mask
| p2mask
);
8964 if (CURR_SLOT
.qp_regno
!= 0)
8966 add_qp_imply (CURR_SLOT
.opnd
[0].X_add_number
- REG_P
,
8967 CURR_SLOT
.qp_regno
);
8968 add_qp_imply (CURR_SLOT
.opnd
[1].X_add_number
- REG_P
,
8969 CURR_SLOT
.qp_regno
);
8972 else if (CURR_SLOT
.qp_regno
== 0)
8974 add_qp_mutex (p1mask
| p2mask
);
8978 clear_qp_mutex (p1mask
| p2mask
);
8982 /* Look for mov imm insns into GRs. */
8983 else if (idesc
->operands
[0] == IA64_OPND_R1
8984 && (idesc
->operands
[1] == IA64_OPND_IMM22
8985 || idesc
->operands
[1] == IA64_OPND_IMMU64
)
8986 && (strcmp (idesc
->name
, "mov") == 0
8987 || strcmp (idesc
->name
, "movl") == 0))
8989 int regno
= CURR_SLOT
.opnd
[0].X_add_number
- REG_GR
;
8990 if (regno
> 0 && regno
< NELEMS (gr_values
))
8992 gr_values
[regno
].known
= 1;
8993 gr_values
[regno
].value
= CURR_SLOT
.opnd
[1].X_add_number
;
8994 gr_values
[regno
].path
= md
.path
;
8997 fprintf (stderr
, " Know gr%d = ", regno
);
8998 fprintf_vma (stderr
, gr_values
[regno
].value
);
8999 fputs ("\n", stderr
);
9005 clear_qp_mutex (qp_changemask
);
9006 clear_qp_implies (qp_changemask
, qp_changemask
);
9010 /* Return whether the given predicate registers are currently mutex. */
9013 qp_mutex (p1
, p2
, path
)
9023 mask
= ((valueT
) 1 << p1
) | (valueT
) 1 << p2
;
9024 for (i
= 0; i
< qp_mutexeslen
; i
++)
9026 if (qp_mutexes
[i
].path
>= path
9027 && (qp_mutexes
[i
].prmask
& mask
) == mask
)
9034 /* Return whether the given resource is in the given insn's list of chks
9035 Return 1 if the conflict is absolutely determined, 2 if it's a potential
9039 resources_match (rs
, idesc
, note
, qp_regno
, path
)
9041 struct ia64_opcode
*idesc
;
9046 struct rsrc specs
[MAX_SPECS
];
9049 /* If the marked resource's qp_regno and the given qp_regno are mutex,
9050 we don't need to check. One exception is note 11, which indicates that
9051 target predicates are written regardless of PR[qp]. */
9052 if (qp_mutex (rs
->qp_regno
, qp_regno
, path
)
9056 count
= specify_resource (rs
->dependency
, idesc
, DV_CHK
, specs
, note
, path
);
9059 /* UNAT checking is a bit more specific than other resources */
9060 if (rs
->dependency
->specifier
== IA64_RS_AR_UNAT
9061 && specs
[count
].mem_offset
.hint
9062 && rs
->mem_offset
.hint
)
9064 if (rs
->mem_offset
.base
== specs
[count
].mem_offset
.base
)
9066 if (((rs
->mem_offset
.offset
>> 3) & 0x3F) ==
9067 ((specs
[count
].mem_offset
.offset
>> 3) & 0x3F))
9074 /* Skip apparent PR write conflicts where both writes are an AND or both
9075 writes are an OR. */
9076 if (rs
->dependency
->specifier
== IA64_RS_PR
9077 || rs
->dependency
->specifier
== IA64_RS_PRr
9078 || rs
->dependency
->specifier
== IA64_RS_PR63
)
9080 if (specs
[count
].cmp_type
!= CMP_NONE
9081 && specs
[count
].cmp_type
== rs
->cmp_type
)
9084 fprintf (stderr
, " %s on parallel compare allowed (PR%d)\n",
9085 dv_mode
[rs
->dependency
->mode
],
9086 rs
->dependency
->specifier
!= IA64_RS_PR63
?
9087 specs
[count
].index
: 63);
9092 " %s on parallel compare conflict %s vs %s on PR%d\n",
9093 dv_mode
[rs
->dependency
->mode
],
9094 dv_cmp_type
[rs
->cmp_type
],
9095 dv_cmp_type
[specs
[count
].cmp_type
],
9096 rs
->dependency
->specifier
!= IA64_RS_PR63
?
9097 specs
[count
].index
: 63);
9101 /* If either resource is not specific, conservatively assume a conflict
9103 if (!specs
[count
].specific
|| !rs
->specific
)
9105 else if (specs
[count
].index
== rs
->index
)
9110 fprintf (stderr
, " No %s conflicts\n", rs
->dependency
->name
);
9116 /* Indicate an instruction group break; if INSERT_STOP is non-zero, then
9117 insert a stop to create the break. Update all resource dependencies
9118 appropriately. If QP_REGNO is non-zero, only apply the break to resources
9119 which use the same QP_REGNO and have the link_to_qp_branch flag set.
9120 If SAVE_CURRENT is non-zero, don't affect resources marked by the current
9124 insn_group_break (insert_stop
, qp_regno
, save_current
)
9131 if (insert_stop
&& md
.num_slots_in_use
> 0)
9132 PREV_SLOT
.end_of_insn_group
= 1;
9136 fprintf (stderr
, " Insn group break%s",
9137 (insert_stop
? " (w/stop)" : ""));
9139 fprintf (stderr
, " effective for QP=%d", qp_regno
);
9140 fprintf (stderr
, "\n");
9144 while (i
< regdepslen
)
9146 const struct ia64_dependency
*dep
= regdeps
[i
].dependency
;
9149 && regdeps
[i
].qp_regno
!= qp_regno
)
9156 && CURR_SLOT
.src_file
== regdeps
[i
].file
9157 && CURR_SLOT
.src_line
== regdeps
[i
].line
)
9163 /* clear dependencies which are automatically cleared by a stop, or
9164 those that have reached the appropriate state of insn serialization */
9165 if (dep
->semantics
== IA64_DVS_IMPLIED
9166 || dep
->semantics
== IA64_DVS_IMPLIEDF
9167 || regdeps
[i
].insn_srlz
== STATE_SRLZ
)
9169 print_dependency ("Removing", i
);
9170 regdeps
[i
] = regdeps
[--regdepslen
];
9174 if (dep
->semantics
== IA64_DVS_DATA
9175 || dep
->semantics
== IA64_DVS_INSTR
9176 || dep
->semantics
== IA64_DVS_SPECIFIC
)
9178 if (regdeps
[i
].insn_srlz
== STATE_NONE
)
9179 regdeps
[i
].insn_srlz
= STATE_STOP
;
9180 if (regdeps
[i
].data_srlz
== STATE_NONE
)
9181 regdeps
[i
].data_srlz
= STATE_STOP
;
9188 /* Add the given resource usage spec to the list of active dependencies. */
9191 mark_resource (idesc
, dep
, spec
, depind
, path
)
9192 struct ia64_opcode
*idesc ATTRIBUTE_UNUSED
;
9193 const struct ia64_dependency
*dep ATTRIBUTE_UNUSED
;
9198 if (regdepslen
== regdepstotlen
)
9200 regdepstotlen
+= 20;
9201 regdeps
= (struct rsrc
*)
9202 xrealloc ((void *) regdeps
,
9203 regdepstotlen
* sizeof (struct rsrc
));
9206 regdeps
[regdepslen
] = *spec
;
9207 regdeps
[regdepslen
].depind
= depind
;
9208 regdeps
[regdepslen
].path
= path
;
9209 regdeps
[regdepslen
].file
= CURR_SLOT
.src_file
;
9210 regdeps
[regdepslen
].line
= CURR_SLOT
.src_line
;
9212 print_dependency ("Adding", regdepslen
);
9218 print_dependency (action
, depind
)
9224 fprintf (stderr
, " %s %s '%s'",
9225 action
, dv_mode
[(regdeps
[depind
].dependency
)->mode
],
9226 (regdeps
[depind
].dependency
)->name
);
9227 if (regdeps
[depind
].specific
&& regdeps
[depind
].index
!= 0)
9228 fprintf (stderr
, " (%d)", regdeps
[depind
].index
);
9229 if (regdeps
[depind
].mem_offset
.hint
)
9231 fputs (" ", stderr
);
9232 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.base
);
9233 fputs ("+", stderr
);
9234 fprintf_vma (stderr
, regdeps
[depind
].mem_offset
.offset
);
9236 fprintf (stderr
, "\n");
9241 instruction_serialization ()
9245 fprintf (stderr
, " Instruction serialization\n");
9246 for (i
= 0; i
< regdepslen
; i
++)
9247 if (regdeps
[i
].insn_srlz
== STATE_STOP
)
9248 regdeps
[i
].insn_srlz
= STATE_SRLZ
;
9252 data_serialization ()
9256 fprintf (stderr
, " Data serialization\n");
9257 while (i
< regdepslen
)
9259 if (regdeps
[i
].data_srlz
== STATE_STOP
9260 /* Note: as of 991210, all "other" dependencies are cleared by a
9261 data serialization. This might change with new tables */
9262 || (regdeps
[i
].dependency
)->semantics
== IA64_DVS_OTHER
)
9264 print_dependency ("Removing", i
);
9265 regdeps
[i
] = regdeps
[--regdepslen
];
9272 /* Insert stops and serializations as needed to avoid DVs. */
9275 remove_marked_resource (rs
)
9278 switch (rs
->dependency
->semantics
)
9280 case IA64_DVS_SPECIFIC
:
9282 fprintf (stderr
, "Implementation-specific, assume worst case...\n");
9283 /* ...fall through... */
9284 case IA64_DVS_INSTR
:
9286 fprintf (stderr
, "Inserting instr serialization\n");
9287 if (rs
->insn_srlz
< STATE_STOP
)
9288 insn_group_break (1, 0, 0);
9289 if (rs
->insn_srlz
< STATE_SRLZ
)
9291 int oldqp
= CURR_SLOT
.qp_regno
;
9292 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9293 /* Manually jam a srlz.i insn into the stream */
9294 CURR_SLOT
.qp_regno
= 0;
9295 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.i");
9296 instruction_serialization ();
9297 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9298 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9300 CURR_SLOT
.qp_regno
= oldqp
;
9301 CURR_SLOT
.idesc
= oldidesc
;
9303 insn_group_break (1, 0, 0);
9305 case IA64_DVS_OTHER
: /* as of rev2 (991220) of the DV tables, all
9306 "other" types of DV are eliminated
9307 by a data serialization */
9310 fprintf (stderr
, "Inserting data serialization\n");
9311 if (rs
->data_srlz
< STATE_STOP
)
9312 insn_group_break (1, 0, 0);
9314 int oldqp
= CURR_SLOT
.qp_regno
;
9315 struct ia64_opcode
*oldidesc
= CURR_SLOT
.idesc
;
9316 /* Manually jam a srlz.d insn into the stream */
9317 CURR_SLOT
.qp_regno
= 0;
9318 CURR_SLOT
.idesc
= ia64_find_opcode ("srlz.d");
9319 data_serialization ();
9320 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9321 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9323 CURR_SLOT
.qp_regno
= oldqp
;
9324 CURR_SLOT
.idesc
= oldidesc
;
9327 case IA64_DVS_IMPLIED
:
9328 case IA64_DVS_IMPLIEDF
:
9330 fprintf (stderr
, "Inserting stop\n");
9331 insn_group_break (1, 0, 0);
9338 /* Check the resources used by the given opcode against the current dependency
9341 The check is run once for each execution path encountered. In this case,
9342 a unique execution path is the sequence of instructions following a code
9343 entry point, e.g. the following has three execution paths, one starting
9344 at L0, one at L1, and one at L2.
9353 check_dependencies (idesc
)
9354 struct ia64_opcode
*idesc
;
9356 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9360 /* Note that the number of marked resources may change within the
9361 loop if in auto mode. */
9363 while (i
< regdepslen
)
9365 struct rsrc
*rs
= ®deps
[i
];
9366 const struct ia64_dependency
*dep
= rs
->dependency
;
9371 if (dep
->semantics
== IA64_DVS_NONE
9372 || (chkind
= depends_on (rs
->depind
, idesc
)) == -1)
9378 note
= NOTE (opdeps
->chks
[chkind
]);
9380 /* Check this resource against each execution path seen thus far. */
9381 for (path
= 0; path
<= md
.path
; path
++)
9385 /* If the dependency wasn't on the path being checked, ignore it. */
9386 if (rs
->path
< path
)
9389 /* If the QP for this insn implies a QP which has branched, don't
9390 bother checking. Ed. NOTE: I don't think this check is terribly
9391 useful; what's the point of generating code which will only be
9392 reached if its QP is zero?
9393 This code was specifically inserted to handle the following code,
9394 based on notes from Intel's DV checking code, where p1 implies p2.
9400 if (CURR_SLOT
.qp_regno
!= 0)
9404 for (implies
= 0; implies
< qp_implieslen
; implies
++)
9406 if (qp_implies
[implies
].path
>= path
9407 && qp_implies
[implies
].p1
== CURR_SLOT
.qp_regno
9408 && qp_implies
[implies
].p2_branched
)
9418 if ((matchtype
= resources_match (rs
, idesc
, note
,
9419 CURR_SLOT
.qp_regno
, path
)) != 0)
9422 char pathmsg
[256] = "";
9423 char indexmsg
[256] = "";
9424 int certain
= (matchtype
== 1 && CURR_SLOT
.qp_regno
== 0);
9427 sprintf (pathmsg
, " when entry is at label '%s'",
9428 md
.entry_labels
[path
- 1]);
9429 if (rs
->specific
&& rs
->index
!= 0)
9430 sprintf (indexmsg
, ", specific resource number is %d",
9432 sprintf (msg
, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
9434 (certain
? "violates" : "may violate"),
9435 dv_mode
[dep
->mode
], dep
->name
,
9436 dv_sem
[dep
->semantics
],
9439 if (md
.explicit_mode
)
9441 as_warn ("%s", msg
);
9443 as_warn (_("Only the first path encountering the conflict "
9445 as_warn_where (rs
->file
, rs
->line
,
9446 _("This is the location of the "
9447 "conflicting usage"));
9448 /* Don't bother checking other paths, to avoid duplicating
9455 fprintf (stderr
, "%s @ %s:%d\n", msg
, rs
->file
, rs
->line
);
9457 remove_marked_resource (rs
);
9459 /* since the set of dependencies has changed, start over */
9460 /* FIXME -- since we're removing dvs as we go, we
9461 probably don't really need to start over... */
9474 /* Register new dependencies based on the given opcode. */
9477 mark_resources (idesc
)
9478 struct ia64_opcode
*idesc
;
9481 const struct ia64_opcode_dependency
*opdeps
= idesc
->dependencies
;
9482 int add_only_qp_reads
= 0;
9484 /* A conditional branch only uses its resources if it is taken; if it is
9485 taken, we stop following that path. The other branch types effectively
9486 *always* write their resources. If it's not taken, register only QP
9488 if (is_conditional_branch (idesc
) || is_interruption_or_rfi (idesc
))
9490 add_only_qp_reads
= 1;
9494 fprintf (stderr
, "Registering '%s' resource usage\n", idesc
->name
);
9496 for (i
= 0; i
< opdeps
->nregs
; i
++)
9498 const struct ia64_dependency
*dep
;
9499 struct rsrc specs
[MAX_SPECS
];
9504 dep
= ia64_find_dependency (opdeps
->regs
[i
]);
9505 note
= NOTE (opdeps
->regs
[i
]);
9507 if (add_only_qp_reads
9508 && !(dep
->mode
== IA64_DV_WAR
9509 && (dep
->specifier
== IA64_RS_PR
9510 || dep
->specifier
== IA64_RS_PRr
9511 || dep
->specifier
== IA64_RS_PR63
)))
9514 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, md
.path
);
9517 if (md
.debug_dv
&& !count
)
9518 fprintf (stderr
, " No %s %s usage found (path %d)\n",
9519 dv_mode
[dep
->mode
], dep
->name
, md
.path
);
9524 mark_resource (idesc
, dep
, &specs
[count
],
9525 DEP (opdeps
->regs
[i
]), md
.path
);
9528 /* The execution path may affect register values, which may in turn
9529 affect which indirect-access resources are accessed. */
9530 switch (dep
->specifier
)
9542 for (path
= 0; path
< md
.path
; path
++)
9544 count
= specify_resource (dep
, idesc
, DV_REG
, specs
, note
, path
);
9546 mark_resource (idesc
, dep
, &specs
[count
],
9547 DEP (opdeps
->regs
[i
]), path
);
9554 /* Remove dependencies when they no longer apply. */
9557 update_dependencies (idesc
)
9558 struct ia64_opcode
*idesc
;
9562 if (strcmp (idesc
->name
, "srlz.i") == 0)
9564 instruction_serialization ();
9566 else if (strcmp (idesc
->name
, "srlz.d") == 0)
9568 data_serialization ();
9570 else if (is_interruption_or_rfi (idesc
)
9571 || is_taken_branch (idesc
))
9573 /* Although technically the taken branch doesn't clear dependencies
9574 which require a srlz.[id], we don't follow the branch; the next
9575 instruction is assumed to start with a clean slate. */
9579 else if (is_conditional_branch (idesc
)
9580 && CURR_SLOT
.qp_regno
!= 0)
9582 int is_call
= strstr (idesc
->name
, ".call") != NULL
;
9584 for (i
= 0; i
< qp_implieslen
; i
++)
9586 /* If the conditional branch's predicate is implied by the predicate
9587 in an existing dependency, remove that dependency. */
9588 if (qp_implies
[i
].p2
== CURR_SLOT
.qp_regno
)
9591 /* Note that this implied predicate takes a branch so that if
9592 a later insn generates a DV but its predicate implies this
9593 one, we can avoid the false DV warning. */
9594 qp_implies
[i
].p2_branched
= 1;
9595 while (depind
< regdepslen
)
9597 if (regdeps
[depind
].qp_regno
== qp_implies
[i
].p1
)
9599 print_dependency ("Removing", depind
);
9600 regdeps
[depind
] = regdeps
[--regdepslen
];
9607 /* Any marked resources which have this same predicate should be
9608 cleared, provided that the QP hasn't been modified between the
9609 marking instruction and the branch. */
9612 insn_group_break (0, CURR_SLOT
.qp_regno
, 1);
9617 while (i
< regdepslen
)
9619 if (regdeps
[i
].qp_regno
== CURR_SLOT
.qp_regno
9620 && regdeps
[i
].link_to_qp_branch
9621 && (regdeps
[i
].file
!= CURR_SLOT
.src_file
9622 || regdeps
[i
].line
!= CURR_SLOT
.src_line
))
9624 /* Treat like a taken branch */
9625 print_dependency ("Removing", i
);
9626 regdeps
[i
] = regdeps
[--regdepslen
];
9635 /* Examine the current instruction for dependency violations. */
9639 struct ia64_opcode
*idesc
;
9643 fprintf (stderr
, "Checking %s for violations (line %d, %d/%d)\n",
9644 idesc
->name
, CURR_SLOT
.src_line
,
9645 idesc
->dependencies
->nchks
,
9646 idesc
->dependencies
->nregs
);
9649 /* Look through the list of currently marked resources; if the current
9650 instruction has the dependency in its chks list which uses that resource,
9651 check against the specific resources used. */
9652 check_dependencies (idesc
);
9654 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads),
9655 then add them to the list of marked resources. */
9656 mark_resources (idesc
);
9658 /* There are several types of dependency semantics, and each has its own
9659 requirements for being cleared
9661 Instruction serialization (insns separated by interruption, rfi, or
9662 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR.
9664 Data serialization (instruction serialization, or writer + srlz.d +
9665 reader, where writer and srlz.d are in separate groups) clears
9666 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to
9667 always be the case).
9669 Instruction group break (groups separated by stop, taken branch,
9670 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF.
9672 update_dependencies (idesc
);
9674 /* Sometimes, knowing a register value allows us to avoid giving a false DV
9675 warning. Keep track of as many as possible that are useful. */
9676 note_register_values (idesc
);
9678 /* We don't need or want this anymore. */
9679 md
.mem_offset
.hint
= 0;
9684 /* Translate one line of assembly. Pseudo ops and labels do not show
9690 char *saved_input_line_pointer
, *mnemonic
;
9691 const struct pseudo_opcode
*pdesc
;
9692 struct ia64_opcode
*idesc
;
9693 unsigned char qp_regno
;
9697 saved_input_line_pointer
= input_line_pointer
;
9698 input_line_pointer
= str
;
9700 /* extract the opcode (mnemonic): */
9702 mnemonic
= input_line_pointer
;
9703 ch
= get_symbol_end ();
9704 pdesc
= (struct pseudo_opcode
*) hash_find (md
.pseudo_hash
, mnemonic
);
9707 *input_line_pointer
= ch
;
9708 (*pdesc
->handler
) (pdesc
->arg
);
9712 /* Find the instruction descriptor matching the arguments. */
9714 idesc
= ia64_find_opcode (mnemonic
);
9715 *input_line_pointer
= ch
;
9718 as_bad ("Unknown opcode `%s'", mnemonic
);
9722 idesc
= parse_operands (idesc
);
9726 /* Handle the dynamic ops we can handle now: */
9727 if (idesc
->type
== IA64_TYPE_DYN
)
9729 if (strcmp (idesc
->name
, "add") == 0)
9731 if (CURR_SLOT
.opnd
[2].X_op
== O_register
9732 && CURR_SLOT
.opnd
[2].X_add_number
< 4)
9736 ia64_free_opcode (idesc
);
9737 idesc
= ia64_find_opcode (mnemonic
);
9739 know (!idesc
->next
);
9742 else if (strcmp (idesc
->name
, "mov") == 0)
9744 enum ia64_opnd opnd1
, opnd2
;
9747 opnd1
= idesc
->operands
[0];
9748 opnd2
= idesc
->operands
[1];
9749 if (opnd1
== IA64_OPND_AR3
)
9751 else if (opnd2
== IA64_OPND_AR3
)
9755 if (CURR_SLOT
.opnd
[rop
].X_op
== O_register
9756 && ar_is_in_integer_unit (CURR_SLOT
.opnd
[rop
].X_add_number
))
9760 ia64_free_opcode (idesc
);
9761 idesc
= ia64_find_opcode (mnemonic
);
9762 while (idesc
!= NULL
9763 && (idesc
->operands
[0] != opnd1
9764 || idesc
->operands
[1] != opnd2
))
9765 idesc
= get_next_opcode (idesc
);
9770 if (md
.qp
.X_op
== O_register
)
9772 qp_regno
= md
.qp
.X_add_number
- REG_P
;
9773 md
.qp
.X_op
= O_absent
;
9776 flags
= idesc
->flags
;
9778 if ((flags
& IA64_OPCODE_FIRST
) != 0)
9779 insn_group_break (1, 0, 0);
9781 if ((flags
& IA64_OPCODE_NO_PRED
) != 0 && qp_regno
!= 0)
9783 as_bad ("`%s' cannot be predicated", idesc
->name
);
9787 /* Build the instruction. */
9788 CURR_SLOT
.qp_regno
= qp_regno
;
9789 CURR_SLOT
.idesc
= idesc
;
9790 as_where (&CURR_SLOT
.src_file
, &CURR_SLOT
.src_line
);
9791 dwarf2_where (&CURR_SLOT
.debug_line
);
9793 /* Add unwind entry, if there is one. */
9794 if (unwind
.current_entry
)
9796 CURR_SLOT
.unwind_record
= unwind
.current_entry
;
9797 unwind
.current_entry
= NULL
;
9800 /* Check for dependency violations. */
9804 md
.curr_slot
= (md
.curr_slot
+ 1) % NUM_SLOTS
;
9805 if (++md
.num_slots_in_use
>= NUM_SLOTS
)
9808 if ((flags
& IA64_OPCODE_LAST
) != 0)
9809 insn_group_break (1, 0, 0);
9811 md
.last_text_seg
= now_seg
;
9814 input_line_pointer
= saved_input_line_pointer
;
9817 /* Called when symbol NAME cannot be found in the symbol table.
9818 Should be used for dynamic valued symbols only. */
9821 md_undefined_symbol (name
)
9822 char *name ATTRIBUTE_UNUSED
;
9827 /* Called for any expression that can not be recognized. When the
9828 function is called, `input_line_pointer' will point to the start of
9835 enum pseudo_type pseudo_type
;
9840 switch (*input_line_pointer
)
9843 /* Find what relocation pseudo-function we're dealing with. */
9845 ch
= *++input_line_pointer
;
9846 for (i
= 0; i
< NELEMS (pseudo_func
); ++i
)
9847 if (pseudo_func
[i
].name
&& pseudo_func
[i
].name
[0] == ch
)
9849 len
= strlen (pseudo_func
[i
].name
);
9850 if (strncmp (pseudo_func
[i
].name
+ 1,
9851 input_line_pointer
+ 1, len
- 1) == 0
9852 && !is_part_of_name (input_line_pointer
[len
]))
9854 input_line_pointer
+= len
;
9855 pseudo_type
= pseudo_func
[i
].type
;
9859 switch (pseudo_type
)
9861 case PSEUDO_FUNC_RELOC
:
9863 if (*input_line_pointer
!= '(')
9865 as_bad ("Expected '('");
9869 ++input_line_pointer
;
9871 if (*input_line_pointer
++ != ')')
9873 as_bad ("Missing ')'");
9876 if (e
->X_op
!= O_symbol
)
9878 if (e
->X_op
!= O_pseudo_fixup
)
9880 as_bad ("Not a symbolic expression");
9883 if (i
!= FUNC_LT_RELATIVE
)
9885 as_bad ("Illegal combination of relocation functions");
9888 switch (S_GET_VALUE (e
->X_op_symbol
))
9890 case FUNC_FPTR_RELATIVE
:
9891 i
= FUNC_LT_FPTR_RELATIVE
; break;
9892 case FUNC_DTP_MODULE
:
9893 i
= FUNC_LT_DTP_MODULE
; break;
9894 case FUNC_DTP_RELATIVE
:
9895 i
= FUNC_LT_DTP_RELATIVE
; break;
9896 case FUNC_TP_RELATIVE
:
9897 i
= FUNC_LT_TP_RELATIVE
; break;
9899 as_bad ("Illegal combination of relocation functions");
9903 /* Make sure gas doesn't get rid of local symbols that are used
9905 e
->X_op
= O_pseudo_fixup
;
9906 e
->X_op_symbol
= pseudo_func
[i
].u
.sym
;
9909 case PSEUDO_FUNC_CONST
:
9910 e
->X_op
= O_constant
;
9911 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9914 case PSEUDO_FUNC_REG
:
9915 e
->X_op
= O_register
;
9916 e
->X_add_number
= pseudo_func
[i
].u
.ival
;
9920 name
= input_line_pointer
- 1;
9922 as_bad ("Unknown pseudo function `%s'", name
);
9928 ++input_line_pointer
;
9930 if (*input_line_pointer
!= ']')
9932 as_bad ("Closing bracket misssing");
9937 if (e
->X_op
!= O_register
)
9938 as_bad ("Register expected as index");
9940 ++input_line_pointer
;
9951 ignore_rest_of_line ();
9954 /* Return 1 if it's OK to adjust a reloc by replacing the symbol with
9955 a section symbol plus some offset. For relocs involving @fptr(),
9956 directives we don't want such adjustments since we need to have the
9957 original symbol's name in the reloc. */
9959 ia64_fix_adjustable (fix
)
9962 /* Prevent all adjustments to global symbols */
9963 if (S_IS_EXTERN (fix
->fx_addsy
) || S_IS_WEAK (fix
->fx_addsy
))
9966 switch (fix
->fx_r_type
)
9968 case BFD_RELOC_IA64_FPTR64I
:
9969 case BFD_RELOC_IA64_FPTR32MSB
:
9970 case BFD_RELOC_IA64_FPTR32LSB
:
9971 case BFD_RELOC_IA64_FPTR64MSB
:
9972 case BFD_RELOC_IA64_FPTR64LSB
:
9973 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9974 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9984 ia64_force_relocation (fix
)
9987 switch (fix
->fx_r_type
)
9989 case BFD_RELOC_IA64_FPTR64I
:
9990 case BFD_RELOC_IA64_FPTR32MSB
:
9991 case BFD_RELOC_IA64_FPTR32LSB
:
9992 case BFD_RELOC_IA64_FPTR64MSB
:
9993 case BFD_RELOC_IA64_FPTR64LSB
:
9995 case BFD_RELOC_IA64_LTOFF22
:
9996 case BFD_RELOC_IA64_LTOFF64I
:
9997 case BFD_RELOC_IA64_LTOFF_FPTR22
:
9998 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
9999 case BFD_RELOC_IA64_PLTOFF22
:
10000 case BFD_RELOC_IA64_PLTOFF64I
:
10001 case BFD_RELOC_IA64_PLTOFF64MSB
:
10002 case BFD_RELOC_IA64_PLTOFF64LSB
:
10009 return S_FORCE_RELOC (fix
->fx_addsy
);
10012 /* Decide from what point a pc-relative relocation is relative to,
10013 relative to the pc-relative fixup. Er, relatively speaking. */
10015 ia64_pcrel_from_section (fix
, sec
)
10019 unsigned long off
= fix
->fx_frag
->fr_address
+ fix
->fx_where
;
10021 if (bfd_get_section_flags (stdoutput
, sec
) & SEC_CODE
)
10027 /* This is called whenever some data item (not an instruction) needs a
10028 fixup. We pick the right reloc code depending on the byteorder
10029 currently in effect. */
10031 ia64_cons_fix_new (f
, where
, nbytes
, exp
)
10037 bfd_reloc_code_real_type code
;
10042 /* There are no reloc for 8 and 16 bit quantities, but we allow
10043 them here since they will work fine as long as the expression
10044 is fully defined at the end of the pass over the source file. */
10045 case 1: code
= BFD_RELOC_8
; break;
10046 case 2: code
= BFD_RELOC_16
; break;
10048 if (target_big_endian
)
10049 code
= BFD_RELOC_IA64_DIR32MSB
;
10051 code
= BFD_RELOC_IA64_DIR32LSB
;
10055 /* In 32-bit mode, data8 could mean function descriptors too. */
10056 if (exp
->X_op
== O_pseudo_fixup
10057 && exp
->X_op_symbol
10058 && S_GET_VALUE (exp
->X_op_symbol
) == FUNC_IPLT_RELOC
10059 && !(md
.flags
& EF_IA_64_ABI64
))
10061 if (target_big_endian
)
10062 code
= BFD_RELOC_IA64_IPLTMSB
;
10064 code
= BFD_RELOC_IA64_IPLTLSB
;
10065 exp
->X_op
= O_symbol
;
10070 if (target_big_endian
)
10071 code
= BFD_RELOC_IA64_DIR64MSB
;
10073 code
= BFD_RELOC_IA64_DIR64LSB
;
10078 if (exp
->X_op
== O_pseudo_fixup
10079 && exp
->X_op_symbol
10080 && S_GET_VALUE (exp
->X_op_symbol
) == FUNC_IPLT_RELOC
)
10082 if (target_big_endian
)
10083 code
= BFD_RELOC_IA64_IPLTMSB
;
10085 code
= BFD_RELOC_IA64_IPLTLSB
;
10087 exp
->X_op
= O_symbol
;
10093 as_bad ("Unsupported fixup size %d", nbytes
);
10094 ignore_rest_of_line ();
10097 if (exp
->X_op
== O_pseudo_fixup
)
10100 exp
->X_op
= O_symbol
;
10101 code
= ia64_gen_real_reloc_type (exp
->X_op_symbol
, code
);
10104 fix
= fix_new_exp (f
, where
, nbytes
, exp
, 0, code
);
10105 /* We need to store the byte order in effect in case we're going
10106 to fix an 8 or 16 bit relocation (for which there no real
10107 relocs available). See md_apply_fix3(). */
10108 fix
->tc_fix_data
.bigendian
= target_big_endian
;
10111 /* Return the actual relocation we wish to associate with the pseudo
10112 reloc described by SYM and R_TYPE. SYM should be one of the
10113 symbols in the pseudo_func array, or NULL. */
10115 static bfd_reloc_code_real_type
10116 ia64_gen_real_reloc_type (sym
, r_type
)
10117 struct symbol
*sym
;
10118 bfd_reloc_code_real_type r_type
;
10120 bfd_reloc_code_real_type
new = 0;
10127 switch (S_GET_VALUE (sym
))
10129 case FUNC_FPTR_RELATIVE
:
10132 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_FPTR64I
; break;
10133 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_FPTR32MSB
; break;
10134 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_FPTR32LSB
; break;
10135 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_FPTR64MSB
; break;
10136 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_FPTR64LSB
; break;
10141 case FUNC_GP_RELATIVE
:
10144 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_GPREL22
; break;
10145 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_GPREL64I
; break;
10146 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_GPREL32MSB
; break;
10147 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_GPREL32LSB
; break;
10148 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_GPREL64MSB
; break;
10149 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_GPREL64LSB
; break;
10154 case FUNC_LT_RELATIVE
:
10157 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_LTOFF22
; break;
10158 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_LTOFF64I
; break;
10163 case FUNC_PC_RELATIVE
:
10166 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PCREL22
; break;
10167 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PCREL64I
; break;
10168 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_PCREL32MSB
; break;
10169 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_PCREL32LSB
; break;
10170 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PCREL64MSB
; break;
10171 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PCREL64LSB
; break;
10176 case FUNC_PLT_RELATIVE
:
10179 case BFD_RELOC_IA64_IMM22
: new = BFD_RELOC_IA64_PLTOFF22
; break;
10180 case BFD_RELOC_IA64_IMM64
: new = BFD_RELOC_IA64_PLTOFF64I
; break;
10181 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_PLTOFF64MSB
;break;
10182 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_PLTOFF64LSB
;break;
10187 case FUNC_SEC_RELATIVE
:
10190 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SECREL32MSB
;break;
10191 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SECREL32LSB
;break;
10192 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SECREL64MSB
;break;
10193 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SECREL64LSB
;break;
10198 case FUNC_SEG_RELATIVE
:
10201 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_SEGREL32MSB
;break;
10202 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_SEGREL32LSB
;break;
10203 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_SEGREL64MSB
;break;
10204 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_SEGREL64LSB
;break;
10209 case FUNC_LTV_RELATIVE
:
10212 case BFD_RELOC_IA64_DIR32MSB
: new = BFD_RELOC_IA64_LTV32MSB
; break;
10213 case BFD_RELOC_IA64_DIR32LSB
: new = BFD_RELOC_IA64_LTV32LSB
; break;
10214 case BFD_RELOC_IA64_DIR64MSB
: new = BFD_RELOC_IA64_LTV64MSB
; break;
10215 case BFD_RELOC_IA64_DIR64LSB
: new = BFD_RELOC_IA64_LTV64LSB
; break;
10220 case FUNC_LT_FPTR_RELATIVE
:
10223 case BFD_RELOC_IA64_IMM22
:
10224 new = BFD_RELOC_IA64_LTOFF_FPTR22
; break;
10225 case BFD_RELOC_IA64_IMM64
:
10226 new = BFD_RELOC_IA64_LTOFF_FPTR64I
; break;
10232 case FUNC_TP_RELATIVE
:
10235 case BFD_RELOC_IA64_IMM14
:
10236 new = BFD_RELOC_IA64_TPREL14
; break;
10237 case BFD_RELOC_IA64_IMM22
:
10238 new = BFD_RELOC_IA64_TPREL22
; break;
10239 case BFD_RELOC_IA64_IMM64
:
10240 new = BFD_RELOC_IA64_TPREL64I
; break;
10246 case FUNC_LT_TP_RELATIVE
:
10249 case BFD_RELOC_IA64_IMM22
:
10250 new = BFD_RELOC_IA64_LTOFF_TPREL22
; break;
10256 case FUNC_LT_DTP_MODULE
:
10259 case BFD_RELOC_IA64_IMM22
:
10260 new = BFD_RELOC_IA64_LTOFF_DTPMOD22
; break;
10266 case FUNC_DTP_RELATIVE
:
10269 case BFD_RELOC_IA64_IMM14
:
10270 new = BFD_RELOC_IA64_DTPREL14
; break;
10271 case BFD_RELOC_IA64_IMM22
:
10272 new = BFD_RELOC_IA64_DTPREL22
; break;
10273 case BFD_RELOC_IA64_IMM64
:
10274 new = BFD_RELOC_IA64_DTPREL64I
; break;
10280 case FUNC_LT_DTP_RELATIVE
:
10283 case BFD_RELOC_IA64_IMM22
:
10284 new = BFD_RELOC_IA64_LTOFF_DTPREL22
; break;
10290 case FUNC_IPLT_RELOC
:
10296 /* Hmmmm. Should this ever occur? */
10303 /* Here is where generate the appropriate reloc for pseudo relocation
10306 ia64_validate_fix (fix
)
10309 switch (fix
->fx_r_type
)
10311 case BFD_RELOC_IA64_FPTR64I
:
10312 case BFD_RELOC_IA64_FPTR32MSB
:
10313 case BFD_RELOC_IA64_FPTR64LSB
:
10314 case BFD_RELOC_IA64_LTOFF_FPTR22
:
10315 case BFD_RELOC_IA64_LTOFF_FPTR64I
:
10316 if (fix
->fx_offset
!= 0)
10317 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10318 "No addend allowed in @fptr() relocation");
10328 fix_insn (fix
, odesc
, value
)
10330 const struct ia64_operand
*odesc
;
10333 bfd_vma insn
[3], t0
, t1
, control_bits
;
10338 slot
= fix
->fx_where
& 0x3;
10339 fixpos
= fix
->fx_frag
->fr_literal
+ (fix
->fx_where
- slot
);
10341 /* Bundles are always in little-endian byte order */
10342 t0
= bfd_getl64 (fixpos
);
10343 t1
= bfd_getl64 (fixpos
+ 8);
10344 control_bits
= t0
& 0x1f;
10345 insn
[0] = (t0
>> 5) & 0x1ffffffffffLL
;
10346 insn
[1] = ((t0
>> 46) & 0x3ffff) | ((t1
& 0x7fffff) << 18);
10347 insn
[2] = (t1
>> 23) & 0x1ffffffffffLL
;
10350 if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU64
)
10352 insn
[1] = (value
>> 22) & 0x1ffffffffffLL
;
10353 insn
[2] |= (((value
& 0x7f) << 13)
10354 | (((value
>> 7) & 0x1ff) << 27)
10355 | (((value
>> 16) & 0x1f) << 22)
10356 | (((value
>> 21) & 0x1) << 21)
10357 | (((value
>> 63) & 0x1) << 36));
10359 else if (odesc
- elf64_ia64_operands
== IA64_OPND_IMMU62
)
10361 if (value
& ~0x3fffffffffffffffULL
)
10362 err
= "integer operand out of range";
10363 insn
[1] = (value
>> 21) & 0x1ffffffffffLL
;
10364 insn
[2] |= (((value
& 0xfffff) << 6) | (((value
>> 20) & 0x1) << 36));
10366 else if (odesc
- elf64_ia64_operands
== IA64_OPND_TGT64
)
10369 insn
[1] = ((value
>> 20) & 0x7fffffffffLL
) << 2;
10370 insn
[2] |= ((((value
>> 59) & 0x1) << 36)
10371 | (((value
>> 0) & 0xfffff) << 13));
10374 err
= (*odesc
->insert
) (odesc
, value
, insn
+ slot
);
10377 as_bad_where (fix
->fx_file
, fix
->fx_line
, err
);
10379 t0
= control_bits
| (insn
[0] << 5) | (insn
[1] << 46);
10380 t1
= ((insn
[1] >> 18) & 0x7fffff) | (insn
[2] << 23);
10381 number_to_chars_littleendian (fixpos
+ 0, t0
, 8);
10382 number_to_chars_littleendian (fixpos
+ 8, t1
, 8);
10385 /* Attempt to simplify or even eliminate a fixup. The return value is
10386 ignored; perhaps it was once meaningful, but now it is historical.
10387 To indicate that a fixup has been eliminated, set FIXP->FX_DONE.
10389 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry
10393 md_apply_fix3 (fix
, valP
, seg
)
10396 segT seg ATTRIBUTE_UNUSED
;
10399 valueT value
= *valP
;
10402 fixpos
= fix
->fx_frag
->fr_literal
+ fix
->fx_where
;
10406 switch (fix
->fx_r_type
)
10408 case BFD_RELOC_IA64_DIR32MSB
:
10409 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32MSB
;
10413 case BFD_RELOC_IA64_DIR32LSB
:
10414 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL32LSB
;
10418 case BFD_RELOC_IA64_DIR64MSB
:
10419 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64MSB
;
10423 case BFD_RELOC_IA64_DIR64LSB
:
10424 fix
->fx_r_type
= BFD_RELOC_IA64_PCREL64LSB
;
10434 switch (fix
->fx_r_type
)
10436 case BFD_RELOC_UNUSED
:
10437 /* This must be a TAG13 or TAG13b operand. There are no external
10438 relocs defined for them, so we must give an error. */
10439 as_bad_where (fix
->fx_file
, fix
->fx_line
,
10440 "%s must have a constant value",
10441 elf64_ia64_operands
[fix
->tc_fix_data
.opnd
].desc
);
10445 case BFD_RELOC_IA64_TPREL14
:
10446 case BFD_RELOC_IA64_TPREL22
:
10447 case BFD_RELOC_IA64_TPREL64I
:
10448 case BFD_RELOC_IA64_LTOFF_TPREL22
:
10449 case BFD_RELOC_IA64_LTOFF_DTPMOD22
:
10450 case BFD_RELOC_IA64_DTPREL14
:
10451 case BFD_RELOC_IA64_DTPREL22
:
10452 case BFD_RELOC_IA64_DTPREL64I
:
10453 case BFD_RELOC_IA64_LTOFF_DTPREL22
:
10454 S_SET_THREAD_LOCAL (fix
->fx_addsy
);
10461 /* ??? This is a hack copied from tc-i386.c to make PCREL relocs
10462 work. There should be a better way to handle this. */
10464 fix
->fx_offset
+= fix
->fx_where
+ fix
->fx_frag
->fr_address
;
10466 else if (fix
->tc_fix_data
.opnd
== IA64_OPND_NIL
)
10468 if (fix
->tc_fix_data
.bigendian
)
10469 number_to_chars_bigendian (fixpos
, value
, fix
->fx_size
);
10471 number_to_chars_littleendian (fixpos
, value
, fix
->fx_size
);
10476 fix_insn (fix
, elf64_ia64_operands
+ fix
->tc_fix_data
.opnd
, value
);
10481 /* Generate the BFD reloc to be stuck in the object file from the
10482 fixup used internally in the assembler. */
10485 tc_gen_reloc (sec
, fixp
)
10486 asection
*sec ATTRIBUTE_UNUSED
;
10491 reloc
= xmalloc (sizeof (*reloc
));
10492 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
10493 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
10494 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10495 reloc
->addend
= fixp
->fx_offset
;
10496 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
10500 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10501 "Cannot represent %s relocation in object file",
10502 bfd_get_reloc_code_name (fixp
->fx_r_type
));
10507 /* Turn a string in input_line_pointer into a floating point constant
10508 of type TYPE, and store the appropriate bytes in *LIT. The number
10509 of LITTLENUMS emitted is stored in *SIZE. An error message is
10510 returned, or NULL on OK. */
10512 #define MAX_LITTLENUMS 5
10515 md_atof (type
, lit
, size
)
10520 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
10521 LITTLENUM_TYPE
*word
;
10551 return "Bad call to MD_ATOF()";
10553 t
= atof_ieee (input_line_pointer
, type
, words
);
10555 input_line_pointer
= t
;
10556 *size
= prec
* sizeof (LITTLENUM_TYPE
);
10558 for (word
= words
+ prec
- 1; prec
--;)
10560 md_number_to_chars (lit
, (long) (*word
--), sizeof (LITTLENUM_TYPE
));
10561 lit
+= sizeof (LITTLENUM_TYPE
);
10566 /* Round up a section's size to the appropriate boundary. */
10568 md_section_align (seg
, size
)
10572 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10573 valueT mask
= ((valueT
) 1 << align
) - 1;
10575 return (size
+ mask
) & ~mask
;
10578 /* Handle ia64 specific semantics of the align directive. */
10581 ia64_md_do_align (n
, fill
, len
, max
)
10582 int n ATTRIBUTE_UNUSED
;
10583 const char *fill ATTRIBUTE_UNUSED
;
10584 int len ATTRIBUTE_UNUSED
;
10585 int max ATTRIBUTE_UNUSED
;
10587 if (subseg_text_p (now_seg
))
10588 ia64_flush_insns ();
10591 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10592 of an rs_align_code fragment. */
10595 ia64_handle_align (fragp
)
10598 /* Use mfi bundle of nops with no stop bits. */
10599 static const unsigned char be_nop
[]
10600 = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
10601 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c};
10602 static const unsigned char le_nop
[]
10603 = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
10604 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
10609 if (fragp
->fr_type
!= rs_align_code
)
10612 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
10613 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
10615 /* Make sure we are on a 16-byte boundary, in case someone has been
10616 putting data into a text section. */
10619 int fix
= bytes
& 15;
10620 memset (p
, 0, fix
);
10623 fragp
->fr_fix
+= fix
;
10626 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 16);
10627 fragp
->fr_var
= 16;