1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R/X.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
29 const CGEN_INSN
* insn
;
32 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
34 char buffer
[CGEN_MAX_INSN_SIZE
];
41 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
42 boundary (i.e. was the first of two 16 bit insns). */
43 static m32r_insn prev_insn
;
45 /* Non-zero if we've seen a relaxable insn since the last 32 bit
47 static int seen_relaxable_p
= 0;
49 /* Non-zero if -relax specified, in which case sufficient relocs are output
50 for the linker to do relaxing.
51 We do simple forms of relaxing internally, but they are always done.
52 This flag does not apply to them. */
53 static int m32r_relax
;
55 /* If non-NULL, pointer to cpu description file to read.
56 This allows runtime additions to the assembler. */
57 static char * m32r_cpu_desc
;
59 /* start-sanitize-m32rx */
60 /* Non-zero if -m32rx has been specified, in which case support for the
61 extended M32RX instruction set should be enabled. */
62 static int enable_m32rx
= 0;
64 /* Non-zero if the programmer should be warned when an explicit parallel
65 instruction might have constraint violations. */
66 static int warn_explicit_parallel_conflicts
= 1;
67 /* end-sanitize-m32rx */
69 /* stuff for .scomm symbols. */
70 static segT sbss_section
;
71 static asection scom_section
;
72 static asymbol scom_symbol
;
74 const char comment_chars
[] = ";";
75 const char line_comment_chars
[] = "#";
76 const char line_separator_chars
[] = "";
77 const char EXP_CHARS
[] = "eE";
78 const char FLT_CHARS
[] = "dD";
80 /* Relocations against symbols are done in two
81 parts, with a HI relocation and a LO relocation. Each relocation
82 has only 16 bits of space to store an addend. This means that in
83 order for the linker to handle carries correctly, it must be able
84 to locate both the HI and the LO relocation. This means that the
85 relocations must appear in order in the relocation table.
87 In order to implement this, we keep track of each unmatched HI
88 relocation. We then sort them so that they immediately precede the
89 corresponding LO relocation. */
93 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
94 fixS
* fixp
; /* This fixup. */
95 segT seg
; /* The section this fixup is in. */
99 /* The list of unmatched HI relocs. */
101 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
104 /* start-sanitize-m32rx */
110 if (stdoutput
!= NULL
)
111 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
112 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
114 /* end-sanitize-m32rx */
116 const char * md_shortopts
= "";
118 struct option md_longopts
[] =
120 /* start-sanitize-m32rx */
121 #define OPTION_M32RX (OPTION_MD_BASE)
122 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
123 #define OPTION_WARN (OPTION_MD_BASE + 1)
124 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN
},
125 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
126 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN
},
127 /* end-sanitize-m32rx */
129 #if 0 /* not supported yet */
130 #define OPTION_RELAX (OPTION_MD_BASE + 3)
131 {"relax", no_argument
, NULL
, OPTION_RELAX
},
132 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
133 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
136 {NULL
, no_argument
, NULL
, 0}
138 size_t md_longopts_size
= sizeof (md_longopts
);
141 md_parse_option (c
, arg
)
147 /* start-sanitize-m32rx */
153 warn_explicit_parallel_conflicts
= 1;
157 warn_explicit_parallel_conflicts
= 0;
159 /* end-sanitize-m32rx */
161 #if 0 /* not supported yet */
165 case OPTION_CPU_DESC
:
176 md_show_usage (stream
)
179 fprintf (stream
, "M32R/X options:\n");
180 /* start-sanitize-m32rx */
182 --m32rx support the extended m32rx instruction set\n");
185 --warn-explicit-parallel-conflicts Warn when parallel instrucitons violate contraints\
186 --no-warn-explicit-parallel-conflicts Do not warn when parallel instrucitons violate contraints\n");
187 /* end-sanitize-m32rx */
191 --relax create linker relaxable code\n");
193 --cpu-desc provide runtime cpu description file\n");
197 static void fill_insn
PARAMS ((int));
198 static void m32r_scomm
PARAMS ((int));
200 /* Set by md_assemble for use by m32r_fill_insn. */
201 static subsegT prev_subseg
;
202 static segT prev_seg
;
204 /* The target specific pseudo-ops which we support. */
205 const pseudo_typeS md_pseudo_table
[] =
208 { "fillinsn", fill_insn
, 0 },
209 { "scomm", m32r_scomm
, 0 },
210 /* start-sanitize-m32rx */
211 { "m32r", allow_m32rx
, 0},
212 { "m32rx", allow_m32rx
, 1},
213 /* end-sanitize-m32rx */
217 /* FIXME: Should be machine generated. */
218 #define NOP_INSN 0x7000
219 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
221 /* When we align the .text section, insert the correct NOP pattern.
222 N is the power of 2 alignment. LEN is the length of pattern FILL.
223 MAX is the maximum number of characters to skip when doing the alignment,
224 or 0 if there is no maximum. */
227 m32r_do_align (n
, fill
, len
, max
)
233 if ((fill
== NULL
|| (* fill
== 0 && len
== 1))
234 && (now_seg
->flags
& SEC_CODE
) != 0
235 /* Only do this special handling if aligning to at least a
238 /* Only do this special handling if we're allowed to emit at
240 && (max
== 0 || max
> 1))
242 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
245 /* First align to a 2 byte boundary, in case there is an odd .byte. */
246 /* FIXME: How much memory will cause gas to use when assembling a big
247 program? Perhaps we can avoid the frag_align call? */
248 frag_align (1, 0, 0);
250 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
252 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
253 /* If doing larger alignments use a repeating sequence of appropriate
257 static const unsigned char multi_nop_pattern
[] =
258 { 0x70, 0x00, 0xf0, 0x00 };
259 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
269 assemble_nop (opcode
)
272 char * f
= frag_more (2);
273 md_number_to_chars (f
, opcode
, 2);
276 /* If the last instruction was the first of 2 16 bit insns,
277 output a nop to move the PC to a 32 bit boundary.
279 This is done via an alignment specification since branch relaxing
280 may make it unnecessary.
282 Internally, we need to output one of these each time a 32 bit insn is
283 seen after an insn that is relaxable. */
289 (void) m32r_do_align (2, NULL
, 0, 0);
290 prev_insn
.insn
= NULL
;
291 seen_relaxable_p
= 0;
294 /* Cover function to fill_insn called after a label and at end of assembly.
296 The result is always 1: we're called in a conditional to see if the
297 current line is a label. */
300 m32r_fill_insn (done
)
306 if (prev_seg
!= NULL
)
311 subseg_set (prev_seg
, prev_subseg
);
315 subseg_set (seg
, subseg
);
328 /* Initialize the `cgen' interface. */
330 /* This is a callback from cgen to gas to parse operands. */
331 cgen_parse_operand_fn
= cgen_parse_operand
;
333 /* Set the machine number and endian. */
334 CGEN_SYM (init_asm
) (0 /* mach number */,
336 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
);
338 #if 0 /* not supported yet */
339 /* If a runtime cpu description file was provided, parse it. */
340 if (m32r_cpu_desc
!= NULL
)
344 errmsg
= cgen_read_cpu_file (m32r_cpu_desc
);
346 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
350 /* Save the current subseg so we can restore it [it's the default one and
351 we don't want the initial section to be .sbss]. */
355 /* The sbss section is for local .scomm symbols. */
356 sbss_section
= subseg_new (".sbss", 0);
358 /* This is copied from perform_an_assembly_pass. */
359 applicable
= bfd_applicable_section_flags (stdoutput
);
360 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
362 #if 0 /* What does this do? [see perform_an_assembly_pass] */
363 seg_info (bss_section
)->bss
= 1;
366 subseg_set (seg
, subseg
);
368 /* We must construct a fake section similar to bfd_com_section
369 but with the name .scommon. */
370 scom_section
= bfd_com_section
;
371 scom_section
.name
= ".scommon";
372 scom_section
.output_section
= & scom_section
;
373 scom_section
.symbol
= & scom_symbol
;
374 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
375 scom_symbol
= * bfd_com_section
.symbol
;
376 scom_symbol
.name
= ".scommon";
377 scom_symbol
.section
= & scom_section
;
379 /* start-sanitize-m32rx */
380 allow_m32rx (enable_m32rx
);
381 /* end-sanitize-m32rx */
384 /* Returns non zero if the given instruction writes to a destination register. */
386 writes_to_dest_reg (insn
)
387 const CGEN_INSN
* insn
;
389 unsigned char * syntax
= CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn
));
392 /* Scan the syntax string looking for a destination register. */
393 while ((c
= (* syntax
++)) != 0)
394 if (c
== 128 + M32R_OPERAND_DR
)
400 /* Returns non zero if the given instruction reads from a source register.
401 Ignores the first 'num_ignore' macthes in the syntax string. */
403 reads_from_src_reg (insn
, num_ignore
)
404 const CGEN_INSN
* insn
;
407 unsigned char * syntax
= CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn
));
410 /* Scan the syntax string looking for a source register. */
411 while ((c
= (* syntax
++)) != 0)
413 if ( c
== 128 + M32R_OPERAND_SR
414 || c
== 128 + M32R_OPERAND_SRC1
415 || c
== 128 + M32R_OPERAND_SRC2
)
417 if (num_ignore
-- > 0)
427 /* Returns the integer value of the destination register held in the fields. */
428 #define get_dest_reg(fields) (fields).f_r1
430 /* Returns an integer representing the source register of the given type. */
432 get_src_reg (syntax_field
, fields
)
433 unsigned char syntax_field
;
434 CGEN_FIELDS
* fields
;
436 switch (syntax_field
)
438 case 128 + M32R_OPERAND_SR
: return fields
->f_r2
;
439 /* Relies upon the fact that no instruction with a $src1 operand
440 also has a $dr operand. */
441 case 128 + M32R_OPERAND_SRC1
: return fields
->f_r1
;
442 case 128 + M32R_OPERAND_SRC2
: return fields
->f_r2
;
443 default: abort(); return -1;
447 /* Returns zero iff the output register of instruction 'a'
448 is an input register to instruction 'b'. */
450 check_parallel_io_clash (a
, b
)
454 if (writes_to_dest_reg (a
->insn
))
456 unsigned char syntax_field
;
459 while (syntax_field
= reads_from_src_reg (b
->insn
, skip
++))
461 if (get_src_reg (syntax_field
, & b
->fields
) == get_dest_reg (a
->fields
))
470 /* Returns NULL if the two 16 bit insns can be executed in parallel,
471 otherwise it returns a pointer to an error message explaining why not. */
473 can_make_parallel (a
, b
)
477 /* start-sanitize-m32rx */
481 /* Make sure the instructions are the right length. */
482 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
483 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
486 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
487 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
489 /* Make sure that the instructions use the correct execution pipelines. */
490 if ( a_pipe
== PIPE_NONE
491 || b_pipe
== PIPE_NONE
)
492 return "Instructions do not use parallel execution pipelines.";
494 if ( a_pipe
== PIPE_S
496 return "Instructions share the same execution pipeline";
498 /* end-sanitize-m32rx */
499 if ( writes_to_dest_reg (a
->insn
)
500 && writes_to_dest_reg (b
->insn
)
501 && (get_dest_reg (a
->fields
) == get_dest_reg (b
->fields
)))
502 return "Instructions write to the same destination register.";
509 make_parallel (buffer
)
510 cgen_insn_t
* buffer
;
512 /* Force the top bit of the second insn to be set. */
516 if (CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
)
518 value
= bfd_getb16 ((bfd_byte
*) buffer
);
520 bfd_putb16 (value
, (char *) buffer
);
524 value
= bfd_getl16 ((bfd_byte
*) buffer
);
526 bfd_putl16 (value
, (char *) buffer
);
531 make_parallel (buffer
)
534 /* Force the top bit of the second insn to be set. */
536 buffer
[CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
? 0 : 1] |= 0x80;
541 /* start-sanitize-m32rx */
543 assemble_parallel_insn (str
, str2
)
552 * str2
= 0; /* Seperate the two instructions. */
554 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
555 so that the parallel instruction will start on a 32 bit boundary. */
559 /* Parse the first instruction. */
560 if (! (first
.insn
= CGEN_SYM (assemble_insn
)
561 (str
, & first
.fields
, first
.buffer
, & errmsg
)))
567 /* Check to see if this is an allowable parallel insn. */
568 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
570 as_bad ("instruction '%s' cannot be executed in parallel.", str
);
575 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
577 as_bad ("instruction '%s' is for the M32RX only", str
);
581 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
582 str3
= str
; /* Save the original string pointer. */
583 str
= str2
+ 2; /* Advanced past the parsed string. */
584 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
586 /* Preserve any fixups that have been generated and reset the list to empty. */
589 /* Parse the second instruction. */
590 if (! (second
.insn
= CGEN_SYM (assemble_insn
)
591 (str
, & second
.fields
, second
.buffer
, & errmsg
)))
599 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
601 as_bad ("instruction '%s' is for the M32RX only", str
);
607 if ( strcmp (first
.insn
->name
, "nop") != 0
608 && strcmp (second
.insn
->name
, "nop") != 0)
610 as_bad ("'%s': only the NOP instruction can be issued in parallel on the m32r", str2
);
615 /* We assume that if the first instruction writes to a register that is
616 read by the second instruction it is because the programmer intended
617 this to happen, (after all they have explicitly requested that these
618 two instructions be executed in parallel). Although if the global
619 variable warn_explicit_parallel_conflicts is true then we do generate
620 a warning message. Similarly we assume that parallel branch and jump
621 instructions are deliberate and should not produce errors. */
623 if (can_make_parallel (& first
, & second
) == NULL
)
625 if (warn_explicit_parallel_conflicts
626 && (! check_parallel_io_clash (& first
, & second
)))
627 as_warn ("%s: output of first instruction fails to overwrite input of second instruction.", str2
);
629 /* Get the fixups for the first instruction. */
633 (void) cgen_asm_finish_insn (first
.insn
, first
.buffer
,
634 CGEN_FIELDS_BITSIZE (& first
.fields
));
636 /* Force the top bit of the second insn to be set. */
637 make_parallel (second
.buffer
);
639 /* Get its fixups. */
640 cgen_restore_fixups ();
643 (void) cgen_asm_finish_insn (second
.insn
, second
.buffer
,
644 CGEN_FIELDS_BITSIZE (& second
.fields
));
646 else if ((errmsg
= (char *) can_make_parallel (& second
, & first
,
647 false, false)) == NULL
)
649 if (warn_explicit_parallel_conflicts
650 && (! check_parallel_io_clash (& second
, & first
)))
651 as_warn ("%s: output of second instruction fails to overwrite input of first instruction.", str2
);
653 /* Write out the second instruction first. */
654 (void) cgen_asm_finish_insn (second
.insn
, second
.buffer
,
655 CGEN_FIELDS_BITSIZE (& second
.fields
));
657 /* Force the top bit of the first instruction to be set. */
658 make_parallel (first
.buffer
);
660 /* Get the fixups for the first instruction. */
661 cgen_restore_fixups ();
663 /* Write out the first instruction. */
664 (void) cgen_asm_finish_insn (first
.insn
, first
.buffer
,
665 CGEN_FIELDS_BITSIZE (& first
.fields
));
669 as_bad ("'%s': %s", str2
, errmsg
);
673 /* Set these so m32r_fill_insn can use them. */
675 prev_subseg
= now_subseg
;
679 /* end-sanitize-m32rx */
690 /* Initialize GAS's cgen interface for a new instruction. */
691 cgen_asm_init_parse ();
693 /* start-sanitize-m32rx */
694 /* Look for a parallel instruction seperator. */
695 if ((str2
= strstr (str
, "||")) != NULL
)
697 assemble_parallel_insn (str
, str2
);
700 /* end-sanitize-m32rx */
702 insn
.insn
= CGEN_SYM (assemble_insn
) (str
, & insn
.fields
, insn
.buffer
, & errmsg
);
709 /* start-sanitize-m32rx */
710 if (! enable_m32rx
&& CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
712 as_bad ("instruction '%s' is for the M32RX only", str
);
715 /* end-sanitize-m32rx */
717 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
719 /* 32 bit insns must live on 32 bit boundaries. */
720 if (prev_insn
.insn
|| seen_relaxable_p
)
722 /* FIXME: If calling fill_insn too many times turns us into a memory
723 pig, can we call assemble_nop instead of !seen_relaxable_p? */
727 (void) cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
728 CGEN_FIELDS_BITSIZE (& insn
.fields
));
732 /* start-sanitize-m32rx */
733 /* start-sanitize-phase2-m32rx */
735 /* end-sanitize-phase2-m32rx */
736 /* end-sanitize-m32rx */
738 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
741 /* Keep track of whether we've seen a pair of 16 bit insns.
742 prev_insn.insn is NULL when we're on a 32 bit boundary. */
745 /* start-sanitize-m32rx */
746 /* start-sanitize-phase2-m32rx */
747 /* Look to see if this instruction can be combined with the
748 previous instruction to make one, parallel, 32 bit instruction.
749 If the previous instruction (potentially) changed the flow of
750 program control, then it cannot be combined with the current
751 instruction. Also if the output of the previous instruction
752 is used as an input to the current instruction then it cannot
753 be combined. Otherwise call can_make_parallel() with both
754 orderings of the instructions to see if they can be combined. */
755 if ( ! CGEN_INSN_ATTR (prev_insn
.insn
, CGEN_INSN_COND_CTI
)
756 && ! CGEN_INSN_ATTR (prev_insn
.insn
, CGEN_INSN_UNCOND_CTI
)
757 && check_parallel_io_clash (& prev_insn
, &insn
)
760 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
761 make_parallel (insn
.buffer
);
762 else if (can_make_parallel (& insn
, & prev_insn
.insn
) == NULL
)
765 /* end-sanitize-phase2-m32rx */
766 /* end-sanitize-m32rx */
768 prev_insn
.insn
= NULL
;
775 /* Record the frag that might be used by this insn. */
776 insn
.frag
= frag_now
;
777 insn
.addr
= cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
778 CGEN_FIELDS_BITSIZE (& insn
.fields
));
780 /* start-sanitize-m32rx */
781 /* start-sanitize-phase2-m32rx */
786 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
788 /* Swap the two insns */
789 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
790 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
792 make_parallel (insn
.addr
);
794 /* Swap any relaxable frags recorded for the two insns. */
795 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
797 prev_insn
.frag
->fr_opcode
= insn
.addr
;
799 else if (insn
.frag
->fr_opcode
== insn
.addr
)
801 insn
.frag
->fr_opcode
= prev_insn
.addr
;
804 /* end-sanitize-phase2-m32rx */
806 /* Record where this instruction was assembled. */
807 prev_insn
.addr
= insn
.addr
;
808 prev_insn
.frag
= insn
.frag
;
809 /* end-sanitize-m32rx */
811 /* If the insn needs the following one to be on a 32 bit boundary
812 (e.g. subroutine calls), fill this insn's slot. */
814 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_FILL_SLOT
) != 0)
817 /* If this is a relaxable insn (can be replaced with a larger version)
818 mark the fact so that we can emit an alignment directive for a
819 following 32 bit insn if we see one. */
820 if (CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_RELAXABLE
) != 0)
821 seen_relaxable_p
= 1;
824 /* Set these so m32r_fill_insn can use them. */
826 prev_subseg
= now_subseg
;
829 /* The syntax in the manual says constants begin with '#'.
830 We just ignore it. */
833 md_operand (expressionP
)
834 expressionS
* expressionP
;
836 if (* input_line_pointer
== '#')
838 input_line_pointer
++;
839 expression (expressionP
);
844 md_section_align (segment
, size
)
848 int align
= bfd_get_section_alignment (stdoutput
, segment
);
849 return ((size
+ (1 << align
) - 1) & (-1 << align
));
853 md_undefined_symbol (name
)
859 /* .scomm pseudo-op handler.
861 This is a new pseudo-op to handle putting objects in .scommon.
862 By doing this the linker won't need to do any work and more importantly
863 it removes the implicit -G arg necessary to correctly link the object file.
870 register char * name
;
874 register symbolS
* symbolP
;
878 name
= input_line_pointer
;
879 c
= get_symbol_end ();
881 /* just after name is now '\0' */
882 p
= input_line_pointer
;
885 if (* input_line_pointer
!= ',')
887 as_bad ("Expected comma after symbol-name: rest of line ignored.");
888 ignore_rest_of_line ();
892 input_line_pointer
++; /* skip ',' */
893 if ((size
= get_absolute_expression ()) < 0)
895 as_warn (".SCOMMon length (%ld.) <0! Ignored.", (long) size
);
896 ignore_rest_of_line ();
900 /* The third argument to .scomm is the alignment. */
901 if (* input_line_pointer
!= ',')
905 ++ input_line_pointer
;
906 align
= get_absolute_expression ();
909 as_warn ("ignoring bad alignment");
913 /* Convert to a power of 2 alignment. */
916 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
920 as_bad ("Common alignment not a power of 2");
921 ignore_rest_of_line ();
929 symbolP
= symbol_find_or_make (name
);
932 if (S_IS_DEFINED (symbolP
))
934 as_bad ("Ignoring attempt to re-define symbol `%s'.",
935 S_GET_NAME (symbolP
));
936 ignore_rest_of_line ();
940 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
942 as_bad ("Length of .scomm \"%s\" is already %ld. Not changed to %ld.",
943 S_GET_NAME (symbolP
),
944 (long) S_GET_VALUE (symbolP
),
947 ignore_rest_of_line ();
953 segT old_sec
= now_seg
;
954 int old_subsec
= now_subseg
;
957 record_alignment (sbss_section
, align2
);
958 subseg_set (sbss_section
, 0);
961 frag_align (align2
, 0, 0);
963 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
964 symbolP
->sy_frag
->fr_symbol
= 0;
966 symbolP
->sy_frag
= frag_now
;
968 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
971 S_SET_SIZE (symbolP
, size
);
972 S_SET_SEGMENT (symbolP
, sbss_section
);
973 S_CLEAR_EXTERNAL (symbolP
);
974 subseg_set (old_sec
, old_subsec
);
978 S_SET_VALUE (symbolP
, (valueT
) size
);
979 S_SET_ALIGN (symbolP
, align2
);
980 S_SET_EXTERNAL (symbolP
);
981 S_SET_SEGMENT (symbolP
, & scom_section
);
984 demand_empty_rest_of_line ();
987 /* Interface to relax_segment. */
989 /* FIXME: Build table by hand, get it working, then machine generate. */
991 const relax_typeS md_relax_table
[] =
994 1) most positive reach of this state,
995 2) most negative reach of this state,
996 3) how many bytes this mode will add to the size of the current frag
997 4) which index into the table to try if we can't fit into this one. */
999 /* The first entry must be unused because an `rlx_more' value of zero ends
1003 /* The displacement used by GAS is from the end of the 2 byte insn,
1004 so we subtract 2 from the following. */
1005 /* 16 bit insn, 8 bit disp -> 10 bit range.
1006 This doesn't handle a branch in the right slot at the border:
1007 the "& -4" isn't taken into account. It's not important enough to
1008 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1010 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1011 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1012 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1013 /* Same thing, but with leading nop for alignment. */
1014 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1018 m32r_relax_frag (fragP
, stretch
)
1022 /* Address of branch insn. */
1023 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1026 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1027 if (fragP
->fr_subtype
== 2)
1029 if ((address
& 3) != 0)
1031 fragP
->fr_subtype
= 3;
1035 else if (fragP
->fr_subtype
== 3)
1037 if ((address
& 3) == 0)
1039 fragP
->fr_subtype
= 2;
1045 growth
= relax_frag (fragP
, stretch
);
1047 /* Long jump on odd halfword boundary? */
1048 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1050 fragP
->fr_subtype
= 3;
1058 /* Return an initial guess of the length by which a fragment must grow to
1059 hold a branch to reach its destination.
1060 Also updates fr_type/fr_subtype as necessary.
1062 Called just before doing relaxation.
1063 Any symbol that is now undefined will not become defined.
1064 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1065 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1066 Although it may not be explicit in the frag, pretend fr_var starts with a
1070 md_estimate_size_before_relax (fragP
, segment
)
1074 int old_fr_fix
= fragP
->fr_fix
;
1075 char * opcode
= fragP
->fr_opcode
;
1077 /* The only thing we have to handle here are symbols outside of the
1078 current segment. They may be undefined or in a different segment in
1079 which case linker scripts may place them anywhere.
1080 However, we can't finish the fragment here and emit the reloc as insn
1081 alignment requirements may move the insn about. */
1083 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1085 /* The symbol is undefined in this segment.
1086 Change the relaxation subtype to the max allowable and leave
1087 all further handling to md_convert_frag. */
1088 fragP
->fr_subtype
= 2;
1090 #if 0 /* Can't use this, but leave in for illustration. */
1091 /* Change 16 bit insn to 32 bit insn. */
1094 /* Increase known (fixed) size of fragment. */
1097 /* Create a relocation for it. */
1098 fix_new (fragP
, old_fr_fix
, 4,
1100 fragP
->fr_offset
, 1 /* pcrel */,
1101 /* FIXME: Can't use a real BFD reloc here.
1102 cgen_md_apply_fix3 can't handle it. */
1103 BFD_RELOC_M32R_26_PCREL
);
1105 /* Mark this fragment as finished. */
1109 const CGEN_INSN
* insn
;
1112 /* Update the recorded insn.
1113 Fortunately we don't have to look very far.
1114 FIXME: Change this to record in the instruction the next higher
1115 relaxable insn to use. */
1116 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1118 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1119 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1121 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1127 fragP
->fr_cgen
.insn
= insn
;
1133 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1136 /* *fragP has been relaxed to its final size, and now needs to have
1137 the bytes inside it modified to conform to the new size.
1139 Called after relaxation is finished.
1140 fragP->fr_type == rs_machine_dependent.
1141 fragP->fr_subtype is the subtype of what the address relaxed to. */
1144 md_convert_frag (abfd
, sec
, fragP
)
1150 char * displacement
;
1156 opcode
= fragP
->fr_opcode
;
1158 /* Address opcode resides at in file space. */
1159 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1161 switch (fragP
->fr_subtype
)
1165 displacement
= & opcode
[1];
1170 displacement
= & opcode
[1];
1173 opcode
[2] = opcode
[0] | 0x80;
1174 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1175 opcode_address
+= 2;
1177 displacement
= & opcode
[3];
1183 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1185 /* symbol must be resolved by linker */
1186 if (fragP
->fr_offset
& 3)
1187 as_warn ("Addend to unresolved symbol not on word boundary.");
1188 addend
= fragP
->fr_offset
>> 2;
1192 /* Address we want to reach in file space. */
1193 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1194 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1195 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1198 /* Create a relocation for symbols that must be resolved by the linker.
1199 Otherwise output the completed insn. */
1201 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1203 assert (fragP
->fr_subtype
!= 1);
1204 assert (fragP
->fr_cgen
.insn
!= 0);
1205 cgen_record_fixup (fragP
,
1206 /* Offset of branch insn in frag. */
1207 fragP
->fr_fix
+ extension
- 4,
1208 fragP
->fr_cgen
.insn
,
1210 /* FIXME: quick hack */
1212 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1214 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1216 fragP
->fr_cgen
.opinfo
,
1217 fragP
->fr_symbol
, fragP
->fr_offset
);
1220 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1222 md_number_to_chars (displacement
, (valueT
) addend
,
1223 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1225 fragP
->fr_fix
+= extension
;
1228 /* Functions concerning relocs. */
1230 /* The location from which a PC relative jump should be calculated,
1231 given a PC relative reloc. */
1234 md_pcrel_from_section (fixP
, sec
)
1238 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1239 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1240 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1242 /* The symbol is undefined (or is defined but not in this section).
1243 Let the linker figure it out. */
1247 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1250 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1251 Returns BFD_RELOC_NONE if no reloc type can be found.
1252 *FIXP may be modified if desired. */
1254 bfd_reloc_code_real_type
1255 CGEN_SYM (lookup_reloc
) (insn
, operand
, fixP
)
1256 const CGEN_INSN
* insn
;
1257 const CGEN_OPERAND
* operand
;
1260 switch (CGEN_OPERAND_TYPE (operand
))
1262 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1263 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1264 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1265 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1266 case M32R_OPERAND_HI16
:
1267 case M32R_OPERAND_SLO16
:
1268 case M32R_OPERAND_ULO16
:
1269 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1270 if (fixP
->tc_fix_data
.opinfo
!= 0)
1271 return fixP
->tc_fix_data
.opinfo
;
1274 return BFD_RELOC_NONE
;
1277 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1280 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1285 struct m32r_hi_fixup
* hi_fixup
;
1287 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1288 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1290 hi_fixup
= ((struct m32r_hi_fixup
*)
1291 xmalloc (sizeof (struct m32r_hi_fixup
)));
1292 hi_fixup
->fixp
= fixP
;
1293 hi_fixup
->seg
= now_seg
;
1294 hi_fixup
->next
= m32r_hi_fixup_list
;
1296 m32r_hi_fixup_list
= hi_fixup
;
1299 /* Called while parsing an instruction to create a fixup.
1300 We need to check for HI16 relocs and queue them up for later sorting. */
1303 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1306 const CGEN_INSN
* insn
;
1308 const CGEN_OPERAND
* operand
;
1312 fixS
* fixP
= cgen_record_fixup_exp (frag
, where
, insn
, length
,
1313 operand
, opinfo
, exp
);
1315 switch (CGEN_OPERAND_TYPE (operand
))
1317 case M32R_OPERAND_HI16
:
1318 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1319 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1320 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1321 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1328 /* Return BFD reloc type from opinfo field in a fixS.
1329 It's tricky using fx_r_type in m32r_frob_file because the values
1330 are BFD_RELOC_UNUSED + operand number. */
1331 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1333 /* Sort any unmatched HI16 relocs so that they immediately precede
1334 the corresponding LO16 reloc. This is called before md_apply_fix and
1340 struct m32r_hi_fixup
* l
;
1342 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1344 segment_info_type
* seginfo
;
1347 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1348 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1350 /* Check quickly whether the next fixup happens to be a matching low. */
1351 if (l
->fixp
->fx_next
!= NULL
1352 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1353 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1354 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1357 /* Look through the fixups for this segment for a matching `low'.
1358 When we find one, move the high/shigh just in front of it. We do
1359 this in two passes. In the first pass, we try to find a
1360 unique `low'. In the second pass, we permit multiple high's
1361 relocs for a single `low'. */
1362 seginfo
= seg_info (l
->seg
);
1363 for (pass
= 0; pass
< 2; pass
++)
1369 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1371 /* Check whether this is a `low' fixup which matches l->fixp. */
1372 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1373 && f
->fx_addsy
== l
->fixp
->fx_addsy
1374 && f
->fx_offset
== l
->fixp
->fx_offset
1377 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1378 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1379 || prev
->fx_addsy
!= f
->fx_addsy
1380 || prev
->fx_offset
!= f
->fx_offset
))
1384 /* Move l->fixp before f. */
1385 for (pf
= &seginfo
->fix_root
;
1387 pf
= & (* pf
)->fx_next
)
1388 assert (* pf
!= NULL
);
1390 * pf
= l
->fixp
->fx_next
;
1392 l
->fixp
->fx_next
= f
;
1394 seginfo
->fix_root
= l
->fixp
;
1396 prev
->fx_next
= l
->fixp
;
1408 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1409 "Unmatched high/shigh reloc");
1414 /* See whether we need to force a relocation into the output file.
1415 This is used to force out switch and PC relative relocations when
1419 m32r_force_relocation (fix
)
1425 return (fix
->fx_pcrel
1429 /* Write a value out to the object file, using the appropriate endianness. */
1432 md_number_to_chars (buf
, val
, n
)
1437 if (target_big_endian
)
1438 number_to_chars_bigendian (buf
, val
, n
);
1440 number_to_chars_littleendian (buf
, val
, n
);
1443 /* Turn a string in input_line_pointer into a floating point constant of type
1444 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1445 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1448 /* Equal to MAX_PRECISION in atof-ieee.c */
1449 #define MAX_LITTLENUMS 6
1452 md_atof (type
, litP
, sizeP
)
1459 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1460 LITTLENUM_TYPE
* wordP
;
1462 char * atof_ieee ();
1480 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1484 return "Bad call to md_atof()";
1487 t
= atof_ieee (input_line_pointer
, type
, words
);
1489 input_line_pointer
= t
;
1490 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1492 if (target_big_endian
)
1494 for (i
= 0; i
< prec
; i
++)
1496 md_number_to_chars (litP
, (valueT
) words
[i
],
1497 sizeof (LITTLENUM_TYPE
));
1498 litP
+= sizeof (LITTLENUM_TYPE
);
1503 for (i
= prec
- 1; i
>= 0; i
--)
1505 md_number_to_chars (litP
, (valueT
) words
[i
],
1506 sizeof (LITTLENUM_TYPE
));
1507 litP
+= sizeof (LITTLENUM_TYPE
);