1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
28 /* Structure to hold all of the different components describing an individual instruction. */
31 const CGEN_INSN
* insn
;
32 const CGEN_INSN
* orig_insn
;
35 cgen_insn_t buffer
[CGEN_MAX_INSN_SIZE
/ sizeof (cgen_insn_t
)];
37 char buffer
[CGEN_MAX_INSN_SIZE
];
41 int indices
[MAX_OPERAND_INSTANCES
];
45 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
46 boundary (i.e. was the first of two 16 bit insns). */
47 static m32r_insn prev_insn
;
49 /* Non-zero if we've seen a relaxable insn since the last 32 bit
51 static int seen_relaxable_p
= 0;
53 /* Non-zero if -relax specified, in which case sufficient relocs are output
54 for the linker to do relaxing.
55 We do simple forms of relaxing internally, but they are always done.
56 This flag does not apply to them. */
57 static int m32r_relax
;
59 /* If non-NULL, pointer to cpu description file to read.
60 This allows runtime additions to the assembler. */
61 static char * m32r_cpu_desc
;
63 /* start-sanitize-m32rx */
64 /* Non-zero if -m32rx has been specified, in which case support for the
65 extended M32RX instruction set should be enabled. */
66 static int enable_m32rx
= 0;
68 /* Non-zero if the programmer should be warned when an explicit parallel
69 instruction might have constraint violations. */
70 static int warn_explicit_parallel_conflicts
= 1;
72 /* start-sanitize-phase2-m32rx */
73 /* Non-zero if insns can be made parallel. */
75 /* end-sanitize-phase2-m32rx */
76 /* end-sanitize-m32rx */
78 /* stuff for .scomm symbols. */
79 static segT sbss_section
;
80 static asection scom_section
;
81 static asymbol scom_symbol
;
83 const char comment_chars
[] = ";";
84 const char line_comment_chars
[] = "#";
85 const char line_separator_chars
[] = "";
86 const char EXP_CHARS
[] = "eE";
87 const char FLT_CHARS
[] = "dD";
89 /* Relocations against symbols are done in two
90 parts, with a HI relocation and a LO relocation. Each relocation
91 has only 16 bits of space to store an addend. This means that in
92 order for the linker to handle carries correctly, it must be able
93 to locate both the HI and the LO relocation. This means that the
94 relocations must appear in order in the relocation table.
96 In order to implement this, we keep track of each unmatched HI
97 relocation. We then sort them so that they immediately precede the
98 corresponding LO relocation. */
102 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
103 fixS
* fixp
; /* This fixup. */
104 segT seg
; /* The section this fixup is in. */
108 /* The list of unmatched HI relocs. */
110 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
113 /* start-sanitize-m32rx */
120 if (stdoutput
!= NULL
)
121 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
122 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
124 /* end-sanitize-m32rx */
126 #define M32R_SHORTOPTS ""
127 /* start-sanitize-phase2-m32rx */
128 #undef M32R_SHORTOPTS
129 #define M32R_SHORTOPTS "O"
130 /* end-sanitize-phase2-m32rx */
131 const char * md_shortopts
= M32R_SHORTOPTS
;
133 struct option md_longopts
[] =
135 /* start-sanitize-m32rx */
136 #define OPTION_M32RX (OPTION_MD_BASE)
137 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
138 #define OPTION_WARN (OPTION_MD_BASE + 1)
139 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN
},
140 {"Wp", no_argument
, NULL
, OPTION_WARN
},
141 #define OPTION_NO_WARN (OPTION_MD_BASE + 2)
142 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN
},
143 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN
},
144 /* end-sanitize-m32rx */
146 #if 0 /* not supported yet */
147 #define OPTION_RELAX (OPTION_MD_BASE + 3)
148 {"relax", no_argument
, NULL
, OPTION_RELAX
},
149 #define OPTION_CPU_DESC (OPTION_MD_BASE + 4)
150 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
153 {NULL
, no_argument
, NULL
, 0}
155 size_t md_longopts_size
= sizeof (md_longopts
);
158 md_parse_option (c
, arg
)
164 /* start-sanitize-m32rx */
165 /* start-sanitize-phase2-m32rx */
169 /* end-sanitize-phase2-m32rx */
176 warn_explicit_parallel_conflicts
= 1;
180 warn_explicit_parallel_conflicts
= 0;
182 /* end-sanitize-m32rx */
184 #if 0 /* not supported yet */
188 case OPTION_CPU_DESC
:
199 md_show_usage (stream
)
202 /* start-sanitize-m32rx */
203 fprintf (stream
, _("M32R/X specific command line options:\n"));
204 fprintf (stream
, _("\
205 --m32rx support the extended m32rx instruction set\n"));
207 /* start-sanitize-phase2-m32rx */
208 fprintf (stream
, _("\
209 -O try to combine instructions in parallel\n"));
210 /* end-sanitize-phase2-m32rx */
212 fprintf (stream
, _("\
213 --warn-explicit-parallel-conflicts warn when parallel instrucitons violate contraints\n"));
214 fprintf (stream
, _("\
215 --no-warn-explicit-parallel-conflicts do not warn when parallel instrucitons violate contraints\n"));
216 fprintf (stream
, _("\
217 --Wp synonym for --warn-explicit-parallel-conflicts\n"));
218 fprintf (stream
, _("\
219 --Wnp synonym for --no-warn-explicit-parallel-conflicts\n"));
220 /* end-sanitize-m32rx */
223 fprintf (stream
, _("\
224 --relax create linker relaxable code\n"));
225 fprintf (stream
, _("\
226 --cpu-desc provide runtime cpu description file\n"));
230 static void fill_insn
PARAMS ((int));
231 static void m32r_scomm
PARAMS ((int));
233 /* Set by md_assemble for use by m32r_fill_insn. */
234 static subsegT prev_subseg
;
235 static segT prev_seg
;
237 /* The target specific pseudo-ops which we support. */
238 const pseudo_typeS md_pseudo_table
[] =
241 { "fillinsn", fill_insn
, 0 },
242 { "scomm", m32r_scomm
, 0 },
243 /* start-sanitize-m32rx */
244 { "m32r", allow_m32rx
, 0},
245 { "m32rx", allow_m32rx
, 1},
246 /* end-sanitize-m32rx */
250 /* FIXME: Should be machine generated. */
251 #define NOP_INSN 0x7000
252 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
254 /* When we align the .text section, insert the correct NOP pattern.
255 N is the power of 2 alignment. LEN is the length of pattern FILL.
256 MAX is the maximum number of characters to skip when doing the alignment,
257 or 0 if there is no maximum. */
260 m32r_do_align (n
, fill
, len
, max
)
266 if ((fill
== NULL
|| (* fill
== 0 && len
== 1))
267 && (now_seg
->flags
& SEC_CODE
) != 0
268 /* Only do this special handling if aligning to at least a
271 /* Only do this special handling if we're allowed to emit at
273 && (max
== 0 || max
> 1))
275 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
278 /* First align to a 2 byte boundary, in case there is an odd .byte. */
279 /* FIXME: How much memory will cause gas to use when assembling a big
280 program? Perhaps we can avoid the frag_align call? */
281 frag_align (1, 0, 0);
283 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
285 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
286 /* If doing larger alignments use a repeating sequence of appropriate
290 static const unsigned char multi_nop_pattern
[] =
291 { 0x70, 0x00, 0xf0, 0x00 };
292 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
302 assemble_nop (opcode
)
305 char * f
= frag_more (2);
306 md_number_to_chars (f
, opcode
, 2);
309 /* If the last instruction was the first of 2 16 bit insns,
310 output a nop to move the PC to a 32 bit boundary.
312 This is done via an alignment specification since branch relaxing
313 may make it unnecessary.
315 Internally, we need to output one of these each time a 32 bit insn is
316 seen after an insn that is relaxable. */
322 (void) m32r_do_align (2, NULL
, 0, 0);
323 prev_insn
.insn
= NULL
;
324 seen_relaxable_p
= 0;
327 /* Cover function to fill_insn called after a label and at end of assembly.
329 The result is always 1: we're called in a conditional to see if the
330 current line is a label. */
333 m32r_fill_insn (done
)
336 if (prev_seg
!= NULL
)
339 subsegT subseg
= now_subseg
;
341 subseg_set (prev_seg
, prev_subseg
);
345 subseg_set (seg
, subseg
);
358 /* Initialize the `cgen' interface. */
360 /* This is a callback from cgen to gas to parse operands. */
361 cgen_parse_operand_fn
= cgen_parse_operand
;
363 /* Set the machine number and endian. */
364 CGEN_SYM (init_asm
) (0 /* mach number */,
366 CGEN_ENDIAN_BIG
: CGEN_ENDIAN_LITTLE
);
368 #if 0 /* not supported yet */
369 /* If a runtime cpu description file was provided, parse it. */
370 if (m32r_cpu_desc
!= NULL
)
374 errmsg
= cgen_read_cpu_file (m32r_cpu_desc
);
376 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
380 /* Save the current subseg so we can restore it [it's the default one and
381 we don't want the initial section to be .sbss]. */
385 /* The sbss section is for local .scomm symbols. */
386 sbss_section
= subseg_new (".sbss", 0);
388 /* This is copied from perform_an_assembly_pass. */
389 applicable
= bfd_applicable_section_flags (stdoutput
);
390 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
392 #if 0 /* What does this do? [see perform_an_assembly_pass] */
393 seg_info (bss_section
)->bss
= 1;
396 subseg_set (seg
, subseg
);
398 /* We must construct a fake section similar to bfd_com_section
399 but with the name .scommon. */
400 scom_section
= bfd_com_section
;
401 scom_section
.name
= ".scommon";
402 scom_section
.output_section
= & scom_section
;
403 scom_section
.symbol
= & scom_symbol
;
404 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
405 scom_symbol
= * bfd_com_section
.symbol
;
406 scom_symbol
.name
= ".scommon";
407 scom_symbol
.section
= & scom_section
;
409 /* start-sanitize-m32rx */
410 allow_m32rx (enable_m32rx
);
411 /* end-sanitize-m32rx */
414 /* start-sanitize-m32rx */
416 #define OPERAND_IS_COND_BIT(operand, indices, index) \
417 (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_COND \
418 || (CGEN_OPERAND_INSTANCE_HW (operand)->type == HW_H_CR \
419 && (indices [index] == 0 || indices [index] == 1)))
421 /* Returns true if an output of instruction 'a' is referenced by an operand
422 of instruction 'b'. If 'check_outputs' is true then b's outputs are
423 checked, otherwise its inputs are examined. */
426 first_writes_to_seconds_operands (a
, b
, check_outputs
)
429 const int check_outputs
;
431 const CGEN_OPERAND_INSTANCE
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
432 const CGEN_OPERAND_INSTANCE
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
435 /* If at least one of the instructions takes no operands, then there is
436 nothing to check. There really are instructions without operands,
438 if (a_operands
== NULL
|| b_ops
== NULL
)
441 /* Scan the operand list of 'a' looking for an output operand. */
443 CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
;
444 a_index
++, a_operands
++)
446 if (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) == CGEN_OPERAND_INSTANCE_OUTPUT
)
449 const CGEN_OPERAND_INSTANCE
* b_operands
= b_ops
;
452 The Condition bit 'C' is a shadow of the CBR register (control
453 register 1) and also a shadow of bit 31 of the program status
454 word (control register 0). For now this is handled here, rather
457 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
459 /* Scan operand list of 'b' looking for another reference to the
460 condition bit, which goes in the right direction. */
462 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
463 b_index
++, b_operands
++)
465 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
466 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
467 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
473 /* Scan operand list of 'b' looking for an operand that references
474 the same hardware element, and which goes in the right direction. */
476 CGEN_OPERAND_INSTANCE_TYPE (b_operands
) != CGEN_OPERAND_INSTANCE_END
;
477 b_index
++, b_operands
++)
479 if ((CGEN_OPERAND_INSTANCE_TYPE (b_operands
) ==
480 (check_outputs
? CGEN_OPERAND_INSTANCE_OUTPUT
: CGEN_OPERAND_INSTANCE_INPUT
))
481 && (CGEN_OPERAND_INSTANCE_HW (b_operands
) == CGEN_OPERAND_INSTANCE_HW (a_operands
))
482 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
492 /* Returns true if the insn can (potentially) alter the program counter. */
498 #if 0 /* Once PC operands are working.... */
499 const CGEN_OPERAND_INSTANCE
* a_operands
== CGEN_INSN_OPERANDS (a
->insn
);
501 if (a_operands
== NULL
)
504 while (CGEN_OPERAND_INSTANCE_TYPE (a_operands
) != CGEN_OPERAND_INSTANCE_END
)
506 if (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
) != NULL
507 && CGEN_OPERAND_INDEX (CGEN_OPERAND_INSTANCE_OPERAND (a_operands
)) == M32R_OPERAND_PC
)
513 if (CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_UNCOND_CTI
)
514 || CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_COND_CTI
))
520 /* Returns NULL if the two 16 bit insns can be executed in parallel,
521 otherwise it returns a pointer to an error message explaining why not. */
524 can_make_parallel (a
, b
)
531 /* Make sure the instructions are the right length. */
532 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
533 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
536 if (first_writes_to_seconds_operands (a
, b
, true))
537 return _("Instructions write to the same destination register.");
539 a_pipe
= CGEN_INSN_ATTR (a
->insn
, CGEN_INSN_PIPE
);
540 b_pipe
= CGEN_INSN_ATTR (b
->insn
, CGEN_INSN_PIPE
);
542 /* Make sure that the instructions use the correct execution pipelines. */
543 if ( a_pipe
== PIPE_NONE
544 || b_pipe
== PIPE_NONE
)
545 return _("Instructions do not use parallel execution pipelines.");
547 /* Leave this test for last, since it is the only test that can
548 go away if the instructions are swapped, and we want to make
549 sure that any other errors are detected before this happens. */
550 if ( a_pipe
== PIPE_S
552 return _("Instructions share the same execution pipeline");
559 make_parallel (buffer
)
560 cgen_insn_t
* buffer
;
562 /* Force the top bit of the second insn to be set. */
566 if (CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
)
568 value
= bfd_getb16 ((bfd_byte
*) buffer
);
570 bfd_putb16 (value
, (char *) buffer
);
574 value
= bfd_getl16 ((bfd_byte
*) buffer
);
576 bfd_putl16 (value
, (char *) buffer
);
581 make_parallel (buffer
)
584 /* Force the top bit of the second insn to be set. */
586 buffer
[CGEN_CURRENT_ENDIAN
== CGEN_ENDIAN_BIG
? 0 : 1] |= 0x80;
592 assemble_parallel_insn (str
, str2
)
601 * str2
= 0; /* Seperate the two instructions. */
603 /* If there was a previous 16 bit insn, then fill the following 16 bit slot,
604 so that the parallel instruction will start on a 32 bit boundary. */
608 /* Parse the first instruction. */
609 if (! (first
.insn
= CGEN_SYM (assemble_insn
)
610 (str
, & first
.fields
, first
.buffer
, & errmsg
)))
616 /* Check to see if this is an allowable parallel insn. */
617 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
619 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
624 && CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
626 as_bad (_("instruction '%s' is for the M32RX only"), str
);
631 If the instruciton is relaxable, reparse it looking for a non-relaxable variant.
632 (We do not want to relax instructions inside a parallel construction, and if it
633 turns out that the branch is too far for the displacement field available to the
634 non-relaxed instruction, then this is the programmer's fault.
635 A better solution would be to pass attribute requirements to assemble_insn() so
636 that the relaxable variant would not be accepted as a valid parse of the instruction. */
638 if (CGEN_INSN_ATTR (first
.insn
, CGEN_INSN_RELAXABLE
) != 0)
642 /* Oh dear - the insn is relaxable, so it might be replaced with a longer,
643 non-parallel version. Try appending ".s" to the instruction and reparsing it. */
645 p
= strchr (str
, ' ');
649 sprintf (buf
, "%s.s %s", str
, p
+ 1);
652 /* Reset fixup list to empty. */
655 first
.insn
= CGEN_SYM (assemble_insn
) (buf
, & first
.fields
, first
.buffer
, & errmsg
);
657 if (first
.insn
== NULL
)
661 *str2
= '|'; /* Restore the original assembly text, just in case it is needed. */
662 str3
= str
; /* Save the original string pointer. */
663 str
= str2
+ 2; /* Advanced past the parsed string. */
664 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
666 /* Preserve any fixups that have been generated and reset the list to empty. */
669 /* Get the indicies of the operands of the instruction. */
670 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
671 doesn't seem right. Perhaps allow passing fields like we do insn. */
672 /* FIXME: ALIAS insns do not have operands, so we use this function
673 to find the equivalent insn and overwrite the value stored in our
674 structure. We still need the original insn, however, since this
675 may have certain attributes that are not present in the unaliased
676 version (eg relaxability). When aliases behave differently this
677 may have to change. */
678 first
.orig_insn
= first
.insn
;
679 first
.insn
= m32r_cgen_get_insn_operands (first
.insn
, bfd_getb16 ((char *) first
.buffer
), 16,
681 if (first
.insn
== NULL
)
682 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed for first insn"));
684 /* Parse the second instruction. */
685 if (! (second
.insn
= CGEN_SYM (assemble_insn
)
686 (str
, & second
.fields
, second
.buffer
, & errmsg
)))
694 && CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
696 as_bad (_("instruction '%s' is for the M32RX only"), str
);
702 if ( strcmp (first
.insn
->name
, "nop") != 0
703 && strcmp (second
.insn
->name
, "nop") != 0)
705 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
710 /* See comment above. */
711 if (CGEN_INSN_ATTR (second
.insn
, CGEN_INSN_RELAXABLE
) != 0)
715 /* Oh dear - the insn is relaxable, so it might be replaced with a longer,
716 non-parallel version. Try appending ".s" to the instruction and reparsing it. */
718 p
= strchr (str
, ' ');
722 sprintf (buf
, "%s.s %s", str
, p
+ 1);
725 /* Reset fixup list to empty, preserving saved fixups. */
726 cgen_restore_fixups();
729 second
.insn
= CGEN_SYM (assemble_insn
) (buf
, & second
.fields
, second
.buffer
, & errmsg
);
731 if (second
.insn
== NULL
)
735 /* Get the indicies of the operands of the instruction. */
736 second
.orig_insn
= second
.insn
;
737 second
.insn
= m32r_cgen_get_insn_operands (second
.insn
, bfd_getb16 ((char *) second
.buffer
), 16,
739 if (second
.insn
== NULL
)
740 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed for second insn"));
742 /* We assume that if the first instruction writes to a register that is
743 read by the second instruction it is because the programmer intended
744 this to happen, (after all they have explicitly requested that these
745 two instructions be executed in parallel). Although if the global
746 variable warn_explicit_parallel_conflicts is true then we do generate
747 a warning message. Similarly we assume that parallel branch and jump
748 instructions are deliberate and should not produce errors. */
750 if (warn_explicit_parallel_conflicts
)
752 if (first_writes_to_seconds_operands (& first
, & second
, false))
753 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
755 if (first_writes_to_seconds_operands (& second
, & first
, false))
756 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
759 if ((errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
761 /* Get the fixups for the first instruction. */
765 (void) cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
766 CGEN_FIELDS_BITSIZE (& first
.fields
));
768 /* Force the top bit of the second insn to be set. */
769 make_parallel (second
.buffer
);
771 /* Get its fixups. */
772 cgen_restore_fixups ();
775 (void) cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
776 CGEN_FIELDS_BITSIZE (& second
.fields
));
778 /* Try swapping the instructions to see if they work that way. */
779 else if (can_make_parallel (& second
, & first
) == NULL
)
781 /* Write out the second instruction first. */
782 (void) cgen_asm_finish_insn (second
.orig_insn
, second
.buffer
,
783 CGEN_FIELDS_BITSIZE (& second
.fields
));
785 /* Force the top bit of the first instruction to be set. */
786 make_parallel (first
.buffer
);
788 /* Get the fixups for the first instruction. */
789 cgen_restore_fixups ();
791 /* Write out the first instruction. */
792 (void) cgen_asm_finish_insn (first
.orig_insn
, first
.buffer
,
793 CGEN_FIELDS_BITSIZE (& first
.fields
));
797 as_bad ("'%s': %s", str2
, errmsg
);
801 /* Set these so m32r_fill_insn can use them. */
803 prev_subseg
= now_subseg
;
808 /* end-sanitize-m32rx */
819 /* Initialize GAS's cgen interface for a new instruction. */
820 cgen_asm_init_parse ();
822 /* start-sanitize-m32rx */
823 /* Look for a parallel instruction seperator. */
824 if ((str2
= strstr (str
, "||")) != NULL
)
826 assemble_parallel_insn (str
, str2
);
829 /* end-sanitize-m32rx */
831 insn
.insn
= CGEN_SYM (assemble_insn
) (str
, & insn
.fields
, insn
.buffer
, & errmsg
);
838 /* start-sanitize-m32rx */
839 if (! enable_m32rx
&& CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
841 as_bad (_("instruction '%s' is for the M32RX only"), str
);
844 /* end-sanitize-m32rx */
846 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
848 /* 32 bit insns must live on 32 bit boundaries. */
849 if (prev_insn
.insn
|| seen_relaxable_p
)
851 /* ??? If calling fill_insn too many times turns us into a memory
852 pig, can we call assemble_nop instead of !seen_relaxable_p? */
856 (void) cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
857 CGEN_FIELDS_BITSIZE (& insn
.fields
));
861 /* start-sanitize-m32rx */
862 /* start-sanitize-phase2-m32rx */
864 /* end-sanitize-phase2-m32rx */
865 /* end-sanitize-m32rx */
867 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
870 /* Get the indices of the operands of the instruction. */
871 insn
.insn
= m32r_cgen_get_insn_operands (insn
.insn
,
872 bfd_getb16 ((char *) insn
.buffer
),
875 if (insn
.insn
== NULL
)
876 as_fatal (_("internal error: m32r_cgen_get_insn_operands failed"));
878 /* Keep track of whether we've seen a pair of 16 bit insns.
879 prev_insn.insn is NULL when we're on a 32 bit boundary. */
882 /* start-sanitize-m32rx */
883 /* start-sanitize-phase2-m32rx */
884 /* Look to see if this instruction can be combined with the
885 previous instruction to make one, parallel, 32 bit instruction.
886 If the previous instruction (potentially) changed the flow of
887 program control, then it cannot be combined with the current
888 instruction. If the current instruction is relaxable, then it
889 might be replaced with a longer version, so we cannot combine it.
890 Also if the output of the previous instruction is used as an
891 input to the current instruction then it cannot be combined.
892 Otherwise call can_make_parallel() with both orderings of the
893 instructions to see if they can be combined. */
896 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_RELAXABLE
) == 0
897 && ! writes_to_pc (& prev_insn
)
898 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
901 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
902 make_parallel (insn
.buffer
);
903 else if (can_make_parallel (& insn
, & prev_insn
.insn
) == NULL
)
906 /* end-sanitize-phase2-m32rx */
907 /* end-sanitize-m32rx */
909 prev_insn
.insn
= NULL
;
916 /* Record the frag that might be used by this insn. */
917 insn
.frag
= frag_now
;
918 insn
.addr
= cgen_asm_finish_insn (insn
.insn
, insn
.buffer
,
919 CGEN_FIELDS_BITSIZE (& insn
.fields
));
921 /* start-sanitize-m32rx */
922 /* start-sanitize-phase2-m32rx */
927 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
929 /* Swap the two insns */
930 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
931 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
933 make_parallel (insn
.addr
);
935 /* Swap any relaxable frags recorded for the two insns. */
936 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
937 prev_insn
.frag
->fr_opcode
= insn
.addr
;
938 else if (insn
.frag
->fr_opcode
== insn
.addr
)
939 insn
.frag
->fr_opcode
= prev_insn
.addr
;
941 /* end-sanitize-phase2-m32rx */
943 /* Record where this instruction was assembled. */
944 prev_insn
.addr
= insn
.addr
;
945 prev_insn
.frag
= insn
.frag
;
946 /* end-sanitize-m32rx */
948 /* If the insn needs the following one to be on a 32 bit boundary
949 (e.g. subroutine calls), fill this insn's slot. */
950 if (prev_insn
.insn
!= NULL
951 && CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_FILL_SLOT
) != 0)
954 /* If this is a relaxable insn (can be replaced with a larger version)
955 mark the fact so that we can emit an alignment directive for a
956 following 32 bit insn if we see one. */
957 if (CGEN_INSN_ATTR (insn
.insn
, CGEN_INSN_RELAXABLE
) != 0)
958 seen_relaxable_p
= 1;
961 /* Set these so m32r_fill_insn can use them. */
963 prev_subseg
= now_subseg
;
966 /* The syntax in the manual says constants begin with '#'.
967 We just ignore it. */
970 md_operand (expressionP
)
971 expressionS
* expressionP
;
973 if (* input_line_pointer
== '#')
975 input_line_pointer
++;
976 expression (expressionP
);
981 md_section_align (segment
, size
)
985 int align
= bfd_get_section_alignment (stdoutput
, segment
);
986 return ((size
+ (1 << align
) - 1) & (-1 << align
));
990 md_undefined_symbol (name
)
996 /* .scomm pseudo-op handler.
998 This is a new pseudo-op to handle putting objects in .scommon.
999 By doing this the linker won't need to do any work and more importantly
1000 it removes the implicit -G arg necessary to correctly link the object file.
1007 register char * name
;
1011 register symbolS
* symbolP
;
1015 name
= input_line_pointer
;
1016 c
= get_symbol_end ();
1018 /* just after name is now '\0' */
1019 p
= input_line_pointer
;
1022 if (* input_line_pointer
!= ',')
1024 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1025 ignore_rest_of_line ();
1029 input_line_pointer
++; /* skip ',' */
1030 if ((size
= get_absolute_expression ()) < 0)
1032 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1033 ignore_rest_of_line ();
1037 /* The third argument to .scomm is the alignment. */
1038 if (* input_line_pointer
!= ',')
1042 ++ input_line_pointer
;
1043 align
= get_absolute_expression ();
1046 as_warn (_("ignoring bad alignment"));
1050 /* Convert to a power of 2 alignment. */
1053 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1057 as_bad (_("Common alignment not a power of 2"));
1058 ignore_rest_of_line ();
1066 symbolP
= symbol_find_or_make (name
);
1069 if (S_IS_DEFINED (symbolP
))
1071 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1072 S_GET_NAME (symbolP
));
1073 ignore_rest_of_line ();
1077 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1079 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1080 S_GET_NAME (symbolP
),
1081 (long) S_GET_VALUE (symbolP
),
1084 ignore_rest_of_line ();
1090 segT old_sec
= now_seg
;
1091 int old_subsec
= now_subseg
;
1094 record_alignment (sbss_section
, align2
);
1095 subseg_set (sbss_section
, 0);
1098 frag_align (align2
, 0, 0);
1100 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1101 symbolP
->sy_frag
->fr_symbol
= 0;
1103 symbolP
->sy_frag
= frag_now
;
1105 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1108 S_SET_SIZE (symbolP
, size
);
1109 S_SET_SEGMENT (symbolP
, sbss_section
);
1110 S_CLEAR_EXTERNAL (symbolP
);
1111 subseg_set (old_sec
, old_subsec
);
1115 S_SET_VALUE (symbolP
, (valueT
) size
);
1116 S_SET_ALIGN (symbolP
, align2
);
1117 S_SET_EXTERNAL (symbolP
);
1118 S_SET_SEGMENT (symbolP
, & scom_section
);
1121 demand_empty_rest_of_line ();
1124 /* Interface to relax_segment. */
1126 /* FIXME: Build table by hand, get it working, then machine generate. */
1128 const relax_typeS md_relax_table
[] =
1131 1) most positive reach of this state,
1132 2) most negative reach of this state,
1133 3) how many bytes this mode will add to the size of the current frag
1134 4) which index into the table to try if we can't fit into this one. */
1136 /* The first entry must be unused because an `rlx_more' value of zero ends
1140 /* The displacement used by GAS is from the end of the 2 byte insn,
1141 so we subtract 2 from the following. */
1142 /* 16 bit insn, 8 bit disp -> 10 bit range.
1143 This doesn't handle a branch in the right slot at the border:
1144 the "& -4" isn't taken into account. It's not important enough to
1145 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1147 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1148 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1149 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1150 /* Same thing, but with leading nop for alignment. */
1151 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1155 m32r_relax_frag (fragP
, stretch
)
1159 /* Address of branch insn. */
1160 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1163 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1164 if (fragP
->fr_subtype
== 2)
1166 if ((address
& 3) != 0)
1168 fragP
->fr_subtype
= 3;
1172 else if (fragP
->fr_subtype
== 3)
1174 if ((address
& 3) == 0)
1176 fragP
->fr_subtype
= 2;
1182 growth
= relax_frag (fragP
, stretch
);
1184 /* Long jump on odd halfword boundary? */
1185 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1187 fragP
->fr_subtype
= 3;
1195 /* Return an initial guess of the length by which a fragment must grow to
1196 hold a branch to reach its destination.
1197 Also updates fr_type/fr_subtype as necessary.
1199 Called just before doing relaxation.
1200 Any symbol that is now undefined will not become defined.
1201 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1202 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1203 Although it may not be explicit in the frag, pretend fr_var starts with a
1207 md_estimate_size_before_relax (fragP
, segment
)
1211 int old_fr_fix
= fragP
->fr_fix
;
1212 char * opcode
= fragP
->fr_opcode
;
1214 /* The only thing we have to handle here are symbols outside of the
1215 current segment. They may be undefined or in a different segment in
1216 which case linker scripts may place them anywhere.
1217 However, we can't finish the fragment here and emit the reloc as insn
1218 alignment requirements may move the insn about. */
1220 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1222 /* The symbol is undefined in this segment.
1223 Change the relaxation subtype to the max allowable and leave
1224 all further handling to md_convert_frag. */
1225 fragP
->fr_subtype
= 2;
1227 #if 0 /* Can't use this, but leave in for illustration. */
1228 /* Change 16 bit insn to 32 bit insn. */
1231 /* Increase known (fixed) size of fragment. */
1234 /* Create a relocation for it. */
1235 fix_new (fragP
, old_fr_fix
, 4,
1237 fragP
->fr_offset
, 1 /* pcrel */,
1238 /* FIXME: Can't use a real BFD reloc here.
1239 cgen_md_apply_fix3 can't handle it. */
1240 BFD_RELOC_M32R_26_PCREL
);
1242 /* Mark this fragment as finished. */
1246 const CGEN_INSN
* insn
;
1249 /* Update the recorded insn.
1250 Fortunately we don't have to look very far.
1251 FIXME: Change this to record in the instruction the next higher
1252 relaxable insn to use. */
1253 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1255 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1256 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1258 && CGEN_INSN_ATTR (insn
, CGEN_INSN_RELAX
))
1264 fragP
->fr_cgen
.insn
= insn
;
1270 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1273 /* *fragP has been relaxed to its final size, and now needs to have
1274 the bytes inside it modified to conform to the new size.
1276 Called after relaxation is finished.
1277 fragP->fr_type == rs_machine_dependent.
1278 fragP->fr_subtype is the subtype of what the address relaxed to. */
1281 md_convert_frag (abfd
, sec
, fragP
)
1287 char * displacement
;
1293 opcode
= fragP
->fr_opcode
;
1295 /* Address opcode resides at in file space. */
1296 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1298 switch (fragP
->fr_subtype
)
1302 displacement
= & opcode
[1];
1307 displacement
= & opcode
[1];
1310 opcode
[2] = opcode
[0] | 0x80;
1311 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1312 opcode_address
+= 2;
1314 displacement
= & opcode
[3];
1320 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1322 /* symbol must be resolved by linker */
1323 if (fragP
->fr_offset
& 3)
1324 as_warn (_("Addend to unresolved symbol not on word boundary."));
1325 addend
= fragP
->fr_offset
>> 2;
1329 /* Address we want to reach in file space. */
1330 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1331 target_address
+= fragP
->fr_symbol
->sy_frag
->fr_address
;
1332 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1335 /* Create a relocation for symbols that must be resolved by the linker.
1336 Otherwise output the completed insn. */
1338 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1340 assert (fragP
->fr_subtype
!= 1);
1341 assert (fragP
->fr_cgen
.insn
!= 0);
1342 cgen_record_fixup (fragP
,
1343 /* Offset of branch insn in frag. */
1344 fragP
->fr_fix
+ extension
- 4,
1345 fragP
->fr_cgen
.insn
,
1347 /* FIXME: quick hack */
1349 CGEN_OPERAND_ENTRY (fragP
->fr_cgen
.opindex
),
1351 CGEN_OPERAND_ENTRY (M32R_OPERAND_DISP24
),
1353 fragP
->fr_cgen
.opinfo
,
1354 fragP
->fr_symbol
, fragP
->fr_offset
);
1357 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1359 md_number_to_chars (displacement
, (valueT
) addend
,
1360 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1362 fragP
->fr_fix
+= extension
;
1365 /* Functions concerning relocs. */
1367 /* The location from which a PC relative jump should be calculated,
1368 given a PC relative reloc. */
1371 md_pcrel_from_section (fixP
, sec
)
1375 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1376 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1377 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1379 /* The symbol is undefined (or is defined but not in this section).
1380 Let the linker figure it out. */
1384 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1387 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1388 Returns BFD_RELOC_NONE if no reloc type can be found.
1389 *FIXP may be modified if desired. */
1391 bfd_reloc_code_real_type
1392 CGEN_SYM (lookup_reloc
) (insn
, operand
, fixP
)
1393 const CGEN_INSN
* insn
;
1394 const CGEN_OPERAND
* operand
;
1397 switch (CGEN_OPERAND_TYPE (operand
))
1399 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1400 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1401 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1402 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1403 case M32R_OPERAND_HI16
:
1404 case M32R_OPERAND_SLO16
:
1405 case M32R_OPERAND_ULO16
:
1406 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1407 if (fixP
->tc_fix_data
.opinfo
!= 0)
1408 return fixP
->tc_fix_data
.opinfo
;
1411 return BFD_RELOC_NONE
;
1414 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1417 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1422 struct m32r_hi_fixup
* hi_fixup
;
1424 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1425 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1427 hi_fixup
= ((struct m32r_hi_fixup
*)
1428 xmalloc (sizeof (struct m32r_hi_fixup
)));
1429 hi_fixup
->fixp
= fixP
;
1430 hi_fixup
->seg
= now_seg
;
1431 hi_fixup
->next
= m32r_hi_fixup_list
;
1433 m32r_hi_fixup_list
= hi_fixup
;
1436 /* Called while parsing an instruction to create a fixup.
1437 We need to check for HI16 relocs and queue them up for later sorting. */
1440 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1443 const CGEN_INSN
* insn
;
1445 const CGEN_OPERAND
* operand
;
1449 fixS
* fixP
= cgen_record_fixup_exp (frag
, where
, insn
, length
,
1450 operand
, opinfo
, exp
);
1452 switch (CGEN_OPERAND_TYPE (operand
))
1454 case M32R_OPERAND_HI16
:
1455 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1456 if (fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1457 || fixP
->tc_fix_data
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1458 m32r_record_hi16 (fixP
->tc_fix_data
.opinfo
, fixP
, now_seg
);
1465 /* Return BFD reloc type from opinfo field in a fixS.
1466 It's tricky using fx_r_type in m32r_frob_file because the values
1467 are BFD_RELOC_UNUSED + operand number. */
1468 #define FX_OPINFO_R_TYPE(f) ((f)->tc_fix_data.opinfo)
1470 /* Sort any unmatched HI16 relocs so that they immediately precede
1471 the corresponding LO16 reloc. This is called before md_apply_fix and
1477 struct m32r_hi_fixup
* l
;
1479 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1481 segment_info_type
* seginfo
;
1484 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1485 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1487 /* Check quickly whether the next fixup happens to be a matching low. */
1488 if (l
->fixp
->fx_next
!= NULL
1489 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1490 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1491 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1494 /* Look through the fixups for this segment for a matching `low'.
1495 When we find one, move the high/shigh just in front of it. We do
1496 this in two passes. In the first pass, we try to find a
1497 unique `low'. In the second pass, we permit multiple high's
1498 relocs for a single `low'. */
1499 seginfo
= seg_info (l
->seg
);
1500 for (pass
= 0; pass
< 2; pass
++)
1506 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1508 /* Check whether this is a `low' fixup which matches l->fixp. */
1509 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1510 && f
->fx_addsy
== l
->fixp
->fx_addsy
1511 && f
->fx_offset
== l
->fixp
->fx_offset
1514 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1515 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1516 || prev
->fx_addsy
!= f
->fx_addsy
1517 || prev
->fx_offset
!= f
->fx_offset
))
1521 /* Move l->fixp before f. */
1522 for (pf
= &seginfo
->fix_root
;
1524 pf
= & (* pf
)->fx_next
)
1525 assert (* pf
!= NULL
);
1527 * pf
= l
->fixp
->fx_next
;
1529 l
->fixp
->fx_next
= f
;
1531 seginfo
->fix_root
= l
->fixp
;
1533 prev
->fx_next
= l
->fixp
;
1545 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1546 _("Unmatched high/shigh reloc"));
1551 /* See whether we need to force a relocation into the output file.
1552 This is used to force out switch and PC relative relocations when
1556 m32r_force_relocation (fix
)
1562 return (fix
->fx_pcrel
1566 /* Write a value out to the object file, using the appropriate endianness. */
1569 md_number_to_chars (buf
, val
, n
)
1574 if (target_big_endian
)
1575 number_to_chars_bigendian (buf
, val
, n
);
1577 number_to_chars_littleendian (buf
, val
, n
);
1580 /* Turn a string in input_line_pointer into a floating point constant of type
1581 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1582 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1585 /* Equal to MAX_PRECISION in atof-ieee.c */
1586 #define MAX_LITTLENUMS 6
1589 md_atof (type
, litP
, sizeP
)
1596 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1597 LITTLENUM_TYPE
* wordP
;
1599 char * atof_ieee ();
1617 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1621 return _("Bad call to md_atof()");
1624 t
= atof_ieee (input_line_pointer
, type
, words
);
1626 input_line_pointer
= t
;
1627 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1629 if (target_big_endian
)
1631 for (i
= 0; i
< prec
; i
++)
1633 md_number_to_chars (litP
, (valueT
) words
[i
],
1634 sizeof (LITTLENUM_TYPE
));
1635 litP
+= sizeof (LITTLENUM_TYPE
);
1640 for (i
= prec
- 1; i
>= 0; i
--)
1642 md_number_to_chars (litP
, (valueT
) words
[i
],
1643 sizeof (LITTLENUM_TYPE
));
1644 litP
+= sizeof (LITTLENUM_TYPE
);
1652 m32r_elf_section_change_hook ()
1654 /* If we have reached the end of a section and we have just emitted a
1655 16 bit insn, then emit a nop to make sure that the section ends on
1656 a 32 bit boundary. */
1658 if (prev_insn
.insn
|| seen_relaxable_p
)
1659 (void) m32r_fill_insn (0);