1 /* tc-m32r.c -- Assembler for the Mitsubishi M32R.
2 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "opcodes/m32r-desc.h"
27 #include "opcodes/m32r-opc.h"
30 /* Linked list of symbols that are debugging symbols to be defined as the
31 beginning of the current instruction. */
32 typedef struct sym_link
34 struct sym_link
*next
;
38 static sym_linkS
*debug_sym_link
= (sym_linkS
*)0;
40 /* Structure to hold all of the different components describing
41 an individual instruction. */
44 const CGEN_INSN
* insn
;
45 const CGEN_INSN
* orig_insn
;
48 CGEN_INSN_INT buffer
[1];
49 #define INSN_VALUE(buf) (*(buf))
51 unsigned char buffer
[CGEN_MAX_INSN_SIZE
];
52 #define INSN_VALUE(buf) (buf)
57 fixS
* fixups
[GAS_CGEN_MAX_FIXUPS
];
58 int indices
[MAX_OPERAND_INSTANCES
];
59 sym_linkS
*debug_sym_link
;
63 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit
64 boundary (i.e. was the first of two 16 bit insns). */
65 static m32r_insn prev_insn
;
67 /* Non-zero if we've seen a relaxable insn since the last 32 bit
69 static int seen_relaxable_p
= 0;
71 /* Non-zero if -relax specified, in which case sufficient relocs are output
72 for the linker to do relaxing.
73 We do simple forms of relaxing internally, but they are always done.
74 This flag does not apply to them. */
75 static int m32r_relax
;
77 #if 0 /* not supported yet */
78 /* If non-NULL, pointer to cpu description file to read.
79 This allows runtime additions to the assembler. */
80 static const char * m32r_cpu_desc
;
83 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
84 Each high/shigh reloc must be paired with it's low cousin in order to
85 properly calculate the addend in a relocatable link (since there is a
86 potential carry from the low to the high/shigh).
87 This option is off by default though for user-written assembler code it
88 might make sense to make the default be on (i.e. have gcc pass a flag
89 to turn it off). This warning must not be on for GCC created code as
90 optimization may delete the low but not the high/shigh (at least we
91 shouldn't assume or require it to). */
92 static int warn_unmatched_high
= 0;
94 /* Non-zero if -m32rx has been specified, in which case support for the
95 extended M32RX instruction set should be enabled. */
96 static int enable_m32rx
= 0;
98 /* Non-zero if -m32rx -hidden has been specified, in which case support for
99 the special M32RX instruction set should be enabled. */
100 static int enable_special
= 0;
102 /* Non-zero if the programmer should be warned when an explicit parallel
103 instruction might have constraint violations. */
104 static int warn_explicit_parallel_conflicts
= 1;
106 /* Non-zero if insns can be made parallel. */
109 /* stuff for .scomm symbols. */
110 static segT sbss_section
;
111 static asection scom_section
;
112 static asymbol scom_symbol
;
114 const char comment_chars
[] = ";";
115 const char line_comment_chars
[] = "#";
116 const char line_separator_chars
[] = "";
117 const char EXP_CHARS
[] = "eE";
118 const char FLT_CHARS
[] = "dD";
120 /* Relocations against symbols are done in two
121 parts, with a HI relocation and a LO relocation. Each relocation
122 has only 16 bits of space to store an addend. This means that in
123 order for the linker to handle carries correctly, it must be able
124 to locate both the HI and the LO relocation. This means that the
125 relocations must appear in order in the relocation table.
127 In order to implement this, we keep track of each unmatched HI
128 relocation. We then sort them so that they immediately precede the
129 corresponding LO relocation. */
133 struct m32r_hi_fixup
* next
; /* Next HI fixup. */
134 fixS
* fixp
; /* This fixup. */
135 segT seg
; /* The section this fixup is in. */
139 /* The list of unmatched HI relocs. */
141 static struct m32r_hi_fixup
* m32r_hi_fixup_list
;
150 if (stdoutput
!= NULL
)
151 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
,
152 enable_m32rx
? bfd_mach_m32rx
: bfd_mach_m32r
);
155 #define M32R_SHORTOPTS "O"
156 const char * md_shortopts
= M32R_SHORTOPTS
;
158 struct option md_longopts
[] =
160 #define OPTION_M32RX (OPTION_MD_BASE)
161 {"m32rx", no_argument
, NULL
, OPTION_M32RX
},
162 #define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
163 {"warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
164 {"Wp", no_argument
, NULL
, OPTION_WARN_PARALLEL
},
165 #define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
166 {"no-warn-explicit-parallel-conflicts", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
167 {"Wnp", no_argument
, NULL
, OPTION_NO_WARN_PARALLEL
},
168 #define OPTION_SPECIAL (OPTION_MD_BASE + 3)
169 {"hidden", no_argument
, NULL
, OPTION_SPECIAL
},
171 /* Sigh. I guess all warnings must now have both variants. */
172 #define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
173 {"warn-unmatched-high", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
174 {"Wuh", no_argument
, NULL
, OPTION_WARN_UNMATCHED
},
175 #define OPTION_NO_WARN_UNMATCHED (OPTION_MD_BASE + 5)
176 {"no-warn-unmatched-high", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
177 {"Wnuh", no_argument
, NULL
, OPTION_NO_WARN_UNMATCHED
},
179 #if 0 /* not supported yet */
180 #define OPTION_RELAX (OPTION_MD_BASE + 6)
181 {"relax", no_argument
, NULL
, OPTION_RELAX
},
182 #define OPTION_CPU_DESC (OPTION_MD_BASE + 7)
183 {"cpu-desc", required_argument
, NULL
, OPTION_CPU_DESC
},
185 {NULL
, no_argument
, NULL
, 0}
187 size_t md_longopts_size
= sizeof (md_longopts
);
190 md_parse_option (c
, arg
)
204 case OPTION_WARN_PARALLEL
:
205 warn_explicit_parallel_conflicts
= 1;
208 case OPTION_NO_WARN_PARALLEL
:
209 warn_explicit_parallel_conflicts
= 0;
217 /* Pretend that we do not recognise this option. */
218 as_bad (_("Unrecognised option: -hidden"));
223 case OPTION_WARN_UNMATCHED
:
224 warn_unmatched_high
= 1;
227 case OPTION_NO_WARN_UNMATCHED
:
228 warn_unmatched_high
= 0;
231 #if 0 /* not supported yet */
235 case OPTION_CPU_DESC
:
248 md_show_usage (stream
)
251 fprintf (stream
, _(" M32R specific command line options:\n"));
253 fprintf (stream
, _("\
254 -m32rx support the extended m32rx instruction set\n"));
255 fprintf (stream
, _("\
256 -O try to combine instructions in parallel\n"));
258 fprintf (stream
, _("\
259 -warn-explicit-parallel-conflicts warn when parallel instructions\n"));
260 fprintf (stream
, _("\
261 violate contraints\n"));
262 fprintf (stream
, _("\
263 -no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
264 fprintf (stream
, _("\
265 instructions violate contraints\n"));
266 fprintf (stream
, _("\
267 -Wp synonym for -warn-explicit-parallel-conflicts\n"));
268 fprintf (stream
, _("\
269 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
271 fprintf (stream
, _("\
272 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
273 fprintf (stream
, _("\
274 -no-warn-unmatched-high do not warn about missing low relocs\n"));
275 fprintf (stream
, _("\
276 -Wuh synonym for -warn-unmatched-high\n"));
277 fprintf (stream
, _("\
278 -Wnuh synonym for -no-warn-unmatched-high\n"));
281 fprintf (stream
, _("\
282 -relax create linker relaxable code\n"));
283 fprintf (stream
, _("\
284 -cpu-desc provide runtime cpu description file\n"));
288 static void fill_insn
PARAMS ((int));
289 static void m32r_scomm
PARAMS ((int));
290 static void debug_sym
PARAMS ((int));
291 static void expand_debug_syms
PARAMS ((sym_linkS
*, int));
293 /* Set by md_assemble for use by m32r_fill_insn. */
294 static subsegT prev_subseg
;
295 static segT prev_seg
;
297 /* The target specific pseudo-ops which we support. */
298 const pseudo_typeS md_pseudo_table
[] =
301 { "fillinsn", fill_insn
, 0 },
302 { "scomm", m32r_scomm
, 0 },
303 { "debugsym", debug_sym
, 0 },
304 /* Not documented as so far there is no need for them.... */
305 { "m32r", allow_m32rx
, 0 },
306 { "m32rx", allow_m32rx
, 1 },
310 /* FIXME: Should be machine generated. */
311 #define NOP_INSN 0x7000
312 #define PAR_NOP_INSN 0xf000 /* can only be used in 2nd slot */
314 /* When we align the .text section, insert the correct NOP pattern.
315 N is the power of 2 alignment. LEN is the length of pattern FILL.
316 MAX is the maximum number of characters to skip when doing the alignment,
317 or 0 if there is no maximum. */
320 m32r_do_align (n
, fill
, len
, max
)
326 /* Only do this if the fill pattern wasn't specified. */
328 && subseg_text_p (now_seg
)
329 /* Only do this special handling if aligning to at least a
332 /* Only do this special handling if we're allowed to emit at
334 && (max
== 0 || max
> 1))
336 static const unsigned char nop_pattern
[] = { 0xf0, 0x00 };
339 /* First align to a 2 byte boundary, in case there is an odd .byte. */
340 /* FIXME: How much memory will cause gas to use when assembling a big
341 program? Perhaps we can avoid the frag_align call? */
342 frag_align (1, 0, 0);
344 /* Next align to a 4 byte boundary (we know n >= 2) using a parallel
346 frag_align_pattern (2, nop_pattern
, sizeof nop_pattern
, 0);
347 /* If doing larger alignments use a repeating sequence of appropriate
351 static const unsigned char multi_nop_pattern
[] =
352 { 0x70, 0x00, 0xf0, 0x00 };
353 frag_align_pattern (n
, multi_nop_pattern
, sizeof multi_nop_pattern
,
357 prev_insn
.insn
= NULL
;
364 /* If the last instruction was the first of 2 16 bit insns,
365 output a nop to move the PC to a 32 bit boundary.
367 This is done via an alignment specification since branch relaxing
368 may make it unnecessary.
370 Internally, we need to output one of these each time a 32 bit insn is
371 seen after an insn that is relaxable. */
377 (void) m32r_do_align (2, NULL
, 0, 0);
378 prev_insn
.insn
= NULL
;
379 seen_relaxable_p
= 0;
382 /* Record the symbol so that when we output the insn, we can create
383 a symbol that is at the start of the instruction. This is used
384 to emit the label for the start of a breakpoint without causing
385 the assembler to emit a NOP if the previous instruction was a
386 16 bit instruction. */
394 register char *end_name
;
395 register symbolS
*symbolP
;
396 register sym_linkS
*link
;
398 name
= input_line_pointer
;
399 delim
= get_symbol_end ();
400 end_name
= input_line_pointer
;
402 if ((symbolP
= symbol_find (name
)) == NULL
403 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
405 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
408 symbol_table_insert (symbolP
);
409 if (S_IS_DEFINED (symbolP
) && S_GET_SEGMENT (symbolP
) != reg_section
)
410 /* xgettext:c-format */
411 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
415 link
= (sym_linkS
*) xmalloc (sizeof (sym_linkS
));
416 link
->symbol
= symbolP
;
417 link
->next
= debug_sym_link
;
418 debug_sym_link
= link
;
419 symbol_get_obj (symbolP
)->local
= 1;
423 demand_empty_rest_of_line ();
426 /* Second pass to expanding the debug symbols, go through linked
427 list of symbols and reassign the address. */
430 expand_debug_syms (syms
, align
)
434 char *save_input_line
= input_line_pointer
;
435 sym_linkS
*next_syms
;
440 (void) m32r_do_align (align
, NULL
, 0, 0);
441 for (; syms
!= (sym_linkS
*)0; syms
= next_syms
)
443 symbolS
*symbolP
= syms
->symbol
;
444 next_syms
= syms
->next
;
445 input_line_pointer
= ".\n";
446 pseudo_set (symbolP
);
450 input_line_pointer
= save_input_line
;
453 /* Cover function to fill_insn called after a label and at end of assembly.
454 The result is always 1: we're called in a conditional to see if the
455 current line is a label. */
458 m32r_fill_insn (done
)
461 if (prev_seg
!= NULL
)
464 subsegT subseg
= now_subseg
;
466 subseg_set (prev_seg
, prev_subseg
);
470 subseg_set (seg
, subseg
);
473 if (done
&& debug_sym_link
)
475 expand_debug_syms (debug_sym_link
, 1);
476 debug_sym_link
= (sym_linkS
*)0;
489 /* Initialize the `cgen' interface. */
491 /* Set the machine number and endian. */
492 gas_cgen_cpu_desc
= m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS
, 0,
493 CGEN_CPU_OPEN_ENDIAN
,
496 m32r_cgen_init_asm (gas_cgen_cpu_desc
);
498 /* The operand instance table is used during optimization to determine
499 which insns can be executed in parallel. It is also used to give
500 warnings regarding operand interference in parallel insns. */
501 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc
);
503 /* This is a callback from cgen to gas to parse operands. */
504 cgen_set_parse_operand_fn (gas_cgen_cpu_desc
, gas_cgen_parse_operand
);
506 #if 0 /* not supported yet */
507 /* If a runtime cpu description file was provided, parse it. */
508 if (m32r_cpu_desc
!= NULL
)
512 errmsg
= cgen_read_cpu_file (gas_cgen_cpu_desc
, m32r_cpu_desc
);
514 as_bad ("%s: %s", m32r_cpu_desc
, errmsg
);
518 /* Save the current subseg so we can restore it [it's the default one and
519 we don't want the initial section to be .sbss]. */
523 /* The sbss section is for local .scomm symbols. */
524 sbss_section
= subseg_new (".sbss", 0);
526 /* This is copied from perform_an_assembly_pass. */
527 applicable
= bfd_applicable_section_flags (stdoutput
);
528 bfd_set_section_flags (stdoutput
, sbss_section
, applicable
& SEC_ALLOC
);
530 #if 0 /* What does this do? [see perform_an_assembly_pass] */
531 seg_info (bss_section
)->bss
= 1;
534 subseg_set (seg
, subseg
);
536 /* We must construct a fake section similar to bfd_com_section
537 but with the name .scommon. */
538 scom_section
= bfd_com_section
;
539 scom_section
.name
= ".scommon";
540 scom_section
.output_section
= & scom_section
;
541 scom_section
.symbol
= & scom_symbol
;
542 scom_section
.symbol_ptr_ptr
= & scom_section
.symbol
;
543 scom_symbol
= * bfd_com_section
.symbol
;
544 scom_symbol
.name
= ".scommon";
545 scom_symbol
.section
= & scom_section
;
547 allow_m32rx (enable_m32rx
);
550 #define OPERAND_IS_COND_BIT(operand, indices, index) \
551 ((operand)->hw_type == HW_H_COND \
552 || ((operand)->hw_type == HW_H_PSW) \
553 || ((operand)->hw_type == HW_H_CR \
554 && (indices [index] == 0 || indices [index] == 1)))
556 /* Returns true if an output of instruction 'a' is referenced by an operand
557 of instruction 'b'. If 'check_outputs' is true then b's outputs are
558 checked, otherwise its inputs are examined. */
561 first_writes_to_seconds_operands (a
, b
, check_outputs
)
564 const int check_outputs
;
566 const CGEN_OPINST
* a_operands
= CGEN_INSN_OPERANDS (a
->insn
);
567 const CGEN_OPINST
* b_ops
= CGEN_INSN_OPERANDS (b
->insn
);
570 /* If at least one of the instructions takes no operands, then there is
571 nothing to check. There really are instructions without operands,
573 if (a_operands
== NULL
|| b_ops
== NULL
)
576 /* Scan the operand list of 'a' looking for an output operand. */
578 a_operands
->type
!= CGEN_OPINST_END
;
579 a_index
++, a_operands
++)
581 if (a_operands
->type
== CGEN_OPINST_OUTPUT
)
584 const CGEN_OPINST
* b_operands
= b_ops
;
587 The Condition bit 'C' is a shadow of the CBR register (control
588 register 1) and also a shadow of bit 31 of the program status
589 word (control register 0). For now this is handled here, rather
592 if (OPERAND_IS_COND_BIT (a_operands
, a
->indices
, a_index
))
594 /* Scan operand list of 'b' looking for another reference to the
595 condition bit, which goes in the right direction. */
597 b_operands
->type
!= CGEN_OPINST_END
;
598 b_index
++, b_operands
++)
600 if ((b_operands
->type
603 : CGEN_OPINST_INPUT
))
604 && OPERAND_IS_COND_BIT (b_operands
, b
->indices
, b_index
))
610 /* Scan operand list of 'b' looking for an operand that
611 references the same hardware element, and which goes in the
614 b_operands
->type
!= CGEN_OPINST_END
;
615 b_index
++, b_operands
++)
617 if ((b_operands
->type
620 : CGEN_OPINST_INPUT
))
621 && (b_operands
->hw_type
== a_operands
->hw_type
)
622 && (a
->indices
[a_index
] == b
->indices
[b_index
]))
632 /* Returns true if the insn can (potentially) alter the program counter. */
638 #if 0 /* Once PC operands are working.... */
639 const CGEN_OPINST
* a_operands
== CGEN_INSN_OPERANDS (gas_cgen_cpu_desc
,
642 if (a_operands
== NULL
)
645 while (a_operands
->type
!= CGEN_OPINST_END
)
647 if (a_operands
->operand
!= NULL
648 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc
, a_operands
->operand
) == M32R_OPERAND_PC
)
654 if (CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_UNCOND_CTI
)
655 || CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_COND_CTI
))
661 /* Returns NULL if the two 16 bit insns can be executed in parallel,
662 otherwise it returns a pointer to an error message explaining why not. */
665 can_make_parallel (a
, b
)
672 /* Make sure the instructions are the right length. */
673 if ( CGEN_FIELDS_BITSIZE (& a
->fields
) != 16
674 || CGEN_FIELDS_BITSIZE (& b
->fields
) != 16)
677 if (first_writes_to_seconds_operands (a
, b
, true))
678 return _("Instructions write to the same destination register.");
680 a_pipe
= CGEN_INSN_ATTR_VALUE (a
->insn
, CGEN_INSN_PIPE
);
681 b_pipe
= CGEN_INSN_ATTR_VALUE (b
->insn
, CGEN_INSN_PIPE
);
683 /* Make sure that the instructions use the correct execution pipelines. */
684 if ( a_pipe
== PIPE_NONE
685 || b_pipe
== PIPE_NONE
)
686 return _("Instructions do not use parallel execution pipelines.");
688 /* Leave this test for last, since it is the only test that can
689 go away if the instructions are swapped, and we want to make
690 sure that any other errors are detected before this happens. */
691 if ( a_pipe
== PIPE_S
693 return _("Instructions share the same execution pipeline");
698 /* Force the top bit of the second 16-bit insn to be set. */
701 make_parallel (buffer
)
702 CGEN_INSN_BYTES_PTR buffer
;
707 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
712 /* Same as make_parallel except buffer contains the bytes in target order. */
715 target_make_parallel (buffer
)
718 buffer
[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc
) == CGEN_ENDIAN_BIG
? 0 : 1]
722 /* Assemble two instructions with an explicit parallel operation (||) or
723 sequential operation (->). */
726 assemble_two_insns (str
, str2
, parallel_p
)
735 char save_str2
= *str2
;
737 * str2
= 0; /* Seperate the two instructions. */
739 /* Make sure the two insns begin on a 32 bit boundary.
740 This is also done for the serial case (foo -> bar), relaxing doesn't
741 affect insns written like this.
742 Note that we must always do this as we can't assume anything about
743 whether we're currently on a 32 bit boundary or not. Relaxing may
747 first
.debug_sym_link
= debug_sym_link
;
748 debug_sym_link
= (sym_linkS
*)0;
750 /* Parse the first instruction. */
751 if (! (first
.insn
= m32r_cgen_assemble_insn
752 (gas_cgen_cpu_desc
, str
, & first
.fields
, first
.buffer
, & errmsg
)))
759 if (CGEN_FIELDS_BITSIZE (&first
.fields
) != 16)
761 /* xgettext:c-format */
762 as_bad (_("not a 16 bit instruction '%s'"), str
);
765 else if (! enable_special
766 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_SPECIAL
))
768 /* xgettext:c-format */
769 as_bad (_("unknown instruction '%s'"), str
);
772 else if (! enable_m32rx
773 /* FIXME: Need standard macro to perform this test. */
774 && CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
776 /* xgettext:c-format */
777 as_bad (_("instruction '%s' is for the M32RX only"), str
);
781 /* Check to see if this is an allowable parallel insn. */
782 if (parallel_p
&& CGEN_INSN_ATTR_VALUE (first
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
784 /* xgettext:c-format */
785 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
789 *str2
= save_str2
; /* Restore the original assembly text, just in case it is needed. */
790 str3
= str
; /* Save the original string pointer. */
791 str
= str2
+ 2; /* Advanced past the parsed string. */
792 str2
= str3
; /* Remember the entire string in case it is needed for error messages. */
794 /* Convert the opcode to lower case. */
798 while (isspace (*s2
++))
803 while (isalnum (*s2
))
805 if (isupper ((unsigned char) *s2
))
811 /* Preserve any fixups that have been generated and reset the list to empty. */
812 gas_cgen_save_fixups ();
814 /* Get the indices of the operands of the instruction. */
815 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
816 doesn't seem right. Perhaps allow passing fields like we do insn. */
817 /* FIXME: ALIAS insns do not have operands, so we use this function
818 to find the equivalent insn and overwrite the value stored in our
819 structure. We still need the original insn, however, since this
820 may have certain attributes that are not present in the unaliased
821 version (eg relaxability). When aliases behave differently this
822 may have to change. */
823 first
.orig_insn
= first
.insn
;
825 CGEN_FIELDS tmp_fields
;
826 first
.insn
= cgen_lookup_get_insn_operands
827 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (first
.buffer
), NULL
, 16,
828 first
.indices
, &tmp_fields
);
831 if (first
.insn
== NULL
)
832 as_fatal (_("internal error: lookup/get operands failed"));
834 second
.debug_sym_link
= NULL
;
836 /* Parse the second instruction. */
837 if (! (second
.insn
= m32r_cgen_assemble_insn
838 (gas_cgen_cpu_desc
, str
, & second
.fields
, second
.buffer
, & errmsg
)))
845 if (CGEN_FIELDS_BITSIZE (&second
.fields
) != 16)
847 /* xgettext:c-format */
848 as_bad (_("not a 16 bit instruction '%s'"), str
);
851 else if (! enable_special
852 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_SPECIAL
))
854 /* xgettext:c-format */
855 as_bad (_("unknown instruction '%s'"), str
);
858 else if (! enable_m32rx
859 && CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
861 /* xgettext:c-format */
862 as_bad (_("instruction '%s' is for the M32RX only"), str
);
866 /* Check to see if this is an allowable parallel insn. */
867 if (parallel_p
&& CGEN_INSN_ATTR_VALUE (second
.insn
, CGEN_INSN_PIPE
) == PIPE_NONE
)
869 /* xgettext:c-format */
870 as_bad (_("instruction '%s' cannot be executed in parallel."), str
);
874 if (parallel_p
&& ! enable_m32rx
)
876 if (CGEN_INSN_NUM (first
.insn
) != M32R_INSN_NOP
877 && CGEN_INSN_NUM (second
.insn
) != M32R_INSN_NOP
)
879 /* xgettext:c-format */
880 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2
);
885 /* Get the indices of the operands of the instruction. */
886 second
.orig_insn
= second
.insn
;
888 CGEN_FIELDS tmp_fields
;
889 second
.insn
= cgen_lookup_get_insn_operands
890 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (second
.buffer
), NULL
, 16,
891 second
.indices
, &tmp_fields
);
894 if (second
.insn
== NULL
)
895 as_fatal (_("internal error: lookup/get operands failed"));
897 /* We assume that if the first instruction writes to a register that is
898 read by the second instruction it is because the programmer intended
899 this to happen, (after all they have explicitly requested that these
900 two instructions be executed in parallel). Although if the global
901 variable warn_explicit_parallel_conflicts is true then we do generate
902 a warning message. Similarly we assume that parallel branch and jump
903 instructions are deliberate and should not produce errors. */
905 if (parallel_p
&& warn_explicit_parallel_conflicts
)
907 if (first_writes_to_seconds_operands (& first
, & second
, false))
908 /* xgettext:c-format */
909 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2
);
911 if (first_writes_to_seconds_operands (& second
, & first
, false))
912 /* xgettext:c-format */
913 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2
);
917 || (errmsg
= (char *) can_make_parallel (& first
, & second
)) == NULL
)
919 /* Get the fixups for the first instruction. */
920 gas_cgen_swap_fixups ();
923 expand_debug_syms (first
.debug_sym_link
, 1);
924 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
925 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
927 /* Force the top bit of the second insn to be set. */
929 make_parallel (second
.buffer
);
931 /* Get its fixups. */
932 gas_cgen_restore_fixups ();
935 expand_debug_syms (second
.debug_sym_link
, 1);
936 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
937 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
939 /* Try swapping the instructions to see if they work that way. */
940 else if (can_make_parallel (& second
, & first
) == NULL
)
942 /* Write out the second instruction first. */
943 expand_debug_syms (second
.debug_sym_link
, 1);
944 gas_cgen_finish_insn (second
.orig_insn
, second
.buffer
,
945 CGEN_FIELDS_BITSIZE (& second
.fields
), 0, NULL
);
947 /* Force the top bit of the first instruction to be set. */
948 make_parallel (first
.buffer
);
950 /* Get the fixups for the first instruction. */
951 gas_cgen_restore_fixups ();
953 /* Write out the first instruction. */
954 expand_debug_syms (first
.debug_sym_link
, 1);
955 gas_cgen_finish_insn (first
.orig_insn
, first
.buffer
,
956 CGEN_FIELDS_BITSIZE (& first
.fields
), 0, NULL
);
960 as_bad ("'%s': %s", str2
, errmsg
);
964 /* Set these so m32r_fill_insn can use them. */
966 prev_subseg
= now_subseg
;
977 /* Initialize GAS's cgen interface for a new instruction. */
978 gas_cgen_init_parse ();
980 /* Look for a parallel instruction seperator. */
981 if ((str2
= strstr (str
, "||")) != NULL
)
983 assemble_two_insns (str
, str2
, 1);
987 /* Also look for a sequential instruction seperator. */
988 if ((str2
= strstr (str
, "->")) != NULL
)
990 assemble_two_insns (str
, str2
, 0);
994 insn
.debug_sym_link
= debug_sym_link
;
995 debug_sym_link
= (sym_linkS
*)0;
997 insn
.insn
= m32r_cgen_assemble_insn
998 (gas_cgen_cpu_desc
, str
, & insn
.fields
, insn
.buffer
, & errmsg
);
1006 if (! enable_special
1007 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_SPECIAL
))
1009 /* xgettext:c-format */
1010 as_bad (_("unknown instruction '%s'"), str
);
1013 else if (! enable_m32rx
1014 && CGEN_INSN_ATTR_VALUE (insn
.insn
, CGEN_INSN_MACH
) == (1 << MACH_M32RX
))
1016 /* xgettext:c-format */
1017 as_bad (_("instruction '%s' is for the M32RX only"), str
);
1021 if (CGEN_INSN_BITSIZE (insn
.insn
) == 32)
1023 /* 32 bit insns must live on 32 bit boundaries. */
1024 if (prev_insn
.insn
|| seen_relaxable_p
)
1026 /* ??? If calling fill_insn too many times turns us into a memory
1027 pig, can we call a fn to assemble a nop instead of
1028 !seen_relaxable_p? */
1032 expand_debug_syms (insn
.debug_sym_link
, 2);
1034 /* Doesn't really matter what we pass for RELAX_P here. */
1035 gas_cgen_finish_insn (insn
.insn
, insn
.buffer
,
1036 CGEN_FIELDS_BITSIZE (& insn
.fields
), 1, NULL
);
1040 int on_32bit_boundary_p
;
1043 if (CGEN_INSN_BITSIZE (insn
.insn
) != 16)
1046 insn
.orig_insn
= insn
.insn
;
1048 /* If the previous insn was relaxable, then it may be expanded
1049 to fill the current 16 bit slot. Emit a NOP here to occupy
1050 this slot, so that we can start at optimizing at a 32 bit
1052 if (prev_insn
.insn
&& seen_relaxable_p
&& optimize
)
1057 /* Get the indices of the operands of the instruction.
1058 FIXME: See assemble_parallel for notes on orig_insn. */
1060 CGEN_FIELDS tmp_fields
;
1061 insn
.insn
= cgen_lookup_get_insn_operands
1062 (gas_cgen_cpu_desc
, NULL
, INSN_VALUE (insn
.buffer
), NULL
,
1063 16, insn
.indices
, &tmp_fields
);
1066 if (insn
.insn
== NULL
)
1067 as_fatal (_("internal error: lookup/get operands failed"));
1070 /* Compute whether we're on a 32 bit boundary or not.
1071 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1072 on_32bit_boundary_p
= prev_insn
.insn
== NULL
;
1074 /* Look to see if this instruction can be combined with the
1075 previous instruction to make one, parallel, 32 bit instruction.
1076 If the previous instruction (potentially) changed the flow of
1077 program control, then it cannot be combined with the current
1078 instruction. If the current instruction is relaxable, then it
1079 might be replaced with a longer version, so we cannot combine it.
1080 Also if the output of the previous instruction is used as an
1081 input to the current instruction then it cannot be combined.
1082 Otherwise call can_make_parallel() with both orderings of the
1083 instructions to see if they can be combined. */
1084 if ( ! on_32bit_boundary_p
1087 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) == 0
1088 && ! writes_to_pc (& prev_insn
)
1089 && ! first_writes_to_seconds_operands (& prev_insn
, &insn
, false)
1092 if (can_make_parallel (& prev_insn
, & insn
) == NULL
)
1093 make_parallel (insn
.buffer
);
1094 else if (can_make_parallel (& insn
, & prev_insn
) == NULL
)
1098 expand_debug_syms (insn
.debug_sym_link
, 1);
1104 /* Ensure each pair of 16 bit insns is in the same frag. */
1107 gas_cgen_finish_insn (insn
.orig_insn
, insn
.buffer
,
1108 CGEN_FIELDS_BITSIZE (& insn
.fields
),
1109 1 /*relax_p*/, &fi
);
1110 insn
.addr
= fi
.addr
;
1111 insn
.frag
= fi
.frag
;
1112 insn
.num_fixups
= fi
.num_fixups
;
1113 for (i
= 0; i
< fi
.num_fixups
; ++i
)
1114 insn
.fixups
[i
] = fi
.fixups
[i
];
1121 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
1123 /* Swap the two insns */
1124 SWAP_BYTES (prev_insn
.addr
[0], insn
.addr
[0]);
1125 SWAP_BYTES (prev_insn
.addr
[1], insn
.addr
[1]);
1127 target_make_parallel (insn
.addr
);
1129 /* Swap any relaxable frags recorded for the two insns. */
1130 /* FIXME: Clarify. relaxation precludes parallel insns */
1131 if (prev_insn
.frag
->fr_opcode
== prev_insn
.addr
)
1132 prev_insn
.frag
->fr_opcode
= insn
.addr
;
1133 else if (insn
.frag
->fr_opcode
== insn
.addr
)
1134 insn
.frag
->fr_opcode
= prev_insn
.addr
;
1136 /* Update the addresses in any fixups.
1137 Note that we don't have to handle the case where each insn is in
1138 a different frag as we ensure they're in the same frag above. */
1139 for (i
= 0; i
< prev_insn
.num_fixups
; ++i
)
1140 prev_insn
.fixups
[i
]->fx_where
+= 2;
1141 for (i
= 0; i
< insn
.num_fixups
; ++i
)
1142 insn
.fixups
[i
]->fx_where
-= 2;
1145 /* Keep track of whether we've seen a pair of 16 bit insns.
1146 prev_insn.insn is NULL when we're on a 32 bit boundary. */
1147 if (on_32bit_boundary_p
)
1150 prev_insn
.insn
= NULL
;
1152 /* If the insn needs the following one to be on a 32 bit boundary
1153 (e.g. subroutine calls), fill this insn's slot. */
1154 if (on_32bit_boundary_p
1155 && CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_FILL_SLOT
) != 0)
1158 /* If this is a relaxable insn (can be replaced with a larger version)
1159 mark the fact so that we can emit an alignment directive for a
1160 following 32 bit insn if we see one. */
1161 if (CGEN_INSN_ATTR_VALUE (insn
.orig_insn
, CGEN_INSN_RELAXABLE
) != 0)
1162 seen_relaxable_p
= 1;
1165 /* Set these so m32r_fill_insn can use them. */
1167 prev_subseg
= now_subseg
;
1170 /* The syntax in the manual says constants begin with '#'.
1171 We just ignore it. */
1174 md_operand (expressionP
)
1175 expressionS
* expressionP
;
1177 if (* input_line_pointer
== '#')
1179 input_line_pointer
++;
1180 expression (expressionP
);
1185 md_section_align (segment
, size
)
1189 int align
= bfd_get_section_alignment (stdoutput
, segment
);
1190 return ((size
+ (1 << align
) - 1) & (-1 << align
));
1194 md_undefined_symbol (name
)
1200 /* .scomm pseudo-op handler.
1202 This is a new pseudo-op to handle putting objects in .scommon.
1203 By doing this the linker won't need to do any work and more importantly
1204 it removes the implicit -G arg necessary to correctly link the object file.
1211 register char * name
;
1215 register symbolS
* symbolP
;
1219 name
= input_line_pointer
;
1220 c
= get_symbol_end ();
1222 /* just after name is now '\0' */
1223 p
= input_line_pointer
;
1226 if (* input_line_pointer
!= ',')
1228 as_bad (_("Expected comma after symbol-name: rest of line ignored."));
1229 ignore_rest_of_line ();
1233 input_line_pointer
++; /* skip ',' */
1234 if ((size
= get_absolute_expression ()) < 0)
1236 /* xgettext:c-format */
1237 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size
);
1238 ignore_rest_of_line ();
1242 /* The third argument to .scomm is the alignment. */
1243 if (* input_line_pointer
!= ',')
1247 ++ input_line_pointer
;
1248 align
= get_absolute_expression ();
1251 as_warn (_("ignoring bad alignment"));
1255 /* Convert to a power of 2 alignment. */
1258 for (align2
= 0; (align
& 1) == 0; align
>>= 1, ++ align2
)
1262 as_bad (_("Common alignment not a power of 2"));
1263 ignore_rest_of_line ();
1271 symbolP
= symbol_find_or_make (name
);
1274 if (S_IS_DEFINED (symbolP
))
1276 /* xgettext:c-format */
1277 as_bad (_("Ignoring attempt to re-define symbol `%s'."),
1278 S_GET_NAME (symbolP
));
1279 ignore_rest_of_line ();
1283 if (S_GET_VALUE (symbolP
) && S_GET_VALUE (symbolP
) != (valueT
) size
)
1285 /* xgettext:c-format */
1286 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."),
1287 S_GET_NAME (symbolP
),
1288 (long) S_GET_VALUE (symbolP
),
1291 ignore_rest_of_line ();
1295 if (symbol_get_obj (symbolP
)->local
)
1297 segT old_sec
= now_seg
;
1298 int old_subsec
= now_subseg
;
1301 record_alignment (sbss_section
, align2
);
1302 subseg_set (sbss_section
, 0);
1305 frag_align (align2
, 0, 0);
1307 if (S_GET_SEGMENT (symbolP
) == sbss_section
)
1308 symbol_get_frag (symbolP
)->fr_symbol
= 0;
1310 symbol_set_frag (symbolP
, frag_now
);
1312 pfrag
= frag_var (rs_org
, 1, 1, (relax_substateT
) 0, symbolP
, size
,
1315 S_SET_SIZE (symbolP
, size
);
1316 S_SET_SEGMENT (symbolP
, sbss_section
);
1317 S_CLEAR_EXTERNAL (symbolP
);
1318 subseg_set (old_sec
, old_subsec
);
1322 S_SET_VALUE (symbolP
, (valueT
) size
);
1323 S_SET_ALIGN (symbolP
, align2
);
1324 S_SET_EXTERNAL (symbolP
);
1325 S_SET_SEGMENT (symbolP
, & scom_section
);
1328 demand_empty_rest_of_line ();
1331 /* Interface to relax_segment. */
1333 /* FIXME: Build table by hand, get it working, then machine generate. */
1335 const relax_typeS md_relax_table
[] =
1338 1) most positive reach of this state,
1339 2) most negative reach of this state,
1340 3) how many bytes this mode will add to the size of the current frag
1341 4) which index into the table to try if we can't fit into this one. */
1343 /* The first entry must be unused because an `rlx_more' value of zero ends
1347 /* The displacement used by GAS is from the end of the 2 byte insn,
1348 so we subtract 2 from the following. */
1349 /* 16 bit insn, 8 bit disp -> 10 bit range.
1350 This doesn't handle a branch in the right slot at the border:
1351 the "& -4" isn't taken into account. It's not important enough to
1352 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
1354 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
1355 /* 32 bit insn, 24 bit disp -> 26 bit range. */
1356 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
1357 /* Same thing, but with leading nop for alignment. */
1358 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
1362 m32r_relax_frag (fragP
, stretch
)
1366 /* Address of branch insn. */
1367 long address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1370 /* Keep 32 bit insns aligned on 32 bit boundaries. */
1371 if (fragP
->fr_subtype
== 2)
1373 if ((address
& 3) != 0)
1375 fragP
->fr_subtype
= 3;
1379 else if (fragP
->fr_subtype
== 3)
1381 if ((address
& 3) == 0)
1383 fragP
->fr_subtype
= 2;
1389 growth
= relax_frag (fragP
, stretch
);
1391 /* Long jump on odd halfword boundary? */
1392 if (fragP
->fr_subtype
== 2 && (address
& 3) != 0)
1394 fragP
->fr_subtype
= 3;
1402 /* Return an initial guess of the length by which a fragment must grow to
1403 hold a branch to reach its destination.
1404 Also updates fr_type/fr_subtype as necessary.
1406 Called just before doing relaxation.
1407 Any symbol that is now undefined will not become defined.
1408 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
1409 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
1410 Although it may not be explicit in the frag, pretend fr_var starts with a
1414 md_estimate_size_before_relax (fragP
, segment
)
1418 int old_fr_fix
= fragP
->fr_fix
;
1420 /* The only thing we have to handle here are symbols outside of the
1421 current segment. They may be undefined or in a different segment in
1422 which case linker scripts may place them anywhere.
1423 However, we can't finish the fragment here and emit the reloc as insn
1424 alignment requirements may move the insn about. */
1426 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
)
1428 /* The symbol is undefined in this segment.
1429 Change the relaxation subtype to the max allowable and leave
1430 all further handling to md_convert_frag. */
1431 fragP
->fr_subtype
= 2;
1433 #if 0 /* Can't use this, but leave in for illustration. */
1434 /* Change 16 bit insn to 32 bit insn. */
1435 fragP
->fr_opcode
[0] |= 0x80;
1437 /* Increase known (fixed) size of fragment. */
1440 /* Create a relocation for it. */
1441 fix_new (fragP
, old_fr_fix
, 4,
1443 fragP
->fr_offset
, 1 /* pcrel */,
1444 /* FIXME: Can't use a real BFD reloc here.
1445 gas_cgen_md_apply_fix3 can't handle it. */
1446 BFD_RELOC_M32R_26_PCREL
);
1448 /* Mark this fragment as finished. */
1452 const CGEN_INSN
* insn
;
1455 /* Update the recorded insn.
1456 Fortunately we don't have to look very far.
1457 FIXME: Change this to record in the instruction the next higher
1458 relaxable insn to use. */
1459 for (i
= 0, insn
= fragP
->fr_cgen
.insn
; i
< 4; i
++, insn
++)
1461 if ((strcmp (CGEN_INSN_MNEMONIC (insn
),
1462 CGEN_INSN_MNEMONIC (fragP
->fr_cgen
.insn
))
1464 && CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_RELAX
))
1470 fragP
->fr_cgen
.insn
= insn
;
1476 return (fragP
->fr_var
+ fragP
->fr_fix
- old_fr_fix
);
1479 /* *fragP has been relaxed to its final size, and now needs to have
1480 the bytes inside it modified to conform to the new size.
1482 Called after relaxation is finished.
1483 fragP->fr_type == rs_machine_dependent.
1484 fragP->fr_subtype is the subtype of what the address relaxed to. */
1487 md_convert_frag (abfd
, sec
, fragP
)
1493 char * displacement
;
1499 opcode
= fragP
->fr_opcode
;
1501 /* Address opcode resides at in file space. */
1502 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
- 2;
1504 switch (fragP
->fr_subtype
)
1508 displacement
= & opcode
[1];
1513 displacement
= & opcode
[1];
1516 opcode
[2] = opcode
[0] | 0x80;
1517 md_number_to_chars (opcode
, PAR_NOP_INSN
, 2);
1518 opcode_address
+= 2;
1520 displacement
= & opcode
[3];
1526 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1528 /* symbol must be resolved by linker */
1529 if (fragP
->fr_offset
& 3)
1530 as_warn (_("Addend to unresolved symbol not on word boundary."));
1531 addend
= fragP
->fr_offset
>> 2;
1535 /* Address we want to reach in file space. */
1536 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
1537 target_address
+= symbol_get_frag (fragP
->fr_symbol
)->fr_address
;
1538 addend
= (target_address
- (opcode_address
& -4)) >> 2;
1541 /* Create a relocation for symbols that must be resolved by the linker.
1542 Otherwise output the completed insn. */
1544 if (S_GET_SEGMENT (fragP
->fr_symbol
) != sec
)
1546 assert (fragP
->fr_subtype
!= 1);
1547 assert (fragP
->fr_cgen
.insn
!= 0);
1548 gas_cgen_record_fixup (fragP
,
1549 /* Offset of branch insn in frag. */
1550 fragP
->fr_fix
+ extension
- 4,
1551 fragP
->fr_cgen
.insn
,
1553 /* FIXME: quick hack */
1555 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1556 fragP
->fr_cgen
.opindex
),
1558 cgen_operand_lookup_by_num (gas_cgen_cpu_desc
,
1559 M32R_OPERAND_DISP24
),
1561 fragP
->fr_cgen
.opinfo
,
1562 fragP
->fr_symbol
, fragP
->fr_offset
);
1565 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
1567 md_number_to_chars (displacement
, (valueT
) addend
,
1568 SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
1570 fragP
->fr_fix
+= extension
;
1573 /* Functions concerning relocs. */
1575 /* The location from which a PC relative jump should be calculated,
1576 given a PC relative reloc. */
1579 md_pcrel_from_section (fixP
, sec
)
1583 if (fixP
->fx_addsy
!= (symbolS
*) NULL
1584 && (! S_IS_DEFINED (fixP
->fx_addsy
)
1585 || S_GET_SEGMENT (fixP
->fx_addsy
) != sec
))
1587 /* The symbol is undefined (or is defined but not in this section).
1588 Let the linker figure it out. */
1592 return (fixP
->fx_frag
->fr_address
+ fixP
->fx_where
) & -4L;
1595 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
1596 Returns BFD_RELOC_NONE if no reloc type can be found.
1597 *FIXP may be modified if desired. */
1599 bfd_reloc_code_real_type
1600 md_cgen_lookup_reloc (insn
, operand
, fixP
)
1601 const CGEN_INSN
* insn
;
1602 const CGEN_OPERAND
* operand
;
1605 switch (operand
->type
)
1607 case M32R_OPERAND_DISP8
: return BFD_RELOC_M32R_10_PCREL
;
1608 case M32R_OPERAND_DISP16
: return BFD_RELOC_M32R_18_PCREL
;
1609 case M32R_OPERAND_DISP24
: return BFD_RELOC_M32R_26_PCREL
;
1610 case M32R_OPERAND_UIMM24
: return BFD_RELOC_M32R_24
;
1611 case M32R_OPERAND_HI16
:
1612 case M32R_OPERAND_SLO16
:
1613 case M32R_OPERAND_ULO16
:
1614 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1615 if (fixP
->fx_cgen
.opinfo
!= 0)
1616 return fixP
->fx_cgen
.opinfo
;
1618 default : /* avoid -Wall warning */
1621 return BFD_RELOC_NONE
;
1624 /* Record a HI16 reloc for later matching with its LO16 cousin. */
1627 m32r_record_hi16 (reloc_type
, fixP
, seg
)
1632 struct m32r_hi_fixup
* hi_fixup
;
1634 assert (reloc_type
== BFD_RELOC_M32R_HI16_SLO
1635 || reloc_type
== BFD_RELOC_M32R_HI16_ULO
);
1637 hi_fixup
= ((struct m32r_hi_fixup
*)
1638 xmalloc (sizeof (struct m32r_hi_fixup
)));
1639 hi_fixup
->fixp
= fixP
;
1640 hi_fixup
->seg
= now_seg
;
1641 hi_fixup
->next
= m32r_hi_fixup_list
;
1643 m32r_hi_fixup_list
= hi_fixup
;
1646 /* Called while parsing an instruction to create a fixup.
1647 We need to check for HI16 relocs and queue them up for later sorting. */
1650 m32r_cgen_record_fixup_exp (frag
, where
, insn
, length
, operand
, opinfo
, exp
)
1653 const CGEN_INSN
* insn
;
1655 const CGEN_OPERAND
* operand
;
1659 fixS
* fixP
= gas_cgen_record_fixup_exp (frag
, where
, insn
, length
,
1660 operand
, opinfo
, exp
);
1662 switch (operand
->type
)
1664 case M32R_OPERAND_HI16
:
1665 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */
1666 if (fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_SLO
1667 || fixP
->fx_cgen
.opinfo
== BFD_RELOC_M32R_HI16_ULO
)
1668 m32r_record_hi16 (fixP
->fx_cgen
.opinfo
, fixP
, now_seg
);
1670 default : /* avoid -Wall warning */
1677 /* Return BFD reloc type from opinfo field in a fixS.
1678 It's tricky using fx_r_type in m32r_frob_file because the values
1679 are BFD_RELOC_UNUSED + operand number. */
1680 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
1682 /* Sort any unmatched HI16 relocs so that they immediately precede
1683 the corresponding LO16 reloc. This is called before md_apply_fix and
1689 struct m32r_hi_fixup
* l
;
1691 for (l
= m32r_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
1693 segment_info_type
* seginfo
;
1696 assert (FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_SLO
1697 || FX_OPINFO_R_TYPE (l
->fixp
) == BFD_RELOC_M32R_HI16_ULO
);
1699 /* Check quickly whether the next fixup happens to be a matching low. */
1700 if (l
->fixp
->fx_next
!= NULL
1701 && FX_OPINFO_R_TYPE (l
->fixp
->fx_next
) == BFD_RELOC_M32R_LO16
1702 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
1703 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
1706 /* Look through the fixups for this segment for a matching `low'.
1707 When we find one, move the high/shigh just in front of it. We do
1708 this in two passes. In the first pass, we try to find a
1709 unique `low'. In the second pass, we permit multiple high's
1710 relocs for a single `low'. */
1711 seginfo
= seg_info (l
->seg
);
1712 for (pass
= 0; pass
< 2; pass
++)
1718 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
1720 /* Check whether this is a `low' fixup which matches l->fixp. */
1721 if (FX_OPINFO_R_TYPE (f
) == BFD_RELOC_M32R_LO16
1722 && f
->fx_addsy
== l
->fixp
->fx_addsy
1723 && f
->fx_offset
== l
->fixp
->fx_offset
1726 || (FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_SLO
1727 && FX_OPINFO_R_TYPE (prev
) != BFD_RELOC_M32R_HI16_ULO
)
1728 || prev
->fx_addsy
!= f
->fx_addsy
1729 || prev
->fx_offset
!= f
->fx_offset
))
1733 /* Move l->fixp before f. */
1734 for (pf
= &seginfo
->fix_root
;
1736 pf
= & (* pf
)->fx_next
)
1737 assert (* pf
!= NULL
);
1739 * pf
= l
->fixp
->fx_next
;
1741 l
->fixp
->fx_next
= f
;
1743 seginfo
->fix_root
= l
->fixp
;
1745 prev
->fx_next
= l
->fixp
;
1757 && warn_unmatched_high
)
1758 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
1759 _("Unmatched high/shigh reloc"));
1764 /* See whether we need to force a relocation into the output file.
1765 This is used to force out switch and PC relative relocations when
1769 m32r_force_relocation (fix
)
1772 if (fix
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1773 || fix
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
1779 return (fix
->fx_pcrel
1783 /* Write a value out to the object file, using the appropriate endianness. */
1786 md_number_to_chars (buf
, val
, n
)
1791 if (target_big_endian
)
1792 number_to_chars_bigendian (buf
, val
, n
);
1794 number_to_chars_littleendian (buf
, val
, n
);
1797 /* Turn a string in input_line_pointer into a floating point constant of type
1798 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
1799 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
1802 /* Equal to MAX_PRECISION in atof-ieee.c */
1803 #define MAX_LITTLENUMS 6
1806 md_atof (type
, litP
, sizeP
)
1813 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1815 char * atof_ieee ();
1833 /* FIXME: Some targets allow other format chars for bigger sizes here. */
1837 return _("Bad call to md_atof()");
1840 t
= atof_ieee (input_line_pointer
, type
, words
);
1842 input_line_pointer
= t
;
1843 * sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1845 if (target_big_endian
)
1847 for (i
= 0; i
< prec
; i
++)
1849 md_number_to_chars (litP
, (valueT
) words
[i
],
1850 sizeof (LITTLENUM_TYPE
));
1851 litP
+= sizeof (LITTLENUM_TYPE
);
1856 for (i
= prec
- 1; i
>= 0; i
--)
1858 md_number_to_chars (litP
, (valueT
) words
[i
],
1859 sizeof (LITTLENUM_TYPE
));
1860 litP
+= sizeof (LITTLENUM_TYPE
);
1868 m32r_elf_section_change_hook ()
1870 /* If we have reached the end of a section and we have just emitted a
1871 16 bit insn, then emit a nop to make sure that the section ends on
1872 a 32 bit boundary. */
1874 if (prev_insn
.insn
|| seen_relaxable_p
)
1875 (void) m32r_fill_insn (0);
1879 m32r_fix_adjustable (fixP
)
1883 if (fixP
->fx_addsy
== NULL
)
1886 /* Prevent all adjustments to global symbols. */
1887 if (S_IS_EXTERN (fixP
->fx_addsy
))
1889 if (S_IS_WEAK (fixP
->fx_addsy
))
1892 /* We need the symbol name for the VTABLE entries */
1893 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
1894 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)