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[binutils-gdb.git] / gas / config / tc-m68hc11.c
1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright (C) 1999, 2000 Free Software Foundation.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include <stdio.h>
23 #include <ctype.h>
24 #include "as.h"
25 #include "subsegs.h"
26 #include "opcode/m68hc11.h"
27 #include "dwarf2dbg.h"
28
29 struct dwarf2_line_info debug_line;
30
31 const char comment_chars[] = ";!";
32 const char line_comment_chars[] = "#*";
33 const char line_separator_chars[] = "";
34
35 const char EXP_CHARS[] = "eE";
36 const char FLT_CHARS[] = "dD";
37
38 #define STATE_CONDITIONAL_BRANCH (1)
39 #define STATE_PC_RELATIVE (2)
40 #define STATE_INDEXED_OFFSET (3)
41 #define STATE_XBCC_BRANCH (4)
42 #define STATE_CONDITIONAL_BRANCH_6812 (5)
43
44 #define STATE_BYTE (0)
45 #define STATE_BITS5 (0)
46 #define STATE_WORD (1)
47 #define STATE_BITS9 (1)
48 #define STATE_LONG (2)
49 #define STATE_BITS16 (2)
50 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
51
52 /* This macro has no side-effects. */
53 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
54
55 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
56
57 /* This table describes how you change sizes for the various types of variable
58 size expressions. This version only supports two kinds. */
59
60 /* The fields are:
61 How far Forward this mode will reach.
62 How far Backward this mode will reach.
63 How many bytes this mode will add to the size of the frag.
64 Which mode to go to if the offset won't fit in this one. */
65
66 relax_typeS md_relax_table[] =
67 {
68 {1, 1, 0, 0}, /* First entries aren't used. */
69 {1, 1, 0, 0}, /* For no good reason except. */
70 {1, 1, 0, 0}, /* that the VAX doesn't either. */
71 {1, 1, 0, 0},
72
73 /* Relax for bcc <L>.
74 These insns are translated into b!cc +3 jmp L. */
75 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD)},
76 {0, 0, 3, 0},
77 {1, 1, 0, 0},
78 {1, 1, 0, 0},
79
80 /* Relax for bsr <L> and bra <L>.
81 These insns are translated into jsr and jmp. */
82 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD)},
83 {0, 0, 1, 0},
84 {1, 1, 0, 0},
85 {1, 1, 0, 0},
86
87 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
88 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9)},
89 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16)},
90 {0, 0, 1, 0},
91 {1, 1, 0, 0},
92
93 /* Relax for dbeq/ibeq/tbeq r,<L>:
94 These insns are translated into db!cc +3 jmp L. */
95 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD)},
96 {0, 0, 3, 0},
97 {1, 1, 0, 0},
98 {1, 1, 0, 0},
99
100 /* Relax for bcc <L> on 68HC12.
101 These insns are translated into lbcc <L>. */
102 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD)},
103 {0, 0, 2, 0},
104 {1, 1, 0, 0},
105 {1, 1, 0, 0},
106
107 };
108
109 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
110 typedef enum register_id
111 {
112 REG_NONE = -1,
113 REG_A = 0,
114 REG_B = 1,
115 REG_CCR = 2,
116 REG_D = 4,
117 REG_X = 5,
118 REG_Y = 6,
119 REG_SP = 7,
120 REG_PC = 8
121 } register_id;
122
123 typedef struct operand
124 {
125 expressionS exp;
126 register_id reg1;
127 register_id reg2;
128 int mode;
129 } operand;
130
131 struct m68hc11_opcode_def
132 {
133 long format;
134 int min_operands;
135 int max_operands;
136 int nb_modes;
137 int used;
138 struct m68hc11_opcode *opcode;
139 };
140
141 static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0;
142 static int m68hc11_nb_opcode_defs = 0;
143
144 typedef struct alias
145 {
146 const char *name;
147 const char *alias;
148 }
149 alias;
150
151 static alias alias_opcodes[] =
152 {
153 {"cpd", "cmpd"},
154 {"cpx", "cmpx"},
155 {"cpy", "cmpy"},
156 {0, 0}
157 };
158
159 /* Local functions. */
160 static register_id reg_name_search PARAMS ((char *));
161 static register_id register_name PARAMS ((void));
162 static int check_range PARAMS ((long, int));
163 static void print_opcode_list PARAMS ((void));
164 static void get_default_target PARAMS ((void));
165 static void print_insn_format PARAMS ((char *));
166 static int get_operand PARAMS ((operand *, int, long));
167 static void fixup8 PARAMS ((expressionS *, int, int));
168 static void fixup16 PARAMS ((expressionS *, int, int));
169 static struct m68hc11_opcode *find_opcode
170 PARAMS ((struct m68hc11_opcode_def *, operand *, int *));
171 static void build_jump_insn
172 PARAMS ((struct m68hc11_opcode *, operand *, int, int));
173 static void build_insn
174 PARAMS ((struct m68hc11_opcode *, operand *, int));
175
176 /* Controls whether relative branches can be turned into long branches.
177 When the relative offset is too large, the insn are changed:
178 bra -> jmp
179 bsr -> jsr
180 bcc -> b!cc +3
181 jmp L
182 dbcc -> db!cc +3
183 jmp L
184
185 Setting the flag forbidds this. */
186 static short flag_fixed_branchs = 0;
187
188 /* Force to use long jumps (absolute) instead of relative branches. */
189 static short flag_force_long_jumps = 0;
190
191 /* Change the direct addressing mode into an absolute addressing mode
192 when the insn does not support direct addressing.
193 For example, "clr *ZD0" is normally not possible and is changed
194 into "clr ZDO". */
195 static short flag_strict_direct_addressing = 1;
196
197 /* When an opcode has invalid operand, print out the syntax of the opcode
198 to stderr. */
199 static short flag_print_insn_syntax = 0;
200
201 /* Dumps the list of instructions with syntax and then exit:
202 1 -> Only dumps the list (sorted by name)
203 2 -> Generate an example (or test) that can be compiled. */
204 static short flag_print_opcodes = 0;
205
206 /* Opcode hash table. */
207 static struct hash_control *m68hc11_hash;
208
209 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
210 by 'get_default_target' by looking at default BFD vector. This is overriden
211 with the -m<cpu> option. */
212 static int current_architecture = 0;
213
214 /* Default cpu determined by 'get_default_target'. */
215 static const char *default_cpu;
216
217 /* Number of opcodes in the sorted table (filtered by current cpu). */
218 static int num_opcodes;
219
220 /* The opcodes sorted by name and filtered by current cpu. */
221 static struct m68hc11_opcode *m68hc11_sorted_opcodes;
222
223 /* These are the machine dependent pseudo-ops. These are included so
224 the assembler can work on the output from the SUN C compiler, which
225 generates these. */
226
227 /* This table describes all the machine specific pseudo-ops the assembler
228 has to support. The fields are:
229 pseudo-op name without dot
230 function to call to execute this pseudo-op
231 Integer arg to pass to the function. */
232 const pseudo_typeS md_pseudo_table[] =
233 {
234 /* The following pseudo-ops are supported for MRI compatibility. */
235 {"fcb", cons, 1},
236 {"fdb", cons, 2},
237 {"fcc", stringer, 1},
238 {"rmb", s_space, 0},
239 {"file", dwarf2_directive_file, 0},
240 {"loc", dwarf2_directive_loc, 0},
241
242 {0, 0, 0}
243 };
244 \f
245 /* Options and initialization. */
246
247 CONST char *md_shortopts = "Sm:";
248
249 struct option md_longopts[] =
250 {
251 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
252 {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
253
254 #define OPTION_SHORT_BRANCHS (OPTION_MD_BASE + 1)
255 {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHS},
256
257 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
258 {"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE},
259
260 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
261 {"print-insn-syntax", no_argument, NULL, OPTION_PRINT_INSN_SYNTAX},
262
263 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
264 {"print-opcodes", no_argument, NULL, OPTION_PRINT_OPCODES},
265
266 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
267 {"generate-example", no_argument, NULL, OPTION_GENERATE_EXAMPLE},
268
269 {NULL, no_argument, NULL, 0}
270 };
271 size_t md_longopts_size = sizeof (md_longopts);
272
273 /* Get the target cpu for the assembler. This is based on the configure
274 options and on the -m68hc11/-m68hc12 option. If no option is specified,
275 we must get the default. */
276 const char *
277 m68hc11_arch_format ()
278 {
279 get_default_target ();
280 if (current_architecture & cpu6811)
281 return "elf32-m68hc11";
282 else
283 return "elf32-m68hc12";
284 }
285
286 enum bfd_architecture
287 m68hc11_arch ()
288 {
289 get_default_target ();
290 if (current_architecture & cpu6811)
291 return bfd_arch_m68hc11;
292 else
293 return bfd_arch_m68hc12;
294 }
295
296 int
297 m68hc11_mach ()
298 {
299 return 0;
300 }
301
302 void
303 md_show_usage (stream)
304 FILE *stream;
305 {
306 get_default_target ();
307 fprintf (stream, _("\
308 Motorola 68HC11/68HC12 options:\n\
309 -m68hc11 | -m68hc12 specify the processor [default %s]\n\
310 --force-long-branchs always turn relative branchs into absolute ones\n\
311 -S,--short-branchs do not turn relative branchs into absolute ones\n\
312 when the offset is out of range\n\
313 --strict-direct-mode do not turn the direct mode into extended mode\n\
314 when the instruction does not support direct mode\n\
315 --print-insn-syntax print the syntax of instruction in case of error\n\
316 --print-opcodes print the list of instructions with syntax\n\
317 --generate-example generate an example of each instruction\n\
318 (used for testing)\n"), default_cpu);
319
320 }
321
322 /* Try to identify the default target based on the BFD library. */
323 static void
324 get_default_target ()
325 {
326 const bfd_target *target;
327 bfd abfd;
328
329 if (current_architecture != 0)
330 return;
331
332 default_cpu = "unknown";
333 target = bfd_find_target (0, &abfd);
334 if (target && target->name)
335 {
336 if (strcmp (target->name, "elf32-m68hc12") == 0)
337 {
338 current_architecture = cpu6812;
339 default_cpu = "m68hc12";
340 }
341 else if (strcmp (target->name, "elf32-m68hc11") == 0)
342 {
343 current_architecture = cpu6811;
344 default_cpu = "m68hc11";
345 }
346 else
347 {
348 as_bad (_("Default target `%s' is not supported."), target->name);
349 }
350 }
351 }
352
353 void
354 m68hc11_print_statistics (file)
355 FILE *file;
356 {
357 int i;
358 struct m68hc11_opcode_def *opc;
359
360 hash_print_statistics (file, "opcode table", m68hc11_hash);
361
362 opc = m68hc11_opcode_defs;
363 if (opc == 0 || m68hc11_nb_opcode_defs == 0)
364 return;
365
366 /* Dump the opcode statistics table. */
367 fprintf (file, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
368 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++)
369 {
370 fprintf (file, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
371 opc->opcode->name,
372 opc->nb_modes,
373 opc->min_operands, opc->max_operands, opc->format, opc->used);
374 }
375 }
376
377 int
378 md_parse_option (c, arg)
379 int c;
380 char *arg;
381 {
382 get_default_target ();
383 switch (c)
384 {
385 /* -S means keep external to 2 bits offset rather than 16 bits one. */
386 case OPTION_SHORT_BRANCHS:
387 case 'S':
388 flag_fixed_branchs = 1;
389 break;
390
391 case OPTION_FORCE_LONG_BRANCH:
392 flag_force_long_jumps = 1;
393 break;
394
395 case OPTION_PRINT_INSN_SYNTAX:
396 flag_print_insn_syntax = 1;
397 break;
398
399 case OPTION_PRINT_OPCODES:
400 flag_print_opcodes = 1;
401 break;
402
403 case OPTION_STRICT_DIRECT_MODE:
404 flag_strict_direct_addressing = 0;
405 break;
406
407 case OPTION_GENERATE_EXAMPLE:
408 flag_print_opcodes = 2;
409 break;
410
411 case 'm':
412 if (strcasecmp (arg, "68hc11") == 0)
413 current_architecture = cpu6811;
414 else if (strcasecmp (arg, "68hc12") == 0)
415 current_architecture = cpu6812;
416 else
417 as_bad (_("Option `%s' is not recognized."), arg);
418 break;
419
420 default:
421 return 0;
422 }
423
424 return 1;
425 }
426 \f
427 symbolS *
428 md_undefined_symbol (name)
429 char *name ATTRIBUTE_UNUSED;
430 {
431 return 0;
432 }
433
434 /* Equal to MAX_PRECISION in atof-ieee.c. */
435 #define MAX_LITTLENUMS 6
436
437 /* Turn a string in input_line_pointer into a floating point constant
438 of type TYPE, and store the appropriate bytes in *LITP. The number
439 of LITTLENUMS emitted is stored in *SIZEP. An error message is
440 returned, or NULL on OK. */
441 char *
442 md_atof (type, litP, sizeP)
443 char type;
444 char *litP;
445 int *sizeP;
446 {
447 int prec;
448 LITTLENUM_TYPE words[MAX_LITTLENUMS];
449 LITTLENUM_TYPE *wordP;
450 char *t;
451
452 switch (type)
453 {
454 case 'f':
455 case 'F':
456 case 's':
457 case 'S':
458 prec = 2;
459 break;
460
461 case 'd':
462 case 'D':
463 case 'r':
464 case 'R':
465 prec = 4;
466 break;
467
468 case 'x':
469 case 'X':
470 prec = 6;
471 break;
472
473 case 'p':
474 case 'P':
475 prec = 6;
476 break;
477
478 default:
479 *sizeP = 0;
480 return _("Bad call to MD_ATOF()");
481 }
482 t = atof_ieee (input_line_pointer, type, words);
483 if (t)
484 input_line_pointer = t;
485
486 *sizeP = prec * sizeof (LITTLENUM_TYPE);
487 for (wordP = words; prec--;)
488 {
489 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
490 litP += sizeof (LITTLENUM_TYPE);
491 }
492 return 0;
493 }
494
495 valueT
496 md_section_align (seg, addr)
497 asection *seg;
498 valueT addr;
499 {
500 int align = bfd_get_section_alignment (stdoutput, seg);
501 return ((addr + (1 << align) - 1) & (-1 << align));
502 }
503
504 static int
505 cmp_opcode (op1, op2)
506 struct m68hc11_opcode *op1;
507 struct m68hc11_opcode *op2;
508 {
509 return strcmp (op1->name, op2->name);
510 }
511
512 /* Initialize the assembler. Create the opcode hash table
513 (sorted on the names) with the M6811 opcode table
514 (from opcode library). */
515 void
516 md_begin ()
517 {
518 char *prev_name = "";
519 struct m68hc11_opcode *opcodes;
520 struct m68hc11_opcode_def *opc = 0;
521 int i, j;
522
523 get_default_target ();
524
525 m68hc11_hash = hash_new ();
526
527 /* Get a writable copy of the opcode table and sort it on the names. */
528 opcodes = (struct m68hc11_opcode *) xmalloc (m68hc11_num_opcodes *
529 sizeof (struct
530 m68hc11_opcode));
531 m68hc11_sorted_opcodes = opcodes;
532 num_opcodes = 0;
533 for (i = 0; i < m68hc11_num_opcodes; i++)
534 {
535 if (m68hc11_opcodes[i].arch & current_architecture)
536 {
537 opcodes[num_opcodes] = m68hc11_opcodes[i];
538 if (opcodes[num_opcodes].name[0] == 'b'
539 && opcodes[num_opcodes].format & M6811_OP_JUMP_REL
540 && !(opcodes[num_opcodes].format & M6811_OP_BITMASK))
541 {
542 num_opcodes++;
543 opcodes[num_opcodes] = m68hc11_opcodes[i];
544 }
545 num_opcodes++;
546 for (j = 0; alias_opcodes[j].name != 0; j++)
547 if (strcmp (m68hc11_opcodes[i].name, alias_opcodes[j].name) == 0)
548 {
549 opcodes[num_opcodes] = m68hc11_opcodes[i];
550 opcodes[num_opcodes].name = alias_opcodes[j].alias;
551 num_opcodes++;
552 break;
553 }
554 }
555 }
556 qsort (opcodes, num_opcodes, sizeof (struct m68hc11_opcode), cmp_opcode);
557
558 opc = (struct m68hc11_opcode_def *)
559 xmalloc (num_opcodes * sizeof (struct m68hc11_opcode_def));
560 m68hc11_opcode_defs = opc--;
561
562 /* Insert unique names into hash table. The M6811 instruction set
563 has several identical opcode names that have different opcodes based
564 on the operands. This hash table then provides a quick index to
565 the first opcode with a particular name in the opcode table. */
566 for (i = 0; i < num_opcodes; i++, opcodes++)
567 {
568 int expect;
569
570 if (strcmp (prev_name, opcodes->name))
571 {
572 prev_name = (char *) opcodes->name;
573
574 opc++;
575 opc->format = 0;
576 opc->min_operands = 100;
577 opc->max_operands = 0;
578 opc->nb_modes = 0;
579 opc->opcode = opcodes;
580 opc->used = 0;
581 hash_insert (m68hc11_hash, opcodes->name, (char *) opc);
582 }
583 opc->nb_modes++;
584 opc->format |= opcodes->format;
585
586 /* See how many operands this opcode needs. */
587 expect = 0;
588 if (opcodes->format & M6811_OP_MASK)
589 expect++;
590 if (opcodes->format & M6811_OP_BITMASK)
591 expect++;
592 if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
593 expect++;
594 if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
595 expect++;
596
597 if (expect < opc->min_operands)
598 opc->min_operands = expect;
599 if (expect > opc->max_operands)
600 opc->max_operands = expect;
601 }
602 opc++;
603 m68hc11_nb_opcode_defs = opc - m68hc11_opcode_defs;
604
605 if (flag_print_opcodes)
606 {
607 print_opcode_list ();
608 exit (EXIT_SUCCESS);
609 }
610 }
611
612 void
613 m68hc11_init_after_args ()
614 {
615 }
616 \f
617 /* Builtin help. */
618
619 /* Return a string that represents the operand format for the instruction.
620 When example is true, this generates an example of operand. This is used
621 to give an example and also to generate a test. */
622 static char *
623 print_opcode_format (opcode, example)
624 struct m68hc11_opcode *opcode;
625 int example;
626 {
627 static char buf[128];
628 int format = opcode->format;
629 char *p;
630
631 p = buf;
632 buf[0] = 0;
633 if (format & M6811_OP_IMM8)
634 {
635 if (example)
636 sprintf (p, "#%d", rand () & 0x0FF);
637 else
638 strcpy (p, _("#<imm8>"));
639 p = &p[strlen (p)];
640 }
641
642 if (format & M6811_OP_IMM16)
643 {
644 if (example)
645 sprintf (p, "#%d", rand () & 0x0FFFF);
646 else
647 strcpy (p, _("#<imm16>"));
648 p = &p[strlen (p)];
649 }
650
651 if (format & M6811_OP_IX)
652 {
653 if (example)
654 sprintf (p, "%d,X", rand () & 0x0FF);
655 else
656 strcpy (p, _("<imm8>,X"));
657 p = &p[strlen (p)];
658 }
659
660 if (format & M6811_OP_IY)
661 {
662 if (example)
663 sprintf (p, "%d,X", rand () & 0x0FF);
664 else
665 strcpy (p, _("<imm8>,X"));
666 p = &p[strlen (p)];
667 }
668
669 if (format & M6812_OP_IDX)
670 {
671 if (example)
672 sprintf (p, "%d,X", rand () & 0x0FF);
673 else
674 strcpy (p, "n,r");
675 p = &p[strlen (p)];
676 }
677
678 if (format & M6811_OP_DIRECT)
679 {
680 if (example)
681 sprintf (p, "*Z%d", rand () & 0x0FF);
682 else
683 strcpy (p, _("*<abs8>"));
684 p = &p[strlen (p)];
685 }
686
687 if (format & M6811_OP_BITMASK)
688 {
689 if (buf[0])
690 *p++ = ' ';
691
692 if (example)
693 sprintf (p, "#$%02x", rand () & 0x0FF);
694 else
695 strcpy (p, _("#<mask>"));
696
697 p = &p[strlen (p)];
698 if (format & M6811_OP_JUMP_REL)
699 *p++ = ' ';
700 }
701
702 if (format & M6811_OP_IND16)
703 {
704 if (example)
705 sprintf (p, _("symbol%d"), rand () & 0x0FF);
706 else
707 strcpy (p, _("<abs>"));
708
709 p = &p[strlen (p)];
710 }
711
712 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
713 {
714 if (example)
715 {
716 if (format & M6811_OP_BITMASK)
717 {
718 sprintf (p, ".+%d", rand () & 0x7F);
719 }
720 else
721 {
722 sprintf (p, "L%d", rand () & 0x0FF);
723 }
724 }
725 else
726 strcpy (p, _("<label>"));
727 }
728
729 return buf;
730 }
731
732 /* Prints the list of instructions with the possible operands. */
733 static void
734 print_opcode_list ()
735 {
736 int i;
737 char *prev_name = "";
738 struct m68hc11_opcode *opcodes;
739 int example = flag_print_opcodes == 2;
740
741 if (example)
742 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
743 default_cpu);
744
745 opcodes = m68hc11_sorted_opcodes;
746
747 /* Walk the list sorted on names (by md_begin). We only report
748 one instruction per line, and we collect the different operand
749 formats. */
750 for (i = 0; i < num_opcodes; i++, opcodes++)
751 {
752 char *fmt = print_opcode_format (opcodes, example);
753
754 if (example)
755 {
756 printf ("L%d:\t", i);
757 printf ("%s %s\n", opcodes->name, fmt);
758 }
759 else
760 {
761 if (strcmp (prev_name, opcodes->name))
762 {
763 if (i > 0)
764 printf ("\n");
765
766 printf ("%-5.5s ", opcodes->name);
767 prev_name = (char *) opcodes->name;
768 }
769 if (fmt[0])
770 printf (" [%s]", fmt);
771 }
772 }
773 printf ("\n");
774 }
775
776 /* Print the instruction format. This operation is called when some
777 instruction is not correct. Instruction format is printed as an
778 error message. */
779 static void
780 print_insn_format (name)
781 char *name;
782 {
783 struct m68hc11_opcode_def *opc;
784 struct m68hc11_opcode *opcode;
785 char buf[128];
786
787 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
788 if (opc == NULL)
789 {
790 as_bad (_("Instruction `%s' is not recognized."), name);
791 return;
792 }
793 opcode = opc->opcode;
794
795 as_bad (_("Instruction formats for `%s':"), name);
796 do
797 {
798 char *fmt;
799
800 fmt = print_opcode_format (opcode, 0, 0);
801 sprintf (buf, "\t%-5.5s %s", opcode->name, fmt);
802
803 as_bad ("%s", buf);
804 opcode++;
805 }
806 while (strcmp (opcode->name, name) == 0);
807 }
808 \f
809 /* Analysis of 68HC11 and 68HC12 operands. */
810
811 /* reg_name_search() finds the register number given its name.
812 Returns the register number or REG_NONE on failure. */
813 static register_id
814 reg_name_search (name)
815 char *name;
816 {
817 if (strcasecmp (name, "x") == 0 || strcasecmp (name, "ix") == 0)
818 return REG_X;
819 if (strcasecmp (name, "y") == 0 || strcasecmp (name, "iy") == 0)
820 return REG_Y;
821 if (strcasecmp (name, "a") == 0)
822 return REG_A;
823 if (strcasecmp (name, "b") == 0)
824 return REG_B;
825 if (strcasecmp (name, "d") == 0)
826 return REG_D;
827 if (strcasecmp (name, "sp") == 0)
828 return REG_SP;
829 if (strcasecmp (name, "pc") == 0)
830 return REG_PC;
831 if (strcasecmp (name, "ccr") == 0)
832 return REG_CCR;
833
834 return REG_NONE;
835 }
836
837 static char *
838 skip_whites (p)
839 char *p;
840 {
841 while (*p == ' ' || *p == '\t')
842 p++;
843
844 return p;
845 }
846
847 /* Check the string at input_line_pointer
848 to see if it is a valid register name. */
849 static register_id
850 register_name ()
851 {
852 register_id reg_number;
853 char c, *p = input_line_pointer;
854
855 if (!is_name_beginner (*p++))
856 return REG_NONE;
857
858 while (is_part_of_name (*p++))
859 continue;
860
861 c = *--p;
862 if (c)
863 *p++ = 0;
864
865 /* Look to see if it's in the register table. */
866 reg_number = reg_name_search (input_line_pointer);
867 if (reg_number != REG_NONE)
868 {
869 if (c)
870 *--p = c;
871
872 input_line_pointer = p;
873 return reg_number;
874 }
875 if (c)
876 *--p = c;
877
878 return reg_number;
879 }
880
881 /* Parse a string of operands and return an array of expressions.
882
883 Operand mode[0] mode[1] exp[0] exp[1]
884 #n M6811_OP_IMM16 - O_*
885 *<exp> M6811_OP_DIRECT - O_*
886 .{+-}<exp> M6811_OP_JUMP_REL - O_*
887 <exp> M6811_OP_IND16 - O_*
888 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
889 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
890 n,+r M6812_PRE_INC " "
891 n,r- M6812_POST_DEC " "
892 n,r+ M6812_POST_INC " "
893 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
894 [D,r] M6811_OP_IDX_2 M6812_OP_REG O_register O_register
895 [n,r] M6811_OP_IDX_1 M6812_OP_REG O_constant O_register */
896 static int
897 get_operand (oper, which, opmode)
898 operand *oper;
899 int which;
900 long opmode;
901 {
902 char *p = input_line_pointer;
903 int mode;
904 register_id reg;
905
906 oper->exp.X_op = O_absent;
907 oper->reg1 = REG_NONE;
908 oper->reg2 = REG_NONE;
909 mode = M6811_OP_NONE;
910
911 p = skip_whites (p);
912
913 if (*p == 0 || *p == '\n' || *p == '\r')
914 {
915 input_line_pointer = p;
916 return 0;
917 }
918
919 if (*p == '*' && (opmode & (M6811_OP_DIRECT | M6811_OP_IND16)))
920 {
921 mode = M6811_OP_DIRECT;
922 p++;
923 }
924 else if (*p == '#')
925 {
926 if (!(opmode & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK)))
927 {
928 as_bad (_("Immediate operand is not allowed for operand %d."),
929 which);
930 return -1;
931 }
932
933 mode = M6811_OP_IMM16;
934 p++;
935 if (strncmp (p, "%hi", 3) == 0)
936 {
937 p += 3;
938 mode |= M6811_OP_HIGH_ADDR;
939 }
940 else if (strncmp (p, "%lo", 3) == 0)
941 {
942 p += 3;
943 mode |= M6811_OP_LOW_ADDR;
944 }
945 }
946 else if (*p == '.' && (p[1] == '+' || p[1] == '-'))
947 {
948 p++;
949 mode = M6811_OP_JUMP_REL;
950 }
951 else if (*p == '[')
952 {
953 if (current_architecture & cpu6811)
954 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
955
956 p++;
957 mode = M6812_OP_IDX_2;
958 p = skip_whites (p);
959 }
960 else if (*p == ',') /* Special handling of ,x and ,y. */
961 {
962 p++;
963 input_line_pointer = p;
964
965 reg = register_name ();
966 if (reg != REG_NONE)
967 {
968 oper->reg1 = reg;
969 oper->exp.X_op = O_constant;
970 oper->exp.X_add_number = 0;
971 oper->mode = M6812_OP_IDX;
972 return 1;
973 }
974 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
975 return -1;
976 }
977 input_line_pointer = p;
978
979 if (mode == M6811_OP_NONE || mode == M6812_OP_IDX_2)
980 reg = register_name ();
981 else
982 reg = REG_NONE;
983
984 if (reg != REG_NONE)
985 {
986 p = skip_whites (input_line_pointer);
987 if (*p == ']' && mode == M6812_OP_IDX_2)
988 {
989 as_bad
990 (_("Missing second register or offset for indexed-indirect mode."));
991 return -1;
992 }
993
994 oper->reg1 = reg;
995 oper->mode = mode | M6812_OP_REG;
996 if (*p != ',')
997 {
998 if (mode == M6812_OP_IDX_2)
999 {
1000 as_bad (_("Missing second register for indexed-indirect mode."));
1001 return -1;
1002 }
1003 return 1;
1004 }
1005
1006 p++;
1007 input_line_pointer = p;
1008 reg = register_name ();
1009 if (reg != REG_NONE)
1010 {
1011 p = skip_whites (input_line_pointer);
1012 if (mode == M6812_OP_IDX_2)
1013 {
1014 if (*p != ']')
1015 {
1016 as_bad (_("Missing `]' to close indexed-indirect mode."));
1017 return -1;
1018 }
1019 p++;
1020 }
1021 input_line_pointer = p;
1022
1023 oper->reg2 = reg;
1024 return 1;
1025 }
1026 return 1;
1027 }
1028
1029 /* In MRI mode, isolate the operand because we can't distinguish
1030 operands from comments. */
1031 if (flag_mri)
1032 {
1033 char c = 0;
1034
1035 p = skip_whites (p);
1036 while (*p && *p != ' ' && *p != '\t')
1037 p++;
1038
1039 if (*p)
1040 {
1041 c = *p;
1042 *p = 0;
1043 }
1044
1045 /* Parse as an expression. */
1046 expression (&oper->exp);
1047
1048 if (c)
1049 {
1050 *p = c;
1051 }
1052 }
1053 else
1054 {
1055 expression (&oper->exp);
1056 }
1057
1058 if (oper->exp.X_op == O_illegal)
1059 {
1060 as_bad (_("Illegal operand."));
1061 return -1;
1062 }
1063 else if (oper->exp.X_op == O_absent)
1064 {
1065 as_bad (_("Missing operand."));
1066 return -1;
1067 }
1068
1069 p = input_line_pointer;
1070
1071 if (mode == M6811_OP_NONE || mode == M6811_OP_DIRECT
1072 || mode == M6812_OP_IDX_2)
1073 {
1074 p = skip_whites (input_line_pointer);
1075
1076 if (*p == ',')
1077 {
1078 p++;
1079
1080 /* 68HC12 pre increment or decrement. */
1081 if (mode == M6811_OP_NONE)
1082 {
1083 if (*p == '-')
1084 {
1085 mode = M6812_PRE_DEC;
1086 p++;
1087 if (current_architecture & cpu6811)
1088 as_bad (_("Pre-decrement mode is not valid for 68HC11"));
1089 }
1090 else if (*p == '+')
1091 {
1092 mode = M6812_PRE_INC;
1093 p++;
1094 if (current_architecture & cpu6811)
1095 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1096 }
1097 p = skip_whites (p);
1098 }
1099 input_line_pointer = p;
1100 reg = register_name ();
1101
1102 /* Backtrack. */
1103 if (which == 0 && opmode & M6812_OP_IDX_P2
1104 && reg != REG_X && reg != REG_Y
1105 && reg != REG_PC && reg != REG_SP)
1106 {
1107 reg = REG_NONE;
1108 input_line_pointer = p;
1109 }
1110
1111 if (reg == REG_NONE && mode != M6811_OP_DIRECT
1112 && !(mode == M6811_OP_NONE && opmode & M6811_OP_IND16))
1113 {
1114 as_bad (_("Wrong register in register indirect mode."));
1115 return -1;
1116 }
1117 if (mode == M6812_OP_IDX_2)
1118 {
1119 p = skip_whites (input_line_pointer);
1120 if (*p++ != ']')
1121 {
1122 as_bad (_("Missing `]' to close register indirect operand."));
1123 return -1;
1124 }
1125 input_line_pointer = p;
1126 }
1127 if (reg != REG_NONE)
1128 {
1129 oper->reg1 = reg;
1130 if (mode == M6811_OP_NONE)
1131 {
1132 p = input_line_pointer;
1133 if (*p == '-')
1134 {
1135 mode = M6812_POST_DEC;
1136 p++;
1137 if (current_architecture & cpu6811)
1138 as_bad
1139 (_("Post-decrement mode is not valid for 68HC11."));
1140 }
1141 else if (*p == '+')
1142 {
1143 mode = M6812_POST_INC;
1144 p++;
1145 if (current_architecture & cpu6811)
1146 as_bad
1147 (_("Post-increment mode is not valid for 68HC11."));
1148 }
1149 else
1150 mode = M6812_OP_IDX;
1151
1152 input_line_pointer = p;
1153 }
1154 else
1155 mode |= M6812_OP_IDX;
1156
1157 oper->mode = mode;
1158 return 1;
1159 }
1160 }
1161
1162 if (mode == M6812_OP_D_IDX_2)
1163 {
1164 as_bad (_("Invalid indexed indirect mode."));
1165 return -1;
1166 }
1167 }
1168
1169 /* If the mode is not known until now, this is either a label
1170 or an indirect address. */
1171 if (mode == M6811_OP_NONE)
1172 mode = M6811_OP_IND16 | M6811_OP_JUMP_REL;
1173
1174 p = input_line_pointer;
1175 while (*p == ' ' || *p == '\t')
1176 p++;
1177 input_line_pointer = p;
1178 oper->mode = mode;
1179
1180 return 1;
1181 }
1182
1183 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1184 | M6812_POST_INC | M6812_POST_DEC)
1185
1186 /* Checks that the number 'num' fits for a given mode. */
1187 static int
1188 check_range (num, mode)
1189 long num;
1190 int mode;
1191 {
1192 /* Auto increment and decrement are ok for [-8..8] without 0. */
1193 if (mode & M6812_AUTO_INC_DEC)
1194 return (num != 0 && num <= 8 && num >= -8);
1195
1196 /* The 68HC12 supports 5, 9 and 16-bits offsets. */
1197 if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX))
1198 mode = M6811_OP_IND16;
1199
1200 if (mode & M6812_OP_JUMP_REL16)
1201 mode = M6811_OP_IND16;
1202
1203 switch (mode)
1204 {
1205 case M6811_OP_IX:
1206 case M6811_OP_IY:
1207 case M6811_OP_DIRECT:
1208 return (num >= 0 && num <= 255) ? 1 : 0;
1209
1210 case M6811_OP_BITMASK:
1211 case M6811_OP_IMM8:
1212 return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00))
1213 ? 1 : 0;
1214
1215 case M6811_OP_JUMP_REL:
1216 return (num >= -128 && num <= 127) ? 1 : 0;
1217
1218 case M6811_OP_IND16:
1219 case M6811_OP_IMM16:
1220 return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000))
1221 ? 1 : 0;
1222
1223 case M6812_OP_IBCC_MARKER:
1224 case M6812_OP_TBCC_MARKER:
1225 case M6812_OP_DBCC_MARKER:
1226 return (num >= -256 && num <= 255) ? 1 : 0;
1227
1228 case M6812_OP_TRAP_ID:
1229 return ((num >= 0x30 && num <= 0x39)
1230 || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0;
1231
1232 default:
1233 return 0;
1234 }
1235 }
1236 \f
1237 /* Gas fixup generation. */
1238
1239 /* Put a 1 byte expression described by 'oper'. If this expression contains
1240 unresolved symbols, generate an 8-bit fixup. */
1241 static void
1242 fixup8 (oper, mode, opmode)
1243 expressionS *oper;
1244 int mode;
1245 int opmode;
1246 {
1247 char *f;
1248
1249 f = frag_more (1);
1250
1251 if (oper->X_op == O_constant)
1252 {
1253 if (mode & M6812_OP_TRAP_ID
1254 && !check_range (oper->X_add_number, M6812_OP_TRAP_ID))
1255 {
1256 static char trap_id_warn_once = 0;
1257
1258 as_bad (_("Trap id `%ld' is out of range."), oper->X_add_number);
1259 if (trap_id_warn_once == 0)
1260 {
1261 trap_id_warn_once = 1;
1262 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1263 }
1264 }
1265
1266 if (!(mode & M6812_OP_TRAP_ID)
1267 && !check_range (oper->X_add_number, mode))
1268 {
1269 as_bad (_("Operand out of 8-bit range: `%ld'."), oper->X_add_number);
1270 }
1271 number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1);
1272 }
1273 else if (oper->X_op != O_register)
1274 {
1275 if (mode & M6812_OP_TRAP_ID)
1276 as_bad (_("The trap id must be a constant."));
1277
1278 if (mode == M6811_OP_JUMP_REL)
1279 {
1280 fixS *fixp;
1281
1282 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
1283 oper, true, BFD_RELOC_8_PCREL);
1284 fixp->fx_pcrel_adjust = 1;
1285 }
1286 else
1287 {
1288 /* Now create an 8-bit fixup. If there was some %hi or %lo
1289 modifier, generate the reloc accordingly. */
1290 fix_new_exp (frag_now, f - frag_now->fr_literal, 1,
1291 oper, false,
1292 ((opmode & M6811_OP_HIGH_ADDR)
1293 ? BFD_RELOC_M68HC11_HI8
1294 : ((opmode & M6811_OP_LOW_ADDR)
1295 ? BFD_RELOC_M68HC11_LO8 : BFD_RELOC_8)));
1296 }
1297 number_to_chars_bigendian (f, 0, 1);
1298 }
1299 else
1300 {
1301 as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op);
1302 }
1303 }
1304
1305 /* Put a 2 bytes expression described by 'oper'. If this expression contains
1306 unresolved symbols, generate a 16-bit fixup. */
1307 static void
1308 fixup16 (oper, mode, opmode)
1309 expressionS *oper;
1310 int mode;
1311 int opmode ATTRIBUTE_UNUSED;
1312 {
1313 char *f;
1314
1315 f = frag_more (2);
1316
1317 if (oper->X_op == O_constant)
1318 {
1319 if (!check_range (oper->X_add_number, mode))
1320 {
1321 as_bad (_("Operand out of 16-bit range: `%ld'."),
1322 oper->X_add_number);
1323 }
1324 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFF, 2);
1325 }
1326 else if (oper->X_op != O_register)
1327 {
1328 fixS *fixp;
1329
1330 /* Now create a 16-bit fixup. */
1331 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1332 oper,
1333 (mode & M6812_OP_JUMP_REL16 ? true : false),
1334 (mode & M6812_OP_JUMP_REL16
1335 ? BFD_RELOC_16_PCREL : BFD_RELOC_16));
1336 number_to_chars_bigendian (f, 0, 2);
1337 if (mode & M6812_OP_JUMP_REL16)
1338 fixp->fx_pcrel_adjust = 2;
1339 }
1340 else
1341 {
1342 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op);
1343 }
1344 }
1345 \f
1346 /* 68HC11 and 68HC12 code generation. */
1347
1348 /* Translate the short branch/bsr instruction into a long branch. */
1349 static unsigned char
1350 convert_branch (code)
1351 unsigned char code;
1352 {
1353 if (IS_OPCODE (code, M6812_BSR))
1354 return M6812_JSR;
1355 else if (IS_OPCODE (code, M6811_BSR))
1356 return M6811_JSR;
1357 else if (IS_OPCODE (code, M6811_BRA))
1358 return (current_architecture & cpu6812) ? M6812_JMP : M6811_JMP;
1359 else
1360 as_fatal (_("Unexpected branch conversion with `%x'"), code);
1361
1362 /* Keep gcc happy. */
1363 return M6811_JSR;
1364 }
1365
1366 /* Start a new insn that contains at least 'size' bytes. Record the
1367 line information of that insn in the dwarf2 debug sections. */
1368 static char *
1369 m68hc11_new_insn (size)
1370 int size;
1371 {
1372 char *f;
1373
1374 f = frag_more (size);
1375
1376 /* Emit line number information in dwarf2 debug sections. */
1377 if (debug_type == DEBUG_DWARF2)
1378 {
1379 bfd_vma addr;
1380
1381 dwarf2_where (&debug_line);
1382 addr = frag_now->fr_address + frag_now_fix () - size;
1383 dwarf2_gen_line_info (addr, &debug_line);
1384 }
1385 return f;
1386 }
1387
1388 /* Builds a jump instruction (bra, bcc, bsr). */
1389 static void
1390 build_jump_insn (opcode, operands, nb_operands, jmp_mode)
1391 struct m68hc11_opcode *opcode;
1392 operand operands[];
1393 int nb_operands;
1394 int jmp_mode;
1395 {
1396 unsigned char code;
1397 int insn_size;
1398 char *f;
1399 unsigned long n;
1400
1401 /* The relative branch convertion is not supported for
1402 brclr and brset. */
1403 assert ((opcode->format & M6811_OP_BITMASK) == 0);
1404 assert (nb_operands == 1);
1405 assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE);
1406
1407 code = opcode->opcode;
1408 insn_size = 1;
1409
1410 n = operands[0].exp.X_add_number;
1411
1412 /* Turn into a long branch:
1413 - when force long branch option (and not for jbcc pseudos),
1414 - when jbcc and the constant is out of -128..127 range,
1415 - when branch optimization is allowed and branch out of range. */
1416 if ((jmp_mode == 0 && flag_force_long_jumps)
1417 || (operands[0].exp.X_op == O_constant
1418 && (!check_range (n, opcode->format) &&
1419 (jmp_mode == 1 || flag_fixed_branchs == 0))))
1420 {
1421 if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
1422 {
1423 code = convert_branch (code);
1424
1425 f = m68hc11_new_insn (1);
1426 number_to_chars_bigendian (f, code, 1);
1427 }
1428 else if (current_architecture & cpu6812)
1429 {
1430 /* 68HC12: translate the bcc into a lbcc. */
1431 f = m68hc11_new_insn (2);
1432 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1433 number_to_chars_bigendian (f + 1, code, 1);
1434 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16,
1435 M6812_OP_JUMP_REL16);
1436 return;
1437 }
1438 else
1439 {
1440 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1441 f = m68hc11_new_insn (3);
1442 code ^= 1;
1443 number_to_chars_bigendian (f, code, 1);
1444 number_to_chars_bigendian (f + 1, 3, 1);
1445 number_to_chars_bigendian (f + 2, M6811_JMP, 1);
1446 }
1447 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16);
1448 return;
1449 }
1450
1451 /* Branch with a constant that must fit in 8-bits. */
1452 if (operands[0].exp.X_op == O_constant)
1453 {
1454 if (!check_range (n, opcode->format))
1455 {
1456 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1457 n);
1458 }
1459 else if (opcode->format & M6812_OP_JUMP_REL16)
1460 {
1461 f = m68hc11_new_insn (4);
1462 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1463 number_to_chars_bigendian (f + 1, code, 1);
1464 number_to_chars_bigendian (f + 2, n & 0x0ffff, 2);
1465 }
1466 else
1467 {
1468 f = m68hc11_new_insn (2);
1469 number_to_chars_bigendian (f, code, 1);
1470 number_to_chars_bigendian (f + 1, n & 0x0FF, 1);
1471 }
1472 }
1473 else if (opcode->format & M6812_OP_JUMP_REL16)
1474 {
1475 f = m68hc11_new_insn (2);
1476 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1);
1477 number_to_chars_bigendian (f + 1, code, 1);
1478 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, M6812_OP_JUMP_REL16);
1479 }
1480 else
1481 {
1482 char *opcode;
1483
1484 /* Branch offset must fit in 8-bits, don't do some relax. */
1485 if (jmp_mode == 0 && flag_fixed_branchs)
1486 {
1487 opcode = m68hc11_new_insn (1);
1488 number_to_chars_bigendian (opcode, code, 1);
1489 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
1490 }
1491
1492 /* bra/bsr made be changed into jmp/jsr. */
1493 else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR)
1494 {
1495 opcode = m68hc11_new_insn (2);
1496 number_to_chars_bigendian (opcode, code, 1);
1497 number_to_chars_bigendian (opcode + 1, 0, 1);
1498 frag_var (rs_machine_dependent, 2, 1,
1499 ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF),
1500 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1501 }
1502 else if (current_architecture & cpu6812)
1503 {
1504 opcode = m68hc11_new_insn (2);
1505 number_to_chars_bigendian (opcode, code, 1);
1506 number_to_chars_bigendian (opcode + 1, 0, 1);
1507 frag_var (rs_machine_dependent, 2, 2,
1508 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF),
1509 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1510 }
1511 else
1512 {
1513 opcode = m68hc11_new_insn (2);
1514 number_to_chars_bigendian (opcode, code, 1);
1515 number_to_chars_bigendian (opcode + 1, 0, 1);
1516 frag_var (rs_machine_dependent, 3, 3,
1517 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF),
1518 operands[0].exp.X_add_symbol, (offsetT) n, opcode);
1519 }
1520 }
1521 }
1522
1523 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1524 static void
1525 build_dbranch_insn (opcode, operands, nb_operands, jmp_mode)
1526 struct m68hc11_opcode *opcode;
1527 operand operands[];
1528 int nb_operands;
1529 int jmp_mode;
1530 {
1531 unsigned char code;
1532 int insn_size;
1533 char *f;
1534 unsigned long n;
1535
1536 /* The relative branch convertion is not supported for
1537 brclr and brset. */
1538 assert ((opcode->format & M6811_OP_BITMASK) == 0);
1539 assert (nb_operands == 2);
1540 assert (operands[0].reg1 != REG_NONE);
1541
1542 code = opcode->opcode & 0x0FF;
1543 insn_size = 1;
1544
1545 f = m68hc11_new_insn (1);
1546 number_to_chars_bigendian (f, code, 1);
1547
1548 n = operands[1].exp.X_add_number;
1549 code = operands[0].reg1;
1550
1551 if (operands[0].reg1 == REG_NONE || operands[0].reg1 == REG_CCR
1552 || operands[0].reg1 == REG_PC)
1553 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1554
1555 if (opcode->format & M6812_OP_IBCC_MARKER)
1556 code |= 0x80;
1557 else if (opcode->format & M6812_OP_TBCC_MARKER)
1558 code |= 0x40;
1559
1560 if (!(opcode->format & M6812_OP_EQ_MARKER))
1561 code |= 0x20;
1562
1563 /* Turn into a long branch:
1564 - when force long branch option (and not for jbcc pseudos),
1565 - when jdbcc and the constant is out of -256..255 range,
1566 - when branch optimization is allowed and branch out of range. */
1567 if ((jmp_mode == 0 && flag_force_long_jumps)
1568 || (operands[1].exp.X_op == O_constant
1569 && (!check_range (n, M6812_OP_IBCC_MARKER) &&
1570 (jmp_mode == 1 || flag_fixed_branchs == 0))))
1571 {
1572 f = frag_more (2);
1573 code ^= 0x20;
1574 number_to_chars_bigendian (f, code, 1);
1575 number_to_chars_bigendian (f + 1, M6812_JMP, 1);
1576 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16);
1577 return;
1578 }
1579
1580 /* Branch with a constant that must fit in 9-bits. */
1581 if (operands[1].exp.X_op == O_constant)
1582 {
1583 if (!check_range (n, M6812_OP_IBCC_MARKER))
1584 {
1585 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1586 n);
1587 }
1588 else
1589 {
1590 if ((long) n < 0)
1591 code |= 0x10;
1592
1593 f = frag_more (2);
1594 number_to_chars_bigendian (f, code, 1);
1595 number_to_chars_bigendian (f + 1, n & 0x0FF, 1);
1596 }
1597 }
1598 else
1599 {
1600 /* Branch offset must fit in 8-bits, don't do some relax. */
1601 if (jmp_mode == 0 && flag_fixed_branchs)
1602 {
1603 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL);
1604 }
1605
1606 else
1607 {
1608 f = frag_more (2);
1609 number_to_chars_bigendian (f, code, 1);
1610 number_to_chars_bigendian (f + 1, 0, 1);
1611 frag_var (rs_machine_dependent, 3, 3,
1612 ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF),
1613 operands[1].exp.X_add_symbol, (offsetT) n, f);
1614 }
1615 }
1616 }
1617
1618 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
1619
1620 /* Assemble the post index byte for 68HC12 extended addressing modes. */
1621 static int
1622 build_indexed_byte (op, format, move_insn)
1623 operand *op;
1624 int format ATTRIBUTE_UNUSED;
1625 int move_insn;
1626 {
1627 unsigned char byte = 0;
1628 char *f;
1629 int mode;
1630 long val;
1631
1632 val = op->exp.X_add_number;
1633 mode = op->mode;
1634 if (mode & M6812_AUTO_INC_DEC)
1635 {
1636 byte = 0x20;
1637 if (mode & (M6812_POST_INC | M6812_POST_DEC))
1638 byte |= 0x10;
1639
1640 if (op->exp.X_op == O_constant)
1641 {
1642 if (!check_range (val, mode))
1643 {
1644 as_bad (_("Increment/decrement value is out of range: `%ld'."),
1645 val);
1646 }
1647 if (mode & (M6812_POST_INC | M6812_PRE_INC))
1648 byte |= (val - 1) & 0x07;
1649 else
1650 byte |= (8 - ((val) & 7)) | 0x8;
1651 }
1652 switch (op->reg1)
1653 {
1654 case REG_NONE:
1655 as_fatal (_("Expecting a register."));
1656
1657 case REG_X:
1658 byte |= 0;
1659 break;
1660
1661 case REG_Y:
1662 byte |= 0x40;
1663 break;
1664
1665 case REG_SP:
1666 byte |= 0x80;
1667 break;
1668
1669 default:
1670 as_bad (_("Invalid register for post/pre increment."));
1671 break;
1672 }
1673
1674 f = frag_more (1);
1675 number_to_chars_bigendian (f, byte, 1);
1676 return 1;
1677 }
1678
1679 if (mode & M6812_OP_IDX)
1680 {
1681 switch (op->reg1)
1682 {
1683 case REG_X:
1684 byte = 0;
1685 break;
1686
1687 case REG_Y:
1688 byte = 1;
1689 break;
1690
1691 case REG_SP:
1692 byte = 2;
1693 break;
1694
1695 case REG_PC:
1696 byte = 3;
1697 break;
1698
1699 default:
1700 as_bad (_("Invalid register."));
1701 break;
1702 }
1703 if (op->exp.X_op == O_constant)
1704 {
1705 if (!check_range (val, M6812_OP_IDX))
1706 {
1707 as_bad (_("Offset out of 16-bit range: %ld."), val);
1708 }
1709
1710 if (move_insn && !(val >= -16 && val <= 15))
1711 {
1712 as_bad (_("Offset out of 5-bit range for movw/movb insn."));
1713 return -1;
1714 }
1715
1716 if (val >= -16 && val <= 15 && !(mode & M6812_OP_IDX_2))
1717 {
1718 byte = byte << 6;
1719 byte |= val & 0x1f;
1720 f = frag_more (1);
1721 number_to_chars_bigendian (f, byte, 1);
1722 return 1;
1723 }
1724 else if (val >= -256 && val <= 255 && !(mode & M6812_OP_IDX_2))
1725 {
1726 byte = byte << 3;
1727 byte |= 0xe0;
1728 if (val < 0)
1729 byte |= 0x1;
1730 f = frag_more (2);
1731 number_to_chars_bigendian (f, byte, 1);
1732 number_to_chars_bigendian (f + 1, val & 0x0FF, 1);
1733 return 2;
1734 }
1735 else
1736 {
1737 byte = byte << 3;
1738 if (mode & M6812_OP_IDX_2)
1739 byte |= 0xe3;
1740 else
1741 byte |= 0xe2;
1742
1743 f = frag_more (3);
1744 number_to_chars_bigendian (f, byte, 1);
1745 number_to_chars_bigendian (f + 1, val & 0x0FFFF, 2);
1746 return 3;
1747 }
1748 }
1749 f = frag_more (1);
1750 number_to_chars_bigendian (f, byte, 1);
1751 #if 0
1752 fix_new_exp (frag_now, f - frag_now->fr_literal, 2,
1753 &op->exp, false, BFD_RELOC_16);
1754 #endif
1755 frag_var (rs_machine_dependent, 2, 2,
1756 ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF),
1757 op->exp.X_add_symbol, val, f);
1758 return 3;
1759 }
1760
1761 if (mode & M6812_OP_REG)
1762 {
1763 if (mode & M6812_OP_IDX_2)
1764 {
1765 if (op->reg1 != REG_D)
1766 as_bad (_("Expecting register D for indexed indirect mode."));
1767 if (move_insn)
1768 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
1769
1770 byte = 0xE7;
1771 }
1772 else
1773 {
1774 switch (op->reg1)
1775 {
1776 case REG_A:
1777 byte = 0xE4;
1778 break;
1779
1780 case REG_B:
1781 byte = 0xE5;
1782 break;
1783
1784 default:
1785 as_bad (_("Invalid accumulator register."));
1786
1787 case REG_D:
1788 byte = 0xE6;
1789 break;
1790 }
1791 }
1792 switch (op->reg2)
1793 {
1794 case REG_X:
1795 break;
1796
1797 case REG_Y:
1798 byte |= (1 << 3);
1799 break;
1800
1801 case REG_SP:
1802 byte |= (2 << 3);
1803 break;
1804
1805 case REG_PC:
1806 byte |= (3 << 3);
1807 break;
1808
1809 default:
1810 as_bad (_("Invalid indexed register."));
1811 break;
1812 }
1813 f = frag_more (1);
1814 number_to_chars_bigendian (f, byte, 1);
1815 return 1;
1816 }
1817
1818 as_fatal (_("Addressing mode not implemented yet."));
1819 return 0;
1820 }
1821
1822 /* Assemble the 68HC12 register mode byte. */
1823 static int
1824 build_reg_mode (op, format)
1825 operand *op;
1826 int format;
1827 {
1828 unsigned char byte;
1829 char *f;
1830
1831 if (format & M6812_OP_SEX_MARKER
1832 && op->reg1 != REG_A && op->reg1 != REG_B && op->reg1 != REG_CCR)
1833 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
1834 else if (op->reg1 == REG_NONE || op->reg1 == REG_PC)
1835 as_bad (_("Invalid source register."));
1836
1837 if (format & M6812_OP_SEX_MARKER
1838 && op->reg2 != REG_D
1839 && op->reg2 != REG_X && op->reg2 != REG_Y && op->reg2 != REG_SP)
1840 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
1841 else if (op->reg2 == REG_NONE || op->reg2 == REG_PC)
1842 as_bad (_("Invalid destination register."));
1843
1844 byte = (op->reg1 << 4) | (op->reg2);
1845 if (format & M6812_OP_EXG_MARKER)
1846 byte |= 0x80;
1847
1848 f = frag_more (1);
1849 number_to_chars_bigendian (f, byte, 1);
1850 return 1;
1851 }
1852
1853 /* build_insn takes a pointer to the opcode entry in the opcode table,
1854 the array of operand expressions and builds the correspding instruction.
1855 This operation only deals with non relative jumps insn (need special
1856 handling). */
1857 static void
1858 build_insn (opcode, operands, nb_operands)
1859 struct m68hc11_opcode *opcode;
1860 operand operands[];
1861 int nb_operands ATTRIBUTE_UNUSED;
1862 {
1863 int i;
1864 char *f;
1865 int insn_size = 1;
1866 long format;
1867 int move_insn = 0;
1868
1869 /* Put the page code instruction if there is one. */
1870 format = opcode->format;
1871 if (format & OP_EXTENDED)
1872 {
1873 int page_code;
1874
1875 f = m68hc11_new_insn (2);
1876 if (format & M6811_OP_PAGE2)
1877 page_code = M6811_OPCODE_PAGE2;
1878 else if (format & M6811_OP_PAGE3)
1879 page_code = M6811_OPCODE_PAGE3;
1880 else
1881 page_code = M6811_OPCODE_PAGE4;
1882
1883 number_to_chars_bigendian (f, page_code, 1);
1884 f++;
1885 insn_size = 2;
1886 }
1887 else
1888 f = m68hc11_new_insn (1);
1889
1890 number_to_chars_bigendian (f, opcode->opcode, 1);
1891
1892 i = 0;
1893
1894 /* The 68HC12 movb and movw instructions are special. We have to handle
1895 them in a special way. */
1896 if (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
1897 {
1898 move_insn = 1;
1899 if (format & M6812_OP_IDX)
1900 {
1901 insn_size += build_indexed_byte (&operands[0], format, 1);
1902 i = 1;
1903 format &= ~M6812_OP_IDX;
1904 }
1905 if (format & M6812_OP_IDX_P2)
1906 {
1907 insn_size += build_indexed_byte (&operands[1], format, 1);
1908 i = 0;
1909 format &= ~M6812_OP_IDX_P2;
1910 }
1911 }
1912
1913 if (format & (M6811_OP_DIRECT | M6811_OP_IMM8))
1914 {
1915 insn_size++;
1916 fixup8 (&operands[i].exp,
1917 format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID),
1918 operands[i].mode);
1919 i++;
1920 }
1921 else if (format & (M6811_OP_IMM16 | M6811_OP_IND16))
1922 {
1923 insn_size += 2;
1924 fixup16 (&operands[i].exp, format & (M6811_OP_IMM16 | M6811_OP_IND16),
1925 operands[i].mode);
1926 i++;
1927 }
1928 else if (format & (M6811_OP_IX | M6811_OP_IY))
1929 {
1930 if ((format & M6811_OP_IX) && (operands[0].reg1 != REG_X))
1931 as_bad (_("Invalid indexed register, expecting register X."));
1932 if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y))
1933 as_bad (_("Invalid indexed register, expecting register Y."));
1934
1935 insn_size++;
1936 fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode);
1937 i = 1;
1938 }
1939 else if (format &
1940 (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1 | M6812_OP_D_IDX))
1941 {
1942 insn_size += build_indexed_byte (&operands[i], format, move_insn);
1943 i++;
1944 }
1945 else if (format & M6812_OP_REG && current_architecture & cpu6812)
1946 {
1947 insn_size += build_reg_mode (&operands[i], format);
1948 i++;
1949 }
1950 if (format & M6811_OP_BITMASK)
1951 {
1952 insn_size++;
1953 fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode);
1954 i++;
1955 }
1956 if (format & M6811_OP_JUMP_REL)
1957 {
1958 insn_size++;
1959 fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode);
1960 i++;
1961 }
1962 else if (format & M6812_OP_IND16_P2)
1963 {
1964 insn_size += 2;
1965 fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode);
1966 }
1967 }
1968 \f
1969 /* Opcode identification and operand analysis. */
1970
1971 /* find() gets a pointer to an entry in the opcode table. It must look at all
1972 opcodes with the same name and use the operands to choose the correct
1973 opcode. Returns the opcode pointer if there was a match and 0 if none. */
1974 static struct m68hc11_opcode *
1975 find (opc, operands, nb_operands)
1976 struct m68hc11_opcode_def *opc;
1977 operand operands[];
1978 int nb_operands;
1979 {
1980 int i, match, pos;
1981 struct m68hc11_opcode *opcode;
1982 struct m68hc11_opcode *op_indirect;
1983
1984 op_indirect = 0;
1985 opcode = opc->opcode;
1986
1987 /* Now search the opcode table table for one with operands
1988 that matches what we've got. We're only done if the operands matched so
1989 far AND there are no more to check. */
1990 for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++)
1991 {
1992 int poss_indirect = 0;
1993 long format = opcode->format;
1994 int expect;
1995
1996 expect = 0;
1997 if (opcode->format & M6811_OP_MASK)
1998 expect++;
1999 if (opcode->format & M6811_OP_BITMASK)
2000 expect++;
2001 if (opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2002 expect++;
2003 if (opcode->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))
2004 expect++;
2005
2006 for (i = 0; expect == nb_operands && i < nb_operands; i++)
2007 {
2008 int mode = operands[i].mode;
2009
2010 if (mode & M6811_OP_IMM16)
2011 {
2012 if (format &
2013 (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK))
2014 continue;
2015 break;
2016 }
2017 if (mode == M6811_OP_DIRECT)
2018 {
2019 if (format & M6811_OP_DIRECT)
2020 continue;
2021
2022 /* If the operand is a page 0 operand, remember a
2023 possible <abs-16> addressing mode. We mark
2024 this and continue to check other operands. */
2025 if (format & M6811_OP_IND16
2026 && flag_strict_direct_addressing && op_indirect == 0)
2027 {
2028 poss_indirect = 1;
2029 continue;
2030 }
2031 break;
2032 }
2033 if (mode & M6811_OP_IND16)
2034 {
2035 if (i == 0 && (format & M6811_OP_IND16) != 0)
2036 continue;
2037 if (i != 0 && (format & M6812_OP_IND16_P2) != 0)
2038 continue;
2039 if (i == 0 && (format & M6811_OP_BITMASK))
2040 break;
2041 }
2042 if (mode & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2043 {
2044 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2045 continue;
2046 }
2047 if (mode & M6812_OP_REG)
2048 {
2049 if (i == 0
2050 && (format & M6812_OP_REG)
2051 && (operands[i].reg2 == REG_NONE))
2052 continue;
2053 if (i == 0
2054 && (format & M6812_OP_REG)
2055 && (format & M6812_OP_REG_2)
2056 && (operands[i].reg2 != REG_NONE))
2057 continue;
2058 if (i == 0
2059 && (format & M6812_OP_IDX)
2060 && (operands[i].reg2 != REG_NONE))
2061 continue;
2062 if (i == 0
2063 && (format & M6812_OP_D_IDX))
2064 continue;
2065 if (i == 0
2066 && (format & M6812_OP_IDX)
2067 && (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)))
2068 continue;
2069 if (i == 1
2070 && (format & M6812_OP_IDX_P2))
2071 continue;
2072 break;
2073 }
2074 if (mode & M6812_OP_IDX)
2075 {
2076 if (format & M6811_OP_IX && operands[i].reg1 == REG_X)
2077 continue;
2078 if (format & M6811_OP_IY && operands[i].reg1 == REG_Y)
2079 continue;
2080 if (i == 0
2081 && format & (M6812_OP_IDX | M6812_OP_IDX_1 | M6812_OP_IDX_2)
2082 && (operands[i].reg1 == REG_X
2083 || operands[i].reg1 == REG_Y
2084 || operands[i].reg1 == REG_SP
2085 || operands[i].reg1 == REG_PC))
2086 continue;
2087 if (i == 1 && format & M6812_OP_IDX_P2)
2088 continue;
2089 }
2090 if (mode & M6812_AUTO_INC_DEC)
2091 {
2092 if (i == 0
2093 && format & (M6812_OP_IDX | M6812_OP_IDX_1 |
2094 M6812_OP_IDX_2))
2095 continue;
2096 if (i == 1 && format & M6812_OP_IDX_P2)
2097 continue;
2098 }
2099 break;
2100 }
2101 match = i == nb_operands;
2102
2103 /* Operands are ok but an operand uses page 0 addressing mode
2104 while the insn supports abs-16 mode. Keep a reference to this
2105 insns in case there is no insn supporting page 0 addressing. */
2106 if (match && poss_indirect)
2107 {
2108 op_indirect = opcode;
2109 match = 0;
2110 }
2111 if (match)
2112 break;
2113 }
2114
2115 /* Page 0 addressing is used but not supported by any insn.
2116 If absolute addresses are supported, we use that insn. */
2117 if (match == 0 && op_indirect)
2118 {
2119 opcode = op_indirect;
2120 match = 1;
2121 }
2122
2123 if (!match)
2124 {
2125 return (0);
2126 }
2127
2128 return opcode;
2129 }
2130
2131 /* Find the real opcode and its associated operands. We use a progressive
2132 approach here. On entry, 'opc' points to the first opcode in the
2133 table that matches the opcode name in the source line. We try to
2134 isolate an operand, find a possible match in the opcode table.
2135 We isolate another operand if no match were found. The table 'operands'
2136 is filled while operands are recognized.
2137
2138 Returns the opcode pointer that matches the opcode name in the
2139 source line and the associated operands. */
2140 static struct m68hc11_opcode *
2141 find_opcode (opc, operands, nb_operands)
2142 struct m68hc11_opcode_def *opc;
2143 operand operands[];
2144 int *nb_operands;
2145 {
2146 struct m68hc11_opcode *opcode;
2147 int i;
2148
2149 if (opc->max_operands == 0)
2150 {
2151 *nb_operands = 0;
2152 return opc->opcode;
2153 }
2154
2155 for (i = 0; i < opc->max_operands;)
2156 {
2157 int result;
2158
2159 result = get_operand (&operands[i], i, opc->format);
2160 if (result <= 0)
2161 return 0;
2162
2163 /* Special case where the bitmask of the bclr/brclr
2164 instructions is not introduced by #.
2165 Example: bclr 3,x $80. */
2166 if (i == 1 && (opc->format & M6811_OP_BITMASK)
2167 && (operands[i].mode & M6811_OP_IND16))
2168 {
2169 operands[i].mode = M6811_OP_IMM16;
2170 }
2171
2172 i += result;
2173 *nb_operands = i;
2174 if (i >= opc->min_operands)
2175 {
2176 opcode = find (opc, operands, i);
2177 if (opcode)
2178 return opcode;
2179 }
2180
2181 if (*input_line_pointer == ',')
2182 input_line_pointer++;
2183 }
2184
2185 return 0;
2186 }
2187
2188 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2189 | M6812_OP_DBCC_MARKER \
2190 | M6812_OP_IBCC_MARKER)
2191 \f
2192 /* Gas line assembler entry point. */
2193
2194 /* This is the main entry point for the machine-dependent assembler. str
2195 points to a machine-dependent instruction. This function is supposed to
2196 emit the frags/bytes it assembles to. */
2197 void
2198 md_assemble (str)
2199 char *str;
2200 {
2201 struct m68hc11_opcode_def *opc;
2202 struct m68hc11_opcode *opcode;
2203
2204 unsigned char *op_start, *save;
2205 unsigned char *op_end;
2206 char name[20];
2207 int nlen = 0;
2208 operand operands[M6811_MAX_OPERANDS];
2209 int nb_operands;
2210 int branch_optimize = 0;
2211 int alias_id = -1;
2212
2213 /* Drop leading whitespace. */
2214 while (*str == ' ')
2215 str++;
2216
2217 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2218 lower case (the opcode table only has lower case op-codes). */
2219 for (op_start = op_end = (unsigned char *) (str);
2220 *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
2221 op_end++)
2222 {
2223 name[nlen] = tolower (op_start[nlen]);
2224 nlen++;
2225 }
2226 name[nlen] = 0;
2227
2228 if (nlen == 0)
2229 {
2230 as_bad (_("No instruction or missing opcode."));
2231 return;
2232 }
2233
2234 /* Find the opcode definition given its name. */
2235 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name);
2236
2237 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
2238 pseudo insns for relative branch. For these branchs, we always
2239 optimize them (turned into absolute branchs) even if --short-branchs
2240 is given. */
2241 if (opc == NULL && name[0] == 'j' && name[1] == 'b')
2242 {
2243 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, &name[1]);
2244 if (opc
2245 && (!(opc->format & M6811_OP_JUMP_REL)
2246 || (opc->format & M6811_OP_BITMASK)))
2247 opc = 0;
2248 if (opc)
2249 branch_optimize = 1;
2250 }
2251
2252 /* The following test should probably be removed. This is not conform
2253 to Motorola assembler specs. */
2254 if (opc == NULL && flag_mri)
2255 {
2256 if (*op_end == ' ' || *op_end == '\t')
2257 {
2258 while (*op_end == ' ' || *op_end == '\t')
2259 op_end++;
2260
2261 if (nlen < 19
2262 && (*op_end &&
2263 (is_end_of_line[op_end[1]]
2264 || op_end[1] == ' ' || op_end[1] == '\t'
2265 || !isalnum (op_end[1])))
2266 && (*op_end == 'a' || *op_end == 'b'
2267 || *op_end == 'A' || *op_end == 'B'
2268 || *op_end == 'd' || *op_end == 'D'
2269 || *op_end == 'x' || *op_end == 'X'
2270 || *op_end == 'y' || *op_end == 'Y'))
2271 {
2272 name[nlen++] = tolower (*op_end++);
2273 name[nlen] = 0;
2274 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash,
2275 name);
2276 }
2277 }
2278 }
2279
2280 /* Identify a possible instruction alias. There are some on the
2281 68HC12 to emulate a fiew 68HC11 instructions. */
2282 if (opc == NULL && (current_architecture & cpu6812))
2283 {
2284 int i;
2285
2286 for (i = 0; i < m68hc12_num_alias; i++)
2287 if (strcmp (m68hc12_alias[i].name, name) == 0)
2288 {
2289 alias_id = i;
2290 break;
2291 }
2292 }
2293 if (opc == NULL && alias_id < 0)
2294 {
2295 as_bad (_("Opcode `%s' is not recognized."), name);
2296 return;
2297 }
2298 save = input_line_pointer;
2299 input_line_pointer = op_end;
2300
2301 if (opc)
2302 {
2303 opc->used++;
2304 opcode = find_opcode (opc, operands, &nb_operands);
2305 }
2306 else
2307 opcode = 0;
2308
2309 if ((opcode || alias_id >= 0) && !flag_mri)
2310 {
2311 char *p = input_line_pointer;
2312
2313 while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r')
2314 p++;
2315
2316 if (*p != '\n' && *p)
2317 as_bad (_("Garbage at end of instruction: `%s'."), p);
2318 }
2319
2320 input_line_pointer = save;
2321
2322 if (alias_id >= 0)
2323 {
2324 char *f = m68hc11_new_insn (m68hc12_alias[alias_id].size);
2325
2326 number_to_chars_bigendian (f, m68hc12_alias[alias_id].code1, 1);
2327 if (m68hc12_alias[alias_id].size > 1)
2328 number_to_chars_bigendian (f + 1, m68hc12_alias[alias_id].code2, 1);
2329
2330 return;
2331 }
2332
2333 /* Opcode is known but does not have valid operands. Print out the
2334 syntax for this opcode. */
2335 if (opcode == 0)
2336 {
2337 if (flag_print_insn_syntax)
2338 print_insn_format (name);
2339
2340 as_bad (_("Invalid operand for `%s'"), name);
2341 return;
2342 }
2343
2344 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
2345 relative and must be in the range -256..255 (9-bits). */
2346 if ((opcode->format & M6812_XBCC_MARKER)
2347 && (opcode->format & M6811_OP_JUMP_REL))
2348 build_dbranch_insn (opcode, operands, nb_operands);
2349
2350 /* Relative jumps instructions are taken care of separately. We have to make
2351 sure that the relative branch is within the range -128..127. If it's out
2352 of range, the instructions are changed into absolute instructions.
2353 This is not supported for the brset and brclr instructions. */
2354 else if ((opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16))
2355 && !(opcode->format & M6811_OP_BITMASK))
2356 build_jump_insn (opcode, operands, nb_operands, branch_optimize);
2357 else
2358 build_insn (opcode, operands, nb_operands);
2359 }
2360 \f
2361 /* Relocation, relaxation and frag conversions. */
2362 long
2363 md_pcrel_from_section (fixp, sec)
2364 fixS *fixp;
2365 segT sec;
2366 {
2367 int adjust;
2368 if (fixp->fx_addsy != (symbolS *) NULL
2369 && (!S_IS_DEFINED (fixp->fx_addsy)
2370 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
2371 return 0;
2372
2373 adjust = fixp->fx_pcrel_adjust;
2374 return fixp->fx_frag->fr_address + fixp->fx_where + adjust;
2375 }
2376
2377 /* If while processing a fixup, a reloc really needs to be created
2378 then it is done here. */
2379 arelent *
2380 tc_gen_reloc (section, fixp)
2381 asection *section;
2382 fixS *fixp;
2383 {
2384 arelent *reloc;
2385
2386 reloc = (arelent *) xmalloc (sizeof (arelent));
2387 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2388 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
2389 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
2390 if (fixp->fx_r_type == 0)
2391 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16);
2392 else
2393 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
2394 if (reloc->howto == (reloc_howto_type *) NULL)
2395 {
2396 as_bad_where (fixp->fx_file, fixp->fx_line,
2397 _("Relocation %d is not supported by object file format."),
2398 (int) fixp->fx_r_type);
2399 return NULL;
2400 }
2401
2402 if (!fixp->fx_pcrel)
2403 reloc->addend = fixp->fx_addnumber;
2404 else
2405 reloc->addend = (section->vma
2406 + (fixp->fx_pcrel_adjust == 64
2407 ? -1 : fixp->fx_pcrel_adjust)
2408 + fixp->fx_addnumber
2409 + md_pcrel_from_section (fixp, section));
2410 return reloc;
2411 }
2412
2413 void
2414 md_convert_frag (abfd, sec, fragP)
2415 bfd *abfd ATTRIBUTE_UNUSED;
2416 asection *sec ATTRIBUTE_UNUSED;
2417 fragS *fragP;
2418 {
2419 fixS *fixp;
2420 long disp;
2421 char *buffer_address = fragP->fr_literal;
2422
2423 /* Address in object code of the displacement. */
2424 register int object_address = fragP->fr_fix + fragP->fr_address;
2425
2426 buffer_address += fragP->fr_fix;
2427
2428 /* The displacement of the address, from current location. */
2429 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
2430 disp = (disp + fragP->fr_offset) - object_address;
2431 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
2432
2433 switch (fragP->fr_subtype)
2434 {
2435 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE):
2436 fragP->fr_opcode[1] = disp;
2437 break;
2438
2439 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD):
2440 /* This relax is only for bsr and bra. */
2441 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2442 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2443 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2444
2445 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]);
2446
2447 fix_new (fragP, fragP->fr_fix - 1, 2,
2448 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2449 fragP->fr_fix += 1;
2450 break;
2451
2452 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE):
2453 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_BYTE):
2454 fragP->fr_opcode[1] = disp;
2455 break;
2456
2457 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD):
2458 /* Invert branch. */
2459 fragP->fr_opcode[0] ^= 1;
2460 fragP->fr_opcode[1] = 3; /* Branch offset. */
2461 buffer_address[0] = M6811_JMP;
2462 fix_new (fragP, fragP->fr_fix + 1, 2,
2463 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2464 fragP->fr_fix += 3;
2465 break;
2466
2467 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD):
2468 /* Translate branch into a long branch. */
2469 fragP->fr_opcode[1] = fragP->fr_opcode[0];
2470 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2;
2471
2472 fixp = fix_new (fragP, fragP->fr_fix, 2,
2473 fragP->fr_symbol, fragP->fr_offset, 1,
2474 BFD_RELOC_16_PCREL);
2475 fixp->fx_pcrel_adjust = 2;
2476 fragP->fr_fix += 2;
2477 break;
2478
2479 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5):
2480 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 5;
2481 fragP->fr_opcode[0] |= disp & 0x1f;
2482 break;
2483
2484 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9):
2485 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3);
2486 fragP->fr_opcode[0] |= 0xE0;
2487 fix_new (fragP, fragP->fr_fix + 1, 1,
2488 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_8);
2489 fragP->fr_fix += 1;
2490 break;
2491
2492 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16):
2493 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3);
2494 fragP->fr_opcode[0] |= 0xE2;
2495 fix_new (fragP, fragP->fr_fix, 2,
2496 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2497 fragP->fr_fix += 1;
2498 break;
2499
2500 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE):
2501 if (disp < 0)
2502 fragP->fr_opcode[0] |= 0x10;
2503
2504 fragP->fr_opcode[1] = disp & 0x0FF;
2505 break;
2506
2507 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD):
2508 /* Invert branch. */
2509 fragP->fr_opcode[0] ^= 0x20;
2510 fragP->fr_opcode[1] = 3; /* Branch offset. */
2511 buffer_address[0] = M6812_JMP;
2512 fix_new (fragP, fragP->fr_fix + 1, 2,
2513 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16);
2514 fragP->fr_fix += 3;
2515 break;
2516
2517 default:
2518 break;
2519 }
2520 }
2521
2522 /* Force truly undefined symbols to their maximum size, and generally set up
2523 the frag list to be relaxed. */
2524 int
2525 md_estimate_size_before_relax (fragP, segment)
2526 fragS *fragP;
2527 asection *segment;
2528 {
2529 int old_fr_fix;
2530 char *buffer_address = fragP->fr_fix + fragP->fr_literal;
2531
2532 old_fr_fix = fragP->fr_fix;
2533
2534 switch (fragP->fr_subtype)
2535 {
2536 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF):
2537
2538 /* This relax is only for bsr and bra. */
2539 assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR)
2540 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA)
2541 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR));
2542
2543 /* A relaxable case. */
2544 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2545 {
2546 fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE);
2547 }
2548 else
2549 {
2550 if (flag_fixed_branchs)
2551 as_bad_where (fragP->fr_file, fragP->fr_line,
2552 _("bra or bsr with undefined symbol."));
2553
2554 /* The symbol is undefined or in a separate section. Turn bra into a
2555 jmp and bsr into a jsr. The insn becomes 3 bytes long (instead of
2556 2). A fixup is necessary for the unresolved symbol address. */
2557
2558 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]);
2559
2560 fragP->fr_fix++;
2561 fix_new (fragP, old_fr_fix - 1, 2, fragP->fr_symbol,
2562 fragP->fr_offset, 0, BFD_RELOC_16);
2563 frag_wane (fragP);
2564 }
2565 break;
2566
2567 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF):
2568 assert (current_architecture & cpu6811);
2569
2570 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2571 {
2572 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH,
2573 STATE_BYTE);
2574 }
2575 else
2576 {
2577 fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */
2578 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
2579
2580 /* Don't use fr_opcode[2] because this may be
2581 in a different frag. */
2582 buffer_address[0] = M6811_JMP;
2583
2584 fragP->fr_fix++;
2585 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2586 fragP->fr_offset, 0, BFD_RELOC_16);
2587 fragP->fr_fix += 2;
2588 frag_wane (fragP);
2589 }
2590 break;
2591
2592 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF):
2593 assert (current_architecture & cpu6812);
2594
2595 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2596 {
2597 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET,
2598 STATE_BITS5);
2599 }
2600 else
2601 {
2602 /* Switch the indexed operation to 16-bit mode. */
2603 if ((fragP->fr_opcode[1] & 0x21) == 0x20)
2604 fragP->fr_opcode[1] = (fragP->fr_opcode[1] >> 3) | 0xc0 | 0x02;
2605
2606 fragP->fr_fix++;
2607 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2608 fragP->fr_offset, 0, BFD_RELOC_16);
2609 fragP->fr_fix += 2;
2610 frag_wane (fragP);
2611 }
2612 break;
2613
2614 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF):
2615 assert (current_architecture & cpu6812);
2616
2617 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2618 {
2619 fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE);
2620 }
2621 else
2622 {
2623 fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */
2624 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */
2625
2626 /* Don't use fr_opcode[2] because this may be
2627 in a different frag. */
2628 buffer_address[0] = M6812_JMP;
2629
2630 fragP->fr_fix++;
2631 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2632 fragP->fr_offset, 0, BFD_RELOC_16);
2633 fragP->fr_fix += 2;
2634 frag_wane (fragP);
2635 }
2636 break;
2637
2638 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF):
2639 assert (current_architecture & cpu6812);
2640
2641 if (S_GET_SEGMENT (fragP->fr_symbol) == segment)
2642 {
2643 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812,
2644 STATE_BYTE);
2645 }
2646 else
2647 {
2648 /* Translate into a lbcc branch. */
2649 fragP->fr_opcode[1] = fragP->fr_opcode[0];
2650 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2;
2651
2652 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
2653 fragP->fr_offset, 0, BFD_RELOC_16_PCREL);
2654 fragP->fr_fix += 2;
2655 frag_wane (fragP);
2656 }
2657 break;
2658
2659 default:
2660 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype);
2661 }
2662
2663 return (fragP->fr_fix - old_fr_fix);
2664 }
2665
2666 int
2667 md_apply_fix (fixp, valuep)
2668 fixS *fixp;
2669 valueT *valuep;
2670 {
2671 char *where;
2672 long value;
2673 int op_type;
2674
2675 if (fixp->fx_addsy == (symbolS *) NULL)
2676 {
2677 value = *valuep;
2678 fixp->fx_done = 1;
2679 }
2680 else if (fixp->fx_pcrel)
2681 {
2682 value = *valuep;
2683 }
2684 else
2685 {
2686 value = fixp->fx_offset;
2687 if (fixp->fx_subsy != (symbolS *) NULL)
2688 {
2689 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
2690 {
2691 value -= S_GET_VALUE (fixp->fx_subsy);
2692 }
2693 else
2694 {
2695 /* We don't actually support subtracting a symbol. */
2696 as_bad_where (fixp->fx_file, fixp->fx_line,
2697 _("Expression too complex."));
2698 }
2699 }
2700 }
2701
2702 op_type = fixp->fx_r_type;
2703
2704 /* Patch the instruction with the resolved operand. Elf relocation
2705 info will also be generated to take care of linker/loader fixups.
2706 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
2707 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
2708 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
2709 because it's either resolved or turned out into non-relative insns (see
2710 relax table, bcc, bra, bsr transformations)
2711
2712 The BFD_RELOC_32 is necessary for the support of --gstabs. */
2713 where = fixp->fx_frag->fr_literal + fixp->fx_where;
2714
2715 switch (fixp->fx_r_type)
2716 {
2717 case BFD_RELOC_32:
2718 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
2719 break;
2720
2721 case BFD_RELOC_16:
2722 case BFD_RELOC_16_PCREL:
2723 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
2724 if (value < -65537 || value > 65535)
2725 as_bad_where (fixp->fx_file, fixp->fx_line,
2726 _("Value out of 16-bit range."));
2727 break;
2728
2729 case BFD_RELOC_M68HC11_HI8:
2730 value = value >> 8;
2731 /* Fall through. */
2732
2733 case BFD_RELOC_M68HC11_LO8:
2734 case BFD_RELOC_8:
2735 #if 0
2736 bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
2737 #endif
2738 ((bfd_byte *) where)[0] = (bfd_byte) value;
2739 break;
2740
2741 case BFD_RELOC_8_PCREL:
2742 #if 0
2743 bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
2744 #endif
2745 ((bfd_byte *) where)[0] = (bfd_byte) value;
2746
2747 if (value < -128 || value > 127)
2748 as_bad_where (fixp->fx_file, fixp->fx_line,
2749 _("Value %ld too large for 8-bit PC-relative branch."),
2750 value);
2751 break;
2752
2753 case BFD_RELOC_M68HC11_3B:
2754 if (value <= 0 || value > 8)
2755 as_bad_where (fixp->fx_file, fixp->fx_line,
2756 _("Auto increment/decrement offset '%ld' is out of range."),
2757 value);
2758 if (where[0] & 0x8)
2759 value = 8 - value;
2760 else
2761 value--;
2762
2763 where[0] = where[0] | (value & 0x07);
2764 break;
2765
2766 default:
2767 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
2768 fixp->fx_line, fixp->fx_r_type);
2769 }
2770
2771 return 0;
2772 }
2773
2774 int
2775 m68hc11_cleanup ()
2776 {
2777 return 1;
2778 }
2779
2780 void
2781 m68hc11_end_of_source ()
2782 {
2783 segT saved_seg;
2784 subsegT saved_subseg;
2785 segT debug_info;
2786 char *p;
2787 long total_size = 0;
2788
2789 if (debug_type != DEBUG_DWARF2)
2790 return;
2791
2792 dwarf2_finish ();
2793
2794 saved_seg = now_seg;
2795 saved_subseg = now_subseg;
2796
2797 debug_info = subseg_new (".debug_info", 0);
2798 bfd_set_section_flags (stdoutput, debug_info, SEC_READONLY);
2799 subseg_set (debug_info, 0);
2800 p = frag_more (10);
2801 total_size = 12;
2802
2803 # define STUFF(val,size) md_number_to_chars (p, val, size); p += size;
2804 STUFF (total_size, 4); /* Length of compilation unit. */
2805 STUFF (2, 2); /* Dwarf version */
2806 STUFF (0, 4);
2807 STUFF (2, 1); /* Pointer size */
2808 STUFF (1, 1); /* Compile unit */
2809 STUFF (0, 4);
2810
2811 now_subseg = saved_subseg;
2812 now_seg = saved_seg;
2813 }