1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
2 Copyright (C) 1999-2021 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
4 XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
26 #include "opcode/m68hc11.h"
27 #include "dwarf2dbg.h"
28 #include "elf/m68hc11.h"
30 const char comment_chars
[] = ";!";
31 const char line_comment_chars
[] = "#*";
32 const char line_separator_chars
[] = "";
34 const char EXP_CHARS
[] = "eE";
35 const char FLT_CHARS
[] = "dD";
37 #define STATE_CONDITIONAL_BRANCH (1)
38 #define STATE_PC_RELATIVE (2)
39 #define STATE_INDEXED_OFFSET (3)
40 #define STATE_INDEXED_PCREL (4)
41 #define STATE_XBCC_BRANCH (5)
42 #define STATE_CONDITIONAL_BRANCH_6812 (6)
44 #define STATE_BYTE (0)
45 #define STATE_BITS5 (0)
46 #define STATE_WORD (1)
47 #define STATE_BITS9 (1)
48 #define STATE_LONG (2)
49 #define STATE_BITS16 (2)
50 #define STATE_UNDF (3) /* Symbol undefined in pass1 */
52 /* This macro has no side-effects. */
53 #define ENCODE_RELAX(what,length) (((what) << 2) + (length))
54 #define RELAX_STATE(s) ((s) >> 2)
55 #define RELAX_LENGTH(s) ((s) & 3)
57 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF))
59 /* This table describes how you change sizes for the various types of variable
60 size expressions. This version only supports two kinds. */
63 How far Forward this mode will reach.
64 How far Backward this mode will reach.
65 How many bytes this mode will add to the size of the frag.
66 Which mode to go to if the offset won't fit in this one. */
68 relax_typeS md_relax_table
[] =
70 {1, 1, 0, 0}, /* First entries aren't used. */
71 {1, 1, 0, 0}, /* For no good reason except. */
72 {1, 1, 0, 0}, /* that the VAX doesn't either. */
76 These insns are translated into b!cc +3 jmp L. */
77 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
)},
82 /* Relax for bsr <L> and bra <L>.
83 These insns are translated into jsr and jmp. */
84 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
)},
89 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */
90 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
)},
91 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
)},
95 /* Relax for PC relative offset: 5-bits, 9-bits, 16-bits.
96 For the 9-bit case, there will be a -1 correction to take into
97 account the new byte that's why the range is -255..256. */
98 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
)},
99 {(256), (-255), 1, ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
)},
103 /* Relax for dbeq/ibeq/tbeq r,<L>:
104 These insns are translated into db!cc +3 jmp L. */
105 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
)},
110 /* Relax for bcc <L> on 68HC12.
111 These insns are translated into lbcc <L>. */
112 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
)},
119 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */
120 typedef enum register_id
144 typedef struct operand
152 struct m68hc11_opcode_def
159 struct m68hc11_opcode
*opcode
;
162 static struct m68hc11_opcode_def
*m68hc11_opcode_defs
= 0;
163 static int m68hc11_nb_opcode_defs
= 0;
171 static alias alias_opcodes
[] =
179 struct m9s12xg_opcode_def
186 struct m9s12xg_opcode
*opcode
;
189 /* Local functions. */
190 static register_id
reg_name_search (char *);
191 static register_id
register_name (void);
192 static int cmp_opcode (struct m68hc11_opcode
*, struct m68hc11_opcode
*);
193 static char *print_opcode_format (struct m68hc11_opcode
*, int);
194 static char *skip_whites (char *);
195 static int check_range (long, int);
196 static void print_opcode_list (void);
197 static void get_default_target (void);
198 static void print_insn_format (char *);
199 static int get_operand (operand
*, int, long);
200 static void fixup8 (expressionS
*, int, int);
201 static void fixup16 (expressionS
*, int, int);
202 static void fixup24 (expressionS
*, int, int);
203 static void fixup8_xg (expressionS
*, int, int);
204 static unsigned char convert_branch (unsigned char);
205 static char *m68hc11_new_insn (int);
206 static void build_dbranch_insn (struct m68hc11_opcode
*,
207 operand
*, int, int);
208 static int build_indexed_byte (operand
*, int, int);
209 static int build_reg_mode (operand
*, int);
211 static struct m68hc11_opcode
*find (struct m68hc11_opcode_def
*,
213 static struct m68hc11_opcode
*find_opcode (struct m68hc11_opcode_def
*,
215 static void build_jump_insn (struct m68hc11_opcode
*, operand
*, int, int);
216 static void build_insn_xg (struct m68hc11_opcode
*, operand
*, int);
217 static void build_insn (struct m68hc11_opcode
*, operand
*, int);
218 static int relaxable_symbol (symbolS
*);
220 /* Pseudo op to indicate a relax group. */
221 static void s_m68hc11_relax (int);
223 /* Pseudo op to control the ELF flags. */
224 static void s_m68hc11_mode (int);
226 /* Process directives specified via pseudo ops. */
227 static void s_m68hc11_parse_pseudo_instruction (int);
229 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
230 are using 'rtc' for returning. It is necessary to use 'call'
231 to invoke them. This is also used by the debugger to correctly
232 find the stack frame. */
233 static void s_m68hc11_mark_symbol (int);
235 /* Controls whether relative branches can be turned into long branches.
236 When the relative offset is too large, the insn are changed:
244 Setting the flag forbids this. */
245 static short flag_fixed_branches
= 0;
247 /* Force to use long jumps (absolute) instead of relative branches. */
248 static short flag_force_long_jumps
= 0;
250 /* Change the direct addressing mode into an absolute addressing mode
251 when the insn does not support direct addressing.
252 For example, "clr *ZD0" is normally not possible and is changed
254 static short flag_strict_direct_addressing
= 1;
256 /* When an opcode has invalid operand, print out the syntax of the opcode
258 static short flag_print_insn_syntax
= 0;
260 /* Dumps the list of instructions with syntax and then exit:
261 1 -> Only dumps the list (sorted by name)
262 2 -> Generate an example (or test) that can be compiled. */
263 static short flag_print_opcodes
= 0;
265 /* Opcode hash table. */
266 static htab_t m68hc11_hash
;
268 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically
269 by 'get_default_target' by looking at default BFD vector. This is overridden
270 with the -m<cpu> option. */
271 static int current_architecture
= 0;
273 /* Default cpu determined by 'get_default_target'. */
274 static const char *default_cpu
;
276 /* Number of opcodes in the sorted table (filtered by current cpu). */
277 static int num_opcodes
;
279 /* The opcodes sorted by name and filtered by current cpu. */
280 static struct m68hc11_opcode
*m68hc11_sorted_opcodes
;
282 /* ELF flags to set in the output file header. */
283 static int elf_flags
= E_M68HC11_F64
;
285 /* These are the machine dependent pseudo-ops. These are included so
286 the assembler can work on the output from the SUN C compiler, which
289 /* This table describes all the machine specific pseudo-ops the assembler
290 has to support. The fields are:
291 pseudo-op name without dot
292 function to call to execute this pseudo-op
293 Integer arg to pass to the function. */
294 const pseudo_typeS md_pseudo_table
[] =
296 /* The following pseudo-ops are supported for MRI compatibility. */
300 {"fcc", stringer
, 8 + 1},
304 {"xrefb", s_ignore
, 0}, /* Same as xref */
306 /* Gcc driven relaxation. */
307 {"relax", s_m68hc11_relax
, 0},
309 /* .mode instruction (ala SH). */
310 {"mode", s_m68hc11_mode
, 0},
312 /* .far instruction. */
313 {"far", s_m68hc11_mark_symbol
, STO_M68HC12_FAR
},
315 /* .interrupt instruction. */
316 {"interrupt", s_m68hc11_mark_symbol
, STO_M68HC12_INTERRUPT
},
318 /* .nobankwarning instruction. */
319 {"nobankwarning", s_m68hc11_parse_pseudo_instruction
, E_M68HC11_NO_BANK_WARNING
},
324 /* Options and initialization. */
326 const char *md_shortopts
= "Sm:";
328 struct option md_longopts
[] =
330 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
331 {"force-long-branches", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
},
332 {"force-long-branchs", no_argument
, NULL
, OPTION_FORCE_LONG_BRANCH
}, /* Misspelled version kept for backwards compatibility. */
334 #define OPTION_SHORT_BRANCHES (OPTION_MD_BASE + 1)
335 {"short-branches", no_argument
, NULL
, OPTION_SHORT_BRANCHES
},
336 {"short-branchs", no_argument
, NULL
, OPTION_SHORT_BRANCHES
}, /* Misspelled version kept for backwards compatibility. */
338 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
339 {"strict-direct-mode", no_argument
, NULL
, OPTION_STRICT_DIRECT_MODE
},
341 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3)
342 {"print-insn-syntax", no_argument
, NULL
, OPTION_PRINT_INSN_SYNTAX
},
344 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4)
345 {"print-opcodes", no_argument
, NULL
, OPTION_PRINT_OPCODES
},
347 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5)
348 {"generate-example", no_argument
, NULL
, OPTION_GENERATE_EXAMPLE
},
350 #define OPTION_MSHORT (OPTION_MD_BASE + 6)
351 {"mshort", no_argument
, NULL
, OPTION_MSHORT
},
353 #define OPTION_MLONG (OPTION_MD_BASE + 7)
354 {"mlong", no_argument
, NULL
, OPTION_MLONG
},
356 #define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8)
357 {"mshort-double", no_argument
, NULL
, OPTION_MSHORT_DOUBLE
},
359 #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9)
360 {"mlong-double", no_argument
, NULL
, OPTION_MLONG_DOUBLE
},
362 #define OPTION_XGATE_RAMOFFSET (OPTION_MD_BASE + 10)
363 {"xgate-ramoffset", no_argument
, NULL
, OPTION_XGATE_RAMOFFSET
},
365 {NULL
, no_argument
, NULL
, 0}
367 size_t md_longopts_size
= sizeof (md_longopts
);
369 /* Get the target cpu for the assembler. This is based on the configure
370 options and on the -m68hc11/-m68hc12 option. If no option is specified,
371 we must get the default. */
373 m68hc11_arch_format (void)
375 get_default_target ();
376 if (current_architecture
& cpu6811
)
377 return "elf32-m68hc11";
379 return "elf32-m68hc12";
382 enum bfd_architecture
385 get_default_target ();
386 if (current_architecture
& cpu6811
)
387 return bfd_arch_m68hc11
;
389 return bfd_arch_m68hc12
;
398 /* Listing header selected according to cpu. */
400 m68hc11_listing_header (void)
402 if (current_architecture
& cpu6811
)
403 return "M68HC11 GAS ";
404 else if (current_architecture
& cpuxgate
)
406 else if (current_architecture
& cpu9s12x
)
409 return "M68HC12 GAS ";
413 md_show_usage (FILE *stream
)
415 get_default_target ();
416 fprintf (stream
, _("\
417 Motorola 68HC11/68HC12/68HCS12 options:\n\
418 -m68hc11 | -m68hc12 |\n\
419 -m68hcs12 | -mm9s12x |\n\
420 -mm9s12xg specify the processor [default %s]\n\
421 -mshort use 16-bit int ABI (default)\n\
422 -mlong use 32-bit int ABI\n\
423 -mshort-double use 32-bit double ABI\n\
424 -mlong-double use 64-bit double ABI (default)\n\
425 --force-long-branches always turn relative branches into absolute ones\n\
426 -S,--short-branches do not turn relative branches into absolute ones\n\
427 when the offset is out of range\n\
428 --strict-direct-mode do not turn the direct mode into extended mode\n\
429 when the instruction does not support direct mode\n\
430 --print-insn-syntax print the syntax of instruction in case of error\n\
431 --print-opcodes print the list of instructions with syntax\n\
432 --xgate-ramoffset offset ram addresses by 0xc000\n\
433 --generate-example generate an example of each instruction\n\
434 (used for testing)\n"), default_cpu
);
438 /* Try to identify the default target based on the BFD library. */
440 get_default_target (void)
442 const bfd_target
*target
;
445 if (current_architecture
!= 0)
448 default_cpu
= "unknown";
449 target
= bfd_find_target (0, &abfd
);
450 if (target
&& target
->name
)
452 if (strcmp (target
->name
, "elf32-m68hc12") == 0)
454 current_architecture
= cpu6812
;
455 default_cpu
= "m68hc12";
457 else if (strcmp (target
->name
, "elf32-m68hc11") == 0)
459 current_architecture
= cpu6811
;
460 default_cpu
= "m68hc11";
464 as_bad (_("Default target `%s' is not supported."), target
->name
);
470 m68hc11_print_statistics (FILE *file
)
473 struct m68hc11_opcode_def
*opc
;
475 htab_print_statistics (file
, "opcode table", m68hc11_hash
);
477 opc
= m68hc11_opcode_defs
;
478 if (opc
== 0 || m68hc11_nb_opcode_defs
== 0)
481 /* Dump the opcode statistics table. */
482 fprintf (file
, _("Name # Modes Min ops Max ops Modes mask # Used\n"));
483 for (i
= 0; i
< m68hc11_nb_opcode_defs
; i
++, opc
++)
485 fprintf (file
, "%-7.7s %5d %7d %7d 0x%08lx %7d\n",
488 opc
->min_operands
, opc
->max_operands
, opc
->format
, opc
->used
);
493 md_parse_option (int c
, const char *arg
)
495 get_default_target ();
498 /* -S means keep external to 2 bit offset rather than 16 bit one. */
499 case OPTION_SHORT_BRANCHES
:
501 flag_fixed_branches
= 1;
504 case OPTION_FORCE_LONG_BRANCH
:
505 flag_force_long_jumps
= 1;
508 case OPTION_PRINT_INSN_SYNTAX
:
509 flag_print_insn_syntax
= 1;
512 case OPTION_PRINT_OPCODES
:
513 flag_print_opcodes
= 1;
516 case OPTION_STRICT_DIRECT_MODE
:
517 flag_strict_direct_addressing
= 0;
520 case OPTION_GENERATE_EXAMPLE
:
521 flag_print_opcodes
= 2;
525 elf_flags
&= ~E_M68HC11_I32
;
529 elf_flags
|= E_M68HC11_I32
;
532 case OPTION_MSHORT_DOUBLE
:
533 elf_flags
&= ~E_M68HC11_F64
;
536 case OPTION_MLONG_DOUBLE
:
537 elf_flags
|= E_M68HC11_F64
;
540 case OPTION_XGATE_RAMOFFSET
:
541 elf_flags
|= E_M68HC11_XGATE_RAMOFFSET
;
545 if ((strcasecmp (arg
, "68hc11") == 0)
546 || (strcasecmp (arg
, "m68hc11") == 0))
547 current_architecture
= cpu6811
;
548 else if ((strcasecmp (arg
, "68hc12") == 0)
549 || (strcasecmp (arg
, "m68hc12") == 0))
550 current_architecture
= cpu6812
;
551 else if ((strcasecmp (arg
, "68hcs12") == 0)
552 || (strcasecmp (arg
, "m68hcs12") == 0))
553 current_architecture
= cpu6812
| cpu6812s
;
554 else if (strcasecmp (arg
, "m9s12x") == 0)
555 current_architecture
= cpu6812
| cpu6812s
| cpu9s12x
;
556 else if ((strcasecmp (arg
, "m9s12xg") == 0)
557 || (strcasecmp (arg
, "xgate") == 0))
558 /* xgate for backwards compatibility */
559 current_architecture
= cpuxgate
;
561 as_bad (_("Option `%s' is not recognized."), arg
);
572 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
578 md_atof (int type
, char *litP
, int *sizeP
)
580 return ieee_md_atof (type
, litP
, sizeP
, TRUE
);
584 md_section_align (asection
*seg
, valueT addr
)
586 int align
= bfd_section_alignment (seg
);
587 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
591 cmp_opcode (struct m68hc11_opcode
*op1
, struct m68hc11_opcode
*op2
)
593 return strcmp (op1
->name
, op2
->name
);
596 #define IS_CALL_SYMBOL(MODE) \
597 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \
598 == ((M6812_OP_PAGE|M6811_OP_IND16)))
600 /* Initialize the assembler. Create the opcode hash table
601 (sorted on the names) with the M6811 opcode table
602 (from opcode library). */
606 const char *prev_name
= "";
607 struct m68hc11_opcode
*opcodes
;
608 struct m68hc11_opcode_def
*opc
= 0;
611 get_default_target ();
613 m68hc11_hash
= str_htab_create ();
615 /* Get a writable copy of the opcode table and sort it on the names. */
616 opcodes
= XNEWVEC (struct m68hc11_opcode
, m68hc11_num_opcodes
);
617 m68hc11_sorted_opcodes
= opcodes
;
619 for (i
= 0; i
< m68hc11_num_opcodes
; i
++)
621 if (m68hc11_opcodes
[i
].arch
& current_architecture
)
623 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
624 if (opcodes
[num_opcodes
].name
[0] == 'b'
625 && opcodes
[num_opcodes
].format
& M6811_OP_JUMP_REL
626 && !(opcodes
[num_opcodes
].format
& M6811_OP_BITMASK
))
629 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
632 for (j
= 0; alias_opcodes
[j
].name
!= 0; j
++)
633 if (strcmp (m68hc11_opcodes
[i
].name
, alias_opcodes
[j
].name
) == 0)
635 opcodes
[num_opcodes
] = m68hc11_opcodes
[i
];
636 opcodes
[num_opcodes
].name
= alias_opcodes
[j
].alias
;
642 qsort (opcodes
, num_opcodes
, sizeof (struct m68hc11_opcode
),
643 (int (*) (const void*, const void*)) cmp_opcode
);
645 opc
= XNEWVEC (struct m68hc11_opcode_def
, num_opcodes
);
646 m68hc11_opcode_defs
= opc
--;
648 /* Insert unique names into hash table. The M6811 instruction set
649 has several identical opcode names that have different opcodes based
650 on the operands. This hash table then provides a quick index to
651 the first opcode with a particular name in the opcode table. */
652 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
656 if (strcmp (prev_name
, opcodes
->name
))
658 prev_name
= (char *) opcodes
->name
;
662 opc
->min_operands
= 100;
663 opc
->max_operands
= 0;
665 opc
->opcode
= opcodes
;
667 str_hash_insert (m68hc11_hash
, opcodes
->name
, opc
, 0);
670 opc
->format
|= opcodes
->format
;
672 /* See how many operands this opcode needs. */
674 if (opcodes
->arch
== cpuxgate
)
676 if (opcodes
->format
& (M68XG_OP_IMM3
| M68XG_OP_R
| M68XG_OP_REL9
679 else if (opcodes
->format
& (M68XG_OP_R_R
| M68XG_OP_R_IMM4
680 | M68XG_OP_R_IMM8
| M68XG_OP_R_IMM8
))
682 else if (opcodes
->format
& (M68XG_OP_R_R_R
| M68XG_OP_R_R_OFFS5
683 | M68XG_OP_RD_RB_RI
| M68XG_OP_RD_RB_RIp
684 | M68XG_OP_RD_RB_mRI
))
689 if (opcodes
->format
& M6811_OP_MASK
)
691 if (opcodes
->format
& M6811_OP_BITMASK
)
693 if (opcodes
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
695 if (opcodes
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
697 /* Special case for call instruction. */
698 if ((opcodes
->format
& M6812_OP_PAGE
)
699 && !(opcodes
->format
& M6811_OP_IND16
))
703 if (expect
< opc
->min_operands
)
704 opc
->min_operands
= expect
;
705 if (IS_CALL_SYMBOL (opcodes
->format
))
707 if (expect
> opc
->max_operands
)
708 opc
->max_operands
= expect
;
711 m68hc11_nb_opcode_defs
= opc
- m68hc11_opcode_defs
;
713 if (flag_print_opcodes
)
715 print_opcode_list ();
721 m68hc11_init_after_args (void)
727 /* Return a string that represents the operand format for the instruction.
728 When example is true, this generates an example of operand. This is used
729 to give an example and also to generate a test. */
732 print_opcode_format (struct m68hc11_opcode
*opcode
, int example
)
734 static char buf
[128];
735 int format
= opcode
->format
;
741 if (current_architecture
== cpuxgate
)
743 if (format
& M68XG_OP_IMM3
)
746 sprintf (p
, "#%d", rand () & 0x007);
748 strcpy (p
, _("imm3"));
751 else if (format
& M68XG_OP_R
)
754 sprintf (p
, "R%d", rand () & 0x07);
759 else if (format
& M68XG_OP_R_R
)
762 sprintf (p
, "R%d,R%d", rand () & 0x07, rand () & 0x07);
764 strcpy (p
, _("RD,RS"));
767 else if (format
& M68XG_OP_R_IMM4
)
770 sprintf (p
, "R%d,#%d", rand () & 0x07, rand () & 0x0f);
772 strcpy (p
, _("RI, #imm4"));
775 else if (format
& M68XG_OP_R_R_R
)
778 sprintf (p
, "R%d,R%d,R%d", rand () & 0x07, rand () & 0x07, rand () & 0x07);
780 strcpy (p
, "RD,RS1,RS2");
783 else if (format
& M68XG_OP_REL9
)
786 sprintf (p
, "%d", rand () & 0x1FF);
788 strcpy (p
, "<rel9>");
791 else if (format
& M68XG_OP_REL10
)
794 sprintf (p
, "%d", rand () & 0x3FF);
796 strcpy (p
, "<rel10>");
799 else if (format
& M68XG_OP_R_R_OFFS5
)
802 sprintf (p
, "R%d, (R%d, #0x%x)", rand () & 0x07, rand () & 0x07, rand () & 0x1f);
804 strcpy (p
, _("RD, (RI,#offs5)"));
807 else if (format
& M68XG_OP_RD_RB_RI
)
810 sprintf (p
, "R%d, (R%d, R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
812 strcpy (p
, "RD, (RB, RI)");
815 else if (format
& M68XG_OP_RD_RB_RIp
)
818 sprintf (p
, "R%d, (R%d, R%d+)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
820 strcpy (p
, "RD, (RB, RI+)");
823 else if (format
& M68XG_OP_RD_RB_mRI
)
826 sprintf (p
, "R%d, (R%d, -R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07);
828 strcpy (p
, "RD, (RB, -RI)");
831 else if (format
& M68XG_OP_R_IMM8
)
834 sprintf (p
, "R%d, #0x%x", rand () & 0x07, rand () & 0xff);
836 strcpy (p
, "RD, #imm8");
839 else if (format
& M68XG_OP_R_IMM16
)
842 sprintf (p
, "R%d, #0x%x", rand () & 0x07, rand () & 0xffff);
844 strcpy (p
, "RD, #imm16");
851 if (format
& M6811_OP_IMM8
)
854 sprintf (p
, "#%d", rand () & 0x0FF);
856 strcpy (p
, _("#<imm8>"));
860 if (format
& M6811_OP_IMM16
)
863 sprintf (p
, "#%d", rand () & 0x0FFFF);
865 strcpy (p
, _("#<imm16>"));
869 if (format
& M6811_OP_IX
)
872 sprintf (p
, "%d,X", rand () & 0x0FF);
874 strcpy (p
, _("<imm8>,X"));
878 if (format
& M6811_OP_IY
)
881 sprintf (p
, "%d,X", rand () & 0x0FF);
883 strcpy (p
, _("<imm8>,X"));
887 if (format
& M6812_OP_IDX
)
890 sprintf (p
, "%d,X", rand () & 0x0FF);
896 if (format
& M6812_OP_PAGE
)
899 sprintf (p
, ", %d", rand () & 0x0FF);
901 strcpy (p
, ", <page>");
905 if (format
& M6811_OP_DIRECT
)
908 sprintf (p
, "*Z%d", rand () & 0x0FF);
910 strcpy (p
, _("*<abs8>"));
914 if (format
& M6811_OP_BITMASK
)
920 sprintf (p
, "#$%02x", rand () & 0x0FF);
922 strcpy (p
, _("#<mask>"));
925 if (format
& M6811_OP_JUMP_REL
)
929 if (format
& M6811_OP_IND16
)
932 sprintf (p
, _("symbol%d"), rand () & 0x0FF);
934 strcpy (p
, _("<abs>"));
939 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
943 if (format
& M6811_OP_BITMASK
)
945 sprintf (p
, ".+%d", rand () & 0x7F);
949 sprintf (p
, "L%d", rand () & 0x0FF);
953 strcpy (p
, _("<label>"));
959 /* Prints the list of instructions with the possible operands. */
961 print_opcode_list (void)
964 const char *prev_name
= "";
965 struct m68hc11_opcode
*opcodes
;
966 int example
= flag_print_opcodes
== 2;
969 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"),
972 opcodes
= m68hc11_sorted_opcodes
;
974 /* Walk the list sorted on names (by md_begin). We only report
975 one instruction per line, and we collect the different operand
977 for (i
= 0; i
< num_opcodes
; i
++, opcodes
++)
979 char *fmt
= print_opcode_format (opcodes
, example
);
983 printf ("L%d:\t", i
);
984 printf ("%s %s\n", opcodes
->name
, fmt
);
988 if (strcmp (prev_name
, opcodes
->name
))
993 printf ("%-5.5s ", opcodes
->name
);
994 prev_name
= (char *) opcodes
->name
;
997 printf (" [%s]", fmt
);
1003 /* Print the instruction format. This operation is called when some
1004 instruction is not correct. Instruction format is printed as an
1007 print_insn_format (char *name
)
1009 struct m68hc11_opcode_def
*opc
;
1010 struct m68hc11_opcode
*opcode
;
1013 opc
= (struct m68hc11_opcode_def
*) str_hash_find (m68hc11_hash
, name
);
1016 as_bad (_("Instruction `%s' is not recognized."), name
);
1019 opcode
= opc
->opcode
;
1021 as_bad (_("Instruction formats for `%s':"), name
);
1026 fmt
= print_opcode_format (opcode
, 0);
1027 sprintf (buf
, "\t%-5.5s %s", opcode
->name
, fmt
);
1032 while (strcmp (opcode
->name
, name
) == 0);
1035 /* Analysis of 68HC11 and 68HC12 operands. */
1037 /* reg_name_search() finds the register number given its name.
1038 Returns the register number or REG_NONE on failure. */
1040 reg_name_search (char *name
)
1042 if (strcasecmp (name
, "x") == 0 || strcasecmp (name
, "ix") == 0)
1044 if (strcasecmp (name
, "y") == 0 || strcasecmp (name
, "iy") == 0)
1046 if (strcasecmp (name
, "a") == 0)
1048 if (strcasecmp (name
, "b") == 0)
1050 if (strcasecmp (name
, "d") == 0)
1052 if (strcasecmp (name
, "sp") == 0)
1054 if (strcasecmp (name
, "pc") == 0)
1056 if (strcasecmp (name
, "ccr") == 0)
1059 if (strcasecmp (name
, "r0") == 0)
1061 if (strcasecmp (name
, "r1") == 0)
1063 if (strcasecmp (name
, "r2") == 0)
1065 if (strcasecmp (name
, "r3") == 0)
1067 if (strcasecmp (name
, "r4") == 0)
1069 if (strcasecmp (name
, "r5") == 0)
1071 if (strcasecmp (name
, "r6") == 0)
1073 if (strcasecmp (name
, "r7") == 0)
1075 if (strcasecmp (name
, "sp") == 0)
1077 if (strcasecmp (name
, "pc") == 0)
1079 if (strcasecmp (name
, "ccr") == 0)
1085 skip_whites (char *p
)
1087 while (*p
== ' ' || *p
== '\t')
1093 /* Check the string at input_line_pointer
1094 to see if it is a valid register name. */
1096 register_name (void)
1098 register_id reg_number
;
1099 char c
, *p
= input_line_pointer
;
1101 if (!is_name_beginner (*p
++))
1104 while (is_part_of_name (*p
++))
1111 /* Look to see if it's in the register table. */
1112 reg_number
= reg_name_search (input_line_pointer
);
1113 if (reg_number
!= REG_NONE
)
1118 input_line_pointer
= p
;
1126 #define M6811_OP_CALL_ADDR 0x00800000
1127 #define M6811_OP_PAGE_ADDR 0x04000000
1129 /* Parse a string of operands and return an array of expressions.
1131 Operand mode[0] mode[1] exp[0] exp[1]
1132 #n M6811_OP_IMM16 - O_*
1133 *<exp> M6811_OP_DIRECT - O_*
1134 .{+-}<exp> M6811_OP_JUMP_REL - O_*
1135 <exp> M6811_OP_IND16 - O_*
1136 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register
1137 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register
1138 n,+r M6812_PRE_INC " "
1139 n,r- M6812_POST_DEC " "
1140 n,r+ M6812_POST_INC " "
1141 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register
1142 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register
1143 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */
1145 get_operand (operand
*oper
, int which
, long opmode
)
1147 char *p
= input_line_pointer
;
1151 oper
->exp
.X_op
= O_absent
;
1152 oper
->reg1
= REG_NONE
;
1153 oper
->reg2
= REG_NONE
;
1154 mode
= M6811_OP_NONE
;
1156 p
= skip_whites (p
);
1158 if (*p
== 0 || *p
== '\n' || *p
== '\r')
1160 input_line_pointer
= p
;
1164 if (*p
== '*' && (opmode
& (M6811_OP_DIRECT
| M6811_OP_IND16
)))
1166 mode
= M6811_OP_DIRECT
;
1171 if (!(opmode
& (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
)))
1173 as_bad (_("Immediate operand is not allowed for operand %d."),
1178 mode
= M6811_OP_IMM16
;
1180 if (strncmp (p
, "%hi", 3) == 0)
1183 mode
|= M6811_OP_HIGH_ADDR
;
1185 else if (strncmp (p
, "%lo", 3) == 0)
1188 mode
|= M6811_OP_LOW_ADDR
;
1190 /* %page modifier is used to obtain only the page number
1191 of the address of a function. */
1192 else if (strncmp (p
, "%page", 5) == 0)
1195 mode
|= M6811_OP_PAGE_ADDR
;
1198 /* %addr modifier is used to obtain the physical address part
1199 of the function (16-bit). For 68HC12 the function will be
1200 mapped in the 16K window at 0x8000 and the value will be
1201 within that window (although the function address may not fit
1202 in 16-bit). See bfd/elf32-m68hc12.c for the translation. */
1203 else if (strncmp (p
, "%addr", 5) == 0)
1206 mode
|= M6811_OP_CALL_ADDR
;
1209 else if (*p
== '.' && (p
[1] == '+' || p
[1] == '-'))
1212 mode
= M6811_OP_JUMP_REL
;
1216 if (current_architecture
& cpu6811
)
1217 as_bad (_("Indirect indexed addressing is not valid for 68HC11."));
1220 mode
= M6812_OP_D_IDX
;
1221 p
= skip_whites (p
);
1223 else if (*p
== ',') /* Special handling of ,x and ,y. */
1226 input_line_pointer
= p
;
1228 reg
= register_name ();
1229 if (reg
!= REG_NONE
)
1232 oper
->exp
.X_op
= O_constant
;
1233 oper
->exp
.X_add_number
= 0;
1234 oper
->mode
= M6812_OP_IDX
;
1237 as_bad (_("Spurious `,' or bad indirect register addressing mode."));
1240 /* Handle 68HC12 page specification in 'call foo,%page(bar)'. */
1241 else if ((opmode
& M6812_OP_PAGE
) && strncmp (p
, "%page", 5) == 0)
1244 mode
= M6811_OP_PAGE_ADDR
| M6812_OP_PAGE
| M6811_OP_IND16
;
1246 input_line_pointer
= p
;
1248 if (mode
== M6811_OP_NONE
|| mode
== M6812_OP_D_IDX
)
1249 reg
= register_name ();
1253 if (reg
!= REG_NONE
)
1255 p
= skip_whites (input_line_pointer
);
1256 if (*p
== ']' && mode
== M6812_OP_D_IDX
)
1259 (_("Missing second register or offset for indexed-indirect mode."));
1264 oper
->mode
= mode
| M6812_OP_REG
;
1267 if (mode
== M6812_OP_D_IDX
)
1269 as_bad (_("Missing second register for indexed-indirect mode."));
1276 input_line_pointer
= p
;
1277 reg
= register_name ();
1278 if (reg
!= REG_NONE
)
1280 p
= skip_whites (input_line_pointer
);
1281 if (mode
== M6812_OP_D_IDX
)
1285 as_bad (_("Missing `]' to close indexed-indirect mode."));
1289 oper
->mode
= M6812_OP_D_IDX
;
1291 input_line_pointer
= p
;
1299 /* In MRI mode, isolate the operand because we can't distinguish
1300 operands from comments. */
1305 p
= skip_whites (p
);
1306 while (*p
&& *p
!= ' ' && *p
!= '\t')
1315 /* Parse as an expression. */
1316 expression (&oper
->exp
);
1325 expression (&oper
->exp
);
1328 if (oper
->exp
.X_op
== O_illegal
)
1330 as_bad (_("Illegal operand."));
1333 else if (oper
->exp
.X_op
== O_absent
)
1335 as_bad (_("Missing operand."));
1339 p
= input_line_pointer
;
1341 if (mode
== M6811_OP_NONE
|| mode
== M6811_OP_DIRECT
1342 || mode
== M6812_OP_D_IDX
)
1344 p
= skip_whites (input_line_pointer
);
1348 int possible_mode
= M6811_OP_NONE
;
1349 char *old_input_line
;
1354 /* 68HC12 pre increment or decrement. */
1355 if (mode
== M6811_OP_NONE
)
1359 possible_mode
= M6812_PRE_DEC
;
1364 possible_mode
= M6812_PRE_INC
;
1367 p
= skip_whites (p
);
1369 input_line_pointer
= p
;
1370 reg
= register_name ();
1372 /* Backtrack if we have a valid constant expression and
1373 it does not correspond to the offset of the 68HC12 indexed
1374 addressing mode (as in N,x). */
1375 if (reg
== REG_NONE
&& mode
== M6811_OP_NONE
1376 && possible_mode
!= M6811_OP_NONE
)
1378 oper
->mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1379 input_line_pointer
= skip_whites (old_input_line
);
1383 if (possible_mode
!= M6811_OP_NONE
)
1384 mode
= possible_mode
;
1386 if ((current_architecture
& cpu6811
)
1387 && possible_mode
!= M6811_OP_NONE
)
1388 as_bad (_("Pre-increment mode is not valid for 68HC11"));
1390 if (which
== 0 && opmode
& M6812_OP_IDX_P2
1391 && reg
!= REG_X
&& reg
!= REG_Y
1392 && reg
!= REG_PC
&& reg
!= REG_SP
)
1395 input_line_pointer
= p
;
1398 if (reg
== REG_NONE
&& mode
!= M6811_OP_DIRECT
1399 && !(mode
== M6811_OP_NONE
&& opmode
& M6811_OP_IND16
))
1401 as_bad (_("Wrong register in register indirect mode."));
1404 if (mode
== M6812_OP_D_IDX
)
1406 p
= skip_whites (input_line_pointer
);
1409 as_bad (_("Missing `]' to close register indirect operand."));
1412 input_line_pointer
= p
;
1414 oper
->mode
= M6812_OP_D_IDX_2
;
1417 if (reg
!= REG_NONE
)
1420 if (mode
== M6811_OP_NONE
)
1422 p
= input_line_pointer
;
1425 mode
= M6812_POST_DEC
;
1427 if (current_architecture
& cpu6811
)
1429 (_("Post-decrement mode is not valid for 68HC11."));
1433 mode
= M6812_POST_INC
;
1435 if (current_architecture
& cpu6811
)
1437 (_("Post-increment mode is not valid for 68HC11."));
1440 mode
= M6812_OP_IDX
;
1442 input_line_pointer
= p
;
1445 mode
|= M6812_OP_IDX
;
1450 input_line_pointer
= old_input_line
;
1453 if (mode
== M6812_OP_D_IDX_2
)
1455 as_bad (_("Invalid indexed indirect mode."));
1460 /* If the mode is not known until now, this is either a label
1461 or an indirect address. */
1462 if (mode
== M6811_OP_NONE
)
1463 mode
= M6811_OP_IND16
| M6811_OP_JUMP_REL
;
1465 p
= input_line_pointer
;
1466 while (*p
== ' ' || *p
== '\t')
1468 input_line_pointer
= p
;
1474 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \
1475 | M6812_POST_INC | M6812_POST_DEC)
1477 /* Checks that the number 'num' fits for a given mode. */
1479 check_range (long num
, int mode
)
1481 if (current_architecture
== cpuxgate
)
1486 return (num
>= 0 && num
<= 7) ? 1 : 0;
1488 case M68XG_OP_R_IMM4
:
1489 return (num
>= 0 && num
<= 15) ? 1 : 0;
1491 case M68XG_OP_R_R_OFFS5
:
1492 return (num
>= 0 && num
<= 31) ? 1 : 0;
1494 case M68XG_OP_R_IMM8
:
1495 return (num
>= 0 && num
<= 255) ? 1 : 0;
1497 case M68XG_OP_R_IMM16
:
1498 return (num
>= 0 && num
<= 65535) ? 1 : 0;
1500 case M68XG_OP_B_MARKER
:
1501 return (num
>= -512 && num
<= 511) ? 1 : 0;
1503 case M68XG_OP_BRA_MARKER
:
1504 return (num
>= -1024 && num
<= 1023) ? 1 : 0;
1512 /* Auto increment and decrement are ok for [-8..8] without 0. */
1513 if (mode
& M6812_AUTO_INC_DEC
)
1514 return (num
!= 0 && num
<= 8 && num
>= -8);
1516 /* The 68HC12 supports 5, 9 and 16-bit offsets. */
1517 if (mode
& (M6812_INDEXED_IND
| M6812_INDEXED
| M6812_OP_IDX
))
1518 mode
= M6811_OP_IND16
;
1520 if (mode
& M6812_OP_JUMP_REL16
)
1521 mode
= M6811_OP_IND16
;
1523 mode
&= ~M6811_OP_BRANCH
;
1528 case M6811_OP_DIRECT
:
1529 return (num
>= 0 && num
<= 255) ? 1 : 0;
1531 case M6811_OP_BITMASK
:
1534 return (((num
& 0xFFFFFF00) == 0) || ((num
& 0xFFFFFF00) == 0xFFFFFF00))
1537 case M6811_OP_JUMP_REL
:
1538 return (num
>= -128 && num
<= 127) ? 1 : 0;
1540 case M6811_OP_IND16
:
1541 case M6811_OP_IND16
| M6812_OP_PAGE
:
1542 case M6811_OP_IMM16
:
1543 return (((num
& 0xFFFF0000) == 0) || ((num
& 0xFFFF0000) == 0xFFFF0000))
1546 case M6812_OP_IBCC_MARKER
:
1547 case M6812_OP_TBCC_MARKER
:
1548 case M6812_OP_DBCC_MARKER
:
1549 return (num
>= -256 && num
<= 255) ? 1 : 0;
1551 case M6812_OP_TRAP_ID
:
1552 return ((num
>= 0x30 && num
<= 0x39)
1553 || (num
>= 0x40 && num
<= 0x0ff)) ? 1 : 0;
1561 /* Gas fixup generation. */
1563 /* Put a 1 byte expression described by 'oper'. If this expression contains
1564 unresolved symbols, generate an 8-bit fixup. */
1566 fixup8 (expressionS
*oper
, int mode
, int opmode
)
1572 if (oper
->X_op
== O_constant
)
1574 if (mode
& M6812_OP_TRAP_ID
1575 && !check_range (oper
->X_add_number
, M6812_OP_TRAP_ID
))
1577 static char trap_id_warn_once
= 0;
1579 as_bad (_("Trap id `%ld' is out of range."), oper
->X_add_number
);
1580 if (trap_id_warn_once
== 0)
1582 trap_id_warn_once
= 1;
1583 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff]."));
1587 if (!(mode
& M6812_OP_TRAP_ID
)
1588 && !check_range (oper
->X_add_number
, mode
))
1590 as_bad (_("Operand out of 8-bit range: `%ld'."), oper
->X_add_number
);
1592 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1594 else if (oper
->X_op
!= O_register
)
1596 if (mode
& M6812_OP_TRAP_ID
)
1597 as_bad (_("The trap id must be a constant."));
1599 if (mode
== M6811_OP_JUMP_REL
)
1601 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1602 oper
, TRUE
, BFD_RELOC_8_PCREL
);
1607 bfd_reloc_code_real_type reloc
;
1609 /* Now create an 8-bit fixup. If there was some %hi, %lo
1610 or %page modifier, generate the reloc accordingly. */
1611 if (opmode
& M6811_OP_HIGH_ADDR
)
1612 reloc
= BFD_RELOC_M68HC11_HI8
;
1613 else if (opmode
& M6811_OP_LOW_ADDR
)
1614 reloc
= BFD_RELOC_M68HC11_LO8
;
1615 else if (opmode
& M6811_OP_PAGE_ADDR
)
1616 reloc
= BFD_RELOC_M68HC11_PAGE
;
1618 reloc
= BFD_RELOC_8
;
1620 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1621 oper
, FALSE
, reloc
);
1622 if (reloc
!= BFD_RELOC_8
)
1623 fixp
->fx_no_overflow
= 1;
1625 number_to_chars_bigendian (f
, 0, 1);
1629 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1633 /* Put a 2 byte expression described by 'oper'. If this expression contains
1634 unresolved symbols, generate a 16-bit fixup. */
1636 fixup16 (expressionS
*oper
, int mode
, int opmode ATTRIBUTE_UNUSED
)
1642 if (oper
->X_op
== O_constant
)
1644 if (!check_range (oper
->X_add_number
, mode
))
1646 as_bad (_("Operand out of 16-bit range: `%ld'."),
1647 oper
->X_add_number
);
1649 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFF, 2);
1651 else if (oper
->X_op
!= O_register
)
1654 bfd_reloc_code_real_type reloc
;
1656 if ((opmode
& M6811_OP_CALL_ADDR
) && (mode
& M6811_OP_IMM16
))
1657 reloc
= BFD_RELOC_M68HC11_LO16
;
1658 else if (mode
& M6812_OP_JUMP_REL16
)
1659 reloc
= BFD_RELOC_16_PCREL
;
1660 else if (mode
& M6812_OP_PAGE
)
1661 reloc
= BFD_RELOC_M68HC11_LO16
;
1663 reloc
= BFD_RELOC_16
;
1665 /* Now create a 16-bit fixup. */
1666 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 2,
1668 reloc
== BFD_RELOC_16_PCREL
,
1670 number_to_chars_bigendian (f
, 0, 2);
1672 if (reloc
== BFD_RELOC_M68HC11_LO16
)
1673 fixp
->fx_no_overflow
= 1;
1677 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1681 /* Put a 3 byte expression described by 'oper'. If this expression contains
1682 unresolved symbols, generate a 24-bit fixup. */
1684 fixup24 (expressionS
*oper
, int mode
, int opmode ATTRIBUTE_UNUSED
)
1690 if (oper
->X_op
== O_constant
)
1692 if (!check_range (oper
->X_add_number
, mode
))
1694 as_bad (_("Operand out of 16-bit range: `%ld'."),
1695 oper
->X_add_number
);
1697 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FFFFFF, 3);
1699 else if (oper
->X_op
!= O_register
)
1701 /* Now create a 24-bit fixup. */
1702 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 3,
1703 oper
, FALSE
, BFD_RELOC_M68HC11_24
);
1704 number_to_chars_bigendian (f
, 0, 3);
1708 as_fatal (_("Operand `%x' not recognized in fixup16."), oper
->X_op
);
1712 /* XGATE Put a 1 byte expression described by 'oper'. If this expression
1713 contains unresolved symbols, generate an 8-bit fixup. */
1715 fixup8_xg (expressionS
*oper
, int mode
, int opmode
)
1721 if (oper
->X_op
== O_constant
)
1724 bfd_reloc_code_real_type reloc
;
1726 if ((opmode
& M6811_OP_HIGH_ADDR
) || (opmode
& M6811_OP_LOW_ADDR
))
1728 if (opmode
& M6811_OP_HIGH_ADDR
)
1729 reloc
= BFD_RELOC_M68HC11_HI8
;
1731 reloc
= BFD_RELOC_M68HC11_LO8
;
1733 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1734 oper
, FALSE
, reloc
);
1735 fixp
->fx_no_overflow
= 1;
1736 number_to_chars_bigendian (f
, 0, 1);
1740 if (!(check_range (oper
->X_add_number
, mode
)))
1741 as_bad (_("Operand out of 8-bit range: `%ld'."),
1742 oper
->X_add_number
);
1743 number_to_chars_bigendian (f
, oper
->X_add_number
& 0x0FF, 1);
1746 else if (oper
->X_op
!= O_register
)
1748 if (mode
== M68XG_OP_REL9
)
1750 /* Future improvement:
1751 This fixup/reloc isn't adding on constants to symbols. */
1752 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
-1, 2,
1753 oper
, TRUE
, BFD_RELOC_M68HC12_9_PCREL
);
1755 else if (mode
== M68XG_OP_REL10
)
1757 /* Future improvement:
1758 This fixup/reloc isn't adding on constants to symbols. */
1759 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
-1, 2,
1760 oper
, TRUE
, BFD_RELOC_M68HC12_10_PCREL
);
1765 bfd_reloc_code_real_type reloc
;
1767 /* Now create an 8-bit fixup. If there was some %hi, %lo
1768 modifier, generate the reloc accordingly. */
1769 if (opmode
& M6811_OP_HIGH_ADDR
)
1770 reloc
= BFD_RELOC_M68HC11_HI8
;
1771 else if (opmode
& M6811_OP_LOW_ADDR
)
1772 reloc
= BFD_RELOC_M68HC11_LO8
;
1774 reloc
= BFD_RELOC_8
;
1776 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
1777 oper
, FALSE
, reloc
);
1778 if (reloc
!= BFD_RELOC_8
)
1779 fixp
->fx_no_overflow
= 1;
1781 number_to_chars_bigendian (f
, 0, 1);
1784 as_fatal (_("Operand `%x' not recognized in fixup8."), oper
->X_op
);
1787 /* 68HC11 and 68HC12 code generation. */
1789 /* Translate the short branch/bsr instruction into a long branch. */
1791 static unsigned char
1792 convert_branch (unsigned char code
)
1794 if (IS_OPCODE (code
, M6812_BSR
))
1796 else if (IS_OPCODE (code
, M6811_BSR
))
1798 else if (IS_OPCODE (code
, M6811_BRA
))
1799 return (current_architecture
& cpu6812
) ? M6812_JMP
: M6811_JMP
;
1801 as_fatal (_("Unexpected branch conversion with `%x'"), code
);
1803 /* Keep gcc happy. */
1807 /* Start a new insn that contains at least 'size' bytes. Record the
1808 line information of that insn in the dwarf2 debug sections. */
1810 m68hc11_new_insn (int size
)
1814 f
= frag_more (size
);
1816 dwarf2_emit_insn (size
);
1821 /* Builds a jump instruction (bra, bcc, bsr). */
1823 build_jump_insn (struct m68hc11_opcode
*opcode
, operand operands
[],
1824 int nb_operands
, int jmp_mode
)
1830 /* The relative branch conversion is not supported for
1832 gas_assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1833 gas_assert (nb_operands
== 1);
1834 gas_assert (operands
[0].reg1
== REG_NONE
&& operands
[0].reg2
== REG_NONE
);
1836 code
= opcode
->opcode
;
1838 n
= operands
[0].exp
.X_add_number
;
1840 /* Turn into a long branch:
1841 - when force long branch option (and not for jbcc pseudos),
1842 - when jbcc and the constant is out of -128..127 range,
1843 - when branch optimization is allowed and branch out of range. */
1844 if ((jmp_mode
== 0 && flag_force_long_jumps
)
1845 || (operands
[0].exp
.X_op
== O_constant
1846 && (!check_range (n
, opcode
->format
) &&
1847 (jmp_mode
== 1 || flag_fixed_branches
== 0))))
1849 fix_new (frag_now
, frag_now_fix (), 0,
1850 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1852 if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1854 code
= convert_branch (code
);
1856 f
= m68hc11_new_insn (1);
1857 number_to_chars_bigendian (f
, code
, 1);
1859 else if (current_architecture
& cpu6812
)
1861 /* 68HC12: translate the bcc into a lbcc. */
1862 f
= m68hc11_new_insn (2);
1863 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1864 number_to_chars_bigendian (f
+ 1, code
, 1);
1865 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
,
1866 M6812_OP_JUMP_REL16
);
1871 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */
1872 f
= m68hc11_new_insn (3);
1874 number_to_chars_bigendian (f
, code
, 1);
1875 number_to_chars_bigendian (f
+ 1, 3, 1);
1876 number_to_chars_bigendian (f
+ 2, M6811_JMP
, 1);
1878 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
1882 /* Branch with a constant that must fit in 8-bits. */
1883 if (operands
[0].exp
.X_op
== O_constant
)
1885 if (!check_range (n
, opcode
->format
))
1887 as_bad (_("Operand out of range for a relative branch: `%ld'"),
1890 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1892 f
= m68hc11_new_insn (4);
1893 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1894 number_to_chars_bigendian (f
+ 1, code
, 1);
1895 number_to_chars_bigendian (f
+ 2, n
& 0x0ffff, 2);
1899 f
= m68hc11_new_insn (2);
1900 number_to_chars_bigendian (f
, code
, 1);
1901 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
1904 else if (opcode
->format
& M6812_OP_JUMP_REL16
)
1906 fix_new (frag_now
, frag_now_fix (), 0,
1907 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1909 f
= m68hc11_new_insn (2);
1910 number_to_chars_bigendian (f
, M6811_OPCODE_PAGE2
, 1);
1911 number_to_chars_bigendian (f
+ 1, code
, 1);
1912 fixup16 (&operands
[0].exp
, M6812_OP_JUMP_REL16
, M6812_OP_JUMP_REL16
);
1918 fix_new (frag_now
, frag_now_fix (), 0,
1919 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
1921 /* Branch offset must fit in 8-bits, don't do some relax. */
1922 if (jmp_mode
== 0 && flag_fixed_branches
)
1924 op
= m68hc11_new_insn (1);
1925 number_to_chars_bigendian (op
, code
, 1);
1926 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
1929 /* bra/bsr made be changed into jmp/jsr. */
1930 else if (code
== M6811_BSR
|| code
== M6811_BRA
|| code
== M6812_BSR
)
1932 /* Allocate worst case storage. */
1933 op
= m68hc11_new_insn (3);
1934 number_to_chars_bigendian (op
, code
, 1);
1935 number_to_chars_bigendian (op
+ 1, 0, 1);
1936 frag_variant (rs_machine_dependent
, 1, 1,
1937 ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_UNDF
),
1938 operands
[0].exp
.X_add_symbol
, (offsetT
) n
,
1941 else if (current_architecture
& cpu6812
)
1943 op
= m68hc11_new_insn (2);
1944 number_to_chars_bigendian (op
, code
, 1);
1945 number_to_chars_bigendian (op
+ 1, 0, 1);
1946 frag_var (rs_machine_dependent
, 2, 2,
1947 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_UNDF
),
1948 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, op
);
1952 op
= m68hc11_new_insn (2);
1953 number_to_chars_bigendian (op
, code
, 1);
1954 number_to_chars_bigendian (op
+ 1, 0, 1);
1955 frag_var (rs_machine_dependent
, 3, 3,
1956 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_UNDF
),
1957 operands
[0].exp
.X_add_symbol
, (offsetT
) n
, op
);
1962 /* Builds a dbne/dbeq/tbne/tbeq instruction. */
1964 build_dbranch_insn (struct m68hc11_opcode
*opcode
, operand operands
[],
1965 int nb_operands
, int jmp_mode
)
1971 /* The relative branch conversion is not supported for
1973 gas_assert ((opcode
->format
& M6811_OP_BITMASK
) == 0);
1974 gas_assert (nb_operands
== 2);
1975 gas_assert (operands
[0].reg1
!= REG_NONE
);
1977 code
= opcode
->opcode
& 0x0FF;
1979 f
= m68hc11_new_insn (1);
1980 number_to_chars_bigendian (f
, code
, 1);
1982 n
= operands
[1].exp
.X_add_number
;
1983 code
= operands
[0].reg1
;
1985 if (operands
[0].reg1
== REG_NONE
|| operands
[0].reg1
== REG_CCR
1986 || operands
[0].reg1
== REG_PC
)
1987 as_bad (_("Invalid register for dbcc/tbcc instruction."));
1989 if (opcode
->format
& M6812_OP_IBCC_MARKER
)
1991 else if (opcode
->format
& M6812_OP_TBCC_MARKER
)
1994 if (!(opcode
->format
& M6812_OP_EQ_MARKER
))
1997 /* Turn into a long branch:
1998 - when force long branch option (and not for jbcc pseudos),
1999 - when jdbcc and the constant is out of -256..255 range,
2000 - when branch optimization is allowed and branch out of range. */
2001 if ((jmp_mode
== 0 && flag_force_long_jumps
)
2002 || (operands
[1].exp
.X_op
== O_constant
2003 && (!check_range (n
, M6812_OP_IBCC_MARKER
) &&
2004 (jmp_mode
== 1 || flag_fixed_branches
== 0))))
2008 number_to_chars_bigendian (f
, code
, 1);
2009 number_to_chars_bigendian (f
+ 1, M6812_JMP
, 1);
2010 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, M6811_OP_IND16
);
2014 /* Branch with a constant that must fit in 9-bits. */
2015 if (operands
[1].exp
.X_op
== O_constant
)
2017 if (!check_range (n
, M6812_OP_IBCC_MARKER
))
2019 as_bad (_("Operand out of range for a relative branch: `%ld'"),
2028 number_to_chars_bigendian (f
, code
, 1);
2029 number_to_chars_bigendian (f
+ 1, n
& 0x0FF, 1);
2034 /* Branch offset must fit in 8-bits, don't do some relax. */
2035 if (jmp_mode
== 0 && flag_fixed_branches
)
2037 fixup8 (&operands
[0].exp
, M6811_OP_JUMP_REL
, M6811_OP_JUMP_REL
);
2043 number_to_chars_bigendian (f
, code
, 1);
2044 number_to_chars_bigendian (f
+ 1, 0, 1);
2045 frag_var (rs_machine_dependent
, 3, 3,
2046 ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_UNDF
),
2047 operands
[1].exp
.X_add_symbol
, (offsetT
) n
, f
);
2052 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4)
2054 /* Assemble the post index byte for 68HC12 extended addressing modes. */
2057 build_indexed_byte (operand
*op
, int format ATTRIBUTE_UNUSED
, int move_insn
)
2059 unsigned char byte
= 0;
2064 val
= op
->exp
.X_add_number
;
2066 if (mode
& M6812_AUTO_INC_DEC
)
2069 if (mode
& (M6812_POST_INC
| M6812_POST_DEC
))
2072 if (op
->exp
.X_op
== O_constant
)
2074 if (!check_range (val
, mode
))
2075 as_bad (_("Increment/decrement value is out of range: `%ld'."),
2078 if (mode
& (M6812_POST_INC
| M6812_PRE_INC
))
2079 byte
|= (val
- 1) & 0x07;
2081 byte
|= (8 - ((val
) & 7)) | 0x8;
2087 as_fatal (_("Expecting a register."));
2102 as_bad (_("Invalid register for post/pre increment."));
2107 number_to_chars_bigendian (f
, byte
, 1);
2111 if (mode
& (M6812_OP_IDX
| M6812_OP_D_IDX_2
))
2132 as_bad (_("Invalid register."));
2136 if (op
->exp
.X_op
== O_constant
)
2138 if (!check_range (val
, M6812_OP_IDX
))
2139 as_bad (_("Offset out of 16-bit range: %ld."), val
);
2141 if (move_insn
&& !(val
>= -16 && val
<= 15)
2142 && ((!(mode
& M6812_OP_IDX
) && !(mode
& M6812_OP_D_IDX_2
))
2143 || !(current_architecture
& cpu9s12x
)))
2145 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."),
2150 if (val
>= -16 && val
<= 15 && !(mode
& M6812_OP_D_IDX_2
))
2155 number_to_chars_bigendian (f
, byte
, 1);
2158 else if (val
>= -256 && val
<= 255 && !(mode
& M6812_OP_D_IDX_2
))
2165 number_to_chars_bigendian (f
, byte
, 1);
2166 number_to_chars_bigendian (f
+ 1, val
& 0x0FF, 1);
2172 if (mode
& M6812_OP_D_IDX_2
)
2178 number_to_chars_bigendian (f
, byte
, 1);
2179 number_to_chars_bigendian (f
+ 1, val
& 0x0FFFF, 2);
2184 if (mode
& M6812_OP_D_IDX_2
)
2186 byte
= (byte
<< 3) | 0xe3;
2188 number_to_chars_bigendian (f
, byte
, 1);
2190 fixup16 (&op
->exp
, 0, 0);
2192 else if (op
->reg1
!= REG_PC
)
2198 number_to_chars_bigendian (f
, byte
, 1);
2199 sym
= op
->exp
.X_add_symbol
;
2200 off
= op
->exp
.X_add_number
;
2201 if (op
->exp
.X_op
!= O_symbol
)
2203 sym
= make_expr_symbol (&op
->exp
);
2207 /* movb/movw cannot be relaxed. */
2210 if ((mode
& M6812_OP_IDX
) && (current_architecture
& cpu9s12x
))
2212 /* Must treat as a 16bit relocate as size of final result is unknown. */
2216 number_to_chars_bigendian (f
, byte
, 1);
2218 fix_new (frag_now
, f
- frag_now
->fr_literal
, 2,
2219 sym
, off
, 0, BFD_RELOC_M68HC12_16B
);
2224 /* Non-S12X will fail at relocate stage if offset out of range. */
2226 number_to_chars_bigendian (f
, byte
, 1);
2227 fix_new (frag_now
, f
- frag_now
->fr_literal
, 1,
2228 sym
, off
, 0, BFD_RELOC_M68HC12_5B
);
2234 number_to_chars_bigendian (f
, byte
, 1);
2235 frag_var (rs_machine_dependent
, 2, 2,
2236 ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_UNDF
),
2244 /* movb/movw cannot be relaxed. */
2248 number_to_chars_bigendian (f
, byte
, 1);
2249 fix_new (frag_now
, f
- frag_now
->fr_literal
, 1,
2250 op
->exp
.X_add_symbol
, op
->exp
.X_add_number
, 0, BFD_RELOC_M68HC12_5B
);
2255 number_to_chars_bigendian (f
, byte
, 1);
2256 frag_var (rs_machine_dependent
, 2, 2,
2257 ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_UNDF
),
2258 op
->exp
.X_add_symbol
,
2259 op
->exp
.X_add_number
, f
);
2265 if (mode
& (M6812_OP_REG
| M6812_OP_D_IDX
))
2267 if (mode
& M6812_OP_D_IDX
)
2269 if (op
->reg1
!= REG_D
)
2270 as_bad (_("Expecting register D for indexed indirect mode."));
2271 if ((move_insn
) && (!(current_architecture
& cpu9s12x
)))
2272 as_bad (_("Indexed indirect mode is not allowed for movb/movw."));
2289 as_bad (_("Invalid accumulator register."));
2315 as_bad (_("Invalid indexed register."));
2319 number_to_chars_bigendian (f
, byte
, 1);
2323 fprintf (stderr
, "mode = 0x%x\nop->reg1 = 0x%x\nop->reg2 = 0x%x\n",
2324 mode
, op
->reg1
, op
->reg2
);
2325 as_fatal (_("Addressing mode not implemented yet."));
2329 /* Assemble the 68HC12 register mode byte. */
2331 build_reg_mode (operand
*op
, int format
)
2336 if ((format
& M6812_OP_SEX_MARKER
)
2337 && (op
->reg1
!= REG_A
) && (op
->reg1
!= REG_B
) && (op
->reg1
!= REG_CCR
)
2338 && (!(current_architecture
& cpu9s12x
)))
2339 as_bad (_("Invalid source register for this instruction, use 'tfr'."));
2340 else if (op
->reg1
== REG_NONE
|| op
->reg1
== REG_PC
)
2341 as_bad (_("Invalid source register."));
2343 if (format
& M6812_OP_SEX_MARKER
2344 && op
->reg2
!= REG_D
2345 && op
->reg2
!= REG_X
&& op
->reg2
!= REG_Y
&& op
->reg2
!= REG_SP
)
2346 as_bad (_("Invalid destination register for this instruction, use 'tfr'."));
2347 else if (op
->reg2
== REG_NONE
|| op
->reg2
== REG_PC
)
2348 as_bad (_("Invalid destination register."));
2350 byte
= (op
->reg1
<< 4) | (op
->reg2
);
2351 if (format
& M6812_OP_EXG_MARKER
)
2354 if ((format
& M6812_OP_SEX_MARKER
)
2355 && (op
->reg1
== REG_D
) && (current_architecture
& cpu9s12x
))
2359 number_to_chars_bigendian (f
, byte
, 1);
2363 /* build_insn_xg takes a pointer to the opcode entry in the opcode table,
2364 the array of operand expressions and builds the corresponding instruction. */
2367 build_insn_xg (struct m68hc11_opcode
*opcode
,
2369 int nb_operands ATTRIBUTE_UNUSED
)
2374 /* Put the page code instruction if there is one. */
2375 format
= opcode
->format
;
2377 if (!(operands
[0].mode
& (M6811_OP_LOW_ADDR
| M6811_OP_HIGH_ADDR
)))
2378 /* Need to retain those two modes, but clear for others. */
2379 operands
[0].mode
= 0;
2381 if (format
& M68XG_OP_R_IMM8
)
2383 /* These opcodes are byte followed by imm8. */
2384 f
= m68hc11_new_insn (1);
2385 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1);
2386 fixup8_xg (&operands
[0].exp
, format
, operands
[0].mode
);
2388 else if (format
& M68XG_OP_R_IMM16
)
2391 /* These opcodes expand into two imm8 instructions.
2392 Emit as low:high as per the Freescale datasheet.
2393 The linker requires them to be adjacent to handle the upper byte. */
2395 /* Build low byte. */
2396 f
= m68hc11_new_insn (1);
2397 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1);
2398 operands
[0].mode
= M6811_OP_LOW_ADDR
;
2400 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
2401 &operands
[0].exp
, FALSE
, BFD_RELOC_M68HC12_LO8XG
);
2402 fixp
->fx_no_overflow
= 1;
2403 number_to_chars_bigendian (f
, 0, 1);
2405 /* Build high byte. */
2406 f
= m68hc11_new_insn (1);
2407 number_to_chars_bigendian (f
, (opcode
->opcode
>> 8) | 0x08, 1);
2408 operands
[0].mode
= M6811_OP_HIGH_ADDR
;
2410 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 1,
2411 &operands
[0].exp
, FALSE
, BFD_RELOC_M68HC12_HI8XG
);
2412 fixp
->fx_no_overflow
= 1;
2413 number_to_chars_bigendian (f
, 0, 1);
2416 else if (format
& M68XG_OP_REL9
)
2418 f
= m68hc11_new_insn (1);
2419 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1); /* High byte. */
2420 fixup8_xg (&operands
[0].exp
, format
, M68XG_OP_REL9
);
2422 else if (format
& M68XG_OP_REL10
)
2424 f
= m68hc11_new_insn (1);
2425 number_to_chars_bigendian (f
, opcode
->opcode
>> 8, 1); /* High byte. */
2426 fixup8_xg (&operands
[0].exp
, format
, M68XG_OP_REL10
);
2430 f
= m68hc11_new_insn (2);
2431 number_to_chars_bigendian (f
, opcode
->opcode
, 2);
2436 /* build_insn takes a pointer to the opcode entry in the opcode table,
2437 the array of operand expressions and builds the corresponding instruction.
2438 This operation only deals with non relative jumps insn (need special
2442 build_insn (struct m68hc11_opcode
*opcode
,
2444 int nb_operands ATTRIBUTE_UNUSED
)
2451 /* Put the page code instruction if there is one. */
2452 format
= opcode
->format
;
2454 if (format
& M6811_OP_BRANCH
)
2455 fix_new (frag_now
, frag_now_fix (), 0,
2456 &abs_symbol
, 0, 1, BFD_RELOC_M68HC11_RL_JUMP
);
2458 if (format
& OP_EXTENDED
)
2462 f
= m68hc11_new_insn (2);
2463 if (format
& M6811_OP_PAGE2
)
2464 page_code
= M6811_OPCODE_PAGE2
;
2465 else if (format
& M6811_OP_PAGE3
)
2466 page_code
= M6811_OPCODE_PAGE3
;
2468 page_code
= M6811_OPCODE_PAGE4
;
2470 number_to_chars_bigendian (f
, page_code
, 1);
2474 f
= m68hc11_new_insn (1);
2476 number_to_chars_bigendian (f
, opcode
->opcode
, 1);
2480 /* The 68HC12 movb and movw instructions are special. We have to handle
2481 them in a special way. */
2482 if (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2485 if (format
& M6812_OP_IDX
)
2487 build_indexed_byte (&operands
[0], format
, 1);
2489 format
&= ~M6812_OP_IDX
;
2491 if (format
& M6812_OP_IDX_P2
)
2493 build_indexed_byte (&operands
[1], format
, 1);
2495 format
&= ~M6812_OP_IDX_P2
;
2499 if (format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
))
2501 fixup8 (&operands
[i
].exp
,
2502 format
& (M6811_OP_DIRECT
| M6811_OP_IMM8
| M6812_OP_TRAP_ID
),
2506 else if (IS_CALL_SYMBOL (format
) && nb_operands
== 1)
2508 format
&= ~M6812_OP_PAGE
;
2509 fixup24 (&operands
[i
].exp
, format
& M6811_OP_IND16
,
2513 else if (format
& (M6811_OP_IMM16
| M6811_OP_IND16
))
2515 fixup16 (&operands
[i
].exp
,
2516 format
& (M6811_OP_IMM16
| M6811_OP_IND16
| M6812_OP_PAGE
),
2520 else if (format
& (M6811_OP_IX
| M6811_OP_IY
))
2522 if ((format
& M6811_OP_IX
) && (operands
[0].reg1
!= REG_X
))
2523 as_bad (_("Invalid indexed register, expecting register X."));
2524 if ((format
& M6811_OP_IY
) && (operands
[0].reg1
!= REG_Y
))
2525 as_bad (_("Invalid indexed register, expecting register Y."));
2527 fixup8 (&operands
[0].exp
, M6811_OP_IX
, operands
[0].mode
);
2531 (M6812_OP_IDX
| M6812_OP_IDX_2
| M6812_OP_IDX_1
2532 | M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2534 build_indexed_byte (&operands
[i
], format
, move_insn
);
2537 else if (format
& M6812_OP_REG
&& current_architecture
& cpu6812
)
2539 build_reg_mode (&operands
[i
], format
);
2542 if (format
& M6811_OP_BITMASK
)
2544 fixup8 (&operands
[i
].exp
, M6811_OP_BITMASK
, operands
[i
].mode
);
2547 if (format
& M6811_OP_JUMP_REL
)
2549 fixup8 (&operands
[i
].exp
, M6811_OP_JUMP_REL
, operands
[i
].mode
);
2551 else if (format
& M6812_OP_IND16_P2
)
2553 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
2555 if (format
& M6812_OP_PAGE
)
2557 fixup8 (&operands
[i
].exp
, M6812_OP_PAGE
, operands
[i
].mode
);
2561 /* Opcode identification and operand analysis. */
2563 /* find() gets a pointer to an entry in the opcode table. It must look at all
2564 opcodes with the same name and use the operands to choose the correct
2565 opcode. Returns the opcode pointer if there was a match and 0 if none. */
2566 static struct m68hc11_opcode
*
2567 find (struct m68hc11_opcode_def
*opc
, operand operands
[], int nb_operands
)
2570 struct m68hc11_opcode
*opcode
;
2571 struct m68hc11_opcode
*op_indirect
;
2574 opcode
= opc
->opcode
;
2576 /* Now search the opcode table table for one with operands
2577 that matches what we've got. */
2579 if (current_architecture
& cpuxgate
)
2581 /* Many XGATE insns are simple enough that we get an exact match. */
2582 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2583 if (opcode
->format
== operands
[nb_operands
-1].mode
)
2591 /* Now search the opcode table table for one with operands
2592 that matches what we've got. We're only done if the operands matched so
2593 far AND there are no more to check. */
2594 for (pos
= match
= 0; match
== 0 && pos
< opc
->nb_modes
; pos
++, opcode
++)
2596 int poss_indirect
= 0;
2597 long format
= opcode
->format
;
2601 if (opcode
->format
& M6811_OP_MASK
)
2603 if (opcode
->format
& M6811_OP_BITMASK
)
2605 if (opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2607 if (opcode
->format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
))
2609 if ((opcode
->format
& M6812_OP_PAGE
)
2610 && (!IS_CALL_SYMBOL (opcode
->format
) || nb_operands
== 2))
2613 for (i
= 0; expect
== nb_operands
&& i
< nb_operands
; i
++)
2615 int mode
= operands
[i
].mode
;
2617 if (mode
& M6811_OP_IMM16
)
2620 (M6811_OP_IMM8
| M6811_OP_IMM16
| M6811_OP_BITMASK
))
2624 if (mode
== M6811_OP_DIRECT
)
2626 if (format
& M6811_OP_DIRECT
)
2629 /* If the operand is a page 0 operand, remember a
2630 possible <abs-16> addressing mode. We mark
2631 this and continue to check other operands. */
2632 if (format
& M6811_OP_IND16
2633 && flag_strict_direct_addressing
&& op_indirect
== 0)
2640 if (mode
& M6811_OP_IND16
)
2642 if (i
== 0 && (format
& M6811_OP_IND16
) != 0)
2644 if (i
!= 0 && (format
& M6812_OP_PAGE
) != 0)
2646 if (i
!= 0 && (format
& M6812_OP_IND16_P2
) != 0)
2648 if (i
== 0 && (format
& M6811_OP_BITMASK
))
2651 if (mode
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2653 if (format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
2656 if (mode
& M6812_OP_REG
)
2659 && (format
& M6812_OP_REG
)
2660 && (operands
[i
].reg2
== REG_NONE
))
2663 && (format
& M6812_OP_REG
)
2664 && (format
& M6812_OP_REG_2
)
2665 && (operands
[i
].reg2
!= REG_NONE
))
2668 && (format
& M6812_OP_IDX
)
2669 && (operands
[i
].reg2
!= REG_NONE
))
2672 && (format
& M6812_OP_IDX
)
2673 && (format
& (M6812_OP_IND16_P2
| M6812_OP_IDX_P2
)))
2676 && (format
& M6812_OP_IDX_P2
))
2680 if (mode
& M6812_OP_IDX
)
2682 if (format
& M6811_OP_IX
&& operands
[i
].reg1
== REG_X
)
2684 if (format
& M6811_OP_IY
&& operands
[i
].reg1
== REG_Y
)
2687 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
| M6812_OP_IDX_2
)
2688 && (operands
[i
].reg1
== REG_X
2689 || operands
[i
].reg1
== REG_Y
2690 || operands
[i
].reg1
== REG_SP
2691 || operands
[i
].reg1
== REG_PC
))
2693 if (i
== 1 && (format
& M6812_OP_IDX_P2
))
2696 if (mode
& format
& (M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
2701 if (mode
& M6812_AUTO_INC_DEC
)
2704 && format
& (M6812_OP_IDX
| M6812_OP_IDX_1
|
2707 if (i
== 1 && format
& M6812_OP_IDX_P2
)
2712 match
= i
== nb_operands
;
2714 /* Operands are ok but an operand uses page 0 addressing mode
2715 while the insn supports abs-16 mode. Keep a reference to this
2716 insns in case there is no insn supporting page 0 addressing. */
2717 if (match
&& poss_indirect
)
2719 op_indirect
= opcode
;
2726 /* Page 0 addressing is used but not supported by any insn.
2727 If absolute addresses are supported, we use that insn. */
2728 if (match
== 0 && op_indirect
)
2730 opcode
= op_indirect
;
2734 return match
? opcode
: 0;
2737 /* Find the real opcode and its associated operands. We use a progressive
2738 approach here. On entry, 'opc' points to the first opcode in the
2739 table that matches the opcode name in the source line. We try to
2740 isolate an operand, find a possible match in the opcode table.
2741 We isolate another operand if no match were found. The table 'operands'
2742 is filled while operands are recognized.
2744 Returns the opcode pointer that matches the opcode name in the
2745 source line and the associated operands. */
2746 static struct m68hc11_opcode
*
2747 find_opcode (struct m68hc11_opcode_def
*opc
, operand operands
[],
2750 struct m68hc11_opcode
*opcode
;
2753 if (opc
->max_operands
== 0)
2759 for (i
= 0; i
< opc
->max_operands
;)
2763 result
= get_operand (&operands
[i
], i
, opc
->format
);
2767 /* Special case where the bitmask of the bclr/brclr
2768 instructions is not introduced by #.
2769 Example: bclr 3,x $80. */
2770 if (i
== 1 && (opc
->format
& M6811_OP_BITMASK
)
2771 && (operands
[i
].mode
& M6811_OP_IND16
))
2773 operands
[i
].mode
= M6811_OP_IMM16
;
2778 if (i
>= opc
->min_operands
)
2780 opcode
= find (opc
, operands
, i
);
2782 /* Another special case for 'call foo,page' instructions.
2783 Since we support 'call foo' and 'call foo,page' we must look
2784 if the optional page specification is present otherwise we will
2785 assemble immediately and treat the page spec as garbage. */
2786 if (opcode
&& !(opcode
->format
& M6812_OP_PAGE
))
2789 if (opcode
&& *input_line_pointer
!= ',')
2793 if (*input_line_pointer
== ',')
2794 input_line_pointer
++;
2800 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \
2801 | M6812_OP_DBCC_MARKER \
2802 | M6812_OP_IBCC_MARKER)
2804 /* Gas line assembler entry point. */
2806 /* This is the main entry point for the machine-dependent assembler. str
2807 points to a machine-dependent instruction. This function is supposed to
2808 emit the frags/bytes it assembles to. */
2810 md_assemble (char *str
)
2812 struct m68hc11_opcode_def
*opc
;
2813 struct m68hc11_opcode
*opcode
;
2815 struct m68hc11_opcode opcode_local
;
2816 unsigned char *op_start
, *op_end
;
2820 operand operands
[M6811_MAX_OPERANDS
];
2821 int nb_operands
= 0;
2822 int branch_optimize
= 0;
2825 /* Drop leading whitespace. */
2829 /* Find the opcode end and get the opcode in 'name'. The opcode is forced
2830 lower case (the opcode table only has lower case op-codes). */
2831 for (op_start
= op_end
= (unsigned char *) str
;
2832 *op_end
&& !is_end_of_line
[*op_end
] && *op_end
!= ' ';
2835 name
[nlen
] = TOLOWER (op_start
[nlen
]);
2837 if (nlen
== sizeof (name
) - 1)
2844 as_bad (_("No instruction or missing opcode."));
2848 if (current_architecture
== cpuxgate
)
2850 /* Find the opcode definition given its name. */
2851 opc
= (struct m68hc11_opcode_def
*) str_hash_find (m68hc11_hash
, name
);
2854 as_bad (_("Opcode `%s' is not recognized."), name
);
2858 /* Grab a local copy. */
2859 opcode_local
.name
= opc
->opcode
->name
;
2860 /* These will be incomplete where multiple variants exist. */
2861 opcode_local
.opcode
= opc
->opcode
->opcode
;
2862 opcode_local
.format
= opc
->opcode
->format
;
2864 save
= input_line_pointer
;
2865 input_line_pointer
= (char *) op_end
;
2867 if (opc
->format
== M68XG_OP_NONE
)
2869 /* No special handling required. */
2870 opcode_local
.format
= M68XG_OP_NONE
;
2871 build_insn_xg (opc
->opcode
, operands
, 0);
2875 /* Special handling of TFR. */
2876 if (strncmp (opc
->opcode
->name
, "tfr",3) == 0)
2878 /* There must be two operands with a comma. */
2879 input_line_pointer
= skip_whites (input_line_pointer
);
2880 operands
[0].reg1
= register_name ();
2881 if (operands
[0].reg1
== REG_NONE
)
2883 as_bad ("Invalid register\n");
2886 input_line_pointer
= skip_whites (input_line_pointer
);
2887 if (*input_line_pointer
!= ',')
2889 as_bad ("Missing comma.\n");
2892 input_line_pointer
++;
2893 input_line_pointer
= skip_whites (input_line_pointer
);
2894 operands
[1].reg1
= register_name ();
2895 if (operands
[1].reg1
== REG_NONE
)
2897 as_bad ("Invalid register\n");
2900 input_line_pointer
= skip_whites (input_line_pointer
);
2901 if (*input_line_pointer
!= '\n' && *input_line_pointer
)
2903 as_bad (_("Garbage at end of instruction: `%s'."),
2904 input_line_pointer
);
2907 if (operands
[1].reg1
== REG_CCR
) /* ,CCR */
2908 opc
->opcode
->opcode
= 0x00f8 | ( operands
[0].reg1
<< 8);
2909 else if (operands
[0].reg1
== REG_CCR
) /* CCR, */
2910 opc
->opcode
->opcode
= 0x00f9 | ( operands
[1].reg1
<< 8);
2911 else if (operands
[1].reg1
== REG_PC
) /* ,PC */
2912 opc
->opcode
->opcode
= 0x00fa | ( operands
[0].reg1
<< 8);
2915 as_bad ("Invalid operand to TFR\n");
2918 /* no special handling required */
2919 opcode_local
.format
= M68XG_OP_NONE
;
2920 opcode_local
.opcode
= opc
->opcode
->opcode
;
2921 build_insn_xg (&opcode_local
, operands
, 0);
2926 if (opc
->format
& M68XG_OP_IMM3
)
2928 /* Either IMM3 or R */
2929 input_line_pointer
= skip_whites (input_line_pointer
);
2930 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
2932 operands
[0].reg1
= register_name ();
2933 if (operands
[0].reg1
== REG_NONE
)
2935 as_bad ("Invalid register\n");
2938 operands
[0].mode
= M68XG_OP_R
;
2939 /* One opcode has multiple modes, so find right one. */
2940 opcode
= find (opc
, operands
, 1);
2943 opcode_local
.opcode
= opcode
->opcode
2944 | (operands
[0].reg1
<< 8);
2945 opcode_local
.format
= M68XG_OP_NONE
;
2946 build_insn_xg (&opcode_local
, operands
, 1);
2949 as_bad ("No opcode found\n");
2955 if (*input_line_pointer
== '#')
2956 input_line_pointer
++;
2958 expression (&operands
[0].exp
);
2959 if (operands
[0].exp
.X_op
== O_illegal
)
2961 as_bad (_("Illegal operand."));
2964 else if (operands
[0].exp
.X_op
== O_absent
)
2966 as_bad (_("Missing operand."));
2970 if (check_range (operands
[0].exp
.X_add_number
,M68XG_OP_IMM3
))
2972 opcode_local
.opcode
|= (operands
[0].exp
.X_add_number
);
2973 operands
[0].mode
= M68XG_OP_IMM3
;
2975 opcode
= find (opc
, operands
, 1);
2978 opcode_local
.opcode
= opcode
->opcode
;
2980 |= (operands
[0].exp
.X_add_number
) << 8;
2981 opcode_local
.format
= M68XG_OP_NONE
;
2982 build_insn_xg (&opcode_local
, operands
, 1);
2985 as_bad ("No opcode found\n");
2991 as_bad ("Number out of range for IMM3\n");
2997 /* Special handling of SIF. */
2998 if (strncmp (opc
->opcode
->name
, "sif",3) == 0)
3000 /* Either OP_NONE or OP_RS. */
3001 if (*input_line_pointer
!= '\n')
3002 input_line_pointer
= skip_whites (input_line_pointer
);
3004 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3005 || (*input_line_pointer
== '\0'))
3006 opc
->opcode
->opcode
= 0x0300;
3009 operands
[0].reg1
= register_name ();
3010 if (operands
[0].reg1
== REG_NONE
)
3012 as_bad ("Invalid register\n");
3015 opcode_local
.opcode
= 0x00f7 | (operands
[0].reg1
<< 8);
3017 opcode_local
.format
= M68XG_OP_NONE
;
3018 build_insn_xg (&opcode_local
, operands
, 0);
3022 /* SEX, PAR, JAL plus aliases NEG, TST, COM */
3023 if (opc
->format
& M68XG_OP_R
)
3025 input_line_pointer
= skip_whites (input_line_pointer
);
3026 operands
[0].reg1
= register_name ();
3027 if (operands
[0].reg1
== REG_NONE
)
3029 as_bad ("Invalid register\n");
3032 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3033 || (*input_line_pointer
== '\0'))
3035 /* Likely to be OP R. */
3036 if (opc
->format
& M68XG_OP_R
)
3038 operands
[0].mode
= M68XG_OP_R
;
3040 opcode
= find (opc
, operands
, 1);
3043 if ((strncmp (opc
->opcode
->name
, "com",3) == 0)
3044 || (strncmp (opc
->opcode
->name
, "neg",3) == 0))
3045 /* Special case for com RD as alias for sub RD,R0,RS */
3046 /* Special case for neg RD as alias for sub RD,R0,RS */
3047 opcode_local
.opcode
= opcode
->opcode
3048 | (operands
[0].reg1
<< 8) | (operands
[0].reg1
<< 2);
3049 else if (strncmp (opc
->opcode
->name
, "tst",3) == 0)
3050 /* Special case for tst RS alias for sub R0, RS, R0 */
3051 opcode_local
.opcode
= opcode
->opcode
3052 | (operands
[0].reg1
<< 5);
3054 opcode_local
.opcode
|= (operands
[0].reg1
<< 8);
3056 opcode_local
.format
= M68XG_OP_NONE
;
3057 build_insn_xg (&opcode_local
, operands
, 0);
3060 as_bad ("No valid mode found\n");
3066 if (opc
->format
& (M68XG_OP_REL9
| M68XG_OP_REL10
))
3068 opcode_local
.format
= opc
->format
;
3069 input_line_pointer
= skip_whites (input_line_pointer
);
3070 expression (&operands
[0].exp
);
3071 if (operands
[0].exp
.X_op
== O_illegal
)
3073 as_bad (_("Illegal operand."));
3076 else if (operands
[0].exp
.X_op
== O_absent
)
3078 as_bad (_("Missing operand."));
3081 opcode_local
.opcode
= opc
->opcode
->opcode
;
3082 build_insn_xg (&opcode_local
, operands
, 1);
3087 /* For other command formats, parse input line and determine the mode
3088 we are using as we go. */
3090 input_line_pointer
= skip_whites (input_line_pointer
);
3091 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3092 || (*input_line_pointer
== '\0'))
3093 return; /* nothing left */
3095 if (*input_line_pointer
== '#')
3097 as_bad ("No register specified before hash\n");
3101 /* first operand is expected to be a register */
3102 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3104 operands
[0].reg1
= register_name ();
3105 if (operands
[0].reg1
== REG_NONE
)
3107 as_bad ("Invalid register\n");
3112 input_line_pointer
= skip_whites (input_line_pointer
);
3113 if (*input_line_pointer
!= ',')
3115 as_bad ("Missing operand\n");
3118 input_line_pointer
++;
3119 input_line_pointer
= skip_whites (input_line_pointer
);
3121 if (*input_line_pointer
== '#')
3123 /* Some kind of immediate mode, check if this is possible. */
3125 & (M68XG_OP_R_IMM8
| M68XG_OP_R_IMM16
| M68XG_OP_R_IMM4
)))
3126 as_bad ("Invalid immediate mode for `%s'", opc
->opcode
->name
);
3129 input_line_pointer
++;
3130 input_line_pointer
= skip_whites (input_line_pointer
);
3131 if (strncmp (input_line_pointer
, "%hi", 3) == 0)
3133 input_line_pointer
+= 3;
3134 operands
[0].mode
= M6811_OP_HIGH_ADDR
;
3136 else if (strncmp (input_line_pointer
, "%lo", 3) == 0)
3138 input_line_pointer
+= 3;
3139 operands
[0].mode
= M6811_OP_LOW_ADDR
;
3142 operands
[0].mode
= 0;
3144 expression (&operands
[0].exp
);
3145 if (operands
[0].exp
.X_op
== O_illegal
)
3147 as_bad (_("Illegal operand."));
3150 else if (operands
[0].exp
.X_op
== O_absent
)
3152 as_bad (_("Missing operand."));
3155 /* ok so far, can only be one mode */
3156 opcode_local
.format
= opc
->format
3157 & (M68XG_OP_R_IMM8
| M68XG_OP_R_IMM16
| M68XG_OP_R_IMM4
);
3158 if (opcode_local
.format
& M68XG_OP_R_IMM4
)
3160 operands
[0].mode
= M68XG_OP_R_IMM4
;
3161 /* same opcodes have multiple modes, so find right one */
3162 opcode
= find (opc
, operands
, 1);
3164 opcode_local
.opcode
= opcode
->opcode
3165 | (operands
[0].reg1
<< 8);
3167 if (operands
[0].exp
.X_op
!= O_constant
)
3168 as_bad ("Only constants supported at for IMM4 mode\n");
3172 (operands
[0].exp
.X_add_number
,M68XG_OP_R_IMM4
))
3174 |= (operands
[0].exp
.X_add_number
<< 4);
3176 as_bad ("Number out of range for IMM4\n");
3178 opcode_local
.format
= M68XG_OP_NONE
;
3180 else if (opcode_local
.format
& M68XG_OP_R_IMM16
)
3182 operands
[0].mode
= M68XG_OP_R_IMM16
;
3184 opcode
= find (opc
, operands
, 1);
3187 opcode_local
.opcode
= opcode
->opcode
3188 | (operands
[0].reg1
<< 8);
3193 opcode_local
.opcode
= opc
->opcode
->opcode
3194 | (operands
[0].reg1
<< 8);
3196 build_insn_xg (&opcode_local
, operands
, 1);
3199 else if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3201 /* we've got as far as OP R, R */
3202 operands
[1].reg1
= register_name ();
3203 if (operands
[1].reg1
== REG_NONE
)
3205 as_bad ("Invalid register\n");
3208 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3209 || (*input_line_pointer
== '\0'))
3211 /* looks like OP_R_R */
3212 if (opc
->format
& M68XG_OP_R_R
)
3214 operands
[0].mode
= M68XG_OP_R_R
;
3215 /* same opcodes have multiple modes, so find right one */
3216 opcode
= find (opc
, operands
, 1);
3219 if ((strncmp (opc
->opcode
->name
, "com",3) == 0)
3220 || (strncmp (opc
->opcode
->name
, "mov",3) == 0)
3221 || (strncmp (opc
->opcode
->name
, "neg",3) == 0))
3223 /* Special cases for:
3224 com RD, RS alias for xnor RD,R0,RS
3225 mov RD, RS alias for or RD, R0, RS
3226 neg RD, RS alias for sub RD, R0, RS */
3227 opcode_local
.opcode
= opcode
->opcode
3228 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 2);
3230 else if ((strncmp (opc
->opcode
->name
, "cmp",3) == 0)
3231 || (strncmp (opc
->opcode
->name
, "cpc",3) == 0))
3233 /* special cases for:
3234 cmp RS1, RS2 alias for sub R0, RS1, RS2
3235 cpc RS1, RS2 alias for sbc R0, RS1, RS2 */
3236 opcode_local
.opcode
= opcode
->opcode
3237 | (operands
[0].reg1
<< 5) | (operands
[1].reg1
<< 2);
3241 opcode_local
.opcode
= opcode
->opcode
3242 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5);
3244 opcode_local
.format
= M68XG_OP_NONE
;
3245 build_insn_xg (&opcode_local
, operands
, 1);
3250 as_bad ("No valid mode found\n");
3256 if (*input_line_pointer
!= ',')
3258 as_bad (_("Missing operand."));
3261 input_line_pointer
++;
3262 input_line_pointer
= skip_whites (input_line_pointer
);
3263 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3265 operands
[2].reg1
= register_name ();
3266 if (operands
[2].reg1
== REG_NONE
)
3268 as_bad ("Invalid register\n");
3271 if (opc
->format
& M68XG_OP_R_R_R
)
3273 operands
[0].mode
= M68XG_OP_R_R_R
;
3275 opcode
= find (opc
, operands
, 1);
3278 opcode_local
.opcode
= opcode
->opcode
3279 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5)
3280 | (operands
[2].reg1
<< 2);
3281 opcode_local
.format
= M68XG_OP_NONE
;
3282 build_insn_xg (&opcode_local
, operands
, 1);
3287 as_bad ("No valid mode found\n");
3292 else if (*input_line_pointer
== '(') /* Indexed modes */
3294 input_line_pointer
++;
3295 input_line_pointer
= skip_whites (input_line_pointer
);
3296 if ((*input_line_pointer
== 'R') || (*input_line_pointer
== 'r'))
3298 /* we've got as far as OP R, (R */
3299 operands
[1].reg1
= register_name ();
3300 if (operands
[1].reg1
== REG_NONE
)
3302 as_bad ("Invalid register\n");
3306 if ((*input_line_pointer
== '\n') || (*input_line_pointer
== '\r')
3307 || (*input_line_pointer
== '\0'))
3309 /* Looks like OP_R_R. */
3310 as_bad (_("Missing operand."));
3314 input_line_pointer
= skip_whites (input_line_pointer
);
3316 if (*input_line_pointer
!= ',')
3318 as_bad (_("Missing operand."));
3321 input_line_pointer
++;
3322 input_line_pointer
= skip_whites (input_line_pointer
);
3324 if (*input_line_pointer
== '#')
3326 input_line_pointer
++;
3327 input_line_pointer
= skip_whites (input_line_pointer
);
3328 expression (&operands
[0].exp
);
3329 if (operands
[0].exp
.X_op
== O_illegal
)
3331 as_bad (_("Illegal operand."));
3334 else if (operands
[0].exp
.X_op
== O_absent
)
3336 as_bad (_("Missing operand."));
3340 input_line_pointer
= skip_whites (input_line_pointer
);
3341 if (*input_line_pointer
!= ')')
3343 as_bad ("Missing `)' to close register indirect operand.");
3348 input_line_pointer
++;
3351 /* Ok so far, can only be one mode. */
3352 opcode_local
.format
= M68XG_OP_R_R_OFFS5
;
3353 operands
[0].mode
= M68XG_OP_R_R_OFFS5
;
3355 opcode
= find (opc
, operands
, 1);
3358 opcode_local
.opcode
= opcode
->opcode
3359 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5);
3360 if (operands
[0].exp
.X_op
!= O_constant
)
3363 ("Only constants supported for indexed OFFS5 mode\n");
3367 if (check_range (operands
[0].exp
.X_add_number
,
3368 M68XG_OP_R_R_OFFS5
))
3371 |= (operands
[0].exp
.X_add_number
);
3372 opcode_local
.format
= M68XG_OP_NONE
;
3373 build_insn_xg (&opcode_local
, operands
, 1);
3377 as_bad ("Number out of range for OFFS5\n");
3384 operands
[0].mode
= M68XG_OP_RD_RB_RI
;
3386 if (*input_line_pointer
== '-')
3388 operands
[0].mode
= M68XG_OP_RD_RB_mRI
;
3389 input_line_pointer
++;
3391 operands
[2].reg1
= register_name ();
3392 if (operands
[2].reg1
== REG_NONE
)
3394 as_bad ("Invalid register\n");
3398 if (*input_line_pointer
== '+')
3400 if (opcode_local
.format
== M68XG_OP_RD_RB_mRI
)
3402 as_bad (_("Illegal operand."));
3405 operands
[0].mode
= M68XG_OP_RD_RB_RIp
;
3406 input_line_pointer
++;
3409 input_line_pointer
= skip_whites (input_line_pointer
);
3410 if (*input_line_pointer
!= ')')
3413 ("Missing `)' to close register indirect operand.");
3418 input_line_pointer
++;
3421 opcode
= find (opc
, operands
, 1);
3424 opcode_local
.opcode
= opcode
->opcode
3425 | (operands
[0].reg1
<< 8) | (operands
[1].reg1
<< 5)
3426 | (operands
[2].reg1
<< 2);
3427 opcode_local
.format
= M68XG_OP_NONE
;
3428 build_insn_xg (&opcode_local
, operands
, 1);
3432 as_bad ("Failed to find opcode for %s %s\n",
3433 opc
->opcode
->name
, (char *)op_end
);
3440 as_bad (_("Failed to find a valid mode for `%s'."),
3444 if (opc
->opcode
&& !flag_mri
)
3446 char *p
= input_line_pointer
;
3448 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
3451 if (*p
!= '\n' && *p
)
3452 as_bad (_("Garbage at end of instruction: `%s'."), p
);
3455 input_line_pointer
= save
;
3457 /* Opcode is known but does not have valid operands. Print out the
3458 syntax for this opcode. */
3459 if (opc
->opcode
== 0)
3461 if (flag_print_insn_syntax
)
3462 print_insn_format (name
);
3464 as_bad (_("Invalid operand for `%s'"), name
);
3471 /* Find the opcode definition given its name. */
3472 opc
= (struct m68hc11_opcode_def
*) str_hash_find (m68hc11_hash
, name
);
3474 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are
3475 pseudo insns for relative branch. For these branches, we always
3476 optimize them (turned into absolute branches) even if --short-branches
3478 if (opc
== NULL
&& name
[0] == 'j' && name
[1] == 'b')
3480 opc
= (struct m68hc11_opcode_def
*) str_hash_find (m68hc11_hash
,
3483 && (!(opc
->format
& M6811_OP_JUMP_REL
)
3484 || (opc
->format
& M6811_OP_BITMASK
)))
3487 branch_optimize
= 1;
3490 /* The following test should probably be removed. This does not conform
3491 to Motorola assembler specs. */
3492 if (opc
== NULL
&& flag_mri
)
3494 if (*op_end
== ' ' || *op_end
== '\t')
3496 while (*op_end
== ' ' || *op_end
== '\t')
3501 (is_end_of_line
[op_end
[1]]
3502 || op_end
[1] == ' ' || op_end
[1] == '\t'
3503 || !ISALNUM (op_end
[1])))
3504 && (*op_end
== 'a' || *op_end
== 'b'
3505 || *op_end
== 'A' || *op_end
== 'B'
3506 || *op_end
== 'd' || *op_end
== 'D'
3507 || *op_end
== 'x' || *op_end
== 'X'
3508 || *op_end
== 'y' || *op_end
== 'Y'))
3510 name
[nlen
++] = TOLOWER (*op_end
++);
3512 opc
= (struct m68hc11_opcode_def
*) str_hash_find (m68hc11_hash
,
3518 /* Identify a possible instruction alias. There are some on the
3519 68HC12 to emulate a few 68HC11 instructions. */
3520 if (opc
== NULL
&& (current_architecture
& cpu6812
))
3524 for (i
= 0; i
< m68hc12_num_alias
; i
++)
3525 if (strcmp (m68hc12_alias
[i
].name
, name
) == 0)
3531 if (opc
== NULL
&& alias_id
< 0)
3533 as_bad (_("Opcode `%s' is not recognized."), name
);
3536 save
= input_line_pointer
;
3537 input_line_pointer
= (char *) op_end
;
3542 opcode
= find_opcode (opc
, operands
, &nb_operands
);
3547 if ((opcode
|| alias_id
>= 0) && !flag_mri
)
3549 char *p
= input_line_pointer
;
3551 while (*p
== ' ' || *p
== '\t' || *p
== '\n' || *p
== '\r')
3554 if (*p
!= '\n' && *p
)
3555 as_bad (_("Garbage at end of instruction: `%s'."), p
);
3558 input_line_pointer
= save
;
3562 char *f
= m68hc11_new_insn (m68hc12_alias
[alias_id
].size
);
3564 number_to_chars_bigendian (f
, m68hc12_alias
[alias_id
].code1
, 1);
3565 if (m68hc12_alias
[alias_id
].size
> 1)
3566 number_to_chars_bigendian (f
+ 1, m68hc12_alias
[alias_id
].code2
, 1);
3571 /* Opcode is known but does not have valid operands. Print out the
3572 syntax for this opcode. */
3575 if (flag_print_insn_syntax
)
3576 print_insn_format (name
);
3578 if (((strcmp (name
, "movb") == 0) || (strcmp (name
, "movw") == 0))
3579 && (current_architecture
& cpu9s12x
))
3583 if (strcmp (name
, "movb") == 0)
3588 /* The existing operand extract code fell over if these additional modes
3589 were enabled in m68hc11-opc.c. So they are commented there and
3590 decoded here instead. */
3592 if (operands
[1].mode
& (M6812_OP_IDX
| M6812_OP_IDX_1
3593 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
| M6812_PRE_INC
3594 | M6812_PRE_DEC
| M6812_POST_INC
| M6812_POST_DEC
))
3596 /* first check if valid mode then start building it up */
3597 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
3598 | M6811_OP_IND16
| M6812_OP_IDX
| M6812_OP_IDX_1
3599 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
3602 if (operands
[1].mode
& (M6811_OP_IND16
))
3607 f
= m68hc11_new_insn (2);
3609 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
))
3611 number_to_chars_bigendian (f
, 0x1800 + movb
+ opr16a
, 2);
3612 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3614 fixup8 (&operands
[0].exp
, M6811_OP_IMM8
,
3617 fixup16 (&operands
[0].exp
, M6811_OP_IMM16
,
3622 else if (operands
[0].mode
& M6811_OP_IND16
)
3624 number_to_chars_bigendian (f
, 0x1801 + movb
+ opr16a
, 2);
3625 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3626 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3631 number_to_chars_bigendian (f
, 0x1802 + movb
+ opr16a
, 2);
3632 build_indexed_byte (&operands
[0], operands
[0].mode
, 1);
3633 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3638 else if (operands
[1].mode
& M6811_OP_IND16
)
3640 /* First check if this is valid mode, then start building it up. */
3641 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
3642 | M6811_OP_IND16
| M6812_OP_IDX
| M6812_OP_IDX_1
3643 | M6812_OP_IDX_2
| M6812_OP_D_IDX
| M6812_OP_D_IDX_2
))
3646 if (operands
[1].mode
& (M6811_OP_IND16
))
3651 f
= m68hc11_new_insn (2);
3653 /* The first two cases here should actually be covered by the
3654 normal operand code. */
3655 if (operands
[0].mode
& (M6811_OP_IMM8
| M6811_OP_IMM16
))
3657 number_to_chars_bigendian (f
, 0x1800 + movb
+ opr16a
, 2);
3659 fixup8 (&operands
[0].exp
, M6811_OP_IMM8
, operands
[0].mode
);
3661 fixup16 (&operands
[0].exp
, M6811_OP_IMM16
, operands
[0].mode
);
3663 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3666 else if (operands
[0].mode
& M6811_OP_IND16
)
3668 number_to_chars_bigendian (f
, 0x1801 + movb
+ opr16a
, 2);
3669 build_indexed_byte (&operands
[1], operands
[1].mode
, 1);
3670 fixup16 (&operands
[0].exp
, M6811_OP_IND16
, operands
[0].mode
);
3675 number_to_chars_bigendian (f
, 0x1802 + movb
+ opr16a
, 2);
3676 build_indexed_byte (&operands
[0], operands
[0].mode
, 1);
3677 fixup16 (&operands
[1].exp
, M6811_OP_IND16
, operands
[1].mode
);
3683 as_bad (_("Invalid operand for `%s'"), name
);
3689 as_bad (_("Invalid operand for `%s'"), name
);
3694 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is
3695 relative and must be in the range -256..255 (9-bits). */
3696 if ((opcode
->format
& M6812_XBCC_MARKER
)
3697 && (opcode
->format
& M6811_OP_JUMP_REL
))
3698 build_dbranch_insn (opcode
, operands
, nb_operands
, branch_optimize
);
3700 /* Relative jumps instructions are taken care of separately. We have to make
3701 sure that the relative branch is within the range -128..127. If it's out
3702 of range, the instructions are changed into absolute instructions.
3703 This is not supported for the brset and brclr instructions. */
3704 else if ((opcode
->format
& (M6811_OP_JUMP_REL
| M6812_OP_JUMP_REL16
))
3705 && !(opcode
->format
& M6811_OP_BITMASK
))
3706 build_jump_insn (opcode
, operands
, nb_operands
, branch_optimize
);
3708 build_insn (opcode
, operands
, nb_operands
);
3712 /* Pseudo op to control the ELF flags. */
3714 s_m68hc11_mode (int x ATTRIBUTE_UNUSED
)
3716 char *name
= input_line_pointer
, ch
;
3718 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
3719 input_line_pointer
++;
3720 ch
= *input_line_pointer
;
3721 *input_line_pointer
= '\0';
3723 if (strcmp (name
, "mshort") == 0)
3725 elf_flags
&= ~E_M68HC11_I32
;
3727 else if (strcmp (name
, "mlong") == 0)
3729 elf_flags
|= E_M68HC11_I32
;
3731 else if (strcmp (name
, "mshort-double") == 0)
3733 elf_flags
&= ~E_M68HC11_F64
;
3735 else if (strcmp (name
, "mlong-double") == 0)
3737 elf_flags
|= E_M68HC11_F64
;
3741 as_warn (_("Invalid mode: %s\n"), name
);
3743 *input_line_pointer
= ch
;
3744 demand_empty_rest_of_line ();
3747 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions
3748 are using 'rtc' for returning. It is necessary to use 'call'
3749 to invoke them. This is also used by the debugger to correctly
3750 find the stack frame. */
3752 s_m68hc11_mark_symbol (int mark
)
3758 elf_symbol_type
*elfsym
;
3762 c
= get_symbol_name (&name
);
3763 symbolP
= symbol_find_or_make (name
);
3764 (void) restore_line_pointer (c
);
3768 bfdsym
= symbol_get_bfdsym (symbolP
);
3769 elfsym
= elf_symbol_from (bfdsym
);
3771 gas_assert (elfsym
);
3773 /* Mark the symbol far (using rtc for function return). */
3774 elfsym
->internal_elf_sym
.st_other
|= mark
;
3778 input_line_pointer
++;
3782 if (*input_line_pointer
== '\n')
3788 demand_empty_rest_of_line ();
3792 s_m68hc11_relax (int ignore ATTRIBUTE_UNUSED
)
3798 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
3800 as_bad (_("bad .relax format"));
3801 ignore_rest_of_line ();
3805 fix_new_exp (frag_now
, frag_now_fix (), 0, &ex
, 1,
3806 BFD_RELOC_M68HC11_RL_GROUP
);
3808 demand_empty_rest_of_line ();
3812 /* Relocation, relaxation and frag conversions. */
3814 /* PC-relative offsets are relative to the start of the
3815 next instruction. That is, the address of the offset, plus its
3816 size, since the offset is always the last part of the insn. */
3818 md_pcrel_from (fixS
*fixP
)
3820 if (fixP
->fx_r_type
== BFD_RELOC_M68HC11_RL_JUMP
)
3823 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3826 /* If while processing a fixup, a reloc really needs to be created
3827 then it is done here. */
3829 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
3833 reloc
= XNEW (arelent
);
3834 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
3835 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
3836 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
3837 if (fixp
->fx_r_type
== 0)
3838 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
3840 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
3841 if (reloc
->howto
== (reloc_howto_type
*) NULL
)
3843 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
3844 _("Relocation %d is not supported by object file format."),
3845 (int) fixp
->fx_r_type
);
3849 /* Since we use Rel instead of Rela, encode the vtable entry to be
3850 used in the relocation's section offset. */
3851 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
3852 reloc
->address
= fixp
->fx_offset
;
3858 /* We need a port-specific relaxation function to cope with sym2 - sym1
3859 relative expressions with both symbols in the same segment (but not
3860 necessarily in the same frag as this insn), for example:
3861 ldab sym2-(sym1-2),pc
3863 The offset can be 5, 9 or 16 bits long. */
3866 m68hc11_relax_frag (segT seg ATTRIBUTE_UNUSED
, fragS
*fragP
,
3867 long stretch ATTRIBUTE_UNUSED
)
3872 const relax_typeS
*this_type
;
3873 const relax_typeS
*start_type
;
3874 relax_substateT next_state
;
3875 relax_substateT this_state
;
3876 const relax_typeS
*table
= TC_GENERIC_RELAX_TABLE
;
3878 /* We only have to cope with frags as prepared by
3879 md_estimate_size_before_relax. The STATE_BITS16 case may get here
3880 because of the different reasons that it's not relaxable. */
3881 switch (fragP
->fr_subtype
)
3883 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
3884 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
3885 /* When we get to this state, the frag won't grow any more. */
3888 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
3889 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
3890 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
3891 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
3892 if (fragP
->fr_symbol
== NULL
3893 || S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
3894 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"),
3895 __FUNCTION__
, (long) fragP
->fr_symbol
);
3896 symbolP
= fragP
->fr_symbol
;
3897 if (symbol_resolved_p (symbolP
))
3898 as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
3900 aim
= S_GET_VALUE (symbolP
);
3904 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"),
3905 __FUNCTION__
, fragP
->fr_subtype
);
3908 /* The rest is stolen from relax_frag. There's no obvious way to
3909 share the code, but fortunately no requirement to keep in sync as
3910 long as fragP->fr_symbol does not have its segment changed. */
3912 this_state
= fragP
->fr_subtype
;
3913 start_type
= this_type
= table
+ this_state
;
3917 /* Look backwards. */
3918 for (next_state
= this_type
->rlx_more
; next_state
;)
3919 if (aim
>= this_type
->rlx_backward
)
3923 /* Grow to next state. */
3924 this_state
= next_state
;
3925 this_type
= table
+ this_state
;
3926 next_state
= this_type
->rlx_more
;
3931 /* Look forwards. */
3932 for (next_state
= this_type
->rlx_more
; next_state
;)
3933 if (aim
<= this_type
->rlx_forward
)
3937 /* Grow to next state. */
3938 this_state
= next_state
;
3939 this_type
= table
+ this_state
;
3940 next_state
= this_type
->rlx_more
;
3944 growth
= this_type
->rlx_length
- start_type
->rlx_length
;
3946 fragP
->fr_subtype
= this_state
;
3951 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec ATTRIBUTE_UNUSED
,
3956 char *buffer_address
= fragP
->fr_literal
;
3958 /* Address in object code of the displacement. */
3959 int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
3961 buffer_address
+= fragP
->fr_fix
;
3963 /* The displacement of the address, from current location. */
3964 value
= S_GET_VALUE (fragP
->fr_symbol
);
3965 disp
= (value
+ fragP
->fr_offset
) - object_address
;
3967 switch (fragP
->fr_subtype
)
3969 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
):
3970 fragP
->fr_opcode
[1] = disp
;
3973 case ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_WORD
):
3974 /* This relax is only for bsr and bra. */
3975 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
3976 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
3977 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
3979 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
3981 fix_new (fragP
, fragP
->fr_fix
- 1, 2,
3982 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
3986 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_BYTE
):
3987 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_BYTE
):
3988 fragP
->fr_opcode
[1] = disp
;
3991 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
, STATE_WORD
):
3992 /* Invert branch. */
3993 fragP
->fr_opcode
[0] ^= 1;
3994 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
3995 buffer_address
[0] = M6811_JMP
;
3996 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
3997 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4001 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
, STATE_WORD
):
4002 /* Translate branch into a long branch. */
4003 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
4004 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
4006 fix_new (fragP
, fragP
->fr_fix
, 2,
4007 fragP
->fr_symbol
, fragP
->fr_offset
, 1,
4008 BFD_RELOC_16_PCREL
);
4012 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS5
):
4013 if (fragP
->fr_symbol
!= 0
4014 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4018 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS5
):
4019 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 6;
4020 fragP
->fr_opcode
[0] |= value
& 0x1f;
4023 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS9
):
4024 /* For a PC-relative offset, use the displacement with a -1 correction
4025 to take into account the additional byte of the insn. */
4026 if (fragP
->fr_symbol
!= 0
4027 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4031 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS9
):
4032 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
4033 fragP
->fr_opcode
[0] |= 0xE0;
4034 fragP
->fr_opcode
[0] |= (value
>> 8) & 1;
4035 fragP
->fr_opcode
[1] = value
;
4039 case ENCODE_RELAX (STATE_INDEXED_PCREL
, STATE_BITS16
):
4040 case ENCODE_RELAX (STATE_INDEXED_OFFSET
, STATE_BITS16
):
4041 fragP
->fr_opcode
[0] = (fragP
->fr_opcode
[0] << 3);
4042 fragP
->fr_opcode
[0] |= 0xe2;
4043 if ((fragP
->fr_opcode
[0] & 0x0ff) == 0x0fa
4044 && fragP
->fr_symbol
!= 0
4045 && S_GET_SEGMENT (fragP
->fr_symbol
) != absolute_section
)
4047 fix_new (fragP
, fragP
->fr_fix
, 2,
4048 fragP
->fr_symbol
, fragP
->fr_offset
,
4049 1, BFD_RELOC_16_PCREL
);
4053 fix_new (fragP
, fragP
->fr_fix
, 2,
4054 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4059 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
):
4061 fragP
->fr_opcode
[0] |= 0x10;
4063 fragP
->fr_opcode
[1] = disp
& 0x0FF;
4066 case ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_WORD
):
4067 /* Invert branch. */
4068 fragP
->fr_opcode
[0] ^= 0x20;
4069 fragP
->fr_opcode
[1] = 3; /* Branch offset. */
4070 buffer_address
[0] = M6812_JMP
;
4071 fix_new (fragP
, fragP
->fr_fix
+ 1, 2,
4072 fragP
->fr_symbol
, fragP
->fr_offset
, 0, BFD_RELOC_16
);
4081 /* On an ELF system, we can't relax a weak symbol. The weak symbol
4082 can be overridden at final link time by a non weak symbol. We can
4083 relax externally visible symbol because there is no shared library
4084 and such symbol can't be overridden (unless they are weak). */
4086 relaxable_symbol (symbolS
*symbol
)
4088 return ! S_IS_WEAK (symbol
);
4091 /* Force truly undefined symbols to their maximum size, and generally set up
4092 the frag list to be relaxed. */
4094 md_estimate_size_before_relax (fragS
*fragP
, asection
*segment
)
4096 if (RELAX_LENGTH (fragP
->fr_subtype
) == STATE_UNDF
)
4098 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
4099 || !relaxable_symbol (fragP
->fr_symbol
)
4100 || (segment
!= absolute_section
4101 && RELAX_STATE (fragP
->fr_subtype
) == STATE_INDEXED_OFFSET
))
4103 /* Non-relaxable cases. */
4105 char *buffer_address
;
4107 old_fr_fix
= fragP
->fr_fix
;
4108 buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4110 switch (RELAX_STATE (fragP
->fr_subtype
))
4112 case STATE_PC_RELATIVE
:
4114 /* This relax is only for bsr and bra. */
4115 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
4116 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
4117 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
4119 if (flag_fixed_branches
)
4120 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4121 _("bra or bsr with undefined symbol."));
4123 /* The symbol is undefined or in a separate section.
4124 Turn bra into a jmp and bsr into a jsr. The insn
4125 becomes 3 bytes long (instead of 2). A fixup is
4126 necessary for the unresolved symbol address. */
4127 fragP
->fr_opcode
[0] = convert_branch (fragP
->fr_opcode
[0]);
4129 fix_new (fragP
, fragP
->fr_fix
- 1, 2, fragP
->fr_symbol
,
4130 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4134 case STATE_CONDITIONAL_BRANCH
:
4135 gas_assert (current_architecture
& cpu6811
);
4137 fragP
->fr_opcode
[0] ^= 1; /* Reverse sense of branch. */
4138 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
4140 /* Don't use fr_opcode[2] because this may be
4141 in a different frag. */
4142 buffer_address
[0] = M6811_JMP
;
4145 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4146 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4150 case STATE_INDEXED_OFFSET
:
4151 gas_assert (current_architecture
& cpu6812
);
4153 if (fragP
->fr_symbol
4154 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
4156 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
4158 /* Return the size of the variable part of the frag. */
4159 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4163 /* Switch the indexed operation to 16-bit mode. */
4164 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
4165 fragP
->fr_opcode
[0] |= 0xe2;
4166 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4167 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4172 case STATE_INDEXED_PCREL
:
4173 gas_assert (current_architecture
& cpu6812
);
4175 if (fragP
->fr_symbol
4176 && S_GET_SEGMENT (fragP
->fr_symbol
) == absolute_section
)
4178 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
4180 /* Return the size of the variable part of the frag. */
4181 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4185 fragP
->fr_opcode
[0] = fragP
->fr_opcode
[0] << 3;
4186 fragP
->fr_opcode
[0] |= 0xe2;
4187 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4188 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
4193 case STATE_XBCC_BRANCH
:
4194 gas_assert (current_architecture
& cpu6812
);
4196 fragP
->fr_opcode
[0] ^= 0x20; /* Reverse sense of branch. */
4197 fragP
->fr_opcode
[1] = 3; /* Skip next jmp insn (3 bytes). */
4199 /* Don't use fr_opcode[2] because this may be
4200 in a different frag. */
4201 buffer_address
[0] = M6812_JMP
;
4204 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4205 fragP
->fr_offset
, 0, BFD_RELOC_16
);
4209 case STATE_CONDITIONAL_BRANCH_6812
:
4210 gas_assert (current_architecture
& cpu6812
);
4212 /* Translate into a lbcc branch. */
4213 fragP
->fr_opcode
[1] = fragP
->fr_opcode
[0];
4214 fragP
->fr_opcode
[0] = M6811_OPCODE_PAGE2
;
4216 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4217 fragP
->fr_offset
, 1, BFD_RELOC_16_PCREL
);
4222 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
4226 /* Return the growth in the fixed part of the frag. */
4227 return fragP
->fr_fix
- old_fr_fix
;
4230 /* Relaxable cases. */
4231 switch (RELAX_STATE (fragP
->fr_subtype
))
4233 case STATE_PC_RELATIVE
:
4234 /* This relax is only for bsr and bra. */
4235 gas_assert (IS_OPCODE (fragP
->fr_opcode
[0], M6811_BSR
)
4236 || IS_OPCODE (fragP
->fr_opcode
[0], M6811_BRA
)
4237 || IS_OPCODE (fragP
->fr_opcode
[0], M6812_BSR
));
4239 fragP
->fr_subtype
= ENCODE_RELAX (STATE_PC_RELATIVE
, STATE_BYTE
);
4242 case STATE_CONDITIONAL_BRANCH
:
4243 gas_assert (current_architecture
& cpu6811
);
4245 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH
,
4249 case STATE_INDEXED_OFFSET
:
4250 gas_assert (current_architecture
& cpu6812
);
4252 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_OFFSET
,
4256 case STATE_INDEXED_PCREL
:
4257 gas_assert (current_architecture
& cpu6812
);
4259 fragP
->fr_subtype
= ENCODE_RELAX (STATE_INDEXED_PCREL
,
4263 case STATE_XBCC_BRANCH
:
4264 gas_assert (current_architecture
& cpu6812
);
4266 fragP
->fr_subtype
= ENCODE_RELAX (STATE_XBCC_BRANCH
, STATE_BYTE
);
4269 case STATE_CONDITIONAL_BRANCH_6812
:
4270 gas_assert (current_architecture
& cpu6812
);
4272 fragP
->fr_subtype
= ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812
,
4278 if (fragP
->fr_subtype
>= sizeof (md_relax_table
) / sizeof (md_relax_table
[0]))
4279 as_fatal (_("Subtype %d is not recognized."), fragP
->fr_subtype
);
4281 /* Return the size of the variable part of the frag. */
4282 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
4285 /* See whether we need to force a relocation into the output file. */
4287 tc_m68hc11_force_relocation (fixS
*fixP
)
4289 if (fixP
->fx_r_type
== BFD_RELOC_M68HC11_RL_GROUP
)
4292 return generic_force_reloc (fixP
);
4295 /* Here we decide which fixups can be adjusted to make them relative
4296 to the beginning of the section instead of the symbol. Basically
4297 we need to make sure that the linker relaxation is done
4298 correctly, so in some cases we force the original symbol to be
4301 tc_m68hc11_fix_adjustable (fixS
*fixP
)
4303 switch (fixP
->fx_r_type
)
4305 /* For the linker relaxation to work correctly, these relocs
4306 need to be on the symbol itself. */
4308 case BFD_RELOC_M68HC11_RL_JUMP
:
4309 case BFD_RELOC_M68HC11_RL_GROUP
:
4310 case BFD_RELOC_VTABLE_INHERIT
:
4311 case BFD_RELOC_VTABLE_ENTRY
:
4314 /* The memory bank addressing translation also needs the original
4316 case BFD_RELOC_M68HC11_LO16
:
4317 case BFD_RELOC_M68HC11_PAGE
:
4318 case BFD_RELOC_M68HC11_24
:
4327 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4330 long value
= * valP
;
4332 if (fixP
->fx_addsy
== (symbolS
*) NULL
)
4335 /* We don't actually support subtracting a symbol. */
4336 if (fixP
->fx_subsy
!= (symbolS
*) NULL
)
4337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, _("Expression too complex."));
4339 /* Patch the instruction with the resolved operand. Elf relocation
4340 info will also be generated to take care of linker/loader fixups.
4341 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit
4342 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker
4343 will warn for overflows). BFD_RELOC_8_PCREL should not be generated
4344 because it's either resolved or turned out into non-relative insns (see
4345 relax table, bcc, bra, bsr transformations)
4347 The BFD_RELOC_32 is necessary for the support of --gstabs. */
4348 where
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
4350 switch (fixP
->fx_r_type
)
4353 bfd_putb32 ((bfd_vma
) value
, (unsigned char *) where
);
4357 case BFD_RELOC_M68HC11_24
:
4358 bfd_putb16 ((bfd_vma
) (value
& 0x0ffff), (unsigned char *) where
);
4359 ((bfd_byte
*) where
)[2] = ((value
>> 16) & 0x0ff);
4363 case BFD_RELOC_16_PCREL
:
4364 case BFD_RELOC_M68HC11_LO16
:
4365 bfd_putb16 ((bfd_vma
) value
, (unsigned char *) where
);
4366 if (value
< -65537 || value
> 65535)
4367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4368 _("Value out of 16-bit range."));
4371 case BFD_RELOC_M68HC11_HI8
:
4372 /* Caution, %hi(<symbol>+%ld) will generate incorrect code if %lo
4374 case BFD_RELOC_M68HC12_HI8XG
:
4378 case BFD_RELOC_M68HC12_LO8XG
:
4379 case BFD_RELOC_M68HC11_LO8
:
4381 case BFD_RELOC_M68HC11_PAGE
:
4382 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
4385 case BFD_RELOC_8_PCREL
:
4386 ((bfd_byte
*) where
)[0] = (bfd_byte
) value
;
4388 if (value
< -128 || value
> 127)
4389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4390 _("Value %ld too large for 8-bit PC-relative branch."),
4394 /* These next two are for XGATE. */
4395 case BFD_RELOC_M68HC12_9_PCREL
:
4396 ((bfd_byte
*) where
)[0] |= (bfd_byte
) ((value
>>9) & 0x01);
4397 ((bfd_byte
*) where
)[1] = (bfd_byte
) ((value
>>1) & 0xff);
4398 if (value
< -512 || value
> 511)
4399 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4400 _("Value %ld too large for 9-bit PC-relative branch."),
4404 case BFD_RELOC_M68HC12_10_PCREL
:
4405 ((bfd_byte
*) where
)[0] |= (bfd_byte
) ((value
>>9) & 0x03);
4406 ((bfd_byte
*) where
)[1] = (bfd_byte
) ((value
>>1) & 0xff);
4407 if (value
< -1024 || value
> 1023)
4408 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4409 _("Value %ld too large for 10-bit PC-relative branch."),
4414 case BFD_RELOC_M68HC11_3B
:
4415 if (value
<= 0 || value
> 8)
4416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4417 _("Auto increment/decrement offset '%ld' is out of range."),
4424 where
[0] = where
[0] | (value
& 0x07);
4427 case BFD_RELOC_M68HC12_5B
:
4428 if (value
< -16 || value
> 15)
4429 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4430 _("Offset out of 5-bit range for movw/movb insn: %ld"),
4435 where
[0] |= (0x10 | (16 + value
));
4438 case BFD_RELOC_M68HC12_9B
:
4439 if (value
< -256 || value
> 255)
4440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4441 _("Offset out of 9-bit range for movw/movb insn: %ld"),
4443 /* sign bit already in xb postbyte */
4447 where
[1] = (256 + value
);
4450 case BFD_RELOC_M68HC12_16B
:
4451 if (value
< -32768 || value
> 32767)
4452 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4453 _("Offset out of 16-bit range for movw/movb insn: %ld"),
4458 where
[0] = (value
>> 8);
4459 where
[1] = (value
& 0xff);
4462 case BFD_RELOC_M68HC11_RL_JUMP
:
4463 case BFD_RELOC_M68HC11_RL_GROUP
:
4464 case BFD_RELOC_VTABLE_INHERIT
:
4465 case BFD_RELOC_VTABLE_ENTRY
:
4470 as_fatal (_("Line %d: unknown relocation type: 0x%x."),
4471 fixP
->fx_line
, fixP
->fx_r_type
);
4475 /* Set the ELF specific flags. */
4477 m68hc11_elf_final_processing (void)
4479 if (current_architecture
& cpu6812s
)
4480 elf_flags
|= EF_M68HCS12_MACH
;
4481 elf_elfheader (stdoutput
)->e_flags
&= ~EF_M68HC11_ABI
;
4482 elf_elfheader (stdoutput
)->e_flags
|= elf_flags
;
4485 /* Process directives specified via pseudo ops */
4487 s_m68hc11_parse_pseudo_instruction (int pseudo_insn
)
4489 switch (pseudo_insn
)
4491 case E_M68HC11_NO_BANK_WARNING
:
4492 elf_flags
|= E_M68HC11_NO_BANK_WARNING
;
4495 as_bad (_("Invalid directive"));