1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
4 Copyright (C) 1987, 1991, 1992, 1993 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
31 /* The opcode table is too big for gcc, which (currently) requires
32 exponential space at compile time for initialized arrays. */
34 #define DO_BREAK_UP_BIG_DECL
35 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
36 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
39 /* Note that this file includes real declarations and thus can only be
40 included by one source file per executable. */
41 #include "opcode/m68k.h"
43 /* This array holds the chars that always start a comment. If the
44 pre-processor is disabled, these aren't very useful */
45 CONST
char comment_chars
[] = "|";
47 /* This array holds the chars that only start a comment at the beginning of
48 a line. If the line seems to have the form '# 123 filename'
49 .line and .file directives will appear in the pre-processed output */
50 /* Note that input_file.c hand checks for '#' at the beginning of the
51 first line of the input file. This is because the compiler outputs
52 #NO_APP at the beginning of its output. */
53 /* Also note that comments like this one will always work. */
54 CONST
char line_comment_chars
[] = "#";
56 CONST
char line_separator_chars
[] = "";
58 /* Chars that can be used to separate mant from exp in floating point nums */
59 CONST
char EXP_CHARS
[] = "eE";
61 /* Chars that mean this number is a floating point constant, as
62 in "0f12.456" or "0d1.2345e12". */
64 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
66 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here. */
70 const int md_reloc_size
= 8; /* Size of relocation record */
72 /* Are we trying to generate PIC code? If so, absolute references
73 ought to be made into linkage table references or pc-relative
77 /* Its an arbitrary name: This means I don't approve of it */
78 /* See flames below */
79 static struct obstack robyn
;
81 #define TAB(x,y) (((x)<<2)+(y))
82 #define TABTYPE(xy) ((xy) >> 2)
98 unsigned long m_opcode
;
102 struct m68k_incant
*m_next
;
105 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
106 #define gettwo(x) (((x)->m_opcode)&0xffff)
108 /* Operands we can parse: (And associated modes)
114 reg: address or data register
115 areg: address register
116 apc: address register, PC, ZPC or empty string
117 num: 16 or 32 bit num
119 sz: w or l if omitted, l assumed
120 scale: 1 2 4 or 8 if omitted, 1 assumed
122 7.4 IMMED #num --> NUM
123 0.? DREG dreg --> dreg
124 1.? AREG areg --> areg
125 2.? AINDR areg@ --> *(areg)
126 3.? AINC areg@+ --> *(areg++)
127 4.? ADEC areg@- --> *(--areg)
128 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
129 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
130 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
131 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
132 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
133 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
134 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
135 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
136 7.0 ABSL num:sz --> *(num)
137 num --> *(num) (sz L assumed)
138 *** MSCR otherreg --> Magic
140 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
141 ?.? DINDR dreg@ --> (dreg) -- cas2 only
151 a1@(5,d2:w:1) @(45,d6:l:4)
156 #name@(numw) -->turn into PC rel mode
157 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
187 short e_siz
; /* 0== default 1==short/byte 2==word 3==long */
190 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
191 8-15==addr reg for operands that take both types */
195 DATA
= 1, /* 1- 8 == data registers 0-7 */
215 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
220 FPREG
, /* Eight FP registers */
229 COPNUM
= (FPREG
+ 8), /* Co-processor #1-#8 */
238 PC
, /* Program counter */
239 ZPC
, /* Hack for Program space, but 0 addressing */
241 CCR
, /* Condition code Reg */
243 /* These have to be in order for the movec instruction to work. */
244 USP
, /* User Stack Pointer */
245 ISP
, /* Interrupt stack pointer */
260 /* end of movec ordering constraints */
266 DRP
, /* 68851 or 68030 MMU regs */
290 PSR
, /* aka MMUSR on 68030 (but not MMUSR on 68040)
291 and ACUSR on 68ec030 */
294 IC
, /* instruction cache token */
295 DC
, /* data cache token */
296 NC
, /* no cache token */
297 BC
, /* both caches token */
299 TT0
, /* 68030 access control unit regs */
303 /* Internal form of an operand. */
306 char *error
; /* Couldn't parse it */
307 enum operand_type mode
; /* What mode this instruction is in. */
308 enum _register reg
; /* Base register */
309 struct m68k_exp
*con1
;
310 int ireg
; /* Index register */
311 int isiz
; /* 0==unspec 1==byte(?) 2==short 3==long */
312 int imul
; /* Multipy ireg by this (1,2,4,or 8) */
313 struct m68k_exp
*con2
;
316 /* internal form of a 68020 instruction */
320 char *args
; /* list of opcode info */
323 int numo
; /* Number of shorts in opcode */
326 struct m68k_op operands
[6];
328 int nexp
; /* number of exprs in use */
329 struct m68k_exp exprs
[4];
331 int nfrag
; /* Number of frags we have to produce */
334 int fragoff
; /* Where in the current opcode[] the frag ends */
341 int nrel
; /* Num of reloc strucs in use */
349 reloc
[5]; /* Five is enough??? */
352 #define cpu_of_arch(x) ((x) & m68000up)
353 #define float_of_arch(x) ((x) & mfloat)
354 #define mmu_of_arch(x) ((x) & mmmu)
356 static struct m68k_it the_ins
; /* the instruction being assembled */
358 #define seg(exp) ((exp)->e_seg)
359 #define op(exp) ((exp)->e_exp.X_op)
360 #define adds(exp) ((exp)->e_exp.X_add_symbol)
361 #define subs(exp) ((exp)->e_exp.X_op_symbol)
362 #define offs(exp) ((exp)->e_exp.X_add_number)
364 /* Macros for adding things to the m68k_it struct */
366 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
368 /* Like addword, but goes BEFORE general operands */
372 struct m68k_incant
*opcode
;
375 for(z
=the_ins
.numo
;z
>opcode
->m_codenum
;--z
)
376 the_ins
.opcode
[z
]=the_ins
.opcode
[z
-1];
377 for(z
=0;z
<the_ins
.nrel
;z
++)
378 the_ins
.reloc
[z
].n
+=2;
379 the_ins
.opcode
[opcode
->m_codenum
]=w
;
383 static struct m68k_exp
*
388 the_ins
.exprs
[the_ins
.nexp
].e_beg
=beg
;
389 the_ins
.exprs
[the_ins
.nexp
].e_end
=end
;
390 return &the_ins
.exprs
[the_ins
.nexp
++];
394 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
397 add_fix (width
, exp
, pc_rel
)
399 struct m68k_exp
*exp
;
402 the_ins
.reloc
[the_ins
.nrel
].n
= (((width
)=='B')
405 ? ((the_ins
.numo
-1)*2)
406 : (the_ins
.numo
*2)));
407 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->e_exp
;
408 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
409 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
413 add_frag(add
,off
,type
)
418 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
419 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
420 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
421 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
425 ((exp) && op (exp) != O_constant && op (exp) != O_big)
427 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
428 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
429 static int get_regs
PARAMS ((int i
, char *str
, struct m68k_op
*opP
));
430 static int reverse_16_bits
PARAMS ((int in
));
431 static int reverse_8_bits
PARAMS ((int in
));
432 static int try_index
PARAMS ((char **s
, struct m68k_op
*opP
));
433 static void install_gen_operand
PARAMS ((int mode
, int val
));
434 static void install_operand
PARAMS ((int mode
, int val
));
435 static void s_bss
PARAMS ((int));
436 static void s_data1
PARAMS ((int));
437 static void s_data2
PARAMS ((int));
438 static void s_even
PARAMS ((int));
439 static void s_proc
PARAMS ((int));
441 static int current_architecture
;
443 /* BCC68000 is for patching in an extra jmp instruction for long offsets
444 on the 68000. The 68000 doesn't support long branches with branchs */
446 /* This table desribes how you change sizes for the various types of variable
447 size expressions. This version only supports two kinds. */
449 /* Note that calls to frag_var need to specify the maximum expansion
450 needed; this is currently 10 bytes for DBCC. */
453 How far Forward this mode will reach:
454 How far Backward this mode will reach:
455 How many bytes this mode will add to the size of the frag
456 Which mode to go to if the offset won't fit in this one
458 CONST relax_typeS md_relax_table
[] =
460 {1, 1, 0, 0}, /* First entries aren't used */
461 {1, 1, 0, 0}, /* For no good reason except */
462 {1, 1, 0, 0}, /* that the VAX doesn't either */
465 {(127), (-128), 0, TAB (ABRANCH
, SHORT
)},
466 {(32767), (-32768), 2, TAB (ABRANCH
, LONG
)},
470 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
471 {(32767), (-32768), 2, TAB (FBRANCH
, LONG
)},
475 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
476 {(32767), (-32768), 2, TAB (PCREL
, LONG
)},
480 {(127), (-128), 0, TAB (BCC68000
, SHORT
)},
481 {(32767), (-32768), 2, TAB (BCC68000
, LONG
)},
482 {0, 0, 6, 0}, /* jmp long space */
485 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
486 {(32767), (-32768), 2, TAB (DBCC
, LONG
)},
487 {0, 0, 10, 0}, /* bra/jmp long space */
490 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
491 {32767, -32768, 2, TAB (PCLEA
, LONG
)},
497 /* These are the machine dependent pseudo-ops. These are included so
498 the assembler can work on the output from the SUN C compiler, which
502 /* This table describes all the machine specific pseudo-ops the assembler
503 has to support. The fields are:
504 pseudo-op name without dot
505 function to call to execute this pseudo-op
506 Integer arg to pass to the function
508 CONST pseudo_typeS md_pseudo_table
[] =
510 {"data1", s_data1
, 0},
511 {"data2", s_data2
, 0},
514 {"skip", s_space
, 0},
517 {"align", s_align_bytes
, 0},
523 /* The mote pseudo ops are put into the opcode table, since they
524 don't start with a . they look like opcodes to gas.
526 extern void obj_coff_section ();
528 CONST pseudo_typeS mote_pseudo_table
[] =
536 {"ds.l", s_space
, 4},
538 {"ds.w", s_space
, 2},
539 {"ds.b", s_space
, 1},
541 {"xdef", s_globl
, 0},
542 {"align", s_align_ptwo
, 0},
544 {"sect", obj_coff_section
, 0},
545 {"section", obj_coff_section
, 0},
550 #define issbyte(x) ((x)>=-128 && (x)<=127)
551 #define isubyte(x) ((x)>=0 && (x)<=255)
552 #define issword(x) ((x)>=-32768 && (x)<=32767)
553 #define isuword(x) ((x)>=0 && (x)<=65535)
555 #define isbyte(x) ((x)>= -255 && (x)<=255)
556 #define isword(x) ((x)>=-32768 && (x)<=65535)
557 #define islong(x) (1)
559 extern char *input_line_pointer
;
567 /* JF these tables here are for speed at the expense of size */
568 /* You can replace them with the #if 0 versions if you really
569 need space and don't mind it running a bit slower */
571 static char mklower_table
[256];
572 #define mklower(c) (mklower_table[(unsigned char)(c)])
573 static char notend_table
[256];
574 static char alt_notend_table
[256];
575 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
576 alt_notend_table[(unsigned char)(s[1])])))
579 #define mklower(c) (isupper(c) ? tolower(c) : c)
583 /* JF modified this to handle cases where the first part of a symbol name
584 looks like a register */
587 * m68k_reg_parse() := if it looks like a register, return it's token &
588 * advance the pointer.
600 #ifdef REGISTER_PREFIX
601 if (*start
!= REGISTER_PREFIX
)
606 if (*p
== OPTIONAL_REGISTER_PREFIX
)
609 if (!isalpha (*p
) || !is_name_beginner (*p
))
613 while (isalpha (c
) || isdigit (c
) || c
== '_')
619 symbolP
= symbol_find (start
);
622 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
625 return S_GET_VALUE (symbolP
);
631 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
632 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
634 /* Parse an index specification using Motorola syntax. */
637 try_moto_index (s
, opP
)
648 i
= m68k_reg_parse (&ss
);
649 if (!(i
>= DATA
+ 0 && i
<= ADDR
+ 7))
650 { /* if i is not DATA or ADDR reg */
651 opP
->error
= "Invalid index register";
667 opP
->error
= "Missing . in index register";
672 if (mklower (*ss
) == 'w')
674 else if (mklower (*ss
) == 'l')
678 opP
->error
= "Size spec not .W or .L";
683 if (*ss
== '.' || *ss
== '*')
692 opP
->imul
= *ss
- '0';
695 opP
->error
= "index multiplier not 1, 2, 4 or 8";
705 opP
->error
= "Missing )";
716 * try_index := data_or_address_register + ')' + SKIP_W
717 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
719 * multiplier := <empty>
720 * | ':' + multiplier_number
723 * multiplier_number := '1' | '2' | '4' | '8' ;
725 * size_spec := 'l' | 'L' | 'w' | 'W' ;
727 * SKIP_W := <empty> | ' ' ;
741 i
= m68k_reg_parse (&ss
);
742 if (!(i
>= DATA
+ 0 && i
<= ADDR
+ 7))
743 { /* if i is not DATA or ADDR reg */
759 opP
->error
= "Missing : in index register";
775 opP
->error
= "Index register size spec not :w or :l";
789 if (cpu_of_arch (current_architecture
) < m68020
)
791 opP
->error
= "no index scaling in pre-68020's";
795 opP
->imul
= *ss
- '0';
798 opP
->error
= "index multiplier not 1, 2, 4 or 8";
808 opP
->error
= "Missing )";
817 /* Ian Taylor expanded this function to accept both MIT and Motorola
818 syntax. I removed the old comment, since it was wrong. The syntax
819 this accepted even before my changes was complex and undocumented.
820 I mainly added a large case when the operand string does not
821 contain an '@', since the Motorola syntax does not use the '@'
825 m68k_ip_op (str
, opP
)
827 register struct m68k_op
*opP
;
831 char *parse_index ();
837 } /* Find the beginning of the string */
841 opP
->error
= "Missing operand";
845 for (strend
= str
; *strend
; strend
++)
852 opP
->con1
= add_exp (str
, strend
);
855 } /* Guess what: A constant. Shar and enjoy */
857 i
= m68k_reg_parse (&str
);
861 if (*str
== '/' || *str
== '-')
863 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
865 return get_regs (i
, str
, opP
);
870 /* "Rn" Register Direct mode */
871 if (i
>= DATA
+ 0 && i
<= DATA
+ 7)
873 else if (i
>= ADDR
+ 0 && i
<= ADDR
+ 7)
885 if ((stmp
= strchr (str
, '@')) != 0)
887 opP
->con1
= add_exp (str
, stmp
- 1);
894 if ((current_architecture
& m68020up
) == 0)
897 } /* if target is not a '20 or better */
900 if (*stmp
++ != '(' || *strend
-- != ')')
902 opP
->error
= "Malformed operand";
905 i
= try_index (&stmp
, opP
);
906 opP
->con2
= add_exp (stmp
, strend
);
917 } /* if there's an '@' */
919 #ifndef MIT_SYNTAX_ONLY
920 /* The operand has no '@'. Try to parse it using
922 /* Logic of the parsing switch(*str):
926 REG AREG or DREG or MSCR 3 or 2 or 13
927 REG- or REG/ REGLST 14
932 (EXPR,REG,INDX) AINDX 8
935 EXP2(REG,INDX) AINDX 8
938 REG means truth(m68k_reg_parse(&str))
939 INDX means truth(try_moto_index(&str,opP))
941 EXP2 means not REG and not '(' and not '-('
947 i
= m68k_reg_parse (&str
);
948 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7)
949 && (i
< DATA
+ 0 || i
> DATA
+ 7
950 || *str
!= ')' || str
[1] != '0')
951 && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
)
953 /* Can't indirect off non address regs */
954 opP
->error
= "Invalid indirect register";
965 /* "(An)" Address Register Indirect mode
966 or "(Dn)" for cas2. */
967 if (i
>= DATA
+ 0 && i
<= DATA
+ 7)
977 /* "(An)+" Register Indirect w Postincrement */
982 opP
->error
= "Junk after indirect";
988 i
= try_moto_index (&str
, opP
);
991 /* "(An,Rn)" Register Indirect with Index mode*/
997 opP
->error
= "Bad indirect syntax";
1003 /* "(EXPR,..." , a displacement */
1007 if ((stmp
= index (str
, ',')) != NULL
)
1009 opP
->con1
= add_exp (str
, stmp
- 1);
1012 i
= m68k_reg_parse (&str
);
1013 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
)
1015 /* Can't indirect off non address regs */
1016 opP
->error
= "Invalid indirect register";
1024 /* "(d,An)" Register Indirect w Displacement */
1031 i
= try_moto_index (&str
, opP
);
1034 /* "(d,An,Rn)" Register Indirect with Index */
1040 opP
->error
= "Bad indirect syntax";
1046 opP
->error
= "Invalid register";
1053 opP
->con1
= add_exp (str
- 1, strend
);
1064 i
= m68k_reg_parse (&str
);
1065 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
)
1067 /* Can't indirect off non address regs */
1068 opP
->error
= "Invalid indirect register";
1079 /* "-(An)" Register Indirect with Predecrement */
1083 opP
->error
= "Junk after indirect";
1086 opP
->error
= "Bad indirect syntax";
1090 opP
->con1
= add_exp (str
- 2, strend
);
1093 /* if '-' but not "-(', do nothing */
1096 /* whether *str=='-' or not */
1098 /* "EXP2" or "EXP2(REG..." */
1101 if ((stmp
= index (str
, '(')) != NULL
)
1105 opP
->con1
= add_exp (str
, stmp
- 1);
1107 i
= m68k_reg_parse (&str
);
1108 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
1109 && i
!= ZPC
&& i
!= FAIL
)
1111 /* Can't indirect off non address regs */
1112 opP
->error
= "Invalid indirect register";
1120 /* "d(An)" Register Indirect w Displacement */
1127 i
= try_moto_index (&str
, opP
);
1130 /* "d(An,Rn)" Register Indirect with Index */
1136 opP
->error
= "Bad indirect syntax";
1143 opP
->con1
= add_exp (ostr
, strend
);
1149 /* "EXP2" Absolute */
1152 if (strend
[-1] == '.' || strend
[-1] == ':')
1154 /* mode ==foo.[wl] */
1167 opP
->con1
= add_exp (str
, strend
);
1172 #else /* defined (MIT_SYNTAX_ONLY) */
1174 opP
->con1
= add_exp (str
, strend
);
1176 #endif /* defined (MIT_SYNTAX_ONLY) */
1181 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1182 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
1183 && (str
[1] != '\0' || i
< DATA
+ 0 || i
> DATA
+ 7))
1185 opP
->error
= "Invalid indirect register";
1194 if (i
< DATA
+ 0 || i
> DATA
+ 7)
1209 opP
->error
= "Junk after indirect";
1212 /* Some kind of indexing involved. Lets find out how bad it is */
1213 i
= try_index (&str
, opP
);
1214 /* Didn't start with an index reg, maybe its offset or offset,reg */
1225 opP
->error
= "Missing )";
1258 opP
->error
="Specified size isn't :w or :l";
1261 opP
->con1
=add_exp(beg_str
,str
-4);
1262 opP
->con1
->e_siz
=siz
;
1266 opP
->con1
= add_exp (beg_str
, str
- 2);
1267 /* Should be offset,reg */
1270 i
= try_index (&str
, opP
);
1273 opP
->error
= "Malformed index reg";
1278 /* We've now got offset) offset,reg) or reg) */
1282 /* Th-the-thats all folks */
1283 if (opP
->reg
== FAIL
)
1284 opP
->mode
= AINDX
; /* Other form of indirect */
1285 else if (opP
->ireg
== FAIL
)
1291 /* Next thing had better be another @ */
1306 if ((current_architecture
& m68020up
) == 0)
1309 } /* if target is not a '20 or better */
1312 if (opP
->ireg
!= FAIL
)
1316 i
= try_index (&str
, opP
);
1319 opP
->error
= "Two index registers! not allowed!";
1325 i
= try_index (&str
, opP
);
1340 opP
->error
= "Missing )";
1355 opP
->con2
= add_exp (beg_str
, str
- 2);
1359 if (opP
->ireg
!= FAIL
)
1361 opP
->error
= "Can't have two index regs";
1365 i
= try_index (&str
, opP
);
1369 opP
->error
= "malformed index reg";
1375 else if (opP
->ireg
!= FAIL
)
1391 opP
->error
= "Junk after indirect";
1395 } /* m68k_ip_op() */
1398 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1401 tc_coff_fix2rtype (fixP
)
1404 return (fixP
->fx_pcrel
?
1405 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
1406 fixP
->fx_size
== 2 ? R_PCRWORD
:
1408 (fixP
->fx_size
== 1 ? R_RELBYTE
:
1409 fixP
->fx_size
== 2 ? R_RELWORD
:
1417 #ifdef BFD_ASSEMBLER
1420 tc_gen_reloc (section
, fixp
)
1425 bfd_reloc_code_real_type code
;
1427 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1428 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1430 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1431 MAP (1, 0, BFD_RELOC_8
);
1432 MAP (2, 0, BFD_RELOC_16
);
1433 MAP (4, 0, BFD_RELOC_32
);
1434 MAP (1, 1, BFD_RELOC_8_PCREL
);
1435 MAP (2, 1, BFD_RELOC_16_PCREL
);
1436 MAP (4, 1, BFD_RELOC_32_PCREL
);
1441 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
1442 assert (reloc
!= 0);
1443 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1444 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1446 reloc
->addend
= fixp
->fx_addnumber
;
1450 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1451 assert (reloc
->howto
!= 0);
1456 #endif /* BFD_ASSEMBLER */
1458 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1462 struct m68k_op thark
;
1468 memset (&thark
, '\0', sizeof (thark
));
1469 if (!m68k_ip_op (buf
, &thark
))
1472 printf ("op1 error %s in %s\n", thark
.error
, buf
);
1473 printf ("mode %d, reg %d, ", thark
.mode
, thark
.reg
);
1475 printf ("Constant: '%.*s',", 1 + thark
.e_const
- thark
.b_const
, thark
.b_const
);
1476 printf ("ireg %d, isiz %d, imul %d ", thark
.ireg
, thark
.isiz
, thark
.imul
);
1478 printf ("Iadd: '%.*s'", 1 + thark
.e_iadd
- thark
.b_iadd
, thark
.b_iadd
);
1487 /* Handle of the OPCODE hash table. NULL means any use before
1488 m68k_ip_begin() will crash. */
1489 static struct hash_control
*op_hash
;
1495 * This converts a string into a 68k instruction.
1496 * The string must be a bare single instruction in sun format
1497 * with RMS-style 68020 indirects
1500 * It provides some error messages: at most one fatal error message (which
1501 * stops the scan) and at most one warning message for each operand.
1502 * The 68k instruction is returned in exploded form, since we have no
1503 * knowledge of how you parse (or evaluate) your expressions.
1504 * We do however strip off and decode addressing modes and operation
1507 * This function's value is a string. If it is not "" then an internal
1508 * logic error was found: read this code to assign meaning to the string.
1509 * No argument string should generate such an error string:
1510 * it means a bug in our code, not in the user's text.
1512 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1516 /* JF this function no longer returns a useful value. Sorry */
1522 register struct m68k_op
*opP
;
1523 register struct m68k_incant
*opcode
;
1525 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1526 char *pdot
, *pdotmove
;
1531 char *crack_operand ();
1532 LITTLENUM_TYPE words
[6];
1533 LITTLENUM_TYPE
*wordp
;
1534 unsigned long ok_arch
= 0;
1536 if (*instring
== ' ')
1537 instring
++; /* skip leading whitespace */
1539 /* Scan up to end of operation-code, which MUST end in end-of-string
1540 or exactly 1 space. */
1542 for (p
= instring
; *p
!= '\0'; p
++)
1552 the_ins
.error
= "No operator";
1553 the_ins
.opcode
[0] = 0;
1554 /* the_ins.numo=1; */
1558 /* p now points to the end of the opcode name, probably whitespace.
1559 make sure the name is null terminated by clobbering the whitespace,
1560 look it up in the hash table, then fix it back.
1561 Remove a dot, first, since the opcode tables have none. */
1564 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1565 *pdotmove
= pdotmove
[1];
1571 opcode
= (struct m68k_incant
*) hash_find (op_hash
, instring
);
1576 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1577 *pdotmove
= pdotmove
[-1];
1584 the_ins
.error
= "Unknown operator";
1585 the_ins
.opcode
[0] = 0;
1586 /* the_ins.numo=1; */
1590 /* found a legitimate opcode, start matching operands */
1595 if (opcode
->m_operands
== 0)
1597 char *old
= input_line_pointer
;
1599 input_line_pointer
= p
;
1600 /* Ahh - it's a motorola style psuedo op */
1601 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1602 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1603 input_line_pointer
= old
;
1609 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1612 p
= crack_operand (p
, opP
);
1616 the_ins
.error
= opP
->error
;
1621 opsfound
= opP
- &the_ins
.operands
[0];
1623 /* This ugly hack is to support the floating pt opcodes in their standard form */
1624 /* Essentially, we fake a first enty of type COP#1 */
1625 if (opcode
->m_operands
[0] == 'I')
1629 for (n
= opsfound
; n
> 0; --n
)
1630 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1632 memset ((char *) (&the_ins
.operands
[0]), '\0', sizeof (the_ins
.operands
[0]));
1633 the_ins
.operands
[0].mode
= MSCR
;
1634 the_ins
.operands
[0].reg
= COPNUM
; /* COP #1 */
1638 /* We've got the operands. Find an opcode that'll accept them */
1641 /* If we didn't get the right number of ops, or we have no
1642 common model with this pattern then reject this pattern. */
1644 if (opsfound
!= opcode
->m_opnum
1645 || ((opcode
->m_arch
& current_architecture
) == 0))
1648 ok_arch
|= opcode
->m_arch
;
1652 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0]; *s
&& !losing
; s
+= 2, opP
++)
1654 /* Warning: this switch is huge! */
1655 /* I've tried to organize the cases into this order:
1656 non-alpha first, then alpha by letter. Lower-case
1657 goes directly before uppercase counterpart. */
1658 /* Code with multiple case ...: gets sorted by the lowest
1659 case ... it belongs to. I hope this makes sense. */
1663 if (opP
->mode
== MSCR
|| opP
->mode
== IMMED
1664 || opP
->mode
== DREG
|| opP
->mode
== AREG
1665 || opP
->mode
== AINC
|| opP
->mode
== ADEC
1666 || opP
->mode
== REGLST
)
1688 if (opP
->mode
!= IMMED
)
1694 t
= get_num (opP
->con1
, 80);
1695 if (s
[1] == 'b' && !isbyte (t
))
1697 else if (s
[1] == 'w' && !isword (t
))
1704 if (opP
->mode
!= IMMED
)
1709 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1710 opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1715 if (opP
->mode
== MSCR
|| opP
->reg
== PC
||
1716 opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1722 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1723 opP
->mode
== AREG
|| opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
||
1724 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== REGLST
)
1729 if (opP
->mode
== MSCR
|| opP
->mode
== REGLST
)
1734 if (opP
->mode
!= AINC
)
1739 if (opP
->mode
!= ADEC
)
1744 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1745 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== IMMED
|| opP
->mode
== REGLST
)
1750 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
|| opP
->mode
== REGLST
)
1755 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1756 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== IMMED
|| opP
->reg
== PC
||
1757 opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1762 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1763 opP
->mode
== IMMED
|| opP
->mode
== REGLST
)
1767 case '~': /* For now! (JF FOO is this right?) */
1768 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1769 opP
->mode
== AREG
|| opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1774 if (opP
->mode
!= MSCR
|| (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1779 if (opP
->mode
!= AREG
)
1783 if (opP
->mode
!= AINDR
)
1786 } /* if not address register indirect */
1789 if (opP
->mode
!= ABSL
|| (flagseen
['S'] && instring
[0] == 'j'
1790 && instring
[1] == 'b'
1791 && instring
[2] == 's'
1792 && instring
[3] == 'r'))
1797 if (opP
->mode
!= MSCR
|| opP
->reg
!= CCR
)
1801 case 'd': /* FOO This mode is a KLUDGE!! */
1802 if (opP
->mode
!= AOFF
&& (opP
->mode
!= ABSL
||
1803 opP
->con1
->e_beg
[0] != '(' || opP
->con1
->e_end
[0] != ')'))
1808 if (opP
->mode
!= DREG
)
1813 if (opP
->mode
!= MSCR
|| opP
->reg
< (FPREG
+ 0) || opP
->reg
> (FPREG
+ 7))
1818 if (opP
->mode
!= MSCR
|| opP
->reg
< COPNUM
||
1819 opP
->reg
>= COPNUM
+ 7)
1824 if (opP
->mode
!= MSCR
1827 || cpu_of_arch (current_architecture
) < m68010
/* before 68010 had none */
1828 || (cpu_of_arch (current_architecture
) < m68020
1832 && opP
->reg
!= VBR
) /* 68010's had only these */
1833 || (cpu_of_arch (current_architecture
) < m68040
1841 && opP
->reg
!= ISP
) /* 680[23]0's have only these */
1842 || (cpu_of_arch (current_architecture
) == m68040
/* 68040 has all but this */
1843 && opP
->reg
== CAAR
))
1846 } /* doesn't cut it */
1850 if (opP
->mode
!= IMMED
)
1856 if (opP
->mode
== DREG
|| opP
->mode
== AREG
|| opP
->mode
== FPREG
)
1863 opP
->reg
= 1 << (opP
->reg
- DATA
);
1866 else if (opP
->mode
!= REGLST
)
1870 else if (s
[1] == '8' && opP
->reg
& 0x0FFffFF)
1872 else if (s
[1] == '3' && opP
->reg
& 0x7000000)
1877 if (opP
->mode
!= IMMED
)
1883 t
= get_num (opP
->con1
, 0);
1885 || isvar (opP
->con1
))
1891 if (opP
->mode
!= DREG
&& opP
->mode
!= IMMED
)
1896 if (opP
->mode
!= IMMED
)
1902 t
= get_num (opP
->con1
, 80);
1903 if (t
< 1 || t
> 8 || isvar (opP
->con1
))
1909 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1914 if (opP
->mode
!= AINDR
&& opP
->mode
!= DINDR
)
1919 if (opP
->mode
!= MSCR
|| !(opP
->reg
== FPI
|| opP
->reg
== FPS
|| opP
->reg
== FPC
))
1924 if (opP
->mode
!= MSCR
|| opP
->reg
!= SR
)
1929 if (opP
->mode
!= IMMED
)
1933 long t
= get_num (opP
->con1
, 80);
1934 if (t
< 0 || t
> 7 || isvar (opP
->con1
))
1940 if (opP
->mode
!= MSCR
|| opP
->reg
!= USP
)
1944 /* JF these are out of order. We could put them
1945 in order if we were willing to put up with
1946 bunches of #ifdef m68851s in the code.
1948 Don't forget that you need these operands
1949 to use 68030 MMU instructions. */
1951 /* Memory addressing mode used by pflushr */
1953 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1954 opP
->mode
== AREG
|| opP
->mode
== REGLST
)
1959 if (opP
->mode
!= MSCR
|| (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1964 if (opP
->mode
!= MSCR
1965 || (opP
->reg
!= TC
&& opP
->reg
!= CAL
1966 && opP
->reg
!= VAL
&& opP
->reg
!= SCC
&& opP
->reg
!= AC
))
1971 if (opP
->reg
!= VAL
)
1976 if (opP
->mode
!= MSCR
1977 || (opP
->reg
!= DRP
&& opP
->reg
!= SRP
1978 && opP
->reg
!= CRP
))
1983 if (opP
->mode
!= MSCR
||
1984 (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7) &&
1985 !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1990 if (opP
->reg
!= PSR
)
1995 if (opP
->reg
!= PCSR
)
2006 } /* not a cache specifier. */
2010 if (opP
->mode
!= ABSL
)
2013 } /* not absolute */
2017 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2018 *s
, __LINE__
, __FILE__
);
2019 } /* switch on type of operand */
2023 } /* for each operand */
2024 } /* if immediately wrong */
2031 opcode
= opcode
->m_next
;
2036 && !(ok_arch
& current_architecture
))
2040 strcpy (buf
, "invalid instruction for this architecture; needs ");
2041 cp
= buf
+ strlen (buf
);
2045 strcpy (cp
, "fpu (68040 or 68881/68882)");
2048 strcpy (cp
, "mmu (68030 or 68851)");
2051 strcpy (cp
, "68020 or higher");
2054 strcpy (cp
, "68000 or higher");
2057 strcpy (cp
, "68010 or higher");
2061 int got_one
= 0, idx
;
2069 { m68000
, "68000" },
2070 { m68010
, "68010" },
2071 { m68020
, "68020" },
2072 { m68030
, "68030" },
2073 { m68040
, "68040" },
2075 { m68881
, "68881" },
2078 for (idx
= 0; idx
< sizeof (archs
) / sizeof (archs
[0]); idx
++)
2080 if (archs
[idx
].arch
& ok_arch
)
2084 strcpy (cp
, " or ");
2088 strcpy (cp
, archs
[idx
].name
);
2100 the_ins
.error
= "operands mismatch";
2102 } /* Fell off the end */
2107 /* now assemble it */
2109 the_ins
.args
= opcode
->m_operands
;
2110 the_ins
.numargs
= opcode
->m_opnum
;
2111 the_ins
.numo
= opcode
->m_codenum
;
2112 the_ins
.opcode
[0] = getone (opcode
);
2113 the_ins
.opcode
[1] = gettwo (opcode
);
2115 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2117 /* This switch is a doozy.
2118 Watch the first step; its a big one! */
2139 tmpreg
= 0x3c; /* 7.4 */
2140 if (strchr ("bwl", s
[1]))
2141 nextword
= get_num (opP
->con1
, 80);
2143 nextword
= get_num (opP
->con1
, 0);
2144 if (isvar (opP
->con1
))
2145 add_fix (s
[1], opP
->con1
, 0);
2149 if (!isbyte (nextword
))
2150 opP
->error
= "operand out of range";
2155 if (!isword (nextword
))
2156 opP
->error
= "operand out of range";
2161 addword (nextword
>> 16);
2183 as_fatal ("Internal error: Can't decode %c%c in line %d of file \"%s\"",
2184 *s
, s
[1], __LINE__
, __FILE__
);
2189 /* We gotta put out some float */
2190 if (op (opP
->con1
) != O_big
)
2195 /* Can other cases happen here? */
2196 if (op (opP
->con1
) != O_constant
)
2199 val
= (valueT
) offs (opP
->con1
);
2203 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2204 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2208 offs (opP
->con1
) = gencnt
;
2210 if (offs (opP
->con1
) > 0)
2212 if (offs (opP
->con1
) > baseo
)
2214 as_warn ("Bignum too big for %c format; truncated", s
[1]);
2215 offs (opP
->con1
) = baseo
;
2217 baseo
-= offs (opP
->con1
);
2220 for (wordp
= generic_bignum
+ offs (opP
->con1
) - 1; offs (opP
->con1
)--; --wordp
)
2224 gen_to_words (words
, baseo
, (long) outro
);
2225 for (wordp
= words
; baseo
--; wordp
++)
2229 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2232 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2235 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2238 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2241 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2245 nextword
= get_num (opP
->con1
, 80);
2246 /* Force into index mode. Hope this works */
2248 /* We do the first bit for 32-bit displacements, and the
2249 second bit for 16 bit ones. It is possible that we
2250 should make the default be WORD instead of LONG, but
2251 I think that'd break GCC, so we put up with a little
2252 inefficiency for the sake of working output. */
2254 if (!issword (nextword
)
2255 || (isvar (opP
->con1
)
2256 && ((opP
->con1
->e_siz
== 0
2257 && flagseen
['l'] == 0)
2258 || opP
->con1
->e_siz
== 3)))
2262 tmpreg
= 0x3B; /* 7.3 */
2264 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2265 if (isvar (opP
->con1
))
2270 add_fix ('l', opP
->con1
, 1);
2271 addword (0), addword (0);
2277 add_fix ('l', opP
->con1
, 0);
2282 addword (nextword
>> 16);
2287 tmpreg
= 0x3A; /* 7.2 */
2289 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2291 if (isvar (opP
->con1
))
2295 add_fix ('w', opP
->con1
, 1);
2298 add_fix ('w', opP
->con1
, 0);
2307 know (current_architecture
& m68020up
);
2308 /* intentional fall-through */
2311 baseo
= get_num (opP
->con1
, 80);
2312 outro
= get_num (opP
->con2
, 80);
2313 /* Figure out the `addressing mode'.
2314 Also turn on the BASE_DISABLE bit, if needed. */
2315 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2317 tmpreg
= 0x3b;/* 7.3 */
2318 if (opP
->reg
== ZPC
)
2321 else if (opP
->reg
== FAIL
)
2324 tmpreg
= 0x30;/* 6.garbage */
2327 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2329 siz1
= (opP
->con1
) ? opP
->con1
->e_siz
: 0;
2330 siz2
= (opP
->con2
) ? opP
->con2
->e_siz
: 0;
2332 /* Index register stuff */
2333 if (opP
->ireg
>= DATA
+ 0 && opP
->ireg
<= ADDR
+ 7)
2335 nextword
|= (opP
->ireg
- DATA
) << 12;
2337 if (opP
->isiz
== 0 || opP
->isiz
== 3)
2353 as_fatal ("failed sanity check.");
2356 GET US OUT OF HERE! */
2358 /* Must be INDEX, with an index
2359 register. Address register
2360 cannot be ZERO-PC, and either
2361 :b was forced, or we know
2363 if (opP
->mode
== AINDX
2368 && !isvar (opP
->con1
))))
2370 nextword
+= baseo
& 0xff;
2372 if (isvar (opP
->con1
))
2373 add_fix ('B', opP
->con1
, 0);
2378 nextword
|= 0x40; /* No index reg */
2380 /* It isn't simple. */
2382 /* If the guy specified a width, we assume that it is
2383 wide enough. Maybe it isn't. If so, we lose. */
2387 if (isvar (opP
->con1
) || !issword (baseo
))
2392 else if (baseo
== 0)
2401 as_warn ("Byte dispacement won't work. Defaulting to :w");
2410 /* Figure out innner displacement stuff */
2411 if (opP
->mode
!= AINDX
)
2416 if (isvar (opP
->con2
) || !issword (outro
))
2421 else if (outro
== 0)
2430 as_warn ("Byte dispacement won't work. Defaulting to :w");
2438 if (opP
->mode
== APODX
)
2440 else if (opP
->mode
== AMIND
)
2445 if (isvar (opP
->con1
))
2447 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2449 opP
->con1
->e_exp
.X_add_number
+= 6;
2450 add_fix (siz1
== 3 ? 'l' : 'w', opP
->con1
, 1);
2453 add_fix (siz1
== 3 ? 'l' : 'w', opP
->con1
, 0);
2456 addword (baseo
>> 16);
2460 if (isvar (opP
->con2
))
2462 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2464 opP
->con1
->e_exp
.X_add_number
+= 6;
2465 add_fix (siz2
== 3 ? 'l' : 'w', opP
->con2
, 1);
2468 add_fix (siz2
== 3 ? 'l' : 'w', opP
->con2
, 0);
2471 addword (outro
>> 16);
2478 nextword
= get_num (opP
->con1
, 80);
2479 switch (opP
->con1
->e_siz
)
2482 as_warn ("Unknown size for absolute reference");
2484 if (!isvar (opP
->con1
) && issword (offs (opP
->con1
)))
2486 tmpreg
= 0x38; /* 7.0 */
2490 /* Don't generate pc relative code on 68010 and
2492 if (isvar (opP
->con1
)
2493 && !subs (opP
->con1
)
2494 && seg (opP
->con1
) == text_section
2495 && now_seg
== text_section
2496 && cpu_of_arch (current_architecture
) >= m68020
2498 && !strchr ("~%&$?", s
[0]))
2500 tmpreg
= 0x3A; /* 7.2 */
2501 add_frag (adds (opP
->con1
),
2503 TAB (PCREL
, SZ_UNDEF
));
2506 case 3: /* Fall through into long */
2507 if (isvar (opP
->con1
))
2508 add_fix ('l', opP
->con1
, 0);
2510 tmpreg
= 0x39;/* 7.1 mode */
2511 addword (nextword
>> 16);
2516 if (isvar (opP
->con1
))
2517 add_fix ('w', opP
->con1
, 0);
2519 tmpreg
= 0x38;/* 7.0 mode */
2525 as_bad ("invalid indirect register");
2529 as_bad ("unknown/incorrect operand");
2532 install_gen_operand (s
[1], tmpreg
);
2538 { /* JF: I hate floating point! */
2553 tmpreg
= get_num (opP
->con1
, tmpreg
);
2554 if (isvar (opP
->con1
))
2555 add_fix (s
[1], opP
->con1
, 0);
2558 case 'b': /* Danger: These do no check for
2559 certain types of overflow.
2561 if (!isbyte (tmpreg
))
2562 opP
->error
= "out of range";
2563 insop (tmpreg
, opcode
);
2564 if (isvar (opP
->con1
))
2565 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2568 if (!isword (tmpreg
))
2569 opP
->error
= "out of range";
2570 insop (tmpreg
, opcode
);
2571 if (isvar (opP
->con1
))
2572 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2575 /* Because of the way insop works, we put these two out
2577 insop (tmpreg
, opcode
);
2578 insop (tmpreg
>> 16, opcode
);
2579 if (isvar (opP
->con1
))
2580 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2586 install_operand (s
[1], tmpreg
);
2589 as_fatal ("Internal error: Unknown mode #%c in line %d of file \"%s\"", s
[1], __LINE__
, __FILE__
);
2597 install_operand (s
[1], opP
->reg
- ADDR
);
2601 tmpreg
= get_num (opP
->con1
, 80);
2605 /* Needs no offsetting */
2606 add_fix ('B', opP
->con1
, 1);
2609 /* Offset the displacement to be relative to byte disp location */
2610 opP
->con1
->e_exp
.X_add_number
+= 2;
2611 add_fix ('w', opP
->con1
, 1);
2616 if (cpu_of_arch (current_architecture
) < m68020
) /* 68000 or 010 */
2617 as_warn ("Can't use long branches on 68000/68010");
2618 the_ins
.opcode
[the_ins
.numo
- 1] |= 0xff;
2619 /* Offset the displacement to be relative to byte disp location */
2620 opP
->con1
->e_exp
.X_add_number
+= 4;
2621 add_fix ('l', opP
->con1
, 1);
2626 if (subs (opP
->con1
)) /* We can't relax it */
2629 /* This could either be a symbol, or an
2630 absolute address. No matter, the
2631 frag hacking will finger it out.
2632 Not quite: it can't switch from
2633 BRANCH to BCC68000 for the case
2634 where opnd is absolute (it needs
2635 to use the 68000 hack since no
2636 conditional abs jumps). */
2637 if (((cpu_of_arch (current_architecture
) < m68020
) || (0 == adds (opP
->con1
)))
2638 && (the_ins
.opcode
[0] >= 0x6200)
2639 && (the_ins
.opcode
[0] <= 0x6f00))
2641 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (BCC68000
, SZ_UNDEF
));
2645 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (ABRANCH
, SZ_UNDEF
));
2649 if (isvar (opP
->con1
))
2652 /* check for DBcc instruction */
2653 if ((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2655 /* size varies if patch */
2656 /* needed for long form */
2657 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (DBCC
, SZ_UNDEF
));
2662 opP
->con1
->e_exp
.X_add_number
+= 2;
2663 add_fix ('w', opP
->con1
, 1);
2667 case 'C': /* Fixed size LONG coproc branches */
2668 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2669 /* Offset the displacement to be relative to byte disp location */
2670 /* Coproc branches don't have a byte disp option, but they are
2671 compatible with the ordinary branches, which do... */
2672 opP
->con1
->e_exp
.X_add_number
+= 4;
2673 add_fix ('l', opP
->con1
, 1);
2677 case 'c': /* Var size Coprocesssor branches */
2678 if (subs (opP
->con1
))
2680 add_fix ('l', opP
->con1
, 1);
2681 add_frag ((symbolS
*) 0, (long) 0, TAB (FBRANCH
, LONG
));
2683 else if (adds (opP
->con1
))
2685 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (FBRANCH
, SZ_UNDEF
));
2689 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2690 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2691 add_fix ('l', opP
->con1
, 1);
2697 as_fatal ("Internal error: operand type B%c unknown in line %d of file \"%s\"",
2698 s
[1], __LINE__
, __FILE__
);
2702 case 'C': /* Ignore it */
2705 case 'd': /* JF this is a kludge */
2706 if (opP
->mode
== AOFF
)
2708 install_operand ('s', opP
->reg
- ADDR
);
2714 tmpP
= opP
->con1
->e_end
- 2;
2716 opP
->con1
->e_end
-= 4; /* point to the , */
2717 baseo
= m68k_reg_parse (&tmpP
);
2718 if (baseo
< ADDR
+ 0 || baseo
> ADDR
+ 7)
2720 as_bad ("Unknown address reg, using A0");
2725 install_operand ('s', baseo
);
2727 tmpreg
= get_num (opP
->con1
, 80);
2728 if (!issword (tmpreg
))
2730 as_warn ("Expression out of range, using 0");
2737 install_operand (s
[1], opP
->reg
- DATA
);
2741 install_operand (s
[1], opP
->reg
- FPREG
);
2745 tmpreg
= 1 + opP
->reg
- COPNUM
;
2748 install_operand (s
[1], tmpreg
);
2751 case 'J': /* JF foo */
2804 as_fatal ("failed sanity check.");
2806 install_operand (s
[1], tmpreg
);
2810 tmpreg
= get_num (opP
->con1
, 55);
2811 install_operand (s
[1], tmpreg
& 0x7f);
2818 if (tmpreg
& 0x7FF0000)
2819 as_bad ("Floating point register in register list");
2820 insop (reverse_16_bits (tmpreg
), opcode
);
2824 if (tmpreg
& 0x700FFFF)
2825 as_bad ("Wrong register in floating-point reglist");
2826 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2834 if (tmpreg
& 0x7FF0000)
2835 as_bad ("Floating point register in register list");
2836 insop (tmpreg
, opcode
);
2838 else if (s
[1] == '8')
2840 if (tmpreg
& 0x0FFFFFF)
2841 as_bad ("incorrect register in reglist");
2842 install_operand (s
[1], tmpreg
>> 24);
2846 if (tmpreg
& 0x700FFFF)
2847 as_bad ("wrong register in floating-point reglist");
2849 install_operand (s
[1], tmpreg
>> 16);
2854 install_operand (s
[1], get_num (opP
->con1
, 60));
2858 tmpreg
= (opP
->mode
== DREG
)
2859 ? 0x20 + opP
->reg
- DATA
2860 : (get_num (opP
->con1
, 40) & 0x1F);
2861 install_operand (s
[1], tmpreg
);
2865 tmpreg
= get_num (opP
->con1
, 10);
2868 install_operand (s
[1], tmpreg
);
2873 /* This depends on the fact that ADDR registers are
2874 eight more than their corresponding DATA regs, so
2875 the result will have the ADDR_REG bit set */
2876 install_operand (s
[1], opP
->reg
- DATA
);
2880 if (opP
->reg
== FPI
)
2882 else if (opP
->reg
== FPS
)
2884 else if (opP
->reg
== FPC
)
2887 as_fatal ("failed sanity check.");
2888 install_operand (s
[1], tmpreg
);
2891 case 'S': /* Ignore it */
2895 install_operand (s
[1], get_num (opP
->con1
, 30));
2898 case 'U': /* Ignore it */
2917 as_fatal ("failed sanity check");
2918 } /* switch on cache token */
2919 install_operand (s
[1], tmpreg
);
2922 /* JF: These are out of order, I fear. */
2933 as_fatal ("failed sanity check.");
2935 install_operand (s
[1], tmpreg
);
2957 as_fatal ("failed sanity check.");
2959 install_operand (s
[1], tmpreg
);
2963 if (opP
->reg
== VAL
)
2965 as_fatal ("failed sanity check.");
2981 as_fatal ("failed sanity check.");
2983 install_operand (s
[1], tmpreg
);
2997 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3008 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3012 as_fatal ("failed sanity check.");
3014 install_operand (s
[1], tmpreg
);
3017 know (opP
->reg
== PSR
);
3020 know (opP
->reg
== PCSR
);
3033 as_fatal ("failed sanity check");
3035 install_operand (s
[1], tmpreg
);
3038 tmpreg
= get_num (opP
->con1
, 20);
3039 install_operand (s
[1], tmpreg
);
3041 case '_': /* used only for move16 absolute 32-bit address */
3042 tmpreg
= get_num (opP
->con1
, 80);
3043 addword (tmpreg
>> 16);
3044 addword (tmpreg
& 0xFFFF);
3047 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3048 s
[0], __LINE__
, __FILE__
);
3052 /* By the time whe get here (FINALLY) the_ins contains the complete
3053 instruction, ready to be emitted. . . */
3057 * get_regs := '/' + ?
3058 * | '-' + <register>
3059 * | '-' + <register> + ?
3064 * The idea here must be to scan in a set of registers but I don't
3065 * understand it. Looks awfully sloppy to me but I don't have any doc on
3073 get_regs (i
, str
, opP
)
3075 struct m68k_op
*opP
;
3078 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3079 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3080 unsigned long cur_regs
= 0;
3083 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3084 else if(x==FPS) cur_regs|=(1<<25);\
3085 else if(x==FPC) cur_regs|=(1<<26);\
3086 else cur_regs|=(1<<(x-1)); }
3096 else if (*str
== '-')
3099 reg2
= m68k_reg_parse (&str
);
3100 if (reg2
< DATA
|| reg2
>= FPREG
+ 8 || reg1
== FPI
|| reg1
== FPS
|| reg1
== FPC
)
3102 opP
->error
= "unknown register in register list";
3105 while (reg1
<= reg2
)
3113 else if (*str
== '\0')
3120 opP
->error
= "unknow character in register list";
3123 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3126 reg1
= m68k_reg_parse (&str
);
3127 if ((reg1
< DATA
|| reg1
>= FPREG
+ 8) && !(reg1
== FPI
|| reg1
== FPS
|| reg1
== FPC
))
3129 opP
->error
= "unknown register in register list";
3133 opP
->reg
= cur_regs
;
3138 reverse_16_bits (in
)
3144 static int mask
[16] =
3146 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3147 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3149 for (n
= 0; n
< 16; n
++)
3152 out
|= mask
[15 - n
];
3155 } /* reverse_16_bits() */
3164 static int mask
[8] =
3166 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3169 for (n
= 0; n
< 8; n
++)
3175 } /* reverse_8_bits() */
3178 install_operand (mode
, val
)
3185 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
3188 the_ins
.opcode
[0] |= val
<< 9;
3191 the_ins
.opcode
[1] |= val
<< 12;
3194 the_ins
.opcode
[1] |= val
<< 6;
3197 the_ins
.opcode
[1] |= val
;
3200 the_ins
.opcode
[2] |= val
<< 12;
3203 the_ins
.opcode
[2] |= val
<< 6;
3206 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3207 three words long! */
3209 the_ins
.opcode
[2] |= val
;
3212 the_ins
.opcode
[1] |= val
<< 7;
3215 the_ins
.opcode
[1] |= val
<< 10;
3219 the_ins
.opcode
[1] |= val
<< 5;
3224 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3227 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3230 the_ins
.opcode
[0] |= val
= 0xff;
3233 the_ins
.opcode
[0] |= val
<< 9;
3236 the_ins
.opcode
[1] |= val
;
3239 the_ins
.opcode
[1] |= val
;
3240 the_ins
.numo
++; /* What a hack */
3243 the_ins
.opcode
[1] |= val
<< 4;
3250 the_ins
.opcode
[0] |= (val
<< 6);
3253 the_ins
.opcode
[1] = (val
>> 16);
3254 the_ins
.opcode
[2] = val
& 0xffff;
3258 as_fatal ("failed sanity check.");
3260 } /* install_operand() */
3263 install_gen_operand (mode
, val
)
3270 the_ins
.opcode
[0] |= val
;
3273 /* This is a kludge!!! */
3274 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3283 the_ins
.opcode
[0] |= val
;
3285 /* more stuff goes here */
3287 as_fatal ("failed sanity check.");
3289 } /* install_gen_operand() */
3292 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3293 * then deal with the bitfield hack.
3297 crack_operand (str
, opP
)
3299 register struct m68k_op
*opP
;
3301 register int parens
;
3303 register char *beg_str
;
3310 for (parens
= 0; *str
&& (parens
> 0 || notend (str
)); str
++)
3314 else if (*str
== ')')
3318 opP
->error
= "Extra )";
3324 if (!*str
&& parens
)
3326 opP
->error
= "Missing )";
3331 if (m68k_ip_op (beg_str
, opP
) == FAIL
)
3338 c
= *++str
; /* JF bitfield hack */
3343 as_bad ("Missing operand");
3348 /* See the comment up above where the #define notend(... is */
3355 if (*s
== '{' || *s
== '}')
3359 /* This kludge here is for the division cmd, which is a kludge */
3360 if (index ("aAdD#", s
[1]))
3367 /* This is the guts of the machine-dependent assembler. STR points to a
3368 machine dependent instruction. This function is supposed to emit
3369 the frags/bytes it assembles to.
3373 insert_reg (regname
, regnum
)
3381 #ifdef REGISTER_PREFIX
3382 buf
[0] = REGISTER_PREFIX
;
3383 strcpy (buf
+ 1, regname
);
3387 symbol_table_insert (s
= symbol_new (regname
, reg_section
, regnum
, &zero_address_frag
));
3389 verify_symbol_chain_2 (s
);
3391 for (i
= 0; regname
[i
]; i
++)
3392 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
3395 symbol_table_insert (s
= symbol_new (buf
, reg_section
, regnum
, &zero_address_frag
));
3396 verify_symbol_chain_2 (s
);
3405 static const struct init_entry init_table
[] =
3507 /* 68ec030 versions of same */
3510 /* 68ec030 access control unit, identical to 030 MMU status reg */
3520 for (i
= 0; init_table
[i
].name
; i
++)
3521 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3524 static int no_68851
, no_68881
;
3527 /* a.out machine type. Default to 68020. */
3528 int m68k_aout_machtype
= 2;
3540 int shorts_this_frag
;
3541 static int done_first_time
;
3543 if (!done_first_time
)
3545 done_first_time
= 1;
3547 if (cpu_of_arch (current_architecture
) == 0)
3551 if (strcmp (TARGET_CPU
, "m68000") == 0
3552 || strcmp (TARGET_CPU
, "m68302") == 0)
3554 else if (strcmp (TARGET_CPU
, "m68010") == 0)
3556 else if (strcmp (TARGET_CPU
, "m68020") == 0
3557 || strcmp (TARGET_CPU
, "m68k") == 0)
3559 else if (strcmp (TARGET_CPU
, "m68030") == 0)
3561 else if (strcmp (TARGET_CPU
, "m68040") == 0)
3563 else if (strcmp (TARGET_CPU
, "cpu32") == 0
3564 || strcmp (TARGET_CPU
, "m68331") == 0
3565 || strcmp (TARGET_CPU
, "m68332") == 0
3566 || strcmp (TARGET_CPU
, "m68333") == 0
3567 || strcmp (TARGET_CPU
, "m68340") == 0)
3572 current_architecture
|= cpu_type
;
3574 #if 0 /* Could be doing emulation. */
3575 if (current_architecture
& m68881
)
3577 if (current_architecture
& m68000
)
3578 as_bad ("incompatible processors 68000 and 68881/2 specified");
3579 if (current_architecture
& m68010
)
3580 as_bad ("incompatible processors 68010 and 68881/2 specified");
3581 if (current_architecture
& m68040
)
3582 as_bad ("incompatible processors 68040 and 68881/2 specified");
3585 /* What other incompatibilities could we check for? */
3587 /* Toss in some default assumptions about coprocessors. */
3589 && (cpu_of_arch (current_architecture
)
3590 /* Can CPU32 have a 68881 coprocessor?? */
3591 & (m68020
| m68030
| cpu32
)))
3593 current_architecture
|= m68881
;
3596 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
3597 && cpu_of_arch (current_architecture
) != m68040
)
3599 current_architecture
|= m68851
;
3601 if (no_68881
&& (current_architecture
& m68881
))
3602 as_bad ("options for 68881 and no-68881 both given");
3603 if (no_68851
&& (current_architecture
& m68851
))
3604 as_bad ("options for 68851 and no-68851 both given");
3607 /* Work out the magic number. This isn't very general. */
3608 if (current_architecture
& m68000
)
3609 m68k_aout_machtype
= 0;
3610 else if (current_architecture
& m68010
)
3611 m68k_aout_machtype
= 1;
3612 else if (current_architecture
& m68020
)
3613 m68k_aout_machtype
= 2;
3615 m68k_aout_machtype
= 2;
3619 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3624 for (n
= the_ins
.numargs
; n
; --n
)
3625 if (the_ins
.operands
[n
].error
)
3627 er
= the_ins
.operands
[n
].error
;
3633 as_bad ("%s -- statement `%s' ignored", er
, str
);
3637 if (the_ins
.nfrag
== 0)
3639 /* No frag hacking involved; just put it out */
3640 toP
= frag_more (2 * the_ins
.numo
);
3641 fromP
= &the_ins
.opcode
[0];
3642 for (m
= the_ins
.numo
; m
; --m
)
3644 md_number_to_chars (toP
, (long) (*fromP
), 2);
3648 /* put out symbol-dependent info */
3649 for (m
= 0; m
< the_ins
.nrel
; m
++)
3651 switch (the_ins
.reloc
[m
].wid
)
3669 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3670 the_ins
.reloc
[m
].wid
);
3673 fix_new_exp (frag_now
,
3674 ((toP
- frag_now
->fr_literal
)
3675 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3677 &the_ins
.reloc
[m
].exp
,
3678 the_ins
.reloc
[m
].pcrel
,
3684 /* There's some frag hacking */
3685 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3690 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3692 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3693 toP
= frag_more (wid
);
3695 shorts_this_frag
= 0;
3696 for (m
= wid
/ 2; m
; --m
)
3698 md_number_to_chars (toP
, (long) (*fromP
), 2);
3703 for (m
= 0; m
< the_ins
.nrel
; m
++)
3705 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3707 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3710 wid
= the_ins
.reloc
[m
].wid
;
3713 the_ins
.reloc
[m
].wid
= 0;
3714 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3716 fix_new_exp (frag_now
,
3717 ((toP
- frag_now
->fr_literal
)
3718 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
3720 &the_ins
.reloc
[m
].exp
,
3721 the_ins
.reloc
[m
].pcrel
,
3724 (void) frag_var (rs_machine_dependent
, 10, 0,
3725 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3726 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3728 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3729 shorts_this_frag
= 0;
3732 toP
= frag_more (n
* sizeof (short));
3735 md_number_to_chars (toP
, (long) (*fromP
), 2);
3741 for (m
= 0; m
< the_ins
.nrel
; m
++)
3745 wid
= the_ins
.reloc
[m
].wid
;
3748 the_ins
.reloc
[m
].wid
= 0;
3749 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3751 fix_new_exp (frag_now
,
3752 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
3753 - shorts_this_frag
* 2),
3755 &the_ins
.reloc
[m
].exp
,
3756 the_ins
.reloc
[m
].pcrel
,
3761 /* See BREAK_UP_BIG_DECL definition, above. */
3762 static struct m68k_opcode
*
3766 #ifdef DO_BREAK_UP_BIG_DECL
3767 int lim1
= sizeof (m68k_opcodes
) / sizeof (m68k_opcodes
[0]);
3769 return m68k_opcodes_2
+ (i
- lim1
);
3771 return m68k_opcodes
+ i
;
3778 * md_begin -- set up hash tables with 68000 instructions.
3779 * similar to what the vax assembler does. ---phr
3781 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3782 a copy of it at runtime, adding in the information we want but isn't
3783 there. I think it'd be better to have an awk script hack the table
3784 at compile time. Or even just xstr the table and use it as-is. But
3785 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3788 register CONST
struct m68k_opcode
*ins
;
3789 register struct m68k_incant
*hack
, *slak
;
3790 register const char *retval
= 0; /* empty string, or error msg text */
3791 register unsigned int i
;
3794 if ((op_hash
= hash_new ()) == NULL
)
3795 as_fatal ("Virtual memory exhausted");
3797 obstack_begin (&robyn
, 4000);
3798 for (i
= 0; i
< numopcodes
; i
++)
3800 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3803 ins
= opcode_ptr (i
);
3804 /* We *could* ignore insns that don't match our arch here
3805 but just leaving them out of the hash. */
3806 slak
->m_operands
= ins
->args
;
3807 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
3808 slak
->m_arch
= ins
->arch
;
3809 slak
->m_opcode
= ins
->opcode
;
3810 /* This is kludgey */
3811 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
3812 if (i
+ 1 != numopcodes
3813 && !strcmp (ins
->name
, opcode_ptr (i
+ 1)->name
))
3815 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3820 slak
= slak
->m_next
;
3824 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
3825 /* Didn't his mommy tell him about null pointers? */
3827 as_bad ("Internal Error: Can't hash %s: %s", ins
->name
, retval
);
3830 for (i
= 0; i
< sizeof (mklower_table
); i
++)
3831 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
3833 for (i
= 0; i
< sizeof (notend_table
); i
++)
3835 notend_table
[i
] = 0;
3836 alt_notend_table
[i
] = 0;
3838 notend_table
[','] = 1;
3839 notend_table
['{'] = 1;
3840 notend_table
['}'] = 1;
3841 alt_notend_table
['a'] = 1;
3842 alt_notend_table
['A'] = 1;
3843 alt_notend_table
['d'] = 1;
3844 alt_notend_table
['D'] = 1;
3845 alt_notend_table
['#'] = 1;
3846 alt_notend_table
['f'] = 1;
3847 alt_notend_table
['F'] = 1;
3848 #ifdef REGISTER_PREFIX
3849 alt_notend_table
[REGISTER_PREFIX
] = 1;
3851 #ifdef OPTIONAL_REGISTER_PREFIX
3852 alt_notend_table
[OPTIONAL_REGISTER_PREFIX
] = 1;
3855 #ifndef MIT_SYNTAX_ONLY
3856 /* Insert pseudo ops, these have to go into the opcode table since
3857 gas expects pseudo ops to start with a dot */
3860 while (mote_pseudo_table
[n
].poc_name
)
3862 hack
= (struct m68k_incant
*)
3863 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3864 hash_insert (op_hash
,
3865 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
3866 hack
->m_operands
= 0;
3877 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3878 || (*s == ':' && strchr("aAdD#", s[1]))) \
3882 /* This funciton is called once, before the assembler exits. It is
3883 supposed to do any final cleanup for this part of the assembler.
3890 /* Equal to MAX_PRECISION in atof-ieee.c */
3891 #define MAX_LITTLENUMS 6
3893 /* Turn a string in input_line_pointer into a floating point constant of type
3894 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3895 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3898 md_atof (type
, litP
, sizeP
)
3904 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3905 LITTLENUM_TYPE
*wordP
;
3937 return "Bad call to MD_ATOF()";
3939 t
= atof_ieee (input_line_pointer
, type
, words
);
3941 input_line_pointer
= t
;
3943 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3944 for (wordP
= words
; prec
--;)
3946 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
3947 litP
+= sizeof (LITTLENUM_TYPE
);
3952 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3953 for use in the a.out file, and stores them in the array pointed to by buf.
3954 This knows about the endian-ness of the target machine and does
3955 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3956 2 (short) and 4 (long) Floating numbers are put out as a series of
3957 LITTLENUMS (shorts, here at least)
3960 md_number_to_chars (buf
, val
, n
)
3971 *buf
++ = (val
>> 8);
3975 *buf
++ = (val
>> 24);
3976 *buf
++ = (val
>> 16);
3977 *buf
++ = (val
>> 8);
3981 as_fatal ("failed sanity check.");
3986 md_apply_fix_2 (fixP
, val
)
3990 unsigned long upper_limit
;
3993 #ifdef IBM_COMPILER_SUX
3994 /* This is unnecessary but it convinces the native rs6000
3995 compiler to generate the code we want. */
3996 char *buf
= fixP
->fx_frag
->fr_literal
;
3997 buf
+= fixP
->fx_where
;
3998 #else /* IBM_COMPILER_SUX */
3999 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
4000 #endif /* IBM_COMPILER_SUX */
4002 switch (fixP
->fx_size
)
4007 lower_limit
= -0x80;
4010 *buf
++ = (val
>> 8);
4012 upper_limit
= 0x7fff;
4013 lower_limit
= -0x8000;
4016 *buf
++ = (val
>> 24);
4017 *buf
++ = (val
>> 16);
4018 *buf
++ = (val
>> 8);
4020 upper_limit
= 0x7fffffff;
4021 lower_limit
= -0x80000000;
4024 BAD_CASE (fixP
->fx_size
);
4027 /* For non-pc-relative values, it's conceivable we might get something
4028 like "0xff" for a byte field. So extend the upper part of the range
4029 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4030 so that we can do any range checking at all. */
4031 if (!fixP
->fx_pcrel
)
4032 upper_limit
= upper_limit
* 2 + 1;
4034 if ((unsigned) val
> upper_limit
&& (val
> 0 || val
< lower_limit
))
4035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "value out of range");
4037 /* A one byte PC-relative reloc means a short branch. We can't use
4038 a short branch with a value of 0 or -1, because those indicate
4039 different opcodes (branches with longer offsets). */
4041 && fixP
->fx_size
== 1
4042 && (fixP
->fx_addsy
== NULL
4043 || S_IS_DEFINED (fixP
->fx_addsy
))
4044 && (val
== 0 || val
== -1))
4045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, "invalid byte branch offset");
4048 #ifdef BFD_ASSEMBLER
4050 md_apply_fix (fixP
, valp
)
4054 md_apply_fix_2 (fixP
, *valp
);
4058 void md_apply_fix (fixP
, val
)
4062 md_apply_fix_2 (fixP
, val
);
4066 /* *fragP has been relaxed to its final size, and now needs to have
4067 the bytes inside it modified to conform to the new size There is UGLY
4071 md_convert_frag_1 (fragP
)
4072 register fragS
*fragP
;
4077 /* Address in object code of the displacement. */
4078 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4080 #ifdef IBM_COMPILER_SUX
4081 /* This is wrong but it convinces the native rs6000 compiler to
4082 generate the code we want. */
4083 register char *buffer_address
= fragP
->fr_literal
;
4084 buffer_address
+= fragP
->fr_fix
;
4085 #else /* IBM_COMPILER_SUX */
4086 /* Address in gas core of the place to store the displacement. */
4087 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4088 #endif /* IBM_COMPILER_SUX */
4090 /* No longer true: know(fragP->fr_symbol); */
4092 /* The displacement of the address, from current location. */
4093 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4094 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4096 switch (fragP
->fr_subtype
)
4098 case TAB (BCC68000
, BYTE
):
4099 case TAB (ABRANCH
, BYTE
):
4100 know (issbyte (disp
));
4102 as_bad ("short branch with zero offset: use :w");
4103 fragP
->fr_opcode
[1] = disp
;
4106 case TAB (DBCC
, SHORT
):
4107 know (issword (disp
));
4110 case TAB (BCC68000
, SHORT
):
4111 case TAB (ABRANCH
, SHORT
):
4112 know (issword (disp
));
4113 fragP
->fr_opcode
[1] = 0x00;
4116 case TAB (ABRANCH
, LONG
):
4117 if (cpu_of_arch (current_architecture
) < m68020
)
4119 if (fragP
->fr_opcode
[0] == 0x61)
4121 fragP
->fr_opcode
[0] = 0x4E;
4122 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4123 subseg_change (text_section
, 0); /* @@ */
4136 else if (fragP
->fr_opcode
[0] == 0x60)
4138 fragP
->fr_opcode
[0] = 0x4E;
4139 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4140 subseg_change (text_section
, 0); /* @@ */
4141 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4142 fragP
->fr_offset
, 0, NO_RELOC
);
4148 as_bad ("Long branch offset not supported.");
4153 fragP
->fr_opcode
[1] = (char) 0xff;
4157 case TAB (BCC68000
, LONG
):
4158 /* only Bcc 68000 instructions can come here */
4159 /* change bcc into b!cc/jmp absl long */
4160 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4161 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
4163 /* JF: these used to be fr_opcode[2,3], but they may be in a
4164 different frag, in which case refering to them is a no-no.
4165 Only fr_opcode[0,1] are guaranteed to work. */
4166 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4167 *buffer_address
++ = (char) 0xf9;
4168 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4169 subseg_change (text_section
, 0);
4170 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4171 fragP
->fr_offset
, 0, NO_RELOC
);
4175 case TAB (DBCC
, LONG
):
4176 /* only DBcc 68000 instructions can come here */
4177 /* change dbcc into dbcc/jmp absl long */
4178 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4179 *buffer_address
++ = 0x00; /* branch offset = 4 */
4180 *buffer_address
++ = 0x04;
4181 *buffer_address
++ = 0x60; /* put in bra pc+6 */
4182 *buffer_address
++ = 0x06;
4183 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4184 *buffer_address
++ = (char) 0xf9;
4186 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
4187 subseg_change (text_section
, 0);
4188 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4189 fragP
->fr_offset
, 0, NO_RELOC
);
4193 case TAB (FBRANCH
, SHORT
):
4194 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4197 case TAB (FBRANCH
, LONG
):
4198 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4201 case TAB (PCREL
, SHORT
):
4204 case TAB (PCREL
, LONG
):
4205 /* The thing to do here is force it to ABSOLUTE LONG, since
4206 PCREL is really trying to shorten an ABSOLUTE address anyway */
4207 /* JF FOO This code has not been tested */
4208 subseg_change (text_section
, 0);
4209 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, fragP
->fr_offset
,
4211 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4212 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4213 (unsigned) fragP
->fr_opcode
[0],
4214 (unsigned long) fragP
->fr_address
);
4215 fragP
->fr_opcode
[1] &= ~0x3F;
4216 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4220 case TAB (PCLEA
, SHORT
):
4221 subseg_change (text_section
, 0);
4222 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4223 fragP
->fr_offset
, 1, NO_RELOC
);
4224 fragP
->fr_opcode
[1] &= ~0x3F;
4225 fragP
->fr_opcode
[1] |= 0x3A;
4228 case TAB (PCLEA
, LONG
):
4229 subseg_change (text_section
, 0);
4230 fix_new (fragP
, (int) (fragP
->fr_fix
) + 2, 4, fragP
->fr_symbol
,
4231 fragP
->fr_offset
+ 2, 1, NO_RELOC
);
4232 *buffer_address
++ = 0x01;
4233 *buffer_address
++ = 0x70;
4241 md_number_to_chars (buffer_address
, (long) disp
, (int) ext
);
4242 fragP
->fr_fix
+= ext
;
4246 #ifndef BFD_ASSEMBLER
4249 md_convert_frag (headers
, fragP
)
4250 object_headers
*headers
;
4253 md_convert_frag_1 (fragP
);
4259 md_convert_frag (abfd
, sec
, fragP
)
4264 md_convert_frag_1 (fragP
);
4268 /* Force truly undefined symbols to their maximum size, and generally set up
4269 the frag list to be relaxed
4272 md_estimate_size_before_relax (fragP
, segment
)
4273 register fragS
*fragP
;
4277 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4279 old_fix
= fragP
->fr_fix
;
4281 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4282 switch (fragP
->fr_subtype
)
4285 case TAB (ABRANCH
, SZ_UNDEF
):
4287 if ((fragP
->fr_symbol
!= NULL
) /* Not absolute */
4288 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4290 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4293 else if ((fragP
->fr_symbol
== 0) || (cpu_of_arch (current_architecture
) < m68020
))
4295 /* On 68000, or for absolute value, switch to abs long */
4296 /* FIXME, we should check abs val, pick short or long */
4297 if (fragP
->fr_opcode
[0] == 0x61)
4299 fragP
->fr_opcode
[0] = 0x4E;
4300 fragP
->fr_opcode
[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4301 subseg_change (text_section
, 0);
4302 fix_new (fragP
, fragP
->fr_fix
, 4,
4303 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4307 else if (fragP
->fr_opcode
[0] == 0x60)
4309 fragP
->fr_opcode
[0] = 0x4E;
4310 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4311 subseg_change (text_section
, 0);
4312 fix_new (fragP
, fragP
->fr_fix
, 4,
4313 fragP
->fr_symbol
, fragP
->fr_offset
, 0, NO_RELOC
);
4319 as_warn ("Long branch offset to extern symbol not supported.");
4323 { /* Symbol is still undefined. Make it simple */
4324 fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4325 fragP
->fr_offset
+ 4, 1, NO_RELOC
);
4327 fragP
->fr_opcode
[1] = (char) 0xff;
4333 } /* case TAB(ABRANCH,SZ_UNDEF) */
4335 case TAB (FBRANCH
, SZ_UNDEF
):
4337 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flagseen
['l'])
4339 fragP
->fr_subtype
= TAB (FBRANCH
, SHORT
);
4344 fragP
->fr_subtype
= TAB (FBRANCH
, LONG
);
4348 } /* TAB(FBRANCH,SZ_UNDEF) */
4350 case TAB (PCREL
, SZ_UNDEF
):
4352 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flagseen
['l'])
4354 fragP
->fr_subtype
= TAB (PCREL
, SHORT
);
4359 fragP
->fr_subtype
= TAB (PCREL
, LONG
);
4363 } /* TAB(PCREL,SZ_UNDEF) */
4365 case TAB (BCC68000
, SZ_UNDEF
):
4367 if ((fragP
->fr_symbol
!= NULL
)
4368 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4370 fragP
->fr_subtype
= TAB (BCC68000
, BYTE
);
4373 /* only Bcc 68000 instructions can come here */
4374 /* change bcc into b!cc/jmp absl long */
4375 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4378 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
4379 /* JF: these were fr_opcode[2,3] */
4380 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4381 buffer_address
[1] = (char) 0xf8;
4382 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4383 subseg_change (text_section
, 0);
4384 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4385 fragP
->fr_offset
, 0, NO_RELOC
);
4390 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
4391 /* JF: these were fr_opcode[2,3] */
4392 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4393 buffer_address
[1] = (char) 0xf9;
4394 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4395 subseg_change (text_section
, 0);
4396 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4397 fragP
->fr_offset
, 0, NO_RELOC
);
4402 } /* case TAB(BCC68000,SZ_UNDEF) */
4404 case TAB (DBCC
, SZ_UNDEF
):
4406 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4408 fragP
->fr_subtype
= TAB (DBCC
, SHORT
);
4412 /* only DBcc 68000 instructions can come here */
4413 /* change dbcc into dbcc/jmp absl long */
4414 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4415 buffer_address
[0] = 0x00; /* branch offset = 4 */
4416 buffer_address
[1] = 0x04;
4417 buffer_address
[2] = 0x60; /* put in bra pc + ... */
4421 /* JF: these were fr_opcode[5-7] */
4422 buffer_address
[3] = 0x04; /* plus 4 */
4423 buffer_address
[4] = 0x4e; /* Put in Jump Word */
4424 buffer_address
[5] = (char) 0xf8;
4425 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4426 subseg_change (text_section
, 0);
4427 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4428 fragP
->fr_offset
, 0, NO_RELOC
);
4433 /* JF: these were fr_opcode[5-7] */
4434 buffer_address
[3] = 0x06; /* Plus 6 */
4435 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
4436 buffer_address
[5] = (char) 0xf9;
4437 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4438 subseg_change (text_section
, 0);
4439 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4440 fragP
->fr_offset
, 0, NO_RELOC
);
4446 } /* case TAB(DBCC,SZ_UNDEF) */
4448 case TAB (PCLEA
, SZ_UNDEF
):
4450 if ((S_GET_SEGMENT (fragP
->fr_symbol
)) == segment
|| flagseen
['l'])
4452 fragP
->fr_subtype
= TAB (PCLEA
, SHORT
);
4457 fragP
->fr_subtype
= TAB (PCLEA
, LONG
);
4461 } /* TAB(PCLEA,SZ_UNDEF) */
4466 } /* switch on subtype looking for SZ_UNDEF's. */
4468 /* now that SZ_UNDEF are taken care of, check others */
4469 switch (fragP
->fr_subtype
)
4471 case TAB (BCC68000
, BYTE
):
4472 case TAB (ABRANCH
, BYTE
):
4473 /* We can't do a short jump to the next instruction,
4474 so we force word mode. */
4475 if (fragP
->fr_symbol
&& S_GET_VALUE (fragP
->fr_symbol
) == 0 &&
4476 fragP
->fr_symbol
->sy_frag
== fragP
->fr_next
)
4478 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4485 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
4488 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4489 /* the bit-field entries in the relocation_info struct plays hell
4490 with the byte-order problems of cross-assembly. So as a hack,
4491 I added this mach. dependent ri twiddler. Ugly, but it gets
4493 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4494 are symbolnum, most sig. byte first. Last byte is broken up with
4495 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4496 nibble as nuthin. (on Sun 3 at least) */
4497 /* Translate the internal relocation information into target-specific
4501 md_ri_to_chars (the_bytes
, ri
)
4503 struct reloc_info_generic
*ri
;
4506 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4507 /* now the fun stuff */
4508 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4509 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4510 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4511 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4512 ((ri
->r_extern
<< 4) & 0x10));
4515 #endif /* comment */
4517 #ifndef BFD_ASSEMBLER
4519 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4522 relax_addressT segment_address_in_file
;
4525 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4526 * Out: GNU LD relocation length code: 0, 1, or 2.
4529 static CONST
unsigned char nbytes_r_length
[] =
4533 know (fixP
->fx_addsy
!= NULL
);
4535 md_number_to_chars (where
,
4536 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4539 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4540 ? S_GET_TYPE (fixP
->fx_addsy
)
4541 : fixP
->fx_addsy
->sy_number
);
4543 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
4544 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4545 where
[6] = r_symbolnum
& 0x0ff;
4546 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
4547 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
4553 #endif /* OBJ_AOUT or OBJ_BOUT */
4555 #ifndef WORKING_DOT_WORD
4556 CONST
int md_short_jump_size
= 4;
4557 CONST
int md_long_jump_size
= 6;
4560 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4562 addressT from_addr
, to_addr
;
4568 offset
= to_addr
- (from_addr
+ 2);
4570 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
4571 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
4575 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4577 addressT from_addr
, to_addr
;
4583 if (cpu_of_arch (current_architecture
) < m68020
)
4585 offset
= to_addr
- S_GET_VALUE (to_symbol
);
4586 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
4587 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4588 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
4593 offset
= to_addr
- (from_addr
+ 2);
4594 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
4595 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4600 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4603 10: Absolute 1:8 only
4604 20: Absolute 0:7 only
4605 30: absolute 0:15 only
4606 40: Absolute 0:31 only
4607 50: absolute 0:127 only
4608 55: absolute -64:63 only
4609 60: absolute -128:127 only
4610 70: absolute 0:4095 only
4617 struct m68k_exp
*exp
;
4625 if (*exp
->e_beg
== '0')
4627 if (exp
->e_beg
[1] == 'x')
4628 sscanf (exp
->e_beg
+ 2, "%x", &l
);
4630 sscanf (exp
->e_beg
+ 1, "%O", &l
);
4633 return atol (exp
->e_beg
);
4641 /* Can't do anything */
4644 if (!exp
->e_beg
|| !exp
->e_end
)
4646 seg (exp
) = absolute_section
;
4649 offs (exp
) = (ok
== 10) ? 1 : 0;
4650 as_warn ("Null expression defaults to %ld", offs (exp
));
4655 if ( /* ok!=80 && */ (exp
->e_end
[-1] == ':' || exp
->e_end
[-1] == '.')
4656 && (exp
->e_end
- exp
->e_beg
) >= 2)
4658 switch (exp
->e_end
[0])
4678 if (exp
->e_end
[-1] == ':')
4679 as_bad ("Unknown size for expression \"%c\"", exp
->e_end
[0]);
4683 c_save
= exp
->e_end
[1];
4684 exp
->e_end
[1] = '\0';
4685 save_in
= input_line_pointer
;
4686 input_line_pointer
= exp
->e_beg
;
4687 section
= expression (&exp
->e_exp
);
4688 seg (exp
) = section
;
4689 if (exp
->e_exp
.X_op
== O_absent
)
4691 /* Do the same thing the VAX asm does */
4692 seg (exp
) = absolute_section
;
4693 op (exp
) = O_constant
;
4699 as_warn ("expression out of range: defaulting to 1");
4703 else if (exp
->e_exp
.X_op
== O_constant
)
4708 if (offs (exp
) < 1 || offs (exp
) > 8)
4710 as_warn ("expression out of range: defaulting to 1");
4715 if (offs (exp
) < 0 || offs (exp
) > 7)
4719 if (offs (exp
) < 0 || offs (exp
) > 15)
4723 if (offs (exp
) < 0 || offs (exp
) > 32)
4727 if (offs (exp
) < 0 || offs (exp
) > 127)
4731 if (offs (exp
) < -64 || offs (exp
) > 63)
4735 if (offs (exp
) < -128 || offs (exp
) > 127)
4739 if (offs (exp
) < 0 || offs (exp
) > 4095)
4742 as_warn ("expression out of range: defaulting to 0");
4750 else if (exp
->e_exp
.X_op
== O_big
)
4752 if (offs (exp
) <= 0 /* flonum */
4753 && (ok
== 80 /* no bignums */
4754 || (ok
> 10 /* small-int ranges including 0 ok */
4755 /* If we have a flonum zero, a zero integer should
4756 do as well (e.g., in moveq). */
4757 && generic_floating_point_number
.exponent
== 0
4758 && generic_floating_point_number
.low
[0] == 0)))
4760 /* HACK! Turn it into a long */
4761 LITTLENUM_TYPE words
[6];
4763 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
4764 seg (exp
) = absolute_section
;
4765 op (exp
) = O_constant
;
4768 offs (exp
) = words
[1] | (words
[0] << 16);
4772 seg (exp
) = absolute_section
;
4773 op (exp
) = O_constant
;
4776 offs (exp
) = (ok
== 10) ? 1 : 0;
4777 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp
->e_beg
, offs (exp
));
4782 if (ok
>= 10 && ok
<= 70)
4784 seg (exp
) = absolute_section
;
4785 op (exp
) = O_constant
;
4788 offs (exp
) = (ok
== 10) ? 1 : 0;
4789 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp
->e_beg
, offs (exp
));
4793 if (input_line_pointer
!= exp
->e_end
+ 1)
4794 as_bad ("Ignoring junk after expression");
4795 exp
->e_end
[1] = c_save
;
4796 input_line_pointer
= save_in
;
4802 if (!isbyte (offs (exp
)))
4803 as_warn ("expression doesn't fit in BYTE");
4806 if (!isword (offs (exp
)))
4807 as_warn ("expression doesn't fit in WORD");
4815 /* These are the back-ends for the various machine dependent pseudo-ops. */
4816 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4822 subseg_set (data_section
, 1);
4823 demand_empty_rest_of_line ();
4830 subseg_set (data_section
, 2);
4831 demand_empty_rest_of_line ();
4838 /* We don't support putting frags in the BSS segment, we fake it
4839 by marking in_bss, then looking at s_skip for clues. */
4841 subseg_set (bss_section
, 0);
4842 demand_empty_rest_of_line ();
4850 register long temp_fill
;
4852 temp
= 1; /* JF should be 2? */
4853 temp_fill
= get_absolute_expression ();
4854 if (!need_pass_2
) /* Never make frag if expect extra pass. */
4855 frag_align (temp
, (int) temp_fill
);
4856 demand_empty_rest_of_line ();
4863 demand_empty_rest_of_line ();
4866 /* s_space is defined in read.c .skip is simply an alias to it. */
4870 * Invocation line includes a switch not recognized by the base assembler.
4871 * See if it's a processor-specific option. These are:
4873 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4874 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4875 * Select the architecture. Instructions or features not
4876 * supported by the selected architecture cause fatal
4877 * errors. More than one may be specified. The default is
4878 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4879 * for -m68000, and -m68882 is a synonym for -m68881.
4880 * -[A]m[c]no-68851, -[A]m[c]no-68881
4881 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4882 * so don't use or document it, but that's the way the parsing
4885 * -pic Indicates PIC.
4886 * -k Indicates PIC. (Sun 3 only.)
4888 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4889 * (e.g. m68020) also requests that float instructions be included. This
4890 * is the default setup, mostly to avoid hassling users. A better
4891 * rearrangement of this structure would be to add an option to DENY
4892 * floating point opcodes, for people who want to really know there's none
4893 * of that funny floaty stuff going on. FIXME-later.
4895 #ifndef MAYBE_FLOAT_TOO
4896 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4900 md_parse_option (argP
, cntP
, vecP
)
4907 case 'l': /* -l means keep external to 2 bit offset
4908 rather than 16 bit one */
4911 case 'S': /* -S means that jbsr's always turn into
4917 /* intentional fall-through */
4924 } /* allow an optional "c" */
4926 if (!strcmp (*argP
, "68000")
4927 || !strcmp (*argP
, "68008")
4928 || !strcmp (*argP
, "68302"))
4930 current_architecture
|= m68000
;
4932 else if (!strcmp (*argP
, "68010"))
4934 current_architecture
|= m68010
;
4936 else if (!strcmp (*argP
, "68020"))
4938 current_architecture
|= m68020
| MAYBE_FLOAT_TOO
;
4940 else if (!strcmp (*argP
, "68030"))
4942 current_architecture
|= m68030
| MAYBE_FLOAT_TOO
;
4944 else if (!strcmp (*argP
, "68040"))
4946 current_architecture
|= m68040
| MAYBE_FLOAT_TOO
;
4949 else if (!strcmp (*argP
, "68881"))
4951 current_architecture
|= m68881
;
4953 else if (!strcmp (*argP
, "68882"))
4955 current_architecture
|= m68882
;
4957 #endif /* NO_68881 */
4958 /* Even if we aren't configured to support the processor,
4959 it should still be possible to assert that the user
4960 doesn't have it... */
4961 else if (!strcmp (*argP
, "no-68881")
4962 || !strcmp (*argP
, "no-68882"))
4967 else if (!strcmp (*argP
, "68851"))
4969 current_architecture
|= m68851
;
4971 #endif /* NO_68851 */
4972 else if (!strcmp (*argP
, "no-68851"))
4976 else if (!strcmp (*argP
, "pu32") /* "cpu32" minus 'c' */
4977 || !strcmp (*argP
, "68331")
4978 || !strcmp (*argP
, "68332")
4979 || !strcmp (*argP
, "68333")
4980 || !strcmp (*argP
, "68340"))
4982 current_architecture
|= cpu32
;
4986 as_warn ("Unknown architecture, \"%s\". option ignored", *argP
);
4987 } /* switch on architecture */
4995 if (!strcmp (*argP
, "pic"))
4999 break; /* -pic, Position Independent Code */
5020 /* TEST2: Test md_assemble() */
5021 /* Warning, this routine probably doesn't work anymore */
5025 struct m68k_it the_ins
;
5033 if (!gets (buf
) || !*buf
)
5035 if (buf
[0] == '|' || buf
[1] == '.')
5037 for (cp
= buf
; *cp
; cp
++)
5042 memset (&the_ins
, '\0', sizeof (the_ins
));
5043 m68k_ip (&the_ins
, buf
);
5046 printf ("Error %s in %s\n", the_ins
.error
, buf
);
5050 printf ("Opcode(%d.%s): ", the_ins
.numo
, the_ins
.args
);
5051 for (n
= 0; n
< the_ins
.numo
; n
++)
5052 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
5054 print_the_insn (&the_ins
.opcode
[0], stdout
);
5055 (void) putchar ('\n');
5057 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
5059 if (the_ins
.operands
[n
].error
)
5061 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
5064 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
5065 if (the_ins
.operands
[n
].b_const
)
5066 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
5067 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
5068 if (the_ins
.operands
[n
].b_iadd
)
5069 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
5070 (void) putchar ('\n');
5082 while (*str
&& *str
!= ' ')
5084 if (str
[-1] == ':' || str
[1] == '=')
5091 /* Possible states for relaxation:
5093 0 0 branch offset byte (bra, etc)
5097 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5101 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5108 /* We have no need to default values of symbols. */
5112 md_undefined_symbol (name
)
5118 /* Parse an operand that is machine-specific.
5119 We just return without modifying the expression if we have nothing
5124 md_operand (expressionP
)
5125 expressionS
*expressionP
;
5129 /* Round up a section size to the appropriate boundary. */
5131 md_section_align (segment
, size
)
5135 return size
; /* Byte alignment is fine */
5138 /* Exactly what point is a PC-relative offset relative TO?
5139 On the 68k, they're relative to the address of the offset, plus
5140 its size. (??? Is this right? FIXME-SOON!) */
5142 md_pcrel_from (fixP
)
5145 return (fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
);
5148 #ifndef BFD_ASSEMBLER
5150 tc_coff_symbol_emit_hook ()
5155 tc_coff_sizemachdep (frag
)
5158 switch (frag
->fr_subtype
& 0x3)
5172 /* end of tc-m68k.c */