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[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #define NO_RELOC 0
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This array holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful */
32 #if defined (OBJ_ELF) || defined (TE_DELTA)
33 const char comment_chars[] = "|#";
34 #else
35 const char comment_chars[] = "|";
36 #endif
37
38 /* This array holds the chars that only start a comment at the beginning of
39 a line. If the line seems to have the form '# 123 filename'
40 .line and .file directives will appear in the pre-processed output */
41 /* Note that input_file.c hand checks for '#' at the beginning of the
42 first line of the input file. This is because the compiler outputs
43 #NO_APP at the beginning of its output. */
44 /* Also note that comments like this one will always work. */
45 const char line_comment_chars[] = "#";
46
47 const char line_separator_chars[] = "";
48
49 /* Chars that can be used to separate mant from exp in floating point nums */
50 CONST char EXP_CHARS[] = "eE";
51
52 /* Chars that mean this number is a floating point constant, as
53 in "0f12.456" or "0d1.2345e12". */
54
55 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
56
57 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
58 changed in read.c . Ideally it shouldn't have to know about it at all,
59 but nothing is ideal around here. */
60
61 const int md_reloc_size = 8; /* Size of relocation record */
62
63 /* Are we trying to generate PIC code? If so, absolute references
64 ought to be made into linkage table references or pc-relative
65 references. */
66 int flag_want_pic;
67
68 static int flag_short_refs; /* -l option */
69 static int flag_long_jumps; /* -S option */
70
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 #else
74 int flag_reg_prefix_optional;
75 #endif
76
77 /* The floating point coprocessor to use by default. */
78 static enum m68k_register m68k_float_copnum = COP1;
79
80 /* If this is non-zero, then references to number(%pc) will be taken
81 to refer to number, rather than to %pc + number. */
82 static int m68k_abspcadd;
83
84 /* If this is non-zero, then the quick forms of the move, add, and sub
85 instructions are used when possible. */
86 static int m68k_quick = 1;
87
88 /* If this is non-zero, then if the size is not specified for a base
89 or outer displacement, the assembler assumes that the size should
90 be 32 bits. */
91 static int m68k_rel32 = 1;
92
93 /* Its an arbitrary name: This means I don't approve of it */
94 /* See flames below */
95 static struct obstack robyn;
96
97 #define TAB(x,y) (((x)<<2)+(y))
98 #define TABTYPE(xy) ((xy) >> 2)
99 #define BYTE 0
100 #define SHORT 1
101 #define LONG 2
102 #define SZ_UNDEF 3
103 #undef BRANCH
104 /* Case `g' except when BCC68000 is applicable. */
105 #define ABRANCH 1
106 /* Coprocessor branches. */
107 #define FBRANCH 2
108 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
109 supported on all cpus. Widens to 32-bit absolute. */
110 #define PCREL 3
111 /* For inserting an extra jmp instruction with long offset on 68000,
112 for expanding conditional branches. (Not bsr or bra.) Since the
113 68000 doesn't support 32-bit displacements for conditional
114 branches, we fake it by reversing the condition and branching
115 around a jmp with an absolute long operand. */
116 #define BCC68000 4
117 /* For the DBcc "instructions". If the displacement requires 32 bits,
118 the branch-around-a-jump game is played here too. */
119 #define DBCC 5
120 /* Not currently used? */
121 #define PCLEA 6
122 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
123 in 16 or 8 bits. */
124 #define PCINDEX 7
125
126 struct m68k_incant
127 {
128 const char *m_operands;
129 unsigned long m_opcode;
130 short m_opnum;
131 short m_codenum;
132 int m_arch;
133 struct m68k_incant *m_next;
134 };
135
136 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
137 #define gettwo(x) (((x)->m_opcode)&0xffff)
138
139 static const enum m68k_register m68000_control_regs[] = { 0 };
140 static const enum m68k_register m68010_control_regs[] = {
141 SFC, DFC, USP, VBR,
142 0
143 };
144 static const enum m68k_register m68020_control_regs[] = {
145 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
146 0
147 };
148 static const enum m68k_register m68040_control_regs[] = {
149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
150 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
151 0
152 };
153 static const enum m68k_register m68060_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
155 USP, VBR, URP, SRP, PCR,
156 0
157 };
158 #define cpu32_control_regs m68010_control_regs
159
160 static const enum m68k_register *control_regs;
161
162 /* internal form of a 68020 instruction */
163 struct m68k_it
164 {
165 const char *error;
166 const char *args; /* list of opcode info */
167 int numargs;
168
169 int numo; /* Number of shorts in opcode */
170 short opcode[11];
171
172 struct m68k_op operands[6];
173
174 int nexp; /* number of exprs in use */
175 struct m68k_exp exprs[4];
176
177 int nfrag; /* Number of frags we have to produce */
178 struct
179 {
180 int fragoff; /* Where in the current opcode the frag ends */
181 symbolS *fadd;
182 long foff;
183 int fragty;
184 }
185 fragb[4];
186
187 int nrel; /* Num of reloc strucs in use */
188 struct
189 {
190 int n;
191 expressionS exp;
192 char wid;
193 char pcrel;
194 /* In a pc relative address the difference between the address
195 of the offset and the address that the offset is relative
196 to. This depends on the addressing mode. Basically this
197 is the value to put in the offset field to address the
198 first byte of the offset, without regarding the special
199 significance of some values (in the branch instruction, for
200 example). */
201 int pcrel_fix;
202 }
203 reloc[5]; /* Five is enough??? */
204 };
205
206 #define cpu_of_arch(x) ((x) & m68000up)
207 #define float_of_arch(x) ((x) & mfloat)
208 #define mmu_of_arch(x) ((x) & mmmu)
209
210 static struct m68k_it the_ins; /* the instruction being assembled */
211
212 #define op(ex) ((ex)->exp.X_op)
213 #define adds(ex) ((ex)->exp.X_add_symbol)
214 #define subs(ex) ((ex)->exp.X_op_symbol)
215 #define offs(ex) ((ex)->exp.X_add_number)
216
217 /* Macros for adding things to the m68k_it struct */
218
219 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
220
221 /* Like addword, but goes BEFORE general operands */
222 static void
223 insop (w, opcode)
224 int w;
225 struct m68k_incant *opcode;
226 {
227 int z;
228 for(z=the_ins.numo;z>opcode->m_codenum;--z)
229 the_ins.opcode[z]=the_ins.opcode[z-1];
230 for(z=0;z<the_ins.nrel;z++)
231 the_ins.reloc[z].n+=2;
232 for (z = 0; z < the_ins.nfrag; z++)
233 the_ins.fragb[z].fragoff++;
234 the_ins.opcode[opcode->m_codenum]=w;
235 the_ins.numo++;
236 }
237
238 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
239 Blecch. */
240 static void
241 add_fix (width, exp, pc_rel, pc_fix)
242 char width;
243 struct m68k_exp *exp;
244 int pc_rel;
245 int pc_fix;
246 {
247 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
248 ? (the_ins.numo*2-1)
249 : (((width)=='b')
250 ? (the_ins.numo*2+1)
251 : (the_ins.numo*2)));
252 the_ins.reloc[the_ins.nrel].exp = exp->exp;
253 the_ins.reloc[the_ins.nrel].wid = width;
254 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
255 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
256 }
257
258 /* Cause an extra frag to be generated here, inserting up to 10 bytes
259 (that value is chosen in the frag_var call in md_assemble). TYPE
260 is the subtype of the frag to be generated; its primary type is
261 rs_machine_dependent.
262
263 The TYPE parameter is also used by md_convert_frag_1 and
264 md_estimate_size_before_relax. The appropriate type of fixup will
265 be emitted by md_convert_frag_1.
266
267 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
268 static void
269 add_frag(add,off,type)
270 symbolS *add;
271 long off;
272 int type;
273 {
274 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
275 the_ins.fragb[the_ins.nfrag].fadd=add;
276 the_ins.fragb[the_ins.nfrag].foff=off;
277 the_ins.fragb[the_ins.nfrag++].fragty=type;
278 }
279
280 #define isvar(ex) \
281 (op (ex) != O_constant && op (ex) != O_big)
282
283 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
284 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
285 static int reverse_16_bits PARAMS ((int in));
286 static int reverse_8_bits PARAMS ((int in));
287 static void install_gen_operand PARAMS ((int mode, int val));
288 static void install_operand PARAMS ((int mode, int val));
289 static void s_bss PARAMS ((int));
290 static void s_data1 PARAMS ((int));
291 static void s_data2 PARAMS ((int));
292 static void s_even PARAMS ((int));
293 static void s_proc PARAMS ((int));
294 static void mri_chip PARAMS ((void));
295 static void s_chip PARAMS ((int));
296 static void s_fopt PARAMS ((int));
297 static void s_opt PARAMS ((int));
298 static void s_reg PARAMS ((int));
299 static void s_restore PARAMS ((int));
300 static void s_save PARAMS ((int));
301 static void s_mri_if PARAMS ((int));
302 static void s_mri_else PARAMS ((int));
303 static void s_mri_endi PARAMS ((int));
304 static void s_mri_break PARAMS ((int));
305 static void s_mri_next PARAMS ((int));
306 static void s_mri_for PARAMS ((int));
307 static void s_mri_endf PARAMS ((int));
308 static void s_mri_repeat PARAMS ((int));
309 static void s_mri_until PARAMS ((int));
310 static void s_mri_while PARAMS ((int));
311 static void s_mri_endw PARAMS ((int));
312
313 static int current_architecture;
314
315 struct m68k_cpu {
316 unsigned long arch;
317 const char *name;
318 };
319
320 static const struct m68k_cpu archs[] = {
321 { m68000, "68000" },
322 { m68010, "68010" },
323 { m68020, "68020" },
324 { m68030, "68030" },
325 { m68040, "68040" },
326 { m68060, "68060" },
327 { cpu32, "cpu32" },
328 { m68881, "68881" },
329 { m68851, "68851" },
330 /* Aliases (effectively, so far as gas is concerned) for the above
331 cpus. */
332 { m68020, "68k" },
333 { m68000, "68302" },
334 { m68000, "68008" },
335 { m68000, "68ec000" },
336 { m68000, "68hc000" },
337 { m68000, "68hc001" },
338 { m68020, "68ec020" },
339 { m68030, "68ec030" },
340 { m68040, "68ec040" },
341 { cpu32, "68330" },
342 { cpu32, "68331" },
343 { cpu32, "68332" },
344 { cpu32, "68333" },
345 { cpu32, "68340" },
346 { cpu32, "68360" },
347 { m68881, "68882" },
348 };
349
350 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
351
352 /* BCC68000 is for patching in an extra jmp instruction for long offsets
353 on the 68000. The 68000 doesn't support long branches with branchs */
354
355 /* This table desribes how you change sizes for the various types of variable
356 size expressions. This version only supports two kinds. */
357
358 /* Note that calls to frag_var need to specify the maximum expansion
359 needed; this is currently 10 bytes for DBCC. */
360
361 /* The fields are:
362 How far Forward this mode will reach:
363 How far Backward this mode will reach:
364 How many bytes this mode will add to the size of the frag
365 Which mode to go to if the offset won't fit in this one
366 */
367 relax_typeS md_relax_table[] =
368 {
369 {1, 1, 0, 0}, /* First entries aren't used */
370 {1, 1, 0, 0}, /* For no good reason except */
371 {1, 1, 0, 0}, /* that the VAX doesn't either */
372 {1, 1, 0, 0},
373
374 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
375 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
376 {0, 0, 4, 0},
377 {1, 1, 0, 0},
378
379 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
380 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
381 {0, 0, 4, 0},
382 {1, 1, 0, 0},
383
384 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
385 {(32767), (-32768), 2, TAB (PCREL, LONG)},
386 {0, 0, 4, 0},
387 {1, 1, 0, 0},
388
389 {(127), (-128), 0, TAB (BCC68000, SHORT)},
390 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
391 {0, 0, 6, 0}, /* jmp long space */
392 {1, 1, 0, 0},
393
394 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
395 {(32767), (-32768), 2, TAB (DBCC, LONG)},
396 {0, 0, 10, 0}, /* bra/jmp long space */
397 {1, 1, 0, 0},
398
399 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
400 {32767, -32768, 2, TAB (PCLEA, LONG)},
401 {0, 0, 6, 0},
402 {1, 1, 0, 0},
403
404 /* For, e.g., jmp pcrel indexed. */
405 {125, -130, 0, TAB (PCINDEX, SHORT)},
406 {32765, -32770, 2, TAB (PCINDEX, LONG)},
407 {0, 0, 4, 0},
408 {1, 1, 0, 0},
409 };
410
411 /* These are the machine dependent pseudo-ops. These are included so
412 the assembler can work on the output from the SUN C compiler, which
413 generates these.
414 */
415
416 /* This table describes all the machine specific pseudo-ops the assembler
417 has to support. The fields are:
418 pseudo-op name without dot
419 function to call to execute this pseudo-op
420 Integer arg to pass to the function
421 */
422 const pseudo_typeS md_pseudo_table[] =
423 {
424 {"data1", s_data1, 0},
425 {"data2", s_data2, 0},
426 {"bss", s_bss, 0},
427 {"even", s_even, 0},
428 {"skip", s_space, 0},
429 {"proc", s_proc, 0},
430 #ifdef TE_SUN3
431 {"align", s_align_bytes, 0},
432 #endif
433 #ifdef OBJ_ELF
434 {"swbeg", s_ignore, 0},
435 #endif
436
437 /* The following pseudo-ops are supported for MRI compatibility. */
438 {"chip", s_chip, 0},
439 {"comline", s_space, 1},
440 {"fopt", s_fopt, 0},
441 {"mask2", s_ignore, 0},
442 {"opt", s_opt, 0},
443 {"reg", s_reg, 0},
444 {"restore", s_restore, 0},
445 {"save", s_save, 0},
446
447 {"if", s_mri_if, 0},
448 {"if.b", s_mri_if, 'b'},
449 {"if.w", s_mri_if, 'w'},
450 {"if.l", s_mri_if, 'l'},
451 {"else", s_mri_else, 0},
452 {"else.s", s_mri_else, 's'},
453 {"else.l", s_mri_else, 'l'},
454 {"endi", s_mri_endi, 0},
455 {"break", s_mri_break, 0},
456 {"break.s", s_mri_break, 's'},
457 {"break.l", s_mri_break, 'l'},
458 {"next", s_mri_next, 0},
459 {"next.s", s_mri_next, 's'},
460 {"next.l", s_mri_next, 'l'},
461 {"for", s_mri_for, 0},
462 {"for.b", s_mri_for, 'b'},
463 {"for.w", s_mri_for, 'w'},
464 {"for.l", s_mri_for, 'l'},
465 {"endf", s_mri_endf, 0},
466 {"repeat", s_mri_repeat, 0},
467 {"until", s_mri_until, 0},
468 {"until.b", s_mri_until, 'b'},
469 {"until.w", s_mri_until, 'w'},
470 {"until.l", s_mri_until, 'l'},
471 {"while", s_mri_while, 0},
472 {"while.b", s_mri_while, 'b'},
473 {"while.w", s_mri_while, 'w'},
474 {"while.l", s_mri_while, 'l'},
475 {"endw", s_mri_endw, 0},
476
477 {0, 0, 0}
478 };
479
480
481 /* The mote pseudo ops are put into the opcode table, since they
482 don't start with a . they look like opcodes to gas.
483 */
484 extern void obj_coff_section ();
485
486 CONST pseudo_typeS mote_pseudo_table[] =
487 {
488
489 {"dcl", cons, 4},
490 {"dc", cons, 2},
491 {"dcw", cons, 2},
492 {"dcb", cons, 1},
493
494 {"dsl", s_space, 4},
495 {"ds", s_space, 2},
496 {"dsw", s_space, 2},
497 {"dsb", s_space, 1},
498
499 {"xdef", s_globl, 0},
500 {"align", s_align_ptwo, 0},
501 #ifdef M68KCOFF
502 {"sect", obj_coff_section, 0},
503 {"section", obj_coff_section, 0},
504 #endif
505 {0, 0, 0}
506 };
507
508 #define issbyte(x) ((x)>=-128 && (x)<=127)
509 #define isubyte(x) ((x)>=0 && (x)<=255)
510 #define issword(x) ((x)>=-32768 && (x)<=32767)
511 #define isuword(x) ((x)>=0 && (x)<=65535)
512
513 #define isbyte(x) ((x)>= -255 && (x)<=255)
514 #define isword(x) ((x)>=-32768 && (x)<=65535)
515 #define islong(x) (1)
516
517 extern char *input_line_pointer;
518
519 static char mklower_table[256];
520 #define mklower(c) (mklower_table[(unsigned char)(c)])
521 static char notend_table[256];
522 static char alt_notend_table[256];
523 #define notend(s) \
524 (! (notend_table[(unsigned char) *s] \
525 || (*s == ':' \
526 && alt_notend_table[(unsigned char) s[1]])))
527
528 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
529
530 #ifdef NO_PCREL_RELOCS
531
532 int
533 make_pcrel_absolute(fixP, add_number)
534 fixS *fixP;
535 long *add_number;
536 {
537 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
538
539 /* rewrite the PC relative instructions to absolute address ones.
540 * these are rumoured to be faster, and the apollo linker refuses
541 * to deal with the PC relative relocations.
542 */
543 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
544 {
545 opcode[0] = 0x4e;
546 opcode[1] = 0xf9;
547 }
548 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
549 {
550 opcode[0] = 0x4e;
551 opcode[1] = 0xb9;
552 }
553 else
554 as_fatal ("Unknown PC relative instruction");
555 *add_number -= 4;
556 return 0;
557 }
558
559 #endif /* NO_PCREL_RELOCS */
560
561 short
562 tc_coff_fix2rtype (fixP)
563 fixS *fixP;
564 {
565 if (fixP->fx_tcbit && fixP->fx_size == 4)
566 return R_RELLONG_NEG;
567 #ifdef NO_PCREL_RELOCS
568 know (fixP->fx_pcrel == 0);
569 return (fixP->fx_size == 1 ? R_RELBYTE
570 : fixP->fx_size == 2 ? R_DIR16
571 : R_DIR32);
572 #else
573 return (fixP->fx_pcrel ?
574 (fixP->fx_size == 1 ? R_PCRBYTE :
575 fixP->fx_size == 2 ? R_PCRWORD :
576 R_PCRLONG) :
577 (fixP->fx_size == 1 ? R_RELBYTE :
578 fixP->fx_size == 2 ? R_RELWORD :
579 R_RELLONG));
580 #endif
581 }
582
583 #endif
584
585 #ifdef BFD_ASSEMBLER
586
587 arelent *
588 tc_gen_reloc (section, fixp)
589 asection *section;
590 fixS *fixp;
591 {
592 arelent *reloc;
593 bfd_reloc_code_real_type code;
594
595 if (fixP->fx_tcbit)
596 abort ();
597
598 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
599 switch (F (fixp->fx_size, fixp->fx_pcrel))
600 {
601 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
602 MAP (1, 0, BFD_RELOC_8);
603 MAP (2, 0, BFD_RELOC_16);
604 MAP (4, 0, BFD_RELOC_32);
605 MAP (1, 1, BFD_RELOC_8_PCREL);
606 MAP (2, 1, BFD_RELOC_16_PCREL);
607 MAP (4, 1, BFD_RELOC_32_PCREL);
608 default:
609 abort ();
610 }
611
612 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
613 assert (reloc != 0);
614 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
615 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
616 if (fixp->fx_pcrel)
617 reloc->addend = fixp->fx_addnumber;
618 else
619 reloc->addend = 0;
620
621 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
622 assert (reloc->howto != 0);
623
624 return reloc;
625 }
626
627 #endif /* BFD_ASSEMBLER */
628
629 /* Handle of the OPCODE hash table. NULL means any use before
630 m68k_ip_begin() will crash. */
631 static struct hash_control *op_hash;
632 \f
633 /* Assemble an m68k instruction. */
634
635 void
636 m68k_ip (instring)
637 char *instring;
638 {
639 register char *p;
640 register struct m68k_op *opP;
641 register struct m68k_incant *opcode;
642 register const char *s;
643 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
644 char *pdot, *pdotmove;
645 enum m68k_size siz1, siz2;
646 char c;
647 int losing;
648 int opsfound;
649 char *crack_operand ();
650 LITTLENUM_TYPE words[6];
651 LITTLENUM_TYPE *wordp;
652 unsigned long ok_arch = 0;
653
654 if (*instring == ' ')
655 instring++; /* skip leading whitespace */
656
657 /* Scan up to end of operation-code, which MUST end in end-of-string
658 or exactly 1 space. */
659 pdot = 0;
660 for (p = instring; *p != '\0'; p++)
661 {
662 if (*p == ' ')
663 break;
664 if (*p == '.')
665 pdot = p;
666 }
667
668 if (p == instring)
669 {
670 the_ins.error = "No operator";
671 return;
672 }
673
674 /* p now points to the end of the opcode name, probably whitespace.
675 Make sure the name is null terminated by clobbering the
676 whitespace, look it up in the hash table, then fix it back.
677 Remove a dot, first, since the opcode tables have none. */
678 if (pdot != NULL)
679 {
680 for (pdotmove = pdot; pdotmove < p; pdotmove++)
681 *pdotmove = pdotmove[1];
682 p--;
683 }
684
685 c = *p;
686 *p = '\0';
687 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
688 *p = c;
689
690 if (pdot != NULL)
691 {
692 for (pdotmove = p; pdotmove > pdot; pdotmove--)
693 *pdotmove = pdotmove[-1];
694 *pdot = '.';
695 ++p;
696 }
697
698 if (opcode == NULL)
699 {
700 the_ins.error = "Unknown operator";
701 return;
702 }
703
704 /* found a legitimate opcode, start matching operands */
705 while (*p == ' ')
706 ++p;
707
708 if (opcode->m_operands == 0)
709 {
710 char *old = input_line_pointer;
711 *old = '\n';
712 input_line_pointer = p;
713 /* Ahh - it's a motorola style psuedo op */
714 mote_pseudo_table[opcode->m_opnum].poc_handler
715 (mote_pseudo_table[opcode->m_opnum].poc_val);
716 input_line_pointer = old;
717 *old = 0;
718
719 return;
720 }
721
722 if (flag_mri && opcode->m_opnum == 0)
723 {
724 /* In MRI mode, random garbage is allowed after an instruction
725 which accepts no operands. */
726 the_ins.args = opcode->m_operands;
727 the_ins.numargs = opcode->m_opnum;
728 the_ins.numo = opcode->m_codenum;
729 the_ins.opcode[0] = getone (opcode);
730 the_ins.opcode[1] = gettwo (opcode);
731 return;
732 }
733
734 for (opP = &the_ins.operands[0]; *p; opP++)
735 {
736 p = crack_operand (p, opP);
737
738 if (opP->error)
739 {
740 the_ins.error = opP->error;
741 return;
742 }
743 }
744
745 opsfound = opP - &the_ins.operands[0];
746
747 /* This ugly hack is to support the floating pt opcodes in their
748 standard form. Essentially, we fake a first enty of type COP#1 */
749 if (opcode->m_operands[0] == 'I')
750 {
751 int n;
752
753 for (n = opsfound; n > 0; --n)
754 the_ins.operands[n] = the_ins.operands[n - 1];
755
756 memset ((char *) (&the_ins.operands[0]), '\0',
757 sizeof (the_ins.operands[0]));
758 the_ins.operands[0].mode = CONTROL;
759 the_ins.operands[0].reg = m68k_float_copnum;
760 opsfound++;
761 }
762
763 /* We've got the operands. Find an opcode that'll accept them */
764 for (losing = 0;;)
765 {
766 /* If we didn't get the right number of ops, or we have no
767 common model with this pattern then reject this pattern. */
768
769 if (opsfound != opcode->m_opnum
770 || ((opcode->m_arch & current_architecture) == 0))
771 {
772 ++losing;
773 ok_arch |= opcode->m_arch;
774 }
775 else
776 {
777 for (s = opcode->m_operands, opP = &the_ins.operands[0];
778 *s && !losing;
779 s += 2, opP++)
780 {
781 /* Warning: this switch is huge! */
782 /* I've tried to organize the cases into this order:
783 non-alpha first, then alpha by letter. Lower-case
784 goes directly before uppercase counterpart. */
785 /* Code with multiple case ...: gets sorted by the lowest
786 case ... it belongs to. I hope this makes sense. */
787 switch (*s)
788 {
789 case '!':
790 switch (opP->mode)
791 {
792 case IMMED:
793 case DREG:
794 case AREG:
795 case FPREG:
796 case CONTROL:
797 case AINC:
798 case ADEC:
799 case REGLST:
800 losing++;
801 break;
802 default:
803 break;
804 }
805 break;
806
807 case '`':
808 switch (opP->mode)
809 {
810 case IMMED:
811 case DREG:
812 case AREG:
813 case FPREG:
814 case CONTROL:
815 case AINC:
816 case REGLST:
817 case AINDR:
818 losing++;
819 break;
820 default:
821 break;
822 }
823 break;
824
825 case '#':
826 if (opP->mode != IMMED)
827 losing++;
828 else if (s[1] == 'b'
829 && ! isvar (&opP->disp)
830 && (opP->disp.exp.X_op != O_constant
831 || ! isbyte (opP->disp.exp.X_add_number)))
832 losing++;
833 else if (s[1] == 'w'
834 && ! isvar (&opP->disp)
835 && (opP->disp.exp.X_op != O_constant
836 || ! isword (opP->disp.exp.X_add_number)))
837 losing++;
838 break;
839
840 case '^':
841 case 'T':
842 if (opP->mode != IMMED)
843 losing++;
844 break;
845
846 case '$':
847 if (opP->mode == AREG
848 || opP->mode == CONTROL
849 || opP->mode == FPREG
850 || opP->mode == IMMED
851 || opP->mode == REGLST
852 || (opP->mode != ABSL
853 && (opP->reg == PC
854 || opP->reg == ZPC)))
855 losing++;
856 break;
857
858 case '%':
859 if (opP->mode == CONTROL
860 || opP->mode == FPREG
861 || opP->mode == REGLST
862 || (opP->mode != ABSL
863 && opP->mode != IMMED
864 && (opP->reg == PC
865 || opP->reg == ZPC)))
866 losing++;
867 break;
868
869 case '&':
870 switch (opP->mode)
871 {
872 case DREG:
873 case AREG:
874 case FPREG:
875 case CONTROL:
876 case IMMED:
877 case AINC:
878 case ADEC:
879 case REGLST:
880 losing++;
881 break;
882 case ABSL:
883 break;
884 default:
885 if (opP->reg == PC
886 || opP->reg == ZPC)
887 losing++;
888 break;
889 }
890 break;
891
892 case '*':
893 if (opP->mode == CONTROL
894 || opP->mode == FPREG
895 || opP->mode == REGLST)
896 losing++;
897 break;
898
899 case '+':
900 if (opP->mode != AINC)
901 losing++;
902 break;
903
904 case '-':
905 if (opP->mode != ADEC)
906 losing++;
907 break;
908
909 case '/':
910 switch (opP->mode)
911 {
912 case AREG:
913 case CONTROL:
914 case FPREG:
915 case AINC:
916 case ADEC:
917 case IMMED:
918 case REGLST:
919 losing++;
920 break;
921 default:
922 break;
923 }
924 break;
925
926 case ';':
927 switch (opP->mode)
928 {
929 case AREG:
930 case CONTROL:
931 case FPREG:
932 case REGLST:
933 losing++;
934 break;
935 default:
936 break;
937 }
938 break;
939
940 case '?':
941 switch (opP->mode)
942 {
943 case AREG:
944 case CONTROL:
945 case FPREG:
946 case AINC:
947 case ADEC:
948 case IMMED:
949 case REGLST:
950 losing++;
951 break;
952 case ABSL:
953 break;
954 default:
955 if (opP->reg == PC || opP->reg == ZPC)
956 losing++;
957 break;
958 }
959 break;
960
961 case '@':
962 switch (opP->mode)
963 {
964 case AREG:
965 case CONTROL:
966 case FPREG:
967 case IMMED:
968 case REGLST:
969 losing++;
970 break;
971 default:
972 break;
973 }
974 break;
975
976 case '~': /* For now! (JF FOO is this right?) */
977 switch (opP->mode)
978 {
979 case DREG:
980 case AREG:
981 case CONTROL:
982 case FPREG:
983 case IMMED:
984 case REGLST:
985 losing++;
986 break;
987 case ABSL:
988 break;
989 default:
990 if (opP->reg == PC
991 || opP->reg == ZPC)
992 losing++;
993 break;
994 }
995 break;
996
997 case '3':
998 if (opP->mode != CONTROL
999 || (opP->reg != TT0 && opP->reg != TT1))
1000 losing++;
1001 break;
1002
1003 case 'A':
1004 if (opP->mode != AREG)
1005 losing++;
1006 break;
1007
1008 case 'a':
1009 if (opP->mode != AINDR)
1010 ++losing;
1011 break;
1012
1013 case 'B': /* FOO */
1014 if (opP->mode != ABSL
1015 || (flag_long_jumps
1016 && strncmp (instring, "jbsr", 4) == 0))
1017 losing++;
1018 break;
1019
1020 case 'C':
1021 if (opP->mode != CONTROL || opP->reg != CCR)
1022 losing++;
1023 break;
1024
1025 case 'd':
1026 if (opP->mode != DISP
1027 || opP->reg < ADDR0
1028 || opP->reg > ADDR7)
1029 losing++;
1030 break;
1031
1032 case 'D':
1033 if (opP->mode != DREG)
1034 losing++;
1035 break;
1036
1037 case 'F':
1038 if (opP->mode != FPREG)
1039 losing++;
1040 break;
1041
1042 case 'I':
1043 if (opP->mode != CONTROL
1044 || opP->reg < COP0
1045 || opP->reg > COP7)
1046 losing++;
1047 break;
1048
1049 case 'J':
1050 if (opP->mode != CONTROL
1051 || opP->reg < USP
1052 || opP->reg > last_movec_reg)
1053 losing++;
1054 else
1055 {
1056 const enum m68k_register *rp;
1057 for (rp = control_regs; *rp; rp++)
1058 if (*rp == opP->reg)
1059 break;
1060 if (*rp == 0)
1061 losing++;
1062 }
1063 break;
1064
1065 case 'k':
1066 if (opP->mode != IMMED)
1067 losing++;
1068 break;
1069
1070 case 'l':
1071 case 'L':
1072 if (opP->mode == DREG
1073 || opP->mode == AREG
1074 || opP->mode == FPREG)
1075 {
1076 if (s[1] == '8')
1077 losing++;
1078 else
1079 {
1080 switch (opP->mode)
1081 {
1082 case DREG:
1083 opP->mask = 1 << (opP->reg - DATA0);
1084 break;
1085 case AREG:
1086 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1087 break;
1088 case FPREG:
1089 opP->mask = 1 << (opP->reg - FP0 + 16);
1090 break;
1091 default:
1092 abort ();
1093 }
1094 opP->mode = REGLST;
1095 }
1096 }
1097 else if (opP->mode == CONTROL)
1098 {
1099 if (s[1] != '8')
1100 losing++;
1101 else
1102 {
1103 switch (opP->reg)
1104 {
1105 case FPI:
1106 opP->mask = 1 << 24;
1107 break;
1108 case FPS:
1109 opP->mask = 1 << 25;
1110 break;
1111 case FPC:
1112 opP->mask = 1 << 26;
1113 break;
1114 default:
1115 losing++;
1116 break;
1117 }
1118 opP->mode = REGLST;
1119 }
1120 }
1121 else if (opP->mode == ABSL
1122 && opP->disp.size == SIZE_UNSPEC
1123 && opP->disp.exp.X_op == O_constant)
1124 {
1125 /* This is what the MRI REG pseudo-op generates. */
1126 opP->mode = REGLST;
1127 opP->mask = opP->disp.exp.X_add_number;
1128 }
1129 else if (opP->mode != REGLST)
1130 losing++;
1131 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1132 losing++;
1133 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1134 losing++;
1135 break;
1136
1137 case 'M':
1138 if (opP->mode != IMMED)
1139 losing++;
1140 else if (opP->disp.exp.X_op != O_constant
1141 || ! issbyte (opP->disp.exp.X_add_number))
1142 losing++;
1143 else if (! m68k_quick
1144 && instring[3] != 'q'
1145 && instring[4] != 'q')
1146 losing++;
1147 break;
1148
1149 case 'O':
1150 if (opP->mode != DREG && opP->mode != IMMED)
1151 losing++;
1152 break;
1153
1154 case 'Q':
1155 if (opP->mode != IMMED)
1156 losing++;
1157 else if (opP->disp.exp.X_op != O_constant
1158 || opP->disp.exp.X_add_number < 1
1159 || opP->disp.exp.X_add_number > 8)
1160 losing++;
1161 else if (! m68k_quick
1162 && (strncmp (instring, "add", 3) == 0
1163 || strncmp (instring, "sub", 3) == 0)
1164 && instring[3] != 'q')
1165 losing++;
1166 break;
1167
1168 case 'R':
1169 if (opP->mode != DREG && opP->mode != AREG)
1170 losing++;
1171 break;
1172
1173 case 'r':
1174 if (opP->mode != AINDR
1175 && (opP->mode != BASE
1176 || (opP->reg != 0
1177 && opP->reg != ZADDR0)
1178 || opP->disp.exp.X_op != O_absent
1179 || ((opP->index.reg < DATA0
1180 || opP->index.reg > DATA7)
1181 && (opP->index.reg < ADDR0
1182 || opP->index.reg > ADDR7))
1183 || opP->index.size != SIZE_UNSPEC
1184 || opP->index.scale != 1))
1185 losing++;
1186 break;
1187
1188 case 's':
1189 if (opP->mode != CONTROL
1190 || ! (opP->reg == FPI
1191 || opP->reg == FPS
1192 || opP->reg == FPC))
1193 losing++;
1194 break;
1195
1196 case 'S':
1197 if (opP->mode != CONTROL || opP->reg != SR)
1198 losing++;
1199 break;
1200
1201 case 't':
1202 if (opP->mode != IMMED)
1203 losing++;
1204 else if (opP->disp.exp.X_op != O_constant
1205 || opP->disp.exp.X_add_number < 0
1206 || opP->disp.exp.X_add_number > 7)
1207 losing++;
1208 break;
1209
1210 case 'U':
1211 if (opP->mode != CONTROL || opP->reg != USP)
1212 losing++;
1213 break;
1214
1215 /* JF these are out of order. We could put them
1216 in order if we were willing to put up with
1217 bunches of #ifdef m68851s in the code.
1218
1219 Don't forget that you need these operands
1220 to use 68030 MMU instructions. */
1221 #ifndef NO_68851
1222 /* Memory addressing mode used by pflushr */
1223 case '|':
1224 if (opP->mode == CONTROL
1225 || opP->mode == FPREG
1226 || opP->mode == DREG
1227 || opP->mode == AREG
1228 || opP->mode == REGLST)
1229 losing++;
1230 /* We should accept immediate operands, but they
1231 supposedly have to be quad word, and we don't
1232 handle that. I would like to see what a Motorola
1233 assembler does before doing something here. */
1234 if (opP->mode == IMMED)
1235 losing++;
1236 break;
1237
1238 case 'f':
1239 if (opP->mode != CONTROL
1240 || (opP->reg != SFC && opP->reg != DFC))
1241 losing++;
1242 break;
1243
1244 case '0':
1245 if (opP->mode != CONTROL || opP->reg != TC)
1246 losing++;
1247 break;
1248
1249 case '1':
1250 if (opP->mode != CONTROL || opP->reg != AC)
1251 losing++;
1252 break;
1253
1254 case '2':
1255 if (opP->mode != CONTROL
1256 || (opP->reg != CAL
1257 && opP->reg != VAL
1258 && opP->reg != SCC))
1259 losing++;
1260 break;
1261
1262 case 'V':
1263 if (opP->mode != CONTROL
1264 || opP->reg != VAL)
1265 losing++;
1266 break;
1267
1268 case 'W':
1269 if (opP->mode != CONTROL
1270 || (opP->reg != DRP
1271 && opP->reg != SRP
1272 && opP->reg != CRP))
1273 losing++;
1274 break;
1275
1276 case 'X':
1277 if (opP->mode != CONTROL
1278 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1279 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1280 losing++;
1281 break;
1282
1283 case 'Y':
1284 if (opP->mode != CONTROL || opP->reg != PSR)
1285 losing++;
1286 break;
1287
1288 case 'Z':
1289 if (opP->mode != CONTROL || opP->reg != PCSR)
1290 losing++;
1291 break;
1292 #endif
1293 case 'c':
1294 if (opP->mode != CONTROL
1295 || (opP->reg != NC
1296 && opP->reg != IC
1297 && opP->reg != DC
1298 && opP->reg != BC))
1299 {
1300 losing++;
1301 } /* not a cache specifier. */
1302 break;
1303
1304 case '_':
1305 if (opP->mode != ABSL)
1306 ++losing;
1307 break;
1308
1309 default:
1310 abort ();
1311 } /* switch on type of operand */
1312
1313 if (losing)
1314 break;
1315 } /* for each operand */
1316 } /* if immediately wrong */
1317
1318 if (!losing)
1319 {
1320 break;
1321 } /* got it. */
1322
1323 opcode = opcode->m_next;
1324
1325 if (!opcode)
1326 {
1327 if (ok_arch
1328 && !(ok_arch & current_architecture))
1329 {
1330 char buf[200], *cp;
1331 int len;
1332 strcpy (buf,
1333 "invalid instruction for this architecture; needs ");
1334 cp = buf + strlen (buf);
1335 switch (ok_arch)
1336 {
1337 case mfloat:
1338 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1339 break;
1340 case mmmu:
1341 strcpy (cp, "mmu (68030 or 68851)");
1342 break;
1343 case m68020up:
1344 strcpy (cp, "68020 or higher");
1345 break;
1346 case m68000up:
1347 strcpy (cp, "68000 or higher");
1348 break;
1349 case m68010up:
1350 strcpy (cp, "68010 or higher");
1351 break;
1352 default:
1353 {
1354 int got_one = 0, idx;
1355 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1356 idx++)
1357 {
1358 if (archs[idx].arch & ok_arch)
1359 {
1360 if (got_one)
1361 {
1362 strcpy (cp, " or ");
1363 cp += strlen (cp);
1364 }
1365 got_one = 1;
1366 strcpy (cp, archs[idx].name);
1367 cp += strlen (cp);
1368 }
1369 }
1370 }
1371 }
1372 len = cp - buf + 1;
1373 cp = malloc (len);
1374 strcpy (cp, buf);
1375 the_ins.error = cp;
1376 }
1377 else
1378 the_ins.error = "operands mismatch";
1379 return;
1380 } /* Fell off the end */
1381
1382 losing = 0;
1383 }
1384
1385 /* now assemble it */
1386
1387 the_ins.args = opcode->m_operands;
1388 the_ins.numargs = opcode->m_opnum;
1389 the_ins.numo = opcode->m_codenum;
1390 the_ins.opcode[0] = getone (opcode);
1391 the_ins.opcode[1] = gettwo (opcode);
1392
1393 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1394 {
1395 /* This switch is a doozy.
1396 Watch the first step; its a big one! */
1397 switch (s[0])
1398 {
1399
1400 case '*':
1401 case '~':
1402 case '%':
1403 case ';':
1404 case '@':
1405 case '!':
1406 case '&':
1407 case '$':
1408 case '?':
1409 case '/':
1410 case '`':
1411 #ifndef NO_68851
1412 case '|':
1413 #endif
1414 switch (opP->mode)
1415 {
1416 case IMMED:
1417 tmpreg = 0x3c; /* 7.4 */
1418 if (strchr ("bwl", s[1]))
1419 nextword = get_num (&opP->disp, 80);
1420 else
1421 nextword = get_num (&opP->disp, 0);
1422 if (isvar (&opP->disp))
1423 add_fix (s[1], &opP->disp, 0, 0);
1424 switch (s[1])
1425 {
1426 case 'b':
1427 if (!isbyte (nextword))
1428 opP->error = "operand out of range";
1429 addword (nextword);
1430 baseo = 0;
1431 break;
1432 case 'w':
1433 if (!isword (nextword))
1434 opP->error = "operand out of range";
1435 addword (nextword);
1436 baseo = 0;
1437 break;
1438 case 'l':
1439 addword (nextword >> 16);
1440 addword (nextword);
1441 baseo = 0;
1442 break;
1443
1444 case 'f':
1445 baseo = 2;
1446 outro = 8;
1447 break;
1448 case 'F':
1449 baseo = 4;
1450 outro = 11;
1451 break;
1452 case 'x':
1453 baseo = 6;
1454 outro = 15;
1455 break;
1456 case 'p':
1457 baseo = 6;
1458 outro = -1;
1459 break;
1460 default:
1461 abort ();
1462 }
1463 if (!baseo)
1464 break;
1465
1466 /* We gotta put out some float */
1467 if (op (&opP->disp) != O_big)
1468 {
1469 valueT val;
1470 int gencnt;
1471
1472 /* Can other cases happen here? */
1473 if (op (&opP->disp) != O_constant)
1474 abort ();
1475
1476 val = (valueT) offs (&opP->disp);
1477 gencnt = 0;
1478 do
1479 {
1480 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1481 val >>= LITTLENUM_NUMBER_OF_BITS;
1482 ++gencnt;
1483 }
1484 while (val != 0);
1485 offs (&opP->disp) = gencnt;
1486 }
1487 if (offs (&opP->disp) > 0)
1488 {
1489 if (offs (&opP->disp) > baseo)
1490 {
1491 as_warn ("Bignum too big for %c format; truncated",
1492 s[1]);
1493 offs (&opP->disp) = baseo;
1494 }
1495 baseo -= offs (&opP->disp);
1496 while (baseo--)
1497 addword (0);
1498 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1499 offs (&opP->disp)--;
1500 --wordp)
1501 addword (*wordp);
1502 break;
1503 }
1504 gen_to_words (words, baseo, (long) outro);
1505 for (wordp = words; baseo--; wordp++)
1506 addword (*wordp);
1507 break;
1508 case DREG:
1509 tmpreg = opP->reg - DATA; /* 0.dreg */
1510 break;
1511 case AREG:
1512 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1513 break;
1514 case AINDR:
1515 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1516 break;
1517 case ADEC:
1518 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1519 break;
1520 case AINC:
1521 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1522 break;
1523 case DISP:
1524
1525 nextword = get_num (&opP->disp, 80);
1526
1527 if (opP->reg == PC
1528 && ! isvar (&opP->disp)
1529 && m68k_abspcadd)
1530 {
1531 opP->disp.exp.X_op = O_symbol;
1532 #ifndef BFD_ASSEMBLER
1533 opP->disp.exp.X_add_symbol = &abs_symbol;
1534 #else
1535 opP->disp.exp.X_add_symbol =
1536 section_symbol (absolute_section);
1537 #endif
1538 }
1539
1540 /* Force into index mode. Hope this works */
1541
1542 /* We do the first bit for 32-bit displacements, and the
1543 second bit for 16 bit ones. It is possible that we
1544 should make the default be WORD instead of LONG, but
1545 I think that'd break GCC, so we put up with a little
1546 inefficiency for the sake of working output. */
1547
1548 if (!issword (nextword)
1549 || (isvar (&opP->disp)
1550 && ((opP->disp.size == SIZE_UNSPEC
1551 && flag_short_refs == 0
1552 && cpu_of_arch (current_architecture) >= m68020)
1553 || opP->disp.size == SIZE_LONG)))
1554 {
1555 if (opP->reg == PC)
1556 tmpreg = 0x3B; /* 7.3 */
1557 else
1558 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1559 if (isvar (&opP->disp))
1560 {
1561 if (opP->reg == PC)
1562 {
1563 #if 0
1564 addword (0x0170);
1565 add_fix ('l', &opP->disp, 1, 2);
1566 addword (0), addword (0);
1567 #else
1568 add_frag (adds (&opP->disp),
1569 offs (&opP->disp),
1570 TAB (PCLEA, SZ_UNDEF));
1571 #endif
1572 break;
1573 }
1574 else
1575 {
1576 addword (0x0170);
1577 add_fix ('l', &opP->disp, 0, 0);
1578 }
1579 }
1580 else
1581 addword (0x0170);
1582 addword (nextword >> 16);
1583 }
1584 else
1585 {
1586 if (opP->reg == PC)
1587 tmpreg = 0x3A; /* 7.2 */
1588 else
1589 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1590
1591 if (isvar (&opP->disp))
1592 {
1593 if (opP->reg == PC)
1594 {
1595 add_fix ('w', &opP->disp, 1, 0);
1596 }
1597 else
1598 add_fix ('w', &opP->disp, 0, 0);
1599 }
1600 }
1601 addword (nextword);
1602 break;
1603
1604 case POST:
1605 case PRE:
1606 case BASE:
1607 nextword = 0;
1608 baseo = get_num (&opP->disp, 80);
1609 if (opP->mode == POST || opP->mode == PRE)
1610 outro = get_num (&opP->odisp, 80);
1611 /* Figure out the `addressing mode'.
1612 Also turn on the BASE_DISABLE bit, if needed. */
1613 if (opP->reg == PC || opP->reg == ZPC)
1614 {
1615 tmpreg = 0x3b; /* 7.3 */
1616 if (opP->reg == ZPC)
1617 nextword |= 0x80;
1618 }
1619 else if (opP->reg == 0)
1620 {
1621 nextword |= 0x80;
1622 tmpreg = 0x30; /* 6.garbage */
1623 }
1624 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1625 {
1626 nextword |= 0x80;
1627 tmpreg = 0x30 + opP->reg - ZADDR0;
1628 }
1629 else
1630 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1631
1632 siz1 = opP->disp.size;
1633 if (opP->mode == POST || opP->mode == PRE)
1634 siz2 = opP->odisp.size;
1635 else
1636 siz2 = SIZE_UNSPEC;
1637
1638 /* Index register stuff */
1639 if (opP->index.reg != 0
1640 && opP->index.reg >= DATA
1641 && opP->index.reg <= ADDR7)
1642 {
1643 nextword |= (opP->index.reg - DATA) << 12;
1644
1645 if (opP->index.size == SIZE_UNSPEC
1646 || opP->index.size == SIZE_LONG)
1647 nextword |= 0x800;
1648
1649 if (cpu_of_arch (current_architecture) < m68020)
1650 {
1651 if (opP->index.scale != 1)
1652 {
1653 opP->error =
1654 "scale factor invalid on this architecture; needs 68020 or higher";
1655 }
1656 }
1657
1658 switch (opP->index.scale)
1659 {
1660 case 1:
1661 break;
1662 case 2:
1663 nextword |= 0x200;
1664 break;
1665 case 4:
1666 nextword |= 0x400;
1667 break;
1668 case 8:
1669 nextword |= 0x600;
1670 break;
1671 default:
1672 abort ();
1673 }
1674 /* IF its simple,
1675 GET US OUT OF HERE! */
1676
1677 /* Must be INDEX, with an index register. Address
1678 register cannot be ZERO-PC, and either :b was
1679 forced, or we know it will fit. For a 68000 or
1680 68010, force this mode anyways, because the
1681 larger modes aren't supported. */
1682 if (opP->mode == BASE
1683 && ((opP->reg >= ADDR0
1684 && opP->reg <= ADDR7)
1685 || opP->reg == PC))
1686 {
1687 if (siz1 == SIZE_BYTE
1688 || cpu_of_arch (current_architecture) < m68020
1689 || (siz1 == SIZE_UNSPEC
1690 && ! isvar (&opP->disp)
1691 && issbyte (baseo)))
1692 {
1693 nextword += baseo & 0xff;
1694 addword (nextword);
1695 if (isvar (&opP->disp))
1696 {
1697 /* Do a byte relocation. If it doesn't
1698 fit (possible on m68000) let the
1699 fixup processing complain later. */
1700 if (opP->reg == PC)
1701 add_fix ('B', &opP->disp, 1, 1);
1702 else
1703 add_fix ('B', &opP->disp, 0, 0);
1704 }
1705 else if (siz1 != SIZE_BYTE)
1706 {
1707 if (siz1 != SIZE_UNSPEC)
1708 as_warn ("Forcing byte displacement");
1709 if (! issbyte (baseo))
1710 opP->error = "byte displacement out of range";
1711 }
1712
1713 break;
1714 }
1715 else if (siz1 == SIZE_UNSPEC
1716 && opP->reg == PC
1717 && isvar (&opP->disp)
1718 && subs (&opP->disp) == NULL)
1719 {
1720 nextword += baseo & 0xff;
1721 addword (nextword);
1722 add_frag (adds (&opP->disp), offs (&opP->disp),
1723 TAB (PCINDEX, SZ_UNDEF));
1724
1725 break;
1726 }
1727 }
1728 }
1729 else
1730 {
1731 nextword |= 0x40; /* No index reg */
1732 if (opP->index.reg >= ZDATA0
1733 && opP->index.reg <= ZDATA7)
1734 nextword |= (opP->index.reg - ZDATA0) << 12;
1735 else if (opP->index.reg >= ZADDR0
1736 || opP->index.reg <= ZADDR7)
1737 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1738 }
1739
1740 /* It isn't simple. */
1741
1742 if (cpu_of_arch (current_architecture) < m68020)
1743 opP->error =
1744 "invalid operand mode for this architecture; needs 68020 or higher";
1745
1746 nextword |= 0x100;
1747 /* If the guy specified a width, we assume that it is
1748 wide enough. Maybe it isn't. If so, we lose. */
1749 switch (siz1)
1750 {
1751 case SIZE_UNSPEC:
1752 if (isvar (&opP->disp)
1753 ? m68k_rel32
1754 : ! issword (baseo))
1755 {
1756 siz1 = SIZE_LONG;
1757 nextword |= 0x30;
1758 }
1759 else if (! isvar (&opP->disp) && baseo == 0)
1760 nextword |= 0x10;
1761 else
1762 {
1763 nextword |= 0x20;
1764 siz1 = SIZE_WORD;
1765 }
1766 break;
1767 case SIZE_BYTE:
1768 as_warn (":b not permitted; defaulting to :w");
1769 /* Fall through. */
1770 case SIZE_WORD:
1771 nextword |= 0x20;
1772 break;
1773 case SIZE_LONG:
1774 nextword |= 0x30;
1775 break;
1776 }
1777
1778 /* Figure out innner displacement stuff */
1779 if (opP->mode == POST || opP->mode == PRE)
1780 {
1781 switch (siz2)
1782 {
1783 case SIZE_UNSPEC:
1784 if (isvar (&opP->odisp)
1785 ? m68k_rel32
1786 : ! issword (outro))
1787 {
1788 siz2 = SIZE_LONG;
1789 nextword |= 0x3;
1790 }
1791 else if (! isvar (&opP->odisp) && outro == 0)
1792 nextword |= 0x1;
1793 else
1794 {
1795 nextword |= 0x2;
1796 siz2 = SIZE_WORD;
1797 }
1798 break;
1799 case 1:
1800 as_warn (":b not permitted; defaulting to :w");
1801 /* Fall through. */
1802 case 2:
1803 nextword |= 0x2;
1804 break;
1805 case 3:
1806 nextword |= 0x3;
1807 break;
1808 }
1809 if (opP->mode == POST
1810 && (nextword & 0x40) == 0)
1811 nextword |= 0x04;
1812 }
1813 addword (nextword);
1814
1815 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1816 {
1817 if (opP->reg == PC || opP->reg == ZPC)
1818 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1819 else
1820 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1821 }
1822 if (siz1 == SIZE_LONG)
1823 addword (baseo >> 16);
1824 if (siz1 != SIZE_UNSPEC)
1825 addword (baseo);
1826
1827 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1828 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1829 if (siz2 == SIZE_LONG)
1830 addword (outro >> 16);
1831 if (siz2 != SIZE_UNSPEC)
1832 addword (outro);
1833
1834 break;
1835
1836 case ABSL:
1837 nextword = get_num (&opP->disp, 80);
1838 switch (opP->disp.size)
1839 {
1840 default:
1841 abort ();
1842 case SIZE_UNSPEC:
1843 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1844 {
1845 tmpreg = 0x38; /* 7.0 */
1846 addword (nextword);
1847 break;
1848 }
1849 /* Don't generate pc relative code on 68010 and
1850 68000. */
1851 if (isvar (&opP->disp)
1852 && !subs (&opP->disp)
1853 && adds (&opP->disp)
1854 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
1855 && cpu_of_arch (current_architecture) >= m68020
1856 && !flag_long_jumps
1857 && !strchr ("~%&$?", s[0]))
1858 {
1859 tmpreg = 0x3A; /* 7.2 */
1860 add_frag (adds (&opP->disp),
1861 offs (&opP->disp),
1862 TAB (PCREL, SZ_UNDEF));
1863 break;
1864 }
1865 /* Fall through into long */
1866 case SIZE_LONG:
1867 if (isvar (&opP->disp))
1868 add_fix ('l', &opP->disp, 0, 0);
1869
1870 tmpreg = 0x39;/* 7.1 mode */
1871 addword (nextword >> 16);
1872 addword (nextword);
1873 break;
1874
1875 case SIZE_WORD: /* Word */
1876 if (isvar (&opP->disp))
1877 add_fix ('w', &opP->disp, 0, 0);
1878
1879 tmpreg = 0x38;/* 7.0 mode */
1880 addword (nextword);
1881 break;
1882 }
1883 break;
1884 case CONTROL:
1885 case FPREG:
1886 default:
1887 as_bad ("unknown/incorrect operand");
1888 /* abort(); */
1889 }
1890 install_gen_operand (s[1], tmpreg);
1891 break;
1892
1893 case '#':
1894 case '^':
1895 switch (s[1])
1896 { /* JF: I hate floating point! */
1897 case 'j':
1898 tmpreg = 70;
1899 break;
1900 case '8':
1901 tmpreg = 20;
1902 break;
1903 case 'C':
1904 tmpreg = 50;
1905 break;
1906 case '3':
1907 default:
1908 tmpreg = 80;
1909 break;
1910 }
1911 tmpreg = get_num (&opP->disp, tmpreg);
1912 if (isvar (&opP->disp))
1913 add_fix (s[1], &opP->disp, 0, 0);
1914 switch (s[1])
1915 {
1916 case 'b': /* Danger: These do no check for
1917 certain types of overflow.
1918 user beware! */
1919 if (!isbyte (tmpreg))
1920 opP->error = "out of range";
1921 insop (tmpreg, opcode);
1922 if (isvar (&opP->disp))
1923 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1924 break;
1925 case 'w':
1926 if (!isword (tmpreg))
1927 opP->error = "out of range";
1928 insop (tmpreg, opcode);
1929 if (isvar (&opP->disp))
1930 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1931 break;
1932 case 'l':
1933 /* Because of the way insop works, we put these two out
1934 backwards. */
1935 insop (tmpreg, opcode);
1936 insop (tmpreg >> 16, opcode);
1937 if (isvar (&opP->disp))
1938 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1939 break;
1940 case '3':
1941 tmpreg &= 0xFF;
1942 case '8':
1943 case 'C':
1944 install_operand (s[1], tmpreg);
1945 break;
1946 default:
1947 abort ();
1948 }
1949 break;
1950
1951 case '+':
1952 case '-':
1953 case 'A':
1954 case 'a':
1955 install_operand (s[1], opP->reg - ADDR);
1956 break;
1957
1958 case 'B':
1959 tmpreg = get_num (&opP->disp, 80);
1960 switch (s[1])
1961 {
1962 case 'B':
1963 /* The pc_fix argument winds up in fx_pcrel_adjust,
1964 which is a char, and may therefore be unsigned. We
1965 want to pass -1, but we pass 64 instead, and convert
1966 back in md_pcrel_from. */
1967 add_fix ('B', &opP->disp, 1, 64);
1968 break;
1969 case 'W':
1970 add_fix ('w', &opP->disp, 1, 0);
1971 addword (0);
1972 break;
1973 case 'L':
1974 long_branch:
1975 if (cpu_of_arch (current_architecture) < m68020)
1976 as_warn ("Can't use long branches on 68000/68010");
1977 the_ins.opcode[the_ins.numo - 1] |= 0xff;
1978 add_fix ('l', &opP->disp, 1, 0);
1979 addword (0);
1980 addword (0);
1981 break;
1982 case 'g':
1983 if (subs (&opP->disp)) /* We can't relax it */
1984 goto long_branch;
1985
1986 /* This could either be a symbol, or an absolute
1987 address. No matter, the frag hacking will finger it
1988 out. Not quite: it can't switch from BRANCH to
1989 BCC68000 for the case where opnd is absolute (it
1990 needs to use the 68000 hack since no conditional abs
1991 jumps). */
1992 if (((cpu_of_arch (current_architecture) < m68020)
1993 || (0 == adds (&opP->disp)))
1994 && (the_ins.opcode[0] >= 0x6200)
1995 && (the_ins.opcode[0] <= 0x6f00))
1996 add_frag (adds (&opP->disp), offs (&opP->disp),
1997 TAB (BCC68000, SZ_UNDEF));
1998 else
1999 add_frag (adds (&opP->disp), offs (&opP->disp),
2000 TAB (ABRANCH, SZ_UNDEF));
2001 break;
2002 case 'w':
2003 if (isvar (&opP->disp))
2004 {
2005 #if 1
2006 /* check for DBcc instruction */
2007 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2008 {
2009 /* size varies if patch */
2010 /* needed for long form */
2011 add_frag (adds (&opP->disp), offs (&opP->disp),
2012 TAB (DBCC, SZ_UNDEF));
2013 break;
2014 }
2015 #endif
2016 add_fix ('w', &opP->disp, 1, 0);
2017 }
2018 addword (0);
2019 break;
2020 case 'C': /* Fixed size LONG coproc branches */
2021 add_fix ('l', &opP->disp, 1, 0);
2022 addword (0);
2023 addword (0);
2024 break;
2025 case 'c': /* Var size Coprocesssor branches */
2026 if (subs (&opP->disp))
2027 {
2028 add_fix ('l', &opP->disp, 1, 0);
2029 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2030 }
2031 else if (adds (&opP->disp))
2032 add_frag (adds (&opP->disp), offs (&opP->disp),
2033 TAB (FBRANCH, SZ_UNDEF));
2034 else
2035 {
2036 /* add_frag((symbolS *) 0, offs(&opP->disp),
2037 TAB(FBRANCH,SHORT)); */
2038 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2039 add_fix ('l', &opP->disp, 1, 0);
2040 addword (0);
2041 addword (0);
2042 }
2043 break;
2044 default:
2045 abort ();
2046 }
2047 break;
2048
2049 case 'C': /* Ignore it */
2050 break;
2051
2052 case 'd': /* JF this is a kludge */
2053 install_operand ('s', opP->reg - ADDR);
2054 tmpreg = get_num (&opP->disp, 80);
2055 if (!issword (tmpreg))
2056 {
2057 as_warn ("Expression out of range, using 0");
2058 tmpreg = 0;
2059 }
2060 addword (tmpreg);
2061 break;
2062
2063 case 'D':
2064 install_operand (s[1], opP->reg - DATA);
2065 break;
2066
2067 case 'F':
2068 install_operand (s[1], opP->reg - FP0);
2069 break;
2070
2071 case 'I':
2072 tmpreg = opP->reg - COP0;
2073 install_operand (s[1], tmpreg);
2074 break;
2075
2076 case 'J': /* JF foo */
2077 switch (opP->reg)
2078 {
2079 case SFC:
2080 tmpreg = 0x000;
2081 break;
2082 case DFC:
2083 tmpreg = 0x001;
2084 break;
2085 case CACR:
2086 tmpreg = 0x002;
2087 break;
2088 case TC:
2089 tmpreg = 0x003;
2090 break;
2091 case ITT0:
2092 tmpreg = 0x004;
2093 break;
2094 case ITT1:
2095 tmpreg = 0x005;
2096 break;
2097 case DTT0:
2098 tmpreg = 0x006;
2099 break;
2100 case DTT1:
2101 tmpreg = 0x007;
2102 break;
2103 case BUSCR:
2104 tmpreg = 0x008;
2105 break;
2106
2107 case USP:
2108 tmpreg = 0x800;
2109 break;
2110 case VBR:
2111 tmpreg = 0x801;
2112 break;
2113 case CAAR:
2114 tmpreg = 0x802;
2115 break;
2116 case MSP:
2117 tmpreg = 0x803;
2118 break;
2119 case ISP:
2120 tmpreg = 0x804;
2121 break;
2122 case MMUSR:
2123 tmpreg = 0x805;
2124 break;
2125 case URP:
2126 tmpreg = 0x806;
2127 break;
2128 case SRP:
2129 tmpreg = 0x807;
2130 break;
2131 case PCR:
2132 tmpreg = 0x808;
2133 break;
2134 default:
2135 abort ();
2136 }
2137 install_operand (s[1], tmpreg);
2138 break;
2139
2140 case 'k':
2141 tmpreg = get_num (&opP->disp, 55);
2142 install_operand (s[1], tmpreg & 0x7f);
2143 break;
2144
2145 case 'l':
2146 tmpreg = opP->mask;
2147 if (s[1] == 'w')
2148 {
2149 if (tmpreg & 0x7FF0000)
2150 as_bad ("Floating point register in register list");
2151 insop (reverse_16_bits (tmpreg), opcode);
2152 }
2153 else
2154 {
2155 if (tmpreg & 0x700FFFF)
2156 as_bad ("Wrong register in floating-point reglist");
2157 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2158 }
2159 break;
2160
2161 case 'L':
2162 tmpreg = opP->mask;
2163 if (s[1] == 'w')
2164 {
2165 if (tmpreg & 0x7FF0000)
2166 as_bad ("Floating point register in register list");
2167 insop (tmpreg, opcode);
2168 }
2169 else if (s[1] == '8')
2170 {
2171 if (tmpreg & 0x0FFFFFF)
2172 as_bad ("incorrect register in reglist");
2173 install_operand (s[1], tmpreg >> 24);
2174 }
2175 else
2176 {
2177 if (tmpreg & 0x700FFFF)
2178 as_bad ("wrong register in floating-point reglist");
2179 else
2180 install_operand (s[1], tmpreg >> 16);
2181 }
2182 break;
2183
2184 case 'M':
2185 install_operand (s[1], get_num (&opP->disp, 60));
2186 break;
2187
2188 case 'O':
2189 tmpreg = ((opP->mode == DREG)
2190 ? 0x20 + opP->reg - DATA
2191 : (get_num (&opP->disp, 40) & 0x1F));
2192 install_operand (s[1], tmpreg);
2193 break;
2194
2195 case 'Q':
2196 tmpreg = get_num (&opP->disp, 10);
2197 if (tmpreg == 8)
2198 tmpreg = 0;
2199 install_operand (s[1], tmpreg);
2200 break;
2201
2202 case 'R':
2203 /* This depends on the fact that ADDR registers are eight
2204 more than their corresponding DATA regs, so the result
2205 will have the ADDR_REG bit set */
2206 install_operand (s[1], opP->reg - DATA);
2207 break;
2208
2209 case 'r':
2210 if (opP->mode == AINDR)
2211 install_operand (s[1], opP->reg - DATA);
2212 else
2213 install_operand (s[1], opP->index.reg - DATA);
2214 break;
2215
2216 case 's':
2217 if (opP->reg == FPI)
2218 tmpreg = 0x1;
2219 else if (opP->reg == FPS)
2220 tmpreg = 0x2;
2221 else if (opP->reg == FPC)
2222 tmpreg = 0x4;
2223 else
2224 abort ();
2225 install_operand (s[1], tmpreg);
2226 break;
2227
2228 case 'S': /* Ignore it */
2229 break;
2230
2231 case 'T':
2232 install_operand (s[1], get_num (&opP->disp, 30));
2233 break;
2234
2235 case 'U': /* Ignore it */
2236 break;
2237
2238 case 'c':
2239 switch (opP->reg)
2240 {
2241 case NC:
2242 tmpreg = 0;
2243 break;
2244 case DC:
2245 tmpreg = 1;
2246 break;
2247 case IC:
2248 tmpreg = 2;
2249 break;
2250 case BC:
2251 tmpreg = 3;
2252 break;
2253 default:
2254 as_fatal ("failed sanity check");
2255 } /* switch on cache token */
2256 install_operand (s[1], tmpreg);
2257 break;
2258 #ifndef NO_68851
2259 /* JF: These are out of order, I fear. */
2260 case 'f':
2261 switch (opP->reg)
2262 {
2263 case SFC:
2264 tmpreg = 0;
2265 break;
2266 case DFC:
2267 tmpreg = 1;
2268 break;
2269 default:
2270 abort ();
2271 }
2272 install_operand (s[1], tmpreg);
2273 break;
2274
2275 case '0':
2276 case '1':
2277 case '2':
2278 switch (opP->reg)
2279 {
2280 case TC:
2281 tmpreg = 0;
2282 break;
2283 case CAL:
2284 tmpreg = 4;
2285 break;
2286 case VAL:
2287 tmpreg = 5;
2288 break;
2289 case SCC:
2290 tmpreg = 6;
2291 break;
2292 case AC:
2293 tmpreg = 7;
2294 break;
2295 default:
2296 abort ();
2297 }
2298 install_operand (s[1], tmpreg);
2299 break;
2300
2301 case 'V':
2302 if (opP->reg == VAL)
2303 break;
2304 abort ();
2305
2306 case 'W':
2307 switch (opP->reg)
2308 {
2309 case DRP:
2310 tmpreg = 1;
2311 break;
2312 case SRP:
2313 tmpreg = 2;
2314 break;
2315 case CRP:
2316 tmpreg = 3;
2317 break;
2318 default:
2319 abort ();
2320 }
2321 install_operand (s[1], tmpreg);
2322 break;
2323
2324 case 'X':
2325 switch (opP->reg)
2326 {
2327 case BAD:
2328 case BAD + 1:
2329 case BAD + 2:
2330 case BAD + 3:
2331 case BAD + 4:
2332 case BAD + 5:
2333 case BAD + 6:
2334 case BAD + 7:
2335 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2336 break;
2337
2338 case BAC:
2339 case BAC + 1:
2340 case BAC + 2:
2341 case BAC + 3:
2342 case BAC + 4:
2343 case BAC + 5:
2344 case BAC + 6:
2345 case BAC + 7:
2346 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2347 break;
2348
2349 default:
2350 abort ();
2351 }
2352 install_operand (s[1], tmpreg);
2353 break;
2354 case 'Y':
2355 know (opP->reg == PSR);
2356 break;
2357 case 'Z':
2358 know (opP->reg == PCSR);
2359 break;
2360 #endif /* m68851 */
2361 case '3':
2362 switch (opP->reg)
2363 {
2364 case TT0:
2365 tmpreg = 2;
2366 break;
2367 case TT1:
2368 tmpreg = 3;
2369 break;
2370 default:
2371 abort ();
2372 }
2373 install_operand (s[1], tmpreg);
2374 break;
2375 case 't':
2376 tmpreg = get_num (&opP->disp, 20);
2377 install_operand (s[1], tmpreg);
2378 break;
2379 case '_': /* used only for move16 absolute 32-bit address */
2380 tmpreg = get_num (&opP->disp, 80);
2381 addword (tmpreg >> 16);
2382 addword (tmpreg & 0xFFFF);
2383 break;
2384 default:
2385 abort ();
2386 }
2387 }
2388
2389 /* By the time whe get here (FINALLY) the_ins contains the complete
2390 instruction, ready to be emitted. . . */
2391 }
2392
2393 static int
2394 reverse_16_bits (in)
2395 int in;
2396 {
2397 int out = 0;
2398 int n;
2399
2400 static int mask[16] =
2401 {
2402 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2403 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2404 };
2405 for (n = 0; n < 16; n++)
2406 {
2407 if (in & mask[n])
2408 out |= mask[15 - n];
2409 }
2410 return out;
2411 } /* reverse_16_bits() */
2412
2413 static int
2414 reverse_8_bits (in)
2415 int in;
2416 {
2417 int out = 0;
2418 int n;
2419
2420 static int mask[8] =
2421 {
2422 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2423 };
2424
2425 for (n = 0; n < 8; n++)
2426 {
2427 if (in & mask[n])
2428 out |= mask[7 - n];
2429 }
2430 return out;
2431 } /* reverse_8_bits() */
2432
2433 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2434 (that value is chosen in the frag_var call in md_assemble). TYPE
2435 is the subtype of the frag to be generated; its primary type is
2436 rs_machine_dependent.
2437
2438 The TYPE parameter is also used by md_convert_frag_1 and
2439 md_estimate_size_before_relax. The appropriate type of fixup will
2440 be emitted by md_convert_frag_1.
2441
2442 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2443 static void
2444 install_operand (mode, val)
2445 int mode;
2446 int val;
2447 {
2448 switch (mode)
2449 {
2450 case 's':
2451 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2452 break;
2453 case 'd':
2454 the_ins.opcode[0] |= val << 9;
2455 break;
2456 case '1':
2457 the_ins.opcode[1] |= val << 12;
2458 break;
2459 case '2':
2460 the_ins.opcode[1] |= val << 6;
2461 break;
2462 case '3':
2463 the_ins.opcode[1] |= val;
2464 break;
2465 case '4':
2466 the_ins.opcode[2] |= val << 12;
2467 break;
2468 case '5':
2469 the_ins.opcode[2] |= val << 6;
2470 break;
2471 case '6':
2472 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2473 three words long! */
2474 the_ins.numo++;
2475 the_ins.opcode[2] |= val;
2476 break;
2477 case '7':
2478 the_ins.opcode[1] |= val << 7;
2479 break;
2480 case '8':
2481 the_ins.opcode[1] |= val << 10;
2482 break;
2483 #ifndef NO_68851
2484 case '9':
2485 the_ins.opcode[1] |= val << 5;
2486 break;
2487 #endif
2488
2489 case 't':
2490 the_ins.opcode[1] |= (val << 10) | (val << 7);
2491 break;
2492 case 'D':
2493 the_ins.opcode[1] |= (val << 12) | val;
2494 break;
2495 case 'g':
2496 the_ins.opcode[0] |= val = 0xff;
2497 break;
2498 case 'i':
2499 the_ins.opcode[0] |= val << 9;
2500 break;
2501 case 'C':
2502 the_ins.opcode[1] |= val;
2503 break;
2504 case 'j':
2505 the_ins.opcode[1] |= val;
2506 the_ins.numo++; /* What a hack */
2507 break;
2508 case 'k':
2509 the_ins.opcode[1] |= val << 4;
2510 break;
2511 case 'b':
2512 case 'w':
2513 case 'l':
2514 break;
2515 case 'e':
2516 the_ins.opcode[0] |= (val << 6);
2517 break;
2518 case 'L':
2519 the_ins.opcode[1] = (val >> 16);
2520 the_ins.opcode[2] = val & 0xffff;
2521 break;
2522 case 'c':
2523 default:
2524 as_fatal ("failed sanity check.");
2525 }
2526 } /* install_operand() */
2527
2528 static void
2529 install_gen_operand (mode, val)
2530 int mode;
2531 int val;
2532 {
2533 switch (mode)
2534 {
2535 case 's':
2536 the_ins.opcode[0] |= val;
2537 break;
2538 case 'd':
2539 /* This is a kludge!!! */
2540 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2541 break;
2542 case 'b':
2543 case 'w':
2544 case 'l':
2545 case 'f':
2546 case 'F':
2547 case 'x':
2548 case 'p':
2549 the_ins.opcode[0] |= val;
2550 break;
2551 /* more stuff goes here */
2552 default:
2553 as_fatal ("failed sanity check.");
2554 }
2555 } /* install_gen_operand() */
2556
2557 /*
2558 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2559 * then deal with the bitfield hack.
2560 */
2561
2562 static char *
2563 crack_operand (str, opP)
2564 register char *str;
2565 register struct m68k_op *opP;
2566 {
2567 register int parens;
2568 register int c;
2569 register char *beg_str;
2570 int inquote = 0;
2571
2572 if (!str)
2573 {
2574 return str;
2575 }
2576 beg_str = str;
2577 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2578 {
2579 if (! inquote)
2580 {
2581 if (*str == '(')
2582 parens++;
2583 else if (*str == ')')
2584 {
2585 if (!parens)
2586 { /* ERROR */
2587 opP->error = "Extra )";
2588 return str;
2589 }
2590 --parens;
2591 }
2592 }
2593 if (flag_mri && *str == '\'')
2594 inquote = ! inquote;
2595 }
2596 if (!*str && parens)
2597 { /* ERROR */
2598 opP->error = "Missing )";
2599 return str;
2600 }
2601 c = *str;
2602 *str = '\0';
2603 if (m68k_ip_op (beg_str, opP) != 0)
2604 {
2605 *str = c;
2606 return str;
2607 }
2608 *str = c;
2609 if (c == '}')
2610 c = *++str; /* JF bitfield hack */
2611 if (c)
2612 {
2613 c = *++str;
2614 if (!c)
2615 as_bad ("Missing operand");
2616 }
2617 return str;
2618 }
2619
2620 /* This is the guts of the machine-dependent assembler. STR points to a
2621 machine dependent instruction. This function is supposed to emit
2622 the frags/bytes it assembles to.
2623 */
2624
2625 void
2626 insert_reg (regname, regnum)
2627 char *regname;
2628 int regnum;
2629 {
2630 char buf[100];
2631 int i;
2632
2633 #ifdef REGISTER_PREFIX
2634 if (!flag_reg_prefix_optional)
2635 {
2636 buf[0] = REGISTER_PREFIX;
2637 strcpy (buf + 1, regname);
2638 regname = buf;
2639 }
2640 #endif
2641
2642 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2643 &zero_address_frag));
2644
2645 for (i = 0; regname[i]; i++)
2646 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2647 buf[i] = '\0';
2648
2649 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2650 &zero_address_frag));
2651 }
2652
2653 struct init_entry
2654 {
2655 const char *name;
2656 int number;
2657 };
2658
2659 static const struct init_entry init_table[] =
2660 {
2661 { "d0", DATA0 },
2662 { "d1", DATA1 },
2663 { "d2", DATA2 },
2664 { "d3", DATA3 },
2665 { "d4", DATA4 },
2666 { "d5", DATA5 },
2667 { "d6", DATA6 },
2668 { "d7", DATA7 },
2669 { "a0", ADDR0 },
2670 { "a1", ADDR1 },
2671 { "a2", ADDR2 },
2672 { "a3", ADDR3 },
2673 { "a4", ADDR4 },
2674 { "a5", ADDR5 },
2675 { "a6", ADDR6 },
2676 { "fp", ADDR6 },
2677 { "a7", ADDR7 },
2678 { "sp", ADDR7 },
2679 { "ssp", ADDR7 },
2680 { "fp0", FP0 },
2681 { "fp1", FP1 },
2682 { "fp2", FP2 },
2683 { "fp3", FP3 },
2684 { "fp4", FP4 },
2685 { "fp5", FP5 },
2686 { "fp6", FP6 },
2687 { "fp7", FP7 },
2688 { "fpi", FPI },
2689 { "fpiar", FPI },
2690 { "fpc", FPI },
2691 { "fps", FPS },
2692 { "fpsr", FPS },
2693 { "fpc", FPC },
2694 { "fpcr", FPC },
2695 { "control", FPC },
2696 { "status", FPS },
2697 { "iaddr", FPI },
2698
2699 { "cop0", COP0 },
2700 { "cop1", COP1 },
2701 { "cop2", COP2 },
2702 { "cop3", COP3 },
2703 { "cop4", COP4 },
2704 { "cop5", COP5 },
2705 { "cop6", COP6 },
2706 { "cop7", COP7 },
2707 { "pc", PC },
2708 { "zpc", ZPC },
2709 { "sr", SR },
2710
2711 { "ccr", CCR },
2712 { "cc", CCR },
2713
2714 { "usp", USP },
2715 { "isp", ISP },
2716 { "sfc", SFC },
2717 { "sfcr", SFC },
2718 { "dfc", DFC },
2719 { "dfcr", DFC },
2720 { "cacr", CACR },
2721 { "caar", CAAR },
2722
2723 { "vbr", VBR },
2724
2725 { "msp", MSP },
2726 { "itt0", ITT0 },
2727 { "itt1", ITT1 },
2728 { "dtt0", DTT0 },
2729 { "dtt1", DTT1 },
2730 { "mmusr", MMUSR },
2731 { "tc", TC },
2732 { "srp", SRP },
2733 { "urp", URP },
2734 { "buscr", BUSCR },
2735 { "pcr", PCR },
2736
2737 { "ac", AC },
2738 { "bc", BC },
2739 { "cal", CAL },
2740 { "crp", CRP },
2741 { "drp", DRP },
2742 { "pcsr", PCSR },
2743 { "psr", PSR },
2744 { "scc", SCC },
2745 { "val", VAL },
2746 { "bad0", BAD0 },
2747 { "bad1", BAD1 },
2748 { "bad2", BAD2 },
2749 { "bad3", BAD3 },
2750 { "bad4", BAD4 },
2751 { "bad5", BAD5 },
2752 { "bad6", BAD6 },
2753 { "bad7", BAD7 },
2754 { "bac0", BAC0 },
2755 { "bac1", BAC1 },
2756 { "bac2", BAC2 },
2757 { "bac3", BAC3 },
2758 { "bac4", BAC4 },
2759 { "bac5", BAC5 },
2760 { "bac6", BAC6 },
2761 { "bac7", BAC7 },
2762
2763 { "ic", IC },
2764 { "dc", DC },
2765 { "nc", NC },
2766
2767 { "tt0", TT0 },
2768 { "tt1", TT1 },
2769 /* 68ec030 versions of same */
2770 { "ac0", TT0 },
2771 { "ac1", TT1 },
2772 /* 68ec030 access control unit, identical to 030 MMU status reg */
2773 { "acusr", PSR },
2774
2775 /* Suppressed data and address registers. */
2776 { "zd0", ZDATA0 },
2777 { "zd1", ZDATA1 },
2778 { "zd2", ZDATA2 },
2779 { "zd3", ZDATA3 },
2780 { "zd4", ZDATA4 },
2781 { "zd5", ZDATA5 },
2782 { "zd6", ZDATA6 },
2783 { "zd7", ZDATA7 },
2784 { "za0", ZADDR0 },
2785 { "za1", ZADDR1 },
2786 { "za2", ZADDR2 },
2787 { "za3", ZADDR3 },
2788 { "za4", ZADDR4 },
2789 { "za5", ZADDR5 },
2790 { "za6", ZADDR6 },
2791 { "za7", ZADDR7 },
2792
2793 { 0, 0 }
2794 };
2795
2796 void
2797 init_regtable ()
2798 {
2799 int i;
2800 for (i = 0; init_table[i].name; i++)
2801 insert_reg (init_table[i].name, init_table[i].number);
2802 }
2803
2804 static int no_68851, no_68881;
2805
2806 #ifdef OBJ_AOUT
2807 /* a.out machine type. Default to 68020. */
2808 int m68k_aout_machtype = 2;
2809 #endif
2810
2811 void
2812 md_assemble (str)
2813 char *str;
2814 {
2815 const char *er;
2816 short *fromP;
2817 char *toP = NULL;
2818 int m, n = 0;
2819 char *to_beg_P;
2820 int shorts_this_frag;
2821 fixS *fixP;
2822
2823 /* In MRI mode, the instruction and operands are separated by a
2824 space. Anything following the operands is a comment. The label
2825 has already been removed. */
2826 if (flag_mri)
2827 {
2828 char *s;
2829 int fields = 0;
2830 int infield = 0;
2831 int inquote = 0;
2832
2833 for (s = str; *s != '\0'; s++)
2834 {
2835 if ((*s == ' ' || *s == '\t') && ! inquote)
2836 {
2837 if (infield)
2838 {
2839 ++fields;
2840 if (fields >= 2)
2841 {
2842 *s = '\0';
2843 break;
2844 }
2845 infield = 0;
2846 }
2847 }
2848 else
2849 {
2850 if (! infield)
2851 infield = 1;
2852 if (*s == '\'')
2853 inquote = ! inquote;
2854 }
2855 }
2856 }
2857
2858 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2859 m68k_ip (str);
2860 er = the_ins.error;
2861 if (!er)
2862 {
2863 for (n = 0; n < the_ins.numargs; n++)
2864 if (the_ins.operands[n].error)
2865 {
2866 er = the_ins.operands[n].error;
2867 break;
2868 }
2869 }
2870 if (er)
2871 {
2872 as_bad ("%s -- statement `%s' ignored", er, str);
2873 return;
2874 }
2875
2876 if (the_ins.nfrag == 0)
2877 {
2878 /* No frag hacking involved; just put it out */
2879 toP = frag_more (2 * the_ins.numo);
2880 fromP = &the_ins.opcode[0];
2881 for (m = the_ins.numo; m; --m)
2882 {
2883 md_number_to_chars (toP, (long) (*fromP), 2);
2884 toP += 2;
2885 fromP++;
2886 }
2887 /* put out symbol-dependent info */
2888 for (m = 0; m < the_ins.nrel; m++)
2889 {
2890 switch (the_ins.reloc[m].wid)
2891 {
2892 case 'B':
2893 n = 1;
2894 break;
2895 case 'b':
2896 n = 1;
2897 break;
2898 case '3':
2899 n = 2;
2900 break;
2901 case 'w':
2902 n = 2;
2903 break;
2904 case 'l':
2905 n = 4;
2906 break;
2907 default:
2908 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2909 the_ins.reloc[m].wid);
2910 }
2911
2912 fixP = fix_new_exp (frag_now,
2913 ((toP - frag_now->fr_literal)
2914 - the_ins.numo * 2 + the_ins.reloc[m].n),
2915 n,
2916 &the_ins.reloc[m].exp,
2917 the_ins.reloc[m].pcrel,
2918 NO_RELOC);
2919 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2920 }
2921 return;
2922 }
2923
2924 /* There's some frag hacking */
2925 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2926 {
2927 int wid;
2928
2929 if (n == 0)
2930 wid = 2 * the_ins.fragb[n].fragoff;
2931 else
2932 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2933 toP = frag_more (wid);
2934 to_beg_P = toP;
2935 shorts_this_frag = 0;
2936 for (m = wid / 2; m; --m)
2937 {
2938 md_number_to_chars (toP, (long) (*fromP), 2);
2939 toP += 2;
2940 fromP++;
2941 shorts_this_frag++;
2942 }
2943 for (m = 0; m < the_ins.nrel; m++)
2944 {
2945 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2946 {
2947 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2948 break;
2949 }
2950 wid = the_ins.reloc[m].wid;
2951 if (wid == 0)
2952 continue;
2953 the_ins.reloc[m].wid = 0;
2954 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2955
2956 fixP = fix_new_exp (frag_now,
2957 ((toP - frag_now->fr_literal)
2958 - the_ins.numo * 2 + the_ins.reloc[m].n),
2959 wid,
2960 &the_ins.reloc[m].exp,
2961 the_ins.reloc[m].pcrel,
2962 NO_RELOC);
2963 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2964 }
2965 (void) frag_var (rs_machine_dependent, 10, 0,
2966 (relax_substateT) (the_ins.fragb[n].fragty),
2967 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2968 }
2969 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2970 shorts_this_frag = 0;
2971 if (n)
2972 {
2973 toP = frag_more (n * sizeof (short));
2974 while (n--)
2975 {
2976 md_number_to_chars (toP, (long) (*fromP), 2);
2977 toP += 2;
2978 fromP++;
2979 shorts_this_frag++;
2980 }
2981 }
2982 for (m = 0; m < the_ins.nrel; m++)
2983 {
2984 int wid;
2985
2986 wid = the_ins.reloc[m].wid;
2987 if (wid == 0)
2988 continue;
2989 the_ins.reloc[m].wid = 0;
2990 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2991
2992 fixP = fix_new_exp (frag_now,
2993 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2994 - shorts_this_frag * 2),
2995 wid,
2996 &the_ins.reloc[m].exp,
2997 the_ins.reloc[m].pcrel,
2998 NO_RELOC);
2999 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3000 }
3001 }
3002
3003 void
3004 md_begin ()
3005 {
3006 /*
3007 * md_begin -- set up hash tables with 68000 instructions.
3008 * similar to what the vax assembler does. ---phr
3009 */
3010 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3011 a copy of it at runtime, adding in the information we want but isn't
3012 there. I think it'd be better to have an awk script hack the table
3013 at compile time. Or even just xstr the table and use it as-is. But
3014 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3015 names. */
3016
3017 register const struct m68k_opcode *ins;
3018 register struct m68k_incant *hack, *slak;
3019 register const char *retval = 0; /* empty string, or error msg text */
3020 register unsigned int i;
3021 register char c;
3022
3023 if (flag_mri)
3024 {
3025 flag_reg_prefix_optional = 1;
3026 m68k_abspcadd = 1;
3027 m68k_rel32 = 0;
3028 }
3029
3030 op_hash = hash_new ();
3031
3032 obstack_begin (&robyn, 4000);
3033 for (i = 0; i < m68k_numopcodes; i++)
3034 {
3035 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3036 do
3037 {
3038 ins = &m68k_opcodes[i];
3039 /* We *could* ignore insns that don't match our arch here
3040 but just leaving them out of the hash. */
3041 slak->m_operands = ins->args;
3042 slak->m_opnum = strlen (slak->m_operands) / 2;
3043 slak->m_arch = ins->arch;
3044 slak->m_opcode = ins->opcode;
3045 /* This is kludgey */
3046 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3047 if (i + 1 != m68k_numopcodes
3048 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3049 {
3050 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3051 i++;
3052 }
3053 else
3054 slak->m_next = 0;
3055 slak = slak->m_next;
3056 }
3057 while (slak);
3058
3059 retval = hash_insert (op_hash, ins->name, (char *) hack);
3060 if (retval)
3061 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3062 }
3063
3064 for (i = 0; i < m68k_numaliases; i++)
3065 {
3066 const char *name = m68k_opcode_aliases[i].primary;
3067 const char *alias = m68k_opcode_aliases[i].alias;
3068 PTR val = hash_find (op_hash, name);
3069 if (!val)
3070 as_fatal ("Internal Error: Can't find %s in hash table", name);
3071 retval = hash_insert (op_hash, alias, val);
3072 if (retval)
3073 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3074 }
3075
3076 /* In MRI mode, all unsized branches are variable sized. Normally,
3077 they are word sized. */
3078 if (flag_mri)
3079 {
3080 static struct m68k_opcode_alias mri_aliases[] =
3081 {
3082 { "bhi", "jhi", },
3083 { "bls", "jls", },
3084 { "bcc", "jcc", },
3085 { "bcs", "jcs", },
3086 { "bne", "jne", },
3087 { "beq", "jeq", },
3088 { "bvc", "jvc", },
3089 { "bvs", "jvs", },
3090 { "bpl", "jpl", },
3091 { "bmi", "jmi", },
3092 { "bge", "jge", },
3093 { "blt", "jlt", },
3094 { "bgt", "jgt", },
3095 { "ble", "jle", },
3096 { "bra", "jra", },
3097 { "bsr", "jbsr", },
3098 };
3099
3100 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3101 {
3102 const char *name = mri_aliases[i].primary;
3103 const char *alias = mri_aliases[i].alias;
3104 PTR val = hash_find (op_hash, name);
3105 if (!val)
3106 as_fatal ("Internal Error: Can't find %s in hash table", name);
3107 retval = hash_jam (op_hash, alias, val);
3108 if (retval)
3109 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3110 }
3111 }
3112
3113 for (i = 0; i < sizeof (mklower_table); i++)
3114 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3115
3116 for (i = 0; i < sizeof (notend_table); i++)
3117 {
3118 notend_table[i] = 0;
3119 alt_notend_table[i] = 0;
3120 }
3121 notend_table[','] = 1;
3122 notend_table['{'] = 1;
3123 notend_table['}'] = 1;
3124 alt_notend_table['a'] = 1;
3125 alt_notend_table['A'] = 1;
3126 alt_notend_table['d'] = 1;
3127 alt_notend_table['D'] = 1;
3128 alt_notend_table['#'] = 1;
3129 alt_notend_table['&'] = 1;
3130 alt_notend_table['f'] = 1;
3131 alt_notend_table['F'] = 1;
3132 #ifdef REGISTER_PREFIX
3133 alt_notend_table[REGISTER_PREFIX] = 1;
3134 #endif
3135
3136 /* We need to put '(' in alt_notend_table to handle
3137 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3138 */
3139 alt_notend_table['('] = 1;
3140
3141 /* We need to put '@' in alt_notend_table to handle
3142 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3143 */
3144 alt_notend_table['@'] = 1;
3145
3146 #ifndef MIT_SYNTAX_ONLY
3147 /* Insert pseudo ops, these have to go into the opcode table since
3148 gas expects pseudo ops to start with a dot */
3149 {
3150 int n = 0;
3151 while (mote_pseudo_table[n].poc_name)
3152 {
3153 hack = (struct m68k_incant *)
3154 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3155 hash_insert (op_hash,
3156 mote_pseudo_table[n].poc_name, (char *) hack);
3157 hack->m_operands = 0;
3158 hack->m_opnum = n;
3159 n++;
3160 }
3161 }
3162 #endif
3163
3164 init_regtable ();
3165 }
3166
3167 void
3168 m68k_init_after_args ()
3169 {
3170 if (cpu_of_arch (current_architecture) == 0)
3171 {
3172 int i;
3173 const char *default_cpu = TARGET_CPU;
3174
3175 if (*default_cpu == 'm')
3176 default_cpu++;
3177 for (i = 0; i < n_archs; i++)
3178 if (strcasecmp (default_cpu, archs[i].name) == 0)
3179 break;
3180 if (i == n_archs)
3181 {
3182 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3183 current_architecture |= m68020;
3184 }
3185 else
3186 current_architecture |= archs[i].arch;
3187 }
3188 /* Permit m68881 specification with all cpus; those that can't work
3189 with a coprocessor could be doing emulation. */
3190 if (current_architecture & m68851)
3191 {
3192 if (current_architecture & m68040)
3193 {
3194 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3195 }
3196 }
3197 /* What other incompatibilities could we check for? */
3198
3199 /* Toss in some default assumptions about coprocessors. */
3200 if (!no_68881
3201 && (cpu_of_arch (current_architecture)
3202 /* Can CPU32 have a 68881 coprocessor?? */
3203 & (m68020 | m68030 | cpu32)))
3204 {
3205 current_architecture |= m68881;
3206 }
3207 if (!no_68851
3208 && (cpu_of_arch (current_architecture) & m68020up) != 0
3209 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3210 {
3211 current_architecture |= m68851;
3212 }
3213 if (no_68881 && (current_architecture & m68881))
3214 as_bad ("options for 68881 and no-68881 both given");
3215 if (no_68851 && (current_architecture & m68851))
3216 as_bad ("options for 68851 and no-68851 both given");
3217
3218 #ifdef OBJ_AOUT
3219 /* Work out the magic number. This isn't very general. */
3220 if (current_architecture & m68000)
3221 m68k_aout_machtype = 0;
3222 else if (current_architecture & m68010)
3223 m68k_aout_machtype = 1;
3224 else if (current_architecture & m68020)
3225 m68k_aout_machtype = 2;
3226 else
3227 m68k_aout_machtype = 2;
3228 #endif
3229
3230 /* Note which set of "movec" control registers is available. */
3231 switch (cpu_of_arch (current_architecture))
3232 {
3233 case m68000:
3234 control_regs = m68000_control_regs;
3235 break;
3236 case m68010:
3237 control_regs = m68010_control_regs;
3238 break;
3239 case m68020:
3240 case m68030:
3241 control_regs = m68020_control_regs;
3242 break;
3243 case m68040:
3244 control_regs = m68040_control_regs;
3245 break;
3246 case m68060:
3247 control_regs = m68060_control_regs;
3248 break;
3249 case cpu32:
3250 control_regs = cpu32_control_regs;
3251 break;
3252 default:
3253 abort ();
3254 }
3255
3256 if (cpu_of_arch (current_architecture) < m68020)
3257 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3258 }
3259
3260 /* Equal to MAX_PRECISION in atof-ieee.c */
3261 #define MAX_LITTLENUMS 6
3262
3263 /* Turn a string in input_line_pointer into a floating point constant
3264 of type type, and store the appropriate bytes in *litP. The number
3265 of LITTLENUMS emitted is stored in *sizeP . An error message is
3266 returned, or NULL on OK. */
3267
3268 char *
3269 md_atof (type, litP, sizeP)
3270 char type;
3271 char *litP;
3272 int *sizeP;
3273 {
3274 int prec;
3275 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3276 LITTLENUM_TYPE *wordP;
3277 char *t;
3278 char *atof_ieee ();
3279
3280 switch (type)
3281 {
3282 case 'f':
3283 case 'F':
3284 case 's':
3285 case 'S':
3286 prec = 2;
3287 break;
3288
3289 case 'd':
3290 case 'D':
3291 case 'r':
3292 case 'R':
3293 prec = 4;
3294 break;
3295
3296 case 'x':
3297 case 'X':
3298 prec = 6;
3299 break;
3300
3301 case 'p':
3302 case 'P':
3303 prec = 6;
3304 break;
3305
3306 default:
3307 *sizeP = 0;
3308 return "Bad call to MD_ATOF()";
3309 }
3310 t = atof_ieee (input_line_pointer, type, words);
3311 if (t)
3312 input_line_pointer = t;
3313
3314 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3315 for (wordP = words; prec--;)
3316 {
3317 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3318 litP += sizeof (LITTLENUM_TYPE);
3319 }
3320 return 0;
3321 }
3322
3323 void
3324 md_number_to_chars (buf, val, n)
3325 char *buf;
3326 valueT val;
3327 int n;
3328 {
3329 number_to_chars_bigendian (buf, val, n);
3330 }
3331
3332 static void
3333 md_apply_fix_2 (fixP, val)
3334 fixS *fixP;
3335 offsetT val;
3336 {
3337 addressT upper_limit;
3338 offsetT lower_limit;
3339
3340 /* This is unnecessary but it convinces the native rs6000 compiler
3341 to generate the code we want. */
3342 char *buf = fixP->fx_frag->fr_literal;
3343 buf += fixP->fx_where;
3344 /* end ibm compiler workaround */
3345
3346 if (val & 0x80000000)
3347 val |= ~(addressT)0x7fffffff;
3348 else
3349 val &= 0x7fffffff;
3350
3351 switch (fixP->fx_size)
3352 {
3353 /* The cast to offsetT below are necessary to make code correct for
3354 machines where ints are smaller than offsetT */
3355 case 1:
3356 *buf++ = val;
3357 upper_limit = 0x7f;
3358 lower_limit = - (offsetT) 0x80;
3359 break;
3360 case 2:
3361 *buf++ = (val >> 8);
3362 *buf++ = val;
3363 upper_limit = 0x7fff;
3364 lower_limit = - (offsetT) 0x8000;
3365 break;
3366 case 4:
3367 *buf++ = (val >> 24);
3368 *buf++ = (val >> 16);
3369 *buf++ = (val >> 8);
3370 *buf++ = val;
3371 upper_limit = 0x7fffffff;
3372 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3373 break;
3374 default:
3375 BAD_CASE (fixP->fx_size);
3376 }
3377
3378 /* Fix up a negative reloc. */
3379 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3380 {
3381 fixP->fx_addsy = fixP->fx_subsy;
3382 fixP->fx_subsy = NULL;
3383 fixP->fx_tcbit = 1;
3384 }
3385
3386 /* For non-pc-relative values, it's conceivable we might get something
3387 like "0xff" for a byte field. So extend the upper part of the range
3388 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3389 so that we can do any range checking at all. */
3390 if (!fixP->fx_pcrel)
3391 upper_limit = upper_limit * 2 + 1;
3392
3393 if ((addressT) val > upper_limit
3394 && (val > 0 || val < lower_limit))
3395 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3396
3397 /* A one byte PC-relative reloc means a short branch. We can't use
3398 a short branch with a value of 0 or -1, because those indicate
3399 different opcodes (branches with longer offsets). */
3400 if (fixP->fx_pcrel
3401 && fixP->fx_size == 1
3402 && (fixP->fx_addsy == NULL
3403 || S_IS_DEFINED (fixP->fx_addsy))
3404 && (val == 0 || val == -1))
3405 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3406 }
3407
3408 #ifdef BFD_ASSEMBLER
3409 int
3410 md_apply_fix (fixP, valp)
3411 fixS *fixP;
3412 valueT *valp;
3413 {
3414 md_apply_fix_2 (fixP, (addressT) *valp);
3415 return 1;
3416 }
3417 #else
3418 void md_apply_fix (fixP, val)
3419 fixS *fixP;
3420 long val;
3421 {
3422 md_apply_fix_2 (fixP, (addressT) val);
3423 }
3424 #endif
3425
3426 /* *fragP has been relaxed to its final size, and now needs to have
3427 the bytes inside it modified to conform to the new size There is UGLY
3428 MAGIC here. ..
3429 */
3430 void
3431 md_convert_frag_1 (fragP)
3432 register fragS *fragP;
3433 {
3434 long disp;
3435 long ext = 0;
3436 fixS *fixP;
3437
3438 /* Address in object code of the displacement. */
3439 register int object_address = fragP->fr_fix + fragP->fr_address;
3440
3441 /* Address in gas core of the place to store the displacement. */
3442 /* This convinces the native rs6000 compiler to generate the code we
3443 want. */
3444 register char *buffer_address = fragP->fr_literal;
3445 buffer_address += fragP->fr_fix;
3446 /* end ibm compiler workaround */
3447
3448 /* The displacement of the address, from current location. */
3449 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3450 disp = (disp + fragP->fr_offset) - object_address;
3451
3452 #ifdef BFD_ASSEMBLER
3453 disp += fragP->fr_symbol->sy_frag->fr_address;
3454 #endif
3455
3456 switch (fragP->fr_subtype)
3457 {
3458 case TAB (BCC68000, BYTE):
3459 case TAB (ABRANCH, BYTE):
3460 know (issbyte (disp));
3461 if (disp == 0)
3462 as_bad ("short branch with zero offset: use :w");
3463 fragP->fr_opcode[1] = disp;
3464 ext = 0;
3465 break;
3466 case TAB (DBCC, SHORT):
3467 know (issword (disp));
3468 ext = 2;
3469 break;
3470 case TAB (BCC68000, SHORT):
3471 case TAB (ABRANCH, SHORT):
3472 know (issword (disp));
3473 fragP->fr_opcode[1] = 0x00;
3474 ext = 2;
3475 break;
3476 case TAB (ABRANCH, LONG):
3477 if (cpu_of_arch (current_architecture) < m68020)
3478 {
3479 if (fragP->fr_opcode[0] == 0x61)
3480 /* BSR */
3481 {
3482 fragP->fr_opcode[0] = 0x4E;
3483 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3484
3485 fix_new (fragP,
3486 fragP->fr_fix,
3487 4,
3488 fragP->fr_symbol,
3489 fragP->fr_offset,
3490 0,
3491 NO_RELOC);
3492
3493 fragP->fr_fix += 4;
3494 ext = 0;
3495 }
3496 /* BRA */
3497 else if (fragP->fr_opcode[0] == 0x60)
3498 {
3499 fragP->fr_opcode[0] = 0x4E;
3500 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3501 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3502 fragP->fr_offset, 0, NO_RELOC);
3503 fragP->fr_fix += 4;
3504 ext = 0;
3505 }
3506 else
3507 {
3508 as_bad ("Long branch offset not supported.");
3509 }
3510 }
3511 else
3512 {
3513 fragP->fr_opcode[1] = (char) 0xff;
3514 ext = 4;
3515 }
3516 break;
3517 case TAB (BCC68000, LONG):
3518 /* only Bcc 68000 instructions can come here */
3519 /* change bcc into b!cc/jmp absl long */
3520 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3521 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3522
3523 /* JF: these used to be fr_opcode[2,3], but they may be in a
3524 different frag, in which case refering to them is a no-no.
3525 Only fr_opcode[0,1] are guaranteed to work. */
3526 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3527 *buffer_address++ = (char) 0xf9;
3528 fragP->fr_fix += 2; /* account for jmp instruction */
3529 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3530 fragP->fr_offset, 0, NO_RELOC);
3531 fragP->fr_fix += 4;
3532 ext = 0;
3533 break;
3534 case TAB (DBCC, LONG):
3535 /* only DBcc 68000 instructions can come here */
3536 /* change dbcc into dbcc/jmp absl long */
3537 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3538 *buffer_address++ = 0x00; /* branch offset = 4 */
3539 *buffer_address++ = 0x04;
3540 *buffer_address++ = 0x60; /* put in bra pc+6 */
3541 *buffer_address++ = 0x06;
3542 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3543 *buffer_address++ = (char) 0xf9;
3544
3545 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3546 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3547 fragP->fr_offset, 0, NO_RELOC);
3548 fragP->fr_fix += 4;
3549 ext = 0;
3550 break;
3551 case TAB (FBRANCH, SHORT):
3552 know ((fragP->fr_opcode[1] & 0x40) == 0);
3553 ext = 2;
3554 break;
3555 case TAB (FBRANCH, LONG):
3556 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3557 ext = 4;
3558 break;
3559 case TAB (PCREL, SHORT):
3560 ext = 2;
3561 break;
3562 case TAB (PCREL, LONG):
3563 /* The thing to do here is force it to ABSOLUTE LONG, since
3564 PCREL is really trying to shorten an ABSOLUTE address anyway */
3565 /* JF FOO This code has not been tested */
3566 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3567 0, NO_RELOC);
3568 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3569 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3570 (unsigned) fragP->fr_opcode[0],
3571 (unsigned long) fragP->fr_address);
3572 fragP->fr_opcode[1] &= ~0x3F;
3573 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3574 fragP->fr_fix += 4;
3575 ext = 0;
3576 break;
3577 case TAB (PCLEA, SHORT):
3578 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3579 fragP->fr_offset, 1, NO_RELOC);
3580 fragP->fr_opcode[1] &= ~0x3F;
3581 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3582 ext = 2;
3583 break;
3584 case TAB (PCLEA, LONG):
3585 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3586 fragP->fr_offset, 1, NO_RELOC);
3587 fixP->fx_pcrel_adjust = 2;
3588 /* Already set to mode 7.3; this indicates: PC indirect with
3589 suppressed index, 32-bit displacement. */
3590 *buffer_address++ = 0x01;
3591 *buffer_address++ = 0x70;
3592 fragP->fr_fix += 2;
3593 ext = 4;
3594 break;
3595
3596 case TAB (PCINDEX, BYTE):
3597 disp += 2;
3598 if (!issbyte (disp))
3599 {
3600 as_bad ("displacement doesn't fit in one byte");
3601 disp = 0;
3602 }
3603 assert (fragP->fr_fix >= 2);
3604 buffer_address[-2] &= ~1;
3605 buffer_address[-1] = disp;
3606 ext = 0;
3607 break;
3608 case TAB (PCINDEX, SHORT):
3609 disp += 2;
3610 assert (issword (disp));
3611 assert (fragP->fr_fix >= 2);
3612 buffer_address[-2] |= 0x1;
3613 buffer_address[-1] = 0x20;
3614 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3615 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3616 NO_RELOC);
3617 fixP->fx_pcrel_adjust = 2;
3618 ext = 2;
3619 break;
3620 case TAB (PCINDEX, LONG):
3621 disp += 2;
3622 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3623 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3624 NO_RELOC);
3625 fixP->fx_pcrel_adjust = 2;
3626 assert (fragP->fr_fix >= 2);
3627 buffer_address[-2] |= 0x1;
3628 buffer_address[-1] = 0x30;
3629 ext = 4;
3630 break;
3631 }
3632
3633 if (ext)
3634 {
3635 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3636 fragP->fr_fix += ext;
3637 }
3638 }
3639
3640 #ifndef BFD_ASSEMBLER
3641
3642 void
3643 md_convert_frag (headers, sec, fragP)
3644 object_headers *headers;
3645 segT sec;
3646 fragS *fragP;
3647 {
3648 md_convert_frag_1 (fragP);
3649 }
3650
3651 #else
3652
3653 void
3654 md_convert_frag (abfd, sec, fragP)
3655 bfd *abfd;
3656 segT sec;
3657 fragS *fragP;
3658 {
3659 md_convert_frag_1 (fragP);
3660 }
3661 #endif
3662
3663 /* Force truly undefined symbols to their maximum size, and generally set up
3664 the frag list to be relaxed
3665 */
3666 int
3667 md_estimate_size_before_relax (fragP, segment)
3668 register fragS *fragP;
3669 segT segment;
3670 {
3671 int old_fix;
3672 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3673
3674 old_fix = fragP->fr_fix;
3675
3676 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3677 switch (fragP->fr_subtype)
3678 {
3679
3680 case TAB (ABRANCH, SZ_UNDEF):
3681 {
3682 if ((fragP->fr_symbol != NULL) /* Not absolute */
3683 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3684 {
3685 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3686 break;
3687 }
3688 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3689 {
3690 /* On 68000, or for absolute value, switch to abs long */
3691 /* FIXME, we should check abs val, pick short or long */
3692 if (fragP->fr_opcode[0] == 0x61)
3693 {
3694 fragP->fr_opcode[0] = 0x4E;
3695 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3696 fix_new (fragP, fragP->fr_fix, 4,
3697 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3698 fragP->fr_fix += 4;
3699 frag_wane (fragP);
3700 }
3701 else if (fragP->fr_opcode[0] == 0x60)
3702 {
3703 fragP->fr_opcode[0] = 0x4E;
3704 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3705 fix_new (fragP, fragP->fr_fix, 4,
3706 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3707 fragP->fr_fix += 4;
3708 frag_wane (fragP);
3709 }
3710 else
3711 {
3712 as_warn ("Long branch offset to extern symbol not supported.");
3713 }
3714 }
3715 else
3716 { /* Symbol is still undefined. Make it simple */
3717 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3718 fragP->fr_offset, 1, NO_RELOC);
3719 fragP->fr_fix += 4;
3720 fragP->fr_opcode[1] = (char) 0xff;
3721 frag_wane (fragP);
3722 break;
3723 }
3724
3725 break;
3726 } /* case TAB(ABRANCH,SZ_UNDEF) */
3727
3728 case TAB (FBRANCH, SZ_UNDEF):
3729 {
3730 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3731 {
3732 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3733 fragP->fr_var += 2;
3734 }
3735 else
3736 {
3737 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3738 fragP->fr_offset, 1, NO_RELOC);
3739 fragP->fr_fix += 4;
3740 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3741 frag_wane (fragP);
3742 }
3743 break;
3744 } /* TAB(FBRANCH,SZ_UNDEF) */
3745
3746 case TAB (PCREL, SZ_UNDEF):
3747 {
3748 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3749 || flag_short_refs
3750 || cpu_of_arch (current_architecture) < m68020)
3751 {
3752 fragP->fr_subtype = TAB (PCREL, SHORT);
3753 fragP->fr_var += 2;
3754 }
3755 else
3756 {
3757 fragP->fr_subtype = TAB (PCREL, LONG);
3758 fragP->fr_var += 4;
3759 }
3760 break;
3761 } /* TAB(PCREL,SZ_UNDEF) */
3762
3763 case TAB (BCC68000, SZ_UNDEF):
3764 {
3765 if ((fragP->fr_symbol != NULL)
3766 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3767 {
3768 fragP->fr_subtype = TAB (BCC68000, BYTE);
3769 break;
3770 }
3771 /* only Bcc 68000 instructions can come here */
3772 /* change bcc into b!cc/jmp absl long */
3773 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3774 if (flag_short_refs)
3775 {
3776 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3777 /* JF: these were fr_opcode[2,3] */
3778 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3779 buffer_address[1] = (char) 0xf8;
3780 fragP->fr_fix += 2; /* account for jmp instruction */
3781 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3782 fragP->fr_offset, 0, NO_RELOC);
3783 fragP->fr_fix += 2;
3784 }
3785 else
3786 {
3787 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3788 /* JF: these were fr_opcode[2,3] */
3789 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3790 buffer_address[1] = (char) 0xf9;
3791 fragP->fr_fix += 2; /* account for jmp instruction */
3792 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3793 fragP->fr_offset, 0, NO_RELOC);
3794 fragP->fr_fix += 4;
3795 }
3796 frag_wane (fragP);
3797 break;
3798 } /* case TAB(BCC68000,SZ_UNDEF) */
3799
3800 case TAB (DBCC, SZ_UNDEF):
3801 {
3802 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3803 {
3804 fragP->fr_subtype = TAB (DBCC, SHORT);
3805 fragP->fr_var += 2;
3806 break;
3807 }
3808 /* only DBcc 68000 instructions can come here */
3809 /* change dbcc into dbcc/jmp absl long */
3810 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3811 buffer_address[0] = 0x00; /* branch offset = 4 */
3812 buffer_address[1] = 0x04;
3813 buffer_address[2] = 0x60; /* put in bra pc + ... */
3814
3815 if (flag_short_refs)
3816 {
3817 /* JF: these were fr_opcode[5-7] */
3818 buffer_address[3] = 0x04; /* plus 4 */
3819 buffer_address[4] = 0x4e; /* Put in Jump Word */
3820 buffer_address[5] = (char) 0xf8;
3821 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3822 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3823 fragP->fr_offset, 0, NO_RELOC);
3824 fragP->fr_fix += 2;
3825 }
3826 else
3827 {
3828 /* JF: these were fr_opcode[5-7] */
3829 buffer_address[3] = 0x06; /* Plus 6 */
3830 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3831 buffer_address[5] = (char) 0xf9;
3832 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3833 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3834 fragP->fr_offset, 0, NO_RELOC);
3835 fragP->fr_fix += 4;
3836 }
3837
3838 frag_wane (fragP);
3839 break;
3840 } /* case TAB(DBCC,SZ_UNDEF) */
3841
3842 case TAB (PCLEA, SZ_UNDEF):
3843 {
3844 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3845 || flag_short_refs
3846 || cpu_of_arch (current_architecture) < m68020)
3847 {
3848 fragP->fr_subtype = TAB (PCLEA, SHORT);
3849 fragP->fr_var += 2;
3850 }
3851 else
3852 {
3853 fragP->fr_subtype = TAB (PCLEA, LONG);
3854 fragP->fr_var += 6;
3855 }
3856 break;
3857 } /* TAB(PCLEA,SZ_UNDEF) */
3858
3859 case TAB (PCINDEX, SZ_UNDEF):
3860 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3861 || cpu_of_arch (current_architecture) < m68020)
3862 {
3863 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3864 }
3865 else
3866 {
3867 fragP->fr_subtype = TAB (PCINDEX, LONG);
3868 fragP->fr_var += 4;
3869 }
3870 break;
3871
3872 default:
3873 break;
3874 }
3875
3876 /* now that SZ_UNDEF are taken care of, check others */
3877 switch (fragP->fr_subtype)
3878 {
3879 case TAB (BCC68000, BYTE):
3880 case TAB (ABRANCH, BYTE):
3881 /* We can't do a short jump to the next instruction,
3882 so we force word mode. */
3883 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3884 fragP->fr_symbol->sy_frag == fragP->fr_next)
3885 {
3886 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3887 fragP->fr_var += 2;
3888 }
3889 break;
3890 default:
3891 break;
3892 }
3893 return fragP->fr_var + fragP->fr_fix - old_fix;
3894 }
3895
3896 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3897 /* the bit-field entries in the relocation_info struct plays hell
3898 with the byte-order problems of cross-assembly. So as a hack,
3899 I added this mach. dependent ri twiddler. Ugly, but it gets
3900 you there. -KWK */
3901 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3902 are symbolnum, most sig. byte first. Last byte is broken up with
3903 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3904 nibble as nuthin. (on Sun 3 at least) */
3905 /* Translate the internal relocation information into target-specific
3906 format. */
3907 #ifdef comment
3908 void
3909 md_ri_to_chars (the_bytes, ri)
3910 char *the_bytes;
3911 struct reloc_info_generic *ri;
3912 {
3913 /* this is easy */
3914 md_number_to_chars (the_bytes, ri->r_address, 4);
3915 /* now the fun stuff */
3916 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3917 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3918 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3919 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3920 ((ri->r_extern << 4) & 0x10));
3921 }
3922
3923 #endif /* comment */
3924
3925 #ifndef BFD_ASSEMBLER
3926 void
3927 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3928 char *where;
3929 fixS *fixP;
3930 relax_addressT segment_address_in_file;
3931 {
3932 /*
3933 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3934 * Out: GNU LD relocation length code: 0, 1, or 2.
3935 */
3936
3937 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3938 long r_symbolnum;
3939
3940 know (fixP->fx_addsy != NULL);
3941
3942 md_number_to_chars (where,
3943 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3944 4);
3945
3946 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3947 ? S_GET_TYPE (fixP->fx_addsy)
3948 : fixP->fx_addsy->sy_number);
3949
3950 where[4] = (r_symbolnum >> 16) & 0x0ff;
3951 where[5] = (r_symbolnum >> 8) & 0x0ff;
3952 where[6] = r_symbolnum & 0x0ff;
3953 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3954 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3955 }
3956 #endif
3957
3958 #endif /* OBJ_AOUT or OBJ_BOUT */
3959
3960 #ifndef WORKING_DOT_WORD
3961 CONST int md_short_jump_size = 4;
3962 CONST int md_long_jump_size = 6;
3963
3964 void
3965 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3966 char *ptr;
3967 addressT from_addr, to_addr;
3968 fragS *frag;
3969 symbolS *to_symbol;
3970 {
3971 valueT offset;
3972
3973 offset = to_addr - (from_addr + 2);
3974
3975 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3976 md_number_to_chars (ptr + 2, (valueT) offset, 2);
3977 }
3978
3979 void
3980 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3981 char *ptr;
3982 addressT from_addr, to_addr;
3983 fragS *frag;
3984 symbolS *to_symbol;
3985 {
3986 valueT offset;
3987
3988 if (cpu_of_arch (current_architecture) < m68020)
3989 {
3990 offset = to_addr - S_GET_VALUE (to_symbol);
3991 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3992 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3993 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3994 0, NO_RELOC);
3995 }
3996 else
3997 {
3998 offset = to_addr - (from_addr + 2);
3999 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4000 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4001 }
4002 }
4003
4004 #endif
4005
4006 /* Different values of OK tell what its OK to return. Things that
4007 aren't OK are an error (what a shock, no?)
4008
4009 0: Everything is OK
4010 10: Absolute 1:8 only
4011 20: Absolute 0:7 only
4012 30: absolute 0:15 only
4013 40: Absolute 0:31 only
4014 50: absolute 0:127 only
4015 55: absolute -64:63 only
4016 60: absolute -128:127 only
4017 70: absolute 0:4095 only
4018 80: No bignums
4019
4020 */
4021
4022 static int
4023 get_num (exp, ok)
4024 struct m68k_exp *exp;
4025 int ok;
4026 {
4027 if (exp->exp.X_op == O_absent)
4028 {
4029 /* Do the same thing the VAX asm does */
4030 op (exp) = O_constant;
4031 adds (exp) = 0;
4032 subs (exp) = 0;
4033 offs (exp) = 0;
4034 if (ok == 10)
4035 {
4036 as_warn ("expression out of range: defaulting to 1");
4037 offs (exp) = 1;
4038 }
4039 }
4040 else if (exp->exp.X_op == O_constant)
4041 {
4042 switch (ok)
4043 {
4044 case 10:
4045 if (offs (exp) < 1 || offs (exp) > 8)
4046 {
4047 as_warn ("expression out of range: defaulting to 1");
4048 offs (exp) = 1;
4049 }
4050 break;
4051 case 20:
4052 if (offs (exp) < 0 || offs (exp) > 7)
4053 goto outrange;
4054 break;
4055 case 30:
4056 if (offs (exp) < 0 || offs (exp) > 15)
4057 goto outrange;
4058 break;
4059 case 40:
4060 if (offs (exp) < 0 || offs (exp) > 32)
4061 goto outrange;
4062 break;
4063 case 50:
4064 if (offs (exp) < 0 || offs (exp) > 127)
4065 goto outrange;
4066 break;
4067 case 55:
4068 if (offs (exp) < -64 || offs (exp) > 63)
4069 goto outrange;
4070 break;
4071 case 60:
4072 if (offs (exp) < -128 || offs (exp) > 127)
4073 goto outrange;
4074 break;
4075 case 70:
4076 if (offs (exp) < 0 || offs (exp) > 4095)
4077 {
4078 outrange:
4079 as_warn ("expression out of range: defaulting to 0");
4080 offs (exp) = 0;
4081 }
4082 break;
4083 default:
4084 break;
4085 }
4086 }
4087 else if (exp->exp.X_op == O_big)
4088 {
4089 if (offs (exp) <= 0 /* flonum */
4090 && (ok == 80 /* no bignums */
4091 || (ok > 10 /* small-int ranges including 0 ok */
4092 /* If we have a flonum zero, a zero integer should
4093 do as well (e.g., in moveq). */
4094 && generic_floating_point_number.exponent == 0
4095 && generic_floating_point_number.low[0] == 0)))
4096 {
4097 /* HACK! Turn it into a long */
4098 LITTLENUM_TYPE words[6];
4099
4100 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4101 op (exp) = O_constant;
4102 adds (exp) = 0;
4103 subs (exp) = 0;
4104 offs (exp) = words[1] | (words[0] << 16);
4105 }
4106 else if (ok != 0)
4107 {
4108 op (exp) = O_constant;
4109 adds (exp) = 0;
4110 subs (exp) = 0;
4111 offs (exp) = (ok == 10) ? 1 : 0;
4112 as_warn ("Can't deal with expression; defaulting to %ld",
4113 offs (exp));
4114 }
4115 }
4116 else
4117 {
4118 if (ok >= 10 && ok <= 70)
4119 {
4120 op (exp) = O_constant;
4121 adds (exp) = 0;
4122 subs (exp) = 0;
4123 offs (exp) = (ok == 10) ? 1 : 0;
4124 as_warn ("Can't deal with expression; defaulting to %ld",
4125 offs (exp));
4126 }
4127 }
4128
4129 if (exp->size != SIZE_UNSPEC)
4130 {
4131 switch (exp->size)
4132 {
4133 case SIZE_UNSPEC:
4134 case SIZE_LONG:
4135 break;
4136 case SIZE_BYTE:
4137 if (!isbyte (offs (exp)))
4138 as_warn ("expression doesn't fit in BYTE");
4139 break;
4140 case SIZE_WORD:
4141 if (!isword (offs (exp)))
4142 as_warn ("expression doesn't fit in WORD");
4143 break;
4144 }
4145 }
4146
4147 return offs (exp);
4148 }
4149
4150 /* These are the back-ends for the various machine dependent pseudo-ops. */
4151 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4152
4153 static void
4154 s_data1 (ignore)
4155 int ignore;
4156 {
4157 subseg_set (data_section, 1);
4158 demand_empty_rest_of_line ();
4159 }
4160
4161 static void
4162 s_data2 (ignore)
4163 int ignore;
4164 {
4165 subseg_set (data_section, 2);
4166 demand_empty_rest_of_line ();
4167 }
4168
4169 static void
4170 s_bss (ignore)
4171 int ignore;
4172 {
4173 /* We don't support putting frags in the BSS segment, we fake it
4174 by marking in_bss, then looking at s_skip for clues. */
4175
4176 subseg_set (bss_section, 0);
4177 demand_empty_rest_of_line ();
4178 }
4179
4180 static void
4181 s_even (ignore)
4182 int ignore;
4183 {
4184 register int temp;
4185 register long temp_fill;
4186
4187 temp = 1; /* JF should be 2? */
4188 temp_fill = get_absolute_expression ();
4189 if (!need_pass_2) /* Never make frag if expect extra pass. */
4190 frag_align (temp, (int) temp_fill);
4191 demand_empty_rest_of_line ();
4192 }
4193
4194 static void
4195 s_proc (ignore)
4196 int ignore;
4197 {
4198 demand_empty_rest_of_line ();
4199 }
4200 \f
4201 /* Pseudo-ops handled for MRI compatibility. */
4202
4203 /* Handle an MRI style chip specification. */
4204
4205 static void
4206 mri_chip ()
4207 {
4208 char *s;
4209 char c;
4210 int i;
4211
4212 s = input_line_pointer;
4213 c = get_symbol_end ();
4214 for (i = 0; i < n_archs; i++)
4215 if (strcasecmp (s, archs[i].name) == 0)
4216 break;
4217 if (i >= n_archs)
4218 {
4219 as_bad ("%s: unrecognized processor name", s);
4220 *input_line_pointer = c;
4221 ignore_rest_of_line ();
4222 return;
4223 }
4224 *input_line_pointer = c;
4225
4226 if (*input_line_pointer == '/')
4227 current_architecture = 0;
4228 else
4229 current_architecture &= m68881 | m68851;
4230 current_architecture |= archs[i].arch;
4231
4232 while (*input_line_pointer == '/')
4233 {
4234 ++input_line_pointer;
4235 s = input_line_pointer;
4236 c = get_symbol_end ();
4237 if (strcmp (s, "68881") == 0)
4238 current_architecture |= m68881;
4239 else if (strcmp (s, "68851") == 0)
4240 current_architecture |= m68851;
4241 *input_line_pointer = c;
4242 }
4243 }
4244
4245 /* The MRI CHIP pseudo-op. */
4246
4247 static void
4248 s_chip (ignore)
4249 int ignore;
4250 {
4251 char *stop = NULL;
4252 char stopc;
4253
4254 if (flag_mri)
4255 stop = mri_comment_field (&stopc);
4256 mri_chip ();
4257 if (flag_mri)
4258 mri_comment_end (stop, stopc);
4259 demand_empty_rest_of_line ();
4260 }
4261
4262 /* The MRI FOPT pseudo-op. */
4263
4264 static void
4265 s_fopt (ignore)
4266 int ignore;
4267 {
4268 SKIP_WHITESPACE ();
4269
4270 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4271 {
4272 int temp;
4273
4274 input_line_pointer += 3;
4275 temp = get_absolute_expression ();
4276 if (temp < 0 || temp > 7)
4277 as_bad ("bad coprocessor id");
4278 else
4279 m68k_float_copnum = COP0 + temp;
4280 }
4281 else
4282 {
4283 as_bad ("unrecognized fopt option");
4284 ignore_rest_of_line ();
4285 return;
4286 }
4287
4288 demand_empty_rest_of_line ();
4289 }
4290
4291 /* The structure used to handle the MRI OPT pseudo-op. */
4292
4293 struct opt_action
4294 {
4295 /* The name of the option. */
4296 const char *name;
4297
4298 /* If this is not NULL, just call this function. The first argument
4299 is the ARG field of this structure, the second argument is
4300 whether the option was negated. */
4301 void (*pfn) PARAMS ((int arg, int on));
4302
4303 /* If this is not NULL, and the PFN field is NULL, set the variable
4304 this points to. Set it to the ARG field if the option was not
4305 negated, and the NOTARG field otherwise. */
4306 int *pvar;
4307
4308 /* The value to pass to PFN or to assign to *PVAR. */
4309 int arg;
4310
4311 /* The value to assign to *PVAR if the option is negated. If PFN is
4312 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4313 the option may not be negated. */
4314 int notarg;
4315 };
4316
4317 /* The table used to handle the MRI OPT pseudo-op. */
4318
4319 static void skip_to_comma PARAMS ((int, int));
4320 static void opt_nest PARAMS ((int, int));
4321 static void opt_chip PARAMS ((int, int));
4322 static void opt_list PARAMS ((int, int));
4323 static void opt_list_symbols PARAMS ((int, int));
4324
4325 static const struct opt_action opt_table[] =
4326 {
4327 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4328
4329 /* We do relaxing, so there is little use for these options. */
4330 { "b", 0, 0, 0, 0 },
4331 { "brs", 0, 0, 0, 0 },
4332 { "brb", 0, 0, 0, 0 },
4333 { "brl", 0, 0, 0, 0 },
4334 { "brw", 0, 0, 0, 0 },
4335
4336 { "c", 0, 0, 0, 0 },
4337 { "cex", 0, 0, 0, 0 },
4338 { "case", 0, &symbols_case_sensitive, 1, 0 },
4339 { "cl", 0, 0, 0, 0 },
4340 { "cre", 0, 0, 0, 0 },
4341 { "d", 0, &flag_keep_locals, 1, 0 },
4342 { "e", 0, 0, 0, 0 },
4343 { "f", 0, &flag_short_refs, 1, 0 },
4344 { "frs", 0, &flag_short_refs, 1, 0 },
4345 { "frl", 0, &flag_short_refs, 0, 1 },
4346 { "g", 0, 0, 0, 0 },
4347 { "i", 0, 0, 0, 0 },
4348 { "m", 0, 0, 0, 0 },
4349 { "mex", 0, 0, 0, 0 },
4350 { "mc", 0, 0, 0, 0 },
4351 { "md", 0, 0, 0, 0 },
4352 { "nest", opt_nest, 0, 0, 0 },
4353 { "next", skip_to_comma, 0, 0, 0 },
4354 { "o", 0, 0, 0, 0 },
4355 { "old", 0, 0, 0, 0 },
4356 { "op", skip_to_comma, 0, 0, 0 },
4357 { "pco", 0, 0, 0, 0 },
4358 { "p", opt_chip, 0, 0, 0 },
4359 { "pcr", 0, 0, 0, 0 },
4360 { "pcs", 0, 0, 0, 0 },
4361 { "r", 0, 0, 0, 0 },
4362 { "quick", 0, &m68k_quick, 1, 0 },
4363 { "rel32", 0, &m68k_rel32, 1, 0 },
4364 { "s", opt_list, 0, 0, 0 },
4365 { "t", opt_list_symbols, 0, 0, 0 },
4366 { "w", 0, &flag_no_warnings, 0, 1 },
4367 { "x", 0, 0, 0, 0 }
4368 };
4369
4370 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4371
4372 /* The MRI OPT pseudo-op. */
4373
4374 static void
4375 s_opt (ignore)
4376 int ignore;
4377 {
4378 do
4379 {
4380 int t;
4381 char *s;
4382 char c;
4383 int i;
4384 const struct opt_action *o;
4385
4386 SKIP_WHITESPACE ();
4387
4388 t = 1;
4389 if (*input_line_pointer == '-')
4390 {
4391 ++input_line_pointer;
4392 t = 0;
4393 }
4394 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4395 {
4396 input_line_pointer += 2;
4397 t = 0;
4398 }
4399
4400 s = input_line_pointer;
4401 c = get_symbol_end ();
4402
4403 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4404 {
4405 if (strcasecmp (s, o->name) == 0)
4406 {
4407 if (o->pfn)
4408 {
4409 /* Restore input_line_pointer now in case the option
4410 takes arguments. */
4411 *input_line_pointer = c;
4412 (*o->pfn) (o->arg, t);
4413 }
4414 else if (o->pvar != NULL)
4415 {
4416 if (! t && o->arg == o->notarg)
4417 as_bad ("option `%s' may not be negated", s);
4418 *input_line_pointer = c;
4419 *o->pvar = t ? o->arg : o->notarg;
4420 }
4421 else
4422 *input_line_pointer = c;
4423 break;
4424 }
4425 }
4426 if (i >= OPTCOUNT)
4427 {
4428 as_bad ("option `%s' not recognized", s);
4429 *input_line_pointer = c;
4430 }
4431 }
4432 while (*input_line_pointer++ == ',');
4433
4434 /* Move back to terminating character. */
4435 --input_line_pointer;
4436 demand_empty_rest_of_line ();
4437 }
4438
4439 /* Skip ahead to a comma. This is used for OPT options which we do
4440 not suppor tand which take arguments. */
4441
4442 static void
4443 skip_to_comma (arg, on)
4444 int arg;
4445 int on;
4446 {
4447 while (*input_line_pointer != ','
4448 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4449 ++input_line_pointer;
4450 }
4451
4452 /* Handle the OPT NEST=depth option. */
4453
4454 static void
4455 opt_nest (arg, on)
4456 int arg;
4457 int on;
4458 {
4459 if (*input_line_pointer != '=')
4460 {
4461 as_bad ("bad format of OPT NEST=depth");
4462 return;
4463 }
4464
4465 ++input_line_pointer;
4466 max_macro_nest = get_absolute_expression ();
4467 }
4468
4469 /* Handle the OPT P=chip option. */
4470
4471 static void
4472 opt_chip (arg, on)
4473 int arg;
4474 int on;
4475 {
4476 if (*input_line_pointer != '=')
4477 {
4478 /* This is just OPT P, which we do not support. */
4479 return;
4480 }
4481
4482 ++input_line_pointer;
4483 mri_chip ();
4484 }
4485
4486 /* Handle the OPT S option. */
4487
4488 static void
4489 opt_list (arg, on)
4490 int arg;
4491 int on;
4492 {
4493 listing_list (on);
4494 }
4495
4496 /* Handle the OPT T option. */
4497
4498 static void
4499 opt_list_symbols (arg, on)
4500 int arg;
4501 int on;
4502 {
4503 if (on)
4504 listing |= LISTING_SYMBOLS;
4505 else
4506 listing &=~ LISTING_SYMBOLS;
4507 }
4508
4509 /* Handle the MRI REG pseudo-op. */
4510
4511 static void
4512 s_reg (ignore)
4513 int ignore;
4514 {
4515 char *s;
4516 int c;
4517 struct m68k_op rop;
4518 unsigned long mask;
4519 char *stop = NULL;
4520 char stopc;
4521
4522 if (line_label == NULL)
4523 {
4524 as_bad ("missing label");
4525 ignore_rest_of_line ();
4526 return;
4527 }
4528
4529 if (flag_mri)
4530 stop = mri_comment_field (&stopc);
4531
4532 SKIP_WHITESPACE ();
4533
4534 s = input_line_pointer;
4535 while (isalnum ((unsigned char) *input_line_pointer)
4536 #ifdef REGISTER_PREFIX
4537 || *input_line_pointer == REGISTER_PREFIX
4538 #endif
4539 || *input_line_pointer == '/'
4540 || *input_line_pointer == '-')
4541 ++input_line_pointer;
4542 c = *input_line_pointer;
4543 *input_line_pointer = '\0';
4544
4545 if (m68k_ip_op (s, &rop) != 0)
4546 {
4547 if (rop.error == NULL)
4548 as_bad ("bad register list");
4549 else
4550 as_bad ("bad register list: %s", rop.error);
4551 *input_line_pointer = c;
4552 ignore_rest_of_line ();
4553 return;
4554 }
4555
4556 *input_line_pointer = c;
4557
4558 if (rop.mode == REGLST)
4559 mask = rop.mask;
4560 else if (rop.mode == DREG)
4561 mask = 1 << (rop.reg - DATA0);
4562 else if (rop.mode == AREG)
4563 mask = 1 << (rop.reg - ADDR0 + 8);
4564 else if (rop.mode == FPREG)
4565 mask = 1 << (rop.reg - FP0 + 16);
4566 else if (rop.mode == CONTROL
4567 && rop.reg == FPI)
4568 mask = 1 << 24;
4569 else if (rop.mode == CONTROL
4570 && rop.reg == FPS)
4571 mask = 1 << 25;
4572 else if (rop.mode == CONTROL
4573 && rop.reg == FPC)
4574 mask = 1 << 26;
4575 else
4576 {
4577 as_bad ("bad register list");
4578 ignore_rest_of_line ();
4579 return;
4580 }
4581
4582 S_SET_SEGMENT (line_label, absolute_section);
4583 S_SET_VALUE (line_label, mask);
4584 line_label->sy_frag = &zero_address_frag;
4585
4586 if (flag_mri)
4587 mri_comment_end (stop, stopc);
4588
4589 demand_empty_rest_of_line ();
4590 }
4591
4592 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4593
4594 struct save_opts
4595 {
4596 struct save_opts *next;
4597 int abspcadd;
4598 int symbols_case_sensitive;
4599 int keep_locals;
4600 int short_refs;
4601 int architecture;
4602 int quick;
4603 int rel32;
4604 int listing;
4605 int no_warnings;
4606 /* FIXME: We don't save OPT S. */
4607 };
4608
4609 /* This variable holds the stack of saved options. */
4610
4611 static struct save_opts *save_stack;
4612
4613 /* The MRI SAVE pseudo-op. */
4614
4615 static void
4616 s_save (ignore)
4617 int ignore;
4618 {
4619 struct save_opts *s;
4620
4621 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4622 s->abspcadd = m68k_abspcadd;
4623 s->symbols_case_sensitive = symbols_case_sensitive;
4624 s->keep_locals = flag_keep_locals;
4625 s->short_refs = flag_short_refs;
4626 s->architecture = current_architecture;
4627 s->quick = m68k_quick;
4628 s->rel32 = m68k_rel32;
4629 s->listing = listing;
4630 s->no_warnings = flag_no_warnings;
4631
4632 s->next = save_stack;
4633 save_stack = s;
4634
4635 demand_empty_rest_of_line ();
4636 }
4637
4638 /* The MRI RESTORE pseudo-op. */
4639
4640 static void
4641 s_restore (ignore)
4642 int ignore;
4643 {
4644 struct save_opts *s;
4645
4646 if (save_stack == NULL)
4647 {
4648 as_bad ("restore without save");
4649 ignore_rest_of_line ();
4650 return;
4651 }
4652
4653 s = save_stack;
4654 save_stack = s->next;
4655
4656 m68k_abspcadd = s->abspcadd;
4657 symbols_case_sensitive = s->symbols_case_sensitive;
4658 flag_keep_locals = s->keep_locals;
4659 flag_short_refs = s->short_refs;
4660 current_architecture = s->architecture;
4661 m68k_quick = s->quick;
4662 m68k_rel32 = s->rel32;
4663 listing = s->listing;
4664 flag_no_warnings = s->no_warnings;
4665
4666 free (s);
4667
4668 demand_empty_rest_of_line ();
4669 }
4670
4671 /* Types of MRI structured control directives. */
4672
4673 enum mri_control_type
4674 {
4675 mri_for,
4676 mri_if,
4677 mri_repeat,
4678 mri_while
4679 };
4680
4681 /* This structure is used to stack the MRI structured control
4682 directives. */
4683
4684 struct mri_control_info
4685 {
4686 /* The directive within which this one is enclosed. */
4687 struct mri_control_info *outer;
4688
4689 /* The type of directive. */
4690 enum mri_control_type type;
4691
4692 /* Whether an ELSE has been in an IF. */
4693 int else_seen;
4694
4695 /* The add or sub statement at the end of a FOR. */
4696 char *incr;
4697
4698 /* The label of the top of a FOR or REPEAT loop. */
4699 char *top;
4700
4701 /* The label to jump to for the next iteration, or the else
4702 expression of a conditional. */
4703 char *next;
4704
4705 /* The label to jump to to break out of the loop, or the label past
4706 the end of a conditional. */
4707 char *bottom;
4708 };
4709
4710 /* The stack of MRI structured control directives. */
4711
4712 static struct mri_control_info *mri_control_stack;
4713
4714 /* The current MRI structured control directive index number, used to
4715 generate label names. */
4716
4717 static int mri_control_index;
4718
4719 /* Some function prototypes. */
4720
4721 static char *mri_control_label PARAMS ((void));
4722 static struct mri_control_info *push_mri_control
4723 PARAMS ((enum mri_control_type));
4724 static void pop_mri_control PARAMS ((void));
4725 static int parse_mri_condition PARAMS ((int *));
4726 static int parse_mri_control_operand
4727 PARAMS ((int *, char **, char **, char **, char **));
4728 static int swap_mri_condition PARAMS ((int));
4729 static int reverse_mri_condition PARAMS ((int));
4730 static void build_mri_control_operand
4731 PARAMS ((int, int, char *, char *, char *, char *, const char *,
4732 const char *, int));
4733 static void parse_mri_control_expression
4734 PARAMS ((char *, int, const char *, const char *, int));
4735
4736 /* Generate a new MRI label structured control directive label name. */
4737
4738 static char *
4739 mri_control_label ()
4740 {
4741 char *n;
4742
4743 n = (char *) xmalloc (20);
4744 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
4745 ++mri_control_index;
4746 return n;
4747 }
4748
4749 /* Create a new MRI structured control directive. */
4750
4751 static struct mri_control_info *
4752 push_mri_control (type)
4753 enum mri_control_type type;
4754 {
4755 struct mri_control_info *n;
4756
4757 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
4758
4759 n->type = type;
4760 n->else_seen = 0;
4761 if (type == mri_if || type == mri_while)
4762 n->top = NULL;
4763 else
4764 n->top = mri_control_label ();
4765 n->next = mri_control_label ();
4766 n->bottom = mri_control_label ();
4767
4768 n->outer = mri_control_stack;
4769 mri_control_stack = n;
4770
4771 return n;
4772 }
4773
4774 /* Pop off the stack of MRI structured control directives. */
4775
4776 static void
4777 pop_mri_control ()
4778 {
4779 struct mri_control_info *n;
4780
4781 n = mri_control_stack;
4782 mri_control_stack = n->outer;
4783 if (n->top != NULL)
4784 free (n->top);
4785 free (n->next);
4786 free (n->bottom);
4787 free (n);
4788 }
4789
4790 /* Recognize a condition code in an MRI structured control expression. */
4791
4792 static int
4793 parse_mri_condition (pcc)
4794 int *pcc;
4795 {
4796 char c1, c2;
4797
4798 know (*input_line_pointer == '<');
4799
4800 ++input_line_pointer;
4801 c1 = *input_line_pointer++;
4802 c2 = *input_line_pointer++;
4803
4804 if (*input_line_pointer != '>')
4805 {
4806 as_bad ("syntax error in structured control directive");
4807 return 0;
4808 }
4809
4810 ++input_line_pointer;
4811 SKIP_WHITESPACE ();
4812
4813 if (isupper (c1))
4814 c1 = tolower (c1);
4815 if (isupper (c2))
4816 c2 = tolower (c2);
4817
4818 *pcc = (c1 << 8) | c2;
4819
4820 return 1;
4821 }
4822
4823 /* Parse a single operand in an MRI structured control expression. */
4824
4825 static int
4826 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
4827 int *pcc;
4828 char **leftstart;
4829 char **leftstop;
4830 char **rightstart;
4831 char **rightstop;
4832 {
4833 char *s;
4834
4835 SKIP_WHITESPACE ();
4836
4837 *pcc = -1;
4838 *leftstart = NULL;
4839 *leftstop = NULL;
4840 *rightstart = NULL;
4841 *rightstop = NULL;
4842
4843 if (*input_line_pointer == '<')
4844 {
4845 /* It's just a condition code. */
4846 return parse_mri_condition (pcc);
4847 }
4848
4849 /* Look ahead for the condition code. */
4850 for (s = input_line_pointer; *s != '\0'; ++s)
4851 {
4852 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
4853 break;
4854 }
4855 if (*s == '\0')
4856 {
4857 as_bad ("missing condition code in structured control directive");
4858 return 0;
4859 }
4860
4861 *leftstart = input_line_pointer;
4862 *leftstop = s;
4863 if (*leftstop > *leftstart
4864 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
4865 --*leftstop;
4866
4867 input_line_pointer = s;
4868 if (! parse_mri_condition (pcc))
4869 return 0;
4870
4871 /* Look ahead for AND or OR or end of line. */
4872 for (s = input_line_pointer; *s != '\0'; ++s)
4873 {
4874 if ((strncasecmp (s, "AND", 3) == 0
4875 && (s[3] == '.' || ! is_part_of_name (s[3])))
4876 || (strncasecmp (s, "OR", 2) == 0
4877 && (s[2] == '.' || ! is_part_of_name (s[2]))))
4878 break;
4879 }
4880
4881 *rightstart = input_line_pointer;
4882 *rightstop = s;
4883 if (*rightstop > *rightstart
4884 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
4885 --*rightstop;
4886
4887 input_line_pointer = s;
4888
4889 return 1;
4890 }
4891
4892 #define MCC(b1, b2) (((b1) << 8) | (b2))
4893
4894 /* Swap the sense of a condition. This changes the condition so that
4895 it generates the same result when the operands are swapped. */
4896
4897 static int
4898 swap_mri_condition (cc)
4899 int cc;
4900 {
4901 switch (cc)
4902 {
4903 case MCC ('h', 'i'): return MCC ('c', 's');
4904 case MCC ('l', 's'): return MCC ('c', 'c');
4905 case MCC ('c', 'c'): return MCC ('l', 's');
4906 case MCC ('c', 's'): return MCC ('h', 'i');
4907 case MCC ('p', 'l'): return MCC ('m', 'i');
4908 case MCC ('m', 'i'): return MCC ('p', 'l');
4909 case MCC ('g', 'e'): return MCC ('l', 'e');
4910 case MCC ('l', 't'): return MCC ('g', 't');
4911 case MCC ('g', 't'): return MCC ('l', 't');
4912 case MCC ('l', 'e'): return MCC ('g', 'e');
4913 }
4914 return cc;
4915 }
4916
4917 /* Reverse the sense of a condition. */
4918
4919 static int
4920 reverse_mri_condition (cc)
4921 int cc;
4922 {
4923 switch (cc)
4924 {
4925 case MCC ('h', 'i'): return MCC ('l', 's');
4926 case MCC ('l', 's'): return MCC ('h', 'i');
4927 case MCC ('c', 'c'): return MCC ('c', 's');
4928 case MCC ('c', 's'): return MCC ('c', 'c');
4929 case MCC ('n', 'e'): return MCC ('e', 'q');
4930 case MCC ('e', 'q'): return MCC ('n', 'e');
4931 case MCC ('v', 'c'): return MCC ('v', 's');
4932 case MCC ('v', 's'): return MCC ('v', 'c');
4933 case MCC ('p', 'l'): return MCC ('m', 'i');
4934 case MCC ('m', 'i'): return MCC ('p', 'l');
4935 case MCC ('g', 'e'): return MCC ('l', 't');
4936 case MCC ('l', 't'): return MCC ('g', 'e');
4937 case MCC ('g', 't'): return MCC ('l', 'e');
4938 case MCC ('l', 'e'): return MCC ('g', 't');
4939 }
4940 return cc;
4941 }
4942
4943 /* Build an MRI structured control expression. This generates test
4944 and branch instructions. It goes to TRUELAB if the condition is
4945 true, and to FALSELAB if the condition is false. Exactly one of
4946 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
4947 is the size qualifier for the expression. EXTENT is the size to
4948 use for the branch. */
4949
4950 static void
4951 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4952 rightstop, truelab, falselab, extent)
4953 int qual;
4954 int cc;
4955 char *leftstart;
4956 char *leftstop;
4957 char *rightstart;
4958 char *rightstop;
4959 const char *truelab;
4960 const char *falselab;
4961 int extent;
4962 {
4963 char *buf;
4964 char *s;
4965
4966 if (leftstart != NULL)
4967 {
4968 struct m68k_op leftop, rightop;
4969 char c;
4970
4971 /* Swap the compare operands, if necessary, to produce a legal
4972 m68k compare instruction. Comparing a register operand with
4973 a non-register operand requires the register to be on the
4974 right (cmp, cmpa). Comparing an immediate value with
4975 anything requires the immediate value to be on the left
4976 (cmpi). */
4977
4978 c = *leftstop;
4979 *leftstop = '\0';
4980 (void) m68k_ip_op (leftstart, &leftop);
4981 *leftstop = c;
4982
4983 c = *rightstop;
4984 *rightstop = '\0';
4985 (void) m68k_ip_op (rightstart, &rightop);
4986 *rightstop = c;
4987
4988 if (rightop.mode == IMMED
4989 || ((leftop.mode == DREG || leftop.mode == AREG)
4990 && (rightop.mode != DREG && rightop.mode != AREG)))
4991 {
4992 char *temp;
4993
4994 cc = swap_mri_condition (cc);
4995 temp = leftstart;
4996 leftstart = rightstart;
4997 rightstart = temp;
4998 temp = leftstop;
4999 leftstop = rightstop;
5000 rightstop = temp;
5001 }
5002 }
5003
5004 if (truelab == NULL)
5005 {
5006 cc = reverse_mri_condition (cc);
5007 truelab = falselab;
5008 }
5009
5010 if (leftstart != NULL)
5011 {
5012 buf = (char *) xmalloc (20
5013 + (leftstop - leftstart)
5014 + (rightstop - rightstart));
5015 s = buf;
5016 *s++ = 'c';
5017 *s++ = 'm';
5018 *s++ = 'p';
5019 if (qual != '\0')
5020 *s++ = qual;
5021 *s++ = ' ';
5022 memcpy (s, leftstart, leftstop - leftstart);
5023 s += leftstop - leftstart;
5024 *s++ = ',';
5025 memcpy (s, rightstart, rightstop - rightstart);
5026 s += rightstop - rightstart;
5027 *s = '\0';
5028 md_assemble (buf);
5029 free (buf);
5030 }
5031
5032 buf = (char *) xmalloc (20 + strlen (truelab));
5033 s = buf;
5034 *s++ = 'b';
5035 *s++ = cc >> 8;
5036 *s++ = cc & 0xff;
5037 if (extent != '\0')
5038 *s++ = extent;
5039 *s++ = ' ';
5040 strcpy (s, truelab);
5041 md_assemble (buf);
5042 free (buf);
5043 }
5044
5045 /* Parse an MRI structured control expression. This generates test
5046 and branch instructions. STOP is where the expression ends. It
5047 goes to TRUELAB if the condition is true, and to FALSELAB if the
5048 condition is false. Exactly one of TRUELAB and FALSELAB will be
5049 NULL, meaning to fall through. QUAL is the size qualifier for the
5050 expression. EXTENT is the size to use for the branch. */
5051
5052 static void
5053 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5054 char *stop;
5055 int qual;
5056 const char *truelab;
5057 const char *falselab;
5058 int extent;
5059 {
5060 int c;
5061 int cc;
5062 char *leftstart;
5063 char *leftstop;
5064 char *rightstart;
5065 char *rightstop;
5066
5067 c = *stop;
5068 *stop = '\0';
5069
5070 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5071 &rightstart, &rightstop))
5072 {
5073 *stop = c;
5074 return;
5075 }
5076
5077 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5078 {
5079 const char *flab;
5080
5081 if (falselab != NULL)
5082 flab = falselab;
5083 else
5084 flab = mri_control_label ();
5085
5086 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5087 rightstop, (const char *) NULL, flab, extent);
5088
5089 input_line_pointer += 3;
5090 if (*input_line_pointer != '.'
5091 || input_line_pointer[1] == '\0')
5092 qual = '\0';
5093 else
5094 {
5095 qual = input_line_pointer[1];
5096 input_line_pointer += 2;
5097 }
5098
5099 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5100 &rightstart, &rightstop))
5101 {
5102 *stop = c;
5103 return;
5104 }
5105
5106 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5107 rightstop, truelab, falselab, extent);
5108
5109 if (falselab == NULL)
5110 colon (flab);
5111 }
5112 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5113 {
5114 const char *tlab;
5115
5116 if (truelab != NULL)
5117 tlab = truelab;
5118 else
5119 tlab = mri_control_label ();
5120
5121 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5122 rightstop, tlab, (const char *) NULL, extent);
5123
5124 input_line_pointer += 2;
5125 if (*input_line_pointer != '.'
5126 || input_line_pointer[1] == '\0')
5127 qual = '\0';
5128 else
5129 {
5130 qual = input_line_pointer[1];
5131 input_line_pointer += 2;
5132 }
5133
5134 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5135 &rightstart, &rightstop))
5136 {
5137 *stop = c;
5138 return;
5139 }
5140
5141 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5142 rightstop, truelab, falselab, extent);
5143
5144 if (truelab == NULL)
5145 colon (tlab);
5146 }
5147 else
5148 {
5149 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5150 rightstop, truelab, falselab, extent);
5151 }
5152
5153 *stop = c;
5154 if (input_line_pointer != stop)
5155 as_bad ("syntax error in structured control directive");
5156 }
5157
5158 /* Handle the MRI IF pseudo-op. This may be a structured control
5159 directive, or it may be a regular assembler conditional, depending
5160 on its operands. */
5161
5162 static void
5163 s_mri_if (qual)
5164 int qual;
5165 {
5166 char *s;
5167 int c;
5168 struct mri_control_info *n;
5169
5170 /* A structured control directive must end with THEN with an
5171 optional qualifier. */
5172 s = input_line_pointer;
5173 while (! is_end_of_line[(unsigned char) *s]
5174 && (! flag_mri || *s != '*'))
5175 ++s;
5176 --s;
5177 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5178 --s;
5179
5180 if (s - input_line_pointer > 1
5181 && s[-1] == '.')
5182 s -= 2;
5183
5184 if (s - input_line_pointer < 3
5185 || strncasecmp (s - 3, "THEN", 4) != 0)
5186 {
5187 if (qual != '\0')
5188 {
5189 as_bad ("missing then");
5190 ignore_rest_of_line ();
5191 return;
5192 }
5193
5194 /* It's a conditional. */
5195 s_if (O_ne);
5196 return;
5197 }
5198
5199 /* Since this might be a conditional if, this pseudo-op will be
5200 called even if we are supported to be ignoring input. Double
5201 check now. Clobber *input_line_pointer so that ignore_input
5202 thinks that this is not a special pseudo-op. */
5203 c = *input_line_pointer;
5204 *input_line_pointer = 0;
5205 if (ignore_input ())
5206 {
5207 *input_line_pointer = c;
5208 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5209 ++input_line_pointer;
5210 demand_empty_rest_of_line ();
5211 return;
5212 }
5213 *input_line_pointer = c;
5214
5215 n = push_mri_control (mri_if);
5216
5217 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5218 n->next, s[1] == '.' ? s[2] : '\0');
5219
5220 if (s[1] == '.')
5221 input_line_pointer = s + 3;
5222 else
5223 input_line_pointer = s + 1;
5224
5225 if (flag_mri)
5226 {
5227 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5228 ++input_line_pointer;
5229 }
5230
5231 demand_empty_rest_of_line ();
5232 }
5233
5234 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5235 structured IF, associate the ELSE with the IF. Otherwise, assume
5236 it is a conditional else. */
5237
5238 static void
5239 s_mri_else (qual)
5240 int qual;
5241 {
5242 int c;
5243 char *buf;
5244 char q[2];
5245
5246 if (qual == '\0'
5247 && (mri_control_stack == NULL
5248 || mri_control_stack->type != mri_if
5249 || mri_control_stack->else_seen))
5250 {
5251 s_else (0);
5252 return;
5253 }
5254
5255 c = *input_line_pointer;
5256 *input_line_pointer = 0;
5257 if (ignore_input ())
5258 {
5259 *input_line_pointer = c;
5260 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5261 ++input_line_pointer;
5262 demand_empty_rest_of_line ();
5263 return;
5264 }
5265 *input_line_pointer = c;
5266
5267 if (mri_control_stack == NULL
5268 || mri_control_stack->type != mri_if
5269 || mri_control_stack->else_seen)
5270 {
5271 as_bad ("else without matching if");
5272 ignore_rest_of_line ();
5273 return;
5274 }
5275
5276 mri_control_stack->else_seen = 1;
5277
5278 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5279 q[0] = qual;
5280 q[1] = '\0';
5281 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5282 md_assemble (buf);
5283 free (buf);
5284
5285 colon (mri_control_stack->next);
5286
5287 if (flag_mri)
5288 {
5289 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5290 ++input_line_pointer;
5291 }
5292
5293 demand_empty_rest_of_line ();
5294 }
5295
5296 /* Handle the MRI ENDI pseudo-op. */
5297
5298 static void
5299 s_mri_endi (ignore)
5300 int ignore;
5301 {
5302 if (mri_control_stack == NULL
5303 || mri_control_stack->type != mri_if)
5304 {
5305 as_bad ("endi without matching if");
5306 ignore_rest_of_line ();
5307 return;
5308 }
5309
5310 /* ignore_input will not return true for ENDI, so we don't need to
5311 worry about checking it again here. */
5312
5313 if (! mri_control_stack->else_seen)
5314 colon (mri_control_stack->next);
5315 colon (mri_control_stack->bottom);
5316
5317 pop_mri_control ();
5318
5319 if (flag_mri)
5320 {
5321 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5322 ++input_line_pointer;
5323 }
5324
5325 demand_empty_rest_of_line ();
5326 }
5327
5328 /* Handle the MRI BREAK pseudo-op. */
5329
5330 static void
5331 s_mri_break (extent)
5332 int extent;
5333 {
5334 struct mri_control_info *n;
5335 char *buf;
5336 char ex[2];
5337
5338 n = mri_control_stack;
5339 while (n != NULL
5340 && n->type != mri_for
5341 && n->type != mri_repeat
5342 && n->type != mri_while)
5343 n = n->outer;
5344 if (n == NULL)
5345 {
5346 as_bad ("break outside of structured loop");
5347 ignore_rest_of_line ();
5348 return;
5349 }
5350
5351 buf = (char *) xmalloc (20 + strlen (n->bottom));
5352 ex[0] = extent;
5353 ex[1] = '\0';
5354 sprintf (buf, "bra%s %s", ex, n->bottom);
5355 md_assemble (buf);
5356 free (buf);
5357
5358 if (flag_mri)
5359 {
5360 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5361 ++input_line_pointer;
5362 }
5363
5364 demand_empty_rest_of_line ();
5365 }
5366
5367 /* Handle the MRI NEXT pseudo-op. */
5368
5369 static void
5370 s_mri_next (extent)
5371 int extent;
5372 {
5373 struct mri_control_info *n;
5374 char *buf;
5375 char ex[2];
5376
5377 n = mri_control_stack;
5378 while (n != NULL
5379 && n->type != mri_for
5380 && n->type != mri_repeat
5381 && n->type != mri_while)
5382 n = n->outer;
5383 if (n == NULL)
5384 {
5385 as_bad ("next outside of structured loop");
5386 ignore_rest_of_line ();
5387 return;
5388 }
5389
5390 buf = (char *) xmalloc (20 + strlen (n->next));
5391 ex[0] = extent;
5392 ex[1] = '\0';
5393 sprintf (buf, "bra%s %s", ex, n->next);
5394 md_assemble (buf);
5395 free (buf);
5396
5397 if (flag_mri)
5398 {
5399 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5400 ++input_line_pointer;
5401 }
5402
5403 demand_empty_rest_of_line ();
5404 }
5405
5406 /* Handle the MRI FOR pseudo-op. */
5407
5408 static void
5409 s_mri_for (qual)
5410 int qual;
5411 {
5412 const char *varstart, *varstop;
5413 const char *initstart, *initstop;
5414 const char *endstart, *endstop;
5415 const char *bystart, *bystop;
5416 int up;
5417 int by;
5418 int extent;
5419 struct mri_control_info *n;
5420 char *buf;
5421 char *s;
5422 char ex[2];
5423
5424 /* The syntax is
5425 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5426 */
5427
5428 SKIP_WHITESPACE ();
5429 varstart = input_line_pointer;
5430
5431 /* Look for the '='. */
5432 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5433 && *input_line_pointer != '=')
5434 ++input_line_pointer;
5435 if (*input_line_pointer != '=')
5436 {
5437 as_bad ("missing =");
5438 ignore_rest_of_line ();
5439 return;
5440 }
5441
5442 varstop = input_line_pointer;
5443 if (varstop > varstart
5444 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5445 --varstop;
5446
5447 ++input_line_pointer;
5448
5449 initstart = input_line_pointer;
5450
5451 /* Look for TO or DOWNTO. */
5452 up = 1;
5453 initstop = NULL;
5454 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5455 {
5456 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5457 && ! is_part_of_name (input_line_pointer[2]))
5458 {
5459 initstop = input_line_pointer;
5460 input_line_pointer += 2;
5461 break;
5462 }
5463 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5464 && ! is_part_of_name (input_line_pointer[6]))
5465 {
5466 initstop = input_line_pointer;
5467 up = 0;
5468 input_line_pointer += 6;
5469 break;
5470 }
5471 ++input_line_pointer;
5472 }
5473 if (initstop == NULL)
5474 {
5475 as_bad ("missing to or downto");
5476 ignore_rest_of_line ();
5477 return;
5478 }
5479 if (initstop > initstart
5480 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5481 --initstop;
5482
5483 SKIP_WHITESPACE ();
5484 endstart = input_line_pointer;
5485
5486 /* Look for BY or DO. */
5487 by = 0;
5488 endstop = NULL;
5489 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5490 {
5491 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5492 && ! is_part_of_name (input_line_pointer[2]))
5493 {
5494 endstop = input_line_pointer;
5495 by = 1;
5496 input_line_pointer += 2;
5497 break;
5498 }
5499 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5500 && (input_line_pointer[2] == '.'
5501 || ! is_part_of_name (input_line_pointer[2])))
5502 {
5503 endstop = input_line_pointer;
5504 input_line_pointer += 2;
5505 break;
5506 }
5507 ++input_line_pointer;
5508 }
5509 if (endstop == NULL)
5510 {
5511 as_bad ("missing do");
5512 ignore_rest_of_line ();
5513 return;
5514 }
5515 if (endstop > endstart
5516 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5517 --endstop;
5518
5519 if (! by)
5520 {
5521 bystart = "#1";
5522 bystop = bystart + 2;
5523 }
5524 else
5525 {
5526 SKIP_WHITESPACE ();
5527 bystart = input_line_pointer;
5528
5529 /* Look for DO. */
5530 bystop = NULL;
5531 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5532 {
5533 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5534 && (input_line_pointer[2] == '.'
5535 || ! is_part_of_name (input_line_pointer[2])))
5536 {
5537 bystop = input_line_pointer;
5538 input_line_pointer += 2;
5539 break;
5540 }
5541 ++input_line_pointer;
5542 }
5543 if (bystop == NULL)
5544 {
5545 as_bad ("missing do");
5546 ignore_rest_of_line ();
5547 return;
5548 }
5549 if (bystop > bystart
5550 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5551 --bystop;
5552 }
5553
5554 if (*input_line_pointer != '.')
5555 extent = '\0';
5556 else
5557 {
5558 extent = input_line_pointer[1];
5559 input_line_pointer += 2;
5560 }
5561
5562 /* We have fully parsed the FOR operands. Now build the loop. */
5563
5564 n = push_mri_control (mri_for);
5565
5566 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5567
5568 /* move init,var */
5569 s = buf;
5570 *s++ = 'm';
5571 *s++ = 'o';
5572 *s++ = 'v';
5573 *s++ = 'e';
5574 if (qual != '\0')
5575 *s++ = qual;
5576 *s++ = ' ';
5577 memcpy (s, initstart, initstop - initstart);
5578 s += initstop - initstart;
5579 *s++ = ',';
5580 memcpy (s, varstart, varstop - varstart);
5581 s += varstop - varstart;
5582 *s = '\0';
5583 md_assemble (buf);
5584
5585 colon (n->top);
5586
5587 /* cmp end,var */
5588 s = buf;
5589 *s++ = 'c';
5590 *s++ = 'm';
5591 *s++ = 'p';
5592 if (qual != '\0')
5593 *s++ = qual;
5594 *s++ = ' ';
5595 memcpy (s, endstart, endstop - endstart);
5596 s += endstop - endstart;
5597 *s++ = ',';
5598 memcpy (s, varstart, varstop - varstart);
5599 s += varstop - varstart;
5600 *s = '\0';
5601 md_assemble (buf);
5602
5603 /* bcc bottom */
5604 ex[0] = extent;
5605 ex[1] = '\0';
5606 if (up)
5607 sprintf (buf, "blt%s %s", ex, n->bottom);
5608 else
5609 sprintf (buf, "bgt%s %s", ex, n->bottom);
5610 md_assemble (buf);
5611
5612 /* Put together the add or sub instruction used by ENDF. */
5613 s = buf;
5614 if (up)
5615 strcpy (s, "add");
5616 else
5617 strcpy (s, "sub");
5618 s += 3;
5619 if (qual != '\0')
5620 *s++ = qual;
5621 *s++ = ' ';
5622 memcpy (s, bystart, bystop - bystart);
5623 s += bystop - bystart;
5624 *s++ = ',';
5625 memcpy (s, varstart, varstop - varstart);
5626 s += varstop - varstart;
5627 *s = '\0';
5628 n->incr = buf;
5629
5630 if (flag_mri)
5631 {
5632 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5633 ++input_line_pointer;
5634 }
5635
5636 demand_empty_rest_of_line ();
5637 }
5638
5639 /* Handle the MRI ENDF pseudo-op. */
5640
5641 static void
5642 s_mri_endf (ignore)
5643 int ignore;
5644 {
5645 if (mri_control_stack == NULL
5646 || mri_control_stack->type != mri_for)
5647 {
5648 as_bad ("endf without for");
5649 ignore_rest_of_line ();
5650 return;
5651 }
5652
5653 colon (mri_control_stack->next);
5654
5655 md_assemble (mri_control_stack->incr);
5656
5657 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5658 md_assemble (mri_control_stack->incr);
5659
5660 free (mri_control_stack->incr);
5661
5662 colon (mri_control_stack->bottom);
5663
5664 pop_mri_control ();
5665
5666 if (flag_mri)
5667 {
5668 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5669 ++input_line_pointer;
5670 }
5671
5672 demand_empty_rest_of_line ();
5673 }
5674
5675 /* Handle the MRI REPEAT pseudo-op. */
5676
5677 static void
5678 s_mri_repeat (ignore)
5679 int ignore;
5680 {
5681 struct mri_control_info *n;
5682
5683 n = push_mri_control (mri_repeat);
5684 colon (n->top);
5685 if (flag_mri)
5686 {
5687 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5688 ++input_line_pointer;
5689 }
5690 demand_empty_rest_of_line ();
5691 }
5692
5693 /* Handle the MRI UNTIL pseudo-op. */
5694
5695 static void
5696 s_mri_until (qual)
5697 int qual;
5698 {
5699 char *s;
5700
5701 if (mri_control_stack == NULL
5702 || mri_control_stack->type != mri_repeat)
5703 {
5704 as_bad ("until without repeat");
5705 ignore_rest_of_line ();
5706 return;
5707 }
5708
5709 colon (mri_control_stack->next);
5710
5711 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
5712 ;
5713
5714 parse_mri_control_expression (s, qual, (const char *) NULL,
5715 mri_control_stack->top, '\0');
5716
5717 colon (mri_control_stack->bottom);
5718
5719 input_line_pointer = s;
5720
5721 if (flag_mri)
5722 {
5723 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5724 ++input_line_pointer;
5725 }
5726
5727 demand_empty_rest_of_line ();
5728 }
5729
5730 /* Handle the MRI WHILE pseudo-op. */
5731
5732 static void
5733 s_mri_while (qual)
5734 int qual;
5735 {
5736 char *s;
5737
5738 struct mri_control_info *n;
5739
5740 s = input_line_pointer;
5741 while (! is_end_of_line[(unsigned char) *s]
5742 && (! flag_mri || *s != '*'))
5743 s++;
5744 --s;
5745 while (*s == ' ' || *s == '\t')
5746 --s;
5747 if (s - input_line_pointer > 1
5748 && s[-1] == '.')
5749 s -= 2;
5750 if (s - input_line_pointer < 2
5751 || strncasecmp (s - 1, "DO", 2) != 0)
5752 {
5753 as_bad ("missing do");
5754 ignore_rest_of_line ();
5755 return;
5756 }
5757
5758 n = push_mri_control (mri_while);
5759
5760 colon (n->next);
5761
5762 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
5763 s[1] == '.' ? s[2] : '\0');
5764
5765 input_line_pointer = s + 1;
5766 if (*input_line_pointer == '.')
5767 input_line_pointer += 2;
5768
5769 if (flag_mri)
5770 {
5771 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5772 ++input_line_pointer;
5773 }
5774
5775 demand_empty_rest_of_line ();
5776 }
5777
5778 /* Handle the MRI ENDW pseudo-op. */
5779
5780 static void
5781 s_mri_endw (ignore)
5782 int ignore;
5783 {
5784 char *buf;
5785
5786 if (mri_control_stack == NULL
5787 || mri_control_stack->type != mri_while)
5788 {
5789 as_bad ("endw without while");
5790 ignore_rest_of_line ();
5791 return;
5792 }
5793
5794 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
5795 sprintf (buf, "bra %s", mri_control_stack->next);
5796 md_assemble (buf);
5797 free (buf);
5798
5799 colon (mri_control_stack->bottom);
5800
5801 pop_mri_control ();
5802
5803 if (flag_mri)
5804 {
5805 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5806 ++input_line_pointer;
5807 }
5808
5809 demand_empty_rest_of_line ();
5810 }
5811 \f
5812 /*
5813 * md_parse_option
5814 * Invocation line includes a switch not recognized by the base assembler.
5815 * See if it's a processor-specific option. These are:
5816 *
5817 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5818 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5819 * Select the architecture. Instructions or features not
5820 * supported by the selected architecture cause fatal
5821 * errors. More than one may be specified. The default is
5822 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5823 * for -m68000, and -m68882 is a synonym for -m68881.
5824 * -[A]m[c]no-68851, -[A]m[c]no-68881
5825 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5826 * so don't use or document it, but that's the way the parsing
5827 * works).
5828 *
5829 * -pic Indicates PIC.
5830 * -k Indicates PIC. (Sun 3 only.)
5831 *
5832 */
5833
5834 #ifdef OBJ_ELF
5835 CONST char *md_shortopts = "lSA:m:kQ:V";
5836 #else
5837 CONST char *md_shortopts = "lSA:m:k";
5838 #endif
5839
5840 struct option md_longopts[] = {
5841 #define OPTION_PIC (OPTION_MD_BASE)
5842 {"pic", no_argument, NULL, OPTION_PIC},
5843 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5844 {"register-prefix-optional", no_argument, NULL,
5845 OPTION_REGISTER_PREFIX_OPTIONAL},
5846 {NULL, no_argument, NULL, 0}
5847 };
5848 size_t md_longopts_size = sizeof(md_longopts);
5849
5850 int
5851 md_parse_option (c, arg)
5852 int c;
5853 char *arg;
5854 {
5855 switch (c)
5856 {
5857 case 'l': /* -l means keep external to 2 bit offset
5858 rather than 16 bit one */
5859 flag_short_refs = 1;
5860 break;
5861
5862 case 'S': /* -S means that jbsr's always turn into
5863 jsr's. */
5864 flag_long_jumps = 1;
5865 break;
5866
5867 case 'A':
5868 if (*arg == 'm')
5869 arg++;
5870 /* intentional fall-through */
5871 case 'm':
5872
5873 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
5874 {
5875 int i;
5876 unsigned long arch;
5877 const char *oarg = arg;
5878
5879 arg += 3;
5880 if (*arg == 'm')
5881 {
5882 arg++;
5883 if (arg[0] == 'c' && arg[1] == '6')
5884 arg++;
5885 }
5886 for (i = 0; i < n_archs; i++)
5887 if (!strcmp (arg, archs[i].name))
5888 break;
5889 if (i == n_archs)
5890 {
5891 unknown:
5892 as_bad ("unrecognized option `%s'", oarg);
5893 return 0;
5894 }
5895 arch = archs[i].arch;
5896 if (arch == m68881)
5897 no_68881 = 1;
5898 else if (arch == m68851)
5899 no_68851 = 1;
5900 else
5901 goto unknown;
5902 }
5903 else
5904 {
5905 int i;
5906
5907 if (arg[0] == 'c' && arg[1] == '6')
5908 arg++;
5909
5910 for (i = 0; i < n_archs; i++)
5911 if (!strcmp (arg, archs[i].name))
5912 {
5913 unsigned long arch = archs[i].arch;
5914 if (cpu_of_arch (arch))
5915 /* It's a cpu spec. */
5916 {
5917 current_architecture &= ~m68000up;
5918 current_architecture |= arch;
5919 }
5920 else if (arch == m68881)
5921 {
5922 current_architecture |= m68881;
5923 no_68881 = 0;
5924 }
5925 else if (arch == m68851)
5926 {
5927 current_architecture |= m68851;
5928 no_68851 = 0;
5929 }
5930 else
5931 /* ??? */
5932 abort ();
5933 break;
5934 }
5935 if (i == n_archs)
5936 {
5937 as_bad ("unrecognized architecture specification `%s'", arg);
5938 return 0;
5939 }
5940 }
5941 break;
5942
5943 case OPTION_PIC:
5944 case 'k':
5945 flag_want_pic = 1;
5946 break; /* -pic, Position Independent Code */
5947
5948 case OPTION_REGISTER_PREFIX_OPTIONAL:
5949 flag_reg_prefix_optional = 1;
5950 break;
5951
5952 case 'Q':
5953 case 'V':
5954 break;
5955
5956 default:
5957 return 0;
5958 }
5959
5960 return 1;
5961 }
5962
5963 void
5964 md_show_usage (stream)
5965 FILE *stream;
5966 {
5967 fprintf(stream, "\
5968 680X0 options:\n\
5969 -l use 1 word for refs to undefined symbols [default 2]\n\
5970 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5971 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5972 | -mcpu32\n\
5973 specify variant of 680X0 architecture [default 68020]\n\
5974 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5975 target has/lacks floating-point coprocessor\n\
5976 [default yes for 68020, 68030, and cpu32]\n");
5977 fprintf(stream, "\
5978 -m68851 | -mno-68851\n\
5979 target has/lacks memory-management unit coprocessor\n\
5980 [default yes for 68020 and up]\n\
5981 -pic, -k generate position independent code\n\
5982 -S turn jbsr into jsr\n\
5983 --register-prefix-optional\n\
5984 recognize register names without prefix character\n");
5985 }
5986 \f
5987 #ifdef TEST2
5988
5989 /* TEST2: Test md_assemble() */
5990 /* Warning, this routine probably doesn't work anymore */
5991
5992 main ()
5993 {
5994 struct m68k_it the_ins;
5995 char buf[120];
5996 char *cp;
5997 int n;
5998
5999 m68k_ip_begin ();
6000 for (;;)
6001 {
6002 if (!gets (buf) || !*buf)
6003 break;
6004 if (buf[0] == '|' || buf[1] == '.')
6005 continue;
6006 for (cp = buf; *cp; cp++)
6007 if (*cp == '\t')
6008 *cp = ' ';
6009 if (is_label (buf))
6010 continue;
6011 memset (&the_ins, '\0', sizeof (the_ins));
6012 m68k_ip (&the_ins, buf);
6013 if (the_ins.error)
6014 {
6015 printf ("Error %s in %s\n", the_ins.error, buf);
6016 }
6017 else
6018 {
6019 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6020 for (n = 0; n < the_ins.numo; n++)
6021 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6022 printf (" ");
6023 print_the_insn (&the_ins.opcode[0], stdout);
6024 (void) putchar ('\n');
6025 }
6026 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6027 {
6028 if (the_ins.operands[n].error)
6029 {
6030 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6031 continue;
6032 }
6033 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6034 if (the_ins.operands[n].b_const)
6035 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6036 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6037 if (the_ins.operands[n].b_iadd)
6038 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6039 (void) putchar ('\n');
6040 }
6041 }
6042 m68k_ip_end ();
6043 return 0;
6044 }
6045
6046 is_label (str)
6047 char *str;
6048 {
6049 while (*str == ' ')
6050 str++;
6051 while (*str && *str != ' ')
6052 str++;
6053 if (str[-1] == ':' || str[1] == '=')
6054 return 1;
6055 return 0;
6056 }
6057
6058 #endif
6059
6060 /* Possible states for relaxation:
6061
6062 0 0 branch offset byte (bra, etc)
6063 0 1 word
6064 0 2 long
6065
6066 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6067 1 1 word
6068 1 2 long
6069
6070 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6071 2 1 word-long
6072 2 2 long-word
6073 2 3 long-long
6074
6075 */
6076
6077 /* We have no need to default values of symbols. */
6078
6079 /* ARGSUSED */
6080 symbolS *
6081 md_undefined_symbol (name)
6082 char *name;
6083 {
6084 return 0;
6085 }
6086
6087 /* Round up a section size to the appropriate boundary. */
6088 valueT
6089 md_section_align (segment, size)
6090 segT segment;
6091 valueT size;
6092 {
6093 return size; /* Byte alignment is fine */
6094 }
6095
6096 /* Exactly what point is a PC-relative offset relative TO?
6097 On the 68k, it is relative to the address of the first extension
6098 word. The difference between the addresses of the offset and the
6099 first extension word is stored in fx_pcrel_adjust. */
6100 long
6101 md_pcrel_from (fixP)
6102 fixS *fixP;
6103 {
6104 int adjust;
6105
6106 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6107 -1 as 64. */
6108 adjust = fixP->fx_pcrel_adjust;
6109 if (adjust == 64)
6110 adjust = -1;
6111 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6112 }
6113
6114 #ifndef BFD_ASSEMBLER
6115 /*ARGSUSED*/
6116 void
6117 tc_coff_symbol_emit_hook (ignore)
6118 symbolS *ignore;
6119 {
6120 }
6121
6122 int
6123 tc_coff_sizemachdep (frag)
6124 fragS *frag;
6125 {
6126 switch (frag->fr_subtype & 0x3)
6127 {
6128 case BYTE:
6129 return 1;
6130 case SHORT:
6131 return 2;
6132 case LONG:
6133 return 4;
6134 default:
6135 abort ();
6136 return 0;
6137 }
6138 }
6139 #endif
6140
6141 /* end of tc-m68k.c */