1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987-2021 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 #include "safe-ctype.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
32 static void m68k_elf_cons (int);
33 static void m68k_elf_gnu_attribute (int);
35 /* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39 #if defined (TE_SVR4) || defined (TE_DELTA)
40 const char *m68k_comment_chars
= "|#";
42 const char *m68k_comment_chars
= "|";
45 /* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48 /* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
50 #NO_APP at the beginning of its output. */
51 /* Also note that comments like this one will always work. */
52 const char line_comment_chars
[] = "#*";
54 const char line_separator_chars
[] = ";";
56 /* Chars that can be used to separate mant from exp in floating point nums. */
57 const char EXP_CHARS
[] = "eE";
59 /* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
62 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
68 /* Are we trying to generate PIC code? If so, absolute references
69 ought to be made into linkage table references or pc-relative
70 references. Not implemented. For ELF there are other means
71 to denote pic relocations. */
74 static int flag_short_refs
; /* -l option. */
75 static int flag_long_jumps
; /* -S option. */
76 static int flag_keep_pcrel
; /* --pcrel option. */
78 #ifdef REGISTER_PREFIX_OPTIONAL
79 int flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
81 int flag_reg_prefix_optional
;
84 /* Whether --register-prefix-optional was used on the command line. */
85 static int reg_prefix_optional_seen
;
87 /* The floating point coprocessor to use by default. */
88 static enum m68k_register m68k_float_copnum
= COP1
;
90 /* If this is non-zero, then references to number(%pc) will be taken
91 to refer to number, rather than to %pc + number. */
92 static int m68k_abspcadd
;
94 /* If this is non-zero, then the quick forms of the move, add, and sub
95 instructions are used when possible. */
96 static int m68k_quick
= 1;
98 /* If this is non-zero, then if the size is not specified for a base
99 or outer displacement, the assembler assumes that the size should
101 static int m68k_rel32
= 1;
103 /* This is non-zero if m68k_rel32 was set from the command line. */
104 static int m68k_rel32_from_cmdline
;
106 /* The default width to use for an index register when using a base
108 static enum m68k_size m68k_index_width_default
= SIZE_LONG
;
110 /* We want to warn if any text labels are misaligned. In order to get
111 the right line number, we need to record the line number for each
115 struct label_line
*next
;
122 /* The list of labels. */
124 static struct label_line
*labels
;
126 /* The current label. */
128 static struct label_line
*current_label
;
130 /* Pointer to list holding the opcodes sorted by name. */
131 static struct m68k_opcode
const ** m68k_sorted_opcodes
;
133 /* It's an arbitrary name: This means I don't approve of it.
135 static struct obstack robyn
;
139 const char *m_operands
;
140 unsigned long m_opcode
;
144 struct m68k_incant
*m_next
;
147 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
148 #define gettwo(x) (((x)->m_opcode)&0xffff)
150 static const enum m68k_register m68000_ctrl
[] = { 0 };
151 static const enum m68k_register m68010_ctrl
[] = {
155 static const enum m68k_register m68020_ctrl
[] = {
156 SFC
, DFC
, USP
, VBR
, CACR
, CAAR
, MSP
, ISP
,
159 static const enum m68k_register m68040_ctrl
[] = {
160 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
,
161 USP
, VBR
, MSP
, ISP
, MMUSR
, URP
, SRP
,
164 static const enum m68k_register m68060_ctrl
[] = {
165 SFC
, DFC
, CACR
, TC
, ITT0
, ITT1
, DTT0
, DTT1
, BUSCR
,
166 USP
, VBR
, URP
, SRP
, PCR
,
169 static const enum m68k_register mcf_ctrl
[] = {
170 CACR
, TC
, ACR0
, ACR1
, ACR2
, ACR3
, VBR
, ROMBAR
,
171 RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
,
174 static const enum m68k_register mcf51_ctrl
[] = {
178 static const enum m68k_register mcf5206_ctrl
[] = {
179 CACR
, ACR0
, ACR1
, VBR
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
182 static const enum m68k_register mcf5208_ctrl
[] = {
183 CACR
, ACR0
, ACR1
, VBR
, RAMBAR
, RAMBAR1
,
186 static const enum m68k_register mcf5210a_ctrl
[] = {
187 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR
, RAMBAR1
, MBAR
,
190 static const enum m68k_register mcf5213_ctrl
[] = {
191 VBR
, RAMBAR
, RAMBAR1
, FLASHBAR
,
194 static const enum m68k_register mcf5216_ctrl
[] = {
195 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
198 static const enum m68k_register mcf5221x_ctrl
[] = {
199 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
202 static const enum m68k_register mcf52223_ctrl
[] = {
203 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
206 static const enum m68k_register mcf52235_ctrl
[] = {
207 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
210 static const enum m68k_register mcf5225_ctrl
[] = {
211 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, MBAR
, RAMBAR1
,
214 static const enum m68k_register mcf52259_ctrl
[] = {
215 VBR
, FLASHBAR
, RAMBAR
, RAMBAR1
,
218 static const enum m68k_register mcf52277_ctrl
[] = {
219 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
222 static const enum m68k_register mcf5235_ctrl
[] = {
223 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
226 static const enum m68k_register mcf5249_ctrl
[] = {
227 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
230 static const enum m68k_register mcf5250_ctrl
[] = {
234 static const enum m68k_register mcf5253_ctrl
[] = {
235 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR1
, RAMBAR
, MBAR
, MBAR2
,
238 static const enum m68k_register mcf5271_ctrl
[] = {
239 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
242 static const enum m68k_register mcf5272_ctrl
[] = {
243 VBR
, CACR
, ACR0
, ACR1
, ROMBAR
, RAMBAR_ALT
, RAMBAR0
, MBAR
,
246 static const enum m68k_register mcf5275_ctrl
[] = {
247 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
250 static const enum m68k_register mcf5282_ctrl
[] = {
251 VBR
, CACR
, ACR0
, ACR1
, FLASHBAR
, RAMBAR
, RAMBAR1
,
254 static const enum m68k_register mcf53017_ctrl
[] = {
255 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
258 static const enum m68k_register mcf5307_ctrl
[] = {
259 VBR
, CACR
, ACR0
, ACR1
, RAMBAR0
, RAMBAR_ALT
, MBAR
,
262 static const enum m68k_register mcf5329_ctrl
[] = {
263 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
266 static const enum m68k_register mcf5373_ctrl
[] = {
267 VBR
, CACR
, ACR0
, ACR1
, RAMBAR
, RAMBAR1
,
270 static const enum m68k_register mcfv4e_ctrl
[] = {
271 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
272 VBR
, PC
, ROMBAR0
, ROMBAR1
, RAMBAR0
, RAMBAR1
,
274 MPCR
/* Multiprocessor Control register */,
275 EDRAMBAR
/* Embedded DRAM Base Address Register */,
276 /* Permutation control registers. */
277 PCR1U0
, PCR1L0
, PCR1U1
, PCR1L1
, PCR2U0
, PCR2L0
, PCR2U1
, PCR2L1
,
278 PCR3U0
, PCR3L0
, PCR3U1
, PCR3L1
,
280 TC
/* ASID */, BUSCR
/* MMUBAR */,
281 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
282 MBAR1
/* MBAR */, MBAR2
/* SECMBAR */, MBAR0
/* SECMBAR */,
283 ROMBAR
/* ROMBAR0 */, RAMBAR
/* RAMBAR1 */,
286 static const enum m68k_register mcf5407_ctrl
[] = {
287 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
,
288 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
291 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
292 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
295 static const enum m68k_register mcf54418_ctrl
[] = {
296 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, ACR4
, ACR5
, ACR6
, ACR7
, MMUBAR
, RGPIOBAR
,
299 TC
/* ASID */, BUSCR
/* MMUBAR */,
300 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
301 RAMBAR
/* RAMBAR1 */,
304 static const enum m68k_register mcf54455_ctrl
[] = {
305 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
308 TC
/* ASID */, BUSCR
/* MMUBAR */,
309 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
310 RAMBAR
/* RAMBAR1 */,
313 static const enum m68k_register mcf5475_ctrl
[] = {
314 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
315 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
317 TC
/* ASID */, BUSCR
/* MMUBAR */,
318 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
319 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
322 static const enum m68k_register mcf5485_ctrl
[] = {
323 CACR
, ASID
, ACR0
, ACR1
, ACR2
, ACR3
, MMUBAR
,
324 VBR
, PC
, RAMBAR0
, RAMBAR1
, MBAR
,
326 TC
/* ASID */, BUSCR
/* MMUBAR */,
327 ITT0
/* ACR0 */, ITT1
/* ACR1 */, DTT0
/* ACR2 */, DTT1
/* ACR3 */,
328 MBAR1
/* MBAR */, RAMBAR
/* RAMBAR1 */,
331 static const enum m68k_register fido_ctrl
[] = {
332 SFC
, DFC
, USP
, VBR
, CAC
, MBO
,
335 #define cpu32_ctrl m68010_ctrl
337 static const enum m68k_register
*control_regs
;
339 /* Internal form of a 68020 instruction. */
343 const char *args
; /* List of opcode info. */
346 int numo
; /* Number of shorts in opcode. */
349 struct m68k_op operands
[6];
351 int nexp
; /* Number of exprs in use. */
352 struct m68k_exp exprs
[4];
354 int nfrag
; /* Number of frags we have to produce. */
357 int fragoff
; /* Where in the current opcode the frag ends. */
364 int nrel
; /* Num of reloc structs in use. */
371 /* In a pc relative address the difference between the address
372 of the offset and the address that the offset is relative
373 to. This depends on the addressing mode. Basically this
374 is the value to put in the offset field to address the
375 first byte of the offset, without regarding the special
376 significance of some values (in the branch instruction, for
379 /* Whether this expression needs special pic relocation, and if
381 enum pic_relocation pic_reloc
;
383 reloc
[5]; /* Five is enough??? */
386 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
387 #define float_of_arch(x) ((x) & mfloat)
388 #define mmu_of_arch(x) ((x) & mmmu)
389 #define arch_coldfire_p(x) ((x) & mcfisa_a)
390 #define arch_coldfire_fpu(x) ((x) & cfloat)
392 /* Macros for determining if cpu supports a specific addressing mode. */
393 #define HAVE_LONG_DISP(x) \
394 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
395 #define HAVE_LONG_CALL(x) \
396 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
397 #define HAVE_LONG_COND(x) \
398 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
399 #define HAVE_LONG_BRANCH(x) \
400 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
401 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
403 static struct m68k_it the_ins
; /* The instruction being assembled. */
405 #define op(ex) ((ex)->exp.X_op)
406 #define adds(ex) ((ex)->exp.X_add_symbol)
407 #define subs(ex) ((ex)->exp.X_op_symbol)
408 #define offs(ex) ((ex)->exp.X_add_number)
410 /* Macros for adding things to the m68k_it struct. */
411 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
413 /* Like addword, but goes BEFORE general operands. */
416 insop (int w
, const struct m68k_incant
*opcode
)
419 for (z
= the_ins
.numo
; z
> opcode
->m_codenum
; --z
)
420 the_ins
.opcode
[z
] = the_ins
.opcode
[z
- 1];
421 for (z
= 0; z
< the_ins
.nrel
; z
++)
422 the_ins
.reloc
[z
].n
+= 2;
423 for (z
= 0; z
< the_ins
.nfrag
; z
++)
424 the_ins
.fragb
[z
].fragoff
++;
425 the_ins
.opcode
[opcode
->m_codenum
] = w
;
429 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
432 add_fix (int width
, struct m68k_exp
*exp
, int pc_rel
, int pc_fix
)
434 the_ins
.reloc
[the_ins
.nrel
].n
= (width
== 'B' || width
== '3'
435 ? the_ins
.numo
* 2 - 1
437 ? the_ins
.numo
* 2 + 1
438 : the_ins
.numo
* 2));
439 the_ins
.reloc
[the_ins
.nrel
].exp
= exp
->exp
;
440 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
441 the_ins
.reloc
[the_ins
.nrel
].pcrel_fix
= pc_fix
;
442 the_ins
.reloc
[the_ins
.nrel
].pic_reloc
= exp
->pic_reloc
;
443 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
446 /* Cause an extra frag to be generated here, inserting up to 10 bytes
447 (that value is chosen in the frag_var call in md_assemble). TYPE
448 is the subtype of the frag to be generated; its primary type is
449 rs_machine_dependent.
451 The TYPE parameter is also used by md_convert_frag_1 and
452 md_estimate_size_before_relax. The appropriate type of fixup will
453 be emitted by md_convert_frag_1.
455 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
457 add_frag (symbolS
*add
, offsetT off
, int type
)
459 the_ins
.fragb
[the_ins
.nfrag
].fragoff
= the_ins
.numo
;
460 the_ins
.fragb
[the_ins
.nfrag
].fadd
= add
;
461 the_ins
.fragb
[the_ins
.nfrag
].foff
= off
;
462 the_ins
.fragb
[the_ins
.nfrag
++].fragty
= type
;
466 (op (ex) != O_constant && op (ex) != O_big)
468 static char *crack_operand (char *str
, struct m68k_op
*opP
);
469 static int get_num (struct m68k_exp
*exp
, int ok
);
470 static int reverse_16_bits (int in
);
471 static int reverse_8_bits (int in
);
472 static void install_gen_operand (int mode
, int val
);
473 static void install_operand (int mode
, int val
);
474 static void s_bss (int);
475 static void s_data1 (int);
476 static void s_data2 (int);
477 static void s_even (int);
478 static void s_proc (int);
479 static void s_chip (int);
480 static void s_fopt (int);
481 static void s_opt (int);
482 static void s_reg (int);
483 static void s_restore (int);
484 static void s_save (int);
485 static void s_mri_if (int);
486 static void s_mri_else (int);
487 static void s_mri_endi (int);
488 static void s_mri_break (int);
489 static void s_mri_next (int);
490 static void s_mri_for (int);
491 static void s_mri_endf (int);
492 static void s_mri_repeat (int);
493 static void s_mri_until (int);
494 static void s_mri_while (int);
495 static void s_mri_endw (int);
496 static void s_m68k_cpu (int);
497 static void s_m68k_arch (int);
501 unsigned long arch
; /* Architecture features. */
502 const enum m68k_register
*control_regs
; /* Control regs on chip */
503 const char *name
; /* Name */
504 int alias
; /* Alias for a canonical name. If 1, then
505 succeeds canonical name, if -1 then
506 succeeds canonical name, if <-1 ||>1 this is a
507 deprecated name, and the next/previous name
511 /* We hold flags for features explicitly enabled and explicitly
513 static int current_architecture
;
514 static int not_current_architecture
;
515 static const struct m68k_cpu
*selected_arch
;
516 static const struct m68k_cpu
*selected_cpu
;
517 static int initialized
;
519 /* Architecture models. */
520 static const struct m68k_cpu m68k_archs
[] =
522 {m68000
, m68000_ctrl
, "68000", 0},
523 {m68010
, m68010_ctrl
, "68010", 0},
524 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
525 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
526 {m68040
, m68040_ctrl
, "68040", 0},
527 {m68060
, m68060_ctrl
, "68060", 0},
528 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
529 {fido_a
, fido_ctrl
, "fidoa", 0},
530 {mcfisa_a
|mcfhwdiv
, NULL
, "isaa", 0},
531 {mcfisa_a
|mcfhwdiv
|mcfisa_aa
|mcfusp
, NULL
, "isaaplus", 0},
532 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfusp
, NULL
, "isab", 0},
533 {mcfisa_a
|mcfhwdiv
|mcfisa_c
|mcfusp
, NULL
, "isac", 0},
534 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfmac
|mcfusp
, mcf_ctrl
, "cfv4", 0},
535 {mcfisa_a
|mcfhwdiv
|mcfisa_b
|mcfemac
|mcfusp
|cfloat
, mcfv4e_ctrl
, "cfv4e", 0},
539 /* For -mno-mac we want to turn off all types of mac. */
540 static const unsigned no_mac
= mcfmac
| mcfemac
;
542 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
544 static const struct m68k_cpu m68k_extensions
[] =
546 {m68851
, NULL
, "68851", -1},
547 {m68881
, NULL
, "68881", -1},
548 {m68881
, NULL
, "68882", -1},
550 {cfloat
|m68881
, NULL
, "float", 0},
552 {mcfhwdiv
, NULL
, "div", 1},
553 {mcfusp
, NULL
, "usp", 1},
554 {mcfmac
, (void *)&no_mac
, "mac", 1},
555 {mcfemac
, NULL
, "emac", 1},
561 static const struct m68k_cpu m68k_cpus
[] =
563 {m68000
, m68000_ctrl
, "68000", 0},
564 {m68000
, m68000_ctrl
, "68ec000", 1},
565 {m68000
, m68000_ctrl
, "68hc000", 1},
566 {m68000
, m68000_ctrl
, "68hc001", 1},
567 {m68000
, m68000_ctrl
, "68008", 1},
568 {m68000
, m68000_ctrl
, "68302", 1},
569 {m68000
, m68000_ctrl
, "68306", 1},
570 {m68000
, m68000_ctrl
, "68307", 1},
571 {m68000
, m68000_ctrl
, "68322", 1},
572 {m68000
, m68000_ctrl
, "68356", 1},
573 {m68010
, m68010_ctrl
, "68010", 0},
574 {m68020
|m68881
|m68851
, m68020_ctrl
, "68020", 0},
575 {m68020
|m68881
|m68851
, m68020_ctrl
, "68k", 1},
576 {m68020
|m68881
|m68851
, m68020_ctrl
, "68ec020", 1},
577 {m68030
|m68881
|m68851
, m68020_ctrl
, "68030", 0},
578 {m68030
|m68881
|m68851
, m68020_ctrl
, "68ec030", 1},
579 {m68040
, m68040_ctrl
, "68040", 0},
580 {m68040
, m68040_ctrl
, "68ec040", 1},
581 {m68060
, m68060_ctrl
, "68060", 0},
582 {m68060
, m68060_ctrl
, "68ec060", 1},
584 {cpu32
|m68881
, cpu32_ctrl
, "cpu32", 0},
585 {cpu32
|m68881
, cpu32_ctrl
, "68330", 1},
586 {cpu32
|m68881
, cpu32_ctrl
, "68331", 1},
587 {cpu32
|m68881
, cpu32_ctrl
, "68332", 1},
588 {cpu32
|m68881
, cpu32_ctrl
, "68333", 1},
589 {cpu32
|m68881
, cpu32_ctrl
, "68334", 1},
590 {cpu32
|m68881
, cpu32_ctrl
, "68336", 1},
591 {cpu32
|m68881
, cpu32_ctrl
, "68340", 1},
592 {cpu32
|m68881
, cpu32_ctrl
, "68341", 1},
593 {cpu32
|m68881
, cpu32_ctrl
, "68349", 1},
594 {cpu32
|m68881
, cpu32_ctrl
, "68360", 1},
596 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51", 0},
597 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51ac", 1},
598 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51ag", 1},
599 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51cn", 1},
600 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51em", 1},
601 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51je", 1},
602 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51jf", 1},
603 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51jg", 1},
604 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51jm", 1},
605 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfmac
, mcf51_ctrl
, "51mm", 1},
606 {mcfisa_a
|mcfisa_c
|mcfusp
, mcf51_ctrl
, "51qe", 1},
607 {mcfisa_a
|mcfisa_c
|mcfusp
|mcfemac
, mcf51_ctrl
, "51qm", 1},
609 {mcfisa_a
, mcf_ctrl
, "5200", 0},
610 {mcfisa_a
, mcf_ctrl
, "5202", 1},
611 {mcfisa_a
, mcf_ctrl
, "5204", 1},
612 {mcfisa_a
, mcf5206_ctrl
, "5206", 1},
614 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5206_ctrl
, "5206e", 0},
616 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5207", -1},
617 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5208_ctrl
, "5208", 0},
619 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5210a", 0},
620 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5210a_ctrl
, "5211a", 1},
622 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5211", -1},
623 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5212", -1},
624 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5213_ctrl
, "5213", 0},
626 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5214", -1},
627 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "5216", 0},
628 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5216_ctrl
, "521x", 2},
630 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5221x_ctrl
, "5221x", 0},
632 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52221", -1},
633 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf52223_ctrl
, "52223", 0},
635 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52230", -1},
636 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52233", -1},
637 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52234", -1},
638 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52235_ctrl
, "52235", 0},
640 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5224", -1},
641 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfmac
|mcfusp
, mcf5225_ctrl
, "5225", 0},
643 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52277_ctrl
, "52274", -1},
644 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52277_ctrl
, "52277", 0},
646 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5232", -1},
647 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5233", -1},
648 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5234", -1},
649 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "5235", -1},
650 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5235_ctrl
, "523x", 0},
652 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5249_ctrl
, "5249", 0},
653 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5250_ctrl
, "5250", 0},
654 {mcfisa_a
|mcfhwdiv
|mcfemac
, mcf5253_ctrl
, "5253", 0},
656 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52252", -1},
657 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52254", -1},
658 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52255", -1},
659 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52256", -1},
660 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52258", -1},
661 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf52259_ctrl
, "52259", 0},
663 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5270", -1},
664 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5271_ctrl
, "5271", 0},
666 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5272_ctrl
, "5272", 0},
668 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5274", -1},
669 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5275_ctrl
, "5275", 0},
671 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5280", -1},
672 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5281", -1},
673 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "5282", -1},
674 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5282_ctrl
, "528x", 0},
676 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53011", -1},
677 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53012", -1},
678 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53013", -1},
679 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53014", -1},
680 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53015", -1},
681 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53016", -1},
682 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf53017_ctrl
, "53017", 0},
684 {mcfisa_a
|mcfhwdiv
|mcfmac
, mcf5307_ctrl
, "5307", 0},
686 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5327", -1},
687 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5328", -1},
688 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "5329", -1},
689 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5329_ctrl
, "532x", 0},
691 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5372", -1},
692 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "5373", -1},
693 {mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfemac
|mcfusp
, mcf5373_ctrl
, "537x", 0},
695 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfmac
, mcf5407_ctrl
, "5407",0},
697 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54410", -1},
698 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54415", -1},
699 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54416", -1},
700 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54417", -1},
701 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54418_ctrl
, "54418", 0},
703 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54450", -1},
704 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54451", -1},
705 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54452", -1},
706 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54453", -1},
707 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54454", -1},
708 {mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfemac
|mcfusp
, mcf54455_ctrl
, "54455", 0},
710 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5470", -1},
711 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5471", -1},
712 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5472", -1},
713 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5473", -1},
714 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5474", -1},
715 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "5475", -1},
716 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5475_ctrl
, "547x", 0},
718 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5480", -1},
719 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5481", -1},
720 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5482", -1},
721 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5483", -1},
722 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5484", -1},
723 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "5485", -1},
724 {mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfemac
|mcfusp
|cfloat
, mcf5485_ctrl
, "548x", 0},
726 {fido_a
, fido_ctrl
, "fidoa", 0},
727 {fido_a
, fido_ctrl
, "fido", 1},
732 static const struct m68k_cpu
*m68k_lookup_cpu
733 (const char *, const struct m68k_cpu
*, int, int *);
734 static int m68k_set_arch (const char *, int, int);
735 static int m68k_set_cpu (const char *, int, int);
736 static int m68k_set_extension (const char *, int, int);
737 static void m68k_init_arch (void);
739 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
740 architecture and we have a lot of relaxation modes. */
742 /* Macros used in the relaxation code. */
743 #define TAB(x,y) (((x) << 2) + (y))
744 #define TABTYPE(x) ((x) >> 2)
746 /* Relaxation states. */
752 /* Here are all the relaxation modes we support. First we can relax ordinary
753 branches. On 68020 and higher and on CPU32 all branch instructions take
754 three forms, so on these CPUs all branches always remain as such. When we
755 have to expand to the LONG form on a 68000, though, we substitute an
756 absolute jump instead. This is a direct replacement for unconditional
757 branches and a branch over a jump for conditional branches. However, if the
758 user requires PIC and disables this with --pcrel, we can only relax between
759 BYTE and SHORT forms, punting if that isn't enough. This gives us four
760 different relaxation modes for branches: */
762 #define BRANCHBWL 0 /* Branch byte, word, or long. */
763 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
764 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
765 #define BRANCHBW 3 /* Branch byte or word. */
767 /* We also relax coprocessor branches and DBcc's. All CPUs that support
768 coprocessor branches support them in word and long forms, so we have only
769 one relaxation mode for them. DBcc's are word only on all CPUs. We can
770 relax them to the LONG form with a branch-around sequence. This sequence
771 can use a long branch (if available) or an absolute jump (if acceptable).
772 This gives us two relaxation modes. If long branches are not available and
773 absolute jumps are not acceptable, we don't relax DBcc's. */
775 #define FBRANCH 4 /* Coprocessor branch. */
776 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
777 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
779 /* That's all for instruction relaxation. However, we also relax PC-relative
780 operands. Specifically, we have three operand relaxation modes. On the
781 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
782 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
783 two. Also PC+displacement+index operands in their simple form (with a non-
784 suppressed index without memory indirection) are supported on all CPUs, but
785 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
786 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
787 form of the PC+displacement+index operand. Finally, some absolute operands
788 can be relaxed down to 16-bit PC-relative. */
790 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
791 #define PCINDEX 8 /* PC + displacement + index. */
792 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
794 /* This relaxation is required for branches where there is no long
795 branch and we are in pcrel mode. We generate a bne/beq pair. */
796 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
799 /* Note that calls to frag_var need to specify the maximum expansion
800 needed; this is currently 12 bytes for bne/beq pair. */
801 #define FRAG_VAR_SIZE 12
804 How far Forward this mode will reach:
805 How far Backward this mode will reach:
806 How many bytes this mode will add to the size of the frag
807 Which mode to go to if the offset won't fit in this one
809 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
810 relax_typeS md_relax_table
[] =
812 { 127, -128, 0, TAB (BRANCHBWL
, SHORT
) },
813 { 32767, -32768, 2, TAB (BRANCHBWL
, LONG
) },
817 { 127, -128, 0, TAB (BRABSJUNC
, SHORT
) },
818 { 32767, -32768, 2, TAB (BRABSJUNC
, LONG
) },
822 { 127, -128, 0, TAB (BRABSJCOND
, SHORT
) },
823 { 32767, -32768, 2, TAB (BRABSJCOND
, LONG
) },
827 { 127, -128, 0, TAB (BRANCHBW
, SHORT
) },
832 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
833 { 32767, -32768, 2, TAB (FBRANCH
, LONG
) },
837 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
838 { 32767, -32768, 2, TAB (DBCCLBR
, LONG
) },
842 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
843 { 32767, -32768, 2, TAB (DBCCABSJ
, LONG
) },
847 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
848 { 32767, -32768, 2, TAB (PCREL1632
, LONG
) },
852 { 125, -130, 0, TAB (PCINDEX
, SHORT
) },
853 { 32765, -32770, 2, TAB (PCINDEX
, LONG
) },
857 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
858 { 32767, -32768, 2, TAB (ABSTOPCREL
, LONG
) },
862 { 127, -128, 0, TAB (BRANCHBWPL
, SHORT
) },
863 { 32767, -32768, 2, TAB (BRANCHBWPL
, LONG
) },
868 /* These are the machine dependent pseudo-ops. These are included so
869 the assembler can work on the output from the SUN C compiler, which
872 /* This table describes all the machine specific pseudo-ops the assembler
873 has to support. The fields are:
874 pseudo-op name without dot
875 function to call to execute this pseudo-op
876 Integer arg to pass to the function. */
877 const pseudo_typeS md_pseudo_table
[] =
879 {"data1", s_data1
, 0},
880 {"data2", s_data2
, 0},
883 {"skip", s_space
, 0},
885 {"align", s_align_bytes
, 0},
886 {"swbeg", s_ignore
, 0},
887 {"long", m68k_elf_cons
, 4},
888 {"extend", float_cons
, 'x'},
889 {"ldouble", float_cons
, 'x'},
891 {"arch", s_m68k_arch
, 0},
892 {"cpu", s_m68k_cpu
, 0},
893 {"gnu_attribute", m68k_elf_gnu_attribute
, 0},
895 /* The following pseudo-ops are supported for MRI compatibility. */
897 {"comline", s_space
, 1},
899 {"mask2", s_ignore
, 0},
902 {"restore", s_restore
, 0},
906 {"if.b", s_mri_if
, 'b'},
907 {"if.w", s_mri_if
, 'w'},
908 {"if.l", s_mri_if
, 'l'},
909 {"else", s_mri_else
, 0},
910 {"else.s", s_mri_else
, 's'},
911 {"else.l", s_mri_else
, 'l'},
912 {"endi", s_mri_endi
, 0},
913 {"break", s_mri_break
, 0},
914 {"break.s", s_mri_break
, 's'},
915 {"break.l", s_mri_break
, 'l'},
916 {"next", s_mri_next
, 0},
917 {"next.s", s_mri_next
, 's'},
918 {"next.l", s_mri_next
, 'l'},
919 {"for", s_mri_for
, 0},
920 {"for.b", s_mri_for
, 'b'},
921 {"for.w", s_mri_for
, 'w'},
922 {"for.l", s_mri_for
, 'l'},
923 {"endf", s_mri_endf
, 0},
924 {"repeat", s_mri_repeat
, 0},
925 {"until", s_mri_until
, 0},
926 {"until.b", s_mri_until
, 'b'},
927 {"until.w", s_mri_until
, 'w'},
928 {"until.l", s_mri_until
, 'l'},
929 {"while", s_mri_while
, 0},
930 {"while.b", s_mri_while
, 'b'},
931 {"while.w", s_mri_while
, 'w'},
932 {"while.l", s_mri_while
, 'l'},
933 {"endw", s_mri_endw
, 0},
938 /* The mote pseudo ops are put into the opcode table, since they
939 don't start with a . they look like opcodes to gas. */
941 const pseudo_typeS mote_pseudo_table
[] =
954 {"xdef", s_globl
, 0},
955 {"align", s_align_bytes
, 0},
959 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
960 gives identical results to a 32-bit host. */
961 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
962 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
964 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
965 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
966 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
967 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
969 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
970 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
971 #define islong(x) (1)
973 static char notend_table
[256];
974 static char alt_notend_table
[256];
976 (! (notend_table[(unsigned char) *s] \
978 && alt_notend_table[(unsigned char) s[1]])))
981 /* Return zero if the reference to SYMBOL from within the same segment may
984 /* On an ELF system, we can't relax an externally visible symbol,
985 because it may be overridden by a shared library. However, if
986 TARGET_OS is "elf", then we presume that we are assembling for an
987 embedded system, in which case we don't have to worry about shared
988 libraries, and we can relax any external sym. */
990 #define relaxable_symbol(symbol) \
991 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
992 || S_IS_WEAK (symbol)))
994 /* Compute the relocation code for a fixup of SIZE bytes, using pc
995 relative relocation if PCREL is non-zero. PIC says whether a special
996 pic relocation was requested. */
998 static bfd_reloc_code_real_type
999 get_reloc_code (int size
, int pcrel
, enum pic_relocation pic
)
1007 return BFD_RELOC_8_GOT_PCREL
;
1009 return BFD_RELOC_16_GOT_PCREL
;
1011 return BFD_RELOC_32_GOT_PCREL
;
1019 return BFD_RELOC_8_GOTOFF
;
1021 return BFD_RELOC_16_GOTOFF
;
1023 return BFD_RELOC_32_GOTOFF
;
1031 return BFD_RELOC_8_PLT_PCREL
;
1033 return BFD_RELOC_16_PLT_PCREL
;
1035 return BFD_RELOC_32_PLT_PCREL
;
1043 return BFD_RELOC_8_PLTOFF
;
1045 return BFD_RELOC_16_PLTOFF
;
1047 return BFD_RELOC_32_PLTOFF
;
1055 return BFD_RELOC_68K_TLS_GD8
;
1057 return BFD_RELOC_68K_TLS_GD16
;
1059 return BFD_RELOC_68K_TLS_GD32
;
1067 return BFD_RELOC_68K_TLS_LDM8
;
1069 return BFD_RELOC_68K_TLS_LDM16
;
1071 return BFD_RELOC_68K_TLS_LDM32
;
1079 return BFD_RELOC_68K_TLS_LDO8
;
1081 return BFD_RELOC_68K_TLS_LDO16
;
1083 return BFD_RELOC_68K_TLS_LDO32
;
1091 return BFD_RELOC_68K_TLS_IE8
;
1093 return BFD_RELOC_68K_TLS_IE16
;
1095 return BFD_RELOC_68K_TLS_IE32
;
1103 return BFD_RELOC_68K_TLS_LE8
;
1105 return BFD_RELOC_68K_TLS_LE16
;
1107 return BFD_RELOC_68K_TLS_LE32
;
1117 return BFD_RELOC_8_PCREL
;
1119 return BFD_RELOC_16_PCREL
;
1121 return BFD_RELOC_32_PCREL
;
1131 return BFD_RELOC_16
;
1133 return BFD_RELOC_32
;
1140 if (pic
== pic_none
)
1141 as_bad (_("Can not do %d byte pc-relative relocation"), size
);
1143 as_bad (_("Can not do %d byte pc-relative pic relocation"), size
);
1147 if (pic
== pic_none
)
1148 as_bad (_("Can not do %d byte relocation"), size
);
1150 as_bad (_("Can not do %d byte pic relocation"), size
);
1153 return BFD_RELOC_NONE
;
1156 /* Here we decide which fixups can be adjusted to make them relative
1157 to the beginning of the section instead of the symbol. Basically
1158 we need to make sure that the dynamic relocations are done
1159 correctly, so in some cases we force the original symbol to be
1162 tc_m68k_fix_adjustable (fixS
*fixP
)
1164 /* Adjust_reloc_syms doesn't know about the GOT. */
1165 switch (fixP
->fx_r_type
)
1167 case BFD_RELOC_8_GOT_PCREL
:
1168 case BFD_RELOC_16_GOT_PCREL
:
1169 case BFD_RELOC_32_GOT_PCREL
:
1170 case BFD_RELOC_8_GOTOFF
:
1171 case BFD_RELOC_16_GOTOFF
:
1172 case BFD_RELOC_32_GOTOFF
:
1173 case BFD_RELOC_8_PLT_PCREL
:
1174 case BFD_RELOC_16_PLT_PCREL
:
1175 case BFD_RELOC_32_PLT_PCREL
:
1176 case BFD_RELOC_8_PLTOFF
:
1177 case BFD_RELOC_16_PLTOFF
:
1178 case BFD_RELOC_32_PLTOFF
:
1179 case BFD_RELOC_68K_TLS_GD32
:
1180 case BFD_RELOC_68K_TLS_GD16
:
1181 case BFD_RELOC_68K_TLS_GD8
:
1182 case BFD_RELOC_68K_TLS_LDM32
:
1183 case BFD_RELOC_68K_TLS_LDM16
:
1184 case BFD_RELOC_68K_TLS_LDM8
:
1185 case BFD_RELOC_68K_TLS_LDO32
:
1186 case BFD_RELOC_68K_TLS_LDO16
:
1187 case BFD_RELOC_68K_TLS_LDO8
:
1188 case BFD_RELOC_68K_TLS_IE32
:
1189 case BFD_RELOC_68K_TLS_IE16
:
1190 case BFD_RELOC_68K_TLS_IE8
:
1191 case BFD_RELOC_68K_TLS_LE32
:
1192 case BFD_RELOC_68K_TLS_LE16
:
1193 case BFD_RELOC_68K_TLS_LE8
:
1196 case BFD_RELOC_VTABLE_INHERIT
:
1197 case BFD_RELOC_VTABLE_ENTRY
:
1206 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
1209 bfd_reloc_code_real_type code
;
1211 /* If the tcbit is set, then this was a fixup of a negative value
1212 that was never resolved. We do not have a reloc to handle this,
1213 so just return. We assume that other code will have detected this
1214 situation and produced a helpful error message, so we just tell the
1215 user that the reloc cannot be produced. */
1219 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1220 _("Unable to produce reloc against symbol '%s'"),
1221 S_GET_NAME (fixp
->fx_addsy
));
1225 if (fixp
->fx_r_type
!= BFD_RELOC_NONE
)
1227 code
= fixp
->fx_r_type
;
1229 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1230 that fixup_segment converted a non-PC relative reloc into a
1231 PC relative reloc. In such a case, we need to convert the
1238 code
= BFD_RELOC_8_PCREL
;
1241 code
= BFD_RELOC_16_PCREL
;
1244 code
= BFD_RELOC_32_PCREL
;
1246 case BFD_RELOC_8_PCREL
:
1247 case BFD_RELOC_16_PCREL
:
1248 case BFD_RELOC_32_PCREL
:
1249 case BFD_RELOC_8_GOT_PCREL
:
1250 case BFD_RELOC_16_GOT_PCREL
:
1251 case BFD_RELOC_32_GOT_PCREL
:
1252 case BFD_RELOC_8_GOTOFF
:
1253 case BFD_RELOC_16_GOTOFF
:
1254 case BFD_RELOC_32_GOTOFF
:
1255 case BFD_RELOC_8_PLT_PCREL
:
1256 case BFD_RELOC_16_PLT_PCREL
:
1257 case BFD_RELOC_32_PLT_PCREL
:
1258 case BFD_RELOC_8_PLTOFF
:
1259 case BFD_RELOC_16_PLTOFF
:
1260 case BFD_RELOC_32_PLTOFF
:
1261 case BFD_RELOC_68K_TLS_GD32
:
1262 case BFD_RELOC_68K_TLS_GD16
:
1263 case BFD_RELOC_68K_TLS_GD8
:
1264 case BFD_RELOC_68K_TLS_LDM32
:
1265 case BFD_RELOC_68K_TLS_LDM16
:
1266 case BFD_RELOC_68K_TLS_LDM8
:
1267 case BFD_RELOC_68K_TLS_LDO32
:
1268 case BFD_RELOC_68K_TLS_LDO16
:
1269 case BFD_RELOC_68K_TLS_LDO8
:
1270 case BFD_RELOC_68K_TLS_IE32
:
1271 case BFD_RELOC_68K_TLS_IE16
:
1272 case BFD_RELOC_68K_TLS_IE8
:
1273 case BFD_RELOC_68K_TLS_LE32
:
1274 case BFD_RELOC_68K_TLS_LE16
:
1275 case BFD_RELOC_68K_TLS_LE8
:
1278 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
1279 _("Cannot make %s relocation PC relative"),
1280 bfd_get_reloc_code_name (code
));
1286 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1287 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1289 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1290 MAP (1, 0, BFD_RELOC_8
);
1291 MAP (2, 0, BFD_RELOC_16
);
1292 MAP (4, 0, BFD_RELOC_32
);
1293 MAP (1, 1, BFD_RELOC_8_PCREL
);
1294 MAP (2, 1, BFD_RELOC_16_PCREL
);
1295 MAP (4, 1, BFD_RELOC_32_PCREL
);
1303 reloc
= XNEW (arelent
);
1304 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
1305 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
1306 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1307 if (!fixp
->fx_pcrel
)
1308 reloc
->addend
= fixp
->fx_addnumber
;
1310 reloc
->addend
= (section
->vma
1311 + fixp
->fx_pcrel_adjust
1312 + fixp
->fx_addnumber
1313 + md_pcrel_from (fixp
));
1315 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1316 gas_assert (reloc
->howto
!= 0);
1321 /* Handle of the OPCODE hash table. NULL means any use before
1322 m68k_ip_begin() will crash. */
1323 static htab_t op_hash
;
1325 /* Assemble an m68k instruction. */
1328 m68k_ip (char *instring
)
1331 struct m68k_op
*opP
;
1332 const struct m68k_incant
*opcode
;
1334 int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1335 char *pdot
, *pdotmove
;
1336 enum m68k_size siz1
, siz2
;
1340 struct m68k_op operands_backup
[6];
1341 LITTLENUM_TYPE words
[6];
1342 LITTLENUM_TYPE
*wordp
;
1343 unsigned long ok_arch
= 0;
1345 if (*instring
== ' ')
1346 instring
++; /* Skip leading whitespace. */
1348 /* Scan up to end of operation-code, which MUST end in end-of-string
1349 or exactly 1 space. */
1351 for (p
= instring
; *p
!= '\0'; p
++)
1361 the_ins
.error
= _("No operator");
1365 /* p now points to the end of the opcode name, probably whitespace.
1366 Make sure the name is null terminated by clobbering the
1367 whitespace, look it up in the hash table, then fix it back.
1368 Remove a dot, first, since the opcode tables have none. */
1371 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1372 *pdotmove
= pdotmove
[1];
1378 opcode
= (const struct m68k_incant
*) str_hash_find (op_hash
, instring
);
1383 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1384 *pdotmove
= pdotmove
[-1];
1391 the_ins
.error
= _("Unknown operator");
1395 /* Found a legitimate opcode, start matching operands. */
1399 if (opcode
->m_operands
== 0)
1401 char *old
= input_line_pointer
;
1403 input_line_pointer
= p
;
1404 /* Ahh - it's a motorola style pseudo op. */
1405 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1406 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1407 input_line_pointer
= old
;
1413 if (flag_mri
&& opcode
->m_opnum
== 0)
1415 /* In MRI mode, random garbage is allowed after an instruction
1416 which accepts no operands. */
1417 the_ins
.args
= opcode
->m_operands
;
1418 the_ins
.numargs
= opcode
->m_opnum
;
1419 the_ins
.numo
= opcode
->m_codenum
;
1420 the_ins
.opcode
[0] = getone (opcode
);
1421 the_ins
.opcode
[1] = gettwo (opcode
);
1425 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1427 p
= crack_operand (p
, opP
);
1431 the_ins
.error
= opP
->error
;
1436 opsfound
= opP
- &the_ins
.operands
[0];
1438 /* This ugly hack is to support the floating pt opcodes in their
1439 standard form. Essentially, we fake a first entry of type COP#1 */
1440 if (opcode
->m_operands
[0] == 'I')
1444 for (n
= opsfound
; n
> 0; --n
)
1445 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1447 memset (&the_ins
.operands
[0], '\0', sizeof (the_ins
.operands
[0]));
1448 the_ins
.operands
[0].mode
= CONTROL
;
1449 the_ins
.operands
[0].reg
= m68k_float_copnum
;
1453 /* We've got the operands. Find an opcode that'll accept them. */
1456 /* If we didn't get the right number of ops, or we have no
1457 common model with this pattern then reject this pattern. */
1459 ok_arch
|= opcode
->m_arch
;
1460 if (opsfound
!= opcode
->m_opnum
1461 || ((opcode
->m_arch
& current_architecture
) == 0))
1467 /* Make a copy of the operands of this insn so that
1468 we can modify them safely, should we want to. */
1469 gas_assert (opsfound
<= (int) ARRAY_SIZE (operands_backup
));
1470 for (i
= 0; i
< opsfound
; i
++)
1471 operands_backup
[i
] = the_ins
.operands
[i
];
1473 for (s
= opcode
->m_operands
, opP
= &operands_backup
[0];
1477 /* Warning: this switch is huge! */
1478 /* I've tried to organize the cases into this order:
1479 non-alpha first, then alpha by letter. Lower-case
1480 goes directly before uppercase counterpart. */
1481 /* Code with multiple case ...: gets sorted by the lowest
1482 case ... it belongs to. I hope this makes sense. */
1588 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1605 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1624 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1634 if (opP
->mode
!= IMMED
)
1636 else if (s
[1] == 'b'
1637 && ! isvar (&opP
->disp
)
1638 && (opP
->disp
.exp
.X_op
!= O_constant
1639 || ! isbyte (opP
->disp
.exp
.X_add_number
)))
1641 else if (s
[1] == 'B'
1642 && ! isvar (&opP
->disp
)
1643 && (opP
->disp
.exp
.X_op
!= O_constant
1644 || ! issbyte (opP
->disp
.exp
.X_add_number
)))
1646 else if (s
[1] == 'w'
1647 && ! isvar (&opP
->disp
)
1648 && (opP
->disp
.exp
.X_op
!= O_constant
1649 || ! isword (opP
->disp
.exp
.X_add_number
)))
1651 else if (s
[1] == 'W'
1652 && ! isvar (&opP
->disp
)
1653 && (opP
->disp
.exp
.X_op
!= O_constant
1654 || ! issword (opP
->disp
.exp
.X_add_number
)))
1660 if (opP
->mode
!= IMMED
)
1665 if (opP
->mode
== AREG
1666 || opP
->mode
== CONTROL
1667 || opP
->mode
== FPREG
1668 || opP
->mode
== IMMED
1669 || opP
->mode
== REGLST
1670 || (opP
->mode
!= ABSL
1672 || opP
->reg
== ZPC
)))
1677 if (opP
->mode
== CONTROL
1678 || opP
->mode
== FPREG
1679 || opP
->mode
== REGLST
1680 || opP
->mode
== IMMED
1681 || (opP
->mode
!= ABSL
1683 || opP
->reg
== ZPC
)))
1711 if (opP
->mode
== CONTROL
1712 || opP
->mode
== FPREG
1713 || opP
->mode
== REGLST
)
1718 if (opP
->mode
!= AINC
)
1723 if (opP
->mode
!= ADEC
)
1773 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
1794 case '~': /* For now! (JF FOO is this right?) */
1816 if (opP
->mode
!= CONTROL
1817 || (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1822 if (opP
->mode
!= AREG
)
1827 if (opP
->mode
!= AINDR
)
1832 if (opP
->mode
!= AINDR
&& opP
->mode
!= AINC
&& opP
->mode
!= ADEC
1833 && (opP
->mode
!= DISP
1835 || opP
->reg
> ADDR7
))
1840 if (opP
->mode
!= ABSL
1842 && strncmp (instring
, "jbsr", 4) == 0))
1865 if (opP
->mode
!= CONTROL
|| opP
->reg
!= CCR
)
1870 if (opP
->mode
!= DISP
1872 || opP
->reg
> ADDR7
)
1877 if (opP
->mode
!= DREG
)
1882 if (opP
->reg
!= ACC
)
1887 if (opP
->reg
!= ACC
&& opP
->reg
!= ACC1
1888 && opP
->reg
!= ACC2
&& opP
->reg
!= ACC3
)
1893 if (opP
->mode
!= FPREG
)
1898 if (opP
->reg
!= MACSR
)
1903 if (opP
->reg
!= ACCEXT01
&& opP
->reg
!= ACCEXT23
)
1908 if (opP
->reg
!= MASK
)
1913 if (opP
->mode
!= CONTROL
1920 if (opP
->mode
!= LSH
&& opP
->mode
!= RSH
)
1925 if (opP
->mode
!= CONTROL
1927 || opP
->reg
> last_movec_reg
1932 const enum m68k_register
*rp
;
1934 for (rp
= control_regs
; *rp
; rp
++)
1936 if (*rp
== opP
->reg
)
1938 /* In most CPUs RAMBAR refers to control reg
1939 c05 (RAMBAR1), but a few CPUs have it
1940 refer to c04 (RAMBAR0). */
1941 else if (*rp
== RAMBAR_ALT
&& opP
->reg
== RAMBAR
)
1943 opP
->reg
= RAMBAR_ALT
;
1953 if (opP
->mode
!= IMMED
)
1959 if (opP
->mode
== DREG
1960 || opP
->mode
== AREG
1961 || opP
->mode
== FPREG
)
1970 opP
->mask
= 1 << (opP
->reg
- DATA0
);
1973 opP
->mask
= 1 << (opP
->reg
- ADDR0
+ 8);
1976 opP
->mask
= 1 << (opP
->reg
- FP0
+ 16);
1984 else if (opP
->mode
== CONTROL
)
1993 opP
->mask
= 1 << 24;
1996 opP
->mask
= 1 << 25;
1999 opP
->mask
= 1 << 26;
2008 else if (opP
->mode
!= REGLST
)
2010 else if (s
[1] == '8' && (opP
->mask
& 0x0ffffff) != 0)
2012 else if (s
[1] == '3' && (opP
->mask
& 0x7000000) != 0)
2017 if (opP
->mode
!= IMMED
)
2019 else if (opP
->disp
.exp
.X_op
!= O_constant
2020 || ! issbyte (opP
->disp
.exp
.X_add_number
))
2022 else if (! m68k_quick
2023 && instring
[3] != 'q'
2024 && instring
[4] != 'q')
2029 if (opP
->mode
!= DREG
2030 && opP
->mode
!= IMMED
2031 && opP
->mode
!= ABSL
)
2036 if (opP
->mode
!= IMMED
)
2038 else if (opP
->disp
.exp
.X_op
!= O_constant
2039 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
2041 else if (! m68k_quick
2042 && (strncmp (instring
, "add", 3) == 0
2043 || strncmp (instring
, "sub", 3) == 0)
2044 && instring
[3] != 'q')
2049 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
2054 if (opP
->mode
!= AINDR
2055 && (opP
->mode
!= BASE
2057 && opP
->reg
!= ZADDR0
)
2058 || opP
->disp
.exp
.X_op
!= O_absent
2059 || ((opP
->index
.reg
< DATA0
2060 || opP
->index
.reg
> DATA7
)
2061 && (opP
->index
.reg
< ADDR0
2062 || opP
->index
.reg
> ADDR7
))
2063 || opP
->index
.size
!= SIZE_UNSPEC
2064 || opP
->index
.scale
!= 1))
2069 if (opP
->mode
!= CONTROL
2070 || ! (opP
->reg
== FPI
2072 || opP
->reg
== FPC
))
2077 if (opP
->mode
!= CONTROL
|| opP
->reg
!= SR
)
2082 if (opP
->mode
!= IMMED
)
2084 else if (opP
->disp
.exp
.X_op
!= O_constant
2085 || TRUNC (opP
->disp
.exp
.X_add_number
) > 7)
2090 if (opP
->mode
!= CONTROL
|| opP
->reg
!= USP
)
2095 if (opP
->mode
!= IMMED
)
2097 else if (opP
->disp
.exp
.X_op
!= O_constant
2098 || (TRUNC (opP
->disp
.exp
.X_add_number
) != 0xffffffff
2099 && TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 6))
2104 if (opP
->mode
!= IMMED
)
2106 else if (opP
->disp
.exp
.X_op
!= O_constant
2107 || TRUNC (opP
->disp
.exp
.X_add_number
) - 1 > 7)
2112 if (opP
->mode
!= IMMED
)
2114 else if (opP
->disp
.exp
.X_op
!= O_constant
2115 || TRUNC (opP
->disp
.exp
.X_add_number
) > 511)
2119 /* JF these are out of order. We could put them
2120 in order if we were willing to put up with
2121 bunches of #ifdef m68851s in the code.
2123 Don't forget that you need these operands
2124 to use 68030 MMU instructions. */
2126 /* Memory addressing mode used by pflushr. */
2128 if (opP
->mode
== CONTROL
2129 || opP
->mode
== FPREG
2130 || opP
->mode
== DREG
2131 || opP
->mode
== AREG
2132 || opP
->mode
== REGLST
)
2134 /* We should accept immediate operands, but they
2135 supposedly have to be quad word, and we don't
2136 handle that. I would like to see what a Motorola
2137 assembler does before doing something here. */
2138 if (opP
->mode
== IMMED
)
2143 if (opP
->mode
!= CONTROL
2144 || (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
2149 if (opP
->mode
!= CONTROL
|| opP
->reg
!= TC
)
2154 if (opP
->mode
!= CONTROL
|| opP
->reg
!= AC
)
2159 if (opP
->mode
!= CONTROL
2162 && opP
->reg
!= SCC
))
2167 if (opP
->mode
!= CONTROL
2173 if (opP
->mode
!= CONTROL
2176 && opP
->reg
!= CRP
))
2200 if (opP
->mode
!= CONTROL
2201 || (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7)
2202 && !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
2207 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PSR
)
2212 if (opP
->mode
!= CONTROL
|| opP
->reg
!= PCSR
)
2217 if (opP
->mode
!= CONTROL
2226 if (opP
->mode
!= ABSL
)
2231 if (opP
->reg
< DATA0L
|| opP
->reg
> ADDR7U
)
2233 /* FIXME: kludge instead of fixing parser:
2234 upper/lower registers are *not* CONTROL
2235 registers, but ordinary ones. */
2236 if ((opP
->reg
>= DATA0L
&& opP
->reg
<= DATA7L
)
2237 || (opP
->reg
>= DATA0U
&& opP
->reg
<= DATA7U
))
2244 if (!(opP
->mode
== AINDR
2245 || (opP
->mode
== DISP
2246 && !(opP
->reg
== PC
|| opP
->reg
== ZPC
))))
2251 if (!(opP
->mode
== AINDR
|| opP
->mode
== DISP
))
2263 /* Since we have found the correct instruction, copy
2264 in the modifications that we may have made. */
2266 for (i
= 0; i
< opsfound
; i
++)
2267 the_ins
.operands
[i
] = operands_backup
[i
];
2273 opcode
= opcode
->m_next
;
2278 && !(ok_arch
& current_architecture
))
2280 const struct m68k_cpu
*cpu
;
2283 char *buf
= XNEWVEC (char, space
+ 1);
2287 the_ins
.error
= buf
;
2288 /* Make sure there's a NUL at the end of the buffer -- strncpy
2289 won't write one when it runs out of buffer. */
2291 #define APPEND(STRING) \
2292 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2294 APPEND (_("invalid instruction for this architecture; needs "));
2298 APPEND ("ColdFire ISA_A");
2301 APPEND ("ColdFire ");
2302 APPEND (_("hardware divide"));
2305 APPEND ("ColdFire ISA_A+");
2308 APPEND ("ColdFire ISA_B");
2311 APPEND ("ColdFire ISA_C");
2314 APPEND ("ColdFire fpu");
2317 APPEND ("M68K fpu");
2320 APPEND ("M68K mmu");
2324 APPEND (_("or higher"));
2328 APPEND (_("or higher"));
2332 APPEND (_("or higher"));
2340 for (cpu
= m68k_cpus
; cpu
->name
; cpu
++)
2341 if (!cpu
->alias
&& (cpu
->arch
& ok_arch
))
2343 const struct m68k_cpu
*alias
;
2344 int seen_master
= 0;
2350 for (alias
= cpu
; alias
!= m68k_cpus
; alias
--)
2351 if (alias
[-1].alias
>= 0)
2353 for (; !seen_master
|| alias
->alias
> 0; alias
++)
2363 APPEND (alias
->name
);
2376 /* We ran out of space, so replace the end of the list
2381 strcpy (buf
, " ...");
2385 the_ins
.error
= _("operands mismatch");
2392 /* Now assemble it. */
2393 the_ins
.args
= opcode
->m_operands
;
2394 the_ins
.numargs
= opcode
->m_opnum
;
2395 the_ins
.numo
= opcode
->m_codenum
;
2396 the_ins
.opcode
[0] = getone (opcode
);
2397 the_ins
.opcode
[1] = gettwo (opcode
);
2399 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2404 /* This switch is a doozy.
2405 Watch the first step; it's a big one! */
2438 tmpreg
= 0x3c; /* 7.4 */
2439 if (strchr ("bwl", s
[1]))
2440 nextword
= get_num (&opP
->disp
, 90);
2442 nextword
= get_num (&opP
->disp
, 0);
2443 if (isvar (&opP
->disp
))
2444 add_fix (s
[1], &opP
->disp
, 0, 0);
2448 if (!isbyte (nextword
))
2449 opP
->error
= _("operand out of range");
2454 if (!isword (nextword
))
2455 opP
->error
= _("operand out of range");
2460 if (!issword (nextword
))
2461 opP
->error
= _("operand out of range");
2466 addword (nextword
>> 16);
2493 /* We gotta put out some float. */
2494 if (op (&opP
->disp
) != O_big
)
2499 /* Can other cases happen here? */
2500 if (op (&opP
->disp
) != O_constant
)
2503 val
= (valueT
) offs (&opP
->disp
);
2507 generic_bignum
[gencnt
] = (LITTLENUM_TYPE
) val
;
2508 val
>>= LITTLENUM_NUMBER_OF_BITS
;
2512 offs (&opP
->disp
) = gencnt
;
2514 if (offs (&opP
->disp
) > 0)
2516 if (offs (&opP
->disp
) > baseo
)
2518 as_warn (_("Bignum too big for %c format; truncated"),
2520 offs (&opP
->disp
) = baseo
;
2522 baseo
-= offs (&opP
->disp
);
2525 for (wordp
= generic_bignum
+ offs (&opP
->disp
) - 1;
2526 offs (&opP
->disp
)--;
2531 gen_to_words (words
, baseo
, (long) outro
);
2532 for (wordp
= words
; baseo
--; wordp
++)
2536 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2539 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2542 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2545 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2548 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2552 nextword
= get_num (&opP
->disp
, 90);
2554 /* Convert mode 5 addressing with a zero offset into
2555 mode 2 addressing to reduce the instruction size by a
2557 if (! isvar (&opP
->disp
)
2559 && (opP
->disp
.size
== SIZE_UNSPEC
)
2560 && (opP
->reg
>= ADDR0
)
2561 && (opP
->reg
<= ADDR7
))
2563 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2568 && ! isvar (&opP
->disp
)
2571 opP
->disp
.exp
.X_op
= O_symbol
;
2572 opP
->disp
.exp
.X_add_symbol
=
2573 section_symbol (absolute_section
);
2576 /* Force into index mode. Hope this works. */
2578 /* We do the first bit for 32-bit displacements, and the
2579 second bit for 16 bit ones. It is possible that we
2580 should make the default be WORD instead of LONG, but
2581 I think that'd break GCC, so we put up with a little
2582 inefficiency for the sake of working output. */
2584 if (!issword (nextword
)
2585 || (isvar (&opP
->disp
)
2586 && ((opP
->disp
.size
== SIZE_UNSPEC
2587 && flag_short_refs
== 0
2588 && cpu_of_arch (current_architecture
) >= m68020
2589 && ! arch_coldfire_p (current_architecture
))
2590 || opP
->disp
.size
== SIZE_LONG
)))
2592 if (cpu_of_arch (current_architecture
) < m68020
2593 || arch_coldfire_p (current_architecture
))
2595 _("displacement too large for this architecture; needs 68020 or higher");
2597 tmpreg
= 0x3B; /* 7.3 */
2599 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2600 if (isvar (&opP
->disp
))
2604 if (opP
->disp
.size
== SIZE_LONG
2605 /* If the displacement needs pic
2606 relocation it cannot be relaxed. */
2607 || opP
->disp
.pic_reloc
!= pic_none
)
2610 add_fix ('l', &opP
->disp
, 1, 2);
2614 add_frag (adds (&opP
->disp
),
2615 SEXT (offs (&opP
->disp
)),
2616 TAB (PCREL1632
, SZ_UNDEF
));
2623 add_fix ('l', &opP
->disp
, 0, 0);
2628 addword (nextword
>> 16);
2633 tmpreg
= 0x3A; /* 7.2 */
2635 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2637 if (isvar (&opP
->disp
))
2641 add_fix ('w', &opP
->disp
, 1, 0);
2644 add_fix ('w', &opP
->disp
, 0, 0);
2654 baseo
= get_num (&opP
->disp
, 90);
2655 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2656 outro
= get_num (&opP
->odisp
, 90);
2657 /* Figure out the `addressing mode'.
2658 Also turn on the BASE_DISABLE bit, if needed. */
2659 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2661 tmpreg
= 0x3b; /* 7.3 */
2662 if (opP
->reg
== ZPC
)
2665 else if (opP
->reg
== 0)
2668 tmpreg
= 0x30; /* 6.garbage */
2670 else if (opP
->reg
>= ZADDR0
&& opP
->reg
<= ZADDR7
)
2673 tmpreg
= 0x30 + opP
->reg
- ZADDR0
;
2676 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2678 siz1
= opP
->disp
.size
;
2679 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2680 siz2
= opP
->odisp
.size
;
2684 /* Index register stuff. */
2685 if (opP
->index
.reg
!= 0
2686 && opP
->index
.reg
>= DATA
2687 && opP
->index
.reg
<= ADDR7
)
2689 nextword
|= (opP
->index
.reg
- DATA
) << 12;
2691 if (opP
->index
.size
== SIZE_LONG
2692 || (opP
->index
.size
== SIZE_UNSPEC
2693 && m68k_index_width_default
== SIZE_LONG
))
2696 if ((opP
->index
.scale
!= 1
2697 && cpu_of_arch (current_architecture
) < m68020
)
2698 || (opP
->index
.scale
== 8
2699 && (arch_coldfire_p (current_architecture
)
2700 && !arch_coldfire_fpu (current_architecture
))))
2703 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2706 if (arch_coldfire_p (current_architecture
)
2707 && opP
->index
.size
== SIZE_WORD
)
2708 opP
->error
= _("invalid index size for coldfire");
2710 switch (opP
->index
.scale
)
2727 GET US OUT OF HERE! */
2729 /* Must be INDEX, with an index register. Address
2730 register cannot be ZERO-PC, and either :b was
2731 forced, or we know it will fit. For a 68000 or
2732 68010, force this mode anyways, because the
2733 larger modes aren't supported. */
2734 if (opP
->mode
== BASE
2735 && ((opP
->reg
>= ADDR0
2736 && opP
->reg
<= ADDR7
)
2739 if (siz1
== SIZE_BYTE
2740 || cpu_of_arch (current_architecture
) < m68020
2741 || arch_coldfire_p (current_architecture
)
2742 || (siz1
== SIZE_UNSPEC
2743 && ! isvar (&opP
->disp
)
2744 && issbyte (baseo
)))
2746 nextword
+= baseo
& 0xff;
2748 if (isvar (&opP
->disp
))
2750 /* Do a byte relocation. If it doesn't
2751 fit (possible on m68000) let the
2752 fixup processing complain later. */
2754 add_fix ('B', &opP
->disp
, 1, 1);
2756 add_fix ('B', &opP
->disp
, 0, 0);
2758 else if (siz1
!= SIZE_BYTE
)
2760 if (siz1
!= SIZE_UNSPEC
)
2761 as_warn (_("Forcing byte displacement"));
2762 if (! issbyte (baseo
))
2763 opP
->error
= _("byte displacement out of range");
2768 else if (siz1
== SIZE_UNSPEC
2770 && isvar (&opP
->disp
)
2771 && subs (&opP
->disp
) == NULL
2772 /* If the displacement needs pic
2773 relocation it cannot be relaxed. */
2774 && opP
->disp
.pic_reloc
== pic_none
)
2776 /* The code in md_convert_frag_1 needs to be
2777 able to adjust nextword. Call frag_grow
2778 to ensure that we have enough space in
2779 the frag obstack to make all the bytes
2782 nextword
+= baseo
& 0xff;
2784 add_frag (adds (&opP
->disp
),
2785 SEXT (offs (&opP
->disp
)),
2786 TAB (PCINDEX
, SZ_UNDEF
));
2794 nextword
|= 0x40; /* No index reg. */
2795 if (opP
->index
.reg
>= ZDATA0
2796 && opP
->index
.reg
<= ZDATA7
)
2797 nextword
|= (opP
->index
.reg
- ZDATA0
) << 12;
2798 else if (opP
->index
.reg
>= ZADDR0
2799 && opP
->index
.reg
<= ZADDR7
)
2800 nextword
|= (opP
->index
.reg
- ZADDR0
+ 8) << 12;
2803 /* It isn't simple. */
2805 if (cpu_of_arch (current_architecture
) < m68020
2806 || arch_coldfire_p (current_architecture
))
2808 _("invalid operand mode for this architecture; needs 68020 or higher");
2811 /* If the guy specified a width, we assume that it is
2812 wide enough. Maybe it isn't. If so, we lose. */
2816 if (isvar (&opP
->disp
)
2818 : ! issword (baseo
))
2823 else if (! isvar (&opP
->disp
) && baseo
== 0)
2832 as_warn (_(":b not permitted; defaulting to :w"));
2842 /* Figure out inner displacement stuff. */
2843 if (opP
->mode
== POST
|| opP
->mode
== PRE
)
2845 if (cpu_of_arch (current_architecture
) & cpu32
)
2846 opP
->error
= _("invalid operand mode for this architecture; needs 68020 or higher");
2850 if (isvar (&opP
->odisp
)
2852 : ! issword (outro
))
2857 else if (! isvar (&opP
->odisp
) && outro
== 0)
2866 as_warn (_(":b not permitted; defaulting to :w"));
2875 if (opP
->mode
== POST
2876 && (nextword
& 0x40) == 0)
2881 if (siz1
!= SIZE_UNSPEC
&& isvar (&opP
->disp
))
2883 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2884 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 1, 2);
2886 add_fix (siz1
== SIZE_LONG
? 'l' : 'w', &opP
->disp
, 0, 0);
2888 if (siz1
== SIZE_LONG
)
2889 addword (baseo
>> 16);
2890 if (siz1
!= SIZE_UNSPEC
)
2893 if (siz2
!= SIZE_UNSPEC
&& isvar (&opP
->odisp
))
2894 add_fix (siz2
== SIZE_LONG
? 'l' : 'w', &opP
->odisp
, 0, 0);
2895 if (siz2
== SIZE_LONG
)
2896 addword (outro
>> 16);
2897 if (siz2
!= SIZE_UNSPEC
)
2903 nextword
= get_num (&opP
->disp
, 90);
2904 switch (opP
->disp
.size
)
2909 if (!isvar (&opP
->disp
) && issword (offs (&opP
->disp
)))
2911 tmpreg
= 0x38; /* 7.0 */
2915 if (isvar (&opP
->disp
)
2916 && !subs (&opP
->disp
)
2917 && adds (&opP
->disp
)
2918 /* If the displacement needs pic relocation it
2919 cannot be relaxed. */
2920 && opP
->disp
.pic_reloc
== pic_none
2922 && !strchr ("~%&$?", s
[0]))
2924 tmpreg
= 0x3A; /* 7.2 */
2925 add_frag (adds (&opP
->disp
),
2926 SEXT (offs (&opP
->disp
)),
2927 TAB (ABSTOPCREL
, SZ_UNDEF
));
2932 if (isvar (&opP
->disp
))
2933 add_fix ('l', &opP
->disp
, 0, 0);
2935 tmpreg
= 0x39;/* 7.1 mode */
2936 addword (nextword
>> 16);
2941 as_bad (_("unsupported byte value; use a different suffix"));
2945 if (isvar (&opP
->disp
))
2946 add_fix ('w', &opP
->disp
, 0, 0);
2948 tmpreg
= 0x38;/* 7.0 mode */
2956 as_bad (_("unknown/incorrect operand"));
2960 /* If s[0] is '4', then this is for the mac instructions
2961 that can have a trailing_ampersand set. If so, set 0x100
2962 bit on tmpreg so install_gen_operand can check for it and
2963 set the appropriate bit (word2, bit 5). */
2966 if (opP
->trailing_ampersand
)
2969 install_gen_operand (s
[1], tmpreg
);
2975 { /* JF: I hate floating point! */
2990 tmpreg
= get_num (&opP
->disp
, tmpreg
);
2991 if (isvar (&opP
->disp
))
2992 add_fix (s
[1], &opP
->disp
, 0, 0);
2995 case 'b': /* Danger: These do no check for
2996 certain types of overflow.
2998 if (!isbyte (tmpreg
))
2999 opP
->error
= _("out of range");
3000 insop (tmpreg
, opcode
);
3001 if (isvar (&opP
->disp
))
3002 the_ins
.reloc
[the_ins
.nrel
- 1].n
=
3003 (opcode
->m_codenum
) * 2 + 1;
3006 if (!issbyte (tmpreg
))
3007 opP
->error
= _("out of range");
3008 the_ins
.opcode
[the_ins
.numo
- 1] |= tmpreg
& 0xff;
3009 if (isvar (&opP
->disp
))
3010 the_ins
.reloc
[the_ins
.nrel
- 1].n
= opcode
->m_codenum
* 2 - 1;
3013 if (!isword (tmpreg
))
3014 opP
->error
= _("out of range");
3015 insop (tmpreg
, opcode
);
3016 if (isvar (&opP
->disp
))
3017 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3020 if (!issword (tmpreg
))
3021 opP
->error
= _("out of range");
3022 insop (tmpreg
, opcode
);
3023 if (isvar (&opP
->disp
))
3024 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3027 /* Because of the way insop works, we put these two out
3029 insop (tmpreg
, opcode
);
3030 insop (tmpreg
>> 16, opcode
);
3031 if (isvar (&opP
->disp
))
3032 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
3040 install_operand (s
[1], tmpreg
);
3051 install_operand (s
[1], opP
->reg
- ADDR
);
3055 tmpreg
= get_num (&opP
->disp
, 90);
3060 add_fix ('B', &opP
->disp
, 1, -1);
3063 add_fix ('w', &opP
->disp
, 1, 0);
3068 the_ins
.opcode
[0] |= 0xff;
3069 add_fix ('l', &opP
->disp
, 1, 0);
3073 case 'g': /* Conditional branch */
3074 have_disp
= HAVE_LONG_CALL (current_architecture
);
3077 case 'b': /* Unconditional branch */
3078 have_disp
= HAVE_LONG_BRANCH (current_architecture
);
3079 use_pl
= LONG_BRANCH_VIA_COND (current_architecture
);
3082 case 's': /* Unconditional subroutine */
3083 have_disp
= HAVE_LONG_CALL (current_architecture
);
3086 if (subs (&opP
->disp
) /* We can't relax it. */
3087 /* If the displacement needs pic relocation it cannot be
3089 || opP
->disp
.pic_reloc
!= pic_none
)
3092 as_warn (_("Can't use long branches on this architecture"));
3096 /* This could either be a symbol, or an absolute
3097 address. If it's an absolute address, turn it into
3098 an absolute jump right here and keep it out of the
3100 if (adds (&opP
->disp
) == 0)
3102 if (the_ins
.opcode
[0] == 0x6000) /* jbra */
3103 the_ins
.opcode
[0] = 0x4EF9;
3104 else if (the_ins
.opcode
[0] == 0x6100) /* jbsr */
3105 the_ins
.opcode
[0] = 0x4EB9;
3108 the_ins
.opcode
[0] ^= 0x0100;
3109 the_ins
.opcode
[0] |= 0x0006;
3112 add_fix ('l', &opP
->disp
, 0, 0);
3118 /* Now we know it's going into the relaxer. Now figure
3119 out which mode. We try in this order of preference:
3120 long branch, absolute jump, byte/word branches only. */
3122 add_frag (adds (&opP
->disp
),
3123 SEXT (offs (&opP
->disp
)),
3124 TAB (BRANCHBWL
, SZ_UNDEF
));
3125 else if (! flag_keep_pcrel
)
3127 if ((the_ins
.opcode
[0] == 0x6000)
3128 || (the_ins
.opcode
[0] == 0x6100))
3129 add_frag (adds (&opP
->disp
),
3130 SEXT (offs (&opP
->disp
)),
3131 TAB (BRABSJUNC
, SZ_UNDEF
));
3133 add_frag (adds (&opP
->disp
),
3134 SEXT (offs (&opP
->disp
)),
3135 TAB (BRABSJCOND
, SZ_UNDEF
));
3138 add_frag (adds (&opP
->disp
),
3139 SEXT (offs (&opP
->disp
)),
3140 (use_pl
? TAB (BRANCHBWPL
, SZ_UNDEF
)
3141 : TAB (BRANCHBW
, SZ_UNDEF
)));
3144 if (isvar (&opP
->disp
))
3146 /* Check for DBcc instructions. We can relax them,
3147 but only if we have long branches and/or absolute
3149 if (((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
3150 && (HAVE_LONG_BRANCH (current_architecture
)
3151 || ! flag_keep_pcrel
))
3153 if (HAVE_LONG_BRANCH (current_architecture
))
3154 add_frag (adds (&opP
->disp
),
3155 SEXT (offs (&opP
->disp
)),
3156 TAB (DBCCLBR
, SZ_UNDEF
));
3158 add_frag (adds (&opP
->disp
),
3159 SEXT (offs (&opP
->disp
)),
3160 TAB (DBCCABSJ
, SZ_UNDEF
));
3163 add_fix ('w', &opP
->disp
, 1, 0);
3167 case 'C': /* Fixed size LONG coproc branches. */
3168 add_fix ('l', &opP
->disp
, 1, 0);
3172 case 'c': /* Var size Coprocesssor branches. */
3173 if (subs (&opP
->disp
) || (adds (&opP
->disp
) == 0))
3175 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
3176 add_fix ('l', &opP
->disp
, 1, 0);
3181 add_frag (adds (&opP
->disp
),
3182 SEXT (offs (&opP
->disp
)),
3183 TAB (FBRANCH
, SZ_UNDEF
));
3190 case 'C': /* Ignore it. */
3193 case 'd': /* JF this is a kludge. */
3194 install_operand ('s', opP
->reg
- ADDR
);
3195 tmpreg
= get_num (&opP
->disp
, 90);
3196 if (!issword (tmpreg
))
3198 as_warn (_("Expression out of range, using 0"));
3205 install_operand (s
[1], opP
->reg
- DATA
);
3208 case 'e': /* EMAC ACCx, reg/reg. */
3209 install_operand (s
[1], opP
->reg
- ACC
);
3212 case 'E': /* Ignore it. */
3216 install_operand (s
[1], opP
->reg
- FP0
);
3219 case 'g': /* EMAC ACCEXTx. */
3220 install_operand (s
[1], opP
->reg
- ACCEXT01
);
3223 case 'G': /* Ignore it. */
3228 tmpreg
= opP
->reg
- COP0
;
3229 install_operand (s
[1], tmpreg
);
3232 case 'i': /* MAC/EMAC scale factor. */
3233 install_operand (s
[1], opP
->mode
== LSH
? 0x1 : 0x3);
3236 case 'J': /* JF foo. */
3279 tmpreg
= 0x00c + (opP
->reg
- ACR4
);
3386 install_operand (s
[1], tmpreg
);
3390 tmpreg
= get_num (&opP
->disp
, 55);
3391 install_operand (s
[1], tmpreg
& 0x7f);
3398 if (tmpreg
& 0x7FF0000)
3399 as_bad (_("Floating point register in register list"));
3400 insop (reverse_16_bits (tmpreg
), opcode
);
3404 if (tmpreg
& 0x700FFFF)
3405 as_bad (_("Wrong register in floating-point reglist"));
3406 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
3414 if (tmpreg
& 0x7FF0000)
3415 as_bad (_("Floating point register in register list"));
3416 insop (tmpreg
, opcode
);
3418 else if (s
[1] == '8')
3420 if (tmpreg
& 0x0FFFFFF)
3421 as_bad (_("incorrect register in reglist"));
3422 install_operand (s
[1], tmpreg
>> 24);
3426 if (tmpreg
& 0x700FFFF)
3427 as_bad (_("wrong register in floating-point reglist"));
3429 install_operand (s
[1], tmpreg
>> 16);
3434 install_operand (s
[1], get_num (&opP
->disp
, 60));
3438 tmpreg
= ((opP
->mode
== DREG
)
3439 ? 0x20 + (int) (opP
->reg
- DATA
)
3440 : (get_num (&opP
->disp
, 40) & 0x1F));
3441 install_operand (s
[1], tmpreg
);
3445 tmpreg
= get_num (&opP
->disp
, 10);
3448 install_operand (s
[1], tmpreg
);
3452 /* This depends on the fact that ADDR registers are eight
3453 more than their corresponding DATA regs, so the result
3454 will have the ADDR_REG bit set. */
3455 install_operand (s
[1], opP
->reg
- DATA
);
3459 if (opP
->mode
== AINDR
)
3460 install_operand (s
[1], opP
->reg
- DATA
);
3462 install_operand (s
[1], opP
->index
.reg
- DATA
);
3466 if (opP
->reg
== FPI
)
3468 else if (opP
->reg
== FPS
)
3470 else if (opP
->reg
== FPC
)
3474 install_operand (s
[1], tmpreg
);
3477 case 'S': /* Ignore it. */
3481 install_operand (s
[1], get_num (&opP
->disp
, 30));
3484 case 'U': /* Ignore it. */
3503 as_fatal (_("failed sanity check"));
3504 } /* switch on cache token. */
3505 install_operand (s
[1], tmpreg
);
3508 /* JF: These are out of order, I fear. */
3521 install_operand (s
[1], tmpreg
);
3547 install_operand (s
[1], tmpreg
);
3551 if (opP
->reg
== VAL
)
3570 install_operand (s
[1], tmpreg
);
3584 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3595 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3601 install_operand (s
[1], tmpreg
);
3604 know (opP
->reg
== PSR
);
3607 know (opP
->reg
== PCSR
);
3622 install_operand (s
[1], tmpreg
);
3625 tmpreg
= get_num (&opP
->disp
, 20);
3626 install_operand (s
[1], tmpreg
);
3628 case '_': /* used only for move16 absolute 32-bit address. */
3629 if (isvar (&opP
->disp
))
3630 add_fix ('l', &opP
->disp
, 0, 0);
3631 tmpreg
= get_num (&opP
->disp
, 90);
3632 addword (tmpreg
>> 16);
3633 addword (tmpreg
& 0xFFFF);
3636 install_operand (s
[1], opP
->reg
- DATA0L
);
3637 opP
->reg
-= (DATA0L
);
3638 opP
->reg
&= 0x0F; /* remove upper/lower bit. */
3641 tmpreg
= get_num (&opP
->disp
, 80);
3644 install_operand (s
[1], tmpreg
);
3647 tmpreg
= get_num (&opP
->disp
, 10);
3648 install_operand (s
[1], tmpreg
- 1);
3651 tmpreg
= get_num (&opP
->disp
, 65);
3652 install_operand (s
[1], tmpreg
);
3659 /* By the time when get here (FINALLY) the_ins contains the complete
3660 instruction, ready to be emitted. . . */
3664 reverse_16_bits (int in
)
3669 static int mask
[16] =
3671 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3672 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3674 for (n
= 0; n
< 16; n
++)
3677 out
|= mask
[15 - n
];
3680 } /* reverse_16_bits() */
3683 reverse_8_bits (int in
)
3688 static int mask
[8] =
3690 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3693 for (n
= 0; n
< 8; n
++)
3699 } /* reverse_8_bits() */
3701 /* Cause an extra frag to be generated here, inserting up to
3702 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3703 generated; its primary type is rs_machine_dependent.
3705 The TYPE parameter is also used by md_convert_frag_1 and
3706 md_estimate_size_before_relax. The appropriate type of fixup will
3707 be emitted by md_convert_frag_1.
3709 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3711 install_operand (int mode
, int val
)
3716 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge. */
3719 the_ins
.opcode
[0] |= val
<< 9;
3722 the_ins
.opcode
[1] |= val
<< 9;
3725 the_ins
.opcode
[1] |= val
<< 12;
3728 the_ins
.opcode
[1] |= val
<< 6;
3731 the_ins
.opcode
[1] |= val
;
3734 the_ins
.opcode
[2] |= val
<< 12;
3737 the_ins
.opcode
[2] |= val
<< 6;
3740 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3741 three words long! */
3743 the_ins
.opcode
[2] |= val
;
3746 the_ins
.opcode
[1] |= val
<< 7;
3749 the_ins
.opcode
[1] |= val
<< 10;
3753 the_ins
.opcode
[1] |= val
<< 5;
3758 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3761 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3764 the_ins
.opcode
[0] |= val
= 0xff;
3767 the_ins
.opcode
[0] |= val
<< 9;
3770 the_ins
.opcode
[1] |= val
;
3773 the_ins
.opcode
[1] |= val
;
3774 the_ins
.numo
++; /* What a hack. */
3777 the_ins
.opcode
[1] |= val
<< 4;
3785 the_ins
.opcode
[0] |= (val
<< 6);
3788 the_ins
.opcode
[1] = (val
>> 16);
3789 the_ins
.opcode
[2] = val
& 0xffff;
3792 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3793 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3794 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3796 case 'n': /* MAC/EMAC Rx on !load. */
3797 the_ins
.opcode
[0] |= ((val
& 0x8) << (6 - 3));
3798 the_ins
.opcode
[0] |= ((val
& 0x7) << 9);
3799 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3801 case 'o': /* MAC/EMAC Rx on load. */
3802 the_ins
.opcode
[1] |= val
<< 12;
3803 the_ins
.opcode
[1] |= ((val
& 0x10) << (7 - 4));
3805 case 'M': /* MAC/EMAC Ry on !load. */
3806 the_ins
.opcode
[0] |= (val
& 0xF);
3807 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3809 case 'N': /* MAC/EMAC Ry on load. */
3810 the_ins
.opcode
[1] |= (val
& 0xF);
3811 the_ins
.opcode
[1] |= ((val
& 0x10) << (6 - 4));
3814 the_ins
.opcode
[1] |= ((val
!= 1) << 10);
3817 the_ins
.opcode
[0] |= ((val
& 0x3) << 9);
3820 the_ins
.opcode
[0] |= ((val
& 0x3) << 0);
3822 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3823 the_ins
.opcode
[0] |= ((~val
& 0x1) << 7);
3824 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3826 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3827 the_ins
.opcode
[0] |= ((val
& 0x1) << 7);
3828 the_ins
.opcode
[1] |= ((val
& 0x2) << (4 - 1));
3831 the_ins
.opcode
[1] |= ((val
& 0x3) << 9);
3834 the_ins
.opcode
[0] |= (val
& 0x1) <<10;
3838 as_fatal (_("failed sanity check."));
3843 install_gen_operand (int mode
, int val
)
3847 case '/': /* Special for mask loads for mac/msac insns with
3848 possible mask; trailing_ampersand set in bit 8. */
3849 the_ins
.opcode
[0] |= (val
& 0x3f);
3850 the_ins
.opcode
[1] |= (((val
& 0x100) >> 8) << 5);
3853 the_ins
.opcode
[0] |= val
;
3856 /* This is a kludge!!! */
3857 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3866 the_ins
.opcode
[0] |= val
;
3868 /* more stuff goes here. */
3870 as_fatal (_("failed sanity check."));
3874 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3875 then deal with the bitfield hack. */
3878 crack_operand (char *str
, struct m68k_op
*opP
)
3890 for (parens
= 0; *str
&& (parens
> 0 || inquote
|| notend (str
)); str
++)
3896 else if (*str
== ')')
3900 opP
->error
= _("Extra )");
3906 if (flag_mri
&& *str
== '\'')
3907 inquote
= ! inquote
;
3909 if (!*str
&& parens
)
3911 opP
->error
= _("Missing )");
3916 if (m68k_ip_op (beg_str
, opP
) != 0)
3923 c
= *++str
; /* JF bitfield hack. */
3928 as_bad (_("Missing operand"));
3931 /* Detect MRI REG symbols and convert them to REGLSTs. */
3932 if (opP
->mode
== CONTROL
&& (int)opP
->reg
< 0)
3935 opP
->mask
= ~(int)opP
->reg
;
3942 /* This is the guts of the machine-dependent assembler. STR points to a
3943 machine dependent instruction. This function is supposed to emit
3944 the frags/bytes it assembles to.
3948 insert_reg (const char *regname
, int regnum
)
3953 #ifdef REGISTER_PREFIX
3954 if (!flag_reg_prefix_optional
)
3956 buf
[0] = REGISTER_PREFIX
;
3957 strcpy (buf
+ 1, regname
);
3962 symbol_table_insert (symbol_new (regname
, reg_section
,
3963 &zero_address_frag
, regnum
));
3965 for (i
= 0; regname
[i
]; i
++)
3966 buf
[i
] = TOUPPER (regname
[i
]);
3969 symbol_table_insert (symbol_new (buf
, reg_section
,
3970 &zero_address_frag
, regnum
));
3979 static const struct init_entry init_table
[] =
4039 { "accext01", ACCEXT01
},
4040 { "accext23", ACCEXT23
},
4044 /* Control registers. */
4045 { "sfc", SFC
}, /* Source Function Code. */
4047 { "dfc", DFC
}, /* Destination Function Code. */
4049 { "cacr", CACR
}, /* Cache Control Register. */
4050 { "caar", CAAR
}, /* Cache Address Register. */
4051 { "cpucr", CPUCR
}, /* CPU Control Register. */
4053 { "usp", USP
}, /* User Stack Pointer. */
4054 { "vbr", VBR
}, /* Vector Base Register. */
4055 { "msp", MSP
}, /* Master Stack Pointer. */
4056 { "isp", ISP
}, /* Interrupt Stack Pointer. */
4058 { "itt0", ITT0
}, /* Instruction Transparent Translation Reg 0. */
4059 { "itt1", ITT1
}, /* Instruction Transparent Translation Reg 1. */
4060 { "dtt0", DTT0
}, /* Data Transparent Translation Register 0. */
4061 { "dtt1", DTT1
}, /* Data Transparent Translation Register 1. */
4063 /* 68ec040 versions of same */
4064 { "iacr0", ITT0
}, /* Instruction Access Control Register 0. */
4065 { "iacr1", ITT1
}, /* Instruction Access Control Register 0. */
4066 { "dacr0", DTT0
}, /* Data Access Control Register 0. */
4067 { "dacr1", DTT1
}, /* Data Access Control Register 0. */
4069 /* Coldfire versions of same. The ColdFire programmer's reference
4070 manual indicated that the order is 2,3,0,1, but Ken Rose
4071 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4072 { "acr0", ACR0
}, /* Access Control Unit 0. */
4073 { "acr1", ACR1
}, /* Access Control Unit 1. */
4074 { "acr2", ACR2
}, /* Access Control Unit 2. */
4075 { "acr3", ACR3
}, /* Access Control Unit 3. */
4076 { "acr4", ACR4
}, /* Access Control Unit 4. */
4077 { "acr5", ACR5
}, /* Access Control Unit 5. */
4078 { "acr6", ACR6
}, /* Access Control Unit 6. */
4079 { "acr7", ACR7
}, /* Access Control Unit 7. */
4081 { "tc", TC
}, /* MMU Translation Control Register. */
4085 { "mmusr", MMUSR
}, /* MMU Status Register. */
4086 { "srp", SRP
}, /* User Root Pointer. */
4087 { "urp", URP
}, /* Supervisor Root Pointer. */
4090 { "mmubar", MMUBAR
},
4093 { "rombar", ROMBAR
}, /* ROM Base Address Register. */
4094 { "rambar0", RAMBAR0
}, /* ROM Base Address Register. */
4095 { "rambar1", RAMBAR1
}, /* ROM Base Address Register. */
4096 { "mbar", MBAR
}, /* Module Base Address Register. */
4098 { "mbar0", MBAR0
}, /* mcfv4e registers. */
4099 { "mbar1", MBAR1
}, /* mcfv4e registers. */
4100 { "rombar0", ROMBAR0
}, /* mcfv4e registers. */
4101 { "rombar1", ROMBAR1
}, /* mcfv4e registers. */
4102 { "mpcr", MPCR
}, /* mcfv4e registers. */
4103 { "edrambar", EDRAMBAR
}, /* mcfv4e registers. */
4104 { "secmbar", SECMBAR
}, /* mcfv4e registers. */
4105 { "asid", TC
}, /* mcfv4e registers. */
4106 { "mmubar", BUSCR
}, /* mcfv4e registers. */
4107 { "pcr1u0", PCR1U0
}, /* mcfv4e registers. */
4108 { "pcr1l0", PCR1L0
}, /* mcfv4e registers. */
4109 { "pcr2u0", PCR2U0
}, /* mcfv4e registers. */
4110 { "pcr2l0", PCR2L0
}, /* mcfv4e registers. */
4111 { "pcr3u0", PCR3U0
}, /* mcfv4e registers. */
4112 { "pcr3l0", PCR3L0
}, /* mcfv4e registers. */
4113 { "pcr1u1", PCR1U1
}, /* mcfv4e registers. */
4114 { "pcr1l1", PCR1L1
}, /* mcfv4e registers. */
4115 { "pcr2u1", PCR2U1
}, /* mcfv4e registers. */
4116 { "pcr2l1", PCR2L1
}, /* mcfv4e registers. */
4117 { "pcr3u1", PCR3U1
}, /* mcfv4e registers. */
4118 { "pcr3l1", PCR3L1
}, /* mcfv4e registers. */
4120 { "flashbar", FLASHBAR
}, /* mcf528x registers. */
4121 { "rambar", RAMBAR
}, /* mcf528x registers. */
4123 { "mbar2", MBAR2
}, /* mcf5249 registers. */
4125 { "rgpiobar", RGPIOBAR
}, /* mcf54418 registers. */
4127 { "cac", CAC
}, /* fido registers. */
4128 { "mbb", MBO
}, /* fido registers (obsolete). */
4129 { "mbo", MBO
}, /* fido registers. */
4130 /* End of control registers. */
4164 /* 68ec030 versions of same. */
4167 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4170 /* Suppressed data and address registers. */
4188 /* Upper and lower data and address registers, used by macw and msacw. */
4229 init_regtable (void)
4232 for (i
= 0; init_table
[i
].name
; i
++)
4233 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
4237 md_assemble (char *str
)
4244 int shorts_this_frag
;
4247 if (!selected_cpu
&& !selected_arch
)
4249 /* We've not selected an architecture yet. Set the default
4250 now. We do this lazily so that an initial .cpu or .arch directive
4252 if (!m68k_set_cpu (TARGET_CPU
, 1, 1))
4253 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU
);
4258 /* In MRI mode, the instruction and operands are separated by a
4259 space. Anything following the operands is a comment. The label
4260 has already been removed. */
4268 for (s
= str
; *s
!= '\0'; s
++)
4270 if ((*s
== ' ' || *s
== '\t') && ! inquote
)
4288 inquote
= ! inquote
;
4293 memset (&the_ins
, '\0', sizeof (the_ins
));
4298 for (n
= 0; n
< the_ins
.numargs
; n
++)
4299 if (the_ins
.operands
[n
].error
)
4301 er
= the_ins
.operands
[n
].error
;
4307 as_bad (_("%s -- statement `%s' ignored"), er
, str
);
4311 /* If there is a current label, record that it marks an instruction. */
4312 if (current_label
!= NULL
)
4314 current_label
->text
= 1;
4315 current_label
= NULL
;
4318 /* Tie dwarf2 debug info to the address at the start of the insn. */
4319 dwarf2_emit_insn (0);
4321 if (the_ins
.nfrag
== 0)
4323 /* No frag hacking involved; just put it out. */
4324 toP
= frag_more (2 * the_ins
.numo
);
4325 fromP
= &the_ins
.opcode
[0];
4326 for (m
= the_ins
.numo
; m
; --m
)
4328 md_number_to_chars (toP
, (long) (*fromP
), 2);
4332 /* Put out symbol-dependent info. */
4333 for (m
= 0; m
< the_ins
.nrel
; m
++)
4335 switch (the_ins
.reloc
[m
].wid
)
4354 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
4355 the_ins
.reloc
[m
].wid
);
4358 fixP
= fix_new_exp (frag_now
,
4359 ((toP
- frag_now
->fr_literal
)
4360 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4362 &the_ins
.reloc
[m
].exp
,
4363 the_ins
.reloc
[m
].pcrel
,
4364 get_reloc_code (n
, the_ins
.reloc
[m
].pcrel
,
4365 the_ins
.reloc
[m
].pic_reloc
));
4366 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4367 if (the_ins
.reloc
[m
].wid
== 'B')
4368 fixP
->fx_signed
= 1;
4373 /* There's some frag hacking. */
4375 /* Calculate the max frag size. */
4378 wid
= 2 * the_ins
.fragb
[0].fragoff
;
4379 for (n
= 1; n
< the_ins
.nfrag
; n
++)
4380 wid
+= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4381 /* frag_var part. */
4382 wid
+= FRAG_VAR_SIZE
;
4383 /* Make sure the whole insn fits in one chunk, in particular that
4384 the var part is attached, as we access one byte before the
4385 variable frag for byte branches. */
4389 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
4394 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
4396 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
4397 toP
= frag_more (wid
);
4399 shorts_this_frag
= 0;
4400 for (m
= wid
/ 2; m
; --m
)
4402 md_number_to_chars (toP
, (long) (*fromP
), 2);
4407 for (m
= 0; m
< the_ins
.nrel
; m
++)
4409 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
4411 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
4414 wid
= the_ins
.reloc
[m
].wid
;
4417 the_ins
.reloc
[m
].wid
= 0;
4418 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4420 fixP
= fix_new_exp (frag_now
,
4421 ((toP
- frag_now
->fr_literal
)
4422 - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
),
4424 &the_ins
.reloc
[m
].exp
,
4425 the_ins
.reloc
[m
].pcrel
,
4426 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4427 the_ins
.reloc
[m
].pic_reloc
));
4428 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4430 (void) frag_var (rs_machine_dependent
, FRAG_VAR_SIZE
, 0,
4431 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
4432 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
4434 gas_assert (the_ins
.nfrag
>= 1);
4435 n
= the_ins
.numo
- the_ins
.fragb
[the_ins
.nfrag
- 1].fragoff
;
4436 shorts_this_frag
= 0;
4439 toP
= frag_more (n
* 2);
4442 md_number_to_chars (toP
, (long) (*fromP
), 2);
4448 for (m
= 0; m
< the_ins
.nrel
; m
++)
4452 wid
= the_ins
.reloc
[m
].wid
;
4455 the_ins
.reloc
[m
].wid
= 0;
4456 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
4458 fixP
= fix_new_exp (frag_now
,
4459 ((the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
)
4460 - shorts_this_frag
* 2),
4462 &the_ins
.reloc
[m
].exp
,
4463 the_ins
.reloc
[m
].pcrel
,
4464 get_reloc_code (wid
, the_ins
.reloc
[m
].pcrel
,
4465 the_ins
.reloc
[m
].pic_reloc
));
4466 fixP
->fx_pcrel_adjust
= the_ins
.reloc
[m
].pcrel_fix
;
4470 /* Comparison function used by qsort to rank the opcode entries by name. */
4473 m68k_compare_opcode (const void * v1
, const void * v2
)
4475 struct m68k_opcode
* op1
, * op2
;
4481 op1
= *(struct m68k_opcode
**) v1
;
4482 op2
= *(struct m68k_opcode
**) v2
;
4484 /* Compare the two names. If different, return the comparison.
4485 If the same, return the order they are in the opcode table. */
4486 ret
= strcmp (op1
->name
, op2
->name
);
4497 const struct m68k_opcode
*ins
;
4498 struct m68k_incant
*hack
, *slak
;
4501 /* Set up hash tables with 68000 instructions.
4502 similar to what the vax assembler does. */
4503 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4504 a copy of it at runtime, adding in the information we want but isn't
4505 there. I think it'd be better to have an awk script hack the table
4506 at compile time. Or even just xstr the table and use it as-is. But
4507 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4512 flag_reg_prefix_optional
= 1;
4514 if (! m68k_rel32_from_cmdline
)
4518 /* First sort the opcode table into alphabetical order to separate
4519 the order that the assembler wants to see the opcodes from the
4520 order that the disassembler wants to see them. */
4521 m68k_sorted_opcodes
= XNEWVEC (const struct m68k_opcode
*, m68k_numopcodes
);
4523 for (i
= m68k_numopcodes
; i
--;)
4524 m68k_sorted_opcodes
[i
] = m68k_opcodes
+ i
;
4526 qsort (m68k_sorted_opcodes
, m68k_numopcodes
,
4527 sizeof (m68k_sorted_opcodes
[0]), m68k_compare_opcode
);
4529 op_hash
= str_htab_create ();
4531 obstack_begin (&robyn
, 4000);
4532 for (i
= 0; i
< m68k_numopcodes
; i
++)
4534 hack
= slak
= XOBNEW (&robyn
, struct m68k_incant
);
4537 ins
= m68k_sorted_opcodes
[i
];
4539 /* We must enter all insns into the table, because .arch and
4540 .cpu directives can change things. */
4541 slak
->m_operands
= ins
->args
;
4542 slak
->m_arch
= ins
->arch
;
4543 slak
->m_opcode
= ins
->opcode
;
4545 /* In most cases we can determine the number of opcode words
4546 by checking the second word of the mask. Unfortunately
4547 some instructions have 2 opcode words, but no fixed bits
4548 in the second word. A leading dot in the operands
4549 string also indicates 2 opcodes. */
4550 if (*slak
->m_operands
== '.')
4553 slak
->m_codenum
= 2;
4555 else if (ins
->match
& 0xffffL
)
4556 slak
->m_codenum
= 2;
4558 slak
->m_codenum
= 1;
4559 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
4561 if (i
+ 1 != m68k_numopcodes
4562 && !strcmp (ins
->name
, m68k_sorted_opcodes
[i
+ 1]->name
))
4564 slak
->m_next
= XOBNEW (&robyn
, struct m68k_incant
);
4569 slak
= slak
->m_next
;
4573 if (str_hash_insert (op_hash
, ins
->name
, hack
, 0) != NULL
)
4574 as_fatal (_("duplicate %s"), ins
->name
);
4577 for (i
= 0; i
< m68k_numaliases
; i
++)
4579 const char *name
= m68k_opcode_aliases
[i
].primary
;
4580 const char *alias
= m68k_opcode_aliases
[i
].alias
;
4581 void *val
= (void *) str_hash_find (op_hash
, name
);
4584 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4585 if (str_hash_insert (op_hash
, alias
, val
, 0) != NULL
)
4586 as_fatal (_("duplicate %s"), alias
);
4589 /* In MRI mode, all unsized branches are variable sized. Normally,
4590 they are word sized. */
4593 static struct m68k_opcode_alias mri_aliases
[] =
4614 i
< (int) (sizeof mri_aliases
/ sizeof mri_aliases
[0]);
4617 const char *name
= mri_aliases
[i
].primary
;
4618 const char *alias
= mri_aliases
[i
].alias
;
4619 void *val
= (void *) str_hash_find (op_hash
, name
);
4622 as_fatal (_("Internal Error: Can't find %s in hash table"), name
);
4623 str_hash_insert (op_hash
, alias
, val
, 1);
4627 for (i
= 0; i
< (int) sizeof (notend_table
); i
++)
4629 notend_table
[i
] = 0;
4630 alt_notend_table
[i
] = 0;
4633 notend_table
[','] = 1;
4634 notend_table
['{'] = 1;
4635 notend_table
['}'] = 1;
4636 alt_notend_table
['a'] = 1;
4637 alt_notend_table
['A'] = 1;
4638 alt_notend_table
['d'] = 1;
4639 alt_notend_table
['D'] = 1;
4640 alt_notend_table
['#'] = 1;
4641 alt_notend_table
['&'] = 1;
4642 alt_notend_table
['f'] = 1;
4643 alt_notend_table
['F'] = 1;
4644 #ifdef REGISTER_PREFIX
4645 alt_notend_table
[REGISTER_PREFIX
] = 1;
4648 /* We need to put '(' in alt_notend_table to handle
4649 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4650 alt_notend_table
['('] = 1;
4652 /* We need to put '@' in alt_notend_table to handle
4653 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4654 alt_notend_table
['@'] = 1;
4656 /* We need to put digits in alt_notend_table to handle
4657 bfextu %d0{24:1},%d0 */
4658 alt_notend_table
['0'] = 1;
4659 alt_notend_table
['1'] = 1;
4660 alt_notend_table
['2'] = 1;
4661 alt_notend_table
['3'] = 1;
4662 alt_notend_table
['4'] = 1;
4663 alt_notend_table
['5'] = 1;
4664 alt_notend_table
['6'] = 1;
4665 alt_notend_table
['7'] = 1;
4666 alt_notend_table
['8'] = 1;
4667 alt_notend_table
['9'] = 1;
4669 #ifndef MIT_SYNTAX_ONLY
4670 /* Insert pseudo ops, these have to go into the opcode table since
4671 gas expects pseudo ops to start with a dot. */
4675 while (mote_pseudo_table
[n
].poc_name
)
4677 hack
= XOBNEW (&robyn
, struct m68k_incant
);
4678 str_hash_insert (op_hash
,
4679 mote_pseudo_table
[n
].poc_name
, hack
, 0);
4680 hack
->m_operands
= 0;
4689 record_alignment (text_section
, 2);
4690 record_alignment (data_section
, 2);
4691 record_alignment (bss_section
, 2);
4695 /* This is called when a label is defined. */
4698 m68k_frob_label (symbolS
*sym
)
4700 struct label_line
*n
;
4702 n
= XNEW (struct label_line
);
4705 n
->file
= as_where (&n
->line
);
4710 dwarf2_emit_label (sym
);
4713 /* This is called when a value that is not an instruction is emitted. */
4716 m68k_flush_pending_output (void)
4718 current_label
= NULL
;
4721 /* This is called at the end of the assembly, when the final value of
4722 the label is known. We warn if this is a text symbol aligned at an
4726 m68k_frob_symbol (symbolS
*sym
)
4728 if (S_GET_SEGMENT (sym
) == reg_section
4729 && (int) S_GET_VALUE (sym
) < 0)
4731 S_SET_SEGMENT (sym
, absolute_section
);
4732 S_SET_VALUE (sym
, ~(int)S_GET_VALUE (sym
));
4734 else if ((S_GET_VALUE (sym
) & 1) != 0)
4736 struct label_line
*l
;
4738 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4740 if (l
->label
== sym
)
4743 as_warn_where (l
->file
, l
->line
,
4744 _("text label `%s' aligned to odd boundary"),
4752 /* This is called if we go in or out of MRI mode because of the .mri
4756 m68k_mri_mode_change (int on
)
4760 if (! flag_reg_prefix_optional
)
4762 flag_reg_prefix_optional
= 1;
4763 #ifdef REGISTER_PREFIX
4768 if (! m68k_rel32_from_cmdline
)
4773 if (! reg_prefix_optional_seen
)
4775 #ifdef REGISTER_PREFIX_OPTIONAL
4776 flag_reg_prefix_optional
= REGISTER_PREFIX_OPTIONAL
;
4778 flag_reg_prefix_optional
= 0;
4780 #ifdef REGISTER_PREFIX
4785 if (! m68k_rel32_from_cmdline
)
4791 md_atof (int type
, char *litP
, int *sizeP
)
4793 return ieee_md_atof (type
, litP
, sizeP
, true);
4797 md_number_to_chars (char *buf
, valueT val
, int n
)
4799 number_to_chars_bigendian (buf
, val
, n
);
4803 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
4805 offsetT val
= *valP
;
4806 addressT upper_limit
;
4807 offsetT lower_limit
;
4809 /* This is unnecessary but it convinces the native rs6000 compiler
4810 to generate the code we want. */
4811 char *buf
= fixP
->fx_frag
->fr_literal
;
4812 buf
+= fixP
->fx_where
;
4813 /* End ibm compiler workaround. */
4817 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_pcrel
== 0)
4822 memset (buf
, 0, fixP
->fx_size
);
4823 fixP
->fx_addnumber
= val
; /* Remember value for emit_reloc. */
4825 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4826 && !S_IS_DEFINED (fixP
->fx_addsy
)
4827 && !S_IS_WEAK (fixP
->fx_addsy
))
4828 S_SET_WEAK (fixP
->fx_addsy
);
4830 switch (fixP
->fx_r_type
)
4832 case BFD_RELOC_68K_TLS_GD32
:
4833 case BFD_RELOC_68K_TLS_GD16
:
4834 case BFD_RELOC_68K_TLS_GD8
:
4835 case BFD_RELOC_68K_TLS_LDM32
:
4836 case BFD_RELOC_68K_TLS_LDM16
:
4837 case BFD_RELOC_68K_TLS_LDM8
:
4838 case BFD_RELOC_68K_TLS_LDO32
:
4839 case BFD_RELOC_68K_TLS_LDO16
:
4840 case BFD_RELOC_68K_TLS_LDO8
:
4841 case BFD_RELOC_68K_TLS_IE32
:
4842 case BFD_RELOC_68K_TLS_IE16
:
4843 case BFD_RELOC_68K_TLS_IE8
:
4844 case BFD_RELOC_68K_TLS_LE32
:
4845 case BFD_RELOC_68K_TLS_LE16
:
4846 case BFD_RELOC_68K_TLS_LE8
:
4847 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
4857 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
4858 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
4861 switch (fixP
->fx_size
)
4863 /* The cast to offsetT below are necessary to make code
4864 correct for machines where ints are smaller than offsetT. */
4868 lower_limit
= - (offsetT
) 0x80;
4871 *buf
++ = (val
>> 8);
4873 upper_limit
= 0x7fff;
4874 lower_limit
= - (offsetT
) 0x8000;
4877 *buf
++ = (val
>> 24);
4878 *buf
++ = (val
>> 16);
4879 *buf
++ = (val
>> 8);
4881 upper_limit
= 0x7fffffff;
4882 lower_limit
= - (offsetT
) 0x7fffffff - 1; /* Avoid constant overflow. */
4885 BAD_CASE (fixP
->fx_size
);
4888 /* Fix up a negative reloc. */
4889 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_subsy
!= NULL
)
4891 fixP
->fx_addsy
= fixP
->fx_subsy
;
4892 fixP
->fx_subsy
= NULL
;
4896 /* For non-pc-relative values, it's conceivable we might get something
4897 like "0xff" for a byte field. So extend the upper part of the range
4898 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4899 so that we can do any range checking at all. */
4900 if (! fixP
->fx_pcrel
&& ! fixP
->fx_signed
)
4901 upper_limit
= upper_limit
* 2 + 1;
4903 if ((addressT
) val
> upper_limit
4904 && (val
> 0 || val
< lower_limit
))
4905 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4906 _("value %ld out of range"), (long)val
);
4908 /* A one byte PC-relative reloc means a short branch. We can't use
4909 a short branch with a value of 0 or -1, because those indicate
4910 different opcodes (branches with longer offsets). fixup_segment
4911 in write.c may have clobbered fx_pcrel, so we need to examine the
4914 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
4915 && fixP
->fx_size
== 1
4916 && (fixP
->fx_addsy
== NULL
4917 || S_IS_DEFINED (fixP
->fx_addsy
))
4918 && (val
== 0 || val
== -1))
4919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
4920 _("invalid byte branch offset"));
4923 /* *fragP has been relaxed to its final size, and now needs to have
4924 the bytes inside it modified to conform to the new size There is UGLY
4928 md_convert_frag_1 (fragS
*fragP
)
4933 /* Address in object code of the displacement. */
4934 int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4936 /* Address in gas core of the place to store the displacement. */
4937 /* This convinces the native rs6000 compiler to generate the code we
4939 char *buffer_address
= fragP
->fr_literal
;
4940 buffer_address
+= fragP
->fr_fix
;
4941 /* End ibm compiler workaround. */
4943 /* The displacement of the address, from current location. */
4944 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4945 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4947 switch (fragP
->fr_subtype
)
4949 case TAB (BRANCHBWL
, BYTE
):
4950 case TAB (BRABSJUNC
, BYTE
):
4951 case TAB (BRABSJCOND
, BYTE
):
4952 case TAB (BRANCHBW
, BYTE
):
4953 case TAB (BRANCHBWPL
, BYTE
):
4954 know (issbyte (disp
));
4956 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
4957 _("short branch with zero offset: use :w"));
4958 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
4959 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
4960 fixP
->fx_pcrel_adjust
= -1;
4962 case TAB (BRANCHBWL
, SHORT
):
4963 case TAB (BRABSJUNC
, SHORT
):
4964 case TAB (BRABSJCOND
, SHORT
):
4965 case TAB (BRANCHBW
, SHORT
):
4966 case TAB (BRANCHBWPL
, SHORT
):
4967 fragP
->fr_opcode
[1] = 0x00;
4968 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
4969 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
4972 case TAB (BRANCHBWL
, LONG
):
4973 fragP
->fr_opcode
[1] = (char) 0xFF;
4974 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4975 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4978 case TAB (BRANCHBWPL
, LONG
):
4979 /* Here we are converting an unconditional branch into a pair of
4980 conditional branches, in order to get the range. */
4981 fragP
->fr_opcode
[0] = 0x66; /* bne */
4982 fragP
->fr_opcode
[1] = 0xFF;
4983 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4984 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4985 fixP
->fx_file
= fragP
->fr_file
;
4986 fixP
->fx_line
= fragP
->fr_line
;
4987 fragP
->fr_fix
+= 4; /* Skip first offset */
4988 buffer_address
+= 4;
4989 *buffer_address
++ = 0x67; /* beq */
4990 *buffer_address
++ = 0xff;
4991 fragP
->fr_fix
+= 2; /* Skip second branch opcode */
4992 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
4993 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
4996 case TAB (BRABSJUNC
, LONG
):
4997 if (fragP
->fr_opcode
[0] == 0x61) /* jbsr */
4999 if (flag_keep_pcrel
)
5000 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5001 _("Conversion of PC relative BSR to absolute JSR"));
5002 fragP
->fr_opcode
[0] = 0x4E;
5003 fragP
->fr_opcode
[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
5004 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5005 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5008 else if (fragP
->fr_opcode
[0] == 0x60) /* jbra */
5010 if (flag_keep_pcrel
)
5011 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5012 _("Conversion of PC relative branch to absolute jump"));
5013 fragP
->fr_opcode
[0] = 0x4E;
5014 fragP
->fr_opcode
[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
5015 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5016 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5021 /* This cannot happen, because jbsr and jbra are the only two
5022 unconditional branches. */
5026 case TAB (BRABSJCOND
, LONG
):
5027 if (flag_keep_pcrel
)
5028 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5029 _("Conversion of PC relative conditional branch to absolute jump"));
5031 /* Only Bcc 68000 instructions can come here
5032 Change bcc into b!cc/jmp absl long. */
5033 fragP
->fr_opcode
[0] ^= 0x01; /* Invert bcc. */
5034 fragP
->fr_opcode
[1] = 0x06; /* Branch offset = 6. */
5036 /* JF: these used to be fr_opcode[2,3], but they may be in a
5037 different frag, in which case referring to them is a no-no.
5038 Only fr_opcode[0,1] are guaranteed to work. */
5039 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
5040 *buffer_address
++ = (char) 0xf9;
5041 fragP
->fr_fix
+= 2; /* Account for jmp instruction. */
5042 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5043 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5046 case TAB (FBRANCH
, SHORT
):
5047 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
5048 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5049 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5052 case TAB (FBRANCH
, LONG
):
5053 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit. */
5054 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5055 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5058 case TAB (DBCCLBR
, SHORT
):
5059 case TAB (DBCCABSJ
, SHORT
):
5060 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5061 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5064 case TAB (DBCCLBR
, LONG
):
5065 /* Only DBcc instructions can come here.
5066 Change dbcc into dbcc/bral.
5067 JF: these used to be fr_opcode[2-7], but that's wrong. */
5068 *buffer_address
++ = 0x00; /* Branch offset = 4. */
5069 *buffer_address
++ = 0x04;
5070 *buffer_address
++ = 0x60; /* Put in bra pc+6. */
5071 *buffer_address
++ = 0x06;
5072 *buffer_address
++ = 0x60; /* Put in bral (0x60ff). */
5073 *buffer_address
++ = (char) 0xff;
5075 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
5076 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5077 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5080 case TAB (DBCCABSJ
, LONG
):
5081 /* Only DBcc instructions can come here.
5082 Change dbcc into dbcc/jmp.
5083 JF: these used to be fr_opcode[2-7], but that's wrong. */
5084 if (flag_keep_pcrel
)
5085 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5086 _("Conversion of PC relative conditional branch to absolute jump"));
5088 *buffer_address
++ = 0x00; /* Branch offset = 4. */
5089 *buffer_address
++ = 0x04;
5090 *buffer_address
++ = 0x60; /* Put in bra pc + 6. */
5091 *buffer_address
++ = 0x06;
5092 *buffer_address
++ = 0x4e; /* Put in jmp long (0x4ef9). */
5093 *buffer_address
++ = (char) 0xf9;
5095 fragP
->fr_fix
+= 6; /* Account for bra/jmp instructions. */
5096 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5097 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5100 case TAB (PCREL1632
, SHORT
):
5101 fragP
->fr_opcode
[1] &= ~0x3F;
5102 fragP
->fr_opcode
[1] |= 0x3A; /* 072 - mode 7.2 */
5103 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5104 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5107 case TAB (PCREL1632
, LONG
):
5108 /* Already set to mode 7.3; this indicates: PC indirect with
5109 suppressed index, 32-bit displacement. */
5110 *buffer_address
++ = 0x01;
5111 *buffer_address
++ = 0x70;
5113 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5114 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5115 fixP
->fx_pcrel_adjust
= 2;
5118 case TAB (PCINDEX
, BYTE
):
5119 gas_assert (fragP
->fr_fix
>= 2);
5120 buffer_address
[-2] &= ~1;
5121 fixP
= fix_new (fragP
, fragP
->fr_fix
- 1, 1, fragP
->fr_symbol
,
5122 fragP
->fr_offset
, 1, RELAX_RELOC_PC8
);
5123 fixP
->fx_pcrel_adjust
= 1;
5125 case TAB (PCINDEX
, SHORT
):
5126 gas_assert (fragP
->fr_fix
>= 2);
5127 buffer_address
[-2] |= 0x1;
5128 buffer_address
[-1] = 0x20;
5129 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
5130 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5131 fixP
->fx_pcrel_adjust
= 2;
5134 case TAB (PCINDEX
, LONG
):
5135 gas_assert (fragP
->fr_fix
>= 2);
5136 buffer_address
[-2] |= 0x1;
5137 buffer_address
[-1] = 0x30;
5138 fixP
= fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
5139 fragP
->fr_offset
, 1, RELAX_RELOC_PC32
);
5140 fixP
->fx_pcrel_adjust
= 2;
5143 case TAB (ABSTOPCREL
, SHORT
):
5144 fixP
= fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
,
5145 fragP
->fr_offset
, 1, RELAX_RELOC_PC16
);
5148 case TAB (ABSTOPCREL
, LONG
):
5149 if (flag_keep_pcrel
)
5150 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
5151 _("Conversion of PC relative displacement to absolute"));
5152 /* The thing to do here is force it to ABSOLUTE LONG, since
5153 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5154 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
5156 fragP
->fr_opcode
[1] &= ~0x3F;
5157 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
5158 fixP
= fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
,
5159 fragP
->fr_offset
, 0, RELAX_RELOC_ABS32
);
5165 fixP
->fx_file
= fragP
->fr_file
;
5166 fixP
->fx_line
= fragP
->fr_line
;
5171 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
,
5172 segT sec ATTRIBUTE_UNUSED
,
5175 md_convert_frag_1 (fragP
);
5178 /* Force truly undefined symbols to their maximum size, and generally set up
5179 the frag list to be relaxed
5182 md_estimate_size_before_relax (fragS
*fragP
, segT segment
)
5184 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5185 switch (fragP
->fr_subtype
)
5187 case TAB (BRANCHBWL
, SZ_UNDEF
):
5188 case TAB (BRANCHBWPL
, SZ_UNDEF
):
5189 case TAB (BRABSJUNC
, SZ_UNDEF
):
5190 case TAB (BRABSJCOND
, SZ_UNDEF
):
5192 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5193 && relaxable_symbol (fragP
->fr_symbol
))
5195 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5197 else if (flag_short_refs
)
5199 /* Symbol is undefined and we want short ref. */
5200 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5204 /* Symbol is still undefined. Make it LONG. */
5205 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5210 case TAB (BRANCHBW
, SZ_UNDEF
):
5212 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5213 && relaxable_symbol (fragP
->fr_symbol
))
5215 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
5219 /* Symbol is undefined and we don't have long branches. */
5220 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5225 case TAB (FBRANCH
, SZ_UNDEF
):
5226 case TAB (DBCCLBR
, SZ_UNDEF
):
5227 case TAB (DBCCABSJ
, SZ_UNDEF
):
5228 case TAB (PCREL1632
, SZ_UNDEF
):
5230 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5231 && relaxable_symbol (fragP
->fr_symbol
))
5234 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5238 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), LONG
);
5243 case TAB (PCINDEX
, SZ_UNDEF
):
5244 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5245 && relaxable_symbol (fragP
->fr_symbol
)))
5247 fragP
->fr_subtype
= TAB (PCINDEX
, BYTE
);
5251 fragP
->fr_subtype
= TAB (PCINDEX
, LONG
);
5255 case TAB (ABSTOPCREL
, SZ_UNDEF
):
5257 if ((S_GET_SEGMENT (fragP
->fr_symbol
) == segment
5258 && relaxable_symbol (fragP
->fr_symbol
)))
5260 fragP
->fr_subtype
= TAB (ABSTOPCREL
, SHORT
);
5264 fragP
->fr_subtype
= TAB (ABSTOPCREL
, LONG
);
5273 /* Now that SZ_UNDEF are taken care of, check others. */
5274 switch (fragP
->fr_subtype
)
5276 case TAB (BRANCHBWL
, BYTE
):
5277 case TAB (BRABSJUNC
, BYTE
):
5278 case TAB (BRABSJCOND
, BYTE
):
5279 case TAB (BRANCHBW
, BYTE
):
5280 /* We can't do a short jump to the next instruction, so in that
5281 case we force word mode. If the symbol is at the start of a
5282 frag, and it is the next frag with any data in it (usually
5283 this is just the next frag, but assembler listings may
5284 introduce empty frags), we must use word mode. */
5285 if (fragP
->fr_symbol
)
5289 sym_frag
= symbol_get_frag (fragP
->fr_symbol
);
5290 if (S_GET_VALUE (fragP
->fr_symbol
) == sym_frag
->fr_address
)
5294 for (l
= fragP
->fr_next
; l
&& l
!= sym_frag
; l
= l
->fr_next
)
5298 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
5305 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
5308 #ifndef WORKING_DOT_WORD
5309 int md_short_jump_size
= 4;
5310 int md_long_jump_size
= 6;
5313 md_create_short_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5314 fragS
*frag ATTRIBUTE_UNUSED
,
5315 symbolS
*to_symbol ATTRIBUTE_UNUSED
)
5319 offset
= to_addr
- (from_addr
+ 2);
5321 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
5322 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
5326 md_create_long_jump (char *ptr
, addressT from_addr
, addressT to_addr
,
5327 fragS
*frag
, symbolS
*to_symbol
)
5331 if (!HAVE_LONG_BRANCH (current_architecture
))
5333 if (flag_keep_pcrel
)
5334 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5335 offset
= to_addr
- S_GET_VALUE (to_symbol
);
5336 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
5337 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5338 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (offsetT
) 0,
5343 offset
= to_addr
- (from_addr
+ 2);
5344 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
5345 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
5351 /* Different values of OK tell what it's OK to return. Things that
5352 aren't OK are an error (what a shock, no?)
5355 10: Absolute 1:8 only
5356 20: Absolute 0:7 only
5357 30: absolute 0:15 only
5358 40: Absolute 0:31 only
5359 50: absolute 0:127 only
5360 55: absolute -64:63 only
5361 60: absolute -128:127 only
5362 65: absolute 0:511 only
5363 70: absolute 0:4095 only
5364 80: absolute -1, 1:7 only
5368 get_num (struct m68k_exp
*exp
, int ok
)
5370 if (exp
->exp
.X_op
== O_absent
)
5372 /* Do the same thing the VAX asm does. */
5373 op (exp
) = O_constant
;
5379 as_warn (_("expression out of range: defaulting to 1"));
5383 else if (exp
->exp
.X_op
== O_constant
)
5388 if ((valueT
) TRUNC (offs (exp
)) - 1 > 7)
5390 as_warn (_("expression out of range: defaulting to 1"));
5395 if ((valueT
) TRUNC (offs (exp
)) > 7)
5399 if ((valueT
) TRUNC (offs (exp
)) > 15)
5403 if ((valueT
) TRUNC (offs (exp
)) > 32)
5407 if ((valueT
) TRUNC (offs (exp
)) > 127)
5411 if ((valueT
) SEXT (offs (exp
)) + 64 > 127)
5415 if ((valueT
) SEXT (offs (exp
)) + 128 > 255)
5419 if ((valueT
) TRUNC (offs (exp
)) > 511)
5423 if ((valueT
) TRUNC (offs (exp
)) > 4095)
5426 as_warn (_("expression out of range: defaulting to 0"));
5431 if ((valueT
) TRUNC (offs (exp
)) != 0xffffffff
5432 && (valueT
) TRUNC (offs (exp
)) - 1 > 6)
5434 as_warn (_("expression out of range: defaulting to 1"));
5442 else if (exp
->exp
.X_op
== O_big
)
5444 if (offs (exp
) <= 0 /* flonum. */
5445 && (ok
== 90 /* no bignums */
5446 || (ok
> 10 /* Small-int ranges including 0 ok. */
5447 /* If we have a flonum zero, a zero integer should
5448 do as well (e.g., in moveq). */
5449 && generic_floating_point_number
.exponent
== 0
5450 && generic_floating_point_number
.low
[0] == 0)))
5452 /* HACK! Turn it into a long. */
5453 LITTLENUM_TYPE words
[6];
5455 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
5456 op (exp
) = O_constant
;
5459 offs (exp
) = words
[1] | (words
[0] << 16);
5463 op (exp
) = O_constant
;
5466 offs (exp
) = (ok
== 10) ? 1 : 0;
5467 as_warn (_("Can't deal with expression; defaulting to %ld"),
5473 if (ok
>= 10 && ok
<= 80)
5475 op (exp
) = O_constant
;
5478 offs (exp
) = (ok
== 10) ? 1 : 0;
5479 as_warn (_("Can't deal with expression; defaulting to %ld"),
5484 if (exp
->size
!= SIZE_UNSPEC
)
5492 if (!isbyte (offs (exp
)))
5493 as_warn (_("expression doesn't fit in BYTE"));
5496 if (!isword (offs (exp
)))
5497 as_warn (_("expression doesn't fit in WORD"));
5505 /* These are the back-ends for the various machine dependent pseudo-ops. */
5508 s_data1 (int ignore ATTRIBUTE_UNUSED
)
5510 subseg_set (data_section
, 1);
5511 demand_empty_rest_of_line ();
5515 s_data2 (int ignore ATTRIBUTE_UNUSED
)
5517 subseg_set (data_section
, 2);
5518 demand_empty_rest_of_line ();
5522 s_bss (int ignore ATTRIBUTE_UNUSED
)
5524 /* We don't support putting frags in the BSS segment, we fake it
5525 by marking in_bss, then looking at s_skip for clues. */
5527 subseg_set (bss_section
, 0);
5528 demand_empty_rest_of_line ();
5532 s_even (int ignore ATTRIBUTE_UNUSED
)
5537 temp
= 1; /* JF should be 2? */
5538 temp_fill
= get_absolute_expression ();
5539 if (!need_pass_2
) /* Never make frag if expect extra pass. */
5540 frag_align (temp
, (int) temp_fill
, 0);
5541 demand_empty_rest_of_line ();
5542 record_alignment (now_seg
, temp
);
5546 s_proc (int ignore ATTRIBUTE_UNUSED
)
5548 demand_empty_rest_of_line ();
5551 /* Pseudo-ops handled for MRI compatibility. */
5553 /* This function returns non-zero if the argument is a conditional
5554 pseudo-op. This is called when checking whether a pending
5555 alignment is needed. */
5558 m68k_conditional_pseudoop (const pseudo_typeS
*pop
)
5560 return (pop
->poc_handler
== s_mri_if
5561 || pop
->poc_handler
== s_mri_else
);
5564 /* Handle an MRI style chip specification. */
5573 s
= input_line_pointer
;
5574 /* We can't use get_symbol_name since the processor names are not proper
5576 while (is_part_of_name (c
= *input_line_pointer
++))
5578 *--input_line_pointer
= 0;
5579 for (i
= 0; m68k_cpus
[i
].name
; i
++)
5580 if (strcasecmp (s
, m68k_cpus
[i
].name
) == 0)
5582 if (!m68k_cpus
[i
].name
)
5584 as_bad (_("%s: unrecognized processor name"), s
);
5585 *input_line_pointer
= c
;
5586 ignore_rest_of_line ();
5589 *input_line_pointer
= c
;
5591 if (*input_line_pointer
== '/')
5592 current_architecture
= 0;
5594 current_architecture
&= m68881
| m68851
;
5595 current_architecture
|= m68k_cpus
[i
].arch
& ~(m68881
| m68851
);
5596 control_regs
= m68k_cpus
[i
].control_regs
;
5598 while (*input_line_pointer
== '/')
5600 ++input_line_pointer
;
5601 s
= input_line_pointer
;
5602 /* We can't use get_symbol_name since the processor names are not
5604 while (is_part_of_name (c
= *input_line_pointer
++))
5606 *--input_line_pointer
= 0;
5607 if (strcmp (s
, "68881") == 0)
5608 current_architecture
|= m68881
;
5609 else if (strcmp (s
, "68851") == 0)
5610 current_architecture
|= m68851
;
5611 *input_line_pointer
= c
;
5615 /* The MRI CHIP pseudo-op. */
5618 s_chip (int ignore ATTRIBUTE_UNUSED
)
5624 stop
= mri_comment_field (&stopc
);
5627 mri_comment_end (stop
, stopc
);
5628 demand_empty_rest_of_line ();
5631 /* The MRI FOPT pseudo-op. */
5634 s_fopt (int ignore ATTRIBUTE_UNUSED
)
5638 if (strncasecmp (input_line_pointer
, "ID=", 3) == 0)
5642 input_line_pointer
+= 3;
5643 temp
= get_absolute_expression ();
5644 if (temp
< 0 || temp
> 7)
5645 as_bad (_("bad coprocessor id"));
5647 m68k_float_copnum
= COP0
+ temp
;
5651 as_bad (_("unrecognized fopt option"));
5652 ignore_rest_of_line ();
5656 demand_empty_rest_of_line ();
5659 /* The structure used to handle the MRI OPT pseudo-op. */
5663 /* The name of the option. */
5666 /* If this is not NULL, just call this function. The first argument
5667 is the ARG field of this structure, the second argument is
5668 whether the option was negated. */
5669 void (*pfn
) (int arg
, int on
);
5671 /* If this is not NULL, and the PFN field is NULL, set the variable
5672 this points to. Set it to the ARG field if the option was not
5673 negated, and the NOTARG field otherwise. */
5676 /* The value to pass to PFN or to assign to *PVAR. */
5679 /* The value to assign to *PVAR if the option is negated. If PFN is
5680 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5681 the option may not be negated. */
5685 /* The table used to handle the MRI OPT pseudo-op. */
5687 static void skip_to_comma (int, int);
5688 static void opt_nest (int, int);
5689 static void opt_chip (int, int);
5690 static void opt_list (int, int);
5691 static void opt_list_symbols (int, int);
5693 static const struct opt_action opt_table
[] =
5695 { "abspcadd", 0, &m68k_abspcadd
, 1, 0 },
5697 /* We do relaxing, so there is little use for these options. */
5698 { "b", 0, 0, 0, 0 },
5699 { "brs", 0, 0, 0, 0 },
5700 { "brb", 0, 0, 0, 0 },
5701 { "brl", 0, 0, 0, 0 },
5702 { "brw", 0, 0, 0, 0 },
5704 { "c", 0, 0, 0, 0 },
5705 { "cex", 0, 0, 0, 0 },
5706 { "case", 0, &symbols_case_sensitive
, 1, 0 },
5707 { "cl", 0, 0, 0, 0 },
5708 { "cre", 0, 0, 0, 0 },
5709 { "d", 0, &flag_keep_locals
, 1, 0 },
5710 { "e", 0, 0, 0, 0 },
5711 { "f", 0, &flag_short_refs
, 1, 0 },
5712 { "frs", 0, &flag_short_refs
, 1, 0 },
5713 { "frl", 0, &flag_short_refs
, 0, 1 },
5714 { "g", 0, 0, 0, 0 },
5715 { "i", 0, 0, 0, 0 },
5716 { "m", 0, 0, 0, 0 },
5717 { "mex", 0, 0, 0, 0 },
5718 { "mc", 0, 0, 0, 0 },
5719 { "md", 0, 0, 0, 0 },
5720 { "nest", opt_nest
, 0, 0, 0 },
5721 { "next", skip_to_comma
, 0, 0, 0 },
5722 { "o", 0, 0, 0, 0 },
5723 { "old", 0, 0, 0, 0 },
5724 { "op", skip_to_comma
, 0, 0, 0 },
5725 { "pco", 0, 0, 0, 0 },
5726 { "p", opt_chip
, 0, 0, 0 },
5727 { "pcr", 0, 0, 0, 0 },
5728 { "pcs", 0, 0, 0, 0 },
5729 { "r", 0, 0, 0, 0 },
5730 { "quick", 0, &m68k_quick
, 1, 0 },
5731 { "rel32", 0, &m68k_rel32
, 1, 0 },
5732 { "s", opt_list
, 0, 0, 0 },
5733 { "t", opt_list_symbols
, 0, 0, 0 },
5734 { "w", 0, &flag_no_warnings
, 0, 1 },
5738 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5740 /* The MRI OPT pseudo-op. */
5743 s_opt (int ignore ATTRIBUTE_UNUSED
)
5751 const struct opt_action
*o
;
5756 if (*input_line_pointer
== '-')
5758 ++input_line_pointer
;
5761 else if (strncasecmp (input_line_pointer
, "NO", 2) == 0)
5763 input_line_pointer
+= 2;
5767 c
= get_symbol_name (&s
);
5769 for (i
= 0, o
= opt_table
; i
< OPTCOUNT
; i
++, o
++)
5771 if (strcasecmp (s
, o
->name
) == 0)
5775 /* Restore input_line_pointer now in case the option
5777 (void) restore_line_pointer (c
);
5778 (*o
->pfn
) (o
->arg
, t
);
5780 else if (o
->pvar
!= NULL
)
5782 if (! t
&& o
->arg
== o
->notarg
)
5783 as_bad (_("option `%s' may not be negated"), s
);
5784 restore_line_pointer (c
);
5785 *o
->pvar
= t
? o
->arg
: o
->notarg
;
5788 *input_line_pointer
= c
;
5794 as_bad (_("option `%s' not recognized"), s
);
5795 restore_line_pointer (c
);
5798 while (*input_line_pointer
++ == ',');
5800 /* Move back to terminating character. */
5801 --input_line_pointer
;
5802 demand_empty_rest_of_line ();
5805 /* Skip ahead to a comma. This is used for OPT options which we do
5806 not support and which take arguments. */
5809 skip_to_comma (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5811 while (*input_line_pointer
!= ','
5812 && ! is_end_of_line
[(unsigned char) *input_line_pointer
])
5813 ++input_line_pointer
;
5816 /* Handle the OPT NEST=depth option. */
5819 opt_nest (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5821 if (*input_line_pointer
!= '=')
5823 as_bad (_("bad format of OPT NEST=depth"));
5827 ++input_line_pointer
;
5828 max_macro_nest
= get_absolute_expression ();
5831 /* Handle the OPT P=chip option. */
5834 opt_chip (int arg ATTRIBUTE_UNUSED
, int on ATTRIBUTE_UNUSED
)
5836 if (*input_line_pointer
!= '=')
5838 /* This is just OPT P, which we do not support. */
5842 ++input_line_pointer
;
5846 /* Handle the OPT S option. */
5849 opt_list (int arg ATTRIBUTE_UNUSED
, int on
)
5854 /* Handle the OPT T option. */
5857 opt_list_symbols (int arg ATTRIBUTE_UNUSED
, int on
)
5860 listing
|= LISTING_SYMBOLS
;
5862 listing
&= ~LISTING_SYMBOLS
;
5865 /* Handle the MRI REG pseudo-op. */
5868 s_reg (int ignore ATTRIBUTE_UNUSED
)
5877 if (line_label
== NULL
)
5879 as_bad (_("missing label"));
5880 ignore_rest_of_line ();
5885 stop
= mri_comment_field (&stopc
);
5889 s
= input_line_pointer
;
5890 while (ISALNUM (*input_line_pointer
)
5891 #ifdef REGISTER_PREFIX
5892 || *input_line_pointer
== REGISTER_PREFIX
5894 || *input_line_pointer
== '/'
5895 || *input_line_pointer
== '-')
5896 ++input_line_pointer
;
5897 c
= *input_line_pointer
;
5898 *input_line_pointer
= '\0';
5900 if (m68k_ip_op (s
, &rop
) != 0)
5902 if (rop
.error
== NULL
)
5903 as_bad (_("bad register list"));
5905 as_bad (_("bad register list: %s"), rop
.error
);
5906 *input_line_pointer
= c
;
5907 ignore_rest_of_line ();
5911 *input_line_pointer
= c
;
5913 if (rop
.mode
== REGLST
)
5915 else if (rop
.mode
== DREG
)
5916 mask
= 1 << (rop
.reg
- DATA0
);
5917 else if (rop
.mode
== AREG
)
5918 mask
= 1 << (rop
.reg
- ADDR0
+ 8);
5919 else if (rop
.mode
== FPREG
)
5920 mask
= 1 << (rop
.reg
- FP0
+ 16);
5921 else if (rop
.mode
== CONTROL
5924 else if (rop
.mode
== CONTROL
5927 else if (rop
.mode
== CONTROL
5932 as_bad (_("bad register list"));
5933 ignore_rest_of_line ();
5937 S_SET_SEGMENT (line_label
, reg_section
);
5938 S_SET_VALUE (line_label
, ~mask
);
5939 symbol_set_frag (line_label
, &zero_address_frag
);
5942 mri_comment_end (stop
, stopc
);
5944 demand_empty_rest_of_line ();
5947 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5951 struct save_opts
*next
;
5953 int symbols_case_sensitive
;
5957 const enum m68k_register
*control_regs
;
5962 /* FIXME: We don't save OPT S. */
5965 /* This variable holds the stack of saved options. */
5967 static struct save_opts
*save_stack
;
5969 /* The MRI SAVE pseudo-op. */
5972 s_save (int ignore ATTRIBUTE_UNUSED
)
5974 struct save_opts
*s
;
5976 s
= XNEW (struct save_opts
);
5977 s
->abspcadd
= m68k_abspcadd
;
5978 s
->symbols_case_sensitive
= symbols_case_sensitive
;
5979 s
->keep_locals
= flag_keep_locals
;
5980 s
->short_refs
= flag_short_refs
;
5981 s
->architecture
= current_architecture
;
5982 s
->control_regs
= control_regs
;
5983 s
->quick
= m68k_quick
;
5984 s
->rel32
= m68k_rel32
;
5985 s
->listing
= listing
;
5986 s
->no_warnings
= flag_no_warnings
;
5988 s
->next
= save_stack
;
5991 demand_empty_rest_of_line ();
5994 /* The MRI RESTORE pseudo-op. */
5997 s_restore (int ignore ATTRIBUTE_UNUSED
)
5999 struct save_opts
*s
;
6001 if (save_stack
== NULL
)
6003 as_bad (_("restore without save"));
6004 ignore_rest_of_line ();
6009 save_stack
= s
->next
;
6011 m68k_abspcadd
= s
->abspcadd
;
6012 symbols_case_sensitive
= s
->symbols_case_sensitive
;
6013 flag_keep_locals
= s
->keep_locals
;
6014 flag_short_refs
= s
->short_refs
;
6015 current_architecture
= s
->architecture
;
6016 control_regs
= s
->control_regs
;
6017 m68k_quick
= s
->quick
;
6018 m68k_rel32
= s
->rel32
;
6019 listing
= s
->listing
;
6020 flag_no_warnings
= s
->no_warnings
;
6024 demand_empty_rest_of_line ();
6027 /* Types of MRI structured control directives. */
6029 enum mri_control_type
6037 /* This structure is used to stack the MRI structured control
6040 struct mri_control_info
6042 /* The directive within which this one is enclosed. */
6043 struct mri_control_info
*outer
;
6045 /* The type of directive. */
6046 enum mri_control_type type
;
6048 /* Whether an ELSE has been in an IF. */
6051 /* The add or sub statement at the end of a FOR. */
6054 /* The label of the top of a FOR or REPEAT loop. */
6057 /* The label to jump to for the next iteration, or the else
6058 expression of a conditional. */
6061 /* The label to jump to to break out of the loop, or the label past
6062 the end of a conditional. */
6066 /* The stack of MRI structured control directives. */
6068 static struct mri_control_info
*mri_control_stack
;
6070 /* The current MRI structured control directive index number, used to
6071 generate label names. */
6073 static int mri_control_index
;
6075 /* Assemble an instruction for an MRI structured control directive. */
6078 mri_assemble (char *str
)
6082 /* md_assemble expects the opcode to be in lower case. */
6083 for (s
= str
; *s
!= ' ' && *s
!= '\0'; s
++)
6089 /* Generate a new MRI label structured control directive label name. */
6092 mri_control_label (void)
6096 n
= XNEWVEC (char, 20);
6097 sprintf (n
, "%smc%d", FAKE_LABEL_NAME
, mri_control_index
);
6098 ++mri_control_index
;
6102 /* Create a new MRI structured control directive. */
6104 static struct mri_control_info
*
6105 push_mri_control (enum mri_control_type type
)
6107 struct mri_control_info
*n
;
6109 n
= XNEW (struct mri_control_info
);
6113 if (type
== mri_if
|| type
== mri_while
)
6116 n
->top
= mri_control_label ();
6117 n
->next
= mri_control_label ();
6118 n
->bottom
= mri_control_label ();
6120 n
->outer
= mri_control_stack
;
6121 mri_control_stack
= n
;
6126 /* Pop off the stack of MRI structured control directives. */
6129 pop_mri_control (void)
6131 struct mri_control_info
*n
;
6133 n
= mri_control_stack
;
6134 mri_control_stack
= n
->outer
;
6141 /* Recognize a condition code in an MRI structured control expression. */
6144 parse_mri_condition (int *pcc
)
6148 know (*input_line_pointer
== '<');
6150 ++input_line_pointer
;
6151 c1
= *input_line_pointer
++;
6152 c2
= *input_line_pointer
++;
6154 if (*input_line_pointer
!= '>')
6156 as_bad (_("syntax error in structured control directive"));
6160 ++input_line_pointer
;
6166 *pcc
= (c1
<< 8) | c2
;
6171 /* Parse a single operand in an MRI structured control expression. */
6174 parse_mri_control_operand (int *pcc
, char **leftstart
, char **leftstop
,
6175 char **rightstart
, char **rightstop
)
6187 if (*input_line_pointer
== '<')
6189 /* It's just a condition code. */
6190 return parse_mri_condition (pcc
);
6193 /* Look ahead for the condition code. */
6194 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6196 if (*s
== '<' && s
[1] != '\0' && s
[2] != '\0' && s
[3] == '>')
6201 as_bad (_("missing condition code in structured control directive"));
6205 *leftstart
= input_line_pointer
;
6207 if (*leftstop
> *leftstart
6208 && ((*leftstop
)[-1] == ' ' || (*leftstop
)[-1] == '\t'))
6211 input_line_pointer
= s
;
6212 if (! parse_mri_condition (pcc
))
6215 /* Look ahead for AND or OR or end of line. */
6216 for (s
= input_line_pointer
; *s
!= '\0'; ++s
)
6218 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6219 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6221 if ((s
== input_line_pointer
6224 && ((strncasecmp (s
, "AND", 3) == 0
6225 && (s
[3] == '.' || ! is_part_of_name (s
[3])))
6226 || (strncasecmp (s
, "OR", 2) == 0
6227 && (s
[2] == '.' || ! is_part_of_name (s
[2])))))
6231 *rightstart
= input_line_pointer
;
6233 if (*rightstop
> *rightstart
6234 && ((*rightstop
)[-1] == ' ' || (*rightstop
)[-1] == '\t'))
6237 input_line_pointer
= s
;
6242 #define MCC(b1, b2) (((b1) << 8) | (b2))
6244 /* Swap the sense of a condition. This changes the condition so that
6245 it generates the same result when the operands are swapped. */
6248 swap_mri_condition (int cc
)
6252 case MCC ('h', 'i'): return MCC ('c', 's');
6253 case MCC ('l', 's'): return MCC ('c', 'c');
6254 /* <HS> is an alias for <CC>. */
6255 case MCC ('h', 's'):
6256 case MCC ('c', 'c'): return MCC ('l', 's');
6257 /* <LO> is an alias for <CS>. */
6258 case MCC ('l', 'o'):
6259 case MCC ('c', 's'): return MCC ('h', 'i');
6260 case MCC ('p', 'l'): return MCC ('m', 'i');
6261 case MCC ('m', 'i'): return MCC ('p', 'l');
6262 case MCC ('g', 'e'): return MCC ('l', 'e');
6263 case MCC ('l', 't'): return MCC ('g', 't');
6264 case MCC ('g', 't'): return MCC ('l', 't');
6265 case MCC ('l', 'e'): return MCC ('g', 'e');
6266 /* Issue a warning for conditions we can not swap. */
6267 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6268 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6269 case MCC ('v', 'c'):
6270 case MCC ('v', 's'):
6272 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6273 (char) (cc
>> 8), (char) (cc
));
6279 /* Reverse the sense of a condition. */
6282 reverse_mri_condition (int cc
)
6286 case MCC ('h', 'i'): return MCC ('l', 's');
6287 case MCC ('l', 's'): return MCC ('h', 'i');
6288 /* <HS> is an alias for <CC> */
6289 case MCC ('h', 's'): return MCC ('l', 'o');
6290 case MCC ('c', 'c'): return MCC ('c', 's');
6291 /* <LO> is an alias for <CS> */
6292 case MCC ('l', 'o'): return MCC ('h', 's');
6293 case MCC ('c', 's'): return MCC ('c', 'c');
6294 case MCC ('n', 'e'): return MCC ('e', 'q');
6295 case MCC ('e', 'q'): return MCC ('n', 'e');
6296 case MCC ('v', 'c'): return MCC ('v', 's');
6297 case MCC ('v', 's'): return MCC ('v', 'c');
6298 case MCC ('p', 'l'): return MCC ('m', 'i');
6299 case MCC ('m', 'i'): return MCC ('p', 'l');
6300 case MCC ('g', 'e'): return MCC ('l', 't');
6301 case MCC ('l', 't'): return MCC ('g', 'e');
6302 case MCC ('g', 't'): return MCC ('l', 'e');
6303 case MCC ('l', 'e'): return MCC ('g', 't');
6308 /* Build an MRI structured control expression. This generates test
6309 and branch instructions. It goes to TRUELAB if the condition is
6310 true, and to FALSELAB if the condition is false. Exactly one of
6311 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6312 is the size qualifier for the expression. EXTENT is the size to
6313 use for the branch. */
6316 build_mri_control_operand (int qual
, int cc
, char *leftstart
, char *leftstop
,
6317 char *rightstart
, char *rightstop
,
6318 const char *truelab
, const char *falselab
,
6324 if (leftstart
!= NULL
)
6326 struct m68k_op leftop
, rightop
;
6329 /* Swap the compare operands, if necessary, to produce a legal
6330 m68k compare instruction. Comparing a register operand with
6331 a non-register operand requires the register to be on the
6332 right (cmp, cmpa). Comparing an immediate value with
6333 anything requires the immediate value to be on the left
6338 (void) m68k_ip_op (leftstart
, &leftop
);
6343 (void) m68k_ip_op (rightstart
, &rightop
);
6346 if (rightop
.mode
== IMMED
6347 || ((leftop
.mode
== DREG
|| leftop
.mode
== AREG
)
6348 && (rightop
.mode
!= DREG
&& rightop
.mode
!= AREG
)))
6352 /* Correct conditional handling:
6353 if #1 <lt> d0 then ;means if (1 < d0)
6359 cmp #1,d0 if we do *not* swap the operands
6360 bgt true we need the swapped condition!
6367 leftstart
= rightstart
;
6370 leftstop
= rightstop
;
6375 cc
= swap_mri_condition (cc
);
6379 if (truelab
== NULL
)
6381 cc
= reverse_mri_condition (cc
);
6385 if (leftstart
!= NULL
)
6387 buf
= XNEWVEC (char, (20
6388 + (leftstop
- leftstart
)
6389 + (rightstop
- rightstart
)));
6395 *s
++ = TOLOWER (qual
);
6397 memcpy (s
, leftstart
, leftstop
- leftstart
);
6398 s
+= leftstop
- leftstart
;
6400 memcpy (s
, rightstart
, rightstop
- rightstart
);
6401 s
+= rightstop
- rightstart
;
6407 buf
= XNEWVEC (char, 20 + strlen (truelab
));
6413 *s
++ = TOLOWER (extent
);
6415 strcpy (s
, truelab
);
6420 /* Parse an MRI structured control expression. This generates test
6421 and branch instructions. STOP is where the expression ends. It
6422 goes to TRUELAB if the condition is true, and to FALSELAB if the
6423 condition is false. Exactly one of TRUELAB and FALSELAB will be
6424 NULL, meaning to fall through. QUAL is the size qualifier for the
6425 expression. EXTENT is the size to use for the branch. */
6428 parse_mri_control_expression (char *stop
, int qual
, const char *truelab
,
6429 const char *falselab
, int extent
)
6441 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6442 &rightstart
, &rightstop
))
6448 if (strncasecmp (input_line_pointer
, "AND", 3) == 0)
6452 if (falselab
!= NULL
)
6455 flab
= mri_control_label ();
6457 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6458 rightstop
, (const char *) NULL
, flab
, extent
);
6460 input_line_pointer
+= 3;
6461 if (*input_line_pointer
!= '.'
6462 || input_line_pointer
[1] == '\0')
6466 qual
= input_line_pointer
[1];
6467 input_line_pointer
+= 2;
6470 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6471 &rightstart
, &rightstop
))
6477 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6478 rightstop
, truelab
, falselab
, extent
);
6480 if (falselab
== NULL
)
6483 else if (strncasecmp (input_line_pointer
, "OR", 2) == 0)
6487 if (truelab
!= NULL
)
6490 tlab
= mri_control_label ();
6492 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6493 rightstop
, tlab
, (const char *) NULL
, extent
);
6495 input_line_pointer
+= 2;
6496 if (*input_line_pointer
!= '.'
6497 || input_line_pointer
[1] == '\0')
6501 qual
= input_line_pointer
[1];
6502 input_line_pointer
+= 2;
6505 if (! parse_mri_control_operand (&cc
, &leftstart
, &leftstop
,
6506 &rightstart
, &rightstop
))
6512 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6513 rightstop
, truelab
, falselab
, extent
);
6515 if (truelab
== NULL
)
6520 build_mri_control_operand (qual
, cc
, leftstart
, leftstop
, rightstart
,
6521 rightstop
, truelab
, falselab
, extent
);
6525 if (input_line_pointer
!= stop
)
6526 as_bad (_("syntax error in structured control directive"));
6529 /* Handle the MRI IF pseudo-op. This may be a structured control
6530 directive, or it may be a regular assembler conditional, depending
6538 struct mri_control_info
*n
;
6540 /* A structured control directive must end with THEN with an
6541 optional qualifier. */
6542 s
= input_line_pointer
;
6543 /* We only accept '*' as introduction of comments if preceded by white space
6544 or at first column of a line (I think this can't actually happen here?)
6545 This is important when assembling:
6546 if d0 <ne> 12(a0,d0*2) then
6547 if d0 <ne> #CONST*20 then. */
6548 while (! (is_end_of_line
[(unsigned char) *s
]
6551 && (s
== input_line_pointer
6553 || *(s
-1) == '\t'))))
6556 while (s
> input_line_pointer
&& (*s
== ' ' || *s
== '\t'))
6559 if (s
- input_line_pointer
> 1
6563 if (s
- input_line_pointer
< 3
6564 || strncasecmp (s
- 3, "THEN", 4) != 0)
6568 as_bad (_("missing then"));
6569 ignore_rest_of_line ();
6573 /* It's a conditional. */
6578 /* Since this might be a conditional if, this pseudo-op will be
6579 called even if we are supported to be ignoring input. Double
6580 check now. Clobber *input_line_pointer so that ignore_input
6581 thinks that this is not a special pseudo-op. */
6582 c
= *input_line_pointer
;
6583 *input_line_pointer
= 0;
6584 if (ignore_input ())
6586 *input_line_pointer
= c
;
6587 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6588 ++input_line_pointer
;
6589 demand_empty_rest_of_line ();
6592 *input_line_pointer
= c
;
6594 n
= push_mri_control (mri_if
);
6596 parse_mri_control_expression (s
- 3, qual
, (const char *) NULL
,
6597 n
->next
, s
[1] == '.' ? s
[2] : '\0');
6600 input_line_pointer
= s
+ 3;
6602 input_line_pointer
= s
+ 1;
6606 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6607 ++input_line_pointer
;
6610 demand_empty_rest_of_line ();
6613 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6614 structured IF, associate the ELSE with the IF. Otherwise, assume
6615 it is a conditional else. */
6618 s_mri_else (int qual
)
6625 && (mri_control_stack
== NULL
6626 || mri_control_stack
->type
!= mri_if
6627 || mri_control_stack
->else_seen
))
6633 c
= *input_line_pointer
;
6634 *input_line_pointer
= 0;
6635 if (ignore_input ())
6637 *input_line_pointer
= c
;
6638 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6639 ++input_line_pointer
;
6640 demand_empty_rest_of_line ();
6643 *input_line_pointer
= c
;
6645 if (mri_control_stack
== NULL
6646 || mri_control_stack
->type
!= mri_if
6647 || mri_control_stack
->else_seen
)
6649 as_bad (_("else without matching if"));
6650 ignore_rest_of_line ();
6654 mri_control_stack
->else_seen
= 1;
6656 buf
= XNEWVEC (char, 20 + strlen (mri_control_stack
->bottom
));
6657 q
[0] = TOLOWER (qual
);
6659 sprintf (buf
, "bra%s %s", q
, mri_control_stack
->bottom
);
6663 colon (mri_control_stack
->next
);
6667 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6668 ++input_line_pointer
;
6671 demand_empty_rest_of_line ();
6674 /* Handle the MRI ENDI pseudo-op. */
6677 s_mri_endi (int ignore ATTRIBUTE_UNUSED
)
6679 if (mri_control_stack
== NULL
6680 || mri_control_stack
->type
!= mri_if
)
6682 as_bad (_("endi without matching if"));
6683 ignore_rest_of_line ();
6687 /* ignore_input will not return true for ENDI, so we don't need to
6688 worry about checking it again here. */
6690 if (! mri_control_stack
->else_seen
)
6691 colon (mri_control_stack
->next
);
6692 colon (mri_control_stack
->bottom
);
6698 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6699 ++input_line_pointer
;
6702 demand_empty_rest_of_line ();
6705 /* Handle the MRI BREAK pseudo-op. */
6708 s_mri_break (int extent
)
6710 struct mri_control_info
*n
;
6714 n
= mri_control_stack
;
6716 && n
->type
!= mri_for
6717 && n
->type
!= mri_repeat
6718 && n
->type
!= mri_while
)
6722 as_bad (_("break outside of structured loop"));
6723 ignore_rest_of_line ();
6727 buf
= XNEWVEC (char, 20 + strlen (n
->bottom
));
6728 ex
[0] = TOLOWER (extent
);
6730 sprintf (buf
, "bra%s %s", ex
, n
->bottom
);
6736 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6737 ++input_line_pointer
;
6740 demand_empty_rest_of_line ();
6743 /* Handle the MRI NEXT pseudo-op. */
6746 s_mri_next (int extent
)
6748 struct mri_control_info
*n
;
6752 n
= mri_control_stack
;
6754 && n
->type
!= mri_for
6755 && n
->type
!= mri_repeat
6756 && n
->type
!= mri_while
)
6760 as_bad (_("next outside of structured loop"));
6761 ignore_rest_of_line ();
6765 buf
= XNEWVEC (char, 20 + strlen (n
->next
));
6766 ex
[0] = TOLOWER (extent
);
6768 sprintf (buf
, "bra%s %s", ex
, n
->next
);
6774 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6775 ++input_line_pointer
;
6778 demand_empty_rest_of_line ();
6781 /* Handle the MRI FOR pseudo-op. */
6784 s_mri_for (int qual
)
6786 const char *varstart
, *varstop
;
6787 const char *initstart
, *initstop
;
6788 const char *endstart
, *endstop
;
6789 const char *bystart
, *bystop
;
6793 struct mri_control_info
*n
;
6799 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6803 varstart
= input_line_pointer
;
6805 /* Look for the '='. */
6806 while (! is_end_of_line
[(unsigned char) *input_line_pointer
]
6807 && *input_line_pointer
!= '=')
6808 ++input_line_pointer
;
6809 if (*input_line_pointer
!= '=')
6811 as_bad (_("missing ="));
6812 ignore_rest_of_line ();
6816 varstop
= input_line_pointer
;
6817 if (varstop
> varstart
6818 && (varstop
[-1] == ' ' || varstop
[-1] == '\t'))
6821 ++input_line_pointer
;
6823 initstart
= input_line_pointer
;
6825 /* Look for TO or DOWNTO. */
6828 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6830 if (strncasecmp (input_line_pointer
, "TO", 2) == 0
6831 && ! is_part_of_name (input_line_pointer
[2]))
6833 initstop
= input_line_pointer
;
6834 input_line_pointer
+= 2;
6837 if (strncasecmp (input_line_pointer
, "DOWNTO", 6) == 0
6838 && ! is_part_of_name (input_line_pointer
[6]))
6840 initstop
= input_line_pointer
;
6842 input_line_pointer
+= 6;
6845 ++input_line_pointer
;
6847 if (initstop
== NULL
)
6849 as_bad (_("missing to or downto"));
6850 ignore_rest_of_line ();
6853 if (initstop
> initstart
6854 && (initstop
[-1] == ' ' || initstop
[-1] == '\t'))
6858 endstart
= input_line_pointer
;
6860 /* Look for BY or DO. */
6863 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6865 if (strncasecmp (input_line_pointer
, "BY", 2) == 0
6866 && ! is_part_of_name (input_line_pointer
[2]))
6868 endstop
= input_line_pointer
;
6870 input_line_pointer
+= 2;
6873 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6874 && (input_line_pointer
[2] == '.'
6875 || ! is_part_of_name (input_line_pointer
[2])))
6877 endstop
= input_line_pointer
;
6878 input_line_pointer
+= 2;
6881 ++input_line_pointer
;
6883 if (endstop
== NULL
)
6885 as_bad (_("missing do"));
6886 ignore_rest_of_line ();
6889 if (endstop
> endstart
6890 && (endstop
[-1] == ' ' || endstop
[-1] == '\t'))
6896 bystop
= bystart
+ 2;
6901 bystart
= input_line_pointer
;
6905 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
6907 if (strncasecmp (input_line_pointer
, "DO", 2) == 0
6908 && (input_line_pointer
[2] == '.'
6909 || ! is_part_of_name (input_line_pointer
[2])))
6911 bystop
= input_line_pointer
;
6912 input_line_pointer
+= 2;
6915 ++input_line_pointer
;
6919 as_bad (_("missing do"));
6920 ignore_rest_of_line ();
6923 if (bystop
> bystart
6924 && (bystop
[-1] == ' ' || bystop
[-1] == '\t'))
6928 if (*input_line_pointer
!= '.')
6932 extent
= input_line_pointer
[1];
6933 input_line_pointer
+= 2;
6936 /* We have fully parsed the FOR operands. Now build the loop. */
6937 n
= push_mri_control (mri_for
);
6939 buf
= XNEWVEC (char, 50 + (input_line_pointer
- varstart
));
6941 /* Move init,var. */
6948 *s
++ = TOLOWER (qual
);
6950 memcpy (s
, initstart
, initstop
- initstart
);
6951 s
+= initstop
- initstart
;
6953 memcpy (s
, varstart
, varstop
- varstart
);
6954 s
+= varstop
- varstart
;
6966 *s
++ = TOLOWER (qual
);
6968 memcpy (s
, endstart
, endstop
- endstart
);
6969 s
+= endstop
- endstart
;
6971 memcpy (s
, varstart
, varstop
- varstart
);
6972 s
+= varstop
- varstart
;
6977 ex
[0] = TOLOWER (extent
);
6980 sprintf (buf
, "blt%s %s", ex
, n
->bottom
);
6982 sprintf (buf
, "bgt%s %s", ex
, n
->bottom
);
6985 /* Put together the add or sub instruction used by ENDF. */
6993 *s
++ = TOLOWER (qual
);
6995 memcpy (s
, bystart
, bystop
- bystart
);
6996 s
+= bystop
- bystart
;
6998 memcpy (s
, varstart
, varstop
- varstart
);
6999 s
+= varstop
- varstart
;
7005 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7006 ++input_line_pointer
;
7009 demand_empty_rest_of_line ();
7012 /* Handle the MRI ENDF pseudo-op. */
7015 s_mri_endf (int ignore ATTRIBUTE_UNUSED
)
7017 if (mri_control_stack
== NULL
7018 || mri_control_stack
->type
!= mri_for
)
7020 as_bad (_("endf without for"));
7021 ignore_rest_of_line ();
7025 colon (mri_control_stack
->next
);
7027 mri_assemble (mri_control_stack
->incr
);
7029 sprintf (mri_control_stack
->incr
, "bra %s", mri_control_stack
->top
);
7030 mri_assemble (mri_control_stack
->incr
);
7032 free (mri_control_stack
->incr
);
7034 colon (mri_control_stack
->bottom
);
7040 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7041 ++input_line_pointer
;
7044 demand_empty_rest_of_line ();
7047 /* Handle the MRI REPEAT pseudo-op. */
7050 s_mri_repeat (int ignore ATTRIBUTE_UNUSED
)
7052 struct mri_control_info
*n
;
7054 n
= push_mri_control (mri_repeat
);
7058 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7059 ++input_line_pointer
;
7061 demand_empty_rest_of_line ();
7064 /* Handle the MRI UNTIL pseudo-op. */
7067 s_mri_until (int qual
)
7071 if (mri_control_stack
== NULL
7072 || mri_control_stack
->type
!= mri_repeat
)
7074 as_bad (_("until without repeat"));
7075 ignore_rest_of_line ();
7079 colon (mri_control_stack
->next
);
7081 for (s
= input_line_pointer
; ! is_end_of_line
[(unsigned char) *s
]; s
++)
7084 parse_mri_control_expression (s
, qual
, (const char *) NULL
,
7085 mri_control_stack
->top
, '\0');
7087 colon (mri_control_stack
->bottom
);
7089 input_line_pointer
= s
;
7095 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7096 ++input_line_pointer
;
7099 demand_empty_rest_of_line ();
7102 /* Handle the MRI WHILE pseudo-op. */
7105 s_mri_while (int qual
)
7109 struct mri_control_info
*n
;
7111 s
= input_line_pointer
;
7112 /* We only accept '*' as introduction of comments if preceded by white space
7113 or at first column of a line (I think this can't actually happen here?)
7114 This is important when assembling:
7115 while d0 <ne> 12(a0,d0*2) do
7116 while d0 <ne> #CONST*20 do. */
7117 while (! (is_end_of_line
[(unsigned char) *s
]
7120 && (s
== input_line_pointer
7122 || *(s
-1) == '\t'))))
7125 while (*s
== ' ' || *s
== '\t')
7127 if (s
- input_line_pointer
> 1
7130 if (s
- input_line_pointer
< 2
7131 || strncasecmp (s
- 1, "DO", 2) != 0)
7133 as_bad (_("missing do"));
7134 ignore_rest_of_line ();
7138 n
= push_mri_control (mri_while
);
7142 parse_mri_control_expression (s
- 1, qual
, (const char *) NULL
, n
->bottom
,
7143 s
[1] == '.' ? s
[2] : '\0');
7145 input_line_pointer
= s
+ 1;
7146 if (*input_line_pointer
== '.')
7147 input_line_pointer
+= 2;
7151 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7152 ++input_line_pointer
;
7155 demand_empty_rest_of_line ();
7158 /* Handle the MRI ENDW pseudo-op. */
7161 s_mri_endw (int ignore ATTRIBUTE_UNUSED
)
7165 if (mri_control_stack
== NULL
7166 || mri_control_stack
->type
!= mri_while
)
7168 as_bad (_("endw without while"));
7169 ignore_rest_of_line ();
7173 buf
= XNEWVEC (char, 20 + strlen (mri_control_stack
->next
));
7174 sprintf (buf
, "bra %s", mri_control_stack
->next
);
7178 colon (mri_control_stack
->bottom
);
7184 while (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7185 ++input_line_pointer
;
7188 demand_empty_rest_of_line ();
7191 /* Parse a .cpu directive. */
7194 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED
)
7201 as_bad (_("already assembled instructions"));
7202 ignore_rest_of_line ();
7206 name
= input_line_pointer
;
7207 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
7208 input_line_pointer
++;
7209 saved_char
= *input_line_pointer
;
7210 *input_line_pointer
= 0;
7212 m68k_set_cpu (name
, 1, 0);
7214 *input_line_pointer
= saved_char
;
7215 demand_empty_rest_of_line ();
7219 /* Parse a .arch directive. */
7222 s_m68k_arch (int ignored ATTRIBUTE_UNUSED
)
7229 as_bad (_("already assembled instructions"));
7230 ignore_rest_of_line ();
7234 name
= input_line_pointer
;
7235 while (*input_line_pointer
&& *input_line_pointer
!= ','
7236 && !ISSPACE (*input_line_pointer
))
7237 input_line_pointer
++;
7238 saved_char
= *input_line_pointer
;
7239 *input_line_pointer
= 0;
7241 if (m68k_set_arch (name
, 1, 0))
7243 /* Scan extensions. */
7246 *input_line_pointer
++ = saved_char
;
7247 if (!*input_line_pointer
|| ISSPACE (*input_line_pointer
))
7249 name
= input_line_pointer
;
7250 while (*input_line_pointer
&& *input_line_pointer
!= ','
7251 && !ISSPACE (*input_line_pointer
))
7252 input_line_pointer
++;
7253 saved_char
= *input_line_pointer
;
7254 *input_line_pointer
= 0;
7256 while (m68k_set_extension (name
, 1, 0));
7259 *input_line_pointer
= saved_char
;
7260 demand_empty_rest_of_line ();
7264 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7265 if none is found, the caller is responsible for emitting an error
7266 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7267 cpu name, if it begins with a '6' (possibly skipping an intervening
7268 'c'. We also allow a 'c' in the same place. if NEGATED is
7269 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7270 the option is indeed negated. */
7272 static const struct m68k_cpu
*
7273 m68k_lookup_cpu (const char *arg
, const struct m68k_cpu
*table
,
7274 int allow_m
, int *negated
)
7276 /* allow negated value? */
7281 if (arg
[0] == 'n' && arg
[1] == 'o' && arg
[2] == '-')
7288 /* Remove 'm' or 'mc' prefix from 68k variants. */
7295 else if (arg
[1] == 'c' && arg
[2] == '6')
7299 else if (arg
[0] == 'c' && arg
[1] == '6')
7302 for (; table
->name
; table
++)
7303 if (!strcmp (arg
, table
->name
))
7305 if (table
->alias
< -1 || table
->alias
> 1)
7306 as_bad (_("`%s' is deprecated, use `%s'"),
7307 table
->name
, table
[table
->alias
< 0 ? 1 : -1].name
);
7313 /* Set the cpu, issuing errors if it is unrecognized. */
7316 m68k_set_cpu (char const *name
, int allow_m
, int silent
)
7318 const struct m68k_cpu
*cpu
;
7320 cpu
= m68k_lookup_cpu (name
, m68k_cpus
, allow_m
, NULL
);
7325 as_bad (_("cpu `%s' unrecognized"), name
);
7332 /* Set the architecture, issuing errors if it is unrecognized. */
7335 m68k_set_arch (char const *name
, int allow_m
, int silent
)
7337 const struct m68k_cpu
*arch
;
7339 arch
= m68k_lookup_cpu (name
, m68k_archs
, allow_m
, NULL
);
7344 as_bad (_("architecture `%s' unrecognized"), name
);
7347 selected_arch
= arch
;
7351 /* Set the architecture extension, issuing errors if it is
7352 unrecognized, or invalid */
7355 m68k_set_extension (char const *name
, int allow_m
, int silent
)
7358 const struct m68k_cpu
*ext
;
7360 ext
= m68k_lookup_cpu (name
, m68k_extensions
, allow_m
, &negated
);
7365 as_bad (_("extension `%s' unrecognized"), name
);
7370 not_current_architecture
|= (ext
->control_regs
7371 ? *(unsigned *)ext
->control_regs
: ext
->arch
);
7373 current_architecture
|= ext
->arch
;
7378 Invocation line includes a switch not recognized by the base assembler.
7381 const char *md_shortopts
= "lSA:m:kQ:V";
7383 struct option md_longopts
[] = {
7384 #define OPTION_PIC (OPTION_MD_BASE)
7385 {"pic", no_argument
, NULL
, OPTION_PIC
},
7386 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7387 {"register-prefix-optional", no_argument
, NULL
,
7388 OPTION_REGISTER_PREFIX_OPTIONAL
},
7389 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7390 {"bitwise-or", no_argument
, NULL
, OPTION_BITWISE_OR
},
7391 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7392 {"base-size-default-16", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_16
},
7393 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7394 {"base-size-default-32", no_argument
, NULL
, OPTION_BASE_SIZE_DEFAULT_32
},
7395 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7396 {"disp-size-default-16", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_16
},
7397 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7398 {"disp-size-default-32", no_argument
, NULL
, OPTION_DISP_SIZE_DEFAULT_32
},
7399 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7400 {"pcrel", no_argument
, NULL
, OPTION_PCREL
},
7401 {NULL
, no_argument
, NULL
, 0}
7403 size_t md_longopts_size
= sizeof (md_longopts
);
7406 md_parse_option (int c
, const char *arg
)
7410 case 'l': /* -l means keep external to 2 bit offset
7411 rather than 16 bit one. */
7412 flag_short_refs
= 1;
7415 case 'S': /* -S means that jbsr's always turn into
7417 flag_long_jumps
= 1;
7420 case OPTION_PCREL
: /* --pcrel means never turn PC-relative
7421 branches into absolute jumps. */
7422 flag_keep_pcrel
= 1;
7428 break; /* -pic, Position Independent Code. */
7430 case OPTION_REGISTER_PREFIX_OPTIONAL
:
7431 flag_reg_prefix_optional
= 1;
7432 reg_prefix_optional_seen
= 1;
7435 /* -V: SVR4 argument to print version ID. */
7437 print_version_id ();
7440 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7441 should be emitted or not. FIXME: Not implemented. */
7445 case OPTION_BITWISE_OR
:
7450 n
= XNEWVEC (char, strlen (m68k_comment_chars
) + 1);
7452 for (s
= m68k_comment_chars
; *s
!= '\0'; s
++)
7456 m68k_comment_chars
= n
;
7460 case OPTION_BASE_SIZE_DEFAULT_16
:
7461 m68k_index_width_default
= SIZE_WORD
;
7464 case OPTION_BASE_SIZE_DEFAULT_32
:
7465 m68k_index_width_default
= SIZE_LONG
;
7468 case OPTION_DISP_SIZE_DEFAULT_16
:
7470 m68k_rel32_from_cmdline
= 1;
7473 case OPTION_DISP_SIZE_DEFAULT_32
:
7475 m68k_rel32_from_cmdline
= 1;
7480 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7483 /* Intentional fall-through. */
7485 if (!strncmp (arg
, "arch=", 5))
7486 m68k_set_arch (arg
+ 5, 1, 0);
7487 else if (!strncmp (arg
, "cpu=", 4))
7488 m68k_set_cpu (arg
+ 4, 1, 0);
7489 else if (m68k_set_extension (arg
, 0, 1))
7491 else if (m68k_set_arch (arg
, 0, 1))
7493 else if (m68k_set_cpu (arg
, 0, 1))
7506 /* Setup tables from the selected arch and/or cpu */
7509 m68k_init_arch (void)
7511 if (not_current_architecture
& current_architecture
)
7513 as_bad (_("architecture features both enabled and disabled"));
7514 not_current_architecture
&= ~current_architecture
;
7518 current_architecture
|= selected_arch
->arch
;
7519 control_regs
= selected_arch
->control_regs
;
7522 current_architecture
|= selected_cpu
->arch
;
7524 current_architecture
&= ~not_current_architecture
;
7526 if ((current_architecture
& (cfloat
| m68881
)) == (cfloat
| m68881
))
7528 /* Determine which float is really meant. */
7529 if (current_architecture
& (m68k_mask
& ~m68881
))
7530 current_architecture
^= cfloat
;
7532 current_architecture
^= m68881
;
7537 control_regs
= selected_cpu
->control_regs
;
7538 if (current_architecture
& ~selected_cpu
->arch
)
7540 as_bad (_("selected processor does not have all features of selected architecture"));
7541 current_architecture
7542 = selected_cpu
->arch
& ~not_current_architecture
;
7546 if ((current_architecture
& m68k_mask
)
7547 && (current_architecture
& ~m68k_mask
))
7549 as_bad (_ ("m68k and cf features both selected"));
7550 if (current_architecture
& m68k_mask
)
7551 current_architecture
&= m68k_mask
;
7553 current_architecture
&= ~m68k_mask
;
7556 /* Permit m68881 specification with all cpus; those that can't work
7557 with a coprocessor could be doing emulation. */
7558 if (current_architecture
& m68851
)
7560 if (current_architecture
& m68040
)
7561 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7563 /* What other incompatibilities could we check for? */
7565 if (cpu_of_arch (current_architecture
) < m68020
7566 || arch_coldfire_p (current_architecture
))
7567 md_relax_table
[TAB (PCINDEX
, BYTE
)].rlx_more
= 0;
7573 md_show_usage (FILE *stream
)
7575 const char *default_cpu
= TARGET_CPU
;
7578 /* Get the canonical name for the default target CPU. */
7579 if (*default_cpu
== 'm')
7581 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7583 if (strcasecmp (default_cpu
, m68k_cpus
[i
].name
) == 0)
7585 while (m68k_cpus
[i
].alias
> 0)
7587 while (m68k_cpus
[i
].alias
< 0)
7589 default_cpu
= m68k_cpus
[i
].name
;
7593 fprintf (stream
, _("\
7594 -march=<arch> set architecture\n\
7595 -mcpu=<cpu> set cpu [default %s]\n\
7597 for (i
= 0; m68k_extensions
[i
].name
; i
++)
7598 fprintf (stream
, _("\
7599 -m[no-]%-16s enable/disable %s architecture extension\n\
7600 "), m68k_extensions
[i
].name
,
7601 m68k_extensions
[i
].alias
> 0 ? " ColdFire"
7602 : m68k_extensions
[i
].alias
< 0 ? " m68k" : "");
7604 fprintf (stream
, _("\
7605 -l use 1 word for refs to undefined symbols [default 2]\n\
7606 -pic, -k generate position independent code\n\
7607 -S turn jbsr into jsr\n\
7608 --pcrel never turn PC-relative branches into absolute jumps\n\
7609 --register-prefix-optional\n\
7610 recognize register names without prefix character\n\
7611 --bitwise-or do not treat `|' as a comment character\n\
7612 --base-size-default-16 base reg without size is 16 bits\n\
7613 --base-size-default-32 base reg without size is 32 bits (default)\n\
7614 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7615 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7618 fprintf (stream
, _("Architecture variants are: "));
7619 for (i
= 0; m68k_archs
[i
].name
; i
++)
7622 fprintf (stream
, " | ");
7623 fprintf (stream
, "%s", m68k_archs
[i
].name
);
7625 fprintf (stream
, "\n");
7627 fprintf (stream
, _("Processor variants are: "));
7628 for (i
= 0; m68k_cpus
[i
].name
; i
++)
7631 fprintf (stream
, " | ");
7632 fprintf (stream
, "%s", m68k_cpus
[i
].name
);
7634 fprintf (stream
, _("\n"));
7639 /* TEST2: Test md_assemble() */
7640 /* Warning, this routine probably doesn't work anymore. */
7644 struct m68k_it the_ins
;
7652 if (!gets (buf
) || !*buf
)
7654 if (buf
[0] == '|' || buf
[1] == '.')
7656 for (cp
= buf
; *cp
; cp
++)
7661 memset (&the_ins
, '\0', sizeof (the_ins
));
7662 m68k_ip (&the_ins
, buf
);
7665 printf (_("Error %s in %s\n"), the_ins
.error
, buf
);
7669 printf (_("Opcode(%d.%s): "), the_ins
.numo
, the_ins
.args
);
7670 for (n
= 0; n
< the_ins
.numo
; n
++)
7671 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
7673 print_the_insn (&the_ins
.opcode
[0], stdout
);
7674 (void) putchar ('\n');
7676 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
7678 if (the_ins
.operands
[n
].error
)
7680 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
7683 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
,
7684 the_ins
.operands
[n
].reg
);
7685 if (the_ins
.operands
[n
].b_const
)
7686 printf ("Constant: '%.*s', ",
7687 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
,
7688 the_ins
.operands
[n
].b_const
);
7689 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
,
7690 the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
7691 if (the_ins
.operands
[n
].b_iadd
)
7692 printf ("Iadd: '%.*s',",
7693 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
,
7694 the_ins
.operands
[n
].b_iadd
);
7703 is_label (char *str
)
7707 while (*str
&& *str
!= ' ')
7709 if (str
[-1] == ':' || str
[1] == '=')
7716 /* Possible states for relaxation:
7718 0 0 branch offset byte (bra, etc)
7722 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7726 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7733 /* We have no need to default values of symbols. */
7736 md_undefined_symbol (char *name ATTRIBUTE_UNUSED
)
7741 /* Round up a section size to the appropriate boundary. */
7743 md_section_align (segT segment ATTRIBUTE_UNUSED
, valueT size
)
7748 /* Exactly what point is a PC-relative offset relative TO?
7749 On the 68k, it is relative to the address of the first extension
7750 word. The difference between the addresses of the offset and the
7751 first extension word is stored in fx_pcrel_adjust. */
7753 md_pcrel_from (fixS
*fixP
)
7757 adjust
= fixP
->fx_pcrel_adjust
;
7760 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
- adjust
;
7764 m68k_elf_final_processing (void)
7768 if (arch_coldfire_fpu (current_architecture
))
7769 flags
|= EF_M68K_CFV4E
;
7770 /* Set file-specific flags if this is a cpu32 processor. */
7771 if (cpu_of_arch (current_architecture
) & cpu32
)
7772 flags
|= EF_M68K_CPU32
;
7773 else if (cpu_of_arch (current_architecture
) & fido_a
)
7774 flags
|= EF_M68K_FIDO
;
7775 else if ((cpu_of_arch (current_architecture
) & m68000up
)
7776 && !(cpu_of_arch (current_architecture
) & m68020up
))
7777 flags
|= EF_M68K_M68000
;
7779 if (current_architecture
& mcfisa_a
)
7781 static const unsigned isa_features
[][2] =
7783 {EF_M68K_CF_ISA_A_NODIV
,mcfisa_a
},
7784 {EF_M68K_CF_ISA_A
, mcfisa_a
|mcfhwdiv
},
7785 {EF_M68K_CF_ISA_A_PLUS
, mcfisa_a
|mcfisa_aa
|mcfhwdiv
|mcfusp
},
7786 {EF_M68K_CF_ISA_B_NOUSP
,mcfisa_a
|mcfisa_b
|mcfhwdiv
},
7787 {EF_M68K_CF_ISA_B
, mcfisa_a
|mcfisa_b
|mcfhwdiv
|mcfusp
},
7788 {EF_M68K_CF_ISA_C
, mcfisa_a
|mcfisa_c
|mcfhwdiv
|mcfusp
},
7789 {EF_M68K_CF_ISA_C_NODIV
,mcfisa_a
|mcfisa_c
|mcfusp
},
7792 static const unsigned mac_features
[][2] =
7794 {EF_M68K_CF_MAC
, mcfmac
},
7795 {EF_M68K_CF_EMAC
, mcfemac
},
7801 pattern
= (current_architecture
7802 & (mcfisa_a
|mcfisa_aa
|mcfisa_b
|mcfisa_c
|mcfhwdiv
|mcfusp
));
7803 for (ix
= 0; isa_features
[ix
][1]; ix
++)
7805 if (pattern
== isa_features
[ix
][1])
7807 flags
|= isa_features
[ix
][0];
7811 if (!isa_features
[ix
][1])
7814 as_warn (_("Not a defined coldfire architecture"));
7818 if (current_architecture
& cfloat
)
7819 flags
|= EF_M68K_CF_FLOAT
| EF_M68K_CFV4E
;
7821 pattern
= current_architecture
& (mcfmac
|mcfemac
);
7824 for (ix
= 0; mac_features
[ix
][1]; ix
++)
7826 if (pattern
== mac_features
[ix
][1])
7828 flags
|= mac_features
[ix
][0];
7832 if (!mac_features
[ix
][1])
7837 elf_elfheader (stdoutput
)->e_flags
|= flags
;
7840 /* Parse @TLSLDO and return the desired relocation. */
7841 static bfd_reloc_code_real_type
7842 m68k_elf_suffix (char **str_p
, expressionS
*exp_p
)
7851 return BFD_RELOC_UNUSED
;
7853 for (ch
= *str
, str2
= ident
;
7854 (str2
< ident
+ sizeof (ident
) - 1
7855 && (ISALNUM (ch
) || ch
== '@'));
7864 if (strncmp (ident
, "TLSLDO", 6) == 0
7867 /* Now check for identifier@suffix+constant. */
7868 if (*str
== '-' || *str
== '+')
7870 char *orig_line
= input_line_pointer
;
7871 expressionS new_exp
;
7873 input_line_pointer
= str
;
7874 expression (&new_exp
);
7875 if (new_exp
.X_op
== O_constant
)
7877 exp_p
->X_add_number
+= new_exp
.X_add_number
;
7878 str
= input_line_pointer
;
7881 if (&input_line_pointer
!= str_p
)
7882 input_line_pointer
= orig_line
;
7886 return BFD_RELOC_68K_TLS_LDO32
;
7889 return BFD_RELOC_UNUSED
;
7892 /* Handles .long <tls_symbol>+0x8000 debug info.
7893 Clobbers input_line_pointer, checks end-of-line.
7894 Adapted from tc-ppc.c:ppc_elf_cons. */
7896 m68k_elf_cons (int nbytes
/* 4=.long */)
7898 if (is_it_end_of_statement ())
7900 demand_empty_rest_of_line ();
7907 bfd_reloc_code_real_type reloc
;
7910 if (exp
.X_op
== O_symbol
7911 && *input_line_pointer
== '@'
7912 && (reloc
= m68k_elf_suffix (&input_line_pointer
,
7913 &exp
)) != BFD_RELOC_UNUSED
)
7915 reloc_howto_type
*reloc_howto
;
7918 reloc_howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
7919 size
= bfd_get_reloc_size (reloc_howto
);
7923 as_bad (ngettext ("%s relocations do not fit in %u byte",
7924 "%s relocations do not fit in %u bytes",
7926 reloc_howto
->name
, nbytes
);
7933 p
= frag_more (nbytes
);
7935 if (target_big_endian
)
7936 offset
= nbytes
- size
;
7937 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
7942 emit_expr (&exp
, (unsigned int) nbytes
);
7944 while (*input_line_pointer
++ == ',');
7946 /* Put terminator back into stream. */
7947 input_line_pointer
--;
7948 demand_empty_rest_of_line ();
7951 /* Parse a .gnu_attribute directive. */
7953 m68k_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED
)
7955 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_GNU
);
7957 /* Check validity of defined m68k tags. */
7958 if (tag
== Tag_GNU_M68K_ABI_FP
)
7962 val
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
, tag
);
7964 if (tag
== Tag_GNU_M68K_ABI_FP
&& val
> 2)
7965 as_warn (_("unknown .gnu_attribute value"));
7970 tc_m68k_regname_to_dw2regnum (const char *regname
)
7972 unsigned int regnum
;
7973 static const char *const regnames
[] =
7975 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7976 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7977 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7981 for (regnum
= 0; regnum
< ARRAY_SIZE (regnames
); regnum
++)
7982 if (strcmp (regname
, regnames
[regnum
]) == 0)
7989 tc_m68k_frame_initial_instructions (void)
7991 static int sp_regno
= -1;
7994 sp_regno
= tc_m68k_regname_to_dw2regnum ("sp");
7996 cfi_add_CFA_def_cfa (sp_regno
, -DWARF2_CIE_DATA_ALIGNMENT
);
7997 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN
, DWARF2_CIE_DATA_ALIGNMENT
);
8000 /* Check and emit error if broken-word handling has failed to fix up a
8001 case-table. This is called from write.c, after doing everything it
8002 knows about how to handle broken words. */
8005 tc_m68k_check_adjusted_broken_word (offsetT new_offset
, struct broken_word
*brokwP
)
8007 if (new_offset
> 32767 || new_offset
< -32768)
8008 as_bad_where (brokwP
->frag
->fr_file
, brokwP
->frag
->fr_line
,
8009 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),