1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
29 /* note that this file includes real declarations and thus can only be included by one source file per executable. */
30 #include "opcode/m68k.h"
33 /* This variable contains the value to write out at the beginning of
34 the a.out file. The 2<<16 means that this is a 68020 file instead
35 of an old-style 68000 file */
37 long omagic
= 2<<16|OMAGIC
; /* Magic byte for header file */
42 /* This array holds the chars that always start a comment. If the
43 pre-processor is disabled, these aren't very useful */
44 const char comment_chars
[] = "|";
46 /* This array holds the chars that only start a comment at the beginning of
47 a line. If the line seems to have the form '# 123 filename'
48 .line and .file directives will appear in the pre-processed output */
49 /* Note that input_file.c hand checks for '#' at the beginning of the
50 first line of the input file. This is because the compiler outputs
51 #NO_APP at the beginning of its output. */
52 /* Also note that comments like this one will always work. */
53 const char line_comment_chars
[] = "#";
55 const char line_separator_chars
[] = "";
57 /* Chars that can be used to separate mant from exp in floating point nums */
58 const char EXP_CHARS
[] = "eE";
60 /* Chars that mean this number is a floating point constant */
64 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
66 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
67 changed in read.c . Ideally it shouldn't have to know about it at all,
68 but nothing is ideal around here.
71 int md_reloc_size
= 8; /* Size of relocation record */
73 /* Its an arbitrary name: This means I don't approve of it */
74 /* See flames below */
75 static struct obstack robyn
;
77 #define TAB(x,y) (((x)<<2)+(y))
78 #define TABTYPE(xy) ((xy) >> 2)
91 /* Operands we can parse: (And associated modes)
97 reg: address or data register
98 areg: address register
99 apc: address register, PC, ZPC or empty string
100 num: 16 or 32 bit num
102 sz: w or l if omitted, l assumed
103 scale: 1 2 4 or 8 if omitted, 1 assumed
105 7.4 IMMED #num --> NUM
106 0.? DREG dreg --> dreg
107 1.? AREG areg --> areg
108 2.? AINDR areg@ --> *(areg)
109 3.? AINC areg@+ --> *(areg++)
110 4.? ADEC areg@- --> *(--areg)
111 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
112 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
113 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
114 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
115 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
116 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
117 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
118 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
119 7.0 ABSL num:sz --> *(num)
120 num --> *(num) (sz L assumed)
121 *** MSCR otherreg --> Magic
123 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
124 ?.? DINDR dreg@ --> (dreg) -- cas2 only
134 a1@(5,d2:w:1) @(45,d6:l:4)
139 #name@(numw) -->turn into PC rel mode
140 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
167 short e_siz
; /* 0== default 1==short/byte 2==word 3==long */
170 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
171 8-15==addr reg for operands that take both types */
174 DATA
= 1, /* 1- 8 == data registers 0-7 */
194 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
199 FPREG
, /* Eight FP registers */
208 COPNUM
= (FPREG
+8), /* Co-processor #1-#8 */
217 PC
, /* Program counter */
218 ZPC
, /* Hack for Program space, but 0 addressing */
220 CCR
, /* Condition code Reg */
222 /* These have to be in order for the movec instruction to work. */
223 USP
, /* User Stack Pointer */
224 ISP
, /* Interrupt stack pointer */
239 /* end of movec ordering constraints */
245 DRP
, /* 68851 or 68030 MMU regs */
269 PSR
, /* aka MMUSR on 68030 (but not MMUSR on 68040)
270 and ACUSR on 68ec030 */
273 IC
, /* instruction cache token */
274 DC
, /* data cache token */
275 NC
, /* no cache token */
276 BC
, /* both caches token */
278 TT0
, /* 68030 access control unit regs */
282 /* Internal form of an operand. */
284 char *error
; /* Couldn't parse it */
285 enum operand_type mode
; /* What mode this instruction is in. */
286 enum _register reg
; /* Base register */
287 struct m68k_exp
*con1
;
288 int ireg
; /* Index register */
289 int isiz
; /* 0==unspec 1==byte(?) 2==short 3==long */
290 int imul
; /* Multipy ireg by this (1,2,4,or 8) */
291 struct m68k_exp
*con2
;
294 /* internal form of a 68020 instruction */
297 char *args
; /* list of opcode info */
300 int numo
; /* Number of shorts in opcode */
303 struct m68k_op operands
[6];
305 int nexp
; /* number of exprs in use */
306 struct m68k_exp exprs
[4];
308 int nfrag
; /* Number of frags we have to produce */
310 int fragoff
; /* Where in the current opcode[] the frag ends */
316 int nrel
; /* Num of reloc strucs in use */
324 } reloc
[5]; /* Five is enough??? */
327 #define cpu_of_arch(x) ((x) & m68000up)
328 #define float_of_arch(x) ((x) & mfloat)
329 #define mmu_of_arch(x) ((x) & mmmu)
331 static struct m68k_it the_ins
; /* the instruction being assembled */
333 /* Macros for adding things to the m68k_it struct */
335 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
337 /* Like addword, but goes BEFORE general operands */
338 #define insop(w) {int z;\
339 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
340 the_ins.opcode[z]=the_ins.opcode[z-1];\
341 for(z=0;z<the_ins.nrel;z++)\
342 the_ins.reloc[z].n+=2;\
343 the_ins.opcode[opcode->m_codenum]=w;\
348 #define add_exp(beg,end) (\
349 the_ins.exprs[the_ins.nexp].e_beg=beg,\
350 the_ins.exprs[the_ins.nexp].e_end=end,\
351 &the_ins.exprs[the_ins.nexp++]\
355 /* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/
356 #define add_fix(width,exp,pc_rel) {\
357 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \
358 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\
359 the_ins.reloc[the_ins.nrel].add=adds((exp));\
360 the_ins.reloc[the_ins.nrel].sub=subs((exp));\
361 the_ins.reloc[the_ins.nrel].off=offs((exp));\
362 the_ins.reloc[the_ins.nrel].wid=width;\
363 the_ins.reloc[the_ins.nrel++].pcrel=pc_rel;\
366 #define add_frag(add,off,type) {\
367 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\
368 the_ins.fragb[the_ins.nfrag].fadd=add;\
369 the_ins.fragb[the_ins.nfrag].foff=off;\
370 the_ins.fragb[the_ins.nfrag++].fragty=type;\
373 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
375 #define seg(exp) ((exp)->e_exp.X_seg)
376 #define adds(exp) ((exp)->e_exp.X_add_symbol)
377 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
378 #define offs(exp) ((exp)->e_exp.X_add_number)
383 unsigned long m_opcode
;
387 struct m68k_incant
*m_next
;
392 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
393 #define gettwo(x) (((x)->m_opcode)&0xffff)
398 static char *crack_operand(char *str
, struct m68k_op
*opP
);
399 static int get_num(struct m68k_exp
*exp
, int ok
);
400 static int get_regs(int i
, char *str
, struct m68k_op
*opP
);
401 static int reverse_16_bits(int in
);
402 static int reverse_8_bits(int in
);
403 static int try_index(char **s
, struct m68k_op
*opP
);
404 static void install_gen_operand(int mode
, int val
);
405 static void install_operand(int mode
, int val
);
406 static void s_bss(void);
407 static void s_data1(void);
408 static void s_data2(void);
409 static void s_even(void);
410 static void s_proc(void);
412 #else /* not __STDC__ */
414 static char *crack_operand();
415 static int get_num();
416 static int get_regs();
417 static int reverse_16_bits();
418 static int reverse_8_bits();
419 static int try_index();
420 static void install_gen_operand();
421 static void install_operand();
423 void s_align_bytes();
424 static void s_data1();
425 static void s_data2();
426 static void s_even();
427 static void s_proc();
429 #endif /* not __STDC__ */
431 static int current_architecture
= 0;
433 /* BCC68000 is for patching in an extra jmp instruction for long offsets
434 on the 68000. The 68000 doesn't support long branches with branchs */
436 /* This table desribes how you change sizes for the various types of variable
437 size expressions. This version only supports two kinds. */
439 /* Note that calls to frag_var need to specify the maximum expansion needed */
440 /* This is currently 10 bytes for DBCC */
443 How far Forward this mode will reach:
444 How far Backward this mode will reach:
445 How many bytes this mode will add to the size of the frag
446 Which mode to go to if the offset won't fit in this one
450 { 1, 1, 0, 0 }, /* First entries aren't used */
451 { 1, 1, 0, 0 }, /* For no good reason except */
452 { 1, 1, 0, 0 }, /* that the VAX doesn't either */
455 { (127), (-128), 0, TAB(ABRANCH
,SHORT
)},
456 { (32767), (-32768), 2, TAB(ABRANCH
,LONG
) },
460 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */
461 { (32767), (-32768), 2, TAB(FBRANCH
,LONG
)},
465 { 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */
466 { (32767), (-32768), 2, TAB(PCREL
,LONG
)},
470 { (127), (-128), 0, TAB(BCC68000
,SHORT
)},
471 { (32767), (-32768), 2, TAB(BCC68000
,LONG
) },
472 { 0, 0, 6, 0 }, /* jmp long space */
475 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */
476 { (32767), (-32768), 2, TAB(DBCC
,LONG
) },
477 { 0, 0, 10, 0 }, /* bra/jmp long space */
480 { 1, 1, 0, 0 }, /* PCLEA doesn't come BYTE */
481 { 32767, -32768, 2, TAB(PCLEA
,LONG
) },
487 /* These are the machine dependent pseudo-ops. These are included so
488 the assembler can work on the output from the SUN C compiler, which
492 /* This table describes all the machine specific pseudo-ops the assembler
493 has to support. The fields are:
494 pseudo-op name without dot
495 function to call to execute this pseudo-op
496 Integer arg to pass to the function
498 const pseudo_typeS md_pseudo_table
[] = {
499 { "data1", s_data1
, 0 },
500 { "data2", s_data2
, 0 },
502 { "even", s_even
, 0 },
503 { "skip", s_space
, 0 },
504 { "proc", s_proc
, 0 },
506 { "align", s_align_bytes
, 0 },
512 /* The mote pseudo ops are put into the opcode table, since they
513 don't start with a . they look like opcodes to gas.
515 extern void obj_coff_section();
517 const pseudo_typeS mote_pseudo_table
[] =
525 { "ds.l", s_space
,4},
527 { "ds.w", s_space
,2},
528 { "ds.b", s_space
,1},
530 { "xdef", s_globl
, 0},
531 { "align", s_align_ptwo
, 0},
533 { "sect", obj_coff_section
,0},
534 { "section", obj_coff_section
,0},
539 /* #define isbyte(x) ((x)>=-128 && (x)<=127) */
540 /* #define isword(x) ((x)>=-32768 && (x)<=32767) */
542 #define issbyte(x) ((x)>=-128 && (x)<=127)
543 #define isubyte(x) ((x)>=0 && (x)<=255)
544 #define issword(x) ((x)>=-32768 && (x)<=32767)
545 #define isuword(x) ((x)>=0 && (x)<=65535)
547 #define isbyte(x) ((x)>=-128 && (x)<=255)
548 #define isword(x) ((x)>=-32768 && (x)<=65535)
549 #define islong(x) (1)
551 extern char *input_line_pointer
;
558 /* JF these tables here are for speed at the expense of size */
559 /* You can replace them with the #if 0 versions if you really
560 need space and don't mind it running a bit slower */
562 static char mklower_table
[256];
563 #define mklower(c) (mklower_table[(unsigned char)(c)])
564 static char notend_table
[256];
565 static char alt_notend_table
[256];
566 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
567 alt_notend_table[(unsigned char)(s[1])])))
570 #define mklower(c) (isupper(c) ? tolower(c) : c)
574 /* JF modified this to handle cases where the first part of a symbol name
575 looks like a register */
578 * m68k_reg_parse() := if it looks like a register, return it's token &
579 * advance the pointer.
582 enum _register
m68k_reg_parse(ccp
)
590 #ifdef REGISTER_PREFIX
591 if (*start
!= REGISTER_PREFIX
)
596 if (*p
== OPTIONAL_REGISTER_PREFIX
)
599 if (!isalpha (*p
) || !is_name_beginner (*p
))
603 while (isalpha(c
) || isdigit(c
) || c
== '_')
609 symbolP
= symbol_find(start
);
612 if (symbolP
&& S_GET_SEGMENT(symbolP
) == SEG_REGISTER
)
615 return S_GET_VALUE(symbolP
);
621 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
622 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
624 /* Parse an index specification using Motorola syntax. */
627 try_moto_index(s
,opP
)
637 i
=m68k_reg_parse(&ss
);
638 if(!(i
>=DATA
+0 && i
<=ADDR
+7)) { /* if i is not DATA or ADDR reg */
639 opP
->error
="Invalid index register";
653 opP
->error
="Missing . in index register";
658 if(mklower(*ss
)=='w') opP
->isiz
=2;
659 else if(mklower(*ss
)=='l') opP
->isiz
=3;
661 opP
->error
="Size spec not .W or .L";
666 if(*ss
=='.' || *ss
=='*') {
676 opP
->error
="index multiplier not 1, 2, 4 or 8";
683 opP
->error
="Missing )";
694 * try_index := data_or_address_register + ')' + SKIP_W
695 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
697 * multiplier := <empty>
698 * | ':' + multiplier_number
701 * multiplier_number := '1' | '2' | '4' | '8' ;
703 * size_spec := 'l' | 'L' | 'w' | 'W' ;
705 * SKIP_W := <empty> | ' ' ;
709 static int try_index(s
,opP
)
718 i
=m68k_reg_parse(&ss
);
719 if(!(i
>=DATA
+0 && i
<=ADDR
+7)) { /* if i is not DATA or ADDR reg */
733 opP
->error
="Missing : in index register";
748 opP
->error
="Index register size spec not :w or :l";
760 if (cpu_of_arch(current_architecture
) < m68020
) {
761 opP
->error
="no index scaling in pre-68020's";
768 opP
->error
="index multiplier not 1, 2, 4 or 8";
775 opP
->error
="Missing )";
784 /* Ian Taylor expanded this function to accept both MIT and Motorola
785 syntax. I removed the old comment, since it was wrong. The syntax
786 this accepted even before my changes was complex and undocumented.
787 I mainly added a large case when the operand string does not
788 contain an '@', since the Motorola syntax does not use the '@'
794 register struct m68k_op
*opP
;
803 } /* Find the beginning of the string */
806 opP
->error
="Missing operand";
810 for(strend
= str
; *strend
; strend
++)
816 opP
->con1
=add_exp(str
,strend
);
819 } /* Guess what: A constant. Shar and enjoy */
821 i
= m68k_reg_parse(&str
);
824 if(*str
=='/' || *str
=='-') {
825 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
827 return get_regs(i
,str
,opP
);
831 /* "Rn" Register Direct mode */
832 if(i
>=DATA
+0 && i
<=DATA
+7)
834 else if(i
>=ADDR
+0 && i
<=ADDR
+7)
845 if ((stmp
=strchr(str
,'@')) != 0) {
846 opP
->con1
=add_exp(str
,stmp
-1);
852 if ((current_architecture
& m68020up
) == 0) {
854 } /* if target is not a '20 or better */
857 if(*stmp
++!='(' || *strend
--!=')') {
858 opP
->error
="Malformed operand";
861 i
=try_index(&stmp
,opP
);
862 opP
->con2
=add_exp(stmp
,strend
);
870 } /* if there's an '@' */
872 #ifndef MIT_SYNTAX_ONLY
873 /* The operand has no '@'. Try to parse it using
875 /* Logic of the parsing switch(*str):
879 REG AREG or DREG or MSCR 3 or 2 or 13
880 REG- or REG/ REGLST 14
885 (EXPR,REG,INDX) AINDX 8
888 EXP2(REG,INDX) AINDX 8
891 REG means truth(m68k_reg_parse(&str))
892 INDX means truth(try_moto_index(&str,opP))
894 EXP2 means not REG and not '(' and not '-('
899 i
=m68k_reg_parse(&str
);
900 if((i
<ADDR
+0 || i
>ADDR
+7)
901 && (i
<DATA
+0 || i
>DATA
+7
902 || *str
!= ')' || str
[1] != '0')
903 && i
!=PC
&& i
!=ZPC
&& i
!=FAIL
) {
904 /* Can't indirect off non address regs */
905 opP
->error
="Invalid indirect register";
913 /* "(An)" Address Register Indirect mode
914 or "(Dn)" for cas2. */
915 if (i
>=DATA
+0 && i
<=DATA
+7)
923 /* "(An)+" Register Indirect w Postincrement */
928 opP
->error
="Junk after indirect";
933 i
=try_moto_index(&str
,opP
);
934 if(i
==FAIL
) return FAIL
;
935 /* "(An,Rn)" Register Indirect with Index mode*/
940 opP
->error
="Bad indirect syntax";
945 /* "(EXPR,..." , a displacement */
949 if(stmp
=index(str
,',')) {
950 opP
->con1
=add_exp(str
,stmp
-1);
953 i
=m68k_reg_parse(&str
);
954 if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
&& i
!=ZPC
) {
955 /* Can't indirect off non address regs */
956 opP
->error
="Invalid indirect register";
962 /* "(d,An)" Register Indirect w Displacement */
968 i
=try_moto_index(&str
,opP
);
969 if(i
==FAIL
) return FAIL
;
970 /* "(d,An,Rn)" Register Indirect with Index */
975 opP
->error
="Bad indirect syntax";
980 opP
->error
="Invalid register";
986 opP
->con1
= add_exp(str
-1,strend
);
995 i
=m68k_reg_parse(&str
);
996 if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
&& i
!=ZPC
&& i
!=FAIL
) {
997 /* Can't indirect off non address regs */
998 opP
->error
="Invalid indirect register";
1006 /* "-(An)" Register Indirect with Predecrement */
1010 opP
->error
="Junk after indirect";
1013 opP
->error
="Bad indirect syntax";
1017 opP
->con1
= add_exp(str
-2,strend
);
1020 /* if '-' but not "-(', do nothing */
1023 /* whether *str=='-' or not */
1025 /* "EXP2" or "EXP2(REG..." */
1028 if(stmp
=index(str
,'(')) {
1031 opP
->con1
=add_exp(str
,stmp
-1);
1033 i
=m68k_reg_parse(&str
);
1034 if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
1035 && i
!=ZPC
&& i
!=FAIL
) {
1036 /* Can't indirect off non address regs */
1037 opP
->error
="Invalid indirect register";
1043 /* "d(An)" Register Indirect w Displacement */
1049 i
=try_moto_index(&str
,opP
);
1050 if(i
==FAIL
) return FAIL
;
1051 /* "d(An,Rn)" Register Indirect with Index */
1056 opP
->error
="Bad indirect syntax";
1062 opP
->con1
= add_exp(ostr
,strend
);
1067 /* "EXP2" Absolute */
1070 if(strend
[-1]=='.' || strend
[-1]==':') {
1071 /* mode ==foo.[wl] */
1085 opP
->con1
=add_exp(str
,strend
);
1090 #else /* defined (MIT_SYNTAX_ONLY) */
1092 opP
->con1
=add_exp(str
,strend
);
1094 #endif /* defined (MIT_SYNTAX_ONLY) */
1099 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1100 if((i
<ADDR
+0 || i
>ADDR
+7) && i
!=PC
&& i
!=ZPC
&& i
!=FAIL
1101 && (str
[1] != '\0' || i
<DATA
+0 || i
>DATA
+7)) {
1102 opP
->error
="Invalid indirect register";
1110 if (i
<DATA
+0 || i
>DATA
+7)
1125 opP
->error
="Junk after indirect";
1128 /* Some kind of indexing involved. Lets find out how bad it is */
1129 i
=try_index(&str
,opP
);
1130 /* Didn't start with an index reg, maybe its offset or offset,reg */
1138 opP
->error
="Missing )";
1140 case ',': i
=0; break;
1141 case '(': i
++; break;
1142 case ')': --i
; break;
1145 /* if(str[-3]==':') {
1162 opP->error="Specified size isn't :w or :l";
1165 opP->con1=add_exp(beg_str,str-4);
1166 opP->con1->e_siz=siz;
1168 opP
->con1
=add_exp(beg_str
,str
-2);
1169 /* Should be offset,reg */
1171 i
=try_index(&str
,opP
);
1173 opP
->error
="Malformed index reg";
1178 /* We've now got offset) offset,reg) or reg) */
1181 /* Th-the-thats all folks */
1182 if (opP
->reg
== FAIL
) opP
->mode
= AINDX
; /* Other form of indirect */
1183 else if(opP
->ireg
== FAIL
) opP
->mode
= AOFF
;
1184 else opP
->mode
= AINDX
;
1187 /* Next thing had better be another @ */
1189 if (str
[1] == '(') {
1199 if ((current_architecture
& m68020up
) == 0) {
1201 } /* if target is not a '20 or better */
1204 if(opP
->ireg
!= FAIL
) {
1207 i
= try_index(&str
, opP
);
1209 opP
->error
= "Two index registers! not allowed!";
1213 i
= try_index(&str
, opP
);
1225 opP
->error
="Missing )";
1228 case ',': i
=0; break;
1229 case '(': i
++; break;
1230 case ')': --i
; break;
1234 opP
->con2
=add_exp(beg_str
,str
-2);
1236 if (str
[-1] == ',') {
1237 if (opP
->ireg
!= FAIL
) {
1238 opP
->error
= "Can't have two index regs";
1242 i
= try_index(&str
, opP
);
1245 opP
->error
= "malformed index reg";
1250 } else if (opP
->ireg
!= FAIL
) {
1260 opP
->error
="Junk after indirect";
1264 } /* m68k_ip_op() */
1269 short tc_coff_fix2rtype(fixP
)
1272 return (fixP
->fx_pcrel
?
1273 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
1274 fixP
->fx_size
== 2 ? R_PCRWORD
:
1276 (fixP
->fx_size
== 1 ? R_RELBYTE
:
1277 fixP
->fx_size
== 2 ? R_RELWORD
:
1285 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1289 struct m68k_op thark
;
1294 memset(&thark
, '\0', sizeof(thark
));
1295 if(!m68k_ip_op(buf
,&thark
)) printf("FAIL:");
1297 printf("op1 error %s in %s\n",thark
.error
,buf
);
1298 printf("mode %d, reg %d, ",thark
.mode
,thark
.reg
);
1300 printf("Constant: '%.*s',",1+thark
.e_const
-thark
.b_const
,thark
.b_const
);
1301 printf("ireg %d, isiz %d, imul %d ",thark
.ireg
,thark
.isiz
,thark
.imul
);
1303 printf("Iadd: '%.*s'",1+thark
.e_iadd
-thark
.b_iadd
,thark
.b_iadd
);
1312 static struct hash_control
* op_hash
= NULL
; /* handle of the OPCODE hash table
1313 NULL means any use before m68k_ip_begin()
1320 * This converts a string into a 68k instruction.
1321 * The string must be a bare single instruction in sun format
1322 * with RMS-style 68020 indirects
1325 * It provides some error messages: at most one fatal error message (which
1326 * stops the scan) and at most one warning message for each operand.
1327 * The 68k instruction is returned in exploded form, since we have no
1328 * knowledge of how you parse (or evaluate) your expressions.
1329 * We do however strip off and decode addressing modes and operation
1332 * This function's value is a string. If it is not "" then an internal
1333 * logic error was found: read this code to assign meaning to the string.
1334 * No argument string should generate such an error string:
1335 * it means a bug in our code, not in the user's text.
1337 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1341 /* JF this function no longer returns a useful value. Sorry */
1342 void m68k_ip (instring
)
1346 register struct m68k_op
*opP
;
1347 register struct m68k_incant
*opcode
;
1349 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1350 char *pdot
, *pdotmove
;
1355 char *crack_operand();
1356 LITTLENUM_TYPE words
[6];
1357 LITTLENUM_TYPE
*wordp
;
1358 unsigned long ok_arch
= 0;
1360 if (*instring
== ' ')
1361 instring
++; /* skip leading whitespace */
1363 /* Scan up to end of operation-code, which MUST end in end-of-string
1364 or exactly 1 space. */
1366 for (p
= instring
; *p
!= '\0'; p
++) {
1373 if (p
== instring
) {
1374 the_ins
.error
= "No operator";
1375 the_ins
.opcode
[0] = NULL
;
1376 /* the_ins.numo=1; */
1380 /* p now points to the end of the opcode name, probably whitespace.
1381 make sure the name is null terminated by clobbering the whitespace,
1382 look it up in the hash table, then fix it back.
1383 Remove a dot, first, since the opcode tables have none. */
1385 for (pdotmove
=pdot
; pdotmove
<p
; pdotmove
++)
1386 *pdotmove
=pdotmove
[1];
1392 opcode
= (struct m68k_incant
*)hash_find (op_hash
, instring
);
1396 for (pdotmove
=p
; pdotmove
>pdot
; pdotmove
--)
1397 *pdotmove
=pdotmove
[-1];
1402 if (opcode
== NULL
) {
1403 the_ins
.error
= "Unknown operator";
1404 the_ins
.opcode
[0] = NULL
;
1405 /* the_ins.numo=1; */
1409 /* found a legitimate opcode, start matching operands */
1410 while (*p
== ' ') ++p
;
1413 if (opcode
->m_operands
== 0) {
1414 char *old
= input_line_pointer
;
1416 input_line_pointer
= p
;
1417 /* Ahh - it's a motorola style psuedo op */
1418 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1419 ( mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1420 input_line_pointer
= old
;
1426 for(opP
= &the_ins
.operands
[0]; *p
; opP
++) {
1428 p
= crack_operand(p
, opP
);
1431 the_ins
.error
=opP
->error
;
1436 opsfound
= opP
- &the_ins
.operands
[0];
1438 /* This ugly hack is to support the floating pt opcodes in their standard form */
1439 /* Essentially, we fake a first enty of type COP#1 */
1440 if (opcode
->m_operands
[0]=='I') {
1443 for(n
=opsfound
;n
>0;--n
)
1444 the_ins
.operands
[n
]=the_ins
.operands
[n
-1];
1446 memset((char *)(&the_ins
.operands
[0]), '\0', sizeof(the_ins
.operands
[0]));
1447 the_ins
.operands
[0].mode
=MSCR
;
1448 the_ins
.operands
[0].reg
=COPNUM
; /* COP #1 */
1452 /* We've got the operands. Find an opcode that'll accept them */
1453 for (losing
= 0; ; ) {
1454 /* if we didn't get the right number of ops,
1455 or we have no common model with this pattern
1456 then reject this pattern. */
1458 if (opsfound
!= opcode
->m_opnum
1459 || ((opcode
->m_arch
& current_architecture
) == 0))
1462 ok_arch
|= opcode
->m_arch
;
1465 for (s
=opcode
->m_operands
, opP
= &the_ins
.operands
[0]; *s
&& !losing
; s
+= 2, opP
++) {
1466 /* Warning: this switch is huge! */
1467 /* I've tried to organize the cases into this order:
1468 non-alpha first, then alpha by letter. lower-case goes directly
1469 before uppercase counterpart. */
1470 /* Code with multiple case ...: gets sorted by the lowest case ...
1471 it belongs to. I hope this makes sense. */
1474 if (opP
->mode
== MSCR
|| opP
->mode
== IMMED
1475 || opP
->mode
== DREG
|| opP
->mode
== AREG
1476 || opP
->mode
== AINC
|| opP
->mode
== ADEC
1477 || opP
->mode
== REGLST
)
1482 switch (opP
->mode
) {
1483 case MSCR
: case IMMED
: case DREG
: case AREG
:
1484 case AINC
: case REGLST
: case AINDR
:
1490 if(opP
->mode
!=IMMED
)
1495 t
=get_num(opP
->con1
,80);
1496 if(s
[1]=='b' && !isbyte(t
))
1498 else if(s
[1]=='w' && !isword(t
))
1505 if(opP
->mode
!=IMMED
)
1510 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
1511 opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
1516 if(opP
->mode
==MSCR
|| opP
->reg
==PC
||
1517 opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
1523 if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
1524 opP
->mode
==AREG
|| opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
||
1525 opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==REGLST
)
1530 if(opP
->mode
==MSCR
|| opP
->mode
==REGLST
)
1545 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
1546 opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==IMMED
|| opP
->mode
==REGLST
)
1551 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
|| opP
->mode
==REGLST
)
1556 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
1557 opP
->mode
==AINC
|| opP
->mode
==ADEC
|| opP
->mode
==IMMED
|| opP
->reg
==PC
||
1558 opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
1563 if(opP
->mode
==MSCR
|| opP
->mode
==AREG
||
1564 opP
->mode
==IMMED
|| opP
->mode
==REGLST
)
1568 case '~': /* For now! (JF FOO is this right?) */
1569 if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
1570 opP
->mode
==AREG
|| opP
->mode
==IMMED
|| opP
->reg
==PC
|| opP
->reg
==ZPC
|| opP
->mode
==REGLST
)
1575 if (opP
->mode
!= MSCR
|| (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1584 if (opP
->mode
!= AINDR
) {
1586 } /* if not address register indirect */
1589 if(opP
->mode
!=ABSL
|| (flagseen
['S'] && instring
[0] == 'j'
1590 && instring
[1] == 'b'
1591 && instring
[2] == 's'
1592 && instring
[3] == 'r'))
1597 if(opP
->mode
!=MSCR
|| opP
->reg
!=CCR
)
1601 case 'd': /* FOO This mode is a KLUDGE!! */
1602 if(opP
->mode
!=AOFF
&& (opP
->mode
!=ABSL
||
1603 opP
->con1
->e_beg
[0]!='(' || opP
->con1
->e_end
[0]!=')'))
1613 if(opP
->mode
!=MSCR
|| opP
->reg
<(FPREG
+0) || opP
->reg
>(FPREG
+7))
1618 if(opP
->mode
!=MSCR
|| opP
->reg
<COPNUM
||
1624 if (opP
->mode
!= MSCR
1627 || cpu_of_arch(current_architecture
) < m68010
/* before 68010 had none */
1628 || (cpu_of_arch(current_architecture
) < m68020
1632 && opP
->reg
!= VBR
) /* 68010's had only these */
1633 || (cpu_of_arch(current_architecture
) < m68040
1641 && opP
->reg
!= ISP
) /* 680[23]0's have only these */
1642 || (cpu_of_arch(current_architecture
) == m68040
/* 68040 has all but this */
1643 && opP
->reg
== CAAR
)) {
1645 } /* doesn't cut it */
1649 if(opP
->mode
!=IMMED
)
1655 if(opP
->mode
==DREG
|| opP
->mode
==AREG
|| opP
->mode
==FPREG
) {
1660 opP
->reg
=1<<(opP
->reg
-DATA
);
1662 } else if(opP
->mode
!=REGLST
) {
1664 } else if(s
[1]=='8' && opP
->reg
&0x0FFffFF)
1666 else if(s
[1]=='3' && opP
->reg
&0x7000000)
1671 if(opP
->mode
!=IMMED
)
1676 t
=get_num(opP
->con1
,80);
1677 if(!issbyte(t
) || isvar(opP
->con1
))
1683 if(opP
->mode
!=DREG
&& opP
->mode
!=IMMED
)
1688 if(opP
->mode
!=IMMED
)
1693 t
=get_num(opP
->con1
,80);
1694 if(t
<1 || t
>8 || isvar(opP
->con1
))
1700 if(opP
->mode
!=DREG
&& opP
->mode
!=AREG
)
1705 if (opP
->mode
!=AINDR
&& opP
->mode
!=DINDR
)
1710 if(opP
->mode
!=MSCR
|| !(opP
->reg
==FPI
|| opP
->reg
==FPS
|| opP
->reg
==FPC
))
1715 if(opP
->mode
!=MSCR
|| opP
->reg
!=SR
)
1720 if (opP
->mode
!= IMMED
)
1724 long t
= get_num (opP
->con1
, 80);
1725 if (t
< 0 || t
> 7 || isvar (opP
->con1
))
1731 if(opP
->mode
!=MSCR
|| opP
->reg
!=USP
)
1735 /* JF these are out of order. We could put them
1736 in order if we were willing to put up with
1737 bunches of #ifdef m68851s in the code.
1739 Don't forget that you need these operands
1740 to use 68030 MMU instructions. */
1742 /* Memory addressing mode used by pflushr */
1744 if(opP
->mode
==MSCR
|| opP
->mode
==DREG
||
1745 opP
->mode
==AREG
|| opP
->mode
==REGLST
)
1750 if (opP
->mode
!= MSCR
|| (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1755 if (opP
->mode
!= MSCR
1756 || (opP
->reg
!= TC
&& opP
->reg
!= CAL
1757 && opP
->reg
!= VAL
&& opP
->reg
!= SCC
&& opP
->reg
!= AC
))
1762 if (opP
->reg
!= VAL
)
1767 if (opP
->mode
!= MSCR
1768 || (opP
->reg
!= DRP
&& opP
->reg
!= SRP
1769 && opP
->reg
!= CRP
))
1774 if (opP
->mode
!= MSCR
||
1775 (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+7) &&
1776 !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+7)))
1781 if (opP
->reg
!= PSR
)
1786 if (opP
->reg
!= PCSR
)
1794 && opP
->reg
!= BC
) {
1796 } /* not a cache specifier. */
1800 if (opP
->mode
!= ABSL
) {
1802 } /* not absolute */
1806 as_fatal("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
1807 *s
, __LINE__
, __FILE__
);
1808 } /* switch on type of operand */
1812 } /* for each operand */
1813 } /* if immediately wrong */
1819 opcode
= opcode
->m_next
;
1823 && !(ok_arch
& current_architecture
))
1827 strcpy (buf
, "invalid instruction for this architecture; needs ");
1828 cp
= buf
+ strlen (buf
);
1832 strcpy (cp
, "fpu (68040 or 68881/68882)");
1835 strcpy (cp
, "mmu (68030 or 68851)");
1838 strcpy (cp
, "68020 or higher");
1841 strcpy (cp
, "68000 or higher");
1844 strcpy (cp
, "68010 or higher");
1848 int got_one
= 0, idx
;
1849 const static struct {
1862 for (idx
= 0; idx
< sizeof (archs
)/sizeof (archs
[0]); idx
++)
1864 if (archs
[idx
].arch
& ok_arch
)
1868 strcpy (cp
, " or ");
1872 strcpy (cp
, archs
[idx
].name
);
1884 the_ins
.error
= "operands mismatch";
1886 } /* Fell off the end */
1891 /* now assemble it */
1893 the_ins
.args
=opcode
->m_operands
;
1894 the_ins
.numargs
=opcode
->m_opnum
;
1895 the_ins
.numo
=opcode
->m_codenum
;
1896 the_ins
.opcode
[0]=getone(opcode
);
1897 the_ins
.opcode
[1]=gettwo(opcode
);
1899 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++) {
1900 /* This switch is a doozy.
1901 Watch the first step; its a big one! */
1920 tmpreg
=0x3c; /* 7.4 */
1921 if (strchr("bwl",s
[1])) nextword
=get_num(opP
->con1
,80);
1922 else nextword
=nextword
=get_num(opP
->con1
,0);
1923 if(isvar(opP
->con1
))
1924 add_fix(s
[1],opP
->con1
,0);
1927 if(!isbyte(nextword
))
1928 opP
->error
="operand out of range";
1933 if(!isword(nextword
))
1934 opP
->error
="operand out of range";
1939 addword(nextword
>>16);
1961 as_fatal("Internal error: Can't decode %c%c in line %s of file \"%s\"",
1962 *s
, s
[1], __LINE__
, __FILE__
);
1967 /* We gotta put out some float */
1968 if(seg(opP
->con1
)!=SEG_BIG
) {
1969 int_to_gen(nextword
);
1970 gen_to_words(words
,baseo
,(long int)outro
);
1971 for(wordp
=words
;baseo
--;wordp
++)
1975 if(offs(opP
->con1
)>0) {
1976 if(offs(opP
->con1
)>baseo
) {
1977 as_warn("Bignum too big for %c format; truncated",s
[1]);
1978 offs(opP
->con1
)=baseo
;
1980 baseo
-=offs(opP
->con1
);
1981 for(wordp
=generic_bignum
+offs(opP
->con1
)-1;offs(opP
->con1
)--;--wordp
)
1987 gen_to_words(words
,baseo
,(long)outro
);
1988 for (wordp
=words
;baseo
--;wordp
++)
1992 tmpreg
=opP
->reg
-DATA
; /* 0.dreg */
1995 tmpreg
=0x08+opP
->reg
-ADDR
; /* 1.areg */
1998 tmpreg
=0x10+opP
->reg
-ADDR
; /* 2.areg */
2001 tmpreg
=0x20+opP
->reg
-ADDR
; /* 4.areg */
2004 tmpreg
=0x18+opP
->reg
-ADDR
; /* 3.areg */
2008 nextword
=get_num(opP
->con1
,80);
2009 /* Force into index mode. Hope this works */
2011 /* We do the first bit for 32-bit displacements,
2012 and the second bit for 16 bit ones. It is
2013 possible that we should make the default be
2014 WORD instead of LONG, but I think that'd
2015 break GCC, so we put up with a little
2016 inefficiency for the sake of working output.
2019 if( !issword(nextword
)
2020 || ( isvar(opP
->con1
)
2021 && ( ( opP
->con1
->e_siz
==0
2022 && flagseen
['l']==0)
2023 || opP
->con1
->e_siz
==3))) {
2026 tmpreg
=0x3B; /* 7.3 */
2028 tmpreg
=0x30+opP
->reg
-ADDR
; /* 6.areg */
2029 if(isvar(opP
->con1
)) {
2031 add_frag(adds(opP
->con1
),
2033 TAB(PCLEA
,SZ_UNDEF
));
2037 add_fix('l',opP
->con1
,0);
2041 addword(nextword
>>16);
2044 tmpreg
=0x3A; /* 7.2 */
2046 tmpreg
=0x28+opP
->reg
-ADDR
; /* 5.areg */
2048 if(isvar(opP
->con1
)) {
2050 add_fix('w',opP
->con1
,1);
2052 add_fix('w',opP
->con1
,0);
2061 know(current_architecture
& m68020up
);
2062 /* intentional fall-through */
2065 baseo
=get_num(opP
->con1
,80);
2066 outro
=get_num(opP
->con2
,80);
2067 /* Figure out the 'addressing mode' */
2068 /* Also turn on the BASE_DISABLE bit, if needed */
2069 if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
2070 tmpreg
=0x3b; /* 7.3 */
2073 } else if(opP
->reg
==FAIL
) {
2075 tmpreg
=0x30; /* 6.garbage */
2076 } else tmpreg
=0x30+opP
->reg
-ADDR
; /* 6.areg */
2078 siz1
= (opP
->con1
) ? opP
->con1
->e_siz
: 0;
2079 siz2
= (opP
->con2
) ? opP
->con2
->e_siz
: 0;
2081 /* Index register stuff */
2082 if(opP
->ireg
>=DATA
+0 && opP
->ireg
<=ADDR
+7) {
2083 nextword
|=(opP
->ireg
-DATA
)<<12;
2085 if(opP
->isiz
==0 || opP
->isiz
==3)
2089 case 2: nextword
|=0x200; break;
2090 case 4: nextword
|=0x400; break;
2091 case 8: nextword
|=0x600; break;
2092 default: as_fatal("failed sanity check.");
2095 GET US OUT OF HERE! */
2097 /* Must be INDEX, with an index
2098 register. Address register
2099 cannot be ZERO-PC, and either
2100 :b was forced, or we know
2102 if( opP
->mode
==AINDX
2107 && !isvar(opP
->con1
)))) {
2108 nextword
+=baseo
&0xff;
2110 if(isvar(opP
->con1
))
2111 add_fix('B',opP
->con1
,0);
2115 nextword
|=0x40; /* No index reg */
2117 /* It aint simple */
2119 /* If the guy specified a width, we assume that
2120 it is wide enough. Maybe it isn't. If so, we lose
2124 if(isvar(opP
->con1
) || !issword(baseo
)) {
2135 as_warn("Byte dispacement won't work. Defaulting to :w");
2144 /* Figure out innner displacement stuff */
2145 if(opP
->mode
!=AINDX
) {
2148 if(isvar(opP
->con2
) || !issword(outro
)) {
2159 as_warn("Byte dispacement won't work. Defaulting to :w");
2167 if(opP
->mode
==APODX
) nextword
|=0x04;
2168 else if(opP
->mode
==AMIND
) nextword
|=0x40;
2172 if(isvar(opP
->con1
)) {
2173 if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
2174 add_fix(siz1
==3 ? 'l' : 'w',opP
->con1
,1);
2175 opP
->con1
->e_exp
.X_add_number
+=6;
2177 add_fix(siz1
==3 ? 'l' : 'w',opP
->con1
,0);
2184 if(isvar(opP
->con2
)) {
2185 if(opP
->reg
==PC
|| opP
->reg
==ZPC
) {
2186 add_fix(siz2
==3 ? 'l' : 'w',opP
->con2
,1);
2187 opP
->con1
->e_exp
.X_add_number
+=6;
2189 add_fix(siz2
==3 ? 'l' : 'w',opP
->con2
,0);
2199 nextword
=get_num(opP
->con1
,80);
2200 switch(opP
->con1
->e_siz
) {
2202 as_warn("Unknown size for absolute reference");
2204 if(!isvar(opP
->con1
) && issword(offs(opP
->con1
))) {
2205 tmpreg
=0x38; /* 7.0 */
2209 /* Don't generate pc relative code
2210 on 68010 and 68000 */
2213 && seg(opP
->con1
) == SEG_TEXT
2214 && now_seg
== SEG_TEXT
2215 && cpu_of_arch(current_architecture
) >= m68020
2217 && !strchr("~%&$?", s
[0])) {
2218 tmpreg
=0x3A; /* 7.2 */
2219 add_frag(adds(opP
->con1
),
2221 TAB(PCREL
,SZ_UNDEF
));
2224 case 3: /* Fall through into long */
2225 if(isvar(opP
->con1
))
2226 add_fix('l',opP
->con1
,0);
2228 tmpreg
=0x39; /* 7.1 mode */
2229 addword(nextword
>>16);
2234 if(isvar(opP
->con1
))
2235 add_fix('w',opP
->con1
,0);
2237 tmpreg
=0x38; /* 7.0 mode */
2243 as_bad("invalid indirect register");
2247 as_bad("unknown/incorrect operand");
2250 install_gen_operand(s
[1],tmpreg
);
2255 switch(s
[1]) { /* JF: I hate floating point! */
2270 tmpreg
=get_num(opP
->con1
,tmpreg
);
2271 if(isvar(opP
->con1
))
2272 add_fix(s
[1],opP
->con1
,0);
2274 case 'b': /* Danger: These do no check for
2275 certain types of overflow.
2278 opP
->error
="out of range";
2280 if(isvar(opP
->con1
))
2281 the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
2285 opP
->error
="out of range";
2287 if(isvar(opP
->con1
))
2288 the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
2291 insop(tmpreg
); /* Because of the way insop works, we put these two out backwards */
2293 if(isvar(opP
->con1
))
2294 the_ins
.reloc
[the_ins
.nrel
-1].n
=(opcode
->m_codenum
)*2;
2300 install_operand(s
[1],tmpreg
);
2303 as_fatal("Internal error: Unknown mode #%c in line %s of file \"%s\"", s
[1], __LINE__
, __FILE__
);
2311 install_operand(s
[1],opP
->reg
-ADDR
);
2315 tmpreg
=get_num(opP
->con1
,80);
2318 /* Needs no offsetting */
2319 add_fix('B',opP
->con1
,1);
2322 /* Offset the displacement to be relative to byte disp location */
2323 opP
->con1
->e_exp
.X_add_number
+=2;
2324 add_fix('w',opP
->con1
,1);
2329 if (cpu_of_arch(current_architecture
) < m68020
) /* 68000 or 010 */
2330 as_warn("Can't use long branches on 68000/68010");
2331 the_ins
.opcode
[the_ins
.numo
-1]|=0xff;
2332 /* Offset the displacement to be relative to byte disp location */
2333 opP
->con1
->e_exp
.X_add_number
+=4;
2334 add_fix('l',opP
->con1
,1);
2339 if(subs(opP
->con1
)) /* We can't relax it */
2342 /* This could either be a symbol, or an
2343 absolute address. No matter, the
2344 frag hacking will finger it out.
2345 Not quite: it can't switch from
2346 BRANCH to BCC68000 for the case
2347 where opnd is absolute (it needs
2348 to use the 68000 hack since no
2349 conditional abs jumps). */
2350 if (((cpu_of_arch(current_architecture
) < m68020
) || (0==adds(opP
->con1
)))
2351 && (the_ins
.opcode
[0] >= 0x6200)
2352 && (the_ins
.opcode
[0] <= 0x6f00)) {
2353 add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(BCC68000
,SZ_UNDEF
));
2355 add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(ABRANCH
,SZ_UNDEF
));
2359 if(isvar(opP
->con1
)) {
2360 /* check for DBcc instruction */
2361 if ((the_ins
.opcode
[0] & 0xf0f8) ==0x50c8) {
2362 /* size varies if patch */
2363 /* needed for long form */
2364 add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(DBCC
,SZ_UNDEF
));
2369 opP
->con1
->e_exp
.X_add_number
+=2;
2370 add_fix('w',opP
->con1
,1);
2374 case 'C': /* Fixed size LONG coproc branches */
2375 the_ins
.opcode
[the_ins
.numo
-1]|=0x40;
2376 /* Offset the displacement to be relative to byte disp location */
2377 /* Coproc branches don't have a byte disp option, but they are
2378 compatible with the ordinary branches, which do... */
2379 opP
->con1
->e_exp
.X_add_number
+=4;
2380 add_fix('l',opP
->con1
,1);
2384 case 'c': /* Var size Coprocesssor branches */
2385 if(subs(opP
->con1
)) {
2386 add_fix('l',opP
->con1
,1);
2387 add_frag((symbolS
*)0,(long)0,TAB(FBRANCH
,LONG
));
2388 } else if(adds(opP
->con1
)) {
2389 add_frag(adds(opP
->con1
),offs(opP
->con1
),TAB(FBRANCH
,SZ_UNDEF
));
2391 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2392 the_ins
.opcode
[the_ins
.numo
-1]|=0x40;
2393 add_fix('l',opP
->con1
,1);
2399 as_fatal("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2400 s
[1], __LINE__
, __FILE__
);
2404 case 'C': /* Ignore it */
2407 case 'd': /* JF this is a kludge */
2408 if(opP
->mode
==AOFF
) {
2409 install_operand('s',opP
->reg
-ADDR
);
2413 tmpP
=opP
->con1
->e_end
-2;
2415 opP
->con1
->e_end
-=4; /* point to the , */
2416 baseo
=m68k_reg_parse(&tmpP
);
2417 if(baseo
<ADDR
+0 || baseo
>ADDR
+7) {
2418 as_bad("Unknown address reg, using A0");
2421 install_operand('s',baseo
);
2423 tmpreg
=get_num(opP
->con1
,80);
2424 if(!issword(tmpreg
)) {
2425 as_warn("Expression out of range, using 0");
2432 install_operand(s
[1],opP
->reg
-DATA
);
2436 install_operand(s
[1],opP
->reg
-FPREG
);
2440 tmpreg
=1+opP
->reg
-COPNUM
;
2443 install_operand(s
[1],tmpreg
);
2446 case 'J': /* JF foo */
2448 case SFC
: tmpreg
=0x000; break;
2449 case DFC
: tmpreg
=0x001; break;
2450 case CACR
: tmpreg
=0x002; break;
2451 case TC
: tmpreg
=0x003; break;
2452 case ITT0
: tmpreg
=0x004; break;
2453 case ITT1
: tmpreg
=0x005; break;
2454 case DTT0
: tmpreg
=0x006; break;
2455 case DTT1
: tmpreg
=0x007; break;
2457 case USP
: tmpreg
=0x800; break;
2458 case VBR
: tmpreg
=0x801; break;
2459 case CAAR
: tmpreg
=0x802; break;
2460 case MSP
: tmpreg
=0x803; break;
2461 case ISP
: tmpreg
=0x804; break;
2462 case MMUSR
: tmpreg
=0x805; break;
2463 case URP
: tmpreg
=0x806; break;
2464 case SRP
: tmpreg
=0x807; break;
2466 as_fatal("failed sanity check.");
2468 install_operand(s
[1],tmpreg
);
2472 tmpreg
=get_num(opP
->con1
,55);
2473 install_operand(s
[1],tmpreg
&0x7f);
2479 if(tmpreg
&0x7FF0000)
2480 as_bad("Floating point register in register list");
2481 insop(reverse_16_bits(tmpreg
));
2483 if(tmpreg
&0x700FFFF)
2484 as_bad("Wrong register in floating-point reglist");
2485 install_operand(s
[1],reverse_8_bits(tmpreg
>>16));
2492 if(tmpreg
&0x7FF0000)
2493 as_bad("Floating point register in register list");
2495 } else if(s
[1]=='8') {
2496 if(tmpreg
&0x0FFFFFF)
2497 as_bad("incorrect register in reglist");
2498 install_operand(s
[1],tmpreg
>>24);
2500 if(tmpreg
&0x700FFFF)
2501 as_bad("wrong register in floating-point reglist");
2503 install_operand(s
[1],tmpreg
>>16);
2508 install_operand(s
[1],get_num(opP
->con1
,60));
2512 tmpreg
= (opP
->mode
==DREG
)
2513 ? 0x20+opP
->reg
-DATA
2514 : (get_num(opP
->con1
,40)&0x1F);
2515 install_operand(s
[1],tmpreg
);
2519 tmpreg
=get_num(opP
->con1
,10);
2522 install_operand(s
[1],tmpreg
);
2527 /* This depends on the fact that ADDR registers are
2528 eight more than their corresponding DATA regs, so
2529 the result will have the ADDR_REG bit set */
2530 install_operand(s
[1],opP
->reg
-DATA
);
2534 if(opP
->reg
==FPI
) tmpreg
=0x1;
2535 else if(opP
->reg
==FPS
) tmpreg
=0x2;
2536 else if(opP
->reg
==FPC
) tmpreg
=0x4;
2537 else as_fatal("failed sanity check.");
2538 install_operand(s
[1],tmpreg
);
2541 case 'S': /* Ignore it */
2545 install_operand(s
[1],get_num(opP
->con1
,30));
2548 case 'U': /* Ignore it */
2553 case NC
: tmpreg
= 0; break;
2554 case DC
: tmpreg
= 1; break;
2555 case IC
: tmpreg
= 2; break;
2556 case BC
: tmpreg
= 3; break;
2558 as_fatal("failed sanity check");
2559 } /* switch on cache token */
2560 install_operand(s
[1], tmpreg
);
2563 /* JF: These are out of order, I fear. */
2573 as_fatal("failed sanity check.");
2575 install_operand(s
[1],tmpreg
);
2596 as_fatal("failed sanity check.");
2598 install_operand(s
[1],tmpreg
);
2602 if (opP
->reg
== VAL
)
2604 as_fatal("failed sanity check.");
2619 as_fatal("failed sanity check.");
2621 install_operand(s
[1],tmpreg
);
2626 case BAD
: case BAD
+1: case BAD
+2: case BAD
+3:
2627 case BAD
+4: case BAD
+5: case BAD
+6: case BAD
+7:
2628 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
2631 case BAC
: case BAC
+1: case BAC
+2: case BAC
+3:
2632 case BAC
+4: case BAC
+5: case BAC
+6: case BAC
+7:
2633 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
2637 as_fatal("failed sanity check.");
2639 install_operand(s
[1], tmpreg
);
2642 know(opP
->reg
== PSR
);
2645 know(opP
->reg
== PCSR
);
2658 as_fatal ("failed sanity check");
2660 install_operand (s
[1], tmpreg
);
2663 tmpreg
= get_num (opP
->con1
, 20);
2664 install_operand (s
[1], tmpreg
);
2666 case '_': /* used only for move16 absolute 32-bit address */
2667 tmpreg
=get_num(opP
->con1
,80);
2668 addword (tmpreg
>> 16);
2669 addword (tmpreg
& 0xFFFF);
2672 as_fatal("Internal error: Operand type %c unknown in line %d of file \"%s\"",
2673 s
[0], __LINE__
, __FILE__
);
2677 /* By the time whe get here (FINALLY) the_ins contains the complete
2678 instruction, ready to be emitted. . . */
2682 * get_regs := '/' + ?
2683 * | '-' + <register>
2684 * | '-' + <register> + ?
2689 * The idea here must be to scan in a set of registers but I don't
2690 * understand it. Looks awfully sloppy to me but I don't have any doc on
2697 static int get_regs(i
,str
,opP
)
2699 struct m68k_op
*opP
;
2702 /* 26, 25, 24, 23-16, 15-8, 0-7 */
2703 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
2704 unsigned long cur_regs
= 0;
2708 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
2709 else if(x==FPS) cur_regs|=(1<<25);\
2710 else if(x==FPC) cur_regs|=(1<<26);\
2711 else cur_regs|=(1<<(x-1)); }
2718 } else if(*str
=='-') {
2720 reg2
=m68k_reg_parse(&str
);
2721 if(reg2
<DATA
|| reg2
>=FPREG
+8 || reg1
==FPI
|| reg1
==FPS
|| reg1
==FPC
) {
2722 opP
->error
="unknown register in register list";
2731 } else if(*str
=='\0') {
2735 opP
->error
="unknow character in register list";
2738 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
2741 reg1
=m68k_reg_parse(&str
);
2742 if((reg1
<DATA
|| reg1
>=FPREG
+8) && !(reg1
==FPI
|| reg1
==FPS
|| reg1
==FPC
)) {
2743 opP
->error
="unknown register in register list";
2751 static int reverse_16_bits(in
)
2757 static int mask
[16] = {
2758 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2759 0x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000
2766 } /* reverse_16_bits() */
2768 static int reverse_8_bits(in
)
2774 static int mask
[8] = {
2775 0x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080,
2783 } /* reverse_8_bits() */
2785 static void install_operand(mode
,val
)
2791 the_ins
.opcode
[0]|=val
& 0xFF; /* JF FF is for M kludge */
2794 the_ins
.opcode
[0]|=val
<<9;
2797 the_ins
.opcode
[1]|=val
<<12;
2800 the_ins
.opcode
[1]|=val
<<6;
2803 the_ins
.opcode
[1]|=val
;
2806 the_ins
.opcode
[2]|=val
<<12;
2809 the_ins
.opcode
[2]|=val
<<6;
2812 /* DANGER! This is a hack to force cas2l and cas2w cmds
2813 to be three words long! */
2815 the_ins
.opcode
[2]|=val
;
2818 the_ins
.opcode
[1]|=val
<<7;
2821 the_ins
.opcode
[1]|=val
<<10;
2825 the_ins
.opcode
[1]|=val
<<5;
2830 the_ins
.opcode
[1]|=(val
<<10)|(val
<<7);
2833 the_ins
.opcode
[1]|=(val
<<12)|val
;
2836 the_ins
.opcode
[0]|=val
=0xff;
2839 the_ins
.opcode
[0]|=val
<<9;
2842 the_ins
.opcode
[1]|=val
;
2845 the_ins
.opcode
[1]|=val
;
2846 the_ins
.numo
++; /* What a hack */
2849 the_ins
.opcode
[1]|=val
<<4;
2856 the_ins
.opcode
[0] |= (val
<< 6);
2859 the_ins
.opcode
[1] = (val
>> 16);
2860 the_ins
.opcode
[2] = val
& 0xffff;
2864 as_fatal("failed sanity check.");
2866 } /* install_operand() */
2868 static void install_gen_operand(mode
,val
)
2874 the_ins
.opcode
[0]|=val
;
2877 /* This is a kludge!!! */
2878 the_ins
.opcode
[0]|=(val
&0x07)<<9|(val
&0x38)<<3;
2887 the_ins
.opcode
[0]|=val
;
2889 /* more stuff goes here */
2891 as_fatal("failed sanity check.");
2893 } /* install_gen_operand() */
2896 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2897 * then deal with the bitfield hack.
2900 static char *crack_operand(str
,opP
)
2902 register struct m68k_op
*opP
;
2904 register int parens
;
2906 register char *beg_str
;
2912 for(parens
=0;*str
&& (parens
>0 || notend(str
));str
++) {
2913 if(*str
=='(') parens
++;
2914 else if(*str
==')') {
2915 if(!parens
) { /* ERROR */
2916 opP
->error
="Extra )";
2922 if(!*str
&& parens
) { /* ERROR */
2923 opP
->error
="Missing )";
2928 if(m68k_ip_op(beg_str
,opP
)==FAIL
) {
2934 c
= *++str
; /* JF bitfield hack */
2938 as_bad("Missing operand");
2943 /* See the comment up above where the #define notend(... is */
2948 if(*s
==',') return 0;
2949 if(*s
=='{' || *s
=='}')
2951 if(*s
!=':') return 1;
2952 /* This kludge here is for the division cmd, which is a kludge */
2953 if(index("aAdD#",s
[1])) return 0;
2958 /* This is the guts of the machine-dependent assembler. STR points to a
2959 machine dependent instruction. This function is supposed to emit
2960 the frags/bytes it assembles to.
2964 insert_reg(regname
, regnum
)
2970 symbol_table_insert(symbol_new(regname
, SEG_REGISTER
, regnum
, &zero_address_frag
));
2972 for (i
= 0; regname
[i
]; i
++)
2973 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
2976 symbol_table_insert(symbol_new(buf
, SEG_REGISTER
, regnum
, &zero_address_frag
));
2979 static const struct {
3083 /* 68ec030 versions of same */
3086 /* 68ec030 access control unit, identical to 030 MMU status reg */
3098 for (i
= 0; init_table
[i
].name
; i
++)
3099 insert_reg(init_table
[i
].name
, init_table
[i
].number
);
3102 static int no_68851
, no_68881
;
3113 int shorts_this_frag
;
3114 static int done_first_time
;
3116 if (!done_first_time
)
3118 done_first_time
= 1;
3120 if (cpu_of_arch (current_architecture
) == 0)
3127 if (strcmp (TARGET_CPU
, "m68000") == 0)
3129 else if (strcmp (TARGET_CPU
, "m68010") == 0)
3131 else if (strcmp (TARGET_CPU
, "m68020") == 0
3132 || strcmp (TARGET_CPU
, "m68k") == 0)
3134 else if (strcmp (TARGET_CPU
, "m68030") == 0)
3136 else if (strcmp (TARGET_CPU
, "m68040") == 0)
3138 else if (strcmp (TARGET_CPU
, "cpu32") == 0)
3144 current_architecture
|= cpu_type
;
3146 if (current_architecture
& m68881
)
3148 if (current_architecture
& m68000
)
3149 as_bad ("incompatible processors 68000 and 68881/2 specified");
3150 if (current_architecture
& m68010
)
3151 as_bad ("incompatible processors 68010 and 68881/2 specified");
3152 if (current_architecture
& m68040
)
3153 as_bad ("incompatible processors 68040 and 68881/2 specified");
3155 /* What other incompatibilities ought we to check for? */
3157 /* Toss in some default assumptions about coprocessors. */
3159 && (cpu_of_arch (current_architecture
)
3160 /* Can CPU32 have a 68881 coprocessor?? */
3161 & (m68020
| m68030
| cpu32
)))
3163 current_architecture
|= m68881
;
3166 && (cpu_of_arch (current_architecture
) & m68020up
) != 0)
3168 current_architecture
|= m68851
;
3170 if (no_68881
&& (current_architecture
& m68881
))
3171 as_bad ("options for 68881 and no-68881 both given");
3172 if (no_68851
&& (current_architecture
& m68851
))
3173 as_bad ("options for 68851 and no-68851 both given");
3174 done_first_time
= 1;
3177 memset((char *)(&the_ins
), '\0', sizeof(the_ins
)); /* JF for paranoia sake */
3181 for(n
=the_ins
.numargs
;n
;--n
)
3182 if(the_ins
.operands
[n
].error
) {
3183 er
=the_ins
.operands
[n
].error
;
3188 as_bad("%s -- statement `%s' ignored",er
,str
);
3192 if(the_ins
.nfrag
==0) { /* No frag hacking involved; just put it out */
3193 toP
=frag_more(2*the_ins
.numo
);
3194 fromP
= &the_ins
.opcode
[0];
3195 for(m
=the_ins
.numo
;m
;--m
) {
3196 md_number_to_chars(toP
,(long)(*fromP
),2);
3200 /* put out symbol-dependent info */
3201 for(m
=0;m
<the_ins
.nrel
;m
++) {
3202 switch(the_ins
.reloc
[m
].wid
) {
3219 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins
.reloc
[m
].wid
);
3223 (toP
-frag_now
->fr_literal
)-the_ins
.numo
*2+the_ins
.reloc
[m
].n
,
3225 the_ins
.reloc
[m
].add
,
3226 the_ins
.reloc
[m
].sub
,
3227 the_ins
.reloc
[m
].off
,
3228 the_ins
.reloc
[m
].pcrel
,
3234 /* There's some frag hacking */
3235 for(n
=0,fromP
= &the_ins
.opcode
[0];n
<the_ins
.nfrag
;n
++) {
3238 if(n
==0) wid
=2*the_ins
.fragb
[n
].fragoff
;
3239 else wid
=2*(the_ins
.numo
-the_ins
.fragb
[n
-1].fragoff
);
3243 for(m
=wid
/2;m
;--m
) {
3244 md_number_to_chars(toP
,(long)(*fromP
),2);
3249 for(m
=0;m
<the_ins
.nrel
;m
++) {
3250 if((the_ins
.reloc
[m
].n
)>= 2*shorts_this_frag
/* 2*the_ins.fragb[n].fragoff */) {
3251 the_ins
.reloc
[m
].n
-= 2*shorts_this_frag
/* 2*the_ins.fragb[n].fragoff */;
3254 wid
=the_ins
.reloc
[m
].wid
;
3257 the_ins
.reloc
[m
].wid
=0;
3258 wid
= (wid
=='b') ? 1 : (wid
=='w') ? 2 : (wid
=='l') ? 4 : 4000;
3261 (toP
-frag_now
->fr_literal
)-the_ins
.numo
*2+the_ins
.reloc
[m
].n
,
3263 the_ins
.reloc
[m
].add
,
3264 the_ins
.reloc
[m
].sub
,
3265 the_ins
.reloc
[m
].off
,
3266 the_ins
.reloc
[m
].pcrel
,
3269 /* know(the_ins.fragb[n].fadd); */
3270 (void)frag_var(rs_machine_dependent
,10,0,(relax_substateT
)(the_ins
.fragb
[n
].fragty
),
3271 the_ins
.fragb
[n
].fadd
,the_ins
.fragb
[n
].foff
,to_beg_P
);
3273 n
=(the_ins
.numo
-the_ins
.fragb
[n
-1].fragoff
);
3276 toP
=frag_more(n
*sizeof(short));
3278 md_number_to_chars(toP
,(long)(*fromP
),2);
3284 for(m
=0;m
<the_ins
.nrel
;m
++) {
3287 wid
=the_ins
.reloc
[m
].wid
;
3290 the_ins
.reloc
[m
].wid
=0;
3291 wid
= (wid
=='b') ? 1 : (wid
=='w') ? 2 : (wid
=='l') ? 4 : 4000;
3294 (the_ins
.reloc
[m
].n
+ toP
-frag_now
->fr_literal
)-/* the_ins.numo */ shorts_this_frag
*2,
3296 the_ins
.reloc
[m
].add
,
3297 the_ins
.reloc
[m
].sub
,
3298 the_ins
.reloc
[m
].off
,
3299 the_ins
.reloc
[m
].pcrel
,
3310 * md_begin -- set up hash tables with 68000 instructions.
3311 * similar to what the vax assembler does. ---phr
3313 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3314 a copy of it at runtime, adding in the information we want but isn't
3315 there. I think it'd be better to have an awk script hack the table
3316 at compile time. Or even just xstr the table and use it as-is. But
3317 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3320 register const struct m68k_opcode
*ins
;
3321 register struct m68k_incant
*hack
,
3323 register char *retval
= 0; /* empty string, or error msg text */
3324 register unsigned int i
;
3327 if ((op_hash
= hash_new()) == NULL
)
3328 as_fatal("Virtual memory exhausted");
3330 obstack_begin(&robyn
,4000);
3331 for (ins
= m68k_opcodes
; ins
< endop
; ins
++) {
3332 hack
=slak
=(struct m68k_incant
*)obstack_alloc(&robyn
,sizeof(struct m68k_incant
));
3334 /* we *could* ignore insns that don't match our
3335 arch here but just leaving them out of the
3337 slak
->m_operands
=ins
->args
;
3338 slak
->m_opnum
=strlen(slak
->m_operands
)/2;
3339 slak
->m_arch
= ins
->arch
;
3340 slak
->m_opcode
=ins
->opcode
;
3341 /* This is kludgey */
3342 slak
->m_codenum
=((ins
->match
)&0xffffL
) ? 2 : 1;
3343 if((ins
+1)!=endop
&& !strcmp(ins
->name
,(ins
+1)->name
)) {
3344 slak
->m_next
=(struct m68k_incant
*) obstack_alloc(&robyn
,sizeof(struct m68k_incant
));
3351 retval
= hash_insert (op_hash
, ins
->name
,(char *)hack
);
3352 /* Didn't his mommy tell him about null pointers? */
3353 if(retval
&& *retval
)
3354 as_bad("Internal Error: Can't hash %s: %s",ins
->name
,retval
);
3357 for (i
= 0; i
< sizeof(mklower_table
) ; i
++)
3358 mklower_table
[i
] = (isupper(c
= (char) i
)) ? tolower(c
) : c
;
3360 for (i
= 0 ; i
< sizeof(notend_table
) ; i
++) {
3361 notend_table
[i
] = 0;
3362 alt_notend_table
[i
] = 0;
3364 notend_table
[','] = 1;
3365 notend_table
['{'] = 1;
3366 notend_table
['}'] = 1;
3367 alt_notend_table
['a'] = 1;
3368 alt_notend_table
['A'] = 1;
3369 alt_notend_table
['d'] = 1;
3370 alt_notend_table
['D'] = 1;
3371 alt_notend_table
['#'] = 1;
3372 alt_notend_table
['f'] = 1;
3373 alt_notend_table
['F'] = 1;
3374 #ifdef REGISTER_PREFIX
3375 alt_notend_table
[REGISTER_PREFIX
] = 1;
3377 #ifdef OPTIONAL_REGISTER_PREFIX
3378 alt_notend_table
[OPTIONAL_REGISTER_PREFIX
] = 1;
3381 #ifndef MIT_SYNTAX_ONLY
3382 /* Insert pseudo ops, these have to go into the opcode table since
3383 gas expects pseudo ops to start with a dot */
3386 while (mote_pseudo_table
[n
].poc_name
)
3388 hack
=(struct m68k_incant
*)
3389 obstack_alloc(&robyn
,sizeof(struct m68k_incant
));
3390 hash_insert(op_hash
,
3391 mote_pseudo_table
[n
].poc_name
, (char *)hack
);
3392 hack
->m_operands
= 0;
3403 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3404 || (*s == ':' && strchr("aAdD#", s[1]))) \
3408 /* This funciton is called once, before the assembler exits. It is
3409 supposed to do any final cleanup for this part of the assembler.
3416 /* Equal to MAX_PRECISION in atof-ieee.c */
3417 #define MAX_LITTLENUMS 6
3419 /* Turn a string in input_line_pointer into a floating point constant of type
3420 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3421 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3424 md_atof(type
,litP
,sizeP
)
3430 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3431 LITTLENUM_TYPE
*wordP
;
3462 return "Bad call to MD_ATOF()";
3464 t
=atof_ieee(input_line_pointer
,type
,words
);
3466 input_line_pointer
=t
;
3468 *sizeP
=prec
* sizeof(LITTLENUM_TYPE
);
3469 for(wordP
=words
;prec
--;) {
3470 md_number_to_chars(litP
,(long)(*wordP
++),sizeof(LITTLENUM_TYPE
));
3471 litP
+=sizeof(LITTLENUM_TYPE
);
3473 return ""; /* Someone should teach Dean about null pointers */
3476 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3477 for use in the a.out file, and stores them in the array pointed to by buf.
3478 This knows about the endian-ness of the target machine and does
3479 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3480 2 (short) and 4 (long) Floating numbers are put out as a series of
3481 LITTLENUMS (shorts, here at least)
3484 md_number_to_chars(buf
,val
,n
)
3504 as_fatal("failed sanity check.");
3509 md_apply_fix(fixP
, val
)
3513 #ifdef IBM_COMPILER_SUX
3514 /* This is unnecessary but it convinces the native rs6000
3515 compiler to generate the code we want. */
3516 char *buf
= fixP
->fx_frag
->fr_literal
;
3517 buf
+= fixP
->fx_where
;
3518 #else /* IBM_COMPILER_SUX */
3519 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3520 #endif /* IBM_COMPILER_SUX */
3522 switch(fixP
->fx_size
) {
3537 BAD_CASE (fixP
->fx_size
);
3542 /* *fragP has been relaxed to its final size, and now needs to have
3543 the bytes inside it modified to conform to the new size There is UGLY
3547 md_convert_frag(headers
, fragP
)
3548 object_headers
*headers
;
3549 register fragS
*fragP
;
3554 /* Address in object code of the displacement. */
3555 register int object_address
= fragP
-> fr_fix
+ fragP
-> fr_address
;
3557 #ifdef IBM_COMPILER_SUX
3558 /* This is wrong but it convinces the native rs6000 compiler to
3559 generate the code we want. */
3560 register char *buffer_address
= fragP
-> fr_literal
;
3561 buffer_address
+= fragP
-> fr_fix
;
3562 #else /* IBM_COMPILER_SUX */
3563 /* Address in gas core of the place to store the displacement. */
3564 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
3565 #endif /* IBM_COMPILER_SUX */
3567 /* No longer true: know(fragP->fr_symbol); */
3569 /* The displacement of the address, from current location. */
3570 disp
= fragP
->fr_symbol
? S_GET_VALUE(fragP
->fr_symbol
) : 0;
3571 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
3573 switch(fragP
->fr_subtype
) {
3574 case TAB(BCC68000
,BYTE
):
3575 case TAB(ABRANCH
,BYTE
):
3576 know(issbyte(disp
));
3578 as_bad("short branch with zero offset: use :w");
3579 fragP
->fr_opcode
[1]=disp
;
3582 case TAB(DBCC
,SHORT
):
3583 know(issword(disp
));
3586 case TAB(BCC68000
,SHORT
):
3587 case TAB(ABRANCH
,SHORT
):
3588 know(issword(disp
));
3589 fragP
->fr_opcode
[1]=0x00;
3592 case TAB(ABRANCH
,LONG
):
3593 if (cpu_of_arch(current_architecture
) < m68020
) {
3594 if (fragP
->fr_opcode
[0]==0x61) {
3595 fragP
->fr_opcode
[0]= 0x4E;
3596 fragP
->fr_opcode
[1]= 0xB9; /* JBSR with ABSL LONG offset */
3597 subseg_change(SEG_TEXT
, 0);
3610 } else if (fragP
->fr_opcode
[0]==0x60) {
3611 fragP
->fr_opcode
[0]= 0x4E;
3612 fragP
->fr_opcode
[1]= 0xF9; /* JMP with ABSL LONG offset */
3613 subseg_change(SEG_TEXT
, 0);
3614 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
,0,
3619 as_bad("Long branch offset not supported.");
3622 fragP
->fr_opcode
[1]=0xff;
3626 case TAB(BCC68000
,LONG
):
3627 /* only Bcc 68000 instructions can come here */
3628 /* change bcc into b!cc/jmp absl long */
3629 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
3630 fragP
->fr_opcode
[1] = 0x6; /* branch offset = 6 */
3632 /* JF: these used to be fr_opcode[2,3], but they may be in a
3633 different frag, in which case refering to them is a no-no.
3634 Only fr_opcode[0,1] are guaranteed to work. */
3635 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
3636 *buffer_address
++ = 0xf9;
3637 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3638 subseg_change(SEG_TEXT
,0);
3639 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
3645 case TAB(DBCC
,LONG
):
3646 /* only DBcc 68000 instructions can come here */
3647 /* change dbcc into dbcc/jmp absl long */
3648 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3649 *buffer_address
++ = 0x00; /* branch offset = 4 */
3650 *buffer_address
++ = 0x04;
3651 *buffer_address
++ = 0x60; /* put in bra pc+6 */
3652 *buffer_address
++ = 0x06;
3653 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
3654 *buffer_address
++ = 0xf9;
3656 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
3657 subseg_change(SEG_TEXT
,0);
3658 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
3664 case TAB(FBRANCH
,SHORT
):
3665 know((fragP
->fr_opcode
[1]&0x40)==0);
3668 case TAB(FBRANCH
,LONG
):
3669 fragP
->fr_opcode
[1]|=0x40; /* Turn on LONG bit */
3672 case TAB(PCREL
,SHORT
):
3675 case TAB(PCREL
,LONG
):
3676 /* The thing to do here is force it to ABSOLUTE LONG, since
3677 PCREL is really trying to shorten an ABSOLUTE address anyway */
3678 /* JF FOO This code has not been tested */
3679 subseg_change(SEG_TEXT
,0);
3680 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0, NO_RELOC
);
3681 if((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
3682 as_bad("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
3683 fragP
->fr_opcode
[0],fragP
->fr_address
);
3684 fragP
->fr_opcode
[1]&= ~0x3F;
3685 fragP
->fr_opcode
[1]|=0x39; /* Mode 7.1 */
3687 /* md_number_to_chars(buffer_address,
3688 (long)(fragP->fr_symbol->sy_value + fragP->fr_offset),
3692 case TAB(PCLEA
,SHORT
):
3693 subseg_change(SEG_TEXT
,0);
3694 fix_new(fragP
,(int)(fragP
->fr_fix
),2,fragP
->fr_symbol
,(symbolS
*)0,fragP
->fr_offset
,1,
3696 fragP
->fr_opcode
[1] &= ~0x3F;
3697 fragP
->fr_opcode
[1] |= 0x3A;
3700 case TAB(PCLEA
,LONG
):
3701 subseg_change(SEG_TEXT
,0);
3702 fix_new(fragP
,(int)(fragP
->fr_fix
)+2,4,fragP
->fr_symbol
,(symbolS
*)0,fragP
->fr_offset
+2,1,
3704 *buffer_address
++ = 0x01;
3705 *buffer_address
++ = 0x70;
3707 /* buffer_address+=2; */
3711 } /* switch on subtype */
3714 md_number_to_chars(buffer_address
, (long) disp
, (int) ext
);
3715 fragP
->fr_fix
+= ext
;
3716 /* H_SET_TEXT_SIZE(headers, H_GET_TEXT_SIZE(headers) + ext); */
3717 } /* if extending */
3720 } /* md_convert_frag() */
3722 /* Force truly undefined symbols to their maximum size, and generally set up
3723 the frag list to be relaxed
3725 int md_estimate_size_before_relax(fragP
, segment
)
3726 register fragS
*fragP
;
3730 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
3732 old_fix
= fragP
->fr_fix
;
3734 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3735 switch (fragP
->fr_subtype
) {
3737 case TAB(ABRANCH
,SZ_UNDEF
): {
3738 if((fragP
->fr_symbol
!= NULL
) /* Not absolute */
3739 && S_GET_SEGMENT(fragP
->fr_symbol
) == segment
) {
3740 fragP
->fr_subtype
=TAB(TABTYPE(fragP
->fr_subtype
),BYTE
);
3742 } else if((fragP
->fr_symbol
== 0) || (cpu_of_arch(current_architecture
) < m68020
)) {
3743 /* On 68000, or for absolute value, switch to abs long */
3744 /* FIXME, we should check abs val, pick short or long */
3745 if(fragP
->fr_opcode
[0]==0x61) {
3746 fragP
->fr_opcode
[0]= 0x4E;
3747 fragP
->fr_opcode
[1]= 0xB9; /* JBSR with ABSL LONG offset */
3748 subseg_change(SEG_TEXT
, 0);
3749 fix_new(fragP
, fragP
->fr_fix
, 4,
3750 fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0, NO_RELOC
);
3753 } else if(fragP
->fr_opcode
[0]==0x60) {
3754 fragP
->fr_opcode
[0]= 0x4E;
3755 fragP
->fr_opcode
[1]= 0xF9; /* JMP with ABSL LONG offset */
3756 subseg_change(SEG_TEXT
, 0);
3757 fix_new(fragP
, fragP
->fr_fix
, 4,
3758 fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0, NO_RELOC
);
3762 as_warn("Long branch offset to extern symbol not supported.");
3764 } else { /* Symbol is still undefined. Make it simple */
3765 fix_new(fragP
, (int)(fragP
->fr_fix
), 4, fragP
->fr_symbol
,
3766 (symbolS
*)0, fragP
->fr_offset
+4, 1, NO_RELOC
);
3768 fragP
->fr_opcode
[1]=0xff;
3774 } /* case TAB(ABRANCH,SZ_UNDEF) */
3776 case TAB(FBRANCH
,SZ_UNDEF
): {
3777 if(S_GET_SEGMENT(fragP
->fr_symbol
) == segment
|| flagseen
['l']) {
3778 fragP
->fr_subtype
= TAB(FBRANCH
,SHORT
);
3781 fragP
->fr_subtype
= TAB(FBRANCH
,LONG
);
3785 } /* TAB(FBRANCH,SZ_UNDEF) */
3787 case TAB(PCREL
,SZ_UNDEF
): {
3788 if(S_GET_SEGMENT(fragP
->fr_symbol
) == segment
|| flagseen
['l']) {
3789 fragP
->fr_subtype
= TAB(PCREL
,SHORT
);
3792 fragP
->fr_subtype
= TAB(PCREL
,LONG
);
3796 } /* TAB(PCREL,SZ_UNDEF) */
3798 case TAB(BCC68000
,SZ_UNDEF
): {
3799 if((fragP
->fr_symbol
!= NULL
)
3800 && S_GET_SEGMENT(fragP
->fr_symbol
) == segment
) {
3801 fragP
->fr_subtype
=TAB(BCC68000
,BYTE
);
3804 /* only Bcc 68000 instructions can come here */
3805 /* change bcc into b!cc/jmp absl long */
3806 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
3808 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
3809 /* JF: these were fr_opcode[2,3] */
3810 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
3811 buffer_address
[1] = 0xf8;
3812 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3813 subseg_change(SEG_TEXT
,0);
3814 fix_new(fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, 0,
3815 fragP
->fr_offset
, 0, NO_RELOC
);
3818 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
3819 /* JF: these were fr_opcode[2,3] */
3820 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
3821 buffer_address
[1] = 0xf9;
3822 fragP
->fr_fix
+= 2; /* account for jmp instruction */
3823 subseg_change(SEG_TEXT
,0);
3824 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
3825 fragP
->fr_offset
, 0, NO_RELOC
);
3830 } /* case TAB(BCC68000,SZ_UNDEF) */
3832 case TAB(DBCC
,SZ_UNDEF
): {
3833 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT(fragP
->fr_symbol
) == segment
) {
3834 fragP
->fr_subtype
=TAB(DBCC
,SHORT
);
3838 /* only DBcc 68000 instructions can come here */
3839 /* change dbcc into dbcc/jmp absl long */
3840 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3841 buffer_address
[0] = 0x00; /* branch offset = 4 */
3842 buffer_address
[1] = 0x04;
3843 buffer_address
[2] = 0x60; /* put in bra pc + ... */
3846 /* JF: these were fr_opcode[5-7] */
3847 buffer_address
[3] = 0x04; /* plus 4 */
3848 buffer_address
[4] = 0x4e;/* Put in Jump Word */
3849 buffer_address
[5] = 0xf8;
3850 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
3851 subseg_change(SEG_TEXT
,0);
3852 fix_new(fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, 0,
3855 fragP
->fr_offset
, 0, NO_RELOC
);
3858 /* JF: these were fr_opcode[5-7] */
3859 buffer_address
[3] = 0x06; /* Plus 6 */
3860 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
3861 buffer_address
[5] = 0xf9;
3862 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
3863 subseg_change(SEG_TEXT
,0);
3864 fix_new(fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
3865 fragP
->fr_offset
, 0, NO_RELOC
);
3871 } /* case TAB(DBCC,SZ_UNDEF) */
3873 case TAB(PCLEA
,SZ_UNDEF
): {
3874 if ((S_GET_SEGMENT(fragP
->fr_symbol
))==segment
|| flagseen
['l']) {
3875 fragP
->fr_subtype
=TAB(PCLEA
,SHORT
);
3878 fragP
->fr_subtype
=TAB(PCLEA
,LONG
);
3882 } /* TAB(PCLEA,SZ_UNDEF) */
3887 } /* switch on subtype looking for SZ_UNDEF's. */
3889 /* now that SZ_UNDEF are taken care of, check others */
3890 switch (fragP
->fr_subtype
) {
3891 case TAB(BCC68000
,BYTE
):
3892 case TAB(ABRANCH
,BYTE
):
3893 /* We can't do a short jump to the next instruction,
3894 so we force word mode. */
3895 if (fragP
->fr_symbol
&& S_GET_VALUE(fragP
->fr_symbol
)==0 &&
3896 fragP
->fr_symbol
->sy_frag
==fragP
->fr_next
) {
3897 fragP
->fr_subtype
=TAB(TABTYPE(fragP
->fr_subtype
),SHORT
);
3904 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
3907 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3908 /* the bit-field entries in the relocation_info struct plays hell
3909 with the byte-order problems of cross-assembly. So as a hack,
3910 I added this mach. dependent ri twiddler. Ugly, but it gets
3912 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3913 are symbolnum, most sig. byte first. Last byte is broken up with
3914 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3915 nibble as nuthin. (on Sun 3 at least) */
3916 /* Translate the internal relocation information into target-specific
3920 md_ri_to_chars(the_bytes
, ri
)
3922 struct reloc_info_generic
*ri
;
3925 md_number_to_chars(the_bytes
, ri
->r_address
, 4);
3926 /* now the fun stuff */
3927 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
3928 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
3929 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
3930 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
3931 ((ri
->r_extern
<< 4) & 0x10));
3933 #endif /* comment */
3935 void tc_aout_fix_to_chars(where
, fixP
, segment_address_in_file
)
3938 relax_addressT segment_address_in_file
;
3941 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3942 * Out: GNU LD relocation length code: 0, 1, or 2.
3945 static unsigned char nbytes_r_length
[] = { 42, 0, 1, 42, 2 };
3948 know(fixP
->fx_addsy
!= NULL
);
3950 md_number_to_chars(where
,
3951 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
3954 r_symbolnum
= (S_IS_DEFINED(fixP
->fx_addsy
)
3955 ? S_GET_TYPE(fixP
->fx_addsy
)
3956 : fixP
->fx_addsy
->sy_number
);
3958 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
3959 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
3960 where
[6] = r_symbolnum
& 0x0ff;
3961 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
3962 (((!S_IS_DEFINED(fixP
->fx_addsy
)) << 4) & 0x10));
3965 } /* tc_aout_fix_to_chars() */
3967 #endif /* OBJ_AOUT or OBJ_BOUT */
3969 #ifndef WORKING_DOT_WORD
3970 const int md_short_jump_size
= 4;
3971 const int md_long_jump_size
= 6;
3974 md_create_short_jump(ptr
,from_addr
,to_addr
,frag
,to_symbol
)
3983 offset
= to_addr
- (from_addr
+2);
3985 md_number_to_chars(ptr
,(long)0x6000,2);
3986 md_number_to_chars(ptr
+2,(long)offset
,2);
3990 md_create_long_jump(ptr
,from_addr
,to_addr
,frag
,to_symbol
)
3999 if (cpu_of_arch(current_architecture
) < m68020
) {
4000 offset
=to_addr
-S_GET_VALUE(to_symbol
);
4001 md_number_to_chars(ptr
,(long)0x4EF9,2);
4002 md_number_to_chars(ptr
+2,(long)offset
,4);
4003 fix_new(frag
,(ptr
+2)-frag
->fr_literal
,4,to_symbol
,(symbolS
*)0,(long)0,0,
4006 offset
=to_addr
- (from_addr
+2);
4007 md_number_to_chars(ptr
,(long)0x60ff,2);
4008 md_number_to_chars(ptr
+2,(long)offset
,4);
4013 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4016 10: Absolute 1:8 only
4017 20: Absolute 0:7 only
4018 30: absolute 0:15 only
4019 40: Absolute 0:31 only
4020 50: absolute 0:127 only
4021 55: absolute -64:63 only
4022 60: absolute -128:127 only
4023 70: absolute 0:4095 only
4028 static int get_num(exp
,ok
)
4029 struct m68k_exp
*exp
;
4037 if(*exp
->e_beg
=='0') {
4038 if(exp
->e_beg
[1]=='x')
4039 sscanf(exp
->e_beg
+2,"%x",&l
);
4041 sscanf(exp
->e_beg
+1,"%O",&l
);
4044 return atol(exp
->e_beg
);
4050 /* Can't do anything */
4053 if(!exp
->e_beg
|| !exp
->e_end
) {
4054 seg(exp
)=SEG_ABSOLUTE
;
4057 offs(exp
)= (ok
==10) ? 1 : 0;
4058 as_warn("Null expression defaults to %ld",offs(exp
));
4063 if(/* ok!=80 && */ (exp
->e_end
[-1]==':' || exp
->e_end
[-1]=='.')
4064 && (exp
->e_end
-exp
->e_beg
)>=2) {
4065 switch(exp
->e_end
[0]) {
4084 if (exp
->e_end
[-1] == ':')
4085 as_bad("Unknown size for expression \"%c\"",exp
->e_end
[0]);
4089 c_save
=exp
->e_end
[1];
4091 save_in
=input_line_pointer
;
4092 input_line_pointer
=exp
->e_beg
;
4093 switch(expression(&(exp
->e_exp
))) {
4095 seg(exp
)=SEG_ABSOLUTE
;
4098 offs(exp
)= (ok
==10) ? 1 : 0;
4099 as_warn("Unknown expression: '%s' defaulting to %d",exp
->e_beg
,offs(exp
));
4103 /* Do the same thing the VAX asm does */
4104 seg(exp
)=SEG_ABSOLUTE
;
4109 as_warn("expression out of range: defaulting to 1");
4116 if(offs(exp
)<1 || offs(exp
)>8) {
4117 as_warn("expression out of range: defaulting to 1");
4122 if(offs(exp
)<0 || offs(exp
)>7)
4126 if(offs(exp
)<0 || offs(exp
)>15)
4130 if(offs(exp
)<0 || offs(exp
)>32)
4134 if(offs(exp
)<0 || offs(exp
)>127)
4138 if(offs(exp
)<-64 || offs(exp
)>63)
4142 if(offs(exp
)<-128 || offs(exp
)>127)
4146 if(offs(exp
)<0 || offs(exp
)>4095) {
4148 as_warn("expression out of range: defaulting to 0");
4157 if (offs (exp
) < 0 /* flonum */
4158 && (ok
== 80 /* no bignums */
4159 || (ok
> 10 /* small-int ranges including 0 ok */
4160 /* If we have a flonum zero, a zero integer should
4161 do as well (e.g., in moveq). */
4162 && generic_floating_point_number
.exponent
== 0
4163 && generic_floating_point_number
.low
[0] == 0)))
4165 /* HACK! Turn it into a long */
4166 LITTLENUM_TYPE words
[6];
4168 gen_to_words(words
,2,8L);/* These numbers are magic! */
4169 seg(exp
)=SEG_ABSOLUTE
;
4172 offs(exp
)=words
[1]|(words
[0]<<16);
4175 seg(exp
)=SEG_ABSOLUTE
;
4178 offs(exp
)= (ok
==10) ? 1 : 0;
4179 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp
->e_beg
,offs(exp
));
4187 case SEG_DIFFERENCE
:
4188 if(ok
>=10 && ok
<=70) {
4189 seg(exp
)=SEG_ABSOLUTE
;
4192 offs(exp
)= (ok
==10) ? 1 : 0;
4193 as_warn("Can't deal with expression \"%s\": defaulting to %ld",exp
->e_beg
,offs(exp
));
4199 if(input_line_pointer
!=exp
->e_end
+1)
4200 as_bad("Ignoring junk after expression");
4201 exp
->e_end
[1]=c_save
;
4202 input_line_pointer
=save_in
;
4204 switch(exp
->e_siz
) {
4206 if(!isbyte(offs(exp
)))
4207 as_warn("expression doesn't fit in BYTE");
4210 if(!isword(offs(exp
)))
4211 as_warn("expression doesn't fit in WORD");
4219 /* These are the back-ends for the various machine dependent pseudo-ops. */
4220 void demand_empty_rest_of_line(); /* Hate those extra verbose names */
4222 static void s_data1() {
4223 subseg_new(SEG_DATA
,1);
4224 demand_empty_rest_of_line();
4227 static void s_data2() {
4228 subseg_new(SEG_DATA
,2);
4229 demand_empty_rest_of_line();
4234 /* We don't support putting frags in the BSS segment, we fake it
4235 by marking in_bss, then looking at s_skip for clues */
4237 subseg_new(SEG_BSS
, 0);
4238 demand_empty_rest_of_line();
4241 static void s_even() {
4243 register long temp_fill
;
4245 temp
= 1; /* JF should be 2? */
4246 temp_fill
= get_absolute_expression ();
4247 if ( ! need_pass_2
) /* Never make frag if expect extra pass. */
4248 frag_align (temp
, (int)temp_fill
);
4249 demand_empty_rest_of_line();
4252 static void s_proc() {
4253 demand_empty_rest_of_line();
4256 /* s_space is defined in read.c .skip is simply an alias to it. */
4260 * Invocation line includes a switch not recognized by the base assembler.
4261 * See if it's a processor-specific option. These are:
4263 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4264 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4265 * Select the architecture. Instructions or features not
4266 * supported by the selected architecture cause fatal
4267 * errors. More than one may be specified. The default is
4268 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4269 * for -m68000, and -m68882 is a synonym for -m68881.
4270 * -[A]m[c]no-68851, -[A]m[c]no-68881
4271 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4272 * so don't use or document it, but that's the way the parsing
4275 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4276 * (e.g. m68020) also requests that float instructions be included. This
4277 * is the default setup, mostly to avoid hassling users. A better
4278 * rearrangement of this structure would be to add an option to DENY
4279 * floating point opcodes, for people who want to really know there's none
4280 * of that funny floaty stuff going on. FIXME-later.
4282 #ifndef MAYBE_FLOAT_TOO
4283 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4286 int md_parse_option(argP
,cntP
,vecP
)
4292 case 'l': /* -l means keep external to 2 bit offset
4293 rather than 16 bit one */
4296 case 'S': /* -S means that jbsr's always turn into jsr's. */
4301 /* intentional fall-through */
4307 } /* allow an optional "c" */
4309 if (!strcmp(*argP
, "68000")
4310 || !strcmp(*argP
, "68008")) {
4311 current_architecture
|= m68000
;
4312 } else if (!strcmp(*argP
, "68010")) {
4314 omagic
= 1<<16|OMAGIC
;
4316 current_architecture
|= m68010
;
4318 } else if (!strcmp(*argP
, "68020")) {
4319 current_architecture
|= m68020
| MAYBE_FLOAT_TOO
;
4321 } else if (!strcmp(*argP
, "68030")) {
4322 current_architecture
|= m68030
| MAYBE_FLOAT_TOO
;
4324 } else if (!strcmp(*argP
, "68040")) {
4325 current_architecture
|= m68040
| MAYBE_FLOAT_TOO
;
4328 } else if (!strcmp(*argP
, "68881")) {
4329 current_architecture
|= m68881
;
4331 } else if (!strcmp(*argP
, "68882")) {
4332 current_architecture
|= m68882
;
4333 #endif /* NO_68881 */
4334 /* Even if we aren't configured to support the processor,
4335 it should still be possible to assert that the user
4336 doesn't have it... */
4337 } else if (!strcmp (*argP
, "no-68881")
4338 || !strcmp (*argP
, "no-68882")) {
4341 } else if (!strcmp(*argP
,"68851")) {
4342 current_architecture
|= m68851
;
4343 #endif /* NO_68851 */
4344 } else if (!strcmp (*argP
, "no-68851")) {
4346 } else if (!strcmp (*argP
, "pu32")) { /* "-mcpu32" */
4347 current_architecture
|= cpu32
;
4349 as_warn("Unknown architecture, \"%s\". option ignored", *argP
);
4350 } /* switch on architecture */
4352 while(**argP
) (*argP
)++;
4357 if (!strcmp(*argP
,"pic")) {
4359 break; /* -pic, Position Independent Code */
4373 /* TEST2: Test md_assemble() */
4374 /* Warning, this routine probably doesn't work anymore */
4378 struct m68k_it the_ins
;
4385 if(!gets(buf
) || !*buf
)
4387 if(buf
[0]=='|' || buf
[1]=='.')
4389 for(cp
=buf
;*cp
;cp
++)
4394 memset(&the_ins
, '\0', sizeof(the_ins
));
4395 m68k_ip(&the_ins
,buf
);
4397 printf("Error %s in %s\n",the_ins
.error
,buf
);
4399 printf("Opcode(%d.%s): ",the_ins
.numo
,the_ins
.args
);
4400 for(n
=0;n
<the_ins
.numo
;n
++)
4401 printf(" 0x%x",the_ins
.opcode
[n
]&0xffff);
4403 print_the_insn(&the_ins
.opcode
[0],stdout
);
4404 (void)putchar('\n');
4406 for(n
=0;n
<strlen(the_ins
.args
)/2;n
++) {
4407 if(the_ins
.operands
[n
].error
) {
4408 printf("op%d Error %s in %s\n",n
,the_ins
.operands
[n
].error
,buf
);
4411 printf("mode %d, reg %d, ",the_ins
.operands
[n
].mode
,the_ins
.operands
[n
].reg
);
4412 if(the_ins
.operands
[n
].b_const
)
4413 printf("Constant: '%.*s', ",1+the_ins
.operands
[n
].e_const
-the_ins
.operands
[n
].b_const
,the_ins
.operands
[n
].b_const
);
4414 printf("ireg %d, isiz %d, imul %d, ",the_ins
.operands
[n
].ireg
,the_ins
.operands
[n
].isiz
,the_ins
.operands
[n
].imul
);
4415 if(the_ins
.operands
[n
].b_iadd
)
4416 printf("Iadd: '%.*s',",1+the_ins
.operands
[n
].e_iadd
-the_ins
.operands
[n
].b_iadd
,the_ins
.operands
[n
].b_iadd
);
4417 (void)putchar('\n');
4429 while(*str
&& *str
!=' ')
4431 if(str
[-1]==':' || str
[1]=='=')
4438 /* Possible states for relaxation:
4440 0 0 branch offset byte (bra, etc)
4444 1 0 indexed offsets byte a0@(32,d4:w:1) etc
4448 2 0 two-offset index word-word a0@(32,d4)@(45) etc
4467 extern fragS
*text_frag_root
;
4469 for(fragP
=text_frag_root
;fragP
;fragP
=fragP
->fr_next
) {
4470 printf("addr %lu next 0x%x fix %ld var %ld symbol 0x%x offset %ld\n",
4471 fragP
->fr_address
,fragP
->fr_next
,fragP
->fr_fix
,fragP
->fr_var
,fragP
->fr_symbol
,fragP
->fr_offset
);
4472 printf("opcode 0x%x type %d subtype %d\n\n",fragP
->fr_opcode
,fragP
->fr_type
,fragP
->fr_subtype
);
4484 fputs("Internal error:",stderr
);
4485 _doprnt(format
,&args
,stderr
);
4486 (void)putc('\n',stderr
);
4492 /* We have no need to default values of symbols. */
4496 md_undefined_symbol (name
)
4502 /* Parse an operand that is machine-specific.
4503 We just return without modifying the expression if we have nothing
4508 md_operand (expressionP
)
4509 expressionS
*expressionP
;
4513 /* Round up a section size to the appropriate boundary. */
4515 md_section_align (segment
, size
)
4519 return size
; /* Byte alignment is fine */
4522 /* Exactly what point is a PC-relative offset relative TO?
4523 On the 68k, they're relative to the address of the offset, plus
4524 its size. (??? Is this right? FIXME-SOON!) */
4526 md_pcrel_from (fixP
)
4529 return(fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
);
4533 tc_coff_symbol_emit_hook ()
4538 tc_coff_sizemachdep(frag
)
4541 switch (frag
->fr_subtype
& 0x3)
4543 case BYTE
: return 1;
4544 case SHORT
: return 2;
4545 case LONG
: return 4;
4557 /* end of tc-m68k.c */