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2000-09-14 Kazu Hirata <kazu@hxi.com>
[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 #if defined (OBJ_ELF)
31 #include "elf/m68k.h"
32 #endif
33
34 /* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38 #if defined (TE_SVR4) || defined (TE_DELTA)
39 const char *m68k_comment_chars = "|#";
40 #else
41 const char *m68k_comment_chars = "|";
42 #endif
43
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#*";
52
53 const char line_separator_chars[] = ";";
54
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 CONST char EXP_CHARS[] = "eE";
57
58 /* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
61 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
62
63 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
67 const int md_reloc_size = 8; /* Size of relocation record */
68
69 /* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
73 int flag_want_pic;
74
75 static int flag_short_refs; /* -l option */
76 static int flag_long_jumps; /* -S option */
77 static int flag_keep_pcrel; /* --pcrel option. */
78
79 #ifdef REGISTER_PREFIX_OPTIONAL
80 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
81 #else
82 int flag_reg_prefix_optional;
83 #endif
84
85 /* Whether --register-prefix-optional was used on the command line. */
86 static int reg_prefix_optional_seen;
87
88 /* The floating point coprocessor to use by default. */
89 static enum m68k_register m68k_float_copnum = COP1;
90
91 /* If this is non-zero, then references to number(%pc) will be taken
92 to refer to number, rather than to %pc + number. */
93 static int m68k_abspcadd;
94
95 /* If this is non-zero, then the quick forms of the move, add, and sub
96 instructions are used when possible. */
97 static int m68k_quick = 1;
98
99 /* If this is non-zero, then if the size is not specified for a base
100 or outer displacement, the assembler assumes that the size should
101 be 32 bits. */
102 static int m68k_rel32 = 1;
103
104 /* This is non-zero if m68k_rel32 was set from the command line. */
105 static int m68k_rel32_from_cmdline;
106
107 /* The default width to use for an index register when using a base
108 displacement. */
109 static enum m68k_size m68k_index_width_default = SIZE_LONG;
110
111 /* We want to warn if any text labels are misaligned. In order to get
112 the right line number, we need to record the line number for each
113 label. */
114
115 struct label_line
116 {
117 struct label_line *next;
118 symbolS *label;
119 char *file;
120 unsigned int line;
121 int text;
122 };
123
124 /* The list of labels. */
125
126 static struct label_line *labels;
127
128 /* The current label. */
129
130 static struct label_line *current_label;
131
132 /* Its an arbitrary name: This means I don't approve of it */
133 /* See flames below */
134 static struct obstack robyn;
135
136 #define TAB(x,y) (((x)<<2)+(y))
137 #define TABTYPE(xy) ((xy) >> 2)
138 #define BYTE 0
139 #define SHORT 1
140 #define LONG 2
141 #define SZ_UNDEF 3
142 #undef BRANCH
143 /* Case `g' except when BCC68000 is applicable. */
144 #define ABRANCH 1
145 /* Coprocessor branches. */
146 #define FBRANCH 2
147 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
148 supported on all cpus. Widens to 32-bit absolute. */
149 #define PCREL 3
150 /* For inserting an extra jmp instruction with long offset on 68000,
151 for expanding conditional branches. (Not bsr or bra.) Since the
152 68000 doesn't support 32-bit displacements for conditional
153 branches, we fake it by reversing the condition and branching
154 around a jmp with an absolute long operand. */
155 #define BCC68000 4
156 /* For the DBcc "instructions". If the displacement requires 32 bits,
157 the branch-around-a-jump game is played here too. */
158 #define DBCC 5
159 /* Not currently used? */
160 #define PCLEA 6
161 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
162 in 16 or 8 bits. */
163 #define PCINDEX 7
164
165 struct m68k_incant
166 {
167 const char *m_operands;
168 unsigned long m_opcode;
169 short m_opnum;
170 short m_codenum;
171 int m_arch;
172 struct m68k_incant *m_next;
173 };
174
175 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
176 #define gettwo(x) (((x)->m_opcode)&0xffff)
177
178 static const enum m68k_register m68000_control_regs[] = { 0 };
179 static const enum m68k_register m68010_control_regs[] = {
180 SFC, DFC, USP, VBR,
181 0
182 };
183 static const enum m68k_register m68020_control_regs[] = {
184 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
185 0
186 };
187 static const enum m68k_register m68040_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
189 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
190 0
191 };
192 static const enum m68k_register m68060_control_regs[] = {
193 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
194 USP, VBR, URP, SRP, PCR,
195 0
196 };
197 static const enum m68k_register mcf_control_regs[] = {
198 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
199 RAMBAR0, RAMBAR1, MBAR,
200 0
201 };
202 #define cpu32_control_regs m68010_control_regs
203
204 static const enum m68k_register *control_regs;
205
206 /* internal form of a 68020 instruction */
207 struct m68k_it
208 {
209 const char *error;
210 const char *args; /* list of opcode info */
211 int numargs;
212
213 int numo; /* Number of shorts in opcode */
214 short opcode[11];
215
216 struct m68k_op operands[6];
217
218 int nexp; /* number of exprs in use */
219 struct m68k_exp exprs[4];
220
221 int nfrag; /* Number of frags we have to produce */
222 struct
223 {
224 int fragoff; /* Where in the current opcode the frag ends */
225 symbolS *fadd;
226 offsetT foff;
227 int fragty;
228 }
229 fragb[4];
230
231 int nrel; /* Num of reloc strucs in use */
232 struct
233 {
234 int n;
235 expressionS exp;
236 char wid;
237 char pcrel;
238 /* In a pc relative address the difference between the address
239 of the offset and the address that the offset is relative
240 to. This depends on the addressing mode. Basically this
241 is the value to put in the offset field to address the
242 first byte of the offset, without regarding the special
243 significance of some values (in the branch instruction, for
244 example). */
245 int pcrel_fix;
246 #ifdef OBJ_ELF
247 /* Whether this expression needs special pic relocation, and if
248 so, which. */
249 enum pic_relocation pic_reloc;
250 #endif
251 }
252 reloc[5]; /* Five is enough??? */
253 };
254
255 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
256 #define float_of_arch(x) ((x) & mfloat)
257 #define mmu_of_arch(x) ((x) & mmmu)
258 #define arch_coldfire_p(x) (((x) & mcf) != 0)
259
260 /* Macros for determining if cpu supports a specific addressing mode */
261 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
262
263 static struct m68k_it the_ins; /* the instruction being assembled */
264
265 #define op(ex) ((ex)->exp.X_op)
266 #define adds(ex) ((ex)->exp.X_add_symbol)
267 #define subs(ex) ((ex)->exp.X_op_symbol)
268 #define offs(ex) ((ex)->exp.X_add_number)
269
270 /* Macros for adding things to the m68k_it struct */
271
272 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
273
274 /* Static functions. */
275
276 static void insop PARAMS ((int, const struct m68k_incant *));
277 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
278 static void add_frag PARAMS ((symbolS *, offsetT, int));
279
280 /* Like addword, but goes BEFORE general operands */
281 static void
282 insop (w, opcode)
283 int w;
284 const struct m68k_incant *opcode;
285 {
286 int z;
287 for(z=the_ins.numo;z>opcode->m_codenum;--z)
288 the_ins.opcode[z]=the_ins.opcode[z-1];
289 for(z=0;z<the_ins.nrel;z++)
290 the_ins.reloc[z].n+=2;
291 for (z = 0; z < the_ins.nfrag; z++)
292 the_ins.fragb[z].fragoff++;
293 the_ins.opcode[opcode->m_codenum]=w;
294 the_ins.numo++;
295 }
296
297 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
298 Blecch. */
299 static void
300 add_fix (width, exp, pc_rel, pc_fix)
301 int width;
302 struct m68k_exp *exp;
303 int pc_rel;
304 int pc_fix;
305 {
306 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
307 ? (the_ins.numo*2-1)
308 : (((width)=='b')
309 ? (the_ins.numo*2+1)
310 : (the_ins.numo*2)));
311 the_ins.reloc[the_ins.nrel].exp = exp->exp;
312 the_ins.reloc[the_ins.nrel].wid = width;
313 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
314 #ifdef OBJ_ELF
315 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
316 #endif
317 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
318 }
319
320 /* Cause an extra frag to be generated here, inserting up to 10 bytes
321 (that value is chosen in the frag_var call in md_assemble). TYPE
322 is the subtype of the frag to be generated; its primary type is
323 rs_machine_dependent.
324
325 The TYPE parameter is also used by md_convert_frag_1 and
326 md_estimate_size_before_relax. The appropriate type of fixup will
327 be emitted by md_convert_frag_1.
328
329 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
330 static void
331 add_frag (add, off, type)
332 symbolS *add;
333 offsetT off;
334 int type;
335 {
336 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
337 the_ins.fragb[the_ins.nfrag].fadd=add;
338 the_ins.fragb[the_ins.nfrag].foff=off;
339 the_ins.fragb[the_ins.nfrag++].fragty=type;
340 }
341
342 #define isvar(ex) \
343 (op (ex) != O_constant && op (ex) != O_big)
344
345 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
346 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
347 static void m68k_ip PARAMS ((char *));
348 static void insert_reg PARAMS ((const char *, int));
349 static void select_control_regs PARAMS ((void));
350 static void init_regtable PARAMS ((void));
351 static int reverse_16_bits PARAMS ((int in));
352 static int reverse_8_bits PARAMS ((int in));
353 static void install_gen_operand PARAMS ((int mode, int val));
354 static void install_operand PARAMS ((int mode, int val));
355 static void s_bss PARAMS ((int));
356 static void s_data1 PARAMS ((int));
357 static void s_data2 PARAMS ((int));
358 static void s_even PARAMS ((int));
359 static void s_proc PARAMS ((int));
360 static void mri_chip PARAMS ((void));
361 static void s_chip PARAMS ((int));
362 static void s_fopt PARAMS ((int));
363 static void s_opt PARAMS ((int));
364 static void s_reg PARAMS ((int));
365 static void s_restore PARAMS ((int));
366 static void s_save PARAMS ((int));
367 static void s_mri_if PARAMS ((int));
368 static void s_mri_else PARAMS ((int));
369 static void s_mri_endi PARAMS ((int));
370 static void s_mri_break PARAMS ((int));
371 static void s_mri_next PARAMS ((int));
372 static void s_mri_for PARAMS ((int));
373 static void s_mri_endf PARAMS ((int));
374 static void s_mri_repeat PARAMS ((int));
375 static void s_mri_until PARAMS ((int));
376 static void s_mri_while PARAMS ((int));
377 static void s_mri_endw PARAMS ((int));
378 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
379 static void md_convert_frag_1 PARAMS ((fragS *));
380
381 static int current_architecture;
382
383 struct m68k_cpu {
384 unsigned long arch;
385 const char *name;
386 int alias;
387 };
388
389 static const struct m68k_cpu archs[] = {
390 { m68000, "68000", 0 },
391 { m68010, "68010", 0 },
392 { m68020, "68020", 0 },
393 { m68030, "68030", 0 },
394 { m68040, "68040", 0 },
395 { m68060, "68060", 0 },
396 { cpu32, "cpu32", 0 },
397 { m68881, "68881", 0 },
398 { m68851, "68851", 0 },
399 { mcf5200, "5200", 0 },
400 { mcf5206e, "5206e", 0 },
401 { mcf5307, "5307", 0},
402 /* Aliases (effectively, so far as gas is concerned) for the above
403 cpus. */
404 { m68020, "68k", 1 },
405 { m68000, "68008", 1 },
406 { m68000, "68302", 1 },
407 { m68000, "68306", 1 },
408 { m68000, "68307", 1 },
409 { m68000, "68322", 1 },
410 { m68000, "68356", 1 },
411 { m68000, "68ec000", 1 },
412 { m68000, "68hc000", 1 },
413 { m68000, "68hc001", 1 },
414 { m68020, "68ec020", 1 },
415 { m68030, "68ec030", 1 },
416 { m68040, "68ec040", 1 },
417 { m68060, "68ec060", 1 },
418 { cpu32, "68330", 1 },
419 { cpu32, "68331", 1 },
420 { cpu32, "68332", 1 },
421 { cpu32, "68333", 1 },
422 { cpu32, "68334", 1 },
423 { cpu32, "68336", 1 },
424 { cpu32, "68340", 1 },
425 { cpu32, "68341", 1 },
426 { cpu32, "68349", 1 },
427 { cpu32, "68360", 1 },
428 { m68881, "68882", 1 },
429 { mcf5200, "5202", 1 },
430 { mcf5200, "5204", 1 },
431 { mcf5200, "5206", 1 },
432 };
433
434 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
435
436 /* BCC68000 is for patching in an extra jmp instruction for long offsets
437 on the 68000. The 68000 doesn't support long branches with branchs */
438
439 /* This table desribes how you change sizes for the various types of variable
440 size expressions. This version only supports two kinds. */
441
442 /* Note that calls to frag_var need to specify the maximum expansion
443 needed; this is currently 10 bytes for DBCC. */
444
445 /* The fields are:
446 How far Forward this mode will reach:
447 How far Backward this mode will reach:
448 How many bytes this mode will add to the size of the frag
449 Which mode to go to if the offset won't fit in this one
450 */
451 relax_typeS md_relax_table[] =
452 {
453 {1, 1, 0, 0}, /* First entries aren't used */
454 {1, 1, 0, 0}, /* For no good reason except */
455 {1, 1, 0, 0}, /* that the VAX doesn't either */
456 {1, 1, 0, 0},
457
458 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
459 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
460 {0, 0, 4, 0},
461 {1, 1, 0, 0},
462
463 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
464 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
465 {0, 0, 4, 0},
466 {1, 1, 0, 0},
467
468 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
469 {(32767), (-32768), 2, TAB (PCREL, LONG)},
470 {0, 0, 4, 0},
471 {1, 1, 0, 0},
472
473 {(127), (-128), 0, TAB (BCC68000, SHORT)},
474 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
475 {0, 0, 6, 0}, /* jmp long space */
476 {1, 1, 0, 0},
477
478 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
479 {(32767), (-32768), 2, TAB (DBCC, LONG)},
480 {0, 0, 10, 0}, /* bra/jmp long space */
481 {1, 1, 0, 0},
482
483 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
484 {32767, -32768, 2, TAB (PCLEA, LONG)},
485 {0, 0, 6, 0},
486 {1, 1, 0, 0},
487
488 /* For, e.g., jmp pcrel indexed. */
489 {125, -130, 0, TAB (PCINDEX, SHORT)},
490 {32765, -32770, 2, TAB (PCINDEX, LONG)},
491 {0, 0, 4, 0},
492 {1, 1, 0, 0},
493 };
494
495 /* These are the machine dependent pseudo-ops. These are included so
496 the assembler can work on the output from the SUN C compiler, which
497 generates these.
498 */
499
500 /* This table describes all the machine specific pseudo-ops the assembler
501 has to support. The fields are:
502 pseudo-op name without dot
503 function to call to execute this pseudo-op
504 Integer arg to pass to the function
505 */
506 const pseudo_typeS md_pseudo_table[] =
507 {
508 {"data1", s_data1, 0},
509 {"data2", s_data2, 0},
510 {"bss", s_bss, 0},
511 {"even", s_even, 0},
512 {"skip", s_space, 0},
513 {"proc", s_proc, 0},
514 #if defined (TE_SUN3) || defined (OBJ_ELF)
515 {"align", s_align_bytes, 0},
516 #endif
517 #ifdef OBJ_ELF
518 {"swbeg", s_ignore, 0},
519 #endif
520 {"extend", float_cons, 'x'},
521 {"ldouble", float_cons, 'x'},
522
523 /* The following pseudo-ops are supported for MRI compatibility. */
524 {"chip", s_chip, 0},
525 {"comline", s_space, 1},
526 {"fopt", s_fopt, 0},
527 {"mask2", s_ignore, 0},
528 {"opt", s_opt, 0},
529 {"reg", s_reg, 0},
530 {"restore", s_restore, 0},
531 {"save", s_save, 0},
532
533 {"if", s_mri_if, 0},
534 {"if.b", s_mri_if, 'b'},
535 {"if.w", s_mri_if, 'w'},
536 {"if.l", s_mri_if, 'l'},
537 {"else", s_mri_else, 0},
538 {"else.s", s_mri_else, 's'},
539 {"else.l", s_mri_else, 'l'},
540 {"endi", s_mri_endi, 0},
541 {"break", s_mri_break, 0},
542 {"break.s", s_mri_break, 's'},
543 {"break.l", s_mri_break, 'l'},
544 {"next", s_mri_next, 0},
545 {"next.s", s_mri_next, 's'},
546 {"next.l", s_mri_next, 'l'},
547 {"for", s_mri_for, 0},
548 {"for.b", s_mri_for, 'b'},
549 {"for.w", s_mri_for, 'w'},
550 {"for.l", s_mri_for, 'l'},
551 {"endf", s_mri_endf, 0},
552 {"repeat", s_mri_repeat, 0},
553 {"until", s_mri_until, 0},
554 {"until.b", s_mri_until, 'b'},
555 {"until.w", s_mri_until, 'w'},
556 {"until.l", s_mri_until, 'l'},
557 {"while", s_mri_while, 0},
558 {"while.b", s_mri_while, 'b'},
559 {"while.w", s_mri_while, 'w'},
560 {"while.l", s_mri_while, 'l'},
561 {"endw", s_mri_endw, 0},
562
563 {0, 0, 0}
564 };
565
566 /* The mote pseudo ops are put into the opcode table, since they
567 don't start with a . they look like opcodes to gas.
568 */
569
570 #ifdef M68KCOFF
571 extern void obj_coff_section PARAMS ((int));
572 #endif
573
574 CONST pseudo_typeS mote_pseudo_table[] =
575 {
576
577 {"dcl", cons, 4},
578 {"dc", cons, 2},
579 {"dcw", cons, 2},
580 {"dcb", cons, 1},
581
582 {"dsl", s_space, 4},
583 {"ds", s_space, 2},
584 {"dsw", s_space, 2},
585 {"dsb", s_space, 1},
586
587 {"xdef", s_globl, 0},
588 #ifdef OBJ_ELF
589 {"align", s_align_bytes, 0},
590 #else
591 {"align", s_align_ptwo, 0},
592 #endif
593 #ifdef M68KCOFF
594 {"sect", obj_coff_section, 0},
595 {"section", obj_coff_section, 0},
596 #endif
597 {0, 0, 0}
598 };
599
600 #define issbyte(x) ((x)>=-128 && (x)<=127)
601 #define isubyte(x) ((x)>=0 && (x)<=255)
602 #define issword(x) ((x)>=-32768 && (x)<=32767)
603 #define isuword(x) ((x)>=0 && (x)<=65535)
604
605 #define isbyte(x) ((x)>= -255 && (x)<=255)
606 #define isword(x) ((x)>=-65536 && (x)<=65535)
607 #define islong(x) (1)
608
609 extern char *input_line_pointer;
610
611 static char mklower_table[256];
612 #define mklower(c) (mklower_table[(unsigned char)(c)])
613 static char notend_table[256];
614 static char alt_notend_table[256];
615 #define notend(s) \
616 (! (notend_table[(unsigned char) *s] \
617 || (*s == ':' \
618 && alt_notend_table[(unsigned char) s[1]])))
619
620 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
621
622 #ifdef NO_PCREL_RELOCS
623
624 int
625 make_pcrel_absolute(fixP, add_number)
626 fixS *fixP;
627 long *add_number;
628 {
629 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
630
631 /* rewrite the PC relative instructions to absolute address ones.
632 * these are rumoured to be faster, and the apollo linker refuses
633 * to deal with the PC relative relocations.
634 */
635 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
636 {
637 opcode[0] = 0x4e;
638 opcode[1] = 0xf9;
639 }
640 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
641 {
642 opcode[0] = 0x4e;
643 opcode[1] = 0xb9;
644 }
645 else
646 as_fatal (_("Unknown PC relative instruction"));
647 *add_number -= 4;
648 return 0;
649 }
650
651 #endif /* NO_PCREL_RELOCS */
652
653 short
654 tc_coff_fix2rtype (fixP)
655 fixS *fixP;
656 {
657 if (fixP->fx_tcbit && fixP->fx_size == 4)
658 return R_RELLONG_NEG;
659 #ifdef NO_PCREL_RELOCS
660 know (fixP->fx_pcrel == 0);
661 return (fixP->fx_size == 1 ? R_RELBYTE
662 : fixP->fx_size == 2 ? R_DIR16
663 : R_DIR32);
664 #else
665 return (fixP->fx_pcrel ?
666 (fixP->fx_size == 1 ? R_PCRBYTE :
667 fixP->fx_size == 2 ? R_PCRWORD :
668 R_PCRLONG) :
669 (fixP->fx_size == 1 ? R_RELBYTE :
670 fixP->fx_size == 2 ? R_RELWORD :
671 R_RELLONG));
672 #endif
673 }
674
675 #endif
676
677 #ifdef OBJ_ELF
678
679 /* Compute the relocation code for a fixup of SIZE bytes, using pc
680 relative relocation if PCREL is non-zero. PIC says whether a special
681 pic relocation was requested. */
682
683 static bfd_reloc_code_real_type get_reloc_code
684 PARAMS ((int, int, enum pic_relocation));
685
686 static bfd_reloc_code_real_type
687 get_reloc_code (size, pcrel, pic)
688 int size;
689 int pcrel;
690 enum pic_relocation pic;
691 {
692 switch (pic)
693 {
694 case pic_got_pcrel:
695 switch (size)
696 {
697 case 1:
698 return BFD_RELOC_8_GOT_PCREL;
699 case 2:
700 return BFD_RELOC_16_GOT_PCREL;
701 case 4:
702 return BFD_RELOC_32_GOT_PCREL;
703 }
704 break;
705
706 case pic_got_off:
707 switch (size)
708 {
709 case 1:
710 return BFD_RELOC_8_GOTOFF;
711 case 2:
712 return BFD_RELOC_16_GOTOFF;
713 case 4:
714 return BFD_RELOC_32_GOTOFF;
715 }
716 break;
717
718 case pic_plt_pcrel:
719 switch (size)
720 {
721 case 1:
722 return BFD_RELOC_8_PLT_PCREL;
723 case 2:
724 return BFD_RELOC_16_PLT_PCREL;
725 case 4:
726 return BFD_RELOC_32_PLT_PCREL;
727 }
728 break;
729
730 case pic_plt_off:
731 switch (size)
732 {
733 case 1:
734 return BFD_RELOC_8_PLTOFF;
735 case 2:
736 return BFD_RELOC_16_PLTOFF;
737 case 4:
738 return BFD_RELOC_32_PLTOFF;
739 }
740 break;
741
742 case pic_none:
743 if (pcrel)
744 {
745 switch (size)
746 {
747 case 1:
748 return BFD_RELOC_8_PCREL;
749 case 2:
750 return BFD_RELOC_16_PCREL;
751 case 4:
752 return BFD_RELOC_32_PCREL;
753 }
754 }
755 else
756 {
757 switch (size)
758 {
759 case 1:
760 return BFD_RELOC_8;
761 case 2:
762 return BFD_RELOC_16;
763 case 4:
764 return BFD_RELOC_32;
765 }
766 }
767 }
768
769 if (pcrel)
770 {
771 if (pic == pic_none)
772 as_bad (_("Can not do %d byte pc-relative relocation"), size);
773 else
774 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
775 }
776 else
777 {
778 if (pic == pic_none)
779 as_bad (_("Can not do %d byte relocation"), size);
780 else
781 as_bad (_("Can not do %d byte pic relocation"), size);
782 }
783
784 return BFD_RELOC_NONE;
785 }
786
787 /* Here we decide which fixups can be adjusted to make them relative
788 to the beginning of the section instead of the symbol. Basically
789 we need to make sure that the dynamic relocations are done
790 correctly, so in some cases we force the original symbol to be
791 used. */
792 int
793 tc_m68k_fix_adjustable (fixP)
794 fixS *fixP;
795 {
796 /* Prevent all adjustments to global symbols. */
797 if (S_IS_EXTERNAL (fixP->fx_addsy)
798 || S_IS_WEAK (fixP->fx_addsy))
799 return 0;
800
801 /* adjust_reloc_syms doesn't know about the GOT */
802 switch (fixP->fx_r_type)
803 {
804 case BFD_RELOC_8_GOT_PCREL:
805 case BFD_RELOC_16_GOT_PCREL:
806 case BFD_RELOC_32_GOT_PCREL:
807 case BFD_RELOC_8_GOTOFF:
808 case BFD_RELOC_16_GOTOFF:
809 case BFD_RELOC_32_GOTOFF:
810 case BFD_RELOC_8_PLT_PCREL:
811 case BFD_RELOC_16_PLT_PCREL:
812 case BFD_RELOC_32_PLT_PCREL:
813 case BFD_RELOC_8_PLTOFF:
814 case BFD_RELOC_16_PLTOFF:
815 case BFD_RELOC_32_PLTOFF:
816 return 0;
817
818 case BFD_RELOC_VTABLE_INHERIT:
819 case BFD_RELOC_VTABLE_ENTRY:
820 return 0;
821
822 default:
823 return 1;
824 }
825 }
826
827 #else /* !OBJ_ELF */
828
829 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
830
831 #endif /* OBJ_ELF */
832
833 #ifdef BFD_ASSEMBLER
834
835 arelent *
836 tc_gen_reloc (section, fixp)
837 asection *section;
838 fixS *fixp;
839 {
840 arelent *reloc;
841 bfd_reloc_code_real_type code;
842
843 if (fixp->fx_tcbit)
844 abort ();
845
846 if (fixp->fx_r_type != BFD_RELOC_NONE)
847 {
848 code = fixp->fx_r_type;
849
850 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
851 that fixup_segment converted a non-PC relative reloc into a
852 PC relative reloc. In such a case, we need to convert the
853 reloc code. */
854 if (fixp->fx_pcrel)
855 {
856 switch (code)
857 {
858 case BFD_RELOC_8:
859 code = BFD_RELOC_8_PCREL;
860 break;
861 case BFD_RELOC_16:
862 code = BFD_RELOC_16_PCREL;
863 break;
864 case BFD_RELOC_32:
865 code = BFD_RELOC_32_PCREL;
866 break;
867 case BFD_RELOC_8_PCREL:
868 case BFD_RELOC_16_PCREL:
869 case BFD_RELOC_32_PCREL:
870 case BFD_RELOC_8_GOT_PCREL:
871 case BFD_RELOC_16_GOT_PCREL:
872 case BFD_RELOC_32_GOT_PCREL:
873 case BFD_RELOC_8_GOTOFF:
874 case BFD_RELOC_16_GOTOFF:
875 case BFD_RELOC_32_GOTOFF:
876 case BFD_RELOC_8_PLT_PCREL:
877 case BFD_RELOC_16_PLT_PCREL:
878 case BFD_RELOC_32_PLT_PCREL:
879 case BFD_RELOC_8_PLTOFF:
880 case BFD_RELOC_16_PLTOFF:
881 case BFD_RELOC_32_PLTOFF:
882 break;
883 default:
884 as_bad_where (fixp->fx_file, fixp->fx_line,
885 _("Cannot make %s relocation PC relative"),
886 bfd_get_reloc_code_name (code));
887 }
888 }
889 }
890 else
891 {
892 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
893 switch (F (fixp->fx_size, fixp->fx_pcrel))
894 {
895 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
896 MAP (1, 0, BFD_RELOC_8);
897 MAP (2, 0, BFD_RELOC_16);
898 MAP (4, 0, BFD_RELOC_32);
899 MAP (1, 1, BFD_RELOC_8_PCREL);
900 MAP (2, 1, BFD_RELOC_16_PCREL);
901 MAP (4, 1, BFD_RELOC_32_PCREL);
902 default:
903 abort ();
904 }
905 }
906 #undef F
907 #undef MAP
908
909 reloc = (arelent *) xmalloc (sizeof (arelent));
910 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
911 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
912 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
913 #ifndef OBJ_ELF
914 if (fixp->fx_pcrel)
915 reloc->addend = fixp->fx_addnumber;
916 else
917 reloc->addend = 0;
918 #else
919 if (!fixp->fx_pcrel)
920 reloc->addend = fixp->fx_addnumber;
921 else
922 reloc->addend = (section->vma
923 + (fixp->fx_pcrel_adjust == 64
924 ? -1 : fixp->fx_pcrel_adjust)
925 + fixp->fx_addnumber
926 + md_pcrel_from (fixp));
927 #endif
928
929 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
930 assert (reloc->howto != 0);
931
932 return reloc;
933 }
934
935 #endif /* BFD_ASSEMBLER */
936
937 /* Return zero if the reference to SYMBOL from within the same segment may
938 be relaxed. */
939 #ifdef OBJ_ELF
940
941 /* On an ELF system, we can't relax an externally visible symbol,
942 because it may be overridden by a shared library. However, if
943 TARGET_OS is "elf", then we presume that we are assembling for an
944 embedded system, in which case we don't have to worry about shared
945 libraries, and we can relax anything. */
946
947 #define relaxable_symbol(symbol) \
948 (strcmp (TARGET_OS, "elf") == 0 \
949 || (! S_IS_EXTERNAL (symbol) \
950 && ! S_IS_WEAK (symbol)))
951
952 #else
953
954 #define relaxable_symbol(symbol) 1
955
956 #endif
957
958 /* Handle of the OPCODE hash table. NULL means any use before
959 m68k_ip_begin() will crash. */
960 static struct hash_control *op_hash;
961 \f
962 /* Assemble an m68k instruction. */
963
964 static void
965 m68k_ip (instring)
966 char *instring;
967 {
968 register char *p;
969 register struct m68k_op *opP;
970 register const struct m68k_incant *opcode;
971 register const char *s;
972 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
973 char *pdot, *pdotmove;
974 enum m68k_size siz1, siz2;
975 char c;
976 int losing;
977 int opsfound;
978 LITTLENUM_TYPE words[6];
979 LITTLENUM_TYPE *wordp;
980 unsigned long ok_arch = 0;
981
982 if (*instring == ' ')
983 instring++; /* skip leading whitespace */
984
985 /* Scan up to end of operation-code, which MUST end in end-of-string
986 or exactly 1 space. */
987 pdot = 0;
988 for (p = instring; *p != '\0'; p++)
989 {
990 if (*p == ' ')
991 break;
992 if (*p == '.')
993 pdot = p;
994 }
995
996 if (p == instring)
997 {
998 the_ins.error = _("No operator");
999 return;
1000 }
1001
1002 /* p now points to the end of the opcode name, probably whitespace.
1003 Make sure the name is null terminated by clobbering the
1004 whitespace, look it up in the hash table, then fix it back.
1005 Remove a dot, first, since the opcode tables have none. */
1006 if (pdot != NULL)
1007 {
1008 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1009 *pdotmove = pdotmove[1];
1010 p--;
1011 }
1012
1013 c = *p;
1014 *p = '\0';
1015 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1016 *p = c;
1017
1018 if (pdot != NULL)
1019 {
1020 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1021 *pdotmove = pdotmove[-1];
1022 *pdot = '.';
1023 ++p;
1024 }
1025
1026 if (opcode == NULL)
1027 {
1028 the_ins.error = _("Unknown operator");
1029 return;
1030 }
1031
1032 /* found a legitimate opcode, start matching operands */
1033 while (*p == ' ')
1034 ++p;
1035
1036 if (opcode->m_operands == 0)
1037 {
1038 char *old = input_line_pointer;
1039 *old = '\n';
1040 input_line_pointer = p;
1041 /* Ahh - it's a motorola style psuedo op */
1042 mote_pseudo_table[opcode->m_opnum].poc_handler
1043 (mote_pseudo_table[opcode->m_opnum].poc_val);
1044 input_line_pointer = old;
1045 *old = 0;
1046
1047 return;
1048 }
1049
1050 if (flag_mri && opcode->m_opnum == 0)
1051 {
1052 /* In MRI mode, random garbage is allowed after an instruction
1053 which accepts no operands. */
1054 the_ins.args = opcode->m_operands;
1055 the_ins.numargs = opcode->m_opnum;
1056 the_ins.numo = opcode->m_codenum;
1057 the_ins.opcode[0] = getone (opcode);
1058 the_ins.opcode[1] = gettwo (opcode);
1059 return;
1060 }
1061
1062 for (opP = &the_ins.operands[0]; *p; opP++)
1063 {
1064 p = crack_operand (p, opP);
1065
1066 if (opP->error)
1067 {
1068 the_ins.error = opP->error;
1069 return;
1070 }
1071 }
1072
1073 opsfound = opP - &the_ins.operands[0];
1074
1075 /* This ugly hack is to support the floating pt opcodes in their
1076 standard form. Essentially, we fake a first enty of type COP#1 */
1077 if (opcode->m_operands[0] == 'I')
1078 {
1079 int n;
1080
1081 for (n = opsfound; n > 0; --n)
1082 the_ins.operands[n] = the_ins.operands[n - 1];
1083
1084 memset ((char *) (&the_ins.operands[0]), '\0',
1085 sizeof (the_ins.operands[0]));
1086 the_ins.operands[0].mode = CONTROL;
1087 the_ins.operands[0].reg = m68k_float_copnum;
1088 opsfound++;
1089 }
1090
1091 /* We've got the operands. Find an opcode that'll accept them */
1092 for (losing = 0;;)
1093 {
1094 /* If we didn't get the right number of ops, or we have no
1095 common model with this pattern then reject this pattern. */
1096
1097 ok_arch |= opcode->m_arch;
1098 if (opsfound != opcode->m_opnum
1099 || ((opcode->m_arch & current_architecture) == 0))
1100 ++losing;
1101 else
1102 {
1103 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1104 *s && !losing;
1105 s += 2, opP++)
1106 {
1107 /* Warning: this switch is huge! */
1108 /* I've tried to organize the cases into this order:
1109 non-alpha first, then alpha by letter. Lower-case
1110 goes directly before uppercase counterpart. */
1111 /* Code with multiple case ...: gets sorted by the lowest
1112 case ... it belongs to. I hope this makes sense. */
1113 switch (*s)
1114 {
1115 case '!':
1116 switch (opP->mode)
1117 {
1118 case IMMED:
1119 case DREG:
1120 case AREG:
1121 case FPREG:
1122 case CONTROL:
1123 case AINC:
1124 case ADEC:
1125 case REGLST:
1126 losing++;
1127 break;
1128 default:
1129 break;
1130 }
1131 break;
1132
1133 case '<':
1134 switch (opP->mode)
1135 {
1136 case DREG:
1137 case AREG:
1138 case FPREG:
1139 case CONTROL:
1140 case IMMED:
1141 case ADEC:
1142 case REGLST:
1143 losing++;
1144 break;
1145 default:
1146 break;
1147 }
1148 break;
1149
1150 case '>':
1151 switch (opP->mode)
1152 {
1153 case DREG:
1154 case AREG:
1155 case FPREG:
1156 case CONTROL:
1157 case IMMED:
1158 case AINC:
1159 case REGLST:
1160 losing++;
1161 break;
1162 case ABSL:
1163 break;
1164 default:
1165 if (opP->reg == PC
1166 || opP->reg == ZPC)
1167 losing++;
1168 break;
1169 }
1170 break;
1171
1172 case 'm':
1173 switch (opP->mode)
1174 {
1175 case DREG:
1176 case AREG:
1177 case AINDR:
1178 case AINC:
1179 case ADEC:
1180 break;
1181 default:
1182 losing++;
1183 }
1184 break;
1185
1186 case 'n':
1187 switch (opP->mode)
1188 {
1189 case DISP:
1190 break;
1191 default:
1192 losing++;
1193 }
1194 break;
1195
1196 case 'o':
1197 switch (opP->mode)
1198 {
1199 case BASE:
1200 case ABSL:
1201 case IMMED:
1202 break;
1203 default:
1204 losing++;
1205 }
1206 break;
1207
1208 case 'p':
1209 switch (opP->mode)
1210 {
1211 case DREG:
1212 case AREG:
1213 case AINDR:
1214 case AINC:
1215 case ADEC:
1216 break;
1217 case DISP:
1218 if (opP->reg == PC || opP->reg == ZPC)
1219 losing++;
1220 break;
1221 default:
1222 losing++;
1223 }
1224 break;
1225
1226 case 'q':
1227 switch (opP->mode)
1228 {
1229 case DREG:
1230 case AINDR:
1231 case AINC:
1232 case ADEC:
1233 break;
1234 case DISP:
1235 if (opP->reg == PC || opP->reg == ZPC)
1236 losing++;
1237 break;
1238 default:
1239 losing++;
1240 break;
1241 }
1242 break;
1243
1244 case 'v':
1245 switch (opP->mode)
1246 {
1247 case DREG:
1248 case AINDR:
1249 case AINC:
1250 case ADEC:
1251 case ABSL:
1252 break;
1253 case DISP:
1254 if (opP->reg == PC || opP->reg == ZPC)
1255 losing++;
1256 break;
1257 default:
1258 losing++;
1259 break;
1260 }
1261 break;
1262
1263 case '#':
1264 if (opP->mode != IMMED)
1265 losing++;
1266 else if (s[1] == 'b'
1267 && ! isvar (&opP->disp)
1268 && (opP->disp.exp.X_op != O_constant
1269 || ! isbyte (opP->disp.exp.X_add_number)))
1270 losing++;
1271 else if (s[1] == 'B'
1272 && ! isvar (&opP->disp)
1273 && (opP->disp.exp.X_op != O_constant
1274 || ! issbyte (opP->disp.exp.X_add_number)))
1275 losing++;
1276 else if (s[1] == 'w'
1277 && ! isvar (&opP->disp)
1278 && (opP->disp.exp.X_op != O_constant
1279 || ! isword (opP->disp.exp.X_add_number)))
1280 losing++;
1281 else if (s[1] == 'W'
1282 && ! isvar (&opP->disp)
1283 && (opP->disp.exp.X_op != O_constant
1284 || ! issword (opP->disp.exp.X_add_number)))
1285 losing++;
1286 break;
1287
1288 case '^':
1289 case 'T':
1290 if (opP->mode != IMMED)
1291 losing++;
1292 break;
1293
1294 case '$':
1295 if (opP->mode == AREG
1296 || opP->mode == CONTROL
1297 || opP->mode == FPREG
1298 || opP->mode == IMMED
1299 || opP->mode == REGLST
1300 || (opP->mode != ABSL
1301 && (opP->reg == PC
1302 || opP->reg == ZPC)))
1303 losing++;
1304 break;
1305
1306 case '%':
1307 if (opP->mode == CONTROL
1308 || opP->mode == FPREG
1309 || opP->mode == REGLST
1310 || opP->mode == IMMED
1311 || (opP->mode != ABSL
1312 && (opP->reg == PC
1313 || opP->reg == ZPC)))
1314 losing++;
1315 break;
1316
1317 case '&':
1318 switch (opP->mode)
1319 {
1320 case DREG:
1321 case AREG:
1322 case FPREG:
1323 case CONTROL:
1324 case IMMED:
1325 case AINC:
1326 case ADEC:
1327 case REGLST:
1328 losing++;
1329 break;
1330 case ABSL:
1331 break;
1332 default:
1333 if (opP->reg == PC
1334 || opP->reg == ZPC)
1335 losing++;
1336 break;
1337 }
1338 break;
1339
1340 case '*':
1341 if (opP->mode == CONTROL
1342 || opP->mode == FPREG
1343 || opP->mode == REGLST)
1344 losing++;
1345 break;
1346
1347 case '+':
1348 if (opP->mode != AINC)
1349 losing++;
1350 break;
1351
1352 case '-':
1353 if (opP->mode != ADEC)
1354 losing++;
1355 break;
1356
1357 case '/':
1358 switch (opP->mode)
1359 {
1360 case AREG:
1361 case CONTROL:
1362 case FPREG:
1363 case AINC:
1364 case ADEC:
1365 case IMMED:
1366 case REGLST:
1367 losing++;
1368 break;
1369 default:
1370 break;
1371 }
1372 break;
1373
1374 case ';':
1375 switch (opP->mode)
1376 {
1377 case AREG:
1378 case CONTROL:
1379 case FPREG:
1380 case REGLST:
1381 losing++;
1382 break;
1383 default:
1384 break;
1385 }
1386 break;
1387
1388 case '?':
1389 switch (opP->mode)
1390 {
1391 case AREG:
1392 case CONTROL:
1393 case FPREG:
1394 case AINC:
1395 case ADEC:
1396 case IMMED:
1397 case REGLST:
1398 losing++;
1399 break;
1400 case ABSL:
1401 break;
1402 default:
1403 if (opP->reg == PC || opP->reg == ZPC)
1404 losing++;
1405 break;
1406 }
1407 break;
1408
1409 case '@':
1410 switch (opP->mode)
1411 {
1412 case AREG:
1413 case CONTROL:
1414 case FPREG:
1415 case IMMED:
1416 case REGLST:
1417 losing++;
1418 break;
1419 default:
1420 break;
1421 }
1422 break;
1423
1424 case '~': /* For now! (JF FOO is this right?) */
1425 switch (opP->mode)
1426 {
1427 case DREG:
1428 case AREG:
1429 case CONTROL:
1430 case FPREG:
1431 case IMMED:
1432 case REGLST:
1433 losing++;
1434 break;
1435 case ABSL:
1436 break;
1437 default:
1438 if (opP->reg == PC
1439 || opP->reg == ZPC)
1440 losing++;
1441 break;
1442 }
1443 break;
1444
1445 case '3':
1446 if (opP->mode != CONTROL
1447 || (opP->reg != TT0 && opP->reg != TT1))
1448 losing++;
1449 break;
1450
1451 case 'A':
1452 if (opP->mode != AREG)
1453 losing++;
1454 break;
1455
1456 case 'a':
1457 if (opP->mode != AINDR)
1458 ++losing;
1459 break;
1460
1461 case 'B': /* FOO */
1462 if (opP->mode != ABSL
1463 || (flag_long_jumps
1464 && strncmp (instring, "jbsr", 4) == 0))
1465 losing++;
1466 break;
1467
1468 case 'C':
1469 if (opP->mode != CONTROL || opP->reg != CCR)
1470 losing++;
1471 break;
1472
1473 case 'd':
1474 if (opP->mode != DISP
1475 || opP->reg < ADDR0
1476 || opP->reg > ADDR7)
1477 losing++;
1478 break;
1479
1480 case 'D':
1481 if (opP->mode != DREG)
1482 losing++;
1483 break;
1484
1485 case 'E':
1486 if (opP->reg != ACC)
1487 losing++;
1488 break;
1489
1490 case 'F':
1491 if (opP->mode != FPREG)
1492 losing++;
1493 break;
1494
1495 case 'G':
1496 if (opP->reg != MACSR)
1497 losing++;
1498 break;
1499
1500 case 'H':
1501 if (opP->reg != MASK)
1502 losing++;
1503 break;
1504
1505 case 'I':
1506 if (opP->mode != CONTROL
1507 || opP->reg < COP0
1508 || opP->reg > COP7)
1509 losing++;
1510 break;
1511
1512 case 'J':
1513 if (opP->mode != CONTROL
1514 || opP->reg < USP
1515 || opP->reg > last_movec_reg)
1516 losing++;
1517 else
1518 {
1519 const enum m68k_register *rp;
1520 for (rp = control_regs; *rp; rp++)
1521 if (*rp == opP->reg)
1522 break;
1523 if (*rp == 0)
1524 losing++;
1525 }
1526 break;
1527
1528 case 'k':
1529 if (opP->mode != IMMED)
1530 losing++;
1531 break;
1532
1533 case 'l':
1534 case 'L':
1535 if (opP->mode == DREG
1536 || opP->mode == AREG
1537 || opP->mode == FPREG)
1538 {
1539 if (s[1] == '8')
1540 losing++;
1541 else
1542 {
1543 switch (opP->mode)
1544 {
1545 case DREG:
1546 opP->mask = 1 << (opP->reg - DATA0);
1547 break;
1548 case AREG:
1549 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1550 break;
1551 case FPREG:
1552 opP->mask = 1 << (opP->reg - FP0 + 16);
1553 break;
1554 default:
1555 abort ();
1556 }
1557 opP->mode = REGLST;
1558 }
1559 }
1560 else if (opP->mode == CONTROL)
1561 {
1562 if (s[1] != '8')
1563 losing++;
1564 else
1565 {
1566 switch (opP->reg)
1567 {
1568 case FPI:
1569 opP->mask = 1 << 24;
1570 break;
1571 case FPS:
1572 opP->mask = 1 << 25;
1573 break;
1574 case FPC:
1575 opP->mask = 1 << 26;
1576 break;
1577 default:
1578 losing++;
1579 break;
1580 }
1581 opP->mode = REGLST;
1582 }
1583 }
1584 else if (opP->mode != REGLST)
1585 losing++;
1586 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1587 losing++;
1588 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1589 losing++;
1590 break;
1591
1592 case 'M':
1593 if (opP->mode != IMMED)
1594 losing++;
1595 else if (opP->disp.exp.X_op != O_constant
1596 || ! issbyte (opP->disp.exp.X_add_number))
1597 losing++;
1598 else if (! m68k_quick
1599 && instring[3] != 'q'
1600 && instring[4] != 'q')
1601 losing++;
1602 break;
1603
1604 case 'O':
1605 if (opP->mode != DREG
1606 && opP->mode != IMMED
1607 && opP->mode != ABSL)
1608 losing++;
1609 break;
1610
1611 case 'Q':
1612 if (opP->mode != IMMED)
1613 losing++;
1614 else if (opP->disp.exp.X_op != O_constant
1615 || opP->disp.exp.X_add_number < 1
1616 || opP->disp.exp.X_add_number > 8)
1617 losing++;
1618 else if (! m68k_quick
1619 && (strncmp (instring, "add", 3) == 0
1620 || strncmp (instring, "sub", 3) == 0)
1621 && instring[3] != 'q')
1622 losing++;
1623 break;
1624
1625 case 'R':
1626 if (opP->mode != DREG && opP->mode != AREG)
1627 losing++;
1628 break;
1629
1630 case 'r':
1631 if (opP->mode != AINDR
1632 && (opP->mode != BASE
1633 || (opP->reg != 0
1634 && opP->reg != ZADDR0)
1635 || opP->disp.exp.X_op != O_absent
1636 || ((opP->index.reg < DATA0
1637 || opP->index.reg > DATA7)
1638 && (opP->index.reg < ADDR0
1639 || opP->index.reg > ADDR7))
1640 || opP->index.size != SIZE_UNSPEC
1641 || opP->index.scale != 1))
1642 losing++;
1643 break;
1644
1645 case 's':
1646 if (opP->mode != CONTROL
1647 || ! (opP->reg == FPI
1648 || opP->reg == FPS
1649 || opP->reg == FPC))
1650 losing++;
1651 break;
1652
1653 case 'S':
1654 if (opP->mode != CONTROL || opP->reg != SR)
1655 losing++;
1656 break;
1657
1658 case 't':
1659 if (opP->mode != IMMED)
1660 losing++;
1661 else if (opP->disp.exp.X_op != O_constant
1662 || opP->disp.exp.X_add_number < 0
1663 || opP->disp.exp.X_add_number > 7)
1664 losing++;
1665 break;
1666
1667 case 'U':
1668 if (opP->mode != CONTROL || opP->reg != USP)
1669 losing++;
1670 break;
1671
1672 /* JF these are out of order. We could put them
1673 in order if we were willing to put up with
1674 bunches of #ifdef m68851s in the code.
1675
1676 Don't forget that you need these operands
1677 to use 68030 MMU instructions. */
1678 #ifndef NO_68851
1679 /* Memory addressing mode used by pflushr */
1680 case '|':
1681 if (opP->mode == CONTROL
1682 || opP->mode == FPREG
1683 || opP->mode == DREG
1684 || opP->mode == AREG
1685 || opP->mode == REGLST)
1686 losing++;
1687 /* We should accept immediate operands, but they
1688 supposedly have to be quad word, and we don't
1689 handle that. I would like to see what a Motorola
1690 assembler does before doing something here. */
1691 if (opP->mode == IMMED)
1692 losing++;
1693 break;
1694
1695 case 'f':
1696 if (opP->mode != CONTROL
1697 || (opP->reg != SFC && opP->reg != DFC))
1698 losing++;
1699 break;
1700
1701 case '0':
1702 if (opP->mode != CONTROL || opP->reg != TC)
1703 losing++;
1704 break;
1705
1706 case '1':
1707 if (opP->mode != CONTROL || opP->reg != AC)
1708 losing++;
1709 break;
1710
1711 case '2':
1712 if (opP->mode != CONTROL
1713 || (opP->reg != CAL
1714 && opP->reg != VAL
1715 && opP->reg != SCC))
1716 losing++;
1717 break;
1718
1719 case 'V':
1720 if (opP->mode != CONTROL
1721 || opP->reg != VAL)
1722 losing++;
1723 break;
1724
1725 case 'W':
1726 if (opP->mode != CONTROL
1727 || (opP->reg != DRP
1728 && opP->reg != SRP
1729 && opP->reg != CRP))
1730 losing++;
1731 break;
1732
1733 case 'X':
1734 if (opP->mode != CONTROL
1735 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1736 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1737 losing++;
1738 break;
1739
1740 case 'Y':
1741 if (opP->mode != CONTROL || opP->reg != PSR)
1742 losing++;
1743 break;
1744
1745 case 'Z':
1746 if (opP->mode != CONTROL || opP->reg != PCSR)
1747 losing++;
1748 break;
1749 #endif
1750 case 'c':
1751 if (opP->mode != CONTROL
1752 || (opP->reg != NC
1753 && opP->reg != IC
1754 && opP->reg != DC
1755 && opP->reg != BC))
1756 {
1757 losing++;
1758 } /* not a cache specifier. */
1759 break;
1760
1761 case '_':
1762 if (opP->mode != ABSL)
1763 ++losing;
1764 break;
1765
1766 case 'u':
1767 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1768 losing++;
1769 /* FIXME: kludge instead of fixing parser:
1770 upper/lower registers are *not* CONTROL
1771 registers, but ordinary ones. */
1772 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1773 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1774 opP->mode = DREG;
1775 else
1776 opP->mode = AREG;
1777 break;
1778
1779 default:
1780 abort ();
1781 } /* switch on type of operand */
1782
1783 if (losing)
1784 break;
1785 } /* for each operand */
1786 } /* if immediately wrong */
1787
1788 if (!losing)
1789 {
1790 break;
1791 } /* got it. */
1792
1793 opcode = opcode->m_next;
1794
1795 if (!opcode)
1796 {
1797 if (ok_arch
1798 && !(ok_arch & current_architecture))
1799 {
1800 char buf[200], *cp;
1801
1802 strcpy (buf,
1803 _("invalid instruction for this architecture; needs "));
1804 cp = buf + strlen (buf);
1805 switch (ok_arch)
1806 {
1807 case mfloat:
1808 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1809 break;
1810 case mmmu:
1811 strcpy (cp, _("mmu (68030 or 68851)"));
1812 break;
1813 case m68020up:
1814 strcpy (cp, _("68020 or higher"));
1815 break;
1816 case m68000up:
1817 strcpy (cp, _("68000 or higher"));
1818 break;
1819 case m68010up:
1820 strcpy (cp, _("68010 or higher"));
1821 break;
1822 default:
1823 {
1824 int got_one = 0, idx;
1825 for (idx = 0;
1826 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1827 idx++)
1828 {
1829 if ((archs[idx].arch & ok_arch)
1830 && ! archs[idx].alias)
1831 {
1832 if (got_one)
1833 {
1834 strcpy (cp, " or ");
1835 cp += strlen (cp);
1836 }
1837 got_one = 1;
1838 strcpy (cp, archs[idx].name);
1839 cp += strlen (cp);
1840 }
1841 }
1842 }
1843 }
1844 cp = xmalloc (strlen (buf) + 1);
1845 strcpy (cp, buf);
1846 the_ins.error = cp;
1847 }
1848 else
1849 the_ins.error = _("operands mismatch");
1850 return;
1851 } /* Fell off the end */
1852
1853 losing = 0;
1854 }
1855
1856 /* now assemble it */
1857
1858 the_ins.args = opcode->m_operands;
1859 the_ins.numargs = opcode->m_opnum;
1860 the_ins.numo = opcode->m_codenum;
1861 the_ins.opcode[0] = getone (opcode);
1862 the_ins.opcode[1] = gettwo (opcode);
1863
1864 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1865 {
1866 /* This switch is a doozy.
1867 Watch the first step; its a big one! */
1868 switch (s[0])
1869 {
1870
1871 case '*':
1872 case '~':
1873 case '%':
1874 case ';':
1875 case '@':
1876 case '!':
1877 case '&':
1878 case '$':
1879 case '?':
1880 case '/':
1881 case '<':
1882 case '>':
1883 case 'm':
1884 case 'n':
1885 case 'o':
1886 case 'p':
1887 case 'q':
1888 case 'v':
1889 #ifndef NO_68851
1890 case '|':
1891 #endif
1892 switch (opP->mode)
1893 {
1894 case IMMED:
1895 tmpreg = 0x3c; /* 7.4 */
1896 if (strchr ("bwl", s[1]))
1897 nextword = get_num (&opP->disp, 80);
1898 else
1899 nextword = get_num (&opP->disp, 0);
1900 if (isvar (&opP->disp))
1901 add_fix (s[1], &opP->disp, 0, 0);
1902 switch (s[1])
1903 {
1904 case 'b':
1905 if (!isbyte (nextword))
1906 opP->error = _("operand out of range");
1907 addword (nextword);
1908 baseo = 0;
1909 break;
1910 case 'w':
1911 if (!isword (nextword))
1912 opP->error = _("operand out of range");
1913 addword (nextword);
1914 baseo = 0;
1915 break;
1916 case 'W':
1917 if (!issword (nextword))
1918 opP->error = _("operand out of range");
1919 addword (nextword);
1920 baseo = 0;
1921 break;
1922 case 'l':
1923 addword (nextword >> 16);
1924 addword (nextword);
1925 baseo = 0;
1926 break;
1927
1928 case 'f':
1929 baseo = 2;
1930 outro = 8;
1931 break;
1932 case 'F':
1933 baseo = 4;
1934 outro = 11;
1935 break;
1936 case 'x':
1937 baseo = 6;
1938 outro = 15;
1939 break;
1940 case 'p':
1941 baseo = 6;
1942 outro = -1;
1943 break;
1944 default:
1945 abort ();
1946 }
1947 if (!baseo)
1948 break;
1949
1950 /* We gotta put out some float */
1951 if (op (&opP->disp) != O_big)
1952 {
1953 valueT val;
1954 int gencnt;
1955
1956 /* Can other cases happen here? */
1957 if (op (&opP->disp) != O_constant)
1958 abort ();
1959
1960 val = (valueT) offs (&opP->disp);
1961 gencnt = 0;
1962 do
1963 {
1964 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1965 val >>= LITTLENUM_NUMBER_OF_BITS;
1966 ++gencnt;
1967 }
1968 while (val != 0);
1969 offs (&opP->disp) = gencnt;
1970 }
1971 if (offs (&opP->disp) > 0)
1972 {
1973 if (offs (&opP->disp) > baseo)
1974 {
1975 as_warn (_("Bignum too big for %c format; truncated"),
1976 s[1]);
1977 offs (&opP->disp) = baseo;
1978 }
1979 baseo -= offs (&opP->disp);
1980 while (baseo--)
1981 addword (0);
1982 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1983 offs (&opP->disp)--;
1984 --wordp)
1985 addword (*wordp);
1986 break;
1987 }
1988 gen_to_words (words, baseo, (long) outro);
1989 for (wordp = words; baseo--; wordp++)
1990 addword (*wordp);
1991 break;
1992 case DREG:
1993 tmpreg = opP->reg - DATA; /* 0.dreg */
1994 break;
1995 case AREG:
1996 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1997 break;
1998 case AINDR:
1999 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2000 break;
2001 case ADEC:
2002 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2003 break;
2004 case AINC:
2005 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2006 break;
2007 case DISP:
2008
2009 nextword = get_num (&opP->disp, 80);
2010
2011 if (opP->reg == PC
2012 && ! isvar (&opP->disp)
2013 && m68k_abspcadd)
2014 {
2015 opP->disp.exp.X_op = O_symbol;
2016 #ifndef BFD_ASSEMBLER
2017 opP->disp.exp.X_add_symbol = &abs_symbol;
2018 #else
2019 opP->disp.exp.X_add_symbol =
2020 section_symbol (absolute_section);
2021 #endif
2022 }
2023
2024 /* Force into index mode. Hope this works */
2025
2026 /* We do the first bit for 32-bit displacements, and the
2027 second bit for 16 bit ones. It is possible that we
2028 should make the default be WORD instead of LONG, but
2029 I think that'd break GCC, so we put up with a little
2030 inefficiency for the sake of working output. */
2031
2032 if (!issword (nextword)
2033 || (isvar (&opP->disp)
2034 && ((opP->disp.size == SIZE_UNSPEC
2035 && flag_short_refs == 0
2036 && cpu_of_arch (current_architecture) >= m68020
2037 && ! arch_coldfire_p (current_architecture))
2038 || opP->disp.size == SIZE_LONG)))
2039 {
2040 if (cpu_of_arch (current_architecture) < m68020
2041 || arch_coldfire_p (current_architecture))
2042 opP->error =
2043 _("displacement too large for this architecture; needs 68020 or higher");
2044 if (opP->reg == PC)
2045 tmpreg = 0x3B; /* 7.3 */
2046 else
2047 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2048 if (isvar (&opP->disp))
2049 {
2050 if (opP->reg == PC)
2051 {
2052 if (opP->disp.size == SIZE_LONG
2053 #ifdef OBJ_ELF
2054 /* If the displacement needs pic
2055 relocation it cannot be relaxed. */
2056 || opP->disp.pic_reloc != pic_none
2057 #endif
2058 )
2059 {
2060 addword (0x0170);
2061 add_fix ('l', &opP->disp, 1, 2);
2062 }
2063 else
2064 {
2065 add_frag (adds (&opP->disp),
2066 offs (&opP->disp),
2067 TAB (PCLEA, SZ_UNDEF));
2068 break;
2069 }
2070 }
2071 else
2072 {
2073 addword (0x0170);
2074 add_fix ('l', &opP->disp, 0, 0);
2075 }
2076 }
2077 else
2078 addword (0x0170);
2079 addword (nextword >> 16);
2080 }
2081 else
2082 {
2083 if (opP->reg == PC)
2084 tmpreg = 0x3A; /* 7.2 */
2085 else
2086 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2087
2088 if (isvar (&opP->disp))
2089 {
2090 if (opP->reg == PC)
2091 {
2092 add_fix ('w', &opP->disp, 1, 0);
2093 }
2094 else
2095 add_fix ('w', &opP->disp, 0, 0);
2096 }
2097 }
2098 addword (nextword);
2099 break;
2100
2101 case POST:
2102 case PRE:
2103 case BASE:
2104 nextword = 0;
2105 baseo = get_num (&opP->disp, 80);
2106 if (opP->mode == POST || opP->mode == PRE)
2107 outro = get_num (&opP->odisp, 80);
2108 /* Figure out the `addressing mode'.
2109 Also turn on the BASE_DISABLE bit, if needed. */
2110 if (opP->reg == PC || opP->reg == ZPC)
2111 {
2112 tmpreg = 0x3b; /* 7.3 */
2113 if (opP->reg == ZPC)
2114 nextword |= 0x80;
2115 }
2116 else if (opP->reg == 0)
2117 {
2118 nextword |= 0x80;
2119 tmpreg = 0x30; /* 6.garbage */
2120 }
2121 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2122 {
2123 nextword |= 0x80;
2124 tmpreg = 0x30 + opP->reg - ZADDR0;
2125 }
2126 else
2127 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2128
2129 siz1 = opP->disp.size;
2130 if (opP->mode == POST || opP->mode == PRE)
2131 siz2 = opP->odisp.size;
2132 else
2133 siz2 = SIZE_UNSPEC;
2134
2135 /* Index register stuff */
2136 if (opP->index.reg != 0
2137 && opP->index.reg >= DATA
2138 && opP->index.reg <= ADDR7)
2139 {
2140 nextword |= (opP->index.reg - DATA) << 12;
2141
2142 if (opP->index.size == SIZE_LONG
2143 || (opP->index.size == SIZE_UNSPEC
2144 && m68k_index_width_default == SIZE_LONG))
2145 nextword |= 0x800;
2146
2147 if ((opP->index.scale != 1
2148 && cpu_of_arch (current_architecture) < m68020)
2149 || (opP->index.scale == 8
2150 && arch_coldfire_p (current_architecture)))
2151 {
2152 opP->error =
2153 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2154 }
2155
2156 if (arch_coldfire_p (current_architecture)
2157 && opP->index.size == SIZE_WORD)
2158 opP->error = _("invalid index size for coldfire");
2159
2160 switch (opP->index.scale)
2161 {
2162 case 1:
2163 break;
2164 case 2:
2165 nextword |= 0x200;
2166 break;
2167 case 4:
2168 nextword |= 0x400;
2169 break;
2170 case 8:
2171 nextword |= 0x600;
2172 break;
2173 default:
2174 abort ();
2175 }
2176 /* IF its simple,
2177 GET US OUT OF HERE! */
2178
2179 /* Must be INDEX, with an index register. Address
2180 register cannot be ZERO-PC, and either :b was
2181 forced, or we know it will fit. For a 68000 or
2182 68010, force this mode anyways, because the
2183 larger modes aren't supported. */
2184 if (opP->mode == BASE
2185 && ((opP->reg >= ADDR0
2186 && opP->reg <= ADDR7)
2187 || opP->reg == PC))
2188 {
2189 if (siz1 == SIZE_BYTE
2190 || cpu_of_arch (current_architecture) < m68020
2191 || arch_coldfire_p (current_architecture)
2192 || (siz1 == SIZE_UNSPEC
2193 && ! isvar (&opP->disp)
2194 && issbyte (baseo)))
2195 {
2196 nextword += baseo & 0xff;
2197 addword (nextword);
2198 if (isvar (&opP->disp))
2199 {
2200 /* Do a byte relocation. If it doesn't
2201 fit (possible on m68000) let the
2202 fixup processing complain later. */
2203 if (opP->reg == PC)
2204 add_fix ('B', &opP->disp, 1, 1);
2205 else
2206 add_fix ('B', &opP->disp, 0, 0);
2207 }
2208 else if (siz1 != SIZE_BYTE)
2209 {
2210 if (siz1 != SIZE_UNSPEC)
2211 as_warn (_("Forcing byte displacement"));
2212 if (! issbyte (baseo))
2213 opP->error = _("byte displacement out of range");
2214 }
2215
2216 break;
2217 }
2218 else if (siz1 == SIZE_UNSPEC
2219 && opP->reg == PC
2220 && isvar (&opP->disp)
2221 && subs (&opP->disp) == NULL
2222 #ifdef OBJ_ELF
2223 /* If the displacement needs pic
2224 relocation it cannot be relaxed. */
2225 && opP->disp.pic_reloc == pic_none
2226 #endif
2227 )
2228 {
2229 /* The code in md_convert_frag_1 needs to be
2230 able to adjust nextword. Call frag_grow
2231 to ensure that we have enough space in
2232 the frag obstack to make all the bytes
2233 contiguous. */
2234 frag_grow (14);
2235 nextword += baseo & 0xff;
2236 addword (nextword);
2237 add_frag (adds (&opP->disp), offs (&opP->disp),
2238 TAB (PCINDEX, SZ_UNDEF));
2239
2240 break;
2241 }
2242 }
2243 }
2244 else
2245 {
2246 nextword |= 0x40; /* No index reg */
2247 if (opP->index.reg >= ZDATA0
2248 && opP->index.reg <= ZDATA7)
2249 nextword |= (opP->index.reg - ZDATA0) << 12;
2250 else if (opP->index.reg >= ZADDR0
2251 || opP->index.reg <= ZADDR7)
2252 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2253 }
2254
2255 /* It isn't simple. */
2256
2257 if (cpu_of_arch (current_architecture) < m68020
2258 || arch_coldfire_p (current_architecture))
2259 opP->error =
2260 _("invalid operand mode for this architecture; needs 68020 or higher");
2261
2262 nextword |= 0x100;
2263 /* If the guy specified a width, we assume that it is
2264 wide enough. Maybe it isn't. If so, we lose. */
2265 switch (siz1)
2266 {
2267 case SIZE_UNSPEC:
2268 if (isvar (&opP->disp)
2269 ? m68k_rel32
2270 : ! issword (baseo))
2271 {
2272 siz1 = SIZE_LONG;
2273 nextword |= 0x30;
2274 }
2275 else if (! isvar (&opP->disp) && baseo == 0)
2276 nextword |= 0x10;
2277 else
2278 {
2279 nextword |= 0x20;
2280 siz1 = SIZE_WORD;
2281 }
2282 break;
2283 case SIZE_BYTE:
2284 as_warn (_(":b not permitted; defaulting to :w"));
2285 /* Fall through. */
2286 case SIZE_WORD:
2287 nextword |= 0x20;
2288 break;
2289 case SIZE_LONG:
2290 nextword |= 0x30;
2291 break;
2292 }
2293
2294 /* Figure out innner displacement stuff */
2295 if (opP->mode == POST || opP->mode == PRE)
2296 {
2297 if (cpu_of_arch (current_architecture) & cpu32)
2298 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2299 switch (siz2)
2300 {
2301 case SIZE_UNSPEC:
2302 if (isvar (&opP->odisp)
2303 ? m68k_rel32
2304 : ! issword (outro))
2305 {
2306 siz2 = SIZE_LONG;
2307 nextword |= 0x3;
2308 }
2309 else if (! isvar (&opP->odisp) && outro == 0)
2310 nextword |= 0x1;
2311 else
2312 {
2313 nextword |= 0x2;
2314 siz2 = SIZE_WORD;
2315 }
2316 break;
2317 case 1:
2318 as_warn (_(":b not permitted; defaulting to :w"));
2319 /* Fall through. */
2320 case 2:
2321 nextword |= 0x2;
2322 break;
2323 case 3:
2324 nextword |= 0x3;
2325 break;
2326 }
2327 if (opP->mode == POST
2328 && (nextword & 0x40) == 0)
2329 nextword |= 0x04;
2330 }
2331 addword (nextword);
2332
2333 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2334 {
2335 if (opP->reg == PC || opP->reg == ZPC)
2336 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2337 else
2338 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2339 }
2340 if (siz1 == SIZE_LONG)
2341 addword (baseo >> 16);
2342 if (siz1 != SIZE_UNSPEC)
2343 addword (baseo);
2344
2345 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2346 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2347 if (siz2 == SIZE_LONG)
2348 addword (outro >> 16);
2349 if (siz2 != SIZE_UNSPEC)
2350 addword (outro);
2351
2352 break;
2353
2354 case ABSL:
2355 nextword = get_num (&opP->disp, 80);
2356 switch (opP->disp.size)
2357 {
2358 default:
2359 abort ();
2360 case SIZE_UNSPEC:
2361 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2362 {
2363 tmpreg = 0x38; /* 7.0 */
2364 addword (nextword);
2365 break;
2366 }
2367 if (isvar (&opP->disp)
2368 && !subs (&opP->disp)
2369 && adds (&opP->disp)
2370 #ifdef OBJ_ELF
2371 /* If the displacement needs pic relocation it
2372 cannot be relaxed. */
2373 && opP->disp.pic_reloc == pic_none
2374 #endif
2375 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2376 && relaxable_symbol (adds (&opP->disp))
2377 && !flag_long_jumps
2378 && !strchr ("~%&$?", s[0]))
2379 {
2380 tmpreg = 0x3A; /* 7.2 */
2381 add_frag (adds (&opP->disp),
2382 offs (&opP->disp),
2383 TAB (PCREL, SZ_UNDEF));
2384 break;
2385 }
2386 /* Fall through into long */
2387 case SIZE_LONG:
2388 if (isvar (&opP->disp))
2389 add_fix ('l', &opP->disp, 0, 0);
2390
2391 tmpreg = 0x39;/* 7.1 mode */
2392 addword (nextword >> 16);
2393 addword (nextword);
2394 break;
2395
2396 case SIZE_BYTE:
2397 as_bad (_("unsupported byte value; use a different suffix"));
2398 /* Fall through. */
2399 case SIZE_WORD: /* Word */
2400 if (isvar (&opP->disp))
2401 add_fix ('w', &opP->disp, 0, 0);
2402
2403 tmpreg = 0x38;/* 7.0 mode */
2404 addword (nextword);
2405 break;
2406 }
2407 break;
2408 case CONTROL:
2409 case FPREG:
2410 default:
2411 as_bad (_("unknown/incorrect operand"));
2412 /* abort(); */
2413 }
2414 install_gen_operand (s[1], tmpreg);
2415 break;
2416
2417 case '#':
2418 case '^':
2419 switch (s[1])
2420 { /* JF: I hate floating point! */
2421 case 'j':
2422 tmpreg = 70;
2423 break;
2424 case '8':
2425 tmpreg = 20;
2426 break;
2427 case 'C':
2428 tmpreg = 50;
2429 break;
2430 case '3':
2431 default:
2432 tmpreg = 80;
2433 break;
2434 }
2435 tmpreg = get_num (&opP->disp, tmpreg);
2436 if (isvar (&opP->disp))
2437 add_fix (s[1], &opP->disp, 0, 0);
2438 switch (s[1])
2439 {
2440 case 'b': /* Danger: These do no check for
2441 certain types of overflow.
2442 user beware! */
2443 if (!isbyte (tmpreg))
2444 opP->error = _("out of range");
2445 insop (tmpreg, opcode);
2446 if (isvar (&opP->disp))
2447 the_ins.reloc[the_ins.nrel - 1].n =
2448 (opcode->m_codenum) * 2 + 1;
2449 break;
2450 case 'B':
2451 if (!issbyte (tmpreg))
2452 opP->error = _("out of range");
2453 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2454 if (isvar (&opP->disp))
2455 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2456 break;
2457 case 'w':
2458 if (!isword (tmpreg))
2459 opP->error = _("out of range");
2460 insop (tmpreg, opcode);
2461 if (isvar (&opP->disp))
2462 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2463 break;
2464 case 'W':
2465 if (!issword (tmpreg))
2466 opP->error = _("out of range");
2467 insop (tmpreg, opcode);
2468 if (isvar (&opP->disp))
2469 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2470 break;
2471 case 'l':
2472 /* Because of the way insop works, we put these two out
2473 backwards. */
2474 insop (tmpreg, opcode);
2475 insop (tmpreg >> 16, opcode);
2476 if (isvar (&opP->disp))
2477 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2478 break;
2479 case '3':
2480 tmpreg &= 0xFF;
2481 case '8':
2482 case 'C':
2483 case 'j':
2484 install_operand (s[1], tmpreg);
2485 break;
2486 default:
2487 abort ();
2488 }
2489 break;
2490
2491 case '+':
2492 case '-':
2493 case 'A':
2494 case 'a':
2495 install_operand (s[1], opP->reg - ADDR);
2496 break;
2497
2498 case 'B':
2499 tmpreg = get_num (&opP->disp, 80);
2500 switch (s[1])
2501 {
2502 case 'B':
2503 /* The pc_fix argument winds up in fx_pcrel_adjust,
2504 which is a char, and may therefore be unsigned. We
2505 want to pass -1, but we pass 64 instead, and convert
2506 back in md_pcrel_from. */
2507 add_fix ('B', &opP->disp, 1, 64);
2508 break;
2509 case 'W':
2510 add_fix ('w', &opP->disp, 1, 0);
2511 addword (0);
2512 break;
2513 case 'L':
2514 long_branch:
2515 if (!HAVE_LONG_BRANCH(current_architecture))
2516 as_warn (_("Can't use long branches on 68000/68010/5200"));
2517 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2518 add_fix ('l', &opP->disp, 1, 0);
2519 addword (0);
2520 addword (0);
2521 break;
2522 case 'g':
2523 if (subs (&opP->disp)) /* We can't relax it */
2524 goto long_branch;
2525
2526 #ifdef OBJ_ELF
2527 /* If the displacement needs pic relocation it cannot be
2528 relaxed. */
2529 if (opP->disp.pic_reloc != pic_none)
2530 goto long_branch;
2531 #endif
2532
2533 /* This could either be a symbol, or an absolute
2534 address. No matter, the frag hacking will finger it
2535 out. Not quite: it can't switch from BRANCH to
2536 BCC68000 for the case where opnd is absolute (it
2537 needs to use the 68000 hack since no conditional abs
2538 jumps). */
2539 if (( !HAVE_LONG_BRANCH(current_architecture)
2540 || (0 == adds (&opP->disp)))
2541 && (the_ins.opcode[0] >= 0x6200)
2542 && (the_ins.opcode[0] <= 0x6f00))
2543 add_frag (adds (&opP->disp), offs (&opP->disp),
2544 TAB (BCC68000, SZ_UNDEF));
2545 else
2546 add_frag (adds (&opP->disp), offs (&opP->disp),
2547 TAB (ABRANCH, SZ_UNDEF));
2548 break;
2549 case 'w':
2550 if (isvar (&opP->disp))
2551 {
2552 #if 1
2553 /* check for DBcc instruction */
2554 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2555 {
2556 /* size varies if patch */
2557 /* needed for long form */
2558 add_frag (adds (&opP->disp), offs (&opP->disp),
2559 TAB (DBCC, SZ_UNDEF));
2560 break;
2561 }
2562 #endif
2563 add_fix ('w', &opP->disp, 1, 0);
2564 }
2565 addword (0);
2566 break;
2567 case 'C': /* Fixed size LONG coproc branches */
2568 add_fix ('l', &opP->disp, 1, 0);
2569 addword (0);
2570 addword (0);
2571 break;
2572 case 'c': /* Var size Coprocesssor branches */
2573 if (subs (&opP->disp))
2574 {
2575 add_fix ('l', &opP->disp, 1, 0);
2576 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2577 }
2578 else if (adds (&opP->disp))
2579 add_frag (adds (&opP->disp), offs (&opP->disp),
2580 TAB (FBRANCH, SZ_UNDEF));
2581 else
2582 {
2583 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2584 TAB(FBRANCH,SHORT)); */
2585 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2586 add_fix ('l', &opP->disp, 1, 0);
2587 addword (0);
2588 addword (0);
2589 }
2590 break;
2591 default:
2592 abort ();
2593 }
2594 break;
2595
2596 case 'C': /* Ignore it */
2597 break;
2598
2599 case 'd': /* JF this is a kludge */
2600 install_operand ('s', opP->reg - ADDR);
2601 tmpreg = get_num (&opP->disp, 80);
2602 if (!issword (tmpreg))
2603 {
2604 as_warn (_("Expression out of range, using 0"));
2605 tmpreg = 0;
2606 }
2607 addword (tmpreg);
2608 break;
2609
2610 case 'D':
2611 install_operand (s[1], opP->reg - DATA);
2612 break;
2613
2614 case 'E': /* Ignore it */
2615 break;
2616
2617 case 'F':
2618 install_operand (s[1], opP->reg - FP0);
2619 break;
2620
2621 case 'G': /* Ignore it */
2622 case 'H':
2623 break;
2624
2625 case 'I':
2626 tmpreg = opP->reg - COP0;
2627 install_operand (s[1], tmpreg);
2628 break;
2629
2630 case 'J': /* JF foo */
2631 switch (opP->reg)
2632 {
2633 case SFC:
2634 tmpreg = 0x000;
2635 break;
2636 case DFC:
2637 tmpreg = 0x001;
2638 break;
2639 case CACR:
2640 tmpreg = 0x002;
2641 break;
2642 case TC:
2643 tmpreg = 0x003;
2644 break;
2645 case ITT0:
2646 tmpreg = 0x004;
2647 break;
2648 case ITT1:
2649 tmpreg = 0x005;
2650 break;
2651 case DTT0:
2652 tmpreg = 0x006;
2653 break;
2654 case DTT1:
2655 tmpreg = 0x007;
2656 break;
2657 case BUSCR:
2658 tmpreg = 0x008;
2659 break;
2660
2661 case USP:
2662 tmpreg = 0x800;
2663 break;
2664 case VBR:
2665 tmpreg = 0x801;
2666 break;
2667 case CAAR:
2668 tmpreg = 0x802;
2669 break;
2670 case MSP:
2671 tmpreg = 0x803;
2672 break;
2673 case ISP:
2674 tmpreg = 0x804;
2675 break;
2676 case MMUSR:
2677 tmpreg = 0x805;
2678 break;
2679 case URP:
2680 tmpreg = 0x806;
2681 break;
2682 case SRP:
2683 tmpreg = 0x807;
2684 break;
2685 case PCR:
2686 tmpreg = 0x808;
2687 break;
2688 case ROMBAR:
2689 tmpreg = 0xC00;
2690 break;
2691 case RAMBAR0:
2692 tmpreg = 0xC04;
2693 break;
2694 case RAMBAR1:
2695 tmpreg = 0xC05;
2696 break;
2697 case MBAR:
2698 tmpreg = 0xC0F;
2699 break;
2700 default:
2701 abort ();
2702 }
2703 install_operand (s[1], tmpreg);
2704 break;
2705
2706 case 'k':
2707 tmpreg = get_num (&opP->disp, 55);
2708 install_operand (s[1], tmpreg & 0x7f);
2709 break;
2710
2711 case 'l':
2712 tmpreg = opP->mask;
2713 if (s[1] == 'w')
2714 {
2715 if (tmpreg & 0x7FF0000)
2716 as_bad (_("Floating point register in register list"));
2717 insop (reverse_16_bits (tmpreg), opcode);
2718 }
2719 else
2720 {
2721 if (tmpreg & 0x700FFFF)
2722 as_bad (_("Wrong register in floating-point reglist"));
2723 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2724 }
2725 break;
2726
2727 case 'L':
2728 tmpreg = opP->mask;
2729 if (s[1] == 'w')
2730 {
2731 if (tmpreg & 0x7FF0000)
2732 as_bad (_("Floating point register in register list"));
2733 insop (tmpreg, opcode);
2734 }
2735 else if (s[1] == '8')
2736 {
2737 if (tmpreg & 0x0FFFFFF)
2738 as_bad (_("incorrect register in reglist"));
2739 install_operand (s[1], tmpreg >> 24);
2740 }
2741 else
2742 {
2743 if (tmpreg & 0x700FFFF)
2744 as_bad (_("wrong register in floating-point reglist"));
2745 else
2746 install_operand (s[1], tmpreg >> 16);
2747 }
2748 break;
2749
2750 case 'M':
2751 install_operand (s[1], get_num (&opP->disp, 60));
2752 break;
2753
2754 case 'O':
2755 tmpreg = ((opP->mode == DREG)
2756 ? 0x20 + (int) (opP->reg - DATA)
2757 : (get_num (&opP->disp, 40) & 0x1F));
2758 install_operand (s[1], tmpreg);
2759 break;
2760
2761 case 'Q':
2762 tmpreg = get_num (&opP->disp, 10);
2763 if (tmpreg == 8)
2764 tmpreg = 0;
2765 install_operand (s[1], tmpreg);
2766 break;
2767
2768 case 'R':
2769 /* This depends on the fact that ADDR registers are eight
2770 more than their corresponding DATA regs, so the result
2771 will have the ADDR_REG bit set */
2772 install_operand (s[1], opP->reg - DATA);
2773 break;
2774
2775 case 'r':
2776 if (opP->mode == AINDR)
2777 install_operand (s[1], opP->reg - DATA);
2778 else
2779 install_operand (s[1], opP->index.reg - DATA);
2780 break;
2781
2782 case 's':
2783 if (opP->reg == FPI)
2784 tmpreg = 0x1;
2785 else if (opP->reg == FPS)
2786 tmpreg = 0x2;
2787 else if (opP->reg == FPC)
2788 tmpreg = 0x4;
2789 else
2790 abort ();
2791 install_operand (s[1], tmpreg);
2792 break;
2793
2794 case 'S': /* Ignore it */
2795 break;
2796
2797 case 'T':
2798 install_operand (s[1], get_num (&opP->disp, 30));
2799 break;
2800
2801 case 'U': /* Ignore it */
2802 break;
2803
2804 case 'c':
2805 switch (opP->reg)
2806 {
2807 case NC:
2808 tmpreg = 0;
2809 break;
2810 case DC:
2811 tmpreg = 1;
2812 break;
2813 case IC:
2814 tmpreg = 2;
2815 break;
2816 case BC:
2817 tmpreg = 3;
2818 break;
2819 default:
2820 as_fatal (_("failed sanity check"));
2821 } /* switch on cache token */
2822 install_operand (s[1], tmpreg);
2823 break;
2824 #ifndef NO_68851
2825 /* JF: These are out of order, I fear. */
2826 case 'f':
2827 switch (opP->reg)
2828 {
2829 case SFC:
2830 tmpreg = 0;
2831 break;
2832 case DFC:
2833 tmpreg = 1;
2834 break;
2835 default:
2836 abort ();
2837 }
2838 install_operand (s[1], tmpreg);
2839 break;
2840
2841 case '0':
2842 case '1':
2843 case '2':
2844 switch (opP->reg)
2845 {
2846 case TC:
2847 tmpreg = 0;
2848 break;
2849 case CAL:
2850 tmpreg = 4;
2851 break;
2852 case VAL:
2853 tmpreg = 5;
2854 break;
2855 case SCC:
2856 tmpreg = 6;
2857 break;
2858 case AC:
2859 tmpreg = 7;
2860 break;
2861 default:
2862 abort ();
2863 }
2864 install_operand (s[1], tmpreg);
2865 break;
2866
2867 case 'V':
2868 if (opP->reg == VAL)
2869 break;
2870 abort ();
2871
2872 case 'W':
2873 switch (opP->reg)
2874 {
2875 case DRP:
2876 tmpreg = 1;
2877 break;
2878 case SRP:
2879 tmpreg = 2;
2880 break;
2881 case CRP:
2882 tmpreg = 3;
2883 break;
2884 default:
2885 abort ();
2886 }
2887 install_operand (s[1], tmpreg);
2888 break;
2889
2890 case 'X':
2891 switch (opP->reg)
2892 {
2893 case BAD:
2894 case BAD + 1:
2895 case BAD + 2:
2896 case BAD + 3:
2897 case BAD + 4:
2898 case BAD + 5:
2899 case BAD + 6:
2900 case BAD + 7:
2901 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2902 break;
2903
2904 case BAC:
2905 case BAC + 1:
2906 case BAC + 2:
2907 case BAC + 3:
2908 case BAC + 4:
2909 case BAC + 5:
2910 case BAC + 6:
2911 case BAC + 7:
2912 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2913 break;
2914
2915 default:
2916 abort ();
2917 }
2918 install_operand (s[1], tmpreg);
2919 break;
2920 case 'Y':
2921 know (opP->reg == PSR);
2922 break;
2923 case 'Z':
2924 know (opP->reg == PCSR);
2925 break;
2926 #endif /* m68851 */
2927 case '3':
2928 switch (opP->reg)
2929 {
2930 case TT0:
2931 tmpreg = 2;
2932 break;
2933 case TT1:
2934 tmpreg = 3;
2935 break;
2936 default:
2937 abort ();
2938 }
2939 install_operand (s[1], tmpreg);
2940 break;
2941 case 't':
2942 tmpreg = get_num (&opP->disp, 20);
2943 install_operand (s[1], tmpreg);
2944 break;
2945 case '_': /* used only for move16 absolute 32-bit address */
2946 if (isvar (&opP->disp))
2947 add_fix ('l', &opP->disp, 0, 0);
2948 tmpreg = get_num (&opP->disp, 80);
2949 addword (tmpreg >> 16);
2950 addword (tmpreg & 0xFFFF);
2951 break;
2952 case 'u':
2953 install_operand (s[1], opP->reg - DATA0L);
2954 opP->reg -= (DATA0L);
2955 opP->reg &= 0x0F; /* remove upper/lower bit */
2956 break;
2957 default:
2958 abort ();
2959 }
2960 }
2961
2962 /* By the time whe get here (FINALLY) the_ins contains the complete
2963 instruction, ready to be emitted. . . */
2964 }
2965
2966 static int
2967 reverse_16_bits (in)
2968 int in;
2969 {
2970 int out = 0;
2971 int n;
2972
2973 static int mask[16] =
2974 {
2975 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2976 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2977 };
2978 for (n = 0; n < 16; n++)
2979 {
2980 if (in & mask[n])
2981 out |= mask[15 - n];
2982 }
2983 return out;
2984 } /* reverse_16_bits() */
2985
2986 static int
2987 reverse_8_bits (in)
2988 int in;
2989 {
2990 int out = 0;
2991 int n;
2992
2993 static int mask[8] =
2994 {
2995 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2996 };
2997
2998 for (n = 0; n < 8; n++)
2999 {
3000 if (in & mask[n])
3001 out |= mask[7 - n];
3002 }
3003 return out;
3004 } /* reverse_8_bits() */
3005
3006 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3007 (that value is chosen in the frag_var call in md_assemble). TYPE
3008 is the subtype of the frag to be generated; its primary type is
3009 rs_machine_dependent.
3010
3011 The TYPE parameter is also used by md_convert_frag_1 and
3012 md_estimate_size_before_relax. The appropriate type of fixup will
3013 be emitted by md_convert_frag_1.
3014
3015 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3016 static void
3017 install_operand (mode, val)
3018 int mode;
3019 int val;
3020 {
3021 switch (mode)
3022 {
3023 case 's':
3024 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3025 break;
3026 case 'd':
3027 the_ins.opcode[0] |= val << 9;
3028 break;
3029 case '1':
3030 the_ins.opcode[1] |= val << 12;
3031 break;
3032 case '2':
3033 the_ins.opcode[1] |= val << 6;
3034 break;
3035 case '3':
3036 the_ins.opcode[1] |= val;
3037 break;
3038 case '4':
3039 the_ins.opcode[2] |= val << 12;
3040 break;
3041 case '5':
3042 the_ins.opcode[2] |= val << 6;
3043 break;
3044 case '6':
3045 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3046 three words long! */
3047 the_ins.numo++;
3048 the_ins.opcode[2] |= val;
3049 break;
3050 case '7':
3051 the_ins.opcode[1] |= val << 7;
3052 break;
3053 case '8':
3054 the_ins.opcode[1] |= val << 10;
3055 break;
3056 #ifndef NO_68851
3057 case '9':
3058 the_ins.opcode[1] |= val << 5;
3059 break;
3060 #endif
3061
3062 case 't':
3063 the_ins.opcode[1] |= (val << 10) | (val << 7);
3064 break;
3065 case 'D':
3066 the_ins.opcode[1] |= (val << 12) | val;
3067 break;
3068 case 'g':
3069 the_ins.opcode[0] |= val = 0xff;
3070 break;
3071 case 'i':
3072 the_ins.opcode[0] |= val << 9;
3073 break;
3074 case 'C':
3075 the_ins.opcode[1] |= val;
3076 break;
3077 case 'j':
3078 the_ins.opcode[1] |= val;
3079 the_ins.numo++; /* What a hack */
3080 break;
3081 case 'k':
3082 the_ins.opcode[1] |= val << 4;
3083 break;
3084 case 'b':
3085 case 'w':
3086 case 'W':
3087 case 'l':
3088 break;
3089 case 'e':
3090 the_ins.opcode[0] |= (val << 6);
3091 break;
3092 case 'L':
3093 the_ins.opcode[1] = (val >> 16);
3094 the_ins.opcode[2] = val & 0xffff;
3095 break;
3096 case 'm':
3097 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3098 the_ins.opcode[0] |= ((val & 0x7) << 9);
3099 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3100 break;
3101 case 'n':
3102 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3103 the_ins.opcode[0] |= ((val & 0x7) << 9);
3104 break;
3105 case 'o':
3106 the_ins.opcode[1] |= val << 12;
3107 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3108 break;
3109 case 'M':
3110 the_ins.opcode[0] |= (val & 0xF);
3111 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3112 break;
3113 case 'N':
3114 the_ins.opcode[1] |= (val & 0xF);
3115 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3116 break;
3117 case 'h':
3118 the_ins.opcode[1] |= ((val != 1) << 10);
3119 break;
3120 case 'c':
3121 default:
3122 as_fatal (_("failed sanity check."));
3123 }
3124 } /* install_operand() */
3125
3126 static void
3127 install_gen_operand (mode, val)
3128 int mode;
3129 int val;
3130 {
3131 switch (mode)
3132 {
3133 case 's':
3134 the_ins.opcode[0] |= val;
3135 break;
3136 case 'd':
3137 /* This is a kludge!!! */
3138 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3139 break;
3140 case 'b':
3141 case 'w':
3142 case 'l':
3143 case 'f':
3144 case 'F':
3145 case 'x':
3146 case 'p':
3147 the_ins.opcode[0] |= val;
3148 break;
3149 /* more stuff goes here */
3150 default:
3151 as_fatal (_("failed sanity check."));
3152 }
3153 } /* install_gen_operand() */
3154
3155 /*
3156 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3157 * then deal with the bitfield hack.
3158 */
3159
3160 static char *
3161 crack_operand (str, opP)
3162 register char *str;
3163 register struct m68k_op *opP;
3164 {
3165 register int parens;
3166 register int c;
3167 register char *beg_str;
3168 int inquote = 0;
3169
3170 if (!str)
3171 {
3172 return str;
3173 }
3174 beg_str = str;
3175 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3176 {
3177 if (! inquote)
3178 {
3179 if (*str == '(')
3180 parens++;
3181 else if (*str == ')')
3182 {
3183 if (!parens)
3184 { /* ERROR */
3185 opP->error = _("Extra )");
3186 return str;
3187 }
3188 --parens;
3189 }
3190 }
3191 if (flag_mri && *str == '\'')
3192 inquote = ! inquote;
3193 }
3194 if (!*str && parens)
3195 { /* ERROR */
3196 opP->error = _("Missing )");
3197 return str;
3198 }
3199 c = *str;
3200 *str = '\0';
3201 if (m68k_ip_op (beg_str, opP) != 0)
3202 {
3203 *str = c;
3204 return str;
3205 }
3206 *str = c;
3207 if (c == '}')
3208 c = *++str; /* JF bitfield hack */
3209 if (c)
3210 {
3211 c = *++str;
3212 if (!c)
3213 as_bad (_("Missing operand"));
3214 }
3215
3216 /* Detect MRI REG symbols and convert them to REGLSTs. */
3217 if (opP->mode == CONTROL && (int)opP->reg < 0)
3218 {
3219 opP->mode = REGLST;
3220 opP->mask = ~(int)opP->reg;
3221 opP->reg = 0;
3222 }
3223
3224 return str;
3225 }
3226
3227 /* This is the guts of the machine-dependent assembler. STR points to a
3228 machine dependent instruction. This function is supposed to emit
3229 the frags/bytes it assembles to.
3230 */
3231
3232 static void
3233 insert_reg (regname, regnum)
3234 const char *regname;
3235 int regnum;
3236 {
3237 char buf[100];
3238 int i;
3239
3240 #ifdef REGISTER_PREFIX
3241 if (!flag_reg_prefix_optional)
3242 {
3243 buf[0] = REGISTER_PREFIX;
3244 strcpy (buf + 1, regname);
3245 regname = buf;
3246 }
3247 #endif
3248
3249 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3250 &zero_address_frag));
3251
3252 for (i = 0; regname[i]; i++)
3253 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3254 buf[i] = '\0';
3255
3256 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3257 &zero_address_frag));
3258 }
3259
3260 struct init_entry
3261 {
3262 const char *name;
3263 int number;
3264 };
3265
3266 static const struct init_entry init_table[] =
3267 {
3268 { "d0", DATA0 },
3269 { "d1", DATA1 },
3270 { "d2", DATA2 },
3271 { "d3", DATA3 },
3272 { "d4", DATA4 },
3273 { "d5", DATA5 },
3274 { "d6", DATA6 },
3275 { "d7", DATA7 },
3276 { "a0", ADDR0 },
3277 { "a1", ADDR1 },
3278 { "a2", ADDR2 },
3279 { "a3", ADDR3 },
3280 { "a4", ADDR4 },
3281 { "a5", ADDR5 },
3282 { "a6", ADDR6 },
3283 { "fp", ADDR6 },
3284 { "a7", ADDR7 },
3285 { "sp", ADDR7 },
3286 { "ssp", ADDR7 },
3287 { "fp0", FP0 },
3288 { "fp1", FP1 },
3289 { "fp2", FP2 },
3290 { "fp3", FP3 },
3291 { "fp4", FP4 },
3292 { "fp5", FP5 },
3293 { "fp6", FP6 },
3294 { "fp7", FP7 },
3295 { "fpi", FPI },
3296 { "fpiar", FPI },
3297 { "fpc", FPI },
3298 { "fps", FPS },
3299 { "fpsr", FPS },
3300 { "fpc", FPC },
3301 { "fpcr", FPC },
3302 { "control", FPC },
3303 { "status", FPS },
3304 { "iaddr", FPI },
3305
3306 { "cop0", COP0 },
3307 { "cop1", COP1 },
3308 { "cop2", COP2 },
3309 { "cop3", COP3 },
3310 { "cop4", COP4 },
3311 { "cop5", COP5 },
3312 { "cop6", COP6 },
3313 { "cop7", COP7 },
3314 { "pc", PC },
3315 { "zpc", ZPC },
3316 { "sr", SR },
3317
3318 { "ccr", CCR },
3319 { "cc", CCR },
3320
3321 { "acc", ACC },
3322 { "macsr", MACSR },
3323 { "mask", MASK },
3324
3325 /* control registers */
3326 { "sfc", SFC }, /* Source Function Code */
3327 { "sfcr", SFC },
3328 { "dfc", DFC }, /* Destination Function Code */
3329 { "dfcr", DFC },
3330 { "cacr", CACR }, /* Cache Control Register */
3331 { "caar", CAAR }, /* Cache Address Register */
3332
3333 { "usp", USP }, /* User Stack Pointer */
3334 { "vbr", VBR }, /* Vector Base Register */
3335 { "msp", MSP }, /* Master Stack Pointer */
3336 { "isp", ISP }, /* Interrupt Stack Pointer */
3337
3338 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3339 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3340 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3341 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3342
3343 /* 68ec040 versions of same */
3344 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3345 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3346 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3347 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3348
3349 /* mcf5200 versions of same. The ColdFire programmer's reference
3350 manual indicated that the order is 2,3,0,1, but Ken Rose
3351 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3352 { "acr0", ITT0 }, /* Access Control Unit 0 */
3353 { "acr1", ITT1 }, /* Access Control Unit 1 */
3354 { "acr2", DTT0 }, /* Access Control Unit 2 */
3355 { "acr3", DTT1 }, /* Access Control Unit 3 */
3356
3357 { "tc", TC }, /* MMU Translation Control Register */
3358 { "tcr", TC },
3359
3360 { "mmusr", MMUSR }, /* MMU Status Register */
3361 { "srp", SRP }, /* User Root Pointer */
3362 { "urp", URP }, /* Supervisor Root Pointer */
3363
3364 { "buscr", BUSCR },
3365 { "pcr", PCR },
3366
3367 { "rombar", ROMBAR }, /* ROM Base Address Register */
3368 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3369 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3370 { "mbar", MBAR }, /* Module Base Address Register */
3371 /* end of control registers */
3372
3373 { "ac", AC },
3374 { "bc", BC },
3375 { "cal", CAL },
3376 { "crp", CRP },
3377 { "drp", DRP },
3378 { "pcsr", PCSR },
3379 { "psr", PSR },
3380 { "scc", SCC },
3381 { "val", VAL },
3382 { "bad0", BAD0 },
3383 { "bad1", BAD1 },
3384 { "bad2", BAD2 },
3385 { "bad3", BAD3 },
3386 { "bad4", BAD4 },
3387 { "bad5", BAD5 },
3388 { "bad6", BAD6 },
3389 { "bad7", BAD7 },
3390 { "bac0", BAC0 },
3391 { "bac1", BAC1 },
3392 { "bac2", BAC2 },
3393 { "bac3", BAC3 },
3394 { "bac4", BAC4 },
3395 { "bac5", BAC5 },
3396 { "bac6", BAC6 },
3397 { "bac7", BAC7 },
3398
3399 { "ic", IC },
3400 { "dc", DC },
3401 { "nc", NC },
3402
3403 { "tt0", TT0 },
3404 { "tt1", TT1 },
3405 /* 68ec030 versions of same */
3406 { "ac0", TT0 },
3407 { "ac1", TT1 },
3408 /* 68ec030 access control unit, identical to 030 MMU status reg */
3409 { "acusr", PSR },
3410
3411 /* Suppressed data and address registers. */
3412 { "zd0", ZDATA0 },
3413 { "zd1", ZDATA1 },
3414 { "zd2", ZDATA2 },
3415 { "zd3", ZDATA3 },
3416 { "zd4", ZDATA4 },
3417 { "zd5", ZDATA5 },
3418 { "zd6", ZDATA6 },
3419 { "zd7", ZDATA7 },
3420 { "za0", ZADDR0 },
3421 { "za1", ZADDR1 },
3422 { "za2", ZADDR2 },
3423 { "za3", ZADDR3 },
3424 { "za4", ZADDR4 },
3425 { "za5", ZADDR5 },
3426 { "za6", ZADDR6 },
3427 { "za7", ZADDR7 },
3428
3429 /* Upper and lower data and address registers, used by macw and msacw. */
3430 { "d0l", DATA0L },
3431 { "d1l", DATA1L },
3432 { "d2l", DATA2L },
3433 { "d3l", DATA3L },
3434 { "d4l", DATA4L },
3435 { "d5l", DATA5L },
3436 { "d6l", DATA6L },
3437 { "d7l", DATA7L },
3438
3439 { "a0l", ADDR0L },
3440 { "a1l", ADDR1L },
3441 { "a2l", ADDR2L },
3442 { "a3l", ADDR3L },
3443 { "a4l", ADDR4L },
3444 { "a5l", ADDR5L },
3445 { "a6l", ADDR6L },
3446 { "a7l", ADDR7L },
3447
3448 { "d0u", DATA0U },
3449 { "d1u", DATA1U },
3450 { "d2u", DATA2U },
3451 { "d3u", DATA3U },
3452 { "d4u", DATA4U },
3453 { "d5u", DATA5U },
3454 { "d6u", DATA6U },
3455 { "d7u", DATA7U },
3456
3457 { "a0u", ADDR0U },
3458 { "a1u", ADDR1U },
3459 { "a2u", ADDR2U },
3460 { "a3u", ADDR3U },
3461 { "a4u", ADDR4U },
3462 { "a5u", ADDR5U },
3463 { "a6u", ADDR6U },
3464 { "a7u", ADDR7U },
3465
3466 { 0, 0 }
3467 };
3468
3469 static void
3470 init_regtable ()
3471 {
3472 int i;
3473 for (i = 0; init_table[i].name; i++)
3474 insert_reg (init_table[i].name, init_table[i].number);
3475 }
3476
3477 static int no_68851, no_68881;
3478
3479 #ifdef OBJ_AOUT
3480 /* a.out machine type. Default to 68020. */
3481 int m68k_aout_machtype = 2;
3482 #endif
3483
3484 void
3485 md_assemble (str)
3486 char *str;
3487 {
3488 const char *er;
3489 short *fromP;
3490 char *toP = NULL;
3491 int m, n = 0;
3492 char *to_beg_P;
3493 int shorts_this_frag;
3494 fixS *fixP;
3495
3496 /* In MRI mode, the instruction and operands are separated by a
3497 space. Anything following the operands is a comment. The label
3498 has already been removed. */
3499 if (flag_mri)
3500 {
3501 char *s;
3502 int fields = 0;
3503 int infield = 0;
3504 int inquote = 0;
3505
3506 for (s = str; *s != '\0'; s++)
3507 {
3508 if ((*s == ' ' || *s == '\t') && ! inquote)
3509 {
3510 if (infield)
3511 {
3512 ++fields;
3513 if (fields >= 2)
3514 {
3515 *s = '\0';
3516 break;
3517 }
3518 infield = 0;
3519 }
3520 }
3521 else
3522 {
3523 if (! infield)
3524 infield = 1;
3525 if (*s == '\'')
3526 inquote = ! inquote;
3527 }
3528 }
3529 }
3530
3531 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3532 m68k_ip (str);
3533 er = the_ins.error;
3534 if (!er)
3535 {
3536 for (n = 0; n < the_ins.numargs; n++)
3537 if (the_ins.operands[n].error)
3538 {
3539 er = the_ins.operands[n].error;
3540 break;
3541 }
3542 }
3543 if (er)
3544 {
3545 as_bad (_("%s -- statement `%s' ignored"), er, str);
3546 return;
3547 }
3548
3549 /* If there is a current label, record that it marks an instruction. */
3550 if (current_label != NULL)
3551 {
3552 current_label->text = 1;
3553 current_label = NULL;
3554 }
3555
3556 if (the_ins.nfrag == 0)
3557 {
3558 /* No frag hacking involved; just put it out */
3559 toP = frag_more (2 * the_ins.numo);
3560 fromP = &the_ins.opcode[0];
3561 for (m = the_ins.numo; m; --m)
3562 {
3563 md_number_to_chars (toP, (long) (*fromP), 2);
3564 toP += 2;
3565 fromP++;
3566 }
3567 /* put out symbol-dependent info */
3568 for (m = 0; m < the_ins.nrel; m++)
3569 {
3570 switch (the_ins.reloc[m].wid)
3571 {
3572 case 'B':
3573 n = 1;
3574 break;
3575 case 'b':
3576 n = 1;
3577 break;
3578 case '3':
3579 n = 1;
3580 break;
3581 case 'w':
3582 case 'W':
3583 n = 2;
3584 break;
3585 case 'l':
3586 n = 4;
3587 break;
3588 default:
3589 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3590 the_ins.reloc[m].wid);
3591 }
3592
3593 fixP = fix_new_exp (frag_now,
3594 ((toP - frag_now->fr_literal)
3595 - the_ins.numo * 2 + the_ins.reloc[m].n),
3596 n,
3597 &the_ins.reloc[m].exp,
3598 the_ins.reloc[m].pcrel,
3599 get_reloc_code (n, the_ins.reloc[m].pcrel,
3600 the_ins.reloc[m].pic_reloc));
3601 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3602 if (the_ins.reloc[m].wid == 'B')
3603 fixP->fx_signed = 1;
3604 }
3605 return;
3606 }
3607
3608 /* There's some frag hacking */
3609 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3610 {
3611 int wid;
3612
3613 if (n == 0)
3614 wid = 2 * the_ins.fragb[n].fragoff;
3615 else
3616 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3617 toP = frag_more (wid);
3618 to_beg_P = toP;
3619 shorts_this_frag = 0;
3620 for (m = wid / 2; m; --m)
3621 {
3622 md_number_to_chars (toP, (long) (*fromP), 2);
3623 toP += 2;
3624 fromP++;
3625 shorts_this_frag++;
3626 }
3627 for (m = 0; m < the_ins.nrel; m++)
3628 {
3629 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3630 {
3631 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3632 break;
3633 }
3634 wid = the_ins.reloc[m].wid;
3635 if (wid == 0)
3636 continue;
3637 the_ins.reloc[m].wid = 0;
3638 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3639
3640 fixP = fix_new_exp (frag_now,
3641 ((toP - frag_now->fr_literal)
3642 - the_ins.numo * 2 + the_ins.reloc[m].n),
3643 wid,
3644 &the_ins.reloc[m].exp,
3645 the_ins.reloc[m].pcrel,
3646 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3647 the_ins.reloc[m].pic_reloc));
3648 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3649 }
3650 (void) frag_var (rs_machine_dependent, 10, 0,
3651 (relax_substateT) (the_ins.fragb[n].fragty),
3652 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3653 }
3654 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3655 shorts_this_frag = 0;
3656 if (n)
3657 {
3658 toP = frag_more (n * sizeof (short));
3659 while (n--)
3660 {
3661 md_number_to_chars (toP, (long) (*fromP), 2);
3662 toP += 2;
3663 fromP++;
3664 shorts_this_frag++;
3665 }
3666 }
3667 for (m = 0; m < the_ins.nrel; m++)
3668 {
3669 int wid;
3670
3671 wid = the_ins.reloc[m].wid;
3672 if (wid == 0)
3673 continue;
3674 the_ins.reloc[m].wid = 0;
3675 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3676
3677 fixP = fix_new_exp (frag_now,
3678 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3679 - shorts_this_frag * 2),
3680 wid,
3681 &the_ins.reloc[m].exp,
3682 the_ins.reloc[m].pcrel,
3683 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3684 the_ins.reloc[m].pic_reloc));
3685 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3686 }
3687 }
3688
3689 void
3690 md_begin ()
3691 {
3692 /*
3693 * md_begin -- set up hash tables with 68000 instructions.
3694 * similar to what the vax assembler does. ---phr
3695 */
3696 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3697 a copy of it at runtime, adding in the information we want but isn't
3698 there. I think it'd be better to have an awk script hack the table
3699 at compile time. Or even just xstr the table and use it as-is. But
3700 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3701 names. */
3702
3703 register const struct m68k_opcode *ins;
3704 register struct m68k_incant *hack, *slak;
3705 register const char *retval = 0; /* empty string, or error msg text */
3706 register int i;
3707 register char c;
3708
3709 if (flag_mri)
3710 {
3711 flag_reg_prefix_optional = 1;
3712 m68k_abspcadd = 1;
3713 if (! m68k_rel32_from_cmdline)
3714 m68k_rel32 = 0;
3715 }
3716
3717 op_hash = hash_new ();
3718
3719 obstack_begin (&robyn, 4000);
3720 for (i = 0; i < m68k_numopcodes; i++)
3721 {
3722 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3723 do
3724 {
3725 ins = &m68k_opcodes[i];
3726 /* We *could* ignore insns that don't match our arch here
3727 but just leaving them out of the hash. */
3728 slak->m_operands = ins->args;
3729 slak->m_opnum = strlen (slak->m_operands) / 2;
3730 slak->m_arch = ins->arch;
3731 slak->m_opcode = ins->opcode;
3732 /* This is kludgey */
3733 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3734 if (i + 1 != m68k_numopcodes
3735 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3736 {
3737 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3738 i++;
3739 }
3740 else
3741 slak->m_next = 0;
3742 slak = slak->m_next;
3743 }
3744 while (slak);
3745
3746 retval = hash_insert (op_hash, ins->name, (char *) hack);
3747 if (retval)
3748 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3749 }
3750
3751 for (i = 0; i < m68k_numaliases; i++)
3752 {
3753 const char *name = m68k_opcode_aliases[i].primary;
3754 const char *alias = m68k_opcode_aliases[i].alias;
3755 PTR val = hash_find (op_hash, name);
3756 if (!val)
3757 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3758 retval = hash_insert (op_hash, alias, val);
3759 if (retval)
3760 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3761 }
3762
3763 /* In MRI mode, all unsized branches are variable sized. Normally,
3764 they are word sized. */
3765 if (flag_mri)
3766 {
3767 static struct m68k_opcode_alias mri_aliases[] =
3768 {
3769 { "bhi", "jhi", },
3770 { "bls", "jls", },
3771 { "bcc", "jcc", },
3772 { "bcs", "jcs", },
3773 { "bne", "jne", },
3774 { "beq", "jeq", },
3775 { "bvc", "jvc", },
3776 { "bvs", "jvs", },
3777 { "bpl", "jpl", },
3778 { "bmi", "jmi", },
3779 { "bge", "jge", },
3780 { "blt", "jlt", },
3781 { "bgt", "jgt", },
3782 { "ble", "jle", },
3783 { "bra", "jra", },
3784 { "bsr", "jbsr", },
3785 };
3786
3787 for (i = 0;
3788 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3789 i++)
3790 {
3791 const char *name = mri_aliases[i].primary;
3792 const char *alias = mri_aliases[i].alias;
3793 PTR val = hash_find (op_hash, name);
3794 if (!val)
3795 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3796 retval = hash_jam (op_hash, alias, val);
3797 if (retval)
3798 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3799 }
3800 }
3801
3802 for (i = 0; i < (int) sizeof (mklower_table); i++)
3803 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3804
3805 for (i = 0; i < (int) sizeof (notend_table); i++)
3806 {
3807 notend_table[i] = 0;
3808 alt_notend_table[i] = 0;
3809 }
3810 notend_table[','] = 1;
3811 notend_table['{'] = 1;
3812 notend_table['}'] = 1;
3813 alt_notend_table['a'] = 1;
3814 alt_notend_table['A'] = 1;
3815 alt_notend_table['d'] = 1;
3816 alt_notend_table['D'] = 1;
3817 alt_notend_table['#'] = 1;
3818 alt_notend_table['&'] = 1;
3819 alt_notend_table['f'] = 1;
3820 alt_notend_table['F'] = 1;
3821 #ifdef REGISTER_PREFIX
3822 alt_notend_table[REGISTER_PREFIX] = 1;
3823 #endif
3824
3825 /* We need to put '(' in alt_notend_table to handle
3826 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3827 */
3828 alt_notend_table['('] = 1;
3829
3830 /* We need to put '@' in alt_notend_table to handle
3831 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3832 */
3833 alt_notend_table['@'] = 1;
3834
3835 /* We need to put digits in alt_notend_table to handle
3836 bfextu %d0{24:1},%d0
3837 */
3838 alt_notend_table['0'] = 1;
3839 alt_notend_table['1'] = 1;
3840 alt_notend_table['2'] = 1;
3841 alt_notend_table['3'] = 1;
3842 alt_notend_table['4'] = 1;
3843 alt_notend_table['5'] = 1;
3844 alt_notend_table['6'] = 1;
3845 alt_notend_table['7'] = 1;
3846 alt_notend_table['8'] = 1;
3847 alt_notend_table['9'] = 1;
3848
3849 #ifndef MIT_SYNTAX_ONLY
3850 /* Insert pseudo ops, these have to go into the opcode table since
3851 gas expects pseudo ops to start with a dot */
3852 {
3853 int n = 0;
3854 while (mote_pseudo_table[n].poc_name)
3855 {
3856 hack = (struct m68k_incant *)
3857 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3858 hash_insert (op_hash,
3859 mote_pseudo_table[n].poc_name, (char *) hack);
3860 hack->m_operands = 0;
3861 hack->m_opnum = n;
3862 n++;
3863 }
3864 }
3865 #endif
3866
3867 init_regtable ();
3868
3869 #ifdef OBJ_ELF
3870 record_alignment (text_section, 2);
3871 record_alignment (data_section, 2);
3872 record_alignment (bss_section, 2);
3873 #endif
3874 }
3875
3876 static void
3877 select_control_regs ()
3878 {
3879 /* Note which set of "movec" control registers is available. */
3880 switch (cpu_of_arch (current_architecture))
3881 {
3882 case m68000:
3883 control_regs = m68000_control_regs;
3884 break;
3885 case m68010:
3886 control_regs = m68010_control_regs;
3887 break;
3888 case m68020:
3889 case m68030:
3890 control_regs = m68020_control_regs;
3891 break;
3892 case m68040:
3893 control_regs = m68040_control_regs;
3894 break;
3895 case m68060:
3896 control_regs = m68060_control_regs;
3897 break;
3898 case cpu32:
3899 control_regs = cpu32_control_regs;
3900 break;
3901 case mcf5200:
3902 case mcf5206e:
3903 case mcf5307:
3904 control_regs = mcf_control_regs;
3905 break;
3906 default:
3907 abort ();
3908 }
3909 }
3910
3911 void
3912 m68k_init_after_args ()
3913 {
3914 if (cpu_of_arch (current_architecture) == 0)
3915 {
3916 int i;
3917 const char *default_cpu = TARGET_CPU;
3918
3919 if (*default_cpu == 'm')
3920 default_cpu++;
3921 for (i = 0; i < n_archs; i++)
3922 if (strcasecmp (default_cpu, archs[i].name) == 0)
3923 break;
3924 if (i == n_archs)
3925 {
3926 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3927 current_architecture |= m68020;
3928 }
3929 else
3930 current_architecture |= archs[i].arch;
3931 }
3932 /* Permit m68881 specification with all cpus; those that can't work
3933 with a coprocessor could be doing emulation. */
3934 if (current_architecture & m68851)
3935 {
3936 if (current_architecture & m68040)
3937 {
3938 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
3939 }
3940 }
3941 /* What other incompatibilities could we check for? */
3942
3943 /* Toss in some default assumptions about coprocessors. */
3944 if (!no_68881
3945 && (cpu_of_arch (current_architecture)
3946 /* Can CPU32 have a 68881 coprocessor?? */
3947 & (m68020 | m68030 | cpu32)))
3948 {
3949 current_architecture |= m68881;
3950 }
3951 if (!no_68851
3952 && (cpu_of_arch (current_architecture) & m68020up) != 0
3953 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3954 {
3955 current_architecture |= m68851;
3956 }
3957 if (no_68881 && (current_architecture & m68881))
3958 as_bad (_("options for 68881 and no-68881 both given"));
3959 if (no_68851 && (current_architecture & m68851))
3960 as_bad (_("options for 68851 and no-68851 both given"));
3961
3962 #ifdef OBJ_AOUT
3963 /* Work out the magic number. This isn't very general. */
3964 if (current_architecture & m68000)
3965 m68k_aout_machtype = 0;
3966 else if (current_architecture & m68010)
3967 m68k_aout_machtype = 1;
3968 else if (current_architecture & m68020)
3969 m68k_aout_machtype = 2;
3970 else
3971 m68k_aout_machtype = 2;
3972 #endif
3973
3974 /* Note which set of "movec" control registers is available. */
3975 select_control_regs ();
3976
3977 if (cpu_of_arch (current_architecture) < m68020
3978 || arch_coldfire_p (current_architecture))
3979 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3980 }
3981 \f
3982 /* This is called when a label is defined. */
3983
3984 void
3985 m68k_frob_label (sym)
3986 symbolS *sym;
3987 {
3988 struct label_line *n;
3989
3990 n = (struct label_line *) xmalloc (sizeof *n);
3991 n->next = labels;
3992 n->label = sym;
3993 as_where (&n->file, &n->line);
3994 n->text = 0;
3995 labels = n;
3996 current_label = n;
3997 }
3998
3999 /* This is called when a value that is not an instruction is emitted. */
4000
4001 void
4002 m68k_flush_pending_output ()
4003 {
4004 current_label = NULL;
4005 }
4006
4007 /* This is called at the end of the assembly, when the final value of
4008 the label is known. We warn if this is a text symbol aligned at an
4009 odd location. */
4010
4011 void
4012 m68k_frob_symbol (sym)
4013 symbolS *sym;
4014 {
4015 if (S_GET_SEGMENT (sym) == reg_section
4016 && (int) S_GET_VALUE (sym) < 0)
4017 {
4018 S_SET_SEGMENT (sym, absolute_section);
4019 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4020 }
4021 else if ((S_GET_VALUE (sym) & 1) != 0)
4022 {
4023 struct label_line *l;
4024
4025 for (l = labels; l != NULL; l = l->next)
4026 {
4027 if (l->label == sym)
4028 {
4029 if (l->text)
4030 as_warn_where (l->file, l->line,
4031 _("text label `%s' aligned to odd boundary"),
4032 S_GET_NAME (sym));
4033 break;
4034 }
4035 }
4036 }
4037 }
4038 \f
4039 /* This is called if we go in or out of MRI mode because of the .mri
4040 pseudo-op. */
4041
4042 void
4043 m68k_mri_mode_change (on)
4044 int on;
4045 {
4046 if (on)
4047 {
4048 if (! flag_reg_prefix_optional)
4049 {
4050 flag_reg_prefix_optional = 1;
4051 #ifdef REGISTER_PREFIX
4052 init_regtable ();
4053 #endif
4054 }
4055 m68k_abspcadd = 1;
4056 if (! m68k_rel32_from_cmdline)
4057 m68k_rel32 = 0;
4058 }
4059 else
4060 {
4061 if (! reg_prefix_optional_seen)
4062 {
4063 #ifdef REGISTER_PREFIX_OPTIONAL
4064 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4065 #else
4066 flag_reg_prefix_optional = 0;
4067 #endif
4068 #ifdef REGISTER_PREFIX
4069 init_regtable ();
4070 #endif
4071 }
4072 m68k_abspcadd = 0;
4073 if (! m68k_rel32_from_cmdline)
4074 m68k_rel32 = 1;
4075 }
4076 }
4077
4078 /* Equal to MAX_PRECISION in atof-ieee.c */
4079 #define MAX_LITTLENUMS 6
4080
4081 /* Turn a string in input_line_pointer into a floating point constant
4082 of type TYPE, and store the appropriate bytes in *LITP. The number
4083 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4084 returned, or NULL on OK. */
4085
4086 char *
4087 md_atof (type, litP, sizeP)
4088 char type;
4089 char *litP;
4090 int *sizeP;
4091 {
4092 int prec;
4093 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4094 LITTLENUM_TYPE *wordP;
4095 char *t;
4096
4097 switch (type)
4098 {
4099 case 'f':
4100 case 'F':
4101 case 's':
4102 case 'S':
4103 prec = 2;
4104 break;
4105
4106 case 'd':
4107 case 'D':
4108 case 'r':
4109 case 'R':
4110 prec = 4;
4111 break;
4112
4113 case 'x':
4114 case 'X':
4115 prec = 6;
4116 break;
4117
4118 case 'p':
4119 case 'P':
4120 prec = 6;
4121 break;
4122
4123 default:
4124 *sizeP = 0;
4125 return _("Bad call to MD_ATOF()");
4126 }
4127 t = atof_ieee (input_line_pointer, type, words);
4128 if (t)
4129 input_line_pointer = t;
4130
4131 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4132 for (wordP = words; prec--;)
4133 {
4134 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4135 litP += sizeof (LITTLENUM_TYPE);
4136 }
4137 return 0;
4138 }
4139
4140 void
4141 md_number_to_chars (buf, val, n)
4142 char *buf;
4143 valueT val;
4144 int n;
4145 {
4146 number_to_chars_bigendian (buf, val, n);
4147 }
4148
4149 static void
4150 md_apply_fix_2 (fixP, val)
4151 fixS *fixP;
4152 offsetT val;
4153 {
4154 addressT upper_limit;
4155 offsetT lower_limit;
4156
4157 /* This is unnecessary but it convinces the native rs6000 compiler
4158 to generate the code we want. */
4159 char *buf = fixP->fx_frag->fr_literal;
4160 buf += fixP->fx_where;
4161 /* end ibm compiler workaround */
4162
4163 if (val & 0x80000000)
4164 val |= ~(addressT)0x7fffffff;
4165 else
4166 val &= 0x7fffffff;
4167
4168 #ifdef OBJ_ELF
4169 if (fixP->fx_addsy)
4170 {
4171 memset (buf, 0, fixP->fx_size);
4172 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4173
4174 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4175 && !S_IS_DEFINED (fixP->fx_addsy)
4176 && !S_IS_WEAK (fixP->fx_addsy))
4177 S_SET_WEAK (fixP->fx_addsy);
4178 return;
4179 }
4180 #endif
4181
4182 #ifdef BFD_ASSEMBLER
4183 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4184 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4185 return;
4186 #endif
4187
4188 switch (fixP->fx_size)
4189 {
4190 /* The cast to offsetT below are necessary to make code correct for
4191 machines where ints are smaller than offsetT */
4192 case 1:
4193 *buf++ = val;
4194 upper_limit = 0x7f;
4195 lower_limit = - (offsetT) 0x80;
4196 break;
4197 case 2:
4198 *buf++ = (val >> 8);
4199 *buf++ = val;
4200 upper_limit = 0x7fff;
4201 lower_limit = - (offsetT) 0x8000;
4202 break;
4203 case 4:
4204 *buf++ = (val >> 24);
4205 *buf++ = (val >> 16);
4206 *buf++ = (val >> 8);
4207 *buf++ = val;
4208 upper_limit = 0x7fffffff;
4209 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4210 break;
4211 default:
4212 BAD_CASE (fixP->fx_size);
4213 }
4214
4215 /* Fix up a negative reloc. */
4216 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4217 {
4218 fixP->fx_addsy = fixP->fx_subsy;
4219 fixP->fx_subsy = NULL;
4220 fixP->fx_tcbit = 1;
4221 }
4222
4223 /* For non-pc-relative values, it's conceivable we might get something
4224 like "0xff" for a byte field. So extend the upper part of the range
4225 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4226 so that we can do any range checking at all. */
4227 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4228 upper_limit = upper_limit * 2 + 1;
4229
4230 if ((addressT) val > upper_limit
4231 && (val > 0 || val < lower_limit))
4232 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4233
4234 /* A one byte PC-relative reloc means a short branch. We can't use
4235 a short branch with a value of 0 or -1, because those indicate
4236 different opcodes (branches with longer offsets). fixup_segment
4237 in write.c may have clobbered fx_pcrel, so we need to examine the
4238 reloc type. */
4239 if ((fixP->fx_pcrel
4240 #ifdef BFD_ASSEMBLER
4241 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4242 #endif
4243 )
4244 && fixP->fx_size == 1
4245 && (fixP->fx_addsy == NULL
4246 || S_IS_DEFINED (fixP->fx_addsy))
4247 && (val == 0 || val == -1))
4248 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4249 }
4250
4251 #ifdef BFD_ASSEMBLER
4252 int
4253 md_apply_fix (fixP, valp)
4254 fixS *fixP;
4255 valueT *valp;
4256 {
4257 md_apply_fix_2 (fixP, (addressT) *valp);
4258 return 1;
4259 }
4260 #else
4261 void md_apply_fix (fixP, val)
4262 fixS *fixP;
4263 long val;
4264 {
4265 md_apply_fix_2 (fixP, (addressT) val);
4266 }
4267 #endif
4268
4269 /* *fragP has been relaxed to its final size, and now needs to have
4270 the bytes inside it modified to conform to the new size There is UGLY
4271 MAGIC here. ..
4272 */
4273 static void
4274 md_convert_frag_1 (fragP)
4275 register fragS *fragP;
4276 {
4277 long disp;
4278 long ext = 0;
4279 fixS *fixP;
4280
4281 /* Address in object code of the displacement. */
4282 register int object_address = fragP->fr_fix + fragP->fr_address;
4283
4284 /* Address in gas core of the place to store the displacement. */
4285 /* This convinces the native rs6000 compiler to generate the code we
4286 want. */
4287 register char *buffer_address = fragP->fr_literal;
4288 buffer_address += fragP->fr_fix;
4289 /* end ibm compiler workaround */
4290
4291 /* The displacement of the address, from current location. */
4292 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4293 disp = (disp + fragP->fr_offset) - object_address;
4294
4295 #ifdef BFD_ASSEMBLER
4296 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4297 #endif
4298
4299 switch (fragP->fr_subtype)
4300 {
4301 case TAB (BCC68000, BYTE):
4302 case TAB (ABRANCH, BYTE):
4303 know (issbyte (disp));
4304 if (disp == 0)
4305 as_bad (_("short branch with zero offset: use :w"));
4306 fragP->fr_opcode[1] = disp;
4307 ext = 0;
4308 break;
4309 case TAB (DBCC, SHORT):
4310 know (issword (disp));
4311 ext = 2;
4312 break;
4313 case TAB (BCC68000, SHORT):
4314 case TAB (ABRANCH, SHORT):
4315 know (issword (disp));
4316 fragP->fr_opcode[1] = 0x00;
4317 ext = 2;
4318 break;
4319 case TAB (ABRANCH, LONG):
4320 if (!HAVE_LONG_BRANCH (current_architecture))
4321 {
4322 if (flag_keep_pcrel)
4323 as_bad (_("long branch not supported"));
4324
4325 if (fragP->fr_opcode[0] == 0x61)
4326 /* BSR */
4327 {
4328 fragP->fr_opcode[0] = 0x4E;
4329 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4330
4331 fix_new (fragP,
4332 fragP->fr_fix,
4333 4,
4334 fragP->fr_symbol,
4335 fragP->fr_offset,
4336 0,
4337 NO_RELOC);
4338
4339 fragP->fr_fix += 4;
4340 ext = 0;
4341 }
4342 /* BRA */
4343 else if (fragP->fr_opcode[0] == 0x60)
4344 {
4345 fragP->fr_opcode[0] = 0x4E;
4346 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4347 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4348 fragP->fr_offset, 0, NO_RELOC);
4349 fragP->fr_fix += 4;
4350 ext = 0;
4351 }
4352 else
4353 {
4354 /* This should never happen, because if it's a conditional
4355 branch and we are on a 68000, BCC68000 should have been
4356 picked instead of ABRANCH. */
4357 abort ();
4358 }
4359 }
4360 else
4361 {
4362 fragP->fr_opcode[1] = (char) 0xff;
4363 ext = 4;
4364 }
4365 break;
4366 case TAB (BCC68000, LONG):
4367 /* only Bcc 68000 instructions can come here */
4368 /* change bcc into b!cc/jmp absl long */
4369 if (flag_keep_pcrel)
4370 as_bad (_("long branch not supported"));
4371
4372 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4373 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4374
4375 /* JF: these used to be fr_opcode[2,3], but they may be in a
4376 different frag, in which case refering to them is a no-no.
4377 Only fr_opcode[0,1] are guaranteed to work. */
4378 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4379 *buffer_address++ = (char) 0xf9;
4380 fragP->fr_fix += 2; /* account for jmp instruction */
4381 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4382 fragP->fr_offset, 0, NO_RELOC);
4383 fragP->fr_fix += 4;
4384 ext = 0;
4385 break;
4386 case TAB (DBCC, LONG):
4387 /* only DBcc 68000 instructions can come here */
4388 /* Change dbcc into dbcc/bral. */
4389 if (! HAVE_LONG_BRANCH (current_architecture) && flag_keep_pcrel)
4390 as_bad (_("long branch not supported"));
4391
4392 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4393 *buffer_address++ = 0x00; /* branch offset = 4 */
4394 *buffer_address++ = 0x04;
4395 *buffer_address++ = 0x60; /* put in bra pc+6 */
4396 *buffer_address++ = 0x06;
4397 if (HAVE_LONG_BRANCH (current_architecture))
4398 {
4399 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4400 *buffer_address++ = (char) 0xff;
4401 }
4402 else
4403 {
4404 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4405 *buffer_address++ = (char) 0xf9;
4406 }
4407
4408 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4409 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4410 fragP->fr_offset, HAVE_LONG_BRANCH (current_architecture),
4411 NO_RELOC);
4412 fragP->fr_fix += 4;
4413 ext = 0;
4414 break;
4415 case TAB (FBRANCH, SHORT):
4416 know ((fragP->fr_opcode[1] & 0x40) == 0);
4417 ext = 2;
4418 break;
4419 case TAB (FBRANCH, LONG):
4420 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4421 ext = 4;
4422 break;
4423 case TAB (PCREL, SHORT):
4424 ext = 2;
4425 break;
4426 case TAB (PCREL, LONG):
4427 /* The thing to do here is force it to ABSOLUTE LONG, since
4428 PCREL is really trying to shorten an ABSOLUTE address anyway */
4429 /* JF FOO This code has not been tested */
4430 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4431 0, NO_RELOC);
4432 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4433 as_bad (_("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx"),
4434 (unsigned) fragP->fr_opcode[0],
4435 (unsigned long) fragP->fr_address);
4436 fragP->fr_opcode[1] &= ~0x3F;
4437 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4438 fragP->fr_fix += 4;
4439 ext = 0;
4440 break;
4441 case TAB (PCLEA, SHORT):
4442 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4443 fragP->fr_offset, 1, NO_RELOC);
4444 fragP->fr_opcode[1] &= ~0x3F;
4445 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4446 ext = 2;
4447 break;
4448 case TAB (PCLEA, LONG):
4449 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4450 fragP->fr_offset, 1, NO_RELOC);
4451 fixP->fx_pcrel_adjust = 2;
4452 /* Already set to mode 7.3; this indicates: PC indirect with
4453 suppressed index, 32-bit displacement. */
4454 *buffer_address++ = 0x01;
4455 *buffer_address++ = 0x70;
4456 fragP->fr_fix += 2;
4457 ext = 4;
4458 break;
4459
4460 case TAB (PCINDEX, BYTE):
4461 disp += 2;
4462 if (!issbyte (disp))
4463 {
4464 as_bad (_("displacement doesn't fit in one byte"));
4465 disp = 0;
4466 }
4467 assert (fragP->fr_fix >= 2);
4468 buffer_address[-2] &= ~1;
4469 buffer_address[-1] = disp;
4470 ext = 0;
4471 break;
4472 case TAB (PCINDEX, SHORT):
4473 disp += 2;
4474 assert (issword (disp));
4475 assert (fragP->fr_fix >= 2);
4476 buffer_address[-2] |= 0x1;
4477 buffer_address[-1] = 0x20;
4478 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4479 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4480 NO_RELOC);
4481 fixP->fx_pcrel_adjust = 2;
4482 ext = 2;
4483 break;
4484 case TAB (PCINDEX, LONG):
4485 disp += 2;
4486 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4487 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4488 NO_RELOC);
4489 fixP->fx_pcrel_adjust = 2;
4490 assert (fragP->fr_fix >= 2);
4491 buffer_address[-2] |= 0x1;
4492 buffer_address[-1] = 0x30;
4493 ext = 4;
4494 break;
4495 }
4496
4497 if (ext)
4498 {
4499 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4500 fragP->fr_fix += ext;
4501 }
4502 }
4503
4504 #ifndef BFD_ASSEMBLER
4505
4506 void
4507 md_convert_frag (headers, sec, fragP)
4508 object_headers *headers ATTRIBUTE_UNUSED;
4509 segT sec ATTRIBUTE_UNUSED;
4510 fragS *fragP;
4511 {
4512 md_convert_frag_1 (fragP);
4513 }
4514
4515 #else
4516
4517 void
4518 md_convert_frag (abfd, sec, fragP)
4519 bfd *abfd ATTRIBUTE_UNUSED;
4520 segT sec ATTRIBUTE_UNUSED;
4521 fragS *fragP;
4522 {
4523 md_convert_frag_1 (fragP);
4524 }
4525 #endif
4526
4527 /* Force truly undefined symbols to their maximum size, and generally set up
4528 the frag list to be relaxed
4529 */
4530 int
4531 md_estimate_size_before_relax (fragP, segment)
4532 register fragS *fragP;
4533 segT segment;
4534 {
4535 int old_fix;
4536 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4537
4538 old_fix = fragP->fr_fix;
4539
4540 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4541 switch (fragP->fr_subtype)
4542 {
4543
4544 case TAB (ABRANCH, SZ_UNDEF):
4545 {
4546 if ((fragP->fr_symbol != NULL) /* Not absolute */
4547 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4548 && relaxable_symbol (fragP->fr_symbol))
4549 {
4550 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4551 break;
4552 }
4553 else if ((fragP->fr_symbol != NULL)
4554 && (flag_short_refs || flag_keep_pcrel))
4555 { /* Symbol is undefined and we want short ref */
4556 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4557 fragP->fr_offset, 1, NO_RELOC);
4558 fragP->fr_fix += 2;
4559 frag_wane (fragP);
4560 break;
4561 }
4562 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4563 {
4564 /* On 68000, or for absolute value, switch to abs long */
4565 /* FIXME, we should check abs val, pick short or long */
4566 if (fragP->fr_opcode[0] == 0x61)
4567 {
4568 fragP->fr_opcode[0] = 0x4E;
4569 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4570 fix_new (fragP, fragP->fr_fix, 4,
4571 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4572 fragP->fr_fix += 4;
4573 frag_wane (fragP);
4574 }
4575 else if (fragP->fr_opcode[0] == 0x60)
4576 {
4577 fragP->fr_opcode[0] = 0x4E;
4578 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4579 fix_new (fragP, fragP->fr_fix, 4,
4580 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4581 fragP->fr_fix += 4;
4582 frag_wane (fragP);
4583 }
4584 else
4585 {
4586 /* This should never happen, because if it's a conditional
4587 branch and we are on a 68000, BCC68000 should have been
4588 picked instead of ABRANCH. */
4589 abort ();
4590 }
4591 }
4592 else
4593 { /* Symbol is still undefined. Make it simple */
4594 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4595 fragP->fr_offset, 1, NO_RELOC);
4596 fragP->fr_fix += 4;
4597 fragP->fr_opcode[1] = (char) 0xff;
4598 frag_wane (fragP);
4599 break;
4600 }
4601
4602 break;
4603 } /* case TAB(ABRANCH,SZ_UNDEF) */
4604
4605 case TAB (FBRANCH, SZ_UNDEF):
4606 {
4607 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4608 && relaxable_symbol (fragP->fr_symbol))
4609 || flag_short_refs)
4610 {
4611 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4612 fragP->fr_var += 2;
4613 }
4614 else
4615 {
4616 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4617 fragP->fr_offset, 1, NO_RELOC);
4618 fragP->fr_fix += 4;
4619 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4620 frag_wane (fragP);
4621 }
4622 break;
4623 } /* TAB(FBRANCH,SZ_UNDEF) */
4624
4625 case TAB (PCREL, SZ_UNDEF):
4626 {
4627 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4628 && relaxable_symbol (fragP->fr_symbol))
4629 || flag_short_refs)
4630 {
4631 fragP->fr_subtype = TAB (PCREL, SHORT);
4632 fragP->fr_var += 2;
4633 }
4634 else
4635 {
4636 fragP->fr_subtype = TAB (PCREL, LONG);
4637 fragP->fr_var += 4;
4638 }
4639 break;
4640 } /* TAB(PCREL,SZ_UNDEF) */
4641
4642 case TAB (BCC68000, SZ_UNDEF):
4643 {
4644 if ((fragP->fr_symbol != NULL)
4645 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4646 && relaxable_symbol (fragP->fr_symbol))
4647 {
4648 fragP->fr_subtype = TAB (BCC68000, BYTE);
4649 break;
4650 }
4651 /* only Bcc 68000 instructions can come here */
4652 if ((fragP->fr_symbol != NULL) && (flag_short_refs || flag_keep_pcrel))
4653 {
4654 /* the user wants short refs, so emit one */
4655 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4656 fragP->fr_offset, 1, NO_RELOC);
4657 fragP->fr_fix += 2;
4658 }
4659 else
4660 {
4661 /* change bcc into b!cc/jmp absl long */
4662 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4663 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4664 /* JF: these were fr_opcode[2,3] */
4665 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4666 buffer_address[1] = (char) 0xf9;
4667 fragP->fr_fix += 2; /* account for jmp instruction */
4668 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4669 fragP->fr_offset, 0, NO_RELOC);
4670 fragP->fr_fix += 4;
4671 }
4672 frag_wane (fragP);
4673 break;
4674 } /* case TAB(BCC68000,SZ_UNDEF) */
4675
4676 case TAB (DBCC, SZ_UNDEF):
4677 {
4678 if (fragP->fr_symbol != NULL
4679 && S_GET_SEGMENT (fragP->fr_symbol) == segment
4680 && relaxable_symbol (fragP->fr_symbol))
4681 {
4682 fragP->fr_subtype = TAB (DBCC, SHORT);
4683 fragP->fr_var += 2;
4684 break;
4685 }
4686 /* only DBcc 68000 instructions can come here */
4687
4688 if (fragP->fr_symbol != NULL
4689 && (flag_short_refs
4690 || (! HAVE_LONG_BRANCH (current_architecture)
4691 && flag_keep_pcrel)))
4692 {
4693 /* the user wants short refs, so emit one */
4694 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4695 fragP->fr_offset, 1, NO_RELOC);
4696 fragP->fr_fix += 2;
4697 }
4698 else
4699 {
4700 /* Change dbcc into dbcc/bral. */
4701 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4702 buffer_address[0] = 0x00; /* branch offset = 4 */
4703 buffer_address[1] = 0x04;
4704 buffer_address[2] = 0x60; /* put in bra pc + ... */
4705 /* JF: these were fr_opcode[5-7] */
4706 buffer_address[3] = 0x06; /* Plus 6 */
4707 if (HAVE_LONG_BRANCH (current_architecture))
4708 {
4709 buffer_address[4] = 0x60; /* Put in bral (0x60ff). */
4710 buffer_address[5] = (char) 0xff;
4711 }
4712 else
4713 {
4714 buffer_address[4] = 0x4e; /* Put in jmp long (0x4ef9). */
4715 buffer_address[5] = (char) 0xf9;
4716 }
4717 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4718 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4719 fragP->fr_offset, HAVE_LONG_BRANCH (current_architecture),
4720 NO_RELOC);
4721 fragP->fr_fix += 4;
4722 }
4723
4724 frag_wane (fragP);
4725 break;
4726 } /* case TAB(DBCC,SZ_UNDEF) */
4727
4728 case TAB (PCLEA, SZ_UNDEF):
4729 {
4730 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4731 && relaxable_symbol (fragP->fr_symbol))
4732 || flag_short_refs
4733 || cpu_of_arch (current_architecture) < m68020
4734 || cpu_of_arch (current_architecture) == mcf5200)
4735 {
4736 fragP->fr_subtype = TAB (PCLEA, SHORT);
4737 fragP->fr_var += 2;
4738 }
4739 else
4740 {
4741 fragP->fr_subtype = TAB (PCLEA, LONG);
4742 fragP->fr_var += 6;
4743 }
4744 break;
4745 } /* TAB(PCLEA,SZ_UNDEF) */
4746
4747 case TAB (PCINDEX, SZ_UNDEF):
4748 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4749 && relaxable_symbol (fragP->fr_symbol))
4750 || cpu_of_arch (current_architecture) < m68020
4751 || cpu_of_arch (current_architecture) == mcf5200)
4752 {
4753 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4754 }
4755 else
4756 {
4757 fragP->fr_subtype = TAB (PCINDEX, LONG);
4758 fragP->fr_var += 4;
4759 }
4760 break;
4761
4762 default:
4763 break;
4764 }
4765
4766 /* now that SZ_UNDEF are taken care of, check others */
4767 switch (fragP->fr_subtype)
4768 {
4769 case TAB (BCC68000, BYTE):
4770 case TAB (ABRANCH, BYTE):
4771 /* We can't do a short jump to the next instruction, so in that
4772 case we force word mode. At this point S_GET_VALUE should
4773 return the offset of the symbol within its frag. If the
4774 symbol is at the start of a frag, and it is the next frag
4775 with any data in it (usually this is just the next frag, but
4776 assembler listings may introduce empty frags), we must use
4777 word mode. */
4778 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4779 {
4780 fragS *stop;
4781 fragS *l;
4782
4783 stop = symbol_get_frag (fragP->fr_symbol);
4784 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4785 if (l->fr_fix + l->fr_var != 0)
4786 break;
4787 if (l == stop)
4788 {
4789 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4790 fragP->fr_var += 2;
4791 }
4792 }
4793 break;
4794 default:
4795 break;
4796 }
4797 return fragP->fr_var + fragP->fr_fix - old_fix;
4798 }
4799
4800 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4801 /* the bit-field entries in the relocation_info struct plays hell
4802 with the byte-order problems of cross-assembly. So as a hack,
4803 I added this mach. dependent ri twiddler. Ugly, but it gets
4804 you there. -KWK */
4805 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4806 are symbolnum, most sig. byte first. Last byte is broken up with
4807 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4808 nibble as nuthin. (on Sun 3 at least) */
4809 /* Translate the internal relocation information into target-specific
4810 format. */
4811 #ifdef comment
4812 void
4813 md_ri_to_chars (the_bytes, ri)
4814 char *the_bytes;
4815 struct reloc_info_generic *ri;
4816 {
4817 /* this is easy */
4818 md_number_to_chars (the_bytes, ri->r_address, 4);
4819 /* now the fun stuff */
4820 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4821 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4822 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4823 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4824 ((ri->r_extern << 4) & 0x10));
4825 }
4826
4827 #endif /* comment */
4828
4829 #ifndef BFD_ASSEMBLER
4830 void
4831 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4832 char *where;
4833 fixS *fixP;
4834 relax_addressT segment_address_in_file;
4835 {
4836 /*
4837 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4838 * Out: GNU LD relocation length code: 0, 1, or 2.
4839 */
4840
4841 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4842 long r_symbolnum;
4843
4844 know (fixP->fx_addsy != NULL);
4845
4846 md_number_to_chars (where,
4847 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4848 4);
4849
4850 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4851 ? S_GET_TYPE (fixP->fx_addsy)
4852 : fixP->fx_addsy->sy_number);
4853
4854 where[4] = (r_symbolnum >> 16) & 0x0ff;
4855 where[5] = (r_symbolnum >> 8) & 0x0ff;
4856 where[6] = r_symbolnum & 0x0ff;
4857 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4858 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4859 }
4860 #endif
4861
4862 #endif /* OBJ_AOUT or OBJ_BOUT */
4863
4864 #ifndef WORKING_DOT_WORD
4865 CONST int md_short_jump_size = 4;
4866 CONST int md_long_jump_size = 6;
4867
4868 void
4869 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4870 char *ptr;
4871 addressT from_addr, to_addr;
4872 fragS *frag ATTRIBUTE_UNUSED;
4873 symbolS *to_symbol ATTRIBUTE_UNUSED;
4874 {
4875 valueT offset;
4876
4877 offset = to_addr - (from_addr + 2);
4878
4879 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4880 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4881 }
4882
4883 void
4884 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4885 char *ptr;
4886 addressT from_addr, to_addr;
4887 fragS *frag;
4888 symbolS *to_symbol;
4889 {
4890 valueT offset;
4891
4892 if (!HAVE_LONG_BRANCH(current_architecture))
4893 {
4894 offset = to_addr - S_GET_VALUE (to_symbol);
4895 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4896 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4897 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4898 0, NO_RELOC);
4899 }
4900 else
4901 {
4902 offset = to_addr - (from_addr + 2);
4903 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4904 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4905 }
4906 }
4907
4908 #endif
4909
4910 /* Different values of OK tell what its OK to return. Things that
4911 aren't OK are an error (what a shock, no?)
4912
4913 0: Everything is OK
4914 10: Absolute 1:8 only
4915 20: Absolute 0:7 only
4916 30: absolute 0:15 only
4917 40: Absolute 0:31 only
4918 50: absolute 0:127 only
4919 55: absolute -64:63 only
4920 60: absolute -128:127 only
4921 70: absolute 0:4095 only
4922 80: No bignums
4923
4924 */
4925
4926 static int
4927 get_num (exp, ok)
4928 struct m68k_exp *exp;
4929 int ok;
4930 {
4931 if (exp->exp.X_op == O_absent)
4932 {
4933 /* Do the same thing the VAX asm does */
4934 op (exp) = O_constant;
4935 adds (exp) = 0;
4936 subs (exp) = 0;
4937 offs (exp) = 0;
4938 if (ok == 10)
4939 {
4940 as_warn (_("expression out of range: defaulting to 1"));
4941 offs (exp) = 1;
4942 }
4943 }
4944 else if (exp->exp.X_op == O_constant)
4945 {
4946 switch (ok)
4947 {
4948 case 10:
4949 if (offs (exp) < 1 || offs (exp) > 8)
4950 {
4951 as_warn (_("expression out of range: defaulting to 1"));
4952 offs (exp) = 1;
4953 }
4954 break;
4955 case 20:
4956 if (offs (exp) < 0 || offs (exp) > 7)
4957 goto outrange;
4958 break;
4959 case 30:
4960 if (offs (exp) < 0 || offs (exp) > 15)
4961 goto outrange;
4962 break;
4963 case 40:
4964 if (offs (exp) < 0 || offs (exp) > 32)
4965 goto outrange;
4966 break;
4967 case 50:
4968 if (offs (exp) < 0 || offs (exp) > 127)
4969 goto outrange;
4970 break;
4971 case 55:
4972 if (offs (exp) < -64 || offs (exp) > 63)
4973 goto outrange;
4974 break;
4975 case 60:
4976 if (offs (exp) < -128 || offs (exp) > 127)
4977 goto outrange;
4978 break;
4979 case 70:
4980 if (offs (exp) < 0 || offs (exp) > 4095)
4981 {
4982 outrange:
4983 as_warn (_("expression out of range: defaulting to 0"));
4984 offs (exp) = 0;
4985 }
4986 break;
4987 default:
4988 break;
4989 }
4990 }
4991 else if (exp->exp.X_op == O_big)
4992 {
4993 if (offs (exp) <= 0 /* flonum */
4994 && (ok == 80 /* no bignums */
4995 || (ok > 10 /* small-int ranges including 0 ok */
4996 /* If we have a flonum zero, a zero integer should
4997 do as well (e.g., in moveq). */
4998 && generic_floating_point_number.exponent == 0
4999 && generic_floating_point_number.low[0] == 0)))
5000 {
5001 /* HACK! Turn it into a long */
5002 LITTLENUM_TYPE words[6];
5003
5004 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5005 op (exp) = O_constant;
5006 adds (exp) = 0;
5007 subs (exp) = 0;
5008 offs (exp) = words[1] | (words[0] << 16);
5009 }
5010 else if (ok != 0)
5011 {
5012 op (exp) = O_constant;
5013 adds (exp) = 0;
5014 subs (exp) = 0;
5015 offs (exp) = (ok == 10) ? 1 : 0;
5016 as_warn (_("Can't deal with expression; defaulting to %ld"),
5017 offs (exp));
5018 }
5019 }
5020 else
5021 {
5022 if (ok >= 10 && ok <= 70)
5023 {
5024 op (exp) = O_constant;
5025 adds (exp) = 0;
5026 subs (exp) = 0;
5027 offs (exp) = (ok == 10) ? 1 : 0;
5028 as_warn (_("Can't deal with expression; defaulting to %ld"),
5029 offs (exp));
5030 }
5031 }
5032
5033 if (exp->size != SIZE_UNSPEC)
5034 {
5035 switch (exp->size)
5036 {
5037 case SIZE_UNSPEC:
5038 case SIZE_LONG:
5039 break;
5040 case SIZE_BYTE:
5041 if (!isbyte (offs (exp)))
5042 as_warn (_("expression doesn't fit in BYTE"));
5043 break;
5044 case SIZE_WORD:
5045 if (!isword (offs (exp)))
5046 as_warn (_("expression doesn't fit in WORD"));
5047 break;
5048 }
5049 }
5050
5051 return offs (exp);
5052 }
5053
5054 /* These are the back-ends for the various machine dependent pseudo-ops. */
5055
5056 static void
5057 s_data1 (ignore)
5058 int ignore ATTRIBUTE_UNUSED;
5059 {
5060 subseg_set (data_section, 1);
5061 demand_empty_rest_of_line ();
5062 }
5063
5064 static void
5065 s_data2 (ignore)
5066 int ignore ATTRIBUTE_UNUSED;
5067 {
5068 subseg_set (data_section, 2);
5069 demand_empty_rest_of_line ();
5070 }
5071
5072 static void
5073 s_bss (ignore)
5074 int ignore ATTRIBUTE_UNUSED;
5075 {
5076 /* We don't support putting frags in the BSS segment, we fake it
5077 by marking in_bss, then looking at s_skip for clues. */
5078
5079 subseg_set (bss_section, 0);
5080 demand_empty_rest_of_line ();
5081 }
5082
5083 static void
5084 s_even (ignore)
5085 int ignore ATTRIBUTE_UNUSED;
5086 {
5087 register int temp;
5088 register long temp_fill;
5089
5090 temp = 1; /* JF should be 2? */
5091 temp_fill = get_absolute_expression ();
5092 if (!need_pass_2) /* Never make frag if expect extra pass. */
5093 frag_align (temp, (int) temp_fill, 0);
5094 demand_empty_rest_of_line ();
5095 record_alignment (now_seg, temp);
5096 }
5097
5098 static void
5099 s_proc (ignore)
5100 int ignore ATTRIBUTE_UNUSED;
5101 {
5102 demand_empty_rest_of_line ();
5103 }
5104 \f
5105 /* Pseudo-ops handled for MRI compatibility. */
5106
5107 /* This function returns non-zero if the argument is a conditional
5108 pseudo-op. This is called when checking whether a pending
5109 alignment is needed. */
5110
5111 int
5112 m68k_conditional_pseudoop (pop)
5113 pseudo_typeS *pop;
5114 {
5115 return (pop->poc_handler == s_mri_if
5116 || pop->poc_handler == s_mri_else);
5117 }
5118
5119 /* Handle an MRI style chip specification. */
5120
5121 static void
5122 mri_chip ()
5123 {
5124 char *s;
5125 char c;
5126 int i;
5127
5128 s = input_line_pointer;
5129 /* We can't use get_symbol_end since the processor names are not proper
5130 symbols. */
5131 while (is_part_of_name (c = *input_line_pointer++))
5132 ;
5133 *--input_line_pointer = 0;
5134 for (i = 0; i < n_archs; i++)
5135 if (strcasecmp (s, archs[i].name) == 0)
5136 break;
5137 if (i >= n_archs)
5138 {
5139 as_bad (_("%s: unrecognized processor name"), s);
5140 *input_line_pointer = c;
5141 ignore_rest_of_line ();
5142 return;
5143 }
5144 *input_line_pointer = c;
5145
5146 if (*input_line_pointer == '/')
5147 current_architecture = 0;
5148 else
5149 current_architecture &= m68881 | m68851;
5150 current_architecture |= archs[i].arch;
5151
5152 while (*input_line_pointer == '/')
5153 {
5154 ++input_line_pointer;
5155 s = input_line_pointer;
5156 /* We can't use get_symbol_end since the processor names are not
5157 proper symbols. */
5158 while (is_part_of_name (c = *input_line_pointer++))
5159 ;
5160 *--input_line_pointer = 0;
5161 if (strcmp (s, "68881") == 0)
5162 current_architecture |= m68881;
5163 else if (strcmp (s, "68851") == 0)
5164 current_architecture |= m68851;
5165 *input_line_pointer = c;
5166 }
5167
5168 /* Update info about available control registers. */
5169 select_control_regs ();
5170 }
5171
5172 /* The MRI CHIP pseudo-op. */
5173
5174 static void
5175 s_chip (ignore)
5176 int ignore ATTRIBUTE_UNUSED;
5177 {
5178 char *stop = NULL;
5179 char stopc;
5180
5181 if (flag_mri)
5182 stop = mri_comment_field (&stopc);
5183 mri_chip ();
5184 if (flag_mri)
5185 mri_comment_end (stop, stopc);
5186 demand_empty_rest_of_line ();
5187 }
5188
5189 /* The MRI FOPT pseudo-op. */
5190
5191 static void
5192 s_fopt (ignore)
5193 int ignore ATTRIBUTE_UNUSED;
5194 {
5195 SKIP_WHITESPACE ();
5196
5197 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5198 {
5199 int temp;
5200
5201 input_line_pointer += 3;
5202 temp = get_absolute_expression ();
5203 if (temp < 0 || temp > 7)
5204 as_bad (_("bad coprocessor id"));
5205 else
5206 m68k_float_copnum = COP0 + temp;
5207 }
5208 else
5209 {
5210 as_bad (_("unrecognized fopt option"));
5211 ignore_rest_of_line ();
5212 return;
5213 }
5214
5215 demand_empty_rest_of_line ();
5216 }
5217
5218 /* The structure used to handle the MRI OPT pseudo-op. */
5219
5220 struct opt_action
5221 {
5222 /* The name of the option. */
5223 const char *name;
5224
5225 /* If this is not NULL, just call this function. The first argument
5226 is the ARG field of this structure, the second argument is
5227 whether the option was negated. */
5228 void (*pfn) PARAMS ((int arg, int on));
5229
5230 /* If this is not NULL, and the PFN field is NULL, set the variable
5231 this points to. Set it to the ARG field if the option was not
5232 negated, and the NOTARG field otherwise. */
5233 int *pvar;
5234
5235 /* The value to pass to PFN or to assign to *PVAR. */
5236 int arg;
5237
5238 /* The value to assign to *PVAR if the option is negated. If PFN is
5239 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5240 the option may not be negated. */
5241 int notarg;
5242 };
5243
5244 /* The table used to handle the MRI OPT pseudo-op. */
5245
5246 static void skip_to_comma PARAMS ((int, int));
5247 static void opt_nest PARAMS ((int, int));
5248 static void opt_chip PARAMS ((int, int));
5249 static void opt_list PARAMS ((int, int));
5250 static void opt_list_symbols PARAMS ((int, int));
5251
5252 static const struct opt_action opt_table[] =
5253 {
5254 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5255
5256 /* We do relaxing, so there is little use for these options. */
5257 { "b", 0, 0, 0, 0 },
5258 { "brs", 0, 0, 0, 0 },
5259 { "brb", 0, 0, 0, 0 },
5260 { "brl", 0, 0, 0, 0 },
5261 { "brw", 0, 0, 0, 0 },
5262
5263 { "c", 0, 0, 0, 0 },
5264 { "cex", 0, 0, 0, 0 },
5265 { "case", 0, &symbols_case_sensitive, 1, 0 },
5266 { "cl", 0, 0, 0, 0 },
5267 { "cre", 0, 0, 0, 0 },
5268 { "d", 0, &flag_keep_locals, 1, 0 },
5269 { "e", 0, 0, 0, 0 },
5270 { "f", 0, &flag_short_refs, 1, 0 },
5271 { "frs", 0, &flag_short_refs, 1, 0 },
5272 { "frl", 0, &flag_short_refs, 0, 1 },
5273 { "g", 0, 0, 0, 0 },
5274 { "i", 0, 0, 0, 0 },
5275 { "m", 0, 0, 0, 0 },
5276 { "mex", 0, 0, 0, 0 },
5277 { "mc", 0, 0, 0, 0 },
5278 { "md", 0, 0, 0, 0 },
5279 { "nest", opt_nest, 0, 0, 0 },
5280 { "next", skip_to_comma, 0, 0, 0 },
5281 { "o", 0, 0, 0, 0 },
5282 { "old", 0, 0, 0, 0 },
5283 { "op", skip_to_comma, 0, 0, 0 },
5284 { "pco", 0, 0, 0, 0 },
5285 { "p", opt_chip, 0, 0, 0 },
5286 { "pcr", 0, 0, 0, 0 },
5287 { "pcs", 0, 0, 0, 0 },
5288 { "r", 0, 0, 0, 0 },
5289 { "quick", 0, &m68k_quick, 1, 0 },
5290 { "rel32", 0, &m68k_rel32, 1, 0 },
5291 { "s", opt_list, 0, 0, 0 },
5292 { "t", opt_list_symbols, 0, 0, 0 },
5293 { "w", 0, &flag_no_warnings, 0, 1 },
5294 { "x", 0, 0, 0, 0 }
5295 };
5296
5297 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5298
5299 /* The MRI OPT pseudo-op. */
5300
5301 static void
5302 s_opt (ignore)
5303 int ignore ATTRIBUTE_UNUSED;
5304 {
5305 do
5306 {
5307 int t;
5308 char *s;
5309 char c;
5310 int i;
5311 const struct opt_action *o;
5312
5313 SKIP_WHITESPACE ();
5314
5315 t = 1;
5316 if (*input_line_pointer == '-')
5317 {
5318 ++input_line_pointer;
5319 t = 0;
5320 }
5321 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5322 {
5323 input_line_pointer += 2;
5324 t = 0;
5325 }
5326
5327 s = input_line_pointer;
5328 c = get_symbol_end ();
5329
5330 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5331 {
5332 if (strcasecmp (s, o->name) == 0)
5333 {
5334 if (o->pfn)
5335 {
5336 /* Restore input_line_pointer now in case the option
5337 takes arguments. */
5338 *input_line_pointer = c;
5339 (*o->pfn) (o->arg, t);
5340 }
5341 else if (o->pvar != NULL)
5342 {
5343 if (! t && o->arg == o->notarg)
5344 as_bad (_("option `%s' may not be negated"), s);
5345 *input_line_pointer = c;
5346 *o->pvar = t ? o->arg : o->notarg;
5347 }
5348 else
5349 *input_line_pointer = c;
5350 break;
5351 }
5352 }
5353 if (i >= OPTCOUNT)
5354 {
5355 as_bad (_("option `%s' not recognized"), s);
5356 *input_line_pointer = c;
5357 }
5358 }
5359 while (*input_line_pointer++ == ',');
5360
5361 /* Move back to terminating character. */
5362 --input_line_pointer;
5363 demand_empty_rest_of_line ();
5364 }
5365
5366 /* Skip ahead to a comma. This is used for OPT options which we do
5367 not suppor tand which take arguments. */
5368
5369 static void
5370 skip_to_comma (arg, on)
5371 int arg ATTRIBUTE_UNUSED;
5372 int on ATTRIBUTE_UNUSED;
5373 {
5374 while (*input_line_pointer != ','
5375 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5376 ++input_line_pointer;
5377 }
5378
5379 /* Handle the OPT NEST=depth option. */
5380
5381 static void
5382 opt_nest (arg, on)
5383 int arg ATTRIBUTE_UNUSED;
5384 int on ATTRIBUTE_UNUSED;
5385 {
5386 if (*input_line_pointer != '=')
5387 {
5388 as_bad (_("bad format of OPT NEST=depth"));
5389 return;
5390 }
5391
5392 ++input_line_pointer;
5393 max_macro_nest = get_absolute_expression ();
5394 }
5395
5396 /* Handle the OPT P=chip option. */
5397
5398 static void
5399 opt_chip (arg, on)
5400 int arg ATTRIBUTE_UNUSED;
5401 int on ATTRIBUTE_UNUSED;
5402 {
5403 if (*input_line_pointer != '=')
5404 {
5405 /* This is just OPT P, which we do not support. */
5406 return;
5407 }
5408
5409 ++input_line_pointer;
5410 mri_chip ();
5411 }
5412
5413 /* Handle the OPT S option. */
5414
5415 static void
5416 opt_list (arg, on)
5417 int arg ATTRIBUTE_UNUSED;
5418 int on;
5419 {
5420 listing_list (on);
5421 }
5422
5423 /* Handle the OPT T option. */
5424
5425 static void
5426 opt_list_symbols (arg, on)
5427 int arg ATTRIBUTE_UNUSED;
5428 int on;
5429 {
5430 if (on)
5431 listing |= LISTING_SYMBOLS;
5432 else
5433 listing &=~ LISTING_SYMBOLS;
5434 }
5435
5436 /* Handle the MRI REG pseudo-op. */
5437
5438 static void
5439 s_reg (ignore)
5440 int ignore ATTRIBUTE_UNUSED;
5441 {
5442 char *s;
5443 int c;
5444 struct m68k_op rop;
5445 int mask;
5446 char *stop = NULL;
5447 char stopc;
5448
5449 if (line_label == NULL)
5450 {
5451 as_bad (_("missing label"));
5452 ignore_rest_of_line ();
5453 return;
5454 }
5455
5456 if (flag_mri)
5457 stop = mri_comment_field (&stopc);
5458
5459 SKIP_WHITESPACE ();
5460
5461 s = input_line_pointer;
5462 while (isalnum ((unsigned char) *input_line_pointer)
5463 #ifdef REGISTER_PREFIX
5464 || *input_line_pointer == REGISTER_PREFIX
5465 #endif
5466 || *input_line_pointer == '/'
5467 || *input_line_pointer == '-')
5468 ++input_line_pointer;
5469 c = *input_line_pointer;
5470 *input_line_pointer = '\0';
5471
5472 if (m68k_ip_op (s, &rop) != 0)
5473 {
5474 if (rop.error == NULL)
5475 as_bad (_("bad register list"));
5476 else
5477 as_bad (_("bad register list: %s"), rop.error);
5478 *input_line_pointer = c;
5479 ignore_rest_of_line ();
5480 return;
5481 }
5482
5483 *input_line_pointer = c;
5484
5485 if (rop.mode == REGLST)
5486 mask = rop.mask;
5487 else if (rop.mode == DREG)
5488 mask = 1 << (rop.reg - DATA0);
5489 else if (rop.mode == AREG)
5490 mask = 1 << (rop.reg - ADDR0 + 8);
5491 else if (rop.mode == FPREG)
5492 mask = 1 << (rop.reg - FP0 + 16);
5493 else if (rop.mode == CONTROL
5494 && rop.reg == FPI)
5495 mask = 1 << 24;
5496 else if (rop.mode == CONTROL
5497 && rop.reg == FPS)
5498 mask = 1 << 25;
5499 else if (rop.mode == CONTROL
5500 && rop.reg == FPC)
5501 mask = 1 << 26;
5502 else
5503 {
5504 as_bad (_("bad register list"));
5505 ignore_rest_of_line ();
5506 return;
5507 }
5508
5509 S_SET_SEGMENT (line_label, reg_section);
5510 S_SET_VALUE (line_label, ~mask);
5511 symbol_set_frag (line_label, &zero_address_frag);
5512
5513 if (flag_mri)
5514 mri_comment_end (stop, stopc);
5515
5516 demand_empty_rest_of_line ();
5517 }
5518
5519 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5520
5521 struct save_opts
5522 {
5523 struct save_opts *next;
5524 int abspcadd;
5525 int symbols_case_sensitive;
5526 int keep_locals;
5527 int short_refs;
5528 int architecture;
5529 int quick;
5530 int rel32;
5531 int listing;
5532 int no_warnings;
5533 /* FIXME: We don't save OPT S. */
5534 };
5535
5536 /* This variable holds the stack of saved options. */
5537
5538 static struct save_opts *save_stack;
5539
5540 /* The MRI SAVE pseudo-op. */
5541
5542 static void
5543 s_save (ignore)
5544 int ignore ATTRIBUTE_UNUSED;
5545 {
5546 struct save_opts *s;
5547
5548 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5549 s->abspcadd = m68k_abspcadd;
5550 s->symbols_case_sensitive = symbols_case_sensitive;
5551 s->keep_locals = flag_keep_locals;
5552 s->short_refs = flag_short_refs;
5553 s->architecture = current_architecture;
5554 s->quick = m68k_quick;
5555 s->rel32 = m68k_rel32;
5556 s->listing = listing;
5557 s->no_warnings = flag_no_warnings;
5558
5559 s->next = save_stack;
5560 save_stack = s;
5561
5562 demand_empty_rest_of_line ();
5563 }
5564
5565 /* The MRI RESTORE pseudo-op. */
5566
5567 static void
5568 s_restore (ignore)
5569 int ignore ATTRIBUTE_UNUSED;
5570 {
5571 struct save_opts *s;
5572
5573 if (save_stack == NULL)
5574 {
5575 as_bad (_("restore without save"));
5576 ignore_rest_of_line ();
5577 return;
5578 }
5579
5580 s = save_stack;
5581 save_stack = s->next;
5582
5583 m68k_abspcadd = s->abspcadd;
5584 symbols_case_sensitive = s->symbols_case_sensitive;
5585 flag_keep_locals = s->keep_locals;
5586 flag_short_refs = s->short_refs;
5587 current_architecture = s->architecture;
5588 m68k_quick = s->quick;
5589 m68k_rel32 = s->rel32;
5590 listing = s->listing;
5591 flag_no_warnings = s->no_warnings;
5592
5593 free (s);
5594
5595 demand_empty_rest_of_line ();
5596 }
5597
5598 /* Types of MRI structured control directives. */
5599
5600 enum mri_control_type
5601 {
5602 mri_for,
5603 mri_if,
5604 mri_repeat,
5605 mri_while
5606 };
5607
5608 /* This structure is used to stack the MRI structured control
5609 directives. */
5610
5611 struct mri_control_info
5612 {
5613 /* The directive within which this one is enclosed. */
5614 struct mri_control_info *outer;
5615
5616 /* The type of directive. */
5617 enum mri_control_type type;
5618
5619 /* Whether an ELSE has been in an IF. */
5620 int else_seen;
5621
5622 /* The add or sub statement at the end of a FOR. */
5623 char *incr;
5624
5625 /* The label of the top of a FOR or REPEAT loop. */
5626 char *top;
5627
5628 /* The label to jump to for the next iteration, or the else
5629 expression of a conditional. */
5630 char *next;
5631
5632 /* The label to jump to to break out of the loop, or the label past
5633 the end of a conditional. */
5634 char *bottom;
5635 };
5636
5637 /* The stack of MRI structured control directives. */
5638
5639 static struct mri_control_info *mri_control_stack;
5640
5641 /* The current MRI structured control directive index number, used to
5642 generate label names. */
5643
5644 static int mri_control_index;
5645
5646 /* Some function prototypes. */
5647
5648 static void mri_assemble PARAMS ((char *));
5649 static char *mri_control_label PARAMS ((void));
5650 static struct mri_control_info *push_mri_control
5651 PARAMS ((enum mri_control_type));
5652 static void pop_mri_control PARAMS ((void));
5653 static int parse_mri_condition PARAMS ((int *));
5654 static int parse_mri_control_operand
5655 PARAMS ((int *, char **, char **, char **, char **));
5656 static int swap_mri_condition PARAMS ((int));
5657 static int reverse_mri_condition PARAMS ((int));
5658 static void build_mri_control_operand
5659 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5660 const char *, int));
5661 static void parse_mri_control_expression
5662 PARAMS ((char *, int, const char *, const char *, int));
5663
5664 /* Assemble an instruction for an MRI structured control directive. */
5665
5666 static void
5667 mri_assemble (str)
5668 char *str;
5669 {
5670 char *s;
5671
5672 /* md_assemble expects the opcode to be in lower case. */
5673 for (s = str; *s != ' ' && *s != '\0'; s++)
5674 {
5675 if (isupper ((unsigned char) *s))
5676 *s = tolower ((unsigned char) *s);
5677 }
5678
5679 md_assemble (str);
5680 }
5681
5682 /* Generate a new MRI label structured control directive label name. */
5683
5684 static char *
5685 mri_control_label ()
5686 {
5687 char *n;
5688
5689 n = (char *) xmalloc (20);
5690 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5691 ++mri_control_index;
5692 return n;
5693 }
5694
5695 /* Create a new MRI structured control directive. */
5696
5697 static struct mri_control_info *
5698 push_mri_control (type)
5699 enum mri_control_type type;
5700 {
5701 struct mri_control_info *n;
5702
5703 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5704
5705 n->type = type;
5706 n->else_seen = 0;
5707 if (type == mri_if || type == mri_while)
5708 n->top = NULL;
5709 else
5710 n->top = mri_control_label ();
5711 n->next = mri_control_label ();
5712 n->bottom = mri_control_label ();
5713
5714 n->outer = mri_control_stack;
5715 mri_control_stack = n;
5716
5717 return n;
5718 }
5719
5720 /* Pop off the stack of MRI structured control directives. */
5721
5722 static void
5723 pop_mri_control ()
5724 {
5725 struct mri_control_info *n;
5726
5727 n = mri_control_stack;
5728 mri_control_stack = n->outer;
5729 if (n->top != NULL)
5730 free (n->top);
5731 free (n->next);
5732 free (n->bottom);
5733 free (n);
5734 }
5735
5736 /* Recognize a condition code in an MRI structured control expression. */
5737
5738 static int
5739 parse_mri_condition (pcc)
5740 int *pcc;
5741 {
5742 char c1, c2;
5743
5744 know (*input_line_pointer == '<');
5745
5746 ++input_line_pointer;
5747 c1 = *input_line_pointer++;
5748 c2 = *input_line_pointer++;
5749
5750 if (*input_line_pointer != '>')
5751 {
5752 as_bad (_("syntax error in structured control directive"));
5753 return 0;
5754 }
5755
5756 ++input_line_pointer;
5757 SKIP_WHITESPACE ();
5758
5759 if (isupper (c1))
5760 c1 = tolower (c1);
5761 if (isupper (c2))
5762 c2 = tolower (c2);
5763
5764 *pcc = (c1 << 8) | c2;
5765
5766 return 1;
5767 }
5768
5769 /* Parse a single operand in an MRI structured control expression. */
5770
5771 static int
5772 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5773 int *pcc;
5774 char **leftstart;
5775 char **leftstop;
5776 char **rightstart;
5777 char **rightstop;
5778 {
5779 char *s;
5780
5781 SKIP_WHITESPACE ();
5782
5783 *pcc = -1;
5784 *leftstart = NULL;
5785 *leftstop = NULL;
5786 *rightstart = NULL;
5787 *rightstop = NULL;
5788
5789 if (*input_line_pointer == '<')
5790 {
5791 /* It's just a condition code. */
5792 return parse_mri_condition (pcc);
5793 }
5794
5795 /* Look ahead for the condition code. */
5796 for (s = input_line_pointer; *s != '\0'; ++s)
5797 {
5798 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5799 break;
5800 }
5801 if (*s == '\0')
5802 {
5803 as_bad (_("missing condition code in structured control directive"));
5804 return 0;
5805 }
5806
5807 *leftstart = input_line_pointer;
5808 *leftstop = s;
5809 if (*leftstop > *leftstart
5810 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5811 --*leftstop;
5812
5813 input_line_pointer = s;
5814 if (! parse_mri_condition (pcc))
5815 return 0;
5816
5817 /* Look ahead for AND or OR or end of line. */
5818 for (s = input_line_pointer; *s != '\0'; ++s)
5819 {
5820 if ((strncasecmp (s, "AND", 3) == 0
5821 && (s[3] == '.' || ! is_part_of_name (s[3])))
5822 || (strncasecmp (s, "OR", 2) == 0
5823 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5824 break;
5825 }
5826
5827 *rightstart = input_line_pointer;
5828 *rightstop = s;
5829 if (*rightstop > *rightstart
5830 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5831 --*rightstop;
5832
5833 input_line_pointer = s;
5834
5835 return 1;
5836 }
5837
5838 #define MCC(b1, b2) (((b1) << 8) | (b2))
5839
5840 /* Swap the sense of a condition. This changes the condition so that
5841 it generates the same result when the operands are swapped. */
5842
5843 static int
5844 swap_mri_condition (cc)
5845 int cc;
5846 {
5847 switch (cc)
5848 {
5849 case MCC ('h', 'i'): return MCC ('c', 's');
5850 case MCC ('l', 's'): return MCC ('c', 'c');
5851 case MCC ('c', 'c'): return MCC ('l', 's');
5852 case MCC ('c', 's'): return MCC ('h', 'i');
5853 case MCC ('p', 'l'): return MCC ('m', 'i');
5854 case MCC ('m', 'i'): return MCC ('p', 'l');
5855 case MCC ('g', 'e'): return MCC ('l', 'e');
5856 case MCC ('l', 't'): return MCC ('g', 't');
5857 case MCC ('g', 't'): return MCC ('l', 't');
5858 case MCC ('l', 'e'): return MCC ('g', 'e');
5859 }
5860 return cc;
5861 }
5862
5863 /* Reverse the sense of a condition. */
5864
5865 static int
5866 reverse_mri_condition (cc)
5867 int cc;
5868 {
5869 switch (cc)
5870 {
5871 case MCC ('h', 'i'): return MCC ('l', 's');
5872 case MCC ('l', 's'): return MCC ('h', 'i');
5873 case MCC ('c', 'c'): return MCC ('c', 's');
5874 case MCC ('c', 's'): return MCC ('c', 'c');
5875 case MCC ('n', 'e'): return MCC ('e', 'q');
5876 case MCC ('e', 'q'): return MCC ('n', 'e');
5877 case MCC ('v', 'c'): return MCC ('v', 's');
5878 case MCC ('v', 's'): return MCC ('v', 'c');
5879 case MCC ('p', 'l'): return MCC ('m', 'i');
5880 case MCC ('m', 'i'): return MCC ('p', 'l');
5881 case MCC ('g', 'e'): return MCC ('l', 't');
5882 case MCC ('l', 't'): return MCC ('g', 'e');
5883 case MCC ('g', 't'): return MCC ('l', 'e');
5884 case MCC ('l', 'e'): return MCC ('g', 't');
5885 }
5886 return cc;
5887 }
5888
5889 /* Build an MRI structured control expression. This generates test
5890 and branch instructions. It goes to TRUELAB if the condition is
5891 true, and to FALSELAB if the condition is false. Exactly one of
5892 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5893 is the size qualifier for the expression. EXTENT is the size to
5894 use for the branch. */
5895
5896 static void
5897 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5898 rightstop, truelab, falselab, extent)
5899 int qual;
5900 int cc;
5901 char *leftstart;
5902 char *leftstop;
5903 char *rightstart;
5904 char *rightstop;
5905 const char *truelab;
5906 const char *falselab;
5907 int extent;
5908 {
5909 char *buf;
5910 char *s;
5911
5912 if (leftstart != NULL)
5913 {
5914 struct m68k_op leftop, rightop;
5915 char c;
5916
5917 /* Swap the compare operands, if necessary, to produce a legal
5918 m68k compare instruction. Comparing a register operand with
5919 a non-register operand requires the register to be on the
5920 right (cmp, cmpa). Comparing an immediate value with
5921 anything requires the immediate value to be on the left
5922 (cmpi). */
5923
5924 c = *leftstop;
5925 *leftstop = '\0';
5926 (void) m68k_ip_op (leftstart, &leftop);
5927 *leftstop = c;
5928
5929 c = *rightstop;
5930 *rightstop = '\0';
5931 (void) m68k_ip_op (rightstart, &rightop);
5932 *rightstop = c;
5933
5934 if (rightop.mode == IMMED
5935 || ((leftop.mode == DREG || leftop.mode == AREG)
5936 && (rightop.mode != DREG && rightop.mode != AREG)))
5937 {
5938 char *temp;
5939
5940 cc = swap_mri_condition (cc);
5941 temp = leftstart;
5942 leftstart = rightstart;
5943 rightstart = temp;
5944 temp = leftstop;
5945 leftstop = rightstop;
5946 rightstop = temp;
5947 }
5948 }
5949
5950 if (truelab == NULL)
5951 {
5952 cc = reverse_mri_condition (cc);
5953 truelab = falselab;
5954 }
5955
5956 if (leftstart != NULL)
5957 {
5958 buf = (char *) xmalloc (20
5959 + (leftstop - leftstart)
5960 + (rightstop - rightstart));
5961 s = buf;
5962 *s++ = 'c';
5963 *s++ = 'm';
5964 *s++ = 'p';
5965 if (qual != '\0')
5966 *s++ = qual;
5967 *s++ = ' ';
5968 memcpy (s, leftstart, leftstop - leftstart);
5969 s += leftstop - leftstart;
5970 *s++ = ',';
5971 memcpy (s, rightstart, rightstop - rightstart);
5972 s += rightstop - rightstart;
5973 *s = '\0';
5974 mri_assemble (buf);
5975 free (buf);
5976 }
5977
5978 buf = (char *) xmalloc (20 + strlen (truelab));
5979 s = buf;
5980 *s++ = 'b';
5981 *s++ = cc >> 8;
5982 *s++ = cc & 0xff;
5983 if (extent != '\0')
5984 *s++ = extent;
5985 *s++ = ' ';
5986 strcpy (s, truelab);
5987 mri_assemble (buf);
5988 free (buf);
5989 }
5990
5991 /* Parse an MRI structured control expression. This generates test
5992 and branch instructions. STOP is where the expression ends. It
5993 goes to TRUELAB if the condition is true, and to FALSELAB if the
5994 condition is false. Exactly one of TRUELAB and FALSELAB will be
5995 NULL, meaning to fall through. QUAL is the size qualifier for the
5996 expression. EXTENT is the size to use for the branch. */
5997
5998 static void
5999 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
6000 char *stop;
6001 int qual;
6002 const char *truelab;
6003 const char *falselab;
6004 int extent;
6005 {
6006 int c;
6007 int cc;
6008 char *leftstart;
6009 char *leftstop;
6010 char *rightstart;
6011 char *rightstop;
6012
6013 c = *stop;
6014 *stop = '\0';
6015
6016 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6017 &rightstart, &rightstop))
6018 {
6019 *stop = c;
6020 return;
6021 }
6022
6023 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6024 {
6025 const char *flab;
6026
6027 if (falselab != NULL)
6028 flab = falselab;
6029 else
6030 flab = mri_control_label ();
6031
6032 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6033 rightstop, (const char *) NULL, flab, extent);
6034
6035 input_line_pointer += 3;
6036 if (*input_line_pointer != '.'
6037 || input_line_pointer[1] == '\0')
6038 qual = '\0';
6039 else
6040 {
6041 qual = input_line_pointer[1];
6042 input_line_pointer += 2;
6043 }
6044
6045 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6046 &rightstart, &rightstop))
6047 {
6048 *stop = c;
6049 return;
6050 }
6051
6052 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6053 rightstop, truelab, falselab, extent);
6054
6055 if (falselab == NULL)
6056 colon (flab);
6057 }
6058 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6059 {
6060 const char *tlab;
6061
6062 if (truelab != NULL)
6063 tlab = truelab;
6064 else
6065 tlab = mri_control_label ();
6066
6067 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6068 rightstop, tlab, (const char *) NULL, extent);
6069
6070 input_line_pointer += 2;
6071 if (*input_line_pointer != '.'
6072 || input_line_pointer[1] == '\0')
6073 qual = '\0';
6074 else
6075 {
6076 qual = input_line_pointer[1];
6077 input_line_pointer += 2;
6078 }
6079
6080 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6081 &rightstart, &rightstop))
6082 {
6083 *stop = c;
6084 return;
6085 }
6086
6087 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6088 rightstop, truelab, falselab, extent);
6089
6090 if (truelab == NULL)
6091 colon (tlab);
6092 }
6093 else
6094 {
6095 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6096 rightstop, truelab, falselab, extent);
6097 }
6098
6099 *stop = c;
6100 if (input_line_pointer != stop)
6101 as_bad (_("syntax error in structured control directive"));
6102 }
6103
6104 /* Handle the MRI IF pseudo-op. This may be a structured control
6105 directive, or it may be a regular assembler conditional, depending
6106 on its operands. */
6107
6108 static void
6109 s_mri_if (qual)
6110 int qual;
6111 {
6112 char *s;
6113 int c;
6114 struct mri_control_info *n;
6115
6116 /* A structured control directive must end with THEN with an
6117 optional qualifier. */
6118 s = input_line_pointer;
6119 while (! is_end_of_line[(unsigned char) *s]
6120 && (! flag_mri || *s != '*'))
6121 ++s;
6122 --s;
6123 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6124 --s;
6125
6126 if (s - input_line_pointer > 1
6127 && s[-1] == '.')
6128 s -= 2;
6129
6130 if (s - input_line_pointer < 3
6131 || strncasecmp (s - 3, "THEN", 4) != 0)
6132 {
6133 if (qual != '\0')
6134 {
6135 as_bad (_("missing then"));
6136 ignore_rest_of_line ();
6137 return;
6138 }
6139
6140 /* It's a conditional. */
6141 s_if (O_ne);
6142 return;
6143 }
6144
6145 /* Since this might be a conditional if, this pseudo-op will be
6146 called even if we are supported to be ignoring input. Double
6147 check now. Clobber *input_line_pointer so that ignore_input
6148 thinks that this is not a special pseudo-op. */
6149 c = *input_line_pointer;
6150 *input_line_pointer = 0;
6151 if (ignore_input ())
6152 {
6153 *input_line_pointer = c;
6154 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6155 ++input_line_pointer;
6156 demand_empty_rest_of_line ();
6157 return;
6158 }
6159 *input_line_pointer = c;
6160
6161 n = push_mri_control (mri_if);
6162
6163 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6164 n->next, s[1] == '.' ? s[2] : '\0');
6165
6166 if (s[1] == '.')
6167 input_line_pointer = s + 3;
6168 else
6169 input_line_pointer = s + 1;
6170
6171 if (flag_mri)
6172 {
6173 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6174 ++input_line_pointer;
6175 }
6176
6177 demand_empty_rest_of_line ();
6178 }
6179
6180 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6181 structured IF, associate the ELSE with the IF. Otherwise, assume
6182 it is a conditional else. */
6183
6184 static void
6185 s_mri_else (qual)
6186 int qual;
6187 {
6188 int c;
6189 char *buf;
6190 char q[2];
6191
6192 if (qual == '\0'
6193 && (mri_control_stack == NULL
6194 || mri_control_stack->type != mri_if
6195 || mri_control_stack->else_seen))
6196 {
6197 s_else (0);
6198 return;
6199 }
6200
6201 c = *input_line_pointer;
6202 *input_line_pointer = 0;
6203 if (ignore_input ())
6204 {
6205 *input_line_pointer = c;
6206 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6207 ++input_line_pointer;
6208 demand_empty_rest_of_line ();
6209 return;
6210 }
6211 *input_line_pointer = c;
6212
6213 if (mri_control_stack == NULL
6214 || mri_control_stack->type != mri_if
6215 || mri_control_stack->else_seen)
6216 {
6217 as_bad (_("else without matching if"));
6218 ignore_rest_of_line ();
6219 return;
6220 }
6221
6222 mri_control_stack->else_seen = 1;
6223
6224 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6225 q[0] = qual;
6226 q[1] = '\0';
6227 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6228 mri_assemble (buf);
6229 free (buf);
6230
6231 colon (mri_control_stack->next);
6232
6233 if (flag_mri)
6234 {
6235 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6236 ++input_line_pointer;
6237 }
6238
6239 demand_empty_rest_of_line ();
6240 }
6241
6242 /* Handle the MRI ENDI pseudo-op. */
6243
6244 static void
6245 s_mri_endi (ignore)
6246 int ignore ATTRIBUTE_UNUSED;
6247 {
6248 if (mri_control_stack == NULL
6249 || mri_control_stack->type != mri_if)
6250 {
6251 as_bad (_("endi without matching if"));
6252 ignore_rest_of_line ();
6253 return;
6254 }
6255
6256 /* ignore_input will not return true for ENDI, so we don't need to
6257 worry about checking it again here. */
6258
6259 if (! mri_control_stack->else_seen)
6260 colon (mri_control_stack->next);
6261 colon (mri_control_stack->bottom);
6262
6263 pop_mri_control ();
6264
6265 if (flag_mri)
6266 {
6267 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6268 ++input_line_pointer;
6269 }
6270
6271 demand_empty_rest_of_line ();
6272 }
6273
6274 /* Handle the MRI BREAK pseudo-op. */
6275
6276 static void
6277 s_mri_break (extent)
6278 int extent;
6279 {
6280 struct mri_control_info *n;
6281 char *buf;
6282 char ex[2];
6283
6284 n = mri_control_stack;
6285 while (n != NULL
6286 && n->type != mri_for
6287 && n->type != mri_repeat
6288 && n->type != mri_while)
6289 n = n->outer;
6290 if (n == NULL)
6291 {
6292 as_bad (_("break outside of structured loop"));
6293 ignore_rest_of_line ();
6294 return;
6295 }
6296
6297 buf = (char *) xmalloc (20 + strlen (n->bottom));
6298 ex[0] = extent;
6299 ex[1] = '\0';
6300 sprintf (buf, "bra%s %s", ex, n->bottom);
6301 mri_assemble (buf);
6302 free (buf);
6303
6304 if (flag_mri)
6305 {
6306 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6307 ++input_line_pointer;
6308 }
6309
6310 demand_empty_rest_of_line ();
6311 }
6312
6313 /* Handle the MRI NEXT pseudo-op. */
6314
6315 static void
6316 s_mri_next (extent)
6317 int extent;
6318 {
6319 struct mri_control_info *n;
6320 char *buf;
6321 char ex[2];
6322
6323 n = mri_control_stack;
6324 while (n != NULL
6325 && n->type != mri_for
6326 && n->type != mri_repeat
6327 && n->type != mri_while)
6328 n = n->outer;
6329 if (n == NULL)
6330 {
6331 as_bad (_("next outside of structured loop"));
6332 ignore_rest_of_line ();
6333 return;
6334 }
6335
6336 buf = (char *) xmalloc (20 + strlen (n->next));
6337 ex[0] = extent;
6338 ex[1] = '\0';
6339 sprintf (buf, "bra%s %s", ex, n->next);
6340 mri_assemble (buf);
6341 free (buf);
6342
6343 if (flag_mri)
6344 {
6345 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6346 ++input_line_pointer;
6347 }
6348
6349 demand_empty_rest_of_line ();
6350 }
6351
6352 /* Handle the MRI FOR pseudo-op. */
6353
6354 static void
6355 s_mri_for (qual)
6356 int qual;
6357 {
6358 const char *varstart, *varstop;
6359 const char *initstart, *initstop;
6360 const char *endstart, *endstop;
6361 const char *bystart, *bystop;
6362 int up;
6363 int by;
6364 int extent;
6365 struct mri_control_info *n;
6366 char *buf;
6367 char *s;
6368 char ex[2];
6369
6370 /* The syntax is
6371 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6372 */
6373
6374 SKIP_WHITESPACE ();
6375 varstart = input_line_pointer;
6376
6377 /* Look for the '='. */
6378 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6379 && *input_line_pointer != '=')
6380 ++input_line_pointer;
6381 if (*input_line_pointer != '=')
6382 {
6383 as_bad (_("missing ="));
6384 ignore_rest_of_line ();
6385 return;
6386 }
6387
6388 varstop = input_line_pointer;
6389 if (varstop > varstart
6390 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6391 --varstop;
6392
6393 ++input_line_pointer;
6394
6395 initstart = input_line_pointer;
6396
6397 /* Look for TO or DOWNTO. */
6398 up = 1;
6399 initstop = NULL;
6400 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6401 {
6402 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6403 && ! is_part_of_name (input_line_pointer[2]))
6404 {
6405 initstop = input_line_pointer;
6406 input_line_pointer += 2;
6407 break;
6408 }
6409 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6410 && ! is_part_of_name (input_line_pointer[6]))
6411 {
6412 initstop = input_line_pointer;
6413 up = 0;
6414 input_line_pointer += 6;
6415 break;
6416 }
6417 ++input_line_pointer;
6418 }
6419 if (initstop == NULL)
6420 {
6421 as_bad (_("missing to or downto"));
6422 ignore_rest_of_line ();
6423 return;
6424 }
6425 if (initstop > initstart
6426 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6427 --initstop;
6428
6429 SKIP_WHITESPACE ();
6430 endstart = input_line_pointer;
6431
6432 /* Look for BY or DO. */
6433 by = 0;
6434 endstop = NULL;
6435 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6436 {
6437 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6438 && ! is_part_of_name (input_line_pointer[2]))
6439 {
6440 endstop = input_line_pointer;
6441 by = 1;
6442 input_line_pointer += 2;
6443 break;
6444 }
6445 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6446 && (input_line_pointer[2] == '.'
6447 || ! is_part_of_name (input_line_pointer[2])))
6448 {
6449 endstop = input_line_pointer;
6450 input_line_pointer += 2;
6451 break;
6452 }
6453 ++input_line_pointer;
6454 }
6455 if (endstop == NULL)
6456 {
6457 as_bad (_("missing do"));
6458 ignore_rest_of_line ();
6459 return;
6460 }
6461 if (endstop > endstart
6462 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6463 --endstop;
6464
6465 if (! by)
6466 {
6467 bystart = "#1";
6468 bystop = bystart + 2;
6469 }
6470 else
6471 {
6472 SKIP_WHITESPACE ();
6473 bystart = input_line_pointer;
6474
6475 /* Look for DO. */
6476 bystop = NULL;
6477 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6478 {
6479 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6480 && (input_line_pointer[2] == '.'
6481 || ! is_part_of_name (input_line_pointer[2])))
6482 {
6483 bystop = input_line_pointer;
6484 input_line_pointer += 2;
6485 break;
6486 }
6487 ++input_line_pointer;
6488 }
6489 if (bystop == NULL)
6490 {
6491 as_bad (_("missing do"));
6492 ignore_rest_of_line ();
6493 return;
6494 }
6495 if (bystop > bystart
6496 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6497 --bystop;
6498 }
6499
6500 if (*input_line_pointer != '.')
6501 extent = '\0';
6502 else
6503 {
6504 extent = input_line_pointer[1];
6505 input_line_pointer += 2;
6506 }
6507
6508 /* We have fully parsed the FOR operands. Now build the loop. */
6509
6510 n = push_mri_control (mri_for);
6511
6512 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6513
6514 /* move init,var */
6515 s = buf;
6516 *s++ = 'm';
6517 *s++ = 'o';
6518 *s++ = 'v';
6519 *s++ = 'e';
6520 if (qual != '\0')
6521 *s++ = qual;
6522 *s++ = ' ';
6523 memcpy (s, initstart, initstop - initstart);
6524 s += initstop - initstart;
6525 *s++ = ',';
6526 memcpy (s, varstart, varstop - varstart);
6527 s += varstop - varstart;
6528 *s = '\0';
6529 mri_assemble (buf);
6530
6531 colon (n->top);
6532
6533 /* cmp end,var */
6534 s = buf;
6535 *s++ = 'c';
6536 *s++ = 'm';
6537 *s++ = 'p';
6538 if (qual != '\0')
6539 *s++ = qual;
6540 *s++ = ' ';
6541 memcpy (s, endstart, endstop - endstart);
6542 s += endstop - endstart;
6543 *s++ = ',';
6544 memcpy (s, varstart, varstop - varstart);
6545 s += varstop - varstart;
6546 *s = '\0';
6547 mri_assemble (buf);
6548
6549 /* bcc bottom */
6550 ex[0] = extent;
6551 ex[1] = '\0';
6552 if (up)
6553 sprintf (buf, "blt%s %s", ex, n->bottom);
6554 else
6555 sprintf (buf, "bgt%s %s", ex, n->bottom);
6556 mri_assemble (buf);
6557
6558 /* Put together the add or sub instruction used by ENDF. */
6559 s = buf;
6560 if (up)
6561 strcpy (s, "add");
6562 else
6563 strcpy (s, "sub");
6564 s += 3;
6565 if (qual != '\0')
6566 *s++ = qual;
6567 *s++ = ' ';
6568 memcpy (s, bystart, bystop - bystart);
6569 s += bystop - bystart;
6570 *s++ = ',';
6571 memcpy (s, varstart, varstop - varstart);
6572 s += varstop - varstart;
6573 *s = '\0';
6574 n->incr = buf;
6575
6576 if (flag_mri)
6577 {
6578 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6579 ++input_line_pointer;
6580 }
6581
6582 demand_empty_rest_of_line ();
6583 }
6584
6585 /* Handle the MRI ENDF pseudo-op. */
6586
6587 static void
6588 s_mri_endf (ignore)
6589 int ignore ATTRIBUTE_UNUSED;
6590 {
6591 if (mri_control_stack == NULL
6592 || mri_control_stack->type != mri_for)
6593 {
6594 as_bad (_("endf without for"));
6595 ignore_rest_of_line ();
6596 return;
6597 }
6598
6599 colon (mri_control_stack->next);
6600
6601 mri_assemble (mri_control_stack->incr);
6602
6603 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6604 mri_assemble (mri_control_stack->incr);
6605
6606 free (mri_control_stack->incr);
6607
6608 colon (mri_control_stack->bottom);
6609
6610 pop_mri_control ();
6611
6612 if (flag_mri)
6613 {
6614 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6615 ++input_line_pointer;
6616 }
6617
6618 demand_empty_rest_of_line ();
6619 }
6620
6621 /* Handle the MRI REPEAT pseudo-op. */
6622
6623 static void
6624 s_mri_repeat (ignore)
6625 int ignore ATTRIBUTE_UNUSED;
6626 {
6627 struct mri_control_info *n;
6628
6629 n = push_mri_control (mri_repeat);
6630 colon (n->top);
6631 if (flag_mri)
6632 {
6633 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6634 ++input_line_pointer;
6635 }
6636 demand_empty_rest_of_line ();
6637 }
6638
6639 /* Handle the MRI UNTIL pseudo-op. */
6640
6641 static void
6642 s_mri_until (qual)
6643 int qual;
6644 {
6645 char *s;
6646
6647 if (mri_control_stack == NULL
6648 || mri_control_stack->type != mri_repeat)
6649 {
6650 as_bad (_("until without repeat"));
6651 ignore_rest_of_line ();
6652 return;
6653 }
6654
6655 colon (mri_control_stack->next);
6656
6657 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6658 ;
6659
6660 parse_mri_control_expression (s, qual, (const char *) NULL,
6661 mri_control_stack->top, '\0');
6662
6663 colon (mri_control_stack->bottom);
6664
6665 input_line_pointer = s;
6666
6667 pop_mri_control ();
6668
6669 if (flag_mri)
6670 {
6671 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6672 ++input_line_pointer;
6673 }
6674
6675 demand_empty_rest_of_line ();
6676 }
6677
6678 /* Handle the MRI WHILE pseudo-op. */
6679
6680 static void
6681 s_mri_while (qual)
6682 int qual;
6683 {
6684 char *s;
6685
6686 struct mri_control_info *n;
6687
6688 s = input_line_pointer;
6689 while (! is_end_of_line[(unsigned char) *s]
6690 && (! flag_mri || *s != '*'))
6691 s++;
6692 --s;
6693 while (*s == ' ' || *s == '\t')
6694 --s;
6695 if (s - input_line_pointer > 1
6696 && s[-1] == '.')
6697 s -= 2;
6698 if (s - input_line_pointer < 2
6699 || strncasecmp (s - 1, "DO", 2) != 0)
6700 {
6701 as_bad (_("missing do"));
6702 ignore_rest_of_line ();
6703 return;
6704 }
6705
6706 n = push_mri_control (mri_while);
6707
6708 colon (n->next);
6709
6710 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6711 s[1] == '.' ? s[2] : '\0');
6712
6713 input_line_pointer = s + 1;
6714 if (*input_line_pointer == '.')
6715 input_line_pointer += 2;
6716
6717 if (flag_mri)
6718 {
6719 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6720 ++input_line_pointer;
6721 }
6722
6723 demand_empty_rest_of_line ();
6724 }
6725
6726 /* Handle the MRI ENDW pseudo-op. */
6727
6728 static void
6729 s_mri_endw (ignore)
6730 int ignore ATTRIBUTE_UNUSED;
6731 {
6732 char *buf;
6733
6734 if (mri_control_stack == NULL
6735 || mri_control_stack->type != mri_while)
6736 {
6737 as_bad (_("endw without while"));
6738 ignore_rest_of_line ();
6739 return;
6740 }
6741
6742 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6743 sprintf (buf, "bra %s", mri_control_stack->next);
6744 mri_assemble (buf);
6745 free (buf);
6746
6747 colon (mri_control_stack->bottom);
6748
6749 pop_mri_control ();
6750
6751 if (flag_mri)
6752 {
6753 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6754 ++input_line_pointer;
6755 }
6756
6757 demand_empty_rest_of_line ();
6758 }
6759 \f
6760 /*
6761 * md_parse_option
6762 * Invocation line includes a switch not recognized by the base assembler.
6763 * See if it's a processor-specific option. These are:
6764 *
6765 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6766 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6767 * Select the architecture. Instructions or features not
6768 * supported by the selected architecture cause fatal
6769 * errors. More than one may be specified. The default is
6770 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6771 * for -m68000, and -m68882 is a synonym for -m68881.
6772 * -[A]m[c]no-68851, -[A]m[c]no-68881
6773 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6774 * so don't use or document it, but that's the way the parsing
6775 * works).
6776 *
6777 * -pic Indicates PIC.
6778 * -k Indicates PIC. (Sun 3 only.)
6779 * --pcrel Never turn PC-relative branches into absolute jumps.
6780 *
6781 * --bitwise-or
6782 * Permit `|' to be used in expressions.
6783 *
6784 */
6785
6786 #ifdef OBJ_ELF
6787 CONST char *md_shortopts = "lSA:m:kQ:V";
6788 #else
6789 CONST char *md_shortopts = "lSA:m:k";
6790 #endif
6791
6792 struct option md_longopts[] = {
6793 #define OPTION_PIC (OPTION_MD_BASE)
6794 {"pic", no_argument, NULL, OPTION_PIC},
6795 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6796 {"register-prefix-optional", no_argument, NULL,
6797 OPTION_REGISTER_PREFIX_OPTIONAL},
6798 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6799 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6800 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6801 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6802 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6803 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6804 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6805 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6806 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6807 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6808 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6809 {"pcrel", no_argument, NULL, OPTION_PCREL},
6810 {NULL, no_argument, NULL, 0}
6811 };
6812 size_t md_longopts_size = sizeof(md_longopts);
6813
6814 int
6815 md_parse_option (c, arg)
6816 int c;
6817 char *arg;
6818 {
6819 switch (c)
6820 {
6821 case 'l': /* -l means keep external to 2 bit offset
6822 rather than 16 bit one */
6823 flag_short_refs = 1;
6824 break;
6825
6826 case 'S': /* -S means that jbsr's always turn into
6827 jsr's. */
6828 flag_long_jumps = 1;
6829 break;
6830
6831 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6832 branches into absolute jumps. */
6833 flag_keep_pcrel = 1;
6834 break;
6835
6836 case 'A':
6837 if (*arg == 'm')
6838 arg++;
6839 /* intentional fall-through */
6840 case 'm':
6841
6842 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6843 {
6844 int i;
6845 unsigned long arch;
6846 const char *oarg = arg;
6847
6848 arg += 3;
6849 if (*arg == 'm')
6850 {
6851 arg++;
6852 if (arg[0] == 'c' && arg[1] == '6')
6853 arg++;
6854 }
6855 for (i = 0; i < n_archs; i++)
6856 if (!strcmp (arg, archs[i].name))
6857 break;
6858 if (i == n_archs)
6859 {
6860 unknown:
6861 as_bad (_("unrecognized option `%s'"), oarg);
6862 return 0;
6863 }
6864 arch = archs[i].arch;
6865 if (arch == m68881)
6866 no_68881 = 1;
6867 else if (arch == m68851)
6868 no_68851 = 1;
6869 else
6870 goto unknown;
6871 }
6872 else
6873 {
6874 int i;
6875
6876 if (arg[0] == 'c' && arg[1] == '6')
6877 arg++;
6878
6879 for (i = 0; i < n_archs; i++)
6880 if (!strcmp (arg, archs[i].name))
6881 {
6882 unsigned long arch = archs[i].arch;
6883 if (cpu_of_arch (arch))
6884 /* It's a cpu spec. */
6885 {
6886 current_architecture &= ~m68000up;
6887 current_architecture |= arch;
6888 }
6889 else if (arch == m68881)
6890 {
6891 current_architecture |= m68881;
6892 no_68881 = 0;
6893 }
6894 else if (arch == m68851)
6895 {
6896 current_architecture |= m68851;
6897 no_68851 = 0;
6898 }
6899 else
6900 /* ??? */
6901 abort ();
6902 break;
6903 }
6904 if (i == n_archs)
6905 {
6906 as_bad (_("unrecognized architecture specification `%s'"), arg);
6907 return 0;
6908 }
6909 }
6910 break;
6911
6912 case OPTION_PIC:
6913 case 'k':
6914 flag_want_pic = 1;
6915 break; /* -pic, Position Independent Code */
6916
6917 case OPTION_REGISTER_PREFIX_OPTIONAL:
6918 flag_reg_prefix_optional = 1;
6919 reg_prefix_optional_seen = 1;
6920 break;
6921
6922 /* -V: SVR4 argument to print version ID. */
6923 case 'V':
6924 print_version_id ();
6925 break;
6926
6927 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6928 should be emitted or not. FIXME: Not implemented. */
6929 case 'Q':
6930 break;
6931
6932 case OPTION_BITWISE_OR:
6933 {
6934 char *n, *t;
6935 const char *s;
6936
6937 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6938 t = n;
6939 for (s = m68k_comment_chars; *s != '\0'; s++)
6940 if (*s != '|')
6941 *t++ = *s;
6942 *t = '\0';
6943 m68k_comment_chars = n;
6944 }
6945 break;
6946
6947 case OPTION_BASE_SIZE_DEFAULT_16:
6948 m68k_index_width_default = SIZE_WORD;
6949 break;
6950
6951 case OPTION_BASE_SIZE_DEFAULT_32:
6952 m68k_index_width_default = SIZE_LONG;
6953 break;
6954
6955 case OPTION_DISP_SIZE_DEFAULT_16:
6956 m68k_rel32 = 0;
6957 m68k_rel32_from_cmdline = 1;
6958 break;
6959
6960 case OPTION_DISP_SIZE_DEFAULT_32:
6961 m68k_rel32 = 1;
6962 m68k_rel32_from_cmdline = 1;
6963 break;
6964
6965 default:
6966 return 0;
6967 }
6968
6969 return 1;
6970 }
6971
6972 void
6973 md_show_usage (stream)
6974 FILE *stream;
6975 {
6976 fprintf(stream, _("\
6977 680X0 options:\n\
6978 -l use 1 word for refs to undefined symbols [default 2]\n\
6979 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6980 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6981 | -mcpu32 | -m5200\n\
6982 specify variant of 680X0 architecture [default 68020]\n\
6983 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6984 target has/lacks floating-point coprocessor\n\
6985 [default yes for 68020, 68030, and cpu32]\n"));
6986 fprintf(stream, _("\
6987 -m68851 | -mno-68851\n\
6988 target has/lacks memory-management unit coprocessor\n\
6989 [default yes for 68020 and up]\n\
6990 -pic, -k generate position independent code\n\
6991 -S turn jbsr into jsr\n\
6992 --pcrel never turn PC-relative branches into absolute jumps\n\
6993 --register-prefix-optional\n\
6994 recognize register names without prefix character\n\
6995 --bitwise-or do not treat `|' as a comment character\n"));
6996 fprintf (stream, _("\
6997 --base-size-default-16 base reg without size is 16 bits\n\
6998 --base-size-default-32 base reg without size is 32 bits (default)\n\
6999 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7000 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7001 }
7002 \f
7003 #ifdef TEST2
7004
7005 /* TEST2: Test md_assemble() */
7006 /* Warning, this routine probably doesn't work anymore */
7007
7008 main ()
7009 {
7010 struct m68k_it the_ins;
7011 char buf[120];
7012 char *cp;
7013 int n;
7014
7015 m68k_ip_begin ();
7016 for (;;)
7017 {
7018 if (!gets (buf) || !*buf)
7019 break;
7020 if (buf[0] == '|' || buf[1] == '.')
7021 continue;
7022 for (cp = buf; *cp; cp++)
7023 if (*cp == '\t')
7024 *cp = ' ';
7025 if (is_label (buf))
7026 continue;
7027 memset (&the_ins, '\0', sizeof (the_ins));
7028 m68k_ip (&the_ins, buf);
7029 if (the_ins.error)
7030 {
7031 printf (_("Error %s in %s\n"), the_ins.error, buf);
7032 }
7033 else
7034 {
7035 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7036 for (n = 0; n < the_ins.numo; n++)
7037 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7038 printf (" ");
7039 print_the_insn (&the_ins.opcode[0], stdout);
7040 (void) putchar ('\n');
7041 }
7042 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7043 {
7044 if (the_ins.operands[n].error)
7045 {
7046 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7047 continue;
7048 }
7049 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7050 if (the_ins.operands[n].b_const)
7051 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7052 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7053 if (the_ins.operands[n].b_iadd)
7054 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7055 (void) putchar ('\n');
7056 }
7057 }
7058 m68k_ip_end ();
7059 return 0;
7060 }
7061
7062 is_label (str)
7063 char *str;
7064 {
7065 while (*str == ' ')
7066 str++;
7067 while (*str && *str != ' ')
7068 str++;
7069 if (str[-1] == ':' || str[1] == '=')
7070 return 1;
7071 return 0;
7072 }
7073
7074 #endif
7075
7076 /* Possible states for relaxation:
7077
7078 0 0 branch offset byte (bra, etc)
7079 0 1 word
7080 0 2 long
7081
7082 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7083 1 1 word
7084 1 2 long
7085
7086 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7087 2 1 word-long
7088 2 2 long-word
7089 2 3 long-long
7090
7091 */
7092
7093 /* We have no need to default values of symbols. */
7094
7095 /* ARGSUSED */
7096 symbolS *
7097 md_undefined_symbol (name)
7098 char *name ATTRIBUTE_UNUSED;
7099 {
7100 return 0;
7101 }
7102
7103 /* Round up a section size to the appropriate boundary. */
7104 valueT
7105 md_section_align (segment, size)
7106 segT segment ATTRIBUTE_UNUSED;
7107 valueT size;
7108 {
7109 #ifdef OBJ_AOUT
7110 #ifdef BFD_ASSEMBLER
7111 /* For a.out, force the section size to be aligned. If we don't do
7112 this, BFD will align it for us, but it will not write out the
7113 final bytes of the section. This may be a bug in BFD, but it is
7114 easier to fix it here since that is how the other a.out targets
7115 work. */
7116 int align;
7117
7118 align = bfd_get_section_alignment (stdoutput, segment);
7119 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7120 #endif
7121 #endif
7122
7123 return size;
7124 }
7125
7126 /* Exactly what point is a PC-relative offset relative TO?
7127 On the 68k, it is relative to the address of the first extension
7128 word. The difference between the addresses of the offset and the
7129 first extension word is stored in fx_pcrel_adjust. */
7130 long
7131 md_pcrel_from (fixP)
7132 fixS *fixP;
7133 {
7134 int adjust;
7135
7136 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7137 -1 as 64. */
7138 adjust = fixP->fx_pcrel_adjust;
7139 if (adjust == 64)
7140 adjust = -1;
7141 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7142 }
7143
7144 #ifndef BFD_ASSEMBLER
7145 #ifdef OBJ_COFF
7146
7147 /*ARGSUSED*/
7148 void
7149 tc_coff_symbol_emit_hook (ignore)
7150 symbolS *ignore ATTRIBUTE_UNUSED;
7151 {
7152 }
7153
7154 int
7155 tc_coff_sizemachdep (frag)
7156 fragS *frag;
7157 {
7158 switch (frag->fr_subtype & 0x3)
7159 {
7160 case BYTE:
7161 return 1;
7162 case SHORT:
7163 return 2;
7164 case LONG:
7165 return 4;
7166 default:
7167 abort ();
7168 return 0;
7169 }
7170 }
7171
7172 #endif
7173 #endif
7174 #ifdef OBJ_ELF
7175 void m68k_elf_final_processing()
7176 {
7177 /* Set file-specific flags if this is a cpu32 processor */
7178 if (cpu_of_arch (current_architecture) & cpu32)
7179 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7180 }
7181 #endif
7182 /* end of tc-m68k.c */