1 /* tc-m68k.c All the m68020 specific stuff in one convenient, huge,
2 slow to compile, easy to find file.
4 Copyright (C) 1987, 1991, 1992 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
31 /* The opcode table is too big for gcc, which (currently) requires
32 exponential space at compile time for initialized arrays. */
34 #define DO_BREAK_UP_BIG_DECL
35 #define BREAK_UP_BIG_DECL }; struct m68k_opcode m68k_opcodes_2[] = {
36 #define AND_OTHER_PART sizeof (m68k_opcodes_2)
39 /* Note that this file includes real declarations and thus can only be
40 included by one source file per executable. */
41 #include "opcode/m68k.h"
45 /* This variable contains the value to write out at the beginning of
46 the a.out file. The 2<<16 means that this is a 68020 file instead
47 of an old-style 68000 file */
49 long omagic
= 2 << 16 | OMAGIC
; /* Magic byte for header file */
55 /* This array holds the chars that always start a comment. If the
56 pre-processor is disabled, these aren't very useful */
57 CONST
char comment_chars
[] = "|";
59 /* This array holds the chars that only start a comment at the beginning of
60 a line. If the line seems to have the form '# 123 filename'
61 .line and .file directives will appear in the pre-processed output */
62 /* Note that input_file.c hand checks for '#' at the beginning of the
63 first line of the input file. This is because the compiler outputs
64 #NO_APP at the beginning of its output. */
65 /* Also note that comments like this one will always work. */
66 CONST
char line_comment_chars
[] = "#";
68 CONST
char line_separator_chars
[] = "";
70 /* Chars that can be used to separate mant from exp in floating point nums */
71 CONST
char EXP_CHARS
[] = "eE";
73 /* Chars that mean this number is a floating point constant, as
74 in "0f12.456" or "0d1.2345e12". */
76 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
78 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
79 changed in read.c . Ideally it shouldn't have to know about it at all,
80 but nothing is ideal around here. */
82 const int md_reloc_size
= 8; /* Size of relocation record */
84 /* Its an arbitrary name: This means I don't approve of it */
85 /* See flames below */
86 static struct obstack robyn
;
88 #define TAB(x,y) (((x)<<2)+(y))
89 #define TABTYPE(xy) ((xy) >> 2)
102 /* Operands we can parse: (And associated modes)
108 reg: address or data register
109 areg: address register
110 apc: address register, PC, ZPC or empty string
111 num: 16 or 32 bit num
113 sz: w or l if omitted, l assumed
114 scale: 1 2 4 or 8 if omitted, 1 assumed
116 7.4 IMMED #num --> NUM
117 0.? DREG dreg --> dreg
118 1.? AREG areg --> areg
119 2.? AINDR areg@ --> *(areg)
120 3.? AINC areg@+ --> *(areg++)
121 4.? ADEC areg@- --> *(--areg)
122 5.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here
123 6.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale)
124 6.? AINDX apc@(reg:sz:scale) --> same, with num=0
125 6.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale)
126 6.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0
127 6.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg)
128 6.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2)
129 6.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0
130 7.0 ABSL num:sz --> *(num)
131 num --> *(num) (sz L assumed)
132 *** MSCR otherreg --> Magic
134 5.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still
135 ?.? DINDR dreg@ --> (dreg) -- cas2 only
145 a1@(5,d2:w:1) @(45,d6:l:4)
150 #name@(numw) -->turn into PC rel mode
151 apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale)
180 short e_siz
; /* 0== default 1==short/byte 2==word 3==long */
183 /* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg,
184 8-15==addr reg for operands that take both types */
188 DATA
= 1, /* 1- 8 == data registers 0-7 */
208 /* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */
213 FPREG
, /* Eight FP registers */
222 COPNUM
= (FPREG
+ 8), /* Co-processor #1-#8 */
231 PC
, /* Program counter */
232 ZPC
, /* Hack for Program space, but 0 addressing */
234 CCR
, /* Condition code Reg */
236 /* These have to be in order for the movec instruction to work. */
237 USP
, /* User Stack Pointer */
238 ISP
, /* Interrupt stack pointer */
253 /* end of movec ordering constraints */
259 DRP
, /* 68851 or 68030 MMU regs */
283 PSR
, /* aka MMUSR on 68030 (but not MMUSR on 68040)
284 and ACUSR on 68ec030 */
287 IC
, /* instruction cache token */
288 DC
, /* data cache token */
289 NC
, /* no cache token */
290 BC
, /* both caches token */
292 TT0
, /* 68030 access control unit regs */
296 /* Internal form of an operand. */
299 char *error
; /* Couldn't parse it */
300 enum operand_type mode
; /* What mode this instruction is in. */
301 enum _register reg
; /* Base register */
302 struct m68k_exp
*con1
;
303 int ireg
; /* Index register */
304 int isiz
; /* 0==unspec 1==byte(?) 2==short 3==long */
305 int imul
; /* Multipy ireg by this (1,2,4,or 8) */
306 struct m68k_exp
*con2
;
309 /* internal form of a 68020 instruction */
313 char *args
; /* list of opcode info */
316 int numo
; /* Number of shorts in opcode */
319 struct m68k_op operands
[6];
321 int nexp
; /* number of exprs in use */
322 struct m68k_exp exprs
[4];
324 int nfrag
; /* Number of frags we have to produce */
327 int fragoff
; /* Where in the current opcode[] the frag ends */
334 int nrel
; /* Num of reloc strucs in use */
343 reloc
[5]; /* Five is enough??? */
346 #define cpu_of_arch(x) ((x) & m68000up)
347 #define float_of_arch(x) ((x) & mfloat)
348 #define mmu_of_arch(x) ((x) & mmmu)
350 static struct m68k_it the_ins
; /* the instruction being assembled */
352 #define seg(exp) ((exp)->e_exp.X_seg)
353 #define adds(exp) ((exp)->e_exp.X_add_symbol)
354 #define subs(exp) ((exp)->e_exp.X_subtract_symbol)
355 #define offs(exp) ((exp)->e_exp.X_add_number)
357 /* Macros for adding things to the m68k_it struct */
359 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
361 /* Like addword, but goes BEFORE general operands */
362 #define insop(w) {int z;\
363 for(z=the_ins.numo;z>opcode->m_codenum;--z)\
364 the_ins.opcode[z]=the_ins.opcode[z-1];\
365 for(z=0;z<the_ins.nrel;z++)\
366 the_ins.reloc[z].n+=2;\
367 the_ins.opcode[opcode->m_codenum]=w;\
372 #define add_exp(beg,end) (\
373 the_ins.exprs[the_ins.nexp].e_beg=beg,\
374 the_ins.exprs[the_ins.nexp].e_end=end,\
375 &the_ins.exprs[the_ins.nexp++]\
379 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
382 add_fix (width
, exp
, pc_rel
)
384 struct m68k_exp
*exp
;
387 the_ins
.reloc
[the_ins
.nrel
].n
= (((width
)=='B')
390 ? ((the_ins
.numo
-1)*2)
391 : (the_ins
.numo
*2)));
392 the_ins
.reloc
[the_ins
.nrel
].add
= adds((exp
));
393 the_ins
.reloc
[the_ins
.nrel
].sub
= subs((exp
));
394 the_ins
.reloc
[the_ins
.nrel
].off
= offs((exp
));
395 the_ins
.reloc
[the_ins
.nrel
].wid
= width
;
396 the_ins
.reloc
[the_ins
.nrel
++].pcrel
= pc_rel
;
400 add_frag(add
,off
,type
)
405 the_ins
.fragb
[the_ins
.nfrag
].fragoff
=the_ins
.numo
;
406 the_ins
.fragb
[the_ins
.nfrag
].fadd
=add
;
407 the_ins
.fragb
[the_ins
.nfrag
].foff
=off
;
408 the_ins
.fragb
[the_ins
.nfrag
++].fragty
=type
;
411 #define isvar(exp) ((exp) && (adds(exp) || subs(exp)))
416 unsigned long m_opcode
;
420 struct m68k_incant
*m_next
;
425 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
426 #define gettwo(x) (((x)->m_opcode)&0xffff)
429 static char *crack_operand
PARAMS ((char *str
, struct m68k_op
*opP
));
430 static int get_num
PARAMS ((struct m68k_exp
*exp
, int ok
));
431 static int get_regs
PARAMS ((int i
, char *str
, struct m68k_op
*opP
));
432 static int reverse_16_bits
PARAMS ((int in
));
433 static int reverse_8_bits
PARAMS ((int in
));
434 static int try_index
PARAMS ((char **s
, struct m68k_op
*opP
));
435 static void install_gen_operand
PARAMS ((int mode
, int val
));
436 static void install_operand
PARAMS ((int mode
, int val
));
437 static void s_bss
PARAMS ((void));
438 static void s_data1
PARAMS ((void));
439 static void s_data2
PARAMS ((void));
440 static void s_even
PARAMS ((void));
441 static void s_proc
PARAMS ((void));
443 static int current_architecture
;
445 /* BCC68000 is for patching in an extra jmp instruction for long offsets
446 on the 68000. The 68000 doesn't support long branches with branchs */
448 /* This table desribes how you change sizes for the various types of variable
449 size expressions. This version only supports two kinds. */
451 /* Note that calls to frag_var need to specify the maximum expansion
452 needed; this is currently 10 bytes for DBCC. */
455 How far Forward this mode will reach:
456 How far Backward this mode will reach:
457 How many bytes this mode will add to the size of the frag
458 Which mode to go to if the offset won't fit in this one
460 CONST relax_typeS md_relax_table
[] =
462 {1, 1, 0, 0}, /* First entries aren't used */
463 {1, 1, 0, 0}, /* For no good reason except */
464 {1, 1, 0, 0}, /* that the VAX doesn't either */
467 {(127), (-128), 0, TAB (ABRANCH
, SHORT
)},
468 {(32767), (-32768), 2, TAB (ABRANCH
, LONG
)},
472 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
473 {(32767), (-32768), 2, TAB (FBRANCH
, LONG
)},
477 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
478 {(32767), (-32768), 2, TAB (PCREL
, LONG
)},
482 {(127), (-128), 0, TAB (BCC68000
, SHORT
)},
483 {(32767), (-32768), 2, TAB (BCC68000
, LONG
)},
484 {0, 0, 6, 0}, /* jmp long space */
487 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
488 {(32767), (-32768), 2, TAB (DBCC
, LONG
)},
489 {0, 0, 10, 0}, /* bra/jmp long space */
492 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
493 {32767, -32768, 2, TAB (PCLEA
, LONG
)},
499 /* These are the machine dependent pseudo-ops. These are included so
500 the assembler can work on the output from the SUN C compiler, which
504 /* This table describes all the machine specific pseudo-ops the assembler
505 has to support. The fields are:
506 pseudo-op name without dot
507 function to call to execute this pseudo-op
508 Integer arg to pass to the function
510 CONST pseudo_typeS md_pseudo_table
[] =
512 {"data1", s_data1
, 0},
513 {"data2", s_data2
, 0},
516 {"skip", s_space
, 0},
519 {"align", s_align_bytes
, 0},
525 /* The mote pseudo ops are put into the opcode table, since they
526 don't start with a . they look like opcodes to gas.
528 extern void obj_coff_section ();
530 CONST pseudo_typeS mote_pseudo_table
[] =
538 {"ds.l", s_space
, 4},
540 {"ds.w", s_space
, 2},
541 {"ds.b", s_space
, 1},
543 {"xdef", s_globl
, 0},
544 {"align", s_align_ptwo
, 0},
546 {"sect", obj_coff_section
, 0},
547 {"section", obj_coff_section
, 0},
552 #define issbyte(x) ((x)>=-128 && (x)<=127)
553 #define isubyte(x) ((x)>=0 && (x)<=255)
554 #define issword(x) ((x)>=-32768 && (x)<=32767)
555 #define isuword(x) ((x)>=0 && (x)<=65535)
557 #define isbyte(x) ((x)>= -255 && (x)<=255)
558 #define isword(x) ((x)>=-32768 && (x)<=65535)
559 #define islong(x) (1)
561 extern char *input_line_pointer
;
569 /* JF these tables here are for speed at the expense of size */
570 /* You can replace them with the #if 0 versions if you really
571 need space and don't mind it running a bit slower */
573 static char mklower_table
[256];
574 #define mklower(c) (mklower_table[(unsigned char)(c)])
575 static char notend_table
[256];
576 static char alt_notend_table
[256];
577 #define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\
578 alt_notend_table[(unsigned char)(s[1])])))
581 #define mklower(c) (isupper(c) ? tolower(c) : c)
585 /* JF modified this to handle cases where the first part of a symbol name
586 looks like a register */
589 * m68k_reg_parse() := if it looks like a register, return it's token &
590 * advance the pointer.
602 #ifdef REGISTER_PREFIX
603 if (*start
!= REGISTER_PREFIX
)
608 if (*p
== OPTIONAL_REGISTER_PREFIX
)
611 if (!isalpha (*p
) || !is_name_beginner (*p
))
615 while (isalpha (c
) || isdigit (c
) || c
== '_')
621 symbolP
= symbol_find (start
);
624 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
627 return S_GET_VALUE (symbolP
);
633 #define SKIP_WHITE() { str++; if(*str==' ') str++;}
634 #define SKIP_W() { ss++; if(*ss==' ') ss++;}
636 /* Parse an index specification using Motorola syntax. */
639 try_moto_index (s
, opP
)
650 i
= m68k_reg_parse (&ss
);
651 if (!(i
>= DATA
+ 0 && i
<= ADDR
+ 7))
652 { /* if i is not DATA or ADDR reg */
653 opP
->error
= "Invalid index register";
669 opP
->error
= "Missing . in index register";
674 if (mklower (*ss
) == 'w')
676 else if (mklower (*ss
) == 'l')
680 opP
->error
= "Size spec not .W or .L";
685 if (*ss
== '.' || *ss
== '*')
694 opP
->imul
= *ss
- '0';
697 opP
->error
= "index multiplier not 1, 2, 4 or 8";
707 opP
->error
= "Missing )";
718 * try_index := data_or_address_register + ')' + SKIP_W
719 * | data_or_address_register + ':' + SKIP_W + size_spec + SKIP_W + multiplier + ')' + SKIP_W
721 * multiplier := <empty>
722 * | ':' + multiplier_number
725 * multiplier_number := '1' | '2' | '4' | '8' ;
727 * size_spec := 'l' | 'L' | 'w' | 'W' ;
729 * SKIP_W := <empty> | ' ' ;
743 i
= m68k_reg_parse (&ss
);
744 if (!(i
>= DATA
+ 0 && i
<= ADDR
+ 7))
745 { /* if i is not DATA or ADDR reg */
761 opP
->error
= "Missing : in index register";
777 opP
->error
= "Index register size spec not :w or :l";
791 if (cpu_of_arch (current_architecture
) < m68020
)
793 opP
->error
= "no index scaling in pre-68020's";
797 opP
->imul
= *ss
- '0';
800 opP
->error
= "index multiplier not 1, 2, 4 or 8";
810 opP
->error
= "Missing )";
819 /* Ian Taylor expanded this function to accept both MIT and Motorola
820 syntax. I removed the old comment, since it was wrong. The syntax
821 this accepted even before my changes was complex and undocumented.
822 I mainly added a large case when the operand string does not
823 contain an '@', since the Motorola syntax does not use the '@'
827 m68k_ip_op (str
, opP
)
829 register struct m68k_op
*opP
;
833 char *parse_index ();
839 } /* Find the beginning of the string */
843 opP
->error
= "Missing operand";
847 for (strend
= str
; *strend
; strend
++)
854 opP
->con1
= add_exp (str
, strend
);
857 } /* Guess what: A constant. Shar and enjoy */
859 i
= m68k_reg_parse (&str
);
863 if (*str
== '/' || *str
== '-')
865 /* "Rm-Rn/Ro-Rp" Register list for MOVEM instruction */
867 return get_regs (i
, str
, opP
);
872 /* "Rn" Register Direct mode */
873 if (i
>= DATA
+ 0 && i
<= DATA
+ 7)
875 else if (i
>= ADDR
+ 0 && i
<= ADDR
+ 7)
887 if ((stmp
= strchr (str
, '@')) != 0)
889 opP
->con1
= add_exp (str
, stmp
- 1);
896 if ((current_architecture
& m68020up
) == 0)
899 } /* if target is not a '20 or better */
902 if (*stmp
++ != '(' || *strend
-- != ')')
904 opP
->error
= "Malformed operand";
907 i
= try_index (&stmp
, opP
);
908 opP
->con2
= add_exp (stmp
, strend
);
919 } /* if there's an '@' */
921 #ifndef MIT_SYNTAX_ONLY
922 /* The operand has no '@'. Try to parse it using
924 /* Logic of the parsing switch(*str):
928 REG AREG or DREG or MSCR 3 or 2 or 13
929 REG- or REG/ REGLST 14
934 (EXPR,REG,INDX) AINDX 8
937 EXP2(REG,INDX) AINDX 8
940 REG means truth(m68k_reg_parse(&str))
941 INDX means truth(try_moto_index(&str,opP))
943 EXP2 means not REG and not '(' and not '-('
949 i
= m68k_reg_parse (&str
);
950 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7)
951 && (i
< DATA
+ 0 || i
> DATA
+ 7
952 || *str
!= ')' || str
[1] != '0')
953 && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
)
955 /* Can't indirect off non address regs */
956 opP
->error
= "Invalid indirect register";
967 /* "(An)" Address Register Indirect mode
968 or "(Dn)" for cas2. */
969 if (i
>= DATA
+ 0 && i
<= DATA
+ 7)
979 /* "(An)+" Register Indirect w Postincrement */
984 opP
->error
= "Junk after indirect";
990 i
= try_moto_index (&str
, opP
);
993 /* "(An,Rn)" Register Indirect with Index mode*/
999 opP
->error
= "Bad indirect syntax";
1005 /* "(EXPR,..." , a displacement */
1009 if (stmp
= index (str
, ','))
1011 opP
->con1
= add_exp (str
, stmp
- 1);
1014 i
= m68k_reg_parse (&str
);
1015 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
)
1017 /* Can't indirect off non address regs */
1018 opP
->error
= "Invalid indirect register";
1026 /* "(d,An)" Register Indirect w Displacement */
1033 i
= try_moto_index (&str
, opP
);
1036 /* "(d,An,Rn)" Register Indirect with Index */
1042 opP
->error
= "Bad indirect syntax";
1048 opP
->error
= "Invalid register";
1055 opP
->con1
= add_exp (str
- 1, strend
);
1066 i
= m68k_reg_parse (&str
);
1067 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
)
1069 /* Can't indirect off non address regs */
1070 opP
->error
= "Invalid indirect register";
1081 /* "-(An)" Register Indirect with Predecrement */
1085 opP
->error
= "Junk after indirect";
1088 opP
->error
= "Bad indirect syntax";
1092 opP
->con1
= add_exp (str
- 2, strend
);
1095 /* if '-' but not "-(', do nothing */
1098 /* whether *str=='-' or not */
1100 /* "EXP2" or "EXP2(REG..." */
1103 if (stmp
= index (str
, '('))
1107 opP
->con1
= add_exp (str
, stmp
- 1);
1109 i
= m68k_reg_parse (&str
);
1110 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
1111 && i
!= ZPC
&& i
!= FAIL
)
1113 /* Can't indirect off non address regs */
1114 opP
->error
= "Invalid indirect register";
1122 /* "d(An)" Register Indirect w Displacement */
1129 i
= try_moto_index (&str
, opP
);
1132 /* "d(An,Rn)" Register Indirect with Index */
1138 opP
->error
= "Bad indirect syntax";
1145 opP
->con1
= add_exp (ostr
, strend
);
1151 /* "EXP2" Absolute */
1154 if (strend
[-1] == '.' || strend
[-1] == ':')
1156 /* mode ==foo.[wl] */
1169 opP
->con1
= add_exp (str
, strend
);
1174 #else /* defined (MIT_SYNTAX_ONLY) */
1176 opP
->con1
= add_exp (str
, strend
);
1178 #endif /* defined (MIT_SYNTAX_ONLY) */
1183 /* Can't indirect off non address regs, but Dx@ is OK for cas2 */
1184 if ((i
< ADDR
+ 0 || i
> ADDR
+ 7) && i
!= PC
&& i
!= ZPC
&& i
!= FAIL
1185 && (str
[1] != '\0' || i
< DATA
+ 0 || i
> DATA
+ 7))
1187 opP
->error
= "Invalid indirect register";
1196 if (i
< DATA
+ 0 || i
> DATA
+ 7)
1211 opP
->error
= "Junk after indirect";
1214 /* Some kind of indexing involved. Lets find out how bad it is */
1215 i
= try_index (&str
, opP
);
1216 /* Didn't start with an index reg, maybe its offset or offset,reg */
1227 opP
->error
= "Missing )";
1260 opP
->error
="Specified size isn't :w or :l";
1263 opP
->con1
=add_exp(beg_str
,str
-4);
1264 opP
->con1
->e_siz
=siz
;
1268 opP
->con1
= add_exp (beg_str
, str
- 2);
1269 /* Should be offset,reg */
1272 i
= try_index (&str
, opP
);
1275 opP
->error
= "Malformed index reg";
1280 /* We've now got offset) offset,reg) or reg) */
1284 /* Th-the-thats all folks */
1285 if (opP
->reg
== FAIL
)
1286 opP
->mode
= AINDX
; /* Other form of indirect */
1287 else if (opP
->ireg
== FAIL
)
1293 /* Next thing had better be another @ */
1308 if ((current_architecture
& m68020up
) == 0)
1311 } /* if target is not a '20 or better */
1314 if (opP
->ireg
!= FAIL
)
1318 i
= try_index (&str
, opP
);
1321 opP
->error
= "Two index registers! not allowed!";
1327 i
= try_index (&str
, opP
);
1342 opP
->error
= "Missing )";
1357 opP
->con2
= add_exp (beg_str
, str
- 2);
1361 if (opP
->ireg
!= FAIL
)
1363 opP
->error
= "Can't have two index regs";
1367 i
= try_index (&str
, opP
);
1371 opP
->error
= "malformed index reg";
1377 else if (opP
->ireg
!= FAIL
)
1393 opP
->error
= "Junk after indirect";
1397 } /* m68k_ip_op() */
1400 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
1403 tc_coff_fix2rtype (fixP
)
1406 return (fixP
->fx_pcrel
?
1407 (fixP
->fx_size
== 1 ? R_PCRBYTE
:
1408 fixP
->fx_size
== 2 ? R_PCRWORD
:
1410 (fixP
->fx_size
== 1 ? R_RELBYTE
:
1411 fixP
->fx_size
== 2 ? R_RELWORD
:
1419 #ifdef BFD_ASSEMBLER
1422 tc_gen_reloc (section
, fixp
)
1427 bfd_reloc_code_real_type code
;
1429 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1430 switch (F (fixp
->fx_size
, fixp
->fx_pcrel
))
1432 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1433 MAP (1, 0, BFD_RELOC_8
);
1434 MAP (2, 0, BFD_RELOC_16
);
1435 MAP (4, 0, BFD_RELOC_32
);
1436 MAP (1, 1, BFD_RELOC_8_PCREL
);
1437 MAP (2, 1, BFD_RELOC_16_PCREL
);
1438 MAP (4, 1, BFD_RELOC_32_PCREL
);
1443 reloc
= (arelent
*) bfd_alloc_by_size_t (stdoutput
, sizeof (arelent
));
1444 assert (reloc
!= 0);
1445 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
1446 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
1448 reloc
->addend
= fixp
->fx_addnumber
;
1452 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
1453 assert (reloc
->howto
!= 0);
1458 #endif /* BFD_ASSEMBLER */
1460 #ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */
1464 struct m68k_op thark
;
1470 memset (&thark
, '\0', sizeof (thark
));
1471 if (!m68k_ip_op (buf
, &thark
))
1474 printf ("op1 error %s in %s\n", thark
.error
, buf
);
1475 printf ("mode %d, reg %d, ", thark
.mode
, thark
.reg
);
1477 printf ("Constant: '%.*s',", 1 + thark
.e_const
- thark
.b_const
, thark
.b_const
);
1478 printf ("ireg %d, isiz %d, imul %d ", thark
.ireg
, thark
.isiz
, thark
.imul
);
1480 printf ("Iadd: '%.*s'", 1 + thark
.e_iadd
- thark
.b_iadd
, thark
.b_iadd
);
1489 /* Handle of the OPCODE hash table. NULL means any use before
1490 m68k_ip_begin() will crash. */
1491 static struct hash_control
*op_hash
;
1497 * This converts a string into a 68k instruction.
1498 * The string must be a bare single instruction in sun format
1499 * with RMS-style 68020 indirects
1502 * It provides some error messages: at most one fatal error message (which
1503 * stops the scan) and at most one warning message for each operand.
1504 * The 68k instruction is returned in exploded form, since we have no
1505 * knowledge of how you parse (or evaluate) your expressions.
1506 * We do however strip off and decode addressing modes and operation
1509 * This function's value is a string. If it is not "" then an internal
1510 * logic error was found: read this code to assign meaning to the string.
1511 * No argument string should generate such an error string:
1512 * it means a bug in our code, not in the user's text.
1514 * You MUST have called m68k_ip_begin() once and m86_ip_end() never before using
1518 /* JF this function no longer returns a useful value. Sorry */
1524 register struct m68k_op
*opP
;
1525 register struct m68k_incant
*opcode
;
1527 register int tmpreg
= 0, baseo
= 0, outro
= 0, nextword
;
1528 char *pdot
, *pdotmove
;
1533 char *crack_operand ();
1534 LITTLENUM_TYPE words
[6];
1535 LITTLENUM_TYPE
*wordp
;
1536 unsigned long ok_arch
= 0;
1538 if (*instring
== ' ')
1539 instring
++; /* skip leading whitespace */
1541 /* Scan up to end of operation-code, which MUST end in end-of-string
1542 or exactly 1 space. */
1544 for (p
= instring
; *p
!= '\0'; p
++)
1554 the_ins
.error
= "No operator";
1555 the_ins
.opcode
[0] = NULL
;
1556 /* the_ins.numo=1; */
1560 /* p now points to the end of the opcode name, probably whitespace.
1561 make sure the name is null terminated by clobbering the whitespace,
1562 look it up in the hash table, then fix it back.
1563 Remove a dot, first, since the opcode tables have none. */
1566 for (pdotmove
= pdot
; pdotmove
< p
; pdotmove
++)
1567 *pdotmove
= pdotmove
[1];
1573 opcode
= (struct m68k_incant
*) hash_find (op_hash
, instring
);
1578 for (pdotmove
= p
; pdotmove
> pdot
; pdotmove
--)
1579 *pdotmove
= pdotmove
[-1];
1586 the_ins
.error
= "Unknown operator";
1587 the_ins
.opcode
[0] = NULL
;
1588 /* the_ins.numo=1; */
1592 /* found a legitimate opcode, start matching operands */
1597 if (opcode
->m_operands
== 0)
1599 char *old
= input_line_pointer
;
1601 input_line_pointer
= p
;
1602 /* Ahh - it's a motorola style psuedo op */
1603 mote_pseudo_table
[opcode
->m_opnum
].poc_handler
1604 (mote_pseudo_table
[opcode
->m_opnum
].poc_val
);
1605 input_line_pointer
= old
;
1611 for (opP
= &the_ins
.operands
[0]; *p
; opP
++)
1614 p
= crack_operand (p
, opP
);
1618 the_ins
.error
= opP
->error
;
1623 opsfound
= opP
- &the_ins
.operands
[0];
1625 /* This ugly hack is to support the floating pt opcodes in their standard form */
1626 /* Essentially, we fake a first enty of type COP#1 */
1627 if (opcode
->m_operands
[0] == 'I')
1631 for (n
= opsfound
; n
> 0; --n
)
1632 the_ins
.operands
[n
] = the_ins
.operands
[n
- 1];
1634 memset ((char *) (&the_ins
.operands
[0]), '\0', sizeof (the_ins
.operands
[0]));
1635 the_ins
.operands
[0].mode
= MSCR
;
1636 the_ins
.operands
[0].reg
= COPNUM
; /* COP #1 */
1640 /* We've got the operands. Find an opcode that'll accept them */
1643 /* If we didn't get the right number of ops, or we have no
1644 common model with this pattern then reject this pattern. */
1646 if (opsfound
!= opcode
->m_opnum
1647 || ((opcode
->m_arch
& current_architecture
) == 0))
1650 ok_arch
|= opcode
->m_arch
;
1654 for (s
= opcode
->m_operands
, opP
= &the_ins
.operands
[0]; *s
&& !losing
; s
+= 2, opP
++)
1656 /* Warning: this switch is huge! */
1657 /* I've tried to organize the cases into this order:
1658 non-alpha first, then alpha by letter. Lower-case
1659 goes directly before uppercase counterpart. */
1660 /* Code with multiple case ...: gets sorted by the lowest
1661 case ... it belongs to. I hope this makes sense. */
1665 if (opP
->mode
== MSCR
|| opP
->mode
== IMMED
1666 || opP
->mode
== DREG
|| opP
->mode
== AREG
1667 || opP
->mode
== AINC
|| opP
->mode
== ADEC
1668 || opP
->mode
== REGLST
)
1687 if (opP
->mode
!= IMMED
)
1693 t
= get_num (opP
->con1
, 80);
1694 if (s
[1] == 'b' && !isbyte (t
))
1696 else if (s
[1] == 'w' && !isword (t
))
1703 if (opP
->mode
!= IMMED
)
1708 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1709 opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1714 if (opP
->mode
== MSCR
|| opP
->reg
== PC
||
1715 opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1721 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1722 opP
->mode
== AREG
|| opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
||
1723 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== REGLST
)
1728 if (opP
->mode
== MSCR
|| opP
->mode
== REGLST
)
1733 if (opP
->mode
!= AINC
)
1738 if (opP
->mode
!= ADEC
)
1743 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1744 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== IMMED
|| opP
->mode
== REGLST
)
1749 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
|| opP
->mode
== REGLST
)
1754 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1755 opP
->mode
== AINC
|| opP
->mode
== ADEC
|| opP
->mode
== IMMED
|| opP
->reg
== PC
||
1756 opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1761 if (opP
->mode
== MSCR
|| opP
->mode
== AREG
||
1762 opP
->mode
== IMMED
|| opP
->mode
== REGLST
)
1766 case '~': /* For now! (JF FOO is this right?) */
1767 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1768 opP
->mode
== AREG
|| opP
->mode
== IMMED
|| opP
->reg
== PC
|| opP
->reg
== ZPC
|| opP
->mode
== REGLST
)
1773 if (opP
->mode
!= MSCR
|| (opP
->reg
!= TT0
&& opP
->reg
!= TT1
))
1778 if (opP
->mode
!= AREG
)
1782 if (opP
->mode
!= AINDR
)
1785 } /* if not address register indirect */
1788 if (opP
->mode
!= ABSL
|| (flagseen
['S'] && instring
[0] == 'j'
1789 && instring
[1] == 'b'
1790 && instring
[2] == 's'
1791 && instring
[3] == 'r'))
1796 if (opP
->mode
!= MSCR
|| opP
->reg
!= CCR
)
1800 case 'd': /* FOO This mode is a KLUDGE!! */
1801 if (opP
->mode
!= AOFF
&& (opP
->mode
!= ABSL
||
1802 opP
->con1
->e_beg
[0] != '(' || opP
->con1
->e_end
[0] != ')'))
1807 if (opP
->mode
!= DREG
)
1812 if (opP
->mode
!= MSCR
|| opP
->reg
< (FPREG
+ 0) || opP
->reg
> (FPREG
+ 7))
1817 if (opP
->mode
!= MSCR
|| opP
->reg
< COPNUM
||
1818 opP
->reg
>= COPNUM
+ 7)
1823 if (opP
->mode
!= MSCR
1826 || cpu_of_arch (current_architecture
) < m68010
/* before 68010 had none */
1827 || (cpu_of_arch (current_architecture
) < m68020
1831 && opP
->reg
!= VBR
) /* 68010's had only these */
1832 || (cpu_of_arch (current_architecture
) < m68040
1840 && opP
->reg
!= ISP
) /* 680[23]0's have only these */
1841 || (cpu_of_arch (current_architecture
) == m68040
/* 68040 has all but this */
1842 && opP
->reg
== CAAR
))
1845 } /* doesn't cut it */
1849 if (opP
->mode
!= IMMED
)
1855 if (opP
->mode
== DREG
|| opP
->mode
== AREG
|| opP
->mode
== FPREG
)
1862 opP
->reg
= 1 << (opP
->reg
- DATA
);
1865 else if (opP
->mode
!= REGLST
)
1869 else if (s
[1] == '8' && opP
->reg
& 0x0FFffFF)
1871 else if (s
[1] == '3' && opP
->reg
& 0x7000000)
1876 if (opP
->mode
!= IMMED
)
1882 t
= get_num (opP
->con1
, 0);
1884 || isvar (opP
->con1
)
1885 || seg (opP
->con1
) != absolute_section
)
1891 if (opP
->mode
!= DREG
&& opP
->mode
!= IMMED
)
1896 if (opP
->mode
!= IMMED
)
1902 t
= get_num (opP
->con1
, 80);
1903 if (t
< 1 || t
> 8 || isvar (opP
->con1
))
1909 if (opP
->mode
!= DREG
&& opP
->mode
!= AREG
)
1914 if (opP
->mode
!= AINDR
&& opP
->mode
!= DINDR
)
1919 if (opP
->mode
!= MSCR
|| !(opP
->reg
== FPI
|| opP
->reg
== FPS
|| opP
->reg
== FPC
))
1924 if (opP
->mode
!= MSCR
|| opP
->reg
!= SR
)
1929 if (opP
->mode
!= IMMED
)
1933 long t
= get_num (opP
->con1
, 80);
1934 if (t
< 0 || t
> 7 || isvar (opP
->con1
))
1940 if (opP
->mode
!= MSCR
|| opP
->reg
!= USP
)
1944 /* JF these are out of order. We could put them
1945 in order if we were willing to put up with
1946 bunches of #ifdef m68851s in the code.
1948 Don't forget that you need these operands
1949 to use 68030 MMU instructions. */
1951 /* Memory addressing mode used by pflushr */
1953 if (opP
->mode
== MSCR
|| opP
->mode
== DREG
||
1954 opP
->mode
== AREG
|| opP
->mode
== REGLST
)
1959 if (opP
->mode
!= MSCR
|| (opP
->reg
!= SFC
&& opP
->reg
!= DFC
))
1964 if (opP
->mode
!= MSCR
1965 || (opP
->reg
!= TC
&& opP
->reg
!= CAL
1966 && opP
->reg
!= VAL
&& opP
->reg
!= SCC
&& opP
->reg
!= AC
))
1971 if (opP
->reg
!= VAL
)
1976 if (opP
->mode
!= MSCR
1977 || (opP
->reg
!= DRP
&& opP
->reg
!= SRP
1978 && opP
->reg
!= CRP
))
1983 if (opP
->mode
!= MSCR
||
1984 (!(opP
->reg
>= BAD
&& opP
->reg
<= BAD
+ 7) &&
1985 !(opP
->reg
>= BAC
&& opP
->reg
<= BAC
+ 7)))
1990 if (opP
->reg
!= PSR
)
1995 if (opP
->reg
!= PCSR
)
2006 } /* not a cache specifier. */
2010 if (opP
->mode
!= ABSL
)
2013 } /* not absolute */
2017 as_fatal ("Internal error: Operand mode %c unknown in line %d of file \"%s\"",
2018 *s
, __LINE__
, __FILE__
);
2019 } /* switch on type of operand */
2023 } /* for each operand */
2024 } /* if immediately wrong */
2031 opcode
= opcode
->m_next
;
2036 && !(ok_arch
& current_architecture
))
2040 strcpy (buf
, "invalid instruction for this architecture; needs ");
2041 cp
= buf
+ strlen (buf
);
2045 strcpy (cp
, "fpu (68040 or 68881/68882)");
2048 strcpy (cp
, "mmu (68030 or 68851)");
2051 strcpy (cp
, "68020 or higher");
2054 strcpy (cp
, "68000 or higher");
2057 strcpy (cp
, "68010 or higher");
2061 int got_one
= 0, idx
;
2078 for (idx
= 0; idx
< sizeof (archs
) / sizeof (archs
[0]); idx
++)
2080 if (archs
[idx
].arch
& ok_arch
)
2084 strcpy (cp
, " or ");
2088 strcpy (cp
, archs
[idx
].name
);
2100 the_ins
.error
= "operands mismatch";
2102 } /* Fell off the end */
2107 /* now assemble it */
2109 the_ins
.args
= opcode
->m_operands
;
2110 the_ins
.numargs
= opcode
->m_opnum
;
2111 the_ins
.numo
= opcode
->m_codenum
;
2112 the_ins
.opcode
[0] = getone (opcode
);
2113 the_ins
.opcode
[1] = gettwo (opcode
);
2115 for (s
= the_ins
.args
, opP
= &the_ins
.operands
[0]; *s
; s
+= 2, opP
++)
2117 /* This switch is a doozy.
2118 Watch the first step; its a big one! */
2139 tmpreg
= 0x3c; /* 7.4 */
2140 if (strchr ("bwl", s
[1]))
2141 nextword
= get_num (opP
->con1
, 80);
2143 nextword
= get_num (opP
->con1
, 0);
2144 if (isvar (opP
->con1
))
2145 add_fix (s
[1], opP
->con1
, 0);
2149 if (!isbyte (nextword
))
2150 opP
->error
= "operand out of range";
2155 if (!isword (nextword
))
2156 opP
->error
= "operand out of range";
2161 addword (nextword
>> 16);
2183 as_fatal ("Internal error: Can't decode %c%c in line %s of file \"%s\"",
2184 *s
, s
[1], __LINE__
, __FILE__
);
2189 /* We gotta put out some float */
2191 if (seg (opP
->con1
) != SEG_BIG
)
2193 int_to_gen (nextword
);
2194 gen_to_words (words
, baseo
, (long int) outro
);
2195 for (wordp
= words
; baseo
--; wordp
++)
2200 if (seg (opP
->con1
) != big_section
)
2205 if (offs (opP
->con1
) > 0)
2207 if (offs (opP
->con1
) > baseo
)
2209 as_warn ("Bignum too big for %c format; truncated", s
[1]);
2210 offs (opP
->con1
) = baseo
;
2212 baseo
-= offs (opP
->con1
);
2213 for (wordp
= generic_bignum
+ offs (opP
->con1
) - 1; offs (opP
->con1
)--; --wordp
)
2219 gen_to_words (words
, baseo
, (long) outro
);
2220 for (wordp
= words
; baseo
--; wordp
++)
2224 tmpreg
= opP
->reg
- DATA
; /* 0.dreg */
2227 tmpreg
= 0x08 + opP
->reg
- ADDR
; /* 1.areg */
2230 tmpreg
= 0x10 + opP
->reg
- ADDR
; /* 2.areg */
2233 tmpreg
= 0x20 + opP
->reg
- ADDR
; /* 4.areg */
2236 tmpreg
= 0x18 + opP
->reg
- ADDR
; /* 3.areg */
2240 nextword
= get_num (opP
->con1
, 80);
2241 /* Force into index mode. Hope this works */
2243 /* We do the first bit for 32-bit displacements, and the
2244 second bit for 16 bit ones. It is possible that we
2245 should make the default be WORD instead of LONG, but
2246 I think that'd break GCC, so we put up with a little
2247 inefficiency for the sake of working output. */
2249 if (!issword (nextword
)
2250 || (isvar (opP
->con1
)
2251 && ((opP
->con1
->e_siz
== 0
2252 && flagseen
['l'] == 0)
2253 || opP
->con1
->e_siz
== 3)))
2257 tmpreg
= 0x3B; /* 7.3 */
2259 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2260 if (isvar (opP
->con1
))
2264 add_frag (adds (opP
->con1
),
2265 offs (opP
->con1
) + 2,
2266 TAB (PCLEA
, SZ_UNDEF
));
2272 add_fix ('l', opP
->con1
, 0);
2277 addword (nextword
>> 16);
2282 tmpreg
= 0x3A; /* 7.2 */
2284 tmpreg
= 0x28 + opP
->reg
- ADDR
; /* 5.areg */
2286 if (isvar (opP
->con1
))
2290 add_fix ('w', opP
->con1
, 1);
2293 add_fix ('w', opP
->con1
, 0);
2302 know (current_architecture
& m68020up
);
2303 /* intentional fall-through */
2306 baseo
= get_num (opP
->con1
, 80);
2307 outro
= get_num (opP
->con2
, 80);
2308 /* Figure out the `addressing mode'.
2309 Also turn on the BASE_DISABLE bit, if needed. */
2310 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2312 tmpreg
= 0x3b;/* 7.3 */
2313 if (opP
->reg
== ZPC
)
2316 else if (opP
->reg
== FAIL
)
2319 tmpreg
= 0x30;/* 6.garbage */
2322 tmpreg
= 0x30 + opP
->reg
- ADDR
; /* 6.areg */
2324 siz1
= (opP
->con1
) ? opP
->con1
->e_siz
: 0;
2325 siz2
= (opP
->con2
) ? opP
->con2
->e_siz
: 0;
2327 /* Index register stuff */
2328 if (opP
->ireg
>= DATA
+ 0 && opP
->ireg
<= ADDR
+ 7)
2330 nextword
|= (opP
->ireg
- DATA
) << 12;
2332 if (opP
->isiz
== 0 || opP
->isiz
== 3)
2348 as_fatal ("failed sanity check.");
2351 GET US OUT OF HERE! */
2353 /* Must be INDEX, with an index
2354 register. Address register
2355 cannot be ZERO-PC, and either
2356 :b was forced, or we know
2358 if (opP
->mode
== AINDX
2363 && !isvar (opP
->con1
))))
2365 nextword
+= baseo
& 0xff;
2367 if (isvar (opP
->con1
))
2368 add_fix ('B', opP
->con1
, 0);
2373 nextword
|= 0x40; /* No index reg */
2375 /* It isn't simple. */
2377 /* If the guy specified a width, we assume that it is
2378 wide enough. Maybe it isn't. If so, we lose. */
2382 if (isvar (opP
->con1
) || !issword (baseo
))
2387 else if (baseo
== 0)
2396 as_warn ("Byte dispacement won't work. Defaulting to :w");
2405 /* Figure out innner displacement stuff */
2406 if (opP
->mode
!= AINDX
)
2411 if (isvar (opP
->con2
) || !issword (outro
))
2416 else if (outro
== 0)
2425 as_warn ("Byte dispacement won't work. Defaulting to :w");
2433 if (opP
->mode
== APODX
)
2435 else if (opP
->mode
== AMIND
)
2440 if (isvar (opP
->con1
))
2442 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2444 opP
->con1
->e_exp
.X_add_number
+= 6;
2445 add_fix (siz1
== 3 ? 'l' : 'w', opP
->con1
, 1);
2448 add_fix (siz1
== 3 ? 'l' : 'w', opP
->con1
, 0);
2451 addword (baseo
>> 16);
2455 if (isvar (opP
->con2
))
2457 if (opP
->reg
== PC
|| opP
->reg
== ZPC
)
2459 opP
->con1
->e_exp
.X_add_number
+= 6;
2460 add_fix (siz2
== 3 ? 'l' : 'w', opP
->con2
, 1);
2463 add_fix (siz2
== 3 ? 'l' : 'w', opP
->con2
, 0);
2466 addword (outro
>> 16);
2473 nextword
= get_num (opP
->con1
, 80);
2474 switch (opP
->con1
->e_siz
)
2477 as_warn ("Unknown size for absolute reference");
2479 if (!isvar (opP
->con1
) && issword (offs (opP
->con1
)))
2481 tmpreg
= 0x38; /* 7.0 */
2485 /* Don't generate pc relative code
2486 on 68010 and 68000 */
2487 if (isvar (opP
->con1
)
2488 && !subs (opP
->con1
)
2489 && seg (opP
->con1
) == text_section
2490 && now_seg
== text_section
2491 && cpu_of_arch (current_architecture
) >= m68020
2493 && !strchr ("~%&$?", s
[0]))
2495 tmpreg
= 0x3A; /* 7.2 */
2496 add_frag (adds (opP
->con1
),
2498 TAB (PCREL
, SZ_UNDEF
));
2501 case 3: /* Fall through into long */
2502 if (isvar (opP
->con1
))
2503 add_fix ('l', opP
->con1
, 0);
2505 tmpreg
= 0x39;/* 7.1 mode */
2506 addword (nextword
>> 16);
2511 if (isvar (opP
->con1
))
2512 add_fix ('w', opP
->con1
, 0);
2514 tmpreg
= 0x38;/* 7.0 mode */
2520 as_bad ("invalid indirect register");
2524 as_bad ("unknown/incorrect operand");
2527 install_gen_operand (s
[1], tmpreg
);
2533 { /* JF: I hate floating point! */
2548 tmpreg
= get_num (opP
->con1
, tmpreg
);
2549 if (isvar (opP
->con1
))
2550 add_fix (s
[1], opP
->con1
, 0);
2553 case 'b': /* Danger: These do no check for
2554 certain types of overflow.
2556 if (!isbyte (tmpreg
))
2557 opP
->error
= "out of range";
2559 if (isvar (opP
->con1
))
2560 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2563 if (!isword (tmpreg
))
2564 opP
->error
= "out of range";
2566 if (isvar (opP
->con1
))
2567 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2570 insop (tmpreg
); /* Because of the way insop works, we put these two out backwards */
2571 insop (tmpreg
>> 16);
2572 if (isvar (opP
->con1
))
2573 the_ins
.reloc
[the_ins
.nrel
- 1].n
= (opcode
->m_codenum
) * 2;
2579 install_operand (s
[1], tmpreg
);
2582 as_fatal ("Internal error: Unknown mode #%c in line %s of file \"%s\"", s
[1], __LINE__
, __FILE__
);
2590 install_operand (s
[1], opP
->reg
- ADDR
);
2594 tmpreg
= get_num (opP
->con1
, 80);
2598 /* Needs no offsetting */
2599 add_fix ('B', opP
->con1
, 1);
2602 /* Offset the displacement to be relative to byte disp location */
2603 opP
->con1
->e_exp
.X_add_number
+= 2;
2604 add_fix ('w', opP
->con1
, 1);
2609 if (cpu_of_arch (current_architecture
) < m68020
) /* 68000 or 010 */
2610 as_warn ("Can't use long branches on 68000/68010");
2611 the_ins
.opcode
[the_ins
.numo
- 1] |= 0xff;
2612 /* Offset the displacement to be relative to byte disp location */
2613 opP
->con1
->e_exp
.X_add_number
+= 4;
2614 add_fix ('l', opP
->con1
, 1);
2619 if (subs (opP
->con1
)) /* We can't relax it */
2622 /* This could either be a symbol, or an
2623 absolute address. No matter, the
2624 frag hacking will finger it out.
2625 Not quite: it can't switch from
2626 BRANCH to BCC68000 for the case
2627 where opnd is absolute (it needs
2628 to use the 68000 hack since no
2629 conditional abs jumps). */
2630 if (((cpu_of_arch (current_architecture
) < m68020
) || (0 == adds (opP
->con1
)))
2631 && (the_ins
.opcode
[0] >= 0x6200)
2632 && (the_ins
.opcode
[0] <= 0x6f00))
2634 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (BCC68000
, SZ_UNDEF
));
2638 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (ABRANCH
, SZ_UNDEF
));
2642 if (isvar (opP
->con1
))
2645 /* check for DBcc instruction */
2646 if ((the_ins
.opcode
[0] & 0xf0f8) == 0x50c8)
2648 /* size varies if patch */
2649 /* needed for long form */
2650 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (DBCC
, SZ_UNDEF
));
2655 opP
->con1
->e_exp
.X_add_number
+= 2;
2656 add_fix ('w', opP
->con1
, 1);
2660 case 'C': /* Fixed size LONG coproc branches */
2661 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2662 /* Offset the displacement to be relative to byte disp location */
2663 /* Coproc branches don't have a byte disp option, but they are
2664 compatible with the ordinary branches, which do... */
2665 opP
->con1
->e_exp
.X_add_number
+= 4;
2666 add_fix ('l', opP
->con1
, 1);
2670 case 'c': /* Var size Coprocesssor branches */
2671 if (subs (opP
->con1
))
2673 add_fix ('l', opP
->con1
, 1);
2674 add_frag ((symbolS
*) 0, (long) 0, TAB (FBRANCH
, LONG
));
2676 else if (adds (opP
->con1
))
2678 add_frag (adds (opP
->con1
), offs (opP
->con1
), TAB (FBRANCH
, SZ_UNDEF
));
2682 /* add_frag((symbolS *)0,offs(opP->con1),TAB(FBRANCH,SHORT)); */
2683 the_ins
.opcode
[the_ins
.numo
- 1] |= 0x40;
2684 add_fix ('l', opP
->con1
, 1);
2690 as_fatal ("Internal error: operand type B%c unknown in line %s of file \"%s\"",
2691 s
[1], __LINE__
, __FILE__
);
2695 case 'C': /* Ignore it */
2698 case 'd': /* JF this is a kludge */
2699 if (opP
->mode
== AOFF
)
2701 install_operand ('s', opP
->reg
- ADDR
);
2707 tmpP
= opP
->con1
->e_end
- 2;
2709 opP
->con1
->e_end
-= 4; /* point to the , */
2710 baseo
= m68k_reg_parse (&tmpP
);
2711 if (baseo
< ADDR
+ 0 || baseo
> ADDR
+ 7)
2713 as_bad ("Unknown address reg, using A0");
2718 install_operand ('s', baseo
);
2720 tmpreg
= get_num (opP
->con1
, 80);
2721 if (!issword (tmpreg
))
2723 as_warn ("Expression out of range, using 0");
2730 install_operand (s
[1], opP
->reg
- DATA
);
2734 install_operand (s
[1], opP
->reg
- FPREG
);
2738 tmpreg
= 1 + opP
->reg
- COPNUM
;
2741 install_operand (s
[1], tmpreg
);
2744 case 'J': /* JF foo */
2797 as_fatal ("failed sanity check.");
2799 install_operand (s
[1], tmpreg
);
2803 tmpreg
= get_num (opP
->con1
, 55);
2804 install_operand (s
[1], tmpreg
& 0x7f);
2811 if (tmpreg
& 0x7FF0000)
2812 as_bad ("Floating point register in register list");
2813 insop (reverse_16_bits (tmpreg
));
2817 if (tmpreg
& 0x700FFFF)
2818 as_bad ("Wrong register in floating-point reglist");
2819 install_operand (s
[1], reverse_8_bits (tmpreg
>> 16));
2827 if (tmpreg
& 0x7FF0000)
2828 as_bad ("Floating point register in register list");
2831 else if (s
[1] == '8')
2833 if (tmpreg
& 0x0FFFFFF)
2834 as_bad ("incorrect register in reglist");
2835 install_operand (s
[1], tmpreg
>> 24);
2839 if (tmpreg
& 0x700FFFF)
2840 as_bad ("wrong register in floating-point reglist");
2842 install_operand (s
[1], tmpreg
>> 16);
2847 install_operand (s
[1], get_num (opP
->con1
, 60));
2851 tmpreg
= (opP
->mode
== DREG
)
2852 ? 0x20 + opP
->reg
- DATA
2853 : (get_num (opP
->con1
, 40) & 0x1F);
2854 install_operand (s
[1], tmpreg
);
2858 tmpreg
= get_num (opP
->con1
, 10);
2861 install_operand (s
[1], tmpreg
);
2866 /* This depends on the fact that ADDR registers are
2867 eight more than their corresponding DATA regs, so
2868 the result will have the ADDR_REG bit set */
2869 install_operand (s
[1], opP
->reg
- DATA
);
2873 if (opP
->reg
== FPI
)
2875 else if (opP
->reg
== FPS
)
2877 else if (opP
->reg
== FPC
)
2880 as_fatal ("failed sanity check.");
2881 install_operand (s
[1], tmpreg
);
2884 case 'S': /* Ignore it */
2888 install_operand (s
[1], get_num (opP
->con1
, 30));
2891 case 'U': /* Ignore it */
2910 as_fatal ("failed sanity check");
2911 } /* switch on cache token */
2912 install_operand (s
[1], tmpreg
);
2915 /* JF: These are out of order, I fear. */
2926 as_fatal ("failed sanity check.");
2928 install_operand (s
[1], tmpreg
);
2950 as_fatal ("failed sanity check.");
2952 install_operand (s
[1], tmpreg
);
2956 if (opP
->reg
== VAL
)
2958 as_fatal ("failed sanity check.");
2974 as_fatal ("failed sanity check.");
2976 install_operand (s
[1], tmpreg
);
2990 tmpreg
= (4 << 10) | ((opP
->reg
- BAD
) << 2);
3001 tmpreg
= (5 << 10) | ((opP
->reg
- BAC
) << 2);
3005 as_fatal ("failed sanity check.");
3007 install_operand (s
[1], tmpreg
);
3010 know (opP
->reg
== PSR
);
3013 know (opP
->reg
== PCSR
);
3026 as_fatal ("failed sanity check");
3028 install_operand (s
[1], tmpreg
);
3031 tmpreg
= get_num (opP
->con1
, 20);
3032 install_operand (s
[1], tmpreg
);
3034 case '_': /* used only for move16 absolute 32-bit address */
3035 tmpreg
= get_num (opP
->con1
, 80);
3036 addword (tmpreg
>> 16);
3037 addword (tmpreg
& 0xFFFF);
3040 as_fatal ("Internal error: Operand type %c unknown in line %d of file \"%s\"",
3041 s
[0], __LINE__
, __FILE__
);
3045 /* By the time whe get here (FINALLY) the_ins contains the complete
3046 instruction, ready to be emitted. . . */
3050 * get_regs := '/' + ?
3051 * | '-' + <register>
3052 * | '-' + <register> + ?
3057 * The idea here must be to scan in a set of registers but I don't
3058 * understand it. Looks awfully sloppy to me but I don't have any doc on
3066 get_regs (i
, str
, opP
)
3068 struct m68k_op
*opP
;
3071 /* 26, 25, 24, 23-16, 15-8, 0-7 */
3072 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */
3073 unsigned long cur_regs
= 0;
3076 #define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\
3077 else if(x==FPS) cur_regs|=(1<<25);\
3078 else if(x==FPC) cur_regs|=(1<<26);\
3079 else cur_regs|=(1<<(x-1)); }
3089 else if (*str
== '-')
3092 reg2
= m68k_reg_parse (&str
);
3093 if (reg2
< DATA
|| reg2
>= FPREG
+ 8 || reg1
== FPI
|| reg1
== FPS
|| reg1
== FPC
)
3095 opP
->error
= "unknown register in register list";
3098 while (reg1
<= reg2
)
3106 else if (*str
== '\0')
3113 opP
->error
= "unknow character in register list";
3116 /* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */
3119 reg1
= m68k_reg_parse (&str
);
3120 if ((reg1
< DATA
|| reg1
>= FPREG
+ 8) && !(reg1
== FPI
|| reg1
== FPS
|| reg1
== FPC
))
3122 opP
->error
= "unknown register in register list";
3126 opP
->reg
= cur_regs
;
3131 reverse_16_bits (in
)
3137 static int mask
[16] =
3139 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3140 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3142 for (n
= 0; n
< 16; n
++)
3145 out
|= mask
[15 - n
];
3148 } /* reverse_16_bits() */
3157 static int mask
[8] =
3159 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3162 for (n
= 0; n
< 8; n
++)
3168 } /* reverse_8_bits() */
3171 install_operand (mode
, val
)
3178 the_ins
.opcode
[0] |= val
& 0xFF; /* JF FF is for M kludge */
3181 the_ins
.opcode
[0] |= val
<< 9;
3184 the_ins
.opcode
[1] |= val
<< 12;
3187 the_ins
.opcode
[1] |= val
<< 6;
3190 the_ins
.opcode
[1] |= val
;
3193 the_ins
.opcode
[2] |= val
<< 12;
3196 the_ins
.opcode
[2] |= val
<< 6;
3199 /* DANGER! This is a hack to force cas2l and cas2w cmds
3200 to be three words long! */
3202 the_ins
.opcode
[2] |= val
;
3205 the_ins
.opcode
[1] |= val
<< 7;
3208 the_ins
.opcode
[1] |= val
<< 10;
3212 the_ins
.opcode
[1] |= val
<< 5;
3217 the_ins
.opcode
[1] |= (val
<< 10) | (val
<< 7);
3220 the_ins
.opcode
[1] |= (val
<< 12) | val
;
3223 the_ins
.opcode
[0] |= val
= 0xff;
3226 the_ins
.opcode
[0] |= val
<< 9;
3229 the_ins
.opcode
[1] |= val
;
3232 the_ins
.opcode
[1] |= val
;
3233 the_ins
.numo
++; /* What a hack */
3236 the_ins
.opcode
[1] |= val
<< 4;
3243 the_ins
.opcode
[0] |= (val
<< 6);
3246 the_ins
.opcode
[1] = (val
>> 16);
3247 the_ins
.opcode
[2] = val
& 0xffff;
3251 as_fatal ("failed sanity check.");
3253 } /* install_operand() */
3256 install_gen_operand (mode
, val
)
3263 the_ins
.opcode
[0] |= val
;
3266 /* This is a kludge!!! */
3267 the_ins
.opcode
[0] |= (val
& 0x07) << 9 | (val
& 0x38) << 3;
3276 the_ins
.opcode
[0] |= val
;
3278 /* more stuff goes here */
3280 as_fatal ("failed sanity check.");
3282 } /* install_gen_operand() */
3285 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3286 * then deal with the bitfield hack.
3290 crack_operand (str
, opP
)
3292 register struct m68k_op
*opP
;
3294 register int parens
;
3296 register char *beg_str
;
3303 for (parens
= 0; *str
&& (parens
> 0 || notend (str
)); str
++)
3307 else if (*str
== ')')
3311 opP
->error
= "Extra )";
3317 if (!*str
&& parens
)
3319 opP
->error
= "Missing )";
3324 if (m68k_ip_op (beg_str
, opP
) == FAIL
)
3331 c
= *++str
; /* JF bitfield hack */
3336 as_bad ("Missing operand");
3341 /* See the comment up above where the #define notend(... is */
3348 if (*s
== '{' || *s
== '}')
3352 /* This kludge here is for the division cmd, which is a kludge */
3353 if (index ("aAdD#", s
[1]))
3360 /* This is the guts of the machine-dependent assembler. STR points to a
3361 machine dependent instruction. This function is supposed to emit
3362 the frags/bytes it assembles to.
3366 insert_reg (regname
, regnum
)
3374 #ifdef REGISTER_PREFIX
3375 buf
[0] = REGISTER_PREFIX
;
3376 strcpy (buf
+ 1, regname
);
3380 symbol_table_insert (s
= symbol_new (regname
, reg_section
, regnum
, &zero_address_frag
));
3382 verify_symbol_chain_2 (s
);
3384 for (i
= 0; regname
[i
]; i
++)
3385 buf
[i
] = islower (regname
[i
]) ? toupper (regname
[i
]) : regname
[i
];
3388 symbol_table_insert (s
= symbol_new (buf
, reg_section
, regnum
, &zero_address_frag
));
3389 verify_symbol_chain_2 (s
);
3398 static CONST
struct init_entry init_table
[] =
3500 /* 68ec030 versions of same */
3503 /* 68ec030 access control unit, identical to 030 MMU status reg */
3515 for (i
= 0; init_table
[i
].name
; i
++)
3516 insert_reg (init_table
[i
].name
, init_table
[i
].number
);
3519 static int no_68851
, no_68881
;
3530 int shorts_this_frag
;
3531 static int done_first_time
;
3533 if (!done_first_time
)
3535 done_first_time
= 1;
3537 if (cpu_of_arch (current_architecture
) == 0)
3541 if (strcmp (TARGET_CPU
, "m68000") == 0
3542 || strcmp (TARGET_CPU
, "m68302") == 0)
3544 else if (strcmp (TARGET_CPU
, "m68010") == 0)
3546 else if (strcmp (TARGET_CPU
, "m68020") == 0
3547 || strcmp (TARGET_CPU
, "m68k") == 0)
3549 else if (strcmp (TARGET_CPU
, "m68030") == 0)
3551 else if (strcmp (TARGET_CPU
, "m68040") == 0)
3553 else if (strcmp (TARGET_CPU
, "cpu32") == 0
3554 || strcmp (TARGET_CPU
, "m68331") == 0
3555 || strcmp (TARGET_CPU
, "m68332") == 0
3556 || strcmp (TARGET_CPU
, "m68333") == 0
3557 || strcmp (TARGET_CPU
, "m68340") == 0)
3562 current_architecture
|= cpu_type
;
3564 #if 0 /* Could be doing emulation. */
3565 if (current_architecture
& m68881
)
3567 if (current_architecture
& m68000
)
3568 as_bad ("incompatible processors 68000 and 68881/2 specified");
3569 if (current_architecture
& m68010
)
3570 as_bad ("incompatible processors 68010 and 68881/2 specified");
3571 if (current_architecture
& m68040
)
3572 as_bad ("incompatible processors 68040 and 68881/2 specified");
3575 /* What other incompatibilities could we check for? */
3577 /* Toss in some default assumptions about coprocessors. */
3579 && (cpu_of_arch (current_architecture
)
3580 /* Can CPU32 have a 68881 coprocessor?? */
3581 & (m68020
| m68030
| cpu32
)))
3583 current_architecture
|= m68881
;
3586 && (cpu_of_arch (current_architecture
) & m68020up
) != 0
3587 && cpu_of_arch (current_architecture
) != m68040
)
3589 current_architecture
|= m68851
;
3591 if (no_68881
&& (current_architecture
& m68881
))
3592 as_bad ("options for 68881 and no-68881 both given");
3593 if (no_68851
&& (current_architecture
& m68851
))
3594 as_bad ("options for 68851 and no-68851 both given");
3595 done_first_time
= 1;
3598 memset ((char *) (&the_ins
), '\0', sizeof (the_ins
));
3603 for (n
= the_ins
.numargs
; n
; --n
)
3604 if (the_ins
.operands
[n
].error
)
3606 er
= the_ins
.operands
[n
].error
;
3612 as_bad ("%s -- statement `%s' ignored", er
, str
);
3616 if (the_ins
.nfrag
== 0)
3618 /* No frag hacking involved; just put it out */
3619 toP
= frag_more (2 * the_ins
.numo
);
3620 fromP
= &the_ins
.opcode
[0];
3621 for (m
= the_ins
.numo
; m
; --m
)
3623 md_number_to_chars (toP
, (long) (*fromP
), 2);
3627 /* put out symbol-dependent info */
3628 for (m
= 0; m
< the_ins
.nrel
; m
++)
3630 switch (the_ins
.reloc
[m
].wid
)
3648 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3649 the_ins
.reloc
[m
].wid
);
3653 (toP
- frag_now
->fr_literal
) - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
,
3655 the_ins
.reloc
[m
].add
,
3656 the_ins
.reloc
[m
].sub
,
3657 the_ins
.reloc
[m
].off
,
3658 the_ins
.reloc
[m
].pcrel
,
3664 /* There's some frag hacking */
3665 for (n
= 0, fromP
= &the_ins
.opcode
[0]; n
< the_ins
.nfrag
; n
++)
3670 wid
= 2 * the_ins
.fragb
[n
].fragoff
;
3672 wid
= 2 * (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3673 toP
= frag_more (wid
);
3675 shorts_this_frag
= 0;
3676 for (m
= wid
/ 2; m
; --m
)
3678 md_number_to_chars (toP
, (long) (*fromP
), 2);
3683 for (m
= 0; m
< the_ins
.nrel
; m
++)
3685 if ((the_ins
.reloc
[m
].n
) >= 2 * shorts_this_frag
)
3687 the_ins
.reloc
[m
].n
-= 2 * shorts_this_frag
;
3690 wid
= the_ins
.reloc
[m
].wid
;
3693 the_ins
.reloc
[m
].wid
= 0;
3694 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3697 (toP
- frag_now
->fr_literal
) - the_ins
.numo
* 2 + the_ins
.reloc
[m
].n
,
3699 the_ins
.reloc
[m
].add
,
3700 the_ins
.reloc
[m
].sub
,
3701 the_ins
.reloc
[m
].off
,
3702 the_ins
.reloc
[m
].pcrel
,
3705 (void) frag_var (rs_machine_dependent
, 10, 0,
3706 (relax_substateT
) (the_ins
.fragb
[n
].fragty
),
3707 the_ins
.fragb
[n
].fadd
, the_ins
.fragb
[n
].foff
, to_beg_P
);
3709 n
= (the_ins
.numo
- the_ins
.fragb
[n
- 1].fragoff
);
3710 shorts_this_frag
= 0;
3713 toP
= frag_more (n
* sizeof (short));
3716 md_number_to_chars (toP
, (long) (*fromP
), 2);
3722 for (m
= 0; m
< the_ins
.nrel
; m
++)
3726 wid
= the_ins
.reloc
[m
].wid
;
3729 the_ins
.reloc
[m
].wid
= 0;
3730 wid
= (wid
== 'b') ? 1 : (wid
== 'w') ? 2 : (wid
== 'l') ? 4 : 4000;
3733 (the_ins
.reloc
[m
].n
+ toP
- frag_now
->fr_literal
) - shorts_this_frag
* 2,
3735 the_ins
.reloc
[m
].add
,
3736 the_ins
.reloc
[m
].sub
,
3737 the_ins
.reloc
[m
].off
,
3738 the_ins
.reloc
[m
].pcrel
,
3743 /* See BREAK_UP_BIG_DECL definition, above. */
3744 static struct m68k_opcode
*
3748 #ifdef DO_BREAK_UP_BIG_DECL
3749 int lim1
= sizeof (m68k_opcodes
) / sizeof (m68k_opcodes
[0]);
3751 return m68k_opcodes_2
+ (i
- lim1
);
3753 return m68k_opcodes
+ i
;
3760 * md_begin -- set up hash tables with 68000 instructions.
3761 * similar to what the vax assembler does. ---phr
3763 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3764 a copy of it at runtime, adding in the information we want but isn't
3765 there. I think it'd be better to have an awk script hack the table
3766 at compile time. Or even just xstr the table and use it as-is. But
3767 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3770 register CONST
struct m68k_opcode
*ins
;
3771 register struct m68k_incant
*hack
, *slak
;
3772 register char *retval
= 0; /* empty string, or error msg text */
3773 register unsigned int i
;
3776 if ((op_hash
= hash_new ()) == NULL
)
3777 as_fatal ("Virtual memory exhausted");
3779 obstack_begin (&robyn
, 4000);
3780 for (i
= 0; i
< numopcodes
; i
++)
3782 hack
= slak
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3785 ins
= opcode_ptr (i
);
3786 /* We *could* ignore insns that don't match our arch here
3787 but just leaving them out of the hash. */
3788 slak
->m_operands
= ins
->args
;
3789 slak
->m_opnum
= strlen (slak
->m_operands
) / 2;
3790 slak
->m_arch
= ins
->arch
;
3791 slak
->m_opcode
= ins
->opcode
;
3792 /* This is kludgey */
3793 slak
->m_codenum
= ((ins
->match
) & 0xffffL
) ? 2 : 1;
3794 if (i
+ 1 != numopcodes
3795 && !strcmp (ins
->name
, opcode_ptr (i
+ 1)->name
))
3797 slak
->m_next
= (struct m68k_incant
*) obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3802 slak
= slak
->m_next
;
3806 retval
= hash_insert (op_hash
, ins
->name
, (char *) hack
);
3807 /* Didn't his mommy tell him about null pointers? */
3808 if (retval
&& *retval
)
3809 as_bad ("Internal Error: Can't hash %s: %s", ins
->name
, retval
);
3812 for (i
= 0; i
< sizeof (mklower_table
); i
++)
3813 mklower_table
[i
] = (isupper (c
= (char) i
)) ? tolower (c
) : c
;
3815 for (i
= 0; i
< sizeof (notend_table
); i
++)
3817 notend_table
[i
] = 0;
3818 alt_notend_table
[i
] = 0;
3820 notend_table
[','] = 1;
3821 notend_table
['{'] = 1;
3822 notend_table
['}'] = 1;
3823 alt_notend_table
['a'] = 1;
3824 alt_notend_table
['A'] = 1;
3825 alt_notend_table
['d'] = 1;
3826 alt_notend_table
['D'] = 1;
3827 alt_notend_table
['#'] = 1;
3828 alt_notend_table
['f'] = 1;
3829 alt_notend_table
['F'] = 1;
3830 #ifdef REGISTER_PREFIX
3831 alt_notend_table
[REGISTER_PREFIX
] = 1;
3833 #ifdef OPTIONAL_REGISTER_PREFIX
3834 alt_notend_table
[OPTIONAL_REGISTER_PREFIX
] = 1;
3837 #ifndef MIT_SYNTAX_ONLY
3838 /* Insert pseudo ops, these have to go into the opcode table since
3839 gas expects pseudo ops to start with a dot */
3842 while (mote_pseudo_table
[n
].poc_name
)
3844 hack
= (struct m68k_incant
*)
3845 obstack_alloc (&robyn
, sizeof (struct m68k_incant
));
3846 hash_insert (op_hash
,
3847 mote_pseudo_table
[n
].poc_name
, (char *) hack
);
3848 hack
->m_operands
= 0;
3859 #define notend(s) ((*s == ',' || *s == '}' || *s == '{' \
3860 || (*s == ':' && strchr("aAdD#", s[1]))) \
3864 /* This funciton is called once, before the assembler exits. It is
3865 supposed to do any final cleanup for this part of the assembler.
3872 /* Equal to MAX_PRECISION in atof-ieee.c */
3873 #define MAX_LITTLENUMS 6
3875 /* Turn a string in input_line_pointer into a floating point constant of type
3876 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
3877 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
3880 md_atof (type
, litP
, sizeP
)
3886 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
3887 LITTLENUM_TYPE
*wordP
;
3919 return "Bad call to MD_ATOF()";
3921 t
= atof_ieee (input_line_pointer
, type
, words
);
3923 input_line_pointer
= t
;
3925 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
3926 for (wordP
= words
; prec
--;)
3928 md_number_to_chars (litP
, (long) (*wordP
++), sizeof (LITTLENUM_TYPE
));
3929 litP
+= sizeof (LITTLENUM_TYPE
);
3934 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
3935 for use in the a.out file, and stores them in the array pointed to by buf.
3936 This knows about the endian-ness of the target machine and does
3937 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
3938 2 (short) and 4 (long) Floating numbers are put out as a series of
3939 LITTLENUMS (shorts, here at least)
3942 md_number_to_chars (buf
, val
, n
)
3953 *buf
++ = (val
>> 8);
3957 *buf
++ = (val
>> 24);
3958 *buf
++ = (val
>> 16);
3959 *buf
++ = (val
>> 8);
3963 as_fatal ("failed sanity check.");
3968 md_apply_fix_2 (fixP
, val
)
3972 unsigned long upper_limit
;
3975 #ifdef IBM_COMPILER_SUX
3976 /* This is unnecessary but it convinces the native rs6000
3977 compiler to generate the code we want. */
3978 char *buf
= fixP
->fx_frag
->fr_literal
;
3979 buf
+= fixP
->fx_where
;
3980 #else /* IBM_COMPILER_SUX */
3981 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
3982 #endif /* IBM_COMPILER_SUX */
3984 switch (fixP
->fx_size
)
3989 lower_limit
= -0x80;
3992 *buf
++ = (val
>> 8);
3994 upper_limit
= 0x7fff;
3995 lower_limit
= -0x8000;
3998 *buf
++ = (val
>> 24);
3999 *buf
++ = (val
>> 16);
4000 *buf
++ = (val
>> 8);
4002 upper_limit
= 0x7fffffff;
4003 lower_limit
= -0x80000000;
4006 BAD_CASE (fixP
->fx_size
);
4009 /* For non-pc-relative values, it's conceivable we might get something
4010 like "0xff" for a byte field. So extend the upper part of the range
4011 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4012 so that we can do any range checking at all. */
4013 if (!fixP
->fx_pcrel
)
4014 upper_limit
= upper_limit
* 2 + 1;
4016 if ((unsigned) val
> upper_limit
&& (val
> 0 || val
< lower_limit
))
4017 as_bad ("value out of range");
4020 #ifdef BFD_ASSEMBLER
4022 md_apply_fix (fixP
, valp
)
4026 md_apply_fix_2 (fixP
, *valp
);
4030 void md_apply_fix (fixP
, val
)
4034 md_apply_fix_2 (fixP
, val
);
4038 /* *fragP has been relaxed to its final size, and now needs to have
4039 the bytes inside it modified to conform to the new size There is UGLY
4043 md_convert_frag_1 (fragP
)
4044 register fragS
*fragP
;
4049 /* Address in object code of the displacement. */
4050 register int object_address
= fragP
->fr_fix
+ fragP
->fr_address
;
4052 #ifdef IBM_COMPILER_SUX
4053 /* This is wrong but it convinces the native rs6000 compiler to
4054 generate the code we want. */
4055 register char *buffer_address
= fragP
->fr_literal
;
4056 buffer_address
+= fragP
->fr_fix
;
4057 #else /* IBM_COMPILER_SUX */
4058 /* Address in gas core of the place to store the displacement. */
4059 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4060 #endif /* IBM_COMPILER_SUX */
4062 /* No longer true: know(fragP->fr_symbol); */
4064 /* The displacement of the address, from current location. */
4065 disp
= fragP
->fr_symbol
? S_GET_VALUE (fragP
->fr_symbol
) : 0;
4066 disp
= (disp
+ fragP
->fr_offset
) - object_address
;
4068 switch (fragP
->fr_subtype
)
4070 case TAB (BCC68000
, BYTE
):
4071 case TAB (ABRANCH
, BYTE
):
4072 know (issbyte (disp
));
4074 as_bad ("short branch with zero offset: use :w");
4075 fragP
->fr_opcode
[1] = disp
;
4078 case TAB (DBCC
, SHORT
):
4079 know (issword (disp
));
4082 case TAB (BCC68000
, SHORT
):
4083 case TAB (ABRANCH
, SHORT
):
4084 know (issword (disp
));
4085 fragP
->fr_opcode
[1] = 0x00;
4088 case TAB (ABRANCH
, LONG
):
4089 if (cpu_of_arch (current_architecture
) < m68020
)
4091 if (fragP
->fr_opcode
[0] == 0x61)
4093 fragP
->fr_opcode
[0] = 0x4E;
4094 fragP
->fr_opcode
[1] = 0xB9; /* JBSR with ABSL LONG offset */
4095 subseg_change (text_section
, 0); /* @@ */
4109 else if (fragP
->fr_opcode
[0] == 0x60)
4111 fragP
->fr_opcode
[0] = 0x4E;
4112 fragP
->fr_opcode
[1] = 0xF9; /* JMP with ABSL LONG offset */
4113 subseg_change (text_section
, 0); /* @@ */
4114 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0,
4121 as_bad ("Long branch offset not supported.");
4126 fragP
->fr_opcode
[1] = 0xff;
4130 case TAB (BCC68000
, LONG
):
4131 /* only Bcc 68000 instructions can come here */
4132 /* change bcc into b!cc/jmp absl long */
4133 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4134 fragP
->fr_opcode
[1] = 0x6;/* branch offset = 6 */
4136 /* JF: these used to be fr_opcode[2,3], but they may be in a
4137 different frag, in which case refering to them is a no-no.
4138 Only fr_opcode[0,1] are guaranteed to work. */
4139 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4140 *buffer_address
++ = 0xf9;
4141 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4142 subseg_change (text_section
, 0);
4143 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
4144 fragP
->fr_offset
, 0,
4149 case TAB (DBCC
, LONG
):
4150 /* only DBcc 68000 instructions can come here */
4151 /* change dbcc into dbcc/jmp absl long */
4152 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4153 *buffer_address
++ = 0x00; /* branch offset = 4 */
4154 *buffer_address
++ = 0x04;
4155 *buffer_address
++ = 0x60; /* put in bra pc+6 */
4156 *buffer_address
++ = 0x06;
4157 *buffer_address
++ = 0x4e; /* put in jmp long (0x4ef9) */
4158 *buffer_address
++ = 0xf9;
4160 fragP
->fr_fix
+= 6; /* account for bra/jmp instructions */
4161 subseg_change (text_section
, 0);
4162 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
4163 fragP
->fr_offset
, 0, NO_RELOC
);
4167 case TAB (FBRANCH
, SHORT
):
4168 know ((fragP
->fr_opcode
[1] & 0x40) == 0);
4171 case TAB (FBRANCH
, LONG
):
4172 fragP
->fr_opcode
[1] |= 0x40; /* Turn on LONG bit */
4175 case TAB (PCREL
, SHORT
):
4178 case TAB (PCREL
, LONG
):
4179 /* The thing to do here is force it to ABSOLUTE LONG, since
4180 PCREL is really trying to shorten an ABSOLUTE address anyway */
4181 /* JF FOO This code has not been tested */
4182 subseg_change (text_section
, 0);
4183 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0, fragP
->fr_offset
,
4185 if ((fragP
->fr_opcode
[1] & 0x3F) != 0x3A)
4186 as_bad ("Internal error (long PC-relative operand) for insn 0x%04lx at 0x%lx",
4187 fragP
->fr_opcode
[0], fragP
->fr_address
);
4188 fragP
->fr_opcode
[1] &= ~0x3F;
4189 fragP
->fr_opcode
[1] |= 0x39; /* Mode 7.1 */
4193 case TAB (PCLEA
, SHORT
):
4194 subseg_change (text_section
, 0);
4195 fix_new (fragP
, (int) (fragP
->fr_fix
), 2, fragP
->fr_symbol
,
4196 (symbolS
*) 0, fragP
->fr_offset
, 1, NO_RELOC
);
4197 fragP
->fr_opcode
[1] &= ~0x3F;
4198 fragP
->fr_opcode
[1] |= 0x3A;
4201 case TAB (PCLEA
, LONG
):
4202 subseg_change (text_section
, 0);
4203 fix_new (fragP
, (int) (fragP
->fr_fix
) + 2, 4, fragP
->fr_symbol
,
4204 (symbolS
*) 0, fragP
->fr_offset
+ 2, 1, NO_RELOC
);
4205 *buffer_address
++ = 0x01;
4206 *buffer_address
++ = 0x70;
4214 md_number_to_chars (buffer_address
, (long) disp
, (int) ext
);
4215 fragP
->fr_fix
+= ext
;
4219 #ifndef BFD_ASSEMBLER
4222 md_convert_frag (headers
, fragP
)
4223 object_headers
*headers
;
4226 md_convert_frag_1 (fragP
);
4232 md_convert_frag (abfd
, sec
, fragP
)
4237 md_convert_frag_1 (fragP
);
4241 /* Force truly undefined symbols to their maximum size, and generally set up
4242 the frag list to be relaxed
4245 md_estimate_size_before_relax (fragP
, segment
)
4246 register fragS
*fragP
;
4250 register char *buffer_address
= fragP
->fr_fix
+ fragP
->fr_literal
;
4252 old_fix
= fragP
->fr_fix
;
4254 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4255 switch (fragP
->fr_subtype
)
4258 case TAB (ABRANCH
, SZ_UNDEF
):
4260 if ((fragP
->fr_symbol
!= NULL
) /* Not absolute */
4261 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4263 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), BYTE
);
4266 else if ((fragP
->fr_symbol
== 0) || (cpu_of_arch (current_architecture
) < m68020
))
4268 /* On 68000, or for absolute value, switch to abs long */
4269 /* FIXME, we should check abs val, pick short or long */
4270 if (fragP
->fr_opcode
[0] == 0x61)
4272 fragP
->fr_opcode
[0] = 0x4E;
4273 fragP
->fr_opcode
[1] = 0xB9; /* JBSR with ABSL LONG offset */
4274 subseg_change (text_section
, 0);
4275 fix_new (fragP
, fragP
->fr_fix
, 4,
4276 fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0, NO_RELOC
);
4280 else if (fragP
->fr_opcode
[0] == 0x60)
4282 fragP
->fr_opcode
[0] = 0x4E;
4283 fragP
->fr_opcode
[1] = 0xF9; /* JMP with ABSL LONG offset */
4284 subseg_change (text_section
, 0);
4285 fix_new (fragP
, fragP
->fr_fix
, 4,
4286 fragP
->fr_symbol
, 0, fragP
->fr_offset
, 0, NO_RELOC
);
4292 as_warn ("Long branch offset to extern symbol not supported.");
4296 { /* Symbol is still undefined. Make it simple */
4297 fix_new (fragP
, (int) (fragP
->fr_fix
), 4, fragP
->fr_symbol
,
4298 (symbolS
*) 0, fragP
->fr_offset
+ 4, 1, NO_RELOC
);
4300 fragP
->fr_opcode
[1] = 0xff;
4306 } /* case TAB(ABRANCH,SZ_UNDEF) */
4308 case TAB (FBRANCH
, SZ_UNDEF
):
4310 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flagseen
['l'])
4312 fragP
->fr_subtype
= TAB (FBRANCH
, SHORT
);
4317 fragP
->fr_subtype
= TAB (FBRANCH
, LONG
);
4321 } /* TAB(FBRANCH,SZ_UNDEF) */
4323 case TAB (PCREL
, SZ_UNDEF
):
4325 if (S_GET_SEGMENT (fragP
->fr_symbol
) == segment
|| flagseen
['l'])
4327 fragP
->fr_subtype
= TAB (PCREL
, SHORT
);
4332 fragP
->fr_subtype
= TAB (PCREL
, LONG
);
4336 } /* TAB(PCREL,SZ_UNDEF) */
4338 case TAB (BCC68000
, SZ_UNDEF
):
4340 if ((fragP
->fr_symbol
!= NULL
)
4341 && S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4343 fragP
->fr_subtype
= TAB (BCC68000
, BYTE
);
4346 /* only Bcc 68000 instructions can come here */
4347 /* change bcc into b!cc/jmp absl long */
4348 fragP
->fr_opcode
[0] ^= 0x01; /* invert bcc */
4351 fragP
->fr_opcode
[1] = 0x04; /* branch offset = 6 */
4352 /* JF: these were fr_opcode[2,3] */
4353 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4354 buffer_address
[1] = 0xf8;
4355 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4356 subseg_change (text_section
, 0);
4357 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, 0,
4358 fragP
->fr_offset
, 0, NO_RELOC
);
4363 fragP
->fr_opcode
[1] = 0x06; /* branch offset = 6 */
4364 /* JF: these were fr_opcode[2,3] */
4365 buffer_address
[0] = 0x4e; /* put in jmp long (0x4ef9) */
4366 buffer_address
[1] = 0xf9;
4367 fragP
->fr_fix
+= 2; /* account for jmp instruction */
4368 subseg_change (text_section
, 0);
4369 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
4370 fragP
->fr_offset
, 0, NO_RELOC
);
4375 } /* case TAB(BCC68000,SZ_UNDEF) */
4377 case TAB (DBCC
, SZ_UNDEF
):
4379 if (fragP
->fr_symbol
!= NULL
&& S_GET_SEGMENT (fragP
->fr_symbol
) == segment
)
4381 fragP
->fr_subtype
= TAB (DBCC
, SHORT
);
4385 /* only DBcc 68000 instructions can come here */
4386 /* change dbcc into dbcc/jmp absl long */
4387 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4388 buffer_address
[0] = 0x00; /* branch offset = 4 */
4389 buffer_address
[1] = 0x04;
4390 buffer_address
[2] = 0x60; /* put in bra pc + ... */
4394 /* JF: these were fr_opcode[5-7] */
4395 buffer_address
[3] = 0x04; /* plus 4 */
4396 buffer_address
[4] = 0x4e; /* Put in Jump Word */
4397 buffer_address
[5] = 0xf8;
4398 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4399 subseg_change (text_section
, 0);
4400 fix_new (fragP
, fragP
->fr_fix
, 2, fragP
->fr_symbol
, 0,
4403 fragP
->fr_offset
, 0, NO_RELOC
);
4408 /* JF: these were fr_opcode[5-7] */
4409 buffer_address
[3] = 0x06; /* Plus 6 */
4410 buffer_address
[4] = 0x4e; /* put in jmp long (0x4ef9) */
4411 buffer_address
[5] = 0xf9;
4412 fragP
->fr_fix
+= 6; /* account for bra/jmp instruction */
4413 subseg_change (text_section
, 0);
4414 fix_new (fragP
, fragP
->fr_fix
, 4, fragP
->fr_symbol
, 0,
4415 fragP
->fr_offset
, 0, NO_RELOC
);
4421 } /* case TAB(DBCC,SZ_UNDEF) */
4423 case TAB (PCLEA
, SZ_UNDEF
):
4425 if ((S_GET_SEGMENT (fragP
->fr_symbol
)) == segment
|| flagseen
['l'])
4427 fragP
->fr_subtype
= TAB (PCLEA
, SHORT
);
4432 fragP
->fr_subtype
= TAB (PCLEA
, LONG
);
4436 } /* TAB(PCLEA,SZ_UNDEF) */
4441 } /* switch on subtype looking for SZ_UNDEF's. */
4443 /* now that SZ_UNDEF are taken care of, check others */
4444 switch (fragP
->fr_subtype
)
4446 case TAB (BCC68000
, BYTE
):
4447 case TAB (ABRANCH
, BYTE
):
4448 /* We can't do a short jump to the next instruction,
4449 so we force word mode. */
4450 if (fragP
->fr_symbol
&& S_GET_VALUE (fragP
->fr_symbol
) == 0 &&
4451 fragP
->fr_symbol
->sy_frag
== fragP
->fr_next
)
4453 fragP
->fr_subtype
= TAB (TABTYPE (fragP
->fr_subtype
), SHORT
);
4460 return fragP
->fr_var
+ fragP
->fr_fix
- old_fix
;
4463 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4464 /* the bit-field entries in the relocation_info struct plays hell
4465 with the byte-order problems of cross-assembly. So as a hack,
4466 I added this mach. dependent ri twiddler. Ugly, but it gets
4468 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4469 are symbolnum, most sig. byte first. Last byte is broken up with
4470 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4471 nibble as nuthin. (on Sun 3 at least) */
4472 /* Translate the internal relocation information into target-specific
4476 md_ri_to_chars (the_bytes
, ri
)
4478 struct reloc_info_generic
*ri
;
4481 md_number_to_chars (the_bytes
, ri
->r_address
, 4);
4482 /* now the fun stuff */
4483 the_bytes
[4] = (ri
->r_symbolnum
>> 16) & 0x0ff;
4484 the_bytes
[5] = (ri
->r_symbolnum
>> 8) & 0x0ff;
4485 the_bytes
[6] = ri
->r_symbolnum
& 0x0ff;
4486 the_bytes
[7] = (((ri
->r_pcrel
<< 7) & 0x80) | ((ri
->r_length
<< 5) & 0x60) |
4487 ((ri
->r_extern
<< 4) & 0x10));
4490 #endif /* comment */
4492 #ifndef BFD_ASSEMBLER
4494 tc_aout_fix_to_chars (where
, fixP
, segment_address_in_file
)
4497 relax_addressT segment_address_in_file
;
4500 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4501 * Out: GNU LD relocation length code: 0, 1, or 2.
4504 static CONST
unsigned char nbytes_r_length
[] =
4508 know (fixP
->fx_addsy
!= NULL
);
4510 md_number_to_chars (where
,
4511 fixP
->fx_frag
->fr_address
+ fixP
->fx_where
- segment_address_in_file
,
4514 r_symbolnum
= (S_IS_DEFINED (fixP
->fx_addsy
)
4515 ? S_GET_TYPE (fixP
->fx_addsy
)
4516 : fixP
->fx_addsy
->sy_number
);
4518 where
[4] = (r_symbolnum
>> 16) & 0x0ff;
4519 where
[5] = (r_symbolnum
>> 8) & 0x0ff;
4520 where
[6] = r_symbolnum
& 0x0ff;
4521 where
[7] = (((fixP
->fx_pcrel
<< 7) & 0x80) | ((nbytes_r_length
[fixP
->fx_size
] << 5) & 0x60) |
4522 (((!S_IS_DEFINED (fixP
->fx_addsy
)) << 4) & 0x10));
4528 #endif /* OBJ_AOUT or OBJ_BOUT */
4530 #ifndef WORKING_DOT_WORD
4531 CONST
int md_short_jump_size
= 4;
4532 CONST
int md_long_jump_size
= 6;
4535 md_create_short_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4537 addressT from_addr
, to_addr
;
4543 offset
= to_addr
- (from_addr
+ 2);
4545 md_number_to_chars (ptr
, (valueT
) 0x6000, 2);
4546 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 2);
4550 md_create_long_jump (ptr
, from_addr
, to_addr
, frag
, to_symbol
)
4552 addressT from_addr
, to_addr
;
4558 if (cpu_of_arch (current_architecture
) < m68020
)
4560 offset
= to_addr
- S_GET_VALUE (to_symbol
);
4561 md_number_to_chars (ptr
, (valueT
) 0x4EF9, 2);
4562 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4563 fix_new (frag
, (ptr
+ 2) - frag
->fr_literal
, 4, to_symbol
, (symbolS
*) 0, (long) 0, 0,
4568 offset
= to_addr
- (from_addr
+ 2);
4569 md_number_to_chars (ptr
, (valueT
) 0x60ff, 2);
4570 md_number_to_chars (ptr
+ 2, (valueT
) offset
, 4);
4575 /* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?)
4578 10: Absolute 1:8 only
4579 20: Absolute 0:7 only
4580 30: absolute 0:15 only
4581 40: Absolute 0:31 only
4582 50: absolute 0:127 only
4583 55: absolute -64:63 only
4584 60: absolute -128:127 only
4585 70: absolute 0:4095 only
4592 struct m68k_exp
*exp
;
4600 if (*exp
->e_beg
== '0')
4602 if (exp
->e_beg
[1] == 'x')
4603 sscanf (exp
->e_beg
+ 2, "%x", &l
);
4605 sscanf (exp
->e_beg
+ 1, "%O", &l
);
4608 return atol (exp
->e_beg
);
4616 /* Can't do anything */
4619 if (!exp
->e_beg
|| !exp
->e_end
)
4621 seg (exp
) = absolute_section
;
4624 offs (exp
) = (ok
== 10) ? 1 : 0;
4625 as_warn ("Null expression defaults to %ld", offs (exp
));
4630 if ( /* ok!=80 && */ (exp
->e_end
[-1] == ':' || exp
->e_end
[-1] == '.')
4631 && (exp
->e_end
- exp
->e_beg
) >= 2)
4633 switch (exp
->e_end
[0])
4653 if (exp
->e_end
[-1] == ':')
4654 as_bad ("Unknown size for expression \"%c\"", exp
->e_end
[0]);
4658 c_save
= exp
->e_end
[1];
4659 exp
->e_end
[1] = '\0';
4660 save_in
= input_line_pointer
;
4661 input_line_pointer
= exp
->e_beg
;
4662 section
= expression (&exp
->e_exp
);
4663 if (section
== pass1_section
)
4665 seg (exp
) = absolute_section
;
4668 offs (exp
) = (ok
== 10) ? 1 : 0;
4669 as_warn ("Unknown expression: '%s' defaulting to %d", exp
->e_beg
, offs (exp
));
4671 else if (section
== absent_section
)
4673 /* Do the same thing the VAX asm does */
4674 seg (exp
) = absolute_section
;
4680 as_warn ("expression out of range: defaulting to 1");
4684 else if (section
== absolute_section
)
4689 if (offs (exp
) < 1 || offs (exp
) > 8)
4691 as_warn ("expression out of range: defaulting to 1");
4696 if (offs (exp
) < 0 || offs (exp
) > 7)
4700 if (offs (exp
) < 0 || offs (exp
) > 15)
4704 if (offs (exp
) < 0 || offs (exp
) > 32)
4708 if (offs (exp
) < 0 || offs (exp
) > 127)
4712 if (offs (exp
) < -64 || offs (exp
) > 63)
4716 if (offs (exp
) < -128 || offs (exp
) > 127)
4720 if (offs (exp
) < 0 || offs (exp
) > 4095)
4723 as_warn ("expression out of range: defaulting to 0");
4731 else if (section
== big_section
)
4733 if (offs (exp
) < 0 /* flonum */
4734 && (ok
== 80 /* no bignums */
4735 || (ok
> 10 /* small-int ranges including 0 ok */
4736 /* If we have a flonum zero, a zero integer should
4737 do as well (e.g., in moveq). */
4738 && generic_floating_point_number
.exponent
== 0
4739 && generic_floating_point_number
.low
[0] == 0)))
4741 /* HACK! Turn it into a long */
4742 LITTLENUM_TYPE words
[6];
4744 gen_to_words (words
, 2, 8L); /* These numbers are magic! */
4745 seg (exp
) = absolute_section
;
4748 offs (exp
) = words
[1] | (words
[0] << 16);
4752 seg (exp
) = absolute_section
;
4755 offs (exp
) = (ok
== 10) ? 1 : 0;
4756 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp
->e_beg
, offs (exp
));
4761 if (ok
>= 10 && ok
<= 70)
4763 seg (exp
) = absolute_section
;
4766 offs (exp
) = (ok
== 10) ? 1 : 0;
4767 as_warn ("Can't deal with expression \"%s\": defaulting to %ld", exp
->e_beg
, offs (exp
));
4771 if (input_line_pointer
!= exp
->e_end
+ 1)
4772 as_bad ("Ignoring junk after expression");
4773 exp
->e_end
[1] = c_save
;
4774 input_line_pointer
= save_in
;
4780 if (!isbyte (offs (exp
)))
4781 as_warn ("expression doesn't fit in BYTE");
4784 if (!isword (offs (exp
)))
4785 as_warn ("expression doesn't fit in WORD");
4793 /* These are the back-ends for the various machine dependent pseudo-ops. */
4794 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4799 subseg_new (data_section
, 1);
4800 demand_empty_rest_of_line ();
4806 subseg_new (data_section
, 2);
4807 demand_empty_rest_of_line ();
4813 /* We don't support putting frags in the BSS segment, we fake it
4814 by marking in_bss, then looking at s_skip for clues. */
4816 subseg_new (bss_section
, 0);
4817 demand_empty_rest_of_line ();
4824 register long temp_fill
;
4826 temp
= 1; /* JF should be 2? */
4827 temp_fill
= get_absolute_expression ();
4828 if (!need_pass_2
) /* Never make frag if expect extra pass. */
4829 frag_align (temp
, (int) temp_fill
);
4830 demand_empty_rest_of_line ();
4836 demand_empty_rest_of_line ();
4839 /* s_space is defined in read.c .skip is simply an alias to it. */
4843 * Invocation line includes a switch not recognized by the base assembler.
4844 * See if it's a processor-specific option. These are:
4846 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
4847 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
4848 * Select the architecture. Instructions or features not
4849 * supported by the selected architecture cause fatal
4850 * errors. More than one may be specified. The default is
4851 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
4852 * for -m68000, and -m68882 is a synonym for -m68881.
4853 * -[A]m[c]no-68851, -[A]m[c]no-68881
4854 * Don't accept 688?1 instructions. (The "c" is kind of silly,
4855 * so don't use or document it, but that's the way the parsing
4858 * MAYBE_FLOAT_TOO is defined below so that specifying a processor type
4859 * (e.g. m68020) also requests that float instructions be included. This
4860 * is the default setup, mostly to avoid hassling users. A better
4861 * rearrangement of this structure would be to add an option to DENY
4862 * floating point opcodes, for people who want to really know there's none
4863 * of that funny floaty stuff going on. FIXME-later.
4865 #ifndef MAYBE_FLOAT_TOO
4866 #define MAYBE_FLOAT_TOO /* m68881 */ 0 /* this is handled later */
4870 md_parse_option (argP
, cntP
, vecP
)
4877 case 'l': /* -l means keep external to 2 bit offset
4878 rather than 16 bit one */
4881 case 'S': /* -S means that jbsr's always turn into
4887 /* intentional fall-through */
4894 } /* allow an optional "c" */
4896 if (!strcmp (*argP
, "68000")
4897 || !strcmp (*argP
, "68008")
4898 || !strcmp (*argP
, "68302"))
4900 current_architecture
|= m68000
;
4902 else if (!strcmp (*argP
, "68010"))
4905 omagic
= 1 << 16 | OMAGIC
;
4907 current_architecture
|= m68010
;
4909 else if (!strcmp (*argP
, "68020"))
4911 current_architecture
|= m68020
| MAYBE_FLOAT_TOO
;
4913 else if (!strcmp (*argP
, "68030"))
4915 current_architecture
|= m68030
| MAYBE_FLOAT_TOO
;
4917 else if (!strcmp (*argP
, "68040"))
4919 current_architecture
|= m68040
| MAYBE_FLOAT_TOO
;
4922 else if (!strcmp (*argP
, "68881"))
4924 current_architecture
|= m68881
;
4926 else if (!strcmp (*argP
, "68882"))
4928 current_architecture
|= m68882
;
4930 #endif /* NO_68881 */
4931 /* Even if we aren't configured to support the processor,
4932 it should still be possible to assert that the user
4933 doesn't have it... */
4934 else if (!strcmp (*argP
, "no-68881")
4935 || !strcmp (*argP
, "no-68882"))
4940 else if (!strcmp (*argP
, "68851"))
4942 current_architecture
|= m68851
;
4944 #endif /* NO_68851 */
4945 else if (!strcmp (*argP
, "no-68851"))
4949 else if (!strcmp (*argP
, "pu32") /* "cpu32" minus 'c' */
4950 || !strcmp (*argP
, "68331")
4951 || !strcmp (*argP
, "68332")
4952 || !strcmp (*argP
, "68333")
4953 || !strcmp (*argP
, "68340"))
4955 current_architecture
|= cpu32
;
4959 as_warn ("Unknown architecture, \"%s\". option ignored", *argP
);
4960 } /* switch on architecture */
4968 if (!strcmp (*argP
, "pic"))
4971 break; /* -pic, Position Independent Code */
4987 /* TEST2: Test md_assemble() */
4988 /* Warning, this routine probably doesn't work anymore */
4992 struct m68k_it the_ins
;
5000 if (!gets (buf
) || !*buf
)
5002 if (buf
[0] == '|' || buf
[1] == '.')
5004 for (cp
= buf
; *cp
; cp
++)
5009 memset (&the_ins
, '\0', sizeof (the_ins
));
5010 m68k_ip (&the_ins
, buf
);
5013 printf ("Error %s in %s\n", the_ins
.error
, buf
);
5017 printf ("Opcode(%d.%s): ", the_ins
.numo
, the_ins
.args
);
5018 for (n
= 0; n
< the_ins
.numo
; n
++)
5019 printf (" 0x%x", the_ins
.opcode
[n
] & 0xffff);
5021 print_the_insn (&the_ins
.opcode
[0], stdout
);
5022 (void) putchar ('\n');
5024 for (n
= 0; n
< strlen (the_ins
.args
) / 2; n
++)
5026 if (the_ins
.operands
[n
].error
)
5028 printf ("op%d Error %s in %s\n", n
, the_ins
.operands
[n
].error
, buf
);
5031 printf ("mode %d, reg %d, ", the_ins
.operands
[n
].mode
, the_ins
.operands
[n
].reg
);
5032 if (the_ins
.operands
[n
].b_const
)
5033 printf ("Constant: '%.*s', ", 1 + the_ins
.operands
[n
].e_const
- the_ins
.operands
[n
].b_const
, the_ins
.operands
[n
].b_const
);
5034 printf ("ireg %d, isiz %d, imul %d, ", the_ins
.operands
[n
].ireg
, the_ins
.operands
[n
].isiz
, the_ins
.operands
[n
].imul
);
5035 if (the_ins
.operands
[n
].b_iadd
)
5036 printf ("Iadd: '%.*s',", 1 + the_ins
.operands
[n
].e_iadd
- the_ins
.operands
[n
].b_iadd
, the_ins
.operands
[n
].b_iadd
);
5037 (void) putchar ('\n');
5049 while (*str
&& *str
!= ' ')
5051 if (str
[-1] == ':' || str
[1] == '=')
5058 /* Possible states for relaxation:
5060 0 0 branch offset byte (bra, etc)
5064 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5068 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5075 /* We have no need to default values of symbols. */
5079 md_undefined_symbol (name
)
5085 /* Parse an operand that is machine-specific.
5086 We just return without modifying the expression if we have nothing
5091 md_operand (expressionP
)
5092 expressionS
*expressionP
;
5096 /* Round up a section size to the appropriate boundary. */
5098 md_section_align (segment
, size
)
5102 return size
; /* Byte alignment is fine */
5105 /* Exactly what point is a PC-relative offset relative TO?
5106 On the 68k, they're relative to the address of the offset, plus
5107 its size. (??? Is this right? FIXME-SOON!) */
5109 md_pcrel_from (fixP
)
5112 return (fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
);
5115 #ifndef BFD_ASSEMBLER
5117 tc_coff_symbol_emit_hook ()
5122 tc_coff_sizemachdep (frag
)
5125 switch (frag
->fr_subtype
& 0x3)
5139 /* end of tc-m68k.c */