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[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
36 #else
37 const char *m68k_comment_chars = "|";
38 #endif
39
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#*";
48
49 const char line_separator_chars[] = "";
50
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
53
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
56
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
58
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
62
63 const int md_reloc_size = 8; /* Size of relocation record */
64
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
69 int flag_want_pic;
70
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
73
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76 #else
77 int flag_reg_prefix_optional;
78 #endif
79
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
82
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
85
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
89
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
93
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97 static int m68k_rel32 = 1;
98
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
101
102 /* The default width to use for an index register when using a base
103 displacement. */
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110 struct label_line
111 {
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117 };
118
119 /* The list of labels. */
120
121 static struct label_line *labels;
122
123 /* The current label. */
124
125 static struct label_line *current_label;
126
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
130
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
133 #define BYTE 0
134 #define SHORT 1
135 #define LONG 2
136 #define SZ_UNDEF 3
137 #undef BRANCH
138 /* Case `g' except when BCC68000 is applicable. */
139 #define ABRANCH 1
140 /* Coprocessor branches. */
141 #define FBRANCH 2
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
144 #define PCREL 3
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
150 #define BCC68000 4
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
153 #define DBCC 5
154 /* Not currently used? */
155 #define PCLEA 6
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158 #define PCINDEX 7
159
160 struct m68k_incant
161 {
162 const char *m_operands;
163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
172
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
175 SFC, DFC, USP, VBR,
176 0
177 };
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181 };
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186 };
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191 };
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196 };
197 #define cpu32_control_regs m68010_control_regs
198
199 static const enum m68k_register *control_regs;
200
201 /* internal form of a 68020 instruction */
202 struct m68k_it
203 {
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
207
208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
210
211 struct m68k_op operands[6];
212
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
215
216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
221 offsetT foff;
222 int fragty;
223 }
224 fragb[4];
225
226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
241 #ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245 #endif
246 }
247 reloc[5]; /* Five is enough??? */
248 };
249
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
253
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
257 static struct m68k_it the_ins; /* the instruction being assembled */
258
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
263
264 /* Macros for adding things to the m68k_it struct */
265
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
268 /* Static functions. */
269
270 static void insop PARAMS ((int, struct m68k_incant *));
271 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
272 static void add_frag PARAMS ((symbolS *, offsetT, int));
273
274 /* Like addword, but goes BEFORE general operands */
275 static void
276 insop (w, opcode)
277 int w;
278 struct m68k_incant *opcode;
279 {
280 int z;
281 for(z=the_ins.numo;z>opcode->m_codenum;--z)
282 the_ins.opcode[z]=the_ins.opcode[z-1];
283 for(z=0;z<the_ins.nrel;z++)
284 the_ins.reloc[z].n+=2;
285 for (z = 0; z < the_ins.nfrag; z++)
286 the_ins.fragb[z].fragoff++;
287 the_ins.opcode[opcode->m_codenum]=w;
288 the_ins.numo++;
289 }
290
291 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
292 Blecch. */
293 static void
294 add_fix (width, exp, pc_rel, pc_fix)
295 int width;
296 struct m68k_exp *exp;
297 int pc_rel;
298 int pc_fix;
299 {
300 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
301 ? (the_ins.numo*2-1)
302 : (((width)=='b')
303 ? (the_ins.numo*2+1)
304 : (the_ins.numo*2)));
305 the_ins.reloc[the_ins.nrel].exp = exp->exp;
306 the_ins.reloc[the_ins.nrel].wid = width;
307 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
308 #ifdef OBJ_ELF
309 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
310 #endif
311 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
312 }
313
314 /* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
318
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
322
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
324 static void
325 add_frag (add, off, type)
326 symbolS *add;
327 offsetT off;
328 int type;
329 {
330 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
331 the_ins.fragb[the_ins.nfrag].fadd=add;
332 the_ins.fragb[the_ins.nfrag].foff=off;
333 the_ins.fragb[the_ins.nfrag++].fragty=type;
334 }
335
336 #define isvar(ex) \
337 (op (ex) != O_constant && op (ex) != O_big)
338
339 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
340 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
341 static void m68k_ip PARAMS ((char *));
342 static void insert_reg PARAMS ((const char *, int));
343 static void select_control_regs PARAMS ((void));
344 static void init_regtable PARAMS ((void));
345 static int reverse_16_bits PARAMS ((int in));
346 static int reverse_8_bits PARAMS ((int in));
347 static void install_gen_operand PARAMS ((int mode, int val));
348 static void install_operand PARAMS ((int mode, int val));
349 static void s_bss PARAMS ((int));
350 static void s_data1 PARAMS ((int));
351 static void s_data2 PARAMS ((int));
352 static void s_even PARAMS ((int));
353 static void s_proc PARAMS ((int));
354 static void mri_chip PARAMS ((void));
355 static void s_chip PARAMS ((int));
356 static void s_fopt PARAMS ((int));
357 static void s_opt PARAMS ((int));
358 static void s_reg PARAMS ((int));
359 static void s_restore PARAMS ((int));
360 static void s_save PARAMS ((int));
361 static void s_mri_if PARAMS ((int));
362 static void s_mri_else PARAMS ((int));
363 static void s_mri_endi PARAMS ((int));
364 static void s_mri_break PARAMS ((int));
365 static void s_mri_next PARAMS ((int));
366 static void s_mri_for PARAMS ((int));
367 static void s_mri_endf PARAMS ((int));
368 static void s_mri_repeat PARAMS ((int));
369 static void s_mri_until PARAMS ((int));
370 static void s_mri_while PARAMS ((int));
371 static void s_mri_endw PARAMS ((int));
372 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
373 static void md_convert_frag_1 PARAMS ((fragS *));
374
375 static int current_architecture;
376
377 struct m68k_cpu {
378 unsigned long arch;
379 const char *name;
380 int alias;
381 };
382
383 static const struct m68k_cpu archs[] = {
384 { m68000, "68000", 0 },
385 { m68010, "68010", 0 },
386 { m68020, "68020", 0 },
387 { m68030, "68030", 0 },
388 { m68040, "68040", 0 },
389 { m68060, "68060", 0 },
390 { cpu32, "cpu32", 0 },
391 { m68881, "68881", 0 },
392 { m68851, "68851", 0 },
393 { mcf5200, "5200", 0 },
394 /* Aliases (effectively, so far as gas is concerned) for the above
395 cpus. */
396 { m68020, "68k", 1 },
397 { m68000, "68008", 1 },
398 { m68000, "68302", 1 },
399 { m68000, "68306", 1 },
400 { m68000, "68307", 1 },
401 { m68000, "68322", 1 },
402 { m68000, "68356", 1 },
403 { m68000, "68ec000", 1 },
404 { m68000, "68hc000", 1 },
405 { m68000, "68hc001", 1 },
406 { m68020, "68ec020", 1 },
407 { m68030, "68ec030", 1 },
408 { m68040, "68ec040", 1 },
409 { m68060, "68ec060", 1 },
410 { cpu32, "68330", 1 },
411 { cpu32, "68331", 1 },
412 { cpu32, "68332", 1 },
413 { cpu32, "68333", 1 },
414 { cpu32, "68334", 1 },
415 { cpu32, "68336", 1 },
416 { cpu32, "68340", 1 },
417 { cpu32, "68341", 1 },
418 { cpu32, "68349", 1 },
419 { cpu32, "68360", 1 },
420 { m68881, "68882", 1 },
421 };
422
423 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
424
425 /* BCC68000 is for patching in an extra jmp instruction for long offsets
426 on the 68000. The 68000 doesn't support long branches with branchs */
427
428 /* This table desribes how you change sizes for the various types of variable
429 size expressions. This version only supports two kinds. */
430
431 /* Note that calls to frag_var need to specify the maximum expansion
432 needed; this is currently 10 bytes for DBCC. */
433
434 /* The fields are:
435 How far Forward this mode will reach:
436 How far Backward this mode will reach:
437 How many bytes this mode will add to the size of the frag
438 Which mode to go to if the offset won't fit in this one
439 */
440 relax_typeS md_relax_table[] =
441 {
442 {1, 1, 0, 0}, /* First entries aren't used */
443 {1, 1, 0, 0}, /* For no good reason except */
444 {1, 1, 0, 0}, /* that the VAX doesn't either */
445 {1, 1, 0, 0},
446
447 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
448 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
449 {0, 0, 4, 0},
450 {1, 1, 0, 0},
451
452 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
453 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
454 {0, 0, 4, 0},
455 {1, 1, 0, 0},
456
457 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
458 {(32767), (-32768), 2, TAB (PCREL, LONG)},
459 {0, 0, 4, 0},
460 {1, 1, 0, 0},
461
462 {(127), (-128), 0, TAB (BCC68000, SHORT)},
463 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
464 {0, 0, 6, 0}, /* jmp long space */
465 {1, 1, 0, 0},
466
467 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
468 {(32767), (-32768), 2, TAB (DBCC, LONG)},
469 {0, 0, 10, 0}, /* bra/jmp long space */
470 {1, 1, 0, 0},
471
472 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
473 {32767, -32768, 2, TAB (PCLEA, LONG)},
474 {0, 0, 6, 0},
475 {1, 1, 0, 0},
476
477 /* For, e.g., jmp pcrel indexed. */
478 {125, -130, 0, TAB (PCINDEX, SHORT)},
479 {32765, -32770, 2, TAB (PCINDEX, LONG)},
480 {0, 0, 4, 0},
481 {1, 1, 0, 0},
482 };
483
484 /* These are the machine dependent pseudo-ops. These are included so
485 the assembler can work on the output from the SUN C compiler, which
486 generates these.
487 */
488
489 /* This table describes all the machine specific pseudo-ops the assembler
490 has to support. The fields are:
491 pseudo-op name without dot
492 function to call to execute this pseudo-op
493 Integer arg to pass to the function
494 */
495 const pseudo_typeS md_pseudo_table[] =
496 {
497 {"data1", s_data1, 0},
498 {"data2", s_data2, 0},
499 {"bss", s_bss, 0},
500 {"even", s_even, 0},
501 {"skip", s_space, 0},
502 {"proc", s_proc, 0},
503 #if defined (TE_SUN3) || defined (OBJ_ELF)
504 {"align", s_align_bytes, 0},
505 #endif
506 #ifdef OBJ_ELF
507 {"swbeg", s_ignore, 0},
508 #endif
509 {"extend", float_cons, 'x'},
510 {"ldouble", float_cons, 'x'},
511
512 /* The following pseudo-ops are supported for MRI compatibility. */
513 {"chip", s_chip, 0},
514 {"comline", s_space, 1},
515 {"fopt", s_fopt, 0},
516 {"mask2", s_ignore, 0},
517 {"opt", s_opt, 0},
518 {"reg", s_reg, 0},
519 {"restore", s_restore, 0},
520 {"save", s_save, 0},
521
522 {"if", s_mri_if, 0},
523 {"if.b", s_mri_if, 'b'},
524 {"if.w", s_mri_if, 'w'},
525 {"if.l", s_mri_if, 'l'},
526 {"else", s_mri_else, 0},
527 {"else.s", s_mri_else, 's'},
528 {"else.l", s_mri_else, 'l'},
529 {"endi", s_mri_endi, 0},
530 {"break", s_mri_break, 0},
531 {"break.s", s_mri_break, 's'},
532 {"break.l", s_mri_break, 'l'},
533 {"next", s_mri_next, 0},
534 {"next.s", s_mri_next, 's'},
535 {"next.l", s_mri_next, 'l'},
536 {"for", s_mri_for, 0},
537 {"for.b", s_mri_for, 'b'},
538 {"for.w", s_mri_for, 'w'},
539 {"for.l", s_mri_for, 'l'},
540 {"endf", s_mri_endf, 0},
541 {"repeat", s_mri_repeat, 0},
542 {"until", s_mri_until, 0},
543 {"until.b", s_mri_until, 'b'},
544 {"until.w", s_mri_until, 'w'},
545 {"until.l", s_mri_until, 'l'},
546 {"while", s_mri_while, 0},
547 {"while.b", s_mri_while, 'b'},
548 {"while.w", s_mri_while, 'w'},
549 {"while.l", s_mri_while, 'l'},
550 {"endw", s_mri_endw, 0},
551
552 {0, 0, 0}
553 };
554
555
556 /* The mote pseudo ops are put into the opcode table, since they
557 don't start with a . they look like opcodes to gas.
558 */
559
560 #ifdef M68KCOFF
561 extern void obj_coff_section PARAMS ((int));
562 #endif
563
564 CONST pseudo_typeS mote_pseudo_table[] =
565 {
566
567 {"dcl", cons, 4},
568 {"dc", cons, 2},
569 {"dcw", cons, 2},
570 {"dcb", cons, 1},
571
572 {"dsl", s_space, 4},
573 {"ds", s_space, 2},
574 {"dsw", s_space, 2},
575 {"dsb", s_space, 1},
576
577 {"xdef", s_globl, 0},
578 #ifdef OBJ_ELF
579 {"align", s_align_bytes, 0},
580 #else
581 {"align", s_align_ptwo, 0},
582 #endif
583 #ifdef M68KCOFF
584 {"sect", obj_coff_section, 0},
585 {"section", obj_coff_section, 0},
586 #endif
587 {0, 0, 0}
588 };
589
590 #define issbyte(x) ((x)>=-128 && (x)<=127)
591 #define isubyte(x) ((x)>=0 && (x)<=255)
592 #define issword(x) ((x)>=-32768 && (x)<=32767)
593 #define isuword(x) ((x)>=0 && (x)<=65535)
594
595 #define isbyte(x) ((x)>= -255 && (x)<=255)
596 #define isword(x) ((x)>=-65536 && (x)<=65535)
597 #define islong(x) (1)
598
599 extern char *input_line_pointer;
600
601 static char mklower_table[256];
602 #define mklower(c) (mklower_table[(unsigned char)(c)])
603 static char notend_table[256];
604 static char alt_notend_table[256];
605 #define notend(s) \
606 (! (notend_table[(unsigned char) *s] \
607 || (*s == ':' \
608 && alt_notend_table[(unsigned char) s[1]])))
609
610 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
611
612 #ifdef NO_PCREL_RELOCS
613
614 int
615 make_pcrel_absolute(fixP, add_number)
616 fixS *fixP;
617 long *add_number;
618 {
619 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
620
621 /* rewrite the PC relative instructions to absolute address ones.
622 * these are rumoured to be faster, and the apollo linker refuses
623 * to deal with the PC relative relocations.
624 */
625 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
626 {
627 opcode[0] = 0x4e;
628 opcode[1] = 0xf9;
629 }
630 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
631 {
632 opcode[0] = 0x4e;
633 opcode[1] = 0xb9;
634 }
635 else
636 as_fatal ("Unknown PC relative instruction");
637 *add_number -= 4;
638 return 0;
639 }
640
641 #endif /* NO_PCREL_RELOCS */
642
643 short
644 tc_coff_fix2rtype (fixP)
645 fixS *fixP;
646 {
647 if (fixP->fx_tcbit && fixP->fx_size == 4)
648 return R_RELLONG_NEG;
649 #ifdef NO_PCREL_RELOCS
650 know (fixP->fx_pcrel == 0);
651 return (fixP->fx_size == 1 ? R_RELBYTE
652 : fixP->fx_size == 2 ? R_DIR16
653 : R_DIR32);
654 #else
655 return (fixP->fx_pcrel ?
656 (fixP->fx_size == 1 ? R_PCRBYTE :
657 fixP->fx_size == 2 ? R_PCRWORD :
658 R_PCRLONG) :
659 (fixP->fx_size == 1 ? R_RELBYTE :
660 fixP->fx_size == 2 ? R_RELWORD :
661 R_RELLONG));
662 #endif
663 }
664
665 #endif
666
667 #ifdef OBJ_ELF
668
669 /* Compute the relocation code for a fixup of SIZE bytes, using pc
670 relative relocation if PCREL is non-zero. PIC says whether a special
671 pic relocation was requested. */
672
673 static bfd_reloc_code_real_type get_reloc_code
674 PARAMS ((int, int, enum pic_relocation));
675
676 static bfd_reloc_code_real_type
677 get_reloc_code (size, pcrel, pic)
678 int size;
679 int pcrel;
680 enum pic_relocation pic;
681 {
682 switch (pic)
683 {
684 case pic_got_pcrel:
685 switch (size)
686 {
687 case 1:
688 return BFD_RELOC_8_GOT_PCREL;
689 case 2:
690 return BFD_RELOC_16_GOT_PCREL;
691 case 4:
692 return BFD_RELOC_32_GOT_PCREL;
693 }
694 break;
695
696 case pic_got_off:
697 switch (size)
698 {
699 case 1:
700 return BFD_RELOC_8_GOTOFF;
701 case 2:
702 return BFD_RELOC_16_GOTOFF;
703 case 4:
704 return BFD_RELOC_32_GOTOFF;
705 }
706 break;
707
708 case pic_plt_pcrel:
709 switch (size)
710 {
711 case 1:
712 return BFD_RELOC_8_PLT_PCREL;
713 case 2:
714 return BFD_RELOC_16_PLT_PCREL;
715 case 4:
716 return BFD_RELOC_32_PLT_PCREL;
717 }
718 break;
719
720 case pic_plt_off:
721 switch (size)
722 {
723 case 1:
724 return BFD_RELOC_8_PLTOFF;
725 case 2:
726 return BFD_RELOC_16_PLTOFF;
727 case 4:
728 return BFD_RELOC_32_PLTOFF;
729 }
730 break;
731
732 case pic_none:
733 if (pcrel)
734 {
735 switch (size)
736 {
737 case 1:
738 return BFD_RELOC_8_PCREL;
739 case 2:
740 return BFD_RELOC_16_PCREL;
741 case 4:
742 return BFD_RELOC_32_PCREL;
743 }
744 }
745 else
746 {
747 switch (size)
748 {
749 case 1:
750 return BFD_RELOC_8;
751 case 2:
752 return BFD_RELOC_16;
753 case 4:
754 return BFD_RELOC_32;
755 }
756 }
757 }
758
759 as_bad ("Can not do %d byte %s%srelocation", size,
760 pcrel ? "pc-relative " : "",
761 pic == pic_none ? "" : "pic ");
762 return BFD_RELOC_NONE;
763 }
764
765 /* Here we decide which fixups can be adjusted to make them relative
766 to the beginning of the section instead of the symbol. Basically
767 we need to make sure that the dynamic relocations are done
768 correctly, so in some cases we force the original symbol to be
769 used. */
770 int
771 tc_m68k_fix_adjustable (fixP)
772 fixS *fixP;
773 {
774 /* Prevent all adjustments to global symbols. */
775 if (S_IS_EXTERNAL (fixP->fx_addsy))
776 return 0;
777
778 /* adjust_reloc_syms doesn't know about the GOT */
779 switch (fixP->fx_r_type)
780 {
781 case BFD_RELOC_8_GOT_PCREL:
782 case BFD_RELOC_16_GOT_PCREL:
783 case BFD_RELOC_32_GOT_PCREL:
784 case BFD_RELOC_8_GOTOFF:
785 case BFD_RELOC_16_GOTOFF:
786 case BFD_RELOC_32_GOTOFF:
787 case BFD_RELOC_8_PLT_PCREL:
788 case BFD_RELOC_16_PLT_PCREL:
789 case BFD_RELOC_32_PLT_PCREL:
790 case BFD_RELOC_8_PLTOFF:
791 case BFD_RELOC_16_PLTOFF:
792 case BFD_RELOC_32_PLTOFF:
793 return 0;
794
795 default:
796 return 1;
797 }
798 }
799
800 #else /* !OBJ_ELF */
801
802 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
803
804 #endif /* OBJ_ELF */
805
806 #ifdef BFD_ASSEMBLER
807
808 arelent *
809 tc_gen_reloc (section, fixp)
810 asection *section;
811 fixS *fixp;
812 {
813 arelent *reloc;
814 bfd_reloc_code_real_type code;
815
816 if (fixp->fx_tcbit)
817 abort ();
818
819 if (fixp->fx_r_type != BFD_RELOC_NONE)
820 {
821 code = fixp->fx_r_type;
822
823 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
824 that fixup_segment converted a non-PC relative reloc into a
825 PC relative reloc. In such a case, we need to convert the
826 reloc code. */
827 if (fixp->fx_pcrel)
828 {
829 switch (code)
830 {
831 case BFD_RELOC_8:
832 code = BFD_RELOC_8_PCREL;
833 break;
834 case BFD_RELOC_16:
835 code = BFD_RELOC_16_PCREL;
836 break;
837 case BFD_RELOC_32:
838 code = BFD_RELOC_32_PCREL;
839 break;
840 case BFD_RELOC_8_PCREL:
841 case BFD_RELOC_16_PCREL:
842 case BFD_RELOC_32_PCREL:
843 case BFD_RELOC_8_GOT_PCREL:
844 case BFD_RELOC_16_GOT_PCREL:
845 case BFD_RELOC_32_GOT_PCREL:
846 case BFD_RELOC_8_GOTOFF:
847 case BFD_RELOC_16_GOTOFF:
848 case BFD_RELOC_32_GOTOFF:
849 case BFD_RELOC_8_PLT_PCREL:
850 case BFD_RELOC_16_PLT_PCREL:
851 case BFD_RELOC_32_PLT_PCREL:
852 case BFD_RELOC_8_PLTOFF:
853 case BFD_RELOC_16_PLTOFF:
854 case BFD_RELOC_32_PLTOFF:
855 break;
856 default:
857 as_bad_where (fixp->fx_file, fixp->fx_line,
858 "Cannot make %s relocation PC relative",
859 bfd_get_reloc_code_name (code));
860 }
861 }
862 }
863 else
864 {
865 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
866 switch (F (fixp->fx_size, fixp->fx_pcrel))
867 {
868 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
869 MAP (1, 0, BFD_RELOC_8);
870 MAP (2, 0, BFD_RELOC_16);
871 MAP (4, 0, BFD_RELOC_32);
872 MAP (1, 1, BFD_RELOC_8_PCREL);
873 MAP (2, 1, BFD_RELOC_16_PCREL);
874 MAP (4, 1, BFD_RELOC_32_PCREL);
875 default:
876 abort ();
877 }
878 }
879 #undef F
880 #undef MAP
881
882 reloc = (arelent *) xmalloc (sizeof (arelent));
883 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
884 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
885 #ifndef OBJ_ELF
886 if (fixp->fx_pcrel)
887 reloc->addend = fixp->fx_addnumber;
888 else
889 reloc->addend = 0;
890 #else
891 if (!fixp->fx_pcrel)
892 reloc->addend = fixp->fx_addnumber;
893 else
894 reloc->addend = (section->vma
895 + (fixp->fx_pcrel_adjust == 64
896 ? -1 : fixp->fx_pcrel_adjust)
897 + fixp->fx_addnumber
898 + md_pcrel_from (fixp));
899 #endif
900
901 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
902 assert (reloc->howto != 0);
903
904 return reloc;
905 }
906
907 #endif /* BFD_ASSEMBLER */
908
909 /* Handle of the OPCODE hash table. NULL means any use before
910 m68k_ip_begin() will crash. */
911 static struct hash_control *op_hash;
912 \f
913 /* Assemble an m68k instruction. */
914
915 void
916 m68k_ip (instring)
917 char *instring;
918 {
919 register char *p;
920 register struct m68k_op *opP;
921 register struct m68k_incant *opcode;
922 register const char *s;
923 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
924 char *pdot, *pdotmove;
925 enum m68k_size siz1, siz2;
926 char c;
927 int losing;
928 int opsfound;
929 LITTLENUM_TYPE words[6];
930 LITTLENUM_TYPE *wordp;
931 unsigned long ok_arch = 0;
932
933 if (*instring == ' ')
934 instring++; /* skip leading whitespace */
935
936 /* Scan up to end of operation-code, which MUST end in end-of-string
937 or exactly 1 space. */
938 pdot = 0;
939 for (p = instring; *p != '\0'; p++)
940 {
941 if (*p == ' ')
942 break;
943 if (*p == '.')
944 pdot = p;
945 }
946
947 if (p == instring)
948 {
949 the_ins.error = "No operator";
950 return;
951 }
952
953 /* p now points to the end of the opcode name, probably whitespace.
954 Make sure the name is null terminated by clobbering the
955 whitespace, look it up in the hash table, then fix it back.
956 Remove a dot, first, since the opcode tables have none. */
957 if (pdot != NULL)
958 {
959 for (pdotmove = pdot; pdotmove < p; pdotmove++)
960 *pdotmove = pdotmove[1];
961 p--;
962 }
963
964 c = *p;
965 *p = '\0';
966 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
967 *p = c;
968
969 if (pdot != NULL)
970 {
971 for (pdotmove = p; pdotmove > pdot; pdotmove--)
972 *pdotmove = pdotmove[-1];
973 *pdot = '.';
974 ++p;
975 }
976
977 if (opcode == NULL)
978 {
979 the_ins.error = "Unknown operator";
980 return;
981 }
982
983 /* found a legitimate opcode, start matching operands */
984 while (*p == ' ')
985 ++p;
986
987 if (opcode->m_operands == 0)
988 {
989 char *old = input_line_pointer;
990 *old = '\n';
991 input_line_pointer = p;
992 /* Ahh - it's a motorola style psuedo op */
993 mote_pseudo_table[opcode->m_opnum].poc_handler
994 (mote_pseudo_table[opcode->m_opnum].poc_val);
995 input_line_pointer = old;
996 *old = 0;
997
998 return;
999 }
1000
1001 if (flag_mri && opcode->m_opnum == 0)
1002 {
1003 /* In MRI mode, random garbage is allowed after an instruction
1004 which accepts no operands. */
1005 the_ins.args = opcode->m_operands;
1006 the_ins.numargs = opcode->m_opnum;
1007 the_ins.numo = opcode->m_codenum;
1008 the_ins.opcode[0] = getone (opcode);
1009 the_ins.opcode[1] = gettwo (opcode);
1010 return;
1011 }
1012
1013 for (opP = &the_ins.operands[0]; *p; opP++)
1014 {
1015 p = crack_operand (p, opP);
1016
1017 if (opP->error)
1018 {
1019 the_ins.error = opP->error;
1020 return;
1021 }
1022 }
1023
1024 opsfound = opP - &the_ins.operands[0];
1025
1026 /* This ugly hack is to support the floating pt opcodes in their
1027 standard form. Essentially, we fake a first enty of type COP#1 */
1028 if (opcode->m_operands[0] == 'I')
1029 {
1030 int n;
1031
1032 for (n = opsfound; n > 0; --n)
1033 the_ins.operands[n] = the_ins.operands[n - 1];
1034
1035 memset ((char *) (&the_ins.operands[0]), '\0',
1036 sizeof (the_ins.operands[0]));
1037 the_ins.operands[0].mode = CONTROL;
1038 the_ins.operands[0].reg = m68k_float_copnum;
1039 opsfound++;
1040 }
1041
1042 /* We've got the operands. Find an opcode that'll accept them */
1043 for (losing = 0;;)
1044 {
1045 /* If we didn't get the right number of ops, or we have no
1046 common model with this pattern then reject this pattern. */
1047
1048 ok_arch |= opcode->m_arch;
1049 if (opsfound != opcode->m_opnum
1050 || ((opcode->m_arch & current_architecture) == 0))
1051 ++losing;
1052 else
1053 {
1054 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1055 *s && !losing;
1056 s += 2, opP++)
1057 {
1058 /* Warning: this switch is huge! */
1059 /* I've tried to organize the cases into this order:
1060 non-alpha first, then alpha by letter. Lower-case
1061 goes directly before uppercase counterpart. */
1062 /* Code with multiple case ...: gets sorted by the lowest
1063 case ... it belongs to. I hope this makes sense. */
1064 switch (*s)
1065 {
1066 case '!':
1067 switch (opP->mode)
1068 {
1069 case IMMED:
1070 case DREG:
1071 case AREG:
1072 case FPREG:
1073 case CONTROL:
1074 case AINC:
1075 case ADEC:
1076 case REGLST:
1077 losing++;
1078 break;
1079 default:
1080 break;
1081 }
1082 break;
1083
1084 case '<':
1085 switch (opP->mode)
1086 {
1087 case DREG:
1088 case AREG:
1089 case FPREG:
1090 case CONTROL:
1091 case IMMED:
1092 case ADEC:
1093 case REGLST:
1094 losing++;
1095 break;
1096 default:
1097 break;
1098 }
1099 break;
1100
1101 case '>':
1102 switch (opP->mode)
1103 {
1104 case DREG:
1105 case AREG:
1106 case FPREG:
1107 case CONTROL:
1108 case IMMED:
1109 case AINC:
1110 case REGLST:
1111 losing++;
1112 break;
1113 case ABSL:
1114 break;
1115 default:
1116 if (opP->reg == PC
1117 || opP->reg == ZPC)
1118 losing++;
1119 break;
1120 }
1121 break;
1122
1123 case 'm':
1124 switch (opP->mode)
1125 {
1126 case DREG:
1127 case AREG:
1128 case AINDR:
1129 case AINC:
1130 case ADEC:
1131 break;
1132 default:
1133 losing++;
1134 }
1135 break;
1136
1137 case 'n':
1138 switch (opP->mode)
1139 {
1140 case DISP:
1141 break;
1142 default:
1143 losing++;
1144 }
1145 break;
1146
1147 case 'o':
1148 switch (opP->mode)
1149 {
1150 case BASE:
1151 case ABSL:
1152 case IMMED:
1153 break;
1154 default:
1155 losing++;
1156 }
1157 break;
1158
1159 case 'p':
1160 switch (opP->mode)
1161 {
1162 case DREG:
1163 case AREG:
1164 case AINDR:
1165 case AINC:
1166 case ADEC:
1167 break;
1168 case DISP:
1169 if (opP->reg == PC || opP->reg == ZPC)
1170 losing++;
1171 break;
1172 default:
1173 losing++;
1174 }
1175 break;
1176
1177 case 'q':
1178 switch (opP->mode)
1179 {
1180 case DREG:
1181 case AINDR:
1182 case AINC:
1183 case ADEC:
1184 break;
1185 case DISP:
1186 if (opP->reg == PC || opP->reg == ZPC)
1187 losing++;
1188 break;
1189 default:
1190 losing++;
1191 break;
1192 }
1193 break;
1194
1195 case 'v':
1196 switch (opP->mode)
1197 {
1198 case DREG:
1199 case AINDR:
1200 case AINC:
1201 case ADEC:
1202 case ABSL:
1203 break;
1204 case DISP:
1205 if (opP->reg == PC || opP->reg == ZPC)
1206 losing++;
1207 break;
1208 default:
1209 losing++;
1210 break;
1211 }
1212 break;
1213
1214 case '#':
1215 if (opP->mode != IMMED)
1216 losing++;
1217 else if (s[1] == 'b'
1218 && ! isvar (&opP->disp)
1219 && (opP->disp.exp.X_op != O_constant
1220 || ! isbyte (opP->disp.exp.X_add_number)))
1221 losing++;
1222 else if (s[1] == 'B'
1223 && ! isvar (&opP->disp)
1224 && (opP->disp.exp.X_op != O_constant
1225 || ! issbyte (opP->disp.exp.X_add_number)))
1226 losing++;
1227 else if (s[1] == 'w'
1228 && ! isvar (&opP->disp)
1229 && (opP->disp.exp.X_op != O_constant
1230 || ! isword (opP->disp.exp.X_add_number)))
1231 losing++;
1232 else if (s[1] == 'W'
1233 && ! isvar (&opP->disp)
1234 && (opP->disp.exp.X_op != O_constant
1235 || ! issword (opP->disp.exp.X_add_number)))
1236 losing++;
1237 break;
1238
1239 case '^':
1240 case 'T':
1241 if (opP->mode != IMMED)
1242 losing++;
1243 break;
1244
1245 case '$':
1246 if (opP->mode == AREG
1247 || opP->mode == CONTROL
1248 || opP->mode == FPREG
1249 || opP->mode == IMMED
1250 || opP->mode == REGLST
1251 || (opP->mode != ABSL
1252 && (opP->reg == PC
1253 || opP->reg == ZPC)))
1254 losing++;
1255 break;
1256
1257 case '%':
1258 if (opP->mode == CONTROL
1259 || opP->mode == FPREG
1260 || opP->mode == REGLST
1261 || opP->mode == IMMED
1262 || (opP->mode != ABSL
1263 && (opP->reg == PC
1264 || opP->reg == ZPC)))
1265 losing++;
1266 break;
1267
1268 case '&':
1269 switch (opP->mode)
1270 {
1271 case DREG:
1272 case AREG:
1273 case FPREG:
1274 case CONTROL:
1275 case IMMED:
1276 case AINC:
1277 case ADEC:
1278 case REGLST:
1279 losing++;
1280 break;
1281 case ABSL:
1282 break;
1283 default:
1284 if (opP->reg == PC
1285 || opP->reg == ZPC)
1286 losing++;
1287 break;
1288 }
1289 break;
1290
1291 case '*':
1292 if (opP->mode == CONTROL
1293 || opP->mode == FPREG
1294 || opP->mode == REGLST)
1295 losing++;
1296 break;
1297
1298 case '+':
1299 if (opP->mode != AINC)
1300 losing++;
1301 break;
1302
1303 case '-':
1304 if (opP->mode != ADEC)
1305 losing++;
1306 break;
1307
1308 case '/':
1309 switch (opP->mode)
1310 {
1311 case AREG:
1312 case CONTROL:
1313 case FPREG:
1314 case AINC:
1315 case ADEC:
1316 case IMMED:
1317 case REGLST:
1318 losing++;
1319 break;
1320 default:
1321 break;
1322 }
1323 break;
1324
1325 case ';':
1326 switch (opP->mode)
1327 {
1328 case AREG:
1329 case CONTROL:
1330 case FPREG:
1331 case REGLST:
1332 losing++;
1333 break;
1334 default:
1335 break;
1336 }
1337 break;
1338
1339 case '?':
1340 switch (opP->mode)
1341 {
1342 case AREG:
1343 case CONTROL:
1344 case FPREG:
1345 case AINC:
1346 case ADEC:
1347 case IMMED:
1348 case REGLST:
1349 losing++;
1350 break;
1351 case ABSL:
1352 break;
1353 default:
1354 if (opP->reg == PC || opP->reg == ZPC)
1355 losing++;
1356 break;
1357 }
1358 break;
1359
1360 case '@':
1361 switch (opP->mode)
1362 {
1363 case AREG:
1364 case CONTROL:
1365 case FPREG:
1366 case IMMED:
1367 case REGLST:
1368 losing++;
1369 break;
1370 default:
1371 break;
1372 }
1373 break;
1374
1375 case '~': /* For now! (JF FOO is this right?) */
1376 switch (opP->mode)
1377 {
1378 case DREG:
1379 case AREG:
1380 case CONTROL:
1381 case FPREG:
1382 case IMMED:
1383 case REGLST:
1384 losing++;
1385 break;
1386 case ABSL:
1387 break;
1388 default:
1389 if (opP->reg == PC
1390 || opP->reg == ZPC)
1391 losing++;
1392 break;
1393 }
1394 break;
1395
1396 case '3':
1397 if (opP->mode != CONTROL
1398 || (opP->reg != TT0 && opP->reg != TT1))
1399 losing++;
1400 break;
1401
1402 case 'A':
1403 if (opP->mode != AREG)
1404 losing++;
1405 break;
1406
1407 case 'a':
1408 if (opP->mode != AINDR)
1409 ++losing;
1410 break;
1411
1412 case 'B': /* FOO */
1413 if (opP->mode != ABSL
1414 || (flag_long_jumps
1415 && strncmp (instring, "jbsr", 4) == 0))
1416 losing++;
1417 break;
1418
1419 case 'C':
1420 if (opP->mode != CONTROL || opP->reg != CCR)
1421 losing++;
1422 break;
1423
1424 case 'd':
1425 if (opP->mode != DISP
1426 || opP->reg < ADDR0
1427 || opP->reg > ADDR7)
1428 losing++;
1429 break;
1430
1431 case 'D':
1432 if (opP->mode != DREG)
1433 losing++;
1434 break;
1435
1436 case 'F':
1437 if (opP->mode != FPREG)
1438 losing++;
1439 break;
1440
1441 case 'I':
1442 if (opP->mode != CONTROL
1443 || opP->reg < COP0
1444 || opP->reg > COP7)
1445 losing++;
1446 break;
1447
1448 case 'J':
1449 if (opP->mode != CONTROL
1450 || opP->reg < USP
1451 || opP->reg > last_movec_reg)
1452 losing++;
1453 else
1454 {
1455 const enum m68k_register *rp;
1456 for (rp = control_regs; *rp; rp++)
1457 if (*rp == opP->reg)
1458 break;
1459 if (*rp == 0)
1460 losing++;
1461 }
1462 break;
1463
1464 case 'k':
1465 if (opP->mode != IMMED)
1466 losing++;
1467 break;
1468
1469 case 'l':
1470 case 'L':
1471 if (opP->mode == DREG
1472 || opP->mode == AREG
1473 || opP->mode == FPREG)
1474 {
1475 if (s[1] == '8')
1476 losing++;
1477 else
1478 {
1479 switch (opP->mode)
1480 {
1481 case DREG:
1482 opP->mask = 1 << (opP->reg - DATA0);
1483 break;
1484 case AREG:
1485 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1486 break;
1487 case FPREG:
1488 opP->mask = 1 << (opP->reg - FP0 + 16);
1489 break;
1490 default:
1491 abort ();
1492 }
1493 opP->mode = REGLST;
1494 }
1495 }
1496 else if (opP->mode == CONTROL)
1497 {
1498 if (s[1] != '8')
1499 losing++;
1500 else
1501 {
1502 switch (opP->reg)
1503 {
1504 case FPI:
1505 opP->mask = 1 << 24;
1506 break;
1507 case FPS:
1508 opP->mask = 1 << 25;
1509 break;
1510 case FPC:
1511 opP->mask = 1 << 26;
1512 break;
1513 default:
1514 losing++;
1515 break;
1516 }
1517 opP->mode = REGLST;
1518 }
1519 }
1520 else if (opP->mode == ABSL
1521 && opP->disp.size == SIZE_UNSPEC
1522 && opP->disp.exp.X_op == O_constant)
1523 {
1524 /* This is what the MRI REG pseudo-op generates. */
1525 opP->mode = REGLST;
1526 opP->mask = opP->disp.exp.X_add_number;
1527 }
1528 else if (opP->mode != REGLST)
1529 losing++;
1530 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1531 losing++;
1532 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1533 losing++;
1534 break;
1535
1536 case 'M':
1537 if (opP->mode != IMMED)
1538 losing++;
1539 else if (opP->disp.exp.X_op != O_constant
1540 || ! issbyte (opP->disp.exp.X_add_number))
1541 losing++;
1542 else if (! m68k_quick
1543 && instring[3] != 'q'
1544 && instring[4] != 'q')
1545 losing++;
1546 break;
1547
1548 case 'O':
1549 if (opP->mode != DREG
1550 && opP->mode != IMMED
1551 && opP->mode != ABSL)
1552 losing++;
1553 break;
1554
1555 case 'Q':
1556 if (opP->mode != IMMED)
1557 losing++;
1558 else if (opP->disp.exp.X_op != O_constant
1559 || opP->disp.exp.X_add_number < 1
1560 || opP->disp.exp.X_add_number > 8)
1561 losing++;
1562 else if (! m68k_quick
1563 && (strncmp (instring, "add", 3) == 0
1564 || strncmp (instring, "sub", 3) == 0)
1565 && instring[3] != 'q')
1566 losing++;
1567 break;
1568
1569 case 'R':
1570 if (opP->mode != DREG && opP->mode != AREG)
1571 losing++;
1572 break;
1573
1574 case 'r':
1575 if (opP->mode != AINDR
1576 && (opP->mode != BASE
1577 || (opP->reg != 0
1578 && opP->reg != ZADDR0)
1579 || opP->disp.exp.X_op != O_absent
1580 || ((opP->index.reg < DATA0
1581 || opP->index.reg > DATA7)
1582 && (opP->index.reg < ADDR0
1583 || opP->index.reg > ADDR7))
1584 || opP->index.size != SIZE_UNSPEC
1585 || opP->index.scale != 1))
1586 losing++;
1587 break;
1588
1589 case 's':
1590 if (opP->mode != CONTROL
1591 || ! (opP->reg == FPI
1592 || opP->reg == FPS
1593 || opP->reg == FPC))
1594 losing++;
1595 break;
1596
1597 case 'S':
1598 if (opP->mode != CONTROL || opP->reg != SR)
1599 losing++;
1600 break;
1601
1602 case 't':
1603 if (opP->mode != IMMED)
1604 losing++;
1605 else if (opP->disp.exp.X_op != O_constant
1606 || opP->disp.exp.X_add_number < 0
1607 || opP->disp.exp.X_add_number > 7)
1608 losing++;
1609 break;
1610
1611 case 'U':
1612 if (opP->mode != CONTROL || opP->reg != USP)
1613 losing++;
1614 break;
1615
1616 /* JF these are out of order. We could put them
1617 in order if we were willing to put up with
1618 bunches of #ifdef m68851s in the code.
1619
1620 Don't forget that you need these operands
1621 to use 68030 MMU instructions. */
1622 #ifndef NO_68851
1623 /* Memory addressing mode used by pflushr */
1624 case '|':
1625 if (opP->mode == CONTROL
1626 || opP->mode == FPREG
1627 || opP->mode == DREG
1628 || opP->mode == AREG
1629 || opP->mode == REGLST)
1630 losing++;
1631 /* We should accept immediate operands, but they
1632 supposedly have to be quad word, and we don't
1633 handle that. I would like to see what a Motorola
1634 assembler does before doing something here. */
1635 if (opP->mode == IMMED)
1636 losing++;
1637 break;
1638
1639 case 'f':
1640 if (opP->mode != CONTROL
1641 || (opP->reg != SFC && opP->reg != DFC))
1642 losing++;
1643 break;
1644
1645 case '0':
1646 if (opP->mode != CONTROL || opP->reg != TC)
1647 losing++;
1648 break;
1649
1650 case '1':
1651 if (opP->mode != CONTROL || opP->reg != AC)
1652 losing++;
1653 break;
1654
1655 case '2':
1656 if (opP->mode != CONTROL
1657 || (opP->reg != CAL
1658 && opP->reg != VAL
1659 && opP->reg != SCC))
1660 losing++;
1661 break;
1662
1663 case 'V':
1664 if (opP->mode != CONTROL
1665 || opP->reg != VAL)
1666 losing++;
1667 break;
1668
1669 case 'W':
1670 if (opP->mode != CONTROL
1671 || (opP->reg != DRP
1672 && opP->reg != SRP
1673 && opP->reg != CRP))
1674 losing++;
1675 break;
1676
1677 case 'X':
1678 if (opP->mode != CONTROL
1679 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1680 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1681 losing++;
1682 break;
1683
1684 case 'Y':
1685 if (opP->mode != CONTROL || opP->reg != PSR)
1686 losing++;
1687 break;
1688
1689 case 'Z':
1690 if (opP->mode != CONTROL || opP->reg != PCSR)
1691 losing++;
1692 break;
1693 #endif
1694 case 'c':
1695 if (opP->mode != CONTROL
1696 || (opP->reg != NC
1697 && opP->reg != IC
1698 && opP->reg != DC
1699 && opP->reg != BC))
1700 {
1701 losing++;
1702 } /* not a cache specifier. */
1703 break;
1704
1705 case '_':
1706 if (opP->mode != ABSL)
1707 ++losing;
1708 break;
1709
1710 default:
1711 abort ();
1712 } /* switch on type of operand */
1713
1714 if (losing)
1715 break;
1716 } /* for each operand */
1717 } /* if immediately wrong */
1718
1719 if (!losing)
1720 {
1721 break;
1722 } /* got it. */
1723
1724 opcode = opcode->m_next;
1725
1726 if (!opcode)
1727 {
1728 if (ok_arch
1729 && !(ok_arch & current_architecture))
1730 {
1731 char buf[200], *cp;
1732
1733 strcpy (buf,
1734 "invalid instruction for this architecture; needs ");
1735 cp = buf + strlen (buf);
1736 switch (ok_arch)
1737 {
1738 case mfloat:
1739 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1740 break;
1741 case mmmu:
1742 strcpy (cp, "mmu (68030 or 68851)");
1743 break;
1744 case m68020up:
1745 strcpy (cp, "68020 or higher");
1746 break;
1747 case m68000up:
1748 strcpy (cp, "68000 or higher");
1749 break;
1750 case m68010up:
1751 strcpy (cp, "68010 or higher");
1752 break;
1753 default:
1754 {
1755 int got_one = 0, idx;
1756 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1757 idx++)
1758 {
1759 if ((archs[idx].arch & ok_arch)
1760 && ! archs[idx].alias)
1761 {
1762 if (got_one)
1763 {
1764 strcpy (cp, " or ");
1765 cp += strlen (cp);
1766 }
1767 got_one = 1;
1768 strcpy (cp, archs[idx].name);
1769 cp += strlen (cp);
1770 }
1771 }
1772 }
1773 }
1774 cp = xmalloc (strlen (buf) + 1);
1775 strcpy (cp, buf);
1776 the_ins.error = cp;
1777 }
1778 else
1779 the_ins.error = "operands mismatch";
1780 return;
1781 } /* Fell off the end */
1782
1783 losing = 0;
1784 }
1785
1786 /* now assemble it */
1787
1788 the_ins.args = opcode->m_operands;
1789 the_ins.numargs = opcode->m_opnum;
1790 the_ins.numo = opcode->m_codenum;
1791 the_ins.opcode[0] = getone (opcode);
1792 the_ins.opcode[1] = gettwo (opcode);
1793
1794 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1795 {
1796 /* This switch is a doozy.
1797 Watch the first step; its a big one! */
1798 switch (s[0])
1799 {
1800
1801 case '*':
1802 case '~':
1803 case '%':
1804 case ';':
1805 case '@':
1806 case '!':
1807 case '&':
1808 case '$':
1809 case '?':
1810 case '/':
1811 case '<':
1812 case '>':
1813 case 'm':
1814 case 'n':
1815 case 'o':
1816 case 'p':
1817 case 'q':
1818 case 'v':
1819 #ifndef NO_68851
1820 case '|':
1821 #endif
1822 switch (opP->mode)
1823 {
1824 case IMMED:
1825 tmpreg = 0x3c; /* 7.4 */
1826 if (strchr ("bwl", s[1]))
1827 nextword = get_num (&opP->disp, 80);
1828 else
1829 nextword = get_num (&opP->disp, 0);
1830 if (isvar (&opP->disp))
1831 add_fix (s[1], &opP->disp, 0, 0);
1832 switch (s[1])
1833 {
1834 case 'b':
1835 if (!isbyte (nextword))
1836 opP->error = "operand out of range";
1837 addword (nextword);
1838 baseo = 0;
1839 break;
1840 case 'w':
1841 if (!isword (nextword))
1842 opP->error = "operand out of range";
1843 addword (nextword);
1844 baseo = 0;
1845 break;
1846 case 'W':
1847 if (!issword (nextword))
1848 opP->error = "operand out of range";
1849 addword (nextword);
1850 baseo = 0;
1851 break;
1852 case 'l':
1853 addword (nextword >> 16);
1854 addword (nextword);
1855 baseo = 0;
1856 break;
1857
1858 case 'f':
1859 baseo = 2;
1860 outro = 8;
1861 break;
1862 case 'F':
1863 baseo = 4;
1864 outro = 11;
1865 break;
1866 case 'x':
1867 baseo = 6;
1868 outro = 15;
1869 break;
1870 case 'p':
1871 baseo = 6;
1872 outro = -1;
1873 break;
1874 default:
1875 abort ();
1876 }
1877 if (!baseo)
1878 break;
1879
1880 /* We gotta put out some float */
1881 if (op (&opP->disp) != O_big)
1882 {
1883 valueT val;
1884 int gencnt;
1885
1886 /* Can other cases happen here? */
1887 if (op (&opP->disp) != O_constant)
1888 abort ();
1889
1890 val = (valueT) offs (&opP->disp);
1891 gencnt = 0;
1892 do
1893 {
1894 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1895 val >>= LITTLENUM_NUMBER_OF_BITS;
1896 ++gencnt;
1897 }
1898 while (val != 0);
1899 offs (&opP->disp) = gencnt;
1900 }
1901 if (offs (&opP->disp) > 0)
1902 {
1903 if (offs (&opP->disp) > baseo)
1904 {
1905 as_warn ("Bignum too big for %c format; truncated",
1906 s[1]);
1907 offs (&opP->disp) = baseo;
1908 }
1909 baseo -= offs (&opP->disp);
1910 while (baseo--)
1911 addword (0);
1912 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1913 offs (&opP->disp)--;
1914 --wordp)
1915 addword (*wordp);
1916 break;
1917 }
1918 gen_to_words (words, baseo, (long) outro);
1919 for (wordp = words; baseo--; wordp++)
1920 addword (*wordp);
1921 break;
1922 case DREG:
1923 tmpreg = opP->reg - DATA; /* 0.dreg */
1924 break;
1925 case AREG:
1926 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1927 break;
1928 case AINDR:
1929 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1930 break;
1931 case ADEC:
1932 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1933 break;
1934 case AINC:
1935 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1936 break;
1937 case DISP:
1938
1939 nextword = get_num (&opP->disp, 80);
1940
1941 if (opP->reg == PC
1942 && ! isvar (&opP->disp)
1943 && m68k_abspcadd)
1944 {
1945 opP->disp.exp.X_op = O_symbol;
1946 #ifndef BFD_ASSEMBLER
1947 opP->disp.exp.X_add_symbol = &abs_symbol;
1948 #else
1949 opP->disp.exp.X_add_symbol =
1950 section_symbol (absolute_section);
1951 #endif
1952 }
1953
1954 /* Force into index mode. Hope this works */
1955
1956 /* We do the first bit for 32-bit displacements, and the
1957 second bit for 16 bit ones. It is possible that we
1958 should make the default be WORD instead of LONG, but
1959 I think that'd break GCC, so we put up with a little
1960 inefficiency for the sake of working output. */
1961
1962 if (!issword (nextword)
1963 || (isvar (&opP->disp)
1964 && ((opP->disp.size == SIZE_UNSPEC
1965 && flag_short_refs == 0
1966 && cpu_of_arch (current_architecture) >= m68020)
1967 || opP->disp.size == SIZE_LONG)))
1968 {
1969 if (cpu_of_arch (current_architecture) < m68020)
1970 opP->error =
1971 "displacement too large for this architecture; needs 68020 or higher";
1972 if (opP->reg == PC)
1973 tmpreg = 0x3B; /* 7.3 */
1974 else
1975 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1976 if (isvar (&opP->disp))
1977 {
1978 if (opP->reg == PC)
1979 {
1980 if (opP->disp.size == SIZE_LONG
1981 #ifdef OBJ_ELF
1982 /* If the displacement needs pic
1983 relocation it cannot be relaxed. */
1984 || opP->disp.pic_reloc != pic_none
1985 #endif
1986 )
1987 {
1988 addword (0x0170);
1989 add_fix ('l', &opP->disp, 1, 2);
1990 }
1991 else
1992 {
1993 add_frag (adds (&opP->disp),
1994 offs (&opP->disp),
1995 TAB (PCLEA, SZ_UNDEF));
1996 break;
1997 }
1998 }
1999 else
2000 {
2001 addword (0x0170);
2002 add_fix ('l', &opP->disp, 0, 0);
2003 }
2004 }
2005 else
2006 addword (0x0170);
2007 addword (nextword >> 16);
2008 }
2009 else
2010 {
2011 if (opP->reg == PC)
2012 tmpreg = 0x3A; /* 7.2 */
2013 else
2014 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2015
2016 if (isvar (&opP->disp))
2017 {
2018 if (opP->reg == PC)
2019 {
2020 add_fix ('w', &opP->disp, 1, 0);
2021 }
2022 else
2023 add_fix ('w', &opP->disp, 0, 0);
2024 }
2025 }
2026 addword (nextword);
2027 break;
2028
2029 case POST:
2030 case PRE:
2031 case BASE:
2032 nextword = 0;
2033 baseo = get_num (&opP->disp, 80);
2034 if (opP->mode == POST || opP->mode == PRE)
2035 outro = get_num (&opP->odisp, 80);
2036 /* Figure out the `addressing mode'.
2037 Also turn on the BASE_DISABLE bit, if needed. */
2038 if (opP->reg == PC || opP->reg == ZPC)
2039 {
2040 tmpreg = 0x3b; /* 7.3 */
2041 if (opP->reg == ZPC)
2042 nextword |= 0x80;
2043 }
2044 else if (opP->reg == 0)
2045 {
2046 nextword |= 0x80;
2047 tmpreg = 0x30; /* 6.garbage */
2048 }
2049 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2050 {
2051 nextword |= 0x80;
2052 tmpreg = 0x30 + opP->reg - ZADDR0;
2053 }
2054 else
2055 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2056
2057 siz1 = opP->disp.size;
2058 if (opP->mode == POST || opP->mode == PRE)
2059 siz2 = opP->odisp.size;
2060 else
2061 siz2 = SIZE_UNSPEC;
2062
2063 /* Index register stuff */
2064 if (opP->index.reg != 0
2065 && opP->index.reg >= DATA
2066 && opP->index.reg <= ADDR7)
2067 {
2068 nextword |= (opP->index.reg - DATA) << 12;
2069
2070 if (opP->index.size == SIZE_LONG
2071 || (opP->index.size == SIZE_UNSPEC
2072 && m68k_index_width_default == SIZE_LONG))
2073 nextword |= 0x800;
2074
2075 if ((opP->index.scale != 1
2076 && cpu_of_arch (current_architecture) < m68020)
2077 || (opP->index.scale == 8
2078 && current_architecture == mcf5200))
2079 {
2080 opP->error =
2081 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2082 }
2083
2084 switch (opP->index.scale)
2085 {
2086 case 1:
2087 break;
2088 case 2:
2089 nextword |= 0x200;
2090 break;
2091 case 4:
2092 nextword |= 0x400;
2093 break;
2094 case 8:
2095 nextword |= 0x600;
2096 break;
2097 default:
2098 abort ();
2099 }
2100 /* IF its simple,
2101 GET US OUT OF HERE! */
2102
2103 /* Must be INDEX, with an index register. Address
2104 register cannot be ZERO-PC, and either :b was
2105 forced, or we know it will fit. For a 68000 or
2106 68010, force this mode anyways, because the
2107 larger modes aren't supported. */
2108 if (opP->mode == BASE
2109 && ((opP->reg >= ADDR0
2110 && opP->reg <= ADDR7)
2111 || opP->reg == PC))
2112 {
2113 if (siz1 == SIZE_BYTE
2114 || cpu_of_arch (current_architecture) < m68020
2115 || (siz1 == SIZE_UNSPEC
2116 && ! isvar (&opP->disp)
2117 && issbyte (baseo)))
2118 {
2119 nextword += baseo & 0xff;
2120 addword (nextword);
2121 if (isvar (&opP->disp))
2122 {
2123 /* Do a byte relocation. If it doesn't
2124 fit (possible on m68000) let the
2125 fixup processing complain later. */
2126 if (opP->reg == PC)
2127 add_fix ('B', &opP->disp, 1, 1);
2128 else
2129 add_fix ('B', &opP->disp, 0, 0);
2130 }
2131 else if (siz1 != SIZE_BYTE)
2132 {
2133 if (siz1 != SIZE_UNSPEC)
2134 as_warn ("Forcing byte displacement");
2135 if (! issbyte (baseo))
2136 opP->error = "byte displacement out of range";
2137 }
2138
2139 break;
2140 }
2141 else if (siz1 == SIZE_UNSPEC
2142 && opP->reg == PC
2143 && isvar (&opP->disp)
2144 && subs (&opP->disp) == NULL
2145 #ifdef OBJ_ELF
2146 /* If the displacement needs pic
2147 relocation it cannot be relaxed. */
2148 && opP->disp.pic_reloc == pic_none
2149 #endif
2150 )
2151 {
2152 /* The code in md_convert_frag_1 needs to be
2153 able to adjust nextword. Call frag_grow
2154 to ensure that we have enough space in
2155 the frag obstack to make all the bytes
2156 contiguous. */
2157 frag_grow (14);
2158 nextword += baseo & 0xff;
2159 addword (nextword);
2160 add_frag (adds (&opP->disp), offs (&opP->disp),
2161 TAB (PCINDEX, SZ_UNDEF));
2162
2163 break;
2164 }
2165 }
2166 }
2167 else
2168 {
2169 nextword |= 0x40; /* No index reg */
2170 if (opP->index.reg >= ZDATA0
2171 && opP->index.reg <= ZDATA7)
2172 nextword |= (opP->index.reg - ZDATA0) << 12;
2173 else if (opP->index.reg >= ZADDR0
2174 || opP->index.reg <= ZADDR7)
2175 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2176 }
2177
2178 /* It isn't simple. */
2179
2180 if (cpu_of_arch (current_architecture) < m68020)
2181 opP->error =
2182 "invalid operand mode for this architecture; needs 68020 or higher";
2183
2184 nextword |= 0x100;
2185 /* If the guy specified a width, we assume that it is
2186 wide enough. Maybe it isn't. If so, we lose. */
2187 switch (siz1)
2188 {
2189 case SIZE_UNSPEC:
2190 if (isvar (&opP->disp)
2191 ? m68k_rel32
2192 : ! issword (baseo))
2193 {
2194 siz1 = SIZE_LONG;
2195 nextword |= 0x30;
2196 }
2197 else if (! isvar (&opP->disp) && baseo == 0)
2198 nextword |= 0x10;
2199 else
2200 {
2201 nextword |= 0x20;
2202 siz1 = SIZE_WORD;
2203 }
2204 break;
2205 case SIZE_BYTE:
2206 as_warn (":b not permitted; defaulting to :w");
2207 /* Fall through. */
2208 case SIZE_WORD:
2209 nextword |= 0x20;
2210 break;
2211 case SIZE_LONG:
2212 nextword |= 0x30;
2213 break;
2214 }
2215
2216 /* Figure out innner displacement stuff */
2217 if (opP->mode == POST || opP->mode == PRE)
2218 {
2219 if (cpu_of_arch (current_architecture) & cpu32)
2220 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2221 switch (siz2)
2222 {
2223 case SIZE_UNSPEC:
2224 if (isvar (&opP->odisp)
2225 ? m68k_rel32
2226 : ! issword (outro))
2227 {
2228 siz2 = SIZE_LONG;
2229 nextword |= 0x3;
2230 }
2231 else if (! isvar (&opP->odisp) && outro == 0)
2232 nextword |= 0x1;
2233 else
2234 {
2235 nextword |= 0x2;
2236 siz2 = SIZE_WORD;
2237 }
2238 break;
2239 case 1:
2240 as_warn (":b not permitted; defaulting to :w");
2241 /* Fall through. */
2242 case 2:
2243 nextword |= 0x2;
2244 break;
2245 case 3:
2246 nextword |= 0x3;
2247 break;
2248 }
2249 if (opP->mode == POST
2250 && (nextword & 0x40) == 0)
2251 nextword |= 0x04;
2252 }
2253 addword (nextword);
2254
2255 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2256 {
2257 if (opP->reg == PC || opP->reg == ZPC)
2258 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2259 else
2260 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2261 }
2262 if (siz1 == SIZE_LONG)
2263 addword (baseo >> 16);
2264 if (siz1 != SIZE_UNSPEC)
2265 addword (baseo);
2266
2267 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2268 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2269 if (siz2 == SIZE_LONG)
2270 addword (outro >> 16);
2271 if (siz2 != SIZE_UNSPEC)
2272 addword (outro);
2273
2274 break;
2275
2276 case ABSL:
2277 nextword = get_num (&opP->disp, 80);
2278 switch (opP->disp.size)
2279 {
2280 default:
2281 abort ();
2282 case SIZE_UNSPEC:
2283 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2284 {
2285 tmpreg = 0x38; /* 7.0 */
2286 addword (nextword);
2287 break;
2288 }
2289 /* Don't generate pc relative code on 68010 and
2290 68000. */
2291 if (isvar (&opP->disp)
2292 && !subs (&opP->disp)
2293 && adds (&opP->disp)
2294 #ifdef OBJ_ELF
2295 /* If the displacement needs pic relocation it
2296 cannot be relaxed. */
2297 && opP->disp.pic_reloc == pic_none
2298 #endif
2299 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2300 && HAVE_LONG_BRANCH(current_architecture)
2301 && !flag_long_jumps
2302 && !strchr ("~%&$?", s[0]))
2303 {
2304 tmpreg = 0x3A; /* 7.2 */
2305 add_frag (adds (&opP->disp),
2306 offs (&opP->disp),
2307 TAB (PCREL, SZ_UNDEF));
2308 break;
2309 }
2310 /* Fall through into long */
2311 case SIZE_LONG:
2312 if (isvar (&opP->disp))
2313 add_fix ('l', &opP->disp, 0, 0);
2314
2315 tmpreg = 0x39;/* 7.1 mode */
2316 addword (nextword >> 16);
2317 addword (nextword);
2318 break;
2319
2320 case SIZE_BYTE:
2321 as_bad ("unsupported byte value; use a different suffix");
2322 /* Fall through. */
2323 case SIZE_WORD: /* Word */
2324 if (isvar (&opP->disp))
2325 add_fix ('w', &opP->disp, 0, 0);
2326
2327 tmpreg = 0x38;/* 7.0 mode */
2328 addword (nextword);
2329 break;
2330 }
2331 break;
2332 case CONTROL:
2333 case FPREG:
2334 default:
2335 as_bad ("unknown/incorrect operand");
2336 /* abort(); */
2337 }
2338 install_gen_operand (s[1], tmpreg);
2339 break;
2340
2341 case '#':
2342 case '^':
2343 switch (s[1])
2344 { /* JF: I hate floating point! */
2345 case 'j':
2346 tmpreg = 70;
2347 break;
2348 case '8':
2349 tmpreg = 20;
2350 break;
2351 case 'C':
2352 tmpreg = 50;
2353 break;
2354 case '3':
2355 default:
2356 tmpreg = 80;
2357 break;
2358 }
2359 tmpreg = get_num (&opP->disp, tmpreg);
2360 if (isvar (&opP->disp))
2361 add_fix (s[1], &opP->disp, 0, 0);
2362 switch (s[1])
2363 {
2364 case 'b': /* Danger: These do no check for
2365 certain types of overflow.
2366 user beware! */
2367 if (!isbyte (tmpreg))
2368 opP->error = "out of range";
2369 insop (tmpreg, opcode);
2370 if (isvar (&opP->disp))
2371 the_ins.reloc[the_ins.nrel - 1].n =
2372 (opcode->m_codenum) * 2 + 1;
2373 break;
2374 case 'B':
2375 if (!issbyte (tmpreg))
2376 opP->error = "out of range";
2377 opcode->m_opcode |= tmpreg;
2378 if (isvar (&opP->disp))
2379 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2380 break;
2381 case 'w':
2382 if (!isword (tmpreg))
2383 opP->error = "out of range";
2384 insop (tmpreg, opcode);
2385 if (isvar (&opP->disp))
2386 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2387 break;
2388 case 'W':
2389 if (!issword (tmpreg))
2390 opP->error = "out of range";
2391 insop (tmpreg, opcode);
2392 if (isvar (&opP->disp))
2393 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2394 break;
2395 case 'l':
2396 /* Because of the way insop works, we put these two out
2397 backwards. */
2398 insop (tmpreg, opcode);
2399 insop (tmpreg >> 16, opcode);
2400 if (isvar (&opP->disp))
2401 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2402 break;
2403 case '3':
2404 tmpreg &= 0xFF;
2405 case '8':
2406 case 'C':
2407 case 'j':
2408 install_operand (s[1], tmpreg);
2409 break;
2410 default:
2411 abort ();
2412 }
2413 break;
2414
2415 case '+':
2416 case '-':
2417 case 'A':
2418 case 'a':
2419 install_operand (s[1], opP->reg - ADDR);
2420 break;
2421
2422 case 'B':
2423 tmpreg = get_num (&opP->disp, 80);
2424 switch (s[1])
2425 {
2426 case 'B':
2427 /* The pc_fix argument winds up in fx_pcrel_adjust,
2428 which is a char, and may therefore be unsigned. We
2429 want to pass -1, but we pass 64 instead, and convert
2430 back in md_pcrel_from. */
2431 add_fix ('B', &opP->disp, 1, 64);
2432 break;
2433 case 'W':
2434 add_fix ('w', &opP->disp, 1, 0);
2435 addword (0);
2436 break;
2437 case 'L':
2438 long_branch:
2439 if (!HAVE_LONG_BRANCH(current_architecture))
2440 as_warn ("Can't use long branches on 68000/68010/5200");
2441 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2442 add_fix ('l', &opP->disp, 1, 0);
2443 addword (0);
2444 addword (0);
2445 break;
2446 case 'g':
2447 if (subs (&opP->disp)) /* We can't relax it */
2448 goto long_branch;
2449
2450 #ifdef OBJ_ELF
2451 /* If the displacement needs pic relocation it cannot be
2452 relaxed. */
2453 if (opP->disp.pic_reloc != pic_none)
2454 goto long_branch;
2455 #endif
2456
2457 /* This could either be a symbol, or an absolute
2458 address. No matter, the frag hacking will finger it
2459 out. Not quite: it can't switch from BRANCH to
2460 BCC68000 for the case where opnd is absolute (it
2461 needs to use the 68000 hack since no conditional abs
2462 jumps). */
2463 if (( !HAVE_LONG_BRANCH(current_architecture)
2464 || (0 == adds (&opP->disp)))
2465 && (the_ins.opcode[0] >= 0x6200)
2466 && (the_ins.opcode[0] <= 0x6f00))
2467 add_frag (adds (&opP->disp), offs (&opP->disp),
2468 TAB (BCC68000, SZ_UNDEF));
2469 else
2470 add_frag (adds (&opP->disp), offs (&opP->disp),
2471 TAB (ABRANCH, SZ_UNDEF));
2472 break;
2473 case 'w':
2474 if (isvar (&opP->disp))
2475 {
2476 #if 1
2477 /* check for DBcc instruction */
2478 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2479 {
2480 /* size varies if patch */
2481 /* needed for long form */
2482 add_frag (adds (&opP->disp), offs (&opP->disp),
2483 TAB (DBCC, SZ_UNDEF));
2484 break;
2485 }
2486 #endif
2487 add_fix ('w', &opP->disp, 1, 0);
2488 }
2489 addword (0);
2490 break;
2491 case 'C': /* Fixed size LONG coproc branches */
2492 add_fix ('l', &opP->disp, 1, 0);
2493 addword (0);
2494 addword (0);
2495 break;
2496 case 'c': /* Var size Coprocesssor branches */
2497 if (subs (&opP->disp))
2498 {
2499 add_fix ('l', &opP->disp, 1, 0);
2500 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2501 }
2502 else if (adds (&opP->disp))
2503 add_frag (adds (&opP->disp), offs (&opP->disp),
2504 TAB (FBRANCH, SZ_UNDEF));
2505 else
2506 {
2507 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2508 TAB(FBRANCH,SHORT)); */
2509 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2510 add_fix ('l', &opP->disp, 1, 0);
2511 addword (0);
2512 addword (0);
2513 }
2514 break;
2515 default:
2516 abort ();
2517 }
2518 break;
2519
2520 case 'C': /* Ignore it */
2521 break;
2522
2523 case 'd': /* JF this is a kludge */
2524 install_operand ('s', opP->reg - ADDR);
2525 tmpreg = get_num (&opP->disp, 80);
2526 if (!issword (tmpreg))
2527 {
2528 as_warn ("Expression out of range, using 0");
2529 tmpreg = 0;
2530 }
2531 addword (tmpreg);
2532 break;
2533
2534 case 'D':
2535 install_operand (s[1], opP->reg - DATA);
2536 break;
2537
2538 case 'F':
2539 install_operand (s[1], opP->reg - FP0);
2540 break;
2541
2542 case 'I':
2543 tmpreg = opP->reg - COP0;
2544 install_operand (s[1], tmpreg);
2545 break;
2546
2547 case 'J': /* JF foo */
2548 switch (opP->reg)
2549 {
2550 case SFC:
2551 tmpreg = 0x000;
2552 break;
2553 case DFC:
2554 tmpreg = 0x001;
2555 break;
2556 case CACR:
2557 tmpreg = 0x002;
2558 break;
2559 case TC:
2560 tmpreg = 0x003;
2561 break;
2562 case ITT0:
2563 tmpreg = 0x004;
2564 break;
2565 case ITT1:
2566 tmpreg = 0x005;
2567 break;
2568 case DTT0:
2569 tmpreg = 0x006;
2570 break;
2571 case DTT1:
2572 tmpreg = 0x007;
2573 break;
2574 case BUSCR:
2575 tmpreg = 0x008;
2576 break;
2577
2578 case USP:
2579 tmpreg = 0x800;
2580 break;
2581 case VBR:
2582 tmpreg = 0x801;
2583 break;
2584 case CAAR:
2585 tmpreg = 0x802;
2586 break;
2587 case MSP:
2588 tmpreg = 0x803;
2589 break;
2590 case ISP:
2591 tmpreg = 0x804;
2592 break;
2593 case MMUSR:
2594 tmpreg = 0x805;
2595 break;
2596 case URP:
2597 tmpreg = 0x806;
2598 break;
2599 case SRP:
2600 tmpreg = 0x807;
2601 break;
2602 case PCR:
2603 tmpreg = 0x808;
2604 break;
2605 case ROMBAR:
2606 tmpreg = 0xC00;
2607 break;
2608 case RAMBAR0:
2609 tmpreg = 0xC04;
2610 break;
2611 case RAMBAR1:
2612 tmpreg = 0xC05;
2613 break;
2614 case MBAR:
2615 tmpreg = 0xC0F;
2616 break;
2617 default:
2618 abort ();
2619 }
2620 install_operand (s[1], tmpreg);
2621 break;
2622
2623 case 'k':
2624 tmpreg = get_num (&opP->disp, 55);
2625 install_operand (s[1], tmpreg & 0x7f);
2626 break;
2627
2628 case 'l':
2629 tmpreg = opP->mask;
2630 if (s[1] == 'w')
2631 {
2632 if (tmpreg & 0x7FF0000)
2633 as_bad ("Floating point register in register list");
2634 insop (reverse_16_bits (tmpreg), opcode);
2635 }
2636 else
2637 {
2638 if (tmpreg & 0x700FFFF)
2639 as_bad ("Wrong register in floating-point reglist");
2640 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2641 }
2642 break;
2643
2644 case 'L':
2645 tmpreg = opP->mask;
2646 if (s[1] == 'w')
2647 {
2648 if (tmpreg & 0x7FF0000)
2649 as_bad ("Floating point register in register list");
2650 insop (tmpreg, opcode);
2651 }
2652 else if (s[1] == '8')
2653 {
2654 if (tmpreg & 0x0FFFFFF)
2655 as_bad ("incorrect register in reglist");
2656 install_operand (s[1], tmpreg >> 24);
2657 }
2658 else
2659 {
2660 if (tmpreg & 0x700FFFF)
2661 as_bad ("wrong register in floating-point reglist");
2662 else
2663 install_operand (s[1], tmpreg >> 16);
2664 }
2665 break;
2666
2667 case 'M':
2668 install_operand (s[1], get_num (&opP->disp, 60));
2669 break;
2670
2671 case 'O':
2672 tmpreg = ((opP->mode == DREG)
2673 ? 0x20 + opP->reg - DATA
2674 : (get_num (&opP->disp, 40) & 0x1F));
2675 install_operand (s[1], tmpreg);
2676 break;
2677
2678 case 'Q':
2679 tmpreg = get_num (&opP->disp, 10);
2680 if (tmpreg == 8)
2681 tmpreg = 0;
2682 install_operand (s[1], tmpreg);
2683 break;
2684
2685 case 'R':
2686 /* This depends on the fact that ADDR registers are eight
2687 more than their corresponding DATA regs, so the result
2688 will have the ADDR_REG bit set */
2689 install_operand (s[1], opP->reg - DATA);
2690 break;
2691
2692 case 'r':
2693 if (opP->mode == AINDR)
2694 install_operand (s[1], opP->reg - DATA);
2695 else
2696 install_operand (s[1], opP->index.reg - DATA);
2697 break;
2698
2699 case 's':
2700 if (opP->reg == FPI)
2701 tmpreg = 0x1;
2702 else if (opP->reg == FPS)
2703 tmpreg = 0x2;
2704 else if (opP->reg == FPC)
2705 tmpreg = 0x4;
2706 else
2707 abort ();
2708 install_operand (s[1], tmpreg);
2709 break;
2710
2711 case 'S': /* Ignore it */
2712 break;
2713
2714 case 'T':
2715 install_operand (s[1], get_num (&opP->disp, 30));
2716 break;
2717
2718 case 'U': /* Ignore it */
2719 break;
2720
2721 case 'c':
2722 switch (opP->reg)
2723 {
2724 case NC:
2725 tmpreg = 0;
2726 break;
2727 case DC:
2728 tmpreg = 1;
2729 break;
2730 case IC:
2731 tmpreg = 2;
2732 break;
2733 case BC:
2734 tmpreg = 3;
2735 break;
2736 default:
2737 as_fatal ("failed sanity check");
2738 } /* switch on cache token */
2739 install_operand (s[1], tmpreg);
2740 break;
2741 #ifndef NO_68851
2742 /* JF: These are out of order, I fear. */
2743 case 'f':
2744 switch (opP->reg)
2745 {
2746 case SFC:
2747 tmpreg = 0;
2748 break;
2749 case DFC:
2750 tmpreg = 1;
2751 break;
2752 default:
2753 abort ();
2754 }
2755 install_operand (s[1], tmpreg);
2756 break;
2757
2758 case '0':
2759 case '1':
2760 case '2':
2761 switch (opP->reg)
2762 {
2763 case TC:
2764 tmpreg = 0;
2765 break;
2766 case CAL:
2767 tmpreg = 4;
2768 break;
2769 case VAL:
2770 tmpreg = 5;
2771 break;
2772 case SCC:
2773 tmpreg = 6;
2774 break;
2775 case AC:
2776 tmpreg = 7;
2777 break;
2778 default:
2779 abort ();
2780 }
2781 install_operand (s[1], tmpreg);
2782 break;
2783
2784 case 'V':
2785 if (opP->reg == VAL)
2786 break;
2787 abort ();
2788
2789 case 'W':
2790 switch (opP->reg)
2791 {
2792 case DRP:
2793 tmpreg = 1;
2794 break;
2795 case SRP:
2796 tmpreg = 2;
2797 break;
2798 case CRP:
2799 tmpreg = 3;
2800 break;
2801 default:
2802 abort ();
2803 }
2804 install_operand (s[1], tmpreg);
2805 break;
2806
2807 case 'X':
2808 switch (opP->reg)
2809 {
2810 case BAD:
2811 case BAD + 1:
2812 case BAD + 2:
2813 case BAD + 3:
2814 case BAD + 4:
2815 case BAD + 5:
2816 case BAD + 6:
2817 case BAD + 7:
2818 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2819 break;
2820
2821 case BAC:
2822 case BAC + 1:
2823 case BAC + 2:
2824 case BAC + 3:
2825 case BAC + 4:
2826 case BAC + 5:
2827 case BAC + 6:
2828 case BAC + 7:
2829 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2830 break;
2831
2832 default:
2833 abort ();
2834 }
2835 install_operand (s[1], tmpreg);
2836 break;
2837 case 'Y':
2838 know (opP->reg == PSR);
2839 break;
2840 case 'Z':
2841 know (opP->reg == PCSR);
2842 break;
2843 #endif /* m68851 */
2844 case '3':
2845 switch (opP->reg)
2846 {
2847 case TT0:
2848 tmpreg = 2;
2849 break;
2850 case TT1:
2851 tmpreg = 3;
2852 break;
2853 default:
2854 abort ();
2855 }
2856 install_operand (s[1], tmpreg);
2857 break;
2858 case 't':
2859 tmpreg = get_num (&opP->disp, 20);
2860 install_operand (s[1], tmpreg);
2861 break;
2862 case '_': /* used only for move16 absolute 32-bit address */
2863 tmpreg = get_num (&opP->disp, 80);
2864 addword (tmpreg >> 16);
2865 addword (tmpreg & 0xFFFF);
2866 break;
2867 default:
2868 abort ();
2869 }
2870 }
2871
2872 /* By the time whe get here (FINALLY) the_ins contains the complete
2873 instruction, ready to be emitted. . . */
2874 }
2875
2876 static int
2877 reverse_16_bits (in)
2878 int in;
2879 {
2880 int out = 0;
2881 int n;
2882
2883 static int mask[16] =
2884 {
2885 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2886 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2887 };
2888 for (n = 0; n < 16; n++)
2889 {
2890 if (in & mask[n])
2891 out |= mask[15 - n];
2892 }
2893 return out;
2894 } /* reverse_16_bits() */
2895
2896 static int
2897 reverse_8_bits (in)
2898 int in;
2899 {
2900 int out = 0;
2901 int n;
2902
2903 static int mask[8] =
2904 {
2905 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2906 };
2907
2908 for (n = 0; n < 8; n++)
2909 {
2910 if (in & mask[n])
2911 out |= mask[7 - n];
2912 }
2913 return out;
2914 } /* reverse_8_bits() */
2915
2916 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2917 (that value is chosen in the frag_var call in md_assemble). TYPE
2918 is the subtype of the frag to be generated; its primary type is
2919 rs_machine_dependent.
2920
2921 The TYPE parameter is also used by md_convert_frag_1 and
2922 md_estimate_size_before_relax. The appropriate type of fixup will
2923 be emitted by md_convert_frag_1.
2924
2925 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2926 static void
2927 install_operand (mode, val)
2928 int mode;
2929 int val;
2930 {
2931 switch (mode)
2932 {
2933 case 's':
2934 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2935 break;
2936 case 'd':
2937 the_ins.opcode[0] |= val << 9;
2938 break;
2939 case '1':
2940 the_ins.opcode[1] |= val << 12;
2941 break;
2942 case '2':
2943 the_ins.opcode[1] |= val << 6;
2944 break;
2945 case '3':
2946 the_ins.opcode[1] |= val;
2947 break;
2948 case '4':
2949 the_ins.opcode[2] |= val << 12;
2950 break;
2951 case '5':
2952 the_ins.opcode[2] |= val << 6;
2953 break;
2954 case '6':
2955 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2956 three words long! */
2957 the_ins.numo++;
2958 the_ins.opcode[2] |= val;
2959 break;
2960 case '7':
2961 the_ins.opcode[1] |= val << 7;
2962 break;
2963 case '8':
2964 the_ins.opcode[1] |= val << 10;
2965 break;
2966 #ifndef NO_68851
2967 case '9':
2968 the_ins.opcode[1] |= val << 5;
2969 break;
2970 #endif
2971
2972 case 't':
2973 the_ins.opcode[1] |= (val << 10) | (val << 7);
2974 break;
2975 case 'D':
2976 the_ins.opcode[1] |= (val << 12) | val;
2977 break;
2978 case 'g':
2979 the_ins.opcode[0] |= val = 0xff;
2980 break;
2981 case 'i':
2982 the_ins.opcode[0] |= val << 9;
2983 break;
2984 case 'C':
2985 the_ins.opcode[1] |= val;
2986 break;
2987 case 'j':
2988 the_ins.opcode[1] |= val;
2989 the_ins.numo++; /* What a hack */
2990 break;
2991 case 'k':
2992 the_ins.opcode[1] |= val << 4;
2993 break;
2994 case 'b':
2995 case 'w':
2996 case 'W':
2997 case 'l':
2998 break;
2999 case 'e':
3000 the_ins.opcode[0] |= (val << 6);
3001 break;
3002 case 'L':
3003 the_ins.opcode[1] = (val >> 16);
3004 the_ins.opcode[2] = val & 0xffff;
3005 break;
3006 case 'c':
3007 default:
3008 as_fatal ("failed sanity check.");
3009 }
3010 } /* install_operand() */
3011
3012 static void
3013 install_gen_operand (mode, val)
3014 int mode;
3015 int val;
3016 {
3017 switch (mode)
3018 {
3019 case 's':
3020 the_ins.opcode[0] |= val;
3021 break;
3022 case 'd':
3023 /* This is a kludge!!! */
3024 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3025 break;
3026 case 'b':
3027 case 'w':
3028 case 'l':
3029 case 'f':
3030 case 'F':
3031 case 'x':
3032 case 'p':
3033 the_ins.opcode[0] |= val;
3034 break;
3035 /* more stuff goes here */
3036 default:
3037 as_fatal ("failed sanity check.");
3038 }
3039 } /* install_gen_operand() */
3040
3041 /*
3042 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3043 * then deal with the bitfield hack.
3044 */
3045
3046 static char *
3047 crack_operand (str, opP)
3048 register char *str;
3049 register struct m68k_op *opP;
3050 {
3051 register int parens;
3052 register int c;
3053 register char *beg_str;
3054 int inquote = 0;
3055
3056 if (!str)
3057 {
3058 return str;
3059 }
3060 beg_str = str;
3061 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3062 {
3063 if (! inquote)
3064 {
3065 if (*str == '(')
3066 parens++;
3067 else if (*str == ')')
3068 {
3069 if (!parens)
3070 { /* ERROR */
3071 opP->error = "Extra )";
3072 return str;
3073 }
3074 --parens;
3075 }
3076 }
3077 if (flag_mri && *str == '\'')
3078 inquote = ! inquote;
3079 }
3080 if (!*str && parens)
3081 { /* ERROR */
3082 opP->error = "Missing )";
3083 return str;
3084 }
3085 c = *str;
3086 *str = '\0';
3087 if (m68k_ip_op (beg_str, opP) != 0)
3088 {
3089 *str = c;
3090 return str;
3091 }
3092 *str = c;
3093 if (c == '}')
3094 c = *++str; /* JF bitfield hack */
3095 if (c)
3096 {
3097 c = *++str;
3098 if (!c)
3099 as_bad ("Missing operand");
3100 }
3101 return str;
3102 }
3103
3104 /* This is the guts of the machine-dependent assembler. STR points to a
3105 machine dependent instruction. This function is supposed to emit
3106 the frags/bytes it assembles to.
3107 */
3108
3109 void
3110 insert_reg (regname, regnum)
3111 const char *regname;
3112 int regnum;
3113 {
3114 char buf[100];
3115 int i;
3116
3117 #ifdef REGISTER_PREFIX
3118 if (!flag_reg_prefix_optional)
3119 {
3120 buf[0] = REGISTER_PREFIX;
3121 strcpy (buf + 1, regname);
3122 regname = buf;
3123 }
3124 #endif
3125
3126 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3127 &zero_address_frag));
3128
3129 for (i = 0; regname[i]; i++)
3130 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3131 buf[i] = '\0';
3132
3133 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3134 &zero_address_frag));
3135 }
3136
3137 struct init_entry
3138 {
3139 const char *name;
3140 int number;
3141 };
3142
3143 static const struct init_entry init_table[] =
3144 {
3145 { "d0", DATA0 },
3146 { "d1", DATA1 },
3147 { "d2", DATA2 },
3148 { "d3", DATA3 },
3149 { "d4", DATA4 },
3150 { "d5", DATA5 },
3151 { "d6", DATA6 },
3152 { "d7", DATA7 },
3153 { "a0", ADDR0 },
3154 { "a1", ADDR1 },
3155 { "a2", ADDR2 },
3156 { "a3", ADDR3 },
3157 { "a4", ADDR4 },
3158 { "a5", ADDR5 },
3159 { "a6", ADDR6 },
3160 { "fp", ADDR6 },
3161 { "a7", ADDR7 },
3162 { "sp", ADDR7 },
3163 { "ssp", ADDR7 },
3164 { "fp0", FP0 },
3165 { "fp1", FP1 },
3166 { "fp2", FP2 },
3167 { "fp3", FP3 },
3168 { "fp4", FP4 },
3169 { "fp5", FP5 },
3170 { "fp6", FP6 },
3171 { "fp7", FP7 },
3172 { "fpi", FPI },
3173 { "fpiar", FPI },
3174 { "fpc", FPI },
3175 { "fps", FPS },
3176 { "fpsr", FPS },
3177 { "fpc", FPC },
3178 { "fpcr", FPC },
3179 { "control", FPC },
3180 { "status", FPS },
3181 { "iaddr", FPI },
3182
3183 { "cop0", COP0 },
3184 { "cop1", COP1 },
3185 { "cop2", COP2 },
3186 { "cop3", COP3 },
3187 { "cop4", COP4 },
3188 { "cop5", COP5 },
3189 { "cop6", COP6 },
3190 { "cop7", COP7 },
3191 { "pc", PC },
3192 { "zpc", ZPC },
3193 { "sr", SR },
3194
3195 { "ccr", CCR },
3196 { "cc", CCR },
3197
3198 /* control registers */
3199 { "sfc", SFC }, /* Source Function Code */
3200 { "sfcr", SFC },
3201 { "dfc", DFC }, /* Destination Function Code */
3202 { "dfcr", DFC },
3203 { "cacr", CACR }, /* Cache Control Register */
3204 { "caar", CAAR }, /* Cache Address Register */
3205
3206 { "usp", USP }, /* User Stack Pointer */
3207 { "vbr", VBR }, /* Vector Base Register */
3208 { "msp", MSP }, /* Master Stack Pointer */
3209 { "isp", ISP }, /* Interrupt Stack Pointer */
3210
3211 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3212 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3213 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3214 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3215
3216 /* 68ec040 versions of same */
3217 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3218 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3219 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3220 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3221
3222 /* mcf5200 versions of same. The ColdFire programmer's reference
3223 manual indicated that the order is 2,3,0,1, but Ken Rose
3224 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3225 { "acr0", ITT0 }, /* Access Control Unit 0 */
3226 { "acr1", ITT1 }, /* Access Control Unit 1 */
3227 { "acr2", DTT0 }, /* Access Control Unit 2 */
3228 { "acr3", DTT1 }, /* Access Control Unit 3 */
3229
3230 { "tc", TC }, /* MMU Translation Control Register */
3231 { "tcr", TC },
3232
3233 { "mmusr", MMUSR }, /* MMU Status Register */
3234 { "srp", SRP }, /* User Root Pointer */
3235 { "urp", URP }, /* Supervisor Root Pointer */
3236
3237 { "buscr", BUSCR },
3238 { "pcr", PCR },
3239
3240 { "rombar", ROMBAR }, /* ROM Base Address Register */
3241 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3242 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3243 { "mbar", MBAR }, /* Module Base Address Register */
3244 /* end of control registers */
3245
3246 { "ac", AC },
3247 { "bc", BC },
3248 { "cal", CAL },
3249 { "crp", CRP },
3250 { "drp", DRP },
3251 { "pcsr", PCSR },
3252 { "psr", PSR },
3253 { "scc", SCC },
3254 { "val", VAL },
3255 { "bad0", BAD0 },
3256 { "bad1", BAD1 },
3257 { "bad2", BAD2 },
3258 { "bad3", BAD3 },
3259 { "bad4", BAD4 },
3260 { "bad5", BAD5 },
3261 { "bad6", BAD6 },
3262 { "bad7", BAD7 },
3263 { "bac0", BAC0 },
3264 { "bac1", BAC1 },
3265 { "bac2", BAC2 },
3266 { "bac3", BAC3 },
3267 { "bac4", BAC4 },
3268 { "bac5", BAC5 },
3269 { "bac6", BAC6 },
3270 { "bac7", BAC7 },
3271
3272 { "ic", IC },
3273 { "dc", DC },
3274 { "nc", NC },
3275
3276 { "tt0", TT0 },
3277 { "tt1", TT1 },
3278 /* 68ec030 versions of same */
3279 { "ac0", TT0 },
3280 { "ac1", TT1 },
3281 /* 68ec030 access control unit, identical to 030 MMU status reg */
3282 { "acusr", PSR },
3283
3284 /* Suppressed data and address registers. */
3285 { "zd0", ZDATA0 },
3286 { "zd1", ZDATA1 },
3287 { "zd2", ZDATA2 },
3288 { "zd3", ZDATA3 },
3289 { "zd4", ZDATA4 },
3290 { "zd5", ZDATA5 },
3291 { "zd6", ZDATA6 },
3292 { "zd7", ZDATA7 },
3293 { "za0", ZADDR0 },
3294 { "za1", ZADDR1 },
3295 { "za2", ZADDR2 },
3296 { "za3", ZADDR3 },
3297 { "za4", ZADDR4 },
3298 { "za5", ZADDR5 },
3299 { "za6", ZADDR6 },
3300 { "za7", ZADDR7 },
3301
3302 { 0, 0 }
3303 };
3304
3305 void
3306 init_regtable ()
3307 {
3308 int i;
3309 for (i = 0; init_table[i].name; i++)
3310 insert_reg (init_table[i].name, init_table[i].number);
3311 }
3312
3313 static int no_68851, no_68881;
3314
3315 #ifdef OBJ_AOUT
3316 /* a.out machine type. Default to 68020. */
3317 int m68k_aout_machtype = 2;
3318 #endif
3319
3320 void
3321 md_assemble (str)
3322 char *str;
3323 {
3324 const char *er;
3325 short *fromP;
3326 char *toP = NULL;
3327 int m, n = 0;
3328 char *to_beg_P;
3329 int shorts_this_frag;
3330 fixS *fixP;
3331
3332 /* In MRI mode, the instruction and operands are separated by a
3333 space. Anything following the operands is a comment. The label
3334 has already been removed. */
3335 if (flag_mri)
3336 {
3337 char *s;
3338 int fields = 0;
3339 int infield = 0;
3340 int inquote = 0;
3341
3342 for (s = str; *s != '\0'; s++)
3343 {
3344 if ((*s == ' ' || *s == '\t') && ! inquote)
3345 {
3346 if (infield)
3347 {
3348 ++fields;
3349 if (fields >= 2)
3350 {
3351 *s = '\0';
3352 break;
3353 }
3354 infield = 0;
3355 }
3356 }
3357 else
3358 {
3359 if (! infield)
3360 infield = 1;
3361 if (*s == '\'')
3362 inquote = ! inquote;
3363 }
3364 }
3365 }
3366
3367 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3368 m68k_ip (str);
3369 er = the_ins.error;
3370 if (!er)
3371 {
3372 for (n = 0; n < the_ins.numargs; n++)
3373 if (the_ins.operands[n].error)
3374 {
3375 er = the_ins.operands[n].error;
3376 break;
3377 }
3378 }
3379 if (er)
3380 {
3381 as_bad ("%s -- statement `%s' ignored", er, str);
3382 return;
3383 }
3384
3385 /* If there is a current label, record that it marks an instruction. */
3386 if (current_label != NULL)
3387 {
3388 current_label->text = 1;
3389 current_label = NULL;
3390 }
3391
3392 if (the_ins.nfrag == 0)
3393 {
3394 /* No frag hacking involved; just put it out */
3395 toP = frag_more (2 * the_ins.numo);
3396 fromP = &the_ins.opcode[0];
3397 for (m = the_ins.numo; m; --m)
3398 {
3399 md_number_to_chars (toP, (long) (*fromP), 2);
3400 toP += 2;
3401 fromP++;
3402 }
3403 /* put out symbol-dependent info */
3404 for (m = 0; m < the_ins.nrel; m++)
3405 {
3406 switch (the_ins.reloc[m].wid)
3407 {
3408 case 'B':
3409 n = 1;
3410 break;
3411 case 'b':
3412 n = 1;
3413 break;
3414 case '3':
3415 n = 1;
3416 break;
3417 case 'w':
3418 case 'W':
3419 n = 2;
3420 break;
3421 case 'l':
3422 n = 4;
3423 break;
3424 default:
3425 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3426 the_ins.reloc[m].wid);
3427 }
3428
3429 fixP = fix_new_exp (frag_now,
3430 ((toP - frag_now->fr_literal)
3431 - the_ins.numo * 2 + the_ins.reloc[m].n),
3432 n,
3433 &the_ins.reloc[m].exp,
3434 the_ins.reloc[m].pcrel,
3435 get_reloc_code (n, the_ins.reloc[m].pcrel,
3436 the_ins.reloc[m].pic_reloc));
3437 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3438 if (the_ins.reloc[m].wid == 'B')
3439 fixP->fx_signed = 1;
3440 }
3441 return;
3442 }
3443
3444 /* There's some frag hacking */
3445 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3446 {
3447 int wid;
3448
3449 if (n == 0)
3450 wid = 2 * the_ins.fragb[n].fragoff;
3451 else
3452 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3453 toP = frag_more (wid);
3454 to_beg_P = toP;
3455 shorts_this_frag = 0;
3456 for (m = wid / 2; m; --m)
3457 {
3458 md_number_to_chars (toP, (long) (*fromP), 2);
3459 toP += 2;
3460 fromP++;
3461 shorts_this_frag++;
3462 }
3463 for (m = 0; m < the_ins.nrel; m++)
3464 {
3465 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3466 {
3467 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3468 break;
3469 }
3470 wid = the_ins.reloc[m].wid;
3471 if (wid == 0)
3472 continue;
3473 the_ins.reloc[m].wid = 0;
3474 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3475
3476 fixP = fix_new_exp (frag_now,
3477 ((toP - frag_now->fr_literal)
3478 - the_ins.numo * 2 + the_ins.reloc[m].n),
3479 wid,
3480 &the_ins.reloc[m].exp,
3481 the_ins.reloc[m].pcrel,
3482 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3483 the_ins.reloc[m].pic_reloc));
3484 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3485 }
3486 (void) frag_var (rs_machine_dependent, 10, 0,
3487 (relax_substateT) (the_ins.fragb[n].fragty),
3488 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3489 }
3490 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3491 shorts_this_frag = 0;
3492 if (n)
3493 {
3494 toP = frag_more (n * sizeof (short));
3495 while (n--)
3496 {
3497 md_number_to_chars (toP, (long) (*fromP), 2);
3498 toP += 2;
3499 fromP++;
3500 shorts_this_frag++;
3501 }
3502 }
3503 for (m = 0; m < the_ins.nrel; m++)
3504 {
3505 int wid;
3506
3507 wid = the_ins.reloc[m].wid;
3508 if (wid == 0)
3509 continue;
3510 the_ins.reloc[m].wid = 0;
3511 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3512
3513 fixP = fix_new_exp (frag_now,
3514 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3515 - shorts_this_frag * 2),
3516 wid,
3517 &the_ins.reloc[m].exp,
3518 the_ins.reloc[m].pcrel,
3519 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3520 the_ins.reloc[m].pic_reloc));
3521 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3522 }
3523 }
3524
3525 void
3526 md_begin ()
3527 {
3528 /*
3529 * md_begin -- set up hash tables with 68000 instructions.
3530 * similar to what the vax assembler does. ---phr
3531 */
3532 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3533 a copy of it at runtime, adding in the information we want but isn't
3534 there. I think it'd be better to have an awk script hack the table
3535 at compile time. Or even just xstr the table and use it as-is. But
3536 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3537 names. */
3538
3539 register const struct m68k_opcode *ins;
3540 register struct m68k_incant *hack, *slak;
3541 register const char *retval = 0; /* empty string, or error msg text */
3542 register unsigned int i;
3543 register char c;
3544
3545 if (flag_mri)
3546 {
3547 flag_reg_prefix_optional = 1;
3548 m68k_abspcadd = 1;
3549 if (! m68k_rel32_from_cmdline)
3550 m68k_rel32 = 0;
3551 }
3552
3553 op_hash = hash_new ();
3554
3555 obstack_begin (&robyn, 4000);
3556 for (i = 0; i < m68k_numopcodes; i++)
3557 {
3558 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3559 do
3560 {
3561 ins = &m68k_opcodes[i];
3562 /* We *could* ignore insns that don't match our arch here
3563 but just leaving them out of the hash. */
3564 slak->m_operands = ins->args;
3565 slak->m_opnum = strlen (slak->m_operands) / 2;
3566 slak->m_arch = ins->arch;
3567 slak->m_opcode = ins->opcode;
3568 /* This is kludgey */
3569 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3570 if (i + 1 != m68k_numopcodes
3571 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3572 {
3573 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3574 i++;
3575 }
3576 else
3577 slak->m_next = 0;
3578 slak = slak->m_next;
3579 }
3580 while (slak);
3581
3582 retval = hash_insert (op_hash, ins->name, (char *) hack);
3583 if (retval)
3584 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3585 }
3586
3587 for (i = 0; i < m68k_numaliases; i++)
3588 {
3589 const char *name = m68k_opcode_aliases[i].primary;
3590 const char *alias = m68k_opcode_aliases[i].alias;
3591 PTR val = hash_find (op_hash, name);
3592 if (!val)
3593 as_fatal ("Internal Error: Can't find %s in hash table", name);
3594 retval = hash_insert (op_hash, alias, val);
3595 if (retval)
3596 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3597 }
3598
3599 /* In MRI mode, all unsized branches are variable sized. Normally,
3600 they are word sized. */
3601 if (flag_mri)
3602 {
3603 static struct m68k_opcode_alias mri_aliases[] =
3604 {
3605 { "bhi", "jhi", },
3606 { "bls", "jls", },
3607 { "bcc", "jcc", },
3608 { "bcs", "jcs", },
3609 { "bne", "jne", },
3610 { "beq", "jeq", },
3611 { "bvc", "jvc", },
3612 { "bvs", "jvs", },
3613 { "bpl", "jpl", },
3614 { "bmi", "jmi", },
3615 { "bge", "jge", },
3616 { "blt", "jlt", },
3617 { "bgt", "jgt", },
3618 { "ble", "jle", },
3619 { "bra", "jra", },
3620 { "bsr", "jbsr", },
3621 };
3622
3623 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3624 {
3625 const char *name = mri_aliases[i].primary;
3626 const char *alias = mri_aliases[i].alias;
3627 PTR val = hash_find (op_hash, name);
3628 if (!val)
3629 as_fatal ("Internal Error: Can't find %s in hash table", name);
3630 retval = hash_jam (op_hash, alias, val);
3631 if (retval)
3632 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3633 }
3634 }
3635
3636 for (i = 0; i < sizeof (mklower_table); i++)
3637 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3638
3639 for (i = 0; i < sizeof (notend_table); i++)
3640 {
3641 notend_table[i] = 0;
3642 alt_notend_table[i] = 0;
3643 }
3644 notend_table[','] = 1;
3645 notend_table['{'] = 1;
3646 notend_table['}'] = 1;
3647 alt_notend_table['a'] = 1;
3648 alt_notend_table['A'] = 1;
3649 alt_notend_table['d'] = 1;
3650 alt_notend_table['D'] = 1;
3651 alt_notend_table['#'] = 1;
3652 alt_notend_table['&'] = 1;
3653 alt_notend_table['f'] = 1;
3654 alt_notend_table['F'] = 1;
3655 #ifdef REGISTER_PREFIX
3656 alt_notend_table[REGISTER_PREFIX] = 1;
3657 #endif
3658
3659 /* We need to put '(' in alt_notend_table to handle
3660 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3661 */
3662 alt_notend_table['('] = 1;
3663
3664 /* We need to put '@' in alt_notend_table to handle
3665 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3666 */
3667 alt_notend_table['@'] = 1;
3668
3669 /* We need to put digits in alt_notend_table to handle
3670 bfextu %d0{24:1},%d0
3671 */
3672 alt_notend_table['0'] = 1;
3673 alt_notend_table['1'] = 1;
3674 alt_notend_table['2'] = 1;
3675 alt_notend_table['3'] = 1;
3676 alt_notend_table['4'] = 1;
3677 alt_notend_table['5'] = 1;
3678 alt_notend_table['6'] = 1;
3679 alt_notend_table['7'] = 1;
3680 alt_notend_table['8'] = 1;
3681 alt_notend_table['9'] = 1;
3682
3683 #ifndef MIT_SYNTAX_ONLY
3684 /* Insert pseudo ops, these have to go into the opcode table since
3685 gas expects pseudo ops to start with a dot */
3686 {
3687 int n = 0;
3688 while (mote_pseudo_table[n].poc_name)
3689 {
3690 hack = (struct m68k_incant *)
3691 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3692 hash_insert (op_hash,
3693 mote_pseudo_table[n].poc_name, (char *) hack);
3694 hack->m_operands = 0;
3695 hack->m_opnum = n;
3696 n++;
3697 }
3698 }
3699 #endif
3700
3701 init_regtable ();
3702
3703 #ifdef OBJ_ELF
3704 record_alignment (text_section, 2);
3705 record_alignment (data_section, 2);
3706 record_alignment (bss_section, 2);
3707 #endif
3708 }
3709
3710 static void
3711 select_control_regs ()
3712 {
3713 /* Note which set of "movec" control registers is available. */
3714 switch (cpu_of_arch (current_architecture))
3715 {
3716 case m68000:
3717 control_regs = m68000_control_regs;
3718 break;
3719 case m68010:
3720 control_regs = m68010_control_regs;
3721 break;
3722 case m68020:
3723 case m68030:
3724 control_regs = m68020_control_regs;
3725 break;
3726 case m68040:
3727 control_regs = m68040_control_regs;
3728 break;
3729 case m68060:
3730 control_regs = m68060_control_regs;
3731 break;
3732 case cpu32:
3733 control_regs = cpu32_control_regs;
3734 break;
3735 case mcf5200:
3736 control_regs = mcf5200_control_regs;
3737 break;
3738 default:
3739 abort ();
3740 }
3741 }
3742
3743 void
3744 m68k_init_after_args ()
3745 {
3746 if (cpu_of_arch (current_architecture) == 0)
3747 {
3748 int i;
3749 const char *default_cpu = TARGET_CPU;
3750
3751 if (*default_cpu == 'm')
3752 default_cpu++;
3753 for (i = 0; i < n_archs; i++)
3754 if (strcasecmp (default_cpu, archs[i].name) == 0)
3755 break;
3756 if (i == n_archs)
3757 {
3758 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3759 current_architecture |= m68020;
3760 }
3761 else
3762 current_architecture |= archs[i].arch;
3763 }
3764 /* Permit m68881 specification with all cpus; those that can't work
3765 with a coprocessor could be doing emulation. */
3766 if (current_architecture & m68851)
3767 {
3768 if (current_architecture & m68040)
3769 {
3770 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3771 }
3772 }
3773 /* What other incompatibilities could we check for? */
3774
3775 /* Toss in some default assumptions about coprocessors. */
3776 if (!no_68881
3777 && (cpu_of_arch (current_architecture)
3778 /* Can CPU32 have a 68881 coprocessor?? */
3779 & (m68020 | m68030 | cpu32)))
3780 {
3781 current_architecture |= m68881;
3782 }
3783 if (!no_68851
3784 && (cpu_of_arch (current_architecture) & m68020up) != 0
3785 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3786 {
3787 current_architecture |= m68851;
3788 }
3789 if (no_68881 && (current_architecture & m68881))
3790 as_bad ("options for 68881 and no-68881 both given");
3791 if (no_68851 && (current_architecture & m68851))
3792 as_bad ("options for 68851 and no-68851 both given");
3793
3794 #ifdef OBJ_AOUT
3795 /* Work out the magic number. This isn't very general. */
3796 if (current_architecture & m68000)
3797 m68k_aout_machtype = 0;
3798 else if (current_architecture & m68010)
3799 m68k_aout_machtype = 1;
3800 else if (current_architecture & m68020)
3801 m68k_aout_machtype = 2;
3802 else
3803 m68k_aout_machtype = 2;
3804 #endif
3805
3806 /* Note which set of "movec" control registers is available. */
3807 select_control_regs ();
3808
3809 if (cpu_of_arch (current_architecture) < m68020)
3810 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3811 }
3812 \f
3813 /* This is called when a label is defined. */
3814
3815 void
3816 m68k_frob_label (sym)
3817 symbolS *sym;
3818 {
3819 struct label_line *n;
3820
3821 n = (struct label_line *) xmalloc (sizeof *n);
3822 n->next = labels;
3823 n->label = sym;
3824 as_where (&n->file, &n->line);
3825 n->text = 0;
3826 labels = n;
3827 current_label = n;
3828 }
3829
3830 /* This is called when a value that is not an instruction is emitted. */
3831
3832 void
3833 m68k_flush_pending_output ()
3834 {
3835 current_label = NULL;
3836 }
3837
3838 /* This is called at the end of the assembly, when the final value of
3839 the label is known. We warn if this is a text symbol aligned at an
3840 odd location. */
3841
3842 void
3843 m68k_frob_symbol (sym)
3844 symbolS *sym;
3845 {
3846 if ((S_GET_VALUE (sym) & 1) != 0)
3847 {
3848 struct label_line *l;
3849
3850 for (l = labels; l != NULL; l = l->next)
3851 {
3852 if (l->label == sym)
3853 {
3854 if (l->text)
3855 as_warn_where (l->file, l->line,
3856 "text label `%s' aligned to odd boundary",
3857 S_GET_NAME (sym));
3858 break;
3859 }
3860 }
3861 }
3862 }
3863 \f
3864 /* This is called if we go in or out of MRI mode because of the .mri
3865 pseudo-op. */
3866
3867 void
3868 m68k_mri_mode_change (on)
3869 int on;
3870 {
3871 if (on)
3872 {
3873 if (! flag_reg_prefix_optional)
3874 {
3875 flag_reg_prefix_optional = 1;
3876 #ifdef REGISTER_PREFIX
3877 init_regtable ();
3878 #endif
3879 }
3880 m68k_abspcadd = 1;
3881 if (! m68k_rel32_from_cmdline)
3882 m68k_rel32 = 0;
3883 }
3884 else
3885 {
3886 if (! reg_prefix_optional_seen)
3887 {
3888 #ifdef REGISTER_PREFIX_OPTIONAL
3889 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3890 #else
3891 flag_reg_prefix_optional = 0;
3892 #endif
3893 #ifdef REGISTER_PREFIX
3894 init_regtable ();
3895 #endif
3896 }
3897 m68k_abspcadd = 0;
3898 if (! m68k_rel32_from_cmdline)
3899 m68k_rel32 = 1;
3900 }
3901 }
3902
3903 /* Equal to MAX_PRECISION in atof-ieee.c */
3904 #define MAX_LITTLENUMS 6
3905
3906 /* Turn a string in input_line_pointer into a floating point constant
3907 of type type, and store the appropriate bytes in *litP. The number
3908 of LITTLENUMS emitted is stored in *sizeP . An error message is
3909 returned, or NULL on OK. */
3910
3911 char *
3912 md_atof (type, litP, sizeP)
3913 char type;
3914 char *litP;
3915 int *sizeP;
3916 {
3917 int prec;
3918 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3919 LITTLENUM_TYPE *wordP;
3920 char *t;
3921
3922 switch (type)
3923 {
3924 case 'f':
3925 case 'F':
3926 case 's':
3927 case 'S':
3928 prec = 2;
3929 break;
3930
3931 case 'd':
3932 case 'D':
3933 case 'r':
3934 case 'R':
3935 prec = 4;
3936 break;
3937
3938 case 'x':
3939 case 'X':
3940 prec = 6;
3941 break;
3942
3943 case 'p':
3944 case 'P':
3945 prec = 6;
3946 break;
3947
3948 default:
3949 *sizeP = 0;
3950 return "Bad call to MD_ATOF()";
3951 }
3952 t = atof_ieee (input_line_pointer, type, words);
3953 if (t)
3954 input_line_pointer = t;
3955
3956 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3957 for (wordP = words; prec--;)
3958 {
3959 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3960 litP += sizeof (LITTLENUM_TYPE);
3961 }
3962 return 0;
3963 }
3964
3965 void
3966 md_number_to_chars (buf, val, n)
3967 char *buf;
3968 valueT val;
3969 int n;
3970 {
3971 number_to_chars_bigendian (buf, val, n);
3972 }
3973
3974 static void
3975 md_apply_fix_2 (fixP, val)
3976 fixS *fixP;
3977 offsetT val;
3978 {
3979 addressT upper_limit;
3980 offsetT lower_limit;
3981
3982 /* This is unnecessary but it convinces the native rs6000 compiler
3983 to generate the code we want. */
3984 char *buf = fixP->fx_frag->fr_literal;
3985 buf += fixP->fx_where;
3986 /* end ibm compiler workaround */
3987
3988 if (val & 0x80000000)
3989 val |= ~(addressT)0x7fffffff;
3990 else
3991 val &= 0x7fffffff;
3992
3993 #ifdef OBJ_ELF
3994 if (fixP->fx_addsy)
3995 {
3996 memset (buf, 0, fixP->fx_size);
3997 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3998 return;
3999 }
4000 #endif
4001
4002 switch (fixP->fx_size)
4003 {
4004 /* The cast to offsetT below are necessary to make code correct for
4005 machines where ints are smaller than offsetT */
4006 case 1:
4007 *buf++ = val;
4008 upper_limit = 0x7f;
4009 lower_limit = - (offsetT) 0x80;
4010 break;
4011 case 2:
4012 *buf++ = (val >> 8);
4013 *buf++ = val;
4014 upper_limit = 0x7fff;
4015 lower_limit = - (offsetT) 0x8000;
4016 break;
4017 case 4:
4018 *buf++ = (val >> 24);
4019 *buf++ = (val >> 16);
4020 *buf++ = (val >> 8);
4021 *buf++ = val;
4022 upper_limit = 0x7fffffff;
4023 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4024 break;
4025 default:
4026 BAD_CASE (fixP->fx_size);
4027 }
4028
4029 /* Fix up a negative reloc. */
4030 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4031 {
4032 fixP->fx_addsy = fixP->fx_subsy;
4033 fixP->fx_subsy = NULL;
4034 fixP->fx_tcbit = 1;
4035 }
4036
4037 /* For non-pc-relative values, it's conceivable we might get something
4038 like "0xff" for a byte field. So extend the upper part of the range
4039 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4040 so that we can do any range checking at all. */
4041 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4042 upper_limit = upper_limit * 2 + 1;
4043
4044 if ((addressT) val > upper_limit
4045 && (val > 0 || val < lower_limit))
4046 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4047
4048 /* A one byte PC-relative reloc means a short branch. We can't use
4049 a short branch with a value of 0 or -1, because those indicate
4050 different opcodes (branches with longer offsets). fixup_segment
4051 in write.c may have clobbered fx_pcrel, so we need to examine the
4052 reloc type. */
4053 if ((fixP->fx_pcrel
4054 #ifdef BFD_ASSEMBLER
4055 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4056 #endif
4057 )
4058 && fixP->fx_size == 1
4059 && (fixP->fx_addsy == NULL
4060 || S_IS_DEFINED (fixP->fx_addsy))
4061 && (val == 0 || val == -1))
4062 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4063 }
4064
4065 #ifdef BFD_ASSEMBLER
4066 int
4067 md_apply_fix (fixP, valp)
4068 fixS *fixP;
4069 valueT *valp;
4070 {
4071 md_apply_fix_2 (fixP, (addressT) *valp);
4072 return 1;
4073 }
4074 #else
4075 void md_apply_fix (fixP, val)
4076 fixS *fixP;
4077 long val;
4078 {
4079 md_apply_fix_2 (fixP, (addressT) val);
4080 }
4081 #endif
4082
4083 /* *fragP has been relaxed to its final size, and now needs to have
4084 the bytes inside it modified to conform to the new size There is UGLY
4085 MAGIC here. ..
4086 */
4087 void
4088 md_convert_frag_1 (fragP)
4089 register fragS *fragP;
4090 {
4091 long disp;
4092 long ext = 0;
4093 fixS *fixP;
4094
4095 /* Address in object code of the displacement. */
4096 register int object_address = fragP->fr_fix + fragP->fr_address;
4097
4098 /* Address in gas core of the place to store the displacement. */
4099 /* This convinces the native rs6000 compiler to generate the code we
4100 want. */
4101 register char *buffer_address = fragP->fr_literal;
4102 buffer_address += fragP->fr_fix;
4103 /* end ibm compiler workaround */
4104
4105 /* The displacement of the address, from current location. */
4106 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4107 disp = (disp + fragP->fr_offset) - object_address;
4108
4109 #ifdef BFD_ASSEMBLER
4110 disp += fragP->fr_symbol->sy_frag->fr_address;
4111 #endif
4112
4113 switch (fragP->fr_subtype)
4114 {
4115 case TAB (BCC68000, BYTE):
4116 case TAB (ABRANCH, BYTE):
4117 know (issbyte (disp));
4118 if (disp == 0)
4119 as_bad ("short branch with zero offset: use :w");
4120 fragP->fr_opcode[1] = disp;
4121 ext = 0;
4122 break;
4123 case TAB (DBCC, SHORT):
4124 know (issword (disp));
4125 ext = 2;
4126 break;
4127 case TAB (BCC68000, SHORT):
4128 case TAB (ABRANCH, SHORT):
4129 know (issword (disp));
4130 fragP->fr_opcode[1] = 0x00;
4131 ext = 2;
4132 break;
4133 case TAB (ABRANCH, LONG):
4134 if (!HAVE_LONG_BRANCH(current_architecture))
4135 {
4136 if (fragP->fr_opcode[0] == 0x61)
4137 /* BSR */
4138 {
4139 fragP->fr_opcode[0] = 0x4E;
4140 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4141
4142 fix_new (fragP,
4143 fragP->fr_fix,
4144 4,
4145 fragP->fr_symbol,
4146 fragP->fr_offset,
4147 0,
4148 NO_RELOC);
4149
4150 fragP->fr_fix += 4;
4151 ext = 0;
4152 }
4153 /* BRA */
4154 else if (fragP->fr_opcode[0] == 0x60)
4155 {
4156 fragP->fr_opcode[0] = 0x4E;
4157 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4158 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4159 fragP->fr_offset, 0, NO_RELOC);
4160 fragP->fr_fix += 4;
4161 ext = 0;
4162 }
4163 else
4164 {
4165 as_bad ("Long branch offset not supported.");
4166 }
4167 }
4168 else
4169 {
4170 fragP->fr_opcode[1] = (char) 0xff;
4171 ext = 4;
4172 }
4173 break;
4174 case TAB (BCC68000, LONG):
4175 /* only Bcc 68000 instructions can come here */
4176 /* change bcc into b!cc/jmp absl long */
4177 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4178 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4179
4180 /* JF: these used to be fr_opcode[2,3], but they may be in a
4181 different frag, in which case refering to them is a no-no.
4182 Only fr_opcode[0,1] are guaranteed to work. */
4183 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4184 *buffer_address++ = (char) 0xf9;
4185 fragP->fr_fix += 2; /* account for jmp instruction */
4186 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4187 fragP->fr_offset, 0, NO_RELOC);
4188 fragP->fr_fix += 4;
4189 ext = 0;
4190 break;
4191 case TAB (DBCC, LONG):
4192 /* only DBcc 68000 instructions can come here */
4193 /* change dbcc into dbcc/jmp absl long */
4194 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4195 *buffer_address++ = 0x00; /* branch offset = 4 */
4196 *buffer_address++ = 0x04;
4197 *buffer_address++ = 0x60; /* put in bra pc+6 */
4198 *buffer_address++ = 0x06;
4199 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4200 *buffer_address++ = (char) 0xf9;
4201
4202 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4203 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4204 fragP->fr_offset, 0, NO_RELOC);
4205 fragP->fr_fix += 4;
4206 ext = 0;
4207 break;
4208 case TAB (FBRANCH, SHORT):
4209 know ((fragP->fr_opcode[1] & 0x40) == 0);
4210 ext = 2;
4211 break;
4212 case TAB (FBRANCH, LONG):
4213 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4214 ext = 4;
4215 break;
4216 case TAB (PCREL, SHORT):
4217 ext = 2;
4218 break;
4219 case TAB (PCREL, LONG):
4220 /* The thing to do here is force it to ABSOLUTE LONG, since
4221 PCREL is really trying to shorten an ABSOLUTE address anyway */
4222 /* JF FOO This code has not been tested */
4223 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4224 0, NO_RELOC);
4225 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4226 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4227 (unsigned) fragP->fr_opcode[0],
4228 (unsigned long) fragP->fr_address);
4229 fragP->fr_opcode[1] &= ~0x3F;
4230 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4231 fragP->fr_fix += 4;
4232 ext = 0;
4233 break;
4234 case TAB (PCLEA, SHORT):
4235 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4236 fragP->fr_offset, 1, NO_RELOC);
4237 fragP->fr_opcode[1] &= ~0x3F;
4238 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4239 ext = 2;
4240 break;
4241 case TAB (PCLEA, LONG):
4242 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4243 fragP->fr_offset, 1, NO_RELOC);
4244 fixP->fx_pcrel_adjust = 2;
4245 /* Already set to mode 7.3; this indicates: PC indirect with
4246 suppressed index, 32-bit displacement. */
4247 *buffer_address++ = 0x01;
4248 *buffer_address++ = 0x70;
4249 fragP->fr_fix += 2;
4250 ext = 4;
4251 break;
4252
4253 case TAB (PCINDEX, BYTE):
4254 disp += 2;
4255 if (!issbyte (disp))
4256 {
4257 as_bad ("displacement doesn't fit in one byte");
4258 disp = 0;
4259 }
4260 assert (fragP->fr_fix >= 2);
4261 buffer_address[-2] &= ~1;
4262 buffer_address[-1] = disp;
4263 ext = 0;
4264 break;
4265 case TAB (PCINDEX, SHORT):
4266 disp += 2;
4267 assert (issword (disp));
4268 assert (fragP->fr_fix >= 2);
4269 buffer_address[-2] |= 0x1;
4270 buffer_address[-1] = 0x20;
4271 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4272 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4273 NO_RELOC);
4274 fixP->fx_pcrel_adjust = 2;
4275 ext = 2;
4276 break;
4277 case TAB (PCINDEX, LONG):
4278 disp += 2;
4279 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4280 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4281 NO_RELOC);
4282 fixP->fx_pcrel_adjust = 2;
4283 assert (fragP->fr_fix >= 2);
4284 buffer_address[-2] |= 0x1;
4285 buffer_address[-1] = 0x30;
4286 ext = 4;
4287 break;
4288 }
4289
4290 if (ext)
4291 {
4292 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4293 fragP->fr_fix += ext;
4294 }
4295 }
4296
4297 #ifndef BFD_ASSEMBLER
4298
4299 void
4300 md_convert_frag (headers, sec, fragP)
4301 object_headers *headers;
4302 segT sec;
4303 fragS *fragP;
4304 {
4305 md_convert_frag_1 (fragP);
4306 }
4307
4308 #else
4309
4310 void
4311 md_convert_frag (abfd, sec, fragP)
4312 bfd *abfd;
4313 segT sec;
4314 fragS *fragP;
4315 {
4316 md_convert_frag_1 (fragP);
4317 }
4318 #endif
4319
4320 /* Force truly undefined symbols to their maximum size, and generally set up
4321 the frag list to be relaxed
4322 */
4323 int
4324 md_estimate_size_before_relax (fragP, segment)
4325 register fragS *fragP;
4326 segT segment;
4327 {
4328 int old_fix;
4329 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4330
4331 old_fix = fragP->fr_fix;
4332
4333 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4334 switch (fragP->fr_subtype)
4335 {
4336
4337 case TAB (ABRANCH, SZ_UNDEF):
4338 {
4339 if ((fragP->fr_symbol != NULL) /* Not absolute */
4340 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4341 {
4342 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4343 break;
4344 }
4345 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4346 {
4347 /* On 68000, or for absolute value, switch to abs long */
4348 /* FIXME, we should check abs val, pick short or long */
4349 if (fragP->fr_opcode[0] == 0x61)
4350 {
4351 fragP->fr_opcode[0] = 0x4E;
4352 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4353 fix_new (fragP, fragP->fr_fix, 4,
4354 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4355 fragP->fr_fix += 4;
4356 frag_wane (fragP);
4357 }
4358 else if (fragP->fr_opcode[0] == 0x60)
4359 {
4360 fragP->fr_opcode[0] = 0x4E;
4361 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4362 fix_new (fragP, fragP->fr_fix, 4,
4363 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4364 fragP->fr_fix += 4;
4365 frag_wane (fragP);
4366 }
4367 else
4368 {
4369 as_warn ("Long branch offset to extern symbol not supported.");
4370 }
4371 }
4372 else
4373 { /* Symbol is still undefined. Make it simple */
4374 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4375 fragP->fr_offset, 1, NO_RELOC);
4376 fragP->fr_fix += 4;
4377 fragP->fr_opcode[1] = (char) 0xff;
4378 frag_wane (fragP);
4379 break;
4380 }
4381
4382 break;
4383 } /* case TAB(ABRANCH,SZ_UNDEF) */
4384
4385 case TAB (FBRANCH, SZ_UNDEF):
4386 {
4387 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4388 {
4389 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4390 fragP->fr_var += 2;
4391 }
4392 else
4393 {
4394 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4395 fragP->fr_offset, 1, NO_RELOC);
4396 fragP->fr_fix += 4;
4397 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4398 frag_wane (fragP);
4399 }
4400 break;
4401 } /* TAB(FBRANCH,SZ_UNDEF) */
4402
4403 case TAB (PCREL, SZ_UNDEF):
4404 {
4405 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4406 || flag_short_refs
4407 || cpu_of_arch (current_architecture) < m68020)
4408 {
4409 fragP->fr_subtype = TAB (PCREL, SHORT);
4410 fragP->fr_var += 2;
4411 }
4412 else
4413 {
4414 fragP->fr_subtype = TAB (PCREL, LONG);
4415 fragP->fr_var += 4;
4416 }
4417 break;
4418 } /* TAB(PCREL,SZ_UNDEF) */
4419
4420 case TAB (BCC68000, SZ_UNDEF):
4421 {
4422 if ((fragP->fr_symbol != NULL)
4423 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4424 {
4425 fragP->fr_subtype = TAB (BCC68000, BYTE);
4426 break;
4427 }
4428 /* only Bcc 68000 instructions can come here */
4429 /* change bcc into b!cc/jmp absl long */
4430 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4431 if (flag_short_refs)
4432 {
4433 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4434 /* JF: these were fr_opcode[2,3] */
4435 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4436 buffer_address[1] = (char) 0xf8;
4437 fragP->fr_fix += 2; /* account for jmp instruction */
4438 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4439 fragP->fr_offset, 0, NO_RELOC);
4440 fragP->fr_fix += 2;
4441 }
4442 else
4443 {
4444 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4445 /* JF: these were fr_opcode[2,3] */
4446 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4447 buffer_address[1] = (char) 0xf9;
4448 fragP->fr_fix += 2; /* account for jmp instruction */
4449 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4450 fragP->fr_offset, 0, NO_RELOC);
4451 fragP->fr_fix += 4;
4452 }
4453 frag_wane (fragP);
4454 break;
4455 } /* case TAB(BCC68000,SZ_UNDEF) */
4456
4457 case TAB (DBCC, SZ_UNDEF):
4458 {
4459 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4460 {
4461 fragP->fr_subtype = TAB (DBCC, SHORT);
4462 fragP->fr_var += 2;
4463 break;
4464 }
4465 /* only DBcc 68000 instructions can come here */
4466 /* change dbcc into dbcc/jmp absl long */
4467 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4468 buffer_address[0] = 0x00; /* branch offset = 4 */
4469 buffer_address[1] = 0x04;
4470 buffer_address[2] = 0x60; /* put in bra pc + ... */
4471
4472 if (flag_short_refs)
4473 {
4474 /* JF: these were fr_opcode[5-7] */
4475 buffer_address[3] = 0x04; /* plus 4 */
4476 buffer_address[4] = 0x4e; /* Put in Jump Word */
4477 buffer_address[5] = (char) 0xf8;
4478 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4479 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4480 fragP->fr_offset, 0, NO_RELOC);
4481 fragP->fr_fix += 2;
4482 }
4483 else
4484 {
4485 /* JF: these were fr_opcode[5-7] */
4486 buffer_address[3] = 0x06; /* Plus 6 */
4487 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4488 buffer_address[5] = (char) 0xf9;
4489 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4490 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4491 fragP->fr_offset, 0, NO_RELOC);
4492 fragP->fr_fix += 4;
4493 }
4494
4495 frag_wane (fragP);
4496 break;
4497 } /* case TAB(DBCC,SZ_UNDEF) */
4498
4499 case TAB (PCLEA, SZ_UNDEF):
4500 {
4501 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4502 || flag_short_refs
4503 || cpu_of_arch (current_architecture) < m68020)
4504 {
4505 fragP->fr_subtype = TAB (PCLEA, SHORT);
4506 fragP->fr_var += 2;
4507 }
4508 else
4509 {
4510 fragP->fr_subtype = TAB (PCLEA, LONG);
4511 fragP->fr_var += 6;
4512 }
4513 break;
4514 } /* TAB(PCLEA,SZ_UNDEF) */
4515
4516 case TAB (PCINDEX, SZ_UNDEF):
4517 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4518 || cpu_of_arch (current_architecture) < m68020)
4519 {
4520 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4521 }
4522 else
4523 {
4524 fragP->fr_subtype = TAB (PCINDEX, LONG);
4525 fragP->fr_var += 4;
4526 }
4527 break;
4528
4529 default:
4530 break;
4531 }
4532
4533 /* now that SZ_UNDEF are taken care of, check others */
4534 switch (fragP->fr_subtype)
4535 {
4536 case TAB (BCC68000, BYTE):
4537 case TAB (ABRANCH, BYTE):
4538 /* We can't do a short jump to the next instruction, so in that
4539 case we force word mode. At this point S_GET_VALUE should
4540 return the offset of the symbol within its frag. If the
4541 symbol is at the start of a frag, and it is the next frag
4542 with any data in it (usually this is just the next frag, but
4543 assembler listings may introduce empty frags), we must use
4544 word mode. */
4545 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4546 {
4547 fragS *l;
4548
4549 for (l = fragP->fr_next;
4550 l != fragP->fr_symbol->sy_frag;
4551 l = l->fr_next)
4552 if (l->fr_fix + l->fr_var != 0)
4553 break;
4554 if (l == fragP->fr_symbol->sy_frag)
4555 {
4556 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4557 fragP->fr_var += 2;
4558 }
4559 }
4560 break;
4561 default:
4562 break;
4563 }
4564 return fragP->fr_var + fragP->fr_fix - old_fix;
4565 }
4566
4567 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4568 /* the bit-field entries in the relocation_info struct plays hell
4569 with the byte-order problems of cross-assembly. So as a hack,
4570 I added this mach. dependent ri twiddler. Ugly, but it gets
4571 you there. -KWK */
4572 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4573 are symbolnum, most sig. byte first. Last byte is broken up with
4574 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4575 nibble as nuthin. (on Sun 3 at least) */
4576 /* Translate the internal relocation information into target-specific
4577 format. */
4578 #ifdef comment
4579 void
4580 md_ri_to_chars (the_bytes, ri)
4581 char *the_bytes;
4582 struct reloc_info_generic *ri;
4583 {
4584 /* this is easy */
4585 md_number_to_chars (the_bytes, ri->r_address, 4);
4586 /* now the fun stuff */
4587 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4588 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4589 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4590 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4591 ((ri->r_extern << 4) & 0x10));
4592 }
4593
4594 #endif /* comment */
4595
4596 #ifndef BFD_ASSEMBLER
4597 void
4598 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4599 char *where;
4600 fixS *fixP;
4601 relax_addressT segment_address_in_file;
4602 {
4603 /*
4604 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4605 * Out: GNU LD relocation length code: 0, 1, or 2.
4606 */
4607
4608 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4609 long r_symbolnum;
4610
4611 know (fixP->fx_addsy != NULL);
4612
4613 md_number_to_chars (where,
4614 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4615 4);
4616
4617 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4618 ? S_GET_TYPE (fixP->fx_addsy)
4619 : fixP->fx_addsy->sy_number);
4620
4621 where[4] = (r_symbolnum >> 16) & 0x0ff;
4622 where[5] = (r_symbolnum >> 8) & 0x0ff;
4623 where[6] = r_symbolnum & 0x0ff;
4624 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4625 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4626 }
4627 #endif
4628
4629 #endif /* OBJ_AOUT or OBJ_BOUT */
4630
4631 #ifndef WORKING_DOT_WORD
4632 CONST int md_short_jump_size = 4;
4633 CONST int md_long_jump_size = 6;
4634
4635 void
4636 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4637 char *ptr;
4638 addressT from_addr, to_addr;
4639 fragS *frag;
4640 symbolS *to_symbol;
4641 {
4642 valueT offset;
4643
4644 offset = to_addr - (from_addr + 2);
4645
4646 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4647 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4648 }
4649
4650 void
4651 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4652 char *ptr;
4653 addressT from_addr, to_addr;
4654 fragS *frag;
4655 symbolS *to_symbol;
4656 {
4657 valueT offset;
4658
4659 if (!HAVE_LONG_BRANCH(current_architecture))
4660 {
4661 offset = to_addr - S_GET_VALUE (to_symbol);
4662 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4663 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4664 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4665 0, NO_RELOC);
4666 }
4667 else
4668 {
4669 offset = to_addr - (from_addr + 2);
4670 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4671 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4672 }
4673 }
4674
4675 #endif
4676
4677 /* Different values of OK tell what its OK to return. Things that
4678 aren't OK are an error (what a shock, no?)
4679
4680 0: Everything is OK
4681 10: Absolute 1:8 only
4682 20: Absolute 0:7 only
4683 30: absolute 0:15 only
4684 40: Absolute 0:31 only
4685 50: absolute 0:127 only
4686 55: absolute -64:63 only
4687 60: absolute -128:127 only
4688 70: absolute 0:4095 only
4689 80: No bignums
4690
4691 */
4692
4693 static int
4694 get_num (exp, ok)
4695 struct m68k_exp *exp;
4696 int ok;
4697 {
4698 if (exp->exp.X_op == O_absent)
4699 {
4700 /* Do the same thing the VAX asm does */
4701 op (exp) = O_constant;
4702 adds (exp) = 0;
4703 subs (exp) = 0;
4704 offs (exp) = 0;
4705 if (ok == 10)
4706 {
4707 as_warn ("expression out of range: defaulting to 1");
4708 offs (exp) = 1;
4709 }
4710 }
4711 else if (exp->exp.X_op == O_constant)
4712 {
4713 switch (ok)
4714 {
4715 case 10:
4716 if (offs (exp) < 1 || offs (exp) > 8)
4717 {
4718 as_warn ("expression out of range: defaulting to 1");
4719 offs (exp) = 1;
4720 }
4721 break;
4722 case 20:
4723 if (offs (exp) < 0 || offs (exp) > 7)
4724 goto outrange;
4725 break;
4726 case 30:
4727 if (offs (exp) < 0 || offs (exp) > 15)
4728 goto outrange;
4729 break;
4730 case 40:
4731 if (offs (exp) < 0 || offs (exp) > 32)
4732 goto outrange;
4733 break;
4734 case 50:
4735 if (offs (exp) < 0 || offs (exp) > 127)
4736 goto outrange;
4737 break;
4738 case 55:
4739 if (offs (exp) < -64 || offs (exp) > 63)
4740 goto outrange;
4741 break;
4742 case 60:
4743 if (offs (exp) < -128 || offs (exp) > 127)
4744 goto outrange;
4745 break;
4746 case 70:
4747 if (offs (exp) < 0 || offs (exp) > 4095)
4748 {
4749 outrange:
4750 as_warn ("expression out of range: defaulting to 0");
4751 offs (exp) = 0;
4752 }
4753 break;
4754 default:
4755 break;
4756 }
4757 }
4758 else if (exp->exp.X_op == O_big)
4759 {
4760 if (offs (exp) <= 0 /* flonum */
4761 && (ok == 80 /* no bignums */
4762 || (ok > 10 /* small-int ranges including 0 ok */
4763 /* If we have a flonum zero, a zero integer should
4764 do as well (e.g., in moveq). */
4765 && generic_floating_point_number.exponent == 0
4766 && generic_floating_point_number.low[0] == 0)))
4767 {
4768 /* HACK! Turn it into a long */
4769 LITTLENUM_TYPE words[6];
4770
4771 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4772 op (exp) = O_constant;
4773 adds (exp) = 0;
4774 subs (exp) = 0;
4775 offs (exp) = words[1] | (words[0] << 16);
4776 }
4777 else if (ok != 0)
4778 {
4779 op (exp) = O_constant;
4780 adds (exp) = 0;
4781 subs (exp) = 0;
4782 offs (exp) = (ok == 10) ? 1 : 0;
4783 as_warn ("Can't deal with expression; defaulting to %ld",
4784 offs (exp));
4785 }
4786 }
4787 else
4788 {
4789 if (ok >= 10 && ok <= 70)
4790 {
4791 op (exp) = O_constant;
4792 adds (exp) = 0;
4793 subs (exp) = 0;
4794 offs (exp) = (ok == 10) ? 1 : 0;
4795 as_warn ("Can't deal with expression; defaulting to %ld",
4796 offs (exp));
4797 }
4798 }
4799
4800 if (exp->size != SIZE_UNSPEC)
4801 {
4802 switch (exp->size)
4803 {
4804 case SIZE_UNSPEC:
4805 case SIZE_LONG:
4806 break;
4807 case SIZE_BYTE:
4808 if (!isbyte (offs (exp)))
4809 as_warn ("expression doesn't fit in BYTE");
4810 break;
4811 case SIZE_WORD:
4812 if (!isword (offs (exp)))
4813 as_warn ("expression doesn't fit in WORD");
4814 break;
4815 }
4816 }
4817
4818 return offs (exp);
4819 }
4820
4821 /* These are the back-ends for the various machine dependent pseudo-ops. */
4822
4823 static void
4824 s_data1 (ignore)
4825 int ignore;
4826 {
4827 subseg_set (data_section, 1);
4828 demand_empty_rest_of_line ();
4829 }
4830
4831 static void
4832 s_data2 (ignore)
4833 int ignore;
4834 {
4835 subseg_set (data_section, 2);
4836 demand_empty_rest_of_line ();
4837 }
4838
4839 static void
4840 s_bss (ignore)
4841 int ignore;
4842 {
4843 /* We don't support putting frags in the BSS segment, we fake it
4844 by marking in_bss, then looking at s_skip for clues. */
4845
4846 subseg_set (bss_section, 0);
4847 demand_empty_rest_of_line ();
4848 }
4849
4850 static void
4851 s_even (ignore)
4852 int ignore;
4853 {
4854 register int temp;
4855 register long temp_fill;
4856
4857 temp = 1; /* JF should be 2? */
4858 temp_fill = get_absolute_expression ();
4859 if (!need_pass_2) /* Never make frag if expect extra pass. */
4860 frag_align (temp, (int) temp_fill, 0);
4861 demand_empty_rest_of_line ();
4862 record_alignment (now_seg, temp);
4863 }
4864
4865 static void
4866 s_proc (ignore)
4867 int ignore;
4868 {
4869 demand_empty_rest_of_line ();
4870 }
4871 \f
4872 /* Pseudo-ops handled for MRI compatibility. */
4873
4874 /* This function returns non-zero if the argument is a conditional
4875 pseudo-op. This is called when checking whether a pending
4876 alignment is needed. */
4877
4878 int
4879 m68k_conditional_pseudoop (pop)
4880 pseudo_typeS *pop;
4881 {
4882 return (pop->poc_handler == s_mri_if
4883 || pop->poc_handler == s_mri_else);
4884 }
4885
4886 /* Handle an MRI style chip specification. */
4887
4888 static void
4889 mri_chip ()
4890 {
4891 char *s;
4892 char c;
4893 int i;
4894
4895 s = input_line_pointer;
4896 /* We can't use get_symbol_end since the processor names are not proper
4897 symbols. */
4898 while (is_part_of_name (c = *input_line_pointer++))
4899 ;
4900 *--input_line_pointer = 0;
4901 for (i = 0; i < n_archs; i++)
4902 if (strcasecmp (s, archs[i].name) == 0)
4903 break;
4904 if (i >= n_archs)
4905 {
4906 as_bad ("%s: unrecognized processor name", s);
4907 *input_line_pointer = c;
4908 ignore_rest_of_line ();
4909 return;
4910 }
4911 *input_line_pointer = c;
4912
4913 if (*input_line_pointer == '/')
4914 current_architecture = 0;
4915 else
4916 current_architecture &= m68881 | m68851;
4917 current_architecture |= archs[i].arch;
4918
4919 while (*input_line_pointer == '/')
4920 {
4921 ++input_line_pointer;
4922 s = input_line_pointer;
4923 /* We can't use get_symbol_end since the processor names are not
4924 proper symbols. */
4925 while (is_part_of_name (c = *input_line_pointer++))
4926 ;
4927 *--input_line_pointer = 0;
4928 if (strcmp (s, "68881") == 0)
4929 current_architecture |= m68881;
4930 else if (strcmp (s, "68851") == 0)
4931 current_architecture |= m68851;
4932 *input_line_pointer = c;
4933 }
4934
4935 /* Update info about available control registers. */
4936 select_control_regs ();
4937 }
4938
4939 /* The MRI CHIP pseudo-op. */
4940
4941 static void
4942 s_chip (ignore)
4943 int ignore;
4944 {
4945 char *stop = NULL;
4946 char stopc;
4947
4948 if (flag_mri)
4949 stop = mri_comment_field (&stopc);
4950 mri_chip ();
4951 if (flag_mri)
4952 mri_comment_end (stop, stopc);
4953 demand_empty_rest_of_line ();
4954 }
4955
4956 /* The MRI FOPT pseudo-op. */
4957
4958 static void
4959 s_fopt (ignore)
4960 int ignore;
4961 {
4962 SKIP_WHITESPACE ();
4963
4964 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4965 {
4966 int temp;
4967
4968 input_line_pointer += 3;
4969 temp = get_absolute_expression ();
4970 if (temp < 0 || temp > 7)
4971 as_bad ("bad coprocessor id");
4972 else
4973 m68k_float_copnum = COP0 + temp;
4974 }
4975 else
4976 {
4977 as_bad ("unrecognized fopt option");
4978 ignore_rest_of_line ();
4979 return;
4980 }
4981
4982 demand_empty_rest_of_line ();
4983 }
4984
4985 /* The structure used to handle the MRI OPT pseudo-op. */
4986
4987 struct opt_action
4988 {
4989 /* The name of the option. */
4990 const char *name;
4991
4992 /* If this is not NULL, just call this function. The first argument
4993 is the ARG field of this structure, the second argument is
4994 whether the option was negated. */
4995 void (*pfn) PARAMS ((int arg, int on));
4996
4997 /* If this is not NULL, and the PFN field is NULL, set the variable
4998 this points to. Set it to the ARG field if the option was not
4999 negated, and the NOTARG field otherwise. */
5000 int *pvar;
5001
5002 /* The value to pass to PFN or to assign to *PVAR. */
5003 int arg;
5004
5005 /* The value to assign to *PVAR if the option is negated. If PFN is
5006 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5007 the option may not be negated. */
5008 int notarg;
5009 };
5010
5011 /* The table used to handle the MRI OPT pseudo-op. */
5012
5013 static void skip_to_comma PARAMS ((int, int));
5014 static void opt_nest PARAMS ((int, int));
5015 static void opt_chip PARAMS ((int, int));
5016 static void opt_list PARAMS ((int, int));
5017 static void opt_list_symbols PARAMS ((int, int));
5018
5019 static const struct opt_action opt_table[] =
5020 {
5021 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5022
5023 /* We do relaxing, so there is little use for these options. */
5024 { "b", 0, 0, 0, 0 },
5025 { "brs", 0, 0, 0, 0 },
5026 { "brb", 0, 0, 0, 0 },
5027 { "brl", 0, 0, 0, 0 },
5028 { "brw", 0, 0, 0, 0 },
5029
5030 { "c", 0, 0, 0, 0 },
5031 { "cex", 0, 0, 0, 0 },
5032 { "case", 0, &symbols_case_sensitive, 1, 0 },
5033 { "cl", 0, 0, 0, 0 },
5034 { "cre", 0, 0, 0, 0 },
5035 { "d", 0, &flag_keep_locals, 1, 0 },
5036 { "e", 0, 0, 0, 0 },
5037 { "f", 0, &flag_short_refs, 1, 0 },
5038 { "frs", 0, &flag_short_refs, 1, 0 },
5039 { "frl", 0, &flag_short_refs, 0, 1 },
5040 { "g", 0, 0, 0, 0 },
5041 { "i", 0, 0, 0, 0 },
5042 { "m", 0, 0, 0, 0 },
5043 { "mex", 0, 0, 0, 0 },
5044 { "mc", 0, 0, 0, 0 },
5045 { "md", 0, 0, 0, 0 },
5046 { "nest", opt_nest, 0, 0, 0 },
5047 { "next", skip_to_comma, 0, 0, 0 },
5048 { "o", 0, 0, 0, 0 },
5049 { "old", 0, 0, 0, 0 },
5050 { "op", skip_to_comma, 0, 0, 0 },
5051 { "pco", 0, 0, 0, 0 },
5052 { "p", opt_chip, 0, 0, 0 },
5053 { "pcr", 0, 0, 0, 0 },
5054 { "pcs", 0, 0, 0, 0 },
5055 { "r", 0, 0, 0, 0 },
5056 { "quick", 0, &m68k_quick, 1, 0 },
5057 { "rel32", 0, &m68k_rel32, 1, 0 },
5058 { "s", opt_list, 0, 0, 0 },
5059 { "t", opt_list_symbols, 0, 0, 0 },
5060 { "w", 0, &flag_no_warnings, 0, 1 },
5061 { "x", 0, 0, 0, 0 }
5062 };
5063
5064 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5065
5066 /* The MRI OPT pseudo-op. */
5067
5068 static void
5069 s_opt (ignore)
5070 int ignore;
5071 {
5072 do
5073 {
5074 int t;
5075 char *s;
5076 char c;
5077 int i;
5078 const struct opt_action *o;
5079
5080 SKIP_WHITESPACE ();
5081
5082 t = 1;
5083 if (*input_line_pointer == '-')
5084 {
5085 ++input_line_pointer;
5086 t = 0;
5087 }
5088 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5089 {
5090 input_line_pointer += 2;
5091 t = 0;
5092 }
5093
5094 s = input_line_pointer;
5095 c = get_symbol_end ();
5096
5097 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5098 {
5099 if (strcasecmp (s, o->name) == 0)
5100 {
5101 if (o->pfn)
5102 {
5103 /* Restore input_line_pointer now in case the option
5104 takes arguments. */
5105 *input_line_pointer = c;
5106 (*o->pfn) (o->arg, t);
5107 }
5108 else if (o->pvar != NULL)
5109 {
5110 if (! t && o->arg == o->notarg)
5111 as_bad ("option `%s' may not be negated", s);
5112 *input_line_pointer = c;
5113 *o->pvar = t ? o->arg : o->notarg;
5114 }
5115 else
5116 *input_line_pointer = c;
5117 break;
5118 }
5119 }
5120 if (i >= OPTCOUNT)
5121 {
5122 as_bad ("option `%s' not recognized", s);
5123 *input_line_pointer = c;
5124 }
5125 }
5126 while (*input_line_pointer++ == ',');
5127
5128 /* Move back to terminating character. */
5129 --input_line_pointer;
5130 demand_empty_rest_of_line ();
5131 }
5132
5133 /* Skip ahead to a comma. This is used for OPT options which we do
5134 not suppor tand which take arguments. */
5135
5136 static void
5137 skip_to_comma (arg, on)
5138 int arg;
5139 int on;
5140 {
5141 while (*input_line_pointer != ','
5142 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5143 ++input_line_pointer;
5144 }
5145
5146 /* Handle the OPT NEST=depth option. */
5147
5148 static void
5149 opt_nest (arg, on)
5150 int arg;
5151 int on;
5152 {
5153 if (*input_line_pointer != '=')
5154 {
5155 as_bad ("bad format of OPT NEST=depth");
5156 return;
5157 }
5158
5159 ++input_line_pointer;
5160 max_macro_nest = get_absolute_expression ();
5161 }
5162
5163 /* Handle the OPT P=chip option. */
5164
5165 static void
5166 opt_chip (arg, on)
5167 int arg;
5168 int on;
5169 {
5170 if (*input_line_pointer != '=')
5171 {
5172 /* This is just OPT P, which we do not support. */
5173 return;
5174 }
5175
5176 ++input_line_pointer;
5177 mri_chip ();
5178 }
5179
5180 /* Handle the OPT S option. */
5181
5182 static void
5183 opt_list (arg, on)
5184 int arg;
5185 int on;
5186 {
5187 listing_list (on);
5188 }
5189
5190 /* Handle the OPT T option. */
5191
5192 static void
5193 opt_list_symbols (arg, on)
5194 int arg;
5195 int on;
5196 {
5197 if (on)
5198 listing |= LISTING_SYMBOLS;
5199 else
5200 listing &=~ LISTING_SYMBOLS;
5201 }
5202
5203 /* Handle the MRI REG pseudo-op. */
5204
5205 static void
5206 s_reg (ignore)
5207 int ignore;
5208 {
5209 char *s;
5210 int c;
5211 struct m68k_op rop;
5212 unsigned long mask;
5213 char *stop = NULL;
5214 char stopc;
5215
5216 if (line_label == NULL)
5217 {
5218 as_bad ("missing label");
5219 ignore_rest_of_line ();
5220 return;
5221 }
5222
5223 if (flag_mri)
5224 stop = mri_comment_field (&stopc);
5225
5226 SKIP_WHITESPACE ();
5227
5228 s = input_line_pointer;
5229 while (isalnum ((unsigned char) *input_line_pointer)
5230 #ifdef REGISTER_PREFIX
5231 || *input_line_pointer == REGISTER_PREFIX
5232 #endif
5233 || *input_line_pointer == '/'
5234 || *input_line_pointer == '-')
5235 ++input_line_pointer;
5236 c = *input_line_pointer;
5237 *input_line_pointer = '\0';
5238
5239 if (m68k_ip_op (s, &rop) != 0)
5240 {
5241 if (rop.error == NULL)
5242 as_bad ("bad register list");
5243 else
5244 as_bad ("bad register list: %s", rop.error);
5245 *input_line_pointer = c;
5246 ignore_rest_of_line ();
5247 return;
5248 }
5249
5250 *input_line_pointer = c;
5251
5252 if (rop.mode == REGLST)
5253 mask = rop.mask;
5254 else if (rop.mode == DREG)
5255 mask = 1 << (rop.reg - DATA0);
5256 else if (rop.mode == AREG)
5257 mask = 1 << (rop.reg - ADDR0 + 8);
5258 else if (rop.mode == FPREG)
5259 mask = 1 << (rop.reg - FP0 + 16);
5260 else if (rop.mode == CONTROL
5261 && rop.reg == FPI)
5262 mask = 1 << 24;
5263 else if (rop.mode == CONTROL
5264 && rop.reg == FPS)
5265 mask = 1 << 25;
5266 else if (rop.mode == CONTROL
5267 && rop.reg == FPC)
5268 mask = 1 << 26;
5269 else
5270 {
5271 as_bad ("bad register list");
5272 ignore_rest_of_line ();
5273 return;
5274 }
5275
5276 S_SET_SEGMENT (line_label, absolute_section);
5277 S_SET_VALUE (line_label, mask);
5278 line_label->sy_frag = &zero_address_frag;
5279
5280 if (flag_mri)
5281 mri_comment_end (stop, stopc);
5282
5283 demand_empty_rest_of_line ();
5284 }
5285
5286 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5287
5288 struct save_opts
5289 {
5290 struct save_opts *next;
5291 int abspcadd;
5292 int symbols_case_sensitive;
5293 int keep_locals;
5294 int short_refs;
5295 int architecture;
5296 int quick;
5297 int rel32;
5298 int listing;
5299 int no_warnings;
5300 /* FIXME: We don't save OPT S. */
5301 };
5302
5303 /* This variable holds the stack of saved options. */
5304
5305 static struct save_opts *save_stack;
5306
5307 /* The MRI SAVE pseudo-op. */
5308
5309 static void
5310 s_save (ignore)
5311 int ignore;
5312 {
5313 struct save_opts *s;
5314
5315 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5316 s->abspcadd = m68k_abspcadd;
5317 s->symbols_case_sensitive = symbols_case_sensitive;
5318 s->keep_locals = flag_keep_locals;
5319 s->short_refs = flag_short_refs;
5320 s->architecture = current_architecture;
5321 s->quick = m68k_quick;
5322 s->rel32 = m68k_rel32;
5323 s->listing = listing;
5324 s->no_warnings = flag_no_warnings;
5325
5326 s->next = save_stack;
5327 save_stack = s;
5328
5329 demand_empty_rest_of_line ();
5330 }
5331
5332 /* The MRI RESTORE pseudo-op. */
5333
5334 static void
5335 s_restore (ignore)
5336 int ignore;
5337 {
5338 struct save_opts *s;
5339
5340 if (save_stack == NULL)
5341 {
5342 as_bad ("restore without save");
5343 ignore_rest_of_line ();
5344 return;
5345 }
5346
5347 s = save_stack;
5348 save_stack = s->next;
5349
5350 m68k_abspcadd = s->abspcadd;
5351 symbols_case_sensitive = s->symbols_case_sensitive;
5352 flag_keep_locals = s->keep_locals;
5353 flag_short_refs = s->short_refs;
5354 current_architecture = s->architecture;
5355 m68k_quick = s->quick;
5356 m68k_rel32 = s->rel32;
5357 listing = s->listing;
5358 flag_no_warnings = s->no_warnings;
5359
5360 free (s);
5361
5362 demand_empty_rest_of_line ();
5363 }
5364
5365 /* Types of MRI structured control directives. */
5366
5367 enum mri_control_type
5368 {
5369 mri_for,
5370 mri_if,
5371 mri_repeat,
5372 mri_while
5373 };
5374
5375 /* This structure is used to stack the MRI structured control
5376 directives. */
5377
5378 struct mri_control_info
5379 {
5380 /* The directive within which this one is enclosed. */
5381 struct mri_control_info *outer;
5382
5383 /* The type of directive. */
5384 enum mri_control_type type;
5385
5386 /* Whether an ELSE has been in an IF. */
5387 int else_seen;
5388
5389 /* The add or sub statement at the end of a FOR. */
5390 char *incr;
5391
5392 /* The label of the top of a FOR or REPEAT loop. */
5393 char *top;
5394
5395 /* The label to jump to for the next iteration, or the else
5396 expression of a conditional. */
5397 char *next;
5398
5399 /* The label to jump to to break out of the loop, or the label past
5400 the end of a conditional. */
5401 char *bottom;
5402 };
5403
5404 /* The stack of MRI structured control directives. */
5405
5406 static struct mri_control_info *mri_control_stack;
5407
5408 /* The current MRI structured control directive index number, used to
5409 generate label names. */
5410
5411 static int mri_control_index;
5412
5413 /* Some function prototypes. */
5414
5415 static char *mri_control_label PARAMS ((void));
5416 static struct mri_control_info *push_mri_control
5417 PARAMS ((enum mri_control_type));
5418 static void pop_mri_control PARAMS ((void));
5419 static int parse_mri_condition PARAMS ((int *));
5420 static int parse_mri_control_operand
5421 PARAMS ((int *, char **, char **, char **, char **));
5422 static int swap_mri_condition PARAMS ((int));
5423 static int reverse_mri_condition PARAMS ((int));
5424 static void build_mri_control_operand
5425 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5426 const char *, int));
5427 static void parse_mri_control_expression
5428 PARAMS ((char *, int, const char *, const char *, int));
5429
5430 /* Generate a new MRI label structured control directive label name. */
5431
5432 static char *
5433 mri_control_label ()
5434 {
5435 char *n;
5436
5437 n = (char *) xmalloc (20);
5438 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5439 ++mri_control_index;
5440 return n;
5441 }
5442
5443 /* Create a new MRI structured control directive. */
5444
5445 static struct mri_control_info *
5446 push_mri_control (type)
5447 enum mri_control_type type;
5448 {
5449 struct mri_control_info *n;
5450
5451 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5452
5453 n->type = type;
5454 n->else_seen = 0;
5455 if (type == mri_if || type == mri_while)
5456 n->top = NULL;
5457 else
5458 n->top = mri_control_label ();
5459 n->next = mri_control_label ();
5460 n->bottom = mri_control_label ();
5461
5462 n->outer = mri_control_stack;
5463 mri_control_stack = n;
5464
5465 return n;
5466 }
5467
5468 /* Pop off the stack of MRI structured control directives. */
5469
5470 static void
5471 pop_mri_control ()
5472 {
5473 struct mri_control_info *n;
5474
5475 n = mri_control_stack;
5476 mri_control_stack = n->outer;
5477 if (n->top != NULL)
5478 free (n->top);
5479 free (n->next);
5480 free (n->bottom);
5481 free (n);
5482 }
5483
5484 /* Recognize a condition code in an MRI structured control expression. */
5485
5486 static int
5487 parse_mri_condition (pcc)
5488 int *pcc;
5489 {
5490 char c1, c2;
5491
5492 know (*input_line_pointer == '<');
5493
5494 ++input_line_pointer;
5495 c1 = *input_line_pointer++;
5496 c2 = *input_line_pointer++;
5497
5498 if (*input_line_pointer != '>')
5499 {
5500 as_bad ("syntax error in structured control directive");
5501 return 0;
5502 }
5503
5504 ++input_line_pointer;
5505 SKIP_WHITESPACE ();
5506
5507 if (isupper (c1))
5508 c1 = tolower (c1);
5509 if (isupper (c2))
5510 c2 = tolower (c2);
5511
5512 *pcc = (c1 << 8) | c2;
5513
5514 return 1;
5515 }
5516
5517 /* Parse a single operand in an MRI structured control expression. */
5518
5519 static int
5520 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5521 int *pcc;
5522 char **leftstart;
5523 char **leftstop;
5524 char **rightstart;
5525 char **rightstop;
5526 {
5527 char *s;
5528
5529 SKIP_WHITESPACE ();
5530
5531 *pcc = -1;
5532 *leftstart = NULL;
5533 *leftstop = NULL;
5534 *rightstart = NULL;
5535 *rightstop = NULL;
5536
5537 if (*input_line_pointer == '<')
5538 {
5539 /* It's just a condition code. */
5540 return parse_mri_condition (pcc);
5541 }
5542
5543 /* Look ahead for the condition code. */
5544 for (s = input_line_pointer; *s != '\0'; ++s)
5545 {
5546 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5547 break;
5548 }
5549 if (*s == '\0')
5550 {
5551 as_bad ("missing condition code in structured control directive");
5552 return 0;
5553 }
5554
5555 *leftstart = input_line_pointer;
5556 *leftstop = s;
5557 if (*leftstop > *leftstart
5558 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5559 --*leftstop;
5560
5561 input_line_pointer = s;
5562 if (! parse_mri_condition (pcc))
5563 return 0;
5564
5565 /* Look ahead for AND or OR or end of line. */
5566 for (s = input_line_pointer; *s != '\0'; ++s)
5567 {
5568 if ((strncasecmp (s, "AND", 3) == 0
5569 && (s[3] == '.' || ! is_part_of_name (s[3])))
5570 || (strncasecmp (s, "OR", 2) == 0
5571 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5572 break;
5573 }
5574
5575 *rightstart = input_line_pointer;
5576 *rightstop = s;
5577 if (*rightstop > *rightstart
5578 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5579 --*rightstop;
5580
5581 input_line_pointer = s;
5582
5583 return 1;
5584 }
5585
5586 #define MCC(b1, b2) (((b1) << 8) | (b2))
5587
5588 /* Swap the sense of a condition. This changes the condition so that
5589 it generates the same result when the operands are swapped. */
5590
5591 static int
5592 swap_mri_condition (cc)
5593 int cc;
5594 {
5595 switch (cc)
5596 {
5597 case MCC ('h', 'i'): return MCC ('c', 's');
5598 case MCC ('l', 's'): return MCC ('c', 'c');
5599 case MCC ('c', 'c'): return MCC ('l', 's');
5600 case MCC ('c', 's'): return MCC ('h', 'i');
5601 case MCC ('p', 'l'): return MCC ('m', 'i');
5602 case MCC ('m', 'i'): return MCC ('p', 'l');
5603 case MCC ('g', 'e'): return MCC ('l', 'e');
5604 case MCC ('l', 't'): return MCC ('g', 't');
5605 case MCC ('g', 't'): return MCC ('l', 't');
5606 case MCC ('l', 'e'): return MCC ('g', 'e');
5607 }
5608 return cc;
5609 }
5610
5611 /* Reverse the sense of a condition. */
5612
5613 static int
5614 reverse_mri_condition (cc)
5615 int cc;
5616 {
5617 switch (cc)
5618 {
5619 case MCC ('h', 'i'): return MCC ('l', 's');
5620 case MCC ('l', 's'): return MCC ('h', 'i');
5621 case MCC ('c', 'c'): return MCC ('c', 's');
5622 case MCC ('c', 's'): return MCC ('c', 'c');
5623 case MCC ('n', 'e'): return MCC ('e', 'q');
5624 case MCC ('e', 'q'): return MCC ('n', 'e');
5625 case MCC ('v', 'c'): return MCC ('v', 's');
5626 case MCC ('v', 's'): return MCC ('v', 'c');
5627 case MCC ('p', 'l'): return MCC ('m', 'i');
5628 case MCC ('m', 'i'): return MCC ('p', 'l');
5629 case MCC ('g', 'e'): return MCC ('l', 't');
5630 case MCC ('l', 't'): return MCC ('g', 'e');
5631 case MCC ('g', 't'): return MCC ('l', 'e');
5632 case MCC ('l', 'e'): return MCC ('g', 't');
5633 }
5634 return cc;
5635 }
5636
5637 /* Build an MRI structured control expression. This generates test
5638 and branch instructions. It goes to TRUELAB if the condition is
5639 true, and to FALSELAB if the condition is false. Exactly one of
5640 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5641 is the size qualifier for the expression. EXTENT is the size to
5642 use for the branch. */
5643
5644 static void
5645 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5646 rightstop, truelab, falselab, extent)
5647 int qual;
5648 int cc;
5649 char *leftstart;
5650 char *leftstop;
5651 char *rightstart;
5652 char *rightstop;
5653 const char *truelab;
5654 const char *falselab;
5655 int extent;
5656 {
5657 char *buf;
5658 char *s;
5659
5660 if (leftstart != NULL)
5661 {
5662 struct m68k_op leftop, rightop;
5663 char c;
5664
5665 /* Swap the compare operands, if necessary, to produce a legal
5666 m68k compare instruction. Comparing a register operand with
5667 a non-register operand requires the register to be on the
5668 right (cmp, cmpa). Comparing an immediate value with
5669 anything requires the immediate value to be on the left
5670 (cmpi). */
5671
5672 c = *leftstop;
5673 *leftstop = '\0';
5674 (void) m68k_ip_op (leftstart, &leftop);
5675 *leftstop = c;
5676
5677 c = *rightstop;
5678 *rightstop = '\0';
5679 (void) m68k_ip_op (rightstart, &rightop);
5680 *rightstop = c;
5681
5682 if (rightop.mode == IMMED
5683 || ((leftop.mode == DREG || leftop.mode == AREG)
5684 && (rightop.mode != DREG && rightop.mode != AREG)))
5685 {
5686 char *temp;
5687
5688 cc = swap_mri_condition (cc);
5689 temp = leftstart;
5690 leftstart = rightstart;
5691 rightstart = temp;
5692 temp = leftstop;
5693 leftstop = rightstop;
5694 rightstop = temp;
5695 }
5696 }
5697
5698 if (truelab == NULL)
5699 {
5700 cc = reverse_mri_condition (cc);
5701 truelab = falselab;
5702 }
5703
5704 if (leftstart != NULL)
5705 {
5706 buf = (char *) xmalloc (20
5707 + (leftstop - leftstart)
5708 + (rightstop - rightstart));
5709 s = buf;
5710 *s++ = 'c';
5711 *s++ = 'm';
5712 *s++ = 'p';
5713 if (qual != '\0')
5714 *s++ = qual;
5715 *s++ = ' ';
5716 memcpy (s, leftstart, leftstop - leftstart);
5717 s += leftstop - leftstart;
5718 *s++ = ',';
5719 memcpy (s, rightstart, rightstop - rightstart);
5720 s += rightstop - rightstart;
5721 *s = '\0';
5722 md_assemble (buf);
5723 free (buf);
5724 }
5725
5726 buf = (char *) xmalloc (20 + strlen (truelab));
5727 s = buf;
5728 *s++ = 'b';
5729 *s++ = cc >> 8;
5730 *s++ = cc & 0xff;
5731 if (extent != '\0')
5732 *s++ = extent;
5733 *s++ = ' ';
5734 strcpy (s, truelab);
5735 md_assemble (buf);
5736 free (buf);
5737 }
5738
5739 /* Parse an MRI structured control expression. This generates test
5740 and branch instructions. STOP is where the expression ends. It
5741 goes to TRUELAB if the condition is true, and to FALSELAB if the
5742 condition is false. Exactly one of TRUELAB and FALSELAB will be
5743 NULL, meaning to fall through. QUAL is the size qualifier for the
5744 expression. EXTENT is the size to use for the branch. */
5745
5746 static void
5747 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5748 char *stop;
5749 int qual;
5750 const char *truelab;
5751 const char *falselab;
5752 int extent;
5753 {
5754 int c;
5755 int cc;
5756 char *leftstart;
5757 char *leftstop;
5758 char *rightstart;
5759 char *rightstop;
5760
5761 c = *stop;
5762 *stop = '\0';
5763
5764 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5765 &rightstart, &rightstop))
5766 {
5767 *stop = c;
5768 return;
5769 }
5770
5771 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5772 {
5773 const char *flab;
5774
5775 if (falselab != NULL)
5776 flab = falselab;
5777 else
5778 flab = mri_control_label ();
5779
5780 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5781 rightstop, (const char *) NULL, flab, extent);
5782
5783 input_line_pointer += 3;
5784 if (*input_line_pointer != '.'
5785 || input_line_pointer[1] == '\0')
5786 qual = '\0';
5787 else
5788 {
5789 qual = input_line_pointer[1];
5790 input_line_pointer += 2;
5791 }
5792
5793 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5794 &rightstart, &rightstop))
5795 {
5796 *stop = c;
5797 return;
5798 }
5799
5800 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5801 rightstop, truelab, falselab, extent);
5802
5803 if (falselab == NULL)
5804 colon (flab);
5805 }
5806 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5807 {
5808 const char *tlab;
5809
5810 if (truelab != NULL)
5811 tlab = truelab;
5812 else
5813 tlab = mri_control_label ();
5814
5815 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5816 rightstop, tlab, (const char *) NULL, extent);
5817
5818 input_line_pointer += 2;
5819 if (*input_line_pointer != '.'
5820 || input_line_pointer[1] == '\0')
5821 qual = '\0';
5822 else
5823 {
5824 qual = input_line_pointer[1];
5825 input_line_pointer += 2;
5826 }
5827
5828 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5829 &rightstart, &rightstop))
5830 {
5831 *stop = c;
5832 return;
5833 }
5834
5835 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5836 rightstop, truelab, falselab, extent);
5837
5838 if (truelab == NULL)
5839 colon (tlab);
5840 }
5841 else
5842 {
5843 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5844 rightstop, truelab, falselab, extent);
5845 }
5846
5847 *stop = c;
5848 if (input_line_pointer != stop)
5849 as_bad ("syntax error in structured control directive");
5850 }
5851
5852 /* Handle the MRI IF pseudo-op. This may be a structured control
5853 directive, or it may be a regular assembler conditional, depending
5854 on its operands. */
5855
5856 static void
5857 s_mri_if (qual)
5858 int qual;
5859 {
5860 char *s;
5861 int c;
5862 struct mri_control_info *n;
5863
5864 /* A structured control directive must end with THEN with an
5865 optional qualifier. */
5866 s = input_line_pointer;
5867 while (! is_end_of_line[(unsigned char) *s]
5868 && (! flag_mri || *s != '*'))
5869 ++s;
5870 --s;
5871 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5872 --s;
5873
5874 if (s - input_line_pointer > 1
5875 && s[-1] == '.')
5876 s -= 2;
5877
5878 if (s - input_line_pointer < 3
5879 || strncasecmp (s - 3, "THEN", 4) != 0)
5880 {
5881 if (qual != '\0')
5882 {
5883 as_bad ("missing then");
5884 ignore_rest_of_line ();
5885 return;
5886 }
5887
5888 /* It's a conditional. */
5889 s_if (O_ne);
5890 return;
5891 }
5892
5893 /* Since this might be a conditional if, this pseudo-op will be
5894 called even if we are supported to be ignoring input. Double
5895 check now. Clobber *input_line_pointer so that ignore_input
5896 thinks that this is not a special pseudo-op. */
5897 c = *input_line_pointer;
5898 *input_line_pointer = 0;
5899 if (ignore_input ())
5900 {
5901 *input_line_pointer = c;
5902 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5903 ++input_line_pointer;
5904 demand_empty_rest_of_line ();
5905 return;
5906 }
5907 *input_line_pointer = c;
5908
5909 n = push_mri_control (mri_if);
5910
5911 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5912 n->next, s[1] == '.' ? s[2] : '\0');
5913
5914 if (s[1] == '.')
5915 input_line_pointer = s + 3;
5916 else
5917 input_line_pointer = s + 1;
5918
5919 if (flag_mri)
5920 {
5921 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5922 ++input_line_pointer;
5923 }
5924
5925 demand_empty_rest_of_line ();
5926 }
5927
5928 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5929 structured IF, associate the ELSE with the IF. Otherwise, assume
5930 it is a conditional else. */
5931
5932 static void
5933 s_mri_else (qual)
5934 int qual;
5935 {
5936 int c;
5937 char *buf;
5938 char q[2];
5939
5940 if (qual == '\0'
5941 && (mri_control_stack == NULL
5942 || mri_control_stack->type != mri_if
5943 || mri_control_stack->else_seen))
5944 {
5945 s_else (0);
5946 return;
5947 }
5948
5949 c = *input_line_pointer;
5950 *input_line_pointer = 0;
5951 if (ignore_input ())
5952 {
5953 *input_line_pointer = c;
5954 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5955 ++input_line_pointer;
5956 demand_empty_rest_of_line ();
5957 return;
5958 }
5959 *input_line_pointer = c;
5960
5961 if (mri_control_stack == NULL
5962 || mri_control_stack->type != mri_if
5963 || mri_control_stack->else_seen)
5964 {
5965 as_bad ("else without matching if");
5966 ignore_rest_of_line ();
5967 return;
5968 }
5969
5970 mri_control_stack->else_seen = 1;
5971
5972 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5973 q[0] = qual;
5974 q[1] = '\0';
5975 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5976 md_assemble (buf);
5977 free (buf);
5978
5979 colon (mri_control_stack->next);
5980
5981 if (flag_mri)
5982 {
5983 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5984 ++input_line_pointer;
5985 }
5986
5987 demand_empty_rest_of_line ();
5988 }
5989
5990 /* Handle the MRI ENDI pseudo-op. */
5991
5992 static void
5993 s_mri_endi (ignore)
5994 int ignore;
5995 {
5996 if (mri_control_stack == NULL
5997 || mri_control_stack->type != mri_if)
5998 {
5999 as_bad ("endi without matching if");
6000 ignore_rest_of_line ();
6001 return;
6002 }
6003
6004 /* ignore_input will not return true for ENDI, so we don't need to
6005 worry about checking it again here. */
6006
6007 if (! mri_control_stack->else_seen)
6008 colon (mri_control_stack->next);
6009 colon (mri_control_stack->bottom);
6010
6011 pop_mri_control ();
6012
6013 if (flag_mri)
6014 {
6015 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6016 ++input_line_pointer;
6017 }
6018
6019 demand_empty_rest_of_line ();
6020 }
6021
6022 /* Handle the MRI BREAK pseudo-op. */
6023
6024 static void
6025 s_mri_break (extent)
6026 int extent;
6027 {
6028 struct mri_control_info *n;
6029 char *buf;
6030 char ex[2];
6031
6032 n = mri_control_stack;
6033 while (n != NULL
6034 && n->type != mri_for
6035 && n->type != mri_repeat
6036 && n->type != mri_while)
6037 n = n->outer;
6038 if (n == NULL)
6039 {
6040 as_bad ("break outside of structured loop");
6041 ignore_rest_of_line ();
6042 return;
6043 }
6044
6045 buf = (char *) xmalloc (20 + strlen (n->bottom));
6046 ex[0] = extent;
6047 ex[1] = '\0';
6048 sprintf (buf, "bra%s %s", ex, n->bottom);
6049 md_assemble (buf);
6050 free (buf);
6051
6052 if (flag_mri)
6053 {
6054 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6055 ++input_line_pointer;
6056 }
6057
6058 demand_empty_rest_of_line ();
6059 }
6060
6061 /* Handle the MRI NEXT pseudo-op. */
6062
6063 static void
6064 s_mri_next (extent)
6065 int extent;
6066 {
6067 struct mri_control_info *n;
6068 char *buf;
6069 char ex[2];
6070
6071 n = mri_control_stack;
6072 while (n != NULL
6073 && n->type != mri_for
6074 && n->type != mri_repeat
6075 && n->type != mri_while)
6076 n = n->outer;
6077 if (n == NULL)
6078 {
6079 as_bad ("next outside of structured loop");
6080 ignore_rest_of_line ();
6081 return;
6082 }
6083
6084 buf = (char *) xmalloc (20 + strlen (n->next));
6085 ex[0] = extent;
6086 ex[1] = '\0';
6087 sprintf (buf, "bra%s %s", ex, n->next);
6088 md_assemble (buf);
6089 free (buf);
6090
6091 if (flag_mri)
6092 {
6093 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6094 ++input_line_pointer;
6095 }
6096
6097 demand_empty_rest_of_line ();
6098 }
6099
6100 /* Handle the MRI FOR pseudo-op. */
6101
6102 static void
6103 s_mri_for (qual)
6104 int qual;
6105 {
6106 const char *varstart, *varstop;
6107 const char *initstart, *initstop;
6108 const char *endstart, *endstop;
6109 const char *bystart, *bystop;
6110 int up;
6111 int by;
6112 int extent;
6113 struct mri_control_info *n;
6114 char *buf;
6115 char *s;
6116 char ex[2];
6117
6118 /* The syntax is
6119 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6120 */
6121
6122 SKIP_WHITESPACE ();
6123 varstart = input_line_pointer;
6124
6125 /* Look for the '='. */
6126 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6127 && *input_line_pointer != '=')
6128 ++input_line_pointer;
6129 if (*input_line_pointer != '=')
6130 {
6131 as_bad ("missing =");
6132 ignore_rest_of_line ();
6133 return;
6134 }
6135
6136 varstop = input_line_pointer;
6137 if (varstop > varstart
6138 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6139 --varstop;
6140
6141 ++input_line_pointer;
6142
6143 initstart = input_line_pointer;
6144
6145 /* Look for TO or DOWNTO. */
6146 up = 1;
6147 initstop = NULL;
6148 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6149 {
6150 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6151 && ! is_part_of_name (input_line_pointer[2]))
6152 {
6153 initstop = input_line_pointer;
6154 input_line_pointer += 2;
6155 break;
6156 }
6157 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6158 && ! is_part_of_name (input_line_pointer[6]))
6159 {
6160 initstop = input_line_pointer;
6161 up = 0;
6162 input_line_pointer += 6;
6163 break;
6164 }
6165 ++input_line_pointer;
6166 }
6167 if (initstop == NULL)
6168 {
6169 as_bad ("missing to or downto");
6170 ignore_rest_of_line ();
6171 return;
6172 }
6173 if (initstop > initstart
6174 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6175 --initstop;
6176
6177 SKIP_WHITESPACE ();
6178 endstart = input_line_pointer;
6179
6180 /* Look for BY or DO. */
6181 by = 0;
6182 endstop = NULL;
6183 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6184 {
6185 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6186 && ! is_part_of_name (input_line_pointer[2]))
6187 {
6188 endstop = input_line_pointer;
6189 by = 1;
6190 input_line_pointer += 2;
6191 break;
6192 }
6193 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6194 && (input_line_pointer[2] == '.'
6195 || ! is_part_of_name (input_line_pointer[2])))
6196 {
6197 endstop = input_line_pointer;
6198 input_line_pointer += 2;
6199 break;
6200 }
6201 ++input_line_pointer;
6202 }
6203 if (endstop == NULL)
6204 {
6205 as_bad ("missing do");
6206 ignore_rest_of_line ();
6207 return;
6208 }
6209 if (endstop > endstart
6210 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6211 --endstop;
6212
6213 if (! by)
6214 {
6215 bystart = "#1";
6216 bystop = bystart + 2;
6217 }
6218 else
6219 {
6220 SKIP_WHITESPACE ();
6221 bystart = input_line_pointer;
6222
6223 /* Look for DO. */
6224 bystop = NULL;
6225 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6226 {
6227 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6228 && (input_line_pointer[2] == '.'
6229 || ! is_part_of_name (input_line_pointer[2])))
6230 {
6231 bystop = input_line_pointer;
6232 input_line_pointer += 2;
6233 break;
6234 }
6235 ++input_line_pointer;
6236 }
6237 if (bystop == NULL)
6238 {
6239 as_bad ("missing do");
6240 ignore_rest_of_line ();
6241 return;
6242 }
6243 if (bystop > bystart
6244 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6245 --bystop;
6246 }
6247
6248 if (*input_line_pointer != '.')
6249 extent = '\0';
6250 else
6251 {
6252 extent = input_line_pointer[1];
6253 input_line_pointer += 2;
6254 }
6255
6256 /* We have fully parsed the FOR operands. Now build the loop. */
6257
6258 n = push_mri_control (mri_for);
6259
6260 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6261
6262 /* move init,var */
6263 s = buf;
6264 *s++ = 'm';
6265 *s++ = 'o';
6266 *s++ = 'v';
6267 *s++ = 'e';
6268 if (qual != '\0')
6269 *s++ = qual;
6270 *s++ = ' ';
6271 memcpy (s, initstart, initstop - initstart);
6272 s += initstop - initstart;
6273 *s++ = ',';
6274 memcpy (s, varstart, varstop - varstart);
6275 s += varstop - varstart;
6276 *s = '\0';
6277 md_assemble (buf);
6278
6279 colon (n->top);
6280
6281 /* cmp end,var */
6282 s = buf;
6283 *s++ = 'c';
6284 *s++ = 'm';
6285 *s++ = 'p';
6286 if (qual != '\0')
6287 *s++ = qual;
6288 *s++ = ' ';
6289 memcpy (s, endstart, endstop - endstart);
6290 s += endstop - endstart;
6291 *s++ = ',';
6292 memcpy (s, varstart, varstop - varstart);
6293 s += varstop - varstart;
6294 *s = '\0';
6295 md_assemble (buf);
6296
6297 /* bcc bottom */
6298 ex[0] = extent;
6299 ex[1] = '\0';
6300 if (up)
6301 sprintf (buf, "blt%s %s", ex, n->bottom);
6302 else
6303 sprintf (buf, "bgt%s %s", ex, n->bottom);
6304 md_assemble (buf);
6305
6306 /* Put together the add or sub instruction used by ENDF. */
6307 s = buf;
6308 if (up)
6309 strcpy (s, "add");
6310 else
6311 strcpy (s, "sub");
6312 s += 3;
6313 if (qual != '\0')
6314 *s++ = qual;
6315 *s++ = ' ';
6316 memcpy (s, bystart, bystop - bystart);
6317 s += bystop - bystart;
6318 *s++ = ',';
6319 memcpy (s, varstart, varstop - varstart);
6320 s += varstop - varstart;
6321 *s = '\0';
6322 n->incr = buf;
6323
6324 if (flag_mri)
6325 {
6326 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6327 ++input_line_pointer;
6328 }
6329
6330 demand_empty_rest_of_line ();
6331 }
6332
6333 /* Handle the MRI ENDF pseudo-op. */
6334
6335 static void
6336 s_mri_endf (ignore)
6337 int ignore;
6338 {
6339 if (mri_control_stack == NULL
6340 || mri_control_stack->type != mri_for)
6341 {
6342 as_bad ("endf without for");
6343 ignore_rest_of_line ();
6344 return;
6345 }
6346
6347 colon (mri_control_stack->next);
6348
6349 md_assemble (mri_control_stack->incr);
6350
6351 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6352 md_assemble (mri_control_stack->incr);
6353
6354 free (mri_control_stack->incr);
6355
6356 colon (mri_control_stack->bottom);
6357
6358 pop_mri_control ();
6359
6360 if (flag_mri)
6361 {
6362 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6363 ++input_line_pointer;
6364 }
6365
6366 demand_empty_rest_of_line ();
6367 }
6368
6369 /* Handle the MRI REPEAT pseudo-op. */
6370
6371 static void
6372 s_mri_repeat (ignore)
6373 int ignore;
6374 {
6375 struct mri_control_info *n;
6376
6377 n = push_mri_control (mri_repeat);
6378 colon (n->top);
6379 if (flag_mri)
6380 {
6381 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6382 ++input_line_pointer;
6383 }
6384 demand_empty_rest_of_line ();
6385 }
6386
6387 /* Handle the MRI UNTIL pseudo-op. */
6388
6389 static void
6390 s_mri_until (qual)
6391 int qual;
6392 {
6393 char *s;
6394
6395 if (mri_control_stack == NULL
6396 || mri_control_stack->type != mri_repeat)
6397 {
6398 as_bad ("until without repeat");
6399 ignore_rest_of_line ();
6400 return;
6401 }
6402
6403 colon (mri_control_stack->next);
6404
6405 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6406 ;
6407
6408 parse_mri_control_expression (s, qual, (const char *) NULL,
6409 mri_control_stack->top, '\0');
6410
6411 colon (mri_control_stack->bottom);
6412
6413 input_line_pointer = s;
6414
6415 pop_mri_control ();
6416
6417 if (flag_mri)
6418 {
6419 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6420 ++input_line_pointer;
6421 }
6422
6423 demand_empty_rest_of_line ();
6424 }
6425
6426 /* Handle the MRI WHILE pseudo-op. */
6427
6428 static void
6429 s_mri_while (qual)
6430 int qual;
6431 {
6432 char *s;
6433
6434 struct mri_control_info *n;
6435
6436 s = input_line_pointer;
6437 while (! is_end_of_line[(unsigned char) *s]
6438 && (! flag_mri || *s != '*'))
6439 s++;
6440 --s;
6441 while (*s == ' ' || *s == '\t')
6442 --s;
6443 if (s - input_line_pointer > 1
6444 && s[-1] == '.')
6445 s -= 2;
6446 if (s - input_line_pointer < 2
6447 || strncasecmp (s - 1, "DO", 2) != 0)
6448 {
6449 as_bad ("missing do");
6450 ignore_rest_of_line ();
6451 return;
6452 }
6453
6454 n = push_mri_control (mri_while);
6455
6456 colon (n->next);
6457
6458 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6459 s[1] == '.' ? s[2] : '\0');
6460
6461 input_line_pointer = s + 1;
6462 if (*input_line_pointer == '.')
6463 input_line_pointer += 2;
6464
6465 if (flag_mri)
6466 {
6467 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6468 ++input_line_pointer;
6469 }
6470
6471 demand_empty_rest_of_line ();
6472 }
6473
6474 /* Handle the MRI ENDW pseudo-op. */
6475
6476 static void
6477 s_mri_endw (ignore)
6478 int ignore;
6479 {
6480 char *buf;
6481
6482 if (mri_control_stack == NULL
6483 || mri_control_stack->type != mri_while)
6484 {
6485 as_bad ("endw without while");
6486 ignore_rest_of_line ();
6487 return;
6488 }
6489
6490 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6491 sprintf (buf, "bra %s", mri_control_stack->next);
6492 md_assemble (buf);
6493 free (buf);
6494
6495 colon (mri_control_stack->bottom);
6496
6497 pop_mri_control ();
6498
6499 if (flag_mri)
6500 {
6501 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6502 ++input_line_pointer;
6503 }
6504
6505 demand_empty_rest_of_line ();
6506 }
6507 \f
6508 /*
6509 * md_parse_option
6510 * Invocation line includes a switch not recognized by the base assembler.
6511 * See if it's a processor-specific option. These are:
6512 *
6513 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6514 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6515 * Select the architecture. Instructions or features not
6516 * supported by the selected architecture cause fatal
6517 * errors. More than one may be specified. The default is
6518 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6519 * for -m68000, and -m68882 is a synonym for -m68881.
6520 * -[A]m[c]no-68851, -[A]m[c]no-68881
6521 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6522 * so don't use or document it, but that's the way the parsing
6523 * works).
6524 *
6525 * -pic Indicates PIC.
6526 * -k Indicates PIC. (Sun 3 only.)
6527 *
6528 * --bitwise-or
6529 * Permit `|' to be used in expressions.
6530 *
6531 */
6532
6533 #ifdef OBJ_ELF
6534 CONST char *md_shortopts = "lSA:m:kQ:V";
6535 #else
6536 CONST char *md_shortopts = "lSA:m:k";
6537 #endif
6538
6539 struct option md_longopts[] = {
6540 #define OPTION_PIC (OPTION_MD_BASE)
6541 {"pic", no_argument, NULL, OPTION_PIC},
6542 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6543 {"register-prefix-optional", no_argument, NULL,
6544 OPTION_REGISTER_PREFIX_OPTIONAL},
6545 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6546 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6547 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6548 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6549 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6550 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6551 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6552 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6553 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6554 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6555 {NULL, no_argument, NULL, 0}
6556 };
6557 size_t md_longopts_size = sizeof(md_longopts);
6558
6559 int
6560 md_parse_option (c, arg)
6561 int c;
6562 char *arg;
6563 {
6564 switch (c)
6565 {
6566 case 'l': /* -l means keep external to 2 bit offset
6567 rather than 16 bit one */
6568 flag_short_refs = 1;
6569 break;
6570
6571 case 'S': /* -S means that jbsr's always turn into
6572 jsr's. */
6573 flag_long_jumps = 1;
6574 break;
6575
6576 case 'A':
6577 if (*arg == 'm')
6578 arg++;
6579 /* intentional fall-through */
6580 case 'm':
6581
6582 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6583 {
6584 int i;
6585 unsigned long arch;
6586 const char *oarg = arg;
6587
6588 arg += 3;
6589 if (*arg == 'm')
6590 {
6591 arg++;
6592 if (arg[0] == 'c' && arg[1] == '6')
6593 arg++;
6594 }
6595 for (i = 0; i < n_archs; i++)
6596 if (!strcmp (arg, archs[i].name))
6597 break;
6598 if (i == n_archs)
6599 {
6600 unknown:
6601 as_bad ("unrecognized option `%s'", oarg);
6602 return 0;
6603 }
6604 arch = archs[i].arch;
6605 if (arch == m68881)
6606 no_68881 = 1;
6607 else if (arch == m68851)
6608 no_68851 = 1;
6609 else
6610 goto unknown;
6611 }
6612 else
6613 {
6614 int i;
6615
6616 if (arg[0] == 'c' && arg[1] == '6')
6617 arg++;
6618
6619 for (i = 0; i < n_archs; i++)
6620 if (!strcmp (arg, archs[i].name))
6621 {
6622 unsigned long arch = archs[i].arch;
6623 if (cpu_of_arch (arch))
6624 /* It's a cpu spec. */
6625 {
6626 current_architecture &= ~m68000up;
6627 current_architecture |= arch;
6628 }
6629 else if (arch == m68881)
6630 {
6631 current_architecture |= m68881;
6632 no_68881 = 0;
6633 }
6634 else if (arch == m68851)
6635 {
6636 current_architecture |= m68851;
6637 no_68851 = 0;
6638 }
6639 else
6640 /* ??? */
6641 abort ();
6642 break;
6643 }
6644 if (i == n_archs)
6645 {
6646 as_bad ("unrecognized architecture specification `%s'", arg);
6647 return 0;
6648 }
6649 }
6650 break;
6651
6652 case OPTION_PIC:
6653 case 'k':
6654 flag_want_pic = 1;
6655 break; /* -pic, Position Independent Code */
6656
6657 case OPTION_REGISTER_PREFIX_OPTIONAL:
6658 flag_reg_prefix_optional = 1;
6659 reg_prefix_optional_seen = 1;
6660 break;
6661
6662 /* -V: SVR4 argument to print version ID. */
6663 case 'V':
6664 print_version_id ();
6665 break;
6666
6667 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6668 should be emitted or not. FIXME: Not implemented. */
6669 case 'Q':
6670 break;
6671
6672 case OPTION_BITWISE_OR:
6673 {
6674 char *n, *t;
6675 const char *s;
6676
6677 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6678 t = n;
6679 for (s = m68k_comment_chars; *s != '\0'; s++)
6680 if (*s != '|')
6681 *t++ = *s;
6682 *t = '\0';
6683 m68k_comment_chars = n;
6684 }
6685 break;
6686
6687 case OPTION_BASE_SIZE_DEFAULT_16:
6688 m68k_index_width_default = SIZE_WORD;
6689 break;
6690
6691 case OPTION_BASE_SIZE_DEFAULT_32:
6692 m68k_index_width_default = SIZE_LONG;
6693 break;
6694
6695 case OPTION_DISP_SIZE_DEFAULT_16:
6696 m68k_rel32 = 0;
6697 m68k_rel32_from_cmdline = 1;
6698 break;
6699
6700 case OPTION_DISP_SIZE_DEFAULT_32:
6701 m68k_rel32 = 1;
6702 m68k_rel32_from_cmdline = 1;
6703 break;
6704
6705 default:
6706 return 0;
6707 }
6708
6709 return 1;
6710 }
6711
6712 void
6713 md_show_usage (stream)
6714 FILE *stream;
6715 {
6716 fprintf(stream, "\
6717 680X0 options:\n\
6718 -l use 1 word for refs to undefined symbols [default 2]\n\
6719 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6720 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6721 | -mcpu32 | -m5200\n\
6722 specify variant of 680X0 architecture [default 68020]\n\
6723 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6724 target has/lacks floating-point coprocessor\n\
6725 [default yes for 68020, 68030, and cpu32]\n");
6726 fprintf(stream, "\
6727 -m68851 | -mno-68851\n\
6728 target has/lacks memory-management unit coprocessor\n\
6729 [default yes for 68020 and up]\n\
6730 -pic, -k generate position independent code\n\
6731 -S turn jbsr into jsr\n\
6732 --register-prefix-optional\n\
6733 recognize register names without prefix character\n\
6734 --bitwise-or do not treat `|' as a comment character\n");
6735 fprintf (stream, "\
6736 --base-size-default-16 base reg without size is 16 bits\n\
6737 --base-size-default-32 base reg without size is 32 bits (default)\n\
6738 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6739 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6740 }
6741 \f
6742 #ifdef TEST2
6743
6744 /* TEST2: Test md_assemble() */
6745 /* Warning, this routine probably doesn't work anymore */
6746
6747 main ()
6748 {
6749 struct m68k_it the_ins;
6750 char buf[120];
6751 char *cp;
6752 int n;
6753
6754 m68k_ip_begin ();
6755 for (;;)
6756 {
6757 if (!gets (buf) || !*buf)
6758 break;
6759 if (buf[0] == '|' || buf[1] == '.')
6760 continue;
6761 for (cp = buf; *cp; cp++)
6762 if (*cp == '\t')
6763 *cp = ' ';
6764 if (is_label (buf))
6765 continue;
6766 memset (&the_ins, '\0', sizeof (the_ins));
6767 m68k_ip (&the_ins, buf);
6768 if (the_ins.error)
6769 {
6770 printf ("Error %s in %s\n", the_ins.error, buf);
6771 }
6772 else
6773 {
6774 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6775 for (n = 0; n < the_ins.numo; n++)
6776 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6777 printf (" ");
6778 print_the_insn (&the_ins.opcode[0], stdout);
6779 (void) putchar ('\n');
6780 }
6781 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6782 {
6783 if (the_ins.operands[n].error)
6784 {
6785 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6786 continue;
6787 }
6788 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6789 if (the_ins.operands[n].b_const)
6790 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6791 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6792 if (the_ins.operands[n].b_iadd)
6793 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6794 (void) putchar ('\n');
6795 }
6796 }
6797 m68k_ip_end ();
6798 return 0;
6799 }
6800
6801 is_label (str)
6802 char *str;
6803 {
6804 while (*str == ' ')
6805 str++;
6806 while (*str && *str != ' ')
6807 str++;
6808 if (str[-1] == ':' || str[1] == '=')
6809 return 1;
6810 return 0;
6811 }
6812
6813 #endif
6814
6815 /* Possible states for relaxation:
6816
6817 0 0 branch offset byte (bra, etc)
6818 0 1 word
6819 0 2 long
6820
6821 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6822 1 1 word
6823 1 2 long
6824
6825 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6826 2 1 word-long
6827 2 2 long-word
6828 2 3 long-long
6829
6830 */
6831
6832 /* We have no need to default values of symbols. */
6833
6834 /* ARGSUSED */
6835 symbolS *
6836 md_undefined_symbol (name)
6837 char *name;
6838 {
6839 return 0;
6840 }
6841
6842 /* Round up a section size to the appropriate boundary. */
6843 valueT
6844 md_section_align (segment, size)
6845 segT segment;
6846 valueT size;
6847 {
6848 #ifdef OBJ_AOUT
6849 #ifdef BFD_ASSEMBLER
6850 /* For a.out, force the section size to be aligned. If we don't do
6851 this, BFD will align it for us, but it will not write out the
6852 final bytes of the section. This may be a bug in BFD, but it is
6853 easier to fix it here since that is how the other a.out targets
6854 work. */
6855 int align;
6856
6857 align = bfd_get_section_alignment (stdoutput, segment);
6858 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6859 #endif
6860 #endif
6861
6862 return size;
6863 }
6864
6865 /* Exactly what point is a PC-relative offset relative TO?
6866 On the 68k, it is relative to the address of the first extension
6867 word. The difference between the addresses of the offset and the
6868 first extension word is stored in fx_pcrel_adjust. */
6869 long
6870 md_pcrel_from (fixP)
6871 fixS *fixP;
6872 {
6873 int adjust;
6874
6875 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6876 -1 as 64. */
6877 adjust = fixP->fx_pcrel_adjust;
6878 if (adjust == 64)
6879 adjust = -1;
6880 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6881 }
6882
6883 #ifndef BFD_ASSEMBLER
6884 #ifdef OBJ_COFF
6885
6886 /*ARGSUSED*/
6887 void
6888 tc_coff_symbol_emit_hook (ignore)
6889 symbolS *ignore;
6890 {
6891 }
6892
6893 int
6894 tc_coff_sizemachdep (frag)
6895 fragS *frag;
6896 {
6897 switch (frag->fr_subtype & 0x3)
6898 {
6899 case BYTE:
6900 return 1;
6901 case SHORT:
6902 return 2;
6903 case LONG:
6904 return 4;
6905 default:
6906 abort ();
6907 return 0;
6908 }
6909 }
6910
6911 #endif
6912 #endif
6913
6914 /* end of tc-m68k.c */