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[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This string holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful. The macro
32 tc_comment_chars points to this. We use this, rather than the
33 usual comment_chars, so that the --bitwise-or option will work. */
34 #if defined (TE_SVR4) || defined (TE_DELTA)
35 const char *m68k_comment_chars = "|#";
36 #else
37 const char *m68k_comment_chars = "|";
38 #endif
39
40 /* This array holds the chars that only start a comment at the beginning of
41 a line. If the line seems to have the form '# 123 filename'
42 .line and .file directives will appear in the pre-processed output */
43 /* Note that input_file.c hand checks for '#' at the beginning of the
44 first line of the input file. This is because the compiler outputs
45 #NO_APP at the beginning of its output. */
46 /* Also note that comments like this one will always work. */
47 const char line_comment_chars[] = "#*";
48
49 const char line_separator_chars[] = "";
50
51 /* Chars that can be used to separate mant from exp in floating point nums */
52 CONST char EXP_CHARS[] = "eE";
53
54 /* Chars that mean this number is a floating point constant, as
55 in "0f12.456" or "0d1.2345e12". */
56
57 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
58
59 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
60 changed in read.c . Ideally it shouldn't have to know about it at all,
61 but nothing is ideal around here. */
62
63 const int md_reloc_size = 8; /* Size of relocation record */
64
65 /* Are we trying to generate PIC code? If so, absolute references
66 ought to be made into linkage table references or pc-relative
67 references. Not implemented. For ELF there are other means
68 to denote pic relocations. */
69 int flag_want_pic;
70
71 static int flag_short_refs; /* -l option */
72 static int flag_long_jumps; /* -S option */
73
74 #ifdef REGISTER_PREFIX_OPTIONAL
75 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
76 #else
77 int flag_reg_prefix_optional;
78 #endif
79
80 /* Whether --register-prefix-optional was used on the command line. */
81 static int reg_prefix_optional_seen;
82
83 /* The floating point coprocessor to use by default. */
84 static enum m68k_register m68k_float_copnum = COP1;
85
86 /* If this is non-zero, then references to number(%pc) will be taken
87 to refer to number, rather than to %pc + number. */
88 static int m68k_abspcadd;
89
90 /* If this is non-zero, then the quick forms of the move, add, and sub
91 instructions are used when possible. */
92 static int m68k_quick = 1;
93
94 /* If this is non-zero, then if the size is not specified for a base
95 or outer displacement, the assembler assumes that the size should
96 be 32 bits. */
97 static int m68k_rel32 = 1;
98
99 /* This is non-zero if m68k_rel32 was set from the command line. */
100 static int m68k_rel32_from_cmdline;
101
102 /* The default width to use for an index register when using a base
103 displacement. */
104 static enum m68k_size m68k_index_width_default = SIZE_LONG;
105
106 /* We want to warn if any text labels are misaligned. In order to get
107 the right line number, we need to record the line number for each
108 label. */
109
110 struct label_line
111 {
112 struct label_line *next;
113 symbolS *label;
114 char *file;
115 unsigned int line;
116 int text;
117 };
118
119 /* The list of labels. */
120
121 static struct label_line *labels;
122
123 /* The current label. */
124
125 static struct label_line *current_label;
126
127 /* Its an arbitrary name: This means I don't approve of it */
128 /* See flames below */
129 static struct obstack robyn;
130
131 #define TAB(x,y) (((x)<<2)+(y))
132 #define TABTYPE(xy) ((xy) >> 2)
133 #define BYTE 0
134 #define SHORT 1
135 #define LONG 2
136 #define SZ_UNDEF 3
137 #undef BRANCH
138 /* Case `g' except when BCC68000 is applicable. */
139 #define ABRANCH 1
140 /* Coprocessor branches. */
141 #define FBRANCH 2
142 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
143 supported on all cpus. Widens to 32-bit absolute. */
144 #define PCREL 3
145 /* For inserting an extra jmp instruction with long offset on 68000,
146 for expanding conditional branches. (Not bsr or bra.) Since the
147 68000 doesn't support 32-bit displacements for conditional
148 branches, we fake it by reversing the condition and branching
149 around a jmp with an absolute long operand. */
150 #define BCC68000 4
151 /* For the DBcc "instructions". If the displacement requires 32 bits,
152 the branch-around-a-jump game is played here too. */
153 #define DBCC 5
154 /* Not currently used? */
155 #define PCLEA 6
156 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
157 in 16 or 8 bits. */
158 #define PCINDEX 7
159
160 struct m68k_incant
161 {
162 const char *m_operands;
163 unsigned long m_opcode;
164 short m_opnum;
165 short m_codenum;
166 int m_arch;
167 struct m68k_incant *m_next;
168 };
169
170 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
171 #define gettwo(x) (((x)->m_opcode)&0xffff)
172
173 static const enum m68k_register m68000_control_regs[] = { 0 };
174 static const enum m68k_register m68010_control_regs[] = {
175 SFC, DFC, USP, VBR,
176 0
177 };
178 static const enum m68k_register m68020_control_regs[] = {
179 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
180 0
181 };
182 static const enum m68k_register m68040_control_regs[] = {
183 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
184 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
185 0
186 };
187 static const enum m68k_register m68060_control_regs[] = {
188 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
189 USP, VBR, URP, SRP, PCR,
190 0
191 };
192 static const enum m68k_register mcf5200_control_regs[] = {
193 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
194 RAMBAR0, RAMBAR1, MBAR,
195 0
196 };
197 #define cpu32_control_regs m68010_control_regs
198
199 static const enum m68k_register *control_regs;
200
201 /* internal form of a 68020 instruction */
202 struct m68k_it
203 {
204 const char *error;
205 const char *args; /* list of opcode info */
206 int numargs;
207
208 int numo; /* Number of shorts in opcode */
209 short opcode[11];
210
211 struct m68k_op operands[6];
212
213 int nexp; /* number of exprs in use */
214 struct m68k_exp exprs[4];
215
216 int nfrag; /* Number of frags we have to produce */
217 struct
218 {
219 int fragoff; /* Where in the current opcode the frag ends */
220 symbolS *fadd;
221 offsetT foff;
222 int fragty;
223 }
224 fragb[4];
225
226 int nrel; /* Num of reloc strucs in use */
227 struct
228 {
229 int n;
230 expressionS exp;
231 char wid;
232 char pcrel;
233 /* In a pc relative address the difference between the address
234 of the offset and the address that the offset is relative
235 to. This depends on the addressing mode. Basically this
236 is the value to put in the offset field to address the
237 first byte of the offset, without regarding the special
238 significance of some values (in the branch instruction, for
239 example). */
240 int pcrel_fix;
241 #ifdef OBJ_ELF
242 /* Whether this expression needs special pic relocation, and if
243 so, which. */
244 enum pic_relocation pic_reloc;
245 #endif
246 }
247 reloc[5]; /* Five is enough??? */
248 };
249
250 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
251 #define float_of_arch(x) ((x) & mfloat)
252 #define mmu_of_arch(x) ((x) & mmmu)
253
254 /* Macros for determining if cpu supports a specific addressing mode */
255 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
256
257 static struct m68k_it the_ins; /* the instruction being assembled */
258
259 #define op(ex) ((ex)->exp.X_op)
260 #define adds(ex) ((ex)->exp.X_add_symbol)
261 #define subs(ex) ((ex)->exp.X_op_symbol)
262 #define offs(ex) ((ex)->exp.X_add_number)
263
264 /* Macros for adding things to the m68k_it struct */
265
266 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
267
268 /* Static functions. */
269
270 static void insop PARAMS ((int, struct m68k_incant *));
271 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
272 static void add_frag PARAMS ((symbolS *, offsetT, int));
273
274 /* Like addword, but goes BEFORE general operands */
275 static void
276 insop (w, opcode)
277 int w;
278 struct m68k_incant *opcode;
279 {
280 int z;
281 for(z=the_ins.numo;z>opcode->m_codenum;--z)
282 the_ins.opcode[z]=the_ins.opcode[z-1];
283 for(z=0;z<the_ins.nrel;z++)
284 the_ins.reloc[z].n+=2;
285 for (z = 0; z < the_ins.nfrag; z++)
286 the_ins.fragb[z].fragoff++;
287 the_ins.opcode[opcode->m_codenum]=w;
288 the_ins.numo++;
289 }
290
291 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
292 Blecch. */
293 static void
294 add_fix (width, exp, pc_rel, pc_fix)
295 int width;
296 struct m68k_exp *exp;
297 int pc_rel;
298 int pc_fix;
299 {
300 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
301 ? (the_ins.numo*2-1)
302 : (((width)=='b')
303 ? (the_ins.numo*2+1)
304 : (the_ins.numo*2)));
305 the_ins.reloc[the_ins.nrel].exp = exp->exp;
306 the_ins.reloc[the_ins.nrel].wid = width;
307 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
308 #ifdef OBJ_ELF
309 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
310 #endif
311 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
312 }
313
314 /* Cause an extra frag to be generated here, inserting up to 10 bytes
315 (that value is chosen in the frag_var call in md_assemble). TYPE
316 is the subtype of the frag to be generated; its primary type is
317 rs_machine_dependent.
318
319 The TYPE parameter is also used by md_convert_frag_1 and
320 md_estimate_size_before_relax. The appropriate type of fixup will
321 be emitted by md_convert_frag_1.
322
323 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
324 static void
325 add_frag (add, off, type)
326 symbolS *add;
327 offsetT off;
328 int type;
329 {
330 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
331 the_ins.fragb[the_ins.nfrag].fadd=add;
332 the_ins.fragb[the_ins.nfrag].foff=off;
333 the_ins.fragb[the_ins.nfrag++].fragty=type;
334 }
335
336 #define isvar(ex) \
337 (op (ex) != O_constant && op (ex) != O_big)
338
339 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
340 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
341 static void m68k_ip PARAMS ((char *));
342 static void insert_reg PARAMS ((const char *, int));
343 static void select_control_regs PARAMS ((void));
344 static void init_regtable PARAMS ((void));
345 static int reverse_16_bits PARAMS ((int in));
346 static int reverse_8_bits PARAMS ((int in));
347 static void install_gen_operand PARAMS ((int mode, int val));
348 static void install_operand PARAMS ((int mode, int val));
349 static void s_bss PARAMS ((int));
350 static void s_data1 PARAMS ((int));
351 static void s_data2 PARAMS ((int));
352 static void s_even PARAMS ((int));
353 static void s_proc PARAMS ((int));
354 static void mri_chip PARAMS ((void));
355 static void s_chip PARAMS ((int));
356 static void s_fopt PARAMS ((int));
357 static void s_opt PARAMS ((int));
358 static void s_reg PARAMS ((int));
359 static void s_restore PARAMS ((int));
360 static void s_save PARAMS ((int));
361 static void s_mri_if PARAMS ((int));
362 static void s_mri_else PARAMS ((int));
363 static void s_mri_endi PARAMS ((int));
364 static void s_mri_break PARAMS ((int));
365 static void s_mri_next PARAMS ((int));
366 static void s_mri_for PARAMS ((int));
367 static void s_mri_endf PARAMS ((int));
368 static void s_mri_repeat PARAMS ((int));
369 static void s_mri_until PARAMS ((int));
370 static void s_mri_while PARAMS ((int));
371 static void s_mri_endw PARAMS ((int));
372 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
373 static void md_convert_frag_1 PARAMS ((fragS *));
374
375 static int current_architecture;
376
377 struct m68k_cpu {
378 unsigned long arch;
379 const char *name;
380 int alias;
381 };
382
383 static const struct m68k_cpu archs[] = {
384 { m68000, "68000", 0 },
385 { m68010, "68010", 0 },
386 { m68020, "68020", 0 },
387 { m68030, "68030", 0 },
388 { m68040, "68040", 0 },
389 { m68060, "68060", 0 },
390 { cpu32, "cpu32", 0 },
391 { m68881, "68881", 0 },
392 { m68851, "68851", 0 },
393 { mcf5200, "5200", 0 },
394 /* Aliases (effectively, so far as gas is concerned) for the above
395 cpus. */
396 { m68020, "68k", 1 },
397 { m68000, "68302", 1 },
398 { m68000, "68008", 1 },
399 { m68000, "68ec000", 1 },
400 { m68000, "68hc000", 1 },
401 { m68000, "68hc001", 1 },
402 { m68020, "68ec020", 1 },
403 { m68030, "68ec030", 1 },
404 { m68040, "68ec040", 1 },
405 { m68060, "68ec060", 1 },
406 { cpu32, "68330", 1 },
407 { cpu32, "68331", 1 },
408 { cpu32, "68332", 1 },
409 { cpu32, "68333", 1 },
410 { cpu32, "68340", 1 },
411 { cpu32, "68360", 1 },
412 { m68881, "68882", 1 },
413 };
414
415 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
416
417 /* BCC68000 is for patching in an extra jmp instruction for long offsets
418 on the 68000. The 68000 doesn't support long branches with branchs */
419
420 /* This table desribes how you change sizes for the various types of variable
421 size expressions. This version only supports two kinds. */
422
423 /* Note that calls to frag_var need to specify the maximum expansion
424 needed; this is currently 10 bytes for DBCC. */
425
426 /* The fields are:
427 How far Forward this mode will reach:
428 How far Backward this mode will reach:
429 How many bytes this mode will add to the size of the frag
430 Which mode to go to if the offset won't fit in this one
431 */
432 relax_typeS md_relax_table[] =
433 {
434 {1, 1, 0, 0}, /* First entries aren't used */
435 {1, 1, 0, 0}, /* For no good reason except */
436 {1, 1, 0, 0}, /* that the VAX doesn't either */
437 {1, 1, 0, 0},
438
439 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
440 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
441 {0, 0, 4, 0},
442 {1, 1, 0, 0},
443
444 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
445 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
446 {0, 0, 4, 0},
447 {1, 1, 0, 0},
448
449 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
450 {(32767), (-32768), 2, TAB (PCREL, LONG)},
451 {0, 0, 4, 0},
452 {1, 1, 0, 0},
453
454 {(127), (-128), 0, TAB (BCC68000, SHORT)},
455 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
456 {0, 0, 6, 0}, /* jmp long space */
457 {1, 1, 0, 0},
458
459 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
460 {(32767), (-32768), 2, TAB (DBCC, LONG)},
461 {0, 0, 10, 0}, /* bra/jmp long space */
462 {1, 1, 0, 0},
463
464 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
465 {32767, -32768, 2, TAB (PCLEA, LONG)},
466 {0, 0, 6, 0},
467 {1, 1, 0, 0},
468
469 /* For, e.g., jmp pcrel indexed. */
470 {125, -130, 0, TAB (PCINDEX, SHORT)},
471 {32765, -32770, 2, TAB (PCINDEX, LONG)},
472 {0, 0, 4, 0},
473 {1, 1, 0, 0},
474 };
475
476 /* These are the machine dependent pseudo-ops. These are included so
477 the assembler can work on the output from the SUN C compiler, which
478 generates these.
479 */
480
481 /* This table describes all the machine specific pseudo-ops the assembler
482 has to support. The fields are:
483 pseudo-op name without dot
484 function to call to execute this pseudo-op
485 Integer arg to pass to the function
486 */
487 const pseudo_typeS md_pseudo_table[] =
488 {
489 {"data1", s_data1, 0},
490 {"data2", s_data2, 0},
491 {"bss", s_bss, 0},
492 {"even", s_even, 0},
493 {"skip", s_space, 0},
494 {"proc", s_proc, 0},
495 #if defined (TE_SUN3) || defined (OBJ_ELF)
496 {"align", s_align_bytes, 0},
497 #endif
498 #ifdef OBJ_ELF
499 {"swbeg", s_ignore, 0},
500 #endif
501 {"extend", float_cons, 'x'},
502 {"ldouble", float_cons, 'x'},
503
504 /* The following pseudo-ops are supported for MRI compatibility. */
505 {"chip", s_chip, 0},
506 {"comline", s_space, 1},
507 {"fopt", s_fopt, 0},
508 {"mask2", s_ignore, 0},
509 {"opt", s_opt, 0},
510 {"reg", s_reg, 0},
511 {"restore", s_restore, 0},
512 {"save", s_save, 0},
513
514 {"if", s_mri_if, 0},
515 {"if.b", s_mri_if, 'b'},
516 {"if.w", s_mri_if, 'w'},
517 {"if.l", s_mri_if, 'l'},
518 {"else", s_mri_else, 0},
519 {"else.s", s_mri_else, 's'},
520 {"else.l", s_mri_else, 'l'},
521 {"endi", s_mri_endi, 0},
522 {"break", s_mri_break, 0},
523 {"break.s", s_mri_break, 's'},
524 {"break.l", s_mri_break, 'l'},
525 {"next", s_mri_next, 0},
526 {"next.s", s_mri_next, 's'},
527 {"next.l", s_mri_next, 'l'},
528 {"for", s_mri_for, 0},
529 {"for.b", s_mri_for, 'b'},
530 {"for.w", s_mri_for, 'w'},
531 {"for.l", s_mri_for, 'l'},
532 {"endf", s_mri_endf, 0},
533 {"repeat", s_mri_repeat, 0},
534 {"until", s_mri_until, 0},
535 {"until.b", s_mri_until, 'b'},
536 {"until.w", s_mri_until, 'w'},
537 {"until.l", s_mri_until, 'l'},
538 {"while", s_mri_while, 0},
539 {"while.b", s_mri_while, 'b'},
540 {"while.w", s_mri_while, 'w'},
541 {"while.l", s_mri_while, 'l'},
542 {"endw", s_mri_endw, 0},
543
544 {0, 0, 0}
545 };
546
547
548 /* The mote pseudo ops are put into the opcode table, since they
549 don't start with a . they look like opcodes to gas.
550 */
551
552 #ifdef M68KCOFF
553 extern void obj_coff_section PARAMS ((int));
554 #endif
555
556 CONST pseudo_typeS mote_pseudo_table[] =
557 {
558
559 {"dcl", cons, 4},
560 {"dc", cons, 2},
561 {"dcw", cons, 2},
562 {"dcb", cons, 1},
563
564 {"dsl", s_space, 4},
565 {"ds", s_space, 2},
566 {"dsw", s_space, 2},
567 {"dsb", s_space, 1},
568
569 {"xdef", s_globl, 0},
570 #ifdef OBJ_ELF
571 {"align", s_align_bytes, 0},
572 #else
573 {"align", s_align_ptwo, 0},
574 #endif
575 #ifdef M68KCOFF
576 {"sect", obj_coff_section, 0},
577 {"section", obj_coff_section, 0},
578 #endif
579 {0, 0, 0}
580 };
581
582 #define issbyte(x) ((x)>=-128 && (x)<=127)
583 #define isubyte(x) ((x)>=0 && (x)<=255)
584 #define issword(x) ((x)>=-32768 && (x)<=32767)
585 #define isuword(x) ((x)>=0 && (x)<=65535)
586
587 #define isbyte(x) ((x)>= -255 && (x)<=255)
588 #define isword(x) ((x)>=-65536 && (x)<=65535)
589 #define islong(x) (1)
590
591 extern char *input_line_pointer;
592
593 static char mklower_table[256];
594 #define mklower(c) (mklower_table[(unsigned char)(c)])
595 static char notend_table[256];
596 static char alt_notend_table[256];
597 #define notend(s) \
598 (! (notend_table[(unsigned char) *s] \
599 || (*s == ':' \
600 && alt_notend_table[(unsigned char) s[1]])))
601
602 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
603
604 #ifdef NO_PCREL_RELOCS
605
606 int
607 make_pcrel_absolute(fixP, add_number)
608 fixS *fixP;
609 long *add_number;
610 {
611 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
612
613 /* rewrite the PC relative instructions to absolute address ones.
614 * these are rumoured to be faster, and the apollo linker refuses
615 * to deal with the PC relative relocations.
616 */
617 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
618 {
619 opcode[0] = 0x4e;
620 opcode[1] = 0xf9;
621 }
622 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
623 {
624 opcode[0] = 0x4e;
625 opcode[1] = 0xb9;
626 }
627 else
628 as_fatal ("Unknown PC relative instruction");
629 *add_number -= 4;
630 return 0;
631 }
632
633 #endif /* NO_PCREL_RELOCS */
634
635 short
636 tc_coff_fix2rtype (fixP)
637 fixS *fixP;
638 {
639 if (fixP->fx_tcbit && fixP->fx_size == 4)
640 return R_RELLONG_NEG;
641 #ifdef NO_PCREL_RELOCS
642 know (fixP->fx_pcrel == 0);
643 return (fixP->fx_size == 1 ? R_RELBYTE
644 : fixP->fx_size == 2 ? R_DIR16
645 : R_DIR32);
646 #else
647 return (fixP->fx_pcrel ?
648 (fixP->fx_size == 1 ? R_PCRBYTE :
649 fixP->fx_size == 2 ? R_PCRWORD :
650 R_PCRLONG) :
651 (fixP->fx_size == 1 ? R_RELBYTE :
652 fixP->fx_size == 2 ? R_RELWORD :
653 R_RELLONG));
654 #endif
655 }
656
657 #endif
658
659 #ifdef OBJ_ELF
660
661 /* Compute the relocation code for a fixup of SIZE bytes, using pc
662 relative relocation if PCREL is non-zero. PIC says whether a special
663 pic relocation was requested. */
664
665 static bfd_reloc_code_real_type get_reloc_code
666 PARAMS ((int, int, enum pic_relocation));
667
668 static bfd_reloc_code_real_type
669 get_reloc_code (size, pcrel, pic)
670 int size;
671 int pcrel;
672 enum pic_relocation pic;
673 {
674 switch (pic)
675 {
676 case pic_got_pcrel:
677 switch (size)
678 {
679 case 1:
680 return BFD_RELOC_8_GOT_PCREL;
681 case 2:
682 return BFD_RELOC_16_GOT_PCREL;
683 case 4:
684 return BFD_RELOC_32_GOT_PCREL;
685 }
686 break;
687
688 case pic_got_off:
689 switch (size)
690 {
691 case 1:
692 return BFD_RELOC_8_GOTOFF;
693 case 2:
694 return BFD_RELOC_16_GOTOFF;
695 case 4:
696 return BFD_RELOC_32_GOTOFF;
697 }
698 break;
699
700 case pic_plt_pcrel:
701 switch (size)
702 {
703 case 1:
704 return BFD_RELOC_8_PLT_PCREL;
705 case 2:
706 return BFD_RELOC_16_PLT_PCREL;
707 case 4:
708 return BFD_RELOC_32_PLT_PCREL;
709 }
710 break;
711
712 case pic_plt_off:
713 switch (size)
714 {
715 case 1:
716 return BFD_RELOC_8_PLTOFF;
717 case 2:
718 return BFD_RELOC_16_PLTOFF;
719 case 4:
720 return BFD_RELOC_32_PLTOFF;
721 }
722 break;
723
724 case pic_none:
725 if (pcrel)
726 {
727 switch (size)
728 {
729 case 1:
730 return BFD_RELOC_8_PCREL;
731 case 2:
732 return BFD_RELOC_16_PCREL;
733 case 4:
734 return BFD_RELOC_32_PCREL;
735 }
736 }
737 else
738 {
739 switch (size)
740 {
741 case 1:
742 return BFD_RELOC_8;
743 case 2:
744 return BFD_RELOC_16;
745 case 4:
746 return BFD_RELOC_32;
747 }
748 }
749 }
750
751 as_bad ("Can not do %d byte %s%srelocation", size,
752 pcrel ? "pc-relative " : "",
753 pic == pic_none ? "" : "pic ");
754 return BFD_RELOC_NONE;
755 }
756
757 /* Here we decide which fixups can be adjusted to make them relative
758 to the beginning of the section instead of the symbol. Basically
759 we need to make sure that the dynamic relocations are done
760 correctly, so in some cases we force the original symbol to be
761 used. */
762 int
763 tc_m68k_fix_adjustable (fixP)
764 fixS *fixP;
765 {
766 /* Prevent all adjustments to global symbols. */
767 if (S_IS_EXTERNAL (fixP->fx_addsy))
768 return 0;
769
770 /* adjust_reloc_syms doesn't know about the GOT */
771 switch (fixP->fx_r_type)
772 {
773 case BFD_RELOC_8_GOT_PCREL:
774 case BFD_RELOC_16_GOT_PCREL:
775 case BFD_RELOC_32_GOT_PCREL:
776 case BFD_RELOC_8_GOTOFF:
777 case BFD_RELOC_16_GOTOFF:
778 case BFD_RELOC_32_GOTOFF:
779 case BFD_RELOC_8_PLT_PCREL:
780 case BFD_RELOC_16_PLT_PCREL:
781 case BFD_RELOC_32_PLT_PCREL:
782 case BFD_RELOC_8_PLTOFF:
783 case BFD_RELOC_16_PLTOFF:
784 case BFD_RELOC_32_PLTOFF:
785 return 0;
786
787 default:
788 return 1;
789 }
790 }
791
792 #else /* !OBJ_ELF */
793
794 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
795
796 #endif /* OBJ_ELF */
797
798 #ifdef BFD_ASSEMBLER
799
800 arelent *
801 tc_gen_reloc (section, fixp)
802 asection *section;
803 fixS *fixp;
804 {
805 arelent *reloc;
806 bfd_reloc_code_real_type code;
807
808 if (fixp->fx_tcbit)
809 abort ();
810
811 if (fixp->fx_r_type != BFD_RELOC_NONE)
812 {
813 code = fixp->fx_r_type;
814
815 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
816 that fixup_segment converted a non-PC relative reloc into a
817 PC relative reloc. In such a case, we need to convert the
818 reloc code. */
819 if (fixp->fx_pcrel)
820 {
821 switch (code)
822 {
823 case BFD_RELOC_8:
824 code = BFD_RELOC_8_PCREL;
825 break;
826 case BFD_RELOC_16:
827 code = BFD_RELOC_16_PCREL;
828 break;
829 case BFD_RELOC_32:
830 code = BFD_RELOC_32_PCREL;
831 break;
832 case BFD_RELOC_8_PCREL:
833 case BFD_RELOC_16_PCREL:
834 case BFD_RELOC_32_PCREL:
835 case BFD_RELOC_8_GOT_PCREL:
836 case BFD_RELOC_16_GOT_PCREL:
837 case BFD_RELOC_32_GOT_PCREL:
838 case BFD_RELOC_8_GOTOFF:
839 case BFD_RELOC_16_GOTOFF:
840 case BFD_RELOC_32_GOTOFF:
841 case BFD_RELOC_8_PLT_PCREL:
842 case BFD_RELOC_16_PLT_PCREL:
843 case BFD_RELOC_32_PLT_PCREL:
844 case BFD_RELOC_8_PLTOFF:
845 case BFD_RELOC_16_PLTOFF:
846 case BFD_RELOC_32_PLTOFF:
847 break;
848 default:
849 as_bad_where (fixp->fx_file, fixp->fx_line,
850 "Cannot make %s relocation PC relative",
851 bfd_get_reloc_code_name (code));
852 }
853 }
854 }
855 else
856 {
857 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
858 switch (F (fixp->fx_size, fixp->fx_pcrel))
859 {
860 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
861 MAP (1, 0, BFD_RELOC_8);
862 MAP (2, 0, BFD_RELOC_16);
863 MAP (4, 0, BFD_RELOC_32);
864 MAP (1, 1, BFD_RELOC_8_PCREL);
865 MAP (2, 1, BFD_RELOC_16_PCREL);
866 MAP (4, 1, BFD_RELOC_32_PCREL);
867 default:
868 abort ();
869 }
870 }
871 #undef F
872 #undef MAP
873
874 reloc = (arelent *) xmalloc (sizeof (arelent));
875 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
876 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
877 #ifndef OBJ_ELF
878 if (fixp->fx_pcrel)
879 reloc->addend = fixp->fx_addnumber;
880 else
881 reloc->addend = 0;
882 #else
883 if (!fixp->fx_pcrel)
884 reloc->addend = fixp->fx_addnumber;
885 else
886 reloc->addend = (section->vma
887 + (fixp->fx_pcrel_adjust == 64
888 ? -1 : fixp->fx_pcrel_adjust)
889 + fixp->fx_addnumber
890 + md_pcrel_from (fixp));
891 #endif
892
893 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
894 assert (reloc->howto != 0);
895
896 return reloc;
897 }
898
899 #endif /* BFD_ASSEMBLER */
900
901 /* Handle of the OPCODE hash table. NULL means any use before
902 m68k_ip_begin() will crash. */
903 static struct hash_control *op_hash;
904 \f
905 /* Assemble an m68k instruction. */
906
907 void
908 m68k_ip (instring)
909 char *instring;
910 {
911 register char *p;
912 register struct m68k_op *opP;
913 register struct m68k_incant *opcode;
914 register const char *s;
915 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
916 char *pdot, *pdotmove;
917 enum m68k_size siz1, siz2;
918 char c;
919 int losing;
920 int opsfound;
921 LITTLENUM_TYPE words[6];
922 LITTLENUM_TYPE *wordp;
923 unsigned long ok_arch = 0;
924
925 if (*instring == ' ')
926 instring++; /* skip leading whitespace */
927
928 /* Scan up to end of operation-code, which MUST end in end-of-string
929 or exactly 1 space. */
930 pdot = 0;
931 for (p = instring; *p != '\0'; p++)
932 {
933 if (*p == ' ')
934 break;
935 if (*p == '.')
936 pdot = p;
937 }
938
939 if (p == instring)
940 {
941 the_ins.error = "No operator";
942 return;
943 }
944
945 /* p now points to the end of the opcode name, probably whitespace.
946 Make sure the name is null terminated by clobbering the
947 whitespace, look it up in the hash table, then fix it back.
948 Remove a dot, first, since the opcode tables have none. */
949 if (pdot != NULL)
950 {
951 for (pdotmove = pdot; pdotmove < p; pdotmove++)
952 *pdotmove = pdotmove[1];
953 p--;
954 }
955
956 c = *p;
957 *p = '\0';
958 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
959 *p = c;
960
961 if (pdot != NULL)
962 {
963 for (pdotmove = p; pdotmove > pdot; pdotmove--)
964 *pdotmove = pdotmove[-1];
965 *pdot = '.';
966 ++p;
967 }
968
969 if (opcode == NULL)
970 {
971 the_ins.error = "Unknown operator";
972 return;
973 }
974
975 /* found a legitimate opcode, start matching operands */
976 while (*p == ' ')
977 ++p;
978
979 if (opcode->m_operands == 0)
980 {
981 char *old = input_line_pointer;
982 *old = '\n';
983 input_line_pointer = p;
984 /* Ahh - it's a motorola style psuedo op */
985 mote_pseudo_table[opcode->m_opnum].poc_handler
986 (mote_pseudo_table[opcode->m_opnum].poc_val);
987 input_line_pointer = old;
988 *old = 0;
989
990 return;
991 }
992
993 if (flag_mri && opcode->m_opnum == 0)
994 {
995 /* In MRI mode, random garbage is allowed after an instruction
996 which accepts no operands. */
997 the_ins.args = opcode->m_operands;
998 the_ins.numargs = opcode->m_opnum;
999 the_ins.numo = opcode->m_codenum;
1000 the_ins.opcode[0] = getone (opcode);
1001 the_ins.opcode[1] = gettwo (opcode);
1002 return;
1003 }
1004
1005 for (opP = &the_ins.operands[0]; *p; opP++)
1006 {
1007 p = crack_operand (p, opP);
1008
1009 if (opP->error)
1010 {
1011 the_ins.error = opP->error;
1012 return;
1013 }
1014 }
1015
1016 opsfound = opP - &the_ins.operands[0];
1017
1018 /* This ugly hack is to support the floating pt opcodes in their
1019 standard form. Essentially, we fake a first enty of type COP#1 */
1020 if (opcode->m_operands[0] == 'I')
1021 {
1022 int n;
1023
1024 for (n = opsfound; n > 0; --n)
1025 the_ins.operands[n] = the_ins.operands[n - 1];
1026
1027 memset ((char *) (&the_ins.operands[0]), '\0',
1028 sizeof (the_ins.operands[0]));
1029 the_ins.operands[0].mode = CONTROL;
1030 the_ins.operands[0].reg = m68k_float_copnum;
1031 opsfound++;
1032 }
1033
1034 /* We've got the operands. Find an opcode that'll accept them */
1035 for (losing = 0;;)
1036 {
1037 /* If we didn't get the right number of ops, or we have no
1038 common model with this pattern then reject this pattern. */
1039
1040 ok_arch |= opcode->m_arch;
1041 if (opsfound != opcode->m_opnum
1042 || ((opcode->m_arch & current_architecture) == 0))
1043 ++losing;
1044 else
1045 {
1046 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1047 *s && !losing;
1048 s += 2, opP++)
1049 {
1050 /* Warning: this switch is huge! */
1051 /* I've tried to organize the cases into this order:
1052 non-alpha first, then alpha by letter. Lower-case
1053 goes directly before uppercase counterpart. */
1054 /* Code with multiple case ...: gets sorted by the lowest
1055 case ... it belongs to. I hope this makes sense. */
1056 switch (*s)
1057 {
1058 case '!':
1059 switch (opP->mode)
1060 {
1061 case IMMED:
1062 case DREG:
1063 case AREG:
1064 case FPREG:
1065 case CONTROL:
1066 case AINC:
1067 case ADEC:
1068 case REGLST:
1069 losing++;
1070 break;
1071 default:
1072 break;
1073 }
1074 break;
1075
1076 case '`':
1077 switch (opP->mode)
1078 {
1079 case IMMED:
1080 case DREG:
1081 case AREG:
1082 case FPREG:
1083 case CONTROL:
1084 case AINC:
1085 case REGLST:
1086 case AINDR:
1087 losing++;
1088 break;
1089 default:
1090 break;
1091 }
1092 break;
1093
1094 case '<':
1095 switch (opP->mode)
1096 {
1097 case DREG:
1098 case AREG:
1099 case FPREG:
1100 case CONTROL:
1101 case IMMED:
1102 case ADEC:
1103 case REGLST:
1104 losing++;
1105 break;
1106 default:
1107 break;
1108 }
1109 break;
1110
1111 case '>':
1112 switch (opP->mode)
1113 {
1114 case DREG:
1115 case AREG:
1116 case FPREG:
1117 case CONTROL:
1118 case IMMED:
1119 case AINC:
1120 case REGLST:
1121 losing++;
1122 break;
1123 case ABSL:
1124 break;
1125 default:
1126 if (opP->reg == PC
1127 || opP->reg == ZPC)
1128 losing++;
1129 break;
1130 }
1131 break;
1132
1133 case 'm':
1134 switch (opP->mode)
1135 {
1136 case DREG:
1137 case AREG:
1138 case AINDR:
1139 case AINC:
1140 case ADEC:
1141 break;
1142 default:
1143 losing++;
1144 }
1145 break;
1146
1147 case 'n':
1148 switch (opP->mode)
1149 {
1150 case DISP:
1151 break;
1152 default:
1153 losing++;
1154 }
1155 break;
1156
1157 case 'o':
1158 switch (opP->mode)
1159 {
1160 case BASE:
1161 case ABSL:
1162 case IMMED:
1163 break;
1164 default:
1165 losing++;
1166 }
1167 break;
1168
1169 case 'p':
1170 switch (opP->mode)
1171 {
1172 case DREG:
1173 case AREG:
1174 case AINDR:
1175 case AINC:
1176 case ADEC:
1177 break;
1178 case DISP:
1179 if (opP->reg == PC || opP->reg == ZPC)
1180 losing++;
1181 break;
1182 default:
1183 losing++;
1184 }
1185 break;
1186
1187 case 'q':
1188 switch (opP->mode)
1189 {
1190 case DREG:
1191 case AINDR:
1192 case AINC:
1193 case ADEC:
1194 break;
1195 case DISP:
1196 if (opP->reg == PC || opP->reg == ZPC)
1197 losing++;
1198 break;
1199 default:
1200 losing++;
1201 break;
1202 }
1203 break;
1204
1205 case 'v':
1206 switch (opP->mode)
1207 {
1208 case DREG:
1209 case AINDR:
1210 case AINC:
1211 case ADEC:
1212 case ABSL:
1213 break;
1214 case DISP:
1215 if (opP->reg == PC || opP->reg == ZPC)
1216 losing++;
1217 break;
1218 default:
1219 losing++;
1220 break;
1221 }
1222 break;
1223
1224 case '#':
1225 if (opP->mode != IMMED)
1226 losing++;
1227 else if (s[1] == 'b'
1228 && ! isvar (&opP->disp)
1229 && (opP->disp.exp.X_op != O_constant
1230 || ! isbyte (opP->disp.exp.X_add_number)))
1231 losing++;
1232 else if (s[1] == 'B'
1233 && ! isvar (&opP->disp)
1234 && (opP->disp.exp.X_op != O_constant
1235 || ! issbyte (opP->disp.exp.X_add_number)))
1236 losing++;
1237 else if (s[1] == 'w'
1238 && ! isvar (&opP->disp)
1239 && (opP->disp.exp.X_op != O_constant
1240 || ! isword (opP->disp.exp.X_add_number)))
1241 losing++;
1242 else if (s[1] == 'W'
1243 && ! isvar (&opP->disp)
1244 && (opP->disp.exp.X_op != O_constant
1245 || ! issword (opP->disp.exp.X_add_number)))
1246 losing++;
1247 break;
1248
1249 case '^':
1250 case 'T':
1251 if (opP->mode != IMMED)
1252 losing++;
1253 break;
1254
1255 case '$':
1256 if (opP->mode == AREG
1257 || opP->mode == CONTROL
1258 || opP->mode == FPREG
1259 || opP->mode == IMMED
1260 || opP->mode == REGLST
1261 || (opP->mode != ABSL
1262 && (opP->reg == PC
1263 || opP->reg == ZPC)))
1264 losing++;
1265 break;
1266
1267 case '%':
1268 if (opP->mode == CONTROL
1269 || opP->mode == FPREG
1270 || opP->mode == REGLST
1271 || opP->mode == IMMED
1272 || (opP->mode != ABSL
1273 && (opP->reg == PC
1274 || opP->reg == ZPC)))
1275 losing++;
1276 break;
1277
1278 case '&':
1279 switch (opP->mode)
1280 {
1281 case DREG:
1282 case AREG:
1283 case FPREG:
1284 case CONTROL:
1285 case IMMED:
1286 case AINC:
1287 case ADEC:
1288 case REGLST:
1289 losing++;
1290 break;
1291 case ABSL:
1292 break;
1293 default:
1294 if (opP->reg == PC
1295 || opP->reg == ZPC)
1296 losing++;
1297 break;
1298 }
1299 break;
1300
1301 case '*':
1302 if (opP->mode == CONTROL
1303 || opP->mode == FPREG
1304 || opP->mode == REGLST)
1305 losing++;
1306 break;
1307
1308 case '+':
1309 if (opP->mode != AINC)
1310 losing++;
1311 break;
1312
1313 case '-':
1314 if (opP->mode != ADEC)
1315 losing++;
1316 break;
1317
1318 case '/':
1319 switch (opP->mode)
1320 {
1321 case AREG:
1322 case CONTROL:
1323 case FPREG:
1324 case AINC:
1325 case ADEC:
1326 case IMMED:
1327 case REGLST:
1328 losing++;
1329 break;
1330 default:
1331 break;
1332 }
1333 break;
1334
1335 case ';':
1336 switch (opP->mode)
1337 {
1338 case AREG:
1339 case CONTROL:
1340 case FPREG:
1341 case REGLST:
1342 losing++;
1343 break;
1344 default:
1345 break;
1346 }
1347 break;
1348
1349 case '?':
1350 switch (opP->mode)
1351 {
1352 case AREG:
1353 case CONTROL:
1354 case FPREG:
1355 case AINC:
1356 case ADEC:
1357 case IMMED:
1358 case REGLST:
1359 losing++;
1360 break;
1361 case ABSL:
1362 break;
1363 default:
1364 if (opP->reg == PC || opP->reg == ZPC)
1365 losing++;
1366 break;
1367 }
1368 break;
1369
1370 case '@':
1371 switch (opP->mode)
1372 {
1373 case AREG:
1374 case CONTROL:
1375 case FPREG:
1376 case IMMED:
1377 case REGLST:
1378 losing++;
1379 break;
1380 default:
1381 break;
1382 }
1383 break;
1384
1385 case '~': /* For now! (JF FOO is this right?) */
1386 switch (opP->mode)
1387 {
1388 case DREG:
1389 case AREG:
1390 case CONTROL:
1391 case FPREG:
1392 case IMMED:
1393 case REGLST:
1394 losing++;
1395 break;
1396 case ABSL:
1397 break;
1398 default:
1399 if (opP->reg == PC
1400 || opP->reg == ZPC)
1401 losing++;
1402 break;
1403 }
1404 break;
1405
1406 case '3':
1407 if (opP->mode != CONTROL
1408 || (opP->reg != TT0 && opP->reg != TT1))
1409 losing++;
1410 break;
1411
1412 case 'A':
1413 if (opP->mode != AREG)
1414 losing++;
1415 break;
1416
1417 case 'a':
1418 if (opP->mode != AINDR)
1419 ++losing;
1420 break;
1421
1422 case 'B': /* FOO */
1423 if (opP->mode != ABSL
1424 || (flag_long_jumps
1425 && strncmp (instring, "jbsr", 4) == 0))
1426 losing++;
1427 break;
1428
1429 case 'C':
1430 if (opP->mode != CONTROL || opP->reg != CCR)
1431 losing++;
1432 break;
1433
1434 case 'd':
1435 if (opP->mode != DISP
1436 || opP->reg < ADDR0
1437 || opP->reg > ADDR7)
1438 losing++;
1439 break;
1440
1441 case 'D':
1442 if (opP->mode != DREG)
1443 losing++;
1444 break;
1445
1446 case 'F':
1447 if (opP->mode != FPREG)
1448 losing++;
1449 break;
1450
1451 case 'I':
1452 if (opP->mode != CONTROL
1453 || opP->reg < COP0
1454 || opP->reg > COP7)
1455 losing++;
1456 break;
1457
1458 case 'J':
1459 if (opP->mode != CONTROL
1460 || opP->reg < USP
1461 || opP->reg > last_movec_reg)
1462 losing++;
1463 else
1464 {
1465 const enum m68k_register *rp;
1466 for (rp = control_regs; *rp; rp++)
1467 if (*rp == opP->reg)
1468 break;
1469 if (*rp == 0)
1470 losing++;
1471 }
1472 break;
1473
1474 case 'k':
1475 if (opP->mode != IMMED)
1476 losing++;
1477 break;
1478
1479 case 'l':
1480 case 'L':
1481 if (opP->mode == DREG
1482 || opP->mode == AREG
1483 || opP->mode == FPREG)
1484 {
1485 if (s[1] == '8')
1486 losing++;
1487 else
1488 {
1489 switch (opP->mode)
1490 {
1491 case DREG:
1492 opP->mask = 1 << (opP->reg - DATA0);
1493 break;
1494 case AREG:
1495 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1496 break;
1497 case FPREG:
1498 opP->mask = 1 << (opP->reg - FP0 + 16);
1499 break;
1500 default:
1501 abort ();
1502 }
1503 opP->mode = REGLST;
1504 }
1505 }
1506 else if (opP->mode == CONTROL)
1507 {
1508 if (s[1] != '8')
1509 losing++;
1510 else
1511 {
1512 switch (opP->reg)
1513 {
1514 case FPI:
1515 opP->mask = 1 << 24;
1516 break;
1517 case FPS:
1518 opP->mask = 1 << 25;
1519 break;
1520 case FPC:
1521 opP->mask = 1 << 26;
1522 break;
1523 default:
1524 losing++;
1525 break;
1526 }
1527 opP->mode = REGLST;
1528 }
1529 }
1530 else if (opP->mode == ABSL
1531 && opP->disp.size == SIZE_UNSPEC
1532 && opP->disp.exp.X_op == O_constant)
1533 {
1534 /* This is what the MRI REG pseudo-op generates. */
1535 opP->mode = REGLST;
1536 opP->mask = opP->disp.exp.X_add_number;
1537 }
1538 else if (opP->mode != REGLST)
1539 losing++;
1540 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1541 losing++;
1542 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1543 losing++;
1544 break;
1545
1546 case 'M':
1547 if (opP->mode != IMMED)
1548 losing++;
1549 else if (opP->disp.exp.X_op != O_constant
1550 || ! issbyte (opP->disp.exp.X_add_number))
1551 losing++;
1552 else if (! m68k_quick
1553 && instring[3] != 'q'
1554 && instring[4] != 'q')
1555 losing++;
1556 break;
1557
1558 case 'O':
1559 if (opP->mode != DREG
1560 && opP->mode != IMMED
1561 && opP->mode != ABSL)
1562 losing++;
1563 break;
1564
1565 case 'Q':
1566 if (opP->mode != IMMED)
1567 losing++;
1568 else if (opP->disp.exp.X_op != O_constant
1569 || opP->disp.exp.X_add_number < 1
1570 || opP->disp.exp.X_add_number > 8)
1571 losing++;
1572 else if (! m68k_quick
1573 && (strncmp (instring, "add", 3) == 0
1574 || strncmp (instring, "sub", 3) == 0)
1575 && instring[3] != 'q')
1576 losing++;
1577 break;
1578
1579 case 'R':
1580 if (opP->mode != DREG && opP->mode != AREG)
1581 losing++;
1582 break;
1583
1584 case 'r':
1585 if (opP->mode != AINDR
1586 && (opP->mode != BASE
1587 || (opP->reg != 0
1588 && opP->reg != ZADDR0)
1589 || opP->disp.exp.X_op != O_absent
1590 || ((opP->index.reg < DATA0
1591 || opP->index.reg > DATA7)
1592 && (opP->index.reg < ADDR0
1593 || opP->index.reg > ADDR7))
1594 || opP->index.size != SIZE_UNSPEC
1595 || opP->index.scale != 1))
1596 losing++;
1597 break;
1598
1599 case 's':
1600 if (opP->mode != CONTROL
1601 || ! (opP->reg == FPI
1602 || opP->reg == FPS
1603 || opP->reg == FPC))
1604 losing++;
1605 break;
1606
1607 case 'S':
1608 if (opP->mode != CONTROL || opP->reg != SR)
1609 losing++;
1610 break;
1611
1612 case 't':
1613 if (opP->mode != IMMED)
1614 losing++;
1615 else if (opP->disp.exp.X_op != O_constant
1616 || opP->disp.exp.X_add_number < 0
1617 || opP->disp.exp.X_add_number > 7)
1618 losing++;
1619 break;
1620
1621 case 'U':
1622 if (opP->mode != CONTROL || opP->reg != USP)
1623 losing++;
1624 break;
1625
1626 /* JF these are out of order. We could put them
1627 in order if we were willing to put up with
1628 bunches of #ifdef m68851s in the code.
1629
1630 Don't forget that you need these operands
1631 to use 68030 MMU instructions. */
1632 #ifndef NO_68851
1633 /* Memory addressing mode used by pflushr */
1634 case '|':
1635 if (opP->mode == CONTROL
1636 || opP->mode == FPREG
1637 || opP->mode == DREG
1638 || opP->mode == AREG
1639 || opP->mode == REGLST)
1640 losing++;
1641 /* We should accept immediate operands, but they
1642 supposedly have to be quad word, and we don't
1643 handle that. I would like to see what a Motorola
1644 assembler does before doing something here. */
1645 if (opP->mode == IMMED)
1646 losing++;
1647 break;
1648
1649 case 'f':
1650 if (opP->mode != CONTROL
1651 || (opP->reg != SFC && opP->reg != DFC))
1652 losing++;
1653 break;
1654
1655 case '0':
1656 if (opP->mode != CONTROL || opP->reg != TC)
1657 losing++;
1658 break;
1659
1660 case '1':
1661 if (opP->mode != CONTROL || opP->reg != AC)
1662 losing++;
1663 break;
1664
1665 case '2':
1666 if (opP->mode != CONTROL
1667 || (opP->reg != CAL
1668 && opP->reg != VAL
1669 && opP->reg != SCC))
1670 losing++;
1671 break;
1672
1673 case 'V':
1674 if (opP->mode != CONTROL
1675 || opP->reg != VAL)
1676 losing++;
1677 break;
1678
1679 case 'W':
1680 if (opP->mode != CONTROL
1681 || (opP->reg != DRP
1682 && opP->reg != SRP
1683 && opP->reg != CRP))
1684 losing++;
1685 break;
1686
1687 case 'X':
1688 if (opP->mode != CONTROL
1689 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1690 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1691 losing++;
1692 break;
1693
1694 case 'Y':
1695 if (opP->mode != CONTROL || opP->reg != PSR)
1696 losing++;
1697 break;
1698
1699 case 'Z':
1700 if (opP->mode != CONTROL || opP->reg != PCSR)
1701 losing++;
1702 break;
1703 #endif
1704 case 'c':
1705 if (opP->mode != CONTROL
1706 || (opP->reg != NC
1707 && opP->reg != IC
1708 && opP->reg != DC
1709 && opP->reg != BC))
1710 {
1711 losing++;
1712 } /* not a cache specifier. */
1713 break;
1714
1715 case '_':
1716 if (opP->mode != ABSL)
1717 ++losing;
1718 break;
1719
1720 default:
1721 abort ();
1722 } /* switch on type of operand */
1723
1724 if (losing)
1725 break;
1726 } /* for each operand */
1727 } /* if immediately wrong */
1728
1729 if (!losing)
1730 {
1731 break;
1732 } /* got it. */
1733
1734 opcode = opcode->m_next;
1735
1736 if (!opcode)
1737 {
1738 if (ok_arch
1739 && !(ok_arch & current_architecture))
1740 {
1741 char buf[200], *cp;
1742
1743 strcpy (buf,
1744 "invalid instruction for this architecture; needs ");
1745 cp = buf + strlen (buf);
1746 switch (ok_arch)
1747 {
1748 case mfloat:
1749 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1750 break;
1751 case mmmu:
1752 strcpy (cp, "mmu (68030 or 68851)");
1753 break;
1754 case m68020up:
1755 strcpy (cp, "68020 or higher");
1756 break;
1757 case m68000up:
1758 strcpy (cp, "68000 or higher");
1759 break;
1760 case m68010up:
1761 strcpy (cp, "68010 or higher");
1762 break;
1763 default:
1764 {
1765 int got_one = 0, idx;
1766 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1767 idx++)
1768 {
1769 if ((archs[idx].arch & ok_arch)
1770 && ! archs[idx].alias)
1771 {
1772 if (got_one)
1773 {
1774 strcpy (cp, " or ");
1775 cp += strlen (cp);
1776 }
1777 got_one = 1;
1778 strcpy (cp, archs[idx].name);
1779 cp += strlen (cp);
1780 }
1781 }
1782 }
1783 }
1784 cp = xmalloc (strlen (buf) + 1);
1785 strcpy (cp, buf);
1786 the_ins.error = cp;
1787 }
1788 else
1789 the_ins.error = "operands mismatch";
1790 return;
1791 } /* Fell off the end */
1792
1793 losing = 0;
1794 }
1795
1796 /* now assemble it */
1797
1798 the_ins.args = opcode->m_operands;
1799 the_ins.numargs = opcode->m_opnum;
1800 the_ins.numo = opcode->m_codenum;
1801 the_ins.opcode[0] = getone (opcode);
1802 the_ins.opcode[1] = gettwo (opcode);
1803
1804 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1805 {
1806 /* This switch is a doozy.
1807 Watch the first step; its a big one! */
1808 switch (s[0])
1809 {
1810
1811 case '*':
1812 case '~':
1813 case '%':
1814 case ';':
1815 case '@':
1816 case '!':
1817 case '&':
1818 case '$':
1819 case '?':
1820 case '/':
1821 case '`':
1822 case '<':
1823 case '>':
1824 case 'm':
1825 case 'n':
1826 case 'o':
1827 case 'p':
1828 case 'q':
1829 case 'v':
1830 #ifndef NO_68851
1831 case '|':
1832 #endif
1833 switch (opP->mode)
1834 {
1835 case IMMED:
1836 tmpreg = 0x3c; /* 7.4 */
1837 if (strchr ("bwl", s[1]))
1838 nextword = get_num (&opP->disp, 80);
1839 else
1840 nextword = get_num (&opP->disp, 0);
1841 if (isvar (&opP->disp))
1842 add_fix (s[1], &opP->disp, 0, 0);
1843 switch (s[1])
1844 {
1845 case 'b':
1846 if (!isbyte (nextword))
1847 opP->error = "operand out of range";
1848 addword (nextword);
1849 baseo = 0;
1850 break;
1851 case 'w':
1852 if (!isword (nextword))
1853 opP->error = "operand out of range";
1854 addword (nextword);
1855 baseo = 0;
1856 break;
1857 case 'W':
1858 if (!issword (nextword))
1859 opP->error = "operand out of range";
1860 addword (nextword);
1861 baseo = 0;
1862 break;
1863 case 'l':
1864 addword (nextword >> 16);
1865 addword (nextword);
1866 baseo = 0;
1867 break;
1868
1869 case 'f':
1870 baseo = 2;
1871 outro = 8;
1872 break;
1873 case 'F':
1874 baseo = 4;
1875 outro = 11;
1876 break;
1877 case 'x':
1878 baseo = 6;
1879 outro = 15;
1880 break;
1881 case 'p':
1882 baseo = 6;
1883 outro = -1;
1884 break;
1885 default:
1886 abort ();
1887 }
1888 if (!baseo)
1889 break;
1890
1891 /* We gotta put out some float */
1892 if (op (&opP->disp) != O_big)
1893 {
1894 valueT val;
1895 int gencnt;
1896
1897 /* Can other cases happen here? */
1898 if (op (&opP->disp) != O_constant)
1899 abort ();
1900
1901 val = (valueT) offs (&opP->disp);
1902 gencnt = 0;
1903 do
1904 {
1905 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1906 val >>= LITTLENUM_NUMBER_OF_BITS;
1907 ++gencnt;
1908 }
1909 while (val != 0);
1910 offs (&opP->disp) = gencnt;
1911 }
1912 if (offs (&opP->disp) > 0)
1913 {
1914 if (offs (&opP->disp) > baseo)
1915 {
1916 as_warn ("Bignum too big for %c format; truncated",
1917 s[1]);
1918 offs (&opP->disp) = baseo;
1919 }
1920 baseo -= offs (&opP->disp);
1921 while (baseo--)
1922 addword (0);
1923 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1924 offs (&opP->disp)--;
1925 --wordp)
1926 addword (*wordp);
1927 break;
1928 }
1929 gen_to_words (words, baseo, (long) outro);
1930 for (wordp = words; baseo--; wordp++)
1931 addword (*wordp);
1932 break;
1933 case DREG:
1934 tmpreg = opP->reg - DATA; /* 0.dreg */
1935 break;
1936 case AREG:
1937 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1938 break;
1939 case AINDR:
1940 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1941 break;
1942 case ADEC:
1943 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1944 break;
1945 case AINC:
1946 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1947 break;
1948 case DISP:
1949
1950 nextword = get_num (&opP->disp, 80);
1951
1952 if (opP->reg == PC
1953 && ! isvar (&opP->disp)
1954 && m68k_abspcadd)
1955 {
1956 opP->disp.exp.X_op = O_symbol;
1957 #ifndef BFD_ASSEMBLER
1958 opP->disp.exp.X_add_symbol = &abs_symbol;
1959 #else
1960 opP->disp.exp.X_add_symbol =
1961 section_symbol (absolute_section);
1962 #endif
1963 }
1964
1965 /* Force into index mode. Hope this works */
1966
1967 /* We do the first bit for 32-bit displacements, and the
1968 second bit for 16 bit ones. It is possible that we
1969 should make the default be WORD instead of LONG, but
1970 I think that'd break GCC, so we put up with a little
1971 inefficiency for the sake of working output. */
1972
1973 if (!issword (nextword)
1974 || (isvar (&opP->disp)
1975 && ((opP->disp.size == SIZE_UNSPEC
1976 && flag_short_refs == 0
1977 && cpu_of_arch (current_architecture) >= m68020)
1978 || opP->disp.size == SIZE_LONG)))
1979 {
1980 if (cpu_of_arch (current_architecture) < m68020)
1981 opP->error =
1982 "displacement too large for this architecture; needs 68020 or higher";
1983 if (opP->reg == PC)
1984 tmpreg = 0x3B; /* 7.3 */
1985 else
1986 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1987 if (isvar (&opP->disp))
1988 {
1989 if (opP->reg == PC)
1990 {
1991 if (opP->disp.size == SIZE_LONG
1992 #ifdef OBJ_ELF
1993 /* If the displacement needs pic
1994 relocation it cannot be relaxed. */
1995 || opP->disp.pic_reloc != pic_none
1996 #endif
1997 )
1998 {
1999 addword (0x0170);
2000 add_fix ('l', &opP->disp, 1, 2);
2001 }
2002 else
2003 {
2004 add_frag (adds (&opP->disp),
2005 offs (&opP->disp),
2006 TAB (PCLEA, SZ_UNDEF));
2007 break;
2008 }
2009 }
2010 else
2011 {
2012 addword (0x0170);
2013 add_fix ('l', &opP->disp, 0, 0);
2014 }
2015 }
2016 else
2017 addword (0x0170);
2018 addword (nextword >> 16);
2019 }
2020 else
2021 {
2022 if (opP->reg == PC)
2023 tmpreg = 0x3A; /* 7.2 */
2024 else
2025 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2026
2027 if (isvar (&opP->disp))
2028 {
2029 if (opP->reg == PC)
2030 {
2031 add_fix ('w', &opP->disp, 1, 0);
2032 }
2033 else
2034 add_fix ('w', &opP->disp, 0, 0);
2035 }
2036 }
2037 addword (nextword);
2038 break;
2039
2040 case POST:
2041 case PRE:
2042 case BASE:
2043 nextword = 0;
2044 baseo = get_num (&opP->disp, 80);
2045 if (opP->mode == POST || opP->mode == PRE)
2046 outro = get_num (&opP->odisp, 80);
2047 /* Figure out the `addressing mode'.
2048 Also turn on the BASE_DISABLE bit, if needed. */
2049 if (opP->reg == PC || opP->reg == ZPC)
2050 {
2051 tmpreg = 0x3b; /* 7.3 */
2052 if (opP->reg == ZPC)
2053 nextword |= 0x80;
2054 }
2055 else if (opP->reg == 0)
2056 {
2057 nextword |= 0x80;
2058 tmpreg = 0x30; /* 6.garbage */
2059 }
2060 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2061 {
2062 nextword |= 0x80;
2063 tmpreg = 0x30 + opP->reg - ZADDR0;
2064 }
2065 else
2066 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2067
2068 siz1 = opP->disp.size;
2069 if (opP->mode == POST || opP->mode == PRE)
2070 siz2 = opP->odisp.size;
2071 else
2072 siz2 = SIZE_UNSPEC;
2073
2074 /* Index register stuff */
2075 if (opP->index.reg != 0
2076 && opP->index.reg >= DATA
2077 && opP->index.reg <= ADDR7)
2078 {
2079 nextword |= (opP->index.reg - DATA) << 12;
2080
2081 if (opP->index.size == SIZE_LONG
2082 || (opP->index.size == SIZE_UNSPEC
2083 && m68k_index_width_default == SIZE_LONG))
2084 nextword |= 0x800;
2085
2086 if ((opP->index.scale != 1
2087 && cpu_of_arch (current_architecture) < m68020)
2088 || (opP->index.scale == 8
2089 && current_architecture == mcf5200))
2090 {
2091 opP->error =
2092 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
2093 }
2094
2095 switch (opP->index.scale)
2096 {
2097 case 1:
2098 break;
2099 case 2:
2100 nextword |= 0x200;
2101 break;
2102 case 4:
2103 nextword |= 0x400;
2104 break;
2105 case 8:
2106 nextword |= 0x600;
2107 break;
2108 default:
2109 abort ();
2110 }
2111 /* IF its simple,
2112 GET US OUT OF HERE! */
2113
2114 /* Must be INDEX, with an index register. Address
2115 register cannot be ZERO-PC, and either :b was
2116 forced, or we know it will fit. For a 68000 or
2117 68010, force this mode anyways, because the
2118 larger modes aren't supported. */
2119 if (opP->mode == BASE
2120 && ((opP->reg >= ADDR0
2121 && opP->reg <= ADDR7)
2122 || opP->reg == PC))
2123 {
2124 if (siz1 == SIZE_BYTE
2125 || cpu_of_arch (current_architecture) < m68020
2126 || (siz1 == SIZE_UNSPEC
2127 && ! isvar (&opP->disp)
2128 && issbyte (baseo)))
2129 {
2130 nextword += baseo & 0xff;
2131 addword (nextword);
2132 if (isvar (&opP->disp))
2133 {
2134 /* Do a byte relocation. If it doesn't
2135 fit (possible on m68000) let the
2136 fixup processing complain later. */
2137 if (opP->reg == PC)
2138 add_fix ('B', &opP->disp, 1, 1);
2139 else
2140 add_fix ('B', &opP->disp, 0, 0);
2141 }
2142 else if (siz1 != SIZE_BYTE)
2143 {
2144 if (siz1 != SIZE_UNSPEC)
2145 as_warn ("Forcing byte displacement");
2146 if (! issbyte (baseo))
2147 opP->error = "byte displacement out of range";
2148 }
2149
2150 break;
2151 }
2152 else if (siz1 == SIZE_UNSPEC
2153 && opP->reg == PC
2154 && isvar (&opP->disp)
2155 && subs (&opP->disp) == NULL
2156 #ifdef OBJ_ELF
2157 /* If the displacement needs pic
2158 relocation it cannot be relaxed. */
2159 && opP->disp.pic_reloc == pic_none
2160 #endif
2161 )
2162 {
2163 /* The code in md_convert_frag_1 needs to be
2164 able to adjust nextword. Call frag_grow
2165 to ensure that we have enough space in
2166 the frag obstack to make all the bytes
2167 contiguous. */
2168 frag_grow (14);
2169 nextword += baseo & 0xff;
2170 addword (nextword);
2171 add_frag (adds (&opP->disp), offs (&opP->disp),
2172 TAB (PCINDEX, SZ_UNDEF));
2173
2174 break;
2175 }
2176 }
2177 }
2178 else
2179 {
2180 nextword |= 0x40; /* No index reg */
2181 if (opP->index.reg >= ZDATA0
2182 && opP->index.reg <= ZDATA7)
2183 nextword |= (opP->index.reg - ZDATA0) << 12;
2184 else if (opP->index.reg >= ZADDR0
2185 || opP->index.reg <= ZADDR7)
2186 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2187 }
2188
2189 /* It isn't simple. */
2190
2191 if (cpu_of_arch (current_architecture) < m68020)
2192 opP->error =
2193 "invalid operand mode for this architecture; needs 68020 or higher";
2194
2195 nextword |= 0x100;
2196 /* If the guy specified a width, we assume that it is
2197 wide enough. Maybe it isn't. If so, we lose. */
2198 switch (siz1)
2199 {
2200 case SIZE_UNSPEC:
2201 if (isvar (&opP->disp)
2202 ? m68k_rel32
2203 : ! issword (baseo))
2204 {
2205 siz1 = SIZE_LONG;
2206 nextword |= 0x30;
2207 }
2208 else if (! isvar (&opP->disp) && baseo == 0)
2209 nextword |= 0x10;
2210 else
2211 {
2212 nextword |= 0x20;
2213 siz1 = SIZE_WORD;
2214 }
2215 break;
2216 case SIZE_BYTE:
2217 as_warn (":b not permitted; defaulting to :w");
2218 /* Fall through. */
2219 case SIZE_WORD:
2220 nextword |= 0x20;
2221 break;
2222 case SIZE_LONG:
2223 nextword |= 0x30;
2224 break;
2225 }
2226
2227 /* Figure out innner displacement stuff */
2228 if (opP->mode == POST || opP->mode == PRE)
2229 {
2230 if (cpu_of_arch (current_architecture) & cpu32)
2231 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2232 switch (siz2)
2233 {
2234 case SIZE_UNSPEC:
2235 if (isvar (&opP->odisp)
2236 ? m68k_rel32
2237 : ! issword (outro))
2238 {
2239 siz2 = SIZE_LONG;
2240 nextword |= 0x3;
2241 }
2242 else if (! isvar (&opP->odisp) && outro == 0)
2243 nextword |= 0x1;
2244 else
2245 {
2246 nextword |= 0x2;
2247 siz2 = SIZE_WORD;
2248 }
2249 break;
2250 case 1:
2251 as_warn (":b not permitted; defaulting to :w");
2252 /* Fall through. */
2253 case 2:
2254 nextword |= 0x2;
2255 break;
2256 case 3:
2257 nextword |= 0x3;
2258 break;
2259 }
2260 if (opP->mode == POST
2261 && (nextword & 0x40) == 0)
2262 nextword |= 0x04;
2263 }
2264 addword (nextword);
2265
2266 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2267 {
2268 if (opP->reg == PC || opP->reg == ZPC)
2269 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2270 else
2271 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2272 }
2273 if (siz1 == SIZE_LONG)
2274 addword (baseo >> 16);
2275 if (siz1 != SIZE_UNSPEC)
2276 addword (baseo);
2277
2278 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2279 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2280 if (siz2 == SIZE_LONG)
2281 addword (outro >> 16);
2282 if (siz2 != SIZE_UNSPEC)
2283 addword (outro);
2284
2285 break;
2286
2287 case ABSL:
2288 nextword = get_num (&opP->disp, 80);
2289 switch (opP->disp.size)
2290 {
2291 default:
2292 abort ();
2293 case SIZE_UNSPEC:
2294 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2295 {
2296 tmpreg = 0x38; /* 7.0 */
2297 addword (nextword);
2298 break;
2299 }
2300 /* Don't generate pc relative code on 68010 and
2301 68000. */
2302 if (isvar (&opP->disp)
2303 && !subs (&opP->disp)
2304 && adds (&opP->disp)
2305 #ifdef OBJ_ELF
2306 /* If the displacement needs pic relocation it
2307 cannot be relaxed. */
2308 && opP->disp.pic_reloc == pic_none
2309 #endif
2310 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2311 && HAVE_LONG_BRANCH(current_architecture)
2312 && !flag_long_jumps
2313 && !strchr ("~%&$?", s[0]))
2314 {
2315 tmpreg = 0x3A; /* 7.2 */
2316 add_frag (adds (&opP->disp),
2317 offs (&opP->disp),
2318 TAB (PCREL, SZ_UNDEF));
2319 break;
2320 }
2321 /* Fall through into long */
2322 case SIZE_LONG:
2323 if (isvar (&opP->disp))
2324 add_fix ('l', &opP->disp, 0, 0);
2325
2326 tmpreg = 0x39;/* 7.1 mode */
2327 addword (nextword >> 16);
2328 addword (nextword);
2329 break;
2330
2331 case SIZE_BYTE:
2332 as_bad ("unsupported byte value; use a different suffix");
2333 /* Fall through. */
2334 case SIZE_WORD: /* Word */
2335 if (isvar (&opP->disp))
2336 add_fix ('w', &opP->disp, 0, 0);
2337
2338 tmpreg = 0x38;/* 7.0 mode */
2339 addword (nextword);
2340 break;
2341 }
2342 break;
2343 case CONTROL:
2344 case FPREG:
2345 default:
2346 as_bad ("unknown/incorrect operand");
2347 /* abort(); */
2348 }
2349 install_gen_operand (s[1], tmpreg);
2350 break;
2351
2352 case '#':
2353 case '^':
2354 switch (s[1])
2355 { /* JF: I hate floating point! */
2356 case 'j':
2357 tmpreg = 70;
2358 break;
2359 case '8':
2360 tmpreg = 20;
2361 break;
2362 case 'C':
2363 tmpreg = 50;
2364 break;
2365 case '3':
2366 default:
2367 tmpreg = 80;
2368 break;
2369 }
2370 tmpreg = get_num (&opP->disp, tmpreg);
2371 if (isvar (&opP->disp))
2372 add_fix (s[1], &opP->disp, 0, 0);
2373 switch (s[1])
2374 {
2375 case 'b': /* Danger: These do no check for
2376 certain types of overflow.
2377 user beware! */
2378 if (!isbyte (tmpreg))
2379 opP->error = "out of range";
2380 insop (tmpreg, opcode);
2381 if (isvar (&opP->disp))
2382 the_ins.reloc[the_ins.nrel - 1].n =
2383 (opcode->m_codenum) * 2 + 1;
2384 break;
2385 case 'B':
2386 if (!issbyte (tmpreg))
2387 opP->error = "out of range";
2388 opcode->m_opcode |= tmpreg;
2389 if (isvar (&opP->disp))
2390 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2391 break;
2392 case 'w':
2393 if (!isword (tmpreg))
2394 opP->error = "out of range";
2395 insop (tmpreg, opcode);
2396 if (isvar (&opP->disp))
2397 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2398 break;
2399 case 'W':
2400 if (!issword (tmpreg))
2401 opP->error = "out of range";
2402 insop (tmpreg, opcode);
2403 if (isvar (&opP->disp))
2404 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2405 break;
2406 case 'l':
2407 /* Because of the way insop works, we put these two out
2408 backwards. */
2409 insop (tmpreg, opcode);
2410 insop (tmpreg >> 16, opcode);
2411 if (isvar (&opP->disp))
2412 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2413 break;
2414 case '3':
2415 tmpreg &= 0xFF;
2416 case '8':
2417 case 'C':
2418 case 'j':
2419 install_operand (s[1], tmpreg);
2420 break;
2421 default:
2422 abort ();
2423 }
2424 break;
2425
2426 case '+':
2427 case '-':
2428 case 'A':
2429 case 'a':
2430 install_operand (s[1], opP->reg - ADDR);
2431 break;
2432
2433 case 'B':
2434 tmpreg = get_num (&opP->disp, 80);
2435 switch (s[1])
2436 {
2437 case 'B':
2438 /* The pc_fix argument winds up in fx_pcrel_adjust,
2439 which is a char, and may therefore be unsigned. We
2440 want to pass -1, but we pass 64 instead, and convert
2441 back in md_pcrel_from. */
2442 add_fix ('B', &opP->disp, 1, 64);
2443 break;
2444 case 'W':
2445 add_fix ('w', &opP->disp, 1, 0);
2446 addword (0);
2447 break;
2448 case 'L':
2449 long_branch:
2450 if (!HAVE_LONG_BRANCH(current_architecture))
2451 as_warn ("Can't use long branches on 68000/68010/5200");
2452 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2453 add_fix ('l', &opP->disp, 1, 0);
2454 addword (0);
2455 addword (0);
2456 break;
2457 case 'g':
2458 if (subs (&opP->disp)) /* We can't relax it */
2459 goto long_branch;
2460
2461 #ifdef OBJ_ELF
2462 /* If the displacement needs pic relocation it cannot be
2463 relaxed. */
2464 if (opP->disp.pic_reloc != pic_none)
2465 goto long_branch;
2466 #endif
2467
2468 /* This could either be a symbol, or an absolute
2469 address. No matter, the frag hacking will finger it
2470 out. Not quite: it can't switch from BRANCH to
2471 BCC68000 for the case where opnd is absolute (it
2472 needs to use the 68000 hack since no conditional abs
2473 jumps). */
2474 if (( !HAVE_LONG_BRANCH(current_architecture)
2475 || (0 == adds (&opP->disp)))
2476 && (the_ins.opcode[0] >= 0x6200)
2477 && (the_ins.opcode[0] <= 0x6f00))
2478 add_frag (adds (&opP->disp), offs (&opP->disp),
2479 TAB (BCC68000, SZ_UNDEF));
2480 else
2481 add_frag (adds (&opP->disp), offs (&opP->disp),
2482 TAB (ABRANCH, SZ_UNDEF));
2483 break;
2484 case 'w':
2485 if (isvar (&opP->disp))
2486 {
2487 #if 1
2488 /* check for DBcc instruction */
2489 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2490 {
2491 /* size varies if patch */
2492 /* needed for long form */
2493 add_frag (adds (&opP->disp), offs (&opP->disp),
2494 TAB (DBCC, SZ_UNDEF));
2495 break;
2496 }
2497 #endif
2498 add_fix ('w', &opP->disp, 1, 0);
2499 }
2500 addword (0);
2501 break;
2502 case 'C': /* Fixed size LONG coproc branches */
2503 add_fix ('l', &opP->disp, 1, 0);
2504 addword (0);
2505 addword (0);
2506 break;
2507 case 'c': /* Var size Coprocesssor branches */
2508 if (subs (&opP->disp))
2509 {
2510 add_fix ('l', &opP->disp, 1, 0);
2511 add_frag ((symbolS *) 0, (offsetT) 0, TAB (FBRANCH, LONG));
2512 }
2513 else if (adds (&opP->disp))
2514 add_frag (adds (&opP->disp), offs (&opP->disp),
2515 TAB (FBRANCH, SZ_UNDEF));
2516 else
2517 {
2518 /* add_frag ((symbolS *) 0, offs (&opP->disp),
2519 TAB(FBRANCH,SHORT)); */
2520 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2521 add_fix ('l', &opP->disp, 1, 0);
2522 addword (0);
2523 addword (0);
2524 }
2525 break;
2526 default:
2527 abort ();
2528 }
2529 break;
2530
2531 case 'C': /* Ignore it */
2532 break;
2533
2534 case 'd': /* JF this is a kludge */
2535 install_operand ('s', opP->reg - ADDR);
2536 tmpreg = get_num (&opP->disp, 80);
2537 if (!issword (tmpreg))
2538 {
2539 as_warn ("Expression out of range, using 0");
2540 tmpreg = 0;
2541 }
2542 addword (tmpreg);
2543 break;
2544
2545 case 'D':
2546 install_operand (s[1], opP->reg - DATA);
2547 break;
2548
2549 case 'F':
2550 install_operand (s[1], opP->reg - FP0);
2551 break;
2552
2553 case 'I':
2554 tmpreg = opP->reg - COP0;
2555 install_operand (s[1], tmpreg);
2556 break;
2557
2558 case 'J': /* JF foo */
2559 switch (opP->reg)
2560 {
2561 case SFC:
2562 tmpreg = 0x000;
2563 break;
2564 case DFC:
2565 tmpreg = 0x001;
2566 break;
2567 case CACR:
2568 tmpreg = 0x002;
2569 break;
2570 case TC:
2571 tmpreg = 0x003;
2572 break;
2573 case ITT0:
2574 tmpreg = 0x004;
2575 break;
2576 case ITT1:
2577 tmpreg = 0x005;
2578 break;
2579 case DTT0:
2580 tmpreg = 0x006;
2581 break;
2582 case DTT1:
2583 tmpreg = 0x007;
2584 break;
2585 case BUSCR:
2586 tmpreg = 0x008;
2587 break;
2588
2589 case USP:
2590 tmpreg = 0x800;
2591 break;
2592 case VBR:
2593 tmpreg = 0x801;
2594 break;
2595 case CAAR:
2596 tmpreg = 0x802;
2597 break;
2598 case MSP:
2599 tmpreg = 0x803;
2600 break;
2601 case ISP:
2602 tmpreg = 0x804;
2603 break;
2604 case MMUSR:
2605 tmpreg = 0x805;
2606 break;
2607 case URP:
2608 tmpreg = 0x806;
2609 break;
2610 case SRP:
2611 tmpreg = 0x807;
2612 break;
2613 case PCR:
2614 tmpreg = 0x808;
2615 break;
2616 case ROMBAR:
2617 tmpreg = 0xC00;
2618 break;
2619 case RAMBAR0:
2620 tmpreg = 0xC04;
2621 break;
2622 case RAMBAR1:
2623 tmpreg = 0xC05;
2624 break;
2625 case MBAR:
2626 tmpreg = 0xC0F;
2627 break;
2628 default:
2629 abort ();
2630 }
2631 install_operand (s[1], tmpreg);
2632 break;
2633
2634 case 'k':
2635 tmpreg = get_num (&opP->disp, 55);
2636 install_operand (s[1], tmpreg & 0x7f);
2637 break;
2638
2639 case 'l':
2640 tmpreg = opP->mask;
2641 if (s[1] == 'w')
2642 {
2643 if (tmpreg & 0x7FF0000)
2644 as_bad ("Floating point register in register list");
2645 insop (reverse_16_bits (tmpreg), opcode);
2646 }
2647 else
2648 {
2649 if (tmpreg & 0x700FFFF)
2650 as_bad ("Wrong register in floating-point reglist");
2651 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2652 }
2653 break;
2654
2655 case 'L':
2656 tmpreg = opP->mask;
2657 if (s[1] == 'w')
2658 {
2659 if (tmpreg & 0x7FF0000)
2660 as_bad ("Floating point register in register list");
2661 insop (tmpreg, opcode);
2662 }
2663 else if (s[1] == '8')
2664 {
2665 if (tmpreg & 0x0FFFFFF)
2666 as_bad ("incorrect register in reglist");
2667 install_operand (s[1], tmpreg >> 24);
2668 }
2669 else
2670 {
2671 if (tmpreg & 0x700FFFF)
2672 as_bad ("wrong register in floating-point reglist");
2673 else
2674 install_operand (s[1], tmpreg >> 16);
2675 }
2676 break;
2677
2678 case 'M':
2679 install_operand (s[1], get_num (&opP->disp, 60));
2680 break;
2681
2682 case 'O':
2683 tmpreg = ((opP->mode == DREG)
2684 ? 0x20 + opP->reg - DATA
2685 : (get_num (&opP->disp, 40) & 0x1F));
2686 install_operand (s[1], tmpreg);
2687 break;
2688
2689 case 'Q':
2690 tmpreg = get_num (&opP->disp, 10);
2691 if (tmpreg == 8)
2692 tmpreg = 0;
2693 install_operand (s[1], tmpreg);
2694 break;
2695
2696 case 'R':
2697 /* This depends on the fact that ADDR registers are eight
2698 more than their corresponding DATA regs, so the result
2699 will have the ADDR_REG bit set */
2700 install_operand (s[1], opP->reg - DATA);
2701 break;
2702
2703 case 'r':
2704 if (opP->mode == AINDR)
2705 install_operand (s[1], opP->reg - DATA);
2706 else
2707 install_operand (s[1], opP->index.reg - DATA);
2708 break;
2709
2710 case 's':
2711 if (opP->reg == FPI)
2712 tmpreg = 0x1;
2713 else if (opP->reg == FPS)
2714 tmpreg = 0x2;
2715 else if (opP->reg == FPC)
2716 tmpreg = 0x4;
2717 else
2718 abort ();
2719 install_operand (s[1], tmpreg);
2720 break;
2721
2722 case 'S': /* Ignore it */
2723 break;
2724
2725 case 'T':
2726 install_operand (s[1], get_num (&opP->disp, 30));
2727 break;
2728
2729 case 'U': /* Ignore it */
2730 break;
2731
2732 case 'c':
2733 switch (opP->reg)
2734 {
2735 case NC:
2736 tmpreg = 0;
2737 break;
2738 case DC:
2739 tmpreg = 1;
2740 break;
2741 case IC:
2742 tmpreg = 2;
2743 break;
2744 case BC:
2745 tmpreg = 3;
2746 break;
2747 default:
2748 as_fatal ("failed sanity check");
2749 } /* switch on cache token */
2750 install_operand (s[1], tmpreg);
2751 break;
2752 #ifndef NO_68851
2753 /* JF: These are out of order, I fear. */
2754 case 'f':
2755 switch (opP->reg)
2756 {
2757 case SFC:
2758 tmpreg = 0;
2759 break;
2760 case DFC:
2761 tmpreg = 1;
2762 break;
2763 default:
2764 abort ();
2765 }
2766 install_operand (s[1], tmpreg);
2767 break;
2768
2769 case '0':
2770 case '1':
2771 case '2':
2772 switch (opP->reg)
2773 {
2774 case TC:
2775 tmpreg = 0;
2776 break;
2777 case CAL:
2778 tmpreg = 4;
2779 break;
2780 case VAL:
2781 tmpreg = 5;
2782 break;
2783 case SCC:
2784 tmpreg = 6;
2785 break;
2786 case AC:
2787 tmpreg = 7;
2788 break;
2789 default:
2790 abort ();
2791 }
2792 install_operand (s[1], tmpreg);
2793 break;
2794
2795 case 'V':
2796 if (opP->reg == VAL)
2797 break;
2798 abort ();
2799
2800 case 'W':
2801 switch (opP->reg)
2802 {
2803 case DRP:
2804 tmpreg = 1;
2805 break;
2806 case SRP:
2807 tmpreg = 2;
2808 break;
2809 case CRP:
2810 tmpreg = 3;
2811 break;
2812 default:
2813 abort ();
2814 }
2815 install_operand (s[1], tmpreg);
2816 break;
2817
2818 case 'X':
2819 switch (opP->reg)
2820 {
2821 case BAD:
2822 case BAD + 1:
2823 case BAD + 2:
2824 case BAD + 3:
2825 case BAD + 4:
2826 case BAD + 5:
2827 case BAD + 6:
2828 case BAD + 7:
2829 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2830 break;
2831
2832 case BAC:
2833 case BAC + 1:
2834 case BAC + 2:
2835 case BAC + 3:
2836 case BAC + 4:
2837 case BAC + 5:
2838 case BAC + 6:
2839 case BAC + 7:
2840 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2841 break;
2842
2843 default:
2844 abort ();
2845 }
2846 install_operand (s[1], tmpreg);
2847 break;
2848 case 'Y':
2849 know (opP->reg == PSR);
2850 break;
2851 case 'Z':
2852 know (opP->reg == PCSR);
2853 break;
2854 #endif /* m68851 */
2855 case '3':
2856 switch (opP->reg)
2857 {
2858 case TT0:
2859 tmpreg = 2;
2860 break;
2861 case TT1:
2862 tmpreg = 3;
2863 break;
2864 default:
2865 abort ();
2866 }
2867 install_operand (s[1], tmpreg);
2868 break;
2869 case 't':
2870 tmpreg = get_num (&opP->disp, 20);
2871 install_operand (s[1], tmpreg);
2872 break;
2873 case '_': /* used only for move16 absolute 32-bit address */
2874 tmpreg = get_num (&opP->disp, 80);
2875 addword (tmpreg >> 16);
2876 addword (tmpreg & 0xFFFF);
2877 break;
2878 default:
2879 abort ();
2880 }
2881 }
2882
2883 /* By the time whe get here (FINALLY) the_ins contains the complete
2884 instruction, ready to be emitted. . . */
2885 }
2886
2887 static int
2888 reverse_16_bits (in)
2889 int in;
2890 {
2891 int out = 0;
2892 int n;
2893
2894 static int mask[16] =
2895 {
2896 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2897 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2898 };
2899 for (n = 0; n < 16; n++)
2900 {
2901 if (in & mask[n])
2902 out |= mask[15 - n];
2903 }
2904 return out;
2905 } /* reverse_16_bits() */
2906
2907 static int
2908 reverse_8_bits (in)
2909 int in;
2910 {
2911 int out = 0;
2912 int n;
2913
2914 static int mask[8] =
2915 {
2916 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2917 };
2918
2919 for (n = 0; n < 8; n++)
2920 {
2921 if (in & mask[n])
2922 out |= mask[7 - n];
2923 }
2924 return out;
2925 } /* reverse_8_bits() */
2926
2927 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2928 (that value is chosen in the frag_var call in md_assemble). TYPE
2929 is the subtype of the frag to be generated; its primary type is
2930 rs_machine_dependent.
2931
2932 The TYPE parameter is also used by md_convert_frag_1 and
2933 md_estimate_size_before_relax. The appropriate type of fixup will
2934 be emitted by md_convert_frag_1.
2935
2936 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2937 static void
2938 install_operand (mode, val)
2939 int mode;
2940 int val;
2941 {
2942 switch (mode)
2943 {
2944 case 's':
2945 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2946 break;
2947 case 'd':
2948 the_ins.opcode[0] |= val << 9;
2949 break;
2950 case '1':
2951 the_ins.opcode[1] |= val << 12;
2952 break;
2953 case '2':
2954 the_ins.opcode[1] |= val << 6;
2955 break;
2956 case '3':
2957 the_ins.opcode[1] |= val;
2958 break;
2959 case '4':
2960 the_ins.opcode[2] |= val << 12;
2961 break;
2962 case '5':
2963 the_ins.opcode[2] |= val << 6;
2964 break;
2965 case '6':
2966 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2967 three words long! */
2968 the_ins.numo++;
2969 the_ins.opcode[2] |= val;
2970 break;
2971 case '7':
2972 the_ins.opcode[1] |= val << 7;
2973 break;
2974 case '8':
2975 the_ins.opcode[1] |= val << 10;
2976 break;
2977 #ifndef NO_68851
2978 case '9':
2979 the_ins.opcode[1] |= val << 5;
2980 break;
2981 #endif
2982
2983 case 't':
2984 the_ins.opcode[1] |= (val << 10) | (val << 7);
2985 break;
2986 case 'D':
2987 the_ins.opcode[1] |= (val << 12) | val;
2988 break;
2989 case 'g':
2990 the_ins.opcode[0] |= val = 0xff;
2991 break;
2992 case 'i':
2993 the_ins.opcode[0] |= val << 9;
2994 break;
2995 case 'C':
2996 the_ins.opcode[1] |= val;
2997 break;
2998 case 'j':
2999 the_ins.opcode[1] |= val;
3000 the_ins.numo++; /* What a hack */
3001 break;
3002 case 'k':
3003 the_ins.opcode[1] |= val << 4;
3004 break;
3005 case 'b':
3006 case 'w':
3007 case 'W':
3008 case 'l':
3009 break;
3010 case 'e':
3011 the_ins.opcode[0] |= (val << 6);
3012 break;
3013 case 'L':
3014 the_ins.opcode[1] = (val >> 16);
3015 the_ins.opcode[2] = val & 0xffff;
3016 break;
3017 case 'c':
3018 default:
3019 as_fatal ("failed sanity check.");
3020 }
3021 } /* install_operand() */
3022
3023 static void
3024 install_gen_operand (mode, val)
3025 int mode;
3026 int val;
3027 {
3028 switch (mode)
3029 {
3030 case 's':
3031 the_ins.opcode[0] |= val;
3032 break;
3033 case 'd':
3034 /* This is a kludge!!! */
3035 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3036 break;
3037 case 'b':
3038 case 'w':
3039 case 'l':
3040 case 'f':
3041 case 'F':
3042 case 'x':
3043 case 'p':
3044 the_ins.opcode[0] |= val;
3045 break;
3046 /* more stuff goes here */
3047 default:
3048 as_fatal ("failed sanity check.");
3049 }
3050 } /* install_gen_operand() */
3051
3052 /*
3053 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3054 * then deal with the bitfield hack.
3055 */
3056
3057 static char *
3058 crack_operand (str, opP)
3059 register char *str;
3060 register struct m68k_op *opP;
3061 {
3062 register int parens;
3063 register int c;
3064 register char *beg_str;
3065 int inquote = 0;
3066
3067 if (!str)
3068 {
3069 return str;
3070 }
3071 beg_str = str;
3072 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3073 {
3074 if (! inquote)
3075 {
3076 if (*str == '(')
3077 parens++;
3078 else if (*str == ')')
3079 {
3080 if (!parens)
3081 { /* ERROR */
3082 opP->error = "Extra )";
3083 return str;
3084 }
3085 --parens;
3086 }
3087 }
3088 if (flag_mri && *str == '\'')
3089 inquote = ! inquote;
3090 }
3091 if (!*str && parens)
3092 { /* ERROR */
3093 opP->error = "Missing )";
3094 return str;
3095 }
3096 c = *str;
3097 *str = '\0';
3098 if (m68k_ip_op (beg_str, opP) != 0)
3099 {
3100 *str = c;
3101 return str;
3102 }
3103 *str = c;
3104 if (c == '}')
3105 c = *++str; /* JF bitfield hack */
3106 if (c)
3107 {
3108 c = *++str;
3109 if (!c)
3110 as_bad ("Missing operand");
3111 }
3112 return str;
3113 }
3114
3115 /* This is the guts of the machine-dependent assembler. STR points to a
3116 machine dependent instruction. This function is supposed to emit
3117 the frags/bytes it assembles to.
3118 */
3119
3120 void
3121 insert_reg (regname, regnum)
3122 const char *regname;
3123 int regnum;
3124 {
3125 char buf[100];
3126 int i;
3127
3128 #ifdef REGISTER_PREFIX
3129 if (!flag_reg_prefix_optional)
3130 {
3131 buf[0] = REGISTER_PREFIX;
3132 strcpy (buf + 1, regname);
3133 regname = buf;
3134 }
3135 #endif
3136
3137 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3138 &zero_address_frag));
3139
3140 for (i = 0; regname[i]; i++)
3141 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3142 buf[i] = '\0';
3143
3144 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3145 &zero_address_frag));
3146 }
3147
3148 struct init_entry
3149 {
3150 const char *name;
3151 int number;
3152 };
3153
3154 static const struct init_entry init_table[] =
3155 {
3156 { "d0", DATA0 },
3157 { "d1", DATA1 },
3158 { "d2", DATA2 },
3159 { "d3", DATA3 },
3160 { "d4", DATA4 },
3161 { "d5", DATA5 },
3162 { "d6", DATA6 },
3163 { "d7", DATA7 },
3164 { "a0", ADDR0 },
3165 { "a1", ADDR1 },
3166 { "a2", ADDR2 },
3167 { "a3", ADDR3 },
3168 { "a4", ADDR4 },
3169 { "a5", ADDR5 },
3170 { "a6", ADDR6 },
3171 { "fp", ADDR6 },
3172 { "a7", ADDR7 },
3173 { "sp", ADDR7 },
3174 { "ssp", ADDR7 },
3175 { "fp0", FP0 },
3176 { "fp1", FP1 },
3177 { "fp2", FP2 },
3178 { "fp3", FP3 },
3179 { "fp4", FP4 },
3180 { "fp5", FP5 },
3181 { "fp6", FP6 },
3182 { "fp7", FP7 },
3183 { "fpi", FPI },
3184 { "fpiar", FPI },
3185 { "fpc", FPI },
3186 { "fps", FPS },
3187 { "fpsr", FPS },
3188 { "fpc", FPC },
3189 { "fpcr", FPC },
3190 { "control", FPC },
3191 { "status", FPS },
3192 { "iaddr", FPI },
3193
3194 { "cop0", COP0 },
3195 { "cop1", COP1 },
3196 { "cop2", COP2 },
3197 { "cop3", COP3 },
3198 { "cop4", COP4 },
3199 { "cop5", COP5 },
3200 { "cop6", COP6 },
3201 { "cop7", COP7 },
3202 { "pc", PC },
3203 { "zpc", ZPC },
3204 { "sr", SR },
3205
3206 { "ccr", CCR },
3207 { "cc", CCR },
3208
3209 /* control registers */
3210 { "sfc", SFC }, /* Source Function Code */
3211 { "sfcr", SFC },
3212 { "dfc", DFC }, /* Destination Function Code */
3213 { "dfcr", DFC },
3214 { "cacr", CACR }, /* Cache Control Register */
3215 { "caar", CAAR }, /* Cache Address Register */
3216
3217 { "usp", USP }, /* User Stack Pointer */
3218 { "vbr", VBR }, /* Vector Base Register */
3219 { "msp", MSP }, /* Master Stack Pointer */
3220 { "isp", ISP }, /* Interrupt Stack Pointer */
3221
3222 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3223 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3224 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3225 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3226
3227 /* 68ec040 versions of same */
3228 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3229 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3230 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3231 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3232
3233 /* mcf5200 versions of same. The ColdFire programmer's reference
3234 manual indicated that the order is 2,3,0,1, but Ken Rose
3235 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3236 { "acr0", ITT0 }, /* Access Control Unit 0 */
3237 { "acr1", ITT1 }, /* Access Control Unit 1 */
3238 { "acr2", DTT0 }, /* Access Control Unit 2 */
3239 { "acr3", DTT1 }, /* Access Control Unit 3 */
3240
3241 { "tc", TC }, /* MMU Translation Control Register */
3242 { "tcr", TC },
3243
3244 { "mmusr", MMUSR }, /* MMU Status Register */
3245 { "srp", SRP }, /* User Root Pointer */
3246 { "urp", URP }, /* Supervisor Root Pointer */
3247
3248 { "buscr", BUSCR },
3249 { "pcr", PCR },
3250
3251 { "rombar", ROMBAR }, /* ROM Base Address Register */
3252 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3253 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3254 { "mbar", MBAR }, /* Module Base Address Register */
3255 /* end of control registers */
3256
3257 { "ac", AC },
3258 { "bc", BC },
3259 { "cal", CAL },
3260 { "crp", CRP },
3261 { "drp", DRP },
3262 { "pcsr", PCSR },
3263 { "psr", PSR },
3264 { "scc", SCC },
3265 { "val", VAL },
3266 { "bad0", BAD0 },
3267 { "bad1", BAD1 },
3268 { "bad2", BAD2 },
3269 { "bad3", BAD3 },
3270 { "bad4", BAD4 },
3271 { "bad5", BAD5 },
3272 { "bad6", BAD6 },
3273 { "bad7", BAD7 },
3274 { "bac0", BAC0 },
3275 { "bac1", BAC1 },
3276 { "bac2", BAC2 },
3277 { "bac3", BAC3 },
3278 { "bac4", BAC4 },
3279 { "bac5", BAC5 },
3280 { "bac6", BAC6 },
3281 { "bac7", BAC7 },
3282
3283 { "ic", IC },
3284 { "dc", DC },
3285 { "nc", NC },
3286
3287 { "tt0", TT0 },
3288 { "tt1", TT1 },
3289 /* 68ec030 versions of same */
3290 { "ac0", TT0 },
3291 { "ac1", TT1 },
3292 /* 68ec030 access control unit, identical to 030 MMU status reg */
3293 { "acusr", PSR },
3294
3295 /* Suppressed data and address registers. */
3296 { "zd0", ZDATA0 },
3297 { "zd1", ZDATA1 },
3298 { "zd2", ZDATA2 },
3299 { "zd3", ZDATA3 },
3300 { "zd4", ZDATA4 },
3301 { "zd5", ZDATA5 },
3302 { "zd6", ZDATA6 },
3303 { "zd7", ZDATA7 },
3304 { "za0", ZADDR0 },
3305 { "za1", ZADDR1 },
3306 { "za2", ZADDR2 },
3307 { "za3", ZADDR3 },
3308 { "za4", ZADDR4 },
3309 { "za5", ZADDR5 },
3310 { "za6", ZADDR6 },
3311 { "za7", ZADDR7 },
3312
3313 { 0, 0 }
3314 };
3315
3316 void
3317 init_regtable ()
3318 {
3319 int i;
3320 for (i = 0; init_table[i].name; i++)
3321 insert_reg (init_table[i].name, init_table[i].number);
3322 }
3323
3324 static int no_68851, no_68881;
3325
3326 #ifdef OBJ_AOUT
3327 /* a.out machine type. Default to 68020. */
3328 int m68k_aout_machtype = 2;
3329 #endif
3330
3331 void
3332 md_assemble (str)
3333 char *str;
3334 {
3335 const char *er;
3336 short *fromP;
3337 char *toP = NULL;
3338 int m, n = 0;
3339 char *to_beg_P;
3340 int shorts_this_frag;
3341 fixS *fixP;
3342
3343 /* In MRI mode, the instruction and operands are separated by a
3344 space. Anything following the operands is a comment. The label
3345 has already been removed. */
3346 if (flag_mri)
3347 {
3348 char *s;
3349 int fields = 0;
3350 int infield = 0;
3351 int inquote = 0;
3352
3353 for (s = str; *s != '\0'; s++)
3354 {
3355 if ((*s == ' ' || *s == '\t') && ! inquote)
3356 {
3357 if (infield)
3358 {
3359 ++fields;
3360 if (fields >= 2)
3361 {
3362 *s = '\0';
3363 break;
3364 }
3365 infield = 0;
3366 }
3367 }
3368 else
3369 {
3370 if (! infield)
3371 infield = 1;
3372 if (*s == '\'')
3373 inquote = ! inquote;
3374 }
3375 }
3376 }
3377
3378 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3379 m68k_ip (str);
3380 er = the_ins.error;
3381 if (!er)
3382 {
3383 for (n = 0; n < the_ins.numargs; n++)
3384 if (the_ins.operands[n].error)
3385 {
3386 er = the_ins.operands[n].error;
3387 break;
3388 }
3389 }
3390 if (er)
3391 {
3392 as_bad ("%s -- statement `%s' ignored", er, str);
3393 return;
3394 }
3395
3396 /* If there is a current label, record that it marks an instruction. */
3397 if (current_label != NULL)
3398 {
3399 current_label->text = 1;
3400 current_label = NULL;
3401 }
3402
3403 if (the_ins.nfrag == 0)
3404 {
3405 /* No frag hacking involved; just put it out */
3406 toP = frag_more (2 * the_ins.numo);
3407 fromP = &the_ins.opcode[0];
3408 for (m = the_ins.numo; m; --m)
3409 {
3410 md_number_to_chars (toP, (long) (*fromP), 2);
3411 toP += 2;
3412 fromP++;
3413 }
3414 /* put out symbol-dependent info */
3415 for (m = 0; m < the_ins.nrel; m++)
3416 {
3417 switch (the_ins.reloc[m].wid)
3418 {
3419 case 'B':
3420 n = 1;
3421 break;
3422 case 'b':
3423 n = 1;
3424 break;
3425 case '3':
3426 n = 1;
3427 break;
3428 case 'w':
3429 case 'W':
3430 n = 2;
3431 break;
3432 case 'l':
3433 n = 4;
3434 break;
3435 default:
3436 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3437 the_ins.reloc[m].wid);
3438 }
3439
3440 fixP = fix_new_exp (frag_now,
3441 ((toP - frag_now->fr_literal)
3442 - the_ins.numo * 2 + the_ins.reloc[m].n),
3443 n,
3444 &the_ins.reloc[m].exp,
3445 the_ins.reloc[m].pcrel,
3446 get_reloc_code (n, the_ins.reloc[m].pcrel,
3447 the_ins.reloc[m].pic_reloc));
3448 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3449 if (the_ins.reloc[m].wid == 'B')
3450 fixP->fx_signed = 1;
3451 }
3452 return;
3453 }
3454
3455 /* There's some frag hacking */
3456 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3457 {
3458 int wid;
3459
3460 if (n == 0)
3461 wid = 2 * the_ins.fragb[n].fragoff;
3462 else
3463 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3464 toP = frag_more (wid);
3465 to_beg_P = toP;
3466 shorts_this_frag = 0;
3467 for (m = wid / 2; m; --m)
3468 {
3469 md_number_to_chars (toP, (long) (*fromP), 2);
3470 toP += 2;
3471 fromP++;
3472 shorts_this_frag++;
3473 }
3474 for (m = 0; m < the_ins.nrel; m++)
3475 {
3476 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3477 {
3478 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3479 break;
3480 }
3481 wid = the_ins.reloc[m].wid;
3482 if (wid == 0)
3483 continue;
3484 the_ins.reloc[m].wid = 0;
3485 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3486
3487 fixP = fix_new_exp (frag_now,
3488 ((toP - frag_now->fr_literal)
3489 - the_ins.numo * 2 + the_ins.reloc[m].n),
3490 wid,
3491 &the_ins.reloc[m].exp,
3492 the_ins.reloc[m].pcrel,
3493 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3494 the_ins.reloc[m].pic_reloc));
3495 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3496 }
3497 (void) frag_var (rs_machine_dependent, 10, 0,
3498 (relax_substateT) (the_ins.fragb[n].fragty),
3499 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3500 }
3501 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3502 shorts_this_frag = 0;
3503 if (n)
3504 {
3505 toP = frag_more (n * sizeof (short));
3506 while (n--)
3507 {
3508 md_number_to_chars (toP, (long) (*fromP), 2);
3509 toP += 2;
3510 fromP++;
3511 shorts_this_frag++;
3512 }
3513 }
3514 for (m = 0; m < the_ins.nrel; m++)
3515 {
3516 int wid;
3517
3518 wid = the_ins.reloc[m].wid;
3519 if (wid == 0)
3520 continue;
3521 the_ins.reloc[m].wid = 0;
3522 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3523
3524 fixP = fix_new_exp (frag_now,
3525 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3526 - shorts_this_frag * 2),
3527 wid,
3528 &the_ins.reloc[m].exp,
3529 the_ins.reloc[m].pcrel,
3530 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3531 the_ins.reloc[m].pic_reloc));
3532 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3533 }
3534 }
3535
3536 void
3537 md_begin ()
3538 {
3539 /*
3540 * md_begin -- set up hash tables with 68000 instructions.
3541 * similar to what the vax assembler does. ---phr
3542 */
3543 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3544 a copy of it at runtime, adding in the information we want but isn't
3545 there. I think it'd be better to have an awk script hack the table
3546 at compile time. Or even just xstr the table and use it as-is. But
3547 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3548 names. */
3549
3550 register const struct m68k_opcode *ins;
3551 register struct m68k_incant *hack, *slak;
3552 register const char *retval = 0; /* empty string, or error msg text */
3553 register unsigned int i;
3554 register char c;
3555
3556 if (flag_mri)
3557 {
3558 flag_reg_prefix_optional = 1;
3559 m68k_abspcadd = 1;
3560 if (! m68k_rel32_from_cmdline)
3561 m68k_rel32 = 0;
3562 }
3563
3564 op_hash = hash_new ();
3565
3566 obstack_begin (&robyn, 4000);
3567 for (i = 0; i < m68k_numopcodes; i++)
3568 {
3569 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3570 do
3571 {
3572 ins = &m68k_opcodes[i];
3573 /* We *could* ignore insns that don't match our arch here
3574 but just leaving them out of the hash. */
3575 slak->m_operands = ins->args;
3576 slak->m_opnum = strlen (slak->m_operands) / 2;
3577 slak->m_arch = ins->arch;
3578 slak->m_opcode = ins->opcode;
3579 /* This is kludgey */
3580 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3581 if (i + 1 != m68k_numopcodes
3582 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3583 {
3584 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3585 i++;
3586 }
3587 else
3588 slak->m_next = 0;
3589 slak = slak->m_next;
3590 }
3591 while (slak);
3592
3593 retval = hash_insert (op_hash, ins->name, (char *) hack);
3594 if (retval)
3595 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3596 }
3597
3598 for (i = 0; i < m68k_numaliases; i++)
3599 {
3600 const char *name = m68k_opcode_aliases[i].primary;
3601 const char *alias = m68k_opcode_aliases[i].alias;
3602 PTR val = hash_find (op_hash, name);
3603 if (!val)
3604 as_fatal ("Internal Error: Can't find %s in hash table", name);
3605 retval = hash_insert (op_hash, alias, val);
3606 if (retval)
3607 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3608 }
3609
3610 /* In MRI mode, all unsized branches are variable sized. Normally,
3611 they are word sized. */
3612 if (flag_mri)
3613 {
3614 static struct m68k_opcode_alias mri_aliases[] =
3615 {
3616 { "bhi", "jhi", },
3617 { "bls", "jls", },
3618 { "bcc", "jcc", },
3619 { "bcs", "jcs", },
3620 { "bne", "jne", },
3621 { "beq", "jeq", },
3622 { "bvc", "jvc", },
3623 { "bvs", "jvs", },
3624 { "bpl", "jpl", },
3625 { "bmi", "jmi", },
3626 { "bge", "jge", },
3627 { "blt", "jlt", },
3628 { "bgt", "jgt", },
3629 { "ble", "jle", },
3630 { "bra", "jra", },
3631 { "bsr", "jbsr", },
3632 };
3633
3634 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3635 {
3636 const char *name = mri_aliases[i].primary;
3637 const char *alias = mri_aliases[i].alias;
3638 PTR val = hash_find (op_hash, name);
3639 if (!val)
3640 as_fatal ("Internal Error: Can't find %s in hash table", name);
3641 retval = hash_jam (op_hash, alias, val);
3642 if (retval)
3643 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3644 }
3645 }
3646
3647 for (i = 0; i < sizeof (mklower_table); i++)
3648 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3649
3650 for (i = 0; i < sizeof (notend_table); i++)
3651 {
3652 notend_table[i] = 0;
3653 alt_notend_table[i] = 0;
3654 }
3655 notend_table[','] = 1;
3656 notend_table['{'] = 1;
3657 notend_table['}'] = 1;
3658 alt_notend_table['a'] = 1;
3659 alt_notend_table['A'] = 1;
3660 alt_notend_table['d'] = 1;
3661 alt_notend_table['D'] = 1;
3662 alt_notend_table['#'] = 1;
3663 alt_notend_table['&'] = 1;
3664 alt_notend_table['f'] = 1;
3665 alt_notend_table['F'] = 1;
3666 #ifdef REGISTER_PREFIX
3667 alt_notend_table[REGISTER_PREFIX] = 1;
3668 #endif
3669
3670 /* We need to put '(' in alt_notend_table to handle
3671 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3672 */
3673 alt_notend_table['('] = 1;
3674
3675 /* We need to put '@' in alt_notend_table to handle
3676 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3677 */
3678 alt_notend_table['@'] = 1;
3679
3680 /* We need to put digits in alt_notend_table to handle
3681 bfextu %d0{24:1},%d0
3682 */
3683 alt_notend_table['0'] = 1;
3684 alt_notend_table['1'] = 1;
3685 alt_notend_table['2'] = 1;
3686 alt_notend_table['3'] = 1;
3687 alt_notend_table['4'] = 1;
3688 alt_notend_table['5'] = 1;
3689 alt_notend_table['6'] = 1;
3690 alt_notend_table['7'] = 1;
3691 alt_notend_table['8'] = 1;
3692 alt_notend_table['9'] = 1;
3693
3694 #ifndef MIT_SYNTAX_ONLY
3695 /* Insert pseudo ops, these have to go into the opcode table since
3696 gas expects pseudo ops to start with a dot */
3697 {
3698 int n = 0;
3699 while (mote_pseudo_table[n].poc_name)
3700 {
3701 hack = (struct m68k_incant *)
3702 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3703 hash_insert (op_hash,
3704 mote_pseudo_table[n].poc_name, (char *) hack);
3705 hack->m_operands = 0;
3706 hack->m_opnum = n;
3707 n++;
3708 }
3709 }
3710 #endif
3711
3712 init_regtable ();
3713
3714 #ifdef OBJ_ELF
3715 record_alignment (text_section, 2);
3716 record_alignment (data_section, 2);
3717 record_alignment (bss_section, 2);
3718 #endif
3719 }
3720
3721 static void
3722 select_control_regs ()
3723 {
3724 /* Note which set of "movec" control registers is available. */
3725 switch (cpu_of_arch (current_architecture))
3726 {
3727 case m68000:
3728 control_regs = m68000_control_regs;
3729 break;
3730 case m68010:
3731 control_regs = m68010_control_regs;
3732 break;
3733 case m68020:
3734 case m68030:
3735 control_regs = m68020_control_regs;
3736 break;
3737 case m68040:
3738 control_regs = m68040_control_regs;
3739 break;
3740 case m68060:
3741 control_regs = m68060_control_regs;
3742 break;
3743 case cpu32:
3744 control_regs = cpu32_control_regs;
3745 break;
3746 case mcf5200:
3747 control_regs = mcf5200_control_regs;
3748 break;
3749 default:
3750 abort ();
3751 }
3752 }
3753
3754 void
3755 m68k_init_after_args ()
3756 {
3757 if (cpu_of_arch (current_architecture) == 0)
3758 {
3759 int i;
3760 const char *default_cpu = TARGET_CPU;
3761
3762 if (*default_cpu == 'm')
3763 default_cpu++;
3764 for (i = 0; i < n_archs; i++)
3765 if (strcasecmp (default_cpu, archs[i].name) == 0)
3766 break;
3767 if (i == n_archs)
3768 {
3769 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3770 current_architecture |= m68020;
3771 }
3772 else
3773 current_architecture |= archs[i].arch;
3774 }
3775 /* Permit m68881 specification with all cpus; those that can't work
3776 with a coprocessor could be doing emulation. */
3777 if (current_architecture & m68851)
3778 {
3779 if (current_architecture & m68040)
3780 {
3781 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3782 }
3783 }
3784 /* What other incompatibilities could we check for? */
3785
3786 /* Toss in some default assumptions about coprocessors. */
3787 if (!no_68881
3788 && (cpu_of_arch (current_architecture)
3789 /* Can CPU32 have a 68881 coprocessor?? */
3790 & (m68020 | m68030 | cpu32)))
3791 {
3792 current_architecture |= m68881;
3793 }
3794 if (!no_68851
3795 && (cpu_of_arch (current_architecture) & m68020up) != 0
3796 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3797 {
3798 current_architecture |= m68851;
3799 }
3800 if (no_68881 && (current_architecture & m68881))
3801 as_bad ("options for 68881 and no-68881 both given");
3802 if (no_68851 && (current_architecture & m68851))
3803 as_bad ("options for 68851 and no-68851 both given");
3804
3805 #ifdef OBJ_AOUT
3806 /* Work out the magic number. This isn't very general. */
3807 if (current_architecture & m68000)
3808 m68k_aout_machtype = 0;
3809 else if (current_architecture & m68010)
3810 m68k_aout_machtype = 1;
3811 else if (current_architecture & m68020)
3812 m68k_aout_machtype = 2;
3813 else
3814 m68k_aout_machtype = 2;
3815 #endif
3816
3817 /* Note which set of "movec" control registers is available. */
3818 select_control_regs ();
3819
3820 if (cpu_of_arch (current_architecture) < m68020)
3821 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3822 }
3823 \f
3824 /* This is called when a label is defined. */
3825
3826 void
3827 m68k_frob_label (sym)
3828 symbolS *sym;
3829 {
3830 struct label_line *n;
3831
3832 n = (struct label_line *) xmalloc (sizeof *n);
3833 n->next = labels;
3834 n->label = sym;
3835 as_where (&n->file, &n->line);
3836 n->text = 0;
3837 labels = n;
3838 current_label = n;
3839 }
3840
3841 /* This is called when a value that is not an instruction is emitted. */
3842
3843 void
3844 m68k_flush_pending_output ()
3845 {
3846 current_label = NULL;
3847 }
3848
3849 /* This is called at the end of the assembly, when the final value of
3850 the label is known. We warn if this is a text symbol aligned at an
3851 odd location. */
3852
3853 void
3854 m68k_frob_symbol (sym)
3855 symbolS *sym;
3856 {
3857 if ((S_GET_VALUE (sym) & 1) != 0)
3858 {
3859 struct label_line *l;
3860
3861 for (l = labels; l != NULL; l = l->next)
3862 {
3863 if (l->label == sym)
3864 {
3865 if (l->text)
3866 as_warn_where (l->file, l->line,
3867 "text label `%s' aligned to odd boundary",
3868 S_GET_NAME (sym));
3869 break;
3870 }
3871 }
3872 }
3873 }
3874 \f
3875 /* This is called if we go in or out of MRI mode because of the .mri
3876 pseudo-op. */
3877
3878 void
3879 m68k_mri_mode_change (on)
3880 int on;
3881 {
3882 if (on)
3883 {
3884 if (! flag_reg_prefix_optional)
3885 {
3886 flag_reg_prefix_optional = 1;
3887 #ifdef REGISTER_PREFIX
3888 init_regtable ();
3889 #endif
3890 }
3891 m68k_abspcadd = 1;
3892 if (! m68k_rel32_from_cmdline)
3893 m68k_rel32 = 0;
3894 }
3895 else
3896 {
3897 if (! reg_prefix_optional_seen)
3898 {
3899 #ifdef REGISTER_PREFIX_OPTIONAL
3900 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3901 #else
3902 flag_reg_prefix_optional = 0;
3903 #endif
3904 #ifdef REGISTER_PREFIX
3905 init_regtable ();
3906 #endif
3907 }
3908 m68k_abspcadd = 0;
3909 if (! m68k_rel32_from_cmdline)
3910 m68k_rel32 = 1;
3911 }
3912 }
3913
3914 /* Equal to MAX_PRECISION in atof-ieee.c */
3915 #define MAX_LITTLENUMS 6
3916
3917 /* Turn a string in input_line_pointer into a floating point constant
3918 of type type, and store the appropriate bytes in *litP. The number
3919 of LITTLENUMS emitted is stored in *sizeP . An error message is
3920 returned, or NULL on OK. */
3921
3922 char *
3923 md_atof (type, litP, sizeP)
3924 char type;
3925 char *litP;
3926 int *sizeP;
3927 {
3928 int prec;
3929 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3930 LITTLENUM_TYPE *wordP;
3931 char *t;
3932
3933 switch (type)
3934 {
3935 case 'f':
3936 case 'F':
3937 case 's':
3938 case 'S':
3939 prec = 2;
3940 break;
3941
3942 case 'd':
3943 case 'D':
3944 case 'r':
3945 case 'R':
3946 prec = 4;
3947 break;
3948
3949 case 'x':
3950 case 'X':
3951 prec = 6;
3952 break;
3953
3954 case 'p':
3955 case 'P':
3956 prec = 6;
3957 break;
3958
3959 default:
3960 *sizeP = 0;
3961 return "Bad call to MD_ATOF()";
3962 }
3963 t = atof_ieee (input_line_pointer, type, words);
3964 if (t)
3965 input_line_pointer = t;
3966
3967 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3968 for (wordP = words; prec--;)
3969 {
3970 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3971 litP += sizeof (LITTLENUM_TYPE);
3972 }
3973 return 0;
3974 }
3975
3976 void
3977 md_number_to_chars (buf, val, n)
3978 char *buf;
3979 valueT val;
3980 int n;
3981 {
3982 number_to_chars_bigendian (buf, val, n);
3983 }
3984
3985 static void
3986 md_apply_fix_2 (fixP, val)
3987 fixS *fixP;
3988 offsetT val;
3989 {
3990 addressT upper_limit;
3991 offsetT lower_limit;
3992
3993 /* This is unnecessary but it convinces the native rs6000 compiler
3994 to generate the code we want. */
3995 char *buf = fixP->fx_frag->fr_literal;
3996 buf += fixP->fx_where;
3997 /* end ibm compiler workaround */
3998
3999 if (val & 0x80000000)
4000 val |= ~(addressT)0x7fffffff;
4001 else
4002 val &= 0x7fffffff;
4003
4004 #ifdef OBJ_ELF
4005 if (fixP->fx_addsy)
4006 {
4007 memset (buf, 0, fixP->fx_size);
4008 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4009 return;
4010 }
4011 #endif
4012
4013 switch (fixP->fx_size)
4014 {
4015 /* The cast to offsetT below are necessary to make code correct for
4016 machines where ints are smaller than offsetT */
4017 case 1:
4018 *buf++ = val;
4019 upper_limit = 0x7f;
4020 lower_limit = - (offsetT) 0x80;
4021 break;
4022 case 2:
4023 *buf++ = (val >> 8);
4024 *buf++ = val;
4025 upper_limit = 0x7fff;
4026 lower_limit = - (offsetT) 0x8000;
4027 break;
4028 case 4:
4029 *buf++ = (val >> 24);
4030 *buf++ = (val >> 16);
4031 *buf++ = (val >> 8);
4032 *buf++ = val;
4033 upper_limit = 0x7fffffff;
4034 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4035 break;
4036 default:
4037 BAD_CASE (fixP->fx_size);
4038 }
4039
4040 /* Fix up a negative reloc. */
4041 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4042 {
4043 fixP->fx_addsy = fixP->fx_subsy;
4044 fixP->fx_subsy = NULL;
4045 fixP->fx_tcbit = 1;
4046 }
4047
4048 /* For non-pc-relative values, it's conceivable we might get something
4049 like "0xff" for a byte field. So extend the upper part of the range
4050 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4051 so that we can do any range checking at all. */
4052 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4053 upper_limit = upper_limit * 2 + 1;
4054
4055 if ((addressT) val > upper_limit
4056 && (val > 0 || val < lower_limit))
4057 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
4058
4059 /* A one byte PC-relative reloc means a short branch. We can't use
4060 a short branch with a value of 0 or -1, because those indicate
4061 different opcodes (branches with longer offsets). fixup_segment
4062 in write.c may have clobbered fx_pcrel, so we need to examine the
4063 reloc type. */
4064 if ((fixP->fx_pcrel
4065 #ifdef BFD_ASSEMBLER
4066 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4067 #endif
4068 )
4069 && fixP->fx_size == 1
4070 && (fixP->fx_addsy == NULL
4071 || S_IS_DEFINED (fixP->fx_addsy))
4072 && (val == 0 || val == -1))
4073 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
4074 }
4075
4076 #ifdef BFD_ASSEMBLER
4077 int
4078 md_apply_fix (fixP, valp)
4079 fixS *fixP;
4080 valueT *valp;
4081 {
4082 md_apply_fix_2 (fixP, (addressT) *valp);
4083 return 1;
4084 }
4085 #else
4086 void md_apply_fix (fixP, val)
4087 fixS *fixP;
4088 long val;
4089 {
4090 md_apply_fix_2 (fixP, (addressT) val);
4091 }
4092 #endif
4093
4094 /* *fragP has been relaxed to its final size, and now needs to have
4095 the bytes inside it modified to conform to the new size There is UGLY
4096 MAGIC here. ..
4097 */
4098 void
4099 md_convert_frag_1 (fragP)
4100 register fragS *fragP;
4101 {
4102 long disp;
4103 long ext = 0;
4104 fixS *fixP;
4105
4106 /* Address in object code of the displacement. */
4107 register int object_address = fragP->fr_fix + fragP->fr_address;
4108
4109 /* Address in gas core of the place to store the displacement. */
4110 /* This convinces the native rs6000 compiler to generate the code we
4111 want. */
4112 register char *buffer_address = fragP->fr_literal;
4113 buffer_address += fragP->fr_fix;
4114 /* end ibm compiler workaround */
4115
4116 /* The displacement of the address, from current location. */
4117 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4118 disp = (disp + fragP->fr_offset) - object_address;
4119
4120 #ifdef BFD_ASSEMBLER
4121 disp += fragP->fr_symbol->sy_frag->fr_address;
4122 #endif
4123
4124 switch (fragP->fr_subtype)
4125 {
4126 case TAB (BCC68000, BYTE):
4127 case TAB (ABRANCH, BYTE):
4128 know (issbyte (disp));
4129 if (disp == 0)
4130 as_bad ("short branch with zero offset: use :w");
4131 fragP->fr_opcode[1] = disp;
4132 ext = 0;
4133 break;
4134 case TAB (DBCC, SHORT):
4135 know (issword (disp));
4136 ext = 2;
4137 break;
4138 case TAB (BCC68000, SHORT):
4139 case TAB (ABRANCH, SHORT):
4140 know (issword (disp));
4141 fragP->fr_opcode[1] = 0x00;
4142 ext = 2;
4143 break;
4144 case TAB (ABRANCH, LONG):
4145 if (!HAVE_LONG_BRANCH(current_architecture))
4146 {
4147 if (fragP->fr_opcode[0] == 0x61)
4148 /* BSR */
4149 {
4150 fragP->fr_opcode[0] = 0x4E;
4151 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4152
4153 fix_new (fragP,
4154 fragP->fr_fix,
4155 4,
4156 fragP->fr_symbol,
4157 fragP->fr_offset,
4158 0,
4159 NO_RELOC);
4160
4161 fragP->fr_fix += 4;
4162 ext = 0;
4163 }
4164 /* BRA */
4165 else if (fragP->fr_opcode[0] == 0x60)
4166 {
4167 fragP->fr_opcode[0] = 0x4E;
4168 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4169 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4170 fragP->fr_offset, 0, NO_RELOC);
4171 fragP->fr_fix += 4;
4172 ext = 0;
4173 }
4174 else
4175 {
4176 as_bad ("Long branch offset not supported.");
4177 }
4178 }
4179 else
4180 {
4181 fragP->fr_opcode[1] = (char) 0xff;
4182 ext = 4;
4183 }
4184 break;
4185 case TAB (BCC68000, LONG):
4186 /* only Bcc 68000 instructions can come here */
4187 /* change bcc into b!cc/jmp absl long */
4188 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4189 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4190
4191 /* JF: these used to be fr_opcode[2,3], but they may be in a
4192 different frag, in which case refering to them is a no-no.
4193 Only fr_opcode[0,1] are guaranteed to work. */
4194 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4195 *buffer_address++ = (char) 0xf9;
4196 fragP->fr_fix += 2; /* account for jmp instruction */
4197 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4198 fragP->fr_offset, 0, NO_RELOC);
4199 fragP->fr_fix += 4;
4200 ext = 0;
4201 break;
4202 case TAB (DBCC, LONG):
4203 /* only DBcc 68000 instructions can come here */
4204 /* change dbcc into dbcc/jmp absl long */
4205 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4206 *buffer_address++ = 0x00; /* branch offset = 4 */
4207 *buffer_address++ = 0x04;
4208 *buffer_address++ = 0x60; /* put in bra pc+6 */
4209 *buffer_address++ = 0x06;
4210 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4211 *buffer_address++ = (char) 0xf9;
4212
4213 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4214 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4215 fragP->fr_offset, 0, NO_RELOC);
4216 fragP->fr_fix += 4;
4217 ext = 0;
4218 break;
4219 case TAB (FBRANCH, SHORT):
4220 know ((fragP->fr_opcode[1] & 0x40) == 0);
4221 ext = 2;
4222 break;
4223 case TAB (FBRANCH, LONG):
4224 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4225 ext = 4;
4226 break;
4227 case TAB (PCREL, SHORT):
4228 ext = 2;
4229 break;
4230 case TAB (PCREL, LONG):
4231 /* The thing to do here is force it to ABSOLUTE LONG, since
4232 PCREL is really trying to shorten an ABSOLUTE address anyway */
4233 /* JF FOO This code has not been tested */
4234 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4235 0, NO_RELOC);
4236 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4237 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
4238 (unsigned) fragP->fr_opcode[0],
4239 (unsigned long) fragP->fr_address);
4240 fragP->fr_opcode[1] &= ~0x3F;
4241 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4242 fragP->fr_fix += 4;
4243 ext = 0;
4244 break;
4245 case TAB (PCLEA, SHORT):
4246 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4247 fragP->fr_offset, 1, NO_RELOC);
4248 fragP->fr_opcode[1] &= ~0x3F;
4249 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4250 ext = 2;
4251 break;
4252 case TAB (PCLEA, LONG):
4253 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
4254 fragP->fr_offset, 1, NO_RELOC);
4255 fixP->fx_pcrel_adjust = 2;
4256 /* Already set to mode 7.3; this indicates: PC indirect with
4257 suppressed index, 32-bit displacement. */
4258 *buffer_address++ = 0x01;
4259 *buffer_address++ = 0x70;
4260 fragP->fr_fix += 2;
4261 ext = 4;
4262 break;
4263
4264 case TAB (PCINDEX, BYTE):
4265 disp += 2;
4266 if (!issbyte (disp))
4267 {
4268 as_bad ("displacement doesn't fit in one byte");
4269 disp = 0;
4270 }
4271 assert (fragP->fr_fix >= 2);
4272 buffer_address[-2] &= ~1;
4273 buffer_address[-1] = disp;
4274 ext = 0;
4275 break;
4276 case TAB (PCINDEX, SHORT):
4277 disp += 2;
4278 assert (issword (disp));
4279 assert (fragP->fr_fix >= 2);
4280 buffer_address[-2] |= 0x1;
4281 buffer_address[-1] = 0x20;
4282 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4283 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4284 NO_RELOC);
4285 fixP->fx_pcrel_adjust = 2;
4286 ext = 2;
4287 break;
4288 case TAB (PCINDEX, LONG):
4289 disp += 2;
4290 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4291 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4292 NO_RELOC);
4293 fixP->fx_pcrel_adjust = 2;
4294 assert (fragP->fr_fix >= 2);
4295 buffer_address[-2] |= 0x1;
4296 buffer_address[-1] = 0x30;
4297 ext = 4;
4298 break;
4299 }
4300
4301 if (ext)
4302 {
4303 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4304 fragP->fr_fix += ext;
4305 }
4306 }
4307
4308 #ifndef BFD_ASSEMBLER
4309
4310 void
4311 md_convert_frag (headers, sec, fragP)
4312 object_headers *headers;
4313 segT sec;
4314 fragS *fragP;
4315 {
4316 md_convert_frag_1 (fragP);
4317 }
4318
4319 #else
4320
4321 void
4322 md_convert_frag (abfd, sec, fragP)
4323 bfd *abfd;
4324 segT sec;
4325 fragS *fragP;
4326 {
4327 md_convert_frag_1 (fragP);
4328 }
4329 #endif
4330
4331 /* Force truly undefined symbols to their maximum size, and generally set up
4332 the frag list to be relaxed
4333 */
4334 int
4335 md_estimate_size_before_relax (fragP, segment)
4336 register fragS *fragP;
4337 segT segment;
4338 {
4339 int old_fix;
4340 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4341
4342 old_fix = fragP->fr_fix;
4343
4344 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4345 switch (fragP->fr_subtype)
4346 {
4347
4348 case TAB (ABRANCH, SZ_UNDEF):
4349 {
4350 if ((fragP->fr_symbol != NULL) /* Not absolute */
4351 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4352 {
4353 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4354 break;
4355 }
4356 else if ((fragP->fr_symbol == 0) || !HAVE_LONG_BRANCH(current_architecture))
4357 {
4358 /* On 68000, or for absolute value, switch to abs long */
4359 /* FIXME, we should check abs val, pick short or long */
4360 if (fragP->fr_opcode[0] == 0x61)
4361 {
4362 fragP->fr_opcode[0] = 0x4E;
4363 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4364 fix_new (fragP, fragP->fr_fix, 4,
4365 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4366 fragP->fr_fix += 4;
4367 frag_wane (fragP);
4368 }
4369 else if (fragP->fr_opcode[0] == 0x60)
4370 {
4371 fragP->fr_opcode[0] = 0x4E;
4372 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4373 fix_new (fragP, fragP->fr_fix, 4,
4374 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4375 fragP->fr_fix += 4;
4376 frag_wane (fragP);
4377 }
4378 else
4379 {
4380 as_warn ("Long branch offset to extern symbol not supported.");
4381 }
4382 }
4383 else
4384 { /* Symbol is still undefined. Make it simple */
4385 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4386 fragP->fr_offset, 1, NO_RELOC);
4387 fragP->fr_fix += 4;
4388 fragP->fr_opcode[1] = (char) 0xff;
4389 frag_wane (fragP);
4390 break;
4391 }
4392
4393 break;
4394 } /* case TAB(ABRANCH,SZ_UNDEF) */
4395
4396 case TAB (FBRANCH, SZ_UNDEF):
4397 {
4398 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4399 {
4400 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4401 fragP->fr_var += 2;
4402 }
4403 else
4404 {
4405 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4406 fragP->fr_offset, 1, NO_RELOC);
4407 fragP->fr_fix += 4;
4408 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4409 frag_wane (fragP);
4410 }
4411 break;
4412 } /* TAB(FBRANCH,SZ_UNDEF) */
4413
4414 case TAB (PCREL, SZ_UNDEF):
4415 {
4416 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4417 || flag_short_refs
4418 || cpu_of_arch (current_architecture) < m68020)
4419 {
4420 fragP->fr_subtype = TAB (PCREL, SHORT);
4421 fragP->fr_var += 2;
4422 }
4423 else
4424 {
4425 fragP->fr_subtype = TAB (PCREL, LONG);
4426 fragP->fr_var += 4;
4427 }
4428 break;
4429 } /* TAB(PCREL,SZ_UNDEF) */
4430
4431 case TAB (BCC68000, SZ_UNDEF):
4432 {
4433 if ((fragP->fr_symbol != NULL)
4434 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4435 {
4436 fragP->fr_subtype = TAB (BCC68000, BYTE);
4437 break;
4438 }
4439 /* only Bcc 68000 instructions can come here */
4440 /* change bcc into b!cc/jmp absl long */
4441 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4442 if (flag_short_refs)
4443 {
4444 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4445 /* JF: these were fr_opcode[2,3] */
4446 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4447 buffer_address[1] = (char) 0xf8;
4448 fragP->fr_fix += 2; /* account for jmp instruction */
4449 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4450 fragP->fr_offset, 0, NO_RELOC);
4451 fragP->fr_fix += 2;
4452 }
4453 else
4454 {
4455 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4456 /* JF: these were fr_opcode[2,3] */
4457 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4458 buffer_address[1] = (char) 0xf9;
4459 fragP->fr_fix += 2; /* account for jmp instruction */
4460 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4461 fragP->fr_offset, 0, NO_RELOC);
4462 fragP->fr_fix += 4;
4463 }
4464 frag_wane (fragP);
4465 break;
4466 } /* case TAB(BCC68000,SZ_UNDEF) */
4467
4468 case TAB (DBCC, SZ_UNDEF):
4469 {
4470 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4471 {
4472 fragP->fr_subtype = TAB (DBCC, SHORT);
4473 fragP->fr_var += 2;
4474 break;
4475 }
4476 /* only DBcc 68000 instructions can come here */
4477 /* change dbcc into dbcc/jmp absl long */
4478 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4479 buffer_address[0] = 0x00; /* branch offset = 4 */
4480 buffer_address[1] = 0x04;
4481 buffer_address[2] = 0x60; /* put in bra pc + ... */
4482
4483 if (flag_short_refs)
4484 {
4485 /* JF: these were fr_opcode[5-7] */
4486 buffer_address[3] = 0x04; /* plus 4 */
4487 buffer_address[4] = 0x4e; /* Put in Jump Word */
4488 buffer_address[5] = (char) 0xf8;
4489 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4490 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4491 fragP->fr_offset, 0, NO_RELOC);
4492 fragP->fr_fix += 2;
4493 }
4494 else
4495 {
4496 /* JF: these were fr_opcode[5-7] */
4497 buffer_address[3] = 0x06; /* Plus 6 */
4498 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4499 buffer_address[5] = (char) 0xf9;
4500 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4501 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4502 fragP->fr_offset, 0, NO_RELOC);
4503 fragP->fr_fix += 4;
4504 }
4505
4506 frag_wane (fragP);
4507 break;
4508 } /* case TAB(DBCC,SZ_UNDEF) */
4509
4510 case TAB (PCLEA, SZ_UNDEF):
4511 {
4512 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4513 || flag_short_refs
4514 || cpu_of_arch (current_architecture) < m68020)
4515 {
4516 fragP->fr_subtype = TAB (PCLEA, SHORT);
4517 fragP->fr_var += 2;
4518 }
4519 else
4520 {
4521 fragP->fr_subtype = TAB (PCLEA, LONG);
4522 fragP->fr_var += 6;
4523 }
4524 break;
4525 } /* TAB(PCLEA,SZ_UNDEF) */
4526
4527 case TAB (PCINDEX, SZ_UNDEF):
4528 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4529 || cpu_of_arch (current_architecture) < m68020)
4530 {
4531 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4532 }
4533 else
4534 {
4535 fragP->fr_subtype = TAB (PCINDEX, LONG);
4536 fragP->fr_var += 4;
4537 }
4538 break;
4539
4540 default:
4541 break;
4542 }
4543
4544 /* now that SZ_UNDEF are taken care of, check others */
4545 switch (fragP->fr_subtype)
4546 {
4547 case TAB (BCC68000, BYTE):
4548 case TAB (ABRANCH, BYTE):
4549 /* We can't do a short jump to the next instruction, so in that
4550 case we force word mode. At this point S_GET_VALUE should
4551 return the offset of the symbol within its frag. If the
4552 symbol is at the start of a frag, and it is the next frag
4553 with any data in it (usually this is just the next frag, but
4554 assembler listings may introduce empty frags), we must use
4555 word mode. */
4556 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4557 {
4558 fragS *l;
4559
4560 for (l = fragP->fr_next;
4561 l != fragP->fr_symbol->sy_frag;
4562 l = l->fr_next)
4563 if (l->fr_fix + l->fr_var != 0)
4564 break;
4565 if (l == fragP->fr_symbol->sy_frag)
4566 {
4567 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4568 fragP->fr_var += 2;
4569 }
4570 }
4571 break;
4572 default:
4573 break;
4574 }
4575 return fragP->fr_var + fragP->fr_fix - old_fix;
4576 }
4577
4578 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4579 /* the bit-field entries in the relocation_info struct plays hell
4580 with the byte-order problems of cross-assembly. So as a hack,
4581 I added this mach. dependent ri twiddler. Ugly, but it gets
4582 you there. -KWK */
4583 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4584 are symbolnum, most sig. byte first. Last byte is broken up with
4585 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4586 nibble as nuthin. (on Sun 3 at least) */
4587 /* Translate the internal relocation information into target-specific
4588 format. */
4589 #ifdef comment
4590 void
4591 md_ri_to_chars (the_bytes, ri)
4592 char *the_bytes;
4593 struct reloc_info_generic *ri;
4594 {
4595 /* this is easy */
4596 md_number_to_chars (the_bytes, ri->r_address, 4);
4597 /* now the fun stuff */
4598 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4599 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4600 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4601 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4602 ((ri->r_extern << 4) & 0x10));
4603 }
4604
4605 #endif /* comment */
4606
4607 #ifndef BFD_ASSEMBLER
4608 void
4609 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4610 char *where;
4611 fixS *fixP;
4612 relax_addressT segment_address_in_file;
4613 {
4614 /*
4615 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4616 * Out: GNU LD relocation length code: 0, 1, or 2.
4617 */
4618
4619 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4620 long r_symbolnum;
4621
4622 know (fixP->fx_addsy != NULL);
4623
4624 md_number_to_chars (where,
4625 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4626 4);
4627
4628 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4629 ? S_GET_TYPE (fixP->fx_addsy)
4630 : fixP->fx_addsy->sy_number);
4631
4632 where[4] = (r_symbolnum >> 16) & 0x0ff;
4633 where[5] = (r_symbolnum >> 8) & 0x0ff;
4634 where[6] = r_symbolnum & 0x0ff;
4635 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4636 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4637 }
4638 #endif
4639
4640 #endif /* OBJ_AOUT or OBJ_BOUT */
4641
4642 #ifndef WORKING_DOT_WORD
4643 CONST int md_short_jump_size = 4;
4644 CONST int md_long_jump_size = 6;
4645
4646 void
4647 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4648 char *ptr;
4649 addressT from_addr, to_addr;
4650 fragS *frag;
4651 symbolS *to_symbol;
4652 {
4653 valueT offset;
4654
4655 offset = to_addr - (from_addr + 2);
4656
4657 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4658 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4659 }
4660
4661 void
4662 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4663 char *ptr;
4664 addressT from_addr, to_addr;
4665 fragS *frag;
4666 symbolS *to_symbol;
4667 {
4668 valueT offset;
4669
4670 if (!HAVE_LONG_BRANCH(current_architecture))
4671 {
4672 offset = to_addr - S_GET_VALUE (to_symbol);
4673 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4674 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4675 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4676 0, NO_RELOC);
4677 }
4678 else
4679 {
4680 offset = to_addr - (from_addr + 2);
4681 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4682 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4683 }
4684 }
4685
4686 #endif
4687
4688 /* Different values of OK tell what its OK to return. Things that
4689 aren't OK are an error (what a shock, no?)
4690
4691 0: Everything is OK
4692 10: Absolute 1:8 only
4693 20: Absolute 0:7 only
4694 30: absolute 0:15 only
4695 40: Absolute 0:31 only
4696 50: absolute 0:127 only
4697 55: absolute -64:63 only
4698 60: absolute -128:127 only
4699 70: absolute 0:4095 only
4700 80: No bignums
4701
4702 */
4703
4704 static int
4705 get_num (exp, ok)
4706 struct m68k_exp *exp;
4707 int ok;
4708 {
4709 if (exp->exp.X_op == O_absent)
4710 {
4711 /* Do the same thing the VAX asm does */
4712 op (exp) = O_constant;
4713 adds (exp) = 0;
4714 subs (exp) = 0;
4715 offs (exp) = 0;
4716 if (ok == 10)
4717 {
4718 as_warn ("expression out of range: defaulting to 1");
4719 offs (exp) = 1;
4720 }
4721 }
4722 else if (exp->exp.X_op == O_constant)
4723 {
4724 switch (ok)
4725 {
4726 case 10:
4727 if (offs (exp) < 1 || offs (exp) > 8)
4728 {
4729 as_warn ("expression out of range: defaulting to 1");
4730 offs (exp) = 1;
4731 }
4732 break;
4733 case 20:
4734 if (offs (exp) < 0 || offs (exp) > 7)
4735 goto outrange;
4736 break;
4737 case 30:
4738 if (offs (exp) < 0 || offs (exp) > 15)
4739 goto outrange;
4740 break;
4741 case 40:
4742 if (offs (exp) < 0 || offs (exp) > 32)
4743 goto outrange;
4744 break;
4745 case 50:
4746 if (offs (exp) < 0 || offs (exp) > 127)
4747 goto outrange;
4748 break;
4749 case 55:
4750 if (offs (exp) < -64 || offs (exp) > 63)
4751 goto outrange;
4752 break;
4753 case 60:
4754 if (offs (exp) < -128 || offs (exp) > 127)
4755 goto outrange;
4756 break;
4757 case 70:
4758 if (offs (exp) < 0 || offs (exp) > 4095)
4759 {
4760 outrange:
4761 as_warn ("expression out of range: defaulting to 0");
4762 offs (exp) = 0;
4763 }
4764 break;
4765 default:
4766 break;
4767 }
4768 }
4769 else if (exp->exp.X_op == O_big)
4770 {
4771 if (offs (exp) <= 0 /* flonum */
4772 && (ok == 80 /* no bignums */
4773 || (ok > 10 /* small-int ranges including 0 ok */
4774 /* If we have a flonum zero, a zero integer should
4775 do as well (e.g., in moveq). */
4776 && generic_floating_point_number.exponent == 0
4777 && generic_floating_point_number.low[0] == 0)))
4778 {
4779 /* HACK! Turn it into a long */
4780 LITTLENUM_TYPE words[6];
4781
4782 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4783 op (exp) = O_constant;
4784 adds (exp) = 0;
4785 subs (exp) = 0;
4786 offs (exp) = words[1] | (words[0] << 16);
4787 }
4788 else if (ok != 0)
4789 {
4790 op (exp) = O_constant;
4791 adds (exp) = 0;
4792 subs (exp) = 0;
4793 offs (exp) = (ok == 10) ? 1 : 0;
4794 as_warn ("Can't deal with expression; defaulting to %ld",
4795 offs (exp));
4796 }
4797 }
4798 else
4799 {
4800 if (ok >= 10 && ok <= 70)
4801 {
4802 op (exp) = O_constant;
4803 adds (exp) = 0;
4804 subs (exp) = 0;
4805 offs (exp) = (ok == 10) ? 1 : 0;
4806 as_warn ("Can't deal with expression; defaulting to %ld",
4807 offs (exp));
4808 }
4809 }
4810
4811 if (exp->size != SIZE_UNSPEC)
4812 {
4813 switch (exp->size)
4814 {
4815 case SIZE_UNSPEC:
4816 case SIZE_LONG:
4817 break;
4818 case SIZE_BYTE:
4819 if (!isbyte (offs (exp)))
4820 as_warn ("expression doesn't fit in BYTE");
4821 break;
4822 case SIZE_WORD:
4823 if (!isword (offs (exp)))
4824 as_warn ("expression doesn't fit in WORD");
4825 break;
4826 }
4827 }
4828
4829 return offs (exp);
4830 }
4831
4832 /* These are the back-ends for the various machine dependent pseudo-ops. */
4833
4834 static void
4835 s_data1 (ignore)
4836 int ignore;
4837 {
4838 subseg_set (data_section, 1);
4839 demand_empty_rest_of_line ();
4840 }
4841
4842 static void
4843 s_data2 (ignore)
4844 int ignore;
4845 {
4846 subseg_set (data_section, 2);
4847 demand_empty_rest_of_line ();
4848 }
4849
4850 static void
4851 s_bss (ignore)
4852 int ignore;
4853 {
4854 /* We don't support putting frags in the BSS segment, we fake it
4855 by marking in_bss, then looking at s_skip for clues. */
4856
4857 subseg_set (bss_section, 0);
4858 demand_empty_rest_of_line ();
4859 }
4860
4861 static void
4862 s_even (ignore)
4863 int ignore;
4864 {
4865 register int temp;
4866 register long temp_fill;
4867
4868 temp = 1; /* JF should be 2? */
4869 temp_fill = get_absolute_expression ();
4870 if (!need_pass_2) /* Never make frag if expect extra pass. */
4871 frag_align (temp, (int) temp_fill, 0);
4872 demand_empty_rest_of_line ();
4873 record_alignment (now_seg, temp);
4874 }
4875
4876 static void
4877 s_proc (ignore)
4878 int ignore;
4879 {
4880 demand_empty_rest_of_line ();
4881 }
4882 \f
4883 /* Pseudo-ops handled for MRI compatibility. */
4884
4885 /* This function returns non-zero if the argument is a conditional
4886 pseudo-op. This is called when checking whether a pending
4887 alignment is needed. */
4888
4889 int
4890 m68k_conditional_pseudoop (pop)
4891 pseudo_typeS *pop;
4892 {
4893 return (pop->poc_handler == s_mri_if
4894 || pop->poc_handler == s_mri_else);
4895 }
4896
4897 /* Handle an MRI style chip specification. */
4898
4899 static void
4900 mri_chip ()
4901 {
4902 char *s;
4903 char c;
4904 int i;
4905
4906 s = input_line_pointer;
4907 /* We can't use get_symbol_end since the processor names are not proper
4908 symbols. */
4909 while (is_part_of_name (c = *input_line_pointer++))
4910 ;
4911 *--input_line_pointer = 0;
4912 for (i = 0; i < n_archs; i++)
4913 if (strcasecmp (s, archs[i].name) == 0)
4914 break;
4915 if (i >= n_archs)
4916 {
4917 as_bad ("%s: unrecognized processor name", s);
4918 *input_line_pointer = c;
4919 ignore_rest_of_line ();
4920 return;
4921 }
4922 *input_line_pointer = c;
4923
4924 if (*input_line_pointer == '/')
4925 current_architecture = 0;
4926 else
4927 current_architecture &= m68881 | m68851;
4928 current_architecture |= archs[i].arch;
4929
4930 while (*input_line_pointer == '/')
4931 {
4932 ++input_line_pointer;
4933 s = input_line_pointer;
4934 /* We can't use get_symbol_end since the processor names are not
4935 proper symbols. */
4936 while (is_part_of_name (c = *input_line_pointer++))
4937 ;
4938 *--input_line_pointer = 0;
4939 if (strcmp (s, "68881") == 0)
4940 current_architecture |= m68881;
4941 else if (strcmp (s, "68851") == 0)
4942 current_architecture |= m68851;
4943 *input_line_pointer = c;
4944 }
4945
4946 /* Update info about available control registers. */
4947 select_control_regs ();
4948 }
4949
4950 /* The MRI CHIP pseudo-op. */
4951
4952 static void
4953 s_chip (ignore)
4954 int ignore;
4955 {
4956 char *stop = NULL;
4957 char stopc;
4958
4959 if (flag_mri)
4960 stop = mri_comment_field (&stopc);
4961 mri_chip ();
4962 if (flag_mri)
4963 mri_comment_end (stop, stopc);
4964 demand_empty_rest_of_line ();
4965 }
4966
4967 /* The MRI FOPT pseudo-op. */
4968
4969 static void
4970 s_fopt (ignore)
4971 int ignore;
4972 {
4973 SKIP_WHITESPACE ();
4974
4975 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4976 {
4977 int temp;
4978
4979 input_line_pointer += 3;
4980 temp = get_absolute_expression ();
4981 if (temp < 0 || temp > 7)
4982 as_bad ("bad coprocessor id");
4983 else
4984 m68k_float_copnum = COP0 + temp;
4985 }
4986 else
4987 {
4988 as_bad ("unrecognized fopt option");
4989 ignore_rest_of_line ();
4990 return;
4991 }
4992
4993 demand_empty_rest_of_line ();
4994 }
4995
4996 /* The structure used to handle the MRI OPT pseudo-op. */
4997
4998 struct opt_action
4999 {
5000 /* The name of the option. */
5001 const char *name;
5002
5003 /* If this is not NULL, just call this function. The first argument
5004 is the ARG field of this structure, the second argument is
5005 whether the option was negated. */
5006 void (*pfn) PARAMS ((int arg, int on));
5007
5008 /* If this is not NULL, and the PFN field is NULL, set the variable
5009 this points to. Set it to the ARG field if the option was not
5010 negated, and the NOTARG field otherwise. */
5011 int *pvar;
5012
5013 /* The value to pass to PFN or to assign to *PVAR. */
5014 int arg;
5015
5016 /* The value to assign to *PVAR if the option is negated. If PFN is
5017 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5018 the option may not be negated. */
5019 int notarg;
5020 };
5021
5022 /* The table used to handle the MRI OPT pseudo-op. */
5023
5024 static void skip_to_comma PARAMS ((int, int));
5025 static void opt_nest PARAMS ((int, int));
5026 static void opt_chip PARAMS ((int, int));
5027 static void opt_list PARAMS ((int, int));
5028 static void opt_list_symbols PARAMS ((int, int));
5029
5030 static const struct opt_action opt_table[] =
5031 {
5032 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5033
5034 /* We do relaxing, so there is little use for these options. */
5035 { "b", 0, 0, 0, 0 },
5036 { "brs", 0, 0, 0, 0 },
5037 { "brb", 0, 0, 0, 0 },
5038 { "brl", 0, 0, 0, 0 },
5039 { "brw", 0, 0, 0, 0 },
5040
5041 { "c", 0, 0, 0, 0 },
5042 { "cex", 0, 0, 0, 0 },
5043 { "case", 0, &symbols_case_sensitive, 1, 0 },
5044 { "cl", 0, 0, 0, 0 },
5045 { "cre", 0, 0, 0, 0 },
5046 { "d", 0, &flag_keep_locals, 1, 0 },
5047 { "e", 0, 0, 0, 0 },
5048 { "f", 0, &flag_short_refs, 1, 0 },
5049 { "frs", 0, &flag_short_refs, 1, 0 },
5050 { "frl", 0, &flag_short_refs, 0, 1 },
5051 { "g", 0, 0, 0, 0 },
5052 { "i", 0, 0, 0, 0 },
5053 { "m", 0, 0, 0, 0 },
5054 { "mex", 0, 0, 0, 0 },
5055 { "mc", 0, 0, 0, 0 },
5056 { "md", 0, 0, 0, 0 },
5057 { "nest", opt_nest, 0, 0, 0 },
5058 { "next", skip_to_comma, 0, 0, 0 },
5059 { "o", 0, 0, 0, 0 },
5060 { "old", 0, 0, 0, 0 },
5061 { "op", skip_to_comma, 0, 0, 0 },
5062 { "pco", 0, 0, 0, 0 },
5063 { "p", opt_chip, 0, 0, 0 },
5064 { "pcr", 0, 0, 0, 0 },
5065 { "pcs", 0, 0, 0, 0 },
5066 { "r", 0, 0, 0, 0 },
5067 { "quick", 0, &m68k_quick, 1, 0 },
5068 { "rel32", 0, &m68k_rel32, 1, 0 },
5069 { "s", opt_list, 0, 0, 0 },
5070 { "t", opt_list_symbols, 0, 0, 0 },
5071 { "w", 0, &flag_no_warnings, 0, 1 },
5072 { "x", 0, 0, 0, 0 }
5073 };
5074
5075 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
5076
5077 /* The MRI OPT pseudo-op. */
5078
5079 static void
5080 s_opt (ignore)
5081 int ignore;
5082 {
5083 do
5084 {
5085 int t;
5086 char *s;
5087 char c;
5088 int i;
5089 const struct opt_action *o;
5090
5091 SKIP_WHITESPACE ();
5092
5093 t = 1;
5094 if (*input_line_pointer == '-')
5095 {
5096 ++input_line_pointer;
5097 t = 0;
5098 }
5099 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5100 {
5101 input_line_pointer += 2;
5102 t = 0;
5103 }
5104
5105 s = input_line_pointer;
5106 c = get_symbol_end ();
5107
5108 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5109 {
5110 if (strcasecmp (s, o->name) == 0)
5111 {
5112 if (o->pfn)
5113 {
5114 /* Restore input_line_pointer now in case the option
5115 takes arguments. */
5116 *input_line_pointer = c;
5117 (*o->pfn) (o->arg, t);
5118 }
5119 else if (o->pvar != NULL)
5120 {
5121 if (! t && o->arg == o->notarg)
5122 as_bad ("option `%s' may not be negated", s);
5123 *input_line_pointer = c;
5124 *o->pvar = t ? o->arg : o->notarg;
5125 }
5126 else
5127 *input_line_pointer = c;
5128 break;
5129 }
5130 }
5131 if (i >= OPTCOUNT)
5132 {
5133 as_bad ("option `%s' not recognized", s);
5134 *input_line_pointer = c;
5135 }
5136 }
5137 while (*input_line_pointer++ == ',');
5138
5139 /* Move back to terminating character. */
5140 --input_line_pointer;
5141 demand_empty_rest_of_line ();
5142 }
5143
5144 /* Skip ahead to a comma. This is used for OPT options which we do
5145 not suppor tand which take arguments. */
5146
5147 static void
5148 skip_to_comma (arg, on)
5149 int arg;
5150 int on;
5151 {
5152 while (*input_line_pointer != ','
5153 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5154 ++input_line_pointer;
5155 }
5156
5157 /* Handle the OPT NEST=depth option. */
5158
5159 static void
5160 opt_nest (arg, on)
5161 int arg;
5162 int on;
5163 {
5164 if (*input_line_pointer != '=')
5165 {
5166 as_bad ("bad format of OPT NEST=depth");
5167 return;
5168 }
5169
5170 ++input_line_pointer;
5171 max_macro_nest = get_absolute_expression ();
5172 }
5173
5174 /* Handle the OPT P=chip option. */
5175
5176 static void
5177 opt_chip (arg, on)
5178 int arg;
5179 int on;
5180 {
5181 if (*input_line_pointer != '=')
5182 {
5183 /* This is just OPT P, which we do not support. */
5184 return;
5185 }
5186
5187 ++input_line_pointer;
5188 mri_chip ();
5189 }
5190
5191 /* Handle the OPT S option. */
5192
5193 static void
5194 opt_list (arg, on)
5195 int arg;
5196 int on;
5197 {
5198 listing_list (on);
5199 }
5200
5201 /* Handle the OPT T option. */
5202
5203 static void
5204 opt_list_symbols (arg, on)
5205 int arg;
5206 int on;
5207 {
5208 if (on)
5209 listing |= LISTING_SYMBOLS;
5210 else
5211 listing &=~ LISTING_SYMBOLS;
5212 }
5213
5214 /* Handle the MRI REG pseudo-op. */
5215
5216 static void
5217 s_reg (ignore)
5218 int ignore;
5219 {
5220 char *s;
5221 int c;
5222 struct m68k_op rop;
5223 unsigned long mask;
5224 char *stop = NULL;
5225 char stopc;
5226
5227 if (line_label == NULL)
5228 {
5229 as_bad ("missing label");
5230 ignore_rest_of_line ();
5231 return;
5232 }
5233
5234 if (flag_mri)
5235 stop = mri_comment_field (&stopc);
5236
5237 SKIP_WHITESPACE ();
5238
5239 s = input_line_pointer;
5240 while (isalnum ((unsigned char) *input_line_pointer)
5241 #ifdef REGISTER_PREFIX
5242 || *input_line_pointer == REGISTER_PREFIX
5243 #endif
5244 || *input_line_pointer == '/'
5245 || *input_line_pointer == '-')
5246 ++input_line_pointer;
5247 c = *input_line_pointer;
5248 *input_line_pointer = '\0';
5249
5250 if (m68k_ip_op (s, &rop) != 0)
5251 {
5252 if (rop.error == NULL)
5253 as_bad ("bad register list");
5254 else
5255 as_bad ("bad register list: %s", rop.error);
5256 *input_line_pointer = c;
5257 ignore_rest_of_line ();
5258 return;
5259 }
5260
5261 *input_line_pointer = c;
5262
5263 if (rop.mode == REGLST)
5264 mask = rop.mask;
5265 else if (rop.mode == DREG)
5266 mask = 1 << (rop.reg - DATA0);
5267 else if (rop.mode == AREG)
5268 mask = 1 << (rop.reg - ADDR0 + 8);
5269 else if (rop.mode == FPREG)
5270 mask = 1 << (rop.reg - FP0 + 16);
5271 else if (rop.mode == CONTROL
5272 && rop.reg == FPI)
5273 mask = 1 << 24;
5274 else if (rop.mode == CONTROL
5275 && rop.reg == FPS)
5276 mask = 1 << 25;
5277 else if (rop.mode == CONTROL
5278 && rop.reg == FPC)
5279 mask = 1 << 26;
5280 else
5281 {
5282 as_bad ("bad register list");
5283 ignore_rest_of_line ();
5284 return;
5285 }
5286
5287 S_SET_SEGMENT (line_label, absolute_section);
5288 S_SET_VALUE (line_label, mask);
5289 line_label->sy_frag = &zero_address_frag;
5290
5291 if (flag_mri)
5292 mri_comment_end (stop, stopc);
5293
5294 demand_empty_rest_of_line ();
5295 }
5296
5297 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5298
5299 struct save_opts
5300 {
5301 struct save_opts *next;
5302 int abspcadd;
5303 int symbols_case_sensitive;
5304 int keep_locals;
5305 int short_refs;
5306 int architecture;
5307 int quick;
5308 int rel32;
5309 int listing;
5310 int no_warnings;
5311 /* FIXME: We don't save OPT S. */
5312 };
5313
5314 /* This variable holds the stack of saved options. */
5315
5316 static struct save_opts *save_stack;
5317
5318 /* The MRI SAVE pseudo-op. */
5319
5320 static void
5321 s_save (ignore)
5322 int ignore;
5323 {
5324 struct save_opts *s;
5325
5326 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5327 s->abspcadd = m68k_abspcadd;
5328 s->symbols_case_sensitive = symbols_case_sensitive;
5329 s->keep_locals = flag_keep_locals;
5330 s->short_refs = flag_short_refs;
5331 s->architecture = current_architecture;
5332 s->quick = m68k_quick;
5333 s->rel32 = m68k_rel32;
5334 s->listing = listing;
5335 s->no_warnings = flag_no_warnings;
5336
5337 s->next = save_stack;
5338 save_stack = s;
5339
5340 demand_empty_rest_of_line ();
5341 }
5342
5343 /* The MRI RESTORE pseudo-op. */
5344
5345 static void
5346 s_restore (ignore)
5347 int ignore;
5348 {
5349 struct save_opts *s;
5350
5351 if (save_stack == NULL)
5352 {
5353 as_bad ("restore without save");
5354 ignore_rest_of_line ();
5355 return;
5356 }
5357
5358 s = save_stack;
5359 save_stack = s->next;
5360
5361 m68k_abspcadd = s->abspcadd;
5362 symbols_case_sensitive = s->symbols_case_sensitive;
5363 flag_keep_locals = s->keep_locals;
5364 flag_short_refs = s->short_refs;
5365 current_architecture = s->architecture;
5366 m68k_quick = s->quick;
5367 m68k_rel32 = s->rel32;
5368 listing = s->listing;
5369 flag_no_warnings = s->no_warnings;
5370
5371 free (s);
5372
5373 demand_empty_rest_of_line ();
5374 }
5375
5376 /* Types of MRI structured control directives. */
5377
5378 enum mri_control_type
5379 {
5380 mri_for,
5381 mri_if,
5382 mri_repeat,
5383 mri_while
5384 };
5385
5386 /* This structure is used to stack the MRI structured control
5387 directives. */
5388
5389 struct mri_control_info
5390 {
5391 /* The directive within which this one is enclosed. */
5392 struct mri_control_info *outer;
5393
5394 /* The type of directive. */
5395 enum mri_control_type type;
5396
5397 /* Whether an ELSE has been in an IF. */
5398 int else_seen;
5399
5400 /* The add or sub statement at the end of a FOR. */
5401 char *incr;
5402
5403 /* The label of the top of a FOR or REPEAT loop. */
5404 char *top;
5405
5406 /* The label to jump to for the next iteration, or the else
5407 expression of a conditional. */
5408 char *next;
5409
5410 /* The label to jump to to break out of the loop, or the label past
5411 the end of a conditional. */
5412 char *bottom;
5413 };
5414
5415 /* The stack of MRI structured control directives. */
5416
5417 static struct mri_control_info *mri_control_stack;
5418
5419 /* The current MRI structured control directive index number, used to
5420 generate label names. */
5421
5422 static int mri_control_index;
5423
5424 /* Some function prototypes. */
5425
5426 static char *mri_control_label PARAMS ((void));
5427 static struct mri_control_info *push_mri_control
5428 PARAMS ((enum mri_control_type));
5429 static void pop_mri_control PARAMS ((void));
5430 static int parse_mri_condition PARAMS ((int *));
5431 static int parse_mri_control_operand
5432 PARAMS ((int *, char **, char **, char **, char **));
5433 static int swap_mri_condition PARAMS ((int));
5434 static int reverse_mri_condition PARAMS ((int));
5435 static void build_mri_control_operand
5436 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5437 const char *, int));
5438 static void parse_mri_control_expression
5439 PARAMS ((char *, int, const char *, const char *, int));
5440
5441 /* Generate a new MRI label structured control directive label name. */
5442
5443 static char *
5444 mri_control_label ()
5445 {
5446 char *n;
5447
5448 n = (char *) xmalloc (20);
5449 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5450 ++mri_control_index;
5451 return n;
5452 }
5453
5454 /* Create a new MRI structured control directive. */
5455
5456 static struct mri_control_info *
5457 push_mri_control (type)
5458 enum mri_control_type type;
5459 {
5460 struct mri_control_info *n;
5461
5462 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5463
5464 n->type = type;
5465 n->else_seen = 0;
5466 if (type == mri_if || type == mri_while)
5467 n->top = NULL;
5468 else
5469 n->top = mri_control_label ();
5470 n->next = mri_control_label ();
5471 n->bottom = mri_control_label ();
5472
5473 n->outer = mri_control_stack;
5474 mri_control_stack = n;
5475
5476 return n;
5477 }
5478
5479 /* Pop off the stack of MRI structured control directives. */
5480
5481 static void
5482 pop_mri_control ()
5483 {
5484 struct mri_control_info *n;
5485
5486 n = mri_control_stack;
5487 mri_control_stack = n->outer;
5488 if (n->top != NULL)
5489 free (n->top);
5490 free (n->next);
5491 free (n->bottom);
5492 free (n);
5493 }
5494
5495 /* Recognize a condition code in an MRI structured control expression. */
5496
5497 static int
5498 parse_mri_condition (pcc)
5499 int *pcc;
5500 {
5501 char c1, c2;
5502
5503 know (*input_line_pointer == '<');
5504
5505 ++input_line_pointer;
5506 c1 = *input_line_pointer++;
5507 c2 = *input_line_pointer++;
5508
5509 if (*input_line_pointer != '>')
5510 {
5511 as_bad ("syntax error in structured control directive");
5512 return 0;
5513 }
5514
5515 ++input_line_pointer;
5516 SKIP_WHITESPACE ();
5517
5518 if (isupper (c1))
5519 c1 = tolower (c1);
5520 if (isupper (c2))
5521 c2 = tolower (c2);
5522
5523 *pcc = (c1 << 8) | c2;
5524
5525 return 1;
5526 }
5527
5528 /* Parse a single operand in an MRI structured control expression. */
5529
5530 static int
5531 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5532 int *pcc;
5533 char **leftstart;
5534 char **leftstop;
5535 char **rightstart;
5536 char **rightstop;
5537 {
5538 char *s;
5539
5540 SKIP_WHITESPACE ();
5541
5542 *pcc = -1;
5543 *leftstart = NULL;
5544 *leftstop = NULL;
5545 *rightstart = NULL;
5546 *rightstop = NULL;
5547
5548 if (*input_line_pointer == '<')
5549 {
5550 /* It's just a condition code. */
5551 return parse_mri_condition (pcc);
5552 }
5553
5554 /* Look ahead for the condition code. */
5555 for (s = input_line_pointer; *s != '\0'; ++s)
5556 {
5557 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5558 break;
5559 }
5560 if (*s == '\0')
5561 {
5562 as_bad ("missing condition code in structured control directive");
5563 return 0;
5564 }
5565
5566 *leftstart = input_line_pointer;
5567 *leftstop = s;
5568 if (*leftstop > *leftstart
5569 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5570 --*leftstop;
5571
5572 input_line_pointer = s;
5573 if (! parse_mri_condition (pcc))
5574 return 0;
5575
5576 /* Look ahead for AND or OR or end of line. */
5577 for (s = input_line_pointer; *s != '\0'; ++s)
5578 {
5579 if ((strncasecmp (s, "AND", 3) == 0
5580 && (s[3] == '.' || ! is_part_of_name (s[3])))
5581 || (strncasecmp (s, "OR", 2) == 0
5582 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5583 break;
5584 }
5585
5586 *rightstart = input_line_pointer;
5587 *rightstop = s;
5588 if (*rightstop > *rightstart
5589 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5590 --*rightstop;
5591
5592 input_line_pointer = s;
5593
5594 return 1;
5595 }
5596
5597 #define MCC(b1, b2) (((b1) << 8) | (b2))
5598
5599 /* Swap the sense of a condition. This changes the condition so that
5600 it generates the same result when the operands are swapped. */
5601
5602 static int
5603 swap_mri_condition (cc)
5604 int cc;
5605 {
5606 switch (cc)
5607 {
5608 case MCC ('h', 'i'): return MCC ('c', 's');
5609 case MCC ('l', 's'): return MCC ('c', 'c');
5610 case MCC ('c', 'c'): return MCC ('l', 's');
5611 case MCC ('c', 's'): return MCC ('h', 'i');
5612 case MCC ('p', 'l'): return MCC ('m', 'i');
5613 case MCC ('m', 'i'): return MCC ('p', 'l');
5614 case MCC ('g', 'e'): return MCC ('l', 'e');
5615 case MCC ('l', 't'): return MCC ('g', 't');
5616 case MCC ('g', 't'): return MCC ('l', 't');
5617 case MCC ('l', 'e'): return MCC ('g', 'e');
5618 }
5619 return cc;
5620 }
5621
5622 /* Reverse the sense of a condition. */
5623
5624 static int
5625 reverse_mri_condition (cc)
5626 int cc;
5627 {
5628 switch (cc)
5629 {
5630 case MCC ('h', 'i'): return MCC ('l', 's');
5631 case MCC ('l', 's'): return MCC ('h', 'i');
5632 case MCC ('c', 'c'): return MCC ('c', 's');
5633 case MCC ('c', 's'): return MCC ('c', 'c');
5634 case MCC ('n', 'e'): return MCC ('e', 'q');
5635 case MCC ('e', 'q'): return MCC ('n', 'e');
5636 case MCC ('v', 'c'): return MCC ('v', 's');
5637 case MCC ('v', 's'): return MCC ('v', 'c');
5638 case MCC ('p', 'l'): return MCC ('m', 'i');
5639 case MCC ('m', 'i'): return MCC ('p', 'l');
5640 case MCC ('g', 'e'): return MCC ('l', 't');
5641 case MCC ('l', 't'): return MCC ('g', 'e');
5642 case MCC ('g', 't'): return MCC ('l', 'e');
5643 case MCC ('l', 'e'): return MCC ('g', 't');
5644 }
5645 return cc;
5646 }
5647
5648 /* Build an MRI structured control expression. This generates test
5649 and branch instructions. It goes to TRUELAB if the condition is
5650 true, and to FALSELAB if the condition is false. Exactly one of
5651 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5652 is the size qualifier for the expression. EXTENT is the size to
5653 use for the branch. */
5654
5655 static void
5656 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5657 rightstop, truelab, falselab, extent)
5658 int qual;
5659 int cc;
5660 char *leftstart;
5661 char *leftstop;
5662 char *rightstart;
5663 char *rightstop;
5664 const char *truelab;
5665 const char *falselab;
5666 int extent;
5667 {
5668 char *buf;
5669 char *s;
5670
5671 if (leftstart != NULL)
5672 {
5673 struct m68k_op leftop, rightop;
5674 char c;
5675
5676 /* Swap the compare operands, if necessary, to produce a legal
5677 m68k compare instruction. Comparing a register operand with
5678 a non-register operand requires the register to be on the
5679 right (cmp, cmpa). Comparing an immediate value with
5680 anything requires the immediate value to be on the left
5681 (cmpi). */
5682
5683 c = *leftstop;
5684 *leftstop = '\0';
5685 (void) m68k_ip_op (leftstart, &leftop);
5686 *leftstop = c;
5687
5688 c = *rightstop;
5689 *rightstop = '\0';
5690 (void) m68k_ip_op (rightstart, &rightop);
5691 *rightstop = c;
5692
5693 if (rightop.mode == IMMED
5694 || ((leftop.mode == DREG || leftop.mode == AREG)
5695 && (rightop.mode != DREG && rightop.mode != AREG)))
5696 {
5697 char *temp;
5698
5699 cc = swap_mri_condition (cc);
5700 temp = leftstart;
5701 leftstart = rightstart;
5702 rightstart = temp;
5703 temp = leftstop;
5704 leftstop = rightstop;
5705 rightstop = temp;
5706 }
5707 }
5708
5709 if (truelab == NULL)
5710 {
5711 cc = reverse_mri_condition (cc);
5712 truelab = falselab;
5713 }
5714
5715 if (leftstart != NULL)
5716 {
5717 buf = (char *) xmalloc (20
5718 + (leftstop - leftstart)
5719 + (rightstop - rightstart));
5720 s = buf;
5721 *s++ = 'c';
5722 *s++ = 'm';
5723 *s++ = 'p';
5724 if (qual != '\0')
5725 *s++ = qual;
5726 *s++ = ' ';
5727 memcpy (s, leftstart, leftstop - leftstart);
5728 s += leftstop - leftstart;
5729 *s++ = ',';
5730 memcpy (s, rightstart, rightstop - rightstart);
5731 s += rightstop - rightstart;
5732 *s = '\0';
5733 md_assemble (buf);
5734 free (buf);
5735 }
5736
5737 buf = (char *) xmalloc (20 + strlen (truelab));
5738 s = buf;
5739 *s++ = 'b';
5740 *s++ = cc >> 8;
5741 *s++ = cc & 0xff;
5742 if (extent != '\0')
5743 *s++ = extent;
5744 *s++ = ' ';
5745 strcpy (s, truelab);
5746 md_assemble (buf);
5747 free (buf);
5748 }
5749
5750 /* Parse an MRI structured control expression. This generates test
5751 and branch instructions. STOP is where the expression ends. It
5752 goes to TRUELAB if the condition is true, and to FALSELAB if the
5753 condition is false. Exactly one of TRUELAB and FALSELAB will be
5754 NULL, meaning to fall through. QUAL is the size qualifier for the
5755 expression. EXTENT is the size to use for the branch. */
5756
5757 static void
5758 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5759 char *stop;
5760 int qual;
5761 const char *truelab;
5762 const char *falselab;
5763 int extent;
5764 {
5765 int c;
5766 int cc;
5767 char *leftstart;
5768 char *leftstop;
5769 char *rightstart;
5770 char *rightstop;
5771
5772 c = *stop;
5773 *stop = '\0';
5774
5775 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5776 &rightstart, &rightstop))
5777 {
5778 *stop = c;
5779 return;
5780 }
5781
5782 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5783 {
5784 const char *flab;
5785
5786 if (falselab != NULL)
5787 flab = falselab;
5788 else
5789 flab = mri_control_label ();
5790
5791 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5792 rightstop, (const char *) NULL, flab, extent);
5793
5794 input_line_pointer += 3;
5795 if (*input_line_pointer != '.'
5796 || input_line_pointer[1] == '\0')
5797 qual = '\0';
5798 else
5799 {
5800 qual = input_line_pointer[1];
5801 input_line_pointer += 2;
5802 }
5803
5804 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5805 &rightstart, &rightstop))
5806 {
5807 *stop = c;
5808 return;
5809 }
5810
5811 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5812 rightstop, truelab, falselab, extent);
5813
5814 if (falselab == NULL)
5815 colon (flab);
5816 }
5817 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5818 {
5819 const char *tlab;
5820
5821 if (truelab != NULL)
5822 tlab = truelab;
5823 else
5824 tlab = mri_control_label ();
5825
5826 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5827 rightstop, tlab, (const char *) NULL, extent);
5828
5829 input_line_pointer += 2;
5830 if (*input_line_pointer != '.'
5831 || input_line_pointer[1] == '\0')
5832 qual = '\0';
5833 else
5834 {
5835 qual = input_line_pointer[1];
5836 input_line_pointer += 2;
5837 }
5838
5839 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5840 &rightstart, &rightstop))
5841 {
5842 *stop = c;
5843 return;
5844 }
5845
5846 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5847 rightstop, truelab, falselab, extent);
5848
5849 if (truelab == NULL)
5850 colon (tlab);
5851 }
5852 else
5853 {
5854 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5855 rightstop, truelab, falselab, extent);
5856 }
5857
5858 *stop = c;
5859 if (input_line_pointer != stop)
5860 as_bad ("syntax error in structured control directive");
5861 }
5862
5863 /* Handle the MRI IF pseudo-op. This may be a structured control
5864 directive, or it may be a regular assembler conditional, depending
5865 on its operands. */
5866
5867 static void
5868 s_mri_if (qual)
5869 int qual;
5870 {
5871 char *s;
5872 int c;
5873 struct mri_control_info *n;
5874
5875 /* A structured control directive must end with THEN with an
5876 optional qualifier. */
5877 s = input_line_pointer;
5878 while (! is_end_of_line[(unsigned char) *s]
5879 && (! flag_mri || *s != '*'))
5880 ++s;
5881 --s;
5882 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5883 --s;
5884
5885 if (s - input_line_pointer > 1
5886 && s[-1] == '.')
5887 s -= 2;
5888
5889 if (s - input_line_pointer < 3
5890 || strncasecmp (s - 3, "THEN", 4) != 0)
5891 {
5892 if (qual != '\0')
5893 {
5894 as_bad ("missing then");
5895 ignore_rest_of_line ();
5896 return;
5897 }
5898
5899 /* It's a conditional. */
5900 s_if (O_ne);
5901 return;
5902 }
5903
5904 /* Since this might be a conditional if, this pseudo-op will be
5905 called even if we are supported to be ignoring input. Double
5906 check now. Clobber *input_line_pointer so that ignore_input
5907 thinks that this is not a special pseudo-op. */
5908 c = *input_line_pointer;
5909 *input_line_pointer = 0;
5910 if (ignore_input ())
5911 {
5912 *input_line_pointer = c;
5913 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5914 ++input_line_pointer;
5915 demand_empty_rest_of_line ();
5916 return;
5917 }
5918 *input_line_pointer = c;
5919
5920 n = push_mri_control (mri_if);
5921
5922 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5923 n->next, s[1] == '.' ? s[2] : '\0');
5924
5925 if (s[1] == '.')
5926 input_line_pointer = s + 3;
5927 else
5928 input_line_pointer = s + 1;
5929
5930 if (flag_mri)
5931 {
5932 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5933 ++input_line_pointer;
5934 }
5935
5936 demand_empty_rest_of_line ();
5937 }
5938
5939 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5940 structured IF, associate the ELSE with the IF. Otherwise, assume
5941 it is a conditional else. */
5942
5943 static void
5944 s_mri_else (qual)
5945 int qual;
5946 {
5947 int c;
5948 char *buf;
5949 char q[2];
5950
5951 if (qual == '\0'
5952 && (mri_control_stack == NULL
5953 || mri_control_stack->type != mri_if
5954 || mri_control_stack->else_seen))
5955 {
5956 s_else (0);
5957 return;
5958 }
5959
5960 c = *input_line_pointer;
5961 *input_line_pointer = 0;
5962 if (ignore_input ())
5963 {
5964 *input_line_pointer = c;
5965 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5966 ++input_line_pointer;
5967 demand_empty_rest_of_line ();
5968 return;
5969 }
5970 *input_line_pointer = c;
5971
5972 if (mri_control_stack == NULL
5973 || mri_control_stack->type != mri_if
5974 || mri_control_stack->else_seen)
5975 {
5976 as_bad ("else without matching if");
5977 ignore_rest_of_line ();
5978 return;
5979 }
5980
5981 mri_control_stack->else_seen = 1;
5982
5983 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5984 q[0] = qual;
5985 q[1] = '\0';
5986 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5987 md_assemble (buf);
5988 free (buf);
5989
5990 colon (mri_control_stack->next);
5991
5992 if (flag_mri)
5993 {
5994 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5995 ++input_line_pointer;
5996 }
5997
5998 demand_empty_rest_of_line ();
5999 }
6000
6001 /* Handle the MRI ENDI pseudo-op. */
6002
6003 static void
6004 s_mri_endi (ignore)
6005 int ignore;
6006 {
6007 if (mri_control_stack == NULL
6008 || mri_control_stack->type != mri_if)
6009 {
6010 as_bad ("endi without matching if");
6011 ignore_rest_of_line ();
6012 return;
6013 }
6014
6015 /* ignore_input will not return true for ENDI, so we don't need to
6016 worry about checking it again here. */
6017
6018 if (! mri_control_stack->else_seen)
6019 colon (mri_control_stack->next);
6020 colon (mri_control_stack->bottom);
6021
6022 pop_mri_control ();
6023
6024 if (flag_mri)
6025 {
6026 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6027 ++input_line_pointer;
6028 }
6029
6030 demand_empty_rest_of_line ();
6031 }
6032
6033 /* Handle the MRI BREAK pseudo-op. */
6034
6035 static void
6036 s_mri_break (extent)
6037 int extent;
6038 {
6039 struct mri_control_info *n;
6040 char *buf;
6041 char ex[2];
6042
6043 n = mri_control_stack;
6044 while (n != NULL
6045 && n->type != mri_for
6046 && n->type != mri_repeat
6047 && n->type != mri_while)
6048 n = n->outer;
6049 if (n == NULL)
6050 {
6051 as_bad ("break outside of structured loop");
6052 ignore_rest_of_line ();
6053 return;
6054 }
6055
6056 buf = (char *) xmalloc (20 + strlen (n->bottom));
6057 ex[0] = extent;
6058 ex[1] = '\0';
6059 sprintf (buf, "bra%s %s", ex, n->bottom);
6060 md_assemble (buf);
6061 free (buf);
6062
6063 if (flag_mri)
6064 {
6065 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6066 ++input_line_pointer;
6067 }
6068
6069 demand_empty_rest_of_line ();
6070 }
6071
6072 /* Handle the MRI NEXT pseudo-op. */
6073
6074 static void
6075 s_mri_next (extent)
6076 int extent;
6077 {
6078 struct mri_control_info *n;
6079 char *buf;
6080 char ex[2];
6081
6082 n = mri_control_stack;
6083 while (n != NULL
6084 && n->type != mri_for
6085 && n->type != mri_repeat
6086 && n->type != mri_while)
6087 n = n->outer;
6088 if (n == NULL)
6089 {
6090 as_bad ("next outside of structured loop");
6091 ignore_rest_of_line ();
6092 return;
6093 }
6094
6095 buf = (char *) xmalloc (20 + strlen (n->next));
6096 ex[0] = extent;
6097 ex[1] = '\0';
6098 sprintf (buf, "bra%s %s", ex, n->next);
6099 md_assemble (buf);
6100 free (buf);
6101
6102 if (flag_mri)
6103 {
6104 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6105 ++input_line_pointer;
6106 }
6107
6108 demand_empty_rest_of_line ();
6109 }
6110
6111 /* Handle the MRI FOR pseudo-op. */
6112
6113 static void
6114 s_mri_for (qual)
6115 int qual;
6116 {
6117 const char *varstart, *varstop;
6118 const char *initstart, *initstop;
6119 const char *endstart, *endstop;
6120 const char *bystart, *bystop;
6121 int up;
6122 int by;
6123 int extent;
6124 struct mri_control_info *n;
6125 char *buf;
6126 char *s;
6127 char ex[2];
6128
6129 /* The syntax is
6130 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6131 */
6132
6133 SKIP_WHITESPACE ();
6134 varstart = input_line_pointer;
6135
6136 /* Look for the '='. */
6137 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6138 && *input_line_pointer != '=')
6139 ++input_line_pointer;
6140 if (*input_line_pointer != '=')
6141 {
6142 as_bad ("missing =");
6143 ignore_rest_of_line ();
6144 return;
6145 }
6146
6147 varstop = input_line_pointer;
6148 if (varstop > varstart
6149 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6150 --varstop;
6151
6152 ++input_line_pointer;
6153
6154 initstart = input_line_pointer;
6155
6156 /* Look for TO or DOWNTO. */
6157 up = 1;
6158 initstop = NULL;
6159 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6160 {
6161 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6162 && ! is_part_of_name (input_line_pointer[2]))
6163 {
6164 initstop = input_line_pointer;
6165 input_line_pointer += 2;
6166 break;
6167 }
6168 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6169 && ! is_part_of_name (input_line_pointer[6]))
6170 {
6171 initstop = input_line_pointer;
6172 up = 0;
6173 input_line_pointer += 6;
6174 break;
6175 }
6176 ++input_line_pointer;
6177 }
6178 if (initstop == NULL)
6179 {
6180 as_bad ("missing to or downto");
6181 ignore_rest_of_line ();
6182 return;
6183 }
6184 if (initstop > initstart
6185 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6186 --initstop;
6187
6188 SKIP_WHITESPACE ();
6189 endstart = input_line_pointer;
6190
6191 /* Look for BY or DO. */
6192 by = 0;
6193 endstop = NULL;
6194 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6195 {
6196 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6197 && ! is_part_of_name (input_line_pointer[2]))
6198 {
6199 endstop = input_line_pointer;
6200 by = 1;
6201 input_line_pointer += 2;
6202 break;
6203 }
6204 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6205 && (input_line_pointer[2] == '.'
6206 || ! is_part_of_name (input_line_pointer[2])))
6207 {
6208 endstop = input_line_pointer;
6209 input_line_pointer += 2;
6210 break;
6211 }
6212 ++input_line_pointer;
6213 }
6214 if (endstop == NULL)
6215 {
6216 as_bad ("missing do");
6217 ignore_rest_of_line ();
6218 return;
6219 }
6220 if (endstop > endstart
6221 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6222 --endstop;
6223
6224 if (! by)
6225 {
6226 bystart = "#1";
6227 bystop = bystart + 2;
6228 }
6229 else
6230 {
6231 SKIP_WHITESPACE ();
6232 bystart = input_line_pointer;
6233
6234 /* Look for DO. */
6235 bystop = NULL;
6236 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6237 {
6238 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6239 && (input_line_pointer[2] == '.'
6240 || ! is_part_of_name (input_line_pointer[2])))
6241 {
6242 bystop = input_line_pointer;
6243 input_line_pointer += 2;
6244 break;
6245 }
6246 ++input_line_pointer;
6247 }
6248 if (bystop == NULL)
6249 {
6250 as_bad ("missing do");
6251 ignore_rest_of_line ();
6252 return;
6253 }
6254 if (bystop > bystart
6255 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6256 --bystop;
6257 }
6258
6259 if (*input_line_pointer != '.')
6260 extent = '\0';
6261 else
6262 {
6263 extent = input_line_pointer[1];
6264 input_line_pointer += 2;
6265 }
6266
6267 /* We have fully parsed the FOR operands. Now build the loop. */
6268
6269 n = push_mri_control (mri_for);
6270
6271 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6272
6273 /* move init,var */
6274 s = buf;
6275 *s++ = 'm';
6276 *s++ = 'o';
6277 *s++ = 'v';
6278 *s++ = 'e';
6279 if (qual != '\0')
6280 *s++ = qual;
6281 *s++ = ' ';
6282 memcpy (s, initstart, initstop - initstart);
6283 s += initstop - initstart;
6284 *s++ = ',';
6285 memcpy (s, varstart, varstop - varstart);
6286 s += varstop - varstart;
6287 *s = '\0';
6288 md_assemble (buf);
6289
6290 colon (n->top);
6291
6292 /* cmp end,var */
6293 s = buf;
6294 *s++ = 'c';
6295 *s++ = 'm';
6296 *s++ = 'p';
6297 if (qual != '\0')
6298 *s++ = qual;
6299 *s++ = ' ';
6300 memcpy (s, endstart, endstop - endstart);
6301 s += endstop - endstart;
6302 *s++ = ',';
6303 memcpy (s, varstart, varstop - varstart);
6304 s += varstop - varstart;
6305 *s = '\0';
6306 md_assemble (buf);
6307
6308 /* bcc bottom */
6309 ex[0] = extent;
6310 ex[1] = '\0';
6311 if (up)
6312 sprintf (buf, "blt%s %s", ex, n->bottom);
6313 else
6314 sprintf (buf, "bgt%s %s", ex, n->bottom);
6315 md_assemble (buf);
6316
6317 /* Put together the add or sub instruction used by ENDF. */
6318 s = buf;
6319 if (up)
6320 strcpy (s, "add");
6321 else
6322 strcpy (s, "sub");
6323 s += 3;
6324 if (qual != '\0')
6325 *s++ = qual;
6326 *s++ = ' ';
6327 memcpy (s, bystart, bystop - bystart);
6328 s += bystop - bystart;
6329 *s++ = ',';
6330 memcpy (s, varstart, varstop - varstart);
6331 s += varstop - varstart;
6332 *s = '\0';
6333 n->incr = buf;
6334
6335 if (flag_mri)
6336 {
6337 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6338 ++input_line_pointer;
6339 }
6340
6341 demand_empty_rest_of_line ();
6342 }
6343
6344 /* Handle the MRI ENDF pseudo-op. */
6345
6346 static void
6347 s_mri_endf (ignore)
6348 int ignore;
6349 {
6350 if (mri_control_stack == NULL
6351 || mri_control_stack->type != mri_for)
6352 {
6353 as_bad ("endf without for");
6354 ignore_rest_of_line ();
6355 return;
6356 }
6357
6358 colon (mri_control_stack->next);
6359
6360 md_assemble (mri_control_stack->incr);
6361
6362 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6363 md_assemble (mri_control_stack->incr);
6364
6365 free (mri_control_stack->incr);
6366
6367 colon (mri_control_stack->bottom);
6368
6369 pop_mri_control ();
6370
6371 if (flag_mri)
6372 {
6373 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6374 ++input_line_pointer;
6375 }
6376
6377 demand_empty_rest_of_line ();
6378 }
6379
6380 /* Handle the MRI REPEAT pseudo-op. */
6381
6382 static void
6383 s_mri_repeat (ignore)
6384 int ignore;
6385 {
6386 struct mri_control_info *n;
6387
6388 n = push_mri_control (mri_repeat);
6389 colon (n->top);
6390 if (flag_mri)
6391 {
6392 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6393 ++input_line_pointer;
6394 }
6395 demand_empty_rest_of_line ();
6396 }
6397
6398 /* Handle the MRI UNTIL pseudo-op. */
6399
6400 static void
6401 s_mri_until (qual)
6402 int qual;
6403 {
6404 char *s;
6405
6406 if (mri_control_stack == NULL
6407 || mri_control_stack->type != mri_repeat)
6408 {
6409 as_bad ("until without repeat");
6410 ignore_rest_of_line ();
6411 return;
6412 }
6413
6414 colon (mri_control_stack->next);
6415
6416 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6417 ;
6418
6419 parse_mri_control_expression (s, qual, (const char *) NULL,
6420 mri_control_stack->top, '\0');
6421
6422 colon (mri_control_stack->bottom);
6423
6424 input_line_pointer = s;
6425
6426 pop_mri_control ();
6427
6428 if (flag_mri)
6429 {
6430 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6431 ++input_line_pointer;
6432 }
6433
6434 demand_empty_rest_of_line ();
6435 }
6436
6437 /* Handle the MRI WHILE pseudo-op. */
6438
6439 static void
6440 s_mri_while (qual)
6441 int qual;
6442 {
6443 char *s;
6444
6445 struct mri_control_info *n;
6446
6447 s = input_line_pointer;
6448 while (! is_end_of_line[(unsigned char) *s]
6449 && (! flag_mri || *s != '*'))
6450 s++;
6451 --s;
6452 while (*s == ' ' || *s == '\t')
6453 --s;
6454 if (s - input_line_pointer > 1
6455 && s[-1] == '.')
6456 s -= 2;
6457 if (s - input_line_pointer < 2
6458 || strncasecmp (s - 1, "DO", 2) != 0)
6459 {
6460 as_bad ("missing do");
6461 ignore_rest_of_line ();
6462 return;
6463 }
6464
6465 n = push_mri_control (mri_while);
6466
6467 colon (n->next);
6468
6469 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6470 s[1] == '.' ? s[2] : '\0');
6471
6472 input_line_pointer = s + 1;
6473 if (*input_line_pointer == '.')
6474 input_line_pointer += 2;
6475
6476 if (flag_mri)
6477 {
6478 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6479 ++input_line_pointer;
6480 }
6481
6482 demand_empty_rest_of_line ();
6483 }
6484
6485 /* Handle the MRI ENDW pseudo-op. */
6486
6487 static void
6488 s_mri_endw (ignore)
6489 int ignore;
6490 {
6491 char *buf;
6492
6493 if (mri_control_stack == NULL
6494 || mri_control_stack->type != mri_while)
6495 {
6496 as_bad ("endw without while");
6497 ignore_rest_of_line ();
6498 return;
6499 }
6500
6501 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6502 sprintf (buf, "bra %s", mri_control_stack->next);
6503 md_assemble (buf);
6504 free (buf);
6505
6506 colon (mri_control_stack->bottom);
6507
6508 pop_mri_control ();
6509
6510 if (flag_mri)
6511 {
6512 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6513 ++input_line_pointer;
6514 }
6515
6516 demand_empty_rest_of_line ();
6517 }
6518 \f
6519 /*
6520 * md_parse_option
6521 * Invocation line includes a switch not recognized by the base assembler.
6522 * See if it's a processor-specific option. These are:
6523 *
6524 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6525 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6526 * Select the architecture. Instructions or features not
6527 * supported by the selected architecture cause fatal
6528 * errors. More than one may be specified. The default is
6529 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6530 * for -m68000, and -m68882 is a synonym for -m68881.
6531 * -[A]m[c]no-68851, -[A]m[c]no-68881
6532 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6533 * so don't use or document it, but that's the way the parsing
6534 * works).
6535 *
6536 * -pic Indicates PIC.
6537 * -k Indicates PIC. (Sun 3 only.)
6538 *
6539 * --bitwise-or
6540 * Permit `|' to be used in expressions.
6541 *
6542 */
6543
6544 #ifdef OBJ_ELF
6545 CONST char *md_shortopts = "lSA:m:kQ:V";
6546 #else
6547 CONST char *md_shortopts = "lSA:m:k";
6548 #endif
6549
6550 struct option md_longopts[] = {
6551 #define OPTION_PIC (OPTION_MD_BASE)
6552 {"pic", no_argument, NULL, OPTION_PIC},
6553 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6554 {"register-prefix-optional", no_argument, NULL,
6555 OPTION_REGISTER_PREFIX_OPTIONAL},
6556 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6557 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6558 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6559 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6560 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6561 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6562 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6563 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6564 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6565 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6566 {NULL, no_argument, NULL, 0}
6567 };
6568 size_t md_longopts_size = sizeof(md_longopts);
6569
6570 int
6571 md_parse_option (c, arg)
6572 int c;
6573 char *arg;
6574 {
6575 switch (c)
6576 {
6577 case 'l': /* -l means keep external to 2 bit offset
6578 rather than 16 bit one */
6579 flag_short_refs = 1;
6580 break;
6581
6582 case 'S': /* -S means that jbsr's always turn into
6583 jsr's. */
6584 flag_long_jumps = 1;
6585 break;
6586
6587 case 'A':
6588 if (*arg == 'm')
6589 arg++;
6590 /* intentional fall-through */
6591 case 'm':
6592
6593 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6594 {
6595 int i;
6596 unsigned long arch;
6597 const char *oarg = arg;
6598
6599 arg += 3;
6600 if (*arg == 'm')
6601 {
6602 arg++;
6603 if (arg[0] == 'c' && arg[1] == '6')
6604 arg++;
6605 }
6606 for (i = 0; i < n_archs; i++)
6607 if (!strcmp (arg, archs[i].name))
6608 break;
6609 if (i == n_archs)
6610 {
6611 unknown:
6612 as_bad ("unrecognized option `%s'", oarg);
6613 return 0;
6614 }
6615 arch = archs[i].arch;
6616 if (arch == m68881)
6617 no_68881 = 1;
6618 else if (arch == m68851)
6619 no_68851 = 1;
6620 else
6621 goto unknown;
6622 }
6623 else
6624 {
6625 int i;
6626
6627 if (arg[0] == 'c' && arg[1] == '6')
6628 arg++;
6629
6630 for (i = 0; i < n_archs; i++)
6631 if (!strcmp (arg, archs[i].name))
6632 {
6633 unsigned long arch = archs[i].arch;
6634 if (cpu_of_arch (arch))
6635 /* It's a cpu spec. */
6636 {
6637 current_architecture &= ~m68000up;
6638 current_architecture |= arch;
6639 }
6640 else if (arch == m68881)
6641 {
6642 current_architecture |= m68881;
6643 no_68881 = 0;
6644 }
6645 else if (arch == m68851)
6646 {
6647 current_architecture |= m68851;
6648 no_68851 = 0;
6649 }
6650 else
6651 /* ??? */
6652 abort ();
6653 break;
6654 }
6655 if (i == n_archs)
6656 {
6657 as_bad ("unrecognized architecture specification `%s'", arg);
6658 return 0;
6659 }
6660 }
6661 break;
6662
6663 case OPTION_PIC:
6664 case 'k':
6665 flag_want_pic = 1;
6666 break; /* -pic, Position Independent Code */
6667
6668 case OPTION_REGISTER_PREFIX_OPTIONAL:
6669 flag_reg_prefix_optional = 1;
6670 reg_prefix_optional_seen = 1;
6671 break;
6672
6673 /* -V: SVR4 argument to print version ID. */
6674 case 'V':
6675 print_version_id ();
6676 break;
6677
6678 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6679 should be emitted or not. FIXME: Not implemented. */
6680 case 'Q':
6681 break;
6682
6683 case OPTION_BITWISE_OR:
6684 {
6685 char *n, *t;
6686 const char *s;
6687
6688 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6689 t = n;
6690 for (s = m68k_comment_chars; *s != '\0'; s++)
6691 if (*s != '|')
6692 *t++ = *s;
6693 *t = '\0';
6694 m68k_comment_chars = n;
6695 }
6696 break;
6697
6698 case OPTION_BASE_SIZE_DEFAULT_16:
6699 m68k_index_width_default = SIZE_WORD;
6700 break;
6701
6702 case OPTION_BASE_SIZE_DEFAULT_32:
6703 m68k_index_width_default = SIZE_LONG;
6704 break;
6705
6706 case OPTION_DISP_SIZE_DEFAULT_16:
6707 m68k_rel32 = 0;
6708 m68k_rel32_from_cmdline = 1;
6709 break;
6710
6711 case OPTION_DISP_SIZE_DEFAULT_32:
6712 m68k_rel32 = 1;
6713 m68k_rel32_from_cmdline = 1;
6714 break;
6715
6716 default:
6717 return 0;
6718 }
6719
6720 return 1;
6721 }
6722
6723 void
6724 md_show_usage (stream)
6725 FILE *stream;
6726 {
6727 fprintf(stream, "\
6728 680X0 options:\n\
6729 -l use 1 word for refs to undefined symbols [default 2]\n\
6730 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6731 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6732 | -mcpu32 | -m5200\n\
6733 specify variant of 680X0 architecture [default 68020]\n\
6734 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6735 target has/lacks floating-point coprocessor\n\
6736 [default yes for 68020, 68030, and cpu32]\n");
6737 fprintf(stream, "\
6738 -m68851 | -mno-68851\n\
6739 target has/lacks memory-management unit coprocessor\n\
6740 [default yes for 68020 and up]\n\
6741 -pic, -k generate position independent code\n\
6742 -S turn jbsr into jsr\n\
6743 --register-prefix-optional\n\
6744 recognize register names without prefix character\n\
6745 --bitwise-or do not treat `|' as a comment character\n");
6746 fprintf (stream, "\
6747 --base-size-default-16 base reg without size is 16 bits\n\
6748 --base-size-default-32 base reg without size is 32 bits (default)\n\
6749 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6750 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n");
6751 }
6752 \f
6753 #ifdef TEST2
6754
6755 /* TEST2: Test md_assemble() */
6756 /* Warning, this routine probably doesn't work anymore */
6757
6758 main ()
6759 {
6760 struct m68k_it the_ins;
6761 char buf[120];
6762 char *cp;
6763 int n;
6764
6765 m68k_ip_begin ();
6766 for (;;)
6767 {
6768 if (!gets (buf) || !*buf)
6769 break;
6770 if (buf[0] == '|' || buf[1] == '.')
6771 continue;
6772 for (cp = buf; *cp; cp++)
6773 if (*cp == '\t')
6774 *cp = ' ';
6775 if (is_label (buf))
6776 continue;
6777 memset (&the_ins, '\0', sizeof (the_ins));
6778 m68k_ip (&the_ins, buf);
6779 if (the_ins.error)
6780 {
6781 printf ("Error %s in %s\n", the_ins.error, buf);
6782 }
6783 else
6784 {
6785 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6786 for (n = 0; n < the_ins.numo; n++)
6787 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6788 printf (" ");
6789 print_the_insn (&the_ins.opcode[0], stdout);
6790 (void) putchar ('\n');
6791 }
6792 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6793 {
6794 if (the_ins.operands[n].error)
6795 {
6796 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6797 continue;
6798 }
6799 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6800 if (the_ins.operands[n].b_const)
6801 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6802 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6803 if (the_ins.operands[n].b_iadd)
6804 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6805 (void) putchar ('\n');
6806 }
6807 }
6808 m68k_ip_end ();
6809 return 0;
6810 }
6811
6812 is_label (str)
6813 char *str;
6814 {
6815 while (*str == ' ')
6816 str++;
6817 while (*str && *str != ' ')
6818 str++;
6819 if (str[-1] == ':' || str[1] == '=')
6820 return 1;
6821 return 0;
6822 }
6823
6824 #endif
6825
6826 /* Possible states for relaxation:
6827
6828 0 0 branch offset byte (bra, etc)
6829 0 1 word
6830 0 2 long
6831
6832 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6833 1 1 word
6834 1 2 long
6835
6836 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6837 2 1 word-long
6838 2 2 long-word
6839 2 3 long-long
6840
6841 */
6842
6843 /* We have no need to default values of symbols. */
6844
6845 /* ARGSUSED */
6846 symbolS *
6847 md_undefined_symbol (name)
6848 char *name;
6849 {
6850 return 0;
6851 }
6852
6853 /* Round up a section size to the appropriate boundary. */
6854 valueT
6855 md_section_align (segment, size)
6856 segT segment;
6857 valueT size;
6858 {
6859 #ifdef OBJ_AOUT
6860 #ifdef BFD_ASSEMBLER
6861 /* For a.out, force the section size to be aligned. If we don't do
6862 this, BFD will align it for us, but it will not write out the
6863 final bytes of the section. This may be a bug in BFD, but it is
6864 easier to fix it here since that is how the other a.out targets
6865 work. */
6866 int align;
6867
6868 align = bfd_get_section_alignment (stdoutput, segment);
6869 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6870 #endif
6871 #endif
6872
6873 return size;
6874 }
6875
6876 /* Exactly what point is a PC-relative offset relative TO?
6877 On the 68k, it is relative to the address of the first extension
6878 word. The difference between the addresses of the offset and the
6879 first extension word is stored in fx_pcrel_adjust. */
6880 long
6881 md_pcrel_from (fixP)
6882 fixS *fixP;
6883 {
6884 int adjust;
6885
6886 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6887 -1 as 64. */
6888 adjust = fixP->fx_pcrel_adjust;
6889 if (adjust == 64)
6890 adjust = -1;
6891 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6892 }
6893
6894 #ifndef BFD_ASSEMBLER
6895 #ifdef OBJ_COFF
6896
6897 /*ARGSUSED*/
6898 void
6899 tc_coff_symbol_emit_hook (ignore)
6900 symbolS *ignore;
6901 {
6902 }
6903
6904 int
6905 tc_coff_sizemachdep (frag)
6906 fragS *frag;
6907 {
6908 switch (frag->fr_subtype & 0x3)
6909 {
6910 case BYTE:
6911 return 1;
6912 case SHORT:
6913 return 2;
6914 case LONG:
6915 return 4;
6916 default:
6917 abort ();
6918 return 0;
6919 }
6920 }
6921
6922 #endif
6923 #endif
6924
6925 /* end of tc-m68k.c */