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[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #define NO_RELOC 0
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This array holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful */
32 #if defined (OBJ_ELF) || defined (TE_DELTA)
33 const char comment_chars[] = "|#";
34 #else
35 const char comment_chars[] = "|";
36 #endif
37
38 /* This array holds the chars that only start a comment at the beginning of
39 a line. If the line seems to have the form '# 123 filename'
40 .line and .file directives will appear in the pre-processed output */
41 /* Note that input_file.c hand checks for '#' at the beginning of the
42 first line of the input file. This is because the compiler outputs
43 #NO_APP at the beginning of its output. */
44 /* Also note that comments like this one will always work. */
45 const char line_comment_chars[] = "#";
46
47 const char line_separator_chars[] = "";
48
49 /* Chars that can be used to separate mant from exp in floating point nums */
50 CONST char EXP_CHARS[] = "eE";
51
52 /* Chars that mean this number is a floating point constant, as
53 in "0f12.456" or "0d1.2345e12". */
54
55 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
56
57 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
58 changed in read.c . Ideally it shouldn't have to know about it at all,
59 but nothing is ideal around here. */
60
61 const int md_reloc_size = 8; /* Size of relocation record */
62
63 /* Are we trying to generate PIC code? If so, absolute references
64 ought to be made into linkage table references or pc-relative
65 references. */
66 int flag_want_pic;
67
68 static int flag_short_refs; /* -l option */
69 static int flag_long_jumps; /* -S option */
70
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 #else
74 int flag_reg_prefix_optional;
75 #endif
76
77 /* The floating point coprocessor to use by default. */
78 static enum m68k_register m68k_float_copnum = COP1;
79
80 /* If this is non-zero, then references to number(%pc) will be taken
81 to refer to number, rather than to %pc + number. */
82 static int m68k_abspcadd;
83
84 /* If this is non-zero, then the quick forms of the move, add, and sub
85 instructions are used when possible. */
86 static int m68k_quick = 1;
87
88 /* If this is non-zero, then if the size is not specified for a base
89 or outer displacement, the assembler assumes that the size should
90 be 32 bits. */
91 static int m68k_rel32 = 1;
92
93 /* Its an arbitrary name: This means I don't approve of it */
94 /* See flames below */
95 static struct obstack robyn;
96
97 #define TAB(x,y) (((x)<<2)+(y))
98 #define TABTYPE(xy) ((xy) >> 2)
99 #define BYTE 0
100 #define SHORT 1
101 #define LONG 2
102 #define SZ_UNDEF 3
103 #undef BRANCH
104 /* Case `g' except when BCC68000 is applicable. */
105 #define ABRANCH 1
106 /* Coprocessor branches. */
107 #define FBRANCH 2
108 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
109 supported on all cpus. Widens to 32-bit absolute. */
110 #define PCREL 3
111 /* For inserting an extra jmp instruction with long offset on 68000,
112 for expanding conditional branches. (Not bsr or bra.) Since the
113 68000 doesn't support 32-bit displacements for conditional
114 branches, we fake it by reversing the condition and branching
115 around a jmp with an absolute long operand. */
116 #define BCC68000 4
117 /* For the DBcc "instructions". If the displacement requires 32 bits,
118 the branch-around-a-jump game is played here too. */
119 #define DBCC 5
120 /* Not currently used? */
121 #define PCLEA 6
122 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
123 in 16 or 8 bits. */
124 #define PCINDEX 7
125
126 struct m68k_incant
127 {
128 const char *m_operands;
129 unsigned long m_opcode;
130 short m_opnum;
131 short m_codenum;
132 int m_arch;
133 struct m68k_incant *m_next;
134 };
135
136 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
137 #define gettwo(x) (((x)->m_opcode)&0xffff)
138
139 static const enum m68k_register m68000_control_regs[] = { 0 };
140 static const enum m68k_register m68010_control_regs[] = {
141 SFC, DFC, USP, VBR,
142 0
143 };
144 static const enum m68k_register m68020_control_regs[] = {
145 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
146 0
147 };
148 static const enum m68k_register m68040_control_regs[] = {
149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
150 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
151 0
152 };
153 static const enum m68k_register m68060_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
155 USP, VBR, URP, SRP, PCR,
156 0
157 };
158 #define cpu32_control_regs m68010_control_regs
159
160 static const enum m68k_register *control_regs;
161
162 /* internal form of a 68020 instruction */
163 struct m68k_it
164 {
165 const char *error;
166 const char *args; /* list of opcode info */
167 int numargs;
168
169 int numo; /* Number of shorts in opcode */
170 short opcode[11];
171
172 struct m68k_op operands[6];
173
174 int nexp; /* number of exprs in use */
175 struct m68k_exp exprs[4];
176
177 int nfrag; /* Number of frags we have to produce */
178 struct
179 {
180 int fragoff; /* Where in the current opcode the frag ends */
181 symbolS *fadd;
182 long foff;
183 int fragty;
184 }
185 fragb[4];
186
187 int nrel; /* Num of reloc strucs in use */
188 struct
189 {
190 int n;
191 expressionS exp;
192 char wid;
193 char pcrel;
194 /* In a pc relative address the difference between the address
195 of the offset and the address that the offset is relative
196 to. This depends on the addressing mode. Basically this
197 is the value to put in the offset field to address the
198 first byte of the offset, without regarding the special
199 significance of some values (in the branch instruction, for
200 example). */
201 int pcrel_fix;
202 }
203 reloc[5]; /* Five is enough??? */
204 };
205
206 #define cpu_of_arch(x) ((x) & m68000up)
207 #define float_of_arch(x) ((x) & mfloat)
208 #define mmu_of_arch(x) ((x) & mmmu)
209
210 static struct m68k_it the_ins; /* the instruction being assembled */
211
212 #define op(ex) ((ex)->exp.X_op)
213 #define adds(ex) ((ex)->exp.X_add_symbol)
214 #define subs(ex) ((ex)->exp.X_op_symbol)
215 #define offs(ex) ((ex)->exp.X_add_number)
216
217 /* Macros for adding things to the m68k_it struct */
218
219 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
220
221 /* Like addword, but goes BEFORE general operands */
222 static void
223 insop (w, opcode)
224 int w;
225 struct m68k_incant *opcode;
226 {
227 int z;
228 for(z=the_ins.numo;z>opcode->m_codenum;--z)
229 the_ins.opcode[z]=the_ins.opcode[z-1];
230 for(z=0;z<the_ins.nrel;z++)
231 the_ins.reloc[z].n+=2;
232 for (z = 0; z < the_ins.nfrag; z++)
233 the_ins.fragb[z].fragoff++;
234 the_ins.opcode[opcode->m_codenum]=w;
235 the_ins.numo++;
236 }
237
238 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
239 Blecch. */
240 static void
241 add_fix (width, exp, pc_rel, pc_fix)
242 char width;
243 struct m68k_exp *exp;
244 int pc_rel;
245 int pc_fix;
246 {
247 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
248 ? (the_ins.numo*2-1)
249 : (((width)=='b')
250 ? (the_ins.numo*2+1)
251 : (the_ins.numo*2)));
252 the_ins.reloc[the_ins.nrel].exp = exp->exp;
253 the_ins.reloc[the_ins.nrel].wid = width;
254 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
255 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
256 }
257
258 /* Cause an extra frag to be generated here, inserting up to 10 bytes
259 (that value is chosen in the frag_var call in md_assemble). TYPE
260 is the subtype of the frag to be generated; its primary type is
261 rs_machine_dependent.
262
263 The TYPE parameter is also used by md_convert_frag_1 and
264 md_estimate_size_before_relax. The appropriate type of fixup will
265 be emitted by md_convert_frag_1.
266
267 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
268 static void
269 add_frag(add,off,type)
270 symbolS *add;
271 long off;
272 int type;
273 {
274 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
275 the_ins.fragb[the_ins.nfrag].fadd=add;
276 the_ins.fragb[the_ins.nfrag].foff=off;
277 the_ins.fragb[the_ins.nfrag++].fragty=type;
278 }
279
280 #define isvar(ex) \
281 (op (ex) != O_constant && op (ex) != O_big)
282
283 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
284 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
285 static int reverse_16_bits PARAMS ((int in));
286 static int reverse_8_bits PARAMS ((int in));
287 static void install_gen_operand PARAMS ((int mode, int val));
288 static void install_operand PARAMS ((int mode, int val));
289 static void s_bss PARAMS ((int));
290 static void s_data1 PARAMS ((int));
291 static void s_data2 PARAMS ((int));
292 static void s_even PARAMS ((int));
293 static void s_proc PARAMS ((int));
294 static void mri_chip PARAMS ((void));
295 static void s_chip PARAMS ((int));
296 static void s_fopt PARAMS ((int));
297 static void s_opt PARAMS ((int));
298 static void s_reg PARAMS ((int));
299 static void s_restore PARAMS ((int));
300 static void s_save PARAMS ((int));
301 static void s_mri_if PARAMS ((int));
302 static void s_mri_else PARAMS ((int));
303 static void s_mri_endi PARAMS ((int));
304 static void s_mri_break PARAMS ((int));
305 static void s_mri_next PARAMS ((int));
306 static void s_mri_for PARAMS ((int));
307 static void s_mri_endf PARAMS ((int));
308 static void s_mri_repeat PARAMS ((int));
309 static void s_mri_until PARAMS ((int));
310 static void s_mri_while PARAMS ((int));
311 static void s_mri_endw PARAMS ((int));
312
313 static int current_architecture;
314
315 struct m68k_cpu {
316 unsigned long arch;
317 const char *name;
318 int alias;
319 };
320
321 static const struct m68k_cpu archs[] = {
322 { m68000, "68000", 0 },
323 { m68010, "68010", 0 },
324 { m68020, "68020", 0 },
325 { m68030, "68030", 0 },
326 { m68040, "68040", 0 },
327 { m68060, "68060", 0 },
328 { cpu32, "cpu32", 0 },
329 { m68881, "68881", 0 },
330 { m68851, "68851", 0 },
331 /* Aliases (effectively, so far as gas is concerned) for the above
332 cpus. */
333 { m68020, "68k", 1 },
334 { m68000, "68302", 1 },
335 { m68000, "68008", 1 },
336 { m68000, "68ec000", 1 },
337 { m68000, "68hc000", 1 },
338 { m68000, "68hc001", 1 },
339 { m68020, "68ec020", 1 },
340 { m68030, "68ec030", 1 },
341 { m68040, "68ec040", 1 },
342 { cpu32, "68330", 1 },
343 { cpu32, "68331", 1 },
344 { cpu32, "68332", 1 },
345 { cpu32, "68333", 1 },
346 { cpu32, "68340", 1 },
347 { cpu32, "68360", 1 },
348 { m68881, "68882", 1 },
349 };
350
351 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
352
353 /* BCC68000 is for patching in an extra jmp instruction for long offsets
354 on the 68000. The 68000 doesn't support long branches with branchs */
355
356 /* This table desribes how you change sizes for the various types of variable
357 size expressions. This version only supports two kinds. */
358
359 /* Note that calls to frag_var need to specify the maximum expansion
360 needed; this is currently 10 bytes for DBCC. */
361
362 /* The fields are:
363 How far Forward this mode will reach:
364 How far Backward this mode will reach:
365 How many bytes this mode will add to the size of the frag
366 Which mode to go to if the offset won't fit in this one
367 */
368 relax_typeS md_relax_table[] =
369 {
370 {1, 1, 0, 0}, /* First entries aren't used */
371 {1, 1, 0, 0}, /* For no good reason except */
372 {1, 1, 0, 0}, /* that the VAX doesn't either */
373 {1, 1, 0, 0},
374
375 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
376 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
377 {0, 0, 4, 0},
378 {1, 1, 0, 0},
379
380 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
381 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
382 {0, 0, 4, 0},
383 {1, 1, 0, 0},
384
385 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
386 {(32767), (-32768), 2, TAB (PCREL, LONG)},
387 {0, 0, 4, 0},
388 {1, 1, 0, 0},
389
390 {(127), (-128), 0, TAB (BCC68000, SHORT)},
391 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
392 {0, 0, 6, 0}, /* jmp long space */
393 {1, 1, 0, 0},
394
395 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
396 {(32767), (-32768), 2, TAB (DBCC, LONG)},
397 {0, 0, 10, 0}, /* bra/jmp long space */
398 {1, 1, 0, 0},
399
400 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
401 {32767, -32768, 2, TAB (PCLEA, LONG)},
402 {0, 0, 6, 0},
403 {1, 1, 0, 0},
404
405 /* For, e.g., jmp pcrel indexed. */
406 {125, -130, 0, TAB (PCINDEX, SHORT)},
407 {32765, -32770, 2, TAB (PCINDEX, LONG)},
408 {0, 0, 4, 0},
409 {1, 1, 0, 0},
410 };
411
412 /* These are the machine dependent pseudo-ops. These are included so
413 the assembler can work on the output from the SUN C compiler, which
414 generates these.
415 */
416
417 /* This table describes all the machine specific pseudo-ops the assembler
418 has to support. The fields are:
419 pseudo-op name without dot
420 function to call to execute this pseudo-op
421 Integer arg to pass to the function
422 */
423 const pseudo_typeS md_pseudo_table[] =
424 {
425 {"data1", s_data1, 0},
426 {"data2", s_data2, 0},
427 {"bss", s_bss, 0},
428 {"even", s_even, 0},
429 {"skip", s_space, 0},
430 {"proc", s_proc, 0},
431 #ifdef TE_SUN3
432 {"align", s_align_bytes, 0},
433 #endif
434 #ifdef OBJ_ELF
435 {"swbeg", s_ignore, 0},
436 #endif
437 {"extend", float_cons, 'x'},
438 {"ldouble", float_cons, 'x'},
439
440 /* The following pseudo-ops are supported for MRI compatibility. */
441 {"chip", s_chip, 0},
442 {"comline", s_space, 1},
443 {"fopt", s_fopt, 0},
444 {"mask2", s_ignore, 0},
445 {"opt", s_opt, 0},
446 {"reg", s_reg, 0},
447 {"restore", s_restore, 0},
448 {"save", s_save, 0},
449
450 {"if", s_mri_if, 0},
451 {"if.b", s_mri_if, 'b'},
452 {"if.w", s_mri_if, 'w'},
453 {"if.l", s_mri_if, 'l'},
454 {"else", s_mri_else, 0},
455 {"else.s", s_mri_else, 's'},
456 {"else.l", s_mri_else, 'l'},
457 {"endi", s_mri_endi, 0},
458 {"break", s_mri_break, 0},
459 {"break.s", s_mri_break, 's'},
460 {"break.l", s_mri_break, 'l'},
461 {"next", s_mri_next, 0},
462 {"next.s", s_mri_next, 's'},
463 {"next.l", s_mri_next, 'l'},
464 {"for", s_mri_for, 0},
465 {"for.b", s_mri_for, 'b'},
466 {"for.w", s_mri_for, 'w'},
467 {"for.l", s_mri_for, 'l'},
468 {"endf", s_mri_endf, 0},
469 {"repeat", s_mri_repeat, 0},
470 {"until", s_mri_until, 0},
471 {"until.b", s_mri_until, 'b'},
472 {"until.w", s_mri_until, 'w'},
473 {"until.l", s_mri_until, 'l'},
474 {"while", s_mri_while, 0},
475 {"while.b", s_mri_while, 'b'},
476 {"while.w", s_mri_while, 'w'},
477 {"while.l", s_mri_while, 'l'},
478 {"endw", s_mri_endw, 0},
479
480 {0, 0, 0}
481 };
482
483
484 /* The mote pseudo ops are put into the opcode table, since they
485 don't start with a . they look like opcodes to gas.
486 */
487 extern void obj_coff_section ();
488
489 CONST pseudo_typeS mote_pseudo_table[] =
490 {
491
492 {"dcl", cons, 4},
493 {"dc", cons, 2},
494 {"dcw", cons, 2},
495 {"dcb", cons, 1},
496
497 {"dsl", s_space, 4},
498 {"ds", s_space, 2},
499 {"dsw", s_space, 2},
500 {"dsb", s_space, 1},
501
502 {"xdef", s_globl, 0},
503 {"align", s_align_ptwo, 0},
504 #ifdef M68KCOFF
505 {"sect", obj_coff_section, 0},
506 {"section", obj_coff_section, 0},
507 #endif
508 {0, 0, 0}
509 };
510
511 #define issbyte(x) ((x)>=-128 && (x)<=127)
512 #define isubyte(x) ((x)>=0 && (x)<=255)
513 #define issword(x) ((x)>=-32768 && (x)<=32767)
514 #define isuword(x) ((x)>=0 && (x)<=65535)
515
516 #define isbyte(x) ((x)>= -255 && (x)<=255)
517 #define isword(x) ((x)>=-65536 && (x)<=65535)
518 #define islong(x) (1)
519
520 extern char *input_line_pointer;
521
522 static char mklower_table[256];
523 #define mklower(c) (mklower_table[(unsigned char)(c)])
524 static char notend_table[256];
525 static char alt_notend_table[256];
526 #define notend(s) \
527 (! (notend_table[(unsigned char) *s] \
528 || (*s == ':' \
529 && alt_notend_table[(unsigned char) s[1]])))
530
531 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
532
533 #ifdef NO_PCREL_RELOCS
534
535 int
536 make_pcrel_absolute(fixP, add_number)
537 fixS *fixP;
538 long *add_number;
539 {
540 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
541
542 /* rewrite the PC relative instructions to absolute address ones.
543 * these are rumoured to be faster, and the apollo linker refuses
544 * to deal with the PC relative relocations.
545 */
546 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
547 {
548 opcode[0] = 0x4e;
549 opcode[1] = 0xf9;
550 }
551 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
552 {
553 opcode[0] = 0x4e;
554 opcode[1] = 0xb9;
555 }
556 else
557 as_fatal ("Unknown PC relative instruction");
558 *add_number -= 4;
559 return 0;
560 }
561
562 #endif /* NO_PCREL_RELOCS */
563
564 short
565 tc_coff_fix2rtype (fixP)
566 fixS *fixP;
567 {
568 if (fixP->fx_tcbit && fixP->fx_size == 4)
569 return R_RELLONG_NEG;
570 #ifdef NO_PCREL_RELOCS
571 know (fixP->fx_pcrel == 0);
572 return (fixP->fx_size == 1 ? R_RELBYTE
573 : fixP->fx_size == 2 ? R_DIR16
574 : R_DIR32);
575 #else
576 return (fixP->fx_pcrel ?
577 (fixP->fx_size == 1 ? R_PCRBYTE :
578 fixP->fx_size == 2 ? R_PCRWORD :
579 R_PCRLONG) :
580 (fixP->fx_size == 1 ? R_RELBYTE :
581 fixP->fx_size == 2 ? R_RELWORD :
582 R_RELLONG));
583 #endif
584 }
585
586 #endif
587
588 #ifdef BFD_ASSEMBLER
589
590 arelent *
591 tc_gen_reloc (section, fixp)
592 asection *section;
593 fixS *fixp;
594 {
595 arelent *reloc;
596 bfd_reloc_code_real_type code;
597
598 if (fixp->fx_tcbit)
599 abort ();
600
601 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
602 switch (F (fixp->fx_size, fixp->fx_pcrel))
603 {
604 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
605 MAP (1, 0, BFD_RELOC_8);
606 MAP (2, 0, BFD_RELOC_16);
607 MAP (4, 0, BFD_RELOC_32);
608 MAP (1, 1, BFD_RELOC_8_PCREL);
609 MAP (2, 1, BFD_RELOC_16_PCREL);
610 MAP (4, 1, BFD_RELOC_32_PCREL);
611 default:
612 abort ();
613 }
614
615 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
616 assert (reloc != 0);
617 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
618 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
619 if (fixp->fx_pcrel)
620 reloc->addend = fixp->fx_addnumber;
621 else
622 reloc->addend = 0;
623
624 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
625 assert (reloc->howto != 0);
626
627 return reloc;
628 }
629
630 #endif /* BFD_ASSEMBLER */
631
632 /* Handle of the OPCODE hash table. NULL means any use before
633 m68k_ip_begin() will crash. */
634 static struct hash_control *op_hash;
635 \f
636 /* Assemble an m68k instruction. */
637
638 void
639 m68k_ip (instring)
640 char *instring;
641 {
642 register char *p;
643 register struct m68k_op *opP;
644 register struct m68k_incant *opcode;
645 register const char *s;
646 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
647 char *pdot, *pdotmove;
648 enum m68k_size siz1, siz2;
649 char c;
650 int losing;
651 int opsfound;
652 char *crack_operand ();
653 LITTLENUM_TYPE words[6];
654 LITTLENUM_TYPE *wordp;
655 unsigned long ok_arch = 0;
656
657 if (*instring == ' ')
658 instring++; /* skip leading whitespace */
659
660 /* Scan up to end of operation-code, which MUST end in end-of-string
661 or exactly 1 space. */
662 pdot = 0;
663 for (p = instring; *p != '\0'; p++)
664 {
665 if (*p == ' ')
666 break;
667 if (*p == '.')
668 pdot = p;
669 }
670
671 if (p == instring)
672 {
673 the_ins.error = "No operator";
674 return;
675 }
676
677 /* p now points to the end of the opcode name, probably whitespace.
678 Make sure the name is null terminated by clobbering the
679 whitespace, look it up in the hash table, then fix it back.
680 Remove a dot, first, since the opcode tables have none. */
681 if (pdot != NULL)
682 {
683 for (pdotmove = pdot; pdotmove < p; pdotmove++)
684 *pdotmove = pdotmove[1];
685 p--;
686 }
687
688 c = *p;
689 *p = '\0';
690 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
691 *p = c;
692
693 if (pdot != NULL)
694 {
695 for (pdotmove = p; pdotmove > pdot; pdotmove--)
696 *pdotmove = pdotmove[-1];
697 *pdot = '.';
698 ++p;
699 }
700
701 if (opcode == NULL)
702 {
703 the_ins.error = "Unknown operator";
704 return;
705 }
706
707 /* found a legitimate opcode, start matching operands */
708 while (*p == ' ')
709 ++p;
710
711 if (opcode->m_operands == 0)
712 {
713 char *old = input_line_pointer;
714 *old = '\n';
715 input_line_pointer = p;
716 /* Ahh - it's a motorola style psuedo op */
717 mote_pseudo_table[opcode->m_opnum].poc_handler
718 (mote_pseudo_table[opcode->m_opnum].poc_val);
719 input_line_pointer = old;
720 *old = 0;
721
722 return;
723 }
724
725 if (flag_mri && opcode->m_opnum == 0)
726 {
727 /* In MRI mode, random garbage is allowed after an instruction
728 which accepts no operands. */
729 the_ins.args = opcode->m_operands;
730 the_ins.numargs = opcode->m_opnum;
731 the_ins.numo = opcode->m_codenum;
732 the_ins.opcode[0] = getone (opcode);
733 the_ins.opcode[1] = gettwo (opcode);
734 return;
735 }
736
737 for (opP = &the_ins.operands[0]; *p; opP++)
738 {
739 p = crack_operand (p, opP);
740
741 if (opP->error)
742 {
743 the_ins.error = opP->error;
744 return;
745 }
746 }
747
748 opsfound = opP - &the_ins.operands[0];
749
750 /* This ugly hack is to support the floating pt opcodes in their
751 standard form. Essentially, we fake a first enty of type COP#1 */
752 if (opcode->m_operands[0] == 'I')
753 {
754 int n;
755
756 for (n = opsfound; n > 0; --n)
757 the_ins.operands[n] = the_ins.operands[n - 1];
758
759 memset ((char *) (&the_ins.operands[0]), '\0',
760 sizeof (the_ins.operands[0]));
761 the_ins.operands[0].mode = CONTROL;
762 the_ins.operands[0].reg = m68k_float_copnum;
763 opsfound++;
764 }
765
766 /* We've got the operands. Find an opcode that'll accept them */
767 for (losing = 0;;)
768 {
769 /* If we didn't get the right number of ops, or we have no
770 common model with this pattern then reject this pattern. */
771
772 if (opsfound != opcode->m_opnum
773 || ((opcode->m_arch & current_architecture) == 0))
774 {
775 ++losing;
776 ok_arch |= opcode->m_arch;
777 }
778 else
779 {
780 for (s = opcode->m_operands, opP = &the_ins.operands[0];
781 *s && !losing;
782 s += 2, opP++)
783 {
784 /* Warning: this switch is huge! */
785 /* I've tried to organize the cases into this order:
786 non-alpha first, then alpha by letter. Lower-case
787 goes directly before uppercase counterpart. */
788 /* Code with multiple case ...: gets sorted by the lowest
789 case ... it belongs to. I hope this makes sense. */
790 switch (*s)
791 {
792 case '!':
793 switch (opP->mode)
794 {
795 case IMMED:
796 case DREG:
797 case AREG:
798 case FPREG:
799 case CONTROL:
800 case AINC:
801 case ADEC:
802 case REGLST:
803 losing++;
804 break;
805 default:
806 break;
807 }
808 break;
809
810 case '`':
811 switch (opP->mode)
812 {
813 case IMMED:
814 case DREG:
815 case AREG:
816 case FPREG:
817 case CONTROL:
818 case AINC:
819 case REGLST:
820 case AINDR:
821 losing++;
822 break;
823 default:
824 break;
825 }
826 break;
827
828 case '#':
829 if (opP->mode != IMMED)
830 losing++;
831 else if (s[1] == 'b'
832 && ! isvar (&opP->disp)
833 && (opP->disp.exp.X_op != O_constant
834 || ! isbyte (opP->disp.exp.X_add_number)))
835 losing++;
836 else if (s[1] == 'w'
837 && ! isvar (&opP->disp)
838 && (opP->disp.exp.X_op != O_constant
839 || ! isword (opP->disp.exp.X_add_number)))
840 losing++;
841 else if (s[1] == 'W'
842 && ! isvar (&opP->disp)
843 && (opP->disp.exp.X_op != O_constant
844 || ! issword (opP->disp.exp.X_add_number)))
845 losing++;
846 break;
847
848 case '^':
849 case 'T':
850 if (opP->mode != IMMED)
851 losing++;
852 break;
853
854 case '$':
855 if (opP->mode == AREG
856 || opP->mode == CONTROL
857 || opP->mode == FPREG
858 || opP->mode == IMMED
859 || opP->mode == REGLST
860 || (opP->mode != ABSL
861 && (opP->reg == PC
862 || opP->reg == ZPC)))
863 losing++;
864 break;
865
866 case '%':
867 if (opP->mode == CONTROL
868 || opP->mode == FPREG
869 || opP->mode == REGLST
870 || opP->mode == IMMED
871 || (opP->mode != ABSL
872 && (opP->reg == PC
873 || opP->reg == ZPC)))
874 losing++;
875 break;
876
877 case '&':
878 switch (opP->mode)
879 {
880 case DREG:
881 case AREG:
882 case FPREG:
883 case CONTROL:
884 case IMMED:
885 case AINC:
886 case ADEC:
887 case REGLST:
888 losing++;
889 break;
890 case ABSL:
891 break;
892 default:
893 if (opP->reg == PC
894 || opP->reg == ZPC)
895 losing++;
896 break;
897 }
898 break;
899
900 case '*':
901 if (opP->mode == CONTROL
902 || opP->mode == FPREG
903 || opP->mode == REGLST)
904 losing++;
905 break;
906
907 case '+':
908 if (opP->mode != AINC)
909 losing++;
910 break;
911
912 case '-':
913 if (opP->mode != ADEC)
914 losing++;
915 break;
916
917 case '/':
918 switch (opP->mode)
919 {
920 case AREG:
921 case CONTROL:
922 case FPREG:
923 case AINC:
924 case ADEC:
925 case IMMED:
926 case REGLST:
927 losing++;
928 break;
929 default:
930 break;
931 }
932 break;
933
934 case ';':
935 switch (opP->mode)
936 {
937 case AREG:
938 case CONTROL:
939 case FPREG:
940 case REGLST:
941 losing++;
942 break;
943 default:
944 break;
945 }
946 break;
947
948 case '?':
949 switch (opP->mode)
950 {
951 case AREG:
952 case CONTROL:
953 case FPREG:
954 case AINC:
955 case ADEC:
956 case IMMED:
957 case REGLST:
958 losing++;
959 break;
960 case ABSL:
961 break;
962 default:
963 if (opP->reg == PC || opP->reg == ZPC)
964 losing++;
965 break;
966 }
967 break;
968
969 case '@':
970 switch (opP->mode)
971 {
972 case AREG:
973 case CONTROL:
974 case FPREG:
975 case IMMED:
976 case REGLST:
977 losing++;
978 break;
979 default:
980 break;
981 }
982 break;
983
984 case '~': /* For now! (JF FOO is this right?) */
985 switch (opP->mode)
986 {
987 case DREG:
988 case AREG:
989 case CONTROL:
990 case FPREG:
991 case IMMED:
992 case REGLST:
993 losing++;
994 break;
995 case ABSL:
996 break;
997 default:
998 if (opP->reg == PC
999 || opP->reg == ZPC)
1000 losing++;
1001 break;
1002 }
1003 break;
1004
1005 case '3':
1006 if (opP->mode != CONTROL
1007 || (opP->reg != TT0 && opP->reg != TT1))
1008 losing++;
1009 break;
1010
1011 case 'A':
1012 if (opP->mode != AREG)
1013 losing++;
1014 break;
1015
1016 case 'a':
1017 if (opP->mode != AINDR)
1018 ++losing;
1019 break;
1020
1021 case 'B': /* FOO */
1022 if (opP->mode != ABSL
1023 || (flag_long_jumps
1024 && strncmp (instring, "jbsr", 4) == 0))
1025 losing++;
1026 break;
1027
1028 case 'C':
1029 if (opP->mode != CONTROL || opP->reg != CCR)
1030 losing++;
1031 break;
1032
1033 case 'd':
1034 if (opP->mode != DISP
1035 || opP->reg < ADDR0
1036 || opP->reg > ADDR7)
1037 losing++;
1038 break;
1039
1040 case 'D':
1041 if (opP->mode != DREG)
1042 losing++;
1043 break;
1044
1045 case 'F':
1046 if (opP->mode != FPREG)
1047 losing++;
1048 break;
1049
1050 case 'I':
1051 if (opP->mode != CONTROL
1052 || opP->reg < COP0
1053 || opP->reg > COP7)
1054 losing++;
1055 break;
1056
1057 case 'J':
1058 if (opP->mode != CONTROL
1059 || opP->reg < USP
1060 || opP->reg > last_movec_reg)
1061 losing++;
1062 else
1063 {
1064 const enum m68k_register *rp;
1065 for (rp = control_regs; *rp; rp++)
1066 if (*rp == opP->reg)
1067 break;
1068 if (*rp == 0)
1069 losing++;
1070 }
1071 break;
1072
1073 case 'k':
1074 if (opP->mode != IMMED)
1075 losing++;
1076 break;
1077
1078 case 'l':
1079 case 'L':
1080 if (opP->mode == DREG
1081 || opP->mode == AREG
1082 || opP->mode == FPREG)
1083 {
1084 if (s[1] == '8')
1085 losing++;
1086 else
1087 {
1088 switch (opP->mode)
1089 {
1090 case DREG:
1091 opP->mask = 1 << (opP->reg - DATA0);
1092 break;
1093 case AREG:
1094 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1095 break;
1096 case FPREG:
1097 opP->mask = 1 << (opP->reg - FP0 + 16);
1098 break;
1099 default:
1100 abort ();
1101 }
1102 opP->mode = REGLST;
1103 }
1104 }
1105 else if (opP->mode == CONTROL)
1106 {
1107 if (s[1] != '8')
1108 losing++;
1109 else
1110 {
1111 switch (opP->reg)
1112 {
1113 case FPI:
1114 opP->mask = 1 << 24;
1115 break;
1116 case FPS:
1117 opP->mask = 1 << 25;
1118 break;
1119 case FPC:
1120 opP->mask = 1 << 26;
1121 break;
1122 default:
1123 losing++;
1124 break;
1125 }
1126 opP->mode = REGLST;
1127 }
1128 }
1129 else if (opP->mode == ABSL
1130 && opP->disp.size == SIZE_UNSPEC
1131 && opP->disp.exp.X_op == O_constant)
1132 {
1133 /* This is what the MRI REG pseudo-op generates. */
1134 opP->mode = REGLST;
1135 opP->mask = opP->disp.exp.X_add_number;
1136 }
1137 else if (opP->mode != REGLST)
1138 losing++;
1139 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1140 losing++;
1141 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1142 losing++;
1143 break;
1144
1145 case 'M':
1146 if (opP->mode != IMMED)
1147 losing++;
1148 else if (opP->disp.exp.X_op != O_constant
1149 || ! issbyte (opP->disp.exp.X_add_number))
1150 losing++;
1151 else if (! m68k_quick
1152 && instring[3] != 'q'
1153 && instring[4] != 'q')
1154 losing++;
1155 break;
1156
1157 case 'O':
1158 if (opP->mode != DREG && opP->mode != IMMED)
1159 losing++;
1160 break;
1161
1162 case 'Q':
1163 if (opP->mode != IMMED)
1164 losing++;
1165 else if (opP->disp.exp.X_op != O_constant
1166 || opP->disp.exp.X_add_number < 1
1167 || opP->disp.exp.X_add_number > 8)
1168 losing++;
1169 else if (! m68k_quick
1170 && (strncmp (instring, "add", 3) == 0
1171 || strncmp (instring, "sub", 3) == 0)
1172 && instring[3] != 'q')
1173 losing++;
1174 break;
1175
1176 case 'R':
1177 if (opP->mode != DREG && opP->mode != AREG)
1178 losing++;
1179 break;
1180
1181 case 'r':
1182 if (opP->mode != AINDR
1183 && (opP->mode != BASE
1184 || (opP->reg != 0
1185 && opP->reg != ZADDR0)
1186 || opP->disp.exp.X_op != O_absent
1187 || ((opP->index.reg < DATA0
1188 || opP->index.reg > DATA7)
1189 && (opP->index.reg < ADDR0
1190 || opP->index.reg > ADDR7))
1191 || opP->index.size != SIZE_UNSPEC
1192 || opP->index.scale != 1))
1193 losing++;
1194 break;
1195
1196 case 's':
1197 if (opP->mode != CONTROL
1198 || ! (opP->reg == FPI
1199 || opP->reg == FPS
1200 || opP->reg == FPC))
1201 losing++;
1202 break;
1203
1204 case 'S':
1205 if (opP->mode != CONTROL || opP->reg != SR)
1206 losing++;
1207 break;
1208
1209 case 't':
1210 if (opP->mode != IMMED)
1211 losing++;
1212 else if (opP->disp.exp.X_op != O_constant
1213 || opP->disp.exp.X_add_number < 0
1214 || opP->disp.exp.X_add_number > 7)
1215 losing++;
1216 break;
1217
1218 case 'U':
1219 if (opP->mode != CONTROL || opP->reg != USP)
1220 losing++;
1221 break;
1222
1223 /* JF these are out of order. We could put them
1224 in order if we were willing to put up with
1225 bunches of #ifdef m68851s in the code.
1226
1227 Don't forget that you need these operands
1228 to use 68030 MMU instructions. */
1229 #ifndef NO_68851
1230 /* Memory addressing mode used by pflushr */
1231 case '|':
1232 if (opP->mode == CONTROL
1233 || opP->mode == FPREG
1234 || opP->mode == DREG
1235 || opP->mode == AREG
1236 || opP->mode == REGLST)
1237 losing++;
1238 /* We should accept immediate operands, but they
1239 supposedly have to be quad word, and we don't
1240 handle that. I would like to see what a Motorola
1241 assembler does before doing something here. */
1242 if (opP->mode == IMMED)
1243 losing++;
1244 break;
1245
1246 case 'f':
1247 if (opP->mode != CONTROL
1248 || (opP->reg != SFC && opP->reg != DFC))
1249 losing++;
1250 break;
1251
1252 case '0':
1253 if (opP->mode != CONTROL || opP->reg != TC)
1254 losing++;
1255 break;
1256
1257 case '1':
1258 if (opP->mode != CONTROL || opP->reg != AC)
1259 losing++;
1260 break;
1261
1262 case '2':
1263 if (opP->mode != CONTROL
1264 || (opP->reg != CAL
1265 && opP->reg != VAL
1266 && opP->reg != SCC))
1267 losing++;
1268 break;
1269
1270 case 'V':
1271 if (opP->mode != CONTROL
1272 || opP->reg != VAL)
1273 losing++;
1274 break;
1275
1276 case 'W':
1277 if (opP->mode != CONTROL
1278 || (opP->reg != DRP
1279 && opP->reg != SRP
1280 && opP->reg != CRP))
1281 losing++;
1282 break;
1283
1284 case 'X':
1285 if (opP->mode != CONTROL
1286 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1287 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1288 losing++;
1289 break;
1290
1291 case 'Y':
1292 if (opP->mode != CONTROL || opP->reg != PSR)
1293 losing++;
1294 break;
1295
1296 case 'Z':
1297 if (opP->mode != CONTROL || opP->reg != PCSR)
1298 losing++;
1299 break;
1300 #endif
1301 case 'c':
1302 if (opP->mode != CONTROL
1303 || (opP->reg != NC
1304 && opP->reg != IC
1305 && opP->reg != DC
1306 && opP->reg != BC))
1307 {
1308 losing++;
1309 } /* not a cache specifier. */
1310 break;
1311
1312 case '_':
1313 if (opP->mode != ABSL)
1314 ++losing;
1315 break;
1316
1317 default:
1318 abort ();
1319 } /* switch on type of operand */
1320
1321 if (losing)
1322 break;
1323 } /* for each operand */
1324 } /* if immediately wrong */
1325
1326 if (!losing)
1327 {
1328 break;
1329 } /* got it. */
1330
1331 opcode = opcode->m_next;
1332
1333 if (!opcode)
1334 {
1335 if (ok_arch
1336 && !(ok_arch & current_architecture))
1337 {
1338 char buf[200], *cp;
1339 int len;
1340 strcpy (buf,
1341 "invalid instruction for this architecture; needs ");
1342 cp = buf + strlen (buf);
1343 switch (ok_arch)
1344 {
1345 case mfloat:
1346 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1347 break;
1348 case mmmu:
1349 strcpy (cp, "mmu (68030 or 68851)");
1350 break;
1351 case m68020up:
1352 strcpy (cp, "68020 or higher");
1353 break;
1354 case m68000up:
1355 strcpy (cp, "68000 or higher");
1356 break;
1357 case m68010up:
1358 strcpy (cp, "68010 or higher");
1359 break;
1360 default:
1361 {
1362 int got_one = 0, idx;
1363 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1364 idx++)
1365 {
1366 if ((archs[idx].arch & ok_arch)
1367 && ! archs[idx].alias)
1368 {
1369 if (got_one)
1370 {
1371 strcpy (cp, " or ");
1372 cp += strlen (cp);
1373 }
1374 got_one = 1;
1375 strcpy (cp, archs[idx].name);
1376 cp += strlen (cp);
1377 }
1378 }
1379 }
1380 }
1381 len = cp - buf + 1;
1382 cp = malloc (len);
1383 strcpy (cp, buf);
1384 the_ins.error = cp;
1385 }
1386 else
1387 the_ins.error = "operands mismatch";
1388 return;
1389 } /* Fell off the end */
1390
1391 losing = 0;
1392 }
1393
1394 /* now assemble it */
1395
1396 the_ins.args = opcode->m_operands;
1397 the_ins.numargs = opcode->m_opnum;
1398 the_ins.numo = opcode->m_codenum;
1399 the_ins.opcode[0] = getone (opcode);
1400 the_ins.opcode[1] = gettwo (opcode);
1401
1402 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1403 {
1404 /* This switch is a doozy.
1405 Watch the first step; its a big one! */
1406 switch (s[0])
1407 {
1408
1409 case '*':
1410 case '~':
1411 case '%':
1412 case ';':
1413 case '@':
1414 case '!':
1415 case '&':
1416 case '$':
1417 case '?':
1418 case '/':
1419 case '`':
1420 #ifndef NO_68851
1421 case '|':
1422 #endif
1423 switch (opP->mode)
1424 {
1425 case IMMED:
1426 tmpreg = 0x3c; /* 7.4 */
1427 if (strchr ("bwl", s[1]))
1428 nextword = get_num (&opP->disp, 80);
1429 else
1430 nextword = get_num (&opP->disp, 0);
1431 if (isvar (&opP->disp))
1432 add_fix (s[1], &opP->disp, 0, 0);
1433 switch (s[1])
1434 {
1435 case 'b':
1436 if (!isbyte (nextword))
1437 opP->error = "operand out of range";
1438 addword (nextword);
1439 baseo = 0;
1440 break;
1441 case 'w':
1442 if (!isword (nextword))
1443 opP->error = "operand out of range";
1444 addword (nextword);
1445 baseo = 0;
1446 break;
1447 case 'W':
1448 if (!issword (nextword))
1449 opP->error = "operand out of range";
1450 addword (nextword);
1451 baseo = 0;
1452 break;
1453 case 'l':
1454 addword (nextword >> 16);
1455 addword (nextword);
1456 baseo = 0;
1457 break;
1458
1459 case 'f':
1460 baseo = 2;
1461 outro = 8;
1462 break;
1463 case 'F':
1464 baseo = 4;
1465 outro = 11;
1466 break;
1467 case 'x':
1468 baseo = 6;
1469 outro = 15;
1470 break;
1471 case 'p':
1472 baseo = 6;
1473 outro = -1;
1474 break;
1475 default:
1476 abort ();
1477 }
1478 if (!baseo)
1479 break;
1480
1481 /* We gotta put out some float */
1482 if (op (&opP->disp) != O_big)
1483 {
1484 valueT val;
1485 int gencnt;
1486
1487 /* Can other cases happen here? */
1488 if (op (&opP->disp) != O_constant)
1489 abort ();
1490
1491 val = (valueT) offs (&opP->disp);
1492 gencnt = 0;
1493 do
1494 {
1495 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1496 val >>= LITTLENUM_NUMBER_OF_BITS;
1497 ++gencnt;
1498 }
1499 while (val != 0);
1500 offs (&opP->disp) = gencnt;
1501 }
1502 if (offs (&opP->disp) > 0)
1503 {
1504 if (offs (&opP->disp) > baseo)
1505 {
1506 as_warn ("Bignum too big for %c format; truncated",
1507 s[1]);
1508 offs (&opP->disp) = baseo;
1509 }
1510 baseo -= offs (&opP->disp);
1511 while (baseo--)
1512 addword (0);
1513 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1514 offs (&opP->disp)--;
1515 --wordp)
1516 addword (*wordp);
1517 break;
1518 }
1519 gen_to_words (words, baseo, (long) outro);
1520 for (wordp = words; baseo--; wordp++)
1521 addword (*wordp);
1522 break;
1523 case DREG:
1524 tmpreg = opP->reg - DATA; /* 0.dreg */
1525 break;
1526 case AREG:
1527 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1528 break;
1529 case AINDR:
1530 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1531 break;
1532 case ADEC:
1533 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1534 break;
1535 case AINC:
1536 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1537 break;
1538 case DISP:
1539
1540 nextword = get_num (&opP->disp, 80);
1541
1542 if (opP->reg == PC
1543 && ! isvar (&opP->disp)
1544 && m68k_abspcadd)
1545 {
1546 opP->disp.exp.X_op = O_symbol;
1547 #ifndef BFD_ASSEMBLER
1548 opP->disp.exp.X_add_symbol = &abs_symbol;
1549 #else
1550 opP->disp.exp.X_add_symbol =
1551 section_symbol (absolute_section);
1552 #endif
1553 }
1554
1555 /* Force into index mode. Hope this works */
1556
1557 /* We do the first bit for 32-bit displacements, and the
1558 second bit for 16 bit ones. It is possible that we
1559 should make the default be WORD instead of LONG, but
1560 I think that'd break GCC, so we put up with a little
1561 inefficiency for the sake of working output. */
1562
1563 if (!issword (nextword)
1564 || (isvar (&opP->disp)
1565 && ((opP->disp.size == SIZE_UNSPEC
1566 && flag_short_refs == 0
1567 && cpu_of_arch (current_architecture) >= m68020)
1568 || opP->disp.size == SIZE_LONG)))
1569 {
1570 if (opP->reg == PC)
1571 tmpreg = 0x3B; /* 7.3 */
1572 else
1573 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1574 if (isvar (&opP->disp))
1575 {
1576 if (opP->reg == PC)
1577 {
1578 #if 0
1579 addword (0x0170);
1580 add_fix ('l', &opP->disp, 1, 2);
1581 addword (0), addword (0);
1582 #else
1583 add_frag (adds (&opP->disp),
1584 offs (&opP->disp),
1585 TAB (PCLEA, SZ_UNDEF));
1586 #endif
1587 break;
1588 }
1589 else
1590 {
1591 addword (0x0170);
1592 add_fix ('l', &opP->disp, 0, 0);
1593 }
1594 }
1595 else
1596 addword (0x0170);
1597 addword (nextword >> 16);
1598 }
1599 else
1600 {
1601 if (opP->reg == PC)
1602 tmpreg = 0x3A; /* 7.2 */
1603 else
1604 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1605
1606 if (isvar (&opP->disp))
1607 {
1608 if (opP->reg == PC)
1609 {
1610 add_fix ('w', &opP->disp, 1, 0);
1611 }
1612 else
1613 add_fix ('w', &opP->disp, 0, 0);
1614 }
1615 }
1616 addword (nextword);
1617 break;
1618
1619 case POST:
1620 case PRE:
1621 case BASE:
1622 nextword = 0;
1623 baseo = get_num (&opP->disp, 80);
1624 if (opP->mode == POST || opP->mode == PRE)
1625 outro = get_num (&opP->odisp, 80);
1626 /* Figure out the `addressing mode'.
1627 Also turn on the BASE_DISABLE bit, if needed. */
1628 if (opP->reg == PC || opP->reg == ZPC)
1629 {
1630 tmpreg = 0x3b; /* 7.3 */
1631 if (opP->reg == ZPC)
1632 nextword |= 0x80;
1633 }
1634 else if (opP->reg == 0)
1635 {
1636 nextword |= 0x80;
1637 tmpreg = 0x30; /* 6.garbage */
1638 }
1639 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1640 {
1641 nextword |= 0x80;
1642 tmpreg = 0x30 + opP->reg - ZADDR0;
1643 }
1644 else
1645 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1646
1647 siz1 = opP->disp.size;
1648 if (opP->mode == POST || opP->mode == PRE)
1649 siz2 = opP->odisp.size;
1650 else
1651 siz2 = SIZE_UNSPEC;
1652
1653 /* Index register stuff */
1654 if (opP->index.reg != 0
1655 && opP->index.reg >= DATA
1656 && opP->index.reg <= ADDR7)
1657 {
1658 nextword |= (opP->index.reg - DATA) << 12;
1659
1660 if (opP->index.size == SIZE_UNSPEC
1661 || opP->index.size == SIZE_LONG)
1662 nextword |= 0x800;
1663
1664 if (cpu_of_arch (current_architecture) < m68020)
1665 {
1666 if (opP->index.scale != 1)
1667 {
1668 opP->error =
1669 "scale factor invalid on this architecture; needs 68020 or higher";
1670 }
1671 }
1672
1673 switch (opP->index.scale)
1674 {
1675 case 1:
1676 break;
1677 case 2:
1678 nextword |= 0x200;
1679 break;
1680 case 4:
1681 nextword |= 0x400;
1682 break;
1683 case 8:
1684 nextword |= 0x600;
1685 break;
1686 default:
1687 abort ();
1688 }
1689 /* IF its simple,
1690 GET US OUT OF HERE! */
1691
1692 /* Must be INDEX, with an index register. Address
1693 register cannot be ZERO-PC, and either :b was
1694 forced, or we know it will fit. For a 68000 or
1695 68010, force this mode anyways, because the
1696 larger modes aren't supported. */
1697 if (opP->mode == BASE
1698 && ((opP->reg >= ADDR0
1699 && opP->reg <= ADDR7)
1700 || opP->reg == PC))
1701 {
1702 if (siz1 == SIZE_BYTE
1703 || cpu_of_arch (current_architecture) < m68020
1704 || (siz1 == SIZE_UNSPEC
1705 && ! isvar (&opP->disp)
1706 && issbyte (baseo)))
1707 {
1708 nextword += baseo & 0xff;
1709 addword (nextword);
1710 if (isvar (&opP->disp))
1711 {
1712 /* Do a byte relocation. If it doesn't
1713 fit (possible on m68000) let the
1714 fixup processing complain later. */
1715 if (opP->reg == PC)
1716 add_fix ('B', &opP->disp, 1, 1);
1717 else
1718 add_fix ('B', &opP->disp, 0, 0);
1719 }
1720 else if (siz1 != SIZE_BYTE)
1721 {
1722 if (siz1 != SIZE_UNSPEC)
1723 as_warn ("Forcing byte displacement");
1724 if (! issbyte (baseo))
1725 opP->error = "byte displacement out of range";
1726 }
1727
1728 break;
1729 }
1730 else if (siz1 == SIZE_UNSPEC
1731 && opP->reg == PC
1732 && isvar (&opP->disp)
1733 && subs (&opP->disp) == NULL)
1734 {
1735 nextword += baseo & 0xff;
1736 addword (nextword);
1737 add_frag (adds (&opP->disp), offs (&opP->disp),
1738 TAB (PCINDEX, SZ_UNDEF));
1739
1740 break;
1741 }
1742 }
1743 }
1744 else
1745 {
1746 nextword |= 0x40; /* No index reg */
1747 if (opP->index.reg >= ZDATA0
1748 && opP->index.reg <= ZDATA7)
1749 nextword |= (opP->index.reg - ZDATA0) << 12;
1750 else if (opP->index.reg >= ZADDR0
1751 || opP->index.reg <= ZADDR7)
1752 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1753 }
1754
1755 /* It isn't simple. */
1756
1757 if (cpu_of_arch (current_architecture) < m68020)
1758 opP->error =
1759 "invalid operand mode for this architecture; needs 68020 or higher";
1760
1761 nextword |= 0x100;
1762 /* If the guy specified a width, we assume that it is
1763 wide enough. Maybe it isn't. If so, we lose. */
1764 switch (siz1)
1765 {
1766 case SIZE_UNSPEC:
1767 if (isvar (&opP->disp)
1768 ? m68k_rel32
1769 : ! issword (baseo))
1770 {
1771 siz1 = SIZE_LONG;
1772 nextword |= 0x30;
1773 }
1774 else if (! isvar (&opP->disp) && baseo == 0)
1775 nextword |= 0x10;
1776 else
1777 {
1778 nextword |= 0x20;
1779 siz1 = SIZE_WORD;
1780 }
1781 break;
1782 case SIZE_BYTE:
1783 as_warn (":b not permitted; defaulting to :w");
1784 /* Fall through. */
1785 case SIZE_WORD:
1786 nextword |= 0x20;
1787 break;
1788 case SIZE_LONG:
1789 nextword |= 0x30;
1790 break;
1791 }
1792
1793 /* Figure out innner displacement stuff */
1794 if (opP->mode == POST || opP->mode == PRE)
1795 {
1796 switch (siz2)
1797 {
1798 case SIZE_UNSPEC:
1799 if (isvar (&opP->odisp)
1800 ? m68k_rel32
1801 : ! issword (outro))
1802 {
1803 siz2 = SIZE_LONG;
1804 nextword |= 0x3;
1805 }
1806 else if (! isvar (&opP->odisp) && outro == 0)
1807 nextword |= 0x1;
1808 else
1809 {
1810 nextword |= 0x2;
1811 siz2 = SIZE_WORD;
1812 }
1813 break;
1814 case 1:
1815 as_warn (":b not permitted; defaulting to :w");
1816 /* Fall through. */
1817 case 2:
1818 nextword |= 0x2;
1819 break;
1820 case 3:
1821 nextword |= 0x3;
1822 break;
1823 }
1824 if (opP->mode == POST
1825 && (nextword & 0x40) == 0)
1826 nextword |= 0x04;
1827 }
1828 addword (nextword);
1829
1830 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1831 {
1832 if (opP->reg == PC || opP->reg == ZPC)
1833 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1834 else
1835 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1836 }
1837 if (siz1 == SIZE_LONG)
1838 addword (baseo >> 16);
1839 if (siz1 != SIZE_UNSPEC)
1840 addword (baseo);
1841
1842 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1843 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1844 if (siz2 == SIZE_LONG)
1845 addword (outro >> 16);
1846 if (siz2 != SIZE_UNSPEC)
1847 addword (outro);
1848
1849 break;
1850
1851 case ABSL:
1852 nextword = get_num (&opP->disp, 80);
1853 switch (opP->disp.size)
1854 {
1855 default:
1856 abort ();
1857 case SIZE_UNSPEC:
1858 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1859 {
1860 tmpreg = 0x38; /* 7.0 */
1861 addword (nextword);
1862 break;
1863 }
1864 /* Don't generate pc relative code on 68010 and
1865 68000. */
1866 if (isvar (&opP->disp)
1867 && !subs (&opP->disp)
1868 && adds (&opP->disp)
1869 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
1870 && cpu_of_arch (current_architecture) >= m68020
1871 && !flag_long_jumps
1872 && !strchr ("~%&$?", s[0]))
1873 {
1874 tmpreg = 0x3A; /* 7.2 */
1875 add_frag (adds (&opP->disp),
1876 offs (&opP->disp),
1877 TAB (PCREL, SZ_UNDEF));
1878 break;
1879 }
1880 /* Fall through into long */
1881 case SIZE_LONG:
1882 if (isvar (&opP->disp))
1883 add_fix ('l', &opP->disp, 0, 0);
1884
1885 tmpreg = 0x39;/* 7.1 mode */
1886 addword (nextword >> 16);
1887 addword (nextword);
1888 break;
1889
1890 case SIZE_WORD: /* Word */
1891 if (isvar (&opP->disp))
1892 add_fix ('w', &opP->disp, 0, 0);
1893
1894 tmpreg = 0x38;/* 7.0 mode */
1895 addword (nextword);
1896 break;
1897 }
1898 break;
1899 case CONTROL:
1900 case FPREG:
1901 default:
1902 as_bad ("unknown/incorrect operand");
1903 /* abort(); */
1904 }
1905 install_gen_operand (s[1], tmpreg);
1906 break;
1907
1908 case '#':
1909 case '^':
1910 switch (s[1])
1911 { /* JF: I hate floating point! */
1912 case 'j':
1913 tmpreg = 70;
1914 break;
1915 case '8':
1916 tmpreg = 20;
1917 break;
1918 case 'C':
1919 tmpreg = 50;
1920 break;
1921 case '3':
1922 default:
1923 tmpreg = 80;
1924 break;
1925 }
1926 tmpreg = get_num (&opP->disp, tmpreg);
1927 if (isvar (&opP->disp))
1928 add_fix (s[1], &opP->disp, 0, 0);
1929 switch (s[1])
1930 {
1931 case 'b': /* Danger: These do no check for
1932 certain types of overflow.
1933 user beware! */
1934 if (!isbyte (tmpreg))
1935 opP->error = "out of range";
1936 insop (tmpreg, opcode);
1937 if (isvar (&opP->disp))
1938 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1939 break;
1940 case 'w':
1941 if (!isword (tmpreg))
1942 opP->error = "out of range";
1943 insop (tmpreg, opcode);
1944 if (isvar (&opP->disp))
1945 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1946 break;
1947 case 'W':
1948 if (!issword (tmpreg))
1949 opP->error = "out of range";
1950 insop (tmpreg, opcode);
1951 if (isvar (&opP->disp))
1952 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1953 break;
1954 case 'l':
1955 /* Because of the way insop works, we put these two out
1956 backwards. */
1957 insop (tmpreg, opcode);
1958 insop (tmpreg >> 16, opcode);
1959 if (isvar (&opP->disp))
1960 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1961 break;
1962 case '3':
1963 tmpreg &= 0xFF;
1964 case '8':
1965 case 'C':
1966 install_operand (s[1], tmpreg);
1967 break;
1968 default:
1969 abort ();
1970 }
1971 break;
1972
1973 case '+':
1974 case '-':
1975 case 'A':
1976 case 'a':
1977 install_operand (s[1], opP->reg - ADDR);
1978 break;
1979
1980 case 'B':
1981 tmpreg = get_num (&opP->disp, 80);
1982 switch (s[1])
1983 {
1984 case 'B':
1985 /* The pc_fix argument winds up in fx_pcrel_adjust,
1986 which is a char, and may therefore be unsigned. We
1987 want to pass -1, but we pass 64 instead, and convert
1988 back in md_pcrel_from. */
1989 add_fix ('B', &opP->disp, 1, 64);
1990 break;
1991 case 'W':
1992 add_fix ('w', &opP->disp, 1, 0);
1993 addword (0);
1994 break;
1995 case 'L':
1996 long_branch:
1997 if (cpu_of_arch (current_architecture) < m68020)
1998 as_warn ("Can't use long branches on 68000/68010");
1999 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2000 add_fix ('l', &opP->disp, 1, 0);
2001 addword (0);
2002 addword (0);
2003 break;
2004 case 'g':
2005 if (subs (&opP->disp)) /* We can't relax it */
2006 goto long_branch;
2007
2008 /* This could either be a symbol, or an absolute
2009 address. No matter, the frag hacking will finger it
2010 out. Not quite: it can't switch from BRANCH to
2011 BCC68000 for the case where opnd is absolute (it
2012 needs to use the 68000 hack since no conditional abs
2013 jumps). */
2014 if (((cpu_of_arch (current_architecture) < m68020)
2015 || (0 == adds (&opP->disp)))
2016 && (the_ins.opcode[0] >= 0x6200)
2017 && (the_ins.opcode[0] <= 0x6f00))
2018 add_frag (adds (&opP->disp), offs (&opP->disp),
2019 TAB (BCC68000, SZ_UNDEF));
2020 else
2021 add_frag (adds (&opP->disp), offs (&opP->disp),
2022 TAB (ABRANCH, SZ_UNDEF));
2023 break;
2024 case 'w':
2025 if (isvar (&opP->disp))
2026 {
2027 #if 1
2028 /* check for DBcc instruction */
2029 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2030 {
2031 /* size varies if patch */
2032 /* needed for long form */
2033 add_frag (adds (&opP->disp), offs (&opP->disp),
2034 TAB (DBCC, SZ_UNDEF));
2035 break;
2036 }
2037 #endif
2038 add_fix ('w', &opP->disp, 1, 0);
2039 }
2040 addword (0);
2041 break;
2042 case 'C': /* Fixed size LONG coproc branches */
2043 add_fix ('l', &opP->disp, 1, 0);
2044 addword (0);
2045 addword (0);
2046 break;
2047 case 'c': /* Var size Coprocesssor branches */
2048 if (subs (&opP->disp))
2049 {
2050 add_fix ('l', &opP->disp, 1, 0);
2051 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2052 }
2053 else if (adds (&opP->disp))
2054 add_frag (adds (&opP->disp), offs (&opP->disp),
2055 TAB (FBRANCH, SZ_UNDEF));
2056 else
2057 {
2058 /* add_frag((symbolS *) 0, offs(&opP->disp),
2059 TAB(FBRANCH,SHORT)); */
2060 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2061 add_fix ('l', &opP->disp, 1, 0);
2062 addword (0);
2063 addword (0);
2064 }
2065 break;
2066 default:
2067 abort ();
2068 }
2069 break;
2070
2071 case 'C': /* Ignore it */
2072 break;
2073
2074 case 'd': /* JF this is a kludge */
2075 install_operand ('s', opP->reg - ADDR);
2076 tmpreg = get_num (&opP->disp, 80);
2077 if (!issword (tmpreg))
2078 {
2079 as_warn ("Expression out of range, using 0");
2080 tmpreg = 0;
2081 }
2082 addword (tmpreg);
2083 break;
2084
2085 case 'D':
2086 install_operand (s[1], opP->reg - DATA);
2087 break;
2088
2089 case 'F':
2090 install_operand (s[1], opP->reg - FP0);
2091 break;
2092
2093 case 'I':
2094 tmpreg = opP->reg - COP0;
2095 install_operand (s[1], tmpreg);
2096 break;
2097
2098 case 'J': /* JF foo */
2099 switch (opP->reg)
2100 {
2101 case SFC:
2102 tmpreg = 0x000;
2103 break;
2104 case DFC:
2105 tmpreg = 0x001;
2106 break;
2107 case CACR:
2108 tmpreg = 0x002;
2109 break;
2110 case TC:
2111 tmpreg = 0x003;
2112 break;
2113 case ITT0:
2114 tmpreg = 0x004;
2115 break;
2116 case ITT1:
2117 tmpreg = 0x005;
2118 break;
2119 case DTT0:
2120 tmpreg = 0x006;
2121 break;
2122 case DTT1:
2123 tmpreg = 0x007;
2124 break;
2125 case BUSCR:
2126 tmpreg = 0x008;
2127 break;
2128
2129 case USP:
2130 tmpreg = 0x800;
2131 break;
2132 case VBR:
2133 tmpreg = 0x801;
2134 break;
2135 case CAAR:
2136 tmpreg = 0x802;
2137 break;
2138 case MSP:
2139 tmpreg = 0x803;
2140 break;
2141 case ISP:
2142 tmpreg = 0x804;
2143 break;
2144 case MMUSR:
2145 tmpreg = 0x805;
2146 break;
2147 case URP:
2148 tmpreg = 0x806;
2149 break;
2150 case SRP:
2151 tmpreg = 0x807;
2152 break;
2153 case PCR:
2154 tmpreg = 0x808;
2155 break;
2156 default:
2157 abort ();
2158 }
2159 install_operand (s[1], tmpreg);
2160 break;
2161
2162 case 'k':
2163 tmpreg = get_num (&opP->disp, 55);
2164 install_operand (s[1], tmpreg & 0x7f);
2165 break;
2166
2167 case 'l':
2168 tmpreg = opP->mask;
2169 if (s[1] == 'w')
2170 {
2171 if (tmpreg & 0x7FF0000)
2172 as_bad ("Floating point register in register list");
2173 insop (reverse_16_bits (tmpreg), opcode);
2174 }
2175 else
2176 {
2177 if (tmpreg & 0x700FFFF)
2178 as_bad ("Wrong register in floating-point reglist");
2179 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2180 }
2181 break;
2182
2183 case 'L':
2184 tmpreg = opP->mask;
2185 if (s[1] == 'w')
2186 {
2187 if (tmpreg & 0x7FF0000)
2188 as_bad ("Floating point register in register list");
2189 insop (tmpreg, opcode);
2190 }
2191 else if (s[1] == '8')
2192 {
2193 if (tmpreg & 0x0FFFFFF)
2194 as_bad ("incorrect register in reglist");
2195 install_operand (s[1], tmpreg >> 24);
2196 }
2197 else
2198 {
2199 if (tmpreg & 0x700FFFF)
2200 as_bad ("wrong register in floating-point reglist");
2201 else
2202 install_operand (s[1], tmpreg >> 16);
2203 }
2204 break;
2205
2206 case 'M':
2207 install_operand (s[1], get_num (&opP->disp, 60));
2208 break;
2209
2210 case 'O':
2211 tmpreg = ((opP->mode == DREG)
2212 ? 0x20 + opP->reg - DATA
2213 : (get_num (&opP->disp, 40) & 0x1F));
2214 install_operand (s[1], tmpreg);
2215 break;
2216
2217 case 'Q':
2218 tmpreg = get_num (&opP->disp, 10);
2219 if (tmpreg == 8)
2220 tmpreg = 0;
2221 install_operand (s[1], tmpreg);
2222 break;
2223
2224 case 'R':
2225 /* This depends on the fact that ADDR registers are eight
2226 more than their corresponding DATA regs, so the result
2227 will have the ADDR_REG bit set */
2228 install_operand (s[1], opP->reg - DATA);
2229 break;
2230
2231 case 'r':
2232 if (opP->mode == AINDR)
2233 install_operand (s[1], opP->reg - DATA);
2234 else
2235 install_operand (s[1], opP->index.reg - DATA);
2236 break;
2237
2238 case 's':
2239 if (opP->reg == FPI)
2240 tmpreg = 0x1;
2241 else if (opP->reg == FPS)
2242 tmpreg = 0x2;
2243 else if (opP->reg == FPC)
2244 tmpreg = 0x4;
2245 else
2246 abort ();
2247 install_operand (s[1], tmpreg);
2248 break;
2249
2250 case 'S': /* Ignore it */
2251 break;
2252
2253 case 'T':
2254 install_operand (s[1], get_num (&opP->disp, 30));
2255 break;
2256
2257 case 'U': /* Ignore it */
2258 break;
2259
2260 case 'c':
2261 switch (opP->reg)
2262 {
2263 case NC:
2264 tmpreg = 0;
2265 break;
2266 case DC:
2267 tmpreg = 1;
2268 break;
2269 case IC:
2270 tmpreg = 2;
2271 break;
2272 case BC:
2273 tmpreg = 3;
2274 break;
2275 default:
2276 as_fatal ("failed sanity check");
2277 } /* switch on cache token */
2278 install_operand (s[1], tmpreg);
2279 break;
2280 #ifndef NO_68851
2281 /* JF: These are out of order, I fear. */
2282 case 'f':
2283 switch (opP->reg)
2284 {
2285 case SFC:
2286 tmpreg = 0;
2287 break;
2288 case DFC:
2289 tmpreg = 1;
2290 break;
2291 default:
2292 abort ();
2293 }
2294 install_operand (s[1], tmpreg);
2295 break;
2296
2297 case '0':
2298 case '1':
2299 case '2':
2300 switch (opP->reg)
2301 {
2302 case TC:
2303 tmpreg = 0;
2304 break;
2305 case CAL:
2306 tmpreg = 4;
2307 break;
2308 case VAL:
2309 tmpreg = 5;
2310 break;
2311 case SCC:
2312 tmpreg = 6;
2313 break;
2314 case AC:
2315 tmpreg = 7;
2316 break;
2317 default:
2318 abort ();
2319 }
2320 install_operand (s[1], tmpreg);
2321 break;
2322
2323 case 'V':
2324 if (opP->reg == VAL)
2325 break;
2326 abort ();
2327
2328 case 'W':
2329 switch (opP->reg)
2330 {
2331 case DRP:
2332 tmpreg = 1;
2333 break;
2334 case SRP:
2335 tmpreg = 2;
2336 break;
2337 case CRP:
2338 tmpreg = 3;
2339 break;
2340 default:
2341 abort ();
2342 }
2343 install_operand (s[1], tmpreg);
2344 break;
2345
2346 case 'X':
2347 switch (opP->reg)
2348 {
2349 case BAD:
2350 case BAD + 1:
2351 case BAD + 2:
2352 case BAD + 3:
2353 case BAD + 4:
2354 case BAD + 5:
2355 case BAD + 6:
2356 case BAD + 7:
2357 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2358 break;
2359
2360 case BAC:
2361 case BAC + 1:
2362 case BAC + 2:
2363 case BAC + 3:
2364 case BAC + 4:
2365 case BAC + 5:
2366 case BAC + 6:
2367 case BAC + 7:
2368 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2369 break;
2370
2371 default:
2372 abort ();
2373 }
2374 install_operand (s[1], tmpreg);
2375 break;
2376 case 'Y':
2377 know (opP->reg == PSR);
2378 break;
2379 case 'Z':
2380 know (opP->reg == PCSR);
2381 break;
2382 #endif /* m68851 */
2383 case '3':
2384 switch (opP->reg)
2385 {
2386 case TT0:
2387 tmpreg = 2;
2388 break;
2389 case TT1:
2390 tmpreg = 3;
2391 break;
2392 default:
2393 abort ();
2394 }
2395 install_operand (s[1], tmpreg);
2396 break;
2397 case 't':
2398 tmpreg = get_num (&opP->disp, 20);
2399 install_operand (s[1], tmpreg);
2400 break;
2401 case '_': /* used only for move16 absolute 32-bit address */
2402 tmpreg = get_num (&opP->disp, 80);
2403 addword (tmpreg >> 16);
2404 addword (tmpreg & 0xFFFF);
2405 break;
2406 default:
2407 abort ();
2408 }
2409 }
2410
2411 /* By the time whe get here (FINALLY) the_ins contains the complete
2412 instruction, ready to be emitted. . . */
2413 }
2414
2415 static int
2416 reverse_16_bits (in)
2417 int in;
2418 {
2419 int out = 0;
2420 int n;
2421
2422 static int mask[16] =
2423 {
2424 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2425 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2426 };
2427 for (n = 0; n < 16; n++)
2428 {
2429 if (in & mask[n])
2430 out |= mask[15 - n];
2431 }
2432 return out;
2433 } /* reverse_16_bits() */
2434
2435 static int
2436 reverse_8_bits (in)
2437 int in;
2438 {
2439 int out = 0;
2440 int n;
2441
2442 static int mask[8] =
2443 {
2444 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2445 };
2446
2447 for (n = 0; n < 8; n++)
2448 {
2449 if (in & mask[n])
2450 out |= mask[7 - n];
2451 }
2452 return out;
2453 } /* reverse_8_bits() */
2454
2455 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2456 (that value is chosen in the frag_var call in md_assemble). TYPE
2457 is the subtype of the frag to be generated; its primary type is
2458 rs_machine_dependent.
2459
2460 The TYPE parameter is also used by md_convert_frag_1 and
2461 md_estimate_size_before_relax. The appropriate type of fixup will
2462 be emitted by md_convert_frag_1.
2463
2464 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2465 static void
2466 install_operand (mode, val)
2467 int mode;
2468 int val;
2469 {
2470 switch (mode)
2471 {
2472 case 's':
2473 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2474 break;
2475 case 'd':
2476 the_ins.opcode[0] |= val << 9;
2477 break;
2478 case '1':
2479 the_ins.opcode[1] |= val << 12;
2480 break;
2481 case '2':
2482 the_ins.opcode[1] |= val << 6;
2483 break;
2484 case '3':
2485 the_ins.opcode[1] |= val;
2486 break;
2487 case '4':
2488 the_ins.opcode[2] |= val << 12;
2489 break;
2490 case '5':
2491 the_ins.opcode[2] |= val << 6;
2492 break;
2493 case '6':
2494 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2495 three words long! */
2496 the_ins.numo++;
2497 the_ins.opcode[2] |= val;
2498 break;
2499 case '7':
2500 the_ins.opcode[1] |= val << 7;
2501 break;
2502 case '8':
2503 the_ins.opcode[1] |= val << 10;
2504 break;
2505 #ifndef NO_68851
2506 case '9':
2507 the_ins.opcode[1] |= val << 5;
2508 break;
2509 #endif
2510
2511 case 't':
2512 the_ins.opcode[1] |= (val << 10) | (val << 7);
2513 break;
2514 case 'D':
2515 the_ins.opcode[1] |= (val << 12) | val;
2516 break;
2517 case 'g':
2518 the_ins.opcode[0] |= val = 0xff;
2519 break;
2520 case 'i':
2521 the_ins.opcode[0] |= val << 9;
2522 break;
2523 case 'C':
2524 the_ins.opcode[1] |= val;
2525 break;
2526 case 'j':
2527 the_ins.opcode[1] |= val;
2528 the_ins.numo++; /* What a hack */
2529 break;
2530 case 'k':
2531 the_ins.opcode[1] |= val << 4;
2532 break;
2533 case 'b':
2534 case 'w':
2535 case 'W':
2536 case 'l':
2537 break;
2538 case 'e':
2539 the_ins.opcode[0] |= (val << 6);
2540 break;
2541 case 'L':
2542 the_ins.opcode[1] = (val >> 16);
2543 the_ins.opcode[2] = val & 0xffff;
2544 break;
2545 case 'c':
2546 default:
2547 as_fatal ("failed sanity check.");
2548 }
2549 } /* install_operand() */
2550
2551 static void
2552 install_gen_operand (mode, val)
2553 int mode;
2554 int val;
2555 {
2556 switch (mode)
2557 {
2558 case 's':
2559 the_ins.opcode[0] |= val;
2560 break;
2561 case 'd':
2562 /* This is a kludge!!! */
2563 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2564 break;
2565 case 'b':
2566 case 'w':
2567 case 'l':
2568 case 'f':
2569 case 'F':
2570 case 'x':
2571 case 'p':
2572 the_ins.opcode[0] |= val;
2573 break;
2574 /* more stuff goes here */
2575 default:
2576 as_fatal ("failed sanity check.");
2577 }
2578 } /* install_gen_operand() */
2579
2580 /*
2581 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2582 * then deal with the bitfield hack.
2583 */
2584
2585 static char *
2586 crack_operand (str, opP)
2587 register char *str;
2588 register struct m68k_op *opP;
2589 {
2590 register int parens;
2591 register int c;
2592 register char *beg_str;
2593 int inquote = 0;
2594
2595 if (!str)
2596 {
2597 return str;
2598 }
2599 beg_str = str;
2600 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2601 {
2602 if (! inquote)
2603 {
2604 if (*str == '(')
2605 parens++;
2606 else if (*str == ')')
2607 {
2608 if (!parens)
2609 { /* ERROR */
2610 opP->error = "Extra )";
2611 return str;
2612 }
2613 --parens;
2614 }
2615 }
2616 if (flag_mri && *str == '\'')
2617 inquote = ! inquote;
2618 }
2619 if (!*str && parens)
2620 { /* ERROR */
2621 opP->error = "Missing )";
2622 return str;
2623 }
2624 c = *str;
2625 *str = '\0';
2626 if (m68k_ip_op (beg_str, opP) != 0)
2627 {
2628 *str = c;
2629 return str;
2630 }
2631 *str = c;
2632 if (c == '}')
2633 c = *++str; /* JF bitfield hack */
2634 if (c)
2635 {
2636 c = *++str;
2637 if (!c)
2638 as_bad ("Missing operand");
2639 }
2640 return str;
2641 }
2642
2643 /* This is the guts of the machine-dependent assembler. STR points to a
2644 machine dependent instruction. This function is supposed to emit
2645 the frags/bytes it assembles to.
2646 */
2647
2648 void
2649 insert_reg (regname, regnum)
2650 char *regname;
2651 int regnum;
2652 {
2653 char buf[100];
2654 int i;
2655
2656 #ifdef REGISTER_PREFIX
2657 if (!flag_reg_prefix_optional)
2658 {
2659 buf[0] = REGISTER_PREFIX;
2660 strcpy (buf + 1, regname);
2661 regname = buf;
2662 }
2663 #endif
2664
2665 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2666 &zero_address_frag));
2667
2668 for (i = 0; regname[i]; i++)
2669 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2670 buf[i] = '\0';
2671
2672 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2673 &zero_address_frag));
2674 }
2675
2676 struct init_entry
2677 {
2678 const char *name;
2679 int number;
2680 };
2681
2682 static const struct init_entry init_table[] =
2683 {
2684 { "d0", DATA0 },
2685 { "d1", DATA1 },
2686 { "d2", DATA2 },
2687 { "d3", DATA3 },
2688 { "d4", DATA4 },
2689 { "d5", DATA5 },
2690 { "d6", DATA6 },
2691 { "d7", DATA7 },
2692 { "a0", ADDR0 },
2693 { "a1", ADDR1 },
2694 { "a2", ADDR2 },
2695 { "a3", ADDR3 },
2696 { "a4", ADDR4 },
2697 { "a5", ADDR5 },
2698 { "a6", ADDR6 },
2699 { "fp", ADDR6 },
2700 { "a7", ADDR7 },
2701 { "sp", ADDR7 },
2702 { "ssp", ADDR7 },
2703 { "fp0", FP0 },
2704 { "fp1", FP1 },
2705 { "fp2", FP2 },
2706 { "fp3", FP3 },
2707 { "fp4", FP4 },
2708 { "fp5", FP5 },
2709 { "fp6", FP6 },
2710 { "fp7", FP7 },
2711 { "fpi", FPI },
2712 { "fpiar", FPI },
2713 { "fpc", FPI },
2714 { "fps", FPS },
2715 { "fpsr", FPS },
2716 { "fpc", FPC },
2717 { "fpcr", FPC },
2718 { "control", FPC },
2719 { "status", FPS },
2720 { "iaddr", FPI },
2721
2722 { "cop0", COP0 },
2723 { "cop1", COP1 },
2724 { "cop2", COP2 },
2725 { "cop3", COP3 },
2726 { "cop4", COP4 },
2727 { "cop5", COP5 },
2728 { "cop6", COP6 },
2729 { "cop7", COP7 },
2730 { "pc", PC },
2731 { "zpc", ZPC },
2732 { "sr", SR },
2733
2734 { "ccr", CCR },
2735 { "cc", CCR },
2736
2737 { "usp", USP },
2738 { "isp", ISP },
2739 { "sfc", SFC },
2740 { "sfcr", SFC },
2741 { "dfc", DFC },
2742 { "dfcr", DFC },
2743 { "cacr", CACR },
2744 { "caar", CAAR },
2745
2746 { "vbr", VBR },
2747
2748 { "msp", MSP },
2749 { "itt0", ITT0 },
2750 { "itt1", ITT1 },
2751 { "dtt0", DTT0 },
2752 { "dtt1", DTT1 },
2753 { "mmusr", MMUSR },
2754 { "tc", TC },
2755 { "srp", SRP },
2756 { "urp", URP },
2757 { "buscr", BUSCR },
2758 { "pcr", PCR },
2759
2760 { "ac", AC },
2761 { "bc", BC },
2762 { "cal", CAL },
2763 { "crp", CRP },
2764 { "drp", DRP },
2765 { "pcsr", PCSR },
2766 { "psr", PSR },
2767 { "scc", SCC },
2768 { "val", VAL },
2769 { "bad0", BAD0 },
2770 { "bad1", BAD1 },
2771 { "bad2", BAD2 },
2772 { "bad3", BAD3 },
2773 { "bad4", BAD4 },
2774 { "bad5", BAD5 },
2775 { "bad6", BAD6 },
2776 { "bad7", BAD7 },
2777 { "bac0", BAC0 },
2778 { "bac1", BAC1 },
2779 { "bac2", BAC2 },
2780 { "bac3", BAC3 },
2781 { "bac4", BAC4 },
2782 { "bac5", BAC5 },
2783 { "bac6", BAC6 },
2784 { "bac7", BAC7 },
2785
2786 { "ic", IC },
2787 { "dc", DC },
2788 { "nc", NC },
2789
2790 { "tt0", TT0 },
2791 { "tt1", TT1 },
2792 /* 68ec030 versions of same */
2793 { "ac0", TT0 },
2794 { "ac1", TT1 },
2795 /* 68ec030 access control unit, identical to 030 MMU status reg */
2796 { "acusr", PSR },
2797
2798 /* Suppressed data and address registers. */
2799 { "zd0", ZDATA0 },
2800 { "zd1", ZDATA1 },
2801 { "zd2", ZDATA2 },
2802 { "zd3", ZDATA3 },
2803 { "zd4", ZDATA4 },
2804 { "zd5", ZDATA5 },
2805 { "zd6", ZDATA6 },
2806 { "zd7", ZDATA7 },
2807 { "za0", ZADDR0 },
2808 { "za1", ZADDR1 },
2809 { "za2", ZADDR2 },
2810 { "za3", ZADDR3 },
2811 { "za4", ZADDR4 },
2812 { "za5", ZADDR5 },
2813 { "za6", ZADDR6 },
2814 { "za7", ZADDR7 },
2815
2816 { 0, 0 }
2817 };
2818
2819 void
2820 init_regtable ()
2821 {
2822 int i;
2823 for (i = 0; init_table[i].name; i++)
2824 insert_reg (init_table[i].name, init_table[i].number);
2825 }
2826
2827 static int no_68851, no_68881;
2828
2829 #ifdef OBJ_AOUT
2830 /* a.out machine type. Default to 68020. */
2831 int m68k_aout_machtype = 2;
2832 #endif
2833
2834 void
2835 md_assemble (str)
2836 char *str;
2837 {
2838 const char *er;
2839 short *fromP;
2840 char *toP = NULL;
2841 int m, n = 0;
2842 char *to_beg_P;
2843 int shorts_this_frag;
2844 fixS *fixP;
2845
2846 /* In MRI mode, the instruction and operands are separated by a
2847 space. Anything following the operands is a comment. The label
2848 has already been removed. */
2849 if (flag_mri)
2850 {
2851 char *s;
2852 int fields = 0;
2853 int infield = 0;
2854 int inquote = 0;
2855
2856 for (s = str; *s != '\0'; s++)
2857 {
2858 if ((*s == ' ' || *s == '\t') && ! inquote)
2859 {
2860 if (infield)
2861 {
2862 ++fields;
2863 if (fields >= 2)
2864 {
2865 *s = '\0';
2866 break;
2867 }
2868 infield = 0;
2869 }
2870 }
2871 else
2872 {
2873 if (! infield)
2874 infield = 1;
2875 if (*s == '\'')
2876 inquote = ! inquote;
2877 }
2878 }
2879 }
2880
2881 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2882 m68k_ip (str);
2883 er = the_ins.error;
2884 if (!er)
2885 {
2886 for (n = 0; n < the_ins.numargs; n++)
2887 if (the_ins.operands[n].error)
2888 {
2889 er = the_ins.operands[n].error;
2890 break;
2891 }
2892 }
2893 if (er)
2894 {
2895 as_bad ("%s -- statement `%s' ignored", er, str);
2896 return;
2897 }
2898
2899 if (the_ins.nfrag == 0)
2900 {
2901 /* No frag hacking involved; just put it out */
2902 toP = frag_more (2 * the_ins.numo);
2903 fromP = &the_ins.opcode[0];
2904 for (m = the_ins.numo; m; --m)
2905 {
2906 md_number_to_chars (toP, (long) (*fromP), 2);
2907 toP += 2;
2908 fromP++;
2909 }
2910 /* put out symbol-dependent info */
2911 for (m = 0; m < the_ins.nrel; m++)
2912 {
2913 switch (the_ins.reloc[m].wid)
2914 {
2915 case 'B':
2916 n = 1;
2917 break;
2918 case 'b':
2919 n = 1;
2920 break;
2921 case '3':
2922 n = 2;
2923 break;
2924 case 'w':
2925 n = 2;
2926 break;
2927 case 'l':
2928 n = 4;
2929 break;
2930 default:
2931 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2932 the_ins.reloc[m].wid);
2933 }
2934
2935 fixP = fix_new_exp (frag_now,
2936 ((toP - frag_now->fr_literal)
2937 - the_ins.numo * 2 + the_ins.reloc[m].n),
2938 n,
2939 &the_ins.reloc[m].exp,
2940 the_ins.reloc[m].pcrel,
2941 NO_RELOC);
2942 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2943 }
2944 return;
2945 }
2946
2947 /* There's some frag hacking */
2948 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2949 {
2950 int wid;
2951
2952 if (n == 0)
2953 wid = 2 * the_ins.fragb[n].fragoff;
2954 else
2955 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2956 toP = frag_more (wid);
2957 to_beg_P = toP;
2958 shorts_this_frag = 0;
2959 for (m = wid / 2; m; --m)
2960 {
2961 md_number_to_chars (toP, (long) (*fromP), 2);
2962 toP += 2;
2963 fromP++;
2964 shorts_this_frag++;
2965 }
2966 for (m = 0; m < the_ins.nrel; m++)
2967 {
2968 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2969 {
2970 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2971 break;
2972 }
2973 wid = the_ins.reloc[m].wid;
2974 if (wid == 0)
2975 continue;
2976 the_ins.reloc[m].wid = 0;
2977 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2978
2979 fixP = fix_new_exp (frag_now,
2980 ((toP - frag_now->fr_literal)
2981 - the_ins.numo * 2 + the_ins.reloc[m].n),
2982 wid,
2983 &the_ins.reloc[m].exp,
2984 the_ins.reloc[m].pcrel,
2985 NO_RELOC);
2986 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2987 }
2988 (void) frag_var (rs_machine_dependent, 10, 0,
2989 (relax_substateT) (the_ins.fragb[n].fragty),
2990 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2991 }
2992 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2993 shorts_this_frag = 0;
2994 if (n)
2995 {
2996 toP = frag_more (n * sizeof (short));
2997 while (n--)
2998 {
2999 md_number_to_chars (toP, (long) (*fromP), 2);
3000 toP += 2;
3001 fromP++;
3002 shorts_this_frag++;
3003 }
3004 }
3005 for (m = 0; m < the_ins.nrel; m++)
3006 {
3007 int wid;
3008
3009 wid = the_ins.reloc[m].wid;
3010 if (wid == 0)
3011 continue;
3012 the_ins.reloc[m].wid = 0;
3013 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3014
3015 fixP = fix_new_exp (frag_now,
3016 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3017 - shorts_this_frag * 2),
3018 wid,
3019 &the_ins.reloc[m].exp,
3020 the_ins.reloc[m].pcrel,
3021 NO_RELOC);
3022 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3023 }
3024 }
3025
3026 void
3027 md_begin ()
3028 {
3029 /*
3030 * md_begin -- set up hash tables with 68000 instructions.
3031 * similar to what the vax assembler does. ---phr
3032 */
3033 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3034 a copy of it at runtime, adding in the information we want but isn't
3035 there. I think it'd be better to have an awk script hack the table
3036 at compile time. Or even just xstr the table and use it as-is. But
3037 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3038 names. */
3039
3040 register const struct m68k_opcode *ins;
3041 register struct m68k_incant *hack, *slak;
3042 register const char *retval = 0; /* empty string, or error msg text */
3043 register unsigned int i;
3044 register char c;
3045
3046 if (flag_mri)
3047 {
3048 flag_reg_prefix_optional = 1;
3049 m68k_abspcadd = 1;
3050 m68k_rel32 = 0;
3051 }
3052
3053 op_hash = hash_new ();
3054
3055 obstack_begin (&robyn, 4000);
3056 for (i = 0; i < m68k_numopcodes; i++)
3057 {
3058 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3059 do
3060 {
3061 ins = &m68k_opcodes[i];
3062 /* We *could* ignore insns that don't match our arch here
3063 but just leaving them out of the hash. */
3064 slak->m_operands = ins->args;
3065 slak->m_opnum = strlen (slak->m_operands) / 2;
3066 slak->m_arch = ins->arch;
3067 slak->m_opcode = ins->opcode;
3068 /* This is kludgey */
3069 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3070 if (i + 1 != m68k_numopcodes
3071 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3072 {
3073 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3074 i++;
3075 }
3076 else
3077 slak->m_next = 0;
3078 slak = slak->m_next;
3079 }
3080 while (slak);
3081
3082 retval = hash_insert (op_hash, ins->name, (char *) hack);
3083 if (retval)
3084 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3085 }
3086
3087 for (i = 0; i < m68k_numaliases; i++)
3088 {
3089 const char *name = m68k_opcode_aliases[i].primary;
3090 const char *alias = m68k_opcode_aliases[i].alias;
3091 PTR val = hash_find (op_hash, name);
3092 if (!val)
3093 as_fatal ("Internal Error: Can't find %s in hash table", name);
3094 retval = hash_insert (op_hash, alias, val);
3095 if (retval)
3096 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3097 }
3098
3099 /* In MRI mode, all unsized branches are variable sized. Normally,
3100 they are word sized. */
3101 if (flag_mri)
3102 {
3103 static struct m68k_opcode_alias mri_aliases[] =
3104 {
3105 { "bhi", "jhi", },
3106 { "bls", "jls", },
3107 { "bcc", "jcc", },
3108 { "bcs", "jcs", },
3109 { "bne", "jne", },
3110 { "beq", "jeq", },
3111 { "bvc", "jvc", },
3112 { "bvs", "jvs", },
3113 { "bpl", "jpl", },
3114 { "bmi", "jmi", },
3115 { "bge", "jge", },
3116 { "blt", "jlt", },
3117 { "bgt", "jgt", },
3118 { "ble", "jle", },
3119 { "bra", "jra", },
3120 { "bsr", "jbsr", },
3121 };
3122
3123 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3124 {
3125 const char *name = mri_aliases[i].primary;
3126 const char *alias = mri_aliases[i].alias;
3127 PTR val = hash_find (op_hash, name);
3128 if (!val)
3129 as_fatal ("Internal Error: Can't find %s in hash table", name);
3130 retval = hash_jam (op_hash, alias, val);
3131 if (retval)
3132 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3133 }
3134 }
3135
3136 for (i = 0; i < sizeof (mklower_table); i++)
3137 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3138
3139 for (i = 0; i < sizeof (notend_table); i++)
3140 {
3141 notend_table[i] = 0;
3142 alt_notend_table[i] = 0;
3143 }
3144 notend_table[','] = 1;
3145 notend_table['{'] = 1;
3146 notend_table['}'] = 1;
3147 alt_notend_table['a'] = 1;
3148 alt_notend_table['A'] = 1;
3149 alt_notend_table['d'] = 1;
3150 alt_notend_table['D'] = 1;
3151 alt_notend_table['#'] = 1;
3152 alt_notend_table['&'] = 1;
3153 alt_notend_table['f'] = 1;
3154 alt_notend_table['F'] = 1;
3155 #ifdef REGISTER_PREFIX
3156 alt_notend_table[REGISTER_PREFIX] = 1;
3157 #endif
3158
3159 /* We need to put '(' in alt_notend_table to handle
3160 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3161 */
3162 alt_notend_table['('] = 1;
3163
3164 /* We need to put '@' in alt_notend_table to handle
3165 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3166 */
3167 alt_notend_table['@'] = 1;
3168
3169 #ifndef MIT_SYNTAX_ONLY
3170 /* Insert pseudo ops, these have to go into the opcode table since
3171 gas expects pseudo ops to start with a dot */
3172 {
3173 int n = 0;
3174 while (mote_pseudo_table[n].poc_name)
3175 {
3176 hack = (struct m68k_incant *)
3177 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3178 hash_insert (op_hash,
3179 mote_pseudo_table[n].poc_name, (char *) hack);
3180 hack->m_operands = 0;
3181 hack->m_opnum = n;
3182 n++;
3183 }
3184 }
3185 #endif
3186
3187 init_regtable ();
3188 }
3189
3190 void
3191 m68k_init_after_args ()
3192 {
3193 if (cpu_of_arch (current_architecture) == 0)
3194 {
3195 int i;
3196 const char *default_cpu = TARGET_CPU;
3197
3198 if (*default_cpu == 'm')
3199 default_cpu++;
3200 for (i = 0; i < n_archs; i++)
3201 if (strcasecmp (default_cpu, archs[i].name) == 0)
3202 break;
3203 if (i == n_archs)
3204 {
3205 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3206 current_architecture |= m68020;
3207 }
3208 else
3209 current_architecture |= archs[i].arch;
3210 }
3211 /* Permit m68881 specification with all cpus; those that can't work
3212 with a coprocessor could be doing emulation. */
3213 if (current_architecture & m68851)
3214 {
3215 if (current_architecture & m68040)
3216 {
3217 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3218 }
3219 }
3220 /* What other incompatibilities could we check for? */
3221
3222 /* Toss in some default assumptions about coprocessors. */
3223 if (!no_68881
3224 && (cpu_of_arch (current_architecture)
3225 /* Can CPU32 have a 68881 coprocessor?? */
3226 & (m68020 | m68030 | cpu32)))
3227 {
3228 current_architecture |= m68881;
3229 }
3230 if (!no_68851
3231 && (cpu_of_arch (current_architecture) & m68020up) != 0
3232 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3233 {
3234 current_architecture |= m68851;
3235 }
3236 if (no_68881 && (current_architecture & m68881))
3237 as_bad ("options for 68881 and no-68881 both given");
3238 if (no_68851 && (current_architecture & m68851))
3239 as_bad ("options for 68851 and no-68851 both given");
3240
3241 #ifdef OBJ_AOUT
3242 /* Work out the magic number. This isn't very general. */
3243 if (current_architecture & m68000)
3244 m68k_aout_machtype = 0;
3245 else if (current_architecture & m68010)
3246 m68k_aout_machtype = 1;
3247 else if (current_architecture & m68020)
3248 m68k_aout_machtype = 2;
3249 else
3250 m68k_aout_machtype = 2;
3251 #endif
3252
3253 /* Note which set of "movec" control registers is available. */
3254 switch (cpu_of_arch (current_architecture))
3255 {
3256 case m68000:
3257 control_regs = m68000_control_regs;
3258 break;
3259 case m68010:
3260 control_regs = m68010_control_regs;
3261 break;
3262 case m68020:
3263 case m68030:
3264 control_regs = m68020_control_regs;
3265 break;
3266 case m68040:
3267 control_regs = m68040_control_regs;
3268 break;
3269 case m68060:
3270 control_regs = m68060_control_regs;
3271 break;
3272 case cpu32:
3273 control_regs = cpu32_control_regs;
3274 break;
3275 default:
3276 abort ();
3277 }
3278
3279 if (cpu_of_arch (current_architecture) < m68020)
3280 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3281 }
3282
3283 /* Equal to MAX_PRECISION in atof-ieee.c */
3284 #define MAX_LITTLENUMS 6
3285
3286 /* Turn a string in input_line_pointer into a floating point constant
3287 of type type, and store the appropriate bytes in *litP. The number
3288 of LITTLENUMS emitted is stored in *sizeP . An error message is
3289 returned, or NULL on OK. */
3290
3291 char *
3292 md_atof (type, litP, sizeP)
3293 char type;
3294 char *litP;
3295 int *sizeP;
3296 {
3297 int prec;
3298 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3299 LITTLENUM_TYPE *wordP;
3300 char *t;
3301 char *atof_ieee ();
3302
3303 switch (type)
3304 {
3305 case 'f':
3306 case 'F':
3307 case 's':
3308 case 'S':
3309 prec = 2;
3310 break;
3311
3312 case 'd':
3313 case 'D':
3314 case 'r':
3315 case 'R':
3316 prec = 4;
3317 break;
3318
3319 case 'x':
3320 case 'X':
3321 prec = 6;
3322 break;
3323
3324 case 'p':
3325 case 'P':
3326 prec = 6;
3327 break;
3328
3329 default:
3330 *sizeP = 0;
3331 return "Bad call to MD_ATOF()";
3332 }
3333 t = atof_ieee (input_line_pointer, type, words);
3334 if (t)
3335 input_line_pointer = t;
3336
3337 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3338 for (wordP = words; prec--;)
3339 {
3340 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3341 litP += sizeof (LITTLENUM_TYPE);
3342 }
3343 return 0;
3344 }
3345
3346 void
3347 md_number_to_chars (buf, val, n)
3348 char *buf;
3349 valueT val;
3350 int n;
3351 {
3352 number_to_chars_bigendian (buf, val, n);
3353 }
3354
3355 static void
3356 md_apply_fix_2 (fixP, val)
3357 fixS *fixP;
3358 offsetT val;
3359 {
3360 addressT upper_limit;
3361 offsetT lower_limit;
3362
3363 /* This is unnecessary but it convinces the native rs6000 compiler
3364 to generate the code we want. */
3365 char *buf = fixP->fx_frag->fr_literal;
3366 buf += fixP->fx_where;
3367 /* end ibm compiler workaround */
3368
3369 if (val & 0x80000000)
3370 val |= ~(addressT)0x7fffffff;
3371 else
3372 val &= 0x7fffffff;
3373
3374 switch (fixP->fx_size)
3375 {
3376 /* The cast to offsetT below are necessary to make code correct for
3377 machines where ints are smaller than offsetT */
3378 case 1:
3379 *buf++ = val;
3380 upper_limit = 0x7f;
3381 lower_limit = - (offsetT) 0x80;
3382 break;
3383 case 2:
3384 *buf++ = (val >> 8);
3385 *buf++ = val;
3386 upper_limit = 0x7fff;
3387 lower_limit = - (offsetT) 0x8000;
3388 break;
3389 case 4:
3390 *buf++ = (val >> 24);
3391 *buf++ = (val >> 16);
3392 *buf++ = (val >> 8);
3393 *buf++ = val;
3394 upper_limit = 0x7fffffff;
3395 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3396 break;
3397 default:
3398 BAD_CASE (fixP->fx_size);
3399 }
3400
3401 /* Fix up a negative reloc. */
3402 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3403 {
3404 fixP->fx_addsy = fixP->fx_subsy;
3405 fixP->fx_subsy = NULL;
3406 fixP->fx_tcbit = 1;
3407 }
3408
3409 /* For non-pc-relative values, it's conceivable we might get something
3410 like "0xff" for a byte field. So extend the upper part of the range
3411 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3412 so that we can do any range checking at all. */
3413 if (!fixP->fx_pcrel)
3414 upper_limit = upper_limit * 2 + 1;
3415
3416 if ((addressT) val > upper_limit
3417 && (val > 0 || val < lower_limit))
3418 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3419
3420 /* A one byte PC-relative reloc means a short branch. We can't use
3421 a short branch with a value of 0 or -1, because those indicate
3422 different opcodes (branches with longer offsets). */
3423 if (fixP->fx_pcrel
3424 && fixP->fx_size == 1
3425 && (fixP->fx_addsy == NULL
3426 || S_IS_DEFINED (fixP->fx_addsy))
3427 && (val == 0 || val == -1))
3428 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3429 }
3430
3431 #ifdef BFD_ASSEMBLER
3432 int
3433 md_apply_fix (fixP, valp)
3434 fixS *fixP;
3435 valueT *valp;
3436 {
3437 md_apply_fix_2 (fixP, (addressT) *valp);
3438 return 1;
3439 }
3440 #else
3441 void md_apply_fix (fixP, val)
3442 fixS *fixP;
3443 long val;
3444 {
3445 md_apply_fix_2 (fixP, (addressT) val);
3446 }
3447 #endif
3448
3449 /* *fragP has been relaxed to its final size, and now needs to have
3450 the bytes inside it modified to conform to the new size There is UGLY
3451 MAGIC here. ..
3452 */
3453 void
3454 md_convert_frag_1 (fragP)
3455 register fragS *fragP;
3456 {
3457 long disp;
3458 long ext = 0;
3459 fixS *fixP;
3460
3461 /* Address in object code of the displacement. */
3462 register int object_address = fragP->fr_fix + fragP->fr_address;
3463
3464 /* Address in gas core of the place to store the displacement. */
3465 /* This convinces the native rs6000 compiler to generate the code we
3466 want. */
3467 register char *buffer_address = fragP->fr_literal;
3468 buffer_address += fragP->fr_fix;
3469 /* end ibm compiler workaround */
3470
3471 /* The displacement of the address, from current location. */
3472 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3473 disp = (disp + fragP->fr_offset) - object_address;
3474
3475 #ifdef BFD_ASSEMBLER
3476 disp += fragP->fr_symbol->sy_frag->fr_address;
3477 #endif
3478
3479 switch (fragP->fr_subtype)
3480 {
3481 case TAB (BCC68000, BYTE):
3482 case TAB (ABRANCH, BYTE):
3483 know (issbyte (disp));
3484 if (disp == 0)
3485 as_bad ("short branch with zero offset: use :w");
3486 fragP->fr_opcode[1] = disp;
3487 ext = 0;
3488 break;
3489 case TAB (DBCC, SHORT):
3490 know (issword (disp));
3491 ext = 2;
3492 break;
3493 case TAB (BCC68000, SHORT):
3494 case TAB (ABRANCH, SHORT):
3495 know (issword (disp));
3496 fragP->fr_opcode[1] = 0x00;
3497 ext = 2;
3498 break;
3499 case TAB (ABRANCH, LONG):
3500 if (cpu_of_arch (current_architecture) < m68020)
3501 {
3502 if (fragP->fr_opcode[0] == 0x61)
3503 /* BSR */
3504 {
3505 fragP->fr_opcode[0] = 0x4E;
3506 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3507
3508 fix_new (fragP,
3509 fragP->fr_fix,
3510 4,
3511 fragP->fr_symbol,
3512 fragP->fr_offset,
3513 0,
3514 NO_RELOC);
3515
3516 fragP->fr_fix += 4;
3517 ext = 0;
3518 }
3519 /* BRA */
3520 else if (fragP->fr_opcode[0] == 0x60)
3521 {
3522 fragP->fr_opcode[0] = 0x4E;
3523 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3524 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3525 fragP->fr_offset, 0, NO_RELOC);
3526 fragP->fr_fix += 4;
3527 ext = 0;
3528 }
3529 else
3530 {
3531 as_bad ("Long branch offset not supported.");
3532 }
3533 }
3534 else
3535 {
3536 fragP->fr_opcode[1] = (char) 0xff;
3537 ext = 4;
3538 }
3539 break;
3540 case TAB (BCC68000, LONG):
3541 /* only Bcc 68000 instructions can come here */
3542 /* change bcc into b!cc/jmp absl long */
3543 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3544 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3545
3546 /* JF: these used to be fr_opcode[2,3], but they may be in a
3547 different frag, in which case refering to them is a no-no.
3548 Only fr_opcode[0,1] are guaranteed to work. */
3549 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3550 *buffer_address++ = (char) 0xf9;
3551 fragP->fr_fix += 2; /* account for jmp instruction */
3552 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3553 fragP->fr_offset, 0, NO_RELOC);
3554 fragP->fr_fix += 4;
3555 ext = 0;
3556 break;
3557 case TAB (DBCC, LONG):
3558 /* only DBcc 68000 instructions can come here */
3559 /* change dbcc into dbcc/jmp absl long */
3560 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3561 *buffer_address++ = 0x00; /* branch offset = 4 */
3562 *buffer_address++ = 0x04;
3563 *buffer_address++ = 0x60; /* put in bra pc+6 */
3564 *buffer_address++ = 0x06;
3565 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3566 *buffer_address++ = (char) 0xf9;
3567
3568 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3569 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3570 fragP->fr_offset, 0, NO_RELOC);
3571 fragP->fr_fix += 4;
3572 ext = 0;
3573 break;
3574 case TAB (FBRANCH, SHORT):
3575 know ((fragP->fr_opcode[1] & 0x40) == 0);
3576 ext = 2;
3577 break;
3578 case TAB (FBRANCH, LONG):
3579 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3580 ext = 4;
3581 break;
3582 case TAB (PCREL, SHORT):
3583 ext = 2;
3584 break;
3585 case TAB (PCREL, LONG):
3586 /* The thing to do here is force it to ABSOLUTE LONG, since
3587 PCREL is really trying to shorten an ABSOLUTE address anyway */
3588 /* JF FOO This code has not been tested */
3589 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3590 0, NO_RELOC);
3591 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3592 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3593 (unsigned) fragP->fr_opcode[0],
3594 (unsigned long) fragP->fr_address);
3595 fragP->fr_opcode[1] &= ~0x3F;
3596 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3597 fragP->fr_fix += 4;
3598 ext = 0;
3599 break;
3600 case TAB (PCLEA, SHORT):
3601 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3602 fragP->fr_offset, 1, NO_RELOC);
3603 fragP->fr_opcode[1] &= ~0x3F;
3604 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3605 ext = 2;
3606 break;
3607 case TAB (PCLEA, LONG):
3608 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3609 fragP->fr_offset, 1, NO_RELOC);
3610 fixP->fx_pcrel_adjust = 2;
3611 /* Already set to mode 7.3; this indicates: PC indirect with
3612 suppressed index, 32-bit displacement. */
3613 *buffer_address++ = 0x01;
3614 *buffer_address++ = 0x70;
3615 fragP->fr_fix += 2;
3616 ext = 4;
3617 break;
3618
3619 case TAB (PCINDEX, BYTE):
3620 disp += 2;
3621 if (!issbyte (disp))
3622 {
3623 as_bad ("displacement doesn't fit in one byte");
3624 disp = 0;
3625 }
3626 assert (fragP->fr_fix >= 2);
3627 buffer_address[-2] &= ~1;
3628 buffer_address[-1] = disp;
3629 ext = 0;
3630 break;
3631 case TAB (PCINDEX, SHORT):
3632 disp += 2;
3633 assert (issword (disp));
3634 assert (fragP->fr_fix >= 2);
3635 buffer_address[-2] |= 0x1;
3636 buffer_address[-1] = 0x20;
3637 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3638 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3639 NO_RELOC);
3640 fixP->fx_pcrel_adjust = 2;
3641 ext = 2;
3642 break;
3643 case TAB (PCINDEX, LONG):
3644 disp += 2;
3645 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3646 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3647 NO_RELOC);
3648 fixP->fx_pcrel_adjust = 2;
3649 assert (fragP->fr_fix >= 2);
3650 buffer_address[-2] |= 0x1;
3651 buffer_address[-1] = 0x30;
3652 ext = 4;
3653 break;
3654 }
3655
3656 if (ext)
3657 {
3658 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3659 fragP->fr_fix += ext;
3660 }
3661 }
3662
3663 #ifndef BFD_ASSEMBLER
3664
3665 void
3666 md_convert_frag (headers, sec, fragP)
3667 object_headers *headers;
3668 segT sec;
3669 fragS *fragP;
3670 {
3671 md_convert_frag_1 (fragP);
3672 }
3673
3674 #else
3675
3676 void
3677 md_convert_frag (abfd, sec, fragP)
3678 bfd *abfd;
3679 segT sec;
3680 fragS *fragP;
3681 {
3682 md_convert_frag_1 (fragP);
3683 }
3684 #endif
3685
3686 /* Force truly undefined symbols to their maximum size, and generally set up
3687 the frag list to be relaxed
3688 */
3689 int
3690 md_estimate_size_before_relax (fragP, segment)
3691 register fragS *fragP;
3692 segT segment;
3693 {
3694 int old_fix;
3695 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3696
3697 old_fix = fragP->fr_fix;
3698
3699 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3700 switch (fragP->fr_subtype)
3701 {
3702
3703 case TAB (ABRANCH, SZ_UNDEF):
3704 {
3705 if ((fragP->fr_symbol != NULL) /* Not absolute */
3706 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3707 {
3708 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3709 break;
3710 }
3711 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3712 {
3713 /* On 68000, or for absolute value, switch to abs long */
3714 /* FIXME, we should check abs val, pick short or long */
3715 if (fragP->fr_opcode[0] == 0x61)
3716 {
3717 fragP->fr_opcode[0] = 0x4E;
3718 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3719 fix_new (fragP, fragP->fr_fix, 4,
3720 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3721 fragP->fr_fix += 4;
3722 frag_wane (fragP);
3723 }
3724 else if (fragP->fr_opcode[0] == 0x60)
3725 {
3726 fragP->fr_opcode[0] = 0x4E;
3727 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3728 fix_new (fragP, fragP->fr_fix, 4,
3729 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3730 fragP->fr_fix += 4;
3731 frag_wane (fragP);
3732 }
3733 else
3734 {
3735 as_warn ("Long branch offset to extern symbol not supported.");
3736 }
3737 }
3738 else
3739 { /* Symbol is still undefined. Make it simple */
3740 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3741 fragP->fr_offset, 1, NO_RELOC);
3742 fragP->fr_fix += 4;
3743 fragP->fr_opcode[1] = (char) 0xff;
3744 frag_wane (fragP);
3745 break;
3746 }
3747
3748 break;
3749 } /* case TAB(ABRANCH,SZ_UNDEF) */
3750
3751 case TAB (FBRANCH, SZ_UNDEF):
3752 {
3753 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3754 {
3755 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3756 fragP->fr_var += 2;
3757 }
3758 else
3759 {
3760 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3761 fragP->fr_offset, 1, NO_RELOC);
3762 fragP->fr_fix += 4;
3763 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3764 frag_wane (fragP);
3765 }
3766 break;
3767 } /* TAB(FBRANCH,SZ_UNDEF) */
3768
3769 case TAB (PCREL, SZ_UNDEF):
3770 {
3771 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3772 || flag_short_refs
3773 || cpu_of_arch (current_architecture) < m68020)
3774 {
3775 fragP->fr_subtype = TAB (PCREL, SHORT);
3776 fragP->fr_var += 2;
3777 }
3778 else
3779 {
3780 fragP->fr_subtype = TAB (PCREL, LONG);
3781 fragP->fr_var += 4;
3782 }
3783 break;
3784 } /* TAB(PCREL,SZ_UNDEF) */
3785
3786 case TAB (BCC68000, SZ_UNDEF):
3787 {
3788 if ((fragP->fr_symbol != NULL)
3789 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3790 {
3791 fragP->fr_subtype = TAB (BCC68000, BYTE);
3792 break;
3793 }
3794 /* only Bcc 68000 instructions can come here */
3795 /* change bcc into b!cc/jmp absl long */
3796 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3797 if (flag_short_refs)
3798 {
3799 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3800 /* JF: these were fr_opcode[2,3] */
3801 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3802 buffer_address[1] = (char) 0xf8;
3803 fragP->fr_fix += 2; /* account for jmp instruction */
3804 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3805 fragP->fr_offset, 0, NO_RELOC);
3806 fragP->fr_fix += 2;
3807 }
3808 else
3809 {
3810 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3811 /* JF: these were fr_opcode[2,3] */
3812 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3813 buffer_address[1] = (char) 0xf9;
3814 fragP->fr_fix += 2; /* account for jmp instruction */
3815 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3816 fragP->fr_offset, 0, NO_RELOC);
3817 fragP->fr_fix += 4;
3818 }
3819 frag_wane (fragP);
3820 break;
3821 } /* case TAB(BCC68000,SZ_UNDEF) */
3822
3823 case TAB (DBCC, SZ_UNDEF):
3824 {
3825 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3826 {
3827 fragP->fr_subtype = TAB (DBCC, SHORT);
3828 fragP->fr_var += 2;
3829 break;
3830 }
3831 /* only DBcc 68000 instructions can come here */
3832 /* change dbcc into dbcc/jmp absl long */
3833 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3834 buffer_address[0] = 0x00; /* branch offset = 4 */
3835 buffer_address[1] = 0x04;
3836 buffer_address[2] = 0x60; /* put in bra pc + ... */
3837
3838 if (flag_short_refs)
3839 {
3840 /* JF: these were fr_opcode[5-7] */
3841 buffer_address[3] = 0x04; /* plus 4 */
3842 buffer_address[4] = 0x4e; /* Put in Jump Word */
3843 buffer_address[5] = (char) 0xf8;
3844 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3845 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3846 fragP->fr_offset, 0, NO_RELOC);
3847 fragP->fr_fix += 2;
3848 }
3849 else
3850 {
3851 /* JF: these were fr_opcode[5-7] */
3852 buffer_address[3] = 0x06; /* Plus 6 */
3853 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3854 buffer_address[5] = (char) 0xf9;
3855 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3856 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3857 fragP->fr_offset, 0, NO_RELOC);
3858 fragP->fr_fix += 4;
3859 }
3860
3861 frag_wane (fragP);
3862 break;
3863 } /* case TAB(DBCC,SZ_UNDEF) */
3864
3865 case TAB (PCLEA, SZ_UNDEF):
3866 {
3867 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3868 || flag_short_refs
3869 || cpu_of_arch (current_architecture) < m68020)
3870 {
3871 fragP->fr_subtype = TAB (PCLEA, SHORT);
3872 fragP->fr_var += 2;
3873 }
3874 else
3875 {
3876 fragP->fr_subtype = TAB (PCLEA, LONG);
3877 fragP->fr_var += 6;
3878 }
3879 break;
3880 } /* TAB(PCLEA,SZ_UNDEF) */
3881
3882 case TAB (PCINDEX, SZ_UNDEF):
3883 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3884 || cpu_of_arch (current_architecture) < m68020)
3885 {
3886 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3887 }
3888 else
3889 {
3890 fragP->fr_subtype = TAB (PCINDEX, LONG);
3891 fragP->fr_var += 4;
3892 }
3893 break;
3894
3895 default:
3896 break;
3897 }
3898
3899 /* now that SZ_UNDEF are taken care of, check others */
3900 switch (fragP->fr_subtype)
3901 {
3902 case TAB (BCC68000, BYTE):
3903 case TAB (ABRANCH, BYTE):
3904 /* We can't do a short jump to the next instruction,
3905 so we force word mode. */
3906 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3907 fragP->fr_symbol->sy_frag == fragP->fr_next)
3908 {
3909 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3910 fragP->fr_var += 2;
3911 }
3912 break;
3913 default:
3914 break;
3915 }
3916 return fragP->fr_var + fragP->fr_fix - old_fix;
3917 }
3918
3919 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3920 /* the bit-field entries in the relocation_info struct plays hell
3921 with the byte-order problems of cross-assembly. So as a hack,
3922 I added this mach. dependent ri twiddler. Ugly, but it gets
3923 you there. -KWK */
3924 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3925 are symbolnum, most sig. byte first. Last byte is broken up with
3926 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3927 nibble as nuthin. (on Sun 3 at least) */
3928 /* Translate the internal relocation information into target-specific
3929 format. */
3930 #ifdef comment
3931 void
3932 md_ri_to_chars (the_bytes, ri)
3933 char *the_bytes;
3934 struct reloc_info_generic *ri;
3935 {
3936 /* this is easy */
3937 md_number_to_chars (the_bytes, ri->r_address, 4);
3938 /* now the fun stuff */
3939 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3940 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3941 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3942 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3943 ((ri->r_extern << 4) & 0x10));
3944 }
3945
3946 #endif /* comment */
3947
3948 #ifndef BFD_ASSEMBLER
3949 void
3950 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3951 char *where;
3952 fixS *fixP;
3953 relax_addressT segment_address_in_file;
3954 {
3955 /*
3956 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3957 * Out: GNU LD relocation length code: 0, 1, or 2.
3958 */
3959
3960 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3961 long r_symbolnum;
3962
3963 know (fixP->fx_addsy != NULL);
3964
3965 md_number_to_chars (where,
3966 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3967 4);
3968
3969 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3970 ? S_GET_TYPE (fixP->fx_addsy)
3971 : fixP->fx_addsy->sy_number);
3972
3973 where[4] = (r_symbolnum >> 16) & 0x0ff;
3974 where[5] = (r_symbolnum >> 8) & 0x0ff;
3975 where[6] = r_symbolnum & 0x0ff;
3976 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3977 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3978 }
3979 #endif
3980
3981 #endif /* OBJ_AOUT or OBJ_BOUT */
3982
3983 #ifndef WORKING_DOT_WORD
3984 CONST int md_short_jump_size = 4;
3985 CONST int md_long_jump_size = 6;
3986
3987 void
3988 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3989 char *ptr;
3990 addressT from_addr, to_addr;
3991 fragS *frag;
3992 symbolS *to_symbol;
3993 {
3994 valueT offset;
3995
3996 offset = to_addr - (from_addr + 2);
3997
3998 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3999 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4000 }
4001
4002 void
4003 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4004 char *ptr;
4005 addressT from_addr, to_addr;
4006 fragS *frag;
4007 symbolS *to_symbol;
4008 {
4009 valueT offset;
4010
4011 if (cpu_of_arch (current_architecture) < m68020)
4012 {
4013 offset = to_addr - S_GET_VALUE (to_symbol);
4014 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4015 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4016 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4017 0, NO_RELOC);
4018 }
4019 else
4020 {
4021 offset = to_addr - (from_addr + 2);
4022 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4023 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4024 }
4025 }
4026
4027 #endif
4028
4029 /* Different values of OK tell what its OK to return. Things that
4030 aren't OK are an error (what a shock, no?)
4031
4032 0: Everything is OK
4033 10: Absolute 1:8 only
4034 20: Absolute 0:7 only
4035 30: absolute 0:15 only
4036 40: Absolute 0:31 only
4037 50: absolute 0:127 only
4038 55: absolute -64:63 only
4039 60: absolute -128:127 only
4040 70: absolute 0:4095 only
4041 80: No bignums
4042
4043 */
4044
4045 static int
4046 get_num (exp, ok)
4047 struct m68k_exp *exp;
4048 int ok;
4049 {
4050 if (exp->exp.X_op == O_absent)
4051 {
4052 /* Do the same thing the VAX asm does */
4053 op (exp) = O_constant;
4054 adds (exp) = 0;
4055 subs (exp) = 0;
4056 offs (exp) = 0;
4057 if (ok == 10)
4058 {
4059 as_warn ("expression out of range: defaulting to 1");
4060 offs (exp) = 1;
4061 }
4062 }
4063 else if (exp->exp.X_op == O_constant)
4064 {
4065 switch (ok)
4066 {
4067 case 10:
4068 if (offs (exp) < 1 || offs (exp) > 8)
4069 {
4070 as_warn ("expression out of range: defaulting to 1");
4071 offs (exp) = 1;
4072 }
4073 break;
4074 case 20:
4075 if (offs (exp) < 0 || offs (exp) > 7)
4076 goto outrange;
4077 break;
4078 case 30:
4079 if (offs (exp) < 0 || offs (exp) > 15)
4080 goto outrange;
4081 break;
4082 case 40:
4083 if (offs (exp) < 0 || offs (exp) > 32)
4084 goto outrange;
4085 break;
4086 case 50:
4087 if (offs (exp) < 0 || offs (exp) > 127)
4088 goto outrange;
4089 break;
4090 case 55:
4091 if (offs (exp) < -64 || offs (exp) > 63)
4092 goto outrange;
4093 break;
4094 case 60:
4095 if (offs (exp) < -128 || offs (exp) > 127)
4096 goto outrange;
4097 break;
4098 case 70:
4099 if (offs (exp) < 0 || offs (exp) > 4095)
4100 {
4101 outrange:
4102 as_warn ("expression out of range: defaulting to 0");
4103 offs (exp) = 0;
4104 }
4105 break;
4106 default:
4107 break;
4108 }
4109 }
4110 else if (exp->exp.X_op == O_big)
4111 {
4112 if (offs (exp) <= 0 /* flonum */
4113 && (ok == 80 /* no bignums */
4114 || (ok > 10 /* small-int ranges including 0 ok */
4115 /* If we have a flonum zero, a zero integer should
4116 do as well (e.g., in moveq). */
4117 && generic_floating_point_number.exponent == 0
4118 && generic_floating_point_number.low[0] == 0)))
4119 {
4120 /* HACK! Turn it into a long */
4121 LITTLENUM_TYPE words[6];
4122
4123 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4124 op (exp) = O_constant;
4125 adds (exp) = 0;
4126 subs (exp) = 0;
4127 offs (exp) = words[1] | (words[0] << 16);
4128 }
4129 else if (ok != 0)
4130 {
4131 op (exp) = O_constant;
4132 adds (exp) = 0;
4133 subs (exp) = 0;
4134 offs (exp) = (ok == 10) ? 1 : 0;
4135 as_warn ("Can't deal with expression; defaulting to %ld",
4136 offs (exp));
4137 }
4138 }
4139 else
4140 {
4141 if (ok >= 10 && ok <= 70)
4142 {
4143 op (exp) = O_constant;
4144 adds (exp) = 0;
4145 subs (exp) = 0;
4146 offs (exp) = (ok == 10) ? 1 : 0;
4147 as_warn ("Can't deal with expression; defaulting to %ld",
4148 offs (exp));
4149 }
4150 }
4151
4152 if (exp->size != SIZE_UNSPEC)
4153 {
4154 switch (exp->size)
4155 {
4156 case SIZE_UNSPEC:
4157 case SIZE_LONG:
4158 break;
4159 case SIZE_BYTE:
4160 if (!isbyte (offs (exp)))
4161 as_warn ("expression doesn't fit in BYTE");
4162 break;
4163 case SIZE_WORD:
4164 if (!isword (offs (exp)))
4165 as_warn ("expression doesn't fit in WORD");
4166 break;
4167 }
4168 }
4169
4170 return offs (exp);
4171 }
4172
4173 /* These are the back-ends for the various machine dependent pseudo-ops. */
4174 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4175
4176 static void
4177 s_data1 (ignore)
4178 int ignore;
4179 {
4180 subseg_set (data_section, 1);
4181 demand_empty_rest_of_line ();
4182 }
4183
4184 static void
4185 s_data2 (ignore)
4186 int ignore;
4187 {
4188 subseg_set (data_section, 2);
4189 demand_empty_rest_of_line ();
4190 }
4191
4192 static void
4193 s_bss (ignore)
4194 int ignore;
4195 {
4196 /* We don't support putting frags in the BSS segment, we fake it
4197 by marking in_bss, then looking at s_skip for clues. */
4198
4199 subseg_set (bss_section, 0);
4200 demand_empty_rest_of_line ();
4201 }
4202
4203 static void
4204 s_even (ignore)
4205 int ignore;
4206 {
4207 register int temp;
4208 register long temp_fill;
4209
4210 temp = 1; /* JF should be 2? */
4211 temp_fill = get_absolute_expression ();
4212 if (!need_pass_2) /* Never make frag if expect extra pass. */
4213 frag_align (temp, (int) temp_fill);
4214 demand_empty_rest_of_line ();
4215 }
4216
4217 static void
4218 s_proc (ignore)
4219 int ignore;
4220 {
4221 demand_empty_rest_of_line ();
4222 }
4223 \f
4224 /* Pseudo-ops handled for MRI compatibility. */
4225
4226 /* Handle an MRI style chip specification. */
4227
4228 static void
4229 mri_chip ()
4230 {
4231 char *s;
4232 char c;
4233 int i;
4234
4235 s = input_line_pointer;
4236 c = get_symbol_end ();
4237 for (i = 0; i < n_archs; i++)
4238 if (strcasecmp (s, archs[i].name) == 0)
4239 break;
4240 if (i >= n_archs)
4241 {
4242 as_bad ("%s: unrecognized processor name", s);
4243 *input_line_pointer = c;
4244 ignore_rest_of_line ();
4245 return;
4246 }
4247 *input_line_pointer = c;
4248
4249 if (*input_line_pointer == '/')
4250 current_architecture = 0;
4251 else
4252 current_architecture &= m68881 | m68851;
4253 current_architecture |= archs[i].arch;
4254
4255 while (*input_line_pointer == '/')
4256 {
4257 ++input_line_pointer;
4258 s = input_line_pointer;
4259 c = get_symbol_end ();
4260 if (strcmp (s, "68881") == 0)
4261 current_architecture |= m68881;
4262 else if (strcmp (s, "68851") == 0)
4263 current_architecture |= m68851;
4264 *input_line_pointer = c;
4265 }
4266 }
4267
4268 /* The MRI CHIP pseudo-op. */
4269
4270 static void
4271 s_chip (ignore)
4272 int ignore;
4273 {
4274 char *stop = NULL;
4275 char stopc;
4276
4277 if (flag_mri)
4278 stop = mri_comment_field (&stopc);
4279 mri_chip ();
4280 if (flag_mri)
4281 mri_comment_end (stop, stopc);
4282 demand_empty_rest_of_line ();
4283 }
4284
4285 /* The MRI FOPT pseudo-op. */
4286
4287 static void
4288 s_fopt (ignore)
4289 int ignore;
4290 {
4291 SKIP_WHITESPACE ();
4292
4293 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4294 {
4295 int temp;
4296
4297 input_line_pointer += 3;
4298 temp = get_absolute_expression ();
4299 if (temp < 0 || temp > 7)
4300 as_bad ("bad coprocessor id");
4301 else
4302 m68k_float_copnum = COP0 + temp;
4303 }
4304 else
4305 {
4306 as_bad ("unrecognized fopt option");
4307 ignore_rest_of_line ();
4308 return;
4309 }
4310
4311 demand_empty_rest_of_line ();
4312 }
4313
4314 /* The structure used to handle the MRI OPT pseudo-op. */
4315
4316 struct opt_action
4317 {
4318 /* The name of the option. */
4319 const char *name;
4320
4321 /* If this is not NULL, just call this function. The first argument
4322 is the ARG field of this structure, the second argument is
4323 whether the option was negated. */
4324 void (*pfn) PARAMS ((int arg, int on));
4325
4326 /* If this is not NULL, and the PFN field is NULL, set the variable
4327 this points to. Set it to the ARG field if the option was not
4328 negated, and the NOTARG field otherwise. */
4329 int *pvar;
4330
4331 /* The value to pass to PFN or to assign to *PVAR. */
4332 int arg;
4333
4334 /* The value to assign to *PVAR if the option is negated. If PFN is
4335 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4336 the option may not be negated. */
4337 int notarg;
4338 };
4339
4340 /* The table used to handle the MRI OPT pseudo-op. */
4341
4342 static void skip_to_comma PARAMS ((int, int));
4343 static void opt_nest PARAMS ((int, int));
4344 static void opt_chip PARAMS ((int, int));
4345 static void opt_list PARAMS ((int, int));
4346 static void opt_list_symbols PARAMS ((int, int));
4347
4348 static const struct opt_action opt_table[] =
4349 {
4350 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4351
4352 /* We do relaxing, so there is little use for these options. */
4353 { "b", 0, 0, 0, 0 },
4354 { "brs", 0, 0, 0, 0 },
4355 { "brb", 0, 0, 0, 0 },
4356 { "brl", 0, 0, 0, 0 },
4357 { "brw", 0, 0, 0, 0 },
4358
4359 { "c", 0, 0, 0, 0 },
4360 { "cex", 0, 0, 0, 0 },
4361 { "case", 0, &symbols_case_sensitive, 1, 0 },
4362 { "cl", 0, 0, 0, 0 },
4363 { "cre", 0, 0, 0, 0 },
4364 { "d", 0, &flag_keep_locals, 1, 0 },
4365 { "e", 0, 0, 0, 0 },
4366 { "f", 0, &flag_short_refs, 1, 0 },
4367 { "frs", 0, &flag_short_refs, 1, 0 },
4368 { "frl", 0, &flag_short_refs, 0, 1 },
4369 { "g", 0, 0, 0, 0 },
4370 { "i", 0, 0, 0, 0 },
4371 { "m", 0, 0, 0, 0 },
4372 { "mex", 0, 0, 0, 0 },
4373 { "mc", 0, 0, 0, 0 },
4374 { "md", 0, 0, 0, 0 },
4375 { "nest", opt_nest, 0, 0, 0 },
4376 { "next", skip_to_comma, 0, 0, 0 },
4377 { "o", 0, 0, 0, 0 },
4378 { "old", 0, 0, 0, 0 },
4379 { "op", skip_to_comma, 0, 0, 0 },
4380 { "pco", 0, 0, 0, 0 },
4381 { "p", opt_chip, 0, 0, 0 },
4382 { "pcr", 0, 0, 0, 0 },
4383 { "pcs", 0, 0, 0, 0 },
4384 { "r", 0, 0, 0, 0 },
4385 { "quick", 0, &m68k_quick, 1, 0 },
4386 { "rel32", 0, &m68k_rel32, 1, 0 },
4387 { "s", opt_list, 0, 0, 0 },
4388 { "t", opt_list_symbols, 0, 0, 0 },
4389 { "w", 0, &flag_no_warnings, 0, 1 },
4390 { "x", 0, 0, 0, 0 }
4391 };
4392
4393 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4394
4395 /* The MRI OPT pseudo-op. */
4396
4397 static void
4398 s_opt (ignore)
4399 int ignore;
4400 {
4401 do
4402 {
4403 int t;
4404 char *s;
4405 char c;
4406 int i;
4407 const struct opt_action *o;
4408
4409 SKIP_WHITESPACE ();
4410
4411 t = 1;
4412 if (*input_line_pointer == '-')
4413 {
4414 ++input_line_pointer;
4415 t = 0;
4416 }
4417 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4418 {
4419 input_line_pointer += 2;
4420 t = 0;
4421 }
4422
4423 s = input_line_pointer;
4424 c = get_symbol_end ();
4425
4426 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4427 {
4428 if (strcasecmp (s, o->name) == 0)
4429 {
4430 if (o->pfn)
4431 {
4432 /* Restore input_line_pointer now in case the option
4433 takes arguments. */
4434 *input_line_pointer = c;
4435 (*o->pfn) (o->arg, t);
4436 }
4437 else if (o->pvar != NULL)
4438 {
4439 if (! t && o->arg == o->notarg)
4440 as_bad ("option `%s' may not be negated", s);
4441 *input_line_pointer = c;
4442 *o->pvar = t ? o->arg : o->notarg;
4443 }
4444 else
4445 *input_line_pointer = c;
4446 break;
4447 }
4448 }
4449 if (i >= OPTCOUNT)
4450 {
4451 as_bad ("option `%s' not recognized", s);
4452 *input_line_pointer = c;
4453 }
4454 }
4455 while (*input_line_pointer++ == ',');
4456
4457 /* Move back to terminating character. */
4458 --input_line_pointer;
4459 demand_empty_rest_of_line ();
4460 }
4461
4462 /* Skip ahead to a comma. This is used for OPT options which we do
4463 not suppor tand which take arguments. */
4464
4465 static void
4466 skip_to_comma (arg, on)
4467 int arg;
4468 int on;
4469 {
4470 while (*input_line_pointer != ','
4471 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4472 ++input_line_pointer;
4473 }
4474
4475 /* Handle the OPT NEST=depth option. */
4476
4477 static void
4478 opt_nest (arg, on)
4479 int arg;
4480 int on;
4481 {
4482 if (*input_line_pointer != '=')
4483 {
4484 as_bad ("bad format of OPT NEST=depth");
4485 return;
4486 }
4487
4488 ++input_line_pointer;
4489 max_macro_nest = get_absolute_expression ();
4490 }
4491
4492 /* Handle the OPT P=chip option. */
4493
4494 static void
4495 opt_chip (arg, on)
4496 int arg;
4497 int on;
4498 {
4499 if (*input_line_pointer != '=')
4500 {
4501 /* This is just OPT P, which we do not support. */
4502 return;
4503 }
4504
4505 ++input_line_pointer;
4506 mri_chip ();
4507 }
4508
4509 /* Handle the OPT S option. */
4510
4511 static void
4512 opt_list (arg, on)
4513 int arg;
4514 int on;
4515 {
4516 listing_list (on);
4517 }
4518
4519 /* Handle the OPT T option. */
4520
4521 static void
4522 opt_list_symbols (arg, on)
4523 int arg;
4524 int on;
4525 {
4526 if (on)
4527 listing |= LISTING_SYMBOLS;
4528 else
4529 listing &=~ LISTING_SYMBOLS;
4530 }
4531
4532 /* Handle the MRI REG pseudo-op. */
4533
4534 static void
4535 s_reg (ignore)
4536 int ignore;
4537 {
4538 char *s;
4539 int c;
4540 struct m68k_op rop;
4541 unsigned long mask;
4542 char *stop = NULL;
4543 char stopc;
4544
4545 if (line_label == NULL)
4546 {
4547 as_bad ("missing label");
4548 ignore_rest_of_line ();
4549 return;
4550 }
4551
4552 if (flag_mri)
4553 stop = mri_comment_field (&stopc);
4554
4555 SKIP_WHITESPACE ();
4556
4557 s = input_line_pointer;
4558 while (isalnum ((unsigned char) *input_line_pointer)
4559 #ifdef REGISTER_PREFIX
4560 || *input_line_pointer == REGISTER_PREFIX
4561 #endif
4562 || *input_line_pointer == '/'
4563 || *input_line_pointer == '-')
4564 ++input_line_pointer;
4565 c = *input_line_pointer;
4566 *input_line_pointer = '\0';
4567
4568 if (m68k_ip_op (s, &rop) != 0)
4569 {
4570 if (rop.error == NULL)
4571 as_bad ("bad register list");
4572 else
4573 as_bad ("bad register list: %s", rop.error);
4574 *input_line_pointer = c;
4575 ignore_rest_of_line ();
4576 return;
4577 }
4578
4579 *input_line_pointer = c;
4580
4581 if (rop.mode == REGLST)
4582 mask = rop.mask;
4583 else if (rop.mode == DREG)
4584 mask = 1 << (rop.reg - DATA0);
4585 else if (rop.mode == AREG)
4586 mask = 1 << (rop.reg - ADDR0 + 8);
4587 else if (rop.mode == FPREG)
4588 mask = 1 << (rop.reg - FP0 + 16);
4589 else if (rop.mode == CONTROL
4590 && rop.reg == FPI)
4591 mask = 1 << 24;
4592 else if (rop.mode == CONTROL
4593 && rop.reg == FPS)
4594 mask = 1 << 25;
4595 else if (rop.mode == CONTROL
4596 && rop.reg == FPC)
4597 mask = 1 << 26;
4598 else
4599 {
4600 as_bad ("bad register list");
4601 ignore_rest_of_line ();
4602 return;
4603 }
4604
4605 S_SET_SEGMENT (line_label, absolute_section);
4606 S_SET_VALUE (line_label, mask);
4607 line_label->sy_frag = &zero_address_frag;
4608
4609 if (flag_mri)
4610 mri_comment_end (stop, stopc);
4611
4612 demand_empty_rest_of_line ();
4613 }
4614
4615 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4616
4617 struct save_opts
4618 {
4619 struct save_opts *next;
4620 int abspcadd;
4621 int symbols_case_sensitive;
4622 int keep_locals;
4623 int short_refs;
4624 int architecture;
4625 int quick;
4626 int rel32;
4627 int listing;
4628 int no_warnings;
4629 /* FIXME: We don't save OPT S. */
4630 };
4631
4632 /* This variable holds the stack of saved options. */
4633
4634 static struct save_opts *save_stack;
4635
4636 /* The MRI SAVE pseudo-op. */
4637
4638 static void
4639 s_save (ignore)
4640 int ignore;
4641 {
4642 struct save_opts *s;
4643
4644 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4645 s->abspcadd = m68k_abspcadd;
4646 s->symbols_case_sensitive = symbols_case_sensitive;
4647 s->keep_locals = flag_keep_locals;
4648 s->short_refs = flag_short_refs;
4649 s->architecture = current_architecture;
4650 s->quick = m68k_quick;
4651 s->rel32 = m68k_rel32;
4652 s->listing = listing;
4653 s->no_warnings = flag_no_warnings;
4654
4655 s->next = save_stack;
4656 save_stack = s;
4657
4658 demand_empty_rest_of_line ();
4659 }
4660
4661 /* The MRI RESTORE pseudo-op. */
4662
4663 static void
4664 s_restore (ignore)
4665 int ignore;
4666 {
4667 struct save_opts *s;
4668
4669 if (save_stack == NULL)
4670 {
4671 as_bad ("restore without save");
4672 ignore_rest_of_line ();
4673 return;
4674 }
4675
4676 s = save_stack;
4677 save_stack = s->next;
4678
4679 m68k_abspcadd = s->abspcadd;
4680 symbols_case_sensitive = s->symbols_case_sensitive;
4681 flag_keep_locals = s->keep_locals;
4682 flag_short_refs = s->short_refs;
4683 current_architecture = s->architecture;
4684 m68k_quick = s->quick;
4685 m68k_rel32 = s->rel32;
4686 listing = s->listing;
4687 flag_no_warnings = s->no_warnings;
4688
4689 free (s);
4690
4691 demand_empty_rest_of_line ();
4692 }
4693
4694 /* Types of MRI structured control directives. */
4695
4696 enum mri_control_type
4697 {
4698 mri_for,
4699 mri_if,
4700 mri_repeat,
4701 mri_while
4702 };
4703
4704 /* This structure is used to stack the MRI structured control
4705 directives. */
4706
4707 struct mri_control_info
4708 {
4709 /* The directive within which this one is enclosed. */
4710 struct mri_control_info *outer;
4711
4712 /* The type of directive. */
4713 enum mri_control_type type;
4714
4715 /* Whether an ELSE has been in an IF. */
4716 int else_seen;
4717
4718 /* The add or sub statement at the end of a FOR. */
4719 char *incr;
4720
4721 /* The label of the top of a FOR or REPEAT loop. */
4722 char *top;
4723
4724 /* The label to jump to for the next iteration, or the else
4725 expression of a conditional. */
4726 char *next;
4727
4728 /* The label to jump to to break out of the loop, or the label past
4729 the end of a conditional. */
4730 char *bottom;
4731 };
4732
4733 /* The stack of MRI structured control directives. */
4734
4735 static struct mri_control_info *mri_control_stack;
4736
4737 /* The current MRI structured control directive index number, used to
4738 generate label names. */
4739
4740 static int mri_control_index;
4741
4742 /* Some function prototypes. */
4743
4744 static char *mri_control_label PARAMS ((void));
4745 static struct mri_control_info *push_mri_control
4746 PARAMS ((enum mri_control_type));
4747 static void pop_mri_control PARAMS ((void));
4748 static int parse_mri_condition PARAMS ((int *));
4749 static int parse_mri_control_operand
4750 PARAMS ((int *, char **, char **, char **, char **));
4751 static int swap_mri_condition PARAMS ((int));
4752 static int reverse_mri_condition PARAMS ((int));
4753 static void build_mri_control_operand
4754 PARAMS ((int, int, char *, char *, char *, char *, const char *,
4755 const char *, int));
4756 static void parse_mri_control_expression
4757 PARAMS ((char *, int, const char *, const char *, int));
4758
4759 /* Generate a new MRI label structured control directive label name. */
4760
4761 static char *
4762 mri_control_label ()
4763 {
4764 char *n;
4765
4766 n = (char *) xmalloc (20);
4767 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
4768 ++mri_control_index;
4769 return n;
4770 }
4771
4772 /* Create a new MRI structured control directive. */
4773
4774 static struct mri_control_info *
4775 push_mri_control (type)
4776 enum mri_control_type type;
4777 {
4778 struct mri_control_info *n;
4779
4780 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
4781
4782 n->type = type;
4783 n->else_seen = 0;
4784 if (type == mri_if || type == mri_while)
4785 n->top = NULL;
4786 else
4787 n->top = mri_control_label ();
4788 n->next = mri_control_label ();
4789 n->bottom = mri_control_label ();
4790
4791 n->outer = mri_control_stack;
4792 mri_control_stack = n;
4793
4794 return n;
4795 }
4796
4797 /* Pop off the stack of MRI structured control directives. */
4798
4799 static void
4800 pop_mri_control ()
4801 {
4802 struct mri_control_info *n;
4803
4804 n = mri_control_stack;
4805 mri_control_stack = n->outer;
4806 if (n->top != NULL)
4807 free (n->top);
4808 free (n->next);
4809 free (n->bottom);
4810 free (n);
4811 }
4812
4813 /* Recognize a condition code in an MRI structured control expression. */
4814
4815 static int
4816 parse_mri_condition (pcc)
4817 int *pcc;
4818 {
4819 char c1, c2;
4820
4821 know (*input_line_pointer == '<');
4822
4823 ++input_line_pointer;
4824 c1 = *input_line_pointer++;
4825 c2 = *input_line_pointer++;
4826
4827 if (*input_line_pointer != '>')
4828 {
4829 as_bad ("syntax error in structured control directive");
4830 return 0;
4831 }
4832
4833 ++input_line_pointer;
4834 SKIP_WHITESPACE ();
4835
4836 if (isupper (c1))
4837 c1 = tolower (c1);
4838 if (isupper (c2))
4839 c2 = tolower (c2);
4840
4841 *pcc = (c1 << 8) | c2;
4842
4843 return 1;
4844 }
4845
4846 /* Parse a single operand in an MRI structured control expression. */
4847
4848 static int
4849 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
4850 int *pcc;
4851 char **leftstart;
4852 char **leftstop;
4853 char **rightstart;
4854 char **rightstop;
4855 {
4856 char *s;
4857
4858 SKIP_WHITESPACE ();
4859
4860 *pcc = -1;
4861 *leftstart = NULL;
4862 *leftstop = NULL;
4863 *rightstart = NULL;
4864 *rightstop = NULL;
4865
4866 if (*input_line_pointer == '<')
4867 {
4868 /* It's just a condition code. */
4869 return parse_mri_condition (pcc);
4870 }
4871
4872 /* Look ahead for the condition code. */
4873 for (s = input_line_pointer; *s != '\0'; ++s)
4874 {
4875 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
4876 break;
4877 }
4878 if (*s == '\0')
4879 {
4880 as_bad ("missing condition code in structured control directive");
4881 return 0;
4882 }
4883
4884 *leftstart = input_line_pointer;
4885 *leftstop = s;
4886 if (*leftstop > *leftstart
4887 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
4888 --*leftstop;
4889
4890 input_line_pointer = s;
4891 if (! parse_mri_condition (pcc))
4892 return 0;
4893
4894 /* Look ahead for AND or OR or end of line. */
4895 for (s = input_line_pointer; *s != '\0'; ++s)
4896 {
4897 if ((strncasecmp (s, "AND", 3) == 0
4898 && (s[3] == '.' || ! is_part_of_name (s[3])))
4899 || (strncasecmp (s, "OR", 2) == 0
4900 && (s[2] == '.' || ! is_part_of_name (s[2]))))
4901 break;
4902 }
4903
4904 *rightstart = input_line_pointer;
4905 *rightstop = s;
4906 if (*rightstop > *rightstart
4907 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
4908 --*rightstop;
4909
4910 input_line_pointer = s;
4911
4912 return 1;
4913 }
4914
4915 #define MCC(b1, b2) (((b1) << 8) | (b2))
4916
4917 /* Swap the sense of a condition. This changes the condition so that
4918 it generates the same result when the operands are swapped. */
4919
4920 static int
4921 swap_mri_condition (cc)
4922 int cc;
4923 {
4924 switch (cc)
4925 {
4926 case MCC ('h', 'i'): return MCC ('c', 's');
4927 case MCC ('l', 's'): return MCC ('c', 'c');
4928 case MCC ('c', 'c'): return MCC ('l', 's');
4929 case MCC ('c', 's'): return MCC ('h', 'i');
4930 case MCC ('p', 'l'): return MCC ('m', 'i');
4931 case MCC ('m', 'i'): return MCC ('p', 'l');
4932 case MCC ('g', 'e'): return MCC ('l', 'e');
4933 case MCC ('l', 't'): return MCC ('g', 't');
4934 case MCC ('g', 't'): return MCC ('l', 't');
4935 case MCC ('l', 'e'): return MCC ('g', 'e');
4936 }
4937 return cc;
4938 }
4939
4940 /* Reverse the sense of a condition. */
4941
4942 static int
4943 reverse_mri_condition (cc)
4944 int cc;
4945 {
4946 switch (cc)
4947 {
4948 case MCC ('h', 'i'): return MCC ('l', 's');
4949 case MCC ('l', 's'): return MCC ('h', 'i');
4950 case MCC ('c', 'c'): return MCC ('c', 's');
4951 case MCC ('c', 's'): return MCC ('c', 'c');
4952 case MCC ('n', 'e'): return MCC ('e', 'q');
4953 case MCC ('e', 'q'): return MCC ('n', 'e');
4954 case MCC ('v', 'c'): return MCC ('v', 's');
4955 case MCC ('v', 's'): return MCC ('v', 'c');
4956 case MCC ('p', 'l'): return MCC ('m', 'i');
4957 case MCC ('m', 'i'): return MCC ('p', 'l');
4958 case MCC ('g', 'e'): return MCC ('l', 't');
4959 case MCC ('l', 't'): return MCC ('g', 'e');
4960 case MCC ('g', 't'): return MCC ('l', 'e');
4961 case MCC ('l', 'e'): return MCC ('g', 't');
4962 }
4963 return cc;
4964 }
4965
4966 /* Build an MRI structured control expression. This generates test
4967 and branch instructions. It goes to TRUELAB if the condition is
4968 true, and to FALSELAB if the condition is false. Exactly one of
4969 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
4970 is the size qualifier for the expression. EXTENT is the size to
4971 use for the branch. */
4972
4973 static void
4974 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4975 rightstop, truelab, falselab, extent)
4976 int qual;
4977 int cc;
4978 char *leftstart;
4979 char *leftstop;
4980 char *rightstart;
4981 char *rightstop;
4982 const char *truelab;
4983 const char *falselab;
4984 int extent;
4985 {
4986 char *buf;
4987 char *s;
4988
4989 if (leftstart != NULL)
4990 {
4991 struct m68k_op leftop, rightop;
4992 char c;
4993
4994 /* Swap the compare operands, if necessary, to produce a legal
4995 m68k compare instruction. Comparing a register operand with
4996 a non-register operand requires the register to be on the
4997 right (cmp, cmpa). Comparing an immediate value with
4998 anything requires the immediate value to be on the left
4999 (cmpi). */
5000
5001 c = *leftstop;
5002 *leftstop = '\0';
5003 (void) m68k_ip_op (leftstart, &leftop);
5004 *leftstop = c;
5005
5006 c = *rightstop;
5007 *rightstop = '\0';
5008 (void) m68k_ip_op (rightstart, &rightop);
5009 *rightstop = c;
5010
5011 if (rightop.mode == IMMED
5012 || ((leftop.mode == DREG || leftop.mode == AREG)
5013 && (rightop.mode != DREG && rightop.mode != AREG)))
5014 {
5015 char *temp;
5016
5017 cc = swap_mri_condition (cc);
5018 temp = leftstart;
5019 leftstart = rightstart;
5020 rightstart = temp;
5021 temp = leftstop;
5022 leftstop = rightstop;
5023 rightstop = temp;
5024 }
5025 }
5026
5027 if (truelab == NULL)
5028 {
5029 cc = reverse_mri_condition (cc);
5030 truelab = falselab;
5031 }
5032
5033 if (leftstart != NULL)
5034 {
5035 buf = (char *) xmalloc (20
5036 + (leftstop - leftstart)
5037 + (rightstop - rightstart));
5038 s = buf;
5039 *s++ = 'c';
5040 *s++ = 'm';
5041 *s++ = 'p';
5042 if (qual != '\0')
5043 *s++ = qual;
5044 *s++ = ' ';
5045 memcpy (s, leftstart, leftstop - leftstart);
5046 s += leftstop - leftstart;
5047 *s++ = ',';
5048 memcpy (s, rightstart, rightstop - rightstart);
5049 s += rightstop - rightstart;
5050 *s = '\0';
5051 md_assemble (buf);
5052 free (buf);
5053 }
5054
5055 buf = (char *) xmalloc (20 + strlen (truelab));
5056 s = buf;
5057 *s++ = 'b';
5058 *s++ = cc >> 8;
5059 *s++ = cc & 0xff;
5060 if (extent != '\0')
5061 *s++ = extent;
5062 *s++ = ' ';
5063 strcpy (s, truelab);
5064 md_assemble (buf);
5065 free (buf);
5066 }
5067
5068 /* Parse an MRI structured control expression. This generates test
5069 and branch instructions. STOP is where the expression ends. It
5070 goes to TRUELAB if the condition is true, and to FALSELAB if the
5071 condition is false. Exactly one of TRUELAB and FALSELAB will be
5072 NULL, meaning to fall through. QUAL is the size qualifier for the
5073 expression. EXTENT is the size to use for the branch. */
5074
5075 static void
5076 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5077 char *stop;
5078 int qual;
5079 const char *truelab;
5080 const char *falselab;
5081 int extent;
5082 {
5083 int c;
5084 int cc;
5085 char *leftstart;
5086 char *leftstop;
5087 char *rightstart;
5088 char *rightstop;
5089
5090 c = *stop;
5091 *stop = '\0';
5092
5093 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5094 &rightstart, &rightstop))
5095 {
5096 *stop = c;
5097 return;
5098 }
5099
5100 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5101 {
5102 const char *flab;
5103
5104 if (falselab != NULL)
5105 flab = falselab;
5106 else
5107 flab = mri_control_label ();
5108
5109 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5110 rightstop, (const char *) NULL, flab, extent);
5111
5112 input_line_pointer += 3;
5113 if (*input_line_pointer != '.'
5114 || input_line_pointer[1] == '\0')
5115 qual = '\0';
5116 else
5117 {
5118 qual = input_line_pointer[1];
5119 input_line_pointer += 2;
5120 }
5121
5122 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5123 &rightstart, &rightstop))
5124 {
5125 *stop = c;
5126 return;
5127 }
5128
5129 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5130 rightstop, truelab, falselab, extent);
5131
5132 if (falselab == NULL)
5133 colon (flab);
5134 }
5135 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5136 {
5137 const char *tlab;
5138
5139 if (truelab != NULL)
5140 tlab = truelab;
5141 else
5142 tlab = mri_control_label ();
5143
5144 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5145 rightstop, tlab, (const char *) NULL, extent);
5146
5147 input_line_pointer += 2;
5148 if (*input_line_pointer != '.'
5149 || input_line_pointer[1] == '\0')
5150 qual = '\0';
5151 else
5152 {
5153 qual = input_line_pointer[1];
5154 input_line_pointer += 2;
5155 }
5156
5157 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5158 &rightstart, &rightstop))
5159 {
5160 *stop = c;
5161 return;
5162 }
5163
5164 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5165 rightstop, truelab, falselab, extent);
5166
5167 if (truelab == NULL)
5168 colon (tlab);
5169 }
5170 else
5171 {
5172 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5173 rightstop, truelab, falselab, extent);
5174 }
5175
5176 *stop = c;
5177 if (input_line_pointer != stop)
5178 as_bad ("syntax error in structured control directive");
5179 }
5180
5181 /* Handle the MRI IF pseudo-op. This may be a structured control
5182 directive, or it may be a regular assembler conditional, depending
5183 on its operands. */
5184
5185 static void
5186 s_mri_if (qual)
5187 int qual;
5188 {
5189 char *s;
5190 int c;
5191 struct mri_control_info *n;
5192
5193 /* A structured control directive must end with THEN with an
5194 optional qualifier. */
5195 s = input_line_pointer;
5196 while (! is_end_of_line[(unsigned char) *s]
5197 && (! flag_mri || *s != '*'))
5198 ++s;
5199 --s;
5200 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5201 --s;
5202
5203 if (s - input_line_pointer > 1
5204 && s[-1] == '.')
5205 s -= 2;
5206
5207 if (s - input_line_pointer < 3
5208 || strncasecmp (s - 3, "THEN", 4) != 0)
5209 {
5210 if (qual != '\0')
5211 {
5212 as_bad ("missing then");
5213 ignore_rest_of_line ();
5214 return;
5215 }
5216
5217 /* It's a conditional. */
5218 s_if (O_ne);
5219 return;
5220 }
5221
5222 /* Since this might be a conditional if, this pseudo-op will be
5223 called even if we are supported to be ignoring input. Double
5224 check now. Clobber *input_line_pointer so that ignore_input
5225 thinks that this is not a special pseudo-op. */
5226 c = *input_line_pointer;
5227 *input_line_pointer = 0;
5228 if (ignore_input ())
5229 {
5230 *input_line_pointer = c;
5231 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5232 ++input_line_pointer;
5233 demand_empty_rest_of_line ();
5234 return;
5235 }
5236 *input_line_pointer = c;
5237
5238 n = push_mri_control (mri_if);
5239
5240 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5241 n->next, s[1] == '.' ? s[2] : '\0');
5242
5243 if (s[1] == '.')
5244 input_line_pointer = s + 3;
5245 else
5246 input_line_pointer = s + 1;
5247
5248 if (flag_mri)
5249 {
5250 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5251 ++input_line_pointer;
5252 }
5253
5254 demand_empty_rest_of_line ();
5255 }
5256
5257 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5258 structured IF, associate the ELSE with the IF. Otherwise, assume
5259 it is a conditional else. */
5260
5261 static void
5262 s_mri_else (qual)
5263 int qual;
5264 {
5265 int c;
5266 char *buf;
5267 char q[2];
5268
5269 if (qual == '\0'
5270 && (mri_control_stack == NULL
5271 || mri_control_stack->type != mri_if
5272 || mri_control_stack->else_seen))
5273 {
5274 s_else (0);
5275 return;
5276 }
5277
5278 c = *input_line_pointer;
5279 *input_line_pointer = 0;
5280 if (ignore_input ())
5281 {
5282 *input_line_pointer = c;
5283 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5284 ++input_line_pointer;
5285 demand_empty_rest_of_line ();
5286 return;
5287 }
5288 *input_line_pointer = c;
5289
5290 if (mri_control_stack == NULL
5291 || mri_control_stack->type != mri_if
5292 || mri_control_stack->else_seen)
5293 {
5294 as_bad ("else without matching if");
5295 ignore_rest_of_line ();
5296 return;
5297 }
5298
5299 mri_control_stack->else_seen = 1;
5300
5301 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5302 q[0] = qual;
5303 q[1] = '\0';
5304 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5305 md_assemble (buf);
5306 free (buf);
5307
5308 colon (mri_control_stack->next);
5309
5310 if (flag_mri)
5311 {
5312 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5313 ++input_line_pointer;
5314 }
5315
5316 demand_empty_rest_of_line ();
5317 }
5318
5319 /* Handle the MRI ENDI pseudo-op. */
5320
5321 static void
5322 s_mri_endi (ignore)
5323 int ignore;
5324 {
5325 if (mri_control_stack == NULL
5326 || mri_control_stack->type != mri_if)
5327 {
5328 as_bad ("endi without matching if");
5329 ignore_rest_of_line ();
5330 return;
5331 }
5332
5333 /* ignore_input will not return true for ENDI, so we don't need to
5334 worry about checking it again here. */
5335
5336 if (! mri_control_stack->else_seen)
5337 colon (mri_control_stack->next);
5338 colon (mri_control_stack->bottom);
5339
5340 pop_mri_control ();
5341
5342 if (flag_mri)
5343 {
5344 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5345 ++input_line_pointer;
5346 }
5347
5348 demand_empty_rest_of_line ();
5349 }
5350
5351 /* Handle the MRI BREAK pseudo-op. */
5352
5353 static void
5354 s_mri_break (extent)
5355 int extent;
5356 {
5357 struct mri_control_info *n;
5358 char *buf;
5359 char ex[2];
5360
5361 n = mri_control_stack;
5362 while (n != NULL
5363 && n->type != mri_for
5364 && n->type != mri_repeat
5365 && n->type != mri_while)
5366 n = n->outer;
5367 if (n == NULL)
5368 {
5369 as_bad ("break outside of structured loop");
5370 ignore_rest_of_line ();
5371 return;
5372 }
5373
5374 buf = (char *) xmalloc (20 + strlen (n->bottom));
5375 ex[0] = extent;
5376 ex[1] = '\0';
5377 sprintf (buf, "bra%s %s", ex, n->bottom);
5378 md_assemble (buf);
5379 free (buf);
5380
5381 if (flag_mri)
5382 {
5383 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5384 ++input_line_pointer;
5385 }
5386
5387 demand_empty_rest_of_line ();
5388 }
5389
5390 /* Handle the MRI NEXT pseudo-op. */
5391
5392 static void
5393 s_mri_next (extent)
5394 int extent;
5395 {
5396 struct mri_control_info *n;
5397 char *buf;
5398 char ex[2];
5399
5400 n = mri_control_stack;
5401 while (n != NULL
5402 && n->type != mri_for
5403 && n->type != mri_repeat
5404 && n->type != mri_while)
5405 n = n->outer;
5406 if (n == NULL)
5407 {
5408 as_bad ("next outside of structured loop");
5409 ignore_rest_of_line ();
5410 return;
5411 }
5412
5413 buf = (char *) xmalloc (20 + strlen (n->next));
5414 ex[0] = extent;
5415 ex[1] = '\0';
5416 sprintf (buf, "bra%s %s", ex, n->next);
5417 md_assemble (buf);
5418 free (buf);
5419
5420 if (flag_mri)
5421 {
5422 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5423 ++input_line_pointer;
5424 }
5425
5426 demand_empty_rest_of_line ();
5427 }
5428
5429 /* Handle the MRI FOR pseudo-op. */
5430
5431 static void
5432 s_mri_for (qual)
5433 int qual;
5434 {
5435 const char *varstart, *varstop;
5436 const char *initstart, *initstop;
5437 const char *endstart, *endstop;
5438 const char *bystart, *bystop;
5439 int up;
5440 int by;
5441 int extent;
5442 struct mri_control_info *n;
5443 char *buf;
5444 char *s;
5445 char ex[2];
5446
5447 /* The syntax is
5448 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5449 */
5450
5451 SKIP_WHITESPACE ();
5452 varstart = input_line_pointer;
5453
5454 /* Look for the '='. */
5455 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5456 && *input_line_pointer != '=')
5457 ++input_line_pointer;
5458 if (*input_line_pointer != '=')
5459 {
5460 as_bad ("missing =");
5461 ignore_rest_of_line ();
5462 return;
5463 }
5464
5465 varstop = input_line_pointer;
5466 if (varstop > varstart
5467 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5468 --varstop;
5469
5470 ++input_line_pointer;
5471
5472 initstart = input_line_pointer;
5473
5474 /* Look for TO or DOWNTO. */
5475 up = 1;
5476 initstop = NULL;
5477 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5478 {
5479 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5480 && ! is_part_of_name (input_line_pointer[2]))
5481 {
5482 initstop = input_line_pointer;
5483 input_line_pointer += 2;
5484 break;
5485 }
5486 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5487 && ! is_part_of_name (input_line_pointer[6]))
5488 {
5489 initstop = input_line_pointer;
5490 up = 0;
5491 input_line_pointer += 6;
5492 break;
5493 }
5494 ++input_line_pointer;
5495 }
5496 if (initstop == NULL)
5497 {
5498 as_bad ("missing to or downto");
5499 ignore_rest_of_line ();
5500 return;
5501 }
5502 if (initstop > initstart
5503 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5504 --initstop;
5505
5506 SKIP_WHITESPACE ();
5507 endstart = input_line_pointer;
5508
5509 /* Look for BY or DO. */
5510 by = 0;
5511 endstop = NULL;
5512 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5513 {
5514 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5515 && ! is_part_of_name (input_line_pointer[2]))
5516 {
5517 endstop = input_line_pointer;
5518 by = 1;
5519 input_line_pointer += 2;
5520 break;
5521 }
5522 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5523 && (input_line_pointer[2] == '.'
5524 || ! is_part_of_name (input_line_pointer[2])))
5525 {
5526 endstop = input_line_pointer;
5527 input_line_pointer += 2;
5528 break;
5529 }
5530 ++input_line_pointer;
5531 }
5532 if (endstop == NULL)
5533 {
5534 as_bad ("missing do");
5535 ignore_rest_of_line ();
5536 return;
5537 }
5538 if (endstop > endstart
5539 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5540 --endstop;
5541
5542 if (! by)
5543 {
5544 bystart = "#1";
5545 bystop = bystart + 2;
5546 }
5547 else
5548 {
5549 SKIP_WHITESPACE ();
5550 bystart = input_line_pointer;
5551
5552 /* Look for DO. */
5553 bystop = NULL;
5554 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5555 {
5556 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5557 && (input_line_pointer[2] == '.'
5558 || ! is_part_of_name (input_line_pointer[2])))
5559 {
5560 bystop = input_line_pointer;
5561 input_line_pointer += 2;
5562 break;
5563 }
5564 ++input_line_pointer;
5565 }
5566 if (bystop == NULL)
5567 {
5568 as_bad ("missing do");
5569 ignore_rest_of_line ();
5570 return;
5571 }
5572 if (bystop > bystart
5573 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5574 --bystop;
5575 }
5576
5577 if (*input_line_pointer != '.')
5578 extent = '\0';
5579 else
5580 {
5581 extent = input_line_pointer[1];
5582 input_line_pointer += 2;
5583 }
5584
5585 /* We have fully parsed the FOR operands. Now build the loop. */
5586
5587 n = push_mri_control (mri_for);
5588
5589 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5590
5591 /* move init,var */
5592 s = buf;
5593 *s++ = 'm';
5594 *s++ = 'o';
5595 *s++ = 'v';
5596 *s++ = 'e';
5597 if (qual != '\0')
5598 *s++ = qual;
5599 *s++ = ' ';
5600 memcpy (s, initstart, initstop - initstart);
5601 s += initstop - initstart;
5602 *s++ = ',';
5603 memcpy (s, varstart, varstop - varstart);
5604 s += varstop - varstart;
5605 *s = '\0';
5606 md_assemble (buf);
5607
5608 colon (n->top);
5609
5610 /* cmp end,var */
5611 s = buf;
5612 *s++ = 'c';
5613 *s++ = 'm';
5614 *s++ = 'p';
5615 if (qual != '\0')
5616 *s++ = qual;
5617 *s++ = ' ';
5618 memcpy (s, endstart, endstop - endstart);
5619 s += endstop - endstart;
5620 *s++ = ',';
5621 memcpy (s, varstart, varstop - varstart);
5622 s += varstop - varstart;
5623 *s = '\0';
5624 md_assemble (buf);
5625
5626 /* bcc bottom */
5627 ex[0] = extent;
5628 ex[1] = '\0';
5629 if (up)
5630 sprintf (buf, "blt%s %s", ex, n->bottom);
5631 else
5632 sprintf (buf, "bgt%s %s", ex, n->bottom);
5633 md_assemble (buf);
5634
5635 /* Put together the add or sub instruction used by ENDF. */
5636 s = buf;
5637 if (up)
5638 strcpy (s, "add");
5639 else
5640 strcpy (s, "sub");
5641 s += 3;
5642 if (qual != '\0')
5643 *s++ = qual;
5644 *s++ = ' ';
5645 memcpy (s, bystart, bystop - bystart);
5646 s += bystop - bystart;
5647 *s++ = ',';
5648 memcpy (s, varstart, varstop - varstart);
5649 s += varstop - varstart;
5650 *s = '\0';
5651 n->incr = buf;
5652
5653 if (flag_mri)
5654 {
5655 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5656 ++input_line_pointer;
5657 }
5658
5659 demand_empty_rest_of_line ();
5660 }
5661
5662 /* Handle the MRI ENDF pseudo-op. */
5663
5664 static void
5665 s_mri_endf (ignore)
5666 int ignore;
5667 {
5668 if (mri_control_stack == NULL
5669 || mri_control_stack->type != mri_for)
5670 {
5671 as_bad ("endf without for");
5672 ignore_rest_of_line ();
5673 return;
5674 }
5675
5676 colon (mri_control_stack->next);
5677
5678 md_assemble (mri_control_stack->incr);
5679
5680 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5681 md_assemble (mri_control_stack->incr);
5682
5683 free (mri_control_stack->incr);
5684
5685 colon (mri_control_stack->bottom);
5686
5687 pop_mri_control ();
5688
5689 if (flag_mri)
5690 {
5691 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5692 ++input_line_pointer;
5693 }
5694
5695 demand_empty_rest_of_line ();
5696 }
5697
5698 /* Handle the MRI REPEAT pseudo-op. */
5699
5700 static void
5701 s_mri_repeat (ignore)
5702 int ignore;
5703 {
5704 struct mri_control_info *n;
5705
5706 n = push_mri_control (mri_repeat);
5707 colon (n->top);
5708 if (flag_mri)
5709 {
5710 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5711 ++input_line_pointer;
5712 }
5713 demand_empty_rest_of_line ();
5714 }
5715
5716 /* Handle the MRI UNTIL pseudo-op. */
5717
5718 static void
5719 s_mri_until (qual)
5720 int qual;
5721 {
5722 char *s;
5723
5724 if (mri_control_stack == NULL
5725 || mri_control_stack->type != mri_repeat)
5726 {
5727 as_bad ("until without repeat");
5728 ignore_rest_of_line ();
5729 return;
5730 }
5731
5732 colon (mri_control_stack->next);
5733
5734 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
5735 ;
5736
5737 parse_mri_control_expression (s, qual, (const char *) NULL,
5738 mri_control_stack->top, '\0');
5739
5740 colon (mri_control_stack->bottom);
5741
5742 input_line_pointer = s;
5743
5744 pop_mri_control ();
5745
5746 if (flag_mri)
5747 {
5748 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5749 ++input_line_pointer;
5750 }
5751
5752 demand_empty_rest_of_line ();
5753 }
5754
5755 /* Handle the MRI WHILE pseudo-op. */
5756
5757 static void
5758 s_mri_while (qual)
5759 int qual;
5760 {
5761 char *s;
5762
5763 struct mri_control_info *n;
5764
5765 s = input_line_pointer;
5766 while (! is_end_of_line[(unsigned char) *s]
5767 && (! flag_mri || *s != '*'))
5768 s++;
5769 --s;
5770 while (*s == ' ' || *s == '\t')
5771 --s;
5772 if (s - input_line_pointer > 1
5773 && s[-1] == '.')
5774 s -= 2;
5775 if (s - input_line_pointer < 2
5776 || strncasecmp (s - 1, "DO", 2) != 0)
5777 {
5778 as_bad ("missing do");
5779 ignore_rest_of_line ();
5780 return;
5781 }
5782
5783 n = push_mri_control (mri_while);
5784
5785 colon (n->next);
5786
5787 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
5788 s[1] == '.' ? s[2] : '\0');
5789
5790 input_line_pointer = s + 1;
5791 if (*input_line_pointer == '.')
5792 input_line_pointer += 2;
5793
5794 if (flag_mri)
5795 {
5796 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5797 ++input_line_pointer;
5798 }
5799
5800 demand_empty_rest_of_line ();
5801 }
5802
5803 /* Handle the MRI ENDW pseudo-op. */
5804
5805 static void
5806 s_mri_endw (ignore)
5807 int ignore;
5808 {
5809 char *buf;
5810
5811 if (mri_control_stack == NULL
5812 || mri_control_stack->type != mri_while)
5813 {
5814 as_bad ("endw without while");
5815 ignore_rest_of_line ();
5816 return;
5817 }
5818
5819 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
5820 sprintf (buf, "bra %s", mri_control_stack->next);
5821 md_assemble (buf);
5822 free (buf);
5823
5824 colon (mri_control_stack->bottom);
5825
5826 pop_mri_control ();
5827
5828 if (flag_mri)
5829 {
5830 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5831 ++input_line_pointer;
5832 }
5833
5834 demand_empty_rest_of_line ();
5835 }
5836 \f
5837 /*
5838 * md_parse_option
5839 * Invocation line includes a switch not recognized by the base assembler.
5840 * See if it's a processor-specific option. These are:
5841 *
5842 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5843 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5844 * Select the architecture. Instructions or features not
5845 * supported by the selected architecture cause fatal
5846 * errors. More than one may be specified. The default is
5847 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5848 * for -m68000, and -m68882 is a synonym for -m68881.
5849 * -[A]m[c]no-68851, -[A]m[c]no-68881
5850 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5851 * so don't use or document it, but that's the way the parsing
5852 * works).
5853 *
5854 * -pic Indicates PIC.
5855 * -k Indicates PIC. (Sun 3 only.)
5856 *
5857 */
5858
5859 #ifdef OBJ_ELF
5860 CONST char *md_shortopts = "lSA:m:kQ:V";
5861 #else
5862 CONST char *md_shortopts = "lSA:m:k";
5863 #endif
5864
5865 struct option md_longopts[] = {
5866 #define OPTION_PIC (OPTION_MD_BASE)
5867 {"pic", no_argument, NULL, OPTION_PIC},
5868 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5869 {"register-prefix-optional", no_argument, NULL,
5870 OPTION_REGISTER_PREFIX_OPTIONAL},
5871 {NULL, no_argument, NULL, 0}
5872 };
5873 size_t md_longopts_size = sizeof(md_longopts);
5874
5875 int
5876 md_parse_option (c, arg)
5877 int c;
5878 char *arg;
5879 {
5880 switch (c)
5881 {
5882 case 'l': /* -l means keep external to 2 bit offset
5883 rather than 16 bit one */
5884 flag_short_refs = 1;
5885 break;
5886
5887 case 'S': /* -S means that jbsr's always turn into
5888 jsr's. */
5889 flag_long_jumps = 1;
5890 break;
5891
5892 case 'A':
5893 if (*arg == 'm')
5894 arg++;
5895 /* intentional fall-through */
5896 case 'm':
5897
5898 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
5899 {
5900 int i;
5901 unsigned long arch;
5902 const char *oarg = arg;
5903
5904 arg += 3;
5905 if (*arg == 'm')
5906 {
5907 arg++;
5908 if (arg[0] == 'c' && arg[1] == '6')
5909 arg++;
5910 }
5911 for (i = 0; i < n_archs; i++)
5912 if (!strcmp (arg, archs[i].name))
5913 break;
5914 if (i == n_archs)
5915 {
5916 unknown:
5917 as_bad ("unrecognized option `%s'", oarg);
5918 return 0;
5919 }
5920 arch = archs[i].arch;
5921 if (arch == m68881)
5922 no_68881 = 1;
5923 else if (arch == m68851)
5924 no_68851 = 1;
5925 else
5926 goto unknown;
5927 }
5928 else
5929 {
5930 int i;
5931
5932 if (arg[0] == 'c' && arg[1] == '6')
5933 arg++;
5934
5935 for (i = 0; i < n_archs; i++)
5936 if (!strcmp (arg, archs[i].name))
5937 {
5938 unsigned long arch = archs[i].arch;
5939 if (cpu_of_arch (arch))
5940 /* It's a cpu spec. */
5941 {
5942 current_architecture &= ~m68000up;
5943 current_architecture |= arch;
5944 }
5945 else if (arch == m68881)
5946 {
5947 current_architecture |= m68881;
5948 no_68881 = 0;
5949 }
5950 else if (arch == m68851)
5951 {
5952 current_architecture |= m68851;
5953 no_68851 = 0;
5954 }
5955 else
5956 /* ??? */
5957 abort ();
5958 break;
5959 }
5960 if (i == n_archs)
5961 {
5962 as_bad ("unrecognized architecture specification `%s'", arg);
5963 return 0;
5964 }
5965 }
5966 break;
5967
5968 case OPTION_PIC:
5969 case 'k':
5970 flag_want_pic = 1;
5971 break; /* -pic, Position Independent Code */
5972
5973 case OPTION_REGISTER_PREFIX_OPTIONAL:
5974 flag_reg_prefix_optional = 1;
5975 break;
5976
5977 case 'Q':
5978 case 'V':
5979 break;
5980
5981 default:
5982 return 0;
5983 }
5984
5985 return 1;
5986 }
5987
5988 void
5989 md_show_usage (stream)
5990 FILE *stream;
5991 {
5992 fprintf(stream, "\
5993 680X0 options:\n\
5994 -l use 1 word for refs to undefined symbols [default 2]\n\
5995 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5996 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5997 | -mcpu32\n\
5998 specify variant of 680X0 architecture [default 68020]\n\
5999 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6000 target has/lacks floating-point coprocessor\n\
6001 [default yes for 68020, 68030, and cpu32]\n");
6002 fprintf(stream, "\
6003 -m68851 | -mno-68851\n\
6004 target has/lacks memory-management unit coprocessor\n\
6005 [default yes for 68020 and up]\n\
6006 -pic, -k generate position independent code\n\
6007 -S turn jbsr into jsr\n\
6008 --register-prefix-optional\n\
6009 recognize register names without prefix character\n");
6010 }
6011 \f
6012 #ifdef TEST2
6013
6014 /* TEST2: Test md_assemble() */
6015 /* Warning, this routine probably doesn't work anymore */
6016
6017 main ()
6018 {
6019 struct m68k_it the_ins;
6020 char buf[120];
6021 char *cp;
6022 int n;
6023
6024 m68k_ip_begin ();
6025 for (;;)
6026 {
6027 if (!gets (buf) || !*buf)
6028 break;
6029 if (buf[0] == '|' || buf[1] == '.')
6030 continue;
6031 for (cp = buf; *cp; cp++)
6032 if (*cp == '\t')
6033 *cp = ' ';
6034 if (is_label (buf))
6035 continue;
6036 memset (&the_ins, '\0', sizeof (the_ins));
6037 m68k_ip (&the_ins, buf);
6038 if (the_ins.error)
6039 {
6040 printf ("Error %s in %s\n", the_ins.error, buf);
6041 }
6042 else
6043 {
6044 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6045 for (n = 0; n < the_ins.numo; n++)
6046 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6047 printf (" ");
6048 print_the_insn (&the_ins.opcode[0], stdout);
6049 (void) putchar ('\n');
6050 }
6051 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6052 {
6053 if (the_ins.operands[n].error)
6054 {
6055 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6056 continue;
6057 }
6058 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6059 if (the_ins.operands[n].b_const)
6060 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6061 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6062 if (the_ins.operands[n].b_iadd)
6063 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6064 (void) putchar ('\n');
6065 }
6066 }
6067 m68k_ip_end ();
6068 return 0;
6069 }
6070
6071 is_label (str)
6072 char *str;
6073 {
6074 while (*str == ' ')
6075 str++;
6076 while (*str && *str != ' ')
6077 str++;
6078 if (str[-1] == ':' || str[1] == '=')
6079 return 1;
6080 return 0;
6081 }
6082
6083 #endif
6084
6085 /* Possible states for relaxation:
6086
6087 0 0 branch offset byte (bra, etc)
6088 0 1 word
6089 0 2 long
6090
6091 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6092 1 1 word
6093 1 2 long
6094
6095 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6096 2 1 word-long
6097 2 2 long-word
6098 2 3 long-long
6099
6100 */
6101
6102 /* We have no need to default values of symbols. */
6103
6104 /* ARGSUSED */
6105 symbolS *
6106 md_undefined_symbol (name)
6107 char *name;
6108 {
6109 return 0;
6110 }
6111
6112 /* Round up a section size to the appropriate boundary. */
6113 valueT
6114 md_section_align (segment, size)
6115 segT segment;
6116 valueT size;
6117 {
6118 return size; /* Byte alignment is fine */
6119 }
6120
6121 /* Exactly what point is a PC-relative offset relative TO?
6122 On the 68k, it is relative to the address of the first extension
6123 word. The difference between the addresses of the offset and the
6124 first extension word is stored in fx_pcrel_adjust. */
6125 long
6126 md_pcrel_from (fixP)
6127 fixS *fixP;
6128 {
6129 int adjust;
6130
6131 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6132 -1 as 64. */
6133 adjust = fixP->fx_pcrel_adjust;
6134 if (adjust == 64)
6135 adjust = -1;
6136 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6137 }
6138
6139 #ifndef BFD_ASSEMBLER
6140 /*ARGSUSED*/
6141 void
6142 tc_coff_symbol_emit_hook (ignore)
6143 symbolS *ignore;
6144 {
6145 }
6146
6147 int
6148 tc_coff_sizemachdep (frag)
6149 fragS *frag;
6150 {
6151 switch (frag->fr_subtype & 0x3)
6152 {
6153 case BYTE:
6154 return 1;
6155 case SHORT:
6156 return 2;
6157 case LONG:
6158 return 4;
6159 default:
6160 abort ();
6161 return 0;
6162 }
6163 }
6164 #endif
6165
6166 /* end of tc-m68k.c */