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* write.c (fixup_segment): Handle ABS-sym in -sym case rather than
[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #define NO_RELOC 0
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This array holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful */
32 #if defined (OBJ_ELF) || defined (TE_DELTA)
33 const char comment_chars[] = "|#";
34 #else
35 const char comment_chars[] = "|";
36 #endif
37
38 /* This array holds the chars that only start a comment at the beginning of
39 a line. If the line seems to have the form '# 123 filename'
40 .line and .file directives will appear in the pre-processed output */
41 /* Note that input_file.c hand checks for '#' at the beginning of the
42 first line of the input file. This is because the compiler outputs
43 #NO_APP at the beginning of its output. */
44 /* Also note that comments like this one will always work. */
45 const char line_comment_chars[] = "#";
46
47 const char line_separator_chars[] = "";
48
49 /* Chars that can be used to separate mant from exp in floating point nums */
50 CONST char EXP_CHARS[] = "eE";
51
52 /* Chars that mean this number is a floating point constant, as
53 in "0f12.456" or "0d1.2345e12". */
54
55 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
56
57 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
58 changed in read.c . Ideally it shouldn't have to know about it at all,
59 but nothing is ideal around here. */
60
61 const int md_reloc_size = 8; /* Size of relocation record */
62
63 /* Are we trying to generate PIC code? If so, absolute references
64 ought to be made into linkage table references or pc-relative
65 references. */
66 int flag_want_pic;
67
68 static int flag_short_refs; /* -l option */
69 static int flag_long_jumps; /* -S option */
70
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 #else
74 int flag_reg_prefix_optional;
75 #endif
76
77 /* The floating point coprocessor to use by default. */
78 static enum m68k_register m68k_float_copnum = COP1;
79
80 /* If this is non-zero, then references to number(%pc) will be taken
81 to refer to number, rather than to %pc + number. */
82 static int m68k_abspcadd;
83
84 /* If this is non-zero, then the quick forms of the move, add, and sub
85 instructions are used when possible. */
86 static int m68k_quick = 1;
87
88 /* If this is non-zero, then if the size is not specified for a base
89 or outer displacement, the assembler assumes that the size should
90 be 32 bits. */
91 static int m68k_rel32 = 1;
92
93 /* Its an arbitrary name: This means I don't approve of it */
94 /* See flames below */
95 static struct obstack robyn;
96
97 #define TAB(x,y) (((x)<<2)+(y))
98 #define TABTYPE(xy) ((xy) >> 2)
99 #define BYTE 0
100 #define SHORT 1
101 #define LONG 2
102 #define SZ_UNDEF 3
103 #undef BRANCH
104 /* Case `g' except when BCC68000 is applicable. */
105 #define ABRANCH 1
106 /* Coprocessor branches. */
107 #define FBRANCH 2
108 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
109 supported on all cpus. Widens to 32-bit absolute. */
110 #define PCREL 3
111 /* For inserting an extra jmp instruction with long offset on 68000,
112 for expanding conditional branches. (Not bsr or bra.) Since the
113 68000 doesn't support 32-bit displacements for conditional
114 branches, we fake it by reversing the condition and branching
115 around a jmp with an absolute long operand. */
116 #define BCC68000 4
117 /* For the DBcc "instructions". If the displacement requires 32 bits,
118 the branch-around-a-jump game is played here too. */
119 #define DBCC 5
120 /* Not currently used? */
121 #define PCLEA 6
122 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
123 in 16 or 8 bits. */
124 #define PCINDEX 7
125
126 struct m68k_incant
127 {
128 const char *m_operands;
129 unsigned long m_opcode;
130 short m_opnum;
131 short m_codenum;
132 int m_arch;
133 struct m68k_incant *m_next;
134 };
135
136 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
137 #define gettwo(x) (((x)->m_opcode)&0xffff)
138
139 static const enum m68k_register m68000_control_regs[] = { 0 };
140 static const enum m68k_register m68010_control_regs[] = {
141 SFC, DFC, USP, VBR,
142 0
143 };
144 static const enum m68k_register m68020_control_regs[] = {
145 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
146 0
147 };
148 static const enum m68k_register m68040_control_regs[] = {
149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
150 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
151 0
152 };
153 static const enum m68k_register m68060_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
155 USP, VBR, URP, SRP, PCR,
156 0
157 };
158 #define cpu32_control_regs m68010_control_regs
159
160 static const enum m68k_register *control_regs;
161
162 /* internal form of a 68020 instruction */
163 struct m68k_it
164 {
165 const char *error;
166 const char *args; /* list of opcode info */
167 int numargs;
168
169 int numo; /* Number of shorts in opcode */
170 short opcode[11];
171
172 struct m68k_op operands[6];
173
174 int nexp; /* number of exprs in use */
175 struct m68k_exp exprs[4];
176
177 int nfrag; /* Number of frags we have to produce */
178 struct
179 {
180 int fragoff; /* Where in the current opcode the frag ends */
181 symbolS *fadd;
182 long foff;
183 int fragty;
184 }
185 fragb[4];
186
187 int nrel; /* Num of reloc strucs in use */
188 struct
189 {
190 int n;
191 expressionS exp;
192 char wid;
193 char pcrel;
194 /* In a pc relative address the difference between the address
195 of the offset and the address that the offset is relative
196 to. This depends on the addressing mode. Basically this
197 is the value to put in the offset field to address the
198 first byte of the offset, without regarding the special
199 significance of some values (in the branch instruction, for
200 example). */
201 int pcrel_fix;
202 }
203 reloc[5]; /* Five is enough??? */
204 };
205
206 #define cpu_of_arch(x) ((x) & m68000up)
207 #define float_of_arch(x) ((x) & mfloat)
208 #define mmu_of_arch(x) ((x) & mmmu)
209
210 static struct m68k_it the_ins; /* the instruction being assembled */
211
212 #define op(ex) ((ex)->exp.X_op)
213 #define adds(ex) ((ex)->exp.X_add_symbol)
214 #define subs(ex) ((ex)->exp.X_op_symbol)
215 #define offs(ex) ((ex)->exp.X_add_number)
216
217 /* Macros for adding things to the m68k_it struct */
218
219 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
220
221 /* Like addword, but goes BEFORE general operands */
222 static void
223 insop (w, opcode)
224 int w;
225 struct m68k_incant *opcode;
226 {
227 int z;
228 for(z=the_ins.numo;z>opcode->m_codenum;--z)
229 the_ins.opcode[z]=the_ins.opcode[z-1];
230 for(z=0;z<the_ins.nrel;z++)
231 the_ins.reloc[z].n+=2;
232 for (z = 0; z < the_ins.nfrag; z++)
233 the_ins.fragb[z].fragoff++;
234 the_ins.opcode[opcode->m_codenum]=w;
235 the_ins.numo++;
236 }
237
238 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
239 Blecch. */
240 static void
241 add_fix (width, exp, pc_rel, pc_fix)
242 char width;
243 struct m68k_exp *exp;
244 int pc_rel;
245 int pc_fix;
246 {
247 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
248 ? (the_ins.numo*2-1)
249 : (((width)=='b')
250 ? (the_ins.numo*2+1)
251 : (the_ins.numo*2)));
252 the_ins.reloc[the_ins.nrel].exp = exp->exp;
253 the_ins.reloc[the_ins.nrel].wid = width;
254 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
255 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
256 }
257
258 /* Cause an extra frag to be generated here, inserting up to 10 bytes
259 (that value is chosen in the frag_var call in md_assemble). TYPE
260 is the subtype of the frag to be generated; its primary type is
261 rs_machine_dependent.
262
263 The TYPE parameter is also used by md_convert_frag_1 and
264 md_estimate_size_before_relax. The appropriate type of fixup will
265 be emitted by md_convert_frag_1.
266
267 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
268 static void
269 add_frag(add,off,type)
270 symbolS *add;
271 long off;
272 int type;
273 {
274 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
275 the_ins.fragb[the_ins.nfrag].fadd=add;
276 the_ins.fragb[the_ins.nfrag].foff=off;
277 the_ins.fragb[the_ins.nfrag++].fragty=type;
278 }
279
280 #define isvar(ex) \
281 (op (ex) != O_constant && op (ex) != O_big)
282
283 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
284 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
285 static int reverse_16_bits PARAMS ((int in));
286 static int reverse_8_bits PARAMS ((int in));
287 static void install_gen_operand PARAMS ((int mode, int val));
288 static void install_operand PARAMS ((int mode, int val));
289 static void s_bss PARAMS ((int));
290 static void s_data1 PARAMS ((int));
291 static void s_data2 PARAMS ((int));
292 static void s_even PARAMS ((int));
293 static void s_proc PARAMS ((int));
294 static void mri_chip PARAMS ((void));
295 static void s_chip PARAMS ((int));
296 static void s_fopt PARAMS ((int));
297 static void s_opt PARAMS ((int));
298 static void s_reg PARAMS ((int));
299 static void s_restore PARAMS ((int));
300 static void s_save PARAMS ((int));
301 static void s_mri_if PARAMS ((int));
302 static void s_mri_else PARAMS ((int));
303 static void s_mri_endi PARAMS ((int));
304 static void s_mri_break PARAMS ((int));
305 static void s_mri_next PARAMS ((int));
306 static void s_mri_for PARAMS ((int));
307 static void s_mri_endf PARAMS ((int));
308 static void s_mri_repeat PARAMS ((int));
309 static void s_mri_until PARAMS ((int));
310 static void s_mri_while PARAMS ((int));
311 static void s_mri_endw PARAMS ((int));
312
313 static int current_architecture;
314
315 struct m68k_cpu {
316 unsigned long arch;
317 const char *name;
318 };
319
320 static const struct m68k_cpu archs[] = {
321 { m68000, "68000" },
322 { m68010, "68010" },
323 { m68020, "68020" },
324 { m68030, "68030" },
325 { m68040, "68040" },
326 { m68060, "68060" },
327 { cpu32, "cpu32" },
328 { m68881, "68881" },
329 { m68851, "68851" },
330 /* Aliases (effectively, so far as gas is concerned) for the above
331 cpus. */
332 { m68020, "68k" },
333 { m68000, "68302" },
334 { m68000, "68008" },
335 { m68000, "68ec000" },
336 { m68000, "68hc000" },
337 { m68000, "68hc001" },
338 { m68020, "68ec020" },
339 { m68030, "68ec030" },
340 { m68040, "68ec040" },
341 { cpu32, "68330" },
342 { cpu32, "68331" },
343 { cpu32, "68332" },
344 { cpu32, "68333" },
345 { cpu32, "68340" },
346 { cpu32, "68360" },
347 { m68881, "68882" },
348 };
349
350 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
351
352 /* BCC68000 is for patching in an extra jmp instruction for long offsets
353 on the 68000. The 68000 doesn't support long branches with branchs */
354
355 /* This table desribes how you change sizes for the various types of variable
356 size expressions. This version only supports two kinds. */
357
358 /* Note that calls to frag_var need to specify the maximum expansion
359 needed; this is currently 10 bytes for DBCC. */
360
361 /* The fields are:
362 How far Forward this mode will reach:
363 How far Backward this mode will reach:
364 How many bytes this mode will add to the size of the frag
365 Which mode to go to if the offset won't fit in this one
366 */
367 relax_typeS md_relax_table[] =
368 {
369 {1, 1, 0, 0}, /* First entries aren't used */
370 {1, 1, 0, 0}, /* For no good reason except */
371 {1, 1, 0, 0}, /* that the VAX doesn't either */
372 {1, 1, 0, 0},
373
374 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
375 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
376 {0, 0, 4, 0},
377 {1, 1, 0, 0},
378
379 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
380 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
381 {0, 0, 4, 0},
382 {1, 1, 0, 0},
383
384 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
385 {(32767), (-32768), 2, TAB (PCREL, LONG)},
386 {0, 0, 4, 0},
387 {1, 1, 0, 0},
388
389 {(127), (-128), 0, TAB (BCC68000, SHORT)},
390 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
391 {0, 0, 6, 0}, /* jmp long space */
392 {1, 1, 0, 0},
393
394 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
395 {(32767), (-32768), 2, TAB (DBCC, LONG)},
396 {0, 0, 10, 0}, /* bra/jmp long space */
397 {1, 1, 0, 0},
398
399 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
400 {32767, -32768, 2, TAB (PCLEA, LONG)},
401 {0, 0, 6, 0},
402 {1, 1, 0, 0},
403
404 /* For, e.g., jmp pcrel indexed. */
405 {125, -130, 0, TAB (PCINDEX, SHORT)},
406 {32765, -32770, 2, TAB (PCINDEX, LONG)},
407 {0, 0, 4, 0},
408 {1, 1, 0, 0},
409 };
410
411 /* These are the machine dependent pseudo-ops. These are included so
412 the assembler can work on the output from the SUN C compiler, which
413 generates these.
414 */
415
416 /* This table describes all the machine specific pseudo-ops the assembler
417 has to support. The fields are:
418 pseudo-op name without dot
419 function to call to execute this pseudo-op
420 Integer arg to pass to the function
421 */
422 const pseudo_typeS md_pseudo_table[] =
423 {
424 {"data1", s_data1, 0},
425 {"data2", s_data2, 0},
426 {"bss", s_bss, 0},
427 {"even", s_even, 0},
428 {"skip", s_space, 0},
429 {"proc", s_proc, 0},
430 #ifdef TE_SUN3
431 {"align", s_align_bytes, 0},
432 #endif
433 #ifdef OBJ_ELF
434 {"swbeg", s_ignore, 0},
435 #endif
436
437 /* The following pseudo-ops are supported for MRI compatibility. */
438 {"chip", s_chip, 0},
439 {"comline", s_space, 1},
440 {"fopt", s_fopt, 0},
441 {"mask2", s_ignore, 0},
442 {"opt", s_opt, 0},
443 {"reg", s_reg, 0},
444 {"restore", s_restore, 0},
445 {"save", s_save, 0},
446
447 {"if", s_mri_if, 0},
448 {"if.b", s_mri_if, 'b'},
449 {"if.w", s_mri_if, 'w'},
450 {"if.l", s_mri_if, 'l'},
451 {"else", s_mri_else, 0},
452 {"else.s", s_mri_else, 's'},
453 {"else.l", s_mri_else, 'l'},
454 {"endi", s_mri_endi, 0},
455 {"break", s_mri_break, 0},
456 {"break.s", s_mri_break, 's'},
457 {"break.l", s_mri_break, 'l'},
458 {"next", s_mri_next, 0},
459 {"next.s", s_mri_next, 's'},
460 {"next.l", s_mri_next, 'l'},
461 {"for", s_mri_for, 0},
462 {"for.b", s_mri_for, 'b'},
463 {"for.w", s_mri_for, 'w'},
464 {"for.l", s_mri_for, 'l'},
465 {"endf", s_mri_endf, 0},
466 {"repeat", s_mri_repeat, 0},
467 {"until", s_mri_until, 0},
468 {"until.b", s_mri_until, 'b'},
469 {"until.w", s_mri_until, 'w'},
470 {"until.l", s_mri_until, 'l'},
471 {"while", s_mri_while, 0},
472 {"while.b", s_mri_while, 'b'},
473 {"while.w", s_mri_while, 'w'},
474 {"while.l", s_mri_while, 'l'},
475 {"endw", s_mri_endw, 0},
476
477 {0, 0, 0}
478 };
479
480
481 /* The mote pseudo ops are put into the opcode table, since they
482 don't start with a . they look like opcodes to gas.
483 */
484 extern void obj_coff_section ();
485
486 CONST pseudo_typeS mote_pseudo_table[] =
487 {
488
489 {"dcl", cons, 4},
490 {"dc", cons, 2},
491 {"dcw", cons, 2},
492 {"dcb", cons, 1},
493
494 {"dsl", s_space, 4},
495 {"ds", s_space, 2},
496 {"dsw", s_space, 2},
497 {"dsb", s_space, 1},
498
499 {"xdef", s_globl, 0},
500 {"align", s_align_ptwo, 0},
501 #ifdef M68KCOFF
502 {"sect", obj_coff_section, 0},
503 {"section", obj_coff_section, 0},
504 #endif
505 {0, 0, 0}
506 };
507
508 #define issbyte(x) ((x)>=-128 && (x)<=127)
509 #define isubyte(x) ((x)>=0 && (x)<=255)
510 #define issword(x) ((x)>=-32768 && (x)<=32767)
511 #define isuword(x) ((x)>=0 && (x)<=65535)
512
513 #define isbyte(x) ((x)>= -255 && (x)<=255)
514 #define isword(x) ((x)>=-32768 && (x)<=65535)
515 #define islong(x) (1)
516
517 extern char *input_line_pointer;
518
519 static char mklower_table[256];
520 #define mklower(c) (mklower_table[(unsigned char)(c)])
521 static char notend_table[256];
522 static char alt_notend_table[256];
523 #define notend(s) \
524 (! (notend_table[(unsigned char) *s] \
525 || (*s == ':' \
526 && alt_notend_table[(unsigned char) s[1]])))
527
528 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
529
530 #ifdef NO_PCREL_RELOCS
531
532 int
533 make_pcrel_absolute(fixP, add_number)
534 fixS *fixP;
535 long *add_number;
536 {
537 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
538
539 /* rewrite the PC relative instructions to absolute address ones.
540 * these are rumoured to be faster, and the apollo linker refuses
541 * to deal with the PC relative relocations.
542 */
543 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
544 {
545 opcode[0] = 0x4e;
546 opcode[1] = 0xf9;
547 }
548 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
549 {
550 opcode[0] = 0x4e;
551 opcode[1] = 0xb9;
552 }
553 else
554 as_fatal ("Unknown PC relative instruction");
555 *add_number -= 4;
556 return 0;
557 }
558
559 #endif /* NO_PCREL_RELOCS */
560
561 short
562 tc_coff_fix2rtype (fixP)
563 fixS *fixP;
564 {
565 if (fixP->fx_tcbit && fixP->fx_size == 4)
566 return R_RELLONG_NEG;
567 #ifdef NO_PCREL_RELOCS
568 know (fixP->fx_pcrel == 0);
569 return (fixP->fx_size == 1 ? R_RELBYTE
570 : fixP->fx_size == 2 ? R_DIR16
571 : R_DIR32);
572 #else
573 return (fixP->fx_pcrel ?
574 (fixP->fx_size == 1 ? R_PCRBYTE :
575 fixP->fx_size == 2 ? R_PCRWORD :
576 R_PCRLONG) :
577 (fixP->fx_size == 1 ? R_RELBYTE :
578 fixP->fx_size == 2 ? R_RELWORD :
579 R_RELLONG));
580 #endif
581 }
582
583 #endif
584
585 #ifdef BFD_ASSEMBLER
586
587 arelent *
588 tc_gen_reloc (section, fixp)
589 asection *section;
590 fixS *fixp;
591 {
592 arelent *reloc;
593 bfd_reloc_code_real_type code;
594
595 if (fixP->fx_tcbit)
596 abort ();
597
598 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
599 switch (F (fixp->fx_size, fixp->fx_pcrel))
600 {
601 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
602 MAP (1, 0, BFD_RELOC_8);
603 MAP (2, 0, BFD_RELOC_16);
604 MAP (4, 0, BFD_RELOC_32);
605 MAP (1, 1, BFD_RELOC_8_PCREL);
606 MAP (2, 1, BFD_RELOC_16_PCREL);
607 MAP (4, 1, BFD_RELOC_32_PCREL);
608 default:
609 abort ();
610 }
611
612 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
613 assert (reloc != 0);
614 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
615 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
616 if (fixp->fx_pcrel)
617 reloc->addend = fixp->fx_addnumber;
618 else
619 reloc->addend = 0;
620
621 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
622 assert (reloc->howto != 0);
623
624 return reloc;
625 }
626
627 #endif /* BFD_ASSEMBLER */
628
629 /* Handle of the OPCODE hash table. NULL means any use before
630 m68k_ip_begin() will crash. */
631 static struct hash_control *op_hash;
632 \f
633 /* Assemble an m68k instruction. */
634
635 void
636 m68k_ip (instring)
637 char *instring;
638 {
639 register char *p;
640 register struct m68k_op *opP;
641 register struct m68k_incant *opcode;
642 register const char *s;
643 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
644 char *pdot, *pdotmove;
645 enum m68k_size siz1, siz2;
646 char c;
647 int losing;
648 int opsfound;
649 char *crack_operand ();
650 LITTLENUM_TYPE words[6];
651 LITTLENUM_TYPE *wordp;
652 unsigned long ok_arch = 0;
653
654 if (*instring == ' ')
655 instring++; /* skip leading whitespace */
656
657 /* Scan up to end of operation-code, which MUST end in end-of-string
658 or exactly 1 space. */
659 pdot = 0;
660 for (p = instring; *p != '\0'; p++)
661 {
662 if (*p == ' ')
663 break;
664 if (*p == '.')
665 pdot = p;
666 }
667
668 if (p == instring)
669 {
670 the_ins.error = "No operator";
671 return;
672 }
673
674 /* p now points to the end of the opcode name, probably whitespace.
675 Make sure the name is null terminated by clobbering the
676 whitespace, look it up in the hash table, then fix it back.
677 Remove a dot, first, since the opcode tables have none. */
678 if (pdot != NULL)
679 {
680 for (pdotmove = pdot; pdotmove < p; pdotmove++)
681 *pdotmove = pdotmove[1];
682 p--;
683 }
684
685 c = *p;
686 *p = '\0';
687 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
688 *p = c;
689
690 if (pdot != NULL)
691 {
692 for (pdotmove = p; pdotmove > pdot; pdotmove--)
693 *pdotmove = pdotmove[-1];
694 *pdot = '.';
695 ++p;
696 }
697
698 if (opcode == NULL)
699 {
700 the_ins.error = "Unknown operator";
701 return;
702 }
703
704 /* found a legitimate opcode, start matching operands */
705 while (*p == ' ')
706 ++p;
707
708 if (opcode->m_operands == 0)
709 {
710 char *old = input_line_pointer;
711 *old = '\n';
712 input_line_pointer = p;
713 /* Ahh - it's a motorola style psuedo op */
714 mote_pseudo_table[opcode->m_opnum].poc_handler
715 (mote_pseudo_table[opcode->m_opnum].poc_val);
716 input_line_pointer = old;
717 *old = 0;
718
719 return;
720 }
721
722 if (flag_mri && opcode->m_opnum == 0)
723 {
724 /* In MRI mode, random garbage is allowed after an instruction
725 which accepts no operands. */
726 the_ins.args = opcode->m_operands;
727 the_ins.numargs = opcode->m_opnum;
728 the_ins.numo = opcode->m_codenum;
729 the_ins.opcode[0] = getone (opcode);
730 the_ins.opcode[1] = gettwo (opcode);
731 return;
732 }
733
734 for (opP = &the_ins.operands[0]; *p; opP++)
735 {
736 p = crack_operand (p, opP);
737
738 if (opP->error)
739 {
740 the_ins.error = opP->error;
741 return;
742 }
743 }
744
745 opsfound = opP - &the_ins.operands[0];
746
747 /* This ugly hack is to support the floating pt opcodes in their
748 standard form. Essentially, we fake a first enty of type COP#1 */
749 if (opcode->m_operands[0] == 'I')
750 {
751 int n;
752
753 for (n = opsfound; n > 0; --n)
754 the_ins.operands[n] = the_ins.operands[n - 1];
755
756 memset ((char *) (&the_ins.operands[0]), '\0',
757 sizeof (the_ins.operands[0]));
758 the_ins.operands[0].mode = CONTROL;
759 the_ins.operands[0].reg = m68k_float_copnum;
760 opsfound++;
761 }
762
763 /* We've got the operands. Find an opcode that'll accept them */
764 for (losing = 0;;)
765 {
766 /* If we didn't get the right number of ops, or we have no
767 common model with this pattern then reject this pattern. */
768
769 if (opsfound != opcode->m_opnum
770 || ((opcode->m_arch & current_architecture) == 0))
771 {
772 ++losing;
773 ok_arch |= opcode->m_arch;
774 }
775 else
776 {
777 for (s = opcode->m_operands, opP = &the_ins.operands[0];
778 *s && !losing;
779 s += 2, opP++)
780 {
781 /* Warning: this switch is huge! */
782 /* I've tried to organize the cases into this order:
783 non-alpha first, then alpha by letter. Lower-case
784 goes directly before uppercase counterpart. */
785 /* Code with multiple case ...: gets sorted by the lowest
786 case ... it belongs to. I hope this makes sense. */
787 switch (*s)
788 {
789 case '!':
790 switch (opP->mode)
791 {
792 case IMMED:
793 case DREG:
794 case AREG:
795 case FPREG:
796 case CONTROL:
797 case AINC:
798 case ADEC:
799 case REGLST:
800 losing++;
801 break;
802 default:
803 break;
804 }
805 break;
806
807 case '`':
808 switch (opP->mode)
809 {
810 case IMMED:
811 case DREG:
812 case AREG:
813 case FPREG:
814 case CONTROL:
815 case AINC:
816 case REGLST:
817 case AINDR:
818 losing++;
819 break;
820 default:
821 break;
822 }
823 break;
824
825 case '#':
826 if (opP->mode != IMMED)
827 losing++;
828 else if (s[1] == 'b'
829 && ! isvar (&opP->disp)
830 && (opP->disp.exp.X_op != O_constant
831 || ! isbyte (opP->disp.exp.X_add_number)))
832 losing++;
833 else if (s[1] == 'w'
834 && ! isvar (&opP->disp)
835 && (opP->disp.exp.X_op != O_constant
836 || ! isword (opP->disp.exp.X_add_number)))
837 losing++;
838 break;
839
840 case '^':
841 case 'T':
842 if (opP->mode != IMMED)
843 losing++;
844 break;
845
846 case '$':
847 if (opP->mode == AREG
848 || opP->mode == CONTROL
849 || opP->mode == FPREG
850 || opP->mode == IMMED
851 || opP->mode == REGLST
852 || (opP->mode != ABSL
853 && (opP->reg == PC
854 || opP->reg == ZPC)))
855 losing++;
856 break;
857
858 case '%':
859 if (opP->mode == CONTROL
860 || opP->mode == FPREG
861 || opP->mode == REGLST
862 || (opP->mode != ABSL
863 && opP->mode != IMMED
864 && (opP->reg == PC
865 || opP->reg == ZPC)))
866 losing++;
867 break;
868
869 case '&':
870 switch (opP->mode)
871 {
872 case DREG:
873 case AREG:
874 case FPREG:
875 case CONTROL:
876 case IMMED:
877 case AINC:
878 case ADEC:
879 case REGLST:
880 losing++;
881 break;
882 case ABSL:
883 break;
884 default:
885 if (opP->reg == PC
886 || opP->reg == ZPC)
887 losing++;
888 break;
889 }
890 break;
891
892 case '*':
893 if (opP->mode == CONTROL
894 || opP->mode == FPREG
895 || opP->mode == REGLST)
896 losing++;
897 break;
898
899 case '+':
900 if (opP->mode != AINC)
901 losing++;
902 break;
903
904 case '-':
905 if (opP->mode != ADEC)
906 losing++;
907 break;
908
909 case '/':
910 switch (opP->mode)
911 {
912 case AREG:
913 case CONTROL:
914 case FPREG:
915 case AINC:
916 case ADEC:
917 case IMMED:
918 case REGLST:
919 losing++;
920 break;
921 default:
922 break;
923 }
924 break;
925
926 case ';':
927 switch (opP->mode)
928 {
929 case AREG:
930 case CONTROL:
931 case FPREG:
932 case REGLST:
933 losing++;
934 break;
935 default:
936 break;
937 }
938 break;
939
940 case '?':
941 switch (opP->mode)
942 {
943 case AREG:
944 case CONTROL:
945 case FPREG:
946 case AINC:
947 case ADEC:
948 case IMMED:
949 case REGLST:
950 losing++;
951 break;
952 case ABSL:
953 break;
954 default:
955 if (opP->reg == PC || opP->reg == ZPC)
956 losing++;
957 break;
958 }
959 break;
960
961 case '@':
962 switch (opP->mode)
963 {
964 case AREG:
965 case CONTROL:
966 case FPREG:
967 case IMMED:
968 case REGLST:
969 losing++;
970 break;
971 default:
972 break;
973 }
974 break;
975
976 case '~': /* For now! (JF FOO is this right?) */
977 switch (opP->mode)
978 {
979 case DREG:
980 case AREG:
981 case CONTROL:
982 case FPREG:
983 case IMMED:
984 case REGLST:
985 losing++;
986 break;
987 case ABSL:
988 break;
989 default:
990 if (opP->reg == PC
991 || opP->reg == ZPC)
992 losing++;
993 break;
994 }
995 break;
996
997 case '3':
998 if (opP->mode != CONTROL
999 || (opP->reg != TT0 && opP->reg != TT1))
1000 losing++;
1001 break;
1002
1003 case 'A':
1004 if (opP->mode != AREG)
1005 losing++;
1006 break;
1007
1008 case 'a':
1009 if (opP->mode != AINDR)
1010 ++losing;
1011 break;
1012
1013 case 'B': /* FOO */
1014 if (opP->mode != ABSL
1015 || (flag_long_jumps
1016 && strncmp (instring, "jbsr", 4) == 0))
1017 losing++;
1018 break;
1019
1020 case 'C':
1021 if (opP->mode != CONTROL || opP->reg != CCR)
1022 losing++;
1023 break;
1024
1025 case 'd':
1026 if (opP->mode != DISP
1027 || opP->reg < ADDR0
1028 || opP->reg > ADDR7)
1029 losing++;
1030 break;
1031
1032 case 'D':
1033 if (opP->mode != DREG)
1034 losing++;
1035 break;
1036
1037 case 'F':
1038 if (opP->mode != FPREG)
1039 losing++;
1040 break;
1041
1042 case 'I':
1043 if (opP->mode != CONTROL
1044 || opP->reg < COP0
1045 || opP->reg > COP7)
1046 losing++;
1047 break;
1048
1049 case 'J':
1050 if (opP->mode != CONTROL
1051 || opP->reg < USP
1052 || opP->reg > last_movec_reg)
1053 losing++;
1054 else
1055 {
1056 const enum m68k_register *rp;
1057 for (rp = control_regs; *rp; rp++)
1058 if (*rp == opP->reg)
1059 break;
1060 if (*rp == 0)
1061 losing++;
1062 }
1063 break;
1064
1065 case 'k':
1066 if (opP->mode != IMMED)
1067 losing++;
1068 break;
1069
1070 case 'l':
1071 case 'L':
1072 if (opP->mode == DREG
1073 || opP->mode == AREG
1074 || opP->mode == FPREG)
1075 {
1076 if (s[1] == '8')
1077 losing++;
1078 else
1079 {
1080 switch (opP->mode)
1081 {
1082 case DREG:
1083 opP->mask = 1 << (opP->reg - DATA0);
1084 break;
1085 case AREG:
1086 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1087 break;
1088 case FPREG:
1089 opP->mask = 1 << (opP->reg - FP0 + 16);
1090 break;
1091 default:
1092 abort ();
1093 }
1094 opP->mode = REGLST;
1095 }
1096 }
1097 else if (opP->mode == CONTROL)
1098 {
1099 if (s[1] != '8')
1100 losing++;
1101 else
1102 {
1103 switch (opP->reg)
1104 {
1105 case FPI:
1106 opP->mask = 1 << 24;
1107 break;
1108 case FPS:
1109 opP->mask = 1 << 25;
1110 break;
1111 case FPC:
1112 opP->mask = 1 << 26;
1113 break;
1114 default:
1115 losing++;
1116 break;
1117 }
1118 opP->mode = REGLST;
1119 }
1120 }
1121 else if (opP->mode == ABSL
1122 && opP->disp.size == SIZE_UNSPEC
1123 && opP->disp.exp.X_op == O_constant)
1124 {
1125 /* This is what the MRI REG pseudo-op generates. */
1126 opP->mode = REGLST;
1127 opP->mask = opP->disp.exp.X_add_number;
1128 }
1129 else if (opP->mode != REGLST)
1130 losing++;
1131 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1132 losing++;
1133 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1134 losing++;
1135 break;
1136
1137 case 'M':
1138 if (opP->mode != IMMED)
1139 losing++;
1140 else if (opP->disp.exp.X_op != O_constant
1141 || ! issbyte (opP->disp.exp.X_add_number))
1142 losing++;
1143 else if (! m68k_quick
1144 && instring[3] != 'q'
1145 && instring[4] != 'q')
1146 losing++;
1147 break;
1148
1149 case 'O':
1150 if (opP->mode != DREG && opP->mode != IMMED)
1151 losing++;
1152 break;
1153
1154 case 'Q':
1155 if (opP->mode != IMMED)
1156 losing++;
1157 else if (opP->disp.exp.X_op != O_constant
1158 || opP->disp.exp.X_add_number < 1
1159 || opP->disp.exp.X_add_number > 8)
1160 losing++;
1161 else if (! m68k_quick
1162 && (strncmp (instring, "add", 3) == 0
1163 || strncmp (instring, "sub", 3) == 0)
1164 && instring[3] != 'q')
1165 losing++;
1166 break;
1167
1168 case 'R':
1169 if (opP->mode != DREG && opP->mode != AREG)
1170 losing++;
1171 break;
1172
1173 case 'r':
1174 if (opP->mode != AINDR
1175 && (opP->mode != BASE
1176 || (opP->reg != 0
1177 && opP->reg != ZADDR0)
1178 || opP->disp.exp.X_op != O_absent
1179 || ((opP->index.reg < DATA0
1180 || opP->index.reg > DATA7)
1181 && (opP->index.reg < ADDR0
1182 || opP->index.reg > ADDR7))
1183 || opP->index.size != SIZE_UNSPEC
1184 || opP->index.scale != 1))
1185 losing++;
1186 break;
1187
1188 case 's':
1189 if (opP->mode != CONTROL
1190 || ! (opP->reg == FPI
1191 || opP->reg == FPS
1192 || opP->reg == FPC))
1193 losing++;
1194 break;
1195
1196 case 'S':
1197 if (opP->mode != CONTROL || opP->reg != SR)
1198 losing++;
1199 break;
1200
1201 case 't':
1202 if (opP->mode != IMMED)
1203 losing++;
1204 else if (opP->disp.exp.X_op != O_constant
1205 || opP->disp.exp.X_add_number < 0
1206 || opP->disp.exp.X_add_number > 7)
1207 losing++;
1208 break;
1209
1210 case 'U':
1211 if (opP->mode != CONTROL || opP->reg != USP)
1212 losing++;
1213 break;
1214
1215 /* JF these are out of order. We could put them
1216 in order if we were willing to put up with
1217 bunches of #ifdef m68851s in the code.
1218
1219 Don't forget that you need these operands
1220 to use 68030 MMU instructions. */
1221 #ifndef NO_68851
1222 /* Memory addressing mode used by pflushr */
1223 case '|':
1224 if (opP->mode == CONTROL
1225 || opP->mode == FPREG
1226 || opP->mode == DREG
1227 || opP->mode == AREG
1228 || opP->mode == REGLST)
1229 losing++;
1230 break;
1231
1232 case 'f':
1233 if (opP->mode != CONTROL
1234 || (opP->reg != SFC && opP->reg != DFC))
1235 losing++;
1236 break;
1237
1238 case 'P':
1239 if (opP->mode != CONTROL
1240 || (opP->reg != TC
1241 && opP->reg != CAL
1242 && opP->reg != VAL
1243 && opP->reg != SCC
1244 && opP->reg != AC))
1245 losing++;
1246 break;
1247
1248 case 'V':
1249 if (opP->mode != CONTROL
1250 || opP->reg != VAL)
1251 losing++;
1252 break;
1253
1254 case 'W':
1255 if (opP->mode != CONTROL
1256 || (opP->reg != DRP
1257 && opP->reg != SRP
1258 && opP->reg != CRP))
1259 losing++;
1260 break;
1261
1262 case 'X':
1263 if (opP->mode != CONTROL
1264 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1265 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1266 losing++;
1267 break;
1268
1269 case 'Y':
1270 if (opP->mode != CONTROL || opP->reg != PSR)
1271 losing++;
1272 break;
1273
1274 case 'Z':
1275 if (opP->mode != CONTROL || opP->reg != PCSR)
1276 losing++;
1277 break;
1278 #endif
1279 case 'c':
1280 if (opP->mode != CONTROL
1281 || (opP->reg != NC
1282 && opP->reg != IC
1283 && opP->reg != DC
1284 && opP->reg != BC))
1285 {
1286 losing++;
1287 } /* not a cache specifier. */
1288 break;
1289
1290 case '_':
1291 if (opP->mode != ABSL)
1292 ++losing;
1293 break;
1294
1295 default:
1296 abort ();
1297 } /* switch on type of operand */
1298
1299 if (losing)
1300 break;
1301 } /* for each operand */
1302 } /* if immediately wrong */
1303
1304 if (!losing)
1305 {
1306 break;
1307 } /* got it. */
1308
1309 opcode = opcode->m_next;
1310
1311 if (!opcode)
1312 {
1313 if (ok_arch
1314 && !(ok_arch & current_architecture))
1315 {
1316 char buf[200], *cp;
1317 int len;
1318 strcpy (buf,
1319 "invalid instruction for this architecture; needs ");
1320 cp = buf + strlen (buf);
1321 switch (ok_arch)
1322 {
1323 case mfloat:
1324 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1325 break;
1326 case mmmu:
1327 strcpy (cp, "mmu (68030 or 68851)");
1328 break;
1329 case m68020up:
1330 strcpy (cp, "68020 or higher");
1331 break;
1332 case m68000up:
1333 strcpy (cp, "68000 or higher");
1334 break;
1335 case m68010up:
1336 strcpy (cp, "68010 or higher");
1337 break;
1338 default:
1339 {
1340 int got_one = 0, idx;
1341 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1342 idx++)
1343 {
1344 if (archs[idx].arch & ok_arch)
1345 {
1346 if (got_one)
1347 {
1348 strcpy (cp, " or ");
1349 cp += strlen (cp);
1350 }
1351 got_one = 1;
1352 strcpy (cp, archs[idx].name);
1353 cp += strlen (cp);
1354 }
1355 }
1356 }
1357 }
1358 len = cp - buf + 1;
1359 cp = malloc (len);
1360 strcpy (cp, buf);
1361 the_ins.error = cp;
1362 }
1363 else
1364 the_ins.error = "operands mismatch";
1365 return;
1366 } /* Fell off the end */
1367
1368 losing = 0;
1369 }
1370
1371 /* now assemble it */
1372
1373 the_ins.args = opcode->m_operands;
1374 the_ins.numargs = opcode->m_opnum;
1375 the_ins.numo = opcode->m_codenum;
1376 the_ins.opcode[0] = getone (opcode);
1377 the_ins.opcode[1] = gettwo (opcode);
1378
1379 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1380 {
1381 /* This switch is a doozy.
1382 Watch the first step; its a big one! */
1383 switch (s[0])
1384 {
1385
1386 case '*':
1387 case '~':
1388 case '%':
1389 case ';':
1390 case '@':
1391 case '!':
1392 case '&':
1393 case '$':
1394 case '?':
1395 case '/':
1396 case '`':
1397 #ifndef NO_68851
1398 case '|':
1399 #endif
1400 switch (opP->mode)
1401 {
1402 case IMMED:
1403 tmpreg = 0x3c; /* 7.4 */
1404 if (strchr ("bwl", s[1]))
1405 nextword = get_num (&opP->disp, 80);
1406 else
1407 nextword = get_num (&opP->disp, 0);
1408 if (isvar (&opP->disp))
1409 add_fix (s[1], &opP->disp, 0, 0);
1410 switch (s[1])
1411 {
1412 case 'b':
1413 if (!isbyte (nextword))
1414 opP->error = "operand out of range";
1415 addword (nextword);
1416 baseo = 0;
1417 break;
1418 case 'w':
1419 if (!isword (nextword))
1420 opP->error = "operand out of range";
1421 addword (nextword);
1422 baseo = 0;
1423 break;
1424 case 'l':
1425 addword (nextword >> 16);
1426 addword (nextword);
1427 baseo = 0;
1428 break;
1429
1430 case 'f':
1431 baseo = 2;
1432 outro = 8;
1433 break;
1434 case 'F':
1435 baseo = 4;
1436 outro = 11;
1437 break;
1438 case 'x':
1439 baseo = 6;
1440 outro = 15;
1441 break;
1442 case 'p':
1443 baseo = 6;
1444 outro = -1;
1445 break;
1446 default:
1447 abort ();
1448 }
1449 if (!baseo)
1450 break;
1451
1452 /* We gotta put out some float */
1453 if (op (&opP->disp) != O_big)
1454 {
1455 valueT val;
1456 int gencnt;
1457
1458 /* Can other cases happen here? */
1459 if (op (&opP->disp) != O_constant)
1460 abort ();
1461
1462 val = (valueT) offs (&opP->disp);
1463 gencnt = 0;
1464 do
1465 {
1466 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1467 val >>= LITTLENUM_NUMBER_OF_BITS;
1468 ++gencnt;
1469 }
1470 while (val != 0);
1471 offs (&opP->disp) = gencnt;
1472 }
1473 if (offs (&opP->disp) > 0)
1474 {
1475 if (offs (&opP->disp) > baseo)
1476 {
1477 as_warn ("Bignum too big for %c format; truncated",
1478 s[1]);
1479 offs (&opP->disp) = baseo;
1480 }
1481 baseo -= offs (&opP->disp);
1482 while (baseo--)
1483 addword (0);
1484 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1485 offs (&opP->disp)--;
1486 --wordp)
1487 addword (*wordp);
1488 break;
1489 }
1490 gen_to_words (words, baseo, (long) outro);
1491 for (wordp = words; baseo--; wordp++)
1492 addword (*wordp);
1493 break;
1494 case DREG:
1495 tmpreg = opP->reg - DATA; /* 0.dreg */
1496 break;
1497 case AREG:
1498 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1499 break;
1500 case AINDR:
1501 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1502 break;
1503 case ADEC:
1504 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1505 break;
1506 case AINC:
1507 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1508 break;
1509 case DISP:
1510
1511 nextword = get_num (&opP->disp, 80);
1512
1513 if (opP->reg == PC
1514 && ! isvar (&opP->disp)
1515 && m68k_abspcadd)
1516 {
1517 opP->disp.exp.X_op = O_symbol;
1518 #ifndef BFD_ASSEMBLER
1519 opP->disp.exp.X_add_symbol = &abs_symbol;
1520 #else
1521 opP->disp.exp.X_add_symbol =
1522 section_symbol (absolute_section);
1523 #endif
1524 }
1525
1526 /* Force into index mode. Hope this works */
1527
1528 /* We do the first bit for 32-bit displacements, and the
1529 second bit for 16 bit ones. It is possible that we
1530 should make the default be WORD instead of LONG, but
1531 I think that'd break GCC, so we put up with a little
1532 inefficiency for the sake of working output. */
1533
1534 if (!issword (nextword)
1535 || (isvar (&opP->disp)
1536 && ((opP->disp.size == SIZE_UNSPEC
1537 && flag_short_refs == 0
1538 && cpu_of_arch (current_architecture) >= m68020)
1539 || opP->disp.size == SIZE_LONG)))
1540 {
1541 if (opP->reg == PC)
1542 tmpreg = 0x3B; /* 7.3 */
1543 else
1544 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1545 if (isvar (&opP->disp))
1546 {
1547 if (opP->reg == PC)
1548 {
1549 #if 0
1550 addword (0x0170);
1551 add_fix ('l', &opP->disp, 1, 2);
1552 addword (0), addword (0);
1553 #else
1554 add_frag (adds (&opP->disp),
1555 offs (&opP->disp),
1556 TAB (PCLEA, SZ_UNDEF));
1557 #endif
1558 break;
1559 }
1560 else
1561 {
1562 addword (0x0170);
1563 add_fix ('l', &opP->disp, 0, 0);
1564 }
1565 }
1566 else
1567 addword (0x0170);
1568 addword (nextword >> 16);
1569 }
1570 else
1571 {
1572 if (opP->reg == PC)
1573 tmpreg = 0x3A; /* 7.2 */
1574 else
1575 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1576
1577 if (isvar (&opP->disp))
1578 {
1579 if (opP->reg == PC)
1580 {
1581 add_fix ('w', &opP->disp, 1, 0);
1582 }
1583 else
1584 add_fix ('w', &opP->disp, 0, 0);
1585 }
1586 }
1587 addword (nextword);
1588 break;
1589
1590 case POST:
1591 case PRE:
1592 case BASE:
1593 nextword = 0;
1594 baseo = get_num (&opP->disp, 80);
1595 if (opP->mode == POST || opP->mode == PRE)
1596 outro = get_num (&opP->odisp, 80);
1597 /* Figure out the `addressing mode'.
1598 Also turn on the BASE_DISABLE bit, if needed. */
1599 if (opP->reg == PC || opP->reg == ZPC)
1600 {
1601 tmpreg = 0x3b; /* 7.3 */
1602 if (opP->reg == ZPC)
1603 nextword |= 0x80;
1604 }
1605 else if (opP->reg == 0)
1606 {
1607 nextword |= 0x80;
1608 tmpreg = 0x30; /* 6.garbage */
1609 }
1610 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1611 {
1612 nextword |= 0x80;
1613 tmpreg = 0x30 + opP->reg - ZADDR0;
1614 }
1615 else
1616 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1617
1618 siz1 = opP->disp.size;
1619 if (opP->mode == POST || opP->mode == PRE)
1620 siz2 = opP->odisp.size;
1621 else
1622 siz2 = SIZE_UNSPEC;
1623
1624 /* Index register stuff */
1625 if (opP->index.reg != 0
1626 && opP->index.reg >= DATA
1627 && opP->index.reg <= ADDR7)
1628 {
1629 nextword |= (opP->index.reg - DATA) << 12;
1630
1631 if (opP->index.size == SIZE_UNSPEC
1632 || opP->index.size == SIZE_LONG)
1633 nextword |= 0x800;
1634
1635 if (cpu_of_arch (current_architecture) < m68020)
1636 {
1637 if (opP->index.scale != 1)
1638 {
1639 opP->error =
1640 "scale factor invalid on this architecture; needs 68020 or higher";
1641 }
1642 }
1643
1644 switch (opP->index.scale)
1645 {
1646 case 1:
1647 break;
1648 case 2:
1649 nextword |= 0x200;
1650 break;
1651 case 4:
1652 nextword |= 0x400;
1653 break;
1654 case 8:
1655 nextword |= 0x600;
1656 break;
1657 default:
1658 abort ();
1659 }
1660 /* IF its simple,
1661 GET US OUT OF HERE! */
1662
1663 /* Must be INDEX, with an index register. Address
1664 register cannot be ZERO-PC, and either :b was
1665 forced, or we know it will fit. For a 68000 or
1666 68010, force this mode anyways, because the
1667 larger modes aren't supported. */
1668 if (opP->mode == BASE
1669 && ((opP->reg >= ADDR0
1670 && opP->reg <= ADDR7)
1671 || opP->reg == PC))
1672 {
1673 if (siz1 == SIZE_BYTE
1674 || cpu_of_arch (current_architecture) < m68020
1675 || (siz1 == SIZE_UNSPEC
1676 && ! isvar (&opP->disp)
1677 && issbyte (baseo)))
1678 {
1679 nextword += baseo & 0xff;
1680 addword (nextword);
1681 if (isvar (&opP->disp))
1682 {
1683 /* Do a byte relocation. If it doesn't
1684 fit (possible on m68000) let the
1685 fixup processing complain later. */
1686 if (opP->reg == PC)
1687 add_fix ('B', &opP->disp, 1, 1);
1688 else
1689 add_fix ('B', &opP->disp, 0, 0);
1690 }
1691 else if (siz1 != SIZE_BYTE)
1692 {
1693 if (siz1 != SIZE_UNSPEC)
1694 as_warn ("Forcing byte displacement");
1695 if (! issbyte (baseo))
1696 opP->error = "byte displacement out of range";
1697 }
1698
1699 break;
1700 }
1701 else if (siz1 == SIZE_UNSPEC
1702 && opP->reg == PC
1703 && isvar (&opP->disp)
1704 && subs (&opP->disp) == NULL)
1705 {
1706 nextword += baseo & 0xff;
1707 addword (nextword);
1708 add_frag (adds (&opP->disp), offs (&opP->disp),
1709 TAB (PCINDEX, SZ_UNDEF));
1710
1711 break;
1712 }
1713 }
1714 }
1715 else
1716 {
1717 nextword |= 0x40; /* No index reg */
1718 if (opP->index.reg >= ZDATA0
1719 && opP->index.reg <= ZDATA7)
1720 nextword |= (opP->index.reg - ZDATA0) << 12;
1721 else if (opP->index.reg >= ZADDR0
1722 || opP->index.reg <= ZADDR7)
1723 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1724 }
1725
1726 /* It isn't simple. */
1727
1728 if (cpu_of_arch (current_architecture) < m68020)
1729 opP->error =
1730 "invalid operand mode for this architecture; needs 68020 or higher";
1731
1732 nextword |= 0x100;
1733 /* If the guy specified a width, we assume that it is
1734 wide enough. Maybe it isn't. If so, we lose. */
1735 switch (siz1)
1736 {
1737 case SIZE_UNSPEC:
1738 if (isvar (&opP->disp)
1739 ? m68k_rel32
1740 : ! issword (baseo))
1741 {
1742 siz1 = SIZE_LONG;
1743 nextword |= 0x30;
1744 }
1745 else if (! isvar (&opP->disp) && baseo == 0)
1746 nextword |= 0x10;
1747 else
1748 {
1749 nextword |= 0x20;
1750 siz1 = SIZE_WORD;
1751 }
1752 break;
1753 case SIZE_BYTE:
1754 as_warn (":b not permitted; defaulting to :w");
1755 /* Fall through. */
1756 case SIZE_WORD:
1757 nextword |= 0x20;
1758 break;
1759 case SIZE_LONG:
1760 nextword |= 0x30;
1761 break;
1762 }
1763
1764 /* Figure out innner displacement stuff */
1765 if (opP->mode == POST || opP->mode == PRE)
1766 {
1767 switch (siz2)
1768 {
1769 case SIZE_UNSPEC:
1770 if (isvar (&opP->odisp)
1771 ? m68k_rel32
1772 : ! issword (outro))
1773 {
1774 siz2 = SIZE_LONG;
1775 nextword |= 0x3;
1776 }
1777 else if (! isvar (&opP->odisp) && outro == 0)
1778 nextword |= 0x1;
1779 else
1780 {
1781 nextword |= 0x2;
1782 siz2 = SIZE_WORD;
1783 }
1784 break;
1785 case 1:
1786 as_warn (":b not permitted; defaulting to :w");
1787 /* Fall through. */
1788 case 2:
1789 nextword |= 0x2;
1790 break;
1791 case 3:
1792 nextword |= 0x3;
1793 break;
1794 }
1795 if (opP->mode == POST
1796 && (nextword & 0x40) == 0)
1797 nextword |= 0x04;
1798 }
1799 addword (nextword);
1800
1801 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1802 {
1803 if (opP->reg == PC || opP->reg == ZPC)
1804 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1805 else
1806 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1807 }
1808 if (siz1 == SIZE_LONG)
1809 addword (baseo >> 16);
1810 if (siz1 != SIZE_UNSPEC)
1811 addword (baseo);
1812
1813 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1814 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1815 if (siz2 == SIZE_LONG)
1816 addword (outro >> 16);
1817 if (siz2 != SIZE_UNSPEC)
1818 addword (outro);
1819
1820 break;
1821
1822 case ABSL:
1823 nextword = get_num (&opP->disp, 80);
1824 switch (opP->disp.size)
1825 {
1826 default:
1827 abort ();
1828 case SIZE_UNSPEC:
1829 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1830 {
1831 tmpreg = 0x38; /* 7.0 */
1832 addword (nextword);
1833 break;
1834 }
1835 /* Don't generate pc relative code on 68010 and
1836 68000. */
1837 if (isvar (&opP->disp)
1838 && !subs (&opP->disp)
1839 && adds (&opP->disp)
1840 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
1841 && cpu_of_arch (current_architecture) >= m68020
1842 && !flag_long_jumps
1843 && !strchr ("~%&$?", s[0]))
1844 {
1845 tmpreg = 0x3A; /* 7.2 */
1846 add_frag (adds (&opP->disp),
1847 offs (&opP->disp),
1848 TAB (PCREL, SZ_UNDEF));
1849 break;
1850 }
1851 /* Fall through into long */
1852 case SIZE_LONG:
1853 if (isvar (&opP->disp))
1854 add_fix ('l', &opP->disp, 0, 0);
1855
1856 tmpreg = 0x39;/* 7.1 mode */
1857 addword (nextword >> 16);
1858 addword (nextword);
1859 break;
1860
1861 case SIZE_WORD: /* Word */
1862 if (isvar (&opP->disp))
1863 add_fix ('w', &opP->disp, 0, 0);
1864
1865 tmpreg = 0x38;/* 7.0 mode */
1866 addword (nextword);
1867 break;
1868 }
1869 break;
1870 case CONTROL:
1871 case FPREG:
1872 default:
1873 as_bad ("unknown/incorrect operand");
1874 /* abort(); */
1875 }
1876 install_gen_operand (s[1], tmpreg);
1877 break;
1878
1879 case '#':
1880 case '^':
1881 switch (s[1])
1882 { /* JF: I hate floating point! */
1883 case 'j':
1884 tmpreg = 70;
1885 break;
1886 case '8':
1887 tmpreg = 20;
1888 break;
1889 case 'C':
1890 tmpreg = 50;
1891 break;
1892 case '3':
1893 default:
1894 tmpreg = 80;
1895 break;
1896 }
1897 tmpreg = get_num (&opP->disp, tmpreg);
1898 if (isvar (&opP->disp))
1899 add_fix (s[1], &opP->disp, 0, 0);
1900 switch (s[1])
1901 {
1902 case 'b': /* Danger: These do no check for
1903 certain types of overflow.
1904 user beware! */
1905 if (!isbyte (tmpreg))
1906 opP->error = "out of range";
1907 insop (tmpreg, opcode);
1908 if (isvar (&opP->disp))
1909 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1910 break;
1911 case 'w':
1912 if (!isword (tmpreg))
1913 opP->error = "out of range";
1914 insop (tmpreg, opcode);
1915 if (isvar (&opP->disp))
1916 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1917 break;
1918 case 'l':
1919 /* Because of the way insop works, we put these two out
1920 backwards. */
1921 insop (tmpreg, opcode);
1922 insop (tmpreg >> 16, opcode);
1923 if (isvar (&opP->disp))
1924 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1925 break;
1926 case '3':
1927 tmpreg &= 0xFF;
1928 case '8':
1929 case 'C':
1930 install_operand (s[1], tmpreg);
1931 break;
1932 default:
1933 abort ();
1934 }
1935 break;
1936
1937 case '+':
1938 case '-':
1939 case 'A':
1940 case 'a':
1941 install_operand (s[1], opP->reg - ADDR);
1942 break;
1943
1944 case 'B':
1945 tmpreg = get_num (&opP->disp, 80);
1946 switch (s[1])
1947 {
1948 case 'B':
1949 /* The pc_fix argument winds up in fx_pcrel_adjust,
1950 which is a char, and may therefore be unsigned. We
1951 want to pass -1, but we pass 64 instead, and convert
1952 back in md_pcrel_from. */
1953 add_fix ('B', &opP->disp, 1, 64);
1954 break;
1955 case 'W':
1956 add_fix ('w', &opP->disp, 1, 0);
1957 addword (0);
1958 break;
1959 case 'L':
1960 long_branch:
1961 if (cpu_of_arch (current_architecture) < m68020)
1962 as_warn ("Can't use long branches on 68000/68010");
1963 the_ins.opcode[the_ins.numo - 1] |= 0xff;
1964 add_fix ('l', &opP->disp, 1, 0);
1965 addword (0);
1966 addword (0);
1967 break;
1968 case 'g':
1969 if (subs (&opP->disp)) /* We can't relax it */
1970 goto long_branch;
1971
1972 /* This could either be a symbol, or an absolute
1973 address. No matter, the frag hacking will finger it
1974 out. Not quite: it can't switch from BRANCH to
1975 BCC68000 for the case where opnd is absolute (it
1976 needs to use the 68000 hack since no conditional abs
1977 jumps). */
1978 if (((cpu_of_arch (current_architecture) < m68020)
1979 || (0 == adds (&opP->disp)))
1980 && (the_ins.opcode[0] >= 0x6200)
1981 && (the_ins.opcode[0] <= 0x6f00))
1982 add_frag (adds (&opP->disp), offs (&opP->disp),
1983 TAB (BCC68000, SZ_UNDEF));
1984 else
1985 add_frag (adds (&opP->disp), offs (&opP->disp),
1986 TAB (ABRANCH, SZ_UNDEF));
1987 break;
1988 case 'w':
1989 if (isvar (&opP->disp))
1990 {
1991 #if 1
1992 /* check for DBcc instruction */
1993 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1994 {
1995 /* size varies if patch */
1996 /* needed for long form */
1997 add_frag (adds (&opP->disp), offs (&opP->disp),
1998 TAB (DBCC, SZ_UNDEF));
1999 break;
2000 }
2001 #endif
2002 add_fix ('w', &opP->disp, 1, 0);
2003 }
2004 addword (0);
2005 break;
2006 case 'C': /* Fixed size LONG coproc branches */
2007 add_fix ('l', &opP->disp, 1, 0);
2008 addword (0);
2009 addword (0);
2010 break;
2011 case 'c': /* Var size Coprocesssor branches */
2012 if (subs (&opP->disp))
2013 {
2014 add_fix ('l', &opP->disp, 1, 0);
2015 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2016 }
2017 else if (adds (&opP->disp))
2018 add_frag (adds (&opP->disp), offs (&opP->disp),
2019 TAB (FBRANCH, SZ_UNDEF));
2020 else
2021 {
2022 /* add_frag((symbolS *) 0, offs(&opP->disp),
2023 TAB(FBRANCH,SHORT)); */
2024 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2025 add_fix ('l', &opP->disp, 1, 0);
2026 addword (0);
2027 addword (0);
2028 }
2029 break;
2030 default:
2031 abort ();
2032 }
2033 break;
2034
2035 case 'C': /* Ignore it */
2036 break;
2037
2038 case 'd': /* JF this is a kludge */
2039 install_operand ('s', opP->reg - ADDR);
2040 tmpreg = get_num (&opP->disp, 80);
2041 if (!issword (tmpreg))
2042 {
2043 as_warn ("Expression out of range, using 0");
2044 tmpreg = 0;
2045 }
2046 addword (tmpreg);
2047 break;
2048
2049 case 'D':
2050 install_operand (s[1], opP->reg - DATA);
2051 break;
2052
2053 case 'F':
2054 install_operand (s[1], opP->reg - FP0);
2055 break;
2056
2057 case 'I':
2058 tmpreg = opP->reg - COP0;
2059 install_operand (s[1], tmpreg);
2060 break;
2061
2062 case 'J': /* JF foo */
2063 switch (opP->reg)
2064 {
2065 case SFC:
2066 tmpreg = 0x000;
2067 break;
2068 case DFC:
2069 tmpreg = 0x001;
2070 break;
2071 case CACR:
2072 tmpreg = 0x002;
2073 break;
2074 case TC:
2075 tmpreg = 0x003;
2076 break;
2077 case ITT0:
2078 tmpreg = 0x004;
2079 break;
2080 case ITT1:
2081 tmpreg = 0x005;
2082 break;
2083 case DTT0:
2084 tmpreg = 0x006;
2085 break;
2086 case DTT1:
2087 tmpreg = 0x007;
2088 break;
2089 case BUSCR:
2090 tmpreg = 0x008;
2091 break;
2092
2093 case USP:
2094 tmpreg = 0x800;
2095 break;
2096 case VBR:
2097 tmpreg = 0x801;
2098 break;
2099 case CAAR:
2100 tmpreg = 0x802;
2101 break;
2102 case MSP:
2103 tmpreg = 0x803;
2104 break;
2105 case ISP:
2106 tmpreg = 0x804;
2107 break;
2108 case MMUSR:
2109 tmpreg = 0x805;
2110 break;
2111 case URP:
2112 tmpreg = 0x806;
2113 break;
2114 case SRP:
2115 tmpreg = 0x807;
2116 break;
2117 case PCR:
2118 tmpreg = 0x808;
2119 break;
2120 default:
2121 abort ();
2122 }
2123 install_operand (s[1], tmpreg);
2124 break;
2125
2126 case 'k':
2127 tmpreg = get_num (&opP->disp, 55);
2128 install_operand (s[1], tmpreg & 0x7f);
2129 break;
2130
2131 case 'l':
2132 tmpreg = opP->mask;
2133 if (s[1] == 'w')
2134 {
2135 if (tmpreg & 0x7FF0000)
2136 as_bad ("Floating point register in register list");
2137 insop (reverse_16_bits (tmpreg), opcode);
2138 }
2139 else
2140 {
2141 if (tmpreg & 0x700FFFF)
2142 as_bad ("Wrong register in floating-point reglist");
2143 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2144 }
2145 break;
2146
2147 case 'L':
2148 tmpreg = opP->mask;
2149 if (s[1] == 'w')
2150 {
2151 if (tmpreg & 0x7FF0000)
2152 as_bad ("Floating point register in register list");
2153 insop (tmpreg, opcode);
2154 }
2155 else if (s[1] == '8')
2156 {
2157 if (tmpreg & 0x0FFFFFF)
2158 as_bad ("incorrect register in reglist");
2159 install_operand (s[1], tmpreg >> 24);
2160 }
2161 else
2162 {
2163 if (tmpreg & 0x700FFFF)
2164 as_bad ("wrong register in floating-point reglist");
2165 else
2166 install_operand (s[1], tmpreg >> 16);
2167 }
2168 break;
2169
2170 case 'M':
2171 install_operand (s[1], get_num (&opP->disp, 60));
2172 break;
2173
2174 case 'O':
2175 tmpreg = ((opP->mode == DREG)
2176 ? 0x20 + opP->reg - DATA
2177 : (get_num (&opP->disp, 40) & 0x1F));
2178 install_operand (s[1], tmpreg);
2179 break;
2180
2181 case 'Q':
2182 tmpreg = get_num (&opP->disp, 10);
2183 if (tmpreg == 8)
2184 tmpreg = 0;
2185 install_operand (s[1], tmpreg);
2186 break;
2187
2188 case 'R':
2189 /* This depends on the fact that ADDR registers are eight
2190 more than their corresponding DATA regs, so the result
2191 will have the ADDR_REG bit set */
2192 install_operand (s[1], opP->reg - DATA);
2193 break;
2194
2195 case 'r':
2196 if (opP->mode == AINDR)
2197 install_operand (s[1], opP->reg - DATA);
2198 else
2199 install_operand (s[1], opP->index.reg - DATA);
2200 break;
2201
2202 case 's':
2203 if (opP->reg == FPI)
2204 tmpreg = 0x1;
2205 else if (opP->reg == FPS)
2206 tmpreg = 0x2;
2207 else if (opP->reg == FPC)
2208 tmpreg = 0x4;
2209 else
2210 abort ();
2211 install_operand (s[1], tmpreg);
2212 break;
2213
2214 case 'S': /* Ignore it */
2215 break;
2216
2217 case 'T':
2218 install_operand (s[1], get_num (&opP->disp, 30));
2219 break;
2220
2221 case 'U': /* Ignore it */
2222 break;
2223
2224 case 'c':
2225 switch (opP->reg)
2226 {
2227 case NC:
2228 tmpreg = 0;
2229 break;
2230 case DC:
2231 tmpreg = 1;
2232 break;
2233 case IC:
2234 tmpreg = 2;
2235 break;
2236 case BC:
2237 tmpreg = 3;
2238 break;
2239 default:
2240 as_fatal ("failed sanity check");
2241 } /* switch on cache token */
2242 install_operand (s[1], tmpreg);
2243 break;
2244 #ifndef NO_68851
2245 /* JF: These are out of order, I fear. */
2246 case 'f':
2247 switch (opP->reg)
2248 {
2249 case SFC:
2250 tmpreg = 0;
2251 break;
2252 case DFC:
2253 tmpreg = 1;
2254 break;
2255 default:
2256 abort ();
2257 }
2258 install_operand (s[1], tmpreg);
2259 break;
2260
2261 case 'P':
2262 switch (opP->reg)
2263 {
2264 case TC:
2265 tmpreg = 0;
2266 break;
2267 case CAL:
2268 tmpreg = 4;
2269 break;
2270 case VAL:
2271 tmpreg = 5;
2272 break;
2273 case SCC:
2274 tmpreg = 6;
2275 break;
2276 case AC:
2277 tmpreg = 7;
2278 break;
2279 default:
2280 abort ();
2281 }
2282 install_operand (s[1], tmpreg);
2283 break;
2284
2285 case 'V':
2286 if (opP->reg == VAL)
2287 break;
2288 abort ();
2289
2290 case 'W':
2291 switch (opP->reg)
2292 {
2293 case DRP:
2294 tmpreg = 1;
2295 break;
2296 case SRP:
2297 tmpreg = 2;
2298 break;
2299 case CRP:
2300 tmpreg = 3;
2301 break;
2302 default:
2303 abort ();
2304 }
2305 install_operand (s[1], tmpreg);
2306 break;
2307
2308 case 'X':
2309 switch (opP->reg)
2310 {
2311 case BAD:
2312 case BAD + 1:
2313 case BAD + 2:
2314 case BAD + 3:
2315 case BAD + 4:
2316 case BAD + 5:
2317 case BAD + 6:
2318 case BAD + 7:
2319 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2320 break;
2321
2322 case BAC:
2323 case BAC + 1:
2324 case BAC + 2:
2325 case BAC + 3:
2326 case BAC + 4:
2327 case BAC + 5:
2328 case BAC + 6:
2329 case BAC + 7:
2330 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2331 break;
2332
2333 default:
2334 abort ();
2335 }
2336 install_operand (s[1], tmpreg);
2337 break;
2338 case 'Y':
2339 know (opP->reg == PSR);
2340 break;
2341 case 'Z':
2342 know (opP->reg == PCSR);
2343 break;
2344 #endif /* m68851 */
2345 case '3':
2346 switch (opP->reg)
2347 {
2348 case TT0:
2349 tmpreg = 2;
2350 break;
2351 case TT1:
2352 tmpreg = 3;
2353 break;
2354 default:
2355 abort ();
2356 }
2357 install_operand (s[1], tmpreg);
2358 break;
2359 case 't':
2360 tmpreg = get_num (&opP->disp, 20);
2361 install_operand (s[1], tmpreg);
2362 break;
2363 case '_': /* used only for move16 absolute 32-bit address */
2364 tmpreg = get_num (&opP->disp, 80);
2365 addword (tmpreg >> 16);
2366 addword (tmpreg & 0xFFFF);
2367 break;
2368 default:
2369 abort ();
2370 }
2371 }
2372
2373 /* By the time whe get here (FINALLY) the_ins contains the complete
2374 instruction, ready to be emitted. . . */
2375 }
2376
2377 static int
2378 reverse_16_bits (in)
2379 int in;
2380 {
2381 int out = 0;
2382 int n;
2383
2384 static int mask[16] =
2385 {
2386 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2387 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2388 };
2389 for (n = 0; n < 16; n++)
2390 {
2391 if (in & mask[n])
2392 out |= mask[15 - n];
2393 }
2394 return out;
2395 } /* reverse_16_bits() */
2396
2397 static int
2398 reverse_8_bits (in)
2399 int in;
2400 {
2401 int out = 0;
2402 int n;
2403
2404 static int mask[8] =
2405 {
2406 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2407 };
2408
2409 for (n = 0; n < 8; n++)
2410 {
2411 if (in & mask[n])
2412 out |= mask[7 - n];
2413 }
2414 return out;
2415 } /* reverse_8_bits() */
2416
2417 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2418 (that value is chosen in the frag_var call in md_assemble). TYPE
2419 is the subtype of the frag to be generated; its primary type is
2420 rs_machine_dependent.
2421
2422 The TYPE parameter is also used by md_convert_frag_1 and
2423 md_estimate_size_before_relax. The appropriate type of fixup will
2424 be emitted by md_convert_frag_1.
2425
2426 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2427 static void
2428 install_operand (mode, val)
2429 int mode;
2430 int val;
2431 {
2432 switch (mode)
2433 {
2434 case 's':
2435 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2436 break;
2437 case 'd':
2438 the_ins.opcode[0] |= val << 9;
2439 break;
2440 case '1':
2441 the_ins.opcode[1] |= val << 12;
2442 break;
2443 case '2':
2444 the_ins.opcode[1] |= val << 6;
2445 break;
2446 case '3':
2447 the_ins.opcode[1] |= val;
2448 break;
2449 case '4':
2450 the_ins.opcode[2] |= val << 12;
2451 break;
2452 case '5':
2453 the_ins.opcode[2] |= val << 6;
2454 break;
2455 case '6':
2456 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2457 three words long! */
2458 the_ins.numo++;
2459 the_ins.opcode[2] |= val;
2460 break;
2461 case '7':
2462 the_ins.opcode[1] |= val << 7;
2463 break;
2464 case '8':
2465 the_ins.opcode[1] |= val << 10;
2466 break;
2467 #ifndef NO_68851
2468 case '9':
2469 the_ins.opcode[1] |= val << 5;
2470 break;
2471 #endif
2472
2473 case 't':
2474 the_ins.opcode[1] |= (val << 10) | (val << 7);
2475 break;
2476 case 'D':
2477 the_ins.opcode[1] |= (val << 12) | val;
2478 break;
2479 case 'g':
2480 the_ins.opcode[0] |= val = 0xff;
2481 break;
2482 case 'i':
2483 the_ins.opcode[0] |= val << 9;
2484 break;
2485 case 'C':
2486 the_ins.opcode[1] |= val;
2487 break;
2488 case 'j':
2489 the_ins.opcode[1] |= val;
2490 the_ins.numo++; /* What a hack */
2491 break;
2492 case 'k':
2493 the_ins.opcode[1] |= val << 4;
2494 break;
2495 case 'b':
2496 case 'w':
2497 case 'l':
2498 break;
2499 case 'e':
2500 the_ins.opcode[0] |= (val << 6);
2501 break;
2502 case 'L':
2503 the_ins.opcode[1] = (val >> 16);
2504 the_ins.opcode[2] = val & 0xffff;
2505 break;
2506 case 'c':
2507 default:
2508 as_fatal ("failed sanity check.");
2509 }
2510 } /* install_operand() */
2511
2512 static void
2513 install_gen_operand (mode, val)
2514 int mode;
2515 int val;
2516 {
2517 switch (mode)
2518 {
2519 case 's':
2520 the_ins.opcode[0] |= val;
2521 break;
2522 case 'd':
2523 /* This is a kludge!!! */
2524 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2525 break;
2526 case 'b':
2527 case 'w':
2528 case 'l':
2529 case 'f':
2530 case 'F':
2531 case 'x':
2532 case 'p':
2533 the_ins.opcode[0] |= val;
2534 break;
2535 /* more stuff goes here */
2536 default:
2537 as_fatal ("failed sanity check.");
2538 }
2539 } /* install_gen_operand() */
2540
2541 /*
2542 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2543 * then deal with the bitfield hack.
2544 */
2545
2546 static char *
2547 crack_operand (str, opP)
2548 register char *str;
2549 register struct m68k_op *opP;
2550 {
2551 register int parens;
2552 register int c;
2553 register char *beg_str;
2554 int inquote = 0;
2555
2556 if (!str)
2557 {
2558 return str;
2559 }
2560 beg_str = str;
2561 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2562 {
2563 if (! inquote)
2564 {
2565 if (*str == '(')
2566 parens++;
2567 else if (*str == ')')
2568 {
2569 if (!parens)
2570 { /* ERROR */
2571 opP->error = "Extra )";
2572 return str;
2573 }
2574 --parens;
2575 }
2576 }
2577 if (flag_mri && *str == '\'')
2578 inquote = ! inquote;
2579 }
2580 if (!*str && parens)
2581 { /* ERROR */
2582 opP->error = "Missing )";
2583 return str;
2584 }
2585 c = *str;
2586 *str = '\0';
2587 if (m68k_ip_op (beg_str, opP) != 0)
2588 {
2589 *str = c;
2590 return str;
2591 }
2592 *str = c;
2593 if (c == '}')
2594 c = *++str; /* JF bitfield hack */
2595 if (c)
2596 {
2597 c = *++str;
2598 if (!c)
2599 as_bad ("Missing operand");
2600 }
2601 return str;
2602 }
2603
2604 /* This is the guts of the machine-dependent assembler. STR points to a
2605 machine dependent instruction. This function is supposed to emit
2606 the frags/bytes it assembles to.
2607 */
2608
2609 void
2610 insert_reg (regname, regnum)
2611 char *regname;
2612 int regnum;
2613 {
2614 char buf[100];
2615 int i;
2616
2617 #ifdef REGISTER_PREFIX
2618 if (!flag_reg_prefix_optional)
2619 {
2620 buf[0] = REGISTER_PREFIX;
2621 strcpy (buf + 1, regname);
2622 regname = buf;
2623 }
2624 #endif
2625
2626 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2627 &zero_address_frag));
2628
2629 for (i = 0; regname[i]; i++)
2630 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2631 buf[i] = '\0';
2632
2633 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2634 &zero_address_frag));
2635 }
2636
2637 struct init_entry
2638 {
2639 const char *name;
2640 int number;
2641 };
2642
2643 static const struct init_entry init_table[] =
2644 {
2645 { "d0", DATA0 },
2646 { "d1", DATA1 },
2647 { "d2", DATA2 },
2648 { "d3", DATA3 },
2649 { "d4", DATA4 },
2650 { "d5", DATA5 },
2651 { "d6", DATA6 },
2652 { "d7", DATA7 },
2653 { "a0", ADDR0 },
2654 { "a1", ADDR1 },
2655 { "a2", ADDR2 },
2656 { "a3", ADDR3 },
2657 { "a4", ADDR4 },
2658 { "a5", ADDR5 },
2659 { "a6", ADDR6 },
2660 { "fp", ADDR6 },
2661 { "a7", ADDR7 },
2662 { "sp", ADDR7 },
2663 { "ssp", ADDR7 },
2664 { "fp0", FP0 },
2665 { "fp1", FP1 },
2666 { "fp2", FP2 },
2667 { "fp3", FP3 },
2668 { "fp4", FP4 },
2669 { "fp5", FP5 },
2670 { "fp6", FP6 },
2671 { "fp7", FP7 },
2672 { "fpi", FPI },
2673 { "fpiar", FPI },
2674 { "fpc", FPI },
2675 { "fps", FPS },
2676 { "fpsr", FPS },
2677 { "fpc", FPC },
2678 { "fpcr", FPC },
2679 { "control", FPC },
2680 { "status", FPS },
2681 { "iaddr", FPI },
2682
2683 { "cop0", COP0 },
2684 { "cop1", COP1 },
2685 { "cop2", COP2 },
2686 { "cop3", COP3 },
2687 { "cop4", COP4 },
2688 { "cop5", COP5 },
2689 { "cop6", COP6 },
2690 { "cop7", COP7 },
2691 { "pc", PC },
2692 { "zpc", ZPC },
2693 { "sr", SR },
2694
2695 { "ccr", CCR },
2696 { "cc", CCR },
2697
2698 { "usp", USP },
2699 { "isp", ISP },
2700 { "sfc", SFC },
2701 { "sfcr", SFC },
2702 { "dfc", DFC },
2703 { "dfcr", DFC },
2704 { "cacr", CACR },
2705 { "caar", CAAR },
2706
2707 { "vbr", VBR },
2708
2709 { "msp", MSP },
2710 { "itt0", ITT0 },
2711 { "itt1", ITT1 },
2712 { "dtt0", DTT0 },
2713 { "dtt1", DTT1 },
2714 { "mmusr", MMUSR },
2715 { "tc", TC },
2716 { "srp", SRP },
2717 { "urp", URP },
2718 { "buscr", BUSCR },
2719 { "pcr", PCR },
2720
2721 { "ac", AC },
2722 { "bc", BC },
2723 { "cal", CAL },
2724 { "crp", CRP },
2725 { "drp", DRP },
2726 { "pcsr", PCSR },
2727 { "psr", PSR },
2728 { "scc", SCC },
2729 { "val", VAL },
2730 { "bad0", BAD0 },
2731 { "bad1", BAD1 },
2732 { "bad2", BAD2 },
2733 { "bad3", BAD3 },
2734 { "bad4", BAD4 },
2735 { "bad5", BAD5 },
2736 { "bad6", BAD6 },
2737 { "bad7", BAD7 },
2738 { "bac0", BAC0 },
2739 { "bac1", BAC1 },
2740 { "bac2", BAC2 },
2741 { "bac3", BAC3 },
2742 { "bac4", BAC4 },
2743 { "bac5", BAC5 },
2744 { "bac6", BAC6 },
2745 { "bac7", BAC7 },
2746
2747 { "ic", IC },
2748 { "dc", DC },
2749 { "nc", NC },
2750
2751 { "tt0", TT0 },
2752 { "tt1", TT1 },
2753 /* 68ec030 versions of same */
2754 { "ac0", TT0 },
2755 { "ac1", TT1 },
2756 /* 68ec030 access control unit, identical to 030 MMU status reg */
2757 { "acusr", PSR },
2758
2759 /* Suppressed data and address registers. */
2760 { "zd0", ZDATA0 },
2761 { "zd1", ZDATA1 },
2762 { "zd2", ZDATA2 },
2763 { "zd3", ZDATA3 },
2764 { "zd4", ZDATA4 },
2765 { "zd5", ZDATA5 },
2766 { "zd6", ZDATA6 },
2767 { "zd7", ZDATA7 },
2768 { "za0", ZADDR0 },
2769 { "za1", ZADDR1 },
2770 { "za2", ZADDR2 },
2771 { "za3", ZADDR3 },
2772 { "za4", ZADDR4 },
2773 { "za5", ZADDR5 },
2774 { "za6", ZADDR6 },
2775 { "za7", ZADDR7 },
2776
2777 { 0, 0 }
2778 };
2779
2780 void
2781 init_regtable ()
2782 {
2783 int i;
2784 for (i = 0; init_table[i].name; i++)
2785 insert_reg (init_table[i].name, init_table[i].number);
2786 }
2787
2788 static int no_68851, no_68881;
2789
2790 #ifdef OBJ_AOUT
2791 /* a.out machine type. Default to 68020. */
2792 int m68k_aout_machtype = 2;
2793 #endif
2794
2795 void
2796 md_assemble (str)
2797 char *str;
2798 {
2799 const char *er;
2800 short *fromP;
2801 char *toP = NULL;
2802 int m, n = 0;
2803 char *to_beg_P;
2804 int shorts_this_frag;
2805 fixS *fixP;
2806
2807 /* In MRI mode, the instruction and operands are separated by a
2808 space. Anything following the operands is a comment. The label
2809 has already been removed. */
2810 if (flag_mri)
2811 {
2812 char *s;
2813 int fields = 0;
2814 int infield = 0;
2815 int inquote = 0;
2816
2817 for (s = str; *s != '\0'; s++)
2818 {
2819 if ((*s == ' ' || *s == '\t') && ! inquote)
2820 {
2821 if (infield)
2822 {
2823 ++fields;
2824 if (fields >= 2)
2825 {
2826 *s = '\0';
2827 break;
2828 }
2829 infield = 0;
2830 }
2831 }
2832 else
2833 {
2834 if (! infield)
2835 infield = 1;
2836 if (*s == '\'')
2837 inquote = ! inquote;
2838 }
2839 }
2840 }
2841
2842 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2843 m68k_ip (str);
2844 er = the_ins.error;
2845 if (!er)
2846 {
2847 for (n = 0; n < the_ins.numargs; n++)
2848 if (the_ins.operands[n].error)
2849 {
2850 er = the_ins.operands[n].error;
2851 break;
2852 }
2853 }
2854 if (er)
2855 {
2856 as_bad ("%s -- statement `%s' ignored", er, str);
2857 return;
2858 }
2859
2860 if (the_ins.nfrag == 0)
2861 {
2862 /* No frag hacking involved; just put it out */
2863 toP = frag_more (2 * the_ins.numo);
2864 fromP = &the_ins.opcode[0];
2865 for (m = the_ins.numo; m; --m)
2866 {
2867 md_number_to_chars (toP, (long) (*fromP), 2);
2868 toP += 2;
2869 fromP++;
2870 }
2871 /* put out symbol-dependent info */
2872 for (m = 0; m < the_ins.nrel; m++)
2873 {
2874 switch (the_ins.reloc[m].wid)
2875 {
2876 case 'B':
2877 n = 1;
2878 break;
2879 case 'b':
2880 n = 1;
2881 break;
2882 case '3':
2883 n = 2;
2884 break;
2885 case 'w':
2886 n = 2;
2887 break;
2888 case 'l':
2889 n = 4;
2890 break;
2891 default:
2892 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2893 the_ins.reloc[m].wid);
2894 }
2895
2896 fixP = fix_new_exp (frag_now,
2897 ((toP - frag_now->fr_literal)
2898 - the_ins.numo * 2 + the_ins.reloc[m].n),
2899 n,
2900 &the_ins.reloc[m].exp,
2901 the_ins.reloc[m].pcrel,
2902 NO_RELOC);
2903 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2904 }
2905 return;
2906 }
2907
2908 /* There's some frag hacking */
2909 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2910 {
2911 int wid;
2912
2913 if (n == 0)
2914 wid = 2 * the_ins.fragb[n].fragoff;
2915 else
2916 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2917 toP = frag_more (wid);
2918 to_beg_P = toP;
2919 shorts_this_frag = 0;
2920 for (m = wid / 2; m; --m)
2921 {
2922 md_number_to_chars (toP, (long) (*fromP), 2);
2923 toP += 2;
2924 fromP++;
2925 shorts_this_frag++;
2926 }
2927 for (m = 0; m < the_ins.nrel; m++)
2928 {
2929 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2930 {
2931 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2932 break;
2933 }
2934 wid = the_ins.reloc[m].wid;
2935 if (wid == 0)
2936 continue;
2937 the_ins.reloc[m].wid = 0;
2938 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2939
2940 fixP = fix_new_exp (frag_now,
2941 ((toP - frag_now->fr_literal)
2942 - the_ins.numo * 2 + the_ins.reloc[m].n),
2943 wid,
2944 &the_ins.reloc[m].exp,
2945 the_ins.reloc[m].pcrel,
2946 NO_RELOC);
2947 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2948 }
2949 (void) frag_var (rs_machine_dependent, 10, 0,
2950 (relax_substateT) (the_ins.fragb[n].fragty),
2951 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2952 }
2953 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2954 shorts_this_frag = 0;
2955 if (n)
2956 {
2957 toP = frag_more (n * sizeof (short));
2958 while (n--)
2959 {
2960 md_number_to_chars (toP, (long) (*fromP), 2);
2961 toP += 2;
2962 fromP++;
2963 shorts_this_frag++;
2964 }
2965 }
2966 for (m = 0; m < the_ins.nrel; m++)
2967 {
2968 int wid;
2969
2970 wid = the_ins.reloc[m].wid;
2971 if (wid == 0)
2972 continue;
2973 the_ins.reloc[m].wid = 0;
2974 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2975
2976 fixP = fix_new_exp (frag_now,
2977 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2978 - shorts_this_frag * 2),
2979 wid,
2980 &the_ins.reloc[m].exp,
2981 the_ins.reloc[m].pcrel,
2982 NO_RELOC);
2983 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2984 }
2985 }
2986
2987 void
2988 md_begin ()
2989 {
2990 /*
2991 * md_begin -- set up hash tables with 68000 instructions.
2992 * similar to what the vax assembler does. ---phr
2993 */
2994 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2995 a copy of it at runtime, adding in the information we want but isn't
2996 there. I think it'd be better to have an awk script hack the table
2997 at compile time. Or even just xstr the table and use it as-is. But
2998 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2999 names. */
3000
3001 register const struct m68k_opcode *ins;
3002 register struct m68k_incant *hack, *slak;
3003 register const char *retval = 0; /* empty string, or error msg text */
3004 register unsigned int i;
3005 register char c;
3006
3007 if (flag_mri)
3008 {
3009 flag_reg_prefix_optional = 1;
3010 m68k_abspcadd = 1;
3011 m68k_rel32 = 0;
3012 }
3013
3014 op_hash = hash_new ();
3015
3016 obstack_begin (&robyn, 4000);
3017 for (i = 0; i < m68k_numopcodes; i++)
3018 {
3019 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3020 do
3021 {
3022 ins = &m68k_opcodes[i];
3023 /* We *could* ignore insns that don't match our arch here
3024 but just leaving them out of the hash. */
3025 slak->m_operands = ins->args;
3026 slak->m_opnum = strlen (slak->m_operands) / 2;
3027 slak->m_arch = ins->arch;
3028 slak->m_opcode = ins->opcode;
3029 /* This is kludgey */
3030 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3031 if (i + 1 != m68k_numopcodes
3032 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3033 {
3034 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3035 i++;
3036 }
3037 else
3038 slak->m_next = 0;
3039 slak = slak->m_next;
3040 }
3041 while (slak);
3042
3043 retval = hash_insert (op_hash, ins->name, (char *) hack);
3044 if (retval)
3045 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3046 }
3047
3048 for (i = 0; i < m68k_numaliases; i++)
3049 {
3050 const char *name = m68k_opcode_aliases[i].primary;
3051 const char *alias = m68k_opcode_aliases[i].alias;
3052 PTR val = hash_find (op_hash, name);
3053 if (!val)
3054 as_fatal ("Internal Error: Can't find %s in hash table", name);
3055 retval = hash_insert (op_hash, alias, val);
3056 if (retval)
3057 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3058 }
3059
3060 /* In MRI mode, all unsized branches are variable sized. Normally,
3061 they are word sized. */
3062 if (flag_mri)
3063 {
3064 static struct m68k_opcode_alias mri_aliases[] =
3065 {
3066 { "bhi", "jhi", },
3067 { "bls", "jls", },
3068 { "bcc", "jcc", },
3069 { "bcs", "jcs", },
3070 { "bne", "jne", },
3071 { "beq", "jeq", },
3072 { "bvc", "jvc", },
3073 { "bvs", "jvs", },
3074 { "bpl", "jpl", },
3075 { "bmi", "jmi", },
3076 { "bge", "jge", },
3077 { "blt", "jlt", },
3078 { "bgt", "jgt", },
3079 { "ble", "jle", },
3080 { "bra", "jra", },
3081 { "bsr", "jbsr", },
3082 };
3083
3084 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3085 {
3086 const char *name = mri_aliases[i].primary;
3087 const char *alias = mri_aliases[i].alias;
3088 PTR val = hash_find (op_hash, name);
3089 if (!val)
3090 as_fatal ("Internal Error: Can't find %s in hash table", name);
3091 retval = hash_jam (op_hash, alias, val);
3092 if (retval)
3093 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3094 }
3095 }
3096
3097 for (i = 0; i < sizeof (mklower_table); i++)
3098 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3099
3100 for (i = 0; i < sizeof (notend_table); i++)
3101 {
3102 notend_table[i] = 0;
3103 alt_notend_table[i] = 0;
3104 }
3105 notend_table[','] = 1;
3106 notend_table['{'] = 1;
3107 notend_table['}'] = 1;
3108 alt_notend_table['a'] = 1;
3109 alt_notend_table['A'] = 1;
3110 alt_notend_table['d'] = 1;
3111 alt_notend_table['D'] = 1;
3112 alt_notend_table['#'] = 1;
3113 alt_notend_table['&'] = 1;
3114 alt_notend_table['f'] = 1;
3115 alt_notend_table['F'] = 1;
3116 #ifdef REGISTER_PREFIX
3117 alt_notend_table[REGISTER_PREFIX] = 1;
3118 #endif
3119
3120 /* We need to put '(' in alt_notend_table to handle
3121 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3122 */
3123 alt_notend_table['('] = 1;
3124
3125 /* We need to put '@' in alt_notend_table to handle
3126 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3127 */
3128 alt_notend_table['@'] = 1;
3129
3130 #ifndef MIT_SYNTAX_ONLY
3131 /* Insert pseudo ops, these have to go into the opcode table since
3132 gas expects pseudo ops to start with a dot */
3133 {
3134 int n = 0;
3135 while (mote_pseudo_table[n].poc_name)
3136 {
3137 hack = (struct m68k_incant *)
3138 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3139 hash_insert (op_hash,
3140 mote_pseudo_table[n].poc_name, (char *) hack);
3141 hack->m_operands = 0;
3142 hack->m_opnum = n;
3143 n++;
3144 }
3145 }
3146 #endif
3147
3148 init_regtable ();
3149 }
3150
3151 void
3152 m68k_init_after_args ()
3153 {
3154 if (cpu_of_arch (current_architecture) == 0)
3155 {
3156 int i;
3157 const char *default_cpu = TARGET_CPU;
3158
3159 if (*default_cpu == 'm')
3160 default_cpu++;
3161 for (i = 0; i < n_archs; i++)
3162 if (strcasecmp (default_cpu, archs[i].name) == 0)
3163 break;
3164 if (i == n_archs)
3165 {
3166 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3167 current_architecture |= m68020;
3168 }
3169 else
3170 current_architecture |= archs[i].arch;
3171 }
3172 /* Permit m68881 specification with all cpus; those that can't work
3173 with a coprocessor could be doing emulation. */
3174 if (current_architecture & m68851)
3175 {
3176 if (current_architecture & m68040)
3177 {
3178 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3179 }
3180 }
3181 /* What other incompatibilities could we check for? */
3182
3183 /* Toss in some default assumptions about coprocessors. */
3184 if (!no_68881
3185 && (cpu_of_arch (current_architecture)
3186 /* Can CPU32 have a 68881 coprocessor?? */
3187 & (m68020 | m68030 | cpu32)))
3188 {
3189 current_architecture |= m68881;
3190 }
3191 if (!no_68851
3192 && (cpu_of_arch (current_architecture) & m68020up) != 0
3193 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3194 {
3195 current_architecture |= m68851;
3196 }
3197 if (no_68881 && (current_architecture & m68881))
3198 as_bad ("options for 68881 and no-68881 both given");
3199 if (no_68851 && (current_architecture & m68851))
3200 as_bad ("options for 68851 and no-68851 both given");
3201
3202 #ifdef OBJ_AOUT
3203 /* Work out the magic number. This isn't very general. */
3204 if (current_architecture & m68000)
3205 m68k_aout_machtype = 0;
3206 else if (current_architecture & m68010)
3207 m68k_aout_machtype = 1;
3208 else if (current_architecture & m68020)
3209 m68k_aout_machtype = 2;
3210 else
3211 m68k_aout_machtype = 2;
3212 #endif
3213
3214 /* Note which set of "movec" control registers is available. */
3215 switch (cpu_of_arch (current_architecture))
3216 {
3217 case m68000:
3218 control_regs = m68000_control_regs;
3219 break;
3220 case m68010:
3221 control_regs = m68010_control_regs;
3222 break;
3223 case m68020:
3224 case m68030:
3225 control_regs = m68020_control_regs;
3226 break;
3227 case m68040:
3228 control_regs = m68040_control_regs;
3229 break;
3230 case m68060:
3231 control_regs = m68060_control_regs;
3232 break;
3233 case cpu32:
3234 control_regs = cpu32_control_regs;
3235 break;
3236 default:
3237 abort ();
3238 }
3239
3240 if (cpu_of_arch (current_architecture) < m68020)
3241 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3242 }
3243
3244 /* Equal to MAX_PRECISION in atof-ieee.c */
3245 #define MAX_LITTLENUMS 6
3246
3247 /* Turn a string in input_line_pointer into a floating point constant
3248 of type type, and store the appropriate bytes in *litP. The number
3249 of LITTLENUMS emitted is stored in *sizeP . An error message is
3250 returned, or NULL on OK. */
3251
3252 char *
3253 md_atof (type, litP, sizeP)
3254 char type;
3255 char *litP;
3256 int *sizeP;
3257 {
3258 int prec;
3259 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3260 LITTLENUM_TYPE *wordP;
3261 char *t;
3262 char *atof_ieee ();
3263
3264 switch (type)
3265 {
3266 case 'f':
3267 case 'F':
3268 case 's':
3269 case 'S':
3270 prec = 2;
3271 break;
3272
3273 case 'd':
3274 case 'D':
3275 case 'r':
3276 case 'R':
3277 prec = 4;
3278 break;
3279
3280 case 'x':
3281 case 'X':
3282 prec = 6;
3283 break;
3284
3285 case 'p':
3286 case 'P':
3287 prec = 6;
3288 break;
3289
3290 default:
3291 *sizeP = 0;
3292 return "Bad call to MD_ATOF()";
3293 }
3294 t = atof_ieee (input_line_pointer, type, words);
3295 if (t)
3296 input_line_pointer = t;
3297
3298 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3299 for (wordP = words; prec--;)
3300 {
3301 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3302 litP += sizeof (LITTLENUM_TYPE);
3303 }
3304 return 0;
3305 }
3306
3307 void
3308 md_number_to_chars (buf, val, n)
3309 char *buf;
3310 valueT val;
3311 int n;
3312 {
3313 number_to_chars_bigendian (buf, val, n);
3314 }
3315
3316 static void
3317 md_apply_fix_2 (fixP, val)
3318 fixS *fixP;
3319 offsetT val;
3320 {
3321 addressT upper_limit;
3322 offsetT lower_limit;
3323
3324 /* This is unnecessary but it convinces the native rs6000 compiler
3325 to generate the code we want. */
3326 char *buf = fixP->fx_frag->fr_literal;
3327 buf += fixP->fx_where;
3328 /* end ibm compiler workaround */
3329
3330 if (val & 0x80000000)
3331 val |= ~(addressT)0x7fffffff;
3332 else
3333 val &= 0x7fffffff;
3334
3335 switch (fixP->fx_size)
3336 {
3337 /* The cast to offsetT below are necessary to make code correct for
3338 machines where ints are smaller than offsetT */
3339 case 1:
3340 *buf++ = val;
3341 upper_limit = 0x7f;
3342 lower_limit = - (offsetT) 0x80;
3343 break;
3344 case 2:
3345 *buf++ = (val >> 8);
3346 *buf++ = val;
3347 upper_limit = 0x7fff;
3348 lower_limit = - (offsetT) 0x8000;
3349 break;
3350 case 4:
3351 *buf++ = (val >> 24);
3352 *buf++ = (val >> 16);
3353 *buf++ = (val >> 8);
3354 *buf++ = val;
3355 upper_limit = 0x7fffffff;
3356 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3357 break;
3358 default:
3359 BAD_CASE (fixP->fx_size);
3360 }
3361
3362 /* Fix up a negative reloc. */
3363 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3364 {
3365 fixP->fx_addsy = fixP->fx_subsy;
3366 fixP->fx_subsy = NULL;
3367 fixP->fx_tcbit = 1;
3368 }
3369
3370 /* For non-pc-relative values, it's conceivable we might get something
3371 like "0xff" for a byte field. So extend the upper part of the range
3372 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3373 so that we can do any range checking at all. */
3374 if (!fixP->fx_pcrel)
3375 upper_limit = upper_limit * 2 + 1;
3376
3377 if ((addressT) val > upper_limit
3378 && (val > 0 || val < lower_limit))
3379 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3380
3381 /* A one byte PC-relative reloc means a short branch. We can't use
3382 a short branch with a value of 0 or -1, because those indicate
3383 different opcodes (branches with longer offsets). */
3384 if (fixP->fx_pcrel
3385 && fixP->fx_size == 1
3386 && (fixP->fx_addsy == NULL
3387 || S_IS_DEFINED (fixP->fx_addsy))
3388 && (val == 0 || val == -1))
3389 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3390 }
3391
3392 #ifdef BFD_ASSEMBLER
3393 int
3394 md_apply_fix (fixP, valp)
3395 fixS *fixP;
3396 valueT *valp;
3397 {
3398 md_apply_fix_2 (fixP, (addressT) *valp);
3399 return 1;
3400 }
3401 #else
3402 void md_apply_fix (fixP, val)
3403 fixS *fixP;
3404 long val;
3405 {
3406 md_apply_fix_2 (fixP, (addressT) val);
3407 }
3408 #endif
3409
3410 /* *fragP has been relaxed to its final size, and now needs to have
3411 the bytes inside it modified to conform to the new size There is UGLY
3412 MAGIC here. ..
3413 */
3414 void
3415 md_convert_frag_1 (fragP)
3416 register fragS *fragP;
3417 {
3418 long disp;
3419 long ext = 0;
3420 fixS *fixP;
3421
3422 /* Address in object code of the displacement. */
3423 register int object_address = fragP->fr_fix + fragP->fr_address;
3424
3425 /* Address in gas core of the place to store the displacement. */
3426 /* This convinces the native rs6000 compiler to generate the code we
3427 want. */
3428 register char *buffer_address = fragP->fr_literal;
3429 buffer_address += fragP->fr_fix;
3430 /* end ibm compiler workaround */
3431
3432 /* The displacement of the address, from current location. */
3433 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3434 disp = (disp + fragP->fr_offset) - object_address;
3435
3436 #ifdef BFD_ASSEMBLER
3437 disp += fragP->fr_symbol->sy_frag->fr_address;
3438 #endif
3439
3440 switch (fragP->fr_subtype)
3441 {
3442 case TAB (BCC68000, BYTE):
3443 case TAB (ABRANCH, BYTE):
3444 know (issbyte (disp));
3445 if (disp == 0)
3446 as_bad ("short branch with zero offset: use :w");
3447 fragP->fr_opcode[1] = disp;
3448 ext = 0;
3449 break;
3450 case TAB (DBCC, SHORT):
3451 know (issword (disp));
3452 ext = 2;
3453 break;
3454 case TAB (BCC68000, SHORT):
3455 case TAB (ABRANCH, SHORT):
3456 know (issword (disp));
3457 fragP->fr_opcode[1] = 0x00;
3458 ext = 2;
3459 break;
3460 case TAB (ABRANCH, LONG):
3461 if (cpu_of_arch (current_architecture) < m68020)
3462 {
3463 if (fragP->fr_opcode[0] == 0x61)
3464 /* BSR */
3465 {
3466 fragP->fr_opcode[0] = 0x4E;
3467 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3468
3469 fix_new (fragP,
3470 fragP->fr_fix,
3471 4,
3472 fragP->fr_symbol,
3473 fragP->fr_offset,
3474 0,
3475 NO_RELOC);
3476
3477 fragP->fr_fix += 4;
3478 ext = 0;
3479 }
3480 /* BRA */
3481 else if (fragP->fr_opcode[0] == 0x60)
3482 {
3483 fragP->fr_opcode[0] = 0x4E;
3484 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3485 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3486 fragP->fr_offset, 0, NO_RELOC);
3487 fragP->fr_fix += 4;
3488 ext = 0;
3489 }
3490 else
3491 {
3492 as_bad ("Long branch offset not supported.");
3493 }
3494 }
3495 else
3496 {
3497 fragP->fr_opcode[1] = (char) 0xff;
3498 ext = 4;
3499 }
3500 break;
3501 case TAB (BCC68000, LONG):
3502 /* only Bcc 68000 instructions can come here */
3503 /* change bcc into b!cc/jmp absl long */
3504 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3505 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3506
3507 /* JF: these used to be fr_opcode[2,3], but they may be in a
3508 different frag, in which case refering to them is a no-no.
3509 Only fr_opcode[0,1] are guaranteed to work. */
3510 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3511 *buffer_address++ = (char) 0xf9;
3512 fragP->fr_fix += 2; /* account for jmp instruction */
3513 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3514 fragP->fr_offset, 0, NO_RELOC);
3515 fragP->fr_fix += 4;
3516 ext = 0;
3517 break;
3518 case TAB (DBCC, LONG):
3519 /* only DBcc 68000 instructions can come here */
3520 /* change dbcc into dbcc/jmp absl long */
3521 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3522 *buffer_address++ = 0x00; /* branch offset = 4 */
3523 *buffer_address++ = 0x04;
3524 *buffer_address++ = 0x60; /* put in bra pc+6 */
3525 *buffer_address++ = 0x06;
3526 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3527 *buffer_address++ = (char) 0xf9;
3528
3529 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3530 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3531 fragP->fr_offset, 0, NO_RELOC);
3532 fragP->fr_fix += 4;
3533 ext = 0;
3534 break;
3535 case TAB (FBRANCH, SHORT):
3536 know ((fragP->fr_opcode[1] & 0x40) == 0);
3537 ext = 2;
3538 break;
3539 case TAB (FBRANCH, LONG):
3540 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3541 ext = 4;
3542 break;
3543 case TAB (PCREL, SHORT):
3544 ext = 2;
3545 break;
3546 case TAB (PCREL, LONG):
3547 /* The thing to do here is force it to ABSOLUTE LONG, since
3548 PCREL is really trying to shorten an ABSOLUTE address anyway */
3549 /* JF FOO This code has not been tested */
3550 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3551 0, NO_RELOC);
3552 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3553 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3554 (unsigned) fragP->fr_opcode[0],
3555 (unsigned long) fragP->fr_address);
3556 fragP->fr_opcode[1] &= ~0x3F;
3557 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3558 fragP->fr_fix += 4;
3559 ext = 0;
3560 break;
3561 case TAB (PCLEA, SHORT):
3562 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3563 fragP->fr_offset, 1, NO_RELOC);
3564 fragP->fr_opcode[1] &= ~0x3F;
3565 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3566 ext = 2;
3567 break;
3568 case TAB (PCLEA, LONG):
3569 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3570 fragP->fr_offset, 1, NO_RELOC);
3571 fixP->fx_pcrel_adjust = 2;
3572 /* Already set to mode 7.3; this indicates: PC indirect with
3573 suppressed index, 32-bit displacement. */
3574 *buffer_address++ = 0x01;
3575 *buffer_address++ = 0x70;
3576 fragP->fr_fix += 2;
3577 ext = 4;
3578 break;
3579
3580 case TAB (PCINDEX, BYTE):
3581 disp += 2;
3582 if (!issbyte (disp))
3583 {
3584 as_bad ("displacement doesn't fit in one byte");
3585 disp = 0;
3586 }
3587 assert (fragP->fr_fix >= 2);
3588 buffer_address[-2] &= ~1;
3589 buffer_address[-1] = disp;
3590 ext = 0;
3591 break;
3592 case TAB (PCINDEX, SHORT):
3593 disp += 2;
3594 assert (issword (disp));
3595 assert (fragP->fr_fix >= 2);
3596 buffer_address[-2] |= 0x1;
3597 buffer_address[-1] = 0x20;
3598 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3599 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3600 NO_RELOC);
3601 fixP->fx_pcrel_adjust = 2;
3602 ext = 2;
3603 break;
3604 case TAB (PCINDEX, LONG):
3605 disp += 2;
3606 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3607 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3608 NO_RELOC);
3609 fixP->fx_pcrel_adjust = 2;
3610 assert (fragP->fr_fix >= 2);
3611 buffer_address[-2] |= 0x1;
3612 buffer_address[-1] = 0x30;
3613 ext = 4;
3614 break;
3615 }
3616
3617 if (ext)
3618 {
3619 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3620 fragP->fr_fix += ext;
3621 }
3622 }
3623
3624 #ifndef BFD_ASSEMBLER
3625
3626 void
3627 md_convert_frag (headers, sec, fragP)
3628 object_headers *headers;
3629 segT sec;
3630 fragS *fragP;
3631 {
3632 md_convert_frag_1 (fragP);
3633 }
3634
3635 #else
3636
3637 void
3638 md_convert_frag (abfd, sec, fragP)
3639 bfd *abfd;
3640 segT sec;
3641 fragS *fragP;
3642 {
3643 md_convert_frag_1 (fragP);
3644 }
3645 #endif
3646
3647 /* Force truly undefined symbols to their maximum size, and generally set up
3648 the frag list to be relaxed
3649 */
3650 int
3651 md_estimate_size_before_relax (fragP, segment)
3652 register fragS *fragP;
3653 segT segment;
3654 {
3655 int old_fix;
3656 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3657
3658 old_fix = fragP->fr_fix;
3659
3660 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3661 switch (fragP->fr_subtype)
3662 {
3663
3664 case TAB (ABRANCH, SZ_UNDEF):
3665 {
3666 if ((fragP->fr_symbol != NULL) /* Not absolute */
3667 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3668 {
3669 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3670 break;
3671 }
3672 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3673 {
3674 /* On 68000, or for absolute value, switch to abs long */
3675 /* FIXME, we should check abs val, pick short or long */
3676 if (fragP->fr_opcode[0] == 0x61)
3677 {
3678 fragP->fr_opcode[0] = 0x4E;
3679 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3680 fix_new (fragP, fragP->fr_fix, 4,
3681 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3682 fragP->fr_fix += 4;
3683 frag_wane (fragP);
3684 }
3685 else if (fragP->fr_opcode[0] == 0x60)
3686 {
3687 fragP->fr_opcode[0] = 0x4E;
3688 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3689 fix_new (fragP, fragP->fr_fix, 4,
3690 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3691 fragP->fr_fix += 4;
3692 frag_wane (fragP);
3693 }
3694 else
3695 {
3696 as_warn ("Long branch offset to extern symbol not supported.");
3697 }
3698 }
3699 else
3700 { /* Symbol is still undefined. Make it simple */
3701 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3702 fragP->fr_offset, 1, NO_RELOC);
3703 fragP->fr_fix += 4;
3704 fragP->fr_opcode[1] = (char) 0xff;
3705 frag_wane (fragP);
3706 break;
3707 }
3708
3709 break;
3710 } /* case TAB(ABRANCH,SZ_UNDEF) */
3711
3712 case TAB (FBRANCH, SZ_UNDEF):
3713 {
3714 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3715 {
3716 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3717 fragP->fr_var += 2;
3718 }
3719 else
3720 {
3721 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3722 fragP->fr_offset, 1, NO_RELOC);
3723 fragP->fr_fix += 4;
3724 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3725 frag_wane (fragP);
3726 }
3727 break;
3728 } /* TAB(FBRANCH,SZ_UNDEF) */
3729
3730 case TAB (PCREL, SZ_UNDEF):
3731 {
3732 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3733 || flag_short_refs
3734 || cpu_of_arch (current_architecture) < m68020)
3735 {
3736 fragP->fr_subtype = TAB (PCREL, SHORT);
3737 fragP->fr_var += 2;
3738 }
3739 else
3740 {
3741 fragP->fr_subtype = TAB (PCREL, LONG);
3742 fragP->fr_var += 4;
3743 }
3744 break;
3745 } /* TAB(PCREL,SZ_UNDEF) */
3746
3747 case TAB (BCC68000, SZ_UNDEF):
3748 {
3749 if ((fragP->fr_symbol != NULL)
3750 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3751 {
3752 fragP->fr_subtype = TAB (BCC68000, BYTE);
3753 break;
3754 }
3755 /* only Bcc 68000 instructions can come here */
3756 /* change bcc into b!cc/jmp absl long */
3757 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3758 if (flag_short_refs)
3759 {
3760 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3761 /* JF: these were fr_opcode[2,3] */
3762 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3763 buffer_address[1] = (char) 0xf8;
3764 fragP->fr_fix += 2; /* account for jmp instruction */
3765 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3766 fragP->fr_offset, 0, NO_RELOC);
3767 fragP->fr_fix += 2;
3768 }
3769 else
3770 {
3771 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3772 /* JF: these were fr_opcode[2,3] */
3773 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3774 buffer_address[1] = (char) 0xf9;
3775 fragP->fr_fix += 2; /* account for jmp instruction */
3776 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3777 fragP->fr_offset, 0, NO_RELOC);
3778 fragP->fr_fix += 4;
3779 }
3780 frag_wane (fragP);
3781 break;
3782 } /* case TAB(BCC68000,SZ_UNDEF) */
3783
3784 case TAB (DBCC, SZ_UNDEF):
3785 {
3786 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3787 {
3788 fragP->fr_subtype = TAB (DBCC, SHORT);
3789 fragP->fr_var += 2;
3790 break;
3791 }
3792 /* only DBcc 68000 instructions can come here */
3793 /* change dbcc into dbcc/jmp absl long */
3794 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3795 buffer_address[0] = 0x00; /* branch offset = 4 */
3796 buffer_address[1] = 0x04;
3797 buffer_address[2] = 0x60; /* put in bra pc + ... */
3798
3799 if (flag_short_refs)
3800 {
3801 /* JF: these were fr_opcode[5-7] */
3802 buffer_address[3] = 0x04; /* plus 4 */
3803 buffer_address[4] = 0x4e; /* Put in Jump Word */
3804 buffer_address[5] = (char) 0xf8;
3805 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3806 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3807 fragP->fr_offset, 0, NO_RELOC);
3808 fragP->fr_fix += 2;
3809 }
3810 else
3811 {
3812 /* JF: these were fr_opcode[5-7] */
3813 buffer_address[3] = 0x06; /* Plus 6 */
3814 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3815 buffer_address[5] = (char) 0xf9;
3816 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3817 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3818 fragP->fr_offset, 0, NO_RELOC);
3819 fragP->fr_fix += 4;
3820 }
3821
3822 frag_wane (fragP);
3823 break;
3824 } /* case TAB(DBCC,SZ_UNDEF) */
3825
3826 case TAB (PCLEA, SZ_UNDEF):
3827 {
3828 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3829 || flag_short_refs
3830 || cpu_of_arch (current_architecture) < m68020)
3831 {
3832 fragP->fr_subtype = TAB (PCLEA, SHORT);
3833 fragP->fr_var += 2;
3834 }
3835 else
3836 {
3837 fragP->fr_subtype = TAB (PCLEA, LONG);
3838 fragP->fr_var += 6;
3839 }
3840 break;
3841 } /* TAB(PCLEA,SZ_UNDEF) */
3842
3843 case TAB (PCINDEX, SZ_UNDEF):
3844 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3845 || cpu_of_arch (current_architecture) < m68020)
3846 {
3847 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3848 }
3849 else
3850 {
3851 fragP->fr_subtype = TAB (PCINDEX, LONG);
3852 fragP->fr_var += 4;
3853 }
3854 break;
3855
3856 default:
3857 break;
3858 }
3859
3860 /* now that SZ_UNDEF are taken care of, check others */
3861 switch (fragP->fr_subtype)
3862 {
3863 case TAB (BCC68000, BYTE):
3864 case TAB (ABRANCH, BYTE):
3865 /* We can't do a short jump to the next instruction,
3866 so we force word mode. */
3867 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3868 fragP->fr_symbol->sy_frag == fragP->fr_next)
3869 {
3870 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3871 fragP->fr_var += 2;
3872 }
3873 break;
3874 default:
3875 break;
3876 }
3877 return fragP->fr_var + fragP->fr_fix - old_fix;
3878 }
3879
3880 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3881 /* the bit-field entries in the relocation_info struct plays hell
3882 with the byte-order problems of cross-assembly. So as a hack,
3883 I added this mach. dependent ri twiddler. Ugly, but it gets
3884 you there. -KWK */
3885 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3886 are symbolnum, most sig. byte first. Last byte is broken up with
3887 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3888 nibble as nuthin. (on Sun 3 at least) */
3889 /* Translate the internal relocation information into target-specific
3890 format. */
3891 #ifdef comment
3892 void
3893 md_ri_to_chars (the_bytes, ri)
3894 char *the_bytes;
3895 struct reloc_info_generic *ri;
3896 {
3897 /* this is easy */
3898 md_number_to_chars (the_bytes, ri->r_address, 4);
3899 /* now the fun stuff */
3900 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3901 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3902 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3903 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3904 ((ri->r_extern << 4) & 0x10));
3905 }
3906
3907 #endif /* comment */
3908
3909 #ifndef BFD_ASSEMBLER
3910 void
3911 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3912 char *where;
3913 fixS *fixP;
3914 relax_addressT segment_address_in_file;
3915 {
3916 /*
3917 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3918 * Out: GNU LD relocation length code: 0, 1, or 2.
3919 */
3920
3921 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3922 long r_symbolnum;
3923
3924 know (fixP->fx_addsy != NULL);
3925
3926 md_number_to_chars (where,
3927 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3928 4);
3929
3930 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3931 ? S_GET_TYPE (fixP->fx_addsy)
3932 : fixP->fx_addsy->sy_number);
3933
3934 where[4] = (r_symbolnum >> 16) & 0x0ff;
3935 where[5] = (r_symbolnum >> 8) & 0x0ff;
3936 where[6] = r_symbolnum & 0x0ff;
3937 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3938 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3939 }
3940 #endif
3941
3942 #endif /* OBJ_AOUT or OBJ_BOUT */
3943
3944 #ifndef WORKING_DOT_WORD
3945 CONST int md_short_jump_size = 4;
3946 CONST int md_long_jump_size = 6;
3947
3948 void
3949 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3950 char *ptr;
3951 addressT from_addr, to_addr;
3952 fragS *frag;
3953 symbolS *to_symbol;
3954 {
3955 valueT offset;
3956
3957 offset = to_addr - (from_addr + 2);
3958
3959 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3960 md_number_to_chars (ptr + 2, (valueT) offset, 2);
3961 }
3962
3963 void
3964 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3965 char *ptr;
3966 addressT from_addr, to_addr;
3967 fragS *frag;
3968 symbolS *to_symbol;
3969 {
3970 valueT offset;
3971
3972 if (cpu_of_arch (current_architecture) < m68020)
3973 {
3974 offset = to_addr - S_GET_VALUE (to_symbol);
3975 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3976 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3977 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3978 0, NO_RELOC);
3979 }
3980 else
3981 {
3982 offset = to_addr - (from_addr + 2);
3983 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3984 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3985 }
3986 }
3987
3988 #endif
3989
3990 /* Different values of OK tell what its OK to return. Things that
3991 aren't OK are an error (what a shock, no?)
3992
3993 0: Everything is OK
3994 10: Absolute 1:8 only
3995 20: Absolute 0:7 only
3996 30: absolute 0:15 only
3997 40: Absolute 0:31 only
3998 50: absolute 0:127 only
3999 55: absolute -64:63 only
4000 60: absolute -128:127 only
4001 70: absolute 0:4095 only
4002 80: No bignums
4003
4004 */
4005
4006 static int
4007 get_num (exp, ok)
4008 struct m68k_exp *exp;
4009 int ok;
4010 {
4011 if (exp->exp.X_op == O_absent)
4012 {
4013 /* Do the same thing the VAX asm does */
4014 op (exp) = O_constant;
4015 adds (exp) = 0;
4016 subs (exp) = 0;
4017 offs (exp) = 0;
4018 if (ok == 10)
4019 {
4020 as_warn ("expression out of range: defaulting to 1");
4021 offs (exp) = 1;
4022 }
4023 }
4024 else if (exp->exp.X_op == O_constant)
4025 {
4026 switch (ok)
4027 {
4028 case 10:
4029 if (offs (exp) < 1 || offs (exp) > 8)
4030 {
4031 as_warn ("expression out of range: defaulting to 1");
4032 offs (exp) = 1;
4033 }
4034 break;
4035 case 20:
4036 if (offs (exp) < 0 || offs (exp) > 7)
4037 goto outrange;
4038 break;
4039 case 30:
4040 if (offs (exp) < 0 || offs (exp) > 15)
4041 goto outrange;
4042 break;
4043 case 40:
4044 if (offs (exp) < 0 || offs (exp) > 32)
4045 goto outrange;
4046 break;
4047 case 50:
4048 if (offs (exp) < 0 || offs (exp) > 127)
4049 goto outrange;
4050 break;
4051 case 55:
4052 if (offs (exp) < -64 || offs (exp) > 63)
4053 goto outrange;
4054 break;
4055 case 60:
4056 if (offs (exp) < -128 || offs (exp) > 127)
4057 goto outrange;
4058 break;
4059 case 70:
4060 if (offs (exp) < 0 || offs (exp) > 4095)
4061 {
4062 outrange:
4063 as_warn ("expression out of range: defaulting to 0");
4064 offs (exp) = 0;
4065 }
4066 break;
4067 default:
4068 break;
4069 }
4070 }
4071 else if (exp->exp.X_op == O_big)
4072 {
4073 if (offs (exp) <= 0 /* flonum */
4074 && (ok == 80 /* no bignums */
4075 || (ok > 10 /* small-int ranges including 0 ok */
4076 /* If we have a flonum zero, a zero integer should
4077 do as well (e.g., in moveq). */
4078 && generic_floating_point_number.exponent == 0
4079 && generic_floating_point_number.low[0] == 0)))
4080 {
4081 /* HACK! Turn it into a long */
4082 LITTLENUM_TYPE words[6];
4083
4084 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4085 op (exp) = O_constant;
4086 adds (exp) = 0;
4087 subs (exp) = 0;
4088 offs (exp) = words[1] | (words[0] << 16);
4089 }
4090 else if (ok != 0)
4091 {
4092 op (exp) = O_constant;
4093 adds (exp) = 0;
4094 subs (exp) = 0;
4095 offs (exp) = (ok == 10) ? 1 : 0;
4096 as_warn ("Can't deal with expression; defaulting to %ld",
4097 offs (exp));
4098 }
4099 }
4100 else
4101 {
4102 if (ok >= 10 && ok <= 70)
4103 {
4104 op (exp) = O_constant;
4105 adds (exp) = 0;
4106 subs (exp) = 0;
4107 offs (exp) = (ok == 10) ? 1 : 0;
4108 as_warn ("Can't deal with expression; defaulting to %ld",
4109 offs (exp));
4110 }
4111 }
4112
4113 if (exp->size != SIZE_UNSPEC)
4114 {
4115 switch (exp->size)
4116 {
4117 case SIZE_UNSPEC:
4118 case SIZE_LONG:
4119 break;
4120 case SIZE_BYTE:
4121 if (!isbyte (offs (exp)))
4122 as_warn ("expression doesn't fit in BYTE");
4123 break;
4124 case SIZE_WORD:
4125 if (!isword (offs (exp)))
4126 as_warn ("expression doesn't fit in WORD");
4127 break;
4128 }
4129 }
4130
4131 return offs (exp);
4132 }
4133
4134 /* These are the back-ends for the various machine dependent pseudo-ops. */
4135 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4136
4137 static void
4138 s_data1 (ignore)
4139 int ignore;
4140 {
4141 subseg_set (data_section, 1);
4142 demand_empty_rest_of_line ();
4143 }
4144
4145 static void
4146 s_data2 (ignore)
4147 int ignore;
4148 {
4149 subseg_set (data_section, 2);
4150 demand_empty_rest_of_line ();
4151 }
4152
4153 static void
4154 s_bss (ignore)
4155 int ignore;
4156 {
4157 /* We don't support putting frags in the BSS segment, we fake it
4158 by marking in_bss, then looking at s_skip for clues. */
4159
4160 subseg_set (bss_section, 0);
4161 demand_empty_rest_of_line ();
4162 }
4163
4164 static void
4165 s_even (ignore)
4166 int ignore;
4167 {
4168 register int temp;
4169 register long temp_fill;
4170
4171 temp = 1; /* JF should be 2? */
4172 temp_fill = get_absolute_expression ();
4173 if (!need_pass_2) /* Never make frag if expect extra pass. */
4174 frag_align (temp, (int) temp_fill);
4175 demand_empty_rest_of_line ();
4176 }
4177
4178 static void
4179 s_proc (ignore)
4180 int ignore;
4181 {
4182 demand_empty_rest_of_line ();
4183 }
4184 \f
4185 /* Pseudo-ops handled for MRI compatibility. */
4186
4187 /* Handle an MRI style chip specification. */
4188
4189 static void
4190 mri_chip ()
4191 {
4192 char *s;
4193 char c;
4194 int i;
4195
4196 s = input_line_pointer;
4197 c = get_symbol_end ();
4198 for (i = 0; i < n_archs; i++)
4199 if (strcasecmp (s, archs[i].name) == 0)
4200 break;
4201 if (i >= n_archs)
4202 {
4203 as_bad ("%s: unrecognized processor name", s);
4204 *input_line_pointer = c;
4205 ignore_rest_of_line ();
4206 return;
4207 }
4208 *input_line_pointer = c;
4209
4210 if (*input_line_pointer == '/')
4211 current_architecture = 0;
4212 else
4213 current_architecture &= m68881 | m68851;
4214 current_architecture |= archs[i].arch;
4215
4216 while (*input_line_pointer == '/')
4217 {
4218 ++input_line_pointer;
4219 s = input_line_pointer;
4220 c = get_symbol_end ();
4221 if (strcmp (s, "68881") == 0)
4222 current_architecture |= m68881;
4223 else if (strcmp (s, "68851") == 0)
4224 current_architecture |= m68851;
4225 *input_line_pointer = c;
4226 }
4227 }
4228
4229 /* The MRI CHIP pseudo-op. */
4230
4231 static void
4232 s_chip (ignore)
4233 int ignore;
4234 {
4235 mri_chip ();
4236 demand_empty_rest_of_line ();
4237 }
4238
4239 /* The MRI FOPT pseudo-op. */
4240
4241 static void
4242 s_fopt (ignore)
4243 int ignore;
4244 {
4245 SKIP_WHITESPACE ();
4246
4247 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4248 {
4249 int temp;
4250
4251 input_line_pointer += 3;
4252 temp = get_absolute_expression ();
4253 if (temp < 0 || temp > 7)
4254 as_bad ("bad coprocessor id");
4255 else
4256 m68k_float_copnum = COP0 + temp;
4257 }
4258 else
4259 {
4260 as_bad ("unrecognized fopt option");
4261 ignore_rest_of_line ();
4262 return;
4263 }
4264
4265 demand_empty_rest_of_line ();
4266 }
4267
4268 /* The structure used to handle the MRI OPT pseudo-op. */
4269
4270 struct opt_action
4271 {
4272 /* The name of the option. */
4273 const char *name;
4274
4275 /* If this is not NULL, just call this function. The first argument
4276 is the ARG field of this structure, the second argument is
4277 whether the option was negated. */
4278 void (*pfn) PARAMS ((int arg, int on));
4279
4280 /* If this is not NULL, and the PFN field is NULL, set the variable
4281 this points to. Set it to the ARG field if the option was not
4282 negated, and the NOTARG field otherwise. */
4283 int *pvar;
4284
4285 /* The value to pass to PFN or to assign to *PVAR. */
4286 int arg;
4287
4288 /* The value to assign to *PVAR if the option is negated. If PFN is
4289 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4290 the option may not be negated. */
4291 int notarg;
4292 };
4293
4294 /* The table used to handle the MRI OPT pseudo-op. */
4295
4296 static void skip_to_comma PARAMS ((int, int));
4297 static void opt_nest PARAMS ((int, int));
4298 static void opt_chip PARAMS ((int, int));
4299 static void opt_list PARAMS ((int, int));
4300 static void opt_list_symbols PARAMS ((int, int));
4301
4302 static const struct opt_action opt_table[] =
4303 {
4304 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4305
4306 /* We do relaxing, so there is little use for these options. */
4307 { "b", 0, 0, 0, 0 },
4308 { "brs", 0, 0, 0, 0 },
4309 { "brb", 0, 0, 0, 0 },
4310 { "brl", 0, 0, 0, 0 },
4311 { "brw", 0, 0, 0, 0 },
4312
4313 { "c", 0, 0, 0, 0 },
4314 { "cex", 0, 0, 0, 0 },
4315 { "case", 0, &symbols_case_sensitive, 1, 0 },
4316 { "cl", 0, 0, 0, 0 },
4317 { "cre", 0, 0, 0, 0 },
4318 { "d", 0, &flag_keep_locals, 1, 0 },
4319 { "e", 0, 0, 0, 0 },
4320 { "f", 0, &flag_short_refs, 1, 0 },
4321 { "frs", 0, &flag_short_refs, 1, 0 },
4322 { "frl", 0, &flag_short_refs, 0, 1 },
4323 { "g", 0, 0, 0, 0 },
4324 { "i", 0, 0, 0, 0 },
4325 { "m", 0, 0, 0, 0 },
4326 { "mex", 0, 0, 0, 0 },
4327 { "mc", 0, 0, 0, 0 },
4328 { "md", 0, 0, 0, 0 },
4329 { "nest", opt_nest, 0, 0, 0 },
4330 { "next", skip_to_comma, 0, 0, 0 },
4331 { "o", 0, 0, 0, 0 },
4332 { "old", 0, 0, 0, 0 },
4333 { "op", skip_to_comma, 0, 0, 0 },
4334 { "pco", 0, 0, 0, 0 },
4335 { "p", opt_chip, 0, 0, 0 },
4336 { "pcr", 0, 0, 0, 0 },
4337 { "pcs", 0, 0, 0, 0 },
4338 { "r", 0, 0, 0, 0 },
4339 { "quick", 0, &m68k_quick, 1, 0 },
4340 { "rel32", 0, &m68k_rel32, 1, 0 },
4341 { "s", opt_list, 0, 0, 0 },
4342 { "t", opt_list_symbols, 0, 0, 0 },
4343 { "w", 0, &flag_no_warnings, 0, 1 },
4344 { "x", 0, 0, 0, 0 }
4345 };
4346
4347 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4348
4349 /* The MRI OPT pseudo-op. */
4350
4351 static void
4352 s_opt (ignore)
4353 int ignore;
4354 {
4355 do
4356 {
4357 int t;
4358 char *s;
4359 char c;
4360 int i;
4361 const struct opt_action *o;
4362
4363 SKIP_WHITESPACE ();
4364
4365 t = 1;
4366 if (*input_line_pointer == '-')
4367 {
4368 ++input_line_pointer;
4369 t = 0;
4370 }
4371 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4372 {
4373 input_line_pointer += 2;
4374 t = 0;
4375 }
4376
4377 s = input_line_pointer;
4378 c = get_symbol_end ();
4379
4380 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4381 {
4382 if (strcasecmp (s, o->name) == 0)
4383 {
4384 if (o->pfn)
4385 {
4386 /* Restore input_line_pointer now in case the option
4387 takes arguments. */
4388 *input_line_pointer = c;
4389 (*o->pfn) (o->arg, t);
4390 }
4391 else if (o->pvar != NULL)
4392 {
4393 if (! t && o->arg == o->notarg)
4394 as_bad ("option `%s' may not be negated", s);
4395 *input_line_pointer = c;
4396 *o->pvar = t ? o->arg : o->notarg;
4397 }
4398 else
4399 *input_line_pointer = c;
4400 break;
4401 }
4402 }
4403 if (i >= OPTCOUNT)
4404 {
4405 as_bad ("option `%s' not recognized", s);
4406 *input_line_pointer = c;
4407 }
4408 }
4409 while (*input_line_pointer++ == ',');
4410
4411 /* Move back to terminating character. */
4412 --input_line_pointer;
4413 demand_empty_rest_of_line ();
4414 }
4415
4416 /* Skip ahead to a comma. This is used for OPT options which we do
4417 not suppor tand which take arguments. */
4418
4419 static void
4420 skip_to_comma (arg, on)
4421 int arg;
4422 int on;
4423 {
4424 while (*input_line_pointer != ','
4425 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4426 ++input_line_pointer;
4427 }
4428
4429 /* Handle the OPT NEST=depth option. */
4430
4431 static void
4432 opt_nest (arg, on)
4433 int arg;
4434 int on;
4435 {
4436 if (*input_line_pointer != '=')
4437 {
4438 as_bad ("bad format of OPT NEST=depth");
4439 return;
4440 }
4441
4442 ++input_line_pointer;
4443 max_macro_nest = get_absolute_expression ();
4444 }
4445
4446 /* Handle the OPT P=chip option. */
4447
4448 static void
4449 opt_chip (arg, on)
4450 int arg;
4451 int on;
4452 {
4453 if (*input_line_pointer != '=')
4454 {
4455 /* This is just OPT P, which we do not support. */
4456 return;
4457 }
4458
4459 ++input_line_pointer;
4460 mri_chip ();
4461 }
4462
4463 /* Handle the OPT S option. */
4464
4465 static void
4466 opt_list (arg, on)
4467 int arg;
4468 int on;
4469 {
4470 listing_list (on);
4471 }
4472
4473 /* Handle the OPT T option. */
4474
4475 static void
4476 opt_list_symbols (arg, on)
4477 int arg;
4478 int on;
4479 {
4480 if (on)
4481 listing |= LISTING_SYMBOLS;
4482 else
4483 listing &=~ LISTING_SYMBOLS;
4484 }
4485
4486 /* Handle the MRI REG pseudo-op. */
4487
4488 static void
4489 s_reg (ignore)
4490 int ignore;
4491 {
4492 char *s;
4493 int c;
4494 struct m68k_op rop;
4495 unsigned long mask;
4496
4497 if (line_label == NULL)
4498 {
4499 as_bad ("missing label");
4500 ignore_rest_of_line ();
4501 return;
4502 }
4503
4504 SKIP_WHITESPACE ();
4505
4506 s = input_line_pointer;
4507 while (isalnum ((unsigned char) *input_line_pointer)
4508 #ifdef REGISTER_PREFIX
4509 || *input_line_pointer == REGISTER_PREFIX
4510 #endif
4511 || *input_line_pointer == '/'
4512 || *input_line_pointer == '-')
4513 ++input_line_pointer;
4514 c = *input_line_pointer;
4515 *input_line_pointer = '\0';
4516
4517 if (m68k_ip_op (s, &rop) != 0)
4518 {
4519 if (rop.error == NULL)
4520 as_bad ("bad register list");
4521 else
4522 as_bad ("bad register list: %s", rop.error);
4523 *input_line_pointer = c;
4524 ignore_rest_of_line ();
4525 return;
4526 }
4527
4528 *input_line_pointer = c;
4529
4530 if (rop.mode == REGLST)
4531 mask = rop.mask;
4532 else if (rop.mode == DREG)
4533 mask = 1 << (rop.reg - DATA0);
4534 else if (rop.mode == AREG)
4535 mask = 1 << (rop.reg - ADDR0 + 8);
4536 else if (rop.mode == FPREG)
4537 mask = 1 << (rop.reg - FP0 + 16);
4538 else if (rop.mode == CONTROL
4539 && rop.reg == FPI)
4540 mask = 1 << 24;
4541 else if (rop.mode == CONTROL
4542 && rop.reg == FPS)
4543 mask = 1 << 25;
4544 else if (rop.mode == CONTROL
4545 && rop.reg == FPC)
4546 mask = 1 << 26;
4547 else
4548 {
4549 as_bad ("bad register list");
4550 ignore_rest_of_line ();
4551 return;
4552 }
4553
4554 S_SET_SEGMENT (line_label, absolute_section);
4555 S_SET_VALUE (line_label, mask);
4556 line_label->sy_frag = &zero_address_frag;
4557
4558 if (flag_mri)
4559 {
4560 /* Ignore the comment field. */
4561 while (! is_end_of_line[(unsigned char) *input_line_pointer])
4562 ++input_line_pointer;
4563 }
4564
4565 demand_empty_rest_of_line ();
4566 }
4567
4568 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4569
4570 struct save_opts
4571 {
4572 struct save_opts *next;
4573 int abspcadd;
4574 int symbols_case_sensitive;
4575 int keep_locals;
4576 int short_refs;
4577 int architecture;
4578 int quick;
4579 int rel32;
4580 int listing;
4581 int no_warnings;
4582 /* FIXME: We don't save OPT S. */
4583 };
4584
4585 /* This variable holds the stack of saved options. */
4586
4587 static struct save_opts *save_stack;
4588
4589 /* The MRI SAVE pseudo-op. */
4590
4591 static void
4592 s_save (ignore)
4593 int ignore;
4594 {
4595 struct save_opts *s;
4596
4597 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4598 s->abspcadd = m68k_abspcadd;
4599 s->symbols_case_sensitive = symbols_case_sensitive;
4600 s->keep_locals = flag_keep_locals;
4601 s->short_refs = flag_short_refs;
4602 s->architecture = current_architecture;
4603 s->quick = m68k_quick;
4604 s->rel32 = m68k_rel32;
4605 s->listing = listing;
4606 s->no_warnings = flag_no_warnings;
4607
4608 s->next = save_stack;
4609 save_stack = s;
4610
4611 demand_empty_rest_of_line ();
4612 }
4613
4614 /* The MRI RESTORE pseudo-op. */
4615
4616 static void
4617 s_restore (ignore)
4618 int ignore;
4619 {
4620 struct save_opts *s;
4621
4622 if (save_stack == NULL)
4623 {
4624 as_bad ("restore without save");
4625 ignore_rest_of_line ();
4626 return;
4627 }
4628
4629 s = save_stack;
4630 save_stack = s->next;
4631
4632 m68k_abspcadd = s->abspcadd;
4633 symbols_case_sensitive = s->symbols_case_sensitive;
4634 flag_keep_locals = s->keep_locals;
4635 flag_short_refs = s->short_refs;
4636 current_architecture = s->architecture;
4637 m68k_quick = s->quick;
4638 m68k_rel32 = s->rel32;
4639 listing = s->listing;
4640 flag_no_warnings = s->no_warnings;
4641
4642 free (s);
4643
4644 demand_empty_rest_of_line ();
4645 }
4646
4647 /* Types of MRI structured control directives. */
4648
4649 enum mri_control_type
4650 {
4651 mri_for,
4652 mri_if,
4653 mri_repeat,
4654 mri_while
4655 };
4656
4657 /* This structure is used to stack the MRI structured control
4658 directives. */
4659
4660 struct mri_control_info
4661 {
4662 /* The directive within which this one is enclosed. */
4663 struct mri_control_info *outer;
4664
4665 /* The type of directive. */
4666 enum mri_control_type type;
4667
4668 /* Whether an ELSE has been in an IF. */
4669 int else_seen;
4670
4671 /* The add or sub statement at the end of a FOR. */
4672 char *incr;
4673
4674 /* The label of the top of a FOR or REPEAT loop. */
4675 char *top;
4676
4677 /* The label to jump to for the next iteration, or the else
4678 expression of a conditional. */
4679 char *next;
4680
4681 /* The label to jump to to break out of the loop, or the label past
4682 the end of a conditional. */
4683 char *bottom;
4684 };
4685
4686 /* The stack of MRI structured control directives. */
4687
4688 static struct mri_control_info *mri_control_stack;
4689
4690 /* The current MRI structured control directive index number, used to
4691 generate label names. */
4692
4693 static int mri_control_index;
4694
4695 /* Some function prototypes. */
4696
4697 static char *mri_control_label PARAMS ((void));
4698 static struct mri_control_info *push_mri_control
4699 PARAMS ((enum mri_control_type));
4700 static void pop_mri_control PARAMS ((void));
4701 static int parse_mri_condition PARAMS ((int *));
4702 static int parse_mri_control_operand
4703 PARAMS ((int *, const char **, const char **, const char **, const char **));
4704 static int swap_mri_condition PARAMS ((int));
4705 static int reverse_mri_condition PARAMS ((int));
4706 static void build_mri_control_operand
4707 PARAMS ((int, int, const char *, const char *, const char *, const char *,
4708 const char *, const char *, int));
4709 static void parse_mri_control_expression
4710 PARAMS ((char *, int, const char *, const char *, int));
4711
4712 /* Generate a new MRI label structured control directive label name. */
4713
4714 static char *
4715 mri_control_label ()
4716 {
4717 char *n;
4718
4719 n = (char *) xmalloc (20);
4720 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
4721 ++mri_control_index;
4722 return n;
4723 }
4724
4725 /* Create a new MRI structured control directive. */
4726
4727 static struct mri_control_info *
4728 push_mri_control (type)
4729 enum mri_control_type type;
4730 {
4731 struct mri_control_info *n;
4732
4733 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
4734
4735 n->type = type;
4736 n->else_seen = 0;
4737 if (type == mri_if || type == mri_while)
4738 n->top = NULL;
4739 else
4740 n->top = mri_control_label ();
4741 n->next = mri_control_label ();
4742 n->bottom = mri_control_label ();
4743
4744 n->outer = mri_control_stack;
4745 mri_control_stack = n;
4746
4747 return n;
4748 }
4749
4750 /* Pop off the stack of MRI structured control directives. */
4751
4752 static void
4753 pop_mri_control ()
4754 {
4755 struct mri_control_info *n;
4756
4757 n = mri_control_stack;
4758 mri_control_stack = n->outer;
4759 if (n->top != NULL)
4760 free (n->top);
4761 free (n->next);
4762 free (n->bottom);
4763 free (n);
4764 }
4765
4766 /* Recognize a condition code in an MRI structured control expression. */
4767
4768 static int
4769 parse_mri_condition (pcc)
4770 int *pcc;
4771 {
4772 char c1, c2;
4773
4774 know (*input_line_pointer == '<');
4775
4776 ++input_line_pointer;
4777 c1 = *input_line_pointer++;
4778 c2 = *input_line_pointer++;
4779
4780 if (*input_line_pointer != '>')
4781 {
4782 as_bad ("syntax error in structured control directive");
4783 return 0;
4784 }
4785
4786 ++input_line_pointer;
4787 SKIP_WHITESPACE ();
4788
4789 if (isupper (c1))
4790 c1 = tolower (c1);
4791 if (isupper (c2))
4792 c2 = tolower (c2);
4793
4794 *pcc = (c1 << 8) | c2;
4795
4796 return 1;
4797 }
4798
4799 /* Parse a single operand in an MRI structured control expression. */
4800
4801 static int
4802 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
4803 int *pcc;
4804 const char **leftstart;
4805 const char **leftstop;
4806 const char **rightstart;
4807 const char **rightstop;
4808 {
4809 char *s;
4810
4811 SKIP_WHITESPACE ();
4812
4813 *pcc = -1;
4814 *leftstart = NULL;
4815 *leftstop = NULL;
4816 *rightstart = NULL;
4817 *rightstop = NULL;
4818
4819 if (*input_line_pointer == '<')
4820 {
4821 /* It's just a condition code. */
4822 return parse_mri_condition (pcc);
4823 }
4824
4825 /* Look ahead for the condition code. */
4826 for (s = input_line_pointer; *s != '\0'; ++s)
4827 {
4828 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
4829 break;
4830 }
4831 if (*s == '\0')
4832 {
4833 as_bad ("missing condition code in structured control directive");
4834 return 0;
4835 }
4836
4837 *leftstart = input_line_pointer;
4838 *leftstop = s;
4839 if (*leftstop > *leftstart
4840 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
4841 --*leftstop;
4842
4843 input_line_pointer = s;
4844 if (! parse_mri_condition (pcc))
4845 return 0;
4846
4847 /* Look ahead for AND or OR or end of line. */
4848 for (s = input_line_pointer; *s != '\0'; ++s)
4849 {
4850 if ((strncasecmp (s, "AND", 3) == 0
4851 && (s[3] == '.' || ! is_part_of_name (s[3])))
4852 || (strncasecmp (s, "OR", 2) == 0
4853 && (s[2] == '.' || ! is_part_of_name (s[2]))))
4854 break;
4855 }
4856
4857 *rightstart = input_line_pointer;
4858 *rightstop = s;
4859 if (*rightstop > *rightstart
4860 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
4861 --*rightstop;
4862
4863 input_line_pointer = s;
4864
4865 return 1;
4866 }
4867
4868 #define MCC(b1, b2) (((b1) << 8) | (b2))
4869
4870 /* Swap the sense of a condition. This changes the condition so that
4871 it generates the same result when the operands are swapped. */
4872
4873 static int
4874 swap_mri_condition (cc)
4875 int cc;
4876 {
4877 switch (cc)
4878 {
4879 case MCC ('h', 'i'): return MCC ('c', 's');
4880 case MCC ('l', 's'): return MCC ('c', 'c');
4881 case MCC ('c', 'c'): return MCC ('l', 's');
4882 case MCC ('c', 's'): return MCC ('h', 'i');
4883 case MCC ('p', 'l'): return MCC ('m', 'i');
4884 case MCC ('m', 'i'): return MCC ('p', 'l');
4885 case MCC ('g', 'e'): return MCC ('l', 'e');
4886 case MCC ('l', 't'): return MCC ('g', 't');
4887 case MCC ('g', 't'): return MCC ('l', 't');
4888 case MCC ('l', 'e'): return MCC ('g', 'e');
4889 }
4890 return cc;
4891 }
4892
4893 /* Reverse the sense of a condition. */
4894
4895 static int
4896 reverse_mri_condition (cc)
4897 int cc;
4898 {
4899 switch (cc)
4900 {
4901 case MCC ('h', 'i'): return MCC ('l', 's');
4902 case MCC ('l', 's'): return MCC ('h', 'i');
4903 case MCC ('c', 'c'): return MCC ('c', 's');
4904 case MCC ('c', 's'): return MCC ('c', 'c');
4905 case MCC ('n', 'e'): return MCC ('e', 'q');
4906 case MCC ('e', 'q'): return MCC ('n', 'e');
4907 case MCC ('v', 'c'): return MCC ('v', 's');
4908 case MCC ('v', 's'): return MCC ('v', 'c');
4909 case MCC ('p', 'l'): return MCC ('m', 'i');
4910 case MCC ('m', 'i'): return MCC ('p', 'l');
4911 case MCC ('g', 'e'): return MCC ('l', 't');
4912 case MCC ('l', 't'): return MCC ('g', 'e');
4913 case MCC ('g', 't'): return MCC ('l', 'e');
4914 case MCC ('l', 'e'): return MCC ('g', 't');
4915 }
4916 return cc;
4917 }
4918
4919 /* Build an MRI structured control expression. This generates test
4920 and branch instructions. It goes to TRUELAB if the condition is
4921 true, and to FALSELAB if the condition is false. Exactly one of
4922 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
4923 is the size qualifier for the expression. EXTENT is the size to
4924 use for the branch. */
4925
4926 static void
4927 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4928 rightstop, truelab, falselab, extent)
4929 int qual;
4930 int cc;
4931 const char *leftstart;
4932 const char *leftstop;
4933 const char *rightstart;
4934 const char *rightstop;
4935 const char *truelab;
4936 const char *falselab;
4937 int extent;
4938 {
4939 char *buf;
4940 char *s;
4941
4942 /* The 68k can't do a general comparision with an immediate operand
4943 on the right hand side. */
4944 if (rightstart != NULL && *rightstart == '#')
4945 {
4946 const char *temp;
4947
4948 cc = swap_mri_condition (cc);
4949 temp = leftstart;
4950 leftstart = rightstart;
4951 rightstart = temp;
4952 temp = leftstop;
4953 leftstop = rightstop;
4954 rightstop = temp;
4955 }
4956
4957 if (truelab == NULL)
4958 {
4959 cc = reverse_mri_condition (cc);
4960 truelab = falselab;
4961 }
4962
4963 if (leftstart != NULL)
4964 {
4965 buf = (char *) xmalloc (20
4966 + (leftstop - leftstart)
4967 + (rightstop - rightstart));
4968 s = buf;
4969 *s++ = 'c';
4970 *s++ = 'm';
4971 *s++ = 'p';
4972 if (qual != '\0')
4973 *s++ = qual;
4974 *s++ = ' ';
4975 memcpy (s, leftstart, leftstop - leftstart);
4976 s += leftstop - leftstart;
4977 *s++ = ',';
4978 memcpy (s, rightstart, rightstop - rightstart);
4979 s += rightstop - rightstart;
4980 *s = '\0';
4981 md_assemble (buf);
4982 free (buf);
4983 }
4984
4985 buf = (char *) xmalloc (20 + strlen (truelab));
4986 s = buf;
4987 *s++ = 'b';
4988 *s++ = cc >> 8;
4989 *s++ = cc & 0xff;
4990 if (extent != '\0')
4991 *s++ = extent;
4992 *s++ = ' ';
4993 strcpy (s, truelab);
4994 md_assemble (buf);
4995 free (buf);
4996 }
4997
4998 /* Parse an MRI structured control expression. This generates test
4999 and branch instructions. STOP is where the expression ends. It
5000 goes to TRUELAB if the condition is true, and to FALSELAB if the
5001 condition is false. Exactly one of TRUELAB and FALSELAB will be
5002 NULL, meaning to fall through. QUAL is the size qualifier for the
5003 expression. EXTENT is the size to use for the branch. */
5004
5005 static void
5006 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5007 char *stop;
5008 int qual;
5009 const char *truelab;
5010 const char *falselab;
5011 int extent;
5012 {
5013 int c;
5014 int cc;
5015 const char *leftstart;
5016 const char *leftstop;
5017 const char *rightstart;
5018 const char *rightstop;
5019
5020 c = *stop;
5021 *stop = '\0';
5022
5023 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5024 &rightstart, &rightstop))
5025 {
5026 *stop = c;
5027 return;
5028 }
5029
5030 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5031 {
5032 const char *flab;
5033
5034 if (falselab != NULL)
5035 flab = falselab;
5036 else
5037 flab = mri_control_label ();
5038
5039 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5040 rightstop, (const char *) NULL, flab, extent);
5041
5042 input_line_pointer += 3;
5043 if (*input_line_pointer != '.'
5044 || input_line_pointer[1] == '\0')
5045 qual = '\0';
5046 else
5047 {
5048 qual = input_line_pointer[1];
5049 input_line_pointer += 2;
5050 }
5051
5052 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5053 &rightstart, &rightstop))
5054 {
5055 *stop = c;
5056 return;
5057 }
5058
5059 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5060 rightstop, truelab, falselab, extent);
5061
5062 if (falselab == NULL)
5063 colon (flab);
5064 }
5065 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5066 {
5067 const char *tlab;
5068
5069 if (truelab != NULL)
5070 tlab = truelab;
5071 else
5072 tlab = mri_control_label ();
5073
5074 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5075 rightstop, tlab, (const char *) NULL, extent);
5076
5077 input_line_pointer += 2;
5078 if (*input_line_pointer != '.'
5079 || input_line_pointer[1] == '\0')
5080 qual = '\0';
5081 else
5082 {
5083 qual = input_line_pointer[1];
5084 input_line_pointer += 2;
5085 }
5086
5087 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5088 &rightstart, &rightstop))
5089 {
5090 *stop = c;
5091 return;
5092 }
5093
5094 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5095 rightstop, truelab, falselab, extent);
5096
5097 if (truelab == NULL)
5098 colon (tlab);
5099 }
5100 else
5101 {
5102 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5103 rightstop, truelab, falselab, extent);
5104 }
5105
5106 *stop = c;
5107 if (input_line_pointer != stop)
5108 as_bad ("syntax error in structured control directive");
5109 }
5110
5111 /* Handle the MRI IF pseudo-op. This may be a structured control
5112 directive, or it may be a regular assembler conditional, depending
5113 on its operands. */
5114
5115 static void
5116 s_mri_if (qual)
5117 int qual;
5118 {
5119 char *s;
5120 int c;
5121 struct mri_control_info *n;
5122
5123 /* A structured control directive must end with THEN with an
5124 optional qualifier. */
5125 s = input_line_pointer;
5126 while (! is_end_of_line[(unsigned char) *s])
5127 ++s;
5128 --s;
5129 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5130 --s;
5131
5132 if (s - input_line_pointer > 1
5133 && s[-1] == '.')
5134 s -= 2;
5135
5136 if (s - input_line_pointer < 3
5137 || strncasecmp (s - 3, "THEN", 4) != 0)
5138 {
5139 if (qual != '\0')
5140 {
5141 as_bad ("missing then");
5142 ignore_rest_of_line ();
5143 return;
5144 }
5145
5146 /* It's a conditional. */
5147 s_if (O_ne);
5148 return;
5149 }
5150
5151 /* Since this might be a conditional if, this pseudo-op will be
5152 called even if we are supported to be ignoring input. Double
5153 check now. Clobber *input_line_pointer so that ignore_input
5154 thinks that this is not a special pseudo-op. */
5155 c = *input_line_pointer;
5156 *input_line_pointer = 0;
5157 if (ignore_input ())
5158 {
5159 *input_line_pointer = c;
5160 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5161 ++input_line_pointer;
5162 demand_empty_rest_of_line ();
5163 return;
5164 }
5165 *input_line_pointer = c;
5166
5167 n = push_mri_control (mri_if);
5168
5169 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5170 n->next, s[1] == '.' ? s[2] : '\0');
5171
5172 if (s[1] == '.')
5173 input_line_pointer = s + 3;
5174 else
5175 input_line_pointer = s + 1;
5176
5177 demand_empty_rest_of_line ();
5178 }
5179
5180 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5181 structured IF, associate the ELSE with the IF. Otherwise, assume
5182 it is a conditional else. */
5183
5184 static void
5185 s_mri_else (qual)
5186 int qual;
5187 {
5188 int c;
5189 char *buf;
5190 char q[2];
5191
5192 if (qual == '\0'
5193 && (mri_control_stack == NULL
5194 || mri_control_stack->type != mri_if
5195 || mri_control_stack->else_seen))
5196 {
5197 s_else (0);
5198 return;
5199 }
5200
5201 c = *input_line_pointer;
5202 *input_line_pointer = 0;
5203 if (ignore_input ())
5204 {
5205 *input_line_pointer = c;
5206 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5207 ++input_line_pointer;
5208 demand_empty_rest_of_line ();
5209 return;
5210 }
5211 *input_line_pointer = c;
5212
5213 if (mri_control_stack == NULL
5214 || mri_control_stack->type != mri_if
5215 || mri_control_stack->else_seen)
5216 {
5217 as_bad ("else without matching if");
5218 ignore_rest_of_line ();
5219 return;
5220 }
5221
5222 mri_control_stack->else_seen = 1;
5223
5224 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5225 q[0] = qual;
5226 q[1] = '\0';
5227 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5228 md_assemble (buf);
5229 free (buf);
5230
5231 colon (mri_control_stack->next);
5232
5233 demand_empty_rest_of_line ();
5234 }
5235
5236 /* Handle the MRI ENDI pseudo-op. */
5237
5238 static void
5239 s_mri_endi (ignore)
5240 int ignore;
5241 {
5242 if (mri_control_stack == NULL
5243 || mri_control_stack->type != mri_if)
5244 {
5245 as_bad ("endi without matching if");
5246 ignore_rest_of_line ();
5247 return;
5248 }
5249
5250 /* ignore_input will not return true for ENDI, so we don't need to
5251 worry about checking it again here. */
5252
5253 if (! mri_control_stack->else_seen)
5254 colon (mri_control_stack->next);
5255 colon (mri_control_stack->bottom);
5256
5257 pop_mri_control ();
5258
5259 demand_empty_rest_of_line ();
5260 }
5261
5262 /* Handle the MRI BREAK pseudo-op. */
5263
5264 static void
5265 s_mri_break (extent)
5266 int extent;
5267 {
5268 struct mri_control_info *n;
5269 char *buf;
5270 char ex[2];
5271
5272 n = mri_control_stack;
5273 while (n != NULL
5274 && n->type != mri_for
5275 && n->type != mri_repeat
5276 && n->type != mri_while)
5277 n = n->outer;
5278 if (n == NULL)
5279 {
5280 as_bad ("break outside of structured loop");
5281 ignore_rest_of_line ();
5282 return;
5283 }
5284
5285 buf = (char *) xmalloc (20 + strlen (n->bottom));
5286 ex[0] = extent;
5287 ex[1] = '\0';
5288 sprintf (buf, "bra%s %s", ex, n->bottom);
5289 md_assemble (buf);
5290 free (buf);
5291
5292 demand_empty_rest_of_line ();
5293 }
5294
5295 /* Handle the MRI NEXT pseudo-op. */
5296
5297 static void
5298 s_mri_next (extent)
5299 int extent;
5300 {
5301 struct mri_control_info *n;
5302 char *buf;
5303 char ex[2];
5304
5305 n = mri_control_stack;
5306 while (n != NULL
5307 && n->type != mri_for
5308 && n->type != mri_repeat
5309 && n->type != mri_while)
5310 n = n->outer;
5311 if (n == NULL)
5312 {
5313 as_bad ("next outside of structured loop");
5314 ignore_rest_of_line ();
5315 return;
5316 }
5317
5318 buf = (char *) xmalloc (20 + strlen (n->next));
5319 ex[0] = extent;
5320 ex[1] = '\0';
5321 sprintf (buf, "bra%s %s", ex, n->next);
5322 md_assemble (buf);
5323 free (buf);
5324
5325 demand_empty_rest_of_line ();
5326 }
5327
5328 /* Handle the MRI FOR pseudo-op. */
5329
5330 static void
5331 s_mri_for (qual)
5332 int qual;
5333 {
5334 const char *varstart, *varstop;
5335 const char *initstart, *initstop;
5336 const char *endstart, *endstop;
5337 const char *bystart, *bystop;
5338 int up;
5339 int by;
5340 int extent;
5341 struct mri_control_info *n;
5342 char *buf;
5343 char *s;
5344 char ex[2];
5345
5346 /* The syntax is
5347 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5348 */
5349
5350 SKIP_WHITESPACE ();
5351 varstart = input_line_pointer;
5352
5353 /* Look for the '='. */
5354 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5355 && *input_line_pointer != '=')
5356 ++input_line_pointer;
5357 if (*input_line_pointer != '=')
5358 {
5359 as_bad ("missing =");
5360 ignore_rest_of_line ();
5361 return;
5362 }
5363
5364 varstop = input_line_pointer;
5365 if (varstop > varstart
5366 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5367 --varstop;
5368
5369 ++input_line_pointer;
5370
5371 initstart = input_line_pointer;
5372
5373 /* Look for TO or DOWNTO. */
5374 up = 1;
5375 initstop = NULL;
5376 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5377 {
5378 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5379 && ! is_part_of_name (input_line_pointer[2]))
5380 {
5381 initstop = input_line_pointer;
5382 input_line_pointer += 2;
5383 break;
5384 }
5385 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5386 && ! is_part_of_name (input_line_pointer[6]))
5387 {
5388 initstop = input_line_pointer;
5389 up = 0;
5390 input_line_pointer += 6;
5391 break;
5392 }
5393 ++input_line_pointer;
5394 }
5395 if (initstop == NULL)
5396 {
5397 as_bad ("missing to or downto");
5398 ignore_rest_of_line ();
5399 return;
5400 }
5401 if (initstop > initstart
5402 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5403 --initstop;
5404
5405 SKIP_WHITESPACE ();
5406 endstart = input_line_pointer;
5407
5408 /* Look for BY or DO. */
5409 by = 0;
5410 endstop = NULL;
5411 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5412 {
5413 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5414 && ! is_part_of_name (input_line_pointer[2]))
5415 {
5416 endstop = input_line_pointer;
5417 by = 1;
5418 input_line_pointer += 2;
5419 break;
5420 }
5421 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5422 && (input_line_pointer[2] == '.'
5423 || ! is_part_of_name (input_line_pointer[2])))
5424 {
5425 endstop = input_line_pointer;
5426 input_line_pointer += 2;
5427 break;
5428 }
5429 ++input_line_pointer;
5430 }
5431 if (endstop == NULL)
5432 {
5433 as_bad ("missing do");
5434 ignore_rest_of_line ();
5435 return;
5436 }
5437 if (endstop > endstart
5438 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5439 --endstop;
5440
5441 if (! by)
5442 {
5443 bystart = "#1";
5444 bystop = bystart + 2;
5445 }
5446 else
5447 {
5448 SKIP_WHITESPACE ();
5449 bystart = input_line_pointer;
5450
5451 /* Look for DO. */
5452 bystop = NULL;
5453 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5454 {
5455 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5456 && (input_line_pointer[2] == '.'
5457 || ! is_part_of_name (input_line_pointer[2])))
5458 {
5459 bystop = input_line_pointer;
5460 input_line_pointer += 2;
5461 break;
5462 }
5463 ++input_line_pointer;
5464 }
5465 if (bystop == NULL)
5466 {
5467 as_bad ("missing do");
5468 ignore_rest_of_line ();
5469 return;
5470 }
5471 if (bystop > bystart
5472 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5473 --bystop;
5474 }
5475
5476 if (*input_line_pointer != '.')
5477 extent = '\0';
5478 else
5479 {
5480 extent = input_line_pointer[1];
5481 input_line_pointer += 2;
5482 }
5483
5484 /* We have fully parsed the FOR operands. Now build the loop. */
5485
5486 n = push_mri_control (mri_for);
5487
5488 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5489
5490 /* move init,var */
5491 s = buf;
5492 *s++ = 'm';
5493 *s++ = 'o';
5494 *s++ = 'v';
5495 *s++ = 'e';
5496 if (qual != '\0')
5497 *s++ = qual;
5498 *s++ = ' ';
5499 memcpy (s, initstart, initstop - initstart);
5500 s += initstop - initstart;
5501 *s++ = ',';
5502 memcpy (s, varstart, varstop - varstart);
5503 s += varstop - varstart;
5504 *s = '\0';
5505 md_assemble (buf);
5506
5507 colon (n->top);
5508
5509 /* cmp end,var */
5510 s = buf;
5511 *s++ = 'c';
5512 *s++ = 'm';
5513 *s++ = 'p';
5514 if (qual != '\0')
5515 *s++ = qual;
5516 *s++ = ' ';
5517 memcpy (s, endstart, endstop - endstart);
5518 s += endstop - endstart;
5519 *s++ = ',';
5520 memcpy (s, varstart, varstop - varstart);
5521 s += varstop - varstart;
5522 *s = '\0';
5523 md_assemble (buf);
5524
5525 /* bcc bottom */
5526 ex[0] = extent;
5527 ex[1] = '\0';
5528 if (up)
5529 sprintf (buf, "blt%s %s", ex, n->bottom);
5530 else
5531 sprintf (buf, "bgt%s %s", ex, n->bottom);
5532 md_assemble (buf);
5533
5534 /* Put together the add or sub instruction used by ENDF. */
5535 s = buf;
5536 if (up)
5537 strcpy (s, "add");
5538 else
5539 strcpy (s, "sub");
5540 s += 3;
5541 if (qual != '\0')
5542 *s++ = qual;
5543 *s++ = ' ';
5544 memcpy (s, bystart, bystop - bystart);
5545 s += bystop - bystart;
5546 *s++ = ',';
5547 memcpy (s, varstart, varstop - varstart);
5548 s += varstop - varstart;
5549 *s = '\0';
5550 n->incr = buf;
5551
5552 demand_empty_rest_of_line ();
5553 }
5554
5555 /* Handle the MRI ENDF pseudo-op. */
5556
5557 static void
5558 s_mri_endf (ignore)
5559 int ignore;
5560 {
5561 if (mri_control_stack == NULL
5562 || mri_control_stack->type != mri_for)
5563 {
5564 as_bad ("endf without for");
5565 ignore_rest_of_line ();
5566 return;
5567 }
5568
5569 colon (mri_control_stack->next);
5570
5571 md_assemble (mri_control_stack->incr);
5572
5573 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5574 md_assemble (mri_control_stack->incr);
5575
5576 free (mri_control_stack->incr);
5577
5578 colon (mri_control_stack->bottom);
5579
5580 pop_mri_control ();
5581
5582 demand_empty_rest_of_line ();
5583 }
5584
5585 /* Handle the MRI REPEAT pseudo-op. */
5586
5587 static void
5588 s_mri_repeat (ignore)
5589 int ignore;
5590 {
5591 struct mri_control_info *n;
5592
5593 n = push_mri_control (mri_repeat);
5594 colon (n->top);
5595 demand_empty_rest_of_line ();
5596 }
5597
5598 /* Handle the MRI UNTIL pseudo-op. */
5599
5600 static void
5601 s_mri_until (qual)
5602 int qual;
5603 {
5604 char *s;
5605
5606 if (mri_control_stack == NULL
5607 || mri_control_stack->type != mri_repeat)
5608 {
5609 as_bad ("until without repeat");
5610 ignore_rest_of_line ();
5611 return;
5612 }
5613
5614 colon (mri_control_stack->next);
5615
5616 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
5617 ;
5618
5619 parse_mri_control_expression (s, qual, (const char *) NULL,
5620 mri_control_stack->top, '\0');
5621
5622 colon (mri_control_stack->bottom);
5623
5624 input_line_pointer = s;
5625
5626 demand_empty_rest_of_line ();
5627 }
5628
5629 /* Handle the MRI WHILE pseudo-op. */
5630
5631 static void
5632 s_mri_while (qual)
5633 int qual;
5634 {
5635 char *s;
5636
5637 struct mri_control_info *n;
5638
5639 s = input_line_pointer;
5640 while (! is_end_of_line[(unsigned char) *s])
5641 s++;
5642 --s;
5643 while (*s == ' ' || *s == '\t')
5644 --s;
5645 if (s - input_line_pointer > 1
5646 && s[-1] == '.')
5647 s -= 2;
5648 if (s - input_line_pointer < 2
5649 || strncasecmp (s - 1, "DO", 2) != 0)
5650 {
5651 as_bad ("missing do");
5652 ignore_rest_of_line ();
5653 return;
5654 }
5655
5656 n = push_mri_control (mri_while);
5657
5658 colon (n->next);
5659
5660 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
5661 s[1] == '.' ? s[2] : '\0');
5662
5663 input_line_pointer = s + 1;
5664 if (*input_line_pointer == '.')
5665 input_line_pointer += 2;
5666
5667 demand_empty_rest_of_line ();
5668 }
5669
5670 /* Handle the MRI ENDW pseudo-op. */
5671
5672 static void
5673 s_mri_endw (ignore)
5674 int ignore;
5675 {
5676 char *buf;
5677
5678 if (mri_control_stack == NULL
5679 || mri_control_stack->type != mri_while)
5680 {
5681 as_bad ("endw without while");
5682 ignore_rest_of_line ();
5683 return;
5684 }
5685
5686 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
5687 sprintf (buf, "bra %s", mri_control_stack->next);
5688 md_assemble (buf);
5689 free (buf);
5690
5691 colon (mri_control_stack->bottom);
5692
5693 pop_mri_control ();
5694
5695 demand_empty_rest_of_line ();
5696 }
5697 \f
5698 /*
5699 * md_parse_option
5700 * Invocation line includes a switch not recognized by the base assembler.
5701 * See if it's a processor-specific option. These are:
5702 *
5703 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5704 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5705 * Select the architecture. Instructions or features not
5706 * supported by the selected architecture cause fatal
5707 * errors. More than one may be specified. The default is
5708 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5709 * for -m68000, and -m68882 is a synonym for -m68881.
5710 * -[A]m[c]no-68851, -[A]m[c]no-68881
5711 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5712 * so don't use or document it, but that's the way the parsing
5713 * works).
5714 *
5715 * -pic Indicates PIC.
5716 * -k Indicates PIC. (Sun 3 only.)
5717 *
5718 */
5719
5720 #ifdef OBJ_ELF
5721 CONST char *md_shortopts = "lSA:m:kQ:V";
5722 #else
5723 CONST char *md_shortopts = "lSA:m:k";
5724 #endif
5725
5726 struct option md_longopts[] = {
5727 #define OPTION_PIC (OPTION_MD_BASE)
5728 {"pic", no_argument, NULL, OPTION_PIC},
5729 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5730 {"register-prefix-optional", no_argument, NULL,
5731 OPTION_REGISTER_PREFIX_OPTIONAL},
5732 {NULL, no_argument, NULL, 0}
5733 };
5734 size_t md_longopts_size = sizeof(md_longopts);
5735
5736 int
5737 md_parse_option (c, arg)
5738 int c;
5739 char *arg;
5740 {
5741 switch (c)
5742 {
5743 case 'l': /* -l means keep external to 2 bit offset
5744 rather than 16 bit one */
5745 flag_short_refs = 1;
5746 break;
5747
5748 case 'S': /* -S means that jbsr's always turn into
5749 jsr's. */
5750 flag_long_jumps = 1;
5751 break;
5752
5753 case 'A':
5754 if (*arg == 'm')
5755 arg++;
5756 /* intentional fall-through */
5757 case 'm':
5758
5759 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
5760 {
5761 int i;
5762 unsigned long arch;
5763 const char *oarg = arg;
5764
5765 arg += 3;
5766 if (*arg == 'm')
5767 {
5768 arg++;
5769 if (arg[0] == 'c' && arg[1] == '6')
5770 arg++;
5771 }
5772 for (i = 0; i < n_archs; i++)
5773 if (!strcmp (arg, archs[i].name))
5774 break;
5775 if (i == n_archs)
5776 {
5777 unknown:
5778 as_bad ("unrecognized option `%s'", oarg);
5779 return 0;
5780 }
5781 arch = archs[i].arch;
5782 if (arch == m68881)
5783 no_68881 = 1;
5784 else if (arch == m68851)
5785 no_68851 = 1;
5786 else
5787 goto unknown;
5788 }
5789 else
5790 {
5791 int i;
5792
5793 if (arg[0] == 'c' && arg[1] == '6')
5794 arg++;
5795
5796 for (i = 0; i < n_archs; i++)
5797 if (!strcmp (arg, archs[i].name))
5798 {
5799 unsigned long arch = archs[i].arch;
5800 if (cpu_of_arch (arch))
5801 /* It's a cpu spec. */
5802 {
5803 current_architecture &= ~m68000up;
5804 current_architecture |= arch;
5805 }
5806 else if (arch == m68881)
5807 {
5808 current_architecture |= m68881;
5809 no_68881 = 0;
5810 }
5811 else if (arch == m68851)
5812 {
5813 current_architecture |= m68851;
5814 no_68851 = 0;
5815 }
5816 else
5817 /* ??? */
5818 abort ();
5819 break;
5820 }
5821 if (i == n_archs)
5822 {
5823 as_bad ("unrecognized architecture specification `%s'", arg);
5824 return 0;
5825 }
5826 }
5827 break;
5828
5829 case OPTION_PIC:
5830 case 'k':
5831 flag_want_pic = 1;
5832 break; /* -pic, Position Independent Code */
5833
5834 case OPTION_REGISTER_PREFIX_OPTIONAL:
5835 flag_reg_prefix_optional = 1;
5836 break;
5837
5838 case 'Q':
5839 case 'V':
5840 break;
5841
5842 default:
5843 return 0;
5844 }
5845
5846 return 1;
5847 }
5848
5849 void
5850 md_show_usage (stream)
5851 FILE *stream;
5852 {
5853 fprintf(stream, "\
5854 680X0 options:\n\
5855 -l use 1 word for refs to undefined symbols [default 2]\n\
5856 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5857 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5858 | -mcpu32\n\
5859 specify variant of 680X0 architecture [default 68020]\n\
5860 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5861 target has/lacks floating-point coprocessor\n\
5862 [default yes for 68020, 68030, and cpu32]\n");
5863 fprintf(stream, "\
5864 -m68851 | -mno-68851\n\
5865 target has/lacks memory-management unit coprocessor\n\
5866 [default yes for 68020 and up]\n\
5867 -pic, -k generate position independent code\n\
5868 -S turn jbsr into jsr\n\
5869 --register-prefix-optional\n\
5870 recognize register names without prefix character\n");
5871 }
5872 \f
5873 #ifdef TEST2
5874
5875 /* TEST2: Test md_assemble() */
5876 /* Warning, this routine probably doesn't work anymore */
5877
5878 main ()
5879 {
5880 struct m68k_it the_ins;
5881 char buf[120];
5882 char *cp;
5883 int n;
5884
5885 m68k_ip_begin ();
5886 for (;;)
5887 {
5888 if (!gets (buf) || !*buf)
5889 break;
5890 if (buf[0] == '|' || buf[1] == '.')
5891 continue;
5892 for (cp = buf; *cp; cp++)
5893 if (*cp == '\t')
5894 *cp = ' ';
5895 if (is_label (buf))
5896 continue;
5897 memset (&the_ins, '\0', sizeof (the_ins));
5898 m68k_ip (&the_ins, buf);
5899 if (the_ins.error)
5900 {
5901 printf ("Error %s in %s\n", the_ins.error, buf);
5902 }
5903 else
5904 {
5905 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5906 for (n = 0; n < the_ins.numo; n++)
5907 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5908 printf (" ");
5909 print_the_insn (&the_ins.opcode[0], stdout);
5910 (void) putchar ('\n');
5911 }
5912 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5913 {
5914 if (the_ins.operands[n].error)
5915 {
5916 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5917 continue;
5918 }
5919 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5920 if (the_ins.operands[n].b_const)
5921 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5922 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5923 if (the_ins.operands[n].b_iadd)
5924 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5925 (void) putchar ('\n');
5926 }
5927 }
5928 m68k_ip_end ();
5929 return 0;
5930 }
5931
5932 is_label (str)
5933 char *str;
5934 {
5935 while (*str == ' ')
5936 str++;
5937 while (*str && *str != ' ')
5938 str++;
5939 if (str[-1] == ':' || str[1] == '=')
5940 return 1;
5941 return 0;
5942 }
5943
5944 #endif
5945
5946 /* Possible states for relaxation:
5947
5948 0 0 branch offset byte (bra, etc)
5949 0 1 word
5950 0 2 long
5951
5952 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5953 1 1 word
5954 1 2 long
5955
5956 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5957 2 1 word-long
5958 2 2 long-word
5959 2 3 long-long
5960
5961 */
5962
5963 /* We have no need to default values of symbols. */
5964
5965 /* ARGSUSED */
5966 symbolS *
5967 md_undefined_symbol (name)
5968 char *name;
5969 {
5970 return 0;
5971 }
5972
5973 /* Round up a section size to the appropriate boundary. */
5974 valueT
5975 md_section_align (segment, size)
5976 segT segment;
5977 valueT size;
5978 {
5979 return size; /* Byte alignment is fine */
5980 }
5981
5982 /* Exactly what point is a PC-relative offset relative TO?
5983 On the 68k, it is relative to the address of the first extension
5984 word. The difference between the addresses of the offset and the
5985 first extension word is stored in fx_pcrel_adjust. */
5986 long
5987 md_pcrel_from (fixP)
5988 fixS *fixP;
5989 {
5990 int adjust;
5991
5992 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
5993 -1 as 64. */
5994 adjust = fixP->fx_pcrel_adjust;
5995 if (adjust == 64)
5996 adjust = -1;
5997 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
5998 }
5999
6000 #ifndef BFD_ASSEMBLER
6001 /*ARGSUSED*/
6002 void
6003 tc_coff_symbol_emit_hook (ignore)
6004 symbolS *ignore;
6005 {
6006 }
6007
6008 int
6009 tc_coff_sizemachdep (frag)
6010 fragS *frag;
6011 {
6012 switch (frag->fr_subtype & 0x3)
6013 {
6014 case BYTE:
6015 return 1;
6016 case SHORT:
6017 return 2;
6018 case LONG:
6019 return 4;
6020 default:
6021 abort ();
6022 return 0;
6023 }
6024 }
6025 #endif
6026
6027 /* end of tc-m68k.c */