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* read.c (read_a_source_file): In MRI mode, don't end the
[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #define NO_RELOC 0
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 /* This array holds the chars that always start a comment. If the
31 pre-processor is disabled, these aren't very useful */
32 #ifdef OBJ_ELF
33 CONST char comment_chars[] = "|#";
34 #else
35 CONST char comment_chars[] = "|";
36 #endif
37
38 /* This array holds the chars that only start a comment at the beginning of
39 a line. If the line seems to have the form '# 123 filename'
40 .line and .file directives will appear in the pre-processed output */
41 /* Note that input_file.c hand checks for '#' at the beginning of the
42 first line of the input file. This is because the compiler outputs
43 #NO_APP at the beginning of its output. */
44 /* Also note that comments like this one will always work. */
45 CONST char line_comment_chars[] = "#";
46
47 CONST char line_separator_chars[] = "";
48
49 /* Chars that can be used to separate mant from exp in floating point nums */
50 CONST char EXP_CHARS[] = "eE";
51
52 /* Chars that mean this number is a floating point constant, as
53 in "0f12.456" or "0d1.2345e12". */
54
55 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
56
57 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
58 changed in read.c . Ideally it shouldn't have to know about it at all,
59 but nothing is ideal around here. */
60
61 const int md_reloc_size = 8; /* Size of relocation record */
62
63 /* Are we trying to generate PIC code? If so, absolute references
64 ought to be made into linkage table references or pc-relative
65 references. */
66 int flag_want_pic;
67
68 static int flag_short_refs; /* -l option */
69 static int flag_long_jumps; /* -S option */
70
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 #else
74 int flag_reg_prefix_optional;
75 #endif
76
77 /* The floating point coprocessor to use by default. */
78 static enum m68k_register m68k_float_copnum = COP1;
79
80 /* If this is non-zero, then references to number(%pc) will be taken
81 to refer to number, rather than to %pc + number. */
82 static int m68k_abspcadd;
83
84 /* If this is non-zero, then the quick forms of the move, add, and sub
85 instructions are used when possible. */
86 static int m68k_quick = 1;
87
88 /* If this is non-zero, then if the size is not specified for a base
89 or outer displacement, the assembler assumes that the size should
90 be 32 bits. */
91 static int m68k_rel32 = 1;
92
93 /* Its an arbitrary name: This means I don't approve of it */
94 /* See flames below */
95 static struct obstack robyn;
96
97 #define TAB(x,y) (((x)<<2)+(y))
98 #define TABTYPE(xy) ((xy) >> 2)
99 #define BYTE 0
100 #define SHORT 1
101 #define LONG 2
102 #define SZ_UNDEF 3
103 #undef BRANCH
104 /* Case `g' except when BCC68000 is applicable. */
105 #define ABRANCH 1
106 /* Coprocessor branches. */
107 #define FBRANCH 2
108 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
109 supported on all cpus. Widens to 32-bit absolute. */
110 #define PCREL 3
111 /* For inserting an extra jmp instruction with long offset on 68000,
112 for expanding conditional branches. (Not bsr or bra.) Since the
113 68000 doesn't support 32-bit displacements for conditional
114 branches, we fake it by reversing the condition and branching
115 around a jmp with an absolute long operand. */
116 #define BCC68000 4
117 /* For the DBcc "instructions". If the displacement requires 32 bits,
118 the branch-around-a-jump game is played here too. */
119 #define DBCC 5
120 /* Not currently used? */
121 #define PCLEA 6
122 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
123 in 16 or 8 bits. */
124 #define PCINDEX 7
125
126 struct m68k_incant
127 {
128 const char *m_operands;
129 unsigned long m_opcode;
130 short m_opnum;
131 short m_codenum;
132 int m_arch;
133 struct m68k_incant *m_next;
134 };
135
136 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
137 #define gettwo(x) (((x)->m_opcode)&0xffff)
138
139 static const enum m68k_register m68000_control_regs[] = { 0 };
140 static const enum m68k_register m68010_control_regs[] = {
141 SFC, DFC, USP, VBR,
142 0
143 };
144 static const enum m68k_register m68020_control_regs[] = {
145 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
146 0
147 };
148 static const enum m68k_register m68040_control_regs[] = {
149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
150 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
151 0
152 };
153 static const enum m68k_register m68060_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
155 USP, VBR, URP, SRP, PCR,
156 0
157 };
158 #define cpu32_control_regs m68010_control_regs
159
160 static const enum m68k_register *control_regs;
161
162 /* internal form of a 68020 instruction */
163 struct m68k_it
164 {
165 const char *error;
166 const char *args; /* list of opcode info */
167 int numargs;
168
169 int numo; /* Number of shorts in opcode */
170 short opcode[11];
171
172 struct m68k_op operands[6];
173
174 int nexp; /* number of exprs in use */
175 struct m68k_exp exprs[4];
176
177 int nfrag; /* Number of frags we have to produce */
178 struct
179 {
180 int fragoff; /* Where in the current opcode the frag ends */
181 symbolS *fadd;
182 long foff;
183 int fragty;
184 }
185 fragb[4];
186
187 int nrel; /* Num of reloc strucs in use */
188 struct
189 {
190 int n;
191 expressionS exp;
192 char wid;
193 char pcrel;
194 /* In a pc relative address the difference between the address
195 of the offset and the address that the offset is relative
196 to. This depends on the addressing mode. Basically this
197 is the value to put in the offset field to address the
198 first byte of the offset, without regarding the special
199 significance of some values (in the branch instruction, for
200 example). */
201 int pcrel_fix;
202 }
203 reloc[5]; /* Five is enough??? */
204 };
205
206 #define cpu_of_arch(x) ((x) & m68000up)
207 #define float_of_arch(x) ((x) & mfloat)
208 #define mmu_of_arch(x) ((x) & mmmu)
209
210 static struct m68k_it the_ins; /* the instruction being assembled */
211
212 #define op(ex) ((ex)->exp.X_op)
213 #define adds(ex) ((ex)->exp.X_add_symbol)
214 #define subs(ex) ((ex)->exp.X_op_symbol)
215 #define offs(ex) ((ex)->exp.X_add_number)
216
217 /* Macros for adding things to the m68k_it struct */
218
219 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
220
221 /* Like addword, but goes BEFORE general operands */
222 static void
223 insop (w, opcode)
224 int w;
225 struct m68k_incant *opcode;
226 {
227 int z;
228 for(z=the_ins.numo;z>opcode->m_codenum;--z)
229 the_ins.opcode[z]=the_ins.opcode[z-1];
230 for(z=0;z<the_ins.nrel;z++)
231 the_ins.reloc[z].n+=2;
232 for (z = 0; z < the_ins.nfrag; z++)
233 the_ins.fragb[z].fragoff++;
234 the_ins.opcode[opcode->m_codenum]=w;
235 the_ins.numo++;
236 }
237
238 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
239 Blecch. */
240 static void
241 add_fix (width, exp, pc_rel, pc_fix)
242 char width;
243 struct m68k_exp *exp;
244 int pc_rel;
245 int pc_fix;
246 {
247 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
248 ? (the_ins.numo*2-1)
249 : (((width)=='b')
250 ? (the_ins.numo*2+1)
251 : (the_ins.numo*2)));
252 the_ins.reloc[the_ins.nrel].exp = exp->exp;
253 the_ins.reloc[the_ins.nrel].wid = width;
254 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
255 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
256 }
257
258 /* Cause an extra frag to be generated here, inserting up to 10 bytes
259 (that value is chosen in the frag_var call in md_assemble). TYPE
260 is the subtype of the frag to be generated; its primary type is
261 rs_machine_dependent.
262
263 The TYPE parameter is also used by md_convert_frag_1 and
264 md_estimate_size_before_relax. The appropriate type of fixup will
265 be emitted by md_convert_frag_1.
266
267 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
268 static void
269 add_frag(add,off,type)
270 symbolS *add;
271 long off;
272 int type;
273 {
274 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
275 the_ins.fragb[the_ins.nfrag].fadd=add;
276 the_ins.fragb[the_ins.nfrag].foff=off;
277 the_ins.fragb[the_ins.nfrag++].fragty=type;
278 }
279
280 #define isvar(ex) \
281 (op (ex) != O_constant && op (ex) != O_big)
282
283 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
284 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
285 static int reverse_16_bits PARAMS ((int in));
286 static int reverse_8_bits PARAMS ((int in));
287 static void install_gen_operand PARAMS ((int mode, int val));
288 static void install_operand PARAMS ((int mode, int val));
289 static void s_bss PARAMS ((int));
290 static void s_data1 PARAMS ((int));
291 static void s_data2 PARAMS ((int));
292 static void s_even PARAMS ((int));
293 static void s_proc PARAMS ((int));
294 static void mri_chip PARAMS ((void));
295 static void s_chip PARAMS ((int));
296 static void s_fopt PARAMS ((int));
297 static void s_opt PARAMS ((int));
298 static void s_reg PARAMS ((int));
299 static void s_restore PARAMS ((int));
300 static void s_save PARAMS ((int));
301 static void s_mri_if PARAMS ((int));
302 static void s_mri_else PARAMS ((int));
303 static void s_mri_endi PARAMS ((int));
304 static void s_mri_break PARAMS ((int));
305 static void s_mri_next PARAMS ((int));
306 static void s_mri_for PARAMS ((int));
307 static void s_mri_endf PARAMS ((int));
308 static void s_mri_repeat PARAMS ((int));
309 static void s_mri_until PARAMS ((int));
310 static void s_mri_while PARAMS ((int));
311 static void s_mri_endw PARAMS ((int));
312
313 static int current_architecture;
314
315 struct m68k_cpu {
316 unsigned long arch;
317 const char *name;
318 };
319
320 static const struct m68k_cpu archs[] = {
321 { m68000, "68000" },
322 { m68010, "68010" },
323 { m68020, "68020" },
324 { m68030, "68030" },
325 { m68040, "68040" },
326 { m68060, "68060" },
327 { cpu32, "cpu32" },
328 { m68881, "68881" },
329 { m68851, "68851" },
330 /* Aliases (effectively, so far as gas is concerned) for the above
331 cpus. */
332 { m68020, "68k" },
333 { m68000, "68302" },
334 { m68000, "68008" },
335 { m68000, "68ec000" },
336 { m68000, "68hc000" },
337 { m68000, "68hc001" },
338 { m68020, "68ec020" },
339 { m68030, "68ec030" },
340 { m68040, "68ec040" },
341 { cpu32, "68330" },
342 { cpu32, "68331" },
343 { cpu32, "68332" },
344 { cpu32, "68333" },
345 { cpu32, "68340" },
346 { cpu32, "68360" },
347 { m68881, "68882" },
348 };
349
350 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
351
352 /* BCC68000 is for patching in an extra jmp instruction for long offsets
353 on the 68000. The 68000 doesn't support long branches with branchs */
354
355 /* This table desribes how you change sizes for the various types of variable
356 size expressions. This version only supports two kinds. */
357
358 /* Note that calls to frag_var need to specify the maximum expansion
359 needed; this is currently 10 bytes for DBCC. */
360
361 /* The fields are:
362 How far Forward this mode will reach:
363 How far Backward this mode will reach:
364 How many bytes this mode will add to the size of the frag
365 Which mode to go to if the offset won't fit in this one
366 */
367 relax_typeS md_relax_table[] =
368 {
369 {1, 1, 0, 0}, /* First entries aren't used */
370 {1, 1, 0, 0}, /* For no good reason except */
371 {1, 1, 0, 0}, /* that the VAX doesn't either */
372 {1, 1, 0, 0},
373
374 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
375 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
376 {0, 0, 4, 0},
377 {1, 1, 0, 0},
378
379 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
380 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
381 {0, 0, 4, 0},
382 {1, 1, 0, 0},
383
384 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
385 {(32767), (-32768), 2, TAB (PCREL, LONG)},
386 {0, 0, 4, 0},
387 {1, 1, 0, 0},
388
389 {(127), (-128), 0, TAB (BCC68000, SHORT)},
390 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
391 {0, 0, 6, 0}, /* jmp long space */
392 {1, 1, 0, 0},
393
394 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
395 {(32767), (-32768), 2, TAB (DBCC, LONG)},
396 {0, 0, 10, 0}, /* bra/jmp long space */
397 {1, 1, 0, 0},
398
399 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
400 {32767, -32768, 2, TAB (PCLEA, LONG)},
401 {0, 0, 6, 0},
402 {1, 1, 0, 0},
403
404 /* For, e.g., jmp pcrel indexed. */
405 {125, -130, 0, TAB (PCINDEX, SHORT)},
406 {32765, -32770, 2, TAB (PCINDEX, LONG)},
407 {0, 0, 4, 0},
408 {1, 1, 0, 0},
409 };
410
411 /* These are the machine dependent pseudo-ops. These are included so
412 the assembler can work on the output from the SUN C compiler, which
413 generates these.
414 */
415
416 /* This table describes all the machine specific pseudo-ops the assembler
417 has to support. The fields are:
418 pseudo-op name without dot
419 function to call to execute this pseudo-op
420 Integer arg to pass to the function
421 */
422 CONST pseudo_typeS md_pseudo_table[] =
423 {
424 {"data1", s_data1, 0},
425 {"data2", s_data2, 0},
426 {"bss", s_bss, 0},
427 {"even", s_even, 0},
428 {"skip", s_space, 0},
429 {"proc", s_proc, 0},
430 #ifdef TE_SUN3
431 {"align", s_align_bytes, 0},
432 #endif
433 #ifdef OBJ_ELF
434 {"swbeg", s_ignore, 0},
435 #endif
436
437 /* The following pseudo-ops are supported for MRI compatibility. */
438 {"chip", s_chip, 0},
439 {"comline", s_space, 1},
440 {"fopt", s_fopt, 0},
441 {"mask2", s_ignore, 0},
442 {"opt", s_opt, 0},
443 {"reg", s_reg, 0},
444 {"restore", s_restore, 0},
445 {"save", s_save, 0},
446
447 {"if", s_mri_if, 0},
448 {"if.b", s_mri_if, 'b'},
449 {"if.w", s_mri_if, 'w'},
450 {"if.l", s_mri_if, 'l'},
451 {"else", s_mri_else, 0},
452 {"else.s", s_mri_else, 's'},
453 {"else.l", s_mri_else, 'l'},
454 {"endi", s_mri_endi, 0},
455 {"break", s_mri_break, 0},
456 {"break.s", s_mri_break, 's'},
457 {"break.l", s_mri_break, 'l'},
458 {"next", s_mri_next, 0},
459 {"next.s", s_mri_next, 's'},
460 {"next.l", s_mri_next, 'l'},
461 {"for", s_mri_for, 0},
462 {"for.b", s_mri_for, 'b'},
463 {"for.w", s_mri_for, 'w'},
464 {"for.l", s_mri_for, 'l'},
465 {"endf", s_mri_endf, 0},
466 {"repeat", s_mri_repeat, 0},
467 {"until", s_mri_until, 0},
468 {"until.b", s_mri_until, 'b'},
469 {"until.w", s_mri_until, 'w'},
470 {"until.l", s_mri_until, 'l'},
471 {"while", s_mri_while, 0},
472 {"while.b", s_mri_while, 'b'},
473 {"while.w", s_mri_while, 'w'},
474 {"while.l", s_mri_while, 'l'},
475 {"endw", s_mri_endw, 0},
476
477 {0, 0, 0}
478 };
479
480
481 /* The mote pseudo ops are put into the opcode table, since they
482 don't start with a . they look like opcodes to gas.
483 */
484 extern void obj_coff_section ();
485
486 CONST pseudo_typeS mote_pseudo_table[] =
487 {
488
489 {"dcl", cons, 4},
490 {"dc", cons, 2},
491 {"dcw", cons, 2},
492 {"dcb", cons, 1},
493
494 {"dsl", s_space, 4},
495 {"ds", s_space, 2},
496 {"dsw", s_space, 2},
497 {"dsb", s_space, 1},
498
499 {"xdef", s_globl, 0},
500 {"align", s_align_ptwo, 0},
501 #ifdef M68KCOFF
502 {"sect", obj_coff_section, 0},
503 {"section", obj_coff_section, 0},
504 #endif
505 {0, 0, 0}
506 };
507
508 #define issbyte(x) ((x)>=-128 && (x)<=127)
509 #define isubyte(x) ((x)>=0 && (x)<=255)
510 #define issword(x) ((x)>=-32768 && (x)<=32767)
511 #define isuword(x) ((x)>=0 && (x)<=65535)
512
513 #define isbyte(x) ((x)>= -255 && (x)<=255)
514 #define isword(x) ((x)>=-32768 && (x)<=65535)
515 #define islong(x) (1)
516
517 extern char *input_line_pointer;
518
519 static char mklower_table[256];
520 #define mklower(c) (mklower_table[(unsigned char)(c)])
521 static char notend_table[256];
522 static char alt_notend_table[256];
523 #define notend(s) \
524 (! (notend_table[(unsigned char) *s] \
525 || (*s == ':' \
526 && alt_notend_table[(unsigned char) s[1]])))
527
528 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
529
530 #ifdef NO_PCREL_RELOCS
531
532 int
533 make_pcrel_absolute(fixP, add_number)
534 fixS *fixP;
535 long *add_number;
536 {
537 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
538
539 /* rewrite the PC relative instructions to absolute address ones.
540 * these are rumoured to be faster, and the apollo linker refuses
541 * to deal with the PC relative relocations.
542 */
543 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
544 {
545 opcode[0] = 0x4e;
546 opcode[1] = 0xf9;
547 }
548 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
549 {
550 opcode[0] = 0x4e;
551 opcode[1] = 0xb9;
552 }
553 else
554 as_fatal ("Unknown PC relative instruction");
555 *add_number -= 4;
556 return 0;
557 }
558
559 #endif /* NO_PCREL_RELOCS */
560
561 short
562 tc_coff_fix2rtype (fixP)
563 fixS *fixP;
564 {
565 #ifdef NO_PCREL_RELOCS
566 know (fixP->fx_pcrel == 0);
567 return (fixP->fx_size == 1 ? R_RELBYTE
568 : fixP->fx_size == 2 ? R_DIR16
569 : R_DIR32);
570 #else
571 return (fixP->fx_pcrel ?
572 (fixP->fx_size == 1 ? R_PCRBYTE :
573 fixP->fx_size == 2 ? R_PCRWORD :
574 R_PCRLONG) :
575 (fixP->fx_size == 1 ? R_RELBYTE :
576 fixP->fx_size == 2 ? R_RELWORD :
577 R_RELLONG));
578 #endif
579 }
580
581 #endif
582
583 #ifdef BFD_ASSEMBLER
584
585 arelent *
586 tc_gen_reloc (section, fixp)
587 asection *section;
588 fixS *fixp;
589 {
590 arelent *reloc;
591 bfd_reloc_code_real_type code;
592
593 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
594 switch (F (fixp->fx_size, fixp->fx_pcrel))
595 {
596 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
597 MAP (1, 0, BFD_RELOC_8);
598 MAP (2, 0, BFD_RELOC_16);
599 MAP (4, 0, BFD_RELOC_32);
600 MAP (1, 1, BFD_RELOC_8_PCREL);
601 MAP (2, 1, BFD_RELOC_16_PCREL);
602 MAP (4, 1, BFD_RELOC_32_PCREL);
603 default:
604 abort ();
605 }
606
607 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
608 assert (reloc != 0);
609 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
610 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
611 if (fixp->fx_pcrel)
612 reloc->addend = fixp->fx_addnumber;
613 else
614 reloc->addend = 0;
615
616 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
617 assert (reloc->howto != 0);
618
619 return reloc;
620 }
621
622 #endif /* BFD_ASSEMBLER */
623
624 /* Handle of the OPCODE hash table. NULL means any use before
625 m68k_ip_begin() will crash. */
626 static struct hash_control *op_hash;
627 \f
628 /* Assemble an m68k instruction. */
629
630 void
631 m68k_ip (instring)
632 char *instring;
633 {
634 register char *p;
635 register struct m68k_op *opP;
636 register struct m68k_incant *opcode;
637 register const char *s;
638 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
639 char *pdot, *pdotmove;
640 enum m68k_size siz1, siz2;
641 char c;
642 int losing;
643 int opsfound;
644 char *crack_operand ();
645 LITTLENUM_TYPE words[6];
646 LITTLENUM_TYPE *wordp;
647 unsigned long ok_arch = 0;
648
649 if (*instring == ' ')
650 instring++; /* skip leading whitespace */
651
652 /* Scan up to end of operation-code, which MUST end in end-of-string
653 or exactly 1 space. */
654 pdot = 0;
655 for (p = instring; *p != '\0'; p++)
656 {
657 if (*p == ' ')
658 break;
659 if (*p == '.')
660 pdot = p;
661 }
662
663 if (p == instring)
664 {
665 the_ins.error = "No operator";
666 return;
667 }
668
669 /* p now points to the end of the opcode name, probably whitespace.
670 Make sure the name is null terminated by clobbering the
671 whitespace, look it up in the hash table, then fix it back.
672 Remove a dot, first, since the opcode tables have none. */
673 if (pdot != NULL)
674 {
675 for (pdotmove = pdot; pdotmove < p; pdotmove++)
676 *pdotmove = pdotmove[1];
677 p--;
678 }
679
680 c = *p;
681 *p = '\0';
682 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
683 *p = c;
684
685 if (pdot != NULL)
686 {
687 for (pdotmove = p; pdotmove > pdot; pdotmove--)
688 *pdotmove = pdotmove[-1];
689 *pdot = '.';
690 ++p;
691 }
692
693 if (opcode == NULL)
694 {
695 the_ins.error = "Unknown operator";
696 return;
697 }
698
699 /* found a legitimate opcode, start matching operands */
700 while (*p == ' ')
701 ++p;
702
703 if (opcode->m_operands == 0)
704 {
705 char *old = input_line_pointer;
706 *old = '\n';
707 input_line_pointer = p;
708 /* Ahh - it's a motorola style psuedo op */
709 mote_pseudo_table[opcode->m_opnum].poc_handler
710 (mote_pseudo_table[opcode->m_opnum].poc_val);
711 input_line_pointer = old;
712 *old = 0;
713
714 return;
715 }
716
717 for (opP = &the_ins.operands[0]; *p; opP++)
718 {
719 p = crack_operand (p, opP);
720
721 if (opP->error)
722 {
723 the_ins.error = opP->error;
724 return;
725 }
726 }
727
728 opsfound = opP - &the_ins.operands[0];
729
730 /* This ugly hack is to support the floating pt opcodes in their
731 standard form. Essentially, we fake a first enty of type COP#1 */
732 if (opcode->m_operands[0] == 'I')
733 {
734 int n;
735
736 for (n = opsfound; n > 0; --n)
737 the_ins.operands[n] = the_ins.operands[n - 1];
738
739 memset ((char *) (&the_ins.operands[0]), '\0',
740 sizeof (the_ins.operands[0]));
741 the_ins.operands[0].mode = CONTROL;
742 the_ins.operands[0].reg = m68k_float_copnum;
743 opsfound++;
744 }
745
746 /* We've got the operands. Find an opcode that'll accept them */
747 for (losing = 0;;)
748 {
749 /* If we didn't get the right number of ops, or we have no
750 common model with this pattern then reject this pattern. */
751
752 if (opsfound != opcode->m_opnum
753 || ((opcode->m_arch & current_architecture) == 0))
754 {
755 ++losing;
756 ok_arch |= opcode->m_arch;
757 }
758 else
759 {
760 for (s = opcode->m_operands, opP = &the_ins.operands[0];
761 *s && !losing;
762 s += 2, opP++)
763 {
764 /* Warning: this switch is huge! */
765 /* I've tried to organize the cases into this order:
766 non-alpha first, then alpha by letter. Lower-case
767 goes directly before uppercase counterpart. */
768 /* Code with multiple case ...: gets sorted by the lowest
769 case ... it belongs to. I hope this makes sense. */
770 switch (*s)
771 {
772 case '!':
773 switch (opP->mode)
774 {
775 case IMMED:
776 case DREG:
777 case AREG:
778 case FPREG:
779 case CONTROL:
780 case AINC:
781 case ADEC:
782 case REGLST:
783 losing++;
784 break;
785 default:
786 break;
787 }
788 break;
789
790 case '`':
791 switch (opP->mode)
792 {
793 case IMMED:
794 case DREG:
795 case AREG:
796 case FPREG:
797 case CONTROL:
798 case AINC:
799 case REGLST:
800 case AINDR:
801 losing++;
802 break;
803 default:
804 break;
805 }
806 break;
807
808 case '#':
809 if (opP->mode != IMMED)
810 losing++;
811 else if (s[1] == 'b'
812 && ! isvar (&opP->disp)
813 && (opP->disp.exp.X_op != O_constant
814 || ! isbyte (opP->disp.exp.X_add_number)))
815 losing++;
816 else if (s[1] == 'w'
817 && ! isvar (&opP->disp)
818 && (opP->disp.exp.X_op != O_constant
819 || ! isword (opP->disp.exp.X_add_number)))
820 losing++;
821 break;
822
823 case '^':
824 case 'T':
825 if (opP->mode != IMMED)
826 losing++;
827 break;
828
829 case '$':
830 if (opP->mode == AREG
831 || opP->mode == CONTROL
832 || opP->mode == FPREG
833 || opP->mode == IMMED
834 || opP->mode == REGLST
835 || (opP->mode != ABSL
836 && (opP->reg == PC
837 || opP->reg == ZPC)))
838 losing++;
839 break;
840
841 case '%':
842 if (opP->mode == CONTROL
843 || opP->mode == FPREG
844 || opP->mode == REGLST
845 || (opP->mode != ABSL
846 && opP->mode != IMMED
847 && (opP->reg == PC
848 || opP->reg == ZPC)))
849 losing++;
850 break;
851
852 case '&':
853 switch (opP->mode)
854 {
855 case DREG:
856 case AREG:
857 case FPREG:
858 case CONTROL:
859 case IMMED:
860 case AINC:
861 case ADEC:
862 case REGLST:
863 losing++;
864 break;
865 case ABSL:
866 break;
867 default:
868 if (opP->reg == PC
869 || opP->reg == ZPC)
870 losing++;
871 break;
872 }
873 break;
874
875 case '*':
876 if (opP->mode == CONTROL
877 || opP->mode == FPREG
878 || opP->mode == REGLST)
879 losing++;
880 break;
881
882 case '+':
883 if (opP->mode != AINC)
884 losing++;
885 break;
886
887 case '-':
888 if (opP->mode != ADEC)
889 losing++;
890 break;
891
892 case '/':
893 switch (opP->mode)
894 {
895 case AREG:
896 case CONTROL:
897 case FPREG:
898 case AINC:
899 case ADEC:
900 case IMMED:
901 case REGLST:
902 losing++;
903 break;
904 default:
905 break;
906 }
907 break;
908
909 case ';':
910 switch (opP->mode)
911 {
912 case AREG:
913 case CONTROL:
914 case FPREG:
915 case REGLST:
916 losing++;
917 break;
918 default:
919 break;
920 }
921 break;
922
923 case '?':
924 switch (opP->mode)
925 {
926 case AREG:
927 case CONTROL:
928 case FPREG:
929 case AINC:
930 case ADEC:
931 case IMMED:
932 case REGLST:
933 losing++;
934 break;
935 case ABSL:
936 break;
937 default:
938 if (opP->reg == PC || opP->reg == ZPC)
939 losing++;
940 break;
941 }
942 break;
943
944 case '@':
945 switch (opP->mode)
946 {
947 case AREG:
948 case CONTROL:
949 case FPREG:
950 case IMMED:
951 case REGLST:
952 losing++;
953 break;
954 default:
955 break;
956 }
957 break;
958
959 case '~': /* For now! (JF FOO is this right?) */
960 switch (opP->mode)
961 {
962 case DREG:
963 case AREG:
964 case CONTROL:
965 case FPREG:
966 case IMMED:
967 case REGLST:
968 losing++;
969 break;
970 case ABSL:
971 break;
972 default:
973 if (opP->reg == PC
974 || opP->reg == ZPC)
975 losing++;
976 break;
977 }
978 break;
979
980 case '3':
981 if (opP->mode != CONTROL
982 || (opP->reg != TT0 && opP->reg != TT1))
983 losing++;
984 break;
985
986 case 'A':
987 if (opP->mode != AREG)
988 losing++;
989 break;
990
991 case 'a':
992 if (opP->mode != AINDR)
993 ++losing;
994 break;
995
996 case 'B': /* FOO */
997 if (opP->mode != ABSL
998 || (flag_long_jumps
999 && strncmp (instring, "jbsr", 4) == 0))
1000 losing++;
1001 break;
1002
1003 case 'C':
1004 if (opP->mode != CONTROL || opP->reg != CCR)
1005 losing++;
1006 break;
1007
1008 case 'd':
1009 if (opP->mode != DISP
1010 || opP->reg < ADDR0
1011 || opP->reg > ADDR7)
1012 losing++;
1013 break;
1014
1015 case 'D':
1016 if (opP->mode != DREG)
1017 losing++;
1018 break;
1019
1020 case 'F':
1021 if (opP->mode != FPREG)
1022 losing++;
1023 break;
1024
1025 case 'I':
1026 if (opP->mode != CONTROL
1027 || opP->reg < COP0
1028 || opP->reg > COP7)
1029 losing++;
1030 break;
1031
1032 case 'J':
1033 if (opP->mode != CONTROL
1034 || opP->reg < USP
1035 || opP->reg > last_movec_reg)
1036 losing++;
1037 else
1038 {
1039 const enum m68k_register *rp;
1040 for (rp = control_regs; *rp; rp++)
1041 if (*rp == opP->reg)
1042 break;
1043 if (*rp == 0)
1044 losing++;
1045 }
1046 break;
1047
1048 case 'k':
1049 if (opP->mode != IMMED)
1050 losing++;
1051 break;
1052
1053 case 'l':
1054 case 'L':
1055 if (opP->mode == DREG
1056 || opP->mode == AREG
1057 || opP->mode == FPREG)
1058 {
1059 if (s[1] == '8')
1060 losing++;
1061 else
1062 {
1063 switch (opP->mode)
1064 {
1065 case DREG:
1066 opP->mask = 1 << (opP->reg - DATA0);
1067 break;
1068 case AREG:
1069 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1070 break;
1071 case FPREG:
1072 opP->mask = 1 << (opP->reg - FP0 + 16);
1073 break;
1074 default:
1075 abort ();
1076 }
1077 opP->mode = REGLST;
1078 }
1079 }
1080 else if (opP->mode == CONTROL)
1081 {
1082 if (s[1] != '8')
1083 losing++;
1084 else
1085 {
1086 switch (opP->reg)
1087 {
1088 case FPI:
1089 opP->mask = 1 << 24;
1090 break;
1091 case FPS:
1092 opP->mask = 1 << 25;
1093 break;
1094 case FPC:
1095 opP->mask = 1 << 26;
1096 break;
1097 default:
1098 losing++;
1099 break;
1100 }
1101 opP->mode = REGLST;
1102 }
1103 }
1104 else if (opP->mode == ABSL
1105 && opP->disp.size == SIZE_UNSPEC
1106 && opP->disp.exp.X_op == O_constant)
1107 {
1108 /* This is what the MRI REG pseudo-op generates. */
1109 opP->mode = REGLST;
1110 opP->mask = opP->disp.exp.X_add_number;
1111 }
1112 else if (opP->mode != REGLST)
1113 losing++;
1114 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1115 losing++;
1116 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1117 losing++;
1118 break;
1119
1120 case 'M':
1121 if (opP->mode != IMMED)
1122 losing++;
1123 else if (opP->disp.exp.X_op != O_constant
1124 || ! issbyte (opP->disp.exp.X_add_number))
1125 losing++;
1126 else if (! m68k_quick
1127 && instring[3] != 'q'
1128 && instring[4] != 'q')
1129 losing++;
1130 break;
1131
1132 case 'O':
1133 if (opP->mode != DREG && opP->mode != IMMED)
1134 losing++;
1135 break;
1136
1137 case 'Q':
1138 if (opP->mode != IMMED)
1139 losing++;
1140 else if (opP->disp.exp.X_op != O_constant
1141 || opP->disp.exp.X_add_number < 1
1142 || opP->disp.exp.X_add_number > 8)
1143 losing++;
1144 else if (! m68k_quick
1145 && (strncmp (instring, "add", 3) == 0
1146 || strncmp (instring, "sub", 3) == 0)
1147 && instring[3] != 'q')
1148 losing++;
1149 break;
1150
1151 case 'R':
1152 if (opP->mode != DREG && opP->mode != AREG)
1153 losing++;
1154 break;
1155
1156 case 'r':
1157 if (opP->mode != AINDR
1158 && (opP->mode != BASE
1159 || (opP->reg != 0
1160 && opP->reg != ZADDR0)
1161 || opP->disp.exp.X_op != O_absent
1162 || ((opP->index.reg < DATA0
1163 || opP->index.reg > DATA7)
1164 && (opP->index.reg < ADDR0
1165 || opP->index.reg > ADDR7))
1166 || opP->index.size != SIZE_UNSPEC
1167 || opP->index.scale != 1))
1168 losing++;
1169 break;
1170
1171 case 's':
1172 if (opP->mode != CONTROL
1173 || ! (opP->reg == FPI
1174 || opP->reg == FPS
1175 || opP->reg == FPC))
1176 losing++;
1177 break;
1178
1179 case 'S':
1180 if (opP->mode != CONTROL || opP->reg != SR)
1181 losing++;
1182 break;
1183
1184 case 't':
1185 if (opP->mode != IMMED)
1186 losing++;
1187 else if (opP->disp.exp.X_op != O_constant
1188 || opP->disp.exp.X_add_number < 0
1189 || opP->disp.exp.X_add_number > 7)
1190 losing++;
1191 break;
1192
1193 case 'U':
1194 if (opP->mode != CONTROL || opP->reg != USP)
1195 losing++;
1196 break;
1197
1198 /* JF these are out of order. We could put them
1199 in order if we were willing to put up with
1200 bunches of #ifdef m68851s in the code.
1201
1202 Don't forget that you need these operands
1203 to use 68030 MMU instructions. */
1204 #ifndef NO_68851
1205 /* Memory addressing mode used by pflushr */
1206 case '|':
1207 if (opP->mode == CONTROL
1208 || opP->mode == FPREG
1209 || opP->mode == DREG
1210 || opP->mode == AREG
1211 || opP->mode == REGLST)
1212 losing++;
1213 break;
1214
1215 case 'f':
1216 if (opP->mode != CONTROL
1217 || (opP->reg != SFC && opP->reg != DFC))
1218 losing++;
1219 break;
1220
1221 case 'P':
1222 if (opP->mode != CONTROL
1223 || (opP->reg != TC
1224 && opP->reg != CAL
1225 && opP->reg != VAL
1226 && opP->reg != SCC
1227 && opP->reg != AC))
1228 losing++;
1229 break;
1230
1231 case 'V':
1232 if (opP->mode != CONTROL
1233 || opP->reg != VAL)
1234 losing++;
1235 break;
1236
1237 case 'W':
1238 if (opP->mode != CONTROL
1239 || (opP->reg != DRP
1240 && opP->reg != SRP
1241 && opP->reg != CRP))
1242 losing++;
1243 break;
1244
1245 case 'X':
1246 if (opP->mode != CONTROL
1247 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1248 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1249 losing++;
1250 break;
1251
1252 case 'Y':
1253 if (opP->mode != CONTROL || opP->reg != PSR)
1254 losing++;
1255 break;
1256
1257 case 'Z':
1258 if (opP->mode != CONTROL || opP->reg != PCSR)
1259 losing++;
1260 break;
1261 #endif
1262 case 'c':
1263 if (opP->mode != CONTROL
1264 || (opP->reg != NC
1265 && opP->reg != IC
1266 && opP->reg != DC
1267 && opP->reg != BC))
1268 {
1269 losing++;
1270 } /* not a cache specifier. */
1271 break;
1272
1273 case '_':
1274 if (opP->mode != ABSL)
1275 ++losing;
1276 break;
1277
1278 default:
1279 abort ();
1280 } /* switch on type of operand */
1281
1282 if (losing)
1283 break;
1284 } /* for each operand */
1285 } /* if immediately wrong */
1286
1287 if (!losing)
1288 {
1289 break;
1290 } /* got it. */
1291
1292 opcode = opcode->m_next;
1293
1294 if (!opcode)
1295 {
1296 if (ok_arch
1297 && !(ok_arch & current_architecture))
1298 {
1299 char buf[200], *cp;
1300 int len;
1301 strcpy (buf,
1302 "invalid instruction for this architecture; needs ");
1303 cp = buf + strlen (buf);
1304 switch (ok_arch)
1305 {
1306 case mfloat:
1307 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1308 break;
1309 case mmmu:
1310 strcpy (cp, "mmu (68030 or 68851)");
1311 break;
1312 case m68020up:
1313 strcpy (cp, "68020 or higher");
1314 break;
1315 case m68000up:
1316 strcpy (cp, "68000 or higher");
1317 break;
1318 case m68010up:
1319 strcpy (cp, "68010 or higher");
1320 break;
1321 default:
1322 {
1323 int got_one = 0, idx;
1324 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1325 idx++)
1326 {
1327 if (archs[idx].arch & ok_arch)
1328 {
1329 if (got_one)
1330 {
1331 strcpy (cp, " or ");
1332 cp += strlen (cp);
1333 }
1334 got_one = 1;
1335 strcpy (cp, archs[idx].name);
1336 cp += strlen (cp);
1337 }
1338 }
1339 }
1340 }
1341 len = cp - buf + 1;
1342 cp = malloc (len);
1343 strcpy (cp, buf);
1344 the_ins.error = cp;
1345 }
1346 else
1347 the_ins.error = "operands mismatch";
1348 return;
1349 } /* Fell off the end */
1350
1351 losing = 0;
1352 }
1353
1354 /* now assemble it */
1355
1356 the_ins.args = opcode->m_operands;
1357 the_ins.numargs = opcode->m_opnum;
1358 the_ins.numo = opcode->m_codenum;
1359 the_ins.opcode[0] = getone (opcode);
1360 the_ins.opcode[1] = gettwo (opcode);
1361
1362 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1363 {
1364 /* This switch is a doozy.
1365 Watch the first step; its a big one! */
1366 switch (s[0])
1367 {
1368
1369 case '*':
1370 case '~':
1371 case '%':
1372 case ';':
1373 case '@':
1374 case '!':
1375 case '&':
1376 case '$':
1377 case '?':
1378 case '/':
1379 case '`':
1380 #ifndef NO_68851
1381 case '|':
1382 #endif
1383 switch (opP->mode)
1384 {
1385 case IMMED:
1386 tmpreg = 0x3c; /* 7.4 */
1387 if (strchr ("bwl", s[1]))
1388 nextword = get_num (&opP->disp, 80);
1389 else
1390 nextword = get_num (&opP->disp, 0);
1391 if (isvar (&opP->disp))
1392 add_fix (s[1], &opP->disp, 0, 0);
1393 switch (s[1])
1394 {
1395 case 'b':
1396 if (!isbyte (nextword))
1397 opP->error = "operand out of range";
1398 addword (nextword);
1399 baseo = 0;
1400 break;
1401 case 'w':
1402 if (!isword (nextword))
1403 opP->error = "operand out of range";
1404 addword (nextword);
1405 baseo = 0;
1406 break;
1407 case 'l':
1408 addword (nextword >> 16);
1409 addword (nextword);
1410 baseo = 0;
1411 break;
1412
1413 case 'f':
1414 baseo = 2;
1415 outro = 8;
1416 break;
1417 case 'F':
1418 baseo = 4;
1419 outro = 11;
1420 break;
1421 case 'x':
1422 baseo = 6;
1423 outro = 15;
1424 break;
1425 case 'p':
1426 baseo = 6;
1427 outro = -1;
1428 break;
1429 default:
1430 abort ();
1431 }
1432 if (!baseo)
1433 break;
1434
1435 /* We gotta put out some float */
1436 if (op (&opP->disp) != O_big)
1437 {
1438 valueT val;
1439 int gencnt;
1440
1441 /* Can other cases happen here? */
1442 if (op (&opP->disp) != O_constant)
1443 abort ();
1444
1445 val = (valueT) offs (&opP->disp);
1446 gencnt = 0;
1447 do
1448 {
1449 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1450 val >>= LITTLENUM_NUMBER_OF_BITS;
1451 ++gencnt;
1452 }
1453 while (val != 0);
1454 offs (&opP->disp) = gencnt;
1455 }
1456 if (offs (&opP->disp) > 0)
1457 {
1458 if (offs (&opP->disp) > baseo)
1459 {
1460 as_warn ("Bignum too big for %c format; truncated",
1461 s[1]);
1462 offs (&opP->disp) = baseo;
1463 }
1464 baseo -= offs (&opP->disp);
1465 while (baseo--)
1466 addword (0);
1467 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1468 offs (&opP->disp)--;
1469 --wordp)
1470 addword (*wordp);
1471 break;
1472 }
1473 gen_to_words (words, baseo, (long) outro);
1474 for (wordp = words; baseo--; wordp++)
1475 addword (*wordp);
1476 break;
1477 case DREG:
1478 tmpreg = opP->reg - DATA; /* 0.dreg */
1479 break;
1480 case AREG:
1481 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1482 break;
1483 case AINDR:
1484 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1485 break;
1486 case ADEC:
1487 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1488 break;
1489 case AINC:
1490 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1491 break;
1492 case DISP:
1493
1494 nextword = get_num (&opP->disp, 80);
1495
1496 if (opP->reg == PC
1497 && ! isvar (&opP->disp)
1498 && m68k_abspcadd)
1499 {
1500 opP->disp.exp.X_op = O_symbol;
1501 #ifndef BFD_ASSEMBLER
1502 opP->disp.exp.X_add_symbol = &abs_symbol;
1503 #else
1504 opP->disp.exp.X_add_symbol =
1505 section_symbol (absolute_section);
1506 #endif
1507 }
1508
1509 /* Force into index mode. Hope this works */
1510
1511 /* We do the first bit for 32-bit displacements, and the
1512 second bit for 16 bit ones. It is possible that we
1513 should make the default be WORD instead of LONG, but
1514 I think that'd break GCC, so we put up with a little
1515 inefficiency for the sake of working output. */
1516
1517 if (!issword (nextword)
1518 || (isvar (&opP->disp)
1519 && ((opP->disp.size == SIZE_UNSPEC
1520 && flag_short_refs == 0
1521 && cpu_of_arch (current_architecture) >= m68020)
1522 || opP->disp.size == SIZE_LONG)))
1523 {
1524 if (opP->reg == PC)
1525 tmpreg = 0x3B; /* 7.3 */
1526 else
1527 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1528 if (isvar (&opP->disp))
1529 {
1530 if (opP->reg == PC)
1531 {
1532 #if 0
1533 addword (0x0170);
1534 add_fix ('l', &opP->disp, 1, 2);
1535 addword (0), addword (0);
1536 #else
1537 add_frag (adds (&opP->disp),
1538 offs (&opP->disp),
1539 TAB (PCLEA, SZ_UNDEF));
1540 #endif
1541 break;
1542 }
1543 else
1544 {
1545 addword (0x0170);
1546 add_fix ('l', &opP->disp, 0, 0);
1547 }
1548 }
1549 else
1550 addword (0x0170);
1551 addword (nextword >> 16);
1552 }
1553 else
1554 {
1555 if (opP->reg == PC)
1556 tmpreg = 0x3A; /* 7.2 */
1557 else
1558 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1559
1560 if (isvar (&opP->disp))
1561 {
1562 if (opP->reg == PC)
1563 {
1564 add_fix ('w', &opP->disp, 1, 0);
1565 }
1566 else
1567 add_fix ('w', &opP->disp, 0, 0);
1568 }
1569 }
1570 addword (nextword);
1571 break;
1572
1573 case POST:
1574 case PRE:
1575 case BASE:
1576 nextword = 0;
1577 baseo = get_num (&opP->disp, 80);
1578 if (opP->mode == POST || opP->mode == PRE)
1579 outro = get_num (&opP->odisp, 80);
1580 /* Figure out the `addressing mode'.
1581 Also turn on the BASE_DISABLE bit, if needed. */
1582 if (opP->reg == PC || opP->reg == ZPC)
1583 {
1584 tmpreg = 0x3b; /* 7.3 */
1585 if (opP->reg == ZPC)
1586 nextword |= 0x80;
1587 }
1588 else if (opP->reg == 0)
1589 {
1590 nextword |= 0x80;
1591 tmpreg = 0x30; /* 6.garbage */
1592 }
1593 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1594 {
1595 nextword |= 0x80;
1596 tmpreg = 0x30 + opP->reg - ZADDR0;
1597 }
1598 else
1599 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1600
1601 siz1 = opP->disp.size;
1602 if (opP->mode == POST || opP->mode == PRE)
1603 siz2 = opP->odisp.size;
1604 else
1605 siz2 = SIZE_UNSPEC;
1606
1607 /* Index register stuff */
1608 if (opP->index.reg != 0
1609 && opP->index.reg >= DATA
1610 && opP->index.reg <= ADDR7)
1611 {
1612 nextword |= (opP->index.reg - DATA) << 12;
1613
1614 if (opP->index.size == SIZE_UNSPEC
1615 || opP->index.size == SIZE_LONG)
1616 nextword |= 0x800;
1617
1618 if (cpu_of_arch (current_architecture) < m68020)
1619 {
1620 if (opP->index.scale != 1)
1621 {
1622 opP->error =
1623 "scale factor invalid on this architecture; needs 68020 or higher";
1624 }
1625 }
1626
1627 switch (opP->index.scale)
1628 {
1629 case 1:
1630 break;
1631 case 2:
1632 nextword |= 0x200;
1633 break;
1634 case 4:
1635 nextword |= 0x400;
1636 break;
1637 case 8:
1638 nextword |= 0x600;
1639 break;
1640 default:
1641 abort ();
1642 }
1643 /* IF its simple,
1644 GET US OUT OF HERE! */
1645
1646 /* Must be INDEX, with an index register. Address
1647 register cannot be ZERO-PC, and either :b was
1648 forced, or we know it will fit. For a 68000 or
1649 68010, force this mode anyways, because the
1650 larger modes aren't supported. */
1651 if (opP->mode == BASE
1652 && ((opP->reg >= ADDR0
1653 && opP->reg <= ADDR7)
1654 || opP->reg == PC))
1655 {
1656 if (siz1 == SIZE_BYTE
1657 || cpu_of_arch (current_architecture) < m68020
1658 || (siz1 == SIZE_UNSPEC
1659 && ! isvar (&opP->disp)
1660 && issbyte (baseo)))
1661 {
1662 nextword += baseo & 0xff;
1663 addword (nextword);
1664 if (isvar (&opP->disp))
1665 {
1666 /* Do a byte relocation. If it doesn't
1667 fit (possible on m68000) let the
1668 fixup processing complain later. */
1669 if (opP->reg == PC)
1670 add_fix ('B', &opP->disp, 1, 1);
1671 else
1672 add_fix ('B', &opP->disp, 0, 0);
1673 }
1674 else if (siz1 != SIZE_BYTE)
1675 {
1676 if (siz1 != SIZE_UNSPEC)
1677 as_warn ("Forcing byte displacement");
1678 if (! issbyte (baseo))
1679 opP->error = "byte displacement out of range";
1680 }
1681
1682 break;
1683 }
1684 else if (siz1 == SIZE_UNSPEC
1685 && opP->reg == PC
1686 && isvar (&opP->disp)
1687 && subs (&opP->disp) == NULL)
1688 {
1689 nextword += baseo & 0xff;
1690 addword (nextword);
1691 add_frag (adds (&opP->disp), offs (&opP->disp),
1692 TAB (PCINDEX, SZ_UNDEF));
1693
1694 break;
1695 }
1696 }
1697 }
1698 else
1699 {
1700 nextword |= 0x40; /* No index reg */
1701 if (opP->index.reg >= ZDATA0
1702 && opP->index.reg <= ZDATA7)
1703 nextword |= (opP->index.reg - ZDATA0) << 12;
1704 else if (opP->index.reg >= ZADDR0
1705 || opP->index.reg <= ZADDR7)
1706 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1707 }
1708
1709 /* It isn't simple. */
1710
1711 if (cpu_of_arch (current_architecture) < m68020)
1712 opP->error =
1713 "invalid operand mode for this architecture; needs 68020 or higher";
1714
1715 nextword |= 0x100;
1716 /* If the guy specified a width, we assume that it is
1717 wide enough. Maybe it isn't. If so, we lose. */
1718 switch (siz1)
1719 {
1720 case SIZE_UNSPEC:
1721 if (isvar (&opP->disp)
1722 ? m68k_rel32
1723 : ! issword (baseo))
1724 {
1725 siz1 = SIZE_LONG;
1726 nextword |= 0x30;
1727 }
1728 else if (! isvar (&opP->disp) && baseo == 0)
1729 nextword |= 0x10;
1730 else
1731 {
1732 nextword |= 0x20;
1733 siz1 = SIZE_WORD;
1734 }
1735 break;
1736 case SIZE_BYTE:
1737 as_warn (":b not permitted; defaulting to :w");
1738 /* Fall through. */
1739 case SIZE_WORD:
1740 nextword |= 0x20;
1741 break;
1742 case SIZE_LONG:
1743 nextword |= 0x30;
1744 break;
1745 }
1746
1747 /* Figure out innner displacement stuff */
1748 if (opP->mode == POST || opP->mode == PRE)
1749 {
1750 switch (siz2)
1751 {
1752 case SIZE_UNSPEC:
1753 if (isvar (&opP->odisp)
1754 ? m68k_rel32
1755 : ! issword (outro))
1756 {
1757 siz2 = SIZE_LONG;
1758 nextword |= 0x3;
1759 }
1760 else if (! isvar (&opP->disp) && outro == 0)
1761 nextword |= 0x1;
1762 else
1763 {
1764 nextword |= 0x2;
1765 siz2 = SIZE_WORD;
1766 }
1767 break;
1768 case 1:
1769 as_warn (":b not permitted; defaulting to :w");
1770 /* Fall through. */
1771 case 2:
1772 nextword |= 0x2;
1773 break;
1774 case 3:
1775 nextword |= 0x3;
1776 break;
1777 }
1778 if (opP->mode == POST)
1779 nextword |= 0x04;
1780 }
1781 addword (nextword);
1782
1783 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
1784 {
1785 if (opP->reg == PC || opP->reg == ZPC)
1786 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
1787 else
1788 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
1789 }
1790 if (siz1 == SIZE_LONG)
1791 addword (baseo >> 16);
1792 if (siz1 != SIZE_UNSPEC)
1793 addword (baseo);
1794
1795 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
1796 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
1797 if (siz2 == SIZE_LONG)
1798 addword (outro >> 16);
1799 if (siz2 != SIZE_UNSPEC)
1800 addword (outro);
1801
1802 break;
1803
1804 case ABSL:
1805 nextword = get_num (&opP->disp, 80);
1806 switch (opP->disp.size)
1807 {
1808 default:
1809 abort ();
1810 case SIZE_UNSPEC:
1811 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
1812 {
1813 tmpreg = 0x38; /* 7.0 */
1814 addword (nextword);
1815 break;
1816 }
1817 /* Don't generate pc relative code on 68010 and
1818 68000. */
1819 if (isvar (&opP->disp)
1820 && !subs (&opP->disp)
1821 && adds (&opP->disp)
1822 && (S_GET_SEGMENT (adds (&opP->disp)) == text_section)
1823 && now_seg == text_section
1824 && cpu_of_arch (current_architecture) >= m68020
1825 && !flag_long_jumps
1826 && !strchr ("~%&$?", s[0]))
1827 {
1828 tmpreg = 0x3A; /* 7.2 */
1829 add_frag (adds (&opP->disp),
1830 offs (&opP->disp),
1831 TAB (PCREL, SZ_UNDEF));
1832 break;
1833 }
1834 /* Fall through into long */
1835 case SIZE_LONG:
1836 if (isvar (&opP->disp))
1837 add_fix ('l', &opP->disp, 0, 0);
1838
1839 tmpreg = 0x39;/* 7.1 mode */
1840 addword (nextword >> 16);
1841 addword (nextword);
1842 break;
1843
1844 case SIZE_WORD: /* Word */
1845 if (isvar (&opP->disp))
1846 add_fix ('w', &opP->disp, 0, 0);
1847
1848 tmpreg = 0x38;/* 7.0 mode */
1849 addword (nextword);
1850 break;
1851 }
1852 break;
1853 case CONTROL:
1854 case FPREG:
1855 default:
1856 as_bad ("unknown/incorrect operand");
1857 /* abort(); */
1858 }
1859 install_gen_operand (s[1], tmpreg);
1860 break;
1861
1862 case '#':
1863 case '^':
1864 switch (s[1])
1865 { /* JF: I hate floating point! */
1866 case 'j':
1867 tmpreg = 70;
1868 break;
1869 case '8':
1870 tmpreg = 20;
1871 break;
1872 case 'C':
1873 tmpreg = 50;
1874 break;
1875 case '3':
1876 default:
1877 tmpreg = 80;
1878 break;
1879 }
1880 tmpreg = get_num (&opP->disp, tmpreg);
1881 if (isvar (&opP->disp))
1882 add_fix (s[1], &opP->disp, 0, 0);
1883 switch (s[1])
1884 {
1885 case 'b': /* Danger: These do no check for
1886 certain types of overflow.
1887 user beware! */
1888 if (!isbyte (tmpreg))
1889 opP->error = "out of range";
1890 insop (tmpreg, opcode);
1891 if (isvar (&opP->disp))
1892 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1893 break;
1894 case 'w':
1895 if (!isword (tmpreg))
1896 opP->error = "out of range";
1897 insop (tmpreg, opcode);
1898 if (isvar (&opP->disp))
1899 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1900 break;
1901 case 'l':
1902 /* Because of the way insop works, we put these two out
1903 backwards. */
1904 insop (tmpreg, opcode);
1905 insop (tmpreg >> 16, opcode);
1906 if (isvar (&opP->disp))
1907 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
1908 break;
1909 case '3':
1910 tmpreg &= 0xFF;
1911 case '8':
1912 case 'C':
1913 install_operand (s[1], tmpreg);
1914 break;
1915 default:
1916 abort ();
1917 }
1918 break;
1919
1920 case '+':
1921 case '-':
1922 case 'A':
1923 case 'a':
1924 install_operand (s[1], opP->reg - ADDR);
1925 break;
1926
1927 case 'B':
1928 tmpreg = get_num (&opP->disp, 80);
1929 switch (s[1])
1930 {
1931 case 'B':
1932 /* The pc_fix argument winds up in fx_pcrel_adjust,
1933 which is a char, and may therefore be unsigned. We
1934 want to pass -1, but we pass 64 instead, and convert
1935 back in md_pcrel_from. */
1936 add_fix ('B', &opP->disp, 1, 64);
1937 break;
1938 case 'W':
1939 add_fix ('w', &opP->disp, 1, 0);
1940 addword (0);
1941 break;
1942 case 'L':
1943 long_branch:
1944 if (cpu_of_arch (current_architecture) < m68020)
1945 as_warn ("Can't use long branches on 68000/68010");
1946 the_ins.opcode[the_ins.numo - 1] |= 0xff;
1947 add_fix ('l', &opP->disp, 1, 0);
1948 addword (0);
1949 addword (0);
1950 break;
1951 case 'g':
1952 if (subs (&opP->disp)) /* We can't relax it */
1953 goto long_branch;
1954
1955 /* This could either be a symbol, or an absolute
1956 address. No matter, the frag hacking will finger it
1957 out. Not quite: it can't switch from BRANCH to
1958 BCC68000 for the case where opnd is absolute (it
1959 needs to use the 68000 hack since no conditional abs
1960 jumps). */
1961 if (((cpu_of_arch (current_architecture) < m68020)
1962 || (0 == adds (&opP->disp)))
1963 && (the_ins.opcode[0] >= 0x6200)
1964 && (the_ins.opcode[0] <= 0x6f00))
1965 add_frag (adds (&opP->disp), offs (&opP->disp),
1966 TAB (BCC68000, SZ_UNDEF));
1967 else
1968 add_frag (adds (&opP->disp), offs (&opP->disp),
1969 TAB (ABRANCH, SZ_UNDEF));
1970 break;
1971 case 'w':
1972 if (isvar (&opP->disp))
1973 {
1974 #if 1
1975 /* check for DBcc instruction */
1976 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
1977 {
1978 /* size varies if patch */
1979 /* needed for long form */
1980 add_frag (adds (&opP->disp), offs (&opP->disp),
1981 TAB (DBCC, SZ_UNDEF));
1982 break;
1983 }
1984 #endif
1985 add_fix ('w', &opP->disp, 1, 0);
1986 }
1987 addword (0);
1988 break;
1989 case 'C': /* Fixed size LONG coproc branches */
1990 add_fix ('l', &opP->disp, 1, 0);
1991 addword (0);
1992 addword (0);
1993 break;
1994 case 'c': /* Var size Coprocesssor branches */
1995 if (subs (&opP->disp))
1996 {
1997 add_fix ('l', &opP->disp, 1, 0);
1998 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
1999 }
2000 else if (adds (&opP->disp))
2001 add_frag (adds (&opP->disp), offs (&opP->disp),
2002 TAB (FBRANCH, SZ_UNDEF));
2003 else
2004 {
2005 /* add_frag((symbolS *) 0, offs(&opP->disp),
2006 TAB(FBRANCH,SHORT)); */
2007 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2008 add_fix ('l', &opP->disp, 1, 0);
2009 addword (0);
2010 addword (0);
2011 }
2012 break;
2013 default:
2014 abort ();
2015 }
2016 break;
2017
2018 case 'C': /* Ignore it */
2019 break;
2020
2021 case 'd': /* JF this is a kludge */
2022 install_operand ('s', opP->reg - ADDR);
2023 tmpreg = get_num (&opP->disp, 80);
2024 if (!issword (tmpreg))
2025 {
2026 as_warn ("Expression out of range, using 0");
2027 tmpreg = 0;
2028 }
2029 addword (tmpreg);
2030 break;
2031
2032 case 'D':
2033 install_operand (s[1], opP->reg - DATA);
2034 break;
2035
2036 case 'F':
2037 install_operand (s[1], opP->reg - FP0);
2038 break;
2039
2040 case 'I':
2041 tmpreg = opP->reg - COP0;
2042 install_operand (s[1], tmpreg);
2043 break;
2044
2045 case 'J': /* JF foo */
2046 switch (opP->reg)
2047 {
2048 case SFC:
2049 tmpreg = 0x000;
2050 break;
2051 case DFC:
2052 tmpreg = 0x001;
2053 break;
2054 case CACR:
2055 tmpreg = 0x002;
2056 break;
2057 case TC:
2058 tmpreg = 0x003;
2059 break;
2060 case ITT0:
2061 tmpreg = 0x004;
2062 break;
2063 case ITT1:
2064 tmpreg = 0x005;
2065 break;
2066 case DTT0:
2067 tmpreg = 0x006;
2068 break;
2069 case DTT1:
2070 tmpreg = 0x007;
2071 break;
2072 case BUSCR:
2073 tmpreg = 0x008;
2074 break;
2075
2076 case USP:
2077 tmpreg = 0x800;
2078 break;
2079 case VBR:
2080 tmpreg = 0x801;
2081 break;
2082 case CAAR:
2083 tmpreg = 0x802;
2084 break;
2085 case MSP:
2086 tmpreg = 0x803;
2087 break;
2088 case ISP:
2089 tmpreg = 0x804;
2090 break;
2091 case MMUSR:
2092 tmpreg = 0x805;
2093 break;
2094 case URP:
2095 tmpreg = 0x806;
2096 break;
2097 case SRP:
2098 tmpreg = 0x807;
2099 break;
2100 case PCR:
2101 tmpreg = 0x808;
2102 break;
2103 default:
2104 abort ();
2105 }
2106 install_operand (s[1], tmpreg);
2107 break;
2108
2109 case 'k':
2110 tmpreg = get_num (&opP->disp, 55);
2111 install_operand (s[1], tmpreg & 0x7f);
2112 break;
2113
2114 case 'l':
2115 tmpreg = opP->mask;
2116 if (s[1] == 'w')
2117 {
2118 if (tmpreg & 0x7FF0000)
2119 as_bad ("Floating point register in register list");
2120 insop (reverse_16_bits (tmpreg), opcode);
2121 }
2122 else
2123 {
2124 if (tmpreg & 0x700FFFF)
2125 as_bad ("Wrong register in floating-point reglist");
2126 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2127 }
2128 break;
2129
2130 case 'L':
2131 tmpreg = opP->mask;
2132 if (s[1] == 'w')
2133 {
2134 if (tmpreg & 0x7FF0000)
2135 as_bad ("Floating point register in register list");
2136 insop (tmpreg, opcode);
2137 }
2138 else if (s[1] == '8')
2139 {
2140 if (tmpreg & 0x0FFFFFF)
2141 as_bad ("incorrect register in reglist");
2142 install_operand (s[1], tmpreg >> 24);
2143 }
2144 else
2145 {
2146 if (tmpreg & 0x700FFFF)
2147 as_bad ("wrong register in floating-point reglist");
2148 else
2149 install_operand (s[1], tmpreg >> 16);
2150 }
2151 break;
2152
2153 case 'M':
2154 install_operand (s[1], get_num (&opP->disp, 60));
2155 break;
2156
2157 case 'O':
2158 tmpreg = ((opP->mode == DREG)
2159 ? 0x20 + opP->reg - DATA
2160 : (get_num (&opP->disp, 40) & 0x1F));
2161 install_operand (s[1], tmpreg);
2162 break;
2163
2164 case 'Q':
2165 tmpreg = get_num (&opP->disp, 10);
2166 if (tmpreg == 8)
2167 tmpreg = 0;
2168 install_operand (s[1], tmpreg);
2169 break;
2170
2171 case 'R':
2172 /* This depends on the fact that ADDR registers are eight
2173 more than their corresponding DATA regs, so the result
2174 will have the ADDR_REG bit set */
2175 install_operand (s[1], opP->reg - DATA);
2176 break;
2177
2178 case 'r':
2179 if (opP->mode == AINDR)
2180 install_operand (s[1], opP->reg - DATA);
2181 else
2182 install_operand (s[1], opP->index.reg - DATA);
2183 break;
2184
2185 case 's':
2186 if (opP->reg == FPI)
2187 tmpreg = 0x1;
2188 else if (opP->reg == FPS)
2189 tmpreg = 0x2;
2190 else if (opP->reg == FPC)
2191 tmpreg = 0x4;
2192 else
2193 abort ();
2194 install_operand (s[1], tmpreg);
2195 break;
2196
2197 case 'S': /* Ignore it */
2198 break;
2199
2200 case 'T':
2201 install_operand (s[1], get_num (&opP->disp, 30));
2202 break;
2203
2204 case 'U': /* Ignore it */
2205 break;
2206
2207 case 'c':
2208 switch (opP->reg)
2209 {
2210 case NC:
2211 tmpreg = 0;
2212 break;
2213 case DC:
2214 tmpreg = 1;
2215 break;
2216 case IC:
2217 tmpreg = 2;
2218 break;
2219 case BC:
2220 tmpreg = 3;
2221 break;
2222 default:
2223 as_fatal ("failed sanity check");
2224 } /* switch on cache token */
2225 install_operand (s[1], tmpreg);
2226 break;
2227 #ifndef NO_68851
2228 /* JF: These are out of order, I fear. */
2229 case 'f':
2230 switch (opP->reg)
2231 {
2232 case SFC:
2233 tmpreg = 0;
2234 break;
2235 case DFC:
2236 tmpreg = 1;
2237 break;
2238 default:
2239 abort ();
2240 }
2241 install_operand (s[1], tmpreg);
2242 break;
2243
2244 case 'P':
2245 switch (opP->reg)
2246 {
2247 case TC:
2248 tmpreg = 0;
2249 break;
2250 case CAL:
2251 tmpreg = 4;
2252 break;
2253 case VAL:
2254 tmpreg = 5;
2255 break;
2256 case SCC:
2257 tmpreg = 6;
2258 break;
2259 case AC:
2260 tmpreg = 7;
2261 break;
2262 default:
2263 abort ();
2264 }
2265 install_operand (s[1], tmpreg);
2266 break;
2267
2268 case 'V':
2269 if (opP->reg == VAL)
2270 break;
2271 abort ();
2272
2273 case 'W':
2274 switch (opP->reg)
2275 {
2276 case DRP:
2277 tmpreg = 1;
2278 break;
2279 case SRP:
2280 tmpreg = 2;
2281 break;
2282 case CRP:
2283 tmpreg = 3;
2284 break;
2285 default:
2286 abort ();
2287 }
2288 install_operand (s[1], tmpreg);
2289 break;
2290
2291 case 'X':
2292 switch (opP->reg)
2293 {
2294 case BAD:
2295 case BAD + 1:
2296 case BAD + 2:
2297 case BAD + 3:
2298 case BAD + 4:
2299 case BAD + 5:
2300 case BAD + 6:
2301 case BAD + 7:
2302 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2303 break;
2304
2305 case BAC:
2306 case BAC + 1:
2307 case BAC + 2:
2308 case BAC + 3:
2309 case BAC + 4:
2310 case BAC + 5:
2311 case BAC + 6:
2312 case BAC + 7:
2313 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2314 break;
2315
2316 default:
2317 abort ();
2318 }
2319 install_operand (s[1], tmpreg);
2320 break;
2321 case 'Y':
2322 know (opP->reg == PSR);
2323 break;
2324 case 'Z':
2325 know (opP->reg == PCSR);
2326 break;
2327 #endif /* m68851 */
2328 case '3':
2329 switch (opP->reg)
2330 {
2331 case TT0:
2332 tmpreg = 2;
2333 break;
2334 case TT1:
2335 tmpreg = 3;
2336 break;
2337 default:
2338 abort ();
2339 }
2340 install_operand (s[1], tmpreg);
2341 break;
2342 case 't':
2343 tmpreg = get_num (&opP->disp, 20);
2344 install_operand (s[1], tmpreg);
2345 break;
2346 case '_': /* used only for move16 absolute 32-bit address */
2347 tmpreg = get_num (&opP->disp, 80);
2348 addword (tmpreg >> 16);
2349 addword (tmpreg & 0xFFFF);
2350 break;
2351 default:
2352 abort ();
2353 }
2354 }
2355
2356 /* By the time whe get here (FINALLY) the_ins contains the complete
2357 instruction, ready to be emitted. . . */
2358 }
2359
2360 static int
2361 reverse_16_bits (in)
2362 int in;
2363 {
2364 int out = 0;
2365 int n;
2366
2367 static int mask[16] =
2368 {
2369 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2370 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2371 };
2372 for (n = 0; n < 16; n++)
2373 {
2374 if (in & mask[n])
2375 out |= mask[15 - n];
2376 }
2377 return out;
2378 } /* reverse_16_bits() */
2379
2380 static int
2381 reverse_8_bits (in)
2382 int in;
2383 {
2384 int out = 0;
2385 int n;
2386
2387 static int mask[8] =
2388 {
2389 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2390 };
2391
2392 for (n = 0; n < 8; n++)
2393 {
2394 if (in & mask[n])
2395 out |= mask[7 - n];
2396 }
2397 return out;
2398 } /* reverse_8_bits() */
2399
2400 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2401 (that value is chosen in the frag_var call in md_assemble). TYPE
2402 is the subtype of the frag to be generated; its primary type is
2403 rs_machine_dependent.
2404
2405 The TYPE parameter is also used by md_convert_frag_1 and
2406 md_estimate_size_before_relax. The appropriate type of fixup will
2407 be emitted by md_convert_frag_1.
2408
2409 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2410 static void
2411 install_operand (mode, val)
2412 int mode;
2413 int val;
2414 {
2415 switch (mode)
2416 {
2417 case 's':
2418 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2419 break;
2420 case 'd':
2421 the_ins.opcode[0] |= val << 9;
2422 break;
2423 case '1':
2424 the_ins.opcode[1] |= val << 12;
2425 break;
2426 case '2':
2427 the_ins.opcode[1] |= val << 6;
2428 break;
2429 case '3':
2430 the_ins.opcode[1] |= val;
2431 break;
2432 case '4':
2433 the_ins.opcode[2] |= val << 12;
2434 break;
2435 case '5':
2436 the_ins.opcode[2] |= val << 6;
2437 break;
2438 case '6':
2439 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2440 three words long! */
2441 the_ins.numo++;
2442 the_ins.opcode[2] |= val;
2443 break;
2444 case '7':
2445 the_ins.opcode[1] |= val << 7;
2446 break;
2447 case '8':
2448 the_ins.opcode[1] |= val << 10;
2449 break;
2450 #ifndef NO_68851
2451 case '9':
2452 the_ins.opcode[1] |= val << 5;
2453 break;
2454 #endif
2455
2456 case 't':
2457 the_ins.opcode[1] |= (val << 10) | (val << 7);
2458 break;
2459 case 'D':
2460 the_ins.opcode[1] |= (val << 12) | val;
2461 break;
2462 case 'g':
2463 the_ins.opcode[0] |= val = 0xff;
2464 break;
2465 case 'i':
2466 the_ins.opcode[0] |= val << 9;
2467 break;
2468 case 'C':
2469 the_ins.opcode[1] |= val;
2470 break;
2471 case 'j':
2472 the_ins.opcode[1] |= val;
2473 the_ins.numo++; /* What a hack */
2474 break;
2475 case 'k':
2476 the_ins.opcode[1] |= val << 4;
2477 break;
2478 case 'b':
2479 case 'w':
2480 case 'l':
2481 break;
2482 case 'e':
2483 the_ins.opcode[0] |= (val << 6);
2484 break;
2485 case 'L':
2486 the_ins.opcode[1] = (val >> 16);
2487 the_ins.opcode[2] = val & 0xffff;
2488 break;
2489 case 'c':
2490 default:
2491 as_fatal ("failed sanity check.");
2492 }
2493 } /* install_operand() */
2494
2495 static void
2496 install_gen_operand (mode, val)
2497 int mode;
2498 int val;
2499 {
2500 switch (mode)
2501 {
2502 case 's':
2503 the_ins.opcode[0] |= val;
2504 break;
2505 case 'd':
2506 /* This is a kludge!!! */
2507 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2508 break;
2509 case 'b':
2510 case 'w':
2511 case 'l':
2512 case 'f':
2513 case 'F':
2514 case 'x':
2515 case 'p':
2516 the_ins.opcode[0] |= val;
2517 break;
2518 /* more stuff goes here */
2519 default:
2520 as_fatal ("failed sanity check.");
2521 }
2522 } /* install_gen_operand() */
2523
2524 /*
2525 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2526 * then deal with the bitfield hack.
2527 */
2528
2529 static char *
2530 crack_operand (str, opP)
2531 register char *str;
2532 register struct m68k_op *opP;
2533 {
2534 register int parens;
2535 register int c;
2536 register char *beg_str;
2537 int inquote = 0;
2538
2539 if (!str)
2540 {
2541 return str;
2542 }
2543 beg_str = str;
2544 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2545 {
2546 if (! inquote)
2547 {
2548 if (*str == '(')
2549 parens++;
2550 else if (*str == ')')
2551 {
2552 if (!parens)
2553 { /* ERROR */
2554 opP->error = "Extra )";
2555 return str;
2556 }
2557 --parens;
2558 }
2559 }
2560 if (flag_mri && *str == '\'')
2561 inquote = ! inquote;
2562 }
2563 if (!*str && parens)
2564 { /* ERROR */
2565 opP->error = "Missing )";
2566 return str;
2567 }
2568 c = *str;
2569 *str = '\0';
2570 if (m68k_ip_op (beg_str, opP) != 0)
2571 {
2572 *str = c;
2573 return str;
2574 }
2575 *str = c;
2576 if (c == '}')
2577 c = *++str; /* JF bitfield hack */
2578 if (c)
2579 {
2580 c = *++str;
2581 if (!c)
2582 as_bad ("Missing operand");
2583 }
2584 return str;
2585 }
2586
2587 /* This is the guts of the machine-dependent assembler. STR points to a
2588 machine dependent instruction. This function is supposed to emit
2589 the frags/bytes it assembles to.
2590 */
2591
2592 void
2593 insert_reg (regname, regnum)
2594 char *regname;
2595 int regnum;
2596 {
2597 char buf[100];
2598 int i;
2599
2600 #ifdef REGISTER_PREFIX
2601 if (!flag_reg_prefix_optional)
2602 {
2603 buf[0] = REGISTER_PREFIX;
2604 strcpy (buf + 1, regname);
2605 regname = buf;
2606 }
2607 #endif
2608
2609 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2610 &zero_address_frag));
2611
2612 for (i = 0; regname[i]; i++)
2613 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2614 buf[i] = '\0';
2615
2616 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2617 &zero_address_frag));
2618 }
2619
2620 struct init_entry
2621 {
2622 const char *name;
2623 int number;
2624 };
2625
2626 static const struct init_entry init_table[] =
2627 {
2628 { "d0", DATA0 },
2629 { "d1", DATA1 },
2630 { "d2", DATA2 },
2631 { "d3", DATA3 },
2632 { "d4", DATA4 },
2633 { "d5", DATA5 },
2634 { "d6", DATA6 },
2635 { "d7", DATA7 },
2636 { "a0", ADDR0 },
2637 { "a1", ADDR1 },
2638 { "a2", ADDR2 },
2639 { "a3", ADDR3 },
2640 { "a4", ADDR4 },
2641 { "a5", ADDR5 },
2642 { "a6", ADDR6 },
2643 { "fp", ADDR6 },
2644 { "a7", ADDR7 },
2645 { "sp", ADDR7 },
2646 { "ssp", ADDR7 },
2647 { "fp0", FP0 },
2648 { "fp1", FP1 },
2649 { "fp2", FP2 },
2650 { "fp3", FP3 },
2651 { "fp4", FP4 },
2652 { "fp5", FP5 },
2653 { "fp6", FP6 },
2654 { "fp7", FP7 },
2655 { "fpi", FPI },
2656 { "fpiar", FPI },
2657 { "fpc", FPI },
2658 { "fps", FPS },
2659 { "fpsr", FPS },
2660 { "fpc", FPC },
2661 { "fpcr", FPC },
2662 { "control", FPC },
2663 { "status", FPS },
2664 { "iaddr", FPI },
2665
2666 { "cop0", COP0 },
2667 { "cop1", COP1 },
2668 { "cop2", COP2 },
2669 { "cop3", COP3 },
2670 { "cop4", COP4 },
2671 { "cop5", COP5 },
2672 { "cop6", COP6 },
2673 { "cop7", COP7 },
2674 { "pc", PC },
2675 { "zpc", ZPC },
2676 { "sr", SR },
2677
2678 { "ccr", CCR },
2679 { "cc", CCR },
2680
2681 { "usp", USP },
2682 { "isp", ISP },
2683 { "sfc", SFC },
2684 { "sfcr", SFC },
2685 { "dfc", DFC },
2686 { "dfcr", DFC },
2687 { "cacr", CACR },
2688 { "caar", CAAR },
2689
2690 { "vbr", VBR },
2691
2692 { "msp", MSP },
2693 { "itt0", ITT0 },
2694 { "itt1", ITT1 },
2695 { "dtt0", DTT0 },
2696 { "dtt1", DTT1 },
2697 { "mmusr", MMUSR },
2698 { "tc", TC },
2699 { "srp", SRP },
2700 { "urp", URP },
2701 { "buscr", BUSCR },
2702 { "pcr", PCR },
2703
2704 { "ac", AC },
2705 { "bc", BC },
2706 { "cal", CAL },
2707 { "crp", CRP },
2708 { "drp", DRP },
2709 { "pcsr", PCSR },
2710 { "psr", PSR },
2711 { "scc", SCC },
2712 { "val", VAL },
2713 { "bad0", BAD0 },
2714 { "bad1", BAD1 },
2715 { "bad2", BAD2 },
2716 { "bad3", BAD3 },
2717 { "bad4", BAD4 },
2718 { "bad5", BAD5 },
2719 { "bad6", BAD6 },
2720 { "bad7", BAD7 },
2721 { "bac0", BAC0 },
2722 { "bac1", BAC1 },
2723 { "bac2", BAC2 },
2724 { "bac3", BAC3 },
2725 { "bac4", BAC4 },
2726 { "bac5", BAC5 },
2727 { "bac6", BAC6 },
2728 { "bac7", BAC7 },
2729
2730 { "ic", IC },
2731 { "dc", DC },
2732 { "nc", NC },
2733
2734 { "tt0", TT0 },
2735 { "tt1", TT1 },
2736 /* 68ec030 versions of same */
2737 { "ac0", TT0 },
2738 { "ac1", TT1 },
2739 /* 68ec030 access control unit, identical to 030 MMU status reg */
2740 { "acusr", PSR },
2741
2742 /* Suppressed data and address registers. */
2743 { "zd0", ZDATA0 },
2744 { "zd1", ZDATA1 },
2745 { "zd2", ZDATA2 },
2746 { "zd3", ZDATA3 },
2747 { "zd4", ZDATA4 },
2748 { "zd5", ZDATA5 },
2749 { "zd6", ZDATA6 },
2750 { "zd7", ZDATA7 },
2751 { "za0", ZADDR0 },
2752 { "za1", ZADDR1 },
2753 { "za2", ZADDR2 },
2754 { "za3", ZADDR3 },
2755 { "za4", ZADDR4 },
2756 { "za5", ZADDR5 },
2757 { "za6", ZADDR6 },
2758 { "za7", ZADDR7 },
2759
2760 { 0, 0 }
2761 };
2762
2763 void
2764 init_regtable ()
2765 {
2766 int i;
2767 for (i = 0; init_table[i].name; i++)
2768 insert_reg (init_table[i].name, init_table[i].number);
2769 }
2770
2771 static int no_68851, no_68881;
2772
2773 #ifdef OBJ_AOUT
2774 /* a.out machine type. Default to 68020. */
2775 int m68k_aout_machtype = 2;
2776 #endif
2777
2778 void
2779 md_assemble (str)
2780 char *str;
2781 {
2782 const char *er;
2783 short *fromP;
2784 char *toP = NULL;
2785 int m, n = 0;
2786 char *to_beg_P;
2787 int shorts_this_frag;
2788 fixS *fixP;
2789
2790 /* In MRI mode, the instruction and operands are separated by a
2791 space. Anything following the operands is a comment. The label
2792 has already been removed. */
2793 if (flag_mri)
2794 {
2795 char *s;
2796 int fields = 0;
2797 int infield = 0;
2798 int inquote = 0;
2799
2800 for (s = str; *s != '\0'; s++)
2801 {
2802 if ((*s == ' ' || *s == '\t') && ! inquote)
2803 {
2804 if (infield)
2805 {
2806 ++fields;
2807 if (fields >= 2)
2808 {
2809 *s = '\0';
2810 break;
2811 }
2812 infield = 0;
2813 }
2814 }
2815 else
2816 {
2817 if (! infield)
2818 infield = 1;
2819 if (*s == '\'')
2820 inquote = ! inquote;
2821 }
2822 }
2823 }
2824
2825 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
2826 m68k_ip (str);
2827 er = the_ins.error;
2828 if (!er)
2829 {
2830 for (n = 0; n < the_ins.numargs; n++)
2831 if (the_ins.operands[n].error)
2832 {
2833 er = the_ins.operands[n].error;
2834 break;
2835 }
2836 }
2837 if (er)
2838 {
2839 as_bad ("%s -- statement `%s' ignored", er, str);
2840 return;
2841 }
2842
2843 if (the_ins.nfrag == 0)
2844 {
2845 /* No frag hacking involved; just put it out */
2846 toP = frag_more (2 * the_ins.numo);
2847 fromP = &the_ins.opcode[0];
2848 for (m = the_ins.numo; m; --m)
2849 {
2850 md_number_to_chars (toP, (long) (*fromP), 2);
2851 toP += 2;
2852 fromP++;
2853 }
2854 /* put out symbol-dependent info */
2855 for (m = 0; m < the_ins.nrel; m++)
2856 {
2857 switch (the_ins.reloc[m].wid)
2858 {
2859 case 'B':
2860 n = 1;
2861 break;
2862 case 'b':
2863 n = 1;
2864 break;
2865 case '3':
2866 n = 2;
2867 break;
2868 case 'w':
2869 n = 2;
2870 break;
2871 case 'l':
2872 n = 4;
2873 break;
2874 default:
2875 as_fatal ("Don't know how to figure width of %c in md_assemble()",
2876 the_ins.reloc[m].wid);
2877 }
2878
2879 fixP = fix_new_exp (frag_now,
2880 ((toP - frag_now->fr_literal)
2881 - the_ins.numo * 2 + the_ins.reloc[m].n),
2882 n,
2883 &the_ins.reloc[m].exp,
2884 the_ins.reloc[m].pcrel,
2885 NO_RELOC);
2886 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2887 }
2888 return;
2889 }
2890
2891 /* There's some frag hacking */
2892 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
2893 {
2894 int wid;
2895
2896 if (n == 0)
2897 wid = 2 * the_ins.fragb[n].fragoff;
2898 else
2899 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2900 toP = frag_more (wid);
2901 to_beg_P = toP;
2902 shorts_this_frag = 0;
2903 for (m = wid / 2; m; --m)
2904 {
2905 md_number_to_chars (toP, (long) (*fromP), 2);
2906 toP += 2;
2907 fromP++;
2908 shorts_this_frag++;
2909 }
2910 for (m = 0; m < the_ins.nrel; m++)
2911 {
2912 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
2913 {
2914 the_ins.reloc[m].n -= 2 * shorts_this_frag;
2915 break;
2916 }
2917 wid = the_ins.reloc[m].wid;
2918 if (wid == 0)
2919 continue;
2920 the_ins.reloc[m].wid = 0;
2921 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2922
2923 fixP = fix_new_exp (frag_now,
2924 ((toP - frag_now->fr_literal)
2925 - the_ins.numo * 2 + the_ins.reloc[m].n),
2926 wid,
2927 &the_ins.reloc[m].exp,
2928 the_ins.reloc[m].pcrel,
2929 NO_RELOC);
2930 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2931 }
2932 (void) frag_var (rs_machine_dependent, 10, 0,
2933 (relax_substateT) (the_ins.fragb[n].fragty),
2934 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
2935 }
2936 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
2937 shorts_this_frag = 0;
2938 if (n)
2939 {
2940 toP = frag_more (n * sizeof (short));
2941 while (n--)
2942 {
2943 md_number_to_chars (toP, (long) (*fromP), 2);
2944 toP += 2;
2945 fromP++;
2946 shorts_this_frag++;
2947 }
2948 }
2949 for (m = 0; m < the_ins.nrel; m++)
2950 {
2951 int wid;
2952
2953 wid = the_ins.reloc[m].wid;
2954 if (wid == 0)
2955 continue;
2956 the_ins.reloc[m].wid = 0;
2957 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
2958
2959 fixP = fix_new_exp (frag_now,
2960 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
2961 - shorts_this_frag * 2),
2962 wid,
2963 &the_ins.reloc[m].exp,
2964 the_ins.reloc[m].pcrel,
2965 NO_RELOC);
2966 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
2967 }
2968 }
2969
2970 void
2971 md_begin ()
2972 {
2973 /*
2974 * md_begin -- set up hash tables with 68000 instructions.
2975 * similar to what the vax assembler does. ---phr
2976 */
2977 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
2978 a copy of it at runtime, adding in the information we want but isn't
2979 there. I think it'd be better to have an awk script hack the table
2980 at compile time. Or even just xstr the table and use it as-is. But
2981 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
2982 names. */
2983
2984 register const struct m68k_opcode *ins;
2985 register struct m68k_incant *hack, *slak;
2986 register const char *retval = 0; /* empty string, or error msg text */
2987 register unsigned int i;
2988 register char c;
2989
2990 if (flag_mri)
2991 {
2992 flag_reg_prefix_optional = 1;
2993 m68k_abspcadd = 1;
2994 m68k_rel32 = 0;
2995 }
2996
2997 op_hash = hash_new ();
2998
2999 obstack_begin (&robyn, 4000);
3000 for (i = 0; i < m68k_numopcodes; i++)
3001 {
3002 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3003 do
3004 {
3005 ins = &m68k_opcodes[i];
3006 /* We *could* ignore insns that don't match our arch here
3007 but just leaving them out of the hash. */
3008 slak->m_operands = ins->args;
3009 slak->m_opnum = strlen (slak->m_operands) / 2;
3010 slak->m_arch = ins->arch;
3011 slak->m_opcode = ins->opcode;
3012 /* This is kludgey */
3013 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3014 if (i + 1 != m68k_numopcodes
3015 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3016 {
3017 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3018 i++;
3019 }
3020 else
3021 slak->m_next = 0;
3022 slak = slak->m_next;
3023 }
3024 while (slak);
3025
3026 retval = hash_insert (op_hash, ins->name, (char *) hack);
3027 if (retval)
3028 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3029 }
3030
3031 for (i = 0; i < m68k_numaliases; i++)
3032 {
3033 const char *name = m68k_opcode_aliases[i].primary;
3034 const char *alias = m68k_opcode_aliases[i].alias;
3035 PTR val = hash_find (op_hash, name);
3036 if (!val)
3037 as_fatal ("Internal Error: Can't find %s in hash table", name);
3038 retval = hash_insert (op_hash, alias, val);
3039 if (retval)
3040 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3041 }
3042
3043 /* In MRI mode, all unsized branches are variable sized. Normally,
3044 they are word sized. */
3045 if (flag_mri)
3046 {
3047 static struct m68k_opcode_alias mri_aliases[] =
3048 {
3049 { "bhi", "jhi", },
3050 { "bls", "jls", },
3051 { "bcc", "jcc", },
3052 { "bcs", "jcs", },
3053 { "bne", "jne", },
3054 { "beq", "jeq", },
3055 { "bvc", "jvc", },
3056 { "bvs", "jvs", },
3057 { "bpl", "jpl", },
3058 { "bmi", "jmi", },
3059 { "bge", "jge", },
3060 { "blt", "jlt", },
3061 { "bgt", "jgt", },
3062 { "ble", "jle", },
3063 { "bra", "jra", },
3064 { "bsr", "jbsr", },
3065 };
3066
3067 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3068 {
3069 const char *name = mri_aliases[i].primary;
3070 const char *alias = mri_aliases[i].alias;
3071 PTR val = hash_find (op_hash, name);
3072 if (!val)
3073 as_fatal ("Internal Error: Can't find %s in hash table", name);
3074 retval = hash_jam (op_hash, alias, val);
3075 if (retval)
3076 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3077 }
3078 }
3079
3080 for (i = 0; i < sizeof (mklower_table); i++)
3081 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3082
3083 for (i = 0; i < sizeof (notend_table); i++)
3084 {
3085 notend_table[i] = 0;
3086 alt_notend_table[i] = 0;
3087 }
3088 notend_table[','] = 1;
3089 notend_table['{'] = 1;
3090 notend_table['}'] = 1;
3091 alt_notend_table['a'] = 1;
3092 alt_notend_table['A'] = 1;
3093 alt_notend_table['d'] = 1;
3094 alt_notend_table['D'] = 1;
3095 alt_notend_table['#'] = 1;
3096 alt_notend_table['&'] = 1;
3097 alt_notend_table['f'] = 1;
3098 alt_notend_table['F'] = 1;
3099 #ifdef REGISTER_PREFIX
3100 alt_notend_table[REGISTER_PREFIX] = 1;
3101 #endif
3102
3103 /* We need to put '(' in alt_notend_table to handle
3104 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3105 */
3106 alt_notend_table['('] = 1;
3107
3108 /* We need to put '@' in alt_notend_table to handle
3109 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3110 */
3111 alt_notend_table['@'] = 1;
3112
3113 #ifndef MIT_SYNTAX_ONLY
3114 /* Insert pseudo ops, these have to go into the opcode table since
3115 gas expects pseudo ops to start with a dot */
3116 {
3117 int n = 0;
3118 while (mote_pseudo_table[n].poc_name)
3119 {
3120 hack = (struct m68k_incant *)
3121 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3122 hash_insert (op_hash,
3123 mote_pseudo_table[n].poc_name, (char *) hack);
3124 hack->m_operands = 0;
3125 hack->m_opnum = n;
3126 n++;
3127 }
3128 }
3129 #endif
3130
3131 init_regtable ();
3132 }
3133
3134 void
3135 m68k_init_after_args ()
3136 {
3137 if (cpu_of_arch (current_architecture) == 0)
3138 {
3139 int i;
3140 const char *default_cpu = TARGET_CPU;
3141
3142 if (*default_cpu == 'm')
3143 default_cpu++;
3144 for (i = 0; i < n_archs; i++)
3145 if (strcasecmp (default_cpu, archs[i].name) == 0)
3146 break;
3147 if (i == n_archs)
3148 {
3149 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3150 current_architecture |= m68020;
3151 }
3152 else
3153 current_architecture |= archs[i].arch;
3154 }
3155 /* Permit m68881 specification with all cpus; those that can't work
3156 with a coprocessor could be doing emulation. */
3157 if (current_architecture & m68851)
3158 {
3159 if (current_architecture & m68040)
3160 {
3161 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3162 }
3163 }
3164 /* What other incompatibilities could we check for? */
3165
3166 /* Toss in some default assumptions about coprocessors. */
3167 if (!no_68881
3168 && (cpu_of_arch (current_architecture)
3169 /* Can CPU32 have a 68881 coprocessor?? */
3170 & (m68020 | m68030 | cpu32)))
3171 {
3172 current_architecture |= m68881;
3173 }
3174 if (!no_68851
3175 && (cpu_of_arch (current_architecture) & m68020up) != 0
3176 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3177 {
3178 current_architecture |= m68851;
3179 }
3180 if (no_68881 && (current_architecture & m68881))
3181 as_bad ("options for 68881 and no-68881 both given");
3182 if (no_68851 && (current_architecture & m68851))
3183 as_bad ("options for 68851 and no-68851 both given");
3184
3185 #ifdef OBJ_AOUT
3186 /* Work out the magic number. This isn't very general. */
3187 if (current_architecture & m68000)
3188 m68k_aout_machtype = 0;
3189 else if (current_architecture & m68010)
3190 m68k_aout_machtype = 1;
3191 else if (current_architecture & m68020)
3192 m68k_aout_machtype = 2;
3193 else
3194 m68k_aout_machtype = 2;
3195 #endif
3196
3197 /* Note which set of "movec" control registers is available. */
3198 switch (cpu_of_arch (current_architecture))
3199 {
3200 case m68000:
3201 control_regs = m68000_control_regs;
3202 break;
3203 case m68010:
3204 control_regs = m68010_control_regs;
3205 break;
3206 case m68020:
3207 case m68030:
3208 control_regs = m68020_control_regs;
3209 break;
3210 case m68040:
3211 control_regs = m68040_control_regs;
3212 break;
3213 case m68060:
3214 control_regs = m68060_control_regs;
3215 break;
3216 case cpu32:
3217 control_regs = cpu32_control_regs;
3218 break;
3219 default:
3220 abort ();
3221 }
3222
3223 if (cpu_of_arch (current_architecture) < m68020)
3224 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3225 }
3226
3227 /* Equal to MAX_PRECISION in atof-ieee.c */
3228 #define MAX_LITTLENUMS 6
3229
3230 /* Turn a string in input_line_pointer into a floating point constant
3231 of type type, and store the appropriate bytes in *litP. The number
3232 of LITTLENUMS emitted is stored in *sizeP . An error message is
3233 returned, or NULL on OK. */
3234
3235 char *
3236 md_atof (type, litP, sizeP)
3237 char type;
3238 char *litP;
3239 int *sizeP;
3240 {
3241 int prec;
3242 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3243 LITTLENUM_TYPE *wordP;
3244 char *t;
3245 char *atof_ieee ();
3246
3247 switch (type)
3248 {
3249 case 'f':
3250 case 'F':
3251 case 's':
3252 case 'S':
3253 prec = 2;
3254 break;
3255
3256 case 'd':
3257 case 'D':
3258 case 'r':
3259 case 'R':
3260 prec = 4;
3261 break;
3262
3263 case 'x':
3264 case 'X':
3265 prec = 6;
3266 break;
3267
3268 case 'p':
3269 case 'P':
3270 prec = 6;
3271 break;
3272
3273 default:
3274 *sizeP = 0;
3275 return "Bad call to MD_ATOF()";
3276 }
3277 t = atof_ieee (input_line_pointer, type, words);
3278 if (t)
3279 input_line_pointer = t;
3280
3281 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3282 for (wordP = words; prec--;)
3283 {
3284 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3285 litP += sizeof (LITTLENUM_TYPE);
3286 }
3287 return 0;
3288 }
3289
3290 void
3291 md_number_to_chars (buf, val, n)
3292 char *buf;
3293 valueT val;
3294 int n;
3295 {
3296 number_to_chars_bigendian (buf, val, n);
3297 }
3298
3299 static void
3300 md_apply_fix_2 (fixP, val)
3301 fixS *fixP;
3302 offsetT val;
3303 {
3304 addressT upper_limit;
3305 offsetT lower_limit;
3306
3307 /* This is unnecessary but it convinces the native rs6000 compiler
3308 to generate the code we want. */
3309 char *buf = fixP->fx_frag->fr_literal;
3310 buf += fixP->fx_where;
3311 /* end ibm compiler workaround */
3312
3313 if (val & 0x80000000)
3314 val |= ~(addressT)0x7fffffff;
3315 else
3316 val &= 0x7fffffff;
3317
3318 switch (fixP->fx_size)
3319 {
3320 /* The cast to offsetT below are necessary to make code correct for
3321 machines where ints are smaller than offsetT */
3322 case 1:
3323 *buf++ = val;
3324 upper_limit = 0x7f;
3325 lower_limit = - (offsetT) 0x80;
3326 break;
3327 case 2:
3328 *buf++ = (val >> 8);
3329 *buf++ = val;
3330 upper_limit = 0x7fff;
3331 lower_limit = - (offsetT) 0x8000;
3332 break;
3333 case 4:
3334 *buf++ = (val >> 24);
3335 *buf++ = (val >> 16);
3336 *buf++ = (val >> 8);
3337 *buf++ = val;
3338 upper_limit = 0x7fffffff;
3339 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3340 break;
3341 default:
3342 BAD_CASE (fixP->fx_size);
3343 }
3344
3345 /* For non-pc-relative values, it's conceivable we might get something
3346 like "0xff" for a byte field. So extend the upper part of the range
3347 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3348 so that we can do any range checking at all. */
3349 if (!fixP->fx_pcrel)
3350 upper_limit = upper_limit * 2 + 1;
3351
3352 if ((addressT) val > upper_limit
3353 && (val > 0 || val < lower_limit))
3354 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3355
3356 /* A one byte PC-relative reloc means a short branch. We can't use
3357 a short branch with a value of 0 or -1, because those indicate
3358 different opcodes (branches with longer offsets). */
3359 if (fixP->fx_pcrel
3360 && fixP->fx_size == 1
3361 && (fixP->fx_addsy == NULL
3362 || S_IS_DEFINED (fixP->fx_addsy))
3363 && (val == 0 || val == -1))
3364 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3365 }
3366
3367 #ifdef BFD_ASSEMBLER
3368 int
3369 md_apply_fix (fixP, valp)
3370 fixS *fixP;
3371 valueT *valp;
3372 {
3373 md_apply_fix_2 (fixP, (addressT) *valp);
3374 return 1;
3375 }
3376 #else
3377 void md_apply_fix (fixP, val)
3378 fixS *fixP;
3379 long val;
3380 {
3381 md_apply_fix_2 (fixP, (addressT) val);
3382 }
3383 #endif
3384
3385 /* *fragP has been relaxed to its final size, and now needs to have
3386 the bytes inside it modified to conform to the new size There is UGLY
3387 MAGIC here. ..
3388 */
3389 void
3390 md_convert_frag_1 (fragP)
3391 register fragS *fragP;
3392 {
3393 long disp;
3394 long ext = 0;
3395 fixS *fixP;
3396
3397 /* Address in object code of the displacement. */
3398 register int object_address = fragP->fr_fix + fragP->fr_address;
3399
3400 /* Address in gas core of the place to store the displacement. */
3401 /* This convinces the native rs6000 compiler to generate the code we
3402 want. */
3403 register char *buffer_address = fragP->fr_literal;
3404 buffer_address += fragP->fr_fix;
3405 /* end ibm compiler workaround */
3406
3407 /* The displacement of the address, from current location. */
3408 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3409 disp = (disp + fragP->fr_offset) - object_address;
3410
3411 #ifdef BFD_ASSEMBLER
3412 disp += fragP->fr_symbol->sy_frag->fr_address;
3413 #endif
3414
3415 switch (fragP->fr_subtype)
3416 {
3417 case TAB (BCC68000, BYTE):
3418 case TAB (ABRANCH, BYTE):
3419 know (issbyte (disp));
3420 if (disp == 0)
3421 as_bad ("short branch with zero offset: use :w");
3422 fragP->fr_opcode[1] = disp;
3423 ext = 0;
3424 break;
3425 case TAB (DBCC, SHORT):
3426 know (issword (disp));
3427 ext = 2;
3428 break;
3429 case TAB (BCC68000, SHORT):
3430 case TAB (ABRANCH, SHORT):
3431 know (issword (disp));
3432 fragP->fr_opcode[1] = 0x00;
3433 ext = 2;
3434 break;
3435 case TAB (ABRANCH, LONG):
3436 if (cpu_of_arch (current_architecture) < m68020)
3437 {
3438 if (fragP->fr_opcode[0] == 0x61)
3439 /* BSR */
3440 {
3441 fragP->fr_opcode[0] = 0x4E;
3442 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3443 subseg_change (text_section, 0); /* @@ */
3444
3445 fix_new (fragP,
3446 fragP->fr_fix,
3447 4,
3448 fragP->fr_symbol,
3449 fragP->fr_offset,
3450 0,
3451 NO_RELOC);
3452
3453 fragP->fr_fix += 4;
3454 ext = 0;
3455 }
3456 /* BRA */
3457 else if (fragP->fr_opcode[0] == 0x60)
3458 {
3459 fragP->fr_opcode[0] = 0x4E;
3460 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3461 subseg_change (text_section, 0); /* @@ */
3462 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3463 fragP->fr_offset, 0, NO_RELOC);
3464 fragP->fr_fix += 4;
3465 ext = 0;
3466 }
3467 else
3468 {
3469 as_bad ("Long branch offset not supported.");
3470 }
3471 }
3472 else
3473 {
3474 fragP->fr_opcode[1] = (char) 0xff;
3475 ext = 4;
3476 }
3477 break;
3478 case TAB (BCC68000, LONG):
3479 /* only Bcc 68000 instructions can come here */
3480 /* change bcc into b!cc/jmp absl long */
3481 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3482 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3483
3484 /* JF: these used to be fr_opcode[2,3], but they may be in a
3485 different frag, in which case refering to them is a no-no.
3486 Only fr_opcode[0,1] are guaranteed to work. */
3487 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3488 *buffer_address++ = (char) 0xf9;
3489 fragP->fr_fix += 2; /* account for jmp instruction */
3490 subseg_change (text_section, 0);
3491 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3492 fragP->fr_offset, 0, NO_RELOC);
3493 fragP->fr_fix += 4;
3494 ext = 0;
3495 break;
3496 case TAB (DBCC, LONG):
3497 /* only DBcc 68000 instructions can come here */
3498 /* change dbcc into dbcc/jmp absl long */
3499 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3500 *buffer_address++ = 0x00; /* branch offset = 4 */
3501 *buffer_address++ = 0x04;
3502 *buffer_address++ = 0x60; /* put in bra pc+6 */
3503 *buffer_address++ = 0x06;
3504 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3505 *buffer_address++ = (char) 0xf9;
3506
3507 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3508 subseg_change (text_section, 0);
3509 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3510 fragP->fr_offset, 0, NO_RELOC);
3511 fragP->fr_fix += 4;
3512 ext = 0;
3513 break;
3514 case TAB (FBRANCH, SHORT):
3515 know ((fragP->fr_opcode[1] & 0x40) == 0);
3516 ext = 2;
3517 break;
3518 case TAB (FBRANCH, LONG):
3519 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3520 ext = 4;
3521 break;
3522 case TAB (PCREL, SHORT):
3523 ext = 2;
3524 break;
3525 case TAB (PCREL, LONG):
3526 /* The thing to do here is force it to ABSOLUTE LONG, since
3527 PCREL is really trying to shorten an ABSOLUTE address anyway */
3528 /* JF FOO This code has not been tested */
3529 subseg_change (text_section, 0);
3530 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3531 0, NO_RELOC);
3532 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3533 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3534 (unsigned) fragP->fr_opcode[0],
3535 (unsigned long) fragP->fr_address);
3536 fragP->fr_opcode[1] &= ~0x3F;
3537 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3538 fragP->fr_fix += 4;
3539 ext = 0;
3540 break;
3541 case TAB (PCLEA, SHORT):
3542 subseg_change (text_section, 0);
3543 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3544 fragP->fr_offset, 1, NO_RELOC);
3545 fragP->fr_opcode[1] &= ~0x3F;
3546 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3547 ext = 2;
3548 break;
3549 case TAB (PCLEA, LONG):
3550 subseg_change (text_section, 0);
3551 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3552 fragP->fr_offset, 1, NO_RELOC);
3553 fixP->fx_pcrel_adjust = 2;
3554 /* Already set to mode 7.3; this indicates: PC indirect with
3555 suppressed index, 32-bit displacement. */
3556 *buffer_address++ = 0x01;
3557 *buffer_address++ = 0x70;
3558 fragP->fr_fix += 2;
3559 ext = 4;
3560 break;
3561
3562 case TAB (PCINDEX, BYTE):
3563 disp += 2;
3564 if (!issbyte (disp))
3565 {
3566 as_bad ("displacement doesn't fit in one byte");
3567 disp = 0;
3568 }
3569 assert (fragP->fr_fix >= 2);
3570 buffer_address[-2] &= ~1;
3571 buffer_address[-1] = disp;
3572 ext = 0;
3573 break;
3574 case TAB (PCINDEX, SHORT):
3575 subseg_change (text_section, 0);
3576 disp += 2;
3577 assert (issword (disp));
3578 assert (fragP->fr_fix >= 2);
3579 buffer_address[-2] |= 0x1;
3580 buffer_address[-1] = 0x20;
3581 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3582 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3583 NO_RELOC);
3584 fixP->fx_pcrel_adjust = 2;
3585 ext = 2;
3586 break;
3587 case TAB (PCINDEX, LONG):
3588 subseg_change (text_section, 0);
3589 disp += 2;
3590 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3591 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3592 NO_RELOC);
3593 fixP->fx_pcrel_adjust = 2;
3594 assert (fragP->fr_fix >= 2);
3595 buffer_address[-2] |= 0x1;
3596 buffer_address[-1] = 0x30;
3597 ext = 4;
3598 break;
3599 }
3600
3601 if (ext)
3602 {
3603 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3604 fragP->fr_fix += ext;
3605 }
3606 }
3607
3608 #ifndef BFD_ASSEMBLER
3609
3610 void
3611 md_convert_frag (headers, sec, fragP)
3612 object_headers *headers;
3613 segT sec;
3614 fragS *fragP;
3615 {
3616 md_convert_frag_1 (fragP);
3617 }
3618
3619 #else
3620
3621 void
3622 md_convert_frag (abfd, sec, fragP)
3623 bfd *abfd;
3624 segT sec;
3625 fragS *fragP;
3626 {
3627 md_convert_frag_1 (fragP);
3628 }
3629 #endif
3630
3631 /* Force truly undefined symbols to their maximum size, and generally set up
3632 the frag list to be relaxed
3633 */
3634 int
3635 md_estimate_size_before_relax (fragP, segment)
3636 register fragS *fragP;
3637 segT segment;
3638 {
3639 int old_fix;
3640 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3641
3642 old_fix = fragP->fr_fix;
3643
3644 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3645 switch (fragP->fr_subtype)
3646 {
3647
3648 case TAB (ABRANCH, SZ_UNDEF):
3649 {
3650 if ((fragP->fr_symbol != NULL) /* Not absolute */
3651 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3652 {
3653 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3654 break;
3655 }
3656 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3657 {
3658 /* On 68000, or for absolute value, switch to abs long */
3659 /* FIXME, we should check abs val, pick short or long */
3660 if (fragP->fr_opcode[0] == 0x61)
3661 {
3662 fragP->fr_opcode[0] = 0x4E;
3663 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3664 subseg_change (text_section, 0);
3665 fix_new (fragP, fragP->fr_fix, 4,
3666 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3667 fragP->fr_fix += 4;
3668 frag_wane (fragP);
3669 }
3670 else if (fragP->fr_opcode[0] == 0x60)
3671 {
3672 fragP->fr_opcode[0] = 0x4E;
3673 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3674 subseg_change (text_section, 0);
3675 fix_new (fragP, fragP->fr_fix, 4,
3676 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3677 fragP->fr_fix += 4;
3678 frag_wane (fragP);
3679 }
3680 else
3681 {
3682 as_warn ("Long branch offset to extern symbol not supported.");
3683 }
3684 }
3685 else
3686 { /* Symbol is still undefined. Make it simple */
3687 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3688 fragP->fr_offset, 1, NO_RELOC);
3689 fragP->fr_fix += 4;
3690 fragP->fr_opcode[1] = (char) 0xff;
3691 frag_wane (fragP);
3692 break;
3693 }
3694
3695 break;
3696 } /* case TAB(ABRANCH,SZ_UNDEF) */
3697
3698 case TAB (FBRANCH, SZ_UNDEF):
3699 {
3700 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3701 {
3702 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3703 fragP->fr_var += 2;
3704 }
3705 else
3706 {
3707 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3708 fragP->fr_offset, 1, NO_RELOC);
3709 fragP->fr_fix += 4;
3710 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3711 frag_wane (fragP);
3712 }
3713 break;
3714 } /* TAB(FBRANCH,SZ_UNDEF) */
3715
3716 case TAB (PCREL, SZ_UNDEF):
3717 {
3718 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3719 || flag_short_refs
3720 || cpu_of_arch (current_architecture) < m68020)
3721 {
3722 fragP->fr_subtype = TAB (PCREL, SHORT);
3723 fragP->fr_var += 2;
3724 }
3725 else
3726 {
3727 fragP->fr_subtype = TAB (PCREL, LONG);
3728 fragP->fr_var += 4;
3729 }
3730 break;
3731 } /* TAB(PCREL,SZ_UNDEF) */
3732
3733 case TAB (BCC68000, SZ_UNDEF):
3734 {
3735 if ((fragP->fr_symbol != NULL)
3736 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3737 {
3738 fragP->fr_subtype = TAB (BCC68000, BYTE);
3739 break;
3740 }
3741 /* only Bcc 68000 instructions can come here */
3742 /* change bcc into b!cc/jmp absl long */
3743 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3744 if (flag_short_refs)
3745 {
3746 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
3747 /* JF: these were fr_opcode[2,3] */
3748 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3749 buffer_address[1] = (char) 0xf8;
3750 fragP->fr_fix += 2; /* account for jmp instruction */
3751 subseg_change (text_section, 0);
3752 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3753 fragP->fr_offset, 0, NO_RELOC);
3754 fragP->fr_fix += 2;
3755 }
3756 else
3757 {
3758 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
3759 /* JF: these were fr_opcode[2,3] */
3760 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
3761 buffer_address[1] = (char) 0xf9;
3762 fragP->fr_fix += 2; /* account for jmp instruction */
3763 subseg_change (text_section, 0);
3764 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3765 fragP->fr_offset, 0, NO_RELOC);
3766 fragP->fr_fix += 4;
3767 }
3768 frag_wane (fragP);
3769 break;
3770 } /* case TAB(BCC68000,SZ_UNDEF) */
3771
3772 case TAB (DBCC, SZ_UNDEF):
3773 {
3774 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3775 {
3776 fragP->fr_subtype = TAB (DBCC, SHORT);
3777 fragP->fr_var += 2;
3778 break;
3779 }
3780 /* only DBcc 68000 instructions can come here */
3781 /* change dbcc into dbcc/jmp absl long */
3782 /* JF: these used to be fr_opcode[2-4], which is wrong. */
3783 buffer_address[0] = 0x00; /* branch offset = 4 */
3784 buffer_address[1] = 0x04;
3785 buffer_address[2] = 0x60; /* put in bra pc + ... */
3786
3787 if (flag_short_refs)
3788 {
3789 /* JF: these were fr_opcode[5-7] */
3790 buffer_address[3] = 0x04; /* plus 4 */
3791 buffer_address[4] = 0x4e; /* Put in Jump Word */
3792 buffer_address[5] = (char) 0xf8;
3793 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3794 subseg_change (text_section, 0);
3795 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
3796 fragP->fr_offset, 0, NO_RELOC);
3797 fragP->fr_fix += 2;
3798 }
3799 else
3800 {
3801 /* JF: these were fr_opcode[5-7] */
3802 buffer_address[3] = 0x06; /* Plus 6 */
3803 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
3804 buffer_address[5] = (char) 0xf9;
3805 fragP->fr_fix += 6; /* account for bra/jmp instruction */
3806 subseg_change (text_section, 0);
3807 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3808 fragP->fr_offset, 0, NO_RELOC);
3809 fragP->fr_fix += 4;
3810 }
3811
3812 frag_wane (fragP);
3813 break;
3814 } /* case TAB(DBCC,SZ_UNDEF) */
3815
3816 case TAB (PCLEA, SZ_UNDEF):
3817 {
3818 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
3819 || flag_short_refs
3820 || cpu_of_arch (current_architecture) < m68020)
3821 {
3822 fragP->fr_subtype = TAB (PCLEA, SHORT);
3823 fragP->fr_var += 2;
3824 }
3825 else
3826 {
3827 fragP->fr_subtype = TAB (PCLEA, LONG);
3828 fragP->fr_var += 6;
3829 }
3830 break;
3831 } /* TAB(PCLEA,SZ_UNDEF) */
3832
3833 case TAB (PCINDEX, SZ_UNDEF):
3834 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3835 || cpu_of_arch (current_architecture) < m68020)
3836 {
3837 fragP->fr_subtype = TAB (PCINDEX, BYTE);
3838 }
3839 else
3840 {
3841 fragP->fr_subtype = TAB (PCINDEX, LONG);
3842 fragP->fr_var += 4;
3843 }
3844 break;
3845
3846 default:
3847 break;
3848 }
3849
3850 /* now that SZ_UNDEF are taken care of, check others */
3851 switch (fragP->fr_subtype)
3852 {
3853 case TAB (BCC68000, BYTE):
3854 case TAB (ABRANCH, BYTE):
3855 /* We can't do a short jump to the next instruction,
3856 so we force word mode. */
3857 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
3858 fragP->fr_symbol->sy_frag == fragP->fr_next)
3859 {
3860 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
3861 fragP->fr_var += 2;
3862 }
3863 break;
3864 default:
3865 break;
3866 }
3867 return fragP->fr_var + fragP->fr_fix - old_fix;
3868 }
3869
3870 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
3871 /* the bit-field entries in the relocation_info struct plays hell
3872 with the byte-order problems of cross-assembly. So as a hack,
3873 I added this mach. dependent ri twiddler. Ugly, but it gets
3874 you there. -KWK */
3875 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
3876 are symbolnum, most sig. byte first. Last byte is broken up with
3877 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
3878 nibble as nuthin. (on Sun 3 at least) */
3879 /* Translate the internal relocation information into target-specific
3880 format. */
3881 #ifdef comment
3882 void
3883 md_ri_to_chars (the_bytes, ri)
3884 char *the_bytes;
3885 struct reloc_info_generic *ri;
3886 {
3887 /* this is easy */
3888 md_number_to_chars (the_bytes, ri->r_address, 4);
3889 /* now the fun stuff */
3890 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
3891 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
3892 the_bytes[6] = ri->r_symbolnum & 0x0ff;
3893 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
3894 ((ri->r_extern << 4) & 0x10));
3895 }
3896
3897 #endif /* comment */
3898
3899 #ifndef BFD_ASSEMBLER
3900 void
3901 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
3902 char *where;
3903 fixS *fixP;
3904 relax_addressT segment_address_in_file;
3905 {
3906 /*
3907 * In: length of relocation (or of address) in chars: 1, 2 or 4.
3908 * Out: GNU LD relocation length code: 0, 1, or 2.
3909 */
3910
3911 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
3912 long r_symbolnum;
3913
3914 know (fixP->fx_addsy != NULL);
3915
3916 md_number_to_chars (where,
3917 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
3918 4);
3919
3920 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
3921 ? S_GET_TYPE (fixP->fx_addsy)
3922 : fixP->fx_addsy->sy_number);
3923
3924 where[4] = (r_symbolnum >> 16) & 0x0ff;
3925 where[5] = (r_symbolnum >> 8) & 0x0ff;
3926 where[6] = r_symbolnum & 0x0ff;
3927 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
3928 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
3929 }
3930 #endif
3931
3932 #endif /* OBJ_AOUT or OBJ_BOUT */
3933
3934 #ifndef WORKING_DOT_WORD
3935 CONST int md_short_jump_size = 4;
3936 CONST int md_long_jump_size = 6;
3937
3938 void
3939 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3940 char *ptr;
3941 addressT from_addr, to_addr;
3942 fragS *frag;
3943 symbolS *to_symbol;
3944 {
3945 valueT offset;
3946
3947 offset = to_addr - (from_addr + 2);
3948
3949 md_number_to_chars (ptr, (valueT) 0x6000, 2);
3950 md_number_to_chars (ptr + 2, (valueT) offset, 2);
3951 }
3952
3953 void
3954 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3955 char *ptr;
3956 addressT from_addr, to_addr;
3957 fragS *frag;
3958 symbolS *to_symbol;
3959 {
3960 valueT offset;
3961
3962 if (cpu_of_arch (current_architecture) < m68020)
3963 {
3964 offset = to_addr - S_GET_VALUE (to_symbol);
3965 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
3966 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3967 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
3968 0, NO_RELOC);
3969 }
3970 else
3971 {
3972 offset = to_addr - (from_addr + 2);
3973 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
3974 md_number_to_chars (ptr + 2, (valueT) offset, 4);
3975 }
3976 }
3977
3978 #endif
3979
3980 /* Different values of OK tell what its OK to return. Things that
3981 aren't OK are an error (what a shock, no?)
3982
3983 0: Everything is OK
3984 10: Absolute 1:8 only
3985 20: Absolute 0:7 only
3986 30: absolute 0:15 only
3987 40: Absolute 0:31 only
3988 50: absolute 0:127 only
3989 55: absolute -64:63 only
3990 60: absolute -128:127 only
3991 70: absolute 0:4095 only
3992 80: No bignums
3993
3994 */
3995
3996 static int
3997 get_num (exp, ok)
3998 struct m68k_exp *exp;
3999 int ok;
4000 {
4001 if (exp->exp.X_op == O_absent)
4002 {
4003 /* Do the same thing the VAX asm does */
4004 op (exp) = O_constant;
4005 adds (exp) = 0;
4006 subs (exp) = 0;
4007 offs (exp) = 0;
4008 if (ok == 10)
4009 {
4010 as_warn ("expression out of range: defaulting to 1");
4011 offs (exp) = 1;
4012 }
4013 }
4014 else if (exp->exp.X_op == O_constant)
4015 {
4016 switch (ok)
4017 {
4018 case 10:
4019 if (offs (exp) < 1 || offs (exp) > 8)
4020 {
4021 as_warn ("expression out of range: defaulting to 1");
4022 offs (exp) = 1;
4023 }
4024 break;
4025 case 20:
4026 if (offs (exp) < 0 || offs (exp) > 7)
4027 goto outrange;
4028 break;
4029 case 30:
4030 if (offs (exp) < 0 || offs (exp) > 15)
4031 goto outrange;
4032 break;
4033 case 40:
4034 if (offs (exp) < 0 || offs (exp) > 32)
4035 goto outrange;
4036 break;
4037 case 50:
4038 if (offs (exp) < 0 || offs (exp) > 127)
4039 goto outrange;
4040 break;
4041 case 55:
4042 if (offs (exp) < -64 || offs (exp) > 63)
4043 goto outrange;
4044 break;
4045 case 60:
4046 if (offs (exp) < -128 || offs (exp) > 127)
4047 goto outrange;
4048 break;
4049 case 70:
4050 if (offs (exp) < 0 || offs (exp) > 4095)
4051 {
4052 outrange:
4053 as_warn ("expression out of range: defaulting to 0");
4054 offs (exp) = 0;
4055 }
4056 break;
4057 default:
4058 break;
4059 }
4060 }
4061 else if (exp->exp.X_op == O_big)
4062 {
4063 if (offs (exp) <= 0 /* flonum */
4064 && (ok == 80 /* no bignums */
4065 || (ok > 10 /* small-int ranges including 0 ok */
4066 /* If we have a flonum zero, a zero integer should
4067 do as well (e.g., in moveq). */
4068 && generic_floating_point_number.exponent == 0
4069 && generic_floating_point_number.low[0] == 0)))
4070 {
4071 /* HACK! Turn it into a long */
4072 LITTLENUM_TYPE words[6];
4073
4074 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4075 op (exp) = O_constant;
4076 adds (exp) = 0;
4077 subs (exp) = 0;
4078 offs (exp) = words[1] | (words[0] << 16);
4079 }
4080 else if (ok != 0)
4081 {
4082 op (exp) = O_constant;
4083 adds (exp) = 0;
4084 subs (exp) = 0;
4085 offs (exp) = (ok == 10) ? 1 : 0;
4086 as_warn ("Can't deal with expression; defaulting to %ld",
4087 offs (exp));
4088 }
4089 }
4090 else
4091 {
4092 if (ok >= 10 && ok <= 70)
4093 {
4094 op (exp) = O_constant;
4095 adds (exp) = 0;
4096 subs (exp) = 0;
4097 offs (exp) = (ok == 10) ? 1 : 0;
4098 as_warn ("Can't deal with expression; defaulting to %ld",
4099 offs (exp));
4100 }
4101 }
4102
4103 if (exp->size != SIZE_UNSPEC)
4104 {
4105 switch (exp->size)
4106 {
4107 case SIZE_UNSPEC:
4108 case SIZE_LONG:
4109 break;
4110 case SIZE_BYTE:
4111 if (!isbyte (offs (exp)))
4112 as_warn ("expression doesn't fit in BYTE");
4113 break;
4114 case SIZE_WORD:
4115 if (!isword (offs (exp)))
4116 as_warn ("expression doesn't fit in WORD");
4117 break;
4118 }
4119 }
4120
4121 return offs (exp);
4122 }
4123
4124 /* These are the back-ends for the various machine dependent pseudo-ops. */
4125 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4126
4127 static void
4128 s_data1 (ignore)
4129 int ignore;
4130 {
4131 subseg_set (data_section, 1);
4132 demand_empty_rest_of_line ();
4133 }
4134
4135 static void
4136 s_data2 (ignore)
4137 int ignore;
4138 {
4139 subseg_set (data_section, 2);
4140 demand_empty_rest_of_line ();
4141 }
4142
4143 static void
4144 s_bss (ignore)
4145 int ignore;
4146 {
4147 /* We don't support putting frags in the BSS segment, we fake it
4148 by marking in_bss, then looking at s_skip for clues. */
4149
4150 subseg_set (bss_section, 0);
4151 demand_empty_rest_of_line ();
4152 }
4153
4154 static void
4155 s_even (ignore)
4156 int ignore;
4157 {
4158 register int temp;
4159 register long temp_fill;
4160
4161 temp = 1; /* JF should be 2? */
4162 temp_fill = get_absolute_expression ();
4163 if (!need_pass_2) /* Never make frag if expect extra pass. */
4164 frag_align (temp, (int) temp_fill);
4165 demand_empty_rest_of_line ();
4166 }
4167
4168 static void
4169 s_proc (ignore)
4170 int ignore;
4171 {
4172 demand_empty_rest_of_line ();
4173 }
4174 \f
4175 /* Pseudo-ops handled for MRI compatibility. */
4176
4177 /* Handle an MRI style chip specification. */
4178
4179 static void
4180 mri_chip ()
4181 {
4182 char *s;
4183 char c;
4184 int i;
4185
4186 s = input_line_pointer;
4187 c = get_symbol_end ();
4188 for (i = 0; i < n_archs; i++)
4189 if (strcasecmp (s, archs[i].name) == 0)
4190 break;
4191 if (i >= n_archs)
4192 {
4193 as_bad ("%s: unrecognized processor name", s);
4194 *input_line_pointer = c;
4195 ignore_rest_of_line ();
4196 return;
4197 }
4198 *input_line_pointer = c;
4199
4200 if (*input_line_pointer == '/')
4201 current_architecture = 0;
4202 else
4203 current_architecture &= m68881 | m68851;
4204 current_architecture |= archs[i].arch;
4205
4206 while (*input_line_pointer == '/')
4207 {
4208 ++input_line_pointer;
4209 s = input_line_pointer;
4210 c = get_symbol_end ();
4211 if (strcmp (s, "68881") == 0)
4212 current_architecture |= m68881;
4213 else if (strcmp (s, "68851") == 0)
4214 current_architecture |= m68851;
4215 *input_line_pointer = c;
4216 }
4217 }
4218
4219 /* The MRI CHIP pseudo-op. */
4220
4221 static void
4222 s_chip (ignore)
4223 int ignore;
4224 {
4225 mri_chip ();
4226 demand_empty_rest_of_line ();
4227 }
4228
4229 /* The MRI FOPT pseudo-op. */
4230
4231 static void
4232 s_fopt (ignore)
4233 int ignore;
4234 {
4235 SKIP_WHITESPACE ();
4236
4237 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4238 {
4239 int temp;
4240
4241 input_line_pointer += 3;
4242 temp = get_absolute_expression ();
4243 if (temp < 0 || temp > 7)
4244 as_bad ("bad coprocessor id");
4245 else
4246 m68k_float_copnum = COP0 + temp;
4247 }
4248 else
4249 {
4250 as_bad ("unrecognized fopt option");
4251 ignore_rest_of_line ();
4252 return;
4253 }
4254
4255 demand_empty_rest_of_line ();
4256 }
4257
4258 /* The structure used to handle the MRI OPT pseudo-op. */
4259
4260 struct opt_action
4261 {
4262 /* The name of the option. */
4263 const char *name;
4264
4265 /* If this is not NULL, just call this function. The first argument
4266 is the ARG field of this structure, the second argument is
4267 whether the option was negated. */
4268 void (*pfn) PARAMS ((int arg, int on));
4269
4270 /* If this is not NULL, and the PFN field is NULL, set the variable
4271 this points to. Set it to the ARG field if the option was not
4272 negated, and the NOTARG field otherwise. */
4273 int *pvar;
4274
4275 /* The value to pass to PFN or to assign to *PVAR. */
4276 int arg;
4277
4278 /* The value to assign to *PVAR if the option is negated. If PFN is
4279 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4280 the option may not be negated. */
4281 int notarg;
4282 };
4283
4284 /* The table used to handle the MRI OPT pseudo-op. */
4285
4286 static void skip_to_comma PARAMS ((int, int));
4287 static void opt_nest PARAMS ((int, int));
4288 static void opt_chip PARAMS ((int, int));
4289 static void opt_list PARAMS ((int, int));
4290 static void opt_list_symbols PARAMS ((int, int));
4291
4292 static const struct opt_action opt_table[] =
4293 {
4294 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4295
4296 /* We do relaxing, so there is little use for these options. */
4297 { "b", 0, 0, 0, 0 },
4298 { "brs", 0, 0, 0, 0 },
4299 { "brb", 0, 0, 0, 0 },
4300 { "brl", 0, 0, 0, 0 },
4301 { "brw", 0, 0, 0, 0 },
4302
4303 { "c", 0, 0, 0, 0 },
4304 { "cex", 0, 0, 0, 0 },
4305 { "case", 0, &symbols_case_sensitive, 1, 0 },
4306 { "cl", 0, 0, 0, 0 },
4307 { "cre", 0, 0, 0, 0 },
4308 { "d", 0, &flag_keep_locals, 1, 0 },
4309 { "e", 0, 0, 0, 0 },
4310 { "f", 0, &flag_short_refs, 1, 0 },
4311 { "frs", 0, &flag_short_refs, 1, 0 },
4312 { "frl", 0, &flag_short_refs, 0, 1 },
4313 { "g", 0, 0, 0, 0 },
4314 { "i", 0, 0, 0, 0 },
4315 { "m", 0, 0, 0, 0 },
4316 { "mex", 0, 0, 0, 0 },
4317 { "mc", 0, 0, 0, 0 },
4318 { "md", 0, 0, 0, 0 },
4319 { "nest", opt_nest, 0, 0, 0 },
4320 { "next", skip_to_comma, 0, 0, 0 },
4321 { "o", 0, 0, 0, 0 },
4322 { "old", 0, 0, 0, 0 },
4323 { "op", skip_to_comma, 0, 0, 0 },
4324 { "pco", 0, 0, 0, 0 },
4325 { "p", opt_chip, 0, 0, 0 },
4326 { "pcr", 0, 0, 0, 0 },
4327 { "pcs", 0, 0, 0, 0 },
4328 { "r", 0, 0, 0, 0 },
4329 { "quick", 0, &m68k_quick, 1, 0 },
4330 { "rel32", 0, &m68k_rel32, 1, 0 },
4331 { "s", opt_list, 0, 0, 0 },
4332 { "t", opt_list_symbols, 0, 0, 0 },
4333 { "w", 0, &flag_no_warnings, 0, 1 },
4334 { "x", 0, 0, 0, 0 }
4335 };
4336
4337 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4338
4339 /* The MRI OPT pseudo-op. */
4340
4341 static void
4342 s_opt (ignore)
4343 int ignore;
4344 {
4345 do
4346 {
4347 int t;
4348 char *s;
4349 char c;
4350 int i;
4351 const struct opt_action *o;
4352
4353 SKIP_WHITESPACE ();
4354
4355 t = 1;
4356 if (*input_line_pointer == '-')
4357 {
4358 ++input_line_pointer;
4359 t = 0;
4360 }
4361 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4362 {
4363 input_line_pointer += 2;
4364 t = 0;
4365 }
4366
4367 s = input_line_pointer;
4368 c = get_symbol_end ();
4369
4370 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4371 {
4372 if (strcasecmp (s, o->name) == 0)
4373 {
4374 if (o->pfn)
4375 {
4376 /* Restore input_line_pointer now in case the option
4377 takes arguments. */
4378 *input_line_pointer = c;
4379 (*o->pfn) (o->arg, t);
4380 }
4381 else if (o->pvar != NULL)
4382 {
4383 if (! t && o->arg == o->notarg)
4384 as_bad ("option `%s' may not be negated", s);
4385 *input_line_pointer = c;
4386 *o->pvar = t ? o->arg : o->notarg;
4387 }
4388 else
4389 *input_line_pointer = c;
4390 break;
4391 }
4392 }
4393 if (i >= OPTCOUNT)
4394 {
4395 as_bad ("option `%s' not recognized", s);
4396 *input_line_pointer = c;
4397 }
4398 }
4399 while (*input_line_pointer++ == ',');
4400
4401 /* Move back to terminating character. */
4402 --input_line_pointer;
4403 demand_empty_rest_of_line ();
4404 }
4405
4406 /* Skip ahead to a comma. This is used for OPT options which we do
4407 not suppor tand which take arguments. */
4408
4409 static void
4410 skip_to_comma (arg, on)
4411 int arg;
4412 int on;
4413 {
4414 while (*input_line_pointer != ','
4415 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4416 ++input_line_pointer;
4417 }
4418
4419 /* Handle the OPT NEST=depth option. */
4420
4421 static void
4422 opt_nest (arg, on)
4423 int arg;
4424 int on;
4425 {
4426 if (*input_line_pointer != '=')
4427 {
4428 as_bad ("bad format of OPT NEST=depth");
4429 return;
4430 }
4431
4432 ++input_line_pointer;
4433 max_macro_nest = get_absolute_expression ();
4434 }
4435
4436 /* Handle the OPT P=chip option. */
4437
4438 static void
4439 opt_chip (arg, on)
4440 int arg;
4441 int on;
4442 {
4443 if (*input_line_pointer != '=')
4444 {
4445 /* This is just OPT P, which we do not support. */
4446 return;
4447 }
4448
4449 ++input_line_pointer;
4450 mri_chip ();
4451 }
4452
4453 /* Handle the OPT S option. */
4454
4455 static void
4456 opt_list (arg, on)
4457 int arg;
4458 int on;
4459 {
4460 listing_list (on);
4461 }
4462
4463 /* Handle the OPT T option. */
4464
4465 static void
4466 opt_list_symbols (arg, on)
4467 int arg;
4468 int on;
4469 {
4470 if (on)
4471 listing |= LISTING_SYMBOLS;
4472 else
4473 listing &=~ LISTING_SYMBOLS;
4474 }
4475
4476 /* Handle the MRI REG pseudo-op. */
4477
4478 static void
4479 s_reg (ignore)
4480 int ignore;
4481 {
4482 char *s;
4483 int c;
4484 struct m68k_op rop;
4485 unsigned long mask;
4486
4487 if (line_label == NULL)
4488 {
4489 as_bad ("missing label");
4490 ignore_rest_of_line ();
4491 return;
4492 }
4493
4494 SKIP_WHITESPACE ();
4495
4496 s = input_line_pointer;
4497 while (isalnum ((unsigned char) *input_line_pointer)
4498 #ifdef REGISTER_PREFIX
4499 || *input_line_pointer == REGISTER_PREFIX
4500 #endif
4501 || *input_line_pointer == '/'
4502 || *input_line_pointer == '-')
4503 ++input_line_pointer;
4504 c = *input_line_pointer;
4505 *input_line_pointer = '\0';
4506
4507 if (m68k_ip_op (s, &rop) != 0)
4508 {
4509 if (rop.error == NULL)
4510 as_bad ("bad register list");
4511 else
4512 as_bad ("bad register list: %s", rop.error);
4513 *input_line_pointer = c;
4514 ignore_rest_of_line ();
4515 return;
4516 }
4517
4518 *input_line_pointer = c;
4519
4520 if (rop.mode == REGLST)
4521 mask = rop.mask;
4522 else if (rop.mode == DREG)
4523 mask = 1 << (rop.reg - DATA0);
4524 else if (rop.mode == AREG)
4525 mask = 1 << (rop.reg - ADDR0 + 8);
4526 else if (rop.mode == FPREG)
4527 mask = 1 << (rop.reg - FP0 + 16);
4528 else if (rop.mode == CONTROL
4529 && rop.reg == FPI)
4530 mask = 1 << 24;
4531 else if (rop.mode == CONTROL
4532 && rop.reg == FPS)
4533 mask = 1 << 25;
4534 else if (rop.mode == CONTROL
4535 && rop.reg == FPC)
4536 mask = 1 << 26;
4537 else
4538 {
4539 as_bad ("bad register list");
4540 ignore_rest_of_line ();
4541 return;
4542 }
4543
4544 S_SET_SEGMENT (line_label, absolute_section);
4545 S_SET_VALUE (line_label, mask);
4546 line_label->sy_frag = &zero_address_frag;
4547
4548 demand_empty_rest_of_line ();
4549 }
4550
4551 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4552
4553 struct save_opts
4554 {
4555 struct save_opts *next;
4556 int abspcadd;
4557 int symbols_case_sensitive;
4558 int keep_locals;
4559 int short_refs;
4560 int architecture;
4561 int quick;
4562 int rel32;
4563 int listing;
4564 int no_warnings;
4565 /* FIXME: We don't save OPT S. */
4566 };
4567
4568 /* This variable holds the stack of saved options. */
4569
4570 static struct save_opts *save_stack;
4571
4572 /* The MRI SAVE pseudo-op. */
4573
4574 static void
4575 s_save (ignore)
4576 int ignore;
4577 {
4578 struct save_opts *s;
4579
4580 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4581 s->abspcadd = m68k_abspcadd;
4582 s->symbols_case_sensitive = symbols_case_sensitive;
4583 s->keep_locals = flag_keep_locals;
4584 s->short_refs = flag_short_refs;
4585 s->architecture = current_architecture;
4586 s->quick = m68k_quick;
4587 s->rel32 = m68k_rel32;
4588 s->listing = listing;
4589 s->no_warnings = flag_no_warnings;
4590
4591 s->next = save_stack;
4592 save_stack = s;
4593
4594 demand_empty_rest_of_line ();
4595 }
4596
4597 /* The MRI RESTORE pseudo-op. */
4598
4599 static void
4600 s_restore (ignore)
4601 int ignore;
4602 {
4603 struct save_opts *s;
4604
4605 if (save_stack == NULL)
4606 {
4607 as_bad ("restore without save");
4608 ignore_rest_of_line ();
4609 return;
4610 }
4611
4612 s = save_stack;
4613 save_stack = s->next;
4614
4615 m68k_abspcadd = s->abspcadd;
4616 symbols_case_sensitive = s->symbols_case_sensitive;
4617 flag_keep_locals = s->keep_locals;
4618 flag_short_refs = s->short_refs;
4619 current_architecture = s->architecture;
4620 m68k_quick = s->quick;
4621 m68k_rel32 = s->rel32;
4622 listing = s->listing;
4623 flag_no_warnings = s->no_warnings;
4624
4625 free (s);
4626
4627 demand_empty_rest_of_line ();
4628 }
4629
4630 /* Types of MRI structured control directives. */
4631
4632 enum mri_control_type
4633 {
4634 mri_for,
4635 mri_if,
4636 mri_repeat,
4637 mri_while
4638 };
4639
4640 /* This structure is used to stack the MRI structured control
4641 directives. */
4642
4643 struct mri_control_info
4644 {
4645 /* The directive within which this one is enclosed. */
4646 struct mri_control_info *outer;
4647
4648 /* The type of directive. */
4649 enum mri_control_type type;
4650
4651 /* Whether an ELSE has been in an IF. */
4652 int else_seen;
4653
4654 /* The add or sub statement at the end of a FOR. */
4655 char *incr;
4656
4657 /* The label of the top of a FOR or REPEAT loop. */
4658 char *top;
4659
4660 /* The label to jump to for the next iteration, or the else
4661 expression of a conditional. */
4662 char *next;
4663
4664 /* The label to jump to to break out of the loop, or the label past
4665 the end of a conditional. */
4666 char *bottom;
4667 };
4668
4669 /* The stack of MRI structured control directives. */
4670
4671 static struct mri_control_info *mri_control_stack;
4672
4673 /* The current MRI structured control directive index number, used to
4674 generate label names. */
4675
4676 static int mri_control_index;
4677
4678 /* Some function prototypes. */
4679
4680 static char *mri_control_label PARAMS ((void));
4681 static struct mri_control_info *push_mri_control
4682 PARAMS ((enum mri_control_type));
4683 static void pop_mri_control PARAMS ((void));
4684 static int parse_mri_condition PARAMS ((int *));
4685 static int parse_mri_control_operand
4686 PARAMS ((int *, const char **, const char **, const char **, const char **));
4687 static int swap_mri_condition PARAMS ((int));
4688 static int reverse_mri_condition PARAMS ((int));
4689 static void build_mri_control_operand
4690 PARAMS ((int, int, const char *, const char *, const char *, const char *,
4691 const char *, const char *, int));
4692 static void parse_mri_control_expression
4693 PARAMS ((char *, int, const char *, const char *, int));
4694
4695 /* Generate a new MRI label structured control directive label name. */
4696
4697 static char *
4698 mri_control_label ()
4699 {
4700 char *n;
4701
4702 n = (char *) xmalloc (20);
4703 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
4704 ++mri_control_index;
4705 return n;
4706 }
4707
4708 /* Create a new MRI structured control directive. */
4709
4710 static struct mri_control_info *
4711 push_mri_control (type)
4712 enum mri_control_type type;
4713 {
4714 struct mri_control_info *n;
4715
4716 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
4717
4718 n->type = type;
4719 n->else_seen = 0;
4720 if (type == mri_if || type == mri_while)
4721 n->top = NULL;
4722 else
4723 n->top = mri_control_label ();
4724 n->next = mri_control_label ();
4725 n->bottom = mri_control_label ();
4726
4727 n->outer = mri_control_stack;
4728 mri_control_stack = n;
4729
4730 return n;
4731 }
4732
4733 /* Pop off the stack of MRI structured control directives. */
4734
4735 static void
4736 pop_mri_control ()
4737 {
4738 struct mri_control_info *n;
4739
4740 n = mri_control_stack;
4741 mri_control_stack = n->outer;
4742 if (n->top != NULL)
4743 free (n->top);
4744 free (n->next);
4745 free (n->bottom);
4746 free (n);
4747 }
4748
4749 /* Recognize a condition code in an MRI structured control expression. */
4750
4751 static int
4752 parse_mri_condition (pcc)
4753 int *pcc;
4754 {
4755 char c1, c2;
4756
4757 know (*input_line_pointer == '<');
4758
4759 ++input_line_pointer;
4760 c1 = *input_line_pointer++;
4761 c2 = *input_line_pointer++;
4762
4763 if (*input_line_pointer != '>')
4764 {
4765 as_bad ("syntax error in structured control directive");
4766 return 0;
4767 }
4768
4769 ++input_line_pointer;
4770 SKIP_WHITESPACE ();
4771
4772 if (isupper (c1))
4773 c1 = tolower (c1);
4774 if (isupper (c2))
4775 c2 = tolower (c2);
4776
4777 *pcc = (c1 << 8) | c2;
4778
4779 return 1;
4780 }
4781
4782 /* Parse a single operand in an MRI structured control expression. */
4783
4784 static int
4785 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
4786 int *pcc;
4787 const char **leftstart;
4788 const char **leftstop;
4789 const char **rightstart;
4790 const char **rightstop;
4791 {
4792 char *s;
4793
4794 SKIP_WHITESPACE ();
4795
4796 *pcc = -1;
4797 *leftstart = NULL;
4798 *leftstop = NULL;
4799 *rightstart = NULL;
4800 *rightstop = NULL;
4801
4802 if (*input_line_pointer == '<')
4803 {
4804 /* It's just a condition code. */
4805 return parse_mri_condition (pcc);
4806 }
4807
4808 /* Look ahead for the condition code. */
4809 for (s = input_line_pointer; *s != '\0'; ++s)
4810 {
4811 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
4812 break;
4813 }
4814 if (*s == '\0')
4815 {
4816 as_bad ("missing condition code in structured control directive");
4817 return 0;
4818 }
4819
4820 *leftstart = input_line_pointer;
4821 *leftstop = s;
4822 if (*leftstop > *leftstart
4823 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
4824 --*leftstop;
4825
4826 input_line_pointer = s;
4827 if (! parse_mri_condition (pcc))
4828 return 0;
4829
4830 /* Look ahead for AND or OR or end of line. */
4831 for (s = input_line_pointer; *s != '\0'; ++s)
4832 {
4833 if ((strncasecmp (s, "AND", 3) == 0
4834 && (s[3] == '.' || ! is_part_of_name (s[3])))
4835 || (strncasecmp (s, "OR", 2) == 0
4836 && (s[2] == '.' || ! is_part_of_name (s[2]))))
4837 break;
4838 }
4839
4840 *rightstart = input_line_pointer;
4841 *rightstop = s;
4842 if (*rightstop > *rightstart
4843 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
4844 --*rightstop;
4845
4846 input_line_pointer = s;
4847
4848 return 1;
4849 }
4850
4851 #define MCC(b1, b2) (((b1) << 8) | (b2))
4852
4853 /* Swap the sense of a condition. This changes the condition so that
4854 it generates the same result when the operands are swapped. */
4855
4856 static int
4857 swap_mri_condition (cc)
4858 int cc;
4859 {
4860 switch (cc)
4861 {
4862 case MCC ('h', 'i'): return MCC ('c', 's');
4863 case MCC ('l', 's'): return MCC ('c', 'c');
4864 case MCC ('c', 'c'): return MCC ('l', 's');
4865 case MCC ('c', 's'): return MCC ('h', 'i');
4866 case MCC ('p', 'l'): return MCC ('m', 'i');
4867 case MCC ('m', 'i'): return MCC ('p', 'l');
4868 case MCC ('g', 'e'): return MCC ('l', 'e');
4869 case MCC ('l', 't'): return MCC ('g', 't');
4870 case MCC ('g', 't'): return MCC ('l', 't');
4871 case MCC ('l', 'e'): return MCC ('g', 'e');
4872 }
4873 return cc;
4874 }
4875
4876 /* Reverse the sense of a condition. */
4877
4878 static int
4879 reverse_mri_condition (cc)
4880 int cc;
4881 {
4882 switch (cc)
4883 {
4884 case MCC ('h', 'i'): return MCC ('l', 's');
4885 case MCC ('l', 's'): return MCC ('h', 'i');
4886 case MCC ('c', 'c'): return MCC ('c', 's');
4887 case MCC ('c', 's'): return MCC ('c', 'c');
4888 case MCC ('n', 'e'): return MCC ('e', 'q');
4889 case MCC ('e', 'q'): return MCC ('n', 'e');
4890 case MCC ('v', 'c'): return MCC ('v', 's');
4891 case MCC ('v', 's'): return MCC ('v', 'c');
4892 case MCC ('p', 'l'): return MCC ('m', 'i');
4893 case MCC ('m', 'i'): return MCC ('p', 'l');
4894 case MCC ('g', 'e'): return MCC ('l', 't');
4895 case MCC ('l', 't'): return MCC ('g', 'e');
4896 case MCC ('g', 't'): return MCC ('l', 'e');
4897 case MCC ('l', 'e'): return MCC ('g', 't');
4898 }
4899 return cc;
4900 }
4901
4902 /* Build an MRI structured control expression. This generates test
4903 and branch instructions. It goes to TRUELAB if the condition is
4904 true, and to FALSELAB if the condition is false. Exactly one of
4905 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
4906 is the size qualifier for the expression. EXTENT is the size to
4907 use for the branch. */
4908
4909 static void
4910 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
4911 rightstop, truelab, falselab, extent)
4912 int qual;
4913 int cc;
4914 const char *leftstart;
4915 const char *leftstop;
4916 const char *rightstart;
4917 const char *rightstop;
4918 const char *truelab;
4919 const char *falselab;
4920 int extent;
4921 {
4922 char *buf;
4923 char *s;
4924
4925 /* The 68k can't do a general comparision with an immediate operand
4926 on the right hand side. */
4927 if (rightstart != NULL && *rightstart == '#')
4928 {
4929 const char *temp;
4930
4931 cc = swap_mri_condition (cc);
4932 temp = leftstart;
4933 leftstart = rightstart;
4934 rightstart = temp;
4935 temp = leftstop;
4936 leftstop = rightstop;
4937 rightstop = temp;
4938 }
4939
4940 if (truelab == NULL)
4941 {
4942 cc = reverse_mri_condition (cc);
4943 truelab = falselab;
4944 }
4945
4946 if (leftstart != NULL)
4947 {
4948 buf = (char *) xmalloc (20
4949 + (leftstop - leftstart)
4950 + (rightstop - rightstart));
4951 s = buf;
4952 *s++ = 'c';
4953 *s++ = 'm';
4954 *s++ = 'p';
4955 if (qual != '\0')
4956 *s++ = qual;
4957 *s++ = ' ';
4958 memcpy (s, leftstart, leftstop - leftstart);
4959 s += leftstop - leftstart;
4960 *s++ = ',';
4961 memcpy (s, rightstart, rightstop - rightstart);
4962 s += rightstop - rightstart;
4963 *s = '\0';
4964 md_assemble (buf);
4965 free (buf);
4966 }
4967
4968 buf = (char *) xmalloc (20 + strlen (truelab));
4969 s = buf;
4970 *s++ = 'b';
4971 *s++ = cc >> 8;
4972 *s++ = cc & 0xff;
4973 if (extent != '\0')
4974 *s++ = extent;
4975 *s++ = ' ';
4976 strcpy (s, truelab);
4977 md_assemble (buf);
4978 free (buf);
4979 }
4980
4981 /* Parse an MRI structured control expression. This generates test
4982 and branch instructions. STOP is where the expression ends. It
4983 goes to TRUELAB if the condition is true, and to FALSELAB if the
4984 condition is false. Exactly one of TRUELAB and FALSELAB will be
4985 NULL, meaning to fall through. QUAL is the size qualifier for the
4986 expression. EXTENT is the size to use for the branch. */
4987
4988 static void
4989 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
4990 char *stop;
4991 int qual;
4992 const char *truelab;
4993 const char *falselab;
4994 int extent;
4995 {
4996 int c;
4997 int cc;
4998 const char *leftstart;
4999 const char *leftstop;
5000 const char *rightstart;
5001 const char *rightstop;
5002
5003 c = *stop;
5004 *stop = '\0';
5005
5006 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5007 &rightstart, &rightstop))
5008 {
5009 *stop = c;
5010 return;
5011 }
5012
5013 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5014 {
5015 const char *flab;
5016
5017 if (falselab != NULL)
5018 flab = falselab;
5019 else
5020 flab = mri_control_label ();
5021
5022 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5023 rightstop, (const char *) NULL, flab, extent);
5024
5025 input_line_pointer += 3;
5026 if (*input_line_pointer != '.'
5027 || input_line_pointer[1] == '\0')
5028 qual = '\0';
5029 else
5030 {
5031 qual = input_line_pointer[1];
5032 input_line_pointer += 2;
5033 }
5034
5035 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5036 &rightstart, &rightstop))
5037 {
5038 *stop = c;
5039 return;
5040 }
5041
5042 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5043 rightstop, truelab, falselab, extent);
5044
5045 if (falselab == NULL)
5046 colon (flab);
5047 }
5048 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5049 {
5050 const char *tlab;
5051
5052 if (truelab != NULL)
5053 tlab = truelab;
5054 else
5055 tlab = mri_control_label ();
5056
5057 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5058 rightstop, tlab, (const char *) NULL, extent);
5059
5060 input_line_pointer += 2;
5061 if (*input_line_pointer != '.'
5062 || input_line_pointer[1] == '\0')
5063 qual = '\0';
5064 else
5065 {
5066 qual = input_line_pointer[1];
5067 input_line_pointer += 2;
5068 }
5069
5070 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5071 &rightstart, &rightstop))
5072 {
5073 *stop = c;
5074 return;
5075 }
5076
5077 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5078 rightstop, truelab, falselab, extent);
5079
5080 if (truelab == NULL)
5081 colon (tlab);
5082 }
5083 else
5084 {
5085 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5086 rightstop, truelab, falselab, extent);
5087 }
5088
5089 *stop = c;
5090 if (input_line_pointer != stop)
5091 as_bad ("syntax error in structured control directive");
5092 }
5093
5094 /* Handle the MRI IF pseudo-op. This may be a structured control
5095 directive, or it may be a regular assembler conditional, depending
5096 on its operands. */
5097
5098 static void
5099 s_mri_if (qual)
5100 int qual;
5101 {
5102 char *s;
5103 int c;
5104 struct mri_control_info *n;
5105
5106 /* A structured control directive must end with THEN with an
5107 optional qualifier. */
5108 s = input_line_pointer;
5109 while (! is_end_of_line[(unsigned char) *s])
5110 ++s;
5111 --s;
5112 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5113 --s;
5114
5115 if (s - input_line_pointer > 1
5116 && s[-1] == '.')
5117 s -= 2;
5118
5119 if (s - input_line_pointer < 3
5120 || strncasecmp (s - 3, "THEN", 4) != 0)
5121 {
5122 if (qual != '\0')
5123 {
5124 as_bad ("missing then");
5125 ignore_rest_of_line ();
5126 return;
5127 }
5128
5129 /* It's a conditional. */
5130 s_if (O_ne);
5131 return;
5132 }
5133
5134 /* Since this might be a conditional if, this pseudo-op will be
5135 called even if we are supported to be ignoring input. Double
5136 check now. Clobber *input_line_pointer so that ignore_input
5137 thinks that this is not a special pseudo-op. */
5138 c = *input_line_pointer;
5139 *input_line_pointer = 0;
5140 if (ignore_input ())
5141 {
5142 *input_line_pointer = c;
5143 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5144 ++input_line_pointer;
5145 demand_empty_rest_of_line ();
5146 return;
5147 }
5148 *input_line_pointer = c;
5149
5150 n = push_mri_control (mri_if);
5151
5152 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5153 n->next, s[1] == '.' ? s[2] : '\0');
5154
5155 if (s[1] == '.')
5156 input_line_pointer = s + 3;
5157 else
5158 input_line_pointer = s + 1;
5159
5160 demand_empty_rest_of_line ();
5161 }
5162
5163 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5164 structured IF, associate the ELSE with the IF. Otherwise, assume
5165 it is a conditional else. */
5166
5167 static void
5168 s_mri_else (qual)
5169 int qual;
5170 {
5171 int c;
5172 char *buf;
5173 char q[2];
5174
5175 if (qual == '\0'
5176 && (mri_control_stack == NULL
5177 || mri_control_stack->type != mri_if
5178 || mri_control_stack->else_seen))
5179 {
5180 s_else (0);
5181 return;
5182 }
5183
5184 c = *input_line_pointer;
5185 *input_line_pointer = 0;
5186 if (ignore_input ())
5187 {
5188 *input_line_pointer = c;
5189 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5190 ++input_line_pointer;
5191 demand_empty_rest_of_line ();
5192 return;
5193 }
5194 *input_line_pointer = c;
5195
5196 if (mri_control_stack == NULL
5197 || mri_control_stack->type != mri_if
5198 || mri_control_stack->else_seen)
5199 {
5200 as_bad ("else without matching if");
5201 ignore_rest_of_line ();
5202 return;
5203 }
5204
5205 mri_control_stack->else_seen = 1;
5206
5207 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5208 q[0] = qual;
5209 q[1] = '\0';
5210 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5211 md_assemble (buf);
5212 free (buf);
5213
5214 colon (mri_control_stack->next);
5215
5216 demand_empty_rest_of_line ();
5217 }
5218
5219 /* Handle the MRI ENDI pseudo-op. */
5220
5221 static void
5222 s_mri_endi (ignore)
5223 int ignore;
5224 {
5225 if (mri_control_stack == NULL
5226 || mri_control_stack->type != mri_if)
5227 {
5228 as_bad ("endi without matching if");
5229 ignore_rest_of_line ();
5230 return;
5231 }
5232
5233 /* ignore_input will not return true for ENDI, so we don't need to
5234 worry about checking it again here. */
5235
5236 if (! mri_control_stack->else_seen)
5237 colon (mri_control_stack->next);
5238 colon (mri_control_stack->bottom);
5239
5240 pop_mri_control ();
5241
5242 demand_empty_rest_of_line ();
5243 }
5244
5245 /* Handle the MRI BREAK pseudo-op. */
5246
5247 static void
5248 s_mri_break (extent)
5249 int extent;
5250 {
5251 struct mri_control_info *n;
5252 char *buf;
5253 char ex[2];
5254
5255 n = mri_control_stack;
5256 while (n != NULL
5257 && n->type != mri_for
5258 && n->type != mri_repeat
5259 && n->type != mri_while)
5260 n = n->outer;
5261 if (n == NULL)
5262 {
5263 as_bad ("break outside of structured loop");
5264 ignore_rest_of_line ();
5265 return;
5266 }
5267
5268 buf = (char *) xmalloc (20 + strlen (n->bottom));
5269 ex[0] = extent;
5270 ex[1] = '\0';
5271 sprintf (buf, "bra%s %s", ex, n->bottom);
5272 md_assemble (buf);
5273 free (buf);
5274
5275 demand_empty_rest_of_line ();
5276 }
5277
5278 /* Handle the MRI NEXT pseudo-op. */
5279
5280 static void
5281 s_mri_next (extent)
5282 int extent;
5283 {
5284 struct mri_control_info *n;
5285 char *buf;
5286 char ex[2];
5287
5288 n = mri_control_stack;
5289 while (n != NULL
5290 && n->type != mri_for
5291 && n->type != mri_repeat
5292 && n->type != mri_while)
5293 n = n->outer;
5294 if (n == NULL)
5295 {
5296 as_bad ("next outside of structured loop");
5297 ignore_rest_of_line ();
5298 return;
5299 }
5300
5301 buf = (char *) xmalloc (20 + strlen (n->next));
5302 ex[0] = extent;
5303 ex[1] = '\0';
5304 sprintf (buf, "bra%s %s", ex, n->next);
5305 md_assemble (buf);
5306 free (buf);
5307
5308 demand_empty_rest_of_line ();
5309 }
5310
5311 /* Handle the MRI FOR pseudo-op. */
5312
5313 static void
5314 s_mri_for (qual)
5315 int qual;
5316 {
5317 const char *varstart, *varstop;
5318 const char *initstart, *initstop;
5319 const char *endstart, *endstop;
5320 const char *bystart, *bystop;
5321 int up;
5322 int by;
5323 int extent;
5324 struct mri_control_info *n;
5325 char *buf;
5326 char *s;
5327 char ex[2];
5328
5329 /* The syntax is
5330 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5331 */
5332
5333 SKIP_WHITESPACE ();
5334 varstart = input_line_pointer;
5335
5336 /* Look for the '='. */
5337 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5338 && *input_line_pointer != '=')
5339 ++input_line_pointer;
5340 if (*input_line_pointer != '=')
5341 {
5342 as_bad ("missing =");
5343 ignore_rest_of_line ();
5344 return;
5345 }
5346
5347 varstop = input_line_pointer;
5348 if (varstop > varstart
5349 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5350 --varstop;
5351
5352 ++input_line_pointer;
5353
5354 initstart = input_line_pointer;
5355
5356 /* Look for TO or DOWNTO. */
5357 up = 1;
5358 initstop = NULL;
5359 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5360 {
5361 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5362 && ! is_part_of_name (input_line_pointer[2]))
5363 {
5364 initstop = input_line_pointer;
5365 input_line_pointer += 2;
5366 break;
5367 }
5368 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5369 && ! is_part_of_name (input_line_pointer[6]))
5370 {
5371 initstop = input_line_pointer;
5372 up = 0;
5373 input_line_pointer += 6;
5374 break;
5375 }
5376 ++input_line_pointer;
5377 }
5378 if (initstop == NULL)
5379 {
5380 as_bad ("missing to or downto");
5381 ignore_rest_of_line ();
5382 return;
5383 }
5384 if (initstop > initstart
5385 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5386 --initstop;
5387
5388 SKIP_WHITESPACE ();
5389 endstart = input_line_pointer;
5390
5391 /* Look for BY or DO. */
5392 by = 0;
5393 endstop = NULL;
5394 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5395 {
5396 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5397 && ! is_part_of_name (input_line_pointer[2]))
5398 {
5399 endstop = input_line_pointer;
5400 by = 1;
5401 input_line_pointer += 2;
5402 break;
5403 }
5404 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5405 && (input_line_pointer[2] == '.'
5406 || ! is_part_of_name (input_line_pointer[2])))
5407 {
5408 endstop = input_line_pointer;
5409 input_line_pointer += 2;
5410 break;
5411 }
5412 ++input_line_pointer;
5413 }
5414 if (endstop == NULL)
5415 {
5416 as_bad ("missing do");
5417 ignore_rest_of_line ();
5418 return;
5419 }
5420 if (endstop > endstart
5421 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5422 --endstop;
5423
5424 if (! by)
5425 {
5426 bystart = "#1";
5427 bystop = bystart + 2;
5428 }
5429 else
5430 {
5431 SKIP_WHITESPACE ();
5432 bystart = input_line_pointer;
5433
5434 /* Look for DO. */
5435 bystop = NULL;
5436 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5437 {
5438 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5439 && (input_line_pointer[2] == '.'
5440 || ! is_part_of_name (input_line_pointer[2])))
5441 {
5442 bystop = input_line_pointer;
5443 input_line_pointer += 2;
5444 break;
5445 }
5446 ++input_line_pointer;
5447 }
5448 if (bystop == NULL)
5449 {
5450 as_bad ("missing do");
5451 ignore_rest_of_line ();
5452 return;
5453 }
5454 if (bystop > bystart
5455 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5456 --bystop;
5457 }
5458
5459 if (*input_line_pointer != '.')
5460 extent = '\0';
5461 else
5462 {
5463 extent = input_line_pointer[1];
5464 input_line_pointer += 2;
5465 }
5466
5467 /* We have fully parsed the FOR operands. Now build the loop. */
5468
5469 n = push_mri_control (mri_for);
5470
5471 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5472
5473 /* move init,var */
5474 s = buf;
5475 *s++ = 'm';
5476 *s++ = 'o';
5477 *s++ = 'v';
5478 *s++ = 'e';
5479 if (qual != '\0')
5480 *s++ = qual;
5481 *s++ = ' ';
5482 memcpy (s, initstart, initstop - initstart);
5483 s += initstop - initstart;
5484 *s++ = ',';
5485 memcpy (s, varstart, varstop - varstart);
5486 s += varstop - varstart;
5487 *s = '\0';
5488 md_assemble (buf);
5489
5490 colon (n->top);
5491
5492 /* cmp end,var */
5493 s = buf;
5494 *s++ = 'c';
5495 *s++ = 'm';
5496 *s++ = 'p';
5497 if (qual != '\0')
5498 *s++ = qual;
5499 *s++ = ' ';
5500 memcpy (s, endstart, endstop - endstart);
5501 s += endstop - endstart;
5502 *s++ = ',';
5503 memcpy (s, varstart, varstop - varstart);
5504 s += varstop - varstart;
5505 *s = '\0';
5506 md_assemble (buf);
5507
5508 /* bcc bottom */
5509 ex[0] = extent;
5510 ex[1] = '\0';
5511 if (up)
5512 sprintf (buf, "blt%s %s", ex, n->bottom);
5513 else
5514 sprintf (buf, "bgt%s %s", ex, n->bottom);
5515 md_assemble (buf);
5516
5517 /* Put together the add or sub instruction used by ENDF. */
5518 s = buf;
5519 if (up)
5520 strcpy (s, "add");
5521 else
5522 strcpy (s, "sub");
5523 s += 3;
5524 if (qual != '\0')
5525 *s++ = qual;
5526 *s++ = ' ';
5527 memcpy (s, bystart, bystop - bystart);
5528 s += bystop - bystart;
5529 *s++ = ',';
5530 memcpy (s, varstart, varstop - varstart);
5531 s += varstop - varstart;
5532 *s = '\0';
5533 n->incr = buf;
5534
5535 demand_empty_rest_of_line ();
5536 }
5537
5538 /* Handle the MRI ENDF pseudo-op. */
5539
5540 static void
5541 s_mri_endf (ignore)
5542 int ignore;
5543 {
5544 if (mri_control_stack == NULL
5545 || mri_control_stack->type != mri_for)
5546 {
5547 as_bad ("endf without for");
5548 ignore_rest_of_line ();
5549 return;
5550 }
5551
5552 colon (mri_control_stack->next);
5553
5554 md_assemble (mri_control_stack->incr);
5555
5556 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5557 md_assemble (mri_control_stack->incr);
5558
5559 free (mri_control_stack->incr);
5560
5561 colon (mri_control_stack->bottom);
5562
5563 pop_mri_control ();
5564
5565 demand_empty_rest_of_line ();
5566 }
5567
5568 /* Handle the MRI REPEAT pseudo-op. */
5569
5570 static void
5571 s_mri_repeat (ignore)
5572 int ignore;
5573 {
5574 struct mri_control_info *n;
5575
5576 n = push_mri_control (mri_repeat);
5577 colon (n->top);
5578 demand_empty_rest_of_line ();
5579 }
5580
5581 /* Handle the MRI UNTIL pseudo-op. */
5582
5583 static void
5584 s_mri_until (qual)
5585 int qual;
5586 {
5587 char *s;
5588
5589 if (mri_control_stack == NULL
5590 || mri_control_stack->type != mri_repeat)
5591 {
5592 as_bad ("until without repeat");
5593 ignore_rest_of_line ();
5594 return;
5595 }
5596
5597 colon (mri_control_stack->next);
5598
5599 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
5600 ;
5601
5602 parse_mri_control_expression (s, qual, (const char *) NULL,
5603 mri_control_stack->top, '\0');
5604
5605 colon (mri_control_stack->bottom);
5606
5607 input_line_pointer = s;
5608
5609 demand_empty_rest_of_line ();
5610 }
5611
5612 /* Handle the MRI WHILE pseudo-op. */
5613
5614 static void
5615 s_mri_while (qual)
5616 int qual;
5617 {
5618 char *s;
5619
5620 struct mri_control_info *n;
5621
5622 s = input_line_pointer;
5623 while (! is_end_of_line[(unsigned char) *s])
5624 s++;
5625 --s;
5626 while (*s == ' ' || *s == '\t')
5627 --s;
5628 if (s - input_line_pointer > 1
5629 && s[-1] == '.')
5630 s -= 2;
5631 if (s - input_line_pointer < 2
5632 || strncasecmp (s - 1, "DO", 2) != 0)
5633 {
5634 as_bad ("missing do");
5635 ignore_rest_of_line ();
5636 return;
5637 }
5638
5639 n = push_mri_control (mri_while);
5640
5641 colon (n->next);
5642
5643 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
5644 s[1] == '.' ? s[2] : '\0');
5645
5646 input_line_pointer = s + 1;
5647 if (*input_line_pointer == '.')
5648 input_line_pointer += 2;
5649
5650 demand_empty_rest_of_line ();
5651 }
5652
5653 /* Handle the MRI ENDW pseudo-op. */
5654
5655 static void
5656 s_mri_endw (ignore)
5657 int ignore;
5658 {
5659 char *buf;
5660
5661 if (mri_control_stack == NULL
5662 || mri_control_stack->type != mri_while)
5663 {
5664 as_bad ("endw without while");
5665 ignore_rest_of_line ();
5666 return;
5667 }
5668
5669 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
5670 sprintf (buf, "bra %s", mri_control_stack->next);
5671 md_assemble (buf);
5672 free (buf);
5673
5674 colon (mri_control_stack->bottom);
5675
5676 pop_mri_control ();
5677
5678 demand_empty_rest_of_line ();
5679 }
5680 \f
5681 /*
5682 * md_parse_option
5683 * Invocation line includes a switch not recognized by the base assembler.
5684 * See if it's a processor-specific option. These are:
5685 *
5686 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
5687 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
5688 * Select the architecture. Instructions or features not
5689 * supported by the selected architecture cause fatal
5690 * errors. More than one may be specified. The default is
5691 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
5692 * for -m68000, and -m68882 is a synonym for -m68881.
5693 * -[A]m[c]no-68851, -[A]m[c]no-68881
5694 * Don't accept 688?1 instructions. (The "c" is kind of silly,
5695 * so don't use or document it, but that's the way the parsing
5696 * works).
5697 *
5698 * -pic Indicates PIC.
5699 * -k Indicates PIC. (Sun 3 only.)
5700 *
5701 */
5702
5703 #ifdef OBJ_ELF
5704 CONST char *md_shortopts = "lSA:m:kQ:V";
5705 #else
5706 CONST char *md_shortopts = "lSA:m:k";
5707 #endif
5708
5709 struct option md_longopts[] = {
5710 #define OPTION_PIC (OPTION_MD_BASE)
5711 {"pic", no_argument, NULL, OPTION_PIC},
5712 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
5713 {"register-prefix-optional", no_argument, NULL,
5714 OPTION_REGISTER_PREFIX_OPTIONAL},
5715 {NULL, no_argument, NULL, 0}
5716 };
5717 size_t md_longopts_size = sizeof(md_longopts);
5718
5719 int
5720 md_parse_option (c, arg)
5721 int c;
5722 char *arg;
5723 {
5724 switch (c)
5725 {
5726 case 'l': /* -l means keep external to 2 bit offset
5727 rather than 16 bit one */
5728 flag_short_refs = 1;
5729 break;
5730
5731 case 'S': /* -S means that jbsr's always turn into
5732 jsr's. */
5733 flag_long_jumps = 1;
5734 break;
5735
5736 case 'A':
5737 if (*arg == 'm')
5738 arg++;
5739 /* intentional fall-through */
5740 case 'm':
5741
5742 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
5743 {
5744 int i;
5745 unsigned long arch;
5746 const char *oarg = arg;
5747
5748 arg += 3;
5749 if (*arg == 'm')
5750 {
5751 arg++;
5752 if (arg[0] == 'c' && arg[1] == '6')
5753 arg++;
5754 }
5755 for (i = 0; i < n_archs; i++)
5756 if (!strcmp (arg, archs[i].name))
5757 break;
5758 if (i == n_archs)
5759 {
5760 unknown:
5761 as_bad ("unrecognized option `%s'", oarg);
5762 return 0;
5763 }
5764 arch = archs[i].arch;
5765 if (arch == m68881)
5766 no_68881 = 1;
5767 else if (arch == m68851)
5768 no_68851 = 1;
5769 else
5770 goto unknown;
5771 }
5772 else
5773 {
5774 int i;
5775
5776 if (arg[0] == 'c' && arg[1] == '6')
5777 arg++;
5778
5779 for (i = 0; i < n_archs; i++)
5780 if (!strcmp (arg, archs[i].name))
5781 {
5782 unsigned long arch = archs[i].arch;
5783 if (cpu_of_arch (arch))
5784 /* It's a cpu spec. */
5785 {
5786 current_architecture &= ~m68000up;
5787 current_architecture |= arch;
5788 }
5789 else if (arch == m68881)
5790 {
5791 current_architecture |= m68881;
5792 no_68881 = 0;
5793 }
5794 else if (arch == m68851)
5795 {
5796 current_architecture |= m68851;
5797 no_68851 = 0;
5798 }
5799 else
5800 /* ??? */
5801 abort ();
5802 break;
5803 }
5804 if (i == n_archs)
5805 {
5806 as_bad ("unrecognized architecture specification `%s'", arg);
5807 return 0;
5808 }
5809 }
5810 break;
5811
5812 case OPTION_PIC:
5813 case 'k':
5814 flag_want_pic = 1;
5815 break; /* -pic, Position Independent Code */
5816
5817 case OPTION_REGISTER_PREFIX_OPTIONAL:
5818 flag_reg_prefix_optional = 1;
5819 break;
5820
5821 case 'Q':
5822 case 'V':
5823 break;
5824
5825 default:
5826 return 0;
5827 }
5828
5829 return 1;
5830 }
5831
5832 void
5833 md_show_usage (stream)
5834 FILE *stream;
5835 {
5836 fprintf(stream, "\
5837 680X0 options:\n\
5838 -l use 1 word for refs to undefined symbols [default 2]\n\
5839 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
5840 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
5841 | -mcpu32\n\
5842 specify variant of 680X0 architecture [default 68020]\n\
5843 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
5844 target has/lacks floating-point coprocessor\n\
5845 [default yes for 68020, 68030, and cpu32]\n\
5846 -m68851 | -mno-68851\n\
5847 target has/lacks memory-management unit coprocessor\n\
5848 [default yes for 68020 and up]\n\
5849 -pic, -k generate position independent code\n\
5850 -S turn jbsr into jsr\n\
5851 --register-prefix-optional\n\
5852 recognize register names without prefix character\n");
5853 }
5854 \f
5855 #ifdef TEST2
5856
5857 /* TEST2: Test md_assemble() */
5858 /* Warning, this routine probably doesn't work anymore */
5859
5860 main ()
5861 {
5862 struct m68k_it the_ins;
5863 char buf[120];
5864 char *cp;
5865 int n;
5866
5867 m68k_ip_begin ();
5868 for (;;)
5869 {
5870 if (!gets (buf) || !*buf)
5871 break;
5872 if (buf[0] == '|' || buf[1] == '.')
5873 continue;
5874 for (cp = buf; *cp; cp++)
5875 if (*cp == '\t')
5876 *cp = ' ';
5877 if (is_label (buf))
5878 continue;
5879 memset (&the_ins, '\0', sizeof (the_ins));
5880 m68k_ip (&the_ins, buf);
5881 if (the_ins.error)
5882 {
5883 printf ("Error %s in %s\n", the_ins.error, buf);
5884 }
5885 else
5886 {
5887 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
5888 for (n = 0; n < the_ins.numo; n++)
5889 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
5890 printf (" ");
5891 print_the_insn (&the_ins.opcode[0], stdout);
5892 (void) putchar ('\n');
5893 }
5894 for (n = 0; n < strlen (the_ins.args) / 2; n++)
5895 {
5896 if (the_ins.operands[n].error)
5897 {
5898 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
5899 continue;
5900 }
5901 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
5902 if (the_ins.operands[n].b_const)
5903 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
5904 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
5905 if (the_ins.operands[n].b_iadd)
5906 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
5907 (void) putchar ('\n');
5908 }
5909 }
5910 m68k_ip_end ();
5911 return 0;
5912 }
5913
5914 is_label (str)
5915 char *str;
5916 {
5917 while (*str == ' ')
5918 str++;
5919 while (*str && *str != ' ')
5920 str++;
5921 if (str[-1] == ':' || str[1] == '=')
5922 return 1;
5923 return 0;
5924 }
5925
5926 #endif
5927
5928 /* Possible states for relaxation:
5929
5930 0 0 branch offset byte (bra, etc)
5931 0 1 word
5932 0 2 long
5933
5934 1 0 indexed offsets byte a0@(32,d4:w:1) etc
5935 1 1 word
5936 1 2 long
5937
5938 2 0 two-offset index word-word a0@(32,d4)@(45) etc
5939 2 1 word-long
5940 2 2 long-word
5941 2 3 long-long
5942
5943 */
5944
5945 /* We have no need to default values of symbols. */
5946
5947 /* ARGSUSED */
5948 symbolS *
5949 md_undefined_symbol (name)
5950 char *name;
5951 {
5952 return 0;
5953 }
5954
5955 /* Round up a section size to the appropriate boundary. */
5956 valueT
5957 md_section_align (segment, size)
5958 segT segment;
5959 valueT size;
5960 {
5961 return size; /* Byte alignment is fine */
5962 }
5963
5964 /* Exactly what point is a PC-relative offset relative TO?
5965 On the 68k, it is relative to the address of the first extension
5966 word. The difference between the addresses of the offset and the
5967 first extension word is stored in fx_pcrel_adjust. */
5968 long
5969 md_pcrel_from (fixP)
5970 fixS *fixP;
5971 {
5972 int adjust;
5973
5974 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
5975 -1 as 64. */
5976 adjust = fixP->fx_pcrel_adjust;
5977 if (adjust == 64)
5978 adjust = -1;
5979 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
5980 }
5981
5982 #ifndef BFD_ASSEMBLER
5983 /*ARGSUSED*/
5984 void
5985 tc_coff_symbol_emit_hook (ignore)
5986 symbolS *ignore;
5987 {
5988 }
5989
5990 int
5991 tc_coff_sizemachdep (frag)
5992 fragS *frag;
5993 {
5994 switch (frag->fr_subtype & 0x3)
5995 {
5996 case BYTE:
5997 return 1;
5998 case SHORT:
5999 return 2;
6000 case LONG:
6001 return 4;
6002 default:
6003 abort ();
6004 return 0;
6005 }
6006 }
6007 #endif
6008
6009 /* end of tc-m68k.c */