projects / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
* config/tc-m68k.c (tc_gen_reloc): Change the code appropriately
[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #include "as.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
28
29 /* This string holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful. The macro
31 tc_comment_chars points to this. We use this, rather than the
32 usual comment_chars, so that the --bitwise-or option will work. */
33 #if (defined (OBJ_ELF) && ! defined (TE_PSOS) && ! defined (TE_LINUX)) || defined (TE_DELTA)
34 const char *m68k_comment_chars = "|#";
35 #else
36 const char *m68k_comment_chars = "|";
37 #endif
38
39 /* This array holds the chars that only start a comment at the beginning of
40 a line. If the line seems to have the form '# 123 filename'
41 .line and .file directives will appear in the pre-processed output */
42 /* Note that input_file.c hand checks for '#' at the beginning of the
43 first line of the input file. This is because the compiler outputs
44 #NO_APP at the beginning of its output. */
45 /* Also note that comments like this one will always work. */
46 const char line_comment_chars[] = "#";
47
48 const char line_separator_chars[] = "";
49
50 /* Chars that can be used to separate mant from exp in floating point nums */
51 CONST char EXP_CHARS[] = "eE";
52
53 /* Chars that mean this number is a floating point constant, as
54 in "0f12.456" or "0d1.2345e12". */
55
56 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
57
58 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
59 changed in read.c . Ideally it shouldn't have to know about it at all,
60 but nothing is ideal around here. */
61
62 const int md_reloc_size = 8; /* Size of relocation record */
63
64 /* Are we trying to generate PIC code? If so, absolute references
65 ought to be made into linkage table references or pc-relative
66 references. Not implemented. For ELF there are other means
67 to denote pic relocations. */
68 int flag_want_pic;
69
70 static int flag_short_refs; /* -l option */
71 static int flag_long_jumps; /* -S option */
72
73 #ifdef REGISTER_PREFIX_OPTIONAL
74 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
75 #else
76 int flag_reg_prefix_optional;
77 #endif
78
79 /* Whether --register-prefix-optional was used on the command line. */
80 static int reg_prefix_optional_seen;
81
82 /* The floating point coprocessor to use by default. */
83 static enum m68k_register m68k_float_copnum = COP1;
84
85 /* If this is non-zero, then references to number(%pc) will be taken
86 to refer to number, rather than to %pc + number. */
87 static int m68k_abspcadd;
88
89 /* If this is non-zero, then the quick forms of the move, add, and sub
90 instructions are used when possible. */
91 static int m68k_quick = 1;
92
93 /* If this is non-zero, then if the size is not specified for a base
94 or outer displacement, the assembler assumes that the size should
95 be 32 bits. */
96 static int m68k_rel32 = 1;
97
98 /* Its an arbitrary name: This means I don't approve of it */
99 /* See flames below */
100 static struct obstack robyn;
101
102 #define TAB(x,y) (((x)<<2)+(y))
103 #define TABTYPE(xy) ((xy) >> 2)
104 #define BYTE 0
105 #define SHORT 1
106 #define LONG 2
107 #define SZ_UNDEF 3
108 #undef BRANCH
109 /* Case `g' except when BCC68000 is applicable. */
110 #define ABRANCH 1
111 /* Coprocessor branches. */
112 #define FBRANCH 2
113 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
114 supported on all cpus. Widens to 32-bit absolute. */
115 #define PCREL 3
116 /* For inserting an extra jmp instruction with long offset on 68000,
117 for expanding conditional branches. (Not bsr or bra.) Since the
118 68000 doesn't support 32-bit displacements for conditional
119 branches, we fake it by reversing the condition and branching
120 around a jmp with an absolute long operand. */
121 #define BCC68000 4
122 /* For the DBcc "instructions". If the displacement requires 32 bits,
123 the branch-around-a-jump game is played here too. */
124 #define DBCC 5
125 /* Not currently used? */
126 #define PCLEA 6
127 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
128 in 16 or 8 bits. */
129 #define PCINDEX 7
130
131 struct m68k_incant
132 {
133 const char *m_operands;
134 unsigned long m_opcode;
135 short m_opnum;
136 short m_codenum;
137 int m_arch;
138 struct m68k_incant *m_next;
139 };
140
141 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
142 #define gettwo(x) (((x)->m_opcode)&0xffff)
143
144 static const enum m68k_register m68000_control_regs[] = { 0 };
145 static const enum m68k_register m68010_control_regs[] = {
146 SFC, DFC, USP, VBR,
147 0
148 };
149 static const enum m68k_register m68020_control_regs[] = {
150 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
151 0
152 };
153 static const enum m68k_register m68040_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
155 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
156 0
157 };
158 static const enum m68k_register m68060_control_regs[] = {
159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
160 USP, VBR, URP, SRP, PCR,
161 0
162 };
163 static const enum m68k_register mcf5200_control_regs[] = {
164 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
165 RAMBAR0, RAMBAR1, MBAR,
166 0
167 };
168 #define cpu32_control_regs m68010_control_regs
169
170 static const enum m68k_register *control_regs;
171
172 /* internal form of a 68020 instruction */
173 struct m68k_it
174 {
175 const char *error;
176 const char *args; /* list of opcode info */
177 int numargs;
178
179 int numo; /* Number of shorts in opcode */
180 short opcode[11];
181
182 struct m68k_op operands[6];
183
184 int nexp; /* number of exprs in use */
185 struct m68k_exp exprs[4];
186
187 int nfrag; /* Number of frags we have to produce */
188 struct
189 {
190 int fragoff; /* Where in the current opcode the frag ends */
191 symbolS *fadd;
192 long foff;
193 int fragty;
194 }
195 fragb[4];
196
197 int nrel; /* Num of reloc strucs in use */
198 struct
199 {
200 int n;
201 expressionS exp;
202 char wid;
203 char pcrel;
204 /* In a pc relative address the difference between the address
205 of the offset and the address that the offset is relative
206 to. This depends on the addressing mode. Basically this
207 is the value to put in the offset field to address the
208 first byte of the offset, without regarding the special
209 significance of some values (in the branch instruction, for
210 example). */
211 int pcrel_fix;
212 #ifdef OBJ_ELF
213 /* Whether this expression needs special pic relocation, and if
214 so, which. */
215 enum pic_relocation pic_reloc;
216 #endif
217 }
218 reloc[5]; /* Five is enough??? */
219 };
220
221 #define cpu_of_arch(x) ((x) & (m68000up|mcf5200))
222 #define float_of_arch(x) ((x) & mfloat)
223 #define mmu_of_arch(x) ((x) & mmmu)
224
225 static struct m68k_it the_ins; /* the instruction being assembled */
226
227 #define op(ex) ((ex)->exp.X_op)
228 #define adds(ex) ((ex)->exp.X_add_symbol)
229 #define subs(ex) ((ex)->exp.X_op_symbol)
230 #define offs(ex) ((ex)->exp.X_add_number)
231
232 /* Macros for adding things to the m68k_it struct */
233
234 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
235
236 /* Like addword, but goes BEFORE general operands */
237 static void
238 insop (w, opcode)
239 int w;
240 struct m68k_incant *opcode;
241 {
242 int z;
243 for(z=the_ins.numo;z>opcode->m_codenum;--z)
244 the_ins.opcode[z]=the_ins.opcode[z-1];
245 for(z=0;z<the_ins.nrel;z++)
246 the_ins.reloc[z].n+=2;
247 for (z = 0; z < the_ins.nfrag; z++)
248 the_ins.fragb[z].fragoff++;
249 the_ins.opcode[opcode->m_codenum]=w;
250 the_ins.numo++;
251 }
252
253 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
254 Blecch. */
255 static void
256 add_fix (width, exp, pc_rel, pc_fix)
257 char width;
258 struct m68k_exp *exp;
259 int pc_rel;
260 int pc_fix;
261 {
262 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
263 ? (the_ins.numo*2-1)
264 : (((width)=='b')
265 ? (the_ins.numo*2+1)
266 : (the_ins.numo*2)));
267 the_ins.reloc[the_ins.nrel].exp = exp->exp;
268 the_ins.reloc[the_ins.nrel].wid = width;
269 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
270 #ifdef OBJ_ELF
271 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
272 #endif
273 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
274 }
275
276 /* Cause an extra frag to be generated here, inserting up to 10 bytes
277 (that value is chosen in the frag_var call in md_assemble). TYPE
278 is the subtype of the frag to be generated; its primary type is
279 rs_machine_dependent.
280
281 The TYPE parameter is also used by md_convert_frag_1 and
282 md_estimate_size_before_relax. The appropriate type of fixup will
283 be emitted by md_convert_frag_1.
284
285 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
286 static void
287 add_frag(add,off,type)
288 symbolS *add;
289 long off;
290 int type;
291 {
292 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
293 the_ins.fragb[the_ins.nfrag].fadd=add;
294 the_ins.fragb[the_ins.nfrag].foff=off;
295 the_ins.fragb[the_ins.nfrag++].fragty=type;
296 }
297
298 #define isvar(ex) \
299 (op (ex) != O_constant && op (ex) != O_big)
300
301 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
302 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
303 static int reverse_16_bits PARAMS ((int in));
304 static int reverse_8_bits PARAMS ((int in));
305 static void install_gen_operand PARAMS ((int mode, int val));
306 static void install_operand PARAMS ((int mode, int val));
307 static void s_bss PARAMS ((int));
308 static void s_data1 PARAMS ((int));
309 static void s_data2 PARAMS ((int));
310 static void s_even PARAMS ((int));
311 static void s_proc PARAMS ((int));
312 static void mri_chip PARAMS ((void));
313 static void s_chip PARAMS ((int));
314 static void s_fopt PARAMS ((int));
315 static void s_opt PARAMS ((int));
316 static void s_reg PARAMS ((int));
317 static void s_restore PARAMS ((int));
318 static void s_save PARAMS ((int));
319 static void s_mri_if PARAMS ((int));
320 static void s_mri_else PARAMS ((int));
321 static void s_mri_endi PARAMS ((int));
322 static void s_mri_break PARAMS ((int));
323 static void s_mri_next PARAMS ((int));
324 static void s_mri_for PARAMS ((int));
325 static void s_mri_endf PARAMS ((int));
326 static void s_mri_repeat PARAMS ((int));
327 static void s_mri_until PARAMS ((int));
328 static void s_mri_while PARAMS ((int));
329 static void s_mri_endw PARAMS ((int));
330
331 static int current_architecture;
332
333 struct m68k_cpu {
334 unsigned long arch;
335 const char *name;
336 int alias;
337 };
338
339 static const struct m68k_cpu archs[] = {
340 { m68000, "68000", 0 },
341 { m68010, "68010", 0 },
342 { m68020, "68020", 0 },
343 { m68030, "68030", 0 },
344 { m68040, "68040", 0 },
345 { m68060, "68060", 0 },
346 { cpu32, "cpu32", 0 },
347 { m68881, "68881", 0 },
348 { m68851, "68851", 0 },
349 { mcf5200, "5200", 0 },
350 /* Aliases (effectively, so far as gas is concerned) for the above
351 cpus. */
352 { m68020, "68k", 1 },
353 { m68000, "68302", 1 },
354 { m68000, "68008", 1 },
355 { m68000, "68ec000", 1 },
356 { m68000, "68hc000", 1 },
357 { m68000, "68hc001", 1 },
358 { m68020, "68ec020", 1 },
359 { m68030, "68ec030", 1 },
360 { m68040, "68ec040", 1 },
361 { m68060, "68ec060", 1 },
362 { cpu32, "68330", 1 },
363 { cpu32, "68331", 1 },
364 { cpu32, "68332", 1 },
365 { cpu32, "68333", 1 },
366 { cpu32, "68340", 1 },
367 { cpu32, "68360", 1 },
368 { m68881, "68882", 1 },
369 };
370
371 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
372
373 /* BCC68000 is for patching in an extra jmp instruction for long offsets
374 on the 68000. The 68000 doesn't support long branches with branchs */
375
376 /* This table desribes how you change sizes for the various types of variable
377 size expressions. This version only supports two kinds. */
378
379 /* Note that calls to frag_var need to specify the maximum expansion
380 needed; this is currently 10 bytes for DBCC. */
381
382 /* The fields are:
383 How far Forward this mode will reach:
384 How far Backward this mode will reach:
385 How many bytes this mode will add to the size of the frag
386 Which mode to go to if the offset won't fit in this one
387 */
388 relax_typeS md_relax_table[] =
389 {
390 {1, 1, 0, 0}, /* First entries aren't used */
391 {1, 1, 0, 0}, /* For no good reason except */
392 {1, 1, 0, 0}, /* that the VAX doesn't either */
393 {1, 1, 0, 0},
394
395 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
396 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
397 {0, 0, 4, 0},
398 {1, 1, 0, 0},
399
400 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
401 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
402 {0, 0, 4, 0},
403 {1, 1, 0, 0},
404
405 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
406 {(32767), (-32768), 2, TAB (PCREL, LONG)},
407 {0, 0, 4, 0},
408 {1, 1, 0, 0},
409
410 {(127), (-128), 0, TAB (BCC68000, SHORT)},
411 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
412 {0, 0, 6, 0}, /* jmp long space */
413 {1, 1, 0, 0},
414
415 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
416 {(32767), (-32768), 2, TAB (DBCC, LONG)},
417 {0, 0, 10, 0}, /* bra/jmp long space */
418 {1, 1, 0, 0},
419
420 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
421 {32767, -32768, 2, TAB (PCLEA, LONG)},
422 {0, 0, 6, 0},
423 {1, 1, 0, 0},
424
425 /* For, e.g., jmp pcrel indexed. */
426 {125, -130, 0, TAB (PCINDEX, SHORT)},
427 {32765, -32770, 2, TAB (PCINDEX, LONG)},
428 {0, 0, 4, 0},
429 {1, 1, 0, 0},
430 };
431
432 /* These are the machine dependent pseudo-ops. These are included so
433 the assembler can work on the output from the SUN C compiler, which
434 generates these.
435 */
436
437 /* This table describes all the machine specific pseudo-ops the assembler
438 has to support. The fields are:
439 pseudo-op name without dot
440 function to call to execute this pseudo-op
441 Integer arg to pass to the function
442 */
443 const pseudo_typeS md_pseudo_table[] =
444 {
445 {"data1", s_data1, 0},
446 {"data2", s_data2, 0},
447 {"bss", s_bss, 0},
448 {"even", s_even, 0},
449 {"skip", s_space, 0},
450 {"proc", s_proc, 0},
451 #if defined (TE_SUN3) || defined (OBJ_ELF)
452 {"align", s_align_bytes, 0},
453 #endif
454 #ifdef OBJ_ELF
455 {"swbeg", s_ignore, 0},
456 #endif
457 {"extend", float_cons, 'x'},
458 {"ldouble", float_cons, 'x'},
459
460 /* The following pseudo-ops are supported for MRI compatibility. */
461 {"chip", s_chip, 0},
462 {"comline", s_space, 1},
463 {"fopt", s_fopt, 0},
464 {"mask2", s_ignore, 0},
465 {"opt", s_opt, 0},
466 {"reg", s_reg, 0},
467 {"restore", s_restore, 0},
468 {"save", s_save, 0},
469
470 {"if", s_mri_if, 0},
471 {"if.b", s_mri_if, 'b'},
472 {"if.w", s_mri_if, 'w'},
473 {"if.l", s_mri_if, 'l'},
474 {"else", s_mri_else, 0},
475 {"else.s", s_mri_else, 's'},
476 {"else.l", s_mri_else, 'l'},
477 {"endi", s_mri_endi, 0},
478 {"break", s_mri_break, 0},
479 {"break.s", s_mri_break, 's'},
480 {"break.l", s_mri_break, 'l'},
481 {"next", s_mri_next, 0},
482 {"next.s", s_mri_next, 's'},
483 {"next.l", s_mri_next, 'l'},
484 {"for", s_mri_for, 0},
485 {"for.b", s_mri_for, 'b'},
486 {"for.w", s_mri_for, 'w'},
487 {"for.l", s_mri_for, 'l'},
488 {"endf", s_mri_endf, 0},
489 {"repeat", s_mri_repeat, 0},
490 {"until", s_mri_until, 0},
491 {"until.b", s_mri_until, 'b'},
492 {"until.w", s_mri_until, 'w'},
493 {"until.l", s_mri_until, 'l'},
494 {"while", s_mri_while, 0},
495 {"while.b", s_mri_while, 'b'},
496 {"while.w", s_mri_while, 'w'},
497 {"while.l", s_mri_while, 'l'},
498 {"endw", s_mri_endw, 0},
499
500 {0, 0, 0}
501 };
502
503
504 /* The mote pseudo ops are put into the opcode table, since they
505 don't start with a . they look like opcodes to gas.
506 */
507 extern void obj_coff_section ();
508
509 CONST pseudo_typeS mote_pseudo_table[] =
510 {
511
512 {"dcl", cons, 4},
513 {"dc", cons, 2},
514 {"dcw", cons, 2},
515 {"dcb", cons, 1},
516
517 {"dsl", s_space, 4},
518 {"ds", s_space, 2},
519 {"dsw", s_space, 2},
520 {"dsb", s_space, 1},
521
522 {"xdef", s_globl, 0},
523 #ifdef OBJ_ELF
524 {"align", s_align_bytes, 0},
525 #else
526 {"align", s_align_ptwo, 0},
527 #endif
528 #ifdef M68KCOFF
529 {"sect", obj_coff_section, 0},
530 {"section", obj_coff_section, 0},
531 #endif
532 {0, 0, 0}
533 };
534
535 #define issbyte(x) ((x)>=-128 && (x)<=127)
536 #define isubyte(x) ((x)>=0 && (x)<=255)
537 #define issword(x) ((x)>=-32768 && (x)<=32767)
538 #define isuword(x) ((x)>=0 && (x)<=65535)
539
540 #define isbyte(x) ((x)>= -255 && (x)<=255)
541 #define isword(x) ((x)>=-65536 && (x)<=65535)
542 #define islong(x) (1)
543
544 extern char *input_line_pointer;
545
546 static char mklower_table[256];
547 #define mklower(c) (mklower_table[(unsigned char)(c)])
548 static char notend_table[256];
549 static char alt_notend_table[256];
550 #define notend(s) \
551 (! (notend_table[(unsigned char) *s] \
552 || (*s == ':' \
553 && alt_notend_table[(unsigned char) s[1]])))
554
555 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
556
557 #ifdef NO_PCREL_RELOCS
558
559 int
560 make_pcrel_absolute(fixP, add_number)
561 fixS *fixP;
562 long *add_number;
563 {
564 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
565
566 /* rewrite the PC relative instructions to absolute address ones.
567 * these are rumoured to be faster, and the apollo linker refuses
568 * to deal with the PC relative relocations.
569 */
570 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
571 {
572 opcode[0] = 0x4e;
573 opcode[1] = 0xf9;
574 }
575 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
576 {
577 opcode[0] = 0x4e;
578 opcode[1] = 0xb9;
579 }
580 else
581 as_fatal ("Unknown PC relative instruction");
582 *add_number -= 4;
583 return 0;
584 }
585
586 #endif /* NO_PCREL_RELOCS */
587
588 short
589 tc_coff_fix2rtype (fixP)
590 fixS *fixP;
591 {
592 if (fixP->fx_tcbit && fixP->fx_size == 4)
593 return R_RELLONG_NEG;
594 #ifdef NO_PCREL_RELOCS
595 know (fixP->fx_pcrel == 0);
596 return (fixP->fx_size == 1 ? R_RELBYTE
597 : fixP->fx_size == 2 ? R_DIR16
598 : R_DIR32);
599 #else
600 return (fixP->fx_pcrel ?
601 (fixP->fx_size == 1 ? R_PCRBYTE :
602 fixP->fx_size == 2 ? R_PCRWORD :
603 R_PCRLONG) :
604 (fixP->fx_size == 1 ? R_RELBYTE :
605 fixP->fx_size == 2 ? R_RELWORD :
606 R_RELLONG));
607 #endif
608 }
609
610 #endif
611
612 #ifdef OBJ_ELF
613
614 /* Compute the relocation code for a fixup of SIZE bytes, using pc
615 relative relocation if PCREL is non-zero. PIC says whether a special
616 pic relocation was requested. */
617
618 static bfd_reloc_code_real_type get_reloc_code
619 PARAMS ((int, int, enum pic_relocation));
620
621 static bfd_reloc_code_real_type
622 get_reloc_code (size, pcrel, pic)
623 int size;
624 int pcrel;
625 enum pic_relocation pic;
626 {
627 switch (pic)
628 {
629 case pic_got_pcrel:
630 switch (size)
631 {
632 case 1:
633 return BFD_RELOC_8_GOT_PCREL;
634 case 2:
635 return BFD_RELOC_16_GOT_PCREL;
636 case 4:
637 return BFD_RELOC_32_GOT_PCREL;
638 }
639 break;
640
641 case pic_got_off:
642 switch (size)
643 {
644 case 1:
645 return BFD_RELOC_8_GOTOFF;
646 case 2:
647 return BFD_RELOC_16_GOTOFF;
648 case 4:
649 return BFD_RELOC_32_GOTOFF;
650 }
651 break;
652
653 case pic_plt_pcrel:
654 switch (size)
655 {
656 case 1:
657 return BFD_RELOC_8_PLT_PCREL;
658 case 2:
659 return BFD_RELOC_16_PLT_PCREL;
660 case 4:
661 return BFD_RELOC_32_PLT_PCREL;
662 }
663 break;
664
665 case pic_plt_off:
666 switch (size)
667 {
668 case 1:
669 return BFD_RELOC_8_PLTOFF;
670 case 2:
671 return BFD_RELOC_16_PLTOFF;
672 case 4:
673 return BFD_RELOC_32_PLTOFF;
674 }
675 break;
676
677 case pic_none:
678 if (pcrel)
679 {
680 switch (size)
681 {
682 case 1:
683 return BFD_RELOC_8_PCREL;
684 case 2:
685 return BFD_RELOC_16_PCREL;
686 case 4:
687 return BFD_RELOC_32_PCREL;
688 }
689 }
690 else
691 {
692 switch (size)
693 {
694 case 1:
695 return BFD_RELOC_8;
696 case 2:
697 return BFD_RELOC_16;
698 case 4:
699 return BFD_RELOC_32;
700 }
701 }
702 }
703
704 as_bad ("Can not do %d byte %s%srelocation", size,
705 pcrel ? "pc-relative " : "",
706 pic == pic_none ? "" : "pic ");
707 return BFD_RELOC_NONE;
708 }
709
710 /* Here we decide which fixups can be adjusted to make them relative
711 to the beginning of the section instead of the symbol. Basically
712 we need to make sure that the dynamic relocations are done
713 correctly, so in some cases we force the original symbol to be
714 used. */
715 int
716 tc_m68k_fix_adjustable (fixP)
717 fixS *fixP;
718 {
719 /* Prevent all adjustments to global symbols. */
720 if (S_IS_EXTERNAL (fixP->fx_addsy))
721 return 0;
722
723 /* adjust_reloc_syms doesn't know about the GOT */
724 switch (fixP->fx_r_type)
725 {
726 case BFD_RELOC_8_GOT_PCREL:
727 case BFD_RELOC_16_GOT_PCREL:
728 case BFD_RELOC_32_GOT_PCREL:
729 case BFD_RELOC_8_GOTOFF:
730 case BFD_RELOC_16_GOTOFF:
731 case BFD_RELOC_32_GOTOFF:
732 case BFD_RELOC_8_PLT_PCREL:
733 case BFD_RELOC_16_PLT_PCREL:
734 case BFD_RELOC_32_PLT_PCREL:
735 case BFD_RELOC_8_PLTOFF:
736 case BFD_RELOC_16_PLTOFF:
737 case BFD_RELOC_32_PLTOFF:
738 return 0;
739
740 default:
741 return 1;
742 }
743 }
744
745 #else /* !OBJ_ELF */
746
747 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
748
749 #endif /* OBJ_ELF */
750
751 #ifdef BFD_ASSEMBLER
752
753 arelent *
754 tc_gen_reloc (section, fixp)
755 asection *section;
756 fixS *fixp;
757 {
758 arelent *reloc;
759 bfd_reloc_code_real_type code;
760
761 if (fixp->fx_tcbit)
762 abort ();
763
764 if (fixp->fx_r_type != BFD_RELOC_NONE)
765 {
766 code = fixp->fx_r_type;
767
768 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
769 that fixup_segment converted a non-PC relative reloc into a
770 PC relative reloc. In such a case, we need to convert the
771 reloc code. */
772 if (fixp->fx_pcrel)
773 {
774 switch (code)
775 {
776 case BFD_RELOC_8:
777 code = BFD_RELOC_8_PCREL;
778 break;
779 case BFD_RELOC_16:
780 code = BFD_RELOC_16_PCREL;
781 break;
782 case BFD_RELOC_32:
783 code = BFD_RELOC_32_PCREL;
784 break;
785 case BFD_RELOC_8_PCREL:
786 case BFD_RELOC_16_PCREL:
787 case BFD_RELOC_32_PCREL:
788 case BFD_RELOC_8_GOT_PCREL:
789 case BFD_RELOC_16_GOT_PCREL:
790 case BFD_RELOC_32_GOT_PCREL:
791 case BFD_RELOC_8_GOTOFF:
792 case BFD_RELOC_16_GOTOFF:
793 case BFD_RELOC_32_GOTOFF:
794 case BFD_RELOC_8_PLT_PCREL:
795 case BFD_RELOC_16_PLT_PCREL:
796 case BFD_RELOC_32_PLT_PCREL:
797 case BFD_RELOC_8_PLTOFF:
798 case BFD_RELOC_16_PLTOFF:
799 case BFD_RELOC_32_PLTOFF:
800 break;
801 default:
802 as_bad_where (fixp->fx_file, fixp->fx_line,
803 "Cannot make %s relocation PC relative",
804 bfd_get_reloc_code_name (code));
805 }
806 }
807 }
808 else
809 {
810 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
811 switch (F (fixp->fx_size, fixp->fx_pcrel))
812 {
813 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
814 MAP (1, 0, BFD_RELOC_8);
815 MAP (2, 0, BFD_RELOC_16);
816 MAP (4, 0, BFD_RELOC_32);
817 MAP (1, 1, BFD_RELOC_8_PCREL);
818 MAP (2, 1, BFD_RELOC_16_PCREL);
819 MAP (4, 1, BFD_RELOC_32_PCREL);
820 default:
821 abort ();
822 }
823 }
824 #undef F
825 #undef MAP
826
827 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
828 assert (reloc != 0);
829 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
830 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
831 #ifndef OBJ_ELF
832 if (fixp->fx_pcrel)
833 reloc->addend = fixp->fx_addnumber;
834 else
835 reloc->addend = 0;
836 #else
837 if (!fixp->fx_pcrel)
838 reloc->addend = fixp->fx_addnumber;
839 else
840 reloc->addend = (section->vma
841 + (fixp->fx_pcrel_adjust == 64
842 ? -1 : fixp->fx_pcrel_adjust)
843 + fixp->fx_addnumber
844 + md_pcrel_from (fixp));
845 #endif
846
847 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
848 assert (reloc->howto != 0);
849
850 return reloc;
851 }
852
853 #endif /* BFD_ASSEMBLER */
854
855 /* Handle of the OPCODE hash table. NULL means any use before
856 m68k_ip_begin() will crash. */
857 static struct hash_control *op_hash;
858 \f
859 /* Assemble an m68k instruction. */
860
861 void
862 m68k_ip (instring)
863 char *instring;
864 {
865 register char *p;
866 register struct m68k_op *opP;
867 register struct m68k_incant *opcode;
868 register const char *s;
869 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
870 char *pdot, *pdotmove;
871 enum m68k_size siz1, siz2;
872 char c;
873 int losing;
874 int opsfound;
875 char *crack_operand ();
876 LITTLENUM_TYPE words[6];
877 LITTLENUM_TYPE *wordp;
878 unsigned long ok_arch = 0;
879
880 if (*instring == ' ')
881 instring++; /* skip leading whitespace */
882
883 /* Scan up to end of operation-code, which MUST end in end-of-string
884 or exactly 1 space. */
885 pdot = 0;
886 for (p = instring; *p != '\0'; p++)
887 {
888 if (*p == ' ')
889 break;
890 if (*p == '.')
891 pdot = p;
892 }
893
894 if (p == instring)
895 {
896 the_ins.error = "No operator";
897 return;
898 }
899
900 /* p now points to the end of the opcode name, probably whitespace.
901 Make sure the name is null terminated by clobbering the
902 whitespace, look it up in the hash table, then fix it back.
903 Remove a dot, first, since the opcode tables have none. */
904 if (pdot != NULL)
905 {
906 for (pdotmove = pdot; pdotmove < p; pdotmove++)
907 *pdotmove = pdotmove[1];
908 p--;
909 }
910
911 c = *p;
912 *p = '\0';
913 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
914 *p = c;
915
916 if (pdot != NULL)
917 {
918 for (pdotmove = p; pdotmove > pdot; pdotmove--)
919 *pdotmove = pdotmove[-1];
920 *pdot = '.';
921 ++p;
922 }
923
924 if (opcode == NULL)
925 {
926 the_ins.error = "Unknown operator";
927 return;
928 }
929
930 /* found a legitimate opcode, start matching operands */
931 while (*p == ' ')
932 ++p;
933
934 if (opcode->m_operands == 0)
935 {
936 char *old = input_line_pointer;
937 *old = '\n';
938 input_line_pointer = p;
939 /* Ahh - it's a motorola style psuedo op */
940 mote_pseudo_table[opcode->m_opnum].poc_handler
941 (mote_pseudo_table[opcode->m_opnum].poc_val);
942 input_line_pointer = old;
943 *old = 0;
944
945 return;
946 }
947
948 if (flag_mri && opcode->m_opnum == 0)
949 {
950 /* In MRI mode, random garbage is allowed after an instruction
951 which accepts no operands. */
952 the_ins.args = opcode->m_operands;
953 the_ins.numargs = opcode->m_opnum;
954 the_ins.numo = opcode->m_codenum;
955 the_ins.opcode[0] = getone (opcode);
956 the_ins.opcode[1] = gettwo (opcode);
957 return;
958 }
959
960 for (opP = &the_ins.operands[0]; *p; opP++)
961 {
962 p = crack_operand (p, opP);
963
964 if (opP->error)
965 {
966 the_ins.error = opP->error;
967 return;
968 }
969 }
970
971 opsfound = opP - &the_ins.operands[0];
972
973 /* This ugly hack is to support the floating pt opcodes in their
974 standard form. Essentially, we fake a first enty of type COP#1 */
975 if (opcode->m_operands[0] == 'I')
976 {
977 int n;
978
979 for (n = opsfound; n > 0; --n)
980 the_ins.operands[n] = the_ins.operands[n - 1];
981
982 memset ((char *) (&the_ins.operands[0]), '\0',
983 sizeof (the_ins.operands[0]));
984 the_ins.operands[0].mode = CONTROL;
985 the_ins.operands[0].reg = m68k_float_copnum;
986 opsfound++;
987 }
988
989 /* We've got the operands. Find an opcode that'll accept them */
990 for (losing = 0;;)
991 {
992 /* If we didn't get the right number of ops, or we have no
993 common model with this pattern then reject this pattern. */
994
995 if (opsfound != opcode->m_opnum
996 || ((opcode->m_arch & current_architecture) == 0))
997 {
998 ++losing;
999 ok_arch |= opcode->m_arch;
1000 }
1001 else
1002 {
1003 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1004 *s && !losing;
1005 s += 2, opP++)
1006 {
1007 /* Warning: this switch is huge! */
1008 /* I've tried to organize the cases into this order:
1009 non-alpha first, then alpha by letter. Lower-case
1010 goes directly before uppercase counterpart. */
1011 /* Code with multiple case ...: gets sorted by the lowest
1012 case ... it belongs to. I hope this makes sense. */
1013 switch (*s)
1014 {
1015 case '!':
1016 switch (opP->mode)
1017 {
1018 case IMMED:
1019 case DREG:
1020 case AREG:
1021 case FPREG:
1022 case CONTROL:
1023 case AINC:
1024 case ADEC:
1025 case REGLST:
1026 losing++;
1027 break;
1028 default:
1029 break;
1030 }
1031 break;
1032
1033 case '`':
1034 switch (opP->mode)
1035 {
1036 case IMMED:
1037 case DREG:
1038 case AREG:
1039 case FPREG:
1040 case CONTROL:
1041 case AINC:
1042 case REGLST:
1043 case AINDR:
1044 losing++;
1045 break;
1046 default:
1047 break;
1048 }
1049 break;
1050
1051 case '#':
1052 if (opP->mode != IMMED)
1053 losing++;
1054 else if (s[1] == 'b'
1055 && ! isvar (&opP->disp)
1056 && (opP->disp.exp.X_op != O_constant
1057 || ! isbyte (opP->disp.exp.X_add_number)))
1058 losing++;
1059 else if (s[1] == 'w'
1060 && ! isvar (&opP->disp)
1061 && (opP->disp.exp.X_op != O_constant
1062 || ! isword (opP->disp.exp.X_add_number)))
1063 losing++;
1064 else if (s[1] == 'W'
1065 && ! isvar (&opP->disp)
1066 && (opP->disp.exp.X_op != O_constant
1067 || ! issword (opP->disp.exp.X_add_number)))
1068 losing++;
1069 break;
1070
1071 case '^':
1072 case 'T':
1073 if (opP->mode != IMMED)
1074 losing++;
1075 break;
1076
1077 case '$':
1078 if (opP->mode == AREG
1079 || opP->mode == CONTROL
1080 || opP->mode == FPREG
1081 || opP->mode == IMMED
1082 || opP->mode == REGLST
1083 || (opP->mode != ABSL
1084 && (opP->reg == PC
1085 || opP->reg == ZPC)))
1086 losing++;
1087 break;
1088
1089 case '%':
1090 if (opP->mode == CONTROL
1091 || opP->mode == FPREG
1092 || opP->mode == REGLST
1093 || opP->mode == IMMED
1094 || (opP->mode != ABSL
1095 && (opP->reg == PC
1096 || opP->reg == ZPC)))
1097 losing++;
1098 break;
1099
1100 case '&':
1101 switch (opP->mode)
1102 {
1103 case DREG:
1104 case AREG:
1105 case FPREG:
1106 case CONTROL:
1107 case IMMED:
1108 case AINC:
1109 case ADEC:
1110 case REGLST:
1111 losing++;
1112 break;
1113 case ABSL:
1114 break;
1115 default:
1116 if (opP->reg == PC
1117 || opP->reg == ZPC)
1118 losing++;
1119 break;
1120 }
1121 break;
1122
1123 case '*':
1124 if (opP->mode == CONTROL
1125 || opP->mode == FPREG
1126 || opP->mode == REGLST)
1127 losing++;
1128 break;
1129
1130 case '+':
1131 if (opP->mode != AINC)
1132 losing++;
1133 break;
1134
1135 case '-':
1136 if (opP->mode != ADEC)
1137 losing++;
1138 break;
1139
1140 case '/':
1141 switch (opP->mode)
1142 {
1143 case AREG:
1144 case CONTROL:
1145 case FPREG:
1146 case AINC:
1147 case ADEC:
1148 case IMMED:
1149 case REGLST:
1150 losing++;
1151 break;
1152 default:
1153 break;
1154 }
1155 break;
1156
1157 case ';':
1158 switch (opP->mode)
1159 {
1160 case AREG:
1161 case CONTROL:
1162 case FPREG:
1163 case REGLST:
1164 losing++;
1165 break;
1166 default:
1167 break;
1168 }
1169 break;
1170
1171 case '?':
1172 switch (opP->mode)
1173 {
1174 case AREG:
1175 case CONTROL:
1176 case FPREG:
1177 case AINC:
1178 case ADEC:
1179 case IMMED:
1180 case REGLST:
1181 losing++;
1182 break;
1183 case ABSL:
1184 break;
1185 default:
1186 if (opP->reg == PC || opP->reg == ZPC)
1187 losing++;
1188 break;
1189 }
1190 break;
1191
1192 case '@':
1193 switch (opP->mode)
1194 {
1195 case AREG:
1196 case CONTROL:
1197 case FPREG:
1198 case IMMED:
1199 case REGLST:
1200 losing++;
1201 break;
1202 default:
1203 break;
1204 }
1205 break;
1206
1207 case '~': /* For now! (JF FOO is this right?) */
1208 switch (opP->mode)
1209 {
1210 case DREG:
1211 case AREG:
1212 case CONTROL:
1213 case FPREG:
1214 case IMMED:
1215 case REGLST:
1216 losing++;
1217 break;
1218 case ABSL:
1219 break;
1220 default:
1221 if (opP->reg == PC
1222 || opP->reg == ZPC)
1223 losing++;
1224 break;
1225 }
1226 break;
1227
1228 case '3':
1229 if (opP->mode != CONTROL
1230 || (opP->reg != TT0 && opP->reg != TT1))
1231 losing++;
1232 break;
1233
1234 case 'A':
1235 if (opP->mode != AREG)
1236 losing++;
1237 break;
1238
1239 case 'a':
1240 if (opP->mode != AINDR)
1241 ++losing;
1242 break;
1243
1244 case 'B': /* FOO */
1245 if (opP->mode != ABSL
1246 || (flag_long_jumps
1247 && strncmp (instring, "jbsr", 4) == 0))
1248 losing++;
1249 break;
1250
1251 case 'C':
1252 if (opP->mode != CONTROL || opP->reg != CCR)
1253 losing++;
1254 break;
1255
1256 case 'd':
1257 if (opP->mode != DISP
1258 || opP->reg < ADDR0
1259 || opP->reg > ADDR7)
1260 losing++;
1261 break;
1262
1263 case 'D':
1264 if (opP->mode != DREG)
1265 losing++;
1266 break;
1267
1268 case 'F':
1269 if (opP->mode != FPREG)
1270 losing++;
1271 break;
1272
1273 case 'I':
1274 if (opP->mode != CONTROL
1275 || opP->reg < COP0
1276 || opP->reg > COP7)
1277 losing++;
1278 break;
1279
1280 case 'J':
1281 if (opP->mode != CONTROL
1282 || opP->reg < USP
1283 || opP->reg > last_movec_reg)
1284 losing++;
1285 else
1286 {
1287 const enum m68k_register *rp;
1288 for (rp = control_regs; *rp; rp++)
1289 if (*rp == opP->reg)
1290 break;
1291 if (*rp == 0)
1292 losing++;
1293 }
1294 break;
1295
1296 case 'k':
1297 if (opP->mode != IMMED)
1298 losing++;
1299 break;
1300
1301 case 'l':
1302 case 'L':
1303 if (opP->mode == DREG
1304 || opP->mode == AREG
1305 || opP->mode == FPREG)
1306 {
1307 if (s[1] == '8')
1308 losing++;
1309 else
1310 {
1311 switch (opP->mode)
1312 {
1313 case DREG:
1314 opP->mask = 1 << (opP->reg - DATA0);
1315 break;
1316 case AREG:
1317 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1318 break;
1319 case FPREG:
1320 opP->mask = 1 << (opP->reg - FP0 + 16);
1321 break;
1322 default:
1323 abort ();
1324 }
1325 opP->mode = REGLST;
1326 }
1327 }
1328 else if (opP->mode == CONTROL)
1329 {
1330 if (s[1] != '8')
1331 losing++;
1332 else
1333 {
1334 switch (opP->reg)
1335 {
1336 case FPI:
1337 opP->mask = 1 << 24;
1338 break;
1339 case FPS:
1340 opP->mask = 1 << 25;
1341 break;
1342 case FPC:
1343 opP->mask = 1 << 26;
1344 break;
1345 default:
1346 losing++;
1347 break;
1348 }
1349 opP->mode = REGLST;
1350 }
1351 }
1352 else if (opP->mode == ABSL
1353 && opP->disp.size == SIZE_UNSPEC
1354 && opP->disp.exp.X_op == O_constant)
1355 {
1356 /* This is what the MRI REG pseudo-op generates. */
1357 opP->mode = REGLST;
1358 opP->mask = opP->disp.exp.X_add_number;
1359 }
1360 else if (opP->mode != REGLST)
1361 losing++;
1362 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1363 losing++;
1364 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1365 losing++;
1366 break;
1367
1368 case 'M':
1369 if (opP->mode != IMMED)
1370 losing++;
1371 else if (opP->disp.exp.X_op != O_constant
1372 || ! issbyte (opP->disp.exp.X_add_number))
1373 losing++;
1374 else if (! m68k_quick
1375 && instring[3] != 'q'
1376 && instring[4] != 'q')
1377 losing++;
1378 break;
1379
1380 case 'O':
1381 if (opP->mode != DREG
1382 && opP->mode != IMMED
1383 && opP->mode != ABSL)
1384 losing++;
1385 break;
1386
1387 case 'Q':
1388 if (opP->mode != IMMED)
1389 losing++;
1390 else if (opP->disp.exp.X_op != O_constant
1391 || opP->disp.exp.X_add_number < 1
1392 || opP->disp.exp.X_add_number > 8)
1393 losing++;
1394 else if (! m68k_quick
1395 && (strncmp (instring, "add", 3) == 0
1396 || strncmp (instring, "sub", 3) == 0)
1397 && instring[3] != 'q')
1398 losing++;
1399 break;
1400
1401 case 'R':
1402 if (opP->mode != DREG && opP->mode != AREG)
1403 losing++;
1404 break;
1405
1406 case 'r':
1407 if (opP->mode != AINDR
1408 && (opP->mode != BASE
1409 || (opP->reg != 0
1410 && opP->reg != ZADDR0)
1411 || opP->disp.exp.X_op != O_absent
1412 || ((opP->index.reg < DATA0
1413 || opP->index.reg > DATA7)
1414 && (opP->index.reg < ADDR0
1415 || opP->index.reg > ADDR7))
1416 || opP->index.size != SIZE_UNSPEC
1417 || opP->index.scale != 1))
1418 losing++;
1419 break;
1420
1421 case 's':
1422 if (opP->mode != CONTROL
1423 || ! (opP->reg == FPI
1424 || opP->reg == FPS
1425 || opP->reg == FPC))
1426 losing++;
1427 break;
1428
1429 case 'S':
1430 if (opP->mode != CONTROL || opP->reg != SR)
1431 losing++;
1432 break;
1433
1434 case 't':
1435 if (opP->mode != IMMED)
1436 losing++;
1437 else if (opP->disp.exp.X_op != O_constant
1438 || opP->disp.exp.X_add_number < 0
1439 || opP->disp.exp.X_add_number > 7)
1440 losing++;
1441 break;
1442
1443 case 'U':
1444 if (opP->mode != CONTROL || opP->reg != USP)
1445 losing++;
1446 break;
1447
1448 /* JF these are out of order. We could put them
1449 in order if we were willing to put up with
1450 bunches of #ifdef m68851s in the code.
1451
1452 Don't forget that you need these operands
1453 to use 68030 MMU instructions. */
1454 #ifndef NO_68851
1455 /* Memory addressing mode used by pflushr */
1456 case '|':
1457 if (opP->mode == CONTROL
1458 || opP->mode == FPREG
1459 || opP->mode == DREG
1460 || opP->mode == AREG
1461 || opP->mode == REGLST)
1462 losing++;
1463 /* We should accept immediate operands, but they
1464 supposedly have to be quad word, and we don't
1465 handle that. I would like to see what a Motorola
1466 assembler does before doing something here. */
1467 if (opP->mode == IMMED)
1468 losing++;
1469 break;
1470
1471 case 'f':
1472 if (opP->mode != CONTROL
1473 || (opP->reg != SFC && opP->reg != DFC))
1474 losing++;
1475 break;
1476
1477 case '0':
1478 if (opP->mode != CONTROL || opP->reg != TC)
1479 losing++;
1480 break;
1481
1482 case '1':
1483 if (opP->mode != CONTROL || opP->reg != AC)
1484 losing++;
1485 break;
1486
1487 case '2':
1488 if (opP->mode != CONTROL
1489 || (opP->reg != CAL
1490 && opP->reg != VAL
1491 && opP->reg != SCC))
1492 losing++;
1493 break;
1494
1495 case 'V':
1496 if (opP->mode != CONTROL
1497 || opP->reg != VAL)
1498 losing++;
1499 break;
1500
1501 case 'W':
1502 if (opP->mode != CONTROL
1503 || (opP->reg != DRP
1504 && opP->reg != SRP
1505 && opP->reg != CRP))
1506 losing++;
1507 break;
1508
1509 case 'X':
1510 if (opP->mode != CONTROL
1511 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1512 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1513 losing++;
1514 break;
1515
1516 case 'Y':
1517 if (opP->mode != CONTROL || opP->reg != PSR)
1518 losing++;
1519 break;
1520
1521 case 'Z':
1522 if (opP->mode != CONTROL || opP->reg != PCSR)
1523 losing++;
1524 break;
1525 #endif
1526 case 'c':
1527 if (opP->mode != CONTROL
1528 || (opP->reg != NC
1529 && opP->reg != IC
1530 && opP->reg != DC
1531 && opP->reg != BC))
1532 {
1533 losing++;
1534 } /* not a cache specifier. */
1535 break;
1536
1537 case '_':
1538 if (opP->mode != ABSL)
1539 ++losing;
1540 break;
1541
1542 default:
1543 abort ();
1544 } /* switch on type of operand */
1545
1546 if (losing)
1547 break;
1548 } /* for each operand */
1549 } /* if immediately wrong */
1550
1551 if (!losing)
1552 {
1553 break;
1554 } /* got it. */
1555
1556 opcode = opcode->m_next;
1557
1558 if (!opcode)
1559 {
1560 if (ok_arch
1561 && !(ok_arch & current_architecture))
1562 {
1563 char buf[200], *cp;
1564 int len;
1565 strcpy (buf,
1566 "invalid instruction for this architecture; needs ");
1567 cp = buf + strlen (buf);
1568 switch (ok_arch)
1569 {
1570 case mfloat:
1571 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1572 break;
1573 case mmmu:
1574 strcpy (cp, "mmu (68030 or 68851)");
1575 break;
1576 case m68020up:
1577 strcpy (cp, "68020 or higher");
1578 break;
1579 case m68000up:
1580 strcpy (cp, "68000 or higher");
1581 break;
1582 case m68010up:
1583 strcpy (cp, "68010 or higher");
1584 break;
1585 default:
1586 {
1587 int got_one = 0, idx;
1588 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1589 idx++)
1590 {
1591 if ((archs[idx].arch & ok_arch)
1592 && ! archs[idx].alias)
1593 {
1594 if (got_one)
1595 {
1596 strcpy (cp, " or ");
1597 cp += strlen (cp);
1598 }
1599 got_one = 1;
1600 strcpy (cp, archs[idx].name);
1601 cp += strlen (cp);
1602 }
1603 }
1604 }
1605 }
1606 len = cp - buf + 1;
1607 cp = malloc (len);
1608 strcpy (cp, buf);
1609 the_ins.error = cp;
1610 }
1611 else
1612 the_ins.error = "operands mismatch";
1613 return;
1614 } /* Fell off the end */
1615
1616 losing = 0;
1617 }
1618
1619 /* now assemble it */
1620
1621 the_ins.args = opcode->m_operands;
1622 the_ins.numargs = opcode->m_opnum;
1623 the_ins.numo = opcode->m_codenum;
1624 the_ins.opcode[0] = getone (opcode);
1625 the_ins.opcode[1] = gettwo (opcode);
1626
1627 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1628 {
1629 /* This switch is a doozy.
1630 Watch the first step; its a big one! */
1631 switch (s[0])
1632 {
1633
1634 case '*':
1635 case '~':
1636 case '%':
1637 case ';':
1638 case '@':
1639 case '!':
1640 case '&':
1641 case '$':
1642 case '?':
1643 case '/':
1644 case '`':
1645 #ifndef NO_68851
1646 case '|':
1647 #endif
1648 switch (opP->mode)
1649 {
1650 case IMMED:
1651 tmpreg = 0x3c; /* 7.4 */
1652 if (strchr ("bwl", s[1]))
1653 nextword = get_num (&opP->disp, 80);
1654 else
1655 nextword = get_num (&opP->disp, 0);
1656 if (isvar (&opP->disp))
1657 add_fix (s[1], &opP->disp, 0, 0);
1658 switch (s[1])
1659 {
1660 case 'b':
1661 if (!isbyte (nextword))
1662 opP->error = "operand out of range";
1663 addword (nextword);
1664 baseo = 0;
1665 break;
1666 case 'w':
1667 if (!isword (nextword))
1668 opP->error = "operand out of range";
1669 addword (nextword);
1670 baseo = 0;
1671 break;
1672 case 'W':
1673 if (!issword (nextword))
1674 opP->error = "operand out of range";
1675 addword (nextword);
1676 baseo = 0;
1677 break;
1678 case 'l':
1679 addword (nextword >> 16);
1680 addword (nextword);
1681 baseo = 0;
1682 break;
1683
1684 case 'f':
1685 baseo = 2;
1686 outro = 8;
1687 break;
1688 case 'F':
1689 baseo = 4;
1690 outro = 11;
1691 break;
1692 case 'x':
1693 baseo = 6;
1694 outro = 15;
1695 break;
1696 case 'p':
1697 baseo = 6;
1698 outro = -1;
1699 break;
1700 default:
1701 abort ();
1702 }
1703 if (!baseo)
1704 break;
1705
1706 /* We gotta put out some float */
1707 if (op (&opP->disp) != O_big)
1708 {
1709 valueT val;
1710 int gencnt;
1711
1712 /* Can other cases happen here? */
1713 if (op (&opP->disp) != O_constant)
1714 abort ();
1715
1716 val = (valueT) offs (&opP->disp);
1717 gencnt = 0;
1718 do
1719 {
1720 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1721 val >>= LITTLENUM_NUMBER_OF_BITS;
1722 ++gencnt;
1723 }
1724 while (val != 0);
1725 offs (&opP->disp) = gencnt;
1726 }
1727 if (offs (&opP->disp) > 0)
1728 {
1729 if (offs (&opP->disp) > baseo)
1730 {
1731 as_warn ("Bignum too big for %c format; truncated",
1732 s[1]);
1733 offs (&opP->disp) = baseo;
1734 }
1735 baseo -= offs (&opP->disp);
1736 while (baseo--)
1737 addword (0);
1738 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1739 offs (&opP->disp)--;
1740 --wordp)
1741 addword (*wordp);
1742 break;
1743 }
1744 gen_to_words (words, baseo, (long) outro);
1745 for (wordp = words; baseo--; wordp++)
1746 addword (*wordp);
1747 break;
1748 case DREG:
1749 tmpreg = opP->reg - DATA; /* 0.dreg */
1750 break;
1751 case AREG:
1752 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1753 break;
1754 case AINDR:
1755 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1756 break;
1757 case ADEC:
1758 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1759 break;
1760 case AINC:
1761 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1762 break;
1763 case DISP:
1764
1765 nextword = get_num (&opP->disp, 80);
1766
1767 if (opP->reg == PC
1768 && ! isvar (&opP->disp)
1769 && m68k_abspcadd)
1770 {
1771 opP->disp.exp.X_op = O_symbol;
1772 #ifndef BFD_ASSEMBLER
1773 opP->disp.exp.X_add_symbol = &abs_symbol;
1774 #else
1775 opP->disp.exp.X_add_symbol =
1776 section_symbol (absolute_section);
1777 #endif
1778 }
1779
1780 /* Force into index mode. Hope this works */
1781
1782 /* We do the first bit for 32-bit displacements, and the
1783 second bit for 16 bit ones. It is possible that we
1784 should make the default be WORD instead of LONG, but
1785 I think that'd break GCC, so we put up with a little
1786 inefficiency for the sake of working output. */
1787
1788 if (!issword (nextword)
1789 || (isvar (&opP->disp)
1790 && ((opP->disp.size == SIZE_UNSPEC
1791 && flag_short_refs == 0
1792 && cpu_of_arch (current_architecture) >= m68020)
1793 || opP->disp.size == SIZE_LONG)))
1794 {
1795 if (cpu_of_arch (current_architecture) < m68020)
1796 opP->error =
1797 "displacement too large for this architecture; needs 68020 or higher";
1798 if (opP->reg == PC)
1799 tmpreg = 0x3B; /* 7.3 */
1800 else
1801 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1802 if (isvar (&opP->disp))
1803 {
1804 if (opP->reg == PC)
1805 {
1806 if (opP->disp.size == SIZE_LONG
1807 #ifdef OBJ_ELF
1808 /* If the displacement needs pic
1809 relocation it cannot be relaxed. */
1810 || opP->disp.pic_reloc != pic_none
1811 #endif
1812 )
1813 {
1814 addword (0x0170);
1815 add_fix ('l', &opP->disp, 1, 2);
1816 }
1817 else
1818 {
1819 add_frag (adds (&opP->disp),
1820 offs (&opP->disp),
1821 TAB (PCLEA, SZ_UNDEF));
1822 break;
1823 }
1824 }
1825 else
1826 {
1827 addword (0x0170);
1828 add_fix ('l', &opP->disp, 0, 0);
1829 }
1830 }
1831 else
1832 addword (0x0170);
1833 addword (nextword >> 16);
1834 }
1835 else
1836 {
1837 if (opP->reg == PC)
1838 tmpreg = 0x3A; /* 7.2 */
1839 else
1840 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1841
1842 if (isvar (&opP->disp))
1843 {
1844 if (opP->reg == PC)
1845 {
1846 add_fix ('w', &opP->disp, 1, 0);
1847 }
1848 else
1849 add_fix ('w', &opP->disp, 0, 0);
1850 }
1851 }
1852 addword (nextword);
1853 break;
1854
1855 case POST:
1856 case PRE:
1857 case BASE:
1858 nextword = 0;
1859 baseo = get_num (&opP->disp, 80);
1860 if (opP->mode == POST || opP->mode == PRE)
1861 outro = get_num (&opP->odisp, 80);
1862 /* Figure out the `addressing mode'.
1863 Also turn on the BASE_DISABLE bit, if needed. */
1864 if (opP->reg == PC || opP->reg == ZPC)
1865 {
1866 tmpreg = 0x3b; /* 7.3 */
1867 if (opP->reg == ZPC)
1868 nextword |= 0x80;
1869 }
1870 else if (opP->reg == 0)
1871 {
1872 nextword |= 0x80;
1873 tmpreg = 0x30; /* 6.garbage */
1874 }
1875 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1876 {
1877 nextword |= 0x80;
1878 tmpreg = 0x30 + opP->reg - ZADDR0;
1879 }
1880 else
1881 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1882
1883 siz1 = opP->disp.size;
1884 if (opP->mode == POST || opP->mode == PRE)
1885 siz2 = opP->odisp.size;
1886 else
1887 siz2 = SIZE_UNSPEC;
1888
1889 /* Index register stuff */
1890 if (opP->index.reg != 0
1891 && opP->index.reg >= DATA
1892 && opP->index.reg <= ADDR7)
1893 {
1894 nextword |= (opP->index.reg - DATA) << 12;
1895
1896 if (opP->index.size == SIZE_UNSPEC
1897 || opP->index.size == SIZE_LONG)
1898 nextword |= 0x800;
1899
1900 if ((opP->index.scale != 1
1901 && cpu_of_arch (current_architecture) < m68020)
1902 || (opP->index.scale == 8
1903 && current_architecture == mcf5200))
1904 {
1905 opP->error =
1906 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher";
1907 }
1908
1909 switch (opP->index.scale)
1910 {
1911 case 1:
1912 break;
1913 case 2:
1914 nextword |= 0x200;
1915 break;
1916 case 4:
1917 nextword |= 0x400;
1918 break;
1919 case 8:
1920 nextword |= 0x600;
1921 break;
1922 default:
1923 abort ();
1924 }
1925 /* IF its simple,
1926 GET US OUT OF HERE! */
1927
1928 /* Must be INDEX, with an index register. Address
1929 register cannot be ZERO-PC, and either :b was
1930 forced, or we know it will fit. For a 68000 or
1931 68010, force this mode anyways, because the
1932 larger modes aren't supported. */
1933 if (opP->mode == BASE
1934 && ((opP->reg >= ADDR0
1935 && opP->reg <= ADDR7)
1936 || opP->reg == PC))
1937 {
1938 if (siz1 == SIZE_BYTE
1939 || cpu_of_arch (current_architecture) < m68020
1940 || (siz1 == SIZE_UNSPEC
1941 && ! isvar (&opP->disp)
1942 && issbyte (baseo)))
1943 {
1944 nextword += baseo & 0xff;
1945 addword (nextword);
1946 if (isvar (&opP->disp))
1947 {
1948 /* Do a byte relocation. If it doesn't
1949 fit (possible on m68000) let the
1950 fixup processing complain later. */
1951 if (opP->reg == PC)
1952 add_fix ('B', &opP->disp, 1, 1);
1953 else
1954 add_fix ('B', &opP->disp, 0, 0);
1955 }
1956 else if (siz1 != SIZE_BYTE)
1957 {
1958 if (siz1 != SIZE_UNSPEC)
1959 as_warn ("Forcing byte displacement");
1960 if (! issbyte (baseo))
1961 opP->error = "byte displacement out of range";
1962 }
1963
1964 break;
1965 }
1966 else if (siz1 == SIZE_UNSPEC
1967 && opP->reg == PC
1968 && isvar (&opP->disp)
1969 && subs (&opP->disp) == NULL
1970 #ifdef OBJ_ELF
1971 /* If the displacement needs pic
1972 relocation it cannot be relaxed. */
1973 && opP->disp.pic_reloc == pic_none
1974 #endif
1975 )
1976 {
1977 nextword += baseo & 0xff;
1978 addword (nextword);
1979 add_frag (adds (&opP->disp), offs (&opP->disp),
1980 TAB (PCINDEX, SZ_UNDEF));
1981
1982 break;
1983 }
1984 }
1985 }
1986 else
1987 {
1988 nextword |= 0x40; /* No index reg */
1989 if (opP->index.reg >= ZDATA0
1990 && opP->index.reg <= ZDATA7)
1991 nextword |= (opP->index.reg - ZDATA0) << 12;
1992 else if (opP->index.reg >= ZADDR0
1993 || opP->index.reg <= ZADDR7)
1994 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1995 }
1996
1997 /* It isn't simple. */
1998
1999 if (cpu_of_arch (current_architecture) < m68020)
2000 opP->error =
2001 "invalid operand mode for this architecture; needs 68020 or higher";
2002
2003 nextword |= 0x100;
2004 /* If the guy specified a width, we assume that it is
2005 wide enough. Maybe it isn't. If so, we lose. */
2006 switch (siz1)
2007 {
2008 case SIZE_UNSPEC:
2009 if (isvar (&opP->disp)
2010 ? m68k_rel32
2011 : ! issword (baseo))
2012 {
2013 siz1 = SIZE_LONG;
2014 nextword |= 0x30;
2015 }
2016 else if (! isvar (&opP->disp) && baseo == 0)
2017 nextword |= 0x10;
2018 else
2019 {
2020 nextword |= 0x20;
2021 siz1 = SIZE_WORD;
2022 }
2023 break;
2024 case SIZE_BYTE:
2025 as_warn (":b not permitted; defaulting to :w");
2026 /* Fall through. */
2027 case SIZE_WORD:
2028 nextword |= 0x20;
2029 break;
2030 case SIZE_LONG:
2031 nextword |= 0x30;
2032 break;
2033 }
2034
2035 /* Figure out innner displacement stuff */
2036 if (opP->mode == POST || opP->mode == PRE)
2037 {
2038 if (cpu_of_arch (current_architecture) & cpu32)
2039 opP->error = "invalid operand mode for this architecture; needs 68020 or higher";
2040 switch (siz2)
2041 {
2042 case SIZE_UNSPEC:
2043 if (isvar (&opP->odisp)
2044 ? m68k_rel32
2045 : ! issword (outro))
2046 {
2047 siz2 = SIZE_LONG;
2048 nextword |= 0x3;
2049 }
2050 else if (! isvar (&opP->odisp) && outro == 0)
2051 nextword |= 0x1;
2052 else
2053 {
2054 nextword |= 0x2;
2055 siz2 = SIZE_WORD;
2056 }
2057 break;
2058 case 1:
2059 as_warn (":b not permitted; defaulting to :w");
2060 /* Fall through. */
2061 case 2:
2062 nextword |= 0x2;
2063 break;
2064 case 3:
2065 nextword |= 0x3;
2066 break;
2067 }
2068 if (opP->mode == POST
2069 && (nextword & 0x40) == 0)
2070 nextword |= 0x04;
2071 }
2072 addword (nextword);
2073
2074 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2075 {
2076 if (opP->reg == PC || opP->reg == ZPC)
2077 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2078 else
2079 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2080 }
2081 if (siz1 == SIZE_LONG)
2082 addword (baseo >> 16);
2083 if (siz1 != SIZE_UNSPEC)
2084 addword (baseo);
2085
2086 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2087 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2088 if (siz2 == SIZE_LONG)
2089 addword (outro >> 16);
2090 if (siz2 != SIZE_UNSPEC)
2091 addword (outro);
2092
2093 break;
2094
2095 case ABSL:
2096 nextword = get_num (&opP->disp, 80);
2097 switch (opP->disp.size)
2098 {
2099 default:
2100 abort ();
2101 case SIZE_UNSPEC:
2102 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2103 {
2104 tmpreg = 0x38; /* 7.0 */
2105 addword (nextword);
2106 break;
2107 }
2108 /* Don't generate pc relative code on 68010 and
2109 68000. */
2110 if (isvar (&opP->disp)
2111 && !subs (&opP->disp)
2112 && adds (&opP->disp)
2113 #ifdef OBJ_ELF
2114 /* If the displacement needs pic relocation it
2115 cannot be relaxed. */
2116 && opP->disp.pic_reloc == pic_none
2117 #endif
2118 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2119 && cpu_of_arch (current_architecture) >= m68020
2120 && !flag_long_jumps
2121 && !strchr ("~%&$?", s[0]))
2122 {
2123 tmpreg = 0x3A; /* 7.2 */
2124 add_frag (adds (&opP->disp),
2125 offs (&opP->disp),
2126 TAB (PCREL, SZ_UNDEF));
2127 break;
2128 }
2129 /* Fall through into long */
2130 case SIZE_LONG:
2131 if (isvar (&opP->disp))
2132 add_fix ('l', &opP->disp, 0, 0);
2133
2134 tmpreg = 0x39;/* 7.1 mode */
2135 addword (nextword >> 16);
2136 addword (nextword);
2137 break;
2138
2139 case SIZE_WORD: /* Word */
2140 if (isvar (&opP->disp))
2141 add_fix ('w', &opP->disp, 0, 0);
2142
2143 tmpreg = 0x38;/* 7.0 mode */
2144 addword (nextword);
2145 break;
2146 }
2147 break;
2148 case CONTROL:
2149 case FPREG:
2150 default:
2151 as_bad ("unknown/incorrect operand");
2152 /* abort(); */
2153 }
2154 install_gen_operand (s[1], tmpreg);
2155 break;
2156
2157 case '#':
2158 case '^':
2159 switch (s[1])
2160 { /* JF: I hate floating point! */
2161 case 'j':
2162 tmpreg = 70;
2163 break;
2164 case '8':
2165 tmpreg = 20;
2166 break;
2167 case 'C':
2168 tmpreg = 50;
2169 break;
2170 case '3':
2171 default:
2172 tmpreg = 80;
2173 break;
2174 }
2175 tmpreg = get_num (&opP->disp, tmpreg);
2176 if (isvar (&opP->disp))
2177 add_fix (s[1], &opP->disp, 0, 0);
2178 switch (s[1])
2179 {
2180 case 'b': /* Danger: These do no check for
2181 certain types of overflow.
2182 user beware! */
2183 if (!isbyte (tmpreg))
2184 opP->error = "out of range";
2185 insop (tmpreg, opcode);
2186 if (isvar (&opP->disp))
2187 the_ins.reloc[the_ins.nrel - 1].n =
2188 (opcode->m_codenum) * 2 + 1;
2189 break;
2190 case 'w':
2191 if (!isword (tmpreg))
2192 opP->error = "out of range";
2193 insop (tmpreg, opcode);
2194 if (isvar (&opP->disp))
2195 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2196 break;
2197 case 'W':
2198 if (!issword (tmpreg))
2199 opP->error = "out of range";
2200 insop (tmpreg, opcode);
2201 if (isvar (&opP->disp))
2202 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2203 break;
2204 case 'l':
2205 /* Because of the way insop works, we put these two out
2206 backwards. */
2207 insop (tmpreg, opcode);
2208 insop (tmpreg >> 16, opcode);
2209 if (isvar (&opP->disp))
2210 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2211 break;
2212 case '3':
2213 tmpreg &= 0xFF;
2214 case '8':
2215 case 'C':
2216 install_operand (s[1], tmpreg);
2217 break;
2218 default:
2219 abort ();
2220 }
2221 break;
2222
2223 case '+':
2224 case '-':
2225 case 'A':
2226 case 'a':
2227 install_operand (s[1], opP->reg - ADDR);
2228 break;
2229
2230 case 'B':
2231 tmpreg = get_num (&opP->disp, 80);
2232 switch (s[1])
2233 {
2234 case 'B':
2235 /* The pc_fix argument winds up in fx_pcrel_adjust,
2236 which is a char, and may therefore be unsigned. We
2237 want to pass -1, but we pass 64 instead, and convert
2238 back in md_pcrel_from. */
2239 add_fix ('B', &opP->disp, 1, 64);
2240 break;
2241 case 'W':
2242 add_fix ('w', &opP->disp, 1, 0);
2243 addword (0);
2244 break;
2245 case 'L':
2246 long_branch:
2247 if (cpu_of_arch (current_architecture) < m68020)
2248 as_warn ("Can't use long branches on 68000/68010");
2249 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2250 add_fix ('l', &opP->disp, 1, 0);
2251 addword (0);
2252 addword (0);
2253 break;
2254 case 'g':
2255 if (subs (&opP->disp)) /* We can't relax it */
2256 goto long_branch;
2257
2258 #ifdef OBJ_ELF
2259 /* If the displacement needs pic relocation it cannot be
2260 relaxed. */
2261 if (opP->disp.pic_reloc != pic_none)
2262 goto long_branch;
2263 #endif
2264
2265 /* This could either be a symbol, or an absolute
2266 address. No matter, the frag hacking will finger it
2267 out. Not quite: it can't switch from BRANCH to
2268 BCC68000 for the case where opnd is absolute (it
2269 needs to use the 68000 hack since no conditional abs
2270 jumps). */
2271 if (((cpu_of_arch (current_architecture) < m68020)
2272 || (0 == adds (&opP->disp)))
2273 && (the_ins.opcode[0] >= 0x6200)
2274 && (the_ins.opcode[0] <= 0x6f00))
2275 add_frag (adds (&opP->disp), offs (&opP->disp),
2276 TAB (BCC68000, SZ_UNDEF));
2277 else
2278 add_frag (adds (&opP->disp), offs (&opP->disp),
2279 TAB (ABRANCH, SZ_UNDEF));
2280 break;
2281 case 'w':
2282 if (isvar (&opP->disp))
2283 {
2284 #if 1
2285 /* check for DBcc instruction */
2286 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2287 {
2288 /* size varies if patch */
2289 /* needed for long form */
2290 add_frag (adds (&opP->disp), offs (&opP->disp),
2291 TAB (DBCC, SZ_UNDEF));
2292 break;
2293 }
2294 #endif
2295 add_fix ('w', &opP->disp, 1, 0);
2296 }
2297 addword (0);
2298 break;
2299 case 'C': /* Fixed size LONG coproc branches */
2300 add_fix ('l', &opP->disp, 1, 0);
2301 addword (0);
2302 addword (0);
2303 break;
2304 case 'c': /* Var size Coprocesssor branches */
2305 if (subs (&opP->disp))
2306 {
2307 add_fix ('l', &opP->disp, 1, 0);
2308 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2309 }
2310 else if (adds (&opP->disp))
2311 add_frag (adds (&opP->disp), offs (&opP->disp),
2312 TAB (FBRANCH, SZ_UNDEF));
2313 else
2314 {
2315 /* add_frag((symbolS *) 0, offs(&opP->disp),
2316 TAB(FBRANCH,SHORT)); */
2317 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2318 add_fix ('l', &opP->disp, 1, 0);
2319 addword (0);
2320 addword (0);
2321 }
2322 break;
2323 default:
2324 abort ();
2325 }
2326 break;
2327
2328 case 'C': /* Ignore it */
2329 break;
2330
2331 case 'd': /* JF this is a kludge */
2332 install_operand ('s', opP->reg - ADDR);
2333 tmpreg = get_num (&opP->disp, 80);
2334 if (!issword (tmpreg))
2335 {
2336 as_warn ("Expression out of range, using 0");
2337 tmpreg = 0;
2338 }
2339 addword (tmpreg);
2340 break;
2341
2342 case 'D':
2343 install_operand (s[1], opP->reg - DATA);
2344 break;
2345
2346 case 'F':
2347 install_operand (s[1], opP->reg - FP0);
2348 break;
2349
2350 case 'I':
2351 tmpreg = opP->reg - COP0;
2352 install_operand (s[1], tmpreg);
2353 break;
2354
2355 case 'J': /* JF foo */
2356 switch (opP->reg)
2357 {
2358 case SFC:
2359 tmpreg = 0x000;
2360 break;
2361 case DFC:
2362 tmpreg = 0x001;
2363 break;
2364 case CACR:
2365 tmpreg = 0x002;
2366 break;
2367 case TC:
2368 tmpreg = 0x003;
2369 break;
2370 case ITT0:
2371 tmpreg = 0x004;
2372 break;
2373 case ITT1:
2374 tmpreg = 0x005;
2375 break;
2376 case DTT0:
2377 tmpreg = 0x006;
2378 break;
2379 case DTT1:
2380 tmpreg = 0x007;
2381 break;
2382 case BUSCR:
2383 tmpreg = 0x008;
2384 break;
2385
2386 case USP:
2387 tmpreg = 0x800;
2388 break;
2389 case VBR:
2390 tmpreg = 0x801;
2391 break;
2392 case CAAR:
2393 tmpreg = 0x802;
2394 break;
2395 case MSP:
2396 tmpreg = 0x803;
2397 break;
2398 case ISP:
2399 tmpreg = 0x804;
2400 break;
2401 case MMUSR:
2402 tmpreg = 0x805;
2403 break;
2404 case URP:
2405 tmpreg = 0x806;
2406 break;
2407 case SRP:
2408 tmpreg = 0x807;
2409 break;
2410 case PCR:
2411 tmpreg = 0x808;
2412 break;
2413 case ROMBAR:
2414 tmpreg = 0xC00;
2415 break;
2416 case RAMBAR0:
2417 tmpreg = 0xC04;
2418 break;
2419 case RAMBAR1:
2420 tmpreg = 0xC05;
2421 break;
2422 case MBAR:
2423 tmpreg = 0xC0F;
2424 break;
2425 default:
2426 abort ();
2427 }
2428 install_operand (s[1], tmpreg);
2429 break;
2430
2431 case 'k':
2432 tmpreg = get_num (&opP->disp, 55);
2433 install_operand (s[1], tmpreg & 0x7f);
2434 break;
2435
2436 case 'l':
2437 tmpreg = opP->mask;
2438 if (s[1] == 'w')
2439 {
2440 if (tmpreg & 0x7FF0000)
2441 as_bad ("Floating point register in register list");
2442 insop (reverse_16_bits (tmpreg), opcode);
2443 }
2444 else
2445 {
2446 if (tmpreg & 0x700FFFF)
2447 as_bad ("Wrong register in floating-point reglist");
2448 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2449 }
2450 break;
2451
2452 case 'L':
2453 tmpreg = opP->mask;
2454 if (s[1] == 'w')
2455 {
2456 if (tmpreg & 0x7FF0000)
2457 as_bad ("Floating point register in register list");
2458 insop (tmpreg, opcode);
2459 }
2460 else if (s[1] == '8')
2461 {
2462 if (tmpreg & 0x0FFFFFF)
2463 as_bad ("incorrect register in reglist");
2464 install_operand (s[1], tmpreg >> 24);
2465 }
2466 else
2467 {
2468 if (tmpreg & 0x700FFFF)
2469 as_bad ("wrong register in floating-point reglist");
2470 else
2471 install_operand (s[1], tmpreg >> 16);
2472 }
2473 break;
2474
2475 case 'M':
2476 install_operand (s[1], get_num (&opP->disp, 60));
2477 break;
2478
2479 case 'O':
2480 tmpreg = ((opP->mode == DREG)
2481 ? 0x20 + opP->reg - DATA
2482 : (get_num (&opP->disp, 40) & 0x1F));
2483 install_operand (s[1], tmpreg);
2484 break;
2485
2486 case 'Q':
2487 tmpreg = get_num (&opP->disp, 10);
2488 if (tmpreg == 8)
2489 tmpreg = 0;
2490 install_operand (s[1], tmpreg);
2491 break;
2492
2493 case 'R':
2494 /* This depends on the fact that ADDR registers are eight
2495 more than their corresponding DATA regs, so the result
2496 will have the ADDR_REG bit set */
2497 install_operand (s[1], opP->reg - DATA);
2498 break;
2499
2500 case 'r':
2501 if (opP->mode == AINDR)
2502 install_operand (s[1], opP->reg - DATA);
2503 else
2504 install_operand (s[1], opP->index.reg - DATA);
2505 break;
2506
2507 case 's':
2508 if (opP->reg == FPI)
2509 tmpreg = 0x1;
2510 else if (opP->reg == FPS)
2511 tmpreg = 0x2;
2512 else if (opP->reg == FPC)
2513 tmpreg = 0x4;
2514 else
2515 abort ();
2516 install_operand (s[1], tmpreg);
2517 break;
2518
2519 case 'S': /* Ignore it */
2520 break;
2521
2522 case 'T':
2523 install_operand (s[1], get_num (&opP->disp, 30));
2524 break;
2525
2526 case 'U': /* Ignore it */
2527 break;
2528
2529 case 'c':
2530 switch (opP->reg)
2531 {
2532 case NC:
2533 tmpreg = 0;
2534 break;
2535 case DC:
2536 tmpreg = 1;
2537 break;
2538 case IC:
2539 tmpreg = 2;
2540 break;
2541 case BC:
2542 tmpreg = 3;
2543 break;
2544 default:
2545 as_fatal ("failed sanity check");
2546 } /* switch on cache token */
2547 install_operand (s[1], tmpreg);
2548 break;
2549 #ifndef NO_68851
2550 /* JF: These are out of order, I fear. */
2551 case 'f':
2552 switch (opP->reg)
2553 {
2554 case SFC:
2555 tmpreg = 0;
2556 break;
2557 case DFC:
2558 tmpreg = 1;
2559 break;
2560 default:
2561 abort ();
2562 }
2563 install_operand (s[1], tmpreg);
2564 break;
2565
2566 case '0':
2567 case '1':
2568 case '2':
2569 switch (opP->reg)
2570 {
2571 case TC:
2572 tmpreg = 0;
2573 break;
2574 case CAL:
2575 tmpreg = 4;
2576 break;
2577 case VAL:
2578 tmpreg = 5;
2579 break;
2580 case SCC:
2581 tmpreg = 6;
2582 break;
2583 case AC:
2584 tmpreg = 7;
2585 break;
2586 default:
2587 abort ();
2588 }
2589 install_operand (s[1], tmpreg);
2590 break;
2591
2592 case 'V':
2593 if (opP->reg == VAL)
2594 break;
2595 abort ();
2596
2597 case 'W':
2598 switch (opP->reg)
2599 {
2600 case DRP:
2601 tmpreg = 1;
2602 break;
2603 case SRP:
2604 tmpreg = 2;
2605 break;
2606 case CRP:
2607 tmpreg = 3;
2608 break;
2609 default:
2610 abort ();
2611 }
2612 install_operand (s[1], tmpreg);
2613 break;
2614
2615 case 'X':
2616 switch (opP->reg)
2617 {
2618 case BAD:
2619 case BAD + 1:
2620 case BAD + 2:
2621 case BAD + 3:
2622 case BAD + 4:
2623 case BAD + 5:
2624 case BAD + 6:
2625 case BAD + 7:
2626 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2627 break;
2628
2629 case BAC:
2630 case BAC + 1:
2631 case BAC + 2:
2632 case BAC + 3:
2633 case BAC + 4:
2634 case BAC + 5:
2635 case BAC + 6:
2636 case BAC + 7:
2637 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2638 break;
2639
2640 default:
2641 abort ();
2642 }
2643 install_operand (s[1], tmpreg);
2644 break;
2645 case 'Y':
2646 know (opP->reg == PSR);
2647 break;
2648 case 'Z':
2649 know (opP->reg == PCSR);
2650 break;
2651 #endif /* m68851 */
2652 case '3':
2653 switch (opP->reg)
2654 {
2655 case TT0:
2656 tmpreg = 2;
2657 break;
2658 case TT1:
2659 tmpreg = 3;
2660 break;
2661 default:
2662 abort ();
2663 }
2664 install_operand (s[1], tmpreg);
2665 break;
2666 case 't':
2667 tmpreg = get_num (&opP->disp, 20);
2668 install_operand (s[1], tmpreg);
2669 break;
2670 case '_': /* used only for move16 absolute 32-bit address */
2671 tmpreg = get_num (&opP->disp, 80);
2672 addword (tmpreg >> 16);
2673 addword (tmpreg & 0xFFFF);
2674 break;
2675 default:
2676 abort ();
2677 }
2678 }
2679
2680 /* By the time whe get here (FINALLY) the_ins contains the complete
2681 instruction, ready to be emitted. . . */
2682 }
2683
2684 static int
2685 reverse_16_bits (in)
2686 int in;
2687 {
2688 int out = 0;
2689 int n;
2690
2691 static int mask[16] =
2692 {
2693 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2694 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2695 };
2696 for (n = 0; n < 16; n++)
2697 {
2698 if (in & mask[n])
2699 out |= mask[15 - n];
2700 }
2701 return out;
2702 } /* reverse_16_bits() */
2703
2704 static int
2705 reverse_8_bits (in)
2706 int in;
2707 {
2708 int out = 0;
2709 int n;
2710
2711 static int mask[8] =
2712 {
2713 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2714 };
2715
2716 for (n = 0; n < 8; n++)
2717 {
2718 if (in & mask[n])
2719 out |= mask[7 - n];
2720 }
2721 return out;
2722 } /* reverse_8_bits() */
2723
2724 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2725 (that value is chosen in the frag_var call in md_assemble). TYPE
2726 is the subtype of the frag to be generated; its primary type is
2727 rs_machine_dependent.
2728
2729 The TYPE parameter is also used by md_convert_frag_1 and
2730 md_estimate_size_before_relax. The appropriate type of fixup will
2731 be emitted by md_convert_frag_1.
2732
2733 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2734 static void
2735 install_operand (mode, val)
2736 int mode;
2737 int val;
2738 {
2739 switch (mode)
2740 {
2741 case 's':
2742 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2743 break;
2744 case 'd':
2745 the_ins.opcode[0] |= val << 9;
2746 break;
2747 case '1':
2748 the_ins.opcode[1] |= val << 12;
2749 break;
2750 case '2':
2751 the_ins.opcode[1] |= val << 6;
2752 break;
2753 case '3':
2754 the_ins.opcode[1] |= val;
2755 break;
2756 case '4':
2757 the_ins.opcode[2] |= val << 12;
2758 break;
2759 case '5':
2760 the_ins.opcode[2] |= val << 6;
2761 break;
2762 case '6':
2763 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2764 three words long! */
2765 the_ins.numo++;
2766 the_ins.opcode[2] |= val;
2767 break;
2768 case '7':
2769 the_ins.opcode[1] |= val << 7;
2770 break;
2771 case '8':
2772 the_ins.opcode[1] |= val << 10;
2773 break;
2774 #ifndef NO_68851
2775 case '9':
2776 the_ins.opcode[1] |= val << 5;
2777 break;
2778 #endif
2779
2780 case 't':
2781 the_ins.opcode[1] |= (val << 10) | (val << 7);
2782 break;
2783 case 'D':
2784 the_ins.opcode[1] |= (val << 12) | val;
2785 break;
2786 case 'g':
2787 the_ins.opcode[0] |= val = 0xff;
2788 break;
2789 case 'i':
2790 the_ins.opcode[0] |= val << 9;
2791 break;
2792 case 'C':
2793 the_ins.opcode[1] |= val;
2794 break;
2795 case 'j':
2796 the_ins.opcode[1] |= val;
2797 the_ins.numo++; /* What a hack */
2798 break;
2799 case 'k':
2800 the_ins.opcode[1] |= val << 4;
2801 break;
2802 case 'b':
2803 case 'w':
2804 case 'W':
2805 case 'l':
2806 break;
2807 case 'e':
2808 the_ins.opcode[0] |= (val << 6);
2809 break;
2810 case 'L':
2811 the_ins.opcode[1] = (val >> 16);
2812 the_ins.opcode[2] = val & 0xffff;
2813 break;
2814 case 'c':
2815 default:
2816 as_fatal ("failed sanity check.");
2817 }
2818 } /* install_operand() */
2819
2820 static void
2821 install_gen_operand (mode, val)
2822 int mode;
2823 int val;
2824 {
2825 switch (mode)
2826 {
2827 case 's':
2828 the_ins.opcode[0] |= val;
2829 break;
2830 case 'd':
2831 /* This is a kludge!!! */
2832 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2833 break;
2834 case 'b':
2835 case 'w':
2836 case 'l':
2837 case 'f':
2838 case 'F':
2839 case 'x':
2840 case 'p':
2841 the_ins.opcode[0] |= val;
2842 break;
2843 /* more stuff goes here */
2844 default:
2845 as_fatal ("failed sanity check.");
2846 }
2847 } /* install_gen_operand() */
2848
2849 /*
2850 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2851 * then deal with the bitfield hack.
2852 */
2853
2854 static char *
2855 crack_operand (str, opP)
2856 register char *str;
2857 register struct m68k_op *opP;
2858 {
2859 register int parens;
2860 register int c;
2861 register char *beg_str;
2862 int inquote = 0;
2863
2864 if (!str)
2865 {
2866 return str;
2867 }
2868 beg_str = str;
2869 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2870 {
2871 if (! inquote)
2872 {
2873 if (*str == '(')
2874 parens++;
2875 else if (*str == ')')
2876 {
2877 if (!parens)
2878 { /* ERROR */
2879 opP->error = "Extra )";
2880 return str;
2881 }
2882 --parens;
2883 }
2884 }
2885 if (flag_mri && *str == '\'')
2886 inquote = ! inquote;
2887 }
2888 if (!*str && parens)
2889 { /* ERROR */
2890 opP->error = "Missing )";
2891 return str;
2892 }
2893 c = *str;
2894 *str = '\0';
2895 if (m68k_ip_op (beg_str, opP) != 0)
2896 {
2897 *str = c;
2898 return str;
2899 }
2900 *str = c;
2901 if (c == '}')
2902 c = *++str; /* JF bitfield hack */
2903 if (c)
2904 {
2905 c = *++str;
2906 if (!c)
2907 as_bad ("Missing operand");
2908 }
2909 return str;
2910 }
2911
2912 /* This is the guts of the machine-dependent assembler. STR points to a
2913 machine dependent instruction. This function is supposed to emit
2914 the frags/bytes it assembles to.
2915 */
2916
2917 void
2918 insert_reg (regname, regnum)
2919 char *regname;
2920 int regnum;
2921 {
2922 char buf[100];
2923 int i;
2924
2925 #ifdef REGISTER_PREFIX
2926 if (!flag_reg_prefix_optional)
2927 {
2928 buf[0] = REGISTER_PREFIX;
2929 strcpy (buf + 1, regname);
2930 regname = buf;
2931 }
2932 #endif
2933
2934 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2935 &zero_address_frag));
2936
2937 for (i = 0; regname[i]; i++)
2938 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2939 buf[i] = '\0';
2940
2941 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2942 &zero_address_frag));
2943 }
2944
2945 struct init_entry
2946 {
2947 const char *name;
2948 int number;
2949 };
2950
2951 static const struct init_entry init_table[] =
2952 {
2953 { "d0", DATA0 },
2954 { "d1", DATA1 },
2955 { "d2", DATA2 },
2956 { "d3", DATA3 },
2957 { "d4", DATA4 },
2958 { "d5", DATA5 },
2959 { "d6", DATA6 },
2960 { "d7", DATA7 },
2961 { "a0", ADDR0 },
2962 { "a1", ADDR1 },
2963 { "a2", ADDR2 },
2964 { "a3", ADDR3 },
2965 { "a4", ADDR4 },
2966 { "a5", ADDR5 },
2967 { "a6", ADDR6 },
2968 { "fp", ADDR6 },
2969 { "a7", ADDR7 },
2970 { "sp", ADDR7 },
2971 { "ssp", ADDR7 },
2972 { "fp0", FP0 },
2973 { "fp1", FP1 },
2974 { "fp2", FP2 },
2975 { "fp3", FP3 },
2976 { "fp4", FP4 },
2977 { "fp5", FP5 },
2978 { "fp6", FP6 },
2979 { "fp7", FP7 },
2980 { "fpi", FPI },
2981 { "fpiar", FPI },
2982 { "fpc", FPI },
2983 { "fps", FPS },
2984 { "fpsr", FPS },
2985 { "fpc", FPC },
2986 { "fpcr", FPC },
2987 { "control", FPC },
2988 { "status", FPS },
2989 { "iaddr", FPI },
2990
2991 { "cop0", COP0 },
2992 { "cop1", COP1 },
2993 { "cop2", COP2 },
2994 { "cop3", COP3 },
2995 { "cop4", COP4 },
2996 { "cop5", COP5 },
2997 { "cop6", COP6 },
2998 { "cop7", COP7 },
2999 { "pc", PC },
3000 { "zpc", ZPC },
3001 { "sr", SR },
3002
3003 { "ccr", CCR },
3004 { "cc", CCR },
3005
3006 /* control registers */
3007 { "sfc", SFC }, /* Source Function Code */
3008 { "sfcr", SFC },
3009 { "dfc", DFC }, /* Destination Function Code */
3010 { "dfcr", DFC },
3011 { "cacr", CACR }, /* Cache Control Register */
3012 { "caar", CAAR }, /* Cache Address Register */
3013
3014 { "usp", USP }, /* User Stack Pointer */
3015 { "vbr", VBR }, /* Vector Base Register */
3016 { "msp", MSP }, /* Master Stack Pointer */
3017 { "isp", ISP }, /* Interrupt Stack Pointer */
3018
3019 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3020 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3021 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3022 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3023
3024 /* 68ec040 versions of same */
3025 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3026 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3027 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3028 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3029
3030 /* mcf5200 versions of same */
3031 { "acr2", ITT0 }, /* Access Control Unit 2 */
3032 { "acr3", ITT1 }, /* Access Control Unit 3 */
3033 { "acr0", DTT0 }, /* Access Control Unit 0 */
3034 { "acr1", DTT1 }, /* Access Control Unit 1 */
3035
3036 { "tc", TC }, /* MMU Translation Control Register */
3037 { "tcr", TC },
3038
3039 { "mmusr", MMUSR }, /* MMU Status Register */
3040 { "srp", SRP }, /* User Root Pointer */
3041 { "urp", URP }, /* Supervisor Root Pointer */
3042
3043 { "buscr", BUSCR },
3044 { "pcr", PCR },
3045
3046 { "rombar", ROMBAR }, /* ROM Base Address Register */
3047 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3048 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3049 { "mbar", MBAR }, /* Module Base Address Register */
3050 /* end of control registers */
3051
3052 { "ac", AC },
3053 { "bc", BC },
3054 { "cal", CAL },
3055 { "crp", CRP },
3056 { "drp", DRP },
3057 { "pcsr", PCSR },
3058 { "psr", PSR },
3059 { "scc", SCC },
3060 { "val", VAL },
3061 { "bad0", BAD0 },
3062 { "bad1", BAD1 },
3063 { "bad2", BAD2 },
3064 { "bad3", BAD3 },
3065 { "bad4", BAD4 },
3066 { "bad5", BAD5 },
3067 { "bad6", BAD6 },
3068 { "bad7", BAD7 },
3069 { "bac0", BAC0 },
3070 { "bac1", BAC1 },
3071 { "bac2", BAC2 },
3072 { "bac3", BAC3 },
3073 { "bac4", BAC4 },
3074 { "bac5", BAC5 },
3075 { "bac6", BAC6 },
3076 { "bac7", BAC7 },
3077
3078 { "ic", IC },
3079 { "dc", DC },
3080 { "nc", NC },
3081
3082 { "tt0", TT0 },
3083 { "tt1", TT1 },
3084 /* 68ec030 versions of same */
3085 { "ac0", TT0 },
3086 { "ac1", TT1 },
3087 /* 68ec030 access control unit, identical to 030 MMU status reg */
3088 { "acusr", PSR },
3089
3090 /* Suppressed data and address registers. */
3091 { "zd0", ZDATA0 },
3092 { "zd1", ZDATA1 },
3093 { "zd2", ZDATA2 },
3094 { "zd3", ZDATA3 },
3095 { "zd4", ZDATA4 },
3096 { "zd5", ZDATA5 },
3097 { "zd6", ZDATA6 },
3098 { "zd7", ZDATA7 },
3099 { "za0", ZADDR0 },
3100 { "za1", ZADDR1 },
3101 { "za2", ZADDR2 },
3102 { "za3", ZADDR3 },
3103 { "za4", ZADDR4 },
3104 { "za5", ZADDR5 },
3105 { "za6", ZADDR6 },
3106 { "za7", ZADDR7 },
3107
3108 { 0, 0 }
3109 };
3110
3111 void
3112 init_regtable ()
3113 {
3114 int i;
3115 for (i = 0; init_table[i].name; i++)
3116 insert_reg (init_table[i].name, init_table[i].number);
3117 }
3118
3119 static int no_68851, no_68881;
3120
3121 #ifdef OBJ_AOUT
3122 /* a.out machine type. Default to 68020. */
3123 int m68k_aout_machtype = 2;
3124 #endif
3125
3126 void
3127 md_assemble (str)
3128 char *str;
3129 {
3130 const char *er;
3131 short *fromP;
3132 char *toP = NULL;
3133 int m, n = 0;
3134 char *to_beg_P;
3135 int shorts_this_frag;
3136 fixS *fixP;
3137
3138 /* In MRI mode, the instruction and operands are separated by a
3139 space. Anything following the operands is a comment. The label
3140 has already been removed. */
3141 if (flag_mri)
3142 {
3143 char *s;
3144 int fields = 0;
3145 int infield = 0;
3146 int inquote = 0;
3147
3148 for (s = str; *s != '\0'; s++)
3149 {
3150 if ((*s == ' ' || *s == '\t') && ! inquote)
3151 {
3152 if (infield)
3153 {
3154 ++fields;
3155 if (fields >= 2)
3156 {
3157 *s = '\0';
3158 break;
3159 }
3160 infield = 0;
3161 }
3162 }
3163 else
3164 {
3165 if (! infield)
3166 infield = 1;
3167 if (*s == '\'')
3168 inquote = ! inquote;
3169 }
3170 }
3171 }
3172
3173 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3174 m68k_ip (str);
3175 er = the_ins.error;
3176 if (!er)
3177 {
3178 for (n = 0; n < the_ins.numargs; n++)
3179 if (the_ins.operands[n].error)
3180 {
3181 er = the_ins.operands[n].error;
3182 break;
3183 }
3184 }
3185 if (er)
3186 {
3187 as_bad ("%s -- statement `%s' ignored", er, str);
3188 return;
3189 }
3190
3191 if (the_ins.nfrag == 0)
3192 {
3193 /* No frag hacking involved; just put it out */
3194 toP = frag_more (2 * the_ins.numo);
3195 fromP = &the_ins.opcode[0];
3196 for (m = the_ins.numo; m; --m)
3197 {
3198 md_number_to_chars (toP, (long) (*fromP), 2);
3199 toP += 2;
3200 fromP++;
3201 }
3202 /* put out symbol-dependent info */
3203 for (m = 0; m < the_ins.nrel; m++)
3204 {
3205 switch (the_ins.reloc[m].wid)
3206 {
3207 case 'B':
3208 n = 1;
3209 break;
3210 case 'b':
3211 n = 1;
3212 break;
3213 case '3':
3214 n = 2;
3215 break;
3216 case 'w':
3217 n = 2;
3218 break;
3219 case 'l':
3220 n = 4;
3221 break;
3222 default:
3223 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3224 the_ins.reloc[m].wid);
3225 }
3226
3227 fixP = fix_new_exp (frag_now,
3228 ((toP - frag_now->fr_literal)
3229 - the_ins.numo * 2 + the_ins.reloc[m].n),
3230 n,
3231 &the_ins.reloc[m].exp,
3232 the_ins.reloc[m].pcrel,
3233 get_reloc_code (n, the_ins.reloc[m].pcrel,
3234 the_ins.reloc[m].pic_reloc));
3235 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3236 }
3237 return;
3238 }
3239
3240 /* There's some frag hacking */
3241 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3242 {
3243 int wid;
3244
3245 if (n == 0)
3246 wid = 2 * the_ins.fragb[n].fragoff;
3247 else
3248 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3249 toP = frag_more (wid);
3250 to_beg_P = toP;
3251 shorts_this_frag = 0;
3252 for (m = wid / 2; m; --m)
3253 {
3254 md_number_to_chars (toP, (long) (*fromP), 2);
3255 toP += 2;
3256 fromP++;
3257 shorts_this_frag++;
3258 }
3259 for (m = 0; m < the_ins.nrel; m++)
3260 {
3261 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3262 {
3263 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3264 break;
3265 }
3266 wid = the_ins.reloc[m].wid;
3267 if (wid == 0)
3268 continue;
3269 the_ins.reloc[m].wid = 0;
3270 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3271
3272 fixP = fix_new_exp (frag_now,
3273 ((toP - frag_now->fr_literal)
3274 - the_ins.numo * 2 + the_ins.reloc[m].n),
3275 wid,
3276 &the_ins.reloc[m].exp,
3277 the_ins.reloc[m].pcrel,
3278 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3279 the_ins.reloc[m].pic_reloc));
3280 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3281 }
3282 (void) frag_var (rs_machine_dependent, 10, 0,
3283 (relax_substateT) (the_ins.fragb[n].fragty),
3284 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3285 }
3286 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3287 shorts_this_frag = 0;
3288 if (n)
3289 {
3290 toP = frag_more (n * sizeof (short));
3291 while (n--)
3292 {
3293 md_number_to_chars (toP, (long) (*fromP), 2);
3294 toP += 2;
3295 fromP++;
3296 shorts_this_frag++;
3297 }
3298 }
3299 for (m = 0; m < the_ins.nrel; m++)
3300 {
3301 int wid;
3302
3303 wid = the_ins.reloc[m].wid;
3304 if (wid == 0)
3305 continue;
3306 the_ins.reloc[m].wid = 0;
3307 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3308
3309 fixP = fix_new_exp (frag_now,
3310 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3311 - shorts_this_frag * 2),
3312 wid,
3313 &the_ins.reloc[m].exp,
3314 the_ins.reloc[m].pcrel,
3315 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3316 the_ins.reloc[m].pic_reloc));
3317 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3318 }
3319 }
3320
3321 void
3322 md_begin ()
3323 {
3324 /*
3325 * md_begin -- set up hash tables with 68000 instructions.
3326 * similar to what the vax assembler does. ---phr
3327 */
3328 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3329 a copy of it at runtime, adding in the information we want but isn't
3330 there. I think it'd be better to have an awk script hack the table
3331 at compile time. Or even just xstr the table and use it as-is. But
3332 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3333 names. */
3334
3335 register const struct m68k_opcode *ins;
3336 register struct m68k_incant *hack, *slak;
3337 register const char *retval = 0; /* empty string, or error msg text */
3338 register unsigned int i;
3339 register char c;
3340
3341 if (flag_mri)
3342 {
3343 flag_reg_prefix_optional = 1;
3344 m68k_abspcadd = 1;
3345 m68k_rel32 = 0;
3346 }
3347
3348 op_hash = hash_new ();
3349
3350 obstack_begin (&robyn, 4000);
3351 for (i = 0; i < m68k_numopcodes; i++)
3352 {
3353 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3354 do
3355 {
3356 ins = &m68k_opcodes[i];
3357 /* We *could* ignore insns that don't match our arch here
3358 but just leaving them out of the hash. */
3359 slak->m_operands = ins->args;
3360 slak->m_opnum = strlen (slak->m_operands) / 2;
3361 slak->m_arch = ins->arch;
3362 slak->m_opcode = ins->opcode;
3363 /* This is kludgey */
3364 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3365 if (i + 1 != m68k_numopcodes
3366 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3367 {
3368 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3369 i++;
3370 }
3371 else
3372 slak->m_next = 0;
3373 slak = slak->m_next;
3374 }
3375 while (slak);
3376
3377 retval = hash_insert (op_hash, ins->name, (char *) hack);
3378 if (retval)
3379 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3380 }
3381
3382 for (i = 0; i < m68k_numaliases; i++)
3383 {
3384 const char *name = m68k_opcode_aliases[i].primary;
3385 const char *alias = m68k_opcode_aliases[i].alias;
3386 PTR val = hash_find (op_hash, name);
3387 if (!val)
3388 as_fatal ("Internal Error: Can't find %s in hash table", name);
3389 retval = hash_insert (op_hash, alias, val);
3390 if (retval)
3391 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3392 }
3393
3394 /* In MRI mode, all unsized branches are variable sized. Normally,
3395 they are word sized. */
3396 if (flag_mri)
3397 {
3398 static struct m68k_opcode_alias mri_aliases[] =
3399 {
3400 { "bhi", "jhi", },
3401 { "bls", "jls", },
3402 { "bcc", "jcc", },
3403 { "bcs", "jcs", },
3404 { "bne", "jne", },
3405 { "beq", "jeq", },
3406 { "bvc", "jvc", },
3407 { "bvs", "jvs", },
3408 { "bpl", "jpl", },
3409 { "bmi", "jmi", },
3410 { "bge", "jge", },
3411 { "blt", "jlt", },
3412 { "bgt", "jgt", },
3413 { "ble", "jle", },
3414 { "bra", "jra", },
3415 { "bsr", "jbsr", },
3416 };
3417
3418 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3419 {
3420 const char *name = mri_aliases[i].primary;
3421 const char *alias = mri_aliases[i].alias;
3422 PTR val = hash_find (op_hash, name);
3423 if (!val)
3424 as_fatal ("Internal Error: Can't find %s in hash table", name);
3425 retval = hash_jam (op_hash, alias, val);
3426 if (retval)
3427 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3428 }
3429 }
3430
3431 for (i = 0; i < sizeof (mklower_table); i++)
3432 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3433
3434 for (i = 0; i < sizeof (notend_table); i++)
3435 {
3436 notend_table[i] = 0;
3437 alt_notend_table[i] = 0;
3438 }
3439 notend_table[','] = 1;
3440 notend_table['{'] = 1;
3441 notend_table['}'] = 1;
3442 alt_notend_table['a'] = 1;
3443 alt_notend_table['A'] = 1;
3444 alt_notend_table['d'] = 1;
3445 alt_notend_table['D'] = 1;
3446 alt_notend_table['#'] = 1;
3447 alt_notend_table['&'] = 1;
3448 alt_notend_table['f'] = 1;
3449 alt_notend_table['F'] = 1;
3450 #ifdef REGISTER_PREFIX
3451 alt_notend_table[REGISTER_PREFIX] = 1;
3452 #endif
3453
3454 /* We need to put '(' in alt_notend_table to handle
3455 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3456 */
3457 alt_notend_table['('] = 1;
3458
3459 /* We need to put '@' in alt_notend_table to handle
3460 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3461 */
3462 alt_notend_table['@'] = 1;
3463
3464 /* We need to put digits in alt_notend_table to handle
3465 bfextu %d0{24:1},%d0
3466 */
3467 alt_notend_table['0'] = 1;
3468 alt_notend_table['1'] = 1;
3469 alt_notend_table['2'] = 1;
3470 alt_notend_table['3'] = 1;
3471 alt_notend_table['4'] = 1;
3472 alt_notend_table['5'] = 1;
3473 alt_notend_table['6'] = 1;
3474 alt_notend_table['7'] = 1;
3475 alt_notend_table['8'] = 1;
3476 alt_notend_table['9'] = 1;
3477
3478 #ifndef MIT_SYNTAX_ONLY
3479 /* Insert pseudo ops, these have to go into the opcode table since
3480 gas expects pseudo ops to start with a dot */
3481 {
3482 int n = 0;
3483 while (mote_pseudo_table[n].poc_name)
3484 {
3485 hack = (struct m68k_incant *)
3486 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3487 hash_insert (op_hash,
3488 mote_pseudo_table[n].poc_name, (char *) hack);
3489 hack->m_operands = 0;
3490 hack->m_opnum = n;
3491 n++;
3492 }
3493 }
3494 #endif
3495
3496 init_regtable ();
3497
3498 #ifdef OBJ_ELF
3499 record_alignment (text_section, 2);
3500 record_alignment (data_section, 2);
3501 record_alignment (bss_section, 2);
3502 #endif
3503 }
3504
3505 void
3506 m68k_init_after_args ()
3507 {
3508 if (cpu_of_arch (current_architecture) == 0)
3509 {
3510 int i;
3511 const char *default_cpu = TARGET_CPU;
3512
3513 if (*default_cpu == 'm')
3514 default_cpu++;
3515 for (i = 0; i < n_archs; i++)
3516 if (strcasecmp (default_cpu, archs[i].name) == 0)
3517 break;
3518 if (i == n_archs)
3519 {
3520 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3521 current_architecture |= m68020;
3522 }
3523 else
3524 current_architecture |= archs[i].arch;
3525 }
3526 /* Permit m68881 specification with all cpus; those that can't work
3527 with a coprocessor could be doing emulation. */
3528 if (current_architecture & m68851)
3529 {
3530 if (current_architecture & m68040)
3531 {
3532 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3533 }
3534 }
3535 /* What other incompatibilities could we check for? */
3536
3537 /* Toss in some default assumptions about coprocessors. */
3538 if (!no_68881
3539 && (cpu_of_arch (current_architecture)
3540 /* Can CPU32 have a 68881 coprocessor?? */
3541 & (m68020 | m68030 | cpu32)))
3542 {
3543 current_architecture |= m68881;
3544 }
3545 if (!no_68851
3546 && (cpu_of_arch (current_architecture) & m68020up) != 0
3547 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3548 {
3549 current_architecture |= m68851;
3550 }
3551 if (no_68881 && (current_architecture & m68881))
3552 as_bad ("options for 68881 and no-68881 both given");
3553 if (no_68851 && (current_architecture & m68851))
3554 as_bad ("options for 68851 and no-68851 both given");
3555
3556 #ifdef OBJ_AOUT
3557 /* Work out the magic number. This isn't very general. */
3558 if (current_architecture & m68000)
3559 m68k_aout_machtype = 0;
3560 else if (current_architecture & m68010)
3561 m68k_aout_machtype = 1;
3562 else if (current_architecture & m68020)
3563 m68k_aout_machtype = 2;
3564 else
3565 m68k_aout_machtype = 2;
3566 #endif
3567
3568 /* Note which set of "movec" control registers is available. */
3569 switch (cpu_of_arch (current_architecture))
3570 {
3571 case m68000:
3572 control_regs = m68000_control_regs;
3573 break;
3574 case m68010:
3575 control_regs = m68010_control_regs;
3576 break;
3577 case m68020:
3578 case m68030:
3579 control_regs = m68020_control_regs;
3580 break;
3581 case m68040:
3582 control_regs = m68040_control_regs;
3583 break;
3584 case m68060:
3585 control_regs = m68060_control_regs;
3586 break;
3587 case cpu32:
3588 control_regs = cpu32_control_regs;
3589 break;
3590 case mcf5200:
3591 control_regs = mcf5200_control_regs;
3592 break;
3593 default:
3594 abort ();
3595 }
3596
3597 if (cpu_of_arch (current_architecture) < m68020)
3598 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3599 }
3600
3601 /* This is called if we go in or out of MRI mode because of the .mri
3602 pseudo-op. */
3603
3604 void
3605 m68k_mri_mode_change (on)
3606 int on;
3607 {
3608 if (on)
3609 {
3610 if (! flag_reg_prefix_optional)
3611 {
3612 flag_reg_prefix_optional = 1;
3613 #ifdef REGISTER_PREFIX
3614 init_regtable ();
3615 #endif
3616 }
3617 m68k_abspcadd = 1;
3618 m68k_rel32 = 0;
3619 }
3620 else
3621 {
3622 if (! reg_prefix_optional_seen)
3623 {
3624 #ifdef REGISTER_PREFIX_OPTIONAL
3625 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
3626 #else
3627 flag_reg_prefix_optional = 0;
3628 #endif
3629 #ifdef REGISTER_PREFIX
3630 init_regtable ();
3631 #endif
3632 }
3633 m68k_abspcadd = 0;
3634 m68k_rel32 = 1;
3635 }
3636 }
3637
3638 /* Equal to MAX_PRECISION in atof-ieee.c */
3639 #define MAX_LITTLENUMS 6
3640
3641 /* Turn a string in input_line_pointer into a floating point constant
3642 of type type, and store the appropriate bytes in *litP. The number
3643 of LITTLENUMS emitted is stored in *sizeP . An error message is
3644 returned, or NULL on OK. */
3645
3646 char *
3647 md_atof (type, litP, sizeP)
3648 char type;
3649 char *litP;
3650 int *sizeP;
3651 {
3652 int prec;
3653 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3654 LITTLENUM_TYPE *wordP;
3655 char *t;
3656 char *atof_ieee ();
3657
3658 switch (type)
3659 {
3660 case 'f':
3661 case 'F':
3662 case 's':
3663 case 'S':
3664 prec = 2;
3665 break;
3666
3667 case 'd':
3668 case 'D':
3669 case 'r':
3670 case 'R':
3671 prec = 4;
3672 break;
3673
3674 case 'x':
3675 case 'X':
3676 prec = 6;
3677 break;
3678
3679 case 'p':
3680 case 'P':
3681 prec = 6;
3682 break;
3683
3684 default:
3685 *sizeP = 0;
3686 return "Bad call to MD_ATOF()";
3687 }
3688 t = atof_ieee (input_line_pointer, type, words);
3689 if (t)
3690 input_line_pointer = t;
3691
3692 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3693 for (wordP = words; prec--;)
3694 {
3695 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3696 litP += sizeof (LITTLENUM_TYPE);
3697 }
3698 return 0;
3699 }
3700
3701 void
3702 md_number_to_chars (buf, val, n)
3703 char *buf;
3704 valueT val;
3705 int n;
3706 {
3707 number_to_chars_bigendian (buf, val, n);
3708 }
3709
3710 static void
3711 md_apply_fix_2 (fixP, val)
3712 fixS *fixP;
3713 offsetT val;
3714 {
3715 addressT upper_limit;
3716 offsetT lower_limit;
3717
3718 /* This is unnecessary but it convinces the native rs6000 compiler
3719 to generate the code we want. */
3720 char *buf = fixP->fx_frag->fr_literal;
3721 buf += fixP->fx_where;
3722 /* end ibm compiler workaround */
3723
3724 if (val & 0x80000000)
3725 val |= ~(addressT)0x7fffffff;
3726 else
3727 val &= 0x7fffffff;
3728
3729 #ifdef OBJ_ELF
3730 if (fixP->fx_addsy)
3731 {
3732 memset (buf, 0, fixP->fx_size);
3733 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3734 return;
3735 }
3736 #endif
3737
3738 switch (fixP->fx_size)
3739 {
3740 /* The cast to offsetT below are necessary to make code correct for
3741 machines where ints are smaller than offsetT */
3742 case 1:
3743 *buf++ = val;
3744 upper_limit = 0x7f;
3745 lower_limit = - (offsetT) 0x80;
3746 break;
3747 case 2:
3748 *buf++ = (val >> 8);
3749 *buf++ = val;
3750 upper_limit = 0x7fff;
3751 lower_limit = - (offsetT) 0x8000;
3752 break;
3753 case 4:
3754 *buf++ = (val >> 24);
3755 *buf++ = (val >> 16);
3756 *buf++ = (val >> 8);
3757 *buf++ = val;
3758 upper_limit = 0x7fffffff;
3759 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3760 break;
3761 default:
3762 BAD_CASE (fixP->fx_size);
3763 }
3764
3765 /* Fix up a negative reloc. */
3766 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3767 {
3768 fixP->fx_addsy = fixP->fx_subsy;
3769 fixP->fx_subsy = NULL;
3770 fixP->fx_tcbit = 1;
3771 }
3772
3773 /* For non-pc-relative values, it's conceivable we might get something
3774 like "0xff" for a byte field. So extend the upper part of the range
3775 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3776 so that we can do any range checking at all. */
3777 if (!fixP->fx_pcrel)
3778 upper_limit = upper_limit * 2 + 1;
3779
3780 if ((addressT) val > upper_limit
3781 && (val > 0 || val < lower_limit))
3782 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3783
3784 /* A one byte PC-relative reloc means a short branch. We can't use
3785 a short branch with a value of 0 or -1, because those indicate
3786 different opcodes (branches with longer offsets). */
3787 if (fixP->fx_pcrel
3788 && fixP->fx_size == 1
3789 && (fixP->fx_addsy == NULL
3790 || S_IS_DEFINED (fixP->fx_addsy))
3791 && (val == 0 || val == -1))
3792 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3793 }
3794
3795 #ifdef BFD_ASSEMBLER
3796 int
3797 md_apply_fix (fixP, valp)
3798 fixS *fixP;
3799 valueT *valp;
3800 {
3801 md_apply_fix_2 (fixP, (addressT) *valp);
3802 return 1;
3803 }
3804 #else
3805 void md_apply_fix (fixP, val)
3806 fixS *fixP;
3807 long val;
3808 {
3809 md_apply_fix_2 (fixP, (addressT) val);
3810 }
3811 #endif
3812
3813 /* *fragP has been relaxed to its final size, and now needs to have
3814 the bytes inside it modified to conform to the new size There is UGLY
3815 MAGIC here. ..
3816 */
3817 void
3818 md_convert_frag_1 (fragP)
3819 register fragS *fragP;
3820 {
3821 long disp;
3822 long ext = 0;
3823 fixS *fixP;
3824
3825 /* Address in object code of the displacement. */
3826 register int object_address = fragP->fr_fix + fragP->fr_address;
3827
3828 /* Address in gas core of the place to store the displacement. */
3829 /* This convinces the native rs6000 compiler to generate the code we
3830 want. */
3831 register char *buffer_address = fragP->fr_literal;
3832 buffer_address += fragP->fr_fix;
3833 /* end ibm compiler workaround */
3834
3835 /* The displacement of the address, from current location. */
3836 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3837 disp = (disp + fragP->fr_offset) - object_address;
3838
3839 #ifdef BFD_ASSEMBLER
3840 disp += fragP->fr_symbol->sy_frag->fr_address;
3841 #endif
3842
3843 switch (fragP->fr_subtype)
3844 {
3845 case TAB (BCC68000, BYTE):
3846 case TAB (ABRANCH, BYTE):
3847 know (issbyte (disp));
3848 if (disp == 0)
3849 as_bad ("short branch with zero offset: use :w");
3850 fragP->fr_opcode[1] = disp;
3851 ext = 0;
3852 break;
3853 case TAB (DBCC, SHORT):
3854 know (issword (disp));
3855 ext = 2;
3856 break;
3857 case TAB (BCC68000, SHORT):
3858 case TAB (ABRANCH, SHORT):
3859 know (issword (disp));
3860 fragP->fr_opcode[1] = 0x00;
3861 ext = 2;
3862 break;
3863 case TAB (ABRANCH, LONG):
3864 if (cpu_of_arch (current_architecture) < m68020)
3865 {
3866 if (fragP->fr_opcode[0] == 0x61)
3867 /* BSR */
3868 {
3869 fragP->fr_opcode[0] = 0x4E;
3870 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3871
3872 fix_new (fragP,
3873 fragP->fr_fix,
3874 4,
3875 fragP->fr_symbol,
3876 fragP->fr_offset,
3877 0,
3878 NO_RELOC);
3879
3880 fragP->fr_fix += 4;
3881 ext = 0;
3882 }
3883 /* BRA */
3884 else if (fragP->fr_opcode[0] == 0x60)
3885 {
3886 fragP->fr_opcode[0] = 0x4E;
3887 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3888 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3889 fragP->fr_offset, 0, NO_RELOC);
3890 fragP->fr_fix += 4;
3891 ext = 0;
3892 }
3893 else
3894 {
3895 as_bad ("Long branch offset not supported.");
3896 }
3897 }
3898 else
3899 {
3900 fragP->fr_opcode[1] = (char) 0xff;
3901 ext = 4;
3902 }
3903 break;
3904 case TAB (BCC68000, LONG):
3905 /* only Bcc 68000 instructions can come here */
3906 /* change bcc into b!cc/jmp absl long */
3907 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3908 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3909
3910 /* JF: these used to be fr_opcode[2,3], but they may be in a
3911 different frag, in which case refering to them is a no-no.
3912 Only fr_opcode[0,1] are guaranteed to work. */
3913 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3914 *buffer_address++ = (char) 0xf9;
3915 fragP->fr_fix += 2; /* account for jmp instruction */
3916 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3917 fragP->fr_offset, 0, NO_RELOC);
3918 fragP->fr_fix += 4;
3919 ext = 0;
3920 break;
3921 case TAB (DBCC, LONG):
3922 /* only DBcc 68000 instructions can come here */
3923 /* change dbcc into dbcc/jmp absl long */
3924 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3925 *buffer_address++ = 0x00; /* branch offset = 4 */
3926 *buffer_address++ = 0x04;
3927 *buffer_address++ = 0x60; /* put in bra pc+6 */
3928 *buffer_address++ = 0x06;
3929 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3930 *buffer_address++ = (char) 0xf9;
3931
3932 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3933 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3934 fragP->fr_offset, 0, NO_RELOC);
3935 fragP->fr_fix += 4;
3936 ext = 0;
3937 break;
3938 case TAB (FBRANCH, SHORT):
3939 know ((fragP->fr_opcode[1] & 0x40) == 0);
3940 ext = 2;
3941 break;
3942 case TAB (FBRANCH, LONG):
3943 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3944 ext = 4;
3945 break;
3946 case TAB (PCREL, SHORT):
3947 ext = 2;
3948 break;
3949 case TAB (PCREL, LONG):
3950 /* The thing to do here is force it to ABSOLUTE LONG, since
3951 PCREL is really trying to shorten an ABSOLUTE address anyway */
3952 /* JF FOO This code has not been tested */
3953 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3954 0, NO_RELOC);
3955 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3956 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3957 (unsigned) fragP->fr_opcode[0],
3958 (unsigned long) fragP->fr_address);
3959 fragP->fr_opcode[1] &= ~0x3F;
3960 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3961 fragP->fr_fix += 4;
3962 ext = 0;
3963 break;
3964 case TAB (PCLEA, SHORT):
3965 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3966 fragP->fr_offset, 1, NO_RELOC);
3967 fragP->fr_opcode[1] &= ~0x3F;
3968 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3969 ext = 2;
3970 break;
3971 case TAB (PCLEA, LONG):
3972 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3973 fragP->fr_offset, 1, NO_RELOC);
3974 fixP->fx_pcrel_adjust = 2;
3975 /* Already set to mode 7.3; this indicates: PC indirect with
3976 suppressed index, 32-bit displacement. */
3977 *buffer_address++ = 0x01;
3978 *buffer_address++ = 0x70;
3979 fragP->fr_fix += 2;
3980 ext = 4;
3981 break;
3982
3983 case TAB (PCINDEX, BYTE):
3984 disp += 2;
3985 if (!issbyte (disp))
3986 {
3987 as_bad ("displacement doesn't fit in one byte");
3988 disp = 0;
3989 }
3990 assert (fragP->fr_fix >= 2);
3991 buffer_address[-2] &= ~1;
3992 buffer_address[-1] = disp;
3993 ext = 0;
3994 break;
3995 case TAB (PCINDEX, SHORT):
3996 disp += 2;
3997 assert (issword (disp));
3998 assert (fragP->fr_fix >= 2);
3999 buffer_address[-2] |= 0x1;
4000 buffer_address[-1] = 0x20;
4001 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4002 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4003 NO_RELOC);
4004 fixP->fx_pcrel_adjust = 2;
4005 ext = 2;
4006 break;
4007 case TAB (PCINDEX, LONG):
4008 disp += 2;
4009 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4010 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
4011 NO_RELOC);
4012 fixP->fx_pcrel_adjust = 2;
4013 assert (fragP->fr_fix >= 2);
4014 buffer_address[-2] |= 0x1;
4015 buffer_address[-1] = 0x30;
4016 ext = 4;
4017 break;
4018 }
4019
4020 if (ext)
4021 {
4022 md_number_to_chars (buffer_address, (long) disp, (int) ext);
4023 fragP->fr_fix += ext;
4024 }
4025 }
4026
4027 #ifndef BFD_ASSEMBLER
4028
4029 void
4030 md_convert_frag (headers, sec, fragP)
4031 object_headers *headers;
4032 segT sec;
4033 fragS *fragP;
4034 {
4035 md_convert_frag_1 (fragP);
4036 }
4037
4038 #else
4039
4040 void
4041 md_convert_frag (abfd, sec, fragP)
4042 bfd *abfd;
4043 segT sec;
4044 fragS *fragP;
4045 {
4046 md_convert_frag_1 (fragP);
4047 }
4048 #endif
4049
4050 /* Force truly undefined symbols to their maximum size, and generally set up
4051 the frag list to be relaxed
4052 */
4053 int
4054 md_estimate_size_before_relax (fragP, segment)
4055 register fragS *fragP;
4056 segT segment;
4057 {
4058 int old_fix;
4059 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
4060
4061 old_fix = fragP->fr_fix;
4062
4063 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
4064 switch (fragP->fr_subtype)
4065 {
4066
4067 case TAB (ABRANCH, SZ_UNDEF):
4068 {
4069 if ((fragP->fr_symbol != NULL) /* Not absolute */
4070 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4071 {
4072 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4073 break;
4074 }
4075 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
4076 {
4077 /* On 68000, or for absolute value, switch to abs long */
4078 /* FIXME, we should check abs val, pick short or long */
4079 if (fragP->fr_opcode[0] == 0x61)
4080 {
4081 fragP->fr_opcode[0] = 0x4E;
4082 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
4083 fix_new (fragP, fragP->fr_fix, 4,
4084 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4085 fragP->fr_fix += 4;
4086 frag_wane (fragP);
4087 }
4088 else if (fragP->fr_opcode[0] == 0x60)
4089 {
4090 fragP->fr_opcode[0] = 0x4E;
4091 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
4092 fix_new (fragP, fragP->fr_fix, 4,
4093 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
4094 fragP->fr_fix += 4;
4095 frag_wane (fragP);
4096 }
4097 else
4098 {
4099 as_warn ("Long branch offset to extern symbol not supported.");
4100 }
4101 }
4102 else
4103 { /* Symbol is still undefined. Make it simple */
4104 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4105 fragP->fr_offset, 1, NO_RELOC);
4106 fragP->fr_fix += 4;
4107 fragP->fr_opcode[1] = (char) 0xff;
4108 frag_wane (fragP);
4109 break;
4110 }
4111
4112 break;
4113 } /* case TAB(ABRANCH,SZ_UNDEF) */
4114
4115 case TAB (FBRANCH, SZ_UNDEF):
4116 {
4117 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
4118 {
4119 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4120 fragP->fr_var += 2;
4121 }
4122 else
4123 {
4124 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
4125 fragP->fr_offset, 1, NO_RELOC);
4126 fragP->fr_fix += 4;
4127 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4128 frag_wane (fragP);
4129 }
4130 break;
4131 } /* TAB(FBRANCH,SZ_UNDEF) */
4132
4133 case TAB (PCREL, SZ_UNDEF):
4134 {
4135 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4136 || flag_short_refs
4137 || cpu_of_arch (current_architecture) < m68020)
4138 {
4139 fragP->fr_subtype = TAB (PCREL, SHORT);
4140 fragP->fr_var += 2;
4141 }
4142 else
4143 {
4144 fragP->fr_subtype = TAB (PCREL, LONG);
4145 fragP->fr_var += 4;
4146 }
4147 break;
4148 } /* TAB(PCREL,SZ_UNDEF) */
4149
4150 case TAB (BCC68000, SZ_UNDEF):
4151 {
4152 if ((fragP->fr_symbol != NULL)
4153 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4154 {
4155 fragP->fr_subtype = TAB (BCC68000, BYTE);
4156 break;
4157 }
4158 /* only Bcc 68000 instructions can come here */
4159 /* change bcc into b!cc/jmp absl long */
4160 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4161 if (flag_short_refs)
4162 {
4163 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4164 /* JF: these were fr_opcode[2,3] */
4165 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4166 buffer_address[1] = (char) 0xf8;
4167 fragP->fr_fix += 2; /* account for jmp instruction */
4168 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4169 fragP->fr_offset, 0, NO_RELOC);
4170 fragP->fr_fix += 2;
4171 }
4172 else
4173 {
4174 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4175 /* JF: these were fr_opcode[2,3] */
4176 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4177 buffer_address[1] = (char) 0xf9;
4178 fragP->fr_fix += 2; /* account for jmp instruction */
4179 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4180 fragP->fr_offset, 0, NO_RELOC);
4181 fragP->fr_fix += 4;
4182 }
4183 frag_wane (fragP);
4184 break;
4185 } /* case TAB(BCC68000,SZ_UNDEF) */
4186
4187 case TAB (DBCC, SZ_UNDEF):
4188 {
4189 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4190 {
4191 fragP->fr_subtype = TAB (DBCC, SHORT);
4192 fragP->fr_var += 2;
4193 break;
4194 }
4195 /* only DBcc 68000 instructions can come here */
4196 /* change dbcc into dbcc/jmp absl long */
4197 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4198 buffer_address[0] = 0x00; /* branch offset = 4 */
4199 buffer_address[1] = 0x04;
4200 buffer_address[2] = 0x60; /* put in bra pc + ... */
4201
4202 if (flag_short_refs)
4203 {
4204 /* JF: these were fr_opcode[5-7] */
4205 buffer_address[3] = 0x04; /* plus 4 */
4206 buffer_address[4] = 0x4e; /* Put in Jump Word */
4207 buffer_address[5] = (char) 0xf8;
4208 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4209 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4210 fragP->fr_offset, 0, NO_RELOC);
4211 fragP->fr_fix += 2;
4212 }
4213 else
4214 {
4215 /* JF: these were fr_opcode[5-7] */
4216 buffer_address[3] = 0x06; /* Plus 6 */
4217 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4218 buffer_address[5] = (char) 0xf9;
4219 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4220 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4221 fragP->fr_offset, 0, NO_RELOC);
4222 fragP->fr_fix += 4;
4223 }
4224
4225 frag_wane (fragP);
4226 break;
4227 } /* case TAB(DBCC,SZ_UNDEF) */
4228
4229 case TAB (PCLEA, SZ_UNDEF):
4230 {
4231 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4232 || flag_short_refs
4233 || cpu_of_arch (current_architecture) < m68020)
4234 {
4235 fragP->fr_subtype = TAB (PCLEA, SHORT);
4236 fragP->fr_var += 2;
4237 }
4238 else
4239 {
4240 fragP->fr_subtype = TAB (PCLEA, LONG);
4241 fragP->fr_var += 6;
4242 }
4243 break;
4244 } /* TAB(PCLEA,SZ_UNDEF) */
4245
4246 case TAB (PCINDEX, SZ_UNDEF):
4247 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4248 || cpu_of_arch (current_architecture) < m68020)
4249 {
4250 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4251 }
4252 else
4253 {
4254 fragP->fr_subtype = TAB (PCINDEX, LONG);
4255 fragP->fr_var += 4;
4256 }
4257 break;
4258
4259 default:
4260 break;
4261 }
4262
4263 /* now that SZ_UNDEF are taken care of, check others */
4264 switch (fragP->fr_subtype)
4265 {
4266 case TAB (BCC68000, BYTE):
4267 case TAB (ABRANCH, BYTE):
4268 /* We can't do a short jump to the next instruction, so in that
4269 case we force word mode. At this point S_GET_VALUE should
4270 return the offset of the symbol within its frag. If the
4271 symbol is at the start of a frag, and it is the next frag
4272 with any data in it (usually this is just the next frag, but
4273 assembler listings may introduce empty frags), we must use
4274 word mode. */
4275 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4276 {
4277 fragS *l;
4278
4279 for (l = fragP->fr_next;
4280 l != fragP->fr_symbol->sy_frag;
4281 l = l->fr_next)
4282 if (l->fr_fix + l->fr_var != 0)
4283 break;
4284 if (l == fragP->fr_symbol->sy_frag)
4285 {
4286 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4287 fragP->fr_var += 2;
4288 }
4289 }
4290 break;
4291 default:
4292 break;
4293 }
4294 return fragP->fr_var + fragP->fr_fix - old_fix;
4295 }
4296
4297 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4298 /* the bit-field entries in the relocation_info struct plays hell
4299 with the byte-order problems of cross-assembly. So as a hack,
4300 I added this mach. dependent ri twiddler. Ugly, but it gets
4301 you there. -KWK */
4302 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4303 are symbolnum, most sig. byte first. Last byte is broken up with
4304 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4305 nibble as nuthin. (on Sun 3 at least) */
4306 /* Translate the internal relocation information into target-specific
4307 format. */
4308 #ifdef comment
4309 void
4310 md_ri_to_chars (the_bytes, ri)
4311 char *the_bytes;
4312 struct reloc_info_generic *ri;
4313 {
4314 /* this is easy */
4315 md_number_to_chars (the_bytes, ri->r_address, 4);
4316 /* now the fun stuff */
4317 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4318 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4319 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4320 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4321 ((ri->r_extern << 4) & 0x10));
4322 }
4323
4324 #endif /* comment */
4325
4326 #ifndef BFD_ASSEMBLER
4327 void
4328 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4329 char *where;
4330 fixS *fixP;
4331 relax_addressT segment_address_in_file;
4332 {
4333 /*
4334 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4335 * Out: GNU LD relocation length code: 0, 1, or 2.
4336 */
4337
4338 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4339 long r_symbolnum;
4340
4341 know (fixP->fx_addsy != NULL);
4342
4343 md_number_to_chars (where,
4344 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4345 4);
4346
4347 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4348 ? S_GET_TYPE (fixP->fx_addsy)
4349 : fixP->fx_addsy->sy_number);
4350
4351 where[4] = (r_symbolnum >> 16) & 0x0ff;
4352 where[5] = (r_symbolnum >> 8) & 0x0ff;
4353 where[6] = r_symbolnum & 0x0ff;
4354 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4355 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4356 }
4357 #endif
4358
4359 #endif /* OBJ_AOUT or OBJ_BOUT */
4360
4361 #ifndef WORKING_DOT_WORD
4362 CONST int md_short_jump_size = 4;
4363 CONST int md_long_jump_size = 6;
4364
4365 void
4366 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4367 char *ptr;
4368 addressT from_addr, to_addr;
4369 fragS *frag;
4370 symbolS *to_symbol;
4371 {
4372 valueT offset;
4373
4374 offset = to_addr - (from_addr + 2);
4375
4376 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4377 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4378 }
4379
4380 void
4381 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4382 char *ptr;
4383 addressT from_addr, to_addr;
4384 fragS *frag;
4385 symbolS *to_symbol;
4386 {
4387 valueT offset;
4388
4389 if (cpu_of_arch (current_architecture) < m68020)
4390 {
4391 offset = to_addr - S_GET_VALUE (to_symbol);
4392 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4393 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4394 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4395 0, NO_RELOC);
4396 }
4397 else
4398 {
4399 offset = to_addr - (from_addr + 2);
4400 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4401 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4402 }
4403 }
4404
4405 #endif
4406
4407 /* Different values of OK tell what its OK to return. Things that
4408 aren't OK are an error (what a shock, no?)
4409
4410 0: Everything is OK
4411 10: Absolute 1:8 only
4412 20: Absolute 0:7 only
4413 30: absolute 0:15 only
4414 40: Absolute 0:31 only
4415 50: absolute 0:127 only
4416 55: absolute -64:63 only
4417 60: absolute -128:127 only
4418 70: absolute 0:4095 only
4419 80: No bignums
4420
4421 */
4422
4423 static int
4424 get_num (exp, ok)
4425 struct m68k_exp *exp;
4426 int ok;
4427 {
4428 if (exp->exp.X_op == O_absent)
4429 {
4430 /* Do the same thing the VAX asm does */
4431 op (exp) = O_constant;
4432 adds (exp) = 0;
4433 subs (exp) = 0;
4434 offs (exp) = 0;
4435 if (ok == 10)
4436 {
4437 as_warn ("expression out of range: defaulting to 1");
4438 offs (exp) = 1;
4439 }
4440 }
4441 else if (exp->exp.X_op == O_constant)
4442 {
4443 switch (ok)
4444 {
4445 case 10:
4446 if (offs (exp) < 1 || offs (exp) > 8)
4447 {
4448 as_warn ("expression out of range: defaulting to 1");
4449 offs (exp) = 1;
4450 }
4451 break;
4452 case 20:
4453 if (offs (exp) < 0 || offs (exp) > 7)
4454 goto outrange;
4455 break;
4456 case 30:
4457 if (offs (exp) < 0 || offs (exp) > 15)
4458 goto outrange;
4459 break;
4460 case 40:
4461 if (offs (exp) < 0 || offs (exp) > 32)
4462 goto outrange;
4463 break;
4464 case 50:
4465 if (offs (exp) < 0 || offs (exp) > 127)
4466 goto outrange;
4467 break;
4468 case 55:
4469 if (offs (exp) < -64 || offs (exp) > 63)
4470 goto outrange;
4471 break;
4472 case 60:
4473 if (offs (exp) < -128 || offs (exp) > 127)
4474 goto outrange;
4475 break;
4476 case 70:
4477 if (offs (exp) < 0 || offs (exp) > 4095)
4478 {
4479 outrange:
4480 as_warn ("expression out of range: defaulting to 0");
4481 offs (exp) = 0;
4482 }
4483 break;
4484 default:
4485 break;
4486 }
4487 }
4488 else if (exp->exp.X_op == O_big)
4489 {
4490 if (offs (exp) <= 0 /* flonum */
4491 && (ok == 80 /* no bignums */
4492 || (ok > 10 /* small-int ranges including 0 ok */
4493 /* If we have a flonum zero, a zero integer should
4494 do as well (e.g., in moveq). */
4495 && generic_floating_point_number.exponent == 0
4496 && generic_floating_point_number.low[0] == 0)))
4497 {
4498 /* HACK! Turn it into a long */
4499 LITTLENUM_TYPE words[6];
4500
4501 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4502 op (exp) = O_constant;
4503 adds (exp) = 0;
4504 subs (exp) = 0;
4505 offs (exp) = words[1] | (words[0] << 16);
4506 }
4507 else if (ok != 0)
4508 {
4509 op (exp) = O_constant;
4510 adds (exp) = 0;
4511 subs (exp) = 0;
4512 offs (exp) = (ok == 10) ? 1 : 0;
4513 as_warn ("Can't deal with expression; defaulting to %ld",
4514 offs (exp));
4515 }
4516 }
4517 else
4518 {
4519 if (ok >= 10 && ok <= 70)
4520 {
4521 op (exp) = O_constant;
4522 adds (exp) = 0;
4523 subs (exp) = 0;
4524 offs (exp) = (ok == 10) ? 1 : 0;
4525 as_warn ("Can't deal with expression; defaulting to %ld",
4526 offs (exp));
4527 }
4528 }
4529
4530 if (exp->size != SIZE_UNSPEC)
4531 {
4532 switch (exp->size)
4533 {
4534 case SIZE_UNSPEC:
4535 case SIZE_LONG:
4536 break;
4537 case SIZE_BYTE:
4538 if (!isbyte (offs (exp)))
4539 as_warn ("expression doesn't fit in BYTE");
4540 break;
4541 case SIZE_WORD:
4542 if (!isword (offs (exp)))
4543 as_warn ("expression doesn't fit in WORD");
4544 break;
4545 }
4546 }
4547
4548 return offs (exp);
4549 }
4550
4551 /* These are the back-ends for the various machine dependent pseudo-ops. */
4552 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4553
4554 static void
4555 s_data1 (ignore)
4556 int ignore;
4557 {
4558 subseg_set (data_section, 1);
4559 demand_empty_rest_of_line ();
4560 }
4561
4562 static void
4563 s_data2 (ignore)
4564 int ignore;
4565 {
4566 subseg_set (data_section, 2);
4567 demand_empty_rest_of_line ();
4568 }
4569
4570 static void
4571 s_bss (ignore)
4572 int ignore;
4573 {
4574 /* We don't support putting frags in the BSS segment, we fake it
4575 by marking in_bss, then looking at s_skip for clues. */
4576
4577 subseg_set (bss_section, 0);
4578 demand_empty_rest_of_line ();
4579 }
4580
4581 static void
4582 s_even (ignore)
4583 int ignore;
4584 {
4585 register int temp;
4586 register long temp_fill;
4587
4588 temp = 1; /* JF should be 2? */
4589 temp_fill = get_absolute_expression ();
4590 if (!need_pass_2) /* Never make frag if expect extra pass. */
4591 frag_align (temp, (int) temp_fill);
4592 demand_empty_rest_of_line ();
4593 }
4594
4595 static void
4596 s_proc (ignore)
4597 int ignore;
4598 {
4599 demand_empty_rest_of_line ();
4600 }
4601 \f
4602 /* Pseudo-ops handled for MRI compatibility. */
4603
4604 /* Handle an MRI style chip specification. */
4605
4606 static void
4607 mri_chip ()
4608 {
4609 char *s;
4610 char c;
4611 int i;
4612
4613 s = input_line_pointer;
4614 c = get_symbol_end ();
4615 for (i = 0; i < n_archs; i++)
4616 if (strcasecmp (s, archs[i].name) == 0)
4617 break;
4618 if (i >= n_archs)
4619 {
4620 as_bad ("%s: unrecognized processor name", s);
4621 *input_line_pointer = c;
4622 ignore_rest_of_line ();
4623 return;
4624 }
4625 *input_line_pointer = c;
4626
4627 if (*input_line_pointer == '/')
4628 current_architecture = 0;
4629 else
4630 current_architecture &= m68881 | m68851;
4631 current_architecture |= archs[i].arch;
4632
4633 while (*input_line_pointer == '/')
4634 {
4635 ++input_line_pointer;
4636 s = input_line_pointer;
4637 c = get_symbol_end ();
4638 if (strcmp (s, "68881") == 0)
4639 current_architecture |= m68881;
4640 else if (strcmp (s, "68851") == 0)
4641 current_architecture |= m68851;
4642 *input_line_pointer = c;
4643 }
4644 }
4645
4646 /* The MRI CHIP pseudo-op. */
4647
4648 static void
4649 s_chip (ignore)
4650 int ignore;
4651 {
4652 char *stop = NULL;
4653 char stopc;
4654
4655 if (flag_mri)
4656 stop = mri_comment_field (&stopc);
4657 mri_chip ();
4658 if (flag_mri)
4659 mri_comment_end (stop, stopc);
4660 demand_empty_rest_of_line ();
4661 }
4662
4663 /* The MRI FOPT pseudo-op. */
4664
4665 static void
4666 s_fopt (ignore)
4667 int ignore;
4668 {
4669 SKIP_WHITESPACE ();
4670
4671 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4672 {
4673 int temp;
4674
4675 input_line_pointer += 3;
4676 temp = get_absolute_expression ();
4677 if (temp < 0 || temp > 7)
4678 as_bad ("bad coprocessor id");
4679 else
4680 m68k_float_copnum = COP0 + temp;
4681 }
4682 else
4683 {
4684 as_bad ("unrecognized fopt option");
4685 ignore_rest_of_line ();
4686 return;
4687 }
4688
4689 demand_empty_rest_of_line ();
4690 }
4691
4692 /* The structure used to handle the MRI OPT pseudo-op. */
4693
4694 struct opt_action
4695 {
4696 /* The name of the option. */
4697 const char *name;
4698
4699 /* If this is not NULL, just call this function. The first argument
4700 is the ARG field of this structure, the second argument is
4701 whether the option was negated. */
4702 void (*pfn) PARAMS ((int arg, int on));
4703
4704 /* If this is not NULL, and the PFN field is NULL, set the variable
4705 this points to. Set it to the ARG field if the option was not
4706 negated, and the NOTARG field otherwise. */
4707 int *pvar;
4708
4709 /* The value to pass to PFN or to assign to *PVAR. */
4710 int arg;
4711
4712 /* The value to assign to *PVAR if the option is negated. If PFN is
4713 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4714 the option may not be negated. */
4715 int notarg;
4716 };
4717
4718 /* The table used to handle the MRI OPT pseudo-op. */
4719
4720 static void skip_to_comma PARAMS ((int, int));
4721 static void opt_nest PARAMS ((int, int));
4722 static void opt_chip PARAMS ((int, int));
4723 static void opt_list PARAMS ((int, int));
4724 static void opt_list_symbols PARAMS ((int, int));
4725
4726 static const struct opt_action opt_table[] =
4727 {
4728 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4729
4730 /* We do relaxing, so there is little use for these options. */
4731 { "b", 0, 0, 0, 0 },
4732 { "brs", 0, 0, 0, 0 },
4733 { "brb", 0, 0, 0, 0 },
4734 { "brl", 0, 0, 0, 0 },
4735 { "brw", 0, 0, 0, 0 },
4736
4737 { "c", 0, 0, 0, 0 },
4738 { "cex", 0, 0, 0, 0 },
4739 { "case", 0, &symbols_case_sensitive, 1, 0 },
4740 { "cl", 0, 0, 0, 0 },
4741 { "cre", 0, 0, 0, 0 },
4742 { "d", 0, &flag_keep_locals, 1, 0 },
4743 { "e", 0, 0, 0, 0 },
4744 { "f", 0, &flag_short_refs, 1, 0 },
4745 { "frs", 0, &flag_short_refs, 1, 0 },
4746 { "frl", 0, &flag_short_refs, 0, 1 },
4747 { "g", 0, 0, 0, 0 },
4748 { "i", 0, 0, 0, 0 },
4749 { "m", 0, 0, 0, 0 },
4750 { "mex", 0, 0, 0, 0 },
4751 { "mc", 0, 0, 0, 0 },
4752 { "md", 0, 0, 0, 0 },
4753 { "nest", opt_nest, 0, 0, 0 },
4754 { "next", skip_to_comma, 0, 0, 0 },
4755 { "o", 0, 0, 0, 0 },
4756 { "old", 0, 0, 0, 0 },
4757 { "op", skip_to_comma, 0, 0, 0 },
4758 { "pco", 0, 0, 0, 0 },
4759 { "p", opt_chip, 0, 0, 0 },
4760 { "pcr", 0, 0, 0, 0 },
4761 { "pcs", 0, 0, 0, 0 },
4762 { "r", 0, 0, 0, 0 },
4763 { "quick", 0, &m68k_quick, 1, 0 },
4764 { "rel32", 0, &m68k_rel32, 1, 0 },
4765 { "s", opt_list, 0, 0, 0 },
4766 { "t", opt_list_symbols, 0, 0, 0 },
4767 { "w", 0, &flag_no_warnings, 0, 1 },
4768 { "x", 0, 0, 0, 0 }
4769 };
4770
4771 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4772
4773 /* The MRI OPT pseudo-op. */
4774
4775 static void
4776 s_opt (ignore)
4777 int ignore;
4778 {
4779 do
4780 {
4781 int t;
4782 char *s;
4783 char c;
4784 int i;
4785 const struct opt_action *o;
4786
4787 SKIP_WHITESPACE ();
4788
4789 t = 1;
4790 if (*input_line_pointer == '-')
4791 {
4792 ++input_line_pointer;
4793 t = 0;
4794 }
4795 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4796 {
4797 input_line_pointer += 2;
4798 t = 0;
4799 }
4800
4801 s = input_line_pointer;
4802 c = get_symbol_end ();
4803
4804 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4805 {
4806 if (strcasecmp (s, o->name) == 0)
4807 {
4808 if (o->pfn)
4809 {
4810 /* Restore input_line_pointer now in case the option
4811 takes arguments. */
4812 *input_line_pointer = c;
4813 (*o->pfn) (o->arg, t);
4814 }
4815 else if (o->pvar != NULL)
4816 {
4817 if (! t && o->arg == o->notarg)
4818 as_bad ("option `%s' may not be negated", s);
4819 *input_line_pointer = c;
4820 *o->pvar = t ? o->arg : o->notarg;
4821 }
4822 else
4823 *input_line_pointer = c;
4824 break;
4825 }
4826 }
4827 if (i >= OPTCOUNT)
4828 {
4829 as_bad ("option `%s' not recognized", s);
4830 *input_line_pointer = c;
4831 }
4832 }
4833 while (*input_line_pointer++ == ',');
4834
4835 /* Move back to terminating character. */
4836 --input_line_pointer;
4837 demand_empty_rest_of_line ();
4838 }
4839
4840 /* Skip ahead to a comma. This is used for OPT options which we do
4841 not suppor tand which take arguments. */
4842
4843 static void
4844 skip_to_comma (arg, on)
4845 int arg;
4846 int on;
4847 {
4848 while (*input_line_pointer != ','
4849 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4850 ++input_line_pointer;
4851 }
4852
4853 /* Handle the OPT NEST=depth option. */
4854
4855 static void
4856 opt_nest (arg, on)
4857 int arg;
4858 int on;
4859 {
4860 if (*input_line_pointer != '=')
4861 {
4862 as_bad ("bad format of OPT NEST=depth");
4863 return;
4864 }
4865
4866 ++input_line_pointer;
4867 max_macro_nest = get_absolute_expression ();
4868 }
4869
4870 /* Handle the OPT P=chip option. */
4871
4872 static void
4873 opt_chip (arg, on)
4874 int arg;
4875 int on;
4876 {
4877 if (*input_line_pointer != '=')
4878 {
4879 /* This is just OPT P, which we do not support. */
4880 return;
4881 }
4882
4883 ++input_line_pointer;
4884 mri_chip ();
4885 }
4886
4887 /* Handle the OPT S option. */
4888
4889 static void
4890 opt_list (arg, on)
4891 int arg;
4892 int on;
4893 {
4894 listing_list (on);
4895 }
4896
4897 /* Handle the OPT T option. */
4898
4899 static void
4900 opt_list_symbols (arg, on)
4901 int arg;
4902 int on;
4903 {
4904 if (on)
4905 listing |= LISTING_SYMBOLS;
4906 else
4907 listing &=~ LISTING_SYMBOLS;
4908 }
4909
4910 /* Handle the MRI REG pseudo-op. */
4911
4912 static void
4913 s_reg (ignore)
4914 int ignore;
4915 {
4916 char *s;
4917 int c;
4918 struct m68k_op rop;
4919 unsigned long mask;
4920 char *stop = NULL;
4921 char stopc;
4922
4923 if (line_label == NULL)
4924 {
4925 as_bad ("missing label");
4926 ignore_rest_of_line ();
4927 return;
4928 }
4929
4930 if (flag_mri)
4931 stop = mri_comment_field (&stopc);
4932
4933 SKIP_WHITESPACE ();
4934
4935 s = input_line_pointer;
4936 while (isalnum ((unsigned char) *input_line_pointer)
4937 #ifdef REGISTER_PREFIX
4938 || *input_line_pointer == REGISTER_PREFIX
4939 #endif
4940 || *input_line_pointer == '/'
4941 || *input_line_pointer == '-')
4942 ++input_line_pointer;
4943 c = *input_line_pointer;
4944 *input_line_pointer = '\0';
4945
4946 if (m68k_ip_op (s, &rop) != 0)
4947 {
4948 if (rop.error == NULL)
4949 as_bad ("bad register list");
4950 else
4951 as_bad ("bad register list: %s", rop.error);
4952 *input_line_pointer = c;
4953 ignore_rest_of_line ();
4954 return;
4955 }
4956
4957 *input_line_pointer = c;
4958
4959 if (rop.mode == REGLST)
4960 mask = rop.mask;
4961 else if (rop.mode == DREG)
4962 mask = 1 << (rop.reg - DATA0);
4963 else if (rop.mode == AREG)
4964 mask = 1 << (rop.reg - ADDR0 + 8);
4965 else if (rop.mode == FPREG)
4966 mask = 1 << (rop.reg - FP0 + 16);
4967 else if (rop.mode == CONTROL
4968 && rop.reg == FPI)
4969 mask = 1 << 24;
4970 else if (rop.mode == CONTROL
4971 && rop.reg == FPS)
4972 mask = 1 << 25;
4973 else if (rop.mode == CONTROL
4974 && rop.reg == FPC)
4975 mask = 1 << 26;
4976 else
4977 {
4978 as_bad ("bad register list");
4979 ignore_rest_of_line ();
4980 return;
4981 }
4982
4983 S_SET_SEGMENT (line_label, absolute_section);
4984 S_SET_VALUE (line_label, mask);
4985 line_label->sy_frag = &zero_address_frag;
4986
4987 if (flag_mri)
4988 mri_comment_end (stop, stopc);
4989
4990 demand_empty_rest_of_line ();
4991 }
4992
4993 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4994
4995 struct save_opts
4996 {
4997 struct save_opts *next;
4998 int abspcadd;
4999 int symbols_case_sensitive;
5000 int keep_locals;
5001 int short_refs;
5002 int architecture;
5003 int quick;
5004 int rel32;
5005 int listing;
5006 int no_warnings;
5007 /* FIXME: We don't save OPT S. */
5008 };
5009
5010 /* This variable holds the stack of saved options. */
5011
5012 static struct save_opts *save_stack;
5013
5014 /* The MRI SAVE pseudo-op. */
5015
5016 static void
5017 s_save (ignore)
5018 int ignore;
5019 {
5020 struct save_opts *s;
5021
5022 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5023 s->abspcadd = m68k_abspcadd;
5024 s->symbols_case_sensitive = symbols_case_sensitive;
5025 s->keep_locals = flag_keep_locals;
5026 s->short_refs = flag_short_refs;
5027 s->architecture = current_architecture;
5028 s->quick = m68k_quick;
5029 s->rel32 = m68k_rel32;
5030 s->listing = listing;
5031 s->no_warnings = flag_no_warnings;
5032
5033 s->next = save_stack;
5034 save_stack = s;
5035
5036 demand_empty_rest_of_line ();
5037 }
5038
5039 /* The MRI RESTORE pseudo-op. */
5040
5041 static void
5042 s_restore (ignore)
5043 int ignore;
5044 {
5045 struct save_opts *s;
5046
5047 if (save_stack == NULL)
5048 {
5049 as_bad ("restore without save");
5050 ignore_rest_of_line ();
5051 return;
5052 }
5053
5054 s = save_stack;
5055 save_stack = s->next;
5056
5057 m68k_abspcadd = s->abspcadd;
5058 symbols_case_sensitive = s->symbols_case_sensitive;
5059 flag_keep_locals = s->keep_locals;
5060 flag_short_refs = s->short_refs;
5061 current_architecture = s->architecture;
5062 m68k_quick = s->quick;
5063 m68k_rel32 = s->rel32;
5064 listing = s->listing;
5065 flag_no_warnings = s->no_warnings;
5066
5067 free (s);
5068
5069 demand_empty_rest_of_line ();
5070 }
5071
5072 /* Types of MRI structured control directives. */
5073
5074 enum mri_control_type
5075 {
5076 mri_for,
5077 mri_if,
5078 mri_repeat,
5079 mri_while
5080 };
5081
5082 /* This structure is used to stack the MRI structured control
5083 directives. */
5084
5085 struct mri_control_info
5086 {
5087 /* The directive within which this one is enclosed. */
5088 struct mri_control_info *outer;
5089
5090 /* The type of directive. */
5091 enum mri_control_type type;
5092
5093 /* Whether an ELSE has been in an IF. */
5094 int else_seen;
5095
5096 /* The add or sub statement at the end of a FOR. */
5097 char *incr;
5098
5099 /* The label of the top of a FOR or REPEAT loop. */
5100 char *top;
5101
5102 /* The label to jump to for the next iteration, or the else
5103 expression of a conditional. */
5104 char *next;
5105
5106 /* The label to jump to to break out of the loop, or the label past
5107 the end of a conditional. */
5108 char *bottom;
5109 };
5110
5111 /* The stack of MRI structured control directives. */
5112
5113 static struct mri_control_info *mri_control_stack;
5114
5115 /* The current MRI structured control directive index number, used to
5116 generate label names. */
5117
5118 static int mri_control_index;
5119
5120 /* Some function prototypes. */
5121
5122 static char *mri_control_label PARAMS ((void));
5123 static struct mri_control_info *push_mri_control
5124 PARAMS ((enum mri_control_type));
5125 static void pop_mri_control PARAMS ((void));
5126 static int parse_mri_condition PARAMS ((int *));
5127 static int parse_mri_control_operand
5128 PARAMS ((int *, char **, char **, char **, char **));
5129 static int swap_mri_condition PARAMS ((int));
5130 static int reverse_mri_condition PARAMS ((int));
5131 static void build_mri_control_operand
5132 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5133 const char *, int));
5134 static void parse_mri_control_expression
5135 PARAMS ((char *, int, const char *, const char *, int));
5136
5137 /* Generate a new MRI label structured control directive label name. */
5138
5139 static char *
5140 mri_control_label ()
5141 {
5142 char *n;
5143
5144 n = (char *) xmalloc (20);
5145 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5146 ++mri_control_index;
5147 return n;
5148 }
5149
5150 /* Create a new MRI structured control directive. */
5151
5152 static struct mri_control_info *
5153 push_mri_control (type)
5154 enum mri_control_type type;
5155 {
5156 struct mri_control_info *n;
5157
5158 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5159
5160 n->type = type;
5161 n->else_seen = 0;
5162 if (type == mri_if || type == mri_while)
5163 n->top = NULL;
5164 else
5165 n->top = mri_control_label ();
5166 n->next = mri_control_label ();
5167 n->bottom = mri_control_label ();
5168
5169 n->outer = mri_control_stack;
5170 mri_control_stack = n;
5171
5172 return n;
5173 }
5174
5175 /* Pop off the stack of MRI structured control directives. */
5176
5177 static void
5178 pop_mri_control ()
5179 {
5180 struct mri_control_info *n;
5181
5182 n = mri_control_stack;
5183 mri_control_stack = n->outer;
5184 if (n->top != NULL)
5185 free (n->top);
5186 free (n->next);
5187 free (n->bottom);
5188 free (n);
5189 }
5190
5191 /* Recognize a condition code in an MRI structured control expression. */
5192
5193 static int
5194 parse_mri_condition (pcc)
5195 int *pcc;
5196 {
5197 char c1, c2;
5198
5199 know (*input_line_pointer == '<');
5200
5201 ++input_line_pointer;
5202 c1 = *input_line_pointer++;
5203 c2 = *input_line_pointer++;
5204
5205 if (*input_line_pointer != '>')
5206 {
5207 as_bad ("syntax error in structured control directive");
5208 return 0;
5209 }
5210
5211 ++input_line_pointer;
5212 SKIP_WHITESPACE ();
5213
5214 if (isupper (c1))
5215 c1 = tolower (c1);
5216 if (isupper (c2))
5217 c2 = tolower (c2);
5218
5219 *pcc = (c1 << 8) | c2;
5220
5221 return 1;
5222 }
5223
5224 /* Parse a single operand in an MRI structured control expression. */
5225
5226 static int
5227 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5228 int *pcc;
5229 char **leftstart;
5230 char **leftstop;
5231 char **rightstart;
5232 char **rightstop;
5233 {
5234 char *s;
5235
5236 SKIP_WHITESPACE ();
5237
5238 *pcc = -1;
5239 *leftstart = NULL;
5240 *leftstop = NULL;
5241 *rightstart = NULL;
5242 *rightstop = NULL;
5243
5244 if (*input_line_pointer == '<')
5245 {
5246 /* It's just a condition code. */
5247 return parse_mri_condition (pcc);
5248 }
5249
5250 /* Look ahead for the condition code. */
5251 for (s = input_line_pointer; *s != '\0'; ++s)
5252 {
5253 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5254 break;
5255 }
5256 if (*s == '\0')
5257 {
5258 as_bad ("missing condition code in structured control directive");
5259 return 0;
5260 }
5261
5262 *leftstart = input_line_pointer;
5263 *leftstop = s;
5264 if (*leftstop > *leftstart
5265 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5266 --*leftstop;
5267
5268 input_line_pointer = s;
5269 if (! parse_mri_condition (pcc))
5270 return 0;
5271
5272 /* Look ahead for AND or OR or end of line. */
5273 for (s = input_line_pointer; *s != '\0'; ++s)
5274 {
5275 if ((strncasecmp (s, "AND", 3) == 0
5276 && (s[3] == '.' || ! is_part_of_name (s[3])))
5277 || (strncasecmp (s, "OR", 2) == 0
5278 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5279 break;
5280 }
5281
5282 *rightstart = input_line_pointer;
5283 *rightstop = s;
5284 if (*rightstop > *rightstart
5285 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5286 --*rightstop;
5287
5288 input_line_pointer = s;
5289
5290 return 1;
5291 }
5292
5293 #define MCC(b1, b2) (((b1) << 8) | (b2))
5294
5295 /* Swap the sense of a condition. This changes the condition so that
5296 it generates the same result when the operands are swapped. */
5297
5298 static int
5299 swap_mri_condition (cc)
5300 int cc;
5301 {
5302 switch (cc)
5303 {
5304 case MCC ('h', 'i'): return MCC ('c', 's');
5305 case MCC ('l', 's'): return MCC ('c', 'c');
5306 case MCC ('c', 'c'): return MCC ('l', 's');
5307 case MCC ('c', 's'): return MCC ('h', 'i');
5308 case MCC ('p', 'l'): return MCC ('m', 'i');
5309 case MCC ('m', 'i'): return MCC ('p', 'l');
5310 case MCC ('g', 'e'): return MCC ('l', 'e');
5311 case MCC ('l', 't'): return MCC ('g', 't');
5312 case MCC ('g', 't'): return MCC ('l', 't');
5313 case MCC ('l', 'e'): return MCC ('g', 'e');
5314 }
5315 return cc;
5316 }
5317
5318 /* Reverse the sense of a condition. */
5319
5320 static int
5321 reverse_mri_condition (cc)
5322 int cc;
5323 {
5324 switch (cc)
5325 {
5326 case MCC ('h', 'i'): return MCC ('l', 's');
5327 case MCC ('l', 's'): return MCC ('h', 'i');
5328 case MCC ('c', 'c'): return MCC ('c', 's');
5329 case MCC ('c', 's'): return MCC ('c', 'c');
5330 case MCC ('n', 'e'): return MCC ('e', 'q');
5331 case MCC ('e', 'q'): return MCC ('n', 'e');
5332 case MCC ('v', 'c'): return MCC ('v', 's');
5333 case MCC ('v', 's'): return MCC ('v', 'c');
5334 case MCC ('p', 'l'): return MCC ('m', 'i');
5335 case MCC ('m', 'i'): return MCC ('p', 'l');
5336 case MCC ('g', 'e'): return MCC ('l', 't');
5337 case MCC ('l', 't'): return MCC ('g', 'e');
5338 case MCC ('g', 't'): return MCC ('l', 'e');
5339 case MCC ('l', 'e'): return MCC ('g', 't');
5340 }
5341 return cc;
5342 }
5343
5344 /* Build an MRI structured control expression. This generates test
5345 and branch instructions. It goes to TRUELAB if the condition is
5346 true, and to FALSELAB if the condition is false. Exactly one of
5347 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5348 is the size qualifier for the expression. EXTENT is the size to
5349 use for the branch. */
5350
5351 static void
5352 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5353 rightstop, truelab, falselab, extent)
5354 int qual;
5355 int cc;
5356 char *leftstart;
5357 char *leftstop;
5358 char *rightstart;
5359 char *rightstop;
5360 const char *truelab;
5361 const char *falselab;
5362 int extent;
5363 {
5364 char *buf;
5365 char *s;
5366
5367 if (leftstart != NULL)
5368 {
5369 struct m68k_op leftop, rightop;
5370 char c;
5371
5372 /* Swap the compare operands, if necessary, to produce a legal
5373 m68k compare instruction. Comparing a register operand with
5374 a non-register operand requires the register to be on the
5375 right (cmp, cmpa). Comparing an immediate value with
5376 anything requires the immediate value to be on the left
5377 (cmpi). */
5378
5379 c = *leftstop;
5380 *leftstop = '\0';
5381 (void) m68k_ip_op (leftstart, &leftop);
5382 *leftstop = c;
5383
5384 c = *rightstop;
5385 *rightstop = '\0';
5386 (void) m68k_ip_op (rightstart, &rightop);
5387 *rightstop = c;
5388
5389 if (rightop.mode == IMMED
5390 || ((leftop.mode == DREG || leftop.mode == AREG)
5391 && (rightop.mode != DREG && rightop.mode != AREG)))
5392 {
5393 char *temp;
5394
5395 cc = swap_mri_condition (cc);
5396 temp = leftstart;
5397 leftstart = rightstart;
5398 rightstart = temp;
5399 temp = leftstop;
5400 leftstop = rightstop;
5401 rightstop = temp;
5402 }
5403 }
5404
5405 if (truelab == NULL)
5406 {
5407 cc = reverse_mri_condition (cc);
5408 truelab = falselab;
5409 }
5410
5411 if (leftstart != NULL)
5412 {
5413 buf = (char *) xmalloc (20
5414 + (leftstop - leftstart)
5415 + (rightstop - rightstart));
5416 s = buf;
5417 *s++ = 'c';
5418 *s++ = 'm';
5419 *s++ = 'p';
5420 if (qual != '\0')
5421 *s++ = qual;
5422 *s++ = ' ';
5423 memcpy (s, leftstart, leftstop - leftstart);
5424 s += leftstop - leftstart;
5425 *s++ = ',';
5426 memcpy (s, rightstart, rightstop - rightstart);
5427 s += rightstop - rightstart;
5428 *s = '\0';
5429 md_assemble (buf);
5430 free (buf);
5431 }
5432
5433 buf = (char *) xmalloc (20 + strlen (truelab));
5434 s = buf;
5435 *s++ = 'b';
5436 *s++ = cc >> 8;
5437 *s++ = cc & 0xff;
5438 if (extent != '\0')
5439 *s++ = extent;
5440 *s++ = ' ';
5441 strcpy (s, truelab);
5442 md_assemble (buf);
5443 free (buf);
5444 }
5445
5446 /* Parse an MRI structured control expression. This generates test
5447 and branch instructions. STOP is where the expression ends. It
5448 goes to TRUELAB if the condition is true, and to FALSELAB if the
5449 condition is false. Exactly one of TRUELAB and FALSELAB will be
5450 NULL, meaning to fall through. QUAL is the size qualifier for the
5451 expression. EXTENT is the size to use for the branch. */
5452
5453 static void
5454 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5455 char *stop;
5456 int qual;
5457 const char *truelab;
5458 const char *falselab;
5459 int extent;
5460 {
5461 int c;
5462 int cc;
5463 char *leftstart;
5464 char *leftstop;
5465 char *rightstart;
5466 char *rightstop;
5467
5468 c = *stop;
5469 *stop = '\0';
5470
5471 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5472 &rightstart, &rightstop))
5473 {
5474 *stop = c;
5475 return;
5476 }
5477
5478 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5479 {
5480 const char *flab;
5481
5482 if (falselab != NULL)
5483 flab = falselab;
5484 else
5485 flab = mri_control_label ();
5486
5487 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5488 rightstop, (const char *) NULL, flab, extent);
5489
5490 input_line_pointer += 3;
5491 if (*input_line_pointer != '.'
5492 || input_line_pointer[1] == '\0')
5493 qual = '\0';
5494 else
5495 {
5496 qual = input_line_pointer[1];
5497 input_line_pointer += 2;
5498 }
5499
5500 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5501 &rightstart, &rightstop))
5502 {
5503 *stop = c;
5504 return;
5505 }
5506
5507 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5508 rightstop, truelab, falselab, extent);
5509
5510 if (falselab == NULL)
5511 colon (flab);
5512 }
5513 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5514 {
5515 const char *tlab;
5516
5517 if (truelab != NULL)
5518 tlab = truelab;
5519 else
5520 tlab = mri_control_label ();
5521
5522 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5523 rightstop, tlab, (const char *) NULL, extent);
5524
5525 input_line_pointer += 2;
5526 if (*input_line_pointer != '.'
5527 || input_line_pointer[1] == '\0')
5528 qual = '\0';
5529 else
5530 {
5531 qual = input_line_pointer[1];
5532 input_line_pointer += 2;
5533 }
5534
5535 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5536 &rightstart, &rightstop))
5537 {
5538 *stop = c;
5539 return;
5540 }
5541
5542 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5543 rightstop, truelab, falselab, extent);
5544
5545 if (truelab == NULL)
5546 colon (tlab);
5547 }
5548 else
5549 {
5550 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5551 rightstop, truelab, falselab, extent);
5552 }
5553
5554 *stop = c;
5555 if (input_line_pointer != stop)
5556 as_bad ("syntax error in structured control directive");
5557 }
5558
5559 /* Handle the MRI IF pseudo-op. This may be a structured control
5560 directive, or it may be a regular assembler conditional, depending
5561 on its operands. */
5562
5563 static void
5564 s_mri_if (qual)
5565 int qual;
5566 {
5567 char *s;
5568 int c;
5569 struct mri_control_info *n;
5570
5571 /* A structured control directive must end with THEN with an
5572 optional qualifier. */
5573 s = input_line_pointer;
5574 while (! is_end_of_line[(unsigned char) *s]
5575 && (! flag_mri || *s != '*'))
5576 ++s;
5577 --s;
5578 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5579 --s;
5580
5581 if (s - input_line_pointer > 1
5582 && s[-1] == '.')
5583 s -= 2;
5584
5585 if (s - input_line_pointer < 3
5586 || strncasecmp (s - 3, "THEN", 4) != 0)
5587 {
5588 if (qual != '\0')
5589 {
5590 as_bad ("missing then");
5591 ignore_rest_of_line ();
5592 return;
5593 }
5594
5595 /* It's a conditional. */
5596 s_if (O_ne);
5597 return;
5598 }
5599
5600 /* Since this might be a conditional if, this pseudo-op will be
5601 called even if we are supported to be ignoring input. Double
5602 check now. Clobber *input_line_pointer so that ignore_input
5603 thinks that this is not a special pseudo-op. */
5604 c = *input_line_pointer;
5605 *input_line_pointer = 0;
5606 if (ignore_input ())
5607 {
5608 *input_line_pointer = c;
5609 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5610 ++input_line_pointer;
5611 demand_empty_rest_of_line ();
5612 return;
5613 }
5614 *input_line_pointer = c;
5615
5616 n = push_mri_control (mri_if);
5617
5618 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5619 n->next, s[1] == '.' ? s[2] : '\0');
5620
5621 if (s[1] == '.')
5622 input_line_pointer = s + 3;
5623 else
5624 input_line_pointer = s + 1;
5625
5626 if (flag_mri)
5627 {
5628 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5629 ++input_line_pointer;
5630 }
5631
5632 demand_empty_rest_of_line ();
5633 }
5634
5635 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5636 structured IF, associate the ELSE with the IF. Otherwise, assume
5637 it is a conditional else. */
5638
5639 static void
5640 s_mri_else (qual)
5641 int qual;
5642 {
5643 int c;
5644 char *buf;
5645 char q[2];
5646
5647 if (qual == '\0'
5648 && (mri_control_stack == NULL
5649 || mri_control_stack->type != mri_if
5650 || mri_control_stack->else_seen))
5651 {
5652 s_else (0);
5653 return;
5654 }
5655
5656 c = *input_line_pointer;
5657 *input_line_pointer = 0;
5658 if (ignore_input ())
5659 {
5660 *input_line_pointer = c;
5661 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5662 ++input_line_pointer;
5663 demand_empty_rest_of_line ();
5664 return;
5665 }
5666 *input_line_pointer = c;
5667
5668 if (mri_control_stack == NULL
5669 || mri_control_stack->type != mri_if
5670 || mri_control_stack->else_seen)
5671 {
5672 as_bad ("else without matching if");
5673 ignore_rest_of_line ();
5674 return;
5675 }
5676
5677 mri_control_stack->else_seen = 1;
5678
5679 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5680 q[0] = qual;
5681 q[1] = '\0';
5682 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5683 md_assemble (buf);
5684 free (buf);
5685
5686 colon (mri_control_stack->next);
5687
5688 if (flag_mri)
5689 {
5690 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5691 ++input_line_pointer;
5692 }
5693
5694 demand_empty_rest_of_line ();
5695 }
5696
5697 /* Handle the MRI ENDI pseudo-op. */
5698
5699 static void
5700 s_mri_endi (ignore)
5701 int ignore;
5702 {
5703 if (mri_control_stack == NULL
5704 || mri_control_stack->type != mri_if)
5705 {
5706 as_bad ("endi without matching if");
5707 ignore_rest_of_line ();
5708 return;
5709 }
5710
5711 /* ignore_input will not return true for ENDI, so we don't need to
5712 worry about checking it again here. */
5713
5714 if (! mri_control_stack->else_seen)
5715 colon (mri_control_stack->next);
5716 colon (mri_control_stack->bottom);
5717
5718 pop_mri_control ();
5719
5720 if (flag_mri)
5721 {
5722 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5723 ++input_line_pointer;
5724 }
5725
5726 demand_empty_rest_of_line ();
5727 }
5728
5729 /* Handle the MRI BREAK pseudo-op. */
5730
5731 static void
5732 s_mri_break (extent)
5733 int extent;
5734 {
5735 struct mri_control_info *n;
5736 char *buf;
5737 char ex[2];
5738
5739 n = mri_control_stack;
5740 while (n != NULL
5741 && n->type != mri_for
5742 && n->type != mri_repeat
5743 && n->type != mri_while)
5744 n = n->outer;
5745 if (n == NULL)
5746 {
5747 as_bad ("break outside of structured loop");
5748 ignore_rest_of_line ();
5749 return;
5750 }
5751
5752 buf = (char *) xmalloc (20 + strlen (n->bottom));
5753 ex[0] = extent;
5754 ex[1] = '\0';
5755 sprintf (buf, "bra%s %s", ex, n->bottom);
5756 md_assemble (buf);
5757 free (buf);
5758
5759 if (flag_mri)
5760 {
5761 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5762 ++input_line_pointer;
5763 }
5764
5765 demand_empty_rest_of_line ();
5766 }
5767
5768 /* Handle the MRI NEXT pseudo-op. */
5769
5770 static void
5771 s_mri_next (extent)
5772 int extent;
5773 {
5774 struct mri_control_info *n;
5775 char *buf;
5776 char ex[2];
5777
5778 n = mri_control_stack;
5779 while (n != NULL
5780 && n->type != mri_for
5781 && n->type != mri_repeat
5782 && n->type != mri_while)
5783 n = n->outer;
5784 if (n == NULL)
5785 {
5786 as_bad ("next outside of structured loop");
5787 ignore_rest_of_line ();
5788 return;
5789 }
5790
5791 buf = (char *) xmalloc (20 + strlen (n->next));
5792 ex[0] = extent;
5793 ex[1] = '\0';
5794 sprintf (buf, "bra%s %s", ex, n->next);
5795 md_assemble (buf);
5796 free (buf);
5797
5798 if (flag_mri)
5799 {
5800 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5801 ++input_line_pointer;
5802 }
5803
5804 demand_empty_rest_of_line ();
5805 }
5806
5807 /* Handle the MRI FOR pseudo-op. */
5808
5809 static void
5810 s_mri_for (qual)
5811 int qual;
5812 {
5813 const char *varstart, *varstop;
5814 const char *initstart, *initstop;
5815 const char *endstart, *endstop;
5816 const char *bystart, *bystop;
5817 int up;
5818 int by;
5819 int extent;
5820 struct mri_control_info *n;
5821 char *buf;
5822 char *s;
5823 char ex[2];
5824
5825 /* The syntax is
5826 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5827 */
5828
5829 SKIP_WHITESPACE ();
5830 varstart = input_line_pointer;
5831
5832 /* Look for the '='. */
5833 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5834 && *input_line_pointer != '=')
5835 ++input_line_pointer;
5836 if (*input_line_pointer != '=')
5837 {
5838 as_bad ("missing =");
5839 ignore_rest_of_line ();
5840 return;
5841 }
5842
5843 varstop = input_line_pointer;
5844 if (varstop > varstart
5845 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5846 --varstop;
5847
5848 ++input_line_pointer;
5849
5850 initstart = input_line_pointer;
5851
5852 /* Look for TO or DOWNTO. */
5853 up = 1;
5854 initstop = NULL;
5855 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5856 {
5857 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5858 && ! is_part_of_name (input_line_pointer[2]))
5859 {
5860 initstop = input_line_pointer;
5861 input_line_pointer += 2;
5862 break;
5863 }
5864 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5865 && ! is_part_of_name (input_line_pointer[6]))
5866 {
5867 initstop = input_line_pointer;
5868 up = 0;
5869 input_line_pointer += 6;
5870 break;
5871 }
5872 ++input_line_pointer;
5873 }
5874 if (initstop == NULL)
5875 {
5876 as_bad ("missing to or downto");
5877 ignore_rest_of_line ();
5878 return;
5879 }
5880 if (initstop > initstart
5881 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5882 --initstop;
5883
5884 SKIP_WHITESPACE ();
5885 endstart = input_line_pointer;
5886
5887 /* Look for BY or DO. */
5888 by = 0;
5889 endstop = NULL;
5890 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5891 {
5892 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5893 && ! is_part_of_name (input_line_pointer[2]))
5894 {
5895 endstop = input_line_pointer;
5896 by = 1;
5897 input_line_pointer += 2;
5898 break;
5899 }
5900 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5901 && (input_line_pointer[2] == '.'
5902 || ! is_part_of_name (input_line_pointer[2])))
5903 {
5904 endstop = input_line_pointer;
5905 input_line_pointer += 2;
5906 break;
5907 }
5908 ++input_line_pointer;
5909 }
5910 if (endstop == NULL)
5911 {
5912 as_bad ("missing do");
5913 ignore_rest_of_line ();
5914 return;
5915 }
5916 if (endstop > endstart
5917 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5918 --endstop;
5919
5920 if (! by)
5921 {
5922 bystart = "#1";
5923 bystop = bystart + 2;
5924 }
5925 else
5926 {
5927 SKIP_WHITESPACE ();
5928 bystart = input_line_pointer;
5929
5930 /* Look for DO. */
5931 bystop = NULL;
5932 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5933 {
5934 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5935 && (input_line_pointer[2] == '.'
5936 || ! is_part_of_name (input_line_pointer[2])))
5937 {
5938 bystop = input_line_pointer;
5939 input_line_pointer += 2;
5940 break;
5941 }
5942 ++input_line_pointer;
5943 }
5944 if (bystop == NULL)
5945 {
5946 as_bad ("missing do");
5947 ignore_rest_of_line ();
5948 return;
5949 }
5950 if (bystop > bystart
5951 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5952 --bystop;
5953 }
5954
5955 if (*input_line_pointer != '.')
5956 extent = '\0';
5957 else
5958 {
5959 extent = input_line_pointer[1];
5960 input_line_pointer += 2;
5961 }
5962
5963 /* We have fully parsed the FOR operands. Now build the loop. */
5964
5965 n = push_mri_control (mri_for);
5966
5967 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5968
5969 /* move init,var */
5970 s = buf;
5971 *s++ = 'm';
5972 *s++ = 'o';
5973 *s++ = 'v';
5974 *s++ = 'e';
5975 if (qual != '\0')
5976 *s++ = qual;
5977 *s++ = ' ';
5978 memcpy (s, initstart, initstop - initstart);
5979 s += initstop - initstart;
5980 *s++ = ',';
5981 memcpy (s, varstart, varstop - varstart);
5982 s += varstop - varstart;
5983 *s = '\0';
5984 md_assemble (buf);
5985
5986 colon (n->top);
5987
5988 /* cmp end,var */
5989 s = buf;
5990 *s++ = 'c';
5991 *s++ = 'm';
5992 *s++ = 'p';
5993 if (qual != '\0')
5994 *s++ = qual;
5995 *s++ = ' ';
5996 memcpy (s, endstart, endstop - endstart);
5997 s += endstop - endstart;
5998 *s++ = ',';
5999 memcpy (s, varstart, varstop - varstart);
6000 s += varstop - varstart;
6001 *s = '\0';
6002 md_assemble (buf);
6003
6004 /* bcc bottom */
6005 ex[0] = extent;
6006 ex[1] = '\0';
6007 if (up)
6008 sprintf (buf, "blt%s %s", ex, n->bottom);
6009 else
6010 sprintf (buf, "bgt%s %s", ex, n->bottom);
6011 md_assemble (buf);
6012
6013 /* Put together the add or sub instruction used by ENDF. */
6014 s = buf;
6015 if (up)
6016 strcpy (s, "add");
6017 else
6018 strcpy (s, "sub");
6019 s += 3;
6020 if (qual != '\0')
6021 *s++ = qual;
6022 *s++ = ' ';
6023 memcpy (s, bystart, bystop - bystart);
6024 s += bystop - bystart;
6025 *s++ = ',';
6026 memcpy (s, varstart, varstop - varstart);
6027 s += varstop - varstart;
6028 *s = '\0';
6029 n->incr = buf;
6030
6031 if (flag_mri)
6032 {
6033 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6034 ++input_line_pointer;
6035 }
6036
6037 demand_empty_rest_of_line ();
6038 }
6039
6040 /* Handle the MRI ENDF pseudo-op. */
6041
6042 static void
6043 s_mri_endf (ignore)
6044 int ignore;
6045 {
6046 if (mri_control_stack == NULL
6047 || mri_control_stack->type != mri_for)
6048 {
6049 as_bad ("endf without for");
6050 ignore_rest_of_line ();
6051 return;
6052 }
6053
6054 colon (mri_control_stack->next);
6055
6056 md_assemble (mri_control_stack->incr);
6057
6058 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6059 md_assemble (mri_control_stack->incr);
6060
6061 free (mri_control_stack->incr);
6062
6063 colon (mri_control_stack->bottom);
6064
6065 pop_mri_control ();
6066
6067 if (flag_mri)
6068 {
6069 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6070 ++input_line_pointer;
6071 }
6072
6073 demand_empty_rest_of_line ();
6074 }
6075
6076 /* Handle the MRI REPEAT pseudo-op. */
6077
6078 static void
6079 s_mri_repeat (ignore)
6080 int ignore;
6081 {
6082 struct mri_control_info *n;
6083
6084 n = push_mri_control (mri_repeat);
6085 colon (n->top);
6086 if (flag_mri)
6087 {
6088 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6089 ++input_line_pointer;
6090 }
6091 demand_empty_rest_of_line ();
6092 }
6093
6094 /* Handle the MRI UNTIL pseudo-op. */
6095
6096 static void
6097 s_mri_until (qual)
6098 int qual;
6099 {
6100 char *s;
6101
6102 if (mri_control_stack == NULL
6103 || mri_control_stack->type != mri_repeat)
6104 {
6105 as_bad ("until without repeat");
6106 ignore_rest_of_line ();
6107 return;
6108 }
6109
6110 colon (mri_control_stack->next);
6111
6112 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6113 ;
6114
6115 parse_mri_control_expression (s, qual, (const char *) NULL,
6116 mri_control_stack->top, '\0');
6117
6118 colon (mri_control_stack->bottom);
6119
6120 input_line_pointer = s;
6121
6122 pop_mri_control ();
6123
6124 if (flag_mri)
6125 {
6126 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6127 ++input_line_pointer;
6128 }
6129
6130 demand_empty_rest_of_line ();
6131 }
6132
6133 /* Handle the MRI WHILE pseudo-op. */
6134
6135 static void
6136 s_mri_while (qual)
6137 int qual;
6138 {
6139 char *s;
6140
6141 struct mri_control_info *n;
6142
6143 s = input_line_pointer;
6144 while (! is_end_of_line[(unsigned char) *s]
6145 && (! flag_mri || *s != '*'))
6146 s++;
6147 --s;
6148 while (*s == ' ' || *s == '\t')
6149 --s;
6150 if (s - input_line_pointer > 1
6151 && s[-1] == '.')
6152 s -= 2;
6153 if (s - input_line_pointer < 2
6154 || strncasecmp (s - 1, "DO", 2) != 0)
6155 {
6156 as_bad ("missing do");
6157 ignore_rest_of_line ();
6158 return;
6159 }
6160
6161 n = push_mri_control (mri_while);
6162
6163 colon (n->next);
6164
6165 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6166 s[1] == '.' ? s[2] : '\0');
6167
6168 input_line_pointer = s + 1;
6169 if (*input_line_pointer == '.')
6170 input_line_pointer += 2;
6171
6172 if (flag_mri)
6173 {
6174 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6175 ++input_line_pointer;
6176 }
6177
6178 demand_empty_rest_of_line ();
6179 }
6180
6181 /* Handle the MRI ENDW pseudo-op. */
6182
6183 static void
6184 s_mri_endw (ignore)
6185 int ignore;
6186 {
6187 char *buf;
6188
6189 if (mri_control_stack == NULL
6190 || mri_control_stack->type != mri_while)
6191 {
6192 as_bad ("endw without while");
6193 ignore_rest_of_line ();
6194 return;
6195 }
6196
6197 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6198 sprintf (buf, "bra %s", mri_control_stack->next);
6199 md_assemble (buf);
6200 free (buf);
6201
6202 colon (mri_control_stack->bottom);
6203
6204 pop_mri_control ();
6205
6206 if (flag_mri)
6207 {
6208 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6209 ++input_line_pointer;
6210 }
6211
6212 demand_empty_rest_of_line ();
6213 }
6214 \f
6215 /*
6216 * md_parse_option
6217 * Invocation line includes a switch not recognized by the base assembler.
6218 * See if it's a processor-specific option. These are:
6219 *
6220 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6221 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6222 * Select the architecture. Instructions or features not
6223 * supported by the selected architecture cause fatal
6224 * errors. More than one may be specified. The default is
6225 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6226 * for -m68000, and -m68882 is a synonym for -m68881.
6227 * -[A]m[c]no-68851, -[A]m[c]no-68881
6228 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6229 * so don't use or document it, but that's the way the parsing
6230 * works).
6231 *
6232 * -pic Indicates PIC.
6233 * -k Indicates PIC. (Sun 3 only.)
6234 *
6235 * --bitwise-or
6236 * Permit `|' to be used in expressions.
6237 *
6238 */
6239
6240 #ifdef OBJ_ELF
6241 CONST char *md_shortopts = "lSA:m:kQ:V";
6242 #else
6243 CONST char *md_shortopts = "lSA:m:k";
6244 #endif
6245
6246 struct option md_longopts[] = {
6247 #define OPTION_PIC (OPTION_MD_BASE)
6248 {"pic", no_argument, NULL, OPTION_PIC},
6249 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6250 {"register-prefix-optional", no_argument, NULL,
6251 OPTION_REGISTER_PREFIX_OPTIONAL},
6252 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6253 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6254 {NULL, no_argument, NULL, 0}
6255 };
6256 size_t md_longopts_size = sizeof(md_longopts);
6257
6258 int
6259 md_parse_option (c, arg)
6260 int c;
6261 char *arg;
6262 {
6263 switch (c)
6264 {
6265 case 'l': /* -l means keep external to 2 bit offset
6266 rather than 16 bit one */
6267 flag_short_refs = 1;
6268 break;
6269
6270 case 'S': /* -S means that jbsr's always turn into
6271 jsr's. */
6272 flag_long_jumps = 1;
6273 break;
6274
6275 case 'A':
6276 if (*arg == 'm')
6277 arg++;
6278 /* intentional fall-through */
6279 case 'm':
6280
6281 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6282 {
6283 int i;
6284 unsigned long arch;
6285 const char *oarg = arg;
6286
6287 arg += 3;
6288 if (*arg == 'm')
6289 {
6290 arg++;
6291 if (arg[0] == 'c' && arg[1] == '6')
6292 arg++;
6293 }
6294 for (i = 0; i < n_archs; i++)
6295 if (!strcmp (arg, archs[i].name))
6296 break;
6297 if (i == n_archs)
6298 {
6299 unknown:
6300 as_bad ("unrecognized option `%s'", oarg);
6301 return 0;
6302 }
6303 arch = archs[i].arch;
6304 if (arch == m68881)
6305 no_68881 = 1;
6306 else if (arch == m68851)
6307 no_68851 = 1;
6308 else
6309 goto unknown;
6310 }
6311 else
6312 {
6313 int i;
6314
6315 if (arg[0] == 'c' && arg[1] == '6')
6316 arg++;
6317
6318 for (i = 0; i < n_archs; i++)
6319 if (!strcmp (arg, archs[i].name))
6320 {
6321 unsigned long arch = archs[i].arch;
6322 if (cpu_of_arch (arch))
6323 /* It's a cpu spec. */
6324 {
6325 current_architecture &= ~m68000up;
6326 current_architecture |= arch;
6327 }
6328 else if (arch == m68881)
6329 {
6330 current_architecture |= m68881;
6331 no_68881 = 0;
6332 }
6333 else if (arch == m68851)
6334 {
6335 current_architecture |= m68851;
6336 no_68851 = 0;
6337 }
6338 else
6339 /* ??? */
6340 abort ();
6341 break;
6342 }
6343 if (i == n_archs)
6344 {
6345 as_bad ("unrecognized architecture specification `%s'", arg);
6346 return 0;
6347 }
6348 }
6349 break;
6350
6351 case OPTION_PIC:
6352 case 'k':
6353 flag_want_pic = 1;
6354 break; /* -pic, Position Independent Code */
6355
6356 case OPTION_REGISTER_PREFIX_OPTIONAL:
6357 flag_reg_prefix_optional = 1;
6358 reg_prefix_optional_seen = 1;
6359 break;
6360
6361 /* -V: SVR4 argument to print version ID. */
6362 case 'V':
6363 print_version_id ();
6364 break;
6365
6366 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6367 should be emitted or not. FIXME: Not implemented. */
6368 case 'Q':
6369 break;
6370
6371 case OPTION_BITWISE_OR:
6372 {
6373 char *n, *t;
6374 const char *s;
6375
6376 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6377 t = n;
6378 for (s = m68k_comment_chars; *s != '\0'; s++)
6379 if (*s != '|')
6380 *t++ = *s;
6381 *t = '\0';
6382 m68k_comment_chars = n;
6383 }
6384 break;
6385
6386 default:
6387 return 0;
6388 }
6389
6390 return 1;
6391 }
6392
6393 void
6394 md_show_usage (stream)
6395 FILE *stream;
6396 {
6397 fprintf(stream, "\
6398 680X0 options:\n\
6399 -l use 1 word for refs to undefined symbols [default 2]\n\
6400 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6401 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6402 | -mcpu32 | -m5200\n\
6403 specify variant of 680X0 architecture [default 68020]\n\
6404 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6405 target has/lacks floating-point coprocessor\n\
6406 [default yes for 68020, 68030, and cpu32]\n");
6407 fprintf(stream, "\
6408 -m68851 | -mno-68851\n\
6409 target has/lacks memory-management unit coprocessor\n\
6410 [default yes for 68020 and up]\n\
6411 -pic, -k generate position independent code\n\
6412 -S turn jbsr into jsr\n\
6413 --register-prefix-optional\n\
6414 recognize register names without prefix character\n\
6415 --bitwise-or do not treat `|' as a comment character\n");
6416 }
6417 \f
6418 #ifdef TEST2
6419
6420 /* TEST2: Test md_assemble() */
6421 /* Warning, this routine probably doesn't work anymore */
6422
6423 main ()
6424 {
6425 struct m68k_it the_ins;
6426 char buf[120];
6427 char *cp;
6428 int n;
6429
6430 m68k_ip_begin ();
6431 for (;;)
6432 {
6433 if (!gets (buf) || !*buf)
6434 break;
6435 if (buf[0] == '|' || buf[1] == '.')
6436 continue;
6437 for (cp = buf; *cp; cp++)
6438 if (*cp == '\t')
6439 *cp = ' ';
6440 if (is_label (buf))
6441 continue;
6442 memset (&the_ins, '\0', sizeof (the_ins));
6443 m68k_ip (&the_ins, buf);
6444 if (the_ins.error)
6445 {
6446 printf ("Error %s in %s\n", the_ins.error, buf);
6447 }
6448 else
6449 {
6450 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6451 for (n = 0; n < the_ins.numo; n++)
6452 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6453 printf (" ");
6454 print_the_insn (&the_ins.opcode[0], stdout);
6455 (void) putchar ('\n');
6456 }
6457 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6458 {
6459 if (the_ins.operands[n].error)
6460 {
6461 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6462 continue;
6463 }
6464 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6465 if (the_ins.operands[n].b_const)
6466 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6467 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6468 if (the_ins.operands[n].b_iadd)
6469 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6470 (void) putchar ('\n');
6471 }
6472 }
6473 m68k_ip_end ();
6474 return 0;
6475 }
6476
6477 is_label (str)
6478 char *str;
6479 {
6480 while (*str == ' ')
6481 str++;
6482 while (*str && *str != ' ')
6483 str++;
6484 if (str[-1] == ':' || str[1] == '=')
6485 return 1;
6486 return 0;
6487 }
6488
6489 #endif
6490
6491 /* Possible states for relaxation:
6492
6493 0 0 branch offset byte (bra, etc)
6494 0 1 word
6495 0 2 long
6496
6497 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6498 1 1 word
6499 1 2 long
6500
6501 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6502 2 1 word-long
6503 2 2 long-word
6504 2 3 long-long
6505
6506 */
6507
6508 /* We have no need to default values of symbols. */
6509
6510 /* ARGSUSED */
6511 symbolS *
6512 md_undefined_symbol (name)
6513 char *name;
6514 {
6515 return 0;
6516 }
6517
6518 /* Round up a section size to the appropriate boundary. */
6519 valueT
6520 md_section_align (segment, size)
6521 segT segment;
6522 valueT size;
6523 {
6524 return size; /* Byte alignment is fine */
6525 }
6526
6527 /* Exactly what point is a PC-relative offset relative TO?
6528 On the 68k, it is relative to the address of the first extension
6529 word. The difference between the addresses of the offset and the
6530 first extension word is stored in fx_pcrel_adjust. */
6531 long
6532 md_pcrel_from (fixP)
6533 fixS *fixP;
6534 {
6535 int adjust;
6536
6537 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6538 -1 as 64. */
6539 adjust = fixP->fx_pcrel_adjust;
6540 if (adjust == 64)
6541 adjust = -1;
6542 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6543 }
6544
6545 #ifndef BFD_ASSEMBLER
6546 /*ARGSUSED*/
6547 void
6548 tc_coff_symbol_emit_hook (ignore)
6549 symbolS *ignore;
6550 {
6551 }
6552
6553 int
6554 tc_coff_sizemachdep (frag)
6555 fragS *frag;
6556 {
6557 switch (frag->fr_subtype & 0x3)
6558 {
6559 case BYTE:
6560 return 1;
6561 case SHORT:
6562 return 2;
6563 case LONG:
6564 return 4;
6565 default:
6566 abort ();
6567 return 0;
6568 }
6569 }
6570 #endif
6571
6572 /* end of tc-m68k.c */