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Mon Feb 12 15:16:29 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
19 02111-1307, USA. */
20
21 #include <ctype.h>
22 #include "as.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25
26 #include "opcode/m68k.h"
27 #include "m68k-parse.h"
28
29 /* This array holds the chars that always start a comment. If the
30 pre-processor is disabled, these aren't very useful */
31 #if defined (OBJ_ELF) || defined (TE_DELTA)
32 const char comment_chars[] = "|#";
33 #else
34 const char comment_chars[] = "|";
35 #endif
36
37 /* This array holds the chars that only start a comment at the beginning of
38 a line. If the line seems to have the form '# 123 filename'
39 .line and .file directives will appear in the pre-processed output */
40 /* Note that input_file.c hand checks for '#' at the beginning of the
41 first line of the input file. This is because the compiler outputs
42 #NO_APP at the beginning of its output. */
43 /* Also note that comments like this one will always work. */
44 const char line_comment_chars[] = "#";
45
46 const char line_separator_chars[] = "";
47
48 /* Chars that can be used to separate mant from exp in floating point nums */
49 CONST char EXP_CHARS[] = "eE";
50
51 /* Chars that mean this number is a floating point constant, as
52 in "0f12.456" or "0d1.2345e12". */
53
54 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
55
56 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
57 changed in read.c . Ideally it shouldn't have to know about it at all,
58 but nothing is ideal around here. */
59
60 const int md_reloc_size = 8; /* Size of relocation record */
61
62 /* Are we trying to generate PIC code? If so, absolute references
63 ought to be made into linkage table references or pc-relative
64 references. Not implemented. For ELF there are other means
65 to denote pic relocations. */
66 int flag_want_pic;
67
68 static int flag_short_refs; /* -l option */
69 static int flag_long_jumps; /* -S option */
70
71 #ifdef REGISTER_PREFIX_OPTIONAL
72 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
73 #else
74 int flag_reg_prefix_optional;
75 #endif
76
77 /* The floating point coprocessor to use by default. */
78 static enum m68k_register m68k_float_copnum = COP1;
79
80 /* If this is non-zero, then references to number(%pc) will be taken
81 to refer to number, rather than to %pc + number. */
82 static int m68k_abspcadd;
83
84 /* If this is non-zero, then the quick forms of the move, add, and sub
85 instructions are used when possible. */
86 static int m68k_quick = 1;
87
88 /* If this is non-zero, then if the size is not specified for a base
89 or outer displacement, the assembler assumes that the size should
90 be 32 bits. */
91 static int m68k_rel32 = 1;
92
93 /* Its an arbitrary name: This means I don't approve of it */
94 /* See flames below */
95 static struct obstack robyn;
96
97 #define TAB(x,y) (((x)<<2)+(y))
98 #define TABTYPE(xy) ((xy) >> 2)
99 #define BYTE 0
100 #define SHORT 1
101 #define LONG 2
102 #define SZ_UNDEF 3
103 #undef BRANCH
104 /* Case `g' except when BCC68000 is applicable. */
105 #define ABRANCH 1
106 /* Coprocessor branches. */
107 #define FBRANCH 2
108 /* Mode 7.2 -- program counter indirect with (16-bit) displacement,
109 supported on all cpus. Widens to 32-bit absolute. */
110 #define PCREL 3
111 /* For inserting an extra jmp instruction with long offset on 68000,
112 for expanding conditional branches. (Not bsr or bra.) Since the
113 68000 doesn't support 32-bit displacements for conditional
114 branches, we fake it by reversing the condition and branching
115 around a jmp with an absolute long operand. */
116 #define BCC68000 4
117 /* For the DBcc "instructions". If the displacement requires 32 bits,
118 the branch-around-a-jump game is played here too. */
119 #define DBCC 5
120 /* Not currently used? */
121 #define PCLEA 6
122 /* Mode AINDX (apc-relative) using PC, with variable target, might fit
123 in 16 or 8 bits. */
124 #define PCINDEX 7
125
126 struct m68k_incant
127 {
128 const char *m_operands;
129 unsigned long m_opcode;
130 short m_opnum;
131 short m_codenum;
132 int m_arch;
133 struct m68k_incant *m_next;
134 };
135
136 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
137 #define gettwo(x) (((x)->m_opcode)&0xffff)
138
139 static const enum m68k_register m68000_control_regs[] = { 0 };
140 static const enum m68k_register m68010_control_regs[] = {
141 SFC, DFC, USP, VBR,
142 0
143 };
144 static const enum m68k_register m68020_control_regs[] = {
145 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
146 0
147 };
148 static const enum m68k_register m68040_control_regs[] = {
149 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
150 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
151 0
152 };
153 static const enum m68k_register m68060_control_regs[] = {
154 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
155 USP, VBR, URP, SRP, PCR,
156 0
157 };
158 #define cpu32_control_regs m68010_control_regs
159
160 static const enum m68k_register *control_regs;
161
162 /* internal form of a 68020 instruction */
163 struct m68k_it
164 {
165 const char *error;
166 const char *args; /* list of opcode info */
167 int numargs;
168
169 int numo; /* Number of shorts in opcode */
170 short opcode[11];
171
172 struct m68k_op operands[6];
173
174 int nexp; /* number of exprs in use */
175 struct m68k_exp exprs[4];
176
177 int nfrag; /* Number of frags we have to produce */
178 struct
179 {
180 int fragoff; /* Where in the current opcode the frag ends */
181 symbolS *fadd;
182 long foff;
183 int fragty;
184 }
185 fragb[4];
186
187 int nrel; /* Num of reloc strucs in use */
188 struct
189 {
190 int n;
191 expressionS exp;
192 char wid;
193 char pcrel;
194 /* In a pc relative address the difference between the address
195 of the offset and the address that the offset is relative
196 to. This depends on the addressing mode. Basically this
197 is the value to put in the offset field to address the
198 first byte of the offset, without regarding the special
199 significance of some values (in the branch instruction, for
200 example). */
201 int pcrel_fix;
202 #ifdef OBJ_ELF
203 /* Whether this expression needs special pic relocation, and if
204 so, which. */
205 enum pic_relocation pic_reloc;
206 #endif
207 }
208 reloc[5]; /* Five is enough??? */
209 };
210
211 #define cpu_of_arch(x) ((x) & m68000up)
212 #define float_of_arch(x) ((x) & mfloat)
213 #define mmu_of_arch(x) ((x) & mmmu)
214
215 static struct m68k_it the_ins; /* the instruction being assembled */
216
217 #define op(ex) ((ex)->exp.X_op)
218 #define adds(ex) ((ex)->exp.X_add_symbol)
219 #define subs(ex) ((ex)->exp.X_op_symbol)
220 #define offs(ex) ((ex)->exp.X_add_number)
221
222 /* Macros for adding things to the m68k_it struct */
223
224 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
225
226 /* Like addword, but goes BEFORE general operands */
227 static void
228 insop (w, opcode)
229 int w;
230 struct m68k_incant *opcode;
231 {
232 int z;
233 for(z=the_ins.numo;z>opcode->m_codenum;--z)
234 the_ins.opcode[z]=the_ins.opcode[z-1];
235 for(z=0;z<the_ins.nrel;z++)
236 the_ins.reloc[z].n+=2;
237 for (z = 0; z < the_ins.nfrag; z++)
238 the_ins.fragb[z].fragoff++;
239 the_ins.opcode[opcode->m_codenum]=w;
240 the_ins.numo++;
241 }
242
243 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
244 Blecch. */
245 static void
246 add_fix (width, exp, pc_rel, pc_fix)
247 char width;
248 struct m68k_exp *exp;
249 int pc_rel;
250 int pc_fix;
251 {
252 the_ins.reloc[the_ins.nrel].n = (((width)=='B')
253 ? (the_ins.numo*2-1)
254 : (((width)=='b')
255 ? (the_ins.numo*2+1)
256 : (the_ins.numo*2)));
257 the_ins.reloc[the_ins.nrel].exp = exp->exp;
258 the_ins.reloc[the_ins.nrel].wid = width;
259 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
260 #ifdef OBJ_ELF
261 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
262 #endif
263 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
264 }
265
266 /* Cause an extra frag to be generated here, inserting up to 10 bytes
267 (that value is chosen in the frag_var call in md_assemble). TYPE
268 is the subtype of the frag to be generated; its primary type is
269 rs_machine_dependent.
270
271 The TYPE parameter is also used by md_convert_frag_1 and
272 md_estimate_size_before_relax. The appropriate type of fixup will
273 be emitted by md_convert_frag_1.
274
275 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
276 static void
277 add_frag(add,off,type)
278 symbolS *add;
279 long off;
280 int type;
281 {
282 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
283 the_ins.fragb[the_ins.nfrag].fadd=add;
284 the_ins.fragb[the_ins.nfrag].foff=off;
285 the_ins.fragb[the_ins.nfrag++].fragty=type;
286 }
287
288 #define isvar(ex) \
289 (op (ex) != O_constant && op (ex) != O_big)
290
291 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
292 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
293 static int reverse_16_bits PARAMS ((int in));
294 static int reverse_8_bits PARAMS ((int in));
295 static void install_gen_operand PARAMS ((int mode, int val));
296 static void install_operand PARAMS ((int mode, int val));
297 static void s_bss PARAMS ((int));
298 static void s_data1 PARAMS ((int));
299 static void s_data2 PARAMS ((int));
300 static void s_even PARAMS ((int));
301 static void s_proc PARAMS ((int));
302 static void mri_chip PARAMS ((void));
303 static void s_chip PARAMS ((int));
304 static void s_fopt PARAMS ((int));
305 static void s_opt PARAMS ((int));
306 static void s_reg PARAMS ((int));
307 static void s_restore PARAMS ((int));
308 static void s_save PARAMS ((int));
309 static void s_mri_if PARAMS ((int));
310 static void s_mri_else PARAMS ((int));
311 static void s_mri_endi PARAMS ((int));
312 static void s_mri_break PARAMS ((int));
313 static void s_mri_next PARAMS ((int));
314 static void s_mri_for PARAMS ((int));
315 static void s_mri_endf PARAMS ((int));
316 static void s_mri_repeat PARAMS ((int));
317 static void s_mri_until PARAMS ((int));
318 static void s_mri_while PARAMS ((int));
319 static void s_mri_endw PARAMS ((int));
320
321 static int current_architecture;
322
323 struct m68k_cpu {
324 unsigned long arch;
325 const char *name;
326 int alias;
327 };
328
329 static const struct m68k_cpu archs[] = {
330 { m68000, "68000", 0 },
331 { m68010, "68010", 0 },
332 { m68020, "68020", 0 },
333 { m68030, "68030", 0 },
334 { m68040, "68040", 0 },
335 { m68060, "68060", 0 },
336 { cpu32, "cpu32", 0 },
337 { m68881, "68881", 0 },
338 { m68851, "68851", 0 },
339 /* Aliases (effectively, so far as gas is concerned) for the above
340 cpus. */
341 { m68020, "68k", 1 },
342 { m68000, "68302", 1 },
343 { m68000, "68008", 1 },
344 { m68000, "68ec000", 1 },
345 { m68000, "68hc000", 1 },
346 { m68000, "68hc001", 1 },
347 { m68020, "68ec020", 1 },
348 { m68030, "68ec030", 1 },
349 { m68040, "68ec040", 1 },
350 { cpu32, "68330", 1 },
351 { cpu32, "68331", 1 },
352 { cpu32, "68332", 1 },
353 { cpu32, "68333", 1 },
354 { cpu32, "68340", 1 },
355 { cpu32, "68360", 1 },
356 { m68881, "68882", 1 },
357 };
358
359 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
360
361 /* BCC68000 is for patching in an extra jmp instruction for long offsets
362 on the 68000. The 68000 doesn't support long branches with branchs */
363
364 /* This table desribes how you change sizes for the various types of variable
365 size expressions. This version only supports two kinds. */
366
367 /* Note that calls to frag_var need to specify the maximum expansion
368 needed; this is currently 10 bytes for DBCC. */
369
370 /* The fields are:
371 How far Forward this mode will reach:
372 How far Backward this mode will reach:
373 How many bytes this mode will add to the size of the frag
374 Which mode to go to if the offset won't fit in this one
375 */
376 relax_typeS md_relax_table[] =
377 {
378 {1, 1, 0, 0}, /* First entries aren't used */
379 {1, 1, 0, 0}, /* For no good reason except */
380 {1, 1, 0, 0}, /* that the VAX doesn't either */
381 {1, 1, 0, 0},
382
383 {(127), (-128), 0, TAB (ABRANCH, SHORT)},
384 {(32767), (-32768), 2, TAB (ABRANCH, LONG)},
385 {0, 0, 4, 0},
386 {1, 1, 0, 0},
387
388 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
389 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
390 {0, 0, 4, 0},
391 {1, 1, 0, 0},
392
393 {1, 1, 0, 0}, /* PCREL doesn't come BYTE */
394 {(32767), (-32768), 2, TAB (PCREL, LONG)},
395 {0, 0, 4, 0},
396 {1, 1, 0, 0},
397
398 {(127), (-128), 0, TAB (BCC68000, SHORT)},
399 {(32767), (-32768), 2, TAB (BCC68000, LONG)},
400 {0, 0, 6, 0}, /* jmp long space */
401 {1, 1, 0, 0},
402
403 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
404 {(32767), (-32768), 2, TAB (DBCC, LONG)},
405 {0, 0, 10, 0}, /* bra/jmp long space */
406 {1, 1, 0, 0},
407
408 {1, 1, 0, 0}, /* PCLEA doesn't come BYTE */
409 {32767, -32768, 2, TAB (PCLEA, LONG)},
410 {0, 0, 6, 0},
411 {1, 1, 0, 0},
412
413 /* For, e.g., jmp pcrel indexed. */
414 {125, -130, 0, TAB (PCINDEX, SHORT)},
415 {32765, -32770, 2, TAB (PCINDEX, LONG)},
416 {0, 0, 4, 0},
417 {1, 1, 0, 0},
418 };
419
420 /* These are the machine dependent pseudo-ops. These are included so
421 the assembler can work on the output from the SUN C compiler, which
422 generates these.
423 */
424
425 /* This table describes all the machine specific pseudo-ops the assembler
426 has to support. The fields are:
427 pseudo-op name without dot
428 function to call to execute this pseudo-op
429 Integer arg to pass to the function
430 */
431 const pseudo_typeS md_pseudo_table[] =
432 {
433 {"data1", s_data1, 0},
434 {"data2", s_data2, 0},
435 {"bss", s_bss, 0},
436 {"even", s_even, 0},
437 {"skip", s_space, 0},
438 {"proc", s_proc, 0},
439 #if defined (TE_SUN3) || defined (OBJ_ELF)
440 {"align", s_align_bytes, 0},
441 #endif
442 #ifdef OBJ_ELF
443 {"swbeg", s_ignore, 0},
444 #endif
445 {"extend", float_cons, 'x'},
446 {"ldouble", float_cons, 'x'},
447
448 /* The following pseudo-ops are supported for MRI compatibility. */
449 {"chip", s_chip, 0},
450 {"comline", s_space, 1},
451 {"fopt", s_fopt, 0},
452 {"mask2", s_ignore, 0},
453 {"opt", s_opt, 0},
454 {"reg", s_reg, 0},
455 {"restore", s_restore, 0},
456 {"save", s_save, 0},
457
458 {"if", s_mri_if, 0},
459 {"if.b", s_mri_if, 'b'},
460 {"if.w", s_mri_if, 'w'},
461 {"if.l", s_mri_if, 'l'},
462 {"else", s_mri_else, 0},
463 {"else.s", s_mri_else, 's'},
464 {"else.l", s_mri_else, 'l'},
465 {"endi", s_mri_endi, 0},
466 {"break", s_mri_break, 0},
467 {"break.s", s_mri_break, 's'},
468 {"break.l", s_mri_break, 'l'},
469 {"next", s_mri_next, 0},
470 {"next.s", s_mri_next, 's'},
471 {"next.l", s_mri_next, 'l'},
472 {"for", s_mri_for, 0},
473 {"for.b", s_mri_for, 'b'},
474 {"for.w", s_mri_for, 'w'},
475 {"for.l", s_mri_for, 'l'},
476 {"endf", s_mri_endf, 0},
477 {"repeat", s_mri_repeat, 0},
478 {"until", s_mri_until, 0},
479 {"until.b", s_mri_until, 'b'},
480 {"until.w", s_mri_until, 'w'},
481 {"until.l", s_mri_until, 'l'},
482 {"while", s_mri_while, 0},
483 {"while.b", s_mri_while, 'b'},
484 {"while.w", s_mri_while, 'w'},
485 {"while.l", s_mri_while, 'l'},
486 {"endw", s_mri_endw, 0},
487
488 {0, 0, 0}
489 };
490
491
492 /* The mote pseudo ops are put into the opcode table, since they
493 don't start with a . they look like opcodes to gas.
494 */
495 extern void obj_coff_section ();
496
497 CONST pseudo_typeS mote_pseudo_table[] =
498 {
499
500 {"dcl", cons, 4},
501 {"dc", cons, 2},
502 {"dcw", cons, 2},
503 {"dcb", cons, 1},
504
505 {"dsl", s_space, 4},
506 {"ds", s_space, 2},
507 {"dsw", s_space, 2},
508 {"dsb", s_space, 1},
509
510 {"xdef", s_globl, 0},
511 #ifdef OBJ_ELF
512 {"align", s_align_bytes, 0},
513 #else
514 {"align", s_align_ptwo, 0},
515 #endif
516 #ifdef M68KCOFF
517 {"sect", obj_coff_section, 0},
518 {"section", obj_coff_section, 0},
519 #endif
520 {0, 0, 0}
521 };
522
523 #define issbyte(x) ((x)>=-128 && (x)<=127)
524 #define isubyte(x) ((x)>=0 && (x)<=255)
525 #define issword(x) ((x)>=-32768 && (x)<=32767)
526 #define isuword(x) ((x)>=0 && (x)<=65535)
527
528 #define isbyte(x) ((x)>= -255 && (x)<=255)
529 #define isword(x) ((x)>=-65536 && (x)<=65535)
530 #define islong(x) (1)
531
532 extern char *input_line_pointer;
533
534 static char mklower_table[256];
535 #define mklower(c) (mklower_table[(unsigned char)(c)])
536 static char notend_table[256];
537 static char alt_notend_table[256];
538 #define notend(s) \
539 (! (notend_table[(unsigned char) *s] \
540 || (*s == ':' \
541 && alt_notend_table[(unsigned char) s[1]])))
542
543 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
544
545 #ifdef NO_PCREL_RELOCS
546
547 int
548 make_pcrel_absolute(fixP, add_number)
549 fixS *fixP;
550 long *add_number;
551 {
552 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
553
554 /* rewrite the PC relative instructions to absolute address ones.
555 * these are rumoured to be faster, and the apollo linker refuses
556 * to deal with the PC relative relocations.
557 */
558 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
559 {
560 opcode[0] = 0x4e;
561 opcode[1] = 0xf9;
562 }
563 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
564 {
565 opcode[0] = 0x4e;
566 opcode[1] = 0xb9;
567 }
568 else
569 as_fatal ("Unknown PC relative instruction");
570 *add_number -= 4;
571 return 0;
572 }
573
574 #endif /* NO_PCREL_RELOCS */
575
576 short
577 tc_coff_fix2rtype (fixP)
578 fixS *fixP;
579 {
580 if (fixP->fx_tcbit && fixP->fx_size == 4)
581 return R_RELLONG_NEG;
582 #ifdef NO_PCREL_RELOCS
583 know (fixP->fx_pcrel == 0);
584 return (fixP->fx_size == 1 ? R_RELBYTE
585 : fixP->fx_size == 2 ? R_DIR16
586 : R_DIR32);
587 #else
588 return (fixP->fx_pcrel ?
589 (fixP->fx_size == 1 ? R_PCRBYTE :
590 fixP->fx_size == 2 ? R_PCRWORD :
591 R_PCRLONG) :
592 (fixP->fx_size == 1 ? R_RELBYTE :
593 fixP->fx_size == 2 ? R_RELWORD :
594 R_RELLONG));
595 #endif
596 }
597
598 #endif
599
600 #ifdef OBJ_ELF
601
602 /* Compute the relocation code for a fixup of SIZE bytes, using pc
603 relative relocation if PCREL is non-zero. PIC says whether a special
604 pic relocation was requested. */
605
606 static bfd_reloc_code_real_type get_reloc_code
607 PARAMS ((int, int, enum pic_relocation));
608
609 static bfd_reloc_code_real_type
610 get_reloc_code (size, pcrel, pic)
611 int size;
612 int pcrel;
613 enum pic_relocation pic;
614 {
615 switch (pic)
616 {
617 case pic_got_pcrel:
618 switch (size)
619 {
620 case 1:
621 return BFD_RELOC_8_GOT_PCREL;
622 case 2:
623 return BFD_RELOC_16_GOT_PCREL;
624 case 4:
625 return BFD_RELOC_32_GOT_PCREL;
626 }
627 break;
628
629 case pic_got_off:
630 switch (size)
631 {
632 case 1:
633 return BFD_RELOC_8_GOTOFF;
634 case 2:
635 return BFD_RELOC_16_GOTOFF;
636 case 4:
637 return BFD_RELOC_32_GOTOFF;
638 }
639 break;
640
641 case pic_plt_pcrel:
642 switch (size)
643 {
644 case 1:
645 return BFD_RELOC_8_PLT_PCREL;
646 case 2:
647 return BFD_RELOC_16_PLT_PCREL;
648 case 4:
649 return BFD_RELOC_32_PLT_PCREL;
650 }
651 break;
652
653 case pic_plt_off:
654 switch (size)
655 {
656 case 1:
657 return BFD_RELOC_8_PLTOFF;
658 case 2:
659 return BFD_RELOC_16_PLTOFF;
660 case 4:
661 return BFD_RELOC_32_PLTOFF;
662 }
663 break;
664
665 case pic_none:
666 if (pcrel)
667 {
668 switch (size)
669 {
670 case 1:
671 return BFD_RELOC_8_PCREL;
672 case 2:
673 return BFD_RELOC_16_PCREL;
674 case 4:
675 return BFD_RELOC_32_PCREL;
676 }
677 }
678 else
679 {
680 switch (size)
681 {
682 case 1:
683 return BFD_RELOC_8;
684 case 2:
685 return BFD_RELOC_16;
686 case 4:
687 return BFD_RELOC_32;
688 }
689 }
690 }
691
692 as_bad ("Can not do %d byte %s%srelocation", size,
693 pcrel ? "pc-relative " : "",
694 pic == pic_none ? "" : "pic ");
695 return BFD_RELOC_NONE;
696 }
697
698 /* Here we decide which fixups can be adjusted to make them relative
699 to the beginning of the section instead of the symbol. Basically
700 we need to make sure that the dynamic relocations are done
701 correctly, so in some cases we force the original symbol to be
702 used. */
703 int
704 tc_m68k_fix_adjustable (fixP)
705 fixS *fixP;
706 {
707 /* Prevent all adjustments to global symbols. */
708 if (S_IS_EXTERNAL (fixP->fx_addsy))
709 return 0;
710
711 /* adjust_reloc_syms doesn't know about the GOT */
712 switch (fixP->fx_r_type)
713 {
714 case BFD_RELOC_8_GOT_PCREL:
715 case BFD_RELOC_16_GOT_PCREL:
716 case BFD_RELOC_32_GOT_PCREL:
717 case BFD_RELOC_8_GOTOFF:
718 case BFD_RELOC_16_GOTOFF:
719 case BFD_RELOC_32_GOTOFF:
720 case BFD_RELOC_8_PLT_PCREL:
721 case BFD_RELOC_16_PLT_PCREL:
722 case BFD_RELOC_32_PLT_PCREL:
723 case BFD_RELOC_8_PLTOFF:
724 case BFD_RELOC_16_PLTOFF:
725 case BFD_RELOC_32_PLTOFF:
726 return 0;
727
728 default:
729 return 1;
730 }
731 }
732
733 #else /* !OBJ_ELF */
734
735 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
736
737 #endif /* OBJ_ELF */
738
739 #ifdef BFD_ASSEMBLER
740
741 arelent *
742 tc_gen_reloc (section, fixp)
743 asection *section;
744 fixS *fixp;
745 {
746 arelent *reloc;
747 bfd_reloc_code_real_type code;
748
749 if (fixp->fx_tcbit)
750 abort ();
751
752 if (fixp->fx_r_type != BFD_RELOC_NONE)
753 code = fixp->fx_r_type;
754 else
755 {
756 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
757 switch (F (fixp->fx_size, fixp->fx_pcrel))
758 {
759 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
760 MAP (1, 0, BFD_RELOC_8);
761 MAP (2, 0, BFD_RELOC_16);
762 MAP (4, 0, BFD_RELOC_32);
763 MAP (1, 1, BFD_RELOC_8_PCREL);
764 MAP (2, 1, BFD_RELOC_16_PCREL);
765 MAP (4, 1, BFD_RELOC_32_PCREL);
766 default:
767 abort ();
768 }
769 }
770 #undef F
771 #undef MAP
772
773 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
774 assert (reloc != 0);
775 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
776 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
777 #ifndef OBJ_ELF
778 if (fixp->fx_pcrel)
779 reloc->addend = fixp->fx_addnumber;
780 else
781 reloc->addend = 0;
782 #else
783 if (!fixp->fx_pcrel)
784 reloc->addend = fixp->fx_addnumber;
785 else if ((fixp->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)
786 reloc->addend = (section->vma
787 + (fixp->fx_pcrel_adjust == 64
788 ? -1 : fixp->fx_pcrel_adjust)
789 + fixp->fx_addnumber
790 + md_pcrel_from (fixp));
791 else
792 reloc->addend = (fixp->fx_offset
793 + (fixp->fx_pcrel_adjust == 64
794 ? -1 : fixp->fx_pcrel_adjust));
795 #endif
796
797 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
798 assert (reloc->howto != 0);
799
800 return reloc;
801 }
802
803 #endif /* BFD_ASSEMBLER */
804
805 /* Handle of the OPCODE hash table. NULL means any use before
806 m68k_ip_begin() will crash. */
807 static struct hash_control *op_hash;
808 \f
809 /* Assemble an m68k instruction. */
810
811 void
812 m68k_ip (instring)
813 char *instring;
814 {
815 register char *p;
816 register struct m68k_op *opP;
817 register struct m68k_incant *opcode;
818 register const char *s;
819 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
820 char *pdot, *pdotmove;
821 enum m68k_size siz1, siz2;
822 char c;
823 int losing;
824 int opsfound;
825 char *crack_operand ();
826 LITTLENUM_TYPE words[6];
827 LITTLENUM_TYPE *wordp;
828 unsigned long ok_arch = 0;
829
830 if (*instring == ' ')
831 instring++; /* skip leading whitespace */
832
833 /* Scan up to end of operation-code, which MUST end in end-of-string
834 or exactly 1 space. */
835 pdot = 0;
836 for (p = instring; *p != '\0'; p++)
837 {
838 if (*p == ' ')
839 break;
840 if (*p == '.')
841 pdot = p;
842 }
843
844 if (p == instring)
845 {
846 the_ins.error = "No operator";
847 return;
848 }
849
850 /* p now points to the end of the opcode name, probably whitespace.
851 Make sure the name is null terminated by clobbering the
852 whitespace, look it up in the hash table, then fix it back.
853 Remove a dot, first, since the opcode tables have none. */
854 if (pdot != NULL)
855 {
856 for (pdotmove = pdot; pdotmove < p; pdotmove++)
857 *pdotmove = pdotmove[1];
858 p--;
859 }
860
861 c = *p;
862 *p = '\0';
863 opcode = (struct m68k_incant *) hash_find (op_hash, instring);
864 *p = c;
865
866 if (pdot != NULL)
867 {
868 for (pdotmove = p; pdotmove > pdot; pdotmove--)
869 *pdotmove = pdotmove[-1];
870 *pdot = '.';
871 ++p;
872 }
873
874 if (opcode == NULL)
875 {
876 the_ins.error = "Unknown operator";
877 return;
878 }
879
880 /* found a legitimate opcode, start matching operands */
881 while (*p == ' ')
882 ++p;
883
884 if (opcode->m_operands == 0)
885 {
886 char *old = input_line_pointer;
887 *old = '\n';
888 input_line_pointer = p;
889 /* Ahh - it's a motorola style psuedo op */
890 mote_pseudo_table[opcode->m_opnum].poc_handler
891 (mote_pseudo_table[opcode->m_opnum].poc_val);
892 input_line_pointer = old;
893 *old = 0;
894
895 return;
896 }
897
898 if (flag_mri && opcode->m_opnum == 0)
899 {
900 /* In MRI mode, random garbage is allowed after an instruction
901 which accepts no operands. */
902 the_ins.args = opcode->m_operands;
903 the_ins.numargs = opcode->m_opnum;
904 the_ins.numo = opcode->m_codenum;
905 the_ins.opcode[0] = getone (opcode);
906 the_ins.opcode[1] = gettwo (opcode);
907 return;
908 }
909
910 for (opP = &the_ins.operands[0]; *p; opP++)
911 {
912 p = crack_operand (p, opP);
913
914 if (opP->error)
915 {
916 the_ins.error = opP->error;
917 return;
918 }
919 }
920
921 opsfound = opP - &the_ins.operands[0];
922
923 /* This ugly hack is to support the floating pt opcodes in their
924 standard form. Essentially, we fake a first enty of type COP#1 */
925 if (opcode->m_operands[0] == 'I')
926 {
927 int n;
928
929 for (n = opsfound; n > 0; --n)
930 the_ins.operands[n] = the_ins.operands[n - 1];
931
932 memset ((char *) (&the_ins.operands[0]), '\0',
933 sizeof (the_ins.operands[0]));
934 the_ins.operands[0].mode = CONTROL;
935 the_ins.operands[0].reg = m68k_float_copnum;
936 opsfound++;
937 }
938
939 /* We've got the operands. Find an opcode that'll accept them */
940 for (losing = 0;;)
941 {
942 /* If we didn't get the right number of ops, or we have no
943 common model with this pattern then reject this pattern. */
944
945 if (opsfound != opcode->m_opnum
946 || ((opcode->m_arch & current_architecture) == 0))
947 {
948 ++losing;
949 ok_arch |= opcode->m_arch;
950 }
951 else
952 {
953 for (s = opcode->m_operands, opP = &the_ins.operands[0];
954 *s && !losing;
955 s += 2, opP++)
956 {
957 /* Warning: this switch is huge! */
958 /* I've tried to organize the cases into this order:
959 non-alpha first, then alpha by letter. Lower-case
960 goes directly before uppercase counterpart. */
961 /* Code with multiple case ...: gets sorted by the lowest
962 case ... it belongs to. I hope this makes sense. */
963 switch (*s)
964 {
965 case '!':
966 switch (opP->mode)
967 {
968 case IMMED:
969 case DREG:
970 case AREG:
971 case FPREG:
972 case CONTROL:
973 case AINC:
974 case ADEC:
975 case REGLST:
976 losing++;
977 break;
978 default:
979 break;
980 }
981 break;
982
983 case '`':
984 switch (opP->mode)
985 {
986 case IMMED:
987 case DREG:
988 case AREG:
989 case FPREG:
990 case CONTROL:
991 case AINC:
992 case REGLST:
993 case AINDR:
994 losing++;
995 break;
996 default:
997 break;
998 }
999 break;
1000
1001 case '#':
1002 if (opP->mode != IMMED)
1003 losing++;
1004 else if (s[1] == 'b'
1005 && ! isvar (&opP->disp)
1006 && (opP->disp.exp.X_op != O_constant
1007 || ! isbyte (opP->disp.exp.X_add_number)))
1008 losing++;
1009 else if (s[1] == 'w'
1010 && ! isvar (&opP->disp)
1011 && (opP->disp.exp.X_op != O_constant
1012 || ! isword (opP->disp.exp.X_add_number)))
1013 losing++;
1014 else if (s[1] == 'W'
1015 && ! isvar (&opP->disp)
1016 && (opP->disp.exp.X_op != O_constant
1017 || ! issword (opP->disp.exp.X_add_number)))
1018 losing++;
1019 break;
1020
1021 case '^':
1022 case 'T':
1023 if (opP->mode != IMMED)
1024 losing++;
1025 break;
1026
1027 case '$':
1028 if (opP->mode == AREG
1029 || opP->mode == CONTROL
1030 || opP->mode == FPREG
1031 || opP->mode == IMMED
1032 || opP->mode == REGLST
1033 || (opP->mode != ABSL
1034 && (opP->reg == PC
1035 || opP->reg == ZPC)))
1036 losing++;
1037 break;
1038
1039 case '%':
1040 if (opP->mode == CONTROL
1041 || opP->mode == FPREG
1042 || opP->mode == REGLST
1043 || opP->mode == IMMED
1044 || (opP->mode != ABSL
1045 && (opP->reg == PC
1046 || opP->reg == ZPC)))
1047 losing++;
1048 break;
1049
1050 case '&':
1051 switch (opP->mode)
1052 {
1053 case DREG:
1054 case AREG:
1055 case FPREG:
1056 case CONTROL:
1057 case IMMED:
1058 case AINC:
1059 case ADEC:
1060 case REGLST:
1061 losing++;
1062 break;
1063 case ABSL:
1064 break;
1065 default:
1066 if (opP->reg == PC
1067 || opP->reg == ZPC)
1068 losing++;
1069 break;
1070 }
1071 break;
1072
1073 case '*':
1074 if (opP->mode == CONTROL
1075 || opP->mode == FPREG
1076 || opP->mode == REGLST)
1077 losing++;
1078 break;
1079
1080 case '+':
1081 if (opP->mode != AINC)
1082 losing++;
1083 break;
1084
1085 case '-':
1086 if (opP->mode != ADEC)
1087 losing++;
1088 break;
1089
1090 case '/':
1091 switch (opP->mode)
1092 {
1093 case AREG:
1094 case CONTROL:
1095 case FPREG:
1096 case AINC:
1097 case ADEC:
1098 case IMMED:
1099 case REGLST:
1100 losing++;
1101 break;
1102 default:
1103 break;
1104 }
1105 break;
1106
1107 case ';':
1108 switch (opP->mode)
1109 {
1110 case AREG:
1111 case CONTROL:
1112 case FPREG:
1113 case REGLST:
1114 losing++;
1115 break;
1116 default:
1117 break;
1118 }
1119 break;
1120
1121 case '?':
1122 switch (opP->mode)
1123 {
1124 case AREG:
1125 case CONTROL:
1126 case FPREG:
1127 case AINC:
1128 case ADEC:
1129 case IMMED:
1130 case REGLST:
1131 losing++;
1132 break;
1133 case ABSL:
1134 break;
1135 default:
1136 if (opP->reg == PC || opP->reg == ZPC)
1137 losing++;
1138 break;
1139 }
1140 break;
1141
1142 case '@':
1143 switch (opP->mode)
1144 {
1145 case AREG:
1146 case CONTROL:
1147 case FPREG:
1148 case IMMED:
1149 case REGLST:
1150 losing++;
1151 break;
1152 default:
1153 break;
1154 }
1155 break;
1156
1157 case '~': /* For now! (JF FOO is this right?) */
1158 switch (opP->mode)
1159 {
1160 case DREG:
1161 case AREG:
1162 case CONTROL:
1163 case FPREG:
1164 case IMMED:
1165 case REGLST:
1166 losing++;
1167 break;
1168 case ABSL:
1169 break;
1170 default:
1171 if (opP->reg == PC
1172 || opP->reg == ZPC)
1173 losing++;
1174 break;
1175 }
1176 break;
1177
1178 case '3':
1179 if (opP->mode != CONTROL
1180 || (opP->reg != TT0 && opP->reg != TT1))
1181 losing++;
1182 break;
1183
1184 case 'A':
1185 if (opP->mode != AREG)
1186 losing++;
1187 break;
1188
1189 case 'a':
1190 if (opP->mode != AINDR)
1191 ++losing;
1192 break;
1193
1194 case 'B': /* FOO */
1195 if (opP->mode != ABSL
1196 || (flag_long_jumps
1197 && strncmp (instring, "jbsr", 4) == 0))
1198 losing++;
1199 break;
1200
1201 case 'C':
1202 if (opP->mode != CONTROL || opP->reg != CCR)
1203 losing++;
1204 break;
1205
1206 case 'd':
1207 if (opP->mode != DISP
1208 || opP->reg < ADDR0
1209 || opP->reg > ADDR7)
1210 losing++;
1211 break;
1212
1213 case 'D':
1214 if (opP->mode != DREG)
1215 losing++;
1216 break;
1217
1218 case 'F':
1219 if (opP->mode != FPREG)
1220 losing++;
1221 break;
1222
1223 case 'I':
1224 if (opP->mode != CONTROL
1225 || opP->reg < COP0
1226 || opP->reg > COP7)
1227 losing++;
1228 break;
1229
1230 case 'J':
1231 if (opP->mode != CONTROL
1232 || opP->reg < USP
1233 || opP->reg > last_movec_reg)
1234 losing++;
1235 else
1236 {
1237 const enum m68k_register *rp;
1238 for (rp = control_regs; *rp; rp++)
1239 if (*rp == opP->reg)
1240 break;
1241 if (*rp == 0)
1242 losing++;
1243 }
1244 break;
1245
1246 case 'k':
1247 if (opP->mode != IMMED)
1248 losing++;
1249 break;
1250
1251 case 'l':
1252 case 'L':
1253 if (opP->mode == DREG
1254 || opP->mode == AREG
1255 || opP->mode == FPREG)
1256 {
1257 if (s[1] == '8')
1258 losing++;
1259 else
1260 {
1261 switch (opP->mode)
1262 {
1263 case DREG:
1264 opP->mask = 1 << (opP->reg - DATA0);
1265 break;
1266 case AREG:
1267 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1268 break;
1269 case FPREG:
1270 opP->mask = 1 << (opP->reg - FP0 + 16);
1271 break;
1272 default:
1273 abort ();
1274 }
1275 opP->mode = REGLST;
1276 }
1277 }
1278 else if (opP->mode == CONTROL)
1279 {
1280 if (s[1] != '8')
1281 losing++;
1282 else
1283 {
1284 switch (opP->reg)
1285 {
1286 case FPI:
1287 opP->mask = 1 << 24;
1288 break;
1289 case FPS:
1290 opP->mask = 1 << 25;
1291 break;
1292 case FPC:
1293 opP->mask = 1 << 26;
1294 break;
1295 default:
1296 losing++;
1297 break;
1298 }
1299 opP->mode = REGLST;
1300 }
1301 }
1302 else if (opP->mode == ABSL
1303 && opP->disp.size == SIZE_UNSPEC
1304 && opP->disp.exp.X_op == O_constant)
1305 {
1306 /* This is what the MRI REG pseudo-op generates. */
1307 opP->mode = REGLST;
1308 opP->mask = opP->disp.exp.X_add_number;
1309 }
1310 else if (opP->mode != REGLST)
1311 losing++;
1312 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1313 losing++;
1314 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1315 losing++;
1316 break;
1317
1318 case 'M':
1319 if (opP->mode != IMMED)
1320 losing++;
1321 else if (opP->disp.exp.X_op != O_constant
1322 || ! issbyte (opP->disp.exp.X_add_number))
1323 losing++;
1324 else if (! m68k_quick
1325 && instring[3] != 'q'
1326 && instring[4] != 'q')
1327 losing++;
1328 break;
1329
1330 case 'O':
1331 if (opP->mode != DREG && opP->mode != IMMED)
1332 losing++;
1333 break;
1334
1335 case 'Q':
1336 if (opP->mode != IMMED)
1337 losing++;
1338 else if (opP->disp.exp.X_op != O_constant
1339 || opP->disp.exp.X_add_number < 1
1340 || opP->disp.exp.X_add_number > 8)
1341 losing++;
1342 else if (! m68k_quick
1343 && (strncmp (instring, "add", 3) == 0
1344 || strncmp (instring, "sub", 3) == 0)
1345 && instring[3] != 'q')
1346 losing++;
1347 break;
1348
1349 case 'R':
1350 if (opP->mode != DREG && opP->mode != AREG)
1351 losing++;
1352 break;
1353
1354 case 'r':
1355 if (opP->mode != AINDR
1356 && (opP->mode != BASE
1357 || (opP->reg != 0
1358 && opP->reg != ZADDR0)
1359 || opP->disp.exp.X_op != O_absent
1360 || ((opP->index.reg < DATA0
1361 || opP->index.reg > DATA7)
1362 && (opP->index.reg < ADDR0
1363 || opP->index.reg > ADDR7))
1364 || opP->index.size != SIZE_UNSPEC
1365 || opP->index.scale != 1))
1366 losing++;
1367 break;
1368
1369 case 's':
1370 if (opP->mode != CONTROL
1371 || ! (opP->reg == FPI
1372 || opP->reg == FPS
1373 || opP->reg == FPC))
1374 losing++;
1375 break;
1376
1377 case 'S':
1378 if (opP->mode != CONTROL || opP->reg != SR)
1379 losing++;
1380 break;
1381
1382 case 't':
1383 if (opP->mode != IMMED)
1384 losing++;
1385 else if (opP->disp.exp.X_op != O_constant
1386 || opP->disp.exp.X_add_number < 0
1387 || opP->disp.exp.X_add_number > 7)
1388 losing++;
1389 break;
1390
1391 case 'U':
1392 if (opP->mode != CONTROL || opP->reg != USP)
1393 losing++;
1394 break;
1395
1396 /* JF these are out of order. We could put them
1397 in order if we were willing to put up with
1398 bunches of #ifdef m68851s in the code.
1399
1400 Don't forget that you need these operands
1401 to use 68030 MMU instructions. */
1402 #ifndef NO_68851
1403 /* Memory addressing mode used by pflushr */
1404 case '|':
1405 if (opP->mode == CONTROL
1406 || opP->mode == FPREG
1407 || opP->mode == DREG
1408 || opP->mode == AREG
1409 || opP->mode == REGLST)
1410 losing++;
1411 /* We should accept immediate operands, but they
1412 supposedly have to be quad word, and we don't
1413 handle that. I would like to see what a Motorola
1414 assembler does before doing something here. */
1415 if (opP->mode == IMMED)
1416 losing++;
1417 break;
1418
1419 case 'f':
1420 if (opP->mode != CONTROL
1421 || (opP->reg != SFC && opP->reg != DFC))
1422 losing++;
1423 break;
1424
1425 case '0':
1426 if (opP->mode != CONTROL || opP->reg != TC)
1427 losing++;
1428 break;
1429
1430 case '1':
1431 if (opP->mode != CONTROL || opP->reg != AC)
1432 losing++;
1433 break;
1434
1435 case '2':
1436 if (opP->mode != CONTROL
1437 || (opP->reg != CAL
1438 && opP->reg != VAL
1439 && opP->reg != SCC))
1440 losing++;
1441 break;
1442
1443 case 'V':
1444 if (opP->mode != CONTROL
1445 || opP->reg != VAL)
1446 losing++;
1447 break;
1448
1449 case 'W':
1450 if (opP->mode != CONTROL
1451 || (opP->reg != DRP
1452 && opP->reg != SRP
1453 && opP->reg != CRP))
1454 losing++;
1455 break;
1456
1457 case 'X':
1458 if (opP->mode != CONTROL
1459 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1460 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1461 losing++;
1462 break;
1463
1464 case 'Y':
1465 if (opP->mode != CONTROL || opP->reg != PSR)
1466 losing++;
1467 break;
1468
1469 case 'Z':
1470 if (opP->mode != CONTROL || opP->reg != PCSR)
1471 losing++;
1472 break;
1473 #endif
1474 case 'c':
1475 if (opP->mode != CONTROL
1476 || (opP->reg != NC
1477 && opP->reg != IC
1478 && opP->reg != DC
1479 && opP->reg != BC))
1480 {
1481 losing++;
1482 } /* not a cache specifier. */
1483 break;
1484
1485 case '_':
1486 if (opP->mode != ABSL)
1487 ++losing;
1488 break;
1489
1490 default:
1491 abort ();
1492 } /* switch on type of operand */
1493
1494 if (losing)
1495 break;
1496 } /* for each operand */
1497 } /* if immediately wrong */
1498
1499 if (!losing)
1500 {
1501 break;
1502 } /* got it. */
1503
1504 opcode = opcode->m_next;
1505
1506 if (!opcode)
1507 {
1508 if (ok_arch
1509 && !(ok_arch & current_architecture))
1510 {
1511 char buf[200], *cp;
1512 int len;
1513 strcpy (buf,
1514 "invalid instruction for this architecture; needs ");
1515 cp = buf + strlen (buf);
1516 switch (ok_arch)
1517 {
1518 case mfloat:
1519 strcpy (cp, "fpu (68040, 68060 or 68881/68882)");
1520 break;
1521 case mmmu:
1522 strcpy (cp, "mmu (68030 or 68851)");
1523 break;
1524 case m68020up:
1525 strcpy (cp, "68020 or higher");
1526 break;
1527 case m68000up:
1528 strcpy (cp, "68000 or higher");
1529 break;
1530 case m68010up:
1531 strcpy (cp, "68010 or higher");
1532 break;
1533 default:
1534 {
1535 int got_one = 0, idx;
1536 for (idx = 0; idx < sizeof (archs) / sizeof (archs[0]);
1537 idx++)
1538 {
1539 if ((archs[idx].arch & ok_arch)
1540 && ! archs[idx].alias)
1541 {
1542 if (got_one)
1543 {
1544 strcpy (cp, " or ");
1545 cp += strlen (cp);
1546 }
1547 got_one = 1;
1548 strcpy (cp, archs[idx].name);
1549 cp += strlen (cp);
1550 }
1551 }
1552 }
1553 }
1554 len = cp - buf + 1;
1555 cp = malloc (len);
1556 strcpy (cp, buf);
1557 the_ins.error = cp;
1558 }
1559 else
1560 the_ins.error = "operands mismatch";
1561 return;
1562 } /* Fell off the end */
1563
1564 losing = 0;
1565 }
1566
1567 /* now assemble it */
1568
1569 the_ins.args = opcode->m_operands;
1570 the_ins.numargs = opcode->m_opnum;
1571 the_ins.numo = opcode->m_codenum;
1572 the_ins.opcode[0] = getone (opcode);
1573 the_ins.opcode[1] = gettwo (opcode);
1574
1575 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1576 {
1577 /* This switch is a doozy.
1578 Watch the first step; its a big one! */
1579 switch (s[0])
1580 {
1581
1582 case '*':
1583 case '~':
1584 case '%':
1585 case ';':
1586 case '@':
1587 case '!':
1588 case '&':
1589 case '$':
1590 case '?':
1591 case '/':
1592 case '`':
1593 #ifndef NO_68851
1594 case '|':
1595 #endif
1596 switch (opP->mode)
1597 {
1598 case IMMED:
1599 tmpreg = 0x3c; /* 7.4 */
1600 if (strchr ("bwl", s[1]))
1601 nextword = get_num (&opP->disp, 80);
1602 else
1603 nextword = get_num (&opP->disp, 0);
1604 if (isvar (&opP->disp))
1605 add_fix (s[1], &opP->disp, 0, 0);
1606 switch (s[1])
1607 {
1608 case 'b':
1609 if (!isbyte (nextword))
1610 opP->error = "operand out of range";
1611 addword (nextword);
1612 baseo = 0;
1613 break;
1614 case 'w':
1615 if (!isword (nextword))
1616 opP->error = "operand out of range";
1617 addword (nextword);
1618 baseo = 0;
1619 break;
1620 case 'W':
1621 if (!issword (nextword))
1622 opP->error = "operand out of range";
1623 addword (nextword);
1624 baseo = 0;
1625 break;
1626 case 'l':
1627 addword (nextword >> 16);
1628 addword (nextword);
1629 baseo = 0;
1630 break;
1631
1632 case 'f':
1633 baseo = 2;
1634 outro = 8;
1635 break;
1636 case 'F':
1637 baseo = 4;
1638 outro = 11;
1639 break;
1640 case 'x':
1641 baseo = 6;
1642 outro = 15;
1643 break;
1644 case 'p':
1645 baseo = 6;
1646 outro = -1;
1647 break;
1648 default:
1649 abort ();
1650 }
1651 if (!baseo)
1652 break;
1653
1654 /* We gotta put out some float */
1655 if (op (&opP->disp) != O_big)
1656 {
1657 valueT val;
1658 int gencnt;
1659
1660 /* Can other cases happen here? */
1661 if (op (&opP->disp) != O_constant)
1662 abort ();
1663
1664 val = (valueT) offs (&opP->disp);
1665 gencnt = 0;
1666 do
1667 {
1668 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
1669 val >>= LITTLENUM_NUMBER_OF_BITS;
1670 ++gencnt;
1671 }
1672 while (val != 0);
1673 offs (&opP->disp) = gencnt;
1674 }
1675 if (offs (&opP->disp) > 0)
1676 {
1677 if (offs (&opP->disp) > baseo)
1678 {
1679 as_warn ("Bignum too big for %c format; truncated",
1680 s[1]);
1681 offs (&opP->disp) = baseo;
1682 }
1683 baseo -= offs (&opP->disp);
1684 while (baseo--)
1685 addword (0);
1686 for (wordp = generic_bignum + offs (&opP->disp) - 1;
1687 offs (&opP->disp)--;
1688 --wordp)
1689 addword (*wordp);
1690 break;
1691 }
1692 gen_to_words (words, baseo, (long) outro);
1693 for (wordp = words; baseo--; wordp++)
1694 addword (*wordp);
1695 break;
1696 case DREG:
1697 tmpreg = opP->reg - DATA; /* 0.dreg */
1698 break;
1699 case AREG:
1700 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
1701 break;
1702 case AINDR:
1703 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
1704 break;
1705 case ADEC:
1706 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
1707 break;
1708 case AINC:
1709 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
1710 break;
1711 case DISP:
1712
1713 nextword = get_num (&opP->disp, 80);
1714
1715 if (opP->reg == PC
1716 && ! isvar (&opP->disp)
1717 && m68k_abspcadd)
1718 {
1719 opP->disp.exp.X_op = O_symbol;
1720 #ifndef BFD_ASSEMBLER
1721 opP->disp.exp.X_add_symbol = &abs_symbol;
1722 #else
1723 opP->disp.exp.X_add_symbol =
1724 section_symbol (absolute_section);
1725 #endif
1726 }
1727
1728 /* Force into index mode. Hope this works */
1729
1730 /* We do the first bit for 32-bit displacements, and the
1731 second bit for 16 bit ones. It is possible that we
1732 should make the default be WORD instead of LONG, but
1733 I think that'd break GCC, so we put up with a little
1734 inefficiency for the sake of working output. */
1735
1736 if (!issword (nextword)
1737 || (isvar (&opP->disp)
1738 && ((opP->disp.size == SIZE_UNSPEC
1739 && flag_short_refs == 0
1740 && cpu_of_arch (current_architecture) >= m68020)
1741 || opP->disp.size == SIZE_LONG)))
1742 {
1743 if (opP->reg == PC)
1744 tmpreg = 0x3B; /* 7.3 */
1745 else
1746 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1747 if (isvar (&opP->disp))
1748 {
1749 if (opP->reg == PC)
1750 {
1751 if (opP->disp.size == SIZE_LONG
1752 #ifdef OBJ_ELF
1753 /* If the displacement needs pic
1754 relocation it cannot be relaxed. */
1755 || opP->disp.pic_reloc != pic_none
1756 #endif
1757 )
1758 {
1759 addword (0x0170);
1760 add_fix ('l', &opP->disp, 1, 2);
1761 }
1762 else
1763 {
1764 add_frag (adds (&opP->disp),
1765 offs (&opP->disp),
1766 TAB (PCLEA, SZ_UNDEF));
1767 break;
1768 }
1769 }
1770 else
1771 {
1772 addword (0x0170);
1773 add_fix ('l', &opP->disp, 0, 0);
1774 }
1775 }
1776 else
1777 addword (0x0170);
1778 addword (nextword >> 16);
1779 }
1780 else
1781 {
1782 if (opP->reg == PC)
1783 tmpreg = 0x3A; /* 7.2 */
1784 else
1785 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
1786
1787 if (isvar (&opP->disp))
1788 {
1789 if (opP->reg == PC)
1790 {
1791 add_fix ('w', &opP->disp, 1, 0);
1792 }
1793 else
1794 add_fix ('w', &opP->disp, 0, 0);
1795 }
1796 }
1797 addword (nextword);
1798 break;
1799
1800 case POST:
1801 case PRE:
1802 case BASE:
1803 nextword = 0;
1804 baseo = get_num (&opP->disp, 80);
1805 if (opP->mode == POST || opP->mode == PRE)
1806 outro = get_num (&opP->odisp, 80);
1807 /* Figure out the `addressing mode'.
1808 Also turn on the BASE_DISABLE bit, if needed. */
1809 if (opP->reg == PC || opP->reg == ZPC)
1810 {
1811 tmpreg = 0x3b; /* 7.3 */
1812 if (opP->reg == ZPC)
1813 nextword |= 0x80;
1814 }
1815 else if (opP->reg == 0)
1816 {
1817 nextword |= 0x80;
1818 tmpreg = 0x30; /* 6.garbage */
1819 }
1820 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
1821 {
1822 nextword |= 0x80;
1823 tmpreg = 0x30 + opP->reg - ZADDR0;
1824 }
1825 else
1826 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
1827
1828 siz1 = opP->disp.size;
1829 if (opP->mode == POST || opP->mode == PRE)
1830 siz2 = opP->odisp.size;
1831 else
1832 siz2 = SIZE_UNSPEC;
1833
1834 /* Index register stuff */
1835 if (opP->index.reg != 0
1836 && opP->index.reg >= DATA
1837 && opP->index.reg <= ADDR7)
1838 {
1839 nextword |= (opP->index.reg - DATA) << 12;
1840
1841 if (opP->index.size == SIZE_UNSPEC
1842 || opP->index.size == SIZE_LONG)
1843 nextword |= 0x800;
1844
1845 if (cpu_of_arch (current_architecture) < m68020)
1846 {
1847 if (opP->index.scale != 1)
1848 {
1849 opP->error =
1850 "scale factor invalid on this architecture; needs 68020 or higher";
1851 }
1852 }
1853
1854 switch (opP->index.scale)
1855 {
1856 case 1:
1857 break;
1858 case 2:
1859 nextword |= 0x200;
1860 break;
1861 case 4:
1862 nextword |= 0x400;
1863 break;
1864 case 8:
1865 nextword |= 0x600;
1866 break;
1867 default:
1868 abort ();
1869 }
1870 /* IF its simple,
1871 GET US OUT OF HERE! */
1872
1873 /* Must be INDEX, with an index register. Address
1874 register cannot be ZERO-PC, and either :b was
1875 forced, or we know it will fit. For a 68000 or
1876 68010, force this mode anyways, because the
1877 larger modes aren't supported. */
1878 if (opP->mode == BASE
1879 && ((opP->reg >= ADDR0
1880 && opP->reg <= ADDR7)
1881 || opP->reg == PC))
1882 {
1883 if (siz1 == SIZE_BYTE
1884 || cpu_of_arch (current_architecture) < m68020
1885 || (siz1 == SIZE_UNSPEC
1886 && ! isvar (&opP->disp)
1887 && issbyte (baseo)))
1888 {
1889 nextword += baseo & 0xff;
1890 addword (nextword);
1891 if (isvar (&opP->disp))
1892 {
1893 /* Do a byte relocation. If it doesn't
1894 fit (possible on m68000) let the
1895 fixup processing complain later. */
1896 if (opP->reg == PC)
1897 add_fix ('B', &opP->disp, 1, 1);
1898 else
1899 add_fix ('B', &opP->disp, 0, 0);
1900 }
1901 else if (siz1 != SIZE_BYTE)
1902 {
1903 if (siz1 != SIZE_UNSPEC)
1904 as_warn ("Forcing byte displacement");
1905 if (! issbyte (baseo))
1906 opP->error = "byte displacement out of range";
1907 }
1908
1909 break;
1910 }
1911 else if (siz1 == SIZE_UNSPEC
1912 && opP->reg == PC
1913 && isvar (&opP->disp)
1914 && subs (&opP->disp) == NULL
1915 #ifdef OBJ_ELF
1916 /* If the displacement needs pic
1917 relocation it cannot be relaxed. */
1918 && opP->disp.pic_reloc == pic_none
1919 #endif
1920 )
1921 {
1922 nextword += baseo & 0xff;
1923 addword (nextword);
1924 add_frag (adds (&opP->disp), offs (&opP->disp),
1925 TAB (PCINDEX, SZ_UNDEF));
1926
1927 break;
1928 }
1929 }
1930 }
1931 else
1932 {
1933 nextword |= 0x40; /* No index reg */
1934 if (opP->index.reg >= ZDATA0
1935 && opP->index.reg <= ZDATA7)
1936 nextword |= (opP->index.reg - ZDATA0) << 12;
1937 else if (opP->index.reg >= ZADDR0
1938 || opP->index.reg <= ZADDR7)
1939 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
1940 }
1941
1942 /* It isn't simple. */
1943
1944 if (cpu_of_arch (current_architecture) < m68020)
1945 opP->error =
1946 "invalid operand mode for this architecture; needs 68020 or higher";
1947
1948 nextword |= 0x100;
1949 /* If the guy specified a width, we assume that it is
1950 wide enough. Maybe it isn't. If so, we lose. */
1951 switch (siz1)
1952 {
1953 case SIZE_UNSPEC:
1954 if (isvar (&opP->disp)
1955 ? m68k_rel32
1956 : ! issword (baseo))
1957 {
1958 siz1 = SIZE_LONG;
1959 nextword |= 0x30;
1960 }
1961 else if (! isvar (&opP->disp) && baseo == 0)
1962 nextword |= 0x10;
1963 else
1964 {
1965 nextword |= 0x20;
1966 siz1 = SIZE_WORD;
1967 }
1968 break;
1969 case SIZE_BYTE:
1970 as_warn (":b not permitted; defaulting to :w");
1971 /* Fall through. */
1972 case SIZE_WORD:
1973 nextword |= 0x20;
1974 break;
1975 case SIZE_LONG:
1976 nextword |= 0x30;
1977 break;
1978 }
1979
1980 /* Figure out innner displacement stuff */
1981 if (opP->mode == POST || opP->mode == PRE)
1982 {
1983 switch (siz2)
1984 {
1985 case SIZE_UNSPEC:
1986 if (isvar (&opP->odisp)
1987 ? m68k_rel32
1988 : ! issword (outro))
1989 {
1990 siz2 = SIZE_LONG;
1991 nextword |= 0x3;
1992 }
1993 else if (! isvar (&opP->odisp) && outro == 0)
1994 nextword |= 0x1;
1995 else
1996 {
1997 nextword |= 0x2;
1998 siz2 = SIZE_WORD;
1999 }
2000 break;
2001 case 1:
2002 as_warn (":b not permitted; defaulting to :w");
2003 /* Fall through. */
2004 case 2:
2005 nextword |= 0x2;
2006 break;
2007 case 3:
2008 nextword |= 0x3;
2009 break;
2010 }
2011 if (opP->mode == POST
2012 && (nextword & 0x40) == 0)
2013 nextword |= 0x04;
2014 }
2015 addword (nextword);
2016
2017 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2018 {
2019 if (opP->reg == PC || opP->reg == ZPC)
2020 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2021 else
2022 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2023 }
2024 if (siz1 == SIZE_LONG)
2025 addword (baseo >> 16);
2026 if (siz1 != SIZE_UNSPEC)
2027 addword (baseo);
2028
2029 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2030 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2031 if (siz2 == SIZE_LONG)
2032 addword (outro >> 16);
2033 if (siz2 != SIZE_UNSPEC)
2034 addword (outro);
2035
2036 break;
2037
2038 case ABSL:
2039 nextword = get_num (&opP->disp, 80);
2040 switch (opP->disp.size)
2041 {
2042 default:
2043 abort ();
2044 case SIZE_UNSPEC:
2045 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2046 {
2047 tmpreg = 0x38; /* 7.0 */
2048 addword (nextword);
2049 break;
2050 }
2051 /* Don't generate pc relative code on 68010 and
2052 68000. */
2053 if (isvar (&opP->disp)
2054 && !subs (&opP->disp)
2055 && adds (&opP->disp)
2056 #ifdef OBJ_ELF
2057 /* If the displacement needs pic relocation it
2058 cannot be relaxed. */
2059 && opP->disp.pic_reloc == pic_none
2060 #endif
2061 && S_GET_SEGMENT (adds (&opP->disp)) == now_seg
2062 && cpu_of_arch (current_architecture) >= m68020
2063 && !flag_long_jumps
2064 && !strchr ("~%&$?", s[0]))
2065 {
2066 tmpreg = 0x3A; /* 7.2 */
2067 add_frag (adds (&opP->disp),
2068 offs (&opP->disp),
2069 TAB (PCREL, SZ_UNDEF));
2070 break;
2071 }
2072 /* Fall through into long */
2073 case SIZE_LONG:
2074 if (isvar (&opP->disp))
2075 add_fix ('l', &opP->disp, 0, 0);
2076
2077 tmpreg = 0x39;/* 7.1 mode */
2078 addword (nextword >> 16);
2079 addword (nextword);
2080 break;
2081
2082 case SIZE_WORD: /* Word */
2083 if (isvar (&opP->disp))
2084 add_fix ('w', &opP->disp, 0, 0);
2085
2086 tmpreg = 0x38;/* 7.0 mode */
2087 addword (nextword);
2088 break;
2089 }
2090 break;
2091 case CONTROL:
2092 case FPREG:
2093 default:
2094 as_bad ("unknown/incorrect operand");
2095 /* abort(); */
2096 }
2097 install_gen_operand (s[1], tmpreg);
2098 break;
2099
2100 case '#':
2101 case '^':
2102 switch (s[1])
2103 { /* JF: I hate floating point! */
2104 case 'j':
2105 tmpreg = 70;
2106 break;
2107 case '8':
2108 tmpreg = 20;
2109 break;
2110 case 'C':
2111 tmpreg = 50;
2112 break;
2113 case '3':
2114 default:
2115 tmpreg = 80;
2116 break;
2117 }
2118 tmpreg = get_num (&opP->disp, tmpreg);
2119 if (isvar (&opP->disp))
2120 add_fix (s[1], &opP->disp, 0, 0);
2121 switch (s[1])
2122 {
2123 case 'b': /* Danger: These do no check for
2124 certain types of overflow.
2125 user beware! */
2126 if (!isbyte (tmpreg))
2127 opP->error = "out of range";
2128 insop (tmpreg, opcode);
2129 if (isvar (&opP->disp))
2130 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2131 break;
2132 case 'w':
2133 if (!isword (tmpreg))
2134 opP->error = "out of range";
2135 insop (tmpreg, opcode);
2136 if (isvar (&opP->disp))
2137 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2138 break;
2139 case 'W':
2140 if (!issword (tmpreg))
2141 opP->error = "out of range";
2142 insop (tmpreg, opcode);
2143 if (isvar (&opP->disp))
2144 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2145 break;
2146 case 'l':
2147 /* Because of the way insop works, we put these two out
2148 backwards. */
2149 insop (tmpreg, opcode);
2150 insop (tmpreg >> 16, opcode);
2151 if (isvar (&opP->disp))
2152 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2153 break;
2154 case '3':
2155 tmpreg &= 0xFF;
2156 case '8':
2157 case 'C':
2158 install_operand (s[1], tmpreg);
2159 break;
2160 default:
2161 abort ();
2162 }
2163 break;
2164
2165 case '+':
2166 case '-':
2167 case 'A':
2168 case 'a':
2169 install_operand (s[1], opP->reg - ADDR);
2170 break;
2171
2172 case 'B':
2173 tmpreg = get_num (&opP->disp, 80);
2174 switch (s[1])
2175 {
2176 case 'B':
2177 /* The pc_fix argument winds up in fx_pcrel_adjust,
2178 which is a char, and may therefore be unsigned. We
2179 want to pass -1, but we pass 64 instead, and convert
2180 back in md_pcrel_from. */
2181 add_fix ('B', &opP->disp, 1, 64);
2182 break;
2183 case 'W':
2184 add_fix ('w', &opP->disp, 1, 0);
2185 addword (0);
2186 break;
2187 case 'L':
2188 long_branch:
2189 if (cpu_of_arch (current_architecture) < m68020)
2190 as_warn ("Can't use long branches on 68000/68010");
2191 the_ins.opcode[the_ins.numo - 1] |= 0xff;
2192 add_fix ('l', &opP->disp, 1, 0);
2193 addword (0);
2194 addword (0);
2195 break;
2196 case 'g':
2197 if (subs (&opP->disp)) /* We can't relax it */
2198 goto long_branch;
2199
2200 #ifdef OBJ_ELF
2201 /* If the displacement needs pic relocation it cannot be
2202 relaxed. */
2203 if (opP->disp.pic_reloc != pic_none)
2204 goto long_branch;
2205 #endif
2206
2207 /* This could either be a symbol, or an absolute
2208 address. No matter, the frag hacking will finger it
2209 out. Not quite: it can't switch from BRANCH to
2210 BCC68000 for the case where opnd is absolute (it
2211 needs to use the 68000 hack since no conditional abs
2212 jumps). */
2213 if (((cpu_of_arch (current_architecture) < m68020)
2214 || (0 == adds (&opP->disp)))
2215 && (the_ins.opcode[0] >= 0x6200)
2216 && (the_ins.opcode[0] <= 0x6f00))
2217 add_frag (adds (&opP->disp), offs (&opP->disp),
2218 TAB (BCC68000, SZ_UNDEF));
2219 else
2220 add_frag (adds (&opP->disp), offs (&opP->disp),
2221 TAB (ABRANCH, SZ_UNDEF));
2222 break;
2223 case 'w':
2224 if (isvar (&opP->disp))
2225 {
2226 #if 1
2227 /* check for DBcc instruction */
2228 if ((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2229 {
2230 /* size varies if patch */
2231 /* needed for long form */
2232 add_frag (adds (&opP->disp), offs (&opP->disp),
2233 TAB (DBCC, SZ_UNDEF));
2234 break;
2235 }
2236 #endif
2237 add_fix ('w', &opP->disp, 1, 0);
2238 }
2239 addword (0);
2240 break;
2241 case 'C': /* Fixed size LONG coproc branches */
2242 add_fix ('l', &opP->disp, 1, 0);
2243 addword (0);
2244 addword (0);
2245 break;
2246 case 'c': /* Var size Coprocesssor branches */
2247 if (subs (&opP->disp))
2248 {
2249 add_fix ('l', &opP->disp, 1, 0);
2250 add_frag ((symbolS *) 0, (long) 0, TAB (FBRANCH, LONG));
2251 }
2252 else if (adds (&opP->disp))
2253 add_frag (adds (&opP->disp), offs (&opP->disp),
2254 TAB (FBRANCH, SZ_UNDEF));
2255 else
2256 {
2257 /* add_frag((symbolS *) 0, offs(&opP->disp),
2258 TAB(FBRANCH,SHORT)); */
2259 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2260 add_fix ('l', &opP->disp, 1, 0);
2261 addword (0);
2262 addword (0);
2263 }
2264 break;
2265 default:
2266 abort ();
2267 }
2268 break;
2269
2270 case 'C': /* Ignore it */
2271 break;
2272
2273 case 'd': /* JF this is a kludge */
2274 install_operand ('s', opP->reg - ADDR);
2275 tmpreg = get_num (&opP->disp, 80);
2276 if (!issword (tmpreg))
2277 {
2278 as_warn ("Expression out of range, using 0");
2279 tmpreg = 0;
2280 }
2281 addword (tmpreg);
2282 break;
2283
2284 case 'D':
2285 install_operand (s[1], opP->reg - DATA);
2286 break;
2287
2288 case 'F':
2289 install_operand (s[1], opP->reg - FP0);
2290 break;
2291
2292 case 'I':
2293 tmpreg = opP->reg - COP0;
2294 install_operand (s[1], tmpreg);
2295 break;
2296
2297 case 'J': /* JF foo */
2298 switch (opP->reg)
2299 {
2300 case SFC:
2301 tmpreg = 0x000;
2302 break;
2303 case DFC:
2304 tmpreg = 0x001;
2305 break;
2306 case CACR:
2307 tmpreg = 0x002;
2308 break;
2309 case TC:
2310 tmpreg = 0x003;
2311 break;
2312 case ITT0:
2313 tmpreg = 0x004;
2314 break;
2315 case ITT1:
2316 tmpreg = 0x005;
2317 break;
2318 case DTT0:
2319 tmpreg = 0x006;
2320 break;
2321 case DTT1:
2322 tmpreg = 0x007;
2323 break;
2324 case BUSCR:
2325 tmpreg = 0x008;
2326 break;
2327
2328 case USP:
2329 tmpreg = 0x800;
2330 break;
2331 case VBR:
2332 tmpreg = 0x801;
2333 break;
2334 case CAAR:
2335 tmpreg = 0x802;
2336 break;
2337 case MSP:
2338 tmpreg = 0x803;
2339 break;
2340 case ISP:
2341 tmpreg = 0x804;
2342 break;
2343 case MMUSR:
2344 tmpreg = 0x805;
2345 break;
2346 case URP:
2347 tmpreg = 0x806;
2348 break;
2349 case SRP:
2350 tmpreg = 0x807;
2351 break;
2352 case PCR:
2353 tmpreg = 0x808;
2354 break;
2355 default:
2356 abort ();
2357 }
2358 install_operand (s[1], tmpreg);
2359 break;
2360
2361 case 'k':
2362 tmpreg = get_num (&opP->disp, 55);
2363 install_operand (s[1], tmpreg & 0x7f);
2364 break;
2365
2366 case 'l':
2367 tmpreg = opP->mask;
2368 if (s[1] == 'w')
2369 {
2370 if (tmpreg & 0x7FF0000)
2371 as_bad ("Floating point register in register list");
2372 insop (reverse_16_bits (tmpreg), opcode);
2373 }
2374 else
2375 {
2376 if (tmpreg & 0x700FFFF)
2377 as_bad ("Wrong register in floating-point reglist");
2378 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2379 }
2380 break;
2381
2382 case 'L':
2383 tmpreg = opP->mask;
2384 if (s[1] == 'w')
2385 {
2386 if (tmpreg & 0x7FF0000)
2387 as_bad ("Floating point register in register list");
2388 insop (tmpreg, opcode);
2389 }
2390 else if (s[1] == '8')
2391 {
2392 if (tmpreg & 0x0FFFFFF)
2393 as_bad ("incorrect register in reglist");
2394 install_operand (s[1], tmpreg >> 24);
2395 }
2396 else
2397 {
2398 if (tmpreg & 0x700FFFF)
2399 as_bad ("wrong register in floating-point reglist");
2400 else
2401 install_operand (s[1], tmpreg >> 16);
2402 }
2403 break;
2404
2405 case 'M':
2406 install_operand (s[1], get_num (&opP->disp, 60));
2407 break;
2408
2409 case 'O':
2410 tmpreg = ((opP->mode == DREG)
2411 ? 0x20 + opP->reg - DATA
2412 : (get_num (&opP->disp, 40) & 0x1F));
2413 install_operand (s[1], tmpreg);
2414 break;
2415
2416 case 'Q':
2417 tmpreg = get_num (&opP->disp, 10);
2418 if (tmpreg == 8)
2419 tmpreg = 0;
2420 install_operand (s[1], tmpreg);
2421 break;
2422
2423 case 'R':
2424 /* This depends on the fact that ADDR registers are eight
2425 more than their corresponding DATA regs, so the result
2426 will have the ADDR_REG bit set */
2427 install_operand (s[1], opP->reg - DATA);
2428 break;
2429
2430 case 'r':
2431 if (opP->mode == AINDR)
2432 install_operand (s[1], opP->reg - DATA);
2433 else
2434 install_operand (s[1], opP->index.reg - DATA);
2435 break;
2436
2437 case 's':
2438 if (opP->reg == FPI)
2439 tmpreg = 0x1;
2440 else if (opP->reg == FPS)
2441 tmpreg = 0x2;
2442 else if (opP->reg == FPC)
2443 tmpreg = 0x4;
2444 else
2445 abort ();
2446 install_operand (s[1], tmpreg);
2447 break;
2448
2449 case 'S': /* Ignore it */
2450 break;
2451
2452 case 'T':
2453 install_operand (s[1], get_num (&opP->disp, 30));
2454 break;
2455
2456 case 'U': /* Ignore it */
2457 break;
2458
2459 case 'c':
2460 switch (opP->reg)
2461 {
2462 case NC:
2463 tmpreg = 0;
2464 break;
2465 case DC:
2466 tmpreg = 1;
2467 break;
2468 case IC:
2469 tmpreg = 2;
2470 break;
2471 case BC:
2472 tmpreg = 3;
2473 break;
2474 default:
2475 as_fatal ("failed sanity check");
2476 } /* switch on cache token */
2477 install_operand (s[1], tmpreg);
2478 break;
2479 #ifndef NO_68851
2480 /* JF: These are out of order, I fear. */
2481 case 'f':
2482 switch (opP->reg)
2483 {
2484 case SFC:
2485 tmpreg = 0;
2486 break;
2487 case DFC:
2488 tmpreg = 1;
2489 break;
2490 default:
2491 abort ();
2492 }
2493 install_operand (s[1], tmpreg);
2494 break;
2495
2496 case '0':
2497 case '1':
2498 case '2':
2499 switch (opP->reg)
2500 {
2501 case TC:
2502 tmpreg = 0;
2503 break;
2504 case CAL:
2505 tmpreg = 4;
2506 break;
2507 case VAL:
2508 tmpreg = 5;
2509 break;
2510 case SCC:
2511 tmpreg = 6;
2512 break;
2513 case AC:
2514 tmpreg = 7;
2515 break;
2516 default:
2517 abort ();
2518 }
2519 install_operand (s[1], tmpreg);
2520 break;
2521
2522 case 'V':
2523 if (opP->reg == VAL)
2524 break;
2525 abort ();
2526
2527 case 'W':
2528 switch (opP->reg)
2529 {
2530 case DRP:
2531 tmpreg = 1;
2532 break;
2533 case SRP:
2534 tmpreg = 2;
2535 break;
2536 case CRP:
2537 tmpreg = 3;
2538 break;
2539 default:
2540 abort ();
2541 }
2542 install_operand (s[1], tmpreg);
2543 break;
2544
2545 case 'X':
2546 switch (opP->reg)
2547 {
2548 case BAD:
2549 case BAD + 1:
2550 case BAD + 2:
2551 case BAD + 3:
2552 case BAD + 4:
2553 case BAD + 5:
2554 case BAD + 6:
2555 case BAD + 7:
2556 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2557 break;
2558
2559 case BAC:
2560 case BAC + 1:
2561 case BAC + 2:
2562 case BAC + 3:
2563 case BAC + 4:
2564 case BAC + 5:
2565 case BAC + 6:
2566 case BAC + 7:
2567 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2568 break;
2569
2570 default:
2571 abort ();
2572 }
2573 install_operand (s[1], tmpreg);
2574 break;
2575 case 'Y':
2576 know (opP->reg == PSR);
2577 break;
2578 case 'Z':
2579 know (opP->reg == PCSR);
2580 break;
2581 #endif /* m68851 */
2582 case '3':
2583 switch (opP->reg)
2584 {
2585 case TT0:
2586 tmpreg = 2;
2587 break;
2588 case TT1:
2589 tmpreg = 3;
2590 break;
2591 default:
2592 abort ();
2593 }
2594 install_operand (s[1], tmpreg);
2595 break;
2596 case 't':
2597 tmpreg = get_num (&opP->disp, 20);
2598 install_operand (s[1], tmpreg);
2599 break;
2600 case '_': /* used only for move16 absolute 32-bit address */
2601 tmpreg = get_num (&opP->disp, 80);
2602 addword (tmpreg >> 16);
2603 addword (tmpreg & 0xFFFF);
2604 break;
2605 default:
2606 abort ();
2607 }
2608 }
2609
2610 /* By the time whe get here (FINALLY) the_ins contains the complete
2611 instruction, ready to be emitted. . . */
2612 }
2613
2614 static int
2615 reverse_16_bits (in)
2616 int in;
2617 {
2618 int out = 0;
2619 int n;
2620
2621 static int mask[16] =
2622 {
2623 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2624 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
2625 };
2626 for (n = 0; n < 16; n++)
2627 {
2628 if (in & mask[n])
2629 out |= mask[15 - n];
2630 }
2631 return out;
2632 } /* reverse_16_bits() */
2633
2634 static int
2635 reverse_8_bits (in)
2636 int in;
2637 {
2638 int out = 0;
2639 int n;
2640
2641 static int mask[8] =
2642 {
2643 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
2644 };
2645
2646 for (n = 0; n < 8; n++)
2647 {
2648 if (in & mask[n])
2649 out |= mask[7 - n];
2650 }
2651 return out;
2652 } /* reverse_8_bits() */
2653
2654 /* Cause an extra frag to be generated here, inserting up to 10 bytes
2655 (that value is chosen in the frag_var call in md_assemble). TYPE
2656 is the subtype of the frag to be generated; its primary type is
2657 rs_machine_dependent.
2658
2659 The TYPE parameter is also used by md_convert_frag_1 and
2660 md_estimate_size_before_relax. The appropriate type of fixup will
2661 be emitted by md_convert_frag_1.
2662
2663 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
2664 static void
2665 install_operand (mode, val)
2666 int mode;
2667 int val;
2668 {
2669 switch (mode)
2670 {
2671 case 's':
2672 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
2673 break;
2674 case 'd':
2675 the_ins.opcode[0] |= val << 9;
2676 break;
2677 case '1':
2678 the_ins.opcode[1] |= val << 12;
2679 break;
2680 case '2':
2681 the_ins.opcode[1] |= val << 6;
2682 break;
2683 case '3':
2684 the_ins.opcode[1] |= val;
2685 break;
2686 case '4':
2687 the_ins.opcode[2] |= val << 12;
2688 break;
2689 case '5':
2690 the_ins.opcode[2] |= val << 6;
2691 break;
2692 case '6':
2693 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
2694 three words long! */
2695 the_ins.numo++;
2696 the_ins.opcode[2] |= val;
2697 break;
2698 case '7':
2699 the_ins.opcode[1] |= val << 7;
2700 break;
2701 case '8':
2702 the_ins.opcode[1] |= val << 10;
2703 break;
2704 #ifndef NO_68851
2705 case '9':
2706 the_ins.opcode[1] |= val << 5;
2707 break;
2708 #endif
2709
2710 case 't':
2711 the_ins.opcode[1] |= (val << 10) | (val << 7);
2712 break;
2713 case 'D':
2714 the_ins.opcode[1] |= (val << 12) | val;
2715 break;
2716 case 'g':
2717 the_ins.opcode[0] |= val = 0xff;
2718 break;
2719 case 'i':
2720 the_ins.opcode[0] |= val << 9;
2721 break;
2722 case 'C':
2723 the_ins.opcode[1] |= val;
2724 break;
2725 case 'j':
2726 the_ins.opcode[1] |= val;
2727 the_ins.numo++; /* What a hack */
2728 break;
2729 case 'k':
2730 the_ins.opcode[1] |= val << 4;
2731 break;
2732 case 'b':
2733 case 'w':
2734 case 'W':
2735 case 'l':
2736 break;
2737 case 'e':
2738 the_ins.opcode[0] |= (val << 6);
2739 break;
2740 case 'L':
2741 the_ins.opcode[1] = (val >> 16);
2742 the_ins.opcode[2] = val & 0xffff;
2743 break;
2744 case 'c':
2745 default:
2746 as_fatal ("failed sanity check.");
2747 }
2748 } /* install_operand() */
2749
2750 static void
2751 install_gen_operand (mode, val)
2752 int mode;
2753 int val;
2754 {
2755 switch (mode)
2756 {
2757 case 's':
2758 the_ins.opcode[0] |= val;
2759 break;
2760 case 'd':
2761 /* This is a kludge!!! */
2762 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
2763 break;
2764 case 'b':
2765 case 'w':
2766 case 'l':
2767 case 'f':
2768 case 'F':
2769 case 'x':
2770 case 'p':
2771 the_ins.opcode[0] |= val;
2772 break;
2773 /* more stuff goes here */
2774 default:
2775 as_fatal ("failed sanity check.");
2776 }
2777 } /* install_gen_operand() */
2778
2779 /*
2780 * verify that we have some number of paren pairs, do m68k_ip_op(), and
2781 * then deal with the bitfield hack.
2782 */
2783
2784 static char *
2785 crack_operand (str, opP)
2786 register char *str;
2787 register struct m68k_op *opP;
2788 {
2789 register int parens;
2790 register int c;
2791 register char *beg_str;
2792 int inquote = 0;
2793
2794 if (!str)
2795 {
2796 return str;
2797 }
2798 beg_str = str;
2799 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
2800 {
2801 if (! inquote)
2802 {
2803 if (*str == '(')
2804 parens++;
2805 else if (*str == ')')
2806 {
2807 if (!parens)
2808 { /* ERROR */
2809 opP->error = "Extra )";
2810 return str;
2811 }
2812 --parens;
2813 }
2814 }
2815 if (flag_mri && *str == '\'')
2816 inquote = ! inquote;
2817 }
2818 if (!*str && parens)
2819 { /* ERROR */
2820 opP->error = "Missing )";
2821 return str;
2822 }
2823 c = *str;
2824 *str = '\0';
2825 if (m68k_ip_op (beg_str, opP) != 0)
2826 {
2827 *str = c;
2828 return str;
2829 }
2830 *str = c;
2831 if (c == '}')
2832 c = *++str; /* JF bitfield hack */
2833 if (c)
2834 {
2835 c = *++str;
2836 if (!c)
2837 as_bad ("Missing operand");
2838 }
2839 return str;
2840 }
2841
2842 /* This is the guts of the machine-dependent assembler. STR points to a
2843 machine dependent instruction. This function is supposed to emit
2844 the frags/bytes it assembles to.
2845 */
2846
2847 void
2848 insert_reg (regname, regnum)
2849 char *regname;
2850 int regnum;
2851 {
2852 char buf[100];
2853 int i;
2854
2855 #ifdef REGISTER_PREFIX
2856 if (!flag_reg_prefix_optional)
2857 {
2858 buf[0] = REGISTER_PREFIX;
2859 strcpy (buf + 1, regname);
2860 regname = buf;
2861 }
2862 #endif
2863
2864 symbol_table_insert (symbol_new (regname, reg_section, regnum,
2865 &zero_address_frag));
2866
2867 for (i = 0; regname[i]; i++)
2868 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
2869 buf[i] = '\0';
2870
2871 symbol_table_insert (symbol_new (buf, reg_section, regnum,
2872 &zero_address_frag));
2873 }
2874
2875 struct init_entry
2876 {
2877 const char *name;
2878 int number;
2879 };
2880
2881 static const struct init_entry init_table[] =
2882 {
2883 { "d0", DATA0 },
2884 { "d1", DATA1 },
2885 { "d2", DATA2 },
2886 { "d3", DATA3 },
2887 { "d4", DATA4 },
2888 { "d5", DATA5 },
2889 { "d6", DATA6 },
2890 { "d7", DATA7 },
2891 { "a0", ADDR0 },
2892 { "a1", ADDR1 },
2893 { "a2", ADDR2 },
2894 { "a3", ADDR3 },
2895 { "a4", ADDR4 },
2896 { "a5", ADDR5 },
2897 { "a6", ADDR6 },
2898 { "fp", ADDR6 },
2899 { "a7", ADDR7 },
2900 { "sp", ADDR7 },
2901 { "ssp", ADDR7 },
2902 { "fp0", FP0 },
2903 { "fp1", FP1 },
2904 { "fp2", FP2 },
2905 { "fp3", FP3 },
2906 { "fp4", FP4 },
2907 { "fp5", FP5 },
2908 { "fp6", FP6 },
2909 { "fp7", FP7 },
2910 { "fpi", FPI },
2911 { "fpiar", FPI },
2912 { "fpc", FPI },
2913 { "fps", FPS },
2914 { "fpsr", FPS },
2915 { "fpc", FPC },
2916 { "fpcr", FPC },
2917 { "control", FPC },
2918 { "status", FPS },
2919 { "iaddr", FPI },
2920
2921 { "cop0", COP0 },
2922 { "cop1", COP1 },
2923 { "cop2", COP2 },
2924 { "cop3", COP3 },
2925 { "cop4", COP4 },
2926 { "cop5", COP5 },
2927 { "cop6", COP6 },
2928 { "cop7", COP7 },
2929 { "pc", PC },
2930 { "zpc", ZPC },
2931 { "sr", SR },
2932
2933 { "ccr", CCR },
2934 { "cc", CCR },
2935
2936 { "usp", USP },
2937 { "isp", ISP },
2938 { "sfc", SFC },
2939 { "sfcr", SFC },
2940 { "dfc", DFC },
2941 { "dfcr", DFC },
2942 { "cacr", CACR },
2943 { "caar", CAAR },
2944
2945 { "vbr", VBR },
2946
2947 { "msp", MSP },
2948 { "itt0", ITT0 },
2949 { "itt1", ITT1 },
2950 { "dtt0", DTT0 },
2951 { "dtt1", DTT1 },
2952 { "mmusr", MMUSR },
2953 { "tc", TC },
2954 { "srp", SRP },
2955 { "urp", URP },
2956 { "buscr", BUSCR },
2957 { "pcr", PCR },
2958
2959 { "ac", AC },
2960 { "bc", BC },
2961 { "cal", CAL },
2962 { "crp", CRP },
2963 { "drp", DRP },
2964 { "pcsr", PCSR },
2965 { "psr", PSR },
2966 { "scc", SCC },
2967 { "val", VAL },
2968 { "bad0", BAD0 },
2969 { "bad1", BAD1 },
2970 { "bad2", BAD2 },
2971 { "bad3", BAD3 },
2972 { "bad4", BAD4 },
2973 { "bad5", BAD5 },
2974 { "bad6", BAD6 },
2975 { "bad7", BAD7 },
2976 { "bac0", BAC0 },
2977 { "bac1", BAC1 },
2978 { "bac2", BAC2 },
2979 { "bac3", BAC3 },
2980 { "bac4", BAC4 },
2981 { "bac5", BAC5 },
2982 { "bac6", BAC6 },
2983 { "bac7", BAC7 },
2984
2985 { "ic", IC },
2986 { "dc", DC },
2987 { "nc", NC },
2988
2989 { "tt0", TT0 },
2990 { "tt1", TT1 },
2991 /* 68ec030 versions of same */
2992 { "ac0", TT0 },
2993 { "ac1", TT1 },
2994 /* 68ec030 access control unit, identical to 030 MMU status reg */
2995 { "acusr", PSR },
2996
2997 /* Suppressed data and address registers. */
2998 { "zd0", ZDATA0 },
2999 { "zd1", ZDATA1 },
3000 { "zd2", ZDATA2 },
3001 { "zd3", ZDATA3 },
3002 { "zd4", ZDATA4 },
3003 { "zd5", ZDATA5 },
3004 { "zd6", ZDATA6 },
3005 { "zd7", ZDATA7 },
3006 { "za0", ZADDR0 },
3007 { "za1", ZADDR1 },
3008 { "za2", ZADDR2 },
3009 { "za3", ZADDR3 },
3010 { "za4", ZADDR4 },
3011 { "za5", ZADDR5 },
3012 { "za6", ZADDR6 },
3013 { "za7", ZADDR7 },
3014
3015 { 0, 0 }
3016 };
3017
3018 void
3019 init_regtable ()
3020 {
3021 int i;
3022 for (i = 0; init_table[i].name; i++)
3023 insert_reg (init_table[i].name, init_table[i].number);
3024 }
3025
3026 static int no_68851, no_68881;
3027
3028 #ifdef OBJ_AOUT
3029 /* a.out machine type. Default to 68020. */
3030 int m68k_aout_machtype = 2;
3031 #endif
3032
3033 void
3034 md_assemble (str)
3035 char *str;
3036 {
3037 const char *er;
3038 short *fromP;
3039 char *toP = NULL;
3040 int m, n = 0;
3041 char *to_beg_P;
3042 int shorts_this_frag;
3043 fixS *fixP;
3044
3045 /* In MRI mode, the instruction and operands are separated by a
3046 space. Anything following the operands is a comment. The label
3047 has already been removed. */
3048 if (flag_mri)
3049 {
3050 char *s;
3051 int fields = 0;
3052 int infield = 0;
3053 int inquote = 0;
3054
3055 for (s = str; *s != '\0'; s++)
3056 {
3057 if ((*s == ' ' || *s == '\t') && ! inquote)
3058 {
3059 if (infield)
3060 {
3061 ++fields;
3062 if (fields >= 2)
3063 {
3064 *s = '\0';
3065 break;
3066 }
3067 infield = 0;
3068 }
3069 }
3070 else
3071 {
3072 if (! infield)
3073 infield = 1;
3074 if (*s == '\'')
3075 inquote = ! inquote;
3076 }
3077 }
3078 }
3079
3080 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3081 m68k_ip (str);
3082 er = the_ins.error;
3083 if (!er)
3084 {
3085 for (n = 0; n < the_ins.numargs; n++)
3086 if (the_ins.operands[n].error)
3087 {
3088 er = the_ins.operands[n].error;
3089 break;
3090 }
3091 }
3092 if (er)
3093 {
3094 as_bad ("%s -- statement `%s' ignored", er, str);
3095 return;
3096 }
3097
3098 if (the_ins.nfrag == 0)
3099 {
3100 /* No frag hacking involved; just put it out */
3101 toP = frag_more (2 * the_ins.numo);
3102 fromP = &the_ins.opcode[0];
3103 for (m = the_ins.numo; m; --m)
3104 {
3105 md_number_to_chars (toP, (long) (*fromP), 2);
3106 toP += 2;
3107 fromP++;
3108 }
3109 /* put out symbol-dependent info */
3110 for (m = 0; m < the_ins.nrel; m++)
3111 {
3112 switch (the_ins.reloc[m].wid)
3113 {
3114 case 'B':
3115 n = 1;
3116 break;
3117 case 'b':
3118 n = 1;
3119 break;
3120 case '3':
3121 n = 2;
3122 break;
3123 case 'w':
3124 n = 2;
3125 break;
3126 case 'l':
3127 n = 4;
3128 break;
3129 default:
3130 as_fatal ("Don't know how to figure width of %c in md_assemble()",
3131 the_ins.reloc[m].wid);
3132 }
3133
3134 fixP = fix_new_exp (frag_now,
3135 ((toP - frag_now->fr_literal)
3136 - the_ins.numo * 2 + the_ins.reloc[m].n),
3137 n,
3138 &the_ins.reloc[m].exp,
3139 the_ins.reloc[m].pcrel,
3140 get_reloc_code (n, the_ins.reloc[m].pcrel,
3141 the_ins.reloc[m].pic_reloc));
3142 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3143 }
3144 return;
3145 }
3146
3147 /* There's some frag hacking */
3148 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3149 {
3150 int wid;
3151
3152 if (n == 0)
3153 wid = 2 * the_ins.fragb[n].fragoff;
3154 else
3155 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3156 toP = frag_more (wid);
3157 to_beg_P = toP;
3158 shorts_this_frag = 0;
3159 for (m = wid / 2; m; --m)
3160 {
3161 md_number_to_chars (toP, (long) (*fromP), 2);
3162 toP += 2;
3163 fromP++;
3164 shorts_this_frag++;
3165 }
3166 for (m = 0; m < the_ins.nrel; m++)
3167 {
3168 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3169 {
3170 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3171 break;
3172 }
3173 wid = the_ins.reloc[m].wid;
3174 if (wid == 0)
3175 continue;
3176 the_ins.reloc[m].wid = 0;
3177 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3178
3179 fixP = fix_new_exp (frag_now,
3180 ((toP - frag_now->fr_literal)
3181 - the_ins.numo * 2 + the_ins.reloc[m].n),
3182 wid,
3183 &the_ins.reloc[m].exp,
3184 the_ins.reloc[m].pcrel,
3185 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3186 the_ins.reloc[m].pic_reloc));
3187 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3188 }
3189 (void) frag_var (rs_machine_dependent, 10, 0,
3190 (relax_substateT) (the_ins.fragb[n].fragty),
3191 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3192 }
3193 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3194 shorts_this_frag = 0;
3195 if (n)
3196 {
3197 toP = frag_more (n * sizeof (short));
3198 while (n--)
3199 {
3200 md_number_to_chars (toP, (long) (*fromP), 2);
3201 toP += 2;
3202 fromP++;
3203 shorts_this_frag++;
3204 }
3205 }
3206 for (m = 0; m < the_ins.nrel; m++)
3207 {
3208 int wid;
3209
3210 wid = the_ins.reloc[m].wid;
3211 if (wid == 0)
3212 continue;
3213 the_ins.reloc[m].wid = 0;
3214 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3215
3216 fixP = fix_new_exp (frag_now,
3217 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3218 - shorts_this_frag * 2),
3219 wid,
3220 &the_ins.reloc[m].exp,
3221 the_ins.reloc[m].pcrel,
3222 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3223 the_ins.reloc[m].pic_reloc));
3224 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3225 }
3226 }
3227
3228 void
3229 md_begin ()
3230 {
3231 /*
3232 * md_begin -- set up hash tables with 68000 instructions.
3233 * similar to what the vax assembler does. ---phr
3234 */
3235 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3236 a copy of it at runtime, adding in the information we want but isn't
3237 there. I think it'd be better to have an awk script hack the table
3238 at compile time. Or even just xstr the table and use it as-is. But
3239 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3240 names. */
3241
3242 register const struct m68k_opcode *ins;
3243 register struct m68k_incant *hack, *slak;
3244 register const char *retval = 0; /* empty string, or error msg text */
3245 register unsigned int i;
3246 register char c;
3247
3248 if (flag_mri)
3249 {
3250 flag_reg_prefix_optional = 1;
3251 m68k_abspcadd = 1;
3252 m68k_rel32 = 0;
3253 }
3254
3255 op_hash = hash_new ();
3256
3257 obstack_begin (&robyn, 4000);
3258 for (i = 0; i < m68k_numopcodes; i++)
3259 {
3260 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3261 do
3262 {
3263 ins = &m68k_opcodes[i];
3264 /* We *could* ignore insns that don't match our arch here
3265 but just leaving them out of the hash. */
3266 slak->m_operands = ins->args;
3267 slak->m_opnum = strlen (slak->m_operands) / 2;
3268 slak->m_arch = ins->arch;
3269 slak->m_opcode = ins->opcode;
3270 /* This is kludgey */
3271 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3272 if (i + 1 != m68k_numopcodes
3273 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3274 {
3275 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3276 i++;
3277 }
3278 else
3279 slak->m_next = 0;
3280 slak = slak->m_next;
3281 }
3282 while (slak);
3283
3284 retval = hash_insert (op_hash, ins->name, (char *) hack);
3285 if (retval)
3286 as_fatal ("Internal Error: Can't hash %s: %s", ins->name, retval);
3287 }
3288
3289 for (i = 0; i < m68k_numaliases; i++)
3290 {
3291 const char *name = m68k_opcode_aliases[i].primary;
3292 const char *alias = m68k_opcode_aliases[i].alias;
3293 PTR val = hash_find (op_hash, name);
3294 if (!val)
3295 as_fatal ("Internal Error: Can't find %s in hash table", name);
3296 retval = hash_insert (op_hash, alias, val);
3297 if (retval)
3298 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3299 }
3300
3301 /* In MRI mode, all unsized branches are variable sized. Normally,
3302 they are word sized. */
3303 if (flag_mri)
3304 {
3305 static struct m68k_opcode_alias mri_aliases[] =
3306 {
3307 { "bhi", "jhi", },
3308 { "bls", "jls", },
3309 { "bcc", "jcc", },
3310 { "bcs", "jcs", },
3311 { "bne", "jne", },
3312 { "beq", "jeq", },
3313 { "bvc", "jvc", },
3314 { "bvs", "jvs", },
3315 { "bpl", "jpl", },
3316 { "bmi", "jmi", },
3317 { "bge", "jge", },
3318 { "blt", "jlt", },
3319 { "bgt", "jgt", },
3320 { "ble", "jle", },
3321 { "bra", "jra", },
3322 { "bsr", "jbsr", },
3323 };
3324
3325 for (i = 0; i < sizeof mri_aliases / sizeof mri_aliases[0]; i++)
3326 {
3327 const char *name = mri_aliases[i].primary;
3328 const char *alias = mri_aliases[i].alias;
3329 PTR val = hash_find (op_hash, name);
3330 if (!val)
3331 as_fatal ("Internal Error: Can't find %s in hash table", name);
3332 retval = hash_jam (op_hash, alias, val);
3333 if (retval)
3334 as_fatal ("Internal Error: Can't hash %s: %s", alias, retval);
3335 }
3336 }
3337
3338 for (i = 0; i < sizeof (mklower_table); i++)
3339 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3340
3341 for (i = 0; i < sizeof (notend_table); i++)
3342 {
3343 notend_table[i] = 0;
3344 alt_notend_table[i] = 0;
3345 }
3346 notend_table[','] = 1;
3347 notend_table['{'] = 1;
3348 notend_table['}'] = 1;
3349 alt_notend_table['a'] = 1;
3350 alt_notend_table['A'] = 1;
3351 alt_notend_table['d'] = 1;
3352 alt_notend_table['D'] = 1;
3353 alt_notend_table['#'] = 1;
3354 alt_notend_table['&'] = 1;
3355 alt_notend_table['f'] = 1;
3356 alt_notend_table['F'] = 1;
3357 #ifdef REGISTER_PREFIX
3358 alt_notend_table[REGISTER_PREFIX] = 1;
3359 #endif
3360
3361 /* We need to put '(' in alt_notend_table to handle
3362 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3363 */
3364 alt_notend_table['('] = 1;
3365
3366 /* We need to put '@' in alt_notend_table to handle
3367 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3368 */
3369 alt_notend_table['@'] = 1;
3370
3371 #ifndef MIT_SYNTAX_ONLY
3372 /* Insert pseudo ops, these have to go into the opcode table since
3373 gas expects pseudo ops to start with a dot */
3374 {
3375 int n = 0;
3376 while (mote_pseudo_table[n].poc_name)
3377 {
3378 hack = (struct m68k_incant *)
3379 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3380 hash_insert (op_hash,
3381 mote_pseudo_table[n].poc_name, (char *) hack);
3382 hack->m_operands = 0;
3383 hack->m_opnum = n;
3384 n++;
3385 }
3386 }
3387 #endif
3388
3389 init_regtable ();
3390
3391 #ifdef OBJ_ELF
3392 record_alignment (text_section, 2);
3393 record_alignment (data_section, 2);
3394 record_alignment (bss_section, 2);
3395 #endif
3396 }
3397
3398 void
3399 m68k_init_after_args ()
3400 {
3401 if (cpu_of_arch (current_architecture) == 0)
3402 {
3403 int i;
3404 const char *default_cpu = TARGET_CPU;
3405
3406 if (*default_cpu == 'm')
3407 default_cpu++;
3408 for (i = 0; i < n_archs; i++)
3409 if (strcasecmp (default_cpu, archs[i].name) == 0)
3410 break;
3411 if (i == n_archs)
3412 {
3413 as_bad ("unrecognized default cpu `%s' ???", TARGET_CPU);
3414 current_architecture |= m68020;
3415 }
3416 else
3417 current_architecture |= archs[i].arch;
3418 }
3419 /* Permit m68881 specification with all cpus; those that can't work
3420 with a coprocessor could be doing emulation. */
3421 if (current_architecture & m68851)
3422 {
3423 if (current_architecture & m68040)
3424 {
3425 as_warn ("68040 and 68851 specified; mmu instructions may assemble incorrectly");
3426 }
3427 }
3428 /* What other incompatibilities could we check for? */
3429
3430 /* Toss in some default assumptions about coprocessors. */
3431 if (!no_68881
3432 && (cpu_of_arch (current_architecture)
3433 /* Can CPU32 have a 68881 coprocessor?? */
3434 & (m68020 | m68030 | cpu32)))
3435 {
3436 current_architecture |= m68881;
3437 }
3438 if (!no_68851
3439 && (cpu_of_arch (current_architecture) & m68020up) != 0
3440 && (cpu_of_arch (current_architecture) & m68040up) == 0)
3441 {
3442 current_architecture |= m68851;
3443 }
3444 if (no_68881 && (current_architecture & m68881))
3445 as_bad ("options for 68881 and no-68881 both given");
3446 if (no_68851 && (current_architecture & m68851))
3447 as_bad ("options for 68851 and no-68851 both given");
3448
3449 #ifdef OBJ_AOUT
3450 /* Work out the magic number. This isn't very general. */
3451 if (current_architecture & m68000)
3452 m68k_aout_machtype = 0;
3453 else if (current_architecture & m68010)
3454 m68k_aout_machtype = 1;
3455 else if (current_architecture & m68020)
3456 m68k_aout_machtype = 2;
3457 else
3458 m68k_aout_machtype = 2;
3459 #endif
3460
3461 /* Note which set of "movec" control registers is available. */
3462 switch (cpu_of_arch (current_architecture))
3463 {
3464 case m68000:
3465 control_regs = m68000_control_regs;
3466 break;
3467 case m68010:
3468 control_regs = m68010_control_regs;
3469 break;
3470 case m68020:
3471 case m68030:
3472 control_regs = m68020_control_regs;
3473 break;
3474 case m68040:
3475 control_regs = m68040_control_regs;
3476 break;
3477 case m68060:
3478 control_regs = m68060_control_regs;
3479 break;
3480 case cpu32:
3481 control_regs = cpu32_control_regs;
3482 break;
3483 default:
3484 abort ();
3485 }
3486
3487 if (cpu_of_arch (current_architecture) < m68020)
3488 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3489 }
3490
3491 /* Equal to MAX_PRECISION in atof-ieee.c */
3492 #define MAX_LITTLENUMS 6
3493
3494 /* Turn a string in input_line_pointer into a floating point constant
3495 of type type, and store the appropriate bytes in *litP. The number
3496 of LITTLENUMS emitted is stored in *sizeP . An error message is
3497 returned, or NULL on OK. */
3498
3499 char *
3500 md_atof (type, litP, sizeP)
3501 char type;
3502 char *litP;
3503 int *sizeP;
3504 {
3505 int prec;
3506 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3507 LITTLENUM_TYPE *wordP;
3508 char *t;
3509 char *atof_ieee ();
3510
3511 switch (type)
3512 {
3513 case 'f':
3514 case 'F':
3515 case 's':
3516 case 'S':
3517 prec = 2;
3518 break;
3519
3520 case 'd':
3521 case 'D':
3522 case 'r':
3523 case 'R':
3524 prec = 4;
3525 break;
3526
3527 case 'x':
3528 case 'X':
3529 prec = 6;
3530 break;
3531
3532 case 'p':
3533 case 'P':
3534 prec = 6;
3535 break;
3536
3537 default:
3538 *sizeP = 0;
3539 return "Bad call to MD_ATOF()";
3540 }
3541 t = atof_ieee (input_line_pointer, type, words);
3542 if (t)
3543 input_line_pointer = t;
3544
3545 *sizeP = prec * sizeof (LITTLENUM_TYPE);
3546 for (wordP = words; prec--;)
3547 {
3548 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
3549 litP += sizeof (LITTLENUM_TYPE);
3550 }
3551 return 0;
3552 }
3553
3554 void
3555 md_number_to_chars (buf, val, n)
3556 char *buf;
3557 valueT val;
3558 int n;
3559 {
3560 number_to_chars_bigendian (buf, val, n);
3561 }
3562
3563 static void
3564 md_apply_fix_2 (fixP, val)
3565 fixS *fixP;
3566 offsetT val;
3567 {
3568 addressT upper_limit;
3569 offsetT lower_limit;
3570
3571 /* This is unnecessary but it convinces the native rs6000 compiler
3572 to generate the code we want. */
3573 char *buf = fixP->fx_frag->fr_literal;
3574 buf += fixP->fx_where;
3575 /* end ibm compiler workaround */
3576
3577 if (val & 0x80000000)
3578 val |= ~(addressT)0x7fffffff;
3579 else
3580 val &= 0x7fffffff;
3581
3582 #ifdef OBJ_ELF
3583 if (fixP->fx_addsy)
3584 {
3585 memset (buf, 0, fixP->fx_size);
3586 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
3587 return;
3588 }
3589 #endif
3590
3591 switch (fixP->fx_size)
3592 {
3593 /* The cast to offsetT below are necessary to make code correct for
3594 machines where ints are smaller than offsetT */
3595 case 1:
3596 *buf++ = val;
3597 upper_limit = 0x7f;
3598 lower_limit = - (offsetT) 0x80;
3599 break;
3600 case 2:
3601 *buf++ = (val >> 8);
3602 *buf++ = val;
3603 upper_limit = 0x7fff;
3604 lower_limit = - (offsetT) 0x8000;
3605 break;
3606 case 4:
3607 *buf++ = (val >> 24);
3608 *buf++ = (val >> 16);
3609 *buf++ = (val >> 8);
3610 *buf++ = val;
3611 upper_limit = 0x7fffffff;
3612 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
3613 break;
3614 default:
3615 BAD_CASE (fixP->fx_size);
3616 }
3617
3618 /* Fix up a negative reloc. */
3619 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
3620 {
3621 fixP->fx_addsy = fixP->fx_subsy;
3622 fixP->fx_subsy = NULL;
3623 fixP->fx_tcbit = 1;
3624 }
3625
3626 /* For non-pc-relative values, it's conceivable we might get something
3627 like "0xff" for a byte field. So extend the upper part of the range
3628 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
3629 so that we can do any range checking at all. */
3630 if (!fixP->fx_pcrel)
3631 upper_limit = upper_limit * 2 + 1;
3632
3633 if ((addressT) val > upper_limit
3634 && (val > 0 || val < lower_limit))
3635 as_bad_where (fixP->fx_file, fixP->fx_line, "value out of range");
3636
3637 /* A one byte PC-relative reloc means a short branch. We can't use
3638 a short branch with a value of 0 or -1, because those indicate
3639 different opcodes (branches with longer offsets). */
3640 if (fixP->fx_pcrel
3641 && fixP->fx_size == 1
3642 && (fixP->fx_addsy == NULL
3643 || S_IS_DEFINED (fixP->fx_addsy))
3644 && (val == 0 || val == -1))
3645 as_bad_where (fixP->fx_file, fixP->fx_line, "invalid byte branch offset");
3646 }
3647
3648 #ifdef BFD_ASSEMBLER
3649 int
3650 md_apply_fix (fixP, valp)
3651 fixS *fixP;
3652 valueT *valp;
3653 {
3654 md_apply_fix_2 (fixP, (addressT) *valp);
3655 return 1;
3656 }
3657 #else
3658 void md_apply_fix (fixP, val)
3659 fixS *fixP;
3660 long val;
3661 {
3662 md_apply_fix_2 (fixP, (addressT) val);
3663 }
3664 #endif
3665
3666 /* *fragP has been relaxed to its final size, and now needs to have
3667 the bytes inside it modified to conform to the new size There is UGLY
3668 MAGIC here. ..
3669 */
3670 void
3671 md_convert_frag_1 (fragP)
3672 register fragS *fragP;
3673 {
3674 long disp;
3675 long ext = 0;
3676 fixS *fixP;
3677
3678 /* Address in object code of the displacement. */
3679 register int object_address = fragP->fr_fix + fragP->fr_address;
3680
3681 /* Address in gas core of the place to store the displacement. */
3682 /* This convinces the native rs6000 compiler to generate the code we
3683 want. */
3684 register char *buffer_address = fragP->fr_literal;
3685 buffer_address += fragP->fr_fix;
3686 /* end ibm compiler workaround */
3687
3688 /* The displacement of the address, from current location. */
3689 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
3690 disp = (disp + fragP->fr_offset) - object_address;
3691
3692 #ifdef BFD_ASSEMBLER
3693 disp += fragP->fr_symbol->sy_frag->fr_address;
3694 #endif
3695
3696 switch (fragP->fr_subtype)
3697 {
3698 case TAB (BCC68000, BYTE):
3699 case TAB (ABRANCH, BYTE):
3700 know (issbyte (disp));
3701 if (disp == 0)
3702 as_bad ("short branch with zero offset: use :w");
3703 fragP->fr_opcode[1] = disp;
3704 ext = 0;
3705 break;
3706 case TAB (DBCC, SHORT):
3707 know (issword (disp));
3708 ext = 2;
3709 break;
3710 case TAB (BCC68000, SHORT):
3711 case TAB (ABRANCH, SHORT):
3712 know (issword (disp));
3713 fragP->fr_opcode[1] = 0x00;
3714 ext = 2;
3715 break;
3716 case TAB (ABRANCH, LONG):
3717 if (cpu_of_arch (current_architecture) < m68020)
3718 {
3719 if (fragP->fr_opcode[0] == 0x61)
3720 /* BSR */
3721 {
3722 fragP->fr_opcode[0] = 0x4E;
3723 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3724
3725 fix_new (fragP,
3726 fragP->fr_fix,
3727 4,
3728 fragP->fr_symbol,
3729 fragP->fr_offset,
3730 0,
3731 NO_RELOC);
3732
3733 fragP->fr_fix += 4;
3734 ext = 0;
3735 }
3736 /* BRA */
3737 else if (fragP->fr_opcode[0] == 0x60)
3738 {
3739 fragP->fr_opcode[0] = 0x4E;
3740 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3741 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3742 fragP->fr_offset, 0, NO_RELOC);
3743 fragP->fr_fix += 4;
3744 ext = 0;
3745 }
3746 else
3747 {
3748 as_bad ("Long branch offset not supported.");
3749 }
3750 }
3751 else
3752 {
3753 fragP->fr_opcode[1] = (char) 0xff;
3754 ext = 4;
3755 }
3756 break;
3757 case TAB (BCC68000, LONG):
3758 /* only Bcc 68000 instructions can come here */
3759 /* change bcc into b!cc/jmp absl long */
3760 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
3761 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
3762
3763 /* JF: these used to be fr_opcode[2,3], but they may be in a
3764 different frag, in which case refering to them is a no-no.
3765 Only fr_opcode[0,1] are guaranteed to work. */
3766 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3767 *buffer_address++ = (char) 0xf9;
3768 fragP->fr_fix += 2; /* account for jmp instruction */
3769 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3770 fragP->fr_offset, 0, NO_RELOC);
3771 fragP->fr_fix += 4;
3772 ext = 0;
3773 break;
3774 case TAB (DBCC, LONG):
3775 /* only DBcc 68000 instructions can come here */
3776 /* change dbcc into dbcc/jmp absl long */
3777 /* JF: these used to be fr_opcode[2-7], but that's wrong */
3778 *buffer_address++ = 0x00; /* branch offset = 4 */
3779 *buffer_address++ = 0x04;
3780 *buffer_address++ = 0x60; /* put in bra pc+6 */
3781 *buffer_address++ = 0x06;
3782 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
3783 *buffer_address++ = (char) 0xf9;
3784
3785 fragP->fr_fix += 6; /* account for bra/jmp instructions */
3786 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
3787 fragP->fr_offset, 0, NO_RELOC);
3788 fragP->fr_fix += 4;
3789 ext = 0;
3790 break;
3791 case TAB (FBRANCH, SHORT):
3792 know ((fragP->fr_opcode[1] & 0x40) == 0);
3793 ext = 2;
3794 break;
3795 case TAB (FBRANCH, LONG):
3796 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3797 ext = 4;
3798 break;
3799 case TAB (PCREL, SHORT):
3800 ext = 2;
3801 break;
3802 case TAB (PCREL, LONG):
3803 /* The thing to do here is force it to ABSOLUTE LONG, since
3804 PCREL is really trying to shorten an ABSOLUTE address anyway */
3805 /* JF FOO This code has not been tested */
3806 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3807 0, NO_RELOC);
3808 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
3809 as_bad ("Internal error (long PC-relative operand) for insn 0x%04x at 0x%lx",
3810 (unsigned) fragP->fr_opcode[0],
3811 (unsigned long) fragP->fr_address);
3812 fragP->fr_opcode[1] &= ~0x3F;
3813 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
3814 fragP->fr_fix += 4;
3815 ext = 0;
3816 break;
3817 case TAB (PCLEA, SHORT):
3818 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3819 fragP->fr_offset, 1, NO_RELOC);
3820 fragP->fr_opcode[1] &= ~0x3F;
3821 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
3822 ext = 2;
3823 break;
3824 case TAB (PCLEA, LONG):
3825 fixP = fix_new (fragP, (int) (fragP->fr_fix) + 2, 4, fragP->fr_symbol,
3826 fragP->fr_offset, 1, NO_RELOC);
3827 fixP->fx_pcrel_adjust = 2;
3828 /* Already set to mode 7.3; this indicates: PC indirect with
3829 suppressed index, 32-bit displacement. */
3830 *buffer_address++ = 0x01;
3831 *buffer_address++ = 0x70;
3832 fragP->fr_fix += 2;
3833 ext = 4;
3834 break;
3835
3836 case TAB (PCINDEX, BYTE):
3837 disp += 2;
3838 if (!issbyte (disp))
3839 {
3840 as_bad ("displacement doesn't fit in one byte");
3841 disp = 0;
3842 }
3843 assert (fragP->fr_fix >= 2);
3844 buffer_address[-2] &= ~1;
3845 buffer_address[-1] = disp;
3846 ext = 0;
3847 break;
3848 case TAB (PCINDEX, SHORT):
3849 disp += 2;
3850 assert (issword (disp));
3851 assert (fragP->fr_fix >= 2);
3852 buffer_address[-2] |= 0x1;
3853 buffer_address[-1] = 0x20;
3854 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
3855 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3856 NO_RELOC);
3857 fixP->fx_pcrel_adjust = 2;
3858 ext = 2;
3859 break;
3860 case TAB (PCINDEX, LONG):
3861 disp += 2;
3862 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3863 fragP->fr_offset, (fragP->fr_opcode[1] & 077) == 073,
3864 NO_RELOC);
3865 fixP->fx_pcrel_adjust = 2;
3866 assert (fragP->fr_fix >= 2);
3867 buffer_address[-2] |= 0x1;
3868 buffer_address[-1] = 0x30;
3869 ext = 4;
3870 break;
3871 }
3872
3873 if (ext)
3874 {
3875 md_number_to_chars (buffer_address, (long) disp, (int) ext);
3876 fragP->fr_fix += ext;
3877 }
3878 }
3879
3880 #ifndef BFD_ASSEMBLER
3881
3882 void
3883 md_convert_frag (headers, sec, fragP)
3884 object_headers *headers;
3885 segT sec;
3886 fragS *fragP;
3887 {
3888 md_convert_frag_1 (fragP);
3889 }
3890
3891 #else
3892
3893 void
3894 md_convert_frag (abfd, sec, fragP)
3895 bfd *abfd;
3896 segT sec;
3897 fragS *fragP;
3898 {
3899 md_convert_frag_1 (fragP);
3900 }
3901 #endif
3902
3903 /* Force truly undefined symbols to their maximum size, and generally set up
3904 the frag list to be relaxed
3905 */
3906 int
3907 md_estimate_size_before_relax (fragP, segment)
3908 register fragS *fragP;
3909 segT segment;
3910 {
3911 int old_fix;
3912 register char *buffer_address = fragP->fr_fix + fragP->fr_literal;
3913
3914 old_fix = fragP->fr_fix;
3915
3916 /* handle SZ_UNDEF first, it can be changed to BYTE or SHORT */
3917 switch (fragP->fr_subtype)
3918 {
3919
3920 case TAB (ABRANCH, SZ_UNDEF):
3921 {
3922 if ((fragP->fr_symbol != NULL) /* Not absolute */
3923 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
3924 {
3925 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
3926 break;
3927 }
3928 else if ((fragP->fr_symbol == 0) || (cpu_of_arch (current_architecture) < m68020))
3929 {
3930 /* On 68000, or for absolute value, switch to abs long */
3931 /* FIXME, we should check abs val, pick short or long */
3932 if (fragP->fr_opcode[0] == 0x61)
3933 {
3934 fragP->fr_opcode[0] = 0x4E;
3935 fragP->fr_opcode[1] = (char) 0xB9; /* JBSR with ABSL LONG offset */
3936 fix_new (fragP, fragP->fr_fix, 4,
3937 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3938 fragP->fr_fix += 4;
3939 frag_wane (fragP);
3940 }
3941 else if (fragP->fr_opcode[0] == 0x60)
3942 {
3943 fragP->fr_opcode[0] = 0x4E;
3944 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG offset */
3945 fix_new (fragP, fragP->fr_fix, 4,
3946 fragP->fr_symbol, fragP->fr_offset, 0, NO_RELOC);
3947 fragP->fr_fix += 4;
3948 frag_wane (fragP);
3949 }
3950 else
3951 {
3952 as_warn ("Long branch offset to extern symbol not supported.");
3953 }
3954 }
3955 else
3956 { /* Symbol is still undefined. Make it simple */
3957 fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
3958 fragP->fr_offset, 1, NO_RELOC);
3959 fragP->fr_fix += 4;
3960 fragP->fr_opcode[1] = (char) 0xff;
3961 frag_wane (fragP);
3962 break;
3963 }
3964
3965 break;
3966 } /* case TAB(ABRANCH,SZ_UNDEF) */
3967
3968 case TAB (FBRANCH, SZ_UNDEF):
3969 {
3970 if (S_GET_SEGMENT (fragP->fr_symbol) == segment || flag_short_refs)
3971 {
3972 fragP->fr_subtype = TAB (FBRANCH, SHORT);
3973 fragP->fr_var += 2;
3974 }
3975 else
3976 {
3977 fix_new (fragP, (int) fragP->fr_fix, 4, fragP->fr_symbol,
3978 fragP->fr_offset, 1, NO_RELOC);
3979 fragP->fr_fix += 4;
3980 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
3981 frag_wane (fragP);
3982 }
3983 break;
3984 } /* TAB(FBRANCH,SZ_UNDEF) */
3985
3986 case TAB (PCREL, SZ_UNDEF):
3987 {
3988 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
3989 || flag_short_refs
3990 || cpu_of_arch (current_architecture) < m68020)
3991 {
3992 fragP->fr_subtype = TAB (PCREL, SHORT);
3993 fragP->fr_var += 2;
3994 }
3995 else
3996 {
3997 fragP->fr_subtype = TAB (PCREL, LONG);
3998 fragP->fr_var += 4;
3999 }
4000 break;
4001 } /* TAB(PCREL,SZ_UNDEF) */
4002
4003 case TAB (BCC68000, SZ_UNDEF):
4004 {
4005 if ((fragP->fr_symbol != NULL)
4006 && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4007 {
4008 fragP->fr_subtype = TAB (BCC68000, BYTE);
4009 break;
4010 }
4011 /* only Bcc 68000 instructions can come here */
4012 /* change bcc into b!cc/jmp absl long */
4013 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4014 if (flag_short_refs)
4015 {
4016 fragP->fr_opcode[1] = 0x04; /* branch offset = 6 */
4017 /* JF: these were fr_opcode[2,3] */
4018 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4019 buffer_address[1] = (char) 0xf8;
4020 fragP->fr_fix += 2; /* account for jmp instruction */
4021 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4022 fragP->fr_offset, 0, NO_RELOC);
4023 fragP->fr_fix += 2;
4024 }
4025 else
4026 {
4027 fragP->fr_opcode[1] = 0x06; /* branch offset = 6 */
4028 /* JF: these were fr_opcode[2,3] */
4029 buffer_address[0] = 0x4e; /* put in jmp long (0x4ef9) */
4030 buffer_address[1] = (char) 0xf9;
4031 fragP->fr_fix += 2; /* account for jmp instruction */
4032 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4033 fragP->fr_offset, 0, NO_RELOC);
4034 fragP->fr_fix += 4;
4035 }
4036 frag_wane (fragP);
4037 break;
4038 } /* case TAB(BCC68000,SZ_UNDEF) */
4039
4040 case TAB (DBCC, SZ_UNDEF):
4041 {
4042 if (fragP->fr_symbol != NULL && S_GET_SEGMENT (fragP->fr_symbol) == segment)
4043 {
4044 fragP->fr_subtype = TAB (DBCC, SHORT);
4045 fragP->fr_var += 2;
4046 break;
4047 }
4048 /* only DBcc 68000 instructions can come here */
4049 /* change dbcc into dbcc/jmp absl long */
4050 /* JF: these used to be fr_opcode[2-4], which is wrong. */
4051 buffer_address[0] = 0x00; /* branch offset = 4 */
4052 buffer_address[1] = 0x04;
4053 buffer_address[2] = 0x60; /* put in bra pc + ... */
4054
4055 if (flag_short_refs)
4056 {
4057 /* JF: these were fr_opcode[5-7] */
4058 buffer_address[3] = 0x04; /* plus 4 */
4059 buffer_address[4] = 0x4e; /* Put in Jump Word */
4060 buffer_address[5] = (char) 0xf8;
4061 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4062 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4063 fragP->fr_offset, 0, NO_RELOC);
4064 fragP->fr_fix += 2;
4065 }
4066 else
4067 {
4068 /* JF: these were fr_opcode[5-7] */
4069 buffer_address[3] = 0x06; /* Plus 6 */
4070 buffer_address[4] = 0x4e; /* put in jmp long (0x4ef9) */
4071 buffer_address[5] = (char) 0xf9;
4072 fragP->fr_fix += 6; /* account for bra/jmp instruction */
4073 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4074 fragP->fr_offset, 0, NO_RELOC);
4075 fragP->fr_fix += 4;
4076 }
4077
4078 frag_wane (fragP);
4079 break;
4080 } /* case TAB(DBCC,SZ_UNDEF) */
4081
4082 case TAB (PCLEA, SZ_UNDEF):
4083 {
4084 if ((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4085 || flag_short_refs
4086 || cpu_of_arch (current_architecture) < m68020)
4087 {
4088 fragP->fr_subtype = TAB (PCLEA, SHORT);
4089 fragP->fr_var += 2;
4090 }
4091 else
4092 {
4093 fragP->fr_subtype = TAB (PCLEA, LONG);
4094 fragP->fr_var += 6;
4095 }
4096 break;
4097 } /* TAB(PCLEA,SZ_UNDEF) */
4098
4099 case TAB (PCINDEX, SZ_UNDEF):
4100 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4101 || cpu_of_arch (current_architecture) < m68020)
4102 {
4103 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4104 }
4105 else
4106 {
4107 fragP->fr_subtype = TAB (PCINDEX, LONG);
4108 fragP->fr_var += 4;
4109 }
4110 break;
4111
4112 default:
4113 break;
4114 }
4115
4116 /* now that SZ_UNDEF are taken care of, check others */
4117 switch (fragP->fr_subtype)
4118 {
4119 case TAB (BCC68000, BYTE):
4120 case TAB (ABRANCH, BYTE):
4121 /* We can't do a short jump to the next instruction,
4122 so we force word mode. */
4123 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0 &&
4124 fragP->fr_symbol->sy_frag == fragP->fr_next)
4125 {
4126 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4127 fragP->fr_var += 2;
4128 }
4129 break;
4130 default:
4131 break;
4132 }
4133 return fragP->fr_var + fragP->fr_fix - old_fix;
4134 }
4135
4136 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4137 /* the bit-field entries in the relocation_info struct plays hell
4138 with the byte-order problems of cross-assembly. So as a hack,
4139 I added this mach. dependent ri twiddler. Ugly, but it gets
4140 you there. -KWK */
4141 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4142 are symbolnum, most sig. byte first. Last byte is broken up with
4143 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4144 nibble as nuthin. (on Sun 3 at least) */
4145 /* Translate the internal relocation information into target-specific
4146 format. */
4147 #ifdef comment
4148 void
4149 md_ri_to_chars (the_bytes, ri)
4150 char *the_bytes;
4151 struct reloc_info_generic *ri;
4152 {
4153 /* this is easy */
4154 md_number_to_chars (the_bytes, ri->r_address, 4);
4155 /* now the fun stuff */
4156 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4157 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4158 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4159 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4160 ((ri->r_extern << 4) & 0x10));
4161 }
4162
4163 #endif /* comment */
4164
4165 #ifndef BFD_ASSEMBLER
4166 void
4167 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4168 char *where;
4169 fixS *fixP;
4170 relax_addressT segment_address_in_file;
4171 {
4172 /*
4173 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4174 * Out: GNU LD relocation length code: 0, 1, or 2.
4175 */
4176
4177 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4178 long r_symbolnum;
4179
4180 know (fixP->fx_addsy != NULL);
4181
4182 md_number_to_chars (where,
4183 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4184 4);
4185
4186 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4187 ? S_GET_TYPE (fixP->fx_addsy)
4188 : fixP->fx_addsy->sy_number);
4189
4190 where[4] = (r_symbolnum >> 16) & 0x0ff;
4191 where[5] = (r_symbolnum >> 8) & 0x0ff;
4192 where[6] = r_symbolnum & 0x0ff;
4193 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4194 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4195 }
4196 #endif
4197
4198 #endif /* OBJ_AOUT or OBJ_BOUT */
4199
4200 #ifndef WORKING_DOT_WORD
4201 CONST int md_short_jump_size = 4;
4202 CONST int md_long_jump_size = 6;
4203
4204 void
4205 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4206 char *ptr;
4207 addressT from_addr, to_addr;
4208 fragS *frag;
4209 symbolS *to_symbol;
4210 {
4211 valueT offset;
4212
4213 offset = to_addr - (from_addr + 2);
4214
4215 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4216 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4217 }
4218
4219 void
4220 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4221 char *ptr;
4222 addressT from_addr, to_addr;
4223 fragS *frag;
4224 symbolS *to_symbol;
4225 {
4226 valueT offset;
4227
4228 if (cpu_of_arch (current_architecture) < m68020)
4229 {
4230 offset = to_addr - S_GET_VALUE (to_symbol);
4231 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4232 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4233 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4234 0, NO_RELOC);
4235 }
4236 else
4237 {
4238 offset = to_addr - (from_addr + 2);
4239 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4240 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4241 }
4242 }
4243
4244 #endif
4245
4246 /* Different values of OK tell what its OK to return. Things that
4247 aren't OK are an error (what a shock, no?)
4248
4249 0: Everything is OK
4250 10: Absolute 1:8 only
4251 20: Absolute 0:7 only
4252 30: absolute 0:15 only
4253 40: Absolute 0:31 only
4254 50: absolute 0:127 only
4255 55: absolute -64:63 only
4256 60: absolute -128:127 only
4257 70: absolute 0:4095 only
4258 80: No bignums
4259
4260 */
4261
4262 static int
4263 get_num (exp, ok)
4264 struct m68k_exp *exp;
4265 int ok;
4266 {
4267 if (exp->exp.X_op == O_absent)
4268 {
4269 /* Do the same thing the VAX asm does */
4270 op (exp) = O_constant;
4271 adds (exp) = 0;
4272 subs (exp) = 0;
4273 offs (exp) = 0;
4274 if (ok == 10)
4275 {
4276 as_warn ("expression out of range: defaulting to 1");
4277 offs (exp) = 1;
4278 }
4279 }
4280 else if (exp->exp.X_op == O_constant)
4281 {
4282 switch (ok)
4283 {
4284 case 10:
4285 if (offs (exp) < 1 || offs (exp) > 8)
4286 {
4287 as_warn ("expression out of range: defaulting to 1");
4288 offs (exp) = 1;
4289 }
4290 break;
4291 case 20:
4292 if (offs (exp) < 0 || offs (exp) > 7)
4293 goto outrange;
4294 break;
4295 case 30:
4296 if (offs (exp) < 0 || offs (exp) > 15)
4297 goto outrange;
4298 break;
4299 case 40:
4300 if (offs (exp) < 0 || offs (exp) > 32)
4301 goto outrange;
4302 break;
4303 case 50:
4304 if (offs (exp) < 0 || offs (exp) > 127)
4305 goto outrange;
4306 break;
4307 case 55:
4308 if (offs (exp) < -64 || offs (exp) > 63)
4309 goto outrange;
4310 break;
4311 case 60:
4312 if (offs (exp) < -128 || offs (exp) > 127)
4313 goto outrange;
4314 break;
4315 case 70:
4316 if (offs (exp) < 0 || offs (exp) > 4095)
4317 {
4318 outrange:
4319 as_warn ("expression out of range: defaulting to 0");
4320 offs (exp) = 0;
4321 }
4322 break;
4323 default:
4324 break;
4325 }
4326 }
4327 else if (exp->exp.X_op == O_big)
4328 {
4329 if (offs (exp) <= 0 /* flonum */
4330 && (ok == 80 /* no bignums */
4331 || (ok > 10 /* small-int ranges including 0 ok */
4332 /* If we have a flonum zero, a zero integer should
4333 do as well (e.g., in moveq). */
4334 && generic_floating_point_number.exponent == 0
4335 && generic_floating_point_number.low[0] == 0)))
4336 {
4337 /* HACK! Turn it into a long */
4338 LITTLENUM_TYPE words[6];
4339
4340 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4341 op (exp) = O_constant;
4342 adds (exp) = 0;
4343 subs (exp) = 0;
4344 offs (exp) = words[1] | (words[0] << 16);
4345 }
4346 else if (ok != 0)
4347 {
4348 op (exp) = O_constant;
4349 adds (exp) = 0;
4350 subs (exp) = 0;
4351 offs (exp) = (ok == 10) ? 1 : 0;
4352 as_warn ("Can't deal with expression; defaulting to %ld",
4353 offs (exp));
4354 }
4355 }
4356 else
4357 {
4358 if (ok >= 10 && ok <= 70)
4359 {
4360 op (exp) = O_constant;
4361 adds (exp) = 0;
4362 subs (exp) = 0;
4363 offs (exp) = (ok == 10) ? 1 : 0;
4364 as_warn ("Can't deal with expression; defaulting to %ld",
4365 offs (exp));
4366 }
4367 }
4368
4369 if (exp->size != SIZE_UNSPEC)
4370 {
4371 switch (exp->size)
4372 {
4373 case SIZE_UNSPEC:
4374 case SIZE_LONG:
4375 break;
4376 case SIZE_BYTE:
4377 if (!isbyte (offs (exp)))
4378 as_warn ("expression doesn't fit in BYTE");
4379 break;
4380 case SIZE_WORD:
4381 if (!isword (offs (exp)))
4382 as_warn ("expression doesn't fit in WORD");
4383 break;
4384 }
4385 }
4386
4387 return offs (exp);
4388 }
4389
4390 /* These are the back-ends for the various machine dependent pseudo-ops. */
4391 void demand_empty_rest_of_line (); /* Hate those extra verbose names */
4392
4393 static void
4394 s_data1 (ignore)
4395 int ignore;
4396 {
4397 subseg_set (data_section, 1);
4398 demand_empty_rest_of_line ();
4399 }
4400
4401 static void
4402 s_data2 (ignore)
4403 int ignore;
4404 {
4405 subseg_set (data_section, 2);
4406 demand_empty_rest_of_line ();
4407 }
4408
4409 static void
4410 s_bss (ignore)
4411 int ignore;
4412 {
4413 /* We don't support putting frags in the BSS segment, we fake it
4414 by marking in_bss, then looking at s_skip for clues. */
4415
4416 subseg_set (bss_section, 0);
4417 demand_empty_rest_of_line ();
4418 }
4419
4420 static void
4421 s_even (ignore)
4422 int ignore;
4423 {
4424 register int temp;
4425 register long temp_fill;
4426
4427 temp = 1; /* JF should be 2? */
4428 temp_fill = get_absolute_expression ();
4429 if (!need_pass_2) /* Never make frag if expect extra pass. */
4430 frag_align (temp, (int) temp_fill);
4431 demand_empty_rest_of_line ();
4432 }
4433
4434 static void
4435 s_proc (ignore)
4436 int ignore;
4437 {
4438 demand_empty_rest_of_line ();
4439 }
4440 \f
4441 /* Pseudo-ops handled for MRI compatibility. */
4442
4443 /* Handle an MRI style chip specification. */
4444
4445 static void
4446 mri_chip ()
4447 {
4448 char *s;
4449 char c;
4450 int i;
4451
4452 s = input_line_pointer;
4453 c = get_symbol_end ();
4454 for (i = 0; i < n_archs; i++)
4455 if (strcasecmp (s, archs[i].name) == 0)
4456 break;
4457 if (i >= n_archs)
4458 {
4459 as_bad ("%s: unrecognized processor name", s);
4460 *input_line_pointer = c;
4461 ignore_rest_of_line ();
4462 return;
4463 }
4464 *input_line_pointer = c;
4465
4466 if (*input_line_pointer == '/')
4467 current_architecture = 0;
4468 else
4469 current_architecture &= m68881 | m68851;
4470 current_architecture |= archs[i].arch;
4471
4472 while (*input_line_pointer == '/')
4473 {
4474 ++input_line_pointer;
4475 s = input_line_pointer;
4476 c = get_symbol_end ();
4477 if (strcmp (s, "68881") == 0)
4478 current_architecture |= m68881;
4479 else if (strcmp (s, "68851") == 0)
4480 current_architecture |= m68851;
4481 *input_line_pointer = c;
4482 }
4483 }
4484
4485 /* The MRI CHIP pseudo-op. */
4486
4487 static void
4488 s_chip (ignore)
4489 int ignore;
4490 {
4491 char *stop = NULL;
4492 char stopc;
4493
4494 if (flag_mri)
4495 stop = mri_comment_field (&stopc);
4496 mri_chip ();
4497 if (flag_mri)
4498 mri_comment_end (stop, stopc);
4499 demand_empty_rest_of_line ();
4500 }
4501
4502 /* The MRI FOPT pseudo-op. */
4503
4504 static void
4505 s_fopt (ignore)
4506 int ignore;
4507 {
4508 SKIP_WHITESPACE ();
4509
4510 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
4511 {
4512 int temp;
4513
4514 input_line_pointer += 3;
4515 temp = get_absolute_expression ();
4516 if (temp < 0 || temp > 7)
4517 as_bad ("bad coprocessor id");
4518 else
4519 m68k_float_copnum = COP0 + temp;
4520 }
4521 else
4522 {
4523 as_bad ("unrecognized fopt option");
4524 ignore_rest_of_line ();
4525 return;
4526 }
4527
4528 demand_empty_rest_of_line ();
4529 }
4530
4531 /* The structure used to handle the MRI OPT pseudo-op. */
4532
4533 struct opt_action
4534 {
4535 /* The name of the option. */
4536 const char *name;
4537
4538 /* If this is not NULL, just call this function. The first argument
4539 is the ARG field of this structure, the second argument is
4540 whether the option was negated. */
4541 void (*pfn) PARAMS ((int arg, int on));
4542
4543 /* If this is not NULL, and the PFN field is NULL, set the variable
4544 this points to. Set it to the ARG field if the option was not
4545 negated, and the NOTARG field otherwise. */
4546 int *pvar;
4547
4548 /* The value to pass to PFN or to assign to *PVAR. */
4549 int arg;
4550
4551 /* The value to assign to *PVAR if the option is negated. If PFN is
4552 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
4553 the option may not be negated. */
4554 int notarg;
4555 };
4556
4557 /* The table used to handle the MRI OPT pseudo-op. */
4558
4559 static void skip_to_comma PARAMS ((int, int));
4560 static void opt_nest PARAMS ((int, int));
4561 static void opt_chip PARAMS ((int, int));
4562 static void opt_list PARAMS ((int, int));
4563 static void opt_list_symbols PARAMS ((int, int));
4564
4565 static const struct opt_action opt_table[] =
4566 {
4567 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
4568
4569 /* We do relaxing, so there is little use for these options. */
4570 { "b", 0, 0, 0, 0 },
4571 { "brs", 0, 0, 0, 0 },
4572 { "brb", 0, 0, 0, 0 },
4573 { "brl", 0, 0, 0, 0 },
4574 { "brw", 0, 0, 0, 0 },
4575
4576 { "c", 0, 0, 0, 0 },
4577 { "cex", 0, 0, 0, 0 },
4578 { "case", 0, &symbols_case_sensitive, 1, 0 },
4579 { "cl", 0, 0, 0, 0 },
4580 { "cre", 0, 0, 0, 0 },
4581 { "d", 0, &flag_keep_locals, 1, 0 },
4582 { "e", 0, 0, 0, 0 },
4583 { "f", 0, &flag_short_refs, 1, 0 },
4584 { "frs", 0, &flag_short_refs, 1, 0 },
4585 { "frl", 0, &flag_short_refs, 0, 1 },
4586 { "g", 0, 0, 0, 0 },
4587 { "i", 0, 0, 0, 0 },
4588 { "m", 0, 0, 0, 0 },
4589 { "mex", 0, 0, 0, 0 },
4590 { "mc", 0, 0, 0, 0 },
4591 { "md", 0, 0, 0, 0 },
4592 { "nest", opt_nest, 0, 0, 0 },
4593 { "next", skip_to_comma, 0, 0, 0 },
4594 { "o", 0, 0, 0, 0 },
4595 { "old", 0, 0, 0, 0 },
4596 { "op", skip_to_comma, 0, 0, 0 },
4597 { "pco", 0, 0, 0, 0 },
4598 { "p", opt_chip, 0, 0, 0 },
4599 { "pcr", 0, 0, 0, 0 },
4600 { "pcs", 0, 0, 0, 0 },
4601 { "r", 0, 0, 0, 0 },
4602 { "quick", 0, &m68k_quick, 1, 0 },
4603 { "rel32", 0, &m68k_rel32, 1, 0 },
4604 { "s", opt_list, 0, 0, 0 },
4605 { "t", opt_list_symbols, 0, 0, 0 },
4606 { "w", 0, &flag_no_warnings, 0, 1 },
4607 { "x", 0, 0, 0, 0 }
4608 };
4609
4610 #define OPTCOUNT (sizeof opt_table / sizeof opt_table[0])
4611
4612 /* The MRI OPT pseudo-op. */
4613
4614 static void
4615 s_opt (ignore)
4616 int ignore;
4617 {
4618 do
4619 {
4620 int t;
4621 char *s;
4622 char c;
4623 int i;
4624 const struct opt_action *o;
4625
4626 SKIP_WHITESPACE ();
4627
4628 t = 1;
4629 if (*input_line_pointer == '-')
4630 {
4631 ++input_line_pointer;
4632 t = 0;
4633 }
4634 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
4635 {
4636 input_line_pointer += 2;
4637 t = 0;
4638 }
4639
4640 s = input_line_pointer;
4641 c = get_symbol_end ();
4642
4643 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
4644 {
4645 if (strcasecmp (s, o->name) == 0)
4646 {
4647 if (o->pfn)
4648 {
4649 /* Restore input_line_pointer now in case the option
4650 takes arguments. */
4651 *input_line_pointer = c;
4652 (*o->pfn) (o->arg, t);
4653 }
4654 else if (o->pvar != NULL)
4655 {
4656 if (! t && o->arg == o->notarg)
4657 as_bad ("option `%s' may not be negated", s);
4658 *input_line_pointer = c;
4659 *o->pvar = t ? o->arg : o->notarg;
4660 }
4661 else
4662 *input_line_pointer = c;
4663 break;
4664 }
4665 }
4666 if (i >= OPTCOUNT)
4667 {
4668 as_bad ("option `%s' not recognized", s);
4669 *input_line_pointer = c;
4670 }
4671 }
4672 while (*input_line_pointer++ == ',');
4673
4674 /* Move back to terminating character. */
4675 --input_line_pointer;
4676 demand_empty_rest_of_line ();
4677 }
4678
4679 /* Skip ahead to a comma. This is used for OPT options which we do
4680 not suppor tand which take arguments. */
4681
4682 static void
4683 skip_to_comma (arg, on)
4684 int arg;
4685 int on;
4686 {
4687 while (*input_line_pointer != ','
4688 && ! is_end_of_line[(unsigned char) *input_line_pointer])
4689 ++input_line_pointer;
4690 }
4691
4692 /* Handle the OPT NEST=depth option. */
4693
4694 static void
4695 opt_nest (arg, on)
4696 int arg;
4697 int on;
4698 {
4699 if (*input_line_pointer != '=')
4700 {
4701 as_bad ("bad format of OPT NEST=depth");
4702 return;
4703 }
4704
4705 ++input_line_pointer;
4706 max_macro_nest = get_absolute_expression ();
4707 }
4708
4709 /* Handle the OPT P=chip option. */
4710
4711 static void
4712 opt_chip (arg, on)
4713 int arg;
4714 int on;
4715 {
4716 if (*input_line_pointer != '=')
4717 {
4718 /* This is just OPT P, which we do not support. */
4719 return;
4720 }
4721
4722 ++input_line_pointer;
4723 mri_chip ();
4724 }
4725
4726 /* Handle the OPT S option. */
4727
4728 static void
4729 opt_list (arg, on)
4730 int arg;
4731 int on;
4732 {
4733 listing_list (on);
4734 }
4735
4736 /* Handle the OPT T option. */
4737
4738 static void
4739 opt_list_symbols (arg, on)
4740 int arg;
4741 int on;
4742 {
4743 if (on)
4744 listing |= LISTING_SYMBOLS;
4745 else
4746 listing &=~ LISTING_SYMBOLS;
4747 }
4748
4749 /* Handle the MRI REG pseudo-op. */
4750
4751 static void
4752 s_reg (ignore)
4753 int ignore;
4754 {
4755 char *s;
4756 int c;
4757 struct m68k_op rop;
4758 unsigned long mask;
4759 char *stop = NULL;
4760 char stopc;
4761
4762 if (line_label == NULL)
4763 {
4764 as_bad ("missing label");
4765 ignore_rest_of_line ();
4766 return;
4767 }
4768
4769 if (flag_mri)
4770 stop = mri_comment_field (&stopc);
4771
4772 SKIP_WHITESPACE ();
4773
4774 s = input_line_pointer;
4775 while (isalnum ((unsigned char) *input_line_pointer)
4776 #ifdef REGISTER_PREFIX
4777 || *input_line_pointer == REGISTER_PREFIX
4778 #endif
4779 || *input_line_pointer == '/'
4780 || *input_line_pointer == '-')
4781 ++input_line_pointer;
4782 c = *input_line_pointer;
4783 *input_line_pointer = '\0';
4784
4785 if (m68k_ip_op (s, &rop) != 0)
4786 {
4787 if (rop.error == NULL)
4788 as_bad ("bad register list");
4789 else
4790 as_bad ("bad register list: %s", rop.error);
4791 *input_line_pointer = c;
4792 ignore_rest_of_line ();
4793 return;
4794 }
4795
4796 *input_line_pointer = c;
4797
4798 if (rop.mode == REGLST)
4799 mask = rop.mask;
4800 else if (rop.mode == DREG)
4801 mask = 1 << (rop.reg - DATA0);
4802 else if (rop.mode == AREG)
4803 mask = 1 << (rop.reg - ADDR0 + 8);
4804 else if (rop.mode == FPREG)
4805 mask = 1 << (rop.reg - FP0 + 16);
4806 else if (rop.mode == CONTROL
4807 && rop.reg == FPI)
4808 mask = 1 << 24;
4809 else if (rop.mode == CONTROL
4810 && rop.reg == FPS)
4811 mask = 1 << 25;
4812 else if (rop.mode == CONTROL
4813 && rop.reg == FPC)
4814 mask = 1 << 26;
4815 else
4816 {
4817 as_bad ("bad register list");
4818 ignore_rest_of_line ();
4819 return;
4820 }
4821
4822 S_SET_SEGMENT (line_label, absolute_section);
4823 S_SET_VALUE (line_label, mask);
4824 line_label->sy_frag = &zero_address_frag;
4825
4826 if (flag_mri)
4827 mri_comment_end (stop, stopc);
4828
4829 demand_empty_rest_of_line ();
4830 }
4831
4832 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
4833
4834 struct save_opts
4835 {
4836 struct save_opts *next;
4837 int abspcadd;
4838 int symbols_case_sensitive;
4839 int keep_locals;
4840 int short_refs;
4841 int architecture;
4842 int quick;
4843 int rel32;
4844 int listing;
4845 int no_warnings;
4846 /* FIXME: We don't save OPT S. */
4847 };
4848
4849 /* This variable holds the stack of saved options. */
4850
4851 static struct save_opts *save_stack;
4852
4853 /* The MRI SAVE pseudo-op. */
4854
4855 static void
4856 s_save (ignore)
4857 int ignore;
4858 {
4859 struct save_opts *s;
4860
4861 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
4862 s->abspcadd = m68k_abspcadd;
4863 s->symbols_case_sensitive = symbols_case_sensitive;
4864 s->keep_locals = flag_keep_locals;
4865 s->short_refs = flag_short_refs;
4866 s->architecture = current_architecture;
4867 s->quick = m68k_quick;
4868 s->rel32 = m68k_rel32;
4869 s->listing = listing;
4870 s->no_warnings = flag_no_warnings;
4871
4872 s->next = save_stack;
4873 save_stack = s;
4874
4875 demand_empty_rest_of_line ();
4876 }
4877
4878 /* The MRI RESTORE pseudo-op. */
4879
4880 static void
4881 s_restore (ignore)
4882 int ignore;
4883 {
4884 struct save_opts *s;
4885
4886 if (save_stack == NULL)
4887 {
4888 as_bad ("restore without save");
4889 ignore_rest_of_line ();
4890 return;
4891 }
4892
4893 s = save_stack;
4894 save_stack = s->next;
4895
4896 m68k_abspcadd = s->abspcadd;
4897 symbols_case_sensitive = s->symbols_case_sensitive;
4898 flag_keep_locals = s->keep_locals;
4899 flag_short_refs = s->short_refs;
4900 current_architecture = s->architecture;
4901 m68k_quick = s->quick;
4902 m68k_rel32 = s->rel32;
4903 listing = s->listing;
4904 flag_no_warnings = s->no_warnings;
4905
4906 free (s);
4907
4908 demand_empty_rest_of_line ();
4909 }
4910
4911 /* Types of MRI structured control directives. */
4912
4913 enum mri_control_type
4914 {
4915 mri_for,
4916 mri_if,
4917 mri_repeat,
4918 mri_while
4919 };
4920
4921 /* This structure is used to stack the MRI structured control
4922 directives. */
4923
4924 struct mri_control_info
4925 {
4926 /* The directive within which this one is enclosed. */
4927 struct mri_control_info *outer;
4928
4929 /* The type of directive. */
4930 enum mri_control_type type;
4931
4932 /* Whether an ELSE has been in an IF. */
4933 int else_seen;
4934
4935 /* The add or sub statement at the end of a FOR. */
4936 char *incr;
4937
4938 /* The label of the top of a FOR or REPEAT loop. */
4939 char *top;
4940
4941 /* The label to jump to for the next iteration, or the else
4942 expression of a conditional. */
4943 char *next;
4944
4945 /* The label to jump to to break out of the loop, or the label past
4946 the end of a conditional. */
4947 char *bottom;
4948 };
4949
4950 /* The stack of MRI structured control directives. */
4951
4952 static struct mri_control_info *mri_control_stack;
4953
4954 /* The current MRI structured control directive index number, used to
4955 generate label names. */
4956
4957 static int mri_control_index;
4958
4959 /* Some function prototypes. */
4960
4961 static char *mri_control_label PARAMS ((void));
4962 static struct mri_control_info *push_mri_control
4963 PARAMS ((enum mri_control_type));
4964 static void pop_mri_control PARAMS ((void));
4965 static int parse_mri_condition PARAMS ((int *));
4966 static int parse_mri_control_operand
4967 PARAMS ((int *, char **, char **, char **, char **));
4968 static int swap_mri_condition PARAMS ((int));
4969 static int reverse_mri_condition PARAMS ((int));
4970 static void build_mri_control_operand
4971 PARAMS ((int, int, char *, char *, char *, char *, const char *,
4972 const char *, int));
4973 static void parse_mri_control_expression
4974 PARAMS ((char *, int, const char *, const char *, int));
4975
4976 /* Generate a new MRI label structured control directive label name. */
4977
4978 static char *
4979 mri_control_label ()
4980 {
4981 char *n;
4982
4983 n = (char *) xmalloc (20);
4984 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
4985 ++mri_control_index;
4986 return n;
4987 }
4988
4989 /* Create a new MRI structured control directive. */
4990
4991 static struct mri_control_info *
4992 push_mri_control (type)
4993 enum mri_control_type type;
4994 {
4995 struct mri_control_info *n;
4996
4997 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
4998
4999 n->type = type;
5000 n->else_seen = 0;
5001 if (type == mri_if || type == mri_while)
5002 n->top = NULL;
5003 else
5004 n->top = mri_control_label ();
5005 n->next = mri_control_label ();
5006 n->bottom = mri_control_label ();
5007
5008 n->outer = mri_control_stack;
5009 mri_control_stack = n;
5010
5011 return n;
5012 }
5013
5014 /* Pop off the stack of MRI structured control directives. */
5015
5016 static void
5017 pop_mri_control ()
5018 {
5019 struct mri_control_info *n;
5020
5021 n = mri_control_stack;
5022 mri_control_stack = n->outer;
5023 if (n->top != NULL)
5024 free (n->top);
5025 free (n->next);
5026 free (n->bottom);
5027 free (n);
5028 }
5029
5030 /* Recognize a condition code in an MRI structured control expression. */
5031
5032 static int
5033 parse_mri_condition (pcc)
5034 int *pcc;
5035 {
5036 char c1, c2;
5037
5038 know (*input_line_pointer == '<');
5039
5040 ++input_line_pointer;
5041 c1 = *input_line_pointer++;
5042 c2 = *input_line_pointer++;
5043
5044 if (*input_line_pointer != '>')
5045 {
5046 as_bad ("syntax error in structured control directive");
5047 return 0;
5048 }
5049
5050 ++input_line_pointer;
5051 SKIP_WHITESPACE ();
5052
5053 if (isupper (c1))
5054 c1 = tolower (c1);
5055 if (isupper (c2))
5056 c2 = tolower (c2);
5057
5058 *pcc = (c1 << 8) | c2;
5059
5060 return 1;
5061 }
5062
5063 /* Parse a single operand in an MRI structured control expression. */
5064
5065 static int
5066 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5067 int *pcc;
5068 char **leftstart;
5069 char **leftstop;
5070 char **rightstart;
5071 char **rightstop;
5072 {
5073 char *s;
5074
5075 SKIP_WHITESPACE ();
5076
5077 *pcc = -1;
5078 *leftstart = NULL;
5079 *leftstop = NULL;
5080 *rightstart = NULL;
5081 *rightstop = NULL;
5082
5083 if (*input_line_pointer == '<')
5084 {
5085 /* It's just a condition code. */
5086 return parse_mri_condition (pcc);
5087 }
5088
5089 /* Look ahead for the condition code. */
5090 for (s = input_line_pointer; *s != '\0'; ++s)
5091 {
5092 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5093 break;
5094 }
5095 if (*s == '\0')
5096 {
5097 as_bad ("missing condition code in structured control directive");
5098 return 0;
5099 }
5100
5101 *leftstart = input_line_pointer;
5102 *leftstop = s;
5103 if (*leftstop > *leftstart
5104 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5105 --*leftstop;
5106
5107 input_line_pointer = s;
5108 if (! parse_mri_condition (pcc))
5109 return 0;
5110
5111 /* Look ahead for AND or OR or end of line. */
5112 for (s = input_line_pointer; *s != '\0'; ++s)
5113 {
5114 if ((strncasecmp (s, "AND", 3) == 0
5115 && (s[3] == '.' || ! is_part_of_name (s[3])))
5116 || (strncasecmp (s, "OR", 2) == 0
5117 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5118 break;
5119 }
5120
5121 *rightstart = input_line_pointer;
5122 *rightstop = s;
5123 if (*rightstop > *rightstart
5124 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5125 --*rightstop;
5126
5127 input_line_pointer = s;
5128
5129 return 1;
5130 }
5131
5132 #define MCC(b1, b2) (((b1) << 8) | (b2))
5133
5134 /* Swap the sense of a condition. This changes the condition so that
5135 it generates the same result when the operands are swapped. */
5136
5137 static int
5138 swap_mri_condition (cc)
5139 int cc;
5140 {
5141 switch (cc)
5142 {
5143 case MCC ('h', 'i'): return MCC ('c', 's');
5144 case MCC ('l', 's'): return MCC ('c', 'c');
5145 case MCC ('c', 'c'): return MCC ('l', 's');
5146 case MCC ('c', 's'): return MCC ('h', 'i');
5147 case MCC ('p', 'l'): return MCC ('m', 'i');
5148 case MCC ('m', 'i'): return MCC ('p', 'l');
5149 case MCC ('g', 'e'): return MCC ('l', 'e');
5150 case MCC ('l', 't'): return MCC ('g', 't');
5151 case MCC ('g', 't'): return MCC ('l', 't');
5152 case MCC ('l', 'e'): return MCC ('g', 'e');
5153 }
5154 return cc;
5155 }
5156
5157 /* Reverse the sense of a condition. */
5158
5159 static int
5160 reverse_mri_condition (cc)
5161 int cc;
5162 {
5163 switch (cc)
5164 {
5165 case MCC ('h', 'i'): return MCC ('l', 's');
5166 case MCC ('l', 's'): return MCC ('h', 'i');
5167 case MCC ('c', 'c'): return MCC ('c', 's');
5168 case MCC ('c', 's'): return MCC ('c', 'c');
5169 case MCC ('n', 'e'): return MCC ('e', 'q');
5170 case MCC ('e', 'q'): return MCC ('n', 'e');
5171 case MCC ('v', 'c'): return MCC ('v', 's');
5172 case MCC ('v', 's'): return MCC ('v', 'c');
5173 case MCC ('p', 'l'): return MCC ('m', 'i');
5174 case MCC ('m', 'i'): return MCC ('p', 'l');
5175 case MCC ('g', 'e'): return MCC ('l', 't');
5176 case MCC ('l', 't'): return MCC ('g', 'e');
5177 case MCC ('g', 't'): return MCC ('l', 'e');
5178 case MCC ('l', 'e'): return MCC ('g', 't');
5179 }
5180 return cc;
5181 }
5182
5183 /* Build an MRI structured control expression. This generates test
5184 and branch instructions. It goes to TRUELAB if the condition is
5185 true, and to FALSELAB if the condition is false. Exactly one of
5186 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5187 is the size qualifier for the expression. EXTENT is the size to
5188 use for the branch. */
5189
5190 static void
5191 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5192 rightstop, truelab, falselab, extent)
5193 int qual;
5194 int cc;
5195 char *leftstart;
5196 char *leftstop;
5197 char *rightstart;
5198 char *rightstop;
5199 const char *truelab;
5200 const char *falselab;
5201 int extent;
5202 {
5203 char *buf;
5204 char *s;
5205
5206 if (leftstart != NULL)
5207 {
5208 struct m68k_op leftop, rightop;
5209 char c;
5210
5211 /* Swap the compare operands, if necessary, to produce a legal
5212 m68k compare instruction. Comparing a register operand with
5213 a non-register operand requires the register to be on the
5214 right (cmp, cmpa). Comparing an immediate value with
5215 anything requires the immediate value to be on the left
5216 (cmpi). */
5217
5218 c = *leftstop;
5219 *leftstop = '\0';
5220 (void) m68k_ip_op (leftstart, &leftop);
5221 *leftstop = c;
5222
5223 c = *rightstop;
5224 *rightstop = '\0';
5225 (void) m68k_ip_op (rightstart, &rightop);
5226 *rightstop = c;
5227
5228 if (rightop.mode == IMMED
5229 || ((leftop.mode == DREG || leftop.mode == AREG)
5230 && (rightop.mode != DREG && rightop.mode != AREG)))
5231 {
5232 char *temp;
5233
5234 cc = swap_mri_condition (cc);
5235 temp = leftstart;
5236 leftstart = rightstart;
5237 rightstart = temp;
5238 temp = leftstop;
5239 leftstop = rightstop;
5240 rightstop = temp;
5241 }
5242 }
5243
5244 if (truelab == NULL)
5245 {
5246 cc = reverse_mri_condition (cc);
5247 truelab = falselab;
5248 }
5249
5250 if (leftstart != NULL)
5251 {
5252 buf = (char *) xmalloc (20
5253 + (leftstop - leftstart)
5254 + (rightstop - rightstart));
5255 s = buf;
5256 *s++ = 'c';
5257 *s++ = 'm';
5258 *s++ = 'p';
5259 if (qual != '\0')
5260 *s++ = qual;
5261 *s++ = ' ';
5262 memcpy (s, leftstart, leftstop - leftstart);
5263 s += leftstop - leftstart;
5264 *s++ = ',';
5265 memcpy (s, rightstart, rightstop - rightstart);
5266 s += rightstop - rightstart;
5267 *s = '\0';
5268 md_assemble (buf);
5269 free (buf);
5270 }
5271
5272 buf = (char *) xmalloc (20 + strlen (truelab));
5273 s = buf;
5274 *s++ = 'b';
5275 *s++ = cc >> 8;
5276 *s++ = cc & 0xff;
5277 if (extent != '\0')
5278 *s++ = extent;
5279 *s++ = ' ';
5280 strcpy (s, truelab);
5281 md_assemble (buf);
5282 free (buf);
5283 }
5284
5285 /* Parse an MRI structured control expression. This generates test
5286 and branch instructions. STOP is where the expression ends. It
5287 goes to TRUELAB if the condition is true, and to FALSELAB if the
5288 condition is false. Exactly one of TRUELAB and FALSELAB will be
5289 NULL, meaning to fall through. QUAL is the size qualifier for the
5290 expression. EXTENT is the size to use for the branch. */
5291
5292 static void
5293 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5294 char *stop;
5295 int qual;
5296 const char *truelab;
5297 const char *falselab;
5298 int extent;
5299 {
5300 int c;
5301 int cc;
5302 char *leftstart;
5303 char *leftstop;
5304 char *rightstart;
5305 char *rightstop;
5306
5307 c = *stop;
5308 *stop = '\0';
5309
5310 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5311 &rightstart, &rightstop))
5312 {
5313 *stop = c;
5314 return;
5315 }
5316
5317 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5318 {
5319 const char *flab;
5320
5321 if (falselab != NULL)
5322 flab = falselab;
5323 else
5324 flab = mri_control_label ();
5325
5326 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5327 rightstop, (const char *) NULL, flab, extent);
5328
5329 input_line_pointer += 3;
5330 if (*input_line_pointer != '.'
5331 || input_line_pointer[1] == '\0')
5332 qual = '\0';
5333 else
5334 {
5335 qual = input_line_pointer[1];
5336 input_line_pointer += 2;
5337 }
5338
5339 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5340 &rightstart, &rightstop))
5341 {
5342 *stop = c;
5343 return;
5344 }
5345
5346 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5347 rightstop, truelab, falselab, extent);
5348
5349 if (falselab == NULL)
5350 colon (flab);
5351 }
5352 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
5353 {
5354 const char *tlab;
5355
5356 if (truelab != NULL)
5357 tlab = truelab;
5358 else
5359 tlab = mri_control_label ();
5360
5361 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5362 rightstop, tlab, (const char *) NULL, extent);
5363
5364 input_line_pointer += 2;
5365 if (*input_line_pointer != '.'
5366 || input_line_pointer[1] == '\0')
5367 qual = '\0';
5368 else
5369 {
5370 qual = input_line_pointer[1];
5371 input_line_pointer += 2;
5372 }
5373
5374 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5375 &rightstart, &rightstop))
5376 {
5377 *stop = c;
5378 return;
5379 }
5380
5381 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5382 rightstop, truelab, falselab, extent);
5383
5384 if (truelab == NULL)
5385 colon (tlab);
5386 }
5387 else
5388 {
5389 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5390 rightstop, truelab, falselab, extent);
5391 }
5392
5393 *stop = c;
5394 if (input_line_pointer != stop)
5395 as_bad ("syntax error in structured control directive");
5396 }
5397
5398 /* Handle the MRI IF pseudo-op. This may be a structured control
5399 directive, or it may be a regular assembler conditional, depending
5400 on its operands. */
5401
5402 static void
5403 s_mri_if (qual)
5404 int qual;
5405 {
5406 char *s;
5407 int c;
5408 struct mri_control_info *n;
5409
5410 /* A structured control directive must end with THEN with an
5411 optional qualifier. */
5412 s = input_line_pointer;
5413 while (! is_end_of_line[(unsigned char) *s]
5414 && (! flag_mri || *s != '*'))
5415 ++s;
5416 --s;
5417 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
5418 --s;
5419
5420 if (s - input_line_pointer > 1
5421 && s[-1] == '.')
5422 s -= 2;
5423
5424 if (s - input_line_pointer < 3
5425 || strncasecmp (s - 3, "THEN", 4) != 0)
5426 {
5427 if (qual != '\0')
5428 {
5429 as_bad ("missing then");
5430 ignore_rest_of_line ();
5431 return;
5432 }
5433
5434 /* It's a conditional. */
5435 s_if (O_ne);
5436 return;
5437 }
5438
5439 /* Since this might be a conditional if, this pseudo-op will be
5440 called even if we are supported to be ignoring input. Double
5441 check now. Clobber *input_line_pointer so that ignore_input
5442 thinks that this is not a special pseudo-op. */
5443 c = *input_line_pointer;
5444 *input_line_pointer = 0;
5445 if (ignore_input ())
5446 {
5447 *input_line_pointer = c;
5448 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5449 ++input_line_pointer;
5450 demand_empty_rest_of_line ();
5451 return;
5452 }
5453 *input_line_pointer = c;
5454
5455 n = push_mri_control (mri_if);
5456
5457 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
5458 n->next, s[1] == '.' ? s[2] : '\0');
5459
5460 if (s[1] == '.')
5461 input_line_pointer = s + 3;
5462 else
5463 input_line_pointer = s + 1;
5464
5465 if (flag_mri)
5466 {
5467 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5468 ++input_line_pointer;
5469 }
5470
5471 demand_empty_rest_of_line ();
5472 }
5473
5474 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
5475 structured IF, associate the ELSE with the IF. Otherwise, assume
5476 it is a conditional else. */
5477
5478 static void
5479 s_mri_else (qual)
5480 int qual;
5481 {
5482 int c;
5483 char *buf;
5484 char q[2];
5485
5486 if (qual == '\0'
5487 && (mri_control_stack == NULL
5488 || mri_control_stack->type != mri_if
5489 || mri_control_stack->else_seen))
5490 {
5491 s_else (0);
5492 return;
5493 }
5494
5495 c = *input_line_pointer;
5496 *input_line_pointer = 0;
5497 if (ignore_input ())
5498 {
5499 *input_line_pointer = c;
5500 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5501 ++input_line_pointer;
5502 demand_empty_rest_of_line ();
5503 return;
5504 }
5505 *input_line_pointer = c;
5506
5507 if (mri_control_stack == NULL
5508 || mri_control_stack->type != mri_if
5509 || mri_control_stack->else_seen)
5510 {
5511 as_bad ("else without matching if");
5512 ignore_rest_of_line ();
5513 return;
5514 }
5515
5516 mri_control_stack->else_seen = 1;
5517
5518 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
5519 q[0] = qual;
5520 q[1] = '\0';
5521 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
5522 md_assemble (buf);
5523 free (buf);
5524
5525 colon (mri_control_stack->next);
5526
5527 if (flag_mri)
5528 {
5529 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5530 ++input_line_pointer;
5531 }
5532
5533 demand_empty_rest_of_line ();
5534 }
5535
5536 /* Handle the MRI ENDI pseudo-op. */
5537
5538 static void
5539 s_mri_endi (ignore)
5540 int ignore;
5541 {
5542 if (mri_control_stack == NULL
5543 || mri_control_stack->type != mri_if)
5544 {
5545 as_bad ("endi without matching if");
5546 ignore_rest_of_line ();
5547 return;
5548 }
5549
5550 /* ignore_input will not return true for ENDI, so we don't need to
5551 worry about checking it again here. */
5552
5553 if (! mri_control_stack->else_seen)
5554 colon (mri_control_stack->next);
5555 colon (mri_control_stack->bottom);
5556
5557 pop_mri_control ();
5558
5559 if (flag_mri)
5560 {
5561 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5562 ++input_line_pointer;
5563 }
5564
5565 demand_empty_rest_of_line ();
5566 }
5567
5568 /* Handle the MRI BREAK pseudo-op. */
5569
5570 static void
5571 s_mri_break (extent)
5572 int extent;
5573 {
5574 struct mri_control_info *n;
5575 char *buf;
5576 char ex[2];
5577
5578 n = mri_control_stack;
5579 while (n != NULL
5580 && n->type != mri_for
5581 && n->type != mri_repeat
5582 && n->type != mri_while)
5583 n = n->outer;
5584 if (n == NULL)
5585 {
5586 as_bad ("break outside of structured loop");
5587 ignore_rest_of_line ();
5588 return;
5589 }
5590
5591 buf = (char *) xmalloc (20 + strlen (n->bottom));
5592 ex[0] = extent;
5593 ex[1] = '\0';
5594 sprintf (buf, "bra%s %s", ex, n->bottom);
5595 md_assemble (buf);
5596 free (buf);
5597
5598 if (flag_mri)
5599 {
5600 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5601 ++input_line_pointer;
5602 }
5603
5604 demand_empty_rest_of_line ();
5605 }
5606
5607 /* Handle the MRI NEXT pseudo-op. */
5608
5609 static void
5610 s_mri_next (extent)
5611 int extent;
5612 {
5613 struct mri_control_info *n;
5614 char *buf;
5615 char ex[2];
5616
5617 n = mri_control_stack;
5618 while (n != NULL
5619 && n->type != mri_for
5620 && n->type != mri_repeat
5621 && n->type != mri_while)
5622 n = n->outer;
5623 if (n == NULL)
5624 {
5625 as_bad ("next outside of structured loop");
5626 ignore_rest_of_line ();
5627 return;
5628 }
5629
5630 buf = (char *) xmalloc (20 + strlen (n->next));
5631 ex[0] = extent;
5632 ex[1] = '\0';
5633 sprintf (buf, "bra%s %s", ex, n->next);
5634 md_assemble (buf);
5635 free (buf);
5636
5637 if (flag_mri)
5638 {
5639 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5640 ++input_line_pointer;
5641 }
5642
5643 demand_empty_rest_of_line ();
5644 }
5645
5646 /* Handle the MRI FOR pseudo-op. */
5647
5648 static void
5649 s_mri_for (qual)
5650 int qual;
5651 {
5652 const char *varstart, *varstop;
5653 const char *initstart, *initstop;
5654 const char *endstart, *endstop;
5655 const char *bystart, *bystop;
5656 int up;
5657 int by;
5658 int extent;
5659 struct mri_control_info *n;
5660 char *buf;
5661 char *s;
5662 char ex[2];
5663
5664 /* The syntax is
5665 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
5666 */
5667
5668 SKIP_WHITESPACE ();
5669 varstart = input_line_pointer;
5670
5671 /* Look for the '='. */
5672 while (! is_end_of_line[(unsigned char) *input_line_pointer]
5673 && *input_line_pointer != '=')
5674 ++input_line_pointer;
5675 if (*input_line_pointer != '=')
5676 {
5677 as_bad ("missing =");
5678 ignore_rest_of_line ();
5679 return;
5680 }
5681
5682 varstop = input_line_pointer;
5683 if (varstop > varstart
5684 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
5685 --varstop;
5686
5687 ++input_line_pointer;
5688
5689 initstart = input_line_pointer;
5690
5691 /* Look for TO or DOWNTO. */
5692 up = 1;
5693 initstop = NULL;
5694 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5695 {
5696 if (strncasecmp (input_line_pointer, "TO", 2) == 0
5697 && ! is_part_of_name (input_line_pointer[2]))
5698 {
5699 initstop = input_line_pointer;
5700 input_line_pointer += 2;
5701 break;
5702 }
5703 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
5704 && ! is_part_of_name (input_line_pointer[6]))
5705 {
5706 initstop = input_line_pointer;
5707 up = 0;
5708 input_line_pointer += 6;
5709 break;
5710 }
5711 ++input_line_pointer;
5712 }
5713 if (initstop == NULL)
5714 {
5715 as_bad ("missing to or downto");
5716 ignore_rest_of_line ();
5717 return;
5718 }
5719 if (initstop > initstart
5720 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
5721 --initstop;
5722
5723 SKIP_WHITESPACE ();
5724 endstart = input_line_pointer;
5725
5726 /* Look for BY or DO. */
5727 by = 0;
5728 endstop = NULL;
5729 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5730 {
5731 if (strncasecmp (input_line_pointer, "BY", 2) == 0
5732 && ! is_part_of_name (input_line_pointer[2]))
5733 {
5734 endstop = input_line_pointer;
5735 by = 1;
5736 input_line_pointer += 2;
5737 break;
5738 }
5739 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5740 && (input_line_pointer[2] == '.'
5741 || ! is_part_of_name (input_line_pointer[2])))
5742 {
5743 endstop = input_line_pointer;
5744 input_line_pointer += 2;
5745 break;
5746 }
5747 ++input_line_pointer;
5748 }
5749 if (endstop == NULL)
5750 {
5751 as_bad ("missing do");
5752 ignore_rest_of_line ();
5753 return;
5754 }
5755 if (endstop > endstart
5756 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
5757 --endstop;
5758
5759 if (! by)
5760 {
5761 bystart = "#1";
5762 bystop = bystart + 2;
5763 }
5764 else
5765 {
5766 SKIP_WHITESPACE ();
5767 bystart = input_line_pointer;
5768
5769 /* Look for DO. */
5770 bystop = NULL;
5771 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5772 {
5773 if (strncasecmp (input_line_pointer, "DO", 2) == 0
5774 && (input_line_pointer[2] == '.'
5775 || ! is_part_of_name (input_line_pointer[2])))
5776 {
5777 bystop = input_line_pointer;
5778 input_line_pointer += 2;
5779 break;
5780 }
5781 ++input_line_pointer;
5782 }
5783 if (bystop == NULL)
5784 {
5785 as_bad ("missing do");
5786 ignore_rest_of_line ();
5787 return;
5788 }
5789 if (bystop > bystart
5790 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
5791 --bystop;
5792 }
5793
5794 if (*input_line_pointer != '.')
5795 extent = '\0';
5796 else
5797 {
5798 extent = input_line_pointer[1];
5799 input_line_pointer += 2;
5800 }
5801
5802 /* We have fully parsed the FOR operands. Now build the loop. */
5803
5804 n = push_mri_control (mri_for);
5805
5806 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
5807
5808 /* move init,var */
5809 s = buf;
5810 *s++ = 'm';
5811 *s++ = 'o';
5812 *s++ = 'v';
5813 *s++ = 'e';
5814 if (qual != '\0')
5815 *s++ = qual;
5816 *s++ = ' ';
5817 memcpy (s, initstart, initstop - initstart);
5818 s += initstop - initstart;
5819 *s++ = ',';
5820 memcpy (s, varstart, varstop - varstart);
5821 s += varstop - varstart;
5822 *s = '\0';
5823 md_assemble (buf);
5824
5825 colon (n->top);
5826
5827 /* cmp end,var */
5828 s = buf;
5829 *s++ = 'c';
5830 *s++ = 'm';
5831 *s++ = 'p';
5832 if (qual != '\0')
5833 *s++ = qual;
5834 *s++ = ' ';
5835 memcpy (s, endstart, endstop - endstart);
5836 s += endstop - endstart;
5837 *s++ = ',';
5838 memcpy (s, varstart, varstop - varstart);
5839 s += varstop - varstart;
5840 *s = '\0';
5841 md_assemble (buf);
5842
5843 /* bcc bottom */
5844 ex[0] = extent;
5845 ex[1] = '\0';
5846 if (up)
5847 sprintf (buf, "blt%s %s", ex, n->bottom);
5848 else
5849 sprintf (buf, "bgt%s %s", ex, n->bottom);
5850 md_assemble (buf);
5851
5852 /* Put together the add or sub instruction used by ENDF. */
5853 s = buf;
5854 if (up)
5855 strcpy (s, "add");
5856 else
5857 strcpy (s, "sub");
5858 s += 3;
5859 if (qual != '\0')
5860 *s++ = qual;
5861 *s++ = ' ';
5862 memcpy (s, bystart, bystop - bystart);
5863 s += bystop - bystart;
5864 *s++ = ',';
5865 memcpy (s, varstart, varstop - varstart);
5866 s += varstop - varstart;
5867 *s = '\0';
5868 n->incr = buf;
5869
5870 if (flag_mri)
5871 {
5872 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5873 ++input_line_pointer;
5874 }
5875
5876 demand_empty_rest_of_line ();
5877 }
5878
5879 /* Handle the MRI ENDF pseudo-op. */
5880
5881 static void
5882 s_mri_endf (ignore)
5883 int ignore;
5884 {
5885 if (mri_control_stack == NULL
5886 || mri_control_stack->type != mri_for)
5887 {
5888 as_bad ("endf without for");
5889 ignore_rest_of_line ();
5890 return;
5891 }
5892
5893 colon (mri_control_stack->next);
5894
5895 md_assemble (mri_control_stack->incr);
5896
5897 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
5898 md_assemble (mri_control_stack->incr);
5899
5900 free (mri_control_stack->incr);
5901
5902 colon (mri_control_stack->bottom);
5903
5904 pop_mri_control ();
5905
5906 if (flag_mri)
5907 {
5908 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5909 ++input_line_pointer;
5910 }
5911
5912 demand_empty_rest_of_line ();
5913 }
5914
5915 /* Handle the MRI REPEAT pseudo-op. */
5916
5917 static void
5918 s_mri_repeat (ignore)
5919 int ignore;
5920 {
5921 struct mri_control_info *n;
5922
5923 n = push_mri_control (mri_repeat);
5924 colon (n->top);
5925 if (flag_mri)
5926 {
5927 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5928 ++input_line_pointer;
5929 }
5930 demand_empty_rest_of_line ();
5931 }
5932
5933 /* Handle the MRI UNTIL pseudo-op. */
5934
5935 static void
5936 s_mri_until (qual)
5937 int qual;
5938 {
5939 char *s;
5940
5941 if (mri_control_stack == NULL
5942 || mri_control_stack->type != mri_repeat)
5943 {
5944 as_bad ("until without repeat");
5945 ignore_rest_of_line ();
5946 return;
5947 }
5948
5949 colon (mri_control_stack->next);
5950
5951 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
5952 ;
5953
5954 parse_mri_control_expression (s, qual, (const char *) NULL,
5955 mri_control_stack->top, '\0');
5956
5957 colon (mri_control_stack->bottom);
5958
5959 input_line_pointer = s;
5960
5961 pop_mri_control ();
5962
5963 if (flag_mri)
5964 {
5965 while (! is_end_of_line[(unsigned char) *input_line_pointer])
5966 ++input_line_pointer;
5967 }
5968
5969 demand_empty_rest_of_line ();
5970 }
5971
5972 /* Handle the MRI WHILE pseudo-op. */
5973
5974 static void
5975 s_mri_while (qual)
5976 int qual;
5977 {
5978 char *s;
5979
5980 struct mri_control_info *n;
5981
5982 s = input_line_pointer;
5983 while (! is_end_of_line[(unsigned char) *s]
5984 && (! flag_mri || *s != '*'))
5985 s++;
5986 --s;
5987 while (*s == ' ' || *s == '\t')
5988 --s;
5989 if (s - input_line_pointer > 1
5990 && s[-1] == '.')
5991 s -= 2;
5992 if (s - input_line_pointer < 2
5993 || strncasecmp (s - 1, "DO", 2) != 0)
5994 {
5995 as_bad ("missing do");
5996 ignore_rest_of_line ();
5997 return;
5998 }
5999
6000 n = push_mri_control (mri_while);
6001
6002 colon (n->next);
6003
6004 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6005 s[1] == '.' ? s[2] : '\0');
6006
6007 input_line_pointer = s + 1;
6008 if (*input_line_pointer == '.')
6009 input_line_pointer += 2;
6010
6011 if (flag_mri)
6012 {
6013 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6014 ++input_line_pointer;
6015 }
6016
6017 demand_empty_rest_of_line ();
6018 }
6019
6020 /* Handle the MRI ENDW pseudo-op. */
6021
6022 static void
6023 s_mri_endw (ignore)
6024 int ignore;
6025 {
6026 char *buf;
6027
6028 if (mri_control_stack == NULL
6029 || mri_control_stack->type != mri_while)
6030 {
6031 as_bad ("endw without while");
6032 ignore_rest_of_line ();
6033 return;
6034 }
6035
6036 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6037 sprintf (buf, "bra %s", mri_control_stack->next);
6038 md_assemble (buf);
6039 free (buf);
6040
6041 colon (mri_control_stack->bottom);
6042
6043 pop_mri_control ();
6044
6045 if (flag_mri)
6046 {
6047 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6048 ++input_line_pointer;
6049 }
6050
6051 demand_empty_rest_of_line ();
6052 }
6053 \f
6054 /*
6055 * md_parse_option
6056 * Invocation line includes a switch not recognized by the base assembler.
6057 * See if it's a processor-specific option. These are:
6058 *
6059 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6060 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6061 * Select the architecture. Instructions or features not
6062 * supported by the selected architecture cause fatal
6063 * errors. More than one may be specified. The default is
6064 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6065 * for -m68000, and -m68882 is a synonym for -m68881.
6066 * -[A]m[c]no-68851, -[A]m[c]no-68881
6067 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6068 * so don't use or document it, but that's the way the parsing
6069 * works).
6070 *
6071 * -pic Indicates PIC.
6072 * -k Indicates PIC. (Sun 3 only.)
6073 *
6074 */
6075
6076 #ifdef OBJ_ELF
6077 CONST char *md_shortopts = "lSA:m:kQ:V";
6078 #else
6079 CONST char *md_shortopts = "lSA:m:k";
6080 #endif
6081
6082 struct option md_longopts[] = {
6083 #define OPTION_PIC (OPTION_MD_BASE)
6084 {"pic", no_argument, NULL, OPTION_PIC},
6085 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6086 {"register-prefix-optional", no_argument, NULL,
6087 OPTION_REGISTER_PREFIX_OPTIONAL},
6088 {NULL, no_argument, NULL, 0}
6089 };
6090 size_t md_longopts_size = sizeof(md_longopts);
6091
6092 int
6093 md_parse_option (c, arg)
6094 int c;
6095 char *arg;
6096 {
6097 switch (c)
6098 {
6099 case 'l': /* -l means keep external to 2 bit offset
6100 rather than 16 bit one */
6101 flag_short_refs = 1;
6102 break;
6103
6104 case 'S': /* -S means that jbsr's always turn into
6105 jsr's. */
6106 flag_long_jumps = 1;
6107 break;
6108
6109 case 'A':
6110 if (*arg == 'm')
6111 arg++;
6112 /* intentional fall-through */
6113 case 'm':
6114
6115 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6116 {
6117 int i;
6118 unsigned long arch;
6119 const char *oarg = arg;
6120
6121 arg += 3;
6122 if (*arg == 'm')
6123 {
6124 arg++;
6125 if (arg[0] == 'c' && arg[1] == '6')
6126 arg++;
6127 }
6128 for (i = 0; i < n_archs; i++)
6129 if (!strcmp (arg, archs[i].name))
6130 break;
6131 if (i == n_archs)
6132 {
6133 unknown:
6134 as_bad ("unrecognized option `%s'", oarg);
6135 return 0;
6136 }
6137 arch = archs[i].arch;
6138 if (arch == m68881)
6139 no_68881 = 1;
6140 else if (arch == m68851)
6141 no_68851 = 1;
6142 else
6143 goto unknown;
6144 }
6145 else
6146 {
6147 int i;
6148
6149 if (arg[0] == 'c' && arg[1] == '6')
6150 arg++;
6151
6152 for (i = 0; i < n_archs; i++)
6153 if (!strcmp (arg, archs[i].name))
6154 {
6155 unsigned long arch = archs[i].arch;
6156 if (cpu_of_arch (arch))
6157 /* It's a cpu spec. */
6158 {
6159 current_architecture &= ~m68000up;
6160 current_architecture |= arch;
6161 }
6162 else if (arch == m68881)
6163 {
6164 current_architecture |= m68881;
6165 no_68881 = 0;
6166 }
6167 else if (arch == m68851)
6168 {
6169 current_architecture |= m68851;
6170 no_68851 = 0;
6171 }
6172 else
6173 /* ??? */
6174 abort ();
6175 break;
6176 }
6177 if (i == n_archs)
6178 {
6179 as_bad ("unrecognized architecture specification `%s'", arg);
6180 return 0;
6181 }
6182 }
6183 break;
6184
6185 case OPTION_PIC:
6186 case 'k':
6187 flag_want_pic = 1;
6188 break; /* -pic, Position Independent Code */
6189
6190 case OPTION_REGISTER_PREFIX_OPTIONAL:
6191 flag_reg_prefix_optional = 1;
6192 break;
6193
6194 /* -V: SVR4 argument to print version ID. */
6195 case 'V':
6196 print_version_id ();
6197 break;
6198
6199 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6200 should be emitted or not. FIXME: Not implemented. */
6201 case 'Q':
6202 break;
6203
6204 default:
6205 return 0;
6206 }
6207
6208 return 1;
6209 }
6210
6211 void
6212 md_show_usage (stream)
6213 FILE *stream;
6214 {
6215 fprintf(stream, "\
6216 680X0 options:\n\
6217 -l use 1 word for refs to undefined symbols [default 2]\n\
6218 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6219 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6220 | -mcpu32\n\
6221 specify variant of 680X0 architecture [default 68020]\n\
6222 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6223 target has/lacks floating-point coprocessor\n\
6224 [default yes for 68020, 68030, and cpu32]\n");
6225 fprintf(stream, "\
6226 -m68851 | -mno-68851\n\
6227 target has/lacks memory-management unit coprocessor\n\
6228 [default yes for 68020 and up]\n\
6229 -pic, -k generate position independent code\n\
6230 -S turn jbsr into jsr\n\
6231 --register-prefix-optional\n\
6232 recognize register names without prefix character\n");
6233 }
6234 \f
6235 #ifdef TEST2
6236
6237 /* TEST2: Test md_assemble() */
6238 /* Warning, this routine probably doesn't work anymore */
6239
6240 main ()
6241 {
6242 struct m68k_it the_ins;
6243 char buf[120];
6244 char *cp;
6245 int n;
6246
6247 m68k_ip_begin ();
6248 for (;;)
6249 {
6250 if (!gets (buf) || !*buf)
6251 break;
6252 if (buf[0] == '|' || buf[1] == '.')
6253 continue;
6254 for (cp = buf; *cp; cp++)
6255 if (*cp == '\t')
6256 *cp = ' ';
6257 if (is_label (buf))
6258 continue;
6259 memset (&the_ins, '\0', sizeof (the_ins));
6260 m68k_ip (&the_ins, buf);
6261 if (the_ins.error)
6262 {
6263 printf ("Error %s in %s\n", the_ins.error, buf);
6264 }
6265 else
6266 {
6267 printf ("Opcode(%d.%s): ", the_ins.numo, the_ins.args);
6268 for (n = 0; n < the_ins.numo; n++)
6269 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
6270 printf (" ");
6271 print_the_insn (&the_ins.opcode[0], stdout);
6272 (void) putchar ('\n');
6273 }
6274 for (n = 0; n < strlen (the_ins.args) / 2; n++)
6275 {
6276 if (the_ins.operands[n].error)
6277 {
6278 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
6279 continue;
6280 }
6281 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
6282 if (the_ins.operands[n].b_const)
6283 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
6284 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
6285 if (the_ins.operands[n].b_iadd)
6286 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
6287 (void) putchar ('\n');
6288 }
6289 }
6290 m68k_ip_end ();
6291 return 0;
6292 }
6293
6294 is_label (str)
6295 char *str;
6296 {
6297 while (*str == ' ')
6298 str++;
6299 while (*str && *str != ' ')
6300 str++;
6301 if (str[-1] == ':' || str[1] == '=')
6302 return 1;
6303 return 0;
6304 }
6305
6306 #endif
6307
6308 /* Possible states for relaxation:
6309
6310 0 0 branch offset byte (bra, etc)
6311 0 1 word
6312 0 2 long
6313
6314 1 0 indexed offsets byte a0@(32,d4:w:1) etc
6315 1 1 word
6316 1 2 long
6317
6318 2 0 two-offset index word-word a0@(32,d4)@(45) etc
6319 2 1 word-long
6320 2 2 long-word
6321 2 3 long-long
6322
6323 */
6324
6325 /* We have no need to default values of symbols. */
6326
6327 /* ARGSUSED */
6328 symbolS *
6329 md_undefined_symbol (name)
6330 char *name;
6331 {
6332 return 0;
6333 }
6334
6335 /* Round up a section size to the appropriate boundary. */
6336 valueT
6337 md_section_align (segment, size)
6338 segT segment;
6339 valueT size;
6340 {
6341 return size; /* Byte alignment is fine */
6342 }
6343
6344 /* Exactly what point is a PC-relative offset relative TO?
6345 On the 68k, it is relative to the address of the first extension
6346 word. The difference between the addresses of the offset and the
6347 first extension word is stored in fx_pcrel_adjust. */
6348 long
6349 md_pcrel_from (fixP)
6350 fixS *fixP;
6351 {
6352 int adjust;
6353
6354 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
6355 -1 as 64. */
6356 adjust = fixP->fx_pcrel_adjust;
6357 if (adjust == 64)
6358 adjust = -1;
6359 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
6360 }
6361
6362 #ifndef BFD_ASSEMBLER
6363 /*ARGSUSED*/
6364 void
6365 tc_coff_symbol_emit_hook (ignore)
6366 symbolS *ignore;
6367 {
6368 }
6369
6370 int
6371 tc_coff_sizemachdep (frag)
6372 fragS *frag;
6373 {
6374 switch (frag->fr_subtype & 0x3)
6375 {
6376 case BYTE:
6377 return 1;
6378 case SHORT:
6379 return 2;
6380 case LONG:
6381 return 4;
6382 default:
6383 abort ();
6384 return 0;
6385 }
6386 }
6387 #endif
6388
6389 /* end of tc-m68k.c */