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* config/tc-m68k.c (LONG_BRANCH_VIA_COND): New.
[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
21
22 #include "as.h"
23 #include "safe-ctype.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
28
29 #include "opcode/m68k.h"
30 #include "m68k-parse.h"
31
32 #if defined (OBJ_ELF)
33 #include "elf/m68k.h"
34 #endif
35
36 #ifdef M68KCOFF
37 #include "obj-coff.h"
38 #endif
39
40 /* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44 #if defined (TE_SVR4) || defined (TE_DELTA)
45 const char *m68k_comment_chars = "|#";
46 #else
47 const char *m68k_comment_chars = "|";
48 #endif
49
50 /* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53 /* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
55 #NO_APP at the beginning of its output. */
56 /* Also note that comments like this one will always work. */
57 const char line_comment_chars[] = "#*";
58
59 const char line_separator_chars[] = ";";
60
61 /* Chars that can be used to separate mant from exp in floating point nums. */
62 const char EXP_CHARS[] = "eE";
63
64 /* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
67 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
68
69 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
73 /* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
75 references. Not implemented. For ELF there are other means
76 to denote pic relocations. */
77 int flag_want_pic;
78
79 static int flag_short_refs; /* -l option. */
80 static int flag_long_jumps; /* -S option. */
81 static int flag_keep_pcrel; /* --pcrel option. */
82
83 #ifdef REGISTER_PREFIX_OPTIONAL
84 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85 #else
86 int flag_reg_prefix_optional;
87 #endif
88
89 /* Whether --register-prefix-optional was used on the command line. */
90 static int reg_prefix_optional_seen;
91
92 /* The floating point coprocessor to use by default. */
93 static enum m68k_register m68k_float_copnum = COP1;
94
95 /* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97 static int m68k_abspcadd;
98
99 /* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101 static int m68k_quick = 1;
102
103 /* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106 static int m68k_rel32 = 1;
107
108 /* This is non-zero if m68k_rel32 was set from the command line. */
109 static int m68k_rel32_from_cmdline;
110
111 /* The default width to use for an index register when using a base
112 displacement. */
113 static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115 /* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
118 struct label_line
119 {
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125 };
126
127 /* The list of labels. */
128
129 static struct label_line *labels;
130
131 /* The current label. */
132
133 static struct label_line *current_label;
134
135 /* Pointer to list holding the opcodes sorted by name. */
136 static struct m68k_opcode const ** m68k_sorted_opcodes;
137
138 /* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
140 static struct obstack robyn;
141
142 struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153 #define gettwo(x) (((x)->m_opcode)&0xffff)
154
155 static const enum m68k_register m68000_ctrl[] = { 0 };
156 static const enum m68k_register m68010_ctrl[] = {
157 SFC, DFC, USP, VBR,
158 0
159 };
160 static const enum m68k_register m68020_ctrl[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163 };
164 static const enum m68k_register m68040_ctrl[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168 };
169 static const enum m68k_register m68060_ctrl[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173 };
174 static const enum m68k_register mcf_ctrl[] = {
175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178 };
179 static const enum m68k_register mcf51qe_ctrl[] = {
180 VBR,
181 0
182 };
183 static const enum m68k_register mcf5206_ctrl[] = {
184 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
185 0
186 };
187 static const enum m68k_register mcf5208_ctrl[] = {
188 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
189 0
190 };
191 static const enum m68k_register mcf5210a_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
193 0
194 };
195 static const enum m68k_register mcf5213_ctrl[] = {
196 VBR, RAMBAR, RAMBAR1, FLASHBAR,
197 0
198 };
199 static const enum m68k_register mcf5216_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52223_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf52235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5225_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
213 0
214 };
215 static const enum m68k_register mcf5235_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
217 0
218 };
219 static const enum m68k_register mcf5249_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
221 0
222 };
223 static const enum m68k_register mcf5250_ctrl[] = {
224 VBR,
225 0
226 };
227 static const enum m68k_register mcf5253_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
229 0
230 };
231 static const enum m68k_register mcf5271_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
233 0
234 };
235 static const enum m68k_register mcf5272_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
237 0
238 };
239 static const enum m68k_register mcf5275_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5282_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
245 0
246 };
247 static const enum m68k_register mcf5307_ctrl[] = {
248 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
249 0
250 };
251 static const enum m68k_register mcf5329_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcf5373_ctrl[] = {
256 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
257 0
258 };
259 static const enum m68k_register mcfv4e_ctrl[] = {
260 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
261 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
262 MBAR, SECMBAR,
263 MPCR /* Multiprocessor Control register */,
264 EDRAMBAR /* Embedded DRAM Base Address Register */,
265 /* Permutation control registers. */
266 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
267 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
268 /* Legacy names */
269 TC /* ASID */, BUSCR /* MMUBAR */,
270 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
271 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
272 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
273 0
274 };
275 static const enum m68k_register mcf5407_ctrl[] = {
276 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
277 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
278 /* Legacy names */
279 TC /* ASID */,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
282 0
283 };
284 static const enum m68k_register mcf54455_ctrl[] = {
285 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
286 VBR, PC, RAMBAR1, MBAR,
287 /* Legacy names */
288 TC /* ASID */, BUSCR /* MMUBAR */,
289 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
291 0
292 };
293 static const enum m68k_register mcf5475_ctrl[] = {
294 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
295 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
296 /* Legacy names */
297 TC /* ASID */, BUSCR /* MMUBAR */,
298 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
299 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
300 0
301 };
302 static const enum m68k_register mcf5485_ctrl[] = {
303 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
304 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
305 /* Legacy names */
306 TC /* ASID */, BUSCR /* MMUBAR */,
307 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
308 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
309 0
310 };
311 static const enum m68k_register fido_ctrl[] = {
312 SFC, DFC, USP, VBR, CAC, MBB,
313 0
314 };
315 #define cpu32_ctrl m68010_ctrl
316
317 static const enum m68k_register *control_regs;
318
319 /* Internal form of a 68020 instruction. */
320 struct m68k_it
321 {
322 const char *error;
323 const char *args; /* List of opcode info. */
324 int numargs;
325
326 int numo; /* Number of shorts in opcode. */
327 short opcode[11];
328
329 struct m68k_op operands[6];
330
331 int nexp; /* Number of exprs in use. */
332 struct m68k_exp exprs[4];
333
334 int nfrag; /* Number of frags we have to produce. */
335 struct
336 {
337 int fragoff; /* Where in the current opcode the frag ends. */
338 symbolS *fadd;
339 offsetT foff;
340 int fragty;
341 }
342 fragb[4];
343
344 int nrel; /* Num of reloc strucs in use. */
345 struct
346 {
347 int n;
348 expressionS exp;
349 char wid;
350 char pcrel;
351 /* In a pc relative address the difference between the address
352 of the offset and the address that the offset is relative
353 to. This depends on the addressing mode. Basically this
354 is the value to put in the offset field to address the
355 first byte of the offset, without regarding the special
356 significance of some values (in the branch instruction, for
357 example). */
358 int pcrel_fix;
359 #ifdef OBJ_ELF
360 /* Whether this expression needs special pic relocation, and if
361 so, which. */
362 enum pic_relocation pic_reloc;
363 #endif
364 }
365 reloc[5]; /* Five is enough??? */
366 };
367
368 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
369 #define float_of_arch(x) ((x) & mfloat)
370 #define mmu_of_arch(x) ((x) & mmmu)
371 #define arch_coldfire_p(x) ((x) & mcfisa_a)
372 #define arch_coldfire_fpu(x) ((x) & cfloat)
373
374 /* Macros for determining if cpu supports a specific addressing mode. */
375 #define HAVE_LONG_DISP(x) \
376 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
377 #define HAVE_LONG_CALL(x) \
378 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
379 #define HAVE_LONG_COND(x) \
380 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
381 #define HAVE_LONG_BRANCH(x) \
382 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
383 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
384
385 static struct m68k_it the_ins; /* The instruction being assembled. */
386
387 #define op(ex) ((ex)->exp.X_op)
388 #define adds(ex) ((ex)->exp.X_add_symbol)
389 #define subs(ex) ((ex)->exp.X_op_symbol)
390 #define offs(ex) ((ex)->exp.X_add_number)
391
392 /* Macros for adding things to the m68k_it struct. */
393 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
394
395 /* Like addword, but goes BEFORE general operands. */
396
397 static void
398 insop (int w, const struct m68k_incant *opcode)
399 {
400 int z;
401 for (z = the_ins.numo; z > opcode->m_codenum; --z)
402 the_ins.opcode[z] = the_ins.opcode[z - 1];
403 for (z = 0; z < the_ins.nrel; z++)
404 the_ins.reloc[z].n += 2;
405 for (z = 0; z < the_ins.nfrag; z++)
406 the_ins.fragb[z].fragoff++;
407 the_ins.opcode[opcode->m_codenum] = w;
408 the_ins.numo++;
409 }
410
411 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
412 Blecch. */
413 static void
414 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
415 {
416 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
417 ? the_ins.numo * 2 - 1
418 : (width == 'b'
419 ? the_ins.numo * 2 + 1
420 : the_ins.numo * 2));
421 the_ins.reloc[the_ins.nrel].exp = exp->exp;
422 the_ins.reloc[the_ins.nrel].wid = width;
423 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
424 #ifdef OBJ_ELF
425 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
426 #endif
427 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
428 }
429
430 /* Cause an extra frag to be generated here, inserting up to 10 bytes
431 (that value is chosen in the frag_var call in md_assemble). TYPE
432 is the subtype of the frag to be generated; its primary type is
433 rs_machine_dependent.
434
435 The TYPE parameter is also used by md_convert_frag_1 and
436 md_estimate_size_before_relax. The appropriate type of fixup will
437 be emitted by md_convert_frag_1.
438
439 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
440 static void
441 add_frag (symbolS *add, offsetT off, int type)
442 {
443 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
444 the_ins.fragb[the_ins.nfrag].fadd = add;
445 the_ins.fragb[the_ins.nfrag].foff = off;
446 the_ins.fragb[the_ins.nfrag++].fragty = type;
447 }
448
449 #define isvar(ex) \
450 (op (ex) != O_constant && op (ex) != O_big)
451
452 static char *crack_operand (char *str, struct m68k_op *opP);
453 static int get_num (struct m68k_exp *exp, int ok);
454 static int reverse_16_bits (int in);
455 static int reverse_8_bits (int in);
456 static void install_gen_operand (int mode, int val);
457 static void install_operand (int mode, int val);
458 static void s_bss (int);
459 static void s_data1 (int);
460 static void s_data2 (int);
461 static void s_even (int);
462 static void s_proc (int);
463 static void s_chip (int);
464 static void s_fopt (int);
465 static void s_opt (int);
466 static void s_reg (int);
467 static void s_restore (int);
468 static void s_save (int);
469 static void s_mri_if (int);
470 static void s_mri_else (int);
471 static void s_mri_endi (int);
472 static void s_mri_break (int);
473 static void s_mri_next (int);
474 static void s_mri_for (int);
475 static void s_mri_endf (int);
476 static void s_mri_repeat (int);
477 static void s_mri_until (int);
478 static void s_mri_while (int);
479 static void s_mri_endw (int);
480 static void s_m68k_cpu (int);
481 static void s_m68k_arch (int);
482
483 struct m68k_cpu
484 {
485 unsigned long arch; /* Architecture features. */
486 const enum m68k_register *control_regs; /* Control regs on chip */
487 const char *name; /* Name */
488 int alias; /* Alias for a cannonical name. If 1, then
489 succeeds canonical name, if -1 then
490 succeeds canonical name, if <-1 ||>1 this is a
491 deprecated name, and the next/previous name
492 should be used. */
493 };
494
495 /* We hold flags for features explicitly enabled and explicitly
496 disabled. */
497 static int current_architecture;
498 static int not_current_architecture;
499 static const struct m68k_cpu *selected_arch;
500 static const struct m68k_cpu *selected_cpu;
501 static int initialized;
502
503 /* Architecture models. */
504 static const struct m68k_cpu m68k_archs[] =
505 {
506 {m68000, m68000_ctrl, "68000", 0},
507 {m68010, m68010_ctrl, "68010", 0},
508 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
509 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
510 {m68040, m68040_ctrl, "68040", 0},
511 {m68060, m68060_ctrl, "68060", 0},
512 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
513 {fido_a, fido_ctrl, "fidoa", 0},
514 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
515 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
516 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
517 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
519 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
520 {0,0,NULL, 0}
521 };
522
523 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
524 for either. */
525 static const struct m68k_cpu m68k_extensions[] =
526 {
527 {m68851, NULL, "68851", -1},
528 {m68881, NULL, "68881", -1},
529 {m68881, NULL, "68882", -1},
530
531 {cfloat|m68881, NULL, "float", 0},
532
533 {mcfhwdiv, NULL, "div", 1},
534 {mcfusp, NULL, "usp", 1},
535 {mcfmac, NULL, "mac", 1},
536 {mcfemac, NULL, "emac", 1},
537
538 {0,NULL,NULL, 0}
539 };
540
541 /* Processor list */
542 static const struct m68k_cpu m68k_cpus[] =
543 {
544 {m68000, m68000_ctrl, "68000", 0},
545 {m68000, m68000_ctrl, "68ec000", 1},
546 {m68000, m68000_ctrl, "68hc000", 1},
547 {m68000, m68000_ctrl, "68hc001", 1},
548 {m68000, m68000_ctrl, "68008", 1},
549 {m68000, m68000_ctrl, "68302", 1},
550 {m68000, m68000_ctrl, "68306", 1},
551 {m68000, m68000_ctrl, "68307", 1},
552 {m68000, m68000_ctrl, "68322", 1},
553 {m68000, m68000_ctrl, "68356", 1},
554 {m68010, m68010_ctrl, "68010", 0},
555 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
556 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
557 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
558 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
559 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
560 {m68040, m68040_ctrl, "68040", 0},
561 {m68040, m68040_ctrl, "68ec040", 1},
562 {m68060, m68060_ctrl, "68060", 0},
563 {m68060, m68060_ctrl, "68ec060", 1},
564
565 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
566 {cpu32|m68881, cpu32_ctrl, "68330", 1},
567 {cpu32|m68881, cpu32_ctrl, "68331", 1},
568 {cpu32|m68881, cpu32_ctrl, "68332", 1},
569 {cpu32|m68881, cpu32_ctrl, "68333", 1},
570 {cpu32|m68881, cpu32_ctrl, "68334", 1},
571 {cpu32|m68881, cpu32_ctrl, "68336", 1},
572 {cpu32|m68881, cpu32_ctrl, "68340", 1},
573 {cpu32|m68881, cpu32_ctrl, "68341", 1},
574 {cpu32|m68881, cpu32_ctrl, "68349", 1},
575 {cpu32|m68881, cpu32_ctrl, "68360", 1},
576
577 {mcfisa_a|mcfisa_c|mcfusp, mcf51qe_ctrl, "51qe", 0},
578
579 {mcfisa_a, mcf_ctrl, "5200", 0},
580 {mcfisa_a, mcf_ctrl, "5202", 1},
581 {mcfisa_a, mcf_ctrl, "5204", 1},
582 {mcfisa_a, mcf5206_ctrl, "5206", 1},
583
584 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
585
586 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
588
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
591
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
594 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
595
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
599
600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
602
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
607
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
609 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
610
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
616
617 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
618 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
619 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
620
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
623
624 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
625
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
628
629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
633
634 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
635
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
638 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
640
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
644
645 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
646
647 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
648 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
649 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
650 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
651 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
652 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
653
654 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
655 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
656 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
657 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
658 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
659 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
660 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
661
662 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
663 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
664 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
665 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
666 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
667 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
668 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
669
670 {fido_a, fido_ctrl, "fidoa", 0},
671 {fido_a, fido_ctrl, "fido", 1},
672
673 {0,NULL,NULL, 0}
674 };
675
676 static const struct m68k_cpu *m68k_lookup_cpu
677 (const char *, const struct m68k_cpu *, int, int *);
678 static int m68k_set_arch (const char *, int, int);
679 static int m68k_set_cpu (const char *, int, int);
680 static int m68k_set_extension (const char *, int, int);
681 static void m68k_init_arch (void);
682
683 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
684 architecture and we have a lot of relaxation modes. */
685
686 /* Macros used in the relaxation code. */
687 #define TAB(x,y) (((x) << 2) + (y))
688 #define TABTYPE(x) ((x) >> 2)
689
690 /* Relaxation states. */
691 #define BYTE 0
692 #define SHORT 1
693 #define LONG 2
694 #define SZ_UNDEF 3
695
696 /* Here are all the relaxation modes we support. First we can relax ordinary
697 branches. On 68020 and higher and on CPU32 all branch instructions take
698 three forms, so on these CPUs all branches always remain as such. When we
699 have to expand to the LONG form on a 68000, though, we substitute an
700 absolute jump instead. This is a direct replacement for unconditional
701 branches and a branch over a jump for conditional branches. However, if the
702 user requires PIC and disables this with --pcrel, we can only relax between
703 BYTE and SHORT forms, punting if that isn't enough. This gives us four
704 different relaxation modes for branches: */
705
706 #define BRANCHBWL 0 /* Branch byte, word, or long. */
707 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
708 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
709 #define BRANCHBW 3 /* Branch byte or word. */
710
711 /* We also relax coprocessor branches and DBcc's. All CPUs that support
712 coprocessor branches support them in word and long forms, so we have only
713 one relaxation mode for them. DBcc's are word only on all CPUs. We can
714 relax them to the LONG form with a branch-around sequence. This sequence
715 can use a long branch (if available) or an absolute jump (if acceptable).
716 This gives us two relaxation modes. If long branches are not available and
717 absolute jumps are not acceptable, we don't relax DBcc's. */
718
719 #define FBRANCH 4 /* Coprocessor branch. */
720 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
721 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
722
723 /* That's all for instruction relaxation. However, we also relax PC-relative
724 operands. Specifically, we have three operand relaxation modes. On the
725 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
726 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
727 two. Also PC+displacement+index operands in their simple form (with a non-
728 suppressed index without memory indirection) are supported on all CPUs, but
729 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
730 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
731 form of the PC+displacement+index operand. Finally, some absolute operands
732 can be relaxed down to 16-bit PC-relative. */
733
734 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
735 #define PCINDEX 8 /* PC + displacement + index. */
736 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
737
738 /* This relaxation is required for branches where there is no long
739 branch and we are in pcrel mode. We generate a bne/beq pair. */
740 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
741 */
742
743 /* Note that calls to frag_var need to specify the maximum expansion
744 needed; this is currently 12 bytes for bne/beq pair. */
745 #define FRAG_VAR_SIZE 12
746
747 /* The fields are:
748 How far Forward this mode will reach:
749 How far Backward this mode will reach:
750 How many bytes this mode will add to the size of the frag
751 Which mode to go to if the offset won't fit in this one
752
753 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
754 relax_typeS md_relax_table[] =
755 {
756 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
757 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
758 { 0, 0, 4, 0 },
759 { 1, 1, 0, 0 },
760
761 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
762 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
763 { 0, 0, 4, 0 },
764 { 1, 1, 0, 0 },
765
766 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
767 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
768 { 0, 0, 6, 0 },
769 { 1, 1, 0, 0 },
770
771 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
772 { 0, 0, 2, 0 },
773 { 1, 1, 0, 0 },
774 { 1, 1, 0, 0 },
775
776 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
777 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
778 { 0, 0, 4, 0 },
779 { 1, 1, 0, 0 },
780
781 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
782 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
783 { 0, 0, 10, 0 },
784 { 1, 1, 0, 0 },
785
786 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
787 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
788 { 0, 0, 10, 0 },
789 { 1, 1, 0, 0 },
790
791 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
792 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
793 { 0, 0, 6, 0 },
794 { 1, 1, 0, 0 },
795
796 { 125, -130, 0, TAB (PCINDEX, SHORT) },
797 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
798 { 0, 0, 4, 0 },
799 { 1, 1, 0, 0 },
800
801 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
802 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
803 { 0, 0, 4, 0 },
804 { 1, 1, 0, 0 },
805
806 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
807 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
808 { 0, 0, 10, 0 },
809 { 1, 1, 0, 0 },
810 };
811
812 /* These are the machine dependent pseudo-ops. These are included so
813 the assembler can work on the output from the SUN C compiler, which
814 generates these. */
815
816 /* This table describes all the machine specific pseudo-ops the assembler
817 has to support. The fields are:
818 pseudo-op name without dot
819 function to call to execute this pseudo-op
820 Integer arg to pass to the function. */
821 const pseudo_typeS md_pseudo_table[] =
822 {
823 {"data1", s_data1, 0},
824 {"data2", s_data2, 0},
825 {"bss", s_bss, 0},
826 {"even", s_even, 0},
827 {"skip", s_space, 0},
828 {"proc", s_proc, 0},
829 #if defined (TE_SUN3) || defined (OBJ_ELF)
830 {"align", s_align_bytes, 0},
831 #endif
832 #ifdef OBJ_ELF
833 {"swbeg", s_ignore, 0},
834 #endif
835 {"extend", float_cons, 'x'},
836 {"ldouble", float_cons, 'x'},
837
838 {"arch", s_m68k_arch, 0},
839 {"cpu", s_m68k_cpu, 0},
840
841 /* The following pseudo-ops are supported for MRI compatibility. */
842 {"chip", s_chip, 0},
843 {"comline", s_space, 1},
844 {"fopt", s_fopt, 0},
845 {"mask2", s_ignore, 0},
846 {"opt", s_opt, 0},
847 {"reg", s_reg, 0},
848 {"restore", s_restore, 0},
849 {"save", s_save, 0},
850
851 {"if", s_mri_if, 0},
852 {"if.b", s_mri_if, 'b'},
853 {"if.w", s_mri_if, 'w'},
854 {"if.l", s_mri_if, 'l'},
855 {"else", s_mri_else, 0},
856 {"else.s", s_mri_else, 's'},
857 {"else.l", s_mri_else, 'l'},
858 {"endi", s_mri_endi, 0},
859 {"break", s_mri_break, 0},
860 {"break.s", s_mri_break, 's'},
861 {"break.l", s_mri_break, 'l'},
862 {"next", s_mri_next, 0},
863 {"next.s", s_mri_next, 's'},
864 {"next.l", s_mri_next, 'l'},
865 {"for", s_mri_for, 0},
866 {"for.b", s_mri_for, 'b'},
867 {"for.w", s_mri_for, 'w'},
868 {"for.l", s_mri_for, 'l'},
869 {"endf", s_mri_endf, 0},
870 {"repeat", s_mri_repeat, 0},
871 {"until", s_mri_until, 0},
872 {"until.b", s_mri_until, 'b'},
873 {"until.w", s_mri_until, 'w'},
874 {"until.l", s_mri_until, 'l'},
875 {"while", s_mri_while, 0},
876 {"while.b", s_mri_while, 'b'},
877 {"while.w", s_mri_while, 'w'},
878 {"while.l", s_mri_while, 'l'},
879 {"endw", s_mri_endw, 0},
880
881 {0, 0, 0}
882 };
883
884 /* The mote pseudo ops are put into the opcode table, since they
885 don't start with a . they look like opcodes to gas. */
886
887 const pseudo_typeS mote_pseudo_table[] =
888 {
889
890 {"dcl", cons, 4},
891 {"dc", cons, 2},
892 {"dcw", cons, 2},
893 {"dcb", cons, 1},
894
895 {"dsl", s_space, 4},
896 {"ds", s_space, 2},
897 {"dsw", s_space, 2},
898 {"dsb", s_space, 1},
899
900 {"xdef", s_globl, 0},
901 #ifdef OBJ_ELF
902 {"align", s_align_bytes, 0},
903 #else
904 {"align", s_align_ptwo, 0},
905 #endif
906 #ifdef M68KCOFF
907 {"sect", obj_coff_section, 0},
908 {"section", obj_coff_section, 0},
909 #endif
910 {0, 0, 0}
911 };
912
913 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
914 gives identical results to a 32-bit host. */
915 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
916 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
917
918 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
919 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
920 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
921 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
922
923 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
924 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
925 #define islong(x) (1)
926
927 static char notend_table[256];
928 static char alt_notend_table[256];
929 #define notend(s) \
930 (! (notend_table[(unsigned char) *s] \
931 || (*s == ':' \
932 && alt_notend_table[(unsigned char) s[1]])))
933
934 #ifdef OBJ_ELF
935
936 /* Return zero if the reference to SYMBOL from within the same segment may
937 be relaxed. */
938
939 /* On an ELF system, we can't relax an externally visible symbol,
940 because it may be overridden by a shared library. However, if
941 TARGET_OS is "elf", then we presume that we are assembling for an
942 embedded system, in which case we don't have to worry about shared
943 libraries, and we can relax any external sym. */
944
945 #define relaxable_symbol(symbol) \
946 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
947 || S_IS_WEAK (symbol)))
948
949 /* Compute the relocation code for a fixup of SIZE bytes, using pc
950 relative relocation if PCREL is non-zero. PIC says whether a special
951 pic relocation was requested. */
952
953 static bfd_reloc_code_real_type
954 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
955 {
956 switch (pic)
957 {
958 case pic_got_pcrel:
959 switch (size)
960 {
961 case 1:
962 return BFD_RELOC_8_GOT_PCREL;
963 case 2:
964 return BFD_RELOC_16_GOT_PCREL;
965 case 4:
966 return BFD_RELOC_32_GOT_PCREL;
967 }
968 break;
969
970 case pic_got_off:
971 switch (size)
972 {
973 case 1:
974 return BFD_RELOC_8_GOTOFF;
975 case 2:
976 return BFD_RELOC_16_GOTOFF;
977 case 4:
978 return BFD_RELOC_32_GOTOFF;
979 }
980 break;
981
982 case pic_plt_pcrel:
983 switch (size)
984 {
985 case 1:
986 return BFD_RELOC_8_PLT_PCREL;
987 case 2:
988 return BFD_RELOC_16_PLT_PCREL;
989 case 4:
990 return BFD_RELOC_32_PLT_PCREL;
991 }
992 break;
993
994 case pic_plt_off:
995 switch (size)
996 {
997 case 1:
998 return BFD_RELOC_8_PLTOFF;
999 case 2:
1000 return BFD_RELOC_16_PLTOFF;
1001 case 4:
1002 return BFD_RELOC_32_PLTOFF;
1003 }
1004 break;
1005
1006 case pic_none:
1007 if (pcrel)
1008 {
1009 switch (size)
1010 {
1011 case 1:
1012 return BFD_RELOC_8_PCREL;
1013 case 2:
1014 return BFD_RELOC_16_PCREL;
1015 case 4:
1016 return BFD_RELOC_32_PCREL;
1017 }
1018 }
1019 else
1020 {
1021 switch (size)
1022 {
1023 case 1:
1024 return BFD_RELOC_8;
1025 case 2:
1026 return BFD_RELOC_16;
1027 case 4:
1028 return BFD_RELOC_32;
1029 }
1030 }
1031 }
1032
1033 if (pcrel)
1034 {
1035 if (pic == pic_none)
1036 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1037 else
1038 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1039 }
1040 else
1041 {
1042 if (pic == pic_none)
1043 as_bad (_("Can not do %d byte relocation"), size);
1044 else
1045 as_bad (_("Can not do %d byte pic relocation"), size);
1046 }
1047
1048 return BFD_RELOC_NONE;
1049 }
1050
1051 /* Here we decide which fixups can be adjusted to make them relative
1052 to the beginning of the section instead of the symbol. Basically
1053 we need to make sure that the dynamic relocations are done
1054 correctly, so in some cases we force the original symbol to be
1055 used. */
1056 int
1057 tc_m68k_fix_adjustable (fixS *fixP)
1058 {
1059 /* Adjust_reloc_syms doesn't know about the GOT. */
1060 switch (fixP->fx_r_type)
1061 {
1062 case BFD_RELOC_8_GOT_PCREL:
1063 case BFD_RELOC_16_GOT_PCREL:
1064 case BFD_RELOC_32_GOT_PCREL:
1065 case BFD_RELOC_8_GOTOFF:
1066 case BFD_RELOC_16_GOTOFF:
1067 case BFD_RELOC_32_GOTOFF:
1068 case BFD_RELOC_8_PLT_PCREL:
1069 case BFD_RELOC_16_PLT_PCREL:
1070 case BFD_RELOC_32_PLT_PCREL:
1071 case BFD_RELOC_8_PLTOFF:
1072 case BFD_RELOC_16_PLTOFF:
1073 case BFD_RELOC_32_PLTOFF:
1074 return 0;
1075
1076 case BFD_RELOC_VTABLE_INHERIT:
1077 case BFD_RELOC_VTABLE_ENTRY:
1078 return 0;
1079
1080 default:
1081 return 1;
1082 }
1083 }
1084
1085 #else /* !OBJ_ELF */
1086
1087 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1088
1089 /* PR gas/3041 Weak symbols are not relaxable
1090 because they must be treated as extern. */
1091 #define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
1092
1093 #endif /* OBJ_ELF */
1094
1095 arelent *
1096 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1097 {
1098 arelent *reloc;
1099 bfd_reloc_code_real_type code;
1100
1101 /* If the tcbit is set, then this was a fixup of a negative value
1102 that was never resolved. We do not have a reloc to handle this,
1103 so just return. We assume that other code will have detected this
1104 situation and produced a helpful error message, so we just tell the
1105 user that the reloc cannot be produced. */
1106 if (fixp->fx_tcbit)
1107 {
1108 if (fixp->fx_addsy)
1109 as_bad_where (fixp->fx_file, fixp->fx_line,
1110 _("Unable to produce reloc against symbol '%s'"),
1111 S_GET_NAME (fixp->fx_addsy));
1112 return NULL;
1113 }
1114
1115 if (fixp->fx_r_type != BFD_RELOC_NONE)
1116 {
1117 code = fixp->fx_r_type;
1118
1119 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1120 that fixup_segment converted a non-PC relative reloc into a
1121 PC relative reloc. In such a case, we need to convert the
1122 reloc code. */
1123 if (fixp->fx_pcrel)
1124 {
1125 switch (code)
1126 {
1127 case BFD_RELOC_8:
1128 code = BFD_RELOC_8_PCREL;
1129 break;
1130 case BFD_RELOC_16:
1131 code = BFD_RELOC_16_PCREL;
1132 break;
1133 case BFD_RELOC_32:
1134 code = BFD_RELOC_32_PCREL;
1135 break;
1136 case BFD_RELOC_8_PCREL:
1137 case BFD_RELOC_16_PCREL:
1138 case BFD_RELOC_32_PCREL:
1139 case BFD_RELOC_8_GOT_PCREL:
1140 case BFD_RELOC_16_GOT_PCREL:
1141 case BFD_RELOC_32_GOT_PCREL:
1142 case BFD_RELOC_8_GOTOFF:
1143 case BFD_RELOC_16_GOTOFF:
1144 case BFD_RELOC_32_GOTOFF:
1145 case BFD_RELOC_8_PLT_PCREL:
1146 case BFD_RELOC_16_PLT_PCREL:
1147 case BFD_RELOC_32_PLT_PCREL:
1148 case BFD_RELOC_8_PLTOFF:
1149 case BFD_RELOC_16_PLTOFF:
1150 case BFD_RELOC_32_PLTOFF:
1151 break;
1152 default:
1153 as_bad_where (fixp->fx_file, fixp->fx_line,
1154 _("Cannot make %s relocation PC relative"),
1155 bfd_get_reloc_code_name (code));
1156 }
1157 }
1158 }
1159 else
1160 {
1161 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1162 switch (F (fixp->fx_size, fixp->fx_pcrel))
1163 {
1164 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1165 MAP (1, 0, BFD_RELOC_8);
1166 MAP (2, 0, BFD_RELOC_16);
1167 MAP (4, 0, BFD_RELOC_32);
1168 MAP (1, 1, BFD_RELOC_8_PCREL);
1169 MAP (2, 1, BFD_RELOC_16_PCREL);
1170 MAP (4, 1, BFD_RELOC_32_PCREL);
1171 default:
1172 abort ();
1173 }
1174 }
1175 #undef F
1176 #undef MAP
1177
1178 reloc = (arelent *) xmalloc (sizeof (arelent));
1179 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1180 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1181 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1182 #ifndef OBJ_ELF
1183 if (fixp->fx_pcrel)
1184 reloc->addend = fixp->fx_addnumber;
1185 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1186 && fixp->fx_addsy
1187 && S_IS_WEAK (fixp->fx_addsy)
1188 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1189 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1190 to put the symbol offset into frags referencing a weak symbol. */
1191 reloc->addend = fixp->fx_addnumber
1192 - (S_GET_VALUE (fixp->fx_addsy) * 2);
1193 else
1194 reloc->addend = 0;
1195 #else
1196 if (!fixp->fx_pcrel)
1197 reloc->addend = fixp->fx_addnumber;
1198 else
1199 reloc->addend = (section->vma
1200 /* Explicit sign extension in case char is
1201 unsigned. */
1202 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
1203 + fixp->fx_addnumber
1204 + md_pcrel_from (fixp));
1205 #endif
1206
1207 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1208 assert (reloc->howto != 0);
1209
1210 return reloc;
1211 }
1212
1213 /* Handle of the OPCODE hash table. NULL means any use before
1214 m68k_ip_begin() will crash. */
1215 static struct hash_control *op_hash;
1216 \f
1217 /* Assemble an m68k instruction. */
1218
1219 static void
1220 m68k_ip (char *instring)
1221 {
1222 register char *p;
1223 register struct m68k_op *opP;
1224 register const struct m68k_incant *opcode;
1225 register const char *s;
1226 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1227 char *pdot, *pdotmove;
1228 enum m68k_size siz1, siz2;
1229 char c;
1230 int losing;
1231 int opsfound;
1232 struct m68k_op operands_backup[6];
1233 LITTLENUM_TYPE words[6];
1234 LITTLENUM_TYPE *wordp;
1235 unsigned long ok_arch = 0;
1236
1237 if (*instring == ' ')
1238 instring++; /* Skip leading whitespace. */
1239
1240 /* Scan up to end of operation-code, which MUST end in end-of-string
1241 or exactly 1 space. */
1242 pdot = 0;
1243 for (p = instring; *p != '\0'; p++)
1244 {
1245 if (*p == ' ')
1246 break;
1247 if (*p == '.')
1248 pdot = p;
1249 }
1250
1251 if (p == instring)
1252 {
1253 the_ins.error = _("No operator");
1254 return;
1255 }
1256
1257 /* p now points to the end of the opcode name, probably whitespace.
1258 Make sure the name is null terminated by clobbering the
1259 whitespace, look it up in the hash table, then fix it back.
1260 Remove a dot, first, since the opcode tables have none. */
1261 if (pdot != NULL)
1262 {
1263 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1264 *pdotmove = pdotmove[1];
1265 p--;
1266 }
1267
1268 c = *p;
1269 *p = '\0';
1270 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1271 *p = c;
1272
1273 if (pdot != NULL)
1274 {
1275 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1276 *pdotmove = pdotmove[-1];
1277 *pdot = '.';
1278 ++p;
1279 }
1280
1281 if (opcode == NULL)
1282 {
1283 the_ins.error = _("Unknown operator");
1284 return;
1285 }
1286
1287 /* Found a legitimate opcode, start matching operands. */
1288 while (*p == ' ')
1289 ++p;
1290
1291 if (opcode->m_operands == 0)
1292 {
1293 char *old = input_line_pointer;
1294 *old = '\n';
1295 input_line_pointer = p;
1296 /* Ahh - it's a motorola style psuedo op. */
1297 mote_pseudo_table[opcode->m_opnum].poc_handler
1298 (mote_pseudo_table[opcode->m_opnum].poc_val);
1299 input_line_pointer = old;
1300 *old = 0;
1301
1302 return;
1303 }
1304
1305 if (flag_mri && opcode->m_opnum == 0)
1306 {
1307 /* In MRI mode, random garbage is allowed after an instruction
1308 which accepts no operands. */
1309 the_ins.args = opcode->m_operands;
1310 the_ins.numargs = opcode->m_opnum;
1311 the_ins.numo = opcode->m_codenum;
1312 the_ins.opcode[0] = getone (opcode);
1313 the_ins.opcode[1] = gettwo (opcode);
1314 return;
1315 }
1316
1317 for (opP = &the_ins.operands[0]; *p; opP++)
1318 {
1319 p = crack_operand (p, opP);
1320
1321 if (opP->error)
1322 {
1323 the_ins.error = opP->error;
1324 return;
1325 }
1326 }
1327
1328 opsfound = opP - &the_ins.operands[0];
1329
1330 /* This ugly hack is to support the floating pt opcodes in their
1331 standard form. Essentially, we fake a first enty of type COP#1 */
1332 if (opcode->m_operands[0] == 'I')
1333 {
1334 int n;
1335
1336 for (n = opsfound; n > 0; --n)
1337 the_ins.operands[n] = the_ins.operands[n - 1];
1338
1339 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1340 the_ins.operands[0].mode = CONTROL;
1341 the_ins.operands[0].reg = m68k_float_copnum;
1342 opsfound++;
1343 }
1344
1345 /* We've got the operands. Find an opcode that'll accept them. */
1346 for (losing = 0;;)
1347 {
1348 /* If we didn't get the right number of ops, or we have no
1349 common model with this pattern then reject this pattern. */
1350
1351 ok_arch |= opcode->m_arch;
1352 if (opsfound != opcode->m_opnum
1353 || ((opcode->m_arch & current_architecture) == 0))
1354 ++losing;
1355 else
1356 {
1357 int i;
1358
1359 /* Make a copy of the operands of this insn so that
1360 we can modify them safely, should we want to. */
1361 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1362 for (i = 0; i < opsfound; i++)
1363 operands_backup[i] = the_ins.operands[i];
1364
1365 for (s = opcode->m_operands, opP = &operands_backup[0];
1366 *s && !losing;
1367 s += 2, opP++)
1368 {
1369 /* Warning: this switch is huge! */
1370 /* I've tried to organize the cases into this order:
1371 non-alpha first, then alpha by letter. Lower-case
1372 goes directly before uppercase counterpart. */
1373 /* Code with multiple case ...: gets sorted by the lowest
1374 case ... it belongs to. I hope this makes sense. */
1375 switch (*s)
1376 {
1377 case '!':
1378 switch (opP->mode)
1379 {
1380 case IMMED:
1381 case DREG:
1382 case AREG:
1383 case FPREG:
1384 case CONTROL:
1385 case AINC:
1386 case ADEC:
1387 case REGLST:
1388 losing++;
1389 break;
1390 default:
1391 break;
1392 }
1393 break;
1394
1395 case '<':
1396 switch (opP->mode)
1397 {
1398 case DREG:
1399 case AREG:
1400 case FPREG:
1401 case CONTROL:
1402 case IMMED:
1403 case ADEC:
1404 case REGLST:
1405 losing++;
1406 break;
1407 default:
1408 break;
1409 }
1410 break;
1411
1412 case '>':
1413 switch (opP->mode)
1414 {
1415 case DREG:
1416 case AREG:
1417 case FPREG:
1418 case CONTROL:
1419 case IMMED:
1420 case AINC:
1421 case REGLST:
1422 losing++;
1423 break;
1424 case ABSL:
1425 break;
1426 default:
1427 if (opP->reg == PC
1428 || opP->reg == ZPC)
1429 losing++;
1430 break;
1431 }
1432 break;
1433
1434 case 'm':
1435 switch (opP->mode)
1436 {
1437 case DREG:
1438 case AREG:
1439 case AINDR:
1440 case AINC:
1441 case ADEC:
1442 break;
1443 default:
1444 losing++;
1445 }
1446 break;
1447
1448 case 'n':
1449 switch (opP->mode)
1450 {
1451 case DISP:
1452 break;
1453 default:
1454 losing++;
1455 }
1456 break;
1457
1458 case 'o':
1459 switch (opP->mode)
1460 {
1461 case BASE:
1462 case ABSL:
1463 case IMMED:
1464 break;
1465 default:
1466 losing++;
1467 }
1468 break;
1469
1470 case 'p':
1471 switch (opP->mode)
1472 {
1473 case DREG:
1474 case AREG:
1475 case AINDR:
1476 case AINC:
1477 case ADEC:
1478 break;
1479 case DISP:
1480 if (opP->reg == PC || opP->reg == ZPC)
1481 losing++;
1482 break;
1483 default:
1484 losing++;
1485 }
1486 break;
1487
1488 case 'q':
1489 switch (opP->mode)
1490 {
1491 case DREG:
1492 case AINDR:
1493 case AINC:
1494 case ADEC:
1495 break;
1496 case DISP:
1497 if (opP->reg == PC || opP->reg == ZPC)
1498 losing++;
1499 break;
1500 default:
1501 losing++;
1502 break;
1503 }
1504 break;
1505
1506 case 'v':
1507 switch (opP->mode)
1508 {
1509 case DREG:
1510 case AINDR:
1511 case AINC:
1512 case ADEC:
1513 case ABSL:
1514 break;
1515 case DISP:
1516 if (opP->reg == PC || opP->reg == ZPC)
1517 losing++;
1518 break;
1519 default:
1520 losing++;
1521 break;
1522 }
1523 break;
1524
1525 case '#':
1526 if (opP->mode != IMMED)
1527 losing++;
1528 else if (s[1] == 'b'
1529 && ! isvar (&opP->disp)
1530 && (opP->disp.exp.X_op != O_constant
1531 || ! isbyte (opP->disp.exp.X_add_number)))
1532 losing++;
1533 else if (s[1] == 'B'
1534 && ! isvar (&opP->disp)
1535 && (opP->disp.exp.X_op != O_constant
1536 || ! issbyte (opP->disp.exp.X_add_number)))
1537 losing++;
1538 else if (s[1] == 'w'
1539 && ! isvar (&opP->disp)
1540 && (opP->disp.exp.X_op != O_constant
1541 || ! isword (opP->disp.exp.X_add_number)))
1542 losing++;
1543 else if (s[1] == 'W'
1544 && ! isvar (&opP->disp)
1545 && (opP->disp.exp.X_op != O_constant
1546 || ! issword (opP->disp.exp.X_add_number)))
1547 losing++;
1548 break;
1549
1550 case '^':
1551 case 'T':
1552 if (opP->mode != IMMED)
1553 losing++;
1554 break;
1555
1556 case '$':
1557 if (opP->mode == AREG
1558 || opP->mode == CONTROL
1559 || opP->mode == FPREG
1560 || opP->mode == IMMED
1561 || opP->mode == REGLST
1562 || (opP->mode != ABSL
1563 && (opP->reg == PC
1564 || opP->reg == ZPC)))
1565 losing++;
1566 break;
1567
1568 case '%':
1569 if (opP->mode == CONTROL
1570 || opP->mode == FPREG
1571 || opP->mode == REGLST
1572 || opP->mode == IMMED
1573 || (opP->mode != ABSL
1574 && (opP->reg == PC
1575 || opP->reg == ZPC)))
1576 losing++;
1577 break;
1578
1579 case '&':
1580 switch (opP->mode)
1581 {
1582 case DREG:
1583 case AREG:
1584 case FPREG:
1585 case CONTROL:
1586 case IMMED:
1587 case AINC:
1588 case ADEC:
1589 case REGLST:
1590 losing++;
1591 break;
1592 case ABSL:
1593 break;
1594 default:
1595 if (opP->reg == PC
1596 || opP->reg == ZPC)
1597 losing++;
1598 break;
1599 }
1600 break;
1601
1602 case '*':
1603 if (opP->mode == CONTROL
1604 || opP->mode == FPREG
1605 || opP->mode == REGLST)
1606 losing++;
1607 break;
1608
1609 case '+':
1610 if (opP->mode != AINC)
1611 losing++;
1612 break;
1613
1614 case '-':
1615 if (opP->mode != ADEC)
1616 losing++;
1617 break;
1618
1619 case '/':
1620 switch (opP->mode)
1621 {
1622 case AREG:
1623 case CONTROL:
1624 case FPREG:
1625 case AINC:
1626 case ADEC:
1627 case IMMED:
1628 case REGLST:
1629 losing++;
1630 break;
1631 default:
1632 break;
1633 }
1634 break;
1635
1636 case ';':
1637 switch (opP->mode)
1638 {
1639 case AREG:
1640 case CONTROL:
1641 case FPREG:
1642 case REGLST:
1643 losing++;
1644 break;
1645 default:
1646 break;
1647 }
1648 break;
1649
1650 case '?':
1651 switch (opP->mode)
1652 {
1653 case AREG:
1654 case CONTROL:
1655 case FPREG:
1656 case AINC:
1657 case ADEC:
1658 case IMMED:
1659 case REGLST:
1660 losing++;
1661 break;
1662 case ABSL:
1663 break;
1664 default:
1665 if (opP->reg == PC || opP->reg == ZPC)
1666 losing++;
1667 break;
1668 }
1669 break;
1670
1671 case '@':
1672 switch (opP->mode)
1673 {
1674 case AREG:
1675 case CONTROL:
1676 case FPREG:
1677 case IMMED:
1678 case REGLST:
1679 losing++;
1680 break;
1681 default:
1682 break;
1683 }
1684 break;
1685
1686 case '~': /* For now! (JF FOO is this right?) */
1687 switch (opP->mode)
1688 {
1689 case DREG:
1690 case AREG:
1691 case CONTROL:
1692 case FPREG:
1693 case IMMED:
1694 case REGLST:
1695 losing++;
1696 break;
1697 case ABSL:
1698 break;
1699 default:
1700 if (opP->reg == PC
1701 || opP->reg == ZPC)
1702 losing++;
1703 break;
1704 }
1705 break;
1706
1707 case '3':
1708 if (opP->mode != CONTROL
1709 || (opP->reg != TT0 && opP->reg != TT1))
1710 losing++;
1711 break;
1712
1713 case 'A':
1714 if (opP->mode != AREG)
1715 losing++;
1716 break;
1717
1718 case 'a':
1719 if (opP->mode != AINDR)
1720 ++losing;
1721 break;
1722
1723 case '4':
1724 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1725 && (opP->mode != DISP
1726 || opP->reg < ADDR0
1727 || opP->reg > ADDR7))
1728 ++losing;
1729 break;
1730
1731 case 'B': /* FOO */
1732 if (opP->mode != ABSL
1733 || (flag_long_jumps
1734 && strncmp (instring, "jbsr", 4) == 0))
1735 losing++;
1736 break;
1737
1738 case 'b':
1739 switch (opP->mode)
1740 {
1741 case IMMED:
1742 case ABSL:
1743 case AREG:
1744 case FPREG:
1745 case CONTROL:
1746 case POST:
1747 case PRE:
1748 case REGLST:
1749 losing++;
1750 break;
1751 default:
1752 break;
1753 }
1754 break;
1755
1756 case 'C':
1757 if (opP->mode != CONTROL || opP->reg != CCR)
1758 losing++;
1759 break;
1760
1761 case 'd':
1762 if (opP->mode != DISP
1763 || opP->reg < ADDR0
1764 || opP->reg > ADDR7)
1765 losing++;
1766 break;
1767
1768 case 'D':
1769 if (opP->mode != DREG)
1770 losing++;
1771 break;
1772
1773 case 'E':
1774 if (opP->reg != ACC)
1775 losing++;
1776 break;
1777
1778 case 'e':
1779 if (opP->reg != ACC && opP->reg != ACC1
1780 && opP->reg != ACC2 && opP->reg != ACC3)
1781 losing++;
1782 break;
1783
1784 case 'F':
1785 if (opP->mode != FPREG)
1786 losing++;
1787 break;
1788
1789 case 'G':
1790 if (opP->reg != MACSR)
1791 losing++;
1792 break;
1793
1794 case 'g':
1795 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1796 losing++;
1797 break;
1798
1799 case 'H':
1800 if (opP->reg != MASK)
1801 losing++;
1802 break;
1803
1804 case 'I':
1805 if (opP->mode != CONTROL
1806 || opP->reg < COP0
1807 || opP->reg > COP7)
1808 losing++;
1809 break;
1810
1811 case 'i':
1812 if (opP->mode != LSH && opP->mode != RSH)
1813 losing++;
1814 break;
1815
1816 case 'J':
1817 if (opP->mode != CONTROL
1818 || opP->reg < USP
1819 || opP->reg > last_movec_reg
1820 || !control_regs)
1821 losing++;
1822 else
1823 {
1824 const enum m68k_register *rp;
1825
1826 for (rp = control_regs; *rp; rp++)
1827 {
1828 if (*rp == opP->reg)
1829 break;
1830 /* In most CPUs RAMBAR refers to control reg
1831 c05 (RAMBAR1), but a few CPUs have it
1832 refer to c04 (RAMBAR0). */
1833 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1834 {
1835 opP->reg = RAMBAR_ALT;
1836 break;
1837 }
1838 }
1839 if (*rp == 0)
1840 losing++;
1841 }
1842 break;
1843
1844 case 'k':
1845 if (opP->mode != IMMED)
1846 losing++;
1847 break;
1848
1849 case 'l':
1850 case 'L':
1851 if (opP->mode == DREG
1852 || opP->mode == AREG
1853 || opP->mode == FPREG)
1854 {
1855 if (s[1] == '8')
1856 losing++;
1857 else
1858 {
1859 switch (opP->mode)
1860 {
1861 case DREG:
1862 opP->mask = 1 << (opP->reg - DATA0);
1863 break;
1864 case AREG:
1865 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1866 break;
1867 case FPREG:
1868 opP->mask = 1 << (opP->reg - FP0 + 16);
1869 break;
1870 default:
1871 abort ();
1872 }
1873 opP->mode = REGLST;
1874 }
1875 }
1876 else if (opP->mode == CONTROL)
1877 {
1878 if (s[1] != '8')
1879 losing++;
1880 else
1881 {
1882 switch (opP->reg)
1883 {
1884 case FPI:
1885 opP->mask = 1 << 24;
1886 break;
1887 case FPS:
1888 opP->mask = 1 << 25;
1889 break;
1890 case FPC:
1891 opP->mask = 1 << 26;
1892 break;
1893 default:
1894 losing++;
1895 break;
1896 }
1897 opP->mode = REGLST;
1898 }
1899 }
1900 else if (opP->mode != REGLST)
1901 losing++;
1902 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1903 losing++;
1904 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1905 losing++;
1906 break;
1907
1908 case 'M':
1909 if (opP->mode != IMMED)
1910 losing++;
1911 else if (opP->disp.exp.X_op != O_constant
1912 || ! issbyte (opP->disp.exp.X_add_number))
1913 losing++;
1914 else if (! m68k_quick
1915 && instring[3] != 'q'
1916 && instring[4] != 'q')
1917 losing++;
1918 break;
1919
1920 case 'O':
1921 if (opP->mode != DREG
1922 && opP->mode != IMMED
1923 && opP->mode != ABSL)
1924 losing++;
1925 break;
1926
1927 case 'Q':
1928 if (opP->mode != IMMED)
1929 losing++;
1930 else if (opP->disp.exp.X_op != O_constant
1931 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
1932 losing++;
1933 else if (! m68k_quick
1934 && (strncmp (instring, "add", 3) == 0
1935 || strncmp (instring, "sub", 3) == 0)
1936 && instring[3] != 'q')
1937 losing++;
1938 break;
1939
1940 case 'R':
1941 if (opP->mode != DREG && opP->mode != AREG)
1942 losing++;
1943 break;
1944
1945 case 'r':
1946 if (opP->mode != AINDR
1947 && (opP->mode != BASE
1948 || (opP->reg != 0
1949 && opP->reg != ZADDR0)
1950 || opP->disp.exp.X_op != O_absent
1951 || ((opP->index.reg < DATA0
1952 || opP->index.reg > DATA7)
1953 && (opP->index.reg < ADDR0
1954 || opP->index.reg > ADDR7))
1955 || opP->index.size != SIZE_UNSPEC
1956 || opP->index.scale != 1))
1957 losing++;
1958 break;
1959
1960 case 's':
1961 if (opP->mode != CONTROL
1962 || ! (opP->reg == FPI
1963 || opP->reg == FPS
1964 || opP->reg == FPC))
1965 losing++;
1966 break;
1967
1968 case 'S':
1969 if (opP->mode != CONTROL || opP->reg != SR)
1970 losing++;
1971 break;
1972
1973 case 't':
1974 if (opP->mode != IMMED)
1975 losing++;
1976 else if (opP->disp.exp.X_op != O_constant
1977 || TRUNC (opP->disp.exp.X_add_number) > 7)
1978 losing++;
1979 break;
1980
1981 case 'U':
1982 if (opP->mode != CONTROL || opP->reg != USP)
1983 losing++;
1984 break;
1985
1986 case 'x':
1987 if (opP->mode != IMMED)
1988 losing++;
1989 else if (opP->disp.exp.X_op != O_constant
1990 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1991 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
1992 losing++;
1993 break;
1994
1995 case 'j':
1996 if (opP->mode != IMMED)
1997 losing++;
1998 else if (opP->disp.exp.X_op != O_constant
1999 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2000 losing++;
2001 break;
2002
2003 case 'K':
2004 if (opP->mode != IMMED)
2005 losing++;
2006 else if (opP->disp.exp.X_op != O_constant
2007 || TRUNC (opP->disp.exp.X_add_number) > 511)
2008 losing++;
2009 break;
2010
2011 /* JF these are out of order. We could put them
2012 in order if we were willing to put up with
2013 bunches of #ifdef m68851s in the code.
2014
2015 Don't forget that you need these operands
2016 to use 68030 MMU instructions. */
2017 #ifndef NO_68851
2018 /* Memory addressing mode used by pflushr. */
2019 case '|':
2020 if (opP->mode == CONTROL
2021 || opP->mode == FPREG
2022 || opP->mode == DREG
2023 || opP->mode == AREG
2024 || opP->mode == REGLST)
2025 losing++;
2026 /* We should accept immediate operands, but they
2027 supposedly have to be quad word, and we don't
2028 handle that. I would like to see what a Motorola
2029 assembler does before doing something here. */
2030 if (opP->mode == IMMED)
2031 losing++;
2032 break;
2033
2034 case 'f':
2035 if (opP->mode != CONTROL
2036 || (opP->reg != SFC && opP->reg != DFC))
2037 losing++;
2038 break;
2039
2040 case '0':
2041 if (opP->mode != CONTROL || opP->reg != TC)
2042 losing++;
2043 break;
2044
2045 case '1':
2046 if (opP->mode != CONTROL || opP->reg != AC)
2047 losing++;
2048 break;
2049
2050 case '2':
2051 if (opP->mode != CONTROL
2052 || (opP->reg != CAL
2053 && opP->reg != VAL
2054 && opP->reg != SCC))
2055 losing++;
2056 break;
2057
2058 case 'V':
2059 if (opP->mode != CONTROL
2060 || opP->reg != VAL)
2061 losing++;
2062 break;
2063
2064 case 'W':
2065 if (opP->mode != CONTROL
2066 || (opP->reg != DRP
2067 && opP->reg != SRP
2068 && opP->reg != CRP))
2069 losing++;
2070 break;
2071
2072 case 'w':
2073 switch (opP->mode)
2074 {
2075 case IMMED:
2076 case ABSL:
2077 case AREG:
2078 case DREG:
2079 case FPREG:
2080 case CONTROL:
2081 case POST:
2082 case PRE:
2083 case REGLST:
2084 losing++;
2085 break;
2086 default:
2087 break;
2088 }
2089 break;
2090
2091 case 'X':
2092 if (opP->mode != CONTROL
2093 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2094 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2095 losing++;
2096 break;
2097
2098 case 'Y':
2099 if (opP->mode != CONTROL || opP->reg != PSR)
2100 losing++;
2101 break;
2102
2103 case 'Z':
2104 if (opP->mode != CONTROL || opP->reg != PCSR)
2105 losing++;
2106 break;
2107 #endif
2108 case 'c':
2109 if (opP->mode != CONTROL
2110 || (opP->reg != NC
2111 && opP->reg != IC
2112 && opP->reg != DC
2113 && opP->reg != BC))
2114 losing++;
2115 break;
2116
2117 case '_':
2118 if (opP->mode != ABSL)
2119 ++losing;
2120 break;
2121
2122 case 'u':
2123 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2124 losing++;
2125 /* FIXME: kludge instead of fixing parser:
2126 upper/lower registers are *not* CONTROL
2127 registers, but ordinary ones. */
2128 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2129 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2130 opP->mode = DREG;
2131 else
2132 opP->mode = AREG;
2133 break;
2134
2135 case 'y':
2136 if (!(opP->mode == AINDR
2137 || (opP->mode == DISP
2138 && !(opP->reg == PC || opP->reg == ZPC))))
2139 losing++;
2140 break;
2141
2142 case 'z':
2143 if (!(opP->mode == AINDR || opP->mode == DISP))
2144 losing++;
2145 break;
2146
2147 default:
2148 abort ();
2149 }
2150
2151 if (losing)
2152 break;
2153 }
2154
2155 /* Since we have found the correct instruction, copy
2156 in the modifications that we may have made. */
2157 if (!losing)
2158 for (i = 0; i < opsfound; i++)
2159 the_ins.operands[i] = operands_backup[i];
2160 }
2161
2162 if (!losing)
2163 break;
2164
2165 opcode = opcode->m_next;
2166
2167 if (!opcode)
2168 {
2169 if (ok_arch
2170 && !(ok_arch & current_architecture))
2171 {
2172 const struct m68k_cpu *cpu;
2173 int any = 0;
2174 size_t space = 400;
2175 char *buf = xmalloc (space + 1);
2176 size_t len;
2177 int paren = 1;
2178
2179 the_ins.error = buf;
2180 /* Make sure there's a NUL at the end of the buffer -- strncpy
2181 won't write one when it runs out of buffer */
2182 buf[space] = 0;
2183 #define APPEND(STRING) \
2184 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2185
2186 APPEND (_("invalid instruction for this architecture; needs "));
2187 switch (ok_arch)
2188 {
2189 case mcfisa_a:
2190 APPEND (_("ColdFire ISA_A"));
2191 break;
2192 case mcfhwdiv:
2193 APPEND (_("ColdFire hardware divide"));
2194 break;
2195 case mcfisa_aa:
2196 APPEND (_("ColdFire ISA_A+"));
2197 break;
2198 case mcfisa_b:
2199 APPEND (_("ColdFire ISA_B"));
2200 break;
2201 case mcfisa_c:
2202 APPEND (_("ColdFire ISA_C"));
2203 break;
2204 case cfloat:
2205 APPEND (_("ColdFire fpu"));
2206 break;
2207 case mfloat:
2208 APPEND (_("M68K fpu"));
2209 break;
2210 case mmmu:
2211 APPEND (_("M68K mmu"));
2212 break;
2213 case m68020up:
2214 APPEND (_("68020 or higher"));
2215 break;
2216 case m68000up:
2217 APPEND (_("68000 or higher"));
2218 break;
2219 case m68010up:
2220 APPEND (_("68010 or higher"));
2221 break;
2222 default:
2223 paren = 0;
2224 }
2225 if (paren)
2226 APPEND (" (");
2227
2228 for (cpu = m68k_cpus; cpu->name; cpu++)
2229 if (!cpu->alias && (cpu->arch & ok_arch))
2230 {
2231 const struct m68k_cpu *alias;
2232 int seen_master = 0;
2233
2234 if (any)
2235 APPEND (", ");
2236 any = 0;
2237 APPEND (cpu->name);
2238 for (alias = cpu; alias != m68k_cpus; alias--)
2239 if (alias[-1].alias >= 0)
2240 break;
2241 for (; !seen_master || alias->alias > 0; alias++)
2242 {
2243 if (!alias->alias)
2244 seen_master = 1;
2245 else
2246 {
2247 if (any)
2248 APPEND (", ");
2249 else
2250 APPEND (" [");
2251 APPEND (alias->name);
2252 any = 1;
2253 }
2254 }
2255 if (any)
2256 APPEND ("]");
2257 any = 1;
2258 }
2259 if (paren)
2260 APPEND (")");
2261 #undef APPEND
2262 if (!space)
2263 {
2264 /* we ran out of space, so replace the end of the list
2265 with ellipsis. */
2266 buf -= 4;
2267 while (*buf != ' ')
2268 buf--;
2269 strcpy (buf, " ...");
2270 }
2271 }
2272 else
2273 the_ins.error = _("operands mismatch");
2274 return;
2275 }
2276
2277 losing = 0;
2278 }
2279
2280 /* Now assemble it. */
2281 the_ins.args = opcode->m_operands;
2282 the_ins.numargs = opcode->m_opnum;
2283 the_ins.numo = opcode->m_codenum;
2284 the_ins.opcode[0] = getone (opcode);
2285 the_ins.opcode[1] = gettwo (opcode);
2286
2287 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2288 {
2289 int have_disp = 0;
2290 int use_pl = 0;
2291
2292 /* This switch is a doozy.
2293 Watch the first step; its a big one! */
2294 switch (s[0])
2295 {
2296
2297 case '*':
2298 case '~':
2299 case '%':
2300 case ';':
2301 case '@':
2302 case '!':
2303 case '&':
2304 case '$':
2305 case '?':
2306 case '/':
2307 case '<':
2308 case '>':
2309 case 'b':
2310 case 'm':
2311 case 'n':
2312 case 'o':
2313 case 'p':
2314 case 'q':
2315 case 'v':
2316 case 'w':
2317 case 'y':
2318 case 'z':
2319 case '4':
2320 #ifndef NO_68851
2321 case '|':
2322 #endif
2323 switch (opP->mode)
2324 {
2325 case IMMED:
2326 tmpreg = 0x3c; /* 7.4 */
2327 if (strchr ("bwl", s[1]))
2328 nextword = get_num (&opP->disp, 90);
2329 else
2330 nextword = get_num (&opP->disp, 0);
2331 if (isvar (&opP->disp))
2332 add_fix (s[1], &opP->disp, 0, 0);
2333 switch (s[1])
2334 {
2335 case 'b':
2336 if (!isbyte (nextword))
2337 opP->error = _("operand out of range");
2338 addword (nextword);
2339 baseo = 0;
2340 break;
2341 case 'w':
2342 if (!isword (nextword))
2343 opP->error = _("operand out of range");
2344 addword (nextword);
2345 baseo = 0;
2346 break;
2347 case 'W':
2348 if (!issword (nextword))
2349 opP->error = _("operand out of range");
2350 addword (nextword);
2351 baseo = 0;
2352 break;
2353 case 'l':
2354 addword (nextword >> 16);
2355 addword (nextword);
2356 baseo = 0;
2357 break;
2358
2359 case 'f':
2360 baseo = 2;
2361 outro = 8;
2362 break;
2363 case 'F':
2364 baseo = 4;
2365 outro = 11;
2366 break;
2367 case 'x':
2368 baseo = 6;
2369 outro = 15;
2370 break;
2371 case 'p':
2372 baseo = 6;
2373 outro = -1;
2374 break;
2375 default:
2376 abort ();
2377 }
2378 if (!baseo)
2379 break;
2380
2381 /* We gotta put out some float. */
2382 if (op (&opP->disp) != O_big)
2383 {
2384 valueT val;
2385 int gencnt;
2386
2387 /* Can other cases happen here? */
2388 if (op (&opP->disp) != O_constant)
2389 abort ();
2390
2391 val = (valueT) offs (&opP->disp);
2392 gencnt = 0;
2393 do
2394 {
2395 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2396 val >>= LITTLENUM_NUMBER_OF_BITS;
2397 ++gencnt;
2398 }
2399 while (val != 0);
2400 offs (&opP->disp) = gencnt;
2401 }
2402 if (offs (&opP->disp) > 0)
2403 {
2404 if (offs (&opP->disp) > baseo)
2405 {
2406 as_warn (_("Bignum too big for %c format; truncated"),
2407 s[1]);
2408 offs (&opP->disp) = baseo;
2409 }
2410 baseo -= offs (&opP->disp);
2411 while (baseo--)
2412 addword (0);
2413 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2414 offs (&opP->disp)--;
2415 --wordp)
2416 addword (*wordp);
2417 break;
2418 }
2419 gen_to_words (words, baseo, (long) outro);
2420 for (wordp = words; baseo--; wordp++)
2421 addword (*wordp);
2422 break;
2423 case DREG:
2424 tmpreg = opP->reg - DATA; /* 0.dreg */
2425 break;
2426 case AREG:
2427 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2428 break;
2429 case AINDR:
2430 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2431 break;
2432 case ADEC:
2433 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2434 break;
2435 case AINC:
2436 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2437 break;
2438 case DISP:
2439
2440 nextword = get_num (&opP->disp, 90);
2441
2442 /* Convert mode 5 addressing with a zero offset into
2443 mode 2 addressing to reduce the instruction size by a
2444 word. */
2445 if (! isvar (&opP->disp)
2446 && (nextword == 0)
2447 && (opP->disp.size == SIZE_UNSPEC)
2448 && (opP->reg >= ADDR0)
2449 && (opP->reg <= ADDR7))
2450 {
2451 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2452 break;
2453 }
2454
2455 if (opP->reg == PC
2456 && ! isvar (&opP->disp)
2457 && m68k_abspcadd)
2458 {
2459 opP->disp.exp.X_op = O_symbol;
2460 opP->disp.exp.X_add_symbol =
2461 section_symbol (absolute_section);
2462 }
2463
2464 /* Force into index mode. Hope this works. */
2465
2466 /* We do the first bit for 32-bit displacements, and the
2467 second bit for 16 bit ones. It is possible that we
2468 should make the default be WORD instead of LONG, but
2469 I think that'd break GCC, so we put up with a little
2470 inefficiency for the sake of working output. */
2471
2472 if (!issword (nextword)
2473 || (isvar (&opP->disp)
2474 && ((opP->disp.size == SIZE_UNSPEC
2475 && flag_short_refs == 0
2476 && cpu_of_arch (current_architecture) >= m68020
2477 && ! arch_coldfire_p (current_architecture))
2478 || opP->disp.size == SIZE_LONG)))
2479 {
2480 if (cpu_of_arch (current_architecture) < m68020
2481 || arch_coldfire_p (current_architecture))
2482 opP->error =
2483 _("displacement too large for this architecture; needs 68020 or higher");
2484 if (opP->reg == PC)
2485 tmpreg = 0x3B; /* 7.3 */
2486 else
2487 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2488 if (isvar (&opP->disp))
2489 {
2490 if (opP->reg == PC)
2491 {
2492 if (opP->disp.size == SIZE_LONG
2493 #ifdef OBJ_ELF
2494 /* If the displacement needs pic
2495 relocation it cannot be relaxed. */
2496 || opP->disp.pic_reloc != pic_none
2497 #endif
2498 )
2499 {
2500 addword (0x0170);
2501 add_fix ('l', &opP->disp, 1, 2);
2502 }
2503 else
2504 {
2505 add_frag (adds (&opP->disp),
2506 SEXT (offs (&opP->disp)),
2507 TAB (PCREL1632, SZ_UNDEF));
2508 break;
2509 }
2510 }
2511 else
2512 {
2513 addword (0x0170);
2514 add_fix ('l', &opP->disp, 0, 0);
2515 }
2516 }
2517 else
2518 addword (0x0170);
2519 addword (nextword >> 16);
2520 }
2521 else
2522 {
2523 if (opP->reg == PC)
2524 tmpreg = 0x3A; /* 7.2 */
2525 else
2526 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2527
2528 if (isvar (&opP->disp))
2529 {
2530 if (opP->reg == PC)
2531 {
2532 add_fix ('w', &opP->disp, 1, 0);
2533 }
2534 else
2535 add_fix ('w', &opP->disp, 0, 0);
2536 }
2537 }
2538 addword (nextword);
2539 break;
2540
2541 case POST:
2542 case PRE:
2543 case BASE:
2544 nextword = 0;
2545 baseo = get_num (&opP->disp, 90);
2546 if (opP->mode == POST || opP->mode == PRE)
2547 outro = get_num (&opP->odisp, 90);
2548 /* Figure out the `addressing mode'.
2549 Also turn on the BASE_DISABLE bit, if needed. */
2550 if (opP->reg == PC || opP->reg == ZPC)
2551 {
2552 tmpreg = 0x3b; /* 7.3 */
2553 if (opP->reg == ZPC)
2554 nextword |= 0x80;
2555 }
2556 else if (opP->reg == 0)
2557 {
2558 nextword |= 0x80;
2559 tmpreg = 0x30; /* 6.garbage */
2560 }
2561 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2562 {
2563 nextword |= 0x80;
2564 tmpreg = 0x30 + opP->reg - ZADDR0;
2565 }
2566 else
2567 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2568
2569 siz1 = opP->disp.size;
2570 if (opP->mode == POST || opP->mode == PRE)
2571 siz2 = opP->odisp.size;
2572 else
2573 siz2 = SIZE_UNSPEC;
2574
2575 /* Index register stuff. */
2576 if (opP->index.reg != 0
2577 && opP->index.reg >= DATA
2578 && opP->index.reg <= ADDR7)
2579 {
2580 nextword |= (opP->index.reg - DATA) << 12;
2581
2582 if (opP->index.size == SIZE_LONG
2583 || (opP->index.size == SIZE_UNSPEC
2584 && m68k_index_width_default == SIZE_LONG))
2585 nextword |= 0x800;
2586
2587 if ((opP->index.scale != 1
2588 && cpu_of_arch (current_architecture) < m68020)
2589 || (opP->index.scale == 8
2590 && (arch_coldfire_p (current_architecture)
2591 && !arch_coldfire_fpu (current_architecture))))
2592 {
2593 opP->error =
2594 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2595 }
2596
2597 if (arch_coldfire_p (current_architecture)
2598 && opP->index.size == SIZE_WORD)
2599 opP->error = _("invalid index size for coldfire");
2600
2601 switch (opP->index.scale)
2602 {
2603 case 1:
2604 break;
2605 case 2:
2606 nextword |= 0x200;
2607 break;
2608 case 4:
2609 nextword |= 0x400;
2610 break;
2611 case 8:
2612 nextword |= 0x600;
2613 break;
2614 default:
2615 abort ();
2616 }
2617 /* IF its simple,
2618 GET US OUT OF HERE! */
2619
2620 /* Must be INDEX, with an index register. Address
2621 register cannot be ZERO-PC, and either :b was
2622 forced, or we know it will fit. For a 68000 or
2623 68010, force this mode anyways, because the
2624 larger modes aren't supported. */
2625 if (opP->mode == BASE
2626 && ((opP->reg >= ADDR0
2627 && opP->reg <= ADDR7)
2628 || opP->reg == PC))
2629 {
2630 if (siz1 == SIZE_BYTE
2631 || cpu_of_arch (current_architecture) < m68020
2632 || arch_coldfire_p (current_architecture)
2633 || (siz1 == SIZE_UNSPEC
2634 && ! isvar (&opP->disp)
2635 && issbyte (baseo)))
2636 {
2637 nextword += baseo & 0xff;
2638 addword (nextword);
2639 if (isvar (&opP->disp))
2640 {
2641 /* Do a byte relocation. If it doesn't
2642 fit (possible on m68000) let the
2643 fixup processing complain later. */
2644 if (opP->reg == PC)
2645 add_fix ('B', &opP->disp, 1, 1);
2646 else
2647 add_fix ('B', &opP->disp, 0, 0);
2648 }
2649 else if (siz1 != SIZE_BYTE)
2650 {
2651 if (siz1 != SIZE_UNSPEC)
2652 as_warn (_("Forcing byte displacement"));
2653 if (! issbyte (baseo))
2654 opP->error = _("byte displacement out of range");
2655 }
2656
2657 break;
2658 }
2659 else if (siz1 == SIZE_UNSPEC
2660 && opP->reg == PC
2661 && isvar (&opP->disp)
2662 && subs (&opP->disp) == NULL
2663 #ifdef OBJ_ELF
2664 /* If the displacement needs pic
2665 relocation it cannot be relaxed. */
2666 && opP->disp.pic_reloc == pic_none
2667 #endif
2668 )
2669 {
2670 /* The code in md_convert_frag_1 needs to be
2671 able to adjust nextword. Call frag_grow
2672 to ensure that we have enough space in
2673 the frag obstack to make all the bytes
2674 contiguous. */
2675 frag_grow (14);
2676 nextword += baseo & 0xff;
2677 addword (nextword);
2678 add_frag (adds (&opP->disp),
2679 SEXT (offs (&opP->disp)),
2680 TAB (PCINDEX, SZ_UNDEF));
2681
2682 break;
2683 }
2684 }
2685 }
2686 else
2687 {
2688 nextword |= 0x40; /* No index reg. */
2689 if (opP->index.reg >= ZDATA0
2690 && opP->index.reg <= ZDATA7)
2691 nextword |= (opP->index.reg - ZDATA0) << 12;
2692 else if (opP->index.reg >= ZADDR0
2693 || opP->index.reg <= ZADDR7)
2694 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2695 }
2696
2697 /* It isn't simple. */
2698
2699 if (cpu_of_arch (current_architecture) < m68020
2700 || arch_coldfire_p (current_architecture))
2701 opP->error =
2702 _("invalid operand mode for this architecture; needs 68020 or higher");
2703
2704 nextword |= 0x100;
2705 /* If the guy specified a width, we assume that it is
2706 wide enough. Maybe it isn't. If so, we lose. */
2707 switch (siz1)
2708 {
2709 case SIZE_UNSPEC:
2710 if (isvar (&opP->disp)
2711 ? m68k_rel32
2712 : ! issword (baseo))
2713 {
2714 siz1 = SIZE_LONG;
2715 nextword |= 0x30;
2716 }
2717 else if (! isvar (&opP->disp) && baseo == 0)
2718 nextword |= 0x10;
2719 else
2720 {
2721 nextword |= 0x20;
2722 siz1 = SIZE_WORD;
2723 }
2724 break;
2725 case SIZE_BYTE:
2726 as_warn (_(":b not permitted; defaulting to :w"));
2727 /* Fall through. */
2728 case SIZE_WORD:
2729 nextword |= 0x20;
2730 break;
2731 case SIZE_LONG:
2732 nextword |= 0x30;
2733 break;
2734 }
2735
2736 /* Figure out inner displacement stuff. */
2737 if (opP->mode == POST || opP->mode == PRE)
2738 {
2739 if (cpu_of_arch (current_architecture) & cpu32)
2740 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2741 switch (siz2)
2742 {
2743 case SIZE_UNSPEC:
2744 if (isvar (&opP->odisp)
2745 ? m68k_rel32
2746 : ! issword (outro))
2747 {
2748 siz2 = SIZE_LONG;
2749 nextword |= 0x3;
2750 }
2751 else if (! isvar (&opP->odisp) && outro == 0)
2752 nextword |= 0x1;
2753 else
2754 {
2755 nextword |= 0x2;
2756 siz2 = SIZE_WORD;
2757 }
2758 break;
2759 case 1:
2760 as_warn (_(":b not permitted; defaulting to :w"));
2761 /* Fall through. */
2762 case 2:
2763 nextword |= 0x2;
2764 break;
2765 case 3:
2766 nextword |= 0x3;
2767 break;
2768 }
2769 if (opP->mode == POST
2770 && (nextword & 0x40) == 0)
2771 nextword |= 0x04;
2772 }
2773 addword (nextword);
2774
2775 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2776 {
2777 if (opP->reg == PC || opP->reg == ZPC)
2778 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2779 else
2780 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2781 }
2782 if (siz1 == SIZE_LONG)
2783 addword (baseo >> 16);
2784 if (siz1 != SIZE_UNSPEC)
2785 addword (baseo);
2786
2787 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2788 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2789 if (siz2 == SIZE_LONG)
2790 addword (outro >> 16);
2791 if (siz2 != SIZE_UNSPEC)
2792 addword (outro);
2793
2794 break;
2795
2796 case ABSL:
2797 nextword = get_num (&opP->disp, 90);
2798 switch (opP->disp.size)
2799 {
2800 default:
2801 abort ();
2802 case SIZE_UNSPEC:
2803 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2804 {
2805 tmpreg = 0x38; /* 7.0 */
2806 addword (nextword);
2807 break;
2808 }
2809 if (isvar (&opP->disp)
2810 && !subs (&opP->disp)
2811 && adds (&opP->disp)
2812 #ifdef OBJ_ELF
2813 /* If the displacement needs pic relocation it
2814 cannot be relaxed. */
2815 && opP->disp.pic_reloc == pic_none
2816 #endif
2817 && !flag_long_jumps
2818 && !strchr ("~%&$?", s[0]))
2819 {
2820 tmpreg = 0x3A; /* 7.2 */
2821 add_frag (adds (&opP->disp),
2822 SEXT (offs (&opP->disp)),
2823 TAB (ABSTOPCREL, SZ_UNDEF));
2824 break;
2825 }
2826 /* Fall through into long. */
2827 case SIZE_LONG:
2828 if (isvar (&opP->disp))
2829 add_fix ('l', &opP->disp, 0, 0);
2830
2831 tmpreg = 0x39;/* 7.1 mode */
2832 addword (nextword >> 16);
2833 addword (nextword);
2834 break;
2835
2836 case SIZE_BYTE:
2837 as_bad (_("unsupported byte value; use a different suffix"));
2838 /* Fall through. */
2839
2840 case SIZE_WORD:
2841 if (isvar (&opP->disp))
2842 add_fix ('w', &opP->disp, 0, 0);
2843
2844 tmpreg = 0x38;/* 7.0 mode */
2845 addword (nextword);
2846 break;
2847 }
2848 break;
2849 case CONTROL:
2850 case FPREG:
2851 default:
2852 as_bad (_("unknown/incorrect operand"));
2853 /* abort (); */
2854 }
2855
2856 /* If s[0] is '4', then this is for the mac instructions
2857 that can have a trailing_ampersand set. If so, set 0x100
2858 bit on tmpreg so install_gen_operand can check for it and
2859 set the appropriate bit (word2, bit 5). */
2860 if (s[0] == '4')
2861 {
2862 if (opP->trailing_ampersand)
2863 tmpreg |= 0x100;
2864 }
2865 install_gen_operand (s[1], tmpreg);
2866 break;
2867
2868 case '#':
2869 case '^':
2870 switch (s[1])
2871 { /* JF: I hate floating point! */
2872 case 'j':
2873 tmpreg = 70;
2874 break;
2875 case '8':
2876 tmpreg = 20;
2877 break;
2878 case 'C':
2879 tmpreg = 50;
2880 break;
2881 case '3':
2882 default:
2883 tmpreg = 90;
2884 break;
2885 }
2886 tmpreg = get_num (&opP->disp, tmpreg);
2887 if (isvar (&opP->disp))
2888 add_fix (s[1], &opP->disp, 0, 0);
2889 switch (s[1])
2890 {
2891 case 'b': /* Danger: These do no check for
2892 certain types of overflow.
2893 user beware! */
2894 if (!isbyte (tmpreg))
2895 opP->error = _("out of range");
2896 insop (tmpreg, opcode);
2897 if (isvar (&opP->disp))
2898 the_ins.reloc[the_ins.nrel - 1].n =
2899 (opcode->m_codenum) * 2 + 1;
2900 break;
2901 case 'B':
2902 if (!issbyte (tmpreg))
2903 opP->error = _("out of range");
2904 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2905 if (isvar (&opP->disp))
2906 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2907 break;
2908 case 'w':
2909 if (!isword (tmpreg))
2910 opP->error = _("out of range");
2911 insop (tmpreg, opcode);
2912 if (isvar (&opP->disp))
2913 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2914 break;
2915 case 'W':
2916 if (!issword (tmpreg))
2917 opP->error = _("out of range");
2918 insop (tmpreg, opcode);
2919 if (isvar (&opP->disp))
2920 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2921 break;
2922 case 'l':
2923 /* Because of the way insop works, we put these two out
2924 backwards. */
2925 insop (tmpreg, opcode);
2926 insop (tmpreg >> 16, opcode);
2927 if (isvar (&opP->disp))
2928 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2929 break;
2930 case '3':
2931 tmpreg &= 0xFF;
2932 case '8':
2933 case 'C':
2934 case 'j':
2935 install_operand (s[1], tmpreg);
2936 break;
2937 default:
2938 abort ();
2939 }
2940 break;
2941
2942 case '+':
2943 case '-':
2944 case 'A':
2945 case 'a':
2946 install_operand (s[1], opP->reg - ADDR);
2947 break;
2948
2949 case 'B':
2950 tmpreg = get_num (&opP->disp, 90);
2951
2952 switch (s[1])
2953 {
2954 case 'B':
2955 add_fix ('B', &opP->disp, 1, -1);
2956 break;
2957 case 'W':
2958 add_fix ('w', &opP->disp, 1, 0);
2959 addword (0);
2960 break;
2961 case 'L':
2962 long_branch:
2963 the_ins.opcode[0] |= 0xff;
2964 add_fix ('l', &opP->disp, 1, 0);
2965 addword (0);
2966 addword (0);
2967 break;
2968 case 'g': /* Conditional branch */
2969 have_disp = HAVE_LONG_CALL (current_architecture);
2970 goto var_branch;
2971
2972 case 'b': /* Unconditional branch */
2973 have_disp = HAVE_LONG_BRANCH (current_architecture);
2974 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
2975 goto var_branch;
2976
2977 case 's': /* Unconditional subroutine */
2978 have_disp = HAVE_LONG_CALL (current_architecture);
2979
2980 var_branch:
2981 if (subs (&opP->disp) /* We can't relax it. */
2982 #ifdef OBJ_ELF
2983 /* If the displacement needs pic relocation it cannot be
2984 relaxed. */
2985 || opP->disp.pic_reloc != pic_none
2986 #endif
2987 || 0)
2988 {
2989 if (!have_disp)
2990 as_warn (_("Can't use long branches on this architecture"));
2991 goto long_branch;
2992 }
2993
2994 /* This could either be a symbol, or an absolute
2995 address. If it's an absolute address, turn it into
2996 an absolute jump right here and keep it out of the
2997 relaxer. */
2998 if (adds (&opP->disp) == 0)
2999 {
3000 if (the_ins.opcode[0] == 0x6000) /* jbra */
3001 the_ins.opcode[0] = 0x4EF9;
3002 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3003 the_ins.opcode[0] = 0x4EB9;
3004 else /* jCC */
3005 {
3006 the_ins.opcode[0] ^= 0x0100;
3007 the_ins.opcode[0] |= 0x0006;
3008 addword (0x4EF9);
3009 }
3010 add_fix ('l', &opP->disp, 0, 0);
3011 addword (0);
3012 addword (0);
3013 break;
3014 }
3015
3016 /* Now we know it's going into the relaxer. Now figure
3017 out which mode. We try in this order of preference:
3018 long branch, absolute jump, byte/word branches only. */
3019 if (have_disp)
3020 add_frag (adds (&opP->disp),
3021 SEXT (offs (&opP->disp)),
3022 TAB (BRANCHBWL, SZ_UNDEF));
3023 else if (! flag_keep_pcrel)
3024 {
3025 if ((the_ins.opcode[0] == 0x6000)
3026 || (the_ins.opcode[0] == 0x6100))
3027 add_frag (adds (&opP->disp),
3028 SEXT (offs (&opP->disp)),
3029 TAB (BRABSJUNC, SZ_UNDEF));
3030 else
3031 add_frag (adds (&opP->disp),
3032 SEXT (offs (&opP->disp)),
3033 TAB (BRABSJCOND, SZ_UNDEF));
3034 }
3035 else
3036 add_frag (adds (&opP->disp),
3037 SEXT (offs (&opP->disp)),
3038 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3039 : TAB (BRANCHBW, SZ_UNDEF)));
3040 break;
3041 case 'w':
3042 if (isvar (&opP->disp))
3043 {
3044 /* Check for DBcc instructions. We can relax them,
3045 but only if we have long branches and/or absolute
3046 jumps. */
3047 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3048 && (HAVE_LONG_BRANCH (current_architecture)
3049 || ! flag_keep_pcrel))
3050 {
3051 if (HAVE_LONG_BRANCH (current_architecture))
3052 add_frag (adds (&opP->disp),
3053 SEXT (offs (&opP->disp)),
3054 TAB (DBCCLBR, SZ_UNDEF));
3055 else
3056 add_frag (adds (&opP->disp),
3057 SEXT (offs (&opP->disp)),
3058 TAB (DBCCABSJ, SZ_UNDEF));
3059 break;
3060 }
3061 add_fix ('w', &opP->disp, 1, 0);
3062 }
3063 addword (0);
3064 break;
3065 case 'C': /* Fixed size LONG coproc branches. */
3066 add_fix ('l', &opP->disp, 1, 0);
3067 addword (0);
3068 addword (0);
3069 break;
3070 case 'c': /* Var size Coprocesssor branches. */
3071 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3072 {
3073 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3074 add_fix ('l', &opP->disp, 1, 0);
3075 addword (0);
3076 addword (0);
3077 }
3078 else
3079 add_frag (adds (&opP->disp),
3080 SEXT (offs (&opP->disp)),
3081 TAB (FBRANCH, SZ_UNDEF));
3082 break;
3083 default:
3084 abort ();
3085 }
3086 break;
3087
3088 case 'C': /* Ignore it. */
3089 break;
3090
3091 case 'd': /* JF this is a kludge. */
3092 install_operand ('s', opP->reg - ADDR);
3093 tmpreg = get_num (&opP->disp, 90);
3094 if (!issword (tmpreg))
3095 {
3096 as_warn (_("Expression out of range, using 0"));
3097 tmpreg = 0;
3098 }
3099 addword (tmpreg);
3100 break;
3101
3102 case 'D':
3103 install_operand (s[1], opP->reg - DATA);
3104 break;
3105
3106 case 'e': /* EMAC ACCx, reg/reg. */
3107 install_operand (s[1], opP->reg - ACC);
3108 break;
3109
3110 case 'E': /* Ignore it. */
3111 break;
3112
3113 case 'F':
3114 install_operand (s[1], opP->reg - FP0);
3115 break;
3116
3117 case 'g': /* EMAC ACCEXTx. */
3118 install_operand (s[1], opP->reg - ACCEXT01);
3119 break;
3120
3121 case 'G': /* Ignore it. */
3122 case 'H':
3123 break;
3124
3125 case 'I':
3126 tmpreg = opP->reg - COP0;
3127 install_operand (s[1], tmpreg);
3128 break;
3129
3130 case 'i': /* MAC/EMAC scale factor. */
3131 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3132 break;
3133
3134 case 'J': /* JF foo. */
3135 switch (opP->reg)
3136 {
3137 case SFC:
3138 tmpreg = 0x000;
3139 break;
3140 case DFC:
3141 tmpreg = 0x001;
3142 break;
3143 case CACR:
3144 tmpreg = 0x002;
3145 break;
3146 case TC:
3147 case ASID:
3148 tmpreg = 0x003;
3149 break;
3150 case ACR0:
3151 case ITT0:
3152 tmpreg = 0x004;
3153 break;
3154 case ACR1:
3155 case ITT1:
3156 tmpreg = 0x005;
3157 break;
3158 case ACR2:
3159 case DTT0:
3160 tmpreg = 0x006;
3161 break;
3162 case ACR3:
3163 case DTT1:
3164 tmpreg = 0x007;
3165 break;
3166 case BUSCR:
3167 case MMUBAR:
3168 tmpreg = 0x008;
3169 break;
3170
3171 case USP:
3172 tmpreg = 0x800;
3173 break;
3174 case VBR:
3175 tmpreg = 0x801;
3176 break;
3177 case CAAR:
3178 tmpreg = 0x802;
3179 break;
3180 case MSP:
3181 tmpreg = 0x803;
3182 break;
3183 case ISP:
3184 tmpreg = 0x804;
3185 break;
3186 case MMUSR:
3187 tmpreg = 0x805;
3188 break;
3189 case URP:
3190 tmpreg = 0x806;
3191 break;
3192 case SRP:
3193 tmpreg = 0x807;
3194 break;
3195 case PCR:
3196 tmpreg = 0x808;
3197 break;
3198 case ROMBAR:
3199 case ROMBAR0:
3200 tmpreg = 0xC00;
3201 break;
3202 case ROMBAR1:
3203 tmpreg = 0xC01;
3204 break;
3205 case FLASHBAR:
3206 case RAMBAR0:
3207 case RAMBAR_ALT:
3208 tmpreg = 0xC04;
3209 break;
3210 case RAMBAR:
3211 case RAMBAR1:
3212 tmpreg = 0xC05;
3213 break;
3214 case MPCR:
3215 tmpreg = 0xC0C;
3216 break;
3217 case EDRAMBAR:
3218 tmpreg = 0xC0D;
3219 break;
3220 case MBAR0:
3221 case MBAR2:
3222 case SECMBAR:
3223 tmpreg = 0xC0E;
3224 break;
3225 case MBAR1:
3226 case MBAR:
3227 tmpreg = 0xC0F;
3228 break;
3229 case PCR1U0:
3230 tmpreg = 0xD02;
3231 break;
3232 case PCR1L0:
3233 tmpreg = 0xD03;
3234 break;
3235 case PCR2U0:
3236 tmpreg = 0xD04;
3237 break;
3238 case PCR2L0:
3239 tmpreg = 0xD05;
3240 break;
3241 case PCR3U0:
3242 tmpreg = 0xD06;
3243 break;
3244 case PCR3L0:
3245 tmpreg = 0xD07;
3246 break;
3247 case PCR1L1:
3248 tmpreg = 0xD0A;
3249 break;
3250 case PCR1U1:
3251 tmpreg = 0xD0B;
3252 break;
3253 case PCR2L1:
3254 tmpreg = 0xD0C;
3255 break;
3256 case PCR2U1:
3257 tmpreg = 0xD0D;
3258 break;
3259 case PCR3L1:
3260 tmpreg = 0xD0E;
3261 break;
3262 case PCR3U1:
3263 tmpreg = 0xD0F;
3264 break;
3265 case CAC:
3266 tmpreg = 0xFFE;
3267 break;
3268 case MBB:
3269 tmpreg = 0xFFF;
3270 break;
3271 default:
3272 abort ();
3273 }
3274 install_operand (s[1], tmpreg);
3275 break;
3276
3277 case 'k':
3278 tmpreg = get_num (&opP->disp, 55);
3279 install_operand (s[1], tmpreg & 0x7f);
3280 break;
3281
3282 case 'l':
3283 tmpreg = opP->mask;
3284 if (s[1] == 'w')
3285 {
3286 if (tmpreg & 0x7FF0000)
3287 as_bad (_("Floating point register in register list"));
3288 insop (reverse_16_bits (tmpreg), opcode);
3289 }
3290 else
3291 {
3292 if (tmpreg & 0x700FFFF)
3293 as_bad (_("Wrong register in floating-point reglist"));
3294 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3295 }
3296 break;
3297
3298 case 'L':
3299 tmpreg = opP->mask;
3300 if (s[1] == 'w')
3301 {
3302 if (tmpreg & 0x7FF0000)
3303 as_bad (_("Floating point register in register list"));
3304 insop (tmpreg, opcode);
3305 }
3306 else if (s[1] == '8')
3307 {
3308 if (tmpreg & 0x0FFFFFF)
3309 as_bad (_("incorrect register in reglist"));
3310 install_operand (s[1], tmpreg >> 24);
3311 }
3312 else
3313 {
3314 if (tmpreg & 0x700FFFF)
3315 as_bad (_("wrong register in floating-point reglist"));
3316 else
3317 install_operand (s[1], tmpreg >> 16);
3318 }
3319 break;
3320
3321 case 'M':
3322 install_operand (s[1], get_num (&opP->disp, 60));
3323 break;
3324
3325 case 'O':
3326 tmpreg = ((opP->mode == DREG)
3327 ? 0x20 + (int) (opP->reg - DATA)
3328 : (get_num (&opP->disp, 40) & 0x1F));
3329 install_operand (s[1], tmpreg);
3330 break;
3331
3332 case 'Q':
3333 tmpreg = get_num (&opP->disp, 10);
3334 if (tmpreg == 8)
3335 tmpreg = 0;
3336 install_operand (s[1], tmpreg);
3337 break;
3338
3339 case 'R':
3340 /* This depends on the fact that ADDR registers are eight
3341 more than their corresponding DATA regs, so the result
3342 will have the ADDR_REG bit set. */
3343 install_operand (s[1], opP->reg - DATA);
3344 break;
3345
3346 case 'r':
3347 if (opP->mode == AINDR)
3348 install_operand (s[1], opP->reg - DATA);
3349 else
3350 install_operand (s[1], opP->index.reg - DATA);
3351 break;
3352
3353 case 's':
3354 if (opP->reg == FPI)
3355 tmpreg = 0x1;
3356 else if (opP->reg == FPS)
3357 tmpreg = 0x2;
3358 else if (opP->reg == FPC)
3359 tmpreg = 0x4;
3360 else
3361 abort ();
3362 install_operand (s[1], tmpreg);
3363 break;
3364
3365 case 'S': /* Ignore it. */
3366 break;
3367
3368 case 'T':
3369 install_operand (s[1], get_num (&opP->disp, 30));
3370 break;
3371
3372 case 'U': /* Ignore it. */
3373 break;
3374
3375 case 'c':
3376 switch (opP->reg)
3377 {
3378 case NC:
3379 tmpreg = 0;
3380 break;
3381 case DC:
3382 tmpreg = 1;
3383 break;
3384 case IC:
3385 tmpreg = 2;
3386 break;
3387 case BC:
3388 tmpreg = 3;
3389 break;
3390 default:
3391 as_fatal (_("failed sanity check"));
3392 } /* switch on cache token. */
3393 install_operand (s[1], tmpreg);
3394 break;
3395 #ifndef NO_68851
3396 /* JF: These are out of order, I fear. */
3397 case 'f':
3398 switch (opP->reg)
3399 {
3400 case SFC:
3401 tmpreg = 0;
3402 break;
3403 case DFC:
3404 tmpreg = 1;
3405 break;
3406 default:
3407 abort ();
3408 }
3409 install_operand (s[1], tmpreg);
3410 break;
3411
3412 case '0':
3413 case '1':
3414 case '2':
3415 switch (opP->reg)
3416 {
3417 case TC:
3418 tmpreg = 0;
3419 break;
3420 case CAL:
3421 tmpreg = 4;
3422 break;
3423 case VAL:
3424 tmpreg = 5;
3425 break;
3426 case SCC:
3427 tmpreg = 6;
3428 break;
3429 case AC:
3430 tmpreg = 7;
3431 break;
3432 default:
3433 abort ();
3434 }
3435 install_operand (s[1], tmpreg);
3436 break;
3437
3438 case 'V':
3439 if (opP->reg == VAL)
3440 break;
3441 abort ();
3442
3443 case 'W':
3444 switch (opP->reg)
3445 {
3446 case DRP:
3447 tmpreg = 1;
3448 break;
3449 case SRP:
3450 tmpreg = 2;
3451 break;
3452 case CRP:
3453 tmpreg = 3;
3454 break;
3455 default:
3456 abort ();
3457 }
3458 install_operand (s[1], tmpreg);
3459 break;
3460
3461 case 'X':
3462 switch (opP->reg)
3463 {
3464 case BAD:
3465 case BAD + 1:
3466 case BAD + 2:
3467 case BAD + 3:
3468 case BAD + 4:
3469 case BAD + 5:
3470 case BAD + 6:
3471 case BAD + 7:
3472 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3473 break;
3474
3475 case BAC:
3476 case BAC + 1:
3477 case BAC + 2:
3478 case BAC + 3:
3479 case BAC + 4:
3480 case BAC + 5:
3481 case BAC + 6:
3482 case BAC + 7:
3483 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3484 break;
3485
3486 default:
3487 abort ();
3488 }
3489 install_operand (s[1], tmpreg);
3490 break;
3491 case 'Y':
3492 know (opP->reg == PSR);
3493 break;
3494 case 'Z':
3495 know (opP->reg == PCSR);
3496 break;
3497 #endif /* m68851 */
3498 case '3':
3499 switch (opP->reg)
3500 {
3501 case TT0:
3502 tmpreg = 2;
3503 break;
3504 case TT1:
3505 tmpreg = 3;
3506 break;
3507 default:
3508 abort ();
3509 }
3510 install_operand (s[1], tmpreg);
3511 break;
3512 case 't':
3513 tmpreg = get_num (&opP->disp, 20);
3514 install_operand (s[1], tmpreg);
3515 break;
3516 case '_': /* used only for move16 absolute 32-bit address. */
3517 if (isvar (&opP->disp))
3518 add_fix ('l', &opP->disp, 0, 0);
3519 tmpreg = get_num (&opP->disp, 90);
3520 addword (tmpreg >> 16);
3521 addword (tmpreg & 0xFFFF);
3522 break;
3523 case 'u':
3524 install_operand (s[1], opP->reg - DATA0L);
3525 opP->reg -= (DATA0L);
3526 opP->reg &= 0x0F; /* remove upper/lower bit. */
3527 break;
3528 case 'x':
3529 tmpreg = get_num (&opP->disp, 80);
3530 if (tmpreg == -1)
3531 tmpreg = 0;
3532 install_operand (s[1], tmpreg);
3533 break;
3534 case 'j':
3535 tmpreg = get_num (&opP->disp, 10);
3536 install_operand (s[1], tmpreg - 1);
3537 break;
3538 case 'K':
3539 tmpreg = get_num (&opP->disp, 65);
3540 install_operand (s[1], tmpreg);
3541 break;
3542 default:
3543 abort ();
3544 }
3545 }
3546
3547 /* By the time whe get here (FINALLY) the_ins contains the complete
3548 instruction, ready to be emitted. . . */
3549 }
3550
3551 static int
3552 reverse_16_bits (int in)
3553 {
3554 int out = 0;
3555 int n;
3556
3557 static int mask[16] =
3558 {
3559 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3560 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3561 };
3562 for (n = 0; n < 16; n++)
3563 {
3564 if (in & mask[n])
3565 out |= mask[15 - n];
3566 }
3567 return out;
3568 } /* reverse_16_bits() */
3569
3570 static int
3571 reverse_8_bits (int in)
3572 {
3573 int out = 0;
3574 int n;
3575
3576 static int mask[8] =
3577 {
3578 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3579 };
3580
3581 for (n = 0; n < 8; n++)
3582 {
3583 if (in & mask[n])
3584 out |= mask[7 - n];
3585 }
3586 return out;
3587 } /* reverse_8_bits() */
3588
3589 /* Cause an extra frag to be generated here, inserting up to
3590 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3591 generated; its primary type is rs_machine_dependent.
3592
3593 The TYPE parameter is also used by md_convert_frag_1 and
3594 md_estimate_size_before_relax. The appropriate type of fixup will
3595 be emitted by md_convert_frag_1.
3596
3597 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3598 static void
3599 install_operand (int mode, int val)
3600 {
3601 switch (mode)
3602 {
3603 case 's':
3604 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3605 break;
3606 case 'd':
3607 the_ins.opcode[0] |= val << 9;
3608 break;
3609 case 'E':
3610 the_ins.opcode[1] |= val << 9;
3611 break;
3612 case '1':
3613 the_ins.opcode[1] |= val << 12;
3614 break;
3615 case '2':
3616 the_ins.opcode[1] |= val << 6;
3617 break;
3618 case '3':
3619 the_ins.opcode[1] |= val;
3620 break;
3621 case '4':
3622 the_ins.opcode[2] |= val << 12;
3623 break;
3624 case '5':
3625 the_ins.opcode[2] |= val << 6;
3626 break;
3627 case '6':
3628 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3629 three words long! */
3630 the_ins.numo++;
3631 the_ins.opcode[2] |= val;
3632 break;
3633 case '7':
3634 the_ins.opcode[1] |= val << 7;
3635 break;
3636 case '8':
3637 the_ins.opcode[1] |= val << 10;
3638 break;
3639 #ifndef NO_68851
3640 case '9':
3641 the_ins.opcode[1] |= val << 5;
3642 break;
3643 #endif
3644
3645 case 't':
3646 the_ins.opcode[1] |= (val << 10) | (val << 7);
3647 break;
3648 case 'D':
3649 the_ins.opcode[1] |= (val << 12) | val;
3650 break;
3651 case 'g':
3652 the_ins.opcode[0] |= val = 0xff;
3653 break;
3654 case 'i':
3655 the_ins.opcode[0] |= val << 9;
3656 break;
3657 case 'C':
3658 the_ins.opcode[1] |= val;
3659 break;
3660 case 'j':
3661 the_ins.opcode[1] |= val;
3662 the_ins.numo++; /* What a hack. */
3663 break;
3664 case 'k':
3665 the_ins.opcode[1] |= val << 4;
3666 break;
3667 case 'b':
3668 case 'w':
3669 case 'W':
3670 case 'l':
3671 break;
3672 case 'e':
3673 the_ins.opcode[0] |= (val << 6);
3674 break;
3675 case 'L':
3676 the_ins.opcode[1] = (val >> 16);
3677 the_ins.opcode[2] = val & 0xffff;
3678 break;
3679 case 'm':
3680 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3681 the_ins.opcode[0] |= ((val & 0x7) << 9);
3682 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3683 break;
3684 case 'n': /* MAC/EMAC Rx on !load. */
3685 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3686 the_ins.opcode[0] |= ((val & 0x7) << 9);
3687 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3688 break;
3689 case 'o': /* MAC/EMAC Rx on load. */
3690 the_ins.opcode[1] |= val << 12;
3691 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3692 break;
3693 case 'M': /* MAC/EMAC Ry on !load. */
3694 the_ins.opcode[0] |= (val & 0xF);
3695 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3696 break;
3697 case 'N': /* MAC/EMAC Ry on load. */
3698 the_ins.opcode[1] |= (val & 0xF);
3699 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3700 break;
3701 case 'h':
3702 the_ins.opcode[1] |= ((val != 1) << 10);
3703 break;
3704 case 'F':
3705 the_ins.opcode[0] |= ((val & 0x3) << 9);
3706 break;
3707 case 'f':
3708 the_ins.opcode[0] |= ((val & 0x3) << 0);
3709 break;
3710 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3711 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3712 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3713 break;
3714 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3715 the_ins.opcode[0] |= ((val & 0x1) << 7);
3716 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3717 break;
3718 case 'I':
3719 the_ins.opcode[1] |= ((val & 0x3) << 9);
3720 break;
3721 case ']':
3722 the_ins.opcode[0] |= (val & 0x1) <<10;
3723 break;
3724 case 'c':
3725 default:
3726 as_fatal (_("failed sanity check."));
3727 }
3728 }
3729
3730 static void
3731 install_gen_operand (int mode, int val)
3732 {
3733 switch (mode)
3734 {
3735 case '/': /* Special for mask loads for mac/msac insns with
3736 possible mask; trailing_ampersend set in bit 8. */
3737 the_ins.opcode[0] |= (val & 0x3f);
3738 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3739 break;
3740 case 's':
3741 the_ins.opcode[0] |= val;
3742 break;
3743 case 'd':
3744 /* This is a kludge!!! */
3745 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3746 break;
3747 case 'b':
3748 case 'w':
3749 case 'l':
3750 case 'f':
3751 case 'F':
3752 case 'x':
3753 case 'p':
3754 the_ins.opcode[0] |= val;
3755 break;
3756 /* more stuff goes here. */
3757 default:
3758 as_fatal (_("failed sanity check."));
3759 }
3760 }
3761
3762 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3763 then deal with the bitfield hack. */
3764
3765 static char *
3766 crack_operand (char *str, struct m68k_op *opP)
3767 {
3768 register int parens;
3769 register int c;
3770 register char *beg_str;
3771 int inquote = 0;
3772
3773 if (!str)
3774 {
3775 return str;
3776 }
3777 beg_str = str;
3778 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3779 {
3780 if (! inquote)
3781 {
3782 if (*str == '(')
3783 parens++;
3784 else if (*str == ')')
3785 {
3786 if (!parens)
3787 { /* ERROR. */
3788 opP->error = _("Extra )");
3789 return str;
3790 }
3791 --parens;
3792 }
3793 }
3794 if (flag_mri && *str == '\'')
3795 inquote = ! inquote;
3796 }
3797 if (!*str && parens)
3798 { /* ERROR. */
3799 opP->error = _("Missing )");
3800 return str;
3801 }
3802 c = *str;
3803 *str = '\0';
3804 if (m68k_ip_op (beg_str, opP) != 0)
3805 {
3806 *str = c;
3807 return str;
3808 }
3809 *str = c;
3810 if (c == '}')
3811 c = *++str; /* JF bitfield hack. */
3812 if (c)
3813 {
3814 c = *++str;
3815 if (!c)
3816 as_bad (_("Missing operand"));
3817 }
3818
3819 /* Detect MRI REG symbols and convert them to REGLSTs. */
3820 if (opP->mode == CONTROL && (int)opP->reg < 0)
3821 {
3822 opP->mode = REGLST;
3823 opP->mask = ~(int)opP->reg;
3824 opP->reg = 0;
3825 }
3826
3827 return str;
3828 }
3829
3830 /* This is the guts of the machine-dependent assembler. STR points to a
3831 machine dependent instruction. This function is supposed to emit
3832 the frags/bytes it assembles to.
3833 */
3834
3835 static void
3836 insert_reg (const char *regname, int regnum)
3837 {
3838 char buf[100];
3839 int i;
3840
3841 #ifdef REGISTER_PREFIX
3842 if (!flag_reg_prefix_optional)
3843 {
3844 buf[0] = REGISTER_PREFIX;
3845 strcpy (buf + 1, regname);
3846 regname = buf;
3847 }
3848 #endif
3849
3850 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3851 &zero_address_frag));
3852
3853 for (i = 0; regname[i]; i++)
3854 buf[i] = TOUPPER (regname[i]);
3855 buf[i] = '\0';
3856
3857 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3858 &zero_address_frag));
3859 }
3860
3861 struct init_entry
3862 {
3863 const char *name;
3864 int number;
3865 };
3866
3867 static const struct init_entry init_table[] =
3868 {
3869 { "d0", DATA0 },
3870 { "d1", DATA1 },
3871 { "d2", DATA2 },
3872 { "d3", DATA3 },
3873 { "d4", DATA4 },
3874 { "d5", DATA5 },
3875 { "d6", DATA6 },
3876 { "d7", DATA7 },
3877 { "a0", ADDR0 },
3878 { "a1", ADDR1 },
3879 { "a2", ADDR2 },
3880 { "a3", ADDR3 },
3881 { "a4", ADDR4 },
3882 { "a5", ADDR5 },
3883 { "a6", ADDR6 },
3884 { "fp", ADDR6 },
3885 { "a7", ADDR7 },
3886 { "sp", ADDR7 },
3887 { "ssp", ADDR7 },
3888 { "fp0", FP0 },
3889 { "fp1", FP1 },
3890 { "fp2", FP2 },
3891 { "fp3", FP3 },
3892 { "fp4", FP4 },
3893 { "fp5", FP5 },
3894 { "fp6", FP6 },
3895 { "fp7", FP7 },
3896 { "fpi", FPI },
3897 { "fpiar", FPI },
3898 { "fpc", FPI },
3899 { "fps", FPS },
3900 { "fpsr", FPS },
3901 { "fpc", FPC },
3902 { "fpcr", FPC },
3903 { "control", FPC },
3904 { "status", FPS },
3905 { "iaddr", FPI },
3906
3907 { "cop0", COP0 },
3908 { "cop1", COP1 },
3909 { "cop2", COP2 },
3910 { "cop3", COP3 },
3911 { "cop4", COP4 },
3912 { "cop5", COP5 },
3913 { "cop6", COP6 },
3914 { "cop7", COP7 },
3915 { "pc", PC },
3916 { "zpc", ZPC },
3917 { "sr", SR },
3918
3919 { "ccr", CCR },
3920 { "cc", CCR },
3921
3922 { "acc", ACC },
3923 { "acc0", ACC },
3924 { "acc1", ACC1 },
3925 { "acc2", ACC2 },
3926 { "acc3", ACC3 },
3927 { "accext01", ACCEXT01 },
3928 { "accext23", ACCEXT23 },
3929 { "macsr", MACSR },
3930 { "mask", MASK },
3931
3932 /* Control registers. */
3933 { "sfc", SFC }, /* Source Function Code. */
3934 { "sfcr", SFC },
3935 { "dfc", DFC }, /* Destination Function Code. */
3936 { "dfcr", DFC },
3937 { "cacr", CACR }, /* Cache Control Register. */
3938 { "caar", CAAR }, /* Cache Address Register. */
3939
3940 { "usp", USP }, /* User Stack Pointer. */
3941 { "vbr", VBR }, /* Vector Base Register. */
3942 { "msp", MSP }, /* Master Stack Pointer. */
3943 { "isp", ISP }, /* Interrupt Stack Pointer. */
3944
3945 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3946 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3947 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3948 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
3949
3950 /* 68ec040 versions of same */
3951 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3952 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3953 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3954 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
3955
3956 /* Coldfire versions of same. The ColdFire programmer's reference
3957 manual indicated that the order is 2,3,0,1, but Ken Rose
3958 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3959 { "acr0", ACR0 }, /* Access Control Unit 0. */
3960 { "acr1", ACR1 }, /* Access Control Unit 1. */
3961 { "acr2", ACR2 }, /* Access Control Unit 2. */
3962 { "acr3", ACR3 }, /* Access Control Unit 3. */
3963
3964 { "tc", TC }, /* MMU Translation Control Register. */
3965 { "tcr", TC },
3966 { "asid", ASID },
3967
3968 { "mmusr", MMUSR }, /* MMU Status Register. */
3969 { "srp", SRP }, /* User Root Pointer. */
3970 { "urp", URP }, /* Supervisor Root Pointer. */
3971
3972 { "buscr", BUSCR },
3973 { "mmubar", MMUBAR },
3974 { "pcr", PCR },
3975
3976 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3977 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3978 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3979 { "mbar", MBAR }, /* Module Base Address Register. */
3980
3981 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3982 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3983 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3984 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3985 { "mpcr", MPCR }, /* mcfv4e registers. */
3986 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3987 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3988 { "asid", TC }, /* mcfv4e registers. */
3989 { "mmubar", BUSCR }, /* mcfv4e registers. */
3990 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3991 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3992 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3993 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3994 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3995 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3996 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3997 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3998 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3999 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4000 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4001 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4002
4003 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4004 { "rambar", RAMBAR }, /* mcf528x registers. */
4005
4006 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4007
4008 { "cac", CAC }, /* fido registers. */
4009 { "mbb", MBB }, /* fido registers. */
4010 /* End of control registers. */
4011
4012 { "ac", AC },
4013 { "bc", BC },
4014 { "cal", CAL },
4015 { "crp", CRP },
4016 { "drp", DRP },
4017 { "pcsr", PCSR },
4018 { "psr", PSR },
4019 { "scc", SCC },
4020 { "val", VAL },
4021 { "bad0", BAD0 },
4022 { "bad1", BAD1 },
4023 { "bad2", BAD2 },
4024 { "bad3", BAD3 },
4025 { "bad4", BAD4 },
4026 { "bad5", BAD5 },
4027 { "bad6", BAD6 },
4028 { "bad7", BAD7 },
4029 { "bac0", BAC0 },
4030 { "bac1", BAC1 },
4031 { "bac2", BAC2 },
4032 { "bac3", BAC3 },
4033 { "bac4", BAC4 },
4034 { "bac5", BAC5 },
4035 { "bac6", BAC6 },
4036 { "bac7", BAC7 },
4037
4038 { "ic", IC },
4039 { "dc", DC },
4040 { "nc", NC },
4041
4042 { "tt0", TT0 },
4043 { "tt1", TT1 },
4044 /* 68ec030 versions of same. */
4045 { "ac0", TT0 },
4046 { "ac1", TT1 },
4047 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4048 { "acusr", PSR },
4049
4050 /* Suppressed data and address registers. */
4051 { "zd0", ZDATA0 },
4052 { "zd1", ZDATA1 },
4053 { "zd2", ZDATA2 },
4054 { "zd3", ZDATA3 },
4055 { "zd4", ZDATA4 },
4056 { "zd5", ZDATA5 },
4057 { "zd6", ZDATA6 },
4058 { "zd7", ZDATA7 },
4059 { "za0", ZADDR0 },
4060 { "za1", ZADDR1 },
4061 { "za2", ZADDR2 },
4062 { "za3", ZADDR3 },
4063 { "za4", ZADDR4 },
4064 { "za5", ZADDR5 },
4065 { "za6", ZADDR6 },
4066 { "za7", ZADDR7 },
4067
4068 /* Upper and lower data and address registers, used by macw and msacw. */
4069 { "d0l", DATA0L },
4070 { "d1l", DATA1L },
4071 { "d2l", DATA2L },
4072 { "d3l", DATA3L },
4073 { "d4l", DATA4L },
4074 { "d5l", DATA5L },
4075 { "d6l", DATA6L },
4076 { "d7l", DATA7L },
4077
4078 { "a0l", ADDR0L },
4079 { "a1l", ADDR1L },
4080 { "a2l", ADDR2L },
4081 { "a3l", ADDR3L },
4082 { "a4l", ADDR4L },
4083 { "a5l", ADDR5L },
4084 { "a6l", ADDR6L },
4085 { "a7l", ADDR7L },
4086
4087 { "d0u", DATA0U },
4088 { "d1u", DATA1U },
4089 { "d2u", DATA2U },
4090 { "d3u", DATA3U },
4091 { "d4u", DATA4U },
4092 { "d5u", DATA5U },
4093 { "d6u", DATA6U },
4094 { "d7u", DATA7U },
4095
4096 { "a0u", ADDR0U },
4097 { "a1u", ADDR1U },
4098 { "a2u", ADDR2U },
4099 { "a3u", ADDR3U },
4100 { "a4u", ADDR4U },
4101 { "a5u", ADDR5U },
4102 { "a6u", ADDR6U },
4103 { "a7u", ADDR7U },
4104
4105 { 0, 0 }
4106 };
4107
4108 static void
4109 init_regtable (void)
4110 {
4111 int i;
4112 for (i = 0; init_table[i].name; i++)
4113 insert_reg (init_table[i].name, init_table[i].number);
4114 }
4115
4116 void
4117 md_assemble (char *str)
4118 {
4119 const char *er;
4120 short *fromP;
4121 char *toP = NULL;
4122 int m, n = 0;
4123 char *to_beg_P;
4124 int shorts_this_frag;
4125 fixS *fixP;
4126
4127 if (!selected_cpu && !selected_arch)
4128 {
4129 /* We've not selected an architecture yet. Set the default
4130 now. We do this lazily so that an initial .cpu or .arch directive
4131 can specify. */
4132 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4133 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4134 }
4135 if (!initialized)
4136 m68k_init_arch ();
4137
4138 /* In MRI mode, the instruction and operands are separated by a
4139 space. Anything following the operands is a comment. The label
4140 has already been removed. */
4141 if (flag_mri)
4142 {
4143 char *s;
4144 int fields = 0;
4145 int infield = 0;
4146 int inquote = 0;
4147
4148 for (s = str; *s != '\0'; s++)
4149 {
4150 if ((*s == ' ' || *s == '\t') && ! inquote)
4151 {
4152 if (infield)
4153 {
4154 ++fields;
4155 if (fields >= 2)
4156 {
4157 *s = '\0';
4158 break;
4159 }
4160 infield = 0;
4161 }
4162 }
4163 else
4164 {
4165 if (! infield)
4166 infield = 1;
4167 if (*s == '\'')
4168 inquote = ! inquote;
4169 }
4170 }
4171 }
4172
4173 memset (&the_ins, '\0', sizeof (the_ins));
4174 m68k_ip (str);
4175 er = the_ins.error;
4176 if (!er)
4177 {
4178 for (n = 0; n < the_ins.numargs; n++)
4179 if (the_ins.operands[n].error)
4180 {
4181 er = the_ins.operands[n].error;
4182 break;
4183 }
4184 }
4185 if (er)
4186 {
4187 as_bad (_("%s -- statement `%s' ignored"), er, str);
4188 return;
4189 }
4190
4191 /* If there is a current label, record that it marks an instruction. */
4192 if (current_label != NULL)
4193 {
4194 current_label->text = 1;
4195 current_label = NULL;
4196 }
4197
4198 #ifdef OBJ_ELF
4199 /* Tie dwarf2 debug info to the address at the start of the insn. */
4200 dwarf2_emit_insn (0);
4201 #endif
4202
4203 if (the_ins.nfrag == 0)
4204 {
4205 /* No frag hacking involved; just put it out. */
4206 toP = frag_more (2 * the_ins.numo);
4207 fromP = &the_ins.opcode[0];
4208 for (m = the_ins.numo; m; --m)
4209 {
4210 md_number_to_chars (toP, (long) (*fromP), 2);
4211 toP += 2;
4212 fromP++;
4213 }
4214 /* Put out symbol-dependent info. */
4215 for (m = 0; m < the_ins.nrel; m++)
4216 {
4217 switch (the_ins.reloc[m].wid)
4218 {
4219 case 'B':
4220 n = 1;
4221 break;
4222 case 'b':
4223 n = 1;
4224 break;
4225 case '3':
4226 n = 1;
4227 break;
4228 case 'w':
4229 case 'W':
4230 n = 2;
4231 break;
4232 case 'l':
4233 n = 4;
4234 break;
4235 default:
4236 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4237 the_ins.reloc[m].wid);
4238 }
4239
4240 fixP = fix_new_exp (frag_now,
4241 ((toP - frag_now->fr_literal)
4242 - the_ins.numo * 2 + the_ins.reloc[m].n),
4243 n,
4244 &the_ins.reloc[m].exp,
4245 the_ins.reloc[m].pcrel,
4246 get_reloc_code (n, the_ins.reloc[m].pcrel,
4247 the_ins.reloc[m].pic_reloc));
4248 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4249 if (the_ins.reloc[m].wid == 'B')
4250 fixP->fx_signed = 1;
4251 }
4252 return;
4253 }
4254
4255 /* There's some frag hacking. */
4256 {
4257 /* Calculate the max frag size. */
4258 int wid;
4259
4260 wid = 2 * the_ins.fragb[0].fragoff;
4261 for (n = 1; n < the_ins.nfrag; n++)
4262 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4263 /* frag_var part. */
4264 wid += FRAG_VAR_SIZE;
4265 /* Make sure the whole insn fits in one chunk, in particular that
4266 the var part is attached, as we access one byte before the
4267 variable frag for byte branches. */
4268 frag_grow (wid);
4269 }
4270
4271 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4272 {
4273 int wid;
4274
4275 if (n == 0)
4276 wid = 2 * the_ins.fragb[n].fragoff;
4277 else
4278 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4279 toP = frag_more (wid);
4280 to_beg_P = toP;
4281 shorts_this_frag = 0;
4282 for (m = wid / 2; m; --m)
4283 {
4284 md_number_to_chars (toP, (long) (*fromP), 2);
4285 toP += 2;
4286 fromP++;
4287 shorts_this_frag++;
4288 }
4289 for (m = 0; m < the_ins.nrel; m++)
4290 {
4291 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4292 {
4293 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4294 break;
4295 }
4296 wid = the_ins.reloc[m].wid;
4297 if (wid == 0)
4298 continue;
4299 the_ins.reloc[m].wid = 0;
4300 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4301
4302 fixP = fix_new_exp (frag_now,
4303 ((toP - frag_now->fr_literal)
4304 - the_ins.numo * 2 + the_ins.reloc[m].n),
4305 wid,
4306 &the_ins.reloc[m].exp,
4307 the_ins.reloc[m].pcrel,
4308 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4309 the_ins.reloc[m].pic_reloc));
4310 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4311 }
4312 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4313 (relax_substateT) (the_ins.fragb[n].fragty),
4314 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4315 }
4316 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4317 shorts_this_frag = 0;
4318 if (n)
4319 {
4320 toP = frag_more (n * 2);
4321 while (n--)
4322 {
4323 md_number_to_chars (toP, (long) (*fromP), 2);
4324 toP += 2;
4325 fromP++;
4326 shorts_this_frag++;
4327 }
4328 }
4329 for (m = 0; m < the_ins.nrel; m++)
4330 {
4331 int wid;
4332
4333 wid = the_ins.reloc[m].wid;
4334 if (wid == 0)
4335 continue;
4336 the_ins.reloc[m].wid = 0;
4337 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4338
4339 fixP = fix_new_exp (frag_now,
4340 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4341 - shorts_this_frag * 2),
4342 wid,
4343 &the_ins.reloc[m].exp,
4344 the_ins.reloc[m].pcrel,
4345 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4346 the_ins.reloc[m].pic_reloc));
4347 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4348 }
4349 }
4350
4351 /* Comparison function used by qsort to rank the opcode entries by name. */
4352
4353 static int
4354 m68k_compare_opcode (const void * v1, const void * v2)
4355 {
4356 struct m68k_opcode * op1, * op2;
4357 int ret;
4358
4359 if (v1 == v2)
4360 return 0;
4361
4362 op1 = *(struct m68k_opcode **) v1;
4363 op2 = *(struct m68k_opcode **) v2;
4364
4365 /* Compare the two names. If different, return the comparison.
4366 If the same, return the order they are in the opcode table. */
4367 ret = strcmp (op1->name, op2->name);
4368 if (ret)
4369 return ret;
4370 if (op1 < op2)
4371 return -1;
4372 return 1;
4373 }
4374
4375 void
4376 md_begin (void)
4377 {
4378 const struct m68k_opcode *ins;
4379 struct m68k_incant *hack, *slak;
4380 const char *retval = 0; /* Empty string, or error msg text. */
4381 int i;
4382
4383 /* Set up hash tables with 68000 instructions.
4384 similar to what the vax assembler does. */
4385 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4386 a copy of it at runtime, adding in the information we want but isn't
4387 there. I think it'd be better to have an awk script hack the table
4388 at compile time. Or even just xstr the table and use it as-is. But
4389 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4390 names. */
4391
4392 if (flag_mri)
4393 {
4394 flag_reg_prefix_optional = 1;
4395 m68k_abspcadd = 1;
4396 if (! m68k_rel32_from_cmdline)
4397 m68k_rel32 = 0;
4398 }
4399
4400 /* First sort the opcode table into alphabetical order to seperate
4401 the order that the assembler wants to see the opcodes from the
4402 order that the disassembler wants to see them. */
4403 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4404 if (!m68k_sorted_opcodes)
4405 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
4406 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4407
4408 for (i = m68k_numopcodes; i--;)
4409 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4410
4411 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4412 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4413
4414 op_hash = hash_new ();
4415
4416 obstack_begin (&robyn, 4000);
4417 for (i = 0; i < m68k_numopcodes; i++)
4418 {
4419 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4420 do
4421 {
4422 ins = m68k_sorted_opcodes[i];
4423
4424 /* We must enter all insns into the table, because .arch and
4425 .cpu directives can change things. */
4426 slak->m_operands = ins->args;
4427 slak->m_arch = ins->arch;
4428 slak->m_opcode = ins->opcode;
4429
4430 /* In most cases we can determine the number of opcode words
4431 by checking the second word of the mask. Unfortunately
4432 some instructions have 2 opcode words, but no fixed bits
4433 in the second word. A leading dot in the operands
4434 string also indicates 2 opcodes. */
4435 if (*slak->m_operands == '.')
4436 {
4437 slak->m_operands++;
4438 slak->m_codenum = 2;
4439 }
4440 else if (ins->match & 0xffffL)
4441 slak->m_codenum = 2;
4442 else
4443 slak->m_codenum = 1;
4444 slak->m_opnum = strlen (slak->m_operands) / 2;
4445
4446 if (i + 1 != m68k_numopcodes
4447 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4448 {
4449 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4450 i++;
4451 }
4452 else
4453 slak->m_next = 0;
4454 slak = slak->m_next;
4455 }
4456 while (slak);
4457
4458 retval = hash_insert (op_hash, ins->name, (char *) hack);
4459 if (retval)
4460 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4461 }
4462
4463 for (i = 0; i < m68k_numaliases; i++)
4464 {
4465 const char *name = m68k_opcode_aliases[i].primary;
4466 const char *alias = m68k_opcode_aliases[i].alias;
4467 PTR val = hash_find (op_hash, name);
4468
4469 if (!val)
4470 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4471 retval = hash_insert (op_hash, alias, val);
4472 if (retval)
4473 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4474 }
4475
4476 /* In MRI mode, all unsized branches are variable sized. Normally,
4477 they are word sized. */
4478 if (flag_mri)
4479 {
4480 static struct m68k_opcode_alias mri_aliases[] =
4481 {
4482 { "bhi", "jhi", },
4483 { "bls", "jls", },
4484 { "bcc", "jcc", },
4485 { "bcs", "jcs", },
4486 { "bne", "jne", },
4487 { "beq", "jeq", },
4488 { "bvc", "jvc", },
4489 { "bvs", "jvs", },
4490 { "bpl", "jpl", },
4491 { "bmi", "jmi", },
4492 { "bge", "jge", },
4493 { "blt", "jlt", },
4494 { "bgt", "jgt", },
4495 { "ble", "jle", },
4496 { "bra", "jra", },
4497 { "bsr", "jbsr", },
4498 };
4499
4500 for (i = 0;
4501 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4502 i++)
4503 {
4504 const char *name = mri_aliases[i].primary;
4505 const char *alias = mri_aliases[i].alias;
4506 PTR val = hash_find (op_hash, name);
4507
4508 if (!val)
4509 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4510 retval = hash_jam (op_hash, alias, val);
4511 if (retval)
4512 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4513 }
4514 }
4515
4516 for (i = 0; i < (int) sizeof (notend_table); i++)
4517 {
4518 notend_table[i] = 0;
4519 alt_notend_table[i] = 0;
4520 }
4521
4522 notend_table[','] = 1;
4523 notend_table['{'] = 1;
4524 notend_table['}'] = 1;
4525 alt_notend_table['a'] = 1;
4526 alt_notend_table['A'] = 1;
4527 alt_notend_table['d'] = 1;
4528 alt_notend_table['D'] = 1;
4529 alt_notend_table['#'] = 1;
4530 alt_notend_table['&'] = 1;
4531 alt_notend_table['f'] = 1;
4532 alt_notend_table['F'] = 1;
4533 #ifdef REGISTER_PREFIX
4534 alt_notend_table[REGISTER_PREFIX] = 1;
4535 #endif
4536
4537 /* We need to put '(' in alt_notend_table to handle
4538 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4539 alt_notend_table['('] = 1;
4540
4541 /* We need to put '@' in alt_notend_table to handle
4542 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4543 alt_notend_table['@'] = 1;
4544
4545 /* We need to put digits in alt_notend_table to handle
4546 bfextu %d0{24:1},%d0 */
4547 alt_notend_table['0'] = 1;
4548 alt_notend_table['1'] = 1;
4549 alt_notend_table['2'] = 1;
4550 alt_notend_table['3'] = 1;
4551 alt_notend_table['4'] = 1;
4552 alt_notend_table['5'] = 1;
4553 alt_notend_table['6'] = 1;
4554 alt_notend_table['7'] = 1;
4555 alt_notend_table['8'] = 1;
4556 alt_notend_table['9'] = 1;
4557
4558 #ifndef MIT_SYNTAX_ONLY
4559 /* Insert pseudo ops, these have to go into the opcode table since
4560 gas expects pseudo ops to start with a dot. */
4561 {
4562 int n = 0;
4563
4564 while (mote_pseudo_table[n].poc_name)
4565 {
4566 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4567 hash_insert (op_hash,
4568 mote_pseudo_table[n].poc_name, (char *) hack);
4569 hack->m_operands = 0;
4570 hack->m_opnum = n;
4571 n++;
4572 }
4573 }
4574 #endif
4575
4576 init_regtable ();
4577
4578 #ifdef OBJ_ELF
4579 record_alignment (text_section, 2);
4580 record_alignment (data_section, 2);
4581 record_alignment (bss_section, 2);
4582 #endif
4583 }
4584
4585 \f
4586 /* This is called when a label is defined. */
4587
4588 void
4589 m68k_frob_label (symbolS *sym)
4590 {
4591 struct label_line *n;
4592
4593 n = (struct label_line *) xmalloc (sizeof *n);
4594 n->next = labels;
4595 n->label = sym;
4596 as_where (&n->file, &n->line);
4597 n->text = 0;
4598 labels = n;
4599 current_label = n;
4600
4601 #ifdef OBJ_ELF
4602 dwarf2_emit_label (sym);
4603 #endif
4604 }
4605
4606 /* This is called when a value that is not an instruction is emitted. */
4607
4608 void
4609 m68k_flush_pending_output (void)
4610 {
4611 current_label = NULL;
4612 }
4613
4614 /* This is called at the end of the assembly, when the final value of
4615 the label is known. We warn if this is a text symbol aligned at an
4616 odd location. */
4617
4618 void
4619 m68k_frob_symbol (symbolS *sym)
4620 {
4621 if (S_GET_SEGMENT (sym) == reg_section
4622 && (int) S_GET_VALUE (sym) < 0)
4623 {
4624 S_SET_SEGMENT (sym, absolute_section);
4625 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4626 }
4627 else if ((S_GET_VALUE (sym) & 1) != 0)
4628 {
4629 struct label_line *l;
4630
4631 for (l = labels; l != NULL; l = l->next)
4632 {
4633 if (l->label == sym)
4634 {
4635 if (l->text)
4636 as_warn_where (l->file, l->line,
4637 _("text label `%s' aligned to odd boundary"),
4638 S_GET_NAME (sym));
4639 break;
4640 }
4641 }
4642 }
4643 }
4644 \f
4645 /* This is called if we go in or out of MRI mode because of the .mri
4646 pseudo-op. */
4647
4648 void
4649 m68k_mri_mode_change (int on)
4650 {
4651 if (on)
4652 {
4653 if (! flag_reg_prefix_optional)
4654 {
4655 flag_reg_prefix_optional = 1;
4656 #ifdef REGISTER_PREFIX
4657 init_regtable ();
4658 #endif
4659 }
4660 m68k_abspcadd = 1;
4661 if (! m68k_rel32_from_cmdline)
4662 m68k_rel32 = 0;
4663 }
4664 else
4665 {
4666 if (! reg_prefix_optional_seen)
4667 {
4668 #ifdef REGISTER_PREFIX_OPTIONAL
4669 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4670 #else
4671 flag_reg_prefix_optional = 0;
4672 #endif
4673 #ifdef REGISTER_PREFIX
4674 init_regtable ();
4675 #endif
4676 }
4677 m68k_abspcadd = 0;
4678 if (! m68k_rel32_from_cmdline)
4679 m68k_rel32 = 1;
4680 }
4681 }
4682
4683 /* Equal to MAX_PRECISION in atof-ieee.c. */
4684 #define MAX_LITTLENUMS 6
4685
4686 /* Turn a string in input_line_pointer into a floating point constant
4687 of type TYPE, and store the appropriate bytes in *LITP. The number
4688 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4689 returned, or NULL on OK. */
4690
4691 char *
4692 md_atof (int type, char *litP, int *sizeP)
4693 {
4694 int prec;
4695 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4696 LITTLENUM_TYPE *wordP;
4697 char *t;
4698
4699 switch (type)
4700 {
4701 case 'f':
4702 case 'F':
4703 case 's':
4704 case 'S':
4705 prec = 2;
4706 break;
4707
4708 case 'd':
4709 case 'D':
4710 case 'r':
4711 case 'R':
4712 prec = 4;
4713 break;
4714
4715 case 'x':
4716 case 'X':
4717 prec = 6;
4718 break;
4719
4720 case 'p':
4721 case 'P':
4722 prec = 6;
4723 break;
4724
4725 default:
4726 *sizeP = 0;
4727 return _("Bad call to MD_ATOF()");
4728 }
4729 t = atof_ieee (input_line_pointer, type, words);
4730 if (t)
4731 input_line_pointer = t;
4732
4733 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4734 for (wordP = words; prec--;)
4735 {
4736 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4737 litP += sizeof (LITTLENUM_TYPE);
4738 }
4739 return 0;
4740 }
4741
4742 void
4743 md_number_to_chars (char *buf, valueT val, int n)
4744 {
4745 number_to_chars_bigendian (buf, val, n);
4746 }
4747
4748 void
4749 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4750 {
4751 offsetT val = *valP;
4752 addressT upper_limit;
4753 offsetT lower_limit;
4754
4755 /* This is unnecessary but it convinces the native rs6000 compiler
4756 to generate the code we want. */
4757 char *buf = fixP->fx_frag->fr_literal;
4758 buf += fixP->fx_where;
4759 /* End ibm compiler workaround. */
4760
4761 val = SEXT (val);
4762
4763 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4764 fixP->fx_done = 1;
4765
4766 #ifdef OBJ_ELF
4767 if (fixP->fx_addsy)
4768 {
4769 memset (buf, 0, fixP->fx_size);
4770 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4771
4772 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4773 && !S_IS_DEFINED (fixP->fx_addsy)
4774 && !S_IS_WEAK (fixP->fx_addsy))
4775 S_SET_WEAK (fixP->fx_addsy);
4776 return;
4777 }
4778 #elif defined(OBJ_AOUT)
4779 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
4780 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4781 {
4782 memset (buf, 0, fixP->fx_size);
4783 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4784 return;
4785 }
4786 #endif
4787
4788 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4789 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4790 return;
4791
4792 switch (fixP->fx_size)
4793 {
4794 /* The cast to offsetT below are necessary to make code
4795 correct for machines where ints are smaller than offsetT. */
4796 case 1:
4797 *buf++ = val;
4798 upper_limit = 0x7f;
4799 lower_limit = - (offsetT) 0x80;
4800 break;
4801 case 2:
4802 *buf++ = (val >> 8);
4803 *buf++ = val;
4804 upper_limit = 0x7fff;
4805 lower_limit = - (offsetT) 0x8000;
4806 break;
4807 case 4:
4808 *buf++ = (val >> 24);
4809 *buf++ = (val >> 16);
4810 *buf++ = (val >> 8);
4811 *buf++ = val;
4812 upper_limit = 0x7fffffff;
4813 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4814 break;
4815 default:
4816 BAD_CASE (fixP->fx_size);
4817 }
4818
4819 /* Fix up a negative reloc. */
4820 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4821 {
4822 fixP->fx_addsy = fixP->fx_subsy;
4823 fixP->fx_subsy = NULL;
4824 fixP->fx_tcbit = 1;
4825 }
4826
4827 /* For non-pc-relative values, it's conceivable we might get something
4828 like "0xff" for a byte field. So extend the upper part of the range
4829 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4830 so that we can do any range checking at all. */
4831 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4832 upper_limit = upper_limit * 2 + 1;
4833
4834 if ((addressT) val > upper_limit
4835 && (val > 0 || val < lower_limit))
4836 as_bad_where (fixP->fx_file, fixP->fx_line,
4837 _("value %ld out of range"), (long)val);
4838
4839 /* A one byte PC-relative reloc means a short branch. We can't use
4840 a short branch with a value of 0 or -1, because those indicate
4841 different opcodes (branches with longer offsets). fixup_segment
4842 in write.c may have clobbered fx_pcrel, so we need to examine the
4843 reloc type. */
4844 if ((fixP->fx_pcrel
4845 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4846 && fixP->fx_size == 1
4847 && (fixP->fx_addsy == NULL
4848 || S_IS_DEFINED (fixP->fx_addsy))
4849 && (val == 0 || val == -1))
4850 as_bad_where (fixP->fx_file, fixP->fx_line,
4851 _("invalid byte branch offset"));
4852 }
4853
4854 /* *fragP has been relaxed to its final size, and now needs to have
4855 the bytes inside it modified to conform to the new size There is UGLY
4856 MAGIC here. ..
4857 */
4858 static void
4859 md_convert_frag_1 (fragS *fragP)
4860 {
4861 long disp;
4862 fixS *fixP = NULL;
4863
4864 /* Address in object code of the displacement. */
4865 register int object_address = fragP->fr_fix + fragP->fr_address;
4866
4867 /* Address in gas core of the place to store the displacement. */
4868 /* This convinces the native rs6000 compiler to generate the code we
4869 want. */
4870 register char *buffer_address = fragP->fr_literal;
4871 buffer_address += fragP->fr_fix;
4872 /* End ibm compiler workaround. */
4873
4874 /* The displacement of the address, from current location. */
4875 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4876 disp = (disp + fragP->fr_offset) - object_address;
4877
4878 switch (fragP->fr_subtype)
4879 {
4880 case TAB (BRANCHBWL, BYTE):
4881 case TAB (BRABSJUNC, BYTE):
4882 case TAB (BRABSJCOND, BYTE):
4883 case TAB (BRANCHBW, BYTE):
4884 case TAB (BRANCHBWPL, BYTE):
4885 know (issbyte (disp));
4886 if (disp == 0)
4887 as_bad_where (fragP->fr_file, fragP->fr_line,
4888 _("short branch with zero offset: use :w"));
4889 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4890 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4891 fixP->fx_pcrel_adjust = -1;
4892 break;
4893 case TAB (BRANCHBWL, SHORT):
4894 case TAB (BRABSJUNC, SHORT):
4895 case TAB (BRABSJCOND, SHORT):
4896 case TAB (BRANCHBW, SHORT):
4897 case TAB (BRANCHBWPL, SHORT):
4898 fragP->fr_opcode[1] = 0x00;
4899 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4900 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4901 fragP->fr_fix += 2;
4902 break;
4903 case TAB (BRANCHBWL, LONG):
4904 fragP->fr_opcode[1] = (char) 0xFF;
4905 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4906 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4907 fragP->fr_fix += 4;
4908 break;
4909 case TAB (BRANCHBWPL, LONG):
4910 /* Here we are converting an unconditional branch into a pair of
4911 conditional branches, in order to get the range. */
4912 fragP->fr_opcode[0] = 0x66; /* bne */
4913 fragP->fr_opcode[1] = 0xFF;
4914 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4915 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4916 fixP->fx_file = fragP->fr_file;
4917 fixP->fx_line = fragP->fr_line;
4918 fragP->fr_fix += 4; /* Skip first offset */
4919 buffer_address += 4;
4920 *buffer_address++ = 0x67; /* beq */
4921 *buffer_address++ = 0xff;
4922 fragP->fr_fix += 2; /* Skip second branch opcode */
4923 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4924 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4925 fragP->fr_fix += 4;
4926 break;
4927 case TAB (BRABSJUNC, LONG):
4928 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4929 {
4930 if (flag_keep_pcrel)
4931 as_bad_where (fragP->fr_file, fragP->fr_line,
4932 _("Conversion of PC relative BSR to absolute JSR"));
4933 fragP->fr_opcode[0] = 0x4E;
4934 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4935 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4936 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4937 fragP->fr_fix += 4;
4938 }
4939 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4940 {
4941 if (flag_keep_pcrel)
4942 as_bad_where (fragP->fr_file, fragP->fr_line,
4943 _("Conversion of PC relative branch to absolute jump"));
4944 fragP->fr_opcode[0] = 0x4E;
4945 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
4946 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4947 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4948 fragP->fr_fix += 4;
4949 }
4950 else
4951 {
4952 /* This cannot happen, because jbsr and jbra are the only two
4953 unconditional branches. */
4954 abort ();
4955 }
4956 break;
4957 case TAB (BRABSJCOND, LONG):
4958 if (flag_keep_pcrel)
4959 as_bad_where (fragP->fr_file, fragP->fr_line,
4960 _("Conversion of PC relative conditional branch to absolute jump"));
4961
4962 /* Only Bcc 68000 instructions can come here
4963 Change bcc into b!cc/jmp absl long. */
4964 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4965 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
4966
4967 /* JF: these used to be fr_opcode[2,3], but they may be in a
4968 different frag, in which case referring to them is a no-no.
4969 Only fr_opcode[0,1] are guaranteed to work. */
4970 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4971 *buffer_address++ = (char) 0xf9;
4972 fragP->fr_fix += 2; /* Account for jmp instruction. */
4973 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4974 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4975 fragP->fr_fix += 4;
4976 break;
4977 case TAB (FBRANCH, SHORT):
4978 know ((fragP->fr_opcode[1] & 0x40) == 0);
4979 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4980 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4981 fragP->fr_fix += 2;
4982 break;
4983 case TAB (FBRANCH, LONG):
4984 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
4985 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4986 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4987 fragP->fr_fix += 4;
4988 break;
4989 case TAB (DBCCLBR, SHORT):
4990 case TAB (DBCCABSJ, SHORT):
4991 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4992 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4993 fragP->fr_fix += 2;
4994 break;
4995 case TAB (DBCCLBR, LONG):
4996 /* Only DBcc instructions can come here.
4997 Change dbcc into dbcc/bral.
4998 JF: these used to be fr_opcode[2-7], but that's wrong. */
4999 if (flag_keep_pcrel)
5000 as_bad_where (fragP->fr_file, fragP->fr_line,
5001 _("Conversion of DBcc to absolute jump"));
5002
5003 *buffer_address++ = 0x00; /* Branch offset = 4. */
5004 *buffer_address++ = 0x04;
5005 *buffer_address++ = 0x60; /* Put in bra pc+6. */
5006 *buffer_address++ = 0x06;
5007 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5008 *buffer_address++ = (char) 0xff;
5009
5010 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5011 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5012 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5013 fragP->fr_fix += 4;
5014 break;
5015 case TAB (DBCCABSJ, LONG):
5016 /* Only DBcc instructions can come here.
5017 Change dbcc into dbcc/jmp.
5018 JF: these used to be fr_opcode[2-7], but that's wrong. */
5019 if (flag_keep_pcrel)
5020 as_bad_where (fragP->fr_file, fragP->fr_line,
5021 _("Conversion of PC relative conditional branch to absolute jump"));
5022
5023 *buffer_address++ = 0x00; /* Branch offset = 4. */
5024 *buffer_address++ = 0x04;
5025 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
5026 *buffer_address++ = 0x06;
5027 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
5028 *buffer_address++ = (char) 0xf9;
5029
5030 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5031 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5032 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5033 fragP->fr_fix += 4;
5034 break;
5035 case TAB (PCREL1632, SHORT):
5036 fragP->fr_opcode[1] &= ~0x3F;
5037 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5038 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5039 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5040 fragP->fr_fix += 2;
5041 break;
5042 case TAB (PCREL1632, LONG):
5043 /* Already set to mode 7.3; this indicates: PC indirect with
5044 suppressed index, 32-bit displacement. */
5045 *buffer_address++ = 0x01;
5046 *buffer_address++ = 0x70;
5047 fragP->fr_fix += 2;
5048 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5049 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5050 fixP->fx_pcrel_adjust = 2;
5051 fragP->fr_fix += 4;
5052 break;
5053 case TAB (PCINDEX, BYTE):
5054 assert (fragP->fr_fix >= 2);
5055 buffer_address[-2] &= ~1;
5056 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5057 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5058 fixP->fx_pcrel_adjust = 1;
5059 break;
5060 case TAB (PCINDEX, SHORT):
5061 assert (fragP->fr_fix >= 2);
5062 buffer_address[-2] |= 0x1;
5063 buffer_address[-1] = 0x20;
5064 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5065 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5066 fixP->fx_pcrel_adjust = 2;
5067 fragP->fr_fix += 2;
5068 break;
5069 case TAB (PCINDEX, LONG):
5070 assert (fragP->fr_fix >= 2);
5071 buffer_address[-2] |= 0x1;
5072 buffer_address[-1] = 0x30;
5073 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5074 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5075 fixP->fx_pcrel_adjust = 2;
5076 fragP->fr_fix += 4;
5077 break;
5078 case TAB (ABSTOPCREL, SHORT):
5079 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5080 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5081 fragP->fr_fix += 2;
5082 break;
5083 case TAB (ABSTOPCREL, LONG):
5084 if (flag_keep_pcrel)
5085 as_fatal (_("Conversion of PC relative displacement to absolute"));
5086 /* The thing to do here is force it to ABSOLUTE LONG, since
5087 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5088 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5089 abort ();
5090 fragP->fr_opcode[1] &= ~0x3F;
5091 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5092 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5093 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5094 fragP->fr_fix += 4;
5095 break;
5096 }
5097 if (fixP)
5098 {
5099 fixP->fx_file = fragP->fr_file;
5100 fixP->fx_line = fragP->fr_line;
5101 }
5102 }
5103
5104 void
5105 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5106 segT sec ATTRIBUTE_UNUSED,
5107 fragS *fragP)
5108 {
5109 md_convert_frag_1 (fragP);
5110 }
5111
5112 /* Force truly undefined symbols to their maximum size, and generally set up
5113 the frag list to be relaxed
5114 */
5115 int
5116 md_estimate_size_before_relax (fragS *fragP, segT segment)
5117 {
5118 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5119 switch (fragP->fr_subtype)
5120 {
5121 case TAB (BRANCHBWL, SZ_UNDEF):
5122 case TAB (BRANCHBWPL, SZ_UNDEF):
5123 case TAB (BRABSJUNC, SZ_UNDEF):
5124 case TAB (BRABSJCOND, SZ_UNDEF):
5125 {
5126 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5127 && relaxable_symbol (fragP->fr_symbol))
5128 {
5129 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5130 }
5131 else if (flag_short_refs)
5132 {
5133 /* Symbol is undefined and we want short ref. */
5134 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5135 }
5136 else
5137 {
5138 /* Symbol is still undefined. Make it LONG. */
5139 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5140 }
5141 break;
5142 }
5143
5144 case TAB (BRANCHBW, SZ_UNDEF):
5145 {
5146 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5147 && relaxable_symbol (fragP->fr_symbol))
5148 {
5149 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5150 }
5151 else
5152 {
5153 /* Symbol is undefined and we don't have long branches. */
5154 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5155 }
5156 break;
5157 }
5158
5159 case TAB (FBRANCH, SZ_UNDEF):
5160 case TAB (DBCCLBR, SZ_UNDEF):
5161 case TAB (DBCCABSJ, SZ_UNDEF):
5162 case TAB (PCREL1632, SZ_UNDEF):
5163 {
5164 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5165 && relaxable_symbol (fragP->fr_symbol))
5166 || flag_short_refs)
5167 {
5168 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5169 }
5170 else
5171 {
5172 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5173 }
5174 break;
5175 }
5176
5177 case TAB (PCINDEX, SZ_UNDEF):
5178 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5179 && relaxable_symbol (fragP->fr_symbol)))
5180 {
5181 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5182 }
5183 else
5184 {
5185 fragP->fr_subtype = TAB (PCINDEX, LONG);
5186 }
5187 break;
5188
5189 case TAB (ABSTOPCREL, SZ_UNDEF):
5190 {
5191 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5192 && relaxable_symbol (fragP->fr_symbol)))
5193 {
5194 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5195 }
5196 else
5197 {
5198 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5199 }
5200 break;
5201 }
5202
5203 default:
5204 break;
5205 }
5206
5207 /* Now that SZ_UNDEF are taken care of, check others. */
5208 switch (fragP->fr_subtype)
5209 {
5210 case TAB (BRANCHBWL, BYTE):
5211 case TAB (BRABSJUNC, BYTE):
5212 case TAB (BRABSJCOND, BYTE):
5213 case TAB (BRANCHBW, BYTE):
5214 /* We can't do a short jump to the next instruction, so in that
5215 case we force word mode. If the symbol is at the start of a
5216 frag, and it is the next frag with any data in it (usually
5217 this is just the next frag, but assembler listings may
5218 introduce empty frags), we must use word mode. */
5219 if (fragP->fr_symbol)
5220 {
5221 fragS *sym_frag;
5222
5223 sym_frag = symbol_get_frag (fragP->fr_symbol);
5224 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5225 {
5226 fragS *l;
5227
5228 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5229 if (l->fr_fix != 0)
5230 break;
5231 if (l == sym_frag)
5232 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5233 }
5234 }
5235 break;
5236 default:
5237 break;
5238 }
5239 return md_relax_table[fragP->fr_subtype].rlx_length;
5240 }
5241
5242 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5243 /* the bit-field entries in the relocation_info struct plays hell
5244 with the byte-order problems of cross-assembly. So as a hack,
5245 I added this mach. dependent ri twiddler. Ugly, but it gets
5246 you there. -KWK */
5247 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5248 are symbolnum, most sig. byte first. Last byte is broken up with
5249 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5250 nibble as nuthin. (on Sun 3 at least) */
5251 /* Translate the internal relocation information into target-specific
5252 format. */
5253 #ifdef comment
5254 void
5255 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5256 {
5257 /* This is easy. */
5258 md_number_to_chars (the_bytes, ri->r_address, 4);
5259 /* Now the fun stuff. */
5260 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5261 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5262 the_bytes[6] = ri->r_symbolnum & 0x0ff;
5263 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5264 | ((ri->r_length << 5) & 0x60)
5265 | ((ri->r_extern << 4) & 0x10));
5266 }
5267
5268 #endif
5269
5270 #endif /* OBJ_AOUT or OBJ_BOUT */
5271
5272 #ifndef WORKING_DOT_WORD
5273 int md_short_jump_size = 4;
5274 int md_long_jump_size = 6;
5275
5276 void
5277 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5278 fragS *frag ATTRIBUTE_UNUSED,
5279 symbolS *to_symbol ATTRIBUTE_UNUSED)
5280 {
5281 valueT offset;
5282
5283 offset = to_addr - (from_addr + 2);
5284
5285 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5286 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5287 }
5288
5289 void
5290 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5291 fragS *frag, symbolS *to_symbol)
5292 {
5293 valueT offset;
5294
5295 if (!HAVE_LONG_BRANCH (current_architecture))
5296 {
5297 if (flag_keep_pcrel)
5298 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5299 offset = to_addr - S_GET_VALUE (to_symbol);
5300 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5301 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5302 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5303 0, NO_RELOC);
5304 }
5305 else
5306 {
5307 offset = to_addr - (from_addr + 2);
5308 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5309 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5310 }
5311 }
5312
5313 #endif
5314
5315 /* Different values of OK tell what its OK to return. Things that
5316 aren't OK are an error (what a shock, no?)
5317
5318 0: Everything is OK
5319 10: Absolute 1:8 only
5320 20: Absolute 0:7 only
5321 30: absolute 0:15 only
5322 40: Absolute 0:31 only
5323 50: absolute 0:127 only
5324 55: absolute -64:63 only
5325 60: absolute -128:127 only
5326 65: absolute 0:511 only
5327 70: absolute 0:4095 only
5328 80: absolute -1, 1:7 only
5329 90: No bignums. */
5330
5331 static int
5332 get_num (struct m68k_exp *exp, int ok)
5333 {
5334 if (exp->exp.X_op == O_absent)
5335 {
5336 /* Do the same thing the VAX asm does. */
5337 op (exp) = O_constant;
5338 adds (exp) = 0;
5339 subs (exp) = 0;
5340 offs (exp) = 0;
5341 if (ok == 10)
5342 {
5343 as_warn (_("expression out of range: defaulting to 1"));
5344 offs (exp) = 1;
5345 }
5346 }
5347 else if (exp->exp.X_op == O_constant)
5348 {
5349 switch (ok)
5350 {
5351 case 10:
5352 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5353 {
5354 as_warn (_("expression out of range: defaulting to 1"));
5355 offs (exp) = 1;
5356 }
5357 break;
5358 case 20:
5359 if ((valueT) TRUNC (offs (exp)) > 7)
5360 goto outrange;
5361 break;
5362 case 30:
5363 if ((valueT) TRUNC (offs (exp)) > 15)
5364 goto outrange;
5365 break;
5366 case 40:
5367 if ((valueT) TRUNC (offs (exp)) > 32)
5368 goto outrange;
5369 break;
5370 case 50:
5371 if ((valueT) TRUNC (offs (exp)) > 127)
5372 goto outrange;
5373 break;
5374 case 55:
5375 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5376 goto outrange;
5377 break;
5378 case 60:
5379 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5380 goto outrange;
5381 break;
5382 case 65:
5383 if ((valueT) TRUNC (offs (exp)) > 511)
5384 goto outrange;
5385 break;
5386 case 70:
5387 if ((valueT) TRUNC (offs (exp)) > 4095)
5388 {
5389 outrange:
5390 as_warn (_("expression out of range: defaulting to 0"));
5391 offs (exp) = 0;
5392 }
5393 break;
5394 case 80:
5395 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5396 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5397 {
5398 as_warn (_("expression out of range: defaulting to 1"));
5399 offs (exp) = 1;
5400 }
5401 break;
5402 default:
5403 break;
5404 }
5405 }
5406 else if (exp->exp.X_op == O_big)
5407 {
5408 if (offs (exp) <= 0 /* flonum. */
5409 && (ok == 90 /* no bignums */
5410 || (ok > 10 /* Small-int ranges including 0 ok. */
5411 /* If we have a flonum zero, a zero integer should
5412 do as well (e.g., in moveq). */
5413 && generic_floating_point_number.exponent == 0
5414 && generic_floating_point_number.low[0] == 0)))
5415 {
5416 /* HACK! Turn it into a long. */
5417 LITTLENUM_TYPE words[6];
5418
5419 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5420 op (exp) = O_constant;
5421 adds (exp) = 0;
5422 subs (exp) = 0;
5423 offs (exp) = words[1] | (words[0] << 16);
5424 }
5425 else if (ok != 0)
5426 {
5427 op (exp) = O_constant;
5428 adds (exp) = 0;
5429 subs (exp) = 0;
5430 offs (exp) = (ok == 10) ? 1 : 0;
5431 as_warn (_("Can't deal with expression; defaulting to %ld"),
5432 (long) offs (exp));
5433 }
5434 }
5435 else
5436 {
5437 if (ok >= 10 && ok <= 80)
5438 {
5439 op (exp) = O_constant;
5440 adds (exp) = 0;
5441 subs (exp) = 0;
5442 offs (exp) = (ok == 10) ? 1 : 0;
5443 as_warn (_("Can't deal with expression; defaulting to %ld"),
5444 (long) offs (exp));
5445 }
5446 }
5447
5448 if (exp->size != SIZE_UNSPEC)
5449 {
5450 switch (exp->size)
5451 {
5452 case SIZE_UNSPEC:
5453 case SIZE_LONG:
5454 break;
5455 case SIZE_BYTE:
5456 if (!isbyte (offs (exp)))
5457 as_warn (_("expression doesn't fit in BYTE"));
5458 break;
5459 case SIZE_WORD:
5460 if (!isword (offs (exp)))
5461 as_warn (_("expression doesn't fit in WORD"));
5462 break;
5463 }
5464 }
5465
5466 return offs (exp);
5467 }
5468
5469 /* These are the back-ends for the various machine dependent pseudo-ops. */
5470
5471 static void
5472 s_data1 (int ignore ATTRIBUTE_UNUSED)
5473 {
5474 subseg_set (data_section, 1);
5475 demand_empty_rest_of_line ();
5476 }
5477
5478 static void
5479 s_data2 (int ignore ATTRIBUTE_UNUSED)
5480 {
5481 subseg_set (data_section, 2);
5482 demand_empty_rest_of_line ();
5483 }
5484
5485 static void
5486 s_bss (int ignore ATTRIBUTE_UNUSED)
5487 {
5488 /* We don't support putting frags in the BSS segment, we fake it
5489 by marking in_bss, then looking at s_skip for clues. */
5490
5491 subseg_set (bss_section, 0);
5492 demand_empty_rest_of_line ();
5493 }
5494
5495 static void
5496 s_even (int ignore ATTRIBUTE_UNUSED)
5497 {
5498 register int temp;
5499 register long temp_fill;
5500
5501 temp = 1; /* JF should be 2? */
5502 temp_fill = get_absolute_expression ();
5503 if (!need_pass_2) /* Never make frag if expect extra pass. */
5504 frag_align (temp, (int) temp_fill, 0);
5505 demand_empty_rest_of_line ();
5506 record_alignment (now_seg, temp);
5507 }
5508
5509 static void
5510 s_proc (int ignore ATTRIBUTE_UNUSED)
5511 {
5512 demand_empty_rest_of_line ();
5513 }
5514 \f
5515 /* Pseudo-ops handled for MRI compatibility. */
5516
5517 /* This function returns non-zero if the argument is a conditional
5518 pseudo-op. This is called when checking whether a pending
5519 alignment is needed. */
5520
5521 int
5522 m68k_conditional_pseudoop (pseudo_typeS *pop)
5523 {
5524 return (pop->poc_handler == s_mri_if
5525 || pop->poc_handler == s_mri_else);
5526 }
5527
5528 /* Handle an MRI style chip specification. */
5529
5530 static void
5531 mri_chip (void)
5532 {
5533 char *s;
5534 char c;
5535 int i;
5536
5537 s = input_line_pointer;
5538 /* We can't use get_symbol_end since the processor names are not proper
5539 symbols. */
5540 while (is_part_of_name (c = *input_line_pointer++))
5541 ;
5542 *--input_line_pointer = 0;
5543 for (i = 0; m68k_cpus[i].name; i++)
5544 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5545 break;
5546 if (!m68k_cpus[i].name)
5547 {
5548 as_bad (_("%s: unrecognized processor name"), s);
5549 *input_line_pointer = c;
5550 ignore_rest_of_line ();
5551 return;
5552 }
5553 *input_line_pointer = c;
5554
5555 if (*input_line_pointer == '/')
5556 current_architecture = 0;
5557 else
5558 current_architecture &= m68881 | m68851;
5559 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5560 control_regs = m68k_cpus[i].control_regs;
5561
5562 while (*input_line_pointer == '/')
5563 {
5564 ++input_line_pointer;
5565 s = input_line_pointer;
5566 /* We can't use get_symbol_end since the processor names are not
5567 proper symbols. */
5568 while (is_part_of_name (c = *input_line_pointer++))
5569 ;
5570 *--input_line_pointer = 0;
5571 if (strcmp (s, "68881") == 0)
5572 current_architecture |= m68881;
5573 else if (strcmp (s, "68851") == 0)
5574 current_architecture |= m68851;
5575 *input_line_pointer = c;
5576 }
5577 }
5578
5579 /* The MRI CHIP pseudo-op. */
5580
5581 static void
5582 s_chip (int ignore ATTRIBUTE_UNUSED)
5583 {
5584 char *stop = NULL;
5585 char stopc;
5586
5587 if (flag_mri)
5588 stop = mri_comment_field (&stopc);
5589 mri_chip ();
5590 if (flag_mri)
5591 mri_comment_end (stop, stopc);
5592 demand_empty_rest_of_line ();
5593 }
5594
5595 /* The MRI FOPT pseudo-op. */
5596
5597 static void
5598 s_fopt (int ignore ATTRIBUTE_UNUSED)
5599 {
5600 SKIP_WHITESPACE ();
5601
5602 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5603 {
5604 int temp;
5605
5606 input_line_pointer += 3;
5607 temp = get_absolute_expression ();
5608 if (temp < 0 || temp > 7)
5609 as_bad (_("bad coprocessor id"));
5610 else
5611 m68k_float_copnum = COP0 + temp;
5612 }
5613 else
5614 {
5615 as_bad (_("unrecognized fopt option"));
5616 ignore_rest_of_line ();
5617 return;
5618 }
5619
5620 demand_empty_rest_of_line ();
5621 }
5622
5623 /* The structure used to handle the MRI OPT pseudo-op. */
5624
5625 struct opt_action
5626 {
5627 /* The name of the option. */
5628 const char *name;
5629
5630 /* If this is not NULL, just call this function. The first argument
5631 is the ARG field of this structure, the second argument is
5632 whether the option was negated. */
5633 void (*pfn) (int arg, int on);
5634
5635 /* If this is not NULL, and the PFN field is NULL, set the variable
5636 this points to. Set it to the ARG field if the option was not
5637 negated, and the NOTARG field otherwise. */
5638 int *pvar;
5639
5640 /* The value to pass to PFN or to assign to *PVAR. */
5641 int arg;
5642
5643 /* The value to assign to *PVAR if the option is negated. If PFN is
5644 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5645 the option may not be negated. */
5646 int notarg;
5647 };
5648
5649 /* The table used to handle the MRI OPT pseudo-op. */
5650
5651 static void skip_to_comma (int, int);
5652 static void opt_nest (int, int);
5653 static void opt_chip (int, int);
5654 static void opt_list (int, int);
5655 static void opt_list_symbols (int, int);
5656
5657 static const struct opt_action opt_table[] =
5658 {
5659 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5660
5661 /* We do relaxing, so there is little use for these options. */
5662 { "b", 0, 0, 0, 0 },
5663 { "brs", 0, 0, 0, 0 },
5664 { "brb", 0, 0, 0, 0 },
5665 { "brl", 0, 0, 0, 0 },
5666 { "brw", 0, 0, 0, 0 },
5667
5668 { "c", 0, 0, 0, 0 },
5669 { "cex", 0, 0, 0, 0 },
5670 { "case", 0, &symbols_case_sensitive, 1, 0 },
5671 { "cl", 0, 0, 0, 0 },
5672 { "cre", 0, 0, 0, 0 },
5673 { "d", 0, &flag_keep_locals, 1, 0 },
5674 { "e", 0, 0, 0, 0 },
5675 { "f", 0, &flag_short_refs, 1, 0 },
5676 { "frs", 0, &flag_short_refs, 1, 0 },
5677 { "frl", 0, &flag_short_refs, 0, 1 },
5678 { "g", 0, 0, 0, 0 },
5679 { "i", 0, 0, 0, 0 },
5680 { "m", 0, 0, 0, 0 },
5681 { "mex", 0, 0, 0, 0 },
5682 { "mc", 0, 0, 0, 0 },
5683 { "md", 0, 0, 0, 0 },
5684 { "nest", opt_nest, 0, 0, 0 },
5685 { "next", skip_to_comma, 0, 0, 0 },
5686 { "o", 0, 0, 0, 0 },
5687 { "old", 0, 0, 0, 0 },
5688 { "op", skip_to_comma, 0, 0, 0 },
5689 { "pco", 0, 0, 0, 0 },
5690 { "p", opt_chip, 0, 0, 0 },
5691 { "pcr", 0, 0, 0, 0 },
5692 { "pcs", 0, 0, 0, 0 },
5693 { "r", 0, 0, 0, 0 },
5694 { "quick", 0, &m68k_quick, 1, 0 },
5695 { "rel32", 0, &m68k_rel32, 1, 0 },
5696 { "s", opt_list, 0, 0, 0 },
5697 { "t", opt_list_symbols, 0, 0, 0 },
5698 { "w", 0, &flag_no_warnings, 0, 1 },
5699 { "x", 0, 0, 0, 0 }
5700 };
5701
5702 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5703
5704 /* The MRI OPT pseudo-op. */
5705
5706 static void
5707 s_opt (int ignore ATTRIBUTE_UNUSED)
5708 {
5709 do
5710 {
5711 int t;
5712 char *s;
5713 char c;
5714 int i;
5715 const struct opt_action *o;
5716
5717 SKIP_WHITESPACE ();
5718
5719 t = 1;
5720 if (*input_line_pointer == '-')
5721 {
5722 ++input_line_pointer;
5723 t = 0;
5724 }
5725 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5726 {
5727 input_line_pointer += 2;
5728 t = 0;
5729 }
5730
5731 s = input_line_pointer;
5732 c = get_symbol_end ();
5733
5734 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5735 {
5736 if (strcasecmp (s, o->name) == 0)
5737 {
5738 if (o->pfn)
5739 {
5740 /* Restore input_line_pointer now in case the option
5741 takes arguments. */
5742 *input_line_pointer = c;
5743 (*o->pfn) (o->arg, t);
5744 }
5745 else if (o->pvar != NULL)
5746 {
5747 if (! t && o->arg == o->notarg)
5748 as_bad (_("option `%s' may not be negated"), s);
5749 *input_line_pointer = c;
5750 *o->pvar = t ? o->arg : o->notarg;
5751 }
5752 else
5753 *input_line_pointer = c;
5754 break;
5755 }
5756 }
5757 if (i >= OPTCOUNT)
5758 {
5759 as_bad (_("option `%s' not recognized"), s);
5760 *input_line_pointer = c;
5761 }
5762 }
5763 while (*input_line_pointer++ == ',');
5764
5765 /* Move back to terminating character. */
5766 --input_line_pointer;
5767 demand_empty_rest_of_line ();
5768 }
5769
5770 /* Skip ahead to a comma. This is used for OPT options which we do
5771 not support and which take arguments. */
5772
5773 static void
5774 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5775 {
5776 while (*input_line_pointer != ','
5777 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5778 ++input_line_pointer;
5779 }
5780
5781 /* Handle the OPT NEST=depth option. */
5782
5783 static void
5784 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5785 {
5786 if (*input_line_pointer != '=')
5787 {
5788 as_bad (_("bad format of OPT NEST=depth"));
5789 return;
5790 }
5791
5792 ++input_line_pointer;
5793 max_macro_nest = get_absolute_expression ();
5794 }
5795
5796 /* Handle the OPT P=chip option. */
5797
5798 static void
5799 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5800 {
5801 if (*input_line_pointer != '=')
5802 {
5803 /* This is just OPT P, which we do not support. */
5804 return;
5805 }
5806
5807 ++input_line_pointer;
5808 mri_chip ();
5809 }
5810
5811 /* Handle the OPT S option. */
5812
5813 static void
5814 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5815 {
5816 listing_list (on);
5817 }
5818
5819 /* Handle the OPT T option. */
5820
5821 static void
5822 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5823 {
5824 if (on)
5825 listing |= LISTING_SYMBOLS;
5826 else
5827 listing &= ~LISTING_SYMBOLS;
5828 }
5829
5830 /* Handle the MRI REG pseudo-op. */
5831
5832 static void
5833 s_reg (int ignore ATTRIBUTE_UNUSED)
5834 {
5835 char *s;
5836 int c;
5837 struct m68k_op rop;
5838 int mask;
5839 char *stop = NULL;
5840 char stopc;
5841
5842 if (line_label == NULL)
5843 {
5844 as_bad (_("missing label"));
5845 ignore_rest_of_line ();
5846 return;
5847 }
5848
5849 if (flag_mri)
5850 stop = mri_comment_field (&stopc);
5851
5852 SKIP_WHITESPACE ();
5853
5854 s = input_line_pointer;
5855 while (ISALNUM (*input_line_pointer)
5856 #ifdef REGISTER_PREFIX
5857 || *input_line_pointer == REGISTER_PREFIX
5858 #endif
5859 || *input_line_pointer == '/'
5860 || *input_line_pointer == '-')
5861 ++input_line_pointer;
5862 c = *input_line_pointer;
5863 *input_line_pointer = '\0';
5864
5865 if (m68k_ip_op (s, &rop) != 0)
5866 {
5867 if (rop.error == NULL)
5868 as_bad (_("bad register list"));
5869 else
5870 as_bad (_("bad register list: %s"), rop.error);
5871 *input_line_pointer = c;
5872 ignore_rest_of_line ();
5873 return;
5874 }
5875
5876 *input_line_pointer = c;
5877
5878 if (rop.mode == REGLST)
5879 mask = rop.mask;
5880 else if (rop.mode == DREG)
5881 mask = 1 << (rop.reg - DATA0);
5882 else if (rop.mode == AREG)
5883 mask = 1 << (rop.reg - ADDR0 + 8);
5884 else if (rop.mode == FPREG)
5885 mask = 1 << (rop.reg - FP0 + 16);
5886 else if (rop.mode == CONTROL
5887 && rop.reg == FPI)
5888 mask = 1 << 24;
5889 else if (rop.mode == CONTROL
5890 && rop.reg == FPS)
5891 mask = 1 << 25;
5892 else if (rop.mode == CONTROL
5893 && rop.reg == FPC)
5894 mask = 1 << 26;
5895 else
5896 {
5897 as_bad (_("bad register list"));
5898 ignore_rest_of_line ();
5899 return;
5900 }
5901
5902 S_SET_SEGMENT (line_label, reg_section);
5903 S_SET_VALUE (line_label, ~mask);
5904 symbol_set_frag (line_label, &zero_address_frag);
5905
5906 if (flag_mri)
5907 mri_comment_end (stop, stopc);
5908
5909 demand_empty_rest_of_line ();
5910 }
5911
5912 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5913
5914 struct save_opts
5915 {
5916 struct save_opts *next;
5917 int abspcadd;
5918 int symbols_case_sensitive;
5919 int keep_locals;
5920 int short_refs;
5921 int architecture;
5922 const enum m68k_register *control_regs;
5923 int quick;
5924 int rel32;
5925 int listing;
5926 int no_warnings;
5927 /* FIXME: We don't save OPT S. */
5928 };
5929
5930 /* This variable holds the stack of saved options. */
5931
5932 static struct save_opts *save_stack;
5933
5934 /* The MRI SAVE pseudo-op. */
5935
5936 static void
5937 s_save (int ignore ATTRIBUTE_UNUSED)
5938 {
5939 struct save_opts *s;
5940
5941 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5942 s->abspcadd = m68k_abspcadd;
5943 s->symbols_case_sensitive = symbols_case_sensitive;
5944 s->keep_locals = flag_keep_locals;
5945 s->short_refs = flag_short_refs;
5946 s->architecture = current_architecture;
5947 s->control_regs = control_regs;
5948 s->quick = m68k_quick;
5949 s->rel32 = m68k_rel32;
5950 s->listing = listing;
5951 s->no_warnings = flag_no_warnings;
5952
5953 s->next = save_stack;
5954 save_stack = s;
5955
5956 demand_empty_rest_of_line ();
5957 }
5958
5959 /* The MRI RESTORE pseudo-op. */
5960
5961 static void
5962 s_restore (int ignore ATTRIBUTE_UNUSED)
5963 {
5964 struct save_opts *s;
5965
5966 if (save_stack == NULL)
5967 {
5968 as_bad (_("restore without save"));
5969 ignore_rest_of_line ();
5970 return;
5971 }
5972
5973 s = save_stack;
5974 save_stack = s->next;
5975
5976 m68k_abspcadd = s->abspcadd;
5977 symbols_case_sensitive = s->symbols_case_sensitive;
5978 flag_keep_locals = s->keep_locals;
5979 flag_short_refs = s->short_refs;
5980 current_architecture = s->architecture;
5981 control_regs = s->control_regs;
5982 m68k_quick = s->quick;
5983 m68k_rel32 = s->rel32;
5984 listing = s->listing;
5985 flag_no_warnings = s->no_warnings;
5986
5987 free (s);
5988
5989 demand_empty_rest_of_line ();
5990 }
5991
5992 /* Types of MRI structured control directives. */
5993
5994 enum mri_control_type
5995 {
5996 mri_for,
5997 mri_if,
5998 mri_repeat,
5999 mri_while
6000 };
6001
6002 /* This structure is used to stack the MRI structured control
6003 directives. */
6004
6005 struct mri_control_info
6006 {
6007 /* The directive within which this one is enclosed. */
6008 struct mri_control_info *outer;
6009
6010 /* The type of directive. */
6011 enum mri_control_type type;
6012
6013 /* Whether an ELSE has been in an IF. */
6014 int else_seen;
6015
6016 /* The add or sub statement at the end of a FOR. */
6017 char *incr;
6018
6019 /* The label of the top of a FOR or REPEAT loop. */
6020 char *top;
6021
6022 /* The label to jump to for the next iteration, or the else
6023 expression of a conditional. */
6024 char *next;
6025
6026 /* The label to jump to to break out of the loop, or the label past
6027 the end of a conditional. */
6028 char *bottom;
6029 };
6030
6031 /* The stack of MRI structured control directives. */
6032
6033 static struct mri_control_info *mri_control_stack;
6034
6035 /* The current MRI structured control directive index number, used to
6036 generate label names. */
6037
6038 static int mri_control_index;
6039
6040 /* Assemble an instruction for an MRI structured control directive. */
6041
6042 static void
6043 mri_assemble (char *str)
6044 {
6045 char *s;
6046
6047 /* md_assemble expects the opcode to be in lower case. */
6048 for (s = str; *s != ' ' && *s != '\0'; s++)
6049 *s = TOLOWER (*s);
6050
6051 md_assemble (str);
6052 }
6053
6054 /* Generate a new MRI label structured control directive label name. */
6055
6056 static char *
6057 mri_control_label (void)
6058 {
6059 char *n;
6060
6061 n = (char *) xmalloc (20);
6062 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6063 ++mri_control_index;
6064 return n;
6065 }
6066
6067 /* Create a new MRI structured control directive. */
6068
6069 static struct mri_control_info *
6070 push_mri_control (enum mri_control_type type)
6071 {
6072 struct mri_control_info *n;
6073
6074 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6075
6076 n->type = type;
6077 n->else_seen = 0;
6078 if (type == mri_if || type == mri_while)
6079 n->top = NULL;
6080 else
6081 n->top = mri_control_label ();
6082 n->next = mri_control_label ();
6083 n->bottom = mri_control_label ();
6084
6085 n->outer = mri_control_stack;
6086 mri_control_stack = n;
6087
6088 return n;
6089 }
6090
6091 /* Pop off the stack of MRI structured control directives. */
6092
6093 static void
6094 pop_mri_control (void)
6095 {
6096 struct mri_control_info *n;
6097
6098 n = mri_control_stack;
6099 mri_control_stack = n->outer;
6100 if (n->top != NULL)
6101 free (n->top);
6102 free (n->next);
6103 free (n->bottom);
6104 free (n);
6105 }
6106
6107 /* Recognize a condition code in an MRI structured control expression. */
6108
6109 static int
6110 parse_mri_condition (int *pcc)
6111 {
6112 char c1, c2;
6113
6114 know (*input_line_pointer == '<');
6115
6116 ++input_line_pointer;
6117 c1 = *input_line_pointer++;
6118 c2 = *input_line_pointer++;
6119
6120 if (*input_line_pointer != '>')
6121 {
6122 as_bad (_("syntax error in structured control directive"));
6123 return 0;
6124 }
6125
6126 ++input_line_pointer;
6127 SKIP_WHITESPACE ();
6128
6129 c1 = TOLOWER (c1);
6130 c2 = TOLOWER (c2);
6131
6132 *pcc = (c1 << 8) | c2;
6133
6134 return 1;
6135 }
6136
6137 /* Parse a single operand in an MRI structured control expression. */
6138
6139 static int
6140 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6141 char **rightstart, char **rightstop)
6142 {
6143 char *s;
6144
6145 SKIP_WHITESPACE ();
6146
6147 *pcc = -1;
6148 *leftstart = NULL;
6149 *leftstop = NULL;
6150 *rightstart = NULL;
6151 *rightstop = NULL;
6152
6153 if (*input_line_pointer == '<')
6154 {
6155 /* It's just a condition code. */
6156 return parse_mri_condition (pcc);
6157 }
6158
6159 /* Look ahead for the condition code. */
6160 for (s = input_line_pointer; *s != '\0'; ++s)
6161 {
6162 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6163 break;
6164 }
6165 if (*s == '\0')
6166 {
6167 as_bad (_("missing condition code in structured control directive"));
6168 return 0;
6169 }
6170
6171 *leftstart = input_line_pointer;
6172 *leftstop = s;
6173 if (*leftstop > *leftstart
6174 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6175 --*leftstop;
6176
6177 input_line_pointer = s;
6178 if (! parse_mri_condition (pcc))
6179 return 0;
6180
6181 /* Look ahead for AND or OR or end of line. */
6182 for (s = input_line_pointer; *s != '\0'; ++s)
6183 {
6184 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6185 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6186 ^^^ ^^ */
6187 if ((s == input_line_pointer
6188 || *(s-1) == ' '
6189 || *(s-1) == '\t')
6190 && ((strncasecmp (s, "AND", 3) == 0
6191 && (s[3] == '.' || ! is_part_of_name (s[3])))
6192 || (strncasecmp (s, "OR", 2) == 0
6193 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6194 break;
6195 }
6196
6197 *rightstart = input_line_pointer;
6198 *rightstop = s;
6199 if (*rightstop > *rightstart
6200 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6201 --*rightstop;
6202
6203 input_line_pointer = s;
6204
6205 return 1;
6206 }
6207
6208 #define MCC(b1, b2) (((b1) << 8) | (b2))
6209
6210 /* Swap the sense of a condition. This changes the condition so that
6211 it generates the same result when the operands are swapped. */
6212
6213 static int
6214 swap_mri_condition (int cc)
6215 {
6216 switch (cc)
6217 {
6218 case MCC ('h', 'i'): return MCC ('c', 's');
6219 case MCC ('l', 's'): return MCC ('c', 'c');
6220 /* <HS> is an alias for <CC>. */
6221 case MCC ('h', 's'):
6222 case MCC ('c', 'c'): return MCC ('l', 's');
6223 /* <LO> is an alias for <CS>. */
6224 case MCC ('l', 'o'):
6225 case MCC ('c', 's'): return MCC ('h', 'i');
6226 case MCC ('p', 'l'): return MCC ('m', 'i');
6227 case MCC ('m', 'i'): return MCC ('p', 'l');
6228 case MCC ('g', 'e'): return MCC ('l', 'e');
6229 case MCC ('l', 't'): return MCC ('g', 't');
6230 case MCC ('g', 't'): return MCC ('l', 't');
6231 case MCC ('l', 'e'): return MCC ('g', 'e');
6232 /* Issue a warning for conditions we can not swap. */
6233 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6234 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6235 case MCC ('v', 'c'):
6236 case MCC ('v', 's'):
6237 default :
6238 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6239 (char) (cc >> 8), (char) (cc));
6240 break;
6241 }
6242 return cc;
6243 }
6244
6245 /* Reverse the sense of a condition. */
6246
6247 static int
6248 reverse_mri_condition (int cc)
6249 {
6250 switch (cc)
6251 {
6252 case MCC ('h', 'i'): return MCC ('l', 's');
6253 case MCC ('l', 's'): return MCC ('h', 'i');
6254 /* <HS> is an alias for <CC> */
6255 case MCC ('h', 's'): return MCC ('l', 'o');
6256 case MCC ('c', 'c'): return MCC ('c', 's');
6257 /* <LO> is an alias for <CS> */
6258 case MCC ('l', 'o'): return MCC ('h', 's');
6259 case MCC ('c', 's'): return MCC ('c', 'c');
6260 case MCC ('n', 'e'): return MCC ('e', 'q');
6261 case MCC ('e', 'q'): return MCC ('n', 'e');
6262 case MCC ('v', 'c'): return MCC ('v', 's');
6263 case MCC ('v', 's'): return MCC ('v', 'c');
6264 case MCC ('p', 'l'): return MCC ('m', 'i');
6265 case MCC ('m', 'i'): return MCC ('p', 'l');
6266 case MCC ('g', 'e'): return MCC ('l', 't');
6267 case MCC ('l', 't'): return MCC ('g', 'e');
6268 case MCC ('g', 't'): return MCC ('l', 'e');
6269 case MCC ('l', 'e'): return MCC ('g', 't');
6270 }
6271 return cc;
6272 }
6273
6274 /* Build an MRI structured control expression. This generates test
6275 and branch instructions. It goes to TRUELAB if the condition is
6276 true, and to FALSELAB if the condition is false. Exactly one of
6277 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6278 is the size qualifier for the expression. EXTENT is the size to
6279 use for the branch. */
6280
6281 static void
6282 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6283 char *rightstart, char *rightstop,
6284 const char *truelab, const char *falselab,
6285 int extent)
6286 {
6287 char *buf;
6288 char *s;
6289
6290 if (leftstart != NULL)
6291 {
6292 struct m68k_op leftop, rightop;
6293 char c;
6294
6295 /* Swap the compare operands, if necessary, to produce a legal
6296 m68k compare instruction. Comparing a register operand with
6297 a non-register operand requires the register to be on the
6298 right (cmp, cmpa). Comparing an immediate value with
6299 anything requires the immediate value to be on the left
6300 (cmpi). */
6301
6302 c = *leftstop;
6303 *leftstop = '\0';
6304 (void) m68k_ip_op (leftstart, &leftop);
6305 *leftstop = c;
6306
6307 c = *rightstop;
6308 *rightstop = '\0';
6309 (void) m68k_ip_op (rightstart, &rightop);
6310 *rightstop = c;
6311
6312 if (rightop.mode == IMMED
6313 || ((leftop.mode == DREG || leftop.mode == AREG)
6314 && (rightop.mode != DREG && rightop.mode != AREG)))
6315 {
6316 char *temp;
6317
6318 /* Correct conditional handling:
6319 if #1 <lt> d0 then ;means if (1 < d0)
6320 ...
6321 endi
6322
6323 should assemble to:
6324
6325 cmp #1,d0 if we do *not* swap the operands
6326 bgt true we need the swapped condition!
6327 ble false
6328 true:
6329 ...
6330 false:
6331 */
6332 temp = leftstart;
6333 leftstart = rightstart;
6334 rightstart = temp;
6335 temp = leftstop;
6336 leftstop = rightstop;
6337 rightstop = temp;
6338 }
6339 else
6340 {
6341 cc = swap_mri_condition (cc);
6342 }
6343 }
6344
6345 if (truelab == NULL)
6346 {
6347 cc = reverse_mri_condition (cc);
6348 truelab = falselab;
6349 }
6350
6351 if (leftstart != NULL)
6352 {
6353 buf = (char *) xmalloc (20
6354 + (leftstop - leftstart)
6355 + (rightstop - rightstart));
6356 s = buf;
6357 *s++ = 'c';
6358 *s++ = 'm';
6359 *s++ = 'p';
6360 if (qual != '\0')
6361 *s++ = TOLOWER (qual);
6362 *s++ = ' ';
6363 memcpy (s, leftstart, leftstop - leftstart);
6364 s += leftstop - leftstart;
6365 *s++ = ',';
6366 memcpy (s, rightstart, rightstop - rightstart);
6367 s += rightstop - rightstart;
6368 *s = '\0';
6369 mri_assemble (buf);
6370 free (buf);
6371 }
6372
6373 buf = (char *) xmalloc (20 + strlen (truelab));
6374 s = buf;
6375 *s++ = 'b';
6376 *s++ = cc >> 8;
6377 *s++ = cc & 0xff;
6378 if (extent != '\0')
6379 *s++ = TOLOWER (extent);
6380 *s++ = ' ';
6381 strcpy (s, truelab);
6382 mri_assemble (buf);
6383 free (buf);
6384 }
6385
6386 /* Parse an MRI structured control expression. This generates test
6387 and branch instructions. STOP is where the expression ends. It
6388 goes to TRUELAB if the condition is true, and to FALSELAB if the
6389 condition is false. Exactly one of TRUELAB and FALSELAB will be
6390 NULL, meaning to fall through. QUAL is the size qualifier for the
6391 expression. EXTENT is the size to use for the branch. */
6392
6393 static void
6394 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6395 const char *falselab, int extent)
6396 {
6397 int c;
6398 int cc;
6399 char *leftstart;
6400 char *leftstop;
6401 char *rightstart;
6402 char *rightstop;
6403
6404 c = *stop;
6405 *stop = '\0';
6406
6407 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6408 &rightstart, &rightstop))
6409 {
6410 *stop = c;
6411 return;
6412 }
6413
6414 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6415 {
6416 const char *flab;
6417
6418 if (falselab != NULL)
6419 flab = falselab;
6420 else
6421 flab = mri_control_label ();
6422
6423 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6424 rightstop, (const char *) NULL, flab, extent);
6425
6426 input_line_pointer += 3;
6427 if (*input_line_pointer != '.'
6428 || input_line_pointer[1] == '\0')
6429 qual = '\0';
6430 else
6431 {
6432 qual = input_line_pointer[1];
6433 input_line_pointer += 2;
6434 }
6435
6436 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6437 &rightstart, &rightstop))
6438 {
6439 *stop = c;
6440 return;
6441 }
6442
6443 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6444 rightstop, truelab, falselab, extent);
6445
6446 if (falselab == NULL)
6447 colon (flab);
6448 }
6449 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6450 {
6451 const char *tlab;
6452
6453 if (truelab != NULL)
6454 tlab = truelab;
6455 else
6456 tlab = mri_control_label ();
6457
6458 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6459 rightstop, tlab, (const char *) NULL, extent);
6460
6461 input_line_pointer += 2;
6462 if (*input_line_pointer != '.'
6463 || input_line_pointer[1] == '\0')
6464 qual = '\0';
6465 else
6466 {
6467 qual = input_line_pointer[1];
6468 input_line_pointer += 2;
6469 }
6470
6471 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6472 &rightstart, &rightstop))
6473 {
6474 *stop = c;
6475 return;
6476 }
6477
6478 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6479 rightstop, truelab, falselab, extent);
6480
6481 if (truelab == NULL)
6482 colon (tlab);
6483 }
6484 else
6485 {
6486 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6487 rightstop, truelab, falselab, extent);
6488 }
6489
6490 *stop = c;
6491 if (input_line_pointer != stop)
6492 as_bad (_("syntax error in structured control directive"));
6493 }
6494
6495 /* Handle the MRI IF pseudo-op. This may be a structured control
6496 directive, or it may be a regular assembler conditional, depending
6497 on its operands. */
6498
6499 static void
6500 s_mri_if (int qual)
6501 {
6502 char *s;
6503 int c;
6504 struct mri_control_info *n;
6505
6506 /* A structured control directive must end with THEN with an
6507 optional qualifier. */
6508 s = input_line_pointer;
6509 /* We only accept '*' as introduction of comments if preceded by white space
6510 or at first column of a line (I think this can't actually happen here?)
6511 This is important when assembling:
6512 if d0 <ne> 12(a0,d0*2) then
6513 if d0 <ne> #CONST*20 then. */
6514 while (! (is_end_of_line[(unsigned char) *s]
6515 || (flag_mri
6516 && *s == '*'
6517 && (s == input_line_pointer
6518 || *(s-1) == ' '
6519 || *(s-1) == '\t'))))
6520 ++s;
6521 --s;
6522 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6523 --s;
6524
6525 if (s - input_line_pointer > 1
6526 && s[-1] == '.')
6527 s -= 2;
6528
6529 if (s - input_line_pointer < 3
6530 || strncasecmp (s - 3, "THEN", 4) != 0)
6531 {
6532 if (qual != '\0')
6533 {
6534 as_bad (_("missing then"));
6535 ignore_rest_of_line ();
6536 return;
6537 }
6538
6539 /* It's a conditional. */
6540 s_if (O_ne);
6541 return;
6542 }
6543
6544 /* Since this might be a conditional if, this pseudo-op will be
6545 called even if we are supported to be ignoring input. Double
6546 check now. Clobber *input_line_pointer so that ignore_input
6547 thinks that this is not a special pseudo-op. */
6548 c = *input_line_pointer;
6549 *input_line_pointer = 0;
6550 if (ignore_input ())
6551 {
6552 *input_line_pointer = c;
6553 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6554 ++input_line_pointer;
6555 demand_empty_rest_of_line ();
6556 return;
6557 }
6558 *input_line_pointer = c;
6559
6560 n = push_mri_control (mri_if);
6561
6562 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6563 n->next, s[1] == '.' ? s[2] : '\0');
6564
6565 if (s[1] == '.')
6566 input_line_pointer = s + 3;
6567 else
6568 input_line_pointer = s + 1;
6569
6570 if (flag_mri)
6571 {
6572 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6573 ++input_line_pointer;
6574 }
6575
6576 demand_empty_rest_of_line ();
6577 }
6578
6579 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6580 structured IF, associate the ELSE with the IF. Otherwise, assume
6581 it is a conditional else. */
6582
6583 static void
6584 s_mri_else (int qual)
6585 {
6586 int c;
6587 char *buf;
6588 char q[2];
6589
6590 if (qual == '\0'
6591 && (mri_control_stack == NULL
6592 || mri_control_stack->type != mri_if
6593 || mri_control_stack->else_seen))
6594 {
6595 s_else (0);
6596 return;
6597 }
6598
6599 c = *input_line_pointer;
6600 *input_line_pointer = 0;
6601 if (ignore_input ())
6602 {
6603 *input_line_pointer = c;
6604 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6605 ++input_line_pointer;
6606 demand_empty_rest_of_line ();
6607 return;
6608 }
6609 *input_line_pointer = c;
6610
6611 if (mri_control_stack == NULL
6612 || mri_control_stack->type != mri_if
6613 || mri_control_stack->else_seen)
6614 {
6615 as_bad (_("else without matching if"));
6616 ignore_rest_of_line ();
6617 return;
6618 }
6619
6620 mri_control_stack->else_seen = 1;
6621
6622 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6623 q[0] = TOLOWER (qual);
6624 q[1] = '\0';
6625 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6626 mri_assemble (buf);
6627 free (buf);
6628
6629 colon (mri_control_stack->next);
6630
6631 if (flag_mri)
6632 {
6633 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6634 ++input_line_pointer;
6635 }
6636
6637 demand_empty_rest_of_line ();
6638 }
6639
6640 /* Handle the MRI ENDI pseudo-op. */
6641
6642 static void
6643 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6644 {
6645 if (mri_control_stack == NULL
6646 || mri_control_stack->type != mri_if)
6647 {
6648 as_bad (_("endi without matching if"));
6649 ignore_rest_of_line ();
6650 return;
6651 }
6652
6653 /* ignore_input will not return true for ENDI, so we don't need to
6654 worry about checking it again here. */
6655
6656 if (! mri_control_stack->else_seen)
6657 colon (mri_control_stack->next);
6658 colon (mri_control_stack->bottom);
6659
6660 pop_mri_control ();
6661
6662 if (flag_mri)
6663 {
6664 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6665 ++input_line_pointer;
6666 }
6667
6668 demand_empty_rest_of_line ();
6669 }
6670
6671 /* Handle the MRI BREAK pseudo-op. */
6672
6673 static void
6674 s_mri_break (int extent)
6675 {
6676 struct mri_control_info *n;
6677 char *buf;
6678 char ex[2];
6679
6680 n = mri_control_stack;
6681 while (n != NULL
6682 && n->type != mri_for
6683 && n->type != mri_repeat
6684 && n->type != mri_while)
6685 n = n->outer;
6686 if (n == NULL)
6687 {
6688 as_bad (_("break outside of structured loop"));
6689 ignore_rest_of_line ();
6690 return;
6691 }
6692
6693 buf = (char *) xmalloc (20 + strlen (n->bottom));
6694 ex[0] = TOLOWER (extent);
6695 ex[1] = '\0';
6696 sprintf (buf, "bra%s %s", ex, n->bottom);
6697 mri_assemble (buf);
6698 free (buf);
6699
6700 if (flag_mri)
6701 {
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6703 ++input_line_pointer;
6704 }
6705
6706 demand_empty_rest_of_line ();
6707 }
6708
6709 /* Handle the MRI NEXT pseudo-op. */
6710
6711 static void
6712 s_mri_next (int extent)
6713 {
6714 struct mri_control_info *n;
6715 char *buf;
6716 char ex[2];
6717
6718 n = mri_control_stack;
6719 while (n != NULL
6720 && n->type != mri_for
6721 && n->type != mri_repeat
6722 && n->type != mri_while)
6723 n = n->outer;
6724 if (n == NULL)
6725 {
6726 as_bad (_("next outside of structured loop"));
6727 ignore_rest_of_line ();
6728 return;
6729 }
6730
6731 buf = (char *) xmalloc (20 + strlen (n->next));
6732 ex[0] = TOLOWER (extent);
6733 ex[1] = '\0';
6734 sprintf (buf, "bra%s %s", ex, n->next);
6735 mri_assemble (buf);
6736 free (buf);
6737
6738 if (flag_mri)
6739 {
6740 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6741 ++input_line_pointer;
6742 }
6743
6744 demand_empty_rest_of_line ();
6745 }
6746
6747 /* Handle the MRI FOR pseudo-op. */
6748
6749 static void
6750 s_mri_for (int qual)
6751 {
6752 const char *varstart, *varstop;
6753 const char *initstart, *initstop;
6754 const char *endstart, *endstop;
6755 const char *bystart, *bystop;
6756 int up;
6757 int by;
6758 int extent;
6759 struct mri_control_info *n;
6760 char *buf;
6761 char *s;
6762 char ex[2];
6763
6764 /* The syntax is
6765 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6766 */
6767
6768 SKIP_WHITESPACE ();
6769 varstart = input_line_pointer;
6770
6771 /* Look for the '='. */
6772 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6773 && *input_line_pointer != '=')
6774 ++input_line_pointer;
6775 if (*input_line_pointer != '=')
6776 {
6777 as_bad (_("missing ="));
6778 ignore_rest_of_line ();
6779 return;
6780 }
6781
6782 varstop = input_line_pointer;
6783 if (varstop > varstart
6784 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6785 --varstop;
6786
6787 ++input_line_pointer;
6788
6789 initstart = input_line_pointer;
6790
6791 /* Look for TO or DOWNTO. */
6792 up = 1;
6793 initstop = NULL;
6794 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6795 {
6796 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6797 && ! is_part_of_name (input_line_pointer[2]))
6798 {
6799 initstop = input_line_pointer;
6800 input_line_pointer += 2;
6801 break;
6802 }
6803 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6804 && ! is_part_of_name (input_line_pointer[6]))
6805 {
6806 initstop = input_line_pointer;
6807 up = 0;
6808 input_line_pointer += 6;
6809 break;
6810 }
6811 ++input_line_pointer;
6812 }
6813 if (initstop == NULL)
6814 {
6815 as_bad (_("missing to or downto"));
6816 ignore_rest_of_line ();
6817 return;
6818 }
6819 if (initstop > initstart
6820 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6821 --initstop;
6822
6823 SKIP_WHITESPACE ();
6824 endstart = input_line_pointer;
6825
6826 /* Look for BY or DO. */
6827 by = 0;
6828 endstop = NULL;
6829 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6830 {
6831 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6832 && ! is_part_of_name (input_line_pointer[2]))
6833 {
6834 endstop = input_line_pointer;
6835 by = 1;
6836 input_line_pointer += 2;
6837 break;
6838 }
6839 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6840 && (input_line_pointer[2] == '.'
6841 || ! is_part_of_name (input_line_pointer[2])))
6842 {
6843 endstop = input_line_pointer;
6844 input_line_pointer += 2;
6845 break;
6846 }
6847 ++input_line_pointer;
6848 }
6849 if (endstop == NULL)
6850 {
6851 as_bad (_("missing do"));
6852 ignore_rest_of_line ();
6853 return;
6854 }
6855 if (endstop > endstart
6856 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6857 --endstop;
6858
6859 if (! by)
6860 {
6861 bystart = "#1";
6862 bystop = bystart + 2;
6863 }
6864 else
6865 {
6866 SKIP_WHITESPACE ();
6867 bystart = input_line_pointer;
6868
6869 /* Look for DO. */
6870 bystop = NULL;
6871 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6872 {
6873 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6874 && (input_line_pointer[2] == '.'
6875 || ! is_part_of_name (input_line_pointer[2])))
6876 {
6877 bystop = input_line_pointer;
6878 input_line_pointer += 2;
6879 break;
6880 }
6881 ++input_line_pointer;
6882 }
6883 if (bystop == NULL)
6884 {
6885 as_bad (_("missing do"));
6886 ignore_rest_of_line ();
6887 return;
6888 }
6889 if (bystop > bystart
6890 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6891 --bystop;
6892 }
6893
6894 if (*input_line_pointer != '.')
6895 extent = '\0';
6896 else
6897 {
6898 extent = input_line_pointer[1];
6899 input_line_pointer += 2;
6900 }
6901
6902 /* We have fully parsed the FOR operands. Now build the loop. */
6903 n = push_mri_control (mri_for);
6904
6905 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6906
6907 /* Move init,var. */
6908 s = buf;
6909 *s++ = 'm';
6910 *s++ = 'o';
6911 *s++ = 'v';
6912 *s++ = 'e';
6913 if (qual != '\0')
6914 *s++ = TOLOWER (qual);
6915 *s++ = ' ';
6916 memcpy (s, initstart, initstop - initstart);
6917 s += initstop - initstart;
6918 *s++ = ',';
6919 memcpy (s, varstart, varstop - varstart);
6920 s += varstop - varstart;
6921 *s = '\0';
6922 mri_assemble (buf);
6923
6924 colon (n->top);
6925
6926 /* cmp end,var. */
6927 s = buf;
6928 *s++ = 'c';
6929 *s++ = 'm';
6930 *s++ = 'p';
6931 if (qual != '\0')
6932 *s++ = TOLOWER (qual);
6933 *s++ = ' ';
6934 memcpy (s, endstart, endstop - endstart);
6935 s += endstop - endstart;
6936 *s++ = ',';
6937 memcpy (s, varstart, varstop - varstart);
6938 s += varstop - varstart;
6939 *s = '\0';
6940 mri_assemble (buf);
6941
6942 /* bcc bottom. */
6943 ex[0] = TOLOWER (extent);
6944 ex[1] = '\0';
6945 if (up)
6946 sprintf (buf, "blt%s %s", ex, n->bottom);
6947 else
6948 sprintf (buf, "bgt%s %s", ex, n->bottom);
6949 mri_assemble (buf);
6950
6951 /* Put together the add or sub instruction used by ENDF. */
6952 s = buf;
6953 if (up)
6954 strcpy (s, "add");
6955 else
6956 strcpy (s, "sub");
6957 s += 3;
6958 if (qual != '\0')
6959 *s++ = TOLOWER (qual);
6960 *s++ = ' ';
6961 memcpy (s, bystart, bystop - bystart);
6962 s += bystop - bystart;
6963 *s++ = ',';
6964 memcpy (s, varstart, varstop - varstart);
6965 s += varstop - varstart;
6966 *s = '\0';
6967 n->incr = buf;
6968
6969 if (flag_mri)
6970 {
6971 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6972 ++input_line_pointer;
6973 }
6974
6975 demand_empty_rest_of_line ();
6976 }
6977
6978 /* Handle the MRI ENDF pseudo-op. */
6979
6980 static void
6981 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
6982 {
6983 if (mri_control_stack == NULL
6984 || mri_control_stack->type != mri_for)
6985 {
6986 as_bad (_("endf without for"));
6987 ignore_rest_of_line ();
6988 return;
6989 }
6990
6991 colon (mri_control_stack->next);
6992
6993 mri_assemble (mri_control_stack->incr);
6994
6995 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6996 mri_assemble (mri_control_stack->incr);
6997
6998 free (mri_control_stack->incr);
6999
7000 colon (mri_control_stack->bottom);
7001
7002 pop_mri_control ();
7003
7004 if (flag_mri)
7005 {
7006 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7007 ++input_line_pointer;
7008 }
7009
7010 demand_empty_rest_of_line ();
7011 }
7012
7013 /* Handle the MRI REPEAT pseudo-op. */
7014
7015 static void
7016 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7017 {
7018 struct mri_control_info *n;
7019
7020 n = push_mri_control (mri_repeat);
7021 colon (n->top);
7022 if (flag_mri)
7023 {
7024 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7025 ++input_line_pointer;
7026 }
7027 demand_empty_rest_of_line ();
7028 }
7029
7030 /* Handle the MRI UNTIL pseudo-op. */
7031
7032 static void
7033 s_mri_until (int qual)
7034 {
7035 char *s;
7036
7037 if (mri_control_stack == NULL
7038 || mri_control_stack->type != mri_repeat)
7039 {
7040 as_bad (_("until without repeat"));
7041 ignore_rest_of_line ();
7042 return;
7043 }
7044
7045 colon (mri_control_stack->next);
7046
7047 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7048 ;
7049
7050 parse_mri_control_expression (s, qual, (const char *) NULL,
7051 mri_control_stack->top, '\0');
7052
7053 colon (mri_control_stack->bottom);
7054
7055 input_line_pointer = s;
7056
7057 pop_mri_control ();
7058
7059 if (flag_mri)
7060 {
7061 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7062 ++input_line_pointer;
7063 }
7064
7065 demand_empty_rest_of_line ();
7066 }
7067
7068 /* Handle the MRI WHILE pseudo-op. */
7069
7070 static void
7071 s_mri_while (int qual)
7072 {
7073 char *s;
7074
7075 struct mri_control_info *n;
7076
7077 s = input_line_pointer;
7078 /* We only accept '*' as introduction of comments if preceded by white space
7079 or at first column of a line (I think this can't actually happen here?)
7080 This is important when assembling:
7081 while d0 <ne> 12(a0,d0*2) do
7082 while d0 <ne> #CONST*20 do. */
7083 while (! (is_end_of_line[(unsigned char) *s]
7084 || (flag_mri
7085 && *s == '*'
7086 && (s == input_line_pointer
7087 || *(s-1) == ' '
7088 || *(s-1) == '\t'))))
7089 s++;
7090 --s;
7091 while (*s == ' ' || *s == '\t')
7092 --s;
7093 if (s - input_line_pointer > 1
7094 && s[-1] == '.')
7095 s -= 2;
7096 if (s - input_line_pointer < 2
7097 || strncasecmp (s - 1, "DO", 2) != 0)
7098 {
7099 as_bad (_("missing do"));
7100 ignore_rest_of_line ();
7101 return;
7102 }
7103
7104 n = push_mri_control (mri_while);
7105
7106 colon (n->next);
7107
7108 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7109 s[1] == '.' ? s[2] : '\0');
7110
7111 input_line_pointer = s + 1;
7112 if (*input_line_pointer == '.')
7113 input_line_pointer += 2;
7114
7115 if (flag_mri)
7116 {
7117 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7118 ++input_line_pointer;
7119 }
7120
7121 demand_empty_rest_of_line ();
7122 }
7123
7124 /* Handle the MRI ENDW pseudo-op. */
7125
7126 static void
7127 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7128 {
7129 char *buf;
7130
7131 if (mri_control_stack == NULL
7132 || mri_control_stack->type != mri_while)
7133 {
7134 as_bad (_("endw without while"));
7135 ignore_rest_of_line ();
7136 return;
7137 }
7138
7139 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7140 sprintf (buf, "bra %s", mri_control_stack->next);
7141 mri_assemble (buf);
7142 free (buf);
7143
7144 colon (mri_control_stack->bottom);
7145
7146 pop_mri_control ();
7147
7148 if (flag_mri)
7149 {
7150 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7151 ++input_line_pointer;
7152 }
7153
7154 demand_empty_rest_of_line ();
7155 }
7156 \f
7157 /* Parse a .cpu directive. */
7158
7159 static void
7160 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7161 {
7162 char saved_char;
7163 char *name;
7164
7165 if (initialized)
7166 {
7167 as_bad (_("already assembled instructions"));
7168 ignore_rest_of_line ();
7169 return;
7170 }
7171
7172 name = input_line_pointer;
7173 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7174 input_line_pointer++;
7175 saved_char = *input_line_pointer;
7176 *input_line_pointer = 0;
7177
7178 m68k_set_cpu (name, 1, 0);
7179
7180 *input_line_pointer = saved_char;
7181 demand_empty_rest_of_line ();
7182 return;
7183 }
7184
7185 /* Parse a .arch directive. */
7186
7187 static void
7188 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7189 {
7190 char saved_char;
7191 char *name;
7192
7193 if (initialized)
7194 {
7195 as_bad (_("already assembled instructions"));
7196 ignore_rest_of_line ();
7197 return;
7198 }
7199
7200 name = input_line_pointer;
7201 while (*input_line_pointer && *input_line_pointer != ','
7202 && !ISSPACE (*input_line_pointer))
7203 input_line_pointer++;
7204 saved_char = *input_line_pointer;
7205 *input_line_pointer = 0;
7206
7207 if (m68k_set_arch (name, 1, 0))
7208 {
7209 /* Scan extensions. */
7210 do
7211 {
7212 *input_line_pointer++ = saved_char;
7213 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7214 break;
7215 name = input_line_pointer;
7216 while (*input_line_pointer && *input_line_pointer != ','
7217 && !ISSPACE (*input_line_pointer))
7218 input_line_pointer++;
7219 saved_char = *input_line_pointer;
7220 *input_line_pointer = 0;
7221 }
7222 while (m68k_set_extension (name, 1, 0));
7223 }
7224
7225 *input_line_pointer = saved_char;
7226 demand_empty_rest_of_line ();
7227 return;
7228 }
7229 \f
7230 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7231 if none is found, the caller is responsible for emitting an error
7232 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7233 cpu name, if it begins with a '6' (possibly skipping an intervening
7234 'c'. We also allow a 'c' in the same place. if NEGATED is
7235 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7236 the option is indeed negated. */
7237
7238 static const struct m68k_cpu *
7239 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7240 int allow_m, int *negated)
7241 {
7242 /* allow negated value? */
7243 if (negated)
7244 {
7245 *negated = 0;
7246
7247 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7248 {
7249 arg += 3;
7250 *negated = 1;
7251 }
7252 }
7253
7254 /* Remove 'm' or 'mc' prefix from 68k variants. */
7255 if (allow_m)
7256 {
7257 if (arg[0] == 'm')
7258 {
7259 if (arg[1] == '6')
7260 arg += 1;
7261 else if (arg[1] == 'c' && arg[2] == '6')
7262 arg += 2;
7263 }
7264 }
7265 else if (arg[0] == 'c' && arg[1] == '6')
7266 arg += 1;
7267
7268 for (; table->name; table++)
7269 if (!strcmp (arg, table->name))
7270 {
7271 if (table->alias < -1 || table->alias > 1)
7272 as_bad (_("`%s' is deprecated, use `%s'"),
7273 table->name, table[table->alias < 0 ? 1 : -1].name);
7274 return table;
7275 }
7276 return 0;
7277 }
7278
7279 /* Set the cpu, issuing errors if it is unrecognized, or invalid */
7280
7281 static int
7282 m68k_set_cpu (char const *name, int allow_m, int silent)
7283 {
7284 const struct m68k_cpu *cpu;
7285
7286 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7287
7288 if (!cpu)
7289 {
7290 if (!silent)
7291 as_bad (_("cpu `%s' unrecognized"), name);
7292 return 0;
7293 }
7294
7295 if (selected_cpu && selected_cpu != cpu)
7296 {
7297 as_bad (_("already selected `%s' processor"),
7298 selected_cpu->name);
7299 return 0;
7300 }
7301 selected_cpu = cpu;
7302 return 1;
7303 }
7304
7305 /* Set the architecture, issuing errors if it is unrecognized, or invalid */
7306
7307 static int
7308 m68k_set_arch (char const *name, int allow_m, int silent)
7309 {
7310 const struct m68k_cpu *arch;
7311
7312 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7313
7314 if (!arch)
7315 {
7316 if (!silent)
7317 as_bad (_("architecture `%s' unrecognized"), name);
7318 return 0;
7319 }
7320
7321 if (selected_arch && selected_arch != arch)
7322 {
7323 as_bad (_("already selected `%s' architecture"),
7324 selected_arch->name);
7325 return 0;
7326 }
7327
7328 selected_arch = arch;
7329 return 1;
7330 }
7331
7332 /* Set the architecture extension, issuing errors if it is
7333 unrecognized, or invalid */
7334
7335 static int
7336 m68k_set_extension (char const *name, int allow_m, int silent)
7337 {
7338 int negated;
7339 const struct m68k_cpu *ext;
7340
7341 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7342
7343 if (!ext)
7344 {
7345 if (!silent)
7346 as_bad (_("extension `%s' unrecognized"), name);
7347 return 0;
7348 }
7349
7350 if (negated)
7351 not_current_architecture |= ext->arch;
7352 else
7353 current_architecture |= ext->arch;
7354 return 1;
7355 }
7356
7357 /* md_parse_option
7358 Invocation line includes a switch not recognized by the base assembler.
7359 */
7360
7361 #ifdef OBJ_ELF
7362 const char *md_shortopts = "lSA:m:kQ:V";
7363 #else
7364 const char *md_shortopts = "lSA:m:k";
7365 #endif
7366
7367 struct option md_longopts[] = {
7368 #define OPTION_PIC (OPTION_MD_BASE)
7369 {"pic", no_argument, NULL, OPTION_PIC},
7370 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7371 {"register-prefix-optional", no_argument, NULL,
7372 OPTION_REGISTER_PREFIX_OPTIONAL},
7373 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7374 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7375 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7376 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7377 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7378 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7379 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7380 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7381 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7382 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7383 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7384 {"pcrel", no_argument, NULL, OPTION_PCREL},
7385 {NULL, no_argument, NULL, 0}
7386 };
7387 size_t md_longopts_size = sizeof (md_longopts);
7388
7389 int
7390 md_parse_option (int c, char *arg)
7391 {
7392 switch (c)
7393 {
7394 case 'l': /* -l means keep external to 2 bit offset
7395 rather than 16 bit one. */
7396 flag_short_refs = 1;
7397 break;
7398
7399 case 'S': /* -S means that jbsr's always turn into
7400 jsr's. */
7401 flag_long_jumps = 1;
7402 break;
7403
7404 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7405 branches into absolute jumps. */
7406 flag_keep_pcrel = 1;
7407 break;
7408
7409 case OPTION_PIC:
7410 case 'k':
7411 flag_want_pic = 1;
7412 break; /* -pic, Position Independent Code. */
7413
7414 case OPTION_REGISTER_PREFIX_OPTIONAL:
7415 flag_reg_prefix_optional = 1;
7416 reg_prefix_optional_seen = 1;
7417 break;
7418
7419 /* -V: SVR4 argument to print version ID. */
7420 case 'V':
7421 print_version_id ();
7422 break;
7423
7424 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7425 should be emitted or not. FIXME: Not implemented. */
7426 case 'Q':
7427 break;
7428
7429 case OPTION_BITWISE_OR:
7430 {
7431 char *n, *t;
7432 const char *s;
7433
7434 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7435 t = n;
7436 for (s = m68k_comment_chars; *s != '\0'; s++)
7437 if (*s != '|')
7438 *t++ = *s;
7439 *t = '\0';
7440 m68k_comment_chars = n;
7441 }
7442 break;
7443
7444 case OPTION_BASE_SIZE_DEFAULT_16:
7445 m68k_index_width_default = SIZE_WORD;
7446 break;
7447
7448 case OPTION_BASE_SIZE_DEFAULT_32:
7449 m68k_index_width_default = SIZE_LONG;
7450 break;
7451
7452 case OPTION_DISP_SIZE_DEFAULT_16:
7453 m68k_rel32 = 0;
7454 m68k_rel32_from_cmdline = 1;
7455 break;
7456
7457 case OPTION_DISP_SIZE_DEFAULT_32:
7458 m68k_rel32 = 1;
7459 m68k_rel32_from_cmdline = 1;
7460 break;
7461
7462 case 'A':
7463 #if WARN_DEPRECATED
7464 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7465 arg, arg));
7466 #endif
7467 /* Intentional fall-through. */
7468 case 'm':
7469 if (!strncmp (arg, "arch=", 5))
7470 m68k_set_arch (arg + 5, 1, 0);
7471 else if (!strncmp (arg, "cpu=", 4))
7472 m68k_set_cpu (arg + 4, 1, 0);
7473 else if (m68k_set_extension (arg, 0, 1))
7474 ;
7475 else if (m68k_set_arch (arg, 0, 1))
7476 ;
7477 else if (m68k_set_cpu (arg, 0, 1))
7478 ;
7479 else
7480 return 0;
7481 break;
7482
7483 default:
7484 return 0;
7485 }
7486
7487 return 1;
7488 }
7489
7490 /* Setup tables from the selected arch and/or cpu */
7491
7492 static void
7493 m68k_init_arch (void)
7494 {
7495 if (not_current_architecture & current_architecture)
7496 {
7497 as_bad (_("architecture features both enabled and disabled"));
7498 not_current_architecture &= ~current_architecture;
7499 }
7500 if (selected_arch)
7501 {
7502 current_architecture |= selected_arch->arch;
7503 control_regs = selected_arch->control_regs;
7504 }
7505 else
7506 current_architecture |= selected_cpu->arch;
7507
7508 current_architecture &= ~not_current_architecture;
7509
7510 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7511 {
7512 /* Determine which float is really meant. */
7513 if (current_architecture & (m68k_mask & ~m68881))
7514 current_architecture ^= cfloat;
7515 else
7516 current_architecture ^= m68881;
7517 }
7518
7519 if (selected_cpu)
7520 {
7521 control_regs = selected_cpu->control_regs;
7522 if (current_architecture & ~selected_cpu->arch)
7523 {
7524 as_bad (_("selected processor does not have all features of selected architecture"));
7525 current_architecture
7526 = selected_cpu->arch & ~not_current_architecture;
7527 }
7528 }
7529
7530 if ((current_architecture & m68k_mask)
7531 && (current_architecture & ~m68k_mask))
7532 {
7533 as_bad (_ ("m68k and cf features both selected"));
7534 if (current_architecture & m68k_mask)
7535 current_architecture &= m68k_mask;
7536 else
7537 current_architecture &= ~m68k_mask;
7538 }
7539
7540 /* Permit m68881 specification with all cpus; those that can't work
7541 with a coprocessor could be doing emulation. */
7542 if (current_architecture & m68851)
7543 {
7544 if (current_architecture & m68040)
7545 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7546 }
7547 /* What other incompatibilities could we check for? */
7548
7549 if (cpu_of_arch (current_architecture) < m68020
7550 || arch_coldfire_p (current_architecture))
7551 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7552
7553 initialized = 1;
7554 }
7555
7556 void
7557 md_show_usage (FILE *stream)
7558 {
7559 const char *default_cpu = TARGET_CPU;
7560 int i;
7561 unsigned int default_arch;
7562
7563 /* Get the canonical name for the default target CPU. */
7564 if (*default_cpu == 'm')
7565 default_cpu++;
7566 for (i = 0; m68k_cpus[i].name; i++)
7567 {
7568 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7569 {
7570 default_arch = m68k_cpus[i].arch;
7571 while (m68k_cpus[i].alias > 0)
7572 i--;
7573 while (m68k_cpus[i].alias < 0)
7574 i++;
7575 default_cpu = m68k_cpus[i].name;
7576 }
7577 }
7578
7579 fprintf (stream, _("\
7580 -march=<arch> set architecture\n\
7581 -mcpu=<cpu> set cpu [default %s]\n\
7582 "), default_cpu);
7583 for (i = 0; m68k_extensions[i].name; i++)
7584 fprintf (stream, _("\
7585 -m[no-]%-16s enable/disable%s architecture extension\n\
7586 "), m68k_extensions[i].name,
7587 m68k_extensions[i].alias > 0 ? " ColdFire"
7588 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7589
7590 fprintf (stream, _("\
7591 -l use 1 word for refs to undefined symbols [default 2]\n\
7592 -pic, -k generate position independent code\n\
7593 -S turn jbsr into jsr\n\
7594 --pcrel never turn PC-relative branches into absolute jumps\n\
7595 --register-prefix-optional\n\
7596 recognize register names without prefix character\n\
7597 --bitwise-or do not treat `|' as a comment character\n\
7598 --base-size-default-16 base reg without size is 16 bits\n\
7599 --base-size-default-32 base reg without size is 32 bits (default)\n\
7600 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7601 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7602 "));
7603
7604 fprintf (stream, _("Architecture variants are: "));
7605 for (i = 0; m68k_archs[i].name; i++)
7606 {
7607 if (i)
7608 fprintf (stream, " | ");
7609 fprintf (stream, m68k_archs[i].name);
7610 }
7611 fprintf (stream, "\n");
7612
7613 fprintf (stream, _("Processor variants are: "));
7614 for (i = 0; m68k_cpus[i].name; i++)
7615 {
7616 if (i)
7617 fprintf (stream, " | ");
7618 fprintf (stream, m68k_cpus[i].name);
7619 }
7620 fprintf (stream, _("\n"));
7621 }
7622 \f
7623 #ifdef TEST2
7624
7625 /* TEST2: Test md_assemble() */
7626 /* Warning, this routine probably doesn't work anymore. */
7627 int
7628 main (void)
7629 {
7630 struct m68k_it the_ins;
7631 char buf[120];
7632 char *cp;
7633 int n;
7634
7635 m68k_ip_begin ();
7636 for (;;)
7637 {
7638 if (!gets (buf) || !*buf)
7639 break;
7640 if (buf[0] == '|' || buf[1] == '.')
7641 continue;
7642 for (cp = buf; *cp; cp++)
7643 if (*cp == '\t')
7644 *cp = ' ';
7645 if (is_label (buf))
7646 continue;
7647 memset (&the_ins, '\0', sizeof (the_ins));
7648 m68k_ip (&the_ins, buf);
7649 if (the_ins.error)
7650 {
7651 printf (_("Error %s in %s\n"), the_ins.error, buf);
7652 }
7653 else
7654 {
7655 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7656 for (n = 0; n < the_ins.numo; n++)
7657 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7658 printf (" ");
7659 print_the_insn (&the_ins.opcode[0], stdout);
7660 (void) putchar ('\n');
7661 }
7662 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7663 {
7664 if (the_ins.operands[n].error)
7665 {
7666 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7667 continue;
7668 }
7669 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7670 the_ins.operands[n].reg);
7671 if (the_ins.operands[n].b_const)
7672 printf ("Constant: '%.*s', ",
7673 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7674 the_ins.operands[n].b_const);
7675 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7676 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7677 if (the_ins.operands[n].b_iadd)
7678 printf ("Iadd: '%.*s',",
7679 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7680 the_ins.operands[n].b_iadd);
7681 putchar ('\n');
7682 }
7683 }
7684 m68k_ip_end ();
7685 return 0;
7686 }
7687
7688 int
7689 is_label (char *str)
7690 {
7691 while (*str == ' ')
7692 str++;
7693 while (*str && *str != ' ')
7694 str++;
7695 if (str[-1] == ':' || str[1] == '=')
7696 return 1;
7697 return 0;
7698 }
7699
7700 #endif
7701
7702 /* Possible states for relaxation:
7703
7704 0 0 branch offset byte (bra, etc)
7705 0 1 word
7706 0 2 long
7707
7708 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7709 1 1 word
7710 1 2 long
7711
7712 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7713 2 1 word-long
7714 2 2 long-word
7715 2 3 long-long
7716
7717 */
7718
7719 /* We have no need to default values of symbols. */
7720
7721 symbolS *
7722 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7723 {
7724 return 0;
7725 }
7726
7727 /* Round up a section size to the appropriate boundary. */
7728 valueT
7729 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7730 {
7731 #ifdef OBJ_AOUT
7732 /* For a.out, force the section size to be aligned. If we don't do
7733 this, BFD will align it for us, but it will not write out the
7734 final bytes of the section. This may be a bug in BFD, but it is
7735 easier to fix it here since that is how the other a.out targets
7736 work. */
7737 int align;
7738
7739 align = bfd_get_section_alignment (stdoutput, segment);
7740 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7741 #endif
7742
7743 return size;
7744 }
7745
7746 /* Exactly what point is a PC-relative offset relative TO?
7747 On the 68k, it is relative to the address of the first extension
7748 word. The difference between the addresses of the offset and the
7749 first extension word is stored in fx_pcrel_adjust. */
7750 long
7751 md_pcrel_from (fixS *fixP)
7752 {
7753 int adjust;
7754
7755 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7756 sign extend the value here. */
7757 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
7758 if (adjust == 64)
7759 adjust = -1;
7760 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7761 }
7762
7763 #ifdef OBJ_ELF
7764 void
7765 m68k_elf_final_processing (void)
7766 {
7767 unsigned flags = 0;
7768
7769 if (arch_coldfire_fpu (current_architecture))
7770 flags |= EF_M68K_CFV4E;
7771 /* Set file-specific flags if this is a cpu32 processor. */
7772 if (cpu_of_arch (current_architecture) & cpu32)
7773 flags |= EF_M68K_CPU32;
7774 else if (cpu_of_arch (current_architecture) & fido_a)
7775 flags |= EF_M68K_FIDO;
7776 else if ((cpu_of_arch (current_architecture) & m68000up)
7777 && !(cpu_of_arch (current_architecture) & m68020up))
7778 flags |= EF_M68K_M68000;
7779
7780 if (current_architecture & mcfisa_a)
7781 {
7782 static const unsigned isa_features[][2] =
7783 {
7784 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7785 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7786 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7787 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7788 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7789 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7790 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7791 {0,0},
7792 };
7793 static const unsigned mac_features[][2] =
7794 {
7795 {EF_M68K_CF_MAC, mcfmac},
7796 {EF_M68K_CF_EMAC, mcfemac},
7797 {0,0},
7798 };
7799 unsigned ix;
7800 unsigned pattern;
7801
7802 pattern = (current_architecture
7803 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7804 for (ix = 0; isa_features[ix][1]; ix++)
7805 {
7806 if (pattern == isa_features[ix][1])
7807 {
7808 flags |= isa_features[ix][0];
7809 break;
7810 }
7811 }
7812 if (!isa_features[ix][1])
7813 {
7814 cf_bad:
7815 as_warn (_("Not a defined coldfire architecture"));
7816 }
7817 else
7818 {
7819 if (current_architecture & cfloat)
7820 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7821
7822 pattern = current_architecture & (mcfmac|mcfemac);
7823 if (pattern)
7824 {
7825 for (ix = 0; mac_features[ix][1]; ix++)
7826 {
7827 if (pattern == mac_features[ix][1])
7828 {
7829 flags |= mac_features[ix][0];
7830 break;
7831 }
7832 }
7833 if (!mac_features[ix][1])
7834 goto cf_bad;
7835 }
7836 }
7837 }
7838 elf_elfheader (stdoutput)->e_flags |= flags;
7839 }
7840 #endif
7841
7842 int
7843 tc_m68k_regname_to_dw2regnum (char *regname)
7844 {
7845 unsigned int regnum;
7846 static const char *const regnames[] =
7847 {
7848 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7849 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7850 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7851 "pc"
7852 };
7853
7854 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7855 if (strcmp (regname, regnames[regnum]) == 0)
7856 return regnum;
7857
7858 return -1;
7859 }
7860
7861 void
7862 tc_m68k_frame_initial_instructions (void)
7863 {
7864 static int sp_regno = -1;
7865
7866 if (sp_regno < 0)
7867 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7868
7869 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7870 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7871 }