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Rest of the changes for Coldfire V4
[binutils-gdb.git] / gas / config / tc-m68k.c
1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001
3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22 #include <ctype.h>
23 #include "as.h"
24 #include "obstack.h"
25 #include "subsegs.h"
26
27 #include "opcode/m68k.h"
28 #include "m68k-parse.h"
29
30 #if defined (OBJ_ELF)
31 #include "elf/m68k.h"
32 #endif
33
34 /* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38 #if defined (TE_SVR4) || defined (TE_DELTA)
39 const char *m68k_comment_chars = "|#";
40 #else
41 const char *m68k_comment_chars = "|";
42 #endif
43
44 /* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47 /* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
49 #NO_APP at the beginning of its output. */
50 /* Also note that comments like this one will always work. */
51 const char line_comment_chars[] = "#*";
52
53 const char line_separator_chars[] = ";";
54
55 /* Chars that can be used to separate mant from exp in floating point nums */
56 CONST char EXP_CHARS[] = "eE";
57
58 /* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
61 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
62
63 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
67 const int md_reloc_size = 8; /* Size of relocation record */
68
69 /* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
71 references. Not implemented. For ELF there are other means
72 to denote pic relocations. */
73 int flag_want_pic;
74
75 static int flag_short_refs; /* -l option */
76 static int flag_long_jumps; /* -S option */
77 static int flag_keep_pcrel; /* --pcrel option. */
78
79 #ifdef REGISTER_PREFIX_OPTIONAL
80 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
81 #else
82 int flag_reg_prefix_optional;
83 #endif
84
85 /* Whether --register-prefix-optional was used on the command line. */
86 static int reg_prefix_optional_seen;
87
88 /* The floating point coprocessor to use by default. */
89 static enum m68k_register m68k_float_copnum = COP1;
90
91 /* If this is non-zero, then references to number(%pc) will be taken
92 to refer to number, rather than to %pc + number. */
93 static int m68k_abspcadd;
94
95 /* If this is non-zero, then the quick forms of the move, add, and sub
96 instructions are used when possible. */
97 static int m68k_quick = 1;
98
99 /* If this is non-zero, then if the size is not specified for a base
100 or outer displacement, the assembler assumes that the size should
101 be 32 bits. */
102 static int m68k_rel32 = 1;
103
104 /* This is non-zero if m68k_rel32 was set from the command line. */
105 static int m68k_rel32_from_cmdline;
106
107 /* The default width to use for an index register when using a base
108 displacement. */
109 static enum m68k_size m68k_index_width_default = SIZE_LONG;
110
111 /* We want to warn if any text labels are misaligned. In order to get
112 the right line number, we need to record the line number for each
113 label. */
114
115 struct label_line
116 {
117 struct label_line *next;
118 symbolS *label;
119 char *file;
120 unsigned int line;
121 int text;
122 };
123
124 /* The list of labels. */
125
126 static struct label_line *labels;
127
128 /* The current label. */
129
130 static struct label_line *current_label;
131
132 /* Its an arbitrary name: This means I don't approve of it */
133 /* See flames below */
134 static struct obstack robyn;
135
136 struct m68k_incant
137 {
138 const char *m_operands;
139 unsigned long m_opcode;
140 short m_opnum;
141 short m_codenum;
142 int m_arch;
143 struct m68k_incant *m_next;
144 };
145
146 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
147 #define gettwo(x) (((x)->m_opcode)&0xffff)
148
149 static const enum m68k_register m68000_control_regs[] = { 0 };
150 static const enum m68k_register m68010_control_regs[] = {
151 SFC, DFC, USP, VBR,
152 0
153 };
154 static const enum m68k_register m68020_control_regs[] = {
155 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
156 0
157 };
158 static const enum m68k_register m68040_control_regs[] = {
159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
160 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
161 0
162 };
163 static const enum m68k_register m68060_control_regs[] = {
164 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
165 USP, VBR, URP, SRP, PCR,
166 0
167 };
168 static const enum m68k_register mcf_control_regs[] = {
169 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
170 RAMBAR0, RAMBAR1, MBAR,
171 0
172 };
173 #define cpu32_control_regs m68010_control_regs
174
175 static const enum m68k_register *control_regs;
176
177 /* internal form of a 68020 instruction */
178 struct m68k_it
179 {
180 const char *error;
181 const char *args; /* list of opcode info */
182 int numargs;
183
184 int numo; /* Number of shorts in opcode */
185 short opcode[11];
186
187 struct m68k_op operands[6];
188
189 int nexp; /* number of exprs in use */
190 struct m68k_exp exprs[4];
191
192 int nfrag; /* Number of frags we have to produce */
193 struct
194 {
195 int fragoff; /* Where in the current opcode the frag ends */
196 symbolS *fadd;
197 offsetT foff;
198 int fragty;
199 }
200 fragb[4];
201
202 int nrel; /* Num of reloc strucs in use */
203 struct
204 {
205 int n;
206 expressionS exp;
207 char wid;
208 char pcrel;
209 /* In a pc relative address the difference between the address
210 of the offset and the address that the offset is relative
211 to. This depends on the addressing mode. Basically this
212 is the value to put in the offset field to address the
213 first byte of the offset, without regarding the special
214 significance of some values (in the branch instruction, for
215 example). */
216 int pcrel_fix;
217 #ifdef OBJ_ELF
218 /* Whether this expression needs special pic relocation, and if
219 so, which. */
220 enum pic_relocation pic_reloc;
221 #endif
222 }
223 reloc[5]; /* Five is enough??? */
224 };
225
226 #define cpu_of_arch(x) ((x) & (m68000up|mcf))
227 #define float_of_arch(x) ((x) & mfloat)
228 #define mmu_of_arch(x) ((x) & mmmu)
229 #define arch_coldfire_p(x) (((x) & mcf) != 0)
230
231 /* Macros for determining if cpu supports a specific addressing mode */
232 #define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407))
233
234 static struct m68k_it the_ins; /* the instruction being assembled */
235
236 #define op(ex) ((ex)->exp.X_op)
237 #define adds(ex) ((ex)->exp.X_add_symbol)
238 #define subs(ex) ((ex)->exp.X_op_symbol)
239 #define offs(ex) ((ex)->exp.X_add_number)
240
241 /* Macros for adding things to the m68k_it struct */
242
243 #define addword(w) the_ins.opcode[the_ins.numo++]=(w)
244
245 /* Static functions. */
246
247 static void insop PARAMS ((int, const struct m68k_incant *));
248 static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
249 static void add_frag PARAMS ((symbolS *, offsetT, int));
250
251 /* Like addword, but goes BEFORE general operands */
252 static void
253 insop (w, opcode)
254 int w;
255 const struct m68k_incant *opcode;
256 {
257 int z;
258 for(z=the_ins.numo;z>opcode->m_codenum;--z)
259 the_ins.opcode[z]=the_ins.opcode[z-1];
260 for(z=0;z<the_ins.nrel;z++)
261 the_ins.reloc[z].n+=2;
262 for (z = 0; z < the_ins.nfrag; z++)
263 the_ins.fragb[z].fragoff++;
264 the_ins.opcode[opcode->m_codenum]=w;
265 the_ins.numo++;
266 }
267
268 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
269 Blecch. */
270 static void
271 add_fix (width, exp, pc_rel, pc_fix)
272 int width;
273 struct m68k_exp *exp;
274 int pc_rel;
275 int pc_fix;
276 {
277 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
278 ? (the_ins.numo*2-1)
279 : (((width)=='b')
280 ? (the_ins.numo*2+1)
281 : (the_ins.numo*2)));
282 the_ins.reloc[the_ins.nrel].exp = exp->exp;
283 the_ins.reloc[the_ins.nrel].wid = width;
284 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
285 #ifdef OBJ_ELF
286 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
287 #endif
288 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
289 }
290
291 /* Cause an extra frag to be generated here, inserting up to 10 bytes
292 (that value is chosen in the frag_var call in md_assemble). TYPE
293 is the subtype of the frag to be generated; its primary type is
294 rs_machine_dependent.
295
296 The TYPE parameter is also used by md_convert_frag_1 and
297 md_estimate_size_before_relax. The appropriate type of fixup will
298 be emitted by md_convert_frag_1.
299
300 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
301 static void
302 add_frag (add, off, type)
303 symbolS *add;
304 offsetT off;
305 int type;
306 {
307 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
308 the_ins.fragb[the_ins.nfrag].fadd=add;
309 the_ins.fragb[the_ins.nfrag].foff=off;
310 the_ins.fragb[the_ins.nfrag++].fragty=type;
311 }
312
313 #define isvar(ex) \
314 (op (ex) != O_constant && op (ex) != O_big)
315
316 static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
317 static int get_num PARAMS ((struct m68k_exp *exp, int ok));
318 static void m68k_ip PARAMS ((char *));
319 static void insert_reg PARAMS ((const char *, int));
320 static void select_control_regs PARAMS ((void));
321 static void init_regtable PARAMS ((void));
322 static int reverse_16_bits PARAMS ((int in));
323 static int reverse_8_bits PARAMS ((int in));
324 static void install_gen_operand PARAMS ((int mode, int val));
325 static void install_operand PARAMS ((int mode, int val));
326 static void s_bss PARAMS ((int));
327 static void s_data1 PARAMS ((int));
328 static void s_data2 PARAMS ((int));
329 static void s_even PARAMS ((int));
330 static void s_proc PARAMS ((int));
331 static void mri_chip PARAMS ((void));
332 static void s_chip PARAMS ((int));
333 static void s_fopt PARAMS ((int));
334 static void s_opt PARAMS ((int));
335 static void s_reg PARAMS ((int));
336 static void s_restore PARAMS ((int));
337 static void s_save PARAMS ((int));
338 static void s_mri_if PARAMS ((int));
339 static void s_mri_else PARAMS ((int));
340 static void s_mri_endi PARAMS ((int));
341 static void s_mri_break PARAMS ((int));
342 static void s_mri_next PARAMS ((int));
343 static void s_mri_for PARAMS ((int));
344 static void s_mri_endf PARAMS ((int));
345 static void s_mri_repeat PARAMS ((int));
346 static void s_mri_until PARAMS ((int));
347 static void s_mri_while PARAMS ((int));
348 static void s_mri_endw PARAMS ((int));
349 static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
350 static void md_convert_frag_1 PARAMS ((fragS *));
351
352 static int current_architecture;
353
354 struct m68k_cpu
355 {
356 unsigned long arch;
357 const char *name;
358 int alias;
359 };
360
361 static const struct m68k_cpu archs[] =
362 {
363 { m68000, "68000", 0 },
364 { m68010, "68010", 0 },
365 { m68020, "68020", 0 },
366 { m68030, "68030", 0 },
367 { m68040, "68040", 0 },
368 { m68060, "68060", 0 },
369 { cpu32, "cpu32", 0 },
370 { m68881, "68881", 0 },
371 { m68851, "68851", 0 },
372 { mcf5200, "5200", 0 },
373 { mcf5206e, "5206e", 0 },
374 { mcf5307, "5307", 0},
375 { mcf5407, "5407", 0},
376 /* Aliases (effectively, so far as gas is concerned) for the above
377 cpus. */
378 { m68020, "68k", 1 },
379 { m68000, "68008", 1 },
380 { m68000, "68302", 1 },
381 { m68000, "68306", 1 },
382 { m68000, "68307", 1 },
383 { m68000, "68322", 1 },
384 { m68000, "68356", 1 },
385 { m68000, "68ec000", 1 },
386 { m68000, "68hc000", 1 },
387 { m68000, "68hc001", 1 },
388 { m68020, "68ec020", 1 },
389 { m68030, "68ec030", 1 },
390 { m68040, "68ec040", 1 },
391 { m68060, "68ec060", 1 },
392 { cpu32, "68330", 1 },
393 { cpu32, "68331", 1 },
394 { cpu32, "68332", 1 },
395 { cpu32, "68333", 1 },
396 { cpu32, "68334", 1 },
397 { cpu32, "68336", 1 },
398 { cpu32, "68340", 1 },
399 { cpu32, "68341", 1 },
400 { cpu32, "68349", 1 },
401 { cpu32, "68360", 1 },
402 { m68881, "68882", 1 },
403 { mcf5200, "5202", 1 },
404 { mcf5200, "5204", 1 },
405 { mcf5200, "5206", 1 },
406 };
407
408 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
409
410 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
411 architecture and we have a lot of relaxation modes. */
412
413 /* Macros used in the relaxation code. */
414 #define TAB(x,y) (((x) << 2) + (y))
415 #define TABTYPE(x) ((x) >> 2)
416
417 /* Relaxation states. */
418 #define BYTE 0
419 #define SHORT 1
420 #define LONG 2
421 #define SZ_UNDEF 3
422
423 /* Here are all the relaxation modes we support. First we can relax ordinary
424 branches. On 68020 and higher and on CPU32 all branch instructions take
425 three forms, so on these CPUs all branches always remain as such. When we
426 have to expand to the LONG form on a 68000, though, we substitute an
427 absolute jump instead. This is a direct replacement for unconditional
428 branches and a branch over a jump for conditional branches. However, if the
429 user requires PIC and disables this with --pcrel, we can only relax between
430 BYTE and SHORT forms, punting if that isn't enough. This gives us four
431 different relaxation modes for branches: */
432
433 #define BRANCHBWL 1 /* branch byte, word, or long */
434 #define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
435 #define BRABSJCOND 3 /* absolute jump for LONG, conditional */
436 #define BRANCHBW 4 /* branch byte or word */
437
438 /* We also relax coprocessor branches and DBcc's. All CPUs that support
439 coprocessor branches support them in word and long forms, so we have only
440 one relaxation mode for them. DBcc's are word only on all CPUs. We can
441 relax them to the LONG form with a branch-around sequence. This sequence
442 can use a long branch (if available) or an absolute jump (if acceptable).
443 This gives us two relaxation modes. If long branches are not available and
444 absolute jumps are not acceptable, we don't relax DBcc's. */
445
446 #define FBRANCH 5 /* coprocessor branch */
447 #define DBCCLBR 6 /* DBcc relaxable with a long branch */
448 #define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
449
450 /* That's all for instruction relaxation. However, we also relax PC-relative
451 operands. Specifically, we have three operand relaxation modes. On the
452 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
453 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
454 two. Also PC+displacement+index operands in their simple form (with a non-
455 suppressed index without memory indirection) are supported on all CPUs, but
456 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
457 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
458 form of the PC+displacement+index operand. Finally, some absolute operands
459 can be relaxed down to 16-bit PC-relative. */
460
461 #define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
462 #define PCINDEX 9 /* PC+displacement+index */
463 #define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
464
465 /* Note that calls to frag_var need to specify the maximum expansion
466 needed; this is currently 10 bytes for DBCC. */
467
468 /* The fields are:
469 How far Forward this mode will reach:
470 How far Backward this mode will reach:
471 How many bytes this mode will add to the size of the frag
472 Which mode to go to if the offset won't fit in this one
473 */
474 relax_typeS md_relax_table[] =
475 {
476 {1, 1, 0, 0}, /* First entries aren't used */
477 {1, 1, 0, 0}, /* For no good reason except */
478 {1, 1, 0, 0}, /* that the VAX doesn't either */
479 {1, 1, 0, 0},
480
481 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
482 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
483 {0, 0, 4, 0},
484 {1, 1, 0, 0},
485
486 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
487 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
488 {0, 0, 4, 0},
489 {1, 1, 0, 0},
490
491 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
492 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
493 {0, 0, 6, 0},
494 {1, 1, 0, 0},
495
496 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
497 {0, 0, 2, 0},
498 {1, 1, 0, 0},
499 {1, 1, 0, 0},
500
501 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
502 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
503 {0, 0, 4, 0},
504 {1, 1, 0, 0},
505
506 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
507 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
508 {0, 0, 10, 0},
509 {1, 1, 0, 0},
510
511 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
512 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
513 {0, 0, 10, 0},
514 {1, 1, 0, 0},
515
516 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
517 {32767, -32768, 2, TAB (PCREL1632, LONG)},
518 {0, 0, 6, 0},
519 {1, 1, 0, 0},
520
521 {125, -130, 0, TAB (PCINDEX, SHORT)},
522 {32765, -32770, 2, TAB (PCINDEX, LONG)},
523 {0, 0, 4, 0},
524 {1, 1, 0, 0},
525
526 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
527 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
528 {0, 0, 4, 0},
529 {1, 1, 0, 0},
530 };
531
532 /* These are the machine dependent pseudo-ops. These are included so
533 the assembler can work on the output from the SUN C compiler, which
534 generates these.
535 */
536
537 /* This table describes all the machine specific pseudo-ops the assembler
538 has to support. The fields are:
539 pseudo-op name without dot
540 function to call to execute this pseudo-op
541 Integer arg to pass to the function
542 */
543 const pseudo_typeS md_pseudo_table[] =
544 {
545 {"data1", s_data1, 0},
546 {"data2", s_data2, 0},
547 {"bss", s_bss, 0},
548 {"even", s_even, 0},
549 {"skip", s_space, 0},
550 {"proc", s_proc, 0},
551 #if defined (TE_SUN3) || defined (OBJ_ELF)
552 {"align", s_align_bytes, 0},
553 #endif
554 #ifdef OBJ_ELF
555 {"swbeg", s_ignore, 0},
556 #endif
557 {"extend", float_cons, 'x'},
558 {"ldouble", float_cons, 'x'},
559
560 /* The following pseudo-ops are supported for MRI compatibility. */
561 {"chip", s_chip, 0},
562 {"comline", s_space, 1},
563 {"fopt", s_fopt, 0},
564 {"mask2", s_ignore, 0},
565 {"opt", s_opt, 0},
566 {"reg", s_reg, 0},
567 {"restore", s_restore, 0},
568 {"save", s_save, 0},
569
570 {"if", s_mri_if, 0},
571 {"if.b", s_mri_if, 'b'},
572 {"if.w", s_mri_if, 'w'},
573 {"if.l", s_mri_if, 'l'},
574 {"else", s_mri_else, 0},
575 {"else.s", s_mri_else, 's'},
576 {"else.l", s_mri_else, 'l'},
577 {"endi", s_mri_endi, 0},
578 {"break", s_mri_break, 0},
579 {"break.s", s_mri_break, 's'},
580 {"break.l", s_mri_break, 'l'},
581 {"next", s_mri_next, 0},
582 {"next.s", s_mri_next, 's'},
583 {"next.l", s_mri_next, 'l'},
584 {"for", s_mri_for, 0},
585 {"for.b", s_mri_for, 'b'},
586 {"for.w", s_mri_for, 'w'},
587 {"for.l", s_mri_for, 'l'},
588 {"endf", s_mri_endf, 0},
589 {"repeat", s_mri_repeat, 0},
590 {"until", s_mri_until, 0},
591 {"until.b", s_mri_until, 'b'},
592 {"until.w", s_mri_until, 'w'},
593 {"until.l", s_mri_until, 'l'},
594 {"while", s_mri_while, 0},
595 {"while.b", s_mri_while, 'b'},
596 {"while.w", s_mri_while, 'w'},
597 {"while.l", s_mri_while, 'l'},
598 {"endw", s_mri_endw, 0},
599
600 {0, 0, 0}
601 };
602
603 /* The mote pseudo ops are put into the opcode table, since they
604 don't start with a . they look like opcodes to gas.
605 */
606
607 #ifdef M68KCOFF
608 extern void obj_coff_section PARAMS ((int));
609 #endif
610
611 CONST pseudo_typeS mote_pseudo_table[] =
612 {
613
614 {"dcl", cons, 4},
615 {"dc", cons, 2},
616 {"dcw", cons, 2},
617 {"dcb", cons, 1},
618
619 {"dsl", s_space, 4},
620 {"ds", s_space, 2},
621 {"dsw", s_space, 2},
622 {"dsb", s_space, 1},
623
624 {"xdef", s_globl, 0},
625 #ifdef OBJ_ELF
626 {"align", s_align_bytes, 0},
627 #else
628 {"align", s_align_ptwo, 0},
629 #endif
630 #ifdef M68KCOFF
631 {"sect", obj_coff_section, 0},
632 {"section", obj_coff_section, 0},
633 #endif
634 {0, 0, 0}
635 };
636
637 #define issbyte(x) ((x)>=-128 && (x)<=127)
638 #define isubyte(x) ((x)>=0 && (x)<=255)
639 #define issword(x) ((x)>=-32768 && (x)<=32767)
640 #define isuword(x) ((x)>=0 && (x)<=65535)
641
642 #define isbyte(x) ((x)>= -255 && (x)<=255)
643 #define isword(x) ((x)>=-65536 && (x)<=65535)
644 #define islong(x) (1)
645
646 extern char *input_line_pointer;
647
648 static char mklower_table[256];
649 #define mklower(c) (mklower_table[(unsigned char) (c)])
650 static char notend_table[256];
651 static char alt_notend_table[256];
652 #define notend(s) \
653 (! (notend_table[(unsigned char) *s] \
654 || (*s == ':' \
655 && alt_notend_table[(unsigned char) s[1]])))
656
657 #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
658
659 #ifdef NO_PCREL_RELOCS
660
661 int
662 make_pcrel_absolute(fixP, add_number)
663 fixS *fixP;
664 long *add_number;
665 {
666 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
667
668 /* rewrite the PC relative instructions to absolute address ones.
669 * these are rumoured to be faster, and the apollo linker refuses
670 * to deal with the PC relative relocations.
671 */
672 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
673 {
674 opcode[0] = 0x4e;
675 opcode[1] = 0xf9;
676 }
677 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
678 {
679 opcode[0] = 0x4e;
680 opcode[1] = 0xb9;
681 }
682 else
683 as_fatal (_("Unknown PC relative instruction"));
684 *add_number -= 4;
685 return 0;
686 }
687
688 #endif /* NO_PCREL_RELOCS */
689
690 short
691 tc_coff_fix2rtype (fixP)
692 fixS *fixP;
693 {
694 if (fixP->fx_tcbit && fixP->fx_size == 4)
695 return R_RELLONG_NEG;
696 #ifdef NO_PCREL_RELOCS
697 know (fixP->fx_pcrel == 0);
698 return (fixP->fx_size == 1 ? R_RELBYTE
699 : fixP->fx_size == 2 ? R_DIR16
700 : R_DIR32);
701 #else
702 return (fixP->fx_pcrel ?
703 (fixP->fx_size == 1 ? R_PCRBYTE :
704 fixP->fx_size == 2 ? R_PCRWORD :
705 R_PCRLONG) :
706 (fixP->fx_size == 1 ? R_RELBYTE :
707 fixP->fx_size == 2 ? R_RELWORD :
708 R_RELLONG));
709 #endif
710 }
711
712 #endif
713
714 #ifdef OBJ_ELF
715
716 /* Compute the relocation code for a fixup of SIZE bytes, using pc
717 relative relocation if PCREL is non-zero. PIC says whether a special
718 pic relocation was requested. */
719
720 static bfd_reloc_code_real_type get_reloc_code
721 PARAMS ((int, int, enum pic_relocation));
722
723 static bfd_reloc_code_real_type
724 get_reloc_code (size, pcrel, pic)
725 int size;
726 int pcrel;
727 enum pic_relocation pic;
728 {
729 switch (pic)
730 {
731 case pic_got_pcrel:
732 switch (size)
733 {
734 case 1:
735 return BFD_RELOC_8_GOT_PCREL;
736 case 2:
737 return BFD_RELOC_16_GOT_PCREL;
738 case 4:
739 return BFD_RELOC_32_GOT_PCREL;
740 }
741 break;
742
743 case pic_got_off:
744 switch (size)
745 {
746 case 1:
747 return BFD_RELOC_8_GOTOFF;
748 case 2:
749 return BFD_RELOC_16_GOTOFF;
750 case 4:
751 return BFD_RELOC_32_GOTOFF;
752 }
753 break;
754
755 case pic_plt_pcrel:
756 switch (size)
757 {
758 case 1:
759 return BFD_RELOC_8_PLT_PCREL;
760 case 2:
761 return BFD_RELOC_16_PLT_PCREL;
762 case 4:
763 return BFD_RELOC_32_PLT_PCREL;
764 }
765 break;
766
767 case pic_plt_off:
768 switch (size)
769 {
770 case 1:
771 return BFD_RELOC_8_PLTOFF;
772 case 2:
773 return BFD_RELOC_16_PLTOFF;
774 case 4:
775 return BFD_RELOC_32_PLTOFF;
776 }
777 break;
778
779 case pic_none:
780 if (pcrel)
781 {
782 switch (size)
783 {
784 case 1:
785 return BFD_RELOC_8_PCREL;
786 case 2:
787 return BFD_RELOC_16_PCREL;
788 case 4:
789 return BFD_RELOC_32_PCREL;
790 }
791 }
792 else
793 {
794 switch (size)
795 {
796 case 1:
797 return BFD_RELOC_8;
798 case 2:
799 return BFD_RELOC_16;
800 case 4:
801 return BFD_RELOC_32;
802 }
803 }
804 }
805
806 if (pcrel)
807 {
808 if (pic == pic_none)
809 as_bad (_("Can not do %d byte pc-relative relocation"), size);
810 else
811 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
812 }
813 else
814 {
815 if (pic == pic_none)
816 as_bad (_("Can not do %d byte relocation"), size);
817 else
818 as_bad (_("Can not do %d byte pic relocation"), size);
819 }
820
821 return BFD_RELOC_NONE;
822 }
823
824 /* Here we decide which fixups can be adjusted to make them relative
825 to the beginning of the section instead of the symbol. Basically
826 we need to make sure that the dynamic relocations are done
827 correctly, so in some cases we force the original symbol to be
828 used. */
829 int
830 tc_m68k_fix_adjustable (fixP)
831 fixS *fixP;
832 {
833 /* Prevent all adjustments to global symbols. */
834 if (S_IS_EXTERNAL (fixP->fx_addsy)
835 || S_IS_WEAK (fixP->fx_addsy))
836 return 0;
837
838 /* adjust_reloc_syms doesn't know about the GOT */
839 switch (fixP->fx_r_type)
840 {
841 case BFD_RELOC_8_GOT_PCREL:
842 case BFD_RELOC_16_GOT_PCREL:
843 case BFD_RELOC_32_GOT_PCREL:
844 case BFD_RELOC_8_GOTOFF:
845 case BFD_RELOC_16_GOTOFF:
846 case BFD_RELOC_32_GOTOFF:
847 case BFD_RELOC_8_PLT_PCREL:
848 case BFD_RELOC_16_PLT_PCREL:
849 case BFD_RELOC_32_PLT_PCREL:
850 case BFD_RELOC_8_PLTOFF:
851 case BFD_RELOC_16_PLTOFF:
852 case BFD_RELOC_32_PLTOFF:
853 return 0;
854
855 case BFD_RELOC_VTABLE_INHERIT:
856 case BFD_RELOC_VTABLE_ENTRY:
857 return 0;
858
859 default:
860 return 1;
861 }
862 }
863
864 #else /* !OBJ_ELF */
865
866 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
867
868 #endif /* OBJ_ELF */
869
870 #ifdef BFD_ASSEMBLER
871
872 arelent *
873 tc_gen_reloc (section, fixp)
874 asection *section;
875 fixS *fixp;
876 {
877 arelent *reloc;
878 bfd_reloc_code_real_type code;
879
880 /* If the tcbit is set, then this was a fixup of a negative value
881 that was never resolved. We do not have a reloc to handle this,
882 so just return. We assume that other code will have detected this
883 situation and produced a helpful error message, so we just tell the
884 user that the reloc cannot be produced. */
885 if (fixp->fx_tcbit)
886 {
887 if (fixp->fx_addsy)
888 as_bad (_("Unable to produce reloc against symbol '%s'"),
889 S_GET_NAME (fixp->fx_addsy));
890 return NULL;
891 }
892
893 if (fixp->fx_r_type != BFD_RELOC_NONE)
894 {
895 code = fixp->fx_r_type;
896
897 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
898 that fixup_segment converted a non-PC relative reloc into a
899 PC relative reloc. In such a case, we need to convert the
900 reloc code. */
901 if (fixp->fx_pcrel)
902 {
903 switch (code)
904 {
905 case BFD_RELOC_8:
906 code = BFD_RELOC_8_PCREL;
907 break;
908 case BFD_RELOC_16:
909 code = BFD_RELOC_16_PCREL;
910 break;
911 case BFD_RELOC_32:
912 code = BFD_RELOC_32_PCREL;
913 break;
914 case BFD_RELOC_8_PCREL:
915 case BFD_RELOC_16_PCREL:
916 case BFD_RELOC_32_PCREL:
917 case BFD_RELOC_8_GOT_PCREL:
918 case BFD_RELOC_16_GOT_PCREL:
919 case BFD_RELOC_32_GOT_PCREL:
920 case BFD_RELOC_8_GOTOFF:
921 case BFD_RELOC_16_GOTOFF:
922 case BFD_RELOC_32_GOTOFF:
923 case BFD_RELOC_8_PLT_PCREL:
924 case BFD_RELOC_16_PLT_PCREL:
925 case BFD_RELOC_32_PLT_PCREL:
926 case BFD_RELOC_8_PLTOFF:
927 case BFD_RELOC_16_PLTOFF:
928 case BFD_RELOC_32_PLTOFF:
929 break;
930 default:
931 as_bad_where (fixp->fx_file, fixp->fx_line,
932 _("Cannot make %s relocation PC relative"),
933 bfd_get_reloc_code_name (code));
934 }
935 }
936 }
937 else
938 {
939 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
940 switch (F (fixp->fx_size, fixp->fx_pcrel))
941 {
942 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
943 MAP (1, 0, BFD_RELOC_8);
944 MAP (2, 0, BFD_RELOC_16);
945 MAP (4, 0, BFD_RELOC_32);
946 MAP (1, 1, BFD_RELOC_8_PCREL);
947 MAP (2, 1, BFD_RELOC_16_PCREL);
948 MAP (4, 1, BFD_RELOC_32_PCREL);
949 default:
950 abort ();
951 }
952 }
953 #undef F
954 #undef MAP
955
956 reloc = (arelent *) xmalloc (sizeof (arelent));
957 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
958 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
959 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
960 #ifndef OBJ_ELF
961 if (fixp->fx_pcrel)
962 reloc->addend = fixp->fx_addnumber;
963 else
964 reloc->addend = 0;
965 #else
966 if (!fixp->fx_pcrel)
967 reloc->addend = fixp->fx_addnumber;
968 else
969 reloc->addend = (section->vma
970 + (fixp->fx_pcrel_adjust == 64
971 ? -1 : fixp->fx_pcrel_adjust)
972 + fixp->fx_addnumber
973 + md_pcrel_from (fixp));
974 #endif
975
976 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
977 assert (reloc->howto != 0);
978
979 return reloc;
980 }
981
982 #endif /* BFD_ASSEMBLER */
983
984 /* Return zero if the reference to SYMBOL from within the same segment may
985 be relaxed. */
986 #ifdef OBJ_ELF
987
988 /* On an ELF system, we can't relax an externally visible symbol,
989 because it may be overridden by a shared library. However, if
990 TARGET_OS is "elf", then we presume that we are assembling for an
991 embedded system, in which case we don't have to worry about shared
992 libraries, and we can relax anything. */
993
994 #define relaxable_symbol(symbol) \
995 (strcmp (TARGET_OS, "elf") == 0 \
996 || (! S_IS_EXTERNAL (symbol) \
997 && ! S_IS_WEAK (symbol)))
998
999 #else
1000
1001 #define relaxable_symbol(symbol) 1
1002
1003 #endif
1004
1005 /* Handle of the OPCODE hash table. NULL means any use before
1006 m68k_ip_begin() will crash. */
1007 static struct hash_control *op_hash;
1008 \f
1009 /* Assemble an m68k instruction. */
1010
1011 static void
1012 m68k_ip (instring)
1013 char *instring;
1014 {
1015 register char *p;
1016 register struct m68k_op *opP;
1017 register const struct m68k_incant *opcode;
1018 register const char *s;
1019 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1020 char *pdot, *pdotmove;
1021 enum m68k_size siz1, siz2;
1022 char c;
1023 int losing;
1024 int opsfound;
1025 LITTLENUM_TYPE words[6];
1026 LITTLENUM_TYPE *wordp;
1027 unsigned long ok_arch = 0;
1028
1029 if (*instring == ' ')
1030 instring++; /* skip leading whitespace */
1031
1032 /* Scan up to end of operation-code, which MUST end in end-of-string
1033 or exactly 1 space. */
1034 pdot = 0;
1035 for (p = instring; *p != '\0'; p++)
1036 {
1037 if (*p == ' ')
1038 break;
1039 if (*p == '.')
1040 pdot = p;
1041 }
1042
1043 if (p == instring)
1044 {
1045 the_ins.error = _("No operator");
1046 return;
1047 }
1048
1049 /* p now points to the end of the opcode name, probably whitespace.
1050 Make sure the name is null terminated by clobbering the
1051 whitespace, look it up in the hash table, then fix it back.
1052 Remove a dot, first, since the opcode tables have none. */
1053 if (pdot != NULL)
1054 {
1055 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1056 *pdotmove = pdotmove[1];
1057 p--;
1058 }
1059
1060 c = *p;
1061 *p = '\0';
1062 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1063 *p = c;
1064
1065 if (pdot != NULL)
1066 {
1067 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1068 *pdotmove = pdotmove[-1];
1069 *pdot = '.';
1070 ++p;
1071 }
1072
1073 if (opcode == NULL)
1074 {
1075 the_ins.error = _("Unknown operator");
1076 return;
1077 }
1078
1079 /* found a legitimate opcode, start matching operands */
1080 while (*p == ' ')
1081 ++p;
1082
1083 if (opcode->m_operands == 0)
1084 {
1085 char *old = input_line_pointer;
1086 *old = '\n';
1087 input_line_pointer = p;
1088 /* Ahh - it's a motorola style psuedo op */
1089 mote_pseudo_table[opcode->m_opnum].poc_handler
1090 (mote_pseudo_table[opcode->m_opnum].poc_val);
1091 input_line_pointer = old;
1092 *old = 0;
1093
1094 return;
1095 }
1096
1097 if (flag_mri && opcode->m_opnum == 0)
1098 {
1099 /* In MRI mode, random garbage is allowed after an instruction
1100 which accepts no operands. */
1101 the_ins.args = opcode->m_operands;
1102 the_ins.numargs = opcode->m_opnum;
1103 the_ins.numo = opcode->m_codenum;
1104 the_ins.opcode[0] = getone (opcode);
1105 the_ins.opcode[1] = gettwo (opcode);
1106 return;
1107 }
1108
1109 for (opP = &the_ins.operands[0]; *p; opP++)
1110 {
1111 p = crack_operand (p, opP);
1112
1113 if (opP->error)
1114 {
1115 the_ins.error = opP->error;
1116 return;
1117 }
1118 }
1119
1120 opsfound = opP - &the_ins.operands[0];
1121
1122 /* This ugly hack is to support the floating pt opcodes in their
1123 standard form. Essentially, we fake a first enty of type COP#1 */
1124 if (opcode->m_operands[0] == 'I')
1125 {
1126 int n;
1127
1128 for (n = opsfound; n > 0; --n)
1129 the_ins.operands[n] = the_ins.operands[n - 1];
1130
1131 memset ((char *) (&the_ins.operands[0]), '\0',
1132 sizeof (the_ins.operands[0]));
1133 the_ins.operands[0].mode = CONTROL;
1134 the_ins.operands[0].reg = m68k_float_copnum;
1135 opsfound++;
1136 }
1137
1138 /* We've got the operands. Find an opcode that'll accept them */
1139 for (losing = 0;;)
1140 {
1141 /* If we didn't get the right number of ops, or we have no
1142 common model with this pattern then reject this pattern. */
1143
1144 ok_arch |= opcode->m_arch;
1145 if (opsfound != opcode->m_opnum
1146 || ((opcode->m_arch & current_architecture) == 0))
1147 ++losing;
1148 else
1149 {
1150 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1151 *s && !losing;
1152 s += 2, opP++)
1153 {
1154 /* Warning: this switch is huge! */
1155 /* I've tried to organize the cases into this order:
1156 non-alpha first, then alpha by letter. Lower-case
1157 goes directly before uppercase counterpart. */
1158 /* Code with multiple case ...: gets sorted by the lowest
1159 case ... it belongs to. I hope this makes sense. */
1160 switch (*s)
1161 {
1162 case '!':
1163 switch (opP->mode)
1164 {
1165 case IMMED:
1166 case DREG:
1167 case AREG:
1168 case FPREG:
1169 case CONTROL:
1170 case AINC:
1171 case ADEC:
1172 case REGLST:
1173 losing++;
1174 break;
1175 default:
1176 break;
1177 }
1178 break;
1179
1180 case '<':
1181 switch (opP->mode)
1182 {
1183 case DREG:
1184 case AREG:
1185 case FPREG:
1186 case CONTROL:
1187 case IMMED:
1188 case ADEC:
1189 case REGLST:
1190 losing++;
1191 break;
1192 default:
1193 break;
1194 }
1195 break;
1196
1197 case '>':
1198 switch (opP->mode)
1199 {
1200 case DREG:
1201 case AREG:
1202 case FPREG:
1203 case CONTROL:
1204 case IMMED:
1205 case AINC:
1206 case REGLST:
1207 losing++;
1208 break;
1209 case ABSL:
1210 break;
1211 default:
1212 if (opP->reg == PC
1213 || opP->reg == ZPC)
1214 losing++;
1215 break;
1216 }
1217 break;
1218
1219 case 'm':
1220 switch (opP->mode)
1221 {
1222 case DREG:
1223 case AREG:
1224 case AINDR:
1225 case AINC:
1226 case ADEC:
1227 break;
1228 default:
1229 losing++;
1230 }
1231 break;
1232
1233 case 'n':
1234 switch (opP->mode)
1235 {
1236 case DISP:
1237 break;
1238 default:
1239 losing++;
1240 }
1241 break;
1242
1243 case 'o':
1244 switch (opP->mode)
1245 {
1246 case BASE:
1247 case ABSL:
1248 case IMMED:
1249 break;
1250 default:
1251 losing++;
1252 }
1253 break;
1254
1255 case 'p':
1256 switch (opP->mode)
1257 {
1258 case DREG:
1259 case AREG:
1260 case AINDR:
1261 case AINC:
1262 case ADEC:
1263 break;
1264 case DISP:
1265 if (opP->reg == PC || opP->reg == ZPC)
1266 losing++;
1267 break;
1268 default:
1269 losing++;
1270 }
1271 break;
1272
1273 case 'q':
1274 switch (opP->mode)
1275 {
1276 case DREG:
1277 case AINDR:
1278 case AINC:
1279 case ADEC:
1280 break;
1281 case DISP:
1282 if (opP->reg == PC || opP->reg == ZPC)
1283 losing++;
1284 break;
1285 default:
1286 losing++;
1287 break;
1288 }
1289 break;
1290
1291 case 'v':
1292 switch (opP->mode)
1293 {
1294 case DREG:
1295 case AINDR:
1296 case AINC:
1297 case ADEC:
1298 case ABSL:
1299 break;
1300 case DISP:
1301 if (opP->reg == PC || opP->reg == ZPC)
1302 losing++;
1303 break;
1304 default:
1305 losing++;
1306 break;
1307 }
1308 break;
1309
1310 case '#':
1311 if (opP->mode != IMMED)
1312 losing++;
1313 else if (s[1] == 'b'
1314 && ! isvar (&opP->disp)
1315 && (opP->disp.exp.X_op != O_constant
1316 || ! isbyte (opP->disp.exp.X_add_number)))
1317 losing++;
1318 else if (s[1] == 'B'
1319 && ! isvar (&opP->disp)
1320 && (opP->disp.exp.X_op != O_constant
1321 || ! issbyte (opP->disp.exp.X_add_number)))
1322 losing++;
1323 else if (s[1] == 'w'
1324 && ! isvar (&opP->disp)
1325 && (opP->disp.exp.X_op != O_constant
1326 || ! isword (opP->disp.exp.X_add_number)))
1327 losing++;
1328 else if (s[1] == 'W'
1329 && ! isvar (&opP->disp)
1330 && (opP->disp.exp.X_op != O_constant
1331 || ! issword (opP->disp.exp.X_add_number)))
1332 losing++;
1333 break;
1334
1335 case '^':
1336 case 'T':
1337 if (opP->mode != IMMED)
1338 losing++;
1339 break;
1340
1341 case '$':
1342 if (opP->mode == AREG
1343 || opP->mode == CONTROL
1344 || opP->mode == FPREG
1345 || opP->mode == IMMED
1346 || opP->mode == REGLST
1347 || (opP->mode != ABSL
1348 && (opP->reg == PC
1349 || opP->reg == ZPC)))
1350 losing++;
1351 break;
1352
1353 case '%':
1354 if (opP->mode == CONTROL
1355 || opP->mode == FPREG
1356 || opP->mode == REGLST
1357 || opP->mode == IMMED
1358 || (opP->mode != ABSL
1359 && (opP->reg == PC
1360 || opP->reg == ZPC)))
1361 losing++;
1362 break;
1363
1364 case '&':
1365 switch (opP->mode)
1366 {
1367 case DREG:
1368 case AREG:
1369 case FPREG:
1370 case CONTROL:
1371 case IMMED:
1372 case AINC:
1373 case ADEC:
1374 case REGLST:
1375 losing++;
1376 break;
1377 case ABSL:
1378 break;
1379 default:
1380 if (opP->reg == PC
1381 || opP->reg == ZPC)
1382 losing++;
1383 break;
1384 }
1385 break;
1386
1387 case '*':
1388 if (opP->mode == CONTROL
1389 || opP->mode == FPREG
1390 || opP->mode == REGLST)
1391 losing++;
1392 break;
1393
1394 case '+':
1395 if (opP->mode != AINC)
1396 losing++;
1397 break;
1398
1399 case '-':
1400 if (opP->mode != ADEC)
1401 losing++;
1402 break;
1403
1404 case '/':
1405 switch (opP->mode)
1406 {
1407 case AREG:
1408 case CONTROL:
1409 case FPREG:
1410 case AINC:
1411 case ADEC:
1412 case IMMED:
1413 case REGLST:
1414 losing++;
1415 break;
1416 default:
1417 break;
1418 }
1419 break;
1420
1421 case ';':
1422 switch (opP->mode)
1423 {
1424 case AREG:
1425 case CONTROL:
1426 case FPREG:
1427 case REGLST:
1428 losing++;
1429 break;
1430 default:
1431 break;
1432 }
1433 break;
1434
1435 case '?':
1436 switch (opP->mode)
1437 {
1438 case AREG:
1439 case CONTROL:
1440 case FPREG:
1441 case AINC:
1442 case ADEC:
1443 case IMMED:
1444 case REGLST:
1445 losing++;
1446 break;
1447 case ABSL:
1448 break;
1449 default:
1450 if (opP->reg == PC || opP->reg == ZPC)
1451 losing++;
1452 break;
1453 }
1454 break;
1455
1456 case '@':
1457 switch (opP->mode)
1458 {
1459 case AREG:
1460 case CONTROL:
1461 case FPREG:
1462 case IMMED:
1463 case REGLST:
1464 losing++;
1465 break;
1466 default:
1467 break;
1468 }
1469 break;
1470
1471 case '~': /* For now! (JF FOO is this right?) */
1472 switch (opP->mode)
1473 {
1474 case DREG:
1475 case AREG:
1476 case CONTROL:
1477 case FPREG:
1478 case IMMED:
1479 case REGLST:
1480 losing++;
1481 break;
1482 case ABSL:
1483 break;
1484 default:
1485 if (opP->reg == PC
1486 || opP->reg == ZPC)
1487 losing++;
1488 break;
1489 }
1490 break;
1491
1492 case '3':
1493 if (opP->mode != CONTROL
1494 || (opP->reg != TT0 && opP->reg != TT1))
1495 losing++;
1496 break;
1497
1498 case 'A':
1499 if (opP->mode != AREG)
1500 losing++;
1501 break;
1502
1503 case 'a':
1504 if (opP->mode != AINDR)
1505 ++losing;
1506 break;
1507
1508 case 'B': /* FOO */
1509 if (opP->mode != ABSL
1510 || (flag_long_jumps
1511 && strncmp (instring, "jbsr", 4) == 0))
1512 losing++;
1513 break;
1514
1515 case 'C':
1516 if (opP->mode != CONTROL || opP->reg != CCR)
1517 losing++;
1518 break;
1519
1520 case 'd':
1521 if (opP->mode != DISP
1522 || opP->reg < ADDR0
1523 || opP->reg > ADDR7)
1524 losing++;
1525 break;
1526
1527 case 'D':
1528 if (opP->mode != DREG)
1529 losing++;
1530 break;
1531
1532 case 'E':
1533 if (opP->reg != ACC)
1534 losing++;
1535 break;
1536
1537 case 'F':
1538 if (opP->mode != FPREG)
1539 losing++;
1540 break;
1541
1542 case 'G':
1543 if (opP->reg != MACSR)
1544 losing++;
1545 break;
1546
1547 case 'H':
1548 if (opP->reg != MASK)
1549 losing++;
1550 break;
1551
1552 case 'I':
1553 if (opP->mode != CONTROL
1554 || opP->reg < COP0
1555 || opP->reg > COP7)
1556 losing++;
1557 break;
1558
1559 case 'J':
1560 if (opP->mode != CONTROL
1561 || opP->reg < USP
1562 || opP->reg > last_movec_reg)
1563 losing++;
1564 else
1565 {
1566 const enum m68k_register *rp;
1567 for (rp = control_regs; *rp; rp++)
1568 if (*rp == opP->reg)
1569 break;
1570 if (*rp == 0)
1571 losing++;
1572 }
1573 break;
1574
1575 case 'k':
1576 if (opP->mode != IMMED)
1577 losing++;
1578 break;
1579
1580 case 'l':
1581 case 'L':
1582 if (opP->mode == DREG
1583 || opP->mode == AREG
1584 || opP->mode == FPREG)
1585 {
1586 if (s[1] == '8')
1587 losing++;
1588 else
1589 {
1590 switch (opP->mode)
1591 {
1592 case DREG:
1593 opP->mask = 1 << (opP->reg - DATA0);
1594 break;
1595 case AREG:
1596 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1597 break;
1598 case FPREG:
1599 opP->mask = 1 << (opP->reg - FP0 + 16);
1600 break;
1601 default:
1602 abort ();
1603 }
1604 opP->mode = REGLST;
1605 }
1606 }
1607 else if (opP->mode == CONTROL)
1608 {
1609 if (s[1] != '8')
1610 losing++;
1611 else
1612 {
1613 switch (opP->reg)
1614 {
1615 case FPI:
1616 opP->mask = 1 << 24;
1617 break;
1618 case FPS:
1619 opP->mask = 1 << 25;
1620 break;
1621 case FPC:
1622 opP->mask = 1 << 26;
1623 break;
1624 default:
1625 losing++;
1626 break;
1627 }
1628 opP->mode = REGLST;
1629 }
1630 }
1631 else if (opP->mode != REGLST)
1632 losing++;
1633 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1634 losing++;
1635 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1636 losing++;
1637 break;
1638
1639 case 'M':
1640 if (opP->mode != IMMED)
1641 losing++;
1642 else if (opP->disp.exp.X_op != O_constant
1643 || ! issbyte (opP->disp.exp.X_add_number))
1644 losing++;
1645 else if (! m68k_quick
1646 && instring[3] != 'q'
1647 && instring[4] != 'q')
1648 losing++;
1649 break;
1650
1651 case 'O':
1652 if (opP->mode != DREG
1653 && opP->mode != IMMED
1654 && opP->mode != ABSL)
1655 losing++;
1656 break;
1657
1658 case 'Q':
1659 if (opP->mode != IMMED)
1660 losing++;
1661 else if (opP->disp.exp.X_op != O_constant
1662 || opP->disp.exp.X_add_number < 1
1663 || opP->disp.exp.X_add_number > 8)
1664 losing++;
1665 else if (! m68k_quick
1666 && (strncmp (instring, "add", 3) == 0
1667 || strncmp (instring, "sub", 3) == 0)
1668 && instring[3] != 'q')
1669 losing++;
1670 break;
1671
1672 case 'R':
1673 if (opP->mode != DREG && opP->mode != AREG)
1674 losing++;
1675 break;
1676
1677 case 'r':
1678 if (opP->mode != AINDR
1679 && (opP->mode != BASE
1680 || (opP->reg != 0
1681 && opP->reg != ZADDR0)
1682 || opP->disp.exp.X_op != O_absent
1683 || ((opP->index.reg < DATA0
1684 || opP->index.reg > DATA7)
1685 && (opP->index.reg < ADDR0
1686 || opP->index.reg > ADDR7))
1687 || opP->index.size != SIZE_UNSPEC
1688 || opP->index.scale != 1))
1689 losing++;
1690 break;
1691
1692 case 's':
1693 if (opP->mode != CONTROL
1694 || ! (opP->reg == FPI
1695 || opP->reg == FPS
1696 || opP->reg == FPC))
1697 losing++;
1698 break;
1699
1700 case 'S':
1701 if (opP->mode != CONTROL || opP->reg != SR)
1702 losing++;
1703 break;
1704
1705 case 't':
1706 if (opP->mode != IMMED)
1707 losing++;
1708 else if (opP->disp.exp.X_op != O_constant
1709 || opP->disp.exp.X_add_number < 0
1710 || opP->disp.exp.X_add_number > 7)
1711 losing++;
1712 break;
1713
1714 case 'U':
1715 if (opP->mode != CONTROL || opP->reg != USP)
1716 losing++;
1717 break;
1718
1719 /* JF these are out of order. We could put them
1720 in order if we were willing to put up with
1721 bunches of #ifdef m68851s in the code.
1722
1723 Don't forget that you need these operands
1724 to use 68030 MMU instructions. */
1725 #ifndef NO_68851
1726 /* Memory addressing mode used by pflushr */
1727 case '|':
1728 if (opP->mode == CONTROL
1729 || opP->mode == FPREG
1730 || opP->mode == DREG
1731 || opP->mode == AREG
1732 || opP->mode == REGLST)
1733 losing++;
1734 /* We should accept immediate operands, but they
1735 supposedly have to be quad word, and we don't
1736 handle that. I would like to see what a Motorola
1737 assembler does before doing something here. */
1738 if (opP->mode == IMMED)
1739 losing++;
1740 break;
1741
1742 case 'f':
1743 if (opP->mode != CONTROL
1744 || (opP->reg != SFC && opP->reg != DFC))
1745 losing++;
1746 break;
1747
1748 case '0':
1749 if (opP->mode != CONTROL || opP->reg != TC)
1750 losing++;
1751 break;
1752
1753 case '1':
1754 if (opP->mode != CONTROL || opP->reg != AC)
1755 losing++;
1756 break;
1757
1758 case '2':
1759 if (opP->mode != CONTROL
1760 || (opP->reg != CAL
1761 && opP->reg != VAL
1762 && opP->reg != SCC))
1763 losing++;
1764 break;
1765
1766 case 'V':
1767 if (opP->mode != CONTROL
1768 || opP->reg != VAL)
1769 losing++;
1770 break;
1771
1772 case 'W':
1773 if (opP->mode != CONTROL
1774 || (opP->reg != DRP
1775 && opP->reg != SRP
1776 && opP->reg != CRP))
1777 losing++;
1778 break;
1779
1780 case 'X':
1781 if (opP->mode != CONTROL
1782 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1783 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1784 losing++;
1785 break;
1786
1787 case 'Y':
1788 if (opP->mode != CONTROL || opP->reg != PSR)
1789 losing++;
1790 break;
1791
1792 case 'Z':
1793 if (opP->mode != CONTROL || opP->reg != PCSR)
1794 losing++;
1795 break;
1796 #endif
1797 case 'c':
1798 if (opP->mode != CONTROL
1799 || (opP->reg != NC
1800 && opP->reg != IC
1801 && opP->reg != DC
1802 && opP->reg != BC))
1803 {
1804 losing++;
1805 } /* not a cache specifier. */
1806 break;
1807
1808 case '_':
1809 if (opP->mode != ABSL)
1810 ++losing;
1811 break;
1812
1813 case 'u':
1814 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1815 losing++;
1816 /* FIXME: kludge instead of fixing parser:
1817 upper/lower registers are *not* CONTROL
1818 registers, but ordinary ones. */
1819 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1820 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1821 opP->mode = DREG;
1822 else
1823 opP->mode = AREG;
1824 break;
1825
1826 default:
1827 abort ();
1828 } /* switch on type of operand */
1829
1830 if (losing)
1831 break;
1832 } /* for each operand */
1833 } /* if immediately wrong */
1834
1835 if (!losing)
1836 {
1837 break;
1838 } /* got it. */
1839
1840 opcode = opcode->m_next;
1841
1842 if (!opcode)
1843 {
1844 if (ok_arch
1845 && !(ok_arch & current_architecture))
1846 {
1847 char buf[200], *cp;
1848
1849 strcpy (buf,
1850 _("invalid instruction for this architecture; needs "));
1851 cp = buf + strlen (buf);
1852 switch (ok_arch)
1853 {
1854 case mfloat:
1855 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1856 break;
1857 case mmmu:
1858 strcpy (cp, _("mmu (68030 or 68851)"));
1859 break;
1860 case m68020up:
1861 strcpy (cp, _("68020 or higher"));
1862 break;
1863 case m68000up:
1864 strcpy (cp, _("68000 or higher"));
1865 break;
1866 case m68010up:
1867 strcpy (cp, _("68010 or higher"));
1868 break;
1869 default:
1870 {
1871 int got_one = 0, idx;
1872 for (idx = 0;
1873 idx < (int) (sizeof (archs) / sizeof (archs[0]));
1874 idx++)
1875 {
1876 if ((archs[idx].arch & ok_arch)
1877 && ! archs[idx].alias)
1878 {
1879 if (got_one)
1880 {
1881 strcpy (cp, " or ");
1882 cp += strlen (cp);
1883 }
1884 got_one = 1;
1885 strcpy (cp, archs[idx].name);
1886 cp += strlen (cp);
1887 }
1888 }
1889 }
1890 }
1891 cp = xmalloc (strlen (buf) + 1);
1892 strcpy (cp, buf);
1893 the_ins.error = cp;
1894 }
1895 else
1896 the_ins.error = _("operands mismatch");
1897 return;
1898 } /* Fell off the end */
1899
1900 losing = 0;
1901 }
1902
1903 /* now assemble it */
1904
1905 the_ins.args = opcode->m_operands;
1906 the_ins.numargs = opcode->m_opnum;
1907 the_ins.numo = opcode->m_codenum;
1908 the_ins.opcode[0] = getone (opcode);
1909 the_ins.opcode[1] = gettwo (opcode);
1910
1911 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1912 {
1913 /* This switch is a doozy.
1914 Watch the first step; its a big one! */
1915 switch (s[0])
1916 {
1917
1918 case '*':
1919 case '~':
1920 case '%':
1921 case ';':
1922 case '@':
1923 case '!':
1924 case '&':
1925 case '$':
1926 case '?':
1927 case '/':
1928 case '<':
1929 case '>':
1930 case 'm':
1931 case 'n':
1932 case 'o':
1933 case 'p':
1934 case 'q':
1935 case 'v':
1936 #ifndef NO_68851
1937 case '|':
1938 #endif
1939 switch (opP->mode)
1940 {
1941 case IMMED:
1942 tmpreg = 0x3c; /* 7.4 */
1943 if (strchr ("bwl", s[1]))
1944 nextword = get_num (&opP->disp, 80);
1945 else
1946 nextword = get_num (&opP->disp, 0);
1947 if (isvar (&opP->disp))
1948 add_fix (s[1], &opP->disp, 0, 0);
1949 switch (s[1])
1950 {
1951 case 'b':
1952 if (!isbyte (nextword))
1953 opP->error = _("operand out of range");
1954 addword (nextword);
1955 baseo = 0;
1956 break;
1957 case 'w':
1958 if (!isword (nextword))
1959 opP->error = _("operand out of range");
1960 addword (nextword);
1961 baseo = 0;
1962 break;
1963 case 'W':
1964 if (!issword (nextword))
1965 opP->error = _("operand out of range");
1966 addword (nextword);
1967 baseo = 0;
1968 break;
1969 case 'l':
1970 addword (nextword >> 16);
1971 addword (nextword);
1972 baseo = 0;
1973 break;
1974
1975 case 'f':
1976 baseo = 2;
1977 outro = 8;
1978 break;
1979 case 'F':
1980 baseo = 4;
1981 outro = 11;
1982 break;
1983 case 'x':
1984 baseo = 6;
1985 outro = 15;
1986 break;
1987 case 'p':
1988 baseo = 6;
1989 outro = -1;
1990 break;
1991 default:
1992 abort ();
1993 }
1994 if (!baseo)
1995 break;
1996
1997 /* We gotta put out some float */
1998 if (op (&opP->disp) != O_big)
1999 {
2000 valueT val;
2001 int gencnt;
2002
2003 /* Can other cases happen here? */
2004 if (op (&opP->disp) != O_constant)
2005 abort ();
2006
2007 val = (valueT) offs (&opP->disp);
2008 gencnt = 0;
2009 do
2010 {
2011 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2012 val >>= LITTLENUM_NUMBER_OF_BITS;
2013 ++gencnt;
2014 }
2015 while (val != 0);
2016 offs (&opP->disp) = gencnt;
2017 }
2018 if (offs (&opP->disp) > 0)
2019 {
2020 if (offs (&opP->disp) > baseo)
2021 {
2022 as_warn (_("Bignum too big for %c format; truncated"),
2023 s[1]);
2024 offs (&opP->disp) = baseo;
2025 }
2026 baseo -= offs (&opP->disp);
2027 while (baseo--)
2028 addword (0);
2029 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2030 offs (&opP->disp)--;
2031 --wordp)
2032 addword (*wordp);
2033 break;
2034 }
2035 gen_to_words (words, baseo, (long) outro);
2036 for (wordp = words; baseo--; wordp++)
2037 addword (*wordp);
2038 break;
2039 case DREG:
2040 tmpreg = opP->reg - DATA; /* 0.dreg */
2041 break;
2042 case AREG:
2043 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2044 break;
2045 case AINDR:
2046 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2047 break;
2048 case ADEC:
2049 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2050 break;
2051 case AINC:
2052 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2053 break;
2054 case DISP:
2055
2056 nextword = get_num (&opP->disp, 80);
2057
2058 if (opP->reg == PC
2059 && ! isvar (&opP->disp)
2060 && m68k_abspcadd)
2061 {
2062 opP->disp.exp.X_op = O_symbol;
2063 #ifndef BFD_ASSEMBLER
2064 opP->disp.exp.X_add_symbol = &abs_symbol;
2065 #else
2066 opP->disp.exp.X_add_symbol =
2067 section_symbol (absolute_section);
2068 #endif
2069 }
2070
2071 /* Force into index mode. Hope this works */
2072
2073 /* We do the first bit for 32-bit displacements, and the
2074 second bit for 16 bit ones. It is possible that we
2075 should make the default be WORD instead of LONG, but
2076 I think that'd break GCC, so we put up with a little
2077 inefficiency for the sake of working output. */
2078
2079 if (!issword (nextword)
2080 || (isvar (&opP->disp)
2081 && ((opP->disp.size == SIZE_UNSPEC
2082 && flag_short_refs == 0
2083 && cpu_of_arch (current_architecture) >= m68020
2084 && ! arch_coldfire_p (current_architecture))
2085 || opP->disp.size == SIZE_LONG)))
2086 {
2087 if (cpu_of_arch (current_architecture) < m68020
2088 || arch_coldfire_p (current_architecture))
2089 opP->error =
2090 _("displacement too large for this architecture; needs 68020 or higher");
2091 if (opP->reg == PC)
2092 tmpreg = 0x3B; /* 7.3 */
2093 else
2094 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2095 if (isvar (&opP->disp))
2096 {
2097 if (opP->reg == PC)
2098 {
2099 if (opP->disp.size == SIZE_LONG
2100 #ifdef OBJ_ELF
2101 /* If the displacement needs pic
2102 relocation it cannot be relaxed. */
2103 || opP->disp.pic_reloc != pic_none
2104 #endif
2105 )
2106 {
2107 addword (0x0170);
2108 add_fix ('l', &opP->disp, 1, 2);
2109 }
2110 else
2111 {
2112 add_frag (adds (&opP->disp),
2113 offs (&opP->disp),
2114 TAB (PCREL1632, SZ_UNDEF));
2115 break;
2116 }
2117 }
2118 else
2119 {
2120 addword (0x0170);
2121 add_fix ('l', &opP->disp, 0, 0);
2122 }
2123 }
2124 else
2125 addword (0x0170);
2126 addword (nextword >> 16);
2127 }
2128 else
2129 {
2130 if (opP->reg == PC)
2131 tmpreg = 0x3A; /* 7.2 */
2132 else
2133 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2134
2135 if (isvar (&opP->disp))
2136 {
2137 if (opP->reg == PC)
2138 {
2139 add_fix ('w', &opP->disp, 1, 0);
2140 }
2141 else
2142 add_fix ('w', &opP->disp, 0, 0);
2143 }
2144 }
2145 addword (nextword);
2146 break;
2147
2148 case POST:
2149 case PRE:
2150 case BASE:
2151 nextword = 0;
2152 baseo = get_num (&opP->disp, 80);
2153 if (opP->mode == POST || opP->mode == PRE)
2154 outro = get_num (&opP->odisp, 80);
2155 /* Figure out the `addressing mode'.
2156 Also turn on the BASE_DISABLE bit, if needed. */
2157 if (opP->reg == PC || opP->reg == ZPC)
2158 {
2159 tmpreg = 0x3b; /* 7.3 */
2160 if (opP->reg == ZPC)
2161 nextword |= 0x80;
2162 }
2163 else if (opP->reg == 0)
2164 {
2165 nextword |= 0x80;
2166 tmpreg = 0x30; /* 6.garbage */
2167 }
2168 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2169 {
2170 nextword |= 0x80;
2171 tmpreg = 0x30 + opP->reg - ZADDR0;
2172 }
2173 else
2174 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2175
2176 siz1 = opP->disp.size;
2177 if (opP->mode == POST || opP->mode == PRE)
2178 siz2 = opP->odisp.size;
2179 else
2180 siz2 = SIZE_UNSPEC;
2181
2182 /* Index register stuff */
2183 if (opP->index.reg != 0
2184 && opP->index.reg >= DATA
2185 && opP->index.reg <= ADDR7)
2186 {
2187 nextword |= (opP->index.reg - DATA) << 12;
2188
2189 if (opP->index.size == SIZE_LONG
2190 || (opP->index.size == SIZE_UNSPEC
2191 && m68k_index_width_default == SIZE_LONG))
2192 nextword |= 0x800;
2193
2194 if ((opP->index.scale != 1
2195 && cpu_of_arch (current_architecture) < m68020)
2196 || (opP->index.scale == 8
2197 && arch_coldfire_p (current_architecture)))
2198 {
2199 opP->error =
2200 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2201 }
2202
2203 if (arch_coldfire_p (current_architecture)
2204 && opP->index.size == SIZE_WORD)
2205 opP->error = _("invalid index size for coldfire");
2206
2207 switch (opP->index.scale)
2208 {
2209 case 1:
2210 break;
2211 case 2:
2212 nextword |= 0x200;
2213 break;
2214 case 4:
2215 nextword |= 0x400;
2216 break;
2217 case 8:
2218 nextword |= 0x600;
2219 break;
2220 default:
2221 abort ();
2222 }
2223 /* IF its simple,
2224 GET US OUT OF HERE! */
2225
2226 /* Must be INDEX, with an index register. Address
2227 register cannot be ZERO-PC, and either :b was
2228 forced, or we know it will fit. For a 68000 or
2229 68010, force this mode anyways, because the
2230 larger modes aren't supported. */
2231 if (opP->mode == BASE
2232 && ((opP->reg >= ADDR0
2233 && opP->reg <= ADDR7)
2234 || opP->reg == PC))
2235 {
2236 if (siz1 == SIZE_BYTE
2237 || cpu_of_arch (current_architecture) < m68020
2238 || arch_coldfire_p (current_architecture)
2239 || (siz1 == SIZE_UNSPEC
2240 && ! isvar (&opP->disp)
2241 && issbyte (baseo)))
2242 {
2243 nextword += baseo & 0xff;
2244 addword (nextword);
2245 if (isvar (&opP->disp))
2246 {
2247 /* Do a byte relocation. If it doesn't
2248 fit (possible on m68000) let the
2249 fixup processing complain later. */
2250 if (opP->reg == PC)
2251 add_fix ('B', &opP->disp, 1, 1);
2252 else
2253 add_fix ('B', &opP->disp, 0, 0);
2254 }
2255 else if (siz1 != SIZE_BYTE)
2256 {
2257 if (siz1 != SIZE_UNSPEC)
2258 as_warn (_("Forcing byte displacement"));
2259 if (! issbyte (baseo))
2260 opP->error = _("byte displacement out of range");
2261 }
2262
2263 break;
2264 }
2265 else if (siz1 == SIZE_UNSPEC
2266 && opP->reg == PC
2267 && isvar (&opP->disp)
2268 && subs (&opP->disp) == NULL
2269 #ifdef OBJ_ELF
2270 /* If the displacement needs pic
2271 relocation it cannot be relaxed. */
2272 && opP->disp.pic_reloc == pic_none
2273 #endif
2274 )
2275 {
2276 /* The code in md_convert_frag_1 needs to be
2277 able to adjust nextword. Call frag_grow
2278 to ensure that we have enough space in
2279 the frag obstack to make all the bytes
2280 contiguous. */
2281 frag_grow (14);
2282 nextword += baseo & 0xff;
2283 addword (nextword);
2284 add_frag (adds (&opP->disp), offs (&opP->disp),
2285 TAB (PCINDEX, SZ_UNDEF));
2286
2287 break;
2288 }
2289 }
2290 }
2291 else
2292 {
2293 nextword |= 0x40; /* No index reg */
2294 if (opP->index.reg >= ZDATA0
2295 && opP->index.reg <= ZDATA7)
2296 nextword |= (opP->index.reg - ZDATA0) << 12;
2297 else if (opP->index.reg >= ZADDR0
2298 || opP->index.reg <= ZADDR7)
2299 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2300 }
2301
2302 /* It isn't simple. */
2303
2304 if (cpu_of_arch (current_architecture) < m68020
2305 || arch_coldfire_p (current_architecture))
2306 opP->error =
2307 _("invalid operand mode for this architecture; needs 68020 or higher");
2308
2309 nextword |= 0x100;
2310 /* If the guy specified a width, we assume that it is
2311 wide enough. Maybe it isn't. If so, we lose. */
2312 switch (siz1)
2313 {
2314 case SIZE_UNSPEC:
2315 if (isvar (&opP->disp)
2316 ? m68k_rel32
2317 : ! issword (baseo))
2318 {
2319 siz1 = SIZE_LONG;
2320 nextword |= 0x30;
2321 }
2322 else if (! isvar (&opP->disp) && baseo == 0)
2323 nextword |= 0x10;
2324 else
2325 {
2326 nextword |= 0x20;
2327 siz1 = SIZE_WORD;
2328 }
2329 break;
2330 case SIZE_BYTE:
2331 as_warn (_(":b not permitted; defaulting to :w"));
2332 /* Fall through. */
2333 case SIZE_WORD:
2334 nextword |= 0x20;
2335 break;
2336 case SIZE_LONG:
2337 nextword |= 0x30;
2338 break;
2339 }
2340
2341 /* Figure out innner displacement stuff */
2342 if (opP->mode == POST || opP->mode == PRE)
2343 {
2344 if (cpu_of_arch (current_architecture) & cpu32)
2345 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2346 switch (siz2)
2347 {
2348 case SIZE_UNSPEC:
2349 if (isvar (&opP->odisp)
2350 ? m68k_rel32
2351 : ! issword (outro))
2352 {
2353 siz2 = SIZE_LONG;
2354 nextword |= 0x3;
2355 }
2356 else if (! isvar (&opP->odisp) && outro == 0)
2357 nextword |= 0x1;
2358 else
2359 {
2360 nextword |= 0x2;
2361 siz2 = SIZE_WORD;
2362 }
2363 break;
2364 case 1:
2365 as_warn (_(":b not permitted; defaulting to :w"));
2366 /* Fall through. */
2367 case 2:
2368 nextword |= 0x2;
2369 break;
2370 case 3:
2371 nextword |= 0x3;
2372 break;
2373 }
2374 if (opP->mode == POST
2375 && (nextword & 0x40) == 0)
2376 nextword |= 0x04;
2377 }
2378 addword (nextword);
2379
2380 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2381 {
2382 if (opP->reg == PC || opP->reg == ZPC)
2383 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2384 else
2385 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2386 }
2387 if (siz1 == SIZE_LONG)
2388 addword (baseo >> 16);
2389 if (siz1 != SIZE_UNSPEC)
2390 addword (baseo);
2391
2392 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2393 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2394 if (siz2 == SIZE_LONG)
2395 addword (outro >> 16);
2396 if (siz2 != SIZE_UNSPEC)
2397 addword (outro);
2398
2399 break;
2400
2401 case ABSL:
2402 nextword = get_num (&opP->disp, 80);
2403 switch (opP->disp.size)
2404 {
2405 default:
2406 abort ();
2407 case SIZE_UNSPEC:
2408 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2409 {
2410 tmpreg = 0x38; /* 7.0 */
2411 addword (nextword);
2412 break;
2413 }
2414 if (isvar (&opP->disp)
2415 && !subs (&opP->disp)
2416 && adds (&opP->disp)
2417 #ifdef OBJ_ELF
2418 /* If the displacement needs pic relocation it
2419 cannot be relaxed. */
2420 && opP->disp.pic_reloc == pic_none
2421 #endif
2422 && !flag_long_jumps
2423 && !strchr ("~%&$?", s[0]))
2424 {
2425 tmpreg = 0x3A; /* 7.2 */
2426 add_frag (adds (&opP->disp),
2427 offs (&opP->disp),
2428 TAB (ABSTOPCREL, SZ_UNDEF));
2429 break;
2430 }
2431 /* Fall through into long */
2432 case SIZE_LONG:
2433 if (isvar (&opP->disp))
2434 add_fix ('l', &opP->disp, 0, 0);
2435
2436 tmpreg = 0x39;/* 7.1 mode */
2437 addword (nextword >> 16);
2438 addword (nextword);
2439 break;
2440
2441 case SIZE_BYTE:
2442 as_bad (_("unsupported byte value; use a different suffix"));
2443 /* Fall through. */
2444 case SIZE_WORD: /* Word */
2445 if (isvar (&opP->disp))
2446 add_fix ('w', &opP->disp, 0, 0);
2447
2448 tmpreg = 0x38;/* 7.0 mode */
2449 addword (nextword);
2450 break;
2451 }
2452 break;
2453 case CONTROL:
2454 case FPREG:
2455 default:
2456 as_bad (_("unknown/incorrect operand"));
2457 /* abort (); */
2458 }
2459 install_gen_operand (s[1], tmpreg);
2460 break;
2461
2462 case '#':
2463 case '^':
2464 switch (s[1])
2465 { /* JF: I hate floating point! */
2466 case 'j':
2467 tmpreg = 70;
2468 break;
2469 case '8':
2470 tmpreg = 20;
2471 break;
2472 case 'C':
2473 tmpreg = 50;
2474 break;
2475 case '3':
2476 default:
2477 tmpreg = 80;
2478 break;
2479 }
2480 tmpreg = get_num (&opP->disp, tmpreg);
2481 if (isvar (&opP->disp))
2482 add_fix (s[1], &opP->disp, 0, 0);
2483 switch (s[1])
2484 {
2485 case 'b': /* Danger: These do no check for
2486 certain types of overflow.
2487 user beware! */
2488 if (!isbyte (tmpreg))
2489 opP->error = _("out of range");
2490 insop (tmpreg, opcode);
2491 if (isvar (&opP->disp))
2492 the_ins.reloc[the_ins.nrel - 1].n =
2493 (opcode->m_codenum) * 2 + 1;
2494 break;
2495 case 'B':
2496 if (!issbyte (tmpreg))
2497 opP->error = _("out of range");
2498 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2499 if (isvar (&opP->disp))
2500 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2501 break;
2502 case 'w':
2503 if (!isword (tmpreg))
2504 opP->error = _("out of range");
2505 insop (tmpreg, opcode);
2506 if (isvar (&opP->disp))
2507 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2508 break;
2509 case 'W':
2510 if (!issword (tmpreg))
2511 opP->error = _("out of range");
2512 insop (tmpreg, opcode);
2513 if (isvar (&opP->disp))
2514 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2515 break;
2516 case 'l':
2517 /* Because of the way insop works, we put these two out
2518 backwards. */
2519 insop (tmpreg, opcode);
2520 insop (tmpreg >> 16, opcode);
2521 if (isvar (&opP->disp))
2522 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2523 break;
2524 case '3':
2525 tmpreg &= 0xFF;
2526 case '8':
2527 case 'C':
2528 case 'j':
2529 install_operand (s[1], tmpreg);
2530 break;
2531 default:
2532 abort ();
2533 }
2534 break;
2535
2536 case '+':
2537 case '-':
2538 case 'A':
2539 case 'a':
2540 install_operand (s[1], opP->reg - ADDR);
2541 break;
2542
2543 case 'B':
2544 tmpreg = get_num (&opP->disp, 80);
2545 switch (s[1])
2546 {
2547 case 'B':
2548 /* The pc_fix argument winds up in fx_pcrel_adjust,
2549 which is a char, and may therefore be unsigned. We
2550 want to pass -1, but we pass 64 instead, and convert
2551 back in md_pcrel_from. */
2552 add_fix ('B', &opP->disp, 1, 64);
2553 break;
2554 case 'W':
2555 add_fix ('w', &opP->disp, 1, 0);
2556 addword (0);
2557 break;
2558 case 'L':
2559 long_branch:
2560 if (! HAVE_LONG_BRANCH (current_architecture))
2561 as_warn (_("Can't use long branches on 68000/68010/5200"));
2562 the_ins.opcode[0] |= 0xff;
2563 add_fix ('l', &opP->disp, 1, 0);
2564 addword (0);
2565 addword (0);
2566 break;
2567 case 'g':
2568 if (subs (&opP->disp)) /* We can't relax it */
2569 goto long_branch;
2570
2571 #ifdef OBJ_ELF
2572 /* If the displacement needs pic relocation it cannot be
2573 relaxed. */
2574 if (opP->disp.pic_reloc != pic_none)
2575 goto long_branch;
2576 #endif
2577 /* This could either be a symbol, or an absolute
2578 address. If it's an absolute address, turn it into
2579 an absolute jump right here and keep it out of the
2580 relaxer. */
2581 if (adds (&opP->disp) == 0)
2582 {
2583 if (the_ins.opcode[0] == 0x6000) /* jbra */
2584 the_ins.opcode[0] = 0x4EF1;
2585 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2586 the_ins.opcode[0] = 0x4EB1;
2587 else /* jCC */
2588 {
2589 the_ins.opcode[0] ^= 0x0100;
2590 the_ins.opcode[0] |= 0x0006;
2591 addword (0x4EF1);
2592 }
2593 add_fix ('l', &opP->disp, 0, 0);
2594 addword (0);
2595 addword (0);
2596 break;
2597 }
2598
2599 /* Now we know it's going into the relaxer. Now figure
2600 out which mode. We try in this order of preference:
2601 long branch, absolute jump, byte/word branches only. */
2602 if (HAVE_LONG_BRANCH (current_architecture))
2603 add_frag (adds (&opP->disp), offs (&opP->disp),
2604 TAB (BRANCHBWL, SZ_UNDEF));
2605 else if (! flag_keep_pcrel)
2606 {
2607 if ((the_ins.opcode[0] == 0x6000)
2608 || (the_ins.opcode[0] == 0x6100))
2609 add_frag (adds (&opP->disp), offs (&opP->disp),
2610 TAB (BRABSJUNC, SZ_UNDEF));
2611 else
2612 add_frag (adds (&opP->disp), offs (&opP->disp),
2613 TAB (BRABSJCOND, SZ_UNDEF));
2614 }
2615 else
2616 add_frag (adds (&opP->disp), offs (&opP->disp),
2617 TAB (BRANCHBW, SZ_UNDEF));
2618 break;
2619 case 'w':
2620 if (isvar (&opP->disp))
2621 {
2622 /* Check for DBcc instructions. We can relax them,
2623 but only if we have long branches and/or absolute
2624 jumps. */
2625 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2626 && (HAVE_LONG_BRANCH (current_architecture)
2627 || (! flag_keep_pcrel)))
2628 {
2629 if (HAVE_LONG_BRANCH (current_architecture))
2630 add_frag (adds (&opP->disp), offs (&opP->disp),
2631 TAB (DBCCLBR, SZ_UNDEF));
2632 else
2633 add_frag (adds (&opP->disp), offs (&opP->disp),
2634 TAB (DBCCABSJ, SZ_UNDEF));
2635 break;
2636 }
2637 add_fix ('w', &opP->disp, 1, 0);
2638 }
2639 addword (0);
2640 break;
2641 case 'C': /* Fixed size LONG coproc branches */
2642 add_fix ('l', &opP->disp, 1, 0);
2643 addword (0);
2644 addword (0);
2645 break;
2646 case 'c': /* Var size Coprocesssor branches */
2647 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
2648 {
2649 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2650 add_fix ('l', &opP->disp, 1, 0);
2651 addword (0);
2652 addword (0);
2653 }
2654 else
2655 add_frag (adds (&opP->disp), offs (&opP->disp),
2656 TAB (FBRANCH, SZ_UNDEF));
2657 break;
2658 default:
2659 abort ();
2660 }
2661 break;
2662
2663 case 'C': /* Ignore it */
2664 break;
2665
2666 case 'd': /* JF this is a kludge */
2667 install_operand ('s', opP->reg - ADDR);
2668 tmpreg = get_num (&opP->disp, 80);
2669 if (!issword (tmpreg))
2670 {
2671 as_warn (_("Expression out of range, using 0"));
2672 tmpreg = 0;
2673 }
2674 addword (tmpreg);
2675 break;
2676
2677 case 'D':
2678 install_operand (s[1], opP->reg - DATA);
2679 break;
2680
2681 case 'E': /* Ignore it */
2682 break;
2683
2684 case 'F':
2685 install_operand (s[1], opP->reg - FP0);
2686 break;
2687
2688 case 'G': /* Ignore it */
2689 case 'H':
2690 break;
2691
2692 case 'I':
2693 tmpreg = opP->reg - COP0;
2694 install_operand (s[1], tmpreg);
2695 break;
2696
2697 case 'J': /* JF foo */
2698 switch (opP->reg)
2699 {
2700 case SFC:
2701 tmpreg = 0x000;
2702 break;
2703 case DFC:
2704 tmpreg = 0x001;
2705 break;
2706 case CACR:
2707 tmpreg = 0x002;
2708 break;
2709 case TC:
2710 tmpreg = 0x003;
2711 break;
2712 case ITT0:
2713 tmpreg = 0x004;
2714 break;
2715 case ITT1:
2716 tmpreg = 0x005;
2717 break;
2718 case DTT0:
2719 tmpreg = 0x006;
2720 break;
2721 case DTT1:
2722 tmpreg = 0x007;
2723 break;
2724 case BUSCR:
2725 tmpreg = 0x008;
2726 break;
2727
2728 case USP:
2729 tmpreg = 0x800;
2730 break;
2731 case VBR:
2732 tmpreg = 0x801;
2733 break;
2734 case CAAR:
2735 tmpreg = 0x802;
2736 break;
2737 case MSP:
2738 tmpreg = 0x803;
2739 break;
2740 case ISP:
2741 tmpreg = 0x804;
2742 break;
2743 case MMUSR:
2744 tmpreg = 0x805;
2745 break;
2746 case URP:
2747 tmpreg = 0x806;
2748 break;
2749 case SRP:
2750 tmpreg = 0x807;
2751 break;
2752 case PCR:
2753 tmpreg = 0x808;
2754 break;
2755 case ROMBAR:
2756 tmpreg = 0xC00;
2757 break;
2758 case RAMBAR0:
2759 tmpreg = 0xC04;
2760 break;
2761 case RAMBAR1:
2762 tmpreg = 0xC05;
2763 break;
2764 case MBAR:
2765 tmpreg = 0xC0F;
2766 break;
2767 default:
2768 abort ();
2769 }
2770 install_operand (s[1], tmpreg);
2771 break;
2772
2773 case 'k':
2774 tmpreg = get_num (&opP->disp, 55);
2775 install_operand (s[1], tmpreg & 0x7f);
2776 break;
2777
2778 case 'l':
2779 tmpreg = opP->mask;
2780 if (s[1] == 'w')
2781 {
2782 if (tmpreg & 0x7FF0000)
2783 as_bad (_("Floating point register in register list"));
2784 insop (reverse_16_bits (tmpreg), opcode);
2785 }
2786 else
2787 {
2788 if (tmpreg & 0x700FFFF)
2789 as_bad (_("Wrong register in floating-point reglist"));
2790 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2791 }
2792 break;
2793
2794 case 'L':
2795 tmpreg = opP->mask;
2796 if (s[1] == 'w')
2797 {
2798 if (tmpreg & 0x7FF0000)
2799 as_bad (_("Floating point register in register list"));
2800 insop (tmpreg, opcode);
2801 }
2802 else if (s[1] == '8')
2803 {
2804 if (tmpreg & 0x0FFFFFF)
2805 as_bad (_("incorrect register in reglist"));
2806 install_operand (s[1], tmpreg >> 24);
2807 }
2808 else
2809 {
2810 if (tmpreg & 0x700FFFF)
2811 as_bad (_("wrong register in floating-point reglist"));
2812 else
2813 install_operand (s[1], tmpreg >> 16);
2814 }
2815 break;
2816
2817 case 'M':
2818 install_operand (s[1], get_num (&opP->disp, 60));
2819 break;
2820
2821 case 'O':
2822 tmpreg = ((opP->mode == DREG)
2823 ? 0x20 + (int) (opP->reg - DATA)
2824 : (get_num (&opP->disp, 40) & 0x1F));
2825 install_operand (s[1], tmpreg);
2826 break;
2827
2828 case 'Q':
2829 tmpreg = get_num (&opP->disp, 10);
2830 if (tmpreg == 8)
2831 tmpreg = 0;
2832 install_operand (s[1], tmpreg);
2833 break;
2834
2835 case 'R':
2836 /* This depends on the fact that ADDR registers are eight
2837 more than their corresponding DATA regs, so the result
2838 will have the ADDR_REG bit set */
2839 install_operand (s[1], opP->reg - DATA);
2840 break;
2841
2842 case 'r':
2843 if (opP->mode == AINDR)
2844 install_operand (s[1], opP->reg - DATA);
2845 else
2846 install_operand (s[1], opP->index.reg - DATA);
2847 break;
2848
2849 case 's':
2850 if (opP->reg == FPI)
2851 tmpreg = 0x1;
2852 else if (opP->reg == FPS)
2853 tmpreg = 0x2;
2854 else if (opP->reg == FPC)
2855 tmpreg = 0x4;
2856 else
2857 abort ();
2858 install_operand (s[1], tmpreg);
2859 break;
2860
2861 case 'S': /* Ignore it */
2862 break;
2863
2864 case 'T':
2865 install_operand (s[1], get_num (&opP->disp, 30));
2866 break;
2867
2868 case 'U': /* Ignore it */
2869 break;
2870
2871 case 'c':
2872 switch (opP->reg)
2873 {
2874 case NC:
2875 tmpreg = 0;
2876 break;
2877 case DC:
2878 tmpreg = 1;
2879 break;
2880 case IC:
2881 tmpreg = 2;
2882 break;
2883 case BC:
2884 tmpreg = 3;
2885 break;
2886 default:
2887 as_fatal (_("failed sanity check"));
2888 } /* switch on cache token */
2889 install_operand (s[1], tmpreg);
2890 break;
2891 #ifndef NO_68851
2892 /* JF: These are out of order, I fear. */
2893 case 'f':
2894 switch (opP->reg)
2895 {
2896 case SFC:
2897 tmpreg = 0;
2898 break;
2899 case DFC:
2900 tmpreg = 1;
2901 break;
2902 default:
2903 abort ();
2904 }
2905 install_operand (s[1], tmpreg);
2906 break;
2907
2908 case '0':
2909 case '1':
2910 case '2':
2911 switch (opP->reg)
2912 {
2913 case TC:
2914 tmpreg = 0;
2915 break;
2916 case CAL:
2917 tmpreg = 4;
2918 break;
2919 case VAL:
2920 tmpreg = 5;
2921 break;
2922 case SCC:
2923 tmpreg = 6;
2924 break;
2925 case AC:
2926 tmpreg = 7;
2927 break;
2928 default:
2929 abort ();
2930 }
2931 install_operand (s[1], tmpreg);
2932 break;
2933
2934 case 'V':
2935 if (opP->reg == VAL)
2936 break;
2937 abort ();
2938
2939 case 'W':
2940 switch (opP->reg)
2941 {
2942 case DRP:
2943 tmpreg = 1;
2944 break;
2945 case SRP:
2946 tmpreg = 2;
2947 break;
2948 case CRP:
2949 tmpreg = 3;
2950 break;
2951 default:
2952 abort ();
2953 }
2954 install_operand (s[1], tmpreg);
2955 break;
2956
2957 case 'X':
2958 switch (opP->reg)
2959 {
2960 case BAD:
2961 case BAD + 1:
2962 case BAD + 2:
2963 case BAD + 3:
2964 case BAD + 4:
2965 case BAD + 5:
2966 case BAD + 6:
2967 case BAD + 7:
2968 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2969 break;
2970
2971 case BAC:
2972 case BAC + 1:
2973 case BAC + 2:
2974 case BAC + 3:
2975 case BAC + 4:
2976 case BAC + 5:
2977 case BAC + 6:
2978 case BAC + 7:
2979 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2980 break;
2981
2982 default:
2983 abort ();
2984 }
2985 install_operand (s[1], tmpreg);
2986 break;
2987 case 'Y':
2988 know (opP->reg == PSR);
2989 break;
2990 case 'Z':
2991 know (opP->reg == PCSR);
2992 break;
2993 #endif /* m68851 */
2994 case '3':
2995 switch (opP->reg)
2996 {
2997 case TT0:
2998 tmpreg = 2;
2999 break;
3000 case TT1:
3001 tmpreg = 3;
3002 break;
3003 default:
3004 abort ();
3005 }
3006 install_operand (s[1], tmpreg);
3007 break;
3008 case 't':
3009 tmpreg = get_num (&opP->disp, 20);
3010 install_operand (s[1], tmpreg);
3011 break;
3012 case '_': /* used only for move16 absolute 32-bit address */
3013 if (isvar (&opP->disp))
3014 add_fix ('l', &opP->disp, 0, 0);
3015 tmpreg = get_num (&opP->disp, 80);
3016 addword (tmpreg >> 16);
3017 addword (tmpreg & 0xFFFF);
3018 break;
3019 case 'u':
3020 install_operand (s[1], opP->reg - DATA0L);
3021 opP->reg -= (DATA0L);
3022 opP->reg &= 0x0F; /* remove upper/lower bit */
3023 break;
3024 default:
3025 abort ();
3026 }
3027 }
3028
3029 /* By the time whe get here (FINALLY) the_ins contains the complete
3030 instruction, ready to be emitted. . . */
3031 }
3032
3033 static int
3034 reverse_16_bits (in)
3035 int in;
3036 {
3037 int out = 0;
3038 int n;
3039
3040 static int mask[16] =
3041 {
3042 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3043 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3044 };
3045 for (n = 0; n < 16; n++)
3046 {
3047 if (in & mask[n])
3048 out |= mask[15 - n];
3049 }
3050 return out;
3051 } /* reverse_16_bits() */
3052
3053 static int
3054 reverse_8_bits (in)
3055 int in;
3056 {
3057 int out = 0;
3058 int n;
3059
3060 static int mask[8] =
3061 {
3062 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3063 };
3064
3065 for (n = 0; n < 8; n++)
3066 {
3067 if (in & mask[n])
3068 out |= mask[7 - n];
3069 }
3070 return out;
3071 } /* reverse_8_bits() */
3072
3073 /* Cause an extra frag to be generated here, inserting up to 10 bytes
3074 (that value is chosen in the frag_var call in md_assemble). TYPE
3075 is the subtype of the frag to be generated; its primary type is
3076 rs_machine_dependent.
3077
3078 The TYPE parameter is also used by md_convert_frag_1 and
3079 md_estimate_size_before_relax. The appropriate type of fixup will
3080 be emitted by md_convert_frag_1.
3081
3082 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3083 static void
3084 install_operand (mode, val)
3085 int mode;
3086 int val;
3087 {
3088 switch (mode)
3089 {
3090 case 's':
3091 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3092 break;
3093 case 'd':
3094 the_ins.opcode[0] |= val << 9;
3095 break;
3096 case '1':
3097 the_ins.opcode[1] |= val << 12;
3098 break;
3099 case '2':
3100 the_ins.opcode[1] |= val << 6;
3101 break;
3102 case '3':
3103 the_ins.opcode[1] |= val;
3104 break;
3105 case '4':
3106 the_ins.opcode[2] |= val << 12;
3107 break;
3108 case '5':
3109 the_ins.opcode[2] |= val << 6;
3110 break;
3111 case '6':
3112 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3113 three words long! */
3114 the_ins.numo++;
3115 the_ins.opcode[2] |= val;
3116 break;
3117 case '7':
3118 the_ins.opcode[1] |= val << 7;
3119 break;
3120 case '8':
3121 the_ins.opcode[1] |= val << 10;
3122 break;
3123 #ifndef NO_68851
3124 case '9':
3125 the_ins.opcode[1] |= val << 5;
3126 break;
3127 #endif
3128
3129 case 't':
3130 the_ins.opcode[1] |= (val << 10) | (val << 7);
3131 break;
3132 case 'D':
3133 the_ins.opcode[1] |= (val << 12) | val;
3134 break;
3135 case 'g':
3136 the_ins.opcode[0] |= val = 0xff;
3137 break;
3138 case 'i':
3139 the_ins.opcode[0] |= val << 9;
3140 break;
3141 case 'C':
3142 the_ins.opcode[1] |= val;
3143 break;
3144 case 'j':
3145 the_ins.opcode[1] |= val;
3146 the_ins.numo++; /* What a hack */
3147 break;
3148 case 'k':
3149 the_ins.opcode[1] |= val << 4;
3150 break;
3151 case 'b':
3152 case 'w':
3153 case 'W':
3154 case 'l':
3155 break;
3156 case 'e':
3157 the_ins.opcode[0] |= (val << 6);
3158 break;
3159 case 'L':
3160 the_ins.opcode[1] = (val >> 16);
3161 the_ins.opcode[2] = val & 0xffff;
3162 break;
3163 case 'm':
3164 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3165 the_ins.opcode[0] |= ((val & 0x7) << 9);
3166 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3167 break;
3168 case 'n':
3169 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3170 the_ins.opcode[0] |= ((val & 0x7) << 9);
3171 break;
3172 case 'o':
3173 the_ins.opcode[1] |= val << 12;
3174 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3175 break;
3176 case 'M':
3177 the_ins.opcode[0] |= (val & 0xF);
3178 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3179 break;
3180 case 'N':
3181 the_ins.opcode[1] |= (val & 0xF);
3182 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3183 break;
3184 case 'h':
3185 the_ins.opcode[1] |= ((val != 1) << 10);
3186 break;
3187 case 'c':
3188 default:
3189 as_fatal (_("failed sanity check."));
3190 }
3191 } /* install_operand() */
3192
3193 static void
3194 install_gen_operand (mode, val)
3195 int mode;
3196 int val;
3197 {
3198 switch (mode)
3199 {
3200 case 's':
3201 the_ins.opcode[0] |= val;
3202 break;
3203 case 'd':
3204 /* This is a kludge!!! */
3205 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3206 break;
3207 case 'b':
3208 case 'w':
3209 case 'l':
3210 case 'f':
3211 case 'F':
3212 case 'x':
3213 case 'p':
3214 the_ins.opcode[0] |= val;
3215 break;
3216 /* more stuff goes here */
3217 default:
3218 as_fatal (_("failed sanity check."));
3219 }
3220 } /* install_gen_operand() */
3221
3222 /*
3223 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3224 * then deal with the bitfield hack.
3225 */
3226
3227 static char *
3228 crack_operand (str, opP)
3229 register char *str;
3230 register struct m68k_op *opP;
3231 {
3232 register int parens;
3233 register int c;
3234 register char *beg_str;
3235 int inquote = 0;
3236
3237 if (!str)
3238 {
3239 return str;
3240 }
3241 beg_str = str;
3242 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3243 {
3244 if (! inquote)
3245 {
3246 if (*str == '(')
3247 parens++;
3248 else if (*str == ')')
3249 {
3250 if (!parens)
3251 { /* ERROR */
3252 opP->error = _("Extra )");
3253 return str;
3254 }
3255 --parens;
3256 }
3257 }
3258 if (flag_mri && *str == '\'')
3259 inquote = ! inquote;
3260 }
3261 if (!*str && parens)
3262 { /* ERROR */
3263 opP->error = _("Missing )");
3264 return str;
3265 }
3266 c = *str;
3267 *str = '\0';
3268 if (m68k_ip_op (beg_str, opP) != 0)
3269 {
3270 *str = c;
3271 return str;
3272 }
3273 *str = c;
3274 if (c == '}')
3275 c = *++str; /* JF bitfield hack */
3276 if (c)
3277 {
3278 c = *++str;
3279 if (!c)
3280 as_bad (_("Missing operand"));
3281 }
3282
3283 /* Detect MRI REG symbols and convert them to REGLSTs. */
3284 if (opP->mode == CONTROL && (int)opP->reg < 0)
3285 {
3286 opP->mode = REGLST;
3287 opP->mask = ~(int)opP->reg;
3288 opP->reg = 0;
3289 }
3290
3291 return str;
3292 }
3293
3294 /* This is the guts of the machine-dependent assembler. STR points to a
3295 machine dependent instruction. This function is supposed to emit
3296 the frags/bytes it assembles to.
3297 */
3298
3299 static void
3300 insert_reg (regname, regnum)
3301 const char *regname;
3302 int regnum;
3303 {
3304 char buf[100];
3305 int i;
3306
3307 #ifdef REGISTER_PREFIX
3308 if (!flag_reg_prefix_optional)
3309 {
3310 buf[0] = REGISTER_PREFIX;
3311 strcpy (buf + 1, regname);
3312 regname = buf;
3313 }
3314 #endif
3315
3316 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3317 &zero_address_frag));
3318
3319 for (i = 0; regname[i]; i++)
3320 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3321 buf[i] = '\0';
3322
3323 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3324 &zero_address_frag));
3325 }
3326
3327 struct init_entry
3328 {
3329 const char *name;
3330 int number;
3331 };
3332
3333 static const struct init_entry init_table[] =
3334 {
3335 { "d0", DATA0 },
3336 { "d1", DATA1 },
3337 { "d2", DATA2 },
3338 { "d3", DATA3 },
3339 { "d4", DATA4 },
3340 { "d5", DATA5 },
3341 { "d6", DATA6 },
3342 { "d7", DATA7 },
3343 { "a0", ADDR0 },
3344 { "a1", ADDR1 },
3345 { "a2", ADDR2 },
3346 { "a3", ADDR3 },
3347 { "a4", ADDR4 },
3348 { "a5", ADDR5 },
3349 { "a6", ADDR6 },
3350 { "fp", ADDR6 },
3351 { "a7", ADDR7 },
3352 { "sp", ADDR7 },
3353 { "ssp", ADDR7 },
3354 { "fp0", FP0 },
3355 { "fp1", FP1 },
3356 { "fp2", FP2 },
3357 { "fp3", FP3 },
3358 { "fp4", FP4 },
3359 { "fp5", FP5 },
3360 { "fp6", FP6 },
3361 { "fp7", FP7 },
3362 { "fpi", FPI },
3363 { "fpiar", FPI },
3364 { "fpc", FPI },
3365 { "fps", FPS },
3366 { "fpsr", FPS },
3367 { "fpc", FPC },
3368 { "fpcr", FPC },
3369 { "control", FPC },
3370 { "status", FPS },
3371 { "iaddr", FPI },
3372
3373 { "cop0", COP0 },
3374 { "cop1", COP1 },
3375 { "cop2", COP2 },
3376 { "cop3", COP3 },
3377 { "cop4", COP4 },
3378 { "cop5", COP5 },
3379 { "cop6", COP6 },
3380 { "cop7", COP7 },
3381 { "pc", PC },
3382 { "zpc", ZPC },
3383 { "sr", SR },
3384
3385 { "ccr", CCR },
3386 { "cc", CCR },
3387
3388 { "acc", ACC },
3389 { "macsr", MACSR },
3390 { "mask", MASK },
3391
3392 /* control registers */
3393 { "sfc", SFC }, /* Source Function Code */
3394 { "sfcr", SFC },
3395 { "dfc", DFC }, /* Destination Function Code */
3396 { "dfcr", DFC },
3397 { "cacr", CACR }, /* Cache Control Register */
3398 { "caar", CAAR }, /* Cache Address Register */
3399
3400 { "usp", USP }, /* User Stack Pointer */
3401 { "vbr", VBR }, /* Vector Base Register */
3402 { "msp", MSP }, /* Master Stack Pointer */
3403 { "isp", ISP }, /* Interrupt Stack Pointer */
3404
3405 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3406 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3407 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3408 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3409
3410 /* 68ec040 versions of same */
3411 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3412 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3413 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3414 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3415
3416 /* mcf5200 versions of same. The ColdFire programmer's reference
3417 manual indicated that the order is 2,3,0,1, but Ken Rose
3418 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3419 { "acr0", ITT0 }, /* Access Control Unit 0 */
3420 { "acr1", ITT1 }, /* Access Control Unit 1 */
3421 { "acr2", DTT0 }, /* Access Control Unit 2 */
3422 { "acr3", DTT1 }, /* Access Control Unit 3 */
3423
3424 { "tc", TC }, /* MMU Translation Control Register */
3425 { "tcr", TC },
3426
3427 { "mmusr", MMUSR }, /* MMU Status Register */
3428 { "srp", SRP }, /* User Root Pointer */
3429 { "urp", URP }, /* Supervisor Root Pointer */
3430
3431 { "buscr", BUSCR },
3432 { "pcr", PCR },
3433
3434 { "rombar", ROMBAR }, /* ROM Base Address Register */
3435 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3436 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3437 { "mbar", MBAR }, /* Module Base Address Register */
3438 /* end of control registers */
3439
3440 { "ac", AC },
3441 { "bc", BC },
3442 { "cal", CAL },
3443 { "crp", CRP },
3444 { "drp", DRP },
3445 { "pcsr", PCSR },
3446 { "psr", PSR },
3447 { "scc", SCC },
3448 { "val", VAL },
3449 { "bad0", BAD0 },
3450 { "bad1", BAD1 },
3451 { "bad2", BAD2 },
3452 { "bad3", BAD3 },
3453 { "bad4", BAD4 },
3454 { "bad5", BAD5 },
3455 { "bad6", BAD6 },
3456 { "bad7", BAD7 },
3457 { "bac0", BAC0 },
3458 { "bac1", BAC1 },
3459 { "bac2", BAC2 },
3460 { "bac3", BAC3 },
3461 { "bac4", BAC4 },
3462 { "bac5", BAC5 },
3463 { "bac6", BAC6 },
3464 { "bac7", BAC7 },
3465
3466 { "ic", IC },
3467 { "dc", DC },
3468 { "nc", NC },
3469
3470 { "tt0", TT0 },
3471 { "tt1", TT1 },
3472 /* 68ec030 versions of same */
3473 { "ac0", TT0 },
3474 { "ac1", TT1 },
3475 /* 68ec030 access control unit, identical to 030 MMU status reg */
3476 { "acusr", PSR },
3477
3478 /* Suppressed data and address registers. */
3479 { "zd0", ZDATA0 },
3480 { "zd1", ZDATA1 },
3481 { "zd2", ZDATA2 },
3482 { "zd3", ZDATA3 },
3483 { "zd4", ZDATA4 },
3484 { "zd5", ZDATA5 },
3485 { "zd6", ZDATA6 },
3486 { "zd7", ZDATA7 },
3487 { "za0", ZADDR0 },
3488 { "za1", ZADDR1 },
3489 { "za2", ZADDR2 },
3490 { "za3", ZADDR3 },
3491 { "za4", ZADDR4 },
3492 { "za5", ZADDR5 },
3493 { "za6", ZADDR6 },
3494 { "za7", ZADDR7 },
3495
3496 /* Upper and lower data and address registers, used by macw and msacw. */
3497 { "d0l", DATA0L },
3498 { "d1l", DATA1L },
3499 { "d2l", DATA2L },
3500 { "d3l", DATA3L },
3501 { "d4l", DATA4L },
3502 { "d5l", DATA5L },
3503 { "d6l", DATA6L },
3504 { "d7l", DATA7L },
3505
3506 { "a0l", ADDR0L },
3507 { "a1l", ADDR1L },
3508 { "a2l", ADDR2L },
3509 { "a3l", ADDR3L },
3510 { "a4l", ADDR4L },
3511 { "a5l", ADDR5L },
3512 { "a6l", ADDR6L },
3513 { "a7l", ADDR7L },
3514
3515 { "d0u", DATA0U },
3516 { "d1u", DATA1U },
3517 { "d2u", DATA2U },
3518 { "d3u", DATA3U },
3519 { "d4u", DATA4U },
3520 { "d5u", DATA5U },
3521 { "d6u", DATA6U },
3522 { "d7u", DATA7U },
3523
3524 { "a0u", ADDR0U },
3525 { "a1u", ADDR1U },
3526 { "a2u", ADDR2U },
3527 { "a3u", ADDR3U },
3528 { "a4u", ADDR4U },
3529 { "a5u", ADDR5U },
3530 { "a6u", ADDR6U },
3531 { "a7u", ADDR7U },
3532
3533 { 0, 0 }
3534 };
3535
3536 static void
3537 init_regtable ()
3538 {
3539 int i;
3540 for (i = 0; init_table[i].name; i++)
3541 insert_reg (init_table[i].name, init_table[i].number);
3542 }
3543
3544 static int no_68851, no_68881;
3545
3546 #ifdef OBJ_AOUT
3547 /* a.out machine type. Default to 68020. */
3548 int m68k_aout_machtype = 2;
3549 #endif
3550
3551 void
3552 md_assemble (str)
3553 char *str;
3554 {
3555 const char *er;
3556 short *fromP;
3557 char *toP = NULL;
3558 int m, n = 0;
3559 char *to_beg_P;
3560 int shorts_this_frag;
3561 fixS *fixP;
3562
3563 /* In MRI mode, the instruction and operands are separated by a
3564 space. Anything following the operands is a comment. The label
3565 has already been removed. */
3566 if (flag_mri)
3567 {
3568 char *s;
3569 int fields = 0;
3570 int infield = 0;
3571 int inquote = 0;
3572
3573 for (s = str; *s != '\0'; s++)
3574 {
3575 if ((*s == ' ' || *s == '\t') && ! inquote)
3576 {
3577 if (infield)
3578 {
3579 ++fields;
3580 if (fields >= 2)
3581 {
3582 *s = '\0';
3583 break;
3584 }
3585 infield = 0;
3586 }
3587 }
3588 else
3589 {
3590 if (! infield)
3591 infield = 1;
3592 if (*s == '\'')
3593 inquote = ! inquote;
3594 }
3595 }
3596 }
3597
3598 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3599 m68k_ip (str);
3600 er = the_ins.error;
3601 if (!er)
3602 {
3603 for (n = 0; n < the_ins.numargs; n++)
3604 if (the_ins.operands[n].error)
3605 {
3606 er = the_ins.operands[n].error;
3607 break;
3608 }
3609 }
3610 if (er)
3611 {
3612 as_bad (_("%s -- statement `%s' ignored"), er, str);
3613 return;
3614 }
3615
3616 /* If there is a current label, record that it marks an instruction. */
3617 if (current_label != NULL)
3618 {
3619 current_label->text = 1;
3620 current_label = NULL;
3621 }
3622
3623 if (the_ins.nfrag == 0)
3624 {
3625 /* No frag hacking involved; just put it out */
3626 toP = frag_more (2 * the_ins.numo);
3627 fromP = &the_ins.opcode[0];
3628 for (m = the_ins.numo; m; --m)
3629 {
3630 md_number_to_chars (toP, (long) (*fromP), 2);
3631 toP += 2;
3632 fromP++;
3633 }
3634 /* put out symbol-dependent info */
3635 for (m = 0; m < the_ins.nrel; m++)
3636 {
3637 switch (the_ins.reloc[m].wid)
3638 {
3639 case 'B':
3640 n = 1;
3641 break;
3642 case 'b':
3643 n = 1;
3644 break;
3645 case '3':
3646 n = 1;
3647 break;
3648 case 'w':
3649 case 'W':
3650 n = 2;
3651 break;
3652 case 'l':
3653 n = 4;
3654 break;
3655 default:
3656 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3657 the_ins.reloc[m].wid);
3658 }
3659
3660 fixP = fix_new_exp (frag_now,
3661 ((toP - frag_now->fr_literal)
3662 - the_ins.numo * 2 + the_ins.reloc[m].n),
3663 n,
3664 &the_ins.reloc[m].exp,
3665 the_ins.reloc[m].pcrel,
3666 get_reloc_code (n, the_ins.reloc[m].pcrel,
3667 the_ins.reloc[m].pic_reloc));
3668 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3669 if (the_ins.reloc[m].wid == 'B')
3670 fixP->fx_signed = 1;
3671 }
3672 return;
3673 }
3674
3675 /* There's some frag hacking */
3676 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3677 {
3678 int wid;
3679
3680 if (n == 0)
3681 wid = 2 * the_ins.fragb[n].fragoff;
3682 else
3683 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3684 toP = frag_more (wid);
3685 to_beg_P = toP;
3686 shorts_this_frag = 0;
3687 for (m = wid / 2; m; --m)
3688 {
3689 md_number_to_chars (toP, (long) (*fromP), 2);
3690 toP += 2;
3691 fromP++;
3692 shorts_this_frag++;
3693 }
3694 for (m = 0; m < the_ins.nrel; m++)
3695 {
3696 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3697 {
3698 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3699 break;
3700 }
3701 wid = the_ins.reloc[m].wid;
3702 if (wid == 0)
3703 continue;
3704 the_ins.reloc[m].wid = 0;
3705 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3706
3707 fixP = fix_new_exp (frag_now,
3708 ((toP - frag_now->fr_literal)
3709 - the_ins.numo * 2 + the_ins.reloc[m].n),
3710 wid,
3711 &the_ins.reloc[m].exp,
3712 the_ins.reloc[m].pcrel,
3713 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3714 the_ins.reloc[m].pic_reloc));
3715 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3716 }
3717 (void) frag_var (rs_machine_dependent, 10, 0,
3718 (relax_substateT) (the_ins.fragb[n].fragty),
3719 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3720 }
3721 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3722 shorts_this_frag = 0;
3723 if (n)
3724 {
3725 toP = frag_more (n * sizeof (short));
3726 while (n--)
3727 {
3728 md_number_to_chars (toP, (long) (*fromP), 2);
3729 toP += 2;
3730 fromP++;
3731 shorts_this_frag++;
3732 }
3733 }
3734 for (m = 0; m < the_ins.nrel; m++)
3735 {
3736 int wid;
3737
3738 wid = the_ins.reloc[m].wid;
3739 if (wid == 0)
3740 continue;
3741 the_ins.reloc[m].wid = 0;
3742 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3743
3744 fixP = fix_new_exp (frag_now,
3745 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3746 - shorts_this_frag * 2),
3747 wid,
3748 &the_ins.reloc[m].exp,
3749 the_ins.reloc[m].pcrel,
3750 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3751 the_ins.reloc[m].pic_reloc));
3752 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3753 }
3754 }
3755
3756 void
3757 md_begin ()
3758 {
3759 /*
3760 * md_begin -- set up hash tables with 68000 instructions.
3761 * similar to what the vax assembler does. ---phr
3762 */
3763 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3764 a copy of it at runtime, adding in the information we want but isn't
3765 there. I think it'd be better to have an awk script hack the table
3766 at compile time. Or even just xstr the table and use it as-is. But
3767 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3768 names. */
3769
3770 register const struct m68k_opcode *ins;
3771 register struct m68k_incant *hack, *slak;
3772 register const char *retval = 0; /* empty string, or error msg text */
3773 register int i;
3774 register char c;
3775
3776 if (flag_mri)
3777 {
3778 flag_reg_prefix_optional = 1;
3779 m68k_abspcadd = 1;
3780 if (! m68k_rel32_from_cmdline)
3781 m68k_rel32 = 0;
3782 }
3783
3784 op_hash = hash_new ();
3785
3786 obstack_begin (&robyn, 4000);
3787 for (i = 0; i < m68k_numopcodes; i++)
3788 {
3789 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3790 do
3791 {
3792 ins = &m68k_opcodes[i];
3793 /* We *could* ignore insns that don't match our arch here
3794 but just leaving them out of the hash. */
3795 slak->m_operands = ins->args;
3796 slak->m_opnum = strlen (slak->m_operands) / 2;
3797 slak->m_arch = ins->arch;
3798 slak->m_opcode = ins->opcode;
3799 /* This is kludgey */
3800 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3801 if (i + 1 != m68k_numopcodes
3802 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3803 {
3804 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3805 i++;
3806 }
3807 else
3808 slak->m_next = 0;
3809 slak = slak->m_next;
3810 }
3811 while (slak);
3812
3813 retval = hash_insert (op_hash, ins->name, (char *) hack);
3814 if (retval)
3815 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3816 }
3817
3818 for (i = 0; i < m68k_numaliases; i++)
3819 {
3820 const char *name = m68k_opcode_aliases[i].primary;
3821 const char *alias = m68k_opcode_aliases[i].alias;
3822 PTR val = hash_find (op_hash, name);
3823 if (!val)
3824 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3825 retval = hash_insert (op_hash, alias, val);
3826 if (retval)
3827 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3828 }
3829
3830 /* In MRI mode, all unsized branches are variable sized. Normally,
3831 they are word sized. */
3832 if (flag_mri)
3833 {
3834 static struct m68k_opcode_alias mri_aliases[] =
3835 {
3836 { "bhi", "jhi", },
3837 { "bls", "jls", },
3838 { "bcc", "jcc", },
3839 { "bcs", "jcs", },
3840 { "bne", "jne", },
3841 { "beq", "jeq", },
3842 { "bvc", "jvc", },
3843 { "bvs", "jvs", },
3844 { "bpl", "jpl", },
3845 { "bmi", "jmi", },
3846 { "bge", "jge", },
3847 { "blt", "jlt", },
3848 { "bgt", "jgt", },
3849 { "ble", "jle", },
3850 { "bra", "jra", },
3851 { "bsr", "jbsr", },
3852 };
3853
3854 for (i = 0;
3855 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3856 i++)
3857 {
3858 const char *name = mri_aliases[i].primary;
3859 const char *alias = mri_aliases[i].alias;
3860 PTR val = hash_find (op_hash, name);
3861 if (!val)
3862 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3863 retval = hash_jam (op_hash, alias, val);
3864 if (retval)
3865 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3866 }
3867 }
3868
3869 for (i = 0; i < (int) sizeof (mklower_table); i++)
3870 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3871
3872 for (i = 0; i < (int) sizeof (notend_table); i++)
3873 {
3874 notend_table[i] = 0;
3875 alt_notend_table[i] = 0;
3876 }
3877 notend_table[','] = 1;
3878 notend_table['{'] = 1;
3879 notend_table['}'] = 1;
3880 alt_notend_table['a'] = 1;
3881 alt_notend_table['A'] = 1;
3882 alt_notend_table['d'] = 1;
3883 alt_notend_table['D'] = 1;
3884 alt_notend_table['#'] = 1;
3885 alt_notend_table['&'] = 1;
3886 alt_notend_table['f'] = 1;
3887 alt_notend_table['F'] = 1;
3888 #ifdef REGISTER_PREFIX
3889 alt_notend_table[REGISTER_PREFIX] = 1;
3890 #endif
3891
3892 /* We need to put '(' in alt_notend_table to handle
3893 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3894 */
3895 alt_notend_table['('] = 1;
3896
3897 /* We need to put '@' in alt_notend_table to handle
3898 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3899 */
3900 alt_notend_table['@'] = 1;
3901
3902 /* We need to put digits in alt_notend_table to handle
3903 bfextu %d0{24:1},%d0
3904 */
3905 alt_notend_table['0'] = 1;
3906 alt_notend_table['1'] = 1;
3907 alt_notend_table['2'] = 1;
3908 alt_notend_table['3'] = 1;
3909 alt_notend_table['4'] = 1;
3910 alt_notend_table['5'] = 1;
3911 alt_notend_table['6'] = 1;
3912 alt_notend_table['7'] = 1;
3913 alt_notend_table['8'] = 1;
3914 alt_notend_table['9'] = 1;
3915
3916 #ifndef MIT_SYNTAX_ONLY
3917 /* Insert pseudo ops, these have to go into the opcode table since
3918 gas expects pseudo ops to start with a dot */
3919 {
3920 int n = 0;
3921 while (mote_pseudo_table[n].poc_name)
3922 {
3923 hack = (struct m68k_incant *)
3924 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3925 hash_insert (op_hash,
3926 mote_pseudo_table[n].poc_name, (char *) hack);
3927 hack->m_operands = 0;
3928 hack->m_opnum = n;
3929 n++;
3930 }
3931 }
3932 #endif
3933
3934 init_regtable ();
3935
3936 #ifdef OBJ_ELF
3937 record_alignment (text_section, 2);
3938 record_alignment (data_section, 2);
3939 record_alignment (bss_section, 2);
3940 #endif
3941 }
3942
3943 static void
3944 select_control_regs ()
3945 {
3946 /* Note which set of "movec" control registers is available. */
3947 switch (cpu_of_arch (current_architecture))
3948 {
3949 case m68000:
3950 control_regs = m68000_control_regs;
3951 break;
3952 case m68010:
3953 control_regs = m68010_control_regs;
3954 break;
3955 case m68020:
3956 case m68030:
3957 control_regs = m68020_control_regs;
3958 break;
3959 case m68040:
3960 control_regs = m68040_control_regs;
3961 break;
3962 case m68060:
3963 control_regs = m68060_control_regs;
3964 break;
3965 case cpu32:
3966 control_regs = cpu32_control_regs;
3967 break;
3968 case mcf5200:
3969 case mcf5206e:
3970 case mcf5307:
3971 case mcf5407:
3972 control_regs = mcf_control_regs;
3973 break;
3974 default:
3975 abort ();
3976 }
3977 }
3978
3979 void
3980 m68k_init_after_args ()
3981 {
3982 if (cpu_of_arch (current_architecture) == 0)
3983 {
3984 int i;
3985 const char *default_cpu = TARGET_CPU;
3986
3987 if (*default_cpu == 'm')
3988 default_cpu++;
3989 for (i = 0; i < n_archs; i++)
3990 if (strcasecmp (default_cpu, archs[i].name) == 0)
3991 break;
3992 if (i == n_archs)
3993 {
3994 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3995 current_architecture |= m68020;
3996 }
3997 else
3998 current_architecture |= archs[i].arch;
3999 }
4000 /* Permit m68881 specification with all cpus; those that can't work
4001 with a coprocessor could be doing emulation. */
4002 if (current_architecture & m68851)
4003 {
4004 if (current_architecture & m68040)
4005 {
4006 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4007 }
4008 }
4009 /* What other incompatibilities could we check for? */
4010
4011 /* Toss in some default assumptions about coprocessors. */
4012 if (!no_68881
4013 && (cpu_of_arch (current_architecture)
4014 /* Can CPU32 have a 68881 coprocessor?? */
4015 & (m68020 | m68030 | cpu32)))
4016 {
4017 current_architecture |= m68881;
4018 }
4019 if (!no_68851
4020 && (cpu_of_arch (current_architecture) & m68020up) != 0
4021 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4022 {
4023 current_architecture |= m68851;
4024 }
4025 if (no_68881 && (current_architecture & m68881))
4026 as_bad (_("options for 68881 and no-68881 both given"));
4027 if (no_68851 && (current_architecture & m68851))
4028 as_bad (_("options for 68851 and no-68851 both given"));
4029
4030 #ifdef OBJ_AOUT
4031 /* Work out the magic number. This isn't very general. */
4032 if (current_architecture & m68000)
4033 m68k_aout_machtype = 0;
4034 else if (current_architecture & m68010)
4035 m68k_aout_machtype = 1;
4036 else if (current_architecture & m68020)
4037 m68k_aout_machtype = 2;
4038 else
4039 m68k_aout_machtype = 2;
4040 #endif
4041
4042 /* Note which set of "movec" control registers is available. */
4043 select_control_regs ();
4044
4045 if (cpu_of_arch (current_architecture) < m68020
4046 || arch_coldfire_p (current_architecture))
4047 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4048 }
4049 \f
4050 /* This is called when a label is defined. */
4051
4052 void
4053 m68k_frob_label (sym)
4054 symbolS *sym;
4055 {
4056 struct label_line *n;
4057
4058 n = (struct label_line *) xmalloc (sizeof *n);
4059 n->next = labels;
4060 n->label = sym;
4061 as_where (&n->file, &n->line);
4062 n->text = 0;
4063 labels = n;
4064 current_label = n;
4065 }
4066
4067 /* This is called when a value that is not an instruction is emitted. */
4068
4069 void
4070 m68k_flush_pending_output ()
4071 {
4072 current_label = NULL;
4073 }
4074
4075 /* This is called at the end of the assembly, when the final value of
4076 the label is known. We warn if this is a text symbol aligned at an
4077 odd location. */
4078
4079 void
4080 m68k_frob_symbol (sym)
4081 symbolS *sym;
4082 {
4083 if (S_GET_SEGMENT (sym) == reg_section
4084 && (int) S_GET_VALUE (sym) < 0)
4085 {
4086 S_SET_SEGMENT (sym, absolute_section);
4087 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4088 }
4089 else if ((S_GET_VALUE (sym) & 1) != 0)
4090 {
4091 struct label_line *l;
4092
4093 for (l = labels; l != NULL; l = l->next)
4094 {
4095 if (l->label == sym)
4096 {
4097 if (l->text)
4098 as_warn_where (l->file, l->line,
4099 _("text label `%s' aligned to odd boundary"),
4100 S_GET_NAME (sym));
4101 break;
4102 }
4103 }
4104 }
4105 }
4106 \f
4107 /* This is called if we go in or out of MRI mode because of the .mri
4108 pseudo-op. */
4109
4110 void
4111 m68k_mri_mode_change (on)
4112 int on;
4113 {
4114 if (on)
4115 {
4116 if (! flag_reg_prefix_optional)
4117 {
4118 flag_reg_prefix_optional = 1;
4119 #ifdef REGISTER_PREFIX
4120 init_regtable ();
4121 #endif
4122 }
4123 m68k_abspcadd = 1;
4124 if (! m68k_rel32_from_cmdline)
4125 m68k_rel32 = 0;
4126 }
4127 else
4128 {
4129 if (! reg_prefix_optional_seen)
4130 {
4131 #ifdef REGISTER_PREFIX_OPTIONAL
4132 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4133 #else
4134 flag_reg_prefix_optional = 0;
4135 #endif
4136 #ifdef REGISTER_PREFIX
4137 init_regtable ();
4138 #endif
4139 }
4140 m68k_abspcadd = 0;
4141 if (! m68k_rel32_from_cmdline)
4142 m68k_rel32 = 1;
4143 }
4144 }
4145
4146 /* Equal to MAX_PRECISION in atof-ieee.c */
4147 #define MAX_LITTLENUMS 6
4148
4149 /* Turn a string in input_line_pointer into a floating point constant
4150 of type TYPE, and store the appropriate bytes in *LITP. The number
4151 of LITTLENUMS emitted is stored in *SIZEP. An error message is
4152 returned, or NULL on OK. */
4153
4154 char *
4155 md_atof (type, litP, sizeP)
4156 char type;
4157 char *litP;
4158 int *sizeP;
4159 {
4160 int prec;
4161 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4162 LITTLENUM_TYPE *wordP;
4163 char *t;
4164
4165 switch (type)
4166 {
4167 case 'f':
4168 case 'F':
4169 case 's':
4170 case 'S':
4171 prec = 2;
4172 break;
4173
4174 case 'd':
4175 case 'D':
4176 case 'r':
4177 case 'R':
4178 prec = 4;
4179 break;
4180
4181 case 'x':
4182 case 'X':
4183 prec = 6;
4184 break;
4185
4186 case 'p':
4187 case 'P':
4188 prec = 6;
4189 break;
4190
4191 default:
4192 *sizeP = 0;
4193 return _("Bad call to MD_ATOF()");
4194 }
4195 t = atof_ieee (input_line_pointer, type, words);
4196 if (t)
4197 input_line_pointer = t;
4198
4199 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4200 for (wordP = words; prec--;)
4201 {
4202 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4203 litP += sizeof (LITTLENUM_TYPE);
4204 }
4205 return 0;
4206 }
4207
4208 void
4209 md_number_to_chars (buf, val, n)
4210 char *buf;
4211 valueT val;
4212 int n;
4213 {
4214 number_to_chars_bigendian (buf, val, n);
4215 }
4216
4217 static void
4218 md_apply_fix_2 (fixP, val)
4219 fixS *fixP;
4220 offsetT val;
4221 {
4222 addressT upper_limit;
4223 offsetT lower_limit;
4224
4225 /* This is unnecessary but it convinces the native rs6000 compiler
4226 to generate the code we want. */
4227 char *buf = fixP->fx_frag->fr_literal;
4228 buf += fixP->fx_where;
4229 /* end ibm compiler workaround */
4230
4231 if (val & 0x80000000)
4232 val |= ~(addressT)0x7fffffff;
4233 else
4234 val &= 0x7fffffff;
4235
4236 #ifdef OBJ_ELF
4237 if (fixP->fx_addsy)
4238 {
4239 memset (buf, 0, fixP->fx_size);
4240 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4241
4242 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4243 && !S_IS_DEFINED (fixP->fx_addsy)
4244 && !S_IS_WEAK (fixP->fx_addsy))
4245 S_SET_WEAK (fixP->fx_addsy);
4246 return;
4247 }
4248 #endif
4249
4250 #ifdef BFD_ASSEMBLER
4251 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4252 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4253 return;
4254 #endif
4255
4256 switch (fixP->fx_size)
4257 {
4258 /* The cast to offsetT below are necessary to make code correct for
4259 machines where ints are smaller than offsetT */
4260 case 1:
4261 *buf++ = val;
4262 upper_limit = 0x7f;
4263 lower_limit = - (offsetT) 0x80;
4264 break;
4265 case 2:
4266 *buf++ = (val >> 8);
4267 *buf++ = val;
4268 upper_limit = 0x7fff;
4269 lower_limit = - (offsetT) 0x8000;
4270 break;
4271 case 4:
4272 *buf++ = (val >> 24);
4273 *buf++ = (val >> 16);
4274 *buf++ = (val >> 8);
4275 *buf++ = val;
4276 upper_limit = 0x7fffffff;
4277 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4278 break;
4279 default:
4280 BAD_CASE (fixP->fx_size);
4281 }
4282
4283 /* Fix up a negative reloc. */
4284 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4285 {
4286 fixP->fx_addsy = fixP->fx_subsy;
4287 fixP->fx_subsy = NULL;
4288 fixP->fx_tcbit = 1;
4289 }
4290
4291 /* For non-pc-relative values, it's conceivable we might get something
4292 like "0xff" for a byte field. So extend the upper part of the range
4293 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4294 so that we can do any range checking at all. */
4295 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4296 upper_limit = upper_limit * 2 + 1;
4297
4298 if ((addressT) val > upper_limit
4299 && (val > 0 || val < lower_limit))
4300 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4301
4302 /* A one byte PC-relative reloc means a short branch. We can't use
4303 a short branch with a value of 0 or -1, because those indicate
4304 different opcodes (branches with longer offsets). fixup_segment
4305 in write.c may have clobbered fx_pcrel, so we need to examine the
4306 reloc type. */
4307 if ((fixP->fx_pcrel
4308 #ifdef BFD_ASSEMBLER
4309 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4310 #endif
4311 )
4312 && fixP->fx_size == 1
4313 && (fixP->fx_addsy == NULL
4314 || S_IS_DEFINED (fixP->fx_addsy))
4315 && (val == 0 || val == -1))
4316 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4317 }
4318
4319 #ifdef BFD_ASSEMBLER
4320 int
4321 md_apply_fix (fixP, valp)
4322 fixS *fixP;
4323 valueT *valp;
4324 {
4325 md_apply_fix_2 (fixP, (addressT) *valp);
4326 return 1;
4327 }
4328 #else
4329 void md_apply_fix (fixP, val)
4330 fixS *fixP;
4331 long val;
4332 {
4333 md_apply_fix_2 (fixP, (addressT) val);
4334 }
4335 #endif
4336
4337 /* *fragP has been relaxed to its final size, and now needs to have
4338 the bytes inside it modified to conform to the new size There is UGLY
4339 MAGIC here. ..
4340 */
4341 static void
4342 md_convert_frag_1 (fragP)
4343 register fragS *fragP;
4344 {
4345 long disp;
4346 fixS *fixP;
4347
4348 /* Address in object code of the displacement. */
4349 register int object_address = fragP->fr_fix + fragP->fr_address;
4350
4351 /* Address in gas core of the place to store the displacement. */
4352 /* This convinces the native rs6000 compiler to generate the code we
4353 want. */
4354 register char *buffer_address = fragP->fr_literal;
4355 buffer_address += fragP->fr_fix;
4356 /* end ibm compiler workaround */
4357
4358 /* The displacement of the address, from current location. */
4359 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4360 disp = (disp + fragP->fr_offset) - object_address;
4361
4362 #ifdef BFD_ASSEMBLER
4363 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
4364 #endif
4365
4366 switch (fragP->fr_subtype)
4367 {
4368 case TAB (BRANCHBWL, BYTE):
4369 case TAB (BRABSJUNC, BYTE):
4370 case TAB (BRABSJCOND, BYTE):
4371 case TAB (BRANCHBW, BYTE):
4372 know (issbyte (disp));
4373 if (disp == 0)
4374 as_bad (_("short branch with zero offset: use :w"));
4375 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4376 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4377 fixP->fx_pcrel_adjust = -1;
4378 break;
4379 case TAB (BRANCHBWL, SHORT):
4380 case TAB (BRABSJUNC, SHORT):
4381 case TAB (BRABSJCOND, SHORT):
4382 case TAB (BRANCHBW, SHORT):
4383 fragP->fr_opcode[1] = 0x00;
4384 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4385 1, RELAX_RELOC_PC16);
4386 fragP->fr_fix += 2;
4387 break;
4388 case TAB (BRANCHBWL, LONG):
4389 fragP->fr_opcode[1] = (char) 0xFF;
4390 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4391 1, RELAX_RELOC_PC32);
4392 fragP->fr_fix += 4;
4393 break;
4394 case TAB (BRABSJUNC, LONG):
4395 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4396 {
4397 fragP->fr_opcode[0] = 0x4E;
4398 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4399 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4400 0, RELAX_RELOC_ABS32);
4401 fragP->fr_fix += 4;
4402 }
4403 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4404 {
4405 fragP->fr_opcode[0] = 0x4E;
4406 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4407 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4408 0, RELAX_RELOC_ABS32);
4409 fragP->fr_fix += 4;
4410 }
4411 else
4412 {
4413 /* This cannot happen, because jbsr and jbra are the only two
4414 unconditional branches. */
4415 abort ();
4416 }
4417 break;
4418 case TAB (BRABSJCOND, LONG):
4419 /* Only Bcc 68000 instructions can come here. */
4420 /* Change bcc into b!cc/jmp absl long. */
4421
4422 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4423 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4424
4425 /* JF: these used to be fr_opcode[2,3], but they may be in a
4426 different frag, in which case refering to them is a no-no.
4427 Only fr_opcode[0,1] are guaranteed to work. */
4428 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4429 *buffer_address++ = (char) 0xf9;
4430 fragP->fr_fix += 2; /* account for jmp instruction */
4431 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4432 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
4433 fragP->fr_fix += 4;
4434 break;
4435 case TAB (FBRANCH, SHORT):
4436 know ((fragP->fr_opcode[1] & 0x40) == 0);
4437 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4438 1, RELAX_RELOC_PC16);
4439 fragP->fr_fix += 2;
4440 break;
4441 case TAB (FBRANCH, LONG):
4442 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4443 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4444 1, RELAX_RELOC_PC32);
4445 fragP->fr_fix += 4;
4446 break;
4447 case TAB (DBCCLBR, SHORT):
4448 case TAB (DBCCABSJ, SHORT):
4449 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4450 1, RELAX_RELOC_PC16);
4451 fragP->fr_fix += 2;
4452 break;
4453 case TAB (DBCCLBR, LONG):
4454 /* only DBcc instructions can come here */
4455 /* Change dbcc into dbcc/bral. */
4456
4457 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4458 *buffer_address++ = 0x00; /* branch offset = 4 */
4459 *buffer_address++ = 0x04;
4460 *buffer_address++ = 0x60; /* put in bra pc+6 */
4461 *buffer_address++ = 0x06;
4462 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4463 *buffer_address++ = (char) 0xff;
4464
4465 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4466 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
4467 RELAX_RELOC_PC32);
4468 fragP->fr_fix += 4;
4469 break;
4470 case TAB (DBCCABSJ, LONG):
4471 /* only DBcc instructions can come here */
4472 /* Change dbcc into dbcc/jmp. */
4473
4474 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4475 *buffer_address++ = 0x00; /* branch offset = 4 */
4476 *buffer_address++ = 0x04;
4477 *buffer_address++ = 0x60; /* put in bra pc+6 */
4478 *buffer_address++ = 0x06;
4479 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4480 *buffer_address++ = (char) 0xf9;
4481
4482 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4483 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
4484 RELAX_RELOC_ABS32);
4485 fragP->fr_fix += 4;
4486 break;
4487 case TAB (PCREL1632, SHORT):
4488 fragP->fr_opcode[1] &= ~0x3F;
4489 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
4490 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4491 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4492 fragP->fr_fix += 2;
4493 break;
4494 case TAB (PCREL1632, LONG):
4495 /* Already set to mode 7.3; this indicates: PC indirect with
4496 suppressed index, 32-bit displacement. */
4497 *buffer_address++ = 0x01;
4498 *buffer_address++ = 0x70;
4499 fragP->fr_fix += 2;
4500 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4501 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4502 fixP->fx_pcrel_adjust = 2;
4503 fragP->fr_fix += 4;
4504 break;
4505 case TAB (PCINDEX, BYTE):
4506 assert (fragP->fr_fix >= 2);
4507 buffer_address[-2] &= ~1;
4508 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4509 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4510 fixP->fx_pcrel_adjust = 1;
4511 break;
4512 case TAB (PCINDEX, SHORT):
4513 assert (fragP->fr_fix >= 2);
4514 buffer_address[-2] |= 0x1;
4515 buffer_address[-1] = 0x20;
4516 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4517 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4518 fixP->fx_pcrel_adjust = 2;
4519 fragP->fr_fix += 2;
4520 break;
4521 case TAB (PCINDEX, LONG):
4522 assert (fragP->fr_fix >= 2);
4523 buffer_address[-2] |= 0x1;
4524 buffer_address[-1] = 0x30;
4525 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
4526 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4527 fixP->fx_pcrel_adjust = 2;
4528 fragP->fr_fix += 4;
4529 break;
4530 case TAB (ABSTOPCREL, SHORT):
4531 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
4532 1, RELAX_RELOC_PC16);
4533 fragP->fr_fix += 2;
4534 break;
4535 case TAB (ABSTOPCREL, LONG):
4536 /* The thing to do here is force it to ABSOLUTE LONG, since
4537 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4538 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4539 abort ();
4540 fragP->fr_opcode[1] &= ~0x3F;
4541 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4542 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
4543 0, RELAX_RELOC_ABS32);
4544 fragP->fr_fix += 4;
4545 break;
4546 }
4547 }
4548
4549 #ifndef BFD_ASSEMBLER
4550
4551 void
4552 md_convert_frag (headers, sec, fragP)
4553 object_headers *headers ATTRIBUTE_UNUSED;
4554 segT sec ATTRIBUTE_UNUSED;
4555 fragS *fragP;
4556 {
4557 md_convert_frag_1 (fragP);
4558 }
4559
4560 #else
4561
4562 void
4563 md_convert_frag (abfd, sec, fragP)
4564 bfd *abfd ATTRIBUTE_UNUSED;
4565 segT sec ATTRIBUTE_UNUSED;
4566 fragS *fragP;
4567 {
4568 md_convert_frag_1 (fragP);
4569 }
4570 #endif
4571
4572 /* Force truly undefined symbols to their maximum size, and generally set up
4573 the frag list to be relaxed
4574 */
4575 int
4576 md_estimate_size_before_relax (fragP, segment)
4577 register fragS *fragP;
4578 segT segment;
4579 {
4580 int old_fix;
4581
4582 old_fix = fragP->fr_fix;
4583
4584 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
4585 switch (fragP->fr_subtype)
4586 {
4587 case TAB (BRANCHBWL, SZ_UNDEF):
4588 case TAB (BRABSJUNC, SZ_UNDEF):
4589 {
4590 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4591 && relaxable_symbol (fragP->fr_symbol))
4592 {
4593 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4594 }
4595 else if (flag_short_refs)
4596 {
4597 /* Symbol is undefined and we want short ref. */
4598 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4599 fragP->fr_var += 2;
4600 }
4601 else
4602 {
4603 /* Symbol is still undefined. Make it LONG. */
4604 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4605 fragP->fr_var += 4;
4606 }
4607 break;
4608 }
4609
4610 case TAB (BRABSJCOND, SZ_UNDEF):
4611 {
4612 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4613 && relaxable_symbol (fragP->fr_symbol))
4614 {
4615 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4616 }
4617 else if (flag_short_refs)
4618 {
4619 /* Symbol is undefined and we want short ref. */
4620 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4621 fragP->fr_var += 2;
4622 }
4623 else
4624 {
4625 /* Symbol is still undefined. Make it LONG. */
4626 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4627 fragP->fr_var += 6;
4628 }
4629 break;
4630 }
4631
4632 case TAB (BRANCHBW, SZ_UNDEF):
4633 {
4634 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4635 && relaxable_symbol (fragP->fr_symbol))
4636 {
4637 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4638 }
4639 else
4640 {
4641 /* Symbol is undefined and we don't have long branches. */
4642 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4643 fragP->fr_var += 2;
4644 }
4645 break;
4646 }
4647
4648 case TAB (FBRANCH, SZ_UNDEF):
4649 {
4650 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4651 && relaxable_symbol (fragP->fr_symbol))
4652 || flag_short_refs)
4653 {
4654 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4655 fragP->fr_var += 2;
4656 }
4657 else
4658 {
4659 fragP->fr_subtype = TAB (FBRANCH, LONG);
4660 fragP->fr_var += 4;
4661 }
4662 break;
4663 }
4664
4665 case TAB (DBCCLBR, SZ_UNDEF):
4666 case TAB (DBCCABSJ, SZ_UNDEF):
4667 {
4668 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4669 && relaxable_symbol (fragP->fr_symbol))
4670 || flag_short_refs)
4671 {
4672 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4673 fragP->fr_var += 2;
4674 }
4675 else
4676 {
4677 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4678 fragP->fr_var += 10;
4679 }
4680 break;
4681 }
4682
4683 case TAB (PCREL1632, SZ_UNDEF):
4684 {
4685 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4686 && relaxable_symbol (fragP->fr_symbol))
4687 || flag_short_refs)
4688 {
4689 fragP->fr_subtype = TAB (PCREL1632, SHORT);
4690 fragP->fr_var += 2;
4691 }
4692 else
4693 {
4694 fragP->fr_subtype = TAB (PCREL1632, LONG);
4695 fragP->fr_var += 6;
4696 }
4697 break;
4698 }
4699
4700 case TAB (PCINDEX, SZ_UNDEF):
4701 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4702 && relaxable_symbol (fragP->fr_symbol)))
4703 {
4704 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4705 }
4706 else
4707 {
4708 fragP->fr_subtype = TAB (PCINDEX, LONG);
4709 fragP->fr_var += 4;
4710 }
4711 break;
4712
4713 case TAB (ABSTOPCREL, SZ_UNDEF):
4714 {
4715 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4716 && relaxable_symbol (fragP->fr_symbol)))
4717 {
4718 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4719 fragP->fr_var += 2;
4720 }
4721 else
4722 {
4723 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4724 fragP->fr_var += 4;
4725 }
4726 break;
4727 }
4728
4729 default:
4730 break;
4731 }
4732
4733 /* Now that SZ_UNDEF are taken care of, check others. */
4734 switch (fragP->fr_subtype)
4735 {
4736 case TAB (BRANCHBWL, BYTE):
4737 case TAB (BRABSJUNC, BYTE):
4738 case TAB (BRABSJCOND, BYTE):
4739 case TAB (BRANCHBW, BYTE):
4740 /* We can't do a short jump to the next instruction, so in that
4741 case we force word mode. At this point S_GET_VALUE should
4742 return the offset of the symbol within its frag. If the
4743 symbol is at the start of a frag, and it is the next frag
4744 with any data in it (usually this is just the next frag, but
4745 assembler listings may introduce empty frags), we must use
4746 word mode. */
4747 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4748 {
4749 fragS *stop;
4750 fragS *l;
4751
4752 stop = symbol_get_frag (fragP->fr_symbol);
4753 for (l = fragP->fr_next; l != stop; l = l->fr_next)
4754 if (l->fr_fix + l->fr_var != 0)
4755 break;
4756 if (l == stop)
4757 {
4758 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4759 fragP->fr_var += 2;
4760 }
4761 }
4762 break;
4763 default:
4764 break;
4765 }
4766 return fragP->fr_var + fragP->fr_fix - old_fix;
4767 }
4768
4769 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4770 /* the bit-field entries in the relocation_info struct plays hell
4771 with the byte-order problems of cross-assembly. So as a hack,
4772 I added this mach. dependent ri twiddler. Ugly, but it gets
4773 you there. -KWK */
4774 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
4775 are symbolnum, most sig. byte first. Last byte is broken up with
4776 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4777 nibble as nuthin. (on Sun 3 at least) */
4778 /* Translate the internal relocation information into target-specific
4779 format. */
4780 #ifdef comment
4781 void
4782 md_ri_to_chars (the_bytes, ri)
4783 char *the_bytes;
4784 struct reloc_info_generic *ri;
4785 {
4786 /* this is easy */
4787 md_number_to_chars (the_bytes, ri->r_address, 4);
4788 /* now the fun stuff */
4789 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4790 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4791 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4792 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4793 ((ri->r_extern << 4) & 0x10));
4794 }
4795
4796 #endif /* comment */
4797
4798 #ifndef BFD_ASSEMBLER
4799 void
4800 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4801 char *where;
4802 fixS *fixP;
4803 relax_addressT segment_address_in_file;
4804 {
4805 /*
4806 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4807 * Out: GNU LD relocation length code: 0, 1, or 2.
4808 */
4809
4810 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4811 long r_symbolnum;
4812
4813 know (fixP->fx_addsy != NULL);
4814
4815 md_number_to_chars (where,
4816 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4817 4);
4818
4819 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4820 ? S_GET_TYPE (fixP->fx_addsy)
4821 : fixP->fx_addsy->sy_number);
4822
4823 where[4] = (r_symbolnum >> 16) & 0x0ff;
4824 where[5] = (r_symbolnum >> 8) & 0x0ff;
4825 where[6] = r_symbolnum & 0x0ff;
4826 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4827 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4828 }
4829 #endif
4830
4831 #endif /* OBJ_AOUT or OBJ_BOUT */
4832
4833 #ifndef WORKING_DOT_WORD
4834 CONST int md_short_jump_size = 4;
4835 CONST int md_long_jump_size = 6;
4836
4837 void
4838 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4839 char *ptr;
4840 addressT from_addr, to_addr;
4841 fragS *frag ATTRIBUTE_UNUSED;
4842 symbolS *to_symbol ATTRIBUTE_UNUSED;
4843 {
4844 valueT offset;
4845
4846 offset = to_addr - (from_addr + 2);
4847
4848 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4849 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4850 }
4851
4852 void
4853 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4854 char *ptr;
4855 addressT from_addr, to_addr;
4856 fragS *frag;
4857 symbolS *to_symbol;
4858 {
4859 valueT offset;
4860
4861 if (!HAVE_LONG_BRANCH(current_architecture))
4862 {
4863 offset = to_addr - S_GET_VALUE (to_symbol);
4864 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4865 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4866 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4867 0, NO_RELOC);
4868 }
4869 else
4870 {
4871 offset = to_addr - (from_addr + 2);
4872 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4873 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4874 }
4875 }
4876
4877 #endif
4878
4879 /* Different values of OK tell what its OK to return. Things that
4880 aren't OK are an error (what a shock, no?)
4881
4882 0: Everything is OK
4883 10: Absolute 1:8 only
4884 20: Absolute 0:7 only
4885 30: absolute 0:15 only
4886 40: Absolute 0:31 only
4887 50: absolute 0:127 only
4888 55: absolute -64:63 only
4889 60: absolute -128:127 only
4890 70: absolute 0:4095 only
4891 80: No bignums
4892
4893 */
4894
4895 static int
4896 get_num (exp, ok)
4897 struct m68k_exp *exp;
4898 int ok;
4899 {
4900 if (exp->exp.X_op == O_absent)
4901 {
4902 /* Do the same thing the VAX asm does */
4903 op (exp) = O_constant;
4904 adds (exp) = 0;
4905 subs (exp) = 0;
4906 offs (exp) = 0;
4907 if (ok == 10)
4908 {
4909 as_warn (_("expression out of range: defaulting to 1"));
4910 offs (exp) = 1;
4911 }
4912 }
4913 else if (exp->exp.X_op == O_constant)
4914 {
4915 switch (ok)
4916 {
4917 case 10:
4918 if (offs (exp) < 1 || offs (exp) > 8)
4919 {
4920 as_warn (_("expression out of range: defaulting to 1"));
4921 offs (exp) = 1;
4922 }
4923 break;
4924 case 20:
4925 if (offs (exp) < 0 || offs (exp) > 7)
4926 goto outrange;
4927 break;
4928 case 30:
4929 if (offs (exp) < 0 || offs (exp) > 15)
4930 goto outrange;
4931 break;
4932 case 40:
4933 if (offs (exp) < 0 || offs (exp) > 32)
4934 goto outrange;
4935 break;
4936 case 50:
4937 if (offs (exp) < 0 || offs (exp) > 127)
4938 goto outrange;
4939 break;
4940 case 55:
4941 if (offs (exp) < -64 || offs (exp) > 63)
4942 goto outrange;
4943 break;
4944 case 60:
4945 if (offs (exp) < -128 || offs (exp) > 127)
4946 goto outrange;
4947 break;
4948 case 70:
4949 if (offs (exp) < 0 || offs (exp) > 4095)
4950 {
4951 outrange:
4952 as_warn (_("expression out of range: defaulting to 0"));
4953 offs (exp) = 0;
4954 }
4955 break;
4956 default:
4957 break;
4958 }
4959 }
4960 else if (exp->exp.X_op == O_big)
4961 {
4962 if (offs (exp) <= 0 /* flonum */
4963 && (ok == 80 /* no bignums */
4964 || (ok > 10 /* small-int ranges including 0 ok */
4965 /* If we have a flonum zero, a zero integer should
4966 do as well (e.g., in moveq). */
4967 && generic_floating_point_number.exponent == 0
4968 && generic_floating_point_number.low[0] == 0)))
4969 {
4970 /* HACK! Turn it into a long */
4971 LITTLENUM_TYPE words[6];
4972
4973 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4974 op (exp) = O_constant;
4975 adds (exp) = 0;
4976 subs (exp) = 0;
4977 offs (exp) = words[1] | (words[0] << 16);
4978 }
4979 else if (ok != 0)
4980 {
4981 op (exp) = O_constant;
4982 adds (exp) = 0;
4983 subs (exp) = 0;
4984 offs (exp) = (ok == 10) ? 1 : 0;
4985 as_warn (_("Can't deal with expression; defaulting to %ld"),
4986 offs (exp));
4987 }
4988 }
4989 else
4990 {
4991 if (ok >= 10 && ok <= 70)
4992 {
4993 op (exp) = O_constant;
4994 adds (exp) = 0;
4995 subs (exp) = 0;
4996 offs (exp) = (ok == 10) ? 1 : 0;
4997 as_warn (_("Can't deal with expression; defaulting to %ld"),
4998 offs (exp));
4999 }
5000 }
5001
5002 if (exp->size != SIZE_UNSPEC)
5003 {
5004 switch (exp->size)
5005 {
5006 case SIZE_UNSPEC:
5007 case SIZE_LONG:
5008 break;
5009 case SIZE_BYTE:
5010 if (!isbyte (offs (exp)))
5011 as_warn (_("expression doesn't fit in BYTE"));
5012 break;
5013 case SIZE_WORD:
5014 if (!isword (offs (exp)))
5015 as_warn (_("expression doesn't fit in WORD"));
5016 break;
5017 }
5018 }
5019
5020 return offs (exp);
5021 }
5022
5023 /* These are the back-ends for the various machine dependent pseudo-ops. */
5024
5025 static void
5026 s_data1 (ignore)
5027 int ignore ATTRIBUTE_UNUSED;
5028 {
5029 subseg_set (data_section, 1);
5030 demand_empty_rest_of_line ();
5031 }
5032
5033 static void
5034 s_data2 (ignore)
5035 int ignore ATTRIBUTE_UNUSED;
5036 {
5037 subseg_set (data_section, 2);
5038 demand_empty_rest_of_line ();
5039 }
5040
5041 static void
5042 s_bss (ignore)
5043 int ignore ATTRIBUTE_UNUSED;
5044 {
5045 /* We don't support putting frags in the BSS segment, we fake it
5046 by marking in_bss, then looking at s_skip for clues. */
5047
5048 subseg_set (bss_section, 0);
5049 demand_empty_rest_of_line ();
5050 }
5051
5052 static void
5053 s_even (ignore)
5054 int ignore ATTRIBUTE_UNUSED;
5055 {
5056 register int temp;
5057 register long temp_fill;
5058
5059 temp = 1; /* JF should be 2? */
5060 temp_fill = get_absolute_expression ();
5061 if (!need_pass_2) /* Never make frag if expect extra pass. */
5062 frag_align (temp, (int) temp_fill, 0);
5063 demand_empty_rest_of_line ();
5064 record_alignment (now_seg, temp);
5065 }
5066
5067 static void
5068 s_proc (ignore)
5069 int ignore ATTRIBUTE_UNUSED;
5070 {
5071 demand_empty_rest_of_line ();
5072 }
5073 \f
5074 /* Pseudo-ops handled for MRI compatibility. */
5075
5076 /* This function returns non-zero if the argument is a conditional
5077 pseudo-op. This is called when checking whether a pending
5078 alignment is needed. */
5079
5080 int
5081 m68k_conditional_pseudoop (pop)
5082 pseudo_typeS *pop;
5083 {
5084 return (pop->poc_handler == s_mri_if
5085 || pop->poc_handler == s_mri_else);
5086 }
5087
5088 /* Handle an MRI style chip specification. */
5089
5090 static void
5091 mri_chip ()
5092 {
5093 char *s;
5094 char c;
5095 int i;
5096
5097 s = input_line_pointer;
5098 /* We can't use get_symbol_end since the processor names are not proper
5099 symbols. */
5100 while (is_part_of_name (c = *input_line_pointer++))
5101 ;
5102 *--input_line_pointer = 0;
5103 for (i = 0; i < n_archs; i++)
5104 if (strcasecmp (s, archs[i].name) == 0)
5105 break;
5106 if (i >= n_archs)
5107 {
5108 as_bad (_("%s: unrecognized processor name"), s);
5109 *input_line_pointer = c;
5110 ignore_rest_of_line ();
5111 return;
5112 }
5113 *input_line_pointer = c;
5114
5115 if (*input_line_pointer == '/')
5116 current_architecture = 0;
5117 else
5118 current_architecture &= m68881 | m68851;
5119 current_architecture |= archs[i].arch;
5120
5121 while (*input_line_pointer == '/')
5122 {
5123 ++input_line_pointer;
5124 s = input_line_pointer;
5125 /* We can't use get_symbol_end since the processor names are not
5126 proper symbols. */
5127 while (is_part_of_name (c = *input_line_pointer++))
5128 ;
5129 *--input_line_pointer = 0;
5130 if (strcmp (s, "68881") == 0)
5131 current_architecture |= m68881;
5132 else if (strcmp (s, "68851") == 0)
5133 current_architecture |= m68851;
5134 *input_line_pointer = c;
5135 }
5136
5137 /* Update info about available control registers. */
5138 select_control_regs ();
5139 }
5140
5141 /* The MRI CHIP pseudo-op. */
5142
5143 static void
5144 s_chip (ignore)
5145 int ignore ATTRIBUTE_UNUSED;
5146 {
5147 char *stop = NULL;
5148 char stopc;
5149
5150 if (flag_mri)
5151 stop = mri_comment_field (&stopc);
5152 mri_chip ();
5153 if (flag_mri)
5154 mri_comment_end (stop, stopc);
5155 demand_empty_rest_of_line ();
5156 }
5157
5158 /* The MRI FOPT pseudo-op. */
5159
5160 static void
5161 s_fopt (ignore)
5162 int ignore ATTRIBUTE_UNUSED;
5163 {
5164 SKIP_WHITESPACE ();
5165
5166 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5167 {
5168 int temp;
5169
5170 input_line_pointer += 3;
5171 temp = get_absolute_expression ();
5172 if (temp < 0 || temp > 7)
5173 as_bad (_("bad coprocessor id"));
5174 else
5175 m68k_float_copnum = COP0 + temp;
5176 }
5177 else
5178 {
5179 as_bad (_("unrecognized fopt option"));
5180 ignore_rest_of_line ();
5181 return;
5182 }
5183
5184 demand_empty_rest_of_line ();
5185 }
5186
5187 /* The structure used to handle the MRI OPT pseudo-op. */
5188
5189 struct opt_action
5190 {
5191 /* The name of the option. */
5192 const char *name;
5193
5194 /* If this is not NULL, just call this function. The first argument
5195 is the ARG field of this structure, the second argument is
5196 whether the option was negated. */
5197 void (*pfn) PARAMS ((int arg, int on));
5198
5199 /* If this is not NULL, and the PFN field is NULL, set the variable
5200 this points to. Set it to the ARG field if the option was not
5201 negated, and the NOTARG field otherwise. */
5202 int *pvar;
5203
5204 /* The value to pass to PFN or to assign to *PVAR. */
5205 int arg;
5206
5207 /* The value to assign to *PVAR if the option is negated. If PFN is
5208 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5209 the option may not be negated. */
5210 int notarg;
5211 };
5212
5213 /* The table used to handle the MRI OPT pseudo-op. */
5214
5215 static void skip_to_comma PARAMS ((int, int));
5216 static void opt_nest PARAMS ((int, int));
5217 static void opt_chip PARAMS ((int, int));
5218 static void opt_list PARAMS ((int, int));
5219 static void opt_list_symbols PARAMS ((int, int));
5220
5221 static const struct opt_action opt_table[] =
5222 {
5223 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5224
5225 /* We do relaxing, so there is little use for these options. */
5226 { "b", 0, 0, 0, 0 },
5227 { "brs", 0, 0, 0, 0 },
5228 { "brb", 0, 0, 0, 0 },
5229 { "brl", 0, 0, 0, 0 },
5230 { "brw", 0, 0, 0, 0 },
5231
5232 { "c", 0, 0, 0, 0 },
5233 { "cex", 0, 0, 0, 0 },
5234 { "case", 0, &symbols_case_sensitive, 1, 0 },
5235 { "cl", 0, 0, 0, 0 },
5236 { "cre", 0, 0, 0, 0 },
5237 { "d", 0, &flag_keep_locals, 1, 0 },
5238 { "e", 0, 0, 0, 0 },
5239 { "f", 0, &flag_short_refs, 1, 0 },
5240 { "frs", 0, &flag_short_refs, 1, 0 },
5241 { "frl", 0, &flag_short_refs, 0, 1 },
5242 { "g", 0, 0, 0, 0 },
5243 { "i", 0, 0, 0, 0 },
5244 { "m", 0, 0, 0, 0 },
5245 { "mex", 0, 0, 0, 0 },
5246 { "mc", 0, 0, 0, 0 },
5247 { "md", 0, 0, 0, 0 },
5248 { "nest", opt_nest, 0, 0, 0 },
5249 { "next", skip_to_comma, 0, 0, 0 },
5250 { "o", 0, 0, 0, 0 },
5251 { "old", 0, 0, 0, 0 },
5252 { "op", skip_to_comma, 0, 0, 0 },
5253 { "pco", 0, 0, 0, 0 },
5254 { "p", opt_chip, 0, 0, 0 },
5255 { "pcr", 0, 0, 0, 0 },
5256 { "pcs", 0, 0, 0, 0 },
5257 { "r", 0, 0, 0, 0 },
5258 { "quick", 0, &m68k_quick, 1, 0 },
5259 { "rel32", 0, &m68k_rel32, 1, 0 },
5260 { "s", opt_list, 0, 0, 0 },
5261 { "t", opt_list_symbols, 0, 0, 0 },
5262 { "w", 0, &flag_no_warnings, 0, 1 },
5263 { "x", 0, 0, 0, 0 }
5264 };
5265
5266 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5267
5268 /* The MRI OPT pseudo-op. */
5269
5270 static void
5271 s_opt (ignore)
5272 int ignore ATTRIBUTE_UNUSED;
5273 {
5274 do
5275 {
5276 int t;
5277 char *s;
5278 char c;
5279 int i;
5280 const struct opt_action *o;
5281
5282 SKIP_WHITESPACE ();
5283
5284 t = 1;
5285 if (*input_line_pointer == '-')
5286 {
5287 ++input_line_pointer;
5288 t = 0;
5289 }
5290 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5291 {
5292 input_line_pointer += 2;
5293 t = 0;
5294 }
5295
5296 s = input_line_pointer;
5297 c = get_symbol_end ();
5298
5299 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5300 {
5301 if (strcasecmp (s, o->name) == 0)
5302 {
5303 if (o->pfn)
5304 {
5305 /* Restore input_line_pointer now in case the option
5306 takes arguments. */
5307 *input_line_pointer = c;
5308 (*o->pfn) (o->arg, t);
5309 }
5310 else if (o->pvar != NULL)
5311 {
5312 if (! t && o->arg == o->notarg)
5313 as_bad (_("option `%s' may not be negated"), s);
5314 *input_line_pointer = c;
5315 *o->pvar = t ? o->arg : o->notarg;
5316 }
5317 else
5318 *input_line_pointer = c;
5319 break;
5320 }
5321 }
5322 if (i >= OPTCOUNT)
5323 {
5324 as_bad (_("option `%s' not recognized"), s);
5325 *input_line_pointer = c;
5326 }
5327 }
5328 while (*input_line_pointer++ == ',');
5329
5330 /* Move back to terminating character. */
5331 --input_line_pointer;
5332 demand_empty_rest_of_line ();
5333 }
5334
5335 /* Skip ahead to a comma. This is used for OPT options which we do
5336 not suppor tand which take arguments. */
5337
5338 static void
5339 skip_to_comma (arg, on)
5340 int arg ATTRIBUTE_UNUSED;
5341 int on ATTRIBUTE_UNUSED;
5342 {
5343 while (*input_line_pointer != ','
5344 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5345 ++input_line_pointer;
5346 }
5347
5348 /* Handle the OPT NEST=depth option. */
5349
5350 static void
5351 opt_nest (arg, on)
5352 int arg ATTRIBUTE_UNUSED;
5353 int on ATTRIBUTE_UNUSED;
5354 {
5355 if (*input_line_pointer != '=')
5356 {
5357 as_bad (_("bad format of OPT NEST=depth"));
5358 return;
5359 }
5360
5361 ++input_line_pointer;
5362 max_macro_nest = get_absolute_expression ();
5363 }
5364
5365 /* Handle the OPT P=chip option. */
5366
5367 static void
5368 opt_chip (arg, on)
5369 int arg ATTRIBUTE_UNUSED;
5370 int on ATTRIBUTE_UNUSED;
5371 {
5372 if (*input_line_pointer != '=')
5373 {
5374 /* This is just OPT P, which we do not support. */
5375 return;
5376 }
5377
5378 ++input_line_pointer;
5379 mri_chip ();
5380 }
5381
5382 /* Handle the OPT S option. */
5383
5384 static void
5385 opt_list (arg, on)
5386 int arg ATTRIBUTE_UNUSED;
5387 int on;
5388 {
5389 listing_list (on);
5390 }
5391
5392 /* Handle the OPT T option. */
5393
5394 static void
5395 opt_list_symbols (arg, on)
5396 int arg ATTRIBUTE_UNUSED;
5397 int on;
5398 {
5399 if (on)
5400 listing |= LISTING_SYMBOLS;
5401 else
5402 listing &=~ LISTING_SYMBOLS;
5403 }
5404
5405 /* Handle the MRI REG pseudo-op. */
5406
5407 static void
5408 s_reg (ignore)
5409 int ignore ATTRIBUTE_UNUSED;
5410 {
5411 char *s;
5412 int c;
5413 struct m68k_op rop;
5414 int mask;
5415 char *stop = NULL;
5416 char stopc;
5417
5418 if (line_label == NULL)
5419 {
5420 as_bad (_("missing label"));
5421 ignore_rest_of_line ();
5422 return;
5423 }
5424
5425 if (flag_mri)
5426 stop = mri_comment_field (&stopc);
5427
5428 SKIP_WHITESPACE ();
5429
5430 s = input_line_pointer;
5431 while (isalnum ((unsigned char) *input_line_pointer)
5432 #ifdef REGISTER_PREFIX
5433 || *input_line_pointer == REGISTER_PREFIX
5434 #endif
5435 || *input_line_pointer == '/'
5436 || *input_line_pointer == '-')
5437 ++input_line_pointer;
5438 c = *input_line_pointer;
5439 *input_line_pointer = '\0';
5440
5441 if (m68k_ip_op (s, &rop) != 0)
5442 {
5443 if (rop.error == NULL)
5444 as_bad (_("bad register list"));
5445 else
5446 as_bad (_("bad register list: %s"), rop.error);
5447 *input_line_pointer = c;
5448 ignore_rest_of_line ();
5449 return;
5450 }
5451
5452 *input_line_pointer = c;
5453
5454 if (rop.mode == REGLST)
5455 mask = rop.mask;
5456 else if (rop.mode == DREG)
5457 mask = 1 << (rop.reg - DATA0);
5458 else if (rop.mode == AREG)
5459 mask = 1 << (rop.reg - ADDR0 + 8);
5460 else if (rop.mode == FPREG)
5461 mask = 1 << (rop.reg - FP0 + 16);
5462 else if (rop.mode == CONTROL
5463 && rop.reg == FPI)
5464 mask = 1 << 24;
5465 else if (rop.mode == CONTROL
5466 && rop.reg == FPS)
5467 mask = 1 << 25;
5468 else if (rop.mode == CONTROL
5469 && rop.reg == FPC)
5470 mask = 1 << 26;
5471 else
5472 {
5473 as_bad (_("bad register list"));
5474 ignore_rest_of_line ();
5475 return;
5476 }
5477
5478 S_SET_SEGMENT (line_label, reg_section);
5479 S_SET_VALUE (line_label, ~mask);
5480 symbol_set_frag (line_label, &zero_address_frag);
5481
5482 if (flag_mri)
5483 mri_comment_end (stop, stopc);
5484
5485 demand_empty_rest_of_line ();
5486 }
5487
5488 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5489
5490 struct save_opts
5491 {
5492 struct save_opts *next;
5493 int abspcadd;
5494 int symbols_case_sensitive;
5495 int keep_locals;
5496 int short_refs;
5497 int architecture;
5498 int quick;
5499 int rel32;
5500 int listing;
5501 int no_warnings;
5502 /* FIXME: We don't save OPT S. */
5503 };
5504
5505 /* This variable holds the stack of saved options. */
5506
5507 static struct save_opts *save_stack;
5508
5509 /* The MRI SAVE pseudo-op. */
5510
5511 static void
5512 s_save (ignore)
5513 int ignore ATTRIBUTE_UNUSED;
5514 {
5515 struct save_opts *s;
5516
5517 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5518 s->abspcadd = m68k_abspcadd;
5519 s->symbols_case_sensitive = symbols_case_sensitive;
5520 s->keep_locals = flag_keep_locals;
5521 s->short_refs = flag_short_refs;
5522 s->architecture = current_architecture;
5523 s->quick = m68k_quick;
5524 s->rel32 = m68k_rel32;
5525 s->listing = listing;
5526 s->no_warnings = flag_no_warnings;
5527
5528 s->next = save_stack;
5529 save_stack = s;
5530
5531 demand_empty_rest_of_line ();
5532 }
5533
5534 /* The MRI RESTORE pseudo-op. */
5535
5536 static void
5537 s_restore (ignore)
5538 int ignore ATTRIBUTE_UNUSED;
5539 {
5540 struct save_opts *s;
5541
5542 if (save_stack == NULL)
5543 {
5544 as_bad (_("restore without save"));
5545 ignore_rest_of_line ();
5546 return;
5547 }
5548
5549 s = save_stack;
5550 save_stack = s->next;
5551
5552 m68k_abspcadd = s->abspcadd;
5553 symbols_case_sensitive = s->symbols_case_sensitive;
5554 flag_keep_locals = s->keep_locals;
5555 flag_short_refs = s->short_refs;
5556 current_architecture = s->architecture;
5557 m68k_quick = s->quick;
5558 m68k_rel32 = s->rel32;
5559 listing = s->listing;
5560 flag_no_warnings = s->no_warnings;
5561
5562 free (s);
5563
5564 demand_empty_rest_of_line ();
5565 }
5566
5567 /* Types of MRI structured control directives. */
5568
5569 enum mri_control_type
5570 {
5571 mri_for,
5572 mri_if,
5573 mri_repeat,
5574 mri_while
5575 };
5576
5577 /* This structure is used to stack the MRI structured control
5578 directives. */
5579
5580 struct mri_control_info
5581 {
5582 /* The directive within which this one is enclosed. */
5583 struct mri_control_info *outer;
5584
5585 /* The type of directive. */
5586 enum mri_control_type type;
5587
5588 /* Whether an ELSE has been in an IF. */
5589 int else_seen;
5590
5591 /* The add or sub statement at the end of a FOR. */
5592 char *incr;
5593
5594 /* The label of the top of a FOR or REPEAT loop. */
5595 char *top;
5596
5597 /* The label to jump to for the next iteration, or the else
5598 expression of a conditional. */
5599 char *next;
5600
5601 /* The label to jump to to break out of the loop, or the label past
5602 the end of a conditional. */
5603 char *bottom;
5604 };
5605
5606 /* The stack of MRI structured control directives. */
5607
5608 static struct mri_control_info *mri_control_stack;
5609
5610 /* The current MRI structured control directive index number, used to
5611 generate label names. */
5612
5613 static int mri_control_index;
5614
5615 /* Some function prototypes. */
5616
5617 static void mri_assemble PARAMS ((char *));
5618 static char *mri_control_label PARAMS ((void));
5619 static struct mri_control_info *push_mri_control
5620 PARAMS ((enum mri_control_type));
5621 static void pop_mri_control PARAMS ((void));
5622 static int parse_mri_condition PARAMS ((int *));
5623 static int parse_mri_control_operand
5624 PARAMS ((int *, char **, char **, char **, char **));
5625 static int swap_mri_condition PARAMS ((int));
5626 static int reverse_mri_condition PARAMS ((int));
5627 static void build_mri_control_operand
5628 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5629 const char *, int));
5630 static void parse_mri_control_expression
5631 PARAMS ((char *, int, const char *, const char *, int));
5632
5633 /* Assemble an instruction for an MRI structured control directive. */
5634
5635 static void
5636 mri_assemble (str)
5637 char *str;
5638 {
5639 char *s;
5640
5641 /* md_assemble expects the opcode to be in lower case. */
5642 for (s = str; *s != ' ' && *s != '\0'; s++)
5643 {
5644 if (isupper ((unsigned char) *s))
5645 *s = tolower ((unsigned char) *s);
5646 }
5647
5648 md_assemble (str);
5649 }
5650
5651 /* Generate a new MRI label structured control directive label name. */
5652
5653 static char *
5654 mri_control_label ()
5655 {
5656 char *n;
5657
5658 n = (char *) xmalloc (20);
5659 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5660 ++mri_control_index;
5661 return n;
5662 }
5663
5664 /* Create a new MRI structured control directive. */
5665
5666 static struct mri_control_info *
5667 push_mri_control (type)
5668 enum mri_control_type type;
5669 {
5670 struct mri_control_info *n;
5671
5672 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5673
5674 n->type = type;
5675 n->else_seen = 0;
5676 if (type == mri_if || type == mri_while)
5677 n->top = NULL;
5678 else
5679 n->top = mri_control_label ();
5680 n->next = mri_control_label ();
5681 n->bottom = mri_control_label ();
5682
5683 n->outer = mri_control_stack;
5684 mri_control_stack = n;
5685
5686 return n;
5687 }
5688
5689 /* Pop off the stack of MRI structured control directives. */
5690
5691 static void
5692 pop_mri_control ()
5693 {
5694 struct mri_control_info *n;
5695
5696 n = mri_control_stack;
5697 mri_control_stack = n->outer;
5698 if (n->top != NULL)
5699 free (n->top);
5700 free (n->next);
5701 free (n->bottom);
5702 free (n);
5703 }
5704
5705 /* Recognize a condition code in an MRI structured control expression. */
5706
5707 static int
5708 parse_mri_condition (pcc)
5709 int *pcc;
5710 {
5711 char c1, c2;
5712
5713 know (*input_line_pointer == '<');
5714
5715 ++input_line_pointer;
5716 c1 = *input_line_pointer++;
5717 c2 = *input_line_pointer++;
5718
5719 if (*input_line_pointer != '>')
5720 {
5721 as_bad (_("syntax error in structured control directive"));
5722 return 0;
5723 }
5724
5725 ++input_line_pointer;
5726 SKIP_WHITESPACE ();
5727
5728 if (isupper (c1))
5729 c1 = tolower (c1);
5730 if (isupper (c2))
5731 c2 = tolower (c2);
5732
5733 *pcc = (c1 << 8) | c2;
5734
5735 return 1;
5736 }
5737
5738 /* Parse a single operand in an MRI structured control expression. */
5739
5740 static int
5741 parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5742 int *pcc;
5743 char **leftstart;
5744 char **leftstop;
5745 char **rightstart;
5746 char **rightstop;
5747 {
5748 char *s;
5749
5750 SKIP_WHITESPACE ();
5751
5752 *pcc = -1;
5753 *leftstart = NULL;
5754 *leftstop = NULL;
5755 *rightstart = NULL;
5756 *rightstop = NULL;
5757
5758 if (*input_line_pointer == '<')
5759 {
5760 /* It's just a condition code. */
5761 return parse_mri_condition (pcc);
5762 }
5763
5764 /* Look ahead for the condition code. */
5765 for (s = input_line_pointer; *s != '\0'; ++s)
5766 {
5767 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5768 break;
5769 }
5770 if (*s == '\0')
5771 {
5772 as_bad (_("missing condition code in structured control directive"));
5773 return 0;
5774 }
5775
5776 *leftstart = input_line_pointer;
5777 *leftstop = s;
5778 if (*leftstop > *leftstart
5779 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5780 --*leftstop;
5781
5782 input_line_pointer = s;
5783 if (! parse_mri_condition (pcc))
5784 return 0;
5785
5786 /* Look ahead for AND or OR or end of line. */
5787 for (s = input_line_pointer; *s != '\0'; ++s)
5788 {
5789 if ((strncasecmp (s, "AND", 3) == 0
5790 && (s[3] == '.' || ! is_part_of_name (s[3])))
5791 || (strncasecmp (s, "OR", 2) == 0
5792 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5793 break;
5794 }
5795
5796 *rightstart = input_line_pointer;
5797 *rightstop = s;
5798 if (*rightstop > *rightstart
5799 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5800 --*rightstop;
5801
5802 input_line_pointer = s;
5803
5804 return 1;
5805 }
5806
5807 #define MCC(b1, b2) (((b1) << 8) | (b2))
5808
5809 /* Swap the sense of a condition. This changes the condition so that
5810 it generates the same result when the operands are swapped. */
5811
5812 static int
5813 swap_mri_condition (cc)
5814 int cc;
5815 {
5816 switch (cc)
5817 {
5818 case MCC ('h', 'i'): return MCC ('c', 's');
5819 case MCC ('l', 's'): return MCC ('c', 'c');
5820 case MCC ('c', 'c'): return MCC ('l', 's');
5821 case MCC ('c', 's'): return MCC ('h', 'i');
5822 case MCC ('p', 'l'): return MCC ('m', 'i');
5823 case MCC ('m', 'i'): return MCC ('p', 'l');
5824 case MCC ('g', 'e'): return MCC ('l', 'e');
5825 case MCC ('l', 't'): return MCC ('g', 't');
5826 case MCC ('g', 't'): return MCC ('l', 't');
5827 case MCC ('l', 'e'): return MCC ('g', 'e');
5828 }
5829 return cc;
5830 }
5831
5832 /* Reverse the sense of a condition. */
5833
5834 static int
5835 reverse_mri_condition (cc)
5836 int cc;
5837 {
5838 switch (cc)
5839 {
5840 case MCC ('h', 'i'): return MCC ('l', 's');
5841 case MCC ('l', 's'): return MCC ('h', 'i');
5842 case MCC ('c', 'c'): return MCC ('c', 's');
5843 case MCC ('c', 's'): return MCC ('c', 'c');
5844 case MCC ('n', 'e'): return MCC ('e', 'q');
5845 case MCC ('e', 'q'): return MCC ('n', 'e');
5846 case MCC ('v', 'c'): return MCC ('v', 's');
5847 case MCC ('v', 's'): return MCC ('v', 'c');
5848 case MCC ('p', 'l'): return MCC ('m', 'i');
5849 case MCC ('m', 'i'): return MCC ('p', 'l');
5850 case MCC ('g', 'e'): return MCC ('l', 't');
5851 case MCC ('l', 't'): return MCC ('g', 'e');
5852 case MCC ('g', 't'): return MCC ('l', 'e');
5853 case MCC ('l', 'e'): return MCC ('g', 't');
5854 }
5855 return cc;
5856 }
5857
5858 /* Build an MRI structured control expression. This generates test
5859 and branch instructions. It goes to TRUELAB if the condition is
5860 true, and to FALSELAB if the condition is false. Exactly one of
5861 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5862 is the size qualifier for the expression. EXTENT is the size to
5863 use for the branch. */
5864
5865 static void
5866 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5867 rightstop, truelab, falselab, extent)
5868 int qual;
5869 int cc;
5870 char *leftstart;
5871 char *leftstop;
5872 char *rightstart;
5873 char *rightstop;
5874 const char *truelab;
5875 const char *falselab;
5876 int extent;
5877 {
5878 char *buf;
5879 char *s;
5880
5881 if (leftstart != NULL)
5882 {
5883 struct m68k_op leftop, rightop;
5884 char c;
5885
5886 /* Swap the compare operands, if necessary, to produce a legal
5887 m68k compare instruction. Comparing a register operand with
5888 a non-register operand requires the register to be on the
5889 right (cmp, cmpa). Comparing an immediate value with
5890 anything requires the immediate value to be on the left
5891 (cmpi). */
5892
5893 c = *leftstop;
5894 *leftstop = '\0';
5895 (void) m68k_ip_op (leftstart, &leftop);
5896 *leftstop = c;
5897
5898 c = *rightstop;
5899 *rightstop = '\0';
5900 (void) m68k_ip_op (rightstart, &rightop);
5901 *rightstop = c;
5902
5903 if (rightop.mode == IMMED
5904 || ((leftop.mode == DREG || leftop.mode == AREG)
5905 && (rightop.mode != DREG && rightop.mode != AREG)))
5906 {
5907 char *temp;
5908
5909 cc = swap_mri_condition (cc);
5910 temp = leftstart;
5911 leftstart = rightstart;
5912 rightstart = temp;
5913 temp = leftstop;
5914 leftstop = rightstop;
5915 rightstop = temp;
5916 }
5917 }
5918
5919 if (truelab == NULL)
5920 {
5921 cc = reverse_mri_condition (cc);
5922 truelab = falselab;
5923 }
5924
5925 if (leftstart != NULL)
5926 {
5927 buf = (char *) xmalloc (20
5928 + (leftstop - leftstart)
5929 + (rightstop - rightstart));
5930 s = buf;
5931 *s++ = 'c';
5932 *s++ = 'm';
5933 *s++ = 'p';
5934 if (qual != '\0')
5935 *s++ = qual;
5936 *s++ = ' ';
5937 memcpy (s, leftstart, leftstop - leftstart);
5938 s += leftstop - leftstart;
5939 *s++ = ',';
5940 memcpy (s, rightstart, rightstop - rightstart);
5941 s += rightstop - rightstart;
5942 *s = '\0';
5943 mri_assemble (buf);
5944 free (buf);
5945 }
5946
5947 buf = (char *) xmalloc (20 + strlen (truelab));
5948 s = buf;
5949 *s++ = 'b';
5950 *s++ = cc >> 8;
5951 *s++ = cc & 0xff;
5952 if (extent != '\0')
5953 *s++ = extent;
5954 *s++ = ' ';
5955 strcpy (s, truelab);
5956 mri_assemble (buf);
5957 free (buf);
5958 }
5959
5960 /* Parse an MRI structured control expression. This generates test
5961 and branch instructions. STOP is where the expression ends. It
5962 goes to TRUELAB if the condition is true, and to FALSELAB if the
5963 condition is false. Exactly one of TRUELAB and FALSELAB will be
5964 NULL, meaning to fall through. QUAL is the size qualifier for the
5965 expression. EXTENT is the size to use for the branch. */
5966
5967 static void
5968 parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5969 char *stop;
5970 int qual;
5971 const char *truelab;
5972 const char *falselab;
5973 int extent;
5974 {
5975 int c;
5976 int cc;
5977 char *leftstart;
5978 char *leftstop;
5979 char *rightstart;
5980 char *rightstop;
5981
5982 c = *stop;
5983 *stop = '\0';
5984
5985 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5986 &rightstart, &rightstop))
5987 {
5988 *stop = c;
5989 return;
5990 }
5991
5992 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5993 {
5994 const char *flab;
5995
5996 if (falselab != NULL)
5997 flab = falselab;
5998 else
5999 flab = mri_control_label ();
6000
6001 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6002 rightstop, (const char *) NULL, flab, extent);
6003
6004 input_line_pointer += 3;
6005 if (*input_line_pointer != '.'
6006 || input_line_pointer[1] == '\0')
6007 qual = '\0';
6008 else
6009 {
6010 qual = input_line_pointer[1];
6011 input_line_pointer += 2;
6012 }
6013
6014 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6015 &rightstart, &rightstop))
6016 {
6017 *stop = c;
6018 return;
6019 }
6020
6021 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6022 rightstop, truelab, falselab, extent);
6023
6024 if (falselab == NULL)
6025 colon (flab);
6026 }
6027 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6028 {
6029 const char *tlab;
6030
6031 if (truelab != NULL)
6032 tlab = truelab;
6033 else
6034 tlab = mri_control_label ();
6035
6036 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6037 rightstop, tlab, (const char *) NULL, extent);
6038
6039 input_line_pointer += 2;
6040 if (*input_line_pointer != '.'
6041 || input_line_pointer[1] == '\0')
6042 qual = '\0';
6043 else
6044 {
6045 qual = input_line_pointer[1];
6046 input_line_pointer += 2;
6047 }
6048
6049 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6050 &rightstart, &rightstop))
6051 {
6052 *stop = c;
6053 return;
6054 }
6055
6056 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6057 rightstop, truelab, falselab, extent);
6058
6059 if (truelab == NULL)
6060 colon (tlab);
6061 }
6062 else
6063 {
6064 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6065 rightstop, truelab, falselab, extent);
6066 }
6067
6068 *stop = c;
6069 if (input_line_pointer != stop)
6070 as_bad (_("syntax error in structured control directive"));
6071 }
6072
6073 /* Handle the MRI IF pseudo-op. This may be a structured control
6074 directive, or it may be a regular assembler conditional, depending
6075 on its operands. */
6076
6077 static void
6078 s_mri_if (qual)
6079 int qual;
6080 {
6081 char *s;
6082 int c;
6083 struct mri_control_info *n;
6084
6085 /* A structured control directive must end with THEN with an
6086 optional qualifier. */
6087 s = input_line_pointer;
6088 while (! is_end_of_line[(unsigned char) *s]
6089 && (! flag_mri || *s != '*'))
6090 ++s;
6091 --s;
6092 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6093 --s;
6094
6095 if (s - input_line_pointer > 1
6096 && s[-1] == '.')
6097 s -= 2;
6098
6099 if (s - input_line_pointer < 3
6100 || strncasecmp (s - 3, "THEN", 4) != 0)
6101 {
6102 if (qual != '\0')
6103 {
6104 as_bad (_("missing then"));
6105 ignore_rest_of_line ();
6106 return;
6107 }
6108
6109 /* It's a conditional. */
6110 s_if (O_ne);
6111 return;
6112 }
6113
6114 /* Since this might be a conditional if, this pseudo-op will be
6115 called even if we are supported to be ignoring input. Double
6116 check now. Clobber *input_line_pointer so that ignore_input
6117 thinks that this is not a special pseudo-op. */
6118 c = *input_line_pointer;
6119 *input_line_pointer = 0;
6120 if (ignore_input ())
6121 {
6122 *input_line_pointer = c;
6123 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6124 ++input_line_pointer;
6125 demand_empty_rest_of_line ();
6126 return;
6127 }
6128 *input_line_pointer = c;
6129
6130 n = push_mri_control (mri_if);
6131
6132 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6133 n->next, s[1] == '.' ? s[2] : '\0');
6134
6135 if (s[1] == '.')
6136 input_line_pointer = s + 3;
6137 else
6138 input_line_pointer = s + 1;
6139
6140 if (flag_mri)
6141 {
6142 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6143 ++input_line_pointer;
6144 }
6145
6146 demand_empty_rest_of_line ();
6147 }
6148
6149 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6150 structured IF, associate the ELSE with the IF. Otherwise, assume
6151 it is a conditional else. */
6152
6153 static void
6154 s_mri_else (qual)
6155 int qual;
6156 {
6157 int c;
6158 char *buf;
6159 char q[2];
6160
6161 if (qual == '\0'
6162 && (mri_control_stack == NULL
6163 || mri_control_stack->type != mri_if
6164 || mri_control_stack->else_seen))
6165 {
6166 s_else (0);
6167 return;
6168 }
6169
6170 c = *input_line_pointer;
6171 *input_line_pointer = 0;
6172 if (ignore_input ())
6173 {
6174 *input_line_pointer = c;
6175 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6176 ++input_line_pointer;
6177 demand_empty_rest_of_line ();
6178 return;
6179 }
6180 *input_line_pointer = c;
6181
6182 if (mri_control_stack == NULL
6183 || mri_control_stack->type != mri_if
6184 || mri_control_stack->else_seen)
6185 {
6186 as_bad (_("else without matching if"));
6187 ignore_rest_of_line ();
6188 return;
6189 }
6190
6191 mri_control_stack->else_seen = 1;
6192
6193 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6194 q[0] = qual;
6195 q[1] = '\0';
6196 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6197 mri_assemble (buf);
6198 free (buf);
6199
6200 colon (mri_control_stack->next);
6201
6202 if (flag_mri)
6203 {
6204 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6205 ++input_line_pointer;
6206 }
6207
6208 demand_empty_rest_of_line ();
6209 }
6210
6211 /* Handle the MRI ENDI pseudo-op. */
6212
6213 static void
6214 s_mri_endi (ignore)
6215 int ignore ATTRIBUTE_UNUSED;
6216 {
6217 if (mri_control_stack == NULL
6218 || mri_control_stack->type != mri_if)
6219 {
6220 as_bad (_("endi without matching if"));
6221 ignore_rest_of_line ();
6222 return;
6223 }
6224
6225 /* ignore_input will not return true for ENDI, so we don't need to
6226 worry about checking it again here. */
6227
6228 if (! mri_control_stack->else_seen)
6229 colon (mri_control_stack->next);
6230 colon (mri_control_stack->bottom);
6231
6232 pop_mri_control ();
6233
6234 if (flag_mri)
6235 {
6236 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6237 ++input_line_pointer;
6238 }
6239
6240 demand_empty_rest_of_line ();
6241 }
6242
6243 /* Handle the MRI BREAK pseudo-op. */
6244
6245 static void
6246 s_mri_break (extent)
6247 int extent;
6248 {
6249 struct mri_control_info *n;
6250 char *buf;
6251 char ex[2];
6252
6253 n = mri_control_stack;
6254 while (n != NULL
6255 && n->type != mri_for
6256 && n->type != mri_repeat
6257 && n->type != mri_while)
6258 n = n->outer;
6259 if (n == NULL)
6260 {
6261 as_bad (_("break outside of structured loop"));
6262 ignore_rest_of_line ();
6263 return;
6264 }
6265
6266 buf = (char *) xmalloc (20 + strlen (n->bottom));
6267 ex[0] = extent;
6268 ex[1] = '\0';
6269 sprintf (buf, "bra%s %s", ex, n->bottom);
6270 mri_assemble (buf);
6271 free (buf);
6272
6273 if (flag_mri)
6274 {
6275 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6276 ++input_line_pointer;
6277 }
6278
6279 demand_empty_rest_of_line ();
6280 }
6281
6282 /* Handle the MRI NEXT pseudo-op. */
6283
6284 static void
6285 s_mri_next (extent)
6286 int extent;
6287 {
6288 struct mri_control_info *n;
6289 char *buf;
6290 char ex[2];
6291
6292 n = mri_control_stack;
6293 while (n != NULL
6294 && n->type != mri_for
6295 && n->type != mri_repeat
6296 && n->type != mri_while)
6297 n = n->outer;
6298 if (n == NULL)
6299 {
6300 as_bad (_("next outside of structured loop"));
6301 ignore_rest_of_line ();
6302 return;
6303 }
6304
6305 buf = (char *) xmalloc (20 + strlen (n->next));
6306 ex[0] = extent;
6307 ex[1] = '\0';
6308 sprintf (buf, "bra%s %s", ex, n->next);
6309 mri_assemble (buf);
6310 free (buf);
6311
6312 if (flag_mri)
6313 {
6314 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6315 ++input_line_pointer;
6316 }
6317
6318 demand_empty_rest_of_line ();
6319 }
6320
6321 /* Handle the MRI FOR pseudo-op. */
6322
6323 static void
6324 s_mri_for (qual)
6325 int qual;
6326 {
6327 const char *varstart, *varstop;
6328 const char *initstart, *initstop;
6329 const char *endstart, *endstop;
6330 const char *bystart, *bystop;
6331 int up;
6332 int by;
6333 int extent;
6334 struct mri_control_info *n;
6335 char *buf;
6336 char *s;
6337 char ex[2];
6338
6339 /* The syntax is
6340 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6341 */
6342
6343 SKIP_WHITESPACE ();
6344 varstart = input_line_pointer;
6345
6346 /* Look for the '='. */
6347 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6348 && *input_line_pointer != '=')
6349 ++input_line_pointer;
6350 if (*input_line_pointer != '=')
6351 {
6352 as_bad (_("missing ="));
6353 ignore_rest_of_line ();
6354 return;
6355 }
6356
6357 varstop = input_line_pointer;
6358 if (varstop > varstart
6359 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6360 --varstop;
6361
6362 ++input_line_pointer;
6363
6364 initstart = input_line_pointer;
6365
6366 /* Look for TO or DOWNTO. */
6367 up = 1;
6368 initstop = NULL;
6369 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6370 {
6371 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6372 && ! is_part_of_name (input_line_pointer[2]))
6373 {
6374 initstop = input_line_pointer;
6375 input_line_pointer += 2;
6376 break;
6377 }
6378 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6379 && ! is_part_of_name (input_line_pointer[6]))
6380 {
6381 initstop = input_line_pointer;
6382 up = 0;
6383 input_line_pointer += 6;
6384 break;
6385 }
6386 ++input_line_pointer;
6387 }
6388 if (initstop == NULL)
6389 {
6390 as_bad (_("missing to or downto"));
6391 ignore_rest_of_line ();
6392 return;
6393 }
6394 if (initstop > initstart
6395 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6396 --initstop;
6397
6398 SKIP_WHITESPACE ();
6399 endstart = input_line_pointer;
6400
6401 /* Look for BY or DO. */
6402 by = 0;
6403 endstop = NULL;
6404 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6405 {
6406 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6407 && ! is_part_of_name (input_line_pointer[2]))
6408 {
6409 endstop = input_line_pointer;
6410 by = 1;
6411 input_line_pointer += 2;
6412 break;
6413 }
6414 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6415 && (input_line_pointer[2] == '.'
6416 || ! is_part_of_name (input_line_pointer[2])))
6417 {
6418 endstop = input_line_pointer;
6419 input_line_pointer += 2;
6420 break;
6421 }
6422 ++input_line_pointer;
6423 }
6424 if (endstop == NULL)
6425 {
6426 as_bad (_("missing do"));
6427 ignore_rest_of_line ();
6428 return;
6429 }
6430 if (endstop > endstart
6431 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6432 --endstop;
6433
6434 if (! by)
6435 {
6436 bystart = "#1";
6437 bystop = bystart + 2;
6438 }
6439 else
6440 {
6441 SKIP_WHITESPACE ();
6442 bystart = input_line_pointer;
6443
6444 /* Look for DO. */
6445 bystop = NULL;
6446 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6447 {
6448 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6449 && (input_line_pointer[2] == '.'
6450 || ! is_part_of_name (input_line_pointer[2])))
6451 {
6452 bystop = input_line_pointer;
6453 input_line_pointer += 2;
6454 break;
6455 }
6456 ++input_line_pointer;
6457 }
6458 if (bystop == NULL)
6459 {
6460 as_bad (_("missing do"));
6461 ignore_rest_of_line ();
6462 return;
6463 }
6464 if (bystop > bystart
6465 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6466 --bystop;
6467 }
6468
6469 if (*input_line_pointer != '.')
6470 extent = '\0';
6471 else
6472 {
6473 extent = input_line_pointer[1];
6474 input_line_pointer += 2;
6475 }
6476
6477 /* We have fully parsed the FOR operands. Now build the loop. */
6478
6479 n = push_mri_control (mri_for);
6480
6481 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6482
6483 /* move init,var */
6484 s = buf;
6485 *s++ = 'm';
6486 *s++ = 'o';
6487 *s++ = 'v';
6488 *s++ = 'e';
6489 if (qual != '\0')
6490 *s++ = qual;
6491 *s++ = ' ';
6492 memcpy (s, initstart, initstop - initstart);
6493 s += initstop - initstart;
6494 *s++ = ',';
6495 memcpy (s, varstart, varstop - varstart);
6496 s += varstop - varstart;
6497 *s = '\0';
6498 mri_assemble (buf);
6499
6500 colon (n->top);
6501
6502 /* cmp end,var */
6503 s = buf;
6504 *s++ = 'c';
6505 *s++ = 'm';
6506 *s++ = 'p';
6507 if (qual != '\0')
6508 *s++ = qual;
6509 *s++ = ' ';
6510 memcpy (s, endstart, endstop - endstart);
6511 s += endstop - endstart;
6512 *s++ = ',';
6513 memcpy (s, varstart, varstop - varstart);
6514 s += varstop - varstart;
6515 *s = '\0';
6516 mri_assemble (buf);
6517
6518 /* bcc bottom */
6519 ex[0] = extent;
6520 ex[1] = '\0';
6521 if (up)
6522 sprintf (buf, "blt%s %s", ex, n->bottom);
6523 else
6524 sprintf (buf, "bgt%s %s", ex, n->bottom);
6525 mri_assemble (buf);
6526
6527 /* Put together the add or sub instruction used by ENDF. */
6528 s = buf;
6529 if (up)
6530 strcpy (s, "add");
6531 else
6532 strcpy (s, "sub");
6533 s += 3;
6534 if (qual != '\0')
6535 *s++ = qual;
6536 *s++ = ' ';
6537 memcpy (s, bystart, bystop - bystart);
6538 s += bystop - bystart;
6539 *s++ = ',';
6540 memcpy (s, varstart, varstop - varstart);
6541 s += varstop - varstart;
6542 *s = '\0';
6543 n->incr = buf;
6544
6545 if (flag_mri)
6546 {
6547 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6548 ++input_line_pointer;
6549 }
6550
6551 demand_empty_rest_of_line ();
6552 }
6553
6554 /* Handle the MRI ENDF pseudo-op. */
6555
6556 static void
6557 s_mri_endf (ignore)
6558 int ignore ATTRIBUTE_UNUSED;
6559 {
6560 if (mri_control_stack == NULL
6561 || mri_control_stack->type != mri_for)
6562 {
6563 as_bad (_("endf without for"));
6564 ignore_rest_of_line ();
6565 return;
6566 }
6567
6568 colon (mri_control_stack->next);
6569
6570 mri_assemble (mri_control_stack->incr);
6571
6572 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6573 mri_assemble (mri_control_stack->incr);
6574
6575 free (mri_control_stack->incr);
6576
6577 colon (mri_control_stack->bottom);
6578
6579 pop_mri_control ();
6580
6581 if (flag_mri)
6582 {
6583 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6584 ++input_line_pointer;
6585 }
6586
6587 demand_empty_rest_of_line ();
6588 }
6589
6590 /* Handle the MRI REPEAT pseudo-op. */
6591
6592 static void
6593 s_mri_repeat (ignore)
6594 int ignore ATTRIBUTE_UNUSED;
6595 {
6596 struct mri_control_info *n;
6597
6598 n = push_mri_control (mri_repeat);
6599 colon (n->top);
6600 if (flag_mri)
6601 {
6602 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6603 ++input_line_pointer;
6604 }
6605 demand_empty_rest_of_line ();
6606 }
6607
6608 /* Handle the MRI UNTIL pseudo-op. */
6609
6610 static void
6611 s_mri_until (qual)
6612 int qual;
6613 {
6614 char *s;
6615
6616 if (mri_control_stack == NULL
6617 || mri_control_stack->type != mri_repeat)
6618 {
6619 as_bad (_("until without repeat"));
6620 ignore_rest_of_line ();
6621 return;
6622 }
6623
6624 colon (mri_control_stack->next);
6625
6626 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6627 ;
6628
6629 parse_mri_control_expression (s, qual, (const char *) NULL,
6630 mri_control_stack->top, '\0');
6631
6632 colon (mri_control_stack->bottom);
6633
6634 input_line_pointer = s;
6635
6636 pop_mri_control ();
6637
6638 if (flag_mri)
6639 {
6640 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6641 ++input_line_pointer;
6642 }
6643
6644 demand_empty_rest_of_line ();
6645 }
6646
6647 /* Handle the MRI WHILE pseudo-op. */
6648
6649 static void
6650 s_mri_while (qual)
6651 int qual;
6652 {
6653 char *s;
6654
6655 struct mri_control_info *n;
6656
6657 s = input_line_pointer;
6658 while (! is_end_of_line[(unsigned char) *s]
6659 && (! flag_mri || *s != '*'))
6660 s++;
6661 --s;
6662 while (*s == ' ' || *s == '\t')
6663 --s;
6664 if (s - input_line_pointer > 1
6665 && s[-1] == '.')
6666 s -= 2;
6667 if (s - input_line_pointer < 2
6668 || strncasecmp (s - 1, "DO", 2) != 0)
6669 {
6670 as_bad (_("missing do"));
6671 ignore_rest_of_line ();
6672 return;
6673 }
6674
6675 n = push_mri_control (mri_while);
6676
6677 colon (n->next);
6678
6679 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6680 s[1] == '.' ? s[2] : '\0');
6681
6682 input_line_pointer = s + 1;
6683 if (*input_line_pointer == '.')
6684 input_line_pointer += 2;
6685
6686 if (flag_mri)
6687 {
6688 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6689 ++input_line_pointer;
6690 }
6691
6692 demand_empty_rest_of_line ();
6693 }
6694
6695 /* Handle the MRI ENDW pseudo-op. */
6696
6697 static void
6698 s_mri_endw (ignore)
6699 int ignore ATTRIBUTE_UNUSED;
6700 {
6701 char *buf;
6702
6703 if (mri_control_stack == NULL
6704 || mri_control_stack->type != mri_while)
6705 {
6706 as_bad (_("endw without while"));
6707 ignore_rest_of_line ();
6708 return;
6709 }
6710
6711 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6712 sprintf (buf, "bra %s", mri_control_stack->next);
6713 mri_assemble (buf);
6714 free (buf);
6715
6716 colon (mri_control_stack->bottom);
6717
6718 pop_mri_control ();
6719
6720 if (flag_mri)
6721 {
6722 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6723 ++input_line_pointer;
6724 }
6725
6726 demand_empty_rest_of_line ();
6727 }
6728 \f
6729 /*
6730 * md_parse_option
6731 * Invocation line includes a switch not recognized by the base assembler.
6732 * See if it's a processor-specific option. These are:
6733 *
6734 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6735 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6736 * Select the architecture. Instructions or features not
6737 * supported by the selected architecture cause fatal
6738 * errors. More than one may be specified. The default is
6739 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6740 * for -m68000, and -m68882 is a synonym for -m68881.
6741 * -[A]m[c]no-68851, -[A]m[c]no-68881
6742 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6743 * so don't use or document it, but that's the way the parsing
6744 * works).
6745 *
6746 * -pic Indicates PIC.
6747 * -k Indicates PIC. (Sun 3 only.)
6748 * --pcrel Never turn PC-relative branches into absolute jumps.
6749 *
6750 * --bitwise-or
6751 * Permit `|' to be used in expressions.
6752 *
6753 */
6754
6755 #ifdef OBJ_ELF
6756 CONST char *md_shortopts = "lSA:m:kQ:V";
6757 #else
6758 CONST char *md_shortopts = "lSA:m:k";
6759 #endif
6760
6761 struct option md_longopts[] = {
6762 #define OPTION_PIC (OPTION_MD_BASE)
6763 {"pic", no_argument, NULL, OPTION_PIC},
6764 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6765 {"register-prefix-optional", no_argument, NULL,
6766 OPTION_REGISTER_PREFIX_OPTIONAL},
6767 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6768 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6769 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6770 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6771 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6772 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6773 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6774 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6775 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6776 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
6777 #define OPTION_PCREL (OPTION_MD_BASE + 7)
6778 {"pcrel", no_argument, NULL, OPTION_PCREL},
6779 {NULL, no_argument, NULL, 0}
6780 };
6781 size_t md_longopts_size = sizeof (md_longopts);
6782
6783 int
6784 md_parse_option (c, arg)
6785 int c;
6786 char *arg;
6787 {
6788 switch (c)
6789 {
6790 case 'l': /* -l means keep external to 2 bit offset
6791 rather than 16 bit one */
6792 flag_short_refs = 1;
6793 break;
6794
6795 case 'S': /* -S means that jbsr's always turn into
6796 jsr's. */
6797 flag_long_jumps = 1;
6798 break;
6799
6800 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6801 branches into absolute jumps. */
6802 flag_keep_pcrel = 1;
6803 break;
6804
6805 case 'A':
6806 if (*arg == 'm')
6807 arg++;
6808 /* intentional fall-through */
6809 case 'm':
6810
6811 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6812 {
6813 int i;
6814 unsigned long arch;
6815 const char *oarg = arg;
6816
6817 arg += 3;
6818 if (*arg == 'm')
6819 {
6820 arg++;
6821 if (arg[0] == 'c' && arg[1] == '6')
6822 arg++;
6823 }
6824 for (i = 0; i < n_archs; i++)
6825 if (!strcmp (arg, archs[i].name))
6826 break;
6827 if (i == n_archs)
6828 {
6829 unknown:
6830 as_bad (_("unrecognized option `%s'"), oarg);
6831 return 0;
6832 }
6833 arch = archs[i].arch;
6834 if (arch == m68881)
6835 no_68881 = 1;
6836 else if (arch == m68851)
6837 no_68851 = 1;
6838 else
6839 goto unknown;
6840 }
6841 else
6842 {
6843 int i;
6844
6845 if (arg[0] == 'c' && arg[1] == '6')
6846 arg++;
6847
6848 for (i = 0; i < n_archs; i++)
6849 if (!strcmp (arg, archs[i].name))
6850 {
6851 unsigned long arch = archs[i].arch;
6852 if (cpu_of_arch (arch))
6853 /* It's a cpu spec. */
6854 {
6855 current_architecture &= ~m68000up;
6856 current_architecture |= arch;
6857 }
6858 else if (arch == m68881)
6859 {
6860 current_architecture |= m68881;
6861 no_68881 = 0;
6862 }
6863 else if (arch == m68851)
6864 {
6865 current_architecture |= m68851;
6866 no_68851 = 0;
6867 }
6868 else
6869 /* ??? */
6870 abort ();
6871 break;
6872 }
6873 if (i == n_archs)
6874 {
6875 as_bad (_("unrecognized architecture specification `%s'"), arg);
6876 return 0;
6877 }
6878 }
6879 break;
6880
6881 case OPTION_PIC:
6882 case 'k':
6883 flag_want_pic = 1;
6884 break; /* -pic, Position Independent Code */
6885
6886 case OPTION_REGISTER_PREFIX_OPTIONAL:
6887 flag_reg_prefix_optional = 1;
6888 reg_prefix_optional_seen = 1;
6889 break;
6890
6891 /* -V: SVR4 argument to print version ID. */
6892 case 'V':
6893 print_version_id ();
6894 break;
6895
6896 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6897 should be emitted or not. FIXME: Not implemented. */
6898 case 'Q':
6899 break;
6900
6901 case OPTION_BITWISE_OR:
6902 {
6903 char *n, *t;
6904 const char *s;
6905
6906 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6907 t = n;
6908 for (s = m68k_comment_chars; *s != '\0'; s++)
6909 if (*s != '|')
6910 *t++ = *s;
6911 *t = '\0';
6912 m68k_comment_chars = n;
6913 }
6914 break;
6915
6916 case OPTION_BASE_SIZE_DEFAULT_16:
6917 m68k_index_width_default = SIZE_WORD;
6918 break;
6919
6920 case OPTION_BASE_SIZE_DEFAULT_32:
6921 m68k_index_width_default = SIZE_LONG;
6922 break;
6923
6924 case OPTION_DISP_SIZE_DEFAULT_16:
6925 m68k_rel32 = 0;
6926 m68k_rel32_from_cmdline = 1;
6927 break;
6928
6929 case OPTION_DISP_SIZE_DEFAULT_32:
6930 m68k_rel32 = 1;
6931 m68k_rel32_from_cmdline = 1;
6932 break;
6933
6934 default:
6935 return 0;
6936 }
6937
6938 return 1;
6939 }
6940
6941 void
6942 md_show_usage (stream)
6943 FILE *stream;
6944 {
6945 fprintf (stream, _("\
6946 680X0 options:\n\
6947 -l use 1 word for refs to undefined symbols [default 2]\n\
6948 -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6949 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6950 | -mcpu32 | -m5200\n\
6951 specify variant of 680X0 architecture [default 68020]\n\
6952 -m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6953 target has/lacks floating-point coprocessor\n\
6954 [default yes for 68020, 68030, and cpu32]\n"));
6955 fprintf (stream, _("\
6956 -m68851 | -mno-68851\n\
6957 target has/lacks memory-management unit coprocessor\n\
6958 [default yes for 68020 and up]\n\
6959 -pic, -k generate position independent code\n\
6960 -S turn jbsr into jsr\n\
6961 --pcrel never turn PC-relative branches into absolute jumps\n\
6962 --register-prefix-optional\n\
6963 recognize register names without prefix character\n\
6964 --bitwise-or do not treat `|' as a comment character\n"));
6965 fprintf (stream, _("\
6966 --base-size-default-16 base reg without size is 16 bits\n\
6967 --base-size-default-32 base reg without size is 32 bits (default)\n\
6968 --disp-size-default-16 displacement with unknown size is 16 bits\n\
6969 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6970 }
6971 \f
6972 #ifdef TEST2
6973
6974 /* TEST2: Test md_assemble() */
6975 /* Warning, this routine probably doesn't work anymore */
6976
6977 main ()
6978 {
6979 struct m68k_it the_ins;
6980 char buf[120];
6981 char *cp;
6982 int n;
6983
6984 m68k_ip_begin ();
6985 for (;;)
6986 {
6987 if (!gets (buf) || !*buf)
6988 break;
6989 if (buf[0] == '|' || buf[1] == '.')
6990 continue;
6991 for (cp = buf; *cp; cp++)
6992 if (*cp == '\t')
6993 *cp = ' ';
6994 if (is_label (buf))
6995 continue;
6996 memset (&the_ins, '\0', sizeof (the_ins));
6997 m68k_ip (&the_ins, buf);
6998 if (the_ins.error)
6999 {
7000 printf (_("Error %s in %s\n"), the_ins.error, buf);
7001 }
7002 else
7003 {
7004 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7005 for (n = 0; n < the_ins.numo; n++)
7006 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7007 printf (" ");
7008 print_the_insn (&the_ins.opcode[0], stdout);
7009 (void) putchar ('\n');
7010 }
7011 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7012 {
7013 if (the_ins.operands[n].error)
7014 {
7015 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7016 continue;
7017 }
7018 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7019 if (the_ins.operands[n].b_const)
7020 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7021 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7022 if (the_ins.operands[n].b_iadd)
7023 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7024 (void) putchar ('\n');
7025 }
7026 }
7027 m68k_ip_end ();
7028 return 0;
7029 }
7030
7031 is_label (str)
7032 char *str;
7033 {
7034 while (*str == ' ')
7035 str++;
7036 while (*str && *str != ' ')
7037 str++;
7038 if (str[-1] == ':' || str[1] == '=')
7039 return 1;
7040 return 0;
7041 }
7042
7043 #endif
7044
7045 /* Possible states for relaxation:
7046
7047 0 0 branch offset byte (bra, etc)
7048 0 1 word
7049 0 2 long
7050
7051 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7052 1 1 word
7053 1 2 long
7054
7055 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7056 2 1 word-long
7057 2 2 long-word
7058 2 3 long-long
7059
7060 */
7061
7062 /* We have no need to default values of symbols. */
7063
7064 symbolS *
7065 md_undefined_symbol (name)
7066 char *name ATTRIBUTE_UNUSED;
7067 {
7068 return 0;
7069 }
7070
7071 /* Round up a section size to the appropriate boundary. */
7072 valueT
7073 md_section_align (segment, size)
7074 segT segment ATTRIBUTE_UNUSED;
7075 valueT size;
7076 {
7077 #ifdef OBJ_AOUT
7078 #ifdef BFD_ASSEMBLER
7079 /* For a.out, force the section size to be aligned. If we don't do
7080 this, BFD will align it for us, but it will not write out the
7081 final bytes of the section. This may be a bug in BFD, but it is
7082 easier to fix it here since that is how the other a.out targets
7083 work. */
7084 int align;
7085
7086 align = bfd_get_section_alignment (stdoutput, segment);
7087 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7088 #endif
7089 #endif
7090
7091 return size;
7092 }
7093
7094 /* Exactly what point is a PC-relative offset relative TO?
7095 On the 68k, it is relative to the address of the first extension
7096 word. The difference between the addresses of the offset and the
7097 first extension word is stored in fx_pcrel_adjust. */
7098 long
7099 md_pcrel_from (fixP)
7100 fixS *fixP;
7101 {
7102 int adjust;
7103
7104 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7105 -1 as 64. */
7106 adjust = fixP->fx_pcrel_adjust;
7107 if (adjust == 64)
7108 adjust = -1;
7109 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7110 }
7111
7112 #ifndef BFD_ASSEMBLER
7113 #ifdef OBJ_COFF
7114
7115 void
7116 tc_coff_symbol_emit_hook (ignore)
7117 symbolS *ignore ATTRIBUTE_UNUSED;
7118 {
7119 }
7120
7121 int
7122 tc_coff_sizemachdep (frag)
7123 fragS *frag;
7124 {
7125 switch (frag->fr_subtype & 0x3)
7126 {
7127 case BYTE:
7128 return 1;
7129 case SHORT:
7130 return 2;
7131 case LONG:
7132 return 4;
7133 default:
7134 abort ();
7135 return 0;
7136 }
7137 }
7138
7139 #endif
7140 #endif
7141 #ifdef OBJ_ELF
7142 void m68k_elf_final_processing()
7143 {
7144 /* Set file-specific flags if this is a cpu32 processor */
7145 if (cpu_of_arch (current_architecture) & cpu32)
7146 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7147 }
7148 #endif