1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 #define AT mips_opts.at
106 /* Allow override of standard little-endian ECOFF format. */
108 #ifndef ECOFF_LITTLE_FORMAT
109 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
112 extern int target_big_endian
;
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* Information about an instruction, including its format, operands
127 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
128 const struct mips_opcode
*insn_mo
;
130 /* True if this is a mips16 instruction and if we want the extended
132 bfd_boolean use_extend
;
134 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
135 unsigned short extend
;
137 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
138 a copy of INSN_MO->match with the operands filled in. */
139 unsigned long insn_opcode
;
141 /* The frag that contains the instruction. */
144 /* The offset into FRAG of the first instruction byte. */
147 /* The relocs associated with the instruction, if any. */
150 /* True if this entry cannot be moved from its current position. */
151 unsigned int fixed_p
: 1;
153 /* True if this instruction occurred in a .set noreorder block. */
154 unsigned int noreorder_p
: 1;
156 /* True for mips16 instructions that jump to an absolute address. */
157 unsigned int mips16_absolute_jump_p
: 1;
160 /* The ABI to use. */
171 /* MIPS ABI we are using for this output file. */
172 static enum mips_abi_level mips_abi
= NO_ABI
;
174 /* Whether or not we have code that can call pic code. */
175 int mips_abicalls
= FALSE
;
177 /* Whether or not we have code which can be put into a shared
179 static bfd_boolean mips_in_shared
= TRUE
;
181 /* This is the set of options which may be modified by the .set
182 pseudo-op. We use a struct so that .set push and .set pop are more
185 struct mips_set_options
187 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
188 if it has not been initialized. Changed by `.set mipsN', and the
189 -mipsN command line option, and the default CPU. */
191 /* Enabled Application Specific Extensions (ASEs). These are set to -1
192 if they have not been initialized. Changed by `.set <asename>', by
193 command line options, and based on the default architecture. */
200 /* Whether we are assembling for the mips16 processor. 0 if we are
201 not, 1 if we are, and -1 if the value has not been initialized.
202 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
203 -nomips16 command line options, and the default CPU. */
205 /* Non-zero if we should not reorder instructions. Changed by `.set
206 reorder' and `.set noreorder'. */
208 /* Non-zero if we should not permit the register designated "assembler
209 temporary" to be used in instructions. The value is the register
210 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
211 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
213 /* Non-zero if we should warn when a macro instruction expands into
214 more than one machine instruction. Changed by `.set nomacro' and
216 int warn_about_macros
;
217 /* Non-zero if we should not move instructions. Changed by `.set
218 move', `.set volatile', `.set nomove', and `.set novolatile'. */
220 /* Non-zero if we should not optimize branches by moving the target
221 of the branch into the delay slot. Actually, we don't perform
222 this optimization anyhow. Changed by `.set bopt' and `.set
225 /* Non-zero if we should not autoextend mips16 instructions.
226 Changed by `.set autoextend' and `.set noautoextend'. */
228 /* Restrict general purpose registers and floating point registers
229 to 32 bit. This is initially determined when -mgp32 or -mfp32
230 is passed but can changed if the assembler code uses .set mipsN. */
233 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
234 command line option, and the default CPU. */
236 /* True if ".set sym32" is in effect. */
238 /* True if floating-point operations are not allowed. Changed by .set
239 softfloat or .set hardfloat, by command line options -msoft-float or
240 -mhard-float. The default is false. */
241 bfd_boolean soft_float
;
243 /* True if only single-precision floating-point operations are allowed.
244 Changed by .set singlefloat or .set doublefloat, command-line options
245 -msingle-float or -mdouble-float. The default is false. */
246 bfd_boolean single_float
;
249 /* This is the struct we use to hold the current set of options. Note
250 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
251 -1 to indicate that they have not been initialized. */
253 /* True if -mgp32 was passed. */
254 static int file_mips_gp32
= -1;
256 /* True if -mfp32 was passed. */
257 static int file_mips_fp32
= -1;
259 /* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */
260 static int file_mips_soft_float
= 0;
262 /* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */
263 static int file_mips_single_float
= 0;
265 static struct mips_set_options mips_opts
=
267 /* isa */ ISA_UNKNOWN
, /* ase_mips3d */ -1, /* ase_mdmx */ -1,
268 /* ase_smartmips */ 0, /* ase_dsp */ -1, /* ase_dspr2 */ -1, /* ase_mt */ -1,
269 /* mips16 */ -1, /* noreorder */ 0, /* at */ ATREG
,
270 /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0,
271 /* noautoextend */ 0, /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN
,
272 /* sym32 */ FALSE
, /* soft_float */ FALSE
, /* single_float */ FALSE
275 /* These variables are filled in with the masks of registers used.
276 The object format code reads them and puts them in the appropriate
278 unsigned long mips_gprmask
;
279 unsigned long mips_cprmask
[4];
281 /* MIPS ISA we are using for this output file. */
282 static int file_mips_isa
= ISA_UNKNOWN
;
284 /* True if -mips16 was passed or implied by arguments passed on the
285 command line (e.g., by -march). */
286 static int file_ase_mips16
;
288 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
289 || mips_opts.isa == ISA_MIPS32R2 \
290 || mips_opts.isa == ISA_MIPS64 \
291 || mips_opts.isa == ISA_MIPS64R2)
293 /* True if -mips3d was passed or implied by arguments passed on the
294 command line (e.g., by -march). */
295 static int file_ase_mips3d
;
297 /* True if -mdmx was passed or implied by arguments passed on the
298 command line (e.g., by -march). */
299 static int file_ase_mdmx
;
301 /* True if -msmartmips was passed or implied by arguments passed on the
302 command line (e.g., by -march). */
303 static int file_ase_smartmips
;
305 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
306 || mips_opts.isa == ISA_MIPS32R2)
308 /* True if -mdsp was passed or implied by arguments passed on the
309 command line (e.g., by -march). */
310 static int file_ase_dsp
;
312 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
313 || mips_opts.isa == ISA_MIPS64R2)
315 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
317 /* True if -mdspr2 was passed or implied by arguments passed on the
318 command line (e.g., by -march). */
319 static int file_ase_dspr2
;
321 #define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
322 || mips_opts.isa == ISA_MIPS64R2)
324 /* True if -mmt was passed or implied by arguments passed on the
325 command line (e.g., by -march). */
326 static int file_ase_mt
;
328 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
329 || mips_opts.isa == ISA_MIPS64R2)
331 /* The argument of the -march= flag. The architecture we are assembling. */
332 static int file_mips_arch
= CPU_UNKNOWN
;
333 static const char *mips_arch_string
;
335 /* The argument of the -mtune= flag. The architecture for which we
337 static int mips_tune
= CPU_UNKNOWN
;
338 static const char *mips_tune_string
;
340 /* True when generating 32-bit code for a 64-bit processor. */
341 static int mips_32bitmode
= 0;
343 /* True if the given ABI requires 32-bit registers. */
344 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
346 /* Likewise 64-bit registers. */
347 #define ABI_NEEDS_64BIT_REGS(ABI) \
349 || (ABI) == N64_ABI \
352 /* Return true if ISA supports 64 bit wide gp registers. */
353 #define ISA_HAS_64BIT_REGS(ISA) \
354 ((ISA) == ISA_MIPS3 \
355 || (ISA) == ISA_MIPS4 \
356 || (ISA) == ISA_MIPS5 \
357 || (ISA) == ISA_MIPS64 \
358 || (ISA) == ISA_MIPS64R2)
360 /* Return true if ISA supports 64 bit wide float registers. */
361 #define ISA_HAS_64BIT_FPRS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS32R2 \
366 || (ISA) == ISA_MIPS64 \
367 || (ISA) == ISA_MIPS64R2)
369 /* Return true if ISA supports 64-bit right rotate (dror et al.)
371 #define ISA_HAS_DROR(ISA) \
372 ((ISA) == ISA_MIPS64R2)
374 /* Return true if ISA supports 32-bit right rotate (ror et al.)
376 #define ISA_HAS_ROR(ISA) \
377 ((ISA) == ISA_MIPS32R2 \
378 || (ISA) == ISA_MIPS64R2 \
379 || mips_opts.ase_smartmips)
381 /* Return true if ISA supports single-precision floats in odd registers. */
382 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
388 /* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390 #define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
394 #define HAVE_32BIT_GPRS \
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
397 #define HAVE_32BIT_FPRS \
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
400 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
403 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
405 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
407 /* True if relocations are stored in-place. */
408 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
410 /* The ABI-derived address size. */
411 #define HAVE_64BIT_ADDRESSES \
412 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
413 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
415 /* The size of symbolic constants (i.e., expressions of the form
416 "SYMBOL" or "SYMBOL + OFFSET"). */
417 #define HAVE_32BIT_SYMBOLS \
418 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
419 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
421 /* Addresses are loaded in different ways, depending on the address size
422 in use. The n32 ABI Documentation also mandates the use of additions
423 with overflow checking, but existing implementations don't follow it. */
424 #define ADDRESS_ADD_INSN \
425 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
427 #define ADDRESS_ADDI_INSN \
428 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
430 #define ADDRESS_LOAD_INSN \
431 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
433 #define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
436 /* Return true if the given CPU supports the MIPS16 ASE. */
437 #define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
441 /* True if CPU has a dror instruction. */
442 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
444 /* True if CPU has a ror instruction. */
445 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
447 /* True if CPU has seq/sne and seqi/snei instructions. */
448 #define CPU_HAS_SEQ(CPU) ((CPU) == CPU_OCTEON)
450 /* True if CPU does not implement the all the coprocessor insns. For these
451 CPUs only those COP insns are accepted that are explicitly marked to be
452 available on the CPU. ISA membership for COP insns is ignored. */
453 #define NO_ISA_COP(CPU) ((CPU) == CPU_OCTEON)
455 /* True if mflo and mfhi can be immediately followed by instructions
456 which write to the HI and LO registers.
458 According to MIPS specifications, MIPS ISAs I, II, and III need
459 (at least) two instructions between the reads of HI/LO and
460 instructions which write them, and later ISAs do not. Contradicting
461 the MIPS specifications, some MIPS IV processor user manuals (e.g.
462 the UM for the NEC Vr5000) document needing the instructions between
463 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
464 MIPS64 and later ISAs to have the interlocks, plus any specific
465 earlier-ISA CPUs for which CPU documentation declares that the
466 instructions are really interlocked. */
467 #define hilo_interlocks \
468 (mips_opts.isa == ISA_MIPS32 \
469 || mips_opts.isa == ISA_MIPS32R2 \
470 || mips_opts.isa == ISA_MIPS64 \
471 || mips_opts.isa == ISA_MIPS64R2 \
472 || mips_opts.arch == CPU_R4010 \
473 || mips_opts.arch == CPU_R10000 \
474 || mips_opts.arch == CPU_R12000 \
475 || mips_opts.arch == CPU_R14000 \
476 || mips_opts.arch == CPU_R16000 \
477 || mips_opts.arch == CPU_RM7000 \
478 || mips_opts.arch == CPU_VR5500 \
481 /* Whether the processor uses hardware interlocks to protect reads
482 from the GPRs after they are loaded from memory, and thus does not
483 require nops to be inserted. This applies to instructions marked
484 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
486 #define gpr_interlocks \
487 (mips_opts.isa != ISA_MIPS1 \
488 || mips_opts.arch == CPU_R3900)
490 /* Whether the processor uses hardware interlocks to avoid delays
491 required by coprocessor instructions, and thus does not require
492 nops to be inserted. This applies to instructions marked
493 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
494 between instructions marked INSN_WRITE_COND_CODE and ones marked
495 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
496 levels I, II, and III. */
497 /* Itbl support may require additional care here. */
498 #define cop_interlocks \
499 ((mips_opts.isa != ISA_MIPS1 \
500 && mips_opts.isa != ISA_MIPS2 \
501 && mips_opts.isa != ISA_MIPS3) \
502 || mips_opts.arch == CPU_R4300 \
505 /* Whether the processor uses hardware interlocks to protect reads
506 from coprocessor registers after they are loaded from memory, and
507 thus does not require nops to be inserted. This applies to
508 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
509 requires at MIPS ISA level I. */
510 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
512 /* Is this a mfhi or mflo instruction? */
513 #define MF_HILO_INSN(PINFO) \
514 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
516 /* Returns true for a (non floating-point) coprocessor instruction. Reading
517 or writing the condition code is only possible on the coprocessors and
518 these insns are not marked with INSN_COP. Thus for these insns use the
519 condition-code flags. */
520 #define COP_INSN(PINFO) \
521 (PINFO != INSN_MACRO \
522 && ((PINFO) & (FP_S | FP_D)) == 0 \
523 && ((PINFO) & (INSN_COP | INSN_READ_COND_CODE | INSN_WRITE_COND_CODE)))
525 /* MIPS PIC level. */
527 enum mips_pic_level mips_pic
;
529 /* 1 if we should generate 32 bit offsets from the $gp register in
530 SVR4_PIC mode. Currently has no meaning in other modes. */
531 static int mips_big_got
= 0;
533 /* 1 if trap instructions should used for overflow rather than break
535 static int mips_trap
= 0;
537 /* 1 if double width floating point constants should not be constructed
538 by assembling two single width halves into two single width floating
539 point registers which just happen to alias the double width destination
540 register. On some architectures this aliasing can be disabled by a bit
541 in the status register, and the setting of this bit cannot be determined
542 automatically at assemble time. */
543 static int mips_disable_float_construction
;
545 /* Non-zero if any .set noreorder directives were used. */
547 static int mips_any_noreorder
;
549 /* Non-zero if nops should be inserted when the register referenced in
550 an mfhi/mflo instruction is read in the next two instructions. */
551 static int mips_7000_hilo_fix
;
553 /* The size of objects in the small data section. */
554 static unsigned int g_switch_value
= 8;
555 /* Whether the -G option was used. */
556 static int g_switch_seen
= 0;
561 /* If we can determine in advance that GP optimization won't be
562 possible, we can skip the relaxation stuff that tries to produce
563 GP-relative references. This makes delay slot optimization work
566 This function can only provide a guess, but it seems to work for
567 gcc output. It needs to guess right for gcc, otherwise gcc
568 will put what it thinks is a GP-relative instruction in a branch
571 I don't know if a fix is needed for the SVR4_PIC mode. I've only
572 fixed it for the non-PIC mode. KR 95/04/07 */
573 static int nopic_need_relax (symbolS
*, int);
575 /* handle of the OPCODE hash table */
576 static struct hash_control
*op_hash
= NULL
;
578 /* The opcode hash table we use for the mips16. */
579 static struct hash_control
*mips16_op_hash
= NULL
;
581 /* This array holds the chars that always start a comment. If the
582 pre-processor is disabled, these aren't very useful */
583 const char comment_chars
[] = "#";
585 /* This array holds the chars that only start a comment at the beginning of
586 a line. If the line seems to have the form '# 123 filename'
587 .line and .file directives will appear in the pre-processed output */
588 /* Note that input_file.c hand checks for '#' at the beginning of the
589 first line of the input file. This is because the compiler outputs
590 #NO_APP at the beginning of its output. */
591 /* Also note that C style comments are always supported. */
592 const char line_comment_chars
[] = "#";
594 /* This array holds machine specific line separator characters. */
595 const char line_separator_chars
[] = ";";
597 /* Chars that can be used to separate mant from exp in floating point nums */
598 const char EXP_CHARS
[] = "eE";
600 /* Chars that mean this number is a floating point constant */
603 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
605 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
606 changed in read.c . Ideally it shouldn't have to know about it at all,
607 but nothing is ideal around here.
610 static char *insn_error
;
612 static int auto_align
= 1;
614 /* When outputting SVR4 PIC code, the assembler needs to know the
615 offset in the stack frame from which to restore the $gp register.
616 This is set by the .cprestore pseudo-op, and saved in this
618 static offsetT mips_cprestore_offset
= -1;
620 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
621 more optimizations, it can use a register value instead of a memory-saved
622 offset and even an other register than $gp as global pointer. */
623 static offsetT mips_cpreturn_offset
= -1;
624 static int mips_cpreturn_register
= -1;
625 static int mips_gp_register
= GP
;
626 static int mips_gprel_offset
= 0;
628 /* Whether mips_cprestore_offset has been set in the current function
629 (or whether it has already been warned about, if not). */
630 static int mips_cprestore_valid
= 0;
632 /* This is the register which holds the stack frame, as set by the
633 .frame pseudo-op. This is needed to implement .cprestore. */
634 static int mips_frame_reg
= SP
;
636 /* Whether mips_frame_reg has been set in the current function
637 (or whether it has already been warned about, if not). */
638 static int mips_frame_reg_valid
= 0;
640 /* To output NOP instructions correctly, we need to keep information
641 about the previous two instructions. */
643 /* Whether we are optimizing. The default value of 2 means to remove
644 unneeded NOPs and swap branch instructions when possible. A value
645 of 1 means to not swap branches. A value of 0 means to always
647 static int mips_optimize
= 2;
649 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
650 equivalent to seeing no -g option at all. */
651 static int mips_debug
= 0;
653 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
654 #define MAX_VR4130_NOPS 4
656 /* The maximum number of NOPs needed to fill delay slots. */
657 #define MAX_DELAY_NOPS 2
659 /* The maximum number of NOPs needed for any purpose. */
662 /* A list of previous instructions, with index 0 being the most recent.
663 We need to look back MAX_NOPS instructions when filling delay slots
664 or working around processor errata. We need to look back one
665 instruction further if we're thinking about using history[0] to
666 fill a branch delay slot. */
667 static struct mips_cl_insn history
[1 + MAX_NOPS
];
669 /* Nop instructions used by emit_nop. */
670 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
672 /* The appropriate nop for the current mode. */
673 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
675 /* If this is set, it points to a frag holding nop instructions which
676 were inserted before the start of a noreorder section. If those
677 nops turn out to be unnecessary, the size of the frag can be
679 static fragS
*prev_nop_frag
;
681 /* The number of nop instructions we created in prev_nop_frag. */
682 static int prev_nop_frag_holds
;
684 /* The number of nop instructions that we know we need in
686 static int prev_nop_frag_required
;
688 /* The number of instructions we've seen since prev_nop_frag. */
689 static int prev_nop_frag_since
;
691 /* For ECOFF and ELF, relocations against symbols are done in two
692 parts, with a HI relocation and a LO relocation. Each relocation
693 has only 16 bits of space to store an addend. This means that in
694 order for the linker to handle carries correctly, it must be able
695 to locate both the HI and the LO relocation. This means that the
696 relocations must appear in order in the relocation table.
698 In order to implement this, we keep track of each unmatched HI
699 relocation. We then sort them so that they immediately precede the
700 corresponding LO relocation. */
705 struct mips_hi_fixup
*next
;
708 /* The section this fixup is in. */
712 /* The list of unmatched HI relocs. */
714 static struct mips_hi_fixup
*mips_hi_fixup_list
;
716 /* The frag containing the last explicit relocation operator.
717 Null if explicit relocations have not been used. */
719 static fragS
*prev_reloc_op_frag
;
721 /* Map normal MIPS register numbers to mips16 register numbers. */
723 #define X ILLEGAL_REG
724 static const int mips32_to_16_reg_map
[] =
726 X
, X
, 2, 3, 4, 5, 6, 7,
727 X
, X
, X
, X
, X
, X
, X
, X
,
728 0, 1, X
, X
, X
, X
, X
, X
,
729 X
, X
, X
, X
, X
, X
, X
, X
733 /* Map mips16 register numbers to normal MIPS register numbers. */
735 static const unsigned int mips16_to_32_reg_map
[] =
737 16, 17, 2, 3, 4, 5, 6, 7
740 /* Classifies the kind of instructions we're interested in when
741 implementing -mfix-vr4120. */
742 enum fix_vr4120_class
{
749 NUM_FIX_VR4120_CLASSES
752 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
753 there must be at least one other instruction between an instruction
754 of type X and an instruction of type Y. */
755 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
757 /* True if -mfix-vr4120 is in force. */
758 static int mips_fix_vr4120
;
760 /* ...likewise -mfix-vr4130. */
761 static int mips_fix_vr4130
;
763 /* We don't relax branches by default, since this causes us to expand
764 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
765 fail to compute the offset before expanding the macro to the most
766 efficient expansion. */
768 static int mips_relax_branch
;
770 /* The expansion of many macros depends on the type of symbol that
771 they refer to. For example, when generating position-dependent code,
772 a macro that refers to a symbol may have two different expansions,
773 one which uses GP-relative addresses and one which uses absolute
774 addresses. When generating SVR4-style PIC, a macro may have
775 different expansions for local and global symbols.
777 We handle these situations by generating both sequences and putting
778 them in variant frags. In position-dependent code, the first sequence
779 will be the GP-relative one and the second sequence will be the
780 absolute one. In SVR4 PIC, the first sequence will be for global
781 symbols and the second will be for local symbols.
783 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
784 SECOND are the lengths of the two sequences in bytes. These fields
785 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
786 the subtype has the following flags:
789 Set if it has been decided that we should use the second
790 sequence instead of the first.
793 Set in the first variant frag if the macro's second implementation
794 is longer than its first. This refers to the macro as a whole,
795 not an individual relaxation.
798 Set in the first variant frag if the macro appeared in a .set nomacro
799 block and if one alternative requires a warning but the other does not.
802 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
805 The frag's "opcode" points to the first fixup for relaxable code.
807 Relaxable macros are generated using a sequence such as:
809 relax_start (SYMBOL);
810 ... generate first expansion ...
812 ... generate second expansion ...
815 The code and fixups for the unwanted alternative are discarded
816 by md_convert_frag. */
817 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
819 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
820 #define RELAX_SECOND(X) ((X) & 0xff)
821 #define RELAX_USE_SECOND 0x10000
822 #define RELAX_SECOND_LONGER 0x20000
823 #define RELAX_NOMACRO 0x40000
824 #define RELAX_DELAY_SLOT 0x80000
826 /* Branch without likely bit. If label is out of range, we turn:
828 beq reg1, reg2, label
838 with the following opcode replacements:
845 bltzal <-> bgezal (with jal label instead of j label)
847 Even though keeping the delay slot instruction in the delay slot of
848 the branch would be more efficient, it would be very tricky to do
849 correctly, because we'd have to introduce a variable frag *after*
850 the delay slot instruction, and expand that instead. Let's do it
851 the easy way for now, even if the branch-not-taken case now costs
852 one additional instruction. Out-of-range branches are not supposed
853 to be common, anyway.
855 Branch likely. If label is out of range, we turn:
857 beql reg1, reg2, label
858 delay slot (annulled if branch not taken)
867 delay slot (executed only if branch taken)
870 It would be possible to generate a shorter sequence by losing the
871 likely bit, generating something like:
876 delay slot (executed only if branch taken)
888 bltzall -> bgezal (with jal label instead of j label)
889 bgezall -> bltzal (ditto)
892 but it's not clear that it would actually improve performance. */
893 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
896 | ((toofar) ? 1 : 0) \
898 | ((likely) ? 4 : 0) \
899 | ((uncond) ? 8 : 0)))
900 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
901 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
902 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
903 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
904 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
906 /* For mips16 code, we use an entirely different form of relaxation.
907 mips16 supports two versions of most instructions which take
908 immediate values: a small one which takes some small value, and a
909 larger one which takes a 16 bit value. Since branches also follow
910 this pattern, relaxing these values is required.
912 We can assemble both mips16 and normal MIPS code in a single
913 object. Therefore, we need to support this type of relaxation at
914 the same time that we support the relaxation described above. We
915 use the high bit of the subtype field to distinguish these cases.
917 The information we store for this type of relaxation is the
918 argument code found in the opcode file for this relocation, whether
919 the user explicitly requested a small or extended form, and whether
920 the relocation is in a jump or jal delay slot. That tells us the
921 size of the value, and how it should be stored. We also store
922 whether the fragment is considered to be extended or not. We also
923 store whether this is known to be a branch to a different section,
924 whether we have tried to relax this frag yet, and whether we have
925 ever extended a PC relative fragment because of a shift count. */
926 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
929 | ((small) ? 0x100 : 0) \
930 | ((ext) ? 0x200 : 0) \
931 | ((dslot) ? 0x400 : 0) \
932 | ((jal_dslot) ? 0x800 : 0))
933 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
934 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
935 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
936 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
937 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
938 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
939 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
940 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
941 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
942 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
943 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
944 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
946 /* Is the given value a sign-extended 32-bit value? */
947 #define IS_SEXT_32BIT_NUM(x) \
948 (((x) &~ (offsetT) 0x7fffffff) == 0 \
949 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
951 /* Is the given value a sign-extended 16-bit value? */
952 #define IS_SEXT_16BIT_NUM(x) \
953 (((x) &~ (offsetT) 0x7fff) == 0 \
954 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
956 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
957 #define IS_ZEXT_32BIT_NUM(x) \
958 (((x) &~ (offsetT) 0xffffffff) == 0 \
959 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
961 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
962 VALUE << SHIFT. VALUE is evaluated exactly once. */
963 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
964 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
965 | (((VALUE) & (MASK)) << (SHIFT)))
967 /* Extract bits MASK << SHIFT from STRUCT and shift them right
969 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
970 (((STRUCT) >> (SHIFT)) & (MASK))
972 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
973 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
975 include/opcode/mips.h specifies operand fields using the macros
976 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
977 with "MIPS16OP" instead of "OP". */
978 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
979 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
980 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
981 INSERT_BITS ((INSN).insn_opcode, VALUE, \
982 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
984 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
985 #define EXTRACT_OPERAND(FIELD, INSN) \
986 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
987 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
988 EXTRACT_BITS ((INSN).insn_opcode, \
989 MIPS16OP_MASK_##FIELD, \
992 /* Global variables used when generating relaxable macros. See the
993 comment above RELAX_ENCODE for more details about how relaxation
996 /* 0 if we're not emitting a relaxable macro.
997 1 if we're emitting the first of the two relaxation alternatives.
998 2 if we're emitting the second alternative. */
1001 /* The first relaxable fixup in the current frag. (In other words,
1002 the first fixup that refers to relaxable code.) */
1005 /* sizes[0] says how many bytes of the first alternative are stored in
1006 the current frag. Likewise sizes[1] for the second alternative. */
1007 unsigned int sizes
[2];
1009 /* The symbol on which the choice of sequence depends. */
1013 /* Global variables used to decide whether a macro needs a warning. */
1015 /* True if the macro is in a branch delay slot. */
1016 bfd_boolean delay_slot_p
;
1018 /* For relaxable macros, sizes[0] is the length of the first alternative
1019 in bytes and sizes[1] is the length of the second alternative.
1020 For non-relaxable macros, both elements give the length of the
1022 unsigned int sizes
[2];
1024 /* The first variant frag for this macro. */
1026 } mips_macro_warning
;
1028 /* Prototypes for static functions. */
1030 #define internalError() \
1031 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
1033 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1035 static void append_insn
1036 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
1037 static void mips_no_prev_insn (void);
1038 static void mips16_macro_build
1039 (expressionS
*, const char *, const char *, va_list);
1040 static void load_register (int, expressionS
*, int);
1041 static void macro_start (void);
1042 static void macro_end (void);
1043 static void macro (struct mips_cl_insn
* ip
);
1044 static void mips16_macro (struct mips_cl_insn
* ip
);
1045 #ifdef LOSING_COMPILER
1046 static void macro2 (struct mips_cl_insn
* ip
);
1048 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1049 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1050 static void mips16_immed
1051 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
1052 unsigned long *, bfd_boolean
*, unsigned short *);
1053 static size_t my_getSmallExpression
1054 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1055 static void my_getExpression (expressionS
*, char *);
1056 static void s_align (int);
1057 static void s_change_sec (int);
1058 static void s_change_section (int);
1059 static void s_cons (int);
1060 static void s_float_cons (int);
1061 static void s_mips_globl (int);
1062 static void s_option (int);
1063 static void s_mipsset (int);
1064 static void s_abicalls (int);
1065 static void s_cpload (int);
1066 static void s_cpsetup (int);
1067 static void s_cplocal (int);
1068 static void s_cprestore (int);
1069 static void s_cpreturn (int);
1070 static void s_dtprelword (int);
1071 static void s_dtpreldword (int);
1072 static void s_gpvalue (int);
1073 static void s_gpword (int);
1074 static void s_gpdword (int);
1075 static void s_cpadd (int);
1076 static void s_insn (int);
1077 static void md_obj_begin (void);
1078 static void md_obj_end (void);
1079 static void s_mips_ent (int);
1080 static void s_mips_end (int);
1081 static void s_mips_frame (int);
1082 static void s_mips_mask (int reg_type
);
1083 static void s_mips_stab (int);
1084 static void s_mips_weakext (int);
1085 static void s_mips_file (int);
1086 static void s_mips_loc (int);
1087 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1088 static int relaxed_branch_length (fragS
*, asection
*, int);
1089 static int validate_mips_insn (const struct mips_opcode
*);
1091 /* Table and functions used to map between CPU/ISA names, and
1092 ISA levels, and CPU numbers. */
1094 struct mips_cpu_info
1096 const char *name
; /* CPU or ISA name. */
1097 int flags
; /* ASEs available, or ISA flag. */
1098 int isa
; /* ISA level. */
1099 int cpu
; /* CPU number (default CPU if ISA). */
1102 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1103 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1104 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1105 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1106 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1107 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1108 #define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1110 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1111 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1112 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1116 The following pseudo-ops from the Kane and Heinrich MIPS book
1117 should be defined here, but are currently unsupported: .alias,
1118 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1120 The following pseudo-ops from the Kane and Heinrich MIPS book are
1121 specific to the type of debugging information being generated, and
1122 should be defined by the object format: .aent, .begin, .bend,
1123 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1126 The following pseudo-ops from the Kane and Heinrich MIPS book are
1127 not MIPS CPU specific, but are also not specific to the object file
1128 format. This file is probably the best place to define them, but
1129 they are not currently supported: .asm0, .endr, .lab, .struct. */
1131 static const pseudo_typeS mips_pseudo_table
[] =
1133 /* MIPS specific pseudo-ops. */
1134 {"option", s_option
, 0},
1135 {"set", s_mipsset
, 0},
1136 {"rdata", s_change_sec
, 'r'},
1137 {"sdata", s_change_sec
, 's'},
1138 {"livereg", s_ignore
, 0},
1139 {"abicalls", s_abicalls
, 0},
1140 {"cpload", s_cpload
, 0},
1141 {"cpsetup", s_cpsetup
, 0},
1142 {"cplocal", s_cplocal
, 0},
1143 {"cprestore", s_cprestore
, 0},
1144 {"cpreturn", s_cpreturn
, 0},
1145 {"dtprelword", s_dtprelword
, 0},
1146 {"dtpreldword", s_dtpreldword
, 0},
1147 {"gpvalue", s_gpvalue
, 0},
1148 {"gpword", s_gpword
, 0},
1149 {"gpdword", s_gpdword
, 0},
1150 {"cpadd", s_cpadd
, 0},
1151 {"insn", s_insn
, 0},
1153 /* Relatively generic pseudo-ops that happen to be used on MIPS
1155 {"asciiz", stringer
, 8 + 1},
1156 {"bss", s_change_sec
, 'b'},
1158 {"half", s_cons
, 1},
1159 {"dword", s_cons
, 3},
1160 {"weakext", s_mips_weakext
, 0},
1161 {"origin", s_org
, 0},
1162 {"repeat", s_rept
, 0},
1164 /* These pseudo-ops are defined in read.c, but must be overridden
1165 here for one reason or another. */
1166 {"align", s_align
, 0},
1167 {"byte", s_cons
, 0},
1168 {"data", s_change_sec
, 'd'},
1169 {"double", s_float_cons
, 'd'},
1170 {"float", s_float_cons
, 'f'},
1171 {"globl", s_mips_globl
, 0},
1172 {"global", s_mips_globl
, 0},
1173 {"hword", s_cons
, 1},
1175 {"long", s_cons
, 2},
1176 {"octa", s_cons
, 4},
1177 {"quad", s_cons
, 3},
1178 {"section", s_change_section
, 0},
1179 {"short", s_cons
, 1},
1180 {"single", s_float_cons
, 'f'},
1181 {"stabn", s_mips_stab
, 'n'},
1182 {"text", s_change_sec
, 't'},
1183 {"word", s_cons
, 2},
1185 { "extern", ecoff_directive_extern
, 0},
1190 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1192 /* These pseudo-ops should be defined by the object file format.
1193 However, a.out doesn't support them, so we have versions here. */
1194 {"aent", s_mips_ent
, 1},
1195 {"bgnb", s_ignore
, 0},
1196 {"end", s_mips_end
, 0},
1197 {"endb", s_ignore
, 0},
1198 {"ent", s_mips_ent
, 0},
1199 {"file", s_mips_file
, 0},
1200 {"fmask", s_mips_mask
, 'F'},
1201 {"frame", s_mips_frame
, 0},
1202 {"loc", s_mips_loc
, 0},
1203 {"mask", s_mips_mask
, 'R'},
1204 {"verstamp", s_ignore
, 0},
1208 extern void pop_insert (const pseudo_typeS
*);
1211 mips_pop_insert (void)
1213 pop_insert (mips_pseudo_table
);
1214 if (! ECOFF_DEBUGGING
)
1215 pop_insert (mips_nonecoff_pseudo_table
);
1218 /* Symbols labelling the current insn. */
1220 struct insn_label_list
1222 struct insn_label_list
*next
;
1226 static struct insn_label_list
*free_insn_labels
;
1227 #define label_list tc_segment_info_data.labels
1229 static void mips_clear_insn_labels (void);
1232 mips_clear_insn_labels (void)
1234 register struct insn_label_list
**pl
;
1235 segment_info_type
*si
;
1239 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1242 si
= seg_info (now_seg
);
1243 *pl
= si
->label_list
;
1244 si
->label_list
= NULL
;
1249 static char *expr_end
;
1251 /* Expressions which appear in instructions. These are set by
1254 static expressionS imm_expr
;
1255 static expressionS imm2_expr
;
1256 static expressionS offset_expr
;
1258 /* Relocs associated with imm_expr and offset_expr. */
1260 static bfd_reloc_code_real_type imm_reloc
[3]
1261 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1262 static bfd_reloc_code_real_type offset_reloc
[3]
1263 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1265 /* These are set by mips16_ip if an explicit extension is used. */
1267 static bfd_boolean mips16_small
, mips16_ext
;
1270 /* The pdr segment for per procedure frame/regmask info. Not used for
1273 static segT pdr_seg
;
1276 /* The default target format to use. */
1279 mips_target_format (void)
1281 switch (OUTPUT_FLAVOR
)
1283 case bfd_target_ecoff_flavour
:
1284 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1285 case bfd_target_coff_flavour
:
1287 case bfd_target_elf_flavour
:
1289 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1290 return (target_big_endian
1291 ? "elf32-bigmips-vxworks"
1292 : "elf32-littlemips-vxworks");
1295 /* This is traditional mips. */
1296 return (target_big_endian
1297 ? (HAVE_64BIT_OBJECTS
1298 ? "elf64-tradbigmips"
1300 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1301 : (HAVE_64BIT_OBJECTS
1302 ? "elf64-tradlittlemips"
1304 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1306 return (target_big_endian
1307 ? (HAVE_64BIT_OBJECTS
1310 ? "elf32-nbigmips" : "elf32-bigmips"))
1311 : (HAVE_64BIT_OBJECTS
1312 ? "elf64-littlemips"
1314 ? "elf32-nlittlemips" : "elf32-littlemips")));
1322 /* Return the length of instruction INSN. */
1324 static inline unsigned int
1325 insn_length (const struct mips_cl_insn
*insn
)
1327 if (!mips_opts
.mips16
)
1329 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1332 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1335 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1340 insn
->use_extend
= FALSE
;
1342 insn
->insn_opcode
= mo
->match
;
1345 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1346 insn
->fixp
[i
] = NULL
;
1347 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1348 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1349 insn
->mips16_absolute_jump_p
= 0;
1352 /* Record the current MIPS16 mode in now_seg. */
1355 mips_record_mips16_mode (void)
1357 segment_info_type
*si
;
1359 si
= seg_info (now_seg
);
1360 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
1361 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
1364 /* Install INSN at the location specified by its "frag" and "where" fields. */
1367 install_insn (const struct mips_cl_insn
*insn
)
1369 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1370 if (!mips_opts
.mips16
)
1371 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1372 else if (insn
->mips16_absolute_jump_p
)
1374 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1375 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1379 if (insn
->use_extend
)
1381 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1384 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1386 mips_record_mips16_mode ();
1389 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1390 and install the opcode in the new location. */
1393 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1398 insn
->where
= where
;
1399 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1400 if (insn
->fixp
[i
] != NULL
)
1402 insn
->fixp
[i
]->fx_frag
= frag
;
1403 insn
->fixp
[i
]->fx_where
= where
;
1405 install_insn (insn
);
1408 /* Add INSN to the end of the output. */
1411 add_fixed_insn (struct mips_cl_insn
*insn
)
1413 char *f
= frag_more (insn_length (insn
));
1414 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1417 /* Start a variant frag and move INSN to the start of the variant part,
1418 marking it as fixed. The other arguments are as for frag_var. */
1421 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1422 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1424 frag_grow (max_chars
);
1425 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1427 frag_var (rs_machine_dependent
, max_chars
, var
,
1428 subtype
, symbol
, offset
, NULL
);
1431 /* Insert N copies of INSN into the history buffer, starting at
1432 position FIRST. Neither FIRST nor N need to be clipped. */
1435 insert_into_history (unsigned int first
, unsigned int n
,
1436 const struct mips_cl_insn
*insn
)
1438 if (mips_relax
.sequence
!= 2)
1442 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1444 history
[i
] = history
[i
- n
];
1450 /* Emit a nop instruction, recording it in the history buffer. */
1455 add_fixed_insn (NOP_INSN
);
1456 insert_into_history (0, 1, NOP_INSN
);
1459 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1460 the idea is to make it obvious at a glance that each errata is
1464 init_vr4120_conflicts (void)
1466 #define CONFLICT(FIRST, SECOND) \
1467 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1469 /* Errata 21 - [D]DIV[U] after [D]MACC */
1470 CONFLICT (MACC
, DIV
);
1471 CONFLICT (DMACC
, DIV
);
1473 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1474 CONFLICT (DMULT
, DMULT
);
1475 CONFLICT (DMULT
, DMACC
);
1476 CONFLICT (DMACC
, DMULT
);
1477 CONFLICT (DMACC
, DMACC
);
1479 /* Errata 24 - MT{LO,HI} after [D]MACC */
1480 CONFLICT (MACC
, MTHILO
);
1481 CONFLICT (DMACC
, MTHILO
);
1483 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1484 instruction is executed immediately after a MACC or DMACC
1485 instruction, the result of [either instruction] is incorrect." */
1486 CONFLICT (MACC
, MULT
);
1487 CONFLICT (MACC
, DMULT
);
1488 CONFLICT (DMACC
, MULT
);
1489 CONFLICT (DMACC
, DMULT
);
1491 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1492 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1493 DDIV or DDIVU instruction, the result of the MACC or
1494 DMACC instruction is incorrect.". */
1495 CONFLICT (DMULT
, MACC
);
1496 CONFLICT (DMULT
, DMACC
);
1497 CONFLICT (DIV
, MACC
);
1498 CONFLICT (DIV
, DMACC
);
1508 #define RTYPE_MASK 0x1ff00
1509 #define RTYPE_NUM 0x00100
1510 #define RTYPE_FPU 0x00200
1511 #define RTYPE_FCC 0x00400
1512 #define RTYPE_VEC 0x00800
1513 #define RTYPE_GP 0x01000
1514 #define RTYPE_CP0 0x02000
1515 #define RTYPE_PC 0x04000
1516 #define RTYPE_ACC 0x08000
1517 #define RTYPE_CCC 0x10000
1518 #define RNUM_MASK 0x000ff
1519 #define RWARN 0x80000
1521 #define GENERIC_REGISTER_NUMBERS \
1522 {"$0", RTYPE_NUM | 0}, \
1523 {"$1", RTYPE_NUM | 1}, \
1524 {"$2", RTYPE_NUM | 2}, \
1525 {"$3", RTYPE_NUM | 3}, \
1526 {"$4", RTYPE_NUM | 4}, \
1527 {"$5", RTYPE_NUM | 5}, \
1528 {"$6", RTYPE_NUM | 6}, \
1529 {"$7", RTYPE_NUM | 7}, \
1530 {"$8", RTYPE_NUM | 8}, \
1531 {"$9", RTYPE_NUM | 9}, \
1532 {"$10", RTYPE_NUM | 10}, \
1533 {"$11", RTYPE_NUM | 11}, \
1534 {"$12", RTYPE_NUM | 12}, \
1535 {"$13", RTYPE_NUM | 13}, \
1536 {"$14", RTYPE_NUM | 14}, \
1537 {"$15", RTYPE_NUM | 15}, \
1538 {"$16", RTYPE_NUM | 16}, \
1539 {"$17", RTYPE_NUM | 17}, \
1540 {"$18", RTYPE_NUM | 18}, \
1541 {"$19", RTYPE_NUM | 19}, \
1542 {"$20", RTYPE_NUM | 20}, \
1543 {"$21", RTYPE_NUM | 21}, \
1544 {"$22", RTYPE_NUM | 22}, \
1545 {"$23", RTYPE_NUM | 23}, \
1546 {"$24", RTYPE_NUM | 24}, \
1547 {"$25", RTYPE_NUM | 25}, \
1548 {"$26", RTYPE_NUM | 26}, \
1549 {"$27", RTYPE_NUM | 27}, \
1550 {"$28", RTYPE_NUM | 28}, \
1551 {"$29", RTYPE_NUM | 29}, \
1552 {"$30", RTYPE_NUM | 30}, \
1553 {"$31", RTYPE_NUM | 31}
1555 #define FPU_REGISTER_NAMES \
1556 {"$f0", RTYPE_FPU | 0}, \
1557 {"$f1", RTYPE_FPU | 1}, \
1558 {"$f2", RTYPE_FPU | 2}, \
1559 {"$f3", RTYPE_FPU | 3}, \
1560 {"$f4", RTYPE_FPU | 4}, \
1561 {"$f5", RTYPE_FPU | 5}, \
1562 {"$f6", RTYPE_FPU | 6}, \
1563 {"$f7", RTYPE_FPU | 7}, \
1564 {"$f8", RTYPE_FPU | 8}, \
1565 {"$f9", RTYPE_FPU | 9}, \
1566 {"$f10", RTYPE_FPU | 10}, \
1567 {"$f11", RTYPE_FPU | 11}, \
1568 {"$f12", RTYPE_FPU | 12}, \
1569 {"$f13", RTYPE_FPU | 13}, \
1570 {"$f14", RTYPE_FPU | 14}, \
1571 {"$f15", RTYPE_FPU | 15}, \
1572 {"$f16", RTYPE_FPU | 16}, \
1573 {"$f17", RTYPE_FPU | 17}, \
1574 {"$f18", RTYPE_FPU | 18}, \
1575 {"$f19", RTYPE_FPU | 19}, \
1576 {"$f20", RTYPE_FPU | 20}, \
1577 {"$f21", RTYPE_FPU | 21}, \
1578 {"$f22", RTYPE_FPU | 22}, \
1579 {"$f23", RTYPE_FPU | 23}, \
1580 {"$f24", RTYPE_FPU | 24}, \
1581 {"$f25", RTYPE_FPU | 25}, \
1582 {"$f26", RTYPE_FPU | 26}, \
1583 {"$f27", RTYPE_FPU | 27}, \
1584 {"$f28", RTYPE_FPU | 28}, \
1585 {"$f29", RTYPE_FPU | 29}, \
1586 {"$f30", RTYPE_FPU | 30}, \
1587 {"$f31", RTYPE_FPU | 31}
1589 #define FPU_CONDITION_CODE_NAMES \
1590 {"$fcc0", RTYPE_FCC | 0}, \
1591 {"$fcc1", RTYPE_FCC | 1}, \
1592 {"$fcc2", RTYPE_FCC | 2}, \
1593 {"$fcc3", RTYPE_FCC | 3}, \
1594 {"$fcc4", RTYPE_FCC | 4}, \
1595 {"$fcc5", RTYPE_FCC | 5}, \
1596 {"$fcc6", RTYPE_FCC | 6}, \
1597 {"$fcc7", RTYPE_FCC | 7}
1599 #define COPROC_CONDITION_CODE_NAMES \
1600 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1601 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1602 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1603 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1604 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1605 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1606 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1607 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1609 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1610 {"$a4", RTYPE_GP | 8}, \
1611 {"$a5", RTYPE_GP | 9}, \
1612 {"$a6", RTYPE_GP | 10}, \
1613 {"$a7", RTYPE_GP | 11}, \
1614 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1615 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1616 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1617 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1618 {"$t0", RTYPE_GP | 12}, \
1619 {"$t1", RTYPE_GP | 13}, \
1620 {"$t2", RTYPE_GP | 14}, \
1621 {"$t3", RTYPE_GP | 15}
1623 #define O32_SYMBOLIC_REGISTER_NAMES \
1624 {"$t0", RTYPE_GP | 8}, \
1625 {"$t1", RTYPE_GP | 9}, \
1626 {"$t2", RTYPE_GP | 10}, \
1627 {"$t3", RTYPE_GP | 11}, \
1628 {"$t4", RTYPE_GP | 12}, \
1629 {"$t5", RTYPE_GP | 13}, \
1630 {"$t6", RTYPE_GP | 14}, \
1631 {"$t7", RTYPE_GP | 15}, \
1632 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1633 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1634 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1635 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1637 /* Remaining symbolic register names */
1638 #define SYMBOLIC_REGISTER_NAMES \
1639 {"$zero", RTYPE_GP | 0}, \
1640 {"$at", RTYPE_GP | 1}, \
1641 {"$AT", RTYPE_GP | 1}, \
1642 {"$v0", RTYPE_GP | 2}, \
1643 {"$v1", RTYPE_GP | 3}, \
1644 {"$a0", RTYPE_GP | 4}, \
1645 {"$a1", RTYPE_GP | 5}, \
1646 {"$a2", RTYPE_GP | 6}, \
1647 {"$a3", RTYPE_GP | 7}, \
1648 {"$s0", RTYPE_GP | 16}, \
1649 {"$s1", RTYPE_GP | 17}, \
1650 {"$s2", RTYPE_GP | 18}, \
1651 {"$s3", RTYPE_GP | 19}, \
1652 {"$s4", RTYPE_GP | 20}, \
1653 {"$s5", RTYPE_GP | 21}, \
1654 {"$s6", RTYPE_GP | 22}, \
1655 {"$s7", RTYPE_GP | 23}, \
1656 {"$t8", RTYPE_GP | 24}, \
1657 {"$t9", RTYPE_GP | 25}, \
1658 {"$k0", RTYPE_GP | 26}, \
1659 {"$kt0", RTYPE_GP | 26}, \
1660 {"$k1", RTYPE_GP | 27}, \
1661 {"$kt1", RTYPE_GP | 27}, \
1662 {"$gp", RTYPE_GP | 28}, \
1663 {"$sp", RTYPE_GP | 29}, \
1664 {"$s8", RTYPE_GP | 30}, \
1665 {"$fp", RTYPE_GP | 30}, \
1666 {"$ra", RTYPE_GP | 31}
1668 #define MIPS16_SPECIAL_REGISTER_NAMES \
1669 {"$pc", RTYPE_PC | 0}
1671 #define MDMX_VECTOR_REGISTER_NAMES \
1672 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1673 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1674 {"$v2", RTYPE_VEC | 2}, \
1675 {"$v3", RTYPE_VEC | 3}, \
1676 {"$v4", RTYPE_VEC | 4}, \
1677 {"$v5", RTYPE_VEC | 5}, \
1678 {"$v6", RTYPE_VEC | 6}, \
1679 {"$v7", RTYPE_VEC | 7}, \
1680 {"$v8", RTYPE_VEC | 8}, \
1681 {"$v9", RTYPE_VEC | 9}, \
1682 {"$v10", RTYPE_VEC | 10}, \
1683 {"$v11", RTYPE_VEC | 11}, \
1684 {"$v12", RTYPE_VEC | 12}, \
1685 {"$v13", RTYPE_VEC | 13}, \
1686 {"$v14", RTYPE_VEC | 14}, \
1687 {"$v15", RTYPE_VEC | 15}, \
1688 {"$v16", RTYPE_VEC | 16}, \
1689 {"$v17", RTYPE_VEC | 17}, \
1690 {"$v18", RTYPE_VEC | 18}, \
1691 {"$v19", RTYPE_VEC | 19}, \
1692 {"$v20", RTYPE_VEC | 20}, \
1693 {"$v21", RTYPE_VEC | 21}, \
1694 {"$v22", RTYPE_VEC | 22}, \
1695 {"$v23", RTYPE_VEC | 23}, \
1696 {"$v24", RTYPE_VEC | 24}, \
1697 {"$v25", RTYPE_VEC | 25}, \
1698 {"$v26", RTYPE_VEC | 26}, \
1699 {"$v27", RTYPE_VEC | 27}, \
1700 {"$v28", RTYPE_VEC | 28}, \
1701 {"$v29", RTYPE_VEC | 29}, \
1702 {"$v30", RTYPE_VEC | 30}, \
1703 {"$v31", RTYPE_VEC | 31}
1705 #define MIPS_DSP_ACCUMULATOR_NAMES \
1706 {"$ac0", RTYPE_ACC | 0}, \
1707 {"$ac1", RTYPE_ACC | 1}, \
1708 {"$ac2", RTYPE_ACC | 2}, \
1709 {"$ac3", RTYPE_ACC | 3}
1711 static const struct regname reg_names
[] = {
1712 GENERIC_REGISTER_NUMBERS
,
1714 FPU_CONDITION_CODE_NAMES
,
1715 COPROC_CONDITION_CODE_NAMES
,
1717 /* The $txx registers depends on the abi,
1718 these will be added later into the symbol table from
1719 one of the tables below once mips_abi is set after
1720 parsing of arguments from the command line. */
1721 SYMBOLIC_REGISTER_NAMES
,
1723 MIPS16_SPECIAL_REGISTER_NAMES
,
1724 MDMX_VECTOR_REGISTER_NAMES
,
1725 MIPS_DSP_ACCUMULATOR_NAMES
,
1729 static const struct regname reg_names_o32
[] = {
1730 O32_SYMBOLIC_REGISTER_NAMES
,
1734 static const struct regname reg_names_n32n64
[] = {
1735 N32N64_SYMBOLIC_REGISTER_NAMES
,
1740 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1747 /* Find end of name. */
1749 if (is_name_beginner (*e
))
1751 while (is_part_of_name (*e
))
1754 /* Terminate name. */
1758 /* Look for a register symbol. */
1759 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1761 int r
= S_GET_VALUE (symbolP
);
1763 reg
= r
& RNUM_MASK
;
1764 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1765 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1766 reg
= (r
& RNUM_MASK
) - 2;
1768 /* Else see if this is a register defined in an itbl entry. */
1769 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1776 if (itbl_get_reg_val (n
, &r
))
1777 reg
= r
& RNUM_MASK
;
1780 /* Advance to next token if a register was recognised. */
1783 else if (types
& RWARN
)
1784 as_warn ("Unrecognized register name `%s'", *s
);
1792 /* Return TRUE if opcode MO is valid on the currently selected ISA and
1793 architecture. If EXPANSIONP is TRUE then this check is done while
1794 expanding a macro. Use is_opcode_valid_16 for MIPS16 opcodes. */
1797 is_opcode_valid (const struct mips_opcode
*mo
, bfd_boolean expansionp
)
1799 int isa
= mips_opts
.isa
;
1802 if (mips_opts
.ase_mdmx
)
1804 if (mips_opts
.ase_dsp
)
1806 if (mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
1808 if (mips_opts
.ase_dspr2
)
1810 if (mips_opts
.ase_mt
)
1812 if (mips_opts
.ase_mips3d
)
1814 if (mips_opts
.ase_smartmips
)
1815 isa
|= INSN_SMARTMIPS
;
1817 /* For user code we don't check for mips_opts.mips16 since we want
1818 to allow jalx if -mips16 was specified on the command line. */
1819 if (expansionp
? mips_opts
.mips16
: file_ase_mips16
)
1822 /* Don't accept instructions based on the ISA if the CPU does not implement
1823 all the coprocessor insns. */
1824 if (NO_ISA_COP (mips_opts
.arch
)
1825 && COP_INSN (mo
->pinfo
))
1828 if (!OPCODE_IS_MEMBER (mo
, isa
, mips_opts
.arch
))
1831 /* Check whether the instruction or macro requires single-precision or
1832 double-precision floating-point support. Note that this information is
1833 stored differently in the opcode table for insns and macros. */
1834 if (mo
->pinfo
== INSN_MACRO
)
1836 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
1837 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
1841 fp_s
= mo
->pinfo
& FP_S
;
1842 fp_d
= mo
->pinfo
& FP_D
;
1845 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
1848 if (fp_s
&& mips_opts
.soft_float
)
1854 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
1855 selected ISA and architecture. */
1858 is_opcode_valid_16 (const struct mips_opcode
*mo
)
1860 return OPCODE_IS_MEMBER (mo
, mips_opts
.isa
, mips_opts
.arch
) ? TRUE
: FALSE
;
1863 /* This function is called once, at assembler startup time. It should set up
1864 all the tables, etc. that the MD part of the assembler will need. */
1869 const char *retval
= NULL
;
1873 if (mips_pic
!= NO_PIC
)
1875 if (g_switch_seen
&& g_switch_value
!= 0)
1876 as_bad (_("-G may not be used in position-independent code"));
1880 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1881 as_warn (_("Could not set architecture and machine"));
1883 op_hash
= hash_new ();
1885 for (i
= 0; i
< NUMOPCODES
;)
1887 const char *name
= mips_opcodes
[i
].name
;
1889 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1892 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1893 mips_opcodes
[i
].name
, retval
);
1894 /* Probably a memory allocation problem? Give up now. */
1895 as_fatal (_("Broken assembler. No assembly attempted."));
1899 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1901 if (!validate_mips_insn (&mips_opcodes
[i
]))
1903 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1905 create_insn (&nop_insn
, mips_opcodes
+ i
);
1906 nop_insn
.fixed_p
= 1;
1911 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1914 mips16_op_hash
= hash_new ();
1917 while (i
< bfd_mips16_num_opcodes
)
1919 const char *name
= mips16_opcodes
[i
].name
;
1921 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1923 as_fatal (_("internal: can't hash `%s': %s"),
1924 mips16_opcodes
[i
].name
, retval
);
1927 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1928 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1929 != mips16_opcodes
[i
].match
))
1931 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1932 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1935 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1937 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1938 mips16_nop_insn
.fixed_p
= 1;
1942 while (i
< bfd_mips16_num_opcodes
1943 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1947 as_fatal (_("Broken assembler. No assembly attempted."));
1949 /* We add all the general register names to the symbol table. This
1950 helps us detect invalid uses of them. */
1951 for (i
= 0; reg_names
[i
].name
; i
++)
1952 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1953 reg_names
[i
].num
, /* & RNUM_MASK, */
1954 &zero_address_frag
));
1956 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1957 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1958 reg_names_n32n64
[i
].num
, /* & RNUM_MASK, */
1959 &zero_address_frag
));
1961 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1962 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1963 reg_names_o32
[i
].num
, /* & RNUM_MASK, */
1964 &zero_address_frag
));
1966 mips_no_prev_insn ();
1969 mips_cprmask
[0] = 0;
1970 mips_cprmask
[1] = 0;
1971 mips_cprmask
[2] = 0;
1972 mips_cprmask
[3] = 0;
1974 /* set the default alignment for the text section (2**2) */
1975 record_alignment (text_section
, 2);
1977 bfd_set_gp_size (stdoutput
, g_switch_value
);
1982 /* On a native system other than VxWorks, sections must be aligned
1983 to 16 byte boundaries. When configured for an embedded ELF
1984 target, we don't bother. */
1985 if (strncmp (TARGET_OS
, "elf", 3) != 0
1986 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
1988 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1989 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1990 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1993 /* Create a .reginfo section for register masks and a .mdebug
1994 section for debugging information. */
2002 subseg
= now_subseg
;
2004 /* The ABI says this section should be loaded so that the
2005 running program can access it. However, we don't load it
2006 if we are configured for an embedded target */
2007 flags
= SEC_READONLY
| SEC_DATA
;
2008 if (strncmp (TARGET_OS
, "elf", 3) != 0)
2009 flags
|= SEC_ALLOC
| SEC_LOAD
;
2011 if (mips_abi
!= N64_ABI
)
2013 sec
= subseg_new (".reginfo", (subsegT
) 0);
2015 bfd_set_section_flags (stdoutput
, sec
, flags
);
2016 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
2018 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
2022 /* The 64-bit ABI uses a .MIPS.options section rather than
2023 .reginfo section. */
2024 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
2025 bfd_set_section_flags (stdoutput
, sec
, flags
);
2026 bfd_set_section_alignment (stdoutput
, sec
, 3);
2028 /* Set up the option header. */
2030 Elf_Internal_Options opthdr
;
2033 opthdr
.kind
= ODK_REGINFO
;
2034 opthdr
.size
= (sizeof (Elf_External_Options
)
2035 + sizeof (Elf64_External_RegInfo
));
2038 f
= frag_more (sizeof (Elf_External_Options
));
2039 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
2040 (Elf_External_Options
*) f
);
2042 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
2046 if (ECOFF_DEBUGGING
)
2048 sec
= subseg_new (".mdebug", (subsegT
) 0);
2049 (void) bfd_set_section_flags (stdoutput
, sec
,
2050 SEC_HAS_CONTENTS
| SEC_READONLY
);
2051 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
2053 else if (mips_flag_pdr
)
2055 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
2056 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
2057 SEC_READONLY
| SEC_RELOC
2059 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
2062 subseg_set (seg
, subseg
);
2065 #endif /* OBJ_ELF */
2067 if (! ECOFF_DEBUGGING
)
2070 if (mips_fix_vr4120
)
2071 init_vr4120_conflicts ();
2077 if (! ECOFF_DEBUGGING
)
2082 md_assemble (char *str
)
2084 struct mips_cl_insn insn
;
2085 bfd_reloc_code_real_type unused_reloc
[3]
2086 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2088 imm_expr
.X_op
= O_absent
;
2089 imm2_expr
.X_op
= O_absent
;
2090 offset_expr
.X_op
= O_absent
;
2091 imm_reloc
[0] = BFD_RELOC_UNUSED
;
2092 imm_reloc
[1] = BFD_RELOC_UNUSED
;
2093 imm_reloc
[2] = BFD_RELOC_UNUSED
;
2094 offset_reloc
[0] = BFD_RELOC_UNUSED
;
2095 offset_reloc
[1] = BFD_RELOC_UNUSED
;
2096 offset_reloc
[2] = BFD_RELOC_UNUSED
;
2098 if (mips_opts
.mips16
)
2099 mips16_ip (str
, &insn
);
2102 mips_ip (str
, &insn
);
2103 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
2104 str
, insn
.insn_opcode
));
2109 as_bad ("%s `%s'", insn_error
, str
);
2113 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2116 if (mips_opts
.mips16
)
2117 mips16_macro (&insn
);
2124 if (imm_expr
.X_op
!= O_absent
)
2125 append_insn (&insn
, &imm_expr
, imm_reloc
);
2126 else if (offset_expr
.X_op
!= O_absent
)
2127 append_insn (&insn
, &offset_expr
, offset_reloc
);
2129 append_insn (&insn
, NULL
, unused_reloc
);
2133 /* Convenience functions for abstracting away the differences between
2134 MIPS16 and non-MIPS16 relocations. */
2136 static inline bfd_boolean
2137 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
2141 case BFD_RELOC_MIPS16_JMP
:
2142 case BFD_RELOC_MIPS16_GPREL
:
2143 case BFD_RELOC_MIPS16_GOT16
:
2144 case BFD_RELOC_MIPS16_CALL16
:
2145 case BFD_RELOC_MIPS16_HI16_S
:
2146 case BFD_RELOC_MIPS16_HI16
:
2147 case BFD_RELOC_MIPS16_LO16
:
2155 static inline bfd_boolean
2156 got16_reloc_p (bfd_reloc_code_real_type reloc
)
2158 return reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
;
2161 static inline bfd_boolean
2162 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
2164 return reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
;
2167 static inline bfd_boolean
2168 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
2170 return reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
;
2173 /* Return true if the given relocation might need a matching %lo().
2174 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2175 need a matching %lo() when applied to local symbols. */
2177 static inline bfd_boolean
2178 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
2180 return (HAVE_IN_PLACE_ADDENDS
2181 && (hi16_reloc_p (reloc
)
2182 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2183 all GOT16 relocations evaluate to "G". */
2184 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
2187 /* Return the type of %lo() reloc needed by RELOC, given that
2188 reloc_needs_lo_p. */
2190 static inline bfd_reloc_code_real_type
2191 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
2193 return mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
: BFD_RELOC_LO16
;
2196 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2199 static inline bfd_boolean
2200 fixup_has_matching_lo_p (fixS
*fixp
)
2202 return (fixp
->fx_next
!= NULL
2203 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
2204 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2205 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2208 /* See whether instruction IP reads register REG. CLASS is the type
2212 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2213 enum mips_regclass
class)
2215 if (class == MIPS16_REG
)
2217 assert (mips_opts
.mips16
);
2218 reg
= mips16_to_32_reg_map
[reg
];
2219 class = MIPS_GR_REG
;
2222 /* Don't report on general register ZERO, since it never changes. */
2223 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2226 if (class == MIPS_FP_REG
)
2228 assert (! mips_opts
.mips16
);
2229 /* If we are called with either $f0 or $f1, we must check $f0.
2230 This is not optimal, because it will introduce an unnecessary
2231 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2232 need to distinguish reading both $f0 and $f1 or just one of
2233 them. Note that we don't have to check the other way,
2234 because there is no instruction that sets both $f0 and $f1
2235 and requires a delay. */
2236 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2237 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2238 == (reg
&~ (unsigned) 1)))
2240 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2241 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2242 == (reg
&~ (unsigned) 1)))
2245 else if (! mips_opts
.mips16
)
2247 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2248 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2250 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2251 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2256 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2257 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2259 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2260 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2262 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2263 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2266 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2268 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2270 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2272 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2273 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2280 /* This function returns true if modifying a register requires a
2284 reg_needs_delay (unsigned int reg
)
2286 unsigned long prev_pinfo
;
2288 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2289 if (! mips_opts
.noreorder
2290 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2291 && ! gpr_interlocks
)
2292 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2293 && ! cop_interlocks
)))
2295 /* A load from a coprocessor or from memory. All load delays
2296 delay the use of general register rt for one instruction. */
2297 /* Itbl support may require additional care here. */
2298 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2299 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2306 /* Move all labels in insn_labels to the current insertion point. */
2309 mips_move_labels (void)
2311 segment_info_type
*si
= seg_info (now_seg
);
2312 struct insn_label_list
*l
;
2315 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2317 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2318 symbol_set_frag (l
->label
, frag_now
);
2319 val
= (valueT
) frag_now_fix ();
2320 /* mips16 text labels are stored as odd. */
2321 if (mips_opts
.mips16
)
2323 S_SET_VALUE (l
->label
, val
);
2328 s_is_linkonce (symbolS
*sym
, segT from_seg
)
2330 bfd_boolean linkonce
= FALSE
;
2331 segT symseg
= S_GET_SEGMENT (sym
);
2333 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
2335 if ((bfd_get_section_flags (stdoutput
, symseg
) & SEC_LINK_ONCE
))
2338 /* The GNU toolchain uses an extension for ELF: a section
2339 beginning with the magic string .gnu.linkonce is a
2340 linkonce section. */
2341 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
2342 sizeof ".gnu.linkonce" - 1) == 0)
2349 /* Mark instruction labels in mips16 mode. This permits the linker to
2350 handle them specially, such as generating jalx instructions when
2351 needed. We also make them odd for the duration of the assembly, in
2352 order to generate the right sort of code. We will make them even
2353 in the adjust_symtab routine, while leaving them marked. This is
2354 convenient for the debugger and the disassembler. The linker knows
2355 to make them odd again. */
2358 mips16_mark_labels (void)
2360 segment_info_type
*si
= seg_info (now_seg
);
2361 struct insn_label_list
*l
;
2363 if (!mips_opts
.mips16
)
2366 for (l
= si
->label_list
; l
!= NULL
; l
= l
->next
)
2368 symbolS
*label
= l
->label
;
2370 #if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2372 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
2374 if ((S_GET_VALUE (label
) & 1) == 0
2375 /* Don't adjust the address if the label is global or weak, or
2376 in a link-once section, since we'll be emitting symbol reloc
2377 references to it which will be patched up by the linker, and
2378 the final value of the symbol may or may not be MIPS16. */
2379 && ! S_IS_WEAK (label
)
2380 && ! S_IS_EXTERNAL (label
)
2381 && ! s_is_linkonce (label
, now_seg
))
2382 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
2386 /* End the current frag. Make it a variant frag and record the
2390 relax_close_frag (void)
2392 mips_macro_warning
.first_frag
= frag_now
;
2393 frag_var (rs_machine_dependent
, 0, 0,
2394 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2395 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2397 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2398 mips_relax
.first_fixup
= 0;
2401 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2402 See the comment above RELAX_ENCODE for more details. */
2405 relax_start (symbolS
*symbol
)
2407 assert (mips_relax
.sequence
== 0);
2408 mips_relax
.sequence
= 1;
2409 mips_relax
.symbol
= symbol
;
2412 /* Start generating the second version of a relaxable sequence.
2413 See the comment above RELAX_ENCODE for more details. */
2418 assert (mips_relax
.sequence
== 1);
2419 mips_relax
.sequence
= 2;
2422 /* End the current relaxable sequence. */
2427 assert (mips_relax
.sequence
== 2);
2428 relax_close_frag ();
2429 mips_relax
.sequence
= 0;
2432 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2433 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2434 by VR4120 errata. */
2437 classify_vr4120_insn (const char *name
)
2439 if (strncmp (name
, "macc", 4) == 0)
2440 return FIX_VR4120_MACC
;
2441 if (strncmp (name
, "dmacc", 5) == 0)
2442 return FIX_VR4120_DMACC
;
2443 if (strncmp (name
, "mult", 4) == 0)
2444 return FIX_VR4120_MULT
;
2445 if (strncmp (name
, "dmult", 5) == 0)
2446 return FIX_VR4120_DMULT
;
2447 if (strstr (name
, "div"))
2448 return FIX_VR4120_DIV
;
2449 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2450 return FIX_VR4120_MTHILO
;
2451 return NUM_FIX_VR4120_CLASSES
;
2454 /* Return the number of instructions that must separate INSN1 and INSN2,
2455 where INSN1 is the earlier instruction. Return the worst-case value
2456 for any INSN2 if INSN2 is null. */
2459 insns_between (const struct mips_cl_insn
*insn1
,
2460 const struct mips_cl_insn
*insn2
)
2462 unsigned long pinfo1
, pinfo2
;
2464 /* This function needs to know which pinfo flags are set for INSN2
2465 and which registers INSN2 uses. The former is stored in PINFO2 and
2466 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2467 will have every flag set and INSN2_USES_REG will always return true. */
2468 pinfo1
= insn1
->insn_mo
->pinfo
;
2469 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2471 #define INSN2_USES_REG(REG, CLASS) \
2472 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2474 /* For most targets, write-after-read dependencies on the HI and LO
2475 registers must be separated by at least two instructions. */
2476 if (!hilo_interlocks
)
2478 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2480 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2484 /* If we're working around r7000 errata, there must be two instructions
2485 between an mfhi or mflo and any instruction that uses the result. */
2486 if (mips_7000_hilo_fix
2487 && MF_HILO_INSN (pinfo1
)
2488 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2491 /* If working around VR4120 errata, check for combinations that need
2492 a single intervening instruction. */
2493 if (mips_fix_vr4120
)
2495 unsigned int class1
, class2
;
2497 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2498 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2502 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2503 if (vr4120_conflicts
[class1
] & (1 << class2
))
2508 if (!mips_opts
.mips16
)
2510 /* Check for GPR or coprocessor load delays. All such delays
2511 are on the RT register. */
2512 /* Itbl support may require additional care here. */
2513 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2514 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2516 know (pinfo1
& INSN_WRITE_GPR_T
);
2517 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2521 /* Check for generic coprocessor hazards.
2523 This case is not handled very well. There is no special
2524 knowledge of CP0 handling, and the coprocessors other than
2525 the floating point unit are not distinguished at all. */
2526 /* Itbl support may require additional care here. FIXME!
2527 Need to modify this to include knowledge about
2528 user specified delays! */
2529 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2530 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2532 /* Handle cases where INSN1 writes to a known general coprocessor
2533 register. There must be a one instruction delay before INSN2
2534 if INSN2 reads that register, otherwise no delay is needed. */
2535 if (pinfo1
& INSN_WRITE_FPR_T
)
2537 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2540 else if (pinfo1
& INSN_WRITE_FPR_S
)
2542 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2547 /* Read-after-write dependencies on the control registers
2548 require a two-instruction gap. */
2549 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2550 && (pinfo2
& INSN_READ_COND_CODE
))
2553 /* We don't know exactly what INSN1 does. If INSN2 is
2554 also a coprocessor instruction, assume there must be
2555 a one instruction gap. */
2556 if (pinfo2
& INSN_COP
)
2561 /* Check for read-after-write dependencies on the coprocessor
2562 control registers in cases where INSN1 does not need a general
2563 coprocessor delay. This means that INSN1 is a floating point
2564 comparison instruction. */
2565 /* Itbl support may require additional care here. */
2566 else if (!cop_interlocks
2567 && (pinfo1
& INSN_WRITE_COND_CODE
)
2568 && (pinfo2
& INSN_READ_COND_CODE
))
2572 #undef INSN2_USES_REG
2577 /* Return the number of nops that would be needed to work around the
2578 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2579 the MAX_VR4130_NOPS instructions described by HISTORY. */
2582 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2583 const struct mips_cl_insn
*insn
)
2587 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2588 are not affected by the errata. */
2590 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2591 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2592 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2595 /* Search for the first MFLO or MFHI. */
2596 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2597 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2599 /* Extract the destination register. */
2600 if (mips_opts
.mips16
)
2601 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2603 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2605 /* No nops are needed if INSN reads that register. */
2606 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2609 /* ...or if any of the intervening instructions do. */
2610 for (j
= 0; j
< i
; j
++)
2611 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2614 return MAX_VR4130_NOPS
- i
;
2619 /* Return the number of nops that would be needed if instruction INSN
2620 immediately followed the MAX_NOPS instructions given by HISTORY,
2621 where HISTORY[0] is the most recent instruction. If INSN is null,
2622 return the worse-case number of nops for any instruction. */
2625 nops_for_insn (const struct mips_cl_insn
*history
,
2626 const struct mips_cl_insn
*insn
)
2628 int i
, nops
, tmp_nops
;
2631 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2632 if (!history
[i
].noreorder_p
)
2634 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2635 if (tmp_nops
> nops
)
2639 if (mips_fix_vr4130
)
2641 tmp_nops
= nops_for_vr4130 (history
, insn
);
2642 if (tmp_nops
> nops
)
2649 /* The variable arguments provide NUM_INSNS extra instructions that
2650 might be added to HISTORY. Return the largest number of nops that
2651 would be needed after the extended sequence. */
2654 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2657 struct mips_cl_insn buffer
[MAX_NOPS
];
2658 struct mips_cl_insn
*cursor
;
2661 va_start (args
, history
);
2662 cursor
= buffer
+ num_insns
;
2663 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2664 while (cursor
> buffer
)
2665 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2667 nops
= nops_for_insn (buffer
, NULL
);
2672 /* Like nops_for_insn, but if INSN is a branch, take into account the
2673 worst-case delay for the branch target. */
2676 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2677 const struct mips_cl_insn
*insn
)
2681 nops
= nops_for_insn (history
, insn
);
2682 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2683 | INSN_COND_BRANCH_DELAY
2684 | INSN_COND_BRANCH_LIKELY
))
2686 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2687 if (tmp_nops
> nops
)
2690 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2692 tmp_nops
= nops_for_sequence (1, history
, insn
);
2693 if (tmp_nops
> nops
)
2699 /* Output an instruction. IP is the instruction information.
2700 ADDRESS_EXPR is an operand of the instruction to be used with
2704 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2705 bfd_reloc_code_real_type
*reloc_type
)
2707 unsigned long prev_pinfo
, pinfo
;
2708 relax_stateT prev_insn_frag_type
= 0;
2709 bfd_boolean relaxed_branch
= FALSE
;
2710 segment_info_type
*si
= seg_info (now_seg
);
2712 /* Mark instruction labels in mips16 mode. */
2713 mips16_mark_labels ();
2715 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2716 pinfo
= ip
->insn_mo
->pinfo
;
2718 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2720 /* There are a lot of optimizations we could do that we don't.
2721 In particular, we do not, in general, reorder instructions.
2722 If you use gcc with optimization, it will reorder
2723 instructions and generally do much more optimization then we
2724 do here; repeating all that work in the assembler would only
2725 benefit hand written assembly code, and does not seem worth
2727 int nops
= (mips_optimize
== 0
2728 ? nops_for_insn (history
, NULL
)
2729 : nops_for_insn_or_target (history
, ip
));
2733 unsigned long old_frag_offset
;
2736 old_frag
= frag_now
;
2737 old_frag_offset
= frag_now_fix ();
2739 for (i
= 0; i
< nops
; i
++)
2744 listing_prev_line ();
2745 /* We may be at the start of a variant frag. In case we
2746 are, make sure there is enough space for the frag
2747 after the frags created by listing_prev_line. The
2748 argument to frag_grow here must be at least as large
2749 as the argument to all other calls to frag_grow in
2750 this file. We don't have to worry about being in the
2751 middle of a variant frag, because the variants insert
2752 all needed nop instructions themselves. */
2756 mips_move_labels ();
2758 #ifndef NO_ECOFF_DEBUGGING
2759 if (ECOFF_DEBUGGING
)
2760 ecoff_fix_loc (old_frag
, old_frag_offset
);
2764 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2766 /* Work out how many nops in prev_nop_frag are needed by IP. */
2767 int nops
= nops_for_insn_or_target (history
, ip
);
2768 assert (nops
<= prev_nop_frag_holds
);
2770 /* Enforce NOPS as a minimum. */
2771 if (nops
> prev_nop_frag_required
)
2772 prev_nop_frag_required
= nops
;
2774 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2776 /* Settle for the current number of nops. Update the history
2777 accordingly (for the benefit of any future .set reorder code). */
2778 prev_nop_frag
= NULL
;
2779 insert_into_history (prev_nop_frag_since
,
2780 prev_nop_frag_holds
, NOP_INSN
);
2784 /* Allow this instruction to replace one of the nops that was
2785 tentatively added to prev_nop_frag. */
2786 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2787 prev_nop_frag_holds
--;
2788 prev_nop_frag_since
++;
2793 /* The value passed to dwarf2_emit_insn is the distance between
2794 the beginning of the current instruction and the address that
2795 should be recorded in the debug tables. For MIPS16 debug info
2796 we want to use ISA-encoded addresses, so we pass -1 for an
2797 address higher by one than the current. */
2798 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2801 /* Record the frag type before frag_var. */
2802 if (history
[0].frag
)
2803 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2806 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2807 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2808 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2809 && mips_relax_branch
2810 /* Don't try branch relaxation within .set nomacro, or within
2811 .set noat if we use $at for PIC computations. If it turns
2812 out that the branch was out-of-range, we'll get an error. */
2813 && !mips_opts
.warn_about_macros
2814 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
2815 && !mips_opts
.mips16
)
2817 relaxed_branch
= TRUE
;
2818 add_relaxed_insn (ip
, (relaxed_branch_length
2820 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2821 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2824 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2825 pinfo
& INSN_COND_BRANCH_LIKELY
,
2826 pinfo
& INSN_WRITE_GPR_31
,
2828 address_expr
->X_add_symbol
,
2829 address_expr
->X_add_number
);
2830 *reloc_type
= BFD_RELOC_UNUSED
;
2832 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2834 /* We need to set up a variant frag. */
2835 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2836 add_relaxed_insn (ip
, 4, 0,
2838 (*reloc_type
- BFD_RELOC_UNUSED
,
2839 mips16_small
, mips16_ext
,
2840 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2841 history
[0].mips16_absolute_jump_p
),
2842 make_expr_symbol (address_expr
), 0);
2844 else if (mips_opts
.mips16
2846 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2848 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2849 /* Make sure there is enough room to swap this instruction with
2850 a following jump instruction. */
2852 add_fixed_insn (ip
);
2856 if (mips_opts
.mips16
2857 && mips_opts
.noreorder
2858 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2859 as_warn (_("extended instruction in delay slot"));
2861 if (mips_relax
.sequence
)
2863 /* If we've reached the end of this frag, turn it into a variant
2864 frag and record the information for the instructions we've
2866 if (frag_room () < 4)
2867 relax_close_frag ();
2868 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2871 if (mips_relax
.sequence
!= 2)
2872 mips_macro_warning
.sizes
[0] += 4;
2873 if (mips_relax
.sequence
!= 1)
2874 mips_macro_warning
.sizes
[1] += 4;
2876 if (mips_opts
.mips16
)
2879 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2881 add_fixed_insn (ip
);
2884 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2886 if (address_expr
->X_op
== O_constant
)
2890 switch (*reloc_type
)
2893 ip
->insn_opcode
|= address_expr
->X_add_number
;
2896 case BFD_RELOC_MIPS_HIGHEST
:
2897 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2898 ip
->insn_opcode
|= tmp
& 0xffff;
2901 case BFD_RELOC_MIPS_HIGHER
:
2902 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2903 ip
->insn_opcode
|= tmp
& 0xffff;
2906 case BFD_RELOC_HI16_S
:
2907 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2908 ip
->insn_opcode
|= tmp
& 0xffff;
2911 case BFD_RELOC_HI16
:
2912 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2915 case BFD_RELOC_UNUSED
:
2916 case BFD_RELOC_LO16
:
2917 case BFD_RELOC_MIPS_GOT_DISP
:
2918 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2921 case BFD_RELOC_MIPS_JMP
:
2922 if ((address_expr
->X_add_number
& 3) != 0)
2923 as_bad (_("jump to misaligned address (0x%lx)"),
2924 (unsigned long) address_expr
->X_add_number
);
2925 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2928 case BFD_RELOC_MIPS16_JMP
:
2929 if ((address_expr
->X_add_number
& 3) != 0)
2930 as_bad (_("jump to misaligned address (0x%lx)"),
2931 (unsigned long) address_expr
->X_add_number
);
2933 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2934 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2935 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2938 case BFD_RELOC_16_PCREL_S2
:
2939 if ((address_expr
->X_add_number
& 3) != 0)
2940 as_bad (_("branch to misaligned address (0x%lx)"),
2941 (unsigned long) address_expr
->X_add_number
);
2942 if (mips_relax_branch
)
2944 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2945 as_bad (_("branch address range overflow (0x%lx)"),
2946 (unsigned long) address_expr
->X_add_number
);
2947 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2954 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2957 reloc_howto_type
*howto
;
2960 /* In a compound relocation, it is the final (outermost)
2961 operator that determines the relocated field. */
2962 for (i
= 1; i
< 3; i
++)
2963 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2966 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2969 /* To reproduce this failure try assembling gas/testsuites/
2970 gas/mips/mips16-intermix.s with a mips-ecoff targeted
2972 as_bad (_("Unsupported MIPS relocation number %d"), reloc_type
[i
- 1]);
2973 howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16
);
2976 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2977 bfd_get_reloc_size (howto
),
2979 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2982 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2983 if (reloc_type
[0] == BFD_RELOC_MIPS16_JMP
2984 && ip
->fixp
[0]->fx_addsy
)
2985 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
2987 /* These relocations can have an addend that won't fit in
2988 4 octets for 64bit assembly. */
2990 && ! howto
->partial_inplace
2991 && (reloc_type
[0] == BFD_RELOC_16
2992 || reloc_type
[0] == BFD_RELOC_32
2993 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2994 || reloc_type
[0] == BFD_RELOC_GPREL16
2995 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2996 || reloc_type
[0] == BFD_RELOC_GPREL32
2997 || reloc_type
[0] == BFD_RELOC_64
2998 || reloc_type
[0] == BFD_RELOC_CTOR
2999 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
3000 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
3001 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
3002 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
3003 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
3004 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
3005 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
3006 || hi16_reloc_p (reloc_type
[0])
3007 || lo16_reloc_p (reloc_type
[0])))
3008 ip
->fixp
[0]->fx_no_overflow
= 1;
3010 if (mips_relax
.sequence
)
3012 if (mips_relax
.first_fixup
== 0)
3013 mips_relax
.first_fixup
= ip
->fixp
[0];
3015 else if (reloc_needs_lo_p (*reloc_type
))
3017 struct mips_hi_fixup
*hi_fixup
;
3019 /* Reuse the last entry if it already has a matching %lo. */
3020 hi_fixup
= mips_hi_fixup_list
;
3022 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
3024 hi_fixup
= ((struct mips_hi_fixup
*)
3025 xmalloc (sizeof (struct mips_hi_fixup
)));
3026 hi_fixup
->next
= mips_hi_fixup_list
;
3027 mips_hi_fixup_list
= hi_fixup
;
3029 hi_fixup
->fixp
= ip
->fixp
[0];
3030 hi_fixup
->seg
= now_seg
;
3033 /* Add fixups for the second and third relocations, if given.
3034 Note that the ABI allows the second relocation to be
3035 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
3036 moment we only use RSS_UNDEF, but we could add support
3037 for the others if it ever becomes necessary. */
3038 for (i
= 1; i
< 3; i
++)
3039 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
3041 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
3042 ip
->fixp
[0]->fx_size
, NULL
, 0,
3043 FALSE
, reloc_type
[i
]);
3045 /* Use fx_tcbit to mark compound relocs. */
3046 ip
->fixp
[0]->fx_tcbit
= 1;
3047 ip
->fixp
[i
]->fx_tcbit
= 1;
3053 /* Update the register mask information. */
3054 if (! mips_opts
.mips16
)
3056 if (pinfo
& INSN_WRITE_GPR_D
)
3057 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
3058 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
3059 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
3060 if (pinfo
& INSN_READ_GPR_S
)
3061 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
3062 if (pinfo
& INSN_WRITE_GPR_31
)
3063 mips_gprmask
|= 1 << RA
;
3064 if (pinfo
& INSN_WRITE_FPR_D
)
3065 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
3066 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
3067 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
3068 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
3069 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
3070 if ((pinfo
& INSN_READ_FPR_R
) != 0)
3071 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
3072 if (pinfo
& INSN_COP
)
3074 /* We don't keep enough information to sort these cases out.
3075 The itbl support does keep this information however, although
3076 we currently don't support itbl fprmats as part of the cop
3077 instruction. May want to add this support in the future. */
3079 /* Never set the bit for $0, which is always zero. */
3080 mips_gprmask
&= ~1 << 0;
3084 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
3085 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
3086 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
3087 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
3088 if (pinfo
& MIPS16_INSN_WRITE_Z
)
3089 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
3090 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
3091 mips_gprmask
|= 1 << TREG
;
3092 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
3093 mips_gprmask
|= 1 << SP
;
3094 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
3095 mips_gprmask
|= 1 << RA
;
3096 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3097 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
3098 if (pinfo
& MIPS16_INSN_READ_Z
)
3099 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
3100 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
3101 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
3104 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
3106 /* Filling the branch delay slot is more complex. We try to
3107 switch the branch with the previous instruction, which we can
3108 do if the previous instruction does not set up a condition
3109 that the branch tests and if the branch is not itself the
3110 target of any branch. */
3111 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3112 || (pinfo
& INSN_COND_BRANCH_DELAY
))
3114 if (mips_optimize
< 2
3115 /* If we have seen .set volatile or .set nomove, don't
3117 || mips_opts
.nomove
!= 0
3118 /* We can't swap if the previous instruction's position
3120 || history
[0].fixed_p
3121 /* If the previous previous insn was in a .set
3122 noreorder, we can't swap. Actually, the MIPS
3123 assembler will swap in this situation. However, gcc
3124 configured -with-gnu-as will generate code like
3130 in which we can not swap the bne and INSN. If gcc is
3131 not configured -with-gnu-as, it does not output the
3133 || history
[1].noreorder_p
3134 /* If the branch is itself the target of a branch, we
3135 can not swap. We cheat on this; all we check for is
3136 whether there is a label on this instruction. If
3137 there are any branches to anything other than a
3138 label, users must use .set noreorder. */
3139 || si
->label_list
!= NULL
3140 /* If the previous instruction is in a variant frag
3141 other than this branch's one, we cannot do the swap.
3142 This does not apply to the mips16, which uses variant
3143 frags for different purposes. */
3144 || (! mips_opts
.mips16
3145 && prev_insn_frag_type
== rs_machine_dependent
)
3146 /* Check for conflicts between the branch and the instructions
3147 before the candidate delay slot. */
3148 || nops_for_insn (history
+ 1, ip
) > 0
3149 /* Check for conflicts between the swapped sequence and the
3150 target of the branch. */
3151 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
3152 /* We do not swap with a trap instruction, since it
3153 complicates trap handlers to have the trap
3154 instruction be in a delay slot. */
3155 || (prev_pinfo
& INSN_TRAP
)
3156 /* If the branch reads a register that the previous
3157 instruction sets, we can not swap. */
3158 || (! mips_opts
.mips16
3159 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3160 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
3162 || (! mips_opts
.mips16
3163 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3164 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
3166 || (mips_opts
.mips16
3167 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
3169 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
3171 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
3173 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
3175 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
3177 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
3179 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
3180 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
3181 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3182 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
3183 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3184 && insn_uses_reg (ip
,
3185 MIPS16OP_EXTRACT_REG32R
3186 (history
[0].insn_opcode
),
3188 /* If the branch writes a register that the previous
3189 instruction sets, we can not swap (we know that
3190 branches write only to RD or to $31). */
3191 || (! mips_opts
.mips16
3192 && (prev_pinfo
& INSN_WRITE_GPR_T
)
3193 && (((pinfo
& INSN_WRITE_GPR_D
)
3194 && (EXTRACT_OPERAND (RT
, history
[0])
3195 == EXTRACT_OPERAND (RD
, *ip
)))
3196 || ((pinfo
& INSN_WRITE_GPR_31
)
3197 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
3198 || (! mips_opts
.mips16
3199 && (prev_pinfo
& INSN_WRITE_GPR_D
)
3200 && (((pinfo
& INSN_WRITE_GPR_D
)
3201 && (EXTRACT_OPERAND (RD
, history
[0])
3202 == EXTRACT_OPERAND (RD
, *ip
)))
3203 || ((pinfo
& INSN_WRITE_GPR_31
)
3204 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
3205 || (mips_opts
.mips16
3206 && (pinfo
& MIPS16_INSN_WRITE_31
)
3207 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
3208 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
3209 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
3211 /* If the branch writes a register that the previous
3212 instruction reads, we can not swap (we know that
3213 branches only write to RD or to $31). */
3214 || (! mips_opts
.mips16
3215 && (pinfo
& INSN_WRITE_GPR_D
)
3216 && insn_uses_reg (&history
[0],
3217 EXTRACT_OPERAND (RD
, *ip
),
3219 || (! mips_opts
.mips16
3220 && (pinfo
& INSN_WRITE_GPR_31
)
3221 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3222 || (mips_opts
.mips16
3223 && (pinfo
& MIPS16_INSN_WRITE_31
)
3224 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
3225 /* If one instruction sets a condition code and the
3226 other one uses a condition code, we can not swap. */
3227 || ((pinfo
& INSN_READ_COND_CODE
)
3228 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
3229 || ((pinfo
& INSN_WRITE_COND_CODE
)
3230 && (prev_pinfo
& INSN_READ_COND_CODE
))
3231 /* If the previous instruction uses the PC, we can not
3233 || (mips_opts
.mips16
3234 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
3235 /* If the previous instruction had a fixup in mips16
3236 mode, we can not swap. This normally means that the
3237 previous instruction was a 4 byte branch anyhow. */
3238 || (mips_opts
.mips16
&& history
[0].fixp
[0])
3239 /* If the previous instruction is a sync, sync.l, or
3240 sync.p, we can not swap. */
3241 || (prev_pinfo
& INSN_SYNC
))
3243 if (mips_opts
.mips16
3244 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3245 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3246 && ISA_SUPPORTS_MIPS16E
)
3248 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3249 ip
->insn_opcode
|= 0x0080;
3251 insert_into_history (0, 1, ip
);
3255 /* We could do even better for unconditional branches to
3256 portions of this object file; we could pick up the
3257 instruction at the destination, put it in the delay
3258 slot, and bump the destination address. */
3259 insert_into_history (0, 1, ip
);
3263 if (mips_relax
.sequence
)
3264 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3268 /* It looks like we can actually do the swap. */
3269 struct mips_cl_insn delay
= history
[0];
3270 if (mips_opts
.mips16
)
3272 know (delay
.frag
== ip
->frag
);
3273 move_insn (ip
, delay
.frag
, delay
.where
);
3274 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3276 else if (relaxed_branch
)
3278 /* Add the delay slot instruction to the end of the
3279 current frag and shrink the fixed part of the
3280 original frag. If the branch occupies the tail of
3281 the latter, move it backwards to cover the gap. */
3282 delay
.frag
->fr_fix
-= 4;
3283 if (delay
.frag
== ip
->frag
)
3284 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3285 add_fixed_insn (&delay
);
3289 move_insn (&delay
, ip
->frag
, ip
->where
);
3290 move_insn (ip
, history
[0].frag
, history
[0].where
);
3294 insert_into_history (0, 1, &delay
);
3297 /* If that was an unconditional branch, forget the previous
3298 insn information. */
3299 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3300 mips_no_prev_insn ();
3302 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3304 /* We don't yet optimize a branch likely. What we should do
3305 is look at the target, copy the instruction found there
3306 into the delay slot, and increment the branch to jump to
3307 the next instruction. */
3308 insert_into_history (0, 1, ip
);
3312 insert_into_history (0, 1, ip
);
3315 insert_into_history (0, 1, ip
);
3317 /* We just output an insn, so the next one doesn't have a label. */
3318 mips_clear_insn_labels ();
3321 /* Forget that there was any previous instruction or label. */
3324 mips_no_prev_insn (void)
3326 prev_nop_frag
= NULL
;
3327 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3328 mips_clear_insn_labels ();
3331 /* This function must be called before we emit something other than
3332 instructions. It is like mips_no_prev_insn except that it inserts
3333 any NOPS that might be needed by previous instructions. */
3336 mips_emit_delays (void)
3338 if (! mips_opts
.noreorder
)
3340 int nops
= nops_for_insn (history
, NULL
);
3344 add_fixed_insn (NOP_INSN
);
3345 mips_move_labels ();
3348 mips_no_prev_insn ();
3351 /* Start a (possibly nested) noreorder block. */
3354 start_noreorder (void)
3356 if (mips_opts
.noreorder
== 0)
3361 /* None of the instructions before the .set noreorder can be moved. */
3362 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3363 history
[i
].fixed_p
= 1;
3365 /* Insert any nops that might be needed between the .set noreorder
3366 block and the previous instructions. We will later remove any
3367 nops that turn out not to be needed. */
3368 nops
= nops_for_insn (history
, NULL
);
3371 if (mips_optimize
!= 0)
3373 /* Record the frag which holds the nop instructions, so
3374 that we can remove them if we don't need them. */
3375 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3376 prev_nop_frag
= frag_now
;
3377 prev_nop_frag_holds
= nops
;
3378 prev_nop_frag_required
= 0;
3379 prev_nop_frag_since
= 0;
3382 for (; nops
> 0; --nops
)
3383 add_fixed_insn (NOP_INSN
);
3385 /* Move on to a new frag, so that it is safe to simply
3386 decrease the size of prev_nop_frag. */
3387 frag_wane (frag_now
);
3389 mips_move_labels ();
3391 mips16_mark_labels ();
3392 mips_clear_insn_labels ();
3394 mips_opts
.noreorder
++;
3395 mips_any_noreorder
= 1;
3398 /* End a nested noreorder block. */
3401 end_noreorder (void)
3403 mips_opts
.noreorder
--;
3404 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3406 /* Commit to inserting prev_nop_frag_required nops and go back to
3407 handling nop insertion the .set reorder way. */
3408 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3409 * (mips_opts
.mips16
? 2 : 4));
3410 insert_into_history (prev_nop_frag_since
,
3411 prev_nop_frag_required
, NOP_INSN
);
3412 prev_nop_frag
= NULL
;
3416 /* Set up global variables for the start of a new macro. */
3421 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3422 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3423 && (history
[0].insn_mo
->pinfo
3424 & (INSN_UNCOND_BRANCH_DELAY
3425 | INSN_COND_BRANCH_DELAY
3426 | INSN_COND_BRANCH_LIKELY
)) != 0);
3429 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3430 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3431 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3434 macro_warning (relax_substateT subtype
)
3436 if (subtype
& RELAX_DELAY_SLOT
)
3437 return _("Macro instruction expanded into multiple instructions"
3438 " in a branch delay slot");
3439 else if (subtype
& RELAX_NOMACRO
)
3440 return _("Macro instruction expanded into multiple instructions");
3445 /* Finish up a macro. Emit warnings as appropriate. */
3450 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3452 relax_substateT subtype
;
3454 /* Set up the relaxation warning flags. */
3456 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3457 subtype
|= RELAX_SECOND_LONGER
;
3458 if (mips_opts
.warn_about_macros
)
3459 subtype
|= RELAX_NOMACRO
;
3460 if (mips_macro_warning
.delay_slot_p
)
3461 subtype
|= RELAX_DELAY_SLOT
;
3463 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3465 /* Either the macro has a single implementation or both
3466 implementations are longer than 4 bytes. Emit the
3468 const char *msg
= macro_warning (subtype
);
3474 /* One implementation might need a warning but the other
3475 definitely doesn't. */
3476 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3481 /* Read a macro's relocation codes from *ARGS and store them in *R.
3482 The first argument in *ARGS will be either the code for a single
3483 relocation or -1 followed by the three codes that make up a
3484 composite relocation. */
3487 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3491 next
= va_arg (*args
, int);
3493 r
[0] = (bfd_reloc_code_real_type
) next
;
3495 for (i
= 0; i
< 3; i
++)
3496 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3499 /* Build an instruction created by a macro expansion. This is passed
3500 a pointer to the count of instructions created so far, an
3501 expression, the name of the instruction to build, an operand format
3502 string, and corresponding arguments. */
3505 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3507 const struct mips_opcode
*mo
;
3508 struct mips_cl_insn insn
;
3509 bfd_reloc_code_real_type r
[3];
3512 va_start (args
, fmt
);
3514 if (mips_opts
.mips16
)
3516 mips16_macro_build (ep
, name
, fmt
, args
);
3521 r
[0] = BFD_RELOC_UNUSED
;
3522 r
[1] = BFD_RELOC_UNUSED
;
3523 r
[2] = BFD_RELOC_UNUSED
;
3524 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3526 assert (strcmp (name
, mo
->name
) == 0);
3530 /* Search until we get a match for NAME. It is assumed here that
3531 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3532 if (strcmp (fmt
, mo
->args
) == 0
3533 && mo
->pinfo
!= INSN_MACRO
3534 && is_opcode_valid (mo
, TRUE
))
3539 assert (strcmp (name
, mo
->name
) == 0);
3542 create_insn (&insn
, mo
);
3560 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3565 /* Note that in the macro case, these arguments are already
3566 in MSB form. (When handling the instruction in the
3567 non-macro case, these arguments are sizes from which
3568 MSB values must be calculated.) */
3569 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3575 /* Note that in the macro case, these arguments are already
3576 in MSBD form. (When handling the instruction in the
3577 non-macro case, these arguments are sizes from which
3578 MSBD values must be calculated.) */
3579 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3583 INSERT_OPERAND (SEQI
, insn
, va_arg (args
, int));
3592 INSERT_OPERAND (BP
, insn
, va_arg (args
, int));
3598 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3602 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3607 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3613 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3618 int tmp
= va_arg (args
, int);
3620 INSERT_OPERAND (RT
, insn
, tmp
);
3621 INSERT_OPERAND (RD
, insn
, tmp
);
3627 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3634 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3638 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3642 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3646 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3650 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3657 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3663 macro_read_relocs (&args
, r
);
3664 assert (*r
== BFD_RELOC_GPREL16
3665 || *r
== BFD_RELOC_MIPS_LITERAL
3666 || *r
== BFD_RELOC_MIPS_HIGHER
3667 || *r
== BFD_RELOC_HI16_S
3668 || *r
== BFD_RELOC_LO16
3669 || *r
== BFD_RELOC_MIPS_GOT16
3670 || *r
== BFD_RELOC_MIPS_CALL16
3671 || *r
== BFD_RELOC_MIPS_GOT_DISP
3672 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3673 || *r
== BFD_RELOC_MIPS_GOT_OFST
3674 || *r
== BFD_RELOC_MIPS_GOT_LO16
3675 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3679 macro_read_relocs (&args
, r
);
3681 && (ep
->X_op
== O_constant
3682 || (ep
->X_op
== O_symbol
3683 && (*r
== BFD_RELOC_MIPS_HIGHEST
3684 || *r
== BFD_RELOC_HI16_S
3685 || *r
== BFD_RELOC_HI16
3686 || *r
== BFD_RELOC_GPREL16
3687 || *r
== BFD_RELOC_MIPS_GOT_HI16
3688 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3692 assert (ep
!= NULL
);
3695 * This allows macro() to pass an immediate expression for
3696 * creating short branches without creating a symbol.
3698 * We don't allow branch relaxation for these branches, as
3699 * they should only appear in ".set nomacro" anyway.
3701 if (ep
->X_op
== O_constant
)
3703 if ((ep
->X_add_number
& 3) != 0)
3704 as_bad (_("branch to misaligned address (0x%lx)"),
3705 (unsigned long) ep
->X_add_number
);
3706 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3707 as_bad (_("branch address range overflow (0x%lx)"),
3708 (unsigned long) ep
->X_add_number
);
3709 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3713 *r
= BFD_RELOC_16_PCREL_S2
;
3717 assert (ep
!= NULL
);
3718 *r
= BFD_RELOC_MIPS_JMP
;
3722 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3726 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3735 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3737 append_insn (&insn
, ep
, r
);
3741 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3744 struct mips_opcode
*mo
;
3745 struct mips_cl_insn insn
;
3746 bfd_reloc_code_real_type r
[3]
3747 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3749 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3751 assert (strcmp (name
, mo
->name
) == 0);
3753 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3757 assert (strcmp (name
, mo
->name
) == 0);
3760 create_insn (&insn
, mo
);
3778 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3783 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3787 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3791 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3801 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3808 regno
= va_arg (args
, int);
3809 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3810 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3831 assert (ep
!= NULL
);
3833 if (ep
->X_op
!= O_constant
)
3834 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3837 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3838 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3841 *r
= BFD_RELOC_UNUSED
;
3847 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3854 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3856 append_insn (&insn
, ep
, r
);
3860 * Sign-extend 32-bit mode constants that have bit 31 set and all
3861 * higher bits unset.
3864 normalize_constant_expr (expressionS
*ex
)
3866 if (ex
->X_op
== O_constant
3867 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3868 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3873 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3874 * all higher bits unset.
3877 normalize_address_expr (expressionS
*ex
)
3879 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3880 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3881 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3882 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3887 * Generate a "jalr" instruction with a relocation hint to the called
3888 * function. This occurs in NewABI PIC code.
3891 macro_build_jalr (expressionS
*ep
)
3900 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3902 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3903 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3907 * Generate a "lui" instruction.
3910 macro_build_lui (expressionS
*ep
, int regnum
)
3912 expressionS high_expr
;
3913 const struct mips_opcode
*mo
;
3914 struct mips_cl_insn insn
;
3915 bfd_reloc_code_real_type r
[3]
3916 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3917 const char *name
= "lui";
3918 const char *fmt
= "t,u";
3920 assert (! mips_opts
.mips16
);
3924 if (high_expr
.X_op
== O_constant
)
3926 /* We can compute the instruction now without a relocation entry. */
3927 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3929 *r
= BFD_RELOC_UNUSED
;
3933 assert (ep
->X_op
== O_symbol
);
3934 /* _gp_disp is a special case, used from s_cpload.
3935 __gnu_local_gp is used if mips_no_shared. */
3936 assert (mips_pic
== NO_PIC
3938 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3939 || (! mips_in_shared
3940 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3941 "__gnu_local_gp") == 0));
3942 *r
= BFD_RELOC_HI16_S
;
3945 mo
= hash_find (op_hash
, name
);
3946 assert (strcmp (name
, mo
->name
) == 0);
3947 assert (strcmp (fmt
, mo
->args
) == 0);
3948 create_insn (&insn
, mo
);
3950 insn
.insn_opcode
= insn
.insn_mo
->match
;
3951 INSERT_OPERAND (RT
, insn
, regnum
);
3952 if (*r
== BFD_RELOC_UNUSED
)
3954 insn
.insn_opcode
|= high_expr
.X_add_number
;
3955 append_insn (&insn
, NULL
, r
);
3958 append_insn (&insn
, &high_expr
, r
);
3961 /* Generate a sequence of instructions to do a load or store from a constant
3962 offset off of a base register (breg) into/from a target register (treg),
3963 using AT if necessary. */
3965 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3966 int treg
, int breg
, int dbl
)
3968 assert (ep
->X_op
== O_constant
);
3970 /* Sign-extending 32-bit constants makes their handling easier. */
3972 normalize_constant_expr (ep
);
3974 /* Right now, this routine can only handle signed 32-bit constants. */
3975 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3976 as_warn (_("operand overflow"));
3978 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3980 /* Signed 16-bit offset will fit in the op. Easy! */
3981 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3985 /* 32-bit offset, need multiple instructions and AT, like:
3986 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3987 addu $tempreg,$tempreg,$breg
3988 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3989 to handle the complete offset. */
3990 macro_build_lui (ep
, AT
);
3991 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3992 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3995 as_bad (_("Macro used $at after \".set noat\""));
4000 * Generates code to set the $at register to true (one)
4001 * if reg is less than the immediate expression.
4004 set_at (int reg
, int unsignedp
)
4006 if (imm_expr
.X_op
== O_constant
4007 && imm_expr
.X_add_number
>= -0x8000
4008 && imm_expr
.X_add_number
< 0x8000)
4009 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
4010 AT
, reg
, BFD_RELOC_LO16
);
4013 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4014 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
4018 /* Warn if an expression is not a constant. */
4021 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
4023 if (ex
->X_op
== O_big
)
4024 as_bad (_("unsupported large constant"));
4025 else if (ex
->X_op
!= O_constant
)
4026 as_bad (_("Instruction %s requires absolute expression"),
4029 if (HAVE_32BIT_GPRS
)
4030 normalize_constant_expr (ex
);
4033 /* Count the leading zeroes by performing a binary chop. This is a
4034 bulky bit of source, but performance is a LOT better for the
4035 majority of values than a simple loop to count the bits:
4036 for (lcnt = 0; (lcnt < 32); lcnt++)
4037 if ((v) & (1 << (31 - lcnt)))
4039 However it is not code size friendly, and the gain will drop a bit
4040 on certain cached systems.
4042 #define COUNT_TOP_ZEROES(v) \
4043 (((v) & ~0xffff) == 0 \
4044 ? ((v) & ~0xff) == 0 \
4045 ? ((v) & ~0xf) == 0 \
4046 ? ((v) & ~0x3) == 0 \
4047 ? ((v) & ~0x1) == 0 \
4052 : ((v) & ~0x7) == 0 \
4055 : ((v) & ~0x3f) == 0 \
4056 ? ((v) & ~0x1f) == 0 \
4059 : ((v) & ~0x7f) == 0 \
4062 : ((v) & ~0xfff) == 0 \
4063 ? ((v) & ~0x3ff) == 0 \
4064 ? ((v) & ~0x1ff) == 0 \
4067 : ((v) & ~0x7ff) == 0 \
4070 : ((v) & ~0x3fff) == 0 \
4071 ? ((v) & ~0x1fff) == 0 \
4074 : ((v) & ~0x7fff) == 0 \
4077 : ((v) & ~0xffffff) == 0 \
4078 ? ((v) & ~0xfffff) == 0 \
4079 ? ((v) & ~0x3ffff) == 0 \
4080 ? ((v) & ~0x1ffff) == 0 \
4083 : ((v) & ~0x7ffff) == 0 \
4086 : ((v) & ~0x3fffff) == 0 \
4087 ? ((v) & ~0x1fffff) == 0 \
4090 : ((v) & ~0x7fffff) == 0 \
4093 : ((v) & ~0xfffffff) == 0 \
4094 ? ((v) & ~0x3ffffff) == 0 \
4095 ? ((v) & ~0x1ffffff) == 0 \
4098 : ((v) & ~0x7ffffff) == 0 \
4101 : ((v) & ~0x3fffffff) == 0 \
4102 ? ((v) & ~0x1fffffff) == 0 \
4105 : ((v) & ~0x7fffffff) == 0 \
4110 * This routine generates the least number of instructions necessary to load
4111 * an absolute expression value into a register.
4114 load_register (int reg
, expressionS
*ep
, int dbl
)
4117 expressionS hi32
, lo32
;
4119 if (ep
->X_op
!= O_big
)
4121 assert (ep
->X_op
== O_constant
);
4123 /* Sign-extending 32-bit constants makes their handling easier. */
4125 normalize_constant_expr (ep
);
4127 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
4129 /* We can handle 16 bit signed values with an addiu to
4130 $zero. No need to ever use daddiu here, since $zero and
4131 the result are always correct in 32 bit mode. */
4132 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4135 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
4137 /* We can handle 16 bit unsigned values with an ori to
4139 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4142 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
4144 /* 32 bit values require an lui. */
4145 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4146 if ((ep
->X_add_number
& 0xffff) != 0)
4147 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4152 /* The value is larger than 32 bits. */
4154 if (!dbl
|| HAVE_32BIT_GPRS
)
4158 sprintf_vma (value
, ep
->X_add_number
);
4159 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
4160 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4164 if (ep
->X_op
!= O_big
)
4167 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4168 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
4169 hi32
.X_add_number
&= 0xffffffff;
4171 lo32
.X_add_number
&= 0xffffffff;
4175 assert (ep
->X_add_number
> 2);
4176 if (ep
->X_add_number
== 3)
4177 generic_bignum
[3] = 0;
4178 else if (ep
->X_add_number
> 4)
4179 as_bad (_("Number larger than 64 bits"));
4180 lo32
.X_op
= O_constant
;
4181 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
4182 hi32
.X_op
= O_constant
;
4183 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
4186 if (hi32
.X_add_number
== 0)
4191 unsigned long hi
, lo
;
4193 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
4195 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
4197 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4200 if (lo32
.X_add_number
& 0x80000000)
4202 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4203 if (lo32
.X_add_number
& 0xffff)
4204 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
4209 /* Check for 16bit shifted constant. We know that hi32 is
4210 non-zero, so start the mask on the first bit of the hi32
4215 unsigned long himask
, lomask
;
4219 himask
= 0xffff >> (32 - shift
);
4220 lomask
= (0xffff << shift
) & 0xffffffff;
4224 himask
= 0xffff << (shift
- 32);
4227 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
4228 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
4232 tmp
.X_op
= O_constant
;
4234 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
4235 | (lo32
.X_add_number
>> shift
));
4237 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
4238 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
4239 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
4240 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4245 while (shift
<= (64 - 16));
4247 /* Find the bit number of the lowest one bit, and store the
4248 shifted value in hi/lo. */
4249 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4250 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4254 while ((lo
& 1) == 0)
4259 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4265 while ((hi
& 1) == 0)
4274 /* Optimize if the shifted value is a (power of 2) - 1. */
4275 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4276 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4278 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4283 /* This instruction will set the register to be all
4285 tmp
.X_op
= O_constant
;
4286 tmp
.X_add_number
= (offsetT
) -1;
4287 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4291 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4292 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4294 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4295 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4300 /* Sign extend hi32 before calling load_register, because we can
4301 generally get better code when we load a sign extended value. */
4302 if ((hi32
.X_add_number
& 0x80000000) != 0)
4303 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4304 load_register (reg
, &hi32
, 0);
4307 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4311 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4319 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4321 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4322 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4328 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4332 mid16
.X_add_number
>>= 16;
4333 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4334 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4337 if ((lo32
.X_add_number
& 0xffff) != 0)
4338 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4342 load_delay_nop (void)
4344 if (!gpr_interlocks
)
4345 macro_build (NULL
, "nop", "");
4348 /* Load an address into a register. */
4351 load_address (int reg
, expressionS
*ep
, int *used_at
)
4353 if (ep
->X_op
!= O_constant
4354 && ep
->X_op
!= O_symbol
)
4356 as_bad (_("expression too complex"));
4357 ep
->X_op
= O_constant
;
4360 if (ep
->X_op
== O_constant
)
4362 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4366 if (mips_pic
== NO_PIC
)
4368 /* If this is a reference to a GP relative symbol, we want
4369 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4371 lui $reg,<sym> (BFD_RELOC_HI16_S)
4372 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4373 If we have an addend, we always use the latter form.
4375 With 64bit address space and a usable $at we want
4376 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4377 lui $at,<sym> (BFD_RELOC_HI16_S)
4378 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4379 daddiu $at,<sym> (BFD_RELOC_LO16)
4383 If $at is already in use, we use a path which is suboptimal
4384 on superscalar processors.
4385 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4386 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4388 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4390 daddiu $reg,<sym> (BFD_RELOC_LO16)
4392 For GP relative symbols in 64bit address space we can use
4393 the same sequence as in 32bit address space. */
4394 if (HAVE_64BIT_SYMBOLS
)
4396 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4397 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4399 relax_start (ep
->X_add_symbol
);
4400 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4401 mips_gp_register
, BFD_RELOC_GPREL16
);
4405 if (*used_at
== 0 && mips_opts
.at
)
4407 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4408 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4409 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4410 BFD_RELOC_MIPS_HIGHER
);
4411 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4412 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4413 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4418 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4419 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4420 BFD_RELOC_MIPS_HIGHER
);
4421 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4422 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4423 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4424 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4427 if (mips_relax
.sequence
)
4432 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4433 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4435 relax_start (ep
->X_add_symbol
);
4436 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4437 mips_gp_register
, BFD_RELOC_GPREL16
);
4440 macro_build_lui (ep
, reg
);
4441 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4442 reg
, reg
, BFD_RELOC_LO16
);
4443 if (mips_relax
.sequence
)
4447 else if (!mips_big_got
)
4451 /* If this is a reference to an external symbol, we want
4452 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4454 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4456 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4457 If there is a constant, it must be added in after.
4459 If we have NewABI, we want
4460 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4461 unless we're referencing a global symbol with a non-zero
4462 offset, in which case cst must be added separately. */
4465 if (ep
->X_add_number
)
4467 ex
.X_add_number
= ep
->X_add_number
;
4468 ep
->X_add_number
= 0;
4469 relax_start (ep
->X_add_symbol
);
4470 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4471 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4472 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4473 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4474 ex
.X_op
= O_constant
;
4475 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4476 reg
, reg
, BFD_RELOC_LO16
);
4477 ep
->X_add_number
= ex
.X_add_number
;
4480 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4481 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4482 if (mips_relax
.sequence
)
4487 ex
.X_add_number
= ep
->X_add_number
;
4488 ep
->X_add_number
= 0;
4489 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4490 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4492 relax_start (ep
->X_add_symbol
);
4494 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4498 if (ex
.X_add_number
!= 0)
4500 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4501 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4502 ex
.X_op
= O_constant
;
4503 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4504 reg
, reg
, BFD_RELOC_LO16
);
4508 else if (mips_big_got
)
4512 /* This is the large GOT case. If this is a reference to an
4513 external symbol, we want
4514 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4516 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4518 Otherwise, for a reference to a local symbol in old ABI, we want
4519 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4521 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4522 If there is a constant, it must be added in after.
4524 In the NewABI, for local symbols, with or without offsets, we want:
4525 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4526 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4530 ex
.X_add_number
= ep
->X_add_number
;
4531 ep
->X_add_number
= 0;
4532 relax_start (ep
->X_add_symbol
);
4533 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4534 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4535 reg
, reg
, mips_gp_register
);
4536 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4537 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4538 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4539 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4540 else if (ex
.X_add_number
)
4542 ex
.X_op
= O_constant
;
4543 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4547 ep
->X_add_number
= ex
.X_add_number
;
4549 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4550 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4551 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4552 BFD_RELOC_MIPS_GOT_OFST
);
4557 ex
.X_add_number
= ep
->X_add_number
;
4558 ep
->X_add_number
= 0;
4559 relax_start (ep
->X_add_symbol
);
4560 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4561 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4562 reg
, reg
, mips_gp_register
);
4563 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4564 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4566 if (reg_needs_delay (mips_gp_register
))
4568 /* We need a nop before loading from $gp. This special
4569 check is required because the lui which starts the main
4570 instruction stream does not refer to $gp, and so will not
4571 insert the nop which may be required. */
4572 macro_build (NULL
, "nop", "");
4574 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4575 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4577 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4581 if (ex
.X_add_number
!= 0)
4583 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4584 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4585 ex
.X_op
= O_constant
;
4586 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4594 if (!mips_opts
.at
&& *used_at
== 1)
4595 as_bad (_("Macro used $at after \".set noat\""));
4598 /* Move the contents of register SOURCE into register DEST. */
4601 move_register (int dest
, int source
)
4603 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4607 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4608 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4609 The two alternatives are:
4611 Global symbol Local sybmol
4612 ------------- ------------
4613 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4615 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4617 load_got_offset emits the first instruction and add_got_offset
4618 emits the second for a 16-bit offset or add_got_offset_hilo emits
4619 a sequence to add a 32-bit offset using a scratch register. */
4622 load_got_offset (int dest
, expressionS
*local
)
4627 global
.X_add_number
= 0;
4629 relax_start (local
->X_add_symbol
);
4630 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4631 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4633 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4634 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4639 add_got_offset (int dest
, expressionS
*local
)
4643 global
.X_op
= O_constant
;
4644 global
.X_op_symbol
= NULL
;
4645 global
.X_add_symbol
= NULL
;
4646 global
.X_add_number
= local
->X_add_number
;
4648 relax_start (local
->X_add_symbol
);
4649 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4650 dest
, dest
, BFD_RELOC_LO16
);
4652 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4657 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4660 int hold_mips_optimize
;
4662 global
.X_op
= O_constant
;
4663 global
.X_op_symbol
= NULL
;
4664 global
.X_add_symbol
= NULL
;
4665 global
.X_add_number
= local
->X_add_number
;
4667 relax_start (local
->X_add_symbol
);
4668 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4670 /* Set mips_optimize around the lui instruction to avoid
4671 inserting an unnecessary nop after the lw. */
4672 hold_mips_optimize
= mips_optimize
;
4674 macro_build_lui (&global
, tmp
);
4675 mips_optimize
= hold_mips_optimize
;
4676 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4679 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4684 * This routine implements the seemingly endless macro or synthesized
4685 * instructions and addressing modes in the mips assembly language. Many
4686 * of these macros are simple and are similar to each other. These could
4687 * probably be handled by some kind of table or grammar approach instead of
4688 * this verbose method. Others are not simple macros but are more like
4689 * optimizing code generation.
4690 * One interesting optimization is when several store macros appear
4691 * consecutively that would load AT with the upper half of the same address.
4692 * The ensuing load upper instructions are ommited. This implies some kind
4693 * of global optimization. We currently only optimize within a single macro.
4694 * For many of the load and store macros if the address is specified as a
4695 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4696 * first load register 'at' with zero and use it as the base register. The
4697 * mips assembler simply uses register $zero. Just one tiny optimization
4701 macro (struct mips_cl_insn
*ip
)
4703 unsigned int treg
, sreg
, dreg
, breg
;
4704 unsigned int tempreg
;
4719 bfd_reloc_code_real_type r
;
4720 int hold_mips_optimize
;
4722 assert (! mips_opts
.mips16
);
4724 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4725 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4726 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4727 mask
= ip
->insn_mo
->mask
;
4729 expr1
.X_op
= O_constant
;
4730 expr1
.X_op_symbol
= NULL
;
4731 expr1
.X_add_symbol
= NULL
;
4732 expr1
.X_add_number
= 1;
4746 expr1
.X_add_number
= 8;
4747 macro_build (&expr1
, "bgez", "s,p", sreg
);
4749 macro_build (NULL
, "nop", "", 0);
4751 move_register (dreg
, sreg
);
4752 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4775 if (imm_expr
.X_op
== O_constant
4776 && imm_expr
.X_add_number
>= -0x8000
4777 && imm_expr
.X_add_number
< 0x8000)
4779 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4783 load_register (AT
, &imm_expr
, dbl
);
4784 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4803 if (imm_expr
.X_op
== O_constant
4804 && imm_expr
.X_add_number
>= 0
4805 && imm_expr
.X_add_number
< 0x10000)
4807 if (mask
!= M_NOR_I
)
4808 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4811 macro_build (&imm_expr
, "ori", "t,r,i",
4812 treg
, sreg
, BFD_RELOC_LO16
);
4813 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4819 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4820 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4824 switch (imm_expr
.X_add_number
)
4827 macro_build (NULL
, "nop", "");
4830 macro_build (NULL
, "packrl.ph", "d,s,t", treg
, treg
, sreg
);
4833 macro_build (NULL
, "balign", "t,s,2", treg
, sreg
,
4834 (int)imm_expr
.X_add_number
);
4853 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4855 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4859 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4860 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4868 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4873 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4877 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4878 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4884 /* check for > max integer */
4885 maxnum
= 0x7fffffff;
4886 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4893 if (imm_expr
.X_op
== O_constant
4894 && imm_expr
.X_add_number
>= maxnum
4895 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4898 /* result is always false */
4900 macro_build (NULL
, "nop", "", 0);
4902 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4905 if (imm_expr
.X_op
!= O_constant
)
4906 as_bad (_("Unsupported large constant"));
4907 ++imm_expr
.X_add_number
;
4911 if (mask
== M_BGEL_I
)
4913 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4915 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4918 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4920 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4923 maxnum
= 0x7fffffff;
4924 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4931 maxnum
= - maxnum
- 1;
4932 if (imm_expr
.X_op
== O_constant
4933 && imm_expr
.X_add_number
<= maxnum
4934 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4937 /* result is always true */
4938 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4939 macro_build (&offset_expr
, "b", "p");
4944 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4954 macro_build (&offset_expr
, likely
? "beql" : "beq",
4959 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4960 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4968 && imm_expr
.X_op
== O_constant
4969 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4971 if (imm_expr
.X_op
!= O_constant
)
4972 as_bad (_("Unsupported large constant"));
4973 ++imm_expr
.X_add_number
;
4977 if (mask
== M_BGEUL_I
)
4979 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4981 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4983 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4989 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4997 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
5002 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
5006 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5007 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5015 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5022 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5023 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5031 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5036 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
5040 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
5041 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5047 maxnum
= 0x7fffffff;
5048 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
5055 if (imm_expr
.X_op
== O_constant
5056 && imm_expr
.X_add_number
>= maxnum
5057 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
5059 if (imm_expr
.X_op
!= O_constant
)
5060 as_bad (_("Unsupported large constant"));
5061 ++imm_expr
.X_add_number
;
5065 if (mask
== M_BLTL_I
)
5067 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5069 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5072 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5074 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
5079 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5087 macro_build (&offset_expr
, likely
? "beql" : "beq",
5094 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
5095 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
5103 && imm_expr
.X_op
== O_constant
5104 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
5106 if (imm_expr
.X_op
!= O_constant
)
5107 as_bad (_("Unsupported large constant"));
5108 ++imm_expr
.X_add_number
;
5112 if (mask
== M_BLTUL_I
)
5114 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5116 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5118 macro_build (&offset_expr
, likely
? "beql" : "beq",
5124 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5132 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
5137 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
5141 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
5142 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5152 macro_build (&offset_expr
, likely
? "bnel" : "bne",
5157 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
5158 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
5166 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5168 as_bad (_("Unsupported large constant"));
5173 pos
= (unsigned long) imm_expr
.X_add_number
;
5174 size
= (unsigned long) imm2_expr
.X_add_number
;
5179 as_bad (_("Improper position (%lu)"), pos
);
5182 if (size
== 0 || size
> 64
5183 || (pos
+ size
- 1) > 63)
5185 as_bad (_("Improper extract size (%lu, position %lu)"),
5190 if (size
<= 32 && pos
< 32)
5195 else if (size
<= 32)
5205 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
5214 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
5216 as_bad (_("Unsupported large constant"));
5221 pos
= (unsigned long) imm_expr
.X_add_number
;
5222 size
= (unsigned long) imm2_expr
.X_add_number
;
5227 as_bad (_("Improper position (%lu)"), pos
);
5230 if (size
== 0 || size
> 64
5231 || (pos
+ size
- 1) > 63)
5233 as_bad (_("Improper insert size (%lu, position %lu)"),
5238 if (pos
< 32 && (pos
+ size
- 1) < 32)
5253 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, (int) pos
,
5254 (int) (pos
+ size
- 1));
5270 as_warn (_("Divide by zero."));
5272 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5274 macro_build (NULL
, "break", "c", 7);
5281 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5282 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5286 expr1
.X_add_number
= 8;
5287 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5288 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5289 macro_build (NULL
, "break", "c", 7);
5291 expr1
.X_add_number
= -1;
5293 load_register (AT
, &expr1
, dbl
);
5294 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5295 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5298 expr1
.X_add_number
= 1;
5299 load_register (AT
, &expr1
, dbl
);
5300 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5304 expr1
.X_add_number
= 0x80000000;
5305 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5309 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5310 /* We want to close the noreorder block as soon as possible, so
5311 that later insns are available for delay slot filling. */
5316 expr1
.X_add_number
= 8;
5317 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5318 macro_build (NULL
, "nop", "", 0);
5320 /* We want to close the noreorder block as soon as possible, so
5321 that later insns are available for delay slot filling. */
5324 macro_build (NULL
, "break", "c", 6);
5326 macro_build (NULL
, s
, "d", dreg
);
5365 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5367 as_warn (_("Divide by zero."));
5369 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5371 macro_build (NULL
, "break", "c", 7);
5374 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5376 if (strcmp (s2
, "mflo") == 0)
5377 move_register (dreg
, sreg
);
5379 move_register (dreg
, 0);
5382 if (imm_expr
.X_op
== O_constant
5383 && imm_expr
.X_add_number
== -1
5384 && s
[strlen (s
) - 1] != 'u')
5386 if (strcmp (s2
, "mflo") == 0)
5388 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5391 move_register (dreg
, 0);
5396 load_register (AT
, &imm_expr
, dbl
);
5397 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5398 macro_build (NULL
, s2
, "d", dreg
);
5420 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5421 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5422 /* We want to close the noreorder block as soon as possible, so
5423 that later insns are available for delay slot filling. */
5428 expr1
.X_add_number
= 8;
5429 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5430 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5432 /* We want to close the noreorder block as soon as possible, so
5433 that later insns are available for delay slot filling. */
5435 macro_build (NULL
, "break", "c", 7);
5437 macro_build (NULL
, s2
, "d", dreg
);
5449 /* Load the address of a symbol into a register. If breg is not
5450 zero, we then add a base register to it. */
5452 if (dbl
&& HAVE_32BIT_GPRS
)
5453 as_warn (_("dla used to load 32-bit register"));
5455 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5456 as_warn (_("la used to load 64-bit address"));
5458 if (offset_expr
.X_op
== O_constant
5459 && offset_expr
.X_add_number
>= -0x8000
5460 && offset_expr
.X_add_number
< 0x8000)
5462 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5463 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5467 if (mips_opts
.at
&& (treg
== breg
))
5477 if (offset_expr
.X_op
!= O_symbol
5478 && offset_expr
.X_op
!= O_constant
)
5480 as_bad (_("expression too complex"));
5481 offset_expr
.X_op
= O_constant
;
5484 if (offset_expr
.X_op
== O_constant
)
5485 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5486 else if (mips_pic
== NO_PIC
)
5488 /* If this is a reference to a GP relative symbol, we want
5489 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5491 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5492 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5493 If we have a constant, we need two instructions anyhow,
5494 so we may as well always use the latter form.
5496 With 64bit address space and a usable $at we want
5497 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5498 lui $at,<sym> (BFD_RELOC_HI16_S)
5499 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5500 daddiu $at,<sym> (BFD_RELOC_LO16)
5502 daddu $tempreg,$tempreg,$at
5504 If $at is already in use, we use a path which is suboptimal
5505 on superscalar processors.
5506 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5507 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5509 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5511 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5513 For GP relative symbols in 64bit address space we can use
5514 the same sequence as in 32bit address space. */
5515 if (HAVE_64BIT_SYMBOLS
)
5517 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5518 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5520 relax_start (offset_expr
.X_add_symbol
);
5521 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5522 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5526 if (used_at
== 0 && mips_opts
.at
)
5528 macro_build (&offset_expr
, "lui", "t,u",
5529 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5530 macro_build (&offset_expr
, "lui", "t,u",
5531 AT
, BFD_RELOC_HI16_S
);
5532 macro_build (&offset_expr
, "daddiu", "t,r,j",
5533 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5534 macro_build (&offset_expr
, "daddiu", "t,r,j",
5535 AT
, AT
, BFD_RELOC_LO16
);
5536 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5537 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5542 macro_build (&offset_expr
, "lui", "t,u",
5543 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5544 macro_build (&offset_expr
, "daddiu", "t,r,j",
5545 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5546 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5547 macro_build (&offset_expr
, "daddiu", "t,r,j",
5548 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5549 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5550 macro_build (&offset_expr
, "daddiu", "t,r,j",
5551 tempreg
, tempreg
, BFD_RELOC_LO16
);
5554 if (mips_relax
.sequence
)
5559 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5560 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5562 relax_start (offset_expr
.X_add_symbol
);
5563 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5564 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5567 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5568 as_bad (_("offset too large"));
5569 macro_build_lui (&offset_expr
, tempreg
);
5570 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5571 tempreg
, tempreg
, BFD_RELOC_LO16
);
5572 if (mips_relax
.sequence
)
5576 else if (!mips_big_got
&& !HAVE_NEWABI
)
5578 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5580 /* If this is a reference to an external symbol, and there
5581 is no constant, we want
5582 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5583 or for lca or if tempreg is PIC_CALL_REG
5584 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5585 For a local symbol, we want
5586 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5588 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5590 If we have a small constant, and this is a reference to
5591 an external symbol, we want
5592 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5594 addiu $tempreg,$tempreg,<constant>
5595 For a local symbol, we want the same instruction
5596 sequence, but we output a BFD_RELOC_LO16 reloc on the
5599 If we have a large constant, and this is a reference to
5600 an external symbol, we want
5601 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5602 lui $at,<hiconstant>
5603 addiu $at,$at,<loconstant>
5604 addu $tempreg,$tempreg,$at
5605 For a local symbol, we want the same instruction
5606 sequence, but we output a BFD_RELOC_LO16 reloc on the
5610 if (offset_expr
.X_add_number
== 0)
5612 if (mips_pic
== SVR4_PIC
5614 && (call
|| tempreg
== PIC_CALL_REG
))
5615 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5617 relax_start (offset_expr
.X_add_symbol
);
5618 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5619 lw_reloc_type
, mips_gp_register
);
5622 /* We're going to put in an addu instruction using
5623 tempreg, so we may as well insert the nop right
5628 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5629 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5631 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5632 tempreg
, tempreg
, BFD_RELOC_LO16
);
5634 /* FIXME: If breg == 0, and the next instruction uses
5635 $tempreg, then if this variant case is used an extra
5636 nop will be generated. */
5638 else if (offset_expr
.X_add_number
>= -0x8000
5639 && offset_expr
.X_add_number
< 0x8000)
5641 load_got_offset (tempreg
, &offset_expr
);
5643 add_got_offset (tempreg
, &offset_expr
);
5647 expr1
.X_add_number
= offset_expr
.X_add_number
;
5648 offset_expr
.X_add_number
=
5649 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5650 load_got_offset (tempreg
, &offset_expr
);
5651 offset_expr
.X_add_number
= expr1
.X_add_number
;
5652 /* If we are going to add in a base register, and the
5653 target register and the base register are the same,
5654 then we are using AT as a temporary register. Since
5655 we want to load the constant into AT, we add our
5656 current AT (from the global offset table) and the
5657 register into the register now, and pretend we were
5658 not using a base register. */
5662 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5667 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5671 else if (!mips_big_got
&& HAVE_NEWABI
)
5673 int add_breg_early
= 0;
5675 /* If this is a reference to an external, and there is no
5676 constant, or local symbol (*), with or without a
5678 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5679 or for lca or if tempreg is PIC_CALL_REG
5680 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5682 If we have a small constant, and this is a reference to
5683 an external symbol, we want
5684 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5685 addiu $tempreg,$tempreg,<constant>
5687 If we have a large constant, and this is a reference to
5688 an external symbol, we want
5689 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5690 lui $at,<hiconstant>
5691 addiu $at,$at,<loconstant>
5692 addu $tempreg,$tempreg,$at
5694 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5695 local symbols, even though it introduces an additional
5698 if (offset_expr
.X_add_number
)
5700 expr1
.X_add_number
= offset_expr
.X_add_number
;
5701 offset_expr
.X_add_number
= 0;
5703 relax_start (offset_expr
.X_add_symbol
);
5704 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5705 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5707 if (expr1
.X_add_number
>= -0x8000
5708 && expr1
.X_add_number
< 0x8000)
5710 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5711 tempreg
, tempreg
, BFD_RELOC_LO16
);
5713 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5717 /* If we are going to add in a base register, and the
5718 target register and the base register are the same,
5719 then we are using AT as a temporary register. Since
5720 we want to load the constant into AT, we add our
5721 current AT (from the global offset table) and the
5722 register into the register now, and pretend we were
5723 not using a base register. */
5728 assert (tempreg
== AT
);
5729 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5735 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5736 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5742 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5745 offset_expr
.X_add_number
= expr1
.X_add_number
;
5747 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5748 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5751 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5752 treg
, tempreg
, breg
);
5758 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5760 relax_start (offset_expr
.X_add_symbol
);
5761 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5762 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5764 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5765 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5770 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5771 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5774 else if (mips_big_got
&& !HAVE_NEWABI
)
5777 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5778 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5779 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5781 /* This is the large GOT case. If this is a reference to an
5782 external symbol, and there is no constant, we want
5783 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5784 addu $tempreg,$tempreg,$gp
5785 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5786 or for lca or if tempreg is PIC_CALL_REG
5787 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5788 addu $tempreg,$tempreg,$gp
5789 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5790 For a local symbol, we want
5791 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5793 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5795 If we have a small constant, and this is a reference to
5796 an external symbol, we want
5797 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5798 addu $tempreg,$tempreg,$gp
5799 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5801 addiu $tempreg,$tempreg,<constant>
5802 For a local symbol, we want
5803 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5805 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5807 If we have a large constant, and this is a reference to
5808 an external symbol, we want
5809 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5810 addu $tempreg,$tempreg,$gp
5811 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5812 lui $at,<hiconstant>
5813 addiu $at,$at,<loconstant>
5814 addu $tempreg,$tempreg,$at
5815 For a local symbol, we want
5816 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5817 lui $at,<hiconstant>
5818 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5819 addu $tempreg,$tempreg,$at
5822 expr1
.X_add_number
= offset_expr
.X_add_number
;
5823 offset_expr
.X_add_number
= 0;
5824 relax_start (offset_expr
.X_add_symbol
);
5825 gpdelay
= reg_needs_delay (mips_gp_register
);
5826 if (expr1
.X_add_number
== 0 && breg
== 0
5827 && (call
|| tempreg
== PIC_CALL_REG
))
5829 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5830 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5832 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5833 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5834 tempreg
, tempreg
, mips_gp_register
);
5835 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5836 tempreg
, lw_reloc_type
, tempreg
);
5837 if (expr1
.X_add_number
== 0)
5841 /* We're going to put in an addu instruction using
5842 tempreg, so we may as well insert the nop right
5847 else if (expr1
.X_add_number
>= -0x8000
5848 && expr1
.X_add_number
< 0x8000)
5851 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5852 tempreg
, tempreg
, BFD_RELOC_LO16
);
5858 /* If we are going to add in a base register, and the
5859 target register and the base register are the same,
5860 then we are using AT as a temporary register. Since
5861 we want to load the constant into AT, we add our
5862 current AT (from the global offset table) and the
5863 register into the register now, and pretend we were
5864 not using a base register. */
5869 assert (tempreg
== AT
);
5871 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5876 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5877 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5881 offset_expr
.X_add_number
=
5882 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5887 /* This is needed because this instruction uses $gp, but
5888 the first instruction on the main stream does not. */
5889 macro_build (NULL
, "nop", "");
5892 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5893 local_reloc_type
, mips_gp_register
);
5894 if (expr1
.X_add_number
>= -0x8000
5895 && expr1
.X_add_number
< 0x8000)
5898 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5899 tempreg
, tempreg
, BFD_RELOC_LO16
);
5900 /* FIXME: If add_number is 0, and there was no base
5901 register, the external symbol case ended with a load,
5902 so if the symbol turns out to not be external, and
5903 the next instruction uses tempreg, an unnecessary nop
5904 will be inserted. */
5910 /* We must add in the base register now, as in the
5911 external symbol case. */
5912 assert (tempreg
== AT
);
5914 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5917 /* We set breg to 0 because we have arranged to add
5918 it in in both cases. */
5922 macro_build_lui (&expr1
, AT
);
5923 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5924 AT
, AT
, BFD_RELOC_LO16
);
5925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5926 tempreg
, tempreg
, AT
);
5931 else if (mips_big_got
&& HAVE_NEWABI
)
5933 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5934 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5935 int add_breg_early
= 0;
5937 /* This is the large GOT case. If this is a reference to an
5938 external symbol, and there is no constant, we want
5939 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5940 add $tempreg,$tempreg,$gp
5941 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5942 or for lca or if tempreg is PIC_CALL_REG
5943 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5944 add $tempreg,$tempreg,$gp
5945 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5947 If we have a small constant, and this is a reference to
5948 an external symbol, we want
5949 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5950 add $tempreg,$tempreg,$gp
5951 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5952 addi $tempreg,$tempreg,<constant>
5954 If we have a large constant, and this is a reference to
5955 an external symbol, we want
5956 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5957 addu $tempreg,$tempreg,$gp
5958 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5959 lui $at,<hiconstant>
5960 addi $at,$at,<loconstant>
5961 add $tempreg,$tempreg,$at
5963 If we have NewABI, and we know it's a local symbol, we want
5964 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5965 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5966 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5968 relax_start (offset_expr
.X_add_symbol
);
5970 expr1
.X_add_number
= offset_expr
.X_add_number
;
5971 offset_expr
.X_add_number
= 0;
5973 if (expr1
.X_add_number
== 0 && breg
== 0
5974 && (call
|| tempreg
== PIC_CALL_REG
))
5976 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5977 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5979 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5980 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5981 tempreg
, tempreg
, mips_gp_register
);
5982 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5983 tempreg
, lw_reloc_type
, tempreg
);
5985 if (expr1
.X_add_number
== 0)
5987 else if (expr1
.X_add_number
>= -0x8000
5988 && expr1
.X_add_number
< 0x8000)
5990 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5991 tempreg
, tempreg
, BFD_RELOC_LO16
);
5993 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5997 /* If we are going to add in a base register, and the
5998 target register and the base register are the same,
5999 then we are using AT as a temporary register. Since
6000 we want to load the constant into AT, we add our
6001 current AT (from the global offset table) and the
6002 register into the register now, and pretend we were
6003 not using a base register. */
6008 assert (tempreg
== AT
);
6009 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6015 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
6016 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
6021 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
6024 offset_expr
.X_add_number
= expr1
.X_add_number
;
6025 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6026 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6027 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6028 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
6031 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6032 treg
, tempreg
, breg
);
6042 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
6046 /* The j instruction may not be used in PIC code, since it
6047 requires an absolute address. We convert it to a b
6049 if (mips_pic
== NO_PIC
)
6050 macro_build (&offset_expr
, "j", "a");
6052 macro_build (&offset_expr
, "b", "p");
6055 /* The jal instructions must be handled as macros because when
6056 generating PIC code they expand to multi-instruction
6057 sequences. Normally they are simple instructions. */
6062 if (mips_pic
== NO_PIC
)
6063 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6066 if (sreg
!= PIC_CALL_REG
)
6067 as_warn (_("MIPS PIC call to register other than $25"));
6069 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
6070 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
6072 if (mips_cprestore_offset
< 0)
6073 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6076 if (! mips_frame_reg_valid
)
6078 as_warn (_("No .frame pseudo-op used in PIC code"));
6079 /* Quiet this warning. */
6080 mips_frame_reg_valid
= 1;
6082 if (! mips_cprestore_valid
)
6084 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6085 /* Quiet this warning. */
6086 mips_cprestore_valid
= 1;
6088 expr1
.X_add_number
= mips_cprestore_offset
;
6089 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6092 HAVE_64BIT_ADDRESSES
);
6100 if (mips_pic
== NO_PIC
)
6101 macro_build (&offset_expr
, "jal", "a");
6102 else if (mips_pic
== SVR4_PIC
)
6104 /* If this is a reference to an external symbol, and we are
6105 using a small GOT, we want
6106 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
6110 lw $gp,cprestore($sp)
6111 The cprestore value is set using the .cprestore
6112 pseudo-op. If we are using a big GOT, we want
6113 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
6115 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
6119 lw $gp,cprestore($sp)
6120 If the symbol is not external, we want
6121 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6123 addiu $25,$25,<sym> (BFD_RELOC_LO16)
6126 lw $gp,cprestore($sp)
6128 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
6129 sequences above, minus nops, unless the symbol is local,
6130 which enables us to use GOT_PAGE/GOT_OFST (big got) or
6136 relax_start (offset_expr
.X_add_symbol
);
6137 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6138 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6141 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6142 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
6148 relax_start (offset_expr
.X_add_symbol
);
6149 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6150 BFD_RELOC_MIPS_CALL_HI16
);
6151 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6152 PIC_CALL_REG
, mips_gp_register
);
6153 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6154 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6157 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6158 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
6160 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6161 PIC_CALL_REG
, PIC_CALL_REG
,
6162 BFD_RELOC_MIPS_GOT_OFST
);
6166 macro_build_jalr (&offset_expr
);
6170 relax_start (offset_expr
.X_add_symbol
);
6173 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6174 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
6183 gpdelay
= reg_needs_delay (mips_gp_register
);
6184 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
6185 BFD_RELOC_MIPS_CALL_HI16
);
6186 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
6187 PIC_CALL_REG
, mips_gp_register
);
6188 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6189 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
6194 macro_build (NULL
, "nop", "");
6196 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6197 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
6200 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
6201 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
6203 macro_build_jalr (&offset_expr
);
6205 if (mips_cprestore_offset
< 0)
6206 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6209 if (! mips_frame_reg_valid
)
6211 as_warn (_("No .frame pseudo-op used in PIC code"));
6212 /* Quiet this warning. */
6213 mips_frame_reg_valid
= 1;
6215 if (! mips_cprestore_valid
)
6217 as_warn (_("No .cprestore pseudo-op used in PIC code"));
6218 /* Quiet this warning. */
6219 mips_cprestore_valid
= 1;
6221 if (mips_opts
.noreorder
)
6222 macro_build (NULL
, "nop", "");
6223 expr1
.X_add_number
= mips_cprestore_offset
;
6224 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
6227 HAVE_64BIT_ADDRESSES
);
6231 else if (mips_pic
== VXWORKS_PIC
)
6232 as_bad (_("Non-PIC jump used in PIC library"));
6255 /* Itbl support may require additional care here. */
6260 /* Itbl support may require additional care here. */
6265 /* Itbl support may require additional care here. */
6270 /* Itbl support may require additional care here. */
6283 /* Itbl support may require additional care here. */
6288 /* Itbl support may require additional care here. */
6293 /* Itbl support may require additional care here. */
6313 if (breg
== treg
|| coproc
|| lr
)
6334 /* Itbl support may require additional care here. */
6339 /* Itbl support may require additional care here. */
6344 /* Itbl support may require additional care here. */
6349 /* Itbl support may require additional care here. */
6370 /* Itbl support may require additional care here. */
6374 /* Itbl support may require additional care here. */
6379 /* Itbl support may require additional care here. */
6392 && NO_ISA_COP (mips_opts
.arch
)
6393 && (ip
->insn_mo
->pinfo2
& (INSN2_M_FP_S
| INSN2_M_FP_D
)) == 0)
6395 as_bad (_("opcode not supported on this processor: %s"),
6396 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
6400 /* Itbl support may require additional care here. */
6401 if (mask
== M_LWC1_AB
6402 || mask
== M_SWC1_AB
6403 || mask
== M_LDC1_AB
6404 || mask
== M_SDC1_AB
6408 else if (mask
== M_CACHE_AB
)
6415 if (offset_expr
.X_op
!= O_constant
6416 && offset_expr
.X_op
!= O_symbol
)
6418 as_bad (_("expression too complex"));
6419 offset_expr
.X_op
= O_constant
;
6422 if (HAVE_32BIT_ADDRESSES
6423 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6427 sprintf_vma (value
, offset_expr
.X_add_number
);
6428 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6431 /* A constant expression in PIC code can be handled just as it
6432 is in non PIC code. */
6433 if (offset_expr
.X_op
== O_constant
)
6435 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6436 & ~(bfd_vma
) 0xffff);
6437 normalize_address_expr (&expr1
);
6438 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6440 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6441 tempreg
, tempreg
, breg
);
6442 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6444 else if (mips_pic
== NO_PIC
)
6446 /* If this is a reference to a GP relative symbol, and there
6447 is no base register, we want
6448 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6449 Otherwise, if there is no base register, we want
6450 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6451 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6452 If we have a constant, we need two instructions anyhow,
6453 so we always use the latter form.
6455 If we have a base register, and this is a reference to a
6456 GP relative symbol, we want
6457 addu $tempreg,$breg,$gp
6458 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6460 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6461 addu $tempreg,$tempreg,$breg
6462 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6463 With a constant we always use the latter case.
6465 With 64bit address space and no base register and $at usable,
6467 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6468 lui $at,<sym> (BFD_RELOC_HI16_S)
6469 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6472 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6473 If we have a base register, we want
6474 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6475 lui $at,<sym> (BFD_RELOC_HI16_S)
6476 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6480 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6482 Without $at we can't generate the optimal path for superscalar
6483 processors here since this would require two temporary registers.
6484 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6485 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6487 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6489 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6490 If we have a base register, we want
6491 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6492 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6494 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6496 daddu $tempreg,$tempreg,$breg
6497 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6499 For GP relative symbols in 64bit address space we can use
6500 the same sequence as in 32bit address space. */
6501 if (HAVE_64BIT_SYMBOLS
)
6503 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6504 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6506 relax_start (offset_expr
.X_add_symbol
);
6509 macro_build (&offset_expr
, s
, fmt
, treg
,
6510 BFD_RELOC_GPREL16
, mips_gp_register
);
6514 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6515 tempreg
, breg
, mips_gp_register
);
6516 macro_build (&offset_expr
, s
, fmt
, treg
,
6517 BFD_RELOC_GPREL16
, tempreg
);
6522 if (used_at
== 0 && mips_opts
.at
)
6524 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6525 BFD_RELOC_MIPS_HIGHEST
);
6526 macro_build (&offset_expr
, "lui", "t,u", AT
,
6528 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6529 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6531 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6532 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6533 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6534 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6540 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6541 BFD_RELOC_MIPS_HIGHEST
);
6542 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6543 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6544 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6545 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6546 tempreg
, BFD_RELOC_HI16_S
);
6547 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6549 macro_build (NULL
, "daddu", "d,v,t",
6550 tempreg
, tempreg
, breg
);
6551 macro_build (&offset_expr
, s
, fmt
, treg
,
6552 BFD_RELOC_LO16
, tempreg
);
6555 if (mips_relax
.sequence
)
6562 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6563 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6565 relax_start (offset_expr
.X_add_symbol
);
6566 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6570 macro_build_lui (&offset_expr
, tempreg
);
6571 macro_build (&offset_expr
, s
, fmt
, treg
,
6572 BFD_RELOC_LO16
, tempreg
);
6573 if (mips_relax
.sequence
)
6578 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6579 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6581 relax_start (offset_expr
.X_add_symbol
);
6582 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6583 tempreg
, breg
, mips_gp_register
);
6584 macro_build (&offset_expr
, s
, fmt
, treg
,
6585 BFD_RELOC_GPREL16
, tempreg
);
6588 macro_build_lui (&offset_expr
, tempreg
);
6589 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6590 tempreg
, tempreg
, breg
);
6591 macro_build (&offset_expr
, s
, fmt
, treg
,
6592 BFD_RELOC_LO16
, tempreg
);
6593 if (mips_relax
.sequence
)
6597 else if (!mips_big_got
)
6599 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6601 /* If this is a reference to an external symbol, we want
6602 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6604 <op> $treg,0($tempreg)
6606 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6608 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6609 <op> $treg,0($tempreg)
6612 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6613 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6615 If there is a base register, we add it to $tempreg before
6616 the <op>. If there is a constant, we stick it in the
6617 <op> instruction. We don't handle constants larger than
6618 16 bits, because we have no way to load the upper 16 bits
6619 (actually, we could handle them for the subset of cases
6620 in which we are not using $at). */
6621 assert (offset_expr
.X_op
== O_symbol
);
6624 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6625 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6627 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6628 tempreg
, tempreg
, breg
);
6629 macro_build (&offset_expr
, s
, fmt
, treg
,
6630 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6633 expr1
.X_add_number
= offset_expr
.X_add_number
;
6634 offset_expr
.X_add_number
= 0;
6635 if (expr1
.X_add_number
< -0x8000
6636 || expr1
.X_add_number
>= 0x8000)
6637 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6638 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6639 lw_reloc_type
, mips_gp_register
);
6641 relax_start (offset_expr
.X_add_symbol
);
6643 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6644 tempreg
, BFD_RELOC_LO16
);
6647 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6648 tempreg
, tempreg
, breg
);
6649 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6651 else if (mips_big_got
&& !HAVE_NEWABI
)
6655 /* If this is a reference to an external symbol, we want
6656 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6657 addu $tempreg,$tempreg,$gp
6658 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6659 <op> $treg,0($tempreg)
6661 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6663 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6664 <op> $treg,0($tempreg)
6665 If there is a base register, we add it to $tempreg before
6666 the <op>. If there is a constant, we stick it in the
6667 <op> instruction. We don't handle constants larger than
6668 16 bits, because we have no way to load the upper 16 bits
6669 (actually, we could handle them for the subset of cases
6670 in which we are not using $at). */
6671 assert (offset_expr
.X_op
== O_symbol
);
6672 expr1
.X_add_number
= offset_expr
.X_add_number
;
6673 offset_expr
.X_add_number
= 0;
6674 if (expr1
.X_add_number
< -0x8000
6675 || expr1
.X_add_number
>= 0x8000)
6676 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6677 gpdelay
= reg_needs_delay (mips_gp_register
);
6678 relax_start (offset_expr
.X_add_symbol
);
6679 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6680 BFD_RELOC_MIPS_GOT_HI16
);
6681 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6683 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6684 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6687 macro_build (NULL
, "nop", "");
6688 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6689 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6691 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6692 tempreg
, BFD_RELOC_LO16
);
6696 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6697 tempreg
, tempreg
, breg
);
6698 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6700 else if (mips_big_got
&& HAVE_NEWABI
)
6702 /* If this is a reference to an external symbol, we want
6703 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6704 add $tempreg,$tempreg,$gp
6705 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6706 <op> $treg,<ofst>($tempreg)
6707 Otherwise, for local symbols, we want:
6708 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6709 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6710 assert (offset_expr
.X_op
== O_symbol
);
6711 expr1
.X_add_number
= offset_expr
.X_add_number
;
6712 offset_expr
.X_add_number
= 0;
6713 if (expr1
.X_add_number
< -0x8000
6714 || expr1
.X_add_number
>= 0x8000)
6715 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6716 relax_start (offset_expr
.X_add_symbol
);
6717 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6718 BFD_RELOC_MIPS_GOT_HI16
);
6719 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6721 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6722 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6724 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6725 tempreg
, tempreg
, breg
);
6726 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6729 offset_expr
.X_add_number
= expr1
.X_add_number
;
6730 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6731 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6733 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6734 tempreg
, tempreg
, breg
);
6735 macro_build (&offset_expr
, s
, fmt
, treg
,
6736 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6746 load_register (treg
, &imm_expr
, 0);
6750 load_register (treg
, &imm_expr
, 1);
6754 if (imm_expr
.X_op
== O_constant
)
6757 load_register (AT
, &imm_expr
, 0);
6758 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6763 assert (offset_expr
.X_op
== O_symbol
6764 && strcmp (segment_name (S_GET_SEGMENT
6765 (offset_expr
.X_add_symbol
)),
6767 && offset_expr
.X_add_number
== 0);
6768 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6769 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6774 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6775 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6776 order 32 bits of the value and the low order 32 bits are either
6777 zero or in OFFSET_EXPR. */
6778 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6780 if (HAVE_64BIT_GPRS
)
6781 load_register (treg
, &imm_expr
, 1);
6786 if (target_big_endian
)
6798 load_register (hreg
, &imm_expr
, 0);
6801 if (offset_expr
.X_op
== O_absent
)
6802 move_register (lreg
, 0);
6805 assert (offset_expr
.X_op
== O_constant
);
6806 load_register (lreg
, &offset_expr
, 0);
6813 /* We know that sym is in the .rdata section. First we get the
6814 upper 16 bits of the address. */
6815 if (mips_pic
== NO_PIC
)
6817 macro_build_lui (&offset_expr
, AT
);
6822 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6823 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6827 /* Now we load the register(s). */
6828 if (HAVE_64BIT_GPRS
)
6831 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6836 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6839 /* FIXME: How in the world do we deal with the possible
6841 offset_expr
.X_add_number
+= 4;
6842 macro_build (&offset_expr
, "lw", "t,o(b)",
6843 treg
+ 1, BFD_RELOC_LO16
, AT
);
6849 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6850 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6851 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6852 the value and the low order 32 bits are either zero or in
6854 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6857 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6858 if (HAVE_64BIT_FPRS
)
6860 assert (HAVE_64BIT_GPRS
);
6861 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6865 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6866 if (offset_expr
.X_op
== O_absent
)
6867 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6870 assert (offset_expr
.X_op
== O_constant
);
6871 load_register (AT
, &offset_expr
, 0);
6872 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6878 assert (offset_expr
.X_op
== O_symbol
6879 && offset_expr
.X_add_number
== 0);
6880 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6881 if (strcmp (s
, ".lit8") == 0)
6883 if (mips_opts
.isa
!= ISA_MIPS1
)
6885 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6886 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6889 breg
= mips_gp_register
;
6890 r
= BFD_RELOC_MIPS_LITERAL
;
6895 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6897 if (mips_pic
!= NO_PIC
)
6898 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6899 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6902 /* FIXME: This won't work for a 64 bit address. */
6903 macro_build_lui (&offset_expr
, AT
);
6906 if (mips_opts
.isa
!= ISA_MIPS1
)
6908 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6909 treg
, BFD_RELOC_LO16
, AT
);
6918 /* Even on a big endian machine $fn comes before $fn+1. We have
6919 to adjust when loading from memory. */
6922 assert (mips_opts
.isa
== ISA_MIPS1
);
6923 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6924 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6925 /* FIXME: A possible overflow which I don't know how to deal
6927 offset_expr
.X_add_number
+= 4;
6928 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6929 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6934 * The MIPS assembler seems to check for X_add_number not
6935 * being double aligned and generating:
6938 * addiu at,at,%lo(foo+1)
6941 * But, the resulting address is the same after relocation so why
6942 * generate the extra instruction?
6944 /* Itbl support may require additional care here. */
6946 if (mips_opts
.isa
!= ISA_MIPS1
)
6957 if (mips_opts
.isa
!= ISA_MIPS1
)
6965 /* Itbl support may require additional care here. */
6970 if (HAVE_64BIT_GPRS
)
6981 if (HAVE_64BIT_GPRS
)
6991 if (offset_expr
.X_op
!= O_symbol
6992 && offset_expr
.X_op
!= O_constant
)
6994 as_bad (_("expression too complex"));
6995 offset_expr
.X_op
= O_constant
;
6998 if (HAVE_32BIT_ADDRESSES
6999 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
7003 sprintf_vma (value
, offset_expr
.X_add_number
);
7004 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
7007 /* Even on a big endian machine $fn comes before $fn+1. We have
7008 to adjust when loading from memory. We set coproc if we must
7009 load $fn+1 first. */
7010 /* Itbl support may require additional care here. */
7011 if (! target_big_endian
)
7014 if (mips_pic
== NO_PIC
7015 || offset_expr
.X_op
== O_constant
)
7017 /* If this is a reference to a GP relative symbol, we want
7018 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
7019 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
7020 If we have a base register, we use this
7022 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
7023 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
7024 If this is not a GP relative symbol, we want
7025 lui $at,<sym> (BFD_RELOC_HI16_S)
7026 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7027 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7028 If there is a base register, we add it to $at after the
7029 lui instruction. If there is a constant, we always use
7031 if (offset_expr
.X_op
== O_symbol
7032 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
7033 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
7035 relax_start (offset_expr
.X_add_symbol
);
7038 tempreg
= mips_gp_register
;
7042 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7043 AT
, breg
, mips_gp_register
);
7048 /* Itbl support may require additional care here. */
7049 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7050 BFD_RELOC_GPREL16
, tempreg
);
7051 offset_expr
.X_add_number
+= 4;
7053 /* Set mips_optimize to 2 to avoid inserting an
7055 hold_mips_optimize
= mips_optimize
;
7057 /* Itbl support may require additional care here. */
7058 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7059 BFD_RELOC_GPREL16
, tempreg
);
7060 mips_optimize
= hold_mips_optimize
;
7064 /* We just generated two relocs. When tc_gen_reloc
7065 handles this case, it will skip the first reloc and
7066 handle the second. The second reloc already has an
7067 extra addend of 4, which we added above. We must
7068 subtract it out, and then subtract another 4 to make
7069 the first reloc come out right. The second reloc
7070 will come out right because we are going to add 4 to
7071 offset_expr when we build its instruction below.
7073 If we have a symbol, then we don't want to include
7074 the offset, because it will wind up being included
7075 when we generate the reloc. */
7077 if (offset_expr
.X_op
== O_constant
)
7078 offset_expr
.X_add_number
-= 8;
7081 offset_expr
.X_add_number
= -4;
7082 offset_expr
.X_op
= O_constant
;
7086 macro_build_lui (&offset_expr
, AT
);
7088 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7089 /* Itbl support may require additional care here. */
7090 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7091 BFD_RELOC_LO16
, AT
);
7092 /* FIXME: How do we handle overflow here? */
7093 offset_expr
.X_add_number
+= 4;
7094 /* Itbl support may require additional care here. */
7095 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7096 BFD_RELOC_LO16
, AT
);
7097 if (mips_relax
.sequence
)
7100 else if (!mips_big_got
)
7102 /* If this is a reference to an external symbol, we want
7103 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7108 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7110 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7111 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7112 If there is a base register we add it to $at before the
7113 lwc1 instructions. If there is a constant we include it
7114 in the lwc1 instructions. */
7116 expr1
.X_add_number
= offset_expr
.X_add_number
;
7117 if (expr1
.X_add_number
< -0x8000
7118 || expr1
.X_add_number
>= 0x8000 - 4)
7119 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7120 load_got_offset (AT
, &offset_expr
);
7123 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7125 /* Set mips_optimize to 2 to avoid inserting an undesired
7127 hold_mips_optimize
= mips_optimize
;
7130 /* Itbl support may require additional care here. */
7131 relax_start (offset_expr
.X_add_symbol
);
7132 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7133 BFD_RELOC_LO16
, AT
);
7134 expr1
.X_add_number
+= 4;
7135 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7136 BFD_RELOC_LO16
, AT
);
7138 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7139 BFD_RELOC_LO16
, AT
);
7140 offset_expr
.X_add_number
+= 4;
7141 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7142 BFD_RELOC_LO16
, AT
);
7145 mips_optimize
= hold_mips_optimize
;
7147 else if (mips_big_got
)
7151 /* If this is a reference to an external symbol, we want
7152 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
7154 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
7159 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
7161 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
7162 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
7163 If there is a base register we add it to $at before the
7164 lwc1 instructions. If there is a constant we include it
7165 in the lwc1 instructions. */
7167 expr1
.X_add_number
= offset_expr
.X_add_number
;
7168 offset_expr
.X_add_number
= 0;
7169 if (expr1
.X_add_number
< -0x8000
7170 || expr1
.X_add_number
>= 0x8000 - 4)
7171 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
7172 gpdelay
= reg_needs_delay (mips_gp_register
);
7173 relax_start (offset_expr
.X_add_symbol
);
7174 macro_build (&offset_expr
, "lui", "t,u",
7175 AT
, BFD_RELOC_MIPS_GOT_HI16
);
7176 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
7177 AT
, AT
, mips_gp_register
);
7178 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
7179 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
7182 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7183 /* Itbl support may require additional care here. */
7184 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7185 BFD_RELOC_LO16
, AT
);
7186 expr1
.X_add_number
+= 4;
7188 /* Set mips_optimize to 2 to avoid inserting an undesired
7190 hold_mips_optimize
= mips_optimize
;
7192 /* Itbl support may require additional care here. */
7193 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
7194 BFD_RELOC_LO16
, AT
);
7195 mips_optimize
= hold_mips_optimize
;
7196 expr1
.X_add_number
-= 4;
7199 offset_expr
.X_add_number
= expr1
.X_add_number
;
7201 macro_build (NULL
, "nop", "");
7202 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
7203 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
7206 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
7207 /* Itbl support may require additional care here. */
7208 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
7209 BFD_RELOC_LO16
, AT
);
7210 offset_expr
.X_add_number
+= 4;
7212 /* Set mips_optimize to 2 to avoid inserting an undesired
7214 hold_mips_optimize
= mips_optimize
;
7216 /* Itbl support may require additional care here. */
7217 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
7218 BFD_RELOC_LO16
, AT
);
7219 mips_optimize
= hold_mips_optimize
;
7233 assert (HAVE_32BIT_ADDRESSES
);
7234 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7235 offset_expr
.X_add_number
+= 4;
7236 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
7239 /* New code added to support COPZ instructions.
7240 This code builds table entries out of the macros in mip_opcodes.
7241 R4000 uses interlocks to handle coproc delays.
7242 Other chips (like the R3000) require nops to be inserted for delays.
7244 FIXME: Currently, we require that the user handle delays.
7245 In order to fill delay slots for non-interlocked chips,
7246 we must have a way to specify delays based on the coprocessor.
7247 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7248 What are the side-effects of the cop instruction?
7249 What cache support might we have and what are its effects?
7250 Both coprocessor & memory require delays. how long???
7251 What registers are read/set/modified?
7253 If an itbl is provided to interpret cop instructions,
7254 this knowledge can be encoded in the itbl spec. */
7268 if (NO_ISA_COP (mips_opts
.arch
)
7269 && (ip
->insn_mo
->pinfo2
& INSN2_M_FP_S
) == 0)
7271 as_bad (_("opcode not supported on this processor: %s"),
7272 mips_cpu_info_from_arch (mips_opts
.arch
)->name
);
7276 /* For now we just do C (same as Cz). The parameter will be
7277 stored in insn_opcode by mips_ip. */
7278 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7282 move_register (dreg
, sreg
);
7285 #ifdef LOSING_COMPILER
7287 /* Try and see if this is a new itbl instruction.
7288 This code builds table entries out of the macros in mip_opcodes.
7289 FIXME: For now we just assemble the expression and pass it's
7290 value along as a 32-bit immediate.
7291 We may want to have the assembler assemble this value,
7292 so that we gain the assembler's knowledge of delay slots,
7294 Would it be more efficient to use mask (id) here? */
7295 if (itbl_have_entries
7296 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7298 s
= ip
->insn_mo
->name
;
7300 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7301 macro_build (&immed_expr
, s
, "C");
7307 if (!mips_opts
.at
&& used_at
)
7308 as_bad (_("Macro used $at after \".set noat\""));
7312 macro2 (struct mips_cl_insn
*ip
)
7314 unsigned int treg
, sreg
, dreg
, breg
;
7315 unsigned int tempreg
;
7329 bfd_reloc_code_real_type r
;
7331 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7332 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7333 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7334 mask
= ip
->insn_mo
->mask
;
7336 expr1
.X_op
= O_constant
;
7337 expr1
.X_op_symbol
= NULL
;
7338 expr1
.X_add_symbol
= NULL
;
7339 expr1
.X_add_number
= 1;
7343 #endif /* LOSING_COMPILER */
7348 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7349 macro_build (NULL
, "mflo", "d", dreg
);
7355 /* The MIPS assembler some times generates shifts and adds. I'm
7356 not trying to be that fancy. GCC should do this for us
7359 load_register (AT
, &imm_expr
, dbl
);
7360 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7361 macro_build (NULL
, "mflo", "d", dreg
);
7377 load_register (AT
, &imm_expr
, dbl
);
7378 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7379 macro_build (NULL
, "mflo", "d", dreg
);
7380 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7381 macro_build (NULL
, "mfhi", "d", AT
);
7383 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7386 expr1
.X_add_number
= 8;
7387 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7388 macro_build (NULL
, "nop", "", 0);
7389 macro_build (NULL
, "break", "c", 6);
7392 macro_build (NULL
, "mflo", "d", dreg
);
7408 load_register (AT
, &imm_expr
, dbl
);
7409 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7410 sreg
, imm
? AT
: treg
);
7411 macro_build (NULL
, "mfhi", "d", AT
);
7412 macro_build (NULL
, "mflo", "d", dreg
);
7414 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7417 expr1
.X_add_number
= 8;
7418 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7419 macro_build (NULL
, "nop", "", 0);
7420 macro_build (NULL
, "break", "c", 6);
7426 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7437 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7438 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7442 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7443 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7444 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7445 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7449 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7460 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7461 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7465 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7466 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7467 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7468 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7476 if (imm_expr
.X_op
!= O_constant
)
7477 as_bad (_("Improper rotate count"));
7478 rot
= imm_expr
.X_add_number
& 0x3f;
7479 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7481 rot
= (64 - rot
) & 0x3f;
7483 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7485 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7490 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7493 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7494 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7497 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7498 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7499 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7507 if (imm_expr
.X_op
!= O_constant
)
7508 as_bad (_("Improper rotate count"));
7509 rot
= imm_expr
.X_add_number
& 0x1f;
7510 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7512 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7517 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7521 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7522 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7523 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7528 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7530 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7534 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7535 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7536 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7537 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7541 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7543 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7547 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7548 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7549 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7550 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7558 if (imm_expr
.X_op
!= O_constant
)
7559 as_bad (_("Improper rotate count"));
7560 rot
= imm_expr
.X_add_number
& 0x3f;
7561 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7564 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7566 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7571 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7574 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7575 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7578 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7579 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7580 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7588 if (imm_expr
.X_op
!= O_constant
)
7589 as_bad (_("Improper rotate count"));
7590 rot
= imm_expr
.X_add_number
& 0x1f;
7591 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7593 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7598 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7602 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7603 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7604 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7609 assert (mips_opts
.isa
== ISA_MIPS1
);
7610 /* Even on a big endian machine $fn comes before $fn+1. We have
7611 to adjust when storing to memory. */
7612 macro_build (&offset_expr
, "swc1", "T,o(b)",
7613 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7614 offset_expr
.X_add_number
+= 4;
7615 macro_build (&offset_expr
, "swc1", "T,o(b)",
7616 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7621 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7623 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7626 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7627 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7632 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7634 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7639 as_warn (_("Instruction %s: result is always false"),
7641 move_register (dreg
, 0);
7644 if (CPU_HAS_SEQ (mips_opts
.arch
)
7645 && -512 <= imm_expr
.X_add_number
7646 && imm_expr
.X_add_number
< 512)
7648 macro_build (NULL
, "seqi", "t,r,+Q", dreg
, sreg
,
7649 (int) imm_expr
.X_add_number
);
7652 if (imm_expr
.X_op
== O_constant
7653 && imm_expr
.X_add_number
>= 0
7654 && imm_expr
.X_add_number
< 0x10000)
7656 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7658 else if (imm_expr
.X_op
== O_constant
7659 && imm_expr
.X_add_number
> -0x8000
7660 && imm_expr
.X_add_number
< 0)
7662 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7663 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7664 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7666 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7669 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7670 macro_build (NULL
, "seq", "d,v,t", dreg
, sreg
, AT
);
7675 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7676 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7679 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7682 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7688 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7689 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7692 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7694 if (imm_expr
.X_op
== O_constant
7695 && imm_expr
.X_add_number
>= -0x8000
7696 && imm_expr
.X_add_number
< 0x8000)
7698 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7699 dreg
, sreg
, BFD_RELOC_LO16
);
7703 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7704 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7708 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7711 case M_SGT
: /* sreg > treg <==> treg < sreg */
7717 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7720 case M_SGT_I
: /* sreg > I <==> I < sreg */
7727 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7728 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7731 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7737 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7738 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7741 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7748 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7749 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7750 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7754 if (imm_expr
.X_op
== O_constant
7755 && imm_expr
.X_add_number
>= -0x8000
7756 && imm_expr
.X_add_number
< 0x8000)
7758 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7762 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7763 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7767 if (imm_expr
.X_op
== O_constant
7768 && imm_expr
.X_add_number
>= -0x8000
7769 && imm_expr
.X_add_number
< 0x8000)
7771 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7776 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7777 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7782 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7784 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7787 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7788 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7793 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7795 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7800 as_warn (_("Instruction %s: result is always true"),
7802 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7803 dreg
, 0, BFD_RELOC_LO16
);
7806 if (CPU_HAS_SEQ (mips_opts
.arch
)
7807 && -512 <= imm_expr
.X_add_number
7808 && imm_expr
.X_add_number
< 512)
7810 macro_build (NULL
, "snei", "t,r,+Q", dreg
, sreg
,
7811 (int) imm_expr
.X_add_number
);
7814 if (imm_expr
.X_op
== O_constant
7815 && imm_expr
.X_add_number
>= 0
7816 && imm_expr
.X_add_number
< 0x10000)
7818 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7820 else if (imm_expr
.X_op
== O_constant
7821 && imm_expr
.X_add_number
> -0x8000
7822 && imm_expr
.X_add_number
< 0)
7824 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7825 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7826 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7828 else if (CPU_HAS_SEQ (mips_opts
.arch
))
7831 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7832 macro_build (NULL
, "sne", "d,v,t", dreg
, sreg
, AT
);
7837 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7838 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7841 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7847 if (imm_expr
.X_op
== O_constant
7848 && imm_expr
.X_add_number
> -0x8000
7849 && imm_expr
.X_add_number
<= 0x8000)
7851 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7852 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7853 dreg
, sreg
, BFD_RELOC_LO16
);
7857 load_register (AT
, &imm_expr
, dbl
);
7858 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7864 if (imm_expr
.X_op
== O_constant
7865 && imm_expr
.X_add_number
> -0x8000
7866 && imm_expr
.X_add_number
<= 0x8000)
7868 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7869 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7870 dreg
, sreg
, BFD_RELOC_LO16
);
7874 load_register (AT
, &imm_expr
, dbl
);
7875 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7897 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7898 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7903 assert (mips_opts
.isa
== ISA_MIPS1
);
7905 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7906 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7909 * Is the double cfc1 instruction a bug in the mips assembler;
7910 * or is there a reason for it?
7913 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7914 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7915 macro_build (NULL
, "nop", "");
7916 expr1
.X_add_number
= 3;
7917 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7918 expr1
.X_add_number
= 2;
7919 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7920 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7921 macro_build (NULL
, "nop", "");
7922 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7924 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7925 macro_build (NULL
, "nop", "");
7936 if (offset_expr
.X_add_number
>= 0x7fff)
7937 as_bad (_("operand overflow"));
7938 if (! target_big_endian
)
7939 ++offset_expr
.X_add_number
;
7940 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7941 if (! target_big_endian
)
7942 --offset_expr
.X_add_number
;
7944 ++offset_expr
.X_add_number
;
7945 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7946 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7947 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7960 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7961 as_bad (_("operand overflow"));
7969 if (! target_big_endian
)
7970 offset_expr
.X_add_number
+= off
;
7971 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7972 if (! target_big_endian
)
7973 offset_expr
.X_add_number
-= off
;
7975 offset_expr
.X_add_number
+= off
;
7976 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7978 /* If necessary, move the result in tempreg the final destination. */
7979 if (treg
== tempreg
)
7981 /* Protect second load's delay slot. */
7983 move_register (treg
, tempreg
);
7997 load_address (AT
, &offset_expr
, &used_at
);
7999 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8000 if (! target_big_endian
)
8001 expr1
.X_add_number
= off
;
8003 expr1
.X_add_number
= 0;
8004 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8005 if (! target_big_endian
)
8006 expr1
.X_add_number
= 0;
8008 expr1
.X_add_number
= off
;
8009 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8015 load_address (AT
, &offset_expr
, &used_at
);
8017 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8018 if (target_big_endian
)
8019 expr1
.X_add_number
= 0;
8020 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
8021 treg
, BFD_RELOC_LO16
, AT
);
8022 if (target_big_endian
)
8023 expr1
.X_add_number
= 1;
8025 expr1
.X_add_number
= 0;
8026 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8027 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8028 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8033 if (offset_expr
.X_add_number
>= 0x7fff)
8034 as_bad (_("operand overflow"));
8035 if (target_big_endian
)
8036 ++offset_expr
.X_add_number
;
8037 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8038 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
8039 if (target_big_endian
)
8040 --offset_expr
.X_add_number
;
8042 ++offset_expr
.X_add_number
;
8043 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
8056 if (offset_expr
.X_add_number
>= 0x8000 - off
)
8057 as_bad (_("operand overflow"));
8058 if (! target_big_endian
)
8059 offset_expr
.X_add_number
+= off
;
8060 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8061 if (! target_big_endian
)
8062 offset_expr
.X_add_number
-= off
;
8064 offset_expr
.X_add_number
+= off
;
8065 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
8079 load_address (AT
, &offset_expr
, &used_at
);
8081 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8082 if (! target_big_endian
)
8083 expr1
.X_add_number
= off
;
8085 expr1
.X_add_number
= 0;
8086 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8087 if (! target_big_endian
)
8088 expr1
.X_add_number
= 0;
8090 expr1
.X_add_number
= off
;
8091 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8096 load_address (AT
, &offset_expr
, &used_at
);
8098 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
8099 if (! target_big_endian
)
8100 expr1
.X_add_number
= 0;
8101 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8102 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
8103 if (! target_big_endian
)
8104 expr1
.X_add_number
= 1;
8106 expr1
.X_add_number
= 0;
8107 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
8108 if (! target_big_endian
)
8109 expr1
.X_add_number
= 0;
8111 expr1
.X_add_number
= 1;
8112 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
8113 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
8114 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
8118 /* FIXME: Check if this is one of the itbl macros, since they
8119 are added dynamically. */
8120 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
8123 if (!mips_opts
.at
&& used_at
)
8124 as_bad (_("Macro used $at after \".set noat\""));
8127 /* Implement macros in mips16 mode. */
8130 mips16_macro (struct mips_cl_insn
*ip
)
8133 int xreg
, yreg
, zreg
, tmp
;
8136 const char *s
, *s2
, *s3
;
8138 mask
= ip
->insn_mo
->mask
;
8140 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
8141 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
8142 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
8144 expr1
.X_op
= O_constant
;
8145 expr1
.X_op_symbol
= NULL
;
8146 expr1
.X_add_symbol
= NULL
;
8147 expr1
.X_add_number
= 1;
8167 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
8168 expr1
.X_add_number
= 2;
8169 macro_build (&expr1
, "bnez", "x,p", yreg
);
8170 macro_build (NULL
, "break", "6", 7);
8172 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
8173 since that causes an overflow. We should do that as well,
8174 but I don't see how to do the comparisons without a temporary
8177 macro_build (NULL
, s
, "x", zreg
);
8197 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
8198 expr1
.X_add_number
= 2;
8199 macro_build (&expr1
, "bnez", "x,p", yreg
);
8200 macro_build (NULL
, "break", "6", 7);
8202 macro_build (NULL
, s2
, "x", zreg
);
8208 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
8209 macro_build (NULL
, "mflo", "x", zreg
);
8217 if (imm_expr
.X_op
!= O_constant
)
8218 as_bad (_("Unsupported large constant"));
8219 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8220 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
8224 if (imm_expr
.X_op
!= O_constant
)
8225 as_bad (_("Unsupported large constant"));
8226 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8227 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
8231 if (imm_expr
.X_op
!= O_constant
)
8232 as_bad (_("Unsupported large constant"));
8233 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
8234 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
8256 goto do_reverse_branch
;
8260 goto do_reverse_branch
;
8272 goto do_reverse_branch
;
8283 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8284 macro_build (&offset_expr
, s2
, "p");
8311 goto do_addone_branch_i
;
8316 goto do_addone_branch_i
;
8331 goto do_addone_branch_i
;
8338 if (imm_expr
.X_op
!= O_constant
)
8339 as_bad (_("Unsupported large constant"));
8340 ++imm_expr
.X_add_number
;
8343 macro_build (&imm_expr
, s
, s3
, xreg
);
8344 macro_build (&offset_expr
, s2
, "p");
8348 expr1
.X_add_number
= 0;
8349 macro_build (&expr1
, "slti", "x,8", yreg
);
8351 move_register (xreg
, yreg
);
8352 expr1
.X_add_number
= 2;
8353 macro_build (&expr1
, "bteqz", "p");
8354 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8358 /* For consistency checking, verify that all bits are specified either
8359 by the match/mask part of the instruction definition, or by the
8362 validate_mips_insn (const struct mips_opcode
*opc
)
8364 const char *p
= opc
->args
;
8366 unsigned long used_bits
= opc
->mask
;
8368 if ((used_bits
& opc
->match
) != opc
->match
)
8370 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8371 opc
->name
, opc
->args
);
8374 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8384 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8385 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8386 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8387 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8388 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8389 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8390 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8391 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8392 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8393 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8394 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8395 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8396 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8398 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8399 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8400 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8401 case 'x': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8402 case 'X': USE_BITS (OP_MASK_BBITIND
, OP_SH_BBITIND
); break;
8403 case 'p': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8404 case 'P': USE_BITS (OP_MASK_CINSPOS
, OP_SH_CINSPOS
); break;
8405 case 'Q': USE_BITS (OP_MASK_SEQI
, OP_SH_SEQI
); break;
8406 case 's': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8407 case 'S': USE_BITS (OP_MASK_CINSLM1
, OP_SH_CINSLM1
); break;
8410 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8411 c
, opc
->name
, opc
->args
);
8415 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8416 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8418 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8419 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8420 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8421 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8423 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8424 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8426 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8427 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8429 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8430 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8431 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8432 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8433 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8434 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8435 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8436 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8437 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8438 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8439 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8440 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8441 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8442 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8443 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8444 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8445 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8447 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8448 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8449 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8450 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8452 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8453 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8454 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8455 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8456 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8457 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8458 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8459 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8460 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8463 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8464 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8465 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8466 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8467 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8470 case '1': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8471 case '2': USE_BITS (OP_MASK_BP
, OP_SH_BP
); break;
8472 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8473 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8474 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8475 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8476 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8477 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8478 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8479 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8480 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8481 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8482 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8483 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8484 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8485 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8486 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8487 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8489 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8490 c
, opc
->name
, opc
->args
);
8494 if (used_bits
!= 0xffffffff)
8496 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8497 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8503 /* UDI immediates. */
8511 static const struct mips_immed mips_immed
[] = {
8512 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8513 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8514 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8515 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8519 /* Check whether an odd floating-point register is allowed. */
8521 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8523 const char *s
= insn
->name
;
8525 if (insn
->pinfo
== INSN_MACRO
)
8526 /* Let a macro pass, we'll catch it later when it is expanded. */
8529 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8531 /* Allow odd registers for single-precision ops. */
8532 switch (insn
->pinfo
& (FP_S
| FP_D
))
8536 return 1; /* both single precision - ok */
8538 return 0; /* both double precision - fail */
8543 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8544 s
= strchr (insn
->name
, '.');
8546 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8547 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8550 /* Single-precision coprocessor loads and moves are OK too. */
8551 if ((insn
->pinfo
& FP_S
)
8552 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8553 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8559 /* This routine assembles an instruction into its binary format. As a
8560 side effect, it sets one of the global variables imm_reloc or
8561 offset_reloc to the type of relocation to do if one of the operands
8562 is an address expression. */
8565 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8570 struct mips_opcode
*insn
;
8573 unsigned int lastregno
= 0;
8574 unsigned int lastpos
= 0;
8575 unsigned int limlo
, limhi
;
8578 offsetT min_range
, max_range
;
8584 /* If the instruction contains a '.', we first try to match an instruction
8585 including the '.'. Then we try again without the '.'. */
8587 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8590 /* If we stopped on whitespace, then replace the whitespace with null for
8591 the call to hash_find. Save the character we replaced just in case we
8592 have to re-parse the instruction. */
8599 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8601 /* If we didn't find the instruction in the opcode table, try again, but
8602 this time with just the instruction up to, but not including the
8606 /* Restore the character we overwrite above (if any). */
8610 /* Scan up to the first '.' or whitespace. */
8612 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8616 /* If we did not find a '.', then we can quit now. */
8619 insn_error
= "unrecognized opcode";
8623 /* Lookup the instruction in the hash table. */
8625 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8627 insn_error
= "unrecognized opcode";
8637 assert (strcmp (insn
->name
, str
) == 0);
8639 ok
= is_opcode_valid (insn
, FALSE
);
8642 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8643 && strcmp (insn
->name
, insn
[1].name
) == 0)
8652 static char buf
[100];
8654 _("opcode not supported on this processor: %s (%s)"),
8655 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8656 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8665 create_insn (ip
, insn
);
8668 lastregno
= 0xffffffff;
8669 for (args
= insn
->args
;; ++args
)
8673 s
+= strspn (s
, " \t");
8677 case '\0': /* end of args */
8682 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8683 my_getExpression (&imm_expr
, s
);
8684 check_absolute_expr (ip
, &imm_expr
);
8685 if ((unsigned long) imm_expr
.X_add_number
!= 1
8686 && (unsigned long) imm_expr
.X_add_number
!= 3)
8688 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8689 (unsigned long) imm_expr
.X_add_number
);
8691 INSERT_OPERAND (BP
, *ip
, imm_expr
.X_add_number
);
8692 imm_expr
.X_op
= O_absent
;
8696 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8697 my_getExpression (&imm_expr
, s
);
8698 check_absolute_expr (ip
, &imm_expr
);
8699 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8701 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8702 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8704 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8705 imm_expr
.X_op
= O_absent
;
8709 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8710 my_getExpression (&imm_expr
, s
);
8711 check_absolute_expr (ip
, &imm_expr
);
8712 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8714 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8715 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8717 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8718 imm_expr
.X_op
= O_absent
;
8722 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8723 my_getExpression (&imm_expr
, s
);
8724 check_absolute_expr (ip
, &imm_expr
);
8725 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8727 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8728 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8730 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8731 imm_expr
.X_op
= O_absent
;
8735 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8736 my_getExpression (&imm_expr
, s
);
8737 check_absolute_expr (ip
, &imm_expr
);
8738 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8740 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8741 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8743 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8744 imm_expr
.X_op
= O_absent
;
8748 case '7': /* four dsp accumulators in bits 11,12 */
8749 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8750 s
[3] >= '0' && s
[3] <= '3')
8754 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8758 as_bad (_("Invalid dsp acc register"));
8761 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8762 my_getExpression (&imm_expr
, s
);
8763 check_absolute_expr (ip
, &imm_expr
);
8764 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8766 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8768 (unsigned long) imm_expr
.X_add_number
);
8770 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8771 imm_expr
.X_op
= O_absent
;
8775 case '9': /* four dsp accumulators in bits 21,22 */
8776 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8777 s
[3] >= '0' && s
[3] <= '3')
8781 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8785 as_bad (_("Invalid dsp acc register"));
8788 case '0': /* dsp 6-bit signed immediate in bit 20 */
8789 my_getExpression (&imm_expr
, s
);
8790 check_absolute_expr (ip
, &imm_expr
);
8791 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8792 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8793 if (imm_expr
.X_add_number
< min_range
||
8794 imm_expr
.X_add_number
> max_range
)
8796 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8797 (long) min_range
, (long) max_range
,
8798 (long) imm_expr
.X_add_number
);
8800 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8801 imm_expr
.X_op
= O_absent
;
8805 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8806 my_getExpression (&imm_expr
, s
);
8807 check_absolute_expr (ip
, &imm_expr
);
8808 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8810 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8812 (unsigned long) imm_expr
.X_add_number
);
8814 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8815 imm_expr
.X_op
= O_absent
;
8819 case ':': /* dsp 7-bit signed immediate in bit 19 */
8820 my_getExpression (&imm_expr
, s
);
8821 check_absolute_expr (ip
, &imm_expr
);
8822 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8823 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8824 if (imm_expr
.X_add_number
< min_range
||
8825 imm_expr
.X_add_number
> max_range
)
8827 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8828 (long) min_range
, (long) max_range
,
8829 (long) imm_expr
.X_add_number
);
8831 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8832 imm_expr
.X_op
= O_absent
;
8836 case '@': /* dsp 10-bit signed immediate in bit 16 */
8837 my_getExpression (&imm_expr
, s
);
8838 check_absolute_expr (ip
, &imm_expr
);
8839 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8840 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8841 if (imm_expr
.X_add_number
< min_range
||
8842 imm_expr
.X_add_number
> max_range
)
8844 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8845 (long) min_range
, (long) max_range
,
8846 (long) imm_expr
.X_add_number
);
8848 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8849 imm_expr
.X_op
= O_absent
;
8853 case '!': /* MT usermode flag bit. */
8854 my_getExpression (&imm_expr
, s
);
8855 check_absolute_expr (ip
, &imm_expr
);
8856 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8857 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8858 (unsigned long) imm_expr
.X_add_number
);
8859 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8860 imm_expr
.X_op
= O_absent
;
8864 case '$': /* MT load high flag bit. */
8865 my_getExpression (&imm_expr
, s
);
8866 check_absolute_expr (ip
, &imm_expr
);
8867 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8868 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8869 (unsigned long) imm_expr
.X_add_number
);
8870 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8871 imm_expr
.X_op
= O_absent
;
8875 case '*': /* four dsp accumulators in bits 18,19 */
8876 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8877 s
[3] >= '0' && s
[3] <= '3')
8881 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8885 as_bad (_("Invalid dsp/smartmips acc register"));
8888 case '&': /* four dsp accumulators in bits 13,14 */
8889 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8890 s
[3] >= '0' && s
[3] <= '3')
8894 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8898 as_bad (_("Invalid dsp/smartmips acc register"));
8910 INSERT_OPERAND (RS
, *ip
, lastregno
);
8914 INSERT_OPERAND (RT
, *ip
, lastregno
);
8918 INSERT_OPERAND (FT
, *ip
, lastregno
);
8922 INSERT_OPERAND (FS
, *ip
, lastregno
);
8928 /* Handle optional base register.
8929 Either the base register is omitted or
8930 we must have a left paren. */
8931 /* This is dependent on the next operand specifier
8932 is a base register specification. */
8933 assert (args
[1] == 'b' || args
[1] == '5'
8934 || args
[1] == '-' || args
[1] == '4');
8938 case ')': /* these must match exactly */
8945 case '+': /* Opcode extension character. */
8948 case '1': /* UDI immediates. */
8953 const struct mips_immed
*imm
= mips_immed
;
8955 while (imm
->type
&& imm
->type
!= *args
)
8959 my_getExpression (&imm_expr
, s
);
8960 check_absolute_expr (ip
, &imm_expr
);
8961 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8963 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8964 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8965 (unsigned long) imm_expr
.X_add_number
,
8966 (unsigned long) imm_expr
.X_add_number
);
8967 imm_expr
.X_add_number
&= imm
->mask
;
8969 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8971 imm_expr
.X_op
= O_absent
;
8976 case 'A': /* ins/ext position, becomes LSB. */
8985 my_getExpression (&imm_expr
, s
);
8986 check_absolute_expr (ip
, &imm_expr
);
8987 if ((unsigned long) imm_expr
.X_add_number
< limlo
8988 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8990 as_bad (_("Improper position (%lu)"),
8991 (unsigned long) imm_expr
.X_add_number
);
8992 imm_expr
.X_add_number
= limlo
;
8994 lastpos
= imm_expr
.X_add_number
;
8995 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8996 imm_expr
.X_op
= O_absent
;
9000 case 'B': /* ins size, becomes MSB. */
9009 my_getExpression (&imm_expr
, s
);
9010 check_absolute_expr (ip
, &imm_expr
);
9011 /* Check for negative input so that small negative numbers
9012 will not succeed incorrectly. The checks against
9013 (pos+size) transitively check "size" itself,
9014 assuming that "pos" is reasonable. */
9015 if ((long) imm_expr
.X_add_number
< 0
9016 || ((unsigned long) imm_expr
.X_add_number
9018 || ((unsigned long) imm_expr
.X_add_number
9021 as_bad (_("Improper insert size (%lu, position %lu)"),
9022 (unsigned long) imm_expr
.X_add_number
,
9023 (unsigned long) lastpos
);
9024 imm_expr
.X_add_number
= limlo
- lastpos
;
9026 INSERT_OPERAND (INSMSB
, *ip
,
9027 lastpos
+ imm_expr
.X_add_number
- 1);
9028 imm_expr
.X_op
= O_absent
;
9032 case 'C': /* ext size, becomes MSBD. */
9045 my_getExpression (&imm_expr
, s
);
9046 check_absolute_expr (ip
, &imm_expr
);
9047 /* Check for negative input so that small negative numbers
9048 will not succeed incorrectly. The checks against
9049 (pos+size) transitively check "size" itself,
9050 assuming that "pos" is reasonable. */
9051 if ((long) imm_expr
.X_add_number
< 0
9052 || ((unsigned long) imm_expr
.X_add_number
9054 || ((unsigned long) imm_expr
.X_add_number
9057 as_bad (_("Improper extract size (%lu, position %lu)"),
9058 (unsigned long) imm_expr
.X_add_number
,
9059 (unsigned long) lastpos
);
9060 imm_expr
.X_add_number
= limlo
- lastpos
;
9062 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
9063 imm_expr
.X_op
= O_absent
;
9068 /* +D is for disassembly only; never match. */
9072 /* "+I" is like "I", except that imm2_expr is used. */
9073 my_getExpression (&imm2_expr
, s
);
9074 if (imm2_expr
.X_op
!= O_big
9075 && imm2_expr
.X_op
!= O_constant
)
9076 insn_error
= _("absolute expression required");
9077 if (HAVE_32BIT_GPRS
)
9078 normalize_constant_expr (&imm2_expr
);
9082 case 'T': /* Coprocessor register. */
9083 /* +T is for disassembly only; never match. */
9086 case 't': /* Coprocessor register number. */
9087 if (s
[0] == '$' && ISDIGIT (s
[1]))
9097 while (ISDIGIT (*s
));
9099 as_bad (_("Invalid register number (%d)"), regno
);
9102 INSERT_OPERAND (RT
, *ip
, regno
);
9107 as_bad (_("Invalid coprocessor 0 register number"));
9111 /* bbit[01] and bbit[01]32 bit index. Give error if index
9112 is not in the valid range. */
9113 my_getExpression (&imm_expr
, s
);
9114 check_absolute_expr (ip
, &imm_expr
);
9115 if ((unsigned) imm_expr
.X_add_number
> 31)
9117 as_bad (_("Improper bit index (%lu)"),
9118 (unsigned long) imm_expr
.X_add_number
);
9119 imm_expr
.X_add_number
= 0;
9121 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
);
9122 imm_expr
.X_op
= O_absent
;
9127 /* bbit[01] bit index when bbit is used but we generate
9128 bbit[01]32 because the index is over 32. Move to the
9129 next candidate if index is not in the valid range. */
9130 my_getExpression (&imm_expr
, s
);
9131 check_absolute_expr (ip
, &imm_expr
);
9132 if ((unsigned) imm_expr
.X_add_number
< 32
9133 || (unsigned) imm_expr
.X_add_number
> 63)
9135 INSERT_OPERAND (BBITIND
, *ip
, imm_expr
.X_add_number
- 32);
9136 imm_expr
.X_op
= O_absent
;
9141 /* cins, cins32, exts and exts32 position field. Give error
9142 if it's not in the valid range. */
9143 my_getExpression (&imm_expr
, s
);
9144 check_absolute_expr (ip
, &imm_expr
);
9145 if ((unsigned) imm_expr
.X_add_number
> 31)
9147 as_bad (_("Improper position (%lu)"),
9148 (unsigned long) imm_expr
.X_add_number
);
9149 imm_expr
.X_add_number
= 0;
9151 /* Make the pos explicit to simplify +S. */
9152 lastpos
= imm_expr
.X_add_number
+ 32;
9153 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
);
9154 imm_expr
.X_op
= O_absent
;
9159 /* cins, cins32, exts and exts32 position field. Move to
9160 the next candidate if it's not in the valid range. */
9161 my_getExpression (&imm_expr
, s
);
9162 check_absolute_expr (ip
, &imm_expr
);
9163 if ((unsigned) imm_expr
.X_add_number
< 32
9164 || (unsigned) imm_expr
.X_add_number
> 63)
9166 lastpos
= imm_expr
.X_add_number
;
9167 INSERT_OPERAND (CINSPOS
, *ip
, imm_expr
.X_add_number
- 32);
9168 imm_expr
.X_op
= O_absent
;
9173 /* cins and exts length-minus-one field. */
9174 my_getExpression (&imm_expr
, s
);
9175 check_absolute_expr (ip
, &imm_expr
);
9176 if ((unsigned long) imm_expr
.X_add_number
> 31)
9178 as_bad (_("Improper size (%lu)"),
9179 (unsigned long) imm_expr
.X_add_number
);
9180 imm_expr
.X_add_number
= 0;
9182 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9183 imm_expr
.X_op
= O_absent
;
9188 /* cins32/exts32 and cins/exts aliasing cint32/exts32
9189 length-minus-one field. */
9190 my_getExpression (&imm_expr
, s
);
9191 check_absolute_expr (ip
, &imm_expr
);
9192 if ((long) imm_expr
.X_add_number
< 0
9193 || (unsigned long) imm_expr
.X_add_number
+ lastpos
> 63)
9195 as_bad (_("Improper size (%lu)"),
9196 (unsigned long) imm_expr
.X_add_number
);
9197 imm_expr
.X_add_number
= 0;
9199 INSERT_OPERAND (CINSLM1
, *ip
, imm_expr
.X_add_number
);
9200 imm_expr
.X_op
= O_absent
;
9205 /* seqi/snei immediate field. */
9206 my_getExpression (&imm_expr
, s
);
9207 check_absolute_expr (ip
, &imm_expr
);
9208 if ((long) imm_expr
.X_add_number
< -512
9209 || (long) imm_expr
.X_add_number
>= 512)
9211 as_bad (_("Improper immediate (%ld)"),
9212 (long) imm_expr
.X_add_number
);
9213 imm_expr
.X_add_number
= 0;
9215 INSERT_OPERAND (SEQI
, *ip
, imm_expr
.X_add_number
);
9216 imm_expr
.X_op
= O_absent
;
9221 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
9222 *args
, insn
->name
, insn
->args
);
9223 /* Further processing is fruitless. */
9228 case '<': /* must be at least one digit */
9230 * According to the manual, if the shift amount is greater
9231 * than 31 or less than 0, then the shift amount should be
9232 * mod 32. In reality the mips assembler issues an error.
9233 * We issue a warning and mask out all but the low 5 bits.
9235 my_getExpression (&imm_expr
, s
);
9236 check_absolute_expr (ip
, &imm_expr
);
9237 if ((unsigned long) imm_expr
.X_add_number
> 31)
9238 as_warn (_("Improper shift amount (%lu)"),
9239 (unsigned long) imm_expr
.X_add_number
);
9240 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9241 imm_expr
.X_op
= O_absent
;
9245 case '>': /* shift amount minus 32 */
9246 my_getExpression (&imm_expr
, s
);
9247 check_absolute_expr (ip
, &imm_expr
);
9248 if ((unsigned long) imm_expr
.X_add_number
< 32
9249 || (unsigned long) imm_expr
.X_add_number
> 63)
9251 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
9252 imm_expr
.X_op
= O_absent
;
9256 case 'k': /* cache code */
9257 case 'h': /* prefx code */
9258 case '1': /* sync type */
9259 my_getExpression (&imm_expr
, s
);
9260 check_absolute_expr (ip
, &imm_expr
);
9261 if ((unsigned long) imm_expr
.X_add_number
> 31)
9262 as_warn (_("Invalid value for `%s' (%lu)"),
9264 (unsigned long) imm_expr
.X_add_number
);
9266 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
9267 else if (*args
== 'h')
9268 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
9270 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
9271 imm_expr
.X_op
= O_absent
;
9275 case 'c': /* break code */
9276 my_getExpression (&imm_expr
, s
);
9277 check_absolute_expr (ip
, &imm_expr
);
9278 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
9279 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9281 (unsigned long) imm_expr
.X_add_number
);
9282 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
9283 imm_expr
.X_op
= O_absent
;
9287 case 'q': /* lower break code */
9288 my_getExpression (&imm_expr
, s
);
9289 check_absolute_expr (ip
, &imm_expr
);
9290 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
9291 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9293 (unsigned long) imm_expr
.X_add_number
);
9294 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
9295 imm_expr
.X_op
= O_absent
;
9299 case 'B': /* 20-bit syscall/break code. */
9300 my_getExpression (&imm_expr
, s
);
9301 check_absolute_expr (ip
, &imm_expr
);
9302 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
9303 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9305 (unsigned long) imm_expr
.X_add_number
);
9306 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
9307 imm_expr
.X_op
= O_absent
;
9311 case 'C': /* Coprocessor code */
9312 my_getExpression (&imm_expr
, s
);
9313 check_absolute_expr (ip
, &imm_expr
);
9314 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
9316 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9317 (unsigned long) imm_expr
.X_add_number
);
9318 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
9320 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
9321 imm_expr
.X_op
= O_absent
;
9325 case 'J': /* 19-bit wait code. */
9326 my_getExpression (&imm_expr
, s
);
9327 check_absolute_expr (ip
, &imm_expr
);
9328 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
9330 as_warn (_("Illegal 19-bit code (%lu)"),
9331 (unsigned long) imm_expr
.X_add_number
);
9332 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
9334 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
9335 imm_expr
.X_op
= O_absent
;
9339 case 'P': /* Performance register. */
9340 my_getExpression (&imm_expr
, s
);
9341 check_absolute_expr (ip
, &imm_expr
);
9342 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
9343 as_warn (_("Invalid performance register (%lu)"),
9344 (unsigned long) imm_expr
.X_add_number
);
9345 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
9346 imm_expr
.X_op
= O_absent
;
9350 case 'G': /* Coprocessor destination register. */
9351 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
9352 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
9354 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9355 INSERT_OPERAND (RD
, *ip
, regno
);
9364 case 'b': /* base register */
9365 case 'd': /* destination register */
9366 case 's': /* source register */
9367 case 't': /* target register */
9368 case 'r': /* both target and source */
9369 case 'v': /* both dest and source */
9370 case 'w': /* both dest and target */
9371 case 'E': /* coprocessor target register */
9372 case 'K': /* 'rdhwr' destination register */
9373 case 'x': /* ignore register name */
9374 case 'z': /* must be zero register */
9375 case 'U': /* destination register (clo/clz). */
9376 case 'g': /* coprocessor destination register */
9378 if (*args
== 'E' || *args
== 'K')
9379 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
9382 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
9383 if (regno
== AT
&& mips_opts
.at
)
9385 if (mips_opts
.at
== ATREG
)
9386 as_warn (_("used $at without \".set noat\""));
9388 as_warn (_("used $%u with \".set at=$%u\""),
9389 regno
, mips_opts
.at
);
9399 if (c
== 'r' || c
== 'v' || c
== 'w')
9406 /* 'z' only matches $0. */
9407 if (c
== 'z' && regno
!= 0)
9410 if (c
== 's' && !strncmp (ip
->insn_mo
->name
, "jalr", 4))
9412 if (regno
== lastregno
)
9414 insn_error
= _("source and destination must be different");
9417 if (regno
== 31 && lastregno
== 0xffffffff)
9419 insn_error
= _("a destination register must be supplied");
9423 /* Now that we have assembled one operand, we use the args string
9424 * to figure out where it goes in the instruction. */
9431 INSERT_OPERAND (RS
, *ip
, regno
);
9437 INSERT_OPERAND (RD
, *ip
, regno
);
9440 INSERT_OPERAND (RD
, *ip
, regno
);
9441 INSERT_OPERAND (RT
, *ip
, regno
);
9446 INSERT_OPERAND (RT
, *ip
, regno
);
9449 /* This case exists because on the r3000 trunc
9450 expands into a macro which requires a gp
9451 register. On the r6000 or r4000 it is
9452 assembled into a single instruction which
9453 ignores the register. Thus the insn version
9454 is MIPS_ISA2 and uses 'x', and the macro
9455 version is MIPS_ISA1 and uses 't'. */
9458 /* This case is for the div instruction, which
9459 acts differently if the destination argument
9460 is $0. This only matches $0, and is checked
9461 outside the switch. */
9464 /* Itbl operand; not yet implemented. FIXME ?? */
9466 /* What about all other operands like 'i', which
9467 can be specified in the opcode table? */
9476 INSERT_OPERAND (RS
, *ip
, lastregno
);
9479 INSERT_OPERAND (RT
, *ip
, lastregno
);
9484 case 'O': /* MDMX alignment immediate constant. */
9485 my_getExpression (&imm_expr
, s
);
9486 check_absolute_expr (ip
, &imm_expr
);
9487 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9488 as_warn ("Improper align amount (%ld), using low bits",
9489 (long) imm_expr
.X_add_number
);
9490 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9491 imm_expr
.X_op
= O_absent
;
9495 case 'Q': /* MDMX vector, element sel, or const. */
9498 /* MDMX Immediate. */
9499 my_getExpression (&imm_expr
, s
);
9500 check_absolute_expr (ip
, &imm_expr
);
9501 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9502 as_warn (_("Invalid MDMX Immediate (%ld)"),
9503 (long) imm_expr
.X_add_number
);
9504 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9505 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9506 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9508 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9509 imm_expr
.X_op
= O_absent
;
9513 /* Not MDMX Immediate. Fall through. */
9514 case 'X': /* MDMX destination register. */
9515 case 'Y': /* MDMX source register. */
9516 case 'Z': /* MDMX target register. */
9518 case 'D': /* floating point destination register */
9519 case 'S': /* floating point source register */
9520 case 'T': /* floating point target register */
9521 case 'R': /* floating point source register */
9526 || (mips_opts
.ase_mdmx
9527 && (ip
->insn_mo
->pinfo
& FP_D
)
9528 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9529 | INSN_COPROC_MEMORY_DELAY
9530 | INSN_LOAD_COPROC_DELAY
9531 | INSN_LOAD_MEMORY_DELAY
9532 | INSN_STORE_MEMORY
))))
9535 if (reg_lookup (&s
, rtype
, ®no
))
9537 if ((regno
& 1) != 0
9539 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9540 as_warn (_("Float register should be even, was %d"),
9548 if (c
== 'V' || c
== 'W')
9559 INSERT_OPERAND (FD
, *ip
, regno
);
9564 INSERT_OPERAND (FS
, *ip
, regno
);
9567 /* This is like 'Z', but also needs to fix the MDMX
9568 vector/scalar select bits. Note that the
9569 scalar immediate case is handled above. */
9572 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9573 int max_el
= (is_qh
? 3 : 7);
9575 my_getExpression(&imm_expr
, s
);
9576 check_absolute_expr (ip
, &imm_expr
);
9578 if (imm_expr
.X_add_number
> max_el
)
9579 as_bad(_("Bad element selector %ld"),
9580 (long) imm_expr
.X_add_number
);
9581 imm_expr
.X_add_number
&= max_el
;
9582 ip
->insn_opcode
|= (imm_expr
.X_add_number
9585 imm_expr
.X_op
= O_absent
;
9587 as_warn(_("Expecting ']' found '%s'"), s
);
9593 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9594 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9597 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9604 INSERT_OPERAND (FT
, *ip
, regno
);
9607 INSERT_OPERAND (FR
, *ip
, regno
);
9617 INSERT_OPERAND (FS
, *ip
, lastregno
);
9620 INSERT_OPERAND (FT
, *ip
, lastregno
);
9626 my_getExpression (&imm_expr
, s
);
9627 if (imm_expr
.X_op
!= O_big
9628 && imm_expr
.X_op
!= O_constant
)
9629 insn_error
= _("absolute expression required");
9630 if (HAVE_32BIT_GPRS
)
9631 normalize_constant_expr (&imm_expr
);
9636 my_getExpression (&offset_expr
, s
);
9637 normalize_address_expr (&offset_expr
);
9638 *imm_reloc
= BFD_RELOC_32
;
9651 unsigned char temp
[8];
9653 unsigned int length
;
9658 /* These only appear as the last operand in an
9659 instruction, and every instruction that accepts
9660 them in any variant accepts them in all variants.
9661 This means we don't have to worry about backing out
9662 any changes if the instruction does not match.
9664 The difference between them is the size of the
9665 floating point constant and where it goes. For 'F'
9666 and 'L' the constant is 64 bits; for 'f' and 'l' it
9667 is 32 bits. Where the constant is placed is based
9668 on how the MIPS assembler does things:
9671 f -- immediate value
9674 The .lit4 and .lit8 sections are only used if
9675 permitted by the -G argument.
9677 The code below needs to know whether the target register
9678 is 32 or 64 bits wide. It relies on the fact 'f' and
9679 'F' are used with GPR-based instructions and 'l' and
9680 'L' are used with FPR-based instructions. */
9682 f64
= *args
== 'F' || *args
== 'L';
9683 using_gprs
= *args
== 'F' || *args
== 'f';
9685 save_in
= input_line_pointer
;
9686 input_line_pointer
= s
;
9687 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9689 s
= input_line_pointer
;
9690 input_line_pointer
= save_in
;
9691 if (err
!= NULL
&& *err
!= '\0')
9693 as_bad (_("Bad floating point constant: %s"), err
);
9694 memset (temp
, '\0', sizeof temp
);
9695 length
= f64
? 8 : 4;
9698 assert (length
== (unsigned) (f64
? 8 : 4));
9702 && (g_switch_value
< 4
9703 || (temp
[0] == 0 && temp
[1] == 0)
9704 || (temp
[2] == 0 && temp
[3] == 0))))
9706 imm_expr
.X_op
= O_constant
;
9707 if (! target_big_endian
)
9708 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9710 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9713 && ! mips_disable_float_construction
9714 /* Constants can only be constructed in GPRs and
9715 copied to FPRs if the GPRs are at least as wide
9716 as the FPRs. Force the constant into memory if
9717 we are using 64-bit FPRs but the GPRs are only
9720 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9721 && ((temp
[0] == 0 && temp
[1] == 0)
9722 || (temp
[2] == 0 && temp
[3] == 0))
9723 && ((temp
[4] == 0 && temp
[5] == 0)
9724 || (temp
[6] == 0 && temp
[7] == 0)))
9726 /* The value is simple enough to load with a couple of
9727 instructions. If using 32-bit registers, set
9728 imm_expr to the high order 32 bits and offset_expr to
9729 the low order 32 bits. Otherwise, set imm_expr to
9730 the entire 64 bit constant. */
9731 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9733 imm_expr
.X_op
= O_constant
;
9734 offset_expr
.X_op
= O_constant
;
9735 if (! target_big_endian
)
9737 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9738 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9742 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9743 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9745 if (offset_expr
.X_add_number
== 0)
9746 offset_expr
.X_op
= O_absent
;
9748 else if (sizeof (imm_expr
.X_add_number
) > 4)
9750 imm_expr
.X_op
= O_constant
;
9751 if (! target_big_endian
)
9752 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9754 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9758 imm_expr
.X_op
= O_big
;
9759 imm_expr
.X_add_number
= 4;
9760 if (! target_big_endian
)
9762 generic_bignum
[0] = bfd_getl16 (temp
);
9763 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9764 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9765 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9769 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9770 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9771 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9772 generic_bignum
[3] = bfd_getb16 (temp
);
9778 const char *newname
;
9781 /* Switch to the right section. */
9783 subseg
= now_subseg
;
9786 default: /* unused default case avoids warnings. */
9788 newname
= RDATA_SECTION_NAME
;
9789 if (g_switch_value
>= 8)
9793 newname
= RDATA_SECTION_NAME
;
9796 assert (g_switch_value
>= 4);
9800 new_seg
= subseg_new (newname
, (subsegT
) 0);
9802 bfd_set_section_flags (stdoutput
, new_seg
,
9807 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9808 if (IS_ELF
&& strncmp (TARGET_OS
, "elf", 3) != 0)
9809 record_alignment (new_seg
, 4);
9811 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9813 as_bad (_("Can't use floating point insn in this section"));
9815 /* Set the argument to the current address in the
9817 offset_expr
.X_op
= O_symbol
;
9818 offset_expr
.X_add_symbol
=
9819 symbol_new ("L0\001", now_seg
,
9820 (valueT
) frag_now_fix (), frag_now
);
9821 offset_expr
.X_add_number
= 0;
9823 /* Put the floating point number into the section. */
9824 p
= frag_more ((int) length
);
9825 memcpy (p
, temp
, length
);
9827 /* Switch back to the original section. */
9828 subseg_set (seg
, subseg
);
9833 case 'i': /* 16 bit unsigned immediate */
9834 case 'j': /* 16 bit signed immediate */
9835 *imm_reloc
= BFD_RELOC_LO16
;
9836 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9839 offsetT minval
, maxval
;
9841 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9842 && strcmp (insn
->name
, insn
[1].name
) == 0);
9844 /* If the expression was written as an unsigned number,
9845 only treat it as signed if there are no more
9849 && sizeof (imm_expr
.X_add_number
) <= 4
9850 && imm_expr
.X_op
== O_constant
9851 && imm_expr
.X_add_number
< 0
9852 && imm_expr
.X_unsigned
9856 /* For compatibility with older assemblers, we accept
9857 0x8000-0xffff as signed 16-bit numbers when only
9858 signed numbers are allowed. */
9860 minval
= 0, maxval
= 0xffff;
9862 minval
= -0x8000, maxval
= 0x7fff;
9864 minval
= -0x8000, maxval
= 0xffff;
9866 if (imm_expr
.X_op
!= O_constant
9867 || imm_expr
.X_add_number
< minval
9868 || imm_expr
.X_add_number
> maxval
)
9872 if (imm_expr
.X_op
== O_constant
9873 || imm_expr
.X_op
== O_big
)
9874 as_bad (_("expression out of range"));
9880 case 'o': /* 16 bit offset */
9881 /* Check whether there is only a single bracketed expression
9882 left. If so, it must be the base register and the
9883 constant must be zero. */
9884 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9886 offset_expr
.X_op
= O_constant
;
9887 offset_expr
.X_add_number
= 0;
9891 /* If this value won't fit into a 16 bit offset, then go
9892 find a macro that will generate the 32 bit offset
9894 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9895 && (offset_expr
.X_op
!= O_constant
9896 || offset_expr
.X_add_number
>= 0x8000
9897 || offset_expr
.X_add_number
< -0x8000))
9903 case 'p': /* pc relative offset */
9904 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9905 my_getExpression (&offset_expr
, s
);
9909 case 'u': /* upper 16 bits */
9910 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9911 && imm_expr
.X_op
== O_constant
9912 && (imm_expr
.X_add_number
< 0
9913 || imm_expr
.X_add_number
>= 0x10000))
9914 as_bad (_("lui expression not in range 0..65535"));
9918 case 'a': /* 26 bit address */
9919 my_getExpression (&offset_expr
, s
);
9921 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9924 case 'N': /* 3 bit branch condition code */
9925 case 'M': /* 3 bit compare condition code */
9927 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9929 if (!reg_lookup (&s
, rtype
, ®no
))
9931 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9932 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9933 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9934 && (regno
& 1) != 0)
9935 as_warn(_("Condition code register should be even for %s, was %d"),
9937 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9938 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9939 && (regno
& 3) != 0)
9940 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9943 INSERT_OPERAND (BCC
, *ip
, regno
);
9945 INSERT_OPERAND (CCC
, *ip
, regno
);
9949 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9960 while (ISDIGIT (*s
));
9963 c
= 8; /* Invalid sel value. */
9966 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9967 ip
->insn_opcode
|= c
;
9971 /* Must be at least one digit. */
9972 my_getExpression (&imm_expr
, s
);
9973 check_absolute_expr (ip
, &imm_expr
);
9975 if ((unsigned long) imm_expr
.X_add_number
9976 > (unsigned long) OP_MASK_VECBYTE
)
9978 as_bad (_("bad byte vector index (%ld)"),
9979 (long) imm_expr
.X_add_number
);
9980 imm_expr
.X_add_number
= 0;
9983 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9984 imm_expr
.X_op
= O_absent
;
9989 my_getExpression (&imm_expr
, s
);
9990 check_absolute_expr (ip
, &imm_expr
);
9992 if ((unsigned long) imm_expr
.X_add_number
9993 > (unsigned long) OP_MASK_VECALIGN
)
9995 as_bad (_("bad byte vector index (%ld)"),
9996 (long) imm_expr
.X_add_number
);
9997 imm_expr
.X_add_number
= 0;
10000 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
10001 imm_expr
.X_op
= O_absent
;
10006 as_bad (_("bad char = '%c'\n"), *args
);
10011 /* Args don't match. */
10012 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
10013 !strcmp (insn
->name
, insn
[1].name
))
10017 insn_error
= _("illegal operands");
10021 *(--argsStart
) = save_c
;
10022 insn_error
= _("illegal operands");
10027 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
10029 /* This routine assembles an instruction into its binary format when
10030 assembling for the mips16. As a side effect, it sets one of the
10031 global variables imm_reloc or offset_reloc to the type of
10032 relocation to do if one of the operands is an address expression.
10033 It also sets mips16_small and mips16_ext if the user explicitly
10034 requested a small or extended instruction. */
10037 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
10041 struct mips_opcode
*insn
;
10043 unsigned int regno
;
10044 unsigned int lastregno
= 0;
10050 mips16_small
= FALSE
;
10051 mips16_ext
= FALSE
;
10053 for (s
= str
; ISLOWER (*s
); ++s
)
10065 if (s
[1] == 't' && s
[2] == ' ')
10068 mips16_small
= TRUE
;
10072 else if (s
[1] == 'e' && s
[2] == ' ')
10079 /* Fall through. */
10081 insn_error
= _("unknown opcode");
10085 if (mips_opts
.noautoextend
&& ! mips16_ext
)
10086 mips16_small
= TRUE
;
10088 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
10090 insn_error
= _("unrecognized opcode");
10099 assert (strcmp (insn
->name
, str
) == 0);
10101 ok
= is_opcode_valid_16 (insn
);
10104 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
10105 && strcmp (insn
->name
, insn
[1].name
) == 0)
10114 static char buf
[100];
10116 _("opcode not supported on this processor: %s (%s)"),
10117 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
10118 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
10125 create_insn (ip
, insn
);
10126 imm_expr
.X_op
= O_absent
;
10127 imm_reloc
[0] = BFD_RELOC_UNUSED
;
10128 imm_reloc
[1] = BFD_RELOC_UNUSED
;
10129 imm_reloc
[2] = BFD_RELOC_UNUSED
;
10130 imm2_expr
.X_op
= O_absent
;
10131 offset_expr
.X_op
= O_absent
;
10132 offset_reloc
[0] = BFD_RELOC_UNUSED
;
10133 offset_reloc
[1] = BFD_RELOC_UNUSED
;
10134 offset_reloc
[2] = BFD_RELOC_UNUSED
;
10135 for (args
= insn
->args
; 1; ++args
)
10142 /* In this switch statement we call break if we did not find
10143 a match, continue if we did find a match, or return if we
10152 /* Stuff the immediate value in now, if we can. */
10153 if (imm_expr
.X_op
== O_constant
10154 && *imm_reloc
> BFD_RELOC_UNUSED
10155 && *imm_reloc
!= BFD_RELOC_MIPS16_GOT16
10156 && *imm_reloc
!= BFD_RELOC_MIPS16_CALL16
10157 && insn
->pinfo
!= INSN_MACRO
)
10161 switch (*offset_reloc
)
10163 case BFD_RELOC_MIPS16_HI16_S
:
10164 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
10167 case BFD_RELOC_MIPS16_HI16
:
10168 tmp
= imm_expr
.X_add_number
>> 16;
10171 case BFD_RELOC_MIPS16_LO16
:
10172 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
10176 case BFD_RELOC_UNUSED
:
10177 tmp
= imm_expr
.X_add_number
;
10183 *offset_reloc
= BFD_RELOC_UNUSED
;
10185 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
10186 tmp
, TRUE
, mips16_small
,
10187 mips16_ext
, &ip
->insn_opcode
,
10188 &ip
->use_extend
, &ip
->extend
);
10189 imm_expr
.X_op
= O_absent
;
10190 *imm_reloc
= BFD_RELOC_UNUSED
;
10204 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10207 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10223 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10225 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10229 /* Fall through. */
10240 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
10242 if (c
== 'v' || c
== 'w')
10245 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
10247 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
10258 if (c
== 'v' || c
== 'w')
10260 regno
= mips16_to_32_reg_map
[lastregno
];
10274 regno
= mips32_to_16_reg_map
[regno
];
10279 regno
= ILLEGAL_REG
;
10284 regno
= ILLEGAL_REG
;
10289 regno
= ILLEGAL_REG
;
10294 if (regno
== AT
&& mips_opts
.at
)
10296 if (mips_opts
.at
== ATREG
)
10297 as_warn (_("used $at without \".set noat\""));
10299 as_warn (_("used $%u with \".set at=$%u\""),
10300 regno
, mips_opts
.at
);
10308 if (regno
== ILLEGAL_REG
)
10315 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
10319 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
10322 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
10325 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
10331 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
10334 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
10335 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
10345 if (strncmp (s
, "$pc", 3) == 0)
10362 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
10365 if (imm_expr
.X_op
!= O_constant
)
10368 ip
->use_extend
= TRUE
;
10373 /* We need to relax this instruction. */
10374 *offset_reloc
= *imm_reloc
;
10375 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10380 *imm_reloc
= BFD_RELOC_UNUSED
;
10381 /* Fall through. */
10388 my_getExpression (&imm_expr
, s
);
10389 if (imm_expr
.X_op
== O_register
)
10391 /* What we thought was an expression turned out to
10394 if (s
[0] == '(' && args
[1] == '(')
10396 /* It looks like the expression was omitted
10397 before a register indirection, which means
10398 that the expression is implicitly zero. We
10399 still set up imm_expr, so that we handle
10400 explicit extensions correctly. */
10401 imm_expr
.X_op
= O_constant
;
10402 imm_expr
.X_add_number
= 0;
10403 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10410 /* We need to relax this instruction. */
10411 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10420 /* We use offset_reloc rather than imm_reloc for the PC
10421 relative operands. This lets macros with both
10422 immediate and address operands work correctly. */
10423 my_getExpression (&offset_expr
, s
);
10425 if (offset_expr
.X_op
== O_register
)
10428 /* We need to relax this instruction. */
10429 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10433 case '6': /* break code */
10434 my_getExpression (&imm_expr
, s
);
10435 check_absolute_expr (ip
, &imm_expr
);
10436 if ((unsigned long) imm_expr
.X_add_number
> 63)
10437 as_warn (_("Invalid value for `%s' (%lu)"),
10439 (unsigned long) imm_expr
.X_add_number
);
10440 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10441 imm_expr
.X_op
= O_absent
;
10445 case 'a': /* 26 bit address */
10446 my_getExpression (&offset_expr
, s
);
10448 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10449 ip
->insn_opcode
<<= 16;
10452 case 'l': /* register list for entry macro */
10453 case 'L': /* register list for exit macro */
10463 unsigned int freg
, reg1
, reg2
;
10465 while (*s
== ' ' || *s
== ',')
10467 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10469 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10473 as_bad (_("can't parse register list"));
10483 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10484 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10486 as_bad (_("invalid register list"));
10490 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10492 mask
&= ~ (7 << 3);
10495 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10497 mask
&= ~ (7 << 3);
10500 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10501 mask
|= (reg2
- 3) << 3;
10502 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10503 mask
|= (reg2
- 15) << 1;
10504 else if (reg1
== RA
&& reg2
== RA
)
10508 as_bad (_("invalid register list"));
10512 /* The mask is filled in in the opcode table for the
10513 benefit of the disassembler. We remove it before
10514 applying the actual mask. */
10515 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10516 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10520 case 'm': /* Register list for save insn. */
10521 case 'M': /* Register list for restore insn. */
10524 int framesz
= 0, seen_framesz
= 0;
10525 int args
= 0, statics
= 0, sregs
= 0;
10529 unsigned int reg1
, reg2
;
10531 SKIP_SPACE_TABS (s
);
10534 SKIP_SPACE_TABS (s
);
10536 my_getExpression (&imm_expr
, s
);
10537 if (imm_expr
.X_op
== O_constant
)
10539 /* Handle the frame size. */
10542 as_bad (_("more than one frame size in list"));
10546 framesz
= imm_expr
.X_add_number
;
10547 imm_expr
.X_op
= O_absent
;
10552 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10554 as_bad (_("can't parse register list"));
10566 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10569 as_bad (_("can't parse register list"));
10574 while (reg1
<= reg2
)
10576 if (reg1
>= 4 && reg1
<= 7)
10580 args
|= 1 << (reg1
- 4);
10582 /* statics $a0-$a3 */
10583 statics
|= 1 << (reg1
- 4);
10585 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10588 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10590 else if (reg1
== 31)
10592 /* Add $ra to insn. */
10597 as_bad (_("unexpected register in list"));
10605 /* Encode args/statics combination. */
10606 if (args
& statics
)
10607 as_bad (_("arg/static registers overlap"));
10608 else if (args
== 0xf)
10609 /* All $a0-$a3 are args. */
10610 opcode
|= MIPS16_ALL_ARGS
<< 16;
10611 else if (statics
== 0xf)
10612 /* All $a0-$a3 are statics. */
10613 opcode
|= MIPS16_ALL_STATICS
<< 16;
10616 int narg
= 0, nstat
= 0;
10618 /* Count arg registers. */
10625 as_bad (_("invalid arg register list"));
10627 /* Count static registers. */
10628 while (statics
& 0x8)
10630 statics
= (statics
<< 1) & 0xf;
10634 as_bad (_("invalid static register list"));
10636 /* Encode args/statics. */
10637 opcode
|= ((narg
<< 2) | nstat
) << 16;
10640 /* Encode $s0/$s1. */
10641 if (sregs
& (1 << 0)) /* $s0 */
10643 if (sregs
& (1 << 1)) /* $s1 */
10649 /* Count regs $s2-$s8. */
10657 as_bad (_("invalid static register list"));
10658 /* Encode $s2-$s8. */
10659 opcode
|= nsreg
<< 24;
10662 /* Encode frame size. */
10664 as_bad (_("missing frame size"));
10665 else if ((framesz
& 7) != 0 || framesz
< 0
10666 || framesz
> 0xff * 8)
10667 as_bad (_("invalid frame size"));
10668 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10671 opcode
|= (((framesz
& 0xf0) << 16)
10672 | (framesz
& 0x0f));
10675 /* Finally build the instruction. */
10676 if ((opcode
>> 16) != 0 || framesz
== 0)
10678 ip
->use_extend
= TRUE
;
10679 ip
->extend
= opcode
>> 16;
10681 ip
->insn_opcode
|= opcode
& 0x7f;
10685 case 'e': /* extend code */
10686 my_getExpression (&imm_expr
, s
);
10687 check_absolute_expr (ip
, &imm_expr
);
10688 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10690 as_warn (_("Invalid value for `%s' (%lu)"),
10692 (unsigned long) imm_expr
.X_add_number
);
10693 imm_expr
.X_add_number
&= 0x7ff;
10695 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10696 imm_expr
.X_op
= O_absent
;
10706 /* Args don't match. */
10707 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10708 strcmp (insn
->name
, insn
[1].name
) == 0)
10715 insn_error
= _("illegal operands");
10721 /* This structure holds information we know about a mips16 immediate
10724 struct mips16_immed_operand
10726 /* The type code used in the argument string in the opcode table. */
10728 /* The number of bits in the short form of the opcode. */
10730 /* The number of bits in the extended form of the opcode. */
10732 /* The amount by which the short form is shifted when it is used;
10733 for example, the sw instruction has a shift count of 2. */
10735 /* The amount by which the short form is shifted when it is stored
10736 into the instruction code. */
10738 /* Non-zero if the short form is unsigned. */
10740 /* Non-zero if the extended form is unsigned. */
10742 /* Non-zero if the value is PC relative. */
10746 /* The mips16 immediate operand types. */
10748 static const struct mips16_immed_operand mips16_immed_operands
[] =
10750 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10751 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10752 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10753 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10754 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10755 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10756 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10757 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10758 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10759 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10760 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10761 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10762 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10763 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10764 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10765 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10766 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10767 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10768 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10769 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10770 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10773 #define MIPS16_NUM_IMMED \
10774 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10776 /* Handle a mips16 instruction with an immediate value. This or's the
10777 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10778 whether an extended value is needed; if one is needed, it sets
10779 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10780 If SMALL is true, an unextended opcode was explicitly requested.
10781 If EXT is true, an extended opcode was explicitly requested. If
10782 WARN is true, warn if EXT does not match reality. */
10785 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10786 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10787 unsigned long *insn
, bfd_boolean
*use_extend
,
10788 unsigned short *extend
)
10790 const struct mips16_immed_operand
*op
;
10791 int mintiny
, maxtiny
;
10792 bfd_boolean needext
;
10794 op
= mips16_immed_operands
;
10795 while (op
->type
!= type
)
10798 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10803 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10806 maxtiny
= 1 << op
->nbits
;
10811 maxtiny
= (1 << op
->nbits
) - 1;
10816 mintiny
= - (1 << (op
->nbits
- 1));
10817 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10820 /* Branch offsets have an implicit 0 in the lowest bit. */
10821 if (type
== 'p' || type
== 'q')
10824 if ((val
& ((1 << op
->shift
) - 1)) != 0
10825 || val
< (mintiny
<< op
->shift
)
10826 || val
> (maxtiny
<< op
->shift
))
10831 if (warn
&& ext
&& ! needext
)
10832 as_warn_where (file
, line
,
10833 _("extended operand requested but not required"));
10834 if (small
&& needext
)
10835 as_bad_where (file
, line
, _("invalid unextended operand value"));
10837 if (small
|| (! ext
&& ! needext
))
10841 *use_extend
= FALSE
;
10842 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10843 insnval
<<= op
->op_shift
;
10848 long minext
, maxext
;
10854 maxext
= (1 << op
->extbits
) - 1;
10858 minext
= - (1 << (op
->extbits
- 1));
10859 maxext
= (1 << (op
->extbits
- 1)) - 1;
10861 if (val
< minext
|| val
> maxext
)
10862 as_bad_where (file
, line
,
10863 _("operand value out of range for instruction"));
10865 *use_extend
= TRUE
;
10866 if (op
->extbits
== 16)
10868 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10871 else if (op
->extbits
== 15)
10873 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10878 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10882 *extend
= (unsigned short) extval
;
10887 struct percent_op_match
10890 bfd_reloc_code_real_type reloc
;
10893 static const struct percent_op_match mips_percent_op
[] =
10895 {"%lo", BFD_RELOC_LO16
},
10897 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10898 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10899 {"%call16", BFD_RELOC_MIPS_CALL16
},
10900 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10901 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10902 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10903 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10904 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10905 {"%got", BFD_RELOC_MIPS_GOT16
},
10906 {"%gp_rel", BFD_RELOC_GPREL16
},
10907 {"%half", BFD_RELOC_16
},
10908 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10909 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10910 {"%neg", BFD_RELOC_MIPS_SUB
},
10911 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10912 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10913 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10914 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10915 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10916 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10917 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10919 {"%hi", BFD_RELOC_HI16_S
}
10922 static const struct percent_op_match mips16_percent_op
[] =
10924 {"%lo", BFD_RELOC_MIPS16_LO16
},
10925 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10926 {"%got", BFD_RELOC_MIPS16_GOT16
},
10927 {"%call16", BFD_RELOC_MIPS16_CALL16
},
10928 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10932 /* Return true if *STR points to a relocation operator. When returning true,
10933 move *STR over the operator and store its relocation code in *RELOC.
10934 Leave both *STR and *RELOC alone when returning false. */
10937 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10939 const struct percent_op_match
*percent_op
;
10942 if (mips_opts
.mips16
)
10944 percent_op
= mips16_percent_op
;
10945 limit
= ARRAY_SIZE (mips16_percent_op
);
10949 percent_op
= mips_percent_op
;
10950 limit
= ARRAY_SIZE (mips_percent_op
);
10953 for (i
= 0; i
< limit
; i
++)
10954 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10956 int len
= strlen (percent_op
[i
].str
);
10958 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10961 *str
+= strlen (percent_op
[i
].str
);
10962 *reloc
= percent_op
[i
].reloc
;
10964 /* Check whether the output BFD supports this relocation.
10965 If not, issue an error and fall back on something safe. */
10966 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10968 as_bad ("relocation %s isn't supported by the current ABI",
10969 percent_op
[i
].str
);
10970 *reloc
= BFD_RELOC_UNUSED
;
10978 /* Parse string STR as a 16-bit relocatable operand. Store the
10979 expression in *EP and the relocations in the array starting
10980 at RELOC. Return the number of relocation operators used.
10982 On exit, EXPR_END points to the first character after the expression. */
10985 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10988 bfd_reloc_code_real_type reversed_reloc
[3];
10989 size_t reloc_index
, i
;
10990 int crux_depth
, str_depth
;
10993 /* Search for the start of the main expression, recoding relocations
10994 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10995 of the main expression and with CRUX_DEPTH containing the number
10996 of open brackets at that point. */
11003 crux_depth
= str_depth
;
11005 /* Skip over whitespace and brackets, keeping count of the number
11007 while (*str
== ' ' || *str
== '\t' || *str
== '(')
11012 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
11013 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
11015 my_getExpression (ep
, crux
);
11018 /* Match every open bracket. */
11019 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
11023 if (crux_depth
> 0)
11024 as_bad ("unclosed '('");
11028 if (reloc_index
!= 0)
11030 prev_reloc_op_frag
= frag_now
;
11031 for (i
= 0; i
< reloc_index
; i
++)
11032 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
11035 return reloc_index
;
11039 my_getExpression (expressionS
*ep
, char *str
)
11044 save_in
= input_line_pointer
;
11045 input_line_pointer
= str
;
11047 expr_end
= input_line_pointer
;
11048 input_line_pointer
= save_in
;
11050 /* If we are in mips16 mode, and this is an expression based on `.',
11051 then we bump the value of the symbol by 1 since that is how other
11052 text symbols are handled. We don't bother to handle complex
11053 expressions, just `.' plus or minus a constant. */
11054 if (mips_opts
.mips16
11055 && ep
->X_op
== O_symbol
11056 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
11057 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
11058 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
11059 && symbol_constant_p (ep
->X_add_symbol
)
11060 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
11061 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
11065 md_atof (int type
, char *litP
, int *sizeP
)
11067 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
11071 md_number_to_chars (char *buf
, valueT val
, int n
)
11073 if (target_big_endian
)
11074 number_to_chars_bigendian (buf
, val
, n
);
11076 number_to_chars_littleendian (buf
, val
, n
);
11080 static int support_64bit_objects(void)
11082 const char **list
, **l
;
11085 list
= bfd_target_list ();
11086 for (l
= list
; *l
!= NULL
; l
++)
11088 /* This is traditional mips */
11089 if (strcmp (*l
, "elf64-tradbigmips") == 0
11090 || strcmp (*l
, "elf64-tradlittlemips") == 0)
11092 if (strcmp (*l
, "elf64-bigmips") == 0
11093 || strcmp (*l
, "elf64-littlemips") == 0)
11096 yes
= (*l
!= NULL
);
11100 #endif /* OBJ_ELF */
11102 const char *md_shortopts
= "O::g::G:";
11106 OPTION_MARCH
= OPTION_MD_BASE
,
11128 OPTION_NO_SMARTMIPS
,
11131 OPTION_COMPAT_ARCH_BASE
,
11140 OPTION_M7000_HILO_FIX
,
11141 OPTION_MNO_7000_HILO_FIX
,
11143 OPTION_NO_FIX_VR4120
,
11145 OPTION_NO_FIX_VR4130
,
11152 OPTION_CONSTRUCT_FLOATS
,
11153 OPTION_NO_CONSTRUCT_FLOATS
,
11156 OPTION_RELAX_BRANCH
,
11157 OPTION_NO_RELAX_BRANCH
,
11164 OPTION_SINGLE_FLOAT
,
11165 OPTION_DOUBLE_FLOAT
,
11168 OPTION_CALL_SHARED
,
11169 OPTION_CALL_NONPIC
,
11179 OPTION_MVXWORKS_PIC
,
11180 #endif /* OBJ_ELF */
11184 struct option md_longopts
[] =
11186 /* Options which specify architecture. */
11187 {"march", required_argument
, NULL
, OPTION_MARCH
},
11188 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
11189 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
11190 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
11191 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
11192 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
11193 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
11194 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
11195 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
11196 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
11197 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
11198 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
11200 /* Options which specify Application Specific Extensions (ASEs). */
11201 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
11202 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
11203 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
11204 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
11205 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
11206 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
11207 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
11208 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
11209 {"mmt", no_argument
, NULL
, OPTION_MT
},
11210 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
11211 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
11212 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
11213 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
11214 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
11216 /* Old-style architecture options. Don't add more of these. */
11217 {"m4650", no_argument
, NULL
, OPTION_M4650
},
11218 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
11219 {"m4010", no_argument
, NULL
, OPTION_M4010
},
11220 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
11221 {"m4100", no_argument
, NULL
, OPTION_M4100
},
11222 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
11223 {"m3900", no_argument
, NULL
, OPTION_M3900
},
11224 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
11226 /* Options which enable bug fixes. */
11227 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
11228 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11229 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
11230 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
11231 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
11232 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
11233 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
11235 /* Miscellaneous options. */
11236 {"trap", no_argument
, NULL
, OPTION_TRAP
},
11237 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
11238 {"break", no_argument
, NULL
, OPTION_BREAK
},
11239 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
11240 {"EB", no_argument
, NULL
, OPTION_EB
},
11241 {"EL", no_argument
, NULL
, OPTION_EL
},
11242 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
11243 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
11244 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
11245 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
11246 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
11247 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
11248 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
11249 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
11250 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
11251 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
11252 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
11253 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
11254 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
11255 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
11256 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
11257 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
11259 /* Strictly speaking this next option is ELF specific,
11260 but we allow it for other ports as well in order to
11261 make testing easier. */
11262 {"32", no_argument
, NULL
, OPTION_32
},
11264 /* ELF-specific options. */
11266 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
11267 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
11268 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
11269 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
11270 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
11271 {"mabi", required_argument
, NULL
, OPTION_MABI
},
11272 {"n32", no_argument
, NULL
, OPTION_N32
},
11273 {"64", no_argument
, NULL
, OPTION_64
},
11274 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
11275 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
11276 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
11277 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
11278 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
11279 #endif /* OBJ_ELF */
11281 {NULL
, no_argument
, NULL
, 0}
11283 size_t md_longopts_size
= sizeof (md_longopts
);
11285 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
11286 NEW_VALUE. Warn if another value was already specified. Note:
11287 we have to defer parsing the -march and -mtune arguments in order
11288 to handle 'from-abi' correctly, since the ABI might be specified
11289 in a later argument. */
11292 mips_set_option_string (const char **string_ptr
, const char *new_value
)
11294 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
11295 as_warn (_("A different %s was already specified, is now %s"),
11296 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
11299 *string_ptr
= new_value
;
11303 md_parse_option (int c
, char *arg
)
11307 case OPTION_CONSTRUCT_FLOATS
:
11308 mips_disable_float_construction
= 0;
11311 case OPTION_NO_CONSTRUCT_FLOATS
:
11312 mips_disable_float_construction
= 1;
11324 target_big_endian
= 1;
11328 target_big_endian
= 0;
11334 else if (arg
[0] == '0')
11336 else if (arg
[0] == '1')
11346 mips_debug
= atoi (arg
);
11350 file_mips_isa
= ISA_MIPS1
;
11354 file_mips_isa
= ISA_MIPS2
;
11358 file_mips_isa
= ISA_MIPS3
;
11362 file_mips_isa
= ISA_MIPS4
;
11366 file_mips_isa
= ISA_MIPS5
;
11369 case OPTION_MIPS32
:
11370 file_mips_isa
= ISA_MIPS32
;
11373 case OPTION_MIPS32R2
:
11374 file_mips_isa
= ISA_MIPS32R2
;
11377 case OPTION_MIPS64R2
:
11378 file_mips_isa
= ISA_MIPS64R2
;
11381 case OPTION_MIPS64
:
11382 file_mips_isa
= ISA_MIPS64
;
11386 mips_set_option_string (&mips_tune_string
, arg
);
11390 mips_set_option_string (&mips_arch_string
, arg
);
11394 mips_set_option_string (&mips_arch_string
, "4650");
11395 mips_set_option_string (&mips_tune_string
, "4650");
11398 case OPTION_NO_M4650
:
11402 mips_set_option_string (&mips_arch_string
, "4010");
11403 mips_set_option_string (&mips_tune_string
, "4010");
11406 case OPTION_NO_M4010
:
11410 mips_set_option_string (&mips_arch_string
, "4100");
11411 mips_set_option_string (&mips_tune_string
, "4100");
11414 case OPTION_NO_M4100
:
11418 mips_set_option_string (&mips_arch_string
, "3900");
11419 mips_set_option_string (&mips_tune_string
, "3900");
11422 case OPTION_NO_M3900
:
11426 mips_opts
.ase_mdmx
= 1;
11429 case OPTION_NO_MDMX
:
11430 mips_opts
.ase_mdmx
= 0;
11434 mips_opts
.ase_dsp
= 1;
11435 mips_opts
.ase_dspr2
= 0;
11438 case OPTION_NO_DSP
:
11439 mips_opts
.ase_dsp
= 0;
11440 mips_opts
.ase_dspr2
= 0;
11444 mips_opts
.ase_dspr2
= 1;
11445 mips_opts
.ase_dsp
= 1;
11448 case OPTION_NO_DSPR2
:
11449 mips_opts
.ase_dspr2
= 0;
11450 mips_opts
.ase_dsp
= 0;
11454 mips_opts
.ase_mt
= 1;
11458 mips_opts
.ase_mt
= 0;
11461 case OPTION_MIPS16
:
11462 mips_opts
.mips16
= 1;
11463 mips_no_prev_insn ();
11466 case OPTION_NO_MIPS16
:
11467 mips_opts
.mips16
= 0;
11468 mips_no_prev_insn ();
11471 case OPTION_MIPS3D
:
11472 mips_opts
.ase_mips3d
= 1;
11475 case OPTION_NO_MIPS3D
:
11476 mips_opts
.ase_mips3d
= 0;
11479 case OPTION_SMARTMIPS
:
11480 mips_opts
.ase_smartmips
= 1;
11483 case OPTION_NO_SMARTMIPS
:
11484 mips_opts
.ase_smartmips
= 0;
11487 case OPTION_FIX_VR4120
:
11488 mips_fix_vr4120
= 1;
11491 case OPTION_NO_FIX_VR4120
:
11492 mips_fix_vr4120
= 0;
11495 case OPTION_FIX_VR4130
:
11496 mips_fix_vr4130
= 1;
11499 case OPTION_NO_FIX_VR4130
:
11500 mips_fix_vr4130
= 0;
11503 case OPTION_RELAX_BRANCH
:
11504 mips_relax_branch
= 1;
11507 case OPTION_NO_RELAX_BRANCH
:
11508 mips_relax_branch
= 0;
11511 case OPTION_MSHARED
:
11512 mips_in_shared
= TRUE
;
11515 case OPTION_MNO_SHARED
:
11516 mips_in_shared
= FALSE
;
11519 case OPTION_MSYM32
:
11520 mips_opts
.sym32
= TRUE
;
11523 case OPTION_MNO_SYM32
:
11524 mips_opts
.sym32
= FALSE
;
11528 /* When generating ELF code, we permit -KPIC and -call_shared to
11529 select SVR4_PIC, and -non_shared to select no PIC. This is
11530 intended to be compatible with Irix 5. */
11531 case OPTION_CALL_SHARED
:
11534 as_bad (_("-call_shared is supported only for ELF format"));
11537 mips_pic
= SVR4_PIC
;
11538 mips_abicalls
= TRUE
;
11541 case OPTION_CALL_NONPIC
:
11544 as_bad (_("-call_nonpic is supported only for ELF format"));
11548 mips_abicalls
= TRUE
;
11551 case OPTION_NON_SHARED
:
11554 as_bad (_("-non_shared is supported only for ELF format"));
11558 mips_abicalls
= FALSE
;
11561 /* The -xgot option tells the assembler to use 32 bit offsets
11562 when accessing the got in SVR4_PIC mode. It is for Irix
11567 #endif /* OBJ_ELF */
11570 g_switch_value
= atoi (arg
);
11574 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11578 mips_abi
= O32_ABI
;
11579 /* We silently ignore -32 for non-ELF targets. This greatly
11580 simplifies the construction of the MIPS GAS test cases. */
11587 as_bad (_("-n32 is supported for ELF format only"));
11590 mips_abi
= N32_ABI
;
11596 as_bad (_("-64 is supported for ELF format only"));
11599 mips_abi
= N64_ABI
;
11600 if (!support_64bit_objects())
11601 as_fatal (_("No compiled in support for 64 bit object file format"));
11603 #endif /* OBJ_ELF */
11606 file_mips_gp32
= 1;
11610 file_mips_gp32
= 0;
11614 file_mips_fp32
= 1;
11618 file_mips_fp32
= 0;
11621 case OPTION_SINGLE_FLOAT
:
11622 file_mips_single_float
= 1;
11625 case OPTION_DOUBLE_FLOAT
:
11626 file_mips_single_float
= 0;
11629 case OPTION_SOFT_FLOAT
:
11630 file_mips_soft_float
= 1;
11633 case OPTION_HARD_FLOAT
:
11634 file_mips_soft_float
= 0;
11641 as_bad (_("-mabi is supported for ELF format only"));
11644 if (strcmp (arg
, "32") == 0)
11645 mips_abi
= O32_ABI
;
11646 else if (strcmp (arg
, "o64") == 0)
11647 mips_abi
= O64_ABI
;
11648 else if (strcmp (arg
, "n32") == 0)
11649 mips_abi
= N32_ABI
;
11650 else if (strcmp (arg
, "64") == 0)
11652 mips_abi
= N64_ABI
;
11653 if (! support_64bit_objects())
11654 as_fatal (_("No compiled in support for 64 bit object file "
11657 else if (strcmp (arg
, "eabi") == 0)
11658 mips_abi
= EABI_ABI
;
11661 as_fatal (_("invalid abi -mabi=%s"), arg
);
11665 #endif /* OBJ_ELF */
11667 case OPTION_M7000_HILO_FIX
:
11668 mips_7000_hilo_fix
= TRUE
;
11671 case OPTION_MNO_7000_HILO_FIX
:
11672 mips_7000_hilo_fix
= FALSE
;
11676 case OPTION_MDEBUG
:
11677 mips_flag_mdebug
= TRUE
;
11680 case OPTION_NO_MDEBUG
:
11681 mips_flag_mdebug
= FALSE
;
11685 mips_flag_pdr
= TRUE
;
11688 case OPTION_NO_PDR
:
11689 mips_flag_pdr
= FALSE
;
11692 case OPTION_MVXWORKS_PIC
:
11693 mips_pic
= VXWORKS_PIC
;
11695 #endif /* OBJ_ELF */
11704 /* Set up globals to generate code for the ISA or processor
11705 described by INFO. */
11708 mips_set_architecture (const struct mips_cpu_info
*info
)
11712 file_mips_arch
= info
->cpu
;
11713 mips_opts
.arch
= info
->cpu
;
11714 mips_opts
.isa
= info
->isa
;
11719 /* Likewise for tuning. */
11722 mips_set_tune (const struct mips_cpu_info
*info
)
11725 mips_tune
= info
->cpu
;
11730 mips_after_parse_args (void)
11732 const struct mips_cpu_info
*arch_info
= 0;
11733 const struct mips_cpu_info
*tune_info
= 0;
11735 /* GP relative stuff not working for PE */
11736 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11738 if (g_switch_seen
&& g_switch_value
!= 0)
11739 as_bad (_("-G not supported in this configuration."));
11740 g_switch_value
= 0;
11743 if (mips_abi
== NO_ABI
)
11744 mips_abi
= MIPS_DEFAULT_ABI
;
11746 /* The following code determines the architecture and register size.
11747 Similar code was added to GCC 3.3 (see override_options() in
11748 config/mips/mips.c). The GAS and GCC code should be kept in sync
11749 as much as possible. */
11751 if (mips_arch_string
!= 0)
11752 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11754 if (file_mips_isa
!= ISA_UNKNOWN
)
11756 /* Handle -mipsN. At this point, file_mips_isa contains the
11757 ISA level specified by -mipsN, while arch_info->isa contains
11758 the -march selection (if any). */
11759 if (arch_info
!= 0)
11761 /* -march takes precedence over -mipsN, since it is more descriptive.
11762 There's no harm in specifying both as long as the ISA levels
11764 if (file_mips_isa
!= arch_info
->isa
)
11765 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11766 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11767 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11770 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11773 if (arch_info
== 0)
11774 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11776 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11777 as_bad ("-march=%s is not compatible with the selected ABI",
11780 mips_set_architecture (arch_info
);
11782 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11783 if (mips_tune_string
!= 0)
11784 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11786 if (tune_info
== 0)
11787 mips_set_tune (arch_info
);
11789 mips_set_tune (tune_info
);
11791 if (file_mips_gp32
>= 0)
11793 /* The user specified the size of the integer registers. Make sure
11794 it agrees with the ABI and ISA. */
11795 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11796 as_bad (_("-mgp64 used with a 32-bit processor"));
11797 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11798 as_bad (_("-mgp32 used with a 64-bit ABI"));
11799 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11800 as_bad (_("-mgp64 used with a 32-bit ABI"));
11804 /* Infer the integer register size from the ABI and processor.
11805 Restrict ourselves to 32-bit registers if that's all the
11806 processor has, or if the ABI cannot handle 64-bit registers. */
11807 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11808 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11811 switch (file_mips_fp32
)
11815 /* No user specified float register size.
11816 ??? GAS treats single-float processors as though they had 64-bit
11817 float registers (although it complains when double-precision
11818 instructions are used). As things stand, saying they have 32-bit
11819 registers would lead to spurious "register must be even" messages.
11820 So here we assume float registers are never smaller than the
11822 if (file_mips_gp32
== 0)
11823 /* 64-bit integer registers implies 64-bit float registers. */
11824 file_mips_fp32
= 0;
11825 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11826 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11827 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11828 file_mips_fp32
= 0;
11830 /* 32-bit float registers. */
11831 file_mips_fp32
= 1;
11834 /* The user specified the size of the float registers. Check if it
11835 agrees with the ABI and ISA. */
11837 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11838 as_bad (_("-mfp64 used with a 32-bit fpu"));
11839 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11840 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11841 as_warn (_("-mfp64 used with a 32-bit ABI"));
11844 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11845 as_warn (_("-mfp32 used with a 64-bit ABI"));
11849 /* End of GCC-shared inference code. */
11851 /* This flag is set when we have a 64-bit capable CPU but use only
11852 32-bit wide registers. Note that EABI does not use it. */
11853 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11854 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11855 || mips_abi
== O32_ABI
))
11856 mips_32bitmode
= 1;
11858 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11859 as_bad (_("trap exception not supported at ISA 1"));
11861 /* If the selected architecture includes support for ASEs, enable
11862 generation of code for them. */
11863 if (mips_opts
.mips16
== -1)
11864 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11865 if (mips_opts
.ase_mips3d
== -1)
11866 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11867 && file_mips_fp32
== 0) ? 1 : 0;
11868 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11869 as_bad (_("-mfp32 used with -mips3d"));
11871 if (mips_opts
.ase_mdmx
== -1)
11872 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11873 && file_mips_fp32
== 0) ? 1 : 0;
11874 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11875 as_bad (_("-mfp32 used with -mdmx"));
11877 if (mips_opts
.ase_smartmips
== -1)
11878 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11879 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11880 as_warn ("%s ISA does not support SmartMIPS",
11881 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11883 if (mips_opts
.ase_dsp
== -1)
11884 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11885 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11886 as_warn ("%s ISA does not support DSP ASE",
11887 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11889 if (mips_opts
.ase_dspr2
== -1)
11891 mips_opts
.ase_dspr2
= (arch_info
->flags
& MIPS_CPU_ASE_DSPR2
) ? 1 : 0;
11892 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11894 if (mips_opts
.ase_dspr2
&& !ISA_SUPPORTS_DSPR2_ASE
)
11895 as_warn ("%s ISA does not support DSP R2 ASE",
11896 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11898 if (mips_opts
.ase_mt
== -1)
11899 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11900 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11901 as_warn ("%s ISA does not support MT ASE",
11902 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11904 file_mips_isa
= mips_opts
.isa
;
11905 file_ase_mips16
= mips_opts
.mips16
;
11906 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11907 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11908 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11909 file_ase_dsp
= mips_opts
.ase_dsp
;
11910 file_ase_dspr2
= mips_opts
.ase_dspr2
;
11911 file_ase_mt
= mips_opts
.ase_mt
;
11912 mips_opts
.gp32
= file_mips_gp32
;
11913 mips_opts
.fp32
= file_mips_fp32
;
11914 mips_opts
.soft_float
= file_mips_soft_float
;
11915 mips_opts
.single_float
= file_mips_single_float
;
11917 if (mips_flag_mdebug
< 0)
11919 #ifdef OBJ_MAYBE_ECOFF
11920 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11921 mips_flag_mdebug
= 1;
11923 #endif /* OBJ_MAYBE_ECOFF */
11924 mips_flag_mdebug
= 0;
11929 mips_init_after_args (void)
11931 /* initialize opcodes */
11932 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11933 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11937 md_pcrel_from (fixS
*fixP
)
11939 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11940 switch (fixP
->fx_r_type
)
11942 case BFD_RELOC_16_PCREL_S2
:
11943 case BFD_RELOC_MIPS_JMP
:
11944 /* Return the address of the delay slot. */
11947 /* We have no relocation type for PC relative MIPS16 instructions. */
11948 if (fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != now_seg
)
11949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11950 _("PC relative MIPS16 instruction references a different section"));
11955 /* This is called before the symbol table is processed. In order to
11956 work with gcc when using mips-tfile, we must keep all local labels.
11957 However, in other cases, we want to discard them. If we were
11958 called with -g, but we didn't see any debugging information, it may
11959 mean that gcc is smuggling debugging information through to
11960 mips-tfile, in which case we must generate all local labels. */
11963 mips_frob_file_before_adjust (void)
11965 #ifndef NO_ECOFF_DEBUGGING
11966 if (ECOFF_DEBUGGING
11968 && ! ecoff_debugging_seen
)
11969 flag_keep_locals
= 1;
11973 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11974 the corresponding LO16 reloc. This is called before md_apply_fix and
11975 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11976 relocation operators.
11978 For our purposes, a %lo() expression matches a %got() or %hi()
11981 (a) it refers to the same symbol; and
11982 (b) the offset applied in the %lo() expression is no lower than
11983 the offset applied in the %got() or %hi().
11985 (b) allows us to cope with code like:
11988 lh $4,%lo(foo+2)($4)
11990 ...which is legal on RELA targets, and has a well-defined behaviour
11991 if the user knows that adding 2 to "foo" will not induce a carry to
11994 When several %lo()s match a particular %got() or %hi(), we use the
11995 following rules to distinguish them:
11997 (1) %lo()s with smaller offsets are a better match than %lo()s with
12000 (2) %lo()s with no matching %got() or %hi() are better than those
12001 that already have a matching %got() or %hi().
12003 (3) later %lo()s are better than earlier %lo()s.
12005 These rules are applied in order.
12007 (1) means, among other things, that %lo()s with identical offsets are
12008 chosen if they exist.
12010 (2) means that we won't associate several high-part relocations with
12011 the same low-part relocation unless there's no alternative. Having
12012 several high parts for the same low part is a GNU extension; this rule
12013 allows careful users to avoid it.
12015 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
12016 with the last high-part relocation being at the front of the list.
12017 It therefore makes sense to choose the last matching low-part
12018 relocation, all other things being equal. It's also easier
12019 to code that way. */
12022 mips_frob_file (void)
12024 struct mips_hi_fixup
*l
;
12025 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
12027 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
12029 segment_info_type
*seginfo
;
12030 bfd_boolean matched_lo_p
;
12031 fixS
**hi_pos
, **lo_pos
, **pos
;
12033 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
12035 /* If a GOT16 relocation turns out to be against a global symbol,
12036 there isn't supposed to be a matching LO. */
12037 if (got16_reloc_p (l
->fixp
->fx_r_type
)
12038 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
12041 /* Check quickly whether the next fixup happens to be a matching %lo. */
12042 if (fixup_has_matching_lo_p (l
->fixp
))
12045 seginfo
= seg_info (l
->seg
);
12047 /* Set HI_POS to the position of this relocation in the chain.
12048 Set LO_POS to the position of the chosen low-part relocation.
12049 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
12050 relocation that matches an immediately-preceding high-part
12054 matched_lo_p
= FALSE
;
12055 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
12057 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
12059 if (*pos
== l
->fixp
)
12062 if ((*pos
)->fx_r_type
== looking_for_rtype
12063 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
12064 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
12066 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
12068 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
12071 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
12072 && fixup_has_matching_lo_p (*pos
));
12075 /* If we found a match, remove the high-part relocation from its
12076 current position and insert it before the low-part relocation.
12077 Make the offsets match so that fixup_has_matching_lo_p()
12080 We don't warn about unmatched high-part relocations since some
12081 versions of gcc have been known to emit dead "lui ...%hi(...)"
12083 if (lo_pos
!= NULL
)
12085 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
12086 if (l
->fixp
->fx_next
!= *lo_pos
)
12088 *hi_pos
= l
->fixp
->fx_next
;
12089 l
->fixp
->fx_next
= *lo_pos
;
12096 /* We may have combined relocations without symbols in the N32/N64 ABI.
12097 We have to prevent gas from dropping them. */
12100 mips_force_relocation (fixS
*fixp
)
12102 if (generic_force_reloc (fixp
))
12106 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
12107 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
12108 || hi16_reloc_p (fixp
->fx_r_type
)
12109 || lo16_reloc_p (fixp
->fx_r_type
)))
12115 /* Apply a fixup to the object file. */
12118 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
12122 reloc_howto_type
*howto
;
12124 /* We ignore generic BFD relocations we don't know about. */
12125 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
12129 assert (fixP
->fx_size
== 4
12130 || fixP
->fx_r_type
== BFD_RELOC_16
12131 || fixP
->fx_r_type
== BFD_RELOC_64
12132 || fixP
->fx_r_type
== BFD_RELOC_CTOR
12133 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
12134 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12135 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
12136 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
);
12138 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
12140 assert (!fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
12142 /* Don't treat parts of a composite relocation as done. There are two
12145 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12146 should nevertheless be emitted if the first part is.
12148 (2) In normal usage, composite relocations are never assembly-time
12149 constants. The easiest way of dealing with the pathological
12150 exceptions is to generate a relocation against STN_UNDEF and
12151 leave everything up to the linker. */
12152 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
12155 switch (fixP
->fx_r_type
)
12157 case BFD_RELOC_MIPS_TLS_GD
:
12158 case BFD_RELOC_MIPS_TLS_LDM
:
12159 case BFD_RELOC_MIPS_TLS_DTPREL32
:
12160 case BFD_RELOC_MIPS_TLS_DTPREL64
:
12161 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
12162 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
12163 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
12164 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
12165 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
12166 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
12169 case BFD_RELOC_MIPS_JMP
:
12170 case BFD_RELOC_MIPS_SHIFT5
:
12171 case BFD_RELOC_MIPS_SHIFT6
:
12172 case BFD_RELOC_MIPS_GOT_DISP
:
12173 case BFD_RELOC_MIPS_GOT_PAGE
:
12174 case BFD_RELOC_MIPS_GOT_OFST
:
12175 case BFD_RELOC_MIPS_SUB
:
12176 case BFD_RELOC_MIPS_INSERT_A
:
12177 case BFD_RELOC_MIPS_INSERT_B
:
12178 case BFD_RELOC_MIPS_DELETE
:
12179 case BFD_RELOC_MIPS_HIGHEST
:
12180 case BFD_RELOC_MIPS_HIGHER
:
12181 case BFD_RELOC_MIPS_SCN_DISP
:
12182 case BFD_RELOC_MIPS_REL16
:
12183 case BFD_RELOC_MIPS_RELGOT
:
12184 case BFD_RELOC_MIPS_JALR
:
12185 case BFD_RELOC_HI16
:
12186 case BFD_RELOC_HI16_S
:
12187 case BFD_RELOC_GPREL16
:
12188 case BFD_RELOC_MIPS_LITERAL
:
12189 case BFD_RELOC_MIPS_CALL16
:
12190 case BFD_RELOC_MIPS_GOT16
:
12191 case BFD_RELOC_GPREL32
:
12192 case BFD_RELOC_MIPS_GOT_HI16
:
12193 case BFD_RELOC_MIPS_GOT_LO16
:
12194 case BFD_RELOC_MIPS_CALL_HI16
:
12195 case BFD_RELOC_MIPS_CALL_LO16
:
12196 case BFD_RELOC_MIPS16_GPREL
:
12197 case BFD_RELOC_MIPS16_GOT16
:
12198 case BFD_RELOC_MIPS16_CALL16
:
12199 case BFD_RELOC_MIPS16_HI16
:
12200 case BFD_RELOC_MIPS16_HI16_S
:
12201 case BFD_RELOC_MIPS16_JMP
:
12202 /* Nothing needed to do. The value comes from the reloc entry. */
12206 /* This is handled like BFD_RELOC_32, but we output a sign
12207 extended value if we are only 32 bits. */
12210 if (8 <= sizeof (valueT
))
12211 md_number_to_chars ((char *) buf
, *valP
, 8);
12216 if ((*valP
& 0x80000000) != 0)
12220 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
12222 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
12228 case BFD_RELOC_RVA
:
12231 /* If we are deleting this reloc entry, we must fill in the
12232 value now. This can happen if we have a .word which is not
12233 resolved when it appears but is later defined. */
12235 md_number_to_chars ((char *) buf
, *valP
, fixP
->fx_size
);
12238 case BFD_RELOC_LO16
:
12239 case BFD_RELOC_MIPS16_LO16
:
12240 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12241 may be safe to remove, but if so it's not obvious. */
12242 /* When handling an embedded PIC switch statement, we can wind
12243 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12246 if (*valP
+ 0x8000 > 0xffff)
12247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12248 _("relocation overflow"));
12249 if (target_big_endian
)
12251 md_number_to_chars ((char *) buf
, *valP
, 2);
12255 case BFD_RELOC_16_PCREL_S2
:
12256 if ((*valP
& 0x3) != 0)
12257 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12258 _("Branch to misaligned address (%lx)"), (long) *valP
);
12260 /* We need to save the bits in the instruction since fixup_segment()
12261 might be deleting the relocation entry (i.e., a branch within
12262 the current segment). */
12263 if (! fixP
->fx_done
)
12266 /* Update old instruction data. */
12267 if (target_big_endian
)
12268 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
12270 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
12272 if (*valP
+ 0x20000 <= 0x3ffff)
12274 insn
|= (*valP
>> 2) & 0xffff;
12275 md_number_to_chars ((char *) buf
, insn
, 4);
12277 else if (mips_pic
== NO_PIC
12279 && fixP
->fx_frag
->fr_address
>= text_section
->vma
12280 && (fixP
->fx_frag
->fr_address
12281 < text_section
->vma
+ bfd_get_section_size (text_section
))
12282 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
12283 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
12284 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
12286 /* The branch offset is too large. If this is an
12287 unconditional branch, and we are not generating PIC code,
12288 we can convert it to an absolute jump instruction. */
12289 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
12290 insn
= 0x0c000000; /* jal */
12292 insn
= 0x08000000; /* j */
12293 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
12295 fixP
->fx_addsy
= section_symbol (text_section
);
12296 *valP
+= md_pcrel_from (fixP
);
12297 md_number_to_chars ((char *) buf
, insn
, 4);
12301 /* If we got here, we have branch-relaxation disabled,
12302 and there's nothing we can do to fix this instruction
12303 without turning it into a longer sequence. */
12304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
12305 _("Branch out of range"));
12309 case BFD_RELOC_VTABLE_INHERIT
:
12312 && !S_IS_DEFINED (fixP
->fx_addsy
)
12313 && !S_IS_WEAK (fixP
->fx_addsy
))
12314 S_SET_WEAK (fixP
->fx_addsy
);
12317 case BFD_RELOC_VTABLE_ENTRY
:
12325 /* Remember value for tc_gen_reloc. */
12326 fixP
->fx_addnumber
= *valP
;
12336 name
= input_line_pointer
;
12337 c
= get_symbol_end ();
12338 p
= (symbolS
*) symbol_find_or_make (name
);
12339 *input_line_pointer
= c
;
12343 /* Align the current frag to a given power of two. If a particular
12344 fill byte should be used, FILL points to an integer that contains
12345 that byte, otherwise FILL is null.
12347 The MIPS assembler also automatically adjusts any preceding
12351 mips_align (int to
, int *fill
, symbolS
*label
)
12353 mips_emit_delays ();
12354 mips_record_mips16_mode ();
12355 if (fill
== NULL
&& subseg_text_p (now_seg
))
12356 frag_align_code (to
, 0);
12358 frag_align (to
, fill
? *fill
: 0, 0);
12359 record_alignment (now_seg
, to
);
12362 assert (S_GET_SEGMENT (label
) == now_seg
);
12363 symbol_set_frag (label
, frag_now
);
12364 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
12368 /* Align to a given power of two. .align 0 turns off the automatic
12369 alignment used by the data creating pseudo-ops. */
12372 s_align (int x ATTRIBUTE_UNUSED
)
12374 int temp
, fill_value
, *fill_ptr
;
12375 long max_alignment
= 28;
12377 /* o Note that the assembler pulls down any immediately preceding label
12378 to the aligned address.
12379 o It's not documented but auto alignment is reinstated by
12380 a .align pseudo instruction.
12381 o Note also that after auto alignment is turned off the mips assembler
12382 issues an error on attempt to assemble an improperly aligned data item.
12385 temp
= get_absolute_expression ();
12386 if (temp
> max_alignment
)
12387 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
12390 as_warn (_("Alignment negative: 0 assumed."));
12393 if (*input_line_pointer
== ',')
12395 ++input_line_pointer
;
12396 fill_value
= get_absolute_expression ();
12397 fill_ptr
= &fill_value
;
12403 segment_info_type
*si
= seg_info (now_seg
);
12404 struct insn_label_list
*l
= si
->label_list
;
12405 /* Auto alignment should be switched on by next section change. */
12407 mips_align (temp
, fill_ptr
, l
!= NULL
? l
->label
: NULL
);
12414 demand_empty_rest_of_line ();
12418 s_change_sec (int sec
)
12423 /* The ELF backend needs to know that we are changing sections, so
12424 that .previous works correctly. We could do something like check
12425 for an obj_section_change_hook macro, but that might be confusing
12426 as it would not be appropriate to use it in the section changing
12427 functions in read.c, since obj-elf.c intercepts those. FIXME:
12428 This should be cleaner, somehow. */
12430 obj_elf_section_change_hook ();
12433 mips_emit_delays ();
12443 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12444 demand_empty_rest_of_line ();
12448 seg
= subseg_new (RDATA_SECTION_NAME
,
12449 (subsegT
) get_absolute_expression ());
12452 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12453 | SEC_READONLY
| SEC_RELOC
12455 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12456 record_alignment (seg
, 4);
12458 demand_empty_rest_of_line ();
12462 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12465 bfd_set_section_flags (stdoutput
, seg
,
12466 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12467 if (strncmp (TARGET_OS
, "elf", 3) != 0)
12468 record_alignment (seg
, 4);
12470 demand_empty_rest_of_line ();
12478 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12481 char *section_name
;
12486 int section_entry_size
;
12487 int section_alignment
;
12492 section_name
= input_line_pointer
;
12493 c
= get_symbol_end ();
12495 next_c
= *(input_line_pointer
+ 1);
12497 /* Do we have .section Name<,"flags">? */
12498 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12500 /* just after name is now '\0'. */
12501 *input_line_pointer
= c
;
12502 input_line_pointer
= section_name
;
12503 obj_elf_section (ignore
);
12506 input_line_pointer
++;
12508 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12510 section_type
= get_absolute_expression ();
12513 if (*input_line_pointer
++ == ',')
12514 section_flag
= get_absolute_expression ();
12517 if (*input_line_pointer
++ == ',')
12518 section_entry_size
= get_absolute_expression ();
12520 section_entry_size
= 0;
12521 if (*input_line_pointer
++ == ',')
12522 section_alignment
= get_absolute_expression ();
12524 section_alignment
= 0;
12526 section_name
= xstrdup (section_name
);
12528 /* When using the generic form of .section (as implemented by obj-elf.c),
12529 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12530 traditionally had to fall back on the more common @progbits instead.
12532 There's nothing really harmful in this, since bfd will correct
12533 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12534 means that, for backwards compatibility, the special_section entries
12535 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12537 Even so, we shouldn't force users of the MIPS .section syntax to
12538 incorrectly label the sections as SHT_PROGBITS. The best compromise
12539 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12540 generic type-checking code. */
12541 if (section_type
== SHT_MIPS_DWARF
)
12542 section_type
= SHT_PROGBITS
;
12544 obj_elf_change_section (section_name
, section_type
, section_flag
,
12545 section_entry_size
, 0, 0, 0);
12547 if (now_seg
->name
!= section_name
)
12548 free (section_name
);
12549 #endif /* OBJ_ELF */
12553 mips_enable_auto_align (void)
12559 s_cons (int log_size
)
12561 segment_info_type
*si
= seg_info (now_seg
);
12562 struct insn_label_list
*l
= si
->label_list
;
12565 label
= l
!= NULL
? l
->label
: NULL
;
12566 mips_emit_delays ();
12567 if (log_size
> 0 && auto_align
)
12568 mips_align (log_size
, 0, label
);
12569 mips_clear_insn_labels ();
12570 cons (1 << log_size
);
12574 s_float_cons (int type
)
12576 segment_info_type
*si
= seg_info (now_seg
);
12577 struct insn_label_list
*l
= si
->label_list
;
12580 label
= l
!= NULL
? l
->label
: NULL
;
12582 mips_emit_delays ();
12587 mips_align (3, 0, label
);
12589 mips_align (2, 0, label
);
12592 mips_clear_insn_labels ();
12597 /* Handle .globl. We need to override it because on Irix 5 you are
12600 where foo is an undefined symbol, to mean that foo should be
12601 considered to be the address of a function. */
12604 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12613 name
= input_line_pointer
;
12614 c
= get_symbol_end ();
12615 symbolP
= symbol_find_or_make (name
);
12616 S_SET_EXTERNAL (symbolP
);
12618 *input_line_pointer
= c
;
12619 SKIP_WHITESPACE ();
12621 /* On Irix 5, every global symbol that is not explicitly labelled as
12622 being a function is apparently labelled as being an object. */
12625 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12626 && (*input_line_pointer
!= ','))
12631 secname
= input_line_pointer
;
12632 c
= get_symbol_end ();
12633 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12635 as_bad (_("%s: no such section"), secname
);
12636 *input_line_pointer
= c
;
12638 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12639 flag
= BSF_FUNCTION
;
12642 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12644 c
= *input_line_pointer
;
12647 input_line_pointer
++;
12648 SKIP_WHITESPACE ();
12649 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12655 demand_empty_rest_of_line ();
12659 s_option (int x ATTRIBUTE_UNUSED
)
12664 opt
= input_line_pointer
;
12665 c
= get_symbol_end ();
12669 /* FIXME: What does this mean? */
12671 else if (strncmp (opt
, "pic", 3) == 0)
12675 i
= atoi (opt
+ 3);
12680 mips_pic
= SVR4_PIC
;
12681 mips_abicalls
= TRUE
;
12684 as_bad (_(".option pic%d not supported"), i
);
12686 if (mips_pic
== SVR4_PIC
)
12688 if (g_switch_seen
&& g_switch_value
!= 0)
12689 as_warn (_("-G may not be used with SVR4 PIC code"));
12690 g_switch_value
= 0;
12691 bfd_set_gp_size (stdoutput
, 0);
12695 as_warn (_("Unrecognized option \"%s\""), opt
);
12697 *input_line_pointer
= c
;
12698 demand_empty_rest_of_line ();
12701 /* This structure is used to hold a stack of .set values. */
12703 struct mips_option_stack
12705 struct mips_option_stack
*next
;
12706 struct mips_set_options options
;
12709 static struct mips_option_stack
*mips_opts_stack
;
12711 /* Handle the .set pseudo-op. */
12714 s_mipsset (int x ATTRIBUTE_UNUSED
)
12716 char *name
= input_line_pointer
, ch
;
12718 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12719 ++input_line_pointer
;
12720 ch
= *input_line_pointer
;
12721 *input_line_pointer
= '\0';
12723 if (strcmp (name
, "reorder") == 0)
12725 if (mips_opts
.noreorder
)
12728 else if (strcmp (name
, "noreorder") == 0)
12730 if (!mips_opts
.noreorder
)
12731 start_noreorder ();
12733 else if (strncmp (name
, "at=", 3) == 0)
12735 char *s
= name
+ 3;
12737 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
12738 as_bad (_("Unrecognized register name `%s'"), s
);
12740 else if (strcmp (name
, "at") == 0)
12742 mips_opts
.at
= ATREG
;
12744 else if (strcmp (name
, "noat") == 0)
12746 mips_opts
.at
= ZERO
;
12748 else if (strcmp (name
, "macro") == 0)
12750 mips_opts
.warn_about_macros
= 0;
12752 else if (strcmp (name
, "nomacro") == 0)
12754 if (mips_opts
.noreorder
== 0)
12755 as_bad (_("`noreorder' must be set before `nomacro'"));
12756 mips_opts
.warn_about_macros
= 1;
12758 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12760 mips_opts
.nomove
= 0;
12762 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12764 mips_opts
.nomove
= 1;
12766 else if (strcmp (name
, "bopt") == 0)
12768 mips_opts
.nobopt
= 0;
12770 else if (strcmp (name
, "nobopt") == 0)
12772 mips_opts
.nobopt
= 1;
12774 else if (strcmp (name
, "gp=default") == 0)
12775 mips_opts
.gp32
= file_mips_gp32
;
12776 else if (strcmp (name
, "gp=32") == 0)
12777 mips_opts
.gp32
= 1;
12778 else if (strcmp (name
, "gp=64") == 0)
12780 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12781 as_warn ("%s isa does not support 64-bit registers",
12782 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12783 mips_opts
.gp32
= 0;
12785 else if (strcmp (name
, "fp=default") == 0)
12786 mips_opts
.fp32
= file_mips_fp32
;
12787 else if (strcmp (name
, "fp=32") == 0)
12788 mips_opts
.fp32
= 1;
12789 else if (strcmp (name
, "fp=64") == 0)
12791 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12792 as_warn ("%s isa does not support 64-bit floating point registers",
12793 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12794 mips_opts
.fp32
= 0;
12796 else if (strcmp (name
, "softfloat") == 0)
12797 mips_opts
.soft_float
= 1;
12798 else if (strcmp (name
, "hardfloat") == 0)
12799 mips_opts
.soft_float
= 0;
12800 else if (strcmp (name
, "singlefloat") == 0)
12801 mips_opts
.single_float
= 1;
12802 else if (strcmp (name
, "doublefloat") == 0)
12803 mips_opts
.single_float
= 0;
12804 else if (strcmp (name
, "mips16") == 0
12805 || strcmp (name
, "MIPS-16") == 0)
12806 mips_opts
.mips16
= 1;
12807 else if (strcmp (name
, "nomips16") == 0
12808 || strcmp (name
, "noMIPS-16") == 0)
12809 mips_opts
.mips16
= 0;
12810 else if (strcmp (name
, "smartmips") == 0)
12812 if (!ISA_SUPPORTS_SMARTMIPS
)
12813 as_warn ("%s ISA does not support SmartMIPS ASE",
12814 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12815 mips_opts
.ase_smartmips
= 1;
12817 else if (strcmp (name
, "nosmartmips") == 0)
12818 mips_opts
.ase_smartmips
= 0;
12819 else if (strcmp (name
, "mips3d") == 0)
12820 mips_opts
.ase_mips3d
= 1;
12821 else if (strcmp (name
, "nomips3d") == 0)
12822 mips_opts
.ase_mips3d
= 0;
12823 else if (strcmp (name
, "mdmx") == 0)
12824 mips_opts
.ase_mdmx
= 1;
12825 else if (strcmp (name
, "nomdmx") == 0)
12826 mips_opts
.ase_mdmx
= 0;
12827 else if (strcmp (name
, "dsp") == 0)
12829 if (!ISA_SUPPORTS_DSP_ASE
)
12830 as_warn ("%s ISA does not support DSP ASE",
12831 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12832 mips_opts
.ase_dsp
= 1;
12833 mips_opts
.ase_dspr2
= 0;
12835 else if (strcmp (name
, "nodsp") == 0)
12837 mips_opts
.ase_dsp
= 0;
12838 mips_opts
.ase_dspr2
= 0;
12840 else if (strcmp (name
, "dspr2") == 0)
12842 if (!ISA_SUPPORTS_DSPR2_ASE
)
12843 as_warn ("%s ISA does not support DSP R2 ASE",
12844 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12845 mips_opts
.ase_dspr2
= 1;
12846 mips_opts
.ase_dsp
= 1;
12848 else if (strcmp (name
, "nodspr2") == 0)
12850 mips_opts
.ase_dspr2
= 0;
12851 mips_opts
.ase_dsp
= 0;
12853 else if (strcmp (name
, "mt") == 0)
12855 if (!ISA_SUPPORTS_MT_ASE
)
12856 as_warn ("%s ISA does not support MT ASE",
12857 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12858 mips_opts
.ase_mt
= 1;
12860 else if (strcmp (name
, "nomt") == 0)
12861 mips_opts
.ase_mt
= 0;
12862 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12866 /* Permit the user to change the ISA and architecture on the fly.
12867 Needless to say, misuse can cause serious problems. */
12868 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12871 mips_opts
.isa
= file_mips_isa
;
12872 mips_opts
.arch
= file_mips_arch
;
12874 else if (strncmp (name
, "arch=", 5) == 0)
12876 const struct mips_cpu_info
*p
;
12878 p
= mips_parse_cpu("internal use", name
+ 5);
12880 as_bad (_("unknown architecture %s"), name
+ 5);
12883 mips_opts
.arch
= p
->cpu
;
12884 mips_opts
.isa
= p
->isa
;
12887 else if (strncmp (name
, "mips", 4) == 0)
12889 const struct mips_cpu_info
*p
;
12891 p
= mips_parse_cpu("internal use", name
);
12893 as_bad (_("unknown ISA level %s"), name
+ 4);
12896 mips_opts
.arch
= p
->cpu
;
12897 mips_opts
.isa
= p
->isa
;
12901 as_bad (_("unknown ISA or architecture %s"), name
);
12903 switch (mips_opts
.isa
)
12911 mips_opts
.gp32
= 1;
12912 mips_opts
.fp32
= 1;
12919 mips_opts
.gp32
= 0;
12920 mips_opts
.fp32
= 0;
12923 as_bad (_("unknown ISA level %s"), name
+ 4);
12928 mips_opts
.gp32
= file_mips_gp32
;
12929 mips_opts
.fp32
= file_mips_fp32
;
12932 else if (strcmp (name
, "autoextend") == 0)
12933 mips_opts
.noautoextend
= 0;
12934 else if (strcmp (name
, "noautoextend") == 0)
12935 mips_opts
.noautoextend
= 1;
12936 else if (strcmp (name
, "push") == 0)
12938 struct mips_option_stack
*s
;
12940 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12941 s
->next
= mips_opts_stack
;
12942 s
->options
= mips_opts
;
12943 mips_opts_stack
= s
;
12945 else if (strcmp (name
, "pop") == 0)
12947 struct mips_option_stack
*s
;
12949 s
= mips_opts_stack
;
12951 as_bad (_(".set pop with no .set push"));
12954 /* If we're changing the reorder mode we need to handle
12955 delay slots correctly. */
12956 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12957 start_noreorder ();
12958 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12961 mips_opts
= s
->options
;
12962 mips_opts_stack
= s
->next
;
12966 else if (strcmp (name
, "sym32") == 0)
12967 mips_opts
.sym32
= TRUE
;
12968 else if (strcmp (name
, "nosym32") == 0)
12969 mips_opts
.sym32
= FALSE
;
12970 else if (strchr (name
, ','))
12972 /* Generic ".set" directive; use the generic handler. */
12973 *input_line_pointer
= ch
;
12974 input_line_pointer
= name
;
12980 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12982 *input_line_pointer
= ch
;
12983 demand_empty_rest_of_line ();
12986 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12987 .option pic2. It means to generate SVR4 PIC calls. */
12990 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12992 mips_pic
= SVR4_PIC
;
12993 mips_abicalls
= TRUE
;
12995 if (g_switch_seen
&& g_switch_value
!= 0)
12996 as_warn (_("-G may not be used with SVR4 PIC code"));
12997 g_switch_value
= 0;
12999 bfd_set_gp_size (stdoutput
, 0);
13000 demand_empty_rest_of_line ();
13003 /* Handle the .cpload pseudo-op. This is used when generating SVR4
13004 PIC code. It sets the $gp register for the function based on the
13005 function address, which is in the register named in the argument.
13006 This uses a relocation against _gp_disp, which is handled specially
13007 by the linker. The result is:
13008 lui $gp,%hi(_gp_disp)
13009 addiu $gp,$gp,%lo(_gp_disp)
13010 addu $gp,$gp,.cpload argument
13011 The .cpload argument is normally $25 == $t9.
13013 The -mno-shared option changes this to:
13014 lui $gp,%hi(__gnu_local_gp)
13015 addiu $gp,$gp,%lo(__gnu_local_gp)
13016 and the argument is ignored. This saves an instruction, but the
13017 resulting code is not position independent; it uses an absolute
13018 address for __gnu_local_gp. Thus code assembled with -mno-shared
13019 can go into an ordinary executable, but not into a shared library. */
13022 s_cpload (int ignore ATTRIBUTE_UNUSED
)
13028 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13029 .cpload is ignored. */
13030 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13036 /* .cpload should be in a .set noreorder section. */
13037 if (mips_opts
.noreorder
== 0)
13038 as_warn (_(".cpload not in noreorder section"));
13040 reg
= tc_get_register (0);
13042 /* If we need to produce a 64-bit address, we are better off using
13043 the default instruction sequence. */
13044 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
13046 ex
.X_op
= O_symbol
;
13047 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
13049 ex
.X_op_symbol
= NULL
;
13050 ex
.X_add_number
= 0;
13052 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13053 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13056 macro_build_lui (&ex
, mips_gp_register
);
13057 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13058 mips_gp_register
, BFD_RELOC_LO16
);
13060 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
13061 mips_gp_register
, reg
);
13064 demand_empty_rest_of_line ();
13067 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
13068 .cpsetup $reg1, offset|$reg2, label
13070 If offset is given, this results in:
13071 sd $gp, offset($sp)
13072 lui $gp, %hi(%neg(%gp_rel(label)))
13073 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13074 daddu $gp, $gp, $reg1
13076 If $reg2 is given, this results in:
13077 daddu $reg2, $gp, $0
13078 lui $gp, %hi(%neg(%gp_rel(label)))
13079 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13080 daddu $gp, $gp, $reg1
13081 $reg1 is normally $25 == $t9.
13083 The -mno-shared option replaces the last three instructions with
13085 addiu $gp,$gp,%lo(_gp) */
13088 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
13090 expressionS ex_off
;
13091 expressionS ex_sym
;
13094 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
13095 We also need NewABI support. */
13096 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13102 reg1
= tc_get_register (0);
13103 SKIP_WHITESPACE ();
13104 if (*input_line_pointer
!= ',')
13106 as_bad (_("missing argument separator ',' for .cpsetup"));
13110 ++input_line_pointer
;
13111 SKIP_WHITESPACE ();
13112 if (*input_line_pointer
== '$')
13114 mips_cpreturn_register
= tc_get_register (0);
13115 mips_cpreturn_offset
= -1;
13119 mips_cpreturn_offset
= get_absolute_expression ();
13120 mips_cpreturn_register
= -1;
13122 SKIP_WHITESPACE ();
13123 if (*input_line_pointer
!= ',')
13125 as_bad (_("missing argument separator ',' for .cpsetup"));
13129 ++input_line_pointer
;
13130 SKIP_WHITESPACE ();
13131 expression (&ex_sym
);
13134 if (mips_cpreturn_register
== -1)
13136 ex_off
.X_op
= O_constant
;
13137 ex_off
.X_add_symbol
= NULL
;
13138 ex_off
.X_op_symbol
= NULL
;
13139 ex_off
.X_add_number
= mips_cpreturn_offset
;
13141 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
13142 BFD_RELOC_LO16
, SP
);
13145 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
13146 mips_gp_register
, 0);
13148 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
13150 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
13151 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
13154 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
13155 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
13156 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
13158 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
13159 mips_gp_register
, reg1
);
13165 ex
.X_op
= O_symbol
;
13166 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
13167 ex
.X_op_symbol
= NULL
;
13168 ex
.X_add_number
= 0;
13170 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
13171 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
13173 macro_build_lui (&ex
, mips_gp_register
);
13174 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
13175 mips_gp_register
, BFD_RELOC_LO16
);
13180 demand_empty_rest_of_line ();
13184 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
13186 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13187 .cplocal is ignored. */
13188 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13194 mips_gp_register
= tc_get_register (0);
13195 demand_empty_rest_of_line ();
13198 /* Handle the .cprestore pseudo-op. This stores $gp into a given
13199 offset from $sp. The offset is remembered, and after making a PIC
13200 call $gp is restored from that location. */
13203 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
13207 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
13208 .cprestore is ignored. */
13209 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
13215 mips_cprestore_offset
= get_absolute_expression ();
13216 mips_cprestore_valid
= 1;
13218 ex
.X_op
= O_constant
;
13219 ex
.X_add_symbol
= NULL
;
13220 ex
.X_op_symbol
= NULL
;
13221 ex
.X_add_number
= mips_cprestore_offset
;
13224 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
13225 SP
, HAVE_64BIT_ADDRESSES
);
13228 demand_empty_rest_of_line ();
13231 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13232 was given in the preceding .cpsetup, it results in:
13233 ld $gp, offset($sp)
13235 If a register $reg2 was given there, it results in:
13236 daddu $gp, $reg2, $0 */
13239 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
13243 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13244 We also need NewABI support. */
13245 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13252 if (mips_cpreturn_register
== -1)
13254 ex
.X_op
= O_constant
;
13255 ex
.X_add_symbol
= NULL
;
13256 ex
.X_op_symbol
= NULL
;
13257 ex
.X_add_number
= mips_cpreturn_offset
;
13259 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
13262 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
13263 mips_cpreturn_register
, 0);
13266 demand_empty_rest_of_line ();
13269 /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13270 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13271 use in DWARF debug information. */
13274 s_dtprel_internal (size_t bytes
)
13281 if (ex
.X_op
!= O_symbol
)
13283 as_bad (_("Unsupported use of %s"), (bytes
== 8
13286 ignore_rest_of_line ();
13289 p
= frag_more (bytes
);
13290 md_number_to_chars (p
, 0, bytes
);
13291 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
,
13293 ? BFD_RELOC_MIPS_TLS_DTPREL64
13294 : BFD_RELOC_MIPS_TLS_DTPREL32
));
13296 demand_empty_rest_of_line ();
13299 /* Handle .dtprelword. */
13302 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
13304 s_dtprel_internal (4);
13307 /* Handle .dtpreldword. */
13310 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
13312 s_dtprel_internal (8);
13315 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13316 code. It sets the offset to use in gp_rel relocations. */
13319 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
13321 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13322 We also need NewABI support. */
13323 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
13329 mips_gprel_offset
= get_absolute_expression ();
13331 demand_empty_rest_of_line ();
13334 /* Handle the .gpword pseudo-op. This is used when generating PIC
13335 code. It generates a 32 bit GP relative reloc. */
13338 s_gpword (int ignore ATTRIBUTE_UNUSED
)
13340 segment_info_type
*si
;
13341 struct insn_label_list
*l
;
13346 /* When not generating PIC code, this is treated as .word. */
13347 if (mips_pic
!= SVR4_PIC
)
13353 si
= seg_info (now_seg
);
13354 l
= si
->label_list
;
13355 label
= l
!= NULL
? l
->label
: NULL
;
13356 mips_emit_delays ();
13358 mips_align (2, 0, label
);
13359 mips_clear_insn_labels ();
13363 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13365 as_bad (_("Unsupported use of .gpword"));
13366 ignore_rest_of_line ();
13370 md_number_to_chars (p
, 0, 4);
13371 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13372 BFD_RELOC_GPREL32
);
13374 demand_empty_rest_of_line ();
13378 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
13380 segment_info_type
*si
;
13381 struct insn_label_list
*l
;
13386 /* When not generating PIC code, this is treated as .dword. */
13387 if (mips_pic
!= SVR4_PIC
)
13393 si
= seg_info (now_seg
);
13394 l
= si
->label_list
;
13395 label
= l
!= NULL
? l
->label
: NULL
;
13396 mips_emit_delays ();
13398 mips_align (3, 0, label
);
13399 mips_clear_insn_labels ();
13403 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
13405 as_bad (_("Unsupported use of .gpdword"));
13406 ignore_rest_of_line ();
13410 md_number_to_chars (p
, 0, 8);
13411 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
13412 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
13414 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
13415 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
13416 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
13418 demand_empty_rest_of_line ();
13421 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
13422 tables in SVR4 PIC code. */
13425 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
13429 /* This is ignored when not generating SVR4 PIC code. */
13430 if (mips_pic
!= SVR4_PIC
)
13436 /* Add $gp to the register named as an argument. */
13438 reg
= tc_get_register (0);
13439 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
13442 demand_empty_rest_of_line ();
13445 /* Handle the .insn pseudo-op. This marks instruction labels in
13446 mips16 mode. This permits the linker to handle them specially,
13447 such as generating jalx instructions when needed. We also make
13448 them odd for the duration of the assembly, in order to generate the
13449 right sort of code. We will make them even in the adjust_symtab
13450 routine, while leaving them marked. This is convenient for the
13451 debugger and the disassembler. The linker knows to make them odd
13455 s_insn (int ignore ATTRIBUTE_UNUSED
)
13457 mips16_mark_labels ();
13459 demand_empty_rest_of_line ();
13462 /* Handle a .stabn directive. We need these in order to mark a label
13463 as being a mips16 text label correctly. Sometimes the compiler
13464 will emit a label, followed by a .stabn, and then switch sections.
13465 If the label and .stabn are in mips16 mode, then the label is
13466 really a mips16 text label. */
13469 s_mips_stab (int type
)
13472 mips16_mark_labels ();
13477 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
13480 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
13487 name
= input_line_pointer
;
13488 c
= get_symbol_end ();
13489 symbolP
= symbol_find_or_make (name
);
13490 S_SET_WEAK (symbolP
);
13491 *input_line_pointer
= c
;
13493 SKIP_WHITESPACE ();
13495 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
13497 if (S_IS_DEFINED (symbolP
))
13499 as_bad ("ignoring attempt to redefine symbol %s",
13500 S_GET_NAME (symbolP
));
13501 ignore_rest_of_line ();
13505 if (*input_line_pointer
== ',')
13507 ++input_line_pointer
;
13508 SKIP_WHITESPACE ();
13512 if (exp
.X_op
!= O_symbol
)
13514 as_bad ("bad .weakext directive");
13515 ignore_rest_of_line ();
13518 symbol_set_value_expression (symbolP
, &exp
);
13521 demand_empty_rest_of_line ();
13524 /* Parse a register string into a number. Called from the ECOFF code
13525 to parse .frame. The argument is non-zero if this is the frame
13526 register, so that we can record it in mips_frame_reg. */
13529 tc_get_register (int frame
)
13533 SKIP_WHITESPACE ();
13534 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13538 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13539 mips_frame_reg_valid
= 1;
13540 mips_cprestore_valid
= 0;
13546 md_section_align (asection
*seg
, valueT addr
)
13548 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13552 /* We don't need to align ELF sections to the full alignment.
13553 However, Irix 5 may prefer that we align them at least to a 16
13554 byte boundary. We don't bother to align the sections if we
13555 are targeted for an embedded system. */
13556 if (strncmp (TARGET_OS
, "elf", 3) == 0)
13562 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13565 /* Utility routine, called from above as well. If called while the
13566 input file is still being read, it's only an approximation. (For
13567 example, a symbol may later become defined which appeared to be
13568 undefined earlier.) */
13571 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13576 if (g_switch_value
> 0)
13578 const char *symname
;
13581 /* Find out whether this symbol can be referenced off the $gp
13582 register. It can be if it is smaller than the -G size or if
13583 it is in the .sdata or .sbss section. Certain symbols can
13584 not be referenced off the $gp, although it appears as though
13586 symname
= S_GET_NAME (sym
);
13587 if (symname
!= (const char *) NULL
13588 && (strcmp (symname
, "eprol") == 0
13589 || strcmp (symname
, "etext") == 0
13590 || strcmp (symname
, "_gp") == 0
13591 || strcmp (symname
, "edata") == 0
13592 || strcmp (symname
, "_fbss") == 0
13593 || strcmp (symname
, "_fdata") == 0
13594 || strcmp (symname
, "_ftext") == 0
13595 || strcmp (symname
, "end") == 0
13596 || strcmp (symname
, "_gp_disp") == 0))
13598 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13600 #ifndef NO_ECOFF_DEBUGGING
13601 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13602 && (symbol_get_obj (sym
)->ecoff_extern_size
13603 <= g_switch_value
))
13605 /* We must defer this decision until after the whole
13606 file has been read, since there might be a .extern
13607 after the first use of this symbol. */
13608 || (before_relaxing
13609 #ifndef NO_ECOFF_DEBUGGING
13610 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13612 && S_GET_VALUE (sym
) == 0)
13613 || (S_GET_VALUE (sym
) != 0
13614 && S_GET_VALUE (sym
) <= g_switch_value
)))
13618 const char *segname
;
13620 segname
= segment_name (S_GET_SEGMENT (sym
));
13621 assert (strcmp (segname
, ".lit8") != 0
13622 && strcmp (segname
, ".lit4") != 0);
13623 change
= (strcmp (segname
, ".sdata") != 0
13624 && strcmp (segname
, ".sbss") != 0
13625 && strncmp (segname
, ".sdata.", 7) != 0
13626 && strncmp (segname
, ".sbss.", 6) != 0
13627 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
13628 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13633 /* We are not optimizing for the $gp register. */
13638 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13641 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13645 /* Handle the case of a symbol equated to another symbol. */
13646 while (symbol_equated_reloc_p (sym
))
13650 /* It's possible to get a loop here in a badly written program. */
13651 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13657 if (symbol_section_p (sym
))
13660 symsec
= S_GET_SEGMENT (sym
);
13662 /* This must duplicate the test in adjust_reloc_syms. */
13663 return (symsec
!= &bfd_und_section
13664 && symsec
!= &bfd_abs_section
13665 && !bfd_is_com_section (symsec
)
13666 && !s_is_linkonce (sym
, segtype
)
13668 /* A global or weak symbol is treated as external. */
13669 && (!IS_ELF
|| (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13675 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13676 extended opcode. SEC is the section the frag is in. */
13679 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13682 const struct mips16_immed_operand
*op
;
13684 int mintiny
, maxtiny
;
13688 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13690 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13693 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13694 op
= mips16_immed_operands
;
13695 while (op
->type
!= type
)
13698 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13703 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13706 maxtiny
= 1 << op
->nbits
;
13711 maxtiny
= (1 << op
->nbits
) - 1;
13716 mintiny
= - (1 << (op
->nbits
- 1));
13717 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13720 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13721 val
= S_GET_VALUE (fragp
->fr_symbol
);
13722 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13728 /* We won't have the section when we are called from
13729 mips_relax_frag. However, we will always have been called
13730 from md_estimate_size_before_relax first. If this is a
13731 branch to a different section, we mark it as such. If SEC is
13732 NULL, and the frag is not marked, then it must be a branch to
13733 the same section. */
13736 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13741 /* Must have been called from md_estimate_size_before_relax. */
13744 fragp
->fr_subtype
=
13745 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13747 /* FIXME: We should support this, and let the linker
13748 catch branches and loads that are out of range. */
13749 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13750 _("unsupported PC relative reference to different section"));
13754 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13755 /* Assume non-extended on the first relaxation pass.
13756 The address we have calculated will be bogus if this is
13757 a forward branch to another frag, as the forward frag
13758 will have fr_address == 0. */
13762 /* In this case, we know for sure that the symbol fragment is in
13763 the same section. If the relax_marker of the symbol fragment
13764 differs from the relax_marker of this fragment, we have not
13765 yet adjusted the symbol fragment fr_address. We want to add
13766 in STRETCH in order to get a better estimate of the address.
13767 This particularly matters because of the shift bits. */
13769 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13773 /* Adjust stretch for any alignment frag. Note that if have
13774 been expanding the earlier code, the symbol may be
13775 defined in what appears to be an earlier frag. FIXME:
13776 This doesn't handle the fr_subtype field, which specifies
13777 a maximum number of bytes to skip when doing an
13779 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13781 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13784 stretch
= - ((- stretch
)
13785 & ~ ((1 << (int) f
->fr_offset
) - 1));
13787 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13796 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13798 /* The base address rules are complicated. The base address of
13799 a branch is the following instruction. The base address of a
13800 PC relative load or add is the instruction itself, but if it
13801 is in a delay slot (in which case it can not be extended) use
13802 the address of the instruction whose delay slot it is in. */
13803 if (type
== 'p' || type
== 'q')
13807 /* If we are currently assuming that this frag should be
13808 extended, then, the current address is two bytes
13810 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13813 /* Ignore the low bit in the target, since it will be set
13814 for a text label. */
13815 if ((val
& 1) != 0)
13818 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13820 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13823 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13825 /* Branch offsets have an implicit 0 in the lowest bit. */
13826 if (type
== 'p' || type
== 'q')
13829 /* If any of the shifted bits are set, we must use an extended
13830 opcode. If the address depends on the size of this
13831 instruction, this can lead to a loop, so we arrange to always
13832 use an extended opcode. We only check this when we are in
13833 the main relaxation loop, when SEC is NULL. */
13834 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13836 fragp
->fr_subtype
=
13837 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13841 /* If we are about to mark a frag as extended because the value
13842 is precisely maxtiny + 1, then there is a chance of an
13843 infinite loop as in the following code:
13848 In this case when the la is extended, foo is 0x3fc bytes
13849 away, so the la can be shrunk, but then foo is 0x400 away, so
13850 the la must be extended. To avoid this loop, we mark the
13851 frag as extended if it was small, and is about to become
13852 extended with a value of maxtiny + 1. */
13853 if (val
== ((maxtiny
+ 1) << op
->shift
)
13854 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13857 fragp
->fr_subtype
=
13858 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13862 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13863 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13865 if ((val
& ((1 << op
->shift
) - 1)) != 0
13866 || val
< (mintiny
<< op
->shift
)
13867 || val
> (maxtiny
<< op
->shift
))
13873 /* Compute the length of a branch sequence, and adjust the
13874 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13875 worst-case length is computed, with UPDATE being used to indicate
13876 whether an unconditional (-1), branch-likely (+1) or regular (0)
13877 branch is to be computed. */
13879 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13881 bfd_boolean toofar
;
13885 && S_IS_DEFINED (fragp
->fr_symbol
)
13886 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13891 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13893 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13897 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13900 /* If the symbol is not defined or it's in a different segment,
13901 assume the user knows what's going on and emit a short
13907 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13909 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13910 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13911 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13917 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13920 if (mips_pic
!= NO_PIC
)
13922 /* Additional space for PIC loading of target address. */
13924 if (mips_opts
.isa
== ISA_MIPS1
)
13925 /* Additional space for $at-stabilizing nop. */
13929 /* If branch is conditional. */
13930 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13937 /* Estimate the size of a frag before relaxing. Unless this is the
13938 mips16, we are not really relaxing here, and the final size is
13939 encoded in the subtype information. For the mips16, we have to
13940 decide whether we are using an extended opcode or not. */
13943 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13947 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13950 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13952 return fragp
->fr_var
;
13955 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13956 /* We don't want to modify the EXTENDED bit here; it might get us
13957 into infinite loops. We change it only in mips_relax_frag(). */
13958 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13960 if (mips_pic
== NO_PIC
)
13961 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13962 else if (mips_pic
== SVR4_PIC
)
13963 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13964 else if (mips_pic
== VXWORKS_PIC
)
13965 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13972 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13973 return -RELAX_FIRST (fragp
->fr_subtype
);
13976 return -RELAX_SECOND (fragp
->fr_subtype
);
13979 /* This is called to see whether a reloc against a defined symbol
13980 should be converted into a reloc against a section. */
13983 mips_fix_adjustable (fixS
*fixp
)
13985 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13986 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13989 if (fixp
->fx_addsy
== NULL
)
13992 /* If symbol SYM is in a mergeable section, relocations of the form
13993 SYM + 0 can usually be made section-relative. The mergeable data
13994 is then identified by the section offset rather than by the symbol.
13996 However, if we're generating REL LO16 relocations, the offset is split
13997 between the LO16 and parterning high part relocation. The linker will
13998 need to recalculate the complete offset in order to correctly identify
14001 The linker has traditionally not looked for the parterning high part
14002 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
14003 placed anywhere. Rather than break backwards compatibility by changing
14004 this, it seems better not to force the issue, and instead keep the
14005 original symbol. This will work with either linker behavior. */
14006 if ((lo16_reloc_p (fixp
->fx_r_type
)
14007 || reloc_needs_lo_p (fixp
->fx_r_type
))
14008 && HAVE_IN_PLACE_ADDENDS
14009 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
14013 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14014 to a floating-point stub. The same is true for non-R_MIPS16_26
14015 relocations against MIPS16 functions; in this case, the stub becomes
14016 the function's canonical address.
14018 Floating-point stubs are stored in unique .mips16.call.* or
14019 .mips16.fn.* sections. If a stub T for function F is in section S,
14020 the first relocation in section S must be against F; this is how the
14021 linker determines the target function. All relocations that might
14022 resolve to T must also be against F. We therefore have the following
14023 restrictions, which are given in an intentionally-redundant way:
14025 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14028 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14029 if that stub might be used.
14031 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14034 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14035 that stub might be used.
14037 There is a further restriction:
14039 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14040 on targets with in-place addends; the relocation field cannot
14041 encode the low bit.
14043 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14044 against a MIPS16 symbol.
14046 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14047 relocation against some symbol R, no relocation against R may be
14048 reduced. (Note that this deals with (2) as well as (1) because
14049 relocations against global symbols will never be reduced on ELF
14050 targets.) This approach is a little simpler than trying to detect
14051 stub sections, and gives the "all or nothing" per-symbol consistency
14052 that we have for MIPS16 symbols. */
14054 && fixp
->fx_subsy
== NULL
14055 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
14056 || *symbol_get_tc (fixp
->fx_addsy
)))
14063 /* Translate internal representation of relocation info to BFD target
14067 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
14069 static arelent
*retval
[4];
14071 bfd_reloc_code_real_type code
;
14073 memset (retval
, 0, sizeof(retval
));
14074 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
14075 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
14076 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
14077 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
14079 if (fixp
->fx_pcrel
)
14081 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
14083 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14084 Relocations want only the symbol offset. */
14085 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
14088 /* A gruesome hack which is a result of the gruesome gas
14089 reloc handling. What's worse, for COFF (as opposed to
14090 ECOFF), we might need yet another copy of reloc->address.
14091 See bfd_install_relocation. */
14092 reloc
->addend
+= reloc
->address
;
14096 reloc
->addend
= fixp
->fx_addnumber
;
14098 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
14099 entry to be used in the relocation's section offset. */
14100 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
14102 reloc
->address
= reloc
->addend
;
14106 code
= fixp
->fx_r_type
;
14108 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
14109 if (reloc
->howto
== NULL
)
14111 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
14112 _("Can not represent %s relocation in this object file format"),
14113 bfd_get_reloc_code_name (code
));
14120 /* Relax a machine dependent frag. This returns the amount by which
14121 the current size of the frag should change. */
14124 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
14126 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14128 offsetT old_var
= fragp
->fr_var
;
14130 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
14132 return fragp
->fr_var
- old_var
;
14135 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
14138 if (mips16_extended_frag (fragp
, NULL
, stretch
))
14140 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14142 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
14147 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14149 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
14156 /* Convert a machine dependent frag. */
14159 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
14161 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
14164 unsigned long insn
;
14168 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
14170 if (target_big_endian
)
14171 insn
= bfd_getb32 (buf
);
14173 insn
= bfd_getl32 (buf
);
14175 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
14177 /* We generate a fixup instead of applying it right now
14178 because, if there are linker relaxations, we're going to
14179 need the relocations. */
14180 exp
.X_op
= O_symbol
;
14181 exp
.X_add_symbol
= fragp
->fr_symbol
;
14182 exp
.X_add_number
= fragp
->fr_offset
;
14184 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14185 4, &exp
, TRUE
, BFD_RELOC_16_PCREL_S2
);
14186 fixp
->fx_file
= fragp
->fr_file
;
14187 fixp
->fx_line
= fragp
->fr_line
;
14189 md_number_to_chars ((char *) buf
, insn
, 4);
14196 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14197 _("relaxed out-of-range branch into a jump"));
14199 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
14202 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14204 /* Reverse the branch. */
14205 switch ((insn
>> 28) & 0xf)
14208 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
14209 have the condition reversed by tweaking a single
14210 bit, and their opcodes all have 0x4???????. */
14211 assert ((insn
& 0xf1000000) == 0x41000000);
14212 insn
^= 0x00010000;
14216 /* bltz 0x04000000 bgez 0x04010000
14217 bltzal 0x04100000 bgezal 0x04110000 */
14218 assert ((insn
& 0xfc0e0000) == 0x04000000);
14219 insn
^= 0x00010000;
14223 /* beq 0x10000000 bne 0x14000000
14224 blez 0x18000000 bgtz 0x1c000000 */
14225 insn
^= 0x04000000;
14233 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14235 /* Clear the and-link bit. */
14236 assert ((insn
& 0xfc1c0000) == 0x04100000);
14238 /* bltzal 0x04100000 bgezal 0x04110000
14239 bltzall 0x04120000 bgezall 0x04130000 */
14240 insn
&= ~0x00100000;
14243 /* Branch over the branch (if the branch was likely) or the
14244 full jump (not likely case). Compute the offset from the
14245 current instruction to branch to. */
14246 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14250 /* How many bytes in instructions we've already emitted? */
14251 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14252 /* How many bytes in instructions from here to the end? */
14253 i
= fragp
->fr_var
- i
;
14255 /* Convert to instruction count. */
14257 /* Branch counts from the next instruction. */
14260 /* Branch over the jump. */
14261 md_number_to_chars ((char *) buf
, insn
, 4);
14265 md_number_to_chars ((char *) buf
, 0, 4);
14268 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
14270 /* beql $0, $0, 2f */
14272 /* Compute the PC offset from the current instruction to
14273 the end of the variable frag. */
14274 /* How many bytes in instructions we've already emitted? */
14275 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
14276 /* How many bytes in instructions from here to the end? */
14277 i
= fragp
->fr_var
- i
;
14278 /* Convert to instruction count. */
14280 /* Don't decrement i, because we want to branch over the
14284 md_number_to_chars ((char *) buf
, insn
, 4);
14287 md_number_to_chars ((char *) buf
, 0, 4);
14292 if (mips_pic
== NO_PIC
)
14295 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
14296 ? 0x0c000000 : 0x08000000);
14297 exp
.X_op
= O_symbol
;
14298 exp
.X_add_symbol
= fragp
->fr_symbol
;
14299 exp
.X_add_number
= fragp
->fr_offset
;
14301 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14302 4, &exp
, FALSE
, BFD_RELOC_MIPS_JMP
);
14303 fixp
->fx_file
= fragp
->fr_file
;
14304 fixp
->fx_line
= fragp
->fr_line
;
14306 md_number_to_chars ((char *) buf
, insn
, 4);
14311 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
14312 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
14313 exp
.X_op
= O_symbol
;
14314 exp
.X_add_symbol
= fragp
->fr_symbol
;
14315 exp
.X_add_number
= fragp
->fr_offset
;
14317 if (fragp
->fr_offset
)
14319 exp
.X_add_symbol
= make_expr_symbol (&exp
);
14320 exp
.X_add_number
= 0;
14323 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14324 4, &exp
, FALSE
, BFD_RELOC_MIPS_GOT16
);
14325 fixp
->fx_file
= fragp
->fr_file
;
14326 fixp
->fx_line
= fragp
->fr_line
;
14328 md_number_to_chars ((char *) buf
, insn
, 4);
14331 if (mips_opts
.isa
== ISA_MIPS1
)
14334 md_number_to_chars ((char *) buf
, 0, 4);
14338 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14339 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
14341 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
14342 4, &exp
, FALSE
, BFD_RELOC_LO16
);
14343 fixp
->fx_file
= fragp
->fr_file
;
14344 fixp
->fx_line
= fragp
->fr_line
;
14346 md_number_to_chars ((char *) buf
, insn
, 4);
14350 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
14355 md_number_to_chars ((char *) buf
, insn
, 4);
14360 assert (buf
== (bfd_byte
*)fragp
->fr_literal
14361 + fragp
->fr_fix
+ fragp
->fr_var
);
14363 fragp
->fr_fix
+= fragp
->fr_var
;
14368 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
14371 const struct mips16_immed_operand
*op
;
14372 bfd_boolean small
, ext
;
14375 unsigned long insn
;
14376 bfd_boolean use_extend
;
14377 unsigned short extend
;
14379 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
14380 op
= mips16_immed_operands
;
14381 while (op
->type
!= type
)
14384 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
14395 resolve_symbol_value (fragp
->fr_symbol
);
14396 val
= S_GET_VALUE (fragp
->fr_symbol
);
14401 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
14403 /* The rules for the base address of a PC relative reloc are
14404 complicated; see mips16_extended_frag. */
14405 if (type
== 'p' || type
== 'q')
14410 /* Ignore the low bit in the target, since it will be
14411 set for a text label. */
14412 if ((val
& 1) != 0)
14415 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
14417 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
14420 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
14423 /* Make sure the section winds up with the alignment we have
14426 record_alignment (asec
, op
->shift
);
14430 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
14431 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
14432 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
14433 _("extended instruction in delay slot"));
14435 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
14437 if (target_big_endian
)
14438 insn
= bfd_getb16 (buf
);
14440 insn
= bfd_getl16 (buf
);
14442 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
14443 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
14444 small
, ext
, &insn
, &use_extend
, &extend
);
14448 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
14449 fragp
->fr_fix
+= 2;
14453 md_number_to_chars ((char *) buf
, insn
, 2);
14454 fragp
->fr_fix
+= 2;
14462 first
= RELAX_FIRST (fragp
->fr_subtype
);
14463 second
= RELAX_SECOND (fragp
->fr_subtype
);
14464 fixp
= (fixS
*) fragp
->fr_opcode
;
14466 /* Possibly emit a warning if we've chosen the longer option. */
14467 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
14468 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
14470 const char *msg
= macro_warning (fragp
->fr_subtype
);
14472 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
14475 /* Go through all the fixups for the first sequence. Disable them
14476 (by marking them as done) if we're going to use the second
14477 sequence instead. */
14479 && fixp
->fx_frag
== fragp
14480 && fixp
->fx_where
< fragp
->fr_fix
- second
)
14482 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14484 fixp
= fixp
->fx_next
;
14487 /* Go through the fixups for the second sequence. Disable them if
14488 we're going to use the first sequence, otherwise adjust their
14489 addresses to account for the relaxation. */
14490 while (fixp
&& fixp
->fx_frag
== fragp
)
14492 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14493 fixp
->fx_where
-= first
;
14496 fixp
= fixp
->fx_next
;
14499 /* Now modify the frag contents. */
14500 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
14504 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
14505 memmove (start
, start
+ first
, second
);
14506 fragp
->fr_fix
-= first
;
14509 fragp
->fr_fix
-= second
;
14515 /* This function is called after the relocs have been generated.
14516 We've been storing mips16 text labels as odd. Here we convert them
14517 back to even for the convenience of the debugger. */
14520 mips_frob_file_after_relocs (void)
14523 unsigned int count
, i
;
14528 syms
= bfd_get_outsymbols (stdoutput
);
14529 count
= bfd_get_symcount (stdoutput
);
14530 for (i
= 0; i
< count
; i
++, syms
++)
14532 if (ELF_ST_IS_MIPS16 (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
14533 && ((*syms
)->value
& 1) != 0)
14535 (*syms
)->value
&= ~1;
14536 /* If the symbol has an odd size, it was probably computed
14537 incorrectly, so adjust that as well. */
14538 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
14539 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
14546 /* This function is called whenever a label is defined. It is used
14547 when handling branch delays; if a branch has a label, we assume we
14548 can not move it. */
14551 mips_define_label (symbolS
*sym
)
14553 segment_info_type
*si
= seg_info (now_seg
);
14554 struct insn_label_list
*l
;
14556 if (free_insn_labels
== NULL
)
14557 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14560 l
= free_insn_labels
;
14561 free_insn_labels
= l
->next
;
14565 l
->next
= si
->label_list
;
14566 si
->label_list
= l
;
14569 dwarf2_emit_label (sym
);
14573 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14575 /* Some special processing for a MIPS ELF file. */
14578 mips_elf_final_processing (void)
14580 /* Write out the register information. */
14581 if (mips_abi
!= N64_ABI
)
14585 s
.ri_gprmask
= mips_gprmask
;
14586 s
.ri_cprmask
[0] = mips_cprmask
[0];
14587 s
.ri_cprmask
[1] = mips_cprmask
[1];
14588 s
.ri_cprmask
[2] = mips_cprmask
[2];
14589 s
.ri_cprmask
[3] = mips_cprmask
[3];
14590 /* The gp_value field is set by the MIPS ELF backend. */
14592 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14593 ((Elf32_External_RegInfo
*)
14594 mips_regmask_frag
));
14598 Elf64_Internal_RegInfo s
;
14600 s
.ri_gprmask
= mips_gprmask
;
14602 s
.ri_cprmask
[0] = mips_cprmask
[0];
14603 s
.ri_cprmask
[1] = mips_cprmask
[1];
14604 s
.ri_cprmask
[2] = mips_cprmask
[2];
14605 s
.ri_cprmask
[3] = mips_cprmask
[3];
14606 /* The gp_value field is set by the MIPS ELF backend. */
14608 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14609 ((Elf64_External_RegInfo
*)
14610 mips_regmask_frag
));
14613 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14614 sort of BFD interface for this. */
14615 if (mips_any_noreorder
)
14616 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14617 if (mips_pic
!= NO_PIC
)
14619 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14620 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14623 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14625 /* Set MIPS ELF flags for ASEs. */
14626 /* We may need to define a new flag for DSP ASE, and set this flag when
14627 file_ase_dsp is true. */
14628 /* Same for DSP R2. */
14629 /* We may need to define a new flag for MT ASE, and set this flag when
14630 file_ase_mt is true. */
14631 if (file_ase_mips16
)
14632 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14633 #if 0 /* XXX FIXME */
14634 if (file_ase_mips3d
)
14635 elf_elfheader (stdoutput
)->e_flags
|= ???;
14638 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14640 /* Set the MIPS ELF ABI flags. */
14641 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14642 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14643 else if (mips_abi
== O64_ABI
)
14644 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14645 else if (mips_abi
== EABI_ABI
)
14647 if (!file_mips_gp32
)
14648 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14650 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14652 else if (mips_abi
== N32_ABI
)
14653 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14655 /* Nothing to do for N64_ABI. */
14657 if (mips_32bitmode
)
14658 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14660 #if 0 /* XXX FIXME */
14661 /* 32 bit code with 64 bit FP registers. */
14662 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14663 elf_elfheader (stdoutput
)->e_flags
|= ???;
14667 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14669 typedef struct proc
{
14671 symbolS
*func_end_sym
;
14672 unsigned long reg_mask
;
14673 unsigned long reg_offset
;
14674 unsigned long fpreg_mask
;
14675 unsigned long fpreg_offset
;
14676 unsigned long frame_offset
;
14677 unsigned long frame_reg
;
14678 unsigned long pc_reg
;
14681 static procS cur_proc
;
14682 static procS
*cur_proc_ptr
;
14683 static int numprocs
;
14685 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1" and a normal
14689 mips_nop_opcode (void)
14691 return seg_info (now_seg
)->tc_segment_info_data
.mips16
;
14694 /* Fill in an rs_align_code fragment. This only needs to do something
14695 for MIPS16 code, where 0 is not a nop. */
14698 mips_handle_align (fragS
*fragp
)
14702 if (fragp
->fr_type
!= rs_align_code
)
14705 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14710 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14716 md_number_to_chars (p
, mips16_nop_insn
.insn_opcode
, 2);
14722 md_obj_begin (void)
14729 /* Check for premature end, nesting errors, etc. */
14731 as_warn (_("missing .end at end of assembly"));
14740 if (*input_line_pointer
== '-')
14742 ++input_line_pointer
;
14745 if (!ISDIGIT (*input_line_pointer
))
14746 as_bad (_("expected simple number"));
14747 if (input_line_pointer
[0] == '0')
14749 if (input_line_pointer
[1] == 'x')
14751 input_line_pointer
+= 2;
14752 while (ISXDIGIT (*input_line_pointer
))
14755 val
|= hex_value (*input_line_pointer
++);
14757 return negative
? -val
: val
;
14761 ++input_line_pointer
;
14762 while (ISDIGIT (*input_line_pointer
))
14765 val
|= *input_line_pointer
++ - '0';
14767 return negative
? -val
: val
;
14770 if (!ISDIGIT (*input_line_pointer
))
14772 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14773 *input_line_pointer
, *input_line_pointer
);
14774 as_warn (_("invalid number"));
14777 while (ISDIGIT (*input_line_pointer
))
14780 val
+= *input_line_pointer
++ - '0';
14782 return negative
? -val
: val
;
14785 /* The .file directive; just like the usual .file directive, but there
14786 is an initial number which is the ECOFF file index. In the non-ECOFF
14787 case .file implies DWARF-2. */
14790 s_mips_file (int x ATTRIBUTE_UNUSED
)
14792 static int first_file_directive
= 0;
14794 if (ECOFF_DEBUGGING
)
14803 filename
= dwarf2_directive_file (0);
14805 /* Versions of GCC up to 3.1 start files with a ".file"
14806 directive even for stabs output. Make sure that this
14807 ".file" is handled. Note that you need a version of GCC
14808 after 3.1 in order to support DWARF-2 on MIPS. */
14809 if (filename
!= NULL
&& ! first_file_directive
)
14811 (void) new_logical_line (filename
, -1);
14812 s_app_file_string (filename
, 0);
14814 first_file_directive
= 1;
14818 /* The .loc directive, implying DWARF-2. */
14821 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14823 if (!ECOFF_DEBUGGING
)
14824 dwarf2_directive_loc (0);
14827 /* The .end directive. */
14830 s_mips_end (int x ATTRIBUTE_UNUSED
)
14834 /* Following functions need their own .frame and .cprestore directives. */
14835 mips_frame_reg_valid
= 0;
14836 mips_cprestore_valid
= 0;
14838 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14841 demand_empty_rest_of_line ();
14846 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14847 as_warn (_(".end not in text section"));
14851 as_warn (_(".end directive without a preceding .ent directive."));
14852 demand_empty_rest_of_line ();
14858 assert (S_GET_NAME (p
));
14859 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14860 as_warn (_(".end symbol does not match .ent symbol."));
14862 if (debug_type
== DEBUG_STABS
)
14863 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14867 as_warn (_(".end directive missing or unknown symbol"));
14870 /* Create an expression to calculate the size of the function. */
14871 if (p
&& cur_proc_ptr
)
14873 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14874 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14877 exp
->X_op
= O_subtract
;
14878 exp
->X_add_symbol
= symbol_temp_new_now ();
14879 exp
->X_op_symbol
= p
;
14880 exp
->X_add_number
= 0;
14882 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14885 /* Generate a .pdr section. */
14886 if (IS_ELF
&& !ECOFF_DEBUGGING
&& mips_flag_pdr
)
14888 segT saved_seg
= now_seg
;
14889 subsegT saved_subseg
= now_subseg
;
14894 dot
= frag_now_fix ();
14896 #ifdef md_flush_pending_output
14897 md_flush_pending_output ();
14901 subseg_set (pdr_seg
, 0);
14903 /* Write the symbol. */
14904 exp
.X_op
= O_symbol
;
14905 exp
.X_add_symbol
= p
;
14906 exp
.X_add_number
= 0;
14907 emit_expr (&exp
, 4);
14909 fragp
= frag_more (7 * 4);
14911 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14912 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14913 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14914 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14915 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14916 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14917 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14919 subseg_set (saved_seg
, saved_subseg
);
14921 #endif /* OBJ_ELF */
14923 cur_proc_ptr
= NULL
;
14926 /* The .aent and .ent directives. */
14929 s_mips_ent (int aent
)
14933 symbolP
= get_symbol ();
14934 if (*input_line_pointer
== ',')
14935 ++input_line_pointer
;
14936 SKIP_WHITESPACE ();
14937 if (ISDIGIT (*input_line_pointer
)
14938 || *input_line_pointer
== '-')
14941 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14942 as_warn (_(".ent or .aent not in text section."));
14944 if (!aent
&& cur_proc_ptr
)
14945 as_warn (_("missing .end"));
14949 /* This function needs its own .frame and .cprestore directives. */
14950 mips_frame_reg_valid
= 0;
14951 mips_cprestore_valid
= 0;
14953 cur_proc_ptr
= &cur_proc
;
14954 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14956 cur_proc_ptr
->func_sym
= symbolP
;
14958 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14962 if (debug_type
== DEBUG_STABS
)
14963 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14964 S_GET_NAME (symbolP
));
14967 demand_empty_rest_of_line ();
14970 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14971 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14972 s_mips_frame is used so that we can set the PDR information correctly.
14973 We can't use the ecoff routines because they make reference to the ecoff
14974 symbol table (in the mdebug section). */
14977 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14980 if (IS_ELF
&& !ECOFF_DEBUGGING
)
14984 if (cur_proc_ptr
== (procS
*) NULL
)
14986 as_warn (_(".frame outside of .ent"));
14987 demand_empty_rest_of_line ();
14991 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14993 SKIP_WHITESPACE ();
14994 if (*input_line_pointer
++ != ','
14995 || get_absolute_expression_and_terminator (&val
) != ',')
14997 as_warn (_("Bad .frame directive"));
14998 --input_line_pointer
;
14999 demand_empty_rest_of_line ();
15003 cur_proc_ptr
->frame_offset
= val
;
15004 cur_proc_ptr
->pc_reg
= tc_get_register (0);
15006 demand_empty_rest_of_line ();
15009 #endif /* OBJ_ELF */
15013 /* The .fmask and .mask directives. If the mdebug section is present
15014 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
15015 embedded targets, s_mips_mask is used so that we can set the PDR
15016 information correctly. We can't use the ecoff routines because they
15017 make reference to the ecoff symbol table (in the mdebug section). */
15020 s_mips_mask (int reg_type
)
15023 if (IS_ELF
&& !ECOFF_DEBUGGING
)
15027 if (cur_proc_ptr
== (procS
*) NULL
)
15029 as_warn (_(".mask/.fmask outside of .ent"));
15030 demand_empty_rest_of_line ();
15034 if (get_absolute_expression_and_terminator (&mask
) != ',')
15036 as_warn (_("Bad .mask/.fmask directive"));
15037 --input_line_pointer
;
15038 demand_empty_rest_of_line ();
15042 off
= get_absolute_expression ();
15044 if (reg_type
== 'F')
15046 cur_proc_ptr
->fpreg_mask
= mask
;
15047 cur_proc_ptr
->fpreg_offset
= off
;
15051 cur_proc_ptr
->reg_mask
= mask
;
15052 cur_proc_ptr
->reg_offset
= off
;
15055 demand_empty_rest_of_line ();
15058 #endif /* OBJ_ELF */
15059 s_ignore (reg_type
);
15062 /* A table describing all the processors gas knows about. Names are
15063 matched in the order listed.
15065 To ease comparison, please keep this table in the same order as
15066 gcc's mips_cpu_info_table[]. */
15067 static const struct mips_cpu_info mips_cpu_info_table
[] =
15069 /* Entries for generic ISAs */
15070 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
15071 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
15072 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
15073 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
15074 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
15075 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
15076 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15077 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
15078 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
15081 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
15082 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
15083 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
15086 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
15089 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
15090 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
15091 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
15092 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
15093 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
15094 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
15095 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
15096 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
15097 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
15098 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
15099 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
15100 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
15101 /* ST Microelectronics Loongson 2E and 2F cores */
15102 { "loongson2e", 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
15103 { "loongson2f", 0, ISA_MIPS3
, CPU_LOONGSON_2F
},
15106 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
15107 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
15108 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
15109 { "r14000", 0, ISA_MIPS4
, CPU_R14000
},
15110 { "r16000", 0, ISA_MIPS4
, CPU_R16000
},
15111 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
15112 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
15113 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
15114 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
15115 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
15116 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
15117 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
15118 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
15119 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
15120 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
15123 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
15124 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
15125 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
15126 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
15128 /* MIPS 32 Release 2 */
15129 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15130 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15131 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15132 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15133 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15134 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15135 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15136 { "24kf2_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15137 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15138 { "24kf1_1", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15139 /* Deprecated forms of the above. */
15140 { "24kfx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15141 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
15142 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15143 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15144 { "24kef2_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15145 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15146 { "24kef1_1", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15147 /* Deprecated forms of the above. */
15148 { "24kefx", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15149 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
15150 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15151 { "34kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15152 ISA_MIPS32R2
, CPU_MIPS32R2
},
15153 { "34kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15154 ISA_MIPS32R2
, CPU_MIPS32R2
},
15155 { "34kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15156 ISA_MIPS32R2
, CPU_MIPS32R2
},
15157 { "34kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15158 ISA_MIPS32R2
, CPU_MIPS32R2
},
15159 /* Deprecated forms of the above. */
15160 { "34kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15161 ISA_MIPS32R2
, CPU_MIPS32R2
},
15162 { "34kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_MT
,
15163 ISA_MIPS32R2
, CPU_MIPS32R2
},
15164 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15165 { "74kc", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15166 ISA_MIPS32R2
, CPU_MIPS32R2
},
15167 { "74kf2_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15168 ISA_MIPS32R2
, CPU_MIPS32R2
},
15169 { "74kf", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15170 ISA_MIPS32R2
, CPU_MIPS32R2
},
15171 { "74kf1_1", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15172 ISA_MIPS32R2
, CPU_MIPS32R2
},
15173 { "74kf3_2", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15174 ISA_MIPS32R2
, CPU_MIPS32R2
},
15175 /* Deprecated forms of the above. */
15176 { "74kfx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15177 ISA_MIPS32R2
, CPU_MIPS32R2
},
15178 { "74kx", MIPS_CPU_ASE_DSP
| MIPS_CPU_ASE_DSPR2
,
15179 ISA_MIPS32R2
, CPU_MIPS32R2
},
15182 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
15183 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
15184 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15185 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
15187 /* Broadcom SB-1 CPU core */
15188 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15189 ISA_MIPS64
, CPU_SB1
},
15190 /* Broadcom SB-1A CPU core */
15191 { "sb1a", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
15192 ISA_MIPS64
, CPU_SB1
},
15194 /* MIPS 64 Release 2 */
15196 /* Cavium Networks Octeon CPU core */
15197 { "octeon", 0, ISA_MIPS64R2
, CPU_OCTEON
},
15204 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15205 with a final "000" replaced by "k". Ignore case.
15207 Note: this function is shared between GCC and GAS. */
15210 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15212 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15213 given
++, canonical
++;
15215 return ((*given
== 0 && *canonical
== 0)
15216 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15220 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15221 CPU name. We've traditionally allowed a lot of variation here.
15223 Note: this function is shared between GCC and GAS. */
15226 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15228 /* First see if the name matches exactly, or with a final "000"
15229 turned into "k". */
15230 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15233 /* If not, try comparing based on numerical designation alone.
15234 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15235 if (TOLOWER (*given
) == 'r')
15237 if (!ISDIGIT (*given
))
15240 /* Skip over some well-known prefixes in the canonical name,
15241 hoping to find a number there too. */
15242 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15244 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15246 else if (TOLOWER (canonical
[0]) == 'r')
15249 return mips_strict_matching_cpu_name_p (canonical
, given
);
15253 /* Parse an option that takes the name of a processor as its argument.
15254 OPTION is the name of the option and CPU_STRING is the argument.
15255 Return the corresponding processor enumeration if the CPU_STRING is
15256 recognized, otherwise report an error and return null.
15258 A similar function exists in GCC. */
15260 static const struct mips_cpu_info
*
15261 mips_parse_cpu (const char *option
, const char *cpu_string
)
15263 const struct mips_cpu_info
*p
;
15265 /* 'from-abi' selects the most compatible architecture for the given
15266 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15267 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15268 version. Look first at the -mgp options, if given, otherwise base
15269 the choice on MIPS_DEFAULT_64BIT.
15271 Treat NO_ABI like the EABIs. One reason to do this is that the
15272 plain 'mips' and 'mips64' configs have 'from-abi' as their default
15273 architecture. This code picks MIPS I for 'mips' and MIPS III for
15274 'mips64', just as we did in the days before 'from-abi'. */
15275 if (strcasecmp (cpu_string
, "from-abi") == 0)
15277 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
15278 return mips_cpu_info_from_isa (ISA_MIPS1
);
15280 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
15281 return mips_cpu_info_from_isa (ISA_MIPS3
);
15283 if (file_mips_gp32
>= 0)
15284 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
15286 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
15291 /* 'default' has traditionally been a no-op. Probably not very useful. */
15292 if (strcasecmp (cpu_string
, "default") == 0)
15295 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
15296 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
15299 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
15303 /* Return the canonical processor information for ISA (a member of the
15304 ISA_MIPS* enumeration). */
15306 static const struct mips_cpu_info
*
15307 mips_cpu_info_from_isa (int isa
)
15311 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15312 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
15313 && isa
== mips_cpu_info_table
[i
].isa
)
15314 return (&mips_cpu_info_table
[i
]);
15319 static const struct mips_cpu_info
*
15320 mips_cpu_info_from_arch (int arch
)
15324 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15325 if (arch
== mips_cpu_info_table
[i
].cpu
)
15326 return (&mips_cpu_info_table
[i
]);
15332 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
15336 fprintf (stream
, "%24s", "");
15341 fprintf (stream
, ", ");
15345 if (*col_p
+ strlen (string
) > 72)
15347 fprintf (stream
, "\n%24s", "");
15351 fprintf (stream
, "%s", string
);
15352 *col_p
+= strlen (string
);
15358 md_show_usage (FILE *stream
)
15363 fprintf (stream
, _("\
15365 -EB generate big endian output\n\
15366 -EL generate little endian output\n\
15367 -g, -g2 do not remove unneeded NOPs or swap branches\n\
15368 -G NUM allow referencing objects up to NUM bytes\n\
15369 implicitly with the gp register [default 8]\n"));
15370 fprintf (stream
, _("\
15371 -mips1 generate MIPS ISA I instructions\n\
15372 -mips2 generate MIPS ISA II instructions\n\
15373 -mips3 generate MIPS ISA III instructions\n\
15374 -mips4 generate MIPS ISA IV instructions\n\
15375 -mips5 generate MIPS ISA V instructions\n\
15376 -mips32 generate MIPS32 ISA instructions\n\
15377 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
15378 -mips64 generate MIPS64 ISA instructions\n\
15379 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
15380 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
15384 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
15385 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
15386 show (stream
, "from-abi", &column
, &first
);
15387 fputc ('\n', stream
);
15389 fprintf (stream
, _("\
15390 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
15391 -no-mCPU don't generate code specific to CPU.\n\
15392 For -mCPU and -no-mCPU, CPU must be one of:\n"));
15396 show (stream
, "3900", &column
, &first
);
15397 show (stream
, "4010", &column
, &first
);
15398 show (stream
, "4100", &column
, &first
);
15399 show (stream
, "4650", &column
, &first
);
15400 fputc ('\n', stream
);
15402 fprintf (stream
, _("\
15403 -mips16 generate mips16 instructions\n\
15404 -no-mips16 do not generate mips16 instructions\n"));
15405 fprintf (stream
, _("\
15406 -msmartmips generate smartmips instructions\n\
15407 -mno-smartmips do not generate smartmips instructions\n"));
15408 fprintf (stream
, _("\
15409 -mdsp generate DSP instructions\n\
15410 -mno-dsp do not generate DSP instructions\n"));
15411 fprintf (stream
, _("\
15412 -mdspr2 generate DSP R2 instructions\n\
15413 -mno-dspr2 do not generate DSP R2 instructions\n"));
15414 fprintf (stream
, _("\
15415 -mmt generate MT instructions\n\
15416 -mno-mt do not generate MT instructions\n"));
15417 fprintf (stream
, _("\
15418 -mfix-vr4120 work around certain VR4120 errata\n\
15419 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15420 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15421 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15422 -msym32 assume all symbols have 32-bit values\n\
15423 -O0 remove unneeded NOPs, do not swap branches\n\
15424 -O remove unneeded NOPs and swap branches\n\
15425 --trap, --no-break trap exception on div by 0 and mult overflow\n\
15426 --break, --no-trap break exception on div by 0 and mult overflow\n"));
15427 fprintf (stream
, _("\
15428 -mhard-float allow floating-point instructions\n\
15429 -msoft-float do not allow floating-point instructions\n\
15430 -msingle-float only allow 32-bit floating-point operations\n\
15431 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
15432 --[no-]construct-floats [dis]allow floating point values to be constructed\n"
15435 fprintf (stream
, _("\
15436 -KPIC, -call_shared generate SVR4 position independent code\n\
15437 -call_nonpic generate non-PIC code that can operate with DSOs\n\
15438 -mvxworks-pic generate VxWorks position independent code\n\
15439 -non_shared do not generate code that can operate with DSOs\n\
15440 -xgot assume a 32 bit GOT\n\
15441 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15442 -mshared, -mno-shared disable/enable .cpload optimization for\n\
15443 position dependent (non shared) code\n\
15444 -mabi=ABI create ABI conformant object file for:\n"));
15448 show (stream
, "32", &column
, &first
);
15449 show (stream
, "o64", &column
, &first
);
15450 show (stream
, "n32", &column
, &first
);
15451 show (stream
, "64", &column
, &first
);
15452 show (stream
, "eabi", &column
, &first
);
15454 fputc ('\n', stream
);
15456 fprintf (stream
, _("\
15457 -32 create o32 ABI object file (default)\n\
15458 -n32 create n32 ABI object file\n\
15459 -64 create 64 ABI object file\n"));
15464 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
15466 if (HAVE_64BIT_SYMBOLS
)
15469 return dwarf2_format_64bit_irix
;
15471 return dwarf2_format_64bit
;
15475 return dwarf2_format_32bit
;
15479 mips_dwarf2_addr_size (void)
15481 if (HAVE_64BIT_SYMBOLS
)
15487 /* Standard calling conventions leave the CFA at SP on entry. */
15489 mips_cfi_frame_initial_instructions (void)
15491 cfi_add_CFA_def_cfa_register (SP
);
15495 tc_mips_regname_to_dw2regnum (char *regname
)
15497 unsigned int regnum
= -1;
15500 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))