1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
49 /* MIPS ISA (Instruction Set Architecture) level. */
50 static int mips_isa
= -1;
52 static int mips_warn_about_macros
;
53 static int mips_noreorder
;
54 static int mips_nomove
;
56 static int mips_nobopt
;
59 /* The size of the small data section. */
60 static int g_switch_value
= 8;
66 /* handle of the OPCODE hash table */
67 static struct hash_control
*op_hash
= NULL
;
69 /* This array holds the chars that always start a comment. If the
70 pre-processor is disabled, these aren't very useful */
71 const char comment_chars
[] = "#";
73 /* This array holds the chars that only start a comment at the beginning of
74 a line. If the line seems to have the form '# 123 filename'
75 .line and .file directives will appear in the pre-processed output */
76 /* Note that input_file.c hand checks for '#' at the beginning of the
77 first line of the input file. This is because the compiler outputs
78 #NO_APP at the beginning of its output. */
79 /* Also note that C style comments are always supported. */
80 const char line_comment_chars
[] = "#";
82 /* This array holds machine specific line separator characters. */
83 const char line_separator_chars
[] = "";
85 /* Chars that can be used to separate mant from exp in floating point nums */
86 const char EXP_CHARS
[] = "eE";
88 /* Chars that mean this number is a floating point constant */
91 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
93 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
94 changed in read.c . Ideally it shouldn't have to know about it at all,
95 but nothing is ideal around here.
98 static char *insn_error
;
100 static int byte_order
= BYTE_ORDER
;
102 static int auto_align
= 1;
104 /* Symbol labelling the current insn. */
105 static symbolS
*insn_label
;
107 /* To output NOP instructions correctly, we need to keep information
108 about the previous two instructions. */
110 /* Whether we are optimizing. The default value of 2 means to remove
111 unneeded NOPs and swap branch instructions when possible. A value
112 of 1 means to not swap branches. A value of 0 means to always
114 static int mips_optimize
= 2;
116 /* The previous instruction. */
117 static struct mips_cl_insn prev_insn
;
119 /* The instruction before prev_insn. */
120 static struct mips_cl_insn prev_prev_insn
;
122 /* If we don't want information for prev_insn or prev_prev_insn, we
123 point the insn_mo field at this dummy integer. */
124 static const struct mips_opcode dummy_opcode
= { 0 };
126 /* Non-zero if prev_insn is valid. */
127 static int prev_insn_valid
;
129 /* The frag for the previous instruction. */
130 static struct frag
*prev_insn_frag
;
132 /* The offset into prev_insn_frag for the previous instruction. */
133 static long prev_insn_where
;
135 /* The reloc for the previous instruction, if any. */
136 static fixS
*prev_insn_fixp
;
138 /* Non-zero if the previous instruction was in a delay slot. */
139 static int prev_insn_is_delay_slot
;
141 /* Non-zero if the previous instruction was in a .set noreorder. */
142 static int prev_insn_unreordered
;
144 /* Non-zero if the previous previous instruction was in a .set
146 static int prev_prev_insn_unreordered
;
148 /* Prototypes for static functions. */
151 #define internalError() \
152 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
154 #define internalError() as_fatal ("MIPS internal Error");
157 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
158 unsigned int reg
, int fpr
));
159 static void append_insn
PARAMS ((struct mips_cl_insn
* ip
,
161 bfd_reloc_code_real_type r
));
162 static void mips_no_prev_insn
PARAMS ((void));
163 static void mips_emit_delays
PARAMS ((void));
164 static int gp_reference
PARAMS ((expressionS
* ep
));
165 static void macro_build
PARAMS ((int *counter
, expressionS
* ep
,
166 const char *name
, const char *fmt
,
168 static void macro_build_lui
PARAMS ((int *counter
, expressionS
* ep
,
170 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
171 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
173 static void load_register
PARAMS ((int *counter
,
174 int reg
, expressionS
* ep
));
175 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
176 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
177 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
178 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
179 static symbolS
*get_symbol
PARAMS ((void));
180 static void mips_align
PARAMS ((int to
, int fill
));
181 static void s_align
PARAMS ((int));
182 static void s_stringer
PARAMS ((int));
183 static void s_change_sec
PARAMS ((int));
184 static void s_cons
PARAMS ((int));
185 static void s_err
PARAMS ((int));
186 static void s_extern
PARAMS ((int));
187 static void s_float_cons
PARAMS ((int));
188 static void s_option
PARAMS ((int));
189 static void s_mipsset
PARAMS ((int));
190 static void s_mips_space
PARAMS ((int));
192 static void md_obj_begin
PARAMS ((void));
193 static void md_obj_end
PARAMS ((void));
194 static long get_number
PARAMS ((void));
195 static void s_ent
PARAMS ((int));
196 static void s_mipsend
PARAMS ((int));
197 static void s_file
PARAMS ((int));
198 static void s_frame
PARAMS ((int));
199 static void s_loc
PARAMS ((int));
200 static void s_mask
PARAMS ((char));
205 The following pseudo-ops from the Kane and Heinrich MIPS book
206 should be defined here, but are currently unsupported: .alias,
207 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
209 The following pseudo-ops from the Kane and Heinrich MIPS book are
210 specific to the type of debugging information being generated, and
211 should be defined by the object format: .aent, .begin, .bend,
212 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
215 The following pseudo-ops from the Kane and Heinrich MIPS book are
216 not MIPS CPU specific, but are also not specific to the object file
217 format. This file is probably the best place to define them, but
218 they are not currently supported: .asm0, .endr, .lab, .repeat,
219 .struct, .weakext. */
221 const pseudo_typeS md_pseudo_table
[] =
223 /* MIPS specific pseudo-ops. */
224 {"option", s_option
, 0},
225 {"set", s_mipsset
, 0},
226 {"rdata", s_change_sec
, 'r',},
227 {"sdata", s_change_sec
, 's',},
229 /* Relatively generic pseudo-ops that happen to be used on MIPS
231 {"asciiz", s_stringer
, 1},
232 {"bss", s_change_sec
, 'b'},
236 /* These pseudo-ops are defined in read.c, but must be overridden
237 here for one reason or another. */
238 {"align", s_align
, 0},
239 {"ascii", s_stringer
, 0},
240 {"asciz", s_stringer
, 1},
242 {"data", s_change_sec
, 'd'},
243 {"double", s_float_cons
, 'd'},
244 {"extern", s_extern
, 0},
245 {"float", s_float_cons
, 'f'},
246 {"space", s_mips_space
, 0},
247 {"text", s_change_sec
, 't'},
251 /* These pseudo-ops should be defined by the object file format.
252 However, ECOFF is the only format which currently defines them,
253 so we have versions here for a.out. */
255 {"end", s_mipsend
, 0},
258 {"fmask", s_ignore
, 'F'},
259 {"frame", s_ignore
, 0},
260 {"loc", s_ignore
, 0},
261 {"mask", s_ignore
, 'R'},
262 {"verstamp", s_ignore
, 0},
269 const relax_typeS md_relax_table
[] =
275 static char *expr_end
;
277 static expressionS imm_expr
;
278 static expressionS offset_expr
;
279 static bfd_reloc_code_real_type imm_reloc
;
280 static bfd_reloc_code_real_type offset_reloc
;
283 * This function is called once, at assembler startup time. It should
284 * set up all the tables, etc. that the MD part of the assembler will need.
290 register const char *retval
= NULL
;
291 register unsigned int i
= 0;
295 if (strcmp (TARGET_CPU
, "mips") == 0)
297 else if (strcmp (TARGET_CPU
, "r6000") == 0
298 || strcmp (TARGET_CPU
, "mips2") == 0)
300 else if (strcmp (TARGET_CPU
, "mips64") == 0
301 || strcmp (TARGET_CPU
, "r4000") == 0
302 || strcmp (TARGET_CPU
, "mips3") == 0)
311 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
314 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
317 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
321 as_warn ("Could not set architecture and machine");
323 if ((op_hash
= hash_new ()) == NULL
)
325 as_fatal ("Virtual memory exhausted");
327 for (i
= 0; i
< NUMOPCODES
;)
329 const char *name
= mips_opcodes
[i
].name
;
331 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
332 if (retval
!= NULL
&& *retval
!= '\0')
334 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
335 mips_opcodes
[i
].name
, retval
);
336 as_fatal ("Broken assembler. No assembly attempted.");
340 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
341 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
342 != mips_opcodes
[i
].match
))
344 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
345 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
346 as_fatal ("Broken assembler. No assembly attempted.");
350 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
353 mips_no_prev_insn ();
355 /* set the default alignment for the text section (2**2) */
356 record_alignment (text_section
, 2);
359 bfd_set_gp_size (stdoutput
, g_switch_value
);
379 struct mips_cl_insn insn
;
381 imm_expr
.X_op
= O_absent
;
382 offset_expr
.X_op
= O_absent
;
384 mips_ip (str
, &insn
);
387 as_bad ("%s `%s'", insn_error
, str
);
390 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
396 if (imm_expr
.X_op
!= O_absent
)
397 append_insn (&insn
, &imm_expr
, imm_reloc
);
398 else if (offset_expr
.X_op
!= O_absent
)
399 append_insn (&insn
, &offset_expr
, offset_reloc
);
401 append_insn (&insn
, NULL
, BFD_RELOC_UNUSED
);
405 /* See whether instruction IP reads register REG. If FPR is non-zero,
406 REG is a floating point register. */
409 insn_uses_reg (ip
, reg
, fpr
)
410 struct mips_cl_insn
*ip
;
414 /* Don't report on general register 0, since it never changes. */
415 if (! fpr
&& reg
== 0)
420 /* If we are called with either $f0 or $f1, we must check $f0.
421 This is not optimal, because it will introduce an unnecessary
422 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
423 need to distinguish reading both $f0 and $f1 or just one of
424 them. Note that we don't have to check the other way,
425 because there is no instruction that sets both $f0 and $f1
426 and requires a delay. */
427 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
428 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
429 == (reg
&~ (unsigned) 1)))
431 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
432 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
433 == (reg
&~ (unsigned) 1)))
438 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
439 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
441 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
442 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
449 #define ALIGN_ERR "Attempt to assemble instruction onto non word boundary."
450 #define ALIGN_ERR2 "GAS doesn't do implicit alignment; use .align directive."
454 * Output an instruction.
457 append_insn (ip
, address_expr
, reloc_type
)
458 struct mips_cl_insn
*ip
;
459 expressionS
*address_expr
;
460 bfd_reloc_code_real_type reloc_type
;
466 if (! mips_noreorder
)
468 /* If the previous insn required any delay slots, see if we need
469 to insert a NOP or two. There are eight kinds of possible
470 hazards, of which an instruction can have at most one type.
471 (1) a load from memory delay
472 (2) a load from a coprocessor delay
473 (3) an unconditional branch delay
474 (4) a conditional branch delay
475 (5) a move to coprocessor register delay
476 (6) a load coprocessor register from memory delay
477 (7) a coprocessor condition code delay
478 (8) a HI/LO special register delay
480 There are a lot of optimizations we could do that we don't.
481 In particular, we do not, in general, reorder instructions.
482 If you use gcc with optimization, it will reorder
483 instructions and generally do much more optimization then we
484 do here; repeating all that work in the assembler would only
485 benefit hand written assembly code, and does not seem worth
488 /* This is how a NOP is emitted. */
489 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
491 /* The previous insn might require a delay slot, depending upon
492 the contents of the current insn. */
493 if ((prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
495 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)))
497 /* A load from a coprocessor or from memory. All load
498 delays delay the use of general register rt for one
499 instruction on the r3000. The r6000 and r4000 use
501 know (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
);
502 if (mips_optimize
== 0
503 || insn_uses_reg (ip
,
504 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
509 else if ((prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
511 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)))
513 /* A generic coprocessor delay. The previous instruction
514 modified a coprocessor general or control register. If
515 it modified a control register, we need to avoid any
516 coprocessor instruction (this is probably not always
517 required, but it sometimes is). If it modified a general
518 register, we avoid using that register.
520 On the r6000 and r4000 loading a coprocessor register
521 from memory is interlocked, and does not require a delay.
523 This case is not handled very well. There is no special
524 knowledge of CP0 handling, and the coprocessors other
525 than the floating point unit are not distinguished at
527 if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_T
)
529 if (mips_optimize
== 0
530 || insn_uses_reg (ip
,
531 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
536 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_FPR_S
)
538 if (mips_optimize
== 0
539 || insn_uses_reg (ip
,
540 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
547 /* We don't know exactly what the previous instruction
548 does. If the current instruction uses a coprocessor
549 register, we must insert a NOP. If previous
550 instruction may set the condition codes, and the
551 current instruction uses them, we must insert two
553 if (mips_optimize
== 0
554 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
555 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)))
557 else if (ip
->insn_mo
->pinfo
& INSN_COP
)
561 else if (prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
563 /* The previous instruction sets the coprocessor condition
564 codes, but does not require a general coprocessor delay
565 (this means it is a floating point comparison
566 instruction). If this instruction uses the condition
567 codes, we need to insert a single NOP. */
568 if (mips_optimize
== 0
569 || ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
572 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
574 /* The previous instruction reads the LO register; if the
575 current instruction writes to the LO register, we must
577 if (mips_optimize
== 0
578 || ip
->insn_mo
->pinfo
& INSN_WRITE_LO
)
581 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
583 /* The previous instruction reads the HI register; if the
584 current instruction writes to the HI register, we must
586 if (mips_optimize
== 0
587 || ip
->insn_mo
->pinfo
& INSN_WRITE_HI
)
591 /* There are two cases which require two intervening
592 instructions: 1) setting the condition codes using a move to
593 coprocessor instruction which requires a general coprocessor
594 delay and then reading the condition codes 2) reading the HI
595 or LO register and then writing to it. If we are not already
596 emitting a NOP instruction, we must check for these cases
597 compared to the instruction previous to the previous
600 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
601 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
602 && (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
))
603 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
604 && (ip
->insn_mo
->pinfo
& INSN_WRITE_LO
))
605 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
606 && (ip
->insn_mo
->pinfo
& INSN_WRITE_HI
))))
609 /* Now emit the right number of NOP instructions. */
615 if (insn_label
!= NULL
)
617 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
618 insn_label
->sy_frag
= frag_now
;
619 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
626 /* This is testing the address of the frag, not the alignment of
627 the instruction in the current section. */
635 if (address_expr
!= NULL
)
637 if (address_expr
->X_op
== O_constant
)
642 ip
->insn_opcode
|= address_expr
->X_add_number
;
646 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
649 case BFD_RELOC_MIPS_JMP
:
650 case BFD_RELOC_16_PCREL_S2
:
659 assert (reloc_type
!= BFD_RELOC_UNUSED
);
661 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
663 reloc_type
== BFD_RELOC_16_PCREL_S2
,
668 md_number_to_chars (f
, ip
->insn_opcode
, 4);
670 if (! mips_noreorder
)
672 /* Filling the branch delay slot is more complex. We try to
673 switch the branch with the previous instruction, which we can
674 do if the previous instruction does not set up a condition
675 that the branch tests and if the branch is not itself the
676 target of any branch. */
677 if ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
678 || (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_DELAY
))
680 if (mips_optimize
< 2
681 /* If we have seen .set nobopt, don't optimize. */
683 /* If we have seen .set volatile or .set nomove, don't
686 /* If we had to emit any NOP instructions, then we
687 already know we can not swap. */
689 /* If we don't even know the previous insn, we can not
692 /* If the previous insn is already in a branch delay
693 slot, then we can not swap. */
694 || prev_insn_is_delay_slot
695 /* If the previous previous insn was in a .set
696 noreorder, we can't swap. Actually, the MIPS
697 assembler will swap in this situation. However, gcc
698 configured -with-gnu-as will generate code like
704 in which we can not swap the bne and INSN. If gcc is
705 not configured -with-gnu-as, it does not output the
706 .set pseudo-ops. We don't have to check
707 prev_insn_unreordered, because prev_insn_valid will
708 be 0 in that case. We don't want to use
709 prev_prev_insn_valid, because we do want to be able
710 to swap at the start of a function. */
711 || prev_prev_insn_unreordered
712 /* If the branch is itself the target of a branch, we
713 can not swap. We cheat on this; all we check for is
714 whether there is a label on this instruction. If
715 there are any branches to anything other than a
716 label, users must use .set noreorder. */
717 || insn_label
!= NULL
718 /* If the branch reads the condition codes, we don't
719 even try to swap, because in the sequence
724 we can not swap, and I don't feel like handling that
726 || (ip
->insn_mo
->pinfo
& INSN_READ_COND_CODE
)
727 /* We can not swap with an instruction that requires a
728 delay slot, becase the target of the branch might
729 interfere with that instruction. */
730 || (prev_insn
.insn_mo
->pinfo
731 & (INSN_LOAD_COPROC_DELAY
732 | INSN_COPROC_MOVE_DELAY
733 | INSN_WRITE_COND_CODE
737 && (prev_insn
.insn_mo
->pinfo
738 & (INSN_LOAD_MEMORY_DELAY
739 | INSN_COPROC_MEMORY_DELAY
)))
740 /* We can not swap with a branch instruction. */
741 || (prev_insn
.insn_mo
->pinfo
742 & (INSN_UNCOND_BRANCH_DELAY
743 | INSN_COND_BRANCH_DELAY
744 | INSN_COND_BRANCH_LIKELY
))
745 /* We can not swap with a trap instruction, since it
746 might change the PC. */
747 || (prev_insn
.insn_mo
->pinfo
& INSN_TRAP
)
748 /* If the branch reads a register that the previous
749 instruction sets, we can not swap. */
750 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
751 && insn_uses_reg (ip
,
752 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
755 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
756 && insn_uses_reg (ip
,
757 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
760 /* If the branch writes a register that the previous
761 instruction sets, we can not swap (we know that
762 branches write only to RD or to $31). */
763 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_T
)
764 && (((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
765 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
766 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
767 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
768 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
771 || ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
772 && (((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
773 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
774 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
775 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
776 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
779 /* If the branch writes a register that the previous
780 instruction reads, we can not swap (we know that
781 branches only write to RD or to $31). */
782 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_D
)
783 && insn_uses_reg (&prev_insn
,
784 ((ip
->insn_opcode
>> OP_SH_RD
)
787 || ((ip
->insn_mo
->pinfo
& INSN_WRITE_GPR_31
)
788 && insn_uses_reg (&prev_insn
, 31, 0))
789 /* If the previous previous instruction has a load
790 delay, and sets a register that the branch reads, we
792 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
794 && (prev_prev_insn
.insn_mo
->pinfo
795 & INSN_LOAD_MEMORY_DELAY
)))
796 && insn_uses_reg (ip
,
797 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
801 /* We could do even better for unconditional branches to
802 portions of this object file; we could pick up the
803 instruction at the destination, put it in the delay
804 slot, and bump the destination address. */
806 /* Update the previous insn information. */
807 prev_prev_insn
= *ip
;
808 prev_insn
.insn_mo
= &dummy_opcode
;
815 /* It looks like we can actually do the swap. */
816 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
817 memcpy (temp
, prev_f
, 4);
818 memcpy (prev_f
, f
, 4);
822 prev_insn_fixp
->fx_frag
= frag_now
;
823 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
827 fixp
->fx_frag
= prev_insn_frag
;
828 fixp
->fx_where
= prev_insn_where
;
830 /* Update the previous insn information; leave prev_insn
832 prev_prev_insn
= *ip
;
834 prev_insn_is_delay_slot
= 1;
836 /* If that was an unconditional branch, forget the previous
838 if (ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
)
840 prev_prev_insn
.insn_mo
= &dummy_opcode
;
841 prev_insn
.insn_mo
= &dummy_opcode
;
844 else if (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
)
846 /* We don't yet optimize a branch likely. What we should do
847 is look at the target, copy the instruction found there
848 into the delay slot, and increment the branch to jump to
849 the next instruction. */
851 /* Update the previous insn information. */
852 prev_prev_insn
= *ip
;
853 prev_insn
.insn_mo
= &dummy_opcode
;
857 /* Update the previous insn information. */
859 prev_prev_insn
.insn_mo
= &dummy_opcode
;
861 prev_prev_insn
= prev_insn
;
864 /* Any time we see a branch, we always fill the delay slot
865 immediately; since this insn is not a branch, we know it
866 is not in a delay slot. */
867 prev_insn_is_delay_slot
= 0;
870 prev_prev_insn_unreordered
= prev_insn_unreordered
;
871 prev_insn_unreordered
= 0;
872 prev_insn_frag
= frag_now
;
873 prev_insn_where
= f
- frag_now
->fr_literal
;
874 prev_insn_fixp
= fixp
;
878 /* We just output an insn, so the next one doesn't have a label. */
882 /* This function forgets that there was any previous instruction or
888 prev_insn
.insn_mo
= &dummy_opcode
;
889 prev_prev_insn
.insn_mo
= &dummy_opcode
;
891 prev_insn_is_delay_slot
= 0;
892 prev_insn_unreordered
= 0;
893 prev_prev_insn_unreordered
= 0;
897 /* This function must be called whenever we turn on noreorder or emit
898 something other than instructions. It inserts any NOPS which might
899 be needed by the previous instruction, and clears the information
900 kept for the previous instructions. */
905 if (! mips_noreorder
)
910 if ((prev_insn
.insn_mo
->pinfo
911 & (INSN_LOAD_COPROC_DELAY
912 | INSN_COPROC_MOVE_DELAY
913 | INSN_WRITE_COND_CODE
917 && (prev_insn
.insn_mo
->pinfo
918 & (INSN_LOAD_MEMORY_DELAY
919 | INSN_COPROC_MEMORY_DELAY
))))
922 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
923 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
924 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
927 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
928 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
929 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
934 if (insn_label
!= NULL
)
936 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
937 insn_label
->sy_frag
= frag_now
;
938 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
941 mips_no_prev_insn ();
945 /* Return 1 if an expression can be accessed via the GP register. */
956 sym
= ep
->X_add_symbol
;
957 if (sym
== (symbolS
*) NULL
958 || ep
->X_op_symbol
!= (symbolS
*) NULL
)
961 /* Certain symbols can not be referenced off the GP, although it
962 appears as though they can. */
963 symname
= S_GET_NAME (sym
);
964 if (symname
!= (const char *) NULL
965 && (strcmp (symname
, "eprol") == 0
966 || strcmp (symname
, "etext") == 0
967 || strcmp (symname
, "_gp") == 0
968 || strcmp (symname
, "edata") == 0
969 || strcmp (symname
, "_fbss") == 0
970 || strcmp (symname
, "_fdata") == 0
971 || strcmp (symname
, "_ftext") == 0
972 || strcmp (symname
, "end") == 0))
974 if (! S_IS_DEFINED (sym
)
975 && S_GET_VALUE (sym
) != 0
976 && S_GET_VALUE (sym
) <= g_switch_value
)
978 segname
= segment_name (S_GET_SEGMENT (ep
->X_add_symbol
));
979 return (strcmp (segname
, ".sdata") == 0
980 || strcmp (segname
, ".sbss") == 0
981 || strcmp (segname
, ".lit8") == 0
982 || strcmp (segname
, ".lit4") == 0);
983 #else /* ! defined (OBJ_ECOFF) */
984 /* The GP register is only used for ECOFF. */
986 #endif /* ! defined (OBJ_ECOFF) */
989 /* Build an instruction created by a macro expansion. This is passed
990 a pointer to the count of instructions created so far, an
991 expression, the name of the instruction to build, an operand format
992 string, and corresponding arguments. */
996 macro_build (int *counter
,
1001 #else /* ! defined (NO_STDARG) */
1003 macro_build (counter
, ep
, name
, fmt
, va_alist
)
1009 #endif /* ! defined (NO_STDARG) */
1011 struct mips_cl_insn insn
;
1012 bfd_reloc_code_real_type r
;
1016 va_start (args
, fmt
);
1022 * If the macro is about to expand into a second instruction,
1023 * print a warning if needed. We need to pass ip as a parameter
1024 * to generate a better warning message here...
1026 if (mips_warn_about_macros
&& *counter
== 1)
1027 as_warn ("Macro instruction expanded into multiple instructions");
1029 *counter
+= 1; /* bump instruction counter */
1031 r
= BFD_RELOC_UNUSED
;
1032 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1033 assert (insn
.insn_mo
);
1034 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1036 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0)
1039 assert (insn
.insn_mo
->name
);
1040 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1042 assert (insn
.insn_mo
->pinfo
!= INSN_MACRO
);
1043 insn
.insn_opcode
= insn
.insn_mo
->match
;
1059 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1065 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1070 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1075 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1082 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1086 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1090 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1097 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1107 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1108 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1113 assert (ep
!= NULL
);
1115 * This allows macro() to pass an immediate expression for
1116 * creating short branches without creating a symbol.
1117 * Note that the expression still might come from the assembly
1118 * input, in which case the value is not checked for range nor
1119 * is a relocation entry generated (yuck).
1121 if (ep
->X_op
== O_constant
)
1123 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1127 r
= BFD_RELOC_16_PCREL_S2
;
1136 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1138 /* Use GP relative addressing if possible. */
1139 if (r
== BFD_RELOC_LO16
1140 && gp_reference (ep
))
1141 r
= BFD_RELOC_MIPS_GPREL
;
1143 append_insn (&insn
, ep
, r
);
1147 * Generate a "lui" instruction.
1150 macro_build_lui (counter
, ep
, regnum
)
1155 expressionS high_expr
;
1156 struct mips_cl_insn insn
;
1157 bfd_reloc_code_real_type r
;
1158 CONST
char *name
= "lui";
1159 CONST
char *fmt
= "t,u";
1163 if (high_expr
.X_op
== O_constant
)
1165 /* we can compute the instruction now without a relocation entry */
1166 if (high_expr
.X_add_number
& 0x8000)
1167 high_expr
.X_add_number
+= 0x10000;
1168 high_expr
.X_add_number
=
1169 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1170 r
= BFD_RELOC_UNUSED
;
1173 r
= BFD_RELOC_HI16_S
;
1176 * If the macro is about to expand into a second instruction,
1177 * print a warning if needed. We need to pass ip as a parameter
1178 * to generate a better warning message here...
1180 if (mips_warn_about_macros
&& *counter
== 1)
1181 as_warn ("Macro instruction expanded into multiple instructions");
1183 *counter
+= 1; /* bump instruction counter */
1185 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1186 assert (insn
.insn_mo
);
1187 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1188 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1190 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< 16);
1191 if (r
== BFD_RELOC_UNUSED
)
1193 insn
.insn_opcode
|= high_expr
.X_add_number
;
1194 append_insn (&insn
, NULL
, r
);
1197 append_insn (&insn
, &high_expr
, r
);
1201 * Generates code to set the $at register to true (one)
1202 * if reg is less than the immediate expression.
1205 set_at (counter
, reg
, unsignedp
)
1210 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1211 macro_build (counter
, &imm_expr
,
1212 unsignedp
? "sltiu" : "slti",
1216 load_register (counter
, AT
, &imm_expr
);
1217 macro_build (counter
, NULL
,
1218 unsignedp
? "sltu" : "slt",
1219 "d,v,t", AT
, reg
, AT
);
1223 /* Warn if an expression is not a constant. */
1226 check_absolute_expr (ip
, ex
)
1227 struct mips_cl_insn
*ip
;
1230 if (ex
->X_op
!= O_constant
)
1231 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1235 * This routine generates the least number of instructions neccessary to load
1236 * an absolute expression value into a register.
1239 load_register (counter
, reg
, ep
)
1244 assert (ep
->X_op
== O_constant
);
1245 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1246 macro_build (counter
, ep
,
1247 mips_isa
< 3 ? "addiu" : "daddiu",
1249 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1250 macro_build (counter
, ep
, "ori", "t,r,i", reg
, 0);
1251 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1252 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1253 == ~ (offsetT
) 0x7fffffff))
1255 macro_build (counter
, ep
, "lui", "t,u", reg
);
1256 if ((ep
->X_add_number
& 0xffff) != 0)
1257 macro_build (counter
, ep
, "ori", "t,r,i", reg
, reg
);
1259 else if (mips_isa
< 3)
1261 as_bad ("Number larger than 32 bits");
1262 macro_build (counter
, ep
, "addiu", "t,r,j", reg
, 0);
1267 expressionS hi32
, lo32
;
1271 hi32
.X_add_number
>>= shift
;
1272 hi32
.X_add_number
&= 0xffffffff;
1273 if ((hi32
.X_add_number
& 0x80000000) != 0)
1274 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1275 load_register (counter
, reg
, &hi32
);
1277 lo32
.X_add_number
&= 0xffffffff;
1278 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1279 macro_build (counter
, NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
1284 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1286 mid16
.X_add_number
>>= 16;
1287 macro_build (counter
, &mid16
, "ori", "t,r,i", reg
, reg
);
1288 macro_build (counter
, NULL
, "dsll", "d,w,<", reg
, reg
, 16);
1290 if ((lo32
.X_add_number
& 0xffff) != 0)
1291 macro_build (counter
, &lo32
, "ori", "t,r,i", reg
, reg
);
1297 * This routine implements the seemingly endless macro or synthesized
1298 * instructions and addressing modes in the mips assembly language. Many
1299 * of these macros are simple and are similar to each other. These could
1300 * probably be handled by some kind of table or grammer aproach instead of
1301 * this verbose method. Others are not simple macros but are more like
1302 * optimizing code generation.
1303 * One interesting optimization is when several store macros appear
1304 * consecutivly that would load AT with the upper half of the same address.
1305 * The ensuing load upper instructions are ommited. This implies some kind
1306 * of global optimization. We currently only optimize within a single macro.
1307 * For many of the load and store macros if the address is specified as a
1308 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1309 * first load register 'at' with zero and use it as the base register. The
1310 * mips assembler simply uses register $zero. Just one tiny optimization
1315 struct mips_cl_insn
*ip
;
1317 register int treg
, sreg
, dreg
, breg
;
1331 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1332 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1333 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1334 mask
= ip
->insn_mo
->mask
;
1336 expr1
.X_op
= O_constant
;
1337 expr1
.X_op_symbol
= NULL
;
1338 expr1
.X_add_symbol
= NULL
;
1339 expr1
.X_add_number
= 1;
1351 mips_emit_delays ();
1354 expr1
.X_add_number
= 8;
1355 macro_build (&icnt
, &expr1
, "bgez", "s,p", sreg
);
1357 macro_build (&icnt
, NULL
, "nop", "", 0);
1359 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1360 macro_build (&icnt
, NULL
,
1361 dbl
? "dsub" : "sub",
1362 "d,v,t", dreg
, 0, sreg
);
1385 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1387 macro_build (&icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
);
1390 load_register (&icnt
, AT
, &imm_expr
);
1391 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1410 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1412 if (mask
!= M_NOR_I
)
1413 macro_build (&icnt
, &imm_expr
, s
, "t,r,i", treg
, sreg
);
1416 macro_build (&icnt
, &imm_expr
, "ori", "t,r,i", treg
, sreg
);
1417 macro_build (&icnt
, &imm_expr
, "nor", "d,v,t", treg
, treg
, 0);
1422 load_register (&icnt
, AT
, &imm_expr
);
1423 macro_build (&icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1440 if (imm_expr
.X_add_number
== 0)
1442 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, 0);
1445 load_register (&icnt
, AT
, &imm_expr
);
1446 macro_build (&icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1454 macro_build (&icnt
, &offset_expr
,
1455 likely
? "bgezl" : "bgez",
1461 macro_build (&icnt
, &offset_expr
,
1462 likely
? "blezl" : "blez",
1466 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1467 macro_build (&icnt
, &offset_expr
,
1468 likely
? "beql" : "beq",
1475 /* check for > max integer */
1476 maxnum
= 0x7fffffff;
1484 if (imm_expr
.X_add_number
>= maxnum
)
1487 /* result is always false */
1490 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1491 macro_build (&icnt
, NULL
, "nop", "", 0);
1495 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1496 macro_build (&icnt
, &offset_expr
, "bnel", "s,t,p", 0, 0);
1500 imm_expr
.X_add_number
++;
1504 if (mask
== M_BGEL_I
)
1506 if (imm_expr
.X_add_number
== 0)
1508 macro_build (&icnt
, &offset_expr
,
1509 likely
? "bgezl" : "bgez",
1513 if (imm_expr
.X_add_number
== 1)
1515 macro_build (&icnt
, &offset_expr
,
1516 likely
? "bgtzl" : "bgtz",
1520 maxnum
= 0x7fffffff;
1528 maxnum
= - maxnum
- 1;
1529 if (imm_expr
.X_add_number
<= maxnum
)
1532 /* result is always true */
1533 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1534 macro_build (&icnt
, &offset_expr
, "b", "p");
1537 set_at (&icnt
, sreg
, 0);
1538 macro_build (&icnt
, &offset_expr
,
1539 likely
? "beql" : "beq",
1550 macro_build (&icnt
, &offset_expr
,
1551 likely
? "beql" : "beq",
1555 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1556 macro_build (&icnt
, &offset_expr
,
1557 likely
? "beql" : "beq",
1564 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1566 imm_expr
.X_add_number
++;
1570 if (mask
== M_BGEUL_I
)
1572 if (imm_expr
.X_add_number
== 0)
1574 if (imm_expr
.X_add_number
== 1)
1576 macro_build (&icnt
, &offset_expr
,
1577 likely
? "bnel" : "bne",
1581 set_at (&icnt
, sreg
, 1);
1582 macro_build (&icnt
, &offset_expr
,
1583 likely
? "beql" : "beq",
1592 macro_build (&icnt
, &offset_expr
,
1593 likely
? "bgtzl" : "bgtz",
1599 macro_build (&icnt
, &offset_expr
,
1600 likely
? "bltzl" : "bltz",
1604 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1605 macro_build (&icnt
, &offset_expr
,
1606 likely
? "bnel" : "bne",
1615 macro_build (&icnt
, &offset_expr
,
1616 likely
? "bnel" : "bne",
1622 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1623 macro_build (&icnt
, &offset_expr
,
1624 likely
? "bnel" : "bne",
1633 macro_build (&icnt
, &offset_expr
,
1634 likely
? "blezl" : "blez",
1640 macro_build (&icnt
, &offset_expr
,
1641 likely
? "bgezl" : "bgez",
1645 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1646 macro_build (&icnt
, &offset_expr
,
1647 likely
? "beql" : "beq",
1654 maxnum
= 0x7fffffff;
1662 if (imm_expr
.X_add_number
>= maxnum
)
1664 imm_expr
.X_add_number
++;
1668 if (mask
== M_BLTL_I
)
1670 if (imm_expr
.X_add_number
== 0)
1672 macro_build (&icnt
, &offset_expr
,
1673 likely
? "bltzl" : "bltz",
1677 if (imm_expr
.X_add_number
== 1)
1679 macro_build (&icnt
, &offset_expr
,
1680 likely
? "blezl" : "blez",
1684 set_at (&icnt
, sreg
, 0);
1685 macro_build (&icnt
, &offset_expr
,
1686 likely
? "bnel" : "bne",
1695 macro_build (&icnt
, &offset_expr
,
1696 likely
? "beql" : "beq",
1702 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
1703 macro_build (&icnt
, &offset_expr
,
1704 likely
? "beql" : "beq",
1711 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1713 imm_expr
.X_add_number
++;
1717 if (mask
== M_BLTUL_I
)
1719 if (imm_expr
.X_add_number
== 0)
1721 if (imm_expr
.X_add_number
== 1)
1723 macro_build (&icnt
, &offset_expr
,
1724 likely
? "beql" : "beq",
1728 set_at (&icnt
, sreg
, 1);
1729 macro_build (&icnt
, &offset_expr
,
1730 likely
? "bnel" : "bne",
1739 macro_build (&icnt
, &offset_expr
,
1740 likely
? "bltzl" : "bltz",
1746 macro_build (&icnt
, &offset_expr
,
1747 likely
? "bgtzl" : "bgtz",
1751 macro_build (&icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1752 macro_build (&icnt
, &offset_expr
,
1753 likely
? "bnel" : "bne",
1764 macro_build (&icnt
, &offset_expr
,
1765 likely
? "bnel" : "bne",
1769 macro_build (&icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
1770 macro_build (&icnt
, &offset_expr
,
1771 likely
? "bnel" : "bne",
1787 as_warn ("Divide by zero.");
1788 macro_build (&icnt
, NULL
, "break", "c", 7);
1792 mips_emit_delays ();
1794 macro_build (&icnt
, NULL
,
1795 dbl
? "ddiv" : "div",
1796 "z,s,t", sreg
, treg
);
1797 expr1
.X_add_number
= 8;
1798 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1799 macro_build (&icnt
, NULL
, "nop", "", 0);
1800 macro_build (&icnt
, NULL
, "break", "c", 7);
1801 expr1
.X_add_number
= -1;
1802 macro_build (&icnt
, &expr1
,
1803 dbl
? "daddiu" : "addiu",
1805 expr1
.X_add_number
= dbl
? 20 : 16;
1806 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
1809 expr1
.X_add_number
= 1;
1810 macro_build (&icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0);
1811 macro_build (&icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
1815 expr1
.X_add_number
= 0x80000000;
1816 macro_build (&icnt
, &expr1
, "lui", "t,u", AT
);
1818 expr1
.X_add_number
= 8;
1819 macro_build (&icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
1820 macro_build (&icnt
, NULL
, "nop", "", 0);
1821 macro_build (&icnt
, NULL
, "break", "c", 6);
1823 macro_build (&icnt
, NULL
, s
, "d", dreg
);
1862 if (imm_expr
.X_add_number
== 0)
1864 as_warn ("Divide by zero.");
1865 macro_build (&icnt
, NULL
, "break", "c", 7);
1868 if (imm_expr
.X_add_number
== 1)
1870 if (strcmp (s2
, "mflo") == 0)
1871 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, sreg
);
1873 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1876 if (imm_expr
.X_add_number
== -1
1877 && s
[strlen (s
) - 1] != 'u')
1879 if (strcmp (s2
, "mflo") == 0)
1882 macro_build (&icnt
, NULL
, "dneg", "d,w", dreg
, sreg
);
1884 macro_build (&icnt
, NULL
, "neg", "d,w", dreg
, sreg
);
1887 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
1891 load_register (&icnt
, AT
, &imm_expr
);
1892 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
1893 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1912 mips_emit_delays ();
1914 macro_build (&icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
1915 expr1
.X_add_number
= 8;
1916 macro_build (&icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
1917 macro_build (&icnt
, NULL
, "nop", "", 0);
1918 macro_build (&icnt
, NULL
, "break", "c", 7);
1920 macro_build (&icnt
, NULL
, s2
, "d", dreg
);
1924 if (offset_expr
.X_op
== O_constant
)
1926 load_register (&icnt
, treg
, &offset_expr
);
1929 if (gp_reference (&offset_expr
))
1930 macro_build (&icnt
, &offset_expr
,
1931 mips_isa
< 3 ? "addiu" : "daddiu",
1935 /* FIXME: This won't work for a 64 bit address. */
1936 macro_build_lui (&icnt
, &offset_expr
, treg
);
1937 macro_build (&icnt
, &offset_expr
,
1938 mips_isa
< 3 ? "addiu" : "daddiu",
1939 "t,r,j", treg
, treg
);
1944 tempreg
= (breg
== treg
) ? AT
: treg
;
1945 if (offset_expr
.X_op
== O_constant
)
1946 load_register (&icnt
, tempreg
, &offset_expr
);
1947 else if (gp_reference (&offset_expr
))
1948 macro_build (&icnt
, &offset_expr
,
1949 mips_isa
< 3 ? "addiu" : "daddiu",
1950 "t,r,j", tempreg
, GP
);
1953 /* FIXME: This won't work for a 64 bit address. */
1954 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
1955 macro_build (&icnt
, &offset_expr
,
1956 mips_isa
< 3 ? "addiu" : "daddiu",
1957 "t,r,j", tempreg
, tempreg
);
1960 macro_build (&icnt
, NULL
, "addu", "d,v,t", treg
, tempreg
, breg
);
2030 if (breg
== treg
|| coproc
)
2099 if (mask
== M_LWC1_AB
2100 || mask
== M_SWC1_AB
2102 || mask
== M_LDC1_AB
2103 || mask
== M_SDC1_AB
)
2109 if (gp_reference (&offset_expr
))
2113 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, GP
);
2116 macro_build (&icnt
, (expressionS
*) NULL
,
2117 mips_isa
< 3 ? "addu" : "daddu",
2118 "d,v,t", tempreg
, breg
, GP
);
2122 /* FIXME: This won't work for a 64 bit address. */
2123 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2125 macro_build (&icnt
, NULL
,
2126 mips_isa
< 3 ? "addu" : "daddu",
2127 "d,v,t", tempreg
, tempreg
, breg
);
2129 macro_build (&icnt
, &offset_expr
, s
, fmt
, treg
, tempreg
);
2136 load_register (&icnt
, treg
, &imm_expr
);
2141 lw $v0,%lo(foo)($at)
2142 lw $v1,%lo(foo+4)($at)
2147 /* FIXME: This won't work for a 64 bit address. */
2148 macro_build_lui (&icnt
, &offset_expr
, AT
);
2150 macro_build (&icnt
, &offset_expr
, "ld", "t,o(b)", treg
, AT
);
2153 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
, AT
);
2154 offset_expr
.X_add_number
+= 4;
2155 macro_build (&icnt
, &offset_expr
, "lw", "t,o(b)", treg
+ 1, AT
);
2160 /* Load a floating point number from the .lit8 section. */
2163 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, GP
);
2169 /* Even on a big endian machine $fn comes before $fn+1. We have
2170 to adjust when loading from memory. */
2171 assert (mips_isa
< 2);
2172 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2173 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2175 offset_expr
.X_add_number
+= 4;
2176 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2177 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2183 * The MIPS assembler seems to check for X_add_number not
2184 * being double aligned and generating:
2187 * addiu at,at,%lo(foo+1)
2190 * But, the resulting address is the same after relocation so why
2191 * generate the extra instruction?
2193 if (gp_reference (&offset_expr
))
2199 macro_build (&icnt
, &offset_expr
,
2200 mips_isa
< 3 ? "addu" : "daddu",
2201 "d,v,t", AT
, breg
, GP
);
2207 /* FIXME: This won't work for a 64 bit address. */
2208 macro_build_lui (&icnt
, &offset_expr
, AT
);
2210 macro_build (&icnt
, NULL
,
2211 mips_isa
< 3 ? "addu" : "daddu",
2212 "d,v,t", AT
, AT
, breg
);
2216 macro_build (&icnt
, &offset_expr
, "ldc1", "T,o(b)", treg
, tempreg
);
2219 /* Even on a big endian machine $fn comes before $fn+1. We
2220 have to adjust when loading from memory. */
2221 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2222 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2224 offset_expr
.X_add_number
+= 4;
2225 macro_build (&icnt
, &offset_expr
, "lwc1", "T,o(b)",
2226 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2239 assert (mips_isa
< 3);
2240 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2241 offset_expr
.X_add_number
+= 4;
2242 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, breg
);
2265 if (gp_reference (&offset_expr
))
2273 macro_build (&icnt
, (expressionS
*) NULL
,
2274 mips_isa
< 3 ? "addu" : "daddu",
2275 "d,v,t", tempreg
, breg
, GP
);
2279 /* FIXME: This won't work for a 64 bit address. */
2280 macro_build_lui (&icnt
, &offset_expr
, tempreg
);
2282 macro_build (&icnt
, NULL
,
2283 mips_isa
< 3 ? "addu" : "daddu",
2284 "d,v,t", tempreg
, tempreg
, breg
);
2287 macro_build (&icnt
, &offset_expr
, s2
, "t,o(b)", treg
, tempreg
);
2290 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, tempreg
);
2291 offset_expr
.X_add_number
+= 4;
2292 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1, tempreg
);
2301 macro_build (&icnt
, NULL
,
2302 dbl
? "dmultu" : "multu",
2304 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2310 /* The MIPS assembler some times generates shifts and adds. I'm
2311 not trying to be that fancy. GCC should do this for us
2313 load_register (&icnt
, AT
, &imm_expr
);
2314 macro_build (&icnt
, NULL
,
2315 dbl
? "dmult" : "mult",
2317 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2323 mips_emit_delays ();
2325 macro_build (&icnt
, NULL
,
2326 dbl
? "dmult" : "mult",
2328 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2329 macro_build (&icnt
, NULL
,
2330 dbl
? "dsra32" : "sra",
2331 "d,w,<", dreg
, dreg
, 31);
2332 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2333 expr1
.X_add_number
= 8;
2334 macro_build (&icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
2335 macro_build (&icnt
, NULL
, "nop", "", 0);
2336 macro_build (&icnt
, NULL
, "break", "c", 6);
2338 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2344 mips_emit_delays ();
2346 macro_build (&icnt
, NULL
,
2347 dbl
? "dmultu" : "multu",
2349 macro_build (&icnt
, NULL
, "mfhi", "d", AT
);
2350 macro_build (&icnt
, NULL
, "mflo", "d", dreg
);
2351 expr1
.X_add_number
= 8;
2352 macro_build (&icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
2353 macro_build (&icnt
, NULL
, "nop", "", 0);
2354 macro_build (&icnt
, NULL
, "break", "c", 6);
2359 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2360 macro_build (&icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
2361 macro_build (&icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
2362 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2366 macro_build (&icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
2367 imm_expr
.X_add_number
& 0x1f);
2368 macro_build (&icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
2369 (0 - imm_expr
.X_add_number
) & 0x1f);
2370 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2374 macro_build (&icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
2375 macro_build (&icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
2376 macro_build (&icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
2377 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2381 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
2382 imm_expr
.X_add_number
& 0x1f);
2383 macro_build (&icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
2384 (0 - imm_expr
.X_add_number
) & 0x1f);
2385 macro_build (&icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
2389 assert (mips_isa
< 2);
2390 /* Even on a big endian machine $fn comes before $fn+1. We have
2391 to adjust when storing to memory. */
2392 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2393 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2395 offset_expr
.X_add_number
+= 4;
2396 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2397 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2402 if (gp_reference (&offset_expr
))
2408 macro_build (&icnt
, (expressionS
*) NULL
,
2409 mips_isa
< 3 ? "addu" : "daddu",
2410 "d,v,t", AT
, breg
, GP
);
2416 /* FIXME: This won't work for a 64 bit address. */
2417 macro_build_lui (&icnt
, &offset_expr
, AT
);
2419 macro_build (&icnt
, NULL
,
2420 mips_isa
< 3 ? "addu" : "daddu",
2421 "d,v,t", AT
, AT
, breg
);
2425 macro_build (&icnt
, &offset_expr
, "sdc1", "T,o(b)", treg
, tempreg
);
2428 /* Even on a big endian machine $fn comes before $fn+1. We
2429 have to adjust when storing to memory. */
2430 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2431 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2433 offset_expr
.X_add_number
+= 4;
2434 macro_build (&icnt
, &offset_expr
, "swc1", "T,o(b)",
2435 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2444 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, treg
);
2446 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2449 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2450 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2455 if (imm_expr
.X_add_number
== 0)
2457 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, sreg
);
2462 as_warn ("Instruction %s: result is always false",
2464 macro_build (&icnt
, NULL
, "move", "d,s", dreg
, 0);
2467 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2469 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2472 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2474 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2475 macro_build (&icnt
, &imm_expr
,
2476 mips_isa
< 3 ? "addiu" : "daddiu",
2477 "t,r,j", dreg
, sreg
);
2482 load_register (&icnt
, AT
, &imm_expr
);
2483 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2486 macro_build (&icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
);
2491 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
2497 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
2498 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2501 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
2503 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2505 macro_build (&icnt
, &expr1
,
2506 mask
== M_SGE_I
? "slti" : "sltiu",
2507 "t,r,j", dreg
, sreg
);
2512 load_register (&icnt
, AT
, &imm_expr
);
2513 macro_build (&icnt
, NULL
,
2514 mask
== M_SGE_I
? "slt" : "sltu",
2515 "d,v,t", dreg
, sreg
, AT
);
2518 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2523 case M_SGT
: /* sreg > treg <==> treg < sreg */
2529 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2532 case M_SGT_I
: /* sreg > I <==> I < sreg */
2538 load_register (&icnt
, AT
, &imm_expr
);
2539 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2542 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
2548 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
2549 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2552 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
2558 load_register (&icnt
, AT
, &imm_expr
);
2559 macro_build (&icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
2560 macro_build (&icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
);
2564 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2566 macro_build (&icnt
, &imm_expr
, "slti", "t,r,j", dreg
, sreg
);
2569 load_register (&icnt
, AT
, &imm_expr
);
2570 macro_build (&icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
2574 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2576 macro_build (&icnt
, &imm_expr
, "sltiu", "t,r,j", dreg
, sreg
);
2579 load_register (&icnt
, AT
, &imm_expr
);
2580 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
2585 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
2587 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2590 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
2591 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2596 if (imm_expr
.X_add_number
== 0)
2598 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
2603 as_warn ("Instruction %s: result is always true",
2605 macro_build (&icnt
, &expr1
,
2606 mips_isa
< 3 ? "addiu" : "daddiu",
2610 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2612 macro_build (&icnt
, &imm_expr
, "xori", "t,r,i", dreg
, sreg
);
2615 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
2617 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2618 macro_build (&icnt
, &imm_expr
,
2619 mips_isa
< 3 ? "addiu" : "daddiu",
2620 "t,r,j", dreg
, sreg
);
2625 load_register (&icnt
, AT
, &imm_expr
);
2626 macro_build (&icnt
, NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
2629 macro_build (&icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
2637 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2639 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2640 macro_build (&icnt
, &imm_expr
,
2641 dbl
? "daddi" : "addi",
2642 "t,r,j", dreg
, sreg
);
2645 load_register (&icnt
, AT
, &imm_expr
);
2646 macro_build (&icnt
, NULL
,
2647 dbl
? "dsub" : "sub",
2648 "d,v,t", dreg
, sreg
, AT
);
2654 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
2656 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
2657 macro_build (&icnt
, &imm_expr
,
2658 dbl
? "daddiu" : "addiu",
2659 "t,r,j", dreg
, sreg
);
2662 load_register (&icnt
, AT
, &imm_expr
);
2663 macro_build (&icnt
, NULL
,
2664 dbl
? "dsubu" : "subu",
2665 "d,v,t", dreg
, sreg
, AT
);
2686 load_register (&icnt
, AT
, &imm_expr
);
2687 macro_build (&icnt
, NULL
, s
, "s,t", sreg
, AT
);
2692 assert (mips_isa
< 2);
2693 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
2694 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
2697 * Is the double cfc1 instruction a bug in the mips assembler;
2698 * or is there a reason for it?
2700 mips_emit_delays ();
2702 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2703 macro_build (&icnt
, NULL
, "cfc1", "t,G", treg
, 31);
2704 macro_build (&icnt
, NULL
, "nop", "");
2705 expr1
.X_add_number
= 3;
2706 macro_build (&icnt
, &expr1
, "ori", "t,r,i", AT
, treg
);
2707 expr1
.X_add_number
= 2;
2708 macro_build (&icnt
, &expr1
, "xori", "t,r,i", AT
, AT
);
2709 macro_build (&icnt
, NULL
, "ctc1", "t,G", AT
, 31);
2710 macro_build (&icnt
, NULL
, "nop", "");
2711 macro_build (&icnt
, NULL
,
2712 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
2713 macro_build (&icnt
, NULL
, "ctc1", "t,G", treg
, 31);
2714 macro_build (&icnt
, NULL
, "nop", "");
2724 /* avoid load delay */
2725 offset_expr
.X_add_number
+= 1;
2726 macro_build (&icnt
, &offset_expr
, s
, "t,o(b)", treg
, breg
);
2727 offset_expr
.X_add_number
-= 1;
2728 macro_build (&icnt
, &offset_expr
, "lbu", "t,o(b)", AT
, breg
);
2729 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2730 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2734 /* does this work on a big endian machine? */
2735 offset_expr
.X_add_number
+= 3;
2736 macro_build (&icnt
, &offset_expr
, "lwl", "t,o(b)", treg
, breg
);
2737 offset_expr
.X_add_number
-= 3;
2738 macro_build (&icnt
, &offset_expr
, "lwr", "t,o(b)", treg
, breg
);
2744 if (offset_expr
.X_op
== O_constant
)
2745 load_register (&icnt
, AT
, &offset_expr
);
2746 else if (gp_reference (&offset_expr
))
2747 macro_build (&icnt
, &offset_expr
,
2748 mips_isa
< 3 ? "addiu" : "daddiu",
2752 /* FIXME: This won't work for a 64 bit address. */
2753 macro_build_lui (&icnt
, &offset_expr
, AT
);
2754 macro_build (&icnt
, &offset_expr
,
2755 mips_isa
< 3 ? "addiu" : "daddiu",
2758 if (mask
== M_ULW_A
)
2760 expr1
.X_add_number
= 3;
2761 macro_build (&icnt
, &expr1
, "lwl", "t,o(b)", treg
, AT
);
2762 imm_expr
.X_add_number
= 0;
2763 macro_build (&icnt
, &expr1
, "lwr", "t,o(b)", treg
, AT
);
2767 macro_build (&icnt
, &expr1
,
2768 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
, AT
);
2769 imm_expr
.X_add_number
= 0;
2770 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2771 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2772 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2777 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", treg
, breg
);
2778 macro_build (&icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
2779 offset_expr
.X_add_number
+= 1;
2780 macro_build (&icnt
, &offset_expr
, "sb", "t,o(b)", AT
, breg
);
2784 offset_expr
.X_add_number
+= 3;
2785 macro_build (&icnt
, &offset_expr
, "swl", "t,o(b)", treg
, breg
);
2786 offset_expr
.X_add_number
-= 3;
2787 macro_build (&icnt
, &offset_expr
, "swr", "t,o(b)", treg
, breg
);
2792 if (offset_expr
.X_op
== O_constant
)
2793 load_register (&icnt
, AT
, &offset_expr
);
2794 else if (gp_reference (&offset_expr
))
2795 macro_build (&icnt
, &offset_expr
,
2796 mips_isa
< 3 ? "addiu" : "daddiu",
2800 /* FIXME: This won't work for a 64 bit address. */
2801 macro_build_lui (&icnt
, &offset_expr
, AT
);
2802 macro_build (&icnt
, &offset_expr
,
2803 mips_isa
< 3 ? "addiu" : "daddiu",
2806 if (mask
== M_USW_A
)
2808 expr1
.X_add_number
= 3;
2809 macro_build (&icnt
, &expr1
, "swl", "t,o(b)", treg
, AT
);
2810 expr1
.X_add_number
= 0;
2811 macro_build (&icnt
, &expr1
, "swr", "t,o(b)", treg
, AT
);
2815 expr1
.X_add_number
= 0;
2816 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2817 macro_build (&icnt
, NULL
, "srl", "d,w,<", treg
, treg
, 8);
2818 expr1
.X_add_number
= 1;
2819 macro_build (&icnt
, &expr1
, "sb", "t,o(b)", treg
, AT
);
2820 expr1
.X_add_number
= 0;
2821 macro_build (&icnt
, &expr1
, "lbu", "t,o(b)", AT
, AT
);
2822 macro_build (&icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
2823 macro_build (&icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
2828 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
2832 as_warn ("Macro used $at after \".set noat\"");
2837 This routine assembles an instruction into its binary format. As a side
2838 effect it sets one of the global variables imm_reloc or offset_reloc to the
2839 type of relocation to do if one of the operands is an address expression.
2844 struct mips_cl_insn
*ip
;
2849 struct mips_opcode
*insn
;
2852 unsigned int lastregno
= 0;
2857 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
2869 as_warn ("Unknown opcode: `%s'", str
);
2872 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
2874 as_warn ("`%s' not in hash table.", str
);
2875 insn_error
= "ERROR: Unrecognized opcode";
2883 assert (strcmp (insn
->name
, str
) == 0);
2885 if (insn
->pinfo
== INSN_MACRO
)
2886 insn_isa
= insn
->match
;
2887 else if (insn
->pinfo
& INSN_ISA2
)
2889 else if (insn
->pinfo
& INSN_ISA3
)
2894 if (insn_isa
> mips_isa
)
2896 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
2897 && strcmp (insn
->name
, insn
[1].name
) == 0)
2902 insn_error
= "ERROR: instruction not supported on this processor";
2907 ip
->insn_opcode
= insn
->match
;
2908 for (args
= insn
->args
;; ++args
)
2914 case '\0': /* end of args */
2927 ip
->insn_opcode
|= lastregno
<< 21;
2932 ip
->insn_opcode
|= lastregno
<< 16;
2936 ip
->insn_opcode
|= lastregno
<< 11;
2942 /* handle optional base register.
2943 Either the base register is omitted or
2944 we must have a left paren. */
2945 /* this is dependent on the next operand specifier
2946 is a 'b' for base register */
2947 assert (args
[1] == 'b');
2951 case ')': /* these must match exactly */
2956 case '<': /* must be at least one digit */
2958 * According to the manual, if the shift amount is greater
2959 * than 31 or less than 0 the the shift amount should be
2960 * mod 32. In reality the mips assembler issues an error.
2961 * We issue a warning and do the mod.
2963 my_getExpression (&imm_expr
, s
);
2964 check_absolute_expr (ip
, &imm_expr
);
2965 if ((unsigned long) imm_expr
.X_add_number
> 31)
2967 as_warn ("Improper shift amount (%ld)",
2968 (long) imm_expr
.X_add_number
);
2969 imm_expr
.X_add_number
= imm_expr
.X_add_number
% 32;
2971 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2972 imm_expr
.X_op
= O_absent
;
2976 case 'c': /* break code */
2977 my_getExpression (&imm_expr
, s
);
2978 check_absolute_expr (ip
, &imm_expr
);
2979 if ((unsigned) imm_expr
.X_add_number
> 1023)
2980 as_warn ("Illegal break code (%ld)",
2981 (long) imm_expr
.X_add_number
);
2982 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
2983 imm_expr
.X_op
= O_absent
;
2987 case 'B': /* syscall code */
2988 my_getExpression (&imm_expr
, s
);
2989 check_absolute_expr (ip
, &imm_expr
);
2990 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
2991 as_warn ("Illegal syscall code (%ld)",
2992 (long) imm_expr
.X_add_number
);
2993 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
2994 imm_expr
.X_op
= O_absent
;
2998 case 'C': /* Coprocessor code */
2999 my_getExpression (&imm_expr
, s
);
3000 check_absolute_expr (ip
, &imm_expr
);
3001 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3003 as_warn ("Coproccesor code > 25 bits (%ld)",
3004 (long) imm_expr
.X_add_number
);
3005 imm_expr
.X_add_number
&= ((1<<25) - 1);
3007 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3008 imm_expr
.X_op
= O_absent
;
3012 case 'b': /* base register */
3013 case 'd': /* destination register */
3014 case 's': /* source register */
3015 case 't': /* target register */
3016 case 'r': /* both target and source */
3017 case 'v': /* both dest and source */
3018 case 'w': /* both dest and target */
3019 case 'E': /* coprocessor target register */
3020 case 'G': /* coprocessor destination register */
3021 case 'x': /* ignore register name */
3022 case 'z': /* must be zero register */
3036 while (isdigit (*s
));
3038 as_bad ("Invalid register number (%d)", regno
);
3040 else if (*args
!= 'E' && *args
!= 'G')
3042 if (s
[1] == 'f' && s
[2] == 'p')
3047 else if (s
[1] == 's' && s
[2] == 'p')
3052 else if (s
[1] == 'g' && s
[2] == 'p')
3057 else if (s
[1] == 'a' && s
[2] == 't')
3064 if (regno
== AT
&& ! mips_noat
)
3065 as_warn ("Used $at without \".set noat\"");
3072 if (c
== 'r' || c
== 'v' || c
== 'w')
3079 /* 'z' only matches $0. */
3080 if (c
== 'z' && regno
!= 0)
3088 ip
->insn_opcode
|= regno
<< 21;
3092 ip
->insn_opcode
|= regno
<< 11;
3097 ip
->insn_opcode
|= regno
<< 16;
3100 /* This case exists because on the r3000 trunc
3101 expands into a macro which requires a gp
3102 register. On the r6000 or r4000 it is
3103 assembled into a single instruction which
3104 ignores the register. Thus the insn version
3105 is MIPS_ISA2 and uses 'x', and the macro
3106 version is MIPS_ISA1 and uses 't'. */
3109 /* This case is for the div instruction, which
3110 acts differently if the destination argument
3111 is $0. This only matches $0, and is checked
3112 outside the switch. */
3123 ip
->insn_opcode
|= lastregno
<< 21;
3126 ip
->insn_opcode
|= lastregno
<< 16;
3131 case 'D': /* floating point destination register */
3132 case 'S': /* floating point source register */
3133 case 'T': /* floating point target register */
3137 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
3147 while (isdigit (*s
));
3150 as_bad ("Invalid float register number (%d)", regno
);
3153 !(strcmp (str
, "mtc1") == 0 ||
3154 strcmp (str
, "mfc1") == 0 ||
3155 strcmp (str
, "lwc1") == 0 ||
3156 strcmp (str
, "swc1") == 0))
3157 as_warn ("Float register should be even, was %d",
3165 if (c
== 'V' || c
== 'W')
3175 ip
->insn_opcode
|= regno
<< 6;
3179 ip
->insn_opcode
|= regno
<< 11;
3183 ip
->insn_opcode
|= regno
<< 16;
3191 ip
->insn_opcode
|= lastregno
<< 11;
3194 ip
->insn_opcode
|= lastregno
<< 16;
3200 my_getExpression (&imm_expr
, s
);
3201 check_absolute_expr (ip
, &imm_expr
);
3206 my_getExpression (&offset_expr
, s
);
3207 imm_reloc
= BFD_RELOC_32
;
3219 unsigned char temp
[8];
3221 unsigned int length
;
3226 /* These only appear as the last operand in an
3227 instruction, and every instruction that accepts
3228 them in any variant accepts them in all variants.
3229 This means we don't have to worry about backing out
3230 any changes if the instruction does not match.
3232 The difference between them is the size of the
3233 floating point constant and where it goes. For 'F'
3234 and 'L' the constant is 64 bits; for 'f' and 'l' it
3235 is 32 bits. Where the constant is placed is based
3236 on how the MIPS assembler does things:
3239 f -- immediate value
3243 f64
= *args
== 'F' || *args
== 'L';
3245 save_in
= input_line_pointer
;
3246 input_line_pointer
= s
;
3247 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
3249 s
= input_line_pointer
;
3250 input_line_pointer
= save_in
;
3251 if (err
!= NULL
&& *err
!= '\0')
3253 as_bad ("Bad floating point constant: %s", err
);
3254 memset (temp
, '\0', sizeof temp
);
3255 length
= f64
? 8 : 4;
3258 assert (length
== (f64
? 8 : 4));
3262 imm_expr
.X_op
= O_constant
;
3263 if (byte_order
== LITTLE_ENDIAN
)
3264 imm_expr
.X_add_number
=
3265 (((((((int) temp
[3] << 8)
3270 imm_expr
.X_add_number
=
3271 (((((((int) temp
[0] << 8)
3278 /* Switch to the right section. */
3280 subseg
= now_subseg
;
3284 subseg_new (".rdata", (subsegT
) 0);
3287 subseg_new (".lit8", (subsegT
) 0);
3290 subseg_new (".lit4", (subsegT
) 0);
3294 as_bad ("Can't use floating point insn in this section");
3296 /* Set the argument to the current address in the
3298 offset_expr
.X_op
= O_symbol
;
3299 offset_expr
.X_add_symbol
=
3300 symbol_new ("L0\001", now_seg
,
3301 (valueT
) frag_now_fix (), frag_now
);
3302 offset_expr
.X_add_number
= 0;
3304 /* Put the floating point number into the section. */
3305 p
= frag_more ((int) length
);
3306 memcpy (p
, temp
, length
);
3308 /* Switch back to the original section. */
3309 subseg_set (seg
, subseg
);
3314 case 'i': /* 16 bit unsigned immediate */
3315 case 'j': /* 16 bit signed immediate */
3316 imm_reloc
= BFD_RELOC_LO16
;
3317 c
= my_getSmallExpression (&imm_expr
, s
);
3322 if (imm_expr
.X_op
== O_constant
)
3323 imm_expr
.X_add_number
=
3324 (imm_expr
.X_add_number
>> 16) & 0xffff;
3326 imm_reloc
= BFD_RELOC_HI16_S
;
3328 imm_reloc
= BFD_RELOC_HI16
;
3332 check_absolute_expr (ip
, &imm_expr
);
3335 if (imm_expr
.X_add_number
< 0
3336 || imm_expr
.X_add_number
>= 0x10000)
3338 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3339 !strcmp (insn
->name
, insn
[1].name
))
3341 as_bad ("16 bit expression not in range 0..65535");
3346 if (imm_expr
.X_add_number
< -0x8000 ||
3347 imm_expr
.X_add_number
>= 0x8000)
3349 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3350 !strcmp (insn
->name
, insn
[1].name
))
3352 as_bad ("16 bit expression not in range -32768..32767");
3358 case 'o': /* 16 bit offset */
3359 c
= my_getSmallExpression (&offset_expr
, s
);
3361 * If this value won't fit into a 16 bit offset, then
3362 * go find a macro that will generate the 32 bit offset
3365 if (offset_expr
.X_op
!= O_constant
3366 || offset_expr
.X_add_number
>= 0x8000
3367 || offset_expr
.X_add_number
< -0x8000)
3370 offset_reloc
= BFD_RELOC_LO16
;
3371 if (c
== 'h' || c
== 'H')
3373 assert (offset_expr
.X_op
== O_constant
);
3374 offset_expr
.X_add_number
=
3375 (offset_expr
.X_add_number
>> 16) & 0xffff;
3380 case 'p': /* pc relative offset */
3381 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
3382 my_getExpression (&offset_expr
, s
);
3386 case 'u': /* upper 16 bits */
3387 c
= my_getSmallExpression (&imm_expr
, s
);
3388 if (imm_expr
.X_op
!= O_constant
3389 || imm_expr
.X_add_number
< 0
3390 || imm_expr
.X_add_number
>= 0x10000)
3391 as_bad ("lui expression not in range 0..65535");
3392 imm_reloc
= BFD_RELOC_LO16
;
3397 if (imm_expr
.X_op
== O_constant
)
3398 imm_expr
.X_add_number
=
3399 (imm_expr
.X_add_number
>> 16) & 0xffff;
3401 imm_reloc
= BFD_RELOC_HI16_S
;
3403 imm_reloc
= BFD_RELOC_HI16
;
3409 case 'a': /* 26 bit address */
3410 my_getExpression (&offset_expr
, s
);
3412 offset_reloc
= BFD_RELOC_MIPS_JMP
;
3416 fprintf (stderr
, "bad char = '%c'\n", *args
);
3421 /* Args don't match. */
3422 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
3423 !strcmp (insn
->name
, insn
[1].name
))
3429 insn_error
= "ERROR: Illegal operands";
3438 my_getSmallExpression (ep
, str
)
3449 ((str
[1] == 'h' && str
[2] == 'i')
3450 || (str
[1] == 'H' && str
[2] == 'I')
3451 || (str
[1] == 'l' && str
[2] == 'o'))
3463 * A small expression may be followed by a base register.
3464 * Scan to the end of this operand, and then back over a possible
3465 * base register. Then scan the small expression up to that
3466 * point. (Based on code in sparc.c...)
3468 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
3470 if (sp
- 4 >= str
&& sp
[-1] == RP
)
3472 if (isdigit (sp
[-2]))
3474 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
3476 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
3482 else if (sp
- 5 >= str
3485 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
3486 || (sp
[-3] == 's' && sp
[-2] == 'p')
3487 || (sp
[-3] == 'g' && sp
[-2] == 'p')
3488 || (sp
[-3] == 'a' && sp
[-2] == 't')))
3494 /* no expression means zero offset */
3497 /* %xx(reg) is an error */
3498 ep
->X_op
= O_absent
;
3503 ep
->X_op
= O_absent
;
3506 ep
->X_add_symbol
= NULL
;
3507 ep
->X_op_symbol
= NULL
;
3508 ep
->X_add_number
= 0;
3513 my_getExpression (ep
, str
);
3520 my_getExpression (ep
, str
);
3521 return c
; /* => %hi or %lo encountered */
3525 my_getExpression (ep
, str
)
3531 save_in
= input_line_pointer
;
3532 input_line_pointer
= str
;
3534 expr_end
= input_line_pointer
;
3535 input_line_pointer
= save_in
;
3538 /* Turn a string in input_line_pointer into a floating point constant
3539 of type type, and store the appropriate bytes in *litP. The number
3540 of LITTLENUMS emitted is stored in *sizeP . An error message is
3541 returned, or NULL on OK. */
3544 md_atof (type
, litP
, sizeP
)
3550 LITTLENUM_TYPE words
[4];
3566 return "bad call to md_atof";
3569 t
= atof_ieee (input_line_pointer
, type
, words
);
3571 input_line_pointer
= t
;
3575 if (byte_order
== LITTLE_ENDIAN
)
3577 for (i
= prec
- 1; i
>= 0; i
--)
3579 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3585 for (i
= 0; i
< prec
; i
++)
3587 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
3596 md_number_to_chars (buf
, val
, n
)
3644 md_number_to_chars (buf
, hi
, 4);
3669 md_parse_option (argP
, cntP
, vecP
)
3674 /* Accept -nocpp but ignore it. */
3675 if (strcmp (*argP
, "nocpp") == 0)
3681 if (strcmp (*argP
, "EL") == 0
3682 || strcmp (*argP
, "EB") == 0)
3684 /* FIXME: This breaks -L -EL. */
3692 if ((*argP
)[1] == '0')
3701 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
3706 if (strncmp (*argP
, "mips", 4) == 0)
3708 mips_isa
= atol (*argP
+ 4);
3711 else if (mips_isa
< 1 || mips_isa
> 3)
3713 as_bad ("-mips%d not supported", mips_isa
);
3720 if (strncmp (*argP
, "mcpu=", 5) == 0)
3724 /* Identify the processor type */
3726 if (strcmp (p
, "default") == 0
3727 || strcmp (p
, "DEFAULT") == 0)
3731 if (*p
== 'r' || *p
== 'R')
3738 if (strcmp (p
, "2000") == 0
3739 || strcmp (p
, "2k") == 0
3740 || strcmp (p
, "2K") == 0)
3745 if (strcmp (p
, "3000") == 0
3746 || strcmp (p
, "3k") == 0
3747 || strcmp (p
, "3K") == 0)
3752 if (strcmp (p
, "4000") == 0
3753 || strcmp (p
, "4k") == 0
3754 || strcmp (p
, "4K") == 0)
3759 if (strcmp (p
, "6000") == 0
3760 || strcmp (p
, "6k") == 0
3761 || strcmp (p
, "6K") == 0)
3768 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
3781 if ((*argP
)[1] != '\0')
3782 g_switch_value
= atoi (*argP
+ 1);
3785 **vecP
= (char *) NULL
;
3788 g_switch_value
= atoi (**vecP
);
3791 as_warn ("Number expected after -G");
3797 return 1; /* pretend you parsed the character */
3801 md_pcrel_from (fixP
)
3804 /* return the address of the delay slot */
3805 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
3809 md_apply_fix (fixP
, valueP
)
3816 assert (fixP
->fx_size
== 4);
3819 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
3821 switch (fixP
->fx_r_type
)
3824 case BFD_RELOC_MIPS_JMP
:
3825 case BFD_RELOC_HI16
:
3826 case BFD_RELOC_HI16_S
:
3827 case BFD_RELOC_LO16
:
3828 case BFD_RELOC_MIPS_GPREL
:
3829 /* Nothing needed to do. The value comes from the reloc entry */
3832 case BFD_RELOC_16_PCREL_S2
:
3834 * We need to save the bits in the instruction since fixup_segment()
3835 * might be deleting the relocation entry (i.e., a branch within
3836 * the current segment).
3839 as_warn ("Branch to odd address (%lx)", value
);
3841 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
3842 as_bad ("Relocation overflow");
3844 /* update old instruction data */
3845 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
3849 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
3853 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
3860 insn
|= value
& 0xFFFF;
3861 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
3875 const struct mips_opcode
*p
;
3876 int treg
, sreg
, dreg
, shamt
;
3881 for (i
= 0; i
< NUMOPCODES
; ++i
)
3883 p
= &mips_opcodes
[i
];
3884 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
3886 printf ("%08lx %s\t", oc
, p
->name
);
3887 treg
= (oc
>> 16) & 0x1f;
3888 sreg
= (oc
>> 21) & 0x1f;
3889 dreg
= (oc
>> 11) & 0x1f;
3890 shamt
= (oc
>> 6) & 0x1f;
3892 for (args
= p
->args
;; ++args
)
3903 printf ("%c", *args
);
3907 assert (treg
== sreg
);
3908 printf ("$%d,$%d", treg
, sreg
);
3913 printf ("$%d", dreg
);
3918 printf ("$%d", treg
);
3923 printf ("$%d", sreg
);
3927 printf ("0x%08lx", oc
& 0x1ffffff);
3938 printf ("$%d", shamt
);
3949 printf ("%08lx UNDEFINED\n", oc
);
3960 name
= input_line_pointer
;
3961 c
= get_symbol_end ();
3962 p
= (symbolS
*) symbol_find_or_make (name
);
3963 *input_line_pointer
= c
;
3967 /* Align the current frag to a given power of two. The MIPS assembler
3968 also automatically adjusts any preceding label. */
3971 mips_align (to
, fill
)
3975 mips_emit_delays ();
3976 frag_align (to
, fill
);
3977 record_alignment (now_seg
, to
);
3978 if (insn_label
!= NULL
)
3980 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
3981 insn_label
->sy_frag
= frag_now
;
3982 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
3987 /* Align to a given power of two. .align 0 turns off the automatic
3988 alignment used by the data creating pseudo-ops. */
3995 register long temp_fill
;
3996 long max_alignment
= 15;
4000 o Note that the assembler pulls down any immediately preceeding label
4001 to the aligned address.
4002 o It's not documented but auto alignment is reinstated by
4003 a .align pseudo instruction.
4004 o Note also that after auto alignment is turned off the mips assembler
4005 issues an error on attempt to assemble an improperly aligned data item.
4010 temp
= get_absolute_expression ();
4011 if (temp
> max_alignment
)
4012 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4015 as_warn ("Alignment negative: 0 assumed.");
4018 if (*input_line_pointer
== ',')
4020 input_line_pointer
++;
4021 temp_fill
= get_absolute_expression ();
4028 mips_align (temp
, (int) temp_fill
);
4035 demand_empty_rest_of_line ();
4038 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4039 that there was a previous instruction. */
4042 s_stringer (append_zero
)
4045 mips_emit_delays ();
4047 stringer (append_zero
);
4056 mips_emit_delays ();
4065 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
4066 demand_empty_rest_of_line ();
4075 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
4076 demand_empty_rest_of_line ();
4080 subseg_new (".sdata", (subsegT
) get_absolute_expression ());
4081 demand_empty_rest_of_line ();
4084 as_bad ("Global pointers not supported; recompile -G 0");
4085 demand_empty_rest_of_line ();
4096 mips_emit_delays ();
4097 if (log_size
> 0 && auto_align
)
4098 mips_align (log_size
, 0);
4100 cons (1 << log_size
);
4107 as_fatal ("Encountered `.err', aborting assembly");
4117 symbolP
= get_symbol ();
4118 if (*input_line_pointer
== ',')
4119 input_line_pointer
++;
4120 size
= get_absolute_expression ();
4121 S_SET_VALUE (symbolP
, size
);
4122 S_SET_EXTERNAL (symbolP
);
4125 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
4126 so we use an additional ECOFF specific field. */
4127 symbolP
->ecoff_undefined
= 1;
4135 mips_emit_delays ();
4152 if (strcmp (input_line_pointer
, "O1") != 0
4153 && strcmp (input_line_pointer
, "O2") != 0)
4154 as_warn ("Unrecognized option");
4155 demand_empty_rest_of_line ();
4162 char *name
= input_line_pointer
, ch
;
4164 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4165 input_line_pointer
++;
4166 ch
= *input_line_pointer
;
4167 *input_line_pointer
= '\0';
4169 if (strcmp (name
, "reorder") == 0)
4173 prev_insn_unreordered
= 1;
4174 prev_prev_insn_unreordered
= 1;
4178 else if (strcmp (name
, "noreorder") == 0)
4180 mips_emit_delays ();
4183 else if (strcmp (name
, "at") == 0)
4187 else if (strcmp (name
, "noat") == 0)
4191 else if (strcmp (name
, "macro") == 0)
4193 mips_warn_about_macros
= 0;
4195 else if (strcmp (name
, "nomacro") == 0)
4197 if (mips_noreorder
== 0)
4198 as_bad ("`noreorder' must be set before `nomacro'");
4199 mips_warn_about_macros
= 1;
4201 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
4205 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
4209 else if (strcmp (name
, "bopt") == 0)
4213 else if (strcmp (name
, "nobopt") == 0)
4219 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
4221 *input_line_pointer
= ch
;
4222 demand_empty_rest_of_line ();
4225 /* The same as the usual .space directive, except that we have to
4226 forget about any previous instruction. */
4229 s_mips_space (param
)
4232 mips_emit_delays ();
4243 if (*input_line_pointer
++ != '$')
4245 as_warn ("expected `$'");
4248 if (isdigit ((unsigned char) *input_line_pointer
))
4250 reg
= get_absolute_expression ();
4251 if (reg
< 0 || reg
>= 32)
4253 as_warn ("Bad register number");
4259 if (strncmp (input_line_pointer
, "fp", 2) == 0)
4261 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
4263 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
4265 else if (strncmp (input_line_pointer
, "at", 2) == 0)
4269 as_warn ("Unrecognized register name");
4272 input_line_pointer
+= 2;
4278 * Translate internal representation of relocation info to BFD target format.
4281 tc_gen_reloc (section
, fixp
)
4287 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
4288 assert (reloc
!= 0);
4290 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
4291 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
4292 if (fixp
->fx_pcrel
== 0)
4293 reloc
->addend
= fixp
->fx_addnumber
;
4298 reloc
->addend
= -reloc
->address
;
4300 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
4301 assert (reloc
->howto
!= 0);
4306 /* should never be called */
4308 md_section_align (seg
, addr
)
4312 int align
= bfd_get_section_alignment (stdoutput
, seg
);
4314 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
4318 md_estimate_size_before_relax (fragP
, segtype
)
4322 as_fatal ("md_estimate_size_before_relax");
4324 } /* md_estimate_size_before_relax() */
4326 /* This function is called whenever a label is defined. It is used
4327 when handling branch delays; if a branch has a label, we assume we
4331 mips_define_label (sym
)
4339 /* These functions should really be defined by the object file format,
4340 since they are related to debugging information. However, this
4341 code has to work for the a.out format, which does not define them,
4342 so we provide simple versions here. These don't actually generate
4343 any debugging information, but they do simple checking and someday
4344 somebody may make them useful. */
4348 struct loc
*loc_next
;
4349 unsigned long loc_fileno
;
4350 unsigned long loc_lineno
;
4351 unsigned long loc_offset
;
4352 unsigned short loc_delta
;
4353 unsigned short loc_count
;
4362 struct proc
*proc_next
;
4363 struct symbol
*proc_isym
;
4364 struct symbol
*proc_end
;
4365 unsigned long proc_reg_mask
;
4366 unsigned long proc_reg_offset
;
4367 unsigned long proc_fpreg_mask
;
4368 unsigned long proc_fpreg_offset
;
4369 unsigned long proc_frameoffset
;
4370 unsigned long proc_framereg
;
4371 unsigned long proc_pcreg
;
4373 struct file
*proc_file
;
4380 struct file
*file_next
;
4381 unsigned long file_fileno
;
4382 struct symbol
*file_symbol
;
4383 struct symbol
*file_end
;
4384 struct proc
*file_proc
;
4389 static struct obstack proc_frags
;
4390 static procS
*proc_lastP
;
4391 static procS
*proc_rootP
;
4392 static int numprocs
;
4397 obstack_begin (&proc_frags
, 0x2000);
4403 /* check for premature end, nesting errors, etc */
4404 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4405 as_warn ("missing `.end' at end of assembly");
4408 extern char hex_value
[];
4416 if (*input_line_pointer
== '-')
4418 ++input_line_pointer
;
4421 if (!isdigit (*input_line_pointer
))
4422 as_bad ("Expected simple number.");
4423 if (input_line_pointer
[0] == '0')
4425 if (input_line_pointer
[1] == 'x')
4427 input_line_pointer
+= 2;
4428 while (isxdigit (*input_line_pointer
))
4431 val
|= hex_value
[(int) *input_line_pointer
++];
4433 return negative
? -val
: val
;
4437 ++input_line_pointer
;
4438 while (isdigit (*input_line_pointer
))
4441 val
|= *input_line_pointer
++ - '0';
4443 return negative
? -val
: val
;
4446 if (!isdigit (*input_line_pointer
))
4448 printf (" *input_line_pointer == '%c' 0x%02x\n",
4449 *input_line_pointer
, *input_line_pointer
);
4450 as_warn ("Invalid number");
4453 while (isdigit (*input_line_pointer
))
4456 val
+= *input_line_pointer
++ - '0';
4458 return negative
? -val
: val
;
4461 /* The .file directive; just like the usual .file directive, but there
4462 is an initial number which is the ECOFF file index. */
4470 line
= get_number ();
4475 /* The .end directive. */
4483 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
4486 demand_empty_rest_of_line ();
4490 if (now_seg
!= text_section
)
4491 as_warn (".end not in text section");
4494 as_warn (".end and no .ent seen yet.");
4500 assert (S_GET_NAME (p
));
4501 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
4502 as_warn (".end symbol does not match .ent symbol.");
4505 proc_lastP
->proc_end
= (symbolS
*) 1;
4508 /* The .aent and .ent directives. */
4518 symbolP
= get_symbol ();
4519 if (*input_line_pointer
== ',')
4520 input_line_pointer
++;
4521 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
4522 number
= get_number ();
4523 if (now_seg
!= text_section
)
4524 as_warn (".ent or .aent not in text section.");
4526 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
4527 as_warn ("missing `.end'");
4531 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
4532 procP
->proc_isym
= symbolP
;
4533 procP
->proc_reg_mask
= 0;
4534 procP
->proc_reg_offset
= 0;
4535 procP
->proc_fpreg_mask
= 0;
4536 procP
->proc_fpreg_offset
= 0;
4537 procP
->proc_frameoffset
= 0;
4538 procP
->proc_framereg
= 0;
4539 procP
->proc_pcreg
= 0;
4540 procP
->proc_end
= NULL
;
4541 procP
->proc_next
= NULL
;
4543 proc_lastP
->proc_next
= procP
;
4549 demand_empty_rest_of_line ();
4552 /* The .frame directive. */
4565 frame_reg
= tc_get_register ();
4566 if (*input_line_pointer
== ',')
4567 input_line_pointer
++;
4568 frame_off
= get_absolute_expression ();
4569 if (*input_line_pointer
== ',')
4570 input_line_pointer
++;
4571 pcreg
= tc_get_register ();
4574 assert (proc_rootP
);
4575 proc_rootP
->proc_framereg
= frame_reg
;
4576 proc_rootP
->proc_frameoffset
= frame_off
;
4577 proc_rootP
->proc_pcreg
= pcreg
;
4578 /* bob macho .frame */
4580 /* We don't have to write out a frame stab for unoptimized code. */
4581 if (!(frame_reg
== 30 && frame_off
== 0))
4584 as_warn ("No .ent for .frame to use.");
4585 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
4586 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
4587 S_SET_TYPE (symP
, N_RMASK
);
4588 S_SET_OTHER (symP
, 0);
4589 S_SET_DESC (symP
, 0);
4590 symP
->sy_forward
= proc_lastP
->proc_isym
;
4591 /* bob perhaps I should have used pseudo set */
4593 demand_empty_rest_of_line ();
4597 /* The .fmask and .mask directives. */
4604 char str
[100], *strP
;
4610 mask
= get_number ();
4611 if (*input_line_pointer
== ',')
4612 input_line_pointer
++;
4613 off
= get_absolute_expression ();
4615 /* bob only for coff */
4616 assert (proc_rootP
);
4617 if (reg_type
== 'F')
4619 proc_rootP
->proc_fpreg_mask
= mask
;
4620 proc_rootP
->proc_fpreg_offset
= off
;
4624 proc_rootP
->proc_reg_mask
= mask
;
4625 proc_rootP
->proc_reg_offset
= off
;
4628 /* bob macho .mask + .fmask */
4630 /* We don't have to write out a mask stab if no saved regs. */
4634 as_warn ("No .ent for .mask to use.");
4636 for (i
= 0; i
< 32; i
++)
4640 sprintf (strP
, "%c%d,", reg_type
, i
);
4641 strP
+= strlen (strP
);
4645 sprintf (strP
, ";%d,", off
);
4646 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
4647 S_SET_TYPE (symP
, N_RMASK
);
4648 S_SET_OTHER (symP
, 0);
4649 S_SET_DESC (symP
, 0);
4650 symP
->sy_forward
= proc_lastP
->proc_isym
;
4651 /* bob perhaps I should have used pseudo set */
4656 /* The .loc directive. */
4667 assert (now_seg
== text_section
);
4669 lineno
= get_number ();
4670 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
4672 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
4673 S_SET_TYPE (symbolP
, N_SLINE
);
4674 S_SET_OTHER (symbolP
, 0);
4675 S_SET_DESC (symbolP
, lineno
);
4676 symbolP
->sy_segment
= now_seg
;
4680 #endif /* ! defined (OBJ_ECOFF) */