1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* The name of the readonly data section. */
106 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
108 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
110 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
112 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
116 /* The ABI to use. */
127 /* MIPS ABI we are using for this output file. */
128 static enum mips_abi_level file_mips_abi
= NO_ABI
;
130 /* This is the set of options which may be modified by the .set
131 pseudo-op. We use a struct so that .set push and .set pop are more
134 struct mips_set_options
136 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
137 if it has not been initialized. Changed by `.set mipsN', and the
138 -mipsN command line option, and the default CPU. */
140 /* Whether we are assembling for the mips16 processor. 0 if we are
141 not, 1 if we are, and -1 if the value has not been initialized.
142 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
143 -nomips16 command line options, and the default CPU. */
145 /* Non-zero if we should not reorder instructions. Changed by `.set
146 reorder' and `.set noreorder'. */
148 /* Non-zero if we should not permit the $at ($1) register to be used
149 in instructions. Changed by `.set at' and `.set noat'. */
151 /* Non-zero if we should warn when a macro instruction expands into
152 more than one machine instruction. Changed by `.set nomacro' and
154 int warn_about_macros
;
155 /* Non-zero if we should not move instructions. Changed by `.set
156 move', `.set volatile', `.set nomove', and `.set novolatile'. */
158 /* Non-zero if we should not optimize branches by moving the target
159 of the branch into the delay slot. Actually, we don't perform
160 this optimization anyhow. Changed by `.set bopt' and `.set
163 /* Non-zero if we should not autoextend mips16 instructions.
164 Changed by `.set autoextend' and `.set noautoextend'. */
166 /* Restrict general purpose registers and floating point registers
167 to 32 bit. This is initially determined when -mgp32 or -mfp32
168 is passed but can changed if the assembler code uses .set mipsN. */
171 /* The ABI currently in use. This is changed by .set mipsN to loosen
172 restrictions and doesn't affect the whole file. */
173 enum mips_abi_level abi
;
176 /* True if -mgp32 was passed. */
177 static int file_mips_gp32
= -1;
179 /* True if -mfp32 was passed. */
180 static int file_mips_fp32
= -1;
182 /* This is the struct we use to hold the current set of options. Note
183 that we must set the isa field to ISA_UNKNOWN and the mips16 field to
184 -1 to indicate that they have not been initialized. */
186 static struct mips_set_options mips_opts
=
188 ISA_UNKNOWN
, -1, 0, 0, 0, 0, 0, 0, 0, 0, NO_ABI
191 /* These variables are filled in with the masks of registers used.
192 The object format code reads them and puts them in the appropriate
194 unsigned long mips_gprmask
;
195 unsigned long mips_cprmask
[4];
197 /* MIPS ISA we are using for this output file. */
198 static int file_mips_isa
= ISA_UNKNOWN
;
200 /* The argument of the -mcpu= flag. Historical for code generation. */
201 static int mips_cpu
= CPU_UNKNOWN
;
203 /* The argument of the -march= flag. The architecture we are assembling. */
204 static int mips_arch
= CPU_UNKNOWN
;
206 /* The argument of the -mtune= flag. The architecture for which we
208 static int mips_tune
= CPU_UNKNOWN
;
210 /* Whether we should mark the file EABI64 or EABI32. */
211 static int mips_eabi64
= 0;
213 /* If they asked for mips1 or mips2 and a cpu that is
214 mips3 or greater, then mark the object file 32BITMODE. */
215 static int mips_32bitmode
= 0;
217 /* Some ISA's have delay slots for instructions which read or write
218 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
219 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
220 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
221 delay slot in this ISA. The uses of this macro assume that any
222 ISA that has delay slots for one of these, has them for all. They
223 also assume that ISAs which don't have delays for these insns, don't
224 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
225 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
227 || (ISA) == ISA_MIPS2 \
228 || (ISA) == ISA_MIPS3 \
231 /* Return true if ISA supports 64 bit gp register instructions. */
232 #define ISA_HAS_64BIT_REGS(ISA) ( \
234 || (ISA) == ISA_MIPS4 \
235 || (ISA) == ISA_MIPS5 \
236 || (ISA) == ISA_MIPS64 \
239 #define HAVE_32BIT_GPRS \
241 || mips_opts.abi == O32_ABI \
242 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
244 #define HAVE_32BIT_FPRS \
246 || mips_opts.abi == O32_ABI \
247 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
249 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
250 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
252 #define HAVE_NEWABI (mips_opts.abi == N32_ABI || mips_opts.abi == N64_ABI)
254 #define HAVE_64BIT_OBJECTS (mips_opts.abi == N64_ABI)
256 /* We can only have 64bit addresses if the object file format
258 #define HAVE_32BIT_ADDRESSES \
260 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
261 || ! HAVE_64BIT_OBJECTS) \
262 && mips_pic != EMBEDDED_PIC))
264 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
266 /* Whether the processor uses hardware interlocks to protect
267 reads from the HI and LO registers, and thus does not
268 require nops to be inserted. */
270 #define hilo_interlocks (mips_arch == CPU_R4010 \
271 || mips_arch == CPU_SB1 \
274 /* Whether the processor uses hardware interlocks to protect reads
275 from the GPRs, and thus does not require nops to be inserted. */
276 #define gpr_interlocks \
277 (mips_opts.isa != ISA_MIPS1 \
278 || mips_arch == CPU_R3900)
280 /* As with other "interlocks" this is used by hardware that has FP
281 (co-processor) interlocks. */
282 /* Itbl support may require additional care here. */
283 #define cop_interlocks (mips_arch == CPU_R4300 \
284 || mips_arch == CPU_SB1 \
287 /* Is this a mfhi or mflo instruction? */
288 #define MF_HILO_INSN(PINFO) \
289 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
291 /* MIPS PIC level. */
295 /* Do not generate PIC code. */
298 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
299 not sure what it is supposed to do. */
302 /* Generate PIC code as in the SVR4 MIPS ABI. */
305 /* Generate PIC code without using a global offset table: the data
306 segment has a maximum size of 64K, all data references are off
307 the $gp register, and all text references are PC relative. This
308 is used on some embedded systems. */
312 static enum mips_pic_level mips_pic
;
314 /* Warn about all NOPS that the assembler generates. */
315 static int warn_nops
= 0;
317 /* 1 if we should generate 32 bit offsets from the GP register in
318 SVR4_PIC mode. Currently has no meaning in other modes. */
319 static int mips_big_got
;
321 /* 1 if trap instructions should used for overflow rather than break
323 static int mips_trap
;
325 /* 1 if double width floating point constants should not be constructed
326 by assembling two single width halves into two single width floating
327 point registers which just happen to alias the double width destination
328 register. On some architectures this aliasing can be disabled by a bit
329 in the status register, and the setting of this bit cannot be determined
330 automatically at assemble time. */
331 static int mips_disable_float_construction
;
333 /* Non-zero if any .set noreorder directives were used. */
335 static int mips_any_noreorder
;
337 /* Non-zero if nops should be inserted when the register referenced in
338 an mfhi/mflo instruction is read in the next two instructions. */
339 static int mips_7000_hilo_fix
;
341 /* The size of the small data section. */
342 static unsigned int g_switch_value
= 8;
343 /* Whether the -G option was used. */
344 static int g_switch_seen
= 0;
349 /* If we can determine in advance that GP optimization won't be
350 possible, we can skip the relaxation stuff that tries to produce
351 GP-relative references. This makes delay slot optimization work
354 This function can only provide a guess, but it seems to work for
355 gcc output. It needs to guess right for gcc, otherwise gcc
356 will put what it thinks is a GP-relative instruction in a branch
359 I don't know if a fix is needed for the SVR4_PIC mode. I've only
360 fixed it for the non-PIC mode. KR 95/04/07 */
361 static int nopic_need_relax
PARAMS ((symbolS
*, int));
363 /* handle of the OPCODE hash table */
364 static struct hash_control
*op_hash
= NULL
;
366 /* The opcode hash table we use for the mips16. */
367 static struct hash_control
*mips16_op_hash
= NULL
;
369 /* This array holds the chars that always start a comment. If the
370 pre-processor is disabled, these aren't very useful */
371 const char comment_chars
[] = "#";
373 /* This array holds the chars that only start a comment at the beginning of
374 a line. If the line seems to have the form '# 123 filename'
375 .line and .file directives will appear in the pre-processed output */
376 /* Note that input_file.c hand checks for '#' at the beginning of the
377 first line of the input file. This is because the compiler outputs
378 #NO_APP at the beginning of its output. */
379 /* Also note that C style comments are always supported. */
380 const char line_comment_chars
[] = "#";
382 /* This array holds machine specific line separator characters. */
383 const char line_separator_chars
[] = ";";
385 /* Chars that can be used to separate mant from exp in floating point nums */
386 const char EXP_CHARS
[] = "eE";
388 /* Chars that mean this number is a floating point constant */
391 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
393 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
394 changed in read.c . Ideally it shouldn't have to know about it at all,
395 but nothing is ideal around here.
398 static char *insn_error
;
400 static int auto_align
= 1;
402 /* When outputting SVR4 PIC code, the assembler needs to know the
403 offset in the stack frame from which to restore the $gp register.
404 This is set by the .cprestore pseudo-op, and saved in this
406 static offsetT mips_cprestore_offset
= -1;
408 /* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
409 more optimizations, it can use a register value instead of a memory-saved
410 offset and even an other register than $gp as global pointer. */
411 static offsetT mips_cpreturn_offset
= -1;
412 static int mips_cpreturn_register
= -1;
413 static int mips_gp_register
= GP
;
415 /* Whether mips_cprestore_offset has been set in the current function
416 (or whether it has already been warned about, if not). */
417 static int mips_cprestore_valid
= 0;
419 /* This is the register which holds the stack frame, as set by the
420 .frame pseudo-op. This is needed to implement .cprestore. */
421 static int mips_frame_reg
= SP
;
423 /* Whether mips_frame_reg has been set in the current function
424 (or whether it has already been warned about, if not). */
425 static int mips_frame_reg_valid
= 0;
427 /* To output NOP instructions correctly, we need to keep information
428 about the previous two instructions. */
430 /* Whether we are optimizing. The default value of 2 means to remove
431 unneeded NOPs and swap branch instructions when possible. A value
432 of 1 means to not swap branches. A value of 0 means to always
434 static int mips_optimize
= 2;
436 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
437 equivalent to seeing no -g option at all. */
438 static int mips_debug
= 0;
440 /* The previous instruction. */
441 static struct mips_cl_insn prev_insn
;
443 /* The instruction before prev_insn. */
444 static struct mips_cl_insn prev_prev_insn
;
446 /* If we don't want information for prev_insn or prev_prev_insn, we
447 point the insn_mo field at this dummy integer. */
448 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
450 /* Non-zero if prev_insn is valid. */
451 static int prev_insn_valid
;
453 /* The frag for the previous instruction. */
454 static struct frag
*prev_insn_frag
;
456 /* The offset into prev_insn_frag for the previous instruction. */
457 static long prev_insn_where
;
459 /* The reloc type for the previous instruction, if any. */
460 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
462 /* The reloc for the previous instruction, if any. */
463 static fixS
*prev_insn_fixp
[3];
465 /* Non-zero if the previous instruction was in a delay slot. */
466 static int prev_insn_is_delay_slot
;
468 /* Non-zero if the previous instruction was in a .set noreorder. */
469 static int prev_insn_unreordered
;
471 /* Non-zero if the previous instruction uses an extend opcode (if
473 static int prev_insn_extended
;
475 /* Non-zero if the previous previous instruction was in a .set
477 static int prev_prev_insn_unreordered
;
479 /* If this is set, it points to a frag holding nop instructions which
480 were inserted before the start of a noreorder section. If those
481 nops turn out to be unnecessary, the size of the frag can be
483 static fragS
*prev_nop_frag
;
485 /* The number of nop instructions we created in prev_nop_frag. */
486 static int prev_nop_frag_holds
;
488 /* The number of nop instructions that we know we need in
490 static int prev_nop_frag_required
;
492 /* The number of instructions we've seen since prev_nop_frag. */
493 static int prev_nop_frag_since
;
495 /* For ECOFF and ELF, relocations against symbols are done in two
496 parts, with a HI relocation and a LO relocation. Each relocation
497 has only 16 bits of space to store an addend. This means that in
498 order for the linker to handle carries correctly, it must be able
499 to locate both the HI and the LO relocation. This means that the
500 relocations must appear in order in the relocation table.
502 In order to implement this, we keep track of each unmatched HI
503 relocation. We then sort them so that they immediately precede the
504 corresponding LO relocation. */
509 struct mips_hi_fixup
*next
;
512 /* The section this fixup is in. */
516 /* The list of unmatched HI relocs. */
518 static struct mips_hi_fixup
*mips_hi_fixup_list
;
520 /* Map normal MIPS register numbers to mips16 register numbers. */
522 #define X ILLEGAL_REG
523 static const int mips32_to_16_reg_map
[] =
525 X
, X
, 2, 3, 4, 5, 6, 7,
526 X
, X
, X
, X
, X
, X
, X
, X
,
527 0, 1, X
, X
, X
, X
, X
, X
,
528 X
, X
, X
, X
, X
, X
, X
, X
532 /* Map mips16 register numbers to normal MIPS register numbers. */
534 static const unsigned int mips16_to_32_reg_map
[] =
536 16, 17, 2, 3, 4, 5, 6, 7
539 /* Since the MIPS does not have multiple forms of PC relative
540 instructions, we do not have to do relaxing as is done on other
541 platforms. However, we do have to handle GP relative addressing
542 correctly, which turns out to be a similar problem.
544 Every macro that refers to a symbol can occur in (at least) two
545 forms, one with GP relative addressing and one without. For
546 example, loading a global variable into a register generally uses
547 a macro instruction like this:
549 If i can be addressed off the GP register (this is true if it is in
550 the .sbss or .sdata section, or if it is known to be smaller than
551 the -G argument) this will generate the following instruction:
553 This instruction will use a GPREL reloc. If i can not be addressed
554 off the GP register, the following instruction sequence will be used:
557 In this case the first instruction will have a HI16 reloc, and the
558 second reloc will have a LO16 reloc. Both relocs will be against
561 The issue here is that we may not know whether i is GP addressable
562 until after we see the instruction that uses it. Therefore, we
563 want to be able to choose the final instruction sequence only at
564 the end of the assembly. This is similar to the way other
565 platforms choose the size of a PC relative instruction only at the
568 When generating position independent code we do not use GP
569 addressing in quite the same way, but the issue still arises as
570 external symbols and local symbols must be handled differently.
572 We handle these issues by actually generating both possible
573 instruction sequences. The longer one is put in a frag_var with
574 type rs_machine_dependent. We encode what to do with the frag in
575 the subtype field. We encode (1) the number of existing bytes to
576 replace, (2) the number of new bytes to use, (3) the offset from
577 the start of the existing bytes to the first reloc we must generate
578 (that is, the offset is applied from the start of the existing
579 bytes after they are replaced by the new bytes, if any), (4) the
580 offset from the start of the existing bytes to the second reloc,
581 (5) whether a third reloc is needed (the third reloc is always four
582 bytes after the second reloc), and (6) whether to warn if this
583 variant is used (this is sometimes needed if .set nomacro or .set
584 noat is in effect). All these numbers are reasonably small.
586 Generating two instruction sequences must be handled carefully to
587 ensure that delay slots are handled correctly. Fortunately, there
588 are a limited number of cases. When the second instruction
589 sequence is generated, append_insn is directed to maintain the
590 existing delay slot information, so it continues to apply to any
591 code after the second instruction sequence. This means that the
592 second instruction sequence must not impose any requirements not
593 required by the first instruction sequence.
595 These variant frags are then handled in functions called by the
596 machine independent code. md_estimate_size_before_relax returns
597 the final size of the frag. md_convert_frag sets up the final form
598 of the frag. tc_gen_reloc adjust the first reloc and adds a second
600 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
604 | (((reloc1) + 64) << 9) \
605 | (((reloc2) + 64) << 2) \
606 | ((reloc3) ? (1 << 1) : 0) \
608 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
609 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
610 #define RELAX_RELOC1(i) ((valueT) (((i) >> 9) & 0x7f) - 64)
611 #define RELAX_RELOC2(i) ((valueT) (((i) >> 2) & 0x7f) - 64)
612 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
613 #define RELAX_WARN(i) ((i) & 1)
615 /* For mips16 code, we use an entirely different form of relaxation.
616 mips16 supports two versions of most instructions which take
617 immediate values: a small one which takes some small value, and a
618 larger one which takes a 16 bit value. Since branches also follow
619 this pattern, relaxing these values is required.
621 We can assemble both mips16 and normal MIPS code in a single
622 object. Therefore, we need to support this type of relaxation at
623 the same time that we support the relaxation described above. We
624 use the high bit of the subtype field to distinguish these cases.
626 The information we store for this type of relaxation is the
627 argument code found in the opcode file for this relocation, whether
628 the user explicitly requested a small or extended form, and whether
629 the relocation is in a jump or jal delay slot. That tells us the
630 size of the value, and how it should be stored. We also store
631 whether the fragment is considered to be extended or not. We also
632 store whether this is known to be a branch to a different section,
633 whether we have tried to relax this frag yet, and whether we have
634 ever extended a PC relative fragment because of a shift count. */
635 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
638 | ((small) ? 0x100 : 0) \
639 | ((ext) ? 0x200 : 0) \
640 | ((dslot) ? 0x400 : 0) \
641 | ((jal_dslot) ? 0x800 : 0))
642 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
643 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
644 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
645 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
646 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
647 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
648 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
649 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
650 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
651 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
652 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
653 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
655 /* Prototypes for static functions. */
658 #define internalError() \
659 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
661 #define internalError() as_fatal (_("MIPS internal Error"));
664 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
666 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
667 unsigned int reg
, enum mips_regclass
class));
668 static int reg_needs_delay
PARAMS ((unsigned int));
669 static void mips16_mark_labels
PARAMS ((void));
670 static void append_insn
PARAMS ((char *place
,
671 struct mips_cl_insn
* ip
,
673 bfd_reloc_code_real_type
*r
,
675 static void mips_no_prev_insn
PARAMS ((int));
676 static void mips_emit_delays
PARAMS ((boolean
));
678 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
679 const char *name
, const char *fmt
,
682 static void macro_build ();
684 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
685 const char *, const char *,
687 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
688 expressionS
* ep
, int regnum
));
689 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
690 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
692 static void load_register
PARAMS ((int *, int, expressionS
*, int));
693 static void load_address
PARAMS ((int *, int, expressionS
*, int, int *));
694 static void move_register
PARAMS ((int *, int, int));
695 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
696 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
697 #ifdef LOSING_COMPILER
698 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
700 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
701 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
702 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
703 boolean
, boolean
, unsigned long *,
704 boolean
*, unsigned short *));
705 static int my_getSmallParser
PARAMS ((char **, unsigned int *, int *));
706 static int my_getSmallExpression
PARAMS ((expressionS
*, char *));
707 static void my_getExpression
PARAMS ((expressionS
*, char *));
709 static int support_64bit_objects
PARAMS((void));
711 static symbolS
*get_symbol
PARAMS ((void));
712 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
713 static void s_align
PARAMS ((int));
714 static void s_change_sec
PARAMS ((int));
715 static void s_cons
PARAMS ((int));
716 static void s_float_cons
PARAMS ((int));
717 static void s_mips_globl
PARAMS ((int));
718 static void s_option
PARAMS ((int));
719 static void s_mipsset
PARAMS ((int));
720 static void s_abicalls
PARAMS ((int));
721 static void s_cpload
PARAMS ((int));
722 static void s_cpsetup
PARAMS ((int));
723 static void s_cplocal
PARAMS ((int));
724 static void s_cprestore
PARAMS ((int));
725 static void s_cpreturn
PARAMS ((int));
726 static void s_gpvalue
PARAMS ((int));
727 static void s_gpword
PARAMS ((int));
728 static void s_cpadd
PARAMS ((int));
729 static void s_insn
PARAMS ((int));
730 static void md_obj_begin
PARAMS ((void));
731 static void md_obj_end
PARAMS ((void));
732 static long get_number
PARAMS ((void));
733 static void s_mips_ent
PARAMS ((int));
734 static void s_mips_end
PARAMS ((int));
735 static void s_mips_frame
PARAMS ((int));
736 static void s_mips_mask
PARAMS ((int));
737 static void s_mips_stab
PARAMS ((int));
738 static void s_mips_weakext
PARAMS ((int));
739 static void s_file
PARAMS ((int));
740 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
741 static const char *mips_isa_to_str
PARAMS ((int));
742 static const char *mips_cpu_to_str
PARAMS ((int));
743 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
744 static void show
PARAMS ((FILE *, char *, int *, int *));
746 static int mips_need_elf_addend_fixup
PARAMS ((fixS
*));
749 /* Return values of my_getSmallExpression(). */
756 /* Direct relocation creation by %percent_op(). */
775 /* Table and functions used to map between CPU/ISA names, and
776 ISA levels, and CPU numbers. */
780 const char *name
; /* CPU or ISA name. */
781 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
782 int isa
; /* ISA level. */
783 int cpu
; /* CPU number (default CPU if ISA). */
786 static const struct mips_cpu_info
*mips_cpu_info_from_name
PARAMS ((const char *));
787 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
788 static const struct mips_cpu_info
*mips_cpu_info_from_cpu
PARAMS ((int));
792 The following pseudo-ops from the Kane and Heinrich MIPS book
793 should be defined here, but are currently unsupported: .alias,
794 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
796 The following pseudo-ops from the Kane and Heinrich MIPS book are
797 specific to the type of debugging information being generated, and
798 should be defined by the object format: .aent, .begin, .bend,
799 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
802 The following pseudo-ops from the Kane and Heinrich MIPS book are
803 not MIPS CPU specific, but are also not specific to the object file
804 format. This file is probably the best place to define them, but
805 they are not currently supported: .asm0, .endr, .lab, .repeat,
808 static const pseudo_typeS mips_pseudo_table
[] =
810 /* MIPS specific pseudo-ops. */
811 {"option", s_option
, 0},
812 {"set", s_mipsset
, 0},
813 {"rdata", s_change_sec
, 'r'},
814 {"sdata", s_change_sec
, 's'},
815 {"livereg", s_ignore
, 0},
816 {"abicalls", s_abicalls
, 0},
817 {"cpload", s_cpload
, 0},
818 {"cpsetup", s_cpsetup
, 0},
819 {"cplocal", s_cplocal
, 0},
820 {"cprestore", s_cprestore
, 0},
821 {"cpreturn", s_cpreturn
, 0},
822 {"gpvalue", s_gpvalue
, 0},
823 {"gpword", s_gpword
, 0},
824 {"cpadd", s_cpadd
, 0},
827 /* Relatively generic pseudo-ops that happen to be used on MIPS
829 {"asciiz", stringer
, 1},
830 {"bss", s_change_sec
, 'b'},
833 {"dword", s_cons
, 3},
834 {"weakext", s_mips_weakext
, 0},
836 /* These pseudo-ops are defined in read.c, but must be overridden
837 here for one reason or another. */
838 {"align", s_align
, 0},
840 {"data", s_change_sec
, 'd'},
841 {"double", s_float_cons
, 'd'},
842 {"float", s_float_cons
, 'f'},
843 {"globl", s_mips_globl
, 0},
844 {"global", s_mips_globl
, 0},
845 {"hword", s_cons
, 1},
850 {"short", s_cons
, 1},
851 {"single", s_float_cons
, 'f'},
852 {"stabn", s_mips_stab
, 'n'},
853 {"text", s_change_sec
, 't'},
856 #ifdef MIPS_STABS_ELF
857 { "extern", ecoff_directive_extern
, 0},
863 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
865 /* These pseudo-ops should be defined by the object file format.
866 However, a.out doesn't support them, so we have versions here. */
867 {"aent", s_mips_ent
, 1},
868 {"bgnb", s_ignore
, 0},
869 {"end", s_mips_end
, 0},
870 {"endb", s_ignore
, 0},
871 {"ent", s_mips_ent
, 0},
873 {"fmask", s_mips_mask
, 'F'},
874 {"frame", s_mips_frame
, 0},
875 {"loc", s_ignore
, 0},
876 {"mask", s_mips_mask
, 'R'},
877 {"verstamp", s_ignore
, 0},
881 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
886 pop_insert (mips_pseudo_table
);
887 if (! ECOFF_DEBUGGING
)
888 pop_insert (mips_nonecoff_pseudo_table
);
891 /* Symbols labelling the current insn. */
893 struct insn_label_list
895 struct insn_label_list
*next
;
899 static struct insn_label_list
*insn_labels
;
900 static struct insn_label_list
*free_insn_labels
;
902 static void mips_clear_insn_labels
PARAMS ((void));
905 mips_clear_insn_labels ()
907 register struct insn_label_list
**pl
;
909 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
915 static char *expr_end
;
917 /* Expressions which appear in instructions. These are set by
920 static expressionS imm_expr
;
921 static expressionS offset_expr
;
923 /* Relocs associated with imm_expr and offset_expr. */
925 static bfd_reloc_code_real_type imm_reloc
[3]
926 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
927 static bfd_reloc_code_real_type offset_reloc
[3]
928 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
930 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
932 static boolean imm_unmatched_hi
;
934 /* These are set by mips16_ip if an explicit extension is used. */
936 static boolean mips16_small
, mips16_ext
;
938 #ifdef MIPS_STABS_ELF
939 /* The pdr segment for per procedure frame/regmask info */
945 mips_isa_to_str (isa
)
948 const struct mips_cpu_info
*ci
;
951 ci
= mips_cpu_info_from_isa (isa
);
955 sprintf (s
, "ISA#%d", isa
);
960 mips_cpu_to_str (cpu
)
963 const struct mips_cpu_info
*ci
;
966 ci
= mips_cpu_info_from_cpu (cpu
);
970 sprintf (s
, "CPU#%d", cpu
);
974 /* The default target format to use. */
977 mips_target_format ()
979 switch (OUTPUT_FLAVOR
)
981 case bfd_target_aout_flavour
:
982 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
983 case bfd_target_ecoff_flavour
:
984 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
985 case bfd_target_coff_flavour
:
987 case bfd_target_elf_flavour
:
989 /* This is traditional mips */
990 return (target_big_endian
991 ? (HAVE_64BIT_OBJECTS
? "elf64-tradbigmips"
992 : "elf32-tradbigmips")
993 : (HAVE_64BIT_OBJECTS
? "elf64-tradlittlemips"
994 : "elf32-tradlittlemips"));
996 return (target_big_endian
997 ? (HAVE_64BIT_OBJECTS
? "elf64-bigmips" : "elf32-bigmips")
998 : (HAVE_64BIT_OBJECTS
? "elf64-littlemips"
999 : "elf32-littlemips"));
1007 /* This function is called once, at assembler startup time. It should
1008 set up all the tables, etc. that the MD part of the assembler will need. */
1013 register const char *retval
= NULL
;
1018 int mips_isa_from_cpu
;
1019 int target_cpu_had_mips16
= 0;
1020 const struct mips_cpu_info
*ci
;
1022 /* GP relative stuff not working for PE */
1023 if (strncmp (TARGET_OS
, "pe", 2) == 0
1024 && g_switch_value
!= 0)
1027 as_bad (_("-G not supported in this configuration."));
1032 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
1034 a
= xmalloc (sizeof TARGET_CPU
);
1035 strcpy (a
, TARGET_CPU
);
1036 a
[(sizeof TARGET_CPU
) - 3] = '\0';
1040 if (strncmp (cpu
, "mips16", sizeof "mips16" - 1) == 0)
1042 target_cpu_had_mips16
= 1;
1043 cpu
+= sizeof "mips16" - 1;
1046 if (mips_opts
.mips16
< 0)
1047 mips_opts
.mips16
= target_cpu_had_mips16
;
1049 /* Backward compatibility for historic -mcpu= option. Check for
1050 incompatible options, warn if -mcpu is used. */
1051 if (mips_cpu
!= CPU_UNKNOWN
1052 && mips_arch
!= CPU_UNKNOWN
1053 && mips_cpu
!= mips_arch
)
1055 as_fatal (_("The -mcpu option can't be used together with -march. "
1056 "Use -mtune instead of -mcpu."));
1059 if (mips_cpu
!= CPU_UNKNOWN
1060 && mips_tune
!= CPU_UNKNOWN
1061 && mips_cpu
!= mips_tune
)
1063 as_fatal (_("The -mcpu option can't be used together with -mtune. "
1064 "Use -march instead of -mcpu."));
1068 /* For backward compatibility, let -mipsN set various defaults. */
1069 /* This code should go away, to be replaced with something rather more
1070 draconian. Until GCC 3.1 has been released for some reasonable
1071 amount of time, however, we need to support this. */
1072 if (mips_opts
.isa
!= ISA_UNKNOWN
)
1074 /* Translate -mipsN to the appropriate settings of file_mips_gp32
1075 and file_mips_fp32. Tag binaries as using the mipsN ISA. */
1076 if (file_mips_gp32
< 0)
1078 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1083 if (file_mips_fp32
< 0)
1085 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
1091 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1092 assert (ci
!= NULL
);
1093 /* -mipsN has higher priority than -mcpu but lower than -march. */
1094 if (mips_arch
== CPU_UNKNOWN
)
1095 mips_arch
= ci
->cpu
;
1097 /* Default mips_abi. */
1098 if (mips_opts
.abi
== NO_ABI
)
1100 if (mips_opts
.isa
== ISA_MIPS1
|| mips_opts
.isa
== ISA_MIPS2
)
1101 mips_opts
.abi
= O32_ABI
;
1102 else if (mips_opts
.isa
== ISA_MIPS3
|| mips_opts
.isa
== ISA_MIPS4
)
1103 mips_opts
.abi
= O64_ABI
;
1107 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1109 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1110 assert (ci
!= NULL
);
1111 mips_arch
= ci
->cpu
;
1112 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1113 "-mtune instead."));
1116 /* Set tune from -mcpu, not from -mipsN. */
1117 if (mips_tune
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1119 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1120 assert (ci
!= NULL
);
1121 mips_tune
= ci
->cpu
;
1124 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1125 specified on the command line, or some other value if one was.
1126 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1127 the command line, or will be set otherwise if one was. */
1129 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1130 /* Handled above. */;
1132 if (mips_arch
== CPU_UNKNOWN
&& mips_cpu
!= CPU_UNKNOWN
)
1134 ci
= mips_cpu_info_from_cpu (mips_cpu
);
1135 assert (ci
!= NULL
);
1136 mips_arch
= ci
->cpu
;
1137 as_warn (_("The -mcpu option is deprecated. Please use -march and "
1138 "-mtune instead."));
1141 /* At this point, mips_arch will either be CPU_UNKNOWN if no ARCH was
1142 specified on the command line, or some other value if one was.
1143 Similarly, mips_opts.isa will be ISA_UNKNOWN if not specified on
1144 the command line, or will be set otherwise if one was. */
1146 if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1148 /* We have to check if the isa is the default isa of arch. Otherwise
1149 we'll get invalid object file headers. */
1150 ci
= mips_cpu_info_from_cpu (mips_arch
);
1151 assert (ci
!= NULL
);
1152 if (mips_opts
.isa
!= ci
->isa
)
1154 /* This really should be an error instead of a warning, but old
1155 compilers only have -mcpu which sets both arch and tune. For
1156 now, we discard arch and preserve tune. */
1157 as_warn (_("The -march option is incompatible to -mipsN and "
1158 "therefore ignored."));
1159 if (mips_tune
== CPU_UNKNOWN
)
1160 mips_tune
= mips_arch
;
1161 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1162 assert (ci
!= NULL
);
1163 mips_arch
= ci
->cpu
;
1167 else if (mips_arch
!= CPU_UNKNOWN
&& mips_opts
.isa
== ISA_UNKNOWN
)
1169 /* We have ARCH, we need ISA. */
1170 ci
= mips_cpu_info_from_cpu (mips_arch
);
1171 assert (ci
!= NULL
);
1172 mips_opts
.isa
= ci
->isa
;
1174 else if (mips_arch
== CPU_UNKNOWN
&& mips_opts
.isa
!= ISA_UNKNOWN
)
1176 /* We have ISA, we need default ARCH. */
1177 ci
= mips_cpu_info_from_isa (mips_opts
.isa
);
1178 assert (ci
!= NULL
);
1179 mips_arch
= ci
->cpu
;
1183 /* We need to set both ISA and ARCH from target cpu. */
1184 ci
= mips_cpu_info_from_name (cpu
);
1186 ci
= mips_cpu_info_from_cpu (CPU_R3000
);
1187 assert (ci
!= NULL
);
1188 mips_opts
.isa
= ci
->isa
;
1189 mips_arch
= ci
->cpu
;
1192 if (mips_tune
== CPU_UNKNOWN
)
1193 mips_tune
= mips_arch
;
1195 ci
= mips_cpu_info_from_cpu (mips_arch
);
1196 assert (ci
!= NULL
);
1197 mips_isa_from_cpu
= ci
->isa
;
1199 /* End of TARGET_CPU processing, get rid of malloced memory
1208 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
1209 as_bad (_("trap exception not supported at ISA 1"));
1211 /* Set the EABI kind based on the ISA before the user gets
1212 to change the ISA with directives. This isn't really
1213 the best, but then neither is basing the abi on the isa. */
1214 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1215 && mips_opts
.abi
== EABI_ABI
)
1218 /* If they asked for mips1 or mips2 and a cpu that is
1219 mips3 or greater, then mark the object file 32BITMODE. */
1220 if (mips_isa_from_cpu
!= ISA_UNKNOWN
1221 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1222 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1225 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_arch
))
1226 as_warn (_("Could not set architecture and machine"));
1228 if (file_mips_gp32
< 0)
1230 if (file_mips_fp32
< 0)
1233 file_mips_isa
= mips_opts
.isa
;
1234 file_mips_abi
= mips_opts
.abi
;
1235 mips_opts
.gp32
= file_mips_gp32
;
1236 mips_opts
.fp32
= file_mips_fp32
;
1238 op_hash
= hash_new ();
1240 for (i
= 0; i
< NUMOPCODES
;)
1242 const char *name
= mips_opcodes
[i
].name
;
1244 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1247 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1248 mips_opcodes
[i
].name
, retval
);
1249 /* Probably a memory allocation problem? Give up now. */
1250 as_fatal (_("Broken assembler. No assembly attempted."));
1254 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1256 if (!validate_mips_insn (&mips_opcodes
[i
]))
1261 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1264 mips16_op_hash
= hash_new ();
1267 while (i
< bfd_mips16_num_opcodes
)
1269 const char *name
= mips16_opcodes
[i
].name
;
1271 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1273 as_fatal (_("internal: can't hash `%s': %s"),
1274 mips16_opcodes
[i
].name
, retval
);
1277 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1278 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1279 != mips16_opcodes
[i
].match
))
1281 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1282 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1287 while (i
< bfd_mips16_num_opcodes
1288 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1292 as_fatal (_("Broken assembler. No assembly attempted."));
1294 /* We add all the general register names to the symbol table. This
1295 helps us detect invalid uses of them. */
1296 for (i
= 0; i
< 32; i
++)
1300 sprintf (buf
, "$%d", i
);
1301 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1302 &zero_address_frag
));
1304 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1305 &zero_address_frag
));
1306 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1307 &zero_address_frag
));
1308 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1309 &zero_address_frag
));
1310 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1311 &zero_address_frag
));
1312 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1313 &zero_address_frag
));
1314 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1315 &zero_address_frag
));
1316 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1317 &zero_address_frag
));
1319 mips_no_prev_insn (false);
1322 mips_cprmask
[0] = 0;
1323 mips_cprmask
[1] = 0;
1324 mips_cprmask
[2] = 0;
1325 mips_cprmask
[3] = 0;
1327 /* set the default alignment for the text section (2**2) */
1328 record_alignment (text_section
, 2);
1330 if (USE_GLOBAL_POINTER_OPT
)
1331 bfd_set_gp_size (stdoutput
, g_switch_value
);
1333 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1335 /* On a native system, sections must be aligned to 16 byte
1336 boundaries. When configured for an embedded ELF target, we
1338 if (strcmp (TARGET_OS
, "elf") != 0)
1340 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1341 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1342 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1345 /* Create a .reginfo section for register masks and a .mdebug
1346 section for debugging information. */
1354 subseg
= now_subseg
;
1356 /* The ABI says this section should be loaded so that the
1357 running program can access it. However, we don't load it
1358 if we are configured for an embedded target */
1359 flags
= SEC_READONLY
| SEC_DATA
;
1360 if (strcmp (TARGET_OS
, "elf") != 0)
1361 flags
|= SEC_ALLOC
| SEC_LOAD
;
1365 sec
= subseg_new (".reginfo", (subsegT
) 0);
1367 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1368 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1371 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1376 /* The 64-bit ABI uses a .MIPS.options section rather than
1377 .reginfo section. */
1378 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1379 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1380 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1383 /* Set up the option header. */
1385 Elf_Internal_Options opthdr
;
1388 opthdr
.kind
= ODK_REGINFO
;
1389 opthdr
.size
= (sizeof (Elf_External_Options
)
1390 + sizeof (Elf64_External_RegInfo
));
1393 f
= frag_more (sizeof (Elf_External_Options
));
1394 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1395 (Elf_External_Options
*) f
);
1397 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1402 if (ECOFF_DEBUGGING
)
1404 sec
= subseg_new (".mdebug", (subsegT
) 0);
1405 (void) bfd_set_section_flags (stdoutput
, sec
,
1406 SEC_HAS_CONTENTS
| SEC_READONLY
);
1407 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1410 #ifdef MIPS_STABS_ELF
1411 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1412 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1413 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1414 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1417 subseg_set (seg
, subseg
);
1421 if (! ECOFF_DEBUGGING
)
1428 if (! ECOFF_DEBUGGING
)
1436 struct mips_cl_insn insn
;
1437 bfd_reloc_code_real_type unused_reloc
[3]
1438 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1440 imm_expr
.X_op
= O_absent
;
1441 imm_unmatched_hi
= false;
1442 offset_expr
.X_op
= O_absent
;
1443 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1444 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1445 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1446 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1447 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1448 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1450 if (mips_opts
.mips16
)
1451 mips16_ip (str
, &insn
);
1454 mips_ip (str
, &insn
);
1455 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1456 str
, insn
.insn_opcode
));
1461 as_bad ("%s `%s'", insn_error
, str
);
1465 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1467 if (mips_opts
.mips16
)
1468 mips16_macro (&insn
);
1474 if (imm_expr
.X_op
!= O_absent
)
1475 append_insn (NULL
, &insn
, &imm_expr
, imm_reloc
, imm_unmatched_hi
);
1476 else if (offset_expr
.X_op
!= O_absent
)
1477 append_insn (NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1479 append_insn (NULL
, &insn
, NULL
, unused_reloc
, false);
1483 /* See whether instruction IP reads register REG. CLASS is the type
1487 insn_uses_reg (ip
, reg
, class)
1488 struct mips_cl_insn
*ip
;
1490 enum mips_regclass
class;
1492 if (class == MIPS16_REG
)
1494 assert (mips_opts
.mips16
);
1495 reg
= mips16_to_32_reg_map
[reg
];
1496 class = MIPS_GR_REG
;
1499 /* Don't report on general register 0, since it never changes. */
1500 if (class == MIPS_GR_REG
&& reg
== 0)
1503 if (class == MIPS_FP_REG
)
1505 assert (! mips_opts
.mips16
);
1506 /* If we are called with either $f0 or $f1, we must check $f0.
1507 This is not optimal, because it will introduce an unnecessary
1508 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1509 need to distinguish reading both $f0 and $f1 or just one of
1510 them. Note that we don't have to check the other way,
1511 because there is no instruction that sets both $f0 and $f1
1512 and requires a delay. */
1513 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1514 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1515 == (reg
&~ (unsigned) 1)))
1517 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1518 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1519 == (reg
&~ (unsigned) 1)))
1522 else if (! mips_opts
.mips16
)
1524 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1525 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1527 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1528 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1533 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1534 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1535 & MIPS16OP_MASK_RX
)]
1538 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1539 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1540 & MIPS16OP_MASK_RY
)]
1543 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1544 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1545 & MIPS16OP_MASK_MOVE32Z
)]
1548 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1550 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1552 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1554 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1555 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1556 & MIPS16OP_MASK_REGR32
) == reg
)
1563 /* This function returns true if modifying a register requires a
1567 reg_needs_delay (reg
)
1570 unsigned long prev_pinfo
;
1572 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1573 if (! mips_opts
.noreorder
1574 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1575 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1576 || (! gpr_interlocks
1577 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1579 /* A load from a coprocessor or from memory. All load
1580 delays delay the use of general register rt for one
1581 instruction on the r3000. The r6000 and r4000 use
1583 /* Itbl support may require additional care here. */
1584 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1585 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1592 /* Mark instruction labels in mips16 mode. This permits the linker to
1593 handle them specially, such as generating jalx instructions when
1594 needed. We also make them odd for the duration of the assembly, in
1595 order to generate the right sort of code. We will make them even
1596 in the adjust_symtab routine, while leaving them marked. This is
1597 convenient for the debugger and the disassembler. The linker knows
1598 to make them odd again. */
1601 mips16_mark_labels ()
1603 if (mips_opts
.mips16
)
1605 struct insn_label_list
*l
;
1608 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1611 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1612 S_SET_OTHER (l
->label
, STO_MIPS16
);
1614 val
= S_GET_VALUE (l
->label
);
1616 S_SET_VALUE (l
->label
, val
+ 1);
1621 /* Output an instruction. PLACE is where to put the instruction; if
1622 it is NULL, this uses frag_more to get room. IP is the instruction
1623 information. ADDRESS_EXPR is an operand of the instruction to be
1624 used with RELOC_TYPE. */
1627 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1629 struct mips_cl_insn
*ip
;
1630 expressionS
*address_expr
;
1631 bfd_reloc_code_real_type
*reloc_type
;
1632 boolean unmatched_hi
;
1634 register unsigned long prev_pinfo
, pinfo
;
1639 /* Mark instruction labels in mips16 mode. */
1640 if (mips_opts
.mips16
)
1641 mips16_mark_labels ();
1643 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1644 pinfo
= ip
->insn_mo
->pinfo
;
1646 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1650 /* If the previous insn required any delay slots, see if we need
1651 to insert a NOP or two. There are eight kinds of possible
1652 hazards, of which an instruction can have at most one type.
1653 (1) a load from memory delay
1654 (2) a load from a coprocessor delay
1655 (3) an unconditional branch delay
1656 (4) a conditional branch delay
1657 (5) a move to coprocessor register delay
1658 (6) a load coprocessor register from memory delay
1659 (7) a coprocessor condition code delay
1660 (8) a HI/LO special register delay
1662 There are a lot of optimizations we could do that we don't.
1663 In particular, we do not, in general, reorder instructions.
1664 If you use gcc with optimization, it will reorder
1665 instructions and generally do much more optimization then we
1666 do here; repeating all that work in the assembler would only
1667 benefit hand written assembly code, and does not seem worth
1670 /* This is how a NOP is emitted. */
1671 #define emit_nop() \
1673 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1674 : md_number_to_chars (frag_more (4), 0, 4))
1676 /* The previous insn might require a delay slot, depending upon
1677 the contents of the current insn. */
1678 if (! mips_opts
.mips16
1679 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1680 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1681 && ! cop_interlocks
)
1682 || (! gpr_interlocks
1683 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1685 /* A load from a coprocessor or from memory. All load
1686 delays delay the use of general register rt for one
1687 instruction on the r3000. The r6000 and r4000 use
1689 /* Itbl support may require additional care here. */
1690 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1691 if (mips_optimize
== 0
1692 || insn_uses_reg (ip
,
1693 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1698 else if (! mips_opts
.mips16
1699 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1700 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1701 && ! cop_interlocks
)
1702 || (mips_opts
.isa
== ISA_MIPS1
1703 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1705 /* A generic coprocessor delay. The previous instruction
1706 modified a coprocessor general or control register. If
1707 it modified a control register, we need to avoid any
1708 coprocessor instruction (this is probably not always
1709 required, but it sometimes is). If it modified a general
1710 register, we avoid using that register.
1712 On the r6000 and r4000 loading a coprocessor register
1713 from memory is interlocked, and does not require a delay.
1715 This case is not handled very well. There is no special
1716 knowledge of CP0 handling, and the coprocessors other
1717 than the floating point unit are not distinguished at
1719 /* Itbl support may require additional care here. FIXME!
1720 Need to modify this to include knowledge about
1721 user specified delays! */
1722 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1724 if (mips_optimize
== 0
1725 || insn_uses_reg (ip
,
1726 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1731 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1733 if (mips_optimize
== 0
1734 || insn_uses_reg (ip
,
1735 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1742 /* We don't know exactly what the previous instruction
1743 does. If the current instruction uses a coprocessor
1744 register, we must insert a NOP. If previous
1745 instruction may set the condition codes, and the
1746 current instruction uses them, we must insert two
1748 /* Itbl support may require additional care here. */
1749 if (mips_optimize
== 0
1750 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1751 && (pinfo
& INSN_READ_COND_CODE
)))
1753 else if (pinfo
& INSN_COP
)
1757 else if (! mips_opts
.mips16
1758 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1759 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1760 && ! cop_interlocks
)
1762 /* The previous instruction sets the coprocessor condition
1763 codes, but does not require a general coprocessor delay
1764 (this means it is a floating point comparison
1765 instruction). If this instruction uses the condition
1766 codes, we need to insert a single NOP. */
1767 /* Itbl support may require additional care here. */
1768 if (mips_optimize
== 0
1769 || (pinfo
& INSN_READ_COND_CODE
))
1773 /* If we're fixing up mfhi/mflo for the r7000 and the
1774 previous insn was an mfhi/mflo and the current insn
1775 reads the register that the mfhi/mflo wrote to, then
1778 else if (mips_7000_hilo_fix
1779 && MF_HILO_INSN (prev_pinfo
)
1780 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1787 /* If we're fixing up mfhi/mflo for the r7000 and the
1788 2nd previous insn was an mfhi/mflo and the current insn
1789 reads the register that the mfhi/mflo wrote to, then
1792 else if (mips_7000_hilo_fix
1793 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1794 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1802 else if (prev_pinfo
& INSN_READ_LO
)
1804 /* The previous instruction reads the LO register; if the
1805 current instruction writes to the LO register, we must
1806 insert two NOPS. Some newer processors have interlocks.
1807 Also the tx39's multiply instructions can be exectuted
1808 immediatly after a read from HI/LO (without the delay),
1809 though the tx39's divide insns still do require the
1811 if (! (hilo_interlocks
1812 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1813 && (mips_optimize
== 0
1814 || (pinfo
& INSN_WRITE_LO
)))
1816 /* Most mips16 branch insns don't have a delay slot.
1817 If a read from LO is immediately followed by a branch
1818 to a write to LO we have a read followed by a write
1819 less than 2 insns away. We assume the target of
1820 a branch might be a write to LO, and insert a nop
1821 between a read and an immediately following branch. */
1822 else if (mips_opts
.mips16
1823 && (mips_optimize
== 0
1824 || (pinfo
& MIPS16_INSN_BRANCH
)))
1827 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1829 /* The previous instruction reads the HI register; if the
1830 current instruction writes to the HI register, we must
1831 insert a NOP. Some newer processors have interlocks.
1832 Also the note tx39's multiply above. */
1833 if (! (hilo_interlocks
1834 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1835 && (mips_optimize
== 0
1836 || (pinfo
& INSN_WRITE_HI
)))
1838 /* Most mips16 branch insns don't have a delay slot.
1839 If a read from HI is immediately followed by a branch
1840 to a write to HI we have a read followed by a write
1841 less than 2 insns away. We assume the target of
1842 a branch might be a write to HI, and insert a nop
1843 between a read and an immediately following branch. */
1844 else if (mips_opts
.mips16
1845 && (mips_optimize
== 0
1846 || (pinfo
& MIPS16_INSN_BRANCH
)))
1850 /* If the previous instruction was in a noreorder section, then
1851 we don't want to insert the nop after all. */
1852 /* Itbl support may require additional care here. */
1853 if (prev_insn_unreordered
)
1856 /* There are two cases which require two intervening
1857 instructions: 1) setting the condition codes using a move to
1858 coprocessor instruction which requires a general coprocessor
1859 delay and then reading the condition codes 2) reading the HI
1860 or LO register and then writing to it (except on processors
1861 which have interlocks). If we are not already emitting a NOP
1862 instruction, we must check for these cases compared to the
1863 instruction previous to the previous instruction. */
1864 if ((! mips_opts
.mips16
1865 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1866 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1867 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1868 && (pinfo
& INSN_READ_COND_CODE
)
1869 && ! cop_interlocks
)
1870 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1871 && (pinfo
& INSN_WRITE_LO
)
1872 && ! (hilo_interlocks
1873 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1874 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1875 && (pinfo
& INSN_WRITE_HI
)
1876 && ! (hilo_interlocks
1877 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1882 if (prev_prev_insn_unreordered
)
1885 if (prev_prev_nop
&& nops
== 0)
1888 /* If we are being given a nop instruction, don't bother with
1889 one of the nops we would otherwise output. This will only
1890 happen when a nop instruction is used with mips_optimize set
1893 && ! mips_opts
.noreorder
1894 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1897 /* Now emit the right number of NOP instructions. */
1898 if (nops
> 0 && ! mips_opts
.noreorder
)
1901 unsigned long old_frag_offset
;
1903 struct insn_label_list
*l
;
1905 old_frag
= frag_now
;
1906 old_frag_offset
= frag_now_fix ();
1908 for (i
= 0; i
< nops
; i
++)
1913 listing_prev_line ();
1914 /* We may be at the start of a variant frag. In case we
1915 are, make sure there is enough space for the frag
1916 after the frags created by listing_prev_line. The
1917 argument to frag_grow here must be at least as large
1918 as the argument to all other calls to frag_grow in
1919 this file. We don't have to worry about being in the
1920 middle of a variant frag, because the variants insert
1921 all needed nop instructions themselves. */
1925 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1929 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1930 symbol_set_frag (l
->label
, frag_now
);
1931 val
= (valueT
) frag_now_fix ();
1932 /* mips16 text labels are stored as odd. */
1933 if (mips_opts
.mips16
)
1935 S_SET_VALUE (l
->label
, val
);
1938 #ifndef NO_ECOFF_DEBUGGING
1939 if (ECOFF_DEBUGGING
)
1940 ecoff_fix_loc (old_frag
, old_frag_offset
);
1943 else if (prev_nop_frag
!= NULL
)
1945 /* We have a frag holding nops we may be able to remove. If
1946 we don't need any nops, we can decrease the size of
1947 prev_nop_frag by the size of one instruction. If we do
1948 need some nops, we count them in prev_nops_required. */
1949 if (prev_nop_frag_since
== 0)
1953 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1954 --prev_nop_frag_holds
;
1957 prev_nop_frag_required
+= nops
;
1961 if (prev_prev_nop
== 0)
1963 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1964 --prev_nop_frag_holds
;
1967 ++prev_nop_frag_required
;
1970 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1971 prev_nop_frag
= NULL
;
1973 ++prev_nop_frag_since
;
1975 /* Sanity check: by the time we reach the second instruction
1976 after prev_nop_frag, we should have used up all the nops
1977 one way or another. */
1978 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1982 if (*reloc_type
> BFD_RELOC_UNUSED
)
1984 /* We need to set up a variant frag. */
1985 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1986 f
= frag_var (rs_machine_dependent
, 4, 0,
1987 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
1988 mips16_small
, mips16_ext
,
1990 & INSN_UNCOND_BRANCH_DELAY
),
1991 (*prev_insn_reloc_type
1992 == BFD_RELOC_MIPS16_JMP
)),
1993 make_expr_symbol (address_expr
), 0, NULL
);
1995 else if (place
!= NULL
)
1997 else if (mips_opts
.mips16
1999 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2001 /* Make sure there is enough room to swap this instruction with
2002 a following jump instruction. */
2008 if (mips_opts
.mips16
2009 && mips_opts
.noreorder
2010 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2011 as_warn (_("extended instruction in delay slot"));
2016 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2017 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2019 if (address_expr
->X_op
== O_constant
)
2023 switch (*reloc_type
)
2026 ip
->insn_opcode
|= address_expr
->X_add_number
;
2029 case BFD_RELOC_MIPS_HIGHEST
:
2030 tmp
= (address_expr
->X_add_number
+ 0x800080008000) >> 16;
2032 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2035 case BFD_RELOC_MIPS_HIGHER
:
2036 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2037 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2040 case BFD_RELOC_HI16_S
:
2041 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2045 case BFD_RELOC_HI16
:
2046 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2049 case BFD_RELOC_LO16
:
2050 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2053 case BFD_RELOC_MIPS_JMP
:
2054 if ((address_expr
->X_add_number
& 3) != 0)
2055 as_bad (_("jump to misaligned address (0x%lx)"),
2056 (unsigned long) address_expr
->X_add_number
);
2057 if (address_expr
->X_add_number
& ~0xfffffff
2058 || address_expr
->X_add_number
> 0x7fffffc)
2059 as_bad (_("jump address range overflow (0x%lx)"),
2060 (unsigned long) address_expr
->X_add_number
);
2061 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2064 case BFD_RELOC_MIPS16_JMP
:
2065 if ((address_expr
->X_add_number
& 3) != 0)
2066 as_bad (_("jump to misaligned address (0x%lx)"),
2067 (unsigned long) address_expr
->X_add_number
);
2068 if (address_expr
->X_add_number
& ~0xfffffff
2069 || address_expr
->X_add_number
> 0x7fffffc)
2070 as_bad (_("jump address range overflow (0x%lx)"),
2071 (unsigned long) address_expr
->X_add_number
);
2073 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2074 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2075 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2078 case BFD_RELOC_16_PCREL
:
2079 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2082 case BFD_RELOC_16_PCREL_S2
:
2092 /* Don't generate a reloc if we are writing into a variant frag. */
2095 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
2097 (*reloc_type
== BFD_RELOC_16_PCREL
2098 || *reloc_type
== BFD_RELOC_16_PCREL_S2
),
2101 /* These relocations can have an addend that won't fit in
2102 4 octets for 64bit assembly. */
2103 if (HAVE_64BIT_GPRS
&&
2104 (*reloc_type
== BFD_RELOC_16
2105 || *reloc_type
== BFD_RELOC_32
2106 || *reloc_type
== BFD_RELOC_MIPS_JMP
2107 || *reloc_type
== BFD_RELOC_HI16_S
2108 || *reloc_type
== BFD_RELOC_LO16
2109 || *reloc_type
== BFD_RELOC_GPREL16
2110 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2111 || *reloc_type
== BFD_RELOC_GPREL32
2112 || *reloc_type
== BFD_RELOC_64
2113 || *reloc_type
== BFD_RELOC_CTOR
2114 || *reloc_type
== BFD_RELOC_MIPS_SUB
2115 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2116 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2117 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2118 || *reloc_type
== BFD_RELOC_MIPS_REL16
2119 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2120 fixp
[0]->fx_no_overflow
= 1;
2124 struct mips_hi_fixup
*hi_fixup
;
2126 assert (*reloc_type
== BFD_RELOC_HI16_S
);
2127 hi_fixup
= ((struct mips_hi_fixup
*)
2128 xmalloc (sizeof (struct mips_hi_fixup
)));
2129 hi_fixup
->fixp
= fixp
[0];
2130 hi_fixup
->seg
= now_seg
;
2131 hi_fixup
->next
= mips_hi_fixup_list
;
2132 mips_hi_fixup_list
= hi_fixup
;
2135 if (reloc_type
[1] != BFD_RELOC_UNUSED
)
2137 /* FIXME: This symbol can be one of
2138 RSS_UNDEF, RSS_GP, RSS_GP0, RSS_LOC. */
2139 address_expr
->X_op
= O_absent
;
2140 address_expr
->X_add_symbol
= 0;
2141 address_expr
->X_add_number
= 0;
2143 fixp
[1] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2144 4, address_expr
, false,
2147 /* These relocations can have an addend that won't fit in
2148 4 octets for 64bit assembly. */
2149 if (HAVE_64BIT_GPRS
&&
2150 (*reloc_type
== BFD_RELOC_16
2151 || *reloc_type
== BFD_RELOC_32
2152 || *reloc_type
== BFD_RELOC_MIPS_JMP
2153 || *reloc_type
== BFD_RELOC_HI16_S
2154 || *reloc_type
== BFD_RELOC_LO16
2155 || *reloc_type
== BFD_RELOC_GPREL16
2156 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2157 || *reloc_type
== BFD_RELOC_GPREL32
2158 || *reloc_type
== BFD_RELOC_64
2159 || *reloc_type
== BFD_RELOC_CTOR
2160 || *reloc_type
== BFD_RELOC_MIPS_SUB
2161 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2162 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2163 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2164 || *reloc_type
== BFD_RELOC_MIPS_REL16
2165 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2166 fixp
[1]->fx_no_overflow
= 1;
2168 if (reloc_type
[2] != BFD_RELOC_UNUSED
)
2170 address_expr
->X_op
= O_absent
;
2171 address_expr
->X_add_symbol
= 0;
2172 address_expr
->X_add_number
= 0;
2174 fixp
[2] = fix_new_exp (frag_now
,
2175 f
- frag_now
->fr_literal
, 4,
2176 address_expr
, false,
2179 /* These relocations can have an addend that won't fit in
2180 4 octets for 64bit assembly. */
2181 if (HAVE_64BIT_GPRS
&&
2182 (*reloc_type
== BFD_RELOC_16
2183 || *reloc_type
== BFD_RELOC_32
2184 || *reloc_type
== BFD_RELOC_MIPS_JMP
2185 || *reloc_type
== BFD_RELOC_HI16_S
2186 || *reloc_type
== BFD_RELOC_LO16
2187 || *reloc_type
== BFD_RELOC_GPREL16
2188 || *reloc_type
== BFD_RELOC_MIPS_LITERAL
2189 || *reloc_type
== BFD_RELOC_GPREL32
2190 || *reloc_type
== BFD_RELOC_64
2191 || *reloc_type
== BFD_RELOC_CTOR
2192 || *reloc_type
== BFD_RELOC_MIPS_SUB
2193 || *reloc_type
== BFD_RELOC_MIPS_HIGHEST
2194 || *reloc_type
== BFD_RELOC_MIPS_HIGHER
2195 || *reloc_type
== BFD_RELOC_MIPS_SCN_DISP
2196 || *reloc_type
== BFD_RELOC_MIPS_REL16
2197 || *reloc_type
== BFD_RELOC_MIPS_RELGOT
))
2198 fixp
[2]->fx_no_overflow
= 1;
2205 if (! mips_opts
.mips16
)
2206 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2207 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2209 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2210 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2216 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2219 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2222 /* Update the register mask information. */
2223 if (! mips_opts
.mips16
)
2225 if (pinfo
& INSN_WRITE_GPR_D
)
2226 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2227 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2228 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2229 if (pinfo
& INSN_READ_GPR_S
)
2230 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2231 if (pinfo
& INSN_WRITE_GPR_31
)
2232 mips_gprmask
|= 1 << 31;
2233 if (pinfo
& INSN_WRITE_FPR_D
)
2234 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2235 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2236 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2237 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2238 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2239 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2240 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2241 if (pinfo
& INSN_COP
)
2243 /* We don't keep enough information to sort these cases out.
2244 The itbl support does keep this information however, although
2245 we currently don't support itbl fprmats as part of the cop
2246 instruction. May want to add this support in the future. */
2248 /* Never set the bit for $0, which is always zero. */
2249 mips_gprmask
&= ~1 << 0;
2253 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2254 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2255 & MIPS16OP_MASK_RX
);
2256 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2257 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2258 & MIPS16OP_MASK_RY
);
2259 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2260 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2261 & MIPS16OP_MASK_RZ
);
2262 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2263 mips_gprmask
|= 1 << TREG
;
2264 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2265 mips_gprmask
|= 1 << SP
;
2266 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2267 mips_gprmask
|= 1 << RA
;
2268 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2269 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2270 if (pinfo
& MIPS16_INSN_READ_Z
)
2271 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2272 & MIPS16OP_MASK_MOVE32Z
);
2273 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2274 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2275 & MIPS16OP_MASK_REGR32
);
2278 if (place
== NULL
&& ! mips_opts
.noreorder
)
2280 /* Filling the branch delay slot is more complex. We try to
2281 switch the branch with the previous instruction, which we can
2282 do if the previous instruction does not set up a condition
2283 that the branch tests and if the branch is not itself the
2284 target of any branch. */
2285 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2286 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2288 if (mips_optimize
< 2
2289 /* If we have seen .set volatile or .set nomove, don't
2291 || mips_opts
.nomove
!= 0
2292 /* If we had to emit any NOP instructions, then we
2293 already know we can not swap. */
2295 /* If we don't even know the previous insn, we can not
2297 || ! prev_insn_valid
2298 /* If the previous insn is already in a branch delay
2299 slot, then we can not swap. */
2300 || prev_insn_is_delay_slot
2301 /* If the previous previous insn was in a .set
2302 noreorder, we can't swap. Actually, the MIPS
2303 assembler will swap in this situation. However, gcc
2304 configured -with-gnu-as will generate code like
2310 in which we can not swap the bne and INSN. If gcc is
2311 not configured -with-gnu-as, it does not output the
2312 .set pseudo-ops. We don't have to check
2313 prev_insn_unreordered, because prev_insn_valid will
2314 be 0 in that case. We don't want to use
2315 prev_prev_insn_valid, because we do want to be able
2316 to swap at the start of a function. */
2317 || prev_prev_insn_unreordered
2318 /* If the branch is itself the target of a branch, we
2319 can not swap. We cheat on this; all we check for is
2320 whether there is a label on this instruction. If
2321 there are any branches to anything other than a
2322 label, users must use .set noreorder. */
2323 || insn_labels
!= NULL
2324 /* If the previous instruction is in a variant frag, we
2325 can not do the swap. This does not apply to the
2326 mips16, which uses variant frags for different
2328 || (! mips_opts
.mips16
2329 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2330 /* If the branch reads the condition codes, we don't
2331 even try to swap, because in the sequence
2336 we can not swap, and I don't feel like handling that
2338 || (! mips_opts
.mips16
2339 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2340 && (pinfo
& INSN_READ_COND_CODE
))
2341 /* We can not swap with an instruction that requires a
2342 delay slot, becase the target of the branch might
2343 interfere with that instruction. */
2344 || (! mips_opts
.mips16
2345 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2347 /* Itbl support may require additional care here. */
2348 & (INSN_LOAD_COPROC_DELAY
2349 | INSN_COPROC_MOVE_DELAY
2350 | INSN_WRITE_COND_CODE
)))
2351 || (! (hilo_interlocks
2352 || (mips_tune
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2356 || (! mips_opts
.mips16
2358 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2359 || (! mips_opts
.mips16
2360 && mips_opts
.isa
== ISA_MIPS1
2361 /* Itbl support may require additional care here. */
2362 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2363 /* We can not swap with a branch instruction. */
2365 & (INSN_UNCOND_BRANCH_DELAY
2366 | INSN_COND_BRANCH_DELAY
2367 | INSN_COND_BRANCH_LIKELY
))
2368 /* We do not swap with a trap instruction, since it
2369 complicates trap handlers to have the trap
2370 instruction be in a delay slot. */
2371 || (prev_pinfo
& INSN_TRAP
)
2372 /* If the branch reads a register that the previous
2373 instruction sets, we can not swap. */
2374 || (! mips_opts
.mips16
2375 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2376 && insn_uses_reg (ip
,
2377 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2380 || (! mips_opts
.mips16
2381 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2382 && insn_uses_reg (ip
,
2383 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2386 || (mips_opts
.mips16
2387 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2388 && insn_uses_reg (ip
,
2389 ((prev_insn
.insn_opcode
2391 & MIPS16OP_MASK_RX
),
2393 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2394 && insn_uses_reg (ip
,
2395 ((prev_insn
.insn_opcode
2397 & MIPS16OP_MASK_RY
),
2399 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2400 && insn_uses_reg (ip
,
2401 ((prev_insn
.insn_opcode
2403 & MIPS16OP_MASK_RZ
),
2405 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2406 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2407 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2408 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2409 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2410 && insn_uses_reg (ip
,
2411 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2414 /* If the branch writes a register that the previous
2415 instruction sets, we can not swap (we know that
2416 branches write only to RD or to $31). */
2417 || (! mips_opts
.mips16
2418 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2419 && (((pinfo
& INSN_WRITE_GPR_D
)
2420 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2421 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2422 || ((pinfo
& INSN_WRITE_GPR_31
)
2423 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2426 || (! mips_opts
.mips16
2427 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2428 && (((pinfo
& INSN_WRITE_GPR_D
)
2429 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2430 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2431 || ((pinfo
& INSN_WRITE_GPR_31
)
2432 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2435 || (mips_opts
.mips16
2436 && (pinfo
& MIPS16_INSN_WRITE_31
)
2437 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2438 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2439 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2441 /* If the branch writes a register that the previous
2442 instruction reads, we can not swap (we know that
2443 branches only write to RD or to $31). */
2444 || (! mips_opts
.mips16
2445 && (pinfo
& INSN_WRITE_GPR_D
)
2446 && insn_uses_reg (&prev_insn
,
2447 ((ip
->insn_opcode
>> OP_SH_RD
)
2450 || (! mips_opts
.mips16
2451 && (pinfo
& INSN_WRITE_GPR_31
)
2452 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2453 || (mips_opts
.mips16
2454 && (pinfo
& MIPS16_INSN_WRITE_31
)
2455 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2456 /* If we are generating embedded PIC code, the branch
2457 might be expanded into a sequence which uses $at, so
2458 we can't swap with an instruction which reads it. */
2459 || (mips_pic
== EMBEDDED_PIC
2460 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2461 /* If the previous previous instruction has a load
2462 delay, and sets a register that the branch reads, we
2464 || (! mips_opts
.mips16
2465 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2466 /* Itbl support may require additional care here. */
2467 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2468 || (! gpr_interlocks
2469 && (prev_prev_insn
.insn_mo
->pinfo
2470 & INSN_LOAD_MEMORY_DELAY
)))
2471 && insn_uses_reg (ip
,
2472 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2475 /* If one instruction sets a condition code and the
2476 other one uses a condition code, we can not swap. */
2477 || ((pinfo
& INSN_READ_COND_CODE
)
2478 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2479 || ((pinfo
& INSN_WRITE_COND_CODE
)
2480 && (prev_pinfo
& INSN_READ_COND_CODE
))
2481 /* If the previous instruction uses the PC, we can not
2483 || (mips_opts
.mips16
2484 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2485 /* If the previous instruction was extended, we can not
2487 || (mips_opts
.mips16
&& prev_insn_extended
)
2488 /* If the previous instruction had a fixup in mips16
2489 mode, we can not swap. This normally means that the
2490 previous instruction was a 4 byte branch anyhow. */
2491 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2492 /* If the previous instruction is a sync, sync.l, or
2493 sync.p, we can not swap. */
2494 || (prev_pinfo
& INSN_SYNC
))
2496 /* We could do even better for unconditional branches to
2497 portions of this object file; we could pick up the
2498 instruction at the destination, put it in the delay
2499 slot, and bump the destination address. */
2501 /* Update the previous insn information. */
2502 prev_prev_insn
= *ip
;
2503 prev_insn
.insn_mo
= &dummy_opcode
;
2507 /* It looks like we can actually do the swap. */
2508 if (! mips_opts
.mips16
)
2513 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2514 memcpy (temp
, prev_f
, 4);
2515 memcpy (prev_f
, f
, 4);
2516 memcpy (f
, temp
, 4);
2517 if (prev_insn_fixp
[0])
2519 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2520 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2522 if (prev_insn_fixp
[1])
2524 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2525 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2527 if (prev_insn_fixp
[2])
2529 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2530 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2534 fixp
[0]->fx_frag
= prev_insn_frag
;
2535 fixp
[0]->fx_where
= prev_insn_where
;
2539 fixp
[1]->fx_frag
= prev_insn_frag
;
2540 fixp
[1]->fx_where
= prev_insn_where
;
2544 fixp
[2]->fx_frag
= prev_insn_frag
;
2545 fixp
[2]->fx_where
= prev_insn_where
;
2553 assert (prev_insn_fixp
[0] == NULL
);
2554 assert (prev_insn_fixp
[1] == NULL
);
2555 assert (prev_insn_fixp
[2] == NULL
);
2556 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2557 memcpy (temp
, prev_f
, 2);
2558 memcpy (prev_f
, f
, 2);
2559 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2561 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2562 memcpy (f
, temp
, 2);
2566 memcpy (f
, f
+ 2, 2);
2567 memcpy (f
+ 2, temp
, 2);
2571 fixp
[0]->fx_frag
= prev_insn_frag
;
2572 fixp
[0]->fx_where
= prev_insn_where
;
2576 fixp
[1]->fx_frag
= prev_insn_frag
;
2577 fixp
[1]->fx_where
= prev_insn_where
;
2581 fixp
[2]->fx_frag
= prev_insn_frag
;
2582 fixp
[2]->fx_where
= prev_insn_where
;
2586 /* Update the previous insn information; leave prev_insn
2588 prev_prev_insn
= *ip
;
2590 prev_insn_is_delay_slot
= 1;
2592 /* If that was an unconditional branch, forget the previous
2593 insn information. */
2594 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2596 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2597 prev_insn
.insn_mo
= &dummy_opcode
;
2600 prev_insn_fixp
[0] = NULL
;
2601 prev_insn_fixp
[1] = NULL
;
2602 prev_insn_fixp
[2] = NULL
;
2603 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2604 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2605 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2606 prev_insn_extended
= 0;
2608 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2610 /* We don't yet optimize a branch likely. What we should do
2611 is look at the target, copy the instruction found there
2612 into the delay slot, and increment the branch to jump to
2613 the next instruction. */
2615 /* Update the previous insn information. */
2616 prev_prev_insn
= *ip
;
2617 prev_insn
.insn_mo
= &dummy_opcode
;
2618 prev_insn_fixp
[0] = NULL
;
2619 prev_insn_fixp
[1] = NULL
;
2620 prev_insn_fixp
[2] = NULL
;
2621 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2622 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2623 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2624 prev_insn_extended
= 0;
2628 /* Update the previous insn information. */
2630 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2632 prev_prev_insn
= prev_insn
;
2635 /* Any time we see a branch, we always fill the delay slot
2636 immediately; since this insn is not a branch, we know it
2637 is not in a delay slot. */
2638 prev_insn_is_delay_slot
= 0;
2640 prev_insn_fixp
[0] = fixp
[0];
2641 prev_insn_fixp
[1] = fixp
[1];
2642 prev_insn_fixp
[2] = fixp
[2];
2643 prev_insn_reloc_type
[0] = reloc_type
[0];
2644 prev_insn_reloc_type
[1] = reloc_type
[1];
2645 prev_insn_reloc_type
[2] = reloc_type
[2];
2646 if (mips_opts
.mips16
)
2647 prev_insn_extended
= (ip
->use_extend
2648 || *reloc_type
> BFD_RELOC_UNUSED
);
2651 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2652 prev_insn_unreordered
= 0;
2653 prev_insn_frag
= frag_now
;
2654 prev_insn_where
= f
- frag_now
->fr_literal
;
2655 prev_insn_valid
= 1;
2657 else if (place
== NULL
)
2659 /* We need to record a bit of information even when we are not
2660 reordering, in order to determine the base address for mips16
2661 PC relative relocs. */
2662 prev_prev_insn
= prev_insn
;
2664 prev_insn_reloc_type
[0] = reloc_type
[0];
2665 prev_insn_reloc_type
[1] = reloc_type
[1];
2666 prev_insn_reloc_type
[2] = reloc_type
[2];
2667 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2668 prev_insn_unreordered
= 1;
2671 /* We just output an insn, so the next one doesn't have a label. */
2672 mips_clear_insn_labels ();
2674 /* We must ensure that a fixup associated with an unmatched %hi
2675 reloc does not become a variant frag. Otherwise, the
2676 rearrangement of %hi relocs in frob_file may confuse
2680 frag_wane (frag_now
);
2685 /* This function forgets that there was any previous instruction or
2686 label. If PRESERVE is non-zero, it remembers enough information to
2687 know whether nops are needed before a noreorder section. */
2690 mips_no_prev_insn (preserve
)
2695 prev_insn
.insn_mo
= &dummy_opcode
;
2696 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2697 prev_nop_frag
= NULL
;
2698 prev_nop_frag_holds
= 0;
2699 prev_nop_frag_required
= 0;
2700 prev_nop_frag_since
= 0;
2702 prev_insn_valid
= 0;
2703 prev_insn_is_delay_slot
= 0;
2704 prev_insn_unreordered
= 0;
2705 prev_insn_extended
= 0;
2706 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2707 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2708 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2709 prev_prev_insn_unreordered
= 0;
2710 mips_clear_insn_labels ();
2713 /* This function must be called whenever we turn on noreorder or emit
2714 something other than instructions. It inserts any NOPS which might
2715 be needed by the previous instruction, and clears the information
2716 kept for the previous instructions. The INSNS parameter is true if
2717 instructions are to follow. */
2720 mips_emit_delays (insns
)
2723 if (! mips_opts
.noreorder
)
2728 if ((! mips_opts
.mips16
2729 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2730 && (! cop_interlocks
2731 && (prev_insn
.insn_mo
->pinfo
2732 & (INSN_LOAD_COPROC_DELAY
2733 | INSN_COPROC_MOVE_DELAY
2734 | INSN_WRITE_COND_CODE
))))
2735 || (! hilo_interlocks
2736 && (prev_insn
.insn_mo
->pinfo
2739 || (! mips_opts
.mips16
2741 && (prev_insn
.insn_mo
->pinfo
2742 & INSN_LOAD_MEMORY_DELAY
))
2743 || (! mips_opts
.mips16
2744 && mips_opts
.isa
== ISA_MIPS1
2745 && (prev_insn
.insn_mo
->pinfo
2746 & INSN_COPROC_MEMORY_DELAY
)))
2748 /* Itbl support may require additional care here. */
2750 if ((! mips_opts
.mips16
2751 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2752 && (! cop_interlocks
2753 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2754 || (! hilo_interlocks
2755 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2756 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2759 if (prev_insn_unreordered
)
2762 else if ((! mips_opts
.mips16
2763 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2764 && (! cop_interlocks
2765 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2766 || (! hilo_interlocks
2767 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2768 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2770 /* Itbl support may require additional care here. */
2771 if (! prev_prev_insn_unreordered
)
2777 struct insn_label_list
*l
;
2781 /* Record the frag which holds the nop instructions, so
2782 that we can remove them if we don't need them. */
2783 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2784 prev_nop_frag
= frag_now
;
2785 prev_nop_frag_holds
= nops
;
2786 prev_nop_frag_required
= 0;
2787 prev_nop_frag_since
= 0;
2790 for (; nops
> 0; --nops
)
2795 /* Move on to a new frag, so that it is safe to simply
2796 decrease the size of prev_nop_frag. */
2797 frag_wane (frag_now
);
2801 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2805 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2806 symbol_set_frag (l
->label
, frag_now
);
2807 val
= (valueT
) frag_now_fix ();
2808 /* mips16 text labels are stored as odd. */
2809 if (mips_opts
.mips16
)
2811 S_SET_VALUE (l
->label
, val
);
2816 /* Mark instruction labels in mips16 mode. */
2817 if (mips_opts
.mips16
&& insns
)
2818 mips16_mark_labels ();
2820 mips_no_prev_insn (insns
);
2823 /* Build an instruction created by a macro expansion. This is passed
2824 a pointer to the count of instructions created so far, an
2825 expression, the name of the instruction to build, an operand format
2826 string, and corresponding arguments. */
2830 macro_build (char *place
,
2838 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2847 struct mips_cl_insn insn
;
2848 bfd_reloc_code_real_type r
[3];
2852 va_start (args
, fmt
);
2858 * If the macro is about to expand into a second instruction,
2859 * print a warning if needed. We need to pass ip as a parameter
2860 * to generate a better warning message here...
2862 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2863 as_warn (_("Macro instruction expanded into multiple instructions"));
2866 *counter
+= 1; /* bump instruction counter */
2868 if (mips_opts
.mips16
)
2870 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2875 r
[0] = BFD_RELOC_UNUSED
;
2876 r
[1] = BFD_RELOC_UNUSED
;
2877 r
[2] = BFD_RELOC_UNUSED
;
2878 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2879 assert (insn
.insn_mo
);
2880 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2882 /* Search until we get a match for NAME. */
2885 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2886 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2887 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_arch
)
2888 && (mips_arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2892 assert (insn
.insn_mo
->name
);
2893 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2896 insn
.insn_opcode
= insn
.insn_mo
->match
;
2912 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
2916 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
2921 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
2926 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
2931 int tmp
= va_arg (args
, int);
2933 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
2934 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
2940 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
2947 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
2951 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
2955 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
2959 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
2963 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
2970 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
2976 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2977 assert (*r
== BFD_RELOC_GPREL16
2978 || *r
== BFD_RELOC_MIPS_LITERAL
2979 || *r
== BFD_RELOC_MIPS_HIGHER
2980 || *r
== BFD_RELOC_HI16_S
2981 || *r
== BFD_RELOC_LO16
2982 || *r
== BFD_RELOC_MIPS_GOT16
2983 || *r
== BFD_RELOC_MIPS_CALL16
2984 || *r
== BFD_RELOC_MIPS_GOT_LO16
2985 || *r
== BFD_RELOC_MIPS_CALL_LO16
2986 || (ep
->X_op
== O_subtract
2987 && *r
== BFD_RELOC_PCREL_LO16
));
2991 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2993 && (ep
->X_op
== O_constant
2994 || (ep
->X_op
== O_symbol
2995 && (*r
== BFD_RELOC_MIPS_HIGHEST
2996 || *r
== BFD_RELOC_HI16_S
2997 || *r
== BFD_RELOC_HI16
2998 || *r
== BFD_RELOC_GPREL16
2999 || *r
== BFD_RELOC_MIPS_GOT_HI16
3000 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3001 || (ep
->X_op
== O_subtract
3002 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3006 assert (ep
!= NULL
);
3008 * This allows macro() to pass an immediate expression for
3009 * creating short branches without creating a symbol.
3010 * Note that the expression still might come from the assembly
3011 * input, in which case the value is not checked for range nor
3012 * is a relocation entry generated (yuck).
3014 if (ep
->X_op
== O_constant
)
3016 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3020 if (mips_pic
== EMBEDDED_PIC
)
3021 *r
= BFD_RELOC_16_PCREL_S2
;
3023 *r
= BFD_RELOC_16_PCREL
;
3027 assert (ep
!= NULL
);
3028 *r
= BFD_RELOC_MIPS_JMP
;
3032 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3041 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3043 append_insn (place
, &insn
, ep
, r
, false);
3047 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
3049 int *counter ATTRIBUTE_UNUSED
;
3055 struct mips_cl_insn insn
;
3056 bfd_reloc_code_real_type r
[3]
3057 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3059 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3060 assert (insn
.insn_mo
);
3061 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3063 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3064 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3067 assert (insn
.insn_mo
->name
);
3068 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3071 insn
.insn_opcode
= insn
.insn_mo
->match
;
3072 insn
.use_extend
= false;
3091 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3096 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3100 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3104 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3114 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3121 regno
= va_arg (args
, int);
3122 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3123 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3144 assert (ep
!= NULL
);
3146 if (ep
->X_op
!= O_constant
)
3147 *r
= BFD_RELOC_UNUSED
+ c
;
3150 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, false, false,
3151 false, &insn
.insn_opcode
, &insn
.use_extend
,
3154 *r
= BFD_RELOC_UNUSED
;
3160 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3167 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3169 append_insn (place
, &insn
, ep
, r
, false);
3173 * Generate a "lui" instruction.
3176 macro_build_lui (place
, counter
, ep
, regnum
)
3182 expressionS high_expr
;
3183 struct mips_cl_insn insn
;
3184 bfd_reloc_code_real_type r
[3]
3185 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3186 CONST
char *name
= "lui";
3187 CONST
char *fmt
= "t,u";
3189 assert (! mips_opts
.mips16
);
3195 high_expr
.X_op
= O_constant
;
3196 high_expr
.X_add_number
= ep
->X_add_number
;
3199 if (high_expr
.X_op
== O_constant
)
3201 /* we can compute the instruction now without a relocation entry */
3202 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3204 *r
= BFD_RELOC_UNUSED
;
3206 else if (! HAVE_NEWABI
)
3208 assert (ep
->X_op
== O_symbol
);
3209 /* _gp_disp is a special case, used from s_cpload. */
3210 assert (mips_pic
== NO_PIC
3211 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
3212 *r
= BFD_RELOC_HI16_S
;
3216 * If the macro is about to expand into a second instruction,
3217 * print a warning if needed. We need to pass ip as a parameter
3218 * to generate a better warning message here...
3220 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
3221 as_warn (_("Macro instruction expanded into multiple instructions"));
3224 *counter
+= 1; /* bump instruction counter */
3226 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3227 assert (insn
.insn_mo
);
3228 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3229 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3231 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3232 if (*r
== BFD_RELOC_UNUSED
)
3234 insn
.insn_opcode
|= high_expr
.X_add_number
;
3235 append_insn (place
, &insn
, NULL
, r
, false);
3238 append_insn (place
, &insn
, &high_expr
, r
, false);
3242 * Generates code to set the $at register to true (one)
3243 * if reg is less than the immediate expression.
3246 set_at (counter
, reg
, unsignedp
)
3251 if (imm_expr
.X_op
== O_constant
3252 && imm_expr
.X_add_number
>= -0x8000
3253 && imm_expr
.X_add_number
< 0x8000)
3254 macro_build ((char *) NULL
, counter
, &imm_expr
,
3255 unsignedp
? "sltiu" : "slti",
3256 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
3259 load_register (counter
, AT
, &imm_expr
, 0);
3260 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3261 unsignedp
? "sltu" : "slt",
3262 "d,v,t", AT
, reg
, AT
);
3266 /* Warn if an expression is not a constant. */
3269 check_absolute_expr (ip
, ex
)
3270 struct mips_cl_insn
*ip
;
3273 if (ex
->X_op
== O_big
)
3274 as_bad (_("unsupported large constant"));
3275 else if (ex
->X_op
!= O_constant
)
3276 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3279 /* Count the leading zeroes by performing a binary chop. This is a
3280 bulky bit of source, but performance is a LOT better for the
3281 majority of values than a simple loop to count the bits:
3282 for (lcnt = 0; (lcnt < 32); lcnt++)
3283 if ((v) & (1 << (31 - lcnt)))
3285 However it is not code size friendly, and the gain will drop a bit
3286 on certain cached systems.
3288 #define COUNT_TOP_ZEROES(v) \
3289 (((v) & ~0xffff) == 0 \
3290 ? ((v) & ~0xff) == 0 \
3291 ? ((v) & ~0xf) == 0 \
3292 ? ((v) & ~0x3) == 0 \
3293 ? ((v) & ~0x1) == 0 \
3298 : ((v) & ~0x7) == 0 \
3301 : ((v) & ~0x3f) == 0 \
3302 ? ((v) & ~0x1f) == 0 \
3305 : ((v) & ~0x7f) == 0 \
3308 : ((v) & ~0xfff) == 0 \
3309 ? ((v) & ~0x3ff) == 0 \
3310 ? ((v) & ~0x1ff) == 0 \
3313 : ((v) & ~0x7ff) == 0 \
3316 : ((v) & ~0x3fff) == 0 \
3317 ? ((v) & ~0x1fff) == 0 \
3320 : ((v) & ~0x7fff) == 0 \
3323 : ((v) & ~0xffffff) == 0 \
3324 ? ((v) & ~0xfffff) == 0 \
3325 ? ((v) & ~0x3ffff) == 0 \
3326 ? ((v) & ~0x1ffff) == 0 \
3329 : ((v) & ~0x7ffff) == 0 \
3332 : ((v) & ~0x3fffff) == 0 \
3333 ? ((v) & ~0x1fffff) == 0 \
3336 : ((v) & ~0x7fffff) == 0 \
3339 : ((v) & ~0xfffffff) == 0 \
3340 ? ((v) & ~0x3ffffff) == 0 \
3341 ? ((v) & ~0x1ffffff) == 0 \
3344 : ((v) & ~0x7ffffff) == 0 \
3347 : ((v) & ~0x3fffffff) == 0 \
3348 ? ((v) & ~0x1fffffff) == 0 \
3351 : ((v) & ~0x7fffffff) == 0 \
3356 * This routine generates the least number of instructions neccessary to load
3357 * an absolute expression value into a register.
3360 load_register (counter
, reg
, ep
, dbl
)
3367 expressionS hi32
, lo32
;
3369 if (ep
->X_op
!= O_big
)
3371 assert (ep
->X_op
== O_constant
);
3372 if (ep
->X_add_number
< 0x8000
3373 && (ep
->X_add_number
>= 0
3374 || (ep
->X_add_number
>= -0x8000
3377 || sizeof (ep
->X_add_number
) > 4))))
3379 /* We can handle 16 bit signed values with an addiu to
3380 $zero. No need to ever use daddiu here, since $zero and
3381 the result are always correct in 32 bit mode. */
3382 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3383 (int) BFD_RELOC_LO16
);
3386 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3388 /* We can handle 16 bit unsigned values with an ori to
3390 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3391 (int) BFD_RELOC_LO16
);
3394 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3395 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3396 == ~ (offsetT
) 0x7fffffff))
3399 || sizeof (ep
->X_add_number
) > 4
3400 || (ep
->X_add_number
& 0x80000000) == 0))
3401 || ((HAVE_32BIT_GPRS
|| ! dbl
)
3402 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3405 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3406 == ~ (offsetT
) 0xffffffff)))
3408 /* 32 bit values require an lui. */
3409 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3410 (int) BFD_RELOC_HI16
);
3411 if ((ep
->X_add_number
& 0xffff) != 0)
3412 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3413 (int) BFD_RELOC_LO16
);
3418 /* The value is larger than 32 bits. */
3420 if (HAVE_32BIT_GPRS
)
3422 as_bad (_("Number (0x%lx) larger than 32 bits"),
3423 (unsigned long) ep
->X_add_number
);
3424 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3425 (int) BFD_RELOC_LO16
);
3429 if (ep
->X_op
!= O_big
)
3432 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3433 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3434 hi32
.X_add_number
&= 0xffffffff;
3436 lo32
.X_add_number
&= 0xffffffff;
3440 assert (ep
->X_add_number
> 2);
3441 if (ep
->X_add_number
== 3)
3442 generic_bignum
[3] = 0;
3443 else if (ep
->X_add_number
> 4)
3444 as_bad (_("Number larger than 64 bits"));
3445 lo32
.X_op
= O_constant
;
3446 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3447 hi32
.X_op
= O_constant
;
3448 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3451 if (hi32
.X_add_number
== 0)
3456 unsigned long hi
, lo
;
3458 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3460 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3462 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3463 reg
, 0, (int) BFD_RELOC_LO16
);
3466 if (lo32
.X_add_number
& 0x80000000)
3468 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3469 (int) BFD_RELOC_HI16
);
3470 if (lo32
.X_add_number
& 0xffff)
3471 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3472 reg
, reg
, (int) BFD_RELOC_LO16
);
3477 /* Check for 16bit shifted constant. We know that hi32 is
3478 non-zero, so start the mask on the first bit of the hi32
3483 unsigned long himask
, lomask
;
3487 himask
= 0xffff >> (32 - shift
);
3488 lomask
= (0xffff << shift
) & 0xffffffff;
3492 himask
= 0xffff << (shift
- 32);
3495 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3496 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3500 tmp
.X_op
= O_constant
;
3502 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3503 | (lo32
.X_add_number
>> shift
));
3505 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3506 macro_build ((char *) NULL
, counter
, &tmp
,
3507 "ori", "t,r,i", reg
, 0,
3508 (int) BFD_RELOC_LO16
);
3509 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3510 (shift
>= 32) ? "dsll32" : "dsll",
3512 (shift
>= 32) ? shift
- 32 : shift
);
3517 while (shift
<= (64 - 16));
3519 /* Find the bit number of the lowest one bit, and store the
3520 shifted value in hi/lo. */
3521 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3522 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3526 while ((lo
& 1) == 0)
3531 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3537 while ((hi
& 1) == 0)
3546 /* Optimize if the shifted value is a (power of 2) - 1. */
3547 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3548 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3550 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3555 /* This instruction will set the register to be all
3557 tmp
.X_op
= O_constant
;
3558 tmp
.X_add_number
= (offsetT
) -1;
3559 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3560 reg
, 0, (int) BFD_RELOC_LO16
);
3564 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3565 (bit
>= 32) ? "dsll32" : "dsll",
3567 (bit
>= 32) ? bit
- 32 : bit
);
3569 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3570 (shift
>= 32) ? "dsrl32" : "dsrl",
3572 (shift
>= 32) ? shift
- 32 : shift
);
3577 /* Sign extend hi32 before calling load_register, because we can
3578 generally get better code when we load a sign extended value. */
3579 if ((hi32
.X_add_number
& 0x80000000) != 0)
3580 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3581 load_register (counter
, reg
, &hi32
, 0);
3584 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3588 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3589 "dsll32", "d,w,<", reg
, freg
, 0);
3597 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3599 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3600 (int) BFD_RELOC_HI16
);
3601 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3602 "dsrl32", "d,w,<", reg
, reg
, 0);
3608 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3609 "d,w,<", reg
, freg
, 16);
3613 mid16
.X_add_number
>>= 16;
3614 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3615 freg
, (int) BFD_RELOC_LO16
);
3616 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "dsll",
3617 "d,w,<", reg
, reg
, 16);
3620 if ((lo32
.X_add_number
& 0xffff) != 0)
3621 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3622 (int) BFD_RELOC_LO16
);
3625 /* Load an address into a register. */
3628 load_address (counter
, reg
, ep
, dbl
, used_at
)
3637 if (ep
->X_op
!= O_constant
3638 && ep
->X_op
!= O_symbol
)
3640 as_bad (_("expression too complex"));
3641 ep
->X_op
= O_constant
;
3644 if (ep
->X_op
== O_constant
)
3646 load_register (counter
, reg
, ep
, dbl
);
3650 if (mips_pic
== NO_PIC
)
3652 /* If this is a reference to a GP relative symbol, we want
3653 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3655 lui $reg,<sym> (BFD_RELOC_HI16_S)
3656 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3657 If we have an addend, we always use the latter form.
3659 With 64bit address space and a usable $at we want
3660 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3661 lui $at,<sym> (BFD_RELOC_HI16_S)
3662 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3663 daddiu $at,<sym> (BFD_RELOC_LO16)
3667 If $at is already in use, we use an path which is suboptimal
3668 on superscalar processors.
3669 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3670 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3672 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3674 daddiu $reg,<sym> (BFD_RELOC_LO16)
3680 /* We don't do GP optimization for now because RELAX_ENCODE can't
3681 hold the data for such large chunks. */
3685 macro_build (p
, counter
, ep
, "lui", "t,u",
3686 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3687 macro_build (p
, counter
, ep
, "lui", "t,u",
3688 AT
, (int) BFD_RELOC_HI16_S
);
3689 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3690 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3691 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3692 AT
, AT
, (int) BFD_RELOC_LO16
);
3693 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll32",
3694 "d,w,<", reg
, reg
, 0);
3695 macro_build (p
, counter
, (expressionS
*) NULL
, "dadd",
3696 "d,v,t", reg
, reg
, AT
);
3701 macro_build (p
, counter
, ep
, "lui", "t,u",
3702 reg
, (int) BFD_RELOC_MIPS_HIGHEST
);
3703 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3704 reg
, reg
, (int) BFD_RELOC_MIPS_HIGHER
);
3705 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3706 "d,w,<", reg
, reg
, 16);
3707 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3708 reg
, reg
, (int) BFD_RELOC_HI16_S
);
3709 macro_build (p
, counter
, (expressionS
*) NULL
, "dsll",
3710 "d,w,<", reg
, reg
, 16);
3711 macro_build (p
, counter
, ep
, "daddiu", "t,r,j",
3712 reg
, reg
, (int) BFD_RELOC_LO16
);
3718 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3719 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3722 macro_build ((char *) NULL
, counter
, ep
,
3723 dbl
? "daddiu" : "addiu", "t,r,j", reg
, GP
,
3724 (int) BFD_RELOC_GPREL16
);
3725 p
= frag_var (rs_machine_dependent
, 8, 0,
3726 RELAX_ENCODE (4, 8, 0, 4, 0,
3727 mips_opts
.warn_about_macros
),
3728 ep
->X_add_symbol
, 0, NULL
);
3730 macro_build_lui (p
, counter
, ep
, reg
);
3733 macro_build (p
, counter
, ep
, dbl
? "daddiu" : "addiu",
3734 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3737 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3741 /* If this is a reference to an external symbol, we want
3742 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3744 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3746 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3747 If there is a constant, it must be added in after. */
3748 ex
.X_add_number
= ep
->X_add_number
;
3749 ep
->X_add_number
= 0;
3751 macro_build ((char *) NULL
, counter
, ep
,
3752 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
3753 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3754 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3755 p
= frag_var (rs_machine_dependent
, 4, 0,
3756 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3757 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3758 macro_build (p
, counter
, ep
,
3759 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3760 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3761 if (ex
.X_add_number
!= 0)
3763 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3764 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3765 ex
.X_op
= O_constant
;
3766 macro_build ((char *) NULL
, counter
, &ex
,
3767 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
3768 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3771 else if (mips_pic
== SVR4_PIC
)
3776 /* This is the large GOT case. If this is a reference to an
3777 external symbol, we want
3778 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3780 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3781 Otherwise, for a reference to a local symbol, we want
3782 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3784 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3785 If there is a constant, it must be added in after. */
3786 ex
.X_add_number
= ep
->X_add_number
;
3787 ep
->X_add_number
= 0;
3788 if (reg_needs_delay (GP
))
3793 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3794 (int) BFD_RELOC_MIPS_GOT_HI16
);
3795 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3796 dbl
? "daddu" : "addu", "d,v,t", reg
, reg
, GP
);
3797 macro_build ((char *) NULL
, counter
, ep
, dbl
? "ld" : "lw",
3798 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3799 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3800 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3801 mips_opts
.warn_about_macros
),
3802 ep
->X_add_symbol
, 0, NULL
);
3805 /* We need a nop before loading from $gp. This special
3806 check is required because the lui which starts the main
3807 instruction stream does not refer to $gp, and so will not
3808 insert the nop which may be required. */
3809 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3812 macro_build (p
, counter
, ep
, dbl
? "ld" : "lw",
3813 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3815 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3817 macro_build (p
, counter
, ep
, dbl
? "daddiu" : "addiu",
3818 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3819 if (ex
.X_add_number
!= 0)
3821 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3822 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3823 ex
.X_op
= O_constant
;
3824 macro_build ((char *) NULL
, counter
, &ex
, dbl
? "daddiu" : "addiu",
3825 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3828 else if (mips_pic
== EMBEDDED_PIC
)
3831 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3833 macro_build ((char *) NULL
, counter
, ep
, dbl
? "daddiu" : "addiu",
3834 "t,r,j", reg
, GP
, (int) BFD_RELOC_GPREL16
);
3840 /* Move the contents of register SOURCE into register DEST. */
3843 move_register (counter
, dest
, source
)
3848 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3849 HAVE_32BIT_GPRS
? "addu" : "daddu",
3850 "d,v,t", dest
, source
, 0);
3855 * This routine implements the seemingly endless macro or synthesized
3856 * instructions and addressing modes in the mips assembly language. Many
3857 * of these macros are simple and are similar to each other. These could
3858 * probably be handled by some kind of table or grammer aproach instead of
3859 * this verbose method. Others are not simple macros but are more like
3860 * optimizing code generation.
3861 * One interesting optimization is when several store macros appear
3862 * consecutivly that would load AT with the upper half of the same address.
3863 * The ensuing load upper instructions are ommited. This implies some kind
3864 * of global optimization. We currently only optimize within a single macro.
3865 * For many of the load and store macros if the address is specified as a
3866 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3867 * first load register 'at' with zero and use it as the base register. The
3868 * mips assembler simply uses register $zero. Just one tiny optimization
3873 struct mips_cl_insn
*ip
;
3875 register int treg
, sreg
, dreg
, breg
;
3891 bfd_reloc_code_real_type r
;
3893 int hold_mips_optimize
;
3895 assert (! mips_opts
.mips16
);
3897 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3898 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3899 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3900 mask
= ip
->insn_mo
->mask
;
3902 expr1
.X_op
= O_constant
;
3903 expr1
.X_op_symbol
= NULL
;
3904 expr1
.X_add_symbol
= NULL
;
3905 expr1
.X_add_number
= 1;
3917 mips_emit_delays (true);
3918 ++mips_opts
.noreorder
;
3919 mips_any_noreorder
= 1;
3921 expr1
.X_add_number
= 8;
3922 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3924 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
3927 move_register (&icnt
, dreg
, sreg
);
3928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3929 dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
3931 --mips_opts
.noreorder
;
3952 if (imm_expr
.X_op
== O_constant
3953 && imm_expr
.X_add_number
>= -0x8000
3954 && imm_expr
.X_add_number
< 0x8000)
3956 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3957 (int) BFD_RELOC_LO16
);
3960 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3961 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
3981 if (imm_expr
.X_op
== O_constant
3982 && imm_expr
.X_add_number
>= 0
3983 && imm_expr
.X_add_number
< 0x10000)
3985 if (mask
!= M_NOR_I
)
3986 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3987 sreg
, (int) BFD_RELOC_LO16
);
3990 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3991 treg
, sreg
, (int) BFD_RELOC_LO16
);
3992 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nor",
3993 "d,v,t", treg
, treg
, 0);
3998 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3999 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d,v,t",
4017 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4019 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
4023 load_register (&icnt
, AT
, &imm_expr
, 0);
4024 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
4032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4033 likely
? "bgezl" : "bgez", "s,p", sreg
);
4038 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4039 likely
? "blezl" : "blez", "s,p", treg
);
4042 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4044 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4045 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4051 /* check for > max integer */
4052 maxnum
= 0x7fffffff;
4053 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4060 if (imm_expr
.X_op
== O_constant
4061 && imm_expr
.X_add_number
>= maxnum
4062 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4065 /* result is always false */
4069 as_warn (_("Branch %s is always false (nop)"),
4071 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop",
4077 as_warn (_("Branch likely %s is always false"),
4079 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
4084 if (imm_expr
.X_op
!= O_constant
)
4085 as_bad (_("Unsupported large constant"));
4086 imm_expr
.X_add_number
++;
4090 if (mask
== M_BGEL_I
)
4092 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4094 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4095 likely
? "bgezl" : "bgez", "s,p", sreg
);
4098 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4101 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4104 maxnum
= 0x7fffffff;
4105 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4112 maxnum
= - maxnum
- 1;
4113 if (imm_expr
.X_op
== O_constant
4114 && imm_expr
.X_add_number
<= maxnum
4115 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4118 /* result is always true */
4119 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4120 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4123 set_at (&icnt
, sreg
, 0);
4124 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4125 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4135 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4136 likely
? "beql" : "beq", "s,t,p", 0, treg
);
4139 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4140 "d,v,t", AT
, sreg
, treg
);
4141 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4142 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4150 && imm_expr
.X_op
== O_constant
4151 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4153 if (imm_expr
.X_op
!= O_constant
)
4154 as_bad (_("Unsupported large constant"));
4155 imm_expr
.X_add_number
++;
4159 if (mask
== M_BGEUL_I
)
4161 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4163 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4165 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4166 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4169 set_at (&icnt
, sreg
, 1);
4170 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4171 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4179 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4180 likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4185 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4186 likely
? "bltzl" : "bltz", "s,p", treg
);
4189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4191 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4192 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4200 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4201 likely
? "bnel" : "bne", "s,t,p", sreg
, 0);
4206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4207 "d,v,t", AT
, treg
, sreg
);
4208 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4209 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4217 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4218 likely
? "blezl" : "blez", "s,p", sreg
);
4223 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4224 likely
? "bgezl" : "bgez", "s,p", treg
);
4227 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4229 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4230 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4236 maxnum
= 0x7fffffff;
4237 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4244 if (imm_expr
.X_op
== O_constant
4245 && imm_expr
.X_add_number
>= maxnum
4246 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4248 if (imm_expr
.X_op
!= O_constant
)
4249 as_bad (_("Unsupported large constant"));
4250 imm_expr
.X_add_number
++;
4254 if (mask
== M_BLTL_I
)
4256 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4258 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4259 likely
? "bltzl" : "bltz", "s,p", sreg
);
4262 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4264 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4265 likely
? "blezl" : "blez", "s,p", sreg
);
4268 set_at (&icnt
, sreg
, 0);
4269 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4270 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4278 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4279 likely
? "beql" : "beq", "s,t,p", sreg
, 0);
4284 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4285 "d,v,t", AT
, treg
, sreg
);
4286 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4287 likely
? "beql" : "beq", "s,t,p", AT
, 0);
4295 && imm_expr
.X_op
== O_constant
4296 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4298 if (imm_expr
.X_op
!= O_constant
)
4299 as_bad (_("Unsupported large constant"));
4300 imm_expr
.X_add_number
++;
4304 if (mask
== M_BLTUL_I
)
4306 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4308 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4310 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4311 likely
? "beql" : "beq",
4315 set_at (&icnt
, sreg
, 1);
4316 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4317 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4325 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4326 likely
? "bltzl" : "bltz", "s,p", sreg
);
4331 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4332 likely
? "bgtzl" : "bgtz", "s,p", treg
);
4335 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
4337 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4338 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4348 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4349 likely
? "bnel" : "bne", "s,t,p", 0, treg
);
4352 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
4355 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4356 likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4371 as_warn (_("Divide by zero."));
4373 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4376 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4381 mips_emit_delays (true);
4382 ++mips_opts
.noreorder
;
4383 mips_any_noreorder
= 1;
4386 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4388 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4389 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4393 expr1
.X_add_number
= 8;
4394 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4395 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4396 dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4397 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4400 expr1
.X_add_number
= -1;
4401 macro_build ((char *) NULL
, &icnt
, &expr1
,
4402 dbl
? "daddiu" : "addiu",
4403 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4404 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4405 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4408 expr1
.X_add_number
= 1;
4409 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4410 (int) BFD_RELOC_LO16
);
4411 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "dsll32",
4412 "d,w,<", AT
, AT
, 31);
4416 expr1
.X_add_number
= 0x80000000;
4417 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4418 (int) BFD_RELOC_HI16
);
4422 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4424 /* We want to close the noreorder block as soon as possible, so
4425 that later insns are available for delay slot filling. */
4426 --mips_opts
.noreorder
;
4430 expr1
.X_add_number
= 8;
4431 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4432 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
4435 /* We want to close the noreorder block as soon as possible, so
4436 that later insns are available for delay slot filling. */
4437 --mips_opts
.noreorder
;
4439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4442 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d", dreg
);
4481 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4483 as_warn (_("Divide by zero."));
4485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4488 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4492 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4494 if (strcmp (s2
, "mflo") == 0)
4495 move_register (&icnt
, dreg
, sreg
);
4497 move_register (&icnt
, dreg
, 0);
4500 if (imm_expr
.X_op
== O_constant
4501 && imm_expr
.X_add_number
== -1
4502 && s
[strlen (s
) - 1] != 'u')
4504 if (strcmp (s2
, "mflo") == 0)
4506 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4507 dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4510 move_register (&icnt
, dreg
, 0);
4514 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4515 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4517 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4536 mips_emit_delays (true);
4537 ++mips_opts
.noreorder
;
4538 mips_any_noreorder
= 1;
4541 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "teq",
4543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4545 /* We want to close the noreorder block as soon as possible, so
4546 that later insns are available for delay slot filling. */
4547 --mips_opts
.noreorder
;
4551 expr1
.X_add_number
= 8;
4552 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4553 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "z,s,t",
4556 /* We want to close the noreorder block as soon as possible, so
4557 that later insns are available for delay slot filling. */
4558 --mips_opts
.noreorder
;
4559 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
4562 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "d", dreg
);
4568 /* Load the address of a symbol into a register. If breg is not
4569 zero, we then add a base register to it. */
4582 /* When generating embedded PIC code, we permit expressions of
4585 la $treg,foo-bar($breg)
4586 where bar is an address in the current section. These are used
4587 when getting the addresses of functions. We don't permit
4588 X_add_number to be non-zero, because if the symbol is
4589 external the relaxing code needs to know that any addend is
4590 purely the offset to X_op_symbol. */
4591 if (mips_pic
== EMBEDDED_PIC
4592 && offset_expr
.X_op
== O_subtract
4593 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4594 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4595 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4597 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4600 && (offset_expr
.X_add_number
== 0
4601 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4607 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4608 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4612 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4613 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
4614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4615 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4616 "d,v,t", tempreg
, tempreg
, breg
);
4618 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4619 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4620 "t,r,j", treg
, tempreg
, (int) BFD_RELOC_PCREL_LO16
);
4626 if (offset_expr
.X_op
!= O_symbol
4627 && offset_expr
.X_op
!= O_constant
)
4629 as_bad (_("expression too complex"));
4630 offset_expr
.X_op
= O_constant
;
4633 if (offset_expr
.X_op
== O_constant
)
4634 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4635 else if (mips_pic
== NO_PIC
)
4637 /* If this is a reference to a GP relative symbol, we want
4638 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4640 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4641 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4642 If we have a constant, we need two instructions anyhow,
4643 so we may as well always use the latter form.
4645 With 64bit address space and a usable $at we want
4646 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4647 lui $at,<sym> (BFD_RELOC_HI16_S)
4648 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4649 daddiu $at,<sym> (BFD_RELOC_LO16)
4651 dadd $tempreg,$tempreg,$at
4653 If $at is already in use, we use an path which is suboptimal
4654 on superscalar processors.
4655 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4656 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4658 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4660 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4663 if (HAVE_64BIT_ADDRESSES
)
4665 /* We don't do GP optimization for now because RELAX_ENCODE can't
4666 hold the data for such large chunks. */
4670 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4671 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4672 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4673 AT
, (int) BFD_RELOC_HI16_S
);
4674 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4675 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4676 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4677 AT
, AT
, (int) BFD_RELOC_LO16
);
4678 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
4679 "d,w,<", tempreg
, tempreg
, 0);
4680 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dadd", "d,v,t",
4681 tempreg
, tempreg
, AT
);
4686 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
4687 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
4688 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4689 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
4690 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4691 tempreg
, tempreg
, 16);
4692 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4693 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
4694 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll", "d,w,<",
4695 tempreg
, tempreg
, 16);
4696 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
4697 tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4702 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4703 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4706 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4707 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4708 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_GPREL16
);
4709 p
= frag_var (rs_machine_dependent
, 8, 0,
4710 RELAX_ENCODE (4, 8, 0, 4, 0,
4711 mips_opts
.warn_about_macros
),
4712 offset_expr
.X_add_symbol
, 0, NULL
);
4714 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4717 macro_build (p
, &icnt
, &offset_expr
,
4718 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4719 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4722 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4724 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
4726 /* If this is a reference to an external symbol, and there
4727 is no constant, we want
4728 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4729 or if tempreg is PIC_CALL_REG
4730 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4731 For a local symbol, we want
4732 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4734 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4736 If we have a small constant, and this is a reference to
4737 an external symbol, we want
4738 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4740 addiu $tempreg,$tempreg,<constant>
4741 For a local symbol, we want the same instruction
4742 sequence, but we output a BFD_RELOC_LO16 reloc on the
4745 If we have a large constant, and this is a reference to
4746 an external symbol, we want
4747 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4748 lui $at,<hiconstant>
4749 addiu $at,$at,<loconstant>
4750 addu $tempreg,$tempreg,$at
4751 For a local symbol, we want the same instruction
4752 sequence, but we output a BFD_RELOC_LO16 reloc on the
4753 addiu instruction. */
4754 expr1
.X_add_number
= offset_expr
.X_add_number
;
4755 offset_expr
.X_add_number
= 0;
4757 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4758 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
4759 macro_build ((char *) NULL
, &icnt
, &offset_expr
, dbl
? "ld" : "lw",
4760 "t,o(b)", tempreg
, lw_reloc_type
, GP
);
4761 if (expr1
.X_add_number
== 0)
4769 /* We're going to put in an addu instruction using
4770 tempreg, so we may as well insert the nop right
4772 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4776 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4777 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4779 ? mips_opts
.warn_about_macros
4781 offset_expr
.X_add_symbol
, 0, NULL
);
4784 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4787 macro_build (p
, &icnt
, &expr1
,
4788 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4789 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4790 /* FIXME: If breg == 0, and the next instruction uses
4791 $tempreg, then if this variant case is used an extra
4792 nop will be generated. */
4794 else if (expr1
.X_add_number
>= -0x8000
4795 && expr1
.X_add_number
< 0x8000)
4797 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4799 macro_build ((char *) NULL
, &icnt
, &expr1
,
4800 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4801 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4802 frag_var (rs_machine_dependent
, 0, 0,
4803 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4804 offset_expr
.X_add_symbol
, 0, NULL
);
4810 /* If we are going to add in a base register, and the
4811 target register and the base register are the same,
4812 then we are using AT as a temporary register. Since
4813 we want to load the constant into AT, we add our
4814 current AT (from the global offset table) and the
4815 register into the register now, and pretend we were
4816 not using a base register. */
4821 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4823 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4824 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4825 "d,v,t", treg
, AT
, breg
);
4831 /* Set mips_optimize around the lui instruction to avoid
4832 inserting an unnecessary nop after the lw. */
4833 hold_mips_optimize
= mips_optimize
;
4835 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4836 mips_optimize
= hold_mips_optimize
;
4838 macro_build ((char *) NULL
, &icnt
, &expr1
,
4839 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4840 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4842 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4843 "d,v,t", tempreg
, tempreg
, AT
);
4844 frag_var (rs_machine_dependent
, 0, 0,
4845 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4846 offset_expr
.X_add_symbol
, 0, NULL
);
4850 else if (mips_pic
== SVR4_PIC
)
4853 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
4854 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
4856 /* This is the large GOT case. If this is a reference to an
4857 external symbol, and there is no constant, we want
4858 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4859 addu $tempreg,$tempreg,$gp
4860 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4861 or if tempreg is PIC_CALL_REG
4862 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4863 addu $tempreg,$tempreg,$gp
4864 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
4865 For a local symbol, we want
4866 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4868 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4870 If we have a small constant, and this is a reference to
4871 an external symbol, we want
4872 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4873 addu $tempreg,$tempreg,$gp
4874 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4876 addiu $tempreg,$tempreg,<constant>
4877 For a local symbol, we want
4878 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4880 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4882 If we have a large constant, and this is a reference to
4883 an external symbol, we want
4884 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4885 addu $tempreg,$tempreg,$gp
4886 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4887 lui $at,<hiconstant>
4888 addiu $at,$at,<loconstant>
4889 addu $tempreg,$tempreg,$at
4890 For a local symbol, we want
4891 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4892 lui $at,<hiconstant>
4893 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4894 addu $tempreg,$tempreg,$at
4896 expr1
.X_add_number
= offset_expr
.X_add_number
;
4897 offset_expr
.X_add_number
= 0;
4899 if (reg_needs_delay (GP
))
4903 if (expr1
.X_add_number
== 0 && tempreg
== PIC_CALL_REG
)
4905 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
4906 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
4908 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4909 tempreg
, lui_reloc_type
);
4910 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4911 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4912 "d,v,t", tempreg
, tempreg
, GP
);
4913 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4915 "t,o(b)", tempreg
, lw_reloc_type
, tempreg
);
4916 if (expr1
.X_add_number
== 0)
4924 /* We're going to put in an addu instruction using
4925 tempreg, so we may as well insert the nop right
4927 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4932 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4933 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4936 ? mips_opts
.warn_about_macros
4938 offset_expr
.X_add_symbol
, 0, NULL
);
4940 else if (expr1
.X_add_number
>= -0x8000
4941 && expr1
.X_add_number
< 0x8000)
4943 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4945 macro_build ((char *) NULL
, &icnt
, &expr1
,
4946 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4947 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4949 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4950 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4952 ? mips_opts
.warn_about_macros
4954 offset_expr
.X_add_symbol
, 0, NULL
);
4960 /* If we are going to add in a base register, and the
4961 target register and the base register are the same,
4962 then we are using AT as a temporary register. Since
4963 we want to load the constant into AT, we add our
4964 current AT (from the global offset table) and the
4965 register into the register now, and pretend we were
4966 not using a base register. */
4974 assert (tempreg
== AT
);
4975 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4977 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4978 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4979 "d,v,t", treg
, AT
, breg
);
4984 /* Set mips_optimize around the lui instruction to avoid
4985 inserting an unnecessary nop after the lw. */
4986 hold_mips_optimize
= mips_optimize
;
4988 macro_build_lui (NULL
, &icnt
, &expr1
, AT
);
4989 mips_optimize
= hold_mips_optimize
;
4991 macro_build ((char *) NULL
, &icnt
, &expr1
,
4992 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
4993 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4994 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4995 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
4996 "d,v,t", dreg
, dreg
, AT
);
4998 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4999 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
5002 ? mips_opts
.warn_about_macros
5004 offset_expr
.X_add_symbol
, 0, NULL
);
5011 /* This is needed because this instruction uses $gp, but
5012 the first instruction on the main stream does not. */
5013 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5016 macro_build (p
, &icnt
, &offset_expr
,
5018 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5020 if (expr1
.X_add_number
>= -0x8000
5021 && expr1
.X_add_number
< 0x8000)
5023 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5025 macro_build (p
, &icnt
, &expr1
,
5026 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5027 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5028 /* FIXME: If add_number is 0, and there was no base
5029 register, the external symbol case ended with a load,
5030 so if the symbol turns out to not be external, and
5031 the next instruction uses tempreg, an unnecessary nop
5032 will be inserted. */
5038 /* We must add in the base register now, as in the
5039 external symbol case. */
5040 assert (tempreg
== AT
);
5041 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5043 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5044 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5045 "d,v,t", treg
, AT
, breg
);
5048 /* We set breg to 0 because we have arranged to add
5049 it in in both cases. */
5053 macro_build_lui (p
, &icnt
, &expr1
, AT
);
5055 macro_build (p
, &icnt
, &expr1
,
5056 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5057 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
5059 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5060 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5061 "d,v,t", tempreg
, tempreg
, AT
);
5065 else if (mips_pic
== EMBEDDED_PIC
)
5068 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5070 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5071 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5072 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_GPREL16
);
5078 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5079 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5080 "d,v,t", treg
, tempreg
, breg
);
5088 /* The j instruction may not be used in PIC code, since it
5089 requires an absolute address. We convert it to a b
5091 if (mips_pic
== NO_PIC
)
5092 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
5094 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
5097 /* The jal instructions must be handled as macros because when
5098 generating PIC code they expand to multi-instruction
5099 sequences. Normally they are simple instructions. */
5104 if (mips_pic
== NO_PIC
5105 || mips_pic
== EMBEDDED_PIC
)
5106 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5108 else if (mips_pic
== SVR4_PIC
)
5110 if (sreg
!= PIC_CALL_REG
)
5111 as_warn (_("MIPS PIC call to register other than $25"));
5113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
5117 if (mips_cprestore_offset
< 0)
5118 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5121 if (! mips_frame_reg_valid
)
5123 as_warn (_("No .frame pseudo-op used in PIC code"));
5124 /* Quiet this warning. */
5125 mips_frame_reg_valid
= 1;
5127 if (! mips_cprestore_valid
)
5129 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5130 /* Quiet this warning. */
5131 mips_cprestore_valid
= 1;
5133 expr1
.X_add_number
= mips_cprestore_offset
;
5134 macro_build ((char *) NULL
, &icnt
, &expr1
,
5135 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5136 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5146 if (mips_pic
== NO_PIC
)
5147 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
5148 else if (mips_pic
== SVR4_PIC
)
5150 /* If this is a reference to an external symbol, and we are
5151 using a small GOT, we want
5152 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5156 lw $gp,cprestore($sp)
5157 The cprestore value is set using the .cprestore
5158 pseudo-op. If we are using a big GOT, we want
5159 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5161 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5165 lw $gp,cprestore($sp)
5166 If the symbol is not external, we want
5167 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5169 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5172 lw $gp,cprestore($sp) */
5176 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5177 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5178 "t,o(b)", PIC_CALL_REG
,
5179 (int) BFD_RELOC_MIPS_CALL16
, GP
);
5180 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5182 p
= frag_var (rs_machine_dependent
, 4, 0,
5183 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5184 offset_expr
.X_add_symbol
, 0, NULL
);
5190 if (reg_needs_delay (GP
))
5194 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5195 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
5196 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5197 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5198 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
5199 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5200 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5201 "t,o(b)", PIC_CALL_REG
,
5202 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
5203 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5205 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5206 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
5208 offset_expr
.X_add_symbol
, 0, NULL
);
5211 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5214 macro_build (p
, &icnt
, &offset_expr
,
5215 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5216 "t,o(b)", PIC_CALL_REG
,
5217 (int) BFD_RELOC_MIPS_GOT16
, GP
);
5219 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5222 macro_build (p
, &icnt
, &offset_expr
,
5223 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5224 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
5225 (int) BFD_RELOC_LO16
);
5226 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5227 "jalr", "s", PIC_CALL_REG
);
5230 if (mips_cprestore_offset
< 0)
5231 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5234 if (! mips_frame_reg_valid
)
5236 as_warn (_("No .frame pseudo-op used in PIC code"));
5237 /* Quiet this warning. */
5238 mips_frame_reg_valid
= 1;
5240 if (! mips_cprestore_valid
)
5242 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5243 /* Quiet this warning. */
5244 mips_cprestore_valid
= 1;
5246 if (mips_opts
.noreorder
)
5247 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5249 expr1
.X_add_number
= mips_cprestore_offset
;
5250 macro_build ((char *) NULL
, &icnt
, &expr1
,
5251 HAVE_32BIT_ADDRESSES
? "lw" : "ld", "t,o(b)",
5252 GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
5256 else if (mips_pic
== EMBEDDED_PIC
)
5258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
5259 /* The linker may expand the call to a longer sequence which
5260 uses $at, so we must break rather than return. */
5285 /* Itbl support may require additional care here. */
5290 /* Itbl support may require additional care here. */
5295 /* Itbl support may require additional care here. */
5300 /* Itbl support may require additional care here. */
5312 if (mips_arch
== CPU_R4650
)
5314 as_bad (_("opcode not supported on this processor"));
5318 /* Itbl support may require additional care here. */
5323 /* Itbl support may require additional care here. */
5328 /* Itbl support may require additional care here. */
5348 if (breg
== treg
|| coproc
|| lr
)
5370 /* Itbl support may require additional care here. */
5375 /* Itbl support may require additional care here. */
5380 /* Itbl support may require additional care here. */
5385 /* Itbl support may require additional care here. */
5401 if (mips_arch
== CPU_R4650
)
5403 as_bad (_("opcode not supported on this processor"));
5408 /* Itbl support may require additional care here. */
5412 /* Itbl support may require additional care here. */
5417 /* Itbl support may require additional care here. */
5429 /* Itbl support may require additional care here. */
5430 if (mask
== M_LWC1_AB
5431 || mask
== M_SWC1_AB
5432 || mask
== M_LDC1_AB
5433 || mask
== M_SDC1_AB
5442 /* For embedded PIC, we allow loads where the offset is calculated
5443 by subtracting a symbol in the current segment from an unknown
5444 symbol, relative to a base register, e.g.:
5445 <op> $treg, <sym>-<localsym>($breg)
5446 This is used by the compiler for switch statements. */
5447 if (mips_pic
== EMBEDDED_PIC
5448 && offset_expr
.X_op
== O_subtract
5449 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5450 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5451 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5453 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5457 && (offset_expr
.X_add_number
== 0
5458 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5460 /* For this case, we output the instructions:
5461 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5462 addiu $tempreg,$tempreg,$breg
5463 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5464 If the relocation would fit entirely in 16 bits, it would be
5466 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5467 instead, but that seems quite difficult. */
5468 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5469 tempreg
, (int) BFD_RELOC_PCREL_HI16_S
);
5470 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5471 ((bfd_arch_bits_per_address (stdoutput
) == 32
5472 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5473 ? "addu" : "daddu"),
5474 "d,v,t", tempreg
, tempreg
, breg
);
5475 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5476 (int) BFD_RELOC_PCREL_LO16
, tempreg
);
5482 if (offset_expr
.X_op
!= O_constant
5483 && offset_expr
.X_op
!= O_symbol
)
5485 as_bad (_("expression too complex"));
5486 offset_expr
.X_op
= O_constant
;
5489 /* A constant expression in PIC code can be handled just as it
5490 is in non PIC code. */
5491 if (mips_pic
== NO_PIC
5492 || offset_expr
.X_op
== O_constant
)
5494 /* If this is a reference to a GP relative symbol, and there
5495 is no base register, we want
5496 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5497 Otherwise, if there is no base register, we want
5498 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5499 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5500 If we have a constant, we need two instructions anyhow,
5501 so we always use the latter form.
5503 If we have a base register, and this is a reference to a
5504 GP relative symbol, we want
5505 addu $tempreg,$breg,$gp
5506 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5508 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5509 addu $tempreg,$tempreg,$breg
5510 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5511 With a constant we always use the latter case.
5513 With 64bit address space and no base register and $at usable,
5515 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5516 lui $at,<sym> (BFD_RELOC_HI16_S)
5517 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5520 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5521 If we have a base register, we want
5522 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5523 lui $at,<sym> (BFD_RELOC_HI16_S)
5524 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5528 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5530 Without $at we can't generate the optimal path for superscalar
5531 processors here since this would require two temporary registers.
5532 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5533 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5535 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5537 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5538 If we have a base register, we want
5539 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5540 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5542 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5544 daddu $tempreg,$tempreg,$breg
5545 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5547 if (HAVE_64BIT_ADDRESSES
)
5551 /* We don't do GP optimization for now because RELAX_ENCODE can't
5552 hold the data for such large chunks. */
5556 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5557 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5558 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5559 AT
, (int) BFD_RELOC_HI16_S
);
5560 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5561 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5563 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5564 "d,v,t", AT
, AT
, breg
);
5565 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll32",
5566 "d,w,<", tempreg
, tempreg
, 0);
5567 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5568 "d,v,t", tempreg
, tempreg
, AT
);
5569 macro_build (p
, &icnt
, &offset_expr
, s
,
5570 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5575 macro_build (p
, &icnt
, &offset_expr
, "lui", "t,u",
5576 tempreg
, (int) BFD_RELOC_MIPS_HIGHEST
);
5577 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5578 tempreg
, tempreg
, (int) BFD_RELOC_MIPS_HIGHER
);
5579 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5580 "d,w,<", tempreg
, tempreg
, 16);
5581 macro_build (p
, &icnt
, &offset_expr
, "daddiu", "t,r,j",
5582 tempreg
, tempreg
, (int) BFD_RELOC_HI16_S
);
5583 macro_build (p
, &icnt
, (expressionS
*) NULL
, "dsll",
5584 "d,w,<", tempreg
, tempreg
, 16);
5586 macro_build (p
, &icnt
, (expressionS
*) NULL
, "daddu",
5587 "d,v,t", tempreg
, tempreg
, breg
);
5588 macro_build (p
, &icnt
, &offset_expr
, s
,
5589 fmt
, treg
, (int) BFD_RELOC_LO16
, tempreg
);
5597 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5598 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5603 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5604 treg
, (int) BFD_RELOC_GPREL16
, GP
);
5605 p
= frag_var (rs_machine_dependent
, 8, 0,
5606 RELAX_ENCODE (4, 8, 0, 4, 0,
5607 (mips_opts
.warn_about_macros
5609 && mips_opts
.noat
))),
5610 offset_expr
.X_add_symbol
, 0, NULL
);
5613 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5616 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5617 (int) BFD_RELOC_LO16
, tempreg
);
5621 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
5622 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5627 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5628 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5629 "d,v,t", tempreg
, breg
, GP
);
5630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5631 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5632 p
= frag_var (rs_machine_dependent
, 12, 0,
5633 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5634 offset_expr
.X_add_symbol
, 0, NULL
);
5636 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5639 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5640 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5641 "d,v,t", tempreg
, tempreg
, breg
);
5644 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5645 (int) BFD_RELOC_LO16
, tempreg
);
5648 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5650 /* If this is a reference to an external symbol, we want
5651 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5653 <op> $treg,0($tempreg)
5655 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5657 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5658 <op> $treg,0($tempreg)
5659 If there is a base register, we add it to $tempreg before
5660 the <op>. If there is a constant, we stick it in the
5661 <op> instruction. We don't handle constants larger than
5662 16 bits, because we have no way to load the upper 16 bits
5663 (actually, we could handle them for the subset of cases
5664 in which we are not using $at). */
5665 assert (offset_expr
.X_op
== O_symbol
);
5666 expr1
.X_add_number
= offset_expr
.X_add_number
;
5667 offset_expr
.X_add_number
= 0;
5668 if (expr1
.X_add_number
< -0x8000
5669 || expr1
.X_add_number
>= 0x8000)
5670 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5672 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5673 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5674 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5676 p
= frag_var (rs_machine_dependent
, 4, 0,
5677 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5678 offset_expr
.X_add_symbol
, 0, NULL
);
5679 macro_build (p
, &icnt
, &offset_expr
,
5680 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5681 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5683 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5684 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5685 "d,v,t", tempreg
, tempreg
, breg
);
5686 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5687 (int) BFD_RELOC_LO16
, tempreg
);
5689 else if (mips_pic
== SVR4_PIC
)
5693 /* If this is a reference to an external symbol, we want
5694 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5695 addu $tempreg,$tempreg,$gp
5696 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5697 <op> $treg,0($tempreg)
5699 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5701 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5702 <op> $treg,0($tempreg)
5703 If there is a base register, we add it to $tempreg before
5704 the <op>. If there is a constant, we stick it in the
5705 <op> instruction. We don't handle constants larger than
5706 16 bits, because we have no way to load the upper 16 bits
5707 (actually, we could handle them for the subset of cases
5708 in which we are not using $at). */
5709 assert (offset_expr
.X_op
== O_symbol
);
5710 expr1
.X_add_number
= offset_expr
.X_add_number
;
5711 offset_expr
.X_add_number
= 0;
5712 if (expr1
.X_add_number
< -0x8000
5713 || expr1
.X_add_number
>= 0x8000)
5714 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5715 if (reg_needs_delay (GP
))
5720 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5721 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5722 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5723 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5724 "d,v,t", tempreg
, tempreg
, GP
);
5725 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5726 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5727 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5729 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5730 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5731 offset_expr
.X_add_symbol
, 0, NULL
);
5734 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5737 macro_build (p
, &icnt
, &offset_expr
,
5738 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5739 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5741 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5743 macro_build (p
, &icnt
, &offset_expr
,
5744 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5745 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5748 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5749 "d,v,t", tempreg
, tempreg
, breg
);
5750 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5751 (int) BFD_RELOC_LO16
, tempreg
);
5753 else if (mips_pic
== EMBEDDED_PIC
)
5755 /* If there is no base register, we want
5756 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5757 If there is a base register, we want
5758 addu $tempreg,$breg,$gp
5759 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5761 assert (offset_expr
.X_op
== O_symbol
);
5764 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5765 treg
, (int) BFD_RELOC_GPREL16
, GP
);
5770 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5771 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
5772 "d,v,t", tempreg
, breg
, GP
);
5773 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5774 treg
, (int) BFD_RELOC_GPREL16
, tempreg
);
5787 load_register (&icnt
, treg
, &imm_expr
, 0);
5791 load_register (&icnt
, treg
, &imm_expr
, 1);
5795 if (imm_expr
.X_op
== O_constant
)
5797 load_register (&icnt
, AT
, &imm_expr
, 0);
5798 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5799 "mtc1", "t,G", AT
, treg
);
5804 assert (offset_expr
.X_op
== O_symbol
5805 && strcmp (segment_name (S_GET_SEGMENT
5806 (offset_expr
.X_add_symbol
)),
5808 && offset_expr
.X_add_number
== 0);
5809 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5810 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5815 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
5816 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
5817 order 32 bits of the value and the low order 32 bits are either
5818 zero or in OFFSET_EXPR. */
5819 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5821 if (HAVE_64BIT_GPRS
)
5822 load_register (&icnt
, treg
, &imm_expr
, 1);
5827 if (target_big_endian
)
5839 load_register (&icnt
, hreg
, &imm_expr
, 0);
5842 if (offset_expr
.X_op
== O_absent
)
5843 move_register (&icnt
, lreg
, 0);
5846 assert (offset_expr
.X_op
== O_constant
);
5847 load_register (&icnt
, lreg
, &offset_expr
, 0);
5854 /* We know that sym is in the .rdata section. First we get the
5855 upper 16 bits of the address. */
5856 if (mips_pic
== NO_PIC
)
5858 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
5860 else if (mips_pic
== SVR4_PIC
)
5862 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5863 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5864 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5866 else if (mips_pic
== EMBEDDED_PIC
)
5868 /* For embedded PIC we pick up the entire address off $gp in
5869 a single instruction. */
5870 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5871 HAVE_32BIT_ADDRESSES
? "addiu" : "daddiu",
5872 "t,r,j", AT
, GP
, (int) BFD_RELOC_GPREL16
);
5873 offset_expr
.X_op
= O_constant
;
5874 offset_expr
.X_add_number
= 0;
5879 /* Now we load the register(s). */
5880 if (HAVE_64BIT_GPRS
)
5881 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5882 treg
, (int) BFD_RELOC_LO16
, AT
);
5885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5886 treg
, (int) BFD_RELOC_LO16
, AT
);
5889 /* FIXME: How in the world do we deal with the possible
5891 offset_expr
.X_add_number
+= 4;
5892 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5893 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5897 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5898 does not become a variant frag. */
5899 frag_wane (frag_now
);
5905 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
5906 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
5907 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
5908 the value and the low order 32 bits are either zero or in
5910 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5912 load_register (&icnt
, AT
, &imm_expr
, HAVE_64BIT_FPRS
);
5913 if (HAVE_64BIT_FPRS
)
5915 assert (HAVE_64BIT_GPRS
);
5916 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5917 "dmtc1", "t,S", AT
, treg
);
5921 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5922 "mtc1", "t,G", AT
, treg
+ 1);
5923 if (offset_expr
.X_op
== O_absent
)
5924 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5925 "mtc1", "t,G", 0, treg
);
5928 assert (offset_expr
.X_op
== O_constant
);
5929 load_register (&icnt
, AT
, &offset_expr
, 0);
5930 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5931 "mtc1", "t,G", AT
, treg
);
5937 assert (offset_expr
.X_op
== O_symbol
5938 && offset_expr
.X_add_number
== 0);
5939 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5940 if (strcmp (s
, ".lit8") == 0)
5942 if (mips_opts
.isa
!= ISA_MIPS1
)
5944 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5945 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5949 r
= BFD_RELOC_MIPS_LITERAL
;
5954 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5955 if (mips_pic
== SVR4_PIC
)
5956 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5957 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
5958 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5961 /* FIXME: This won't work for a 64 bit address. */
5962 macro_build_lui (NULL
, &icnt
, &offset_expr
, AT
);
5965 if (mips_opts
.isa
!= ISA_MIPS1
)
5967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5968 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5970 /* To avoid confusion in tc_gen_reloc, we must ensure
5971 that this does not become a variant frag. */
5972 frag_wane (frag_now
);
5983 if (mips_arch
== CPU_R4650
)
5985 as_bad (_("opcode not supported on this processor"));
5988 /* Even on a big endian machine $fn comes before $fn+1. We have
5989 to adjust when loading from memory. */
5992 assert (mips_opts
.isa
== ISA_MIPS1
);
5993 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5994 target_big_endian
? treg
+ 1 : treg
,
5996 /* FIXME: A possible overflow which I don't know how to deal
5998 offset_expr
.X_add_number
+= 4;
5999 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
6000 target_big_endian
? treg
: treg
+ 1,
6003 /* To avoid confusion in tc_gen_reloc, we must ensure that this
6004 does not become a variant frag. */
6005 frag_wane (frag_now
);
6014 * The MIPS assembler seems to check for X_add_number not
6015 * being double aligned and generating:
6018 * addiu at,at,%lo(foo+1)
6021 * But, the resulting address is the same after relocation so why
6022 * generate the extra instruction?
6024 if (mips_arch
== CPU_R4650
)
6026 as_bad (_("opcode not supported on this processor"));
6029 /* Itbl support may require additional care here. */
6031 if (mips_opts
.isa
!= ISA_MIPS1
)
6042 if (mips_arch
== CPU_R4650
)
6044 as_bad (_("opcode not supported on this processor"));
6048 if (mips_opts
.isa
!= ISA_MIPS1
)
6056 /* Itbl support may require additional care here. */
6061 if (HAVE_64BIT_GPRS
)
6072 if (HAVE_64BIT_GPRS
)
6082 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6083 loads for the case of doing a pair of loads to simulate an 'ld'.
6084 This is not currently done by the compiler, and assembly coders
6085 writing embedded-pic code can cope. */
6087 if (offset_expr
.X_op
!= O_symbol
6088 && offset_expr
.X_op
!= O_constant
)
6090 as_bad (_("expression too complex"));
6091 offset_expr
.X_op
= O_constant
;
6094 /* Even on a big endian machine $fn comes before $fn+1. We have
6095 to adjust when loading from memory. We set coproc if we must
6096 load $fn+1 first. */
6097 /* Itbl support may require additional care here. */
6098 if (! target_big_endian
)
6101 if (mips_pic
== NO_PIC
6102 || offset_expr
.X_op
== O_constant
)
6104 /* If this is a reference to a GP relative symbol, we want
6105 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6106 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6107 If we have a base register, we use this
6109 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6110 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6111 If this is not a GP relative symbol, we want
6112 lui $at,<sym> (BFD_RELOC_HI16_S)
6113 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6114 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6115 If there is a base register, we add it to $at after the
6116 lui instruction. If there is a constant, we always use
6118 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6119 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6139 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6140 "d,v,t", AT
, breg
, GP
);
6146 /* Itbl support may require additional care here. */
6147 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6148 coproc
? treg
+ 1 : treg
,
6149 (int) BFD_RELOC_GPREL16
, tempreg
);
6150 offset_expr
.X_add_number
+= 4;
6152 /* Set mips_optimize to 2 to avoid inserting an
6154 hold_mips_optimize
= mips_optimize
;
6156 /* Itbl support may require additional care here. */
6157 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6158 coproc
? treg
: treg
+ 1,
6159 (int) BFD_RELOC_GPREL16
, tempreg
);
6160 mips_optimize
= hold_mips_optimize
;
6162 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
6163 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
6164 used_at
&& mips_opts
.noat
),
6165 offset_expr
.X_add_symbol
, 0, NULL
);
6167 /* We just generated two relocs. When tc_gen_reloc
6168 handles this case, it will skip the first reloc and
6169 handle the second. The second reloc already has an
6170 extra addend of 4, which we added above. We must
6171 subtract it out, and then subtract another 4 to make
6172 the first reloc come out right. The second reloc
6173 will come out right because we are going to add 4 to
6174 offset_expr when we build its instruction below.
6176 If we have a symbol, then we don't want to include
6177 the offset, because it will wind up being included
6178 when we generate the reloc. */
6180 if (offset_expr
.X_op
== O_constant
)
6181 offset_expr
.X_add_number
-= 8;
6184 offset_expr
.X_add_number
= -4;
6185 offset_expr
.X_op
= O_constant
;
6188 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
6193 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6194 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6195 "d,v,t", AT
, breg
, AT
);
6199 /* Itbl support may require additional care here. */
6200 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6201 coproc
? treg
+ 1 : treg
,
6202 (int) BFD_RELOC_LO16
, AT
);
6205 /* FIXME: How do we handle overflow here? */
6206 offset_expr
.X_add_number
+= 4;
6207 /* Itbl support may require additional care here. */
6208 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
6209 coproc
? treg
: treg
+ 1,
6210 (int) BFD_RELOC_LO16
, AT
);
6212 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6216 /* If this is a reference to an external symbol, we want
6217 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6222 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6224 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6225 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6226 If there is a base register we add it to $at before the
6227 lwc1 instructions. If there is a constant we include it
6228 in the lwc1 instructions. */
6230 expr1
.X_add_number
= offset_expr
.X_add_number
;
6231 offset_expr
.X_add_number
= 0;
6232 if (expr1
.X_add_number
< -0x8000
6233 || expr1
.X_add_number
>= 0x8000 - 4)
6234 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6239 frag_grow (24 + off
);
6240 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6241 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6242 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6243 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6245 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6246 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6247 "d,v,t", AT
, breg
, AT
);
6248 /* Itbl support may require additional care here. */
6249 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6250 coproc
? treg
+ 1 : treg
,
6251 (int) BFD_RELOC_LO16
, AT
);
6252 expr1
.X_add_number
+= 4;
6254 /* Set mips_optimize to 2 to avoid inserting an undesired
6256 hold_mips_optimize
= mips_optimize
;
6258 /* Itbl support may require additional care here. */
6259 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6260 coproc
? treg
: treg
+ 1,
6261 (int) BFD_RELOC_LO16
, AT
);
6262 mips_optimize
= hold_mips_optimize
;
6264 (void) frag_var (rs_machine_dependent
, 0, 0,
6265 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
6266 offset_expr
.X_add_symbol
, 0, NULL
);
6268 else if (mips_pic
== SVR4_PIC
)
6272 /* If this is a reference to an external symbol, we want
6273 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6275 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6280 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6282 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6283 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6284 If there is a base register we add it to $at before the
6285 lwc1 instructions. If there is a constant we include it
6286 in the lwc1 instructions. */
6288 expr1
.X_add_number
= offset_expr
.X_add_number
;
6289 offset_expr
.X_add_number
= 0;
6290 if (expr1
.X_add_number
< -0x8000
6291 || expr1
.X_add_number
>= 0x8000 - 4)
6292 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6293 if (reg_needs_delay (GP
))
6302 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
6303 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
6304 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6305 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6306 "d,v,t", AT
, AT
, GP
);
6307 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
6308 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6309 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
6310 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
6312 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6313 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6314 "d,v,t", AT
, breg
, AT
);
6315 /* Itbl support may require additional care here. */
6316 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6317 coproc
? treg
+ 1 : treg
,
6318 (int) BFD_RELOC_LO16
, AT
);
6319 expr1
.X_add_number
+= 4;
6321 /* Set mips_optimize to 2 to avoid inserting an undesired
6323 hold_mips_optimize
= mips_optimize
;
6325 /* Itbl support may require additional care here. */
6326 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
6327 coproc
? treg
: treg
+ 1,
6328 (int) BFD_RELOC_LO16
, AT
);
6329 mips_optimize
= hold_mips_optimize
;
6330 expr1
.X_add_number
-= 4;
6332 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
6333 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
6334 8 + gpdel
+ off
, 1, 0),
6335 offset_expr
.X_add_symbol
, 0, NULL
);
6338 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6341 macro_build (p
, &icnt
, &offset_expr
,
6342 HAVE_32BIT_ADDRESSES
? "lw" : "ld",
6343 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
6345 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
6349 macro_build (p
, &icnt
, (expressionS
*) NULL
,
6350 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6351 "d,v,t", AT
, breg
, AT
);
6354 /* Itbl support may require additional care here. */
6355 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6356 coproc
? treg
+ 1 : treg
,
6357 (int) BFD_RELOC_LO16
, AT
);
6359 expr1
.X_add_number
+= 4;
6361 /* Set mips_optimize to 2 to avoid inserting an undesired
6363 hold_mips_optimize
= mips_optimize
;
6365 /* Itbl support may require additional care here. */
6366 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
6367 coproc
? treg
: treg
+ 1,
6368 (int) BFD_RELOC_LO16
, AT
);
6369 mips_optimize
= hold_mips_optimize
;
6371 else if (mips_pic
== EMBEDDED_PIC
)
6373 /* If there is no base register, we use
6374 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6375 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6376 If we have a base register, we use
6378 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6379 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6388 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6389 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
6390 "d,v,t", AT
, breg
, GP
);
6395 /* Itbl support may require additional care here. */
6396 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6397 coproc
? treg
+ 1 : treg
,
6398 (int) BFD_RELOC_GPREL16
, tempreg
);
6399 offset_expr
.X_add_number
+= 4;
6400 /* Itbl support may require additional care here. */
6401 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
6402 coproc
? treg
: treg
+ 1,
6403 (int) BFD_RELOC_GPREL16
, tempreg
);
6419 assert (HAVE_32BIT_ADDRESSES
);
6420 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6421 (int) BFD_RELOC_LO16
, breg
);
6422 offset_expr
.X_add_number
+= 4;
6423 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6424 (int) BFD_RELOC_LO16
, breg
);
6427 /* New code added to support COPZ instructions.
6428 This code builds table entries out of the macros in mip_opcodes.
6429 R4000 uses interlocks to handle coproc delays.
6430 Other chips (like the R3000) require nops to be inserted for delays.
6432 FIXME: Currently, we require that the user handle delays.
6433 In order to fill delay slots for non-interlocked chips,
6434 we must have a way to specify delays based on the coprocessor.
6435 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6436 What are the side-effects of the cop instruction?
6437 What cache support might we have and what are its effects?
6438 Both coprocessor & memory require delays. how long???
6439 What registers are read/set/modified?
6441 If an itbl is provided to interpret cop instructions,
6442 this knowledge can be encoded in the itbl spec. */
6456 /* For now we just do C (same as Cz). The parameter will be
6457 stored in insn_opcode by mips_ip. */
6458 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6463 move_register (&icnt
, dreg
, sreg
);
6466 #ifdef LOSING_COMPILER
6468 /* Try and see if this is a new itbl instruction.
6469 This code builds table entries out of the macros in mip_opcodes.
6470 FIXME: For now we just assemble the expression and pass it's
6471 value along as a 32-bit immediate.
6472 We may want to have the assembler assemble this value,
6473 so that we gain the assembler's knowledge of delay slots,
6475 Would it be more efficient to use mask (id) here? */
6476 if (itbl_have_entries
6477 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6479 s
= ip
->insn_mo
->name
;
6481 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6482 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6489 as_warn (_("Macro used $at after \".set noat\""));
6494 struct mips_cl_insn
*ip
;
6496 register int treg
, sreg
, dreg
, breg
;
6512 bfd_reloc_code_real_type r
;
6515 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6516 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6517 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6518 mask
= ip
->insn_mo
->mask
;
6520 expr1
.X_op
= O_constant
;
6521 expr1
.X_op_symbol
= NULL
;
6522 expr1
.X_add_symbol
= NULL
;
6523 expr1
.X_add_number
= 1;
6527 #endif /* LOSING_COMPILER */
6532 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6533 dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6534 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6541 /* The MIPS assembler some times generates shifts and adds. I'm
6542 not trying to be that fancy. GCC should do this for us
6544 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6545 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6546 dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6547 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6561 mips_emit_delays (true);
6562 ++mips_opts
.noreorder
;
6563 mips_any_noreorder
= 1;
6565 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6566 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6567 dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6568 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6570 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6571 dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, 31);
6572 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6575 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6579 expr1
.X_add_number
= 8;
6580 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
,
6582 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6584 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6587 --mips_opts
.noreorder
;
6588 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d", dreg
);
6601 mips_emit_delays (true);
6602 ++mips_opts
.noreorder
;
6603 mips_any_noreorder
= 1;
6605 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6606 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6607 dbl
? "dmultu" : "multu",
6608 "s,t", sreg
, imm
? AT
: treg
);
6609 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mfhi", "d",
6611 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "d",
6614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "tne", "s,t",
6618 expr1
.X_add_number
= 8;
6619 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6620 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "",
6622 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
6625 --mips_opts
.noreorder
;
6629 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6630 "d,v,t", AT
, 0, treg
);
6631 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6632 "d,t,s", AT
, sreg
, AT
);
6633 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6634 "d,t,s", dreg
, sreg
, treg
);
6635 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6636 "d,v,t", dreg
, dreg
, AT
);
6640 if (imm_expr
.X_op
!= O_constant
)
6641 as_bad (_("rotate count too large"));
6642 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6643 AT
, sreg
, (int) (imm_expr
.X_add_number
& 0x1f));
6644 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
6645 dreg
, sreg
, (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6646 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6651 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "subu",
6652 "d,v,t", AT
, 0, treg
);
6653 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sllv",
6654 "d,t,s", AT
, sreg
, AT
);
6655 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srlv",
6656 "d,t,s", dreg
, sreg
, treg
);
6657 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or",
6658 "d,v,t", dreg
, dreg
, AT
);
6662 if (imm_expr
.X_op
!= O_constant
)
6663 as_bad (_("rotate count too large"));
6664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
6665 AT
, sreg
, (int) (imm_expr
.X_add_number
& 0x1f));
6666 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
6667 dreg
, sreg
, (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6668 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
6673 if (mips_arch
== CPU_R4650
)
6675 as_bad (_("opcode not supported on this processor"));
6678 assert (mips_opts
.isa
== ISA_MIPS1
);
6679 /* Even on a big endian machine $fn comes before $fn+1. We have
6680 to adjust when storing to memory. */
6681 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6682 target_big_endian
? treg
+ 1 : treg
,
6683 (int) BFD_RELOC_LO16
, breg
);
6684 offset_expr
.X_add_number
+= 4;
6685 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6686 target_big_endian
? treg
: treg
+ 1,
6687 (int) BFD_RELOC_LO16
, breg
);
6692 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6693 treg
, (int) BFD_RELOC_LO16
);
6695 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6696 sreg
, (int) BFD_RELOC_LO16
);
6699 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6700 "d,v,t", dreg
, sreg
, treg
);
6701 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6702 dreg
, (int) BFD_RELOC_LO16
);
6707 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6709 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6710 sreg
, (int) BFD_RELOC_LO16
);
6715 as_warn (_("Instruction %s: result is always false"),
6717 move_register (&icnt
, dreg
, 0);
6720 if (imm_expr
.X_op
== O_constant
6721 && imm_expr
.X_add_number
>= 0
6722 && imm_expr
.X_add_number
< 0x10000)
6724 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6725 sreg
, (int) BFD_RELOC_LO16
);
6728 else if (imm_expr
.X_op
== O_constant
6729 && imm_expr
.X_add_number
> -0x8000
6730 && imm_expr
.X_add_number
< 0)
6732 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6733 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6734 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6735 "t,r,j", dreg
, sreg
,
6736 (int) BFD_RELOC_LO16
);
6741 load_register (&icnt
, AT
, &imm_expr
, 0);
6742 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6743 "d,v,t", dreg
, sreg
, AT
);
6746 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6747 (int) BFD_RELOC_LO16
);
6752 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6758 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6760 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6761 (int) BFD_RELOC_LO16
);
6764 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6766 if (imm_expr
.X_op
== O_constant
6767 && imm_expr
.X_add_number
>= -0x8000
6768 && imm_expr
.X_add_number
< 0x8000)
6770 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6771 mask
== M_SGE_I
? "slti" : "sltiu",
6772 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6777 load_register (&icnt
, AT
, &imm_expr
, 0);
6778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6779 mask
== M_SGE_I
? "slt" : "sltu", "d,v,t", dreg
, sreg
,
6783 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6784 (int) BFD_RELOC_LO16
);
6789 case M_SGT
: /* sreg > treg <==> treg < sreg */
6795 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6799 case M_SGT_I
: /* sreg > I <==> I < sreg */
6805 load_register (&icnt
, AT
, &imm_expr
, 0);
6806 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6810 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6816 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6818 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6819 (int) BFD_RELOC_LO16
);
6822 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6828 load_register (&icnt
, AT
, &imm_expr
, 0);
6829 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "d,v,t",
6831 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6832 (int) BFD_RELOC_LO16
);
6836 if (imm_expr
.X_op
== O_constant
6837 && imm_expr
.X_add_number
>= -0x8000
6838 && imm_expr
.X_add_number
< 0x8000)
6840 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6841 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6844 load_register (&icnt
, AT
, &imm_expr
, 0);
6845 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "slt", "d,v,t",
6850 if (imm_expr
.X_op
== O_constant
6851 && imm_expr
.X_add_number
>= -0x8000
6852 && imm_expr
.X_add_number
< 0x8000)
6854 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6855 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6858 load_register (&icnt
, AT
, &imm_expr
, 0);
6859 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6860 "d,v,t", dreg
, sreg
, AT
);
6865 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6866 "d,v,t", dreg
, 0, treg
);
6868 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6869 "d,v,t", dreg
, 0, sreg
);
6872 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6873 "d,v,t", dreg
, sreg
, treg
);
6874 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6875 "d,v,t", dreg
, 0, dreg
);
6880 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6882 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6883 "d,v,t", dreg
, 0, sreg
);
6888 as_warn (_("Instruction %s: result is always true"),
6890 macro_build ((char *) NULL
, &icnt
, &expr1
,
6891 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6892 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6895 if (imm_expr
.X_op
== O_constant
6896 && imm_expr
.X_add_number
>= 0
6897 && imm_expr
.X_add_number
< 0x10000)
6899 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6900 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6903 else if (imm_expr
.X_op
== O_constant
6904 && imm_expr
.X_add_number
> -0x8000
6905 && imm_expr
.X_add_number
< 0)
6907 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6908 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6909 HAVE_32BIT_GPRS
? "addiu" : "daddiu",
6910 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6915 load_register (&icnt
, AT
, &imm_expr
, 0);
6916 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "xor",
6917 "d,v,t", dreg
, sreg
, AT
);
6920 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sltu",
6921 "d,v,t", dreg
, 0, dreg
);
6929 if (imm_expr
.X_op
== O_constant
6930 && imm_expr
.X_add_number
> -0x8000
6931 && imm_expr
.X_add_number
<= 0x8000)
6933 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6934 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6935 dbl
? "daddi" : "addi",
6936 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6939 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6940 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6941 dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
6947 if (imm_expr
.X_op
== O_constant
6948 && imm_expr
.X_add_number
> -0x8000
6949 && imm_expr
.X_add_number
<= 0x8000)
6951 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6952 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6953 dbl
? "daddiu" : "addiu",
6954 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6957 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6958 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6959 dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
6980 load_register (&icnt
, AT
, &imm_expr
, 0);
6981 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "s,t", sreg
,
6987 assert (mips_opts
.isa
== ISA_MIPS1
);
6988 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6989 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6992 * Is the double cfc1 instruction a bug in the mips assembler;
6993 * or is there a reason for it?
6995 mips_emit_delays (true);
6996 ++mips_opts
.noreorder
;
6997 mips_any_noreorder
= 1;
6998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7000 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "cfc1", "t,G",
7002 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7003 expr1
.X_add_number
= 3;
7004 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
7005 (int) BFD_RELOC_LO16
);
7006 expr1
.X_add_number
= 2;
7007 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
7008 (int) BFD_RELOC_LO16
);
7009 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7011 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7012 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7013 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
7014 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "ctc1", "t,G",
7016 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
7017 --mips_opts
.noreorder
;
7026 if (offset_expr
.X_add_number
>= 0x7fff)
7027 as_bad (_("operand overflow"));
7028 /* avoid load delay */
7029 if (! target_big_endian
)
7030 offset_expr
.X_add_number
+= 1;
7031 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7032 (int) BFD_RELOC_LO16
, breg
);
7033 if (! target_big_endian
)
7034 offset_expr
.X_add_number
-= 1;
7036 offset_expr
.X_add_number
+= 1;
7037 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
7038 (int) BFD_RELOC_LO16
, breg
);
7039 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7055 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7056 as_bad (_("operand overflow"));
7057 if (! target_big_endian
)
7058 offset_expr
.X_add_number
+= off
;
7059 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7060 (int) BFD_RELOC_LO16
, breg
);
7061 if (! target_big_endian
)
7062 offset_expr
.X_add_number
-= off
;
7064 offset_expr
.X_add_number
+= off
;
7065 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7066 (int) BFD_RELOC_LO16
, breg
);
7080 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7083 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7084 "d,v,t", AT
, AT
, breg
);
7085 if (! target_big_endian
)
7086 expr1
.X_add_number
= off
;
7088 expr1
.X_add_number
= 0;
7089 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7090 (int) BFD_RELOC_LO16
, AT
);
7091 if (! target_big_endian
)
7092 expr1
.X_add_number
= 0;
7094 expr1
.X_add_number
= off
;
7095 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7096 (int) BFD_RELOC_LO16
, AT
);
7102 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7104 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7105 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7106 "d,v,t", AT
, AT
, breg
);
7107 if (target_big_endian
)
7108 expr1
.X_add_number
= 0;
7109 macro_build ((char *) NULL
, &icnt
, &expr1
,
7110 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
7111 (int) BFD_RELOC_LO16
, AT
);
7112 if (target_big_endian
)
7113 expr1
.X_add_number
= 1;
7115 expr1
.X_add_number
= 0;
7116 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7117 (int) BFD_RELOC_LO16
, AT
);
7118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7125 if (offset_expr
.X_add_number
>= 0x7fff)
7126 as_bad (_("operand overflow"));
7127 if (target_big_endian
)
7128 offset_expr
.X_add_number
+= 1;
7129 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
7130 (int) BFD_RELOC_LO16
, breg
);
7131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7133 if (target_big_endian
)
7134 offset_expr
.X_add_number
-= 1;
7136 offset_expr
.X_add_number
+= 1;
7137 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
7138 (int) BFD_RELOC_LO16
, breg
);
7151 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7152 as_bad (_("operand overflow"));
7153 if (! target_big_endian
)
7154 offset_expr
.X_add_number
+= off
;
7155 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
7156 (int) BFD_RELOC_LO16
, breg
);
7157 if (! target_big_endian
)
7158 offset_expr
.X_add_number
-= off
;
7160 offset_expr
.X_add_number
+= off
;
7161 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
7162 (int) BFD_RELOC_LO16
, breg
);
7176 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7178 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7179 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7180 "d,v,t", AT
, AT
, breg
);
7181 if (! target_big_endian
)
7182 expr1
.X_add_number
= off
;
7184 expr1
.X_add_number
= 0;
7185 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
7186 (int) BFD_RELOC_LO16
, AT
);
7187 if (! target_big_endian
)
7188 expr1
.X_add_number
= 0;
7190 expr1
.X_add_number
= off
;
7191 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
7192 (int) BFD_RELOC_LO16
, AT
);
7197 load_address (&icnt
, AT
, &offset_expr
, HAVE_64BIT_ADDRESSES
, &used_at
);
7199 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7200 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
7201 "d,v,t", AT
, AT
, breg
);
7202 if (! target_big_endian
)
7203 expr1
.X_add_number
= 0;
7204 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7205 (int) BFD_RELOC_LO16
, AT
);
7206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "srl", "d,w,<",
7208 if (! target_big_endian
)
7209 expr1
.X_add_number
= 1;
7211 expr1
.X_add_number
= 0;
7212 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
7213 (int) BFD_RELOC_LO16
, AT
);
7214 if (! target_big_endian
)
7215 expr1
.X_add_number
= 0;
7217 expr1
.X_add_number
= 1;
7218 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
7219 (int) BFD_RELOC_LO16
, AT
);
7220 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "sll", "d,w,<",
7222 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "or", "d,v,t",
7227 /* FIXME: Check if this is one of the itbl macros, since they
7228 are added dynamically. */
7229 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7233 as_warn (_("Macro used $at after \".set noat\""));
7236 /* Implement macros in mips16 mode. */
7240 struct mips_cl_insn
*ip
;
7243 int xreg
, yreg
, zreg
, tmp
;
7247 const char *s
, *s2
, *s3
;
7249 mask
= ip
->insn_mo
->mask
;
7251 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7252 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7253 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7257 expr1
.X_op
= O_constant
;
7258 expr1
.X_op_symbol
= NULL
;
7259 expr1
.X_add_symbol
= NULL
;
7260 expr1
.X_add_number
= 1;
7279 mips_emit_delays (true);
7280 ++mips_opts
.noreorder
;
7281 mips_any_noreorder
= 1;
7282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7283 dbl
? "ddiv" : "div",
7284 "0,x,y", xreg
, yreg
);
7285 expr1
.X_add_number
= 2;
7286 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7287 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break", "6",
7290 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7291 since that causes an overflow. We should do that as well,
7292 but I don't see how to do the comparisons without a temporary
7294 --mips_opts
.noreorder
;
7295 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x", zreg
);
7314 mips_emit_delays (true);
7315 ++mips_opts
.noreorder
;
7316 mips_any_noreorder
= 1;
7317 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "0,x,y",
7319 expr1
.X_add_number
= 2;
7320 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
7321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "break",
7323 --mips_opts
.noreorder
;
7324 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s2
, "x", zreg
);
7330 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7331 dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7332 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "mflo", "x",
7341 if (imm_expr
.X_op
!= O_constant
)
7342 as_bad (_("Unsupported large constant"));
7343 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7344 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
7345 dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7349 if (imm_expr
.X_op
!= O_constant
)
7350 as_bad (_("Unsupported large constant"));
7351 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7352 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
7357 if (imm_expr
.X_op
!= O_constant
)
7358 as_bad (_("Unsupported large constant"));
7359 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7360 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
7383 goto do_reverse_branch
;
7387 goto do_reverse_branch
;
7399 goto do_reverse_branch
;
7410 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7412 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7439 goto do_addone_branch_i
;
7444 goto do_addone_branch_i
;
7459 goto do_addone_branch_i
;
7466 if (imm_expr
.X_op
!= O_constant
)
7467 as_bad (_("Unsupported large constant"));
7468 ++imm_expr
.X_add_number
;
7471 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7472 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7476 expr1
.X_add_number
= 0;
7477 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7479 move_register (&icnt
, xreg
, yreg
);
7480 expr1
.X_add_number
= 2;
7481 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7483 "neg", "x,w", xreg
, xreg
);
7487 /* For consistency checking, verify that all bits are specified either
7488 by the match/mask part of the instruction definition, or by the
7491 validate_mips_insn (opc
)
7492 const struct mips_opcode
*opc
;
7494 const char *p
= opc
->args
;
7496 unsigned long used_bits
= opc
->mask
;
7498 if ((used_bits
& opc
->match
) != opc
->match
)
7500 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7501 opc
->name
, opc
->args
);
7504 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7511 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7512 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7514 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7515 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7516 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7517 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7519 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7520 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7522 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7524 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7525 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7526 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7527 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7528 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7529 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7530 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7531 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7532 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7533 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7534 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7536 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7537 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7538 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7539 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7541 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7542 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7543 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7544 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7545 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7546 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7547 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7548 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7549 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7552 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7553 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7554 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7556 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7557 c
, opc
->name
, opc
->args
);
7561 if (used_bits
!= 0xffffffff)
7563 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7564 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7570 /* This routine assembles an instruction into its binary format. As a
7571 side effect, it sets one of the global variables imm_reloc or
7572 offset_reloc to the type of relocation to do if one of the operands
7573 is an address expression. */
7578 struct mips_cl_insn
*ip
;
7583 struct mips_opcode
*insn
;
7586 unsigned int lastregno
= 0;
7589 int full_opcode_match
= 1;
7593 /* If the instruction contains a '.', we first try to match an instruction
7594 including the '.'. Then we try again without the '.'. */
7596 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7599 /* If we stopped on whitespace, then replace the whitespace with null for
7600 the call to hash_find. Save the character we replaced just in case we
7601 have to re-parse the instruction. */
7608 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7610 /* If we didn't find the instruction in the opcode table, try again, but
7611 this time with just the instruction up to, but not including the
7615 /* Restore the character we overwrite above (if any). */
7619 /* Scan up to the first '.' or whitespace. */
7621 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7625 /* If we did not find a '.', then we can quit now. */
7628 insn_error
= "unrecognized opcode";
7632 /* Lookup the instruction in the hash table. */
7634 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7636 insn_error
= "unrecognized opcode";
7640 full_opcode_match
= 0;
7648 assert (strcmp (insn
->name
, str
) == 0);
7650 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_arch
))
7655 if (insn
->pinfo
!= INSN_MACRO
)
7657 if (mips_arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
7663 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7664 && strcmp (insn
->name
, insn
[1].name
) == 0)
7673 static char buf
[100];
7675 _("opcode not supported on this processor: %s (%s)"),
7676 mips_cpu_to_str (mips_arch
),
7677 mips_isa_to_str (mips_opts
.isa
));
7688 ip
->insn_opcode
= insn
->match
;
7690 for (args
= insn
->args
;; ++args
)
7692 s
+= strspn (s
, " \t");
7695 case '\0': /* end of args */
7708 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
7712 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
7716 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
7720 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
7726 /* Handle optional base register.
7727 Either the base register is omitted or
7728 we must have a left paren. */
7729 /* This is dependent on the next operand specifier
7730 is a base register specification. */
7731 assert (args
[1] == 'b' || args
[1] == '5'
7732 || args
[1] == '-' || args
[1] == '4');
7736 case ')': /* these must match exactly */
7741 case '<': /* must be at least one digit */
7743 * According to the manual, if the shift amount is greater
7744 * than 31 or less than 0, then the shift amount should be
7745 * mod 32. In reality the mips assembler issues an error.
7746 * We issue a warning and mask out all but the low 5 bits.
7748 my_getExpression (&imm_expr
, s
);
7749 check_absolute_expr (ip
, &imm_expr
);
7750 if ((unsigned long) imm_expr
.X_add_number
> 31)
7752 as_warn (_("Improper shift amount (%ld)"),
7753 (long) imm_expr
.X_add_number
);
7754 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
7756 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
7757 imm_expr
.X_op
= O_absent
;
7761 case '>': /* shift amount minus 32 */
7762 my_getExpression (&imm_expr
, s
);
7763 check_absolute_expr (ip
, &imm_expr
);
7764 if ((unsigned long) imm_expr
.X_add_number
< 32
7765 || (unsigned long) imm_expr
.X_add_number
> 63)
7767 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
7768 imm_expr
.X_op
= O_absent
;
7772 case 'k': /* cache code */
7773 case 'h': /* prefx code */
7774 my_getExpression (&imm_expr
, s
);
7775 check_absolute_expr (ip
, &imm_expr
);
7776 if ((unsigned long) imm_expr
.X_add_number
> 31)
7778 as_warn (_("Invalid value for `%s' (%lu)"),
7780 (unsigned long) imm_expr
.X_add_number
);
7781 imm_expr
.X_add_number
&= 0x1f;
7784 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7786 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7787 imm_expr
.X_op
= O_absent
;
7791 case 'c': /* break code */
7792 my_getExpression (&imm_expr
, s
);
7793 check_absolute_expr (ip
, &imm_expr
);
7794 if ((unsigned) imm_expr
.X_add_number
> 1023)
7796 as_warn (_("Illegal break code (%ld)"),
7797 (long) imm_expr
.X_add_number
);
7798 imm_expr
.X_add_number
&= OP_MASK_CODE
;
7800 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
7801 imm_expr
.X_op
= O_absent
;
7805 case 'q': /* lower break code */
7806 my_getExpression (&imm_expr
, s
);
7807 check_absolute_expr (ip
, &imm_expr
);
7808 if ((unsigned) imm_expr
.X_add_number
> 1023)
7810 as_warn (_("Illegal lower break code (%ld)"),
7811 (long) imm_expr
.X_add_number
);
7812 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
7814 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
7815 imm_expr
.X_op
= O_absent
;
7819 case 'B': /* 20-bit syscall/break code. */
7820 my_getExpression (&imm_expr
, s
);
7821 check_absolute_expr (ip
, &imm_expr
);
7822 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE20
)
7823 as_warn (_("Illegal 20-bit code (%ld)"),
7824 (long) imm_expr
.X_add_number
);
7825 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
7826 imm_expr
.X_op
= O_absent
;
7830 case 'C': /* Coprocessor code */
7831 my_getExpression (&imm_expr
, s
);
7832 check_absolute_expr (ip
, &imm_expr
);
7833 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7835 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7836 (long) imm_expr
.X_add_number
);
7837 imm_expr
.X_add_number
&= ((1<<25) - 1);
7839 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7840 imm_expr
.X_op
= O_absent
;
7844 case 'J': /* 19-bit wait code. */
7845 my_getExpression (&imm_expr
, s
);
7846 check_absolute_expr (ip
, &imm_expr
);
7847 if ((unsigned) imm_expr
.X_add_number
> OP_MASK_CODE19
)
7848 as_warn (_("Illegal 19-bit code (%ld)"),
7849 (long) imm_expr
.X_add_number
);
7850 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
7851 imm_expr
.X_op
= O_absent
;
7855 case 'P': /* Performance register */
7856 my_getExpression (&imm_expr
, s
);
7857 check_absolute_expr (ip
, &imm_expr
);
7858 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7860 as_warn (_("Invalid performance register (%ld)"),
7861 (long) imm_expr
.X_add_number
);
7862 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
7864 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
7865 imm_expr
.X_op
= O_absent
;
7869 case 'b': /* base register */
7870 case 'd': /* destination register */
7871 case 's': /* source register */
7872 case 't': /* target register */
7873 case 'r': /* both target and source */
7874 case 'v': /* both dest and source */
7875 case 'w': /* both dest and target */
7876 case 'E': /* coprocessor target register */
7877 case 'G': /* coprocessor destination register */
7878 case 'x': /* ignore register name */
7879 case 'z': /* must be zero register */
7880 case 'U': /* destination register (clo/clz). */
7895 while (ISDIGIT (*s
));
7897 as_bad (_("Invalid register number (%d)"), regno
);
7899 else if (*args
== 'E' || *args
== 'G')
7903 if (s
[1] == 'f' && s
[2] == 'p')
7908 else if (s
[1] == 's' && s
[2] == 'p')
7913 else if (s
[1] == 'g' && s
[2] == 'p')
7918 else if (s
[1] == 'a' && s
[2] == 't')
7923 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7928 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7933 else if (itbl_have_entries
)
7938 p
= s
+ 1; /* advance past '$' */
7939 n
= itbl_get_field (&p
); /* n is name */
7941 /* See if this is a register defined in an
7943 if (itbl_get_reg_val (n
, &r
))
7945 /* Get_field advances to the start of
7946 the next field, so we need to back
7947 rack to the end of the last field. */
7951 s
= strchr (s
, '\0');
7964 as_warn (_("Used $at without \".set noat\""));
7970 if (c
== 'r' || c
== 'v' || c
== 'w')
7977 /* 'z' only matches $0. */
7978 if (c
== 'z' && regno
!= 0)
7981 /* Now that we have assembled one operand, we use the args string
7982 * to figure out where it goes in the instruction. */
7989 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
7993 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7996 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
7997 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8002 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8005 /* This case exists because on the r3000 trunc
8006 expands into a macro which requires a gp
8007 register. On the r6000 or r4000 it is
8008 assembled into a single instruction which
8009 ignores the register. Thus the insn version
8010 is MIPS_ISA2 and uses 'x', and the macro
8011 version is MIPS_ISA1 and uses 't'. */
8014 /* This case is for the div instruction, which
8015 acts differently if the destination argument
8016 is $0. This only matches $0, and is checked
8017 outside the switch. */
8020 /* Itbl operand; not yet implemented. FIXME ?? */
8022 /* What about all other operands like 'i', which
8023 can be specified in the opcode table? */
8033 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8036 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8041 case 'D': /* floating point destination register */
8042 case 'S': /* floating point source register */
8043 case 'T': /* floating point target register */
8044 case 'R': /* floating point source register */
8048 if (s
[0] == '$' && s
[1] == 'f'
8059 while (ISDIGIT (*s
));
8062 as_bad (_("Invalid float register number (%d)"), regno
);
8064 if ((regno
& 1) != 0
8066 && ! (strcmp (str
, "mtc1") == 0
8067 || strcmp (str
, "mfc1") == 0
8068 || strcmp (str
, "lwc1") == 0
8069 || strcmp (str
, "swc1") == 0
8070 || strcmp (str
, "l.s") == 0
8071 || strcmp (str
, "s.s") == 0))
8072 as_warn (_("Float register should be even, was %d"),
8080 if (c
== 'V' || c
== 'W')
8090 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8094 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8098 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8101 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8111 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8114 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8120 my_getExpression (&imm_expr
, s
);
8121 if (imm_expr
.X_op
!= O_big
8122 && imm_expr
.X_op
!= O_constant
)
8123 insn_error
= _("absolute expression required");
8128 my_getExpression (&offset_expr
, s
);
8129 *imm_reloc
= BFD_RELOC_32
;
8142 unsigned char temp
[8];
8144 unsigned int length
;
8149 /* These only appear as the last operand in an
8150 instruction, and every instruction that accepts
8151 them in any variant accepts them in all variants.
8152 This means we don't have to worry about backing out
8153 any changes if the instruction does not match.
8155 The difference between them is the size of the
8156 floating point constant and where it goes. For 'F'
8157 and 'L' the constant is 64 bits; for 'f' and 'l' it
8158 is 32 bits. Where the constant is placed is based
8159 on how the MIPS assembler does things:
8162 f -- immediate value
8165 The .lit4 and .lit8 sections are only used if
8166 permitted by the -G argument.
8168 When generating embedded PIC code, we use the
8169 .lit8 section but not the .lit4 section (we can do
8170 .lit4 inline easily; we need to put .lit8
8171 somewhere in the data segment, and using .lit8
8172 permits the linker to eventually combine identical
8175 The code below needs to know whether the target register
8176 is 32 or 64 bits wide. It relies on the fact 'f' and
8177 'F' are used with GPR-based instructions and 'l' and
8178 'L' are used with FPR-based instructions. */
8180 f64
= *args
== 'F' || *args
== 'L';
8181 using_gprs
= *args
== 'F' || *args
== 'f';
8183 save_in
= input_line_pointer
;
8184 input_line_pointer
= s
;
8185 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8187 s
= input_line_pointer
;
8188 input_line_pointer
= save_in
;
8189 if (err
!= NULL
&& *err
!= '\0')
8191 as_bad (_("Bad floating point constant: %s"), err
);
8192 memset (temp
, '\0', sizeof temp
);
8193 length
= f64
? 8 : 4;
8196 assert (length
== (unsigned) (f64
? 8 : 4));
8200 && (! USE_GLOBAL_POINTER_OPT
8201 || mips_pic
== EMBEDDED_PIC
8202 || g_switch_value
< 4
8203 || (temp
[0] == 0 && temp
[1] == 0)
8204 || (temp
[2] == 0 && temp
[3] == 0))))
8206 imm_expr
.X_op
= O_constant
;
8207 if (! target_big_endian
)
8208 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8210 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8213 && ! mips_disable_float_construction
8214 /* Constants can only be constructed in GPRs and
8215 copied to FPRs if the GPRs are at least as wide
8216 as the FPRs. Force the constant into memory if
8217 we are using 64-bit FPRs but the GPRs are only
8220 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8221 && ((temp
[0] == 0 && temp
[1] == 0)
8222 || (temp
[2] == 0 && temp
[3] == 0))
8223 && ((temp
[4] == 0 && temp
[5] == 0)
8224 || (temp
[6] == 0 && temp
[7] == 0)))
8226 /* The value is simple enough to load with a couple of
8227 instructions. If using 32-bit registers, set
8228 imm_expr to the high order 32 bits and offset_expr to
8229 the low order 32 bits. Otherwise, set imm_expr to
8230 the entire 64 bit constant. */
8231 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8233 imm_expr
.X_op
= O_constant
;
8234 offset_expr
.X_op
= O_constant
;
8235 if (! target_big_endian
)
8237 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8238 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8242 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8243 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8245 if (offset_expr
.X_add_number
== 0)
8246 offset_expr
.X_op
= O_absent
;
8248 else if (sizeof (imm_expr
.X_add_number
) > 4)
8250 imm_expr
.X_op
= O_constant
;
8251 if (! target_big_endian
)
8252 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8254 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8258 imm_expr
.X_op
= O_big
;
8259 imm_expr
.X_add_number
= 4;
8260 if (! target_big_endian
)
8262 generic_bignum
[0] = bfd_getl16 (temp
);
8263 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8264 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8265 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8269 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8270 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8271 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8272 generic_bignum
[3] = bfd_getb16 (temp
);
8278 const char *newname
;
8281 /* Switch to the right section. */
8283 subseg
= now_subseg
;
8286 default: /* unused default case avoids warnings. */
8288 newname
= RDATA_SECTION_NAME
;
8289 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8290 || mips_pic
== EMBEDDED_PIC
)
8294 if (mips_pic
== EMBEDDED_PIC
)
8297 newname
= RDATA_SECTION_NAME
;
8300 assert (!USE_GLOBAL_POINTER_OPT
8301 || g_switch_value
>= 4);
8305 new_seg
= subseg_new (newname
, (subsegT
) 0);
8306 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8307 bfd_set_section_flags (stdoutput
, new_seg
,
8312 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8313 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8314 && strcmp (TARGET_OS
, "elf") != 0)
8315 record_alignment (new_seg
, 4);
8317 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8319 as_bad (_("Can't use floating point insn in this section"));
8321 /* Set the argument to the current address in the
8323 offset_expr
.X_op
= O_symbol
;
8324 offset_expr
.X_add_symbol
=
8325 symbol_new ("L0\001", now_seg
,
8326 (valueT
) frag_now_fix (), frag_now
);
8327 offset_expr
.X_add_number
= 0;
8329 /* Put the floating point number into the section. */
8330 p
= frag_more ((int) length
);
8331 memcpy (p
, temp
, length
);
8333 /* Switch back to the original section. */
8334 subseg_set (seg
, subseg
);
8339 case 'i': /* 16 bit unsigned immediate */
8340 case 'j': /* 16 bit signed immediate */
8341 *imm_reloc
= BFD_RELOC_LO16
;
8342 c
= my_getSmallExpression (&imm_expr
, s
);
8347 if (imm_expr
.X_op
== O_constant
)
8348 imm_expr
.X_add_number
=
8349 (imm_expr
.X_add_number
>> 16) & 0xffff;
8351 else if (c
== S_EX_HIGHEST
)
8352 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8353 else if (c
== S_EX_HIGHER
)
8354 *imm_reloc
= BFD_RELOC_MIPS_HIGHER
;
8355 else if (c
== S_EX_GP_REL
)
8357 /* This occurs in NewABI only. */
8358 c
= my_getSmallExpression (&imm_expr
, s
);
8360 as_bad (_("bad composition of relocations"));
8363 c
= my_getSmallExpression (&imm_expr
, s
);
8365 as_bad (_("bad composition of relocations"));
8368 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8369 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8370 imm_reloc
[2] = BFD_RELOC_LO16
;
8375 else if (c
== S_EX_HI
)
8377 *imm_reloc
= BFD_RELOC_HI16_S
;
8378 imm_unmatched_hi
= true;
8381 *imm_reloc
= BFD_RELOC_HI16
;
8383 else if (imm_expr
.X_op
== O_constant
)
8384 imm_expr
.X_add_number
&= 0xffff;
8388 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8389 || ((imm_expr
.X_add_number
< 0
8390 || imm_expr
.X_add_number
>= 0x10000)
8391 && imm_expr
.X_op
== O_constant
))
8393 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8394 !strcmp (insn
->name
, insn
[1].name
))
8396 if (imm_expr
.X_op
== O_constant
8397 || imm_expr
.X_op
== O_big
)
8398 as_bad (_("16 bit expression not in range 0..65535"));
8406 /* The upper bound should be 0x8000, but
8407 unfortunately the MIPS assembler accepts numbers
8408 from 0x8000 to 0xffff and sign extends them, and
8409 we want to be compatible. We only permit this
8410 extended range for an instruction which does not
8411 provide any further alternates, since those
8412 alternates may handle other cases. People should
8413 use the numbers they mean, rather than relying on
8414 a mysterious sign extension. */
8415 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8416 strcmp (insn
->name
, insn
[1].name
) == 0);
8421 if ((c
== S_EX_NONE
&& imm_expr
.X_op
!= O_constant
)
8422 || ((imm_expr
.X_add_number
< -0x8000
8423 || imm_expr
.X_add_number
>= max
)
8424 && imm_expr
.X_op
== O_constant
)
8426 && imm_expr
.X_add_number
< 0
8428 && imm_expr
.X_unsigned
8429 && sizeof (imm_expr
.X_add_number
) <= 4))
8433 if (imm_expr
.X_op
== O_constant
8434 || imm_expr
.X_op
== O_big
)
8435 as_bad (_("16 bit expression not in range -32768..32767"));
8441 case 'o': /* 16 bit offset */
8442 c
= my_getSmallExpression (&offset_expr
, s
);
8444 /* If this value won't fit into a 16 bit offset, then go
8445 find a macro that will generate the 32 bit offset
8448 && (offset_expr
.X_op
!= O_constant
8449 || offset_expr
.X_add_number
>= 0x8000
8450 || offset_expr
.X_add_number
< -0x8000))
8455 if (offset_expr
.X_op
!= O_constant
)
8457 offset_expr
.X_add_number
=
8458 (offset_expr
.X_add_number
>> 16) & 0xffff;
8460 *offset_reloc
= BFD_RELOC_LO16
;
8464 case 'p': /* pc relative offset */
8465 if (mips_pic
== EMBEDDED_PIC
)
8466 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8468 *offset_reloc
= BFD_RELOC_16_PCREL
;
8469 my_getExpression (&offset_expr
, s
);
8473 case 'u': /* upper 16 bits */
8474 c
= my_getSmallExpression (&imm_expr
, s
);
8475 *imm_reloc
= BFD_RELOC_LO16
;
8480 if (imm_expr
.X_op
== O_constant
)
8481 imm_expr
.X_add_number
=
8482 (imm_expr
.X_add_number
>> 16) & 0xffff;
8483 else if (c
== S_EX_HI
)
8485 *imm_reloc
= BFD_RELOC_HI16_S
;
8486 imm_unmatched_hi
= true;
8489 else if (c
== S_EX_HIGHEST
)
8490 *imm_reloc
= BFD_RELOC_MIPS_HIGHEST
;
8491 else if (c
== S_EX_GP_REL
)
8493 /* This occurs in NewABI only. */
8494 c
= my_getSmallExpression (&imm_expr
, s
);
8496 as_bad (_("bad composition of relocations"));
8499 c
= my_getSmallExpression (&imm_expr
, s
);
8501 as_bad (_("bad composition of relocations"));
8504 imm_reloc
[0] = BFD_RELOC_GPREL16
;
8505 imm_reloc
[1] = BFD_RELOC_MIPS_SUB
;
8506 imm_reloc
[2] = BFD_RELOC_HI16_S
;
8512 *imm_reloc
= BFD_RELOC_HI16
;
8514 else if (imm_expr
.X_op
== O_constant
)
8515 imm_expr
.X_add_number
&= 0xffff;
8517 if (imm_expr
.X_op
== O_constant
8518 && (imm_expr
.X_add_number
< 0
8519 || imm_expr
.X_add_number
>= 0x10000))
8520 as_bad (_("lui expression not in range 0..65535"));
8524 case 'a': /* 26 bit address */
8525 my_getExpression (&offset_expr
, s
);
8527 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8530 case 'N': /* 3 bit branch condition code */
8531 case 'M': /* 3 bit compare condition code */
8532 if (strncmp (s
, "$fcc", 4) != 0)
8542 while (ISDIGIT (*s
));
8544 as_bad (_("invalid condition code register $fcc%d"), regno
);
8546 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8548 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8552 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
8563 while (ISDIGIT (*s
));
8566 c
= 8; /* Invalid sel value. */
8569 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
8570 ip
->insn_opcode
|= c
;
8574 as_bad (_("bad char = '%c'\n"), *args
);
8579 /* Args don't match. */
8580 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8581 !strcmp (insn
->name
, insn
[1].name
))
8585 insn_error
= _("illegal operands");
8590 insn_error
= _("illegal operands");
8595 /* This routine assembles an instruction into its binary format when
8596 assembling for the mips16. As a side effect, it sets one of the
8597 global variables imm_reloc or offset_reloc to the type of
8598 relocation to do if one of the operands is an address expression.
8599 It also sets mips16_small and mips16_ext if the user explicitly
8600 requested a small or extended instruction. */
8605 struct mips_cl_insn
*ip
;
8609 struct mips_opcode
*insn
;
8612 unsigned int lastregno
= 0;
8617 mips16_small
= false;
8620 for (s
= str
; ISLOWER (*s
); ++s
)
8632 if (s
[1] == 't' && s
[2] == ' ')
8635 mips16_small
= true;
8639 else if (s
[1] == 'e' && s
[2] == ' ')
8648 insn_error
= _("unknown opcode");
8652 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8653 mips16_small
= true;
8655 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8657 insn_error
= _("unrecognized opcode");
8664 assert (strcmp (insn
->name
, str
) == 0);
8667 ip
->insn_opcode
= insn
->match
;
8668 ip
->use_extend
= false;
8669 imm_expr
.X_op
= O_absent
;
8670 imm_reloc
[0] = BFD_RELOC_UNUSED
;
8671 imm_reloc
[1] = BFD_RELOC_UNUSED
;
8672 imm_reloc
[2] = BFD_RELOC_UNUSED
;
8673 offset_expr
.X_op
= O_absent
;
8674 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8675 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8676 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8677 for (args
= insn
->args
; 1; ++args
)
8684 /* In this switch statement we call break if we did not find
8685 a match, continue if we did find a match, or return if we
8694 /* Stuff the immediate value in now, if we can. */
8695 if (imm_expr
.X_op
== O_constant
8696 && *imm_reloc
> BFD_RELOC_UNUSED
8697 && insn
->pinfo
!= INSN_MACRO
)
8699 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
8700 imm_expr
.X_add_number
, true, mips16_small
,
8701 mips16_ext
, &ip
->insn_opcode
,
8702 &ip
->use_extend
, &ip
->extend
);
8703 imm_expr
.X_op
= O_absent
;
8704 *imm_reloc
= BFD_RELOC_UNUSED
;
8718 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8721 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8737 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8739 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8766 while (ISDIGIT (*s
));
8769 as_bad (_("invalid register number (%d)"), regno
);
8775 if (s
[1] == 'f' && s
[2] == 'p')
8780 else if (s
[1] == 's' && s
[2] == 'p')
8785 else if (s
[1] == 'g' && s
[2] == 'p')
8790 else if (s
[1] == 'a' && s
[2] == 't')
8795 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8800 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8813 if (c
== 'v' || c
== 'w')
8815 regno
= mips16_to_32_reg_map
[lastregno
];
8829 regno
= mips32_to_16_reg_map
[regno
];
8834 regno
= ILLEGAL_REG
;
8839 regno
= ILLEGAL_REG
;
8844 regno
= ILLEGAL_REG
;
8849 if (regno
== AT
&& ! mips_opts
.noat
)
8850 as_warn (_("used $at without \".set noat\""));
8857 if (regno
== ILLEGAL_REG
)
8864 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8868 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8871 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8874 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8880 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8883 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8884 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8894 if (strncmp (s
, "$pc", 3) == 0)
8918 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8920 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8921 and generate the appropriate reloc. If the text
8922 inside %gprel is not a symbol name with an
8923 optional offset, then we generate a normal reloc
8924 and will probably fail later. */
8925 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8926 if (imm_expr
.X_op
== O_symbol
)
8929 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8931 ip
->use_extend
= true;
8938 /* Just pick up a normal expression. */
8939 my_getExpression (&imm_expr
, s
);
8942 if (imm_expr
.X_op
== O_register
)
8944 /* What we thought was an expression turned out to
8947 if (s
[0] == '(' && args
[1] == '(')
8949 /* It looks like the expression was omitted
8950 before a register indirection, which means
8951 that the expression is implicitly zero. We
8952 still set up imm_expr, so that we handle
8953 explicit extensions correctly. */
8954 imm_expr
.X_op
= O_constant
;
8955 imm_expr
.X_add_number
= 0;
8956 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8963 /* We need to relax this instruction. */
8964 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8973 /* We use offset_reloc rather than imm_reloc for the PC
8974 relative operands. This lets macros with both
8975 immediate and address operands work correctly. */
8976 my_getExpression (&offset_expr
, s
);
8978 if (offset_expr
.X_op
== O_register
)
8981 /* We need to relax this instruction. */
8982 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8986 case '6': /* break code */
8987 my_getExpression (&imm_expr
, s
);
8988 check_absolute_expr (ip
, &imm_expr
);
8989 if ((unsigned long) imm_expr
.X_add_number
> 63)
8991 as_warn (_("Invalid value for `%s' (%lu)"),
8993 (unsigned long) imm_expr
.X_add_number
);
8994 imm_expr
.X_add_number
&= 0x3f;
8996 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8997 imm_expr
.X_op
= O_absent
;
9001 case 'a': /* 26 bit address */
9002 my_getExpression (&offset_expr
, s
);
9004 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9005 ip
->insn_opcode
<<= 16;
9008 case 'l': /* register list for entry macro */
9009 case 'L': /* register list for exit macro */
9019 int freg
, reg1
, reg2
;
9021 while (*s
== ' ' || *s
== ',')
9025 as_bad (_("can't parse register list"));
9037 while (ISDIGIT (*s
))
9059 as_bad (_("invalid register list"));
9064 while (ISDIGIT (*s
))
9071 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9076 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9081 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9082 mask
|= (reg2
- 3) << 3;
9083 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9084 mask
|= (reg2
- 15) << 1;
9085 else if (reg1
== 31 && reg2
== 31)
9089 as_bad (_("invalid register list"));
9093 /* The mask is filled in in the opcode table for the
9094 benefit of the disassembler. We remove it before
9095 applying the actual mask. */
9096 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9097 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9101 case 'e': /* extend code */
9102 my_getExpression (&imm_expr
, s
);
9103 check_absolute_expr (ip
, &imm_expr
);
9104 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9106 as_warn (_("Invalid value for `%s' (%lu)"),
9108 (unsigned long) imm_expr
.X_add_number
);
9109 imm_expr
.X_add_number
&= 0x7ff;
9111 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9112 imm_expr
.X_op
= O_absent
;
9122 /* Args don't match. */
9123 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9124 strcmp (insn
->name
, insn
[1].name
) == 0)
9131 insn_error
= _("illegal operands");
9137 /* This structure holds information we know about a mips16 immediate
9140 struct mips16_immed_operand
9142 /* The type code used in the argument string in the opcode table. */
9144 /* The number of bits in the short form of the opcode. */
9146 /* The number of bits in the extended form of the opcode. */
9148 /* The amount by which the short form is shifted when it is used;
9149 for example, the sw instruction has a shift count of 2. */
9151 /* The amount by which the short form is shifted when it is stored
9152 into the instruction code. */
9154 /* Non-zero if the short form is unsigned. */
9156 /* Non-zero if the extended form is unsigned. */
9158 /* Non-zero if the value is PC relative. */
9162 /* The mips16 immediate operand types. */
9164 static const struct mips16_immed_operand mips16_immed_operands
[] =
9166 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9167 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9168 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9169 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9170 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9171 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9172 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9173 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9174 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9175 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9176 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9177 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9178 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9179 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9180 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9181 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9182 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9183 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9184 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9185 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9186 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9189 #define MIPS16_NUM_IMMED \
9190 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9192 /* Handle a mips16 instruction with an immediate value. This or's the
9193 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9194 whether an extended value is needed; if one is needed, it sets
9195 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9196 If SMALL is true, an unextended opcode was explicitly requested.
9197 If EXT is true, an extended opcode was explicitly requested. If
9198 WARN is true, warn if EXT does not match reality. */
9201 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9210 unsigned long *insn
;
9211 boolean
*use_extend
;
9212 unsigned short *extend
;
9214 register const struct mips16_immed_operand
*op
;
9215 int mintiny
, maxtiny
;
9218 op
= mips16_immed_operands
;
9219 while (op
->type
!= type
)
9222 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9227 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9230 maxtiny
= 1 << op
->nbits
;
9235 maxtiny
= (1 << op
->nbits
) - 1;
9240 mintiny
= - (1 << (op
->nbits
- 1));
9241 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9244 /* Branch offsets have an implicit 0 in the lowest bit. */
9245 if (type
== 'p' || type
== 'q')
9248 if ((val
& ((1 << op
->shift
) - 1)) != 0
9249 || val
< (mintiny
<< op
->shift
)
9250 || val
> (maxtiny
<< op
->shift
))
9255 if (warn
&& ext
&& ! needext
)
9256 as_warn_where (file
, line
,
9257 _("extended operand requested but not required"));
9258 if (small
&& needext
)
9259 as_bad_where (file
, line
, _("invalid unextended operand value"));
9261 if (small
|| (! ext
&& ! needext
))
9265 *use_extend
= false;
9266 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9267 insnval
<<= op
->op_shift
;
9272 long minext
, maxext
;
9278 maxext
= (1 << op
->extbits
) - 1;
9282 minext
= - (1 << (op
->extbits
- 1));
9283 maxext
= (1 << (op
->extbits
- 1)) - 1;
9285 if (val
< minext
|| val
> maxext
)
9286 as_bad_where (file
, line
,
9287 _("operand value out of range for instruction"));
9290 if (op
->extbits
== 16)
9292 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9295 else if (op
->extbits
== 15)
9297 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9302 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9306 *extend
= (unsigned short) extval
;
9311 static struct percent_op_match
9314 const enum small_ex_type type
;
9318 {"%half", S_EX_HALF
},
9323 {"%gp_rel", S_EX_GP_REL
},
9325 {"%call16", S_EX_CALL16
},
9326 {"%got_disp", S_EX_GOT_DISP
},
9327 {"%got_page", S_EX_GOT_PAGE
},
9328 {"%got_ofst", S_EX_GOT_OFST
},
9329 {"%got_hi", S_EX_GOT_HI
},
9330 {"%got_lo", S_EX_GOT_LO
},
9332 {"%higher", S_EX_HIGHER
},
9333 {"%highest", S_EX_HIGHEST
},
9334 {"%call_hi", S_EX_CALL_HI
},
9335 {"%call_lo", S_EX_CALL_LO
}
9339 /* Parse small expression input. STR gets adjusted to eat up whitespace.
9340 It detects valid "%percent_op(...)" and "($reg)" strings. Percent_op's
9341 can be nested, this is handled by blanking the innermost, parsing the
9342 rest by subsequent calls. */
9345 my_getSmallParser (str
, len
, nestlevel
)
9350 int type
= S_EX_NONE
;
9353 *str
+= strspn (*str
, " \t");
9356 char *b
= *str
+ 1 + strspn (*str
+ 1, " \t");
9359 /* Check for base register. */
9363 && (e
= b
+ strcspn (b
, ") \t"))
9364 && e
- b
> 1 && e
- b
< 4)
9367 && ((b
[1] == 'f' && b
[2] == 'p')
9368 || (b
[1] == 's' && b
[2] == 'p')
9369 || (b
[1] == 'g' && b
[2] == 'p')
9370 || (b
[1] == 'a' && b
[2] == 't')
9372 && ISDIGIT (b
[2]))))
9373 || (ISDIGIT (b
[1])))
9375 *len
= strcspn (*str
, ")") + 1;
9376 return S_EX_REGISTER
;
9380 else if (b
[0] == '%')
9386 /* Some other expression in the braces. */
9387 *len
= strcspn (*str
, ")") + 1;
9389 /* Check for percent_op. */
9390 else if (*str
[0] == '%')
9399 while (ISALPHA (*tmp
) || *tmp
== '_')
9401 *tmp
= TOLOWER (*tmp
);
9404 while (i
< (sizeof (percent_op
) / sizeof (struct percent_op_match
)))
9406 if (strncmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)))
9410 type
= percent_op
[i
].type
;
9412 /* Only %hi and %lo are allowed for OldABI. */
9413 if (! HAVE_NEWABI
&& type
!= S_EX_HI
&& type
!= S_EX_LO
)
9416 *len
= strlen (percent_op
[i
].str
);
9423 /* Any other expression. */
9428 my_getSmallExpression (ep
, str
)
9432 static char *oldstr
= NULL
;
9438 /* Don't update oldstr if the last call had nested percent_op's. */
9445 c
= my_getSmallParser (&str
, &len
, &nest_level
);
9446 if (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
)
9449 while (c
!= S_EX_NONE
&& c
!= S_EX_REGISTER
);
9451 /* A percent_op was encountered. */
9454 /* Don't try to get an expression if it is already blanked out. */
9455 if (*(str
+ strspn (str
+ 1, " )")) != ')')
9459 save
= *(str
+ len
);
9460 *(str
+ len
) = '\0';
9461 my_getExpression (ep
, str
);
9462 *(str
+ len
) = save
;
9466 /* blank out including the % sign. */
9467 char *p
= strrchr (oldstr
, '%');
9468 memset (p
, ' ', str
- p
+ len
);
9473 expr_end
= strchr (str
, ')') + 1;
9477 else if (c
== S_EX_NONE
)
9479 my_getExpression (ep
, str
);
9481 else if (c
== S_EX_REGISTER
)
9483 ep
->X_op
= O_constant
;
9485 ep
->X_add_symbol
= NULL
;
9486 ep
->X_op_symbol
= NULL
;
9487 ep
->X_add_number
= 0;
9491 as_fatal(_("internal error"));
9494 if (nest_level
<= 1)
9501 my_getExpression (ep
, str
)
9508 save_in
= input_line_pointer
;
9509 input_line_pointer
= str
;
9511 expr_end
= input_line_pointer
;
9512 input_line_pointer
= save_in
;
9514 /* If we are in mips16 mode, and this is an expression based on `.',
9515 then we bump the value of the symbol by 1 since that is how other
9516 text symbols are handled. We don't bother to handle complex
9517 expressions, just `.' plus or minus a constant. */
9518 if (mips_opts
.mips16
9519 && ep
->X_op
== O_symbol
9520 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9521 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9522 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9523 && symbol_constant_p (ep
->X_add_symbol
)
9524 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9525 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9528 /* Turn a string in input_line_pointer into a floating point constant
9529 of type TYPE, and store the appropriate bytes in *LITP. The number
9530 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9531 returned, or NULL on OK. */
9534 md_atof (type
, litP
, sizeP
)
9540 LITTLENUM_TYPE words
[4];
9556 return _("bad call to md_atof");
9559 t
= atof_ieee (input_line_pointer
, type
, words
);
9561 input_line_pointer
= t
;
9565 if (! target_big_endian
)
9567 for (i
= prec
- 1; i
>= 0; i
--)
9569 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9575 for (i
= 0; i
< prec
; i
++)
9577 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9586 md_number_to_chars (buf
, val
, n
)
9591 if (target_big_endian
)
9592 number_to_chars_bigendian (buf
, val
, n
);
9594 number_to_chars_littleendian (buf
, val
, n
);
9598 static int support_64bit_objects(void)
9600 const char **list
, **l
;
9602 list
= bfd_target_list ();
9603 for (l
= list
; *l
!= NULL
; l
++)
9605 /* This is traditional mips */
9606 if (strcmp (*l
, "elf64-tradbigmips") == 0
9607 || strcmp (*l
, "elf64-tradlittlemips") == 0)
9609 if (strcmp (*l
, "elf64-bigmips") == 0
9610 || strcmp (*l
, "elf64-littlemips") == 0)
9614 return (*l
!= NULL
);
9616 #endif /* OBJ_ELF */
9618 CONST
char *md_shortopts
= "nO::g::G:";
9620 struct option md_longopts
[] =
9622 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9623 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9624 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9625 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9626 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9627 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9628 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9629 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9630 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9631 #define OPTION_MIPS5 (OPTION_MD_BASE + 5)
9632 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
9633 #define OPTION_MIPS32 (OPTION_MD_BASE + 6)
9634 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
9635 #define OPTION_MIPS64 (OPTION_MD_BASE + 7)
9636 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
9637 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 8)
9638 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9639 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9640 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9641 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9642 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9643 {"break", no_argument
, NULL
, OPTION_BREAK
},
9644 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9645 #define OPTION_EB (OPTION_MD_BASE + 11)
9646 {"EB", no_argument
, NULL
, OPTION_EB
},
9647 #define OPTION_EL (OPTION_MD_BASE + 12)
9648 {"EL", no_argument
, NULL
, OPTION_EL
},
9649 #define OPTION_MIPS16 (OPTION_MD_BASE + 13)
9650 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9651 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 14)
9652 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9653 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 15)
9654 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
9655 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 16)
9656 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
9657 #define OPTION_FP32 (OPTION_MD_BASE + 17)
9658 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
9659 #define OPTION_GP32 (OPTION_MD_BASE + 18)
9660 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
9661 #define OPTION_CONSTRUCT_FLOATS (OPTION_MD_BASE + 19)
9662 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
9663 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MD_BASE + 20)
9664 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
9665 #define OPTION_MARCH (OPTION_MD_BASE + 21)
9666 {"march", required_argument
, NULL
, OPTION_MARCH
},
9667 #define OPTION_MTUNE (OPTION_MD_BASE + 22)
9668 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
9669 #define OPTION_MCPU (OPTION_MD_BASE + 23)
9670 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9671 #define OPTION_M4650 (OPTION_MD_BASE + 24)
9672 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9673 #define OPTION_NO_M4650 (OPTION_MD_BASE + 25)
9674 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9675 #define OPTION_M4010 (OPTION_MD_BASE + 26)
9676 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9677 #define OPTION_NO_M4010 (OPTION_MD_BASE + 27)
9678 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9679 #define OPTION_M4100 (OPTION_MD_BASE + 28)
9680 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9681 #define OPTION_NO_M4100 (OPTION_MD_BASE + 29)
9682 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9683 #define OPTION_M3900 (OPTION_MD_BASE + 30)
9684 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9685 #define OPTION_NO_M3900 (OPTION_MD_BASE + 31)
9686 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9687 #define OPTION_GP64 (OPTION_MD_BASE + 32)
9688 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
9690 #define OPTION_ELF_BASE (OPTION_MD_BASE + 33)
9691 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
9692 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9693 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9694 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
9695 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9696 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
9697 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9698 #define OPTION_MABI (OPTION_ELF_BASE + 3)
9699 {"mabi", required_argument
, NULL
, OPTION_MABI
},
9700 #define OPTION_32 (OPTION_ELF_BASE + 4)
9701 {"32", no_argument
, NULL
, OPTION_32
},
9702 #define OPTION_N32 (OPTION_ELF_BASE + 5)
9703 {"n32", no_argument
, NULL
, OPTION_N32
},
9704 #define OPTION_64 (OPTION_ELF_BASE + 6)
9705 {"64", no_argument
, NULL
, OPTION_64
},
9706 #endif /* OBJ_ELF */
9707 {NULL
, no_argument
, NULL
, 0}
9709 size_t md_longopts_size
= sizeof (md_longopts
);
9712 md_parse_option (c
, arg
)
9718 case OPTION_CONSTRUCT_FLOATS
:
9719 mips_disable_float_construction
= 0;
9722 case OPTION_NO_CONSTRUCT_FLOATS
:
9723 mips_disable_float_construction
= 1;
9735 target_big_endian
= 1;
9739 target_big_endian
= 0;
9747 if (arg
&& arg
[1] == '0')
9757 mips_debug
= atoi (arg
);
9758 /* When the MIPS assembler sees -g or -g2, it does not do
9759 optimizations which limit full symbolic debugging. We take
9760 that to be equivalent to -O0. */
9761 if (mips_debug
== 2)
9766 mips_opts
.isa
= ISA_MIPS1
;
9770 mips_opts
.isa
= ISA_MIPS2
;
9774 mips_opts
.isa
= ISA_MIPS3
;
9778 mips_opts
.isa
= ISA_MIPS4
;
9782 mips_opts
.isa
= ISA_MIPS5
;
9786 mips_opts
.isa
= ISA_MIPS32
;
9790 mips_opts
.isa
= ISA_MIPS64
;
9797 int cpu
= CPU_UNKNOWN
;
9799 /* Identify the processor type. */
9800 if (strcasecmp (arg
, "default") != 0)
9802 const struct mips_cpu_info
*ci
;
9804 ci
= mips_cpu_info_from_name (arg
);
9805 if (ci
== NULL
|| ci
->is_isa
)
9810 as_fatal (_("invalid architecture -mtune=%s"), arg
);
9813 as_fatal (_("invalid architecture -march=%s"), arg
);
9816 as_fatal (_("invalid architecture -mcpu=%s"), arg
);
9827 if (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= cpu
)
9828 as_warn(_("A different -mtune= was already specified, is now "
9833 if (mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= cpu
)
9834 as_warn(_("A different -march= was already specified, is now "
9839 if (mips_cpu
!= CPU_UNKNOWN
&& mips_cpu
!= cpu
)
9840 as_warn(_("A different -mcpu= was already specified, is now "
9848 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4650
)
9849 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4650
))
9850 as_warn(_("A different -march= or -mtune= was already specified, "
9852 mips_arch
= CPU_R4650
;
9853 mips_tune
= CPU_R4650
;
9856 case OPTION_NO_M4650
:
9860 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R4010
)
9861 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R4010
))
9862 as_warn(_("A different -march= or -mtune= was already specified, "
9864 mips_arch
= CPU_R4010
;
9865 mips_tune
= CPU_R4010
;
9868 case OPTION_NO_M4010
:
9872 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_VR4100
)
9873 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_VR4100
))
9874 as_warn(_("A different -march= or -mtune= was already specified, "
9876 mips_arch
= CPU_VR4100
;
9877 mips_tune
= CPU_VR4100
;
9880 case OPTION_NO_M4100
:
9884 if ((mips_arch
!= CPU_UNKNOWN
&& mips_arch
!= CPU_R3900
)
9885 || (mips_tune
!= CPU_UNKNOWN
&& mips_tune
!= CPU_R3900
))
9886 as_warn(_("A different -march= or -mtune= was already specified, "
9888 mips_arch
= CPU_R3900
;
9889 mips_tune
= CPU_R3900
;
9892 case OPTION_NO_M3900
:
9896 mips_opts
.mips16
= 1;
9897 mips_no_prev_insn (false);
9900 case OPTION_NO_MIPS16
:
9901 mips_opts
.mips16
= 0;
9902 mips_no_prev_insn (false);
9905 case OPTION_MEMBEDDED_PIC
:
9906 mips_pic
= EMBEDDED_PIC
;
9907 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9909 as_bad (_("-G may not be used with embedded PIC code"));
9912 g_switch_value
= 0x7fffffff;
9916 /* When generating ELF code, we permit -KPIC and -call_shared to
9917 select SVR4_PIC, and -non_shared to select no PIC. This is
9918 intended to be compatible with Irix 5. */
9919 case OPTION_CALL_SHARED
:
9920 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9922 as_bad (_("-call_shared is supported only for ELF format"));
9925 mips_pic
= SVR4_PIC
;
9926 if (g_switch_seen
&& g_switch_value
!= 0)
9928 as_bad (_("-G may not be used with SVR4 PIC code"));
9934 case OPTION_NON_SHARED
:
9935 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9937 as_bad (_("-non_shared is supported only for ELF format"));
9943 /* The -xgot option tells the assembler to use 32 offsets when
9944 accessing the got in SVR4_PIC mode. It is for Irix
9949 #endif /* OBJ_ELF */
9952 if (! USE_GLOBAL_POINTER_OPT
)
9954 as_bad (_("-G is not supported for this configuration"));
9957 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9959 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9963 g_switch_value
= atoi (arg
);
9968 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
9971 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9973 as_bad (_("-32 is supported for ELF format only"));
9976 mips_opts
.abi
= O32_ABI
;
9980 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9982 as_bad (_("-n32 is supported for ELF format only"));
9985 mips_opts
.abi
= N32_ABI
;
9989 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9991 as_bad (_("-64 is supported for ELF format only"));
9994 mips_opts
.abi
= N64_ABI
;
9995 if (! support_64bit_objects())
9996 as_fatal (_("No compiled in support for 64 bit object file format"));
9998 #endif /* OBJ_ELF */
10001 file_mips_gp32
= 1;
10002 if (mips_opts
.abi
!= O32_ABI
)
10003 mips_opts
.abi
= NO_ABI
;
10007 file_mips_gp32
= 0;
10008 if (mips_opts
.abi
== O32_ABI
)
10009 mips_opts
.abi
= NO_ABI
;
10013 file_mips_fp32
= 1;
10014 if (mips_opts
.abi
!= O32_ABI
)
10015 mips_opts
.abi
= NO_ABI
;
10020 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10022 as_bad (_("-mabi is supported for ELF format only"));
10025 if (strcmp (arg
, "32") == 0)
10026 mips_opts
.abi
= O32_ABI
;
10027 else if (strcmp (arg
, "o64") == 0)
10028 mips_opts
.abi
= O64_ABI
;
10029 else if (strcmp (arg
, "n32") == 0)
10030 mips_opts
.abi
= N32_ABI
;
10031 else if (strcmp (arg
, "64") == 0)
10033 mips_opts
.abi
= N64_ABI
;
10034 if (! support_64bit_objects())
10035 as_fatal (_("No compiled in support for 64 bit object file "
10038 else if (strcmp (arg
, "eabi") == 0)
10039 mips_opts
.abi
= EABI_ABI
;
10041 mips_opts
.abi
= NO_ABI
;
10043 #endif /* OBJ_ELF */
10045 case OPTION_M7000_HILO_FIX
:
10046 mips_7000_hilo_fix
= true;
10049 case OPTION_NO_M7000_HILO_FIX
:
10050 mips_7000_hilo_fix
= false;
10061 show (stream
, string
, col_p
, first_p
)
10069 fprintf (stream
, "%24s", "");
10074 fprintf (stream
, ", ");
10078 if (*col_p
+ strlen (string
) > 72)
10080 fprintf (stream
, "\n%24s", "");
10084 fprintf (stream
, "%s", string
);
10085 *col_p
+= strlen (string
);
10091 md_show_usage (stream
)
10096 fprintf (stream
, _("\
10098 -membedded-pic generate embedded position independent code\n\
10099 -EB generate big endian output\n\
10100 -EL generate little endian output\n\
10101 -g, -g2 do not remove unneeded NOPs or swap branches\n\
10102 -G NUM allow referencing objects up to NUM bytes\n\
10103 implicitly with the gp register [default 8]\n"));
10104 fprintf (stream
, _("\
10105 -mips1 generate MIPS ISA I instructions\n\
10106 -mips2 generate MIPS ISA II instructions\n\
10107 -mips3 generate MIPS ISA III instructions\n\
10108 -mips4 generate MIPS ISA IV instructions\n\
10109 -mips5 generate MIPS ISA V instructions\n\
10110 -mips32 generate MIPS32 ISA instructions\n\
10111 -mips64 generate MIPS64 ISA instructions\n\
10112 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
10116 show (stream
, "2000", &column
, &first
);
10117 show (stream
, "3000", &column
, &first
);
10118 show (stream
, "3900", &column
, &first
);
10119 show (stream
, "4000", &column
, &first
);
10120 show (stream
, "4010", &column
, &first
);
10121 show (stream
, "4100", &column
, &first
);
10122 show (stream
, "4111", &column
, &first
);
10123 show (stream
, "4300", &column
, &first
);
10124 show (stream
, "4400", &column
, &first
);
10125 show (stream
, "4600", &column
, &first
);
10126 show (stream
, "4650", &column
, &first
);
10127 show (stream
, "5000", &column
, &first
);
10128 show (stream
, "5200", &column
, &first
);
10129 show (stream
, "5230", &column
, &first
);
10130 show (stream
, "5231", &column
, &first
);
10131 show (stream
, "5261", &column
, &first
);
10132 show (stream
, "5721", &column
, &first
);
10133 show (stream
, "6000", &column
, &first
);
10134 show (stream
, "8000", &column
, &first
);
10135 show (stream
, "10000", &column
, &first
);
10136 show (stream
, "12000", &column
, &first
);
10137 show (stream
, "sb1", &column
, &first
);
10138 fputc ('\n', stream
);
10140 fprintf (stream
, _("\
10141 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
10142 -no-mCPU don't generate code specific to CPU.\n\
10143 For -mCPU and -no-mCPU, CPU must be one of:\n"));
10147 show (stream
, "3900", &column
, &first
);
10148 show (stream
, "4010", &column
, &first
);
10149 show (stream
, "4100", &column
, &first
);
10150 show (stream
, "4650", &column
, &first
);
10151 fputc ('\n', stream
);
10153 fprintf (stream
, _("\
10154 -mips16 generate mips16 instructions\n\
10155 -no-mips16 do not generate mips16 instructions\n"));
10156 fprintf (stream
, _("\
10157 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
10158 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
10159 -O0 remove unneeded NOPs, do not swap branches\n\
10160 -O remove unneeded NOPs and swap branches\n\
10161 -n warn about NOPs generated from macros\n\
10162 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
10163 --trap, --no-break trap exception on div by 0 and mult overflow\n\
10164 --break, --no-trap break exception on div by 0 and mult overflow\n"));
10166 fprintf (stream
, _("\
10167 -KPIC, -call_shared generate SVR4 position independent code\n\
10168 -non_shared do not generate position independent code\n\
10169 -xgot assume a 32 bit GOT\n\
10170 -mabi=ABI create ABI conformant object file for:\n"));
10174 show (stream
, "32", &column
, &first
);
10175 show (stream
, "o64", &column
, &first
);
10176 show (stream
, "n32", &column
, &first
);
10177 show (stream
, "64", &column
, &first
);
10178 show (stream
, "eabi", &column
, &first
);
10180 fputc ('\n', stream
);
10182 fprintf (stream
, _("\
10183 -32 create o32 ABI object file (default)\n\
10184 -n32 create n32 ABI object file\n\
10185 -64 create 64 ABI object file\n"));
10190 mips_init_after_args ()
10192 /* initialize opcodes */
10193 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10194 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10198 md_pcrel_from (fixP
)
10201 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
10202 && fixP
->fx_addsy
!= (symbolS
*) NULL
10203 && ! S_IS_DEFINED (fixP
->fx_addsy
))
10205 /* This makes a branch to an undefined symbol be a branch to the
10206 current location. */
10207 if (mips_pic
== EMBEDDED_PIC
)
10213 /* return the address of the delay slot */
10214 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10217 /* This is called before the symbol table is processed. In order to
10218 work with gcc when using mips-tfile, we must keep all local labels.
10219 However, in other cases, we want to discard them. If we were
10220 called with -g, but we didn't see any debugging information, it may
10221 mean that gcc is smuggling debugging information through to
10222 mips-tfile, in which case we must generate all local labels. */
10225 mips_frob_file_before_adjust ()
10227 #ifndef NO_ECOFF_DEBUGGING
10228 if (ECOFF_DEBUGGING
10230 && ! ecoff_debugging_seen
)
10231 flag_keep_locals
= 1;
10235 /* Sort any unmatched HI16_S relocs so that they immediately precede
10236 the corresponding LO reloc. This is called before md_apply_fix3 and
10237 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10238 explicit use of the %hi modifier. */
10243 struct mips_hi_fixup
*l
;
10245 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10247 segment_info_type
*seginfo
;
10250 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10252 /* Check quickly whether the next fixup happens to be a matching
10254 if (l
->fixp
->fx_next
!= NULL
10255 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10256 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10257 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10260 /* Look through the fixups for this segment for a matching %lo.
10261 When we find one, move the %hi just in front of it. We do
10262 this in two passes. In the first pass, we try to find a
10263 unique %lo. In the second pass, we permit multiple %hi
10264 relocs for a single %lo (this is a GNU extension). */
10265 seginfo
= seg_info (l
->seg
);
10266 for (pass
= 0; pass
< 2; pass
++)
10271 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10273 /* Check whether this is a %lo fixup which matches l->fixp. */
10274 if (f
->fx_r_type
== BFD_RELOC_LO16
10275 && f
->fx_addsy
== l
->fixp
->fx_addsy
10276 && f
->fx_offset
== l
->fixp
->fx_offset
10279 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10280 || prev
->fx_addsy
!= f
->fx_addsy
10281 || prev
->fx_offset
!= f
->fx_offset
))
10285 /* Move l->fixp before f. */
10286 for (pf
= &seginfo
->fix_root
;
10288 pf
= &(*pf
)->fx_next
)
10289 assert (*pf
!= NULL
);
10291 *pf
= l
->fixp
->fx_next
;
10293 l
->fixp
->fx_next
= f
;
10295 seginfo
->fix_root
= l
->fixp
;
10297 prev
->fx_next
= l
->fixp
;
10308 #if 0 /* GCC code motion plus incomplete dead code elimination
10309 can leave a %hi without a %lo. */
10311 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10312 _("Unmatched %%hi reloc"));
10318 /* When generating embedded PIC code we need to use a special
10319 relocation to represent the difference of two symbols in the .text
10320 section (switch tables use a difference of this sort). See
10321 include/coff/mips.h for details. This macro checks whether this
10322 fixup requires the special reloc. */
10323 #define SWITCH_TABLE(fixp) \
10324 ((fixp)->fx_r_type == BFD_RELOC_32 \
10325 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10326 && (fixp)->fx_addsy != NULL \
10327 && (fixp)->fx_subsy != NULL \
10328 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10329 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10331 /* When generating embedded PIC code we must keep all PC relative
10332 relocations, in case the linker has to relax a call. We also need
10333 to keep relocations for switch table entries.
10335 We may have combined relocations without symbols in the N32/N64 ABI.
10336 We have to prevent gas from dropping them. */
10339 mips_force_relocation (fixp
)
10342 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10343 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10347 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10348 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10349 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10350 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10353 return (mips_pic
== EMBEDDED_PIC
10355 || SWITCH_TABLE (fixp
)
10356 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10357 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10362 mips_need_elf_addend_fixup (fixP
)
10365 return (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10366 || ((S_IS_WEAK (fixP
->fx_addsy
)
10367 || S_IS_EXTERN (fixP
->fx_addsy
))
10368 && !S_IS_COMMON (fixP
->fx_addsy
))
10369 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
10370 && (((bfd_get_section_flags (stdoutput
,
10371 S_GET_SEGMENT (fixP
->fx_addsy
))
10372 & SEC_LINK_ONCE
) != 0)
10373 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
10375 sizeof (".gnu.linkonce") - 1))));
10379 /* Apply a fixup to the object file. */
10382 md_apply_fix3 (fixP
, valP
, seg
)
10385 segT seg ATTRIBUTE_UNUSED
;
10387 unsigned char *buf
;
10391 assert (fixP
->fx_size
== 4
10392 || fixP
->fx_r_type
== BFD_RELOC_16
10393 || fixP
->fx_r_type
== BFD_RELOC_32
10394 || fixP
->fx_r_type
== BFD_RELOC_MIPS_JMP
10395 || fixP
->fx_r_type
== BFD_RELOC_HI16_S
10396 || fixP
->fx_r_type
== BFD_RELOC_LO16
10397 || fixP
->fx_r_type
== BFD_RELOC_GPREL16
10398 || fixP
->fx_r_type
== BFD_RELOC_MIPS_LITERAL
10399 || fixP
->fx_r_type
== BFD_RELOC_GPREL32
10400 || fixP
->fx_r_type
== BFD_RELOC_64
10401 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10402 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10403 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHEST
10404 || fixP
->fx_r_type
== BFD_RELOC_MIPS_HIGHER
10405 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SCN_DISP
10406 || fixP
->fx_r_type
== BFD_RELOC_MIPS_REL16
10407 || fixP
->fx_r_type
== BFD_RELOC_MIPS_RELGOT
10408 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10409 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10413 /* If we aren't adjusting this fixup to be against the section
10414 symbol, we need to adjust the value. */
10416 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10418 if (mips_need_elf_addend_fixup (fixP
))
10420 valueT symval
= S_GET_VALUE (fixP
->fx_addsy
);
10423 if (value
!= 0 && ! fixP
->fx_pcrel
)
10425 /* In this case, the bfd_install_relocation routine will
10426 incorrectly add the symbol value back in. We just want
10427 the addend to appear in the object file. */
10430 /* Make sure the addend is still non-zero. If it became zero
10431 after the last operation, set it to a spurious value and
10432 subtract the same value from the object file's contents. */
10437 /* The in-place addends for LO16 relocations are signed;
10438 leave the matching HI16 in-place addends as zero. */
10439 if (fixP
->fx_r_type
!= BFD_RELOC_HI16_S
)
10441 reloc_howto_type
*howto
;
10442 bfd_vma contents
, mask
, field
;
10444 howto
= bfd_reloc_type_lookup (stdoutput
,
10447 contents
= bfd_get_bits (fixP
->fx_frag
->fr_literal
10450 target_big_endian
);
10452 /* MASK has bits set where the relocation should go.
10453 FIELD is -value, shifted into the appropriate place
10454 for this relocation. */
10455 mask
= 1 << (howto
->bitsize
- 1);
10456 mask
= (((mask
- 1) << 1) | 1) << howto
->bitpos
;
10457 field
= (-value
>> howto
->rightshift
) << howto
->bitpos
;
10459 bfd_put_bits ((field
& mask
) | (contents
& ~mask
),
10460 fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10462 target_big_endian
);
10468 /* This code was generated using trial and error and so is
10469 fragile and not trustworthy. If you change it, you should
10470 rerun the elf-rel, elf-rel2, and empic testcases and ensure
10471 they still pass. */
10472 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
10474 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10476 /* BFD's REL handling, for MIPS, is _very_ weird.
10477 This gives the right results, but it can't possibly
10478 be the way things are supposed to work. */
10479 if ((fixP
->fx_r_type
!= BFD_RELOC_16_PCREL
10480 && fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
)
10481 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
10482 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10487 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc. */
10489 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10492 switch (fixP
->fx_r_type
)
10494 case BFD_RELOC_MIPS_JMP
:
10495 case BFD_RELOC_MIPS_SHIFT5
:
10496 case BFD_RELOC_MIPS_SHIFT6
:
10497 case BFD_RELOC_MIPS_GOT_DISP
:
10498 case BFD_RELOC_MIPS_GOT_PAGE
:
10499 case BFD_RELOC_MIPS_GOT_OFST
:
10500 case BFD_RELOC_MIPS_SUB
:
10501 case BFD_RELOC_MIPS_INSERT_A
:
10502 case BFD_RELOC_MIPS_INSERT_B
:
10503 case BFD_RELOC_MIPS_DELETE
:
10504 case BFD_RELOC_MIPS_HIGHEST
:
10505 case BFD_RELOC_MIPS_HIGHER
:
10506 case BFD_RELOC_MIPS_SCN_DISP
:
10507 case BFD_RELOC_MIPS_REL16
:
10508 case BFD_RELOC_MIPS_RELGOT
:
10509 case BFD_RELOC_MIPS_JALR
:
10510 case BFD_RELOC_HI16
:
10511 case BFD_RELOC_HI16_S
:
10512 case BFD_RELOC_GPREL16
:
10513 case BFD_RELOC_MIPS_LITERAL
:
10514 case BFD_RELOC_MIPS_CALL16
:
10515 case BFD_RELOC_MIPS_GOT16
:
10516 case BFD_RELOC_GPREL32
:
10517 case BFD_RELOC_MIPS_GOT_HI16
:
10518 case BFD_RELOC_MIPS_GOT_LO16
:
10519 case BFD_RELOC_MIPS_CALL_HI16
:
10520 case BFD_RELOC_MIPS_CALL_LO16
:
10521 case BFD_RELOC_MIPS16_GPREL
:
10522 if (fixP
->fx_pcrel
)
10523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10524 _("Invalid PC relative reloc"));
10525 /* Nothing needed to do. The value comes from the reloc entry */
10528 case BFD_RELOC_MIPS16_JMP
:
10529 /* We currently always generate a reloc against a symbol, which
10530 means that we don't want an addend even if the symbol is
10532 fixP
->fx_addnumber
= 0;
10535 case BFD_RELOC_PCREL_HI16_S
:
10536 /* The addend for this is tricky if it is internal, so we just
10537 do everything here rather than in bfd_install_relocation. */
10538 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10543 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10545 /* For an external symbol adjust by the address to make it
10546 pcrel_offset. We use the address of the RELLO reloc
10547 which follows this one. */
10548 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10549 + fixP
->fx_next
->fx_where
);
10551 value
= ((value
+ 0x8000) >> 16) & 0xffff;
10552 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10553 if (target_big_endian
)
10555 md_number_to_chars (buf
, value
, 2);
10558 case BFD_RELOC_PCREL_LO16
:
10559 /* The addend for this is tricky if it is internal, so we just
10560 do everything here rather than in bfd_install_relocation. */
10561 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10566 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
10567 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10568 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10569 if (target_big_endian
)
10571 md_number_to_chars (buf
, value
, 2);
10575 /* This is handled like BFD_RELOC_32, but we output a sign
10576 extended value if we are only 32 bits. */
10578 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10580 if (8 <= sizeof (valueT
))
10581 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10588 w1
= w2
= fixP
->fx_where
;
10589 if (target_big_endian
)
10593 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10594 if ((value
& 0x80000000) != 0)
10598 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10603 case BFD_RELOC_RVA
:
10605 /* If we are deleting this reloc entry, we must fill in the
10606 value now. This can happen if we have a .word which is not
10607 resolved when it appears but is later defined. We also need
10608 to fill in the value if this is an embedded PIC switch table
10611 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10612 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10617 /* If we are deleting this reloc entry, we must fill in the
10619 assert (fixP
->fx_size
== 2);
10621 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10625 case BFD_RELOC_LO16
:
10626 /* When handling an embedded PIC switch statement, we can wind
10627 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10630 if (value
+ 0x8000 > 0xffff)
10631 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10632 _("relocation overflow"));
10633 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10634 if (target_big_endian
)
10636 md_number_to_chars (buf
, value
, 2);
10640 case BFD_RELOC_16_PCREL_S2
:
10641 if ((value
& 0x3) != 0)
10642 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10643 _("Branch to odd address (%lx)"), (long) value
);
10645 /* Fall through. */
10647 case BFD_RELOC_16_PCREL
:
10649 * We need to save the bits in the instruction since fixup_segment()
10650 * might be deleting the relocation entry (i.e., a branch within
10651 * the current segment).
10653 if (!fixP
->fx_done
&& value
!= 0)
10655 /* If 'value' is zero, the remaining reloc code won't actually
10656 do the store, so it must be done here. This is probably
10657 a bug somewhere. */
10658 if (!fixP
->fx_done
)
10659 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10661 value
= (offsetT
) value
>> 2;
10663 /* update old instruction data */
10664 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10665 if (target_big_endian
)
10666 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10668 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10670 if (value
+ 0x8000 <= 0xffff)
10671 insn
|= value
& 0xffff;
10674 /* The branch offset is too large. If this is an
10675 unconditional branch, and we are not generating PIC code,
10676 we can convert it to an absolute jump instruction. */
10677 if (mips_pic
== NO_PIC
10679 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10680 && (fixP
->fx_frag
->fr_address
10681 < text_section
->vma
+ text_section
->_raw_size
)
10682 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10683 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10684 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10686 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10687 insn
= 0x0c000000; /* jal */
10689 insn
= 0x08000000; /* j */
10690 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10692 fixP
->fx_addsy
= section_symbol (text_section
);
10693 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10697 /* FIXME. It would be possible in principle to handle
10698 conditional branches which overflow. They could be
10699 transformed into a branch around a jump. This would
10700 require setting up variant frags for each different
10701 branch type. The native MIPS assembler attempts to
10702 handle these cases, but it appears to do it
10704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10705 _("Branch out of range"));
10709 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10712 case BFD_RELOC_VTABLE_INHERIT
:
10715 && !S_IS_DEFINED (fixP
->fx_addsy
)
10716 && !S_IS_WEAK (fixP
->fx_addsy
))
10717 S_SET_WEAK (fixP
->fx_addsy
);
10720 case BFD_RELOC_VTABLE_ENTRY
:
10734 const struct mips_opcode
*p
;
10735 int treg
, sreg
, dreg
, shamt
;
10740 for (i
= 0; i
< NUMOPCODES
; ++i
)
10742 p
= &mips_opcodes
[i
];
10743 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10745 printf ("%08lx %s\t", oc
, p
->name
);
10746 treg
= (oc
>> 16) & 0x1f;
10747 sreg
= (oc
>> 21) & 0x1f;
10748 dreg
= (oc
>> 11) & 0x1f;
10749 shamt
= (oc
>> 6) & 0x1f;
10751 for (args
= p
->args
;; ++args
)
10762 printf ("%c", *args
);
10766 assert (treg
== sreg
);
10767 printf ("$%d,$%d", treg
, sreg
);
10772 printf ("$%d", dreg
);
10777 printf ("$%d", treg
);
10781 printf ("0x%x", treg
);
10786 printf ("$%d", sreg
);
10790 printf ("0x%08lx", oc
& 0x1ffffff);
10797 printf ("%d", imm
);
10802 printf ("$%d", shamt
);
10813 printf (_("%08lx UNDEFINED\n"), oc
);
10824 name
= input_line_pointer
;
10825 c
= get_symbol_end ();
10826 p
= (symbolS
*) symbol_find_or_make (name
);
10827 *input_line_pointer
= c
;
10831 /* Align the current frag to a given power of two. The MIPS assembler
10832 also automatically adjusts any preceding label. */
10835 mips_align (to
, fill
, label
)
10840 mips_emit_delays (false);
10841 frag_align (to
, fill
, 0);
10842 record_alignment (now_seg
, to
);
10845 assert (S_GET_SEGMENT (label
) == now_seg
);
10846 symbol_set_frag (label
, frag_now
);
10847 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10851 /* Align to a given power of two. .align 0 turns off the automatic
10852 alignment used by the data creating pseudo-ops. */
10856 int x ATTRIBUTE_UNUSED
;
10859 register long temp_fill
;
10860 long max_alignment
= 15;
10864 o Note that the assembler pulls down any immediately preceeding label
10865 to the aligned address.
10866 o It's not documented but auto alignment is reinstated by
10867 a .align pseudo instruction.
10868 o Note also that after auto alignment is turned off the mips assembler
10869 issues an error on attempt to assemble an improperly aligned data item.
10874 temp
= get_absolute_expression ();
10875 if (temp
> max_alignment
)
10876 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10879 as_warn (_("Alignment negative: 0 assumed."));
10882 if (*input_line_pointer
== ',')
10884 input_line_pointer
++;
10885 temp_fill
= get_absolute_expression ();
10892 mips_align (temp
, (int) temp_fill
,
10893 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10900 demand_empty_rest_of_line ();
10904 mips_flush_pending_output ()
10906 mips_emit_delays (false);
10907 mips_clear_insn_labels ();
10916 /* When generating embedded PIC code, we only use the .text, .lit8,
10917 .sdata and .sbss sections. We change the .data and .rdata
10918 pseudo-ops to use .sdata. */
10919 if (mips_pic
== EMBEDDED_PIC
10920 && (sec
== 'd' || sec
== 'r'))
10924 /* The ELF backend needs to know that we are changing sections, so
10925 that .previous works correctly. We could do something like check
10926 for an obj_section_change_hook macro, but that might be confusing
10927 as it would not be appropriate to use it in the section changing
10928 functions in read.c, since obj-elf.c intercepts those. FIXME:
10929 This should be cleaner, somehow. */
10930 obj_elf_section_change_hook ();
10933 mips_emit_delays (false);
10943 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10944 demand_empty_rest_of_line ();
10948 if (USE_GLOBAL_POINTER_OPT
)
10950 seg
= subseg_new (RDATA_SECTION_NAME
,
10951 (subsegT
) get_absolute_expression ());
10952 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10954 bfd_set_section_flags (stdoutput
, seg
,
10960 if (strcmp (TARGET_OS
, "elf") != 0)
10961 record_alignment (seg
, 4);
10963 demand_empty_rest_of_line ();
10967 as_bad (_("No read only data section in this object file format"));
10968 demand_empty_rest_of_line ();
10974 if (USE_GLOBAL_POINTER_OPT
)
10976 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10977 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10979 bfd_set_section_flags (stdoutput
, seg
,
10980 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10982 if (strcmp (TARGET_OS
, "elf") != 0)
10983 record_alignment (seg
, 4);
10985 demand_empty_rest_of_line ();
10990 as_bad (_("Global pointers not supported; recompile -G 0"));
10991 demand_empty_rest_of_line ();
11000 mips_enable_auto_align ()
11011 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11012 mips_emit_delays (false);
11013 if (log_size
> 0 && auto_align
)
11014 mips_align (log_size
, 0, label
);
11015 mips_clear_insn_labels ();
11016 cons (1 << log_size
);
11020 s_float_cons (type
)
11025 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11027 mips_emit_delays (false);
11032 mips_align (3, 0, label
);
11034 mips_align (2, 0, label
);
11037 mips_clear_insn_labels ();
11042 /* Handle .globl. We need to override it because on Irix 5 you are
11045 where foo is an undefined symbol, to mean that foo should be
11046 considered to be the address of a function. */
11050 int x ATTRIBUTE_UNUSED
;
11057 name
= input_line_pointer
;
11058 c
= get_symbol_end ();
11059 symbolP
= symbol_find_or_make (name
);
11060 *input_line_pointer
= c
;
11061 SKIP_WHITESPACE ();
11063 /* On Irix 5, every global symbol that is not explicitly labelled as
11064 being a function is apparently labelled as being an object. */
11067 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11072 secname
= input_line_pointer
;
11073 c
= get_symbol_end ();
11074 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11076 as_bad (_("%s: no such section"), secname
);
11077 *input_line_pointer
= c
;
11079 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11080 flag
= BSF_FUNCTION
;
11083 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11085 S_SET_EXTERNAL (symbolP
);
11086 demand_empty_rest_of_line ();
11091 int x ATTRIBUTE_UNUSED
;
11096 opt
= input_line_pointer
;
11097 c
= get_symbol_end ();
11101 /* FIXME: What does this mean? */
11103 else if (strncmp (opt
, "pic", 3) == 0)
11107 i
= atoi (opt
+ 3);
11111 mips_pic
= SVR4_PIC
;
11113 as_bad (_(".option pic%d not supported"), i
);
11115 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11117 if (g_switch_seen
&& g_switch_value
!= 0)
11118 as_warn (_("-G may not be used with SVR4 PIC code"));
11119 g_switch_value
= 0;
11120 bfd_set_gp_size (stdoutput
, 0);
11124 as_warn (_("Unrecognized option \"%s\""), opt
);
11126 *input_line_pointer
= c
;
11127 demand_empty_rest_of_line ();
11130 /* This structure is used to hold a stack of .set values. */
11132 struct mips_option_stack
11134 struct mips_option_stack
*next
;
11135 struct mips_set_options options
;
11138 static struct mips_option_stack
*mips_opts_stack
;
11140 /* Handle the .set pseudo-op. */
11144 int x ATTRIBUTE_UNUSED
;
11146 char *name
= input_line_pointer
, ch
;
11148 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11149 input_line_pointer
++;
11150 ch
= *input_line_pointer
;
11151 *input_line_pointer
= '\0';
11153 if (strcmp (name
, "reorder") == 0)
11155 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11157 /* If we still have pending nops, we can discard them. The
11158 usual nop handling will insert any that are still
11160 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11161 * (mips_opts
.mips16
? 2 : 4));
11162 prev_nop_frag
= NULL
;
11164 mips_opts
.noreorder
= 0;
11166 else if (strcmp (name
, "noreorder") == 0)
11168 mips_emit_delays (true);
11169 mips_opts
.noreorder
= 1;
11170 mips_any_noreorder
= 1;
11172 else if (strcmp (name
, "at") == 0)
11174 mips_opts
.noat
= 0;
11176 else if (strcmp (name
, "noat") == 0)
11178 mips_opts
.noat
= 1;
11180 else if (strcmp (name
, "macro") == 0)
11182 mips_opts
.warn_about_macros
= 0;
11184 else if (strcmp (name
, "nomacro") == 0)
11186 if (mips_opts
.noreorder
== 0)
11187 as_bad (_("`noreorder' must be set before `nomacro'"));
11188 mips_opts
.warn_about_macros
= 1;
11190 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11192 mips_opts
.nomove
= 0;
11194 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11196 mips_opts
.nomove
= 1;
11198 else if (strcmp (name
, "bopt") == 0)
11200 mips_opts
.nobopt
= 0;
11202 else if (strcmp (name
, "nobopt") == 0)
11204 mips_opts
.nobopt
= 1;
11206 else if (strcmp (name
, "mips16") == 0
11207 || strcmp (name
, "MIPS-16") == 0)
11208 mips_opts
.mips16
= 1;
11209 else if (strcmp (name
, "nomips16") == 0
11210 || strcmp (name
, "noMIPS-16") == 0)
11211 mips_opts
.mips16
= 0;
11212 else if (strncmp (name
, "mips", 4) == 0)
11216 /* Permit the user to change the ISA on the fly. Needless to
11217 say, misuse can cause serious problems. */
11218 isa
= atoi (name
+ 4);
11222 mips_opts
.gp32
= file_mips_gp32
;
11223 mips_opts
.fp32
= file_mips_fp32
;
11224 mips_opts
.abi
= file_mips_abi
;
11229 mips_opts
.gp32
= 1;
11230 mips_opts
.fp32
= 1;
11236 /* Loosen ABI register width restriction. */
11237 if (mips_opts
.abi
== O32_ABI
)
11238 mips_opts
.abi
= NO_ABI
;
11239 mips_opts
.gp32
= 0;
11240 mips_opts
.fp32
= 0;
11243 as_bad (_("unknown ISA level %s"), name
+ 4);
11249 case 0: mips_opts
.isa
= file_mips_isa
; break;
11250 case 1: mips_opts
.isa
= ISA_MIPS1
; break;
11251 case 2: mips_opts
.isa
= ISA_MIPS2
; break;
11252 case 3: mips_opts
.isa
= ISA_MIPS3
; break;
11253 case 4: mips_opts
.isa
= ISA_MIPS4
; break;
11254 case 5: mips_opts
.isa
= ISA_MIPS5
; break;
11255 case 32: mips_opts
.isa
= ISA_MIPS32
; break;
11256 case 64: mips_opts
.isa
= ISA_MIPS64
; break;
11257 default: as_bad (_("unknown ISA level %s"), name
+ 4); break;
11260 else if (strcmp (name
, "autoextend") == 0)
11261 mips_opts
.noautoextend
= 0;
11262 else if (strcmp (name
, "noautoextend") == 0)
11263 mips_opts
.noautoextend
= 1;
11264 else if (strcmp (name
, "push") == 0)
11266 struct mips_option_stack
*s
;
11268 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11269 s
->next
= mips_opts_stack
;
11270 s
->options
= mips_opts
;
11271 mips_opts_stack
= s
;
11273 else if (strcmp (name
, "pop") == 0)
11275 struct mips_option_stack
*s
;
11277 s
= mips_opts_stack
;
11279 as_bad (_(".set pop with no .set push"));
11282 /* If we're changing the reorder mode we need to handle
11283 delay slots correctly. */
11284 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11285 mips_emit_delays (true);
11286 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11288 if (prev_nop_frag
!= NULL
)
11290 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11291 * (mips_opts
.mips16
? 2 : 4));
11292 prev_nop_frag
= NULL
;
11296 mips_opts
= s
->options
;
11297 mips_opts_stack
= s
->next
;
11303 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11305 *input_line_pointer
= ch
;
11306 demand_empty_rest_of_line ();
11309 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11310 .option pic2. It means to generate SVR4 PIC calls. */
11313 s_abicalls (ignore
)
11314 int ignore ATTRIBUTE_UNUSED
;
11316 mips_pic
= SVR4_PIC
;
11317 if (USE_GLOBAL_POINTER_OPT
)
11319 if (g_switch_seen
&& g_switch_value
!= 0)
11320 as_warn (_("-G may not be used with SVR4 PIC code"));
11321 g_switch_value
= 0;
11323 bfd_set_gp_size (stdoutput
, 0);
11324 demand_empty_rest_of_line ();
11327 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11328 PIC code. It sets the $gp register for the function based on the
11329 function address, which is in the register named in the argument.
11330 This uses a relocation against _gp_disp, which is handled specially
11331 by the linker. The result is:
11332 lui $gp,%hi(_gp_disp)
11333 addiu $gp,$gp,%lo(_gp_disp)
11334 addu $gp,$gp,.cpload argument
11335 The .cpload argument is normally $25 == $t9. */
11339 int ignore ATTRIBUTE_UNUSED
;
11344 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11345 .cpload is ignored. */
11346 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11352 /* .cpload should be in a .set noreorder section. */
11353 if (mips_opts
.noreorder
== 0)
11354 as_warn (_(".cpload not in noreorder section"));
11356 ex
.X_op
= O_symbol
;
11357 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
11358 ex
.X_op_symbol
= NULL
;
11359 ex
.X_add_number
= 0;
11361 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11362 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11364 macro_build_lui (NULL
, &icnt
, &ex
, GP
);
11365 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
11366 (int) BFD_RELOC_LO16
);
11368 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
11369 GP
, GP
, tc_get_register (0));
11371 demand_empty_rest_of_line ();
11374 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11375 .cpsetup $reg1, offset|$reg2, label
11377 If offset is given, this results in:
11378 sd $gp, offset($sp)
11379 lui $gp, %hi(%neg(%gp_rel(label)))
11380 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11381 addu $gp, $gp, $reg1
11383 If $reg2 is given, this results in:
11384 daddu $reg2, $gp, $0
11385 lui $gp, %hi(%neg(%gp_rel(label)))
11386 daddiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11387 addu $gp, $gp, $reg1
11391 int ignore ATTRIBUTE_UNUSED
;
11393 expressionS ex_off
;
11394 expressionS ex_sym
;
11399 /* If we are not generating SVR4 PIC code, .cpload is ignored.
11400 We also need NewABI support. */
11401 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11407 reg1
= tc_get_register (0);
11408 SKIP_WHITESPACE ();
11409 if (*input_line_pointer
!= ',')
11411 as_bad (_("missing argument separator ',' for .cpsetup"));
11415 input_line_pointer
++;
11416 SKIP_WHITESPACE ();
11417 if (*input_line_pointer
== '$')
11418 mips_cpreturn_register
= tc_get_register (0);
11420 mips_cpreturn_offset
= get_absolute_expression ();
11421 SKIP_WHITESPACE ();
11422 if (*input_line_pointer
!= ',')
11424 as_bad (_("missing argument separator ',' for .cpsetup"));
11428 input_line_pointer
++;
11429 SKIP_WHITESPACE ();
11430 sym
= input_line_pointer
;
11431 while (ISALNUM (*input_line_pointer
))
11432 input_line_pointer
++;
11433 *input_line_pointer
= 0;
11435 ex_sym
.X_op
= O_symbol
;
11436 ex_sym
.X_add_symbol
= symbol_find_or_make (sym
);
11437 ex_sym
.X_op_symbol
= NULL
;
11438 ex_sym
.X_add_number
= 0;
11440 if (mips_cpreturn_register
== -1)
11442 ex_off
.X_op
= O_constant
;
11443 ex_off
.X_add_symbol
= NULL
;
11444 ex_off
.X_op_symbol
= NULL
;
11445 ex_off
.X_add_number
= mips_cpreturn_offset
;
11447 macro_build ((char *) NULL
, &icnt
, &ex_off
, "sd", "t,o(b)",
11448 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11451 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11452 "d,v,t", mips_cpreturn_register
, mips_gp_register
, 0);
11454 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "lui", "t,u", mips_gp_register
,
11455 (int) BFD_RELOC_GPREL16
);
11456 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11457 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11458 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11459 NULL
, 0, 0, BFD_RELOC_HI16_S
);
11460 macro_build ((char *) NULL
, &icnt
, &ex_sym
, "addiu", "t,r,j",
11461 mips_gp_register
, mips_gp_register
, (int) BFD_RELOC_GPREL16
);
11462 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11463 NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
11464 fix_new (frag_now
, (char *) prev_insn_fixp
- 4 - frag_now
->fr_literal
, 0,
11465 NULL
, 0, 0, BFD_RELOC_LO16
);
11466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11467 "d,v,t", mips_gp_register
, mips_gp_register
, reg1
);
11469 demand_empty_rest_of_line ();
11474 int ignore ATTRIBUTE_UNUSED
;
11476 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11477 .cplocal is ignored. */
11478 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11484 mips_gp_register
= tc_get_register (0);
11487 /* Handle the .cprestore pseudo-op. This stores $gp into a given
11488 offset from $sp. The offset is remembered, and after making a PIC
11489 call $gp is restored from that location. */
11492 s_cprestore (ignore
)
11493 int ignore ATTRIBUTE_UNUSED
;
11498 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11499 .cprestore is ignored. */
11500 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11506 mips_cprestore_offset
= get_absolute_expression ();
11507 mips_cprestore_valid
= 1;
11509 ex
.X_op
= O_constant
;
11510 ex
.X_add_symbol
= NULL
;
11511 ex
.X_op_symbol
= NULL
;
11512 ex
.X_add_number
= mips_cprestore_offset
;
11514 macro_build ((char *) NULL
, &icnt
, &ex
,
11515 HAVE_32BIT_ADDRESSES
? "sw" : "sd",
11516 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
11518 demand_empty_rest_of_line ();
11521 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
11522 was given in the preceeding .gpsetup, it results in:
11523 ld $gp, offset($sp)
11525 If a register $reg2 was given there, it results in:
11526 daddiu $gp, $gp, $reg2
11529 s_cpreturn (ignore
)
11530 int ignore ATTRIBUTE_UNUSED
;
11535 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
11536 We also need NewABI support. */
11537 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11543 if (mips_cpreturn_register
== -1)
11545 ex
.X_op
= O_constant
;
11546 ex
.X_add_symbol
= NULL
;
11547 ex
.X_op_symbol
= NULL
;
11548 ex
.X_add_number
= mips_cpreturn_offset
;
11550 macro_build ((char *) NULL
, &icnt
, &ex
, "ld", "t,o(b)",
11551 mips_gp_register
, (int) BFD_RELOC_LO16
, SP
);
11554 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "daddu",
11555 "d,v,t", mips_gp_register
, mips_cpreturn_register
, 0);
11557 demand_empty_rest_of_line ();
11560 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
11561 code. It sets the offset to use in gp_rel relocations. */
11565 int ignore ATTRIBUTE_UNUSED
;
11567 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
11568 We also need NewABI support. */
11569 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11575 mips_cpreturn_offset
= get_absolute_expression ();
11577 demand_empty_rest_of_line ();
11580 /* Handle the .gpword pseudo-op. This is used when generating PIC
11581 code. It generates a 32 bit GP relative reloc. */
11585 int ignore ATTRIBUTE_UNUSED
;
11591 /* When not generating PIC code, this is treated as .word. */
11592 if (mips_pic
!= SVR4_PIC
)
11598 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11599 mips_emit_delays (true);
11601 mips_align (2, 0, label
);
11602 mips_clear_insn_labels ();
11606 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11608 as_bad (_("Unsupported use of .gpword"));
11609 ignore_rest_of_line ();
11613 md_number_to_chars (p
, (valueT
) 0, 4);
11614 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
11615 BFD_RELOC_GPREL32
);
11617 demand_empty_rest_of_line ();
11620 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11621 tables in SVR4 PIC code. */
11625 int ignore ATTRIBUTE_UNUSED
;
11630 /* This is ignored when not generating SVR4 PIC code or if this is NewABI
11632 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11638 /* Add $gp to the register named as an argument. */
11639 reg
= tc_get_register (0);
11640 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11641 HAVE_32BIT_ADDRESSES
? "addu" : "daddu",
11642 "d,v,t", reg
, reg
, GP
);
11644 demand_empty_rest_of_line ();
11647 /* Handle the .insn pseudo-op. This marks instruction labels in
11648 mips16 mode. This permits the linker to handle them specially,
11649 such as generating jalx instructions when needed. We also make
11650 them odd for the duration of the assembly, in order to generate the
11651 right sort of code. We will make them even in the adjust_symtab
11652 routine, while leaving them marked. This is convenient for the
11653 debugger and the disassembler. The linker knows to make them odd
11658 int ignore ATTRIBUTE_UNUSED
;
11660 if (mips_opts
.mips16
)
11661 mips16_mark_labels ();
11663 demand_empty_rest_of_line ();
11666 /* Handle a .stabn directive. We need these in order to mark a label
11667 as being a mips16 text label correctly. Sometimes the compiler
11668 will emit a label, followed by a .stabn, and then switch sections.
11669 If the label and .stabn are in mips16 mode, then the label is
11670 really a mips16 text label. */
11676 if (type
== 'n' && mips_opts
.mips16
)
11677 mips16_mark_labels ();
11682 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11686 s_mips_weakext (ignore
)
11687 int ignore ATTRIBUTE_UNUSED
;
11694 name
= input_line_pointer
;
11695 c
= get_symbol_end ();
11696 symbolP
= symbol_find_or_make (name
);
11697 S_SET_WEAK (symbolP
);
11698 *input_line_pointer
= c
;
11700 SKIP_WHITESPACE ();
11702 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11704 if (S_IS_DEFINED (symbolP
))
11706 as_bad ("ignoring attempt to redefine symbol %s",
11707 S_GET_NAME (symbolP
));
11708 ignore_rest_of_line ();
11712 if (*input_line_pointer
== ',')
11714 ++input_line_pointer
;
11715 SKIP_WHITESPACE ();
11719 if (exp
.X_op
!= O_symbol
)
11721 as_bad ("bad .weakext directive");
11722 ignore_rest_of_line();
11725 symbol_set_value_expression (symbolP
, &exp
);
11728 demand_empty_rest_of_line ();
11731 /* Parse a register string into a number. Called from the ECOFF code
11732 to parse .frame. The argument is non-zero if this is the frame
11733 register, so that we can record it in mips_frame_reg. */
11736 tc_get_register (frame
)
11741 SKIP_WHITESPACE ();
11742 if (*input_line_pointer
++ != '$')
11744 as_warn (_("expected `$'"));
11747 else if (ISDIGIT (*input_line_pointer
))
11749 reg
= get_absolute_expression ();
11750 if (reg
< 0 || reg
>= 32)
11752 as_warn (_("Bad register number"));
11758 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11760 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11762 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11764 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11768 as_warn (_("Unrecognized register name"));
11771 input_line_pointer
+= 2;
11775 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11776 mips_frame_reg_valid
= 1;
11777 mips_cprestore_valid
= 0;
11783 md_section_align (seg
, addr
)
11787 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11790 /* We don't need to align ELF sections to the full alignment.
11791 However, Irix 5 may prefer that we align them at least to a 16
11792 byte boundary. We don't bother to align the sections if we are
11793 targeted for an embedded system. */
11794 if (strcmp (TARGET_OS
, "elf") == 0)
11800 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11803 /* Utility routine, called from above as well. If called while the
11804 input file is still being read, it's only an approximation. (For
11805 example, a symbol may later become defined which appeared to be
11806 undefined earlier.) */
11809 nopic_need_relax (sym
, before_relaxing
)
11811 int before_relaxing
;
11816 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
11818 const char *symname
;
11821 /* Find out whether this symbol can be referenced off the GP
11822 register. It can be if it is smaller than the -G size or if
11823 it is in the .sdata or .sbss section. Certain symbols can
11824 not be referenced off the GP, although it appears as though
11826 symname
= S_GET_NAME (sym
);
11827 if (symname
!= (const char *) NULL
11828 && (strcmp (symname
, "eprol") == 0
11829 || strcmp (symname
, "etext") == 0
11830 || strcmp (symname
, "_gp") == 0
11831 || strcmp (symname
, "edata") == 0
11832 || strcmp (symname
, "_fbss") == 0
11833 || strcmp (symname
, "_fdata") == 0
11834 || strcmp (symname
, "_ftext") == 0
11835 || strcmp (symname
, "end") == 0
11836 || strcmp (symname
, "_gp_disp") == 0))
11838 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11840 #ifndef NO_ECOFF_DEBUGGING
11841 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
11842 && (symbol_get_obj (sym
)->ecoff_extern_size
11843 <= g_switch_value
))
11845 /* We must defer this decision until after the whole
11846 file has been read, since there might be a .extern
11847 after the first use of this symbol. */
11848 || (before_relaxing
11849 #ifndef NO_ECOFF_DEBUGGING
11850 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
11852 && S_GET_VALUE (sym
) == 0)
11853 || (S_GET_VALUE (sym
) != 0
11854 && S_GET_VALUE (sym
) <= g_switch_value
)))
11858 const char *segname
;
11860 segname
= segment_name (S_GET_SEGMENT (sym
));
11861 assert (strcmp (segname
, ".lit8") != 0
11862 && strcmp (segname
, ".lit4") != 0);
11863 change
= (strcmp (segname
, ".sdata") != 0
11864 && strcmp (segname
, ".sbss") != 0
11865 && strncmp (segname
, ".sdata.", 7) != 0
11866 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
11871 /* We are not optimizing for the GP register. */
11875 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11876 extended opcode. SEC is the section the frag is in. */
11879 mips16_extended_frag (fragp
, sec
, stretch
)
11885 register const struct mips16_immed_operand
*op
;
11887 int mintiny
, maxtiny
;
11891 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11893 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11896 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11897 op
= mips16_immed_operands
;
11898 while (op
->type
!= type
)
11901 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11906 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11909 maxtiny
= 1 << op
->nbits
;
11914 maxtiny
= (1 << op
->nbits
) - 1;
11919 mintiny
= - (1 << (op
->nbits
- 1));
11920 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11923 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
11924 val
= S_GET_VALUE (fragp
->fr_symbol
);
11925 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11931 /* We won't have the section when we are called from
11932 mips_relax_frag. However, we will always have been called
11933 from md_estimate_size_before_relax first. If this is a
11934 branch to a different section, we mark it as such. If SEC is
11935 NULL, and the frag is not marked, then it must be a branch to
11936 the same section. */
11939 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11944 /* Must have been called from md_estimate_size_before_relax. */
11947 fragp
->fr_subtype
=
11948 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11950 /* FIXME: We should support this, and let the linker
11951 catch branches and loads that are out of range. */
11952 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11953 _("unsupported PC relative reference to different section"));
11957 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
11958 /* Assume non-extended on the first relaxation pass.
11959 The address we have calculated will be bogus if this is
11960 a forward branch to another frag, as the forward frag
11961 will have fr_address == 0. */
11965 /* In this case, we know for sure that the symbol fragment is in
11966 the same section. If the relax_marker of the symbol fragment
11967 differs from the relax_marker of this fragment, we have not
11968 yet adjusted the symbol fragment fr_address. We want to add
11969 in STRETCH in order to get a better estimate of the address.
11970 This particularly matters because of the shift bits. */
11972 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
11976 /* Adjust stretch for any alignment frag. Note that if have
11977 been expanding the earlier code, the symbol may be
11978 defined in what appears to be an earlier frag. FIXME:
11979 This doesn't handle the fr_subtype field, which specifies
11980 a maximum number of bytes to skip when doing an
11982 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
11984 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11987 stretch
= - ((- stretch
)
11988 & ~ ((1 << (int) f
->fr_offset
) - 1));
11990 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11999 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12001 /* The base address rules are complicated. The base address of
12002 a branch is the following instruction. The base address of a
12003 PC relative load or add is the instruction itself, but if it
12004 is in a delay slot (in which case it can not be extended) use
12005 the address of the instruction whose delay slot it is in. */
12006 if (type
== 'p' || type
== 'q')
12010 /* If we are currently assuming that this frag should be
12011 extended, then, the current address is two bytes
12013 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12016 /* Ignore the low bit in the target, since it will be set
12017 for a text label. */
12018 if ((val
& 1) != 0)
12021 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12023 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12026 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12028 /* Branch offsets have an implicit 0 in the lowest bit. */
12029 if (type
== 'p' || type
== 'q')
12032 /* If any of the shifted bits are set, we must use an extended
12033 opcode. If the address depends on the size of this
12034 instruction, this can lead to a loop, so we arrange to always
12035 use an extended opcode. We only check this when we are in
12036 the main relaxation loop, when SEC is NULL. */
12037 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12039 fragp
->fr_subtype
=
12040 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12044 /* If we are about to mark a frag as extended because the value
12045 is precisely maxtiny + 1, then there is a chance of an
12046 infinite loop as in the following code:
12051 In this case when the la is extended, foo is 0x3fc bytes
12052 away, so the la can be shrunk, but then foo is 0x400 away, so
12053 the la must be extended. To avoid this loop, we mark the
12054 frag as extended if it was small, and is about to become
12055 extended with a value of maxtiny + 1. */
12056 if (val
== ((maxtiny
+ 1) << op
->shift
)
12057 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12060 fragp
->fr_subtype
=
12061 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12065 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12066 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12068 if ((val
& ((1 << op
->shift
) - 1)) != 0
12069 || val
< (mintiny
<< op
->shift
)
12070 || val
> (maxtiny
<< op
->shift
))
12076 /* Estimate the size of a frag before relaxing. Unless this is the
12077 mips16, we are not really relaxing here, and the final size is
12078 encoded in the subtype information. For the mips16, we have to
12079 decide whether we are using an extended opcode or not. */
12082 md_estimate_size_before_relax (fragp
, segtype
)
12087 boolean linkonce
= false;
12089 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12091 if (mips16_extended_frag (fragp
, segtype
, 0))
12093 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12098 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12103 if (mips_pic
== NO_PIC
)
12105 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12107 else if (mips_pic
== SVR4_PIC
)
12112 sym
= fragp
->fr_symbol
;
12114 /* Handle the case of a symbol equated to another symbol. */
12115 while (symbol_equated_reloc_p (sym
))
12119 /* It's possible to get a loop here in a badly written
12121 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12127 symsec
= S_GET_SEGMENT (sym
);
12129 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12130 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12132 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12136 /* The GNU toolchain uses an extension for ELF: a section
12137 beginning with the magic string .gnu.linkonce is a linkonce
12139 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12140 sizeof ".gnu.linkonce" - 1) == 0)
12144 /* This must duplicate the test in adjust_reloc_syms. */
12145 change
= (symsec
!= &bfd_und_section
12146 && symsec
!= &bfd_abs_section
12147 && ! bfd_is_com_section (symsec
)
12150 /* A global or weak symbol is treated as external. */
12151 && (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12152 && ! (S_IS_EXTERN (sym
) || S_IS_WEAK (sym
)))
12161 /* Record the offset to the first reloc in the fr_opcode field.
12162 This lets md_convert_frag and tc_gen_reloc know that the code
12163 must be expanded. */
12164 fragp
->fr_opcode
= (fragp
->fr_literal
12166 - RELAX_OLD (fragp
->fr_subtype
)
12167 + RELAX_RELOC1 (fragp
->fr_subtype
));
12168 /* FIXME: This really needs as_warn_where. */
12169 if (RELAX_WARN (fragp
->fr_subtype
))
12170 as_warn (_("AT used after \".set noat\" or macro used after "
12171 "\".set nomacro\""));
12173 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
12179 /* This is called to see whether a reloc against a defined symbol
12180 should be converted into a reloc against a section. Don't adjust
12181 MIPS16 jump relocations, so we don't have to worry about the format
12182 of the offset in the .o file. Don't adjust relocations against
12183 mips16 symbols, so that the linker can find them if it needs to set
12187 mips_fix_adjustable (fixp
)
12191 /* Prevent all adjustments to global symbols. */
12192 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12193 && (S_IS_EXTERN (fixp
->fx_addsy
) || S_IS_WEAK (fixp
->fx_addsy
)))
12196 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12198 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12199 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12201 if (fixp
->fx_addsy
== NULL
)
12204 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12205 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12206 && fixp
->fx_subsy
== NULL
)
12212 /* Translate internal representation of relocation info to BFD target
12216 tc_gen_reloc (section
, fixp
)
12217 asection
*section ATTRIBUTE_UNUSED
;
12220 static arelent
*retval
[4];
12222 bfd_reloc_code_real_type code
;
12224 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
12227 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12228 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12229 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12231 if (mips_pic
== EMBEDDED_PIC
12232 && SWITCH_TABLE (fixp
))
12234 /* For a switch table entry we use a special reloc. The addend
12235 is actually the difference between the reloc address and the
12237 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12238 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
12239 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
12240 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
12242 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12243 reloc
->addend
= fixp
->fx_addnumber
;
12244 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
12246 /* We use a special addend for an internal RELLO reloc. */
12247 if (symbol_section_p (fixp
->fx_addsy
))
12248 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
12250 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
12252 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
12254 assert (fixp
->fx_next
!= NULL
12255 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
12256 /* We use a special addend for an internal RELHI reloc. The
12257 reloc is relative to the RELLO; adjust the addend
12259 if (symbol_section_p (fixp
->fx_addsy
))
12260 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
12261 + fixp
->fx_next
->fx_where
12262 - S_GET_VALUE (fixp
->fx_subsy
));
12264 reloc
->addend
= (fixp
->fx_addnumber
12265 + fixp
->fx_next
->fx_frag
->fr_address
12266 + fixp
->fx_next
->fx_where
);
12270 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
12271 /* A gruesome hack which is a result of the gruesome gas reloc
12273 reloc
->addend
= reloc
->address
;
12275 reloc
->addend
= -reloc
->address
;
12278 /* If this is a variant frag, we may need to adjust the existing
12279 reloc and generate a new one. */
12280 if (fixp
->fx_frag
->fr_opcode
!= NULL
12281 && (fixp
->fx_r_type
== BFD_RELOC_GPREL16
12282 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
12283 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
12284 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12285 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
12286 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12287 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
)
12292 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
12294 /* If this is not the last reloc in this frag, then we have two
12295 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
12296 CALL_HI16/CALL_LO16, both of which are being replaced. Let
12297 the second one handle all of them. */
12298 if (fixp
->fx_next
!= NULL
12299 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
12301 assert ((fixp
->fx_r_type
== BFD_RELOC_GPREL16
12302 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_GPREL16
)
12303 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
12304 && (fixp
->fx_next
->fx_r_type
12305 == BFD_RELOC_MIPS_GOT_LO16
))
12306 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
12307 && (fixp
->fx_next
->fx_r_type
12308 == BFD_RELOC_MIPS_CALL_LO16
)));
12313 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
12314 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12315 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
12317 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12318 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12319 reloc2
->address
= (reloc
->address
12320 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
12321 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
12322 reloc2
->addend
= fixp
->fx_addnumber
;
12323 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
12324 assert (reloc2
->howto
!= NULL
);
12326 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
12330 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
12333 reloc3
->address
+= 4;
12336 if (mips_pic
== NO_PIC
)
12338 assert (fixp
->fx_r_type
== BFD_RELOC_GPREL16
);
12339 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
12341 else if (mips_pic
== SVR4_PIC
)
12343 switch (fixp
->fx_r_type
)
12347 case BFD_RELOC_MIPS_GOT16
:
12349 case BFD_RELOC_MIPS_CALL16
:
12350 case BFD_RELOC_MIPS_GOT_LO16
:
12351 case BFD_RELOC_MIPS_CALL_LO16
:
12352 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
12360 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
12361 to be used in the relocation's section offset. */
12362 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12364 reloc
->address
= reloc
->addend
;
12368 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
12369 fixup_segment converted a non-PC relative reloc into a PC
12370 relative reloc. In such a case, we need to convert the reloc
12372 code
= fixp
->fx_r_type
;
12373 if (fixp
->fx_pcrel
)
12378 code
= BFD_RELOC_8_PCREL
;
12381 code
= BFD_RELOC_16_PCREL
;
12384 code
= BFD_RELOC_32_PCREL
;
12387 code
= BFD_RELOC_64_PCREL
;
12389 case BFD_RELOC_8_PCREL
:
12390 case BFD_RELOC_16_PCREL
:
12391 case BFD_RELOC_32_PCREL
:
12392 case BFD_RELOC_64_PCREL
:
12393 case BFD_RELOC_16_PCREL_S2
:
12394 case BFD_RELOC_PCREL_HI16_S
:
12395 case BFD_RELOC_PCREL_LO16
:
12398 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12399 _("Cannot make %s relocation PC relative"),
12400 bfd_get_reloc_code_name (code
));
12405 /* md_apply_fix3 has a double-subtraction hack to get
12406 bfd_install_relocation to behave nicely. GPREL relocations are
12407 handled correctly without this hack, so undo it here. We can't
12408 stop md_apply_fix3 from subtracting twice in the first place since
12409 the fake addend is required for variant frags above. */
12410 if (fixp
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
12411 && code
== BFD_RELOC_GPREL16
12412 && reloc
->addend
!= 0
12413 && mips_need_elf_addend_fixup (fixp
))
12414 reloc
->addend
+= S_GET_VALUE (fixp
->fx_addsy
);
12417 /* To support a PC relative reloc when generating embedded PIC code
12418 for ECOFF, we use a Cygnus extension. We check for that here to
12419 make sure that we don't let such a reloc escape normally. */
12420 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12421 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12422 && code
== BFD_RELOC_16_PCREL_S2
12423 && mips_pic
!= EMBEDDED_PIC
)
12424 reloc
->howto
= NULL
;
12426 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12428 if (reloc
->howto
== NULL
)
12430 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12431 _("Can not represent %s relocation in this object file format"),
12432 bfd_get_reloc_code_name (code
));
12439 /* Relax a machine dependent frag. This returns the amount by which
12440 the current size of the frag should change. */
12443 mips_relax_frag (fragp
, stretch
)
12447 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12450 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12452 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12454 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12459 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12461 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12468 /* Convert a machine dependent frag. */
12471 md_convert_frag (abfd
, asec
, fragp
)
12472 bfd
*abfd ATTRIBUTE_UNUSED
;
12479 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12482 register const struct mips16_immed_operand
*op
;
12483 boolean small
, ext
;
12486 unsigned long insn
;
12487 boolean use_extend
;
12488 unsigned short extend
;
12490 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12491 op
= mips16_immed_operands
;
12492 while (op
->type
!= type
)
12495 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12506 resolve_symbol_value (fragp
->fr_symbol
);
12507 val
= S_GET_VALUE (fragp
->fr_symbol
);
12512 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12514 /* The rules for the base address of a PC relative reloc are
12515 complicated; see mips16_extended_frag. */
12516 if (type
== 'p' || type
== 'q')
12521 /* Ignore the low bit in the target, since it will be
12522 set for a text label. */
12523 if ((val
& 1) != 0)
12526 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12528 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12531 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
12534 /* Make sure the section winds up with the alignment we have
12537 record_alignment (asec
, op
->shift
);
12541 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
12542 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
12543 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12544 _("extended instruction in delay slot"));
12546 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
12548 if (target_big_endian
)
12549 insn
= bfd_getb16 (buf
);
12551 insn
= bfd_getl16 (buf
);
12553 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
12554 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
12555 small
, ext
, &insn
, &use_extend
, &extend
);
12559 md_number_to_chars (buf
, 0xf000 | extend
, 2);
12560 fragp
->fr_fix
+= 2;
12564 md_number_to_chars (buf
, insn
, 2);
12565 fragp
->fr_fix
+= 2;
12570 if (fragp
->fr_opcode
== NULL
)
12573 old
= RELAX_OLD (fragp
->fr_subtype
);
12574 new = RELAX_NEW (fragp
->fr_subtype
);
12575 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
12578 memcpy (fixptr
- old
, fixptr
, new);
12580 fragp
->fr_fix
+= new - old
;
12586 /* This function is called after the relocs have been generated.
12587 We've been storing mips16 text labels as odd. Here we convert them
12588 back to even for the convenience of the debugger. */
12591 mips_frob_file_after_relocs ()
12594 unsigned int count
, i
;
12596 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12599 syms
= bfd_get_outsymbols (stdoutput
);
12600 count
= bfd_get_symcount (stdoutput
);
12601 for (i
= 0; i
< count
; i
++, syms
++)
12603 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
12604 && ((*syms
)->value
& 1) != 0)
12606 (*syms
)->value
&= ~1;
12607 /* If the symbol has an odd size, it was probably computed
12608 incorrectly, so adjust that as well. */
12609 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
12610 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12617 /* This function is called whenever a label is defined. It is used
12618 when handling branch delays; if a branch has a label, we assume we
12619 can not move it. */
12622 mips_define_label (sym
)
12625 struct insn_label_list
*l
;
12627 if (free_insn_labels
== NULL
)
12628 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12631 l
= free_insn_labels
;
12632 free_insn_labels
= l
->next
;
12636 l
->next
= insn_labels
;
12640 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12642 /* Some special processing for a MIPS ELF file. */
12645 mips_elf_final_processing ()
12647 /* Write out the register information. */
12652 s
.ri_gprmask
= mips_gprmask
;
12653 s
.ri_cprmask
[0] = mips_cprmask
[0];
12654 s
.ri_cprmask
[1] = mips_cprmask
[1];
12655 s
.ri_cprmask
[2] = mips_cprmask
[2];
12656 s
.ri_cprmask
[3] = mips_cprmask
[3];
12657 /* The gp_value field is set by the MIPS ELF backend. */
12659 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12660 ((Elf32_External_RegInfo
*)
12661 mips_regmask_frag
));
12665 Elf64_Internal_RegInfo s
;
12667 s
.ri_gprmask
= mips_gprmask
;
12669 s
.ri_cprmask
[0] = mips_cprmask
[0];
12670 s
.ri_cprmask
[1] = mips_cprmask
[1];
12671 s
.ri_cprmask
[2] = mips_cprmask
[2];
12672 s
.ri_cprmask
[3] = mips_cprmask
[3];
12673 /* The gp_value field is set by the MIPS ELF backend. */
12675 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12676 ((Elf64_External_RegInfo
*)
12677 mips_regmask_frag
));
12680 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12681 sort of BFD interface for this. */
12682 if (mips_any_noreorder
)
12683 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12684 if (mips_pic
!= NO_PIC
)
12685 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12687 /* Set the MIPS ELF ABI flags. */
12688 if (file_mips_abi
== NO_ABI
)
12690 else if (file_mips_abi
== O32_ABI
)
12691 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
12692 else if (file_mips_abi
== O64_ABI
)
12693 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
12694 else if (file_mips_abi
== EABI_ABI
)
12697 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
12699 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
12701 else if (file_mips_abi
== N32_ABI
)
12702 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
12704 /* Nothing to do for "64". */
12706 if (mips_32bitmode
)
12707 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
12710 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12712 typedef struct proc
{
12714 unsigned long reg_mask
;
12715 unsigned long reg_offset
;
12716 unsigned long fpreg_mask
;
12717 unsigned long fpreg_offset
;
12718 unsigned long frame_offset
;
12719 unsigned long frame_reg
;
12720 unsigned long pc_reg
;
12723 static procS cur_proc
;
12724 static procS
*cur_proc_ptr
;
12725 static int numprocs
;
12727 /* Fill in an rs_align_code fragment. */
12730 mips_handle_align (fragp
)
12733 if (fragp
->fr_type
!= rs_align_code
)
12736 if (mips_opts
.mips16
)
12738 static const unsigned char be_nop
[] = { 0x65, 0x00 };
12739 static const unsigned char le_nop
[] = { 0x00, 0x65 };
12744 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
12745 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
12750 fragp
->fr_fix
+= 1;
12753 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
12757 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
12768 /* check for premature end, nesting errors, etc */
12770 as_warn (_("missing .end at end of assembly"));
12779 if (*input_line_pointer
== '-')
12781 ++input_line_pointer
;
12784 if (!ISDIGIT (*input_line_pointer
))
12785 as_bad (_("expected simple number"));
12786 if (input_line_pointer
[0] == '0')
12788 if (input_line_pointer
[1] == 'x')
12790 input_line_pointer
+= 2;
12791 while (ISXDIGIT (*input_line_pointer
))
12794 val
|= hex_value (*input_line_pointer
++);
12796 return negative
? -val
: val
;
12800 ++input_line_pointer
;
12801 while (ISDIGIT (*input_line_pointer
))
12804 val
|= *input_line_pointer
++ - '0';
12806 return negative
? -val
: val
;
12809 if (!ISDIGIT (*input_line_pointer
))
12811 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12812 *input_line_pointer
, *input_line_pointer
);
12813 as_warn (_("invalid number"));
12816 while (ISDIGIT (*input_line_pointer
))
12819 val
+= *input_line_pointer
++ - '0';
12821 return negative
? -val
: val
;
12824 /* The .file directive; just like the usual .file directive, but there
12825 is an initial number which is the ECOFF file index. */
12829 int x ATTRIBUTE_UNUSED
;
12833 line
= get_number ();
12837 /* The .end directive. */
12841 int x ATTRIBUTE_UNUSED
;
12846 /* Following functions need their own .frame and .cprestore directives. */
12847 mips_frame_reg_valid
= 0;
12848 mips_cprestore_valid
= 0;
12850 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12853 demand_empty_rest_of_line ();
12858 #ifdef BFD_ASSEMBLER
12859 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12864 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12871 as_warn (_(".end not in text section"));
12875 as_warn (_(".end directive without a preceding .ent directive."));
12876 demand_empty_rest_of_line ();
12882 assert (S_GET_NAME (p
));
12883 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12884 as_warn (_(".end symbol does not match .ent symbol."));
12887 as_warn (_(".end directive missing or unknown symbol"));
12889 #ifdef MIPS_STABS_ELF
12891 segT saved_seg
= now_seg
;
12892 subsegT saved_subseg
= now_subseg
;
12897 dot
= frag_now_fix ();
12899 #ifdef md_flush_pending_output
12900 md_flush_pending_output ();
12904 subseg_set (pdr_seg
, 0);
12906 /* Write the symbol. */
12907 exp
.X_op
= O_symbol
;
12908 exp
.X_add_symbol
= p
;
12909 exp
.X_add_number
= 0;
12910 emit_expr (&exp
, 4);
12912 fragp
= frag_more (7 * 4);
12914 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12915 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12916 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12917 md_number_to_chars (fragp
+ 12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12918 md_number_to_chars (fragp
+ 16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12919 md_number_to_chars (fragp
+ 20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12920 md_number_to_chars (fragp
+ 24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12922 subseg_set (saved_seg
, saved_subseg
);
12926 cur_proc_ptr
= NULL
;
12929 /* The .aent and .ent directives. */
12939 symbolP
= get_symbol ();
12940 if (*input_line_pointer
== ',')
12941 input_line_pointer
++;
12942 SKIP_WHITESPACE ();
12943 if (ISDIGIT (*input_line_pointer
)
12944 || *input_line_pointer
== '-')
12945 number
= get_number ();
12947 #ifdef BFD_ASSEMBLER
12948 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12953 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12960 as_warn (_(".ent or .aent not in text section."));
12962 if (!aent
&& cur_proc_ptr
)
12963 as_warn (_("missing .end"));
12967 /* This function needs its own .frame and .cprestore directives. */
12968 mips_frame_reg_valid
= 0;
12969 mips_cprestore_valid
= 0;
12971 cur_proc_ptr
= &cur_proc
;
12972 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12974 cur_proc_ptr
->isym
= symbolP
;
12976 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
12981 demand_empty_rest_of_line ();
12984 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12985 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12986 s_mips_frame is used so that we can set the PDR information correctly.
12987 We can't use the ecoff routines because they make reference to the ecoff
12988 symbol table (in the mdebug section). */
12991 s_mips_frame (ignore
)
12992 int ignore ATTRIBUTE_UNUSED
;
12994 #ifdef MIPS_STABS_ELF
12998 if (cur_proc_ptr
== (procS
*) NULL
)
13000 as_warn (_(".frame outside of .ent"));
13001 demand_empty_rest_of_line ();
13005 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13007 SKIP_WHITESPACE ();
13008 if (*input_line_pointer
++ != ','
13009 || get_absolute_expression_and_terminator (&val
) != ',')
13011 as_warn (_("Bad .frame directive"));
13012 --input_line_pointer
;
13013 demand_empty_rest_of_line ();
13017 cur_proc_ptr
->frame_offset
= val
;
13018 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13020 demand_empty_rest_of_line ();
13023 #endif /* MIPS_STABS_ELF */
13026 /* The .fmask and .mask directives. If the mdebug section is present
13027 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13028 embedded targets, s_mips_mask is used so that we can set the PDR
13029 information correctly. We can't use the ecoff routines because they
13030 make reference to the ecoff symbol table (in the mdebug section). */
13033 s_mips_mask (reg_type
)
13036 #ifdef MIPS_STABS_ELF
13039 if (cur_proc_ptr
== (procS
*) NULL
)
13041 as_warn (_(".mask/.fmask outside of .ent"));
13042 demand_empty_rest_of_line ();
13046 if (get_absolute_expression_and_terminator (&mask
) != ',')
13048 as_warn (_("Bad .mask/.fmask directive"));
13049 --input_line_pointer
;
13050 demand_empty_rest_of_line ();
13054 off
= get_absolute_expression ();
13056 if (reg_type
== 'F')
13058 cur_proc_ptr
->fpreg_mask
= mask
;
13059 cur_proc_ptr
->fpreg_offset
= off
;
13063 cur_proc_ptr
->reg_mask
= mask
;
13064 cur_proc_ptr
->reg_offset
= off
;
13067 demand_empty_rest_of_line ();
13069 s_ignore (reg_type
);
13070 #endif /* MIPS_STABS_ELF */
13073 /* The .loc directive. */
13084 assert (now_seg
== text_section
);
13086 lineno
= get_number ();
13087 addroff
= frag_now_fix ();
13089 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13090 S_SET_TYPE (symbolP
, N_SLINE
);
13091 S_SET_OTHER (symbolP
, 0);
13092 S_SET_DESC (symbolP
, lineno
);
13093 symbolP
->sy_segment
= now_seg
;
13097 /* CPU name/ISA/number mapping table.
13099 Entries are grouped by type. The first matching CPU or ISA entry
13100 gets chosen by CPU or ISA, so it should be the 'canonical' name
13101 for that type. Entries after that within the type are sorted
13104 Case is ignored in comparison, so put the canonical entry in the
13105 appropriate case but everything else in lower case to ease eye pain. */
13106 static const struct mips_cpu_info mips_cpu_info_table
[] =
13109 { "MIPS1", 1, ISA_MIPS1
, CPU_R3000
, },
13110 { "mips", 1, ISA_MIPS1
, CPU_R3000
, },
13113 { "MIPS2", 1, ISA_MIPS2
, CPU_R6000
, },
13116 { "MIPS3", 1, ISA_MIPS3
, CPU_R4000
, },
13119 { "MIPS4", 1, ISA_MIPS4
, CPU_R8000
, },
13122 { "MIPS5", 1, ISA_MIPS5
, CPU_MIPS5
, },
13123 { "Generic-MIPS5", 0, ISA_MIPS5
, CPU_MIPS5
, },
13126 { "MIPS32", 1, ISA_MIPS32
, CPU_MIPS32
, },
13127 { "mipsisa32", 0, ISA_MIPS32
, CPU_MIPS32
, },
13128 { "Generic-MIPS32", 0, ISA_MIPS32
, CPU_MIPS32
, },
13129 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
, },
13130 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
, },
13131 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
, },
13133 /* For historical reasons. */
13134 { "MIPS64", 1, ISA_MIPS3
, CPU_R4000
, },
13137 { "mipsisa64", 1, ISA_MIPS64
, CPU_MIPS64
, },
13138 { "Generic-MIPS64", 0, ISA_MIPS64
, CPU_MIPS64
, },
13139 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
13140 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
, },
13143 { "R2000", 0, ISA_MIPS1
, CPU_R2000
, },
13144 { "2000", 0, ISA_MIPS1
, CPU_R2000
, },
13145 { "2k", 0, ISA_MIPS1
, CPU_R2000
, },
13146 { "r2k", 0, ISA_MIPS1
, CPU_R2000
, },
13149 { "R3000", 0, ISA_MIPS1
, CPU_R3000
, },
13150 { "3000", 0, ISA_MIPS1
, CPU_R3000
, },
13151 { "3k", 0, ISA_MIPS1
, CPU_R3000
, },
13152 { "r3k", 0, ISA_MIPS1
, CPU_R3000
, },
13155 { "R3900", 0, ISA_MIPS1
, CPU_R3900
, },
13156 { "3900", 0, ISA_MIPS1
, CPU_R3900
, },
13157 { "mipstx39", 0, ISA_MIPS1
, CPU_R3900
, },
13160 { "R4000", 0, ISA_MIPS3
, CPU_R4000
, },
13161 { "4000", 0, ISA_MIPS3
, CPU_R4000
, },
13162 { "4k", 0, ISA_MIPS3
, CPU_R4000
, }, /* beware */
13163 { "r4k", 0, ISA_MIPS3
, CPU_R4000
, },
13166 { "R4010", 0, ISA_MIPS2
, CPU_R4010
, },
13167 { "4010", 0, ISA_MIPS2
, CPU_R4010
, },
13170 { "R4400", 0, ISA_MIPS3
, CPU_R4400
, },
13171 { "4400", 0, ISA_MIPS3
, CPU_R4400
, },
13174 { "R4600", 0, ISA_MIPS3
, CPU_R4600
, },
13175 { "4600", 0, ISA_MIPS3
, CPU_R4600
, },
13176 { "mips64orion", 0, ISA_MIPS3
, CPU_R4600
, },
13177 { "orion", 0, ISA_MIPS3
, CPU_R4600
, },
13180 { "R4650", 0, ISA_MIPS3
, CPU_R4650
, },
13181 { "4650", 0, ISA_MIPS3
, CPU_R4650
, },
13184 { "R6000", 0, ISA_MIPS2
, CPU_R6000
, },
13185 { "6000", 0, ISA_MIPS2
, CPU_R6000
, },
13186 { "6k", 0, ISA_MIPS2
, CPU_R6000
, },
13187 { "r6k", 0, ISA_MIPS2
, CPU_R6000
, },
13190 { "R8000", 0, ISA_MIPS4
, CPU_R8000
, },
13191 { "8000", 0, ISA_MIPS4
, CPU_R8000
, },
13192 { "8k", 0, ISA_MIPS4
, CPU_R8000
, },
13193 { "r8k", 0, ISA_MIPS4
, CPU_R8000
, },
13196 { "R10000", 0, ISA_MIPS4
, CPU_R10000
, },
13197 { "10000", 0, ISA_MIPS4
, CPU_R10000
, },
13198 { "10k", 0, ISA_MIPS4
, CPU_R10000
, },
13199 { "r10k", 0, ISA_MIPS4
, CPU_R10000
, },
13202 { "R12000", 0, ISA_MIPS4
, CPU_R12000
, },
13203 { "12000", 0, ISA_MIPS4
, CPU_R12000
, },
13204 { "12k", 0, ISA_MIPS4
, CPU_R12000
, },
13205 { "r12k", 0, ISA_MIPS4
, CPU_R12000
, },
13208 { "VR4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13209 { "4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13210 { "mips64vr4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13211 { "r4100", 0, ISA_MIPS3
, CPU_VR4100
, },
13214 { "VR4111", 0, ISA_MIPS3
, CPU_R4111
, },
13215 { "4111", 0, ISA_MIPS3
, CPU_R4111
, },
13216 { "mips64vr4111", 0, ISA_MIPS3
, CPU_R4111
, },
13217 { "r4111", 0, ISA_MIPS3
, CPU_R4111
, },
13220 { "VR4300", 0, ISA_MIPS3
, CPU_R4300
, },
13221 { "4300", 0, ISA_MIPS3
, CPU_R4300
, },
13222 { "mips64vr4300", 0, ISA_MIPS3
, CPU_R4300
, },
13223 { "r4300", 0, ISA_MIPS3
, CPU_R4300
, },
13226 { "VR5000", 0, ISA_MIPS4
, CPU_R5000
, },
13227 { "5000", 0, ISA_MIPS4
, CPU_R5000
, },
13228 { "5k", 0, ISA_MIPS4
, CPU_R5000
, },
13229 { "mips64vr5000", 0, ISA_MIPS4
, CPU_R5000
, },
13230 { "r5000", 0, ISA_MIPS4
, CPU_R5000
, },
13231 { "r5200", 0, ISA_MIPS4
, CPU_R5000
, },
13232 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
, },
13233 { "r5230", 0, ISA_MIPS4
, CPU_R5000
, },
13234 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
, },
13235 { "r5231", 0, ISA_MIPS4
, CPU_R5000
, },
13236 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
, },
13237 { "r5261", 0, ISA_MIPS4
, CPU_R5000
, },
13238 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
, },
13239 { "r5721", 0, ISA_MIPS4
, CPU_R5000
, },
13240 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
, },
13241 { "r5k", 0, ISA_MIPS4
, CPU_R5000
, },
13242 { "r7000", 0, ISA_MIPS4
, CPU_R5000
, },
13244 /* Broadcom SB-1 CPU */
13245 { "SB-1", 0, ISA_MIPS64
, CPU_SB1
, },
13246 { "sb-1250", 0, ISA_MIPS64
, CPU_SB1
, },
13247 { "sb1", 0, ISA_MIPS64
, CPU_SB1
, },
13248 { "sb1250", 0, ISA_MIPS64
, CPU_SB1
, },
13251 { NULL
, 0, 0, 0, },
13254 static const struct mips_cpu_info
*
13255 mips_cpu_info_from_name (name
)
13260 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13261 if (strcasecmp (name
, mips_cpu_info_table
[i
].name
) == 0)
13262 return (&mips_cpu_info_table
[i
]);
13267 static const struct mips_cpu_info
*
13268 mips_cpu_info_from_isa (isa
)
13273 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13274 if (mips_cpu_info_table
[i
].is_isa
13275 && isa
== mips_cpu_info_table
[i
].isa
)
13276 return (&mips_cpu_info_table
[i
]);
13281 static const struct mips_cpu_info
*
13282 mips_cpu_info_from_cpu (cpu
)
13287 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
13288 if (!mips_cpu_info_table
[i
].is_isa
13289 && cpu
== mips_cpu_info_table
[i
].cpu
)
13290 return (&mips_cpu_info_table
[i
]);