1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
78 #define PIC_CALL_REG 25
86 extern int target_big_endian
;
88 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
89 32 bit ABI. This has no meaning for ECOFF. */
92 /* The default target format to use. */
96 switch (OUTPUT_FLAVOR
)
98 case bfd_target_aout_flavour
:
99 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
100 case bfd_target_ecoff_flavour
:
101 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
102 case bfd_target_elf_flavour
:
103 return (target_big_endian
104 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
105 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
111 /* The name of the readonly data section. */
112 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
114 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
120 /* These variables are filled in with the masks of registers used.
121 The object format code reads them and puts them in the appropriate
123 unsigned long mips_gprmask
;
124 unsigned long mips_cprmask
[4];
126 /* MIPS ISA (Instruction Set Architecture) level (may be changed
127 temporarily using .set mipsN). */
128 static int mips_isa
= -1;
130 /* MIPS ISA we are using for this output file. */
131 static int file_mips_isa
;
133 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
134 static int mips_cpu
= -1;
136 /* Whether the 4650 instructions (mad/madu) are permitted. */
137 static int mips_4650
= -1;
139 /* Whether the 4010 instructions are permitted. */
140 static int mips_4010
= -1;
142 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
143 static int mips_4100
= -1;
145 /* Whether the processor uses hardware interlocks, and thus does not
146 require nops to be inserted. */
147 static int interlocks
= -1;
149 /* As with "interlocks" this is used by hardware that has FP
150 (co-processor) interlocks. */
151 static int cop_interlocks
= -1;
153 /* MIPS PIC level. */
157 /* Do not generate PIC code. */
160 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
161 not sure what it is supposed to do. */
164 /* Generate PIC code as in the SVR4 MIPS ABI. */
167 /* Generate PIC code without using a global offset table: the data
168 segment has a maximum size of 64K, all data references are off
169 the $gp register, and all text references are PC relative. This
170 is used on some embedded systems. */
174 static enum mips_pic_level mips_pic
;
176 /* 1 if we should generate 32 bit offsets from the GP register in
177 SVR4_PIC mode. Currently has no meaning in other modes. */
178 static int mips_big_got
;
180 /* 1 if trap instructions should used for overflow rather than break
182 static int mips_trap
;
184 static int mips_warn_about_macros
;
185 static int mips_noreorder
;
186 static int mips_any_noreorder
;
187 static int mips_nomove
;
188 static int mips_noat
;
189 static int mips_nobopt
;
191 /* The size of the small data section. */
192 static int g_switch_value
= 8;
193 /* Whether the -G option was used. */
194 static int g_switch_seen
= 0;
199 /* If we can determine in advance that GP optimization won't be
200 possible, we can skip the relaxation stuff that tries to produce
201 GP-relative references. This makes delay slot optimization work
204 This function can only provide a guess, but it seems to work for
205 gcc output. If it guesses wrong, the only loss should be in
206 efficiency; it shouldn't introduce any bugs.
208 I don't know if a fix is needed for the SVR4_PIC mode. I've only
209 fixed it for the non-PIC mode. KR 95/04/07 */
210 static int nopic_need_relax
PARAMS ((symbolS
*));
212 /* handle of the OPCODE hash table */
213 static struct hash_control
*op_hash
= NULL
;
215 /* This array holds the chars that always start a comment. If the
216 pre-processor is disabled, these aren't very useful */
217 const char comment_chars
[] = "#";
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output */
222 /* Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output. */
225 /* Also note that C style comments are always supported. */
226 const char line_comment_chars
[] = "#";
228 /* This array holds machine specific line separator characters. */
229 const char line_separator_chars
[] = "";
231 /* Chars that can be used to separate mant from exp in floating point nums */
232 const char EXP_CHARS
[] = "eE";
234 /* Chars that mean this number is a floating point constant */
237 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
239 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
240 changed in read.c . Ideally it shouldn't have to know about it at all,
241 but nothing is ideal around here.
244 static char *insn_error
;
246 static int byte_order
;
248 static int auto_align
= 1;
250 /* Symbol labelling the current insn. */
251 static symbolS
*insn_label
;
253 /* When outputting SVR4 PIC code, the assembler needs to know the
254 offset in the stack frame from which to restore the $gp register.
255 This is set by the .cprestore pseudo-op, and saved in this
257 static offsetT mips_cprestore_offset
= -1;
259 /* This is the register which holds the stack frame, as set by the
260 .frame pseudo-op. This is needed to implement .cprestore. */
261 static int mips_frame_reg
= SP
;
263 /* To output NOP instructions correctly, we need to keep information
264 about the previous two instructions. */
266 /* Whether we are optimizing. The default value of 2 means to remove
267 unneeded NOPs and swap branch instructions when possible. A value
268 of 1 means to not swap branches. A value of 0 means to always
270 static int mips_optimize
= 2;
272 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
273 equivalent to seeing no -g option at all. */
274 static int mips_debug
= 0;
276 /* The previous instruction. */
277 static struct mips_cl_insn prev_insn
;
279 /* The instruction before prev_insn. */
280 static struct mips_cl_insn prev_prev_insn
;
282 /* If we don't want information for prev_insn or prev_prev_insn, we
283 point the insn_mo field at this dummy integer. */
284 static const struct mips_opcode dummy_opcode
= { 0 };
286 /* Non-zero if prev_insn is valid. */
287 static int prev_insn_valid
;
289 /* The frag for the previous instruction. */
290 static struct frag
*prev_insn_frag
;
292 /* The offset into prev_insn_frag for the previous instruction. */
293 static long prev_insn_where
;
295 /* The reloc for the previous instruction, if any. */
296 static fixS
*prev_insn_fixp
;
298 /* Non-zero if the previous instruction was in a delay slot. */
299 static int prev_insn_is_delay_slot
;
301 /* Non-zero if the previous instruction was in a .set noreorder. */
302 static int prev_insn_unreordered
;
304 /* Non-zero if the previous previous instruction was in a .set
306 static int prev_prev_insn_unreordered
;
308 /* For ECOFF and ELF, relocations against symbols are done in two
309 parts, with a HI relocation and a LO relocation. Each relocation
310 has only 16 bits of space to store an addend. This means that in
311 order for the linker to handle carries correctly, it must be able
312 to locate both the HI and the LO relocation. This means that the
313 relocations must appear in order in the relocation table.
315 In order to implement this, we keep track of each unmatched HI
316 relocation. We then sort them so that they immediately precede the
317 corresponding LO relocation. */
322 struct mips_hi_fixup
*next
;
325 /* The section this fixup is in. */
329 /* The list of unmatched HI relocs. */
331 static struct mips_hi_fixup
*mips_hi_fixup_list
;
333 /* Since the MIPS does not have multiple forms of PC relative
334 instructions, we do not have to do relaxing as is done on other
335 platforms. However, we do have to handle GP relative addressing
336 correctly, which turns out to be a similar problem.
338 Every macro that refers to a symbol can occur in (at least) two
339 forms, one with GP relative addressing and one without. For
340 example, loading a global variable into a register generally uses
341 a macro instruction like this:
343 If i can be addressed off the GP register (this is true if it is in
344 the .sbss or .sdata section, or if it is known to be smaller than
345 the -G argument) this will generate the following instruction:
347 This instruction will use a GPREL reloc. If i can not be addressed
348 off the GP register, the following instruction sequence will be used:
351 In this case the first instruction will have a HI16 reloc, and the
352 second reloc will have a LO16 reloc. Both relocs will be against
355 The issue here is that we may not know whether i is GP addressable
356 until after we see the instruction that uses it. Therefore, we
357 want to be able to choose the final instruction sequence only at
358 the end of the assembly. This is similar to the way other
359 platforms choose the size of a PC relative instruction only at the
362 When generating position independent code we do not use GP
363 addressing in quite the same way, but the issue still arises as
364 external symbols and local symbols must be handled differently.
366 We handle these issues by actually generating both possible
367 instruction sequences. The longer one is put in a frag_var with
368 type rs_machine_dependent. We encode what to do with the frag in
369 the subtype field. We encode (1) the number of existing bytes to
370 replace, (2) the number of new bytes to use, (3) the offset from
371 the start of the existing bytes to the first reloc we must generate
372 (that is, the offset is applied from the start of the existing
373 bytes after they are replaced by the new bytes, if any), (4) the
374 offset from the start of the existing bytes to the second reloc,
375 (5) whether a third reloc is needed (the third reloc is always four
376 bytes after the second reloc), and (6) whether to warn if this
377 variant is used (this is sometimes needed if .set nomacro or .set
378 noat is in effect). All these numbers are reasonably small.
380 Generating two instruction sequences must be handled carefully to
381 ensure that delay slots are handled correctly. Fortunately, there
382 are a limited number of cases. When the second instruction
383 sequence is generated, append_insn is directed to maintain the
384 existing delay slot information, so it continues to apply to any
385 code after the second instruction sequence. This means that the
386 second instruction sequence must not impose any requirements not
387 required by the first instruction sequence.
389 These variant frags are then handled in functions called by the
390 machine independent code. md_estimate_size_before_relax returns
391 the final size of the frag. md_convert_frag sets up the final form
392 of the frag. tc_gen_reloc adjust the first reloc and adds a second
394 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
398 | (((reloc1) + 64) << 9) \
399 | (((reloc2) + 64) << 2) \
400 | ((reloc3) ? (1 << 1) : 0) \
402 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
403 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
404 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
405 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
406 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
407 #define RELAX_WARN(i) ((i) & 1)
409 /* Prototypes for static functions. */
412 #define internalError() \
413 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
415 #define internalError() as_fatal ("MIPS internal Error");
418 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
419 unsigned int reg
, int fpr
));
420 static int reg_needs_delay
PARAMS ((int));
421 static void append_insn
PARAMS ((char *place
,
422 struct mips_cl_insn
* ip
,
424 bfd_reloc_code_real_type r
,
426 static void mips_no_prev_insn
PARAMS ((void));
427 static void mips_emit_delays
PARAMS ((void));
429 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
430 const char *name
, const char *fmt
,
433 static void macro_build ();
435 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
436 expressionS
* ep
, int regnum
));
437 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
438 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
440 static void load_register
PARAMS ((int *, int, expressionS
*, int));
441 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
442 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
443 #ifdef LOSING_COMPILER
444 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
446 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
447 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
448 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
449 static symbolS
*get_symbol
PARAMS ((void));
450 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
451 static void s_align
PARAMS ((int));
452 static void s_change_sec
PARAMS ((int));
453 static void s_cons
PARAMS ((int));
454 static void s_float_cons
PARAMS ((int));
455 static void s_mips_globl
PARAMS ((int));
456 static void s_option
PARAMS ((int));
457 static void s_mipsset
PARAMS ((int));
458 static void s_abicalls
PARAMS ((int));
459 static void s_cpload
PARAMS ((int));
460 static void s_cprestore
PARAMS ((int));
461 static void s_gpword
PARAMS ((int));
462 static void s_cpadd
PARAMS ((int));
463 static void md_obj_begin
PARAMS ((void));
464 static void md_obj_end
PARAMS ((void));
465 static long get_number
PARAMS ((void));
466 static void s_ent
PARAMS ((int));
467 static void s_mipsend
PARAMS ((int));
468 static void s_file
PARAMS ((int));
472 The following pseudo-ops from the Kane and Heinrich MIPS book
473 should be defined here, but are currently unsupported: .alias,
474 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
476 The following pseudo-ops from the Kane and Heinrich MIPS book are
477 specific to the type of debugging information being generated, and
478 should be defined by the object format: .aent, .begin, .bend,
479 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
482 The following pseudo-ops from the Kane and Heinrich MIPS book are
483 not MIPS CPU specific, but are also not specific to the object file
484 format. This file is probably the best place to define them, but
485 they are not currently supported: .asm0, .endr, .lab, .repeat,
486 .struct, .weakext. */
488 static const pseudo_typeS mips_pseudo_table
[] =
490 /* MIPS specific pseudo-ops. */
491 {"option", s_option
, 0},
492 {"set", s_mipsset
, 0},
493 {"rdata", s_change_sec
, 'r'},
494 {"sdata", s_change_sec
, 's'},
495 {"livereg", s_ignore
, 0},
496 {"abicalls", s_abicalls
, 0},
497 {"cpload", s_cpload
, 0},
498 {"cprestore", s_cprestore
, 0},
499 {"gpword", s_gpword
, 0},
500 {"cpadd", s_cpadd
, 0},
502 /* Relatively generic pseudo-ops that happen to be used on MIPS
504 {"asciiz", stringer
, 1},
505 {"bss", s_change_sec
, 'b'},
508 {"dword", s_cons
, 3},
510 /* These pseudo-ops are defined in read.c, but must be overridden
511 here for one reason or another. */
512 {"align", s_align
, 0},
514 {"data", s_change_sec
, 'd'},
515 {"double", s_float_cons
, 'd'},
516 {"float", s_float_cons
, 'f'},
517 {"globl", s_mips_globl
, 0},
518 {"global", s_mips_globl
, 0},
519 {"hword", s_cons
, 1},
524 {"short", s_cons
, 1},
525 {"single", s_float_cons
, 'f'},
526 {"text", s_change_sec
, 't'},
531 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
532 /* These pseudo-ops should be defined by the object file format.
533 However, a.out doesn't support them, so we have versions here. */
535 {"bgnb", s_ignore
, 0},
536 {"end", s_mipsend
, 0},
537 {"endb", s_ignore
, 0},
540 {"fmask", s_ignore
, 'F'},
541 {"frame", s_ignore
, 0},
542 {"loc", s_ignore
, 0},
543 {"mask", s_ignore
, 'R'},
544 {"verstamp", s_ignore
, 0},
548 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
553 pop_insert (mips_pseudo_table
);
554 if (! ECOFF_DEBUGGING
)
555 pop_insert (mips_nonecoff_pseudo_table
);
558 static char *expr_end
;
560 /* Expressions which appear in instructions. These are set by
563 static expressionS imm_expr
;
564 static expressionS offset_expr
;
566 /* Relocs associated with imm_expr and offset_expr. */
568 static bfd_reloc_code_real_type imm_reloc
;
569 static bfd_reloc_code_real_type offset_reloc
;
571 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
573 static boolean imm_unmatched_hi
;
576 * This function is called once, at assembler startup time. It should
577 * set up all the tables, etc. that the MD part of the assembler will need.
583 register const char *retval
= NULL
;
584 register unsigned int i
= 0;
592 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
594 a
= xmalloc (sizeof TARGET_CPU
);
595 strcpy (a
, TARGET_CPU
);
596 a
[(sizeof TARGET_CPU
) - 3] = '\0';
600 if (strcmp (cpu
, "mips") == 0)
606 else if (strcmp (cpu
, "r6000") == 0
607 || strcmp (cpu
, "mips2") == 0)
613 else if (strcmp (cpu
, "mips64") == 0
614 || strcmp (cpu
, "r4000") == 0
615 || strcmp (cpu
, "mips3") == 0)
621 else if (strcmp (cpu
, "r4400") == 0)
627 else if (strcmp (cpu
, "mips64orion") == 0
628 || strcmp (cpu
, "r4600") == 0)
634 else if (strcmp (cpu
, "r4650") == 0)
642 else if (strcmp (cpu
, "mips64vr4300") == 0)
648 else if (strcmp (cpu
, "mips64vr4100") == 0)
656 else if (strcmp (cpu
, "r4010") == 0)
664 else if (strcmp (cpu
, "r5000") == 0
665 || strcmp (cpu
, "mips64vr5000") == 0)
671 else if (strcmp (cpu
, "r8000") == 0
672 || strcmp (cpu
, "mips4") == 0)
678 else if (strcmp (cpu
, "r10000") == 0)
713 if (mips_cpu
== 4300 || mips_cpu
== 5000)
718 if (mips_isa
< 2 && mips_trap
)
719 as_bad ("trap exception not supported at ISA 1");
724 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
727 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
730 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
733 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
737 as_warn ("Could not set architecture and machine");
739 file_mips_isa
= mips_isa
;
741 op_hash
= hash_new ();
743 for (i
= 0; i
< NUMOPCODES
;)
745 const char *name
= mips_opcodes
[i
].name
;
747 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
750 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
751 mips_opcodes
[i
].name
, retval
);
752 as_fatal ("Broken assembler. No assembly attempted.");
756 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
757 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
758 != mips_opcodes
[i
].match
))
760 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
761 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
762 as_fatal ("Broken assembler. No assembly attempted.");
766 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
769 mips_no_prev_insn ();
777 /* set the default alignment for the text section (2**2) */
778 record_alignment (text_section
, 2);
780 if (USE_GLOBAL_POINTER_OPT
)
781 bfd_set_gp_size (stdoutput
, g_switch_value
);
783 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
785 /* Sections must be aligned to 16 byte boundaries. */
786 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
787 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
788 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
790 /* Create a .reginfo section for register masks and a .mdebug
791 section for debugging information. */
802 sec
= subseg_new (".reginfo", (subsegT
) 0);
804 /* The ABI says this section should be loaded so that the
805 running program can access it. */
806 (void) bfd_set_section_flags (stdoutput
, sec
,
807 (SEC_ALLOC
| SEC_LOAD
808 | SEC_READONLY
| SEC_DATA
));
809 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
812 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
817 /* The 64-bit ABI uses a .MIPS.options section rather than
819 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
820 (void) bfd_set_section_flags (stdoutput
, sec
,
821 (SEC_ALLOC
| SEC_LOAD
822 | SEC_READONLY
| SEC_DATA
));
823 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
826 /* Set up the option header. */
828 Elf_Internal_Options opthdr
;
831 opthdr
.kind
= ODK_REGINFO
;
832 opthdr
.size
= (sizeof (Elf_External_Options
)
833 + sizeof (Elf64_External_RegInfo
));
836 f
= frag_more (sizeof (Elf_External_Options
));
837 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
838 (Elf_External_Options
*) f
);
840 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
847 sec
= subseg_new (".mdebug", (subsegT
) 0);
848 (void) bfd_set_section_flags (stdoutput
, sec
,
849 SEC_HAS_CONTENTS
| SEC_READONLY
);
850 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
853 subseg_set (seg
, subseg
);
857 if (! ECOFF_DEBUGGING
)
864 if (! ECOFF_DEBUGGING
)
872 struct mips_cl_insn insn
;
874 imm_expr
.X_op
= O_absent
;
875 imm_reloc
= BFD_RELOC_UNUSED
;
876 imm_unmatched_hi
= false;
877 offset_expr
.X_op
= O_absent
;
878 offset_reloc
= BFD_RELOC_UNUSED
;
880 mips_ip (str
, &insn
);
883 as_bad ("%s `%s'", insn_error
, str
);
886 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
892 if (imm_expr
.X_op
!= O_absent
)
893 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
895 else if (offset_expr
.X_op
!= O_absent
)
896 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
898 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
902 /* See whether instruction IP reads register REG. If FPR is non-zero,
903 REG is a floating point register. */
906 insn_uses_reg (ip
, reg
, fpr
)
907 struct mips_cl_insn
*ip
;
911 /* Don't report on general register 0, since it never changes. */
912 if (! fpr
&& reg
== 0)
917 /* If we are called with either $f0 or $f1, we must check $f0.
918 This is not optimal, because it will introduce an unnecessary
919 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
920 need to distinguish reading both $f0 and $f1 or just one of
921 them. Note that we don't have to check the other way,
922 because there is no instruction that sets both $f0 and $f1
923 and requires a delay. */
924 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
925 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
926 == (reg
&~ (unsigned) 1)))
928 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
929 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
930 == (reg
&~ (unsigned) 1)))
935 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
936 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
938 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
939 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
946 /* This function returns true if modifying a register requires a
950 reg_needs_delay (reg
)
953 unsigned long prev_pinfo
;
955 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
958 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
960 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
962 /* A load from a coprocessor or from memory. All load
963 delays delay the use of general register rt for one
964 instruction on the r3000. The r6000 and r4000 use
966 know (prev_pinfo
& INSN_WRITE_GPR_T
);
967 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
974 /* Output an instruction. PLACE is where to put the instruction; if
975 it is NULL, this uses frag_more to get room. IP is the instruction
976 information. ADDRESS_EXPR is an operand of the instruction to be
977 used with RELOC_TYPE. */
980 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
982 struct mips_cl_insn
*ip
;
983 expressionS
*address_expr
;
984 bfd_reloc_code_real_type reloc_type
;
985 boolean unmatched_hi
;
987 register unsigned long prev_pinfo
, pinfo
;
992 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
993 pinfo
= ip
->insn_mo
->pinfo
;
995 if (place
== NULL
&& ! mips_noreorder
)
997 /* If the previous insn required any delay slots, see if we need
998 to insert a NOP or two. There are eight kinds of possible
999 hazards, of which an instruction can have at most one type.
1000 (1) a load from memory delay
1001 (2) a load from a coprocessor delay
1002 (3) an unconditional branch delay
1003 (4) a conditional branch delay
1004 (5) a move to coprocessor register delay
1005 (6) a load coprocessor register from memory delay
1006 (7) a coprocessor condition code delay
1007 (8) a HI/LO special register delay
1009 There are a lot of optimizations we could do that we don't.
1010 In particular, we do not, in general, reorder instructions.
1011 If you use gcc with optimization, it will reorder
1012 instructions and generally do much more optimization then we
1013 do here; repeating all that work in the assembler would only
1014 benefit hand written assembly code, and does not seem worth
1017 /* This is how a NOP is emitted. */
1018 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1020 /* The previous insn might require a delay slot, depending upon
1021 the contents of the current insn. */
1023 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1024 && ! cop_interlocks
)
1026 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1028 /* A load from a coprocessor or from memory. All load
1029 delays delay the use of general register rt for one
1030 instruction on the r3000. The r6000 and r4000 use
1032 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1033 if (mips_optimize
== 0
1034 || insn_uses_reg (ip
,
1035 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1040 else if (mips_isa
< 4
1041 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1042 && ! cop_interlocks
)
1044 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1046 /* A generic coprocessor delay. The previous instruction
1047 modified a coprocessor general or control register. If
1048 it modified a control register, we need to avoid any
1049 coprocessor instruction (this is probably not always
1050 required, but it sometimes is). If it modified a general
1051 register, we avoid using that register.
1053 On the r6000 and r4000 loading a coprocessor register
1054 from memory is interlocked, and does not require a delay.
1056 This case is not handled very well. There is no special
1057 knowledge of CP0 handling, and the coprocessors other
1058 than the floating point unit are not distinguished at
1060 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1062 if (mips_optimize
== 0
1063 || insn_uses_reg (ip
,
1064 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1069 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1071 if (mips_optimize
== 0
1072 || insn_uses_reg (ip
,
1073 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1080 /* We don't know exactly what the previous instruction
1081 does. If the current instruction uses a coprocessor
1082 register, we must insert a NOP. If previous
1083 instruction may set the condition codes, and the
1084 current instruction uses them, we must insert two
1086 if (mips_optimize
== 0
1087 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1088 && (pinfo
& INSN_READ_COND_CODE
)))
1090 else if (pinfo
& INSN_COP
)
1094 else if (mips_isa
< 4
1095 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1096 && ! cop_interlocks
)
1098 /* The previous instruction sets the coprocessor condition
1099 codes, but does not require a general coprocessor delay
1100 (this means it is a floating point comparison
1101 instruction). If this instruction uses the condition
1102 codes, we need to insert a single NOP. */
1103 if (mips_optimize
== 0
1104 || (pinfo
& INSN_READ_COND_CODE
))
1107 else if (prev_pinfo
& INSN_READ_LO
)
1109 /* The previous instruction reads the LO register; if the
1110 current instruction writes to the LO register, we must
1111 insert two NOPS. Some newer processors have interlocks. */
1113 && (mips_optimize
== 0
1114 || (pinfo
& INSN_WRITE_LO
)))
1117 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1119 /* The previous instruction reads the HI register; if the
1120 current instruction writes to the HI register, we must
1121 insert a NOP. Some newer processors have interlocks. */
1123 && (mips_optimize
== 0
1124 || (pinfo
& INSN_WRITE_HI
)))
1128 /* There are two cases which require two intervening
1129 instructions: 1) setting the condition codes using a move to
1130 coprocessor instruction which requires a general coprocessor
1131 delay and then reading the condition codes 2) reading the HI
1132 or LO register and then writing to it (except on processors
1133 which have interlocks). If we are not already emitting a NOP
1134 instruction, we must check for these cases compared to the
1135 instruction previous to the previous instruction. */
1138 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1139 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1140 && (pinfo
& INSN_READ_COND_CODE
)
1141 && ! cop_interlocks
)
1142 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1143 && (pinfo
& INSN_WRITE_LO
)
1145 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1146 && (pinfo
& INSN_WRITE_HI
)
1150 /* If we are being given a nop instruction, don't bother with
1151 one of the nops we would otherwise output. This will only
1152 happen when a nop instruction is used with mips_optimize set
1154 if (nops
> 0 && ip
->insn_opcode
== 0)
1157 /* Now emit the right number of NOP instructions. */
1161 unsigned long old_frag_offset
;
1164 old_frag
= frag_now
;
1165 old_frag_offset
= frag_now_fix ();
1167 for (i
= 0; i
< nops
; i
++)
1172 listing_prev_line ();
1173 /* We may be at the start of a variant frag. In case we
1174 are, make sure there is enough space for the frag
1175 after the frags created by listing_prev_line. The
1176 argument to frag_grow here must be at least as large
1177 as the argument to all other calls to frag_grow in
1178 this file. We don't have to worry about being in the
1179 middle of a variant frag, because the variants insert
1180 all needed nop instructions themselves. */
1184 if (insn_label
!= NULL
)
1186 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1187 insn_label
->sy_frag
= frag_now
;
1188 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1191 #ifndef NO_ECOFF_DEBUGGING
1192 if (ECOFF_DEBUGGING
)
1193 ecoff_fix_loc (old_frag
, old_frag_offset
);
1203 if (address_expr
!= NULL
)
1205 if (address_expr
->X_op
== O_constant
)
1210 ip
->insn_opcode
|= address_expr
->X_add_number
;
1213 case BFD_RELOC_LO16
:
1214 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1217 case BFD_RELOC_MIPS_JMP
:
1218 case BFD_RELOC_16_PCREL_S2
:
1227 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1229 /* Don't generate a reloc if we are writing into a variant
1233 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1235 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1239 struct mips_hi_fixup
*hi_fixup
;
1241 assert (reloc_type
== BFD_RELOC_HI16_S
);
1242 hi_fixup
= ((struct mips_hi_fixup
*)
1243 xmalloc (sizeof (struct mips_hi_fixup
)));
1244 hi_fixup
->fixp
= fixp
;
1245 hi_fixup
->seg
= now_seg
;
1246 hi_fixup
->next
= mips_hi_fixup_list
;
1247 mips_hi_fixup_list
= hi_fixup
;
1253 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1255 /* Update the register mask information. */
1256 if (pinfo
& INSN_WRITE_GPR_D
)
1257 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1258 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1259 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1260 if (pinfo
& INSN_READ_GPR_S
)
1261 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1262 if (pinfo
& INSN_WRITE_GPR_31
)
1263 mips_gprmask
|= 1 << 31;
1264 if (pinfo
& INSN_WRITE_FPR_D
)
1265 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1266 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1267 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1268 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1269 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1270 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1271 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1272 if (pinfo
& INSN_COP
)
1274 /* We don't keep enough information to sort these cases out. */
1276 /* Never set the bit for $0, which is always zero. */
1277 mips_gprmask
&=~ 1 << 0;
1279 if (place
== NULL
&& ! mips_noreorder
)
1281 /* Filling the branch delay slot is more complex. We try to
1282 switch the branch with the previous instruction, which we can
1283 do if the previous instruction does not set up a condition
1284 that the branch tests and if the branch is not itself the
1285 target of any branch. */
1286 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1287 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1289 if (mips_optimize
< 2
1290 /* If we have seen .set volatile or .set nomove, don't
1293 /* If we had to emit any NOP instructions, then we
1294 already know we can not swap. */
1296 /* If we don't even know the previous insn, we can not
1298 || ! prev_insn_valid
1299 /* If the previous insn is already in a branch delay
1300 slot, then we can not swap. */
1301 || prev_insn_is_delay_slot
1302 /* If the previous previous insn was in a .set
1303 noreorder, we can't swap. Actually, the MIPS
1304 assembler will swap in this situation. However, gcc
1305 configured -with-gnu-as will generate code like
1311 in which we can not swap the bne and INSN. If gcc is
1312 not configured -with-gnu-as, it does not output the
1313 .set pseudo-ops. We don't have to check
1314 prev_insn_unreordered, because prev_insn_valid will
1315 be 0 in that case. We don't want to use
1316 prev_prev_insn_valid, because we do want to be able
1317 to swap at the start of a function. */
1318 || prev_prev_insn_unreordered
1319 /* If the branch is itself the target of a branch, we
1320 can not swap. We cheat on this; all we check for is
1321 whether there is a label on this instruction. If
1322 there are any branches to anything other than a
1323 label, users must use .set noreorder. */
1324 || insn_label
!= NULL
1325 /* If the previous instruction is in a variant frag, we
1326 can not do the swap. */
1327 || prev_insn_frag
->fr_type
== rs_machine_dependent
1328 /* If the branch reads the condition codes, we don't
1329 even try to swap, because in the sequence
1334 we can not swap, and I don't feel like handling that
1337 && (pinfo
& INSN_READ_COND_CODE
))
1338 /* We can not swap with an instruction that requires a
1339 delay slot, becase the target of the branch might
1340 interfere with that instruction. */
1343 & (INSN_LOAD_COPROC_DELAY
1344 | INSN_COPROC_MOVE_DELAY
1345 | INSN_WRITE_COND_CODE
)))
1352 & (INSN_LOAD_MEMORY_DELAY
1353 | INSN_COPROC_MEMORY_DELAY
)))
1354 /* We can not swap with a branch instruction. */
1356 & (INSN_UNCOND_BRANCH_DELAY
1357 | INSN_COND_BRANCH_DELAY
1358 | INSN_COND_BRANCH_LIKELY
))
1359 /* We do not swap with a trap instruction, since it
1360 complicates trap handlers to have the trap
1361 instruction be in a delay slot. */
1362 || (prev_pinfo
& INSN_TRAP
)
1363 /* If the branch reads a register that the previous
1364 instruction sets, we can not swap. */
1365 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1366 && insn_uses_reg (ip
,
1367 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1370 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1371 && insn_uses_reg (ip
,
1372 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1375 /* If the branch writes a register that the previous
1376 instruction sets, we can not swap (we know that
1377 branches write only to RD or to $31). */
1378 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1379 && (((pinfo
& INSN_WRITE_GPR_D
)
1380 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1381 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1382 || ((pinfo
& INSN_WRITE_GPR_31
)
1383 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1386 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1387 && (((pinfo
& INSN_WRITE_GPR_D
)
1388 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1389 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1390 || ((pinfo
& INSN_WRITE_GPR_31
)
1391 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1394 /* If the branch writes a register that the previous
1395 instruction reads, we can not swap (we know that
1396 branches only write to RD or to $31). */
1397 || ((pinfo
& INSN_WRITE_GPR_D
)
1398 && insn_uses_reg (&prev_insn
,
1399 ((ip
->insn_opcode
>> OP_SH_RD
)
1402 || ((pinfo
& INSN_WRITE_GPR_31
)
1403 && insn_uses_reg (&prev_insn
, 31, 0))
1404 /* If we are generating embedded PIC code, the branch
1405 might be expanded into a sequence which uses $at, so
1406 we can't swap with an instruction which reads it. */
1407 || (mips_pic
== EMBEDDED_PIC
1408 && insn_uses_reg (&prev_insn
, AT
, 0))
1409 /* If the previous previous instruction has a load
1410 delay, and sets a register that the branch reads, we
1413 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1415 && (prev_prev_insn
.insn_mo
->pinfo
1416 & INSN_LOAD_MEMORY_DELAY
)))
1417 && insn_uses_reg (ip
,
1418 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1421 /* If one instruction sets a condition code and the
1422 other one uses a condition code, we can not swap. */
1423 || ((pinfo
& INSN_READ_COND_CODE
)
1424 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1425 || ((pinfo
& INSN_WRITE_COND_CODE
)
1426 && (prev_pinfo
& INSN_READ_COND_CODE
)))
1428 /* We could do even better for unconditional branches to
1429 portions of this object file; we could pick up the
1430 instruction at the destination, put it in the delay
1431 slot, and bump the destination address. */
1433 /* Update the previous insn information. */
1434 prev_prev_insn
= *ip
;
1435 prev_insn
.insn_mo
= &dummy_opcode
;
1442 /* It looks like we can actually do the swap. */
1443 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1444 memcpy (temp
, prev_f
, 4);
1445 memcpy (prev_f
, f
, 4);
1446 memcpy (f
, temp
, 4);
1449 prev_insn_fixp
->fx_frag
= frag_now
;
1450 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1454 fixp
->fx_frag
= prev_insn_frag
;
1455 fixp
->fx_where
= prev_insn_where
;
1457 /* Update the previous insn information; leave prev_insn
1459 prev_prev_insn
= *ip
;
1461 prev_insn_is_delay_slot
= 1;
1463 /* If that was an unconditional branch, forget the previous
1464 insn information. */
1465 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1467 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1468 prev_insn
.insn_mo
= &dummy_opcode
;
1471 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1473 /* We don't yet optimize a branch likely. What we should do
1474 is look at the target, copy the instruction found there
1475 into the delay slot, and increment the branch to jump to
1476 the next instruction. */
1478 /* Update the previous insn information. */
1479 prev_prev_insn
= *ip
;
1480 prev_insn
.insn_mo
= &dummy_opcode
;
1484 /* Update the previous insn information. */
1486 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1488 prev_prev_insn
= prev_insn
;
1491 /* Any time we see a branch, we always fill the delay slot
1492 immediately; since this insn is not a branch, we know it
1493 is not in a delay slot. */
1494 prev_insn_is_delay_slot
= 0;
1497 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1498 prev_insn_unreordered
= 0;
1499 prev_insn_frag
= frag_now
;
1500 prev_insn_where
= f
- frag_now
->fr_literal
;
1501 prev_insn_fixp
= fixp
;
1502 prev_insn_valid
= 1;
1505 /* We just output an insn, so the next one doesn't have a label. */
1509 /* This function forgets that there was any previous instruction or
1513 mips_no_prev_insn ()
1515 prev_insn
.insn_mo
= &dummy_opcode
;
1516 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1517 prev_insn_valid
= 0;
1518 prev_insn_is_delay_slot
= 0;
1519 prev_insn_unreordered
= 0;
1520 prev_prev_insn_unreordered
= 0;
1524 /* This function must be called whenever we turn on noreorder or emit
1525 something other than instructions. It inserts any NOPS which might
1526 be needed by the previous instruction, and clears the information
1527 kept for the previous instructions. */
1532 if (! mips_noreorder
)
1538 && (! cop_interlocks
1539 && (prev_insn
.insn_mo
->pinfo
1540 & (INSN_LOAD_COPROC_DELAY
1541 | INSN_COPROC_MOVE_DELAY
1542 | INSN_WRITE_COND_CODE
))))
1544 && (prev_insn
.insn_mo
->pinfo
1548 && (prev_insn
.insn_mo
->pinfo
1549 & (INSN_LOAD_MEMORY_DELAY
1550 | INSN_COPROC_MEMORY_DELAY
))))
1554 && (! cop_interlocks
1555 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1557 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1558 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1561 else if ((mips_isa
< 4
1562 && (! cop_interlocks
1563 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1565 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1566 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1571 if (insn_label
!= NULL
)
1573 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1574 insn_label
->sy_frag
= frag_now
;
1575 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1580 mips_no_prev_insn ();
1583 /* Build an instruction created by a macro expansion. This is passed
1584 a pointer to the count of instructions created so far, an
1585 expression, the name of the instruction to build, an operand format
1586 string, and corresponding arguments. */
1590 macro_build (char *place
,
1598 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1607 struct mips_cl_insn insn
;
1608 bfd_reloc_code_real_type r
;
1612 va_start (args
, fmt
);
1618 * If the macro is about to expand into a second instruction,
1619 * print a warning if needed. We need to pass ip as a parameter
1620 * to generate a better warning message here...
1622 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1623 as_warn ("Macro instruction expanded into multiple instructions");
1626 *counter
+= 1; /* bump instruction counter */
1628 r
= BFD_RELOC_UNUSED
;
1629 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1630 assert (insn
.insn_mo
);
1631 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1633 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1634 || insn
.insn_mo
->pinfo
== INSN_MACRO
1635 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1637 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1639 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1641 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1643 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1645 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1649 assert (insn
.insn_mo
->name
);
1650 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1652 insn
.insn_opcode
= insn
.insn_mo
->match
;
1668 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1674 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1679 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1684 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1691 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1695 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1699 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1706 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1712 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1713 assert (r
== BFD_RELOC_MIPS_GPREL
1714 || r
== BFD_RELOC_MIPS_LITERAL
1715 || r
== BFD_RELOC_LO16
1716 || r
== BFD_RELOC_MIPS_GOT16
1717 || r
== BFD_RELOC_MIPS_CALL16
1718 || r
== BFD_RELOC_MIPS_GOT_LO16
1719 || r
== BFD_RELOC_MIPS_CALL_LO16
1720 || (ep
->X_op
== O_subtract
1721 && now_seg
== text_section
1722 && r
== BFD_RELOC_PCREL_LO16
));
1726 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1728 && (ep
->X_op
== O_constant
1729 || (ep
->X_op
== O_symbol
1730 && (r
== BFD_RELOC_HI16_S
1731 || r
== BFD_RELOC_HI16
1732 || r
== BFD_RELOC_MIPS_GOT_HI16
1733 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1734 || (ep
->X_op
== O_subtract
1735 && now_seg
== text_section
1736 && r
== BFD_RELOC_PCREL_HI16_S
)));
1737 if (ep
->X_op
== O_constant
)
1739 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1741 r
= BFD_RELOC_UNUSED
;
1746 assert (ep
!= NULL
);
1748 * This allows macro() to pass an immediate expression for
1749 * creating short branches without creating a symbol.
1750 * Note that the expression still might come from the assembly
1751 * input, in which case the value is not checked for range nor
1752 * is a relocation entry generated (yuck).
1754 if (ep
->X_op
== O_constant
)
1756 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1760 r
= BFD_RELOC_16_PCREL_S2
;
1764 assert (ep
!= NULL
);
1765 r
= BFD_RELOC_MIPS_JMP
;
1774 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1776 append_insn (place
, &insn
, ep
, r
, false);
1780 * Generate a "lui" instruction.
1783 macro_build_lui (place
, counter
, ep
, regnum
)
1789 expressionS high_expr
;
1790 struct mips_cl_insn insn
;
1791 bfd_reloc_code_real_type r
;
1792 CONST
char *name
= "lui";
1793 CONST
char *fmt
= "t,u";
1799 high_expr
.X_op
= O_constant
;
1800 high_expr
.X_add_number
= ep
->X_add_number
;
1803 if (high_expr
.X_op
== O_constant
)
1805 /* we can compute the instruction now without a relocation entry */
1806 if (high_expr
.X_add_number
& 0x8000)
1807 high_expr
.X_add_number
+= 0x10000;
1808 high_expr
.X_add_number
=
1809 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1810 r
= BFD_RELOC_UNUSED
;
1814 assert (ep
->X_op
== O_symbol
);
1815 /* _gp_disp is a special case, used from s_cpload. */
1816 assert (mips_pic
== NO_PIC
1817 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1818 r
= BFD_RELOC_HI16_S
;
1822 * If the macro is about to expand into a second instruction,
1823 * print a warning if needed. We need to pass ip as a parameter
1824 * to generate a better warning message here...
1826 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1827 as_warn ("Macro instruction expanded into multiple instructions");
1830 *counter
+= 1; /* bump instruction counter */
1832 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1833 assert (insn
.insn_mo
);
1834 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1835 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1837 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1838 if (r
== BFD_RELOC_UNUSED
)
1840 insn
.insn_opcode
|= high_expr
.X_add_number
;
1841 append_insn (place
, &insn
, NULL
, r
, false);
1844 append_insn (place
, &insn
, &high_expr
, r
, false);
1848 * Generates code to set the $at register to true (one)
1849 * if reg is less than the immediate expression.
1852 set_at (counter
, reg
, unsignedp
)
1857 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1858 macro_build ((char *) NULL
, counter
, &imm_expr
,
1859 unsignedp
? "sltiu" : "slti",
1860 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1863 load_register (counter
, AT
, &imm_expr
, 0);
1864 macro_build ((char *) NULL
, counter
, NULL
,
1865 unsignedp
? "sltu" : "slt",
1866 "d,v,t", AT
, reg
, AT
);
1870 /* Warn if an expression is not a constant. */
1873 check_absolute_expr (ip
, ex
)
1874 struct mips_cl_insn
*ip
;
1877 if (ex
->X_op
!= O_constant
)
1878 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1881 /* Count the leading zeroes by performing a binary chop. This is a
1882 bulky bit of source, but performance is a LOT better for the
1883 majority of values than a simple loop to count the bits:
1884 for (lcnt = 0; (lcnt < 32); lcnt++)
1885 if ((v) & (1 << (31 - lcnt)))
1887 However it is not code size friendly, and the gain will drop a bit
1888 on certain cached systems.
1890 #define COUNT_TOP_ZEROES(v) \
1891 (((v) & ~0xffff) == 0 \
1892 ? ((v) & ~0xff) == 0 \
1893 ? ((v) & ~0xf) == 0 \
1894 ? ((v) & ~0x3) == 0 \
1895 ? ((v) & ~0x1) == 0 \
1900 : ((v) & ~0x7) == 0 \
1903 : ((v) & ~0x3f) == 0 \
1904 ? ((v) & ~0x1f) == 0 \
1907 : ((v) & ~0x7f) == 0 \
1910 : ((v) & ~0xfff) == 0 \
1911 ? ((v) & ~0x3ff) == 0 \
1912 ? ((v) & ~0x1ff) == 0 \
1915 : ((v) & ~0x7ff) == 0 \
1918 : ((v) & ~0x3fff) == 0 \
1919 ? ((v) & ~0x1fff) == 0 \
1922 : ((v) & ~0x7fff) == 0 \
1925 : ((v) & ~0xffffff) == 0 \
1926 ? ((v) & ~0xfffff) == 0 \
1927 ? ((v) & ~0x3ffff) == 0 \
1928 ? ((v) & ~0x1ffff) == 0 \
1931 : ((v) & ~0x7ffff) == 0 \
1934 : ((v) & ~0x3fffff) == 0 \
1935 ? ((v) & ~0x1fffff) == 0 \
1938 : ((v) & ~0x7fffff) == 0 \
1941 : ((v) & ~0xfffffff) == 0 \
1942 ? ((v) & ~0x3ffffff) == 0 \
1943 ? ((v) & ~0x1ffffff) == 0 \
1946 : ((v) & ~0x7ffffff) == 0 \
1949 : ((v) & ~0x3fffffff) == 0 \
1950 ? ((v) & ~0x1fffffff) == 0 \
1953 : ((v) & ~0x7fffffff) == 0 \
1958 * This routine generates the least number of instructions neccessary to load
1959 * an absolute expression value into a register.
1962 load_register (counter
, reg
, ep
, dbl
)
1969 expressionS hi32
, lo32
, tmp
;
1971 if (ep
->X_op
!= O_big
)
1973 assert (ep
->X_op
== O_constant
);
1974 if (ep
->X_add_number
< 0x8000
1975 && (ep
->X_add_number
>= 0
1976 || (ep
->X_add_number
>= -0x8000
1979 || sizeof (ep
->X_add_number
) > 4))))
1981 /* We can handle 16 bit signed values with an addiu to
1982 $zero. No need to ever use daddiu here, since $zero and
1983 the result are always correct in 32 bit mode. */
1984 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1985 (int) BFD_RELOC_LO16
);
1988 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1990 /* We can handle 16 bit unsigned values with an ori to
1992 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1993 (int) BFD_RELOC_LO16
);
1996 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1997 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1998 == ~ (offsetT
) 0x7fffffff))
2001 || sizeof (ep
->X_add_number
) > 4
2002 || (ep
->X_add_number
& 0x80000000) == 0))
2003 || ((mips_isa
< 3 || !dbl
)
2004 && (ep
->X_add_number
&~ 0xffffffff) == 0))
2006 /* 32 bit values require an lui. */
2007 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2008 (int) BFD_RELOC_HI16
);
2009 if ((ep
->X_add_number
& 0xffff) != 0)
2010 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2011 (int) BFD_RELOC_LO16
);
2016 /* The value is larger than 32 bits. */
2020 as_bad ("Number larger than 32 bits");
2021 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2022 (int) BFD_RELOC_LO16
);
2026 if (ep
->X_op
!= O_big
)
2030 hi32
.X_add_number
>>= shift
;
2031 hi32
.X_add_number
&= 0xffffffff;
2032 if ((hi32
.X_add_number
& 0x80000000) != 0)
2033 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2035 lo32
.X_add_number
&= 0xffffffff;
2039 assert (ep
->X_add_number
> 2);
2040 if (ep
->X_add_number
== 3)
2041 generic_bignum
[3] = 0;
2042 else if (ep
->X_add_number
> 4)
2043 as_bad ("Number larger than 64 bits");
2044 lo32
.X_op
= O_constant
;
2045 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2046 hi32
.X_op
= O_constant
;
2047 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2050 if (hi32
.X_add_number
== 0)
2054 if (hi32
.X_add_number
== 0xffffffff)
2056 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2058 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
2059 (int) BFD_RELOC_LO16
);
2062 if (lo32
.X_add_number
& 0x80000000)
2064 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2065 (int) BFD_RELOC_HI16
);
2066 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
2067 (int) BFD_RELOC_LO16
);
2072 /* Check for 16bit shifted constant: */
2074 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2075 /* We know that hi32 is non-zero, so start the mask on the first
2076 bit of the hi32 value: */
2080 if ((tmp
.X_add_number
& ~((offsetT
)0xffff << shift
)) == 0)
2082 tmp
.X_op
= O_constant
;
2083 tmp
.X_add_number
>>= shift
;
2084 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2085 (int) BFD_RELOC_LO16
);
2086 macro_build ((char *) NULL
, counter
, NULL
,
2087 (shift
>= 32) ? "dsll32" : "dsll",
2088 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2092 } while (shift
<= (64 - 16));
2096 tmp
.X_add_number
= hi32
.X_add_number
<< shift
| lo32
.X_add_number
;
2097 while ((tmp
.X_add_number
& 1) == 0)
2099 tmp
.X_add_number
>>= 1;
2102 if (((tmp
.X_add_number
+ 1) & tmp
.X_add_number
) == 0) /* (power-of-2 - 1) */
2104 shift
= COUNT_TOP_ZEROES((unsigned int)hi32
.X_add_number
);
2107 tmp
.X_op
= O_constant
;
2108 tmp
.X_add_number
= (offsetT
)-1;
2109 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j", reg
, 0,
2110 (int) BFD_RELOC_LO16
); /* set all ones */
2114 macro_build ((char *) NULL
, counter
, NULL
,
2115 (freg
>= 32) ? "dsll32" : "dsll",
2117 (freg
>= 32) ? freg
- 32 : freg
);
2119 macro_build ((char *) NULL
, counter
, NULL
, (shift
>= 32) ? "dsrl32" : "dsrl",
2120 "d,w,<", reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
2124 load_register (counter
, reg
, &hi32
, 0);
2127 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2131 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2140 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2142 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2143 (int) BFD_RELOC_HI16
);
2144 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2151 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2156 mid16
.X_add_number
>>= 16;
2157 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2158 freg
, (int) BFD_RELOC_LO16
);
2159 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2163 if ((lo32
.X_add_number
& 0xffff) != 0)
2164 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2165 (int) BFD_RELOC_LO16
);
2168 /* Load an address into a register. */
2171 load_address (counter
, reg
, ep
)
2178 if (ep
->X_op
!= O_constant
2179 && ep
->X_op
!= O_symbol
)
2181 as_bad ("expression too complex");
2182 ep
->X_op
= O_constant
;
2185 if (ep
->X_op
== O_constant
)
2187 load_register (counter
, reg
, ep
, 0);
2191 if (mips_pic
== NO_PIC
)
2193 /* If this is a reference to a GP relative symbol, we want
2194 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2196 lui $reg,<sym> (BFD_RELOC_HI16_S)
2197 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2198 If we have an addend, we always use the latter form. */
2199 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2200 || nopic_need_relax (ep
->X_add_symbol
))
2205 macro_build ((char *) NULL
, counter
, ep
,
2206 mips_isa
< 3 ? "addiu" : "daddiu",
2207 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2208 p
= frag_var (rs_machine_dependent
, 8, 0,
2209 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2210 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2212 macro_build_lui (p
, counter
, ep
, reg
);
2215 macro_build (p
, counter
, ep
,
2216 mips_isa
< 3 ? "addiu" : "daddiu",
2217 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2219 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2223 /* If this is a reference to an external symbol, we want
2224 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2226 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2228 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2229 If there is a constant, it must be added in after. */
2230 ex
.X_add_number
= ep
->X_add_number
;
2231 ep
->X_add_number
= 0;
2233 macro_build ((char *) NULL
, counter
, ep
,
2234 mips_isa
< 3 ? "lw" : "ld",
2235 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2236 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2237 p
= frag_var (rs_machine_dependent
, 4, 0,
2238 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2239 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2240 macro_build (p
, counter
, ep
,
2241 mips_isa
< 3 ? "addiu" : "daddiu",
2242 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2243 if (ex
.X_add_number
!= 0)
2245 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2246 as_bad ("PIC code offset overflow (max 16 signed bits)");
2247 ex
.X_op
= O_constant
;
2248 macro_build ((char *) NULL
, counter
, &ex
,
2249 mips_isa
< 3 ? "addiu" : "daddiu",
2250 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2253 else if (mips_pic
== SVR4_PIC
)
2258 /* This is the large GOT case. If this is a reference to an
2259 external symbol, we want
2260 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2262 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2263 Otherwise, for a reference to a local symbol, we want
2264 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2266 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2267 If there is a constant, it must be added in after. */
2268 ex
.X_add_number
= ep
->X_add_number
;
2269 ep
->X_add_number
= 0;
2270 if (reg_needs_delay (GP
))
2275 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2276 (int) BFD_RELOC_MIPS_GOT_HI16
);
2277 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2278 mips_isa
< 3 ? "addu" : "daddu",
2279 "d,v,t", reg
, reg
, GP
);
2280 macro_build ((char *) NULL
, counter
, ep
,
2281 mips_isa
< 3 ? "lw" : "ld",
2282 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2283 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2284 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2285 mips_warn_about_macros
),
2286 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2289 /* We need a nop before loading from $gp. This special
2290 check is required because the lui which starts the main
2291 instruction stream does not refer to $gp, and so will not
2292 insert the nop which may be required. */
2293 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2296 macro_build (p
, counter
, ep
,
2297 mips_isa
< 3 ? "lw" : "ld",
2298 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2300 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2302 macro_build (p
, counter
, ep
,
2303 mips_isa
< 3 ? "addiu" : "daddiu",
2304 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2305 if (ex
.X_add_number
!= 0)
2307 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2308 as_bad ("PIC code offset overflow (max 16 signed bits)");
2309 ex
.X_op
= O_constant
;
2310 macro_build ((char *) NULL
, counter
, &ex
,
2311 mips_isa
< 3 ? "addiu" : "daddiu",
2312 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2315 else if (mips_pic
== EMBEDDED_PIC
)
2318 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2320 macro_build ((char *) NULL
, counter
, ep
,
2321 mips_isa
< 3 ? "addiu" : "daddiu",
2322 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2330 * This routine implements the seemingly endless macro or synthesized
2331 * instructions and addressing modes in the mips assembly language. Many
2332 * of these macros are simple and are similar to each other. These could
2333 * probably be handled by some kind of table or grammer aproach instead of
2334 * this verbose method. Others are not simple macros but are more like
2335 * optimizing code generation.
2336 * One interesting optimization is when several store macros appear
2337 * consecutivly that would load AT with the upper half of the same address.
2338 * The ensuing load upper instructions are ommited. This implies some kind
2339 * of global optimization. We currently only optimize within a single macro.
2340 * For many of the load and store macros if the address is specified as a
2341 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2342 * first load register 'at' with zero and use it as the base register. The
2343 * mips assembler simply uses register $zero. Just one tiny optimization
2348 struct mips_cl_insn
*ip
;
2350 register int treg
, sreg
, dreg
, breg
;
2365 bfd_reloc_code_real_type r
;
2367 int hold_mips_optimize
;
2369 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2370 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2371 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2372 mask
= ip
->insn_mo
->mask
;
2374 expr1
.X_op
= O_constant
;
2375 expr1
.X_op_symbol
= NULL
;
2376 expr1
.X_add_symbol
= NULL
;
2377 expr1
.X_add_number
= 1;
2389 mips_emit_delays ();
2391 mips_any_noreorder
= 1;
2393 expr1
.X_add_number
= 8;
2394 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2396 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2398 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2399 macro_build ((char *) NULL
, &icnt
, NULL
,
2400 dbl
? "dsub" : "sub",
2401 "d,v,t", dreg
, 0, sreg
);
2424 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2426 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2427 (int) BFD_RELOC_LO16
);
2430 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2431 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2450 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2452 if (mask
!= M_NOR_I
)
2453 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2454 sreg
, (int) BFD_RELOC_LO16
);
2457 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2458 treg
, sreg
, (int) BFD_RELOC_LO16
);
2459 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2465 load_register (&icnt
, AT
, &imm_expr
, 0);
2466 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2483 if (imm_expr
.X_add_number
== 0)
2485 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2489 load_register (&icnt
, AT
, &imm_expr
, 0);
2490 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2498 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2499 likely
? "bgezl" : "bgez",
2505 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2506 likely
? "blezl" : "blez",
2510 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2511 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2512 likely
? "beql" : "beq",
2519 /* check for > max integer */
2520 maxnum
= 0x7fffffff;
2528 if (imm_expr
.X_add_number
>= maxnum
2529 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2532 /* result is always false */
2535 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2536 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2540 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2541 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2546 imm_expr
.X_add_number
++;
2550 if (mask
== M_BGEL_I
)
2552 if (imm_expr
.X_add_number
== 0)
2554 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2555 likely
? "bgezl" : "bgez",
2559 if (imm_expr
.X_add_number
== 1)
2561 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2562 likely
? "bgtzl" : "bgtz",
2566 maxnum
= 0x7fffffff;
2574 maxnum
= - maxnum
- 1;
2575 if (imm_expr
.X_add_number
<= maxnum
2576 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2579 /* result is always true */
2580 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2581 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2584 set_at (&icnt
, sreg
, 0);
2585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2586 likely
? "beql" : "beq",
2597 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2598 likely
? "beql" : "beq",
2602 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2604 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2605 likely
? "beql" : "beq",
2612 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2614 imm_expr
.X_add_number
++;
2618 if (mask
== M_BGEUL_I
)
2620 if (imm_expr
.X_add_number
== 0)
2622 if (imm_expr
.X_add_number
== 1)
2624 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2625 likely
? "bnel" : "bne",
2629 set_at (&icnt
, sreg
, 1);
2630 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2631 likely
? "beql" : "beq",
2640 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2641 likely
? "bgtzl" : "bgtz",
2647 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2648 likely
? "bltzl" : "bltz",
2652 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2653 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2654 likely
? "bnel" : "bne",
2663 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2664 likely
? "bnel" : "bne",
2670 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2672 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2673 likely
? "bnel" : "bne",
2682 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2683 likely
? "blezl" : "blez",
2689 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2690 likely
? "bgezl" : "bgez",
2694 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2695 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2696 likely
? "beql" : "beq",
2703 maxnum
= 0x7fffffff;
2711 if (imm_expr
.X_add_number
>= maxnum
2712 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2714 imm_expr
.X_add_number
++;
2718 if (mask
== M_BLTL_I
)
2720 if (imm_expr
.X_add_number
== 0)
2722 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2723 likely
? "bltzl" : "bltz",
2727 if (imm_expr
.X_add_number
== 1)
2729 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2730 likely
? "blezl" : "blez",
2734 set_at (&icnt
, sreg
, 0);
2735 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2736 likely
? "bnel" : "bne",
2745 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2746 likely
? "beql" : "beq",
2752 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2754 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2755 likely
? "beql" : "beq",
2762 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2764 imm_expr
.X_add_number
++;
2768 if (mask
== M_BLTUL_I
)
2770 if (imm_expr
.X_add_number
== 0)
2772 if (imm_expr
.X_add_number
== 1)
2774 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2775 likely
? "beql" : "beq",
2779 set_at (&icnt
, sreg
, 1);
2780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2781 likely
? "bnel" : "bne",
2790 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2791 likely
? "bltzl" : "bltz",
2797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2798 likely
? "bgtzl" : "bgtz",
2802 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2803 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2804 likely
? "bnel" : "bne",
2815 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2816 likely
? "bnel" : "bne",
2820 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2822 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2823 likely
? "bnel" : "bne",
2839 as_warn ("Divide by zero.");
2841 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2843 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2847 mips_emit_delays ();
2849 mips_any_noreorder
= 1;
2850 macro_build ((char *) NULL
, &icnt
, NULL
,
2851 dbl
? "ddiv" : "div",
2852 "z,s,t", sreg
, treg
);
2854 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2857 expr1
.X_add_number
= 8;
2858 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2859 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2860 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2862 expr1
.X_add_number
= -1;
2863 macro_build ((char *) NULL
, &icnt
, &expr1
,
2864 dbl
? "daddiu" : "addiu",
2865 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2866 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2867 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2870 expr1
.X_add_number
= 1;
2871 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2872 (int) BFD_RELOC_LO16
);
2873 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2878 expr1
.X_add_number
= 0x80000000;
2879 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2880 (int) BFD_RELOC_HI16
);
2883 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2886 expr1
.X_add_number
= 8;
2887 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2888 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2889 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2892 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2931 if (imm_expr
.X_add_number
== 0)
2933 as_warn ("Divide by zero.");
2935 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2937 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2940 if (imm_expr
.X_add_number
== 1)
2942 if (strcmp (s2
, "mflo") == 0)
2943 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2946 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2949 if (imm_expr
.X_add_number
== -1
2950 && s
[strlen (s
) - 1] != 'u')
2952 if (strcmp (s2
, "mflo") == 0)
2955 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2958 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2962 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2966 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2967 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2968 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2987 mips_emit_delays ();
2989 mips_any_noreorder
= 1;
2990 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2992 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2995 expr1
.X_add_number
= 8;
2996 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2997 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2998 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3001 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3007 /* Load the address of a symbol into a register. If breg is not
3008 zero, we then add a base register to it. */
3010 /* When generating embedded PIC code, we permit expressions of
3013 where bar is an address in the .text section. These are used
3014 when getting the addresses of functions. We don't permit
3015 X_add_number to be non-zero, because if the symbol is
3016 external the relaxing code needs to know that any addend is
3017 purely the offset to X_op_symbol. */
3018 if (mips_pic
== EMBEDDED_PIC
3019 && offset_expr
.X_op
== O_subtract
3020 && now_seg
== text_section
3021 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3022 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3023 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3024 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3025 ->sy_value
.X_add_symbol
)
3028 && offset_expr
.X_add_number
== 0)
3030 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3031 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3033 mips_isa
< 3 ? "addiu" : "daddiu",
3034 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3038 if (offset_expr
.X_op
!= O_symbol
3039 && offset_expr
.X_op
!= O_constant
)
3041 as_bad ("expression too complex");
3042 offset_expr
.X_op
= O_constant
;
3056 if (offset_expr
.X_op
== O_constant
)
3057 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3058 else if (mips_pic
== NO_PIC
)
3060 /* If this is a reference to an GP relative symbol, we want
3061 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3063 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3064 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3065 If we have a constant, we need two instructions anyhow,
3066 so we may as well always use the latter form. */
3067 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3068 || nopic_need_relax (offset_expr
.X_add_symbol
))
3073 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3074 mips_isa
< 3 ? "addiu" : "daddiu",
3075 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3076 p
= frag_var (rs_machine_dependent
, 8, 0,
3077 RELAX_ENCODE (4, 8, 0, 4, 0,
3078 mips_warn_about_macros
),
3079 offset_expr
.X_add_symbol
, (long) 0,
3082 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3085 macro_build (p
, &icnt
, &offset_expr
,
3086 mips_isa
< 3 ? "addiu" : "daddiu",
3087 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3089 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3091 /* If this is a reference to an external symbol, and there
3092 is no constant, we want
3093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3094 For a local symbol, we want
3095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3097 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3099 If we have a small constant, and this is a reference to
3100 an external symbol, we want
3101 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3103 addiu $tempreg,$tempreg,<constant>
3104 For a local symbol, we want the same instruction
3105 sequence, but we output a BFD_RELOC_LO16 reloc on the
3108 If we have a large constant, and this is a reference to
3109 an external symbol, we want
3110 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3111 lui $at,<hiconstant>
3112 addiu $at,$at,<loconstant>
3113 addu $tempreg,$tempreg,$at
3114 For a local symbol, we want the same instruction
3115 sequence, but we output a BFD_RELOC_LO16 reloc on the
3116 addiu instruction. */
3117 expr1
.X_add_number
= offset_expr
.X_add_number
;
3118 offset_expr
.X_add_number
= 0;
3120 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3122 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3123 if (expr1
.X_add_number
== 0)
3131 /* We're going to put in an addu instruction using
3132 tempreg, so we may as well insert the nop right
3134 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3138 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3139 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3141 ? mips_warn_about_macros
3143 offset_expr
.X_add_symbol
, (long) 0,
3147 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3150 macro_build (p
, &icnt
, &expr1
,
3151 mips_isa
< 3 ? "addiu" : "daddiu",
3152 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3153 /* FIXME: If breg == 0, and the next instruction uses
3154 $tempreg, then if this variant case is used an extra
3155 nop will be generated. */
3157 else if (expr1
.X_add_number
>= -0x8000
3158 && expr1
.X_add_number
< 0x8000)
3160 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3162 macro_build ((char *) NULL
, &icnt
, &expr1
,
3163 mips_isa
< 3 ? "addiu" : "daddiu",
3164 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3165 (void) frag_var (rs_machine_dependent
, 0, 0,
3166 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3167 offset_expr
.X_add_symbol
, (long) 0,
3174 /* If we are going to add in a base register, and the
3175 target register and the base register are the same,
3176 then we are using AT as a temporary register. Since
3177 we want to load the constant into AT, we add our
3178 current AT (from the global offset table) and the
3179 register into the register now, and pretend we were
3180 not using a base register. */
3185 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3187 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3188 mips_isa
< 3 ? "addu" : "daddu",
3189 "d,v,t", treg
, AT
, breg
);
3195 /* Set mips_optimize around the lui instruction to avoid
3196 inserting an unnecessary nop after the lw. */
3197 hold_mips_optimize
= mips_optimize
;
3199 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3200 mips_optimize
= hold_mips_optimize
;
3202 macro_build ((char *) NULL
, &icnt
, &expr1
,
3203 mips_isa
< 3 ? "addiu" : "daddiu",
3204 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3205 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3206 mips_isa
< 3 ? "addu" : "daddu",
3207 "d,v,t", tempreg
, tempreg
, AT
);
3208 (void) frag_var (rs_machine_dependent
, 0, 0,
3209 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3210 offset_expr
.X_add_symbol
, (long) 0,
3215 else if (mips_pic
== SVR4_PIC
)
3219 /* This is the large GOT case. If this is a reference to an
3220 external symbol, and there is no constant, we want
3221 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3222 addu $tempreg,$tempreg,$gp
3223 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3224 For a local symbol, we want
3225 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3227 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3229 If we have a small constant, and this is a reference to
3230 an external symbol, we want
3231 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3232 addu $tempreg,$tempreg,$gp
3233 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3235 addiu $tempreg,$tempreg,<constant>
3236 For a local symbol, we want
3237 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3239 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3241 If we have a large constant, and this is a reference to
3242 an external symbol, we want
3243 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3244 addu $tempreg,$tempreg,$gp
3245 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3246 lui $at,<hiconstant>
3247 addiu $at,$at,<loconstant>
3248 addu $tempreg,$tempreg,$at
3249 For a local symbol, we want
3250 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3251 lui $at,<hiconstant>
3252 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3253 addu $tempreg,$tempreg,$at
3255 expr1
.X_add_number
= offset_expr
.X_add_number
;
3256 offset_expr
.X_add_number
= 0;
3258 if (reg_needs_delay (GP
))
3262 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3263 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3264 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3265 mips_isa
< 3 ? "addu" : "daddu",
3266 "d,v,t", tempreg
, tempreg
, GP
);
3267 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3269 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3271 if (expr1
.X_add_number
== 0)
3279 /* We're going to put in an addu instruction using
3280 tempreg, so we may as well insert the nop right
3282 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3287 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3288 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3291 ? mips_warn_about_macros
3293 offset_expr
.X_add_symbol
, (long) 0,
3296 else if (expr1
.X_add_number
>= -0x8000
3297 && expr1
.X_add_number
< 0x8000)
3299 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3301 macro_build ((char *) NULL
, &icnt
, &expr1
,
3302 mips_isa
< 3 ? "addiu" : "daddiu",
3303 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3305 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3306 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3308 ? mips_warn_about_macros
3310 offset_expr
.X_add_symbol
, (long) 0,
3317 /* If we are going to add in a base register, and the
3318 target register and the base register are the same,
3319 then we are using AT as a temporary register. Since
3320 we want to load the constant into AT, we add our
3321 current AT (from the global offset table) and the
3322 register into the register now, and pretend we were
3323 not using a base register. */
3331 assert (tempreg
== AT
);
3332 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3334 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3335 mips_isa
< 3 ? "addu" : "daddu",
3336 "d,v,t", treg
, AT
, breg
);
3341 /* Set mips_optimize around the lui instruction to avoid
3342 inserting an unnecessary nop after the lw. */
3343 hold_mips_optimize
= mips_optimize
;
3345 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3346 mips_optimize
= hold_mips_optimize
;
3348 macro_build ((char *) NULL
, &icnt
, &expr1
,
3349 mips_isa
< 3 ? "addiu" : "daddiu",
3350 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3351 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3352 mips_isa
< 3 ? "addu" : "daddu",
3353 "d,v,t", dreg
, dreg
, AT
);
3355 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3356 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3359 ? mips_warn_about_macros
3361 offset_expr
.X_add_symbol
, (long) 0,
3369 /* This is needed because this instruction uses $gp, but
3370 the first instruction on the main stream does not. */
3371 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3374 macro_build (p
, &icnt
, &offset_expr
,
3376 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3378 if (expr1
.X_add_number
>= -0x8000
3379 && expr1
.X_add_number
< 0x8000)
3381 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3383 macro_build (p
, &icnt
, &expr1
,
3384 mips_isa
< 3 ? "addiu" : "daddiu",
3385 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3386 /* FIXME: If add_number is 0, and there was no base
3387 register, the external symbol case ended with a load,
3388 so if the symbol turns out to not be external, and
3389 the next instruction uses tempreg, an unnecessary nop
3390 will be inserted. */
3396 /* We must add in the base register now, as in the
3397 external symbol case. */
3398 assert (tempreg
== AT
);
3399 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3401 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3402 mips_isa
< 3 ? "addu" : "daddu",
3403 "d,v,t", treg
, AT
, breg
);
3406 /* We set breg to 0 because we have arranged to add
3407 it in in both cases. */
3411 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3413 macro_build (p
, &icnt
, &expr1
,
3414 mips_isa
< 3 ? "addiu" : "daddiu",
3415 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3417 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3418 mips_isa
< 3 ? "addu" : "daddu",
3419 "d,v,t", tempreg
, tempreg
, AT
);
3423 else if (mips_pic
== EMBEDDED_PIC
)
3426 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3428 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3429 mips_isa
< 3 ? "addiu" : "daddiu",
3430 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3436 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3437 mips_isa
< 3 ? "addu" : "daddu",
3438 "d,v,t", treg
, tempreg
, breg
);
3446 /* The j instruction may not be used in PIC code, since it
3447 requires an absolute address. We convert it to a b
3449 if (mips_pic
== NO_PIC
)
3450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3452 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3455 /* The jal instructions must be handled as macros because when
3456 generating PIC code they expand to multi-instruction
3457 sequences. Normally they are simple instructions. */
3462 if (mips_pic
== NO_PIC
3463 || mips_pic
== EMBEDDED_PIC
)
3464 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3466 else if (mips_pic
== SVR4_PIC
)
3468 if (sreg
!= PIC_CALL_REG
)
3469 as_warn ("MIPS PIC call to register other than $25");
3471 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3473 if (mips_cprestore_offset
< 0)
3474 as_warn ("No .cprestore pseudo-op used in PIC code");
3477 expr1
.X_add_number
= mips_cprestore_offset
;
3478 macro_build ((char *) NULL
, &icnt
, &expr1
,
3479 mips_isa
< 3 ? "lw" : "ld",
3480 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3489 if (mips_pic
== NO_PIC
)
3490 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3491 else if (mips_pic
== SVR4_PIC
)
3493 /* If this is a reference to an external symbol, and we are
3494 using a small GOT, we want
3495 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3499 lw $gp,cprestore($sp)
3500 The cprestore value is set using the .cprestore
3501 pseudo-op. If we are using a big GOT, we want
3502 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3504 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3508 lw $gp,cprestore($sp)
3509 If the symbol is not external, we want
3510 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3512 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3515 lw $gp,cprestore($sp) */
3519 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3520 mips_isa
< 3 ? "lw" : "ld",
3521 "t,o(b)", PIC_CALL_REG
,
3522 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3523 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3525 p
= frag_var (rs_machine_dependent
, 4, 0,
3526 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3527 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3533 if (reg_needs_delay (GP
))
3537 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3538 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3539 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3540 mips_isa
< 3 ? "addu" : "daddu",
3541 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3542 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3543 mips_isa
< 3 ? "lw" : "ld",
3544 "t,o(b)", PIC_CALL_REG
,
3545 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3546 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3548 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3549 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3551 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3554 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3557 macro_build (p
, &icnt
, &offset_expr
,
3558 mips_isa
< 3 ? "lw" : "ld",
3559 "t,o(b)", PIC_CALL_REG
,
3560 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3562 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3565 macro_build (p
, &icnt
, &offset_expr
,
3566 mips_isa
< 3 ? "addiu" : "daddiu",
3567 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3568 (int) BFD_RELOC_LO16
);
3569 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3570 "jalr", "s", PIC_CALL_REG
);
3571 if (mips_cprestore_offset
< 0)
3572 as_warn ("No .cprestore pseudo-op used in PIC code");
3576 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3578 expr1
.X_add_number
= mips_cprestore_offset
;
3579 macro_build ((char *) NULL
, &icnt
, &expr1
,
3580 mips_isa
< 3 ? "lw" : "ld",
3581 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3585 else if (mips_pic
== EMBEDDED_PIC
)
3587 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3588 /* The linker may expand the call to a longer sequence which
3589 uses $at, so we must break rather than return. */
3665 if (breg
== treg
|| coproc
|| lr
)
3734 if (mask
== M_LWC1_AB
3735 || mask
== M_SWC1_AB
3736 || mask
== M_LDC1_AB
3737 || mask
== M_SDC1_AB
3746 if (offset_expr
.X_op
!= O_constant
3747 && offset_expr
.X_op
!= O_symbol
)
3749 as_bad ("expression too complex");
3750 offset_expr
.X_op
= O_constant
;
3753 /* A constant expression in PIC code can be handled just as it
3754 is in non PIC code. */
3755 if (mips_pic
== NO_PIC
3756 || offset_expr
.X_op
== O_constant
)
3758 /* If this is a reference to a GP relative symbol, and there
3759 is no base register, we want
3760 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3761 Otherwise, if there is no base register, we want
3762 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3763 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3764 If we have a constant, we need two instructions anyhow,
3765 so we always use the latter form.
3767 If we have a base register, and this is a reference to a
3768 GP relative symbol, we want
3769 addu $tempreg,$breg,$gp
3770 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3772 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3773 addu $tempreg,$tempreg,$breg
3774 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3775 With a constant we always use the latter case. */
3778 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3779 || nopic_need_relax (offset_expr
.X_add_symbol
))
3784 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3785 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3786 p
= frag_var (rs_machine_dependent
, 8, 0,
3787 RELAX_ENCODE (4, 8, 0, 4, 0,
3788 (mips_warn_about_macros
3789 || (used_at
&& mips_noat
))),
3790 offset_expr
.X_add_symbol
, (long) 0,
3794 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3797 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3798 (int) BFD_RELOC_LO16
, tempreg
);
3802 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3803 || nopic_need_relax (offset_expr
.X_add_symbol
))
3808 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3809 mips_isa
< 3 ? "addu" : "daddu",
3810 "d,v,t", tempreg
, breg
, GP
);
3811 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3812 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3813 p
= frag_var (rs_machine_dependent
, 12, 0,
3814 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3815 offset_expr
.X_add_symbol
, (long) 0,
3818 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3821 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3822 mips_isa
< 3 ? "addu" : "daddu",
3823 "d,v,t", tempreg
, tempreg
, breg
);
3826 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3827 (int) BFD_RELOC_LO16
, tempreg
);
3830 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3832 /* If this is a reference to an external symbol, we want
3833 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3835 <op> $treg,0($tempreg)
3837 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3839 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3840 <op> $treg,0($tempreg)
3841 If there is a base register, we add it to $tempreg before
3842 the <op>. If there is a constant, we stick it in the
3843 <op> instruction. We don't handle constants larger than
3844 16 bits, because we have no way to load the upper 16 bits
3845 (actually, we could handle them for the subset of cases
3846 in which we are not using $at). */
3847 assert (offset_expr
.X_op
== O_symbol
);
3848 expr1
.X_add_number
= offset_expr
.X_add_number
;
3849 offset_expr
.X_add_number
= 0;
3850 if (expr1
.X_add_number
< -0x8000
3851 || expr1
.X_add_number
>= 0x8000)
3852 as_bad ("PIC code offset overflow (max 16 signed bits)");
3854 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3855 mips_isa
< 3 ? "lw" : "ld",
3856 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3858 p
= frag_var (rs_machine_dependent
, 4, 0,
3859 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3860 offset_expr
.X_add_symbol
, (long) 0,
3862 macro_build (p
, &icnt
, &offset_expr
,
3863 mips_isa
< 3 ? "addiu" : "daddiu",
3864 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3866 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3867 mips_isa
< 3 ? "addu" : "daddu",
3868 "d,v,t", tempreg
, tempreg
, breg
);
3869 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3870 (int) BFD_RELOC_LO16
, tempreg
);
3872 else if (mips_pic
== SVR4_PIC
)
3876 /* If this is a reference to an external symbol, we want
3877 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3878 addu $tempreg,$tempreg,$gp
3879 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3880 <op> $treg,0($tempreg)
3882 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3884 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3885 <op> $treg,0($tempreg)
3886 If there is a base register, we add it to $tempreg before
3887 the <op>. If there is a constant, we stick it in the
3888 <op> instruction. We don't handle constants larger than
3889 16 bits, because we have no way to load the upper 16 bits
3890 (actually, we could handle them for the subset of cases
3891 in which we are not using $at). */
3892 assert (offset_expr
.X_op
== O_symbol
);
3893 expr1
.X_add_number
= offset_expr
.X_add_number
;
3894 offset_expr
.X_add_number
= 0;
3895 if (expr1
.X_add_number
< -0x8000
3896 || expr1
.X_add_number
>= 0x8000)
3897 as_bad ("PIC code offset overflow (max 16 signed bits)");
3898 if (reg_needs_delay (GP
))
3903 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3904 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3906 mips_isa
< 3 ? "addu" : "daddu",
3907 "d,v,t", tempreg
, tempreg
, GP
);
3908 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3909 mips_isa
< 3 ? "lw" : "ld",
3910 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3912 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3913 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3914 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3917 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3920 macro_build (p
, &icnt
, &offset_expr
,
3921 mips_isa
< 3 ? "lw" : "ld",
3922 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3924 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3926 macro_build (p
, &icnt
, &offset_expr
,
3927 mips_isa
< 3 ? "addiu" : "daddiu",
3928 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3930 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3931 mips_isa
< 3 ? "addu" : "daddu",
3932 "d,v,t", tempreg
, tempreg
, breg
);
3933 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3934 (int) BFD_RELOC_LO16
, tempreg
);
3936 else if (mips_pic
== EMBEDDED_PIC
)
3938 /* If there is no base register, we want
3939 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3940 If there is a base register, we want
3941 addu $tempreg,$breg,$gp
3942 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3944 assert (offset_expr
.X_op
== O_symbol
);
3947 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3948 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3953 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3954 mips_isa
< 3 ? "addu" : "daddu",
3955 "d,v,t", tempreg
, breg
, GP
);
3956 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3957 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3970 load_register (&icnt
, treg
, &imm_expr
, 0);
3974 load_register (&icnt
, treg
, &imm_expr
, 1);
3978 if (imm_expr
.X_op
== O_constant
)
3980 load_register (&icnt
, AT
, &imm_expr
, 0);
3981 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3982 "mtc1", "t,G", AT
, treg
);
3987 assert (offset_expr
.X_op
== O_symbol
3988 && strcmp (segment_name (S_GET_SEGMENT
3989 (offset_expr
.X_add_symbol
)),
3991 && offset_expr
.X_add_number
== 0);
3992 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3993 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3998 /* We know that sym is in the .rdata section. First we get the
3999 upper 16 bits of the address. */
4000 if (mips_pic
== NO_PIC
)
4002 /* FIXME: This won't work for a 64 bit address. */
4003 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4005 else if (mips_pic
== SVR4_PIC
)
4007 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4008 mips_isa
< 3 ? "lw" : "ld",
4009 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4011 else if (mips_pic
== EMBEDDED_PIC
)
4013 /* For embedded PIC we pick up the entire address off $gp in
4014 a single instruction. */
4015 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4016 mips_isa
< 3 ? "addiu" : "daddiu",
4017 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4018 offset_expr
.X_op
= O_constant
;
4019 offset_expr
.X_add_number
= 0;
4024 /* Now we load the register(s). */
4026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4027 treg
, (int) BFD_RELOC_LO16
, AT
);
4030 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4031 treg
, (int) BFD_RELOC_LO16
, AT
);
4034 /* FIXME: How in the world do we deal with the possible
4036 offset_expr
.X_add_number
+= 4;
4037 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4038 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4042 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4043 does not become a variant frag. */
4044 frag_wane (frag_now
);
4050 assert (offset_expr
.X_op
== O_symbol
4051 && offset_expr
.X_add_number
== 0);
4052 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4053 if (strcmp (s
, ".lit8") == 0)
4057 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4058 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4062 r
= BFD_RELOC_MIPS_LITERAL
;
4067 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4068 if (mips_pic
== SVR4_PIC
)
4069 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4070 mips_isa
< 3 ? "lw" : "ld",
4071 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4074 /* FIXME: This won't work for a 64 bit address. */
4075 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4080 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4081 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4083 /* To avoid confusion in tc_gen_reloc, we must ensure
4084 that this does not become a variant frag. */
4085 frag_wane (frag_now
);
4096 /* Even on a big endian machine $fn comes before $fn+1. We have
4097 to adjust when loading from memory. */
4100 assert (mips_isa
< 2);
4101 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4102 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4104 /* FIXME: A possible overflow which I don't know how to deal
4106 offset_expr
.X_add_number
+= 4;
4107 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4108 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4111 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4112 does not become a variant frag. */
4113 frag_wane (frag_now
);
4122 * The MIPS assembler seems to check for X_add_number not
4123 * being double aligned and generating:
4126 * addiu at,at,%lo(foo+1)
4129 * But, the resulting address is the same after relocation so why
4130 * generate the extra instruction?
4177 if (offset_expr
.X_op
!= O_symbol
4178 && offset_expr
.X_op
!= O_constant
)
4180 as_bad ("expression too complex");
4181 offset_expr
.X_op
= O_constant
;
4184 /* Even on a big endian machine $fn comes before $fn+1. We have
4185 to adjust when loading from memory. We set coproc if we must
4186 load $fn+1 first. */
4187 if (byte_order
== LITTLE_ENDIAN
)
4190 if (mips_pic
== NO_PIC
4191 || offset_expr
.X_op
== O_constant
)
4193 /* If this is a reference to a GP relative symbol, we want
4194 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4195 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4196 If we have a base register, we use this
4198 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4199 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4200 If this is not a GP relative symbol, we want
4201 lui $at,<sym> (BFD_RELOC_HI16_S)
4202 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4203 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4204 If there is a base register, we add it to $at after the
4205 lui instruction. If there is a constant, we always use
4207 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4208 || nopic_need_relax (offset_expr
.X_add_symbol
))
4227 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4228 mips_isa
< 3 ? "addu" : "daddu",
4229 "d,v,t", AT
, breg
, GP
);
4235 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4236 coproc
? treg
+ 1 : treg
,
4237 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4238 offset_expr
.X_add_number
+= 4;
4240 /* Set mips_optimize to 2 to avoid inserting an
4242 hold_mips_optimize
= mips_optimize
;
4244 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4245 coproc
? treg
: treg
+ 1,
4246 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4247 mips_optimize
= hold_mips_optimize
;
4249 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4250 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4251 used_at
&& mips_noat
),
4252 offset_expr
.X_add_symbol
, (long) 0,
4255 /* We just generated two relocs. When tc_gen_reloc
4256 handles this case, it will skip the first reloc and
4257 handle the second. The second reloc already has an
4258 extra addend of 4, which we added above. We must
4259 subtract it out, and then subtract another 4 to make
4260 the first reloc come out right. The second reloc
4261 will come out right because we are going to add 4 to
4262 offset_expr when we build its instruction below. */
4263 offset_expr
.X_add_number
-= 8;
4264 offset_expr
.X_op
= O_constant
;
4266 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4271 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4272 mips_isa
< 3 ? "addu" : "daddu",
4273 "d,v,t", AT
, breg
, AT
);
4277 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4278 coproc
? treg
+ 1 : treg
,
4279 (int) BFD_RELOC_LO16
, AT
);
4282 /* FIXME: How do we handle overflow here? */
4283 offset_expr
.X_add_number
+= 4;
4284 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4285 coproc
? treg
: treg
+ 1,
4286 (int) BFD_RELOC_LO16
, AT
);
4288 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4292 /* If this is a reference to an external symbol, we want
4293 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4298 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4300 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4301 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4302 If there is a base register we add it to $at before the
4303 lwc1 instructions. If there is a constant we include it
4304 in the lwc1 instructions. */
4306 expr1
.X_add_number
= offset_expr
.X_add_number
;
4307 offset_expr
.X_add_number
= 0;
4308 if (expr1
.X_add_number
< -0x8000
4309 || expr1
.X_add_number
>= 0x8000 - 4)
4310 as_bad ("PIC code offset overflow (max 16 signed bits)");
4315 frag_grow (24 + off
);
4316 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4317 mips_isa
< 3 ? "lw" : "ld",
4318 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4319 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4322 mips_isa
< 3 ? "addu" : "daddu",
4323 "d,v,t", AT
, breg
, AT
);
4324 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4325 coproc
? treg
+ 1 : treg
,
4326 (int) BFD_RELOC_LO16
, AT
);
4327 expr1
.X_add_number
+= 4;
4329 /* Set mips_optimize to 2 to avoid inserting an undesired
4331 hold_mips_optimize
= mips_optimize
;
4333 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4334 coproc
? treg
: treg
+ 1,
4335 (int) BFD_RELOC_LO16
, AT
);
4336 mips_optimize
= hold_mips_optimize
;
4338 (void) frag_var (rs_machine_dependent
, 0, 0,
4339 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4340 offset_expr
.X_add_symbol
, (long) 0,
4343 else if (mips_pic
== SVR4_PIC
)
4347 /* If this is a reference to an external symbol, we want
4348 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4350 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4355 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4357 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4358 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4359 If there is a base register we add it to $at before the
4360 lwc1 instructions. If there is a constant we include it
4361 in the lwc1 instructions. */
4363 expr1
.X_add_number
= offset_expr
.X_add_number
;
4364 offset_expr
.X_add_number
= 0;
4365 if (expr1
.X_add_number
< -0x8000
4366 || expr1
.X_add_number
>= 0x8000 - 4)
4367 as_bad ("PIC code offset overflow (max 16 signed bits)");
4368 if (reg_needs_delay (GP
))
4377 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4378 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4380 mips_isa
< 3 ? "addu" : "daddu",
4381 "d,v,t", AT
, AT
, GP
);
4382 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4383 mips_isa
< 3 ? "lw" : "ld",
4384 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4385 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4387 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4388 mips_isa
< 3 ? "addu" : "daddu",
4389 "d,v,t", AT
, breg
, AT
);
4390 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4391 coproc
? treg
+ 1 : treg
,
4392 (int) BFD_RELOC_LO16
, AT
);
4393 expr1
.X_add_number
+= 4;
4395 /* Set mips_optimize to 2 to avoid inserting an undesired
4397 hold_mips_optimize
= mips_optimize
;
4399 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4400 coproc
? treg
: treg
+ 1,
4401 (int) BFD_RELOC_LO16
, AT
);
4402 mips_optimize
= hold_mips_optimize
;
4403 expr1
.X_add_number
-= 4;
4405 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4406 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4407 8 + gpdel
+ off
, 1, 0),
4408 offset_expr
.X_add_symbol
, (long) 0,
4412 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4415 macro_build (p
, &icnt
, &offset_expr
,
4416 mips_isa
< 3 ? "lw" : "ld",
4417 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4419 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4423 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4424 mips_isa
< 3 ? "addu" : "daddu",
4425 "d,v,t", AT
, breg
, AT
);
4428 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4429 coproc
? treg
+ 1 : treg
,
4430 (int) BFD_RELOC_LO16
, AT
);
4432 expr1
.X_add_number
+= 4;
4434 /* Set mips_optimize to 2 to avoid inserting an undesired
4436 hold_mips_optimize
= mips_optimize
;
4438 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4439 coproc
? treg
: treg
+ 1,
4440 (int) BFD_RELOC_LO16
, AT
);
4441 mips_optimize
= hold_mips_optimize
;
4443 else if (mips_pic
== EMBEDDED_PIC
)
4445 /* If there is no base register, we use
4446 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4447 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4448 If we have a base register, we use
4450 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4451 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4460 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4461 mips_isa
< 3 ? "addu" : "daddu",
4462 "d,v,t", AT
, breg
, GP
);
4467 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4468 coproc
? treg
+ 1 : treg
,
4469 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4470 offset_expr
.X_add_number
+= 4;
4471 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4472 coproc
? treg
: treg
+ 1,
4473 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4489 assert (mips_isa
< 3);
4490 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4491 (int) BFD_RELOC_LO16
, breg
);
4492 offset_expr
.X_add_number
+= 4;
4493 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4494 (int) BFD_RELOC_LO16
, breg
);
4496 #ifdef LOSING_COMPILER
4502 as_warn ("Macro used $at after \".set noat\"");
4507 struct mips_cl_insn
*ip
;
4509 register int treg
, sreg
, dreg
, breg
;
4524 bfd_reloc_code_real_type r
;
4527 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4528 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4529 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4530 mask
= ip
->insn_mo
->mask
;
4532 expr1
.X_op
= O_constant
;
4533 expr1
.X_op_symbol
= NULL
;
4534 expr1
.X_add_symbol
= NULL
;
4535 expr1
.X_add_number
= 1;
4539 #endif /* LOSING_COMPILER */
4544 macro_build ((char *) NULL
, &icnt
, NULL
,
4545 dbl
? "dmultu" : "multu",
4547 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4553 /* The MIPS assembler some times generates shifts and adds. I'm
4554 not trying to be that fancy. GCC should do this for us
4556 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4557 macro_build ((char *) NULL
, &icnt
, NULL
,
4558 dbl
? "dmult" : "mult",
4560 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4566 mips_emit_delays ();
4568 mips_any_noreorder
= 1;
4569 macro_build ((char *) NULL
, &icnt
, NULL
,
4570 dbl
? "dmult" : "mult",
4572 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4573 macro_build ((char *) NULL
, &icnt
, NULL
,
4574 dbl
? "dsra32" : "sra",
4575 "d,w,<", dreg
, dreg
, 31);
4576 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4578 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4581 expr1
.X_add_number
= 8;
4582 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4583 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4584 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4587 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4593 mips_emit_delays ();
4595 mips_any_noreorder
= 1;
4596 macro_build ((char *) NULL
, &icnt
, NULL
,
4597 dbl
? "dmultu" : "multu",
4599 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4600 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4602 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4605 expr1
.X_add_number
= 8;
4606 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4607 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4608 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4614 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4615 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4616 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4618 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4622 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4623 (int) (imm_expr
.X_add_number
& 0x1f));
4624 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4625 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4626 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4630 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4631 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4632 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4634 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4638 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4639 (int) (imm_expr
.X_add_number
& 0x1f));
4640 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4641 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4642 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4646 assert (mips_isa
< 2);
4647 /* Even on a big endian machine $fn comes before $fn+1. We have
4648 to adjust when storing to memory. */
4649 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4650 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4651 (int) BFD_RELOC_LO16
, breg
);
4652 offset_expr
.X_add_number
+= 4;
4653 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4654 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4655 (int) BFD_RELOC_LO16
, breg
);
4660 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4661 treg
, (int) BFD_RELOC_LO16
);
4663 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4664 sreg
, (int) BFD_RELOC_LO16
);
4667 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4669 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4670 dreg
, (int) BFD_RELOC_LO16
);
4675 if (imm_expr
.X_add_number
== 0)
4677 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4678 sreg
, (int) BFD_RELOC_LO16
);
4683 as_warn ("Instruction %s: result is always false",
4685 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4688 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4690 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4691 sreg
, (int) BFD_RELOC_LO16
);
4694 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4696 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4697 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4698 mips_isa
< 3 ? "addiu" : "daddiu",
4699 "t,r,j", dreg
, sreg
,
4700 (int) BFD_RELOC_LO16
);
4705 load_register (&icnt
, AT
, &imm_expr
, 0);
4706 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4710 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4711 (int) BFD_RELOC_LO16
);
4716 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4722 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4723 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4724 (int) BFD_RELOC_LO16
);
4727 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4729 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4731 macro_build ((char *) NULL
, &icnt
, &expr1
,
4732 mask
== M_SGE_I
? "slti" : "sltiu",
4733 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4738 load_register (&icnt
, AT
, &imm_expr
, 0);
4739 macro_build ((char *) NULL
, &icnt
, NULL
,
4740 mask
== M_SGE_I
? "slt" : "sltu",
4741 "d,v,t", dreg
, sreg
, AT
);
4744 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4745 (int) BFD_RELOC_LO16
);
4750 case M_SGT
: /* sreg > treg <==> treg < sreg */
4756 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4759 case M_SGT_I
: /* sreg > I <==> I < sreg */
4765 load_register (&icnt
, AT
, &imm_expr
, 0);
4766 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4769 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4775 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4776 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4777 (int) BFD_RELOC_LO16
);
4780 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4786 load_register (&icnt
, AT
, &imm_expr
, 0);
4787 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4788 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4789 (int) BFD_RELOC_LO16
);
4793 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4795 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4796 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4799 load_register (&icnt
, AT
, &imm_expr
, 0);
4800 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4804 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4806 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4807 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4810 load_register (&icnt
, AT
, &imm_expr
, 0);
4811 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4817 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4820 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4824 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4826 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4832 if (imm_expr
.X_add_number
== 0)
4834 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4840 as_warn ("Instruction %s: result is always true",
4842 macro_build ((char *) NULL
, &icnt
, &expr1
,
4843 mips_isa
< 3 ? "addiu" : "daddiu",
4844 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4847 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4849 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4850 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4853 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4855 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4856 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4857 mips_isa
< 3 ? "addiu" : "daddiu",
4858 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4863 load_register (&icnt
, AT
, &imm_expr
, 0);
4864 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4868 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4876 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4878 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4879 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4880 dbl
? "daddi" : "addi",
4881 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4884 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4885 macro_build ((char *) NULL
, &icnt
, NULL
,
4886 dbl
? "dsub" : "sub",
4887 "d,v,t", dreg
, sreg
, AT
);
4893 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4895 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4896 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4897 dbl
? "daddiu" : "addiu",
4898 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4901 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4902 macro_build ((char *) NULL
, &icnt
, NULL
,
4903 dbl
? "dsubu" : "subu",
4904 "d,v,t", dreg
, sreg
, AT
);
4925 load_register (&icnt
, AT
, &imm_expr
, 0);
4926 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4931 assert (mips_isa
< 2);
4932 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4933 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4936 * Is the double cfc1 instruction a bug in the mips assembler;
4937 * or is there a reason for it?
4939 mips_emit_delays ();
4941 mips_any_noreorder
= 1;
4942 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4943 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4944 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4945 expr1
.X_add_number
= 3;
4946 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4947 (int) BFD_RELOC_LO16
);
4948 expr1
.X_add_number
= 2;
4949 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4950 (int) BFD_RELOC_LO16
);
4951 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4952 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4953 macro_build ((char *) NULL
, &icnt
, NULL
,
4954 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4955 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4956 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4966 if (offset_expr
.X_add_number
>= 0x7fff)
4967 as_bad ("operand overflow");
4968 /* avoid load delay */
4969 if (byte_order
== LITTLE_ENDIAN
)
4970 offset_expr
.X_add_number
+= 1;
4971 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4972 (int) BFD_RELOC_LO16
, breg
);
4973 if (byte_order
== LITTLE_ENDIAN
)
4974 offset_expr
.X_add_number
-= 1;
4976 offset_expr
.X_add_number
+= 1;
4977 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4978 (int) BFD_RELOC_LO16
, breg
);
4979 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4980 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4993 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4994 as_bad ("operand overflow");
4995 if (byte_order
== LITTLE_ENDIAN
)
4996 offset_expr
.X_add_number
+= off
;
4997 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4998 (int) BFD_RELOC_LO16
, breg
);
4999 if (byte_order
== LITTLE_ENDIAN
)
5000 offset_expr
.X_add_number
-= off
;
5002 offset_expr
.X_add_number
+= off
;
5003 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5004 (int) BFD_RELOC_LO16
, breg
);
5017 load_address (&icnt
, AT
, &offset_expr
);
5019 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5020 mips_isa
< 3 ? "addu" : "daddu",
5021 "d,v,t", AT
, AT
, breg
);
5022 if (byte_order
== LITTLE_ENDIAN
)
5023 expr1
.X_add_number
= off
;
5025 expr1
.X_add_number
= 0;
5026 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5027 (int) BFD_RELOC_LO16
, AT
);
5028 if (byte_order
== LITTLE_ENDIAN
)
5029 expr1
.X_add_number
= 0;
5031 expr1
.X_add_number
= off
;
5032 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5033 (int) BFD_RELOC_LO16
, AT
);
5038 load_address (&icnt
, AT
, &offset_expr
);
5040 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5041 mips_isa
< 3 ? "addu" : "daddu",
5042 "d,v,t", AT
, AT
, breg
);
5043 if (byte_order
== BIG_ENDIAN
)
5044 expr1
.X_add_number
= 0;
5045 macro_build ((char *) NULL
, &icnt
, &expr1
,
5046 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5047 (int) BFD_RELOC_LO16
, AT
);
5048 if (byte_order
== BIG_ENDIAN
)
5049 expr1
.X_add_number
= 1;
5051 expr1
.X_add_number
= 0;
5052 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5053 (int) BFD_RELOC_LO16
, AT
);
5054 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5056 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5061 if (offset_expr
.X_add_number
>= 0x7fff)
5062 as_bad ("operand overflow");
5063 if (byte_order
== BIG_ENDIAN
)
5064 offset_expr
.X_add_number
+= 1;
5065 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5066 (int) BFD_RELOC_LO16
, breg
);
5067 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5068 if (byte_order
== BIG_ENDIAN
)
5069 offset_expr
.X_add_number
-= 1;
5071 offset_expr
.X_add_number
+= 1;
5072 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5073 (int) BFD_RELOC_LO16
, breg
);
5086 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5087 as_bad ("operand overflow");
5088 if (byte_order
== LITTLE_ENDIAN
)
5089 offset_expr
.X_add_number
+= off
;
5090 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5091 (int) BFD_RELOC_LO16
, breg
);
5092 if (byte_order
== LITTLE_ENDIAN
)
5093 offset_expr
.X_add_number
-= off
;
5095 offset_expr
.X_add_number
+= off
;
5096 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5097 (int) BFD_RELOC_LO16
, breg
);
5110 load_address (&icnt
, AT
, &offset_expr
);
5112 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5113 mips_isa
< 3 ? "addu" : "daddu",
5114 "d,v,t", AT
, AT
, breg
);
5115 if (byte_order
== LITTLE_ENDIAN
)
5116 expr1
.X_add_number
= off
;
5118 expr1
.X_add_number
= 0;
5119 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5120 (int) BFD_RELOC_LO16
, AT
);
5121 if (byte_order
== LITTLE_ENDIAN
)
5122 expr1
.X_add_number
= 0;
5124 expr1
.X_add_number
= off
;
5125 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5126 (int) BFD_RELOC_LO16
, AT
);
5130 load_address (&icnt
, AT
, &offset_expr
);
5132 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5133 mips_isa
< 3 ? "addu" : "daddu",
5134 "d,v,t", AT
, AT
, breg
);
5135 if (byte_order
== LITTLE_ENDIAN
)
5136 expr1
.X_add_number
= 0;
5137 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5138 (int) BFD_RELOC_LO16
, AT
);
5139 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5141 if (byte_order
== LITTLE_ENDIAN
)
5142 expr1
.X_add_number
= 1;
5144 expr1
.X_add_number
= 0;
5145 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5146 (int) BFD_RELOC_LO16
, AT
);
5147 if (byte_order
== LITTLE_ENDIAN
)
5148 expr1
.X_add_number
= 0;
5150 expr1
.X_add_number
= 1;
5151 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5152 (int) BFD_RELOC_LO16
, AT
);
5153 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5155 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5160 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5164 as_warn ("Macro used $at after \".set noat\"");
5167 /* This routine assembles an instruction into its binary format. As a
5168 side effect, it sets one of the global variables imm_reloc or
5169 offset_reloc to the type of relocation to do if one of the operands
5170 is an address expression. */
5175 struct mips_cl_insn
*ip
;
5180 struct mips_opcode
*insn
;
5183 unsigned int lastregno
= 0;
5188 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5200 as_fatal ("Unknown opcode: `%s'", str
);
5202 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5204 insn_error
= "unrecognized opcode";
5212 assert (strcmp (insn
->name
, str
) == 0);
5214 if (insn
->pinfo
== INSN_MACRO
)
5215 insn_isa
= insn
->match
;
5216 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5218 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5220 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5225 if (insn_isa
> mips_isa
5226 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5228 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5230 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5233 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5234 && strcmp (insn
->name
, insn
[1].name
) == 0)
5239 if (insn_isa
<= mips_isa
)
5240 insn_error
= "opcode not supported on this processor";
5243 static char buf
[100];
5245 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
5252 ip
->insn_opcode
= insn
->match
;
5253 for (args
= insn
->args
;; ++args
)
5259 case '\0': /* end of args */
5272 ip
->insn_opcode
|= lastregno
<< 21;
5277 ip
->insn_opcode
|= lastregno
<< 16;
5281 ip
->insn_opcode
|= lastregno
<< 11;
5287 /* handle optional base register.
5288 Either the base register is omitted or
5289 we must have a left paren. */
5290 /* this is dependent on the next operand specifier
5291 is a 'b' for base register */
5292 assert (args
[1] == 'b');
5296 case ')': /* these must match exactly */
5301 case '<': /* must be at least one digit */
5303 * According to the manual, if the shift amount is greater
5304 * than 31 or less than 0 the the shift amount should be
5305 * mod 32. In reality the mips assembler issues an error.
5306 * We issue a warning and mask out all but the low 5 bits.
5308 my_getExpression (&imm_expr
, s
);
5309 check_absolute_expr (ip
, &imm_expr
);
5310 if ((unsigned long) imm_expr
.X_add_number
> 31)
5312 as_warn ("Improper shift amount (%ld)",
5313 (long) imm_expr
.X_add_number
);
5314 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5316 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5317 imm_expr
.X_op
= O_absent
;
5321 case '>': /* shift amount minus 32 */
5322 my_getExpression (&imm_expr
, s
);
5323 check_absolute_expr (ip
, &imm_expr
);
5324 if ((unsigned long) imm_expr
.X_add_number
< 32
5325 || (unsigned long) imm_expr
.X_add_number
> 63)
5327 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5328 imm_expr
.X_op
= O_absent
;
5332 case 'k': /* cache code */
5333 case 'h': /* prefx code */
5334 my_getExpression (&imm_expr
, s
);
5335 check_absolute_expr (ip
, &imm_expr
);
5336 if ((unsigned long) imm_expr
.X_add_number
> 31)
5338 as_warn ("Invalid value for `%s' (%lu)",
5340 (unsigned long) imm_expr
.X_add_number
);
5341 imm_expr
.X_add_number
&= 0x1f;
5344 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5346 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5347 imm_expr
.X_op
= O_absent
;
5351 case 'c': /* break code */
5352 my_getExpression (&imm_expr
, s
);
5353 check_absolute_expr (ip
, &imm_expr
);
5354 if ((unsigned) imm_expr
.X_add_number
> 1023)
5355 as_warn ("Illegal break code (%ld)",
5356 (long) imm_expr
.X_add_number
);
5357 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5358 imm_expr
.X_op
= O_absent
;
5362 case 'B': /* syscall code */
5363 my_getExpression (&imm_expr
, s
);
5364 check_absolute_expr (ip
, &imm_expr
);
5365 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5366 as_warn ("Illegal syscall code (%ld)",
5367 (long) imm_expr
.X_add_number
);
5368 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5369 imm_expr
.X_op
= O_absent
;
5373 case 'C': /* Coprocessor code */
5374 my_getExpression (&imm_expr
, s
);
5375 check_absolute_expr (ip
, &imm_expr
);
5376 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5378 as_warn ("Coproccesor code > 25 bits (%ld)",
5379 (long) imm_expr
.X_add_number
);
5380 imm_expr
.X_add_number
&= ((1<<25) - 1);
5382 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5383 imm_expr
.X_op
= O_absent
;
5387 case 'b': /* base register */
5388 case 'd': /* destination register */
5389 case 's': /* source register */
5390 case 't': /* target register */
5391 case 'r': /* both target and source */
5392 case 'v': /* both dest and source */
5393 case 'w': /* both dest and target */
5394 case 'E': /* coprocessor target register */
5395 case 'G': /* coprocessor destination register */
5396 case 'x': /* ignore register name */
5397 case 'z': /* must be zero register */
5411 while (isdigit (*s
));
5413 as_bad ("Invalid register number (%d)", regno
);
5415 else if (*args
== 'E' || *args
== 'G')
5419 if (s
[1] == 'f' && s
[2] == 'p')
5424 else if (s
[1] == 's' && s
[2] == 'p')
5429 else if (s
[1] == 'g' && s
[2] == 'p')
5434 else if (s
[1] == 'a' && s
[2] == 't')
5439 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5444 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5456 as_warn ("Used $at without \".set noat\"");
5462 if (c
== 'r' || c
== 'v' || c
== 'w')
5469 /* 'z' only matches $0. */
5470 if (c
== 'z' && regno
!= 0)
5478 ip
->insn_opcode
|= regno
<< 21;
5482 ip
->insn_opcode
|= regno
<< 11;
5487 ip
->insn_opcode
|= regno
<< 16;
5490 /* This case exists because on the r3000 trunc
5491 expands into a macro which requires a gp
5492 register. On the r6000 or r4000 it is
5493 assembled into a single instruction which
5494 ignores the register. Thus the insn version
5495 is MIPS_ISA2 and uses 'x', and the macro
5496 version is MIPS_ISA1 and uses 't'. */
5499 /* This case is for the div instruction, which
5500 acts differently if the destination argument
5501 is $0. This only matches $0, and is checked
5502 outside the switch. */
5513 ip
->insn_opcode
|= lastregno
<< 21;
5516 ip
->insn_opcode
|= lastregno
<< 16;
5521 case 'D': /* floating point destination register */
5522 case 'S': /* floating point source register */
5523 case 'T': /* floating point target register */
5524 case 'R': /* floating point source register */
5528 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5538 while (isdigit (*s
));
5541 as_bad ("Invalid float register number (%d)", regno
);
5543 if ((regno
& 1) != 0
5545 && ! (strcmp (str
, "mtc1") == 0 ||
5546 strcmp (str
, "mfc1") == 0 ||
5547 strcmp (str
, "lwc1") == 0 ||
5548 strcmp (str
, "swc1") == 0))
5549 as_warn ("Float register should be even, was %d",
5557 if (c
== 'V' || c
== 'W')
5567 ip
->insn_opcode
|= regno
<< 6;
5571 ip
->insn_opcode
|= regno
<< 11;
5575 ip
->insn_opcode
|= regno
<< 16;
5578 ip
->insn_opcode
|= regno
<< 21;
5587 ip
->insn_opcode
|= lastregno
<< 11;
5590 ip
->insn_opcode
|= lastregno
<< 16;
5596 my_getExpression (&imm_expr
, s
);
5597 if (imm_expr
.X_op
!= O_big
5598 && imm_expr
.X_op
!= O_constant
)
5599 insn_error
= "absolute expression required";
5604 my_getExpression (&offset_expr
, s
);
5605 imm_reloc
= BFD_RELOC_32
;
5617 unsigned char temp
[8];
5619 unsigned int length
;
5624 /* These only appear as the last operand in an
5625 instruction, and every instruction that accepts
5626 them in any variant accepts them in all variants.
5627 This means we don't have to worry about backing out
5628 any changes if the instruction does not match.
5630 The difference between them is the size of the
5631 floating point constant and where it goes. For 'F'
5632 and 'L' the constant is 64 bits; for 'f' and 'l' it
5633 is 32 bits. Where the constant is placed is based
5634 on how the MIPS assembler does things:
5637 f -- immediate value
5640 The .lit4 and .lit8 sections are only used if
5641 permitted by the -G argument.
5643 When generating embedded PIC code, we use the
5644 .lit8 section but not the .lit4 section (we can do
5645 .lit4 inline easily; we need to put .lit8
5646 somewhere in the data segment, and using .lit8
5647 permits the linker to eventually combine identical
5650 f64
= *args
== 'F' || *args
== 'L';
5652 save_in
= input_line_pointer
;
5653 input_line_pointer
= s
;
5654 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5656 s
= input_line_pointer
;
5657 input_line_pointer
= save_in
;
5658 if (err
!= NULL
&& *err
!= '\0')
5660 as_bad ("Bad floating point constant: %s", err
);
5661 memset (temp
, '\0', sizeof temp
);
5662 length
= f64
? 8 : 4;
5665 assert (length
== (f64
? 8 : 4));
5669 && (! USE_GLOBAL_POINTER_OPT
5670 || mips_pic
== EMBEDDED_PIC
5671 || g_switch_value
< 4)
5674 imm_expr
.X_op
= O_constant
;
5675 if (byte_order
== LITTLE_ENDIAN
)
5676 imm_expr
.X_add_number
=
5677 (((((((int) temp
[3] << 8)
5682 imm_expr
.X_add_number
=
5683 (((((((int) temp
[0] << 8)
5690 const char *newname
;
5693 /* Switch to the right section. */
5695 subseg
= now_subseg
;
5698 default: /* unused default case avoids warnings. */
5700 newname
= RDATA_SECTION_NAME
;
5701 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5705 newname
= RDATA_SECTION_NAME
;
5708 assert (!USE_GLOBAL_POINTER_OPT
5709 || g_switch_value
>= 4);
5713 new_seg
= subseg_new (newname
, (subsegT
) 0);
5714 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5715 bfd_set_section_flags (stdoutput
, new_seg
,
5720 frag_align (*args
== 'l' ? 2 : 3, 0);
5721 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5722 record_alignment (new_seg
, 4);
5724 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5726 as_bad ("Can't use floating point insn in this section");
5728 /* Set the argument to the current address in the
5730 offset_expr
.X_op
= O_symbol
;
5731 offset_expr
.X_add_symbol
=
5732 symbol_new ("L0\001", now_seg
,
5733 (valueT
) frag_now_fix (), frag_now
);
5734 offset_expr
.X_add_number
= 0;
5736 /* Put the floating point number into the section. */
5737 p
= frag_more ((int) length
);
5738 memcpy (p
, temp
, length
);
5740 /* Switch back to the original section. */
5741 subseg_set (seg
, subseg
);
5746 case 'i': /* 16 bit unsigned immediate */
5747 case 'j': /* 16 bit signed immediate */
5748 imm_reloc
= BFD_RELOC_LO16
;
5749 c
= my_getSmallExpression (&imm_expr
, s
);
5754 if (imm_expr
.X_op
== O_constant
)
5755 imm_expr
.X_add_number
=
5756 (imm_expr
.X_add_number
>> 16) & 0xffff;
5759 imm_reloc
= BFD_RELOC_HI16_S
;
5760 imm_unmatched_hi
= true;
5763 imm_reloc
= BFD_RELOC_HI16
;
5768 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5769 || ((imm_expr
.X_add_number
< 0
5770 || imm_expr
.X_add_number
>= 0x10000)
5771 && imm_expr
.X_op
== O_constant
))
5773 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5774 !strcmp (insn
->name
, insn
[1].name
))
5776 if (imm_expr
.X_op
!= O_constant
5777 && imm_expr
.X_op
!= O_big
)
5778 insn_error
= "absolute expression required";
5780 as_bad ("16 bit expression not in range 0..65535");
5788 /* The upper bound should be 0x8000, but
5789 unfortunately the MIPS assembler accepts numbers
5790 from 0x8000 to 0xffff and sign extends them, and
5791 we want to be compatible. We only permit this
5792 extended range for an instruction which does not
5793 provide any further alternates, since those
5794 alternates may handle other cases. People should
5795 use the numbers they mean, rather than relying on
5796 a mysterious sign extension. */
5797 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5798 strcmp (insn
->name
, insn
[1].name
) == 0);
5803 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5804 || ((imm_expr
.X_add_number
< -0x8000
5805 || imm_expr
.X_add_number
>= max
)
5806 && imm_expr
.X_op
== O_constant
)
5808 && imm_expr
.X_add_number
< 0
5810 && imm_expr
.X_unsigned
5811 && sizeof (imm_expr
.X_add_number
) <= 4))
5815 if (imm_expr
.X_op
!= O_constant
5816 && imm_expr
.X_op
!= O_big
)
5817 insn_error
= "absolute expression required";
5819 as_bad ("16 bit expression not in range -32768..32767");
5825 case 'o': /* 16 bit offset */
5826 c
= my_getSmallExpression (&offset_expr
, s
);
5828 /* If this value won't fit into a 16 bit offset, then go
5829 find a macro that will generate the 32 bit offset
5830 code pattern. As a special hack, we accept the
5831 difference of two local symbols as a constant. This
5832 is required to suppose embedded PIC switches, which
5833 use an instruction which looks like
5834 lw $4,$L12-$LS12($4)
5835 The problem with handling this in a more general
5836 fashion is that the macro function doesn't expect to
5837 see anything which can be handled in a single
5838 constant instruction. */
5840 && (offset_expr
.X_op
!= O_constant
5841 || offset_expr
.X_add_number
>= 0x8000
5842 || offset_expr
.X_add_number
< -0x8000)
5843 && (mips_pic
!= EMBEDDED_PIC
5844 || offset_expr
.X_op
!= O_subtract
5845 || now_seg
!= text_section
5846 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5850 offset_reloc
= BFD_RELOC_LO16
;
5851 if (c
== 'h' || c
== 'H')
5853 assert (offset_expr
.X_op
== O_constant
);
5854 offset_expr
.X_add_number
=
5855 (offset_expr
.X_add_number
>> 16) & 0xffff;
5860 case 'p': /* pc relative offset */
5861 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5862 my_getExpression (&offset_expr
, s
);
5866 case 'u': /* upper 16 bits */
5867 c
= my_getSmallExpression (&imm_expr
, s
);
5868 if (imm_expr
.X_op
== O_constant
5869 && (imm_expr
.X_add_number
< 0
5870 || imm_expr
.X_add_number
>= 0x10000))
5871 as_bad ("lui expression not in range 0..65535");
5872 imm_reloc
= BFD_RELOC_LO16
;
5877 if (imm_expr
.X_op
== O_constant
)
5878 imm_expr
.X_add_number
=
5879 (imm_expr
.X_add_number
>> 16) & 0xffff;
5882 imm_reloc
= BFD_RELOC_HI16_S
;
5883 imm_unmatched_hi
= true;
5886 imm_reloc
= BFD_RELOC_HI16
;
5892 case 'a': /* 26 bit address */
5893 my_getExpression (&offset_expr
, s
);
5895 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5898 case 'N': /* 3 bit branch condition code */
5899 case 'M': /* 3 bit compare condition code */
5900 if (strncmp (s
, "$fcc", 4) != 0)
5910 while (isdigit (*s
));
5912 as_bad ("invalid condition code register $fcc%d", regno
);
5914 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
5916 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
5920 fprintf (stderr
, "bad char = '%c'\n", *args
);
5925 /* Args don't match. */
5926 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5927 !strcmp (insn
->name
, insn
[1].name
))
5933 insn_error
= "illegal operands";
5942 my_getSmallExpression (ep
, str
)
5953 ((str
[1] == 'h' && str
[2] == 'i')
5954 || (str
[1] == 'H' && str
[2] == 'I')
5955 || (str
[1] == 'l' && str
[2] == 'o'))
5967 * A small expression may be followed by a base register.
5968 * Scan to the end of this operand, and then back over a possible
5969 * base register. Then scan the small expression up to that
5970 * point. (Based on code in sparc.c...)
5972 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5974 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5976 if (isdigit (sp
[-2]))
5978 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5980 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5986 else if (sp
- 5 >= str
5989 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5990 || (sp
[-3] == 's' && sp
[-2] == 'p')
5991 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5992 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5998 /* no expression means zero offset */
6001 /* %xx(reg) is an error */
6002 ep
->X_op
= O_absent
;
6007 ep
->X_op
= O_constant
;
6010 ep
->X_add_symbol
= NULL
;
6011 ep
->X_op_symbol
= NULL
;
6012 ep
->X_add_number
= 0;
6017 my_getExpression (ep
, str
);
6024 my_getExpression (ep
, str
);
6025 return c
; /* => %hi or %lo encountered */
6029 my_getExpression (ep
, str
)
6035 save_in
= input_line_pointer
;
6036 input_line_pointer
= str
;
6038 expr_end
= input_line_pointer
;
6039 input_line_pointer
= save_in
;
6042 /* Turn a string in input_line_pointer into a floating point constant
6043 of type type, and store the appropriate bytes in *litP. The number
6044 of LITTLENUMS emitted is stored in *sizeP . An error message is
6045 returned, or NULL on OK. */
6048 md_atof (type
, litP
, sizeP
)
6054 LITTLENUM_TYPE words
[4];
6070 return "bad call to md_atof";
6073 t
= atof_ieee (input_line_pointer
, type
, words
);
6075 input_line_pointer
= t
;
6079 if (byte_order
== LITTLE_ENDIAN
)
6081 for (i
= prec
- 1; i
>= 0; i
--)
6083 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6089 for (i
= 0; i
< prec
; i
++)
6091 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
6100 md_number_to_chars (buf
, val
, n
)
6108 number_to_chars_littleendian (buf
, val
, n
);
6112 number_to_chars_bigendian (buf
, val
, n
);
6120 CONST
char *md_shortopts
= "O::g::G:";
6122 struct option md_longopts
[] = {
6123 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
6124 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
6125 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
6126 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
6127 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
6128 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
6129 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
6130 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
6131 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
6132 #define OPTION_MCPU (OPTION_MD_BASE + 5)
6133 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
6134 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
6135 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
6136 #define OPTION_TRAP (OPTION_MD_BASE + 9)
6137 {"trap", no_argument
, NULL
, OPTION_TRAP
},
6138 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
6139 #define OPTION_BREAK (OPTION_MD_BASE + 10)
6140 {"break", no_argument
, NULL
, OPTION_BREAK
},
6141 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
6142 #define OPTION_EB (OPTION_MD_BASE + 11)
6143 {"EB", no_argument
, NULL
, OPTION_EB
},
6144 #define OPTION_EL (OPTION_MD_BASE + 12)
6145 {"EL", no_argument
, NULL
, OPTION_EL
},
6146 #define OPTION_M4650 (OPTION_MD_BASE + 13)
6147 {"m4650", no_argument
, NULL
, OPTION_M4650
},
6148 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
6149 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
6150 #define OPTION_M4010 (OPTION_MD_BASE + 15)
6151 {"m4010", no_argument
, NULL
, OPTION_M4010
},
6152 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
6153 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
6154 #define OPTION_M4100 (OPTION_MD_BASE + 17)
6155 {"m4100", no_argument
, NULL
, OPTION_M4100
},
6156 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6157 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6159 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6160 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6161 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6162 #define OPTION_32 (OPTION_MD_BASE + 20)
6163 #define OPTION_64 (OPTION_MD_BASE + 21)
6165 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6166 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6167 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6168 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6169 {"32", no_argument
, NULL
, OPTION_32
},
6170 {"64", no_argument
, NULL
, OPTION_64
},
6173 {NULL
, no_argument
, NULL
, 0}
6175 size_t md_longopts_size
= sizeof(md_longopts
);
6178 md_parse_option (c
, arg
)
6193 target_big_endian
= 1;
6197 target_big_endian
= 0;
6201 if (arg
&& arg
[1] == '0')
6211 mips_debug
= atoi (arg
);
6212 /* When the MIPS assembler sees -g or -g2, it does not do
6213 optimizations which limit full symbolic debugging. We take
6214 that to be equivalent to -O0. */
6215 if (mips_debug
== 2)
6247 /* Identify the processor type */
6249 if (strcmp (p
, "default") == 0
6250 || strcmp (p
, "DEFAULT") == 0)
6256 /* We need to cope with the various "vr" prefixes for the 4300
6258 if (*p
== 'v' || *p
== 'V')
6264 if (*p
== 'r' || *p
== 'R')
6271 if (strcmp (p
, "10000") == 0
6272 || strcmp (p
, "10k") == 0
6273 || strcmp (p
, "10K") == 0)
6278 if (strcmp (p
, "2000") == 0
6279 || strcmp (p
, "2k") == 0
6280 || strcmp (p
, "2K") == 0)
6285 if (strcmp (p
, "3000") == 0
6286 || strcmp (p
, "3k") == 0
6287 || strcmp (p
, "3K") == 0)
6292 if (strcmp (p
, "4000") == 0
6293 || strcmp (p
, "4k") == 0
6294 || strcmp (p
, "4K") == 0)
6296 else if (strcmp (p
, "4100") == 0)
6302 else if (strcmp (p
, "4300") == 0)
6304 else if (strcmp (p
, "4400") == 0)
6306 else if (strcmp (p
, "4600") == 0)
6308 else if (strcmp (p
, "4650") == 0)
6314 else if (strcmp (p
, "4010") == 0)
6323 if (strcmp (p
, "5000") == 0
6324 || strcmp (p
, "5k") == 0
6325 || strcmp (p
, "5K") == 0)
6330 if (strcmp (p
, "6000") == 0
6331 || strcmp (p
, "6k") == 0
6332 || strcmp (p
, "6K") == 0)
6337 if (strcmp (p
, "8000") == 0
6338 || strcmp (p
, "8k") == 0
6339 || strcmp (p
, "8K") == 0)
6344 if (strcmp (p
, "orion") == 0)
6349 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
6351 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6357 as_bad ("invalid architecture -mcpu=%s", arg
);
6368 case OPTION_NO_M4650
:
6376 case OPTION_NO_M4010
:
6384 case OPTION_NO_M4100
:
6388 case OPTION_MEMBEDDED_PIC
:
6389 mips_pic
= EMBEDDED_PIC
;
6390 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6392 as_bad ("-G may not be used with embedded PIC code");
6395 g_switch_value
= 0x7fffffff;
6398 /* When generating ELF code, we permit -KPIC and -call_shared to
6399 select SVR4_PIC, and -non_shared to select no PIC. This is
6400 intended to be compatible with Irix 5. */
6401 case OPTION_CALL_SHARED
:
6402 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6404 as_bad ("-call_shared is supported only for ELF format");
6407 mips_pic
= SVR4_PIC
;
6408 if (g_switch_seen
&& g_switch_value
!= 0)
6410 as_bad ("-G may not be used with SVR4 PIC code");
6416 case OPTION_NON_SHARED
:
6417 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6419 as_bad ("-non_shared is supported only for ELF format");
6425 /* The -xgot option tells the assembler to use 32 offsets when
6426 accessing the got in SVR4_PIC mode. It is for Irix
6433 if (! USE_GLOBAL_POINTER_OPT
)
6435 as_bad ("-G is not supported for this configuration");
6438 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6440 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6444 g_switch_value
= atoi (arg
);
6448 /* The -32 and -64 options tell the assembler to output the 32
6449 bit or the 64 bit MIPS ELF format. */
6456 const char **list
, **l
;
6458 list
= bfd_target_list ();
6459 for (l
= list
; *l
!= NULL
; l
++)
6460 if (strcmp (*l
, "elf64-bigmips") == 0
6461 || strcmp (*l
, "elf64-littlemips") == 0)
6464 as_fatal ("No compiled in support for 64 bit object file format");
6478 md_show_usage (stream
)
6483 -membedded-pic generate embedded position independent code\n\
6484 -EB generate big endian output\n\
6485 -EL generate little endian output\n\
6486 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6487 -G NUM allow referencing objects up to NUM bytes\n\
6488 implicitly with the gp register [default 8]\n");
6490 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6491 -mips2, -mcpu=r6000 generate code for r6000\n\
6492 -mips3, -mcpu=r4000 generate code for r4000\n\
6493 -mips4, -mcpu=r8000 generate code for r8000\n\
6494 -mcpu=vr4300 generate code for vr4300\n\
6495 -mcpu=vr4100 generate code for vr4100\n\
6496 -m4650 permit R4650 instructions\n\
6497 -no-m4650 do not permit R4650 instructions\n\
6498 -m4010 permit R4010 instructions\n\
6499 -no-m4010 do not permit R4010 instructions\n\
6500 -m4100 permit VR4100 instructions\n\
6501 -no-m4100 do not permit VR4100 instructions\n");
6503 -O0 remove unneeded NOPs, do not swap branches\n\
6504 -O remove unneeded NOPs and swap branches\n\
6505 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6506 --break, --no-trap break exception on div by 0 and mult overflow\n");
6509 -KPIC, -call_shared generate SVR4 position independent code\n\
6510 -non_shared do not generate position independent code\n\
6511 -xgot assume a 32 bit GOT\n\
6512 -32 create 32 bit object file (default)\n\
6513 -64 create 64 bit object file\n");
6518 mips_init_after_args ()
6520 if (target_big_endian
)
6521 byte_order
= BIG_ENDIAN
;
6523 byte_order
= LITTLE_ENDIAN
;
6527 md_pcrel_from (fixP
)
6530 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6531 && fixP
->fx_addsy
!= (symbolS
*) NULL
6532 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6534 /* This makes a branch to an undefined symbol be a branch to the
6535 current location. */
6539 /* return the address of the delay slot */
6540 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6543 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6544 reloc for a cons. We could use the definition there, except that
6545 we want to handle 64 bit relocs specially. */
6548 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6551 unsigned int nbytes
;
6554 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6556 if (nbytes
== 8 && ! mips_64
)
6558 if (byte_order
== BIG_ENDIAN
)
6563 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6564 as_bad ("Unsupported reloc size %d", nbytes
);
6566 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6569 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6572 /* Sort any unmatched HI16_S relocs so that they immediately precede
6573 the corresponding LO reloc. This is called before md_apply_fix and
6574 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6575 explicit use of the %hi modifier. */
6580 struct mips_hi_fixup
*l
;
6582 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6584 segment_info_type
*seginfo
;
6587 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6589 /* Check quickly whether the next fixup happens to be a matching
6591 if (l
->fixp
->fx_next
!= NULL
6592 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6593 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6594 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6597 /* Look through the fixups for this segment for a matching %lo.
6598 When we find one, move the %hi just in front of it. We do
6599 this in two passes. In the first pass, we try to find a
6600 unique %lo. In the second pass, we permit multiple %hi
6601 relocs for a single %lo (this is a GNU extension). */
6602 seginfo
= seg_info (l
->seg
);
6603 for (pass
= 0; pass
< 2; pass
++)
6608 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6610 /* Check whether this is a %lo fixup which matches l->fixp. */
6611 if (f
->fx_r_type
== BFD_RELOC_LO16
6612 && f
->fx_addsy
== l
->fixp
->fx_addsy
6613 && f
->fx_offset
== l
->fixp
->fx_offset
6616 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6617 || prev
->fx_addsy
!= f
->fx_addsy
6618 || prev
->fx_offset
!= f
->fx_offset
))
6622 /* Move l->fixp before f. */
6623 for (pf
= &seginfo
->fix_root
;
6625 pf
= &(*pf
)->fx_next
)
6626 assert (*pf
!= NULL
);
6628 *pf
= l
->fixp
->fx_next
;
6630 l
->fixp
->fx_next
= f
;
6632 seginfo
->fix_root
= l
->fixp
;
6634 prev
->fx_next
= l
->fixp
;
6646 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6647 "Unmatched %%hi reloc");
6652 /* When generating embedded PIC code we need to use a special
6653 relocation to represent the difference of two symbols in the .text
6654 section (switch tables use a difference of this sort). See
6655 include/coff/mips.h for details. This macro checks whether this
6656 fixup requires the special reloc. */
6657 #define SWITCH_TABLE(fixp) \
6658 ((fixp)->fx_r_type == BFD_RELOC_32 \
6659 && (fixp)->fx_addsy != NULL \
6660 && (fixp)->fx_subsy != NULL \
6661 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6662 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6664 /* When generating embedded PIC code we must keep all PC relative
6665 relocations, in case the linker has to relax a call. We also need
6666 to keep relocations for switch table entries. */
6670 mips_force_relocation (fixp
)
6673 return (mips_pic
== EMBEDDED_PIC
6675 || SWITCH_TABLE (fixp
)
6676 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6677 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6680 /* Apply a fixup to the object file. */
6683 md_apply_fix (fixP
, valueP
)
6690 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6693 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6695 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6698 switch (fixP
->fx_r_type
)
6700 case BFD_RELOC_MIPS_JMP
:
6701 case BFD_RELOC_HI16
:
6702 case BFD_RELOC_HI16_S
:
6703 case BFD_RELOC_MIPS_GPREL
:
6704 case BFD_RELOC_MIPS_LITERAL
:
6705 case BFD_RELOC_MIPS_CALL16
:
6706 case BFD_RELOC_MIPS_GOT16
:
6707 case BFD_RELOC_MIPS_GPREL32
:
6708 case BFD_RELOC_MIPS_GOT_HI16
:
6709 case BFD_RELOC_MIPS_GOT_LO16
:
6710 case BFD_RELOC_MIPS_CALL_HI16
:
6711 case BFD_RELOC_MIPS_CALL_LO16
:
6713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6714 "Invalid PC relative reloc");
6715 /* Nothing needed to do. The value comes from the reloc entry */
6718 case BFD_RELOC_PCREL_HI16_S
:
6719 /* The addend for this is tricky if it is internal, so we just
6720 do everything here rather than in bfd_perform_relocation. */
6721 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6723 /* For an external symbol adjust by the address to make it
6724 pcrel_offset. We use the address of the RELLO reloc
6725 which follows this one. */
6726 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6727 + fixP
->fx_next
->fx_where
);
6732 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6733 if (byte_order
== BIG_ENDIAN
)
6735 md_number_to_chars (buf
, value
, 2);
6738 case BFD_RELOC_PCREL_LO16
:
6739 /* The addend for this is tricky if it is internal, so we just
6740 do everything here rather than in bfd_perform_relocation. */
6741 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6742 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6743 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6744 if (byte_order
== BIG_ENDIAN
)
6746 md_number_to_chars (buf
, value
, 2);
6750 /* If we are deleting this reloc entry, we must fill in the
6751 value now. This can happen if we have a .word which is not
6752 resolved when it appears but is later defined. We also need
6753 to fill in the value if this is an embedded PIC switch table
6756 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6757 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6762 /* If we are deleting this reloc entry, we must fill in the
6764 assert (fixP
->fx_size
== 2);
6766 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6770 case BFD_RELOC_LO16
:
6771 /* When handling an embedded PIC switch statement, we can wind
6772 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6775 if (value
< -0x8000 || value
> 0x7fff)
6776 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6777 "relocation overflow");
6778 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6779 if (byte_order
== BIG_ENDIAN
)
6781 md_number_to_chars (buf
, value
, 2);
6785 case BFD_RELOC_16_PCREL_S2
:
6787 * We need to save the bits in the instruction since fixup_segment()
6788 * might be deleting the relocation entry (i.e., a branch within
6789 * the current segment).
6792 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6793 "Branch to odd address (%lx)", value
);
6796 /* update old instruction data */
6797 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6801 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6805 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6813 if (value
>= -0x8000 && value
< 0x8000)
6814 insn
|= value
& 0xffff;
6817 /* The branch offset is too large. If this is an
6818 unconditional branch, and we are not generating PIC code,
6819 we can convert it to an absolute jump instruction. */
6820 if (mips_pic
== NO_PIC
6822 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6823 && (fixP
->fx_frag
->fr_address
6824 < text_section
->vma
+ text_section
->_raw_size
)
6825 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6826 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6827 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6829 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6830 insn
= 0x0c000000; /* jal */
6832 insn
= 0x08000000; /* j */
6833 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6835 fixP
->fx_addsy
= section_symbol (text_section
);
6836 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6840 /* FIXME. It would be possible in principle to handle
6841 conditional branches which overflow. They could be
6842 transformed into a branch around a jump. This would
6843 require setting up variant frags for each different
6844 branch type. The native MIPS assembler attempts to
6845 handle these cases, but it appears to do it
6847 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6848 "Relocation overflow");
6852 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6867 const struct mips_opcode
*p
;
6868 int treg
, sreg
, dreg
, shamt
;
6873 for (i
= 0; i
< NUMOPCODES
; ++i
)
6875 p
= &mips_opcodes
[i
];
6876 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6878 printf ("%08lx %s\t", oc
, p
->name
);
6879 treg
= (oc
>> 16) & 0x1f;
6880 sreg
= (oc
>> 21) & 0x1f;
6881 dreg
= (oc
>> 11) & 0x1f;
6882 shamt
= (oc
>> 6) & 0x1f;
6884 for (args
= p
->args
;; ++args
)
6895 printf ("%c", *args
);
6899 assert (treg
== sreg
);
6900 printf ("$%d,$%d", treg
, sreg
);
6905 printf ("$%d", dreg
);
6910 printf ("$%d", treg
);
6914 printf ("0x%x", treg
);
6919 printf ("$%d", sreg
);
6923 printf ("0x%08lx", oc
& 0x1ffffff);
6935 printf ("$%d", shamt
);
6946 printf ("%08lx UNDEFINED\n", oc
);
6957 name
= input_line_pointer
;
6958 c
= get_symbol_end ();
6959 p
= (symbolS
*) symbol_find_or_make (name
);
6960 *input_line_pointer
= c
;
6964 /* Align the current frag to a given power of two. The MIPS assembler
6965 also automatically adjusts any preceding label. */
6968 mips_align (to
, fill
, label
)
6973 mips_emit_delays ();
6974 frag_align (to
, fill
);
6975 record_alignment (now_seg
, to
);
6978 assert (S_GET_SEGMENT (label
) == now_seg
);
6979 label
->sy_frag
= frag_now
;
6980 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6984 /* Align to a given power of two. .align 0 turns off the automatic
6985 alignment used by the data creating pseudo-ops. */
6992 register long temp_fill
;
6993 long max_alignment
= 15;
6997 o Note that the assembler pulls down any immediately preceeding label
6998 to the aligned address.
6999 o It's not documented but auto alignment is reinstated by
7000 a .align pseudo instruction.
7001 o Note also that after auto alignment is turned off the mips assembler
7002 issues an error on attempt to assemble an improperly aligned data item.
7007 temp
= get_absolute_expression ();
7008 if (temp
> max_alignment
)
7009 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
7012 as_warn ("Alignment negative: 0 assumed.");
7015 if (*input_line_pointer
== ',')
7017 input_line_pointer
++;
7018 temp_fill
= get_absolute_expression ();
7025 mips_align (temp
, (int) temp_fill
, insn_label
);
7032 demand_empty_rest_of_line ();
7036 mips_flush_pending_output ()
7038 mips_emit_delays ();
7048 /* When generating embedded PIC code, we only use the .text, .lit8,
7049 .sdata and .sbss sections. We change the .data and .rdata
7050 pseudo-ops to use .sdata. */
7051 if (mips_pic
== EMBEDDED_PIC
7052 && (sec
== 'd' || sec
== 'r'))
7055 mips_emit_delays ();
7065 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
7066 demand_empty_rest_of_line ();
7070 if (USE_GLOBAL_POINTER_OPT
)
7072 seg
= subseg_new (RDATA_SECTION_NAME
,
7073 (subsegT
) get_absolute_expression ());
7074 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7076 bfd_set_section_flags (stdoutput
, seg
,
7082 bfd_set_section_alignment (stdoutput
, seg
, 4);
7084 demand_empty_rest_of_line ();
7088 as_bad ("No read only data section in this object file format");
7089 demand_empty_rest_of_line ();
7095 if (USE_GLOBAL_POINTER_OPT
)
7097 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
7098 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7100 bfd_set_section_flags (stdoutput
, seg
,
7101 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
7103 bfd_set_section_alignment (stdoutput
, seg
, 4);
7105 demand_empty_rest_of_line ();
7110 as_bad ("Global pointers not supported; recompile -G 0");
7111 demand_empty_rest_of_line ();
7120 mips_enable_auto_align ()
7132 mips_emit_delays ();
7133 if (log_size
> 0 && auto_align
)
7134 mips_align (log_size
, 0, label
);
7136 cons (1 << log_size
);
7147 mips_emit_delays ();
7151 mips_align (3, 0, label
);
7153 mips_align (2, 0, label
);
7160 /* Handle .globl. We need to override it because on Irix 5 you are
7163 where foo is an undefined symbol, to mean that foo should be
7164 considered to be the address of a function. */
7175 name
= input_line_pointer
;
7176 c
= get_symbol_end ();
7177 symbolP
= symbol_find_or_make (name
);
7178 *input_line_pointer
= c
;
7181 /* On Irix 5, every global symbol that is not explicitly labelled as
7182 being a function is apparently labelled as being an object. */
7185 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7190 secname
= input_line_pointer
;
7191 c
= get_symbol_end ();
7192 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7194 as_bad ("%s: no such section", secname
);
7195 *input_line_pointer
= c
;
7197 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7198 flag
= BSF_FUNCTION
;
7201 symbolP
->bsym
->flags
|= flag
;
7203 S_SET_EXTERNAL (symbolP
);
7204 demand_empty_rest_of_line ();
7214 opt
= input_line_pointer
;
7215 c
= get_symbol_end ();
7219 /* FIXME: What does this mean? */
7221 else if (strncmp (opt
, "pic", 3) == 0)
7229 mips_pic
= SVR4_PIC
;
7231 as_bad (".option pic%d not supported", i
);
7233 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7235 if (g_switch_seen
&& g_switch_value
!= 0)
7236 as_warn ("-G may not be used with SVR4 PIC code");
7238 bfd_set_gp_size (stdoutput
, 0);
7242 as_warn ("Unrecognized option \"%s\"", opt
);
7244 *input_line_pointer
= c
;
7245 demand_empty_rest_of_line ();
7252 char *name
= input_line_pointer
, ch
;
7254 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7255 input_line_pointer
++;
7256 ch
= *input_line_pointer
;
7257 *input_line_pointer
= '\0';
7259 if (strcmp (name
, "reorder") == 0)
7263 prev_insn_unreordered
= 1;
7264 prev_prev_insn_unreordered
= 1;
7268 else if (strcmp (name
, "noreorder") == 0)
7270 mips_emit_delays ();
7272 mips_any_noreorder
= 1;
7274 else if (strcmp (name
, "at") == 0)
7278 else if (strcmp (name
, "noat") == 0)
7282 else if (strcmp (name
, "macro") == 0)
7284 mips_warn_about_macros
= 0;
7286 else if (strcmp (name
, "nomacro") == 0)
7288 if (mips_noreorder
== 0)
7289 as_bad ("`noreorder' must be set before `nomacro'");
7290 mips_warn_about_macros
= 1;
7292 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7296 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7300 else if (strcmp (name
, "bopt") == 0)
7304 else if (strcmp (name
, "nobopt") == 0)
7308 else if (strncmp (name
, "mips", 4) == 0)
7312 /* Permit the user to change the ISA on the fly. Needless to
7313 say, misuse can cause serious problems. */
7314 isa
= atoi (name
+ 4);
7316 mips_isa
= file_mips_isa
;
7317 else if (isa
< 1 || isa
> 4)
7318 as_bad ("unknown ISA level");
7324 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7326 *input_line_pointer
= ch
;
7327 demand_empty_rest_of_line ();
7330 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7331 .option pic2. It means to generate SVR4 PIC calls. */
7337 mips_pic
= SVR4_PIC
;
7338 if (USE_GLOBAL_POINTER_OPT
)
7340 if (g_switch_seen
&& g_switch_value
!= 0)
7341 as_warn ("-G may not be used with SVR4 PIC code");
7344 bfd_set_gp_size (stdoutput
, 0);
7345 demand_empty_rest_of_line ();
7348 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7349 PIC code. It sets the $gp register for the function based on the
7350 function address, which is in the register named in the argument.
7351 This uses a relocation against _gp_disp, which is handled specially
7352 by the linker. The result is:
7353 lui $gp,%hi(_gp_disp)
7354 addiu $gp,$gp,%lo(_gp_disp)
7355 addu $gp,$gp,.cpload argument
7356 The .cpload argument is normally $25 == $t9. */
7365 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7366 if (mips_pic
!= SVR4_PIC
)
7372 /* .cpload should be a in .set noreorder section. */
7373 if (mips_noreorder
== 0)
7374 as_warn (".cpload not in noreorder section");
7377 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7378 ex
.X_op_symbol
= NULL
;
7379 ex
.X_add_number
= 0;
7381 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7382 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7384 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7385 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7386 (int) BFD_RELOC_LO16
);
7388 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7389 GP
, GP
, tc_get_register (0));
7391 demand_empty_rest_of_line ();
7394 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7395 offset from $sp. The offset is remembered, and after making a PIC
7396 call $gp is restored from that location. */
7399 s_cprestore (ignore
)
7405 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7406 if (mips_pic
!= SVR4_PIC
)
7412 mips_cprestore_offset
= get_absolute_expression ();
7414 ex
.X_op
= O_constant
;
7415 ex
.X_add_symbol
= NULL
;
7416 ex
.X_op_symbol
= NULL
;
7417 ex
.X_add_number
= mips_cprestore_offset
;
7419 macro_build ((char *) NULL
, &icnt
, &ex
,
7420 mips_isa
< 3 ? "sw" : "sd",
7421 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7423 demand_empty_rest_of_line ();
7426 /* Handle the .gpword pseudo-op. This is used when generating PIC
7427 code. It generates a 32 bit GP relative reloc. */
7437 /* When not generating PIC code, this is treated as .word. */
7438 if (mips_pic
!= SVR4_PIC
)
7445 mips_emit_delays ();
7447 mips_align (2, 0, label
);
7452 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7454 as_bad ("Unsupported use of .gpword");
7455 ignore_rest_of_line ();
7459 md_number_to_chars (p
, (valueT
) 0, 4);
7460 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7461 BFD_RELOC_MIPS_GPREL32
);
7463 demand_empty_rest_of_line ();
7466 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7467 tables in SVR4 PIC code. */
7476 /* This is ignored when not generating SVR4 PIC code. */
7477 if (mips_pic
!= SVR4_PIC
)
7483 /* Add $gp to the register named as an argument. */
7484 reg
= tc_get_register (0);
7485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7486 mips_isa
< 3 ? "addu" : "daddu",
7487 "d,v,t", reg
, reg
, GP
);
7489 demand_empty_rest_of_line ();
7492 /* Parse a register string into a number. Called from the ECOFF code
7493 to parse .frame. The argument is non-zero if this is the frame
7494 register, so that we can record it in mips_frame_reg. */
7497 tc_get_register (frame
)
7503 if (*input_line_pointer
++ != '$')
7505 as_warn ("expected `$'");
7508 else if (isdigit ((unsigned char) *input_line_pointer
))
7510 reg
= get_absolute_expression ();
7511 if (reg
< 0 || reg
>= 32)
7513 as_warn ("Bad register number");
7519 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7521 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7523 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7525 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7529 as_warn ("Unrecognized register name");
7532 input_line_pointer
+= 2;
7535 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7540 md_section_align (seg
, addr
)
7544 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7547 /* We don't need to align ELF sections to the full alignment.
7548 However, Irix 5 may prefer that we align them at least to a 16
7554 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7557 /* Utility routine, called from above as well. If called while the
7558 input file is still being read, it's only an approximation. (For
7559 example, a symbol may later become defined which appeared to be
7560 undefined earlier.) */
7563 nopic_need_relax (sym
)
7569 if (USE_GLOBAL_POINTER_OPT
)
7571 const char *symname
;
7574 /* Find out whether this symbol can be referenced off the GP
7575 register. It can be if it is smaller than the -G size or if
7576 it is in the .sdata or .sbss section. Certain symbols can
7577 not be referenced off the GP, although it appears as though
7579 symname
= S_GET_NAME (sym
);
7580 if (symname
!= (const char *) NULL
7581 && (strcmp (symname
, "eprol") == 0
7582 || strcmp (symname
, "etext") == 0
7583 || strcmp (symname
, "_gp") == 0
7584 || strcmp (symname
, "edata") == 0
7585 || strcmp (symname
, "_fbss") == 0
7586 || strcmp (symname
, "_fdata") == 0
7587 || strcmp (symname
, "_ftext") == 0
7588 || strcmp (symname
, "end") == 0
7589 || strcmp (symname
, "_gp_disp") == 0))
7591 else if (! S_IS_DEFINED (sym
)
7593 #ifndef NO_ECOFF_DEBUGGING
7594 || (sym
->ecoff_extern_size
!= 0
7595 && sym
->ecoff_extern_size
<= g_switch_value
)
7597 || (S_GET_VALUE (sym
) != 0
7598 && S_GET_VALUE (sym
) <= g_switch_value
)))
7602 const char *segname
;
7604 segname
= segment_name (S_GET_SEGMENT (sym
));
7605 assert (strcmp (segname
, ".lit8") != 0
7606 && strcmp (segname
, ".lit4") != 0);
7607 change
= (strcmp (segname
, ".sdata") != 0
7608 && strcmp (segname
, ".sbss") != 0);
7613 /* We are not optimizing for the GP register. */
7617 /* Estimate the size of a frag before relaxing. We are not really
7618 relaxing here, and the final size is encoded in the subtype
7623 md_estimate_size_before_relax (fragp
, segtype
)
7629 if (mips_pic
== NO_PIC
)
7631 change
= nopic_need_relax (fragp
->fr_symbol
);
7633 else if (mips_pic
== SVR4_PIC
)
7635 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7637 /* This must duplicate the test in adjust_reloc_syms. */
7638 change
= (symsec
!= &bfd_und_section
7639 && symsec
!= &bfd_abs_section
7640 && ! bfd_is_com_section (symsec
));
7647 /* Record the offset to the first reloc in the fr_opcode field.
7648 This lets md_convert_frag and tc_gen_reloc know that the code
7649 must be expanded. */
7650 fragp
->fr_opcode
= (fragp
->fr_literal
7652 - RELAX_OLD (fragp
->fr_subtype
)
7653 + RELAX_RELOC1 (fragp
->fr_subtype
));
7654 /* FIXME: This really needs as_warn_where. */
7655 if (RELAX_WARN (fragp
->fr_subtype
))
7656 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7662 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7665 /* Translate internal representation of relocation info to BFD target
7669 tc_gen_reloc (section
, fixp
)
7673 static arelent
*retval
[4];
7675 bfd_reloc_code_real_type code
;
7677 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7680 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7681 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7683 if (mips_pic
== EMBEDDED_PIC
7684 && SWITCH_TABLE (fixp
))
7686 /* For a switch table entry we use a special reloc. The addend
7687 is actually the difference between the reloc address and the
7689 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7690 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7691 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7692 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7694 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7696 /* We use a special addend for an internal RELLO reloc. */
7697 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7698 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7700 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7702 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7704 assert (fixp
->fx_next
!= NULL
7705 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7706 /* We use a special addend for an internal RELHI reloc. The
7707 reloc is relative to the RELLO; adjust the addend
7709 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7710 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7711 + fixp
->fx_next
->fx_where
7712 - S_GET_VALUE (fixp
->fx_subsy
));
7714 reloc
->addend
= (fixp
->fx_addnumber
7715 + fixp
->fx_next
->fx_frag
->fr_address
7716 + fixp
->fx_next
->fx_where
);
7718 else if (fixp
->fx_pcrel
== 0)
7719 reloc
->addend
= fixp
->fx_addnumber
;
7722 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7723 /* A gruesome hack which is a result of the gruesome gas reloc
7725 reloc
->addend
= reloc
->address
;
7727 reloc
->addend
= -reloc
->address
;
7730 /* If this is a variant frag, we may need to adjust the existing
7731 reloc and generate a new one. */
7732 if (fixp
->fx_frag
->fr_opcode
!= NULL
7733 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7734 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7735 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7736 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7737 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7738 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7739 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7743 /* If this is not the last reloc in this frag, then we have two
7744 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7745 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7746 the second one handle all of them. */
7747 if (fixp
->fx_next
!= NULL
7748 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7750 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7751 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7752 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7753 && (fixp
->fx_next
->fx_r_type
7754 == BFD_RELOC_MIPS_GOT_LO16
))
7755 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7756 && (fixp
->fx_next
->fx_r_type
7757 == BFD_RELOC_MIPS_CALL_LO16
)));
7762 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7763 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7764 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7766 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7767 reloc2
->address
= (reloc
->address
7768 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7769 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7770 reloc2
->addend
= fixp
->fx_addnumber
;
7771 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7772 assert (reloc2
->howto
!= NULL
);
7774 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7778 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7781 reloc3
->address
+= 4;
7784 if (mips_pic
== NO_PIC
)
7786 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7787 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7789 else if (mips_pic
== SVR4_PIC
)
7791 switch (fixp
->fx_r_type
)
7795 case BFD_RELOC_MIPS_GOT16
:
7797 case BFD_RELOC_MIPS_CALL16
:
7798 case BFD_RELOC_MIPS_GOT_LO16
:
7799 case BFD_RELOC_MIPS_CALL_LO16
:
7800 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7808 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
7809 fixup_segment converted a non-PC relative reloc into a PC
7810 relative reloc. In such a case, we need to convert the reloc
7812 code
= fixp
->fx_r_type
;
7818 code
= BFD_RELOC_8_PCREL
;
7821 code
= BFD_RELOC_16_PCREL
;
7824 code
= BFD_RELOC_32_PCREL
;
7826 case BFD_RELOC_8_PCREL
:
7827 case BFD_RELOC_16_PCREL
:
7828 case BFD_RELOC_32_PCREL
:
7829 case BFD_RELOC_16_PCREL_S2
:
7830 case BFD_RELOC_PCREL_HI16_S
:
7831 case BFD_RELOC_PCREL_LO16
:
7834 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7835 "Cannot make %s relocation PC relative",
7836 bfd_get_reloc_code_name (code
));
7840 /* To support a PC relative reloc when generating embedded PIC code
7841 for ECOFF, we use a Cygnus extension. We check for that here to
7842 make sure that we don't let such a reloc escape normally. */
7843 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7844 && code
== BFD_RELOC_16_PCREL_S2
7845 && mips_pic
!= EMBEDDED_PIC
)
7846 reloc
->howto
= NULL
;
7848 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
7850 if (reloc
->howto
== NULL
)
7852 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7853 "Can not represent %s relocation in this object file format",
7854 bfd_get_reloc_code_name (code
));
7861 /* Convert a machine dependent frag. */
7864 md_convert_frag (abfd
, asec
, fragp
)
7872 if (fragp
->fr_opcode
== NULL
)
7875 old
= RELAX_OLD (fragp
->fr_subtype
);
7876 new = RELAX_NEW (fragp
->fr_subtype
);
7877 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7880 memcpy (fixptr
- old
, fixptr
, new);
7882 fragp
->fr_fix
+= new - old
;
7885 /* This function is called whenever a label is defined. It is used
7886 when handling branch delays; if a branch has a label, we assume we
7890 mips_define_label (sym
)
7896 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7897 In order to work with gcc when using mips-tfile, we must keep all
7898 local labels. However, in other cases, we want to discard them,
7899 since they are useless. */
7902 mips_local_label (name
)
7905 #ifndef NO_ECOFF_DEBUGGING
7908 && ! ecoff_debugging_seen
)
7910 /* We were called with -g, but we didn't see any debugging
7911 information. That may mean that gcc is smuggling debugging
7912 information through to mips-tfile, in which case we must
7913 generate all local labels. */
7918 /* Here it's OK to discard local labels. */
7920 return name
[0] == '$';
7923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7925 /* Some special processing for a MIPS ELF file. */
7928 mips_elf_final_processing ()
7930 /* Write out the register information. */
7935 s
.ri_gprmask
= mips_gprmask
;
7936 s
.ri_cprmask
[0] = mips_cprmask
[0];
7937 s
.ri_cprmask
[1] = mips_cprmask
[1];
7938 s
.ri_cprmask
[2] = mips_cprmask
[2];
7939 s
.ri_cprmask
[3] = mips_cprmask
[3];
7940 /* The gp_value field is set by the MIPS ELF backend. */
7942 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7943 ((Elf32_External_RegInfo
*)
7944 mips_regmask_frag
));
7948 Elf64_Internal_RegInfo s
;
7950 s
.ri_gprmask
= mips_gprmask
;
7952 s
.ri_cprmask
[0] = mips_cprmask
[0];
7953 s
.ri_cprmask
[1] = mips_cprmask
[1];
7954 s
.ri_cprmask
[2] = mips_cprmask
[2];
7955 s
.ri_cprmask
[3] = mips_cprmask
[3];
7956 /* The gp_value field is set by the MIPS ELF backend. */
7958 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7959 ((Elf64_External_RegInfo
*)
7960 mips_regmask_frag
));
7963 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7964 sort of BFD interface for this. */
7965 if (mips_any_noreorder
)
7966 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7967 if (mips_pic
!= NO_PIC
)
7968 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7971 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7973 /* These functions should really be defined by the object file format,
7974 since they are related to debugging information. However, this
7975 code has to work for the a.out format, which does not define them,
7976 so we provide simple versions here. These don't actually generate
7977 any debugging information, but they do simple checking and someday
7978 somebody may make them useful. */
7982 struct loc
*loc_next
;
7983 unsigned long loc_fileno
;
7984 unsigned long loc_lineno
;
7985 unsigned long loc_offset
;
7986 unsigned short loc_delta
;
7987 unsigned short loc_count
;
7996 struct proc
*proc_next
;
7997 struct symbol
*proc_isym
;
7998 struct symbol
*proc_end
;
7999 unsigned long proc_reg_mask
;
8000 unsigned long proc_reg_offset
;
8001 unsigned long proc_fpreg_mask
;
8002 unsigned long proc_fpreg_offset
;
8003 unsigned long proc_frameoffset
;
8004 unsigned long proc_framereg
;
8005 unsigned long proc_pcreg
;
8007 struct file
*proc_file
;
8014 struct file
*file_next
;
8015 unsigned long file_fileno
;
8016 struct symbol
*file_symbol
;
8017 struct symbol
*file_end
;
8018 struct proc
*file_proc
;
8023 static struct obstack proc_frags
;
8024 static procS
*proc_lastP
;
8025 static procS
*proc_rootP
;
8026 static int numprocs
;
8031 obstack_begin (&proc_frags
, 0x2000);
8037 /* check for premature end, nesting errors, etc */
8038 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8039 as_warn ("missing `.end' at end of assembly");
8048 if (*input_line_pointer
== '-')
8050 ++input_line_pointer
;
8053 if (!isdigit (*input_line_pointer
))
8054 as_bad ("Expected simple number.");
8055 if (input_line_pointer
[0] == '0')
8057 if (input_line_pointer
[1] == 'x')
8059 input_line_pointer
+= 2;
8060 while (isxdigit (*input_line_pointer
))
8063 val
|= hex_value (*input_line_pointer
++);
8065 return negative
? -val
: val
;
8069 ++input_line_pointer
;
8070 while (isdigit (*input_line_pointer
))
8073 val
|= *input_line_pointer
++ - '0';
8075 return negative
? -val
: val
;
8078 if (!isdigit (*input_line_pointer
))
8080 printf (" *input_line_pointer == '%c' 0x%02x\n",
8081 *input_line_pointer
, *input_line_pointer
);
8082 as_warn ("Invalid number");
8085 while (isdigit (*input_line_pointer
))
8088 val
+= *input_line_pointer
++ - '0';
8090 return negative
? -val
: val
;
8093 /* The .file directive; just like the usual .file directive, but there
8094 is an initial number which is the ECOFF file index. */
8102 line
= get_number ();
8107 /* The .end directive. */
8115 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8118 demand_empty_rest_of_line ();
8122 if (now_seg
!= text_section
)
8123 as_warn (".end not in text section");
8126 as_warn (".end and no .ent seen yet.");
8132 assert (S_GET_NAME (p
));
8133 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
8134 as_warn (".end symbol does not match .ent symbol.");
8137 proc_lastP
->proc_end
= (symbolS
*) 1;
8140 /* The .aent and .ent directives. */
8150 symbolP
= get_symbol ();
8151 if (*input_line_pointer
== ',')
8152 input_line_pointer
++;
8154 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
8155 number
= get_number ();
8156 if (now_seg
!= text_section
)
8157 as_warn (".ent or .aent not in text section.");
8159 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
8160 as_warn ("missing `.end'");
8164 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
8165 procP
->proc_isym
= symbolP
;
8166 procP
->proc_reg_mask
= 0;
8167 procP
->proc_reg_offset
= 0;
8168 procP
->proc_fpreg_mask
= 0;
8169 procP
->proc_fpreg_offset
= 0;
8170 procP
->proc_frameoffset
= 0;
8171 procP
->proc_framereg
= 0;
8172 procP
->proc_pcreg
= 0;
8173 procP
->proc_end
= NULL
;
8174 procP
->proc_next
= NULL
;
8176 proc_lastP
->proc_next
= procP
;
8182 demand_empty_rest_of_line ();
8185 /* The .frame directive. */
8198 frame_reg
= tc_get_register (1);
8199 if (*input_line_pointer
== ',')
8200 input_line_pointer
++;
8201 frame_off
= get_absolute_expression ();
8202 if (*input_line_pointer
== ',')
8203 input_line_pointer
++;
8204 pcreg
= tc_get_register (0);
8207 assert (proc_rootP
);
8208 proc_rootP
->proc_framereg
= frame_reg
;
8209 proc_rootP
->proc_frameoffset
= frame_off
;
8210 proc_rootP
->proc_pcreg
= pcreg
;
8211 /* bob macho .frame */
8213 /* We don't have to write out a frame stab for unoptimized code. */
8214 if (!(frame_reg
== FP
&& frame_off
== 0))
8217 as_warn ("No .ent for .frame to use.");
8218 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8219 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8220 S_SET_TYPE (symP
, N_RMASK
);
8221 S_SET_OTHER (symP
, 0);
8222 S_SET_DESC (symP
, 0);
8223 symP
->sy_forward
= proc_lastP
->proc_isym
;
8224 /* bob perhaps I should have used pseudo set */
8226 demand_empty_rest_of_line ();
8230 /* The .fmask and .mask directives. */
8237 char str
[100], *strP
;
8243 mask
= get_number ();
8244 if (*input_line_pointer
== ',')
8245 input_line_pointer
++;
8246 off
= get_absolute_expression ();
8248 /* bob only for coff */
8249 assert (proc_rootP
);
8250 if (reg_type
== 'F')
8252 proc_rootP
->proc_fpreg_mask
= mask
;
8253 proc_rootP
->proc_fpreg_offset
= off
;
8257 proc_rootP
->proc_reg_mask
= mask
;
8258 proc_rootP
->proc_reg_offset
= off
;
8261 /* bob macho .mask + .fmask */
8263 /* We don't have to write out a mask stab if no saved regs. */
8267 as_warn ("No .ent for .mask to use.");
8269 for (i
= 0; i
< 32; i
++)
8273 sprintf (strP
, "%c%d,", reg_type
, i
);
8274 strP
+= strlen (strP
);
8278 sprintf (strP
, ";%d,", off
);
8279 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8280 S_SET_TYPE (symP
, N_RMASK
);
8281 S_SET_OTHER (symP
, 0);
8282 S_SET_DESC (symP
, 0);
8283 symP
->sy_forward
= proc_lastP
->proc_isym
;
8284 /* bob perhaps I should have used pseudo set */
8289 /* The .loc directive. */
8300 assert (now_seg
== text_section
);
8302 lineno
= get_number ();
8303 addroff
= frag_now_fix ();
8305 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8306 S_SET_TYPE (symbolP
, N_SLINE
);
8307 S_SET_OTHER (symbolP
, 0);
8308 S_SET_DESC (symbolP
, lineno
);
8309 symbolP
->sy_segment
= now_seg
;