1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* Whether the 4650 instructions (mad/madu) are permitted. */
198 static int mips_4650
= -1;
200 /* Whether the 4010 instructions are permitted. */
201 static int mips_4010
= -1;
203 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
204 static int mips_4100
= -1;
206 /* start-sanitize-vr5400 */
207 /* Whether NEC vr5400 instructions are permitted. */
208 static int mips_5400
= -1;
210 /* end-sanitize-vr5400 */
211 /* start-sanitize-r5900 */
212 /* Whether Toshiba r5900 instructions are permitted. */
213 static int mips_5900
= -1;
215 /* end-sanitize-r5900 */
216 /* Whether Toshiba r3900 instructions are permitted. */
217 static int mips_3900
= -1;
219 /* start-sanitize-tx19 */
220 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
221 The tx19 related options and configuration bits are handled by
223 /* end-sanitize-tx19 */
225 /* Whether the processor uses hardware interlocks to protect
226 reads from the HI and LO registers, and thus does not
227 require nops to be inserted. */
228 #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900 \
229 /* start-sanitize-tx49 */ \
230 || mips_cpu == 4900 \
231 /* end-sanitize-tx49 */ \
234 /* Whether the processor uses hardware interlocks to protect reads
235 from the GPRs, and thus does not require nops to be inserted. */
236 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
238 /* As with other "interlocks" this is used by hardware that has FP
239 (co-processor) interlocks. */
240 /* Itbl support may require additional care here. */
241 #define cop_interlocks (mips_cpu == 4300)
243 /* MIPS PIC level. */
247 /* Do not generate PIC code. */
250 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
251 not sure what it is supposed to do. */
254 /* Generate PIC code as in the SVR4 MIPS ABI. */
257 /* Generate PIC code without using a global offset table: the data
258 segment has a maximum size of 64K, all data references are off
259 the $gp register, and all text references are PC relative. This
260 is used on some embedded systems. */
264 static enum mips_pic_level mips_pic
;
266 /* 1 if we should generate 32 bit offsets from the GP register in
267 SVR4_PIC mode. Currently has no meaning in other modes. */
268 static int mips_big_got
;
270 /* 1 if trap instructions should used for overflow rather than break
272 static int mips_trap
;
274 /* Non-zero if any .set noreorder directives were used. */
276 static int mips_any_noreorder
;
278 /* The size of the small data section. */
279 static int g_switch_value
= 8;
280 /* Whether the -G option was used. */
281 static int g_switch_seen
= 0;
286 /* If we can determine in advance that GP optimization won't be
287 possible, we can skip the relaxation stuff that tries to produce
288 GP-relative references. This makes delay slot optimization work
291 This function can only provide a guess, but it seems to work for
292 gcc output. If it guesses wrong, the only loss should be in
293 efficiency; it shouldn't introduce any bugs.
295 I don't know if a fix is needed for the SVR4_PIC mode. I've only
296 fixed it for the non-PIC mode. KR 95/04/07 */
297 static int nopic_need_relax
PARAMS ((symbolS
*, int));
299 /* handle of the OPCODE hash table */
300 static struct hash_control
*op_hash
= NULL
;
302 /* The opcode hash table we use for the mips16. */
303 static struct hash_control
*mips16_op_hash
= NULL
;
305 /* This array holds the chars that always start a comment. If the
306 pre-processor is disabled, these aren't very useful */
307 const char comment_chars
[] = "#";
309 /* This array holds the chars that only start a comment at the beginning of
310 a line. If the line seems to have the form '# 123 filename'
311 .line and .file directives will appear in the pre-processed output */
312 /* Note that input_file.c hand checks for '#' at the beginning of the
313 first line of the input file. This is because the compiler outputs
314 #NO_APP at the beginning of its output. */
315 /* Also note that C style comments are always supported. */
316 const char line_comment_chars
[] = "#";
318 /* This array holds machine specific line separator characters. */
319 const char line_separator_chars
[] = "";
321 /* Chars that can be used to separate mant from exp in floating point nums */
322 const char EXP_CHARS
[] = "eE";
324 /* Chars that mean this number is a floating point constant */
327 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
329 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
330 changed in read.c . Ideally it shouldn't have to know about it at all,
331 but nothing is ideal around here.
334 static char *insn_error
;
336 static int auto_align
= 1;
338 /* When outputting SVR4 PIC code, the assembler needs to know the
339 offset in the stack frame from which to restore the $gp register.
340 This is set by the .cprestore pseudo-op, and saved in this
342 static offsetT mips_cprestore_offset
= -1;
344 /* This is the register which holds the stack frame, as set by the
345 .frame pseudo-op. This is needed to implement .cprestore. */
346 static int mips_frame_reg
= SP
;
348 /* To output NOP instructions correctly, we need to keep information
349 about the previous two instructions. */
351 /* Whether we are optimizing. The default value of 2 means to remove
352 unneeded NOPs and swap branch instructions when possible. A value
353 of 1 means to not swap branches. A value of 0 means to always
355 static int mips_optimize
= 2;
357 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
358 equivalent to seeing no -g option at all. */
359 static int mips_debug
= 0;
361 /* The previous instruction. */
362 static struct mips_cl_insn prev_insn
;
364 /* The instruction before prev_insn. */
365 static struct mips_cl_insn prev_prev_insn
;
367 /* If we don't want information for prev_insn or prev_prev_insn, we
368 point the insn_mo field at this dummy integer. */
369 static const struct mips_opcode dummy_opcode
= { 0 };
371 /* Non-zero if prev_insn is valid. */
372 static int prev_insn_valid
;
374 /* The frag for the previous instruction. */
375 static struct frag
*prev_insn_frag
;
377 /* The offset into prev_insn_frag for the previous instruction. */
378 static long prev_insn_where
;
380 /* The reloc type for the previous instruction, if any. */
381 static bfd_reloc_code_real_type prev_insn_reloc_type
;
383 /* The reloc for the previous instruction, if any. */
384 static fixS
*prev_insn_fixp
;
386 /* Non-zero if the previous instruction was in a delay slot. */
387 static int prev_insn_is_delay_slot
;
389 /* Non-zero if the previous instruction was in a .set noreorder. */
390 static int prev_insn_unreordered
;
392 /* Non-zero if the previous instruction uses an extend opcode (if
394 static int prev_insn_extended
;
396 /* Non-zero if the previous previous instruction was in a .set
398 static int prev_prev_insn_unreordered
;
400 /* If this is set, it points to a frag holding nop instructions which
401 were inserted before the start of a noreorder section. If those
402 nops turn out to be unnecessary, the size of the frag can be
404 static fragS
*prev_nop_frag
;
406 /* The number of nop instructions we created in prev_nop_frag. */
407 static int prev_nop_frag_holds
;
409 /* The number of nop instructions that we know we need in
411 static int prev_nop_frag_required
;
413 /* The number of instructions we've seen since prev_nop_frag. */
414 static int prev_nop_frag_since
;
416 /* For ECOFF and ELF, relocations against symbols are done in two
417 parts, with a HI relocation and a LO relocation. Each relocation
418 has only 16 bits of space to store an addend. This means that in
419 order for the linker to handle carries correctly, it must be able
420 to locate both the HI and the LO relocation. This means that the
421 relocations must appear in order in the relocation table.
423 In order to implement this, we keep track of each unmatched HI
424 relocation. We then sort them so that they immediately precede the
425 corresponding LO relocation. */
430 struct mips_hi_fixup
*next
;
433 /* The section this fixup is in. */
437 /* The list of unmatched HI relocs. */
439 static struct mips_hi_fixup
*mips_hi_fixup_list
;
441 /* Map normal MIPS register numbers to mips16 register numbers. */
443 #define X ILLEGAL_REG
444 static const int mips32_to_16_reg_map
[] =
446 X
, X
, 2, 3, 4, 5, 6, 7,
447 X
, X
, X
, X
, X
, X
, X
, X
,
448 0, 1, X
, X
, X
, X
, X
, X
,
449 X
, X
, X
, X
, X
, X
, X
, X
453 /* Map mips16 register numbers to normal MIPS register numbers. */
455 static const int mips16_to_32_reg_map
[] =
457 16, 17, 2, 3, 4, 5, 6, 7
460 /* Since the MIPS does not have multiple forms of PC relative
461 instructions, we do not have to do relaxing as is done on other
462 platforms. However, we do have to handle GP relative addressing
463 correctly, which turns out to be a similar problem.
465 Every macro that refers to a symbol can occur in (at least) two
466 forms, one with GP relative addressing and one without. For
467 example, loading a global variable into a register generally uses
468 a macro instruction like this:
470 If i can be addressed off the GP register (this is true if it is in
471 the .sbss or .sdata section, or if it is known to be smaller than
472 the -G argument) this will generate the following instruction:
474 This instruction will use a GPREL reloc. If i can not be addressed
475 off the GP register, the following instruction sequence will be used:
478 In this case the first instruction will have a HI16 reloc, and the
479 second reloc will have a LO16 reloc. Both relocs will be against
482 The issue here is that we may not know whether i is GP addressable
483 until after we see the instruction that uses it. Therefore, we
484 want to be able to choose the final instruction sequence only at
485 the end of the assembly. This is similar to the way other
486 platforms choose the size of a PC relative instruction only at the
489 When generating position independent code we do not use GP
490 addressing in quite the same way, but the issue still arises as
491 external symbols and local symbols must be handled differently.
493 We handle these issues by actually generating both possible
494 instruction sequences. The longer one is put in a frag_var with
495 type rs_machine_dependent. We encode what to do with the frag in
496 the subtype field. We encode (1) the number of existing bytes to
497 replace, (2) the number of new bytes to use, (3) the offset from
498 the start of the existing bytes to the first reloc we must generate
499 (that is, the offset is applied from the start of the existing
500 bytes after they are replaced by the new bytes, if any), (4) the
501 offset from the start of the existing bytes to the second reloc,
502 (5) whether a third reloc is needed (the third reloc is always four
503 bytes after the second reloc), and (6) whether to warn if this
504 variant is used (this is sometimes needed if .set nomacro or .set
505 noat is in effect). All these numbers are reasonably small.
507 Generating two instruction sequences must be handled carefully to
508 ensure that delay slots are handled correctly. Fortunately, there
509 are a limited number of cases. When the second instruction
510 sequence is generated, append_insn is directed to maintain the
511 existing delay slot information, so it continues to apply to any
512 code after the second instruction sequence. This means that the
513 second instruction sequence must not impose any requirements not
514 required by the first instruction sequence.
516 These variant frags are then handled in functions called by the
517 machine independent code. md_estimate_size_before_relax returns
518 the final size of the frag. md_convert_frag sets up the final form
519 of the frag. tc_gen_reloc adjust the first reloc and adds a second
521 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
525 | (((reloc1) + 64) << 9) \
526 | (((reloc2) + 64) << 2) \
527 | ((reloc3) ? (1 << 1) : 0) \
529 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
530 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
531 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
532 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
533 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
534 #define RELAX_WARN(i) ((i) & 1)
536 /* For mips16 code, we use an entirely different form of relaxation.
537 mips16 supports two versions of most instructions which take
538 immediate values: a small one which takes some small value, and a
539 larger one which takes a 16 bit value. Since branches also follow
540 this pattern, relaxing these values is required.
542 We can assemble both mips16 and normal MIPS code in a single
543 object. Therefore, we need to support this type of relaxation at
544 the same time that we support the relaxation described above. We
545 use the high bit of the subtype field to distinguish these cases.
547 The information we store for this type of relaxation is the
548 argument code found in the opcode file for this relocation, whether
549 the user explicitly requested a small or extended form, and whether
550 the relocation is in a jump or jal delay slot. That tells us the
551 size of the value, and how it should be stored. We also store
552 whether the fragment is considered to be extended or not. We also
553 store whether this is known to be a branch to a different section,
554 whether we have tried to relax this frag yet, and whether we have
555 ever extended a PC relative fragment because of a shift count. */
556 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
559 | ((small) ? 0x100 : 0) \
560 | ((ext) ? 0x200 : 0) \
561 | ((dslot) ? 0x400 : 0) \
562 | ((jal_dslot) ? 0x800 : 0))
563 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
564 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
565 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
566 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
567 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
568 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
569 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
570 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
571 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
572 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
573 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
574 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
576 /* Prototypes for static functions. */
579 #define internalError() \
580 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
582 #define internalError() as_fatal ("MIPS internal Error");
585 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
587 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
588 unsigned int reg
, enum mips_regclass
class));
589 static int reg_needs_delay
PARAMS ((int));
590 static void mips16_mark_labels
PARAMS ((void));
591 static void append_insn
PARAMS ((char *place
,
592 struct mips_cl_insn
* ip
,
594 bfd_reloc_code_real_type r
,
596 static void mips_no_prev_insn
PARAMS ((int));
597 static void mips_emit_delays
PARAMS ((boolean
));
599 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
600 const char *name
, const char *fmt
,
603 static void macro_build ();
605 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
606 const char *, const char *,
608 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
609 expressionS
* ep
, int regnum
));
610 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
611 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
613 static void load_register
PARAMS ((int *, int, expressionS
*, int));
614 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
615 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
616 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
617 #ifdef LOSING_COMPILER
618 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
620 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
621 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
622 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
623 boolean
, boolean
, unsigned long *,
624 boolean
*, unsigned short *));
625 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
626 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
627 static symbolS
*get_symbol
PARAMS ((void));
628 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
629 static void s_align
PARAMS ((int));
630 static void s_change_sec
PARAMS ((int));
631 static void s_cons
PARAMS ((int));
632 static void s_float_cons
PARAMS ((int));
633 static void s_mips_globl
PARAMS ((int));
634 static void s_option
PARAMS ((int));
635 static void s_mipsset
PARAMS ((int));
636 static void s_abicalls
PARAMS ((int));
637 static void s_cpload
PARAMS ((int));
638 static void s_cprestore
PARAMS ((int));
639 static void s_gpword
PARAMS ((int));
640 static void s_cpadd
PARAMS ((int));
641 static void s_insn
PARAMS ((int));
642 static void md_obj_begin
PARAMS ((void));
643 static void md_obj_end
PARAMS ((void));
644 static long get_number
PARAMS ((void));
645 static void s_ent
PARAMS ((int));
646 static void s_mipsend
PARAMS ((int));
647 static void s_file
PARAMS ((int));
648 static void s_mips_stab
PARAMS ((int));
649 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
651 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
655 The following pseudo-ops from the Kane and Heinrich MIPS book
656 should be defined here, but are currently unsupported: .alias,
657 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
659 The following pseudo-ops from the Kane and Heinrich MIPS book are
660 specific to the type of debugging information being generated, and
661 should be defined by the object format: .aent, .begin, .bend,
662 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
665 The following pseudo-ops from the Kane and Heinrich MIPS book are
666 not MIPS CPU specific, but are also not specific to the object file
667 format. This file is probably the best place to define them, but
668 they are not currently supported: .asm0, .endr, .lab, .repeat,
669 .struct, .weakext. */
671 static const pseudo_typeS mips_pseudo_table
[] =
673 /* MIPS specific pseudo-ops. */
674 {"option", s_option
, 0},
675 {"set", s_mipsset
, 0},
676 {"rdata", s_change_sec
, 'r'},
677 {"sdata", s_change_sec
, 's'},
678 {"livereg", s_ignore
, 0},
679 {"abicalls", s_abicalls
, 0},
680 {"cpload", s_cpload
, 0},
681 {"cprestore", s_cprestore
, 0},
682 {"gpword", s_gpword
, 0},
683 {"cpadd", s_cpadd
, 0},
686 /* Relatively generic pseudo-ops that happen to be used on MIPS
688 {"asciiz", stringer
, 1},
689 {"bss", s_change_sec
, 'b'},
692 {"dword", s_cons
, 3},
694 /* These pseudo-ops are defined in read.c, but must be overridden
695 here for one reason or another. */
696 {"align", s_align
, 0},
698 {"data", s_change_sec
, 'd'},
699 {"double", s_float_cons
, 'd'},
700 {"float", s_float_cons
, 'f'},
701 {"globl", s_mips_globl
, 0},
702 {"global", s_mips_globl
, 0},
703 {"hword", s_cons
, 1},
708 {"short", s_cons
, 1},
709 {"single", s_float_cons
, 'f'},
710 {"stabn", s_mips_stab
, 'n'},
711 {"text", s_change_sec
, 't'},
716 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
717 /* These pseudo-ops should be defined by the object file format.
718 However, a.out doesn't support them, so we have versions here. */
720 {"bgnb", s_ignore
, 0},
721 {"end", s_mipsend
, 0},
722 {"endb", s_ignore
, 0},
725 {"fmask", s_ignore
, 'F'},
726 {"frame", s_ignore
, 0},
727 {"loc", s_ignore
, 0},
728 {"mask", s_ignore
, 'R'},
729 {"verstamp", s_ignore
, 0},
733 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
738 pop_insert (mips_pseudo_table
);
739 if (! ECOFF_DEBUGGING
)
740 pop_insert (mips_nonecoff_pseudo_table
);
743 /* Symbols labelling the current insn. */
745 struct insn_label_list
747 struct insn_label_list
*next
;
751 static struct insn_label_list
*insn_labels
;
752 static struct insn_label_list
*free_insn_labels
;
754 static void mips_clear_insn_labels
PARAMS ((void));
757 mips_clear_insn_labels ()
759 register struct insn_label_list
**pl
;
761 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
767 static char *expr_end
;
769 /* Expressions which appear in instructions. These are set by
772 static expressionS imm_expr
;
773 static expressionS offset_expr
;
775 /* Relocs associated with imm_expr and offset_expr. */
777 static bfd_reloc_code_real_type imm_reloc
;
778 static bfd_reloc_code_real_type offset_reloc
;
780 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
782 static boolean imm_unmatched_hi
;
784 /* These are set by mips16_ip if an explicit extension is used. */
786 static boolean mips16_small
, mips16_ext
;
789 * This function is called once, at assembler startup time. It should
790 * set up all the tables, etc. that the MD part of the assembler will need.
796 register const char *retval
= NULL
;
797 register unsigned int i
= 0;
800 if (mips_opts
.isa
== -1)
806 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
808 a
= xmalloc (sizeof TARGET_CPU
);
809 strcpy (a
, TARGET_CPU
);
810 a
[(sizeof TARGET_CPU
) - 3] = '\0';
814 if (strcmp (cpu
, "mips") == 0)
820 else if (strcmp (cpu
, "r3900") == 0
821 || strcmp (cpu
, "mipstx39") == 0
822 /* start-sanitize-tx19 */
823 || strcmp (cpu
, "r1900") == 0
824 || strcmp (cpu
, "mipstx19") == 0
825 /* end-sanitize-tx19 */
834 else if (strcmp (cpu
, "r6000") == 0
835 || strcmp (cpu
, "mips2") == 0)
841 else if (strcmp (cpu
, "mips64") == 0
842 || strcmp (cpu
, "r4000") == 0
843 || strcmp (cpu
, "mips3") == 0)
849 else if (strcmp (cpu
, "r4400") == 0)
855 else if (strcmp (cpu
, "mips64orion") == 0
856 || strcmp (cpu
, "r4600") == 0)
862 else if (strcmp (cpu
, "r4650") == 0)
870 else if (strcmp (cpu
, "mips64vr4300") == 0)
876 else if (strcmp (cpu
, "mips64vr4100") == 0)
884 else if (strcmp (cpu
, "r4010") == 0)
892 /* start-sanitize-tx49 */
893 else if (strcmp (cpu
, "mips64tx49") == 0)
899 /* end-sanitize-tx49 */
900 else if (strcmp (cpu
, "r5000") == 0
901 || strcmp (cpu
, "mips64vr5000") == 0)
907 /* start-sanitize-vr5400 */
908 else if (strcmp (cpu
, "r5400") == 0
909 || strcmp (cpu
, "mips64r5400") == 0
910 || strcmp (cpu
, "mips64r5400el") == 0)
918 /* end-sanitize-vr5400 */
919 /* start-sanitize-r5900 */
920 else if (strcmp (cpu
, "r5900") == 0
921 || strcmp (cpu
, "mips64r5900") == 0
922 || strcmp (cpu
, "mips64r5900el") == 0)
930 /* end-sanitize-r5900 */
931 else if (strcmp (cpu
, "r8000") == 0
932 || strcmp (cpu
, "mips4") == 0)
938 else if (strcmp (cpu
, "r10000") == 0)
944 else if (strcmp (cpu
, "mips16") == 0)
948 mips_cpu
= 0; /* FIXME */
961 if (mips_opts
.mips16
< 0)
963 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
964 mips_opts
.mips16
= 1;
966 mips_opts
.mips16
= 0;
978 /* start-sanitize-vr5400 */
982 /* end-sanitize-vr5400 */
983 /* start-sanitize-r5900 */
987 /* end-sanitize-r5900 */
991 if (mips_opts
.isa
< 2 && mips_trap
)
992 as_bad ("trap exception not supported at ISA 1");
994 switch (mips_opts
.isa
)
997 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1000 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1003 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1006 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1010 as_warn ("Could not set architecture and machine");
1012 file_mips_isa
= mips_opts
.isa
;
1014 op_hash
= hash_new ();
1016 for (i
= 0; i
< NUMOPCODES
;)
1018 const char *name
= mips_opcodes
[i
].name
;
1020 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1023 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
1024 mips_opcodes
[i
].name
, retval
);
1025 /* Probably a memory allocation problem? Give up now. */
1026 as_fatal ("Broken assembler. No assembly attempted.");
1030 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1032 if (!validate_mips_insn (&mips_opcodes
[i
]))
1037 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1040 mips16_op_hash
= hash_new ();
1043 while (i
< bfd_mips16_num_opcodes
)
1045 const char *name
= mips16_opcodes
[i
].name
;
1047 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1049 as_fatal ("internal: can't hash `%s': %s",
1050 mips16_opcodes
[i
].name
, retval
);
1053 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1054 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1055 != mips16_opcodes
[i
].match
))
1057 fprintf (stderr
, "internal error: bad mips16 opcode: %s %s\n",
1058 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1063 while (i
< bfd_mips16_num_opcodes
1064 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1068 as_fatal ("Broken assembler. No assembly attempted.");
1070 /* We add all the general register names to the symbol table. This
1071 helps us detect invalid uses of them. */
1072 for (i
= 0; i
< 32; i
++)
1076 sprintf (buf
, "$%d", i
);
1077 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1078 &zero_address_frag
));
1080 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1081 &zero_address_frag
));
1082 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1083 &zero_address_frag
));
1084 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1085 &zero_address_frag
));
1086 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1087 &zero_address_frag
));
1088 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1089 &zero_address_frag
));
1090 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1091 &zero_address_frag
));
1092 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1093 &zero_address_frag
));
1095 mips_no_prev_insn (false);
1098 mips_cprmask
[0] = 0;
1099 mips_cprmask
[1] = 0;
1100 mips_cprmask
[2] = 0;
1101 mips_cprmask
[3] = 0;
1103 /* set the default alignment for the text section (2**2) */
1104 record_alignment (text_section
, 2);
1106 if (USE_GLOBAL_POINTER_OPT
)
1107 bfd_set_gp_size (stdoutput
, g_switch_value
);
1109 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1111 /* On a native system, sections must be aligned to 16 byte
1112 boundaries. When configured for an embedded ELF target, we
1114 if (strcmp (TARGET_OS
, "elf") != 0)
1116 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1117 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1118 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1121 /* Create a .reginfo section for register masks and a .mdebug
1122 section for debugging information. */
1130 subseg
= now_subseg
;
1132 /* The ABI says this section should be loaded so that the
1133 running program can access it. However, we don't load it
1134 if we are configured for an embedded target */
1135 flags
= SEC_READONLY
| SEC_DATA
;
1136 if (strcmp (TARGET_OS
, "elf") != 0)
1137 flags
|= SEC_ALLOC
| SEC_LOAD
;
1141 sec
= subseg_new (".reginfo", (subsegT
) 0);
1144 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1145 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1148 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1153 /* The 64-bit ABI uses a .MIPS.options section rather than
1154 .reginfo section. */
1155 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1156 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1157 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1160 /* Set up the option header. */
1162 Elf_Internal_Options opthdr
;
1165 opthdr
.kind
= ODK_REGINFO
;
1166 opthdr
.size
= (sizeof (Elf_External_Options
)
1167 + sizeof (Elf64_External_RegInfo
));
1170 f
= frag_more (sizeof (Elf_External_Options
));
1171 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1172 (Elf_External_Options
*) f
);
1174 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1179 if (ECOFF_DEBUGGING
)
1181 sec
= subseg_new (".mdebug", (subsegT
) 0);
1182 (void) bfd_set_section_flags (stdoutput
, sec
,
1183 SEC_HAS_CONTENTS
| SEC_READONLY
);
1184 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1187 subseg_set (seg
, subseg
);
1191 if (! ECOFF_DEBUGGING
)
1198 if (! ECOFF_DEBUGGING
)
1206 struct mips_cl_insn insn
;
1208 imm_expr
.X_op
= O_absent
;
1209 imm_reloc
= BFD_RELOC_UNUSED
;
1210 imm_unmatched_hi
= false;
1211 offset_expr
.X_op
= O_absent
;
1212 offset_reloc
= BFD_RELOC_UNUSED
;
1214 if (mips_opts
.mips16
)
1215 mips16_ip (str
, &insn
);
1218 mips_ip (str
, &insn
);
1219 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1220 str
, insn
.insn_opcode
));
1225 as_bad ("%s `%s'", insn_error
, str
);
1229 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1231 if (mips_opts
.mips16
)
1232 mips16_macro (&insn
);
1238 if (imm_expr
.X_op
!= O_absent
)
1239 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1241 else if (offset_expr
.X_op
!= O_absent
)
1242 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1244 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1248 /* See whether instruction IP reads register REG. CLASS is the type
1252 insn_uses_reg (ip
, reg
, class)
1253 struct mips_cl_insn
*ip
;
1255 enum mips_regclass
class;
1257 if (class == MIPS16_REG
)
1259 assert (mips_opts
.mips16
);
1260 reg
= mips16_to_32_reg_map
[reg
];
1261 class = MIPS_GR_REG
;
1264 /* Don't report on general register 0, since it never changes. */
1265 if (class == MIPS_GR_REG
&& reg
== 0)
1268 if (class == MIPS_FP_REG
)
1270 assert (! mips_opts
.mips16
);
1271 /* If we are called with either $f0 or $f1, we must check $f0.
1272 This is not optimal, because it will introduce an unnecessary
1273 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1274 need to distinguish reading both $f0 and $f1 or just one of
1275 them. Note that we don't have to check the other way,
1276 because there is no instruction that sets both $f0 and $f1
1277 and requires a delay. */
1278 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1279 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1280 == (reg
&~ (unsigned) 1)))
1282 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1283 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1284 == (reg
&~ (unsigned) 1)))
1287 else if (! mips_opts
.mips16
)
1289 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1290 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1292 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1293 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1298 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1299 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1300 & MIPS16OP_MASK_RX
)]
1303 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1304 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1305 & MIPS16OP_MASK_RY
)]
1308 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1309 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1310 & MIPS16OP_MASK_MOVE32Z
)]
1313 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1315 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1317 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1319 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1320 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1321 & MIPS16OP_MASK_REGR32
) == reg
)
1328 /* This function returns true if modifying a register requires a
1332 reg_needs_delay (reg
)
1335 unsigned long prev_pinfo
;
1337 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1338 if (! mips_opts
.noreorder
1339 && mips_opts
.isa
< 4
1340 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1341 || (! gpr_interlocks
1342 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1344 /* A load from a coprocessor or from memory. All load
1345 delays delay the use of general register rt for one
1346 instruction on the r3000. The r6000 and r4000 use
1348 /* Itbl support may require additional care here. */
1349 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1350 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1357 /* Mark instruction labels in mips16 mode. This permits the linker to
1358 handle them specially, such as generating jalx instructions when
1359 needed. We also make them odd for the duration of the assembly, in
1360 order to generate the right sort of code. We will make them even
1361 in the adjust_symtab routine, while leaving them marked. This is
1362 convenient for the debugger and the disassembler. The linker knows
1363 to make them odd again. */
1366 mips16_mark_labels ()
1368 if (mips_opts
.mips16
)
1370 struct insn_label_list
*l
;
1372 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1375 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1376 S_SET_OTHER (l
->label
, STO_MIPS16
);
1378 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1379 ++l
->label
->sy_value
.X_add_number
;
1384 /* Output an instruction. PLACE is where to put the instruction; if
1385 it is NULL, this uses frag_more to get room. IP is the instruction
1386 information. ADDRESS_EXPR is an operand of the instruction to be
1387 used with RELOC_TYPE. */
1390 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1392 struct mips_cl_insn
*ip
;
1393 expressionS
*address_expr
;
1394 bfd_reloc_code_real_type reloc_type
;
1395 boolean unmatched_hi
;
1397 register unsigned long prev_pinfo
, pinfo
;
1402 /* Mark instruction labels in mips16 mode. */
1403 if (mips_opts
.mips16
)
1404 mips16_mark_labels ();
1406 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1407 pinfo
= ip
->insn_mo
->pinfo
;
1409 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1413 /* If the previous insn required any delay slots, see if we need
1414 to insert a NOP or two. There are eight kinds of possible
1415 hazards, of which an instruction can have at most one type.
1416 (1) a load from memory delay
1417 (2) a load from a coprocessor delay
1418 (3) an unconditional branch delay
1419 (4) a conditional branch delay
1420 (5) a move to coprocessor register delay
1421 (6) a load coprocessor register from memory delay
1422 (7) a coprocessor condition code delay
1423 (8) a HI/LO special register delay
1425 There are a lot of optimizations we could do that we don't.
1426 In particular, we do not, in general, reorder instructions.
1427 If you use gcc with optimization, it will reorder
1428 instructions and generally do much more optimization then we
1429 do here; repeating all that work in the assembler would only
1430 benefit hand written assembly code, and does not seem worth
1433 /* This is how a NOP is emitted. */
1434 #define emit_nop() \
1436 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1437 : md_number_to_chars (frag_more (4), 0, 4))
1439 /* The previous insn might require a delay slot, depending upon
1440 the contents of the current insn. */
1441 if (! mips_opts
.mips16
1442 && mips_opts
.isa
< 4
1443 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1444 && ! cop_interlocks
)
1445 || (! gpr_interlocks
1446 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1448 /* A load from a coprocessor or from memory. All load
1449 delays delay the use of general register rt for one
1450 instruction on the r3000. The r6000 and r4000 use
1452 /* Itbl support may require additional care here. */
1453 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1454 if (mips_optimize
== 0
1455 || insn_uses_reg (ip
,
1456 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1461 else if (! mips_opts
.mips16
1462 && mips_opts
.isa
< 4
1463 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1464 && ! cop_interlocks
)
1465 || (mips_opts
.isa
< 2
1466 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1468 /* A generic coprocessor delay. The previous instruction
1469 modified a coprocessor general or control register. If
1470 it modified a control register, we need to avoid any
1471 coprocessor instruction (this is probably not always
1472 required, but it sometimes is). If it modified a general
1473 register, we avoid using that register.
1475 On the r6000 and r4000 loading a coprocessor register
1476 from memory is interlocked, and does not require a delay.
1478 This case is not handled very well. There is no special
1479 knowledge of CP0 handling, and the coprocessors other
1480 than the floating point unit are not distinguished at
1482 /* Itbl support may require additional care here. FIXME!
1483 Need to modify this to include knowledge about
1484 user specified delays! */
1485 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1487 if (mips_optimize
== 0
1488 || insn_uses_reg (ip
,
1489 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1494 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1496 if (mips_optimize
== 0
1497 || insn_uses_reg (ip
,
1498 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1505 /* We don't know exactly what the previous instruction
1506 does. If the current instruction uses a coprocessor
1507 register, we must insert a NOP. If previous
1508 instruction may set the condition codes, and the
1509 current instruction uses them, we must insert two
1511 /* Itbl support may require additional care here. */
1512 if (mips_optimize
== 0
1513 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1514 && (pinfo
& INSN_READ_COND_CODE
)))
1516 else if (pinfo
& INSN_COP
)
1520 else if (! mips_opts
.mips16
1521 && mips_opts
.isa
< 4
1522 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1523 && ! cop_interlocks
)
1525 /* The previous instruction sets the coprocessor condition
1526 codes, but does not require a general coprocessor delay
1527 (this means it is a floating point comparison
1528 instruction). If this instruction uses the condition
1529 codes, we need to insert a single NOP. */
1530 /* Itbl support may require additional care here. */
1531 if (mips_optimize
== 0
1532 || (pinfo
& INSN_READ_COND_CODE
))
1535 else if (prev_pinfo
& INSN_READ_LO
)
1537 /* The previous instruction reads the LO register; if the
1538 current instruction writes to the LO register, we must
1539 insert two NOPS. Some newer processors have interlocks. */
1540 if (! hilo_interlocks
1541 && (mips_optimize
== 0
1542 || (pinfo
& INSN_WRITE_LO
)))
1545 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1547 /* The previous instruction reads the HI register; if the
1548 current instruction writes to the HI register, we must
1549 insert a NOP. Some newer processors have interlocks. */
1550 if (! hilo_interlocks
1551 && (mips_optimize
== 0
1552 || (pinfo
& INSN_WRITE_HI
)))
1556 /* If the previous instruction was in a noreorder section, then
1557 we don't want to insert the nop after all. */
1558 /* Itbl support may require additional care here. */
1559 if (prev_insn_unreordered
)
1562 /* There are two cases which require two intervening
1563 instructions: 1) setting the condition codes using a move to
1564 coprocessor instruction which requires a general coprocessor
1565 delay and then reading the condition codes 2) reading the HI
1566 or LO register and then writing to it (except on processors
1567 which have interlocks). If we are not already emitting a NOP
1568 instruction, we must check for these cases compared to the
1569 instruction previous to the previous instruction. */
1570 if ((! mips_opts
.mips16
1571 && mips_opts
.isa
< 4
1572 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1573 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1574 && (pinfo
& INSN_READ_COND_CODE
)
1575 && ! cop_interlocks
)
1576 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1577 && (pinfo
& INSN_WRITE_LO
)
1578 && ! hilo_interlocks
)
1579 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1580 && (pinfo
& INSN_WRITE_HI
)
1581 && ! hilo_interlocks
))
1586 if (prev_prev_insn_unreordered
)
1589 if (prev_prev_nop
&& nops
== 0)
1592 /* If we are being given a nop instruction, don't bother with
1593 one of the nops we would otherwise output. This will only
1594 happen when a nop instruction is used with mips_optimize set
1597 && ! mips_opts
.noreorder
1598 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1601 /* Now emit the right number of NOP instructions. */
1602 if (nops
> 0 && ! mips_opts
.noreorder
)
1605 unsigned long old_frag_offset
;
1607 struct insn_label_list
*l
;
1609 old_frag
= frag_now
;
1610 old_frag_offset
= frag_now_fix ();
1612 for (i
= 0; i
< nops
; i
++)
1617 listing_prev_line ();
1618 /* We may be at the start of a variant frag. In case we
1619 are, make sure there is enough space for the frag
1620 after the frags created by listing_prev_line. The
1621 argument to frag_grow here must be at least as large
1622 as the argument to all other calls to frag_grow in
1623 this file. We don't have to worry about being in the
1624 middle of a variant frag, because the variants insert
1625 all needed nop instructions themselves. */
1629 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1631 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1632 l
->label
->sy_frag
= frag_now
;
1633 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1634 /* mips16 text labels are stored as odd. */
1635 if (mips_opts
.mips16
)
1636 ++l
->label
->sy_value
.X_add_number
;
1639 #ifndef NO_ECOFF_DEBUGGING
1640 if (ECOFF_DEBUGGING
)
1641 ecoff_fix_loc (old_frag
, old_frag_offset
);
1644 else if (prev_nop_frag
!= NULL
)
1646 /* We have a frag holding nops we may be able to remove. If
1647 we don't need any nops, we can decrease the size of
1648 prev_nop_frag by the size of one instruction. If we do
1649 need some nops, we count them in prev_nops_required. */
1650 if (prev_nop_frag_since
== 0)
1654 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1655 --prev_nop_frag_holds
;
1658 prev_nop_frag_required
+= nops
;
1662 if (prev_prev_nop
== 0)
1664 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1665 --prev_nop_frag_holds
;
1668 ++prev_nop_frag_required
;
1671 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1672 prev_nop_frag
= NULL
;
1674 ++prev_nop_frag_since
;
1676 /* Sanity check: by the time we reach the second instruction
1677 after prev_nop_frag, we should have used up all the nops
1678 one way or another. */
1679 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1683 if (reloc_type
> BFD_RELOC_UNUSED
)
1685 /* We need to set up a variant frag. */
1686 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1687 f
= frag_var (rs_machine_dependent
, 4, 0,
1688 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1689 mips16_small
, mips16_ext
,
1691 & INSN_UNCOND_BRANCH_DELAY
),
1692 (prev_insn_reloc_type
1693 == BFD_RELOC_MIPS16_JMP
)),
1694 make_expr_symbol (address_expr
), (offsetT
) 0,
1697 else if (place
!= NULL
)
1699 else if (mips_opts
.mips16
1701 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1703 /* Make sure there is enough room to swap this instruction with
1704 a following jump instruction. */
1710 if (mips_opts
.mips16
1711 && mips_opts
.noreorder
1712 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1713 as_warn ("extended instruction in delay slot");
1719 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1721 if (address_expr
->X_op
== O_constant
)
1726 ip
->insn_opcode
|= address_expr
->X_add_number
;
1729 case BFD_RELOC_LO16
:
1730 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1733 case BFD_RELOC_MIPS_JMP
:
1734 if ((address_expr
->X_add_number
& 3) != 0)
1735 as_bad ("jump to misaligned address (0x%lx)",
1736 (unsigned long) address_expr
->X_add_number
);
1737 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1740 case BFD_RELOC_MIPS16_JMP
:
1741 if ((address_expr
->X_add_number
& 3) != 0)
1742 as_bad ("jump to misaligned address (0x%lx)",
1743 (unsigned long) address_expr
->X_add_number
);
1745 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1746 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1747 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1750 case BFD_RELOC_16_PCREL_S2
:
1760 /* Don't generate a reloc if we are writing into a variant
1764 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1766 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1770 struct mips_hi_fixup
*hi_fixup
;
1772 assert (reloc_type
== BFD_RELOC_HI16_S
);
1773 hi_fixup
= ((struct mips_hi_fixup
*)
1774 xmalloc (sizeof (struct mips_hi_fixup
)));
1775 hi_fixup
->fixp
= fixp
;
1776 hi_fixup
->seg
= now_seg
;
1777 hi_fixup
->next
= mips_hi_fixup_list
;
1778 mips_hi_fixup_list
= hi_fixup
;
1784 if (! mips_opts
.mips16
)
1785 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1786 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1788 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1789 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1795 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1798 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1801 /* Update the register mask information. */
1802 if (! mips_opts
.mips16
)
1804 if (pinfo
& INSN_WRITE_GPR_D
)
1805 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1806 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1807 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1808 if (pinfo
& INSN_READ_GPR_S
)
1809 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1810 if (pinfo
& INSN_WRITE_GPR_31
)
1811 mips_gprmask
|= 1 << 31;
1812 if (pinfo
& INSN_WRITE_FPR_D
)
1813 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1814 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1815 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1816 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1817 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1818 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1819 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1820 if (pinfo
& INSN_COP
)
1822 /* We don't keep enough information to sort these cases out.
1823 The itbl support does keep this information however, although
1824 we currently don't support itbl fprmats as part of the cop
1825 instruction. May want to add this support in the future. */
1827 /* Never set the bit for $0, which is always zero. */
1828 mips_gprmask
&=~ 1 << 0;
1832 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1833 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1834 & MIPS16OP_MASK_RX
);
1835 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1836 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1837 & MIPS16OP_MASK_RY
);
1838 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1839 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1840 & MIPS16OP_MASK_RZ
);
1841 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1842 mips_gprmask
|= 1 << TREG
;
1843 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1844 mips_gprmask
|= 1 << SP
;
1845 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1846 mips_gprmask
|= 1 << RA
;
1847 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1848 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1849 if (pinfo
& MIPS16_INSN_READ_Z
)
1850 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1851 & MIPS16OP_MASK_MOVE32Z
);
1852 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1853 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1854 & MIPS16OP_MASK_REGR32
);
1857 if (place
== NULL
&& ! mips_opts
.noreorder
)
1859 /* Filling the branch delay slot is more complex. We try to
1860 switch the branch with the previous instruction, which we can
1861 do if the previous instruction does not set up a condition
1862 that the branch tests and if the branch is not itself the
1863 target of any branch. */
1864 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1865 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1867 if (mips_optimize
< 2
1868 /* If we have seen .set volatile or .set nomove, don't
1870 || mips_opts
.nomove
!= 0
1871 /* If we had to emit any NOP instructions, then we
1872 already know we can not swap. */
1874 /* If we don't even know the previous insn, we can not
1876 || ! prev_insn_valid
1877 /* If the previous insn is already in a branch delay
1878 slot, then we can not swap. */
1879 || prev_insn_is_delay_slot
1880 /* If the previous previous insn was in a .set
1881 noreorder, we can't swap. Actually, the MIPS
1882 assembler will swap in this situation. However, gcc
1883 configured -with-gnu-as will generate code like
1889 in which we can not swap the bne and INSN. If gcc is
1890 not configured -with-gnu-as, it does not output the
1891 .set pseudo-ops. We don't have to check
1892 prev_insn_unreordered, because prev_insn_valid will
1893 be 0 in that case. We don't want to use
1894 prev_prev_insn_valid, because we do want to be able
1895 to swap at the start of a function. */
1896 || prev_prev_insn_unreordered
1897 /* If the branch is itself the target of a branch, we
1898 can not swap. We cheat on this; all we check for is
1899 whether there is a label on this instruction. If
1900 there are any branches to anything other than a
1901 label, users must use .set noreorder. */
1902 || insn_labels
!= NULL
1903 /* If the previous instruction is in a variant frag, we
1904 can not do the swap. This does not apply to the
1905 mips16, which uses variant frags for different
1907 || (! mips_opts
.mips16
1908 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1909 /* If the branch reads the condition codes, we don't
1910 even try to swap, because in the sequence
1915 we can not swap, and I don't feel like handling that
1917 || (! mips_opts
.mips16
1918 && mips_opts
.isa
< 4
1919 && (pinfo
& INSN_READ_COND_CODE
))
1920 /* We can not swap with an instruction that requires a
1921 delay slot, becase the target of the branch might
1922 interfere with that instruction. */
1923 || (! mips_opts
.mips16
1924 && mips_opts
.isa
< 4
1926 /* Itbl support may require additional care here. */
1927 & (INSN_LOAD_COPROC_DELAY
1928 | INSN_COPROC_MOVE_DELAY
1929 | INSN_WRITE_COND_CODE
)))
1930 || (! hilo_interlocks
1934 || (! mips_opts
.mips16
1936 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1937 || (! mips_opts
.mips16
1938 && mips_opts
.isa
< 2
1939 /* Itbl support may require additional care here. */
1940 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1941 /* We can not swap with a branch instruction. */
1943 & (INSN_UNCOND_BRANCH_DELAY
1944 | INSN_COND_BRANCH_DELAY
1945 | INSN_COND_BRANCH_LIKELY
))
1946 /* We do not swap with a trap instruction, since it
1947 complicates trap handlers to have the trap
1948 instruction be in a delay slot. */
1949 || (prev_pinfo
& INSN_TRAP
)
1950 /* If the branch reads a register that the previous
1951 instruction sets, we can not swap. */
1952 || (! mips_opts
.mips16
1953 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1954 && insn_uses_reg (ip
,
1955 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1958 || (! mips_opts
.mips16
1959 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1960 && insn_uses_reg (ip
,
1961 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1964 || (mips_opts
.mips16
1965 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1966 && insn_uses_reg (ip
,
1967 ((prev_insn
.insn_opcode
1969 & MIPS16OP_MASK_RX
),
1971 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1972 && insn_uses_reg (ip
,
1973 ((prev_insn
.insn_opcode
1975 & MIPS16OP_MASK_RY
),
1977 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1978 && insn_uses_reg (ip
,
1979 ((prev_insn
.insn_opcode
1981 & MIPS16OP_MASK_RZ
),
1983 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1984 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1985 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1986 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1987 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1988 && insn_uses_reg (ip
,
1989 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1992 /* If the branch writes a register that the previous
1993 instruction sets, we can not swap (we know that
1994 branches write only to RD or to $31). */
1995 || (! mips_opts
.mips16
1996 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1997 && (((pinfo
& INSN_WRITE_GPR_D
)
1998 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1999 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2000 || ((pinfo
& INSN_WRITE_GPR_31
)
2001 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2004 || (! mips_opts
.mips16
2005 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2006 && (((pinfo
& INSN_WRITE_GPR_D
)
2007 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2008 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2009 || ((pinfo
& INSN_WRITE_GPR_31
)
2010 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2013 || (mips_opts
.mips16
2014 && (pinfo
& MIPS16_INSN_WRITE_31
)
2015 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2016 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2017 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2019 /* If the branch writes a register that the previous
2020 instruction reads, we can not swap (we know that
2021 branches only write to RD or to $31). */
2022 || (! mips_opts
.mips16
2023 && (pinfo
& INSN_WRITE_GPR_D
)
2024 && insn_uses_reg (&prev_insn
,
2025 ((ip
->insn_opcode
>> OP_SH_RD
)
2028 || (! mips_opts
.mips16
2029 && (pinfo
& INSN_WRITE_GPR_31
)
2030 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2031 || (mips_opts
.mips16
2032 && (pinfo
& MIPS16_INSN_WRITE_31
)
2033 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2034 /* If we are generating embedded PIC code, the branch
2035 might be expanded into a sequence which uses $at, so
2036 we can't swap with an instruction which reads it. */
2037 || (mips_pic
== EMBEDDED_PIC
2038 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2039 /* If the previous previous instruction has a load
2040 delay, and sets a register that the branch reads, we
2042 || (! mips_opts
.mips16
2043 && mips_opts
.isa
< 4
2044 /* Itbl support may require additional care here. */
2045 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2046 || (! gpr_interlocks
2047 && (prev_prev_insn
.insn_mo
->pinfo
2048 & INSN_LOAD_MEMORY_DELAY
)))
2049 && insn_uses_reg (ip
,
2050 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2053 /* If one instruction sets a condition code and the
2054 other one uses a condition code, we can not swap. */
2055 || ((pinfo
& INSN_READ_COND_CODE
)
2056 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2057 || ((pinfo
& INSN_WRITE_COND_CODE
)
2058 && (prev_pinfo
& INSN_READ_COND_CODE
))
2059 /* If the previous instruction uses the PC, we can not
2061 || (mips_opts
.mips16
2062 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2063 /* If the previous instruction was extended, we can not
2065 || (mips_opts
.mips16
&& prev_insn_extended
)
2066 /* If the previous instruction had a fixup in mips16
2067 mode, we can not swap. This normally means that the
2068 previous instruction was a 4 byte branch anyhow. */
2069 || (mips_opts
.mips16
&& prev_insn_fixp
))
2071 /* We could do even better for unconditional branches to
2072 portions of this object file; we could pick up the
2073 instruction at the destination, put it in the delay
2074 slot, and bump the destination address. */
2076 /* Update the previous insn information. */
2077 prev_prev_insn
= *ip
;
2078 prev_insn
.insn_mo
= &dummy_opcode
;
2082 /* It looks like we can actually do the swap. */
2083 if (! mips_opts
.mips16
)
2088 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2089 memcpy (temp
, prev_f
, 4);
2090 memcpy (prev_f
, f
, 4);
2091 memcpy (f
, temp
, 4);
2094 prev_insn_fixp
->fx_frag
= frag_now
;
2095 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2099 fixp
->fx_frag
= prev_insn_frag
;
2100 fixp
->fx_where
= prev_insn_where
;
2108 assert (prev_insn_fixp
== NULL
);
2109 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2110 memcpy (temp
, prev_f
, 2);
2111 memcpy (prev_f
, f
, 2);
2112 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2114 assert (reloc_type
== BFD_RELOC_UNUSED
);
2115 memcpy (f
, temp
, 2);
2119 memcpy (f
, f
+ 2, 2);
2120 memcpy (f
+ 2, temp
, 2);
2124 fixp
->fx_frag
= prev_insn_frag
;
2125 fixp
->fx_where
= prev_insn_where
;
2129 /* Update the previous insn information; leave prev_insn
2131 prev_prev_insn
= *ip
;
2133 prev_insn_is_delay_slot
= 1;
2135 /* If that was an unconditional branch, forget the previous
2136 insn information. */
2137 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2139 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2140 prev_insn
.insn_mo
= &dummy_opcode
;
2143 prev_insn_fixp
= NULL
;
2144 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2145 prev_insn_extended
= 0;
2147 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2149 /* We don't yet optimize a branch likely. What we should do
2150 is look at the target, copy the instruction found there
2151 into the delay slot, and increment the branch to jump to
2152 the next instruction. */
2154 /* Update the previous insn information. */
2155 prev_prev_insn
= *ip
;
2156 prev_insn
.insn_mo
= &dummy_opcode
;
2157 prev_insn_fixp
= NULL
;
2158 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2159 prev_insn_extended
= 0;
2163 /* Update the previous insn information. */
2165 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2167 prev_prev_insn
= prev_insn
;
2170 /* Any time we see a branch, we always fill the delay slot
2171 immediately; since this insn is not a branch, we know it
2172 is not in a delay slot. */
2173 prev_insn_is_delay_slot
= 0;
2175 prev_insn_fixp
= fixp
;
2176 prev_insn_reloc_type
= reloc_type
;
2177 if (mips_opts
.mips16
)
2178 prev_insn_extended
= (ip
->use_extend
2179 || reloc_type
> BFD_RELOC_UNUSED
);
2182 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2183 prev_insn_unreordered
= 0;
2184 prev_insn_frag
= frag_now
;
2185 prev_insn_where
= f
- frag_now
->fr_literal
;
2186 prev_insn_valid
= 1;
2188 else if (place
== NULL
)
2190 /* We need to record a bit of information even when we are not
2191 reordering, in order to determine the base address for mips16
2192 PC relative relocs. */
2193 prev_prev_insn
= prev_insn
;
2195 prev_insn_reloc_type
= reloc_type
;
2196 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2197 prev_insn_unreordered
= 1;
2200 /* We just output an insn, so the next one doesn't have a label. */
2201 mips_clear_insn_labels ();
2204 /* This function forgets that there was any previous instruction or
2205 label. If PRESERVE is non-zero, it remembers enough information to
2206 know whether nops are needed before a noreorder section. */
2209 mips_no_prev_insn (preserve
)
2214 prev_insn
.insn_mo
= &dummy_opcode
;
2215 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2216 prev_nop_frag
= NULL
;
2217 prev_nop_frag_holds
= 0;
2218 prev_nop_frag_required
= 0;
2219 prev_nop_frag_since
= 0;
2221 prev_insn_valid
= 0;
2222 prev_insn_is_delay_slot
= 0;
2223 prev_insn_unreordered
= 0;
2224 prev_insn_extended
= 0;
2225 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2226 prev_prev_insn_unreordered
= 0;
2227 mips_clear_insn_labels ();
2230 /* This function must be called whenever we turn on noreorder or emit
2231 something other than instructions. It inserts any NOPS which might
2232 be needed by the previous instruction, and clears the information
2233 kept for the previous instructions. The INSNS parameter is true if
2234 instructions are to follow. */
2237 mips_emit_delays (insns
)
2240 if (! mips_opts
.noreorder
)
2245 if ((! mips_opts
.mips16
2246 && mips_opts
.isa
< 4
2247 && (! cop_interlocks
2248 && (prev_insn
.insn_mo
->pinfo
2249 & (INSN_LOAD_COPROC_DELAY
2250 | INSN_COPROC_MOVE_DELAY
2251 | INSN_WRITE_COND_CODE
))))
2252 || (! hilo_interlocks
2253 && (prev_insn
.insn_mo
->pinfo
2256 || (! mips_opts
.mips16
2258 && (prev_insn
.insn_mo
->pinfo
2259 & INSN_LOAD_MEMORY_DELAY
))
2260 || (! mips_opts
.mips16
2261 && mips_opts
.isa
< 2
2262 && (prev_insn
.insn_mo
->pinfo
2263 & INSN_COPROC_MEMORY_DELAY
)))
2265 /* Itbl support may require additional care here. */
2267 if ((! mips_opts
.mips16
2268 && mips_opts
.isa
< 4
2269 && (! cop_interlocks
2270 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2271 || (! hilo_interlocks
2272 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2273 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2276 if (prev_insn_unreordered
)
2279 else if ((! mips_opts
.mips16
2280 && mips_opts
.isa
< 4
2281 && (! cop_interlocks
2282 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2283 || (! hilo_interlocks
2284 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2285 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2287 /* Itbl support may require additional care here. */
2288 if (! prev_prev_insn_unreordered
)
2294 struct insn_label_list
*l
;
2298 /* Record the frag which holds the nop instructions, so
2299 that we can remove them if we don't need them. */
2300 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2301 prev_nop_frag
= frag_now
;
2302 prev_nop_frag_holds
= nops
;
2303 prev_nop_frag_required
= 0;
2304 prev_nop_frag_since
= 0;
2307 for (; nops
> 0; --nops
)
2312 /* Move on to a new frag, so that it is safe to simply
2313 decrease the size of prev_nop_frag. */
2314 frag_wane (frag_now
);
2318 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2320 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2321 l
->label
->sy_frag
= frag_now
;
2322 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2323 /* mips16 text labels are stored as odd. */
2324 if (mips_opts
.mips16
)
2325 ++l
->label
->sy_value
.X_add_number
;
2330 /* Mark instruction labels in mips16 mode. */
2331 if (mips_opts
.mips16
&& insns
)
2332 mips16_mark_labels ();
2334 mips_no_prev_insn (insns
);
2337 /* Build an instruction created by a macro expansion. This is passed
2338 a pointer to the count of instructions created so far, an
2339 expression, the name of the instruction to build, an operand format
2340 string, and corresponding arguments. */
2344 macro_build (char *place
,
2352 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2361 struct mips_cl_insn insn
;
2362 bfd_reloc_code_real_type r
;
2367 va_start (args
, fmt
);
2373 * If the macro is about to expand into a second instruction,
2374 * print a warning if needed. We need to pass ip as a parameter
2375 * to generate a better warning message here...
2377 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2378 as_warn ("Macro instruction expanded into multiple instructions");
2381 *counter
+= 1; /* bump instruction counter */
2383 if (mips_opts
.mips16
)
2385 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2390 r
= BFD_RELOC_UNUSED
;
2391 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2392 assert (insn
.insn_mo
);
2393 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2395 /* Search until we get a match for NAME. */
2398 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2399 insn_isa
= insn
.insn_mo
->match
;
2400 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2402 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2404 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2406 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2411 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2412 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2413 && (insn_isa
<= mips_opts
.isa
2415 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2417 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2419 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2420 /* start-sanitize-r5900 */
2422 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2423 /* end-sanitize-r5900 */
2424 /* start-sanitize-vr5400 */
2426 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2427 /* end-sanitize-vr5400 */
2429 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2430 /* start-sanitize-r5900 */
2431 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2432 /* end-sanitize-r5900 */
2433 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2437 assert (insn
.insn_mo
->name
);
2438 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2441 insn
.insn_opcode
= insn
.insn_mo
->match
;
2457 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2463 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2468 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2473 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2480 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2484 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2488 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2495 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2501 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2502 assert (r
== BFD_RELOC_MIPS_GPREL
2503 || r
== BFD_RELOC_MIPS_LITERAL
2504 || r
== BFD_RELOC_LO16
2505 || r
== BFD_RELOC_MIPS_GOT16
2506 || r
== BFD_RELOC_MIPS_CALL16
2507 || r
== BFD_RELOC_MIPS_GOT_LO16
2508 || r
== BFD_RELOC_MIPS_CALL_LO16
2509 || (ep
->X_op
== O_subtract
2510 && now_seg
== text_section
2511 && r
== BFD_RELOC_PCREL_LO16
));
2515 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2517 && (ep
->X_op
== O_constant
2518 || (ep
->X_op
== O_symbol
2519 && (r
== BFD_RELOC_HI16_S
2520 || r
== BFD_RELOC_HI16
2521 || r
== BFD_RELOC_MIPS_GOT_HI16
2522 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2523 || (ep
->X_op
== O_subtract
2524 && now_seg
== text_section
2525 && r
== BFD_RELOC_PCREL_HI16_S
)));
2526 if (ep
->X_op
== O_constant
)
2528 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2530 r
= BFD_RELOC_UNUSED
;
2535 assert (ep
!= NULL
);
2537 * This allows macro() to pass an immediate expression for
2538 * creating short branches without creating a symbol.
2539 * Note that the expression still might come from the assembly
2540 * input, in which case the value is not checked for range nor
2541 * is a relocation entry generated (yuck).
2543 if (ep
->X_op
== O_constant
)
2545 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2549 r
= BFD_RELOC_16_PCREL_S2
;
2553 assert (ep
!= NULL
);
2554 r
= BFD_RELOC_MIPS_JMP
;
2563 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2565 append_insn (place
, &insn
, ep
, r
, false);
2569 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2577 struct mips_cl_insn insn
;
2578 bfd_reloc_code_real_type r
;
2580 r
= BFD_RELOC_UNUSED
;
2581 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2582 assert (insn
.insn_mo
);
2583 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2585 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2586 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2589 assert (insn
.insn_mo
->name
);
2590 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2593 insn
.insn_opcode
= insn
.insn_mo
->match
;
2594 insn
.use_extend
= false;
2613 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2618 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2622 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2626 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2636 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2643 regno
= va_arg (args
, int);
2644 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2645 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2666 assert (ep
!= NULL
);
2668 if (ep
->X_op
!= O_constant
)
2669 r
= BFD_RELOC_UNUSED
+ c
;
2672 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2673 false, false, &insn
.insn_opcode
,
2674 &insn
.use_extend
, &insn
.extend
);
2676 r
= BFD_RELOC_UNUSED
;
2682 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2689 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2691 append_insn (place
, &insn
, ep
, r
, false);
2695 * Generate a "lui" instruction.
2698 macro_build_lui (place
, counter
, ep
, regnum
)
2704 expressionS high_expr
;
2705 struct mips_cl_insn insn
;
2706 bfd_reloc_code_real_type r
;
2707 CONST
char *name
= "lui";
2708 CONST
char *fmt
= "t,u";
2710 assert (! mips_opts
.mips16
);
2716 high_expr
.X_op
= O_constant
;
2717 high_expr
.X_add_number
= ep
->X_add_number
;
2720 if (high_expr
.X_op
== O_constant
)
2722 /* we can compute the instruction now without a relocation entry */
2723 if (high_expr
.X_add_number
& 0x8000)
2724 high_expr
.X_add_number
+= 0x10000;
2725 high_expr
.X_add_number
=
2726 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2727 r
= BFD_RELOC_UNUSED
;
2731 assert (ep
->X_op
== O_symbol
);
2732 /* _gp_disp is a special case, used from s_cpload. */
2733 assert (mips_pic
== NO_PIC
2734 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2735 r
= BFD_RELOC_HI16_S
;
2739 * If the macro is about to expand into a second instruction,
2740 * print a warning if needed. We need to pass ip as a parameter
2741 * to generate a better warning message here...
2743 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2744 as_warn ("Macro instruction expanded into multiple instructions");
2747 *counter
+= 1; /* bump instruction counter */
2749 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2750 assert (insn
.insn_mo
);
2751 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2752 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2754 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2755 if (r
== BFD_RELOC_UNUSED
)
2757 insn
.insn_opcode
|= high_expr
.X_add_number
;
2758 append_insn (place
, &insn
, NULL
, r
, false);
2761 append_insn (place
, &insn
, &high_expr
, r
, false);
2765 * Generates code to set the $at register to true (one)
2766 * if reg is less than the immediate expression.
2769 set_at (counter
, reg
, unsignedp
)
2774 if (imm_expr
.X_op
== O_constant
2775 && imm_expr
.X_add_number
>= -0x8000
2776 && imm_expr
.X_add_number
< 0x8000)
2777 macro_build ((char *) NULL
, counter
, &imm_expr
,
2778 unsignedp
? "sltiu" : "slti",
2779 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2782 load_register (counter
, AT
, &imm_expr
, 0);
2783 macro_build ((char *) NULL
, counter
, NULL
,
2784 unsignedp
? "sltu" : "slt",
2785 "d,v,t", AT
, reg
, AT
);
2789 /* Warn if an expression is not a constant. */
2792 check_absolute_expr (ip
, ex
)
2793 struct mips_cl_insn
*ip
;
2796 if (ex
->X_op
== O_big
)
2797 as_bad ("unsupported large constant");
2798 else if (ex
->X_op
!= O_constant
)
2799 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2802 /* Count the leading zeroes by performing a binary chop. This is a
2803 bulky bit of source, but performance is a LOT better for the
2804 majority of values than a simple loop to count the bits:
2805 for (lcnt = 0; (lcnt < 32); lcnt++)
2806 if ((v) & (1 << (31 - lcnt)))
2808 However it is not code size friendly, and the gain will drop a bit
2809 on certain cached systems.
2811 #define COUNT_TOP_ZEROES(v) \
2812 (((v) & ~0xffff) == 0 \
2813 ? ((v) & ~0xff) == 0 \
2814 ? ((v) & ~0xf) == 0 \
2815 ? ((v) & ~0x3) == 0 \
2816 ? ((v) & ~0x1) == 0 \
2821 : ((v) & ~0x7) == 0 \
2824 : ((v) & ~0x3f) == 0 \
2825 ? ((v) & ~0x1f) == 0 \
2828 : ((v) & ~0x7f) == 0 \
2831 : ((v) & ~0xfff) == 0 \
2832 ? ((v) & ~0x3ff) == 0 \
2833 ? ((v) & ~0x1ff) == 0 \
2836 : ((v) & ~0x7ff) == 0 \
2839 : ((v) & ~0x3fff) == 0 \
2840 ? ((v) & ~0x1fff) == 0 \
2843 : ((v) & ~0x7fff) == 0 \
2846 : ((v) & ~0xffffff) == 0 \
2847 ? ((v) & ~0xfffff) == 0 \
2848 ? ((v) & ~0x3ffff) == 0 \
2849 ? ((v) & ~0x1ffff) == 0 \
2852 : ((v) & ~0x7ffff) == 0 \
2855 : ((v) & ~0x3fffff) == 0 \
2856 ? ((v) & ~0x1fffff) == 0 \
2859 : ((v) & ~0x7fffff) == 0 \
2862 : ((v) & ~0xfffffff) == 0 \
2863 ? ((v) & ~0x3ffffff) == 0 \
2864 ? ((v) & ~0x1ffffff) == 0 \
2867 : ((v) & ~0x7ffffff) == 0 \
2870 : ((v) & ~0x3fffffff) == 0 \
2871 ? ((v) & ~0x1fffffff) == 0 \
2874 : ((v) & ~0x7fffffff) == 0 \
2879 * This routine generates the least number of instructions neccessary to load
2880 * an absolute expression value into a register.
2883 load_register (counter
, reg
, ep
, dbl
)
2890 expressionS hi32
, lo32
;
2892 if (ep
->X_op
!= O_big
)
2894 assert (ep
->X_op
== O_constant
);
2895 if (ep
->X_add_number
< 0x8000
2896 && (ep
->X_add_number
>= 0
2897 || (ep
->X_add_number
>= -0x8000
2900 || sizeof (ep
->X_add_number
) > 4))))
2902 /* We can handle 16 bit signed values with an addiu to
2903 $zero. No need to ever use daddiu here, since $zero and
2904 the result are always correct in 32 bit mode. */
2905 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2906 (int) BFD_RELOC_LO16
);
2909 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2911 /* We can handle 16 bit unsigned values with an ori to
2913 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2914 (int) BFD_RELOC_LO16
);
2917 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2918 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2919 == ~ (offsetT
) 0x7fffffff))
2922 || sizeof (ep
->X_add_number
) > 4
2923 || (ep
->X_add_number
& 0x80000000) == 0))
2924 || ((mips_opts
.isa
< 3 || ! dbl
)
2925 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2926 || (mips_opts
.isa
< 3
2928 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2929 == ~ (offsetT
) 0xffffffff)))
2931 /* 32 bit values require an lui. */
2932 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2933 (int) BFD_RELOC_HI16
);
2934 if ((ep
->X_add_number
& 0xffff) != 0)
2935 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2936 (int) BFD_RELOC_LO16
);
2941 /* The value is larger than 32 bits. */
2943 if (mips_opts
.isa
< 3)
2945 as_bad ("Number larger than 32 bits");
2946 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2947 (int) BFD_RELOC_LO16
);
2951 if (ep
->X_op
!= O_big
)
2954 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2955 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2956 hi32
.X_add_number
&= 0xffffffff;
2958 lo32
.X_add_number
&= 0xffffffff;
2962 assert (ep
->X_add_number
> 2);
2963 if (ep
->X_add_number
== 3)
2964 generic_bignum
[3] = 0;
2965 else if (ep
->X_add_number
> 4)
2966 as_bad ("Number larger than 64 bits");
2967 lo32
.X_op
= O_constant
;
2968 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2969 hi32
.X_op
= O_constant
;
2970 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2973 if (hi32
.X_add_number
== 0)
2978 unsigned long hi
, lo
;
2980 if (hi32
.X_add_number
== 0xffffffff)
2982 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2984 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2985 reg
, 0, (int) BFD_RELOC_LO16
);
2988 if (lo32
.X_add_number
& 0x80000000)
2990 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2991 (int) BFD_RELOC_HI16
);
2992 if (lo32
.X_add_number
& 0xffff)
2993 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2994 reg
, reg
, (int) BFD_RELOC_LO16
);
2999 /* Check for 16bit shifted constant. We know that hi32 is
3000 non-zero, so start the mask on the first bit of the hi32
3005 unsigned long himask
, lomask
;
3009 himask
= 0xffff >> (32 - shift
);
3010 lomask
= (0xffff << shift
) & 0xffffffff;
3014 himask
= 0xffff << (shift
- 32);
3017 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3018 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3022 tmp
.X_op
= O_constant
;
3024 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3025 | (lo32
.X_add_number
>> shift
));
3027 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3028 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3029 (int) BFD_RELOC_LO16
);
3030 macro_build ((char *) NULL
, counter
, NULL
,
3031 (shift
>= 32) ? "dsll32" : "dsll",
3033 (shift
>= 32) ? shift
- 32 : shift
);
3037 } while (shift
<= (64 - 16));
3039 /* Find the bit number of the lowest one bit, and store the
3040 shifted value in hi/lo. */
3041 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3042 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3046 while ((lo
& 1) == 0)
3051 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3057 while ((hi
& 1) == 0)
3066 /* Optimize if the shifted value is a (power of 2) - 1. */
3067 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3068 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3070 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3075 /* This instruction will set the register to be all
3077 tmp
.X_op
= O_constant
;
3078 tmp
.X_add_number
= (offsetT
) -1;
3079 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3080 reg
, 0, (int) BFD_RELOC_LO16
);
3084 macro_build ((char *) NULL
, counter
, NULL
,
3085 (bit
>= 32) ? "dsll32" : "dsll",
3087 (bit
>= 32) ? bit
- 32 : bit
);
3089 macro_build ((char *) NULL
, counter
, NULL
,
3090 (shift
>= 32) ? "dsrl32" : "dsrl",
3092 (shift
>= 32) ? shift
- 32 : shift
);
3097 /* Sign extend hi32 before calling load_register, because we can
3098 generally get better code when we load a sign extended value. */
3099 if ((hi32
.X_add_number
& 0x80000000) != 0)
3100 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3101 load_register (counter
, reg
, &hi32
, 0);
3104 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3108 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3117 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3119 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3120 (int) BFD_RELOC_HI16
);
3121 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3128 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3133 mid16
.X_add_number
>>= 16;
3134 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3135 freg
, (int) BFD_RELOC_LO16
);
3136 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3140 if ((lo32
.X_add_number
& 0xffff) != 0)
3141 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3142 (int) BFD_RELOC_LO16
);
3145 /* Load an address into a register. */
3148 load_address (counter
, reg
, ep
)
3155 if (ep
->X_op
!= O_constant
3156 && ep
->X_op
!= O_symbol
)
3158 as_bad ("expression too complex");
3159 ep
->X_op
= O_constant
;
3162 if (ep
->X_op
== O_constant
)
3164 load_register (counter
, reg
, ep
, 0);
3168 if (mips_pic
== NO_PIC
)
3170 /* If this is a reference to a GP relative symbol, we want
3171 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3173 lui $reg,<sym> (BFD_RELOC_HI16_S)
3174 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3175 If we have an addend, we always use the latter form. */
3176 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3177 || nopic_need_relax (ep
->X_add_symbol
, 1))
3182 macro_build ((char *) NULL
, counter
, ep
,
3183 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3184 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3185 p
= frag_var (rs_machine_dependent
, 8, 0,
3186 RELAX_ENCODE (4, 8, 0, 4, 0,
3187 mips_opts
.warn_about_macros
),
3188 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3190 macro_build_lui (p
, counter
, ep
, reg
);
3193 macro_build (p
, counter
, ep
,
3194 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3195 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3197 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3201 /* If this is a reference to an external symbol, we want
3202 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3204 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3206 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3207 If there is a constant, it must be added in after. */
3208 ex
.X_add_number
= ep
->X_add_number
;
3209 ep
->X_add_number
= 0;
3211 macro_build ((char *) NULL
, counter
, ep
,
3212 mips_opts
.isa
< 3 ? "lw" : "ld",
3213 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3214 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3215 p
= frag_var (rs_machine_dependent
, 4, 0,
3216 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3217 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3218 macro_build (p
, counter
, ep
,
3219 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3220 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3221 if (ex
.X_add_number
!= 0)
3223 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3224 as_bad ("PIC code offset overflow (max 16 signed bits)");
3225 ex
.X_op
= O_constant
;
3226 macro_build ((char *) NULL
, counter
, &ex
,
3227 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3228 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3231 else if (mips_pic
== SVR4_PIC
)
3236 /* This is the large GOT case. If this is a reference to an
3237 external symbol, we want
3238 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3240 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3241 Otherwise, for a reference to a local symbol, we want
3242 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3244 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3245 If there is a constant, it must be added in after. */
3246 ex
.X_add_number
= ep
->X_add_number
;
3247 ep
->X_add_number
= 0;
3248 if (reg_needs_delay (GP
))
3253 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3254 (int) BFD_RELOC_MIPS_GOT_HI16
);
3255 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3256 mips_opts
.isa
< 3 ? "addu" : "daddu",
3257 "d,v,t", reg
, reg
, GP
);
3258 macro_build ((char *) NULL
, counter
, ep
,
3259 mips_opts
.isa
< 3 ? "lw" : "ld",
3260 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3261 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3262 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3263 mips_opts
.warn_about_macros
),
3264 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3267 /* We need a nop before loading from $gp. This special
3268 check is required because the lui which starts the main
3269 instruction stream does not refer to $gp, and so will not
3270 insert the nop which may be required. */
3271 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3274 macro_build (p
, counter
, ep
,
3275 mips_opts
.isa
< 3 ? "lw" : "ld",
3276 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3278 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3280 macro_build (p
, counter
, ep
,
3281 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3282 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3283 if (ex
.X_add_number
!= 0)
3285 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3286 as_bad ("PIC code offset overflow (max 16 signed bits)");
3287 ex
.X_op
= O_constant
;
3288 macro_build ((char *) NULL
, counter
, &ex
,
3289 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3290 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3293 else if (mips_pic
== EMBEDDED_PIC
)
3296 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3298 macro_build ((char *) NULL
, counter
, ep
,
3299 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3300 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3308 * This routine implements the seemingly endless macro or synthesized
3309 * instructions and addressing modes in the mips assembly language. Many
3310 * of these macros are simple and are similar to each other. These could
3311 * probably be handled by some kind of table or grammer aproach instead of
3312 * this verbose method. Others are not simple macros but are more like
3313 * optimizing code generation.
3314 * One interesting optimization is when several store macros appear
3315 * consecutivly that would load AT with the upper half of the same address.
3316 * The ensuing load upper instructions are ommited. This implies some kind
3317 * of global optimization. We currently only optimize within a single macro.
3318 * For many of the load and store macros if the address is specified as a
3319 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3320 * first load register 'at' with zero and use it as the base register. The
3321 * mips assembler simply uses register $zero. Just one tiny optimization
3326 struct mips_cl_insn
*ip
;
3328 register int treg
, sreg
, dreg
, breg
;
3343 bfd_reloc_code_real_type r
;
3345 int hold_mips_optimize
;
3347 assert (! mips_opts
.mips16
);
3349 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3350 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3351 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3352 mask
= ip
->insn_mo
->mask
;
3354 expr1
.X_op
= O_constant
;
3355 expr1
.X_op_symbol
= NULL
;
3356 expr1
.X_add_symbol
= NULL
;
3357 expr1
.X_add_number
= 1;
3369 mips_emit_delays (true);
3370 ++mips_opts
.noreorder
;
3371 mips_any_noreorder
= 1;
3373 expr1
.X_add_number
= 8;
3374 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3376 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3378 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3379 macro_build ((char *) NULL
, &icnt
, NULL
,
3380 dbl
? "dsub" : "sub",
3381 "d,v,t", dreg
, 0, sreg
);
3383 --mips_opts
.noreorder
;
3404 if (imm_expr
.X_op
== O_constant
3405 && imm_expr
.X_add_number
>= -0x8000
3406 && imm_expr
.X_add_number
< 0x8000)
3408 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3409 (int) BFD_RELOC_LO16
);
3412 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3413 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3432 if (imm_expr
.X_op
== O_constant
3433 && imm_expr
.X_add_number
>= 0
3434 && imm_expr
.X_add_number
< 0x10000)
3436 if (mask
!= M_NOR_I
)
3437 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3438 sreg
, (int) BFD_RELOC_LO16
);
3441 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3442 treg
, sreg
, (int) BFD_RELOC_LO16
);
3443 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3449 load_register (&icnt
, AT
, &imm_expr
, 0);
3450 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3467 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3473 load_register (&icnt
, AT
, &imm_expr
, 0);
3474 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3482 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3483 likely
? "bgezl" : "bgez",
3489 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3490 likely
? "blezl" : "blez",
3494 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3495 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3496 likely
? "beql" : "beq",
3503 /* check for > max integer */
3504 maxnum
= 0x7fffffff;
3505 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3512 if (imm_expr
.X_op
== O_constant
3513 && imm_expr
.X_add_number
>= maxnum
3514 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3517 /* result is always false */
3520 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3521 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3525 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3526 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3531 if (imm_expr
.X_op
!= O_constant
)
3532 as_bad ("Unsupported large constant");
3533 imm_expr
.X_add_number
++;
3537 if (mask
== M_BGEL_I
)
3539 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3541 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3542 likely
? "bgezl" : "bgez",
3546 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3548 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3549 likely
? "bgtzl" : "bgtz",
3553 maxnum
= 0x7fffffff;
3554 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3561 maxnum
= - maxnum
- 1;
3562 if (imm_expr
.X_op
== O_constant
3563 && imm_expr
.X_add_number
<= maxnum
3564 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3567 /* result is always true */
3568 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3569 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3572 set_at (&icnt
, sreg
, 0);
3573 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3574 likely
? "beql" : "beq",
3585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3586 likely
? "beql" : "beq",
3590 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3592 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3593 likely
? "beql" : "beq",
3601 || (mips_opts
.isa
< 3
3602 && imm_expr
.X_op
== O_constant
3603 && imm_expr
.X_add_number
== 0xffffffff))
3605 if (imm_expr
.X_op
!= O_constant
)
3606 as_bad ("Unsupported large constant");
3607 imm_expr
.X_add_number
++;
3611 if (mask
== M_BGEUL_I
)
3613 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3615 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3617 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3618 likely
? "bnel" : "bne",
3622 set_at (&icnt
, sreg
, 1);
3623 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3624 likely
? "beql" : "beq",
3633 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3634 likely
? "bgtzl" : "bgtz",
3640 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3641 likely
? "bltzl" : "bltz",
3645 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3646 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3647 likely
? "bnel" : "bne",
3656 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3657 likely
? "bnel" : "bne",
3663 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3665 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3666 likely
? "bnel" : "bne",
3675 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3676 likely
? "blezl" : "blez",
3682 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3683 likely
? "bgezl" : "bgez",
3687 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3688 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3689 likely
? "beql" : "beq",
3696 maxnum
= 0x7fffffff;
3697 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3704 if (imm_expr
.X_op
== O_constant
3705 && imm_expr
.X_add_number
>= maxnum
3706 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3708 if (imm_expr
.X_op
!= O_constant
)
3709 as_bad ("Unsupported large constant");
3710 imm_expr
.X_add_number
++;
3714 if (mask
== M_BLTL_I
)
3716 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3718 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3719 likely
? "bltzl" : "bltz",
3723 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3725 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3726 likely
? "blezl" : "blez",
3730 set_at (&icnt
, sreg
, 0);
3731 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3732 likely
? "bnel" : "bne",
3741 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3742 likely
? "beql" : "beq",
3748 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3751 likely
? "beql" : "beq",
3759 || (mips_opts
.isa
< 3
3760 && imm_expr
.X_op
== O_constant
3761 && imm_expr
.X_add_number
== 0xffffffff))
3763 if (imm_expr
.X_op
!= O_constant
)
3764 as_bad ("Unsupported large constant");
3765 imm_expr
.X_add_number
++;
3769 if (mask
== M_BLTUL_I
)
3771 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3773 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3775 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3776 likely
? "beql" : "beq",
3780 set_at (&icnt
, sreg
, 1);
3781 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3782 likely
? "bnel" : "bne",
3791 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3792 likely
? "bltzl" : "bltz",
3798 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3799 likely
? "bgtzl" : "bgtz",
3803 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3804 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3805 likely
? "bnel" : "bne",
3816 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3817 likely
? "bnel" : "bne",
3821 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3823 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3824 likely
? "bnel" : "bne",
3840 as_warn ("Divide by zero.");
3842 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3844 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3848 mips_emit_delays (true);
3849 ++mips_opts
.noreorder
;
3850 mips_any_noreorder
= 1;
3851 macro_build ((char *) NULL
, &icnt
, NULL
,
3852 dbl
? "ddiv" : "div",
3853 "z,s,t", sreg
, treg
);
3855 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3858 expr1
.X_add_number
= 8;
3859 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3860 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3861 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3863 expr1
.X_add_number
= -1;
3864 macro_build ((char *) NULL
, &icnt
, &expr1
,
3865 dbl
? "daddiu" : "addiu",
3866 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3867 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3868 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3871 expr1
.X_add_number
= 1;
3872 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3873 (int) BFD_RELOC_LO16
);
3874 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3879 expr1
.X_add_number
= 0x80000000;
3880 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3881 (int) BFD_RELOC_HI16
);
3884 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3887 expr1
.X_add_number
= 8;
3888 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3889 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3890 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3892 --mips_opts
.noreorder
;
3893 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3932 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3934 as_warn ("Divide by zero.");
3936 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3938 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3941 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3943 if (strcmp (s2
, "mflo") == 0)
3944 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3947 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3950 if (imm_expr
.X_op
== O_constant
3951 && imm_expr
.X_add_number
== -1
3952 && s
[strlen (s
) - 1] != 'u')
3954 if (strcmp (s2
, "mflo") == 0)
3957 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3960 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3964 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3968 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3969 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3970 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3989 mips_emit_delays (true);
3990 ++mips_opts
.noreorder
;
3991 mips_any_noreorder
= 1;
3992 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3994 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3997 expr1
.X_add_number
= 8;
3998 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3999 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4000 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4002 --mips_opts
.noreorder
;
4003 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4009 /* Load the address of a symbol into a register. If breg is not
4010 zero, we then add a base register to it. */
4012 /* When generating embedded PIC code, we permit expressions of
4015 where bar is an address in the .text section. These are used
4016 when getting the addresses of functions. We don't permit
4017 X_add_number to be non-zero, because if the symbol is
4018 external the relaxing code needs to know that any addend is
4019 purely the offset to X_op_symbol. */
4020 if (mips_pic
== EMBEDDED_PIC
4021 && offset_expr
.X_op
== O_subtract
4022 && now_seg
== text_section
4023 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4024 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4025 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4026 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4027 ->sy_value
.X_add_symbol
)
4030 && offset_expr
.X_add_number
== 0)
4032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4033 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4034 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4035 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4036 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4040 if (offset_expr
.X_op
!= O_symbol
4041 && offset_expr
.X_op
!= O_constant
)
4043 as_bad ("expression too complex");
4044 offset_expr
.X_op
= O_constant
;
4058 if (offset_expr
.X_op
== O_constant
)
4059 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4060 else if (mips_pic
== NO_PIC
)
4062 /* If this is a reference to an GP relative symbol, we want
4063 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4065 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4066 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4067 If we have a constant, we need two instructions anyhow,
4068 so we may as well always use the latter form. */
4069 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4070 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4076 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4077 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4078 p
= frag_var (rs_machine_dependent
, 8, 0,
4079 RELAX_ENCODE (4, 8, 0, 4, 0,
4080 mips_opts
.warn_about_macros
),
4081 offset_expr
.X_add_symbol
, (offsetT
) 0,
4084 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4087 macro_build (p
, &icnt
, &offset_expr
,
4088 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4089 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4091 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4093 /* If this is a reference to an external symbol, and there
4094 is no constant, we want
4095 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4096 For a local symbol, we want
4097 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4099 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4101 If we have a small constant, and this is a reference to
4102 an external symbol, we want
4103 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4105 addiu $tempreg,$tempreg,<constant>
4106 For a local symbol, we want the same instruction
4107 sequence, but we output a BFD_RELOC_LO16 reloc on the
4110 If we have a large constant, and this is a reference to
4111 an external symbol, we want
4112 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4113 lui $at,<hiconstant>
4114 addiu $at,$at,<loconstant>
4115 addu $tempreg,$tempreg,$at
4116 For a local symbol, we want the same instruction
4117 sequence, but we output a BFD_RELOC_LO16 reloc on the
4118 addiu instruction. */
4119 expr1
.X_add_number
= offset_expr
.X_add_number
;
4120 offset_expr
.X_add_number
= 0;
4122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4124 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4125 if (expr1
.X_add_number
== 0)
4133 /* We're going to put in an addu instruction using
4134 tempreg, so we may as well insert the nop right
4136 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4140 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4141 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4143 ? mips_opts
.warn_about_macros
4145 offset_expr
.X_add_symbol
, (offsetT
) 0,
4149 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4152 macro_build (p
, &icnt
, &expr1
,
4153 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4154 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4155 /* FIXME: If breg == 0, and the next instruction uses
4156 $tempreg, then if this variant case is used an extra
4157 nop will be generated. */
4159 else if (expr1
.X_add_number
>= -0x8000
4160 && expr1
.X_add_number
< 0x8000)
4162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4164 macro_build ((char *) NULL
, &icnt
, &expr1
,
4165 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4166 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4167 (void) frag_var (rs_machine_dependent
, 0, 0,
4168 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4169 offset_expr
.X_add_symbol
, (offsetT
) 0,
4176 /* If we are going to add in a base register, and the
4177 target register and the base register are the same,
4178 then we are using AT as a temporary register. Since
4179 we want to load the constant into AT, we add our
4180 current AT (from the global offset table) and the
4181 register into the register now, and pretend we were
4182 not using a base register. */
4187 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4190 mips_opts
.isa
< 3 ? "addu" : "daddu",
4191 "d,v,t", treg
, AT
, breg
);
4197 /* Set mips_optimize around the lui instruction to avoid
4198 inserting an unnecessary nop after the lw. */
4199 hold_mips_optimize
= mips_optimize
;
4201 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4202 mips_optimize
= hold_mips_optimize
;
4204 macro_build ((char *) NULL
, &icnt
, &expr1
,
4205 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4206 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4207 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4208 mips_opts
.isa
< 3 ? "addu" : "daddu",
4209 "d,v,t", tempreg
, tempreg
, AT
);
4210 (void) frag_var (rs_machine_dependent
, 0, 0,
4211 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4212 offset_expr
.X_add_symbol
, (offsetT
) 0,
4217 else if (mips_pic
== SVR4_PIC
)
4221 /* This is the large GOT case. If this is a reference to an
4222 external symbol, and there is no constant, we want
4223 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4224 addu $tempreg,$tempreg,$gp
4225 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4226 For a local symbol, we want
4227 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4229 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4231 If we have a small constant, and this is a reference to
4232 an external symbol, we want
4233 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4234 addu $tempreg,$tempreg,$gp
4235 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4237 addiu $tempreg,$tempreg,<constant>
4238 For a local symbol, we want
4239 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4241 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4243 If we have a large constant, and this is a reference to
4244 an external symbol, we want
4245 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4246 addu $tempreg,$tempreg,$gp
4247 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4248 lui $at,<hiconstant>
4249 addiu $at,$at,<loconstant>
4250 addu $tempreg,$tempreg,$at
4251 For a local symbol, we want
4252 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4253 lui $at,<hiconstant>
4254 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4255 addu $tempreg,$tempreg,$at
4257 expr1
.X_add_number
= offset_expr
.X_add_number
;
4258 offset_expr
.X_add_number
= 0;
4260 if (reg_needs_delay (GP
))
4264 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4265 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4266 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4267 mips_opts
.isa
< 3 ? "addu" : "daddu",
4268 "d,v,t", tempreg
, tempreg
, GP
);
4269 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4271 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4273 if (expr1
.X_add_number
== 0)
4281 /* We're going to put in an addu instruction using
4282 tempreg, so we may as well insert the nop right
4284 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4289 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4290 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4293 ? mips_opts
.warn_about_macros
4295 offset_expr
.X_add_symbol
, (offsetT
) 0,
4298 else if (expr1
.X_add_number
>= -0x8000
4299 && expr1
.X_add_number
< 0x8000)
4301 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4303 macro_build ((char *) NULL
, &icnt
, &expr1
,
4304 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4305 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4307 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4308 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4310 ? mips_opts
.warn_about_macros
4312 offset_expr
.X_add_symbol
, (offsetT
) 0,
4319 /* If we are going to add in a base register, and the
4320 target register and the base register are the same,
4321 then we are using AT as a temporary register. Since
4322 we want to load the constant into AT, we add our
4323 current AT (from the global offset table) and the
4324 register into the register now, and pretend we were
4325 not using a base register. */
4333 assert (tempreg
== AT
);
4334 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4337 mips_opts
.isa
< 3 ? "addu" : "daddu",
4338 "d,v,t", treg
, AT
, breg
);
4343 /* Set mips_optimize around the lui instruction to avoid
4344 inserting an unnecessary nop after the lw. */
4345 hold_mips_optimize
= mips_optimize
;
4347 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4348 mips_optimize
= hold_mips_optimize
;
4350 macro_build ((char *) NULL
, &icnt
, &expr1
,
4351 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4352 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4353 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4354 mips_opts
.isa
< 3 ? "addu" : "daddu",
4355 "d,v,t", dreg
, dreg
, AT
);
4357 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4358 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4361 ? mips_opts
.warn_about_macros
4363 offset_expr
.X_add_symbol
, (offsetT
) 0,
4371 /* This is needed because this instruction uses $gp, but
4372 the first instruction on the main stream does not. */
4373 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4376 macro_build (p
, &icnt
, &offset_expr
,
4378 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4380 if (expr1
.X_add_number
>= -0x8000
4381 && expr1
.X_add_number
< 0x8000)
4383 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4385 macro_build (p
, &icnt
, &expr1
,
4386 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4387 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4388 /* FIXME: If add_number is 0, and there was no base
4389 register, the external symbol case ended with a load,
4390 so if the symbol turns out to not be external, and
4391 the next instruction uses tempreg, an unnecessary nop
4392 will be inserted. */
4398 /* We must add in the base register now, as in the
4399 external symbol case. */
4400 assert (tempreg
== AT
);
4401 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4403 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4404 mips_opts
.isa
< 3 ? "addu" : "daddu",
4405 "d,v,t", treg
, AT
, breg
);
4408 /* We set breg to 0 because we have arranged to add
4409 it in in both cases. */
4413 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4415 macro_build (p
, &icnt
, &expr1
,
4416 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4417 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4419 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4420 mips_opts
.isa
< 3 ? "addu" : "daddu",
4421 "d,v,t", tempreg
, tempreg
, AT
);
4425 else if (mips_pic
== EMBEDDED_PIC
)
4428 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4430 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4431 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4432 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4438 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4439 mips_opts
.isa
< 3 ? "addu" : "daddu",
4440 "d,v,t", treg
, tempreg
, breg
);
4448 /* The j instruction may not be used in PIC code, since it
4449 requires an absolute address. We convert it to a b
4451 if (mips_pic
== NO_PIC
)
4452 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4454 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4457 /* The jal instructions must be handled as macros because when
4458 generating PIC code they expand to multi-instruction
4459 sequences. Normally they are simple instructions. */
4464 if (mips_pic
== NO_PIC
4465 || mips_pic
== EMBEDDED_PIC
)
4466 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4468 else if (mips_pic
== SVR4_PIC
)
4470 if (sreg
!= PIC_CALL_REG
)
4471 as_warn ("MIPS PIC call to register other than $25");
4473 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4475 if (mips_cprestore_offset
< 0)
4476 as_warn ("No .cprestore pseudo-op used in PIC code");
4479 expr1
.X_add_number
= mips_cprestore_offset
;
4480 macro_build ((char *) NULL
, &icnt
, &expr1
,
4481 mips_opts
.isa
< 3 ? "lw" : "ld",
4482 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4491 if (mips_pic
== NO_PIC
)
4492 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4493 else if (mips_pic
== SVR4_PIC
)
4495 /* If this is a reference to an external symbol, and we are
4496 using a small GOT, we want
4497 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4501 lw $gp,cprestore($sp)
4502 The cprestore value is set using the .cprestore
4503 pseudo-op. If we are using a big GOT, we want
4504 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4506 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4510 lw $gp,cprestore($sp)
4511 If the symbol is not external, we want
4512 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4514 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4517 lw $gp,cprestore($sp) */
4521 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4522 mips_opts
.isa
< 3 ? "lw" : "ld",
4523 "t,o(b)", PIC_CALL_REG
,
4524 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4525 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4527 p
= frag_var (rs_machine_dependent
, 4, 0,
4528 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4529 offset_expr
.X_add_symbol
, (offsetT
) 0,
4536 if (reg_needs_delay (GP
))
4540 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4541 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4542 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4543 mips_opts
.isa
< 3 ? "addu" : "daddu",
4544 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4545 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4546 mips_opts
.isa
< 3 ? "lw" : "ld",
4547 "t,o(b)", PIC_CALL_REG
,
4548 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4549 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4551 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4552 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4554 offset_expr
.X_add_symbol
, (offsetT
) 0,
4558 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4561 macro_build (p
, &icnt
, &offset_expr
,
4562 mips_opts
.isa
< 3 ? "lw" : "ld",
4563 "t,o(b)", PIC_CALL_REG
,
4564 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4566 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4569 macro_build (p
, &icnt
, &offset_expr
,
4570 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4571 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4572 (int) BFD_RELOC_LO16
);
4573 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4574 "jalr", "s", PIC_CALL_REG
);
4575 if (mips_cprestore_offset
< 0)
4576 as_warn ("No .cprestore pseudo-op used in PIC code");
4579 if (mips_opts
.noreorder
)
4580 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4582 expr1
.X_add_number
= mips_cprestore_offset
;
4583 macro_build ((char *) NULL
, &icnt
, &expr1
,
4584 mips_opts
.isa
< 3 ? "lw" : "ld",
4585 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4589 else if (mips_pic
== EMBEDDED_PIC
)
4591 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4592 /* The linker may expand the call to a longer sequence which
4593 uses $at, so we must break rather than return. */
4618 /* Itbl support may require additional care here. */
4623 /* Itbl support may require additional care here. */
4628 /* Itbl support may require additional care here. */
4633 /* Itbl support may require additional care here. */
4646 /* Itbl support may require additional care here. */
4651 /* Itbl support may require additional care here. */
4656 /* Itbl support may require additional care here. */
4676 if (breg
== treg
|| coproc
|| lr
)
4698 /* Itbl support may require additional care here. */
4703 /* Itbl support may require additional care here. */
4708 /* Itbl support may require additional care here. */
4713 /* Itbl support may require additional care here. */
4731 /* Itbl support may require additional care here. */
4735 /* Itbl support may require additional care here. */
4740 /* Itbl support may require additional care here. */
4752 /* Itbl support may require additional care here. */
4753 if (mask
== M_LWC1_AB
4754 || mask
== M_SWC1_AB
4755 || mask
== M_LDC1_AB
4756 || mask
== M_SDC1_AB
4765 if (offset_expr
.X_op
!= O_constant
4766 && offset_expr
.X_op
!= O_symbol
)
4768 as_bad ("expression too complex");
4769 offset_expr
.X_op
= O_constant
;
4772 /* A constant expression in PIC code can be handled just as it
4773 is in non PIC code. */
4774 if (mips_pic
== NO_PIC
4775 || offset_expr
.X_op
== O_constant
)
4777 /* If this is a reference to a GP relative symbol, and there
4778 is no base register, we want
4779 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4780 Otherwise, if there is no base register, we want
4781 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4782 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4783 If we have a constant, we need two instructions anyhow,
4784 so we always use the latter form.
4786 If we have a base register, and this is a reference to a
4787 GP relative symbol, we want
4788 addu $tempreg,$breg,$gp
4789 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4791 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4792 addu $tempreg,$tempreg,$breg
4793 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4794 With a constant we always use the latter case. */
4797 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4798 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4803 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4804 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4805 p
= frag_var (rs_machine_dependent
, 8, 0,
4806 RELAX_ENCODE (4, 8, 0, 4, 0,
4807 (mips_opts
.warn_about_macros
4809 && mips_opts
.noat
))),
4810 offset_expr
.X_add_symbol
, (offsetT
) 0,
4814 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4817 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4818 (int) BFD_RELOC_LO16
, tempreg
);
4822 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4823 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4828 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4829 mips_opts
.isa
< 3 ? "addu" : "daddu",
4830 "d,v,t", tempreg
, breg
, GP
);
4831 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4832 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4833 p
= frag_var (rs_machine_dependent
, 12, 0,
4834 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4835 offset_expr
.X_add_symbol
, (offsetT
) 0,
4838 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4841 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4842 mips_opts
.isa
< 3 ? "addu" : "daddu",
4843 "d,v,t", tempreg
, tempreg
, breg
);
4846 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4847 (int) BFD_RELOC_LO16
, tempreg
);
4850 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4852 /* If this is a reference to an external symbol, we want
4853 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4855 <op> $treg,0($tempreg)
4857 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4859 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4860 <op> $treg,0($tempreg)
4861 If there is a base register, we add it to $tempreg before
4862 the <op>. If there is a constant, we stick it in the
4863 <op> instruction. We don't handle constants larger than
4864 16 bits, because we have no way to load the upper 16 bits
4865 (actually, we could handle them for the subset of cases
4866 in which we are not using $at). */
4867 assert (offset_expr
.X_op
== O_symbol
);
4868 expr1
.X_add_number
= offset_expr
.X_add_number
;
4869 offset_expr
.X_add_number
= 0;
4870 if (expr1
.X_add_number
< -0x8000
4871 || expr1
.X_add_number
>= 0x8000)
4872 as_bad ("PIC code offset overflow (max 16 signed bits)");
4874 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4875 mips_opts
.isa
< 3 ? "lw" : "ld",
4876 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4877 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4878 p
= frag_var (rs_machine_dependent
, 4, 0,
4879 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4880 offset_expr
.X_add_symbol
, (offsetT
) 0,
4882 macro_build (p
, &icnt
, &offset_expr
,
4883 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4884 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4886 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4887 mips_opts
.isa
< 3 ? "addu" : "daddu",
4888 "d,v,t", tempreg
, tempreg
, breg
);
4889 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4890 (int) BFD_RELOC_LO16
, tempreg
);
4892 else if (mips_pic
== SVR4_PIC
)
4896 /* If this is a reference to an external symbol, we want
4897 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4898 addu $tempreg,$tempreg,$gp
4899 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4900 <op> $treg,0($tempreg)
4902 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4904 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4905 <op> $treg,0($tempreg)
4906 If there is a base register, we add it to $tempreg before
4907 the <op>. If there is a constant, we stick it in the
4908 <op> instruction. We don't handle constants larger than
4909 16 bits, because we have no way to load the upper 16 bits
4910 (actually, we could handle them for the subset of cases
4911 in which we are not using $at). */
4912 assert (offset_expr
.X_op
== O_symbol
);
4913 expr1
.X_add_number
= offset_expr
.X_add_number
;
4914 offset_expr
.X_add_number
= 0;
4915 if (expr1
.X_add_number
< -0x8000
4916 || expr1
.X_add_number
>= 0x8000)
4917 as_bad ("PIC code offset overflow (max 16 signed bits)");
4918 if (reg_needs_delay (GP
))
4923 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4924 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4925 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4926 mips_opts
.isa
< 3 ? "addu" : "daddu",
4927 "d,v,t", tempreg
, tempreg
, GP
);
4928 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4929 mips_opts
.isa
< 3 ? "lw" : "ld",
4930 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4932 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4933 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4934 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
4937 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4940 macro_build (p
, &icnt
, &offset_expr
,
4941 mips_opts
.isa
< 3 ? "lw" : "ld",
4942 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4944 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4946 macro_build (p
, &icnt
, &offset_expr
,
4947 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4948 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4950 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4951 mips_opts
.isa
< 3 ? "addu" : "daddu",
4952 "d,v,t", tempreg
, tempreg
, breg
);
4953 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4954 (int) BFD_RELOC_LO16
, tempreg
);
4956 else if (mips_pic
== EMBEDDED_PIC
)
4958 /* If there is no base register, we want
4959 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4960 If there is a base register, we want
4961 addu $tempreg,$breg,$gp
4962 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4964 assert (offset_expr
.X_op
== O_symbol
);
4967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4968 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4973 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4974 mips_opts
.isa
< 3 ? "addu" : "daddu",
4975 "d,v,t", tempreg
, breg
, GP
);
4976 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4977 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4990 load_register (&icnt
, treg
, &imm_expr
, 0);
4994 load_register (&icnt
, treg
, &imm_expr
, 1);
4998 if (imm_expr
.X_op
== O_constant
)
5000 load_register (&icnt
, AT
, &imm_expr
, 0);
5001 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5002 "mtc1", "t,G", AT
, treg
);
5007 assert (offset_expr
.X_op
== O_symbol
5008 && strcmp (segment_name (S_GET_SEGMENT
5009 (offset_expr
.X_add_symbol
)),
5011 && offset_expr
.X_add_number
== 0);
5012 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5013 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5018 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5019 the entire value, and in mips1 mode it is the high order 32
5020 bits of the value and the low order 32 bits are either zero
5021 or in offset_expr. */
5022 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5024 if (mips_opts
.isa
>= 3)
5025 load_register (&icnt
, treg
, &imm_expr
, 1);
5030 if (target_big_endian
)
5042 load_register (&icnt
, hreg
, &imm_expr
, 0);
5045 if (offset_expr
.X_op
== O_absent
)
5046 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5050 assert (offset_expr
.X_op
== O_constant
);
5051 load_register (&icnt
, lreg
, &offset_expr
, 0);
5058 /* We know that sym is in the .rdata section. First we get the
5059 upper 16 bits of the address. */
5060 if (mips_pic
== NO_PIC
)
5062 /* FIXME: This won't work for a 64 bit address. */
5063 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5065 else if (mips_pic
== SVR4_PIC
)
5067 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5068 mips_opts
.isa
< 3 ? "lw" : "ld",
5069 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5071 else if (mips_pic
== EMBEDDED_PIC
)
5073 /* For embedded PIC we pick up the entire address off $gp in
5074 a single instruction. */
5075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5076 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5077 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5078 offset_expr
.X_op
= O_constant
;
5079 offset_expr
.X_add_number
= 0;
5084 /* Now we load the register(s). */
5085 if (mips_opts
.isa
>= 3)
5086 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5087 treg
, (int) BFD_RELOC_LO16
, AT
);
5090 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5091 treg
, (int) BFD_RELOC_LO16
, AT
);
5094 /* FIXME: How in the world do we deal with the possible
5096 offset_expr
.X_add_number
+= 4;
5097 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5098 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5102 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5103 does not become a variant frag. */
5104 frag_wane (frag_now
);
5110 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5111 the entire value, and in mips1 mode it is the high order 32
5112 bits of the value and the low order 32 bits are either zero
5113 or in offset_expr. */
5114 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5116 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5117 if (mips_opts
.isa
>= 3)
5118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5119 "dmtc1", "t,S", AT
, treg
);
5122 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5123 "mtc1", "t,G", AT
, treg
+ 1);
5124 if (offset_expr
.X_op
== O_absent
)
5125 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5126 "mtc1", "t,G", 0, treg
);
5129 assert (offset_expr
.X_op
== O_constant
);
5130 load_register (&icnt
, AT
, &offset_expr
, 0);
5131 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5132 "mtc1", "t,G", AT
, treg
);
5138 assert (offset_expr
.X_op
== O_symbol
5139 && offset_expr
.X_add_number
== 0);
5140 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5141 if (strcmp (s
, ".lit8") == 0)
5143 if (mips_opts
.isa
>= 2)
5145 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5146 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5150 r
= BFD_RELOC_MIPS_LITERAL
;
5155 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5156 if (mips_pic
== SVR4_PIC
)
5157 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5158 mips_opts
.isa
< 3 ? "lw" : "ld",
5159 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5162 /* FIXME: This won't work for a 64 bit address. */
5163 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5166 if (mips_opts
.isa
>= 2)
5168 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5169 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5171 /* To avoid confusion in tc_gen_reloc, we must ensure
5172 that this does not become a variant frag. */
5173 frag_wane (frag_now
);
5184 /* Even on a big endian machine $fn comes before $fn+1. We have
5185 to adjust when loading from memory. */
5188 assert (mips_opts
.isa
< 2);
5189 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5190 target_big_endian
? treg
+ 1 : treg
,
5192 /* FIXME: A possible overflow which I don't know how to deal
5194 offset_expr
.X_add_number
+= 4;
5195 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5196 target_big_endian
? treg
: treg
+ 1,
5199 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5200 does not become a variant frag. */
5201 frag_wane (frag_now
);
5210 * The MIPS assembler seems to check for X_add_number not
5211 * being double aligned and generating:
5214 * addiu at,at,%lo(foo+1)
5217 * But, the resulting address is the same after relocation so why
5218 * generate the extra instruction?
5220 /* Itbl support may require additional care here. */
5222 if (mips_opts
.isa
>= 2)
5233 if (mips_opts
.isa
>= 2)
5241 /* Itbl support may require additional care here. */
5246 if (mips_opts
.isa
>= 3)
5257 if (mips_opts
.isa
>= 3)
5267 if (offset_expr
.X_op
!= O_symbol
5268 && offset_expr
.X_op
!= O_constant
)
5270 as_bad ("expression too complex");
5271 offset_expr
.X_op
= O_constant
;
5274 /* Even on a big endian machine $fn comes before $fn+1. We have
5275 to adjust when loading from memory. We set coproc if we must
5276 load $fn+1 first. */
5277 /* Itbl support may require additional care here. */
5278 if (! target_big_endian
)
5281 if (mips_pic
== NO_PIC
5282 || offset_expr
.X_op
== O_constant
)
5284 /* If this is a reference to a GP relative symbol, we want
5285 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5286 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5287 If we have a base register, we use this
5289 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5290 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5291 If this is not a GP relative symbol, we want
5292 lui $at,<sym> (BFD_RELOC_HI16_S)
5293 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5294 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5295 If there is a base register, we add it to $at after the
5296 lui instruction. If there is a constant, we always use
5298 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5299 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5319 mips_opts
.isa
< 3 ? "addu" : "daddu",
5320 "d,v,t", AT
, breg
, GP
);
5326 /* Itbl support may require additional care here. */
5327 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5328 coproc
? treg
+ 1 : treg
,
5329 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5330 offset_expr
.X_add_number
+= 4;
5332 /* Set mips_optimize to 2 to avoid inserting an
5334 hold_mips_optimize
= mips_optimize
;
5336 /* Itbl support may require additional care here. */
5337 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5338 coproc
? treg
: treg
+ 1,
5339 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5340 mips_optimize
= hold_mips_optimize
;
5342 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5343 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5344 used_at
&& mips_opts
.noat
),
5345 offset_expr
.X_add_symbol
, (offsetT
) 0,
5348 /* We just generated two relocs. When tc_gen_reloc
5349 handles this case, it will skip the first reloc and
5350 handle the second. The second reloc already has an
5351 extra addend of 4, which we added above. We must
5352 subtract it out, and then subtract another 4 to make
5353 the first reloc come out right. The second reloc
5354 will come out right because we are going to add 4 to
5355 offset_expr when we build its instruction below.
5357 If we have a symbol, then we don't want to include
5358 the offset, because it will wind up being included
5359 when we generate the reloc. */
5361 if (offset_expr
.X_op
== O_constant
)
5362 offset_expr
.X_add_number
-= 8;
5365 offset_expr
.X_add_number
= -4;
5366 offset_expr
.X_op
= O_constant
;
5369 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5374 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5375 mips_opts
.isa
< 3 ? "addu" : "daddu",
5376 "d,v,t", AT
, breg
, AT
);
5380 /* Itbl support may require additional care here. */
5381 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5382 coproc
? treg
+ 1 : treg
,
5383 (int) BFD_RELOC_LO16
, AT
);
5386 /* FIXME: How do we handle overflow here? */
5387 offset_expr
.X_add_number
+= 4;
5388 /* Itbl support may require additional care here. */
5389 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5390 coproc
? treg
: treg
+ 1,
5391 (int) BFD_RELOC_LO16
, AT
);
5393 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5397 /* If this is a reference to an external symbol, we want
5398 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5403 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5405 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5406 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5407 If there is a base register we add it to $at before the
5408 lwc1 instructions. If there is a constant we include it
5409 in the lwc1 instructions. */
5411 expr1
.X_add_number
= offset_expr
.X_add_number
;
5412 offset_expr
.X_add_number
= 0;
5413 if (expr1
.X_add_number
< -0x8000
5414 || expr1
.X_add_number
>= 0x8000 - 4)
5415 as_bad ("PIC code offset overflow (max 16 signed bits)");
5420 frag_grow (24 + off
);
5421 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5422 mips_opts
.isa
< 3 ? "lw" : "ld",
5423 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5424 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5426 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5427 mips_opts
.isa
< 3 ? "addu" : "daddu",
5428 "d,v,t", AT
, breg
, AT
);
5429 /* Itbl support may require additional care here. */
5430 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5431 coproc
? treg
+ 1 : treg
,
5432 (int) BFD_RELOC_LO16
, AT
);
5433 expr1
.X_add_number
+= 4;
5435 /* Set mips_optimize to 2 to avoid inserting an undesired
5437 hold_mips_optimize
= mips_optimize
;
5439 /* Itbl support may require additional care here. */
5440 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5441 coproc
? treg
: treg
+ 1,
5442 (int) BFD_RELOC_LO16
, AT
);
5443 mips_optimize
= hold_mips_optimize
;
5445 (void) frag_var (rs_machine_dependent
, 0, 0,
5446 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5447 offset_expr
.X_add_symbol
, (offsetT
) 0,
5450 else if (mips_pic
== SVR4_PIC
)
5454 /* If this is a reference to an external symbol, we want
5455 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5457 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5462 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5464 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5465 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5466 If there is a base register we add it to $at before the
5467 lwc1 instructions. If there is a constant we include it
5468 in the lwc1 instructions. */
5470 expr1
.X_add_number
= offset_expr
.X_add_number
;
5471 offset_expr
.X_add_number
= 0;
5472 if (expr1
.X_add_number
< -0x8000
5473 || expr1
.X_add_number
>= 0x8000 - 4)
5474 as_bad ("PIC code offset overflow (max 16 signed bits)");
5475 if (reg_needs_delay (GP
))
5484 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5485 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5486 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5487 mips_opts
.isa
< 3 ? "addu" : "daddu",
5488 "d,v,t", AT
, AT
, GP
);
5489 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5490 mips_opts
.isa
< 3 ? "lw" : "ld",
5491 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5492 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5494 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5495 mips_opts
.isa
< 3 ? "addu" : "daddu",
5496 "d,v,t", AT
, breg
, AT
);
5497 /* Itbl support may require additional care here. */
5498 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5499 coproc
? treg
+ 1 : treg
,
5500 (int) BFD_RELOC_LO16
, AT
);
5501 expr1
.X_add_number
+= 4;
5503 /* Set mips_optimize to 2 to avoid inserting an undesired
5505 hold_mips_optimize
= mips_optimize
;
5507 /* Itbl support may require additional care here. */
5508 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5509 coproc
? treg
: treg
+ 1,
5510 (int) BFD_RELOC_LO16
, AT
);
5511 mips_optimize
= hold_mips_optimize
;
5512 expr1
.X_add_number
-= 4;
5514 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5515 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5516 8 + gpdel
+ off
, 1, 0),
5517 offset_expr
.X_add_symbol
, (offsetT
) 0,
5521 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5524 macro_build (p
, &icnt
, &offset_expr
,
5525 mips_opts
.isa
< 3 ? "lw" : "ld",
5526 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5528 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5532 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5533 mips_opts
.isa
< 3 ? "addu" : "daddu",
5534 "d,v,t", AT
, breg
, AT
);
5537 /* Itbl support may require additional care here. */
5538 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5539 coproc
? treg
+ 1 : treg
,
5540 (int) BFD_RELOC_LO16
, AT
);
5542 expr1
.X_add_number
+= 4;
5544 /* Set mips_optimize to 2 to avoid inserting an undesired
5546 hold_mips_optimize
= mips_optimize
;
5548 /* Itbl support may require additional care here. */
5549 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5550 coproc
? treg
: treg
+ 1,
5551 (int) BFD_RELOC_LO16
, AT
);
5552 mips_optimize
= hold_mips_optimize
;
5554 else if (mips_pic
== EMBEDDED_PIC
)
5556 /* If there is no base register, we use
5557 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5558 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5559 If we have a base register, we use
5561 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5562 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5571 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5572 mips_opts
.isa
< 3 ? "addu" : "daddu",
5573 "d,v,t", AT
, breg
, GP
);
5578 /* Itbl support may require additional care here. */
5579 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5580 coproc
? treg
+ 1 : treg
,
5581 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5582 offset_expr
.X_add_number
+= 4;
5583 /* Itbl support may require additional care here. */
5584 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5585 coproc
? treg
: treg
+ 1,
5586 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5602 assert (mips_opts
.isa
< 3);
5603 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5604 (int) BFD_RELOC_LO16
, breg
);
5605 offset_expr
.X_add_number
+= 4;
5606 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5607 (int) BFD_RELOC_LO16
, breg
);
5610 /* New code added to support COPZ instructions.
5611 This code builds table entries out of the macros in mip_opcodes.
5612 R4000 uses interlocks to handle coproc delays.
5613 Other chips (like the R3000) require nops to be inserted for delays.
5615 FIXME: Currently, we require that the user handle delays.
5616 In order to fill delay slots for non-interlocked chips,
5617 we must have a way to specify delays based on the coprocessor.
5618 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5619 What are the side-effects of the cop instruction?
5620 What cache support might we have and what are its effects?
5621 Both coprocessor & memory require delays. how long???
5622 What registers are read/set/modified?
5624 If an itbl is provided to interpret cop instructions,
5625 this knowledge can be encoded in the itbl spec. */
5639 /* For now we just do C (same as Cz). */
5640 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5643 #ifdef LOSING_COMPILER
5645 /* Try and see if this is a new itbl instruction.
5646 This code builds table entries out of the macros in mip_opcodes.
5647 FIXME: For now we just assemble the expression and pass it's
5648 value along as a 32-bit immediate.
5649 We may want to have the assembler assemble this value,
5650 so that we gain the assembler's knowledge of delay slots,
5652 Would it be more efficient to use mask (id) here? */
5653 if (itbl_have_entries
5654 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5656 s
= ip
->insn_mo
->name
;
5658 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5659 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5666 as_warn ("Macro used $at after \".set noat\"");
5671 struct mips_cl_insn
*ip
;
5673 register int treg
, sreg
, dreg
, breg
;
5688 bfd_reloc_code_real_type r
;
5691 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5692 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5693 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5694 mask
= ip
->insn_mo
->mask
;
5696 expr1
.X_op
= O_constant
;
5697 expr1
.X_op_symbol
= NULL
;
5698 expr1
.X_add_symbol
= NULL
;
5699 expr1
.X_add_number
= 1;
5703 #endif /* LOSING_COMPILER */
5708 macro_build ((char *) NULL
, &icnt
, NULL
,
5709 dbl
? "dmultu" : "multu",
5711 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5717 /* The MIPS assembler some times generates shifts and adds. I'm
5718 not trying to be that fancy. GCC should do this for us
5720 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5721 macro_build ((char *) NULL
, &icnt
, NULL
,
5722 dbl
? "dmult" : "mult",
5724 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5730 mips_emit_delays (true);
5731 ++mips_opts
.noreorder
;
5732 mips_any_noreorder
= 1;
5733 macro_build ((char *) NULL
, &icnt
, NULL
,
5734 dbl
? "dmult" : "mult",
5736 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5737 macro_build ((char *) NULL
, &icnt
, NULL
,
5738 dbl
? "dsra32" : "sra",
5739 "d,w,<", dreg
, dreg
, 31);
5740 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5742 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5745 expr1
.X_add_number
= 8;
5746 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5747 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5748 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5750 --mips_opts
.noreorder
;
5751 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5757 mips_emit_delays (true);
5758 ++mips_opts
.noreorder
;
5759 mips_any_noreorder
= 1;
5760 macro_build ((char *) NULL
, &icnt
, NULL
,
5761 dbl
? "dmultu" : "multu",
5763 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5764 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5766 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5769 expr1
.X_add_number
= 8;
5770 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5771 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5772 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5774 --mips_opts
.noreorder
;
5778 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5779 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5780 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5782 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5786 if (imm_expr
.X_op
!= O_constant
)
5787 as_bad ("rotate count too large");
5788 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5789 (int) (imm_expr
.X_add_number
& 0x1f));
5790 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5791 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5792 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5796 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5797 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5798 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5800 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5804 if (imm_expr
.X_op
!= O_constant
)
5805 as_bad ("rotate count too large");
5806 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5807 (int) (imm_expr
.X_add_number
& 0x1f));
5808 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5809 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5810 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5814 assert (mips_opts
.isa
< 2);
5815 /* Even on a big endian machine $fn comes before $fn+1. We have
5816 to adjust when storing to memory. */
5817 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5818 target_big_endian
? treg
+ 1 : treg
,
5819 (int) BFD_RELOC_LO16
, breg
);
5820 offset_expr
.X_add_number
+= 4;
5821 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5822 target_big_endian
? treg
: treg
+ 1,
5823 (int) BFD_RELOC_LO16
, breg
);
5828 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5829 treg
, (int) BFD_RELOC_LO16
);
5831 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5832 sreg
, (int) BFD_RELOC_LO16
);
5835 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5837 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5838 dreg
, (int) BFD_RELOC_LO16
);
5843 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5845 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5846 sreg
, (int) BFD_RELOC_LO16
);
5851 as_warn ("Instruction %s: result is always false",
5853 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5856 if (imm_expr
.X_op
== O_constant
5857 && imm_expr
.X_add_number
>= 0
5858 && imm_expr
.X_add_number
< 0x10000)
5860 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5861 sreg
, (int) BFD_RELOC_LO16
);
5864 else if (imm_expr
.X_op
== O_constant
5865 && imm_expr
.X_add_number
> -0x8000
5866 && imm_expr
.X_add_number
< 0)
5868 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5869 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5870 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5871 "t,r,j", dreg
, sreg
,
5872 (int) BFD_RELOC_LO16
);
5877 load_register (&icnt
, AT
, &imm_expr
, 0);
5878 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5882 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5883 (int) BFD_RELOC_LO16
);
5888 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5894 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5895 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5896 (int) BFD_RELOC_LO16
);
5899 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5901 if (imm_expr
.X_op
== O_constant
5902 && imm_expr
.X_add_number
>= -0x8000
5903 && imm_expr
.X_add_number
< 0x8000)
5905 macro_build ((char *) NULL
, &icnt
, &expr1
,
5906 mask
== M_SGE_I
? "slti" : "sltiu",
5907 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5912 load_register (&icnt
, AT
, &imm_expr
, 0);
5913 macro_build ((char *) NULL
, &icnt
, NULL
,
5914 mask
== M_SGE_I
? "slt" : "sltu",
5915 "d,v,t", dreg
, sreg
, AT
);
5918 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5919 (int) BFD_RELOC_LO16
);
5924 case M_SGT
: /* sreg > treg <==> treg < sreg */
5930 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5933 case M_SGT_I
: /* sreg > I <==> I < sreg */
5939 load_register (&icnt
, AT
, &imm_expr
, 0);
5940 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5943 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5949 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5950 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5951 (int) BFD_RELOC_LO16
);
5954 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5960 load_register (&icnt
, AT
, &imm_expr
, 0);
5961 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5962 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5963 (int) BFD_RELOC_LO16
);
5967 if (imm_expr
.X_op
== O_constant
5968 && imm_expr
.X_add_number
>= -0x8000
5969 && imm_expr
.X_add_number
< 0x8000)
5971 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5972 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5975 load_register (&icnt
, AT
, &imm_expr
, 0);
5976 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5980 if (imm_expr
.X_op
== O_constant
5981 && imm_expr
.X_add_number
>= -0x8000
5982 && imm_expr
.X_add_number
< 0x8000)
5984 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5985 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5988 load_register (&icnt
, AT
, &imm_expr
, 0);
5989 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5995 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5998 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6002 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6004 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6010 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6012 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6018 as_warn ("Instruction %s: result is always true",
6020 macro_build ((char *) NULL
, &icnt
, &expr1
,
6021 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
6022 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6025 if (imm_expr
.X_op
== O_constant
6026 && imm_expr
.X_add_number
>= 0
6027 && imm_expr
.X_add_number
< 0x10000)
6029 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6030 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6033 else if (imm_expr
.X_op
== O_constant
6034 && imm_expr
.X_add_number
> -0x8000
6035 && imm_expr
.X_add_number
< 0)
6037 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6038 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6039 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
6040 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6045 load_register (&icnt
, AT
, &imm_expr
, 0);
6046 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6050 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6058 if (imm_expr
.X_op
== O_constant
6059 && imm_expr
.X_add_number
> -0x8000
6060 && imm_expr
.X_add_number
<= 0x8000)
6062 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6063 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6064 dbl
? "daddi" : "addi",
6065 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6068 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6069 macro_build ((char *) NULL
, &icnt
, NULL
,
6070 dbl
? "dsub" : "sub",
6071 "d,v,t", dreg
, sreg
, AT
);
6077 if (imm_expr
.X_op
== O_constant
6078 && imm_expr
.X_add_number
> -0x8000
6079 && imm_expr
.X_add_number
<= 0x8000)
6081 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6082 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6083 dbl
? "daddiu" : "addiu",
6084 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6087 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6088 macro_build ((char *) NULL
, &icnt
, NULL
,
6089 dbl
? "dsubu" : "subu",
6090 "d,v,t", dreg
, sreg
, AT
);
6111 load_register (&icnt
, AT
, &imm_expr
, 0);
6112 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6117 assert (mips_opts
.isa
< 2);
6118 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6119 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6122 * Is the double cfc1 instruction a bug in the mips assembler;
6123 * or is there a reason for it?
6125 mips_emit_delays (true);
6126 ++mips_opts
.noreorder
;
6127 mips_any_noreorder
= 1;
6128 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6129 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6130 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6131 expr1
.X_add_number
= 3;
6132 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6133 (int) BFD_RELOC_LO16
);
6134 expr1
.X_add_number
= 2;
6135 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6136 (int) BFD_RELOC_LO16
);
6137 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6138 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6139 macro_build ((char *) NULL
, &icnt
, NULL
,
6140 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6141 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6142 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6143 --mips_opts
.noreorder
;
6152 if (offset_expr
.X_add_number
>= 0x7fff)
6153 as_bad ("operand overflow");
6154 /* avoid load delay */
6155 if (! target_big_endian
)
6156 offset_expr
.X_add_number
+= 1;
6157 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6158 (int) BFD_RELOC_LO16
, breg
);
6159 if (! target_big_endian
)
6160 offset_expr
.X_add_number
-= 1;
6162 offset_expr
.X_add_number
+= 1;
6163 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6164 (int) BFD_RELOC_LO16
, breg
);
6165 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6166 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6179 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6180 as_bad ("operand overflow");
6181 if (! target_big_endian
)
6182 offset_expr
.X_add_number
+= off
;
6183 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6184 (int) BFD_RELOC_LO16
, breg
);
6185 if (! target_big_endian
)
6186 offset_expr
.X_add_number
-= off
;
6188 offset_expr
.X_add_number
+= off
;
6189 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6190 (int) BFD_RELOC_LO16
, breg
);
6203 load_address (&icnt
, AT
, &offset_expr
);
6205 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6206 mips_opts
.isa
< 3 ? "addu" : "daddu",
6207 "d,v,t", AT
, AT
, breg
);
6208 if (! target_big_endian
)
6209 expr1
.X_add_number
= off
;
6211 expr1
.X_add_number
= 0;
6212 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6213 (int) BFD_RELOC_LO16
, AT
);
6214 if (! target_big_endian
)
6215 expr1
.X_add_number
= 0;
6217 expr1
.X_add_number
= off
;
6218 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6219 (int) BFD_RELOC_LO16
, AT
);
6224 load_address (&icnt
, AT
, &offset_expr
);
6226 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6227 mips_opts
.isa
< 3 ? "addu" : "daddu",
6228 "d,v,t", AT
, AT
, breg
);
6229 if (target_big_endian
)
6230 expr1
.X_add_number
= 0;
6231 macro_build ((char *) NULL
, &icnt
, &expr1
,
6232 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6233 (int) BFD_RELOC_LO16
, AT
);
6234 if (target_big_endian
)
6235 expr1
.X_add_number
= 1;
6237 expr1
.X_add_number
= 0;
6238 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6239 (int) BFD_RELOC_LO16
, AT
);
6240 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6242 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6247 if (offset_expr
.X_add_number
>= 0x7fff)
6248 as_bad ("operand overflow");
6249 if (target_big_endian
)
6250 offset_expr
.X_add_number
+= 1;
6251 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6252 (int) BFD_RELOC_LO16
, breg
);
6253 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6254 if (target_big_endian
)
6255 offset_expr
.X_add_number
-= 1;
6257 offset_expr
.X_add_number
+= 1;
6258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6259 (int) BFD_RELOC_LO16
, breg
);
6272 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6273 as_bad ("operand overflow");
6274 if (! target_big_endian
)
6275 offset_expr
.X_add_number
+= off
;
6276 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6277 (int) BFD_RELOC_LO16
, breg
);
6278 if (! target_big_endian
)
6279 offset_expr
.X_add_number
-= off
;
6281 offset_expr
.X_add_number
+= off
;
6282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6283 (int) BFD_RELOC_LO16
, breg
);
6296 load_address (&icnt
, AT
, &offset_expr
);
6298 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6299 mips_opts
.isa
< 3 ? "addu" : "daddu",
6300 "d,v,t", AT
, AT
, breg
);
6301 if (! target_big_endian
)
6302 expr1
.X_add_number
= off
;
6304 expr1
.X_add_number
= 0;
6305 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6306 (int) BFD_RELOC_LO16
, AT
);
6307 if (! target_big_endian
)
6308 expr1
.X_add_number
= 0;
6310 expr1
.X_add_number
= off
;
6311 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6312 (int) BFD_RELOC_LO16
, AT
);
6316 load_address (&icnt
, AT
, &offset_expr
);
6318 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6319 mips_opts
.isa
< 3 ? "addu" : "daddu",
6320 "d,v,t", AT
, AT
, breg
);
6321 if (! target_big_endian
)
6322 expr1
.X_add_number
= 0;
6323 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6324 (int) BFD_RELOC_LO16
, AT
);
6325 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6327 if (! target_big_endian
)
6328 expr1
.X_add_number
= 1;
6330 expr1
.X_add_number
= 0;
6331 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6332 (int) BFD_RELOC_LO16
, AT
);
6333 if (! target_big_endian
)
6334 expr1
.X_add_number
= 0;
6336 expr1
.X_add_number
= 1;
6337 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6338 (int) BFD_RELOC_LO16
, AT
);
6339 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6341 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6346 /* FIXME: Check if this is one of the itbl macros, since they
6347 are added dynamically. */
6348 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6352 as_warn ("Macro used $at after \".set noat\"");
6355 /* Implement macros in mips16 mode. */
6359 struct mips_cl_insn
*ip
;
6362 int xreg
, yreg
, zreg
, tmp
;
6366 const char *s
, *s2
, *s3
;
6368 mask
= ip
->insn_mo
->mask
;
6370 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6371 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6372 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6376 expr1
.X_op
= O_constant
;
6377 expr1
.X_op_symbol
= NULL
;
6378 expr1
.X_add_symbol
= NULL
;
6379 expr1
.X_add_number
= 1;
6398 mips_emit_delays (true);
6399 ++mips_opts
.noreorder
;
6400 mips_any_noreorder
= 1;
6401 macro_build ((char *) NULL
, &icnt
, NULL
,
6402 dbl
? "ddiv" : "div",
6403 "0,x,y", xreg
, yreg
);
6404 expr1
.X_add_number
= 2;
6405 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6406 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6407 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6408 since that causes an overflow. We should do that as well,
6409 but I don't see how to do the comparisons without a temporary
6411 --mips_opts
.noreorder
;
6412 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6431 mips_emit_delays (true);
6432 ++mips_opts
.noreorder
;
6433 mips_any_noreorder
= 1;
6434 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6435 expr1
.X_add_number
= 2;
6436 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6437 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6438 --mips_opts
.noreorder
;
6439 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6445 macro_build ((char *) NULL
, &icnt
, NULL
,
6446 dbl
? "dmultu" : "multu",
6448 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6456 if (imm_expr
.X_op
!= O_constant
)
6457 as_bad ("Unsupported large constant");
6458 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6459 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6460 dbl
? "daddiu" : "addiu",
6461 "y,x,4", yreg
, xreg
);
6465 if (imm_expr
.X_op
!= O_constant
)
6466 as_bad ("Unsupported large constant");
6467 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6468 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6473 if (imm_expr
.X_op
!= O_constant
)
6474 as_bad ("Unsupported large constant");
6475 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6476 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6499 goto do_reverse_branch
;
6503 goto do_reverse_branch
;
6515 goto do_reverse_branch
;
6526 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6528 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6555 goto do_addone_branch_i
;
6560 goto do_addone_branch_i
;
6575 goto do_addone_branch_i
;
6582 if (imm_expr
.X_op
!= O_constant
)
6583 as_bad ("Unsupported large constant");
6584 ++imm_expr
.X_add_number
;
6587 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6588 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6592 expr1
.X_add_number
= 0;
6593 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6595 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6596 "move", "y,X", xreg
, yreg
);
6597 expr1
.X_add_number
= 2;
6598 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6599 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6600 "neg", "x,w", xreg
, xreg
);
6604 /* For consistency checking, verify that all bits are specified either
6605 by the match/mask part of the instruction definition, or by the
6608 validate_mips_insn (opc
)
6609 const struct mips_opcode
*opc
;
6611 const char *p
= opc
->args
;
6613 unsigned long used_bits
= opc
->mask
;
6615 if ((used_bits
& opc
->match
) != opc
->match
)
6617 as_bad ("internal: bad mips opcode (mask error): %s %s",
6618 opc
->name
, opc
->args
);
6621 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6628 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6629 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6631 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6632 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6633 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6634 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6636 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6639 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6640 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6641 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6642 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6643 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6644 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6645 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6646 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6647 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6648 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6649 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6651 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6652 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6653 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6654 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6656 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6657 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6658 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6659 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6660 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6661 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6662 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6663 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6666 /* start-sanitize-vr5400 */
6667 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6668 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
6669 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
6672 /* end-sanitize-vr5400 */
6674 as_bad ("internal: bad mips opcode (unknown operand type `%c'): %s %s",
6675 c
, opc
->name
, opc
->args
);
6679 /* Some of the trapping instructions (break, t*, sdbbp) have "code"
6680 fields that cannot currently be set by assembly code. Ignore them
6682 if (opc
->pinfo
& INSN_TRAP
)
6684 static const char *const trap_insns
[] = {
6686 "teq", "tge", "tgeu", "tlt", "tltu", "tne",
6689 for (i
= sizeof(trap_insns
)/sizeof(trap_insns
[0]) - 1; i
>= 0; i
--)
6690 if (!strcmp (trap_insns
[i
], opc
->name
))
6692 used_bits
|= 0xffc0;
6696 if (used_bits
!= 0xffffffff)
6698 as_bad ("internal: bad mips opcode (bits 0x%lx undefined): %s %s",
6699 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6705 /* This routine assembles an instruction into its binary format. As a
6706 side effect, it sets one of the global variables imm_reloc or
6707 offset_reloc to the type of relocation to do if one of the operands
6708 is an address expression. */
6713 struct mips_cl_insn
*ip
;
6718 struct mips_opcode
*insn
;
6721 unsigned int lastregno
= 0;
6726 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6731 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6733 insn_error
= "unrecognized opcode";
6742 assert (strcmp (insn
->name
, str
) == 0);
6744 if (insn
->pinfo
== INSN_MACRO
)
6745 insn_isa
= insn
->match
;
6746 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
6748 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
6750 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
6752 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
6757 if (insn_isa
<= mips_opts
.isa
)
6759 else if (insn
->pinfo
== INSN_MACRO
)
6761 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
6762 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
6763 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
6764 /* start-sanitize-r5900 */
6765 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
6766 /* end-sanitize-r5900 */
6767 /* start-sanitize-vr5400 */
6768 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
6769 /* end-sanitize-vr5400 */
6770 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
6773 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
6775 /* start-sanitize-r5900 */
6776 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
6778 /* end-sanitize-r5900 */
6785 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6786 && strcmp (insn
->name
, insn
[1].name
) == 0)
6792 || insn_isa
<= mips_opts
.isa
)
6793 insn_error
= "opcode not supported on this processor";
6796 static char buf
[100];
6798 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6805 ip
->insn_opcode
= insn
->match
;
6806 for (args
= insn
->args
;; ++args
)
6812 case '\0': /* end of args */
6825 ip
->insn_opcode
|= lastregno
<< 21;
6830 ip
->insn_opcode
|= lastregno
<< 16;
6834 ip
->insn_opcode
|= lastregno
<< 11;
6840 /* handle optional base register.
6841 Either the base register is omitted or
6842 we must have a left paren. */
6843 /* this is dependent on the next operand specifier
6844 is a 'b' for base register */
6845 assert (args
[1] == 'b');
6849 case ')': /* these must match exactly */
6850 /* start-sanitize-vr5400 */
6853 /* end-sanitize-vr5400 */
6858 case '<': /* must be at least one digit */
6860 * According to the manual, if the shift amount is greater
6861 * than 31 or less than 0 the the shift amount should be
6862 * mod 32. In reality the mips assembler issues an error.
6863 * We issue a warning and mask out all but the low 5 bits.
6865 my_getExpression (&imm_expr
, s
);
6866 check_absolute_expr (ip
, &imm_expr
);
6867 if ((unsigned long) imm_expr
.X_add_number
> 31)
6869 as_warn ("Improper shift amount (%ld)",
6870 (long) imm_expr
.X_add_number
);
6871 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6873 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6874 imm_expr
.X_op
= O_absent
;
6878 case '>': /* shift amount minus 32 */
6879 my_getExpression (&imm_expr
, s
);
6880 check_absolute_expr (ip
, &imm_expr
);
6881 if ((unsigned long) imm_expr
.X_add_number
< 32
6882 || (unsigned long) imm_expr
.X_add_number
> 63)
6884 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6885 imm_expr
.X_op
= O_absent
;
6889 case 'k': /* cache code */
6890 case 'h': /* prefx code */
6891 my_getExpression (&imm_expr
, s
);
6892 check_absolute_expr (ip
, &imm_expr
);
6893 if ((unsigned long) imm_expr
.X_add_number
> 31)
6895 as_warn ("Invalid value for `%s' (%lu)",
6897 (unsigned long) imm_expr
.X_add_number
);
6898 imm_expr
.X_add_number
&= 0x1f;
6901 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6903 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6904 imm_expr
.X_op
= O_absent
;
6908 case 'c': /* break code */
6909 my_getExpression (&imm_expr
, s
);
6910 check_absolute_expr (ip
, &imm_expr
);
6911 if ((unsigned) imm_expr
.X_add_number
> 1023)
6912 as_warn ("Illegal break code (%ld)",
6913 (long) imm_expr
.X_add_number
);
6914 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6915 imm_expr
.X_op
= O_absent
;
6919 case 'B': /* syscall code */
6920 my_getExpression (&imm_expr
, s
);
6921 check_absolute_expr (ip
, &imm_expr
);
6922 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6923 as_warn ("Illegal syscall code (%ld)",
6924 (long) imm_expr
.X_add_number
);
6925 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6926 imm_expr
.X_op
= O_absent
;
6930 case 'C': /* Coprocessor code */
6931 my_getExpression (&imm_expr
, s
);
6932 check_absolute_expr (ip
, &imm_expr
);
6933 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6935 as_warn ("Coproccesor code > 25 bits (%ld)",
6936 (long) imm_expr
.X_add_number
);
6937 imm_expr
.X_add_number
&= ((1<<25) - 1);
6939 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6940 imm_expr
.X_op
= O_absent
;
6944 case 'b': /* base register */
6945 case 'd': /* destination register */
6946 case 's': /* source register */
6947 case 't': /* target register */
6948 case 'r': /* both target and source */
6949 case 'v': /* both dest and source */
6950 case 'w': /* both dest and target */
6951 case 'E': /* coprocessor target register */
6952 case 'G': /* coprocessor destination register */
6953 case 'x': /* ignore register name */
6954 case 'z': /* must be zero register */
6968 while (isdigit (*s
));
6970 as_bad ("Invalid register number (%d)", regno
);
6972 else if (*args
== 'E' || *args
== 'G')
6976 if (s
[1] == 'f' && s
[2] == 'p')
6981 else if (s
[1] == 's' && s
[2] == 'p')
6986 else if (s
[1] == 'g' && s
[2] == 'p')
6991 else if (s
[1] == 'a' && s
[2] == 't')
6996 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7001 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7006 else if (itbl_have_entries
)
7011 p
= s
+1; /* advance past '$' */
7012 n
= itbl_get_field (&p
); /* n is name */
7014 /* See if this is a register defined in an
7016 r
= itbl_get_reg_val (n
);
7019 /* Get_field advances to the start of
7020 the next field, so we need to back
7021 rack to the end of the last field. */
7025 s
= strchr (s
,'\0');
7038 as_warn ("Used $at without \".set noat\"");
7044 if (c
== 'r' || c
== 'v' || c
== 'w')
7051 /* 'z' only matches $0. */
7052 if (c
== 'z' && regno
!= 0)
7055 /* Now that we have assembled one operand, we use the args string
7056 * to figure out where it goes in the instruction. */
7063 ip
->insn_opcode
|= regno
<< 21;
7067 ip
->insn_opcode
|= regno
<< 11;
7072 ip
->insn_opcode
|= regno
<< 16;
7075 /* This case exists because on the r3000 trunc
7076 expands into a macro which requires a gp
7077 register. On the r6000 or r4000 it is
7078 assembled into a single instruction which
7079 ignores the register. Thus the insn version
7080 is MIPS_ISA2 and uses 'x', and the macro
7081 version is MIPS_ISA1 and uses 't'. */
7084 /* This case is for the div instruction, which
7085 acts differently if the destination argument
7086 is $0. This only matches $0, and is checked
7087 outside the switch. */
7090 /* Itbl operand; not yet implemented. FIXME ?? */
7092 /* What about all other operands like 'i', which
7093 can be specified in the opcode table? */
7103 ip
->insn_opcode
|= lastregno
<< 21;
7106 ip
->insn_opcode
|= lastregno
<< 16;
7111 case 'D': /* floating point destination register */
7112 case 'S': /* floating point source register */
7113 case 'T': /* floating point target register */
7114 case 'R': /* floating point source register */
7118 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7128 while (isdigit (*s
));
7131 as_bad ("Invalid float register number (%d)", regno
);
7133 if ((regno
& 1) != 0
7134 && mips_opts
.isa
< 3
7135 && ! (strcmp (str
, "mtc1") == 0
7136 || strcmp (str
, "mfc1") == 0
7137 || strcmp (str
, "lwc1") == 0
7138 || strcmp (str
, "swc1") == 0
7139 || strcmp (str
, "l.s") == 0
7140 || strcmp (str
, "s.s") == 0))
7141 as_warn ("Float register should be even, was %d",
7149 if (c
== 'V' || c
== 'W')
7159 ip
->insn_opcode
|= regno
<< 6;
7163 ip
->insn_opcode
|= regno
<< 11;
7167 ip
->insn_opcode
|= regno
<< 16;
7170 ip
->insn_opcode
|= regno
<< 21;
7179 ip
->insn_opcode
|= lastregno
<< 11;
7182 ip
->insn_opcode
|= lastregno
<< 16;
7188 my_getExpression (&imm_expr
, s
);
7189 if (imm_expr
.X_op
!= O_big
7190 && imm_expr
.X_op
!= O_constant
)
7191 insn_error
= "absolute expression required";
7196 my_getExpression (&offset_expr
, s
);
7197 imm_reloc
= BFD_RELOC_32
;
7209 unsigned char temp
[8];
7211 unsigned int length
;
7216 /* These only appear as the last operand in an
7217 instruction, and every instruction that accepts
7218 them in any variant accepts them in all variants.
7219 This means we don't have to worry about backing out
7220 any changes if the instruction does not match.
7222 The difference between them is the size of the
7223 floating point constant and where it goes. For 'F'
7224 and 'L' the constant is 64 bits; for 'f' and 'l' it
7225 is 32 bits. Where the constant is placed is based
7226 on how the MIPS assembler does things:
7229 f -- immediate value
7232 The .lit4 and .lit8 sections are only used if
7233 permitted by the -G argument.
7235 When generating embedded PIC code, we use the
7236 .lit8 section but not the .lit4 section (we can do
7237 .lit4 inline easily; we need to put .lit8
7238 somewhere in the data segment, and using .lit8
7239 permits the linker to eventually combine identical
7242 f64
= *args
== 'F' || *args
== 'L';
7244 save_in
= input_line_pointer
;
7245 input_line_pointer
= s
;
7246 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7248 s
= input_line_pointer
;
7249 input_line_pointer
= save_in
;
7250 if (err
!= NULL
&& *err
!= '\0')
7252 as_bad ("Bad floating point constant: %s", err
);
7253 memset (temp
, '\0', sizeof temp
);
7254 length
= f64
? 8 : 4;
7257 assert (length
== (f64
? 8 : 4));
7261 && (! USE_GLOBAL_POINTER_OPT
7262 || mips_pic
== EMBEDDED_PIC
7263 || g_switch_value
< 4
7264 || (temp
[0] == 0 && temp
[1] == 0)
7265 || (temp
[2] == 0 && temp
[3] == 0))))
7267 imm_expr
.X_op
= O_constant
;
7268 if (! target_big_endian
)
7269 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7271 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7274 && ((temp
[0] == 0 && temp
[1] == 0)
7275 || (temp
[2] == 0 && temp
[3] == 0))
7276 && ((temp
[4] == 0 && temp
[5] == 0)
7277 || (temp
[6] == 0 && temp
[7] == 0)))
7279 /* The value is simple enough to load with a
7280 couple of instructions. In mips1 mode, set
7281 imm_expr to the high order 32 bits and
7282 offset_expr to the low order 32 bits.
7283 Otherwise, set imm_expr to the entire 64 bit
7285 if (mips_opts
.isa
< 3)
7287 imm_expr
.X_op
= O_constant
;
7288 offset_expr
.X_op
= O_constant
;
7289 if (! target_big_endian
)
7291 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7292 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7296 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7297 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7299 if (offset_expr
.X_add_number
== 0)
7300 offset_expr
.X_op
= O_absent
;
7302 else if (sizeof (imm_expr
.X_add_number
) > 4)
7304 imm_expr
.X_op
= O_constant
;
7305 if (! target_big_endian
)
7306 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7308 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7312 imm_expr
.X_op
= O_big
;
7313 imm_expr
.X_add_number
= 4;
7314 if (! target_big_endian
)
7316 generic_bignum
[0] = bfd_getl16 (temp
);
7317 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7318 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7319 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7323 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7324 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7325 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7326 generic_bignum
[3] = bfd_getb16 (temp
);
7332 const char *newname
;
7335 /* Switch to the right section. */
7337 subseg
= now_subseg
;
7340 default: /* unused default case avoids warnings. */
7342 newname
= RDATA_SECTION_NAME
;
7343 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7347 newname
= RDATA_SECTION_NAME
;
7350 assert (!USE_GLOBAL_POINTER_OPT
7351 || g_switch_value
>= 4);
7355 new_seg
= subseg_new (newname
, (subsegT
) 0);
7356 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7357 bfd_set_section_flags (stdoutput
, new_seg
,
7362 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7363 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7364 && strcmp (TARGET_OS
, "elf") != 0)
7365 record_alignment (new_seg
, 4);
7367 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7369 as_bad ("Can't use floating point insn in this section");
7371 /* Set the argument to the current address in the
7373 offset_expr
.X_op
= O_symbol
;
7374 offset_expr
.X_add_symbol
=
7375 symbol_new ("L0\001", now_seg
,
7376 (valueT
) frag_now_fix (), frag_now
);
7377 offset_expr
.X_add_number
= 0;
7379 /* Put the floating point number into the section. */
7380 p
= frag_more ((int) length
);
7381 memcpy (p
, temp
, length
);
7383 /* Switch back to the original section. */
7384 subseg_set (seg
, subseg
);
7389 case 'i': /* 16 bit unsigned immediate */
7390 case 'j': /* 16 bit signed immediate */
7391 imm_reloc
= BFD_RELOC_LO16
;
7392 c
= my_getSmallExpression (&imm_expr
, s
);
7397 if (imm_expr
.X_op
== O_constant
)
7398 imm_expr
.X_add_number
=
7399 (imm_expr
.X_add_number
>> 16) & 0xffff;
7402 imm_reloc
= BFD_RELOC_HI16_S
;
7403 imm_unmatched_hi
= true;
7406 imm_reloc
= BFD_RELOC_HI16
;
7411 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7412 || ((imm_expr
.X_add_number
< 0
7413 || imm_expr
.X_add_number
>= 0x10000)
7414 && imm_expr
.X_op
== O_constant
))
7416 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7417 !strcmp (insn
->name
, insn
[1].name
))
7419 if (imm_expr
.X_op
!= O_constant
7420 && imm_expr
.X_op
!= O_big
)
7421 insn_error
= "absolute expression required";
7423 as_bad ("16 bit expression not in range 0..65535");
7431 /* The upper bound should be 0x8000, but
7432 unfortunately the MIPS assembler accepts numbers
7433 from 0x8000 to 0xffff and sign extends them, and
7434 we want to be compatible. We only permit this
7435 extended range for an instruction which does not
7436 provide any further alternates, since those
7437 alternates may handle other cases. People should
7438 use the numbers they mean, rather than relying on
7439 a mysterious sign extension. */
7440 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7441 strcmp (insn
->name
, insn
[1].name
) == 0);
7446 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7447 || ((imm_expr
.X_add_number
< -0x8000
7448 || imm_expr
.X_add_number
>= max
)
7449 && imm_expr
.X_op
== O_constant
)
7451 && imm_expr
.X_add_number
< 0
7452 && mips_opts
.isa
>= 3
7453 && imm_expr
.X_unsigned
7454 && sizeof (imm_expr
.X_add_number
) <= 4))
7458 if (imm_expr
.X_op
!= O_constant
7459 && imm_expr
.X_op
!= O_big
)
7460 insn_error
= "absolute expression required";
7462 as_bad ("16 bit expression not in range -32768..32767");
7468 case 'o': /* 16 bit offset */
7469 c
= my_getSmallExpression (&offset_expr
, s
);
7471 /* If this value won't fit into a 16 bit offset, then go
7472 find a macro that will generate the 32 bit offset
7473 code pattern. As a special hack, we accept the
7474 difference of two local symbols as a constant. This
7475 is required to suppose embedded PIC switches, which
7476 use an instruction which looks like
7477 lw $4,$L12-$LS12($4)
7478 The problem with handling this in a more general
7479 fashion is that the macro function doesn't expect to
7480 see anything which can be handled in a single
7481 constant instruction. */
7483 && (offset_expr
.X_op
!= O_constant
7484 || offset_expr
.X_add_number
>= 0x8000
7485 || offset_expr
.X_add_number
< -0x8000)
7486 && (mips_pic
!= EMBEDDED_PIC
7487 || offset_expr
.X_op
!= O_subtract
7488 || now_seg
!= text_section
7489 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7493 offset_reloc
= BFD_RELOC_LO16
;
7494 if (c
== 'h' || c
== 'H')
7496 assert (offset_expr
.X_op
== O_constant
);
7497 offset_expr
.X_add_number
=
7498 (offset_expr
.X_add_number
>> 16) & 0xffff;
7503 case 'p': /* pc relative offset */
7504 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7505 my_getExpression (&offset_expr
, s
);
7509 case 'u': /* upper 16 bits */
7510 c
= my_getSmallExpression (&imm_expr
, s
);
7511 if (imm_expr
.X_op
== O_constant
7512 && (imm_expr
.X_add_number
< 0
7513 || imm_expr
.X_add_number
>= 0x10000))
7514 as_bad ("lui expression not in range 0..65535");
7515 imm_reloc
= BFD_RELOC_LO16
;
7520 if (imm_expr
.X_op
== O_constant
)
7521 imm_expr
.X_add_number
=
7522 (imm_expr
.X_add_number
>> 16) & 0xffff;
7525 imm_reloc
= BFD_RELOC_HI16_S
;
7526 imm_unmatched_hi
= true;
7529 imm_reloc
= BFD_RELOC_HI16
;
7535 case 'a': /* 26 bit address */
7536 my_getExpression (&offset_expr
, s
);
7538 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7541 case 'N': /* 3 bit branch condition code */
7542 case 'M': /* 3 bit compare condition code */
7543 if (strncmp (s
, "$fcc", 4) != 0)
7553 while (isdigit (*s
));
7555 as_bad ("invalid condition code register $fcc%d", regno
);
7557 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7559 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7563 fprintf (stderr
, "bad char = '%c'\n", *args
);
7568 /* Args don't match. */
7569 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7570 !strcmp (insn
->name
, insn
[1].name
))
7576 insn_error
= "illegal operands";
7581 /* This routine assembles an instruction into its binary format when
7582 assembling for the mips16. As a side effect, it sets one of the
7583 global variables imm_reloc or offset_reloc to the type of
7584 relocation to do if one of the operands is an address expression.
7585 It also sets mips16_small and mips16_ext if the user explicitly
7586 requested a small or extended instruction. */
7591 struct mips_cl_insn
*ip
;
7595 struct mips_opcode
*insn
;
7598 unsigned int lastregno
= 0;
7603 mips16_small
= false;
7606 for (s
= str
; islower (*s
); ++s
)
7618 if (s
[1] == 't' && s
[2] == ' ')
7621 mips16_small
= true;
7625 else if (s
[1] == 'e' && s
[2] == ' ')
7634 insn_error
= "unknown opcode";
7638 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7639 mips16_small
= true;
7641 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7643 insn_error
= "unrecognized opcode";
7650 assert (strcmp (insn
->name
, str
) == 0);
7653 ip
->insn_opcode
= insn
->match
;
7654 ip
->use_extend
= false;
7655 imm_expr
.X_op
= O_absent
;
7656 imm_reloc
= BFD_RELOC_UNUSED
;
7657 offset_expr
.X_op
= O_absent
;
7658 offset_reloc
= BFD_RELOC_UNUSED
;
7659 for (args
= insn
->args
; 1; ++args
)
7666 /* In this switch statement we call break if we did not find
7667 a match, continue if we did find a match, or return if we
7676 /* Stuff the immediate value in now, if we can. */
7677 if (imm_expr
.X_op
== O_constant
7678 && imm_reloc
> BFD_RELOC_UNUSED
7679 && insn
->pinfo
!= INSN_MACRO
)
7681 mips16_immed ((char *) NULL
, 0,
7682 imm_reloc
- BFD_RELOC_UNUSED
,
7683 imm_expr
.X_add_number
, true, mips16_small
,
7684 mips16_ext
, &ip
->insn_opcode
,
7685 &ip
->use_extend
, &ip
->extend
);
7686 imm_expr
.X_op
= O_absent
;
7687 imm_reloc
= BFD_RELOC_UNUSED
;
7701 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7704 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7720 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7722 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7749 while (isdigit (*s
));
7752 as_bad ("invalid register number (%d)", regno
);
7758 if (s
[1] == 'f' && s
[2] == 'p')
7763 else if (s
[1] == 's' && s
[2] == 'p')
7768 else if (s
[1] == 'g' && s
[2] == 'p')
7773 else if (s
[1] == 'a' && s
[2] == 't')
7778 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7783 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7796 if (c
== 'v' || c
== 'w')
7798 regno
= mips16_to_32_reg_map
[lastregno
];
7812 regno
= mips32_to_16_reg_map
[regno
];
7817 regno
= ILLEGAL_REG
;
7822 regno
= ILLEGAL_REG
;
7827 regno
= ILLEGAL_REG
;
7832 if (regno
== AT
&& ! mips_opts
.noat
)
7833 as_warn ("used $at without \".set noat\"");
7840 if (regno
== ILLEGAL_REG
)
7847 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7851 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7854 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7857 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7863 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7866 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7867 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7877 if (strncmp (s
, "$pc", 3) == 0)
7901 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7903 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7904 and generate the appropriate reloc. If the text
7905 inside %gprel is not a symbol name with an
7906 optional offset, then we generate a normal reloc
7907 and will probably fail later. */
7908 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7909 if (imm_expr
.X_op
== O_symbol
)
7912 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7914 ip
->use_extend
= true;
7921 /* Just pick up a normal expression. */
7922 my_getExpression (&imm_expr
, s
);
7925 if (imm_expr
.X_op
== O_register
)
7927 /* What we thought was an expression turned out to
7930 if (s
[0] == '(' && args
[1] == '(')
7932 /* It looks like the expression was omitted
7933 before a register indirection, which means
7934 that the expression is implicitly zero. We
7935 still set up imm_expr, so that we handle
7936 explicit extensions correctly. */
7937 imm_expr
.X_op
= O_constant
;
7938 imm_expr
.X_add_number
= 0;
7939 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7946 /* We need to relax this instruction. */
7947 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7956 /* We use offset_reloc rather than imm_reloc for the PC
7957 relative operands. This lets macros with both
7958 immediate and address operands work correctly. */
7959 my_getExpression (&offset_expr
, s
);
7961 if (offset_expr
.X_op
== O_register
)
7964 /* We need to relax this instruction. */
7965 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7969 case '6': /* break code */
7970 my_getExpression (&imm_expr
, s
);
7971 check_absolute_expr (ip
, &imm_expr
);
7972 if ((unsigned long) imm_expr
.X_add_number
> 63)
7974 as_warn ("Invalid value for `%s' (%lu)",
7976 (unsigned long) imm_expr
.X_add_number
);
7977 imm_expr
.X_add_number
&= 0x3f;
7979 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7980 imm_expr
.X_op
= O_absent
;
7984 case 'a': /* 26 bit address */
7985 my_getExpression (&offset_expr
, s
);
7987 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7988 ip
->insn_opcode
<<= 16;
7991 case 'l': /* register list for entry macro */
7992 case 'L': /* register list for exit macro */
8002 int freg
, reg1
, reg2
;
8004 while (*s
== ' ' || *s
== ',')
8008 as_bad ("can't parse register list");
8020 while (isdigit (*s
))
8042 as_bad ("invalid register list");
8047 while (isdigit (*s
))
8054 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8059 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8064 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8065 mask
|= (reg2
- 3) << 3;
8066 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8067 mask
|= (reg2
- 15) << 1;
8068 else if (reg1
== 31 && reg2
== 31)
8072 as_bad ("invalid register list");
8076 /* The mask is filled in in the opcode table for the
8077 benefit of the disassembler. We remove it before
8078 applying the actual mask. */
8079 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8080 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8084 case 'e': /* extend code */
8085 my_getExpression (&imm_expr
, s
);
8086 check_absolute_expr (ip
, &imm_expr
);
8087 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8089 as_warn ("Invalid value for `%s' (%lu)",
8091 (unsigned long) imm_expr
.X_add_number
);
8092 imm_expr
.X_add_number
&= 0x7ff;
8094 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8095 imm_expr
.X_op
= O_absent
;
8105 /* Args don't match. */
8106 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8107 strcmp (insn
->name
, insn
[1].name
) == 0)
8114 insn_error
= "illegal operands";
8120 /* This structure holds information we know about a mips16 immediate
8123 struct mips16_immed_operand
8125 /* The type code used in the argument string in the opcode table. */
8127 /* The number of bits in the short form of the opcode. */
8129 /* The number of bits in the extended form of the opcode. */
8131 /* The amount by which the short form is shifted when it is used;
8132 for example, the sw instruction has a shift count of 2. */
8134 /* The amount by which the short form is shifted when it is stored
8135 into the instruction code. */
8137 /* Non-zero if the short form is unsigned. */
8139 /* Non-zero if the extended form is unsigned. */
8141 /* Non-zero if the value is PC relative. */
8145 /* The mips16 immediate operand types. */
8147 static const struct mips16_immed_operand mips16_immed_operands
[] =
8149 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8150 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8151 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8152 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8153 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8154 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8155 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8156 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8157 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8158 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8159 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8160 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8161 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8162 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8163 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8164 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8165 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8166 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8167 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8168 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8169 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8172 #define MIPS16_NUM_IMMED \
8173 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8175 /* Handle a mips16 instruction with an immediate value. This or's the
8176 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8177 whether an extended value is needed; if one is needed, it sets
8178 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8179 If SMALL is true, an unextended opcode was explicitly requested.
8180 If EXT is true, an extended opcode was explicitly requested. If
8181 WARN is true, warn if EXT does not match reality. */
8184 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8193 unsigned long *insn
;
8194 boolean
*use_extend
;
8195 unsigned short *extend
;
8197 register const struct mips16_immed_operand
*op
;
8198 int mintiny
, maxtiny
;
8201 op
= mips16_immed_operands
;
8202 while (op
->type
!= type
)
8205 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8210 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8213 maxtiny
= 1 << op
->nbits
;
8218 maxtiny
= (1 << op
->nbits
) - 1;
8223 mintiny
= - (1 << (op
->nbits
- 1));
8224 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8227 /* Branch offsets have an implicit 0 in the lowest bit. */
8228 if (type
== 'p' || type
== 'q')
8231 if ((val
& ((1 << op
->shift
) - 1)) != 0
8232 || val
< (mintiny
<< op
->shift
)
8233 || val
> (maxtiny
<< op
->shift
))
8238 if (warn
&& ext
&& ! needext
)
8239 as_warn_where (file
, line
, "extended operand requested but not required");
8240 if (small
&& needext
)
8241 as_bad_where (file
, line
, "invalid unextended operand value");
8243 if (small
|| (! ext
&& ! needext
))
8247 *use_extend
= false;
8248 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8249 insnval
<<= op
->op_shift
;
8254 long minext
, maxext
;
8260 maxext
= (1 << op
->extbits
) - 1;
8264 minext
= - (1 << (op
->extbits
- 1));
8265 maxext
= (1 << (op
->extbits
- 1)) - 1;
8267 if (val
< minext
|| val
> maxext
)
8268 as_bad_where (file
, line
,
8269 "operand value out of range for instruction");
8272 if (op
->extbits
== 16)
8274 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8277 else if (op
->extbits
== 15)
8279 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8284 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8288 *extend
= (unsigned short) extval
;
8297 my_getSmallExpression (ep
, str
)
8308 ((str
[1] == 'h' && str
[2] == 'i')
8309 || (str
[1] == 'H' && str
[2] == 'I')
8310 || (str
[1] == 'l' && str
[2] == 'o'))
8322 * A small expression may be followed by a base register.
8323 * Scan to the end of this operand, and then back over a possible
8324 * base register. Then scan the small expression up to that
8325 * point. (Based on code in sparc.c...)
8327 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8329 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8331 if (isdigit (sp
[-2]))
8333 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8335 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8341 else if (sp
- 5 >= str
8344 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8345 || (sp
[-3] == 's' && sp
[-2] == 'p')
8346 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8347 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8353 /* no expression means zero offset */
8356 /* %xx(reg) is an error */
8357 ep
->X_op
= O_absent
;
8362 ep
->X_op
= O_constant
;
8365 ep
->X_add_symbol
= NULL
;
8366 ep
->X_op_symbol
= NULL
;
8367 ep
->X_add_number
= 0;
8372 my_getExpression (ep
, str
);
8379 my_getExpression (ep
, str
);
8380 return c
; /* => %hi or %lo encountered */
8384 my_getExpression (ep
, str
)
8390 save_in
= input_line_pointer
;
8391 input_line_pointer
= str
;
8393 expr_end
= input_line_pointer
;
8394 input_line_pointer
= save_in
;
8396 /* If we are in mips16 mode, and this is an expression based on `.',
8397 then we bump the value of the symbol by 1 since that is how other
8398 text symbols are handled. We don't bother to handle complex
8399 expressions, just `.' plus or minus a constant. */
8400 if (mips_opts
.mips16
8401 && ep
->X_op
== O_symbol
8402 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8403 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8404 && ep
->X_add_symbol
->sy_frag
== frag_now
8405 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8406 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8407 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8410 /* Turn a string in input_line_pointer into a floating point constant
8411 of type type, and store the appropriate bytes in *litP. The number
8412 of LITTLENUMS emitted is stored in *sizeP . An error message is
8413 returned, or NULL on OK. */
8416 md_atof (type
, litP
, sizeP
)
8422 LITTLENUM_TYPE words
[4];
8438 return "bad call to md_atof";
8441 t
= atof_ieee (input_line_pointer
, type
, words
);
8443 input_line_pointer
= t
;
8447 if (! target_big_endian
)
8449 for (i
= prec
- 1; i
>= 0; i
--)
8451 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8457 for (i
= 0; i
< prec
; i
++)
8459 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8468 md_number_to_chars (buf
, val
, n
)
8473 if (target_big_endian
)
8474 number_to_chars_bigendian (buf
, val
, n
);
8476 number_to_chars_littleendian (buf
, val
, n
);
8479 CONST
char *md_shortopts
= "O::g::G:";
8481 struct option md_longopts
[] = {
8482 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8483 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8484 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8485 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8486 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8487 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8488 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8489 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8490 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8491 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8492 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8493 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8494 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8495 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8496 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8497 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8498 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8499 {"break", no_argument
, NULL
, OPTION_BREAK
},
8500 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8501 #define OPTION_EB (OPTION_MD_BASE + 11)
8502 {"EB", no_argument
, NULL
, OPTION_EB
},
8503 #define OPTION_EL (OPTION_MD_BASE + 12)
8504 {"EL", no_argument
, NULL
, OPTION_EL
},
8505 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8506 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8507 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8508 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8509 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8510 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8511 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8512 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8513 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8514 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8515 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8516 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8517 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8518 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8519 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8520 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8521 /* start-sanitize-r5900 */
8522 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8523 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8524 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8525 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8526 /* end-sanitize-r5900 */
8527 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8528 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8529 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8530 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8532 /* start-sanitize-tx19 */
8533 {"m1900", no_argument
, NULL
, OPTION_M3900
},
8534 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
8535 /* end-sanitize-tx19 */
8537 /* start-sanitize-vr5400 */
8538 #define OPTION_M5400 (OPTION_MD_BASE + 28)
8539 {"m5400", no_argument
, NULL
, OPTION_M5400
},
8540 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
8541 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
8543 /* end-sanitize-vr5400 */
8544 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8545 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8546 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8547 #define OPTION_32 (OPTION_MD_BASE + 20)
8548 #define OPTION_64 (OPTION_MD_BASE + 21)
8550 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8551 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8552 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8553 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8554 {"32", no_argument
, NULL
, OPTION_32
},
8555 {"64", no_argument
, NULL
, OPTION_64
},
8558 {NULL
, no_argument
, NULL
, 0}
8560 size_t md_longopts_size
= sizeof(md_longopts
);
8563 md_parse_option (c
, arg
)
8578 target_big_endian
= 1;
8582 target_big_endian
= 0;
8586 if (arg
&& arg
[1] == '0')
8596 mips_debug
= atoi (arg
);
8597 /* When the MIPS assembler sees -g or -g2, it does not do
8598 optimizations which limit full symbolic debugging. We take
8599 that to be equivalent to -O0. */
8600 if (mips_debug
== 2)
8632 /* Identify the processor type */
8634 if (strcmp (p
, "default") == 0
8635 || strcmp (p
, "DEFAULT") == 0)
8641 /* We need to cope with the various "vr" prefixes for the 4300
8643 if (*p
== 'v' || *p
== 'V')
8649 if (*p
== 'r' || *p
== 'R')
8656 if (strcmp (p
, "10000") == 0
8657 || strcmp (p
, "10k") == 0
8658 || strcmp (p
, "10K") == 0)
8660 /* start-sanitize-tx19 */
8661 else if (strcmp (p
, "1900") == 0)
8663 /* end-sanitize-tx19 */
8667 if (strcmp (p
, "2000") == 0
8668 || strcmp (p
, "2k") == 0
8669 || strcmp (p
, "2K") == 0)
8674 if (strcmp (p
, "3000") == 0
8675 || strcmp (p
, "3k") == 0
8676 || strcmp (p
, "3K") == 0)
8678 else if (strcmp (p
, "3900") == 0)
8683 if (strcmp (p
, "4000") == 0
8684 || strcmp (p
, "4k") == 0
8685 || strcmp (p
, "4K") == 0)
8687 else if (strcmp (p
, "4100") == 0)
8693 else if (strcmp (p
, "4300") == 0)
8695 else if (strcmp (p
, "4400") == 0)
8697 else if (strcmp (p
, "4600") == 0)
8699 else if (strcmp (p
, "4650") == 0)
8705 /* start-sanitize-tx49 */
8706 else if (strcmp (p
, "4900") == 0)
8708 /* end-sanitize-tx49 */
8709 else if (strcmp (p
, "4010") == 0)
8718 if (strcmp (p
, "5000") == 0
8719 || strcmp (p
, "5k") == 0
8720 || strcmp (p
, "5K") == 0)
8722 /* start-sanitize-vr5400 */
8723 else if (strcmp (p
, "5400") == 0)
8725 /* end-sanitize-vr5400 */
8726 /* start-sanitize-r5900 */
8727 else if (strcmp (p
, "5900") == 0)
8729 /* end-sanitize-r5900 */
8733 if (strcmp (p
, "6000") == 0
8734 || strcmp (p
, "6k") == 0
8735 || strcmp (p
, "6K") == 0)
8740 if (strcmp (p
, "8000") == 0
8741 || strcmp (p
, "8k") == 0
8742 || strcmp (p
, "8K") == 0)
8747 if (strcmp (p
, "orion") == 0)
8752 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8754 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8760 as_bad ("invalid architecture -mcpu=%s", arg
);
8771 case OPTION_NO_M4650
:
8779 case OPTION_NO_M4010
:
8787 case OPTION_NO_M4100
:
8791 /* start-sanitize-r5900 */
8796 case OPTION_NO_M5900
:
8799 /* end-sanitize-r5900 */
8801 /* start-sanitize-vr5400 */
8806 case OPTION_NO_M5400
:
8810 /* end-sanitize-vr5400 */
8815 case OPTION_NO_M3900
:
8820 mips_opts
.mips16
= 1;
8821 mips_no_prev_insn (false);
8824 case OPTION_NO_MIPS16
:
8825 mips_opts
.mips16
= 0;
8826 mips_no_prev_insn (false);
8829 case OPTION_MEMBEDDED_PIC
:
8830 mips_pic
= EMBEDDED_PIC
;
8831 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8833 as_bad ("-G may not be used with embedded PIC code");
8836 g_switch_value
= 0x7fffffff;
8839 /* When generating ELF code, we permit -KPIC and -call_shared to
8840 select SVR4_PIC, and -non_shared to select no PIC. This is
8841 intended to be compatible with Irix 5. */
8842 case OPTION_CALL_SHARED
:
8843 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8845 as_bad ("-call_shared is supported only for ELF format");
8848 mips_pic
= SVR4_PIC
;
8849 if (g_switch_seen
&& g_switch_value
!= 0)
8851 as_bad ("-G may not be used with SVR4 PIC code");
8857 case OPTION_NON_SHARED
:
8858 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8860 as_bad ("-non_shared is supported only for ELF format");
8866 /* The -xgot option tells the assembler to use 32 offsets when
8867 accessing the got in SVR4_PIC mode. It is for Irix
8874 if (! USE_GLOBAL_POINTER_OPT
)
8876 as_bad ("-G is not supported for this configuration");
8879 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8881 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8885 g_switch_value
= atoi (arg
);
8889 /* The -32 and -64 options tell the assembler to output the 32
8890 bit or the 64 bit MIPS ELF format. */
8897 const char **list
, **l
;
8899 list
= bfd_target_list ();
8900 for (l
= list
; *l
!= NULL
; l
++)
8901 if (strcmp (*l
, "elf64-bigmips") == 0
8902 || strcmp (*l
, "elf64-littlemips") == 0)
8905 as_fatal ("No compiled in support for 64 bit object file format");
8919 md_show_usage (stream
)
8924 -membedded-pic generate embedded position independent code\n\
8925 -EB generate big endian output\n\
8926 -EL generate little endian output\n\
8927 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8928 -G NUM allow referencing objects up to NUM bytes\n\
8929 implicitly with the gp register [default 8]\n");
8931 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8932 -mips2, -mcpu=r6000 generate code for r6000\n\
8933 -mips3, -mcpu=r4000 generate code for r4000\n\
8934 -mips4, -mcpu=r8000 generate code for r8000\n\
8935 -mcpu=vr4300 generate code for vr4300\n\
8936 -mcpu=vr4100 generate code for vr4100\n\
8937 -m4650 permit R4650 instructions\n\
8938 -no-m4650 do not permit R4650 instructions\n\
8939 -m4010 permit R4010 instructions\n\
8940 -no-m4010 do not permit R4010 instructions\n\
8941 -m4100 permit VR4100 instructions\n\
8942 -no-m4100 do not permit VR4100 instructions\n");
8944 -mips16 generate mips16 instructions\n\
8945 -no-mips16 do not generate mips16 instructions\n");
8947 -O0 remove unneeded NOPs, do not swap branches\n\
8948 -O remove unneeded NOPs and swap branches\n\
8949 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8950 --break, --no-trap break exception on div by 0 and mult overflow\n");
8953 -KPIC, -call_shared generate SVR4 position independent code\n\
8954 -non_shared do not generate position independent code\n\
8955 -xgot assume a 32 bit GOT\n\
8956 -32 create 32 bit object file (default)\n\
8957 -64 create 64 bit object file\n");
8962 mips_init_after_args ()
8964 /* initialize opcodes */
8965 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8966 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8970 md_pcrel_from (fixP
)
8973 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8974 && fixP
->fx_addsy
!= (symbolS
*) NULL
8975 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8977 /* This makes a branch to an undefined symbol be a branch to the
8978 current location. */
8982 /* return the address of the delay slot */
8983 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8986 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8987 reloc for a cons. We could use the definition there, except that
8988 we want to handle 64 bit relocs specially. */
8991 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8994 unsigned int nbytes
;
8998 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9000 if (nbytes
== 8 && ! mips_64
)
9002 if (target_big_endian
)
9008 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9009 as_bad ("Unsupported reloc size %d", nbytes
);
9011 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9014 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9017 /* This is called before the symbol table is processed. In order to
9018 work with gcc when using mips-tfile, we must keep all local labels.
9019 However, in other cases, we want to discard them. If we were
9020 called with -g, but we didn't see any debugging information, it may
9021 mean that gcc is smuggling debugging information through to
9022 mips-tfile, in which case we must generate all local labels. */
9025 mips_frob_file_before_adjust ()
9027 #ifndef NO_ECOFF_DEBUGGING
9030 && ! ecoff_debugging_seen
)
9031 flag_keep_locals
= 1;
9035 /* Sort any unmatched HI16_S relocs so that they immediately precede
9036 the corresponding LO reloc. This is called before md_apply_fix and
9037 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9038 explicit use of the %hi modifier. */
9043 struct mips_hi_fixup
*l
;
9045 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9047 segment_info_type
*seginfo
;
9050 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9052 /* Check quickly whether the next fixup happens to be a matching
9054 if (l
->fixp
->fx_next
!= NULL
9055 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9056 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9057 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9060 /* Look through the fixups for this segment for a matching %lo.
9061 When we find one, move the %hi just in front of it. We do
9062 this in two passes. In the first pass, we try to find a
9063 unique %lo. In the second pass, we permit multiple %hi
9064 relocs for a single %lo (this is a GNU extension). */
9065 seginfo
= seg_info (l
->seg
);
9066 for (pass
= 0; pass
< 2; pass
++)
9071 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9073 /* Check whether this is a %lo fixup which matches l->fixp. */
9074 if (f
->fx_r_type
== BFD_RELOC_LO16
9075 && f
->fx_addsy
== l
->fixp
->fx_addsy
9076 && f
->fx_offset
== l
->fixp
->fx_offset
9079 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9080 || prev
->fx_addsy
!= f
->fx_addsy
9081 || prev
->fx_offset
!= f
->fx_offset
))
9085 /* Move l->fixp before f. */
9086 for (pf
= &seginfo
->fix_root
;
9088 pf
= &(*pf
)->fx_next
)
9089 assert (*pf
!= NULL
);
9091 *pf
= l
->fixp
->fx_next
;
9093 l
->fixp
->fx_next
= f
;
9095 seginfo
->fix_root
= l
->fixp
;
9097 prev
->fx_next
= l
->fixp
;
9109 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9110 "Unmatched %%hi reloc");
9115 /* When generating embedded PIC code we need to use a special
9116 relocation to represent the difference of two symbols in the .text
9117 section (switch tables use a difference of this sort). See
9118 include/coff/mips.h for details. This macro checks whether this
9119 fixup requires the special reloc. */
9120 #define SWITCH_TABLE(fixp) \
9121 ((fixp)->fx_r_type == BFD_RELOC_32 \
9122 && (fixp)->fx_addsy != NULL \
9123 && (fixp)->fx_subsy != NULL \
9124 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9125 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9127 /* When generating embedded PIC code we must keep all PC relative
9128 relocations, in case the linker has to relax a call. We also need
9129 to keep relocations for switch table entries. */
9133 mips_force_relocation (fixp
)
9136 return (mips_pic
== EMBEDDED_PIC
9138 || SWITCH_TABLE (fixp
)
9139 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9140 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9143 /* Apply a fixup to the object file. */
9146 md_apply_fix (fixP
, valueP
)
9153 assert (fixP
->fx_size
== 4
9154 || fixP
->fx_r_type
== BFD_RELOC_16
9155 || fixP
->fx_r_type
== BFD_RELOC_64
);
9159 /* If we aren't adjusting this fixup to be against the section
9160 symbol, we need to adjust the value. */
9162 if (fixP
->fx_addsy
!= NULL
9163 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
9164 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
9166 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9167 if (value
!= 0 && ! fixP
->fx_pcrel
)
9169 /* In this case, the bfd_install_relocation routine will
9170 incorrectly add the symbol value back in. We just want
9171 the addend to appear in the object file. */
9172 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9177 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9179 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9182 switch (fixP
->fx_r_type
)
9184 case BFD_RELOC_MIPS_JMP
:
9185 case BFD_RELOC_HI16
:
9186 case BFD_RELOC_HI16_S
:
9187 case BFD_RELOC_MIPS_GPREL
:
9188 case BFD_RELOC_MIPS_LITERAL
:
9189 case BFD_RELOC_MIPS_CALL16
:
9190 case BFD_RELOC_MIPS_GOT16
:
9191 case BFD_RELOC_MIPS_GPREL32
:
9192 case BFD_RELOC_MIPS_GOT_HI16
:
9193 case BFD_RELOC_MIPS_GOT_LO16
:
9194 case BFD_RELOC_MIPS_CALL_HI16
:
9195 case BFD_RELOC_MIPS_CALL_LO16
:
9196 case BFD_RELOC_MIPS16_GPREL
:
9198 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9199 "Invalid PC relative reloc");
9200 /* Nothing needed to do. The value comes from the reloc entry */
9203 case BFD_RELOC_MIPS16_JMP
:
9204 /* We currently always generate a reloc against a symbol, which
9205 means that we don't want an addend even if the symbol is
9207 fixP
->fx_addnumber
= 0;
9210 case BFD_RELOC_PCREL_HI16_S
:
9211 /* The addend for this is tricky if it is internal, so we just
9212 do everything here rather than in bfd_install_relocation. */
9213 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9215 /* For an external symbol adjust by the address to make it
9216 pcrel_offset. We use the address of the RELLO reloc
9217 which follows this one. */
9218 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9219 + fixP
->fx_next
->fx_where
);
9224 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9225 if (target_big_endian
)
9227 md_number_to_chars (buf
, value
, 2);
9230 case BFD_RELOC_PCREL_LO16
:
9231 /* The addend for this is tricky if it is internal, so we just
9232 do everything here rather than in bfd_install_relocation. */
9233 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9234 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9235 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9236 if (target_big_endian
)
9238 md_number_to_chars (buf
, value
, 2);
9242 /* This is handled like BFD_RELOC_32, but we output a sign
9243 extended value if we are only 32 bits. */
9245 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9247 if (8 <= sizeof (valueT
))
9248 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9255 w1
= w2
= fixP
->fx_where
;
9256 if (target_big_endian
)
9260 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9261 if ((value
& 0x80000000) != 0)
9265 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9271 /* If we are deleting this reloc entry, we must fill in the
9272 value now. This can happen if we have a .word which is not
9273 resolved when it appears but is later defined. We also need
9274 to fill in the value if this is an embedded PIC switch table
9277 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9278 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9283 /* If we are deleting this reloc entry, we must fill in the
9285 assert (fixP
->fx_size
== 2);
9287 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9291 case BFD_RELOC_LO16
:
9292 /* When handling an embedded PIC switch statement, we can wind
9293 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9296 if (value
< -0x8000 || value
> 0x7fff)
9297 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9298 "relocation overflow");
9299 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9300 if (target_big_endian
)
9302 md_number_to_chars (buf
, value
, 2);
9306 case BFD_RELOC_16_PCREL_S2
:
9308 * We need to save the bits in the instruction since fixup_segment()
9309 * might be deleting the relocation entry (i.e., a branch within
9310 * the current segment).
9312 if ((value
& 0x3) != 0)
9313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9314 "Branch to odd address (%lx)", value
);
9317 /* update old instruction data */
9318 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9319 if (target_big_endian
)
9320 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9322 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9324 if (value
>= -0x8000 && value
< 0x8000)
9325 insn
|= value
& 0xffff;
9328 /* The branch offset is too large. If this is an
9329 unconditional branch, and we are not generating PIC code,
9330 we can convert it to an absolute jump instruction. */
9331 if (mips_pic
== NO_PIC
9333 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9334 && (fixP
->fx_frag
->fr_address
9335 < text_section
->vma
+ text_section
->_raw_size
)
9336 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9337 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9338 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9340 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9341 insn
= 0x0c000000; /* jal */
9343 insn
= 0x08000000; /* j */
9344 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9346 fixP
->fx_addsy
= section_symbol (text_section
);
9347 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9351 /* FIXME. It would be possible in principle to handle
9352 conditional branches which overflow. They could be
9353 transformed into a branch around a jump. This would
9354 require setting up variant frags for each different
9355 branch type. The native MIPS assembler attempts to
9356 handle these cases, but it appears to do it
9358 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9359 "Branch out of range");
9363 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9378 const struct mips_opcode
*p
;
9379 int treg
, sreg
, dreg
, shamt
;
9384 for (i
= 0; i
< NUMOPCODES
; ++i
)
9386 p
= &mips_opcodes
[i
];
9387 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9389 printf ("%08lx %s\t", oc
, p
->name
);
9390 treg
= (oc
>> 16) & 0x1f;
9391 sreg
= (oc
>> 21) & 0x1f;
9392 dreg
= (oc
>> 11) & 0x1f;
9393 shamt
= (oc
>> 6) & 0x1f;
9395 for (args
= p
->args
;; ++args
)
9406 printf ("%c", *args
);
9410 assert (treg
== sreg
);
9411 printf ("$%d,$%d", treg
, sreg
);
9416 printf ("$%d", dreg
);
9421 printf ("$%d", treg
);
9425 printf ("0x%x", treg
);
9430 printf ("$%d", sreg
);
9434 printf ("0x%08lx", oc
& 0x1ffffff);
9446 printf ("$%d", shamt
);
9457 printf ("%08lx UNDEFINED\n", oc
);
9468 name
= input_line_pointer
;
9469 c
= get_symbol_end ();
9470 p
= (symbolS
*) symbol_find_or_make (name
);
9471 *input_line_pointer
= c
;
9475 /* Align the current frag to a given power of two. The MIPS assembler
9476 also automatically adjusts any preceding label. */
9479 mips_align (to
, fill
, label
)
9484 mips_emit_delays (false);
9485 frag_align (to
, fill
, 0);
9486 record_alignment (now_seg
, to
);
9489 assert (S_GET_SEGMENT (label
) == now_seg
);
9490 label
->sy_frag
= frag_now
;
9491 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9495 /* Align to a given power of two. .align 0 turns off the automatic
9496 alignment used by the data creating pseudo-ops. */
9503 register long temp_fill
;
9504 long max_alignment
= 15;
9508 o Note that the assembler pulls down any immediately preceeding label
9509 to the aligned address.
9510 o It's not documented but auto alignment is reinstated by
9511 a .align pseudo instruction.
9512 o Note also that after auto alignment is turned off the mips assembler
9513 issues an error on attempt to assemble an improperly aligned data item.
9518 temp
= get_absolute_expression ();
9519 if (temp
> max_alignment
)
9520 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9523 as_warn ("Alignment negative: 0 assumed.");
9526 if (*input_line_pointer
== ',')
9528 input_line_pointer
++;
9529 temp_fill
= get_absolute_expression ();
9536 mips_align (temp
, (int) temp_fill
,
9537 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9544 demand_empty_rest_of_line ();
9548 mips_flush_pending_output ()
9550 mips_emit_delays (false);
9551 mips_clear_insn_labels ();
9560 /* When generating embedded PIC code, we only use the .text, .lit8,
9561 .sdata and .sbss sections. We change the .data and .rdata
9562 pseudo-ops to use .sdata. */
9563 if (mips_pic
== EMBEDDED_PIC
9564 && (sec
== 'd' || sec
== 'r'))
9568 /* The ELF backend needs to know that we are changing sections, so
9569 that .previous works correctly. We could do something like check
9570 for a obj_section_change_hook macro, but that might be confusing
9571 as it would not be appropriate to use it in the section changing
9572 functions in read.c, since obj-elf.c intercepts those. FIXME:
9573 This should be cleaner, somehow. */
9574 obj_elf_section_change_hook ();
9577 mips_emit_delays (false);
9587 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9588 demand_empty_rest_of_line ();
9592 if (USE_GLOBAL_POINTER_OPT
)
9594 seg
= subseg_new (RDATA_SECTION_NAME
,
9595 (subsegT
) get_absolute_expression ());
9596 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9598 bfd_set_section_flags (stdoutput
, seg
,
9604 if (strcmp (TARGET_OS
, "elf") != 0)
9605 bfd_set_section_alignment (stdoutput
, seg
, 4);
9607 demand_empty_rest_of_line ();
9611 as_bad ("No read only data section in this object file format");
9612 demand_empty_rest_of_line ();
9618 if (USE_GLOBAL_POINTER_OPT
)
9620 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9621 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9623 bfd_set_section_flags (stdoutput
, seg
,
9624 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9626 if (strcmp (TARGET_OS
, "elf") != 0)
9627 bfd_set_section_alignment (stdoutput
, seg
, 4);
9629 demand_empty_rest_of_line ();
9634 as_bad ("Global pointers not supported; recompile -G 0");
9635 demand_empty_rest_of_line ();
9644 mips_enable_auto_align ()
9655 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9656 mips_emit_delays (false);
9657 if (log_size
> 0 && auto_align
)
9658 mips_align (log_size
, 0, label
);
9659 mips_clear_insn_labels ();
9660 cons (1 << log_size
);
9669 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9671 mips_emit_delays (false);
9675 mips_align (3, 0, label
);
9677 mips_align (2, 0, label
);
9679 mips_clear_insn_labels ();
9684 /* Handle .globl. We need to override it because on Irix 5 you are
9687 where foo is an undefined symbol, to mean that foo should be
9688 considered to be the address of a function. */
9699 name
= input_line_pointer
;
9700 c
= get_symbol_end ();
9701 symbolP
= symbol_find_or_make (name
);
9702 *input_line_pointer
= c
;
9705 /* On Irix 5, every global symbol that is not explicitly labelled as
9706 being a function is apparently labelled as being an object. */
9709 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9714 secname
= input_line_pointer
;
9715 c
= get_symbol_end ();
9716 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9718 as_bad ("%s: no such section", secname
);
9719 *input_line_pointer
= c
;
9721 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9722 flag
= BSF_FUNCTION
;
9725 symbolP
->bsym
->flags
|= flag
;
9727 S_SET_EXTERNAL (symbolP
);
9728 demand_empty_rest_of_line ();
9738 opt
= input_line_pointer
;
9739 c
= get_symbol_end ();
9743 /* FIXME: What does this mean? */
9745 else if (strncmp (opt
, "pic", 3) == 0)
9753 mips_pic
= SVR4_PIC
;
9755 as_bad (".option pic%d not supported", i
);
9757 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9759 if (g_switch_seen
&& g_switch_value
!= 0)
9760 as_warn ("-G may not be used with SVR4 PIC code");
9762 bfd_set_gp_size (stdoutput
, 0);
9766 as_warn ("Unrecognized option \"%s\"", opt
);
9768 *input_line_pointer
= c
;
9769 demand_empty_rest_of_line ();
9772 /* This structure is used to hold a stack of .set values. */
9774 struct mips_option_stack
9776 struct mips_option_stack
*next
;
9777 struct mips_set_options options
;
9780 static struct mips_option_stack
*mips_opts_stack
;
9782 /* Handle the .set pseudo-op. */
9788 char *name
= input_line_pointer
, ch
;
9790 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9791 input_line_pointer
++;
9792 ch
= *input_line_pointer
;
9793 *input_line_pointer
= '\0';
9795 if (strcmp (name
, "reorder") == 0)
9797 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
9799 /* If we still have pending nops, we can discard them. The
9800 usual nop handling will insert any that are still
9802 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9803 * (mips_opts
.mips16
? 2 : 4));
9804 prev_nop_frag
= NULL
;
9806 mips_opts
.noreorder
= 0;
9808 else if (strcmp (name
, "noreorder") == 0)
9810 mips_emit_delays (true);
9811 mips_opts
.noreorder
= 1;
9812 mips_any_noreorder
= 1;
9814 else if (strcmp (name
, "at") == 0)
9818 else if (strcmp (name
, "noat") == 0)
9822 else if (strcmp (name
, "macro") == 0)
9824 mips_opts
.warn_about_macros
= 0;
9826 else if (strcmp (name
, "nomacro") == 0)
9828 if (mips_opts
.noreorder
== 0)
9829 as_bad ("`noreorder' must be set before `nomacro'");
9830 mips_opts
.warn_about_macros
= 1;
9832 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9834 mips_opts
.nomove
= 0;
9836 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9838 mips_opts
.nomove
= 1;
9840 else if (strcmp (name
, "bopt") == 0)
9842 mips_opts
.nobopt
= 0;
9844 else if (strcmp (name
, "nobopt") == 0)
9846 mips_opts
.nobopt
= 1;
9848 else if (strcmp (name
, "mips16") == 0
9849 || strcmp (name
, "MIPS-16") == 0)
9850 mips_opts
.mips16
= 1;
9851 else if (strcmp (name
, "nomips16") == 0
9852 || strcmp (name
, "noMIPS-16") == 0)
9853 mips_opts
.mips16
= 0;
9854 else if (strncmp (name
, "mips", 4) == 0)
9858 /* Permit the user to change the ISA on the fly. Needless to
9859 say, misuse can cause serious problems. */
9860 isa
= atoi (name
+ 4);
9862 mips_opts
.isa
= file_mips_isa
;
9863 else if (isa
< 1 || isa
> 4)
9864 as_bad ("unknown ISA level");
9866 mips_opts
.isa
= isa
;
9868 else if (strcmp (name
, "autoextend") == 0)
9869 mips_opts
.noautoextend
= 0;
9870 else if (strcmp (name
, "noautoextend") == 0)
9871 mips_opts
.noautoextend
= 1;
9872 else if (strcmp (name
, "push") == 0)
9874 struct mips_option_stack
*s
;
9876 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
9877 s
->next
= mips_opts_stack
;
9878 s
->options
= mips_opts
;
9879 mips_opts_stack
= s
;
9881 else if (strcmp (name
, "pop") == 0)
9883 struct mips_option_stack
*s
;
9885 s
= mips_opts_stack
;
9887 as_bad (".set pop with no .set push");
9890 /* If we're changing the reorder mode we need to handle
9891 delay slots correctly. */
9892 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
9893 mips_emit_delays (true);
9894 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
9896 if (prev_nop_frag
!= NULL
)
9898 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9899 * (mips_opts
.mips16
? 2 : 4));
9900 prev_nop_frag
= NULL
;
9904 mips_opts
= s
->options
;
9905 mips_opts_stack
= s
->next
;
9911 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9913 *input_line_pointer
= ch
;
9914 demand_empty_rest_of_line ();
9917 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9918 .option pic2. It means to generate SVR4 PIC calls. */
9924 mips_pic
= SVR4_PIC
;
9925 if (USE_GLOBAL_POINTER_OPT
)
9927 if (g_switch_seen
&& g_switch_value
!= 0)
9928 as_warn ("-G may not be used with SVR4 PIC code");
9931 bfd_set_gp_size (stdoutput
, 0);
9932 demand_empty_rest_of_line ();
9935 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9936 PIC code. It sets the $gp register for the function based on the
9937 function address, which is in the register named in the argument.
9938 This uses a relocation against _gp_disp, which is handled specially
9939 by the linker. The result is:
9940 lui $gp,%hi(_gp_disp)
9941 addiu $gp,$gp,%lo(_gp_disp)
9942 addu $gp,$gp,.cpload argument
9943 The .cpload argument is normally $25 == $t9. */
9952 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9953 if (mips_pic
!= SVR4_PIC
)
9959 /* .cpload should be a in .set noreorder section. */
9960 if (mips_opts
.noreorder
== 0)
9961 as_warn (".cpload not in noreorder section");
9964 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9965 ex
.X_op_symbol
= NULL
;
9966 ex
.X_add_number
= 0;
9968 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9969 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9971 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9972 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9973 (int) BFD_RELOC_LO16
);
9975 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9976 GP
, GP
, tc_get_register (0));
9978 demand_empty_rest_of_line ();
9981 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9982 offset from $sp. The offset is remembered, and after making a PIC
9983 call $gp is restored from that location. */
9986 s_cprestore (ignore
)
9992 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9993 if (mips_pic
!= SVR4_PIC
)
9999 mips_cprestore_offset
= get_absolute_expression ();
10001 ex
.X_op
= O_constant
;
10002 ex
.X_add_symbol
= NULL
;
10003 ex
.X_op_symbol
= NULL
;
10004 ex
.X_add_number
= mips_cprestore_offset
;
10006 macro_build ((char *) NULL
, &icnt
, &ex
,
10007 mips_opts
.isa
< 3 ? "sw" : "sd",
10008 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10010 demand_empty_rest_of_line ();
10013 /* Handle the .gpword pseudo-op. This is used when generating PIC
10014 code. It generates a 32 bit GP relative reloc. */
10024 /* When not generating PIC code, this is treated as .word. */
10025 if (mips_pic
!= SVR4_PIC
)
10031 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10032 mips_emit_delays (true);
10034 mips_align (2, 0, label
);
10035 mips_clear_insn_labels ();
10039 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10041 as_bad ("Unsupported use of .gpword");
10042 ignore_rest_of_line ();
10046 md_number_to_chars (p
, (valueT
) 0, 4);
10047 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10048 BFD_RELOC_MIPS_GPREL32
);
10050 demand_empty_rest_of_line ();
10053 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10054 tables in SVR4 PIC code. */
10063 /* This is ignored when not generating SVR4 PIC code. */
10064 if (mips_pic
!= SVR4_PIC
)
10070 /* Add $gp to the register named as an argument. */
10071 reg
= tc_get_register (0);
10072 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10073 mips_opts
.isa
< 3 ? "addu" : "daddu",
10074 "d,v,t", reg
, reg
, GP
);
10076 demand_empty_rest_of_line ();
10079 /* Handle the .insn pseudo-op. This marks instruction labels in
10080 mips16 mode. This permits the linker to handle them specially,
10081 such as generating jalx instructions when needed. We also make
10082 them odd for the duration of the assembly, in order to generate the
10083 right sort of code. We will make them even in the adjust_symtab
10084 routine, while leaving them marked. This is convenient for the
10085 debugger and the disassembler. The linker knows to make them odd
10092 if (mips_opts
.mips16
)
10093 mips16_mark_labels ();
10095 demand_empty_rest_of_line ();
10098 /* Handle a .stabn directive. We need these in order to mark a label
10099 as being a mips16 text label correctly. Sometimes the compiler
10100 will emit a label, followed by a .stabn, and then switch sections.
10101 If the label and .stabn are in mips16 mode, then the label is
10102 really a mips16 text label. */
10108 if (type
== 'n' && mips_opts
.mips16
)
10109 mips16_mark_labels ();
10114 /* Parse a register string into a number. Called from the ECOFF code
10115 to parse .frame. The argument is non-zero if this is the frame
10116 register, so that we can record it in mips_frame_reg. */
10119 tc_get_register (frame
)
10124 SKIP_WHITESPACE ();
10125 if (*input_line_pointer
++ != '$')
10127 as_warn ("expected `$'");
10130 else if (isdigit ((unsigned char) *input_line_pointer
))
10132 reg
= get_absolute_expression ();
10133 if (reg
< 0 || reg
>= 32)
10135 as_warn ("Bad register number");
10141 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10143 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10145 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10147 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10151 as_warn ("Unrecognized register name");
10154 input_line_pointer
+= 2;
10157 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10162 md_section_align (seg
, addr
)
10166 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10169 /* We don't need to align ELF sections to the full alignment.
10170 However, Irix 5 may prefer that we align them at least to a 16
10171 byte boundary. We don't bother to align the sections if we are
10172 targeted for an embedded system. */
10173 if (strcmp (TARGET_OS
, "elf") == 0)
10179 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10182 /* Utility routine, called from above as well. If called while the
10183 input file is still being read, it's only an approximation. (For
10184 example, a symbol may later become defined which appeared to be
10185 undefined earlier.) */
10188 nopic_need_relax (sym
, before_relaxing
)
10190 int before_relaxing
;
10195 if (USE_GLOBAL_POINTER_OPT
)
10197 const char *symname
;
10200 /* Find out whether this symbol can be referenced off the GP
10201 register. It can be if it is smaller than the -G size or if
10202 it is in the .sdata or .sbss section. Certain symbols can
10203 not be referenced off the GP, although it appears as though
10205 symname
= S_GET_NAME (sym
);
10206 if (symname
!= (const char *) NULL
10207 && (strcmp (symname
, "eprol") == 0
10208 || strcmp (symname
, "etext") == 0
10209 || strcmp (symname
, "_gp") == 0
10210 || strcmp (symname
, "edata") == 0
10211 || strcmp (symname
, "_fbss") == 0
10212 || strcmp (symname
, "_fdata") == 0
10213 || strcmp (symname
, "_ftext") == 0
10214 || strcmp (symname
, "end") == 0
10215 || strcmp (symname
, "_gp_disp") == 0))
10217 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10219 #ifndef NO_ECOFF_DEBUGGING
10220 || (sym
->ecoff_extern_size
!= 0
10221 && sym
->ecoff_extern_size
<= g_switch_value
)
10223 /* We must defer this decision until after the whole
10224 file has been read, since there might be a .extern
10225 after the first use of this symbol. */
10226 || (before_relaxing
10227 #ifndef NO_ECOFF_DEBUGGING
10228 && sym
->ecoff_extern_size
== 0
10230 && S_GET_VALUE (sym
) == 0)
10231 || (S_GET_VALUE (sym
) != 0
10232 && S_GET_VALUE (sym
) <= g_switch_value
)))
10236 const char *segname
;
10238 segname
= segment_name (S_GET_SEGMENT (sym
));
10239 assert (strcmp (segname
, ".lit8") != 0
10240 && strcmp (segname
, ".lit4") != 0);
10241 change
= (strcmp (segname
, ".sdata") != 0
10242 && strcmp (segname
, ".sbss") != 0);
10247 /* We are not optimizing for the GP register. */
10251 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10252 extended opcode. SEC is the section the frag is in. */
10255 mips16_extended_frag (fragp
, sec
, stretch
)
10261 register const struct mips16_immed_operand
*op
;
10263 int mintiny
, maxtiny
;
10266 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10268 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10271 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10272 op
= mips16_immed_operands
;
10273 while (op
->type
!= type
)
10276 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10281 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10284 maxtiny
= 1 << op
->nbits
;
10289 maxtiny
= (1 << op
->nbits
) - 1;
10294 mintiny
= - (1 << (op
->nbits
- 1));
10295 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10298 /* We can't call S_GET_VALUE here, because we don't want to lock in
10299 a particular frag address. */
10300 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10302 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10303 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10304 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10306 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10307 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10310 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10311 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10312 + fragp
->fr_symbol
->sy_value
.X_add_number
10313 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10314 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10323 /* We won't have the section when we are called from
10324 mips_relax_frag. However, we will always have been called
10325 from md_estimate_size_before_relax first. If this is a
10326 branch to a different section, we mark it as such. If SEC is
10327 NULL, and the frag is not marked, then it must be a branch to
10328 the same section. */
10331 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10338 fragp
->fr_subtype
=
10339 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10341 /* FIXME: We should support this, and let the linker
10342 catch branches and loads that are out of range. */
10343 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10344 "unsupported PC relative reference to different section");
10350 /* In this case, we know for sure that the symbol fragment is in
10351 the same section. If the fr_address of the symbol fragment
10352 is greater then the address of this fragment we want to add
10353 in STRETCH in order to get a better estimate of the address.
10354 This particularly matters because of the shift bits. */
10356 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10360 /* Adjust stretch for any alignment frag. Note that if have
10361 been expanding the earlier code, the symbol may be
10362 defined in what appears to be an earlier frag. FIXME:
10363 This doesn't handle the fr_subtype field, which specifies
10364 a maximum number of bytes to skip when doing an
10367 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10370 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10373 stretch
= - ((- stretch
)
10374 & ~ ((1 << (int) f
->fr_offset
) - 1));
10376 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10385 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10387 /* The base address rules are complicated. The base address of
10388 a branch is the following instruction. The base address of a
10389 PC relative load or add is the instruction itself, but if it
10390 is in a delay slot (in which case it can not be extended) use
10391 the address of the instruction whose delay slot it is in. */
10392 if (type
== 'p' || type
== 'q')
10396 /* If we are currently assuming that this frag should be
10397 extended, then, the current address is two bytes
10399 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10402 /* Ignore the low bit in the target, since it will be set
10403 for a text label. */
10404 if ((val
& 1) != 0)
10407 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10409 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10412 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10414 /* Branch offsets have an implicit 0 in the lowest bit. */
10415 if (type
== 'p' || type
== 'q')
10418 /* If any of the shifted bits are set, we must use an extended
10419 opcode. If the address depends on the size of this
10420 instruction, this can lead to a loop, so we arrange to always
10421 use an extended opcode. We only check this when we are in
10422 the main relaxation loop, when SEC is NULL. */
10423 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10425 fragp
->fr_subtype
=
10426 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10430 /* If we are about to mark a frag as extended because the value
10431 is precisely maxtiny + 1, then there is a chance of an
10432 infinite loop as in the following code:
10437 In this case when the la is extended, foo is 0x3fc bytes
10438 away, so the la can be shrunk, but then foo is 0x400 away, so
10439 the la must be extended. To avoid this loop, we mark the
10440 frag as extended if it was small, and is about to become
10441 extended with a value of maxtiny + 1. */
10442 if (val
== ((maxtiny
+ 1) << op
->shift
)
10443 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10446 fragp
->fr_subtype
=
10447 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10451 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10452 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
10454 if ((val
& ((1 << op
->shift
) - 1)) != 0
10455 || val
< (mintiny
<< op
->shift
)
10456 || val
> (maxtiny
<< op
->shift
))
10462 /* Estimate the size of a frag before relaxing. Unless this is the
10463 mips16, we are not really relaxing here, and the final size is
10464 encoded in the subtype information. For the mips16, we have to
10465 decide whether we are using an extended opcode or not. */
10469 md_estimate_size_before_relax (fragp
, segtype
)
10475 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10477 if (mips16_extended_frag (fragp
, segtype
, 0))
10479 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10484 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10489 if (mips_pic
== NO_PIC
)
10491 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10493 else if (mips_pic
== SVR4_PIC
)
10498 sym
= fragp
->fr_symbol
;
10500 /* Handle the case of a symbol equated to another symbol. */
10501 while (sym
->sy_value
.X_op
== O_symbol
10502 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10506 /* It's possible to get a loop here in a badly written
10508 n
= sym
->sy_value
.X_add_symbol
;
10514 symsec
= S_GET_SEGMENT (sym
);
10516 /* This must duplicate the test in adjust_reloc_syms. */
10517 change
= (symsec
!= &bfd_und_section
10518 && symsec
!= &bfd_abs_section
10519 && ! bfd_is_com_section (symsec
));
10526 /* Record the offset to the first reloc in the fr_opcode field.
10527 This lets md_convert_frag and tc_gen_reloc know that the code
10528 must be expanded. */
10529 fragp
->fr_opcode
= (fragp
->fr_literal
10531 - RELAX_OLD (fragp
->fr_subtype
)
10532 + RELAX_RELOC1 (fragp
->fr_subtype
));
10533 /* FIXME: This really needs as_warn_where. */
10534 if (RELAX_WARN (fragp
->fr_subtype
))
10535 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
10541 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10544 /* This is called to see whether a reloc against a defined symbol
10545 should be converted into a reloc against a section. Don't adjust
10546 MIPS16 jump relocations, so we don't have to worry about the format
10547 of the offset in the .o file. Don't adjust relocations against
10548 mips16 symbols, so that the linker can find them if it needs to set
10552 mips_fix_adjustable (fixp
)
10555 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10557 if (fixp
->fx_addsy
== NULL
)
10560 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10561 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10562 && fixp
->fx_subsy
== NULL
)
10568 /* Translate internal representation of relocation info to BFD target
10572 tc_gen_reloc (section
, fixp
)
10576 static arelent
*retval
[4];
10578 bfd_reloc_code_real_type code
;
10580 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10583 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10584 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10586 if (mips_pic
== EMBEDDED_PIC
10587 && SWITCH_TABLE (fixp
))
10589 /* For a switch table entry we use a special reloc. The addend
10590 is actually the difference between the reloc address and the
10592 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10593 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10594 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10595 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10597 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10599 /* We use a special addend for an internal RELLO reloc. */
10600 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10601 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10603 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10605 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10607 assert (fixp
->fx_next
!= NULL
10608 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10609 /* We use a special addend for an internal RELHI reloc. The
10610 reloc is relative to the RELLO; adjust the addend
10612 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10613 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10614 + fixp
->fx_next
->fx_where
10615 - S_GET_VALUE (fixp
->fx_subsy
));
10617 reloc
->addend
= (fixp
->fx_addnumber
10618 + fixp
->fx_next
->fx_frag
->fr_address
10619 + fixp
->fx_next
->fx_where
);
10621 else if (fixp
->fx_pcrel
== 0)
10622 reloc
->addend
= fixp
->fx_addnumber
;
10625 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10626 /* A gruesome hack which is a result of the gruesome gas reloc
10628 reloc
->addend
= reloc
->address
;
10630 reloc
->addend
= -reloc
->address
;
10633 /* If this is a variant frag, we may need to adjust the existing
10634 reloc and generate a new one. */
10635 if (fixp
->fx_frag
->fr_opcode
!= NULL
10636 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10637 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10638 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10639 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10640 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10641 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10642 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10646 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10648 /* If this is not the last reloc in this frag, then we have two
10649 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10650 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10651 the second one handle all of them. */
10652 if (fixp
->fx_next
!= NULL
10653 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10655 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10656 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10657 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10658 && (fixp
->fx_next
->fx_r_type
10659 == BFD_RELOC_MIPS_GOT_LO16
))
10660 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10661 && (fixp
->fx_next
->fx_r_type
10662 == BFD_RELOC_MIPS_CALL_LO16
)));
10667 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10668 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10669 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10671 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10672 reloc2
->address
= (reloc
->address
10673 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10674 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10675 reloc2
->addend
= fixp
->fx_addnumber
;
10676 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10677 assert (reloc2
->howto
!= NULL
);
10679 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10683 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10686 reloc3
->address
+= 4;
10689 if (mips_pic
== NO_PIC
)
10691 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10692 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10694 else if (mips_pic
== SVR4_PIC
)
10696 switch (fixp
->fx_r_type
)
10700 case BFD_RELOC_MIPS_GOT16
:
10702 case BFD_RELOC_MIPS_CALL16
:
10703 case BFD_RELOC_MIPS_GOT_LO16
:
10704 case BFD_RELOC_MIPS_CALL_LO16
:
10705 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10713 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10714 fixup_segment converted a non-PC relative reloc into a PC
10715 relative reloc. In such a case, we need to convert the reloc
10717 code
= fixp
->fx_r_type
;
10718 if (fixp
->fx_pcrel
)
10723 code
= BFD_RELOC_8_PCREL
;
10726 code
= BFD_RELOC_16_PCREL
;
10729 code
= BFD_RELOC_32_PCREL
;
10732 code
= BFD_RELOC_64_PCREL
;
10734 case BFD_RELOC_8_PCREL
:
10735 case BFD_RELOC_16_PCREL
:
10736 case BFD_RELOC_32_PCREL
:
10737 case BFD_RELOC_64_PCREL
:
10738 case BFD_RELOC_16_PCREL_S2
:
10739 case BFD_RELOC_PCREL_HI16_S
:
10740 case BFD_RELOC_PCREL_LO16
:
10743 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10744 "Cannot make %s relocation PC relative",
10745 bfd_get_reloc_code_name (code
));
10749 /* To support a PC relative reloc when generating embedded PIC code
10750 for ECOFF, we use a Cygnus extension. We check for that here to
10751 make sure that we don't let such a reloc escape normally. */
10752 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10753 && code
== BFD_RELOC_16_PCREL_S2
10754 && mips_pic
!= EMBEDDED_PIC
)
10755 reloc
->howto
= NULL
;
10757 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10759 if (reloc
->howto
== NULL
)
10761 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10762 "Can not represent %s relocation in this object file format",
10763 bfd_get_reloc_code_name (code
));
10770 /* Relax a machine dependent frag. This returns the amount by which
10771 the current size of the frag should change. */
10774 mips_relax_frag (fragp
, stretch
)
10778 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10781 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10783 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10785 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10790 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10792 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10799 /* Convert a machine dependent frag. */
10802 md_convert_frag (abfd
, asec
, fragp
)
10810 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10813 register const struct mips16_immed_operand
*op
;
10814 boolean small
, ext
;
10817 unsigned long insn
;
10818 boolean use_extend
;
10819 unsigned short extend
;
10821 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10822 op
= mips16_immed_operands
;
10823 while (op
->type
!= type
)
10826 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10837 resolve_symbol_value (fragp
->fr_symbol
, 1);
10838 val
= S_GET_VALUE (fragp
->fr_symbol
);
10843 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10845 /* The rules for the base address of a PC relative reloc are
10846 complicated; see mips16_extended_frag. */
10847 if (type
== 'p' || type
== 'q')
10852 /* Ignore the low bit in the target, since it will be
10853 set for a text label. */
10854 if ((val
& 1) != 0)
10857 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10859 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10862 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10865 /* Make sure the section winds up with the alignment we have
10868 record_alignment (asec
, op
->shift
);
10872 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10873 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10874 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10875 "extended instruction in delay slot");
10877 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10879 if (target_big_endian
)
10880 insn
= bfd_getb16 (buf
);
10882 insn
= bfd_getl16 (buf
);
10884 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10885 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10886 small
, ext
, &insn
, &use_extend
, &extend
);
10890 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10891 fragp
->fr_fix
+= 2;
10895 md_number_to_chars (buf
, insn
, 2);
10896 fragp
->fr_fix
+= 2;
10901 if (fragp
->fr_opcode
== NULL
)
10904 old
= RELAX_OLD (fragp
->fr_subtype
);
10905 new = RELAX_NEW (fragp
->fr_subtype
);
10906 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10909 memcpy (fixptr
- old
, fixptr
, new);
10911 fragp
->fr_fix
+= new - old
;
10917 /* This function is called after the relocs have been generated.
10918 We've been storing mips16 text labels as odd. Here we convert them
10919 back to even for the convenience of the debugger. */
10922 mips_frob_file_after_relocs ()
10925 unsigned int count
, i
;
10927 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10930 syms
= bfd_get_outsymbols (stdoutput
);
10931 count
= bfd_get_symcount (stdoutput
);
10932 for (i
= 0; i
< count
; i
++, syms
++)
10934 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10935 && ((*syms
)->value
& 1) != 0)
10937 (*syms
)->value
&= ~1;
10938 /* If the symbol has an odd size, it was probably computed
10939 incorrectly, so adjust that as well. */
10940 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10941 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10948 /* This function is called whenever a label is defined. It is used
10949 when handling branch delays; if a branch has a label, we assume we
10950 can not move it. */
10953 mips_define_label (sym
)
10956 struct insn_label_list
*l
;
10958 if (free_insn_labels
== NULL
)
10959 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10962 l
= free_insn_labels
;
10963 free_insn_labels
= l
->next
;
10967 l
->next
= insn_labels
;
10971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10973 /* Some special processing for a MIPS ELF file. */
10976 mips_elf_final_processing ()
10978 /* Write out the register information. */
10983 s
.ri_gprmask
= mips_gprmask
;
10984 s
.ri_cprmask
[0] = mips_cprmask
[0];
10985 s
.ri_cprmask
[1] = mips_cprmask
[1];
10986 s
.ri_cprmask
[2] = mips_cprmask
[2];
10987 s
.ri_cprmask
[3] = mips_cprmask
[3];
10988 /* The gp_value field is set by the MIPS ELF backend. */
10990 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10991 ((Elf32_External_RegInfo
*)
10992 mips_regmask_frag
));
10996 Elf64_Internal_RegInfo s
;
10998 s
.ri_gprmask
= mips_gprmask
;
11000 s
.ri_cprmask
[0] = mips_cprmask
[0];
11001 s
.ri_cprmask
[1] = mips_cprmask
[1];
11002 s
.ri_cprmask
[2] = mips_cprmask
[2];
11003 s
.ri_cprmask
[3] = mips_cprmask
[3];
11004 /* The gp_value field is set by the MIPS ELF backend. */
11006 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11007 ((Elf64_External_RegInfo
*)
11008 mips_regmask_frag
));
11011 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11012 sort of BFD interface for this. */
11013 if (mips_any_noreorder
)
11014 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11015 if (mips_pic
!= NO_PIC
)
11016 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11019 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11021 /* These functions should really be defined by the object file format,
11022 since they are related to debugging information. However, this
11023 code has to work for the a.out format, which does not define them,
11024 so we provide simple versions here. These don't actually generate
11025 any debugging information, but they do simple checking and someday
11026 somebody may make them useful. */
11030 struct loc
*loc_next
;
11031 unsigned long loc_fileno
;
11032 unsigned long loc_lineno
;
11033 unsigned long loc_offset
;
11034 unsigned short loc_delta
;
11035 unsigned short loc_count
;
11042 typedef struct proc
11044 struct proc
*proc_next
;
11045 struct symbol
*proc_isym
;
11046 struct symbol
*proc_end
;
11047 unsigned long proc_reg_mask
;
11048 unsigned long proc_reg_offset
;
11049 unsigned long proc_fpreg_mask
;
11050 unsigned long proc_fpreg_offset
;
11051 unsigned long proc_frameoffset
;
11052 unsigned long proc_framereg
;
11053 unsigned long proc_pcreg
;
11055 struct file
*proc_file
;
11060 typedef struct file
11062 struct file
*file_next
;
11063 unsigned long file_fileno
;
11064 struct symbol
*file_symbol
;
11065 struct symbol
*file_end
;
11066 struct proc
*file_proc
;
11071 static struct obstack proc_frags
;
11072 static procS
*proc_lastP
;
11073 static procS
*proc_rootP
;
11074 static int numprocs
;
11079 obstack_begin (&proc_frags
, 0x2000);
11085 /* check for premature end, nesting errors, etc */
11086 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11087 as_warn ("missing `.end' at end of assembly");
11096 if (*input_line_pointer
== '-')
11098 ++input_line_pointer
;
11101 if (!isdigit (*input_line_pointer
))
11102 as_bad ("Expected simple number.");
11103 if (input_line_pointer
[0] == '0')
11105 if (input_line_pointer
[1] == 'x')
11107 input_line_pointer
+= 2;
11108 while (isxdigit (*input_line_pointer
))
11111 val
|= hex_value (*input_line_pointer
++);
11113 return negative
? -val
: val
;
11117 ++input_line_pointer
;
11118 while (isdigit (*input_line_pointer
))
11121 val
|= *input_line_pointer
++ - '0';
11123 return negative
? -val
: val
;
11126 if (!isdigit (*input_line_pointer
))
11128 printf (" *input_line_pointer == '%c' 0x%02x\n",
11129 *input_line_pointer
, *input_line_pointer
);
11130 as_warn ("Invalid number");
11133 while (isdigit (*input_line_pointer
))
11136 val
+= *input_line_pointer
++ - '0';
11138 return negative
? -val
: val
;
11141 /* The .file directive; just like the usual .file directive, but there
11142 is an initial number which is the ECOFF file index. */
11150 line
= get_number ();
11155 /* The .end directive. */
11163 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11166 demand_empty_rest_of_line ();
11170 if (now_seg
!= text_section
)
11171 as_warn (".end not in text section");
11174 as_warn (".end and no .ent seen yet.");
11180 assert (S_GET_NAME (p
));
11181 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
11182 as_warn (".end symbol does not match .ent symbol.");
11185 proc_lastP
->proc_end
= (symbolS
*) 1;
11188 /* The .aent and .ent directives. */
11198 symbolP
= get_symbol ();
11199 if (*input_line_pointer
== ',')
11200 input_line_pointer
++;
11201 SKIP_WHITESPACE ();
11202 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11203 number
= get_number ();
11204 if (now_seg
!= text_section
)
11205 as_warn (".ent or .aent not in text section.");
11207 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11208 as_warn ("missing `.end'");
11212 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11213 procP
->proc_isym
= symbolP
;
11214 procP
->proc_reg_mask
= 0;
11215 procP
->proc_reg_offset
= 0;
11216 procP
->proc_fpreg_mask
= 0;
11217 procP
->proc_fpreg_offset
= 0;
11218 procP
->proc_frameoffset
= 0;
11219 procP
->proc_framereg
= 0;
11220 procP
->proc_pcreg
= 0;
11221 procP
->proc_end
= NULL
;
11222 procP
->proc_next
= NULL
;
11224 proc_lastP
->proc_next
= procP
;
11226 proc_rootP
= procP
;
11227 proc_lastP
= procP
;
11230 demand_empty_rest_of_line ();
11233 /* The .frame directive. */
11246 frame_reg
= tc_get_register (1);
11247 if (*input_line_pointer
== ',')
11248 input_line_pointer
++;
11249 frame_off
= get_absolute_expression ();
11250 if (*input_line_pointer
== ',')
11251 input_line_pointer
++;
11252 pcreg
= tc_get_register (0);
11254 /* bob third eye */
11255 assert (proc_rootP
);
11256 proc_rootP
->proc_framereg
= frame_reg
;
11257 proc_rootP
->proc_frameoffset
= frame_off
;
11258 proc_rootP
->proc_pcreg
= pcreg
;
11259 /* bob macho .frame */
11261 /* We don't have to write out a frame stab for unoptimized code. */
11262 if (!(frame_reg
== FP
&& frame_off
== 0))
11265 as_warn ("No .ent for .frame to use.");
11266 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11267 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11268 S_SET_TYPE (symP
, N_RMASK
);
11269 S_SET_OTHER (symP
, 0);
11270 S_SET_DESC (symP
, 0);
11271 symP
->sy_forward
= proc_lastP
->proc_isym
;
11272 /* bob perhaps I should have used pseudo set */
11274 demand_empty_rest_of_line ();
11278 /* The .fmask and .mask directives. */
11285 char str
[100], *strP
;
11291 mask
= get_number ();
11292 if (*input_line_pointer
== ',')
11293 input_line_pointer
++;
11294 off
= get_absolute_expression ();
11296 /* bob only for coff */
11297 assert (proc_rootP
);
11298 if (reg_type
== 'F')
11300 proc_rootP
->proc_fpreg_mask
= mask
;
11301 proc_rootP
->proc_fpreg_offset
= off
;
11305 proc_rootP
->proc_reg_mask
= mask
;
11306 proc_rootP
->proc_reg_offset
= off
;
11309 /* bob macho .mask + .fmask */
11311 /* We don't have to write out a mask stab if no saved regs. */
11315 as_warn ("No .ent for .mask to use.");
11317 for (i
= 0; i
< 32; i
++)
11321 sprintf (strP
, "%c%d,", reg_type
, i
);
11322 strP
+= strlen (strP
);
11326 sprintf (strP
, ";%d,", off
);
11327 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11328 S_SET_TYPE (symP
, N_RMASK
);
11329 S_SET_OTHER (symP
, 0);
11330 S_SET_DESC (symP
, 0);
11331 symP
->sy_forward
= proc_lastP
->proc_isym
;
11332 /* bob perhaps I should have used pseudo set */
11337 /* The .loc directive. */
11348 assert (now_seg
== text_section
);
11350 lineno
= get_number ();
11351 addroff
= frag_now_fix ();
11353 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11354 S_SET_TYPE (symbolP
, N_SLINE
);
11355 S_SET_OTHER (symbolP
, 0);
11356 S_SET_DESC (symbolP
, lineno
);
11357 symbolP
->sy_segment
= now_seg
;