1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993-2021 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
28 #include "safe-ctype.h"
30 #include "opcode/mips.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
35 /* Check assumptions made in this file. */
36 typedef char static_assert1
[sizeof (offsetT
) < 8 ? -1 : 1];
37 typedef char static_assert2
[sizeof (valueT
) < 8 ? -1 : 1];
40 #define DBG(x) printf x
45 #define streq(a, b) (strcmp (a, b) == 0)
47 #define SKIP_SPACE_TABS(S) \
48 do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0)
50 /* Clean up namespace so we can include obj-elf.h too. */
51 static int mips_output_flavor (void);
52 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
53 #undef OBJ_PROCESS_STAB
60 #undef obj_frob_file_after_relocs
61 #undef obj_frob_symbol
63 #undef obj_sec_sym_ok_for_reloc
64 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
67 /* Fix any of them that we actually care about. */
69 #define OUTPUT_FLAVOR mips_output_flavor()
73 #ifndef ECOFF_DEBUGGING
74 #define NO_ECOFF_DEBUGGING
75 #define ECOFF_DEBUGGING 0
78 int mips_flag_mdebug
= -1;
80 /* Control generation of .pdr sections. Off by default on IRIX: the native
81 linker doesn't know about and discards them, but relocations against them
82 remain, leading to rld crashes. */
84 int mips_flag_pdr
= FALSE
;
86 int mips_flag_pdr
= TRUE
;
91 static char *mips_regmask_frag
;
92 static char *mips_flags_frag
;
99 #define PIC_CALL_REG 25
107 #define ILLEGAL_REG (32)
109 #define AT mips_opts.at
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME ".rodata"
116 /* Ways in which an instruction can be "appended" to the output. */
118 /* Just add it normally. */
121 /* Add it normally and then add a nop. */
124 /* Turn an instruction with a delay slot into a "compact" version. */
127 /* Insert the instruction before the last one. */
131 /* Information about an instruction, including its format, operands
135 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
136 const struct mips_opcode
*insn_mo
;
138 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
139 a copy of INSN_MO->match with the operands filled in. If we have
140 decided to use an extended MIPS16 instruction, this includes the
142 unsigned long insn_opcode
;
144 /* The name if this is an label. */
147 /* The target label name if this is an branch. */
150 /* The frag that contains the instruction. */
153 /* The offset into FRAG of the first instruction byte. */
156 /* The relocs associated with the instruction, if any. */
159 /* True if this entry cannot be moved from its current position. */
160 unsigned int fixed_p
: 1;
162 /* True if this instruction occurred in a .set noreorder block. */
163 unsigned int noreorder_p
: 1;
165 /* True for mips16 instructions that jump to an absolute address. */
166 unsigned int mips16_absolute_jump_p
: 1;
168 /* True if this instruction is complete. */
169 unsigned int complete_p
: 1;
171 /* True if this instruction is cleared from history by unconditional
173 unsigned int cleared_p
: 1;
176 /* The ABI to use. */
187 /* MIPS ABI we are using for this output file. */
188 static enum mips_abi_level mips_abi
= NO_ABI
;
190 /* Whether or not we have code that can call pic code. */
191 int mips_abicalls
= FALSE
;
193 /* Whether or not we have code which can be put into a shared
195 static bfd_boolean mips_in_shared
= TRUE
;
197 /* This is the set of options which may be modified by the .set
198 pseudo-op. We use a struct so that .set push and .set pop are more
201 struct mips_set_options
203 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
204 if it has not been initialized. Changed by `.set mipsN', and the
205 -mipsN command line option, and the default CPU. */
207 /* Enabled Application Specific Extensions (ASEs). Changed by `.set
208 <asename>', by command line options, and based on the default
211 /* Whether we are assembling for the mips16 processor. 0 if we are
212 not, 1 if we are, and -1 if the value has not been initialized.
213 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
214 -nomips16 command line options, and the default CPU. */
216 /* Whether we are assembling for the mipsMIPS ASE. 0 if we are not,
217 1 if we are, and -1 if the value has not been initialized. Changed
218 by `.set micromips' and `.set nomicromips', and the -mmicromips
219 and -mno-micromips command line options, and the default CPU. */
221 /* Non-zero if we should not reorder instructions. Changed by `.set
222 reorder' and `.set noreorder'. */
224 /* Non-zero if we should not permit the register designated "assembler
225 temporary" to be used in instructions. The value is the register
226 number, normally $at ($1). Changed by `.set at=REG', `.set noat'
227 (same as `.set at=$0') and `.set at' (same as `.set at=$1'). */
229 /* Non-zero if we should warn when a macro instruction expands into
230 more than one machine instruction. Changed by `.set nomacro' and
232 int warn_about_macros
;
233 /* Non-zero if we should not move instructions. Changed by `.set
234 move', `.set volatile', `.set nomove', and `.set novolatile'. */
236 /* Non-zero if we should not optimize branches by moving the target
237 of the branch into the delay slot. Actually, we don't perform
238 this optimization anyhow. Changed by `.set bopt' and `.set
241 /* Non-zero if we should not autoextend mips16 instructions.
242 Changed by `.set autoextend' and `.set noautoextend'. */
244 /* True if we should only emit 32-bit microMIPS instructions.
245 Changed by `.set insn32' and `.set noinsn32', and the -minsn32
246 and -mno-insn32 command line options. */
248 /* Restrict general purpose registers and floating point registers
249 to 32 bit. This is initially determined when -mgp32 or -mfp32
250 is passed but can changed if the assembler code uses .set mipsN. */
253 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
254 command line option, and the default CPU. */
256 /* True if ".set sym32" is in effect. */
258 /* True if floating-point operations are not allowed. Changed by .set
259 softfloat or .set hardfloat, by command line options -msoft-float or
260 -mhard-float. The default is false. */
261 bfd_boolean soft_float
;
263 /* True if only single-precision floating-point operations are allowed.
264 Changed by .set singlefloat or .set doublefloat, command-line options
265 -msingle-float or -mdouble-float. The default is false. */
266 bfd_boolean single_float
;
268 /* 1 if single-precision operations on odd-numbered registers are
272 /* The set of ASEs that should be enabled for the user specified
273 architecture. This cannot be inferred from 'arch' for all cores
274 as processors only have a unique 'arch' if they add architecture
275 specific instructions (UDI). */
279 /* Specifies whether module level options have been checked yet. */
280 static bfd_boolean file_mips_opts_checked
= FALSE
;
282 /* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the
283 value has not been initialized. Changed by `.nan legacy' and
284 `.nan 2008', and the -mnan=legacy and -mnan=2008 command line
285 options, and the default CPU. */
286 static int mips_nan2008
= -1;
288 /* This is the struct we use to hold the module level set of options.
289 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
290 fp fields to -1 to indicate that they have not been initialized. */
292 static struct mips_set_options file_mips_opts
=
294 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
295 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
296 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
297 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
298 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
302 /* This is similar to file_mips_opts, but for the current set of options. */
304 static struct mips_set_options mips_opts
=
306 /* isa */ ISA_UNKNOWN
, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
307 /* noreorder */ 0, /* at */ ATREG
, /* warn_about_macros */ 0,
308 /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE
,
309 /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN
, /* sym32 */ FALSE
,
310 /* soft_float */ FALSE
, /* single_float */ FALSE
, /* oddspreg */ -1,
314 /* Which bits of file_ase were explicitly set or cleared by ASE options. */
315 static unsigned int file_ase_explicit
;
317 /* These variables are filled in with the masks of registers used.
318 The object format code reads them and puts them in the appropriate
320 unsigned long mips_gprmask
;
321 unsigned long mips_cprmask
[4];
323 /* True if any MIPS16 code was produced. */
324 static int file_ase_mips16
;
326 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
327 || mips_opts.isa == ISA_MIPS32R2 \
328 || mips_opts.isa == ISA_MIPS32R3 \
329 || mips_opts.isa == ISA_MIPS32R5 \
330 || mips_opts.isa == ISA_MIPS64 \
331 || mips_opts.isa == ISA_MIPS64R2 \
332 || mips_opts.isa == ISA_MIPS64R3 \
333 || mips_opts.isa == ISA_MIPS64R5)
335 /* True if any microMIPS code was produced. */
336 static int file_ase_micromips
;
338 /* True if we want to create R_MIPS_JALR for jalr $25. */
340 #define MIPS_JALR_HINT_P(EXPR) HAVE_NEWABI
342 /* As a GNU extension, we use R_MIPS_JALR for o32 too. However,
343 because there's no place for any addend, the only acceptable
344 expression is a bare symbol. */
345 #define MIPS_JALR_HINT_P(EXPR) \
346 (!HAVE_IN_PLACE_ADDENDS \
347 || ((EXPR)->X_op == O_symbol && (EXPR)->X_add_number == 0))
350 /* The argument of the -march= flag. The architecture we are assembling. */
351 static const char *mips_arch_string
;
353 /* The argument of the -mtune= flag. The architecture for which we
355 static int mips_tune
= CPU_UNKNOWN
;
356 static const char *mips_tune_string
;
358 /* True when generating 32-bit code for a 64-bit processor. */
359 static int mips_32bitmode
= 0;
361 /* True if the given ABI requires 32-bit registers. */
362 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
364 /* Likewise 64-bit registers. */
365 #define ABI_NEEDS_64BIT_REGS(ABI) \
367 || (ABI) == N64_ABI \
370 #define ISA_IS_R6(ISA) \
371 ((ISA) == ISA_MIPS32R6 \
372 || (ISA) == ISA_MIPS64R6)
374 /* Return true if ISA supports 64 bit wide gp registers. */
375 #define ISA_HAS_64BIT_REGS(ISA) \
376 ((ISA) == ISA_MIPS3 \
377 || (ISA) == ISA_MIPS4 \
378 || (ISA) == ISA_MIPS5 \
379 || (ISA) == ISA_MIPS64 \
380 || (ISA) == ISA_MIPS64R2 \
381 || (ISA) == ISA_MIPS64R3 \
382 || (ISA) == ISA_MIPS64R5 \
383 || (ISA) == ISA_MIPS64R6)
385 /* Return true if ISA supports 64 bit wide float registers. */
386 #define ISA_HAS_64BIT_FPRS(ISA) \
387 ((ISA) == ISA_MIPS3 \
388 || (ISA) == ISA_MIPS4 \
389 || (ISA) == ISA_MIPS5 \
390 || (ISA) == ISA_MIPS32R2 \
391 || (ISA) == ISA_MIPS32R3 \
392 || (ISA) == ISA_MIPS32R5 \
393 || (ISA) == ISA_MIPS32R6 \
394 || (ISA) == ISA_MIPS64 \
395 || (ISA) == ISA_MIPS64R2 \
396 || (ISA) == ISA_MIPS64R3 \
397 || (ISA) == ISA_MIPS64R5 \
398 || (ISA) == ISA_MIPS64R6)
400 /* Return true if ISA supports 64-bit right rotate (dror et al.)
402 #define ISA_HAS_DROR(ISA) \
403 ((ISA) == ISA_MIPS64R2 \
404 || (ISA) == ISA_MIPS64R3 \
405 || (ISA) == ISA_MIPS64R5 \
406 || (ISA) == ISA_MIPS64R6 \
407 || (mips_opts.micromips \
408 && ISA_HAS_64BIT_REGS (ISA)) \
411 /* Return true if ISA supports 32-bit right rotate (ror et al.)
413 #define ISA_HAS_ROR(ISA) \
414 ((ISA) == ISA_MIPS32R2 \
415 || (ISA) == ISA_MIPS32R3 \
416 || (ISA) == ISA_MIPS32R5 \
417 || (ISA) == ISA_MIPS32R6 \
418 || (ISA) == ISA_MIPS64R2 \
419 || (ISA) == ISA_MIPS64R3 \
420 || (ISA) == ISA_MIPS64R5 \
421 || (ISA) == ISA_MIPS64R6 \
422 || (mips_opts.ase & ASE_SMARTMIPS) \
423 || mips_opts.micromips \
426 /* Return true if ISA supports single-precision floats in odd registers. */
427 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
428 (((ISA) == ISA_MIPS32 \
429 || (ISA) == ISA_MIPS32R2 \
430 || (ISA) == ISA_MIPS32R3 \
431 || (ISA) == ISA_MIPS32R5 \
432 || (ISA) == ISA_MIPS32R6 \
433 || (ISA) == ISA_MIPS64 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6 \
438 || (CPU) == CPU_R5900) \
439 && ((CPU) != CPU_GS464 \
440 || (CPU) != CPU_GS464E \
441 || (CPU) != CPU_GS264E))
443 /* Return true if ISA supports move to/from high part of a 64-bit
444 floating-point register. */
445 #define ISA_HAS_MXHC1(ISA) \
446 ((ISA) == ISA_MIPS32R2 \
447 || (ISA) == ISA_MIPS32R3 \
448 || (ISA) == ISA_MIPS32R5 \
449 || (ISA) == ISA_MIPS32R6 \
450 || (ISA) == ISA_MIPS64R2 \
451 || (ISA) == ISA_MIPS64R3 \
452 || (ISA) == ISA_MIPS64R5 \
453 || (ISA) == ISA_MIPS64R6)
455 /* Return true if ISA supports legacy NAN. */
456 #define ISA_HAS_LEGACY_NAN(ISA) \
457 ((ISA) == ISA_MIPS1 \
458 || (ISA) == ISA_MIPS2 \
459 || (ISA) == ISA_MIPS3 \
460 || (ISA) == ISA_MIPS4 \
461 || (ISA) == ISA_MIPS5 \
462 || (ISA) == ISA_MIPS32 \
463 || (ISA) == ISA_MIPS32R2 \
464 || (ISA) == ISA_MIPS32R3 \
465 || (ISA) == ISA_MIPS32R5 \
466 || (ISA) == ISA_MIPS64 \
467 || (ISA) == ISA_MIPS64R2 \
468 || (ISA) == ISA_MIPS64R3 \
469 || (ISA) == ISA_MIPS64R5)
472 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
477 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
481 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
483 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
485 /* True if relocations are stored in-place. */
486 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
488 /* The ABI-derived address size. */
489 #define HAVE_64BIT_ADDRESSES \
490 (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
491 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
493 /* The size of symbolic constants (i.e., expressions of the form
494 "SYMBOL" or "SYMBOL + OFFSET"). */
495 #define HAVE_32BIT_SYMBOLS \
496 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
497 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
499 /* Addresses are loaded in different ways, depending on the address size
500 in use. The n32 ABI Documentation also mandates the use of additions
501 with overflow checking, but existing implementations don't follow it. */
502 #define ADDRESS_ADD_INSN \
503 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
505 #define ADDRESS_ADDI_INSN \
506 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
508 #define ADDRESS_LOAD_INSN \
509 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
511 #define ADDRESS_STORE_INSN \
512 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
514 /* Return true if the given CPU supports the MIPS16 ASE. */
515 #define CPU_HAS_MIPS16(cpu) \
516 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
517 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
519 /* Return true if the given CPU supports the microMIPS ASE. */
520 #define CPU_HAS_MICROMIPS(cpu) 0
522 /* True if CPU has a dror instruction. */
523 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
525 /* True if CPU has a ror instruction. */
526 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
528 /* True if CPU is in the Octeon family. */
529 #define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
530 || (CPU) == CPU_OCTEON2 || (CPU) == CPU_OCTEON3)
532 /* True if CPU has seq/sne and seqi/snei instructions. */
533 #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU))
535 /* True, if CPU has support for ldc1 and sdc1. */
536 #define CPU_HAS_LDC1_SDC1(CPU) \
537 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
539 /* True if mflo and mfhi can be immediately followed by instructions
540 which write to the HI and LO registers.
542 According to MIPS specifications, MIPS ISAs I, II, and III need
543 (at least) two instructions between the reads of HI/LO and
544 instructions which write them, and later ISAs do not. Contradicting
545 the MIPS specifications, some MIPS IV processor user manuals (e.g.
546 the UM for the NEC Vr5000) document needing the instructions between
547 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
548 MIPS64 and later ISAs to have the interlocks, plus any specific
549 earlier-ISA CPUs for which CPU documentation declares that the
550 instructions are really interlocked. */
551 #define hilo_interlocks \
552 (mips_opts.isa == ISA_MIPS32 \
553 || mips_opts.isa == ISA_MIPS32R2 \
554 || mips_opts.isa == ISA_MIPS32R3 \
555 || mips_opts.isa == ISA_MIPS32R5 \
556 || mips_opts.isa == ISA_MIPS32R6 \
557 || mips_opts.isa == ISA_MIPS64 \
558 || mips_opts.isa == ISA_MIPS64R2 \
559 || mips_opts.isa == ISA_MIPS64R3 \
560 || mips_opts.isa == ISA_MIPS64R5 \
561 || mips_opts.isa == ISA_MIPS64R6 \
562 || mips_opts.arch == CPU_R4010 \
563 || mips_opts.arch == CPU_R5900 \
564 || mips_opts.arch == CPU_R10000 \
565 || mips_opts.arch == CPU_R12000 \
566 || mips_opts.arch == CPU_R14000 \
567 || mips_opts.arch == CPU_R16000 \
568 || mips_opts.arch == CPU_RM7000 \
569 || mips_opts.arch == CPU_VR5500 \
570 || mips_opts.micromips \
573 /* Whether the processor uses hardware interlocks to protect reads
574 from the GPRs after they are loaded from memory, and thus does not
575 require nops to be inserted. This applies to instructions marked
576 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
577 level I and microMIPS mode instructions are always interlocked. */
578 #define gpr_interlocks \
579 (mips_opts.isa != ISA_MIPS1 \
580 || mips_opts.arch == CPU_R3900 \
581 || mips_opts.arch == CPU_R5900 \
582 || mips_opts.micromips \
585 /* Whether the processor uses hardware interlocks to avoid delays
586 required by coprocessor instructions, and thus does not require
587 nops to be inserted. This applies to instructions marked
588 INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
589 instructions marked INSN_WRITE_COND_CODE and ones marked
590 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
591 levels I, II, and III and microMIPS mode instructions are always
593 /* Itbl support may require additional care here. */
594 #define cop_interlocks \
595 ((mips_opts.isa != ISA_MIPS1 \
596 && mips_opts.isa != ISA_MIPS2 \
597 && mips_opts.isa != ISA_MIPS3) \
598 || mips_opts.arch == CPU_R4300 \
599 || mips_opts.micromips \
602 /* Whether the processor uses hardware interlocks to protect reads
603 from coprocessor registers after they are loaded from memory, and
604 thus does not require nops to be inserted. This applies to
605 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
606 requires at MIPS ISA level I and microMIPS mode instructions are
607 always interlocked. */
608 #define cop_mem_interlocks \
609 (mips_opts.isa != ISA_MIPS1 \
610 || mips_opts.micromips \
613 /* Is this a mfhi or mflo instruction? */
614 #define MF_HILO_INSN(PINFO) \
615 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
617 /* Whether code compression (either of the MIPS16 or the microMIPS ASEs)
618 has been selected. This implies, in particular, that addresses of text
619 labels have their LSB set. */
620 #define HAVE_CODE_COMPRESSION \
621 ((mips_opts.mips16 | mips_opts.micromips) != 0)
623 /* The minimum and maximum signed values that can be stored in a GPR. */
624 #define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1))
625 #define GPR_SMIN (-GPR_SMAX - 1)
627 /* MIPS PIC level. */
629 enum mips_pic_level mips_pic
;
631 /* 1 if we should generate 32 bit offsets from the $gp register in
632 SVR4_PIC mode. Currently has no meaning in other modes. */
633 static int mips_big_got
= 0;
635 /* 1 if trap instructions should used for overflow rather than break
637 static int mips_trap
= 0;
639 /* 1 if double width floating point constants should not be constructed
640 by assembling two single width halves into two single width floating
641 point registers which just happen to alias the double width destination
642 register. On some architectures this aliasing can be disabled by a bit
643 in the status register, and the setting of this bit cannot be determined
644 automatically at assemble time. */
645 static int mips_disable_float_construction
;
647 /* Non-zero if any .set noreorder directives were used. */
649 static int mips_any_noreorder
;
651 /* Non-zero if nops should be inserted when the register referenced in
652 an mfhi/mflo instruction is read in the next two instructions. */
653 static int mips_7000_hilo_fix
;
655 /* The size of objects in the small data section. */
656 static unsigned int g_switch_value
= 8;
657 /* Whether the -G option was used. */
658 static int g_switch_seen
= 0;
663 /* If we can determine in advance that GP optimization won't be
664 possible, we can skip the relaxation stuff that tries to produce
665 GP-relative references. This makes delay slot optimization work
668 This function can only provide a guess, but it seems to work for
669 gcc output. It needs to guess right for gcc, otherwise gcc
670 will put what it thinks is a GP-relative instruction in a branch
673 I don't know if a fix is needed for the SVR4_PIC mode. I've only
674 fixed it for the non-PIC mode. KR 95/04/07 */
675 static int nopic_need_relax (symbolS
*, int);
677 /* Handle of the OPCODE hash table. */
678 static htab_t op_hash
= NULL
;
680 /* The opcode hash table we use for the mips16. */
681 static htab_t mips16_op_hash
= NULL
;
683 /* The opcode hash table we use for the microMIPS ASE. */
684 static htab_t micromips_op_hash
= NULL
;
686 /* This array holds the chars that always start a comment. If the
687 pre-processor is disabled, these aren't very useful. */
688 const char comment_chars
[] = "#";
690 /* This array holds the chars that only start a comment at the beginning of
691 a line. If the line seems to have the form '# 123 filename'
692 .line and .file directives will appear in the pre-processed output. */
693 /* Note that input_file.c hand checks for '#' at the beginning of the
694 first line of the input file. This is because the compiler outputs
695 #NO_APP at the beginning of its output. */
696 /* Also note that C style comments are always supported. */
697 const char line_comment_chars
[] = "#";
699 /* This array holds machine specific line separator characters. */
700 const char line_separator_chars
[] = ";";
702 /* Chars that can be used to separate mant from exp in floating point nums. */
703 const char EXP_CHARS
[] = "eE";
705 /* Chars that mean this number is a floating point constant.
708 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
710 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
711 changed in read.c . Ideally it shouldn't have to know about it at all,
712 but nothing is ideal around here. */
714 /* Types of printf format used for instruction-related error messages.
715 "I" means int ("%d") and "S" means string ("%s"). */
716 enum mips_insn_error_format
723 /* Information about an error that was found while assembling the current
725 struct mips_insn_error
727 /* We sometimes need to match an instruction against more than one
728 opcode table entry. Errors found during this matching are reported
729 against a particular syntactic argument rather than against the
730 instruction as a whole. We grade these messages so that errors
731 against argument N have a greater priority than an error against
732 any argument < N, since the former implies that arguments up to N
733 were acceptable and that the opcode entry was therefore a closer match.
734 If several matches report an error against the same argument,
735 we only use that error if it is the same in all cases.
737 min_argnum is the minimum argument number for which an error message
738 should be accepted. It is 0 if MSG is against the instruction as
742 /* The printf()-style message, including its format and arguments. */
743 enum mips_insn_error_format format
;
752 /* The error that should be reported for the current instruction. */
753 static struct mips_insn_error insn_error
;
755 static int auto_align
= 1;
757 /* When outputting SVR4 PIC code, the assembler needs to know the
758 offset in the stack frame from which to restore the $gp register.
759 This is set by the .cprestore pseudo-op, and saved in this
761 static offsetT mips_cprestore_offset
= -1;
763 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
764 more optimizations, it can use a register value instead of a memory-saved
765 offset and even an other register than $gp as global pointer. */
766 static offsetT mips_cpreturn_offset
= -1;
767 static int mips_cpreturn_register
= -1;
768 static int mips_gp_register
= GP
;
769 static int mips_gprel_offset
= 0;
771 /* Whether mips_cprestore_offset has been set in the current function
772 (or whether it has already been warned about, if not). */
773 static int mips_cprestore_valid
= 0;
775 /* This is the register which holds the stack frame, as set by the
776 .frame pseudo-op. This is needed to implement .cprestore. */
777 static int mips_frame_reg
= SP
;
779 /* Whether mips_frame_reg has been set in the current function
780 (or whether it has already been warned about, if not). */
781 static int mips_frame_reg_valid
= 0;
783 /* To output NOP instructions correctly, we need to keep information
784 about the previous two instructions. */
786 /* Whether we are optimizing. The default value of 2 means to remove
787 unneeded NOPs and swap branch instructions when possible. A value
788 of 1 means to not swap branches. A value of 0 means to always
790 static int mips_optimize
= 2;
792 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
793 equivalent to seeing no -g option at all. */
794 static int mips_debug
= 0;
796 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
797 #define MAX_VR4130_NOPS 4
799 /* The maximum number of NOPs needed to fill delay slots. */
800 #define MAX_DELAY_NOPS 2
802 /* The maximum number of NOPs needed for any purpose. */
805 /* The maximum range of context length of ll/sc. */
806 #define MAX_LLSC_RANGE 20
808 /* A list of previous instructions, with index 0 being the most recent.
809 We need to look back MAX_NOPS instructions when filling delay slots
810 or working around processor errata. We need to look back one
811 instruction further if we're thinking about using history[0] to
812 fill a branch delay slot. */
813 static struct mips_cl_insn history
[1 + MAX_NOPS
+ MAX_LLSC_RANGE
];
815 /* The maximum number of LABELS detect for the same address. */
816 #define MAX_LABELS_SAME 10
818 /* Arrays of operands for each instruction. */
819 #define MAX_OPERANDS 6
820 struct mips_operand_array
822 const struct mips_operand
*operand
[MAX_OPERANDS
];
824 static struct mips_operand_array
*mips_operands
;
825 static struct mips_operand_array
*mips16_operands
;
826 static struct mips_operand_array
*micromips_operands
;
828 /* Nop instructions used by emit_nop. */
829 static struct mips_cl_insn nop_insn
;
830 static struct mips_cl_insn mips16_nop_insn
;
831 static struct mips_cl_insn micromips_nop16_insn
;
832 static struct mips_cl_insn micromips_nop32_insn
;
834 /* Sync instructions used by insert sync. */
835 static struct mips_cl_insn sync_insn
;
837 /* The appropriate nop for the current mode. */
838 #define NOP_INSN (mips_opts.mips16 \
840 : (mips_opts.micromips \
841 ? (mips_opts.insn32 \
842 ? µmips_nop32_insn \
843 : µmips_nop16_insn) \
846 /* The size of NOP_INSN in bytes. */
847 #define NOP_INSN_SIZE ((mips_opts.mips16 \
848 || (mips_opts.micromips && !mips_opts.insn32)) \
851 /* If this is set, it points to a frag holding nop instructions which
852 were inserted before the start of a noreorder section. If those
853 nops turn out to be unnecessary, the size of the frag can be
855 static fragS
*prev_nop_frag
;
857 /* The number of nop instructions we created in prev_nop_frag. */
858 static int prev_nop_frag_holds
;
860 /* The number of nop instructions that we know we need in
862 static int prev_nop_frag_required
;
864 /* The number of instructions we've seen since prev_nop_frag. */
865 static int prev_nop_frag_since
;
867 /* Relocations against symbols are sometimes done in two parts, with a HI
868 relocation and a LO relocation. Each relocation has only 16 bits of
869 space to store an addend. This means that in order for the linker to
870 handle carries correctly, it must be able to locate both the HI and
871 the LO relocation. This means that the relocations must appear in
872 order in the relocation table.
874 In order to implement this, we keep track of each unmatched HI
875 relocation. We then sort them so that they immediately precede the
876 corresponding LO relocation. */
881 struct mips_hi_fixup
*next
;
884 /* The section this fixup is in. */
888 /* The list of unmatched HI relocs. */
890 static struct mips_hi_fixup
*mips_hi_fixup_list
;
892 /* Map mips16 register numbers to normal MIPS register numbers. */
894 static const unsigned int mips16_to_32_reg_map
[] =
896 16, 17, 2, 3, 4, 5, 6, 7
899 /* Map microMIPS register numbers to normal MIPS register numbers. */
901 #define micromips_to_32_reg_d_map mips16_to_32_reg_map
903 /* The microMIPS registers with type h. */
904 static const unsigned int micromips_to_32_reg_h_map1
[] =
906 5, 5, 6, 4, 4, 4, 4, 4
908 static const unsigned int micromips_to_32_reg_h_map2
[] =
910 6, 7, 7, 21, 22, 5, 6, 7
913 /* The microMIPS registers with type m. */
914 static const unsigned int micromips_to_32_reg_m_map
[] =
916 0, 17, 2, 3, 16, 18, 19, 20
919 #define micromips_to_32_reg_n_map micromips_to_32_reg_m_map
921 /* Classifies the kind of instructions we're interested in when
922 implementing -mfix-vr4120. */
923 enum fix_vr4120_class
931 NUM_FIX_VR4120_CLASSES
934 /* ...likewise -mfix-loongson2f-jump. */
935 static bfd_boolean mips_fix_loongson2f_jump
;
937 /* ...likewise -mfix-loongson2f-nop. */
938 static bfd_boolean mips_fix_loongson2f_nop
;
940 /* True if -mfix-loongson2f-nop or -mfix-loongson2f-jump passed. */
941 static bfd_boolean mips_fix_loongson2f
;
943 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
944 there must be at least one other instruction between an instruction
945 of type X and an instruction of type Y. */
946 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
948 /* True if -mfix-vr4120 is in force. */
949 static int mips_fix_vr4120
;
951 /* ...likewise -mfix-vr4130. */
952 static int mips_fix_vr4130
;
954 /* ...likewise -mfix-24k. */
955 static int mips_fix_24k
;
957 /* ...likewise -mfix-rm7000 */
958 static int mips_fix_rm7000
;
960 /* ...likewise -mfix-cn63xxp1 */
961 static bfd_boolean mips_fix_cn63xxp1
;
963 /* ...likewise -mfix-r5900 */
964 static bfd_boolean mips_fix_r5900
;
965 static bfd_boolean mips_fix_r5900_explicit
;
967 /* ...likewise -mfix-loongson3-llsc. */
968 static bfd_boolean mips_fix_loongson3_llsc
= DEFAULT_MIPS_FIX_LOONGSON3_LLSC
;
970 /* We don't relax branches by default, since this causes us to expand
971 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
972 fail to compute the offset before expanding the macro to the most
973 efficient expansion. */
975 static int mips_relax_branch
;
977 /* TRUE if checks are suppressed for invalid branches between ISA modes.
978 Needed for broken assembly produced by some GCC versions and some
979 sloppy code out there, where branches to data labels are present. */
980 static bfd_boolean mips_ignore_branch_isa
;
982 /* The expansion of many macros depends on the type of symbol that
983 they refer to. For example, when generating position-dependent code,
984 a macro that refers to a symbol may have two different expansions,
985 one which uses GP-relative addresses and one which uses absolute
986 addresses. When generating SVR4-style PIC, a macro may have
987 different expansions for local and global symbols.
989 We handle these situations by generating both sequences and putting
990 them in variant frags. In position-dependent code, the first sequence
991 will be the GP-relative one and the second sequence will be the
992 absolute one. In SVR4 PIC, the first sequence will be for global
993 symbols and the second will be for local symbols.
995 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
996 SECOND are the lengths of the two sequences in bytes. These fields
997 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
998 the subtype has the following flags:
1001 Set if generating PIC code.
1004 Set if it has been decided that we should use the second
1005 sequence instead of the first.
1008 Set in the first variant frag if the macro's second implementation
1009 is longer than its first. This refers to the macro as a whole,
1010 not an individual relaxation.
1013 Set in the first variant frag if the macro appeared in a .set nomacro
1014 block and if one alternative requires a warning but the other does not.
1017 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
1020 RELAX_DELAY_SLOT_16BIT
1021 Like RELAX_DELAY_SLOT, but indicates that the delay slot requires a
1024 RELAX_DELAY_SLOT_SIZE_FIRST
1025 Like RELAX_DELAY_SLOT, but indicates that the first implementation of
1026 the macro is of the wrong size for the branch delay slot.
1028 RELAX_DELAY_SLOT_SIZE_SECOND
1029 Like RELAX_DELAY_SLOT, but indicates that the second implementation of
1030 the macro is of the wrong size for the branch delay slot.
1032 The frag's "opcode" points to the first fixup for relaxable code.
1034 Relaxable macros are generated using a sequence such as:
1036 relax_start (SYMBOL);
1037 ... generate first expansion ...
1039 ... generate second expansion ...
1042 The code and fixups for the unwanted alternative are discarded
1043 by md_convert_frag. */
1044 #define RELAX_ENCODE(FIRST, SECOND, PIC) \
1045 (((FIRST) << 8) | (SECOND) | ((PIC) ? 0x10000 : 0))
1047 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
1048 #define RELAX_SECOND(X) ((X) & 0xff)
1049 #define RELAX_PIC(X) (((X) & 0x10000) != 0)
1050 #define RELAX_USE_SECOND 0x20000
1051 #define RELAX_SECOND_LONGER 0x40000
1052 #define RELAX_NOMACRO 0x80000
1053 #define RELAX_DELAY_SLOT 0x100000
1054 #define RELAX_DELAY_SLOT_16BIT 0x200000
1055 #define RELAX_DELAY_SLOT_SIZE_FIRST 0x400000
1056 #define RELAX_DELAY_SLOT_SIZE_SECOND 0x800000
1058 /* Branch without likely bit. If label is out of range, we turn:
1060 beq reg1, reg2, label
1070 with the following opcode replacements:
1077 bltzal <-> bgezal (with jal label instead of j label)
1079 Even though keeping the delay slot instruction in the delay slot of
1080 the branch would be more efficient, it would be very tricky to do
1081 correctly, because we'd have to introduce a variable frag *after*
1082 the delay slot instruction, and expand that instead. Let's do it
1083 the easy way for now, even if the branch-not-taken case now costs
1084 one additional instruction. Out-of-range branches are not supposed
1085 to be common, anyway.
1087 Branch likely. If label is out of range, we turn:
1089 beql reg1, reg2, label
1090 delay slot (annulled if branch not taken)
1099 delay slot (executed only if branch taken)
1102 It would be possible to generate a shorter sequence by losing the
1103 likely bit, generating something like:
1108 delay slot (executed only if branch taken)
1120 bltzall -> bgezal (with jal label instead of j label)
1121 bgezall -> bltzal (ditto)
1124 but it's not clear that it would actually improve performance. */
1125 #define RELAX_BRANCH_ENCODE(at, pic, \
1126 uncond, likely, link, toofar) \
1127 ((relax_substateT) \
1130 | ((pic) ? 0x20 : 0) \
1131 | ((toofar) ? 0x40 : 0) \
1132 | ((link) ? 0x80 : 0) \
1133 | ((likely) ? 0x100 : 0) \
1134 | ((uncond) ? 0x200 : 0)))
1135 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
1136 #define RELAX_BRANCH_UNCOND(i) (((i) & 0x200) != 0)
1137 #define RELAX_BRANCH_LIKELY(i) (((i) & 0x100) != 0)
1138 #define RELAX_BRANCH_LINK(i) (((i) & 0x80) != 0)
1139 #define RELAX_BRANCH_TOOFAR(i) (((i) & 0x40) != 0)
1140 #define RELAX_BRANCH_PIC(i) (((i) & 0x20) != 0)
1141 #define RELAX_BRANCH_AT(i) ((i) & 0x1f)
1143 /* For mips16 code, we use an entirely different form of relaxation.
1144 mips16 supports two versions of most instructions which take
1145 immediate values: a small one which takes some small value, and a
1146 larger one which takes a 16 bit value. Since branches also follow
1147 this pattern, relaxing these values is required.
1149 We can assemble both mips16 and normal MIPS code in a single
1150 object. Therefore, we need to support this type of relaxation at
1151 the same time that we support the relaxation described above. We
1152 use the high bit of the subtype field to distinguish these cases.
1154 The information we store for this type of relaxation is the
1155 argument code found in the opcode file for this relocation, whether
1156 the user explicitly requested a small or extended form, and whether
1157 the relocation is in a jump or jal delay slot. That tells us the
1158 size of the value, and how it should be stored. We also store
1159 whether the fragment is considered to be extended or not. We also
1160 store whether this is known to be a branch to a different section,
1161 whether we have tried to relax this frag yet, and whether we have
1162 ever extended a PC relative fragment because of a shift count. */
1163 #define RELAX_MIPS16_ENCODE(type, e2, pic, sym32, nomacro, \
1168 | ((e2) ? 0x100 : 0) \
1169 | ((pic) ? 0x200 : 0) \
1170 | ((sym32) ? 0x400 : 0) \
1171 | ((nomacro) ? 0x800 : 0) \
1172 | ((small) ? 0x1000 : 0) \
1173 | ((ext) ? 0x2000 : 0) \
1174 | ((dslot) ? 0x4000 : 0) \
1175 | ((jal_dslot) ? 0x8000 : 0))
1177 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
1178 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
1179 #define RELAX_MIPS16_E2(i) (((i) & 0x100) != 0)
1180 #define RELAX_MIPS16_PIC(i) (((i) & 0x200) != 0)
1181 #define RELAX_MIPS16_SYM32(i) (((i) & 0x400) != 0)
1182 #define RELAX_MIPS16_NOMACRO(i) (((i) & 0x800) != 0)
1183 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x1000) != 0)
1184 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x2000) != 0)
1185 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x4000) != 0)
1186 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x8000) != 0)
1188 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x10000) != 0)
1189 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x10000)
1190 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) & ~0x10000)
1191 #define RELAX_MIPS16_ALWAYS_EXTENDED(i) (((i) & 0x20000) != 0)
1192 #define RELAX_MIPS16_MARK_ALWAYS_EXTENDED(i) ((i) | 0x20000)
1193 #define RELAX_MIPS16_CLEAR_ALWAYS_EXTENDED(i) ((i) & ~0x20000)
1194 #define RELAX_MIPS16_MACRO(i) (((i) & 0x40000) != 0)
1195 #define RELAX_MIPS16_MARK_MACRO(i) ((i) | 0x40000)
1196 #define RELAX_MIPS16_CLEAR_MACRO(i) ((i) & ~0x40000)
1198 /* For microMIPS code, we use relaxation similar to one we use for
1199 MIPS16 code. Some instructions that take immediate values support
1200 two encodings: a small one which takes some small value, and a
1201 larger one which takes a 16 bit value. As some branches also follow
1202 this pattern, relaxing these values is required.
1204 We can assemble both microMIPS and normal MIPS code in a single
1205 object. Therefore, we need to support this type of relaxation at
1206 the same time that we support the relaxation described above. We
1207 use one of the high bits of the subtype field to distinguish these
1210 The information we store for this type of relaxation is the argument
1211 code found in the opcode file for this relocation, the register
1212 selected as the assembler temporary, whether in the 32-bit
1213 instruction mode, whether the branch is unconditional, whether it is
1214 compact, whether there is no delay-slot instruction available to fill
1215 in, whether it stores the link address implicitly in $ra, whether
1216 relaxation of out-of-range 32-bit branches to a sequence of
1217 instructions is enabled, and whether the displacement of a branch is
1218 too large to fit as an immediate argument of a 16-bit and a 32-bit
1219 branch, respectively. */
1220 #define RELAX_MICROMIPS_ENCODE(type, at, insn32, pic, \
1221 uncond, compact, link, nods, \
1222 relax32, toofar16, toofar32) \
1225 | (((at) & 0x1f) << 8) \
1226 | ((insn32) ? 0x2000 : 0) \
1227 | ((pic) ? 0x4000 : 0) \
1228 | ((uncond) ? 0x8000 : 0) \
1229 | ((compact) ? 0x10000 : 0) \
1230 | ((link) ? 0x20000 : 0) \
1231 | ((nods) ? 0x40000 : 0) \
1232 | ((relax32) ? 0x80000 : 0) \
1233 | ((toofar16) ? 0x100000 : 0) \
1234 | ((toofar32) ? 0x200000 : 0))
1235 #define RELAX_MICROMIPS_P(i) (((i) & 0xc0000000) == 0x40000000)
1236 #define RELAX_MICROMIPS_TYPE(i) ((i) & 0xff)
1237 #define RELAX_MICROMIPS_AT(i) (((i) >> 8) & 0x1f)
1238 #define RELAX_MICROMIPS_INSN32(i) (((i) & 0x2000) != 0)
1239 #define RELAX_MICROMIPS_PIC(i) (((i) & 0x4000) != 0)
1240 #define RELAX_MICROMIPS_UNCOND(i) (((i) & 0x8000) != 0)
1241 #define RELAX_MICROMIPS_COMPACT(i) (((i) & 0x10000) != 0)
1242 #define RELAX_MICROMIPS_LINK(i) (((i) & 0x20000) != 0)
1243 #define RELAX_MICROMIPS_NODS(i) (((i) & 0x40000) != 0)
1244 #define RELAX_MICROMIPS_RELAX32(i) (((i) & 0x80000) != 0)
1246 #define RELAX_MICROMIPS_TOOFAR16(i) (((i) & 0x100000) != 0)
1247 #define RELAX_MICROMIPS_MARK_TOOFAR16(i) ((i) | 0x100000)
1248 #define RELAX_MICROMIPS_CLEAR_TOOFAR16(i) ((i) & ~0x100000)
1249 #define RELAX_MICROMIPS_TOOFAR32(i) (((i) & 0x200000) != 0)
1250 #define RELAX_MICROMIPS_MARK_TOOFAR32(i) ((i) | 0x200000)
1251 #define RELAX_MICROMIPS_CLEAR_TOOFAR32(i) ((i) & ~0x200000)
1253 /* Sign-extend 16-bit value X. */
1254 #define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000)
1256 /* Is the given value a sign-extended 32-bit value? */
1257 #define IS_SEXT_32BIT_NUM(x) \
1258 (((x) &~ (offsetT) 0x7fffffff) == 0 \
1259 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
1261 /* Is the given value a sign-extended 16-bit value? */
1262 #define IS_SEXT_16BIT_NUM(x) \
1263 (((x) &~ (offsetT) 0x7fff) == 0 \
1264 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
1266 /* Is the given value a sign-extended 12-bit value? */
1267 #define IS_SEXT_12BIT_NUM(x) \
1268 (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x))
1270 /* Is the given value a sign-extended 9-bit value? */
1271 #define IS_SEXT_9BIT_NUM(x) \
1272 (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x))
1274 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
1275 #define IS_ZEXT_32BIT_NUM(x) \
1276 (((x) &~ (offsetT) 0xffffffff) == 0 \
1277 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
1279 /* Extract bits MASK << SHIFT from STRUCT and shift them right
1281 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
1282 (((STRUCT) >> (SHIFT)) & (MASK))
1284 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
1285 #define EXTRACT_OPERAND(MICROMIPS, FIELD, INSN) \
1287 ? EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD) \
1288 : EXTRACT_BITS ((INSN).insn_opcode, \
1289 MICROMIPSOP_MASK_##FIELD, MICROMIPSOP_SH_##FIELD))
1290 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
1291 EXTRACT_BITS ((INSN).insn_opcode, \
1292 MIPS16OP_MASK_##FIELD, \
1293 MIPS16OP_SH_##FIELD)
1295 /* The MIPS16 EXTEND opcode, shifted left 16 places. */
1296 #define MIPS16_EXTEND (0xf000U << 16)
1298 /* Whether or not we are emitting a branch-likely macro. */
1299 static bfd_boolean emit_branch_likely_macro
= FALSE
;
1301 /* Global variables used when generating relaxable macros. See the
1302 comment above RELAX_ENCODE for more details about how relaxation
1305 /* 0 if we're not emitting a relaxable macro.
1306 1 if we're emitting the first of the two relaxation alternatives.
1307 2 if we're emitting the second alternative. */
1310 /* The first relaxable fixup in the current frag. (In other words,
1311 the first fixup that refers to relaxable code.) */
1314 /* sizes[0] says how many bytes of the first alternative are stored in
1315 the current frag. Likewise sizes[1] for the second alternative. */
1316 unsigned int sizes
[2];
1318 /* The symbol on which the choice of sequence depends. */
1322 /* Global variables used to decide whether a macro needs a warning. */
1324 /* True if the macro is in a branch delay slot. */
1325 bfd_boolean delay_slot_p
;
1327 /* Set to the length in bytes required if the macro is in a delay slot
1328 that requires a specific length of instruction, otherwise zero. */
1329 unsigned int delay_slot_length
;
1331 /* For relaxable macros, sizes[0] is the length of the first alternative
1332 in bytes and sizes[1] is the length of the second alternative.
1333 For non-relaxable macros, both elements give the length of the
1335 unsigned int sizes
[2];
1337 /* For relaxable macros, first_insn_sizes[0] is the length of the first
1338 instruction of the first alternative in bytes and first_insn_sizes[1]
1339 is the length of the first instruction of the second alternative.
1340 For non-relaxable macros, both elements give the length of the first
1341 instruction in bytes.
1343 Set to zero if we haven't yet seen the first instruction. */
1344 unsigned int first_insn_sizes
[2];
1346 /* For relaxable macros, insns[0] is the number of instructions for the
1347 first alternative and insns[1] is the number of instructions for the
1350 For non-relaxable macros, both elements give the number of
1351 instructions for the macro. */
1352 unsigned int insns
[2];
1354 /* The first variant frag for this macro. */
1356 } mips_macro_warning
;
1358 /* Prototypes for static functions. */
1360 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
1362 static void append_insn
1363 (struct mips_cl_insn
*, expressionS
*, bfd_reloc_code_real_type
*,
1364 bfd_boolean expansionp
);
1365 static void mips_no_prev_insn (void);
1366 static void macro_build (expressionS
*, const char *, const char *, ...);
1367 static void mips16_macro_build
1368 (expressionS
*, const char *, const char *, va_list *);
1369 static void load_register (int, expressionS
*, int);
1370 static void macro_start (void);
1371 static void macro_end (void);
1372 static void macro (struct mips_cl_insn
*ip
, char *str
);
1373 static void mips16_macro (struct mips_cl_insn
* ip
);
1374 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
1375 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
1376 static unsigned long mips16_immed_extend (offsetT
, unsigned int);
1377 static void mips16_immed
1378 (const char *, unsigned int, int, bfd_reloc_code_real_type
, offsetT
,
1379 unsigned int, unsigned long *);
1380 static size_t my_getSmallExpression
1381 (expressionS
*, bfd_reloc_code_real_type
*, char *);
1382 static void my_getExpression (expressionS
*, char *);
1383 static void s_align (int);
1384 static void s_change_sec (int);
1385 static void s_change_section (int);
1386 static void s_cons (int);
1387 static void s_float_cons (int);
1388 static void s_mips_globl (int);
1389 static void s_option (int);
1390 static void s_mipsset (int);
1391 static void s_abicalls (int);
1392 static void s_cpload (int);
1393 static void s_cpsetup (int);
1394 static void s_cplocal (int);
1395 static void s_cprestore (int);
1396 static void s_cpreturn (int);
1397 static void s_dtprelword (int);
1398 static void s_dtpreldword (int);
1399 static void s_tprelword (int);
1400 static void s_tpreldword (int);
1401 static void s_gpvalue (int);
1402 static void s_gpword (int);
1403 static void s_gpdword (int);
1404 static void s_ehword (int);
1405 static void s_cpadd (int);
1406 static void s_insn (int);
1407 static void s_nan (int);
1408 static void s_module (int);
1409 static void s_mips_ent (int);
1410 static void s_mips_end (int);
1411 static void s_mips_frame (int);
1412 static void s_mips_mask (int reg_type
);
1413 static void s_mips_stab (int);
1414 static void s_mips_weakext (int);
1415 static void s_mips_file (int);
1416 static void s_mips_loc (int);
1417 static bfd_boolean
pic_need_relax (symbolS
*);
1418 static int relaxed_branch_length (fragS
*, asection
*, int);
1419 static int relaxed_micromips_16bit_branch_length (fragS
*, asection
*, int);
1420 static int relaxed_micromips_32bit_branch_length (fragS
*, asection
*, int);
1421 static void file_mips_check_options (void);
1423 /* Table and functions used to map between CPU/ISA names, and
1424 ISA levels, and CPU numbers. */
1426 struct mips_cpu_info
1428 const char *name
; /* CPU or ISA name. */
1429 int flags
; /* MIPS_CPU_* flags. */
1430 int ase
; /* Set of ASEs implemented by the CPU. */
1431 int isa
; /* ISA level. */
1432 int cpu
; /* CPU number (default CPU if ISA). */
1435 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1437 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1438 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1439 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1441 /* Command-line options. */
1442 const char *md_shortopts
= "O::g::G:";
1446 OPTION_MARCH
= OPTION_MD_BASE
,
1478 OPTION_NO_SMARTMIPS
,
1488 OPTION_NO_MICROMIPS
,
1503 OPTION_M7000_HILO_FIX
,
1504 OPTION_MNO_7000_HILO_FIX
,
1508 OPTION_NO_FIX_RM7000
,
1509 OPTION_FIX_LOONGSON3_LLSC
,
1510 OPTION_NO_FIX_LOONGSON3_LLSC
,
1511 OPTION_FIX_LOONGSON2F_JUMP
,
1512 OPTION_NO_FIX_LOONGSON2F_JUMP
,
1513 OPTION_FIX_LOONGSON2F_NOP
,
1514 OPTION_NO_FIX_LOONGSON2F_NOP
,
1516 OPTION_NO_FIX_VR4120
,
1518 OPTION_NO_FIX_VR4130
,
1519 OPTION_FIX_CN63XXP1
,
1520 OPTION_NO_FIX_CN63XXP1
,
1522 OPTION_NO_FIX_R5900
,
1529 OPTION_CONSTRUCT_FLOATS
,
1530 OPTION_NO_CONSTRUCT_FLOATS
,
1534 OPTION_RELAX_BRANCH
,
1535 OPTION_NO_RELAX_BRANCH
,
1536 OPTION_IGNORE_BRANCH_ISA
,
1537 OPTION_NO_IGNORE_BRANCH_ISA
,
1546 OPTION_SINGLE_FLOAT
,
1547 OPTION_DOUBLE_FLOAT
,
1560 OPTION_MVXWORKS_PIC
,
1563 OPTION_NO_ODD_SPREG
,
1566 OPTION_LOONGSON_MMI
,
1567 OPTION_NO_LOONGSON_MMI
,
1568 OPTION_LOONGSON_CAM
,
1569 OPTION_NO_LOONGSON_CAM
,
1570 OPTION_LOONGSON_EXT
,
1571 OPTION_NO_LOONGSON_EXT
,
1572 OPTION_LOONGSON_EXT2
,
1573 OPTION_NO_LOONGSON_EXT2
,
1577 struct option md_longopts
[] =
1579 /* Options which specify architecture. */
1580 {"march", required_argument
, NULL
, OPTION_MARCH
},
1581 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
1582 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
1583 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
1584 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
1585 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
1586 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
1587 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
1588 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
1589 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
1590 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
1591 {"mips32r3", no_argument
, NULL
, OPTION_MIPS32R3
},
1592 {"mips32r5", no_argument
, NULL
, OPTION_MIPS32R5
},
1593 {"mips32r6", no_argument
, NULL
, OPTION_MIPS32R6
},
1594 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
1595 {"mips64r3", no_argument
, NULL
, OPTION_MIPS64R3
},
1596 {"mips64r5", no_argument
, NULL
, OPTION_MIPS64R5
},
1597 {"mips64r6", no_argument
, NULL
, OPTION_MIPS64R6
},
1599 /* Options which specify Application Specific Extensions (ASEs). */
1600 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
1601 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
1602 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
1603 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
1604 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
1605 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
1606 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
1607 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
1608 {"mmt", no_argument
, NULL
, OPTION_MT
},
1609 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
1610 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
1611 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
1612 {"mdspr2", no_argument
, NULL
, OPTION_DSPR2
},
1613 {"mno-dspr2", no_argument
, NULL
, OPTION_NO_DSPR2
},
1614 {"mdspr3", no_argument
, NULL
, OPTION_DSPR3
},
1615 {"mno-dspr3", no_argument
, NULL
, OPTION_NO_DSPR3
},
1616 {"meva", no_argument
, NULL
, OPTION_EVA
},
1617 {"mno-eva", no_argument
, NULL
, OPTION_NO_EVA
},
1618 {"mmicromips", no_argument
, NULL
, OPTION_MICROMIPS
},
1619 {"mno-micromips", no_argument
, NULL
, OPTION_NO_MICROMIPS
},
1620 {"mmcu", no_argument
, NULL
, OPTION_MCU
},
1621 {"mno-mcu", no_argument
, NULL
, OPTION_NO_MCU
},
1622 {"mvirt", no_argument
, NULL
, OPTION_VIRT
},
1623 {"mno-virt", no_argument
, NULL
, OPTION_NO_VIRT
},
1624 {"mmsa", no_argument
, NULL
, OPTION_MSA
},
1625 {"mno-msa", no_argument
, NULL
, OPTION_NO_MSA
},
1626 {"mxpa", no_argument
, NULL
, OPTION_XPA
},
1627 {"mno-xpa", no_argument
, NULL
, OPTION_NO_XPA
},
1628 {"mmips16e2", no_argument
, NULL
, OPTION_MIPS16E2
},
1629 {"mno-mips16e2", no_argument
, NULL
, OPTION_NO_MIPS16E2
},
1630 {"mcrc", no_argument
, NULL
, OPTION_CRC
},
1631 {"mno-crc", no_argument
, NULL
, OPTION_NO_CRC
},
1632 {"mginv", no_argument
, NULL
, OPTION_GINV
},
1633 {"mno-ginv", no_argument
, NULL
, OPTION_NO_GINV
},
1634 {"mloongson-mmi", no_argument
, NULL
, OPTION_LOONGSON_MMI
},
1635 {"mno-loongson-mmi", no_argument
, NULL
, OPTION_NO_LOONGSON_MMI
},
1636 {"mloongson-cam", no_argument
, NULL
, OPTION_LOONGSON_CAM
},
1637 {"mno-loongson-cam", no_argument
, NULL
, OPTION_NO_LOONGSON_CAM
},
1638 {"mloongson-ext", no_argument
, NULL
, OPTION_LOONGSON_EXT
},
1639 {"mno-loongson-ext", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT
},
1640 {"mloongson-ext2", no_argument
, NULL
, OPTION_LOONGSON_EXT2
},
1641 {"mno-loongson-ext2", no_argument
, NULL
, OPTION_NO_LOONGSON_EXT2
},
1643 /* Old-style architecture options. Don't add more of these. */
1644 {"m4650", no_argument
, NULL
, OPTION_M4650
},
1645 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
1646 {"m4010", no_argument
, NULL
, OPTION_M4010
},
1647 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
1648 {"m4100", no_argument
, NULL
, OPTION_M4100
},
1649 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
1650 {"m3900", no_argument
, NULL
, OPTION_M3900
},
1651 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
1653 /* Options which enable bug fixes. */
1654 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
1655 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1656 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
1657 {"mfix-loongson3-llsc", no_argument
, NULL
, OPTION_FIX_LOONGSON3_LLSC
},
1658 {"mno-fix-loongson3-llsc", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON3_LLSC
},
1659 {"mfix-loongson2f-jump", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_JUMP
},
1660 {"mno-fix-loongson2f-jump", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_JUMP
},
1661 {"mfix-loongson2f-nop", no_argument
, NULL
, OPTION_FIX_LOONGSON2F_NOP
},
1662 {"mno-fix-loongson2f-nop", no_argument
, NULL
, OPTION_NO_FIX_LOONGSON2F_NOP
},
1663 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
1664 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
1665 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
1666 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
1667 {"mfix-24k", no_argument
, NULL
, OPTION_FIX_24K
},
1668 {"mno-fix-24k", no_argument
, NULL
, OPTION_NO_FIX_24K
},
1669 {"mfix-rm7000", no_argument
, NULL
, OPTION_FIX_RM7000
},
1670 {"mno-fix-rm7000", no_argument
, NULL
, OPTION_NO_FIX_RM7000
},
1671 {"mfix-cn63xxp1", no_argument
, NULL
, OPTION_FIX_CN63XXP1
},
1672 {"mno-fix-cn63xxp1", no_argument
, NULL
, OPTION_NO_FIX_CN63XXP1
},
1673 {"mfix-r5900", no_argument
, NULL
, OPTION_FIX_R5900
},
1674 {"mno-fix-r5900", no_argument
, NULL
, OPTION_NO_FIX_R5900
},
1676 /* Miscellaneous options. */
1677 {"trap", no_argument
, NULL
, OPTION_TRAP
},
1678 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
1679 {"break", no_argument
, NULL
, OPTION_BREAK
},
1680 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
1681 {"EB", no_argument
, NULL
, OPTION_EB
},
1682 {"EL", no_argument
, NULL
, OPTION_EL
},
1683 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
1684 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
1685 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
1686 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
1687 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
1688 {"mfpxx", no_argument
, NULL
, OPTION_FPXX
},
1689 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
1690 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
1691 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
1692 {"mignore-branch-isa", no_argument
, NULL
, OPTION_IGNORE_BRANCH_ISA
},
1693 {"mno-ignore-branch-isa", no_argument
, NULL
, OPTION_NO_IGNORE_BRANCH_ISA
},
1694 {"minsn32", no_argument
, NULL
, OPTION_INSN32
},
1695 {"mno-insn32", no_argument
, NULL
, OPTION_NO_INSN32
},
1696 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
1697 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
1698 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
1699 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
1700 {"msoft-float", no_argument
, NULL
, OPTION_SOFT_FLOAT
},
1701 {"mhard-float", no_argument
, NULL
, OPTION_HARD_FLOAT
},
1702 {"msingle-float", no_argument
, NULL
, OPTION_SINGLE_FLOAT
},
1703 {"mdouble-float", no_argument
, NULL
, OPTION_DOUBLE_FLOAT
},
1704 {"modd-spreg", no_argument
, NULL
, OPTION_ODD_SPREG
},
1705 {"mno-odd-spreg", no_argument
, NULL
, OPTION_NO_ODD_SPREG
},
1707 /* Strictly speaking this next option is ELF specific,
1708 but we allow it for other ports as well in order to
1709 make testing easier. */
1710 {"32", no_argument
, NULL
, OPTION_32
},
1712 /* ELF-specific options. */
1713 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
1714 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
1715 {"call_nonpic", no_argument
, NULL
, OPTION_CALL_NONPIC
},
1716 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
1717 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
1718 {"mabi", required_argument
, NULL
, OPTION_MABI
},
1719 {"n32", no_argument
, NULL
, OPTION_N32
},
1720 {"64", no_argument
, NULL
, OPTION_64
},
1721 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
1722 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
1723 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
1724 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
1725 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
1726 {"mnan", required_argument
, NULL
, OPTION_NAN
},
1728 {NULL
, no_argument
, NULL
, 0}
1730 size_t md_longopts_size
= sizeof (md_longopts
);
1732 /* Information about either an Application Specific Extension or an
1733 optional architecture feature that, for simplicity, we treat in the
1734 same way as an ASE. */
1737 /* The name of the ASE, used in both the command-line and .set options. */
1740 /* The associated ASE_* flags. If the ASE is available on both 32-bit
1741 and 64-bit architectures, the flags here refer to the subset that
1742 is available on both. */
1745 /* The ASE_* flag used for instructions that are available on 64-bit
1746 architectures but that are not included in FLAGS. */
1747 unsigned int flags64
;
1749 /* The command-line options that turn the ASE on and off. */
1753 /* The minimum required architecture revisions for MIPS32, MIPS64,
1754 microMIPS32 and microMIPS64, or -1 if the extension isn't supported. */
1757 int micromips32_rev
;
1758 int micromips64_rev
;
1760 /* The architecture where the ASE was removed or -1 if the extension has not
1765 /* A table of all supported ASEs. */
1766 static const struct mips_ase mips_ases
[] = {
1767 { "dsp", ASE_DSP
, ASE_DSP64
,
1768 OPTION_DSP
, OPTION_NO_DSP
,
1772 { "dspr2", ASE_DSP
| ASE_DSPR2
, 0,
1773 OPTION_DSPR2
, OPTION_NO_DSPR2
,
1777 { "dspr3", ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
, 0,
1778 OPTION_DSPR3
, OPTION_NO_DSPR3
,
1782 { "eva", ASE_EVA
, 0,
1783 OPTION_EVA
, OPTION_NO_EVA
,
1787 { "mcu", ASE_MCU
, 0,
1788 OPTION_MCU
, OPTION_NO_MCU
,
1792 /* Deprecated in MIPS64r5, but we don't implement that yet. */
1793 { "mdmx", ASE_MDMX
, 0,
1794 OPTION_MDMX
, OPTION_NO_MDMX
,
1798 /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */
1799 { "mips3d", ASE_MIPS3D
, 0,
1800 OPTION_MIPS3D
, OPTION_NO_MIPS3D
,
1805 OPTION_MT
, OPTION_NO_MT
,
1809 { "smartmips", ASE_SMARTMIPS
, 0,
1810 OPTION_SMARTMIPS
, OPTION_NO_SMARTMIPS
,
1814 { "virt", ASE_VIRT
, ASE_VIRT64
,
1815 OPTION_VIRT
, OPTION_NO_VIRT
,
1819 { "msa", ASE_MSA
, ASE_MSA64
,
1820 OPTION_MSA
, OPTION_NO_MSA
,
1824 { "xpa", ASE_XPA
, 0,
1825 OPTION_XPA
, OPTION_NO_XPA
,
1829 { "mips16e2", ASE_MIPS16E2
, 0,
1830 OPTION_MIPS16E2
, OPTION_NO_MIPS16E2
,
1834 { "crc", ASE_CRC
, ASE_CRC64
,
1835 OPTION_CRC
, OPTION_NO_CRC
,
1839 { "ginv", ASE_GINV
, 0,
1840 OPTION_GINV
, OPTION_NO_GINV
,
1844 { "loongson-mmi", ASE_LOONGSON_MMI
, 0,
1845 OPTION_LOONGSON_MMI
, OPTION_NO_LOONGSON_MMI
,
1849 { "loongson-cam", ASE_LOONGSON_CAM
, 0,
1850 OPTION_LOONGSON_CAM
, OPTION_NO_LOONGSON_CAM
,
1854 { "loongson-ext", ASE_LOONGSON_EXT
, 0,
1855 OPTION_LOONGSON_EXT
, OPTION_NO_LOONGSON_EXT
,
1859 { "loongson-ext2", ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
, 0,
1860 OPTION_LOONGSON_EXT2
, OPTION_NO_LOONGSON_EXT2
,
1865 /* The set of ASEs that require -mfp64. */
1866 #define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA)
1868 /* Groups of ASE_* flags that represent different revisions of an ASE. */
1869 static const unsigned int mips_ase_groups
[] = {
1870 ASE_DSP
| ASE_DSPR2
| ASE_DSPR3
,
1871 ASE_LOONGSON_EXT
| ASE_LOONGSON_EXT2
1876 The following pseudo-ops from the Kane and Heinrich MIPS book
1877 should be defined here, but are currently unsupported: .alias,
1878 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1880 The following pseudo-ops from the Kane and Heinrich MIPS book are
1881 specific to the type of debugging information being generated, and
1882 should be defined by the object format: .aent, .begin, .bend,
1883 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1886 The following pseudo-ops from the Kane and Heinrich MIPS book are
1887 not MIPS CPU specific, but are also not specific to the object file
1888 format. This file is probably the best place to define them, but
1889 they are not currently supported: .asm0, .endr, .lab, .struct. */
1891 static const pseudo_typeS mips_pseudo_table
[] =
1893 /* MIPS specific pseudo-ops. */
1894 {"option", s_option
, 0},
1895 {"set", s_mipsset
, 0},
1896 {"rdata", s_change_sec
, 'r'},
1897 {"sdata", s_change_sec
, 's'},
1898 {"livereg", s_ignore
, 0},
1899 {"abicalls", s_abicalls
, 0},
1900 {"cpload", s_cpload
, 0},
1901 {"cpsetup", s_cpsetup
, 0},
1902 {"cplocal", s_cplocal
, 0},
1903 {"cprestore", s_cprestore
, 0},
1904 {"cpreturn", s_cpreturn
, 0},
1905 {"dtprelword", s_dtprelword
, 0},
1906 {"dtpreldword", s_dtpreldword
, 0},
1907 {"tprelword", s_tprelword
, 0},
1908 {"tpreldword", s_tpreldword
, 0},
1909 {"gpvalue", s_gpvalue
, 0},
1910 {"gpword", s_gpword
, 0},
1911 {"gpdword", s_gpdword
, 0},
1912 {"ehword", s_ehword
, 0},
1913 {"cpadd", s_cpadd
, 0},
1914 {"insn", s_insn
, 0},
1916 {"module", s_module
, 0},
1918 /* Relatively generic pseudo-ops that happen to be used on MIPS
1920 {"asciiz", stringer
, 8 + 1},
1921 {"bss", s_change_sec
, 'b'},
1923 {"half", s_cons
, 1},
1924 {"dword", s_cons
, 3},
1925 {"weakext", s_mips_weakext
, 0},
1926 {"origin", s_org
, 0},
1927 {"repeat", s_rept
, 0},
1929 /* For MIPS this is non-standard, but we define it for consistency. */
1930 {"sbss", s_change_sec
, 'B'},
1932 /* These pseudo-ops are defined in read.c, but must be overridden
1933 here for one reason or another. */
1934 {"align", s_align
, 0},
1935 {"byte", s_cons
, 0},
1936 {"data", s_change_sec
, 'd'},
1937 {"double", s_float_cons
, 'd'},
1938 {"float", s_float_cons
, 'f'},
1939 {"globl", s_mips_globl
, 0},
1940 {"global", s_mips_globl
, 0},
1941 {"hword", s_cons
, 1},
1943 {"long", s_cons
, 2},
1944 {"octa", s_cons
, 4},
1945 {"quad", s_cons
, 3},
1946 {"section", s_change_section
, 0},
1947 {"short", s_cons
, 1},
1948 {"single", s_float_cons
, 'f'},
1949 {"stabd", s_mips_stab
, 'd'},
1950 {"stabn", s_mips_stab
, 'n'},
1951 {"stabs", s_mips_stab
, 's'},
1952 {"text", s_change_sec
, 't'},
1953 {"word", s_cons
, 2},
1955 { "extern", ecoff_directive_extern
, 0},
1960 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1962 /* These pseudo-ops should be defined by the object file format.
1963 However, a.out doesn't support them, so we have versions here. */
1964 {"aent", s_mips_ent
, 1},
1965 {"bgnb", s_ignore
, 0},
1966 {"end", s_mips_end
, 0},
1967 {"endb", s_ignore
, 0},
1968 {"ent", s_mips_ent
, 0},
1969 {"file", s_mips_file
, 0},
1970 {"fmask", s_mips_mask
, 'F'},
1971 {"frame", s_mips_frame
, 0},
1972 {"loc", s_mips_loc
, 0},
1973 {"mask", s_mips_mask
, 'R'},
1974 {"verstamp", s_ignore
, 0},
1978 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
1979 purpose of the `.dc.a' internal pseudo-op. */
1982 mips_address_bytes (void)
1984 file_mips_check_options ();
1985 return HAVE_64BIT_ADDRESSES
? 8 : 4;
1988 extern void pop_insert (const pseudo_typeS
*);
1991 mips_pop_insert (void)
1993 pop_insert (mips_pseudo_table
);
1994 if (! ECOFF_DEBUGGING
)
1995 pop_insert (mips_nonecoff_pseudo_table
);
1998 /* Symbols labelling the current insn. */
2000 struct insn_label_list
2002 struct insn_label_list
*next
;
2006 static struct insn_label_list
*free_insn_labels
;
2007 #define label_list tc_segment_info_data.labels
2009 static void mips_clear_insn_labels (void);
2010 static void mips_mark_labels (void);
2011 static void mips_compressed_mark_labels (void);
2014 mips_clear_insn_labels (void)
2016 struct insn_label_list
**pl
;
2017 segment_info_type
*si
;
2021 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
2024 si
= seg_info (now_seg
);
2025 *pl
= si
->label_list
;
2026 si
->label_list
= NULL
;
2030 /* Mark instruction labels in MIPS16/microMIPS mode. */
2033 mips_mark_labels (void)
2035 if (HAVE_CODE_COMPRESSION
)
2036 mips_compressed_mark_labels ();
2039 static char *expr_end
;
2041 /* An expression in a macro instruction. This is set by mips_ip and
2042 mips16_ip and when populated is always an O_constant. */
2044 static expressionS imm_expr
;
2046 /* The relocatable field in an instruction and the relocs associated
2047 with it. These variables are used for instructions like LUI and
2048 JAL as well as true offsets. They are also used for address
2049 operands in macros. */
2051 static expressionS offset_expr
;
2052 static bfd_reloc_code_real_type offset_reloc
[3]
2053 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
2055 /* This is set to the resulting size of the instruction to be produced
2056 by mips16_ip if an explicit extension is used or by mips_ip if an
2057 explicit size is supplied. */
2059 static unsigned int forced_insn_length
;
2061 /* True if we are assembling an instruction. All dot symbols defined during
2062 this time should be treated as code labels. */
2064 static bfd_boolean mips_assembling_insn
;
2066 /* The pdr segment for per procedure frame/regmask info. Not used for
2069 static segT pdr_seg
;
2071 /* The default target format to use. */
2073 #if defined (TE_FreeBSD)
2074 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips-freebsd"
2075 #elif defined (TE_TMIPS)
2076 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "mips"
2078 #define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "mips"
2082 mips_target_format (void)
2084 switch (OUTPUT_FLAVOR
)
2086 case bfd_target_elf_flavour
:
2088 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
2089 return (target_big_endian
2090 ? "elf32-bigmips-vxworks"
2091 : "elf32-littlemips-vxworks");
2093 return (target_big_endian
2094 ? (HAVE_64BIT_OBJECTS
2095 ? ELF_TARGET ("elf64-", "big")
2097 ? ELF_TARGET ("elf32-n", "big")
2098 : ELF_TARGET ("elf32-", "big")))
2099 : (HAVE_64BIT_OBJECTS
2100 ? ELF_TARGET ("elf64-", "little")
2102 ? ELF_TARGET ("elf32-n", "little")
2103 : ELF_TARGET ("elf32-", "little"))));
2110 /* Return the ISA revision that is currently in use, or 0 if we are
2111 generating code for MIPS V or below. */
2116 if (mips_opts
.isa
== ISA_MIPS32R2
|| mips_opts
.isa
== ISA_MIPS64R2
)
2119 if (mips_opts
.isa
== ISA_MIPS32R3
|| mips_opts
.isa
== ISA_MIPS64R3
)
2122 if (mips_opts
.isa
== ISA_MIPS32R5
|| mips_opts
.isa
== ISA_MIPS64R5
)
2125 if (mips_opts
.isa
== ISA_MIPS32R6
|| mips_opts
.isa
== ISA_MIPS64R6
)
2128 /* microMIPS implies revision 2 or above. */
2129 if (mips_opts
.micromips
)
2132 if (mips_opts
.isa
== ISA_MIPS32
|| mips_opts
.isa
== ISA_MIPS64
)
2138 /* Return the mask of all ASEs that are revisions of those in FLAGS. */
2141 mips_ase_mask (unsigned int flags
)
2145 for (i
= 0; i
< ARRAY_SIZE (mips_ase_groups
); i
++)
2146 if (flags
& mips_ase_groups
[i
])
2147 flags
|= mips_ase_groups
[i
];
2151 /* Check whether the current ISA supports ASE. Issue a warning if
2155 mips_check_isa_supports_ase (const struct mips_ase
*ase
)
2159 static unsigned int warned_isa
;
2160 static unsigned int warned_fp32
;
2162 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
2163 min_rev
= mips_opts
.micromips
? ase
->micromips64_rev
: ase
->mips64_rev
;
2165 min_rev
= mips_opts
.micromips
? ase
->micromips32_rev
: ase
->mips32_rev
;
2166 if ((min_rev
< 0 || mips_isa_rev () < min_rev
)
2167 && (warned_isa
& ase
->flags
) != ase
->flags
)
2169 warned_isa
|= ase
->flags
;
2170 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2171 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2173 as_warn (_("the %d-bit %s architecture does not support the"
2174 " `%s' extension"), size
, base
, ase
->name
);
2176 as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
2177 ase
->name
, base
, size
, min_rev
);
2179 else if ((ase
->rem_rev
> 0 && mips_isa_rev () >= ase
->rem_rev
)
2180 && (warned_isa
& ase
->flags
) != ase
->flags
)
2182 warned_isa
|= ase
->flags
;
2183 base
= mips_opts
.micromips
? "microMIPS" : "MIPS";
2184 size
= ISA_HAS_64BIT_REGS (mips_opts
.isa
) ? 64 : 32;
2185 as_warn (_("the `%s' extension was removed in %s%d revision %d"),
2186 ase
->name
, base
, size
, ase
->rem_rev
);
2189 if ((ase
->flags
& FP64_ASES
)
2190 && mips_opts
.fp
!= 64
2191 && (warned_fp32
& ase
->flags
) != ase
->flags
)
2193 warned_fp32
|= ase
->flags
;
2194 as_warn (_("the `%s' extension requires 64-bit FPRs"), ase
->name
);
2198 /* Check all enabled ASEs to see whether they are supported by the
2199 chosen architecture. */
2202 mips_check_isa_supports_ases (void)
2204 unsigned int i
, mask
;
2206 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2208 mask
= mips_ase_mask (mips_ases
[i
].flags
);
2209 if ((mips_opts
.ase
& mask
) == mips_ases
[i
].flags
)
2210 mips_check_isa_supports_ase (&mips_ases
[i
]);
2214 /* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags
2215 that were affected. */
2218 mips_set_ase (const struct mips_ase
*ase
, struct mips_set_options
*opts
,
2219 bfd_boolean enabled_p
)
2223 mask
= mips_ase_mask (ase
->flags
);
2226 /* Clear combination ASE flags, which need to be recalculated based on
2227 updated regular ASE settings. */
2228 opts
->ase
&= ~(ASE_MIPS16E2_MT
| ASE_XPA_VIRT
| ASE_EVA_R6
);
2231 opts
->ase
|= ase
->flags
;
2233 /* The Virtualization ASE has eXtended Physical Addressing (XPA)
2234 instructions which are only valid when both ASEs are enabled.
2235 This sets the ASE_XPA_VIRT flag when both ASEs are present. */
2236 if ((opts
->ase
& (ASE_XPA
| ASE_VIRT
)) == (ASE_XPA
| ASE_VIRT
))
2238 opts
->ase
|= ASE_XPA_VIRT
;
2239 mask
|= ASE_XPA_VIRT
;
2241 if ((opts
->ase
& (ASE_MIPS16E2
| ASE_MT
)) == (ASE_MIPS16E2
| ASE_MT
))
2243 opts
->ase
|= ASE_MIPS16E2_MT
;
2244 mask
|= ASE_MIPS16E2_MT
;
2247 /* The EVA Extension has instructions which are only valid when the R6 ISA
2248 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
2250 if (((opts
->ase
& ASE_EVA
) != 0) && ISA_IS_R6 (opts
->isa
))
2252 opts
->ase
|= ASE_EVA_R6
;
2259 /* Return the ASE called NAME, or null if none. */
2261 static const struct mips_ase
*
2262 mips_lookup_ase (const char *name
)
2266 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
2267 if (strcmp (name
, mips_ases
[i
].name
) == 0)
2268 return &mips_ases
[i
];
2272 /* Return the length of a microMIPS instruction in bytes. If bits of
2273 the mask beyond the low 16 are 0, then it is a 16-bit instruction,
2274 otherwise it is a 32-bit instruction. */
2276 static inline unsigned int
2277 micromips_insn_length (const struct mips_opcode
*mo
)
2279 return mips_opcode_32bit_p (mo
) ? 4 : 2;
2282 /* Return the length of MIPS16 instruction OPCODE. */
2284 static inline unsigned int
2285 mips16_opcode_length (unsigned long opcode
)
2287 return (opcode
>> 16) == 0 ? 2 : 4;
2290 /* Return the length of instruction INSN. */
2292 static inline unsigned int
2293 insn_length (const struct mips_cl_insn
*insn
)
2295 if (mips_opts
.micromips
)
2296 return micromips_insn_length (insn
->insn_mo
);
2297 else if (mips_opts
.mips16
)
2298 return mips16_opcode_length (insn
->insn_opcode
);
2303 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
2306 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
2311 insn
->insn_opcode
= mo
->match
;
2314 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2315 insn
->fixp
[i
] = NULL
;
2316 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
2317 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
2318 insn
->mips16_absolute_jump_p
= 0;
2319 insn
->complete_p
= 0;
2320 insn
->cleared_p
= 0;
2323 /* Get a list of all the operands in INSN. */
2325 static const struct mips_operand_array
*
2326 insn_operands (const struct mips_cl_insn
*insn
)
2328 if (insn
->insn_mo
>= &mips_opcodes
[0]
2329 && insn
->insn_mo
< &mips_opcodes
[NUMOPCODES
])
2330 return &mips_operands
[insn
->insn_mo
- &mips_opcodes
[0]];
2332 if (insn
->insn_mo
>= &mips16_opcodes
[0]
2333 && insn
->insn_mo
< &mips16_opcodes
[bfd_mips16_num_opcodes
])
2334 return &mips16_operands
[insn
->insn_mo
- &mips16_opcodes
[0]];
2336 if (insn
->insn_mo
>= µmips_opcodes
[0]
2337 && insn
->insn_mo
< µmips_opcodes
[bfd_micromips_num_opcodes
])
2338 return µmips_operands
[insn
->insn_mo
- µmips_opcodes
[0]];
2343 /* Get a description of operand OPNO of INSN. */
2345 static const struct mips_operand
*
2346 insn_opno (const struct mips_cl_insn
*insn
, unsigned opno
)
2348 const struct mips_operand_array
*operands
;
2350 operands
= insn_operands (insn
);
2351 if (opno
>= MAX_OPERANDS
|| !operands
->operand
[opno
])
2353 return operands
->operand
[opno
];
2356 /* Install UVAL as the value of OPERAND in INSN. */
2359 insn_insert_operand (struct mips_cl_insn
*insn
,
2360 const struct mips_operand
*operand
, unsigned int uval
)
2362 if (mips_opts
.mips16
2363 && operand
->type
== OP_INT
&& operand
->lsb
== 0
2364 && mips_opcode_32bit_p (insn
->insn_mo
))
2365 insn
->insn_opcode
|= mips16_immed_extend (uval
, operand
->size
);
2367 insn
->insn_opcode
= mips_insert_operand (operand
, insn
->insn_opcode
, uval
);
2370 /* Extract the value of OPERAND from INSN. */
2372 static inline unsigned
2373 insn_extract_operand (const struct mips_cl_insn
*insn
,
2374 const struct mips_operand
*operand
)
2376 return mips_extract_operand (operand
, insn
->insn_opcode
);
2379 /* Record the current MIPS16/microMIPS mode in now_seg. */
2382 mips_record_compressed_mode (void)
2384 segment_info_type
*si
;
2386 si
= seg_info (now_seg
);
2387 if (si
->tc_segment_info_data
.mips16
!= mips_opts
.mips16
)
2388 si
->tc_segment_info_data
.mips16
= mips_opts
.mips16
;
2389 if (si
->tc_segment_info_data
.micromips
!= mips_opts
.micromips
)
2390 si
->tc_segment_info_data
.micromips
= mips_opts
.micromips
;
2393 /* Read a standard MIPS instruction from BUF. */
2395 static unsigned long
2396 read_insn (char *buf
)
2398 if (target_big_endian
)
2399 return bfd_getb32 ((bfd_byte
*) buf
);
2401 return bfd_getl32 ((bfd_byte
*) buf
);
2404 /* Write standard MIPS instruction INSN to BUF. Return a pointer to
2408 write_insn (char *buf
, unsigned int insn
)
2410 md_number_to_chars (buf
, insn
, 4);
2414 /* Read a microMIPS or MIPS16 opcode from BUF, given that it
2415 has length LENGTH. */
2417 static unsigned long
2418 read_compressed_insn (char *buf
, unsigned int length
)
2424 for (i
= 0; i
< length
; i
+= 2)
2427 if (target_big_endian
)
2428 insn
|= bfd_getb16 ((char *) buf
);
2430 insn
|= bfd_getl16 ((char *) buf
);
2436 /* Write microMIPS or MIPS16 instruction INSN to BUF, given that the
2437 instruction is LENGTH bytes long. Return a pointer to the next byte. */
2440 write_compressed_insn (char *buf
, unsigned int insn
, unsigned int length
)
2444 for (i
= 0; i
< length
; i
+= 2)
2445 md_number_to_chars (buf
+ i
, insn
>> ((length
- i
- 2) * 8), 2);
2446 return buf
+ length
;
2449 /* Install INSN at the location specified by its "frag" and "where" fields. */
2452 install_insn (const struct mips_cl_insn
*insn
)
2454 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
2455 if (HAVE_CODE_COMPRESSION
)
2456 write_compressed_insn (f
, insn
->insn_opcode
, insn_length (insn
));
2458 write_insn (f
, insn
->insn_opcode
);
2459 mips_record_compressed_mode ();
2462 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
2463 and install the opcode in the new location. */
2466 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
2471 insn
->where
= where
;
2472 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
2473 if (insn
->fixp
[i
] != NULL
)
2475 insn
->fixp
[i
]->fx_frag
= frag
;
2476 insn
->fixp
[i
]->fx_where
= where
;
2478 install_insn (insn
);
2481 /* Add INSN to the end of the output. */
2484 add_fixed_insn (struct mips_cl_insn
*insn
)
2486 char *f
= frag_more (insn_length (insn
));
2487 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
2490 /* Start a variant frag and move INSN to the start of the variant part,
2491 marking it as fixed. The other arguments are as for frag_var. */
2494 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
2495 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
2497 frag_grow (max_chars
);
2498 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
2500 frag_var (rs_machine_dependent
, max_chars
, var
,
2501 subtype
, symbol
, offset
, NULL
);
2504 /* Insert N copies of INSN into the history buffer, starting at
2505 position FIRST. Neither FIRST nor N need to be clipped. */
2508 insert_into_history (unsigned int first
, unsigned int n
,
2509 const struct mips_cl_insn
*insn
)
2511 if (mips_relax
.sequence
!= 2)
2515 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
2517 history
[i
] = history
[i
- n
];
2523 /* Clear the error in insn_error. */
2526 clear_insn_error (void)
2528 memset (&insn_error
, 0, sizeof (insn_error
));
2531 /* Possibly record error message MSG for the current instruction.
2532 If the error is about a particular argument, ARGNUM is the 1-based
2533 number of that argument, otherwise it is 0. FORMAT is the format
2534 of MSG. Return true if MSG was used, false if the current message
2538 set_insn_error_format (int argnum
, enum mips_insn_error_format format
,
2543 /* Give priority to errors against specific arguments, and to
2544 the first whole-instruction message. */
2550 /* Keep insn_error if it is against a later argument. */
2551 if (argnum
< insn_error
.min_argnum
)
2554 /* If both errors are against the same argument but are different,
2555 give up on reporting a specific error for this argument.
2556 See the comment about mips_insn_error for details. */
2557 if (argnum
== insn_error
.min_argnum
2559 && strcmp (insn_error
.msg
, msg
) != 0)
2562 insn_error
.min_argnum
+= 1;
2566 insn_error
.min_argnum
= argnum
;
2567 insn_error
.format
= format
;
2568 insn_error
.msg
= msg
;
2572 /* Record an instruction error with no % format fields. ARGNUM and MSG are
2573 as for set_insn_error_format. */
2576 set_insn_error (int argnum
, const char *msg
)
2578 set_insn_error_format (argnum
, ERR_FMT_PLAIN
, msg
);
2581 /* Record an instruction error with one %d field I. ARGNUM and MSG are
2582 as for set_insn_error_format. */
2585 set_insn_error_i (int argnum
, const char *msg
, int i
)
2587 if (set_insn_error_format (argnum
, ERR_FMT_I
, msg
))
2591 /* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG
2592 are as for set_insn_error_format. */
2595 set_insn_error_ss (int argnum
, const char *msg
, const char *s1
, const char *s2
)
2597 if (set_insn_error_format (argnum
, ERR_FMT_SS
, msg
))
2599 insn_error
.u
.ss
[0] = s1
;
2600 insn_error
.u
.ss
[1] = s2
;
2604 /* Report the error in insn_error, which is against assembly code STR. */
2607 report_insn_error (const char *str
)
2609 const char *msg
= concat (insn_error
.msg
, " `%s'", NULL
);
2611 switch (insn_error
.format
)
2618 as_bad (msg
, insn_error
.u
.i
, str
);
2622 as_bad (msg
, insn_error
.u
.ss
[0], insn_error
.u
.ss
[1], str
);
2626 free ((char *) msg
);
2629 /* Initialize vr4120_conflicts. There is a bit of duplication here:
2630 the idea is to make it obvious at a glance that each errata is
2634 init_vr4120_conflicts (void)
2636 #define CONFLICT(FIRST, SECOND) \
2637 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
2639 /* Errata 21 - [D]DIV[U] after [D]MACC */
2640 CONFLICT (MACC
, DIV
);
2641 CONFLICT (DMACC
, DIV
);
2643 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
2644 CONFLICT (DMULT
, DMULT
);
2645 CONFLICT (DMULT
, DMACC
);
2646 CONFLICT (DMACC
, DMULT
);
2647 CONFLICT (DMACC
, DMACC
);
2649 /* Errata 24 - MT{LO,HI} after [D]MACC */
2650 CONFLICT (MACC
, MTHILO
);
2651 CONFLICT (DMACC
, MTHILO
);
2653 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
2654 instruction is executed immediately after a MACC or DMACC
2655 instruction, the result of [either instruction] is incorrect." */
2656 CONFLICT (MACC
, MULT
);
2657 CONFLICT (MACC
, DMULT
);
2658 CONFLICT (DMACC
, MULT
);
2659 CONFLICT (DMACC
, DMULT
);
2661 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
2662 executed immediately after a DMULT, DMULTU, DIV, DIVU,
2663 DDIV or DDIVU instruction, the result of the MACC or
2664 DMACC instruction is incorrect.". */
2665 CONFLICT (DMULT
, MACC
);
2666 CONFLICT (DMULT
, DMACC
);
2667 CONFLICT (DIV
, MACC
);
2668 CONFLICT (DIV
, DMACC
);
2678 #define RNUM_MASK 0x00000ff
2679 #define RTYPE_MASK 0x0ffff00
2680 #define RTYPE_NUM 0x0000100
2681 #define RTYPE_FPU 0x0000200
2682 #define RTYPE_FCC 0x0000400
2683 #define RTYPE_VEC 0x0000800
2684 #define RTYPE_GP 0x0001000
2685 #define RTYPE_CP0 0x0002000
2686 #define RTYPE_PC 0x0004000
2687 #define RTYPE_ACC 0x0008000
2688 #define RTYPE_CCC 0x0010000
2689 #define RTYPE_VI 0x0020000
2690 #define RTYPE_VF 0x0040000
2691 #define RTYPE_R5900_I 0x0080000
2692 #define RTYPE_R5900_Q 0x0100000
2693 #define RTYPE_R5900_R 0x0200000
2694 #define RTYPE_R5900_ACC 0x0400000
2695 #define RTYPE_MSA 0x0800000
2696 #define RWARN 0x8000000
2698 #define GENERIC_REGISTER_NUMBERS \
2699 {"$0", RTYPE_NUM | 0}, \
2700 {"$1", RTYPE_NUM | 1}, \
2701 {"$2", RTYPE_NUM | 2}, \
2702 {"$3", RTYPE_NUM | 3}, \
2703 {"$4", RTYPE_NUM | 4}, \
2704 {"$5", RTYPE_NUM | 5}, \
2705 {"$6", RTYPE_NUM | 6}, \
2706 {"$7", RTYPE_NUM | 7}, \
2707 {"$8", RTYPE_NUM | 8}, \
2708 {"$9", RTYPE_NUM | 9}, \
2709 {"$10", RTYPE_NUM | 10}, \
2710 {"$11", RTYPE_NUM | 11}, \
2711 {"$12", RTYPE_NUM | 12}, \
2712 {"$13", RTYPE_NUM | 13}, \
2713 {"$14", RTYPE_NUM | 14}, \
2714 {"$15", RTYPE_NUM | 15}, \
2715 {"$16", RTYPE_NUM | 16}, \
2716 {"$17", RTYPE_NUM | 17}, \
2717 {"$18", RTYPE_NUM | 18}, \
2718 {"$19", RTYPE_NUM | 19}, \
2719 {"$20", RTYPE_NUM | 20}, \
2720 {"$21", RTYPE_NUM | 21}, \
2721 {"$22", RTYPE_NUM | 22}, \
2722 {"$23", RTYPE_NUM | 23}, \
2723 {"$24", RTYPE_NUM | 24}, \
2724 {"$25", RTYPE_NUM | 25}, \
2725 {"$26", RTYPE_NUM | 26}, \
2726 {"$27", RTYPE_NUM | 27}, \
2727 {"$28", RTYPE_NUM | 28}, \
2728 {"$29", RTYPE_NUM | 29}, \
2729 {"$30", RTYPE_NUM | 30}, \
2730 {"$31", RTYPE_NUM | 31}
2732 #define FPU_REGISTER_NAMES \
2733 {"$f0", RTYPE_FPU | 0}, \
2734 {"$f1", RTYPE_FPU | 1}, \
2735 {"$f2", RTYPE_FPU | 2}, \
2736 {"$f3", RTYPE_FPU | 3}, \
2737 {"$f4", RTYPE_FPU | 4}, \
2738 {"$f5", RTYPE_FPU | 5}, \
2739 {"$f6", RTYPE_FPU | 6}, \
2740 {"$f7", RTYPE_FPU | 7}, \
2741 {"$f8", RTYPE_FPU | 8}, \
2742 {"$f9", RTYPE_FPU | 9}, \
2743 {"$f10", RTYPE_FPU | 10}, \
2744 {"$f11", RTYPE_FPU | 11}, \
2745 {"$f12", RTYPE_FPU | 12}, \
2746 {"$f13", RTYPE_FPU | 13}, \
2747 {"$f14", RTYPE_FPU | 14}, \
2748 {"$f15", RTYPE_FPU | 15}, \
2749 {"$f16", RTYPE_FPU | 16}, \
2750 {"$f17", RTYPE_FPU | 17}, \
2751 {"$f18", RTYPE_FPU | 18}, \
2752 {"$f19", RTYPE_FPU | 19}, \
2753 {"$f20", RTYPE_FPU | 20}, \
2754 {"$f21", RTYPE_FPU | 21}, \
2755 {"$f22", RTYPE_FPU | 22}, \
2756 {"$f23", RTYPE_FPU | 23}, \
2757 {"$f24", RTYPE_FPU | 24}, \
2758 {"$f25", RTYPE_FPU | 25}, \
2759 {"$f26", RTYPE_FPU | 26}, \
2760 {"$f27", RTYPE_FPU | 27}, \
2761 {"$f28", RTYPE_FPU | 28}, \
2762 {"$f29", RTYPE_FPU | 29}, \
2763 {"$f30", RTYPE_FPU | 30}, \
2764 {"$f31", RTYPE_FPU | 31}
2766 #define FPU_CONDITION_CODE_NAMES \
2767 {"$fcc0", RTYPE_FCC | 0}, \
2768 {"$fcc1", RTYPE_FCC | 1}, \
2769 {"$fcc2", RTYPE_FCC | 2}, \
2770 {"$fcc3", RTYPE_FCC | 3}, \
2771 {"$fcc4", RTYPE_FCC | 4}, \
2772 {"$fcc5", RTYPE_FCC | 5}, \
2773 {"$fcc6", RTYPE_FCC | 6}, \
2774 {"$fcc7", RTYPE_FCC | 7}
2776 #define COPROC_CONDITION_CODE_NAMES \
2777 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
2778 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
2779 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
2780 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
2781 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
2782 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
2783 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
2784 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
2786 #define N32N64_SYMBOLIC_REGISTER_NAMES \
2787 {"$a4", RTYPE_GP | 8}, \
2788 {"$a5", RTYPE_GP | 9}, \
2789 {"$a6", RTYPE_GP | 10}, \
2790 {"$a7", RTYPE_GP | 11}, \
2791 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
2792 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
2793 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
2794 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
2795 {"$t0", RTYPE_GP | 12}, \
2796 {"$t1", RTYPE_GP | 13}, \
2797 {"$t2", RTYPE_GP | 14}, \
2798 {"$t3", RTYPE_GP | 15}
2800 #define O32_SYMBOLIC_REGISTER_NAMES \
2801 {"$t0", RTYPE_GP | 8}, \
2802 {"$t1", RTYPE_GP | 9}, \
2803 {"$t2", RTYPE_GP | 10}, \
2804 {"$t3", RTYPE_GP | 11}, \
2805 {"$t4", RTYPE_GP | 12}, \
2806 {"$t5", RTYPE_GP | 13}, \
2807 {"$t6", RTYPE_GP | 14}, \
2808 {"$t7", RTYPE_GP | 15}, \
2809 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
2810 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
2811 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
2812 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
2814 /* Remaining symbolic register names. */
2815 #define SYMBOLIC_REGISTER_NAMES \
2816 {"$zero", RTYPE_GP | 0}, \
2817 {"$at", RTYPE_GP | 1}, \
2818 {"$AT", RTYPE_GP | 1}, \
2819 {"$v0", RTYPE_GP | 2}, \
2820 {"$v1", RTYPE_GP | 3}, \
2821 {"$a0", RTYPE_GP | 4}, \
2822 {"$a1", RTYPE_GP | 5}, \
2823 {"$a2", RTYPE_GP | 6}, \
2824 {"$a3", RTYPE_GP | 7}, \
2825 {"$s0", RTYPE_GP | 16}, \
2826 {"$s1", RTYPE_GP | 17}, \
2827 {"$s2", RTYPE_GP | 18}, \
2828 {"$s3", RTYPE_GP | 19}, \
2829 {"$s4", RTYPE_GP | 20}, \
2830 {"$s5", RTYPE_GP | 21}, \
2831 {"$s6", RTYPE_GP | 22}, \
2832 {"$s7", RTYPE_GP | 23}, \
2833 {"$t8", RTYPE_GP | 24}, \
2834 {"$t9", RTYPE_GP | 25}, \
2835 {"$k0", RTYPE_GP | 26}, \
2836 {"$kt0", RTYPE_GP | 26}, \
2837 {"$k1", RTYPE_GP | 27}, \
2838 {"$kt1", RTYPE_GP | 27}, \
2839 {"$gp", RTYPE_GP | 28}, \
2840 {"$sp", RTYPE_GP | 29}, \
2841 {"$s8", RTYPE_GP | 30}, \
2842 {"$fp", RTYPE_GP | 30}, \
2843 {"$ra", RTYPE_GP | 31}
2845 #define MIPS16_SPECIAL_REGISTER_NAMES \
2846 {"$pc", RTYPE_PC | 0}
2848 #define MDMX_VECTOR_REGISTER_NAMES \
2849 /* {"$v0", RTYPE_VEC | 0}, Clash with REG 2 above. */ \
2850 /* {"$v1", RTYPE_VEC | 1}, Clash with REG 3 above. */ \
2851 {"$v2", RTYPE_VEC | 2}, \
2852 {"$v3", RTYPE_VEC | 3}, \
2853 {"$v4", RTYPE_VEC | 4}, \
2854 {"$v5", RTYPE_VEC | 5}, \
2855 {"$v6", RTYPE_VEC | 6}, \
2856 {"$v7", RTYPE_VEC | 7}, \
2857 {"$v8", RTYPE_VEC | 8}, \
2858 {"$v9", RTYPE_VEC | 9}, \
2859 {"$v10", RTYPE_VEC | 10}, \
2860 {"$v11", RTYPE_VEC | 11}, \
2861 {"$v12", RTYPE_VEC | 12}, \
2862 {"$v13", RTYPE_VEC | 13}, \
2863 {"$v14", RTYPE_VEC | 14}, \
2864 {"$v15", RTYPE_VEC | 15}, \
2865 {"$v16", RTYPE_VEC | 16}, \
2866 {"$v17", RTYPE_VEC | 17}, \
2867 {"$v18", RTYPE_VEC | 18}, \
2868 {"$v19", RTYPE_VEC | 19}, \
2869 {"$v20", RTYPE_VEC | 20}, \
2870 {"$v21", RTYPE_VEC | 21}, \
2871 {"$v22", RTYPE_VEC | 22}, \
2872 {"$v23", RTYPE_VEC | 23}, \
2873 {"$v24", RTYPE_VEC | 24}, \
2874 {"$v25", RTYPE_VEC | 25}, \
2875 {"$v26", RTYPE_VEC | 26}, \
2876 {"$v27", RTYPE_VEC | 27}, \
2877 {"$v28", RTYPE_VEC | 28}, \
2878 {"$v29", RTYPE_VEC | 29}, \
2879 {"$v30", RTYPE_VEC | 30}, \
2880 {"$v31", RTYPE_VEC | 31}
2882 #define R5900_I_NAMES \
2883 {"$I", RTYPE_R5900_I | 0}
2885 #define R5900_Q_NAMES \
2886 {"$Q", RTYPE_R5900_Q | 0}
2888 #define R5900_R_NAMES \
2889 {"$R", RTYPE_R5900_R | 0}
2891 #define R5900_ACC_NAMES \
2892 {"$ACC", RTYPE_R5900_ACC | 0 }
2894 #define MIPS_DSP_ACCUMULATOR_NAMES \
2895 {"$ac0", RTYPE_ACC | 0}, \
2896 {"$ac1", RTYPE_ACC | 1}, \
2897 {"$ac2", RTYPE_ACC | 2}, \
2898 {"$ac3", RTYPE_ACC | 3}
2900 static const struct regname reg_names
[] = {
2901 GENERIC_REGISTER_NUMBERS
,
2903 FPU_CONDITION_CODE_NAMES
,
2904 COPROC_CONDITION_CODE_NAMES
,
2906 /* The $txx registers depends on the abi,
2907 these will be added later into the symbol table from
2908 one of the tables below once mips_abi is set after
2909 parsing of arguments from the command line. */
2910 SYMBOLIC_REGISTER_NAMES
,
2912 MIPS16_SPECIAL_REGISTER_NAMES
,
2913 MDMX_VECTOR_REGISTER_NAMES
,
2918 MIPS_DSP_ACCUMULATOR_NAMES
,
2922 static const struct regname reg_names_o32
[] = {
2923 O32_SYMBOLIC_REGISTER_NAMES
,
2927 static const struct regname reg_names_n32n64
[] = {
2928 N32N64_SYMBOLIC_REGISTER_NAMES
,
2932 /* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be
2933 interpreted as vector registers 0 and 1. If SYMVAL is the value of one
2934 of these register symbols, return the associated vector register,
2935 otherwise return SYMVAL itself. */
2938 mips_prefer_vec_regno (unsigned int symval
)
2940 if ((symval
& -2) == (RTYPE_GP
| 2))
2941 return RTYPE_VEC
| (symval
& 1);
2945 /* Return true if string [S, E) is a valid register name, storing its
2946 symbol value in *SYMVAL_PTR if so. */
2949 mips_parse_register_1 (char *s
, char *e
, unsigned int *symval_ptr
)
2954 /* Terminate name. */
2958 /* Look up the name. */
2959 symbol
= symbol_find (s
);
2962 if (!symbol
|| S_GET_SEGMENT (symbol
) != reg_section
)
2965 *symval_ptr
= S_GET_VALUE (symbol
);
2969 /* Return true if the string at *SPTR is a valid register name. Allow it
2970 to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
2973 When returning true, move *SPTR past the register, store the
2974 register's symbol value in *SYMVAL_PTR and the channel mask in
2975 *CHANNELS_PTR (if nonnull). The symbol value includes the register
2976 number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
2977 is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
2980 mips_parse_register (char **sptr
, unsigned int *symval_ptr
,
2981 unsigned int *channels_ptr
)
2985 unsigned int channels
, symval
, bit
;
2987 /* Find end of name. */
2989 if (is_name_beginner (*e
))
2991 while (is_part_of_name (*e
))
2995 if (!mips_parse_register_1 (s
, e
, &symval
))
3000 /* Eat characters from the end of the string that are valid
3001 channel suffixes. The preceding register must be $ACC or
3002 end with a digit, so there is no ambiguity. */
3005 for (q
= "wzyx"; *q
; q
++, bit
<<= 1)
3006 if (m
> s
&& m
[-1] == *q
)
3013 || !mips_parse_register_1 (s
, m
, &symval
)
3014 || (symval
& (RTYPE_VI
| RTYPE_VF
| RTYPE_R5900_ACC
)) == 0)
3019 *symval_ptr
= symval
;
3021 *channels_ptr
= channels
;
3025 /* Check if SPTR points at a valid register specifier according to TYPES.
3026 If so, then return 1, advance S to consume the specifier and store
3027 the register's number in REGNOP, otherwise return 0. */
3030 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
3034 if (mips_parse_register (s
, ®no
, NULL
))
3036 if (types
& RTYPE_VEC
)
3037 regno
= mips_prefer_vec_regno (regno
);
3046 as_warn (_("unrecognized register name `%s'"), *s
);
3051 return regno
<= RNUM_MASK
;
3054 /* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
3055 mask in *CHANNELS. Return a pointer to the first unconsumed character. */
3058 mips_parse_vu0_channels (char *s
, unsigned int *channels
)
3063 for (i
= 0; i
< 4; i
++)
3064 if (*s
== "xyzw"[i
])
3066 *channels
|= 1 << (3 - i
);
3072 /* Token types for parsed operand lists. */
3073 enum mips_operand_token_type
{
3074 /* A plain register, e.g. $f2. */
3077 /* A 4-bit XYZW channel mask. */
3080 /* A constant vector index, e.g. [1]. */
3083 /* A register vector index, e.g. [$2]. */
3086 /* A continuous range of registers, e.g. $s0-$s4. */
3089 /* A (possibly relocated) expression. */
3092 /* A floating-point value. */
3095 /* A single character. This can be '(', ')' or ',', but '(' only appears
3099 /* A doubled character, either "--" or "++". */
3102 /* The end of the operand list. */
3106 /* A parsed operand token. */
3107 struct mips_operand_token
3109 /* The type of token. */
3110 enum mips_operand_token_type type
;
3113 /* The register symbol value for an OT_REG or OT_REG_INDEX. */
3116 /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
3117 unsigned int channels
;
3119 /* The integer value of an OT_INTEGER_INDEX. */
3122 /* The two register symbol values involved in an OT_REG_RANGE. */
3124 unsigned int regno1
;
3125 unsigned int regno2
;
3128 /* The value of an OT_INTEGER. The value is represented as an
3129 expression and the relocation operators that were applied to
3130 that expression. The reloc entries are BFD_RELOC_UNUSED if no
3131 relocation operators were used. */
3134 bfd_reloc_code_real_type relocs
[3];
3137 /* The binary data for an OT_FLOAT constant, and the number of bytes
3140 unsigned char data
[8];
3144 /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
3149 /* An obstack used to construct lists of mips_operand_tokens. */
3150 static struct obstack mips_operand_tokens
;
3152 /* Give TOKEN type TYPE and add it to mips_operand_tokens. */
3155 mips_add_token (struct mips_operand_token
*token
,
3156 enum mips_operand_token_type type
)
3159 obstack_grow (&mips_operand_tokens
, token
, sizeof (*token
));
3162 /* Check whether S is '(' followed by a register name. Add OT_CHAR
3163 and OT_REG tokens for them if so, and return a pointer to the first
3164 unconsumed character. Return null otherwise. */
3167 mips_parse_base_start (char *s
)
3169 struct mips_operand_token token
;
3170 unsigned int regno
, channels
;
3171 bfd_boolean decrement_p
;
3177 SKIP_SPACE_TABS (s
);
3179 /* Only match "--" as part of a base expression. In other contexts "--X"
3180 is a double negative. */
3181 decrement_p
= (s
[0] == '-' && s
[1] == '-');
3185 SKIP_SPACE_TABS (s
);
3188 /* Allow a channel specifier because that leads to better error messages
3189 than treating something like "$vf0x++" as an expression. */
3190 if (!mips_parse_register (&s
, ®no
, &channels
))
3194 mips_add_token (&token
, OT_CHAR
);
3199 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3202 token
.u
.regno
= regno
;
3203 mips_add_token (&token
, OT_REG
);
3207 token
.u
.channels
= channels
;
3208 mips_add_token (&token
, OT_CHANNELS
);
3211 /* For consistency, only match "++" as part of base expressions too. */
3212 SKIP_SPACE_TABS (s
);
3213 if (s
[0] == '+' && s
[1] == '+')
3217 mips_add_token (&token
, OT_DOUBLE_CHAR
);
3223 /* Parse one or more tokens from S. Return a pointer to the first
3224 unconsumed character on success. Return null if an error was found
3225 and store the error text in insn_error. FLOAT_FORMAT is as for
3226 mips_parse_arguments. */
3229 mips_parse_argument_token (char *s
, char float_format
)
3231 char *end
, *save_in
;
3233 unsigned int regno1
, regno2
, channels
;
3234 struct mips_operand_token token
;
3236 /* First look for "($reg", since we want to treat that as an
3237 OT_CHAR and OT_REG rather than an expression. */
3238 end
= mips_parse_base_start (s
);
3242 /* Handle other characters that end up as OT_CHARs. */
3243 if (*s
== ')' || *s
== ',')
3246 mips_add_token (&token
, OT_CHAR
);
3251 /* Handle tokens that start with a register. */
3252 if (mips_parse_register (&s
, ®no1
, &channels
))
3256 /* A register and a VU0 channel suffix. */
3257 token
.u
.regno
= regno1
;
3258 mips_add_token (&token
, OT_REG
);
3260 token
.u
.channels
= channels
;
3261 mips_add_token (&token
, OT_CHANNELS
);
3265 SKIP_SPACE_TABS (s
);
3268 /* A register range. */
3270 SKIP_SPACE_TABS (s
);
3271 if (!mips_parse_register (&s
, ®no2
, NULL
))
3273 set_insn_error (0, _("invalid register range"));
3277 token
.u
.reg_range
.regno1
= regno1
;
3278 token
.u
.reg_range
.regno2
= regno2
;
3279 mips_add_token (&token
, OT_REG_RANGE
);
3283 /* Add the register itself. */
3284 token
.u
.regno
= regno1
;
3285 mips_add_token (&token
, OT_REG
);
3287 /* Check for a vector index. */
3291 SKIP_SPACE_TABS (s
);
3292 if (mips_parse_register (&s
, &token
.u
.regno
, NULL
))
3293 mips_add_token (&token
, OT_REG_INDEX
);
3296 expressionS element
;
3298 my_getExpression (&element
, s
);
3299 if (element
.X_op
!= O_constant
)
3301 set_insn_error (0, _("vector element must be constant"));
3305 token
.u
.index
= element
.X_add_number
;
3306 mips_add_token (&token
, OT_INTEGER_INDEX
);
3308 SKIP_SPACE_TABS (s
);
3311 set_insn_error (0, _("missing `]'"));
3321 /* First try to treat expressions as floats. */
3322 save_in
= input_line_pointer
;
3323 input_line_pointer
= s
;
3324 err
= md_atof (float_format
, (char *) token
.u
.flt
.data
,
3325 &token
.u
.flt
.length
);
3326 end
= input_line_pointer
;
3327 input_line_pointer
= save_in
;
3330 set_insn_error (0, err
);
3335 mips_add_token (&token
, OT_FLOAT
);
3340 /* Treat everything else as an integer expression. */
3341 token
.u
.integer
.relocs
[0] = BFD_RELOC_UNUSED
;
3342 token
.u
.integer
.relocs
[1] = BFD_RELOC_UNUSED
;
3343 token
.u
.integer
.relocs
[2] = BFD_RELOC_UNUSED
;
3344 my_getSmallExpression (&token
.u
.integer
.value
, token
.u
.integer
.relocs
, s
);
3346 mips_add_token (&token
, OT_INTEGER
);
3350 /* S points to the operand list for an instruction. FLOAT_FORMAT is 'f'
3351 if expressions should be treated as 32-bit floating-point constants,
3352 'd' if they should be treated as 64-bit floating-point constants,
3353 or 0 if they should be treated as integer expressions (the usual case).
3355 Return a list of tokens on success, otherwise return 0. The caller
3356 must obstack_free the list after use. */
3358 static struct mips_operand_token
*
3359 mips_parse_arguments (char *s
, char float_format
)
3361 struct mips_operand_token token
;
3363 SKIP_SPACE_TABS (s
);
3366 s
= mips_parse_argument_token (s
, float_format
);
3369 obstack_free (&mips_operand_tokens
,
3370 obstack_finish (&mips_operand_tokens
));
3373 SKIP_SPACE_TABS (s
);
3375 mips_add_token (&token
, OT_END
);
3376 return (struct mips_operand_token
*) obstack_finish (&mips_operand_tokens
);
3379 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3380 and architecture. Use is_opcode_valid_16 for MIPS16 opcodes. */
3383 is_opcode_valid (const struct mips_opcode
*mo
)
3385 int isa
= mips_opts
.isa
;
3386 int ase
= mips_opts
.ase
;
3390 if (ISA_HAS_64BIT_REGS (isa
))
3391 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3392 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3393 ase
|= mips_ases
[i
].flags64
;
3395 if (!opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
))
3398 /* Check whether the instruction or macro requires single-precision or
3399 double-precision floating-point support. Note that this information is
3400 stored differently in the opcode table for insns and macros. */
3401 if (mo
->pinfo
== INSN_MACRO
)
3403 fp_s
= mo
->pinfo2
& INSN2_M_FP_S
;
3404 fp_d
= mo
->pinfo2
& INSN2_M_FP_D
;
3408 fp_s
= mo
->pinfo
& FP_S
;
3409 fp_d
= mo
->pinfo
& FP_D
;
3412 if (fp_d
&& (mips_opts
.soft_float
|| mips_opts
.single_float
))
3415 if (fp_s
&& mips_opts
.soft_float
)
3421 /* Return TRUE if the MIPS16 opcode MO is valid on the currently
3422 selected ISA and architecture. */
3425 is_opcode_valid_16 (const struct mips_opcode
*mo
)
3427 int isa
= mips_opts
.isa
;
3428 int ase
= mips_opts
.ase
;
3431 if (ISA_HAS_64BIT_REGS (isa
))
3432 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
3433 if ((ase
& mips_ases
[i
].flags
) == mips_ases
[i
].flags
)
3434 ase
|= mips_ases
[i
].flags64
;
3436 return opcode_is_member (mo
, isa
, ase
, mips_opts
.arch
);
3439 /* Return TRUE if the size of the microMIPS opcode MO matches one
3440 explicitly requested. Always TRUE in the standard MIPS mode.
3441 Use is_size_valid_16 for MIPS16 opcodes. */
3444 is_size_valid (const struct mips_opcode
*mo
)
3446 if (!mips_opts
.micromips
)
3449 if (mips_opts
.insn32
)
3451 if (mo
->pinfo
!= INSN_MACRO
&& micromips_insn_length (mo
) != 4)
3453 if ((mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0)
3456 if (!forced_insn_length
)
3458 if (mo
->pinfo
== INSN_MACRO
)
3460 return forced_insn_length
== micromips_insn_length (mo
);
3463 /* Return TRUE if the size of the MIPS16 opcode MO matches one
3464 explicitly requested. */
3467 is_size_valid_16 (const struct mips_opcode
*mo
)
3469 if (!forced_insn_length
)
3471 if (mo
->pinfo
== INSN_MACRO
)
3473 if (forced_insn_length
== 2 && mips_opcode_32bit_p (mo
))
3475 if (forced_insn_length
== 4 && (mo
->pinfo2
& INSN2_SHORT_ONLY
))
3480 /* Return TRUE if the microMIPS opcode MO is valid for the delay slot
3481 of the preceding instruction. Always TRUE in the standard MIPS mode.
3483 We don't accept macros in 16-bit delay slots to avoid a case where
3484 a macro expansion fails because it relies on a preceding 32-bit real
3485 instruction to have matched and does not handle the operands correctly.
3486 The only macros that may expand to 16-bit instructions are JAL that
3487 cannot be placed in a delay slot anyway, and corner cases of BALIGN
3488 and BGT (that likewise cannot be placed in a delay slot) that decay to
3489 a NOP. In all these cases the macros precede any corresponding real
3490 instruction definitions in the opcode table, so they will match in the
3491 second pass where the size of the delay slot is ignored and therefore
3492 produce correct code. */
3495 is_delay_slot_valid (const struct mips_opcode
*mo
)
3497 if (!mips_opts
.micromips
)
3500 if (mo
->pinfo
== INSN_MACRO
)
3501 return (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) == 0;
3502 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
3503 && micromips_insn_length (mo
) != 4)
3505 if ((history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
3506 && micromips_insn_length (mo
) != 2)
3512 /* For consistency checking, verify that all bits of OPCODE are specified
3513 either by the match/mask part of the instruction definition, or by the
3514 operand list. Also build up a list of operands in OPERANDS.
3516 INSN_BITS says which bits of the instruction are significant.
3517 If OPCODE is a standard or microMIPS instruction, DECODE_OPERAND
3518 provides the mips_operand description of each operand. DECODE_OPERAND
3519 is null for MIPS16 instructions. */
3522 validate_mips_insn (const struct mips_opcode
*opcode
,
3523 unsigned long insn_bits
,
3524 const struct mips_operand
*(*decode_operand
) (const char *),
3525 struct mips_operand_array
*operands
)
3528 unsigned long used_bits
, doubled
, undefined
, opno
, mask
;
3529 const struct mips_operand
*operand
;
3531 mask
= (opcode
->pinfo
== INSN_MACRO
? 0 : opcode
->mask
);
3532 if ((mask
& opcode
->match
) != opcode
->match
)
3534 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
3535 opcode
->name
, opcode
->args
);
3540 if (opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
)
3541 used_bits
= mips_insert_operand (&mips_vu0_channel_mask
, used_bits
, -1);
3542 for (s
= opcode
->args
; *s
; ++s
)
3555 if (!decode_operand
)
3556 operand
= decode_mips16_operand (*s
, mips_opcode_32bit_p (opcode
));
3558 operand
= decode_operand (s
);
3559 if (!operand
&& opcode
->pinfo
!= INSN_MACRO
)
3561 as_bad (_("internal: unknown operand type: %s %s"),
3562 opcode
->name
, opcode
->args
);
3565 gas_assert (opno
< MAX_OPERANDS
);
3566 operands
->operand
[opno
] = operand
;
3567 if (!decode_operand
&& operand
3568 && operand
->type
== OP_INT
&& operand
->lsb
== 0
3569 && mips_opcode_32bit_p (opcode
))
3570 used_bits
|= mips16_immed_extend (-1, operand
->size
);
3571 else if (operand
&& operand
->type
!= OP_VU0_MATCH_SUFFIX
)
3573 used_bits
= mips_insert_operand (operand
, used_bits
, -1);
3574 if (operand
->type
== OP_MDMX_IMM_REG
)
3575 /* Bit 5 is the format selector (OB vs QH). The opcode table
3576 has separate entries for each format. */
3577 used_bits
&= ~(1 << (operand
->lsb
+ 5));
3578 if (operand
->type
== OP_ENTRY_EXIT_LIST
)
3579 used_bits
&= ~(mask
& 0x700);
3580 /* interAptiv MR2 SAVE/RESTORE instructions have a discontiguous
3581 operand field that cannot be fully described with LSB/SIZE. */
3582 if (operand
->type
== OP_SAVE_RESTORE_LIST
&& operand
->lsb
== 6)
3583 used_bits
&= ~0x6000;
3585 /* Skip prefix characters. */
3586 if (decode_operand
&& (*s
== '+' || *s
== 'm' || *s
== '-'))
3591 doubled
= used_bits
& mask
& insn_bits
;
3594 as_bad (_("internal: bad mips opcode (bits 0x%08lx doubly defined):"
3595 " %s %s"), doubled
, opcode
->name
, opcode
->args
);
3599 undefined
= ~used_bits
& insn_bits
;
3600 if (opcode
->pinfo
!= INSN_MACRO
&& undefined
)
3602 as_bad (_("internal: bad mips opcode (bits 0x%08lx undefined): %s %s"),
3603 undefined
, opcode
->name
, opcode
->args
);
3606 used_bits
&= ~insn_bits
;
3609 as_bad (_("internal: bad mips opcode (bits 0x%08lx defined): %s %s"),
3610 used_bits
, opcode
->name
, opcode
->args
);
3616 /* The MIPS16 version of validate_mips_insn. */
3619 validate_mips16_insn (const struct mips_opcode
*opcode
,
3620 struct mips_operand_array
*operands
)
3622 unsigned long insn_bits
= mips_opcode_32bit_p (opcode
) ? 0xffffffff : 0xffff;
3624 return validate_mips_insn (opcode
, insn_bits
, 0, operands
);
3627 /* The microMIPS version of validate_mips_insn. */
3630 validate_micromips_insn (const struct mips_opcode
*opc
,
3631 struct mips_operand_array
*operands
)
3633 unsigned long insn_bits
;
3634 unsigned long major
;
3635 unsigned int length
;
3637 if (opc
->pinfo
== INSN_MACRO
)
3638 return validate_mips_insn (opc
, 0xffffffff, decode_micromips_operand
,
3641 length
= micromips_insn_length (opc
);
3642 if (length
!= 2 && length
!= 4)
3644 as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
3645 "%s %s"), length
, opc
->name
, opc
->args
);
3648 major
= opc
->match
>> (10 + 8 * (length
- 2));
3649 if ((length
== 2 && (major
& 7) != 1 && (major
& 6) != 2)
3650 || (length
== 4 && (major
& 7) != 0 && (major
& 4) != 4))
3652 as_bad (_("internal error: bad microMIPS opcode "
3653 "(opcode/length mismatch): %s %s"), opc
->name
, opc
->args
);
3657 /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */
3658 insn_bits
= 1 << 4 * length
;
3659 insn_bits
<<= 4 * length
;
3661 return validate_mips_insn (opc
, insn_bits
, decode_micromips_operand
,
3665 /* This function is called once, at assembler startup time. It should set up
3666 all the tables, etc. that the MD part of the assembler will need. */
3674 if (mips_pic
!= NO_PIC
)
3676 if (g_switch_seen
&& g_switch_value
!= 0)
3677 as_bad (_("-G may not be used in position-independent code"));
3680 else if (mips_abicalls
)
3682 if (g_switch_seen
&& g_switch_value
!= 0)
3683 as_bad (_("-G may not be used with abicalls"));
3687 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
3688 as_warn (_("could not set architecture and machine"));
3690 op_hash
= str_htab_create ();
3692 mips_operands
= XCNEWVEC (struct mips_operand_array
, NUMOPCODES
);
3693 for (i
= 0; i
< NUMOPCODES
;)
3695 const char *name
= mips_opcodes
[i
].name
;
3697 if (str_hash_insert (op_hash
, name
, &mips_opcodes
[i
], 0) != NULL
)
3698 as_fatal (_("duplicate %s"), name
);
3701 if (!validate_mips_insn (&mips_opcodes
[i
], 0xffffffff,
3702 decode_mips_operand
, &mips_operands
[i
]))
3705 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3707 create_insn (&nop_insn
, mips_opcodes
+ i
);
3708 if (mips_fix_loongson2f_nop
)
3709 nop_insn
.insn_opcode
= LOONGSON2F_NOP_INSN
;
3710 nop_insn
.fixed_p
= 1;
3713 if (sync_insn
.insn_mo
== NULL
&& strcmp (name
, "sync") == 0)
3714 create_insn (&sync_insn
, mips_opcodes
+ i
);
3718 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
3721 mips16_op_hash
= str_htab_create ();
3722 mips16_operands
= XCNEWVEC (struct mips_operand_array
,
3723 bfd_mips16_num_opcodes
);
3726 while (i
< bfd_mips16_num_opcodes
)
3728 const char *name
= mips16_opcodes
[i
].name
;
3730 if (str_hash_insert (mips16_op_hash
, name
, &mips16_opcodes
[i
], 0))
3731 as_fatal (_("duplicate %s"), name
);
3734 if (!validate_mips16_insn (&mips16_opcodes
[i
], &mips16_operands
[i
]))
3736 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
3738 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
3739 mips16_nop_insn
.fixed_p
= 1;
3743 while (i
< bfd_mips16_num_opcodes
3744 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
3747 micromips_op_hash
= str_htab_create ();
3748 micromips_operands
= XCNEWVEC (struct mips_operand_array
,
3749 bfd_micromips_num_opcodes
);
3752 while (i
< bfd_micromips_num_opcodes
)
3754 const char *name
= micromips_opcodes
[i
].name
;
3756 if (str_hash_insert (micromips_op_hash
, name
, µmips_opcodes
[i
], 0))
3757 as_fatal (_("duplicate %s"), name
);
3760 struct mips_cl_insn
*micromips_nop_insn
;
3762 if (!validate_micromips_insn (µmips_opcodes
[i
],
3763 µmips_operands
[i
]))
3766 if (micromips_opcodes
[i
].pinfo
!= INSN_MACRO
)
3768 if (micromips_insn_length (micromips_opcodes
+ i
) == 2)
3769 micromips_nop_insn
= µmips_nop16_insn
;
3770 else if (micromips_insn_length (micromips_opcodes
+ i
) == 4)
3771 micromips_nop_insn
= µmips_nop32_insn
;
3775 if (micromips_nop_insn
->insn_mo
== NULL
3776 && strcmp (name
, "nop") == 0)
3778 create_insn (micromips_nop_insn
, micromips_opcodes
+ i
);
3779 micromips_nop_insn
->fixed_p
= 1;
3783 while (++i
< bfd_micromips_num_opcodes
3784 && strcmp (micromips_opcodes
[i
].name
, name
) == 0);
3788 as_fatal (_("broken assembler, no assembly attempted"));
3790 /* We add all the general register names to the symbol table. This
3791 helps us detect invalid uses of them. */
3792 for (i
= 0; reg_names
[i
].name
; i
++)
3793 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
3797 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
3798 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
3800 reg_names_n32n64
[i
].num
));
3802 for (i
= 0; reg_names_o32
[i
].name
; i
++)
3803 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
3805 reg_names_o32
[i
].num
));
3807 for (i
= 0; i
< 32; i
++)
3811 /* R5900 VU0 floating-point register. */
3812 sprintf (regname
, "$vf%d", i
);
3813 symbol_table_insert (symbol_new (regname
, reg_section
,
3814 &zero_address_frag
, RTYPE_VF
| i
));
3816 /* R5900 VU0 integer register. */
3817 sprintf (regname
, "$vi%d", i
);
3818 symbol_table_insert (symbol_new (regname
, reg_section
,
3819 &zero_address_frag
, RTYPE_VI
| i
));
3822 sprintf (regname
, "$w%d", i
);
3823 symbol_table_insert (symbol_new (regname
, reg_section
,
3824 &zero_address_frag
, RTYPE_MSA
| i
));
3827 obstack_init (&mips_operand_tokens
);
3829 mips_no_prev_insn ();
3832 mips_cprmask
[0] = 0;
3833 mips_cprmask
[1] = 0;
3834 mips_cprmask
[2] = 0;
3835 mips_cprmask
[3] = 0;
3837 /* set the default alignment for the text section (2**2) */
3838 record_alignment (text_section
, 2);
3840 bfd_set_gp_size (stdoutput
, g_switch_value
);
3842 /* On a native system other than VxWorks, sections must be aligned
3843 to 16 byte boundaries. When configured for an embedded ELF
3844 target, we don't bother. */
3845 if (strncmp (TARGET_OS
, "elf", 3) != 0
3846 && strncmp (TARGET_OS
, "vxworks", 7) != 0)
3848 bfd_set_section_alignment (text_section
, 4);
3849 bfd_set_section_alignment (data_section
, 4);
3850 bfd_set_section_alignment (bss_section
, 4);
3853 /* Create a .reginfo section for register masks and a .mdebug
3854 section for debugging information. */
3862 subseg
= now_subseg
;
3864 /* The ABI says this section should be loaded so that the
3865 running program can access it. However, we don't load it
3866 if we are configured for an embedded target. */
3867 flags
= SEC_READONLY
| SEC_DATA
;
3868 if (strncmp (TARGET_OS
, "elf", 3) != 0)
3869 flags
|= SEC_ALLOC
| SEC_LOAD
;
3871 if (mips_abi
!= N64_ABI
)
3873 sec
= subseg_new (".reginfo", (subsegT
) 0);
3875 bfd_set_section_flags (sec
, flags
);
3876 bfd_set_section_alignment (sec
, HAVE_NEWABI
? 3 : 2);
3878 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
3882 /* The 64-bit ABI uses a .MIPS.options section rather than
3883 .reginfo section. */
3884 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
3885 bfd_set_section_flags (sec
, flags
);
3886 bfd_set_section_alignment (sec
, 3);
3888 /* Set up the option header. */
3890 Elf_Internal_Options opthdr
;
3893 opthdr
.kind
= ODK_REGINFO
;
3894 opthdr
.size
= (sizeof (Elf_External_Options
)
3895 + sizeof (Elf64_External_RegInfo
));
3898 f
= frag_more (sizeof (Elf_External_Options
));
3899 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
3900 (Elf_External_Options
*) f
);
3902 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
3906 sec
= subseg_new (".MIPS.abiflags", (subsegT
) 0);
3907 bfd_set_section_flags (sec
,
3908 SEC_READONLY
| SEC_DATA
| SEC_ALLOC
| SEC_LOAD
);
3909 bfd_set_section_alignment (sec
, 3);
3910 mips_flags_frag
= frag_more (sizeof (Elf_External_ABIFlags_v0
));
3912 if (ECOFF_DEBUGGING
)
3914 sec
= subseg_new (".mdebug", (subsegT
) 0);
3915 bfd_set_section_flags (sec
, SEC_HAS_CONTENTS
| SEC_READONLY
);
3916 bfd_set_section_alignment (sec
, 2);
3918 else if (mips_flag_pdr
)
3920 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
3921 bfd_set_section_flags (pdr_seg
,
3922 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
3923 bfd_set_section_alignment (pdr_seg
, 2);
3926 subseg_set (seg
, subseg
);
3929 if (mips_fix_vr4120
)
3930 init_vr4120_conflicts ();
3934 fpabi_incompatible_with (int fpabi
, const char *what
)
3936 as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"),
3937 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3941 fpabi_requires (int fpabi
, const char *what
)
3943 as_warn (_(".gnu_attribute %d,%d requires `%s'"),
3944 Tag_GNU_MIPS_ABI_FP
, fpabi
, what
);
3947 /* Check -mabi and register sizes against the specified FP ABI. */
3949 check_fpabi (int fpabi
)
3953 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
3954 if (file_mips_opts
.soft_float
)
3955 fpabi_incompatible_with (fpabi
, "softfloat");
3956 else if (file_mips_opts
.single_float
)
3957 fpabi_incompatible_with (fpabi
, "singlefloat");
3958 if (file_mips_opts
.gp
== 64 && file_mips_opts
.fp
== 32)
3959 fpabi_incompatible_with (fpabi
, "gp=64 fp=32");
3960 else if (file_mips_opts
.gp
== 32 && file_mips_opts
.fp
== 64)
3961 fpabi_incompatible_with (fpabi
, "gp=32 fp=64");
3964 case Val_GNU_MIPS_ABI_FP_XX
:
3965 if (mips_abi
!= O32_ABI
)
3966 fpabi_requires (fpabi
, "-mabi=32");
3967 else if (file_mips_opts
.soft_float
)
3968 fpabi_incompatible_with (fpabi
, "softfloat");
3969 else if (file_mips_opts
.single_float
)
3970 fpabi_incompatible_with (fpabi
, "singlefloat");
3971 else if (file_mips_opts
.fp
!= 0)
3972 fpabi_requires (fpabi
, "fp=xx");
3975 case Val_GNU_MIPS_ABI_FP_64A
:
3976 case Val_GNU_MIPS_ABI_FP_64
:
3977 if (mips_abi
!= O32_ABI
)
3978 fpabi_requires (fpabi
, "-mabi=32");
3979 else if (file_mips_opts
.soft_float
)
3980 fpabi_incompatible_with (fpabi
, "softfloat");
3981 else if (file_mips_opts
.single_float
)
3982 fpabi_incompatible_with (fpabi
, "singlefloat");
3983 else if (file_mips_opts
.fp
!= 64)
3984 fpabi_requires (fpabi
, "fp=64");
3985 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64
&& !file_mips_opts
.oddspreg
)
3986 fpabi_incompatible_with (fpabi
, "nooddspreg");
3987 else if (fpabi
== Val_GNU_MIPS_ABI_FP_64A
&& file_mips_opts
.oddspreg
)
3988 fpabi_requires (fpabi
, "nooddspreg");
3991 case Val_GNU_MIPS_ABI_FP_SINGLE
:
3992 if (file_mips_opts
.soft_float
)
3993 fpabi_incompatible_with (fpabi
, "softfloat");
3994 else if (!file_mips_opts
.single_float
)
3995 fpabi_requires (fpabi
, "singlefloat");
3998 case Val_GNU_MIPS_ABI_FP_SOFT
:
3999 if (!file_mips_opts
.soft_float
)
4000 fpabi_requires (fpabi
, "softfloat");
4003 case Val_GNU_MIPS_ABI_FP_OLD_64
:
4004 as_warn (_(".gnu_attribute %d,%d is no longer supported"),
4005 Tag_GNU_MIPS_ABI_FP
, fpabi
);
4008 case Val_GNU_MIPS_ABI_FP_NAN2008
:
4009 /* Silently ignore compatibility value. */
4013 as_warn (_(".gnu_attribute %d,%d is not a recognized"
4014 " floating-point ABI"), Tag_GNU_MIPS_ABI_FP
, fpabi
);
4019 /* Perform consistency checks on the current options. */
4022 mips_check_options (struct mips_set_options
*opts
, bfd_boolean abi_checks
)
4024 /* Check the size of integer registers agrees with the ABI and ISA. */
4025 if (opts
->gp
== 64 && !ISA_HAS_64BIT_REGS (opts
->isa
))
4026 as_bad (_("`gp=64' used with a 32-bit processor"));
4028 && opts
->gp
== 32 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4029 as_bad (_("`gp=32' used with a 64-bit ABI"));
4031 && opts
->gp
== 64 && ABI_NEEDS_32BIT_REGS (mips_abi
))
4032 as_bad (_("`gp=64' used with a 32-bit ABI"));
4034 /* Check the size of the float registers agrees with the ABI and ISA. */
4038 if (!CPU_HAS_LDC1_SDC1 (opts
->arch
))
4039 as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions"));
4040 else if (opts
->single_float
== 1)
4041 as_bad (_("`fp=xx' cannot be used with `singlefloat'"));
4044 if (!ISA_HAS_64BIT_FPRS (opts
->isa
))
4045 as_bad (_("`fp=64' used with a 32-bit fpu"));
4047 && ABI_NEEDS_32BIT_REGS (mips_abi
)
4048 && !ISA_HAS_MXHC1 (opts
->isa
))
4049 as_warn (_("`fp=64' used with a 32-bit ABI"));
4053 && ABI_NEEDS_64BIT_REGS (mips_abi
))
4054 as_warn (_("`fp=32' used with a 64-bit ABI"));
4055 if (ISA_IS_R6 (opts
->isa
) && opts
->single_float
== 0)
4056 as_bad (_("`fp=32' used with a MIPS R6 cpu"));
4059 as_bad (_("Unknown size of floating point registers"));
4063 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !opts
->oddspreg
)
4064 as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI"));
4066 if (opts
->micromips
== 1 && opts
->mips16
== 1)
4067 as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
4068 else if (ISA_IS_R6 (opts
->isa
)
4069 && (opts
->micromips
== 1
4070 || opts
->mips16
== 1))
4071 as_fatal (_("`%s' cannot be used with `%s'"),
4072 opts
->micromips
? "micromips" : "mips16",
4073 mips_cpu_info_from_isa (opts
->isa
)->name
);
4075 if (ISA_IS_R6 (opts
->isa
) && mips_relax_branch
)
4076 as_fatal (_("branch relaxation is not supported in `%s'"),
4077 mips_cpu_info_from_isa (opts
->isa
)->name
);
4080 /* Perform consistency checks on the module level options exactly once.
4081 This is a deferred check that happens:
4082 at the first .set directive
4083 or, at the first pseudo op that generates code (inc .dc.a)
4084 or, at the first instruction
4088 file_mips_check_options (void)
4090 if (file_mips_opts_checked
)
4093 /* The following code determines the register size.
4094 Similar code was added to GCC 3.3 (see override_options() in
4095 config/mips/mips.c). The GAS and GCC code should be kept in sync
4096 as much as possible. */
4098 if (file_mips_opts
.gp
< 0)
4100 /* Infer the integer register size from the ABI and processor.
4101 Restrict ourselves to 32-bit registers if that's all the
4102 processor has, or if the ABI cannot handle 64-bit registers. */
4103 file_mips_opts
.gp
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
4104 || !ISA_HAS_64BIT_REGS (file_mips_opts
.isa
))
4108 if (file_mips_opts
.fp
< 0)
4110 /* No user specified float register size.
4111 ??? GAS treats single-float processors as though they had 64-bit
4112 float registers (although it complains when double-precision
4113 instructions are used). As things stand, saying they have 32-bit
4114 registers would lead to spurious "register must be even" messages.
4115 So here we assume float registers are never smaller than the
4117 if (file_mips_opts
.gp
== 64)
4118 /* 64-bit integer registers implies 64-bit float registers. */
4119 file_mips_opts
.fp
= 64;
4120 else if ((file_mips_opts
.ase
& FP64_ASES
)
4121 && ISA_HAS_64BIT_FPRS (file_mips_opts
.isa
))
4122 /* Handle ASEs that require 64-bit float registers, if possible. */
4123 file_mips_opts
.fp
= 64;
4124 else if (ISA_IS_R6 (mips_opts
.isa
))
4125 /* R6 implies 64-bit float registers. */
4126 file_mips_opts
.fp
= 64;
4128 /* 32-bit float registers. */
4129 file_mips_opts
.fp
= 32;
4132 /* Disable operations on odd-numbered floating-point registers by default
4133 when using the FPXX ABI. */
4134 if (file_mips_opts
.oddspreg
< 0)
4136 if (file_mips_opts
.fp
== 0)
4137 file_mips_opts
.oddspreg
= 0;
4139 file_mips_opts
.oddspreg
= 1;
4142 /* End of GCC-shared inference code. */
4144 /* This flag is set when we have a 64-bit capable CPU but use only
4145 32-bit wide registers. Note that EABI does not use it. */
4146 if (ISA_HAS_64BIT_REGS (file_mips_opts
.isa
)
4147 && ((mips_abi
== NO_ABI
&& file_mips_opts
.gp
== 32)
4148 || mips_abi
== O32_ABI
))
4151 if (file_mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
4152 as_bad (_("trap exception not supported at ISA 1"));
4154 /* If the selected architecture includes support for ASEs, enable
4155 generation of code for them. */
4156 if (file_mips_opts
.mips16
== -1)
4157 file_mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_opts
.arch
)) ? 1 : 0;
4158 if (file_mips_opts
.micromips
== -1)
4159 file_mips_opts
.micromips
= (CPU_HAS_MICROMIPS (file_mips_opts
.arch
))
4162 if (mips_nan2008
== -1)
4163 mips_nan2008
= (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
)) ? 0 : 1;
4164 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
) && mips_nan2008
== 0)
4165 as_fatal (_("`%s' does not support legacy NaN"),
4166 mips_cpu_info_from_arch (file_mips_opts
.arch
)->name
);
4168 /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from
4169 being selected implicitly. */
4170 if (file_mips_opts
.fp
!= 64)
4171 file_ase_explicit
|= ASE_MIPS3D
| ASE_MDMX
| ASE_MSA
;
4173 /* If the user didn't explicitly select or deselect a particular ASE,
4174 use the default setting for the CPU. */
4175 file_mips_opts
.ase
|= (file_mips_opts
.init_ase
& ~file_ase_explicit
);
4177 /* Set up the current options. These may change throughout assembly. */
4178 mips_opts
= file_mips_opts
;
4180 mips_check_isa_supports_ases ();
4181 mips_check_options (&file_mips_opts
, TRUE
);
4182 file_mips_opts_checked
= TRUE
;
4184 if (!bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_opts
.arch
))
4185 as_warn (_("could not set architecture and machine"));
4189 md_assemble (char *str
)
4191 struct mips_cl_insn insn
;
4192 bfd_reloc_code_real_type unused_reloc
[3]
4193 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
4195 file_mips_check_options ();
4197 imm_expr
.X_op
= O_absent
;
4198 offset_expr
.X_op
= O_absent
;
4199 offset_reloc
[0] = BFD_RELOC_UNUSED
;
4200 offset_reloc
[1] = BFD_RELOC_UNUSED
;
4201 offset_reloc
[2] = BFD_RELOC_UNUSED
;
4203 mips_mark_labels ();
4204 mips_assembling_insn
= TRUE
;
4205 clear_insn_error ();
4207 if (mips_opts
.mips16
)
4208 mips16_ip (str
, &insn
);
4211 mips_ip (str
, &insn
);
4212 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
4213 str
, insn
.insn_opcode
));
4217 report_insn_error (str
);
4218 else if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
4221 if (mips_opts
.mips16
)
4222 mips16_macro (&insn
);
4229 if (offset_expr
.X_op
!= O_absent
)
4230 append_insn (&insn
, &offset_expr
, offset_reloc
, FALSE
);
4232 append_insn (&insn
, NULL
, unused_reloc
, FALSE
);
4235 mips_assembling_insn
= FALSE
;
4238 /* Convenience functions for abstracting away the differences between
4239 MIPS16 and non-MIPS16 relocations. */
4241 static inline bfd_boolean
4242 mips16_reloc_p (bfd_reloc_code_real_type reloc
)
4246 case BFD_RELOC_MIPS16_JMP
:
4247 case BFD_RELOC_MIPS16_GPREL
:
4248 case BFD_RELOC_MIPS16_GOT16
:
4249 case BFD_RELOC_MIPS16_CALL16
:
4250 case BFD_RELOC_MIPS16_HI16_S
:
4251 case BFD_RELOC_MIPS16_HI16
:
4252 case BFD_RELOC_MIPS16_LO16
:
4253 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4261 static inline bfd_boolean
4262 micromips_reloc_p (bfd_reloc_code_real_type reloc
)
4266 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4267 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4268 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4269 case BFD_RELOC_MICROMIPS_GPREL16
:
4270 case BFD_RELOC_MICROMIPS_JMP
:
4271 case BFD_RELOC_MICROMIPS_HI16
:
4272 case BFD_RELOC_MICROMIPS_HI16_S
:
4273 case BFD_RELOC_MICROMIPS_LO16
:
4274 case BFD_RELOC_MICROMIPS_LITERAL
:
4275 case BFD_RELOC_MICROMIPS_GOT16
:
4276 case BFD_RELOC_MICROMIPS_CALL16
:
4277 case BFD_RELOC_MICROMIPS_GOT_HI16
:
4278 case BFD_RELOC_MICROMIPS_GOT_LO16
:
4279 case BFD_RELOC_MICROMIPS_CALL_HI16
:
4280 case BFD_RELOC_MICROMIPS_CALL_LO16
:
4281 case BFD_RELOC_MICROMIPS_SUB
:
4282 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
4283 case BFD_RELOC_MICROMIPS_GOT_OFST
:
4284 case BFD_RELOC_MICROMIPS_GOT_DISP
:
4285 case BFD_RELOC_MICROMIPS_HIGHEST
:
4286 case BFD_RELOC_MICROMIPS_HIGHER
:
4287 case BFD_RELOC_MICROMIPS_SCN_DISP
:
4288 case BFD_RELOC_MICROMIPS_JALR
:
4296 static inline bfd_boolean
4297 jmp_reloc_p (bfd_reloc_code_real_type reloc
)
4299 return reloc
== BFD_RELOC_MIPS_JMP
|| reloc
== BFD_RELOC_MICROMIPS_JMP
;
4302 static inline bfd_boolean
4303 b_reloc_p (bfd_reloc_code_real_type reloc
)
4305 return (reloc
== BFD_RELOC_MIPS_26_PCREL_S2
4306 || reloc
== BFD_RELOC_MIPS_21_PCREL_S2
4307 || reloc
== BFD_RELOC_16_PCREL_S2
4308 || reloc
== BFD_RELOC_MIPS16_16_PCREL_S1
4309 || reloc
== BFD_RELOC_MICROMIPS_16_PCREL_S1
4310 || reloc
== BFD_RELOC_MICROMIPS_10_PCREL_S1
4311 || reloc
== BFD_RELOC_MICROMIPS_7_PCREL_S1
);
4314 static inline bfd_boolean
4315 got16_reloc_p (bfd_reloc_code_real_type reloc
)
4317 return (reloc
== BFD_RELOC_MIPS_GOT16
|| reloc
== BFD_RELOC_MIPS16_GOT16
4318 || reloc
== BFD_RELOC_MICROMIPS_GOT16
);
4321 static inline bfd_boolean
4322 hi16_reloc_p (bfd_reloc_code_real_type reloc
)
4324 return (reloc
== BFD_RELOC_HI16_S
|| reloc
== BFD_RELOC_MIPS16_HI16_S
4325 || reloc
== BFD_RELOC_MICROMIPS_HI16_S
);
4328 static inline bfd_boolean
4329 lo16_reloc_p (bfd_reloc_code_real_type reloc
)
4331 return (reloc
== BFD_RELOC_LO16
|| reloc
== BFD_RELOC_MIPS16_LO16
4332 || reloc
== BFD_RELOC_MICROMIPS_LO16
);
4335 static inline bfd_boolean
4336 jalr_reloc_p (bfd_reloc_code_real_type reloc
)
4338 return reloc
== BFD_RELOC_MIPS_JALR
|| reloc
== BFD_RELOC_MICROMIPS_JALR
;
4341 static inline bfd_boolean
4342 gprel16_reloc_p (bfd_reloc_code_real_type reloc
)
4344 return (reloc
== BFD_RELOC_GPREL16
|| reloc
== BFD_RELOC_MIPS16_GPREL
4345 || reloc
== BFD_RELOC_MICROMIPS_GPREL16
);
4348 /* Return true if RELOC is a PC-relative relocation that does not have
4349 full address range. */
4351 static inline bfd_boolean
4352 limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc
)
4356 case BFD_RELOC_16_PCREL_S2
:
4357 case BFD_RELOC_MIPS16_16_PCREL_S1
:
4358 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
4359 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
4360 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
4361 case BFD_RELOC_MIPS_21_PCREL_S2
:
4362 case BFD_RELOC_MIPS_26_PCREL_S2
:
4363 case BFD_RELOC_MIPS_18_PCREL_S3
:
4364 case BFD_RELOC_MIPS_19_PCREL_S2
:
4367 case BFD_RELOC_32_PCREL
:
4368 case BFD_RELOC_HI16_S_PCREL
:
4369 case BFD_RELOC_LO16_PCREL
:
4370 return HAVE_64BIT_ADDRESSES
;
4377 /* Return true if the given relocation might need a matching %lo().
4378 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
4379 need a matching %lo() when applied to local symbols. */
4381 static inline bfd_boolean
4382 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
4384 return (HAVE_IN_PLACE_ADDENDS
4385 && (hi16_reloc_p (reloc
)
4386 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
4387 all GOT16 relocations evaluate to "G". */
4388 || (got16_reloc_p (reloc
) && mips_pic
!= VXWORKS_PIC
)));
4391 /* Return the type of %lo() reloc needed by RELOC, given that
4392 reloc_needs_lo_p. */
4394 static inline bfd_reloc_code_real_type
4395 matching_lo_reloc (bfd_reloc_code_real_type reloc
)
4397 return (mips16_reloc_p (reloc
) ? BFD_RELOC_MIPS16_LO16
4398 : (micromips_reloc_p (reloc
) ? BFD_RELOC_MICROMIPS_LO16
4402 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
4405 static inline bfd_boolean
4406 fixup_has_matching_lo_p (fixS
*fixp
)
4408 return (fixp
->fx_next
!= NULL
4409 && fixp
->fx_next
->fx_r_type
== matching_lo_reloc (fixp
->fx_r_type
)
4410 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
4411 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
4414 /* Move all labels in LABELS to the current insertion point. TEXT_P
4415 says whether the labels refer to text or data. */
4418 mips_move_labels (struct insn_label_list
*labels
, bfd_boolean text_p
)
4420 struct insn_label_list
*l
;
4423 for (l
= labels
; l
!= NULL
; l
= l
->next
)
4425 gas_assert (S_GET_SEGMENT (l
->label
) == now_seg
);
4426 symbol_set_frag (l
->label
, frag_now
);
4427 val
= (valueT
) frag_now_fix ();
4428 /* MIPS16/microMIPS text labels are stored as odd.
4429 We just carry the ISA mode bit forward. */
4430 if (text_p
&& HAVE_CODE_COMPRESSION
)
4431 val
|= (S_GET_VALUE (l
->label
) & 0x1);
4432 S_SET_VALUE (l
->label
, val
);
4436 /* Move all labels in insn_labels to the current insertion point
4437 and treat them as text labels. */
4440 mips_move_text_labels (void)
4442 mips_move_labels (seg_info (now_seg
)->label_list
, TRUE
);
4445 /* Duplicate the test for LINK_ONCE sections as in `adjust_reloc_syms'. */
4448 s_is_linkonce (symbolS
*sym
, segT from_seg
)
4450 bfd_boolean linkonce
= FALSE
;
4451 segT symseg
= S_GET_SEGMENT (sym
);
4453 if (symseg
!= from_seg
&& !S_IS_LOCAL (sym
))
4455 if ((bfd_section_flags (symseg
) & SEC_LINK_ONCE
))
4457 /* The GNU toolchain uses an extension for ELF: a section
4458 beginning with the magic string .gnu.linkonce is a
4459 linkonce section. */
4460 if (strncmp (segment_name (symseg
), ".gnu.linkonce",
4461 sizeof ".gnu.linkonce" - 1) == 0)
4467 /* Mark MIPS16 or microMIPS instruction label LABEL. This permits the
4468 linker to handle them specially, such as generating jalx instructions
4469 when needed. We also make them odd for the duration of the assembly,
4470 in order to generate the right sort of code. We will make them even
4471 in the adjust_symtab routine, while leaving them marked. This is
4472 convenient for the debugger and the disassembler. The linker knows
4473 to make them odd again. */
4476 mips_compressed_mark_label (symbolS
*label
)
4478 gas_assert (HAVE_CODE_COMPRESSION
);
4480 if (mips_opts
.mips16
)
4481 S_SET_OTHER (label
, ELF_ST_SET_MIPS16 (S_GET_OTHER (label
)));
4483 S_SET_OTHER (label
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (label
)));
4484 if ((S_GET_VALUE (label
) & 1) == 0
4485 /* Don't adjust the address if the label is global or weak, or
4486 in a link-once section, since we'll be emitting symbol reloc
4487 references to it which will be patched up by the linker, and
4488 the final value of the symbol may or may not be MIPS16/microMIPS. */
4489 && !S_IS_WEAK (label
)
4490 && !S_IS_EXTERNAL (label
)
4491 && !s_is_linkonce (label
, now_seg
))
4492 S_SET_VALUE (label
, S_GET_VALUE (label
) | 1);
4495 /* Mark preceding MIPS16 or microMIPS instruction labels. */
4498 mips_compressed_mark_labels (void)
4500 struct insn_label_list
*l
;
4502 for (l
= seg_info (now_seg
)->label_list
; l
!= NULL
; l
= l
->next
)
4503 mips_compressed_mark_label (l
->label
);
4506 /* End the current frag. Make it a variant frag and record the
4510 relax_close_frag (void)
4512 mips_macro_warning
.first_frag
= frag_now
;
4513 frag_var (rs_machine_dependent
, 0, 0,
4514 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1],
4515 mips_pic
!= NO_PIC
),
4516 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
4518 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
4519 mips_relax
.first_fixup
= 0;
4522 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
4523 See the comment above RELAX_ENCODE for more details. */
4526 relax_start (symbolS
*symbol
)
4528 gas_assert (mips_relax
.sequence
== 0);
4529 mips_relax
.sequence
= 1;
4530 mips_relax
.symbol
= symbol
;
4533 /* Start generating the second version of a relaxable sequence.
4534 See the comment above RELAX_ENCODE for more details. */
4539 gas_assert (mips_relax
.sequence
== 1);
4540 mips_relax
.sequence
= 2;
4543 /* End the current relaxable sequence. */
4548 gas_assert (mips_relax
.sequence
== 2);
4549 relax_close_frag ();
4550 mips_relax
.sequence
= 0;
4553 /* Return true if IP is a delayed branch or jump. */
4555 static inline bfd_boolean
4556 delayed_branch_p (const struct mips_cl_insn
*ip
)
4558 return (ip
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
4559 | INSN_COND_BRANCH_DELAY
4560 | INSN_COND_BRANCH_LIKELY
)) != 0;
4563 /* Return true if IP is a compact branch or jump. */
4565 static inline bfd_boolean
4566 compact_branch_p (const struct mips_cl_insn
*ip
)
4568 return (ip
->insn_mo
->pinfo2
& (INSN2_UNCOND_BRANCH
4569 | INSN2_COND_BRANCH
)) != 0;
4572 /* Return true if IP is an unconditional branch or jump. */
4574 static inline bfd_boolean
4575 uncond_branch_p (const struct mips_cl_insn
*ip
)
4577 return ((ip
->insn_mo
->pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0
4578 || (ip
->insn_mo
->pinfo2
& INSN2_UNCOND_BRANCH
) != 0);
4581 /* Return true if IP is a branch-likely instruction. */
4583 static inline bfd_boolean
4584 branch_likely_p (const struct mips_cl_insn
*ip
)
4586 return (ip
->insn_mo
->pinfo
& INSN_COND_BRANCH_LIKELY
) != 0;
4589 /* Return the type of nop that should be used to fill the delay slot
4590 of delayed branch IP. */
4592 static struct mips_cl_insn
*
4593 get_delay_slot_nop (const struct mips_cl_insn
*ip
)
4595 if (mips_opts
.micromips
4596 && (ip
->insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
4597 return µmips_nop32_insn
;
4601 /* Return a mask that has bit N set if OPCODE reads the register(s)
4605 insn_read_mask (const struct mips_opcode
*opcode
)
4607 return (opcode
->pinfo
& INSN_READ_ALL
) >> INSN_READ_SHIFT
;
4610 /* Return a mask that has bit N set if OPCODE writes to the register(s)
4614 insn_write_mask (const struct mips_opcode
*opcode
)
4616 return (opcode
->pinfo
& INSN_WRITE_ALL
) >> INSN_WRITE_SHIFT
;
4619 /* Return a mask of the registers specified by operand OPERAND of INSN.
4620 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4624 operand_reg_mask (const struct mips_cl_insn
*insn
,
4625 const struct mips_operand
*operand
,
4626 unsigned int type_mask
)
4628 unsigned int uval
, vsel
;
4630 switch (operand
->type
)
4637 case OP_ADDIUSP_INT
:
4638 case OP_ENTRY_EXIT_LIST
:
4639 case OP_REPEAT_DEST_REG
:
4640 case OP_REPEAT_PREV_REG
:
4643 case OP_VU0_MATCH_SUFFIX
:
4651 case OP_OPTIONAL_REG
:
4653 const struct mips_reg_operand
*reg_op
;
4655 reg_op
= (const struct mips_reg_operand
*) operand
;
4656 if (!(type_mask
& (1 << reg_op
->reg_type
)))
4658 uval
= insn_extract_operand (insn
, operand
);
4659 return 1u << mips_decode_reg_operand (reg_op
, uval
);
4664 const struct mips_reg_pair_operand
*pair_op
;
4666 pair_op
= (const struct mips_reg_pair_operand
*) operand
;
4667 if (!(type_mask
& (1 << pair_op
->reg_type
)))
4669 uval
= insn_extract_operand (insn
, operand
);
4670 return (1u << pair_op
->reg1_map
[uval
]) | (1u << pair_op
->reg2_map
[uval
]);
4673 case OP_CLO_CLZ_DEST
:
4674 if (!(type_mask
& (1 << OP_REG_GP
)))
4676 uval
= insn_extract_operand (insn
, operand
);
4677 return (1u << (uval
& 31)) | (1u << (uval
>> 5));
4680 if (!(type_mask
& (1 << OP_REG_GP
)))
4682 uval
= insn_extract_operand (insn
, operand
);
4683 gas_assert ((uval
& 31) == (uval
>> 5));
4684 return 1u << (uval
& 31);
4687 case OP_NON_ZERO_REG
:
4688 if (!(type_mask
& (1 << OP_REG_GP
)))
4690 uval
= insn_extract_operand (insn
, operand
);
4691 return 1u << (uval
& 31);
4693 case OP_LWM_SWM_LIST
:
4696 case OP_SAVE_RESTORE_LIST
:
4699 case OP_MDMX_IMM_REG
:
4700 if (!(type_mask
& (1 << OP_REG_VEC
)))
4702 uval
= insn_extract_operand (insn
, operand
);
4704 if ((vsel
& 0x18) == 0x18)
4706 return 1u << (uval
& 31);
4709 if (!(type_mask
& (1 << OP_REG_GP
)))
4711 return 1u << insn_extract_operand (insn
, operand
);
4716 /* Return a mask of the registers specified by operands OPNO_MASK of INSN,
4717 where bit N of OPNO_MASK is set if operand N should be included.
4718 Ignore registers of type OP_REG_<t> unless bit OP_REG_<t> of TYPE_MASK
4722 insn_reg_mask (const struct mips_cl_insn
*insn
,
4723 unsigned int type_mask
, unsigned int opno_mask
)
4725 unsigned int opno
, reg_mask
;
4729 while (opno_mask
!= 0)
4732 reg_mask
|= operand_reg_mask (insn
, insn_opno (insn
, opno
), type_mask
);
4739 /* Return the mask of core registers that IP reads. */
4742 gpr_read_mask (const struct mips_cl_insn
*ip
)
4744 unsigned long pinfo
, pinfo2
;
4747 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_read_mask (ip
->insn_mo
));
4748 pinfo
= ip
->insn_mo
->pinfo
;
4749 pinfo2
= ip
->insn_mo
->pinfo2
;
4750 if (pinfo
& INSN_UDI
)
4752 /* UDI instructions have traditionally been assumed to read RS
4754 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RT
, *ip
);
4755 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RS
, *ip
);
4757 if (pinfo
& INSN_READ_GPR_24
)
4759 if (pinfo2
& INSN2_READ_GPR_16
)
4761 if (pinfo2
& INSN2_READ_SP
)
4763 if (pinfo2
& INSN2_READ_GPR_31
)
4765 /* Don't include register 0. */
4769 /* Return the mask of core registers that IP writes. */
4772 gpr_write_mask (const struct mips_cl_insn
*ip
)
4774 unsigned long pinfo
, pinfo2
;
4777 mask
= insn_reg_mask (ip
, 1 << OP_REG_GP
, insn_write_mask (ip
->insn_mo
));
4778 pinfo
= ip
->insn_mo
->pinfo
;
4779 pinfo2
= ip
->insn_mo
->pinfo2
;
4780 if (pinfo
& INSN_WRITE_GPR_24
)
4782 if (pinfo
& INSN_WRITE_GPR_31
)
4784 if (pinfo
& INSN_UDI
)
4785 /* UDI instructions have traditionally been assumed to write to RD. */
4786 mask
|= 1 << EXTRACT_OPERAND (mips_opts
.micromips
, RD
, *ip
);
4787 if (pinfo2
& INSN2_WRITE_SP
)
4789 /* Don't include register 0. */
4793 /* Return the mask of floating-point registers that IP reads. */
4796 fpr_read_mask (const struct mips_cl_insn
*ip
)
4798 unsigned long pinfo
;
4801 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4802 | (1 << OP_REG_MSA
)),
4803 insn_read_mask (ip
->insn_mo
));
4804 pinfo
= ip
->insn_mo
->pinfo
;
4805 /* Conservatively treat all operands to an FP_D instruction are doubles.
4806 (This is overly pessimistic for things like cvt.d.s.) */
4807 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4812 /* Return the mask of floating-point registers that IP writes. */
4815 fpr_write_mask (const struct mips_cl_insn
*ip
)
4817 unsigned long pinfo
;
4820 mask
= insn_reg_mask (ip
, ((1 << OP_REG_FP
) | (1 << OP_REG_VEC
)
4821 | (1 << OP_REG_MSA
)),
4822 insn_write_mask (ip
->insn_mo
));
4823 pinfo
= ip
->insn_mo
->pinfo
;
4824 /* Conservatively treat all operands to an FP_D instruction are doubles.
4825 (This is overly pessimistic for things like cvt.s.d.) */
4826 if (FPR_SIZE
!= 64 && (pinfo
& FP_D
))
4831 /* Operand OPNUM of INSN is an odd-numbered floating-point register.
4832 Check whether that is allowed. */
4835 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int opnum
)
4837 const char *s
= insn
->name
;
4838 bfd_boolean oddspreg
= (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
, mips_opts
.arch
)
4840 && mips_opts
.oddspreg
;
4842 if (insn
->pinfo
== INSN_MACRO
)
4843 /* Let a macro pass, we'll catch it later when it is expanded. */
4846 /* Single-precision coprocessor loads and moves are OK for 32-bit registers,
4847 otherwise it depends on oddspreg. */
4848 if ((insn
->pinfo
& FP_S
)
4849 && (insn
->pinfo
& (INSN_LOAD_MEMORY
| INSN_STORE_MEMORY
4850 | INSN_LOAD_COPROC
| INSN_COPROC_MOVE
)))
4851 return FPR_SIZE
== 32 || oddspreg
;
4853 /* Allow odd registers for single-precision ops and double-precision if the
4854 floating-point registers are 64-bit wide. */
4855 switch (insn
->pinfo
& (FP_S
| FP_D
))
4861 return FPR_SIZE
== 64;
4866 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
4867 s
= strchr (insn
->name
, '.');
4868 if (s
!= NULL
&& opnum
== 2)
4869 s
= strchr (s
+ 1, '.');
4870 if (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'))
4873 return FPR_SIZE
== 64;
4876 /* Information about an instruction argument that we're trying to match. */
4877 struct mips_arg_info
4879 /* The instruction so far. */
4880 struct mips_cl_insn
*insn
;
4882 /* The first unconsumed operand token. */
4883 struct mips_operand_token
*token
;
4885 /* The 1-based operand number, in terms of insn->insn_mo->args. */
4888 /* The 1-based argument number, for error reporting. This does not
4889 count elided optional registers, etc.. */
4892 /* The last OP_REG operand seen, or ILLEGAL_REG if none. */
4893 unsigned int last_regno
;
4895 /* If the first operand was an OP_REG, this is the register that it
4896 specified, otherwise it is ILLEGAL_REG. */
4897 unsigned int dest_regno
;
4899 /* The value of the last OP_INT operand. Only used for OP_MSB,
4900 where it gives the lsb position. */
4901 unsigned int last_op_int
;
4903 /* If true, match routines should assume that no later instruction
4904 alternative matches and should therefore be as accommodating as
4905 possible. Match routines should not report errors if something
4906 is only invalid for !LAX_MATCH. */
4907 bfd_boolean lax_match
;
4909 /* True if a reference to the current AT register was seen. */
4910 bfd_boolean seen_at
;
4913 /* Record that the argument is out of range. */
4916 match_out_of_range (struct mips_arg_info
*arg
)
4918 set_insn_error_i (arg
->argnum
, _("operand %d out of range"), arg
->argnum
);
4921 /* Record that the argument isn't constant but needs to be. */
4924 match_not_constant (struct mips_arg_info
*arg
)
4926 set_insn_error_i (arg
->argnum
, _("operand %d must be constant"),
4930 /* Try to match an OT_CHAR token for character CH. Consume the token
4931 and return true on success, otherwise return false. */
4934 match_char (struct mips_arg_info
*arg
, char ch
)
4936 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== ch
)
4946 /* Try to get an expression from the next tokens in ARG. Consume the
4947 tokens and return true on success, storing the expression value in
4948 VALUE and relocation types in R. */
4951 match_expression (struct mips_arg_info
*arg
, expressionS
*value
,
4952 bfd_reloc_code_real_type
*r
)
4954 /* If the next token is a '(' that was parsed as being part of a base
4955 expression, assume we have an elided offset. The later match will fail
4956 if this turns out to be wrong. */
4957 if (arg
->token
->type
== OT_CHAR
&& arg
->token
->u
.ch
== '(')
4959 value
->X_op
= O_constant
;
4960 value
->X_add_number
= 0;
4961 r
[0] = r
[1] = r
[2] = BFD_RELOC_UNUSED
;
4965 /* Reject register-based expressions such as "0+$2" and "(($2))".
4966 For plain registers the default error seems more appropriate. */
4967 if (arg
->token
->type
== OT_INTEGER
4968 && arg
->token
->u
.integer
.value
.X_op
== O_register
)
4970 set_insn_error (arg
->argnum
, _("register value used as expression"));
4974 if (arg
->token
->type
== OT_INTEGER
)
4976 *value
= arg
->token
->u
.integer
.value
;
4977 memcpy (r
, arg
->token
->u
.integer
.relocs
, 3 * sizeof (*r
));
4983 (arg
->argnum
, _("operand %d must be an immediate expression"),
4988 /* Try to get a constant expression from the next tokens in ARG. Consume
4989 the tokens and return true on success, storing the constant value
4993 match_const_int (struct mips_arg_info
*arg
, offsetT
*value
)
4996 bfd_reloc_code_real_type r
[3];
4998 if (!match_expression (arg
, &ex
, r
))
5001 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_constant
)
5002 *value
= ex
.X_add_number
;
5005 if (r
[0] == BFD_RELOC_UNUSED
&& ex
.X_op
== O_big
)
5006 match_out_of_range (arg
);
5008 match_not_constant (arg
);
5014 /* Return the RTYPE_* flags for a register operand of type TYPE that
5015 appears in instruction OPCODE. */
5018 convert_reg_type (const struct mips_opcode
*opcode
,
5019 enum mips_reg_operand_type type
)
5024 return RTYPE_NUM
| RTYPE_GP
;
5027 /* Allow vector register names for MDMX if the instruction is a 64-bit
5028 FPR load, store or move (including moves to and from GPRs). */
5029 if ((mips_opts
.ase
& ASE_MDMX
)
5030 && (opcode
->pinfo
& FP_D
)
5031 && (opcode
->pinfo
& (INSN_COPROC_MOVE
5032 | INSN_COPROC_MEMORY_DELAY
5035 | INSN_STORE_MEMORY
)))
5036 return RTYPE_FPU
| RTYPE_VEC
;
5040 if (opcode
->pinfo
& (FP_D
| FP_S
))
5041 return RTYPE_CCC
| RTYPE_FCC
;
5045 if (opcode
->membership
& INSN_5400
)
5047 return RTYPE_FPU
| RTYPE_VEC
;
5053 if (opcode
->name
[strlen (opcode
->name
) - 1] == '0')
5054 return RTYPE_NUM
| RTYPE_CP0
;
5061 return RTYPE_NUM
| RTYPE_VI
;
5064 return RTYPE_NUM
| RTYPE_VF
;
5066 case OP_REG_R5900_I
:
5067 return RTYPE_R5900_I
;
5069 case OP_REG_R5900_Q
:
5070 return RTYPE_R5900_Q
;
5072 case OP_REG_R5900_R
:
5073 return RTYPE_R5900_R
;
5075 case OP_REG_R5900_ACC
:
5076 return RTYPE_R5900_ACC
;
5081 case OP_REG_MSA_CTRL
:
5087 /* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */
5090 check_regno (struct mips_arg_info
*arg
,
5091 enum mips_reg_operand_type type
, unsigned int regno
)
5093 if (AT
&& type
== OP_REG_GP
&& regno
== AT
)
5094 arg
->seen_at
= TRUE
;
5096 if (type
== OP_REG_FP
5098 && !mips_oddfpreg_ok (arg
->insn
->insn_mo
, arg
->opnum
))
5100 /* This was a warning prior to introducing O32 FPXX and FP64 support
5101 so maintain a warning for FP32 but raise an error for the new
5104 as_warn (_("float register should be even, was %d"), regno
);
5106 as_bad (_("float register should be even, was %d"), regno
);
5109 if (type
== OP_REG_CCC
)
5114 name
= arg
->insn
->insn_mo
->name
;
5115 length
= strlen (name
);
5116 if ((regno
& 1) != 0
5117 && ((length
>= 3 && strcmp (name
+ length
- 3, ".ps") == 0)
5118 || (length
>= 5 && strncmp (name
+ length
- 5, "any2", 4) == 0)))
5119 as_warn (_("condition code register should be even for %s, was %d"),
5122 if ((regno
& 3) != 0
5123 && (length
>= 5 && strncmp (name
+ length
- 5, "any4", 4) == 0))
5124 as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
5129 /* ARG is a register with symbol value SYMVAL. Try to interpret it as
5130 a register of type TYPE. Return true on success, storing the register
5131 number in *REGNO and warning about any dubious uses. */
5134 match_regno (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5135 unsigned int symval
, unsigned int *regno
)
5137 if (type
== OP_REG_VEC
)
5138 symval
= mips_prefer_vec_regno (symval
);
5139 if (!(symval
& convert_reg_type (arg
->insn
->insn_mo
, type
)))
5142 *regno
= symval
& RNUM_MASK
;
5143 check_regno (arg
, type
, *regno
);
5147 /* Try to interpret the next token in ARG as a register of type TYPE.
5148 Consume the token and return true on success, storing the register
5149 number in *REGNO. Return false on failure. */
5152 match_reg (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5153 unsigned int *regno
)
5155 if (arg
->token
->type
== OT_REG
5156 && match_regno (arg
, type
, arg
->token
->u
.regno
, regno
))
5164 /* Try to interpret the next token in ARG as a range of registers of type TYPE.
5165 Consume the token and return true on success, storing the register numbers
5166 in *REGNO1 and *REGNO2. Return false on failure. */
5169 match_reg_range (struct mips_arg_info
*arg
, enum mips_reg_operand_type type
,
5170 unsigned int *regno1
, unsigned int *regno2
)
5172 if (match_reg (arg
, type
, regno1
))
5177 if (arg
->token
->type
== OT_REG_RANGE
5178 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno1
, regno1
)
5179 && match_regno (arg
, type
, arg
->token
->u
.reg_range
.regno2
, regno2
)
5180 && *regno1
<= *regno2
)
5188 /* OP_INT matcher. */
5191 match_int_operand (struct mips_arg_info
*arg
,
5192 const struct mips_operand
*operand_base
)
5194 const struct mips_int_operand
*operand
;
5196 int min_val
, max_val
, factor
;
5199 operand
= (const struct mips_int_operand
*) operand_base
;
5200 factor
= 1 << operand
->shift
;
5201 min_val
= mips_int_operand_min (operand
);
5202 max_val
= mips_int_operand_max (operand
);
5204 if (operand_base
->lsb
== 0
5205 && operand_base
->size
== 16
5206 && operand
->shift
== 0
5207 && operand
->bias
== 0
5208 && (operand
->max_val
== 32767 || operand
->max_val
== 65535))
5210 /* The operand can be relocated. */
5211 if (!match_expression (arg
, &offset_expr
, offset_reloc
))
5214 if (offset_expr
.X_op
== O_big
)
5216 match_out_of_range (arg
);
5220 if (offset_reloc
[0] != BFD_RELOC_UNUSED
)
5221 /* Relocation operators were used. Accept the argument and
5222 leave the relocation value in offset_expr and offset_relocs
5223 for the caller to process. */
5226 if (offset_expr
.X_op
!= O_constant
)
5228 /* Accept non-constant operands if no later alternative matches,
5229 leaving it for the caller to process. */
5230 if (!arg
->lax_match
)
5232 match_not_constant (arg
);
5235 offset_reloc
[0] = BFD_RELOC_LO16
;
5239 /* Clear the global state; we're going to install the operand
5241 sval
= offset_expr
.X_add_number
;
5242 offset_expr
.X_op
= O_absent
;
5244 /* For compatibility with older assemblers, we accept
5245 0x8000-0xffff as signed 16-bit numbers when only
5246 signed numbers are allowed. */
5249 max_val
= ((1 << operand_base
->size
) - 1) << operand
->shift
;
5250 if (!arg
->lax_match
&& sval
<= max_val
)
5252 match_out_of_range (arg
);
5259 if (!match_const_int (arg
, &sval
))
5263 arg
->last_op_int
= sval
;
5265 if (sval
< min_val
|| sval
> max_val
|| sval
% factor
)
5267 match_out_of_range (arg
);
5271 uval
= (unsigned int) sval
>> operand
->shift
;
5272 uval
-= operand
->bias
;
5274 /* Handle -mfix-cn63xxp1. */
5276 && mips_fix_cn63xxp1
5277 && !mips_opts
.micromips
5278 && strcmp ("pref", arg
->insn
->insn_mo
->name
) == 0)
5293 /* The rest must be changed to 28. */
5298 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5302 /* OP_MAPPED_INT matcher. */
5305 match_mapped_int_operand (struct mips_arg_info
*arg
,
5306 const struct mips_operand
*operand_base
)
5308 const struct mips_mapped_int_operand
*operand
;
5309 unsigned int uval
, num_vals
;
5312 operand
= (const struct mips_mapped_int_operand
*) operand_base
;
5313 if (!match_const_int (arg
, &sval
))
5316 num_vals
= 1 << operand_base
->size
;
5317 for (uval
= 0; uval
< num_vals
; uval
++)
5318 if (operand
->int_map
[uval
] == sval
)
5320 if (uval
== num_vals
)
5322 match_out_of_range (arg
);
5326 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5330 /* OP_MSB matcher. */
5333 match_msb_operand (struct mips_arg_info
*arg
,
5334 const struct mips_operand
*operand_base
)
5336 const struct mips_msb_operand
*operand
;
5337 int min_val
, max_val
, max_high
;
5338 offsetT size
, sval
, high
;
5340 operand
= (const struct mips_msb_operand
*) operand_base
;
5341 min_val
= operand
->bias
;
5342 max_val
= min_val
+ (1 << operand_base
->size
) - 1;
5343 max_high
= operand
->opsize
;
5345 if (!match_const_int (arg
, &size
))
5348 high
= size
+ arg
->last_op_int
;
5349 sval
= operand
->add_lsb
? high
: size
;
5351 if (size
< 0 || high
> max_high
|| sval
< min_val
|| sval
> max_val
)
5353 match_out_of_range (arg
);
5356 insn_insert_operand (arg
->insn
, operand_base
, sval
- min_val
);
5360 /* OP_REG matcher. */
5363 match_reg_operand (struct mips_arg_info
*arg
,
5364 const struct mips_operand
*operand_base
)
5366 const struct mips_reg_operand
*operand
;
5367 unsigned int regno
, uval
, num_vals
;
5369 operand
= (const struct mips_reg_operand
*) operand_base
;
5370 if (!match_reg (arg
, operand
->reg_type
, ®no
))
5373 if (operand
->reg_map
)
5375 num_vals
= 1 << operand
->root
.size
;
5376 for (uval
= 0; uval
< num_vals
; uval
++)
5377 if (operand
->reg_map
[uval
] == regno
)
5379 if (num_vals
== uval
)
5385 arg
->last_regno
= regno
;
5386 if (arg
->opnum
== 1)
5387 arg
->dest_regno
= regno
;
5388 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5392 /* OP_REG_PAIR matcher. */
5395 match_reg_pair_operand (struct mips_arg_info
*arg
,
5396 const struct mips_operand
*operand_base
)
5398 const struct mips_reg_pair_operand
*operand
;
5399 unsigned int regno1
, regno2
, uval
, num_vals
;
5401 operand
= (const struct mips_reg_pair_operand
*) operand_base
;
5402 if (!match_reg (arg
, operand
->reg_type
, ®no1
)
5403 || !match_char (arg
, ',')
5404 || !match_reg (arg
, operand
->reg_type
, ®no2
))
5407 num_vals
= 1 << operand_base
->size
;
5408 for (uval
= 0; uval
< num_vals
; uval
++)
5409 if (operand
->reg1_map
[uval
] == regno1
&& operand
->reg2_map
[uval
] == regno2
)
5411 if (uval
== num_vals
)
5414 insn_insert_operand (arg
->insn
, operand_base
, uval
);
5418 /* OP_PCREL matcher. The caller chooses the relocation type. */
5421 match_pcrel_operand (struct mips_arg_info
*arg
)
5423 bfd_reloc_code_real_type r
[3];
5425 return match_expression (arg
, &offset_expr
, r
) && r
[0] == BFD_RELOC_UNUSED
;
5428 /* OP_PERF_REG matcher. */
5431 match_perf_reg_operand (struct mips_arg_info
*arg
,
5432 const struct mips_operand
*operand
)
5436 if (!match_const_int (arg
, &sval
))
5441 || (mips_opts
.arch
== CPU_R5900
5442 && (strcmp (arg
->insn
->insn_mo
->name
, "mfps") == 0
5443 || strcmp (arg
->insn
->insn_mo
->name
, "mtps") == 0))))
5445 set_insn_error (arg
->argnum
, _("invalid performance register"));
5449 insn_insert_operand (arg
->insn
, operand
, sval
);
5453 /* OP_ADDIUSP matcher. */
5456 match_addiusp_operand (struct mips_arg_info
*arg
,
5457 const struct mips_operand
*operand
)
5462 if (!match_const_int (arg
, &sval
))
5467 match_out_of_range (arg
);
5472 if (!(sval
>= -258 && sval
<= 257) || (sval
>= -2 && sval
<= 1))
5474 match_out_of_range (arg
);
5478 uval
= (unsigned int) sval
;
5479 uval
= ((uval
>> 1) & ~0xff) | (uval
& 0xff);
5480 insn_insert_operand (arg
->insn
, operand
, uval
);
5484 /* OP_CLO_CLZ_DEST matcher. */
5487 match_clo_clz_dest_operand (struct mips_arg_info
*arg
,
5488 const struct mips_operand
*operand
)
5492 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5495 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5499 /* OP_CHECK_PREV matcher. */
5502 match_check_prev_operand (struct mips_arg_info
*arg
,
5503 const struct mips_operand
*operand_base
)
5505 const struct mips_check_prev_operand
*operand
;
5508 operand
= (const struct mips_check_prev_operand
*) operand_base
;
5510 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5513 if (!operand
->zero_ok
&& regno
== 0)
5516 if ((operand
->less_than_ok
&& regno
< arg
->last_regno
)
5517 || (operand
->greater_than_ok
&& regno
> arg
->last_regno
)
5518 || (operand
->equal_ok
&& regno
== arg
->last_regno
))
5520 arg
->last_regno
= regno
;
5521 insn_insert_operand (arg
->insn
, operand_base
, regno
);
5528 /* OP_SAME_RS_RT matcher. */
5531 match_same_rs_rt_operand (struct mips_arg_info
*arg
,
5532 const struct mips_operand
*operand
)
5536 if (!match_reg (arg
, OP_REG_GP
, ®no
))
5541 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
5545 arg
->last_regno
= regno
;
5547 insn_insert_operand (arg
->insn
, operand
, regno
| (regno
<< 5));
5551 /* OP_LWM_SWM_LIST matcher. */
5554 match_lwm_swm_list_operand (struct mips_arg_info
*arg
,
5555 const struct mips_operand
*operand
)
5557 unsigned int reglist
, sregs
, ra
, regno1
, regno2
;
5558 struct mips_arg_info reset
;
5561 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5565 if (regno2
== FP
&& regno1
>= S0
&& regno1
<= S7
)
5570 reglist
|= ((1U << regno2
<< 1) - 1) & -(1U << regno1
);
5573 while (match_char (arg
, ',')
5574 && match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
));
5577 if (operand
->size
== 2)
5579 /* The list must include both ra and s0-sN, for 0 <= N <= 3. E.g.:
5585 and any permutations of these. */
5586 if ((reglist
& 0xfff1ffff) != 0x80010000)
5589 sregs
= (reglist
>> 17) & 7;
5594 /* The list must include at least one of ra and s0-sN,
5595 for 0 <= N <= 8. (Note that there is a gap between s7 and s8,
5596 which are $23 and $30 respectively.) E.g.:
5604 and any permutations of these. */
5605 if ((reglist
& 0x3f00ffff) != 0)
5608 ra
= (reglist
>> 27) & 0x10;
5609 sregs
= ((reglist
>> 22) & 0x100) | ((reglist
>> 16) & 0xff);
5612 if ((sregs
& -sregs
) != sregs
)
5615 insn_insert_operand (arg
->insn
, operand
, (ffs (sregs
) - 1) | ra
);
5619 /* OP_ENTRY_EXIT_LIST matcher. */
5622 match_entry_exit_operand (struct mips_arg_info
*arg
,
5623 const struct mips_operand
*operand
)
5626 bfd_boolean is_exit
;
5628 /* The format is the same for both ENTRY and EXIT, but the constraints
5630 is_exit
= strcmp (arg
->insn
->insn_mo
->name
, "exit") == 0;
5631 mask
= (is_exit
? 7 << 3 : 0);
5634 unsigned int regno1
, regno2
;
5635 bfd_boolean is_freg
;
5637 if (match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5639 else if (match_reg_range (arg
, OP_REG_FP
, ®no1
, ®no2
))
5644 if (is_exit
&& is_freg
&& regno1
== 0 && regno2
< 2)
5647 mask
|= (5 + regno2
) << 3;
5649 else if (!is_exit
&& regno1
== 4 && regno2
>= 4 && regno2
<= 7)
5650 mask
|= (regno2
- 3) << 3;
5651 else if (regno1
== 16 && regno2
>= 16 && regno2
<= 17)
5652 mask
|= (regno2
- 15) << 1;
5653 else if (regno1
== RA
&& regno2
== RA
)
5658 while (match_char (arg
, ','));
5660 insn_insert_operand (arg
->insn
, operand
, mask
);
5664 /* Encode regular MIPS SAVE/RESTORE instruction operands according to
5665 the argument register mask AMASK, the number of static registers
5666 saved NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5667 respectively, and the frame size FRAME_SIZE. */
5670 mips_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5671 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5672 unsigned int frame_size
)
5674 return ((nsreg
<< 23) | ((frame_size
& 0xf0) << 15) | (amask
<< 15)
5675 | (ra
<< 12) | (s0
<< 11) | (s1
<< 10) | ((frame_size
& 0xf) << 6));
5678 /* Encode MIPS16 SAVE/RESTORE instruction operands according to the
5679 argument register mask AMASK, the number of static registers saved
5680 NSREG, the $ra, $s0 and $s1 register specifiers RA, S0 and S1
5681 respectively, and the frame size FRAME_SIZE. */
5684 mips16_encode_save_restore (unsigned int amask
, unsigned int nsreg
,
5685 unsigned int ra
, unsigned int s0
, unsigned int s1
,
5686 unsigned int frame_size
)
5690 args
= (ra
<< 6) | (s0
<< 5) | (s1
<< 4) | (frame_size
& 0xf);
5691 if (nsreg
|| amask
|| frame_size
== 0 || frame_size
> 16)
5692 args
|= (MIPS16_EXTEND
| (nsreg
<< 24) | (amask
<< 16)
5693 | ((frame_size
& 0xf0) << 16));
5697 /* OP_SAVE_RESTORE_LIST matcher. */
5700 match_save_restore_list_operand (struct mips_arg_info
*arg
)
5702 unsigned int opcode
, args
, statics
, sregs
;
5703 unsigned int num_frame_sizes
, num_args
, num_statics
, num_sregs
;
5704 unsigned int arg_mask
, ra
, s0
, s1
;
5707 opcode
= arg
->insn
->insn_opcode
;
5709 num_frame_sizes
= 0;
5718 unsigned int regno1
, regno2
;
5720 if (arg
->token
->type
== OT_INTEGER
)
5722 /* Handle the frame size. */
5723 if (!match_const_int (arg
, &frame_size
))
5725 num_frame_sizes
+= 1;
5729 if (!match_reg_range (arg
, OP_REG_GP
, ®no1
, ®no2
))
5732 while (regno1
<= regno2
)
5734 if (regno1
>= 4 && regno1
<= 7)
5736 if (num_frame_sizes
== 0)
5738 args
|= 1 << (regno1
- 4);
5740 /* statics $a0-$a3 */
5741 statics
|= 1 << (regno1
- 4);
5743 else if (regno1
>= 16 && regno1
<= 23)
5745 sregs
|= 1 << (regno1
- 16);
5746 else if (regno1
== 30)
5749 else if (regno1
== 31)
5750 /* Add $ra to insn. */
5760 while (match_char (arg
, ','));
5762 /* Encode args/statics combination. */
5765 else if (args
== 0xf)
5766 /* All $a0-$a3 are args. */
5767 arg_mask
= MIPS_SVRS_ALL_ARGS
;
5768 else if (statics
== 0xf)
5769 /* All $a0-$a3 are statics. */
5770 arg_mask
= MIPS_SVRS_ALL_STATICS
;
5773 /* Count arg registers. */
5783 /* Count static registers. */
5785 while (statics
& 0x8)
5787 statics
= (statics
<< 1) & 0xf;
5793 /* Encode args/statics. */
5794 arg_mask
= (num_args
<< 2) | num_statics
;
5797 /* Encode $s0/$s1. */
5798 if (sregs
& (1 << 0)) /* $s0 */
5800 if (sregs
& (1 << 1)) /* $s1 */
5804 /* Encode $s2-$s8. */
5814 /* Encode frame size. */
5815 if (num_frame_sizes
== 0)
5817 set_insn_error (arg
->argnum
, _("missing frame size"));
5820 if (num_frame_sizes
> 1)
5822 set_insn_error (arg
->argnum
, _("frame size specified twice"));
5825 if ((frame_size
& 7) != 0 || frame_size
< 0 || frame_size
> 0xff * 8)
5827 set_insn_error (arg
->argnum
, _("invalid frame size"));
5832 /* Finally build the instruction. */
5833 if (mips_opts
.mips16
)
5834 opcode
|= mips16_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5836 else if (!mips_opts
.micromips
)
5837 opcode
|= mips_encode_save_restore (arg_mask
, num_sregs
, ra
, s0
, s1
,
5842 arg
->insn
->insn_opcode
= opcode
;
5846 /* OP_MDMX_IMM_REG matcher. */
5849 match_mdmx_imm_reg_operand (struct mips_arg_info
*arg
,
5850 const struct mips_operand
*operand
)
5852 unsigned int regno
, uval
;
5854 const struct mips_opcode
*opcode
;
5856 /* The mips_opcode records whether this is an octobyte or quadhalf
5857 instruction. Start out with that bit in place. */
5858 opcode
= arg
->insn
->insn_mo
;
5859 uval
= mips_extract_operand (operand
, opcode
->match
);
5860 is_qh
= (uval
!= 0);
5862 if (arg
->token
->type
== OT_REG
)
5864 if ((opcode
->membership
& INSN_5400
)
5865 && strcmp (opcode
->name
, "rzu.ob") == 0)
5867 set_insn_error_i (arg
->argnum
, _("operand %d must be an immediate"),
5872 if (!match_regno (arg
, OP_REG_VEC
, arg
->token
->u
.regno
, ®no
))
5876 /* Check whether this is a vector register or a broadcast of
5877 a single element. */
5878 if (arg
->token
->type
== OT_INTEGER_INDEX
)
5880 if (arg
->token
->u
.index
> (is_qh
? 3 : 7))
5882 set_insn_error (arg
->argnum
, _("invalid element selector"));
5885 uval
|= arg
->token
->u
.index
<< (is_qh
? 2 : 1) << 5;
5890 /* A full vector. */
5891 if ((opcode
->membership
& INSN_5400
)
5892 && (strcmp (opcode
->name
, "sll.ob") == 0
5893 || strcmp (opcode
->name
, "srl.ob") == 0))
5895 set_insn_error_i (arg
->argnum
, _("operand %d must be scalar"),
5901 uval
|= MDMX_FMTSEL_VEC_QH
<< 5;
5903 uval
|= MDMX_FMTSEL_VEC_OB
<< 5;
5911 if (!match_const_int (arg
, &sval
))
5913 if (sval
< 0 || sval
> 31)
5915 match_out_of_range (arg
);
5918 uval
|= (sval
& 31);
5920 uval
|= MDMX_FMTSEL_IMM_QH
<< 5;
5922 uval
|= MDMX_FMTSEL_IMM_OB
<< 5;
5924 insn_insert_operand (arg
->insn
, operand
, uval
);
5928 /* OP_IMM_INDEX matcher. */
5931 match_imm_index_operand (struct mips_arg_info
*arg
,
5932 const struct mips_operand
*operand
)
5934 unsigned int max_val
;
5936 if (arg
->token
->type
!= OT_INTEGER_INDEX
)
5939 max_val
= (1 << operand
->size
) - 1;
5940 if (arg
->token
->u
.index
> max_val
)
5942 match_out_of_range (arg
);
5945 insn_insert_operand (arg
->insn
, operand
, arg
->token
->u
.index
);
5950 /* OP_REG_INDEX matcher. */
5953 match_reg_index_operand (struct mips_arg_info
*arg
,
5954 const struct mips_operand
*operand
)
5958 if (arg
->token
->type
!= OT_REG_INDEX
)
5961 if (!match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
))
5964 insn_insert_operand (arg
->insn
, operand
, regno
);
5969 /* OP_PC matcher. */
5972 match_pc_operand (struct mips_arg_info
*arg
)
5974 if (arg
->token
->type
== OT_REG
&& (arg
->token
->u
.regno
& RTYPE_PC
))
5982 /* OP_REG28 matcher. */
5985 match_reg28_operand (struct mips_arg_info
*arg
)
5989 if (arg
->token
->type
== OT_REG
5990 && match_regno (arg
, OP_REG_GP
, arg
->token
->u
.regno
, ®no
)
5999 /* OP_NON_ZERO_REG matcher. */
6002 match_non_zero_reg_operand (struct mips_arg_info
*arg
,
6003 const struct mips_operand
*operand
)
6007 if (!match_reg (arg
, OP_REG_GP
, ®no
))
6012 set_insn_error (arg
->argnum
, _("the source register must not be $0"));
6016 arg
->last_regno
= regno
;
6017 insn_insert_operand (arg
->insn
, operand
, regno
);
6021 /* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the
6022 register that we need to match. */
6025 match_tied_reg_operand (struct mips_arg_info
*arg
, unsigned int other_regno
)
6029 return match_reg (arg
, OP_REG_GP
, ®no
) && regno
== other_regno
;
6032 /* Try to match a floating-point constant from ARG for LI.S or LI.D.
6033 LENGTH is the length of the value in bytes (4 for float, 8 for double)
6034 and USING_GPRS says whether the destination is a GPR rather than an FPR.
6036 Return the constant in IMM and OFFSET as follows:
6038 - If the constant should be loaded via memory, set IMM to O_absent and
6039 OFFSET to the memory address.
6041 - Otherwise, if the constant should be loaded into two 32-bit registers,
6042 set IMM to the O_constant to load into the high register and OFFSET
6043 to the corresponding value for the low register.
6045 - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent.
6047 These constants only appear as the last operand in an instruction,
6048 and every instruction that accepts them in any variant accepts them
6049 in all variants. This means we don't have to worry about backing out
6050 any changes if the instruction does not match. We just match
6051 unconditionally and report an error if the constant is invalid. */
6054 match_float_constant (struct mips_arg_info
*arg
, expressionS
*imm
,
6055 expressionS
*offset
, int length
, bfd_boolean using_gprs
)
6060 const char *newname
;
6061 unsigned char *data
;
6063 /* Where the constant is placed is based on how the MIPS assembler
6066 length == 4 && using_gprs -- immediate value only
6067 length == 8 && using_gprs -- .rdata or immediate value
6068 length == 4 && !using_gprs -- .lit4 or immediate value
6069 length == 8 && !using_gprs -- .lit8 or immediate value
6071 The .lit4 and .lit8 sections are only used if permitted by the
6073 if (arg
->token
->type
!= OT_FLOAT
)
6075 set_insn_error (arg
->argnum
, _("floating-point expression required"));
6079 gas_assert (arg
->token
->u
.flt
.length
== length
);
6080 data
= arg
->token
->u
.flt
.data
;
6083 /* Handle 32-bit constants for which an immediate value is best. */
6086 || g_switch_value
< 4
6087 || (data
[0] == 0 && data
[1] == 0)
6088 || (data
[2] == 0 && data
[3] == 0)))
6090 imm
->X_op
= O_constant
;
6091 if (!target_big_endian
)
6092 imm
->X_add_number
= bfd_getl32 (data
);
6094 imm
->X_add_number
= bfd_getb32 (data
);
6095 offset
->X_op
= O_absent
;
6099 /* Handle 64-bit constants for which an immediate value is best. */
6101 && !mips_disable_float_construction
6102 /* Constants can only be constructed in GPRs and copied to FPRs if the
6103 GPRs are at least as wide as the FPRs or MTHC1 is available.
6104 Unlike most tests for 32-bit floating-point registers this check
6105 specifically looks for GPR_SIZE == 32 as the FPXX ABI does not
6106 permit 64-bit moves without MXHC1.
6107 Force the constant into memory otherwise. */
6110 || ISA_HAS_MXHC1 (mips_opts
.isa
)
6112 && ((data
[0] == 0 && data
[1] == 0)
6113 || (data
[2] == 0 && data
[3] == 0))
6114 && ((data
[4] == 0 && data
[5] == 0)
6115 || (data
[6] == 0 && data
[7] == 0)))
6117 /* The value is simple enough to load with a couple of instructions.
6118 If using 32-bit registers, set IMM to the high order 32 bits and
6119 OFFSET to the low order 32 bits. Otherwise, set IMM to the entire
6121 if (GPR_SIZE
== 32 || (!using_gprs
&& FPR_SIZE
!= 64))
6123 imm
->X_op
= O_constant
;
6124 offset
->X_op
= O_constant
;
6125 if (!target_big_endian
)
6127 imm
->X_add_number
= bfd_getl32 (data
+ 4);
6128 offset
->X_add_number
= bfd_getl32 (data
);
6132 imm
->X_add_number
= bfd_getb32 (data
);
6133 offset
->X_add_number
= bfd_getb32 (data
+ 4);
6135 if (offset
->X_add_number
== 0)
6136 offset
->X_op
= O_absent
;
6140 imm
->X_op
= O_constant
;
6141 if (!target_big_endian
)
6142 imm
->X_add_number
= bfd_getl64 (data
);
6144 imm
->X_add_number
= bfd_getb64 (data
);
6145 offset
->X_op
= O_absent
;
6150 /* Switch to the right section. */
6152 subseg
= now_subseg
;
6155 gas_assert (!using_gprs
&& g_switch_value
>= 4);
6160 if (using_gprs
|| g_switch_value
< 8)
6161 newname
= RDATA_SECTION_NAME
;
6166 new_seg
= subseg_new (newname
, (subsegT
) 0);
6167 bfd_set_section_flags (new_seg
,
6168 SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
| SEC_DATA
);
6169 frag_align (length
== 4 ? 2 : 3, 0, 0);
6170 if (strncmp (TARGET_OS
, "elf", 3) != 0)
6171 record_alignment (new_seg
, 4);
6173 record_alignment (new_seg
, length
== 4 ? 2 : 3);
6175 as_bad (_("cannot use `%s' in this section"), arg
->insn
->insn_mo
->name
);
6177 /* Set the argument to the current address in the section. */
6178 imm
->X_op
= O_absent
;
6179 offset
->X_op
= O_symbol
;
6180 offset
->X_add_symbol
= symbol_temp_new_now ();
6181 offset
->X_add_number
= 0;
6183 /* Put the floating point number into the section. */
6184 p
= frag_more (length
);
6185 memcpy (p
, data
, length
);
6187 /* Switch back to the original section. */
6188 subseg_set (seg
, subseg
);
6192 /* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
6196 match_vu0_suffix_operand (struct mips_arg_info
*arg
,
6197 const struct mips_operand
*operand
,
6198 bfd_boolean match_p
)
6202 /* The operand can be an XYZW mask or a single 2-bit channel index
6203 (with X being 0). */
6204 gas_assert (operand
->size
== 2 || operand
->size
== 4);
6206 /* The suffix can be omitted when it is already part of the opcode. */
6207 if (arg
->token
->type
!= OT_CHANNELS
)
6210 uval
= arg
->token
->u
.channels
;
6211 if (operand
->size
== 2)
6213 /* Check that a single bit is set and convert it into a 2-bit index. */
6214 if ((uval
& -uval
) != uval
)
6216 uval
= 4 - ffs (uval
);
6219 if (match_p
&& insn_extract_operand (arg
->insn
, operand
) != uval
)
6224 insn_insert_operand (arg
->insn
, operand
, uval
);
6228 /* Try to match a token from ARG against OPERAND. Consume the token
6229 and return true on success, otherwise return false. */
6232 match_operand (struct mips_arg_info
*arg
,
6233 const struct mips_operand
*operand
)
6235 switch (operand
->type
)
6238 return match_int_operand (arg
, operand
);
6241 return match_mapped_int_operand (arg
, operand
);
6244 return match_msb_operand (arg
, operand
);
6247 case OP_OPTIONAL_REG
:
6248 return match_reg_operand (arg
, operand
);
6251 return match_reg_pair_operand (arg
, operand
);
6254 return match_pcrel_operand (arg
);
6257 return match_perf_reg_operand (arg
, operand
);
6259 case OP_ADDIUSP_INT
:
6260 return match_addiusp_operand (arg
, operand
);
6262 case OP_CLO_CLZ_DEST
:
6263 return match_clo_clz_dest_operand (arg
, operand
);
6265 case OP_LWM_SWM_LIST
:
6266 return match_lwm_swm_list_operand (arg
, operand
);
6268 case OP_ENTRY_EXIT_LIST
:
6269 return match_entry_exit_operand (arg
, operand
);
6271 case OP_SAVE_RESTORE_LIST
:
6272 return match_save_restore_list_operand (arg
);
6274 case OP_MDMX_IMM_REG
:
6275 return match_mdmx_imm_reg_operand (arg
, operand
);
6277 case OP_REPEAT_DEST_REG
:
6278 return match_tied_reg_operand (arg
, arg
->dest_regno
);
6280 case OP_REPEAT_PREV_REG
:
6281 return match_tied_reg_operand (arg
, arg
->last_regno
);
6284 return match_pc_operand (arg
);
6287 return match_reg28_operand (arg
);
6290 return match_vu0_suffix_operand (arg
, operand
, FALSE
);
6292 case OP_VU0_MATCH_SUFFIX
:
6293 return match_vu0_suffix_operand (arg
, operand
, TRUE
);
6296 return match_imm_index_operand (arg
, operand
);
6299 return match_reg_index_operand (arg
, operand
);
6302 return match_same_rs_rt_operand (arg
, operand
);
6305 return match_check_prev_operand (arg
, operand
);
6307 case OP_NON_ZERO_REG
:
6308 return match_non_zero_reg_operand (arg
, operand
);
6313 /* ARG is the state after successfully matching an instruction.
6314 Issue any queued-up warnings. */
6317 check_completed_insn (struct mips_arg_info
*arg
)
6322 as_warn (_("used $at without \".set noat\""));
6324 as_warn (_("used $%u with \".set at=$%u\""), AT
, AT
);
6328 /* Return true if modifying general-purpose register REG needs a delay. */
6331 reg_needs_delay (unsigned int reg
)
6333 unsigned long prev_pinfo
;
6335 prev_pinfo
= history
[0].insn_mo
->pinfo
;
6336 if (!mips_opts
.noreorder
6337 && (((prev_pinfo
& INSN_LOAD_MEMORY
) && !gpr_interlocks
)
6338 || ((prev_pinfo
& INSN_LOAD_COPROC
) && !cop_interlocks
))
6339 && (gpr_write_mask (&history
[0]) & (1 << reg
)))
6345 /* Classify an instruction according to the FIX_VR4120_* enumeration.
6346 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
6347 by VR4120 errata. */
6350 classify_vr4120_insn (const char *name
)
6352 if (strncmp (name
, "macc", 4) == 0)
6353 return FIX_VR4120_MACC
;
6354 if (strncmp (name
, "dmacc", 5) == 0)
6355 return FIX_VR4120_DMACC
;
6356 if (strncmp (name
, "mult", 4) == 0)
6357 return FIX_VR4120_MULT
;
6358 if (strncmp (name
, "dmult", 5) == 0)
6359 return FIX_VR4120_DMULT
;
6360 if (strstr (name
, "div"))
6361 return FIX_VR4120_DIV
;
6362 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
6363 return FIX_VR4120_MTHILO
;
6364 return NUM_FIX_VR4120_CLASSES
;
6367 #define INSN_ERET 0x42000018
6368 #define INSN_DERET 0x4200001f
6369 #define INSN_DMULT 0x1c
6370 #define INSN_DMULTU 0x1d
6372 /* Return the number of instructions that must separate INSN1 and INSN2,
6373 where INSN1 is the earlier instruction. Return the worst-case value
6374 for any INSN2 if INSN2 is null. */
6377 insns_between (const struct mips_cl_insn
*insn1
,
6378 const struct mips_cl_insn
*insn2
)
6380 unsigned long pinfo1
, pinfo2
;
6383 /* If INFO2 is null, pessimistically assume that all flags are set for
6384 the second instruction. */
6385 pinfo1
= insn1
->insn_mo
->pinfo
;
6386 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
6388 /* For most targets, write-after-read dependencies on the HI and LO
6389 registers must be separated by at least two instructions. */
6390 if (!hilo_interlocks
)
6392 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
6394 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
6398 /* If we're working around r7000 errata, there must be two instructions
6399 between an mfhi or mflo and any instruction that uses the result. */
6400 if (mips_7000_hilo_fix
6401 && !mips_opts
.micromips
6402 && MF_HILO_INSN (pinfo1
)
6403 && (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
))))
6406 /* If we're working around 24K errata, one instruction is required
6407 if an ERET or DERET is followed by a branch instruction. */
6408 if (mips_fix_24k
&& !mips_opts
.micromips
)
6410 if (insn1
->insn_opcode
== INSN_ERET
6411 || insn1
->insn_opcode
== INSN_DERET
)
6414 || insn2
->insn_opcode
== INSN_ERET
6415 || insn2
->insn_opcode
== INSN_DERET
6416 || delayed_branch_p (insn2
))
6421 /* If we're working around PMC RM7000 errata, there must be three
6422 nops between a dmult and a load instruction. */
6423 if (mips_fix_rm7000
&& !mips_opts
.micromips
)
6425 if ((insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULT
6426 || (insn1
->insn_opcode
& insn1
->insn_mo
->mask
) == INSN_DMULTU
)
6428 if (pinfo2
& INSN_LOAD_MEMORY
)
6433 /* If working around VR4120 errata, check for combinations that need
6434 a single intervening instruction. */
6435 if (mips_fix_vr4120
&& !mips_opts
.micromips
)
6437 unsigned int class1
, class2
;
6439 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
6440 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
6444 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
6445 if (vr4120_conflicts
[class1
] & (1 << class2
))
6450 if (!HAVE_CODE_COMPRESSION
)
6452 /* Check for GPR or coprocessor load delays. All such delays
6453 are on the RT register. */
6454 /* Itbl support may require additional care here. */
6455 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY
))
6456 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC
)))
6458 if (insn2
== NULL
|| (gpr_read_mask (insn2
) & gpr_write_mask (insn1
)))
6462 /* Check for generic coprocessor hazards.
6464 This case is not handled very well. There is no special
6465 knowledge of CP0 handling, and the coprocessors other than
6466 the floating point unit are not distinguished at all. */
6467 /* Itbl support may require additional care here. FIXME!
6468 Need to modify this to include knowledge about
6469 user specified delays! */
6470 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE
))
6471 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
6473 /* Handle cases where INSN1 writes to a known general coprocessor
6474 register. There must be a one instruction delay before INSN2
6475 if INSN2 reads that register, otherwise no delay is needed. */
6476 mask
= fpr_write_mask (insn1
);
6479 if (!insn2
|| (mask
& fpr_read_mask (insn2
)) != 0)
6484 /* Read-after-write dependencies on the control registers
6485 require a two-instruction gap. */
6486 if ((pinfo1
& INSN_WRITE_COND_CODE
)
6487 && (pinfo2
& INSN_READ_COND_CODE
))
6490 /* We don't know exactly what INSN1 does. If INSN2 is
6491 also a coprocessor instruction, assume there must be
6492 a one instruction gap. */
6493 if (pinfo2
& INSN_COP
)
6498 /* Check for read-after-write dependencies on the coprocessor
6499 control registers in cases where INSN1 does not need a general
6500 coprocessor delay. This means that INSN1 is a floating point
6501 comparison instruction. */
6502 /* Itbl support may require additional care here. */
6503 else if (!cop_interlocks
6504 && (pinfo1
& INSN_WRITE_COND_CODE
)
6505 && (pinfo2
& INSN_READ_COND_CODE
))
6509 /* Forbidden slots can not contain Control Transfer Instructions (CTIs)
6510 CTIs include all branches and jumps, nal, eret, eretnc, deret, wait
6512 if ((insn1
->insn_mo
->pinfo2
& INSN2_FORBIDDEN_SLOT
)
6513 && ((pinfo2
& INSN_NO_DELAY_SLOT
)
6514 || (insn2
&& delayed_branch_p (insn2
))))
6520 /* Return the number of nops that would be needed to work around the
6521 VR4130 mflo/mfhi errata if instruction INSN immediately followed
6522 the MAX_VR4130_NOPS instructions described by HIST. Ignore hazards
6523 that are contained within the first IGNORE instructions of HIST. */
6526 nops_for_vr4130 (int ignore
, const struct mips_cl_insn
*hist
,
6527 const struct mips_cl_insn
*insn
)
6532 /* Check if the instruction writes to HI or LO. MTHI and MTLO
6533 are not affected by the errata. */
6535 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
6536 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
6537 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
6540 /* Search for the first MFLO or MFHI. */
6541 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
6542 if (MF_HILO_INSN (hist
[i
].insn_mo
->pinfo
))
6544 /* Extract the destination register. */
6545 mask
= gpr_write_mask (&hist
[i
]);
6547 /* No nops are needed if INSN reads that register. */
6548 if (insn
!= NULL
&& (gpr_read_mask (insn
) & mask
) != 0)
6551 /* ...or if any of the intervening instructions do. */
6552 for (j
= 0; j
< i
; j
++)
6553 if (gpr_read_mask (&hist
[j
]) & mask
)
6557 return MAX_VR4130_NOPS
- i
;
6562 #define BASE_REG_EQ(INSN1, INSN2) \
6563 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
6564 == (((INSN2) >> OP_SH_RS) & OP_MASK_RS))
6566 /* Return the minimum alignment for this store instruction. */
6569 fix_24k_align_to (const struct mips_opcode
*mo
)
6571 if (strcmp (mo
->name
, "sh") == 0)
6574 if (strcmp (mo
->name
, "swc1") == 0
6575 || strcmp (mo
->name
, "swc2") == 0
6576 || strcmp (mo
->name
, "sw") == 0
6577 || strcmp (mo
->name
, "sc") == 0
6578 || strcmp (mo
->name
, "s.s") == 0)
6581 if (strcmp (mo
->name
, "sdc1") == 0
6582 || strcmp (mo
->name
, "sdc2") == 0
6583 || strcmp (mo
->name
, "s.d") == 0)
6590 struct fix_24k_store_info
6592 /* Immediate offset, if any, for this store instruction. */
6594 /* Alignment required by this store instruction. */
6596 /* True for register offsets. */
6597 int register_offset
;
6600 /* Comparison function used by qsort. */
6603 fix_24k_sort (const void *a
, const void *b
)
6605 const struct fix_24k_store_info
*pos1
= a
;
6606 const struct fix_24k_store_info
*pos2
= b
;
6608 return (pos1
->off
- pos2
->off
);
6611 /* INSN is a store instruction. Try to record the store information
6612 in STINFO. Return false if the information isn't known. */
6615 fix_24k_record_store_info (struct fix_24k_store_info
*stinfo
,
6616 const struct mips_cl_insn
*insn
)
6618 /* The instruction must have a known offset. */
6619 if (!insn
->complete_p
|| !strstr (insn
->insn_mo
->args
, "o("))
6622 stinfo
->off
= (insn
->insn_opcode
>> OP_SH_IMMEDIATE
) & OP_MASK_IMMEDIATE
;
6623 stinfo
->align_to
= fix_24k_align_to (insn
->insn_mo
);
6627 /* Return the number of nops that would be needed to work around the 24k
6628 "lost data on stores during refill" errata if instruction INSN
6629 immediately followed the 2 instructions described by HIST.
6630 Ignore hazards that are contained within the first IGNORE
6631 instructions of HIST.
6633 Problem: The FSB (fetch store buffer) acts as an intermediate buffer
6634 for the data cache refills and store data. The following describes
6635 the scenario where the store data could be lost.
6637 * A data cache miss, due to either a load or a store, causing fill
6638 data to be supplied by the memory subsystem
6639 * The first three doublewords of fill data are returned and written
6641 * A sequence of four stores occurs in consecutive cycles around the
6642 final doubleword of the fill:
6646 * Zero, One or more instructions
6649 The four stores A-D must be to different doublewords of the line that
6650 is being filled. The fourth instruction in the sequence above permits
6651 the fill of the final doubleword to be transferred from the FSB into
6652 the cache. In the sequence above, the stores may be either integer
6653 (sb, sh, sw, swr, swl, sc) or coprocessor (swc1/swc2, sdc1/sdc2,
6654 swxc1, sdxc1, suxc1) stores, as long as the four stores are to
6655 different doublewords on the line. If the floating point unit is
6656 running in 1:2 mode, it is not possible to create the sequence above
6657 using only floating point store instructions.
6659 In this case, the cache line being filled is incorrectly marked
6660 invalid, thereby losing the data from any store to the line that
6661 occurs between the original miss and the completion of the five
6662 cycle sequence shown above.
6664 The workarounds are:
6666 * Run the data cache in write-through mode.
6667 * Insert a non-store instruction between
6668 Store A and Store B or Store B and Store C. */
6671 nops_for_24k (int ignore
, const struct mips_cl_insn
*hist
,
6672 const struct mips_cl_insn
*insn
)
6674 struct fix_24k_store_info pos
[3];
6675 int align
, i
, base_offset
;
6680 /* If the previous instruction wasn't a store, there's nothing to
6682 if ((hist
[0].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6685 /* If the instructions after the previous one are unknown, we have
6686 to assume the worst. */
6690 /* Check whether we are dealing with three consecutive stores. */
6691 if ((insn
->insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0
6692 || (hist
[1].insn_mo
->pinfo
& INSN_STORE_MEMORY
) == 0)
6695 /* If we don't know the relationship between the store addresses,
6696 assume the worst. */
6697 if (!BASE_REG_EQ (insn
->insn_opcode
, hist
[0].insn_opcode
)
6698 || !BASE_REG_EQ (insn
->insn_opcode
, hist
[1].insn_opcode
))
6701 if (!fix_24k_record_store_info (&pos
[0], insn
)
6702 || !fix_24k_record_store_info (&pos
[1], &hist
[0])
6703 || !fix_24k_record_store_info (&pos
[2], &hist
[1]))
6706 qsort (&pos
, 3, sizeof (struct fix_24k_store_info
), fix_24k_sort
);
6708 /* Pick a value of ALIGN and X such that all offsets are adjusted by
6709 X bytes and such that the base register + X is known to be aligned
6712 if (((insn
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == SP
)
6716 align
= pos
[0].align_to
;
6717 base_offset
= pos
[0].off
;
6718 for (i
= 1; i
< 3; i
++)
6719 if (align
< pos
[i
].align_to
)
6721 align
= pos
[i
].align_to
;
6722 base_offset
= pos
[i
].off
;
6724 for (i
= 0; i
< 3; i
++)
6725 pos
[i
].off
-= base_offset
;
6728 pos
[0].off
&= ~align
+ 1;
6729 pos
[1].off
&= ~align
+ 1;
6730 pos
[2].off
&= ~align
+ 1;
6732 /* If any two stores write to the same chunk, they also write to the
6733 same doubleword. The offsets are still sorted at this point. */
6734 if (pos
[0].off
== pos
[1].off
|| pos
[1].off
== pos
[2].off
)
6737 /* A range of at least 9 bytes is needed for the stores to be in
6738 non-overlapping doublewords. */
6739 if (pos
[2].off
- pos
[0].off
<= 8)
6742 if (pos
[2].off
- pos
[1].off
>= 24
6743 || pos
[1].off
- pos
[0].off
>= 24
6744 || pos
[2].off
- pos
[0].off
>= 32)
6750 /* Return the number of nops that would be needed if instruction INSN
6751 immediately followed the MAX_NOPS instructions given by HIST,
6752 where HIST[0] is the most recent instruction. Ignore hazards
6753 between INSN and the first IGNORE instructions in HIST.
6755 If INSN is null, return the worse-case number of nops for any
6759 nops_for_insn (int ignore
, const struct mips_cl_insn
*hist
,
6760 const struct mips_cl_insn
*insn
)
6762 int i
, nops
, tmp_nops
;
6765 for (i
= ignore
; i
< MAX_DELAY_NOPS
; i
++)
6767 tmp_nops
= insns_between (hist
+ i
, insn
) - i
;
6768 if (tmp_nops
> nops
)
6772 if (mips_fix_vr4130
&& !mips_opts
.micromips
)
6774 tmp_nops
= nops_for_vr4130 (ignore
, hist
, insn
);
6775 if (tmp_nops
> nops
)
6779 if (mips_fix_24k
&& !mips_opts
.micromips
)
6781 tmp_nops
= nops_for_24k (ignore
, hist
, insn
);
6782 if (tmp_nops
> nops
)
6789 /* The variable arguments provide NUM_INSNS extra instructions that
6790 might be added to HIST. Return the largest number of nops that
6791 would be needed after the extended sequence, ignoring hazards
6792 in the first IGNORE instructions. */
6795 nops_for_sequence (int num_insns
, int ignore
,
6796 const struct mips_cl_insn
*hist
, ...)
6799 struct mips_cl_insn buffer
[MAX_NOPS
];
6800 struct mips_cl_insn
*cursor
;
6803 va_start (args
, hist
);
6804 cursor
= buffer
+ num_insns
;
6805 memcpy (cursor
, hist
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
6806 while (cursor
> buffer
)
6807 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
6809 nops
= nops_for_insn (ignore
, buffer
, NULL
);
6814 /* Like nops_for_insn, but if INSN is a branch, take into account the
6815 worst-case delay for the branch target. */
6818 nops_for_insn_or_target (int ignore
, const struct mips_cl_insn
*hist
,
6819 const struct mips_cl_insn
*insn
)
6823 nops
= nops_for_insn (ignore
, hist
, insn
);
6824 if (delayed_branch_p (insn
))
6826 tmp_nops
= nops_for_sequence (2, ignore
? ignore
+ 2 : 0,
6827 hist
, insn
, get_delay_slot_nop (insn
));
6828 if (tmp_nops
> nops
)
6831 else if (compact_branch_p (insn
))
6833 tmp_nops
= nops_for_sequence (1, ignore
? ignore
+ 1 : 0, hist
, insn
);
6834 if (tmp_nops
> nops
)
6840 /* Fix NOP issue: Replace nops by "or at,at,zero". */
6843 fix_loongson2f_nop (struct mips_cl_insn
* ip
)
6845 gas_assert (!HAVE_CODE_COMPRESSION
);
6846 if (strcmp (ip
->insn_mo
->name
, "nop") == 0)
6847 ip
->insn_opcode
= LOONGSON2F_NOP_INSN
;
6850 /* Fix Jump Issue: Eliminate instruction fetch from outside 256M region
6851 jr target pc &= 'hffff_ffff_cfff_ffff. */
6854 fix_loongson2f_jump (struct mips_cl_insn
* ip
)
6856 gas_assert (!HAVE_CODE_COMPRESSION
);
6857 if (strcmp (ip
->insn_mo
->name
, "j") == 0
6858 || strcmp (ip
->insn_mo
->name
, "jr") == 0
6859 || strcmp (ip
->insn_mo
->name
, "jalr") == 0)
6867 sreg
= EXTRACT_OPERAND (0, RS
, *ip
);
6868 if (sreg
== ZERO
|| sreg
== KT0
|| sreg
== KT1
|| sreg
== ATREG
)
6871 ep
.X_op
= O_constant
;
6872 ep
.X_add_number
= 0xcfff0000;
6873 macro_build (&ep
, "lui", "t,u", ATREG
, BFD_RELOC_HI16
);
6874 ep
.X_add_number
= 0xffff;
6875 macro_build (&ep
, "ori", "t,r,i", ATREG
, ATREG
, BFD_RELOC_LO16
);
6876 macro_build (NULL
, "and", "d,v,t", sreg
, sreg
, ATREG
);
6881 fix_loongson2f (struct mips_cl_insn
* ip
)
6883 if (mips_fix_loongson2f_nop
)
6884 fix_loongson2f_nop (ip
);
6886 if (mips_fix_loongson2f_jump
)
6887 fix_loongson2f_jump (ip
);
6891 has_label_name (const char *arr
[], size_t len
,const char *s
)
6894 for (i
= 0; i
< len
; i
++)
6898 if (streq (arr
[i
], s
))
6904 /* Fix loongson3 llsc errata: Insert sync before ll/lld. */
6907 fix_loongson3_llsc (struct mips_cl_insn
* ip
)
6909 gas_assert (!HAVE_CODE_COMPRESSION
);
6911 /* If is an local label and the insn is not sync,
6912 look forward that whether an branch between ll/sc jump to here
6913 if so, insert a sync. */
6914 if (seg_info (now_seg
)->label_list
6915 && S_IS_LOCAL (seg_info (now_seg
)->label_list
->label
)
6916 && (strcmp (ip
->insn_mo
->name
, "sync") != 0))
6920 const char *label_names
[MAX_LABELS_SAME
];
6921 const char *label_name
;
6923 label_name
= S_GET_NAME (seg_info (now_seg
)->label_list
->label
);
6924 label_names
[0] = label_name
;
6925 struct insn_label_list
*llist
= seg_info (now_seg
)->label_list
;
6926 label_value
= S_GET_VALUE (llist
->label
);
6928 for (i
= 1; i
< MAX_LABELS_SAME
; i
++)
6930 llist
= llist
->next
;
6933 if (S_GET_VALUE (llist
->label
) == label_value
)
6934 label_names
[i
] = S_GET_NAME (llist
->label
);
6938 for (; i
< MAX_LABELS_SAME
; i
++)
6939 label_names
[i
] = NULL
;
6941 unsigned long lookback
= ARRAY_SIZE (history
);
6942 for (i
= 0; i
< lookback
; i
++)
6944 if (streq (history
[i
].insn_mo
->name
, "ll")
6945 || streq (history
[i
].insn_mo
->name
, "lld"))
6948 if (streq (history
[i
].insn_mo
->name
, "sc")
6949 || streq (history
[i
].insn_mo
->name
, "scd"))
6953 for (j
= i
+ 1; j
< lookback
; j
++)
6955 if (streq (history
[i
].insn_mo
->name
, "ll")
6956 || streq (history
[i
].insn_mo
->name
, "lld"))
6959 if (delayed_branch_p (&history
[j
]))
6961 if (has_label_name (label_names
,
6965 add_fixed_insn (&sync_insn
);
6966 insert_into_history (0, 1, &sync_insn
);
6975 /* If we find a sc, we look forward to look for an branch insn,
6976 and see whether it jump back and out of ll/sc. */
6977 else if (streq (ip
->insn_mo
->name
, "sc") || streq (ip
->insn_mo
->name
, "scd"))
6979 unsigned long lookback
= ARRAY_SIZE (history
) - 1;
6982 for (i
= 0; i
< lookback
; i
++)
6984 if (streq (history
[i
].insn_mo
->name
, "ll")
6985 || streq (history
[i
].insn_mo
->name
, "lld"))
6988 if (delayed_branch_p (&history
[i
]))
6992 for (j
= i
+ 1; j
< lookback
; j
++)
6994 if (streq (history
[j
].insn_mo
->name
, "ll")
6995 || streq (history
[i
].insn_mo
->name
, "lld"))
6999 for (; j
< lookback
; j
++)
7001 if (history
[j
].label
[0] != '\0'
7002 && streq (history
[j
].label
, history
[i
].target
)
7003 && strcmp (history
[j
+1].insn_mo
->name
, "sync") != 0)
7005 add_fixed_insn (&sync_insn
);
7006 insert_into_history (++j
, 1, &sync_insn
);
7013 /* Skip if there is a sync before ll/lld. */
7014 if ((strcmp (ip
->insn_mo
->name
, "ll") == 0
7015 || strcmp (ip
->insn_mo
->name
, "lld") == 0)
7016 && (strcmp (history
[0].insn_mo
->name
, "sync") != 0))
7018 add_fixed_insn (&sync_insn
);
7019 insert_into_history (0, 1, &sync_insn
);
7023 /* IP is a branch that has a delay slot, and we need to fill it
7024 automatically. Return true if we can do that by swapping IP
7025 with the previous instruction.
7026 ADDRESS_EXPR is an operand of the instruction to be used with
7030 can_swap_branch_p (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7031 bfd_reloc_code_real_type
*reloc_type
)
7033 unsigned long pinfo
, pinfo2
, prev_pinfo
, prev_pinfo2
;
7034 unsigned int gpr_read
, gpr_write
, prev_gpr_read
, prev_gpr_write
;
7035 unsigned int fpr_read
, prev_fpr_write
;
7037 /* -O2 and above is required for this optimization. */
7038 if (mips_optimize
< 2)
7041 /* If we have seen .set volatile or .set nomove, don't optimize. */
7042 if (mips_opts
.nomove
)
7045 /* We can't swap if the previous instruction's position is fixed. */
7046 if (history
[0].fixed_p
)
7049 /* If the previous previous insn was in a .set noreorder, we can't
7050 swap. Actually, the MIPS assembler will swap in this situation.
7051 However, gcc configured -with-gnu-as will generate code like
7059 in which we can not swap the bne and INSN. If gcc is not configured
7060 -with-gnu-as, it does not output the .set pseudo-ops. */
7061 if (history
[1].noreorder_p
)
7064 /* If the previous instruction had a fixup in mips16 mode, we can not swap.
7065 This means that the previous instruction was a 4-byte one anyhow. */
7066 if (mips_opts
.mips16
&& history
[0].fixp
[0])
7069 /* If the branch is itself the target of a branch, we can not swap.
7070 We cheat on this; all we check for is whether there is a label on
7071 this instruction. If there are any branches to anything other than
7072 a label, users must use .set noreorder. */
7073 if (seg_info (now_seg
)->label_list
)
7076 /* If the previous instruction is in a variant frag other than this
7077 branch's one, we cannot do the swap. This does not apply to
7078 MIPS16 code, which uses variant frags for different purposes. */
7079 if (!mips_opts
.mips16
7081 && history
[0].frag
->fr_type
== rs_machine_dependent
)
7084 /* We do not swap with instructions that cannot architecturally
7085 be placed in a branch delay slot, such as SYNC or ERET. We
7086 also refrain from swapping with a trap instruction, since it
7087 complicates trap handlers to have the trap instruction be in
7089 prev_pinfo
= history
[0].insn_mo
->pinfo
;
7090 if (prev_pinfo
& INSN_NO_DELAY_SLOT
)
7093 /* Check for conflicts between the branch and the instructions
7094 before the candidate delay slot. */
7095 if (nops_for_insn (0, history
+ 1, ip
) > 0)
7098 /* Check for conflicts between the swapped sequence and the
7099 target of the branch. */
7100 if (nops_for_sequence (2, 0, history
+ 1, ip
, history
) > 0)
7103 /* If the branch reads a register that the previous
7104 instruction sets, we can not swap. */
7105 gpr_read
= gpr_read_mask (ip
);
7106 prev_gpr_write
= gpr_write_mask (&history
[0]);
7107 if (gpr_read
& prev_gpr_write
)
7110 fpr_read
= fpr_read_mask (ip
);
7111 prev_fpr_write
= fpr_write_mask (&history
[0]);
7112 if (fpr_read
& prev_fpr_write
)
7115 /* If the branch writes a register that the previous
7116 instruction sets, we can not swap. */
7117 gpr_write
= gpr_write_mask (ip
);
7118 if (gpr_write
& prev_gpr_write
)
7121 /* If the branch writes a register that the previous
7122 instruction reads, we can not swap. */
7123 prev_gpr_read
= gpr_read_mask (&history
[0]);
7124 if (gpr_write
& prev_gpr_read
)
7127 /* If one instruction sets a condition code and the
7128 other one uses a condition code, we can not swap. */
7129 pinfo
= ip
->insn_mo
->pinfo
;
7130 if ((pinfo
& INSN_READ_COND_CODE
)
7131 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
7133 if ((pinfo
& INSN_WRITE_COND_CODE
)
7134 && (prev_pinfo
& INSN_READ_COND_CODE
))
7137 /* If the previous instruction uses the PC, we can not swap. */
7138 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7139 if (prev_pinfo2
& INSN2_READ_PC
)
7142 /* If the previous instruction has an incorrect size for a fixed
7143 branch delay slot in microMIPS mode, we cannot swap. */
7144 pinfo2
= ip
->insn_mo
->pinfo2
;
7145 if (mips_opts
.micromips
7146 && (pinfo2
& INSN2_BRANCH_DELAY_16BIT
)
7147 && insn_length (history
) != 2)
7149 if (mips_opts
.micromips
7150 && (pinfo2
& INSN2_BRANCH_DELAY_32BIT
)
7151 && insn_length (history
) != 4)
7154 /* On the R5900 short loops need to be fixed by inserting a NOP in the
7157 The short loop bug under certain conditions causes loops to execute
7158 only once or twice. We must ensure that the assembler never
7159 generates loops that satisfy all of the following conditions:
7161 - a loop consists of less than or equal to six instructions
7162 (including the branch delay slot);
7163 - a loop contains only one conditional branch instruction at the end
7165 - a loop does not contain any other branch or jump instructions;
7166 - a branch delay slot of the loop is not NOP (EE 2.9 or later).
7168 We need to do this because of a hardware bug in the R5900 chip. */
7170 /* Check if instruction has a parameter, ignore "j $31". */
7171 && (address_expr
!= NULL
)
7172 /* Parameter must be 16 bit. */
7173 && (*reloc_type
== BFD_RELOC_16_PCREL_S2
)
7174 /* Branch to same segment. */
7175 && (S_GET_SEGMENT (address_expr
->X_add_symbol
) == now_seg
)
7176 /* Branch to same code fragment. */
7177 && (symbol_get_frag (address_expr
->X_add_symbol
) == frag_now
)
7178 /* Can only calculate branch offset if value is known. */
7179 && symbol_constant_p (address_expr
->X_add_symbol
)
7180 /* Check if branch is really conditional. */
7181 && !((ip
->insn_opcode
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
7182 || (ip
->insn_opcode
& 0xffff0000) == 0x04010000 /* bgez $0 */
7183 || (ip
->insn_opcode
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
7186 /* Check if loop is shorter than or equal to 6 instructions
7187 including branch and delay slot. */
7188 distance
= frag_now_fix () - S_GET_VALUE (address_expr
->X_add_symbol
);
7195 /* When the loop includes branches or jumps,
7196 it is not a short loop. */
7197 for (i
= 0; i
< (distance
/ 4); i
++)
7199 if ((history
[i
].cleared_p
)
7200 || delayed_branch_p (&history
[i
]))
7208 /* Insert nop after branch to fix short loop. */
7217 /* Decide how we should add IP to the instruction stream.
7218 ADDRESS_EXPR is an operand of the instruction to be used with
7221 static enum append_method
7222 get_append_method (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7223 bfd_reloc_code_real_type
*reloc_type
)
7225 /* The relaxed version of a macro sequence must be inherently
7227 if (mips_relax
.sequence
== 2)
7230 /* We must not dabble with instructions in a ".set noreorder" block. */
7231 if (mips_opts
.noreorder
)
7234 /* Otherwise, it's our responsibility to fill branch delay slots. */
7235 if (delayed_branch_p (ip
))
7237 if (!branch_likely_p (ip
)
7238 && can_swap_branch_p (ip
, address_expr
, reloc_type
))
7241 if (mips_opts
.mips16
7242 && ISA_SUPPORTS_MIPS16E
7243 && gpr_read_mask (ip
) != 0)
7244 return APPEND_ADD_COMPACT
;
7246 if (mips_opts
.micromips
7247 && ((ip
->insn_opcode
& 0xffe0) == 0x4580
7248 || (!forced_insn_length
7249 && ((ip
->insn_opcode
& 0xfc00) == 0xcc00
7250 || (ip
->insn_opcode
& 0xdc00) == 0x8c00))
7251 || (ip
->insn_opcode
& 0xdfe00000) == 0x94000000
7252 || (ip
->insn_opcode
& 0xdc1f0000) == 0x94000000))
7253 return APPEND_ADD_COMPACT
;
7255 return APPEND_ADD_WITH_NOP
;
7261 /* IP is an instruction whose opcode we have just changed, END points
7262 to the end of the opcode table processed. Point IP->insn_mo to the
7263 new opcode's definition. */
7266 find_altered_opcode (struct mips_cl_insn
*ip
, const struct mips_opcode
*end
)
7268 const struct mips_opcode
*mo
;
7270 for (mo
= ip
->insn_mo
; mo
< end
; mo
++)
7271 if (mo
->pinfo
!= INSN_MACRO
7272 && (ip
->insn_opcode
& mo
->mask
) == mo
->match
)
7280 /* IP is a MIPS16 instruction whose opcode we have just changed.
7281 Point IP->insn_mo to the new opcode's definition. */
7284 find_altered_mips16_opcode (struct mips_cl_insn
*ip
)
7286 find_altered_opcode (ip
, &mips16_opcodes
[bfd_mips16_num_opcodes
]);
7289 /* IP is a microMIPS instruction whose opcode we have just changed.
7290 Point IP->insn_mo to the new opcode's definition. */
7293 find_altered_micromips_opcode (struct mips_cl_insn
*ip
)
7295 find_altered_opcode (ip
, µmips_opcodes
[bfd_micromips_num_opcodes
]);
7298 /* For microMIPS macros, we need to generate a local number label
7299 as the target of branches. */
7300 #define MICROMIPS_LABEL_CHAR '\037'
7301 static unsigned long micromips_target_label
;
7302 static char micromips_target_name
[32];
7305 micromips_label_name (void)
7307 char *p
= micromips_target_name
;
7308 char symbol_name_temporary
[24];
7316 l
= micromips_target_label
;
7317 #ifdef LOCAL_LABEL_PREFIX
7318 *p
++ = LOCAL_LABEL_PREFIX
;
7321 *p
++ = MICROMIPS_LABEL_CHAR
;
7324 symbol_name_temporary
[i
++] = l
% 10 + '0';
7329 *p
++ = symbol_name_temporary
[--i
];
7332 return micromips_target_name
;
7336 micromips_label_expr (expressionS
*label_expr
)
7338 label_expr
->X_op
= O_symbol
;
7339 label_expr
->X_add_symbol
= symbol_find_or_make (micromips_label_name ());
7340 label_expr
->X_add_number
= 0;
7344 micromips_label_inc (void)
7346 micromips_target_label
++;
7347 *micromips_target_name
= '\0';
7351 micromips_add_label (void)
7355 s
= colon (micromips_label_name ());
7356 micromips_label_inc ();
7357 S_SET_OTHER (s
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (s
)));
7360 /* If assembling microMIPS code, then return the microMIPS reloc
7361 corresponding to the requested one if any. Otherwise return
7362 the reloc unchanged. */
7364 static bfd_reloc_code_real_type
7365 micromips_map_reloc (bfd_reloc_code_real_type reloc
)
7367 static const bfd_reloc_code_real_type relocs
[][2] =
7369 /* Keep sorted incrementally by the left-hand key. */
7370 { BFD_RELOC_16_PCREL_S2
, BFD_RELOC_MICROMIPS_16_PCREL_S1
},
7371 { BFD_RELOC_GPREL16
, BFD_RELOC_MICROMIPS_GPREL16
},
7372 { BFD_RELOC_MIPS_JMP
, BFD_RELOC_MICROMIPS_JMP
},
7373 { BFD_RELOC_HI16
, BFD_RELOC_MICROMIPS_HI16
},
7374 { BFD_RELOC_HI16_S
, BFD_RELOC_MICROMIPS_HI16_S
},
7375 { BFD_RELOC_LO16
, BFD_RELOC_MICROMIPS_LO16
},
7376 { BFD_RELOC_MIPS_LITERAL
, BFD_RELOC_MICROMIPS_LITERAL
},
7377 { BFD_RELOC_MIPS_GOT16
, BFD_RELOC_MICROMIPS_GOT16
},
7378 { BFD_RELOC_MIPS_CALL16
, BFD_RELOC_MICROMIPS_CALL16
},
7379 { BFD_RELOC_MIPS_GOT_HI16
, BFD_RELOC_MICROMIPS_GOT_HI16
},
7380 { BFD_RELOC_MIPS_GOT_LO16
, BFD_RELOC_MICROMIPS_GOT_LO16
},
7381 { BFD_RELOC_MIPS_CALL_HI16
, BFD_RELOC_MICROMIPS_CALL_HI16
},
7382 { BFD_RELOC_MIPS_CALL_LO16
, BFD_RELOC_MICROMIPS_CALL_LO16
},
7383 { BFD_RELOC_MIPS_SUB
, BFD_RELOC_MICROMIPS_SUB
},
7384 { BFD_RELOC_MIPS_GOT_PAGE
, BFD_RELOC_MICROMIPS_GOT_PAGE
},
7385 { BFD_RELOC_MIPS_GOT_OFST
, BFD_RELOC_MICROMIPS_GOT_OFST
},
7386 { BFD_RELOC_MIPS_GOT_DISP
, BFD_RELOC_MICROMIPS_GOT_DISP
},
7387 { BFD_RELOC_MIPS_HIGHEST
, BFD_RELOC_MICROMIPS_HIGHEST
},
7388 { BFD_RELOC_MIPS_HIGHER
, BFD_RELOC_MICROMIPS_HIGHER
},
7389 { BFD_RELOC_MIPS_SCN_DISP
, BFD_RELOC_MICROMIPS_SCN_DISP
},
7390 { BFD_RELOC_MIPS_TLS_GD
, BFD_RELOC_MICROMIPS_TLS_GD
},
7391 { BFD_RELOC_MIPS_TLS_LDM
, BFD_RELOC_MICROMIPS_TLS_LDM
},
7392 { BFD_RELOC_MIPS_TLS_DTPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
},
7393 { BFD_RELOC_MIPS_TLS_DTPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
},
7394 { BFD_RELOC_MIPS_TLS_GOTTPREL
, BFD_RELOC_MICROMIPS_TLS_GOTTPREL
},
7395 { BFD_RELOC_MIPS_TLS_TPREL_HI16
, BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
},
7396 { BFD_RELOC_MIPS_TLS_TPREL_LO16
, BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
}
7398 bfd_reloc_code_real_type r
;
7401 if (!mips_opts
.micromips
)
7403 for (i
= 0; i
< ARRAY_SIZE (relocs
); i
++)
7409 return relocs
[i
][1];
7414 /* Try to resolve relocation RELOC against constant OPERAND at assembly time.
7415 Return true on success, storing the resolved value in RESULT. */
7418 calculate_reloc (bfd_reloc_code_real_type reloc
, offsetT operand
,
7423 case BFD_RELOC_MIPS_HIGHEST
:
7424 case BFD_RELOC_MICROMIPS_HIGHEST
:
7425 *result
= ((operand
+ 0x800080008000ull
) >> 48) & 0xffff;
7428 case BFD_RELOC_MIPS_HIGHER
:
7429 case BFD_RELOC_MICROMIPS_HIGHER
:
7430 *result
= ((operand
+ 0x80008000ull
) >> 32) & 0xffff;
7433 case BFD_RELOC_HI16_S
:
7434 case BFD_RELOC_HI16_S_PCREL
:
7435 case BFD_RELOC_MICROMIPS_HI16_S
:
7436 case BFD_RELOC_MIPS16_HI16_S
:
7437 *result
= ((operand
+ 0x8000) >> 16) & 0xffff;
7440 case BFD_RELOC_HI16
:
7441 case BFD_RELOC_MICROMIPS_HI16
:
7442 case BFD_RELOC_MIPS16_HI16
:
7443 *result
= (operand
>> 16) & 0xffff;
7446 case BFD_RELOC_LO16
:
7447 case BFD_RELOC_LO16_PCREL
:
7448 case BFD_RELOC_MICROMIPS_LO16
:
7449 case BFD_RELOC_MIPS16_LO16
:
7450 *result
= operand
& 0xffff;
7453 case BFD_RELOC_UNUSED
:
7462 /* Output an instruction. IP is the instruction information.
7463 ADDRESS_EXPR is an operand of the instruction to be used with
7464 RELOC_TYPE. EXPANSIONP is true if the instruction is part of
7465 a macro expansion. */
7468 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
7469 bfd_reloc_code_real_type
*reloc_type
, bfd_boolean expansionp
)
7471 unsigned long prev_pinfo2
, pinfo
;
7472 bfd_boolean relaxed_branch
= FALSE
;
7473 enum append_method method
;
7474 bfd_boolean relax32
;
7477 if (mips_fix_loongson2f
&& !HAVE_CODE_COMPRESSION
)
7478 fix_loongson2f (ip
);
7480 ip
->target
[0] = '\0';
7481 if (offset_expr
.X_op
== O_symbol
)
7482 strncpy (ip
->target
, S_GET_NAME (offset_expr
.X_add_symbol
), 15);
7483 ip
->label
[0] = '\0';
7484 if (seg_info (now_seg
)->label_list
)
7485 strncpy (ip
->label
, S_GET_NAME (seg_info (now_seg
)->label_list
->label
), 15);
7486 if (mips_fix_loongson3_llsc
&& !HAVE_CODE_COMPRESSION
)
7487 fix_loongson3_llsc (ip
);
7489 file_ase_mips16
|= mips_opts
.mips16
;
7490 file_ase_micromips
|= mips_opts
.micromips
;
7492 prev_pinfo2
= history
[0].insn_mo
->pinfo2
;
7493 pinfo
= ip
->insn_mo
->pinfo
;
7495 /* Don't raise alarm about `nods' frags as they'll fill in the right
7496 kind of nop in relaxation if required. */
7497 if (mips_opts
.micromips
7499 && !(history
[0].frag
7500 && history
[0].frag
->fr_type
== rs_machine_dependent
7501 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
7502 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
7503 && (((prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0
7504 && micromips_insn_length (ip
->insn_mo
) != 2)
7505 || ((prev_pinfo2
& INSN2_BRANCH_DELAY_32BIT
) != 0
7506 && micromips_insn_length (ip
->insn_mo
) != 4)))
7507 as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
7508 (prev_pinfo2
& INSN2_BRANCH_DELAY_16BIT
) != 0 ? 16 : 32);
7510 if (address_expr
== NULL
)
7512 else if (reloc_type
[0] <= BFD_RELOC_UNUSED
7513 && reloc_type
[1] == BFD_RELOC_UNUSED
7514 && reloc_type
[2] == BFD_RELOC_UNUSED
7515 && address_expr
->X_op
== O_constant
)
7517 switch (*reloc_type
)
7519 case BFD_RELOC_MIPS_JMP
:
7523 /* Shift is 2, unusually, for microMIPS JALX. */
7524 shift
= (mips_opts
.micromips
7525 && strcmp (ip
->insn_mo
->name
, "jalx") != 0) ? 1 : 2;
7526 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7527 as_bad (_("jump to misaligned address (0x%lx)"),
7528 (unsigned long) address_expr
->X_add_number
);
7529 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7535 case BFD_RELOC_MIPS16_JMP
:
7536 if ((address_expr
->X_add_number
& 3) != 0)
7537 as_bad (_("jump to misaligned address (0x%lx)"),
7538 (unsigned long) address_expr
->X_add_number
);
7540 (((address_expr
->X_add_number
& 0x7c0000) << 3)
7541 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
7542 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
7546 case BFD_RELOC_16_PCREL_S2
:
7550 shift
= mips_opts
.micromips
? 1 : 2;
7551 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7552 as_bad (_("branch to misaligned address (0x%lx)"),
7553 (unsigned long) address_expr
->X_add_number
);
7554 if (!mips_relax_branch
)
7556 if ((address_expr
->X_add_number
+ (1 << (shift
+ 15)))
7557 & ~((1 << (shift
+ 16)) - 1))
7558 as_bad (_("branch address range overflow (0x%lx)"),
7559 (unsigned long) address_expr
->X_add_number
);
7560 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7566 case BFD_RELOC_MIPS_21_PCREL_S2
:
7571 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7572 as_bad (_("branch to misaligned address (0x%lx)"),
7573 (unsigned long) address_expr
->X_add_number
);
7574 if ((address_expr
->X_add_number
+ (1 << (shift
+ 20)))
7575 & ~((1 << (shift
+ 21)) - 1))
7576 as_bad (_("branch address range overflow (0x%lx)"),
7577 (unsigned long) address_expr
->X_add_number
);
7578 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7583 case BFD_RELOC_MIPS_26_PCREL_S2
:
7588 if ((address_expr
->X_add_number
& ((1 << shift
) - 1)) != 0)
7589 as_bad (_("branch to misaligned address (0x%lx)"),
7590 (unsigned long) address_expr
->X_add_number
);
7591 if ((address_expr
->X_add_number
+ (1 << (shift
+ 25)))
7592 & ~((1 << (shift
+ 26)) - 1))
7593 as_bad (_("branch address range overflow (0x%lx)"),
7594 (unsigned long) address_expr
->X_add_number
);
7595 ip
->insn_opcode
|= ((address_expr
->X_add_number
>> shift
)
7604 if (calculate_reloc (*reloc_type
, address_expr
->X_add_number
,
7607 ip
->insn_opcode
|= value
& 0xffff;
7615 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
7617 /* There are a lot of optimizations we could do that we don't.
7618 In particular, we do not, in general, reorder instructions.
7619 If you use gcc with optimization, it will reorder
7620 instructions and generally do much more optimization then we
7621 do here; repeating all that work in the assembler would only
7622 benefit hand written assembly code, and does not seem worth
7624 int nops
= (mips_optimize
== 0
7625 ? nops_for_insn (0, history
, NULL
)
7626 : nops_for_insn_or_target (0, history
, ip
));
7630 unsigned long old_frag_offset
;
7633 old_frag
= frag_now
;
7634 old_frag_offset
= frag_now_fix ();
7636 for (i
= 0; i
< nops
; i
++)
7637 add_fixed_insn (NOP_INSN
);
7638 insert_into_history (0, nops
, NOP_INSN
);
7642 listing_prev_line ();
7643 /* We may be at the start of a variant frag. In case we
7644 are, make sure there is enough space for the frag
7645 after the frags created by listing_prev_line. The
7646 argument to frag_grow here must be at least as large
7647 as the argument to all other calls to frag_grow in
7648 this file. We don't have to worry about being in the
7649 middle of a variant frag, because the variants insert
7650 all needed nop instructions themselves. */
7654 mips_move_text_labels ();
7656 #ifndef NO_ECOFF_DEBUGGING
7657 if (ECOFF_DEBUGGING
)
7658 ecoff_fix_loc (old_frag
, old_frag_offset
);
7662 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
7666 /* Work out how many nops in prev_nop_frag are needed by IP,
7667 ignoring hazards generated by the first prev_nop_frag_since
7669 nops
= nops_for_insn_or_target (prev_nop_frag_since
, history
, ip
);
7670 gas_assert (nops
<= prev_nop_frag_holds
);
7672 /* Enforce NOPS as a minimum. */
7673 if (nops
> prev_nop_frag_required
)
7674 prev_nop_frag_required
= nops
;
7676 if (prev_nop_frag_holds
== prev_nop_frag_required
)
7678 /* Settle for the current number of nops. Update the history
7679 accordingly (for the benefit of any future .set reorder code). */
7680 prev_nop_frag
= NULL
;
7681 insert_into_history (prev_nop_frag_since
,
7682 prev_nop_frag_holds
, NOP_INSN
);
7686 /* Allow this instruction to replace one of the nops that was
7687 tentatively added to prev_nop_frag. */
7688 prev_nop_frag
->fr_fix
-= NOP_INSN_SIZE
;
7689 prev_nop_frag_holds
--;
7690 prev_nop_frag_since
++;
7694 method
= get_append_method (ip
, address_expr
, reloc_type
);
7695 branch_disp
= method
== APPEND_SWAP
? insn_length (history
) : 0;
7697 dwarf2_emit_insn (0);
7698 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7699 so "move" the instruction address accordingly.
7701 Also, it doesn't seem appropriate for the assembler to reorder .loc
7702 entries. If this instruction is a branch that we are going to swap
7703 with the previous instruction, the two instructions should be
7704 treated as a unit, and the debug information for both instructions
7705 should refer to the start of the branch sequence. Using the
7706 current position is certainly wrong when swapping a 32-bit branch
7707 and a 16-bit delay slot, since the current position would then be
7708 in the middle of a branch. */
7709 dwarf2_move_insn ((HAVE_CODE_COMPRESSION
? 1 : 0) - branch_disp
);
7711 relax32
= (mips_relax_branch
7712 /* Don't try branch relaxation within .set nomacro, or within
7713 .set noat if we use $at for PIC computations. If it turns
7714 out that the branch was out-of-range, we'll get an error. */
7715 && !mips_opts
.warn_about_macros
7716 && (mips_opts
.at
|| mips_pic
== NO_PIC
)
7717 /* Don't relax BPOSGE32/64 or BC1ANY2T/F and BC1ANY4T/F
7718 as they have no complementing branches. */
7719 && !(ip
->insn_mo
->ase
& (ASE_MIPS3D
| ASE_DSP64
| ASE_DSP
)));
7721 if (!HAVE_CODE_COMPRESSION
7724 && *reloc_type
== BFD_RELOC_16_PCREL_S2
7725 && delayed_branch_p (ip
))
7727 relaxed_branch
= TRUE
;
7728 add_relaxed_insn (ip
, (relaxed_branch_length
7730 uncond_branch_p (ip
) ? -1
7731 : branch_likely_p (ip
) ? 1
7734 (AT
, mips_pic
!= NO_PIC
,
7735 uncond_branch_p (ip
),
7736 branch_likely_p (ip
),
7737 pinfo
& INSN_WRITE_GPR_31
,
7739 address_expr
->X_add_symbol
,
7740 address_expr
->X_add_number
);
7741 *reloc_type
= BFD_RELOC_UNUSED
;
7743 else if (mips_opts
.micromips
7745 && ((relax32
&& *reloc_type
== BFD_RELOC_16_PCREL_S2
)
7746 || *reloc_type
> BFD_RELOC_UNUSED
)
7747 && (delayed_branch_p (ip
) || compact_branch_p (ip
))
7748 /* Don't try branch relaxation when users specify
7749 16-bit/32-bit instructions. */
7750 && !forced_insn_length
)
7752 bfd_boolean relax16
= (method
!= APPEND_ADD_COMPACT
7753 && *reloc_type
> BFD_RELOC_UNUSED
);
7754 int type
= relax16
? *reloc_type
- BFD_RELOC_UNUSED
: 0;
7755 int uncond
= uncond_branch_p (ip
) ? -1 : 0;
7756 int compact
= compact_branch_p (ip
) || method
== APPEND_ADD_COMPACT
;
7757 int nods
= method
== APPEND_ADD_WITH_NOP
;
7758 int al
= pinfo
& INSN_WRITE_GPR_31
;
7759 int length32
= nods
? 8 : 4;
7761 gas_assert (address_expr
!= NULL
);
7762 gas_assert (!mips_relax
.sequence
);
7764 relaxed_branch
= TRUE
;
7766 method
= APPEND_ADD
;
7768 length32
= relaxed_micromips_32bit_branch_length (NULL
, NULL
, uncond
);
7769 add_relaxed_insn (ip
, length32
, relax16
? 2 : 4,
7770 RELAX_MICROMIPS_ENCODE (type
, AT
, mips_opts
.insn32
,
7772 uncond
, compact
, al
, nods
,
7774 address_expr
->X_add_symbol
,
7775 address_expr
->X_add_number
);
7776 *reloc_type
= BFD_RELOC_UNUSED
;
7778 else if (mips_opts
.mips16
&& *reloc_type
> BFD_RELOC_UNUSED
)
7780 bfd_boolean require_unextended
;
7781 bfd_boolean require_extended
;
7785 if (forced_insn_length
!= 0)
7787 require_unextended
= forced_insn_length
== 2;
7788 require_extended
= forced_insn_length
== 4;
7792 require_unextended
= (mips_opts
.noautoextend
7793 && !mips_opcode_32bit_p (ip
->insn_mo
));
7794 require_extended
= 0;
7797 /* We need to set up a variant frag. */
7798 gas_assert (address_expr
!= NULL
);
7799 /* Pass any `O_symbol' expression unchanged as an `expr_section'
7800 symbol created by `make_expr_symbol' may not get a necessary
7801 external relocation produced. */
7802 if (address_expr
->X_op
== O_symbol
)
7804 symbol
= address_expr
->X_add_symbol
;
7805 offset
= address_expr
->X_add_number
;
7809 symbol
= make_expr_symbol (address_expr
);
7810 symbol_append (symbol
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
7813 add_relaxed_insn (ip
, 12, 0,
7815 (*reloc_type
- BFD_RELOC_UNUSED
,
7816 mips_opts
.ase
& ASE_MIPS16E2
,
7819 mips_opts
.warn_about_macros
,
7820 require_unextended
, require_extended
,
7821 delayed_branch_p (&history
[0]),
7822 history
[0].mips16_absolute_jump_p
),
7825 else if (mips_opts
.mips16
&& insn_length (ip
) == 2)
7827 if (!delayed_branch_p (ip
))
7828 /* Make sure there is enough room to swap this instruction with
7829 a following jump instruction. */
7831 add_fixed_insn (ip
);
7835 if (mips_opts
.mips16
7836 && mips_opts
.noreorder
7837 && delayed_branch_p (&history
[0]))
7838 as_warn (_("extended instruction in delay slot"));
7840 if (mips_relax
.sequence
)
7842 /* If we've reached the end of this frag, turn it into a variant
7843 frag and record the information for the instructions we've
7845 if (frag_room () < 4)
7846 relax_close_frag ();
7847 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (ip
);
7850 if (mips_relax
.sequence
!= 2)
7852 if (mips_macro_warning
.first_insn_sizes
[0] == 0)
7853 mips_macro_warning
.first_insn_sizes
[0] = insn_length (ip
);
7854 mips_macro_warning
.sizes
[0] += insn_length (ip
);
7855 mips_macro_warning
.insns
[0]++;
7857 if (mips_relax
.sequence
!= 1)
7859 if (mips_macro_warning
.first_insn_sizes
[1] == 0)
7860 mips_macro_warning
.first_insn_sizes
[1] = insn_length (ip
);
7861 mips_macro_warning
.sizes
[1] += insn_length (ip
);
7862 mips_macro_warning
.insns
[1]++;
7865 if (mips_opts
.mips16
)
7868 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
7870 add_fixed_insn (ip
);
7873 if (!ip
->complete_p
&& *reloc_type
< BFD_RELOC_UNUSED
)
7875 bfd_reloc_code_real_type final_type
[3];
7876 reloc_howto_type
*howto0
;
7877 reloc_howto_type
*howto
;
7880 /* Perform any necessary conversion to microMIPS relocations
7881 and find out how many relocations there actually are. */
7882 for (i
= 0; i
< 3 && reloc_type
[i
] != BFD_RELOC_UNUSED
; i
++)
7883 final_type
[i
] = micromips_map_reloc (reloc_type
[i
]);
7885 /* In a compound relocation, it is the final (outermost)
7886 operator that determines the relocated field. */
7887 howto
= howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[i
- 1]);
7892 howto0
= bfd_reloc_type_lookup (stdoutput
, final_type
[0]);
7893 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
7894 bfd_get_reloc_size (howto
),
7896 howto0
&& howto0
->pc_relative
,
7898 /* Record non-PIC mode in `fx_tcbit2' for `md_apply_fix'. */
7899 ip
->fixp
[0]->fx_tcbit2
= mips_pic
== NO_PIC
;
7901 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
7902 if (final_type
[0] == BFD_RELOC_MIPS16_JMP
&& ip
->fixp
[0]->fx_addsy
)
7903 *symbol_get_tc (ip
->fixp
[0]->fx_addsy
) = 1;
7905 /* These relocations can have an addend that won't fit in
7906 4 octets for 64bit assembly. */
7908 && ! howto
->partial_inplace
7909 && (reloc_type
[0] == BFD_RELOC_16
7910 || reloc_type
[0] == BFD_RELOC_32
7911 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
7912 || reloc_type
[0] == BFD_RELOC_GPREL16
7913 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
7914 || reloc_type
[0] == BFD_RELOC_GPREL32
7915 || reloc_type
[0] == BFD_RELOC_64
7916 || reloc_type
[0] == BFD_RELOC_CTOR
7917 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
7918 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
7919 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
7920 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
7921 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
7922 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
7923 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
7924 || hi16_reloc_p (reloc_type
[0])
7925 || lo16_reloc_p (reloc_type
[0])))
7926 ip
->fixp
[0]->fx_no_overflow
= 1;
7928 /* These relocations can have an addend that won't fit in 2 octets. */
7929 if (reloc_type
[0] == BFD_RELOC_MICROMIPS_7_PCREL_S1
7930 || reloc_type
[0] == BFD_RELOC_MICROMIPS_10_PCREL_S1
)
7931 ip
->fixp
[0]->fx_no_overflow
= 1;
7933 if (mips_relax
.sequence
)
7935 if (mips_relax
.first_fixup
== 0)
7936 mips_relax
.first_fixup
= ip
->fixp
[0];
7938 else if (reloc_needs_lo_p (*reloc_type
))
7940 struct mips_hi_fixup
*hi_fixup
;
7942 /* Reuse the last entry if it already has a matching %lo. */
7943 hi_fixup
= mips_hi_fixup_list
;
7945 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
7947 hi_fixup
= XNEW (struct mips_hi_fixup
);
7948 hi_fixup
->next
= mips_hi_fixup_list
;
7949 mips_hi_fixup_list
= hi_fixup
;
7951 hi_fixup
->fixp
= ip
->fixp
[0];
7952 hi_fixup
->seg
= now_seg
;
7955 /* Add fixups for the second and third relocations, if given.
7956 Note that the ABI allows the second relocation to be
7957 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
7958 moment we only use RSS_UNDEF, but we could add support
7959 for the others if it ever becomes necessary. */
7960 for (i
= 1; i
< 3; i
++)
7961 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
7963 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
7964 ip
->fixp
[0]->fx_size
, NULL
, 0,
7965 FALSE
, final_type
[i
]);
7967 /* Use fx_tcbit to mark compound relocs. */
7968 ip
->fixp
[0]->fx_tcbit
= 1;
7969 ip
->fixp
[i
]->fx_tcbit
= 1;
7973 /* Update the register mask information. */
7974 mips_gprmask
|= gpr_read_mask (ip
) | gpr_write_mask (ip
);
7975 mips_cprmask
[1] |= fpr_read_mask (ip
) | fpr_write_mask (ip
);
7980 insert_into_history (0, 1, ip
);
7983 case APPEND_ADD_WITH_NOP
:
7985 struct mips_cl_insn
*nop
;
7987 insert_into_history (0, 1, ip
);
7988 nop
= get_delay_slot_nop (ip
);
7989 add_fixed_insn (nop
);
7990 insert_into_history (0, 1, nop
);
7991 if (mips_relax
.sequence
)
7992 mips_relax
.sizes
[mips_relax
.sequence
- 1] += insn_length (nop
);
7996 case APPEND_ADD_COMPACT
:
7997 /* Convert MIPS16 jr/jalr into a "compact" jump. */
7998 if (mips_opts
.mips16
)
8000 ip
->insn_opcode
|= 0x0080;
8001 find_altered_mips16_opcode (ip
);
8003 /* Convert microMIPS instructions. */
8004 else if (mips_opts
.micromips
)
8007 if ((ip
->insn_opcode
& 0xffe0) == 0x4580)
8008 ip
->insn_opcode
|= 0x0020;
8010 else if ((ip
->insn_opcode
& 0xfc00) == 0xcc00)
8011 ip
->insn_opcode
= 0x40e00000;
8012 /* beqz16->beqzc, bnez16->bnezc */
8013 else if ((ip
->insn_opcode
& 0xdc00) == 0x8c00)
8015 unsigned long regno
;
8017 regno
= ip
->insn_opcode
>> MICROMIPSOP_SH_MD
;
8018 regno
&= MICROMIPSOP_MASK_MD
;
8019 regno
= micromips_to_32_reg_d_map
[regno
];
8020 ip
->insn_opcode
= (((ip
->insn_opcode
<< 9) & 0x00400000)
8021 | (regno
<< MICROMIPSOP_SH_RS
)
8022 | 0x40a00000) ^ 0x00400000;
8024 /* beqz->beqzc, bnez->bnezc */
8025 else if ((ip
->insn_opcode
& 0xdfe00000) == 0x94000000)
8026 ip
->insn_opcode
= ((ip
->insn_opcode
& 0x001f0000)
8027 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8028 | 0x40a00000) ^ 0x00400000;
8029 /* beq $0->beqzc, bne $0->bnezc */
8030 else if ((ip
->insn_opcode
& 0xdc1f0000) == 0x94000000)
8031 ip
->insn_opcode
= (((ip
->insn_opcode
>>
8032 (MICROMIPSOP_SH_RT
- MICROMIPSOP_SH_RS
))
8033 & (MICROMIPSOP_MASK_RS
<< MICROMIPSOP_SH_RS
))
8034 | ((ip
->insn_opcode
>> 7) & 0x00400000)
8035 | 0x40a00000) ^ 0x00400000;
8038 find_altered_micromips_opcode (ip
);
8043 insert_into_history (0, 1, ip
);
8048 struct mips_cl_insn delay
= history
[0];
8050 if (relaxed_branch
|| delay
.frag
!= ip
->frag
)
8052 /* Add the delay slot instruction to the end of the
8053 current frag and shrink the fixed part of the
8054 original frag. If the branch occupies the tail of
8055 the latter, move it backwards to cover the gap. */
8056 delay
.frag
->fr_fix
-= branch_disp
;
8057 if (delay
.frag
== ip
->frag
)
8058 move_insn (ip
, ip
->frag
, ip
->where
- branch_disp
);
8059 add_fixed_insn (&delay
);
8063 /* If this is not a relaxed branch and we are in the
8064 same frag, then just swap the instructions. */
8065 move_insn (ip
, delay
.frag
, delay
.where
);
8066 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
8070 insert_into_history (0, 1, &delay
);
8075 /* If we have just completed an unconditional branch, clear the history. */
8076 if ((delayed_branch_p (&history
[1]) && uncond_branch_p (&history
[1]))
8077 || (compact_branch_p (&history
[0]) && uncond_branch_p (&history
[0])))
8081 mips_no_prev_insn ();
8083 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8084 history
[i
].cleared_p
= 1;
8087 /* We need to emit a label at the end of branch-likely macros. */
8088 if (emit_branch_likely_macro
)
8090 emit_branch_likely_macro
= FALSE
;
8091 micromips_add_label ();
8094 /* We just output an insn, so the next one doesn't have a label. */
8095 mips_clear_insn_labels ();
8098 /* Forget that there was any previous instruction or label.
8099 When BRANCH is true, the branch history is also flushed. */
8102 mips_no_prev_insn (void)
8104 prev_nop_frag
= NULL
;
8105 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
8106 mips_clear_insn_labels ();
8109 /* This function must be called before we emit something other than
8110 instructions. It is like mips_no_prev_insn except that it inserts
8111 any NOPS that might be needed by previous instructions. */
8114 mips_emit_delays (void)
8116 if (! mips_opts
.noreorder
)
8118 int nops
= nops_for_insn (0, history
, NULL
);
8122 add_fixed_insn (NOP_INSN
);
8123 mips_move_text_labels ();
8126 mips_no_prev_insn ();
8129 /* Start a (possibly nested) noreorder block. */
8132 start_noreorder (void)
8134 if (mips_opts
.noreorder
== 0)
8139 /* None of the instructions before the .set noreorder can be moved. */
8140 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
8141 history
[i
].fixed_p
= 1;
8143 /* Insert any nops that might be needed between the .set noreorder
8144 block and the previous instructions. We will later remove any
8145 nops that turn out not to be needed. */
8146 nops
= nops_for_insn (0, history
, NULL
);
8149 if (mips_optimize
!= 0)
8151 /* Record the frag which holds the nop instructions, so
8152 that we can remove them if we don't need them. */
8153 frag_grow (nops
* NOP_INSN_SIZE
);
8154 prev_nop_frag
= frag_now
;
8155 prev_nop_frag_holds
= nops
;
8156 prev_nop_frag_required
= 0;
8157 prev_nop_frag_since
= 0;
8160 for (; nops
> 0; --nops
)
8161 add_fixed_insn (NOP_INSN
);
8163 /* Move on to a new frag, so that it is safe to simply
8164 decrease the size of prev_nop_frag. */
8165 frag_wane (frag_now
);
8167 mips_move_text_labels ();
8169 mips_mark_labels ();
8170 mips_clear_insn_labels ();
8172 mips_opts
.noreorder
++;
8173 mips_any_noreorder
= 1;
8176 /* End a nested noreorder block. */
8179 end_noreorder (void)
8181 mips_opts
.noreorder
--;
8182 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
8184 /* Commit to inserting prev_nop_frag_required nops and go back to
8185 handling nop insertion the .set reorder way. */
8186 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
8188 insert_into_history (prev_nop_frag_since
,
8189 prev_nop_frag_required
, NOP_INSN
);
8190 prev_nop_frag
= NULL
;
8194 /* Sign-extend 32-bit mode constants that have bit 31 set and all
8195 higher bits unset. */
8198 normalize_constant_expr (expressionS
*ex
)
8200 if (ex
->X_op
== O_constant
8201 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8202 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8206 /* Sign-extend 32-bit mode address offsets that have bit 31 set and
8207 all higher bits unset. */
8210 normalize_address_expr (expressionS
*ex
)
8212 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
8213 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
8214 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
8215 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
8219 /* Try to match TOKENS against OPCODE, storing the result in INSN.
8220 Return true if the match was successful.
8222 OPCODE_EXTRA is a value that should be ORed into the opcode
8223 (used for VU0 channel suffixes, etc.). MORE_ALTS is true if
8224 there are more alternatives after OPCODE and SOFT_MATCH is
8225 as for mips_arg_info. */
8228 match_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8229 struct mips_operand_token
*tokens
, unsigned int opcode_extra
,
8230 bfd_boolean lax_match
, bfd_boolean complete_p
)
8233 struct mips_arg_info arg
;
8234 const struct mips_operand
*operand
;
8237 imm_expr
.X_op
= O_absent
;
8238 offset_expr
.X_op
= O_absent
;
8239 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8240 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8241 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8243 create_insn (insn
, opcode
);
8244 /* When no opcode suffix is specified, assume ".xyzw". */
8245 if ((opcode
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0 && opcode_extra
== 0)
8246 insn
->insn_opcode
|= 0xf << mips_vu0_channel_mask
.lsb
;
8248 insn
->insn_opcode
|= opcode_extra
;
8249 memset (&arg
, 0, sizeof (arg
));
8253 arg
.last_regno
= ILLEGAL_REG
;
8254 arg
.dest_regno
= ILLEGAL_REG
;
8255 arg
.lax_match
= lax_match
;
8256 for (args
= opcode
->args
;; ++args
)
8258 if (arg
.token
->type
== OT_END
)
8260 /* Handle unary instructions in which only one operand is given.
8261 The source is then the same as the destination. */
8262 if (arg
.opnum
== 1 && *args
== ',')
8264 operand
= (mips_opts
.micromips
8265 ? decode_micromips_operand (args
+ 1)
8266 : decode_mips_operand (args
+ 1));
8267 if (operand
&& mips_optional_operand_p (operand
))
8275 /* Treat elided base registers as $0. */
8276 if (strcmp (args
, "(b)") == 0)
8284 /* The register suffix is optional. */
8289 /* Fail the match if there were too few operands. */
8293 /* Successful match. */
8296 clear_insn_error ();
8297 if (arg
.dest_regno
== arg
.last_regno
8298 && strncmp (insn
->insn_mo
->name
, "jalr", 4) == 0)
8302 (0, _("source and destination must be different"));
8303 else if (arg
.last_regno
== 31)
8305 (0, _("a destination register must be supplied"));
8307 else if (arg
.last_regno
== 31
8308 && (strncmp (insn
->insn_mo
->name
, "bltzal", 6) == 0
8309 || strncmp (insn
->insn_mo
->name
, "bgezal", 6) == 0))
8310 set_insn_error (0, _("the source register must not be $31"));
8311 check_completed_insn (&arg
);
8315 /* Fail the match if the line has too many operands. */
8319 /* Handle characters that need to match exactly. */
8320 if (*args
== '(' || *args
== ')' || *args
== ',')
8322 if (match_char (&arg
, *args
))
8329 if (arg
.token
->type
== OT_DOUBLE_CHAR
8330 && arg
.token
->u
.ch
== *args
)
8338 /* Handle special macro operands. Work out the properties of
8347 *offset_reloc
= BFD_RELOC_MIPS_19_PCREL_S2
;
8351 *offset_reloc
= BFD_RELOC_MIPS_18_PCREL_S3
;
8360 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8364 *offset_reloc
= BFD_RELOC_MIPS_26_PCREL_S2
;
8368 *offset_reloc
= BFD_RELOC_MIPS_21_PCREL_S2
;
8374 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8376 imm_expr
.X_op
= O_constant
;
8378 normalize_constant_expr (&imm_expr
);
8382 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8384 /* Assume that the offset has been elided and that what
8385 we saw was a base register. The match will fail later
8386 if that assumption turns out to be wrong. */
8387 offset_expr
.X_op
= O_constant
;
8388 offset_expr
.X_add_number
= 0;
8392 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8394 normalize_address_expr (&offset_expr
);
8399 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8405 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8411 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8417 if (!match_float_constant (&arg
, &imm_expr
, &offset_expr
,
8423 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8427 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8431 gas_assert (mips_opts
.micromips
);
8437 if (!forced_insn_length
)
8438 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8440 *offset_reloc
= BFD_RELOC_MICROMIPS_10_PCREL_S1
;
8442 *offset_reloc
= BFD_RELOC_MICROMIPS_7_PCREL_S1
;
8448 operand
= (mips_opts
.micromips
8449 ? decode_micromips_operand (args
)
8450 : decode_mips_operand (args
));
8454 /* Skip prefixes. */
8455 if (*args
== '+' || *args
== 'm' || *args
== '-')
8458 if (mips_optional_operand_p (operand
)
8460 && (arg
.token
[0].type
!= OT_REG
8461 || arg
.token
[1].type
== OT_END
))
8463 /* Assume that the register has been elided and is the
8464 same as the first operand. */
8469 if (!match_operand (&arg
, operand
))
8474 /* Like match_insn, but for MIPS16. */
8477 match_mips16_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*opcode
,
8478 struct mips_operand_token
*tokens
)
8481 const struct mips_operand
*operand
;
8482 const struct mips_operand
*ext_operand
;
8483 bfd_boolean pcrel
= FALSE
;
8484 int required_insn_length
;
8485 struct mips_arg_info arg
;
8488 if (forced_insn_length
)
8489 required_insn_length
= forced_insn_length
;
8490 else if (mips_opts
.noautoextend
&& !mips_opcode_32bit_p (opcode
))
8491 required_insn_length
= 2;
8493 required_insn_length
= 0;
8495 create_insn (insn
, opcode
);
8496 imm_expr
.X_op
= O_absent
;
8497 offset_expr
.X_op
= O_absent
;
8498 offset_reloc
[0] = BFD_RELOC_UNUSED
;
8499 offset_reloc
[1] = BFD_RELOC_UNUSED
;
8500 offset_reloc
[2] = BFD_RELOC_UNUSED
;
8503 memset (&arg
, 0, sizeof (arg
));
8507 arg
.last_regno
= ILLEGAL_REG
;
8508 arg
.dest_regno
= ILLEGAL_REG
;
8510 for (args
= opcode
->args
;; ++args
)
8514 if (arg
.token
->type
== OT_END
)
8518 /* Handle unary instructions in which only one operand is given.
8519 The source is then the same as the destination. */
8520 if (arg
.opnum
== 1 && *args
== ',')
8522 operand
= decode_mips16_operand (args
[1], FALSE
);
8523 if (operand
&& mips_optional_operand_p (operand
))
8531 /* Fail the match if there were too few operands. */
8535 /* Successful match. Stuff the immediate value in now, if
8537 clear_insn_error ();
8538 if (opcode
->pinfo
== INSN_MACRO
)
8540 gas_assert (relax_char
== 0 || relax_char
== 'p');
8541 gas_assert (*offset_reloc
== BFD_RELOC_UNUSED
);
8544 && offset_expr
.X_op
== O_constant
8546 && calculate_reloc (*offset_reloc
,
8547 offset_expr
.X_add_number
,
8550 mips16_immed (NULL
, 0, relax_char
, *offset_reloc
, value
,
8551 required_insn_length
, &insn
->insn_opcode
);
8552 offset_expr
.X_op
= O_absent
;
8553 *offset_reloc
= BFD_RELOC_UNUSED
;
8555 else if (relax_char
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
8557 if (required_insn_length
== 2)
8558 set_insn_error (0, _("invalid unextended operand value"));
8559 else if (!mips_opcode_32bit_p (opcode
))
8561 forced_insn_length
= 4;
8562 insn
->insn_opcode
|= MIPS16_EXTEND
;
8565 else if (relax_char
)
8566 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ relax_char
;
8568 check_completed_insn (&arg
);
8572 /* Fail the match if the line has too many operands. */
8576 /* Handle characters that need to match exactly. */
8577 if (*args
== '(' || *args
== ')' || *args
== ',')
8579 if (match_char (&arg
, *args
))
8599 if (!match_const_int (&arg
, &imm_expr
.X_add_number
))
8601 imm_expr
.X_op
= O_constant
;
8603 normalize_constant_expr (&imm_expr
);
8608 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8612 operand
= decode_mips16_operand (c
, mips_opcode_32bit_p (opcode
));
8616 if (operand
->type
== OP_PCREL
)
8620 ext_operand
= decode_mips16_operand (c
, TRUE
);
8621 if (operand
!= ext_operand
)
8623 if (arg
.token
->type
== OT_CHAR
&& arg
.token
->u
.ch
== '(')
8625 offset_expr
.X_op
= O_constant
;
8626 offset_expr
.X_add_number
= 0;
8631 if (!match_expression (&arg
, &offset_expr
, offset_reloc
))
8634 /* '8' is used for SLTI(U) and has traditionally not
8635 been allowed to take relocation operators. */
8636 if (offset_reloc
[0] != BFD_RELOC_UNUSED
8637 && (ext_operand
->size
!= 16 || c
== '8'))
8639 match_not_constant (&arg
);
8643 if (offset_expr
.X_op
== O_big
)
8645 match_out_of_range (&arg
);
8654 if (mips_optional_operand_p (operand
)
8656 && (arg
.token
[0].type
!= OT_REG
8657 || arg
.token
[1].type
== OT_END
))
8659 /* Assume that the register has been elided and is the
8660 same as the first operand. */
8665 if (!match_operand (&arg
, operand
))
8670 /* Record that the current instruction is invalid for the current ISA. */
8673 match_invalid_for_isa (void)
8676 (0, _("opcode not supported on this processor: %s (%s)"),
8677 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8678 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8681 /* Try to match TOKENS against a series of opcode entries, starting at FIRST.
8682 Return true if a definite match or failure was found, storing any match
8683 in INSN. OPCODE_EXTRA is a value that should be ORed into the opcode
8684 (to handle things like VU0 suffixes). LAX_MATCH is true if we have already
8685 tried and failed to match under normal conditions and now want to try a
8686 more relaxed match. */
8689 match_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8690 const struct mips_opcode
*past
, struct mips_operand_token
*tokens
,
8691 int opcode_extra
, bfd_boolean lax_match
)
8693 const struct mips_opcode
*opcode
;
8694 const struct mips_opcode
*invalid_delay_slot
;
8695 bfd_boolean seen_valid_for_isa
, seen_valid_for_size
;
8697 /* Search for a match, ignoring alternatives that don't satisfy the
8698 current ISA or forced_length. */
8699 invalid_delay_slot
= 0;
8700 seen_valid_for_isa
= FALSE
;
8701 seen_valid_for_size
= FALSE
;
8705 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8706 if (is_opcode_valid (opcode
))
8708 seen_valid_for_isa
= TRUE
;
8709 if (is_size_valid (opcode
))
8711 bfd_boolean delay_slot_ok
;
8713 seen_valid_for_size
= TRUE
;
8714 delay_slot_ok
= is_delay_slot_valid (opcode
);
8715 if (match_insn (insn
, opcode
, tokens
, opcode_extra
,
8716 lax_match
, delay_slot_ok
))
8720 if (!invalid_delay_slot
)
8721 invalid_delay_slot
= opcode
;
8730 while (opcode
< past
&& strcmp (opcode
->name
, first
->name
) == 0);
8732 /* If the only matches we found had the wrong length for the delay slot,
8733 pick the first such match. We'll issue an appropriate warning later. */
8734 if (invalid_delay_slot
)
8736 if (match_insn (insn
, invalid_delay_slot
, tokens
, opcode_extra
,
8742 /* Handle the case where we didn't try to match an instruction because
8743 all the alternatives were incompatible with the current ISA. */
8744 if (!seen_valid_for_isa
)
8746 match_invalid_for_isa ();
8750 /* Handle the case where we didn't try to match an instruction because
8751 all the alternatives were of the wrong size. */
8752 if (!seen_valid_for_size
)
8754 if (mips_opts
.insn32
)
8755 set_insn_error (0, _("opcode not supported in the `insn32' mode"));
8758 (0, _("unrecognized %d-bit version of microMIPS opcode"),
8759 8 * forced_insn_length
);
8766 /* Like match_insns, but for MIPS16. */
8769 match_mips16_insns (struct mips_cl_insn
*insn
, const struct mips_opcode
*first
,
8770 struct mips_operand_token
*tokens
)
8772 const struct mips_opcode
*opcode
;
8773 bfd_boolean seen_valid_for_isa
;
8774 bfd_boolean seen_valid_for_size
;
8776 /* Search for a match, ignoring alternatives that don't satisfy the
8777 current ISA. There are no separate entries for extended forms so
8778 we deal with forced_length later. */
8779 seen_valid_for_isa
= FALSE
;
8780 seen_valid_for_size
= FALSE
;
8784 gas_assert (strcmp (opcode
->name
, first
->name
) == 0);
8785 if (is_opcode_valid_16 (opcode
))
8787 seen_valid_for_isa
= TRUE
;
8788 if (is_size_valid_16 (opcode
))
8790 seen_valid_for_size
= TRUE
;
8791 if (match_mips16_insn (insn
, opcode
, tokens
))
8797 while (opcode
< &mips16_opcodes
[bfd_mips16_num_opcodes
]
8798 && strcmp (opcode
->name
, first
->name
) == 0);
8800 /* Handle the case where we didn't try to match an instruction because
8801 all the alternatives were incompatible with the current ISA. */
8802 if (!seen_valid_for_isa
)
8804 match_invalid_for_isa ();
8808 /* Handle the case where we didn't try to match an instruction because
8809 all the alternatives were of the wrong size. */
8810 if (!seen_valid_for_size
)
8812 if (forced_insn_length
== 2)
8814 (0, _("unrecognized unextended version of MIPS16 opcode"));
8817 (0, _("unrecognized extended version of MIPS16 opcode"));
8824 /* Set up global variables for the start of a new macro. */
8829 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
8830 memset (&mips_macro_warning
.first_insn_sizes
, 0,
8831 sizeof (mips_macro_warning
.first_insn_sizes
));
8832 memset (&mips_macro_warning
.insns
, 0, sizeof (mips_macro_warning
.insns
));
8833 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
8834 && delayed_branch_p (&history
[0]));
8836 && history
[0].frag
->fr_type
== rs_machine_dependent
8837 && RELAX_MICROMIPS_P (history
[0].frag
->fr_subtype
)
8838 && RELAX_MICROMIPS_NODS (history
[0].frag
->fr_subtype
))
8839 mips_macro_warning
.delay_slot_length
= 0;
8841 switch (history
[0].insn_mo
->pinfo2
8842 & (INSN2_BRANCH_DELAY_32BIT
| INSN2_BRANCH_DELAY_16BIT
))
8844 case INSN2_BRANCH_DELAY_32BIT
:
8845 mips_macro_warning
.delay_slot_length
= 4;
8847 case INSN2_BRANCH_DELAY_16BIT
:
8848 mips_macro_warning
.delay_slot_length
= 2;
8851 mips_macro_warning
.delay_slot_length
= 0;
8854 mips_macro_warning
.first_frag
= NULL
;
8857 /* Given that a macro is longer than one instruction or of the wrong size,
8858 return the appropriate warning for it. Return null if no warning is
8859 needed. SUBTYPE is a bitmask of RELAX_DELAY_SLOT, RELAX_DELAY_SLOT_16BIT,
8860 RELAX_DELAY_SLOT_SIZE_FIRST, RELAX_DELAY_SLOT_SIZE_SECOND,
8861 and RELAX_NOMACRO. */
8864 macro_warning (relax_substateT subtype
)
8866 if (subtype
& RELAX_DELAY_SLOT
)
8867 return _("macro instruction expanded into multiple instructions"
8868 " in a branch delay slot");
8869 else if (subtype
& RELAX_NOMACRO
)
8870 return _("macro instruction expanded into multiple instructions");
8871 else if (subtype
& (RELAX_DELAY_SLOT_SIZE_FIRST
8872 | RELAX_DELAY_SLOT_SIZE_SECOND
))
8873 return ((subtype
& RELAX_DELAY_SLOT_16BIT
)
8874 ? _("macro instruction expanded into a wrong size instruction"
8875 " in a 16-bit branch delay slot")
8876 : _("macro instruction expanded into a wrong size instruction"
8877 " in a 32-bit branch delay slot"));
8882 /* Finish up a macro. Emit warnings as appropriate. */
8887 /* Relaxation warning flags. */
8888 relax_substateT subtype
= 0;
8890 /* Check delay slot size requirements. */
8891 if (mips_macro_warning
.delay_slot_length
== 2)
8892 subtype
|= RELAX_DELAY_SLOT_16BIT
;
8893 if (mips_macro_warning
.delay_slot_length
!= 0)
8895 if (mips_macro_warning
.delay_slot_length
8896 != mips_macro_warning
.first_insn_sizes
[0])
8897 subtype
|= RELAX_DELAY_SLOT_SIZE_FIRST
;
8898 if (mips_macro_warning
.delay_slot_length
8899 != mips_macro_warning
.first_insn_sizes
[1])
8900 subtype
|= RELAX_DELAY_SLOT_SIZE_SECOND
;
8903 /* Check instruction count requirements. */
8904 if (mips_macro_warning
.insns
[0] > 1 || mips_macro_warning
.insns
[1] > 1)
8906 if (mips_macro_warning
.insns
[1] > mips_macro_warning
.insns
[0])
8907 subtype
|= RELAX_SECOND_LONGER
;
8908 if (mips_opts
.warn_about_macros
)
8909 subtype
|= RELAX_NOMACRO
;
8910 if (mips_macro_warning
.delay_slot_p
)
8911 subtype
|= RELAX_DELAY_SLOT
;
8914 /* If both alternatives fail to fill a delay slot correctly,
8915 emit the warning now. */
8916 if ((subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0
8917 && (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0)
8922 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
8923 | RELAX_DELAY_SLOT_SIZE_FIRST
8924 | RELAX_DELAY_SLOT_SIZE_SECOND
);
8925 msg
= macro_warning (s
);
8927 as_warn ("%s", msg
);
8931 /* If both implementations are longer than 1 instruction, then emit the
8933 if (mips_macro_warning
.insns
[0] > 1 && mips_macro_warning
.insns
[1] > 1)
8938 s
= subtype
& (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
);
8939 msg
= macro_warning (s
);
8941 as_warn ("%s", msg
);
8945 /* If any flags still set, then one implementation might need a warning
8946 and the other either will need one of a different kind or none at all.
8947 Pass any remaining flags over to relaxation. */
8948 if (mips_macro_warning
.first_frag
!= NULL
)
8949 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
8952 /* Instruction operand formats used in macros that vary between
8953 standard MIPS and microMIPS code. */
8955 static const char * const brk_fmt
[2][2] = { { "c", "c" }, { "mF", "c" } };
8956 static const char * const cop12_fmt
[2] = { "E,o(b)", "E,~(b)" };
8957 static const char * const jalr_fmt
[2] = { "d,s", "t,s" };
8958 static const char * const lui_fmt
[2] = { "t,u", "s,u" };
8959 static const char * const mem12_fmt
[2] = { "t,o(b)", "t,~(b)" };
8960 static const char * const mfhl_fmt
[2][2] = { { "d", "d" }, { "mj", "s" } };
8961 static const char * const shft_fmt
[2] = { "d,w,<", "t,r,<" };
8962 static const char * const trap_fmt
[2] = { "s,t,q", "s,t,|" };
8964 #define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
8965 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8966 : cop12_fmt[mips_opts.micromips])
8967 #define JALR_FMT (jalr_fmt[mips_opts.micromips])
8968 #define LUI_FMT (lui_fmt[mips_opts.micromips])
8969 #define MEM12_FMT (mem12_fmt[mips_opts.micromips])
8970 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
8971 : mem12_fmt[mips_opts.micromips])
8972 #define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
8973 #define SHFT_FMT (shft_fmt[mips_opts.micromips])
8974 #define TRAP_FMT (trap_fmt[mips_opts.micromips])
8976 /* Read a macro's relocation codes from *ARGS and store them in *R.
8977 The first argument in *ARGS will be either the code for a single
8978 relocation or -1 followed by the three codes that make up a
8979 composite relocation. */
8982 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
8986 next
= va_arg (*args
, int);
8988 r
[0] = (bfd_reloc_code_real_type
) next
;
8991 for (i
= 0; i
< 3; i
++)
8992 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
8993 /* This function is only used for 16-bit relocation fields.
8994 To make the macro code simpler, treat an unrelocated value
8995 in the same way as BFD_RELOC_LO16. */
8996 if (r
[0] == BFD_RELOC_UNUSED
)
8997 r
[0] = BFD_RELOC_LO16
;
9001 /* Build an instruction created by a macro expansion. This is passed
9002 a pointer to the count of instructions created so far, an
9003 expression, the name of the instruction to build, an operand format
9004 string, and corresponding arguments. */
9007 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
9009 const struct mips_opcode
*mo
= NULL
;
9010 bfd_reloc_code_real_type r
[3];
9011 const struct mips_opcode
*amo
;
9012 const struct mips_operand
*operand
;
9014 struct mips_cl_insn insn
;
9018 va_start (args
, fmt
);
9020 if (mips_opts
.mips16
)
9022 mips16_macro_build (ep
, name
, fmt
, &args
);
9027 r
[0] = BFD_RELOC_UNUSED
;
9028 r
[1] = BFD_RELOC_UNUSED
;
9029 r
[2] = BFD_RELOC_UNUSED
;
9030 hash
= mips_opts
.micromips
? micromips_op_hash
: op_hash
;
9031 amo
= (struct mips_opcode
*) str_hash_find (hash
, name
);
9033 gas_assert (strcmp (name
, amo
->name
) == 0);
9037 /* Search until we get a match for NAME. It is assumed here that
9038 macros will never generate MDMX, MIPS-3D, or MT instructions.
9039 We try to match an instruction that fulfills the branch delay
9040 slot instruction length requirement (if any) of the previous
9041 instruction. While doing this we record the first instruction
9042 seen that matches all the other conditions and use it anyway
9043 if the requirement cannot be met; we will issue an appropriate
9044 warning later on. */
9045 if (strcmp (fmt
, amo
->args
) == 0
9046 && amo
->pinfo
!= INSN_MACRO
9047 && is_opcode_valid (amo
)
9048 && is_size_valid (amo
))
9050 if (is_delay_slot_valid (amo
))
9060 gas_assert (amo
->name
);
9062 while (strcmp (name
, amo
->name
) == 0);
9065 create_insn (&insn
, mo
);
9078 macro_read_relocs (&args
, r
);
9079 gas_assert (*r
== BFD_RELOC_GPREL16
9080 || *r
== BFD_RELOC_MIPS_HIGHER
9081 || *r
== BFD_RELOC_HI16_S
9082 || *r
== BFD_RELOC_LO16
9083 || *r
== BFD_RELOC_MIPS_GOT_OFST
9084 || (mips_opts
.micromips
9085 && (*r
== BFD_RELOC_16
9086 || *r
== BFD_RELOC_MIPS_GOT16
9087 || *r
== BFD_RELOC_MIPS_CALL16
9088 || *r
== BFD_RELOC_MIPS_GOT_HI16
9089 || *r
== BFD_RELOC_MIPS_GOT_LO16
9090 || *r
== BFD_RELOC_MIPS_CALL_HI16
9091 || *r
== BFD_RELOC_MIPS_CALL_LO16
9092 || *r
== BFD_RELOC_MIPS_SUB
9093 || *r
== BFD_RELOC_MIPS_GOT_PAGE
9094 || *r
== BFD_RELOC_MIPS_HIGHEST
9095 || *r
== BFD_RELOC_MIPS_GOT_DISP
9096 || *r
== BFD_RELOC_MIPS_TLS_GD
9097 || *r
== BFD_RELOC_MIPS_TLS_LDM
9098 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_HI16
9099 || *r
== BFD_RELOC_MIPS_TLS_DTPREL_LO16
9100 || *r
== BFD_RELOC_MIPS_TLS_GOTTPREL
9101 || *r
== BFD_RELOC_MIPS_TLS_TPREL_HI16
9102 || *r
== BFD_RELOC_MIPS_TLS_TPREL_LO16
)));
9106 macro_read_relocs (&args
, r
);
9110 macro_read_relocs (&args
, r
);
9111 gas_assert (ep
!= NULL
9112 && (ep
->X_op
== O_constant
9113 || (ep
->X_op
== O_symbol
9114 && (*r
== BFD_RELOC_MIPS_HIGHEST
9115 || *r
== BFD_RELOC_HI16_S
9116 || *r
== BFD_RELOC_HI16
9117 || *r
== BFD_RELOC_GPREL16
9118 || *r
== BFD_RELOC_MIPS_GOT_HI16
9119 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
9123 gas_assert (ep
!= NULL
);
9126 * This allows macro() to pass an immediate expression for
9127 * creating short branches without creating a symbol.
9129 * We don't allow branch relaxation for these branches, as
9130 * they should only appear in ".set nomacro" anyway.
9132 if (ep
->X_op
== O_constant
)
9134 /* For microMIPS we always use relocations for branches.
9135 So we should not resolve immediate values. */
9136 gas_assert (!mips_opts
.micromips
);
9138 if ((ep
->X_add_number
& 3) != 0)
9139 as_bad (_("branch to misaligned address (0x%lx)"),
9140 (unsigned long) ep
->X_add_number
);
9141 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
9142 as_bad (_("branch address range overflow (0x%lx)"),
9143 (unsigned long) ep
->X_add_number
);
9144 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
9148 *r
= BFD_RELOC_16_PCREL_S2
;
9152 gas_assert (ep
!= NULL
);
9153 *r
= BFD_RELOC_MIPS_JMP
;
9157 operand
= (mips_opts
.micromips
9158 ? decode_micromips_operand (fmt
)
9159 : decode_mips_operand (fmt
));
9163 uval
= va_arg (args
, int);
9164 if (operand
->type
== OP_CLO_CLZ_DEST
)
9165 uval
|= (uval
<< 5);
9166 insn_insert_operand (&insn
, operand
, uval
);
9168 if (*fmt
== '+' || *fmt
== 'm' || *fmt
== '-')
9174 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9176 append_insn (&insn
, ep
, r
, TRUE
);
9180 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
9183 struct mips_opcode
*mo
;
9184 struct mips_cl_insn insn
;
9185 const struct mips_operand
*operand
;
9186 bfd_reloc_code_real_type r
[3]
9187 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
9189 mo
= (struct mips_opcode
*) str_hash_find (mips16_op_hash
, name
);
9191 gas_assert (strcmp (name
, mo
->name
) == 0);
9193 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
9196 gas_assert (mo
->name
);
9197 gas_assert (strcmp (name
, mo
->name
) == 0);
9200 create_insn (&insn
, mo
);
9237 gas_assert (ep
!= NULL
);
9239 if (ep
->X_op
!= O_constant
)
9240 *r
= (int) BFD_RELOC_UNUSED
+ c
;
9241 else if (calculate_reloc (*r
, ep
->X_add_number
, &value
))
9243 mips16_immed (NULL
, 0, c
, *r
, value
, 0, &insn
.insn_opcode
);
9245 *r
= BFD_RELOC_UNUSED
;
9251 operand
= decode_mips16_operand (c
, FALSE
);
9255 insn_insert_operand (&insn
, operand
, va_arg (*args
, int));
9260 gas_assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
9262 append_insn (&insn
, ep
, r
, TRUE
);
9266 * Generate a "jalr" instruction with a relocation hint to the called
9267 * function. This occurs in NewABI PIC code.
9270 macro_build_jalr (expressionS
*ep
, int cprestore
)
9272 static const bfd_reloc_code_real_type jalr_relocs
[2]
9273 = { BFD_RELOC_MIPS_JALR
, BFD_RELOC_MICROMIPS_JALR
};
9274 bfd_reloc_code_real_type jalr_reloc
= jalr_relocs
[mips_opts
.micromips
];
9278 if (MIPS_JALR_HINT_P (ep
))
9283 if (mips_opts
.micromips
)
9285 jalr
= ((mips_opts
.noreorder
&& !cprestore
) || mips_opts
.insn32
9286 ? "jalr" : "jalrs");
9287 if (MIPS_JALR_HINT_P (ep
)
9289 || (history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9290 macro_build (NULL
, jalr
, "t,s", RA
, PIC_CALL_REG
);
9292 macro_build (NULL
, jalr
, "mj", PIC_CALL_REG
);
9295 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
9296 if (MIPS_JALR_HINT_P (ep
))
9297 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4, ep
, FALSE
, jalr_reloc
);
9301 * Generate a "lui" instruction.
9304 macro_build_lui (expressionS
*ep
, int regnum
)
9306 gas_assert (! mips_opts
.mips16
);
9308 if (ep
->X_op
!= O_constant
)
9310 gas_assert (ep
->X_op
== O_symbol
);
9311 /* _gp_disp is a special case, used from s_cpload.
9312 __gnu_local_gp is used if mips_no_shared. */
9313 gas_assert (mips_pic
== NO_PIC
9315 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
9316 || (! mips_in_shared
9317 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
9318 "__gnu_local_gp") == 0));
9321 macro_build (ep
, "lui", LUI_FMT
, regnum
, BFD_RELOC_HI16_S
);
9324 /* Generate a sequence of instructions to do a load or store from a constant
9325 offset off of a base register (breg) into/from a target register (treg),
9326 using AT if necessary. */
9328 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
9329 int treg
, int breg
, int dbl
)
9331 gas_assert (ep
->X_op
== O_constant
);
9333 /* Sign-extending 32-bit constants makes their handling easier. */
9335 normalize_constant_expr (ep
);
9337 /* Right now, this routine can only handle signed 32-bit constants. */
9338 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
9339 as_warn (_("operand overflow"));
9341 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
9343 /* Signed 16-bit offset will fit in the op. Easy! */
9344 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
9348 /* 32-bit offset, need multiple instructions and AT, like:
9349 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
9350 addu $tempreg,$tempreg,$breg
9351 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
9352 to handle the complete offset. */
9353 macro_build_lui (ep
, AT
);
9354 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
9355 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
9358 as_bad (_("macro used $at after \".set noat\""));
9363 * Generates code to set the $at register to true (one)
9364 * if reg is less than the immediate expression.
9367 set_at (int reg
, int unsignedp
)
9369 if (imm_expr
.X_add_number
>= -0x8000
9370 && imm_expr
.X_add_number
< 0x8000)
9371 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
9372 AT
, reg
, BFD_RELOC_LO16
);
9375 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
9376 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
9380 /* Count the leading zeroes by performing a binary chop. This is a
9381 bulky bit of source, but performance is a LOT better for the
9382 majority of values than a simple loop to count the bits:
9383 for (lcnt = 0; (lcnt < 32); lcnt++)
9384 if ((v) & (1 << (31 - lcnt)))
9386 However it is not code size friendly, and the gain will drop a bit
9387 on certain cached systems.
9389 #define COUNT_TOP_ZEROES(v) \
9390 (((v) & ~0xffff) == 0 \
9391 ? ((v) & ~0xff) == 0 \
9392 ? ((v) & ~0xf) == 0 \
9393 ? ((v) & ~0x3) == 0 \
9394 ? ((v) & ~0x1) == 0 \
9399 : ((v) & ~0x7) == 0 \
9402 : ((v) & ~0x3f) == 0 \
9403 ? ((v) & ~0x1f) == 0 \
9406 : ((v) & ~0x7f) == 0 \
9409 : ((v) & ~0xfff) == 0 \
9410 ? ((v) & ~0x3ff) == 0 \
9411 ? ((v) & ~0x1ff) == 0 \
9414 : ((v) & ~0x7ff) == 0 \
9417 : ((v) & ~0x3fff) == 0 \
9418 ? ((v) & ~0x1fff) == 0 \
9421 : ((v) & ~0x7fff) == 0 \
9424 : ((v) & ~0xffffff) == 0 \
9425 ? ((v) & ~0xfffff) == 0 \
9426 ? ((v) & ~0x3ffff) == 0 \
9427 ? ((v) & ~0x1ffff) == 0 \
9430 : ((v) & ~0x7ffff) == 0 \
9433 : ((v) & ~0x3fffff) == 0 \
9434 ? ((v) & ~0x1fffff) == 0 \
9437 : ((v) & ~0x7fffff) == 0 \
9440 : ((v) & ~0xfffffff) == 0 \
9441 ? ((v) & ~0x3ffffff) == 0 \
9442 ? ((v) & ~0x1ffffff) == 0 \
9445 : ((v) & ~0x7ffffff) == 0 \
9448 : ((v) & ~0x3fffffff) == 0 \
9449 ? ((v) & ~0x1fffffff) == 0 \
9452 : ((v) & ~0x7fffffff) == 0 \
9457 * This routine generates the least number of instructions necessary to load
9458 * an absolute expression value into a register.
9461 load_register (int reg
, expressionS
*ep
, int dbl
)
9464 expressionS hi32
, lo32
;
9466 if (ep
->X_op
!= O_big
)
9468 gas_assert (ep
->X_op
== O_constant
);
9470 /* Sign-extending 32-bit constants makes their handling easier. */
9472 normalize_constant_expr (ep
);
9474 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
9476 /* We can handle 16 bit signed values with an addiu to
9477 $zero. No need to ever use daddiu here, since $zero and
9478 the result are always correct in 32 bit mode. */
9479 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9482 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
9484 /* We can handle 16 bit unsigned values with an ori to
9486 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9489 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
9491 /* 32 bit values require an lui. */
9492 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9493 if ((ep
->X_add_number
& 0xffff) != 0)
9494 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9499 /* The value is larger than 32 bits. */
9501 if (!dbl
|| GPR_SIZE
== 32)
9505 sprintf_vma (value
, ep
->X_add_number
);
9506 as_bad (_("number (0x%s) larger than 32 bits"), value
);
9507 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9511 if (ep
->X_op
!= O_big
)
9514 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9515 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
9516 hi32
.X_add_number
&= 0xffffffff;
9518 lo32
.X_add_number
&= 0xffffffff;
9522 gas_assert (ep
->X_add_number
> 2);
9523 if (ep
->X_add_number
== 3)
9524 generic_bignum
[3] = 0;
9525 else if (ep
->X_add_number
> 4)
9526 as_bad (_("number larger than 64 bits"));
9527 lo32
.X_op
= O_constant
;
9528 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
9529 hi32
.X_op
= O_constant
;
9530 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
9533 if (hi32
.X_add_number
== 0)
9538 unsigned long hi
, lo
;
9540 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
9542 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
9544 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9547 if (lo32
.X_add_number
& 0x80000000)
9549 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9550 if (lo32
.X_add_number
& 0xffff)
9551 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
9556 /* Check for 16bit shifted constant. We know that hi32 is
9557 non-zero, so start the mask on the first bit of the hi32
9562 unsigned long himask
, lomask
;
9566 himask
= 0xffff >> (32 - shift
);
9567 lomask
= (0xffffU
<< shift
) & 0xffffffff;
9571 himask
= 0xffffU
<< (shift
- 32);
9574 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
9575 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
9579 tmp
.X_op
= O_constant
;
9581 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
9582 | (lo32
.X_add_number
>> shift
));
9584 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
9585 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
9586 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9587 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9592 while (shift
<= (64 - 16));
9594 /* Find the bit number of the lowest one bit, and store the
9595 shifted value in hi/lo. */
9596 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
9597 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
9601 while ((lo
& 1) == 0)
9608 lo
|= (hi
& ((2UL << (bit
- 1)) - 1)) << (32 - bit
);
9615 while ((hi
& 1) == 0)
9624 /* Optimize if the shifted value is a (power of 2) - 1. */
9625 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
9626 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
9628 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
9633 /* This instruction will set the register to be all
9635 tmp
.X_op
= O_constant
;
9636 tmp
.X_add_number
= (offsetT
) -1;
9637 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
9641 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", SHFT_FMT
,
9642 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
9644 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", SHFT_FMT
,
9645 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
9650 /* Sign extend hi32 before calling load_register, because we can
9651 generally get better code when we load a sign extended value. */
9652 if ((hi32
.X_add_number
& 0x80000000) != 0)
9653 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
9654 load_register (reg
, &hi32
, 0);
9657 if ((lo32
.X_add_number
& 0xffff0000) == 0)
9661 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, freg
, 0);
9669 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
9671 macro_build (&lo32
, "lui", LUI_FMT
, reg
, BFD_RELOC_HI16
);
9672 macro_build (NULL
, "dsrl32", SHFT_FMT
, reg
, reg
, 0);
9678 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, freg
, 16);
9682 mid16
.X_add_number
>>= 16;
9683 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9684 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9687 if ((lo32
.X_add_number
& 0xffff) != 0)
9688 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
9692 load_delay_nop (void)
9694 if (!gpr_interlocks
)
9695 macro_build (NULL
, "nop", "");
9698 /* Load an address into a register. */
9701 load_address (int reg
, expressionS
*ep
, int *used_at
)
9703 if (ep
->X_op
!= O_constant
9704 && ep
->X_op
!= O_symbol
)
9706 as_bad (_("expression too complex"));
9707 ep
->X_op
= O_constant
;
9710 if (ep
->X_op
== O_constant
)
9712 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
9716 if (mips_pic
== NO_PIC
)
9718 /* If this is a reference to a GP relative symbol, we want
9719 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
9721 lui $reg,<sym> (BFD_RELOC_HI16_S)
9722 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9723 If we have an addend, we always use the latter form.
9725 With 64bit address space and a usable $at we want
9726 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9727 lui $at,<sym> (BFD_RELOC_HI16_S)
9728 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9729 daddiu $at,<sym> (BFD_RELOC_LO16)
9733 If $at is already in use, we use a path which is suboptimal
9734 on superscalar processors.
9735 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
9736 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
9738 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
9740 daddiu $reg,<sym> (BFD_RELOC_LO16)
9742 For GP relative symbols in 64bit address space we can use
9743 the same sequence as in 32bit address space. */
9744 if (HAVE_64BIT_SYMBOLS
)
9746 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9747 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9749 relax_start (ep
->X_add_symbol
);
9750 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9751 mips_gp_register
, BFD_RELOC_GPREL16
);
9755 if (*used_at
== 0 && mips_opts
.at
)
9757 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9758 macro_build (ep
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16_S
);
9759 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9760 BFD_RELOC_MIPS_HIGHER
);
9761 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
9762 macro_build (NULL
, "dsll32", SHFT_FMT
, reg
, reg
, 0);
9763 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
9768 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_HIGHEST
);
9769 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
9770 BFD_RELOC_MIPS_HIGHER
);
9771 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9772 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
9773 macro_build (NULL
, "dsll", SHFT_FMT
, reg
, reg
, 16);
9774 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
9777 if (mips_relax
.sequence
)
9782 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
9783 && !nopic_need_relax (ep
->X_add_symbol
, 1))
9785 relax_start (ep
->X_add_symbol
);
9786 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
9787 mips_gp_register
, BFD_RELOC_GPREL16
);
9790 macro_build_lui (ep
, reg
);
9791 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
9792 reg
, reg
, BFD_RELOC_LO16
);
9793 if (mips_relax
.sequence
)
9797 else if (!mips_big_got
)
9801 /* If this is a reference to an external symbol, we want
9802 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9804 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9806 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9807 If there is a constant, it must be added in after.
9809 If we have NewABI, we want
9810 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
9811 unless we're referencing a global symbol with a non-zero
9812 offset, in which case cst must be added separately. */
9815 if (ep
->X_add_number
)
9817 ex
.X_add_number
= ep
->X_add_number
;
9818 ep
->X_add_number
= 0;
9819 relax_start (ep
->X_add_symbol
);
9820 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9821 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9822 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9823 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9824 ex
.X_op
= O_constant
;
9825 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9826 reg
, reg
, BFD_RELOC_LO16
);
9827 ep
->X_add_number
= ex
.X_add_number
;
9830 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9831 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
9832 if (mips_relax
.sequence
)
9837 ex
.X_add_number
= ep
->X_add_number
;
9838 ep
->X_add_number
= 0;
9839 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9840 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9842 relax_start (ep
->X_add_symbol
);
9844 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9848 if (ex
.X_add_number
!= 0)
9850 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9851 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9852 ex
.X_op
= O_constant
;
9853 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
9854 reg
, reg
, BFD_RELOC_LO16
);
9858 else if (mips_big_got
)
9862 /* This is the large GOT case. If this is a reference to an
9863 external symbol, we want
9864 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
9866 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
9868 Otherwise, for a reference to a local symbol in old ABI, we want
9869 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
9871 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
9872 If there is a constant, it must be added in after.
9874 In the NewABI, for local symbols, with or without offsets, we want:
9875 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
9876 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
9880 ex
.X_add_number
= ep
->X_add_number
;
9881 ep
->X_add_number
= 0;
9882 relax_start (ep
->X_add_symbol
);
9883 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9884 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9885 reg
, reg
, mips_gp_register
);
9886 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9887 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9888 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9889 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9890 else if (ex
.X_add_number
)
9892 ex
.X_op
= O_constant
;
9893 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9897 ep
->X_add_number
= ex
.X_add_number
;
9899 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9900 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
9901 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9902 BFD_RELOC_MIPS_GOT_OFST
);
9907 ex
.X_add_number
= ep
->X_add_number
;
9908 ep
->X_add_number
= 0;
9909 relax_start (ep
->X_add_symbol
);
9910 macro_build (ep
, "lui", LUI_FMT
, reg
, BFD_RELOC_MIPS_GOT_HI16
);
9911 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
9912 reg
, reg
, mips_gp_register
);
9913 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
9914 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
9916 if (reg_needs_delay (mips_gp_register
))
9918 /* We need a nop before loading from $gp. This special
9919 check is required because the lui which starts the main
9920 instruction stream does not refer to $gp, and so will not
9921 insert the nop which may be required. */
9922 macro_build (NULL
, "nop", "");
9924 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
9925 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9927 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9931 if (ex
.X_add_number
!= 0)
9933 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
9934 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
9935 ex
.X_op
= O_constant
;
9936 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
9944 if (!mips_opts
.at
&& *used_at
== 1)
9945 as_bad (_("macro used $at after \".set noat\""));
9948 /* Move the contents of register SOURCE into register DEST. */
9951 move_register (int dest
, int source
)
9953 /* Prefer to use a 16-bit microMIPS instruction unless the previous
9954 instruction specifically requires a 32-bit one. */
9955 if (mips_opts
.micromips
9956 && !mips_opts
.insn32
9957 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
9958 macro_build (NULL
, "move", "mp,mj", dest
, source
);
9960 macro_build (NULL
, "or", "d,v,t", dest
, source
, 0);
9963 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
9964 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
9965 The two alternatives are:
9967 Global symbol Local symbol
9968 ------------- ------------
9969 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
9971 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
9973 load_got_offset emits the first instruction and add_got_offset
9974 emits the second for a 16-bit offset or add_got_offset_hilo emits
9975 a sequence to add a 32-bit offset using a scratch register. */
9978 load_got_offset (int dest
, expressionS
*local
)
9983 global
.X_add_number
= 0;
9985 relax_start (local
->X_add_symbol
);
9986 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9987 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9989 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
9990 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
9995 add_got_offset (int dest
, expressionS
*local
)
9999 global
.X_op
= O_constant
;
10000 global
.X_op_symbol
= NULL
;
10001 global
.X_add_symbol
= NULL
;
10002 global
.X_add_number
= local
->X_add_number
;
10004 relax_start (local
->X_add_symbol
);
10005 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
10006 dest
, dest
, BFD_RELOC_LO16
);
10008 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
10013 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
10015 expressionS global
;
10016 int hold_mips_optimize
;
10018 global
.X_op
= O_constant
;
10019 global
.X_op_symbol
= NULL
;
10020 global
.X_add_symbol
= NULL
;
10021 global
.X_add_number
= local
->X_add_number
;
10023 relax_start (local
->X_add_symbol
);
10024 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
10026 /* Set mips_optimize around the lui instruction to avoid
10027 inserting an unnecessary nop after the lw. */
10028 hold_mips_optimize
= mips_optimize
;
10030 macro_build_lui (&global
, tmp
);
10031 mips_optimize
= hold_mips_optimize
;
10032 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
10035 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
10038 /* Emit a sequence of instructions to emulate a branch likely operation.
10039 BR is an ordinary branch corresponding to one to be emulated. BRNEG
10040 is its complementing branch with the original condition negated.
10041 CALL is set if the original branch specified the link operation.
10042 EP, FMT, SREG and TREG specify the usual macro_build() parameters.
10044 Code like this is produced in the noreorder mode:
10049 delay slot (executed only if branch taken)
10052 or, if CALL is set:
10057 delay slot (executed only if branch taken)
10060 In the reorder mode the delay slot would be filled with a nop anyway,
10061 so code produced is simply:
10066 This function is used when producing code for the microMIPS ASE that
10067 does not implement branch likely instructions in hardware. */
10070 macro_build_branch_likely (const char *br
, const char *brneg
,
10071 int call
, expressionS
*ep
, const char *fmt
,
10072 unsigned int sreg
, unsigned int treg
)
10074 int noreorder
= mips_opts
.noreorder
;
10077 gas_assert (mips_opts
.micromips
);
10078 start_noreorder ();
10081 micromips_label_expr (&expr1
);
10082 macro_build (&expr1
, brneg
, fmt
, sreg
, treg
);
10083 macro_build (NULL
, "nop", "");
10084 macro_build (ep
, call
? "bal" : "b", "p");
10086 /* Set to true so that append_insn adds a label. */
10087 emit_branch_likely_macro
= TRUE
;
10091 macro_build (ep
, br
, fmt
, sreg
, treg
);
10092 macro_build (NULL
, "nop", "");
10097 /* Emit a coprocessor branch-likely macro specified by TYPE, using CC as
10098 the condition code tested. EP specifies the branch target. */
10101 macro_build_branch_ccl (int type
, expressionS
*ep
, unsigned int cc
)
10103 const int call
= 0;
10128 macro_build_branch_likely (br
, brneg
, call
, ep
, "N,p", cc
, ZERO
);
10131 /* Emit a two-argument branch macro specified by TYPE, using SREG as
10132 the register tested. EP specifies the branch target. */
10135 macro_build_branch_rs (int type
, expressionS
*ep
, unsigned int sreg
)
10137 const char *brneg
= NULL
;
10147 br
= mips_opts
.micromips
? "bgez" : "bgezl";
10151 gas_assert (mips_opts
.micromips
);
10152 br
= mips_opts
.insn32
? "bgezal" : "bgezals";
10160 br
= mips_opts
.micromips
? "bgtz" : "bgtzl";
10167 br
= mips_opts
.micromips
? "blez" : "blezl";
10174 br
= mips_opts
.micromips
? "bltz" : "bltzl";
10178 gas_assert (mips_opts
.micromips
);
10179 br
= mips_opts
.insn32
? "bltzal" : "bltzals";
10186 if (mips_opts
.micromips
&& brneg
)
10187 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,p", sreg
, ZERO
);
10189 macro_build (ep
, br
, "s,p", sreg
);
10192 /* Emit a three-argument branch macro specified by TYPE, using SREG and
10193 TREG as the registers tested. EP specifies the branch target. */
10196 macro_build_branch_rsrt (int type
, expressionS
*ep
,
10197 unsigned int sreg
, unsigned int treg
)
10199 const char *brneg
= NULL
;
10200 const int call
= 0;
10211 br
= mips_opts
.micromips
? "beq" : "beql";
10220 br
= mips_opts
.micromips
? "bne" : "bnel";
10226 if (mips_opts
.micromips
&& brneg
)
10227 macro_build_branch_likely (br
, brneg
, call
, ep
, "s,t,p", sreg
, treg
);
10229 macro_build (ep
, br
, "s,t,p", sreg
, treg
);
10232 /* Return the high part that should be loaded in order to make the low
10233 part of VALUE accessible using an offset of OFFBITS bits. */
10236 offset_high_part (offsetT value
, unsigned int offbits
)
10243 bias
= 1 << (offbits
- 1);
10244 low_mask
= bias
* 2 - 1;
10245 return (value
+ bias
) & ~low_mask
;
10248 /* Return true if the value stored in offset_expr and offset_reloc
10249 fits into a signed offset of OFFBITS bits. RANGE is the maximum
10250 amount that the caller wants to add without inducing overflow
10251 and ALIGN is the known alignment of the value in bytes. */
10254 small_offset_p (unsigned int range
, unsigned int align
, unsigned int offbits
)
10258 /* Accept any relocation operator if overflow isn't a concern. */
10259 if (range
< align
&& *offset_reloc
!= BFD_RELOC_UNUSED
)
10262 /* These relocations are guaranteed not to overflow in correct links. */
10263 if (*offset_reloc
== BFD_RELOC_MIPS_LITERAL
10264 || gprel16_reloc_p (*offset_reloc
))
10267 if (offset_expr
.X_op
== O_constant
10268 && offset_high_part (offset_expr
.X_add_number
, offbits
) == 0
10269 && offset_high_part (offset_expr
.X_add_number
+ range
, offbits
) == 0)
10276 * This routine implements the seemingly endless macro or synthesized
10277 * instructions and addressing modes in the mips assembly language. Many
10278 * of these macros are simple and are similar to each other. These could
10279 * probably be handled by some kind of table or grammar approach instead of
10280 * this verbose method. Others are not simple macros but are more like
10281 * optimizing code generation.
10282 * One interesting optimization is when several store macros appear
10283 * consecutively that would load AT with the upper half of the same address.
10284 * The ensuing load upper instructions are omitted. This implies some kind
10285 * of global optimization. We currently only optimize within a single macro.
10286 * For many of the load and store macros if the address is specified as a
10287 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
10288 * first load register 'at' with zero and use it as the base register. The
10289 * mips assembler simply uses register $zero. Just one tiny optimization
10293 macro (struct mips_cl_insn
*ip
, char *str
)
10295 const struct mips_operand_array
*operands
;
10296 unsigned int breg
, i
;
10297 unsigned int tempreg
;
10300 expressionS label_expr
;
10315 int ll_sc_paired
= 0;
10316 bfd_boolean large_offset
;
10318 int hold_mips_optimize
;
10319 unsigned int align
;
10320 unsigned int op
[MAX_OPERANDS
];
10322 gas_assert (! mips_opts
.mips16
);
10324 operands
= insn_operands (ip
);
10325 for (i
= 0; i
< MAX_OPERANDS
; i
++)
10326 if (operands
->operand
[i
])
10327 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
10331 mask
= ip
->insn_mo
->mask
;
10333 label_expr
.X_op
= O_constant
;
10334 label_expr
.X_op_symbol
= NULL
;
10335 label_expr
.X_add_symbol
= NULL
;
10336 label_expr
.X_add_number
= 0;
10338 expr1
.X_op
= O_constant
;
10339 expr1
.X_op_symbol
= NULL
;
10340 expr1
.X_add_symbol
= NULL
;
10341 expr1
.X_add_number
= 1;
10348 /* Fall through. */
10356 start_noreorder ();
10358 if (mips_opts
.micromips
)
10359 micromips_label_expr (&label_expr
);
10361 label_expr
.X_add_number
= 8;
10362 macro_build (&label_expr
, "bgez", "s,p", op
[1]);
10363 if (op
[0] == op
[1])
10364 macro_build (NULL
, "nop", "");
10366 move_register (op
[0], op
[1]);
10367 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", op
[0], 0, op
[1]);
10368 if (mips_opts
.micromips
)
10369 micromips_add_label ();
10377 if (ISA_IS_R6 (mips_opts
.isa
))
10389 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
10391 if (imm_expr
.X_add_number
>= -0x200
10392 && imm_expr
.X_add_number
< 0x200
10393 && !ISA_IS_R6 (mips_opts
.isa
))
10395 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
10396 (int) imm_expr
.X_add_number
);
10405 if (imm_expr
.X_add_number
>= -0x8000
10406 && imm_expr
.X_add_number
< 0x8000)
10408 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
10413 load_register (AT
, &imm_expr
, dbl
);
10414 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10433 if (imm_expr
.X_add_number
>= 0
10434 && imm_expr
.X_add_number
< 0x10000)
10436 if (mask
!= M_NOR_I
)
10437 macro_build (&imm_expr
, s
, "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
10440 macro_build (&imm_expr
, "ori", "t,r,i",
10441 op
[0], op
[1], BFD_RELOC_LO16
);
10442 macro_build (NULL
, "nor", "d,v,t", op
[0], op
[0], 0);
10448 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
10449 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
10453 switch (imm_expr
.X_add_number
)
10456 macro_build (NULL
, "nop", "");
10459 macro_build (NULL
, "packrl.ph", "d,s,t", op
[0], op
[0], op
[1]);
10463 macro_build (NULL
, "balign", "t,s,2", op
[0], op
[1],
10464 (int) imm_expr
.X_add_number
);
10467 as_bad (_("BALIGN immediate not 0, 1, 2 or 3 (%lu)"),
10468 (unsigned long) imm_expr
.X_add_number
);
10477 gas_assert (mips_opts
.micromips
);
10478 macro_build_branch_ccl (mask
, &offset_expr
,
10479 EXTRACT_OPERAND (1, BCC
, *ip
));
10486 if (imm_expr
.X_add_number
== 0)
10492 load_register (op
[1], &imm_expr
, GPR_SIZE
== 64);
10494 /* Fall through. */
10497 macro_build_branch_rsrt (mask
, &offset_expr
, op
[0], op
[1]);
10502 /* Fall through. */
10505 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[0]);
10506 else if (op
[0] == 0)
10507 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[1]);
10511 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10512 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10513 &offset_expr
, AT
, ZERO
);
10523 macro_build_branch_rs (mask
, &offset_expr
, op
[0]);
10528 /* Fall through. */
10530 /* Check for > max integer. */
10531 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10534 /* Result is always false. */
10536 macro_build (NULL
, "nop", "");
10538 macro_build_branch_rsrt (M_BNEL
, &offset_expr
, ZERO
, ZERO
);
10541 ++imm_expr
.X_add_number
;
10542 /* Fall through. */
10545 if (mask
== M_BGEL_I
)
10547 if (imm_expr
.X_add_number
== 0)
10549 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
,
10550 &offset_expr
, op
[0]);
10553 if (imm_expr
.X_add_number
== 1)
10555 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
,
10556 &offset_expr
, op
[0]);
10559 if (imm_expr
.X_add_number
<= GPR_SMIN
)
10562 /* Result is always true. */
10563 as_warn (_("branch %s is always true"), ip
->insn_mo
->name
);
10564 macro_build (&offset_expr
, "b", "p");
10569 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10570 &offset_expr
, AT
, ZERO
);
10575 /* Fall through. */
10579 else if (op
[0] == 0)
10580 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10581 &offset_expr
, ZERO
, op
[1]);
10585 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10586 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10587 &offset_expr
, AT
, ZERO
);
10593 /* Fall through. */
10597 && imm_expr
.X_add_number
== -1))
10599 ++imm_expr
.X_add_number
;
10600 /* Fall through. */
10603 if (mask
== M_BGEUL_I
)
10605 if (imm_expr
.X_add_number
== 0)
10607 else if (imm_expr
.X_add_number
== 1)
10608 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10609 &offset_expr
, op
[0], ZERO
);
10614 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10615 &offset_expr
, AT
, ZERO
);
10621 /* Fall through. */
10624 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[0]);
10625 else if (op
[0] == 0)
10626 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[1]);
10630 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10631 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10632 &offset_expr
, AT
, ZERO
);
10638 /* Fall through. */
10641 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10642 &offset_expr
, op
[0], ZERO
);
10643 else if (op
[0] == 0)
10648 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10649 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10650 &offset_expr
, AT
, ZERO
);
10656 /* Fall through. */
10659 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10660 else if (op
[0] == 0)
10661 macro_build_branch_rs (likely
? M_BGEZL
: M_BGEZ
, &offset_expr
, op
[1]);
10665 macro_build (NULL
, "slt", "d,v,t", AT
, op
[1], op
[0]);
10666 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10667 &offset_expr
, AT
, ZERO
);
10673 /* Fall through. */
10675 if (imm_expr
.X_add_number
>= GPR_SMAX
)
10677 ++imm_expr
.X_add_number
;
10678 /* Fall through. */
10681 if (mask
== M_BLTL_I
)
10683 if (imm_expr
.X_add_number
== 0)
10684 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10685 else if (imm_expr
.X_add_number
== 1)
10686 macro_build_branch_rs (likely
? M_BLEZL
: M_BLEZ
, &offset_expr
, op
[0]);
10691 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10692 &offset_expr
, AT
, ZERO
);
10698 /* Fall through. */
10701 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10702 &offset_expr
, op
[0], ZERO
);
10703 else if (op
[0] == 0)
10708 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[1], op
[0]);
10709 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10710 &offset_expr
, AT
, ZERO
);
10716 /* Fall through. */
10720 && imm_expr
.X_add_number
== -1))
10722 ++imm_expr
.X_add_number
;
10723 /* Fall through. */
10726 if (mask
== M_BLTUL_I
)
10728 if (imm_expr
.X_add_number
== 0)
10730 else if (imm_expr
.X_add_number
== 1)
10731 macro_build_branch_rsrt (likely
? M_BEQL
: M_BEQ
,
10732 &offset_expr
, op
[0], ZERO
);
10737 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10738 &offset_expr
, AT
, ZERO
);
10744 /* Fall through. */
10747 macro_build_branch_rs (likely
? M_BLTZL
: M_BLTZ
, &offset_expr
, op
[0]);
10748 else if (op
[0] == 0)
10749 macro_build_branch_rs (likely
? M_BGTZL
: M_BGTZ
, &offset_expr
, op
[1]);
10753 macro_build (NULL
, "slt", "d,v,t", AT
, op
[0], op
[1]);
10754 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10755 &offset_expr
, AT
, ZERO
);
10761 /* Fall through. */
10765 else if (op
[0] == 0)
10766 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10767 &offset_expr
, ZERO
, op
[1]);
10771 macro_build (NULL
, "sltu", "d,v,t", AT
, op
[0], op
[1]);
10772 macro_build_branch_rsrt (likely
? M_BNEL
: M_BNE
,
10773 &offset_expr
, AT
, ZERO
);
10779 /* Fall through. */
10785 /* Fall through. */
10791 as_warn (_("divide by zero"));
10793 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10795 macro_build (NULL
, "break", BRK_FMT
, 7);
10799 start_noreorder ();
10802 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10803 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10807 if (mips_opts
.micromips
)
10808 micromips_label_expr (&label_expr
);
10810 label_expr
.X_add_number
= 8;
10811 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10812 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", op
[1], op
[2]);
10813 macro_build (NULL
, "break", BRK_FMT
, 7);
10814 if (mips_opts
.micromips
)
10815 micromips_add_label ();
10817 expr1
.X_add_number
= -1;
10819 load_register (AT
, &expr1
, dbl
);
10820 if (mips_opts
.micromips
)
10821 micromips_label_expr (&label_expr
);
10823 label_expr
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
10824 macro_build (&label_expr
, "bne", "s,t,p", op
[2], AT
);
10827 expr1
.X_add_number
= 1;
10828 load_register (AT
, &expr1
, dbl
);
10829 macro_build (NULL
, "dsll32", SHFT_FMT
, AT
, AT
, 31);
10833 expr1
.X_add_number
= 0x80000000;
10834 macro_build (&expr1
, "lui", LUI_FMT
, AT
, BFD_RELOC_HI16
);
10838 macro_build (NULL
, "teq", TRAP_FMT
, op
[1], AT
, 6);
10839 /* We want to close the noreorder block as soon as possible, so
10840 that later insns are available for delay slot filling. */
10845 if (mips_opts
.micromips
)
10846 micromips_label_expr (&label_expr
);
10848 label_expr
.X_add_number
= 8;
10849 macro_build (&label_expr
, "bne", "s,t,p", op
[1], AT
);
10850 macro_build (NULL
, "nop", "");
10852 /* We want to close the noreorder block as soon as possible, so
10853 that later insns are available for delay slot filling. */
10856 macro_build (NULL
, "break", BRK_FMT
, 6);
10858 if (mips_opts
.micromips
)
10859 micromips_add_label ();
10860 macro_build (NULL
, s
, MFHL_FMT
, op
[0]);
10899 if (imm_expr
.X_add_number
== 0)
10901 as_warn (_("divide by zero"));
10903 macro_build (NULL
, "teq", TRAP_FMT
, ZERO
, ZERO
, 7);
10905 macro_build (NULL
, "break", BRK_FMT
, 7);
10908 if (imm_expr
.X_add_number
== 1)
10910 if (strcmp (s2
, "mflo") == 0)
10911 move_register (op
[0], op
[1]);
10913 move_register (op
[0], ZERO
);
10916 if (imm_expr
.X_add_number
== -1 && s
[strlen (s
) - 1] != 'u')
10918 if (strcmp (s2
, "mflo") == 0)
10919 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", op
[0], op
[1]);
10921 move_register (op
[0], ZERO
);
10926 load_register (AT
, &imm_expr
, dbl
);
10927 macro_build (NULL
, s
, "z,s,t", op
[1], AT
);
10928 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10947 start_noreorder ();
10950 macro_build (NULL
, "teq", TRAP_FMT
, op
[2], ZERO
, 7);
10951 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10952 /* We want to close the noreorder block as soon as possible, so
10953 that later insns are available for delay slot filling. */
10958 if (mips_opts
.micromips
)
10959 micromips_label_expr (&label_expr
);
10961 label_expr
.X_add_number
= 8;
10962 macro_build (&label_expr
, "bne", "s,t,p", op
[2], ZERO
);
10963 macro_build (NULL
, s
, "z,s,t", op
[1], op
[2]);
10965 /* We want to close the noreorder block as soon as possible, so
10966 that later insns are available for delay slot filling. */
10968 macro_build (NULL
, "break", BRK_FMT
, 7);
10969 if (mips_opts
.micromips
)
10970 micromips_add_label ();
10972 macro_build (NULL
, s2
, MFHL_FMT
, op
[0]);
10977 /* Fall through. */
10983 /* Fall through. */
10986 /* Load the address of a symbol into a register. If breg is not
10987 zero, we then add a base register to it. */
10990 if (dbl
&& GPR_SIZE
== 32)
10991 as_warn (_("dla used to load 32-bit register; recommend using la "
10994 if (!dbl
&& HAVE_64BIT_OBJECTS
)
10995 as_warn (_("la used to load 64-bit address; recommend using dla "
10998 if (small_offset_p (0, align
, 16))
11000 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", op
[0], breg
,
11001 -1, offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
11005 if (mips_opts
.at
&& (op
[0] == breg
))
11013 if (offset_expr
.X_op
!= O_symbol
11014 && offset_expr
.X_op
!= O_constant
)
11016 as_bad (_("expression too complex"));
11017 offset_expr
.X_op
= O_constant
;
11020 if (offset_expr
.X_op
== O_constant
)
11021 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
11022 else if (mips_pic
== NO_PIC
)
11024 /* If this is a reference to a GP relative symbol, we want
11025 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
11027 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
11028 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11029 If we have a constant, we need two instructions anyhow,
11030 so we may as well always use the latter form.
11032 With 64bit address space and a usable $at we want
11033 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11034 lui $at,<sym> (BFD_RELOC_HI16_S)
11035 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11036 daddiu $at,<sym> (BFD_RELOC_LO16)
11038 daddu $tempreg,$tempreg,$at
11040 If $at is already in use, we use a path which is suboptimal
11041 on superscalar processors.
11042 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
11043 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
11045 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
11047 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
11049 For GP relative symbols in 64bit address space we can use
11050 the same sequence as in 32bit address space. */
11051 if (HAVE_64BIT_SYMBOLS
)
11053 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11054 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11056 relax_start (offset_expr
.X_add_symbol
);
11057 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11058 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11062 if (used_at
== 0 && mips_opts
.at
)
11064 macro_build (&offset_expr
, "lui", LUI_FMT
,
11065 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11066 macro_build (&offset_expr
, "lui", LUI_FMT
,
11067 AT
, BFD_RELOC_HI16_S
);
11068 macro_build (&offset_expr
, "daddiu", "t,r,j",
11069 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11070 macro_build (&offset_expr
, "daddiu", "t,r,j",
11071 AT
, AT
, BFD_RELOC_LO16
);
11072 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
11073 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
11078 macro_build (&offset_expr
, "lui", LUI_FMT
,
11079 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
11080 macro_build (&offset_expr
, "daddiu", "t,r,j",
11081 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
11082 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11083 macro_build (&offset_expr
, "daddiu", "t,r,j",
11084 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
11085 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
11086 macro_build (&offset_expr
, "daddiu", "t,r,j",
11087 tempreg
, tempreg
, BFD_RELOC_LO16
);
11090 if (mips_relax
.sequence
)
11095 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
11096 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
11098 relax_start (offset_expr
.X_add_symbol
);
11099 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11100 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
11103 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
11104 as_bad (_("offset too large"));
11105 macro_build_lui (&offset_expr
, tempreg
);
11106 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11107 tempreg
, tempreg
, BFD_RELOC_LO16
);
11108 if (mips_relax
.sequence
)
11112 else if (!mips_big_got
&& !HAVE_NEWABI
)
11114 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11116 /* If this is a reference to an external symbol, and there
11117 is no constant, we want
11118 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11119 or for lca or if tempreg is PIC_CALL_REG
11120 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11121 For a local symbol, we want
11122 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11124 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11126 If we have a small constant, and this is a reference to
11127 an external symbol, we want
11128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11130 addiu $tempreg,$tempreg,<constant>
11131 For a local symbol, we want the same instruction
11132 sequence, but we output a BFD_RELOC_LO16 reloc on the
11135 If we have a large constant, and this is a reference to
11136 an external symbol, we want
11137 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11138 lui $at,<hiconstant>
11139 addiu $at,$at,<loconstant>
11140 addu $tempreg,$tempreg,$at
11141 For a local symbol, we want the same instruction
11142 sequence, but we output a BFD_RELOC_LO16 reloc on the
11146 if (offset_expr
.X_add_number
== 0)
11148 if (mips_pic
== SVR4_PIC
11150 && (call
|| tempreg
== PIC_CALL_REG
))
11151 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
11153 relax_start (offset_expr
.X_add_symbol
);
11154 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11155 lw_reloc_type
, mips_gp_register
);
11158 /* We're going to put in an addu instruction using
11159 tempreg, so we may as well insert the nop right
11164 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11165 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
11167 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11168 tempreg
, tempreg
, BFD_RELOC_LO16
);
11170 /* FIXME: If breg == 0, and the next instruction uses
11171 $tempreg, then if this variant case is used an extra
11172 nop will be generated. */
11174 else if (offset_expr
.X_add_number
>= -0x8000
11175 && offset_expr
.X_add_number
< 0x8000)
11177 load_got_offset (tempreg
, &offset_expr
);
11179 add_got_offset (tempreg
, &offset_expr
);
11183 expr1
.X_add_number
= offset_expr
.X_add_number
;
11184 offset_expr
.X_add_number
=
11185 SEXT_16BIT (offset_expr
.X_add_number
);
11186 load_got_offset (tempreg
, &offset_expr
);
11187 offset_expr
.X_add_number
= expr1
.X_add_number
;
11188 /* If we are going to add in a base register, and the
11189 target register and the base register are the same,
11190 then we are using AT as a temporary register. Since
11191 we want to load the constant into AT, we add our
11192 current AT (from the global offset table) and the
11193 register into the register now, and pretend we were
11194 not using a base register. */
11198 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11203 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
11207 else if (!mips_big_got
&& HAVE_NEWABI
)
11209 int add_breg_early
= 0;
11211 /* If this is a reference to an external, and there is no
11212 constant, or local symbol (*), with or without a
11214 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11215 or for lca or if tempreg is PIC_CALL_REG
11216 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11218 If we have a small constant, and this is a reference to
11219 an external symbol, we want
11220 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11221 addiu $tempreg,$tempreg,<constant>
11223 If we have a large constant, and this is a reference to
11224 an external symbol, we want
11225 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
11226 lui $at,<hiconstant>
11227 addiu $at,$at,<loconstant>
11228 addu $tempreg,$tempreg,$at
11230 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
11231 local symbols, even though it introduces an additional
11234 if (offset_expr
.X_add_number
)
11236 expr1
.X_add_number
= offset_expr
.X_add_number
;
11237 offset_expr
.X_add_number
= 0;
11239 relax_start (offset_expr
.X_add_symbol
);
11240 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11241 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11243 if (expr1
.X_add_number
>= -0x8000
11244 && expr1
.X_add_number
< 0x8000)
11246 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11247 tempreg
, tempreg
, BFD_RELOC_LO16
);
11249 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11253 /* If we are going to add in a base register, and the
11254 target register and the base register are the same,
11255 then we are using AT as a temporary register. Since
11256 we want to load the constant into AT, we add our
11257 current AT (from the global offset table) and the
11258 register into the register now, and pretend we were
11259 not using a base register. */
11264 gas_assert (tempreg
== AT
);
11265 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11268 add_breg_early
= 1;
11271 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11272 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11278 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11281 offset_expr
.X_add_number
= expr1
.X_add_number
;
11283 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11284 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11285 if (add_breg_early
)
11287 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11288 op
[0], tempreg
, breg
);
11294 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
11296 relax_start (offset_expr
.X_add_symbol
);
11297 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11298 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
11300 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11301 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11306 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11307 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
11310 else if (mips_big_got
&& !HAVE_NEWABI
)
11313 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11314 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11315 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
11317 /* This is the large GOT case. If this is a reference to an
11318 external symbol, and there is no constant, we want
11319 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11320 addu $tempreg,$tempreg,$gp
11321 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11322 or for lca or if tempreg is PIC_CALL_REG
11323 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11324 addu $tempreg,$tempreg,$gp
11325 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11326 For a local symbol, we want
11327 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11329 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
11331 If we have a small constant, and this is a reference to
11332 an external symbol, we want
11333 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11334 addu $tempreg,$tempreg,$gp
11335 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11337 addiu $tempreg,$tempreg,<constant>
11338 For a local symbol, we want
11339 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11341 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
11343 If we have a large constant, and this is a reference to
11344 an external symbol, we want
11345 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11346 addu $tempreg,$tempreg,$gp
11347 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11348 lui $at,<hiconstant>
11349 addiu $at,$at,<loconstant>
11350 addu $tempreg,$tempreg,$at
11351 For a local symbol, we want
11352 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11353 lui $at,<hiconstant>
11354 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
11355 addu $tempreg,$tempreg,$at
11358 expr1
.X_add_number
= offset_expr
.X_add_number
;
11359 offset_expr
.X_add_number
= 0;
11360 relax_start (offset_expr
.X_add_symbol
);
11361 gpdelay
= reg_needs_delay (mips_gp_register
);
11362 if (expr1
.X_add_number
== 0 && breg
== 0
11363 && (call
|| tempreg
== PIC_CALL_REG
))
11365 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11366 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11368 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11369 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11370 tempreg
, tempreg
, mips_gp_register
);
11371 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11372 tempreg
, lw_reloc_type
, tempreg
);
11373 if (expr1
.X_add_number
== 0)
11377 /* We're going to put in an addu instruction using
11378 tempreg, so we may as well insert the nop right
11383 else if (expr1
.X_add_number
>= -0x8000
11384 && expr1
.X_add_number
< 0x8000)
11387 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11388 tempreg
, tempreg
, BFD_RELOC_LO16
);
11394 /* If we are going to add in a base register, and the
11395 target register and the base register are the same,
11396 then we are using AT as a temporary register. Since
11397 we want to load the constant into AT, we add our
11398 current AT (from the global offset table) and the
11399 register into the register now, and pretend we were
11400 not using a base register. */
11405 gas_assert (tempreg
== AT
);
11407 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11412 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11413 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11417 offset_expr
.X_add_number
= SEXT_16BIT (expr1
.X_add_number
);
11422 /* This is needed because this instruction uses $gp, but
11423 the first instruction on the main stream does not. */
11424 macro_build (NULL
, "nop", "");
11427 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11428 local_reloc_type
, mips_gp_register
);
11429 if (expr1
.X_add_number
>= -0x8000
11430 && expr1
.X_add_number
< 0x8000)
11433 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11434 tempreg
, tempreg
, BFD_RELOC_LO16
);
11435 /* FIXME: If add_number is 0, and there was no base
11436 register, the external symbol case ended with a load,
11437 so if the symbol turns out to not be external, and
11438 the next instruction uses tempreg, an unnecessary nop
11439 will be inserted. */
11445 /* We must add in the base register now, as in the
11446 external symbol case. */
11447 gas_assert (tempreg
== AT
);
11449 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11452 /* We set breg to 0 because we have arranged to add
11453 it in in both cases. */
11457 macro_build_lui (&expr1
, AT
);
11458 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11459 AT
, AT
, BFD_RELOC_LO16
);
11460 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11461 tempreg
, tempreg
, AT
);
11466 else if (mips_big_got
&& HAVE_NEWABI
)
11468 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
11469 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
11470 int add_breg_early
= 0;
11472 /* This is the large GOT case. If this is a reference to an
11473 external symbol, and there is no constant, we want
11474 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11475 add $tempreg,$tempreg,$gp
11476 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11477 or for lca or if tempreg is PIC_CALL_REG
11478 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11479 add $tempreg,$tempreg,$gp
11480 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
11482 If we have a small constant, and this is a reference to
11483 an external symbol, we want
11484 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11485 add $tempreg,$tempreg,$gp
11486 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11487 addi $tempreg,$tempreg,<constant>
11489 If we have a large constant, and this is a reference to
11490 an external symbol, we want
11491 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
11492 addu $tempreg,$tempreg,$gp
11493 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
11494 lui $at,<hiconstant>
11495 addi $at,$at,<loconstant>
11496 add $tempreg,$tempreg,$at
11498 If we have NewABI, and we know it's a local symbol, we want
11499 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
11500 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
11501 otherwise we have to resort to GOT_HI16/GOT_LO16. */
11503 relax_start (offset_expr
.X_add_symbol
);
11505 expr1
.X_add_number
= offset_expr
.X_add_number
;
11506 offset_expr
.X_add_number
= 0;
11508 if (expr1
.X_add_number
== 0 && breg
== 0
11509 && (call
|| tempreg
== PIC_CALL_REG
))
11511 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
11512 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
11514 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
, lui_reloc_type
);
11515 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11516 tempreg
, tempreg
, mips_gp_register
);
11517 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11518 tempreg
, lw_reloc_type
, tempreg
);
11520 if (expr1
.X_add_number
== 0)
11522 else if (expr1
.X_add_number
>= -0x8000
11523 && expr1
.X_add_number
< 0x8000)
11525 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
11526 tempreg
, tempreg
, BFD_RELOC_LO16
);
11528 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
11532 /* If we are going to add in a base register, and the
11533 target register and the base register are the same,
11534 then we are using AT as a temporary register. Since
11535 we want to load the constant into AT, we add our
11536 current AT (from the global offset table) and the
11537 register into the register now, and pretend we were
11538 not using a base register. */
11543 gas_assert (tempreg
== AT
);
11544 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11547 add_breg_early
= 1;
11550 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
11551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
11556 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
11559 offset_expr
.X_add_number
= expr1
.X_add_number
;
11560 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
11561 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
11562 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
11563 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
11564 if (add_breg_early
)
11566 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
11567 op
[0], tempreg
, breg
);
11577 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", op
[0], tempreg
, breg
);
11581 gas_assert (!mips_opts
.micromips
);
11582 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x01);
11586 gas_assert (!mips_opts
.micromips
);
11587 macro_build (NULL
, "c2", "C", 0x02);
11591 gas_assert (!mips_opts
.micromips
);
11592 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x02);
11596 gas_assert (!mips_opts
.micromips
);
11597 macro_build (NULL
, "c2", "C", 3);
11601 gas_assert (!mips_opts
.micromips
);
11602 macro_build (NULL
, "c2", "C", (op
[0] << 16) | 0x03);
11606 /* The j instruction may not be used in PIC code, since it
11607 requires an absolute address. We convert it to a b
11609 if (mips_pic
== NO_PIC
)
11610 macro_build (&offset_expr
, "j", "a");
11612 macro_build (&offset_expr
, "b", "p");
11615 /* The jal instructions must be handled as macros because when
11616 generating PIC code they expand to multi-instruction
11617 sequences. Normally they are simple instructions. */
11621 /* Fall through. */
11623 gas_assert (mips_opts
.micromips
);
11624 if (mips_opts
.insn32
)
11626 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11634 /* Fall through. */
11637 if (mips_pic
== NO_PIC
)
11639 s
= jals
? "jalrs" : "jalr";
11640 if (mips_opts
.micromips
11641 && !mips_opts
.insn32
11643 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11644 macro_build (NULL
, s
, "mj", op
[1]);
11646 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11650 int cprestore
= (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
11651 && mips_cprestore_offset
>= 0);
11653 if (op
[1] != PIC_CALL_REG
)
11654 as_warn (_("MIPS PIC call to register other than $25"));
11656 s
= ((mips_opts
.micromips
11657 && !mips_opts
.insn32
11658 && (!mips_opts
.noreorder
|| cprestore
))
11659 ? "jalrs" : "jalr");
11660 if (mips_opts
.micromips
11661 && !mips_opts
.insn32
11663 && !(history
[0].insn_mo
->pinfo2
& INSN2_BRANCH_DELAY_32BIT
))
11664 macro_build (NULL
, s
, "mj", op
[1]);
11666 macro_build (NULL
, s
, JALR_FMT
, op
[0], op
[1]);
11667 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
11669 if (mips_cprestore_offset
< 0)
11670 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11673 if (!mips_frame_reg_valid
)
11675 as_warn (_("no .frame pseudo-op used in PIC code"));
11676 /* Quiet this warning. */
11677 mips_frame_reg_valid
= 1;
11679 if (!mips_cprestore_valid
)
11681 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11682 /* Quiet this warning. */
11683 mips_cprestore_valid
= 1;
11685 if (mips_opts
.noreorder
)
11686 macro_build (NULL
, "nop", "");
11687 expr1
.X_add_number
= mips_cprestore_offset
;
11688 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11691 HAVE_64BIT_ADDRESSES
);
11699 gas_assert (mips_opts
.micromips
);
11700 if (mips_opts
.insn32
)
11702 as_bad (_("opcode not supported in the `insn32' mode `%s'"), str
);
11706 /* Fall through. */
11708 if (mips_pic
== NO_PIC
)
11709 macro_build (&offset_expr
, jals
? "jals" : "jal", "a");
11710 else if (mips_pic
== SVR4_PIC
)
11712 /* If this is a reference to an external symbol, and we are
11713 using a small GOT, we want
11714 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
11718 lw $gp,cprestore($sp)
11719 The cprestore value is set using the .cprestore
11720 pseudo-op. If we are using a big GOT, we want
11721 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
11723 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
11727 lw $gp,cprestore($sp)
11728 If the symbol is not external, we want
11729 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
11731 addiu $25,$25,<sym> (BFD_RELOC_LO16)
11734 lw $gp,cprestore($sp)
11736 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
11737 sequences above, minus nops, unless the symbol is local,
11738 which enables us to use GOT_PAGE/GOT_OFST (big got) or
11744 relax_start (offset_expr
.X_add_symbol
);
11745 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11746 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11749 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11750 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
11756 relax_start (offset_expr
.X_add_symbol
);
11757 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11758 BFD_RELOC_MIPS_CALL_HI16
);
11759 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11760 PIC_CALL_REG
, mips_gp_register
);
11761 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11762 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11765 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11766 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
11768 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11769 PIC_CALL_REG
, PIC_CALL_REG
,
11770 BFD_RELOC_MIPS_GOT_OFST
);
11774 macro_build_jalr (&offset_expr
, 0);
11778 relax_start (offset_expr
.X_add_symbol
);
11781 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11782 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
11791 gpdelay
= reg_needs_delay (mips_gp_register
);
11792 macro_build (&offset_expr
, "lui", LUI_FMT
, PIC_CALL_REG
,
11793 BFD_RELOC_MIPS_CALL_HI16
);
11794 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
11795 PIC_CALL_REG
, mips_gp_register
);
11796 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11797 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
11802 macro_build (NULL
, "nop", "");
11804 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
11805 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
11808 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
11809 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
11811 macro_build_jalr (&offset_expr
, mips_cprestore_offset
>= 0);
11813 if (mips_cprestore_offset
< 0)
11814 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11817 if (!mips_frame_reg_valid
)
11819 as_warn (_("no .frame pseudo-op used in PIC code"));
11820 /* Quiet this warning. */
11821 mips_frame_reg_valid
= 1;
11823 if (!mips_cprestore_valid
)
11825 as_warn (_("no .cprestore pseudo-op used in PIC code"));
11826 /* Quiet this warning. */
11827 mips_cprestore_valid
= 1;
11829 if (mips_opts
.noreorder
)
11830 macro_build (NULL
, "nop", "");
11831 expr1
.X_add_number
= mips_cprestore_offset
;
11832 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
11835 HAVE_64BIT_ADDRESSES
);
11839 else if (mips_pic
== VXWORKS_PIC
)
11840 as_bad (_("non-PIC jump used in PIC library"));
11947 gas_assert (!mips_opts
.micromips
);
11950 /* Itbl support may require additional care here. */
11956 /* Itbl support may require additional care here. */
11962 offbits
= (mips_opts
.micromips
? 12
11963 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11965 /* Itbl support may require additional care here. */
11969 gas_assert (!mips_opts
.micromips
);
11972 /* Itbl support may require additional care here. */
11978 offbits
= (mips_opts
.micromips
? 12 : 16);
11983 offbits
= (mips_opts
.micromips
? 12 : 16);
11988 /* Itbl support may require additional care here. */
11994 offbits
= (mips_opts
.micromips
? 12
11995 : ISA_IS_R6 (mips_opts
.isa
) ? 11
11997 /* Itbl support may require additional care here. */
12003 /* Itbl support may require additional care here. */
12009 /* Itbl support may require additional care here. */
12015 offbits
= (mips_opts
.micromips
? 12 : 16);
12020 offbits
= (mips_opts
.micromips
? 12 : 16);
12025 offbits
= (mips_opts
.micromips
? 12
12026 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12032 offbits
= (mips_opts
.micromips
? 12
12033 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12039 offbits
= (mips_opts
.micromips
? 12 : 16);
12042 gas_assert (mips_opts
.micromips
);
12049 gas_assert (mips_opts
.micromips
);
12058 s
= ip
->insn_mo
->name
;
12064 gas_assert (mips_opts
.micromips
);
12070 gas_assert (mips_opts
.micromips
);
12077 /* Try to use one the the load registers to compute the base address.
12078 We don't want to use $0 as tempreg. */
12081 if ((op
[0] == ZERO
&& op
[3] == op
[1])
12082 || (op
[1] == ZERO
&& op
[3] == op
[0])
12083 || (op
[0] == ZERO
&& op
[1] == ZERO
))
12085 else if (op
[0] != op
[3] && op
[0] != ZERO
)
12092 if (op
[2] == op
[0] + lp
|| op
[0] + lp
== ZERO
)
12095 tempreg
= op
[0] + lp
;
12112 gas_assert (!mips_opts
.micromips
);
12115 /* Itbl support may require additional care here. */
12121 /* Itbl support may require additional care here. */
12127 offbits
= (mips_opts
.micromips
? 12
12128 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12130 /* Itbl support may require additional care here. */
12134 gas_assert (!mips_opts
.micromips
);
12137 /* Itbl support may require additional care here. */
12143 offbits
= (mips_opts
.micromips
? 12 : 16);
12148 offbits
= (mips_opts
.micromips
? 12 : 16);
12153 offbits
= (mips_opts
.micromips
? 12
12154 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12160 offbits
= (mips_opts
.micromips
? 12
12161 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12167 s
= ip
->insn_mo
->name
;
12174 fmt
= (mips_opts
.micromips
? "k,~(b)"
12175 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12177 offbits
= (mips_opts
.micromips
? 12
12178 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12188 fmt
= (mips_opts
.micromips
? "k,~(b)"
12189 : ISA_IS_R6 (mips_opts
.isa
) ? "k,+j(b)"
12191 offbits
= (mips_opts
.micromips
? 12
12192 : ISA_IS_R6 (mips_opts
.isa
) ? 9
12204 /* Itbl support may require additional care here. */
12209 offbits
= (mips_opts
.micromips
? 12
12210 : ISA_IS_R6 (mips_opts
.isa
) ? 11
12212 /* Itbl support may require additional care here. */
12218 /* Itbl support may require additional care here. */
12222 gas_assert (!mips_opts
.micromips
);
12225 /* Itbl support may require additional care here. */
12231 offbits
= (mips_opts
.micromips
? 12 : 16);
12236 offbits
= (mips_opts
.micromips
? 12 : 16);
12239 gas_assert (mips_opts
.micromips
);
12245 gas_assert (mips_opts
.micromips
);
12251 gas_assert (mips_opts
.micromips
);
12257 gas_assert (mips_opts
.micromips
);
12265 breg
= ll_sc_paired
? op
[3] : op
[2];
12266 if (small_offset_p (0, align
, 16))
12268 /* The first case exists for M_LD_AB and M_SD_AB, which are
12269 macros for o32 but which should act like normal instructions
12272 macro_build (&offset_expr
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12273 offset_reloc
[1], offset_reloc
[2], breg
);
12274 else if (small_offset_p (0, align
, offbits
))
12279 macro_build (NULL
, s
, fmt
, op
[0], op
[1], breg
);
12281 macro_build (NULL
, s
, fmt
, op
[0], breg
);
12284 macro_build (NULL
, s
, fmt
, op
[0],
12285 (int) offset_expr
.X_add_number
, breg
);
12291 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
12292 tempreg
, breg
, -1, offset_reloc
[0],
12293 offset_reloc
[1], offset_reloc
[2]);
12297 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12299 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12302 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12310 if (offset_expr
.X_op
!= O_constant
12311 && offset_expr
.X_op
!= O_symbol
)
12313 as_bad (_("expression too complex"));
12314 offset_expr
.X_op
= O_constant
;
12317 if (HAVE_32BIT_ADDRESSES
12318 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
12322 sprintf_vma (value
, offset_expr
.X_add_number
);
12323 as_bad (_("number (0x%s) larger than 32 bits"), value
);
12326 /* A constant expression in PIC code can be handled just as it
12327 is in non PIC code. */
12328 if (offset_expr
.X_op
== O_constant
)
12330 expr1
.X_add_number
= offset_high_part (offset_expr
.X_add_number
,
12331 offbits
== 0 ? 16 : offbits
);
12332 offset_expr
.X_add_number
-= expr1
.X_add_number
;
12334 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
12336 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12337 tempreg
, tempreg
, breg
);
12340 if (offset_expr
.X_add_number
!= 0)
12341 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
12342 "t,r,j", tempreg
, tempreg
, BFD_RELOC_LO16
);
12344 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12346 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12348 else if (offbits
== 16)
12349 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12351 macro_build (NULL
, s
, fmt
, op
[0],
12352 (int) offset_expr
.X_add_number
, tempreg
);
12354 else if (offbits
!= 16)
12356 /* The offset field is too narrow to be used for a low-part
12357 relocation, so load the whole address into the auxiliary
12359 load_address (tempreg
, &offset_expr
, &used_at
);
12361 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12362 tempreg
, tempreg
, breg
);
12366 macro_build (NULL
, s
, fmt
, op
[0], op
[1], tempreg
);
12368 macro_build (NULL
, s
, fmt
, op
[0], tempreg
);
12371 macro_build (NULL
, s
, fmt
, op
[0], 0, tempreg
);
12373 else if (mips_pic
== NO_PIC
)
12375 /* If this is a reference to a GP relative symbol, and there
12376 is no base register, we want
12377 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
12378 Otherwise, if there is no base register, we want
12379 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12380 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12381 If we have a constant, we need two instructions anyhow,
12382 so we always use the latter form.
12384 If we have a base register, and this is a reference to a
12385 GP relative symbol, we want
12386 addu $tempreg,$breg,$gp
12387 <op> op[0],<sym>($tempreg) (BFD_RELOC_GPREL16)
12389 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
12390 addu $tempreg,$tempreg,$breg
12391 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12392 With a constant we always use the latter case.
12394 With 64bit address space and no base register and $at usable,
12396 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12397 lui $at,<sym> (BFD_RELOC_HI16_S)
12398 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12401 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12402 If we have a base register, we want
12403 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12404 lui $at,<sym> (BFD_RELOC_HI16_S)
12405 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12409 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12411 Without $at we can't generate the optimal path for superscalar
12412 processors here since this would require two temporary registers.
12413 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12414 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12416 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12418 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12419 If we have a base register, we want
12420 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
12421 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
12423 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
12425 daddu $tempreg,$tempreg,$breg
12426 <op> op[0],<sym>($tempreg) (BFD_RELOC_LO16)
12428 For GP relative symbols in 64bit address space we can use
12429 the same sequence as in 32bit address space. */
12430 if (HAVE_64BIT_SYMBOLS
)
12432 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12433 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12435 relax_start (offset_expr
.X_add_symbol
);
12438 macro_build (&offset_expr
, s
, fmt
, op
[0],
12439 BFD_RELOC_GPREL16
, mips_gp_register
);
12443 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12444 tempreg
, breg
, mips_gp_register
);
12445 macro_build (&offset_expr
, s
, fmt
, op
[0],
12446 BFD_RELOC_GPREL16
, tempreg
);
12451 if (used_at
== 0 && mips_opts
.at
)
12453 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12454 BFD_RELOC_MIPS_HIGHEST
);
12455 macro_build (&offset_expr
, "lui", LUI_FMT
, AT
,
12457 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12458 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12460 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
12461 macro_build (NULL
, "dsll32", SHFT_FMT
, tempreg
, tempreg
, 0);
12462 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
12463 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_LO16
,
12469 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12470 BFD_RELOC_MIPS_HIGHEST
);
12471 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12472 tempreg
, BFD_RELOC_MIPS_HIGHER
);
12473 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12474 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
12475 tempreg
, BFD_RELOC_HI16_S
);
12476 macro_build (NULL
, "dsll", SHFT_FMT
, tempreg
, tempreg
, 16);
12478 macro_build (NULL
, "daddu", "d,v,t",
12479 tempreg
, tempreg
, breg
);
12480 macro_build (&offset_expr
, s
, fmt
, op
[0],
12481 BFD_RELOC_LO16
, tempreg
);
12484 if (mips_relax
.sequence
)
12491 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12492 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12494 relax_start (offset_expr
.X_add_symbol
);
12495 macro_build (&offset_expr
, s
, fmt
, op
[0], BFD_RELOC_GPREL16
,
12499 macro_build_lui (&offset_expr
, tempreg
);
12500 macro_build (&offset_expr
, s
, fmt
, op
[0],
12501 BFD_RELOC_LO16
, tempreg
);
12502 if (mips_relax
.sequence
)
12507 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
12508 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
12510 relax_start (offset_expr
.X_add_symbol
);
12511 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12512 tempreg
, breg
, mips_gp_register
);
12513 macro_build (&offset_expr
, s
, fmt
, op
[0],
12514 BFD_RELOC_GPREL16
, tempreg
);
12517 macro_build_lui (&offset_expr
, tempreg
);
12518 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12519 tempreg
, tempreg
, breg
);
12520 macro_build (&offset_expr
, s
, fmt
, op
[0],
12521 BFD_RELOC_LO16
, tempreg
);
12522 if (mips_relax
.sequence
)
12526 else if (!mips_big_got
)
12528 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
12530 /* If this is a reference to an external symbol, we want
12531 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12533 <op> op[0],0($tempreg)
12535 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12537 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12538 <op> op[0],0($tempreg)
12540 For NewABI, we want
12541 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12542 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
12544 If there is a base register, we add it to $tempreg before
12545 the <op>. If there is a constant, we stick it in the
12546 <op> instruction. We don't handle constants larger than
12547 16 bits, because we have no way to load the upper 16 bits
12548 (actually, we could handle them for the subset of cases
12549 in which we are not using $at). */
12550 gas_assert (offset_expr
.X_op
== O_symbol
);
12553 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12554 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12556 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12557 tempreg
, tempreg
, breg
);
12558 macro_build (&offset_expr
, s
, fmt
, op
[0],
12559 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12562 expr1
.X_add_number
= offset_expr
.X_add_number
;
12563 offset_expr
.X_add_number
= 0;
12564 if (expr1
.X_add_number
< -0x8000
12565 || expr1
.X_add_number
>= 0x8000)
12566 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12567 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12568 lw_reloc_type
, mips_gp_register
);
12570 relax_start (offset_expr
.X_add_symbol
);
12572 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12573 tempreg
, BFD_RELOC_LO16
);
12576 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12577 tempreg
, tempreg
, breg
);
12578 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12580 else if (mips_big_got
&& !HAVE_NEWABI
)
12584 /* If this is a reference to an external symbol, we want
12585 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12586 addu $tempreg,$tempreg,$gp
12587 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12588 <op> op[0],0($tempreg)
12590 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
12592 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
12593 <op> op[0],0($tempreg)
12594 If there is a base register, we add it to $tempreg before
12595 the <op>. If there is a constant, we stick it in the
12596 <op> instruction. We don't handle constants larger than
12597 16 bits, because we have no way to load the upper 16 bits
12598 (actually, we could handle them for the subset of cases
12599 in which we are not using $at). */
12600 gas_assert (offset_expr
.X_op
== O_symbol
);
12601 expr1
.X_add_number
= offset_expr
.X_add_number
;
12602 offset_expr
.X_add_number
= 0;
12603 if (expr1
.X_add_number
< -0x8000
12604 || expr1
.X_add_number
>= 0x8000)
12605 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12606 gpdelay
= reg_needs_delay (mips_gp_register
);
12607 relax_start (offset_expr
.X_add_symbol
);
12608 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12609 BFD_RELOC_MIPS_GOT_HI16
);
12610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12612 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12613 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12616 macro_build (NULL
, "nop", "");
12617 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12618 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12620 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
12621 tempreg
, BFD_RELOC_LO16
);
12625 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12626 tempreg
, tempreg
, breg
);
12627 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12629 else if (mips_big_got
&& HAVE_NEWABI
)
12631 /* If this is a reference to an external symbol, we want
12632 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
12633 add $tempreg,$tempreg,$gp
12634 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
12635 <op> op[0],<ofst>($tempreg)
12636 Otherwise, for local symbols, we want:
12637 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
12638 <op> op[0],<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
12639 gas_assert (offset_expr
.X_op
== O_symbol
);
12640 expr1
.X_add_number
= offset_expr
.X_add_number
;
12641 offset_expr
.X_add_number
= 0;
12642 if (expr1
.X_add_number
< -0x8000
12643 || expr1
.X_add_number
>= 0x8000)
12644 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
12645 relax_start (offset_expr
.X_add_symbol
);
12646 macro_build (&offset_expr
, "lui", LUI_FMT
, tempreg
,
12647 BFD_RELOC_MIPS_GOT_HI16
);
12648 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
12650 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12651 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
12653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12654 tempreg
, tempreg
, breg
);
12655 macro_build (&expr1
, s
, fmt
, op
[0], BFD_RELOC_LO16
, tempreg
);
12658 offset_expr
.X_add_number
= expr1
.X_add_number
;
12659 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
12660 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
12662 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
12663 tempreg
, tempreg
, breg
);
12664 macro_build (&offset_expr
, s
, fmt
, op
[0],
12665 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
12674 gas_assert (mips_opts
.micromips
);
12675 gas_assert (mips_opts
.insn32
);
12676 start_noreorder ();
12677 macro_build (NULL
, "jr", "s", RA
);
12678 expr1
.X_add_number
= op
[0] << 2;
12679 macro_build (&expr1
, "addiu", "t,r,j", SP
, SP
, BFD_RELOC_LO16
);
12684 gas_assert (mips_opts
.micromips
);
12685 gas_assert (mips_opts
.insn32
);
12686 macro_build (NULL
, "jr", "s", op
[0]);
12687 if (mips_opts
.noreorder
)
12688 macro_build (NULL
, "nop", "");
12693 load_register (op
[0], &imm_expr
, 0);
12697 load_register (op
[0], &imm_expr
, 1);
12701 if (imm_expr
.X_op
== O_constant
)
12704 load_register (AT
, &imm_expr
, 0);
12705 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12710 gas_assert (imm_expr
.X_op
== O_absent
12711 && offset_expr
.X_op
== O_symbol
12712 && strcmp (segment_name (S_GET_SEGMENT
12713 (offset_expr
.X_add_symbol
)),
12715 && offset_expr
.X_add_number
== 0);
12716 macro_build (&offset_expr
, "lwc1", "T,o(b)", op
[0],
12717 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
12722 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
12723 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
12724 order 32 bits of the value and the low order 32 bits are either
12725 zero or in OFFSET_EXPR. */
12726 if (imm_expr
.X_op
== O_constant
)
12728 if (GPR_SIZE
== 64)
12729 load_register (op
[0], &imm_expr
, 1);
12734 if (target_big_endian
)
12746 load_register (hreg
, &imm_expr
, 0);
12749 if (offset_expr
.X_op
== O_absent
)
12750 move_register (lreg
, 0);
12753 gas_assert (offset_expr
.X_op
== O_constant
);
12754 load_register (lreg
, &offset_expr
, 0);
12760 gas_assert (imm_expr
.X_op
== O_absent
);
12762 /* We know that sym is in the .rdata section. First we get the
12763 upper 16 bits of the address. */
12764 if (mips_pic
== NO_PIC
)
12766 macro_build_lui (&offset_expr
, AT
);
12771 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12772 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12776 /* Now we load the register(s). */
12777 if (GPR_SIZE
== 64)
12780 macro_build (&offset_expr
, "ld", "t,o(b)", op
[0],
12781 BFD_RELOC_LO16
, AT
);
12786 macro_build (&offset_expr
, "lw", "t,o(b)", op
[0],
12787 BFD_RELOC_LO16
, AT
);
12790 /* FIXME: How in the world do we deal with the possible
12792 offset_expr
.X_add_number
+= 4;
12793 macro_build (&offset_expr
, "lw", "t,o(b)",
12794 op
[0] + 1, BFD_RELOC_LO16
, AT
);
12800 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
12801 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
12802 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
12803 the value and the low order 32 bits are either zero or in
12805 if (imm_expr
.X_op
== O_constant
)
12808 if (((FPR_SIZE
== 64 && GPR_SIZE
== 64)
12809 || !ISA_HAS_MXHC1 (mips_opts
.isa
))
12810 && imm_expr
.X_add_number
!= 0)
12814 load_register (AT
, &imm_expr
, FPR_SIZE
== 64);
12816 if (FPR_SIZE
== 64 && GPR_SIZE
== 64)
12817 macro_build (NULL
, "dmtc1", "t,S", tempreg
, op
[0]);
12820 if (!ISA_HAS_MXHC1 (mips_opts
.isa
))
12822 if (FPR_SIZE
!= 32)
12823 as_bad (_("Unable to generate `%s' compliant code "
12825 (FPR_SIZE
== 64) ? "fp64" : "fpxx");
12827 macro_build (NULL
, "mtc1", "t,G", tempreg
, op
[0] + 1);
12829 if (offset_expr
.X_op
== O_absent
)
12830 macro_build (NULL
, "mtc1", "t,G", 0, op
[0]);
12833 gas_assert (offset_expr
.X_op
== O_constant
);
12834 load_register (AT
, &offset_expr
, 0);
12835 macro_build (NULL
, "mtc1", "t,G", AT
, op
[0]);
12837 if (ISA_HAS_MXHC1 (mips_opts
.isa
))
12839 if (imm_expr
.X_add_number
!= 0)
12843 load_register (AT
, &imm_expr
, 0);
12845 macro_build (NULL
, "mthc1", "t,G", tempreg
, op
[0]);
12851 gas_assert (imm_expr
.X_op
== O_absent
12852 && offset_expr
.X_op
== O_symbol
12853 && offset_expr
.X_add_number
== 0);
12854 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
12855 if (strcmp (s
, ".lit8") == 0)
12857 op
[2] = mips_gp_register
;
12858 offset_reloc
[0] = BFD_RELOC_MIPS_LITERAL
;
12859 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12860 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12864 gas_assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
12866 if (mips_pic
!= NO_PIC
)
12867 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
12868 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
12871 /* FIXME: This won't work for a 64 bit address. */
12872 macro_build_lui (&offset_expr
, AT
);
12876 offset_reloc
[0] = BFD_RELOC_LO16
;
12877 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12878 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12881 /* Fall through. */
12884 /* The MIPS assembler seems to check for X_add_number not
12885 being double aligned and generating:
12888 addiu at,at,%lo(foo+1)
12891 But, the resulting address is the same after relocation so why
12892 generate the extra instruction? */
12893 /* Itbl support may require additional care here. */
12896 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12905 gas_assert (!mips_opts
.micromips
);
12906 /* Itbl support may require additional care here. */
12909 if (CPU_HAS_LDC1_SDC1 (mips_opts
.arch
))
12929 if (GPR_SIZE
== 64)
12939 if (GPR_SIZE
== 64)
12947 /* Even on a big endian machine $fn comes before $fn+1. We have
12948 to adjust when loading from memory. We set coproc if we must
12949 load $fn+1 first. */
12950 /* Itbl support may require additional care here. */
12951 if (!target_big_endian
)
12955 if (small_offset_p (0, align
, 16))
12958 if (!small_offset_p (4, align
, 16))
12960 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
, breg
,
12961 -1, offset_reloc
[0], offset_reloc
[1],
12963 expr1
.X_add_number
= 0;
12967 offset_reloc
[0] = BFD_RELOC_LO16
;
12968 offset_reloc
[1] = BFD_RELOC_UNUSED
;
12969 offset_reloc
[2] = BFD_RELOC_UNUSED
;
12971 if (strcmp (s
, "lw") == 0 && op
[0] == breg
)
12973 ep
->X_add_number
+= 4;
12974 macro_build (ep
, s
, fmt
, op
[0] + 1, -1, offset_reloc
[0],
12975 offset_reloc
[1], offset_reloc
[2], breg
);
12976 ep
->X_add_number
-= 4;
12977 macro_build (ep
, s
, fmt
, op
[0], -1, offset_reloc
[0],
12978 offset_reloc
[1], offset_reloc
[2], breg
);
12982 macro_build (ep
, s
, fmt
, coproc
? op
[0] + 1 : op
[0], -1,
12983 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12985 ep
->X_add_number
+= 4;
12986 macro_build (ep
, s
, fmt
, coproc
? op
[0] : op
[0] + 1, -1,
12987 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2],
12993 if (offset_expr
.X_op
!= O_symbol
12994 && offset_expr
.X_op
!= O_constant
)
12996 as_bad (_("expression too complex"));
12997 offset_expr
.X_op
= O_constant
;
13000 if (HAVE_32BIT_ADDRESSES
13001 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
13005 sprintf_vma (value
, offset_expr
.X_add_number
);
13006 as_bad (_("number (0x%s) larger than 32 bits"), value
);
13009 if (mips_pic
== NO_PIC
|| offset_expr
.X_op
== O_constant
)
13011 /* If this is a reference to a GP relative symbol, we want
13012 <op> op[0],<sym>($gp) (BFD_RELOC_GPREL16)
13013 <op> op[0]+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
13014 If we have a base register, we use this
13016 <op> op[0],<sym>($at) (BFD_RELOC_GPREL16)
13017 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_GPREL16)
13018 If this is not a GP relative symbol, we want
13019 lui $at,<sym> (BFD_RELOC_HI16_S)
13020 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13021 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13022 If there is a base register, we add it to $at after the
13023 lui instruction. If there is a constant, we always use
13025 if (offset_expr
.X_op
== O_symbol
13026 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
13027 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
13029 relax_start (offset_expr
.X_add_symbol
);
13032 tempreg
= mips_gp_register
;
13036 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13037 AT
, breg
, mips_gp_register
);
13042 /* Itbl support may require additional care here. */
13043 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13044 BFD_RELOC_GPREL16
, tempreg
);
13045 offset_expr
.X_add_number
+= 4;
13047 /* Set mips_optimize to 2 to avoid inserting an
13049 hold_mips_optimize
= mips_optimize
;
13051 /* Itbl support may require additional care here. */
13052 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13053 BFD_RELOC_GPREL16
, tempreg
);
13054 mips_optimize
= hold_mips_optimize
;
13058 offset_expr
.X_add_number
-= 4;
13061 if (offset_high_part (offset_expr
.X_add_number
, 16)
13062 != offset_high_part (offset_expr
.X_add_number
+ 4, 16))
13064 load_address (AT
, &offset_expr
, &used_at
);
13065 offset_expr
.X_op
= O_constant
;
13066 offset_expr
.X_add_number
= 0;
13069 macro_build_lui (&offset_expr
, AT
);
13071 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13072 /* Itbl support may require additional care here. */
13073 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13074 BFD_RELOC_LO16
, AT
);
13075 /* FIXME: How do we handle overflow here? */
13076 offset_expr
.X_add_number
+= 4;
13077 /* Itbl support may require additional care here. */
13078 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13079 BFD_RELOC_LO16
, AT
);
13080 if (mips_relax
.sequence
)
13083 else if (!mips_big_got
)
13085 /* If this is a reference to an external symbol, we want
13086 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13089 <op> op[0]+1,4($at)
13091 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13093 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13094 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13095 If there is a base register we add it to $at before the
13096 lwc1 instructions. If there is a constant we include it
13097 in the lwc1 instructions. */
13099 expr1
.X_add_number
= offset_expr
.X_add_number
;
13100 if (expr1
.X_add_number
< -0x8000
13101 || expr1
.X_add_number
>= 0x8000 - 4)
13102 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13103 load_got_offset (AT
, &offset_expr
);
13106 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13108 /* Set mips_optimize to 2 to avoid inserting an undesired
13110 hold_mips_optimize
= mips_optimize
;
13113 /* Itbl support may require additional care here. */
13114 relax_start (offset_expr
.X_add_symbol
);
13115 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13116 BFD_RELOC_LO16
, AT
);
13117 expr1
.X_add_number
+= 4;
13118 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13119 BFD_RELOC_LO16
, AT
);
13121 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13122 BFD_RELOC_LO16
, AT
);
13123 offset_expr
.X_add_number
+= 4;
13124 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13125 BFD_RELOC_LO16
, AT
);
13128 mips_optimize
= hold_mips_optimize
;
13130 else if (mips_big_got
)
13134 /* If this is a reference to an external symbol, we want
13135 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
13137 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
13140 <op> op[0]+1,4($at)
13142 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
13144 <op> op[0],<sym>($at) (BFD_RELOC_LO16)
13145 <op> op[0]+1,<sym>+4($at) (BFD_RELOC_LO16)
13146 If there is a base register we add it to $at before the
13147 lwc1 instructions. If there is a constant we include it
13148 in the lwc1 instructions. */
13150 expr1
.X_add_number
= offset_expr
.X_add_number
;
13151 offset_expr
.X_add_number
= 0;
13152 if (expr1
.X_add_number
< -0x8000
13153 || expr1
.X_add_number
>= 0x8000 - 4)
13154 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
13155 gpdelay
= reg_needs_delay (mips_gp_register
);
13156 relax_start (offset_expr
.X_add_symbol
);
13157 macro_build (&offset_expr
, "lui", LUI_FMT
,
13158 AT
, BFD_RELOC_MIPS_GOT_HI16
);
13159 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13160 AT
, AT
, mips_gp_register
);
13161 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
13162 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
13165 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13166 /* Itbl support may require additional care here. */
13167 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13168 BFD_RELOC_LO16
, AT
);
13169 expr1
.X_add_number
+= 4;
13171 /* Set mips_optimize to 2 to avoid inserting an undesired
13173 hold_mips_optimize
= mips_optimize
;
13175 /* Itbl support may require additional care here. */
13176 macro_build (&expr1
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13177 BFD_RELOC_LO16
, AT
);
13178 mips_optimize
= hold_mips_optimize
;
13179 expr1
.X_add_number
-= 4;
13182 offset_expr
.X_add_number
= expr1
.X_add_number
;
13184 macro_build (NULL
, "nop", "");
13185 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
13186 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
13189 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
13190 /* Itbl support may require additional care here. */
13191 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] + 1 : op
[0],
13192 BFD_RELOC_LO16
, AT
);
13193 offset_expr
.X_add_number
+= 4;
13195 /* Set mips_optimize to 2 to avoid inserting an undesired
13197 hold_mips_optimize
= mips_optimize
;
13199 /* Itbl support may require additional care here. */
13200 macro_build (&offset_expr
, s
, fmt
, coproc
? op
[0] : op
[0] + 1,
13201 BFD_RELOC_LO16
, AT
);
13202 mips_optimize
= hold_mips_optimize
;
13216 gas_assert (!mips_opts
.micromips
);
13221 /* New code added to support COPZ instructions.
13222 This code builds table entries out of the macros in mip_opcodes.
13223 R4000 uses interlocks to handle coproc delays.
13224 Other chips (like the R3000) require nops to be inserted for delays.
13226 FIXME: Currently, we require that the user handle delays.
13227 In order to fill delay slots for non-interlocked chips,
13228 we must have a way to specify delays based on the coprocessor.
13229 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
13230 What are the side-effects of the cop instruction?
13231 What cache support might we have and what are its effects?
13232 Both coprocessor & memory require delays. how long???
13233 What registers are read/set/modified?
13235 If an itbl is provided to interpret cop instructions,
13236 this knowledge can be encoded in the itbl spec. */
13250 gas_assert (!mips_opts
.micromips
);
13251 /* For now we just do C (same as Cz). The parameter will be
13252 stored in insn_opcode by mips_ip. */
13253 macro_build (NULL
, s
, "C", (int) ip
->insn_opcode
);
13257 move_register (op
[0], op
[1]);
13261 gas_assert (mips_opts
.micromips
);
13262 gas_assert (mips_opts
.insn32
);
13263 move_register (micromips_to_32_reg_h_map1
[op
[0]],
13264 micromips_to_32_reg_m_map
[op
[1]]);
13265 move_register (micromips_to_32_reg_h_map2
[op
[0]],
13266 micromips_to_32_reg_n_map
[op
[2]]);
13271 /* Fall through. */
13273 if (mips_opts
.arch
== CPU_R5900
)
13274 macro_build (NULL
, dbl
? "dmultu" : "multu", "d,s,t", op
[0], op
[1],
13278 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", op
[1], op
[2]);
13279 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13285 /* Fall through. */
13287 /* The MIPS assembler some times generates shifts and adds. I'm
13288 not trying to be that fancy. GCC should do this for us
13291 load_register (AT
, &imm_expr
, dbl
);
13292 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", op
[1], AT
);
13293 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13298 /* Fall through. */
13305 /* Fall through. */
13308 start_noreorder ();
13311 load_register (AT
, &imm_expr
, dbl
);
13312 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t",
13313 op
[1], imm
? AT
: op
[2]);
13314 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13315 macro_build (NULL
, dbl
? "dsra32" : "sra", SHFT_FMT
, op
[0], op
[0], 31);
13316 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13318 macro_build (NULL
, "tne", TRAP_FMT
, op
[0], AT
, 6);
13321 if (mips_opts
.micromips
)
13322 micromips_label_expr (&label_expr
);
13324 label_expr
.X_add_number
= 8;
13325 macro_build (&label_expr
, "beq", "s,t,p", op
[0], AT
);
13326 macro_build (NULL
, "nop", "");
13327 macro_build (NULL
, "break", BRK_FMT
, 6);
13328 if (mips_opts
.micromips
)
13329 micromips_add_label ();
13332 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13337 /* Fall through. */
13344 /* Fall through. */
13347 start_noreorder ();
13350 load_register (AT
, &imm_expr
, dbl
);
13351 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
13352 op
[1], imm
? AT
: op
[2]);
13353 macro_build (NULL
, "mfhi", MFHL_FMT
, AT
);
13354 macro_build (NULL
, "mflo", MFHL_FMT
, op
[0]);
13356 macro_build (NULL
, "tne", TRAP_FMT
, AT
, ZERO
, 6);
13359 if (mips_opts
.micromips
)
13360 micromips_label_expr (&label_expr
);
13362 label_expr
.X_add_number
= 8;
13363 macro_build (&label_expr
, "beq", "s,t,p", AT
, ZERO
);
13364 macro_build (NULL
, "nop", "");
13365 macro_build (NULL
, "break", BRK_FMT
, 6);
13366 if (mips_opts
.micromips
)
13367 micromips_add_label ();
13373 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13375 if (op
[0] == op
[1])
13382 macro_build (NULL
, "dnegu", "d,w", tempreg
, op
[2]);
13383 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], tempreg
);
13387 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13388 macro_build (NULL
, "dsrlv", "d,t,s", AT
, op
[1], AT
);
13389 macro_build (NULL
, "dsllv", "d,t,s", op
[0], op
[1], op
[2]);
13390 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13394 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13396 if (op
[0] == op
[1])
13403 macro_build (NULL
, "negu", "d,w", tempreg
, op
[2]);
13404 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], tempreg
);
13408 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13409 macro_build (NULL
, "srlv", "d,t,s", AT
, op
[1], AT
);
13410 macro_build (NULL
, "sllv", "d,t,s", op
[0], op
[1], op
[2]);
13411 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13420 rot
= imm_expr
.X_add_number
& 0x3f;
13421 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13423 rot
= (64 - rot
) & 0x3f;
13425 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13427 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13432 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13435 l
= (rot
< 0x20) ? "dsll" : "dsll32";
13436 rr
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
13439 macro_build (NULL
, l
, SHFT_FMT
, AT
, op
[1], rot
);
13440 macro_build (NULL
, rr
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13441 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13449 rot
= imm_expr
.X_add_number
& 0x1f;
13450 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13452 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1],
13453 (32 - rot
) & 0x1f);
13458 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13462 macro_build (NULL
, "sll", SHFT_FMT
, AT
, op
[1], rot
);
13463 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13464 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13469 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13471 macro_build (NULL
, "drorv", "d,t,s", op
[0], op
[1], op
[2]);
13475 macro_build (NULL
, "dsubu", "d,v,t", AT
, ZERO
, op
[2]);
13476 macro_build (NULL
, "dsllv", "d,t,s", AT
, op
[1], AT
);
13477 macro_build (NULL
, "dsrlv", "d,t,s", op
[0], op
[1], op
[2]);
13478 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13482 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13484 macro_build (NULL
, "rorv", "d,t,s", op
[0], op
[1], op
[2]);
13488 macro_build (NULL
, "subu", "d,v,t", AT
, ZERO
, op
[2]);
13489 macro_build (NULL
, "sllv", "d,t,s", AT
, op
[1], AT
);
13490 macro_build (NULL
, "srlv", "d,t,s", op
[0], op
[1], op
[2]);
13491 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13500 rot
= imm_expr
.X_add_number
& 0x3f;
13501 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
13504 macro_build (NULL
, "dror32", SHFT_FMT
, op
[0], op
[1], rot
- 32);
13506 macro_build (NULL
, "dror", SHFT_FMT
, op
[0], op
[1], rot
);
13511 macro_build (NULL
, "dsrl", SHFT_FMT
, op
[0], op
[1], 0);
13514 rr
= (rot
< 0x20) ? "dsrl" : "dsrl32";
13515 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
13518 macro_build (NULL
, rr
, SHFT_FMT
, AT
, op
[1], rot
);
13519 macro_build (NULL
, l
, SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13520 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13528 rot
= imm_expr
.X_add_number
& 0x1f;
13529 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
13531 macro_build (NULL
, "ror", SHFT_FMT
, op
[0], op
[1], rot
);
13536 macro_build (NULL
, "srl", SHFT_FMT
, op
[0], op
[1], 0);
13540 macro_build (NULL
, "srl", SHFT_FMT
, AT
, op
[1], rot
);
13541 macro_build (NULL
, "sll", SHFT_FMT
, op
[0], op
[1], (0x20 - rot
) & 0x1f);
13542 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
13548 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[2], BFD_RELOC_LO16
);
13549 else if (op
[2] == 0)
13550 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13553 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13554 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13559 if (imm_expr
.X_add_number
== 0)
13561 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13566 as_warn (_("instruction %s: result is always false"),
13567 ip
->insn_mo
->name
);
13568 move_register (op
[0], 0);
13571 if (CPU_HAS_SEQ (mips_opts
.arch
)
13572 && -512 <= imm_expr
.X_add_number
13573 && imm_expr
.X_add_number
< 512)
13575 macro_build (NULL
, "seqi", "t,r,+Q", op
[0], op
[1],
13576 (int) imm_expr
.X_add_number
);
13579 if (imm_expr
.X_add_number
>= 0
13580 && imm_expr
.X_add_number
< 0x10000)
13581 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1], BFD_RELOC_LO16
);
13582 else if (imm_expr
.X_add_number
> -0x8000
13583 && imm_expr
.X_add_number
< 0)
13585 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13586 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13587 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13589 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13592 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13593 macro_build (NULL
, "seq", "d,v,t", op
[0], op
[1], AT
);
13598 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13599 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13602 macro_build (&expr1
, "sltiu", "t,r,j", op
[0], op
[0], BFD_RELOC_LO16
);
13605 case M_SGE
: /* X >= Y <==> not (X < Y) */
13611 macro_build (NULL
, s
, "d,v,t", op
[0], op
[1], op
[2]);
13612 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13615 case M_SGE_I
: /* X >= I <==> not (X < I). */
13617 if (imm_expr
.X_add_number
>= -0x8000
13618 && imm_expr
.X_add_number
< 0x8000)
13619 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
13620 op
[0], op
[1], BFD_RELOC_LO16
);
13623 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13624 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
13628 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13631 case M_SGT
: /* X > Y <==> Y < X. */
13637 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13640 case M_SGT_I
: /* X > I <==> I < X. */
13647 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13648 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13651 case M_SLE
: /* X <= Y <==> Y >= X <==> not (Y < X). */
13657 macro_build (NULL
, s
, "d,v,t", op
[0], op
[2], op
[1]);
13658 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13661 case M_SLE_I
: /* X <= I <==> I >= X <==> not (I < X) */
13668 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13669 macro_build (NULL
, s
, "d,v,t", op
[0], AT
, op
[1]);
13670 macro_build (&expr1
, "xori", "t,r,i", op
[0], op
[0], BFD_RELOC_LO16
);
13674 if (imm_expr
.X_add_number
>= -0x8000
13675 && imm_expr
.X_add_number
< 0x8000)
13677 macro_build (&imm_expr
, "slti", "t,r,j", op
[0], op
[1],
13682 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13683 macro_build (NULL
, "slt", "d,v,t", op
[0], op
[1], AT
);
13687 if (imm_expr
.X_add_number
>= -0x8000
13688 && imm_expr
.X_add_number
< 0x8000)
13690 macro_build (&imm_expr
, "sltiu", "t,r,j", op
[0], op
[1],
13695 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13696 macro_build (NULL
, "sltu", "d,v,t", op
[0], op
[1], AT
);
13701 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[2]);
13702 else if (op
[2] == 0)
13703 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13706 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], op
[2]);
13707 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13712 if (imm_expr
.X_add_number
== 0)
13714 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[1]);
13719 as_warn (_("instruction %s: result is always true"),
13720 ip
->insn_mo
->name
);
13721 macro_build (&expr1
, GPR_SIZE
== 32 ? "addiu" : "daddiu", "t,r,j",
13722 op
[0], 0, BFD_RELOC_LO16
);
13725 if (CPU_HAS_SEQ (mips_opts
.arch
)
13726 && -512 <= imm_expr
.X_add_number
13727 && imm_expr
.X_add_number
< 512)
13729 macro_build (NULL
, "snei", "t,r,+Q", op
[0], op
[1],
13730 (int) imm_expr
.X_add_number
);
13733 if (imm_expr
.X_add_number
>= 0
13734 && imm_expr
.X_add_number
< 0x10000)
13736 macro_build (&imm_expr
, "xori", "t,r,i", op
[0], op
[1],
13739 else if (imm_expr
.X_add_number
> -0x8000
13740 && imm_expr
.X_add_number
< 0)
13742 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13743 macro_build (&imm_expr
, GPR_SIZE
== 32 ? "addiu" : "daddiu",
13744 "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13746 else if (CPU_HAS_SEQ (mips_opts
.arch
))
13749 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13750 macro_build (NULL
, "sne", "d,v,t", op
[0], op
[1], AT
);
13755 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13756 macro_build (NULL
, "xor", "d,v,t", op
[0], op
[1], AT
);
13759 macro_build (NULL
, "sltu", "d,v,t", op
[0], 0, op
[0]);
13765 if (ISA_IS_R6 (mips_opts
.isa
))
13777 if (!mips_opts
.micromips
&& !ISA_IS_R6 (mips_opts
.isa
))
13779 if (imm_expr
.X_add_number
> -0x200
13780 && imm_expr
.X_add_number
<= 0x200
13781 && !ISA_IS_R6 (mips_opts
.isa
))
13783 macro_build (NULL
, s
, "t,r,.", op
[0], op
[1],
13784 (int) -imm_expr
.X_add_number
);
13793 if (imm_expr
.X_add_number
> -0x8000
13794 && imm_expr
.X_add_number
<= 0x8000)
13796 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
13797 macro_build (&imm_expr
, s
, "t,r,j", op
[0], op
[1], BFD_RELOC_LO16
);
13802 load_register (AT
, &imm_expr
, dbl
);
13803 macro_build (NULL
, s2
, "d,v,t", op
[0], op
[1], AT
);
13825 load_register (AT
, &imm_expr
, GPR_SIZE
== 64);
13826 macro_build (NULL
, s
, "s,t", op
[0], AT
);
13831 gas_assert (!mips_opts
.micromips
);
13832 gas_assert (mips_opts
.isa
== ISA_MIPS1
);
13836 * Is the double cfc1 instruction a bug in the mips assembler;
13837 * or is there a reason for it?
13839 start_noreorder ();
13840 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13841 macro_build (NULL
, "cfc1", "t,G", op
[2], RA
);
13842 macro_build (NULL
, "nop", "");
13843 expr1
.X_add_number
= 3;
13844 macro_build (&expr1
, "ori", "t,r,i", AT
, op
[2], BFD_RELOC_LO16
);
13845 expr1
.X_add_number
= 2;
13846 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
13847 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
13848 macro_build (NULL
, "nop", "");
13849 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
13851 macro_build (NULL
, "ctc1", "t,G", op
[2], RA
);
13852 macro_build (NULL
, "nop", "");
13869 offbits
= (mips_opts
.micromips
? 12 : 16);
13875 offbits
= (mips_opts
.micromips
? 12 : 16);
13887 offbits
= (mips_opts
.micromips
? 12 : 16);
13894 offbits
= (mips_opts
.micromips
? 12 : 16);
13900 large_offset
= !small_offset_p (off
, align
, offbits
);
13902 expr1
.X_add_number
= 0;
13907 if (small_offset_p (0, align
, 16))
13908 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
, breg
, -1,
13909 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2]);
13912 load_address (tempreg
, ep
, &used_at
);
13914 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
13915 tempreg
, tempreg
, breg
);
13917 offset_reloc
[0] = BFD_RELOC_LO16
;
13918 offset_reloc
[1] = BFD_RELOC_UNUSED
;
13919 offset_reloc
[2] = BFD_RELOC_UNUSED
;
13924 else if (!ust
&& op
[0] == breg
)
13935 if (!target_big_endian
)
13936 ep
->X_add_number
+= off
;
13938 macro_build (NULL
, s
, "t,~(b)", tempreg
, (int) ep
->X_add_number
, breg
);
13940 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13941 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13943 if (!target_big_endian
)
13944 ep
->X_add_number
-= off
;
13946 ep
->X_add_number
+= off
;
13948 macro_build (NULL
, s2
, "t,~(b)",
13949 tempreg
, (int) ep
->X_add_number
, breg
);
13951 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13952 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13954 /* If necessary, move the result in tempreg to the final destination. */
13955 if (!ust
&& op
[0] != tempreg
)
13957 /* Protect second load's delay slot. */
13959 move_register (op
[0], tempreg
);
13965 if (target_big_endian
== ust
)
13966 ep
->X_add_number
+= off
;
13967 tempreg
= ust
|| large_offset
? op
[0] : AT
;
13968 macro_build (ep
, s
, "t,o(b)", tempreg
, -1,
13969 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13971 /* For halfword transfers we need a temporary register to shuffle
13972 bytes. Unfortunately for M_USH_A we have none available before
13973 the next store as AT holds the base address. We deal with this
13974 case by clobbering TREG and then restoring it as with ULH. */
13975 tempreg
= ust
== large_offset
? op
[0] : AT
;
13977 macro_build (NULL
, "srl", SHFT_FMT
, tempreg
, op
[0], 8);
13979 if (target_big_endian
== ust
)
13980 ep
->X_add_number
-= off
;
13982 ep
->X_add_number
+= off
;
13983 macro_build (ep
, s2
, "t,o(b)", tempreg
, -1,
13984 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], breg
);
13986 /* For M_USH_A re-retrieve the LSB. */
13987 if (ust
&& large_offset
)
13989 if (target_big_endian
)
13990 ep
->X_add_number
+= off
;
13992 ep
->X_add_number
-= off
;
13993 macro_build (&expr1
, "lbu", "t,o(b)", AT
, -1,
13994 offset_reloc
[0], offset_reloc
[1], offset_reloc
[2], AT
);
13996 /* For ULH and M_USH_A OR the LSB in. */
13997 if (!ust
|| large_offset
)
13999 tempreg
= !large_offset
? AT
: op
[0];
14000 macro_build (NULL
, "sll", SHFT_FMT
, tempreg
, tempreg
, 8);
14001 macro_build (NULL
, "or", "d,v,t", op
[0], op
[0], AT
);
14006 /* FIXME: Check if this is one of the itbl macros, since they
14007 are added dynamically. */
14008 as_bad (_("macro %s not implemented yet"), ip
->insn_mo
->name
);
14011 if (!mips_opts
.at
&& used_at
)
14012 as_bad (_("macro used $at after \".set noat\""));
14015 /* Implement macros in mips16 mode. */
14018 mips16_macro (struct mips_cl_insn
*ip
)
14020 const struct mips_operand_array
*operands
;
14025 const char *s
, *s2
, *s3
;
14026 unsigned int op
[MAX_OPERANDS
];
14029 mask
= ip
->insn_mo
->mask
;
14031 operands
= insn_operands (ip
);
14032 for (i
= 0; i
< MAX_OPERANDS
; i
++)
14033 if (operands
->operand
[i
])
14034 op
[i
] = insn_extract_operand (ip
, operands
->operand
[i
]);
14038 expr1
.X_op
= O_constant
;
14039 expr1
.X_op_symbol
= NULL
;
14040 expr1
.X_add_symbol
= NULL
;
14041 expr1
.X_add_number
= 1;
14052 /* Fall through. */
14058 /* Fall through. */
14062 start_noreorder ();
14063 macro_build (NULL
, dbl
? "ddiv" : "div", ".,x,y", op
[1], op
[2]);
14064 expr1
.X_add_number
= 2;
14065 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14066 macro_build (NULL
, "break", "6", 7);
14068 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
14069 since that causes an overflow. We should do that as well,
14070 but I don't see how to do the comparisons without a temporary
14073 macro_build (NULL
, s
, "x", op
[0]);
14092 start_noreorder ();
14093 macro_build (NULL
, s
, ".,x,y", op
[1], op
[2]);
14094 expr1
.X_add_number
= 2;
14095 macro_build (&expr1
, "bnez", "x,p", op
[2]);
14096 macro_build (NULL
, "break", "6", 7);
14098 macro_build (NULL
, s2
, "x", op
[0]);
14103 /* Fall through. */
14105 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", op
[1], op
[2]);
14106 macro_build (NULL
, "mflo", "x", op
[0]);
14114 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14115 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,F", op
[0], op
[1]);
14119 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14120 macro_build (&imm_expr
, "addiu", "x,k", op
[0]);
14124 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
14125 macro_build (&imm_expr
, "daddiu", "y,j", op
[0]);
14147 goto do_reverse_branch
;
14151 goto do_reverse_branch
;
14163 goto do_reverse_branch
;
14174 macro_build (NULL
, s
, "x,y", op
[0], op
[1]);
14175 macro_build (&offset_expr
, s2
, "p");
14202 goto do_addone_branch_i
;
14207 goto do_addone_branch_i
;
14222 goto do_addone_branch_i
;
14228 do_addone_branch_i
:
14229 ++imm_expr
.X_add_number
;
14232 macro_build (&imm_expr
, s
, s3
, op
[0]);
14233 macro_build (&offset_expr
, s2
, "p");
14237 expr1
.X_add_number
= 0;
14238 macro_build (&expr1
, "slti", "x,8", op
[1]);
14239 if (op
[0] != op
[1])
14240 macro_build (NULL
, "move", "y,X", op
[0], mips16_to_32_reg_map
[op
[1]]);
14241 expr1
.X_add_number
= 2;
14242 macro_build (&expr1
, "bteqz", "p");
14243 macro_build (NULL
, "neg", "x,w", op
[0], op
[0]);
14248 /* Look up instruction [START, START + LENGTH) in HASH. Record any extra
14249 opcode bits in *OPCODE_EXTRA. */
14251 static struct mips_opcode
*
14252 mips_lookup_insn (htab_t hash
, const char *start
,
14253 ssize_t length
, unsigned int *opcode_extra
)
14255 char *name
, *dot
, *p
;
14256 unsigned int mask
, suffix
;
14258 struct mips_opcode
*insn
;
14260 /* Make a copy of the instruction so that we can fiddle with it. */
14261 name
= xstrndup (start
, length
);
14263 /* Look up the instruction as-is. */
14264 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14268 dot
= strchr (name
, '.');
14271 /* Try to interpret the text after the dot as a VU0 channel suffix. */
14272 p
= mips_parse_vu0_channels (dot
+ 1, &mask
);
14273 if (*p
== 0 && mask
!= 0)
14276 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14278 if (insn
&& (insn
->pinfo2
& INSN2_VU0_CHANNEL_SUFFIX
) != 0)
14280 *opcode_extra
|= mask
<< mips_vu0_channel_mask
.lsb
;
14286 if (mips_opts
.micromips
)
14288 /* See if there's an instruction size override suffix,
14289 either `16' or `32', at the end of the mnemonic proper,
14290 that defines the operation, i.e. before the first `.'
14291 character if any. Strip it and retry. */
14292 opend
= dot
!= NULL
? dot
- name
: length
;
14293 if (opend
>= 3 && name
[opend
- 2] == '1' && name
[opend
- 1] == '6')
14295 else if (opend
>= 2 && name
[opend
- 2] == '3' && name
[opend
- 1] == '2')
14301 memmove (name
+ opend
- 2, name
+ opend
, length
- opend
+ 1);
14302 insn
= (struct mips_opcode
*) str_hash_find (hash
, name
);
14305 forced_insn_length
= suffix
;
14317 /* Assemble an instruction into its binary format. If the instruction
14318 is a macro, set imm_expr and offset_expr to the values associated
14319 with "I" and "A" operands respectively. Otherwise store the value
14320 of the relocatable field (if any) in offset_expr. In both cases
14321 set offset_reloc to the relocation operators applied to offset_expr. */
14324 mips_ip (char *str
, struct mips_cl_insn
*insn
)
14326 const struct mips_opcode
*first
, *past
;
14330 struct mips_operand_token
*tokens
;
14331 unsigned int opcode_extra
;
14333 if (mips_opts
.micromips
)
14335 hash
= micromips_op_hash
;
14336 past
= µmips_opcodes
[bfd_micromips_num_opcodes
];
14341 past
= &mips_opcodes
[NUMOPCODES
];
14343 forced_insn_length
= 0;
14346 /* We first try to match an instruction up to a space or to the end. */
14347 for (end
= 0; str
[end
] != '\0' && !ISSPACE (str
[end
]); end
++)
14350 first
= mips_lookup_insn (hash
, str
, end
, &opcode_extra
);
14353 set_insn_error (0, _("unrecognized opcode"));
14357 if (strcmp (first
->name
, "li.s") == 0)
14359 else if (strcmp (first
->name
, "li.d") == 0)
14363 tokens
= mips_parse_arguments (str
+ end
, format
);
14367 if (!match_insns (insn
, first
, past
, tokens
, opcode_extra
, FALSE
)
14368 && !match_insns (insn
, first
, past
, tokens
, opcode_extra
, TRUE
))
14369 set_insn_error (0, _("invalid operands"));
14371 obstack_free (&mips_operand_tokens
, tokens
);
14374 /* As for mips_ip, but used when assembling MIPS16 code.
14375 Also set forced_insn_length to the resulting instruction size in
14376 bytes if the user explicitly requested a small or extended instruction. */
14379 mips16_ip (char *str
, struct mips_cl_insn
*insn
)
14382 struct mips_opcode
*first
;
14383 struct mips_operand_token
*tokens
;
14386 for (s
= str
; *s
!= '\0' && *s
!= '.' && *s
!= ' '; ++s
)
14408 else if (*s
== 'e')
14415 else if (*s
++ == ' ')
14417 set_insn_error (0, _("unrecognized opcode"));
14420 forced_insn_length
= l
;
14423 first
= (struct mips_opcode
*) str_hash_find (mips16_op_hash
, str
);
14428 set_insn_error (0, _("unrecognized opcode"));
14432 tokens
= mips_parse_arguments (s
, 0);
14436 if (!match_mips16_insns (insn
, first
, tokens
))
14437 set_insn_error (0, _("invalid operands"));
14439 obstack_free (&mips_operand_tokens
, tokens
);
14442 /* Marshal immediate value VAL for an extended MIPS16 instruction.
14443 NBITS is the number of significant bits in VAL. */
14445 static unsigned long
14446 mips16_immed_extend (offsetT val
, unsigned int nbits
)
14451 val
&= (1U << nbits
) - 1;
14452 if (nbits
== 16 || nbits
== 9)
14454 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
14457 else if (nbits
== 15)
14459 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
14462 else if (nbits
== 6)
14464 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
14467 return (extval
<< 16) | val
;
14470 /* Like decode_mips16_operand, but require the operand to be defined and
14471 require it to be an integer. */
14473 static const struct mips_int_operand
*
14474 mips16_immed_operand (int type
, bfd_boolean extended_p
)
14476 const struct mips_operand
*operand
;
14478 operand
= decode_mips16_operand (type
, extended_p
);
14479 if (!operand
|| (operand
->type
!= OP_INT
&& operand
->type
!= OP_PCREL
))
14481 return (const struct mips_int_operand
*) operand
;
14484 /* Return true if SVAL fits OPERAND. RELOC is as for mips16_immed. */
14487 mips16_immed_in_range_p (const struct mips_int_operand
*operand
,
14488 bfd_reloc_code_real_type reloc
, offsetT sval
)
14490 int min_val
, max_val
;
14492 min_val
= mips_int_operand_min (operand
);
14493 max_val
= mips_int_operand_max (operand
);
14494 if (reloc
!= BFD_RELOC_UNUSED
)
14497 sval
= SEXT_16BIT (sval
);
14502 return (sval
>= min_val
14504 && (sval
& ((1 << operand
->shift
) - 1)) == 0);
14507 /* Install immediate value VAL into MIPS16 instruction *INSN,
14508 extending it if necessary. The instruction in *INSN may
14509 already be extended.
14511 RELOC is the relocation that produced VAL, or BFD_RELOC_UNUSED
14512 if none. In the former case, VAL is a 16-bit number with no
14513 defined signedness.
14515 TYPE is the type of the immediate field. USER_INSN_LENGTH
14516 is the length that the user requested, or 0 if none. */
14519 mips16_immed (const char *file
, unsigned int line
, int type
,
14520 bfd_reloc_code_real_type reloc
, offsetT val
,
14521 unsigned int user_insn_length
, unsigned long *insn
)
14523 const struct mips_int_operand
*operand
;
14524 unsigned int uval
, length
;
14526 operand
= mips16_immed_operand (type
, FALSE
);
14527 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14529 /* We need an extended instruction. */
14530 if (user_insn_length
== 2)
14531 as_bad_where (file
, line
, _("invalid unextended operand value"));
14533 *insn
|= MIPS16_EXTEND
;
14535 else if (user_insn_length
== 4)
14537 /* The operand doesn't force an unextended instruction to be extended.
14538 Warn if the user wanted an extended instruction anyway. */
14539 *insn
|= MIPS16_EXTEND
;
14540 as_warn_where (file
, line
,
14541 _("extended operand requested but not required"));
14544 length
= mips16_opcode_length (*insn
);
14547 operand
= mips16_immed_operand (type
, TRUE
);
14548 if (!mips16_immed_in_range_p (operand
, reloc
, val
))
14549 as_bad_where (file
, line
,
14550 _("operand value out of range for instruction"));
14552 uval
= ((unsigned int) val
>> operand
->shift
) - operand
->bias
;
14553 if (length
== 2 || operand
->root
.lsb
!= 0)
14554 *insn
= mips_insert_operand (&operand
->root
, *insn
, uval
);
14556 *insn
|= mips16_immed_extend (uval
, operand
->root
.size
);
14559 struct percent_op_match
14562 bfd_reloc_code_real_type reloc
;
14565 static const struct percent_op_match mips_percent_op
[] =
14567 {"%lo", BFD_RELOC_LO16
},
14568 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
14569 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
14570 {"%call16", BFD_RELOC_MIPS_CALL16
},
14571 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
14572 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
14573 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
14574 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
14575 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
14576 {"%got", BFD_RELOC_MIPS_GOT16
},
14577 {"%gp_rel", BFD_RELOC_GPREL16
},
14578 {"%gprel", BFD_RELOC_GPREL16
},
14579 {"%half", BFD_RELOC_16
},
14580 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
14581 {"%higher", BFD_RELOC_MIPS_HIGHER
},
14582 {"%neg", BFD_RELOC_MIPS_SUB
},
14583 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
14584 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
14585 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
14586 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
14587 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
14588 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
14589 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
14590 {"%hi", BFD_RELOC_HI16_S
},
14591 {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL
},
14592 {"%pcrel_lo", BFD_RELOC_LO16_PCREL
}
14595 static const struct percent_op_match mips16_percent_op
[] =
14597 {"%lo", BFD_RELOC_MIPS16_LO16
},
14598 {"%gp_rel", BFD_RELOC_MIPS16_GPREL
},
14599 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
14600 {"%got", BFD_RELOC_MIPS16_GOT16
},
14601 {"%call16", BFD_RELOC_MIPS16_CALL16
},
14602 {"%hi", BFD_RELOC_MIPS16_HI16_S
},
14603 {"%tlsgd", BFD_RELOC_MIPS16_TLS_GD
},
14604 {"%tlsldm", BFD_RELOC_MIPS16_TLS_LDM
},
14605 {"%dtprel_hi", BFD_RELOC_MIPS16_TLS_DTPREL_HI16
},
14606 {"%dtprel_lo", BFD_RELOC_MIPS16_TLS_DTPREL_LO16
},
14607 {"%tprel_hi", BFD_RELOC_MIPS16_TLS_TPREL_HI16
},
14608 {"%tprel_lo", BFD_RELOC_MIPS16_TLS_TPREL_LO16
},
14609 {"%gottprel", BFD_RELOC_MIPS16_TLS_GOTTPREL
}
14613 /* Return true if *STR points to a relocation operator. When returning true,
14614 move *STR over the operator and store its relocation code in *RELOC.
14615 Leave both *STR and *RELOC alone when returning false. */
14618 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
14620 const struct percent_op_match
*percent_op
;
14623 if (mips_opts
.mips16
)
14625 percent_op
= mips16_percent_op
;
14626 limit
= ARRAY_SIZE (mips16_percent_op
);
14630 percent_op
= mips_percent_op
;
14631 limit
= ARRAY_SIZE (mips_percent_op
);
14634 for (i
= 0; i
< limit
; i
++)
14635 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
14637 int len
= strlen (percent_op
[i
].str
);
14639 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
14642 *str
+= strlen (percent_op
[i
].str
);
14643 *reloc
= percent_op
[i
].reloc
;
14645 /* Check whether the output BFD supports this relocation.
14646 If not, issue an error and fall back on something safe. */
14647 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
14649 as_bad (_("relocation %s isn't supported by the current ABI"),
14650 percent_op
[i
].str
);
14651 *reloc
= BFD_RELOC_UNUSED
;
14659 /* Parse string STR as a 16-bit relocatable operand. Store the
14660 expression in *EP and the relocations in the array starting
14661 at RELOC. Return the number of relocation operators used.
14663 On exit, EXPR_END points to the first character after the expression. */
14666 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
14669 bfd_reloc_code_real_type reversed_reloc
[3];
14670 size_t reloc_index
, i
;
14671 int crux_depth
, str_depth
;
14674 /* Search for the start of the main expression, recoding relocations
14675 in REVERSED_RELOC. End the loop with CRUX pointing to the start
14676 of the main expression and with CRUX_DEPTH containing the number
14677 of open brackets at that point. */
14684 crux_depth
= str_depth
;
14686 /* Skip over whitespace and brackets, keeping count of the number
14688 while (*str
== ' ' || *str
== '\t' || *str
== '(')
14693 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
14694 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
14696 my_getExpression (ep
, crux
);
14699 /* Match every open bracket. */
14700 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
14704 if (crux_depth
> 0)
14705 as_bad (_("unclosed '('"));
14709 for (i
= 0; i
< reloc_index
; i
++)
14710 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
14712 return reloc_index
;
14716 my_getExpression (expressionS
*ep
, char *str
)
14720 save_in
= input_line_pointer
;
14721 input_line_pointer
= str
;
14723 expr_end
= input_line_pointer
;
14724 input_line_pointer
= save_in
;
14728 md_atof (int type
, char *litP
, int *sizeP
)
14730 return ieee_md_atof (type
, litP
, sizeP
, target_big_endian
);
14734 md_number_to_chars (char *buf
, valueT val
, int n
)
14736 if (target_big_endian
)
14737 number_to_chars_bigendian (buf
, val
, n
);
14739 number_to_chars_littleendian (buf
, val
, n
);
14742 static int support_64bit_objects(void)
14744 const char **list
, **l
;
14747 list
= bfd_target_list ();
14748 for (l
= list
; *l
!= NULL
; l
++)
14749 if (strcmp (*l
, ELF_TARGET ("elf64-", "big")) == 0
14750 || strcmp (*l
, ELF_TARGET ("elf64-", "little")) == 0)
14752 yes
= (*l
!= NULL
);
14757 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
14758 NEW_VALUE. Warn if another value was already specified. Note:
14759 we have to defer parsing the -march and -mtune arguments in order
14760 to handle 'from-abi' correctly, since the ABI might be specified
14761 in a later argument. */
14764 mips_set_option_string (const char **string_ptr
, const char *new_value
)
14766 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
14767 as_warn (_("a different %s was already specified, is now %s"),
14768 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
14771 *string_ptr
= new_value
;
14775 md_parse_option (int c
, const char *arg
)
14779 for (i
= 0; i
< ARRAY_SIZE (mips_ases
); i
++)
14780 if (c
== mips_ases
[i
].option_on
|| c
== mips_ases
[i
].option_off
)
14782 file_ase_explicit
|= mips_set_ase (&mips_ases
[i
], &file_mips_opts
,
14783 c
== mips_ases
[i
].option_on
);
14789 case OPTION_CONSTRUCT_FLOATS
:
14790 mips_disable_float_construction
= 0;
14793 case OPTION_NO_CONSTRUCT_FLOATS
:
14794 mips_disable_float_construction
= 1;
14806 target_big_endian
= 1;
14810 target_big_endian
= 0;
14816 else if (arg
[0] == '0')
14818 else if (arg
[0] == '1')
14828 mips_debug
= atoi (arg
);
14832 file_mips_opts
.isa
= ISA_MIPS1
;
14836 file_mips_opts
.isa
= ISA_MIPS2
;
14840 file_mips_opts
.isa
= ISA_MIPS3
;
14844 file_mips_opts
.isa
= ISA_MIPS4
;
14848 file_mips_opts
.isa
= ISA_MIPS5
;
14851 case OPTION_MIPS32
:
14852 file_mips_opts
.isa
= ISA_MIPS32
;
14855 case OPTION_MIPS32R2
:
14856 file_mips_opts
.isa
= ISA_MIPS32R2
;
14859 case OPTION_MIPS32R3
:
14860 file_mips_opts
.isa
= ISA_MIPS32R3
;
14863 case OPTION_MIPS32R5
:
14864 file_mips_opts
.isa
= ISA_MIPS32R5
;
14867 case OPTION_MIPS32R6
:
14868 file_mips_opts
.isa
= ISA_MIPS32R6
;
14871 case OPTION_MIPS64R2
:
14872 file_mips_opts
.isa
= ISA_MIPS64R2
;
14875 case OPTION_MIPS64R3
:
14876 file_mips_opts
.isa
= ISA_MIPS64R3
;
14879 case OPTION_MIPS64R5
:
14880 file_mips_opts
.isa
= ISA_MIPS64R5
;
14883 case OPTION_MIPS64R6
:
14884 file_mips_opts
.isa
= ISA_MIPS64R6
;
14887 case OPTION_MIPS64
:
14888 file_mips_opts
.isa
= ISA_MIPS64
;
14892 mips_set_option_string (&mips_tune_string
, arg
);
14896 mips_set_option_string (&mips_arch_string
, arg
);
14900 mips_set_option_string (&mips_arch_string
, "4650");
14901 mips_set_option_string (&mips_tune_string
, "4650");
14904 case OPTION_NO_M4650
:
14908 mips_set_option_string (&mips_arch_string
, "4010");
14909 mips_set_option_string (&mips_tune_string
, "4010");
14912 case OPTION_NO_M4010
:
14916 mips_set_option_string (&mips_arch_string
, "4100");
14917 mips_set_option_string (&mips_tune_string
, "4100");
14920 case OPTION_NO_M4100
:
14924 mips_set_option_string (&mips_arch_string
, "3900");
14925 mips_set_option_string (&mips_tune_string
, "3900");
14928 case OPTION_NO_M3900
:
14931 case OPTION_MICROMIPS
:
14932 if (file_mips_opts
.mips16
== 1)
14934 as_bad (_("-mmicromips cannot be used with -mips16"));
14937 file_mips_opts
.micromips
= 1;
14938 mips_no_prev_insn ();
14941 case OPTION_NO_MICROMIPS
:
14942 file_mips_opts
.micromips
= 0;
14943 mips_no_prev_insn ();
14946 case OPTION_MIPS16
:
14947 if (file_mips_opts
.micromips
== 1)
14949 as_bad (_("-mips16 cannot be used with -micromips"));
14952 file_mips_opts
.mips16
= 1;
14953 mips_no_prev_insn ();
14956 case OPTION_NO_MIPS16
:
14957 file_mips_opts
.mips16
= 0;
14958 mips_no_prev_insn ();
14961 case OPTION_FIX_24K
:
14965 case OPTION_NO_FIX_24K
:
14969 case OPTION_FIX_RM7000
:
14970 mips_fix_rm7000
= 1;
14973 case OPTION_NO_FIX_RM7000
:
14974 mips_fix_rm7000
= 0;
14977 case OPTION_FIX_LOONGSON3_LLSC
:
14978 mips_fix_loongson3_llsc
= TRUE
;
14981 case OPTION_NO_FIX_LOONGSON3_LLSC
:
14982 mips_fix_loongson3_llsc
= FALSE
;
14985 case OPTION_FIX_LOONGSON2F_JUMP
:
14986 mips_fix_loongson2f_jump
= TRUE
;
14989 case OPTION_NO_FIX_LOONGSON2F_JUMP
:
14990 mips_fix_loongson2f_jump
= FALSE
;
14993 case OPTION_FIX_LOONGSON2F_NOP
:
14994 mips_fix_loongson2f_nop
= TRUE
;
14997 case OPTION_NO_FIX_LOONGSON2F_NOP
:
14998 mips_fix_loongson2f_nop
= FALSE
;
15001 case OPTION_FIX_VR4120
:
15002 mips_fix_vr4120
= 1;
15005 case OPTION_NO_FIX_VR4120
:
15006 mips_fix_vr4120
= 0;
15009 case OPTION_FIX_VR4130
:
15010 mips_fix_vr4130
= 1;
15013 case OPTION_NO_FIX_VR4130
:
15014 mips_fix_vr4130
= 0;
15017 case OPTION_FIX_CN63XXP1
:
15018 mips_fix_cn63xxp1
= TRUE
;
15021 case OPTION_NO_FIX_CN63XXP1
:
15022 mips_fix_cn63xxp1
= FALSE
;
15025 case OPTION_FIX_R5900
:
15026 mips_fix_r5900
= TRUE
;
15027 mips_fix_r5900_explicit
= TRUE
;
15030 case OPTION_NO_FIX_R5900
:
15031 mips_fix_r5900
= FALSE
;
15032 mips_fix_r5900_explicit
= TRUE
;
15035 case OPTION_RELAX_BRANCH
:
15036 mips_relax_branch
= 1;
15039 case OPTION_NO_RELAX_BRANCH
:
15040 mips_relax_branch
= 0;
15043 case OPTION_IGNORE_BRANCH_ISA
:
15044 mips_ignore_branch_isa
= TRUE
;
15047 case OPTION_NO_IGNORE_BRANCH_ISA
:
15048 mips_ignore_branch_isa
= FALSE
;
15051 case OPTION_INSN32
:
15052 file_mips_opts
.insn32
= TRUE
;
15055 case OPTION_NO_INSN32
:
15056 file_mips_opts
.insn32
= FALSE
;
15059 case OPTION_MSHARED
:
15060 mips_in_shared
= TRUE
;
15063 case OPTION_MNO_SHARED
:
15064 mips_in_shared
= FALSE
;
15067 case OPTION_MSYM32
:
15068 file_mips_opts
.sym32
= TRUE
;
15071 case OPTION_MNO_SYM32
:
15072 file_mips_opts
.sym32
= FALSE
;
15075 /* When generating ELF code, we permit -KPIC and -call_shared to
15076 select SVR4_PIC, and -non_shared to select no PIC. This is
15077 intended to be compatible with Irix 5. */
15078 case OPTION_CALL_SHARED
:
15079 mips_pic
= SVR4_PIC
;
15080 mips_abicalls
= TRUE
;
15083 case OPTION_CALL_NONPIC
:
15085 mips_abicalls
= TRUE
;
15088 case OPTION_NON_SHARED
:
15090 mips_abicalls
= FALSE
;
15093 /* The -xgot option tells the assembler to use 32 bit offsets
15094 when accessing the got in SVR4_PIC mode. It is for Irix
15101 g_switch_value
= atoi (arg
);
15105 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
15108 mips_abi
= O32_ABI
;
15112 mips_abi
= N32_ABI
;
15116 mips_abi
= N64_ABI
;
15117 if (!support_64bit_objects())
15118 as_fatal (_("no compiled in support for 64 bit object file format"));
15122 file_mips_opts
.gp
= 32;
15126 file_mips_opts
.gp
= 64;
15130 file_mips_opts
.fp
= 32;
15134 file_mips_opts
.fp
= 0;
15138 file_mips_opts
.fp
= 64;
15141 case OPTION_ODD_SPREG
:
15142 file_mips_opts
.oddspreg
= 1;
15145 case OPTION_NO_ODD_SPREG
:
15146 file_mips_opts
.oddspreg
= 0;
15149 case OPTION_SINGLE_FLOAT
:
15150 file_mips_opts
.single_float
= 1;
15153 case OPTION_DOUBLE_FLOAT
:
15154 file_mips_opts
.single_float
= 0;
15157 case OPTION_SOFT_FLOAT
:
15158 file_mips_opts
.soft_float
= 1;
15161 case OPTION_HARD_FLOAT
:
15162 file_mips_opts
.soft_float
= 0;
15166 if (strcmp (arg
, "32") == 0)
15167 mips_abi
= O32_ABI
;
15168 else if (strcmp (arg
, "o64") == 0)
15169 mips_abi
= O64_ABI
;
15170 else if (strcmp (arg
, "n32") == 0)
15171 mips_abi
= N32_ABI
;
15172 else if (strcmp (arg
, "64") == 0)
15174 mips_abi
= N64_ABI
;
15175 if (! support_64bit_objects())
15176 as_fatal (_("no compiled in support for 64 bit object file "
15179 else if (strcmp (arg
, "eabi") == 0)
15180 mips_abi
= EABI_ABI
;
15183 as_fatal (_("invalid abi -mabi=%s"), arg
);
15188 case OPTION_M7000_HILO_FIX
:
15189 mips_7000_hilo_fix
= TRUE
;
15192 case OPTION_MNO_7000_HILO_FIX
:
15193 mips_7000_hilo_fix
= FALSE
;
15196 case OPTION_MDEBUG
:
15197 mips_flag_mdebug
= TRUE
;
15200 case OPTION_NO_MDEBUG
:
15201 mips_flag_mdebug
= FALSE
;
15205 mips_flag_pdr
= TRUE
;
15208 case OPTION_NO_PDR
:
15209 mips_flag_pdr
= FALSE
;
15212 case OPTION_MVXWORKS_PIC
:
15213 mips_pic
= VXWORKS_PIC
;
15217 if (strcmp (arg
, "2008") == 0)
15219 else if (strcmp (arg
, "legacy") == 0)
15223 as_fatal (_("invalid NaN setting -mnan=%s"), arg
);
15232 mips_fix_loongson2f
= mips_fix_loongson2f_nop
|| mips_fix_loongson2f_jump
;
15237 /* Set up globals to tune for the ISA or processor described by INFO. */
15240 mips_set_tune (const struct mips_cpu_info
*info
)
15243 mips_tune
= info
->cpu
;
15248 mips_after_parse_args (void)
15250 const struct mips_cpu_info
*arch_info
= 0;
15251 const struct mips_cpu_info
*tune_info
= 0;
15253 /* GP relative stuff not working for PE. */
15254 if (strncmp (TARGET_OS
, "pe", 2) == 0)
15256 if (g_switch_seen
&& g_switch_value
!= 0)
15257 as_bad (_("-G not supported in this configuration"));
15258 g_switch_value
= 0;
15261 if (mips_abi
== NO_ABI
)
15262 mips_abi
= MIPS_DEFAULT_ABI
;
15264 /* The following code determines the architecture.
15265 Similar code was added to GCC 3.3 (see override_options() in
15266 config/mips/mips.c). The GAS and GCC code should be kept in sync
15267 as much as possible. */
15269 if (mips_arch_string
!= 0)
15270 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
15272 if (file_mips_opts
.isa
!= ISA_UNKNOWN
)
15274 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
15275 ISA level specified by -mipsN, while arch_info->isa contains
15276 the -march selection (if any). */
15277 if (arch_info
!= 0)
15279 /* -march takes precedence over -mipsN, since it is more descriptive.
15280 There's no harm in specifying both as long as the ISA levels
15282 if (file_mips_opts
.isa
!= arch_info
->isa
)
15283 as_bad (_("-%s conflicts with the other architecture options,"
15284 " which imply -%s"),
15285 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
,
15286 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
15289 arch_info
= mips_cpu_info_from_isa (file_mips_opts
.isa
);
15292 if (arch_info
== 0)
15294 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
15295 gas_assert (arch_info
);
15298 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
15299 as_bad (_("-march=%s is not compatible with the selected ABI"),
15302 file_mips_opts
.arch
= arch_info
->cpu
;
15303 file_mips_opts
.isa
= arch_info
->isa
;
15304 file_mips_opts
.init_ase
= arch_info
->ase
;
15306 /* The EVA Extension has instructions which are only valid when the R6 ISA
15307 is enabled. This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
15309 if (((file_mips_opts
.ase
& ASE_EVA
) != 0) && ISA_IS_R6 (file_mips_opts
.isa
))
15310 file_mips_opts
.ase
|= ASE_EVA_R6
;
15312 /* Set up initial mips_opts state. */
15313 mips_opts
= file_mips_opts
;
15315 /* For the R5900 default to `-mfix-r5900' unless the user told otherwise. */
15316 if (!mips_fix_r5900_explicit
)
15317 mips_fix_r5900
= file_mips_opts
.arch
== CPU_R5900
;
15319 /* The register size inference code is now placed in
15320 file_mips_check_options. */
15322 /* Optimize for file_mips_opts.arch, unless -mtune selects a different
15324 if (mips_tune_string
!= 0)
15325 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
15327 if (tune_info
== 0)
15328 mips_set_tune (arch_info
);
15330 mips_set_tune (tune_info
);
15332 if (mips_flag_mdebug
< 0)
15333 mips_flag_mdebug
= 0;
15337 mips_init_after_args (void)
15339 /* Initialize opcodes. */
15340 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
15341 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
15345 md_pcrel_from (fixS
*fixP
)
15347 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
15349 switch (fixP
->fx_r_type
)
15351 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15352 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15353 /* Return the address of the delay slot. */
15356 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15357 case BFD_RELOC_MICROMIPS_JMP
:
15358 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15359 case BFD_RELOC_16_PCREL_S2
:
15360 case BFD_RELOC_MIPS_21_PCREL_S2
:
15361 case BFD_RELOC_MIPS_26_PCREL_S2
:
15362 case BFD_RELOC_MIPS_JMP
:
15363 /* Return the address of the delay slot. */
15366 case BFD_RELOC_MIPS_18_PCREL_S3
:
15367 /* Return the aligned address of the doubleword containing
15368 the instruction. */
15376 /* This is called before the symbol table is processed. In order to
15377 work with gcc when using mips-tfile, we must keep all local labels.
15378 However, in other cases, we want to discard them. If we were
15379 called with -g, but we didn't see any debugging information, it may
15380 mean that gcc is smuggling debugging information through to
15381 mips-tfile, in which case we must generate all local labels. */
15384 mips_frob_file_before_adjust (void)
15386 #ifndef NO_ECOFF_DEBUGGING
15387 if (ECOFF_DEBUGGING
15389 && ! ecoff_debugging_seen
)
15390 flag_keep_locals
= 1;
15394 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
15395 the corresponding LO16 reloc. This is called before md_apply_fix and
15396 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
15397 relocation operators.
15399 For our purposes, a %lo() expression matches a %got() or %hi()
15402 (a) it refers to the same symbol; and
15403 (b) the offset applied in the %lo() expression is no lower than
15404 the offset applied in the %got() or %hi().
15406 (b) allows us to cope with code like:
15409 lh $4,%lo(foo+2)($4)
15411 ...which is legal on RELA targets, and has a well-defined behaviour
15412 if the user knows that adding 2 to "foo" will not induce a carry to
15415 When several %lo()s match a particular %got() or %hi(), we use the
15416 following rules to distinguish them:
15418 (1) %lo()s with smaller offsets are a better match than %lo()s with
15421 (2) %lo()s with no matching %got() or %hi() are better than those
15422 that already have a matching %got() or %hi().
15424 (3) later %lo()s are better than earlier %lo()s.
15426 These rules are applied in order.
15428 (1) means, among other things, that %lo()s with identical offsets are
15429 chosen if they exist.
15431 (2) means that we won't associate several high-part relocations with
15432 the same low-part relocation unless there's no alternative. Having
15433 several high parts for the same low part is a GNU extension; this rule
15434 allows careful users to avoid it.
15436 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
15437 with the last high-part relocation being at the front of the list.
15438 It therefore makes sense to choose the last matching low-part
15439 relocation, all other things being equal. It's also easier
15440 to code that way. */
15443 mips_frob_file (void)
15445 struct mips_hi_fixup
*l
;
15446 bfd_reloc_code_real_type looking_for_rtype
= BFD_RELOC_UNUSED
;
15448 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
15450 segment_info_type
*seginfo
;
15451 bfd_boolean matched_lo_p
;
15452 fixS
**hi_pos
, **lo_pos
, **pos
;
15454 gas_assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
15456 /* If a GOT16 relocation turns out to be against a global symbol,
15457 there isn't supposed to be a matching LO. Ignore %gots against
15458 constants; we'll report an error for those later. */
15459 if (got16_reloc_p (l
->fixp
->fx_r_type
)
15460 && !(l
->fixp
->fx_addsy
15461 && pic_need_relax (l
->fixp
->fx_addsy
)))
15464 /* Check quickly whether the next fixup happens to be a matching %lo. */
15465 if (fixup_has_matching_lo_p (l
->fixp
))
15468 seginfo
= seg_info (l
->seg
);
15470 /* Set HI_POS to the position of this relocation in the chain.
15471 Set LO_POS to the position of the chosen low-part relocation.
15472 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
15473 relocation that matches an immediately-preceding high-part
15477 matched_lo_p
= FALSE
;
15478 looking_for_rtype
= matching_lo_reloc (l
->fixp
->fx_r_type
);
15480 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
15482 if (*pos
== l
->fixp
)
15485 if ((*pos
)->fx_r_type
== looking_for_rtype
15486 && symbol_same_p ((*pos
)->fx_addsy
, l
->fixp
->fx_addsy
)
15487 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
15489 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
15491 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
15494 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
15495 && fixup_has_matching_lo_p (*pos
));
15498 /* If we found a match, remove the high-part relocation from its
15499 current position and insert it before the low-part relocation.
15500 Make the offsets match so that fixup_has_matching_lo_p()
15503 We don't warn about unmatched high-part relocations since some
15504 versions of gcc have been known to emit dead "lui ...%hi(...)"
15506 if (lo_pos
!= NULL
)
15508 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
15509 if (l
->fixp
->fx_next
!= *lo_pos
)
15511 *hi_pos
= l
->fixp
->fx_next
;
15512 l
->fixp
->fx_next
= *lo_pos
;
15520 mips_force_relocation (fixS
*fixp
)
15522 if (generic_force_reloc (fixp
))
15525 /* We want to keep BFD_RELOC_MICROMIPS_*_PCREL_S1 relocation,
15526 so that the linker relaxation can update targets. */
15527 if (fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
15528 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
15529 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
)
15532 /* We want to keep BFD_RELOC_16_PCREL_S2 BFD_RELOC_MIPS_21_PCREL_S2
15533 and BFD_RELOC_MIPS_26_PCREL_S2 relocations against MIPS16 and
15534 microMIPS symbols so that we can do cross-mode branch diagnostics
15535 and BAL to JALX conversion by the linker. */
15536 if ((fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15537 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15538 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
)
15540 && ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixp
->fx_addsy
)))
15543 /* We want all PC-relative relocations to be kept for R6 relaxation. */
15544 if (ISA_IS_R6 (file_mips_opts
.isa
)
15545 && (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
15546 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
15547 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
15548 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
15549 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
15550 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
15551 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
))
15557 /* Implement TC_FORCE_RELOCATION_ABS. */
15560 mips_force_relocation_abs (fixS
*fixp
)
15562 if (generic_force_reloc (fixp
))
15565 /* These relocations do not have enough bits in the in-place addend
15566 to hold an arbitrary absolute section's offset. */
15567 if (HAVE_IN_PLACE_ADDENDS
&& limited_pcrel_reloc_p (fixp
->fx_r_type
))
15573 /* Read the instruction associated with RELOC from BUF. */
15575 static unsigned int
15576 read_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
)
15578 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15579 return read_compressed_insn (buf
, 4);
15581 return read_insn (buf
);
15584 /* Write instruction INSN to BUF, given that it has been relocated
15588 write_reloc_insn (char *buf
, bfd_reloc_code_real_type reloc
,
15589 unsigned long insn
)
15591 if (mips16_reloc_p (reloc
) || micromips_reloc_p (reloc
))
15592 write_compressed_insn (buf
, insn
, 4);
15594 write_insn (buf
, insn
);
15597 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15598 to a symbol in another ISA mode, which cannot be converted to JALX. */
15601 fix_bad_cross_mode_jump_p (fixS
*fixP
)
15603 unsigned long opcode
;
15607 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15610 other
= S_GET_OTHER (fixP
->fx_addsy
);
15611 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15612 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15613 switch (fixP
->fx_r_type
)
15615 case BFD_RELOC_MIPS_JMP
:
15616 return opcode
!= 0x1d && opcode
!= 0x03 && ELF_ST_IS_COMPRESSED (other
);
15617 case BFD_RELOC_MICROMIPS_JMP
:
15618 return opcode
!= 0x3c && opcode
!= 0x3d && !ELF_ST_IS_MICROMIPS (other
);
15624 /* Return TRUE if the instruction pointed to by FIXP is an invalid JALX
15625 jump to a symbol in the same ISA mode. */
15628 fix_bad_same_mode_jalx_p (fixS
*fixP
)
15630 unsigned long opcode
;
15634 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15637 other
= S_GET_OTHER (fixP
->fx_addsy
);
15638 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15639 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 26;
15640 switch (fixP
->fx_r_type
)
15642 case BFD_RELOC_MIPS_JMP
:
15643 return opcode
== 0x1d && !ELF_ST_IS_COMPRESSED (other
);
15644 case BFD_RELOC_MIPS16_JMP
:
15645 return opcode
== 0x07 && ELF_ST_IS_COMPRESSED (other
);
15646 case BFD_RELOC_MICROMIPS_JMP
:
15647 return opcode
== 0x3c && ELF_ST_IS_COMPRESSED (other
);
15653 /* Return TRUE if the instruction pointed to by FIXP is an invalid jump
15654 to a symbol whose value plus addend is not aligned according to the
15655 ultimate (after linker relaxation) jump instruction's immediate field
15656 requirement, either to (1 << SHIFT), or, for jumps from microMIPS to
15657 regular MIPS code, to (1 << 2). */
15660 fix_bad_misaligned_jump_p (fixS
*fixP
, int shift
)
15662 bfd_boolean micro_to_mips_p
;
15666 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15669 other
= S_GET_OTHER (fixP
->fx_addsy
);
15670 val
= S_GET_VALUE (fixP
->fx_addsy
) | ELF_ST_IS_COMPRESSED (other
);
15671 val
+= fixP
->fx_offset
;
15672 micro_to_mips_p
= (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15673 && !ELF_ST_IS_MICROMIPS (other
));
15674 return ((val
& ((1 << (micro_to_mips_p
? 2 : shift
)) - 1))
15675 != ELF_ST_IS_COMPRESSED (other
));
15678 /* Return TRUE if the instruction pointed to by FIXP is an invalid branch
15679 to a symbol whose annotation indicates another ISA mode. For absolute
15680 symbols check the ISA bit instead.
15682 We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
15683 symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
15684 MIPS symbols and associated with BAL instructions as these instructions
15685 may be converted to JALX by the linker. */
15688 fix_bad_cross_mode_branch_p (fixS
*fixP
)
15690 bfd_boolean absolute_p
;
15691 unsigned long opcode
;
15697 if (mips_ignore_branch_isa
)
15700 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15703 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15704 absolute_p
= bfd_is_abs_section (symsec
);
15706 val
= S_GET_VALUE (fixP
->fx_addsy
) + fixP
->fx_offset
;
15707 other
= S_GET_OTHER (fixP
->fx_addsy
);
15709 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15710 opcode
= read_reloc_insn (buf
, fixP
->fx_r_type
) >> 16;
15711 switch (fixP
->fx_r_type
)
15713 case BFD_RELOC_16_PCREL_S2
:
15714 return ((absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
))
15715 && opcode
!= 0x0411);
15716 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15717 return ((absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
))
15718 && opcode
!= 0x4060);
15719 case BFD_RELOC_MIPS_21_PCREL_S2
:
15720 case BFD_RELOC_MIPS_26_PCREL_S2
:
15721 return absolute_p
? val
& 1 : ELF_ST_IS_COMPRESSED (other
);
15722 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15723 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MIPS16 (other
);
15724 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15725 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15726 return absolute_p
? !(val
& 1) : !ELF_ST_IS_MICROMIPS (other
);
15732 /* Return TRUE if the symbol plus addend associated with a regular MIPS
15733 branch instruction pointed to by FIXP is not aligned according to the
15734 branch instruction's immediate field requirement. We need the addend
15735 to preserve the ISA bit and also the sum must not have bit 2 set. We
15736 must explicitly OR in the ISA bit from symbol annotation as the bit
15737 won't be set in the symbol's value then. */
15740 fix_bad_misaligned_branch_p (fixS
*fixP
)
15742 bfd_boolean absolute_p
;
15749 if (!fixP
->fx_addsy
|| S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
15752 symsec
= S_GET_SEGMENT (fixP
->fx_addsy
);
15753 absolute_p
= bfd_is_abs_section (symsec
);
15755 val
= S_GET_VALUE (fixP
->fx_addsy
);
15756 other
= S_GET_OTHER (fixP
->fx_addsy
);
15757 off
= fixP
->fx_offset
;
15759 isa_bit
= absolute_p
? (val
+ off
) & 1 : ELF_ST_IS_COMPRESSED (other
);
15760 val
|= ELF_ST_IS_COMPRESSED (other
);
15762 return (val
& 0x3) != isa_bit
;
15765 /* Calculate the relocation target by masking off ISA mode bit before
15766 combining symbol and addend. */
15769 fix_bad_misaligned_address (fixS
*fixP
)
15774 gas_assert (fixP
!= NULL
&& fixP
->fx_addsy
!= NULL
);
15775 val
= S_GET_VALUE (fixP
->fx_addsy
);
15776 off
= fixP
->fx_offset
;
15777 isa_mode
= (ELF_ST_IS_COMPRESSED (S_GET_OTHER (fixP
->fx_addsy
))
15780 return ((val
& ~isa_mode
) + off
);
15783 /* Make the necessary checks on a regular MIPS branch pointed to by FIXP
15784 and its calculated value VAL. */
15787 fix_validate_branch (fixS
*fixP
, valueT val
)
15789 if (fixP
->fx_done
&& (val
& 0x3) != 0)
15790 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15791 _("branch to misaligned address (0x%lx)"),
15792 (long) (val
+ md_pcrel_from (fixP
)));
15793 else if (fix_bad_cross_mode_branch_p (fixP
))
15794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15795 _("branch to a symbol in another ISA mode"));
15796 else if (fix_bad_misaligned_branch_p (fixP
))
15797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15798 _("branch to misaligned address (0x%lx)"),
15799 (long) fix_bad_misaligned_address (fixP
));
15800 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x3) != 0)
15801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15802 _("cannot encode misaligned addend "
15803 "in the relocatable field (0x%lx)"),
15804 (long) fixP
->fx_offset
);
15807 /* Apply a fixup to the object file. */
15810 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
15813 unsigned long insn
;
15814 reloc_howto_type
*howto
;
15816 if (fixP
->fx_pcrel
)
15817 switch (fixP
->fx_r_type
)
15819 case BFD_RELOC_16_PCREL_S2
:
15820 case BFD_RELOC_MIPS16_16_PCREL_S1
:
15821 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
15822 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
15823 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
15824 case BFD_RELOC_32_PCREL
:
15825 case BFD_RELOC_MIPS_21_PCREL_S2
:
15826 case BFD_RELOC_MIPS_26_PCREL_S2
:
15827 case BFD_RELOC_MIPS_18_PCREL_S3
:
15828 case BFD_RELOC_MIPS_19_PCREL_S2
:
15829 case BFD_RELOC_HI16_S_PCREL
:
15830 case BFD_RELOC_LO16_PCREL
:
15834 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
15838 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15839 _("PC-relative reference to a different section"));
15843 /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations
15844 that have no MIPS ELF equivalent. */
15845 if (fixP
->fx_r_type
!= BFD_RELOC_8
)
15847 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
15852 gas_assert (fixP
->fx_size
== 2
15853 || fixP
->fx_size
== 4
15854 || fixP
->fx_r_type
== BFD_RELOC_8
15855 || fixP
->fx_r_type
== BFD_RELOC_16
15856 || fixP
->fx_r_type
== BFD_RELOC_64
15857 || fixP
->fx_r_type
== BFD_RELOC_CTOR
15858 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
15859 || fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_SUB
15860 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
15861 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
15862 || fixP
->fx_r_type
== BFD_RELOC_MIPS_TLS_DTPREL64
15863 || fixP
->fx_r_type
== BFD_RELOC_NONE
);
15865 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
15867 /* Don't treat parts of a composite relocation as done. There are two
15870 (1) The second and third parts will be against 0 (RSS_UNDEF) but
15871 should nevertheless be emitted if the first part is.
15873 (2) In normal usage, composite relocations are never assembly-time
15874 constants. The easiest way of dealing with the pathological
15875 exceptions is to generate a relocation against STN_UNDEF and
15876 leave everything up to the linker. */
15877 if (fixP
->fx_addsy
== NULL
&& !fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
15880 switch (fixP
->fx_r_type
)
15882 case BFD_RELOC_MIPS_TLS_GD
:
15883 case BFD_RELOC_MIPS_TLS_LDM
:
15884 case BFD_RELOC_MIPS_TLS_DTPREL32
:
15885 case BFD_RELOC_MIPS_TLS_DTPREL64
:
15886 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
15887 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
15888 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
15889 case BFD_RELOC_MIPS_TLS_TPREL32
:
15890 case BFD_RELOC_MIPS_TLS_TPREL64
:
15891 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
15892 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
15893 case BFD_RELOC_MICROMIPS_TLS_GD
:
15894 case BFD_RELOC_MICROMIPS_TLS_LDM
:
15895 case BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
:
15896 case BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
:
15897 case BFD_RELOC_MICROMIPS_TLS_GOTTPREL
:
15898 case BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
:
15899 case BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
:
15900 case BFD_RELOC_MIPS16_TLS_GD
:
15901 case BFD_RELOC_MIPS16_TLS_LDM
:
15902 case BFD_RELOC_MIPS16_TLS_DTPREL_HI16
:
15903 case BFD_RELOC_MIPS16_TLS_DTPREL_LO16
:
15904 case BFD_RELOC_MIPS16_TLS_GOTTPREL
:
15905 case BFD_RELOC_MIPS16_TLS_TPREL_HI16
:
15906 case BFD_RELOC_MIPS16_TLS_TPREL_LO16
:
15907 if (fixP
->fx_addsy
)
15908 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
15910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15911 _("TLS relocation against a constant"));
15914 case BFD_RELOC_MIPS_JMP
:
15915 case BFD_RELOC_MIPS16_JMP
:
15916 case BFD_RELOC_MICROMIPS_JMP
:
15920 gas_assert (!fixP
->fx_done
);
15922 /* Shift is 2, unusually, for microMIPS JALX. */
15923 if (fixP
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
15924 && (read_compressed_insn (buf
, 4) >> 26) != 0x3c)
15929 if (fix_bad_cross_mode_jump_p (fixP
))
15930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15931 _("jump to a symbol in another ISA mode"));
15932 else if (fix_bad_same_mode_jalx_p (fixP
))
15933 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15934 _("JALX to a symbol in the same ISA mode"));
15935 else if (fix_bad_misaligned_jump_p (fixP
, shift
))
15936 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15937 _("jump to misaligned address (0x%lx)"),
15938 (long) fix_bad_misaligned_address (fixP
));
15939 else if (HAVE_IN_PLACE_ADDENDS
15940 && (fixP
->fx_offset
& ((1 << shift
) - 1)) != 0)
15941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
15942 _("cannot encode misaligned addend "
15943 "in the relocatable field (0x%lx)"),
15944 (long) fixP
->fx_offset
);
15946 /* Fall through. */
15948 case BFD_RELOC_MIPS_SHIFT5
:
15949 case BFD_RELOC_MIPS_SHIFT6
:
15950 case BFD_RELOC_MIPS_GOT_DISP
:
15951 case BFD_RELOC_MIPS_GOT_PAGE
:
15952 case BFD_RELOC_MIPS_GOT_OFST
:
15953 case BFD_RELOC_MIPS_SUB
:
15954 case BFD_RELOC_MIPS_INSERT_A
:
15955 case BFD_RELOC_MIPS_INSERT_B
:
15956 case BFD_RELOC_MIPS_DELETE
:
15957 case BFD_RELOC_MIPS_HIGHEST
:
15958 case BFD_RELOC_MIPS_HIGHER
:
15959 case BFD_RELOC_MIPS_SCN_DISP
:
15960 case BFD_RELOC_MIPS_REL16
:
15961 case BFD_RELOC_MIPS_RELGOT
:
15962 case BFD_RELOC_MIPS_JALR
:
15963 case BFD_RELOC_HI16
:
15964 case BFD_RELOC_HI16_S
:
15965 case BFD_RELOC_LO16
:
15966 case BFD_RELOC_GPREL16
:
15967 case BFD_RELOC_MIPS_LITERAL
:
15968 case BFD_RELOC_MIPS_CALL16
:
15969 case BFD_RELOC_MIPS_GOT16
:
15970 case BFD_RELOC_GPREL32
:
15971 case BFD_RELOC_MIPS_GOT_HI16
:
15972 case BFD_RELOC_MIPS_GOT_LO16
:
15973 case BFD_RELOC_MIPS_CALL_HI16
:
15974 case BFD_RELOC_MIPS_CALL_LO16
:
15975 case BFD_RELOC_HI16_S_PCREL
:
15976 case BFD_RELOC_LO16_PCREL
:
15977 case BFD_RELOC_MIPS16_GPREL
:
15978 case BFD_RELOC_MIPS16_GOT16
:
15979 case BFD_RELOC_MIPS16_CALL16
:
15980 case BFD_RELOC_MIPS16_HI16
:
15981 case BFD_RELOC_MIPS16_HI16_S
:
15982 case BFD_RELOC_MIPS16_LO16
:
15983 case BFD_RELOC_MICROMIPS_GOT_DISP
:
15984 case BFD_RELOC_MICROMIPS_GOT_PAGE
:
15985 case BFD_RELOC_MICROMIPS_GOT_OFST
:
15986 case BFD_RELOC_MICROMIPS_SUB
:
15987 case BFD_RELOC_MICROMIPS_HIGHEST
:
15988 case BFD_RELOC_MICROMIPS_HIGHER
:
15989 case BFD_RELOC_MICROMIPS_SCN_DISP
:
15990 case BFD_RELOC_MICROMIPS_JALR
:
15991 case BFD_RELOC_MICROMIPS_HI16
:
15992 case BFD_RELOC_MICROMIPS_HI16_S
:
15993 case BFD_RELOC_MICROMIPS_LO16
:
15994 case BFD_RELOC_MICROMIPS_GPREL16
:
15995 case BFD_RELOC_MICROMIPS_LITERAL
:
15996 case BFD_RELOC_MICROMIPS_CALL16
:
15997 case BFD_RELOC_MICROMIPS_GOT16
:
15998 case BFD_RELOC_MICROMIPS_GOT_HI16
:
15999 case BFD_RELOC_MICROMIPS_GOT_LO16
:
16000 case BFD_RELOC_MICROMIPS_CALL_HI16
:
16001 case BFD_RELOC_MICROMIPS_CALL_LO16
:
16002 case BFD_RELOC_MIPS_EH
:
16007 if (calculate_reloc (fixP
->fx_r_type
, *valP
, &value
))
16009 insn
= read_reloc_insn (buf
, fixP
->fx_r_type
);
16010 if (mips16_reloc_p (fixP
->fx_r_type
))
16011 insn
|= mips16_immed_extend (value
, 16);
16013 insn
|= (value
& 0xffff);
16014 write_reloc_insn (buf
, fixP
->fx_r_type
, insn
);
16017 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16018 _("unsupported constant in relocation"));
16023 /* This is handled like BFD_RELOC_32, but we output a sign
16024 extended value if we are only 32 bits. */
16027 if (8 <= sizeof (valueT
))
16028 md_number_to_chars (buf
, *valP
, 8);
16033 if ((*valP
& 0x80000000) != 0)
16037 md_number_to_chars (buf
+ (target_big_endian
? 4 : 0), *valP
, 4);
16038 md_number_to_chars (buf
+ (target_big_endian
? 0 : 4), hiv
, 4);
16043 case BFD_RELOC_RVA
:
16045 case BFD_RELOC_32_PCREL
:
16048 /* If we are deleting this reloc entry, we must fill in the
16049 value now. This can happen if we have a .word which is not
16050 resolved when it appears but is later defined. */
16052 md_number_to_chars (buf
, *valP
, fixP
->fx_size
);
16055 case BFD_RELOC_MIPS_21_PCREL_S2
:
16056 fix_validate_branch (fixP
, *valP
);
16057 if (!fixP
->fx_done
)
16060 if (*valP
+ 0x400000 <= 0x7fffff)
16062 insn
= read_insn (buf
);
16063 insn
|= (*valP
>> 2) & 0x1fffff;
16064 write_insn (buf
, insn
);
16067 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16068 _("branch out of range"));
16071 case BFD_RELOC_MIPS_26_PCREL_S2
:
16072 fix_validate_branch (fixP
, *valP
);
16073 if (!fixP
->fx_done
)
16076 if (*valP
+ 0x8000000 <= 0xfffffff)
16078 insn
= read_insn (buf
);
16079 insn
|= (*valP
>> 2) & 0x3ffffff;
16080 write_insn (buf
, insn
);
16083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16084 _("branch out of range"));
16087 case BFD_RELOC_MIPS_18_PCREL_S3
:
16088 if (fixP
->fx_addsy
&& (S_GET_VALUE (fixP
->fx_addsy
) & 0x7) != 0)
16089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16090 _("PC-relative access using misaligned symbol (%lx)"),
16091 (long) S_GET_VALUE (fixP
->fx_addsy
));
16092 if ((fixP
->fx_offset
& 0x7) != 0)
16093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16094 _("PC-relative access using misaligned offset (%lx)"),
16095 (long) fixP
->fx_offset
);
16096 if (!fixP
->fx_done
)
16099 if (*valP
+ 0x100000 <= 0x1fffff)
16101 insn
= read_insn (buf
);
16102 insn
|= (*valP
>> 3) & 0x3ffff;
16103 write_insn (buf
, insn
);
16106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16107 _("PC-relative access out of range"));
16110 case BFD_RELOC_MIPS_19_PCREL_S2
:
16111 if ((*valP
& 0x3) != 0)
16112 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16113 _("PC-relative access to misaligned address (%lx)"),
16115 if (!fixP
->fx_done
)
16118 if (*valP
+ 0x100000 <= 0x1fffff)
16120 insn
= read_insn (buf
);
16121 insn
|= (*valP
>> 2) & 0x7ffff;
16122 write_insn (buf
, insn
);
16125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16126 _("PC-relative access out of range"));
16129 case BFD_RELOC_16_PCREL_S2
:
16130 fix_validate_branch (fixP
, *valP
);
16132 /* We need to save the bits in the instruction since fixup_segment()
16133 might be deleting the relocation entry (i.e., a branch within
16134 the current segment). */
16135 if (! fixP
->fx_done
)
16138 /* Update old instruction data. */
16139 insn
= read_insn (buf
);
16141 if (*valP
+ 0x20000 <= 0x3ffff)
16143 insn
|= (*valP
>> 2) & 0xffff;
16144 write_insn (buf
, insn
);
16146 else if (fixP
->fx_tcbit2
16148 && fixP
->fx_frag
->fr_address
>= text_section
->vma
16149 && (fixP
->fx_frag
->fr_address
16150 < text_section
->vma
+ bfd_section_size (text_section
))
16151 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
16152 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
16153 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
16155 /* The branch offset is too large. If this is an
16156 unconditional branch, and we are not generating PIC code,
16157 we can convert it to an absolute jump instruction. */
16158 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
16159 insn
= 0x0c000000; /* jal */
16161 insn
= 0x08000000; /* j */
16162 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
16164 fixP
->fx_addsy
= section_symbol (text_section
);
16165 *valP
+= md_pcrel_from (fixP
);
16166 write_insn (buf
, insn
);
16170 /* If we got here, we have branch-relaxation disabled,
16171 and there's nothing we can do to fix this instruction
16172 without turning it into a longer sequence. */
16173 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16174 _("branch out of range"));
16178 case BFD_RELOC_MIPS16_16_PCREL_S1
:
16179 case BFD_RELOC_MICROMIPS_7_PCREL_S1
:
16180 case BFD_RELOC_MICROMIPS_10_PCREL_S1
:
16181 case BFD_RELOC_MICROMIPS_16_PCREL_S1
:
16182 gas_assert (!fixP
->fx_done
);
16183 if (fix_bad_cross_mode_branch_p (fixP
))
16184 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16185 _("branch to a symbol in another ISA mode"));
16186 else if (fixP
->fx_addsy
16187 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
16188 && !bfd_is_abs_section (S_GET_SEGMENT (fixP
->fx_addsy
))
16189 && (fixP
->fx_offset
& 0x1) != 0)
16190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16191 _("branch to misaligned address (0x%lx)"),
16192 (long) fix_bad_misaligned_address (fixP
));
16193 else if (HAVE_IN_PLACE_ADDENDS
&& (fixP
->fx_offset
& 0x1) != 0)
16194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
16195 _("cannot encode misaligned addend "
16196 "in the relocatable field (0x%lx)"),
16197 (long) fixP
->fx_offset
);
16200 case BFD_RELOC_VTABLE_INHERIT
:
16203 && !S_IS_DEFINED (fixP
->fx_addsy
)
16204 && !S_IS_WEAK (fixP
->fx_addsy
))
16205 S_SET_WEAK (fixP
->fx_addsy
);
16208 case BFD_RELOC_NONE
:
16209 case BFD_RELOC_VTABLE_ENTRY
:
16217 /* Remember value for tc_gen_reloc. */
16218 fixP
->fx_addnumber
= *valP
;
16228 c
= get_symbol_name (&name
);
16229 p
= (symbolS
*) symbol_find_or_make (name
);
16230 (void) restore_line_pointer (c
);
16234 /* Align the current frag to a given power of two. If a particular
16235 fill byte should be used, FILL points to an integer that contains
16236 that byte, otherwise FILL is null.
16238 This function used to have the comment:
16240 The MIPS assembler also automatically adjusts any preceding label.
16242 The implementation therefore applied the adjustment to a maximum of
16243 one label. However, other label adjustments are applied to batches
16244 of labels, and adjusting just one caused problems when new labels
16245 were added for the sake of debugging or unwind information.
16246 We therefore adjust all preceding labels (given as LABELS) instead. */
16249 mips_align (int to
, int *fill
, struct insn_label_list
*labels
)
16251 mips_emit_delays ();
16252 mips_record_compressed_mode ();
16253 if (fill
== NULL
&& subseg_text_p (now_seg
))
16254 frag_align_code (to
, 0);
16256 frag_align (to
, fill
? *fill
: 0, 0);
16257 record_alignment (now_seg
, to
);
16258 mips_move_labels (labels
, subseg_text_p (now_seg
));
16261 /* Align to a given power of two. .align 0 turns off the automatic
16262 alignment used by the data creating pseudo-ops. */
16265 s_align (int x ATTRIBUTE_UNUSED
)
16267 int temp
, fill_value
, *fill_ptr
;
16268 long max_alignment
= 28;
16270 /* o Note that the assembler pulls down any immediately preceding label
16271 to the aligned address.
16272 o It's not documented but auto alignment is reinstated by
16273 a .align pseudo instruction.
16274 o Note also that after auto alignment is turned off the mips assembler
16275 issues an error on attempt to assemble an improperly aligned data item.
16278 temp
= get_absolute_expression ();
16279 if (temp
> max_alignment
)
16280 as_bad (_("alignment too large, %d assumed"), temp
= max_alignment
);
16283 as_warn (_("alignment negative, 0 assumed"));
16286 if (*input_line_pointer
== ',')
16288 ++input_line_pointer
;
16289 fill_value
= get_absolute_expression ();
16290 fill_ptr
= &fill_value
;
16296 segment_info_type
*si
= seg_info (now_seg
);
16297 struct insn_label_list
*l
= si
->label_list
;
16298 /* Auto alignment should be switched on by next section change. */
16300 mips_align (temp
, fill_ptr
, l
);
16307 demand_empty_rest_of_line ();
16311 s_change_sec (int sec
)
16315 /* The ELF backend needs to know that we are changing sections, so
16316 that .previous works correctly. We could do something like check
16317 for an obj_section_change_hook macro, but that might be confusing
16318 as it would not be appropriate to use it in the section changing
16319 functions in read.c, since obj-elf.c intercepts those. FIXME:
16320 This should be cleaner, somehow. */
16321 obj_elf_section_change_hook ();
16323 mips_emit_delays ();
16334 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
16335 demand_empty_rest_of_line ();
16339 seg
= subseg_new (RDATA_SECTION_NAME
,
16340 (subsegT
) get_absolute_expression ());
16341 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_READONLY
16342 | SEC_RELOC
| SEC_DATA
));
16343 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16344 record_alignment (seg
, 4);
16345 demand_empty_rest_of_line ();
16349 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
16350 bfd_set_section_flags (seg
, (SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
16351 | SEC_DATA
| SEC_SMALL_DATA
));
16352 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16353 record_alignment (seg
, 4);
16354 demand_empty_rest_of_line ();
16358 seg
= subseg_new (".sbss", (subsegT
) get_absolute_expression ());
16359 bfd_set_section_flags (seg
, SEC_ALLOC
| SEC_SMALL_DATA
);
16360 if (strncmp (TARGET_OS
, "elf", 3) != 0)
16361 record_alignment (seg
, 4);
16362 demand_empty_rest_of_line ();
16370 s_change_section (int ignore ATTRIBUTE_UNUSED
)
16373 char *section_name
;
16378 int section_entry_size
;
16379 int section_alignment
;
16381 saved_ilp
= input_line_pointer
;
16382 endc
= get_symbol_name (§ion_name
);
16383 c
= (endc
== '"' ? input_line_pointer
[1] : endc
);
16385 next_c
= input_line_pointer
[(endc
== '"' ? 2 : 1)];
16387 /* Do we have .section Name<,"flags">? */
16388 if (c
!= ',' || (c
== ',' && next_c
== '"'))
16390 /* Just after name is now '\0'. */
16391 (void) restore_line_pointer (endc
);
16392 input_line_pointer
= saved_ilp
;
16393 obj_elf_section (ignore
);
16397 section_name
= xstrdup (section_name
);
16398 c
= restore_line_pointer (endc
);
16400 input_line_pointer
++;
16402 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
16404 section_type
= get_absolute_expression ();
16408 if (*input_line_pointer
++ == ',')
16409 section_flag
= get_absolute_expression ();
16413 if (*input_line_pointer
++ == ',')
16414 section_entry_size
= get_absolute_expression ();
16416 section_entry_size
= 0;
16418 if (*input_line_pointer
++ == ',')
16419 section_alignment
= get_absolute_expression ();
16421 section_alignment
= 0;
16423 /* FIXME: really ignore? */
16424 (void) section_alignment
;
16426 /* When using the generic form of .section (as implemented by obj-elf.c),
16427 there's no way to set the section type to SHT_MIPS_DWARF. Users have
16428 traditionally had to fall back on the more common @progbits instead.
16430 There's nothing really harmful in this, since bfd will correct
16431 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
16432 means that, for backwards compatibility, the special_section entries
16433 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
16435 Even so, we shouldn't force users of the MIPS .section syntax to
16436 incorrectly label the sections as SHT_PROGBITS. The best compromise
16437 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
16438 generic type-checking code. */
16439 if (section_type
== SHT_MIPS_DWARF
)
16440 section_type
= SHT_PROGBITS
;
16442 obj_elf_change_section (section_name
, section_type
, section_flag
,
16443 section_entry_size
, 0, 0, 0);
16445 if (now_seg
->name
!= section_name
)
16446 free (section_name
);
16450 mips_enable_auto_align (void)
16456 s_cons (int log_size
)
16458 segment_info_type
*si
= seg_info (now_seg
);
16459 struct insn_label_list
*l
= si
->label_list
;
16461 mips_emit_delays ();
16462 if (log_size
> 0 && auto_align
)
16463 mips_align (log_size
, 0, l
);
16464 cons (1 << log_size
);
16465 mips_clear_insn_labels ();
16469 s_float_cons (int type
)
16471 segment_info_type
*si
= seg_info (now_seg
);
16472 struct insn_label_list
*l
= si
->label_list
;
16474 mips_emit_delays ();
16479 mips_align (3, 0, l
);
16481 mips_align (2, 0, l
);
16485 mips_clear_insn_labels ();
16488 /* Handle .globl. We need to override it because on Irix 5 you are
16491 where foo is an undefined symbol, to mean that foo should be
16492 considered to be the address of a function. */
16495 s_mips_globl (int x ATTRIBUTE_UNUSED
)
16503 c
= get_symbol_name (&name
);
16504 symbolP
= symbol_find_or_make (name
);
16505 S_SET_EXTERNAL (symbolP
);
16507 *input_line_pointer
= c
;
16508 SKIP_WHITESPACE_AFTER_NAME ();
16510 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
16511 && (*input_line_pointer
!= ','))
16516 c
= get_symbol_name (&secname
);
16517 sec
= bfd_get_section_by_name (stdoutput
, secname
);
16519 as_bad (_("%s: no such section"), secname
);
16520 (void) restore_line_pointer (c
);
16522 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
16523 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
16526 c
= *input_line_pointer
;
16529 input_line_pointer
++;
16530 SKIP_WHITESPACE ();
16531 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
16537 demand_empty_rest_of_line ();
16541 /* The Irix 5 and 6 assemblers set the type of any common symbol and
16542 any undefined non-function symbol to STT_OBJECT. We try to be
16543 compatible, since newer Irix 5 and 6 linkers care. */
16546 mips_frob_symbol (symbolS
*symp ATTRIBUTE_UNUSED
)
16548 /* This late in assembly we can set BSF_OBJECT indiscriminately
16549 and let elf.c:swap_out_syms sort out the symbol type. */
16550 flagword
*flags
= &symbol_get_bfdsym (symp
)->flags
;
16551 if ((*flags
& (BSF_GLOBAL
| BSF_WEAK
)) != 0
16552 || !S_IS_DEFINED (symp
))
16553 *flags
|= BSF_OBJECT
;
16558 s_option (int x ATTRIBUTE_UNUSED
)
16563 c
= get_symbol_name (&opt
);
16567 /* FIXME: What does this mean? */
16569 else if (strncmp (opt
, "pic", 3) == 0 && ISDIGIT (opt
[3]) && opt
[4] == '\0')
16573 i
= atoi (opt
+ 3);
16574 if (i
!= 0 && i
!= 2)
16575 as_bad (_(".option pic%d not supported"), i
);
16576 else if (mips_pic
== VXWORKS_PIC
)
16577 as_bad (_(".option pic%d not supported in VxWorks PIC mode"), i
);
16582 mips_pic
= SVR4_PIC
;
16583 mips_abicalls
= TRUE
;
16586 if (mips_pic
== SVR4_PIC
)
16588 if (g_switch_seen
&& g_switch_value
!= 0)
16589 as_warn (_("-G may not be used with SVR4 PIC code"));
16590 g_switch_value
= 0;
16591 bfd_set_gp_size (stdoutput
, 0);
16595 as_warn (_("unrecognized option \"%s\""), opt
);
16597 (void) restore_line_pointer (c
);
16598 demand_empty_rest_of_line ();
16601 /* This structure is used to hold a stack of .set values. */
16603 struct mips_option_stack
16605 struct mips_option_stack
*next
;
16606 struct mips_set_options options
;
16609 static struct mips_option_stack
*mips_opts_stack
;
16611 /* Return status for .set/.module option handling. */
16613 enum code_option_type
16615 /* Unrecognized option. */
16616 OPTION_TYPE_BAD
= -1,
16618 /* Ordinary option. */
16619 OPTION_TYPE_NORMAL
,
16621 /* ISA changing option. */
16625 /* Handle common .set/.module options. Return status indicating option
16628 static enum code_option_type
16629 parse_code_option (char * name
)
16631 bfd_boolean isa_set
= FALSE
;
16632 const struct mips_ase
*ase
;
16634 if (strncmp (name
, "at=", 3) == 0)
16636 char *s
= name
+ 3;
16638 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, &mips_opts
.at
))
16639 as_bad (_("unrecognized register name `%s'"), s
);
16641 else if (strcmp (name
, "at") == 0)
16642 mips_opts
.at
= ATREG
;
16643 else if (strcmp (name
, "noat") == 0)
16644 mips_opts
.at
= ZERO
;
16645 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
16646 mips_opts
.nomove
= 0;
16647 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
16648 mips_opts
.nomove
= 1;
16649 else if (strcmp (name
, "bopt") == 0)
16650 mips_opts
.nobopt
= 0;
16651 else if (strcmp (name
, "nobopt") == 0)
16652 mips_opts
.nobopt
= 1;
16653 else if (strcmp (name
, "gp=32") == 0)
16655 else if (strcmp (name
, "gp=64") == 0)
16657 else if (strcmp (name
, "fp=32") == 0)
16659 else if (strcmp (name
, "fp=xx") == 0)
16661 else if (strcmp (name
, "fp=64") == 0)
16663 else if (strcmp (name
, "softfloat") == 0)
16664 mips_opts
.soft_float
= 1;
16665 else if (strcmp (name
, "hardfloat") == 0)
16666 mips_opts
.soft_float
= 0;
16667 else if (strcmp (name
, "singlefloat") == 0)
16668 mips_opts
.single_float
= 1;
16669 else if (strcmp (name
, "doublefloat") == 0)
16670 mips_opts
.single_float
= 0;
16671 else if (strcmp (name
, "nooddspreg") == 0)
16672 mips_opts
.oddspreg
= 0;
16673 else if (strcmp (name
, "oddspreg") == 0)
16674 mips_opts
.oddspreg
= 1;
16675 else if (strcmp (name
, "mips16") == 0
16676 || strcmp (name
, "MIPS-16") == 0)
16677 mips_opts
.mips16
= 1;
16678 else if (strcmp (name
, "nomips16") == 0
16679 || strcmp (name
, "noMIPS-16") == 0)
16680 mips_opts
.mips16
= 0;
16681 else if (strcmp (name
, "micromips") == 0)
16682 mips_opts
.micromips
= 1;
16683 else if (strcmp (name
, "nomicromips") == 0)
16684 mips_opts
.micromips
= 0;
16685 else if (name
[0] == 'n'
16687 && (ase
= mips_lookup_ase (name
+ 2)))
16688 mips_set_ase (ase
, &mips_opts
, FALSE
);
16689 else if ((ase
= mips_lookup_ase (name
)))
16690 mips_set_ase (ase
, &mips_opts
, TRUE
);
16691 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
16693 /* Permit the user to change the ISA and architecture on the fly.
16694 Needless to say, misuse can cause serious problems. */
16695 if (strncmp (name
, "arch=", 5) == 0)
16697 const struct mips_cpu_info
*p
;
16699 p
= mips_parse_cpu ("internal use", name
+ 5);
16701 as_bad (_("unknown architecture %s"), name
+ 5);
16704 mips_opts
.arch
= p
->cpu
;
16705 mips_opts
.isa
= p
->isa
;
16707 mips_opts
.init_ase
= p
->ase
;
16710 else if (strncmp (name
, "mips", 4) == 0)
16712 const struct mips_cpu_info
*p
;
16714 p
= mips_parse_cpu ("internal use", name
);
16716 as_bad (_("unknown ISA level %s"), name
+ 4);
16719 mips_opts
.arch
= p
->cpu
;
16720 mips_opts
.isa
= p
->isa
;
16722 mips_opts
.init_ase
= p
->ase
;
16726 as_bad (_("unknown ISA or architecture %s"), name
);
16728 else if (strcmp (name
, "autoextend") == 0)
16729 mips_opts
.noautoextend
= 0;
16730 else if (strcmp (name
, "noautoextend") == 0)
16731 mips_opts
.noautoextend
= 1;
16732 else if (strcmp (name
, "insn32") == 0)
16733 mips_opts
.insn32
= TRUE
;
16734 else if (strcmp (name
, "noinsn32") == 0)
16735 mips_opts
.insn32
= FALSE
;
16736 else if (strcmp (name
, "sym32") == 0)
16737 mips_opts
.sym32
= TRUE
;
16738 else if (strcmp (name
, "nosym32") == 0)
16739 mips_opts
.sym32
= FALSE
;
16741 return OPTION_TYPE_BAD
;
16743 return isa_set
? OPTION_TYPE_ISA
: OPTION_TYPE_NORMAL
;
16746 /* Handle the .set pseudo-op. */
16749 s_mipsset (int x ATTRIBUTE_UNUSED
)
16751 enum code_option_type type
= OPTION_TYPE_NORMAL
;
16752 char *name
= input_line_pointer
, ch
;
16754 file_mips_check_options ();
16756 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16757 ++input_line_pointer
;
16758 ch
= *input_line_pointer
;
16759 *input_line_pointer
= '\0';
16761 if (strchr (name
, ','))
16763 /* Generic ".set" directive; use the generic handler. */
16764 *input_line_pointer
= ch
;
16765 input_line_pointer
= name
;
16770 if (strcmp (name
, "reorder") == 0)
16772 if (mips_opts
.noreorder
)
16775 else if (strcmp (name
, "noreorder") == 0)
16777 if (!mips_opts
.noreorder
)
16778 start_noreorder ();
16780 else if (strcmp (name
, "macro") == 0)
16781 mips_opts
.warn_about_macros
= 0;
16782 else if (strcmp (name
, "nomacro") == 0)
16784 if (mips_opts
.noreorder
== 0)
16785 as_bad (_("`noreorder' must be set before `nomacro'"));
16786 mips_opts
.warn_about_macros
= 1;
16788 else if (strcmp (name
, "gp=default") == 0)
16789 mips_opts
.gp
= file_mips_opts
.gp
;
16790 else if (strcmp (name
, "fp=default") == 0)
16791 mips_opts
.fp
= file_mips_opts
.fp
;
16792 else if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
16794 mips_opts
.isa
= file_mips_opts
.isa
;
16795 mips_opts
.arch
= file_mips_opts
.arch
;
16796 mips_opts
.init_ase
= file_mips_opts
.init_ase
;
16797 mips_opts
.gp
= file_mips_opts
.gp
;
16798 mips_opts
.fp
= file_mips_opts
.fp
;
16800 else if (strcmp (name
, "push") == 0)
16802 struct mips_option_stack
*s
;
16804 s
= XNEW (struct mips_option_stack
);
16805 s
->next
= mips_opts_stack
;
16806 s
->options
= mips_opts
;
16807 mips_opts_stack
= s
;
16809 else if (strcmp (name
, "pop") == 0)
16811 struct mips_option_stack
*s
;
16813 s
= mips_opts_stack
;
16815 as_bad (_(".set pop with no .set push"));
16818 /* If we're changing the reorder mode we need to handle
16819 delay slots correctly. */
16820 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
16821 start_noreorder ();
16822 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
16825 mips_opts
= s
->options
;
16826 mips_opts_stack
= s
->next
;
16832 type
= parse_code_option (name
);
16833 if (type
== OPTION_TYPE_BAD
)
16834 as_warn (_("tried to set unrecognized symbol: %s\n"), name
);
16837 /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp
16838 registers based on what is supported by the arch/cpu. */
16839 if (type
== OPTION_TYPE_ISA
)
16841 switch (mips_opts
.isa
)
16846 /* MIPS I cannot support FPXX. */
16848 /* fall-through. */
16855 if (mips_opts
.fp
!= 0)
16871 if (mips_opts
.fp
!= 0)
16873 if (mips_opts
.arch
== CPU_R5900
)
16880 as_bad (_("unknown ISA level %s"), name
+ 4);
16885 mips_check_options (&mips_opts
, FALSE
);
16887 mips_check_isa_supports_ases ();
16888 *input_line_pointer
= ch
;
16889 demand_empty_rest_of_line ();
16892 /* Handle the .module pseudo-op. */
16895 s_module (int ignore ATTRIBUTE_UNUSED
)
16897 char *name
= input_line_pointer
, ch
;
16899 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
16900 ++input_line_pointer
;
16901 ch
= *input_line_pointer
;
16902 *input_line_pointer
= '\0';
16904 if (!file_mips_opts_checked
)
16906 if (parse_code_option (name
) == OPTION_TYPE_BAD
)
16907 as_bad (_(".module used with unrecognized symbol: %s\n"), name
);
16909 /* Update module level settings from mips_opts. */
16910 file_mips_opts
= mips_opts
;
16913 as_bad (_(".module is not permitted after generating code"));
16915 *input_line_pointer
= ch
;
16916 demand_empty_rest_of_line ();
16919 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
16920 .option pic2. It means to generate SVR4 PIC calls. */
16923 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
16925 mips_pic
= SVR4_PIC
;
16926 mips_abicalls
= TRUE
;
16928 if (g_switch_seen
&& g_switch_value
!= 0)
16929 as_warn (_("-G may not be used with SVR4 PIC code"));
16930 g_switch_value
= 0;
16932 bfd_set_gp_size (stdoutput
, 0);
16933 demand_empty_rest_of_line ();
16936 /* Handle the .cpload pseudo-op. This is used when generating SVR4
16937 PIC code. It sets the $gp register for the function based on the
16938 function address, which is in the register named in the argument.
16939 This uses a relocation against _gp_disp, which is handled specially
16940 by the linker. The result is:
16941 lui $gp,%hi(_gp_disp)
16942 addiu $gp,$gp,%lo(_gp_disp)
16943 addu $gp,$gp,.cpload argument
16944 The .cpload argument is normally $25 == $t9.
16946 The -mno-shared option changes this to:
16947 lui $gp,%hi(__gnu_local_gp)
16948 addiu $gp,$gp,%lo(__gnu_local_gp)
16949 and the argument is ignored. This saves an instruction, but the
16950 resulting code is not position independent; it uses an absolute
16951 address for __gnu_local_gp. Thus code assembled with -mno-shared
16952 can go into an ordinary executable, but not into a shared library. */
16955 s_cpload (int ignore ATTRIBUTE_UNUSED
)
16961 file_mips_check_options ();
16963 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
16964 .cpload is ignored. */
16965 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
16971 if (mips_opts
.mips16
)
16973 as_bad (_("%s not supported in MIPS16 mode"), ".cpload");
16974 ignore_rest_of_line ();
16978 /* .cpload should be in a .set noreorder section. */
16979 if (mips_opts
.noreorder
== 0)
16980 as_warn (_(".cpload not in noreorder section"));
16982 reg
= tc_get_register (0);
16984 /* If we need to produce a 64-bit address, we are better off using
16985 the default instruction sequence. */
16986 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
16988 ex
.X_op
= O_symbol
;
16989 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
16991 ex
.X_op_symbol
= NULL
;
16992 ex
.X_add_number
= 0;
16994 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
16995 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
16997 mips_mark_labels ();
16998 mips_assembling_insn
= TRUE
;
17001 macro_build_lui (&ex
, mips_gp_register
);
17002 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17003 mips_gp_register
, BFD_RELOC_LO16
);
17005 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
17006 mips_gp_register
, reg
);
17009 mips_assembling_insn
= FALSE
;
17010 demand_empty_rest_of_line ();
17013 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
17014 .cpsetup $reg1, offset|$reg2, label
17016 If offset is given, this results in:
17017 sd $gp, offset($sp)
17018 lui $gp, %hi(%neg(%gp_rel(label)))
17019 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17020 daddu $gp, $gp, $reg1
17022 If $reg2 is given, this results in:
17024 lui $gp, %hi(%neg(%gp_rel(label)))
17025 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
17026 daddu $gp, $gp, $reg1
17027 $reg1 is normally $25 == $t9.
17029 The -mno-shared option replaces the last three instructions with
17031 addiu $gp,$gp,%lo(_gp) */
17034 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
17036 expressionS ex_off
;
17037 expressionS ex_sym
;
17040 file_mips_check_options ();
17042 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
17043 We also need NewABI support. */
17044 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17050 if (mips_opts
.mips16
)
17052 as_bad (_("%s not supported in MIPS16 mode"), ".cpsetup");
17053 ignore_rest_of_line ();
17057 reg1
= tc_get_register (0);
17058 SKIP_WHITESPACE ();
17059 if (*input_line_pointer
!= ',')
17061 as_bad (_("missing argument separator ',' for .cpsetup"));
17065 ++input_line_pointer
;
17066 SKIP_WHITESPACE ();
17067 if (*input_line_pointer
== '$')
17069 mips_cpreturn_register
= tc_get_register (0);
17070 mips_cpreturn_offset
= -1;
17074 mips_cpreturn_offset
= get_absolute_expression ();
17075 mips_cpreturn_register
= -1;
17077 SKIP_WHITESPACE ();
17078 if (*input_line_pointer
!= ',')
17080 as_bad (_("missing argument separator ',' for .cpsetup"));
17084 ++input_line_pointer
;
17085 SKIP_WHITESPACE ();
17086 expression (&ex_sym
);
17088 mips_mark_labels ();
17089 mips_assembling_insn
= TRUE
;
17092 if (mips_cpreturn_register
== -1)
17094 ex_off
.X_op
= O_constant
;
17095 ex_off
.X_add_symbol
= NULL
;
17096 ex_off
.X_op_symbol
= NULL
;
17097 ex_off
.X_add_number
= mips_cpreturn_offset
;
17099 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
17100 BFD_RELOC_LO16
, SP
);
17103 move_register (mips_cpreturn_register
, mips_gp_register
);
17105 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
17107 macro_build (&ex_sym
, "lui", LUI_FMT
, mips_gp_register
,
17108 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
17111 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
17112 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
17113 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
17115 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
17116 mips_gp_register
, reg1
);
17122 ex
.X_op
= O_symbol
;
17123 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
17124 ex
.X_op_symbol
= NULL
;
17125 ex
.X_add_number
= 0;
17127 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
17128 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
17130 macro_build_lui (&ex
, mips_gp_register
);
17131 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
17132 mips_gp_register
, BFD_RELOC_LO16
);
17137 mips_assembling_insn
= FALSE
;
17138 demand_empty_rest_of_line ();
17142 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
17144 file_mips_check_options ();
17146 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
17147 .cplocal is ignored. */
17148 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17154 if (mips_opts
.mips16
)
17156 as_bad (_("%s not supported in MIPS16 mode"), ".cplocal");
17157 ignore_rest_of_line ();
17161 mips_gp_register
= tc_get_register (0);
17162 demand_empty_rest_of_line ();
17165 /* Handle the .cprestore pseudo-op. This stores $gp into a given
17166 offset from $sp. The offset is remembered, and after making a PIC
17167 call $gp is restored from that location. */
17170 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
17174 file_mips_check_options ();
17176 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
17177 .cprestore is ignored. */
17178 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
17184 if (mips_opts
.mips16
)
17186 as_bad (_("%s not supported in MIPS16 mode"), ".cprestore");
17187 ignore_rest_of_line ();
17191 mips_cprestore_offset
= get_absolute_expression ();
17192 mips_cprestore_valid
= 1;
17194 ex
.X_op
= O_constant
;
17195 ex
.X_add_symbol
= NULL
;
17196 ex
.X_op_symbol
= NULL
;
17197 ex
.X_add_number
= mips_cprestore_offset
;
17199 mips_mark_labels ();
17200 mips_assembling_insn
= TRUE
;
17203 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
17204 SP
, HAVE_64BIT_ADDRESSES
);
17207 mips_assembling_insn
= FALSE
;
17208 demand_empty_rest_of_line ();
17211 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
17212 was given in the preceding .cpsetup, it results in:
17213 ld $gp, offset($sp)
17215 If a register $reg2 was given there, it results in:
17216 or $gp, $reg2, $0 */
17219 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
17223 file_mips_check_options ();
17225 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
17226 We also need NewABI support. */
17227 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17233 if (mips_opts
.mips16
)
17235 as_bad (_("%s not supported in MIPS16 mode"), ".cpreturn");
17236 ignore_rest_of_line ();
17240 mips_mark_labels ();
17241 mips_assembling_insn
= TRUE
;
17244 if (mips_cpreturn_register
== -1)
17246 ex
.X_op
= O_constant
;
17247 ex
.X_add_symbol
= NULL
;
17248 ex
.X_op_symbol
= NULL
;
17249 ex
.X_add_number
= mips_cpreturn_offset
;
17251 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
17254 move_register (mips_gp_register
, mips_cpreturn_register
);
17258 mips_assembling_insn
= FALSE
;
17259 demand_empty_rest_of_line ();
17262 /* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword
17263 pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size
17264 DTP- or TP-relative relocation of type RTYPE, for use in either DWARF
17265 debug information or MIPS16 TLS. */
17268 s_tls_rel_directive (const size_t bytes
, const char *dirstr
,
17269 bfd_reloc_code_real_type rtype
)
17276 if (ex
.X_op
!= O_symbol
)
17278 as_bad (_("unsupported use of %s"), dirstr
);
17279 ignore_rest_of_line ();
17282 p
= frag_more (bytes
);
17283 md_number_to_chars (p
, 0, bytes
);
17284 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, bytes
, &ex
, FALSE
, rtype
);
17285 demand_empty_rest_of_line ();
17286 mips_clear_insn_labels ();
17289 /* Handle .dtprelword. */
17292 s_dtprelword (int ignore ATTRIBUTE_UNUSED
)
17294 s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_MIPS_TLS_DTPREL32
);
17297 /* Handle .dtpreldword. */
17300 s_dtpreldword (int ignore ATTRIBUTE_UNUSED
)
17302 s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_MIPS_TLS_DTPREL64
);
17305 /* Handle .tprelword. */
17308 s_tprelword (int ignore ATTRIBUTE_UNUSED
)
17310 s_tls_rel_directive (4, ".tprelword", BFD_RELOC_MIPS_TLS_TPREL32
);
17313 /* Handle .tpreldword. */
17316 s_tpreldword (int ignore ATTRIBUTE_UNUSED
)
17318 s_tls_rel_directive (8, ".tpreldword", BFD_RELOC_MIPS_TLS_TPREL64
);
17321 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
17322 code. It sets the offset to use in gp_rel relocations. */
17325 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
17327 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
17328 We also need NewABI support. */
17329 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
17335 mips_gprel_offset
= get_absolute_expression ();
17337 demand_empty_rest_of_line ();
17340 /* Handle the .gpword pseudo-op. This is used when generating PIC
17341 code. It generates a 32 bit GP relative reloc. */
17344 s_gpword (int ignore ATTRIBUTE_UNUSED
)
17346 segment_info_type
*si
;
17347 struct insn_label_list
*l
;
17351 /* When not generating PIC code, this is treated as .word. */
17352 if (mips_pic
!= SVR4_PIC
)
17358 si
= seg_info (now_seg
);
17359 l
= si
->label_list
;
17360 mips_emit_delays ();
17362 mips_align (2, 0, l
);
17365 mips_clear_insn_labels ();
17367 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17369 as_bad (_("unsupported use of .gpword"));
17370 ignore_rest_of_line ();
17374 md_number_to_chars (p
, 0, 4);
17375 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17376 BFD_RELOC_GPREL32
);
17378 demand_empty_rest_of_line ();
17382 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
17384 segment_info_type
*si
;
17385 struct insn_label_list
*l
;
17389 /* When not generating PIC code, this is treated as .dword. */
17390 if (mips_pic
!= SVR4_PIC
)
17396 si
= seg_info (now_seg
);
17397 l
= si
->label_list
;
17398 mips_emit_delays ();
17400 mips_align (3, 0, l
);
17403 mips_clear_insn_labels ();
17405 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17407 as_bad (_("unsupported use of .gpdword"));
17408 ignore_rest_of_line ();
17412 md_number_to_chars (p
, 0, 8);
17413 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17414 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
17416 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
17417 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
17418 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
17420 demand_empty_rest_of_line ();
17423 /* Handle the .ehword pseudo-op. This is used when generating unwinding
17424 tables. It generates a R_MIPS_EH reloc. */
17427 s_ehword (int ignore ATTRIBUTE_UNUSED
)
17432 mips_emit_delays ();
17435 mips_clear_insn_labels ();
17437 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
17439 as_bad (_("unsupported use of .ehword"));
17440 ignore_rest_of_line ();
17444 md_number_to_chars (p
, 0, 4);
17445 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
17446 BFD_RELOC_32_PCREL
);
17448 demand_empty_rest_of_line ();
17451 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
17452 tables in SVR4 PIC code. */
17455 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
17459 file_mips_check_options ();
17461 /* This is ignored when not generating SVR4 PIC code. */
17462 if (mips_pic
!= SVR4_PIC
)
17468 mips_mark_labels ();
17469 mips_assembling_insn
= TRUE
;
17471 /* Add $gp to the register named as an argument. */
17473 reg
= tc_get_register (0);
17474 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
17477 mips_assembling_insn
= FALSE
;
17478 demand_empty_rest_of_line ();
17481 /* Handle the .insn pseudo-op. This marks instruction labels in
17482 mips16/micromips mode. This permits the linker to handle them specially,
17483 such as generating jalx instructions when needed. We also make
17484 them odd for the duration of the assembly, in order to generate the
17485 right sort of code. We will make them even in the adjust_symtab
17486 routine, while leaving them marked. This is convenient for the
17487 debugger and the disassembler. The linker knows to make them odd
17491 s_insn (int ignore ATTRIBUTE_UNUSED
)
17493 file_mips_check_options ();
17494 file_ase_mips16
|= mips_opts
.mips16
;
17495 file_ase_micromips
|= mips_opts
.micromips
;
17497 mips_mark_labels ();
17499 demand_empty_rest_of_line ();
17502 /* Handle the .nan pseudo-op. */
17505 s_nan (int ignore ATTRIBUTE_UNUSED
)
17507 static const char str_legacy
[] = "legacy";
17508 static const char str_2008
[] = "2008";
17511 for (i
= 0; !is_end_of_line
[(unsigned char) input_line_pointer
[i
]]; i
++);
17513 if (i
== sizeof (str_2008
) - 1
17514 && memcmp (input_line_pointer
, str_2008
, i
) == 0)
17516 else if (i
== sizeof (str_legacy
) - 1
17517 && memcmp (input_line_pointer
, str_legacy
, i
) == 0)
17519 if (ISA_HAS_LEGACY_NAN (file_mips_opts
.isa
))
17522 as_bad (_("`%s' does not support legacy NaN"),
17523 mips_cpu_info_from_isa (file_mips_opts
.isa
)->name
);
17526 as_bad (_("bad .nan directive"));
17528 input_line_pointer
+= i
;
17529 demand_empty_rest_of_line ();
17532 /* Handle a .stab[snd] directive. Ideally these directives would be
17533 implemented in a transparent way, so that removing them would not
17534 have any effect on the generated instructions. However, s_stab
17535 internally changes the section, so in practice we need to decide
17536 now whether the preceding label marks compressed code. We do not
17537 support changing the compression mode of a label after a .stab*
17538 directive, such as in:
17544 so the current mode wins. */
17547 s_mips_stab (int type
)
17549 file_mips_check_options ();
17550 mips_mark_labels ();
17554 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
17557 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
17564 c
= get_symbol_name (&name
);
17565 symbolP
= symbol_find_or_make (name
);
17566 S_SET_WEAK (symbolP
);
17567 *input_line_pointer
= c
;
17569 SKIP_WHITESPACE_AFTER_NAME ();
17571 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
17573 if (S_IS_DEFINED (symbolP
))
17575 as_bad (_("ignoring attempt to redefine symbol %s"),
17576 S_GET_NAME (symbolP
));
17577 ignore_rest_of_line ();
17581 if (*input_line_pointer
== ',')
17583 ++input_line_pointer
;
17584 SKIP_WHITESPACE ();
17588 if (exp
.X_op
!= O_symbol
)
17590 as_bad (_("bad .weakext directive"));
17591 ignore_rest_of_line ();
17594 symbol_set_value_expression (symbolP
, &exp
);
17597 demand_empty_rest_of_line ();
17600 /* Parse a register string into a number. Called from the ECOFF code
17601 to parse .frame. The argument is non-zero if this is the frame
17602 register, so that we can record it in mips_frame_reg. */
17605 tc_get_register (int frame
)
17609 SKIP_WHITESPACE ();
17610 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
17614 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
17615 mips_frame_reg_valid
= 1;
17616 mips_cprestore_valid
= 0;
17622 md_section_align (asection
*seg
, valueT addr
)
17624 int align
= bfd_section_alignment (seg
);
17626 /* We don't need to align ELF sections to the full alignment.
17627 However, Irix 5 may prefer that we align them at least to a 16
17628 byte boundary. We don't bother to align the sections if we
17629 are targeted for an embedded system. */
17630 if (strncmp (TARGET_OS
, "elf", 3) == 0)
17635 return ((addr
+ (1 << align
) - 1) & -(1 << align
));
17638 /* Utility routine, called from above as well. If called while the
17639 input file is still being read, it's only an approximation. (For
17640 example, a symbol may later become defined which appeared to be
17641 undefined earlier.) */
17644 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
17649 if (g_switch_value
> 0)
17651 const char *symname
;
17654 /* Find out whether this symbol can be referenced off the $gp
17655 register. It can be if it is smaller than the -G size or if
17656 it is in the .sdata or .sbss section. Certain symbols can
17657 not be referenced off the $gp, although it appears as though
17659 symname
= S_GET_NAME (sym
);
17660 if (symname
!= (const char *) NULL
17661 && (strcmp (symname
, "eprol") == 0
17662 || strcmp (symname
, "etext") == 0
17663 || strcmp (symname
, "_gp") == 0
17664 || strcmp (symname
, "edata") == 0
17665 || strcmp (symname
, "_fbss") == 0
17666 || strcmp (symname
, "_fdata") == 0
17667 || strcmp (symname
, "_ftext") == 0
17668 || strcmp (symname
, "end") == 0
17669 || strcmp (symname
, "_gp_disp") == 0))
17671 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
17673 #ifndef NO_ECOFF_DEBUGGING
17674 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
17675 && (symbol_get_obj (sym
)->ecoff_extern_size
17676 <= g_switch_value
))
17678 /* We must defer this decision until after the whole
17679 file has been read, since there might be a .extern
17680 after the first use of this symbol. */
17681 || (before_relaxing
17682 #ifndef NO_ECOFF_DEBUGGING
17683 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
17685 && S_GET_VALUE (sym
) == 0)
17686 || (S_GET_VALUE (sym
) != 0
17687 && S_GET_VALUE (sym
) <= g_switch_value
)))
17691 const char *segname
;
17693 segname
= segment_name (S_GET_SEGMENT (sym
));
17694 gas_assert (strcmp (segname
, ".lit8") != 0
17695 && strcmp (segname
, ".lit4") != 0);
17696 change
= (strcmp (segname
, ".sdata") != 0
17697 && strcmp (segname
, ".sbss") != 0
17698 && strncmp (segname
, ".sdata.", 7) != 0
17699 && strncmp (segname
, ".sbss.", 6) != 0
17700 && strncmp (segname
, ".gnu.linkonce.sb.", 17) != 0
17701 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
17706 /* We are not optimizing for the $gp register. */
17711 /* Return true if the given symbol should be considered local for SVR4 PIC. */
17714 pic_need_relax (symbolS
*sym
)
17718 /* Handle the case of a symbol equated to another symbol. */
17719 while (symbol_equated_reloc_p (sym
))
17723 /* It's possible to get a loop here in a badly written program. */
17724 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
17730 if (symbol_section_p (sym
))
17733 symsec
= S_GET_SEGMENT (sym
);
17735 /* This must duplicate the test in adjust_reloc_syms. */
17736 return (!bfd_is_und_section (symsec
)
17737 && !bfd_is_abs_section (symsec
)
17738 && !bfd_is_com_section (symsec
)
17739 /* A global or weak symbol is treated as external. */
17740 && (!S_IS_WEAK (sym
) && !S_IS_EXTERNAL (sym
)));
17743 /* Given a MIPS16 variant frag FRAGP and PC-relative operand PCREL_OP
17744 convert a section-relative value VAL to the equivalent PC-relative
17748 mips16_pcrel_val (fragS
*fragp
, const struct mips_pcrel_operand
*pcrel_op
,
17749 offsetT val
, long stretch
)
17754 gas_assert (pcrel_op
->root
.root
.type
== OP_PCREL
);
17756 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
17758 /* If the relax_marker of the symbol fragment differs from the
17759 relax_marker of this fragment, we have not yet adjusted the
17760 symbol fragment fr_address. We want to add in STRETCH in
17761 order to get a better estimate of the address. This
17762 particularly matters because of the shift bits. */
17763 if (stretch
!= 0 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17767 /* Adjust stretch for any alignment frag. Note that if have
17768 been expanding the earlier code, the symbol may be
17769 defined in what appears to be an earlier frag. FIXME:
17770 This doesn't handle the fr_subtype field, which specifies
17771 a maximum number of bytes to skip when doing an
17773 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17775 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17778 stretch
= -(-stretch
& ~((1 << (int) f
->fr_offset
) - 1));
17780 stretch
&= ~((1 << (int) f
->fr_offset
) - 1);
17789 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17791 /* The base address rules are complicated. The base address of
17792 a branch is the following instruction. The base address of a
17793 PC relative load or add is the instruction itself, but if it
17794 is in a delay slot (in which case it can not be extended) use
17795 the address of the instruction whose delay slot it is in. */
17796 if (pcrel_op
->include_isa_bit
)
17800 /* If we are currently assuming that this frag should be
17801 extended, then the current address is two bytes higher. */
17802 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17805 /* Ignore the low bit in the target, since it will be set
17806 for a text label. */
17809 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
17811 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
17814 val
-= addr
& -(1 << pcrel_op
->align_log2
);
17819 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
17820 extended opcode. SEC is the section the frag is in. */
17823 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17825 const struct mips_int_operand
*operand
;
17830 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
17832 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17835 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17836 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17837 operand
= mips16_immed_operand (type
, FALSE
);
17838 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
17839 || (operand
->root
.type
== OP_PCREL
17841 : !bfd_is_abs_section (symsec
)))
17844 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17846 if (operand
->root
.type
== OP_PCREL
)
17848 const struct mips_pcrel_operand
*pcrel_op
;
17851 if (RELAX_MIPS16_ALWAYS_EXTENDED (fragp
->fr_subtype
))
17854 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17855 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17857 /* If any of the shifted bits are set, we must use an extended
17858 opcode. If the address depends on the size of this
17859 instruction, this can lead to a loop, so we arrange to always
17860 use an extended opcode. */
17861 if ((val
& ((1 << operand
->shift
) - 1)) != 0)
17863 fragp
->fr_subtype
=
17864 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17868 /* If we are about to mark a frag as extended because the value
17869 is precisely the next value above maxtiny, then there is a
17870 chance of an infinite loop as in the following code:
17875 In this case when the la is extended, foo is 0x3fc bytes
17876 away, so the la can be shrunk, but then foo is 0x400 away, so
17877 the la must be extended. To avoid this loop, we mark the
17878 frag as extended if it was small, and is about to become
17879 extended with the next value above maxtiny. */
17880 maxtiny
= mips_int_operand_max (operand
);
17881 if (val
== maxtiny
+ (1 << operand
->shift
)
17882 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
17884 fragp
->fr_subtype
=
17885 RELAX_MIPS16_MARK_ALWAYS_EXTENDED (fragp
->fr_subtype
);
17890 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17893 /* Given a MIPS16 variant frag FRAGP, return non-zero if it needs
17894 macro expansion. SEC is the section the frag is in. We only
17895 support PC-relative instructions (LA, DLA, LW, LD) here, in
17896 non-PIC code using 32-bit addressing. */
17899 mips16_macro_frag (fragS
*fragp
, asection
*sec
, long stretch
)
17901 const struct mips_pcrel_operand
*pcrel_op
;
17902 const struct mips_int_operand
*operand
;
17907 gas_assert (!RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
));
17909 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
17911 if (!RELAX_MIPS16_SYM32 (fragp
->fr_subtype
))
17914 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
17920 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
17921 if (bfd_is_abs_section (symsec
))
17923 if (RELAX_MIPS16_PIC (fragp
->fr_subtype
))
17925 if (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
) || sec
!= symsec
)
17928 operand
= mips16_immed_operand (type
, TRUE
);
17929 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17930 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
17931 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, stretch
);
17933 return !mips16_immed_in_range_p (operand
, BFD_RELOC_UNUSED
, val
);
17940 /* Compute the length of a branch sequence, and adjust the
17941 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
17942 worst-case length is computed, with UPDATE being used to indicate
17943 whether an unconditional (-1), branch-likely (+1) or regular (0)
17944 branch is to be computed. */
17946 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
17948 bfd_boolean toofar
;
17952 && S_IS_DEFINED (fragp
->fr_symbol
)
17953 && !S_IS_WEAK (fragp
->fr_symbol
)
17954 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
17959 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
17961 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17965 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
17968 /* If the symbol is not defined or it's in a different segment,
17969 we emit the long sequence. */
17972 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
17974 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_AT (fragp
->fr_subtype
),
17975 RELAX_BRANCH_PIC (fragp
->fr_subtype
),
17976 RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
17977 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
17978 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
17984 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
17987 if (!fragp
|| RELAX_BRANCH_PIC (fragp
->fr_subtype
))
17989 /* Additional space for PIC loading of target address. */
17991 if (mips_opts
.isa
== ISA_MIPS1
)
17992 /* Additional space for $at-stabilizing nop. */
17996 /* If branch is conditional. */
17997 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
18004 /* Get a FRAG's branch instruction delay slot size, either from the
18005 short-delay-slot bit of a branch-and-link instruction if AL is TRUE,
18006 or SHORT_INSN_SIZE otherwise. */
18009 frag_branch_delay_slot_size (fragS
*fragp
, bfd_boolean al
, int short_insn_size
)
18011 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18014 return (read_compressed_insn (buf
, 4) & 0x02000000) ? 2 : 4;
18016 return short_insn_size
;
18019 /* Compute the length of a branch sequence, and adjust the
18020 RELAX_MICROMIPS_TOOFAR32 bit accordingly. If FRAGP is NULL, the
18021 worst-case length is computed, with UPDATE being used to indicate
18022 whether an unconditional (-1), or regular (0) branch is to be
18026 relaxed_micromips_32bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18028 bfd_boolean insn32
= TRUE
;
18029 bfd_boolean nods
= TRUE
;
18030 bfd_boolean pic
= TRUE
;
18031 bfd_boolean al
= TRUE
;
18032 int short_insn_size
;
18033 bfd_boolean toofar
;
18038 insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18039 nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18040 pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18041 al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18043 short_insn_size
= insn32
? 4 : 2;
18046 && S_IS_DEFINED (fragp
->fr_symbol
)
18047 && !S_IS_WEAK (fragp
->fr_symbol
)
18048 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18053 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18054 /* Ignore the low bit in the target, since it will be set
18055 for a text label. */
18056 if ((val
& 1) != 0)
18059 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18063 toofar
= val
< - (0x8000 << 1) || val
>= (0x8000 << 1);
18066 /* If the symbol is not defined or it's in a different segment,
18067 we emit the long sequence. */
18070 if (fragp
&& update
18071 && toofar
!= RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18072 fragp
->fr_subtype
= (toofar
18073 ? RELAX_MICROMIPS_MARK_TOOFAR32 (fragp
->fr_subtype
)
18074 : RELAX_MICROMIPS_CLEAR_TOOFAR32 (fragp
->fr_subtype
));
18079 bfd_boolean compact_known
= fragp
!= NULL
;
18080 bfd_boolean compact
= FALSE
;
18081 bfd_boolean uncond
;
18085 compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18086 uncond
= RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
);
18089 uncond
= update
< 0;
18091 /* If label is out of range, we turn branch <br>:
18093 <br> label # 4 bytes
18100 # compact && (!PIC || insn32)
18103 if ((!pic
|| insn32
) && (!compact_known
|| compact
))
18104 length
+= short_insn_size
;
18106 /* If assembling PIC code, we further turn:
18112 lw/ld at, %got(label)(gp) # 4 bytes
18113 d/addiu at, %lo(label) # 4 bytes
18114 jr/c at # 2/4 bytes
18117 length
+= 4 + short_insn_size
;
18119 /* Add an extra nop if the jump has no compact form and we need
18120 to fill the delay slot. */
18121 if ((!pic
|| al
) && nods
)
18123 ? frag_branch_delay_slot_size (fragp
, al
, short_insn_size
)
18124 : short_insn_size
);
18126 /* If branch <br> is conditional, we prepend negated branch <brneg>:
18128 <brneg> 0f # 4 bytes
18129 nop # 2/4 bytes if !compact
18132 length
+= (compact_known
&& compact
) ? 4 : 4 + short_insn_size
;
18136 /* Add an extra nop to fill the delay slot. */
18137 gas_assert (fragp
);
18138 length
+= frag_branch_delay_slot_size (fragp
, al
, short_insn_size
);
18144 /* Compute the length of a branch, and adjust the RELAX_MICROMIPS_TOOFAR16
18145 bit accordingly. */
18148 relaxed_micromips_16bit_branch_length (fragS
*fragp
, asection
*sec
, int update
)
18150 bfd_boolean toofar
;
18153 && S_IS_DEFINED (fragp
->fr_symbol
)
18154 && !S_IS_WEAK (fragp
->fr_symbol
)
18155 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
18161 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
18162 /* Ignore the low bit in the target, since it will be set
18163 for a text label. */
18164 if ((val
& 1) != 0)
18167 /* Assume this is a 2-byte branch. */
18168 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 2;
18170 /* We try to avoid the infinite loop by not adding 2 more bytes for
18175 type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18177 toofar
= val
< - (0x200 << 1) || val
>= (0x200 << 1);
18178 else if (type
== 'E')
18179 toofar
= val
< - (0x40 << 1) || val
>= (0x40 << 1);
18184 /* If the symbol is not defined or it's in a different segment,
18185 we emit a normal 32-bit branch. */
18188 if (fragp
&& update
18189 && toofar
!= RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18191 = toofar
? RELAX_MICROMIPS_MARK_TOOFAR16 (fragp
->fr_subtype
)
18192 : RELAX_MICROMIPS_CLEAR_TOOFAR16 (fragp
->fr_subtype
);
18200 /* Estimate the size of a frag before relaxing. Unless this is the
18201 mips16, we are not really relaxing here, and the final size is
18202 encoded in the subtype information. For the mips16, we have to
18203 decide whether we are using an extended opcode or not. */
18206 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
18210 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18213 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
18215 return fragp
->fr_var
;
18218 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
18220 /* We don't want to modify the EXTENDED bit here; it might get us
18221 into infinite loops. We change it only in mips_relax_frag(). */
18222 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18223 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 8 : 12;
18225 return RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2;
18228 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18232 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18233 length
= relaxed_micromips_16bit_branch_length (fragp
, segtype
, FALSE
);
18234 if (length
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18235 length
= relaxed_micromips_32bit_branch_length (fragp
, segtype
, FALSE
);
18236 fragp
->fr_var
= length
;
18241 if (mips_pic
== VXWORKS_PIC
)
18242 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
18244 else if (RELAX_PIC (fragp
->fr_subtype
))
18245 change
= pic_need_relax (fragp
->fr_symbol
);
18247 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
18251 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
18252 return -RELAX_FIRST (fragp
->fr_subtype
);
18255 return -RELAX_SECOND (fragp
->fr_subtype
);
18258 /* This is called to see whether a reloc against a defined symbol
18259 should be converted into a reloc against a section. */
18262 mips_fix_adjustable (fixS
*fixp
)
18264 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18265 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18268 if (fixp
->fx_addsy
== NULL
)
18271 /* Allow relocs used for EH tables. */
18272 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
18275 /* If symbol SYM is in a mergeable section, relocations of the form
18276 SYM + 0 can usually be made section-relative. The mergeable data
18277 is then identified by the section offset rather than by the symbol.
18279 However, if we're generating REL LO16 relocations, the offset is split
18280 between the LO16 and partnering high part relocation. The linker will
18281 need to recalculate the complete offset in order to correctly identify
18284 The linker has traditionally not looked for the partnering high part
18285 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
18286 placed anywhere. Rather than break backwards compatibility by changing
18287 this, it seems better not to force the issue, and instead keep the
18288 original symbol. This will work with either linker behavior. */
18289 if ((lo16_reloc_p (fixp
->fx_r_type
)
18290 || reloc_needs_lo_p (fixp
->fx_r_type
))
18291 && HAVE_IN_PLACE_ADDENDS
18292 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
18295 /* There is no place to store an in-place offset for JALR relocations. */
18296 if (jalr_reloc_p (fixp
->fx_r_type
) && HAVE_IN_PLACE_ADDENDS
)
18299 /* Likewise an in-range offset of limited PC-relative relocations may
18300 overflow the in-place relocatable field if recalculated against the
18301 start address of the symbol's containing section.
18303 Also, PC relative relocations for MIPS R6 need to be symbol rather than
18304 section relative to allow linker relaxations to be performed later on. */
18305 if (limited_pcrel_reloc_p (fixp
->fx_r_type
)
18306 && (HAVE_IN_PLACE_ADDENDS
|| ISA_IS_R6 (file_mips_opts
.isa
)))
18309 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
18310 to a floating-point stub. The same is true for non-R_MIPS16_26
18311 relocations against MIPS16 functions; in this case, the stub becomes
18312 the function's canonical address.
18314 Floating-point stubs are stored in unique .mips16.call.* or
18315 .mips16.fn.* sections. If a stub T for function F is in section S,
18316 the first relocation in section S must be against F; this is how the
18317 linker determines the target function. All relocations that might
18318 resolve to T must also be against F. We therefore have the following
18319 restrictions, which are given in an intentionally-redundant way:
18321 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
18324 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
18325 if that stub might be used.
18327 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
18330 4. We cannot reduce a stub's relocations against MIPS16 symbols if
18331 that stub might be used.
18333 There is a further restriction:
18335 5. We cannot reduce jump relocations (R_MIPS_26, R_MIPS16_26 or
18336 R_MICROMIPS_26_S1) or branch relocations (R_MIPS_PC26_S2,
18337 R_MIPS_PC21_S2, R_MIPS_PC16, R_MIPS16_PC16_S1,
18338 R_MICROMIPS_PC16_S1, R_MICROMIPS_PC10_S1 or R_MICROMIPS_PC7_S1)
18339 against MIPS16 or microMIPS symbols because we need to keep the
18340 MIPS16 or microMIPS symbol for the purpose of mode mismatch
18341 detection and JAL or BAL to JALX instruction conversion in the
18344 For simplicity, we deal with (3)-(4) by not reducing _any_ relocation
18345 against a MIPS16 symbol. We deal with (5) by additionally leaving
18346 alone any jump and branch relocations against a microMIPS symbol.
18348 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
18349 relocation against some symbol R, no relocation against R may be
18350 reduced. (Note that this deals with (2) as well as (1) because
18351 relocations against global symbols will never be reduced on ELF
18352 targets.) This approach is a little simpler than trying to detect
18353 stub sections, and gives the "all or nothing" per-symbol consistency
18354 that we have for MIPS16 symbols. */
18355 if (fixp
->fx_subsy
== NULL
18356 && (ELF_ST_IS_MIPS16 (S_GET_OTHER (fixp
->fx_addsy
))
18357 || (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixp
->fx_addsy
))
18358 && (jmp_reloc_p (fixp
->fx_r_type
)
18359 || b_reloc_p (fixp
->fx_r_type
)))
18360 || *symbol_get_tc (fixp
->fx_addsy
)))
18366 /* Translate internal representation of relocation info to BFD target
18370 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
18372 static arelent
*retval
[4];
18374 bfd_reloc_code_real_type code
;
18376 memset (retval
, 0, sizeof(retval
));
18377 reloc
= retval
[0] = XCNEW (arelent
);
18378 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
18379 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18380 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18382 if (fixp
->fx_pcrel
)
18384 gas_assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
18385 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_16_PCREL_S1
18386 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_7_PCREL_S1
18387 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_10_PCREL_S1
18388 || fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_16_PCREL_S1
18389 || fixp
->fx_r_type
== BFD_RELOC_32_PCREL
18390 || fixp
->fx_r_type
== BFD_RELOC_MIPS_21_PCREL_S2
18391 || fixp
->fx_r_type
== BFD_RELOC_MIPS_26_PCREL_S2
18392 || fixp
->fx_r_type
== BFD_RELOC_MIPS_18_PCREL_S3
18393 || fixp
->fx_r_type
== BFD_RELOC_MIPS_19_PCREL_S2
18394 || fixp
->fx_r_type
== BFD_RELOC_HI16_S_PCREL
18395 || fixp
->fx_r_type
== BFD_RELOC_LO16_PCREL
);
18397 /* At this point, fx_addnumber is "symbol offset - pcrel address".
18398 Relocations want only the symbol offset. */
18399 switch (fixp
->fx_r_type
)
18401 case BFD_RELOC_MIPS_18_PCREL_S3
:
18402 reloc
->addend
= fixp
->fx_addnumber
+ (reloc
->address
& ~7);
18405 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
18409 else if (HAVE_IN_PLACE_ADDENDS
18410 && fixp
->fx_r_type
== BFD_RELOC_MICROMIPS_JMP
18411 && (read_compressed_insn (fixp
->fx_frag
->fr_literal
18412 + fixp
->fx_where
, 4) >> 26) == 0x3c)
18414 /* Shift is 2, unusually, for microMIPS JALX. Adjust the in-place
18415 addend accordingly. */
18416 reloc
->addend
= fixp
->fx_addnumber
>> 1;
18419 reloc
->addend
= fixp
->fx_addnumber
;
18421 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
18422 entry to be used in the relocation's section offset. */
18423 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18425 reloc
->address
= reloc
->addend
;
18429 code
= fixp
->fx_r_type
;
18431 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18432 if (reloc
->howto
== NULL
)
18434 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18435 _("cannot represent %s relocation in this object file"
18437 bfd_get_reloc_code_name (code
));
18444 /* Relax a machine dependent frag. This returns the amount by which
18445 the current size of the frag should change. */
18448 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18450 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18452 offsetT old_var
= fragp
->fr_var
;
18454 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
18456 return fragp
->fr_var
- old_var
;
18459 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18461 offsetT old_var
= fragp
->fr_var
;
18462 offsetT new_var
= 4;
18464 if (RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
) != 0)
18465 new_var
= relaxed_micromips_16bit_branch_length (fragp
, sec
, TRUE
);
18466 if (new_var
== 4 && RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
))
18467 new_var
= relaxed_micromips_32bit_branch_length (fragp
, sec
, TRUE
);
18468 fragp
->fr_var
= new_var
;
18470 return new_var
- old_var
;
18473 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
18476 if (!mips16_extended_frag (fragp
, sec
, stretch
))
18478 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18480 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18481 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -6 : -10;
18483 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18485 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18491 else if (!mips16_macro_frag (fragp
, sec
, stretch
))
18493 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18495 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_MACRO (fragp
->fr_subtype
);
18496 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18497 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? -4 : -8;
18499 else if (!RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18501 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
18509 if (RELAX_MIPS16_MACRO (fragp
->fr_subtype
))
18511 else if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
18513 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
18514 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18515 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 4 : 8;
18519 fragp
->fr_subtype
= RELAX_MIPS16_MARK_MACRO (fragp
->fr_subtype
);
18520 return RELAX_MIPS16_E2 (fragp
->fr_subtype
) ? 6 : 10;
18527 /* Convert a machine dependent frag. */
18530 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
18532 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
18535 unsigned long insn
;
18538 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18539 insn
= read_insn (buf
);
18541 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
18543 /* We generate a fixup instead of applying it right now
18544 because, if there are linker relaxations, we're going to
18545 need the relocations. */
18546 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18547 fragp
->fr_symbol
, fragp
->fr_offset
,
18548 TRUE
, BFD_RELOC_16_PCREL_S2
);
18549 fixp
->fx_file
= fragp
->fr_file
;
18550 fixp
->fx_line
= fragp
->fr_line
;
18552 buf
= write_insn (buf
, insn
);
18558 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18559 _("relaxed out-of-range branch into a jump"));
18561 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
18564 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18566 /* Reverse the branch. */
18567 switch ((insn
>> 28) & 0xf)
18570 if ((insn
& 0xff000000) == 0x47000000
18571 || (insn
& 0xff600000) == 0x45600000)
18573 /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition
18574 reversed by tweaking bit 23. */
18575 insn
^= 0x00800000;
18579 /* bc[0-3][tf]l? instructions can have the condition
18580 reversed by tweaking a single TF bit, and their
18581 opcodes all have 0x4???????. */
18582 gas_assert ((insn
& 0xf3e00000) == 0x41000000);
18583 insn
^= 0x00010000;
18588 /* bltz 0x04000000 bgez 0x04010000
18589 bltzal 0x04100000 bgezal 0x04110000 */
18590 gas_assert ((insn
& 0xfc0e0000) == 0x04000000);
18591 insn
^= 0x00010000;
18595 /* beq 0x10000000 bne 0x14000000
18596 blez 0x18000000 bgtz 0x1c000000 */
18597 insn
^= 0x04000000;
18605 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18607 /* Clear the and-link bit. */
18608 gas_assert ((insn
& 0xfc1c0000) == 0x04100000);
18610 /* bltzal 0x04100000 bgezal 0x04110000
18611 bltzall 0x04120000 bgezall 0x04130000 */
18612 insn
&= ~0x00100000;
18615 /* Branch over the branch (if the branch was likely) or the
18616 full jump (not likely case). Compute the offset from the
18617 current instruction to branch to. */
18618 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18622 /* How many bytes in instructions we've already emitted? */
18623 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18624 /* How many bytes in instructions from here to the end? */
18625 i
= fragp
->fr_var
- i
;
18627 /* Convert to instruction count. */
18629 /* Branch counts from the next instruction. */
18632 /* Branch over the jump. */
18633 buf
= write_insn (buf
, insn
);
18636 buf
= write_insn (buf
, 0);
18638 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
18640 /* beql $0, $0, 2f */
18642 /* Compute the PC offset from the current instruction to
18643 the end of the variable frag. */
18644 /* How many bytes in instructions we've already emitted? */
18645 i
= buf
- fragp
->fr_literal
- fragp
->fr_fix
;
18646 /* How many bytes in instructions from here to the end? */
18647 i
= fragp
->fr_var
- i
;
18648 /* Convert to instruction count. */
18650 /* Don't decrement i, because we want to branch over the
18654 buf
= write_insn (buf
, insn
);
18655 buf
= write_insn (buf
, 0);
18659 if (!RELAX_BRANCH_PIC (fragp
->fr_subtype
))
18662 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
18663 ? 0x0c000000 : 0x08000000);
18665 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18666 fragp
->fr_symbol
, fragp
->fr_offset
,
18667 FALSE
, BFD_RELOC_MIPS_JMP
);
18668 fixp
->fx_file
= fragp
->fr_file
;
18669 fixp
->fx_line
= fragp
->fr_line
;
18671 buf
= write_insn (buf
, insn
);
18675 unsigned long at
= RELAX_BRANCH_AT (fragp
->fr_subtype
);
18677 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
18678 insn
= HAVE_64BIT_ADDRESSES
? 0xdf800000 : 0x8f800000;
18679 insn
|= at
<< OP_SH_RT
;
18681 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18682 fragp
->fr_symbol
, fragp
->fr_offset
,
18683 FALSE
, BFD_RELOC_MIPS_GOT16
);
18684 fixp
->fx_file
= fragp
->fr_file
;
18685 fixp
->fx_line
= fragp
->fr_line
;
18687 buf
= write_insn (buf
, insn
);
18689 if (mips_opts
.isa
== ISA_MIPS1
)
18691 buf
= write_insn (buf
, 0);
18693 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
18694 insn
= HAVE_64BIT_ADDRESSES
? 0x64000000 : 0x24000000;
18695 insn
|= at
<< OP_SH_RS
| at
<< OP_SH_RT
;
18697 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18698 fragp
->fr_symbol
, fragp
->fr_offset
,
18699 FALSE
, BFD_RELOC_LO16
);
18700 fixp
->fx_file
= fragp
->fr_file
;
18701 fixp
->fx_line
= fragp
->fr_line
;
18703 buf
= write_insn (buf
, insn
);
18706 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
18710 insn
|= at
<< OP_SH_RS
;
18712 buf
= write_insn (buf
, insn
);
18716 fragp
->fr_fix
+= fragp
->fr_var
;
18717 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18721 /* Relax microMIPS branches. */
18722 if (RELAX_MICROMIPS_P (fragp
->fr_subtype
))
18724 char *buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18725 bfd_boolean compact
= RELAX_MICROMIPS_COMPACT (fragp
->fr_subtype
);
18726 bfd_boolean insn32
= RELAX_MICROMIPS_INSN32 (fragp
->fr_subtype
);
18727 bfd_boolean nods
= RELAX_MICROMIPS_NODS (fragp
->fr_subtype
);
18728 bfd_boolean pic
= RELAX_MICROMIPS_PIC (fragp
->fr_subtype
);
18729 bfd_boolean al
= RELAX_MICROMIPS_LINK (fragp
->fr_subtype
);
18730 int type
= RELAX_MICROMIPS_TYPE (fragp
->fr_subtype
);
18731 bfd_boolean short_ds
;
18732 unsigned long insn
;
18735 fragp
->fr_fix
+= fragp
->fr_var
;
18737 /* Handle 16-bit branches that fit or are forced to fit. */
18738 if (type
!= 0 && !RELAX_MICROMIPS_TOOFAR16 (fragp
->fr_subtype
))
18740 /* We generate a fixup instead of applying it right now,
18741 because if there is linker relaxation, we're going to
18742 need the relocations. */
18746 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18747 fragp
->fr_symbol
, fragp
->fr_offset
,
18748 TRUE
, BFD_RELOC_MICROMIPS_10_PCREL_S1
);
18751 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 2,
18752 fragp
->fr_symbol
, fragp
->fr_offset
,
18753 TRUE
, BFD_RELOC_MICROMIPS_7_PCREL_S1
);
18759 fixp
->fx_file
= fragp
->fr_file
;
18760 fixp
->fx_line
= fragp
->fr_line
;
18762 /* These relocations can have an addend that won't fit in
18764 fixp
->fx_no_overflow
= 1;
18769 /* Handle 32-bit branches that fit or are forced to fit. */
18770 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18771 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18773 /* We generate a fixup instead of applying it right now,
18774 because if there is linker relaxation, we're going to
18775 need the relocations. */
18776 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18777 fragp
->fr_symbol
, fragp
->fr_offset
,
18778 TRUE
, BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18779 fixp
->fx_file
= fragp
->fr_file
;
18780 fixp
->fx_line
= fragp
->fr_line
;
18784 insn
= read_compressed_insn (buf
, 4);
18789 /* Check the short-delay-slot bit. */
18790 if (!al
|| (insn
& 0x02000000) != 0)
18791 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18793 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18796 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18801 /* Relax 16-bit branches to 32-bit branches. */
18804 insn
= read_compressed_insn (buf
, 2);
18806 if ((insn
& 0xfc00) == 0xcc00) /* b16 */
18807 insn
= 0x94000000; /* beq */
18808 else if ((insn
& 0xdc00) == 0x8c00) /* beqz16/bnez16 */
18810 unsigned long regno
;
18812 regno
= (insn
>> MICROMIPSOP_SH_MD
) & MICROMIPSOP_MASK_MD
;
18813 regno
= micromips_to_32_reg_d_map
[regno
];
18814 insn
= ((insn
& 0x2000) << 16) | 0x94000000; /* beq/bne */
18815 insn
|= regno
<< MICROMIPSOP_SH_RS
;
18820 /* Nothing else to do, just write it out. */
18821 if (!RELAX_MICROMIPS_RELAX32 (fragp
->fr_subtype
)
18822 || !RELAX_MICROMIPS_TOOFAR32 (fragp
->fr_subtype
))
18824 buf
= write_compressed_insn (buf
, insn
, 4);
18826 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18827 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18832 insn
= read_compressed_insn (buf
, 4);
18834 /* Relax 32-bit branches to a sequence of instructions. */
18835 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
18836 _("relaxed out-of-range branch into a jump"));
18838 /* Set the short-delay-slot bit. */
18839 short_ds
= !al
|| (insn
& 0x02000000) != 0;
18841 if (!RELAX_MICROMIPS_UNCOND (fragp
->fr_subtype
))
18845 /* Reverse the branch. */
18846 if ((insn
& 0xfc000000) == 0x94000000 /* beq */
18847 || (insn
& 0xfc000000) == 0xb4000000) /* bne */
18848 insn
^= 0x20000000;
18849 else if ((insn
& 0xffe00000) == 0x40000000 /* bltz */
18850 || (insn
& 0xffe00000) == 0x40400000 /* bgez */
18851 || (insn
& 0xffe00000) == 0x40800000 /* blez */
18852 || (insn
& 0xffe00000) == 0x40c00000 /* bgtz */
18853 || (insn
& 0xffe00000) == 0x40a00000 /* bnezc */
18854 || (insn
& 0xffe00000) == 0x40e00000 /* beqzc */
18855 || (insn
& 0xffe00000) == 0x40200000 /* bltzal */
18856 || (insn
& 0xffe00000) == 0x40600000 /* bgezal */
18857 || (insn
& 0xffe00000) == 0x42200000 /* bltzals */
18858 || (insn
& 0xffe00000) == 0x42600000) /* bgezals */
18859 insn
^= 0x00400000;
18860 else if ((insn
& 0xffe30000) == 0x43800000 /* bc1f */
18861 || (insn
& 0xffe30000) == 0x43a00000 /* bc1t */
18862 || (insn
& 0xffe30000) == 0x42800000 /* bc2f */
18863 || (insn
& 0xffe30000) == 0x42a00000) /* bc2t */
18864 insn
^= 0x00200000;
18865 else if ((insn
& 0xff000000) == 0x83000000 /* BZ.df
18867 || (insn
& 0xff600000) == 0x81600000) /* BZ.V
18869 insn
^= 0x00800000;
18875 /* Clear the and-link and short-delay-slot bits. */
18876 gas_assert ((insn
& 0xfda00000) == 0x40200000);
18878 /* bltzal 0x40200000 bgezal 0x40600000 */
18879 /* bltzals 0x42200000 bgezals 0x42600000 */
18880 insn
&= ~0x02200000;
18883 /* Make a label at the end for use with the branch. */
18884 l
= symbol_new (micromips_label_name (), asec
, fragp
, fragp
->fr_fix
);
18885 micromips_label_inc ();
18886 S_SET_OTHER (l
, ELF_ST_SET_MICROMIPS (S_GET_OTHER (l
)));
18889 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4, l
, 0, TRUE
,
18890 BFD_RELOC_MICROMIPS_16_PCREL_S1
);
18891 fixp
->fx_file
= fragp
->fr_file
;
18892 fixp
->fx_line
= fragp
->fr_line
;
18894 /* Branch over the jump. */
18895 buf
= write_compressed_insn (buf
, insn
, 4);
18901 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18903 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18909 unsigned long jal
= (short_ds
|| nods
18910 ? 0x74000000 : 0xf4000000); /* jal/s */
18912 /* j/jal/jals <sym> R_MICROMIPS_26_S1 */
18913 insn
= al
? jal
: 0xd4000000;
18915 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18916 fragp
->fr_symbol
, fragp
->fr_offset
,
18917 FALSE
, BFD_RELOC_MICROMIPS_JMP
);
18918 fixp
->fx_file
= fragp
->fr_file
;
18919 fixp
->fx_line
= fragp
->fr_line
;
18921 buf
= write_compressed_insn (buf
, insn
, 4);
18923 if (compact
|| nods
)
18927 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18929 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18934 unsigned long at
= RELAX_MICROMIPS_AT (fragp
->fr_subtype
);
18936 /* lw/ld $at, <sym>($gp) R_MICROMIPS_GOT16 */
18937 insn
= HAVE_64BIT_ADDRESSES
? 0xdc1c0000 : 0xfc1c0000;
18938 insn
|= at
<< MICROMIPSOP_SH_RT
;
18940 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18941 fragp
->fr_symbol
, fragp
->fr_offset
,
18942 FALSE
, BFD_RELOC_MICROMIPS_GOT16
);
18943 fixp
->fx_file
= fragp
->fr_file
;
18944 fixp
->fx_line
= fragp
->fr_line
;
18946 buf
= write_compressed_insn (buf
, insn
, 4);
18948 /* d/addiu $at, $at, <sym> R_MICROMIPS_LO16 */
18949 insn
= HAVE_64BIT_ADDRESSES
? 0x5c000000 : 0x30000000;
18950 insn
|= at
<< MICROMIPSOP_SH_RT
| at
<< MICROMIPSOP_SH_RS
;
18952 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
18953 fragp
->fr_symbol
, fragp
->fr_offset
,
18954 FALSE
, BFD_RELOC_MICROMIPS_LO16
);
18955 fixp
->fx_file
= fragp
->fr_file
;
18956 fixp
->fx_line
= fragp
->fr_line
;
18958 buf
= write_compressed_insn (buf
, insn
, 4);
18963 insn
= 0x00000f3c | (al
? RA
: ZERO
) << MICROMIPSOP_SH_RT
;
18964 insn
|= at
<< MICROMIPSOP_SH_RS
;
18966 buf
= write_compressed_insn (buf
, insn
, 4);
18968 if (compact
|| nods
)
18970 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18974 /* jr/jrc/jalr/jalrs $at */
18975 unsigned long jalr
= short_ds
? 0x45e0 : 0x45c0; /* jalr/s */
18976 unsigned long jr
= compact
|| nods
? 0x45a0 : 0x4580; /* jr/c */
18978 insn
= al
? jalr
: jr
;
18979 insn
|= at
<< MICROMIPSOP_SH_MJ
;
18981 buf
= write_compressed_insn (buf
, insn
, 2);
18986 buf
= write_compressed_insn (buf
, 0x0c00, 2);
18988 buf
= write_compressed_insn (buf
, 0x00000000, 4);
18993 gas_assert (buf
== fragp
->fr_literal
+ fragp
->fr_fix
);
18997 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
19000 const struct mips_int_operand
*operand
;
19003 unsigned int user_length
;
19004 bfd_boolean need_reloc
;
19005 unsigned long insn
;
19010 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
19011 operand
= mips16_immed_operand (type
, FALSE
);
19013 mac
= RELAX_MIPS16_MACRO (fragp
->fr_subtype
);
19014 ext
= RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
);
19015 val
= resolve_symbol_value (fragp
->fr_symbol
) + fragp
->fr_offset
;
19017 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
19018 need_reloc
= (S_FORCE_RELOC (fragp
->fr_symbol
, TRUE
)
19019 || (operand
->root
.type
== OP_PCREL
&& !mac
19021 : !bfd_is_abs_section (symsec
)));
19023 if (operand
->root
.type
== OP_PCREL
&& !mac
)
19025 const struct mips_pcrel_operand
*pcrel_op
;
19027 pcrel_op
= (const struct mips_pcrel_operand
*) operand
;
19029 if (pcrel_op
->include_isa_bit
&& !need_reloc
)
19031 if (!mips_ignore_branch_isa
19032 && !ELF_ST_IS_MIPS16 (S_GET_OTHER (fragp
->fr_symbol
)))
19033 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19034 _("branch to a symbol in another ISA mode"));
19035 else if ((fragp
->fr_offset
& 0x1) != 0)
19036 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19037 _("branch to misaligned address (0x%lx)"),
19038 (long) (resolve_symbol_value (fragp
->fr_symbol
)
19039 + (fragp
->fr_offset
& ~1)));
19042 val
= mips16_pcrel_val (fragp
, pcrel_op
, val
, 0);
19044 /* Make sure the section winds up with the alignment we have
19046 if (operand
->shift
> 0)
19047 record_alignment (asec
, operand
->shift
);
19050 if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
19051 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
19054 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19055 _("macro instruction expanded into multiple "
19056 "instructions in a branch delay slot"));
19058 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19059 _("extended instruction in a branch delay slot"));
19061 else if (RELAX_MIPS16_NOMACRO (fragp
->fr_subtype
) && mac
)
19062 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
19063 _("macro instruction expanded into multiple "
19066 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19068 insn
= read_compressed_insn (buf
, 2);
19070 insn
|= MIPS16_EXTEND
;
19072 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
19074 else if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
19086 gas_assert (type
== 'A' || type
== 'B' || type
== 'E');
19087 gas_assert (RELAX_MIPS16_SYM32 (fragp
->fr_subtype
));
19089 e2
= RELAX_MIPS16_E2 (fragp
->fr_subtype
);
19095 gas_assert (!RELAX_MIPS16_PIC (fragp
->fr_subtype
));
19097 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19098 fragp
->fr_symbol
, fragp
->fr_offset
,
19099 FALSE
, BFD_RELOC_MIPS16_HI16_S
);
19100 fixp
->fx_file
= fragp
->fr_file
;
19101 fixp
->fx_line
= fragp
->fr_line
;
19103 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
+ (e2
? 4 : 8), 4,
19104 fragp
->fr_symbol
, fragp
->fr_offset
,
19105 FALSE
, BFD_RELOC_MIPS16_LO16
);
19106 fixp
->fx_file
= fragp
->fr_file
;
19107 fixp
->fx_line
= fragp
->fr_line
;
19112 switch (insn
& 0xf800)
19114 case 0x0800: /* ADDIU */
19115 reg
= (insn
>> 8) & 0x7;
19116 op
= 0xf0004800 | (reg
<< 8);
19118 case 0xb000: /* LW */
19119 reg
= (insn
>> 8) & 0x7;
19120 op
= 0xf0009800 | (reg
<< 8) | (reg
<< 5);
19122 case 0xf800: /* I64 */
19123 reg
= (insn
>> 5) & 0x7;
19124 switch (insn
& 0x0700)
19126 case 0x0400: /* LD */
19127 op
= 0xf0003800 | (reg
<< 8) | (reg
<< 5);
19129 case 0x0600: /* DADDIU */
19130 op
= 0xf000fd00 | (reg
<< 5);
19140 new = (e2
? 0xf0006820 : 0xf0006800) | (reg
<< 8); /* LUI/LI */
19141 new |= mips16_immed_extend ((val
+ 0x8000) >> 16, 16);
19142 buf
= write_compressed_insn (buf
, new, 4);
19145 new = 0xf4003000 | (reg
<< 8) | (reg
<< 5); /* SLL */
19146 buf
= write_compressed_insn (buf
, new, 4);
19148 op
|= mips16_immed_extend (val
, 16);
19149 buf
= write_compressed_insn (buf
, op
, 4);
19151 fragp
->fr_fix
+= e2
? 8 : 12;
19155 unsigned int length
= ext
? 4 : 2;
19159 bfd_reloc_code_real_type reloc
= BFD_RELOC_NONE
;
19166 reloc
= BFD_RELOC_MIPS16_16_PCREL_S1
;
19171 if (mac
|| reloc
== BFD_RELOC_NONE
)
19172 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19173 _("unsupported relocation"));
19176 fixp
= fix_new (fragp
, buf
- fragp
->fr_literal
, 4,
19177 fragp
->fr_symbol
, fragp
->fr_offset
,
19179 fixp
->fx_file
= fragp
->fr_file
;
19180 fixp
->fx_line
= fragp
->fr_line
;
19183 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
19184 _("invalid unextended operand value"));
19187 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
,
19188 BFD_RELOC_UNUSED
, val
, user_length
, &insn
);
19190 gas_assert (mips16_opcode_length (insn
) == length
);
19191 write_compressed_insn (buf
, insn
, length
);
19192 fragp
->fr_fix
+= length
;
19197 relax_substateT subtype
= fragp
->fr_subtype
;
19198 bfd_boolean second_longer
= (subtype
& RELAX_SECOND_LONGER
) != 0;
19199 bfd_boolean use_second
= (subtype
& RELAX_USE_SECOND
) != 0;
19200 unsigned int first
, second
;
19203 first
= RELAX_FIRST (subtype
);
19204 second
= RELAX_SECOND (subtype
);
19205 fixp
= (fixS
*) fragp
->fr_opcode
;
19207 /* If the delay slot chosen does not match the size of the instruction,
19208 then emit a warning. */
19209 if ((!use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_FIRST
) != 0)
19210 || (use_second
&& (subtype
& RELAX_DELAY_SLOT_SIZE_SECOND
) != 0))
19215 s
= subtype
& (RELAX_DELAY_SLOT_16BIT
19216 | RELAX_DELAY_SLOT_SIZE_FIRST
19217 | RELAX_DELAY_SLOT_SIZE_SECOND
);
19218 msg
= macro_warning (s
);
19220 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19224 /* Possibly emit a warning if we've chosen the longer option. */
19225 if (use_second
== second_longer
)
19231 & (RELAX_SECOND_LONGER
| RELAX_NOMACRO
| RELAX_DELAY_SLOT
));
19232 msg
= macro_warning (s
);
19234 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, "%s", msg
);
19238 /* Go through all the fixups for the first sequence. Disable them
19239 (by marking them as done) if we're going to use the second
19240 sequence instead. */
19242 && fixp
->fx_frag
== fragp
19243 && fixp
->fx_where
+ second
< fragp
->fr_fix
)
19245 if (subtype
& RELAX_USE_SECOND
)
19247 fixp
= fixp
->fx_next
;
19250 /* Go through the fixups for the second sequence. Disable them if
19251 we're going to use the first sequence, otherwise adjust their
19252 addresses to account for the relaxation. */
19253 while (fixp
&& fixp
->fx_frag
== fragp
)
19255 if (subtype
& RELAX_USE_SECOND
)
19256 fixp
->fx_where
-= first
;
19259 fixp
= fixp
->fx_next
;
19262 /* Now modify the frag contents. */
19263 if (subtype
& RELAX_USE_SECOND
)
19267 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
19268 memmove (start
, start
+ first
, second
);
19269 fragp
->fr_fix
-= first
;
19272 fragp
->fr_fix
-= second
;
19276 /* This function is called after the relocs have been generated.
19277 We've been storing mips16 text labels as odd. Here we convert them
19278 back to even for the convenience of the debugger. */
19281 mips_frob_file_after_relocs (void)
19284 unsigned int count
, i
;
19286 syms
= bfd_get_outsymbols (stdoutput
);
19287 count
= bfd_get_symcount (stdoutput
);
19288 for (i
= 0; i
< count
; i
++, syms
++)
19289 if (ELF_ST_IS_COMPRESSED (elf_symbol (*syms
)->internal_elf_sym
.st_other
)
19290 && ((*syms
)->value
& 1) != 0)
19292 (*syms
)->value
&= ~1;
19293 /* If the symbol has an odd size, it was probably computed
19294 incorrectly, so adjust that as well. */
19295 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
19296 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
19300 /* This function is called whenever a label is defined, including fake
19301 labels instantiated off the dot special symbol. It is used when
19302 handling branch delays; if a branch has a label, we assume we cannot
19303 move it. This also bumps the value of the symbol by 1 in compressed
19307 mips_record_label (symbolS
*sym
)
19309 segment_info_type
*si
= seg_info (now_seg
);
19310 struct insn_label_list
*l
;
19312 if (free_insn_labels
== NULL
)
19313 l
= XNEW (struct insn_label_list
);
19316 l
= free_insn_labels
;
19317 free_insn_labels
= l
->next
;
19321 l
->next
= si
->label_list
;
19322 si
->label_list
= l
;
19325 /* This function is called as tc_frob_label() whenever a label is defined
19326 and adds a DWARF-2 record we only want for true labels. */
19329 mips_define_label (symbolS
*sym
)
19331 mips_record_label (sym
);
19332 dwarf2_emit_label (sym
);
19335 /* This function is called by tc_new_dot_label whenever a new dot symbol
19339 mips_add_dot_label (symbolS
*sym
)
19341 mips_record_label (sym
);
19342 if (mips_assembling_insn
&& HAVE_CODE_COMPRESSION
)
19343 mips_compressed_mark_label (sym
);
19346 /* Converting ASE flags from internal to .MIPS.abiflags values. */
19347 static unsigned int
19348 mips_convert_ase_flags (int ase
)
19350 unsigned int ext_ases
= 0;
19353 ext_ases
|= AFL_ASE_DSP
;
19354 if (ase
& ASE_DSPR2
)
19355 ext_ases
|= AFL_ASE_DSPR2
;
19356 if (ase
& ASE_DSPR3
)
19357 ext_ases
|= AFL_ASE_DSPR3
;
19359 ext_ases
|= AFL_ASE_EVA
;
19361 ext_ases
|= AFL_ASE_MCU
;
19362 if (ase
& ASE_MDMX
)
19363 ext_ases
|= AFL_ASE_MDMX
;
19364 if (ase
& ASE_MIPS3D
)
19365 ext_ases
|= AFL_ASE_MIPS3D
;
19367 ext_ases
|= AFL_ASE_MT
;
19368 if (ase
& ASE_SMARTMIPS
)
19369 ext_ases
|= AFL_ASE_SMARTMIPS
;
19370 if (ase
& ASE_VIRT
)
19371 ext_ases
|= AFL_ASE_VIRT
;
19373 ext_ases
|= AFL_ASE_MSA
;
19375 ext_ases
|= AFL_ASE_XPA
;
19376 if (ase
& ASE_MIPS16E2
)
19377 ext_ases
|= file_ase_mips16
? AFL_ASE_MIPS16E2
: 0;
19379 ext_ases
|= AFL_ASE_CRC
;
19380 if (ase
& ASE_GINV
)
19381 ext_ases
|= AFL_ASE_GINV
;
19382 if (ase
& ASE_LOONGSON_MMI
)
19383 ext_ases
|= AFL_ASE_LOONGSON_MMI
;
19384 if (ase
& ASE_LOONGSON_CAM
)
19385 ext_ases
|= AFL_ASE_LOONGSON_CAM
;
19386 if (ase
& ASE_LOONGSON_EXT
)
19387 ext_ases
|= AFL_ASE_LOONGSON_EXT
;
19388 if (ase
& ASE_LOONGSON_EXT2
)
19389 ext_ases
|= AFL_ASE_LOONGSON_EXT2
;
19393 /* Some special processing for a MIPS ELF file. */
19396 mips_elf_final_processing (void)
19399 Elf_Internal_ABIFlags_v0 flags
;
19403 switch (file_mips_opts
.isa
)
19406 flags
.isa_level
= 1;
19409 flags
.isa_level
= 2;
19412 flags
.isa_level
= 3;
19415 flags
.isa_level
= 4;
19418 flags
.isa_level
= 5;
19421 flags
.isa_level
= 32;
19425 flags
.isa_level
= 32;
19429 flags
.isa_level
= 32;
19433 flags
.isa_level
= 32;
19437 flags
.isa_level
= 32;
19441 flags
.isa_level
= 64;
19445 flags
.isa_level
= 64;
19449 flags
.isa_level
= 64;
19453 flags
.isa_level
= 64;
19457 flags
.isa_level
= 64;
19462 flags
.gpr_size
= file_mips_opts
.gp
== 32 ? AFL_REG_32
: AFL_REG_64
;
19463 flags
.cpr1_size
= file_mips_opts
.soft_float
? AFL_REG_NONE
19464 : (file_mips_opts
.ase
& ASE_MSA
) ? AFL_REG_128
19465 : (file_mips_opts
.fp
== 64) ? AFL_REG_64
19467 flags
.cpr2_size
= AFL_REG_NONE
;
19468 flags
.fp_abi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19469 Tag_GNU_MIPS_ABI_FP
);
19470 flags
.isa_ext
= bfd_mips_isa_ext (stdoutput
);
19471 flags
.ases
= mips_convert_ase_flags (file_mips_opts
.ase
);
19472 if (file_ase_mips16
)
19473 flags
.ases
|= AFL_ASE_MIPS16
;
19474 if (file_ase_micromips
)
19475 flags
.ases
|= AFL_ASE_MICROMIPS
;
19477 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts
.isa
, file_mips_opts
.arch
)
19478 || file_mips_opts
.fp
== 64)
19479 && file_mips_opts
.oddspreg
)
19480 flags
.flags1
|= AFL_FLAGS1_ODDSPREG
;
19483 bfd_mips_elf_swap_abiflags_v0_out (stdoutput
, &flags
,
19484 ((Elf_External_ABIFlags_v0
*)
19487 /* Write out the register information. */
19488 if (mips_abi
!= N64_ABI
)
19492 s
.ri_gprmask
= mips_gprmask
;
19493 s
.ri_cprmask
[0] = mips_cprmask
[0];
19494 s
.ri_cprmask
[1] = mips_cprmask
[1];
19495 s
.ri_cprmask
[2] = mips_cprmask
[2];
19496 s
.ri_cprmask
[3] = mips_cprmask
[3];
19497 /* The gp_value field is set by the MIPS ELF backend. */
19499 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
19500 ((Elf32_External_RegInfo
*)
19501 mips_regmask_frag
));
19505 Elf64_Internal_RegInfo s
;
19507 s
.ri_gprmask
= mips_gprmask
;
19509 s
.ri_cprmask
[0] = mips_cprmask
[0];
19510 s
.ri_cprmask
[1] = mips_cprmask
[1];
19511 s
.ri_cprmask
[2] = mips_cprmask
[2];
19512 s
.ri_cprmask
[3] = mips_cprmask
[3];
19513 /* The gp_value field is set by the MIPS ELF backend. */
19515 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
19516 ((Elf64_External_RegInfo
*)
19517 mips_regmask_frag
));
19520 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
19521 sort of BFD interface for this. */
19522 if (mips_any_noreorder
)
19523 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
19524 if (mips_pic
!= NO_PIC
)
19526 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
19527 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19530 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
19532 /* Set MIPS ELF flags for ASEs. Note that not all ASEs have flags
19533 defined at present; this might need to change in future. */
19534 if (file_ase_mips16
)
19535 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
19536 if (file_ase_micromips
)
19537 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MICROMIPS
;
19538 if (file_mips_opts
.ase
& ASE_MDMX
)
19539 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
19541 /* Set the MIPS ELF ABI flags. */
19542 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
19543 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
19544 else if (mips_abi
== O64_ABI
)
19545 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
19546 else if (mips_abi
== EABI_ABI
)
19548 if (file_mips_opts
.gp
== 64)
19549 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
19551 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
19554 /* Nothing to do for N32_ABI or N64_ABI. */
19556 if (mips_32bitmode
)
19557 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
19559 if (mips_nan2008
== 1)
19560 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NAN2008
;
19562 /* 32 bit code with 64 bit FP registers. */
19563 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
19564 Tag_GNU_MIPS_ABI_FP
);
19565 if (fpabi
== Val_GNU_MIPS_ABI_FP_OLD_64
)
19566 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_FP64
;
19569 typedef struct proc
{
19571 symbolS
*func_end_sym
;
19572 unsigned long reg_mask
;
19573 unsigned long reg_offset
;
19574 unsigned long fpreg_mask
;
19575 unsigned long fpreg_offset
;
19576 unsigned long frame_offset
;
19577 unsigned long frame_reg
;
19578 unsigned long pc_reg
;
19581 static procS cur_proc
;
19582 static procS
*cur_proc_ptr
;
19583 static int numprocs
;
19585 /* Implement NOP_OPCODE. We encode a MIPS16 nop as "1", a microMIPS nop
19586 as "2", and a normal nop as "0". */
19588 #define NOP_OPCODE_MIPS 0
19589 #define NOP_OPCODE_MIPS16 1
19590 #define NOP_OPCODE_MICROMIPS 2
19593 mips_nop_opcode (void)
19595 if (seg_info (now_seg
)->tc_segment_info_data
.micromips
)
19596 return NOP_OPCODE_MICROMIPS
;
19597 else if (seg_info (now_seg
)->tc_segment_info_data
.mips16
)
19598 return NOP_OPCODE_MIPS16
;
19600 return NOP_OPCODE_MIPS
;
19603 /* Fill in an rs_align_code fragment. Unlike elsewhere we want to use
19604 32-bit microMIPS NOPs here (if applicable). */
19607 mips_handle_align (fragS
*fragp
)
19611 int bytes
, size
, excess
;
19614 if (fragp
->fr_type
!= rs_align_code
)
19617 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
19619 switch (nop_opcode
)
19621 case NOP_OPCODE_MICROMIPS
:
19622 opcode
= micromips_nop32_insn
.insn_opcode
;
19625 case NOP_OPCODE_MIPS16
:
19626 opcode
= mips16_nop_insn
.insn_opcode
;
19629 case NOP_OPCODE_MIPS
:
19631 opcode
= nop_insn
.insn_opcode
;
19636 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
19637 excess
= bytes
% size
;
19639 /* Handle the leading part if we're not inserting a whole number of
19640 instructions, and make it the end of the fixed part of the frag.
19641 Try to fit in a short microMIPS NOP if applicable and possible,
19642 and use zeroes otherwise. */
19643 gas_assert (excess
< 4);
19644 fragp
->fr_fix
+= excess
;
19649 /* Fall through. */
19651 if (nop_opcode
== NOP_OPCODE_MICROMIPS
&& !mips_opts
.insn32
)
19653 p
= write_compressed_insn (p
, micromips_nop16_insn
.insn_opcode
, 2);
19657 /* Fall through. */
19660 /* Fall through. */
19665 md_number_to_chars (p
, opcode
, size
);
19666 fragp
->fr_var
= size
;
19675 if (*input_line_pointer
== '-')
19677 ++input_line_pointer
;
19680 if (!ISDIGIT (*input_line_pointer
))
19681 as_bad (_("expected simple number"));
19682 if (input_line_pointer
[0] == '0')
19684 if (input_line_pointer
[1] == 'x')
19686 input_line_pointer
+= 2;
19687 while (ISXDIGIT (*input_line_pointer
))
19690 val
|= hex_value (*input_line_pointer
++);
19692 return negative
? -val
: val
;
19696 ++input_line_pointer
;
19697 while (ISDIGIT (*input_line_pointer
))
19700 val
|= *input_line_pointer
++ - '0';
19702 return negative
? -val
: val
;
19705 if (!ISDIGIT (*input_line_pointer
))
19707 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
19708 *input_line_pointer
, *input_line_pointer
);
19709 as_warn (_("invalid number"));
19712 while (ISDIGIT (*input_line_pointer
))
19715 val
+= *input_line_pointer
++ - '0';
19717 return negative
? -val
: val
;
19720 /* The .file directive; just like the usual .file directive, but there
19721 is an initial number which is the ECOFF file index. In the non-ECOFF
19722 case .file implies DWARF-2. */
19725 s_mips_file (int x ATTRIBUTE_UNUSED
)
19727 static int first_file_directive
= 0;
19729 if (ECOFF_DEBUGGING
)
19738 filename
= dwarf2_directive_filename ();
19740 /* Versions of GCC up to 3.1 start files with a ".file"
19741 directive even for stabs output. Make sure that this
19742 ".file" is handled. Note that you need a version of GCC
19743 after 3.1 in order to support DWARF-2 on MIPS. */
19744 if (filename
!= NULL
&& ! first_file_directive
)
19746 (void) new_logical_line (filename
, -1);
19747 s_app_file_string (filename
, 0);
19749 first_file_directive
= 1;
19753 /* The .loc directive, implying DWARF-2. */
19756 s_mips_loc (int x ATTRIBUTE_UNUSED
)
19758 if (!ECOFF_DEBUGGING
)
19759 dwarf2_directive_loc (0);
19762 /* The .end directive. */
19765 s_mips_end (int x ATTRIBUTE_UNUSED
)
19769 /* Following functions need their own .frame and .cprestore directives. */
19770 mips_frame_reg_valid
= 0;
19771 mips_cprestore_valid
= 0;
19773 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
19776 demand_empty_rest_of_line ();
19781 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19782 as_warn (_(".end not in text section"));
19786 as_warn (_(".end directive without a preceding .ent directive"));
19787 demand_empty_rest_of_line ();
19793 gas_assert (S_GET_NAME (p
));
19794 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
19795 as_warn (_(".end symbol does not match .ent symbol"));
19797 if (debug_type
== DEBUG_STABS
)
19798 stabs_generate_asm_endfunc (S_GET_NAME (p
),
19802 as_warn (_(".end directive missing or unknown symbol"));
19804 /* Create an expression to calculate the size of the function. */
19805 if (p
&& cur_proc_ptr
)
19807 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
19808 expressionS
*exp
= XNEW (expressionS
);
19811 exp
->X_op
= O_subtract
;
19812 exp
->X_add_symbol
= symbol_temp_new_now ();
19813 exp
->X_op_symbol
= p
;
19814 exp
->X_add_number
= 0;
19816 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
19819 #ifdef md_flush_pending_output
19820 md_flush_pending_output ();
19823 /* Generate a .pdr section. */
19824 if (!ECOFF_DEBUGGING
&& mips_flag_pdr
)
19826 segT saved_seg
= now_seg
;
19827 subsegT saved_subseg
= now_subseg
;
19831 gas_assert (pdr_seg
);
19832 subseg_set (pdr_seg
, 0);
19834 /* Write the symbol. */
19835 exp
.X_op
= O_symbol
;
19836 exp
.X_add_symbol
= p
;
19837 exp
.X_add_number
= 0;
19838 emit_expr (&exp
, 4);
19840 fragp
= frag_more (7 * 4);
19842 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
19843 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
19844 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
19845 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
19846 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
19847 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
19848 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
19850 subseg_set (saved_seg
, saved_subseg
);
19853 cur_proc_ptr
= NULL
;
19856 /* The .aent and .ent directives. */
19859 s_mips_ent (int aent
)
19863 symbolP
= get_symbol ();
19864 if (*input_line_pointer
== ',')
19865 ++input_line_pointer
;
19866 SKIP_WHITESPACE ();
19867 if (ISDIGIT (*input_line_pointer
)
19868 || *input_line_pointer
== '-')
19871 if ((bfd_section_flags (now_seg
) & SEC_CODE
) == 0)
19872 as_warn (_(".ent or .aent not in text section"));
19874 if (!aent
&& cur_proc_ptr
)
19875 as_warn (_("missing .end"));
19879 /* This function needs its own .frame and .cprestore directives. */
19880 mips_frame_reg_valid
= 0;
19881 mips_cprestore_valid
= 0;
19883 cur_proc_ptr
= &cur_proc
;
19884 memset (cur_proc_ptr
, '\0', sizeof (procS
));
19886 cur_proc_ptr
->func_sym
= symbolP
;
19890 if (debug_type
== DEBUG_STABS
)
19891 stabs_generate_asm_func (S_GET_NAME (symbolP
),
19892 S_GET_NAME (symbolP
));
19895 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
19897 demand_empty_rest_of_line ();
19900 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
19901 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
19902 s_mips_frame is used so that we can set the PDR information correctly.
19903 We can't use the ecoff routines because they make reference to the ecoff
19904 symbol table (in the mdebug section). */
19907 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
19909 if (ECOFF_DEBUGGING
)
19915 if (cur_proc_ptr
== (procS
*) NULL
)
19917 as_warn (_(".frame outside of .ent"));
19918 demand_empty_rest_of_line ();
19922 cur_proc_ptr
->frame_reg
= tc_get_register (1);
19924 SKIP_WHITESPACE ();
19925 if (*input_line_pointer
++ != ','
19926 || get_absolute_expression_and_terminator (&val
) != ',')
19928 as_warn (_("bad .frame directive"));
19929 --input_line_pointer
;
19930 demand_empty_rest_of_line ();
19934 cur_proc_ptr
->frame_offset
= val
;
19935 cur_proc_ptr
->pc_reg
= tc_get_register (0);
19937 demand_empty_rest_of_line ();
19941 /* The .fmask and .mask directives. If the mdebug section is present
19942 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
19943 embedded targets, s_mips_mask is used so that we can set the PDR
19944 information correctly. We can't use the ecoff routines because they
19945 make reference to the ecoff symbol table (in the mdebug section). */
19948 s_mips_mask (int reg_type
)
19950 if (ECOFF_DEBUGGING
)
19951 s_ignore (reg_type
);
19956 if (cur_proc_ptr
== (procS
*) NULL
)
19958 as_warn (_(".mask/.fmask outside of .ent"));
19959 demand_empty_rest_of_line ();
19963 if (get_absolute_expression_and_terminator (&mask
) != ',')
19965 as_warn (_("bad .mask/.fmask directive"));
19966 --input_line_pointer
;
19967 demand_empty_rest_of_line ();
19971 off
= get_absolute_expression ();
19973 if (reg_type
== 'F')
19975 cur_proc_ptr
->fpreg_mask
= mask
;
19976 cur_proc_ptr
->fpreg_offset
= off
;
19980 cur_proc_ptr
->reg_mask
= mask
;
19981 cur_proc_ptr
->reg_offset
= off
;
19984 demand_empty_rest_of_line ();
19988 /* A table describing all the processors gas knows about. Names are
19989 matched in the order listed.
19991 To ease comparison, please keep this table in the same order as
19992 gcc's mips_cpu_info_table[]. */
19993 static const struct mips_cpu_info mips_cpu_info_table
[] =
19995 /* Entries for generic ISAs. */
19996 { "mips1", MIPS_CPU_IS_ISA
, 0, ISA_MIPS1
, CPU_R3000
},
19997 { "mips2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS2
, CPU_R6000
},
19998 { "mips3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS3
, CPU_R4000
},
19999 { "mips4", MIPS_CPU_IS_ISA
, 0, ISA_MIPS4
, CPU_R8000
},
20000 { "mips5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS5
, CPU_MIPS5
},
20001 { "mips32", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32
, CPU_MIPS32
},
20002 { "mips32r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20003 { "mips32r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R3
, CPU_MIPS32R3
},
20004 { "mips32r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R5
, CPU_MIPS32R5
},
20005 { "mips32r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS32R6
, CPU_MIPS32R6
},
20006 { "mips64", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64
, CPU_MIPS64
},
20007 { "mips64r2", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R2
, CPU_MIPS64R2
},
20008 { "mips64r3", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R3
, CPU_MIPS64R3
},
20009 { "mips64r5", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R5
, CPU_MIPS64R5
},
20010 { "mips64r6", MIPS_CPU_IS_ISA
, 0, ISA_MIPS64R6
, CPU_MIPS64R6
},
20013 { "r3000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20014 { "r2000", 0, 0, ISA_MIPS1
, CPU_R3000
},
20015 { "r3900", 0, 0, ISA_MIPS1
, CPU_R3900
},
20018 { "r6000", 0, 0, ISA_MIPS2
, CPU_R6000
},
20021 { "r4000", 0, 0, ISA_MIPS3
, CPU_R4000
},
20022 { "r4010", 0, 0, ISA_MIPS2
, CPU_R4010
},
20023 { "vr4100", 0, 0, ISA_MIPS3
, CPU_VR4100
},
20024 { "vr4111", 0, 0, ISA_MIPS3
, CPU_R4111
},
20025 { "vr4120", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20026 { "vr4130", 0, 0, ISA_MIPS3
, CPU_VR4120
},
20027 { "vr4181", 0, 0, ISA_MIPS3
, CPU_R4111
},
20028 { "vr4300", 0, 0, ISA_MIPS3
, CPU_R4300
},
20029 { "r4400", 0, 0, ISA_MIPS3
, CPU_R4400
},
20030 { "r4600", 0, 0, ISA_MIPS3
, CPU_R4600
},
20031 { "orion", 0, 0, ISA_MIPS3
, CPU_R4600
},
20032 { "r4650", 0, 0, ISA_MIPS3
, CPU_R4650
},
20033 { "r5900", 0, 0, ISA_MIPS3
, CPU_R5900
},
20034 /* ST Microelectronics Loongson 2E and 2F cores. */
20035 { "loongson2e", 0, 0, ISA_MIPS3
, CPU_LOONGSON_2E
},
20036 { "loongson2f", 0, ASE_LOONGSON_MMI
, ISA_MIPS3
, CPU_LOONGSON_2F
},
20039 { "r8000", 0, 0, ISA_MIPS4
, CPU_R8000
},
20040 { "r10000", 0, 0, ISA_MIPS4
, CPU_R10000
},
20041 { "r12000", 0, 0, ISA_MIPS4
, CPU_R12000
},
20042 { "r14000", 0, 0, ISA_MIPS4
, CPU_R14000
},
20043 { "r16000", 0, 0, ISA_MIPS4
, CPU_R16000
},
20044 { "vr5000", 0, 0, ISA_MIPS4
, CPU_R5000
},
20045 { "vr5400", 0, 0, ISA_MIPS4
, CPU_VR5400
},
20046 { "vr5500", 0, 0, ISA_MIPS4
, CPU_VR5500
},
20047 { "rm5200", 0, 0, ISA_MIPS4
, CPU_R5000
},
20048 { "rm5230", 0, 0, ISA_MIPS4
, CPU_R5000
},
20049 { "rm5231", 0, 0, ISA_MIPS4
, CPU_R5000
},
20050 { "rm5261", 0, 0, ISA_MIPS4
, CPU_R5000
},
20051 { "rm5721", 0, 0, ISA_MIPS4
, CPU_R5000
},
20052 { "rm7000", 0, 0, ISA_MIPS4
, CPU_RM7000
},
20053 { "rm9000", 0, 0, ISA_MIPS4
, CPU_RM9000
},
20056 { "4kc", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20057 { "4km", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20058 { "4kp", 0, 0, ISA_MIPS32
, CPU_MIPS32
},
20059 { "4ksc", 0, ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
20061 /* MIPS 32 Release 2 */
20062 { "4kec", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20063 { "4kem", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20064 { "4kep", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20065 { "4ksd", 0, ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20066 { "m4k", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20067 { "m4kp", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20068 { "m14k", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20069 { "m14kc", 0, ASE_MCU
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20070 { "m14ke", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20071 ISA_MIPS32R2
, CPU_MIPS32R2
},
20072 { "m14kec", 0, ASE_DSP
| ASE_DSPR2
| ASE_MCU
,
20073 ISA_MIPS32R2
, CPU_MIPS32R2
},
20074 { "24kc", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20075 { "24kf2_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20076 { "24kf", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20077 { "24kf1_1", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20078 /* Deprecated forms of the above. */
20079 { "24kfx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20080 { "24kx", 0, 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
20081 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
20082 { "24kec", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20083 { "24kef2_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20084 { "24kef", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20085 { "24kef1_1", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20086 /* Deprecated forms of the above. */
20087 { "24kefx", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20088 { "24kex", 0, ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20089 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
20090 { "34kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20091 { "34kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20092 { "34kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20093 { "34kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20094 /* Deprecated forms of the above. */
20095 { "34kfx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20096 { "34kx", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20097 /* 34Kn is a 34kc without DSP. */
20098 { "34kn", 0, ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20099 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
20100 { "74kc", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20101 { "74kf2_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20102 { "74kf", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20103 { "74kf1_1", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20104 { "74kf3_2", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20105 /* Deprecated forms of the above. */
20106 { "74kfx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20107 { "74kx", 0, ASE_DSP
| ASE_DSPR2
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20108 /* 1004K cores are multiprocessor versions of the 34K. */
20109 { "1004kc", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20110 { "1004kf2_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20111 { "1004kf", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20112 { "1004kf1_1", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20113 /* interaptiv is the new name for 1004kf. */
20114 { "interaptiv", 0, ASE_DSP
| ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
20115 { "interaptiv-mr2", 0,
20116 ASE_DSP
| ASE_EVA
| ASE_MT
| ASE_MIPS16E2
| ASE_MIPS16E2_MT
,
20117 ISA_MIPS32R3
, CPU_INTERAPTIV_MR2
},
20118 /* M5100 family. */
20119 { "m5100", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20120 { "m5101", 0, ASE_MCU
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20121 /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
20122 { "p5600", 0, ASE_VIRT
| ASE_EVA
| ASE_XPA
, ISA_MIPS32R5
, CPU_MIPS32R5
},
20125 { "5kc", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20126 { "5kf", 0, 0, ISA_MIPS64
, CPU_MIPS64
},
20127 { "20kc", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20128 { "25kf", 0, ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
20130 /* Broadcom SB-1 CPU core. */
20131 { "sb1", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20132 /* Broadcom SB-1A CPU core. */
20133 { "sb1a", 0, ASE_MIPS3D
| ASE_MDMX
, ISA_MIPS64
, CPU_SB1
},
20135 /* MIPS 64 Release 2. */
20136 /* Loongson CPU core. */
20137 /* -march=loongson3a is an alias of -march=gs464 for compatibility. */
20138 { "loongson3a", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20139 ISA_MIPS64R2
, CPU_GS464
},
20140 { "gs464", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
,
20141 ISA_MIPS64R2
, CPU_GS464
},
20142 { "gs464e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20143 | ASE_LOONGSON_EXT2
, ISA_MIPS64R2
, CPU_GS464E
},
20144 { "gs264e", 0, ASE_LOONGSON_MMI
| ASE_LOONGSON_CAM
| ASE_LOONGSON_EXT
20145 | ASE_LOONGSON_EXT2
| ASE_MSA
| ASE_MSA64
, ISA_MIPS64R2
, CPU_GS264E
},
20147 /* Cavium Networks Octeon CPU core. */
20148 { "octeon", 0, 0, ISA_MIPS64R2
, CPU_OCTEON
},
20149 { "octeon+", 0, 0, ISA_MIPS64R2
, CPU_OCTEONP
},
20150 { "octeon2", 0, 0, ISA_MIPS64R2
, CPU_OCTEON2
},
20151 { "octeon3", 0, ASE_VIRT
| ASE_VIRT64
, ISA_MIPS64R5
, CPU_OCTEON3
},
20154 { "xlr", 0, 0, ISA_MIPS64
, CPU_XLR
},
20157 XLP is mostly like XLR, with the prominent exception that it is
20158 MIPS64R2 rather than MIPS64. */
20159 { "xlp", 0, 0, ISA_MIPS64R2
, CPU_XLR
},
20161 /* MIPS 64 Release 6. */
20162 { "i6400", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20163 { "i6500", 0, ASE_VIRT
| ASE_MSA
| ASE_CRC
| ASE_GINV
,
20164 ISA_MIPS64R6
, CPU_MIPS64R6
},
20165 { "p6600", 0, ASE_VIRT
| ASE_MSA
, ISA_MIPS64R6
, CPU_MIPS64R6
},
20168 { NULL
, 0, 0, 0, 0 }
20172 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
20173 with a final "000" replaced by "k". Ignore case.
20175 Note: this function is shared between GCC and GAS. */
20178 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
20180 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
20181 given
++, canonical
++;
20183 return ((*given
== 0 && *canonical
== 0)
20184 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
20188 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
20189 CPU name. We've traditionally allowed a lot of variation here.
20191 Note: this function is shared between GCC and GAS. */
20194 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
20196 /* First see if the name matches exactly, or with a final "000"
20197 turned into "k". */
20198 if (mips_strict_matching_cpu_name_p (canonical
, given
))
20201 /* If not, try comparing based on numerical designation alone.
20202 See if GIVEN is an unadorned number, or 'r' followed by a number. */
20203 if (TOLOWER (*given
) == 'r')
20205 if (!ISDIGIT (*given
))
20208 /* Skip over some well-known prefixes in the canonical name,
20209 hoping to find a number there too. */
20210 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
20212 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
20214 else if (TOLOWER (canonical
[0]) == 'r')
20217 return mips_strict_matching_cpu_name_p (canonical
, given
);
20221 /* Parse an option that takes the name of a processor as its argument.
20222 OPTION is the name of the option and CPU_STRING is the argument.
20223 Return the corresponding processor enumeration if the CPU_STRING is
20224 recognized, otherwise report an error and return null.
20226 A similar function exists in GCC. */
20228 static const struct mips_cpu_info
*
20229 mips_parse_cpu (const char *option
, const char *cpu_string
)
20231 const struct mips_cpu_info
*p
;
20233 /* 'from-abi' selects the most compatible architecture for the given
20234 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
20235 EABIs, we have to decide whether we're using the 32-bit or 64-bit
20236 version. Look first at the -mgp options, if given, otherwise base
20237 the choice on MIPS_DEFAULT_64BIT.
20239 Treat NO_ABI like the EABIs. One reason to do this is that the
20240 plain 'mips' and 'mips64' configs have 'from-abi' as their default
20241 architecture. This code picks MIPS I for 'mips' and MIPS III for
20242 'mips64', just as we did in the days before 'from-abi'. */
20243 if (strcasecmp (cpu_string
, "from-abi") == 0)
20245 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
20246 return mips_cpu_info_from_isa (ISA_MIPS1
);
20248 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
20249 return mips_cpu_info_from_isa (ISA_MIPS3
);
20251 if (file_mips_opts
.gp
>= 0)
20252 return mips_cpu_info_from_isa (file_mips_opts
.gp
== 32
20253 ? ISA_MIPS1
: ISA_MIPS3
);
20255 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
20260 /* 'default' has traditionally been a no-op. Probably not very useful. */
20261 if (strcasecmp (cpu_string
, "default") == 0)
20264 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
20265 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
20268 as_bad (_("bad value (%s) for %s"), cpu_string
, option
);
20272 /* Return the canonical processor information for ISA (a member of the
20273 ISA_MIPS* enumeration). */
20275 static const struct mips_cpu_info
*
20276 mips_cpu_info_from_isa (int isa
)
20280 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20281 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
20282 && isa
== mips_cpu_info_table
[i
].isa
)
20283 return (&mips_cpu_info_table
[i
]);
20288 static const struct mips_cpu_info
*
20289 mips_cpu_info_from_arch (int arch
)
20293 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20294 if (arch
== mips_cpu_info_table
[i
].cpu
)
20295 return (&mips_cpu_info_table
[i
]);
20301 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
20305 fprintf (stream
, "%24s", "");
20310 fprintf (stream
, ", ");
20314 if (*col_p
+ strlen (string
) > 72)
20316 fprintf (stream
, "\n%24s", "");
20320 fprintf (stream
, "%s", string
);
20321 *col_p
+= strlen (string
);
20327 md_show_usage (FILE *stream
)
20332 fprintf (stream
, _("\
20334 -EB generate big endian output\n\
20335 -EL generate little endian output\n\
20336 -g, -g2 do not remove unneeded NOPs or swap branches\n\
20337 -G NUM allow referencing objects up to NUM bytes\n\
20338 implicitly with the gp register [default 8]\n"));
20339 fprintf (stream
, _("\
20340 -mips1 generate MIPS ISA I instructions\n\
20341 -mips2 generate MIPS ISA II instructions\n\
20342 -mips3 generate MIPS ISA III instructions\n\
20343 -mips4 generate MIPS ISA IV instructions\n\
20344 -mips5 generate MIPS ISA V instructions\n\
20345 -mips32 generate MIPS32 ISA instructions\n\
20346 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
20347 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
20348 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
20349 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
20350 -mips64 generate MIPS64 ISA instructions\n\
20351 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
20352 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
20353 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
20354 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
20355 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
20359 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
20360 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
20361 show (stream
, "from-abi", &column
, &first
);
20362 fputc ('\n', stream
);
20364 fprintf (stream
, _("\
20365 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
20366 -no-mCPU don't generate code specific to CPU.\n\
20367 For -mCPU and -no-mCPU, CPU must be one of:\n"));
20371 show (stream
, "3900", &column
, &first
);
20372 show (stream
, "4010", &column
, &first
);
20373 show (stream
, "4100", &column
, &first
);
20374 show (stream
, "4650", &column
, &first
);
20375 fputc ('\n', stream
);
20377 fprintf (stream
, _("\
20378 -mips16 generate mips16 instructions\n\
20379 -no-mips16 do not generate mips16 instructions\n"));
20380 fprintf (stream
, _("\
20381 -mmips16e2 generate MIPS16e2 instructions\n\
20382 -mno-mips16e2 do not generate MIPS16e2 instructions\n"));
20383 fprintf (stream
, _("\
20384 -mmicromips generate microMIPS instructions\n\
20385 -mno-micromips do not generate microMIPS instructions\n"));
20386 fprintf (stream
, _("\
20387 -msmartmips generate smartmips instructions\n\
20388 -mno-smartmips do not generate smartmips instructions\n"));
20389 fprintf (stream
, _("\
20390 -mdsp generate DSP instructions\n\
20391 -mno-dsp do not generate DSP instructions\n"));
20392 fprintf (stream
, _("\
20393 -mdspr2 generate DSP R2 instructions\n\
20394 -mno-dspr2 do not generate DSP R2 instructions\n"));
20395 fprintf (stream
, _("\
20396 -mdspr3 generate DSP R3 instructions\n\
20397 -mno-dspr3 do not generate DSP R3 instructions\n"));
20398 fprintf (stream
, _("\
20399 -mmt generate MT instructions\n\
20400 -mno-mt do not generate MT instructions\n"));
20401 fprintf (stream
, _("\
20402 -mmcu generate MCU instructions\n\
20403 -mno-mcu do not generate MCU instructions\n"));
20404 fprintf (stream
, _("\
20405 -mmsa generate MSA instructions\n\
20406 -mno-msa do not generate MSA instructions\n"));
20407 fprintf (stream
, _("\
20408 -mxpa generate eXtended Physical Address (XPA) instructions\n\
20409 -mno-xpa do not generate eXtended Physical Address (XPA) instructions\n"));
20410 fprintf (stream
, _("\
20411 -mvirt generate Virtualization instructions\n\
20412 -mno-virt do not generate Virtualization instructions\n"));
20413 fprintf (stream
, _("\
20414 -mcrc generate CRC instructions\n\
20415 -mno-crc do not generate CRC instructions\n"));
20416 fprintf (stream
, _("\
20417 -mginv generate Global INValidate (GINV) instructions\n\
20418 -mno-ginv do not generate Global INValidate instructions\n"));
20419 fprintf (stream
, _("\
20420 -mloongson-mmi generate Loongson MultiMedia extensions Instructions (MMI) instructions\n\
20421 -mno-loongson-mmi do not generate Loongson MultiMedia extensions Instructions\n"));
20422 fprintf (stream
, _("\
20423 -mloongson-cam generate Loongson Content Address Memory (CAM) instructions\n\
20424 -mno-loongson-cam do not generate Loongson Content Address Memory Instructions\n"));
20425 fprintf (stream
, _("\
20426 -mloongson-ext generate Loongson EXTensions (EXT) instructions\n\
20427 -mno-loongson-ext do not generate Loongson EXTensions Instructions\n"));
20428 fprintf (stream
, _("\
20429 -mloongson-ext2 generate Loongson EXTensions R2 (EXT2) instructions\n\
20430 -mno-loongson-ext2 do not generate Loongson EXTensions R2 Instructions\n"));
20431 fprintf (stream
, _("\
20432 -minsn32 only generate 32-bit microMIPS instructions\n\
20433 -mno-insn32 generate all microMIPS instructions\n"));
20434 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
20435 fprintf (stream
, _("\
20436 -mfix-loongson3-llsc work around Loongson3 LL/SC errata, default\n\
20437 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n"));
20439 fprintf (stream
, _("\
20440 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20441 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata, default\n"));
20443 fprintf (stream
, _("\
20444 -mfix-loongson2f-jump work around Loongson2F JUMP instructions\n\
20445 -mfix-loongson2f-nop work around Loongson2F NOP errata\n\
20446 -mfix-loongson3-llsc work around Loongson3 LL/SC errata\n\
20447 -mno-fix-loongson3-llsc disable work around Loongson3 LL/SC errata\n\
20448 -mfix-vr4120 work around certain VR4120 errata\n\
20449 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
20450 -mfix-24k insert a nop after ERET and DERET instructions\n\
20451 -mfix-cn63xxp1 work around CN63XXP1 PREF errata\n\
20452 -mfix-r5900 work around R5900 short loop errata\n\
20453 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
20454 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
20455 -msym32 assume all symbols have 32-bit values\n\
20456 -O0 do not remove unneeded NOPs, do not swap branches\n\
20457 -O, -O1 remove unneeded NOPs, do not swap branches\n\
20458 -O2 remove unneeded NOPs and swap branches\n\
20459 --trap, --no-break trap exception on div by 0 and mult overflow\n\
20460 --break, --no-trap break exception on div by 0 and mult overflow\n"));
20461 fprintf (stream
, _("\
20462 -mhard-float allow floating-point instructions\n\
20463 -msoft-float do not allow floating-point instructions\n\
20464 -msingle-float only allow 32-bit floating-point operations\n\
20465 -mdouble-float allow 32-bit and 64-bit floating-point operations\n\
20466 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
20467 --[no-]relax-branch [dis]allow out-of-range branches to be relaxed\n\
20468 -mignore-branch-isa accept invalid branches requiring an ISA mode switch\n\
20469 -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch\n\
20470 -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of:\n"));
20474 show (stream
, "legacy", &column
, &first
);
20475 show (stream
, "2008", &column
, &first
);
20477 fputc ('\n', stream
);
20479 fprintf (stream
, _("\
20480 -KPIC, -call_shared generate SVR4 position independent code\n\
20481 -call_nonpic generate non-PIC code that can operate with DSOs\n\
20482 -mvxworks-pic generate VxWorks position independent code\n\
20483 -non_shared do not generate code that can operate with DSOs\n\
20484 -xgot assume a 32 bit GOT\n\
20485 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
20486 -mshared, -mno-shared disable/enable .cpload optimization for\n\
20487 position dependent (non shared) code\n\
20488 -mabi=ABI create ABI conformant object file for:\n"));
20492 show (stream
, "32", &column
, &first
);
20493 show (stream
, "o64", &column
, &first
);
20494 show (stream
, "n32", &column
, &first
);
20495 show (stream
, "64", &column
, &first
);
20496 show (stream
, "eabi", &column
, &first
);
20498 fputc ('\n', stream
);
20500 fprintf (stream
, _("\
20501 -32 create o32 ABI object file%s\n"),
20502 MIPS_DEFAULT_ABI
== O32_ABI
? _(" (default)") : "");
20503 fprintf (stream
, _("\
20504 -n32 create n32 ABI object file%s\n"),
20505 MIPS_DEFAULT_ABI
== N32_ABI
? _(" (default)") : "");
20506 fprintf (stream
, _("\
20507 -64 create 64 ABI object file%s\n"),
20508 MIPS_DEFAULT_ABI
== N64_ABI
? _(" (default)") : "");
20513 mips_dwarf2_format (asection
*sec ATTRIBUTE_UNUSED
)
20515 if (HAVE_64BIT_SYMBOLS
)
20516 return dwarf2_format_64bit_irix
;
20518 return dwarf2_format_32bit
;
20523 mips_dwarf2_addr_size (void)
20525 if (HAVE_64BIT_OBJECTS
)
20531 /* Standard calling conventions leave the CFA at SP on entry. */
20533 mips_cfi_frame_initial_instructions (void)
20535 cfi_add_CFA_def_cfa_register (SP
);
20539 tc_mips_regname_to_dw2regnum (char *regname
)
20541 unsigned int regnum
= -1;
20544 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))
20550 /* Implement CONVERT_SYMBOLIC_ATTRIBUTE.
20551 Given a symbolic attribute NAME, return the proper integer value.
20552 Returns -1 if the attribute is not known. */
20555 mips_convert_symbolic_attribute (const char *name
)
20557 static const struct
20562 attribute_table
[] =
20564 #define T(tag) {#tag, tag}
20565 T (Tag_GNU_MIPS_ABI_FP
),
20566 T (Tag_GNU_MIPS_ABI_MSA
),
20574 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
20575 if (streq (name
, attribute_table
[i
].name
))
20576 return attribute_table
[i
].tag
;
20584 int fpabi
= Val_GNU_MIPS_ABI_FP_ANY
;
20586 mips_emit_delays ();
20588 as_warn (_("missing .end at end of assembly"));
20590 /* Just in case no code was emitted, do the consistency check. */
20591 file_mips_check_options ();
20593 /* Set a floating-point ABI if the user did not. */
20594 if (obj_elf_seen_attribute (OBJ_ATTR_GNU
, Tag_GNU_MIPS_ABI_FP
))
20596 /* Perform consistency checks on the floating-point ABI. */
20597 fpabi
= bfd_elf_get_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20598 Tag_GNU_MIPS_ABI_FP
);
20599 if (fpabi
!= Val_GNU_MIPS_ABI_FP_ANY
)
20600 check_fpabi (fpabi
);
20604 /* Soft-float gets precedence over single-float, the two options should
20605 not be used together so this should not matter. */
20606 if (file_mips_opts
.soft_float
== 1)
20607 fpabi
= Val_GNU_MIPS_ABI_FP_SOFT
;
20608 /* Single-float gets precedence over all double_float cases. */
20609 else if (file_mips_opts
.single_float
== 1)
20610 fpabi
= Val_GNU_MIPS_ABI_FP_SINGLE
;
20613 switch (file_mips_opts
.fp
)
20616 if (file_mips_opts
.gp
== 32)
20617 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20620 fpabi
= Val_GNU_MIPS_ABI_FP_XX
;
20623 if (file_mips_opts
.gp
== 32 && !file_mips_opts
.oddspreg
)
20624 fpabi
= Val_GNU_MIPS_ABI_FP_64A
;
20625 else if (file_mips_opts
.gp
== 32)
20626 fpabi
= Val_GNU_MIPS_ABI_FP_64
;
20628 fpabi
= Val_GNU_MIPS_ABI_FP_DOUBLE
;
20633 bfd_elf_add_obj_attr_int (stdoutput
, OBJ_ATTR_GNU
,
20634 Tag_GNU_MIPS_ABI_FP
, fpabi
);
20638 /* Returns the relocation type required for a particular CFI encoding. */
20640 bfd_reloc_code_real_type
20641 mips_cfi_reloc_for_encoding (int encoding
)
20643 if (encoding
== (DW_EH_PE_sdata4
| DW_EH_PE_pcrel
))
20644 return BFD_RELOC_32_PCREL
;
20645 else return BFD_RELOC_NONE
;