1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 FIXME: The CPU specific variables (mips_4010, et. al.) should
146 probably be in here as well, and there should probably be some way
149 struct mips_set_options
151 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
152 if it has not been initialized. Changed by `.set mipsN', and the
153 -mipsN command line option, and the default CPU. */
155 /* Whether we are assembling for the mips16 processor. 0 if we are
156 not, 1 if we are, and -1 if the value has not been initialized.
157 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
158 -nomips16 command line options, and the default CPU. */
160 /* Non-zero if we should not reorder instructions. Changed by `.set
161 reorder' and `.set noreorder'. */
163 /* Non-zero if we should not permit the $at ($1) register to be used
164 in instructions. Changed by `.set at' and `.set noat'. */
166 /* Non-zero if we should warn when a macro instruction expands into
167 more than one machine instruction. Changed by `.set nomacro' and
169 int warn_about_macros
;
170 /* Non-zero if we should not move instructions. Changed by `.set
171 move', `.set volatile', `.set nomove', and `.set novolatile'. */
173 /* Non-zero if we should not optimize branches by moving the target
174 of the branch into the delay slot. Actually, we don't perform
175 this optimization anyhow. Changed by `.set bopt' and `.set
178 /* Non-zero if we should not autoextend mips16 instructions.
179 Changed by `.set autoextend' and `.set noautoextend'. */
183 /* This is the struct we use to hold the current set of options. Note
184 that we must set the isa and mips16 fields to -1 to indicate that
185 they have not been initialized. */
187 static struct mips_set_options mips_opts
= { -1, -1 };
189 /* These variables are filled in with the masks of registers used.
190 The object format code reads them and puts them in the appropriate
192 unsigned long mips_gprmask
;
193 unsigned long mips_cprmask
[4];
195 /* MIPS ISA we are using for this output file. */
196 static int file_mips_isa
;
198 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
199 static int mips_cpu
= -1;
201 /* Whether the 4650 instructions (mad/madu) are permitted. */
202 static int mips_4650
= -1;
204 /* Whether the 4010 instructions are permitted. */
205 static int mips_4010
= -1;
207 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
208 static int mips_4100
= -1;
210 /* start-sanitize-vr4xxx */
211 /* Whether NEC 4121 instructions are permitted. */
212 static int mips_4121
= -1;
214 /* end-sanitize-vr4xxx */
215 /* start-sanitize-vr4320 */
216 /* Whether NEC vr4320 instructions are permitted. */
217 static int mips_4320
= -1;
219 /* end-sanitize-vr4320 */
220 /* start-sanitize-cygnus */
221 /* Whether NEC vr5400 instructions are permitted. */
222 static int mips_5400
= -1;
224 /* end-sanitize-cygnus */
225 /* start-sanitize-r5900 */
226 /* Whether Toshiba r5900 instructions are permitted. */
227 static int mips_5900
= -1;
229 /* end-sanitize-r5900 */
230 /* Whether Toshiba r3900 instructions are permitted. */
231 static int mips_3900
= -1;
233 /* start-sanitize-tx49 */
234 /* Whether Toshiba r4900 instructions are permitted. */
235 static int mips_4900
= -1;
237 /* end-sanitize-tx49 */
238 /* start-sanitize-tx19 */
239 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
240 The tx19 related options and configuration bits are handled by
242 /* end-sanitize-tx19 */
244 /* Whether the processor uses hardware interlocks to protect
245 reads from the HI and LO registers, and thus does not
246 require nops to be inserted.
248 FIXME: We really should not be checking mips_cpu here. The -mcpu=
249 option is documented to not do anything special. In gcc, the
250 -mcpu= option only affects scheduling, and does not affect code
251 generation. Each test of -mcpu= here should actually be testing a
252 specific variable, such as mips_4010, and each such variable should
253 have a command line option to set it. The -mcpu= option may be
254 used to set the default value of these options, as is the case for
257 #define hilo_interlocks (mips_4010 \
258 /* start-sanitize-tx49 */ \
259 || mips_cpu == 4900 || mips_4900 \
260 /* end-sanitize-tx49 */ \
261 /* start-sanitize-vr4320 */ \
262 || mips_cpu == 4320 \
263 /* end-sanitize-vr4320 */ \
264 /* start-sanitize-r5900 */ \
266 /* end-sanitize-r5900 */ \
269 /* Whether the processor uses hardware interlocks to protect reads
270 from the GPRs, and thus does not require nops to be inserted. */
271 #define gpr_interlocks \
272 (mips_opts.isa >= 2 \
273 /* start-sanitize-cygnus */ \
275 /* end-sanitize-cygnus */ \
276 /* start-sanitize-r5900 */ \
278 /* end-sanitize-r5900 */ \
281 /* As with other "interlocks" this is used by hardware that has FP
282 (co-processor) interlocks. */
283 /* Itbl support may require additional care here. */
284 #define cop_interlocks (mips_cpu == 4300 \
285 /* start-sanitize-vr4320 */ \
286 || mips_cpu == 4320 \
287 /* end-sanitize-vr4320 */ \
288 /* start-sanitize-cygnus */ \
289 || mips_cpu == 5400 \
290 /* end-sanitize-cygnus */ \
293 /* MIPS PIC level. */
297 /* Do not generate PIC code. */
300 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
301 not sure what it is supposed to do. */
304 /* Generate PIC code as in the SVR4 MIPS ABI. */
307 /* Generate PIC code without using a global offset table: the data
308 segment has a maximum size of 64K, all data references are off
309 the $gp register, and all text references are PC relative. This
310 is used on some embedded systems. */
314 static enum mips_pic_level mips_pic
;
316 /* 1 if we should generate 32 bit offsets from the GP register in
317 SVR4_PIC mode. Currently has no meaning in other modes. */
318 static int mips_big_got
;
320 /* 1 if trap instructions should used for overflow rather than break
322 static int mips_trap
;
324 /* Non-zero if any .set noreorder directives were used. */
326 static int mips_any_noreorder
;
328 /* The size of the small data section. */
329 static int g_switch_value
= 8;
330 /* Whether the -G option was used. */
331 static int g_switch_seen
= 0;
336 /* If we can determine in advance that GP optimization won't be
337 possible, we can skip the relaxation stuff that tries to produce
338 GP-relative references. This makes delay slot optimization work
341 This function can only provide a guess, but it seems to work for
342 gcc output. If it guesses wrong, the only loss should be in
343 efficiency; it shouldn't introduce any bugs.
345 I don't know if a fix is needed for the SVR4_PIC mode. I've only
346 fixed it for the non-PIC mode. KR 95/04/07 */
347 static int nopic_need_relax
PARAMS ((symbolS
*, int));
349 /* handle of the OPCODE hash table */
350 static struct hash_control
*op_hash
= NULL
;
352 /* The opcode hash table we use for the mips16. */
353 static struct hash_control
*mips16_op_hash
= NULL
;
355 /* This array holds the chars that always start a comment. If the
356 pre-processor is disabled, these aren't very useful */
357 const char comment_chars
[] = "#";
359 /* This array holds the chars that only start a comment at the beginning of
360 a line. If the line seems to have the form '# 123 filename'
361 .line and .file directives will appear in the pre-processed output */
362 /* Note that input_file.c hand checks for '#' at the beginning of the
363 first line of the input file. This is because the compiler outputs
364 #NO_APP at the beginning of its output. */
365 /* Also note that C style comments are always supported. */
366 const char line_comment_chars
[] = "#";
368 /* This array holds machine specific line separator characters. */
369 const char line_separator_chars
[] = "";
371 /* Chars that can be used to separate mant from exp in floating point nums */
372 const char EXP_CHARS
[] = "eE";
374 /* Chars that mean this number is a floating point constant */
377 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
379 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
380 changed in read.c . Ideally it shouldn't have to know about it at all,
381 but nothing is ideal around here.
384 static char *insn_error
;
386 static int auto_align
= 1;
388 /* When outputting SVR4 PIC code, the assembler needs to know the
389 offset in the stack frame from which to restore the $gp register.
390 This is set by the .cprestore pseudo-op, and saved in this
392 static offsetT mips_cprestore_offset
= -1;
394 /* This is the register which holds the stack frame, as set by the
395 .frame pseudo-op. This is needed to implement .cprestore. */
396 static int mips_frame_reg
= SP
;
398 /* To output NOP instructions correctly, we need to keep information
399 about the previous two instructions. */
401 /* Whether we are optimizing. The default value of 2 means to remove
402 unneeded NOPs and swap branch instructions when possible. A value
403 of 1 means to not swap branches. A value of 0 means to always
405 static int mips_optimize
= 2;
407 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
408 equivalent to seeing no -g option at all. */
409 static int mips_debug
= 0;
411 /* The previous instruction. */
412 static struct mips_cl_insn prev_insn
;
414 /* The instruction before prev_insn. */
415 static struct mips_cl_insn prev_prev_insn
;
417 /* If we don't want information for prev_insn or prev_prev_insn, we
418 point the insn_mo field at this dummy integer. */
419 static const struct mips_opcode dummy_opcode
= { 0 };
421 /* Non-zero if prev_insn is valid. */
422 static int prev_insn_valid
;
424 /* The frag for the previous instruction. */
425 static struct frag
*prev_insn_frag
;
427 /* The offset into prev_insn_frag for the previous instruction. */
428 static long prev_insn_where
;
430 /* The reloc type for the previous instruction, if any. */
431 static bfd_reloc_code_real_type prev_insn_reloc_type
;
433 /* The reloc for the previous instruction, if any. */
434 static fixS
*prev_insn_fixp
;
436 /* Non-zero if the previous instruction was in a delay slot. */
437 static int prev_insn_is_delay_slot
;
439 /* Non-zero if the previous instruction was in a .set noreorder. */
440 static int prev_insn_unreordered
;
442 /* Non-zero if the previous instruction uses an extend opcode (if
444 static int prev_insn_extended
;
446 /* Non-zero if the previous previous instruction was in a .set
448 static int prev_prev_insn_unreordered
;
450 /* start-sanitize-branchbug4011 */
451 /* Non-zero if the previous insn had one or more labels */
452 static int prev_insn_labels
;
454 /* end-sanitize-branchbug4011 */
455 /* If this is set, it points to a frag holding nop instructions which
456 were inserted before the start of a noreorder section. If those
457 nops turn out to be unnecessary, the size of the frag can be
459 static fragS
*prev_nop_frag
;
461 /* The number of nop instructions we created in prev_nop_frag. */
462 static int prev_nop_frag_holds
;
464 /* The number of nop instructions that we know we need in
466 static int prev_nop_frag_required
;
468 /* The number of instructions we've seen since prev_nop_frag. */
469 static int prev_nop_frag_since
;
471 /* For ECOFF and ELF, relocations against symbols are done in two
472 parts, with a HI relocation and a LO relocation. Each relocation
473 has only 16 bits of space to store an addend. This means that in
474 order for the linker to handle carries correctly, it must be able
475 to locate both the HI and the LO relocation. This means that the
476 relocations must appear in order in the relocation table.
478 In order to implement this, we keep track of each unmatched HI
479 relocation. We then sort them so that they immediately precede the
480 corresponding LO relocation. */
485 struct mips_hi_fixup
*next
;
488 /* The section this fixup is in. */
492 /* The list of unmatched HI relocs. */
494 static struct mips_hi_fixup
*mips_hi_fixup_list
;
496 /* Map normal MIPS register numbers to mips16 register numbers. */
498 #define X ILLEGAL_REG
499 static const int mips32_to_16_reg_map
[] =
501 X
, X
, 2, 3, 4, 5, 6, 7,
502 X
, X
, X
, X
, X
, X
, X
, X
,
503 0, 1, X
, X
, X
, X
, X
, X
,
504 X
, X
, X
, X
, X
, X
, X
, X
508 /* Map mips16 register numbers to normal MIPS register numbers. */
510 static const int mips16_to_32_reg_map
[] =
512 16, 17, 2, 3, 4, 5, 6, 7
515 /* Since the MIPS does not have multiple forms of PC relative
516 instructions, we do not have to do relaxing as is done on other
517 platforms. However, we do have to handle GP relative addressing
518 correctly, which turns out to be a similar problem.
520 Every macro that refers to a symbol can occur in (at least) two
521 forms, one with GP relative addressing and one without. For
522 example, loading a global variable into a register generally uses
523 a macro instruction like this:
525 If i can be addressed off the GP register (this is true if it is in
526 the .sbss or .sdata section, or if it is known to be smaller than
527 the -G argument) this will generate the following instruction:
529 This instruction will use a GPREL reloc. If i can not be addressed
530 off the GP register, the following instruction sequence will be used:
533 In this case the first instruction will have a HI16 reloc, and the
534 second reloc will have a LO16 reloc. Both relocs will be against
537 The issue here is that we may not know whether i is GP addressable
538 until after we see the instruction that uses it. Therefore, we
539 want to be able to choose the final instruction sequence only at
540 the end of the assembly. This is similar to the way other
541 platforms choose the size of a PC relative instruction only at the
544 When generating position independent code we do not use GP
545 addressing in quite the same way, but the issue still arises as
546 external symbols and local symbols must be handled differently.
548 We handle these issues by actually generating both possible
549 instruction sequences. The longer one is put in a frag_var with
550 type rs_machine_dependent. We encode what to do with the frag in
551 the subtype field. We encode (1) the number of existing bytes to
552 replace, (2) the number of new bytes to use, (3) the offset from
553 the start of the existing bytes to the first reloc we must generate
554 (that is, the offset is applied from the start of the existing
555 bytes after they are replaced by the new bytes, if any), (4) the
556 offset from the start of the existing bytes to the second reloc,
557 (5) whether a third reloc is needed (the third reloc is always four
558 bytes after the second reloc), and (6) whether to warn if this
559 variant is used (this is sometimes needed if .set nomacro or .set
560 noat is in effect). All these numbers are reasonably small.
562 Generating two instruction sequences must be handled carefully to
563 ensure that delay slots are handled correctly. Fortunately, there
564 are a limited number of cases. When the second instruction
565 sequence is generated, append_insn is directed to maintain the
566 existing delay slot information, so it continues to apply to any
567 code after the second instruction sequence. This means that the
568 second instruction sequence must not impose any requirements not
569 required by the first instruction sequence.
571 These variant frags are then handled in functions called by the
572 machine independent code. md_estimate_size_before_relax returns
573 the final size of the frag. md_convert_frag sets up the final form
574 of the frag. tc_gen_reloc adjust the first reloc and adds a second
576 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
580 | (((reloc1) + 64) << 9) \
581 | (((reloc2) + 64) << 2) \
582 | ((reloc3) ? (1 << 1) : 0) \
584 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
585 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
586 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
587 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
588 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
589 #define RELAX_WARN(i) ((i) & 1)
591 /* For mips16 code, we use an entirely different form of relaxation.
592 mips16 supports two versions of most instructions which take
593 immediate values: a small one which takes some small value, and a
594 larger one which takes a 16 bit value. Since branches also follow
595 this pattern, relaxing these values is required.
597 We can assemble both mips16 and normal MIPS code in a single
598 object. Therefore, we need to support this type of relaxation at
599 the same time that we support the relaxation described above. We
600 use the high bit of the subtype field to distinguish these cases.
602 The information we store for this type of relaxation is the
603 argument code found in the opcode file for this relocation, whether
604 the user explicitly requested a small or extended form, and whether
605 the relocation is in a jump or jal delay slot. That tells us the
606 size of the value, and how it should be stored. We also store
607 whether the fragment is considered to be extended or not. We also
608 store whether this is known to be a branch to a different section,
609 whether we have tried to relax this frag yet, and whether we have
610 ever extended a PC relative fragment because of a shift count. */
611 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
614 | ((small) ? 0x100 : 0) \
615 | ((ext) ? 0x200 : 0) \
616 | ((dslot) ? 0x400 : 0) \
617 | ((jal_dslot) ? 0x800 : 0))
618 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
619 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
620 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
621 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
622 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
623 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
624 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
625 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
626 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
627 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
628 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
629 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
630 /* start-sanitize-branchbug4011 */
631 /* The 4011 core has a bug in it's branch processing that
632 an be avoided if branches never branches (where branches
633 are defined as those starting with 'b'). We do this here
634 by insuring that labels are not directly on branch instructions,
635 and if they are inserting a no-op between the label and the
637 static int mips_fix_4011_branch_bug
= 0;
638 /* end-sanitize-branchbug4011 */
640 /* Prototypes for static functions. */
643 #define internalError() \
644 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
646 #define internalError() as_fatal (_("MIPS internal Error"));
649 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
651 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
652 unsigned int reg
, enum mips_regclass
class));
653 static int reg_needs_delay
PARAMS ((int));
654 static void mips16_mark_labels
PARAMS ((void));
655 static void append_insn
PARAMS ((char *place
,
656 struct mips_cl_insn
* ip
,
658 bfd_reloc_code_real_type r
,
660 static void mips_no_prev_insn
PARAMS ((int));
661 static void mips_emit_delays
PARAMS ((boolean
));
663 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
664 const char *name
, const char *fmt
,
667 static void macro_build ();
669 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
670 const char *, const char *,
672 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
673 expressionS
* ep
, int regnum
));
674 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
675 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
677 static void load_register
PARAMS ((int *, int, expressionS
*, int));
678 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
679 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
680 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
681 #ifdef LOSING_COMPILER
682 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
684 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
685 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
686 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
687 boolean
, boolean
, unsigned long *,
688 boolean
*, unsigned short *));
689 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
690 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
691 static symbolS
*get_symbol
PARAMS ((void));
692 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
693 static void s_align
PARAMS ((int));
694 static void s_change_sec
PARAMS ((int));
695 static void s_cons
PARAMS ((int));
696 static void s_float_cons
PARAMS ((int));
697 static void s_mips_globl
PARAMS ((int));
698 static void s_option
PARAMS ((int));
699 static void s_mipsset
PARAMS ((int));
700 static void s_abicalls
PARAMS ((int));
701 static void s_cpload
PARAMS ((int));
702 static void s_cprestore
PARAMS ((int));
703 static void s_gpword
PARAMS ((int));
704 static void s_cpadd
PARAMS ((int));
705 static void s_insn
PARAMS ((int));
706 static void md_obj_begin
PARAMS ((void));
707 static void md_obj_end
PARAMS ((void));
708 static long get_number
PARAMS ((void));
709 static void s_mips_ent
PARAMS ((int));
710 static void s_mips_end
PARAMS ((int));
711 static void s_mips_frame
PARAMS ((int));
712 static void s_mips_mask
PARAMS ((int));
713 static void s_mips_stab
PARAMS ((int));
714 static void s_mips_weakext
PARAMS ((int));
715 static void s_file
PARAMS ((int));
716 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
719 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
723 The following pseudo-ops from the Kane and Heinrich MIPS book
724 should be defined here, but are currently unsupported: .alias,
725 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
727 The following pseudo-ops from the Kane and Heinrich MIPS book are
728 specific to the type of debugging information being generated, and
729 should be defined by the object format: .aent, .begin, .bend,
730 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
733 The following pseudo-ops from the Kane and Heinrich MIPS book are
734 not MIPS CPU specific, but are also not specific to the object file
735 format. This file is probably the best place to define them, but
736 they are not currently supported: .asm0, .endr, .lab, .repeat,
739 static const pseudo_typeS mips_pseudo_table
[] =
741 /* MIPS specific pseudo-ops. */
742 {"option", s_option
, 0},
743 {"set", s_mipsset
, 0},
744 {"rdata", s_change_sec
, 'r'},
745 {"sdata", s_change_sec
, 's'},
746 {"livereg", s_ignore
, 0},
747 {"abicalls", s_abicalls
, 0},
748 {"cpload", s_cpload
, 0},
749 {"cprestore", s_cprestore
, 0},
750 {"gpword", s_gpword
, 0},
751 {"cpadd", s_cpadd
, 0},
754 /* Relatively generic pseudo-ops that happen to be used on MIPS
756 {"asciiz", stringer
, 1},
757 {"bss", s_change_sec
, 'b'},
760 {"dword", s_cons
, 3},
761 {"weakext", s_mips_weakext
, 0},
763 /* These pseudo-ops are defined in read.c, but must be overridden
764 here for one reason or another. */
765 {"align", s_align
, 0},
767 {"data", s_change_sec
, 'd'},
768 {"double", s_float_cons
, 'd'},
769 {"float", s_float_cons
, 'f'},
770 {"globl", s_mips_globl
, 0},
771 {"global", s_mips_globl
, 0},
772 {"hword", s_cons
, 1},
777 {"short", s_cons
, 1},
778 {"single", s_float_cons
, 'f'},
779 {"stabn", s_mips_stab
, 'n'},
780 {"text", s_change_sec
, 't'},
785 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
786 /* These pseudo-ops should be defined by the object file format.
787 However, a.out doesn't support them, so we have versions here. */
788 {"aent", s_mips_ent
, 1},
789 {"bgnb", s_ignore
, 0},
790 {"end", s_mips_end
, 0},
791 {"endb", s_ignore
, 0},
792 {"ent", s_mips_ent
, 0},
794 {"fmask", s_mips_mask
, 'F'},
795 {"frame", s_mips_frame
, 0},
796 {"loc", s_ignore
, 0},
797 {"mask", s_mips_mask
, 'R'},
798 {"verstamp", s_ignore
, 0},
802 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
807 pop_insert (mips_pseudo_table
);
808 if (! ECOFF_DEBUGGING
)
809 pop_insert (mips_nonecoff_pseudo_table
);
812 /* Symbols labelling the current insn. */
814 struct insn_label_list
816 struct insn_label_list
*next
;
820 static struct insn_label_list
*insn_labels
;
821 static struct insn_label_list
*free_insn_labels
;
823 static void mips_clear_insn_labels
PARAMS ((void));
826 mips_clear_insn_labels ()
828 register struct insn_label_list
**pl
;
830 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
836 static char *expr_end
;
838 /* Expressions which appear in instructions. These are set by
841 static expressionS imm_expr
;
842 static expressionS offset_expr
;
844 /* Relocs associated with imm_expr and offset_expr. */
846 static bfd_reloc_code_real_type imm_reloc
;
847 static bfd_reloc_code_real_type offset_reloc
;
849 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
851 static boolean imm_unmatched_hi
;
853 /* These are set by mips16_ip if an explicit extension is used. */
855 static boolean mips16_small
, mips16_ext
;
857 #ifdef MIPS_STABS_ELF
858 /* The pdr segment for per procedure frame/regmask info */
864 * This function is called once, at assembler startup time. It should
865 * set up all the tables, etc. that the MD part of the assembler will need.
871 register const char *retval
= NULL
;
872 register unsigned int i
= 0;
878 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
880 a
= xmalloc (sizeof TARGET_CPU
);
881 strcpy (a
, TARGET_CPU
);
882 a
[(sizeof TARGET_CPU
) - 3] = '\0';
888 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
889 just the generic 'mips', in which case set mips_cpu based
890 on the given ISA, if any. */
892 if (strcmp (cpu
, "mips") == 0)
894 if (mips_opts
.isa
< 0)
897 else if (mips_opts
.isa
== 2)
900 else if (mips_opts
.isa
== 3)
903 else if (mips_opts
.isa
== 4)
910 else if (strcmp (cpu
, "r3900") == 0
911 || strcmp (cpu
, "mipstx39") == 0
912 /* start-sanitize-tx19 */
913 || strcmp (cpu
, "r1900") == 0
914 || strcmp (cpu
, "mipstx19") == 0
915 /* end-sanitize-tx19 */
919 else if (strcmp (cpu
, "r6000") == 0
920 || strcmp (cpu
, "mips2") == 0)
923 else if (strcmp (cpu
, "mips64") == 0
924 || strcmp (cpu
, "r4000") == 0
925 || strcmp (cpu
, "mips3") == 0)
928 else if (strcmp (cpu
, "r4400") == 0)
931 else if (strcmp (cpu
, "mips64orion") == 0
932 || strcmp (cpu
, "r4600") == 0)
935 else if (strcmp (cpu
, "r4650") == 0)
938 else if (strcmp (cpu
, "mips64vr4300") == 0)
941 /* start-sanitize-vr4xxx */
942 else if (strcmp (cpu
, "mips64vr4xxx") == 0)
945 /* end-sanitize-vr4xxx */
946 /* start-sanitize-vr4320 */
947 else if (strcmp (cpu
, "r4320") == 0
948 || strcmp (cpu
, "mips64vr4320") == 0)
951 /* end-sanitize-vr4320 */
952 else if (strcmp (cpu
, "mips64vr4100") == 0)
955 /* start-sanitize-vr4xxx */
956 else if (strcmp (cpu
, "vr4121") == 0
957 || strcmp (cpu
, "mips64vr4121") == 0)
960 /* end-sanitize-vr4xxx */
961 else if (strcmp (cpu
, "r4010") == 0)
964 /* start-sanitize-tx49 */
965 else if (strcmp (cpu
, "mips64tx49") == 0)
967 /* end-sanitize-tx49 */
969 else if (strcmp (cpu
, "r5000") == 0
970 || strcmp (cpu
, "mips64vr5000") == 0)
973 /* start-sanitize-cygnus */
974 else if (strcmp (cpu
, "r5400") == 0
975 || strcmp (cpu
, "mips64vr5400") == 0)
977 /* end-sanitize-cygnus */
979 /* start-sanitize-r5900 */
980 else if (strcmp (cpu
, "r5900") == 0
981 || strcmp (cpu
, "mips64r5900") == 0)
983 /* end-sanitize-r5900 */
985 else if (strcmp (cpu
, "r8000") == 0
986 || strcmp (cpu
, "mips4") == 0)
989 else if (strcmp (cpu
, "r10000") == 0)
992 else if (strcmp (cpu
, "mips16") == 0)
993 mips_cpu
= 0; /* FIXME */
999 if (mips_opts
.isa
== -1)
1001 if (mips_cpu
== 3000
1002 || mips_cpu
== 3900)
1005 else if (mips_cpu
== 6000
1006 || mips_cpu
== 4010)
1009 else if (mips_cpu
== 4000
1011 /* start-sanitize-vr4xxx */
1013 /* end-sanitize-vr4xxx */
1016 /* start-sanitize-vr4320 */
1018 /* end-sanitize-vr4320 */
1020 /* start-sanitize-tx49 */
1022 /* end-sanitize-tx49 */
1023 /* start-sanitize-r5900 */
1025 /* end-sanitize-r5900 */
1026 || mips_cpu
== 4650)
1029 else if (mips_cpu
== 5000
1030 /* start-sanitize-cygnus */
1032 /* end-sanitize-cygnus */
1034 || mips_cpu
== 10000)
1041 if (mips_opts
.mips16
< 0)
1043 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
1044 mips_opts
.mips16
= 1;
1046 mips_opts
.mips16
= 0;
1050 mips_4650
= (mips_cpu
== 4650);
1053 mips_4010
= (mips_cpu
== 4010);
1056 mips_4100
= (mips_cpu
== 4100);
1058 /* start-sanitize-vr4xxx */
1060 mips_4121
= (mips_cpu
== 4121);
1062 /* end-sanitize-vr4xxx */
1063 /* start-sanitize-vr4320 */
1065 mips_4320
= (mips_cpu
== 4320);
1067 /* end-sanitize-vr4320 */
1068 /* start-sanitize-cygnus */
1070 mips_5400
= (mips_cpu
== 5400);
1071 /* end-sanitize-cygnus */
1073 /* start-sanitize-r5900 */
1075 mips_5900
= (mips_cpu
== 5900);
1076 /* end-sanitize-r5900 */
1079 mips_3900
= (mips_cpu
== 3900);
1081 /* start-sanitize-tx49 */
1083 mips_4900
= (mips_cpu
== 4900);
1085 /* end-sanitize-tx49 */
1087 /* End of TARGET_CPU processing, get rid of malloced memory
1096 if (mips_opts
.isa
< 2 && mips_trap
)
1097 as_bad (_("trap exception not supported at ISA 1"));
1099 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1101 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1105 switch (mips_opts
.isa
)
1108 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1111 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1114 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1117 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1123 as_warn (_("Could not set architecture and machine"));
1125 file_mips_isa
= mips_opts
.isa
;
1127 op_hash
= hash_new ();
1129 for (i
= 0; i
< NUMOPCODES
;)
1131 const char *name
= mips_opcodes
[i
].name
;
1133 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1136 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1137 mips_opcodes
[i
].name
, retval
);
1138 /* Probably a memory allocation problem? Give up now. */
1139 as_fatal (_("Broken assembler. No assembly attempted."));
1143 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1145 if (!validate_mips_insn (&mips_opcodes
[i
]))
1150 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1153 mips16_op_hash
= hash_new ();
1156 while (i
< bfd_mips16_num_opcodes
)
1158 const char *name
= mips16_opcodes
[i
].name
;
1160 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1162 as_fatal (_("internal: can't hash `%s': %s"),
1163 mips16_opcodes
[i
].name
, retval
);
1166 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1167 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1168 != mips16_opcodes
[i
].match
))
1170 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1171 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1176 while (i
< bfd_mips16_num_opcodes
1177 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1181 as_fatal (_("Broken assembler. No assembly attempted."));
1183 /* We add all the general register names to the symbol table. This
1184 helps us detect invalid uses of them. */
1185 for (i
= 0; i
< 32; i
++)
1189 sprintf (buf
, "$%d", i
);
1190 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1191 &zero_address_frag
));
1193 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1194 &zero_address_frag
));
1195 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1196 &zero_address_frag
));
1197 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1198 &zero_address_frag
));
1199 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1200 &zero_address_frag
));
1201 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1202 &zero_address_frag
));
1203 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1204 &zero_address_frag
));
1205 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1206 &zero_address_frag
));
1208 mips_no_prev_insn (false);
1211 mips_cprmask
[0] = 0;
1212 mips_cprmask
[1] = 0;
1213 mips_cprmask
[2] = 0;
1214 mips_cprmask
[3] = 0;
1216 /* set the default alignment for the text section (2**2) */
1217 record_alignment (text_section
, 2);
1219 if (USE_GLOBAL_POINTER_OPT
)
1220 bfd_set_gp_size (stdoutput
, g_switch_value
);
1222 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1224 /* On a native system, sections must be aligned to 16 byte
1225 boundaries. When configured for an embedded ELF target, we
1227 if (strcmp (TARGET_OS
, "elf") != 0)
1229 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1230 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1231 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1234 /* Create a .reginfo section for register masks and a .mdebug
1235 section for debugging information. */
1243 subseg
= now_subseg
;
1245 /* The ABI says this section should be loaded so that the
1246 running program can access it. However, we don't load it
1247 if we are configured for an embedded target */
1248 flags
= SEC_READONLY
| SEC_DATA
;
1249 if (strcmp (TARGET_OS
, "elf") != 0)
1250 flags
|= SEC_ALLOC
| SEC_LOAD
;
1254 sec
= subseg_new (".reginfo", (subsegT
) 0);
1257 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1258 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1261 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1266 /* The 64-bit ABI uses a .MIPS.options section rather than
1267 .reginfo section. */
1268 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1269 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1270 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1273 /* Set up the option header. */
1275 Elf_Internal_Options opthdr
;
1278 opthdr
.kind
= ODK_REGINFO
;
1279 opthdr
.size
= (sizeof (Elf_External_Options
)
1280 + sizeof (Elf64_External_RegInfo
));
1283 f
= frag_more (sizeof (Elf_External_Options
));
1284 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1285 (Elf_External_Options
*) f
);
1287 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1292 if (ECOFF_DEBUGGING
)
1294 sec
= subseg_new (".mdebug", (subsegT
) 0);
1295 (void) bfd_set_section_flags (stdoutput
, sec
,
1296 SEC_HAS_CONTENTS
| SEC_READONLY
);
1297 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1300 #ifdef MIPS_STABS_ELF
1301 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1302 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1303 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1304 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1307 subseg_set (seg
, subseg
);
1311 if (! ECOFF_DEBUGGING
)
1318 if (! ECOFF_DEBUGGING
)
1326 struct mips_cl_insn insn
;
1328 imm_expr
.X_op
= O_absent
;
1329 imm_reloc
= BFD_RELOC_UNUSED
;
1330 imm_unmatched_hi
= false;
1331 offset_expr
.X_op
= O_absent
;
1332 offset_reloc
= BFD_RELOC_UNUSED
;
1334 if (mips_opts
.mips16
)
1335 mips16_ip (str
, &insn
);
1338 mips_ip (str
, &insn
);
1339 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1340 str
, insn
.insn_opcode
));
1345 as_bad ("%s `%s'", insn_error
, str
);
1349 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1351 if (mips_opts
.mips16
)
1352 mips16_macro (&insn
);
1358 if (imm_expr
.X_op
!= O_absent
)
1359 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1361 else if (offset_expr
.X_op
!= O_absent
)
1362 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1364 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1368 /* See whether instruction IP reads register REG. CLASS is the type
1372 insn_uses_reg (ip
, reg
, class)
1373 struct mips_cl_insn
*ip
;
1375 enum mips_regclass
class;
1377 if (class == MIPS16_REG
)
1379 assert (mips_opts
.mips16
);
1380 reg
= mips16_to_32_reg_map
[reg
];
1381 class = MIPS_GR_REG
;
1384 /* Don't report on general register 0, since it never changes. */
1385 if (class == MIPS_GR_REG
&& reg
== 0)
1388 if (class == MIPS_FP_REG
)
1390 assert (! mips_opts
.mips16
);
1391 /* If we are called with either $f0 or $f1, we must check $f0.
1392 This is not optimal, because it will introduce an unnecessary
1393 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1394 need to distinguish reading both $f0 and $f1 or just one of
1395 them. Note that we don't have to check the other way,
1396 because there is no instruction that sets both $f0 and $f1
1397 and requires a delay. */
1398 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1399 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1400 == (reg
&~ (unsigned) 1)))
1402 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1403 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1404 == (reg
&~ (unsigned) 1)))
1407 else if (! mips_opts
.mips16
)
1409 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1410 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1412 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1413 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1418 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1419 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1420 & MIPS16OP_MASK_RX
)]
1423 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1424 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1425 & MIPS16OP_MASK_RY
)]
1428 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1429 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1430 & MIPS16OP_MASK_MOVE32Z
)]
1433 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1435 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1437 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1439 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1440 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1441 & MIPS16OP_MASK_REGR32
) == reg
)
1448 /* This function returns true if modifying a register requires a
1452 reg_needs_delay (reg
)
1455 unsigned long prev_pinfo
;
1457 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1458 if (! mips_opts
.noreorder
1459 && mips_opts
.isa
< 4
1460 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1461 || (! gpr_interlocks
1462 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1464 /* A load from a coprocessor or from memory. All load
1465 delays delay the use of general register rt for one
1466 instruction on the r3000. The r6000 and r4000 use
1468 /* Itbl support may require additional care here. */
1469 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1470 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1477 /* Mark instruction labels in mips16 mode. This permits the linker to
1478 handle them specially, such as generating jalx instructions when
1479 needed. We also make them odd for the duration of the assembly, in
1480 order to generate the right sort of code. We will make them even
1481 in the adjust_symtab routine, while leaving them marked. This is
1482 convenient for the debugger and the disassembler. The linker knows
1483 to make them odd again. */
1486 mips16_mark_labels ()
1488 if (mips_opts
.mips16
)
1490 struct insn_label_list
*l
;
1492 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1495 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1496 S_SET_OTHER (l
->label
, STO_MIPS16
);
1498 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1499 ++l
->label
->sy_value
.X_add_number
;
1504 /* Output an instruction. PLACE is where to put the instruction; if
1505 it is NULL, this uses frag_more to get room. IP is the instruction
1506 information. ADDRESS_EXPR is an operand of the instruction to be
1507 used with RELOC_TYPE. */
1510 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1512 struct mips_cl_insn
*ip
;
1513 expressionS
*address_expr
;
1514 bfd_reloc_code_real_type reloc_type
;
1515 boolean unmatched_hi
;
1517 register unsigned long prev_pinfo
, pinfo
;
1521 /* start-sanitize-branchbug4011 */
1522 int label_nop
= 0; /* True if a no-op needs to appear between
1523 the current insn and the current labels */
1524 /* end-sanitize-branchbug4011 */
1526 /* Mark instruction labels in mips16 mode. */
1527 if (mips_opts
.mips16
)
1528 mips16_mark_labels ();
1530 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1531 pinfo
= ip
->insn_mo
->pinfo
;
1533 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1537 /* If the previous insn required any delay slots, see if we need
1538 to insert a NOP or two. There are eight kinds of possible
1539 hazards, of which an instruction can have at most one type.
1540 (1) a load from memory delay
1541 (2) a load from a coprocessor delay
1542 (3) an unconditional branch delay
1543 (4) a conditional branch delay
1544 (5) a move to coprocessor register delay
1545 (6) a load coprocessor register from memory delay
1546 (7) a coprocessor condition code delay
1547 (8) a HI/LO special register delay
1549 There are a lot of optimizations we could do that we don't.
1550 In particular, we do not, in general, reorder instructions.
1551 If you use gcc with optimization, it will reorder
1552 instructions and generally do much more optimization then we
1553 do here; repeating all that work in the assembler would only
1554 benefit hand written assembly code, and does not seem worth
1557 /* This is how a NOP is emitted. */
1558 #define emit_nop() \
1560 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1561 : md_number_to_chars (frag_more (4), 0, 4))
1563 /* The previous insn might require a delay slot, depending upon
1564 the contents of the current insn. */
1565 if (! mips_opts
.mips16
1566 && mips_opts
.isa
< 4
1567 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1568 && ! cop_interlocks
)
1569 || (! gpr_interlocks
1570 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1572 /* A load from a coprocessor or from memory. All load
1573 delays delay the use of general register rt for one
1574 instruction on the r3000. The r6000 and r4000 use
1576 /* Itbl support may require additional care here. */
1577 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1578 if (mips_optimize
== 0
1579 || insn_uses_reg (ip
,
1580 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1585 else if (! mips_opts
.mips16
1586 && mips_opts
.isa
< 4
1587 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1588 && ! cop_interlocks
)
1589 || (mips_opts
.isa
< 2
1590 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1592 /* A generic coprocessor delay. The previous instruction
1593 modified a coprocessor general or control register. If
1594 it modified a control register, we need to avoid any
1595 coprocessor instruction (this is probably not always
1596 required, but it sometimes is). If it modified a general
1597 register, we avoid using that register.
1599 On the r6000 and r4000 loading a coprocessor register
1600 from memory is interlocked, and does not require a delay.
1602 This case is not handled very well. There is no special
1603 knowledge of CP0 handling, and the coprocessors other
1604 than the floating point unit are not distinguished at
1606 /* Itbl support may require additional care here. FIXME!
1607 Need to modify this to include knowledge about
1608 user specified delays! */
1609 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1611 if (mips_optimize
== 0
1612 || insn_uses_reg (ip
,
1613 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1618 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1620 if (mips_optimize
== 0
1621 || insn_uses_reg (ip
,
1622 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1629 /* We don't know exactly what the previous instruction
1630 does. If the current instruction uses a coprocessor
1631 register, we must insert a NOP. If previous
1632 instruction may set the condition codes, and the
1633 current instruction uses them, we must insert two
1635 /* Itbl support may require additional care here. */
1636 if (mips_optimize
== 0
1637 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1638 && (pinfo
& INSN_READ_COND_CODE
)))
1640 else if (pinfo
& INSN_COP
)
1644 else if (! mips_opts
.mips16
1645 && mips_opts
.isa
< 4
1646 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1647 && ! cop_interlocks
)
1649 /* The previous instruction sets the coprocessor condition
1650 codes, but does not require a general coprocessor delay
1651 (this means it is a floating point comparison
1652 instruction). If this instruction uses the condition
1653 codes, we need to insert a single NOP. */
1654 /* Itbl support may require additional care here. */
1655 if (mips_optimize
== 0
1656 || (pinfo
& INSN_READ_COND_CODE
))
1659 else if (prev_pinfo
& INSN_READ_LO
)
1661 /* The previous instruction reads the LO register; if the
1662 current instruction writes to the LO register, we must
1663 insert two NOPS. Some newer processors have interlocks.
1664 Also the tx39's multiply instructions can be exectuted
1665 immediatly after a read from HI/LO (without the delay),
1666 though the tx39's divide insns still do require the
1668 if (! (hilo_interlocks
1669 || (mips_3900
&& (pinfo
& INSN_MULT
)))
1670 && (mips_optimize
== 0
1671 || (pinfo
& INSN_WRITE_LO
)))
1674 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1676 /* The previous instruction reads the HI register; if the
1677 current instruction writes to the HI register, we must
1678 insert a NOP. Some newer processors have interlocks.
1679 Also the note tx39's multiply above. */
1680 if (! (hilo_interlocks
1681 || (mips_3900
&& (pinfo
& INSN_MULT
)))
1682 && (mips_optimize
== 0
1683 || (pinfo
& INSN_WRITE_HI
)))
1687 /* If the previous instruction was in a noreorder section, then
1688 we don't want to insert the nop after all. */
1689 /* Itbl support may require additional care here. */
1690 if (prev_insn_unreordered
)
1693 /* There are two cases which require two intervening
1694 instructions: 1) setting the condition codes using a move to
1695 coprocessor instruction which requires a general coprocessor
1696 delay and then reading the condition codes 2) reading the HI
1697 or LO register and then writing to it (except on processors
1698 which have interlocks). If we are not already emitting a NOP
1699 instruction, we must check for these cases compared to the
1700 instruction previous to the previous instruction. */
1701 if ((! mips_opts
.mips16
1702 && mips_opts
.isa
< 4
1703 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1704 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1705 && (pinfo
& INSN_READ_COND_CODE
)
1706 && ! cop_interlocks
)
1707 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1708 && (pinfo
& INSN_WRITE_LO
)
1709 && ! (hilo_interlocks
1710 || (mips_3900
&& (pinfo
& INSN_MULT
))))
1711 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1712 && (pinfo
& INSN_WRITE_HI
)
1713 && ! (hilo_interlocks
1714 || (mips_3900
&& (pinfo
& INSN_MULT
)))))
1719 if (prev_prev_insn_unreordered
)
1722 if (prev_prev_nop
&& nops
== 0)
1725 /* If we are being given a nop instruction, don't bother with
1726 one of the nops we would otherwise output. This will only
1727 happen when a nop instruction is used with mips_optimize set
1730 && ! mips_opts
.noreorder
1731 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1734 /* start-sanitize-branchbug4011 */
1735 /* If we have a label on a branch insn, we need at least one no-op
1736 between the label and the branch. The pinfo flags in this test
1737 must cover all the kinds of branches. */
1738 if (mips_fix_4011_branch_bug
1739 && insn_labels
!= NULL
1740 && (ip
->insn_mo
->pinfo
1741 & (INSN_UNCOND_BRANCH_DELAY
1742 |INSN_COND_BRANCH_DELAY
1743 |INSN_COND_BRANCH_LIKELY
)))
1747 /* Make sure we've got at least one nop. */
1752 /* end-sanitize-branchbug4011 */
1753 /* Now emit the right number of NOP instructions. */
1754 if (nops
> 0 && ! mips_opts
.noreorder
)
1757 unsigned long old_frag_offset
;
1759 struct insn_label_list
*l
;
1761 old_frag
= frag_now
;
1762 old_frag_offset
= frag_now_fix ();
1764 /* start-sanitize-branchbug4011 */
1765 /* Emit the nops that should be before the label. */
1769 /* end-sanitize-branchbug4011 */
1770 for (i
= 0; i
< nops
; i
++)
1775 listing_prev_line ();
1776 /* We may be at the start of a variant frag. In case we
1777 are, make sure there is enough space for the frag
1778 after the frags created by listing_prev_line. The
1779 argument to frag_grow here must be at least as large
1780 as the argument to all other calls to frag_grow in
1781 this file. We don't have to worry about being in the
1782 middle of a variant frag, because the variants insert
1783 all needed nop instructions themselves. */
1787 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1789 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1790 l
->label
->sy_frag
= frag_now
;
1791 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1792 /* mips16 text labels are stored as odd. */
1793 if (mips_opts
.mips16
)
1794 ++l
->label
->sy_value
.X_add_number
;
1797 #ifndef NO_ECOFF_DEBUGGING
1798 if (ECOFF_DEBUGGING
)
1799 ecoff_fix_loc (old_frag
, old_frag_offset
);
1801 /* start-sanitize-branchbug4011 */
1804 /* Emit the nop after the label, and return the
1805 nop count to it's proper value. */
1809 /* end-sanitize-branchbug4011 */
1811 else if (prev_nop_frag
!= NULL
)
1813 /* We have a frag holding nops we may be able to remove. If
1814 we don't need any nops, we can decrease the size of
1815 prev_nop_frag by the size of one instruction. If we do
1816 need some nops, we count them in prev_nops_required. */
1817 if (prev_nop_frag_since
== 0)
1821 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1822 --prev_nop_frag_holds
;
1825 prev_nop_frag_required
+= nops
;
1829 if (prev_prev_nop
== 0)
1831 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1832 --prev_nop_frag_holds
;
1835 ++prev_nop_frag_required
;
1838 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1839 prev_nop_frag
= NULL
;
1841 ++prev_nop_frag_since
;
1843 /* Sanity check: by the time we reach the second instruction
1844 after prev_nop_frag, we should have used up all the nops
1845 one way or another. */
1846 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1850 if (reloc_type
> BFD_RELOC_UNUSED
)
1852 /* We need to set up a variant frag. */
1853 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1854 f
= frag_var (rs_machine_dependent
, 4, 0,
1855 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1856 mips16_small
, mips16_ext
,
1858 & INSN_UNCOND_BRANCH_DELAY
),
1859 (prev_insn_reloc_type
1860 == BFD_RELOC_MIPS16_JMP
)),
1861 make_expr_symbol (address_expr
), (offsetT
) 0,
1864 else if (place
!= NULL
)
1866 else if (mips_opts
.mips16
1868 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1870 /* Make sure there is enough room to swap this instruction with
1871 a following jump instruction. */
1877 if (mips_opts
.mips16
1878 && mips_opts
.noreorder
1879 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1880 as_warn (_("extended instruction in delay slot"));
1886 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1888 if (address_expr
->X_op
== O_constant
)
1893 ip
->insn_opcode
|= address_expr
->X_add_number
;
1896 case BFD_RELOC_LO16
:
1897 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1900 case BFD_RELOC_MIPS_JMP
:
1901 if ((address_expr
->X_add_number
& 3) != 0)
1902 as_bad (_("jump to misaligned address (0x%lx)"),
1903 (unsigned long) address_expr
->X_add_number
);
1904 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1907 case BFD_RELOC_MIPS16_JMP
:
1908 if ((address_expr
->X_add_number
& 3) != 0)
1909 as_bad (_("jump to misaligned address (0x%lx)"),
1910 (unsigned long) address_expr
->X_add_number
);
1912 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1913 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1914 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1917 /* start-sanitize-r5900 */
1918 case BFD_RELOC_MIPS15_S3
:
1919 ip
->insn_opcode
|= ((imm_expr
.X_add_number
& 0x7fff) >> 3) << 6;
1921 /* end-sanitize-r5900 */
1923 case BFD_RELOC_16_PCREL_S2
:
1933 /* Don't generate a reloc if we are writing into a variant
1937 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1939 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1943 struct mips_hi_fixup
*hi_fixup
;
1945 assert (reloc_type
== BFD_RELOC_HI16_S
);
1946 hi_fixup
= ((struct mips_hi_fixup
*)
1947 xmalloc (sizeof (struct mips_hi_fixup
)));
1948 hi_fixup
->fixp
= fixp
;
1949 hi_fixup
->seg
= now_seg
;
1950 hi_fixup
->next
= mips_hi_fixup_list
;
1951 mips_hi_fixup_list
= hi_fixup
;
1957 if (! mips_opts
.mips16
)
1958 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1959 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1961 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1962 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1968 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1971 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1974 /* Update the register mask information. */
1975 if (! mips_opts
.mips16
)
1977 if (pinfo
& INSN_WRITE_GPR_D
)
1978 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1979 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1980 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1981 if (pinfo
& INSN_READ_GPR_S
)
1982 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1983 if (pinfo
& INSN_WRITE_GPR_31
)
1984 mips_gprmask
|= 1 << 31;
1985 if (pinfo
& INSN_WRITE_FPR_D
)
1986 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1987 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1988 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1989 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1990 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1991 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1992 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1993 if (pinfo
& INSN_COP
)
1995 /* We don't keep enough information to sort these cases out.
1996 The itbl support does keep this information however, although
1997 we currently don't support itbl fprmats as part of the cop
1998 instruction. May want to add this support in the future. */
2000 /* Never set the bit for $0, which is always zero. */
2001 mips_gprmask
&=~ 1 << 0;
2005 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2006 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2007 & MIPS16OP_MASK_RX
);
2008 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2009 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2010 & MIPS16OP_MASK_RY
);
2011 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2012 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2013 & MIPS16OP_MASK_RZ
);
2014 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2015 mips_gprmask
|= 1 << TREG
;
2016 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2017 mips_gprmask
|= 1 << SP
;
2018 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2019 mips_gprmask
|= 1 << RA
;
2020 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2021 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2022 if (pinfo
& MIPS16_INSN_READ_Z
)
2023 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2024 & MIPS16OP_MASK_MOVE32Z
);
2025 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2026 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2027 & MIPS16OP_MASK_REGR32
);
2030 if (place
== NULL
&& ! mips_opts
.noreorder
)
2032 /* Filling the branch delay slot is more complex. We try to
2033 switch the branch with the previous instruction, which we can
2034 do if the previous instruction does not set up a condition
2035 that the branch tests and if the branch is not itself the
2036 target of any branch. */
2037 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2038 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2040 if (mips_optimize
< 2
2041 /* If we have seen .set volatile or .set nomove, don't
2043 || mips_opts
.nomove
!= 0
2044 /* If we had to emit any NOP instructions, then we
2045 already know we can not swap. */
2047 /* If we don't even know the previous insn, we can not
2049 || ! prev_insn_valid
2050 /* If the previous insn is already in a branch delay
2051 slot, then we can not swap. */
2052 || prev_insn_is_delay_slot
2053 /* start-sanitize-branchbug4011 */
2054 /* We can't swap the branch back to a previous label */
2055 || (mips_fix_4011_branch_bug
&& prev_insn_labels
)
2056 /* end-sanitize-branchbug4011 */
2057 /* If the previous previous insn was in a .set
2058 noreorder, we can't swap. Actually, the MIPS
2059 assembler will swap in this situation. However, gcc
2060 configured -with-gnu-as will generate code like
2066 in which we can not swap the bne and INSN. If gcc is
2067 not configured -with-gnu-as, it does not output the
2068 .set pseudo-ops. We don't have to check
2069 prev_insn_unreordered, because prev_insn_valid will
2070 be 0 in that case. We don't want to use
2071 prev_prev_insn_valid, because we do want to be able
2072 to swap at the start of a function. */
2073 || prev_prev_insn_unreordered
2074 /* If the branch is itself the target of a branch, we
2075 can not swap. We cheat on this; all we check for is
2076 whether there is a label on this instruction. If
2077 there are any branches to anything other than a
2078 label, users must use .set noreorder. */
2079 || insn_labels
!= NULL
2080 /* If the previous instruction is in a variant frag, we
2081 can not do the swap. This does not apply to the
2082 mips16, which uses variant frags for different
2084 || (! mips_opts
.mips16
2085 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2086 /* If the branch reads the condition codes, we don't
2087 even try to swap, because in the sequence
2092 we can not swap, and I don't feel like handling that
2094 || (! mips_opts
.mips16
2095 && mips_opts
.isa
< 4
2096 && (pinfo
& INSN_READ_COND_CODE
))
2097 /* We can not swap with an instruction that requires a
2098 delay slot, becase the target of the branch might
2099 interfere with that instruction. */
2100 || (! mips_opts
.mips16
2101 && mips_opts
.isa
< 4
2103 /* Itbl support may require additional care here. */
2104 & (INSN_LOAD_COPROC_DELAY
2105 | INSN_COPROC_MOVE_DELAY
2106 | INSN_WRITE_COND_CODE
)))
2107 || (! (hilo_interlocks
|| (mips_3900
&& (pinfo
& INSN_MULT
)))
2111 || (! mips_opts
.mips16
2113 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2114 || (! mips_opts
.mips16
2115 && mips_opts
.isa
< 2
2116 /* Itbl support may require additional care here. */
2117 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2118 /* We can not swap with a branch instruction. */
2120 & (INSN_UNCOND_BRANCH_DELAY
2121 | INSN_COND_BRANCH_DELAY
2122 | INSN_COND_BRANCH_LIKELY
))
2123 /* We do not swap with a trap instruction, since it
2124 complicates trap handlers to have the trap
2125 instruction be in a delay slot. */
2126 || (prev_pinfo
& INSN_TRAP
)
2127 /* If the branch reads a register that the previous
2128 instruction sets, we can not swap. */
2129 || (! mips_opts
.mips16
2130 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2131 && insn_uses_reg (ip
,
2132 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2135 || (! mips_opts
.mips16
2136 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2137 && insn_uses_reg (ip
,
2138 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2141 || (mips_opts
.mips16
2142 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2143 && insn_uses_reg (ip
,
2144 ((prev_insn
.insn_opcode
2146 & MIPS16OP_MASK_RX
),
2148 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2149 && insn_uses_reg (ip
,
2150 ((prev_insn
.insn_opcode
2152 & MIPS16OP_MASK_RY
),
2154 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2155 && insn_uses_reg (ip
,
2156 ((prev_insn
.insn_opcode
2158 & MIPS16OP_MASK_RZ
),
2160 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2161 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2162 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2163 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2164 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2165 && insn_uses_reg (ip
,
2166 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2169 /* If the branch writes a register that the previous
2170 instruction sets, we can not swap (we know that
2171 branches write only to RD or to $31). */
2172 || (! mips_opts
.mips16
2173 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2174 && (((pinfo
& INSN_WRITE_GPR_D
)
2175 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2176 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2177 || ((pinfo
& INSN_WRITE_GPR_31
)
2178 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2181 || (! mips_opts
.mips16
2182 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2183 && (((pinfo
& INSN_WRITE_GPR_D
)
2184 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2185 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2186 || ((pinfo
& INSN_WRITE_GPR_31
)
2187 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2190 || (mips_opts
.mips16
2191 && (pinfo
& MIPS16_INSN_WRITE_31
)
2192 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2193 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2194 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2196 /* If the branch writes a register that the previous
2197 instruction reads, we can not swap (we know that
2198 branches only write to RD or to $31). */
2199 || (! mips_opts
.mips16
2200 && (pinfo
& INSN_WRITE_GPR_D
)
2201 && insn_uses_reg (&prev_insn
,
2202 ((ip
->insn_opcode
>> OP_SH_RD
)
2205 || (! mips_opts
.mips16
2206 && (pinfo
& INSN_WRITE_GPR_31
)
2207 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2208 || (mips_opts
.mips16
2209 && (pinfo
& MIPS16_INSN_WRITE_31
)
2210 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2211 /* If we are generating embedded PIC code, the branch
2212 might be expanded into a sequence which uses $at, so
2213 we can't swap with an instruction which reads it. */
2214 || (mips_pic
== EMBEDDED_PIC
2215 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2216 /* If the previous previous instruction has a load
2217 delay, and sets a register that the branch reads, we
2219 || (! mips_opts
.mips16
2220 && mips_opts
.isa
< 4
2221 /* Itbl support may require additional care here. */
2222 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2223 || (! gpr_interlocks
2224 && (prev_prev_insn
.insn_mo
->pinfo
2225 & INSN_LOAD_MEMORY_DELAY
)))
2226 && insn_uses_reg (ip
,
2227 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2230 /* If one instruction sets a condition code and the
2231 other one uses a condition code, we can not swap. */
2232 || ((pinfo
& INSN_READ_COND_CODE
)
2233 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2234 || ((pinfo
& INSN_WRITE_COND_CODE
)
2235 && (prev_pinfo
& INSN_READ_COND_CODE
))
2236 /* If the previous instruction uses the PC, we can not
2238 || (mips_opts
.mips16
2239 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2240 /* If the previous instruction was extended, we can not
2242 || (mips_opts
.mips16
&& prev_insn_extended
)
2243 /* If the previous instruction had a fixup in mips16
2244 mode, we can not swap. This normally means that the
2245 previous instruction was a 4 byte branch anyhow. */
2246 || (mips_opts
.mips16
&& prev_insn_fixp
)
2247 /* If the previous instruction is a sync, sync.l, or
2248 sync.p, we can not swap. */
2249 || (prev_pinfo
&& INSN_SYNC
))
2251 /* We could do even better for unconditional branches to
2252 portions of this object file; we could pick up the
2253 instruction at the destination, put it in the delay
2254 slot, and bump the destination address. */
2256 /* Update the previous insn information. */
2257 prev_prev_insn
= *ip
;
2258 prev_insn
.insn_mo
= &dummy_opcode
;
2262 /* It looks like we can actually do the swap. */
2263 if (! mips_opts
.mips16
)
2268 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2269 memcpy (temp
, prev_f
, 4);
2270 memcpy (prev_f
, f
, 4);
2271 memcpy (f
, temp
, 4);
2274 prev_insn_fixp
->fx_frag
= frag_now
;
2275 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2279 fixp
->fx_frag
= prev_insn_frag
;
2280 fixp
->fx_where
= prev_insn_where
;
2288 assert (prev_insn_fixp
== NULL
);
2289 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2290 memcpy (temp
, prev_f
, 2);
2291 memcpy (prev_f
, f
, 2);
2292 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2294 assert (reloc_type
== BFD_RELOC_UNUSED
);
2295 memcpy (f
, temp
, 2);
2299 memcpy (f
, f
+ 2, 2);
2300 memcpy (f
+ 2, temp
, 2);
2304 fixp
->fx_frag
= prev_insn_frag
;
2305 fixp
->fx_where
= prev_insn_where
;
2309 /* Update the previous insn information; leave prev_insn
2311 prev_prev_insn
= *ip
;
2313 prev_insn_is_delay_slot
= 1;
2315 /* If that was an unconditional branch, forget the previous
2316 insn information. */
2317 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2319 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2320 prev_insn
.insn_mo
= &dummy_opcode
;
2323 prev_insn_fixp
= NULL
;
2324 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2325 prev_insn_extended
= 0;
2327 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2329 /* We don't yet optimize a branch likely. What we should do
2330 is look at the target, copy the instruction found there
2331 into the delay slot, and increment the branch to jump to
2332 the next instruction. */
2334 /* Update the previous insn information. */
2335 prev_prev_insn
= *ip
;
2336 prev_insn
.insn_mo
= &dummy_opcode
;
2337 prev_insn_fixp
= NULL
;
2338 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2339 prev_insn_extended
= 0;
2343 /* Update the previous insn information. */
2345 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2347 prev_prev_insn
= prev_insn
;
2350 /* Any time we see a branch, we always fill the delay slot
2351 immediately; since this insn is not a branch, we know it
2352 is not in a delay slot. */
2353 prev_insn_is_delay_slot
= 0;
2355 prev_insn_fixp
= fixp
;
2356 prev_insn_reloc_type
= reloc_type
;
2357 if (mips_opts
.mips16
)
2358 prev_insn_extended
= (ip
->use_extend
2359 || reloc_type
> BFD_RELOC_UNUSED
);
2362 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2363 prev_insn_unreordered
= 0;
2364 prev_insn_frag
= frag_now
;
2365 prev_insn_where
= f
- frag_now
->fr_literal
;
2366 prev_insn_valid
= 1;
2367 /* start-sanitize-branchbug4011 */
2368 prev_insn_labels
= !! insn_labels
;
2369 /* end-sanitize-branchbug4011 */
2371 else if (place
== NULL
)
2373 /* We need to record a bit of information even when we are not
2374 reordering, in order to determine the base address for mips16
2375 PC relative relocs. */
2376 prev_prev_insn
= prev_insn
;
2378 prev_insn_reloc_type
= reloc_type
;
2379 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2380 prev_insn_unreordered
= 1;
2381 /* start-sanitize-branchbug4011 */
2382 prev_insn_labels
= !! insn_labels
;
2383 /* end-sanitize-branchbug4011 */
2386 /* We just output an insn, so the next one doesn't have a label. */
2387 mips_clear_insn_labels ();
2389 /* We must ensure that a fixup associated with an unmatched %hi
2390 reloc does not become a variant frag. Otherwise, the
2391 rearrangement of %hi relocs in frob_file may confuse
2395 frag_wane (frag_now
);
2400 /* This function forgets that there was any previous instruction or
2401 label. If PRESERVE is non-zero, it remembers enough information to
2402 know whether nops are needed before a noreorder section. */
2405 mips_no_prev_insn (preserve
)
2410 prev_insn
.insn_mo
= &dummy_opcode
;
2411 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2412 prev_nop_frag
= NULL
;
2413 prev_nop_frag_holds
= 0;
2414 prev_nop_frag_required
= 0;
2415 prev_nop_frag_since
= 0;
2417 prev_insn_valid
= 0;
2418 prev_insn_is_delay_slot
= 0;
2419 prev_insn_unreordered
= 0;
2420 prev_insn_extended
= 0;
2421 /* start-sanitize-branchbug4011 */
2422 prev_insn_labels
= 0;
2423 /* end-sanitize-branchbug4011 */
2424 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2425 prev_prev_insn_unreordered
= 0;
2426 mips_clear_insn_labels ();
2429 /* This function must be called whenever we turn on noreorder or emit
2430 something other than instructions. It inserts any NOPS which might
2431 be needed by the previous instruction, and clears the information
2432 kept for the previous instructions. The INSNS parameter is true if
2433 instructions are to follow. */
2436 mips_emit_delays (insns
)
2439 if (! mips_opts
.noreorder
)
2444 if ((! mips_opts
.mips16
2445 && mips_opts
.isa
< 4
2446 && (! cop_interlocks
2447 && (prev_insn
.insn_mo
->pinfo
2448 & (INSN_LOAD_COPROC_DELAY
2449 | INSN_COPROC_MOVE_DELAY
2450 | INSN_WRITE_COND_CODE
))))
2451 || (! hilo_interlocks
2452 && (prev_insn
.insn_mo
->pinfo
2455 || (! mips_opts
.mips16
2457 && (prev_insn
.insn_mo
->pinfo
2458 & INSN_LOAD_MEMORY_DELAY
))
2459 || (! mips_opts
.mips16
2460 && mips_opts
.isa
< 2
2461 && (prev_insn
.insn_mo
->pinfo
2462 & INSN_COPROC_MEMORY_DELAY
)))
2464 /* Itbl support may require additional care here. */
2466 if ((! mips_opts
.mips16
2467 && mips_opts
.isa
< 4
2468 && (! cop_interlocks
2469 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2470 || (! hilo_interlocks
2471 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2472 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2475 if (prev_insn_unreordered
)
2478 else if ((! mips_opts
.mips16
2479 && mips_opts
.isa
< 4
2480 && (! cop_interlocks
2481 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2482 || (! hilo_interlocks
2483 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2484 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2486 /* Itbl support may require additional care here. */
2487 if (! prev_prev_insn_unreordered
)
2493 struct insn_label_list
*l
;
2497 /* Record the frag which holds the nop instructions, so
2498 that we can remove them if we don't need them. */
2499 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2500 prev_nop_frag
= frag_now
;
2501 prev_nop_frag_holds
= nops
;
2502 prev_nop_frag_required
= 0;
2503 prev_nop_frag_since
= 0;
2506 for (; nops
> 0; --nops
)
2511 /* Move on to a new frag, so that it is safe to simply
2512 decrease the size of prev_nop_frag. */
2513 frag_wane (frag_now
);
2517 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2519 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2520 l
->label
->sy_frag
= frag_now
;
2521 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2522 /* mips16 text labels are stored as odd. */
2523 if (mips_opts
.mips16
)
2524 ++l
->label
->sy_value
.X_add_number
;
2529 /* Mark instruction labels in mips16 mode. */
2530 if (mips_opts
.mips16
&& insns
)
2531 mips16_mark_labels ();
2533 mips_no_prev_insn (insns
);
2536 /* Build an instruction created by a macro expansion. This is passed
2537 a pointer to the count of instructions created so far, an
2538 expression, the name of the instruction to build, an operand format
2539 string, and corresponding arguments. */
2543 macro_build (char *place
,
2551 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2560 struct mips_cl_insn insn
;
2561 bfd_reloc_code_real_type r
;
2566 va_start (args
, fmt
);
2572 * If the macro is about to expand into a second instruction,
2573 * print a warning if needed. We need to pass ip as a parameter
2574 * to generate a better warning message here...
2576 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2577 as_warn (_("Macro instruction expanded into multiple instructions"));
2580 *counter
+= 1; /* bump instruction counter */
2582 if (mips_opts
.mips16
)
2584 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2589 r
= BFD_RELOC_UNUSED
;
2590 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2591 assert (insn
.insn_mo
);
2592 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2594 /* Search until we get a match for NAME. */
2597 if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2599 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2601 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2603 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2608 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2609 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2610 && (insn_isa
<= mips_opts
.isa
2612 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2614 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2616 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2617 /* start-sanitize-vr4xxx */
2619 && (insn
.insn_mo
->membership
& INSN_4121
) != 0)
2620 /* end-sanitize-vr4xxx */
2621 /* start-sanitize-vr4320 */
2623 && (insn
.insn_mo
->membership
& INSN_4320
) != 0)
2624 /* end-sanitize-vr4320 */
2625 /* start-sanitize-tx49 */
2627 && (insn
.insn_mo
->membership
& INSN_4900
) != 0)
2628 /* end-sanitize-tx49 */
2629 /* start-sanitize-r5900 */
2631 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2632 /* end-sanitize-r5900 */
2633 /* start-sanitize-cygnus */
2635 && (insn
.insn_mo
->membership
& INSN_5400
) != 0)
2636 /* end-sanitize-cygnus */
2638 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2639 /* start-sanitize-r5900 */
2640 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2641 /* end-sanitize-r5900 */
2642 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2646 assert (insn
.insn_mo
->name
);
2647 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2650 insn
.insn_opcode
= insn
.insn_mo
->match
;
2666 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2672 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2677 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2682 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2689 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2693 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2697 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2701 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2708 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2714 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2715 assert (r
== BFD_RELOC_MIPS_GPREL
2716 || r
== BFD_RELOC_MIPS_LITERAL
2717 || r
== BFD_RELOC_LO16
2718 || r
== BFD_RELOC_MIPS_GOT16
2719 || r
== BFD_RELOC_MIPS_CALL16
2720 || r
== BFD_RELOC_MIPS_GOT_LO16
2721 || r
== BFD_RELOC_MIPS_CALL_LO16
2722 || (ep
->X_op
== O_subtract
2723 && now_seg
== text_section
2724 && r
== BFD_RELOC_PCREL_LO16
));
2728 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2730 && (ep
->X_op
== O_constant
2731 || (ep
->X_op
== O_symbol
2732 && (r
== BFD_RELOC_HI16_S
2733 || r
== BFD_RELOC_HI16
2734 || r
== BFD_RELOC_MIPS_GOT_HI16
2735 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2736 || (ep
->X_op
== O_subtract
2737 && now_seg
== text_section
2738 && r
== BFD_RELOC_PCREL_HI16_S
)));
2739 if (ep
->X_op
== O_constant
)
2741 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2743 r
= BFD_RELOC_UNUSED
;
2748 assert (ep
!= NULL
);
2750 * This allows macro() to pass an immediate expression for
2751 * creating short branches without creating a symbol.
2752 * Note that the expression still might come from the assembly
2753 * input, in which case the value is not checked for range nor
2754 * is a relocation entry generated (yuck).
2756 if (ep
->X_op
== O_constant
)
2758 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2762 r
= BFD_RELOC_16_PCREL_S2
;
2766 assert (ep
!= NULL
);
2767 r
= BFD_RELOC_MIPS_JMP
;
2771 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2780 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2782 append_insn (place
, &insn
, ep
, r
, false);
2786 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2794 struct mips_cl_insn insn
;
2795 bfd_reloc_code_real_type r
;
2797 r
= BFD_RELOC_UNUSED
;
2798 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2799 assert (insn
.insn_mo
);
2800 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2802 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2803 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2806 assert (insn
.insn_mo
->name
);
2807 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2810 insn
.insn_opcode
= insn
.insn_mo
->match
;
2811 insn
.use_extend
= false;
2830 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2835 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2839 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2843 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2853 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2860 regno
= va_arg (args
, int);
2861 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2862 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2883 assert (ep
!= NULL
);
2885 if (ep
->X_op
!= O_constant
)
2886 r
= BFD_RELOC_UNUSED
+ c
;
2889 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2890 false, false, &insn
.insn_opcode
,
2891 &insn
.use_extend
, &insn
.extend
);
2893 r
= BFD_RELOC_UNUSED
;
2899 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2906 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2908 append_insn (place
, &insn
, ep
, r
, false);
2912 * Generate a "lui" instruction.
2915 macro_build_lui (place
, counter
, ep
, regnum
)
2921 expressionS high_expr
;
2922 struct mips_cl_insn insn
;
2923 bfd_reloc_code_real_type r
;
2924 CONST
char *name
= "lui";
2925 CONST
char *fmt
= "t,u";
2927 assert (! mips_opts
.mips16
);
2933 high_expr
.X_op
= O_constant
;
2934 high_expr
.X_add_number
= ep
->X_add_number
;
2937 if (high_expr
.X_op
== O_constant
)
2939 /* we can compute the instruction now without a relocation entry */
2940 if (high_expr
.X_add_number
& 0x8000)
2941 high_expr
.X_add_number
+= 0x10000;
2942 high_expr
.X_add_number
=
2943 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2944 r
= BFD_RELOC_UNUSED
;
2948 assert (ep
->X_op
== O_symbol
);
2949 /* _gp_disp is a special case, used from s_cpload. */
2950 assert (mips_pic
== NO_PIC
2951 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2952 r
= BFD_RELOC_HI16_S
;
2956 * If the macro is about to expand into a second instruction,
2957 * print a warning if needed. We need to pass ip as a parameter
2958 * to generate a better warning message here...
2960 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2961 as_warn (_("Macro instruction expanded into multiple instructions"));
2964 *counter
+= 1; /* bump instruction counter */
2966 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2967 assert (insn
.insn_mo
);
2968 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2969 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2971 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2972 if (r
== BFD_RELOC_UNUSED
)
2974 insn
.insn_opcode
|= high_expr
.X_add_number
;
2975 append_insn (place
, &insn
, NULL
, r
, false);
2978 append_insn (place
, &insn
, &high_expr
, r
, false);
2982 * Generates code to set the $at register to true (one)
2983 * if reg is less than the immediate expression.
2986 set_at (counter
, reg
, unsignedp
)
2991 if (imm_expr
.X_op
== O_constant
2992 && imm_expr
.X_add_number
>= -0x8000
2993 && imm_expr
.X_add_number
< 0x8000)
2994 macro_build ((char *) NULL
, counter
, &imm_expr
,
2995 unsignedp
? "sltiu" : "slti",
2996 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2999 load_register (counter
, AT
, &imm_expr
, 0);
3000 macro_build ((char *) NULL
, counter
, NULL
,
3001 unsignedp
? "sltu" : "slt",
3002 "d,v,t", AT
, reg
, AT
);
3006 /* Warn if an expression is not a constant. */
3009 check_absolute_expr (ip
, ex
)
3010 struct mips_cl_insn
*ip
;
3013 if (ex
->X_op
== O_big
)
3014 as_bad (_("unsupported large constant"));
3015 else if (ex
->X_op
!= O_constant
)
3016 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3019 /* Count the leading zeroes by performing a binary chop. This is a
3020 bulky bit of source, but performance is a LOT better for the
3021 majority of values than a simple loop to count the bits:
3022 for (lcnt = 0; (lcnt < 32); lcnt++)
3023 if ((v) & (1 << (31 - lcnt)))
3025 However it is not code size friendly, and the gain will drop a bit
3026 on certain cached systems.
3028 #define COUNT_TOP_ZEROES(v) \
3029 (((v) & ~0xffff) == 0 \
3030 ? ((v) & ~0xff) == 0 \
3031 ? ((v) & ~0xf) == 0 \
3032 ? ((v) & ~0x3) == 0 \
3033 ? ((v) & ~0x1) == 0 \
3038 : ((v) & ~0x7) == 0 \
3041 : ((v) & ~0x3f) == 0 \
3042 ? ((v) & ~0x1f) == 0 \
3045 : ((v) & ~0x7f) == 0 \
3048 : ((v) & ~0xfff) == 0 \
3049 ? ((v) & ~0x3ff) == 0 \
3050 ? ((v) & ~0x1ff) == 0 \
3053 : ((v) & ~0x7ff) == 0 \
3056 : ((v) & ~0x3fff) == 0 \
3057 ? ((v) & ~0x1fff) == 0 \
3060 : ((v) & ~0x7fff) == 0 \
3063 : ((v) & ~0xffffff) == 0 \
3064 ? ((v) & ~0xfffff) == 0 \
3065 ? ((v) & ~0x3ffff) == 0 \
3066 ? ((v) & ~0x1ffff) == 0 \
3069 : ((v) & ~0x7ffff) == 0 \
3072 : ((v) & ~0x3fffff) == 0 \
3073 ? ((v) & ~0x1fffff) == 0 \
3076 : ((v) & ~0x7fffff) == 0 \
3079 : ((v) & ~0xfffffff) == 0 \
3080 ? ((v) & ~0x3ffffff) == 0 \
3081 ? ((v) & ~0x1ffffff) == 0 \
3084 : ((v) & ~0x7ffffff) == 0 \
3087 : ((v) & ~0x3fffffff) == 0 \
3088 ? ((v) & ~0x1fffffff) == 0 \
3091 : ((v) & ~0x7fffffff) == 0 \
3096 * This routine generates the least number of instructions neccessary to load
3097 * an absolute expression value into a register.
3100 load_register (counter
, reg
, ep
, dbl
)
3107 expressionS hi32
, lo32
;
3109 if (ep
->X_op
!= O_big
)
3111 assert (ep
->X_op
== O_constant
);
3112 if (ep
->X_add_number
< 0x8000
3113 && (ep
->X_add_number
>= 0
3114 || (ep
->X_add_number
>= -0x8000
3117 || sizeof (ep
->X_add_number
) > 4))))
3119 /* We can handle 16 bit signed values with an addiu to
3120 $zero. No need to ever use daddiu here, since $zero and
3121 the result are always correct in 32 bit mode. */
3122 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3123 (int) BFD_RELOC_LO16
);
3126 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3128 /* We can handle 16 bit unsigned values with an ori to
3130 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3131 (int) BFD_RELOC_LO16
);
3134 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3135 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3136 == ~ (offsetT
) 0x7fffffff))
3139 || sizeof (ep
->X_add_number
) > 4
3140 || (ep
->X_add_number
& 0x80000000) == 0))
3141 || ((mips_opts
.isa
< 3 || ! dbl
)
3142 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3143 || (mips_opts
.isa
< 3
3145 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3146 == ~ (offsetT
) 0xffffffff)))
3148 /* 32 bit values require an lui. */
3149 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3150 (int) BFD_RELOC_HI16
);
3151 if ((ep
->X_add_number
& 0xffff) != 0)
3152 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3153 (int) BFD_RELOC_LO16
);
3158 /* The value is larger than 32 bits. */
3160 if (mips_opts
.isa
< 3)
3162 as_bad (_("Number larger than 32 bits"));
3163 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3164 (int) BFD_RELOC_LO16
);
3168 if (ep
->X_op
!= O_big
)
3171 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3172 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3173 hi32
.X_add_number
&= 0xffffffff;
3175 lo32
.X_add_number
&= 0xffffffff;
3179 assert (ep
->X_add_number
> 2);
3180 if (ep
->X_add_number
== 3)
3181 generic_bignum
[3] = 0;
3182 else if (ep
->X_add_number
> 4)
3183 as_bad (_("Number larger than 64 bits"));
3184 lo32
.X_op
= O_constant
;
3185 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3186 hi32
.X_op
= O_constant
;
3187 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3190 if (hi32
.X_add_number
== 0)
3195 unsigned long hi
, lo
;
3197 if (hi32
.X_add_number
== 0xffffffff)
3199 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3201 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3202 reg
, 0, (int) BFD_RELOC_LO16
);
3205 if (lo32
.X_add_number
& 0x80000000)
3207 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3208 (int) BFD_RELOC_HI16
);
3209 if (lo32
.X_add_number
& 0xffff)
3210 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3211 reg
, reg
, (int) BFD_RELOC_LO16
);
3216 /* Check for 16bit shifted constant. We know that hi32 is
3217 non-zero, so start the mask on the first bit of the hi32
3222 unsigned long himask
, lomask
;
3226 himask
= 0xffff >> (32 - shift
);
3227 lomask
= (0xffff << shift
) & 0xffffffff;
3231 himask
= 0xffff << (shift
- 32);
3234 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3235 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3239 tmp
.X_op
= O_constant
;
3241 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3242 | (lo32
.X_add_number
>> shift
));
3244 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3245 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3246 (int) BFD_RELOC_LO16
);
3247 macro_build ((char *) NULL
, counter
, NULL
,
3248 (shift
>= 32) ? "dsll32" : "dsll",
3250 (shift
>= 32) ? shift
- 32 : shift
);
3254 } while (shift
<= (64 - 16));
3256 /* Find the bit number of the lowest one bit, and store the
3257 shifted value in hi/lo. */
3258 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3259 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3263 while ((lo
& 1) == 0)
3268 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3274 while ((hi
& 1) == 0)
3283 /* Optimize if the shifted value is a (power of 2) - 1. */
3284 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3285 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3287 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3292 /* This instruction will set the register to be all
3294 tmp
.X_op
= O_constant
;
3295 tmp
.X_add_number
= (offsetT
) -1;
3296 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3297 reg
, 0, (int) BFD_RELOC_LO16
);
3301 macro_build ((char *) NULL
, counter
, NULL
,
3302 (bit
>= 32) ? "dsll32" : "dsll",
3304 (bit
>= 32) ? bit
- 32 : bit
);
3306 macro_build ((char *) NULL
, counter
, NULL
,
3307 (shift
>= 32) ? "dsrl32" : "dsrl",
3309 (shift
>= 32) ? shift
- 32 : shift
);
3314 /* Sign extend hi32 before calling load_register, because we can
3315 generally get better code when we load a sign extended value. */
3316 if ((hi32
.X_add_number
& 0x80000000) != 0)
3317 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3318 load_register (counter
, reg
, &hi32
, 0);
3321 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3325 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3334 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3336 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3337 (int) BFD_RELOC_HI16
);
3338 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3345 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3350 mid16
.X_add_number
>>= 16;
3351 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3352 freg
, (int) BFD_RELOC_LO16
);
3353 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3357 if ((lo32
.X_add_number
& 0xffff) != 0)
3358 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3359 (int) BFD_RELOC_LO16
);
3362 /* Load an address into a register. */
3365 load_address (counter
, reg
, ep
)
3372 if (ep
->X_op
!= O_constant
3373 && ep
->X_op
!= O_symbol
)
3375 as_bad (_("expression too complex"));
3376 ep
->X_op
= O_constant
;
3379 if (ep
->X_op
== O_constant
)
3381 load_register (counter
, reg
, ep
, 0);
3385 if (mips_pic
== NO_PIC
)
3387 /* If this is a reference to a GP relative symbol, we want
3388 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3390 lui $reg,<sym> (BFD_RELOC_HI16_S)
3391 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3392 If we have an addend, we always use the latter form. */
3393 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3394 || nopic_need_relax (ep
->X_add_symbol
, 1))
3399 macro_build ((char *) NULL
, counter
, ep
,
3400 ((bfd_arch_bits_per_address (stdoutput
) == 32
3401 || mips_opts
.isa
< 3)
3402 ? "addiu" : "daddiu"),
3403 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3404 p
= frag_var (rs_machine_dependent
, 8, 0,
3405 RELAX_ENCODE (4, 8, 0, 4, 0,
3406 mips_opts
.warn_about_macros
),
3407 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3409 macro_build_lui (p
, counter
, ep
, reg
);
3412 macro_build (p
, counter
, ep
,
3413 ((bfd_arch_bits_per_address (stdoutput
) == 32
3414 || mips_opts
.isa
< 3)
3415 ? "addiu" : "daddiu"),
3416 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3418 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3422 /* If this is a reference to an external symbol, we want
3423 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3425 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3427 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3428 If there is a constant, it must be added in after. */
3429 ex
.X_add_number
= ep
->X_add_number
;
3430 ep
->X_add_number
= 0;
3432 macro_build ((char *) NULL
, counter
, ep
,
3433 ((bfd_arch_bits_per_address (stdoutput
) == 32
3434 || mips_opts
.isa
< 3)
3436 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3437 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3438 p
= frag_var (rs_machine_dependent
, 4, 0,
3439 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3440 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3441 macro_build (p
, counter
, ep
,
3442 ((bfd_arch_bits_per_address (stdoutput
) == 32
3443 || mips_opts
.isa
< 3)
3444 ? "addiu" : "daddiu"),
3445 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3446 if (ex
.X_add_number
!= 0)
3448 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3449 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3450 ex
.X_op
= O_constant
;
3451 macro_build ((char *) NULL
, counter
, &ex
,
3452 ((bfd_arch_bits_per_address (stdoutput
) == 32
3453 || mips_opts
.isa
< 3)
3454 ? "addiu" : "daddiu"),
3455 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3458 else if (mips_pic
== SVR4_PIC
)
3463 /* This is the large GOT case. If this is a reference to an
3464 external symbol, we want
3465 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3467 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3468 Otherwise, for a reference to a local symbol, we want
3469 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3471 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3472 If there is a constant, it must be added in after. */
3473 ex
.X_add_number
= ep
->X_add_number
;
3474 ep
->X_add_number
= 0;
3475 if (reg_needs_delay (GP
))
3480 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3481 (int) BFD_RELOC_MIPS_GOT_HI16
);
3482 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3483 ((bfd_arch_bits_per_address (stdoutput
) == 32
3484 || mips_opts
.isa
< 3)
3485 ? "addu" : "daddu"),
3486 "d,v,t", reg
, reg
, GP
);
3487 macro_build ((char *) NULL
, counter
, ep
,
3488 ((bfd_arch_bits_per_address (stdoutput
) == 32
3489 || mips_opts
.isa
< 3)
3491 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3492 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3493 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3494 mips_opts
.warn_about_macros
),
3495 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3498 /* We need a nop before loading from $gp. This special
3499 check is required because the lui which starts the main
3500 instruction stream does not refer to $gp, and so will not
3501 insert the nop which may be required. */
3502 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3505 macro_build (p
, counter
, ep
,
3506 ((bfd_arch_bits_per_address (stdoutput
) == 32
3507 || mips_opts
.isa
< 3)
3509 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3511 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3513 macro_build (p
, counter
, ep
,
3514 ((bfd_arch_bits_per_address (stdoutput
) == 32
3515 || mips_opts
.isa
< 3)
3516 ? "addiu" : "daddiu"),
3517 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3518 if (ex
.X_add_number
!= 0)
3520 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3521 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3522 ex
.X_op
= O_constant
;
3523 macro_build ((char *) NULL
, counter
, &ex
,
3524 ((bfd_arch_bits_per_address (stdoutput
) == 32
3525 || mips_opts
.isa
< 3)
3526 ? "addiu" : "daddiu"),
3527 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3530 else if (mips_pic
== EMBEDDED_PIC
)
3533 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3535 macro_build ((char *) NULL
, counter
, ep
,
3536 ((bfd_arch_bits_per_address (stdoutput
) == 32
3537 || mips_opts
.isa
< 3)
3538 ? "addiu" : "daddiu"),
3539 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3547 * This routine implements the seemingly endless macro or synthesized
3548 * instructions and addressing modes in the mips assembly language. Many
3549 * of these macros are simple and are similar to each other. These could
3550 * probably be handled by some kind of table or grammer aproach instead of
3551 * this verbose method. Others are not simple macros but are more like
3552 * optimizing code generation.
3553 * One interesting optimization is when several store macros appear
3554 * consecutivly that would load AT with the upper half of the same address.
3555 * The ensuing load upper instructions are ommited. This implies some kind
3556 * of global optimization. We currently only optimize within a single macro.
3557 * For many of the load and store macros if the address is specified as a
3558 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3559 * first load register 'at' with zero and use it as the base register. The
3560 * mips assembler simply uses register $zero. Just one tiny optimization
3565 struct mips_cl_insn
*ip
;
3567 register int treg
, sreg
, dreg
, breg
;
3583 bfd_reloc_code_real_type r
;
3585 int hold_mips_optimize
;
3587 assert (! mips_opts
.mips16
);
3589 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3590 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3591 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3592 mask
= ip
->insn_mo
->mask
;
3594 expr1
.X_op
= O_constant
;
3595 expr1
.X_op_symbol
= NULL
;
3596 expr1
.X_add_symbol
= NULL
;
3597 expr1
.X_add_number
= 1;
3609 mips_emit_delays (true);
3610 ++mips_opts
.noreorder
;
3611 mips_any_noreorder
= 1;
3613 expr1
.X_add_number
= 8;
3614 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3616 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3618 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3619 macro_build ((char *) NULL
, &icnt
, NULL
,
3620 dbl
? "dsub" : "sub",
3621 "d,v,t", dreg
, 0, sreg
);
3623 --mips_opts
.noreorder
;
3644 if (imm_expr
.X_op
== O_constant
3645 && imm_expr
.X_add_number
>= -0x8000
3646 && imm_expr
.X_add_number
< 0x8000)
3648 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3649 (int) BFD_RELOC_LO16
);
3652 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3653 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3672 if (imm_expr
.X_op
== O_constant
3673 && imm_expr
.X_add_number
>= 0
3674 && imm_expr
.X_add_number
< 0x10000)
3676 if (mask
!= M_NOR_I
)
3677 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3678 sreg
, (int) BFD_RELOC_LO16
);
3681 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3682 treg
, sreg
, (int) BFD_RELOC_LO16
);
3683 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3689 load_register (&icnt
, AT
, &imm_expr
, 0);
3690 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3707 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3709 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3713 load_register (&icnt
, AT
, &imm_expr
, 0);
3714 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3722 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3723 likely
? "bgezl" : "bgez",
3729 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3730 likely
? "blezl" : "blez",
3734 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3735 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3736 likely
? "beql" : "beq",
3743 /* check for > max integer */
3744 maxnum
= 0x7fffffff;
3745 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3752 if (imm_expr
.X_op
== O_constant
3753 && imm_expr
.X_add_number
>= maxnum
3754 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3757 /* result is always false */
3760 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3761 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3765 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3766 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3771 if (imm_expr
.X_op
!= O_constant
)
3772 as_bad (_("Unsupported large constant"));
3773 imm_expr
.X_add_number
++;
3777 if (mask
== M_BGEL_I
)
3779 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3781 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3782 likely
? "bgezl" : "bgez",
3786 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3788 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3789 likely
? "bgtzl" : "bgtz",
3793 maxnum
= 0x7fffffff;
3794 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3801 maxnum
= - maxnum
- 1;
3802 if (imm_expr
.X_op
== O_constant
3803 && imm_expr
.X_add_number
<= maxnum
3804 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3807 /* result is always true */
3808 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3809 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3812 set_at (&icnt
, sreg
, 0);
3813 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3814 likely
? "beql" : "beq",
3825 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3826 likely
? "beql" : "beq",
3830 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3832 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3833 likely
? "beql" : "beq",
3841 || (mips_opts
.isa
< 3
3842 && imm_expr
.X_op
== O_constant
3843 && imm_expr
.X_add_number
== 0xffffffff))
3845 if (imm_expr
.X_op
!= O_constant
)
3846 as_bad (_("Unsupported large constant"));
3847 imm_expr
.X_add_number
++;
3851 if (mask
== M_BGEUL_I
)
3853 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3855 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3857 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3858 likely
? "bnel" : "bne",
3862 set_at (&icnt
, sreg
, 1);
3863 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3864 likely
? "beql" : "beq",
3873 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3874 likely
? "bgtzl" : "bgtz",
3880 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3881 likely
? "bltzl" : "bltz",
3885 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3886 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3887 likely
? "bnel" : "bne",
3896 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3897 likely
? "bnel" : "bne",
3903 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3905 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3906 likely
? "bnel" : "bne",
3915 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3916 likely
? "blezl" : "blez",
3922 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3923 likely
? "bgezl" : "bgez",
3927 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3928 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3929 likely
? "beql" : "beq",
3936 maxnum
= 0x7fffffff;
3937 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3944 if (imm_expr
.X_op
== O_constant
3945 && imm_expr
.X_add_number
>= maxnum
3946 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3948 if (imm_expr
.X_op
!= O_constant
)
3949 as_bad (_("Unsupported large constant"));
3950 imm_expr
.X_add_number
++;
3954 if (mask
== M_BLTL_I
)
3956 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3958 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3959 likely
? "bltzl" : "bltz",
3963 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3965 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3966 likely
? "blezl" : "blez",
3970 set_at (&icnt
, sreg
, 0);
3971 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3972 likely
? "bnel" : "bne",
3981 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3982 likely
? "beql" : "beq",
3988 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3990 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3991 likely
? "beql" : "beq",
3999 || (mips_opts
.isa
< 3
4000 && imm_expr
.X_op
== O_constant
4001 && imm_expr
.X_add_number
== 0xffffffff))
4003 if (imm_expr
.X_op
!= O_constant
)
4004 as_bad (_("Unsupported large constant"));
4005 imm_expr
.X_add_number
++;
4009 if (mask
== M_BLTUL_I
)
4011 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4013 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4015 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4016 likely
? "beql" : "beq",
4020 set_at (&icnt
, sreg
, 1);
4021 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4022 likely
? "bnel" : "bne",
4031 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4032 likely
? "bltzl" : "bltz",
4038 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4039 likely
? "bgtzl" : "bgtz",
4043 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4044 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4045 likely
? "bnel" : "bne",
4056 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4057 likely
? "bnel" : "bne",
4061 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
4063 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4064 likely
? "bnel" : "bne",
4080 as_warn (_("Divide by zero."));
4082 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4084 /* start-sanitize-r5900 */
4086 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4088 /* end-sanitize-r5900 */
4089 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4093 mips_emit_delays (true);
4094 ++mips_opts
.noreorder
;
4095 mips_any_noreorder
= 1;
4098 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4099 macro_build ((char *) NULL
, &icnt
, NULL
,
4100 dbl
? "ddiv" : "div",
4101 "z,s,t", sreg
, treg
);
4105 expr1
.X_add_number
= 8;
4106 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4107 macro_build ((char *) NULL
, &icnt
, NULL
,
4108 dbl
? "ddiv" : "div",
4109 "z,s,t", sreg
, treg
);
4110 /* start-sanitize-r5900 */
4112 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4114 /* end-sanitize-r5900 */
4115 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4117 expr1
.X_add_number
= -1;
4118 macro_build ((char *) NULL
, &icnt
, &expr1
,
4119 dbl
? "daddiu" : "addiu",
4120 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
4121 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4122 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
4125 expr1
.X_add_number
= 1;
4126 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
4127 (int) BFD_RELOC_LO16
);
4128 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
4133 expr1
.X_add_number
= 0x80000000;
4134 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4135 (int) BFD_RELOC_HI16
);
4139 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4140 /* We want to close the noreorder block as soon as possible, so
4141 that later insns are available for delay slot filling. */
4142 --mips_opts
.noreorder
;
4146 expr1
.X_add_number
= 8;
4147 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4148 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4150 /* We want to close the noreorder block as soon as possible, so
4151 that later insns are available for delay slot filling. */
4152 --mips_opts
.noreorder
;
4154 /* start-sanitize-r5900 */
4156 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
4158 /* end-sanitize-r5900 */
4159 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4161 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4200 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4202 as_warn (_("Divide by zero."));
4204 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4206 /* start-sanitize-r5900 */
4208 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4210 /* end-sanitize-r5900 */
4211 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4214 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4216 if (strcmp (s2
, "mflo") == 0)
4217 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4220 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4223 if (imm_expr
.X_op
== O_constant
4224 && imm_expr
.X_add_number
== -1
4225 && s
[strlen (s
) - 1] != 'u')
4227 if (strcmp (s2
, "mflo") == 0)
4230 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4233 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4237 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4241 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4242 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4243 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4262 mips_emit_delays (true);
4263 ++mips_opts
.noreorder
;
4264 mips_any_noreorder
= 1;
4267 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4268 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4269 /* We want to close the noreorder block as soon as possible, so
4270 that later insns are available for delay slot filling. */
4271 --mips_opts
.noreorder
;
4275 expr1
.X_add_number
= 8;
4276 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4277 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4279 /* We want to close the noreorder block as soon as possible, so
4280 that later insns are available for delay slot filling. */
4281 --mips_opts
.noreorder
;
4282 /* start-sanitize-r5900 */
4284 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
4286 /* end-sanitize-r5900 */
4287 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4289 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4295 /* Load the address of a symbol into a register. If breg is not
4296 zero, we then add a base register to it. */
4298 /* When generating embedded PIC code, we permit expressions of
4301 where bar is an address in the .text section. These are used
4302 when getting the addresses of functions. We don't permit
4303 X_add_number to be non-zero, because if the symbol is
4304 external the relaxing code needs to know that any addend is
4305 purely the offset to X_op_symbol. */
4306 if (mips_pic
== EMBEDDED_PIC
4307 && offset_expr
.X_op
== O_subtract
4308 && now_seg
== text_section
4309 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
4310 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
4311 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
4312 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
4313 ->sy_value
.X_add_symbol
)
4316 && offset_expr
.X_add_number
== 0)
4318 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4319 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4320 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4321 ((bfd_arch_bits_per_address (stdoutput
) == 32
4322 || mips_opts
.isa
< 3)
4323 ? "addiu" : "daddiu"),
4324 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4328 if (offset_expr
.X_op
!= O_symbol
4329 && offset_expr
.X_op
!= O_constant
)
4331 as_bad (_("expression too complex"));
4332 offset_expr
.X_op
= O_constant
;
4346 if (offset_expr
.X_op
== O_constant
)
4347 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4348 else if (mips_pic
== NO_PIC
)
4350 /* If this is a reference to an GP relative symbol, we want
4351 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4353 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4354 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4355 If we have a constant, we need two instructions anyhow,
4356 so we may as well always use the latter form. */
4357 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4358 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4363 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4364 ((bfd_arch_bits_per_address (stdoutput
) == 32
4365 || mips_opts
.isa
< 3)
4366 ? "addiu" : "daddiu"),
4367 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4368 p
= frag_var (rs_machine_dependent
, 8, 0,
4369 RELAX_ENCODE (4, 8, 0, 4, 0,
4370 mips_opts
.warn_about_macros
),
4371 offset_expr
.X_add_symbol
, (offsetT
) 0,
4374 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4377 macro_build (p
, &icnt
, &offset_expr
,
4378 ((bfd_arch_bits_per_address (stdoutput
) == 32
4379 || mips_opts
.isa
< 3)
4380 ? "addiu" : "daddiu"),
4381 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4383 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4385 /* If this is a reference to an external symbol, and there
4386 is no constant, we want
4387 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4388 For a local symbol, we want
4389 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4391 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4393 If we have a small constant, and this is a reference to
4394 an external symbol, we want
4395 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4397 addiu $tempreg,$tempreg,<constant>
4398 For a local symbol, we want the same instruction
4399 sequence, but we output a BFD_RELOC_LO16 reloc on the
4402 If we have a large constant, and this is a reference to
4403 an external symbol, we want
4404 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4405 lui $at,<hiconstant>
4406 addiu $at,$at,<loconstant>
4407 addu $tempreg,$tempreg,$at
4408 For a local symbol, we want the same instruction
4409 sequence, but we output a BFD_RELOC_LO16 reloc on the
4410 addiu instruction. */
4411 expr1
.X_add_number
= offset_expr
.X_add_number
;
4412 offset_expr
.X_add_number
= 0;
4414 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4416 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4417 if (expr1
.X_add_number
== 0)
4425 /* We're going to put in an addu instruction using
4426 tempreg, so we may as well insert the nop right
4428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4432 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4433 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4435 ? mips_opts
.warn_about_macros
4437 offset_expr
.X_add_symbol
, (offsetT
) 0,
4441 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4444 macro_build (p
, &icnt
, &expr1
,
4445 ((bfd_arch_bits_per_address (stdoutput
) == 32
4446 || mips_opts
.isa
< 3)
4447 ? "addiu" : "daddiu"),
4448 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4449 /* FIXME: If breg == 0, and the next instruction uses
4450 $tempreg, then if this variant case is used an extra
4451 nop will be generated. */
4453 else if (expr1
.X_add_number
>= -0x8000
4454 && expr1
.X_add_number
< 0x8000)
4456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4458 macro_build ((char *) NULL
, &icnt
, &expr1
,
4459 ((bfd_arch_bits_per_address (stdoutput
) == 32
4460 || mips_opts
.isa
< 3)
4461 ? "addiu" : "daddiu"),
4462 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4463 (void) frag_var (rs_machine_dependent
, 0, 0,
4464 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4465 offset_expr
.X_add_symbol
, (offsetT
) 0,
4472 /* If we are going to add in a base register, and the
4473 target register and the base register are the same,
4474 then we are using AT as a temporary register. Since
4475 we want to load the constant into AT, we add our
4476 current AT (from the global offset table) and the
4477 register into the register now, and pretend we were
4478 not using a base register. */
4483 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4486 ((bfd_arch_bits_per_address (stdoutput
) == 32
4487 || mips_opts
.isa
< 3)
4488 ? "addu" : "daddu"),
4489 "d,v,t", treg
, AT
, breg
);
4495 /* Set mips_optimize around the lui instruction to avoid
4496 inserting an unnecessary nop after the lw. */
4497 hold_mips_optimize
= mips_optimize
;
4499 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4500 mips_optimize
= hold_mips_optimize
;
4502 macro_build ((char *) NULL
, &icnt
, &expr1
,
4503 ((bfd_arch_bits_per_address (stdoutput
) == 32
4504 || mips_opts
.isa
< 3)
4505 ? "addiu" : "daddiu"),
4506 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4507 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4508 ((bfd_arch_bits_per_address (stdoutput
) == 32
4509 || mips_opts
.isa
< 3)
4510 ? "addu" : "daddu"),
4511 "d,v,t", tempreg
, tempreg
, AT
);
4512 (void) frag_var (rs_machine_dependent
, 0, 0,
4513 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4514 offset_expr
.X_add_symbol
, (offsetT
) 0,
4519 else if (mips_pic
== SVR4_PIC
)
4523 /* This is the large GOT case. If this is a reference to an
4524 external symbol, and there is no constant, we want
4525 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4526 addu $tempreg,$tempreg,$gp
4527 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4528 For a local symbol, we want
4529 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4531 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4533 If we have a small constant, and this is a reference to
4534 an external symbol, we want
4535 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4536 addu $tempreg,$tempreg,$gp
4537 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4539 addiu $tempreg,$tempreg,<constant>
4540 For a local symbol, we want
4541 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4543 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4545 If we have a large constant, and this is a reference to
4546 an external symbol, we want
4547 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4548 addu $tempreg,$tempreg,$gp
4549 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4550 lui $at,<hiconstant>
4551 addiu $at,$at,<loconstant>
4552 addu $tempreg,$tempreg,$at
4553 For a local symbol, we want
4554 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4555 lui $at,<hiconstant>
4556 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4557 addu $tempreg,$tempreg,$at
4559 expr1
.X_add_number
= offset_expr
.X_add_number
;
4560 offset_expr
.X_add_number
= 0;
4562 if (reg_needs_delay (GP
))
4566 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4567 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4568 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4569 ((bfd_arch_bits_per_address (stdoutput
) == 32
4570 || mips_opts
.isa
< 3)
4571 ? "addu" : "daddu"),
4572 "d,v,t", tempreg
, tempreg
, GP
);
4573 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4575 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4577 if (expr1
.X_add_number
== 0)
4585 /* We're going to put in an addu instruction using
4586 tempreg, so we may as well insert the nop right
4588 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4593 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4594 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4597 ? mips_opts
.warn_about_macros
4599 offset_expr
.X_add_symbol
, (offsetT
) 0,
4602 else if (expr1
.X_add_number
>= -0x8000
4603 && expr1
.X_add_number
< 0x8000)
4605 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4607 macro_build ((char *) NULL
, &icnt
, &expr1
,
4608 ((bfd_arch_bits_per_address (stdoutput
) == 32
4609 || mips_opts
.isa
< 3)
4610 ? "addiu" : "daddiu"),
4611 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4613 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4614 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4616 ? mips_opts
.warn_about_macros
4618 offset_expr
.X_add_symbol
, (offsetT
) 0,
4625 /* If we are going to add in a base register, and the
4626 target register and the base register are the same,
4627 then we are using AT as a temporary register. Since
4628 we want to load the constant into AT, we add our
4629 current AT (from the global offset table) and the
4630 register into the register now, and pretend we were
4631 not using a base register. */
4639 assert (tempreg
== AT
);
4640 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4642 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4643 ((bfd_arch_bits_per_address (stdoutput
) == 32
4644 || mips_opts
.isa
< 3)
4645 ? "addu" : "daddu"),
4646 "d,v,t", treg
, AT
, breg
);
4651 /* Set mips_optimize around the lui instruction to avoid
4652 inserting an unnecessary nop after the lw. */
4653 hold_mips_optimize
= mips_optimize
;
4655 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4656 mips_optimize
= hold_mips_optimize
;
4658 macro_build ((char *) NULL
, &icnt
, &expr1
,
4659 ((bfd_arch_bits_per_address (stdoutput
) == 32
4660 || mips_opts
.isa
< 3)
4661 ? "addiu" : "daddiu"),
4662 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4663 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4664 ((bfd_arch_bits_per_address (stdoutput
) == 32
4665 || mips_opts
.isa
< 3)
4666 ? "addu" : "daddu"),
4667 "d,v,t", dreg
, dreg
, AT
);
4669 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4670 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4673 ? mips_opts
.warn_about_macros
4675 offset_expr
.X_add_symbol
, (offsetT
) 0,
4683 /* This is needed because this instruction uses $gp, but
4684 the first instruction on the main stream does not. */
4685 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4688 macro_build (p
, &icnt
, &offset_expr
,
4690 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4692 if (expr1
.X_add_number
>= -0x8000
4693 && expr1
.X_add_number
< 0x8000)
4695 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4697 macro_build (p
, &icnt
, &expr1
,
4698 ((bfd_arch_bits_per_address (stdoutput
) == 32
4699 || mips_opts
.isa
< 3)
4700 ? "addiu" : "daddiu"),
4701 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4702 /* FIXME: If add_number is 0, and there was no base
4703 register, the external symbol case ended with a load,
4704 so if the symbol turns out to not be external, and
4705 the next instruction uses tempreg, an unnecessary nop
4706 will be inserted. */
4712 /* We must add in the base register now, as in the
4713 external symbol case. */
4714 assert (tempreg
== AT
);
4715 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4717 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4718 ((bfd_arch_bits_per_address (stdoutput
) == 32
4719 || mips_opts
.isa
< 3)
4720 ? "addu" : "daddu"),
4721 "d,v,t", treg
, AT
, breg
);
4724 /* We set breg to 0 because we have arranged to add
4725 it in in both cases. */
4729 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4731 macro_build (p
, &icnt
, &expr1
,
4732 ((bfd_arch_bits_per_address (stdoutput
) == 32
4733 || mips_opts
.isa
< 3)
4734 ? "addiu" : "daddiu"),
4735 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4737 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4738 ((bfd_arch_bits_per_address (stdoutput
) == 32
4739 || mips_opts
.isa
< 3)
4740 ? "addu" : "daddu"),
4741 "d,v,t", tempreg
, tempreg
, AT
);
4745 else if (mips_pic
== EMBEDDED_PIC
)
4748 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4751 ((bfd_arch_bits_per_address (stdoutput
) == 32
4752 || mips_opts
.isa
< 3)
4753 ? "addiu" : "daddiu"),
4754 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4760 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4761 ((bfd_arch_bits_per_address (stdoutput
) == 32
4762 || mips_opts
.isa
< 3)
4763 ? "addu" : "daddu"),
4764 "d,v,t", treg
, tempreg
, breg
);
4772 /* The j instruction may not be used in PIC code, since it
4773 requires an absolute address. We convert it to a b
4775 if (mips_pic
== NO_PIC
)
4776 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4778 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4781 /* The jal instructions must be handled as macros because when
4782 generating PIC code they expand to multi-instruction
4783 sequences. Normally they are simple instructions. */
4788 if (mips_pic
== NO_PIC
4789 || mips_pic
== EMBEDDED_PIC
)
4790 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4792 else if (mips_pic
== SVR4_PIC
)
4794 if (sreg
!= PIC_CALL_REG
)
4795 as_warn (_("MIPS PIC call to register other than $25"));
4797 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4799 if (mips_cprestore_offset
< 0)
4800 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4803 expr1
.X_add_number
= mips_cprestore_offset
;
4804 macro_build ((char *) NULL
, &icnt
, &expr1
,
4805 ((bfd_arch_bits_per_address (stdoutput
) == 32
4806 || mips_opts
.isa
< 3)
4808 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4817 if (mips_pic
== NO_PIC
)
4818 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4819 else if (mips_pic
== SVR4_PIC
)
4821 /* If this is a reference to an external symbol, and we are
4822 using a small GOT, we want
4823 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4827 lw $gp,cprestore($sp)
4828 The cprestore value is set using the .cprestore
4829 pseudo-op. If we are using a big GOT, we want
4830 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4832 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4836 lw $gp,cprestore($sp)
4837 If the symbol is not external, we want
4838 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4840 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4843 lw $gp,cprestore($sp) */
4847 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4848 ((bfd_arch_bits_per_address (stdoutput
) == 32
4849 || mips_opts
.isa
< 3)
4851 "t,o(b)", PIC_CALL_REG
,
4852 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4853 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4855 p
= frag_var (rs_machine_dependent
, 4, 0,
4856 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4857 offset_expr
.X_add_symbol
, (offsetT
) 0,
4864 if (reg_needs_delay (GP
))
4868 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4869 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4870 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4871 ((bfd_arch_bits_per_address (stdoutput
) == 32
4872 || mips_opts
.isa
< 3)
4873 ? "addu" : "daddu"),
4874 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4875 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4876 ((bfd_arch_bits_per_address (stdoutput
) == 32
4877 || mips_opts
.isa
< 3)
4879 "t,o(b)", PIC_CALL_REG
,
4880 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4881 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4883 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4884 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4886 offset_expr
.X_add_symbol
, (offsetT
) 0,
4890 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4893 macro_build (p
, &icnt
, &offset_expr
,
4894 ((bfd_arch_bits_per_address (stdoutput
) == 32
4895 || mips_opts
.isa
< 3)
4897 "t,o(b)", PIC_CALL_REG
,
4898 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4900 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4903 macro_build (p
, &icnt
, &offset_expr
,
4904 ((bfd_arch_bits_per_address (stdoutput
) == 32
4905 || mips_opts
.isa
< 3)
4906 ? "addiu" : "daddiu"),
4907 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4908 (int) BFD_RELOC_LO16
);
4909 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4910 "jalr", "s", PIC_CALL_REG
);
4911 if (mips_cprestore_offset
< 0)
4912 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4915 if (mips_opts
.noreorder
)
4916 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4918 expr1
.X_add_number
= mips_cprestore_offset
;
4919 macro_build ((char *) NULL
, &icnt
, &expr1
,
4920 ((bfd_arch_bits_per_address (stdoutput
) == 32
4921 || mips_opts
.isa
< 3)
4923 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4927 else if (mips_pic
== EMBEDDED_PIC
)
4929 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4930 /* The linker may expand the call to a longer sequence which
4931 uses $at, so we must break rather than return. */
4956 /* Itbl support may require additional care here. */
4961 /* Itbl support may require additional care here. */
4966 /* Itbl support may require additional care here. */
4971 /* Itbl support may require additional care here. */
4985 as_bad (_("opcode not supported on this processor"));
4989 /* Itbl support may require additional care here. */
4994 /* Itbl support may require additional care here. */
4999 /* Itbl support may require additional care here. */
5019 if (breg
== treg
|| coproc
|| lr
)
5041 /* Itbl support may require additional care here. */
5046 /* Itbl support may require additional care here. */
5051 /* Itbl support may require additional care here. */
5056 /* Itbl support may require additional care here. */
5074 as_bad (_("opcode not supported on this processor"));
5079 /* Itbl support may require additional care here. */
5083 /* Itbl support may require additional care here. */
5088 /* Itbl support may require additional care here. */
5100 /* Itbl support may require additional care here. */
5101 if (mask
== M_LWC1_AB
5102 || mask
== M_SWC1_AB
5103 || mask
== M_LDC1_AB
5104 || mask
== M_SDC1_AB
5113 if (offset_expr
.X_op
!= O_constant
5114 && offset_expr
.X_op
!= O_symbol
)
5116 as_bad (_("expression too complex"));
5117 offset_expr
.X_op
= O_constant
;
5120 /* A constant expression in PIC code can be handled just as it
5121 is in non PIC code. */
5122 if (mips_pic
== NO_PIC
5123 || offset_expr
.X_op
== O_constant
)
5125 /* If this is a reference to a GP relative symbol, and there
5126 is no base register, we want
5127 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5128 Otherwise, if there is no base register, we want
5129 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5130 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5131 If we have a constant, we need two instructions anyhow,
5132 so we always use the latter form.
5134 If we have a base register, and this is a reference to a
5135 GP relative symbol, we want
5136 addu $tempreg,$breg,$gp
5137 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5139 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5140 addu $tempreg,$tempreg,$breg
5141 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5142 With a constant we always use the latter case. */
5145 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5146 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5151 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5152 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5153 p
= frag_var (rs_machine_dependent
, 8, 0,
5154 RELAX_ENCODE (4, 8, 0, 4, 0,
5155 (mips_opts
.warn_about_macros
5157 && mips_opts
.noat
))),
5158 offset_expr
.X_add_symbol
, (offsetT
) 0,
5162 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5165 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5166 (int) BFD_RELOC_LO16
, tempreg
);
5170 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5171 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5176 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5177 ((bfd_arch_bits_per_address (stdoutput
) == 32
5178 || mips_opts
.isa
< 3)
5179 ? "addu" : "daddu"),
5180 "d,v,t", tempreg
, breg
, GP
);
5181 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5182 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5183 p
= frag_var (rs_machine_dependent
, 12, 0,
5184 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5185 offset_expr
.X_add_symbol
, (offsetT
) 0,
5188 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5191 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5192 ((bfd_arch_bits_per_address (stdoutput
) == 32
5193 || mips_opts
.isa
< 3)
5194 ? "addu" : "daddu"),
5195 "d,v,t", tempreg
, tempreg
, breg
);
5198 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5199 (int) BFD_RELOC_LO16
, tempreg
);
5202 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5204 /* If this is a reference to an external symbol, we want
5205 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5207 <op> $treg,0($tempreg)
5209 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5211 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5212 <op> $treg,0($tempreg)
5213 If there is a base register, we add it to $tempreg before
5214 the <op>. If there is a constant, we stick it in the
5215 <op> instruction. We don't handle constants larger than
5216 16 bits, because we have no way to load the upper 16 bits
5217 (actually, we could handle them for the subset of cases
5218 in which we are not using $at). */
5219 assert (offset_expr
.X_op
== O_symbol
);
5220 expr1
.X_add_number
= offset_expr
.X_add_number
;
5221 offset_expr
.X_add_number
= 0;
5222 if (expr1
.X_add_number
< -0x8000
5223 || expr1
.X_add_number
>= 0x8000)
5224 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5226 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5227 ((bfd_arch_bits_per_address (stdoutput
) == 32
5228 || mips_opts
.isa
< 3)
5230 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5231 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5232 p
= frag_var (rs_machine_dependent
, 4, 0,
5233 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5234 offset_expr
.X_add_symbol
, (offsetT
) 0,
5236 macro_build (p
, &icnt
, &offset_expr
,
5237 ((bfd_arch_bits_per_address (stdoutput
) == 32
5238 || mips_opts
.isa
< 3)
5239 ? "addiu" : "daddiu"),
5240 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5242 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5243 ((bfd_arch_bits_per_address (stdoutput
) == 32
5244 || mips_opts
.isa
< 3)
5245 ? "addu" : "daddu"),
5246 "d,v,t", tempreg
, tempreg
, breg
);
5247 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5248 (int) BFD_RELOC_LO16
, tempreg
);
5250 else if (mips_pic
== SVR4_PIC
)
5254 /* If this is a reference to an external symbol, we want
5255 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5256 addu $tempreg,$tempreg,$gp
5257 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5258 <op> $treg,0($tempreg)
5260 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5262 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5263 <op> $treg,0($tempreg)
5264 If there is a base register, we add it to $tempreg before
5265 the <op>. If there is a constant, we stick it in the
5266 <op> instruction. We don't handle constants larger than
5267 16 bits, because we have no way to load the upper 16 bits
5268 (actually, we could handle them for the subset of cases
5269 in which we are not using $at). */
5270 assert (offset_expr
.X_op
== O_symbol
);
5271 expr1
.X_add_number
= offset_expr
.X_add_number
;
5272 offset_expr
.X_add_number
= 0;
5273 if (expr1
.X_add_number
< -0x8000
5274 || expr1
.X_add_number
>= 0x8000)
5275 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5276 if (reg_needs_delay (GP
))
5281 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5282 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5283 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5284 ((bfd_arch_bits_per_address (stdoutput
) == 32
5285 || mips_opts
.isa
< 3)
5286 ? "addu" : "daddu"),
5287 "d,v,t", tempreg
, tempreg
, GP
);
5288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5289 ((bfd_arch_bits_per_address (stdoutput
) == 32
5290 || mips_opts
.isa
< 3)
5292 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5294 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5295 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5296 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5299 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5302 macro_build (p
, &icnt
, &offset_expr
,
5303 ((bfd_arch_bits_per_address (stdoutput
) == 32
5304 || mips_opts
.isa
< 3)
5306 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5308 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5310 macro_build (p
, &icnt
, &offset_expr
,
5311 ((bfd_arch_bits_per_address (stdoutput
) == 32
5312 || mips_opts
.isa
< 3)
5313 ? "addiu" : "daddiu"),
5314 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5317 ((bfd_arch_bits_per_address (stdoutput
) == 32
5318 || mips_opts
.isa
< 3)
5319 ? "addu" : "daddu"),
5320 "d,v,t", tempreg
, tempreg
, breg
);
5321 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5322 (int) BFD_RELOC_LO16
, tempreg
);
5324 else if (mips_pic
== EMBEDDED_PIC
)
5326 /* If there is no base register, we want
5327 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5328 If there is a base register, we want
5329 addu $tempreg,$breg,$gp
5330 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5332 assert (offset_expr
.X_op
== O_symbol
);
5335 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5336 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5341 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5342 ((bfd_arch_bits_per_address (stdoutput
) == 32
5343 || mips_opts
.isa
< 3)
5344 ? "addu" : "daddu"),
5345 "d,v,t", tempreg
, breg
, GP
);
5346 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5347 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5360 load_register (&icnt
, treg
, &imm_expr
, 0);
5364 load_register (&icnt
, treg
, &imm_expr
, 1);
5368 if (imm_expr
.X_op
== O_constant
)
5370 load_register (&icnt
, AT
, &imm_expr
, 0);
5371 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5372 "mtc1", "t,G", AT
, treg
);
5377 assert (offset_expr
.X_op
== O_symbol
5378 && strcmp (segment_name (S_GET_SEGMENT
5379 (offset_expr
.X_add_symbol
)),
5381 && offset_expr
.X_add_number
== 0);
5382 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5383 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5388 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5389 the entire value, and in mips1 mode it is the high order 32
5390 bits of the value and the low order 32 bits are either zero
5391 or in offset_expr. */
5392 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5394 if (mips_opts
.isa
>= 3)
5395 load_register (&icnt
, treg
, &imm_expr
, 1);
5400 if (target_big_endian
)
5412 load_register (&icnt
, hreg
, &imm_expr
, 0);
5415 if (offset_expr
.X_op
== O_absent
)
5416 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5420 assert (offset_expr
.X_op
== O_constant
);
5421 load_register (&icnt
, lreg
, &offset_expr
, 0);
5428 /* We know that sym is in the .rdata section. First we get the
5429 upper 16 bits of the address. */
5430 if (mips_pic
== NO_PIC
)
5432 /* FIXME: This won't work for a 64 bit address. */
5433 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5435 else if (mips_pic
== SVR4_PIC
)
5437 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5438 ((bfd_arch_bits_per_address (stdoutput
) == 32
5439 || mips_opts
.isa
< 3)
5441 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5443 else if (mips_pic
== EMBEDDED_PIC
)
5445 /* For embedded PIC we pick up the entire address off $gp in
5446 a single instruction. */
5447 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5448 ((bfd_arch_bits_per_address (stdoutput
) == 32
5449 || mips_opts
.isa
< 3)
5450 ? "addiu" : "daddiu"),
5451 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5452 offset_expr
.X_op
= O_constant
;
5453 offset_expr
.X_add_number
= 0;
5458 /* Now we load the register(s). */
5459 if (mips_opts
.isa
>= 3)
5460 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5461 treg
, (int) BFD_RELOC_LO16
, AT
);
5464 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5465 treg
, (int) BFD_RELOC_LO16
, AT
);
5468 /* FIXME: How in the world do we deal with the possible
5470 offset_expr
.X_add_number
+= 4;
5471 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5472 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5476 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5477 does not become a variant frag. */
5478 frag_wane (frag_now
);
5484 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5485 the entire value, and in mips1 mode it is the high order 32
5486 bits of the value and the low order 32 bits are either zero
5487 or in offset_expr. */
5488 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5490 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5491 if (mips_opts
.isa
>= 3)
5492 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5493 "dmtc1", "t,S", AT
, treg
);
5496 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5497 "mtc1", "t,G", AT
, treg
+ 1);
5498 if (offset_expr
.X_op
== O_absent
)
5499 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5500 "mtc1", "t,G", 0, treg
);
5503 assert (offset_expr
.X_op
== O_constant
);
5504 load_register (&icnt
, AT
, &offset_expr
, 0);
5505 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5506 "mtc1", "t,G", AT
, treg
);
5512 assert (offset_expr
.X_op
== O_symbol
5513 && offset_expr
.X_add_number
== 0);
5514 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5515 if (strcmp (s
, ".lit8") == 0)
5517 if (mips_opts
.isa
>= 2)
5519 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5520 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5524 r
= BFD_RELOC_MIPS_LITERAL
;
5529 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5530 if (mips_pic
== SVR4_PIC
)
5531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5532 ((bfd_arch_bits_per_address (stdoutput
) == 32
5533 || mips_opts
.isa
< 3)
5535 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5538 /* FIXME: This won't work for a 64 bit address. */
5539 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5542 if (mips_opts
.isa
>= 2)
5544 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5545 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5547 /* To avoid confusion in tc_gen_reloc, we must ensure
5548 that this does not become a variant frag. */
5549 frag_wane (frag_now
);
5562 as_bad (_("opcode not supported on this processor"));
5565 /* Even on a big endian machine $fn comes before $fn+1. We have
5566 to adjust when loading from memory. */
5569 assert (mips_opts
.isa
< 2);
5570 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5571 target_big_endian
? treg
+ 1 : treg
,
5573 /* FIXME: A possible overflow which I don't know how to deal
5575 offset_expr
.X_add_number
+= 4;
5576 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5577 target_big_endian
? treg
: treg
+ 1,
5580 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5581 does not become a variant frag. */
5582 frag_wane (frag_now
);
5591 * The MIPS assembler seems to check for X_add_number not
5592 * being double aligned and generating:
5595 * addiu at,at,%lo(foo+1)
5598 * But, the resulting address is the same after relocation so why
5599 * generate the extra instruction?
5603 as_bad (_("opcode not supported on this processor"));
5606 /* Itbl support may require additional care here. */
5608 if (mips_opts
.isa
>= 2)
5621 as_bad (_("opcode not supported on this processor"));
5625 if (mips_opts
.isa
>= 2)
5633 /* Itbl support may require additional care here. */
5638 if (mips_opts
.isa
>= 3)
5649 if (mips_opts
.isa
>= 3)
5659 if (offset_expr
.X_op
!= O_symbol
5660 && offset_expr
.X_op
!= O_constant
)
5662 as_bad (_("expression too complex"));
5663 offset_expr
.X_op
= O_constant
;
5666 /* Even on a big endian machine $fn comes before $fn+1. We have
5667 to adjust when loading from memory. We set coproc if we must
5668 load $fn+1 first. */
5669 /* Itbl support may require additional care here. */
5670 if (! target_big_endian
)
5673 if (mips_pic
== NO_PIC
5674 || offset_expr
.X_op
== O_constant
)
5676 /* If this is a reference to a GP relative symbol, we want
5677 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5678 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5679 If we have a base register, we use this
5681 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5682 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5683 If this is not a GP relative symbol, we want
5684 lui $at,<sym> (BFD_RELOC_HI16_S)
5685 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5686 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5687 If there is a base register, we add it to $at after the
5688 lui instruction. If there is a constant, we always use
5690 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5691 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5710 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5711 ((bfd_arch_bits_per_address (stdoutput
) == 32
5712 || mips_opts
.isa
< 3)
5713 ? "addu" : "daddu"),
5714 "d,v,t", AT
, breg
, GP
);
5720 /* Itbl support may require additional care here. */
5721 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5722 coproc
? treg
+ 1 : treg
,
5723 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5724 offset_expr
.X_add_number
+= 4;
5726 /* Set mips_optimize to 2 to avoid inserting an
5728 hold_mips_optimize
= mips_optimize
;
5730 /* Itbl support may require additional care here. */
5731 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5732 coproc
? treg
: treg
+ 1,
5733 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5734 mips_optimize
= hold_mips_optimize
;
5736 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5737 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5738 used_at
&& mips_opts
.noat
),
5739 offset_expr
.X_add_symbol
, (offsetT
) 0,
5742 /* We just generated two relocs. When tc_gen_reloc
5743 handles this case, it will skip the first reloc and
5744 handle the second. The second reloc already has an
5745 extra addend of 4, which we added above. We must
5746 subtract it out, and then subtract another 4 to make
5747 the first reloc come out right. The second reloc
5748 will come out right because we are going to add 4 to
5749 offset_expr when we build its instruction below.
5751 If we have a symbol, then we don't want to include
5752 the offset, because it will wind up being included
5753 when we generate the reloc. */
5755 if (offset_expr
.X_op
== O_constant
)
5756 offset_expr
.X_add_number
-= 8;
5759 offset_expr
.X_add_number
= -4;
5760 offset_expr
.X_op
= O_constant
;
5763 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5768 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5769 ((bfd_arch_bits_per_address (stdoutput
) == 32
5770 || mips_opts
.isa
< 3)
5771 ? "addu" : "daddu"),
5772 "d,v,t", AT
, breg
, AT
);
5776 /* Itbl support may require additional care here. */
5777 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5778 coproc
? treg
+ 1 : treg
,
5779 (int) BFD_RELOC_LO16
, AT
);
5782 /* FIXME: How do we handle overflow here? */
5783 offset_expr
.X_add_number
+= 4;
5784 /* Itbl support may require additional care here. */
5785 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5786 coproc
? treg
: treg
+ 1,
5787 (int) BFD_RELOC_LO16
, AT
);
5789 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5793 /* If this is a reference to an external symbol, we want
5794 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5799 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5801 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5802 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5803 If there is a base register we add it to $at before the
5804 lwc1 instructions. If there is a constant we include it
5805 in the lwc1 instructions. */
5807 expr1
.X_add_number
= offset_expr
.X_add_number
;
5808 offset_expr
.X_add_number
= 0;
5809 if (expr1
.X_add_number
< -0x8000
5810 || expr1
.X_add_number
>= 0x8000 - 4)
5811 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5816 frag_grow (24 + off
);
5817 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5818 ((bfd_arch_bits_per_address (stdoutput
) == 32
5819 || mips_opts
.isa
< 3)
5821 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5822 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5824 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5825 ((bfd_arch_bits_per_address (stdoutput
) == 32
5826 || mips_opts
.isa
< 3)
5827 ? "addu" : "daddu"),
5828 "d,v,t", AT
, breg
, AT
);
5829 /* Itbl support may require additional care here. */
5830 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5831 coproc
? treg
+ 1 : treg
,
5832 (int) BFD_RELOC_LO16
, AT
);
5833 expr1
.X_add_number
+= 4;
5835 /* Set mips_optimize to 2 to avoid inserting an undesired
5837 hold_mips_optimize
= mips_optimize
;
5839 /* Itbl support may require additional care here. */
5840 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5841 coproc
? treg
: treg
+ 1,
5842 (int) BFD_RELOC_LO16
, AT
);
5843 mips_optimize
= hold_mips_optimize
;
5845 (void) frag_var (rs_machine_dependent
, 0, 0,
5846 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5847 offset_expr
.X_add_symbol
, (offsetT
) 0,
5850 else if (mips_pic
== SVR4_PIC
)
5854 /* If this is a reference to an external symbol, we want
5855 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5857 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5862 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5864 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5865 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5866 If there is a base register we add it to $at before the
5867 lwc1 instructions. If there is a constant we include it
5868 in the lwc1 instructions. */
5870 expr1
.X_add_number
= offset_expr
.X_add_number
;
5871 offset_expr
.X_add_number
= 0;
5872 if (expr1
.X_add_number
< -0x8000
5873 || expr1
.X_add_number
>= 0x8000 - 4)
5874 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5875 if (reg_needs_delay (GP
))
5884 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5885 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5886 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5887 ((bfd_arch_bits_per_address (stdoutput
) == 32
5888 || mips_opts
.isa
< 3)
5889 ? "addu" : "daddu"),
5890 "d,v,t", AT
, AT
, GP
);
5891 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5892 ((bfd_arch_bits_per_address (stdoutput
) == 32
5893 || mips_opts
.isa
< 3)
5895 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5896 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5898 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5899 ((bfd_arch_bits_per_address (stdoutput
) == 32
5900 || mips_opts
.isa
< 3)
5901 ? "addu" : "daddu"),
5902 "d,v,t", AT
, breg
, AT
);
5903 /* Itbl support may require additional care here. */
5904 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5905 coproc
? treg
+ 1 : treg
,
5906 (int) BFD_RELOC_LO16
, AT
);
5907 expr1
.X_add_number
+= 4;
5909 /* Set mips_optimize to 2 to avoid inserting an undesired
5911 hold_mips_optimize
= mips_optimize
;
5913 /* Itbl support may require additional care here. */
5914 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5915 coproc
? treg
: treg
+ 1,
5916 (int) BFD_RELOC_LO16
, AT
);
5917 mips_optimize
= hold_mips_optimize
;
5918 expr1
.X_add_number
-= 4;
5920 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5921 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5922 8 + gpdel
+ off
, 1, 0),
5923 offset_expr
.X_add_symbol
, (offsetT
) 0,
5927 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5930 macro_build (p
, &icnt
, &offset_expr
,
5931 ((bfd_arch_bits_per_address (stdoutput
) == 32
5932 || mips_opts
.isa
< 3)
5934 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5936 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5940 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5941 ((bfd_arch_bits_per_address (stdoutput
) == 32
5942 || mips_opts
.isa
< 3)
5943 ? "addu" : "daddu"),
5944 "d,v,t", AT
, breg
, AT
);
5947 /* Itbl support may require additional care here. */
5948 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5949 coproc
? treg
+ 1 : treg
,
5950 (int) BFD_RELOC_LO16
, AT
);
5952 expr1
.X_add_number
+= 4;
5954 /* Set mips_optimize to 2 to avoid inserting an undesired
5956 hold_mips_optimize
= mips_optimize
;
5958 /* Itbl support may require additional care here. */
5959 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5960 coproc
? treg
: treg
+ 1,
5961 (int) BFD_RELOC_LO16
, AT
);
5962 mips_optimize
= hold_mips_optimize
;
5964 else if (mips_pic
== EMBEDDED_PIC
)
5966 /* If there is no base register, we use
5967 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5968 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5969 If we have a base register, we use
5971 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5972 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5981 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5982 ((bfd_arch_bits_per_address (stdoutput
) == 32
5983 || mips_opts
.isa
< 3)
5984 ? "addu" : "daddu"),
5985 "d,v,t", AT
, breg
, GP
);
5990 /* Itbl support may require additional care here. */
5991 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5992 coproc
? treg
+ 1 : treg
,
5993 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5994 offset_expr
.X_add_number
+= 4;
5995 /* Itbl support may require additional care here. */
5996 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5997 coproc
? treg
: treg
+ 1,
5998 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
6014 assert (bfd_arch_bits_per_address (stdoutput
) == 32 || mips_opts
.isa
< 3);
6015 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6016 (int) BFD_RELOC_LO16
, breg
);
6017 offset_expr
.X_add_number
+= 4;
6018 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
6019 (int) BFD_RELOC_LO16
, breg
);
6022 /* New code added to support COPZ instructions.
6023 This code builds table entries out of the macros in mip_opcodes.
6024 R4000 uses interlocks to handle coproc delays.
6025 Other chips (like the R3000) require nops to be inserted for delays.
6027 FIXME: Currently, we require that the user handle delays.
6028 In order to fill delay slots for non-interlocked chips,
6029 we must have a way to specify delays based on the coprocessor.
6030 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6031 What are the side-effects of the cop instruction?
6032 What cache support might we have and what are its effects?
6033 Both coprocessor & memory require delays. how long???
6034 What registers are read/set/modified?
6036 If an itbl is provided to interpret cop instructions,
6037 this knowledge can be encoded in the itbl spec. */
6051 /* For now we just do C (same as Cz). The parameter will be
6052 stored in insn_opcode by mips_ip. */
6053 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
6057 #ifdef LOSING_COMPILER
6059 /* Try and see if this is a new itbl instruction.
6060 This code builds table entries out of the macros in mip_opcodes.
6061 FIXME: For now we just assemble the expression and pass it's
6062 value along as a 32-bit immediate.
6063 We may want to have the assembler assemble this value,
6064 so that we gain the assembler's knowledge of delay slots,
6066 Would it be more efficient to use mask (id) here? */
6067 if (itbl_have_entries
6068 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6070 s
= ip
->insn_mo
->name
;
6072 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6073 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
6080 as_warn (_("Macro used $at after \".set noat\""));
6085 struct mips_cl_insn
*ip
;
6087 register int treg
, sreg
, dreg
, breg
;
6103 bfd_reloc_code_real_type r
;
6106 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6107 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6108 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6109 mask
= ip
->insn_mo
->mask
;
6111 expr1
.X_op
= O_constant
;
6112 expr1
.X_op_symbol
= NULL
;
6113 expr1
.X_add_symbol
= NULL
;
6114 expr1
.X_add_number
= 1;
6118 #endif /* LOSING_COMPILER */
6123 macro_build ((char *) NULL
, &icnt
, NULL
,
6124 dbl
? "dmultu" : "multu",
6126 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6132 /* The MIPS assembler some times generates shifts and adds. I'm
6133 not trying to be that fancy. GCC should do this for us
6135 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6136 macro_build ((char *) NULL
, &icnt
, NULL
,
6137 dbl
? "dmult" : "mult",
6139 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6152 mips_emit_delays (true);
6153 ++mips_opts
.noreorder
;
6154 mips_any_noreorder
= 1;
6156 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6157 macro_build ((char *) NULL
, &icnt
, NULL
,
6158 dbl
? "dmult" : "mult",
6159 "s,t", sreg
, imm
? AT
: treg
);
6160 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6161 macro_build ((char *) NULL
, &icnt
, NULL
,
6162 dbl
? "dsra32" : "sra",
6163 "d,w,<", dreg
, dreg
, 31);
6164 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6166 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6169 expr1
.X_add_number
= 8;
6170 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6171 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6172 /* start-sanitize-r5900 */
6174 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
6176 /* end-sanitize-r5900 */
6177 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6179 --mips_opts
.noreorder
;
6180 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6193 mips_emit_delays (true);
6194 ++mips_opts
.noreorder
;
6195 mips_any_noreorder
= 1;
6197 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6198 macro_build ((char *) NULL
, &icnt
, NULL
,
6199 dbl
? "dmultu" : "multu",
6200 "s,t", sreg
, imm
? AT
: treg
);
6201 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6202 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6204 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6207 expr1
.X_add_number
= 8;
6208 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6209 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6210 /* start-sanitize-r5900 */
6212 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 6);
6214 /* end-sanitize-r5900 */
6215 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6217 --mips_opts
.noreorder
;
6221 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6222 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6223 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6225 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6229 if (imm_expr
.X_op
!= O_constant
)
6230 as_bad (_("rotate count too large"));
6231 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6232 (int) (imm_expr
.X_add_number
& 0x1f));
6233 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6234 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6235 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6239 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6240 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6241 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6243 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6247 if (imm_expr
.X_op
!= O_constant
)
6248 as_bad (_("rotate count too large"));
6249 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6250 (int) (imm_expr
.X_add_number
& 0x1f));
6251 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6252 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6253 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6259 as_bad (_("opcode not supported on this processor"));
6262 assert (mips_opts
.isa
< 2);
6263 /* Even on a big endian machine $fn comes before $fn+1. We have
6264 to adjust when storing to memory. */
6265 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6266 target_big_endian
? treg
+ 1 : treg
,
6267 (int) BFD_RELOC_LO16
, breg
);
6268 offset_expr
.X_add_number
+= 4;
6269 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6270 target_big_endian
? treg
: treg
+ 1,
6271 (int) BFD_RELOC_LO16
, breg
);
6276 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6277 treg
, (int) BFD_RELOC_LO16
);
6279 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6280 sreg
, (int) BFD_RELOC_LO16
);
6283 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6285 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6286 dreg
, (int) BFD_RELOC_LO16
);
6291 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6293 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6294 sreg
, (int) BFD_RELOC_LO16
);
6299 as_warn (_("Instruction %s: result is always false"),
6301 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6304 if (imm_expr
.X_op
== O_constant
6305 && imm_expr
.X_add_number
>= 0
6306 && imm_expr
.X_add_number
< 0x10000)
6308 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6309 sreg
, (int) BFD_RELOC_LO16
);
6312 else if (imm_expr
.X_op
== O_constant
6313 && imm_expr
.X_add_number
> -0x8000
6314 && imm_expr
.X_add_number
< 0)
6316 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6317 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6318 ((bfd_arch_bits_per_address (stdoutput
) == 32
6319 || mips_opts
.isa
< 3)
6320 ? "addiu" : "daddiu"),
6321 "t,r,j", dreg
, sreg
,
6322 (int) BFD_RELOC_LO16
);
6327 load_register (&icnt
, AT
, &imm_expr
, 0);
6328 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6332 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6333 (int) BFD_RELOC_LO16
);
6338 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6344 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6345 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6346 (int) BFD_RELOC_LO16
);
6349 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6351 if (imm_expr
.X_op
== O_constant
6352 && imm_expr
.X_add_number
>= -0x8000
6353 && imm_expr
.X_add_number
< 0x8000)
6355 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6356 mask
== M_SGE_I
? "slti" : "sltiu",
6357 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6362 load_register (&icnt
, AT
, &imm_expr
, 0);
6363 macro_build ((char *) NULL
, &icnt
, NULL
,
6364 mask
== M_SGE_I
? "slt" : "sltu",
6365 "d,v,t", dreg
, sreg
, AT
);
6368 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6369 (int) BFD_RELOC_LO16
);
6374 case M_SGT
: /* sreg > treg <==> treg < sreg */
6380 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6383 case M_SGT_I
: /* sreg > I <==> I < sreg */
6389 load_register (&icnt
, AT
, &imm_expr
, 0);
6390 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6393 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6399 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6400 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6401 (int) BFD_RELOC_LO16
);
6404 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6410 load_register (&icnt
, AT
, &imm_expr
, 0);
6411 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6412 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6413 (int) BFD_RELOC_LO16
);
6417 if (imm_expr
.X_op
== O_constant
6418 && imm_expr
.X_add_number
>= -0x8000
6419 && imm_expr
.X_add_number
< 0x8000)
6421 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6422 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6425 load_register (&icnt
, AT
, &imm_expr
, 0);
6426 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6430 if (imm_expr
.X_op
== O_constant
6431 && imm_expr
.X_add_number
>= -0x8000
6432 && imm_expr
.X_add_number
< 0x8000)
6434 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6435 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6438 load_register (&icnt
, AT
, &imm_expr
, 0);
6439 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6445 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6448 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6452 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6454 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6460 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6462 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6468 as_warn (_("Instruction %s: result is always true"),
6470 macro_build ((char *) NULL
, &icnt
, &expr1
,
6471 ((bfd_arch_bits_per_address (stdoutput
) == 32
6472 || mips_opts
.isa
< 3)
6473 ? "addiu" : "daddiu"),
6474 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6477 if (imm_expr
.X_op
== O_constant
6478 && imm_expr
.X_add_number
>= 0
6479 && imm_expr
.X_add_number
< 0x10000)
6481 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6482 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6485 else if (imm_expr
.X_op
== O_constant
6486 && imm_expr
.X_add_number
> -0x8000
6487 && imm_expr
.X_add_number
< 0)
6489 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6490 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6491 ((bfd_arch_bits_per_address (stdoutput
) == 32
6492 || mips_opts
.isa
< 3)
6493 ? "addiu" : "daddiu"),
6494 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6499 load_register (&icnt
, AT
, &imm_expr
, 0);
6500 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6504 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6512 if (imm_expr
.X_op
== O_constant
6513 && imm_expr
.X_add_number
> -0x8000
6514 && imm_expr
.X_add_number
<= 0x8000)
6516 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6517 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6518 dbl
? "daddi" : "addi",
6519 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6522 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6523 macro_build ((char *) NULL
, &icnt
, NULL
,
6524 dbl
? "dsub" : "sub",
6525 "d,v,t", dreg
, sreg
, AT
);
6531 if (imm_expr
.X_op
== O_constant
6532 && imm_expr
.X_add_number
> -0x8000
6533 && imm_expr
.X_add_number
<= 0x8000)
6535 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6536 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6537 dbl
? "daddiu" : "addiu",
6538 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6541 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6542 macro_build ((char *) NULL
, &icnt
, NULL
,
6543 dbl
? "dsubu" : "subu",
6544 "d,v,t", dreg
, sreg
, AT
);
6565 load_register (&icnt
, AT
, &imm_expr
, 0);
6566 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6571 assert (mips_opts
.isa
< 2);
6572 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6573 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6576 * Is the double cfc1 instruction a bug in the mips assembler;
6577 * or is there a reason for it?
6579 mips_emit_delays (true);
6580 ++mips_opts
.noreorder
;
6581 mips_any_noreorder
= 1;
6582 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6583 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6584 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6585 expr1
.X_add_number
= 3;
6586 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6587 (int) BFD_RELOC_LO16
);
6588 expr1
.X_add_number
= 2;
6589 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6590 (int) BFD_RELOC_LO16
);
6591 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6592 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6593 macro_build ((char *) NULL
, &icnt
, NULL
,
6594 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6595 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6596 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6597 --mips_opts
.noreorder
;
6606 if (offset_expr
.X_add_number
>= 0x7fff)
6607 as_bad (_("operand overflow"));
6608 /* avoid load delay */
6609 if (! target_big_endian
)
6610 offset_expr
.X_add_number
+= 1;
6611 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6612 (int) BFD_RELOC_LO16
, breg
);
6613 if (! target_big_endian
)
6614 offset_expr
.X_add_number
-= 1;
6616 offset_expr
.X_add_number
+= 1;
6617 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6618 (int) BFD_RELOC_LO16
, breg
);
6619 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6620 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6633 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6634 as_bad (_("operand overflow"));
6635 if (! target_big_endian
)
6636 offset_expr
.X_add_number
+= off
;
6637 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6638 (int) BFD_RELOC_LO16
, breg
);
6639 if (! target_big_endian
)
6640 offset_expr
.X_add_number
-= off
;
6642 offset_expr
.X_add_number
+= off
;
6643 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6644 (int) BFD_RELOC_LO16
, breg
);
6657 load_address (&icnt
, AT
, &offset_expr
);
6659 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6660 ((bfd_arch_bits_per_address (stdoutput
) == 32
6661 || mips_opts
.isa
< 3)
6662 ? "addu" : "daddu"),
6663 "d,v,t", AT
, AT
, breg
);
6664 if (! target_big_endian
)
6665 expr1
.X_add_number
= off
;
6667 expr1
.X_add_number
= 0;
6668 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6669 (int) BFD_RELOC_LO16
, AT
);
6670 if (! target_big_endian
)
6671 expr1
.X_add_number
= 0;
6673 expr1
.X_add_number
= off
;
6674 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6675 (int) BFD_RELOC_LO16
, AT
);
6680 load_address (&icnt
, AT
, &offset_expr
);
6682 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6683 ((bfd_arch_bits_per_address (stdoutput
) == 32
6684 || mips_opts
.isa
< 3)
6685 ? "addu" : "daddu"),
6686 "d,v,t", AT
, AT
, breg
);
6687 if (target_big_endian
)
6688 expr1
.X_add_number
= 0;
6689 macro_build ((char *) NULL
, &icnt
, &expr1
,
6690 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6691 (int) BFD_RELOC_LO16
, AT
);
6692 if (target_big_endian
)
6693 expr1
.X_add_number
= 1;
6695 expr1
.X_add_number
= 0;
6696 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6697 (int) BFD_RELOC_LO16
, AT
);
6698 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6700 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6705 if (offset_expr
.X_add_number
>= 0x7fff)
6706 as_bad (_("operand overflow"));
6707 if (target_big_endian
)
6708 offset_expr
.X_add_number
+= 1;
6709 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6710 (int) BFD_RELOC_LO16
, breg
);
6711 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6712 if (target_big_endian
)
6713 offset_expr
.X_add_number
-= 1;
6715 offset_expr
.X_add_number
+= 1;
6716 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6717 (int) BFD_RELOC_LO16
, breg
);
6730 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6731 as_bad (_("operand overflow"));
6732 if (! target_big_endian
)
6733 offset_expr
.X_add_number
+= off
;
6734 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6735 (int) BFD_RELOC_LO16
, breg
);
6736 if (! target_big_endian
)
6737 offset_expr
.X_add_number
-= off
;
6739 offset_expr
.X_add_number
+= off
;
6740 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6741 (int) BFD_RELOC_LO16
, breg
);
6754 load_address (&icnt
, AT
, &offset_expr
);
6756 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6757 ((bfd_arch_bits_per_address (stdoutput
) == 32
6758 || mips_opts
.isa
< 3)
6759 ? "addu" : "daddu"),
6760 "d,v,t", AT
, AT
, breg
);
6761 if (! target_big_endian
)
6762 expr1
.X_add_number
= off
;
6764 expr1
.X_add_number
= 0;
6765 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6766 (int) BFD_RELOC_LO16
, AT
);
6767 if (! target_big_endian
)
6768 expr1
.X_add_number
= 0;
6770 expr1
.X_add_number
= off
;
6771 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6772 (int) BFD_RELOC_LO16
, AT
);
6776 load_address (&icnt
, AT
, &offset_expr
);
6778 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6779 ((bfd_arch_bits_per_address (stdoutput
) == 32
6780 || mips_opts
.isa
< 3)
6781 ? "addu" : "daddu"),
6782 "d,v,t", AT
, AT
, breg
);
6783 if (! target_big_endian
)
6784 expr1
.X_add_number
= 0;
6785 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6786 (int) BFD_RELOC_LO16
, AT
);
6787 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6789 if (! target_big_endian
)
6790 expr1
.X_add_number
= 1;
6792 expr1
.X_add_number
= 0;
6793 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6794 (int) BFD_RELOC_LO16
, AT
);
6795 if (! target_big_endian
)
6796 expr1
.X_add_number
= 0;
6798 expr1
.X_add_number
= 1;
6799 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6800 (int) BFD_RELOC_LO16
, AT
);
6801 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6803 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6808 /* FIXME: Check if this is one of the itbl macros, since they
6809 are added dynamically. */
6810 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6814 as_warn (_("Macro used $at after \".set noat\""));
6817 /* Implement macros in mips16 mode. */
6821 struct mips_cl_insn
*ip
;
6824 int xreg
, yreg
, zreg
, tmp
;
6828 const char *s
, *s2
, *s3
;
6830 mask
= ip
->insn_mo
->mask
;
6832 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6833 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6834 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6838 expr1
.X_op
= O_constant
;
6839 expr1
.X_op_symbol
= NULL
;
6840 expr1
.X_add_symbol
= NULL
;
6841 expr1
.X_add_number
= 1;
6860 mips_emit_delays (true);
6861 ++mips_opts
.noreorder
;
6862 mips_any_noreorder
= 1;
6863 macro_build ((char *) NULL
, &icnt
, NULL
,
6864 dbl
? "ddiv" : "div",
6865 "0,x,y", xreg
, yreg
);
6866 expr1
.X_add_number
= 2;
6867 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6868 /* start-sanitize-r5900 */
6870 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
6872 /* end-sanitize-r5900 */
6873 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6875 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6876 since that causes an overflow. We should do that as well,
6877 but I don't see how to do the comparisons without a temporary
6879 --mips_opts
.noreorder
;
6880 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6899 mips_emit_delays (true);
6900 ++mips_opts
.noreorder
;
6901 mips_any_noreorder
= 1;
6902 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6903 expr1
.X_add_number
= 2;
6904 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6905 /* start-sanitize-r5900 */
6907 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "B", 7);
6909 /* end-sanitize-r5900 */
6910 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6911 --mips_opts
.noreorder
;
6912 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6918 macro_build ((char *) NULL
, &icnt
, NULL
,
6919 dbl
? "dmultu" : "multu",
6921 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6929 if (imm_expr
.X_op
!= O_constant
)
6930 as_bad (_("Unsupported large constant"));
6931 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6932 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6933 dbl
? "daddiu" : "addiu",
6934 "y,x,4", yreg
, xreg
);
6938 if (imm_expr
.X_op
!= O_constant
)
6939 as_bad (_("Unsupported large constant"));
6940 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6941 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6946 if (imm_expr
.X_op
!= O_constant
)
6947 as_bad (_("Unsupported large constant"));
6948 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6949 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6972 goto do_reverse_branch
;
6976 goto do_reverse_branch
;
6988 goto do_reverse_branch
;
6999 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
7001 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7028 goto do_addone_branch_i
;
7033 goto do_addone_branch_i
;
7048 goto do_addone_branch_i
;
7055 if (imm_expr
.X_op
!= O_constant
)
7056 as_bad (_("Unsupported large constant"));
7057 ++imm_expr
.X_add_number
;
7060 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
7061 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
7065 expr1
.X_add_number
= 0;
7066 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
7068 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7069 "move", "y,X", xreg
, yreg
);
7070 expr1
.X_add_number
= 2;
7071 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
7072 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7073 "neg", "x,w", xreg
, xreg
);
7077 /* For consistency checking, verify that all bits are specified either
7078 by the match/mask part of the instruction definition, or by the
7081 validate_mips_insn (opc
)
7082 const struct mips_opcode
*opc
;
7084 const char *p
= opc
->args
;
7086 unsigned long used_bits
= opc
->mask
;
7088 if ((used_bits
& opc
->match
) != opc
->match
)
7090 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7091 opc
->name
, opc
->args
);
7094 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7101 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7102 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7104 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
7105 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7106 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7107 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7109 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7112 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7113 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7114 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7115 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7116 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7117 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7118 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7119 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7120 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7121 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7122 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7124 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7125 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7126 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7127 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7129 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7130 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7131 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7132 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7133 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7134 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7135 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7136 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7137 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7140 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7141 /* start-sanitize-r5900 */
7142 case '0': USE_BITS (OP_MASK_VADDI
, OP_SH_VADDI
); break;
7143 case '1': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
7144 case '2': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
7145 case '3': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
7146 case '4': USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
); break;
7147 case '5': USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
); break;
7148 case '6': USE_BITS (OP_MASK_VUDREG
, OP_SH_VUDREG
); break;
7150 USE_BITS (OP_MASK_VUTREG
, OP_SH_VUTREG
);
7151 USE_BITS (OP_MASK_VUFTF
, OP_SH_VUFTF
);
7154 USE_BITS (OP_MASK_VUSREG
, OP_SH_VUSREG
);
7155 USE_BITS (OP_MASK_VUFSF
, OP_SH_VUFSF
);
7163 case 'O': USE_BITS (OP_MASK_VUCALLMS
, OP_SH_VUCALLMS
);break;
7164 case '&': USE_BITS (OP_MASK_VUDEST
, OP_SH_VUDEST
); break;
7171 /* end-sanitize-r5900 */
7172 /* start-sanitize-cygnus */
7173 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7174 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7177 /* end-sanitize-cygnus */
7179 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7180 c
, opc
->name
, opc
->args
);
7184 if (used_bits
!= 0xffffffff)
7186 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7187 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7193 /* This routine assembles an instruction into its binary format. As a
7194 side effect, it sets one of the global variables imm_reloc or
7195 offset_reloc to the type of relocation to do if one of the operands
7196 is an address expression. */
7201 struct mips_cl_insn
*ip
;
7206 struct mips_opcode
*insn
;
7209 unsigned int lastregno
= 0;
7212 int full_opcode_match
= 1;
7216 /* If the instruction contains a '.', we first try to match an instruction
7217 including the '.'. Then we try again without the '.'. */
7219 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
7222 /* If we stopped on whitespace, then replace the whitespace with null for
7223 the call to hash_find. Save the character we replaced just in case we
7224 have to re-parse the instruction. */
7231 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7233 /* If we didn't find the instruction in the opcode table, try again, but
7234 this time with just the instruction up to, but not including the
7238 /* Restore the character we overwrite above (if any). */
7242 /* Scan up to the first '.' or whitespace. */
7243 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace (*s
); ++s
)
7246 /* If we did not find a '.', then we can quit now. */
7249 insn_error
= "unrecognized opcode";
7253 /* Lookup the instruction in the hash table. */
7255 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7257 insn_error
= "unrecognized opcode";
7261 full_opcode_match
= 0;
7270 assert (strcmp (insn
->name
, str
) == 0);
7272 if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
7274 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
7276 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
7278 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
7283 if (insn_isa
<= mips_opts
.isa
)
7285 else if (insn
->pinfo
== INSN_MACRO
)
7287 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
7288 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
7289 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
7290 /* start-sanitize-vr4xxx */
7291 || (mips_4121
&& (insn
->membership
& INSN_4121
) != 0)
7292 /* end-sanitize-vr4xxx */
7293 /* start-sanitize-vr4320 */
7294 || (mips_4320
&& (insn
->membership
& INSN_4320
) != 0)
7295 /* end-sanitize-vr4320 */
7296 /* start-sanitize-tx49 */
7297 || (mips_4900
&& (insn
->membership
& INSN_4900
) != 0)
7298 /* end-sanitize-tx49 */
7299 /* start-sanitize-r5900 */
7300 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
7301 /* end-sanitize-r5900 */
7302 /* start-sanitize-cygnus */
7303 || (mips_5400
&& (insn
->membership
& INSN_5400
) != 0)
7304 /* end-sanitize-cygnus */
7305 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
7310 if (insn
->pinfo
!= INSN_MACRO
)
7312 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
7314 /* start-sanitize-r5900 */
7315 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
7317 /* end-sanitize-r5900 */
7322 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7323 && strcmp (insn
->name
, insn
[1].name
) == 0)
7329 || insn_isa
<= mips_opts
.isa
)
7330 insn_error
= _("opcode not supported on this processor");
7333 static char buf
[100];
7335 sprintf (buf
, _("opcode requires -mips%d or greater"), insn_isa
);
7342 ip
->insn_opcode
= insn
->match
;
7343 for (args
= insn
->args
;; ++args
)
7349 case '\0': /* end of args */
7362 ip
->insn_opcode
|= lastregno
<< 21;
7367 ip
->insn_opcode
|= lastregno
<< 16;
7371 ip
->insn_opcode
|= lastregno
<< 11;
7377 /* Handle optional base register.
7378 Either the base register is omitted or
7379 we must have a left paren. */
7380 /* This is dependent on the next operand specifier
7381 is a base register specification. */
7382 assert (args
[1] == 'b' || args
[1] == '5'
7383 || args
[1] == '-' || args
[1] == '4');
7387 case ')': /* these must match exactly */
7388 /* start-sanitize-cygnus */
7391 /* end-sanitize-cygnus */
7392 /* start-sanitize-r5900 */
7395 /* end-sanitize-r5900 */
7400 case '<': /* must be at least one digit */
7402 * According to the manual, if the shift amount is greater
7403 * than 31 or less than 0 the the shift amount should be
7404 * mod 32. In reality the mips assembler issues an error.
7405 * We issue a warning and mask out all but the low 5 bits.
7407 my_getExpression (&imm_expr
, s
);
7408 check_absolute_expr (ip
, &imm_expr
);
7409 if ((unsigned long) imm_expr
.X_add_number
> 31)
7411 as_warn (_("Improper shift amount (%ld)"),
7412 (long) imm_expr
.X_add_number
);
7413 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7415 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7416 imm_expr
.X_op
= O_absent
;
7420 case '>': /* shift amount minus 32 */
7421 my_getExpression (&imm_expr
, s
);
7422 check_absolute_expr (ip
, &imm_expr
);
7423 if ((unsigned long) imm_expr
.X_add_number
< 32
7424 || (unsigned long) imm_expr
.X_add_number
> 63)
7426 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7427 imm_expr
.X_op
= O_absent
;
7431 /* start-sanitize-r5900 */
7432 case '0': /* 5 bit signed immediate at 6 */
7433 my_getExpression (&imm_expr
, s
);
7434 check_absolute_expr (ip
, &imm_expr
);
7435 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7436 || ((imm_expr
.X_add_number
< -16
7437 || imm_expr
.X_add_number
>= 16)
7438 && imm_expr
.X_op
== O_constant
))
7440 if (imm_expr
.X_op
!= O_constant
7441 && imm_expr
.X_op
!= O_big
)
7442 insn_error
= "absolute expression required";
7444 as_bad (_("5 bit expression not in range -16..15"));
7446 ip
->insn_opcode
|= (imm_expr
.X_add_number
) << 6;
7447 imm_expr
.X_op
= O_absent
;
7451 case '9': /* vi27 for vcallmsr */
7452 if (strncmp (s
, "$vi27", 5) == 0)
7454 else if (strncmp (s
, "vi27", 4) == 0)
7457 as_bad (_("expected vi27"));
7460 case '#': /* escape character */
7461 /* '#' specifies that we've got an optional suffix to this
7462 operand that must match exactly (if it exists). */
7463 if (*s
!= '\0' && *s
!= ','
7464 && *s
!= ' ' && *s
!= '\t' && *s
!= '\n')
7466 if (*s
== *(args
+ 1))
7477 case 'K': /* DEST operand completer (optional), must
7478 match previous dest if specified. */
7479 case '&': /* DEST instruction completer */
7480 case ';': /* DEST instruction completer, must be xyz */
7487 /* Parse the completer. */
7489 while ((!full_opcode_match
|| *args
== 'K')
7490 && *s
!= '\0' && *s
!= ' ' && *s
!= ',')
7502 insn_error
= "Invalid dest specification";
7511 /* Each completer can only appear once. */
7512 if (w
> 1 || x
> 1 || y
> 1 || z
> 1)
7514 insn_error
= "Invalid dest specification";
7518 /* If this is the opcode completer, then we must insert
7519 the appropriate value into the insn. */
7522 /* Not strictly in the specs, but requested by users. */
7523 if (w
== 0 && x
== 0 && y
== 0 && z
== 0)
7526 ip
->insn_opcode
|= ((w
<< 21) | (x
<< 24)
7527 | (y
<< 23) | (z
<< 22));
7528 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7530 else if (*args
== ';')
7532 /* This implicitly has the .xyz completer. */
7533 if (w
== 0 && x
== 0 && y
== 0 && z
== 0)
7536 if (w
!= 0 || x
!= 1 || y
!= 1 || z
!= 1)
7538 insn_error
= "Invalid dest specification";
7542 last_h
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7548 /* This is the operand completer, make sure it matches
7549 the previous opcode completer. */
7550 temp
= (w
<< 3) | (x
<< 0) | (y
<< 1) | (z
<< 2);
7551 if (temp
&& temp
!= last_h
)
7553 insn_error
= "DEST field in operand does not match DEST field in instruction";
7562 case 'J': /* vu0 I register */
7566 insn_error
= "operand `I' expected";
7569 case 'Q': /* vu0 Q register */
7573 insn_error
= "operand `Q' expected";
7576 case 'X': /* vu0 R register */
7580 insn_error
= "operand `R' expected";
7583 case 'U': /* vu0 ACC register */
7584 if (s
[0] == 'A' && s
[1] == 'C' && s
[2] == 'C')
7587 insn_error
= "operand `ACC' expected";
7591 my_getSmallExpression (&imm_expr
, s
);
7592 imm_reloc
= BFD_RELOC_MIPS15_S3
;
7595 /* end-sanitize-r5900 */
7597 case 'k': /* cache code */
7598 case 'h': /* prefx code */
7599 my_getExpression (&imm_expr
, s
);
7600 check_absolute_expr (ip
, &imm_expr
);
7601 if ((unsigned long) imm_expr
.X_add_number
> 31)
7603 as_warn (_("Invalid value for `%s' (%lu)"),
7605 (unsigned long) imm_expr
.X_add_number
);
7606 imm_expr
.X_add_number
&= 0x1f;
7609 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7611 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7612 imm_expr
.X_op
= O_absent
;
7616 case 'c': /* break code */
7617 my_getExpression (&imm_expr
, s
);
7618 check_absolute_expr (ip
, &imm_expr
);
7619 if ((unsigned) imm_expr
.X_add_number
> 1023)
7621 as_warn (_("Illegal break code (%ld)"),
7622 (long) imm_expr
.X_add_number
);
7623 imm_expr
.X_add_number
&= 0x3ff;
7625 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7626 imm_expr
.X_op
= O_absent
;
7630 case 'q': /* lower break code */
7631 my_getExpression (&imm_expr
, s
);
7632 check_absolute_expr (ip
, &imm_expr
);
7633 if ((unsigned) imm_expr
.X_add_number
> 1023)
7635 as_warn (_("Illegal lower break code (%ld)"),
7636 (long) imm_expr
.X_add_number
);
7637 imm_expr
.X_add_number
&= 0x3ff;
7639 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7640 imm_expr
.X_op
= O_absent
;
7644 case 'B': /* syscall code */
7645 my_getExpression (&imm_expr
, s
);
7646 check_absolute_expr (ip
, &imm_expr
);
7647 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7648 as_warn (_("Illegal syscall code (%ld)"),
7649 (long) imm_expr
.X_add_number
);
7650 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7651 imm_expr
.X_op
= O_absent
;
7655 case 'C': /* Coprocessor code */
7656 my_getExpression (&imm_expr
, s
);
7657 check_absolute_expr (ip
, &imm_expr
);
7658 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7660 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7661 (long) imm_expr
.X_add_number
);
7662 imm_expr
.X_add_number
&= ((1<<25) - 1);
7664 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7665 imm_expr
.X_op
= O_absent
;
7669 case 'P': /* Performance register */
7670 my_getExpression (&imm_expr
, s
);
7671 check_absolute_expr (ip
, &imm_expr
);
7672 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7674 as_warn (_("Invalidate performance regster (%ld)"),
7675 (long) imm_expr
.X_add_number
);
7676 imm_expr
.X_add_number
&= 1;
7678 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7679 imm_expr
.X_op
= O_absent
;
7683 case 'b': /* base register */
7684 case 'd': /* destination register */
7685 case 's': /* source register */
7686 case 't': /* target register */
7687 case 'r': /* both target and source */
7688 case 'v': /* both dest and source */
7689 case 'w': /* both dest and target */
7690 case 'E': /* coprocessor target register */
7691 case 'G': /* coprocessor destination register */
7692 case 'x': /* ignore register name */
7693 case 'z': /* must be zero register */
7697 /* start-sanitize-r5900 */
7698 /* Allow "$viNN" as coprocessor register name */
7706 /* end-sanitize-r5900 */
7718 while (isdigit (*s
));
7720 as_bad (_("Invalid register number (%d)"), regno
);
7722 else if (*args
== 'E' || *args
== 'G')
7726 if (s
[1] == 'f' && s
[2] == 'p')
7731 else if (s
[1] == 's' && s
[2] == 'p')
7736 else if (s
[1] == 'g' && s
[2] == 'p')
7741 else if (s
[1] == 'a' && s
[2] == 't')
7746 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7751 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7756 else if (itbl_have_entries
)
7761 p
= s
+1; /* advance past '$' */
7762 n
= itbl_get_field (&p
); /* n is name */
7764 /* See if this is a register defined in an
7766 r
= itbl_get_reg_val (n
);
7769 /* Get_field advances to the start of
7770 the next field, so we need to back
7771 rack to the end of the last field. */
7775 s
= strchr (s
,'\0');
7788 as_warn (_("Used $at without \".set noat\""));
7794 if (c
== 'r' || c
== 'v' || c
== 'w')
7801 /* 'z' only matches $0. */
7802 if (c
== 'z' && regno
!= 0)
7805 /* Now that we have assembled one operand, we use the args string
7806 * to figure out where it goes in the instruction. */
7813 ip
->insn_opcode
|= regno
<< 21;
7817 ip
->insn_opcode
|= regno
<< 11;
7822 ip
->insn_opcode
|= regno
<< 16;
7825 /* This case exists because on the r3000 trunc
7826 expands into a macro which requires a gp
7827 register. On the r6000 or r4000 it is
7828 assembled into a single instruction which
7829 ignores the register. Thus the insn version
7830 is MIPS_ISA2 and uses 'x', and the macro
7831 version is MIPS_ISA1 and uses 't'. */
7834 /* This case is for the div instruction, which
7835 acts differently if the destination argument
7836 is $0. This only matches $0, and is checked
7837 outside the switch. */
7840 /* Itbl operand; not yet implemented. FIXME ?? */
7842 /* What about all other operands like 'i', which
7843 can be specified in the opcode table? */
7853 ip
->insn_opcode
|= lastregno
<< 21;
7856 ip
->insn_opcode
|= lastregno
<< 16;
7861 case 'D': /* floating point destination register */
7862 case 'S': /* floating point source register */
7863 case 'T': /* floating point target register */
7864 case 'R': /* floating point source register */
7867 /* start-sanitize-r5900 */
7868 case '1': /* vu0 fp reg position 1 */
7869 case '2': /* vu0 fp reg position 2 */
7870 case '3': /* vu0 fp reg position 3 */
7871 case '4': /* vu0 int reg position 1 */
7872 case '5': /* vu0 int reg position 2 */
7873 case '6': /* vu0 int reg position 3 */
7874 case '7': /* vu0 fp reg with ftf modifier */
7875 case '8': /* vu0 fp reg with fsf modifier */
7876 /* end-sanitize-r5900 */
7878 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
7888 while (isdigit (*s
));
7891 as_bad (_("Invalid float register number (%d)"), regno
);
7893 if ((regno
& 1) != 0
7894 && mips_opts
.isa
< 3
7895 && ! (strcmp (str
, "mtc1") == 0
7896 || strcmp (str
, "mfc1") == 0
7897 || strcmp (str
, "lwc1") == 0
7898 || strcmp (str
, "swc1") == 0
7899 || strcmp (str
, "l.s") == 0
7900 || strcmp (str
, "s.s") == 0))
7901 as_warn (_("Float register should be even, was %d"),
7909 if (c
== 'V' || c
== 'W')
7919 ip
->insn_opcode
|= regno
<< 6;
7923 ip
->insn_opcode
|= regno
<< 11;
7927 ip
->insn_opcode
|= regno
<< 16;
7930 ip
->insn_opcode
|= regno
<< 21;
7937 /* start-sanitize-r5900 */
7938 /* Handle vf and vi regsiters for vu0. Handle optional
7942 && (s
[1] == 'f' || s
[1] == 'i')
7947 && (s
[2] == 'f' || s
[2] == 'i')
7960 while (isdigit (*s
));
7963 as_bad (_("Invalid vu0 register number (%d)"), regno
);
7967 if (c
== '7' || c
== '8')
7976 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7981 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7986 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7991 ip
->insn_opcode
|= value
<< (c
== '7' ? 23 : 21);
7994 as_bad (_("Invalid FSF/FTF specification"));
8002 if (c
== 'V' || c
== 'W')
8014 ip
->insn_opcode
|= regno
<< 16;
8019 ip
->insn_opcode
|= regno
<< 11;
8023 ip
->insn_opcode
|= regno
<< 6;
8029 /* end-sanitize-r5900 */
8034 ip
->insn_opcode
|= lastregno
<< 11;
8037 ip
->insn_opcode
|= lastregno
<< 16;
8043 my_getExpression (&imm_expr
, s
);
8044 if (imm_expr
.X_op
!= O_big
8045 && imm_expr
.X_op
!= O_constant
)
8046 insn_error
= _("absolute expression required");
8051 my_getExpression (&offset_expr
, s
);
8052 imm_reloc
= BFD_RELOC_32
;
8064 unsigned char temp
[8];
8066 unsigned int length
;
8071 /* These only appear as the last operand in an
8072 instruction, and every instruction that accepts
8073 them in any variant accepts them in all variants.
8074 This means we don't have to worry about backing out
8075 any changes if the instruction does not match.
8077 The difference between them is the size of the
8078 floating point constant and where it goes. For 'F'
8079 and 'L' the constant is 64 bits; for 'f' and 'l' it
8080 is 32 bits. Where the constant is placed is based
8081 on how the MIPS assembler does things:
8084 f -- immediate value
8087 The .lit4 and .lit8 sections are only used if
8088 permitted by the -G argument.
8090 When generating embedded PIC code, we use the
8091 .lit8 section but not the .lit4 section (we can do
8092 .lit4 inline easily; we need to put .lit8
8093 somewhere in the data segment, and using .lit8
8094 permits the linker to eventually combine identical
8097 f64
= *args
== 'F' || *args
== 'L';
8099 save_in
= input_line_pointer
;
8100 input_line_pointer
= s
;
8101 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8103 s
= input_line_pointer
;
8104 input_line_pointer
= save_in
;
8105 if (err
!= NULL
&& *err
!= '\0')
8107 as_bad (_("Bad floating point constant: %s"), err
);
8108 memset (temp
, '\0', sizeof temp
);
8109 length
= f64
? 8 : 4;
8112 assert (length
== (f64
? 8 : 4));
8116 && (! USE_GLOBAL_POINTER_OPT
8117 || mips_pic
== EMBEDDED_PIC
8118 || g_switch_value
< 4
8119 || (temp
[0] == 0 && temp
[1] == 0)
8120 || (temp
[2] == 0 && temp
[3] == 0))))
8122 imm_expr
.X_op
= O_constant
;
8123 if (! target_big_endian
)
8124 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8126 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8129 && ((temp
[0] == 0 && temp
[1] == 0)
8130 || (temp
[2] == 0 && temp
[3] == 0))
8131 && ((temp
[4] == 0 && temp
[5] == 0)
8132 || (temp
[6] == 0 && temp
[7] == 0)))
8134 /* The value is simple enough to load with a
8135 couple of instructions. In mips1 mode, set
8136 imm_expr to the high order 32 bits and
8137 offset_expr to the low order 32 bits.
8138 Otherwise, set imm_expr to the entire 64 bit
8140 if (mips_opts
.isa
< 3)
8142 imm_expr
.X_op
= O_constant
;
8143 offset_expr
.X_op
= O_constant
;
8144 if (! target_big_endian
)
8146 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8147 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8151 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8152 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8154 if (offset_expr
.X_add_number
== 0)
8155 offset_expr
.X_op
= O_absent
;
8157 else if (sizeof (imm_expr
.X_add_number
) > 4)
8159 imm_expr
.X_op
= O_constant
;
8160 if (! target_big_endian
)
8161 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8163 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8167 imm_expr
.X_op
= O_big
;
8168 imm_expr
.X_add_number
= 4;
8169 if (! target_big_endian
)
8171 generic_bignum
[0] = bfd_getl16 (temp
);
8172 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8173 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8174 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8178 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8179 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8180 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8181 generic_bignum
[3] = bfd_getb16 (temp
);
8187 const char *newname
;
8190 /* Switch to the right section. */
8192 subseg
= now_subseg
;
8195 default: /* unused default case avoids warnings. */
8197 newname
= RDATA_SECTION_NAME
;
8198 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8202 newname
= RDATA_SECTION_NAME
;
8205 assert (!USE_GLOBAL_POINTER_OPT
8206 || g_switch_value
>= 4);
8210 new_seg
= subseg_new (newname
, (subsegT
) 0);
8211 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8212 bfd_set_section_flags (stdoutput
, new_seg
,
8217 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8218 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8219 && strcmp (TARGET_OS
, "elf") != 0)
8220 record_alignment (new_seg
, 4);
8222 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8224 as_bad (_("Can't use floating point insn in this section"));
8226 /* Set the argument to the current address in the
8228 offset_expr
.X_op
= O_symbol
;
8229 offset_expr
.X_add_symbol
=
8230 symbol_new ("L0\001", now_seg
,
8231 (valueT
) frag_now_fix (), frag_now
);
8232 offset_expr
.X_add_number
= 0;
8234 /* Put the floating point number into the section. */
8235 p
= frag_more ((int) length
);
8236 memcpy (p
, temp
, length
);
8238 /* Switch back to the original section. */
8239 subseg_set (seg
, subseg
);
8244 case 'i': /* 16 bit unsigned immediate */
8245 case 'j': /* 16 bit signed immediate */
8246 imm_reloc
= BFD_RELOC_LO16
;
8247 c
= my_getSmallExpression (&imm_expr
, s
);
8252 if (imm_expr
.X_op
== O_constant
)
8253 imm_expr
.X_add_number
=
8254 (imm_expr
.X_add_number
>> 16) & 0xffff;
8257 imm_reloc
= BFD_RELOC_HI16_S
;
8258 imm_unmatched_hi
= true;
8261 imm_reloc
= BFD_RELOC_HI16
;
8263 else if (imm_expr
.X_op
== O_constant
)
8264 imm_expr
.X_add_number
&= 0xffff;
8268 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8269 || ((imm_expr
.X_add_number
< 0
8270 || imm_expr
.X_add_number
>= 0x10000)
8271 && imm_expr
.X_op
== O_constant
))
8273 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8274 !strcmp (insn
->name
, insn
[1].name
))
8276 if (imm_expr
.X_op
!= O_constant
8277 && imm_expr
.X_op
!= O_big
)
8278 insn_error
= _("absolute expression required");
8280 as_bad (_("16 bit expression not in range 0..65535"));
8288 /* The upper bound should be 0x8000, but
8289 unfortunately the MIPS assembler accepts numbers
8290 from 0x8000 to 0xffff and sign extends them, and
8291 we want to be compatible. We only permit this
8292 extended range for an instruction which does not
8293 provide any further alternates, since those
8294 alternates may handle other cases. People should
8295 use the numbers they mean, rather than relying on
8296 a mysterious sign extension. */
8297 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8298 strcmp (insn
->name
, insn
[1].name
) == 0);
8303 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
8304 || ((imm_expr
.X_add_number
< -0x8000
8305 || imm_expr
.X_add_number
>= max
)
8306 && imm_expr
.X_op
== O_constant
)
8308 && imm_expr
.X_add_number
< 0
8309 && mips_opts
.isa
>= 3
8310 && imm_expr
.X_unsigned
8311 && sizeof (imm_expr
.X_add_number
) <= 4))
8315 if (imm_expr
.X_op
!= O_constant
8316 && imm_expr
.X_op
!= O_big
)
8317 insn_error
= _("absolute expression required");
8319 as_bad (_("16 bit expression not in range -32768..32767"));
8325 case 'o': /* 16 bit offset */
8326 c
= my_getSmallExpression (&offset_expr
, s
);
8328 /* If this value won't fit into a 16 bit offset, then go
8329 find a macro that will generate the 32 bit offset
8330 code pattern. As a special hack, we accept the
8331 difference of two local symbols as a constant. This
8332 is required to suppose embedded PIC switches, which
8333 use an instruction which looks like
8334 lw $4,$L12-$LS12($4)
8335 The problem with handling this in a more general
8336 fashion is that the macro function doesn't expect to
8337 see anything which can be handled in a single
8338 constant instruction. */
8340 && (offset_expr
.X_op
!= O_constant
8341 || offset_expr
.X_add_number
>= 0x8000
8342 || offset_expr
.X_add_number
< -0x8000)
8343 && (mips_pic
!= EMBEDDED_PIC
8344 || offset_expr
.X_op
!= O_subtract
8345 || now_seg
!= text_section
8346 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
8350 offset_reloc
= BFD_RELOC_LO16
;
8351 if (c
== 'h' || c
== 'H')
8353 assert (offset_expr
.X_op
== O_constant
);
8354 offset_expr
.X_add_number
=
8355 (offset_expr
.X_add_number
>> 16) & 0xffff;
8360 case 'p': /* pc relative offset */
8361 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8362 my_getExpression (&offset_expr
, s
);
8366 case 'u': /* upper 16 bits */
8367 c
= my_getSmallExpression (&imm_expr
, s
);
8368 imm_reloc
= BFD_RELOC_LO16
;
8373 if (imm_expr
.X_op
== O_constant
)
8374 imm_expr
.X_add_number
=
8375 (imm_expr
.X_add_number
>> 16) & 0xffff;
8378 imm_reloc
= BFD_RELOC_HI16_S
;
8379 imm_unmatched_hi
= true;
8382 imm_reloc
= BFD_RELOC_HI16
;
8384 else if (imm_expr
.X_op
== O_constant
)
8385 imm_expr
.X_add_number
&= 0xffff;
8387 if (imm_expr
.X_op
== O_constant
8388 && (imm_expr
.X_add_number
< 0
8389 || imm_expr
.X_add_number
>= 0x10000))
8390 as_bad (_("lui expression not in range 0..65535"));
8394 case 'a': /* 26 bit address */
8395 my_getExpression (&offset_expr
, s
);
8397 offset_reloc
= BFD_RELOC_MIPS_JMP
;
8400 case 'N': /* 3 bit branch condition code */
8401 case 'M': /* 3 bit compare condition code */
8402 if (strncmp (s
, "$fcc", 4) != 0)
8412 while (isdigit (*s
));
8414 as_bad (_("invalid condition code register $fcc%d"), regno
);
8416 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
8418 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
8421 /* start-sanitize-cygnus */
8422 case 'e': /* must be at least one digit */
8423 my_getExpression (&imm_expr
, s
);
8424 check_absolute_expr (ip
, &imm_expr
);
8425 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECBYTE
)
8427 as_bad (_("bad byte vector index (%ld)"),
8428 (long) imm_expr
.X_add_number
);
8429 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8431 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
8432 imm_expr
.X_op
= O_absent
;
8437 my_getExpression (&imm_expr
, s
);
8438 check_absolute_expr (ip
, &imm_expr
);
8439 if ((unsigned long) imm_expr
.X_add_number
> (unsigned long) OP_MASK_VECALIGN
)
8441 as_bad (_("bad byte vector index (%ld)"),
8442 (long) imm_expr
.X_add_number
);
8443 imm_expr
.X_add_number
= imm_expr
.X_add_number
;
8445 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
8446 imm_expr
.X_op
= O_absent
;
8450 /* end-sanitize-cygnus */
8452 as_bad (_("bad char = '%c'\n"), *args
);
8457 /* Args don't match. */
8458 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
8459 !strcmp (insn
->name
, insn
[1].name
))
8465 insn_error
= _("illegal operands");
8470 /* This routine assembles an instruction into its binary format when
8471 assembling for the mips16. As a side effect, it sets one of the
8472 global variables imm_reloc or offset_reloc to the type of
8473 relocation to do if one of the operands is an address expression.
8474 It also sets mips16_small and mips16_ext if the user explicitly
8475 requested a small or extended instruction. */
8480 struct mips_cl_insn
*ip
;
8484 struct mips_opcode
*insn
;
8487 unsigned int lastregno
= 0;
8492 mips16_small
= false;
8495 for (s
= str
; islower (*s
); ++s
)
8507 if (s
[1] == 't' && s
[2] == ' ')
8510 mips16_small
= true;
8514 else if (s
[1] == 'e' && s
[2] == ' ')
8523 insn_error
= _("unknown opcode");
8527 if (mips_opts
.noautoextend
&& ! mips16_ext
)
8528 mips16_small
= true;
8530 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
8532 insn_error
= _("unrecognized opcode");
8539 assert (strcmp (insn
->name
, str
) == 0);
8542 ip
->insn_opcode
= insn
->match
;
8543 ip
->use_extend
= false;
8544 imm_expr
.X_op
= O_absent
;
8545 imm_reloc
= BFD_RELOC_UNUSED
;
8546 offset_expr
.X_op
= O_absent
;
8547 offset_reloc
= BFD_RELOC_UNUSED
;
8548 for (args
= insn
->args
; 1; ++args
)
8555 /* In this switch statement we call break if we did not find
8556 a match, continue if we did find a match, or return if we
8565 /* Stuff the immediate value in now, if we can. */
8566 if (imm_expr
.X_op
== O_constant
8567 && imm_reloc
> BFD_RELOC_UNUSED
8568 && insn
->pinfo
!= INSN_MACRO
)
8570 mips16_immed ((char *) NULL
, 0,
8571 imm_reloc
- BFD_RELOC_UNUSED
,
8572 imm_expr
.X_add_number
, true, mips16_small
,
8573 mips16_ext
, &ip
->insn_opcode
,
8574 &ip
->use_extend
, &ip
->extend
);
8575 imm_expr
.X_op
= O_absent
;
8576 imm_reloc
= BFD_RELOC_UNUSED
;
8590 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8593 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8609 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8611 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8638 while (isdigit (*s
));
8641 as_bad (_("invalid register number (%d)"), regno
);
8647 if (s
[1] == 'f' && s
[2] == 'p')
8652 else if (s
[1] == 's' && s
[2] == 'p')
8657 else if (s
[1] == 'g' && s
[2] == 'p')
8662 else if (s
[1] == 'a' && s
[2] == 't')
8667 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8672 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8685 if (c
== 'v' || c
== 'w')
8687 regno
= mips16_to_32_reg_map
[lastregno
];
8701 regno
= mips32_to_16_reg_map
[regno
];
8706 regno
= ILLEGAL_REG
;
8711 regno
= ILLEGAL_REG
;
8716 regno
= ILLEGAL_REG
;
8721 if (regno
== AT
&& ! mips_opts
.noat
)
8722 as_warn (_("used $at without \".set noat\""));
8729 if (regno
== ILLEGAL_REG
)
8736 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8740 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8743 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8746 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8752 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8755 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8756 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8766 if (strncmp (s
, "$pc", 3) == 0)
8790 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8792 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8793 and generate the appropriate reloc. If the text
8794 inside %gprel is not a symbol name with an
8795 optional offset, then we generate a normal reloc
8796 and will probably fail later. */
8797 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8798 if (imm_expr
.X_op
== O_symbol
)
8801 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8803 ip
->use_extend
= true;
8810 /* Just pick up a normal expression. */
8811 my_getExpression (&imm_expr
, s
);
8814 if (imm_expr
.X_op
== O_register
)
8816 /* What we thought was an expression turned out to
8819 if (s
[0] == '(' && args
[1] == '(')
8821 /* It looks like the expression was omitted
8822 before a register indirection, which means
8823 that the expression is implicitly zero. We
8824 still set up imm_expr, so that we handle
8825 explicit extensions correctly. */
8826 imm_expr
.X_op
= O_constant
;
8827 imm_expr
.X_add_number
= 0;
8828 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8835 /* We need to relax this instruction. */
8836 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8845 /* We use offset_reloc rather than imm_reloc for the PC
8846 relative operands. This lets macros with both
8847 immediate and address operands work correctly. */
8848 my_getExpression (&offset_expr
, s
);
8850 if (offset_expr
.X_op
== O_register
)
8853 /* We need to relax this instruction. */
8854 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8858 case '6': /* break code */
8859 my_getExpression (&imm_expr
, s
);
8860 check_absolute_expr (ip
, &imm_expr
);
8861 if ((unsigned long) imm_expr
.X_add_number
> 63)
8863 as_warn (_("Invalid value for `%s' (%lu)"),
8865 (unsigned long) imm_expr
.X_add_number
);
8866 imm_expr
.X_add_number
&= 0x3f;
8868 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8869 imm_expr
.X_op
= O_absent
;
8873 case 'a': /* 26 bit address */
8874 my_getExpression (&offset_expr
, s
);
8876 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8877 ip
->insn_opcode
<<= 16;
8880 case 'l': /* register list for entry macro */
8881 case 'L': /* register list for exit macro */
8891 int freg
, reg1
, reg2
;
8893 while (*s
== ' ' || *s
== ',')
8897 as_bad (_("can't parse register list"));
8909 while (isdigit (*s
))
8931 as_bad (_("invalid register list"));
8936 while (isdigit (*s
))
8943 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8948 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8953 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8954 mask
|= (reg2
- 3) << 3;
8955 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8956 mask
|= (reg2
- 15) << 1;
8957 else if (reg1
== 31 && reg2
== 31)
8961 as_bad (_("invalid register list"));
8965 /* The mask is filled in in the opcode table for the
8966 benefit of the disassembler. We remove it before
8967 applying the actual mask. */
8968 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8969 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8973 case 'e': /* extend code */
8974 my_getExpression (&imm_expr
, s
);
8975 check_absolute_expr (ip
, &imm_expr
);
8976 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8978 as_warn (_("Invalid value for `%s' (%lu)"),
8980 (unsigned long) imm_expr
.X_add_number
);
8981 imm_expr
.X_add_number
&= 0x7ff;
8983 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8984 imm_expr
.X_op
= O_absent
;
8994 /* Args don't match. */
8995 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8996 strcmp (insn
->name
, insn
[1].name
) == 0)
9003 insn_error
= _("illegal operands");
9009 /* This structure holds information we know about a mips16 immediate
9012 struct mips16_immed_operand
9014 /* The type code used in the argument string in the opcode table. */
9016 /* The number of bits in the short form of the opcode. */
9018 /* The number of bits in the extended form of the opcode. */
9020 /* The amount by which the short form is shifted when it is used;
9021 for example, the sw instruction has a shift count of 2. */
9023 /* The amount by which the short form is shifted when it is stored
9024 into the instruction code. */
9026 /* Non-zero if the short form is unsigned. */
9028 /* Non-zero if the extended form is unsigned. */
9030 /* Non-zero if the value is PC relative. */
9034 /* The mips16 immediate operand types. */
9036 static const struct mips16_immed_operand mips16_immed_operands
[] =
9038 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9039 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9040 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9041 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9042 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9043 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9044 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9045 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9046 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9047 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9048 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9049 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9050 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9051 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9052 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9053 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9054 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9055 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9056 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9057 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9058 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9061 #define MIPS16_NUM_IMMED \
9062 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9064 /* Handle a mips16 instruction with an immediate value. This or's the
9065 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9066 whether an extended value is needed; if one is needed, it sets
9067 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9068 If SMALL is true, an unextended opcode was explicitly requested.
9069 If EXT is true, an extended opcode was explicitly requested. If
9070 WARN is true, warn if EXT does not match reality. */
9073 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
9082 unsigned long *insn
;
9083 boolean
*use_extend
;
9084 unsigned short *extend
;
9086 register const struct mips16_immed_operand
*op
;
9087 int mintiny
, maxtiny
;
9090 op
= mips16_immed_operands
;
9091 while (op
->type
!= type
)
9094 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9099 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9102 maxtiny
= 1 << op
->nbits
;
9107 maxtiny
= (1 << op
->nbits
) - 1;
9112 mintiny
= - (1 << (op
->nbits
- 1));
9113 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9116 /* Branch offsets have an implicit 0 in the lowest bit. */
9117 if (type
== 'p' || type
== 'q')
9120 if ((val
& ((1 << op
->shift
) - 1)) != 0
9121 || val
< (mintiny
<< op
->shift
)
9122 || val
> (maxtiny
<< op
->shift
))
9127 if (warn
&& ext
&& ! needext
)
9128 as_warn_where (file
, line
, _("extended operand requested but not required"));
9129 if (small
&& needext
)
9130 as_bad_where (file
, line
, _("invalid unextended operand value"));
9132 if (small
|| (! ext
&& ! needext
))
9136 *use_extend
= false;
9137 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9138 insnval
<<= op
->op_shift
;
9143 long minext
, maxext
;
9149 maxext
= (1 << op
->extbits
) - 1;
9153 minext
= - (1 << (op
->extbits
- 1));
9154 maxext
= (1 << (op
->extbits
- 1)) - 1;
9156 if (val
< minext
|| val
> maxext
)
9157 as_bad_where (file
, line
,
9158 _("operand value out of range for instruction"));
9161 if (op
->extbits
== 16)
9163 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9166 else if (op
->extbits
== 15)
9168 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9173 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9177 *extend
= (unsigned short) extval
;
9186 my_getSmallExpression (ep
, str
)
9197 ((str
[1] == 'h' && str
[2] == 'i')
9198 || (str
[1] == 'H' && str
[2] == 'I')
9199 || (str
[1] == 'l' && str
[2] == 'o'))
9211 * A small expression may be followed by a base register.
9212 * Scan to the end of this operand, and then back over a possible
9213 * base register. Then scan the small expression up to that
9214 * point. (Based on code in sparc.c...)
9216 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
9218 if (sp
- 4 >= str
&& sp
[-1] == RP
)
9220 if (isdigit (sp
[-2]))
9222 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
9224 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
9230 else if (sp
- 5 >= str
9233 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
9234 || (sp
[-3] == 's' && sp
[-2] == 'p')
9235 || (sp
[-3] == 'g' && sp
[-2] == 'p')
9236 || (sp
[-3] == 'a' && sp
[-2] == 't')))
9242 /* no expression means zero offset */
9245 /* %xx(reg) is an error */
9246 ep
->X_op
= O_absent
;
9251 ep
->X_op
= O_constant
;
9254 ep
->X_add_symbol
= NULL
;
9255 ep
->X_op_symbol
= NULL
;
9256 ep
->X_add_number
= 0;
9261 my_getExpression (ep
, str
);
9268 my_getExpression (ep
, str
);
9269 return c
; /* => %hi or %lo encountered */
9273 my_getExpression (ep
, str
)
9279 save_in
= input_line_pointer
;
9280 input_line_pointer
= str
;
9282 expr_end
= input_line_pointer
;
9283 input_line_pointer
= save_in
;
9285 /* If we are in mips16 mode, and this is an expression based on `.',
9286 then we bump the value of the symbol by 1 since that is how other
9287 text symbols are handled. We don't bother to handle complex
9288 expressions, just `.' plus or minus a constant. */
9289 if (mips_opts
.mips16
9290 && ep
->X_op
== O_symbol
9291 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9292 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9293 && ep
->X_add_symbol
->sy_frag
== frag_now
9294 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
9295 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
9296 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
9299 /* Turn a string in input_line_pointer into a floating point constant
9300 of type type, and store the appropriate bytes in *litP. The number
9301 of LITTLENUMS emitted is stored in *sizeP . An error message is
9302 returned, or NULL on OK. */
9305 md_atof (type
, litP
, sizeP
)
9311 LITTLENUM_TYPE words
[4];
9327 return _("bad call to md_atof");
9330 t
= atof_ieee (input_line_pointer
, type
, words
);
9332 input_line_pointer
= t
;
9336 if (! target_big_endian
)
9338 for (i
= prec
- 1; i
>= 0; i
--)
9340 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9346 for (i
= 0; i
< prec
; i
++)
9348 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
9357 md_number_to_chars (buf
, val
, n
)
9362 if (target_big_endian
)
9363 number_to_chars_bigendian (buf
, val
, n
);
9365 number_to_chars_littleendian (buf
, val
, n
);
9368 CONST
char *md_shortopts
= "O::g::G:";
9370 struct option md_longopts
[] = {
9371 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
9372 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
9373 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
9374 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
9375 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
9376 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
9377 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
9378 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
9379 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
9380 #define OPTION_MCPU (OPTION_MD_BASE + 5)
9381 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
9382 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
9383 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
9384 #define OPTION_TRAP (OPTION_MD_BASE + 9)
9385 {"trap", no_argument
, NULL
, OPTION_TRAP
},
9386 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
9387 #define OPTION_BREAK (OPTION_MD_BASE + 10)
9388 {"break", no_argument
, NULL
, OPTION_BREAK
},
9389 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
9390 #define OPTION_EB (OPTION_MD_BASE + 11)
9391 {"EB", no_argument
, NULL
, OPTION_EB
},
9392 #define OPTION_EL (OPTION_MD_BASE + 12)
9393 {"EL", no_argument
, NULL
, OPTION_EL
},
9394 #define OPTION_M4650 (OPTION_MD_BASE + 13)
9395 {"m4650", no_argument
, NULL
, OPTION_M4650
},
9396 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
9397 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
9398 #define OPTION_M4010 (OPTION_MD_BASE + 15)
9399 {"m4010", no_argument
, NULL
, OPTION_M4010
},
9400 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
9401 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
9402 #define OPTION_M4100 (OPTION_MD_BASE + 17)
9403 {"m4100", no_argument
, NULL
, OPTION_M4100
},
9404 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
9405 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
9406 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
9407 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
9408 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
9409 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
9410 /* start-sanitize-r5900 */
9411 #define OPTION_M5900 (OPTION_MD_BASE + 24)
9412 {"m5900", no_argument
, NULL
, OPTION_M5900
},
9413 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
9414 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
9415 /* end-sanitize-r5900 */
9416 #define OPTION_M3900 (OPTION_MD_BASE + 26)
9417 {"m3900", no_argument
, NULL
, OPTION_M3900
},
9418 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
9419 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
9421 /* start-sanitize-tx19 */
9422 {"m1900", no_argument
, NULL
, OPTION_M3900
},
9423 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
9424 /* end-sanitize-tx19 */
9426 /* start-sanitize-cygnus */
9427 #define OPTION_M5400 (OPTION_MD_BASE + 28)
9428 {"m5400", no_argument
, NULL
, OPTION_M5400
},
9429 #define OPTION_NO_M5400 (OPTION_MD_BASE + 29)
9430 {"no-m5400", no_argument
, NULL
, OPTION_NO_M5400
},
9432 /* end-sanitize-cygnus */
9433 /* start-sanitize-tx49 */
9434 #define OPTION_M4900 (OPTION_MD_BASE + 30)
9435 {"m4900", no_argument
, NULL
, OPTION_M4900
},
9436 #define OPTION_NO_M4900 (OPTION_MD_BASE + 31)
9437 {"no-m4900", no_argument
, NULL
, OPTION_NO_M4900
},
9439 /* end-sanitize-tx49 */
9440 /* start-sanitize-vr4320 */
9441 #define OPTION_M4320 (OPTION_MD_BASE + 32)
9442 {"m4320", no_argument
, NULL
, OPTION_M4320
},
9443 #define OPTION_NO_M4320 (OPTION_MD_BASE + 33)
9444 {"no-m4320", no_argument
, NULL
, OPTION_NO_M4320
},
9446 /* end-sanitize-vr4320 */
9447 /* start-sanitize-branchbug4011 */
9448 #define OPTION_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 34)
9449 {"fix-4011-branch-bug", no_argument
, NULL
, OPTION_FIX_4011_BRANCH_BUG
},
9450 #define OPTION_NO_FIX_4011_BRANCH_BUG (OPTION_MD_BASE + 35)
9451 {"no-fix-4011-branch-bug", no_argument
, NULL
, OPTION_NO_FIX_4011_BRANCH_BUG
},
9452 /* end-sanitize-branchbug4011 */
9454 /* start-sanitize-vr4xxx */
9455 #define OPTION_M4121 (OPTION_MD_BASE + 36)
9456 {"m4121", no_argument
, NULL
, OPTION_M4121
},
9457 #define OPTION_NO_M4121 (OPTION_MD_BASE + 37)
9458 {"no-m4121", no_argument
, NULL
, OPTION_NO_M4121
},
9460 /* end-sanitize-vr4xxx */
9461 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
9462 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
9463 #define OPTION_XGOT (OPTION_MD_BASE + 19)
9464 #define OPTION_32 (OPTION_MD_BASE + 20)
9465 #define OPTION_64 (OPTION_MD_BASE + 21)
9467 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
9468 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
9469 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
9470 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
9471 {"32", no_argument
, NULL
, OPTION_32
},
9472 {"64", no_argument
, NULL
, OPTION_64
},
9475 {NULL
, no_argument
, NULL
, 0}
9477 size_t md_longopts_size
= sizeof(md_longopts
);
9480 md_parse_option (c
, arg
)
9495 target_big_endian
= 1;
9499 target_big_endian
= 0;
9503 if (arg
&& arg
[1] == '0')
9513 mips_debug
= atoi (arg
);
9514 /* When the MIPS assembler sees -g or -g2, it does not do
9515 optimizations which limit full symbolic debugging. We take
9516 that to be equivalent to -O0. */
9517 if (mips_debug
== 2)
9541 /* Identify the processor type */
9543 if (strcmp (p
, "default") == 0
9544 || strcmp (p
, "DEFAULT") == 0)
9550 /* We need to cope with the various "vr" prefixes for the 4300
9552 if (*p
== 'v' || *p
== 'V')
9558 if (*p
== 'r' || *p
== 'R')
9565 if (strcmp (p
, "10000") == 0
9566 || strcmp (p
, "10k") == 0
9567 || strcmp (p
, "10K") == 0)
9569 /* start-sanitize-tx19 */
9570 else if (strcmp (p
, "1900") == 0)
9572 /* end-sanitize-tx19 */
9576 if (strcmp (p
, "2000") == 0
9577 || strcmp (p
, "2k") == 0
9578 || strcmp (p
, "2K") == 0)
9583 if (strcmp (p
, "3000") == 0
9584 || strcmp (p
, "3k") == 0
9585 || strcmp (p
, "3K") == 0)
9587 else if (strcmp (p
, "3900") == 0)
9592 if (strcmp (p
, "4000") == 0
9593 || strcmp (p
, "4k") == 0
9594 || strcmp (p
, "4K") == 0)
9596 else if (strcmp (p
, "4100") == 0)
9598 /* start-sanitize-vr4xxx */
9599 else if (strcmp (p
, "4111") == 0)
9601 else if (strcmp (p
, "4121") == 0)
9603 /* end-sanitize-vr4xxx */
9604 else if (strcmp (p
, "4300") == 0)
9606 /* start-sanitize-vr4320 */
9607 else if (strcmp (p
, "4320") == 0)
9609 /* end-sanitize-vr4320 */
9610 else if (strcmp (p
, "4400") == 0)
9612 else if (strcmp (p
, "4600") == 0)
9614 else if (strcmp (p
, "4650") == 0)
9616 /* start-sanitize-tx49 */
9617 else if (strcmp (p
, "4900") == 0)
9619 /* end-sanitize-tx49 */
9620 else if (strcmp (p
, "4010") == 0)
9625 if (strcmp (p
, "5000") == 0
9626 || strcmp (p
, "5k") == 0
9627 || strcmp (p
, "5K") == 0)
9629 /* start-sanitize-cygnus */
9630 else if (strcmp (p
, "5400") == 0)
9632 /* end-sanitize-cygnus */
9633 /* start-sanitize-r5900 */
9634 else if (strcmp (p
, "5900") == 0)
9636 /* end-sanitize-r5900 */
9640 if (strcmp (p
, "6000") == 0
9641 || strcmp (p
, "6k") == 0
9642 || strcmp (p
, "6K") == 0)
9647 if (strcmp (p
, "8000") == 0
9648 || strcmp (p
, "8k") == 0
9649 || strcmp (p
, "8K") == 0)
9654 if (strcmp (p
, "orion") == 0)
9660 && (mips_cpu
!= 4300
9662 /* start-sanitize-vr4xxx */
9665 /* end-sanitize-vr4xxx */
9666 /* start-sanitize-vr4320 */
9668 /* end-sanitize-vr4320 */
9669 /* start-sanitize-cygnus */
9671 /* end-sanitize-cygnus */
9672 && mips_cpu
!= 5000))
9674 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9680 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9691 case OPTION_NO_M4650
:
9699 case OPTION_NO_M4010
:
9707 case OPTION_NO_M4100
:
9711 /* start-sanitize-vr4xxx */
9716 case OPTION_NO_M4121
:
9720 /* end-sanitize-vr4xxx */
9721 /* start-sanitize-r5900 */
9726 case OPTION_NO_M5900
:
9729 /* end-sanitize-r5900 */
9731 /* start-sanitize-vr4320 */
9736 case OPTION_NO_M4320
:
9740 /* end-sanitize-vr4320 */
9741 /* start-sanitize-cygnus */
9746 case OPTION_NO_M5400
:
9750 /* end-sanitize-cygnus */
9755 case OPTION_NO_M3900
:
9759 /* start-sanitize-tx49 */
9764 case OPTION_NO_M4900
:
9768 /* end-sanitize-tx49 */
9770 mips_opts
.mips16
= 1;
9771 mips_no_prev_insn (false);
9774 case OPTION_NO_MIPS16
:
9775 mips_opts
.mips16
= 0;
9776 mips_no_prev_insn (false);
9779 case OPTION_MEMBEDDED_PIC
:
9780 mips_pic
= EMBEDDED_PIC
;
9781 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9783 as_bad (_("-G may not be used with embedded PIC code"));
9786 g_switch_value
= 0x7fffffff;
9789 /* When generating ELF code, we permit -KPIC and -call_shared to
9790 select SVR4_PIC, and -non_shared to select no PIC. This is
9791 intended to be compatible with Irix 5. */
9792 case OPTION_CALL_SHARED
:
9793 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9795 as_bad (_("-call_shared is supported only for ELF format"));
9798 mips_pic
= SVR4_PIC
;
9799 if (g_switch_seen
&& g_switch_value
!= 0)
9801 as_bad (_("-G may not be used with SVR4 PIC code"));
9807 case OPTION_NON_SHARED
:
9808 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9810 as_bad (_("-non_shared is supported only for ELF format"));
9816 /* The -xgot option tells the assembler to use 32 offsets when
9817 accessing the got in SVR4_PIC mode. It is for Irix
9824 if (! USE_GLOBAL_POINTER_OPT
)
9826 as_bad (_("-G is not supported for this configuration"));
9829 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9831 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9835 g_switch_value
= atoi (arg
);
9839 /* The -32 and -64 options tell the assembler to output the 32
9840 bit or the 64 bit MIPS ELF format. */
9847 const char **list
, **l
;
9849 list
= bfd_target_list ();
9850 for (l
= list
; *l
!= NULL
; l
++)
9851 if (strcmp (*l
, "elf64-bigmips") == 0
9852 || strcmp (*l
, "elf64-littlemips") == 0)
9855 as_fatal (_("No compiled in support for 64 bit object file format"));
9861 /* start-sanitize-branchbug4011 */
9862 case OPTION_FIX_4011_BRANCH_BUG
:
9863 mips_fix_4011_branch_bug
= 1;
9866 case OPTION_NO_FIX_4011_BRANCH_BUG
:
9867 mips_fix_4011_branch_bug
= 0;
9870 /* end-sanitize-branchbug4011 */
9879 md_show_usage (stream
)
9882 fprintf(stream
, _("\
9884 -membedded-pic generate embedded position independent code\n\
9885 -EB generate big endian output\n\
9886 -EL generate little endian output\n\
9887 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9888 -G NUM allow referencing objects up to NUM bytes\n\
9889 implicitly with the gp register [default 8]\n"));
9890 fprintf(stream
, _("\
9891 -mips1 generate MIPS ISA I instructions\n\
9892 -mips2 generate MIPS ISA II instructions\n\
9893 -mips3 generate MIPS ISA III instructions\n\
9894 -mips4 generate MIPS ISA IV instructions\n\
9895 -mcpu=vr4300 generate code for vr4300\n\
9896 -mcpu=vr4100 generate code for vr4100\n\
9897 -m4650 permit R4650 instructions\n\
9898 -no-m4650 do not permit R4650 instructions\n\
9899 -m4010 permit R4010 instructions\n\
9900 -no-m4010 do not permit R4010 instructions\n\
9901 -m4100 permit VR4100 instructions\n\
9902 -no-m4100 do not permit VR4100 instructions\n"));
9903 /* start-sanitize-vr4xxx */
9904 fprintf(stream
, _("\
9905 -mcpu=vr4121 generate code for vr4121\n\
9906 -m4121 permit VR4121 instructions\n\
9907 -no-m4121 do not permit VR4121 instructions\n"));
9908 /* end-sanitize-vr4xxx */
9909 fprintf(stream
, _("\
9910 -mips16 generate mips16 instructions\n\
9911 -no-mips16 do not generate mips16 instructions\n"));
9912 fprintf(stream
, _("\
9913 -O0 remove unneeded NOPs, do not swap branches\n\
9914 -O remove unneeded NOPs and swap branches\n\
9915 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9916 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9918 fprintf(stream
, _("\
9919 -KPIC, -call_shared generate SVR4 position independent code\n\
9920 -non_shared do not generate position independent code\n\
9921 -xgot assume a 32 bit GOT\n\
9922 -32 create 32 bit object file (default)\n\
9923 -64 create 64 bit object file\n"));
9928 mips_init_after_args ()
9930 /* initialize opcodes */
9931 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9932 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9936 md_pcrel_from (fixP
)
9939 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9940 && fixP
->fx_addsy
!= (symbolS
*) NULL
9941 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9943 /* This makes a branch to an undefined symbol be a branch to the
9944 current location. */
9948 /* return the address of the delay slot */
9949 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9952 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9953 reloc for a cons. We could use the definition there, except that
9954 we want to handle 64 bit relocs specially. */
9957 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9960 unsigned int nbytes
;
9964 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9966 if (nbytes
== 8 && ! mips_64
)
9968 if (target_big_endian
)
9974 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9975 as_bad (_("Unsupported reloc size %d"), nbytes
);
9977 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9980 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9983 /* This is called before the symbol table is processed. In order to
9984 work with gcc when using mips-tfile, we must keep all local labels.
9985 However, in other cases, we want to discard them. If we were
9986 called with -g, but we didn't see any debugging information, it may
9987 mean that gcc is smuggling debugging information through to
9988 mips-tfile, in which case we must generate all local labels. */
9991 mips_frob_file_before_adjust ()
9993 #ifndef NO_ECOFF_DEBUGGING
9996 && ! ecoff_debugging_seen
)
9997 flag_keep_locals
= 1;
10001 /* Sort any unmatched HI16_S relocs so that they immediately precede
10002 the corresponding LO reloc. This is called before md_apply_fix and
10003 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10004 explicit use of the %hi modifier. */
10009 struct mips_hi_fixup
*l
;
10011 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10013 segment_info_type
*seginfo
;
10016 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
10018 /* Check quickly whether the next fixup happens to be a matching
10020 if (l
->fixp
->fx_next
!= NULL
10021 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
10022 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
10023 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
10026 /* Look through the fixups for this segment for a matching %lo.
10027 When we find one, move the %hi just in front of it. We do
10028 this in two passes. In the first pass, we try to find a
10029 unique %lo. In the second pass, we permit multiple %hi
10030 relocs for a single %lo (this is a GNU extension). */
10031 seginfo
= seg_info (l
->seg
);
10032 for (pass
= 0; pass
< 2; pass
++)
10037 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10039 /* Check whether this is a %lo fixup which matches l->fixp. */
10040 if (f
->fx_r_type
== BFD_RELOC_LO16
10041 && f
->fx_addsy
== l
->fixp
->fx_addsy
10042 && f
->fx_offset
== l
->fixp
->fx_offset
10045 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
10046 || prev
->fx_addsy
!= f
->fx_addsy
10047 || prev
->fx_offset
!= f
->fx_offset
))
10051 /* Move l->fixp before f. */
10052 for (pf
= &seginfo
->fix_root
;
10054 pf
= &(*pf
)->fx_next
)
10055 assert (*pf
!= NULL
);
10057 *pf
= l
->fixp
->fx_next
;
10059 l
->fixp
->fx_next
= f
;
10061 seginfo
->fix_root
= l
->fixp
;
10063 prev
->fx_next
= l
->fixp
;
10075 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10076 _("Unmatched %%hi reloc"));
10081 /* When generating embedded PIC code we need to use a special
10082 relocation to represent the difference of two symbols in the .text
10083 section (switch tables use a difference of this sort). See
10084 include/coff/mips.h for details. This macro checks whether this
10085 fixup requires the special reloc. */
10086 #define SWITCH_TABLE(fixp) \
10087 ((fixp)->fx_r_type == BFD_RELOC_32 \
10088 && (fixp)->fx_addsy != NULL \
10089 && (fixp)->fx_subsy != NULL \
10090 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10091 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10093 /* When generating embedded PIC code we must keep all PC relative
10094 relocations, in case the linker has to relax a call. We also need
10095 to keep relocations for switch table entries. */
10099 mips_force_relocation (fixp
)
10102 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10103 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
10106 return (mips_pic
== EMBEDDED_PIC
10108 || SWITCH_TABLE (fixp
)
10109 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10110 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10113 /* Apply a fixup to the object file. */
10116 md_apply_fix (fixP
, valueP
)
10120 unsigned char *buf
;
10123 assert (fixP
->fx_size
== 4
10124 || fixP
->fx_r_type
== BFD_RELOC_16
10125 || fixP
->fx_r_type
== BFD_RELOC_64
10126 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10127 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10131 /* If we aren't adjusting this fixup to be against the section
10132 symbol, we need to adjust the value. */
10134 if (fixP
->fx_addsy
!= NULL
10135 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
10136 && (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
10137 || S_IS_WEAK (fixP
->fx_addsy
)))
10139 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10140 if (value
!= 0 && ! fixP
->fx_pcrel
)
10142 /* In this case, the bfd_install_relocation routine will
10143 incorrectly add the symbol value back in. We just want
10144 the addend to appear in the object file. */
10145 value
-= S_GET_VALUE (fixP
->fx_addsy
);
10150 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
10152 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
10155 switch (fixP
->fx_r_type
)
10157 case BFD_RELOC_MIPS_JMP
:
10158 case BFD_RELOC_HI16
:
10159 case BFD_RELOC_HI16_S
:
10160 case BFD_RELOC_MIPS_GPREL
:
10161 case BFD_RELOC_MIPS_LITERAL
:
10162 case BFD_RELOC_MIPS_CALL16
:
10163 case BFD_RELOC_MIPS_GOT16
:
10164 case BFD_RELOC_MIPS_GPREL32
:
10165 case BFD_RELOC_MIPS_GOT_HI16
:
10166 case BFD_RELOC_MIPS_GOT_LO16
:
10167 case BFD_RELOC_MIPS_CALL_HI16
:
10168 case BFD_RELOC_MIPS_CALL_LO16
:
10169 case BFD_RELOC_MIPS16_GPREL
:
10170 /* start-sanitize-r5900 */
10171 case BFD_RELOC_MIPS15_S3
:
10172 /* end-sanitize-r5900 */
10173 if (fixP
->fx_pcrel
)
10174 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10175 _("Invalid PC relative reloc"));
10176 /* Nothing needed to do. The value comes from the reloc entry */
10179 case BFD_RELOC_MIPS16_JMP
:
10180 /* We currently always generate a reloc against a symbol, which
10181 means that we don't want an addend even if the symbol is
10183 fixP
->fx_addnumber
= 0;
10186 case BFD_RELOC_PCREL_HI16_S
:
10187 /* The addend for this is tricky if it is internal, so we just
10188 do everything here rather than in bfd_install_relocation. */
10189 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
10191 /* For an external symbol adjust by the address to make it
10192 pcrel_offset. We use the address of the RELLO reloc
10193 which follows this one. */
10194 value
+= (fixP
->fx_next
->fx_frag
->fr_address
10195 + fixP
->fx_next
->fx_where
);
10197 if (value
& 0x8000)
10200 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10201 if (target_big_endian
)
10203 md_number_to_chars (buf
, value
, 2);
10206 case BFD_RELOC_PCREL_LO16
:
10207 /* The addend for this is tricky if it is internal, so we just
10208 do everything here rather than in bfd_install_relocation. */
10209 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
10210 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
10211 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10212 if (target_big_endian
)
10214 md_number_to_chars (buf
, value
, 2);
10218 /* This is handled like BFD_RELOC_32, but we output a sign
10219 extended value if we are only 32 bits. */
10221 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10223 if (8 <= sizeof (valueT
))
10224 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10231 w1
= w2
= fixP
->fx_where
;
10232 if (target_big_endian
)
10236 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
10237 if ((value
& 0x80000000) != 0)
10241 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
10247 /* If we are deleting this reloc entry, we must fill in the
10248 value now. This can happen if we have a .word which is not
10249 resolved when it appears but is later defined. We also need
10250 to fill in the value if this is an embedded PIC switch table
10253 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
10254 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10259 /* If we are deleting this reloc entry, we must fill in the
10261 assert (fixP
->fx_size
== 2);
10263 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
10267 case BFD_RELOC_LO16
:
10268 /* When handling an embedded PIC switch statement, we can wind
10269 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
10272 if (value
< -0x8000 || value
> 0x7fff)
10273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10274 _("relocation overflow"));
10275 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
10276 if (target_big_endian
)
10278 md_number_to_chars (buf
, value
, 2);
10282 case BFD_RELOC_16_PCREL_S2
:
10284 * We need to save the bits in the instruction since fixup_segment()
10285 * might be deleting the relocation entry (i.e., a branch within
10286 * the current segment).
10288 if ((value
& 0x3) != 0)
10289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10290 _("Branch to odd address (%lx)"), value
);
10293 /* update old instruction data */
10294 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
10295 if (target_big_endian
)
10296 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
10298 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
10300 if (value
>= -0x8000 && value
< 0x8000)
10301 insn
|= value
& 0xffff;
10304 /* The branch offset is too large. If this is an
10305 unconditional branch, and we are not generating PIC code,
10306 we can convert it to an absolute jump instruction. */
10307 if (mips_pic
== NO_PIC
10309 && fixP
->fx_frag
->fr_address
>= text_section
->vma
10310 && (fixP
->fx_frag
->fr_address
10311 < text_section
->vma
+ text_section
->_raw_size
)
10312 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
10313 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
10314 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
10316 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
10317 insn
= 0x0c000000; /* jal */
10319 insn
= 0x08000000; /* j */
10320 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
10322 fixP
->fx_addsy
= section_symbol (text_section
);
10323 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
10327 /* FIXME. It would be possible in principle to handle
10328 conditional branches which overflow. They could be
10329 transformed into a branch around a jump. This would
10330 require setting up variant frags for each different
10331 branch type. The native MIPS assembler attempts to
10332 handle these cases, but it appears to do it
10334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10335 _("Branch out of range"));
10339 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
10342 case BFD_RELOC_VTABLE_INHERIT
:
10345 && !S_IS_DEFINED (fixP
->fx_addsy
)
10346 && !S_IS_WEAK (fixP
->fx_addsy
))
10347 S_SET_WEAK (fixP
->fx_addsy
);
10350 case BFD_RELOC_VTABLE_ENTRY
:
10366 const struct mips_opcode
*p
;
10367 int treg
, sreg
, dreg
, shamt
;
10372 for (i
= 0; i
< NUMOPCODES
; ++i
)
10374 p
= &mips_opcodes
[i
];
10375 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
10377 printf ("%08lx %s\t", oc
, p
->name
);
10378 treg
= (oc
>> 16) & 0x1f;
10379 sreg
= (oc
>> 21) & 0x1f;
10380 dreg
= (oc
>> 11) & 0x1f;
10381 shamt
= (oc
>> 6) & 0x1f;
10383 for (args
= p
->args
;; ++args
)
10394 printf ("%c", *args
);
10398 assert (treg
== sreg
);
10399 printf ("$%d,$%d", treg
, sreg
);
10404 printf ("$%d", dreg
);
10409 printf ("$%d", treg
);
10413 printf ("0x%x", treg
);
10418 printf ("$%d", sreg
);
10422 printf ("0x%08lx", oc
& 0x1ffffff);
10429 printf ("%d", imm
);
10434 printf ("$%d", shamt
);
10445 printf (_("%08lx UNDEFINED\n"), oc
);
10456 name
= input_line_pointer
;
10457 c
= get_symbol_end ();
10458 p
= (symbolS
*) symbol_find_or_make (name
);
10459 *input_line_pointer
= c
;
10463 /* Align the current frag to a given power of two. The MIPS assembler
10464 also automatically adjusts any preceding label. */
10467 mips_align (to
, fill
, label
)
10472 mips_emit_delays (false);
10473 frag_align (to
, fill
, 0);
10474 record_alignment (now_seg
, to
);
10477 assert (S_GET_SEGMENT (label
) == now_seg
);
10478 label
->sy_frag
= frag_now
;
10479 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
10483 /* Align to a given power of two. .align 0 turns off the automatic
10484 alignment used by the data creating pseudo-ops. */
10491 register long temp_fill
;
10492 long max_alignment
= 15;
10496 o Note that the assembler pulls down any immediately preceeding label
10497 to the aligned address.
10498 o It's not documented but auto alignment is reinstated by
10499 a .align pseudo instruction.
10500 o Note also that after auto alignment is turned off the mips assembler
10501 issues an error on attempt to assemble an improperly aligned data item.
10506 temp
= get_absolute_expression ();
10507 if (temp
> max_alignment
)
10508 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
10511 as_warn (_("Alignment negative: 0 assumed."));
10514 if (*input_line_pointer
== ',')
10516 input_line_pointer
++;
10517 temp_fill
= get_absolute_expression ();
10524 mips_align (temp
, (int) temp_fill
,
10525 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
10532 demand_empty_rest_of_line ();
10536 mips_flush_pending_output ()
10538 mips_emit_delays (false);
10539 mips_clear_insn_labels ();
10548 /* When generating embedded PIC code, we only use the .text, .lit8,
10549 .sdata and .sbss sections. We change the .data and .rdata
10550 pseudo-ops to use .sdata. */
10551 if (mips_pic
== EMBEDDED_PIC
10552 && (sec
== 'd' || sec
== 'r'))
10556 /* The ELF backend needs to know that we are changing sections, so
10557 that .previous works correctly. We could do something like check
10558 for a obj_section_change_hook macro, but that might be confusing
10559 as it would not be appropriate to use it in the section changing
10560 functions in read.c, since obj-elf.c intercepts those. FIXME:
10561 This should be cleaner, somehow. */
10562 obj_elf_section_change_hook ();
10565 mips_emit_delays (false);
10575 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10576 demand_empty_rest_of_line ();
10580 if (USE_GLOBAL_POINTER_OPT
)
10582 seg
= subseg_new (RDATA_SECTION_NAME
,
10583 (subsegT
) get_absolute_expression ());
10584 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10586 bfd_set_section_flags (stdoutput
, seg
,
10592 if (strcmp (TARGET_OS
, "elf") != 0)
10593 bfd_set_section_alignment (stdoutput
, seg
, 4);
10595 demand_empty_rest_of_line ();
10599 as_bad (_("No read only data section in this object file format"));
10600 demand_empty_rest_of_line ();
10606 if (USE_GLOBAL_POINTER_OPT
)
10608 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10609 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10611 bfd_set_section_flags (stdoutput
, seg
,
10612 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10614 if (strcmp (TARGET_OS
, "elf") != 0)
10615 bfd_set_section_alignment (stdoutput
, seg
, 4);
10617 demand_empty_rest_of_line ();
10622 as_bad (_("Global pointers not supported; recompile -G 0"));
10623 demand_empty_rest_of_line ();
10632 mips_enable_auto_align ()
10643 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10644 mips_emit_delays (false);
10645 if (log_size
> 0 && auto_align
)
10646 mips_align (log_size
, 0, label
);
10647 mips_clear_insn_labels ();
10648 cons (1 << log_size
);
10652 s_float_cons (type
)
10657 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10659 mips_emit_delays (false);
10663 mips_align (3, 0, label
);
10665 mips_align (2, 0, label
);
10667 mips_clear_insn_labels ();
10672 /* Handle .globl. We need to override it because on Irix 5 you are
10675 where foo is an undefined symbol, to mean that foo should be
10676 considered to be the address of a function. */
10687 name
= input_line_pointer
;
10688 c
= get_symbol_end ();
10689 symbolP
= symbol_find_or_make (name
);
10690 *input_line_pointer
= c
;
10691 SKIP_WHITESPACE ();
10693 /* On Irix 5, every global symbol that is not explicitly labelled as
10694 being a function is apparently labelled as being an object. */
10697 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10702 secname
= input_line_pointer
;
10703 c
= get_symbol_end ();
10704 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10706 as_bad (_("%s: no such section"), secname
);
10707 *input_line_pointer
= c
;
10709 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10710 flag
= BSF_FUNCTION
;
10713 symbolP
->bsym
->flags
|= flag
;
10715 S_SET_EXTERNAL (symbolP
);
10716 demand_empty_rest_of_line ();
10726 opt
= input_line_pointer
;
10727 c
= get_symbol_end ();
10731 /* FIXME: What does this mean? */
10733 else if (strncmp (opt
, "pic", 3) == 0)
10737 i
= atoi (opt
+ 3);
10741 mips_pic
= SVR4_PIC
;
10743 as_bad (_(".option pic%d not supported"), i
);
10745 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10747 if (g_switch_seen
&& g_switch_value
!= 0)
10748 as_warn (_("-G may not be used with SVR4 PIC code"));
10749 g_switch_value
= 0;
10750 bfd_set_gp_size (stdoutput
, 0);
10754 as_warn (_("Unrecognized option \"%s\""), opt
);
10756 *input_line_pointer
= c
;
10757 demand_empty_rest_of_line ();
10760 /* This structure is used to hold a stack of .set values. */
10762 struct mips_option_stack
10764 struct mips_option_stack
*next
;
10765 struct mips_set_options options
;
10768 static struct mips_option_stack
*mips_opts_stack
;
10770 /* Handle the .set pseudo-op. */
10776 char *name
= input_line_pointer
, ch
;
10778 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10779 input_line_pointer
++;
10780 ch
= *input_line_pointer
;
10781 *input_line_pointer
= '\0';
10783 if (strcmp (name
, "reorder") == 0)
10785 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10787 /* If we still have pending nops, we can discard them. The
10788 usual nop handling will insert any that are still
10790 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10791 * (mips_opts
.mips16
? 2 : 4));
10792 prev_nop_frag
= NULL
;
10794 mips_opts
.noreorder
= 0;
10796 else if (strcmp (name
, "noreorder") == 0)
10798 mips_emit_delays (true);
10799 mips_opts
.noreorder
= 1;
10800 mips_any_noreorder
= 1;
10802 else if (strcmp (name
, "at") == 0)
10804 mips_opts
.noat
= 0;
10806 else if (strcmp (name
, "noat") == 0)
10808 mips_opts
.noat
= 1;
10810 else if (strcmp (name
, "macro") == 0)
10812 mips_opts
.warn_about_macros
= 0;
10814 else if (strcmp (name
, "nomacro") == 0)
10816 if (mips_opts
.noreorder
== 0)
10817 as_bad (_("`noreorder' must be set before `nomacro'"));
10818 mips_opts
.warn_about_macros
= 1;
10820 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10822 mips_opts
.nomove
= 0;
10824 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10826 mips_opts
.nomove
= 1;
10828 else if (strcmp (name
, "bopt") == 0)
10830 mips_opts
.nobopt
= 0;
10832 else if (strcmp (name
, "nobopt") == 0)
10834 mips_opts
.nobopt
= 1;
10836 else if (strcmp (name
, "mips16") == 0
10837 || strcmp (name
, "MIPS-16") == 0)
10838 mips_opts
.mips16
= 1;
10839 else if (strcmp (name
, "nomips16") == 0
10840 || strcmp (name
, "noMIPS-16") == 0)
10841 mips_opts
.mips16
= 0;
10842 else if (strncmp (name
, "mips", 4) == 0)
10846 /* Permit the user to change the ISA on the fly. Needless to
10847 say, misuse can cause serious problems. */
10848 isa
= atoi (name
+ 4);
10850 mips_opts
.isa
= file_mips_isa
;
10851 else if (isa
< 1 || isa
> 4)
10852 as_bad (_("unknown ISA level"));
10854 mips_opts
.isa
= isa
;
10856 else if (strcmp (name
, "autoextend") == 0)
10857 mips_opts
.noautoextend
= 0;
10858 else if (strcmp (name
, "noautoextend") == 0)
10859 mips_opts
.noautoextend
= 1;
10860 else if (strcmp (name
, "push") == 0)
10862 struct mips_option_stack
*s
;
10864 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10865 s
->next
= mips_opts_stack
;
10866 s
->options
= mips_opts
;
10867 mips_opts_stack
= s
;
10869 else if (strcmp (name
, "pop") == 0)
10871 struct mips_option_stack
*s
;
10873 s
= mips_opts_stack
;
10875 as_bad (_(".set pop with no .set push"));
10878 /* If we're changing the reorder mode we need to handle
10879 delay slots correctly. */
10880 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10881 mips_emit_delays (true);
10882 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10884 if (prev_nop_frag
!= NULL
)
10886 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10887 * (mips_opts
.mips16
? 2 : 4));
10888 prev_nop_frag
= NULL
;
10892 mips_opts
= s
->options
;
10893 mips_opts_stack
= s
->next
;
10899 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10901 *input_line_pointer
= ch
;
10902 demand_empty_rest_of_line ();
10905 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10906 .option pic2. It means to generate SVR4 PIC calls. */
10909 s_abicalls (ignore
)
10912 mips_pic
= SVR4_PIC
;
10913 if (USE_GLOBAL_POINTER_OPT
)
10915 if (g_switch_seen
&& g_switch_value
!= 0)
10916 as_warn (_("-G may not be used with SVR4 PIC code"));
10917 g_switch_value
= 0;
10919 bfd_set_gp_size (stdoutput
, 0);
10920 demand_empty_rest_of_line ();
10923 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10924 PIC code. It sets the $gp register for the function based on the
10925 function address, which is in the register named in the argument.
10926 This uses a relocation against _gp_disp, which is handled specially
10927 by the linker. The result is:
10928 lui $gp,%hi(_gp_disp)
10929 addiu $gp,$gp,%lo(_gp_disp)
10930 addu $gp,$gp,.cpload argument
10931 The .cpload argument is normally $25 == $t9. */
10940 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10941 if (mips_pic
!= SVR4_PIC
)
10947 /* .cpload should be a in .set noreorder section. */
10948 if (mips_opts
.noreorder
== 0)
10949 as_warn (_(".cpload not in noreorder section"));
10951 ex
.X_op
= O_symbol
;
10952 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10953 ex
.X_op_symbol
= NULL
;
10954 ex
.X_add_number
= 0;
10956 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10957 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
10959 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10960 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10961 (int) BFD_RELOC_LO16
);
10963 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10964 GP
, GP
, tc_get_register (0));
10966 demand_empty_rest_of_line ();
10969 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10970 offset from $sp. The offset is remembered, and after making a PIC
10971 call $gp is restored from that location. */
10974 s_cprestore (ignore
)
10980 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10981 if (mips_pic
!= SVR4_PIC
)
10987 mips_cprestore_offset
= get_absolute_expression ();
10989 ex
.X_op
= O_constant
;
10990 ex
.X_add_symbol
= NULL
;
10991 ex
.X_op_symbol
= NULL
;
10992 ex
.X_add_number
= mips_cprestore_offset
;
10994 macro_build ((char *) NULL
, &icnt
, &ex
,
10995 ((bfd_arch_bits_per_address (stdoutput
) == 32
10996 || mips_opts
.isa
< 3)
10998 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
11000 demand_empty_rest_of_line ();
11003 /* Handle the .gpword pseudo-op. This is used when generating PIC
11004 code. It generates a 32 bit GP relative reloc. */
11014 /* When not generating PIC code, this is treated as .word. */
11015 if (mips_pic
!= SVR4_PIC
)
11021 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11022 mips_emit_delays (true);
11024 mips_align (2, 0, label
);
11025 mips_clear_insn_labels ();
11029 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
11031 as_bad (_("Unsupported use of .gpword"));
11032 ignore_rest_of_line ();
11036 md_number_to_chars (p
, (valueT
) 0, 4);
11037 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
11038 BFD_RELOC_MIPS_GPREL32
);
11040 demand_empty_rest_of_line ();
11043 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
11044 tables in SVR4 PIC code. */
11053 /* This is ignored when not generating SVR4 PIC code. */
11054 if (mips_pic
!= SVR4_PIC
)
11060 /* Add $gp to the register named as an argument. */
11061 reg
= tc_get_register (0);
11062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
11063 ((bfd_arch_bits_per_address (stdoutput
) == 32
11064 || mips_opts
.isa
< 3)
11065 ? "addu" : "daddu"),
11066 "d,v,t", reg
, reg
, GP
);
11068 demand_empty_rest_of_line ();
11071 /* Handle the .insn pseudo-op. This marks instruction labels in
11072 mips16 mode. This permits the linker to handle them specially,
11073 such as generating jalx instructions when needed. We also make
11074 them odd for the duration of the assembly, in order to generate the
11075 right sort of code. We will make them even in the adjust_symtab
11076 routine, while leaving them marked. This is convenient for the
11077 debugger and the disassembler. The linker knows to make them odd
11084 if (mips_opts
.mips16
)
11085 mips16_mark_labels ();
11087 demand_empty_rest_of_line ();
11090 /* Handle a .stabn directive. We need these in order to mark a label
11091 as being a mips16 text label correctly. Sometimes the compiler
11092 will emit a label, followed by a .stabn, and then switch sections.
11093 If the label and .stabn are in mips16 mode, then the label is
11094 really a mips16 text label. */
11100 if (type
== 'n' && mips_opts
.mips16
)
11101 mips16_mark_labels ();
11106 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
11110 s_mips_weakext (ignore
)
11118 name
= input_line_pointer
;
11119 c
= get_symbol_end ();
11120 symbolP
= symbol_find_or_make (name
);
11121 S_SET_WEAK (symbolP
);
11122 *input_line_pointer
= c
;
11124 SKIP_WHITESPACE ();
11126 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11128 if (S_IS_DEFINED (symbolP
))
11130 as_bad ("Ignoring attempt to redefine symbol `%s'.",
11131 S_GET_NAME (symbolP
));
11132 ignore_rest_of_line ();
11136 if (*input_line_pointer
== ',')
11138 ++input_line_pointer
;
11139 SKIP_WHITESPACE ();
11143 if (exp
.X_op
!= O_symbol
)
11145 as_bad ("bad .weakext directive");
11146 ignore_rest_of_line();
11149 symbolP
->sy_value
= exp
;
11152 demand_empty_rest_of_line ();
11155 /* Parse a register string into a number. Called from the ECOFF code
11156 to parse .frame. The argument is non-zero if this is the frame
11157 register, so that we can record it in mips_frame_reg. */
11160 tc_get_register (frame
)
11165 SKIP_WHITESPACE ();
11166 if (*input_line_pointer
++ != '$')
11168 as_warn (_("expected `$'"));
11171 else if (isdigit ((unsigned char) *input_line_pointer
))
11173 reg
= get_absolute_expression ();
11174 if (reg
< 0 || reg
>= 32)
11176 as_warn (_("Bad register number"));
11182 if (strncmp (input_line_pointer
, "fp", 2) == 0)
11184 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
11186 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
11188 else if (strncmp (input_line_pointer
, "at", 2) == 0)
11192 as_warn (_("Unrecognized register name"));
11195 input_line_pointer
+= 2;
11198 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
11203 md_section_align (seg
, addr
)
11207 int align
= bfd_get_section_alignment (stdoutput
, seg
);
11210 /* We don't need to align ELF sections to the full alignment.
11211 However, Irix 5 may prefer that we align them at least to a 16
11212 byte boundary. We don't bother to align the sections if we are
11213 targeted for an embedded system. */
11214 if (strcmp (TARGET_OS
, "elf") == 0)
11220 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
11223 /* Utility routine, called from above as well. If called while the
11224 input file is still being read, it's only an approximation. (For
11225 example, a symbol may later become defined which appeared to be
11226 undefined earlier.) */
11229 nopic_need_relax (sym
, before_relaxing
)
11231 int before_relaxing
;
11236 if (USE_GLOBAL_POINTER_OPT
)
11238 const char *symname
;
11241 /* Find out whether this symbol can be referenced off the GP
11242 register. It can be if it is smaller than the -G size or if
11243 it is in the .sdata or .sbss section. Certain symbols can
11244 not be referenced off the GP, although it appears as though
11246 symname
= S_GET_NAME (sym
);
11247 if (symname
!= (const char *) NULL
11248 && (strcmp (symname
, "eprol") == 0
11249 || strcmp (symname
, "etext") == 0
11250 || strcmp (symname
, "_gp") == 0
11251 || strcmp (symname
, "edata") == 0
11252 || strcmp (symname
, "_fbss") == 0
11253 || strcmp (symname
, "_fdata") == 0
11254 || strcmp (symname
, "_ftext") == 0
11255 || strcmp (symname
, "end") == 0
11256 || strcmp (symname
, "_gp_disp") == 0))
11258 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
11260 #ifndef NO_ECOFF_DEBUGGING
11261 || (sym
->ecoff_extern_size
!= 0
11262 && sym
->ecoff_extern_size
<= g_switch_value
)
11264 /* We must defer this decision until after the whole
11265 file has been read, since there might be a .extern
11266 after the first use of this symbol. */
11267 || (before_relaxing
11268 #ifndef NO_ECOFF_DEBUGGING
11269 && sym
->ecoff_extern_size
== 0
11271 && S_GET_VALUE (sym
) == 0)
11272 || (S_GET_VALUE (sym
) != 0
11273 && S_GET_VALUE (sym
) <= g_switch_value
)))
11277 const char *segname
;
11279 segname
= segment_name (S_GET_SEGMENT (sym
));
11280 assert (strcmp (segname
, ".lit8") != 0
11281 && strcmp (segname
, ".lit4") != 0);
11282 change
= (strcmp (segname
, ".sdata") != 0
11283 && strcmp (segname
, ".sbss") != 0);
11288 /* We are not optimizing for the GP register. */
11292 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
11293 extended opcode. SEC is the section the frag is in. */
11296 mips16_extended_frag (fragp
, sec
, stretch
)
11302 register const struct mips16_immed_operand
*op
;
11304 int mintiny
, maxtiny
;
11307 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
11309 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
11312 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11313 op
= mips16_immed_operands
;
11314 while (op
->type
!= type
)
11317 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
11322 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
11325 maxtiny
= 1 << op
->nbits
;
11330 maxtiny
= (1 << op
->nbits
) - 1;
11335 mintiny
= - (1 << (op
->nbits
- 1));
11336 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
11339 /* We can't call S_GET_VALUE here, because we don't want to lock in
11340 a particular frag address. */
11341 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
11343 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
11344 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11345 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
11347 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
11348 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
11351 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
11352 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
11353 + fragp
->fr_symbol
->sy_value
.X_add_number
11354 + fragp
->fr_symbol
->sy_frag
->fr_address
);
11355 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
11364 /* We won't have the section when we are called from
11365 mips_relax_frag. However, we will always have been called
11366 from md_estimate_size_before_relax first. If this is a
11367 branch to a different section, we mark it as such. If SEC is
11368 NULL, and the frag is not marked, then it must be a branch to
11369 the same section. */
11372 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
11379 fragp
->fr_subtype
=
11380 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11382 /* FIXME: We should support this, and let the linker
11383 catch branches and loads that are out of range. */
11384 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
11385 _("unsupported PC relative reference to different section"));
11391 /* In this case, we know for sure that the symbol fragment is in
11392 the same section. If the fr_address of the symbol fragment
11393 is greater then the address of this fragment we want to add
11394 in STRETCH in order to get a better estimate of the address.
11395 This particularly matters because of the shift bits. */
11397 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
11401 /* Adjust stretch for any alignment frag. Note that if have
11402 been expanding the earlier code, the symbol may be
11403 defined in what appears to be an earlier frag. FIXME:
11404 This doesn't handle the fr_subtype field, which specifies
11405 a maximum number of bytes to skip when doing an
11408 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
11411 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
11414 stretch
= - ((- stretch
)
11415 & ~ ((1 << (int) f
->fr_offset
) - 1));
11417 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
11426 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11428 /* The base address rules are complicated. The base address of
11429 a branch is the following instruction. The base address of a
11430 PC relative load or add is the instruction itself, but if it
11431 is in a delay slot (in which case it can not be extended) use
11432 the address of the instruction whose delay slot it is in. */
11433 if (type
== 'p' || type
== 'q')
11437 /* If we are currently assuming that this frag should be
11438 extended, then, the current address is two bytes
11440 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11443 /* Ignore the low bit in the target, since it will be set
11444 for a text label. */
11445 if ((val
& 1) != 0)
11448 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11450 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11453 val
-= addr
& ~ ((1 << op
->shift
) - 1);
11455 /* Branch offsets have an implicit 0 in the lowest bit. */
11456 if (type
== 'p' || type
== 'q')
11459 /* If any of the shifted bits are set, we must use an extended
11460 opcode. If the address depends on the size of this
11461 instruction, this can lead to a loop, so we arrange to always
11462 use an extended opcode. We only check this when we are in
11463 the main relaxation loop, when SEC is NULL. */
11464 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
11466 fragp
->fr_subtype
=
11467 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11471 /* If we are about to mark a frag as extended because the value
11472 is precisely maxtiny + 1, then there is a chance of an
11473 infinite loop as in the following code:
11478 In this case when the la is extended, foo is 0x3fc bytes
11479 away, so the la can be shrunk, but then foo is 0x400 away, so
11480 the la must be extended. To avoid this loop, we mark the
11481 frag as extended if it was small, and is about to become
11482 extended with a value of maxtiny + 1. */
11483 if (val
== ((maxtiny
+ 1) << op
->shift
)
11484 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
11487 fragp
->fr_subtype
=
11488 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
11492 else if (symsec
!= absolute_section
&& sec
!= NULL
)
11493 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
11495 if ((val
& ((1 << op
->shift
) - 1)) != 0
11496 || val
< (mintiny
<< op
->shift
)
11497 || val
> (maxtiny
<< op
->shift
))
11503 /* Estimate the size of a frag before relaxing. Unless this is the
11504 mips16, we are not really relaxing here, and the final size is
11505 encoded in the subtype information. For the mips16, we have to
11506 decide whether we are using an extended opcode or not. */
11510 md_estimate_size_before_relax (fragp
, segtype
)
11516 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11518 if (mips16_extended_frag (fragp
, segtype
, 0))
11520 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11525 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11530 if (mips_pic
== NO_PIC
)
11532 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11534 else if (mips_pic
== SVR4_PIC
)
11539 sym
= fragp
->fr_symbol
;
11541 /* Handle the case of a symbol equated to another symbol. */
11542 while (sym
->sy_value
.X_op
== O_symbol
11543 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11547 /* It's possible to get a loop here in a badly written
11549 n
= sym
->sy_value
.X_add_symbol
;
11555 symsec
= S_GET_SEGMENT (sym
);
11557 /* This must duplicate the test in adjust_reloc_syms. */
11558 change
= (symsec
!= &bfd_und_section
11559 && symsec
!= &bfd_abs_section
11560 && ! bfd_is_com_section (symsec
));
11567 /* Record the offset to the first reloc in the fr_opcode field.
11568 This lets md_convert_frag and tc_gen_reloc know that the code
11569 must be expanded. */
11570 fragp
->fr_opcode
= (fragp
->fr_literal
11572 - RELAX_OLD (fragp
->fr_subtype
)
11573 + RELAX_RELOC1 (fragp
->fr_subtype
));
11574 /* FIXME: This really needs as_warn_where. */
11575 if (RELAX_WARN (fragp
->fr_subtype
))
11576 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11582 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11585 /* This is called to see whether a reloc against a defined symbol
11586 should be converted into a reloc against a section. Don't adjust
11587 MIPS16 jump relocations, so we don't have to worry about the format
11588 of the offset in the .o file. Don't adjust relocations against
11589 mips16 symbols, so that the linker can find them if it needs to set
11593 mips_fix_adjustable (fixp
)
11596 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11598 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11599 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11601 if (fixp
->fx_addsy
== NULL
)
11604 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11605 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11606 && fixp
->fx_subsy
== NULL
)
11612 /* Translate internal representation of relocation info to BFD target
11616 tc_gen_reloc (section
, fixp
)
11620 static arelent
*retval
[4];
11622 bfd_reloc_code_real_type code
;
11624 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11627 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11628 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11630 if (mips_pic
== EMBEDDED_PIC
11631 && SWITCH_TABLE (fixp
))
11633 /* For a switch table entry we use a special reloc. The addend
11634 is actually the difference between the reloc address and the
11636 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11637 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11638 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11639 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11641 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11643 /* We use a special addend for an internal RELLO reloc. */
11644 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11645 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11647 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11649 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11651 assert (fixp
->fx_next
!= NULL
11652 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11653 /* We use a special addend for an internal RELHI reloc. The
11654 reloc is relative to the RELLO; adjust the addend
11656 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
11657 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11658 + fixp
->fx_next
->fx_where
11659 - S_GET_VALUE (fixp
->fx_subsy
));
11661 reloc
->addend
= (fixp
->fx_addnumber
11662 + fixp
->fx_next
->fx_frag
->fr_address
11663 + fixp
->fx_next
->fx_where
);
11665 else if (fixp
->fx_pcrel
== 0)
11666 reloc
->addend
= fixp
->fx_addnumber
;
11669 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11670 /* A gruesome hack which is a result of the gruesome gas reloc
11672 reloc
->addend
= reloc
->address
;
11674 reloc
->addend
= -reloc
->address
;
11677 /* If this is a variant frag, we may need to adjust the existing
11678 reloc and generate a new one. */
11679 if (fixp
->fx_frag
->fr_opcode
!= NULL
11680 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11681 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11682 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11683 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11684 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11685 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11686 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11690 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11692 /* If this is not the last reloc in this frag, then we have two
11693 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11694 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11695 the second one handle all of them. */
11696 if (fixp
->fx_next
!= NULL
11697 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11699 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11700 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11701 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11702 && (fixp
->fx_next
->fx_r_type
11703 == BFD_RELOC_MIPS_GOT_LO16
))
11704 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11705 && (fixp
->fx_next
->fx_r_type
11706 == BFD_RELOC_MIPS_CALL_LO16
)));
11711 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11712 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11713 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11715 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
11716 reloc2
->address
= (reloc
->address
11717 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11718 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11719 reloc2
->addend
= fixp
->fx_addnumber
;
11720 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11721 assert (reloc2
->howto
!= NULL
);
11723 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11727 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11730 reloc3
->address
+= 4;
11733 if (mips_pic
== NO_PIC
)
11735 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11736 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11738 else if (mips_pic
== SVR4_PIC
)
11740 switch (fixp
->fx_r_type
)
11744 case BFD_RELOC_MIPS_GOT16
:
11746 case BFD_RELOC_MIPS_CALL16
:
11747 case BFD_RELOC_MIPS_GOT_LO16
:
11748 case BFD_RELOC_MIPS_CALL_LO16
:
11749 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11757 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11758 to be used in the relocation's section offset. */
11759 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11761 reloc
->address
= reloc
->addend
;
11765 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11766 fixup_segment converted a non-PC relative reloc into a PC
11767 relative reloc. In such a case, we need to convert the reloc
11769 code
= fixp
->fx_r_type
;
11770 if (fixp
->fx_pcrel
)
11775 code
= BFD_RELOC_8_PCREL
;
11778 code
= BFD_RELOC_16_PCREL
;
11781 code
= BFD_RELOC_32_PCREL
;
11784 code
= BFD_RELOC_64_PCREL
;
11786 case BFD_RELOC_8_PCREL
:
11787 case BFD_RELOC_16_PCREL
:
11788 case BFD_RELOC_32_PCREL
:
11789 case BFD_RELOC_64_PCREL
:
11790 case BFD_RELOC_16_PCREL_S2
:
11791 case BFD_RELOC_PCREL_HI16_S
:
11792 case BFD_RELOC_PCREL_LO16
:
11795 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11796 _("Cannot make %s relocation PC relative"),
11797 bfd_get_reloc_code_name (code
));
11801 /* To support a PC relative reloc when generating embedded PIC code
11802 for ECOFF, we use a Cygnus extension. We check for that here to
11803 make sure that we don't let such a reloc escape normally. */
11804 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11805 && code
== BFD_RELOC_16_PCREL_S2
11806 && mips_pic
!= EMBEDDED_PIC
)
11807 reloc
->howto
= NULL
;
11809 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11811 if (reloc
->howto
== NULL
)
11813 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11814 _("Can not represent %s relocation in this object file format"),
11815 bfd_get_reloc_code_name (code
));
11822 /* Relax a machine dependent frag. This returns the amount by which
11823 the current size of the frag should change. */
11826 mips_relax_frag (fragp
, stretch
)
11830 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11833 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11835 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11837 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11842 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11844 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11851 /* Convert a machine dependent frag. */
11854 md_convert_frag (abfd
, asec
, fragp
)
11862 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11865 register const struct mips16_immed_operand
*op
;
11866 boolean small
, ext
;
11869 unsigned long insn
;
11870 boolean use_extend
;
11871 unsigned short extend
;
11873 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11874 op
= mips16_immed_operands
;
11875 while (op
->type
!= type
)
11878 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11889 resolve_symbol_value (fragp
->fr_symbol
, 1);
11890 val
= S_GET_VALUE (fragp
->fr_symbol
);
11895 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11897 /* The rules for the base address of a PC relative reloc are
11898 complicated; see mips16_extended_frag. */
11899 if (type
== 'p' || type
== 'q')
11904 /* Ignore the low bit in the target, since it will be
11905 set for a text label. */
11906 if ((val
& 1) != 0)
11909 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11911 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11914 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11917 /* Make sure the section winds up with the alignment we have
11920 record_alignment (asec
, op
->shift
);
11924 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11925 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11926 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11927 _("extended instruction in delay slot"));
11929 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11931 if (target_big_endian
)
11932 insn
= bfd_getb16 (buf
);
11934 insn
= bfd_getl16 (buf
);
11936 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11937 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11938 small
, ext
, &insn
, &use_extend
, &extend
);
11942 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11943 fragp
->fr_fix
+= 2;
11947 md_number_to_chars (buf
, insn
, 2);
11948 fragp
->fr_fix
+= 2;
11953 if (fragp
->fr_opcode
== NULL
)
11956 old
= RELAX_OLD (fragp
->fr_subtype
);
11957 new = RELAX_NEW (fragp
->fr_subtype
);
11958 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11961 memcpy (fixptr
- old
, fixptr
, new);
11963 fragp
->fr_fix
+= new - old
;
11969 /* This function is called after the relocs have been generated.
11970 We've been storing mips16 text labels as odd. Here we convert them
11971 back to even for the convenience of the debugger. */
11974 mips_frob_file_after_relocs ()
11977 unsigned int count
, i
;
11979 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11982 syms
= bfd_get_outsymbols (stdoutput
);
11983 count
= bfd_get_symcount (stdoutput
);
11984 for (i
= 0; i
< count
; i
++, syms
++)
11986 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11987 && ((*syms
)->value
& 1) != 0)
11989 (*syms
)->value
&= ~1;
11990 /* If the symbol has an odd size, it was probably computed
11991 incorrectly, so adjust that as well. */
11992 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11993 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
12000 /* This function is called whenever a label is defined. It is used
12001 when handling branch delays; if a branch has a label, we assume we
12002 can not move it. */
12005 mips_define_label (sym
)
12008 struct insn_label_list
*l
;
12010 if (free_insn_labels
== NULL
)
12011 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
12014 l
= free_insn_labels
;
12015 free_insn_labels
= l
->next
;
12019 l
->next
= insn_labels
;
12023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12025 /* Some special processing for a MIPS ELF file. */
12028 mips_elf_final_processing ()
12030 /* Write out the register information. */
12035 s
.ri_gprmask
= mips_gprmask
;
12036 s
.ri_cprmask
[0] = mips_cprmask
[0];
12037 s
.ri_cprmask
[1] = mips_cprmask
[1];
12038 s
.ri_cprmask
[2] = mips_cprmask
[2];
12039 s
.ri_cprmask
[3] = mips_cprmask
[3];
12040 /* The gp_value field is set by the MIPS ELF backend. */
12042 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
12043 ((Elf32_External_RegInfo
*)
12044 mips_regmask_frag
));
12048 Elf64_Internal_RegInfo s
;
12050 s
.ri_gprmask
= mips_gprmask
;
12052 s
.ri_cprmask
[0] = mips_cprmask
[0];
12053 s
.ri_cprmask
[1] = mips_cprmask
[1];
12054 s
.ri_cprmask
[2] = mips_cprmask
[2];
12055 s
.ri_cprmask
[3] = mips_cprmask
[3];
12056 /* The gp_value field is set by the MIPS ELF backend. */
12058 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
12059 ((Elf64_External_RegInfo
*)
12060 mips_regmask_frag
));
12063 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
12064 sort of BFD interface for this. */
12065 if (mips_any_noreorder
)
12066 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
12067 if (mips_pic
!= NO_PIC
)
12068 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
12071 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
12073 typedef struct proc
12075 struct symbol
*isym
;
12076 unsigned long reg_mask
;
12077 unsigned long reg_offset
;
12078 unsigned long fpreg_mask
;
12079 unsigned long fpreg_offset
;
12080 unsigned long frame_offset
;
12081 unsigned long frame_reg
;
12082 unsigned long pc_reg
;
12086 static procS cur_proc
;
12087 static procS
*cur_proc_ptr
;
12088 static int numprocs
;
12098 /* check for premature end, nesting errors, etc */
12100 as_warn (_("missing `.end' at end of assembly"));
12109 if (*input_line_pointer
== '-')
12111 ++input_line_pointer
;
12114 if (!isdigit (*input_line_pointer
))
12115 as_bad (_("Expected simple number."));
12116 if (input_line_pointer
[0] == '0')
12118 if (input_line_pointer
[1] == 'x')
12120 input_line_pointer
+= 2;
12121 while (isxdigit (*input_line_pointer
))
12124 val
|= hex_value (*input_line_pointer
++);
12126 return negative
? -val
: val
;
12130 ++input_line_pointer
;
12131 while (isdigit (*input_line_pointer
))
12134 val
|= *input_line_pointer
++ - '0';
12136 return negative
? -val
: val
;
12139 if (!isdigit (*input_line_pointer
))
12141 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
12142 *input_line_pointer
, *input_line_pointer
);
12143 as_warn (_("Invalid number"));
12146 while (isdigit (*input_line_pointer
))
12149 val
+= *input_line_pointer
++ - '0';
12151 return negative
? -val
: val
;
12154 /* The .file directive; just like the usual .file directive, but there
12155 is an initial number which is the ECOFF file index. */
12163 line
= get_number ();
12168 /* The .end directive. */
12177 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12180 demand_empty_rest_of_line ();
12185 #ifdef BFD_ASSEMBLER
12186 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12191 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12198 as_warn (_(".end not in text section"));
12202 as_warn (_(".end directive without a preceding .ent directive."));
12203 demand_empty_rest_of_line ();
12209 assert (S_GET_NAME (p
));
12210 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
12211 as_warn (_(".end symbol does not match .ent symbol."));
12214 as_warn (_(".end directive missing or unknown symbol"));
12216 #ifdef MIPS_STABS_ELF
12218 segT saved_seg
= now_seg
;
12219 subsegT saved_subseg
= now_subseg
;
12220 fragS
*saved_frag
= frag_now
;
12226 dot
= frag_now_fix ();
12228 #ifdef md_flush_pending_output
12229 md_flush_pending_output ();
12233 subseg_set (pdr_seg
, 0);
12235 /* Write the symbol */
12236 exp
.X_op
= O_symbol
;
12237 exp
.X_add_symbol
= p
;
12238 exp
.X_add_number
= 0;
12239 emit_expr (&exp
, 4);
12241 fragp
= frag_more (7*4);
12243 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
12244 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
12245 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
12246 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
12247 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
12248 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
12249 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
12251 subseg_set (saved_seg
, saved_subseg
);
12255 cur_proc_ptr
= NULL
;
12258 /* The .aent and .ent directives. */
12268 symbolP
= get_symbol ();
12269 if (*input_line_pointer
== ',')
12270 input_line_pointer
++;
12271 SKIP_WHITESPACE ();
12272 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
12273 number
= get_number ();
12275 #ifdef BFD_ASSEMBLER
12276 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
12281 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
12288 as_warn (_(".ent or .aent not in text section."));
12290 if (!aent
&& cur_proc_ptr
)
12291 as_warn (_("missing `.end'"));
12295 cur_proc_ptr
= &cur_proc
;
12296 memset (cur_proc_ptr
, '\0', sizeof (procS
));
12298 cur_proc_ptr
->isym
= symbolP
;
12300 symbolP
->bsym
->flags
|= BSF_FUNCTION
;
12305 demand_empty_rest_of_line ();
12308 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
12309 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
12310 s_mips_frame is used so that we can set the PDR information correctly.
12311 We can't use the ecoff routines because they make reference to the ecoff
12312 symbol table (in the mdebug section). */
12315 s_mips_frame (ignore
)
12318 #ifdef MIPS_STABS_ELF
12322 if (cur_proc_ptr
== (procS
*) NULL
)
12324 as_warn (_(".frame outside of .ent"));
12325 demand_empty_rest_of_line ();
12329 cur_proc_ptr
->frame_reg
= tc_get_register (1);
12331 SKIP_WHITESPACE ();
12332 if (*input_line_pointer
++ != ','
12333 || get_absolute_expression_and_terminator (&val
) != ',')
12335 as_warn (_("Bad .frame directive"));
12336 --input_line_pointer
;
12337 demand_empty_rest_of_line ();
12341 cur_proc_ptr
->frame_offset
= val
;
12342 cur_proc_ptr
->pc_reg
= tc_get_register (0);
12344 demand_empty_rest_of_line ();
12347 #endif /* MIPS_STABS_ELF */
12350 /* The .fmask and .mask directives. If the mdebug section is present
12351 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
12352 embedded targets, s_mips_mask is used so that we can set the PDR
12353 information correctly. We can't use the ecoff routines because they
12354 make reference to the ecoff symbol table (in the mdebug section). */
12357 s_mips_mask (reg_type
)
12360 #ifdef MIPS_STABS_ELF
12363 if (cur_proc_ptr
== (procS
*) NULL
)
12365 as_warn (_(".mask/.fmask outside of .ent"));
12366 demand_empty_rest_of_line ();
12370 if (get_absolute_expression_and_terminator (&mask
) != ',')
12372 as_warn (_("Bad .mask/.fmask directive"));
12373 --input_line_pointer
;
12374 demand_empty_rest_of_line ();
12378 off
= get_absolute_expression ();
12380 if (reg_type
== 'F')
12382 cur_proc_ptr
->fpreg_mask
= mask
;
12383 cur_proc_ptr
->fpreg_offset
= off
;
12387 cur_proc_ptr
->reg_mask
= mask
;
12388 cur_proc_ptr
->reg_offset
= off
;
12391 demand_empty_rest_of_line ();
12393 s_ignore (reg_type
);
12394 #endif /* MIPS_STABS_ELF */
12397 /* The .loc directive. */
12408 assert (now_seg
== text_section
);
12410 lineno
= get_number ();
12411 addroff
= frag_now_fix ();
12413 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
12414 S_SET_TYPE (symbolP
, N_SLINE
);
12415 S_SET_OTHER (symbolP
, 0);
12416 S_SET_DESC (symbolP
, lineno
);
12417 symbolP
->sy_segment
= now_seg
;