1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
63 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
66 /* Fix any of them that we actually care about. */
68 #define OUTPUT_FLAVOR mips_output_flavor()
75 #ifndef ECOFF_DEBUGGING
76 #define NO_ECOFF_DEBUGGING
77 #define ECOFF_DEBUGGING 0
82 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
83 static char *mips_regmask_frag
;
88 #define PIC_CALL_REG 25
96 #define ILLEGAL_REG (32)
98 /* Allow override of standard little-endian ECOFF format. */
100 #ifndef ECOFF_LITTLE_FORMAT
101 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
104 extern int target_big_endian
;
106 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
107 32 bit ABI. This has no meaning for ECOFF.
108 Note that the default is always 32 bit, even if "configured" for
109 64 bit [e.g. --target=mips64-elf]. */
112 /* The default target format to use. */
114 mips_target_format ()
116 switch (OUTPUT_FLAVOR
)
118 case bfd_target_aout_flavour
:
119 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
120 case bfd_target_ecoff_flavour
:
121 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
122 case bfd_target_elf_flavour
:
123 return (target_big_endian
124 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
125 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
132 /* The name of the readonly data section. */
133 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
135 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
137 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Whether we are assembling for the mips16 processor. 0 if we are
152 not, 1 if we are, and -1 if the value has not been initialized.
153 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
154 -nomips16 command line options, and the default CPU. */
156 /* Non-zero if we should not reorder instructions. Changed by `.set
157 reorder' and `.set noreorder'. */
159 /* Non-zero if we should not permit the $at ($1) register to be used
160 in instructions. Changed by `.set at' and `.set noat'. */
162 /* Non-zero if we should warn when a macro instruction expands into
163 more than one machine instruction. Changed by `.set nomacro' and
165 int warn_about_macros
;
166 /* Non-zero if we should not move instructions. Changed by `.set
167 move', `.set volatile', `.set nomove', and `.set novolatile'. */
169 /* Non-zero if we should not optimize branches by moving the target
170 of the branch into the delay slot. Actually, we don't perform
171 this optimization anyhow. Changed by `.set bopt' and `.set
174 /* Non-zero if we should not autoextend mips16 instructions.
175 Changed by `.set autoextend' and `.set noautoextend'. */
179 /* This is the struct we use to hold the current set of options. Note
180 that we must set the isa and mips16 fields to -1 to indicate that
181 they have not been initialized. */
183 static struct mips_set_options mips_opts
= { -1, -1 };
185 /* These variables are filled in with the masks of registers used.
186 The object format code reads them and puts them in the appropriate
188 unsigned long mips_gprmask
;
189 unsigned long mips_cprmask
[4];
191 /* MIPS ISA we are using for this output file. */
192 static int file_mips_isa
;
194 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
195 static int mips_cpu
= -1;
197 /* Whether the 4650 instructions (mad/madu) are permitted. */
198 static int mips_4650
= -1;
200 /* Whether the 4010 instructions are permitted. */
201 static int mips_4010
= -1;
203 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
204 static int mips_4100
= -1;
206 /* start-sanitize-r5900 */
207 /* Whether Toshiba r5900 instructions are permitted. */
208 static int mips_5900
= -1;
209 /* end-sanitize-r5900 */
211 /* Whether Toshiba r3900 instructions are permitted. */
212 static int mips_3900
= -1;
214 /* start-sanitize-tx19 */
215 /* The tx19 (r1900) is a mips16 decoder with a tx39(r3900) behind it.
216 The tx19 related options and configuration bits are handled by
218 /* end-sanitize-tx19 */
220 /* Whether the processor uses hardware interlocks to protect
221 reads from the HI and LO registers, and thus does not
222 require nops to be inserted. */
223 #define hilo_interlocks (mips_4010 || mips_cpu == 4300 || mips_3900)
225 /* Whether the processor uses hardware interlocks to protect reads
226 from the GPRs, and thus does not require nops to be inserted. */
227 #define gpr_interlocks (mips_opts.isa >= 2 || mips_3900)
229 /* As with other "interlocks" this is used by hardware that has FP
230 (co-processor) interlocks. */
231 /* Itbl support may require additional care here. */
232 #define cop_interlocks (mips_cpu == 4300)
234 /* MIPS PIC level. */
238 /* Do not generate PIC code. */
241 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
242 not sure what it is supposed to do. */
245 /* Generate PIC code as in the SVR4 MIPS ABI. */
248 /* Generate PIC code without using a global offset table: the data
249 segment has a maximum size of 64K, all data references are off
250 the $gp register, and all text references are PC relative. This
251 is used on some embedded systems. */
255 static enum mips_pic_level mips_pic
;
257 /* 1 if we should generate 32 bit offsets from the GP register in
258 SVR4_PIC mode. Currently has no meaning in other modes. */
259 static int mips_big_got
;
261 /* 1 if trap instructions should used for overflow rather than break
263 static int mips_trap
;
265 /* Non-zero if any .set noreorder directives were used. */
267 static int mips_any_noreorder
;
269 /* The size of the small data section. */
270 static int g_switch_value
= 8;
271 /* Whether the -G option was used. */
272 static int g_switch_seen
= 0;
277 /* If we can determine in advance that GP optimization won't be
278 possible, we can skip the relaxation stuff that tries to produce
279 GP-relative references. This makes delay slot optimization work
282 This function can only provide a guess, but it seems to work for
283 gcc output. If it guesses wrong, the only loss should be in
284 efficiency; it shouldn't introduce any bugs.
286 I don't know if a fix is needed for the SVR4_PIC mode. I've only
287 fixed it for the non-PIC mode. KR 95/04/07 */
288 static int nopic_need_relax
PARAMS ((symbolS
*, int));
290 /* handle of the OPCODE hash table */
291 static struct hash_control
*op_hash
= NULL
;
293 /* The opcode hash table we use for the mips16. */
294 static struct hash_control
*mips16_op_hash
= NULL
;
296 /* This array holds the chars that always start a comment. If the
297 pre-processor is disabled, these aren't very useful */
298 const char comment_chars
[] = "#";
300 /* This array holds the chars that only start a comment at the beginning of
301 a line. If the line seems to have the form '# 123 filename'
302 .line and .file directives will appear in the pre-processed output */
303 /* Note that input_file.c hand checks for '#' at the beginning of the
304 first line of the input file. This is because the compiler outputs
305 #NO_APP at the beginning of its output. */
306 /* Also note that C style comments are always supported. */
307 const char line_comment_chars
[] = "#";
309 /* This array holds machine specific line separator characters. */
310 const char line_separator_chars
[] = "";
312 /* Chars that can be used to separate mant from exp in floating point nums */
313 const char EXP_CHARS
[] = "eE";
315 /* Chars that mean this number is a floating point constant */
318 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
320 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
321 changed in read.c . Ideally it shouldn't have to know about it at all,
322 but nothing is ideal around here.
325 static char *insn_error
;
327 static int auto_align
= 1;
329 /* When outputting SVR4 PIC code, the assembler needs to know the
330 offset in the stack frame from which to restore the $gp register.
331 This is set by the .cprestore pseudo-op, and saved in this
333 static offsetT mips_cprestore_offset
= -1;
335 /* This is the register which holds the stack frame, as set by the
336 .frame pseudo-op. This is needed to implement .cprestore. */
337 static int mips_frame_reg
= SP
;
339 /* To output NOP instructions correctly, we need to keep information
340 about the previous two instructions. */
342 /* Whether we are optimizing. The default value of 2 means to remove
343 unneeded NOPs and swap branch instructions when possible. A value
344 of 1 means to not swap branches. A value of 0 means to always
346 static int mips_optimize
= 2;
348 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
349 equivalent to seeing no -g option at all. */
350 static int mips_debug
= 0;
352 /* The previous instruction. */
353 static struct mips_cl_insn prev_insn
;
355 /* The instruction before prev_insn. */
356 static struct mips_cl_insn prev_prev_insn
;
358 /* If we don't want information for prev_insn or prev_prev_insn, we
359 point the insn_mo field at this dummy integer. */
360 static const struct mips_opcode dummy_opcode
= { 0 };
362 /* Non-zero if prev_insn is valid. */
363 static int prev_insn_valid
;
365 /* The frag for the previous instruction. */
366 static struct frag
*prev_insn_frag
;
368 /* The offset into prev_insn_frag for the previous instruction. */
369 static long prev_insn_where
;
371 /* The reloc type for the previous instruction, if any. */
372 static bfd_reloc_code_real_type prev_insn_reloc_type
;
374 /* The reloc for the previous instruction, if any. */
375 static fixS
*prev_insn_fixp
;
377 /* Non-zero if the previous instruction was in a delay slot. */
378 static int prev_insn_is_delay_slot
;
380 /* Non-zero if the previous instruction was in a .set noreorder. */
381 static int prev_insn_unreordered
;
383 /* Non-zero if the previous instruction uses an extend opcode (if
385 static int prev_insn_extended
;
387 /* Non-zero if the previous previous instruction was in a .set
389 static int prev_prev_insn_unreordered
;
391 /* If this is set, it points to a frag holding nop instructions which
392 were inserted before the start of a noreorder section. If those
393 nops turn out to be unnecessary, the size of the frag can be
395 static fragS
*prev_nop_frag
;
397 /* The number of nop instructions we created in prev_nop_frag. */
398 static int prev_nop_frag_holds
;
400 /* The number of nop instructions that we know we need in
402 static int prev_nop_frag_required
;
404 /* The number of instructions we've seen since prev_nop_frag. */
405 static int prev_nop_frag_since
;
407 /* For ECOFF and ELF, relocations against symbols are done in two
408 parts, with a HI relocation and a LO relocation. Each relocation
409 has only 16 bits of space to store an addend. This means that in
410 order for the linker to handle carries correctly, it must be able
411 to locate both the HI and the LO relocation. This means that the
412 relocations must appear in order in the relocation table.
414 In order to implement this, we keep track of each unmatched HI
415 relocation. We then sort them so that they immediately precede the
416 corresponding LO relocation. */
421 struct mips_hi_fixup
*next
;
424 /* The section this fixup is in. */
428 /* The list of unmatched HI relocs. */
430 static struct mips_hi_fixup
*mips_hi_fixup_list
;
432 /* Map normal MIPS register numbers to mips16 register numbers. */
434 #define X ILLEGAL_REG
435 static const int mips32_to_16_reg_map
[] =
437 X
, X
, 2, 3, 4, 5, 6, 7,
438 X
, X
, X
, X
, X
, X
, X
, X
,
439 0, 1, X
, X
, X
, X
, X
, X
,
440 X
, X
, X
, X
, X
, X
, X
, X
444 /* Map mips16 register numbers to normal MIPS register numbers. */
446 static const int mips16_to_32_reg_map
[] =
448 16, 17, 2, 3, 4, 5, 6, 7
451 /* Since the MIPS does not have multiple forms of PC relative
452 instructions, we do not have to do relaxing as is done on other
453 platforms. However, we do have to handle GP relative addressing
454 correctly, which turns out to be a similar problem.
456 Every macro that refers to a symbol can occur in (at least) two
457 forms, one with GP relative addressing and one without. For
458 example, loading a global variable into a register generally uses
459 a macro instruction like this:
461 If i can be addressed off the GP register (this is true if it is in
462 the .sbss or .sdata section, or if it is known to be smaller than
463 the -G argument) this will generate the following instruction:
465 This instruction will use a GPREL reloc. If i can not be addressed
466 off the GP register, the following instruction sequence will be used:
469 In this case the first instruction will have a HI16 reloc, and the
470 second reloc will have a LO16 reloc. Both relocs will be against
473 The issue here is that we may not know whether i is GP addressable
474 until after we see the instruction that uses it. Therefore, we
475 want to be able to choose the final instruction sequence only at
476 the end of the assembly. This is similar to the way other
477 platforms choose the size of a PC relative instruction only at the
480 When generating position independent code we do not use GP
481 addressing in quite the same way, but the issue still arises as
482 external symbols and local symbols must be handled differently.
484 We handle these issues by actually generating both possible
485 instruction sequences. The longer one is put in a frag_var with
486 type rs_machine_dependent. We encode what to do with the frag in
487 the subtype field. We encode (1) the number of existing bytes to
488 replace, (2) the number of new bytes to use, (3) the offset from
489 the start of the existing bytes to the first reloc we must generate
490 (that is, the offset is applied from the start of the existing
491 bytes after they are replaced by the new bytes, if any), (4) the
492 offset from the start of the existing bytes to the second reloc,
493 (5) whether a third reloc is needed (the third reloc is always four
494 bytes after the second reloc), and (6) whether to warn if this
495 variant is used (this is sometimes needed if .set nomacro or .set
496 noat is in effect). All these numbers are reasonably small.
498 Generating two instruction sequences must be handled carefully to
499 ensure that delay slots are handled correctly. Fortunately, there
500 are a limited number of cases. When the second instruction
501 sequence is generated, append_insn is directed to maintain the
502 existing delay slot information, so it continues to apply to any
503 code after the second instruction sequence. This means that the
504 second instruction sequence must not impose any requirements not
505 required by the first instruction sequence.
507 These variant frags are then handled in functions called by the
508 machine independent code. md_estimate_size_before_relax returns
509 the final size of the frag. md_convert_frag sets up the final form
510 of the frag. tc_gen_reloc adjust the first reloc and adds a second
512 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
516 | (((reloc1) + 64) << 9) \
517 | (((reloc2) + 64) << 2) \
518 | ((reloc3) ? (1 << 1) : 0) \
520 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
521 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
522 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
523 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
524 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
525 #define RELAX_WARN(i) ((i) & 1)
527 /* For mips16 code, we use an entirely different form of relaxation.
528 mips16 supports two versions of most instructions which take
529 immediate values: a small one which takes some small value, and a
530 larger one which takes a 16 bit value. Since branches also follow
531 this pattern, relaxing these values is required.
533 We can assemble both mips16 and normal MIPS code in a single
534 object. Therefore, we need to support this type of relaxation at
535 the same time that we support the relaxation described above. We
536 use the high bit of the subtype field to distinguish these cases.
538 The information we store for this type of relaxation is the
539 argument code found in the opcode file for this relocation, whether
540 the user explicitly requested a small or extended form, and whether
541 the relocation is in a jump or jal delay slot. That tells us the
542 size of the value, and how it should be stored. We also store
543 whether the fragment is considered to be extended or not. We also
544 store whether this is known to be a branch to a different section,
545 whether we have tried to relax this frag yet, and whether we have
546 ever extended a PC relative fragment because of a shift count. */
547 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
550 | ((small) ? 0x100 : 0) \
551 | ((ext) ? 0x200 : 0) \
552 | ((dslot) ? 0x400 : 0) \
553 | ((jal_dslot) ? 0x800 : 0))
554 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
555 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
556 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
557 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
558 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
559 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
560 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
561 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
562 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
563 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
564 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
565 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
567 /* Prototypes for static functions. */
570 #define internalError() \
571 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
573 #define internalError() as_fatal ("MIPS internal Error");
576 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
578 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
579 unsigned int reg
, enum mips_regclass
class));
580 static int reg_needs_delay
PARAMS ((int));
581 static void mips16_mark_labels
PARAMS ((void));
582 static void append_insn
PARAMS ((char *place
,
583 struct mips_cl_insn
* ip
,
585 bfd_reloc_code_real_type r
,
587 static void mips_no_prev_insn
PARAMS ((int));
588 static void mips_emit_delays
PARAMS ((boolean
));
590 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
591 const char *name
, const char *fmt
,
594 static void macro_build ();
596 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
597 const char *, const char *,
599 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
600 expressionS
* ep
, int regnum
));
601 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
602 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
604 static void load_register
PARAMS ((int *, int, expressionS
*, int));
605 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
606 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
607 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
608 #ifdef LOSING_COMPILER
609 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
611 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
612 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
613 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
614 boolean
, boolean
, unsigned long *,
615 boolean
*, unsigned short *));
616 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
617 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
618 static symbolS
*get_symbol
PARAMS ((void));
619 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
620 static void s_align
PARAMS ((int));
621 static void s_change_sec
PARAMS ((int));
622 static void s_cons
PARAMS ((int));
623 static void s_float_cons
PARAMS ((int));
624 static void s_mips_globl
PARAMS ((int));
625 static void s_option
PARAMS ((int));
626 static void s_mipsset
PARAMS ((int));
627 static void s_abicalls
PARAMS ((int));
628 static void s_cpload
PARAMS ((int));
629 static void s_cprestore
PARAMS ((int));
630 static void s_gpword
PARAMS ((int));
631 static void s_cpadd
PARAMS ((int));
632 static void s_insn
PARAMS ((int));
633 static void md_obj_begin
PARAMS ((void));
634 static void md_obj_end
PARAMS ((void));
635 static long get_number
PARAMS ((void));
636 static void s_ent
PARAMS ((int));
637 static void s_mipsend
PARAMS ((int));
638 static void s_file
PARAMS ((int));
639 static void s_mips_stab
PARAMS ((int));
640 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
644 The following pseudo-ops from the Kane and Heinrich MIPS book
645 should be defined here, but are currently unsupported: .alias,
646 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
648 The following pseudo-ops from the Kane and Heinrich MIPS book are
649 specific to the type of debugging information being generated, and
650 should be defined by the object format: .aent, .begin, .bend,
651 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
654 The following pseudo-ops from the Kane and Heinrich MIPS book are
655 not MIPS CPU specific, but are also not specific to the object file
656 format. This file is probably the best place to define them, but
657 they are not currently supported: .asm0, .endr, .lab, .repeat,
658 .struct, .weakext. */
660 static const pseudo_typeS mips_pseudo_table
[] =
662 /* MIPS specific pseudo-ops. */
663 {"option", s_option
, 0},
664 {"set", s_mipsset
, 0},
665 {"rdata", s_change_sec
, 'r'},
666 {"sdata", s_change_sec
, 's'},
667 {"livereg", s_ignore
, 0},
668 {"abicalls", s_abicalls
, 0},
669 {"cpload", s_cpload
, 0},
670 {"cprestore", s_cprestore
, 0},
671 {"gpword", s_gpword
, 0},
672 {"cpadd", s_cpadd
, 0},
675 /* Relatively generic pseudo-ops that happen to be used on MIPS
677 {"asciiz", stringer
, 1},
678 {"bss", s_change_sec
, 'b'},
681 {"dword", s_cons
, 3},
683 /* These pseudo-ops are defined in read.c, but must be overridden
684 here for one reason or another. */
685 {"align", s_align
, 0},
687 {"data", s_change_sec
, 'd'},
688 {"double", s_float_cons
, 'd'},
689 {"float", s_float_cons
, 'f'},
690 {"globl", s_mips_globl
, 0},
691 {"global", s_mips_globl
, 0},
692 {"hword", s_cons
, 1},
697 {"short", s_cons
, 1},
698 {"single", s_float_cons
, 'f'},
699 {"stabn", s_mips_stab
, 'n'},
700 {"text", s_change_sec
, 't'},
705 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
706 /* These pseudo-ops should be defined by the object file format.
707 However, a.out doesn't support them, so we have versions here. */
709 {"bgnb", s_ignore
, 0},
710 {"end", s_mipsend
, 0},
711 {"endb", s_ignore
, 0},
714 {"fmask", s_ignore
, 'F'},
715 {"frame", s_ignore
, 0},
716 {"loc", s_ignore
, 0},
717 {"mask", s_ignore
, 'R'},
718 {"verstamp", s_ignore
, 0},
722 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
727 pop_insert (mips_pseudo_table
);
728 if (! ECOFF_DEBUGGING
)
729 pop_insert (mips_nonecoff_pseudo_table
);
732 /* Symbols labelling the current insn. */
734 struct insn_label_list
736 struct insn_label_list
*next
;
740 static struct insn_label_list
*insn_labels
;
741 static struct insn_label_list
*free_insn_labels
;
743 static void mips_clear_insn_labels
PARAMS ((void));
746 mips_clear_insn_labels ()
748 register struct insn_label_list
**pl
;
750 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
756 static char *expr_end
;
758 /* Expressions which appear in instructions. These are set by
761 static expressionS imm_expr
;
762 static expressionS offset_expr
;
764 /* Relocs associated with imm_expr and offset_expr. */
766 static bfd_reloc_code_real_type imm_reloc
;
767 static bfd_reloc_code_real_type offset_reloc
;
769 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
771 static boolean imm_unmatched_hi
;
773 /* These are set by mips16_ip if an explicit extension is used. */
775 static boolean mips16_small
, mips16_ext
;
778 * This function is called once, at assembler startup time. It should
779 * set up all the tables, etc. that the MD part of the assembler will need.
785 register const char *retval
= NULL
;
786 register unsigned int i
= 0;
788 if (mips_opts
.isa
== -1)
794 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
796 a
= xmalloc (sizeof TARGET_CPU
);
797 strcpy (a
, TARGET_CPU
);
798 a
[(sizeof TARGET_CPU
) - 3] = '\0';
802 if (strcmp (cpu
, "mips") == 0)
808 else if (strcmp (cpu
, "r3900") == 0
809 || strcmp (cpu
, "mipstx39") == 0
810 /* start-sanitize-tx19 */
811 || strcmp (cpu
, "r1900") == 0
812 || strcmp (cpu
, "mipstx19") == 0
813 /* end-sanitize-tx19 */
822 else if (strcmp (cpu
, "r6000") == 0
823 || strcmp (cpu
, "mips2") == 0)
829 else if (strcmp (cpu
, "mips64") == 0
830 || strcmp (cpu
, "r4000") == 0
831 || strcmp (cpu
, "mips3") == 0)
837 else if (strcmp (cpu
, "r4400") == 0)
843 else if (strcmp (cpu
, "mips64orion") == 0
844 || strcmp (cpu
, "r4600") == 0)
850 else if (strcmp (cpu
, "r4650") == 0)
858 else if (strcmp (cpu
, "mips64vr4300") == 0)
864 else if (strcmp (cpu
, "mips64vr4100") == 0)
872 else if (strcmp (cpu
, "r4010") == 0)
880 else if (strcmp (cpu
, "r5000") == 0
881 || strcmp (cpu
, "mips64vr5000") == 0)
887 /* start-sanitize-r5900 */
888 else if (strcmp (cpu
, "r5900") == 0
889 || strcmp (cpu
, "mips64r5900") == 0
890 || strcmp (cpu
, "mips64r5900el") == 0)
898 /* end-sanitize-r5900 */
899 else if (strcmp (cpu
, "r8000") == 0
900 || strcmp (cpu
, "mips4") == 0)
906 else if (strcmp (cpu
, "r10000") == 0)
912 else if (strcmp (cpu
, "mips16") == 0)
916 mips_cpu
= 0; /* FIXME */
929 if (mips_opts
.mips16
< 0)
931 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
932 mips_opts
.mips16
= 1;
934 mips_opts
.mips16
= 0;
946 /* start-sanitize-r5900 */
949 /* end-sanitize-r5900 */
954 if (mips_opts
.isa
< 2 && mips_trap
)
955 as_bad ("trap exception not supported at ISA 1");
957 switch (mips_opts
.isa
)
960 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
963 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
966 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
969 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
973 as_warn ("Could not set architecture and machine");
975 file_mips_isa
= mips_opts
.isa
;
977 op_hash
= hash_new ();
979 for (i
= 0; i
< NUMOPCODES
;)
981 const char *name
= mips_opcodes
[i
].name
;
983 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
986 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
987 mips_opcodes
[i
].name
, retval
);
988 as_fatal ("Broken assembler. No assembly attempted.");
992 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
993 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
994 != mips_opcodes
[i
].match
))
996 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
997 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
998 as_fatal ("Broken assembler. No assembly attempted.");
1002 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1005 mips16_op_hash
= hash_new ();
1008 while (i
< bfd_mips16_num_opcodes
)
1010 const char *name
= mips16_opcodes
[i
].name
;
1012 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1014 as_fatal ("internal error: can't hash `%s': %s\n",
1015 mips16_opcodes
[i
].name
, retval
);
1018 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1019 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1020 != mips16_opcodes
[i
].match
))
1021 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
1022 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1025 while (i
< bfd_mips16_num_opcodes
1026 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1029 /* We add all the general register names to the symbol table. This
1030 helps us detect invalid uses of them. */
1031 for (i
= 0; i
< 32; i
++)
1035 sprintf (buf
, "$%d", i
);
1036 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1037 &zero_address_frag
));
1039 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1040 &zero_address_frag
));
1041 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1042 &zero_address_frag
));
1043 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1044 &zero_address_frag
));
1045 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1046 &zero_address_frag
));
1047 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1048 &zero_address_frag
));
1049 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1050 &zero_address_frag
));
1051 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1052 &zero_address_frag
));
1054 mips_no_prev_insn (false);
1057 mips_cprmask
[0] = 0;
1058 mips_cprmask
[1] = 0;
1059 mips_cprmask
[2] = 0;
1060 mips_cprmask
[3] = 0;
1062 /* set the default alignment for the text section (2**2) */
1063 record_alignment (text_section
, 2);
1065 if (USE_GLOBAL_POINTER_OPT
)
1066 bfd_set_gp_size (stdoutput
, g_switch_value
);
1068 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1070 /* On a native system, sections must be aligned to 16 byte
1071 boundaries. When configured for an embedded ELF target, we
1073 if (strcmp (TARGET_OS
, "elf") != 0)
1075 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1076 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1077 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1080 /* Create a .reginfo section for register masks and a .mdebug
1081 section for debugging information. */
1089 subseg
= now_subseg
;
1091 /* The ABI says this section should be loaded so that the
1092 running program can access it. However, we don't load it
1093 if we are configured for an embedded target */
1094 flags
= SEC_READONLY
| SEC_DATA
;
1095 if (strcmp (TARGET_OS
, "elf") != 0)
1096 flags
|= SEC_ALLOC
| SEC_LOAD
;
1100 sec
= subseg_new (".reginfo", (subsegT
) 0);
1103 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1104 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1107 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1112 /* The 64-bit ABI uses a .MIPS.options section rather than
1113 .reginfo section. */
1114 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1115 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1116 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1119 /* Set up the option header. */
1121 Elf_Internal_Options opthdr
;
1124 opthdr
.kind
= ODK_REGINFO
;
1125 opthdr
.size
= (sizeof (Elf_External_Options
)
1126 + sizeof (Elf64_External_RegInfo
));
1129 f
= frag_more (sizeof (Elf_External_Options
));
1130 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1131 (Elf_External_Options
*) f
);
1133 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1138 if (ECOFF_DEBUGGING
)
1140 sec
= subseg_new (".mdebug", (subsegT
) 0);
1141 (void) bfd_set_section_flags (stdoutput
, sec
,
1142 SEC_HAS_CONTENTS
| SEC_READONLY
);
1143 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1146 subseg_set (seg
, subseg
);
1150 if (! ECOFF_DEBUGGING
)
1157 if (! ECOFF_DEBUGGING
)
1165 struct mips_cl_insn insn
;
1167 imm_expr
.X_op
= O_absent
;
1168 imm_reloc
= BFD_RELOC_UNUSED
;
1169 imm_unmatched_hi
= false;
1170 offset_expr
.X_op
= O_absent
;
1171 offset_reloc
= BFD_RELOC_UNUSED
;
1173 if (mips_opts
.mips16
)
1174 mips16_ip (str
, &insn
);
1177 mips_ip (str
, &insn
);
1178 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1179 str
, insn
.insn_opcode
));
1184 as_bad ("%s `%s'", insn_error
, str
);
1188 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1190 if (mips_opts
.mips16
)
1191 mips16_macro (&insn
);
1197 if (imm_expr
.X_op
!= O_absent
)
1198 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1200 else if (offset_expr
.X_op
!= O_absent
)
1201 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1203 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1207 /* See whether instruction IP reads register REG. CLASS is the type
1211 insn_uses_reg (ip
, reg
, class)
1212 struct mips_cl_insn
*ip
;
1214 enum mips_regclass
class;
1216 if (class == MIPS16_REG
)
1218 assert (mips_opts
.mips16
);
1219 reg
= mips16_to_32_reg_map
[reg
];
1220 class = MIPS_GR_REG
;
1223 /* Don't report on general register 0, since it never changes. */
1224 if (class == MIPS_GR_REG
&& reg
== 0)
1227 if (class == MIPS_FP_REG
)
1229 assert (! mips_opts
.mips16
);
1230 /* If we are called with either $f0 or $f1, we must check $f0.
1231 This is not optimal, because it will introduce an unnecessary
1232 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1233 need to distinguish reading both $f0 and $f1 or just one of
1234 them. Note that we don't have to check the other way,
1235 because there is no instruction that sets both $f0 and $f1
1236 and requires a delay. */
1237 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1238 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1239 == (reg
&~ (unsigned) 1)))
1241 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1242 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1243 == (reg
&~ (unsigned) 1)))
1246 else if (! mips_opts
.mips16
)
1248 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1249 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1251 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1252 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1257 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1258 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1259 & MIPS16OP_MASK_RX
)]
1262 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1263 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1264 & MIPS16OP_MASK_RY
)]
1267 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1268 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1269 & MIPS16OP_MASK_MOVE32Z
)]
1272 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1274 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1276 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1278 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1279 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1280 & MIPS16OP_MASK_REGR32
) == reg
)
1287 /* This function returns true if modifying a register requires a
1291 reg_needs_delay (reg
)
1294 unsigned long prev_pinfo
;
1296 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1297 if (! mips_opts
.noreorder
1298 && mips_opts
.isa
< 4
1299 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1300 || (! gpr_interlocks
1301 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1303 /* A load from a coprocessor or from memory. All load
1304 delays delay the use of general register rt for one
1305 instruction on the r3000. The r6000 and r4000 use
1307 /* Itbl support may require additional care here. */
1308 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1309 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1316 /* Mark instruction labels in mips16 mode. This permits the linker to
1317 handle them specially, such as generating jalx instructions when
1318 needed. We also make them odd for the duration of the assembly, in
1319 order to generate the right sort of code. We will make them even
1320 in the adjust_symtab routine, while leaving them marked. This is
1321 convenient for the debugger and the disassembler. The linker knows
1322 to make them odd again. */
1325 mips16_mark_labels ()
1327 if (mips_opts
.mips16
)
1329 struct insn_label_list
*l
;
1331 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1334 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1335 S_SET_OTHER (l
->label
, STO_MIPS16
);
1337 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
1338 ++l
->label
->sy_value
.X_add_number
;
1343 /* Output an instruction. PLACE is where to put the instruction; if
1344 it is NULL, this uses frag_more to get room. IP is the instruction
1345 information. ADDRESS_EXPR is an operand of the instruction to be
1346 used with RELOC_TYPE. */
1349 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1351 struct mips_cl_insn
*ip
;
1352 expressionS
*address_expr
;
1353 bfd_reloc_code_real_type reloc_type
;
1354 boolean unmatched_hi
;
1356 register unsigned long prev_pinfo
, pinfo
;
1361 /* Mark instruction labels in mips16 mode. */
1362 if (mips_opts
.mips16
)
1363 mips16_mark_labels ();
1365 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1366 pinfo
= ip
->insn_mo
->pinfo
;
1368 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1372 /* If the previous insn required any delay slots, see if we need
1373 to insert a NOP or two. There are eight kinds of possible
1374 hazards, of which an instruction can have at most one type.
1375 (1) a load from memory delay
1376 (2) a load from a coprocessor delay
1377 (3) an unconditional branch delay
1378 (4) a conditional branch delay
1379 (5) a move to coprocessor register delay
1380 (6) a load coprocessor register from memory delay
1381 (7) a coprocessor condition code delay
1382 (8) a HI/LO special register delay
1384 There are a lot of optimizations we could do that we don't.
1385 In particular, we do not, in general, reorder instructions.
1386 If you use gcc with optimization, it will reorder
1387 instructions and generally do much more optimization then we
1388 do here; repeating all that work in the assembler would only
1389 benefit hand written assembly code, and does not seem worth
1392 /* This is how a NOP is emitted. */
1393 #define emit_nop() \
1395 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1396 : md_number_to_chars (frag_more (4), 0, 4))
1398 /* The previous insn might require a delay slot, depending upon
1399 the contents of the current insn. */
1400 if (! mips_opts
.mips16
1401 && mips_opts
.isa
< 4
1402 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1403 && ! cop_interlocks
)
1404 || (! gpr_interlocks
1405 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1407 /* A load from a coprocessor or from memory. All load
1408 delays delay the use of general register rt for one
1409 instruction on the r3000. The r6000 and r4000 use
1411 /* Itbl support may require additional care here. */
1412 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1413 if (mips_optimize
== 0
1414 || insn_uses_reg (ip
,
1415 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1420 else if (! mips_opts
.mips16
1421 && mips_opts
.isa
< 4
1422 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1423 && ! cop_interlocks
)
1424 || (mips_opts
.isa
< 2
1425 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1427 /* A generic coprocessor delay. The previous instruction
1428 modified a coprocessor general or control register. If
1429 it modified a control register, we need to avoid any
1430 coprocessor instruction (this is probably not always
1431 required, but it sometimes is). If it modified a general
1432 register, we avoid using that register.
1434 On the r6000 and r4000 loading a coprocessor register
1435 from memory is interlocked, and does not require a delay.
1437 This case is not handled very well. There is no special
1438 knowledge of CP0 handling, and the coprocessors other
1439 than the floating point unit are not distinguished at
1441 /* Itbl support may require additional care here. FIXME!
1442 Need to modify this to include knowledge about
1443 user specified delays! */
1444 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1446 if (mips_optimize
== 0
1447 || insn_uses_reg (ip
,
1448 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1453 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1455 if (mips_optimize
== 0
1456 || insn_uses_reg (ip
,
1457 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1464 /* We don't know exactly what the previous instruction
1465 does. If the current instruction uses a coprocessor
1466 register, we must insert a NOP. If previous
1467 instruction may set the condition codes, and the
1468 current instruction uses them, we must insert two
1470 /* Itbl support may require additional care here. */
1471 if (mips_optimize
== 0
1472 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1473 && (pinfo
& INSN_READ_COND_CODE
)))
1475 else if (pinfo
& INSN_COP
)
1479 else if (! mips_opts
.mips16
1480 && mips_opts
.isa
< 4
1481 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1482 && ! cop_interlocks
)
1484 /* The previous instruction sets the coprocessor condition
1485 codes, but does not require a general coprocessor delay
1486 (this means it is a floating point comparison
1487 instruction). If this instruction uses the condition
1488 codes, we need to insert a single NOP. */
1489 /* Itbl support may require additional care here. */
1490 if (mips_optimize
== 0
1491 || (pinfo
& INSN_READ_COND_CODE
))
1494 else if (prev_pinfo
& INSN_READ_LO
)
1496 /* The previous instruction reads the LO register; if the
1497 current instruction writes to the LO register, we must
1498 insert two NOPS. Some newer processors have interlocks. */
1499 if (! hilo_interlocks
1500 && (mips_optimize
== 0
1501 || (pinfo
& INSN_WRITE_LO
)))
1504 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1506 /* The previous instruction reads the HI register; if the
1507 current instruction writes to the HI register, we must
1508 insert a NOP. Some newer processors have interlocks. */
1509 if (! hilo_interlocks
1510 && (mips_optimize
== 0
1511 || (pinfo
& INSN_WRITE_HI
)))
1515 /* If the previous instruction was in a noreorder section, then
1516 we don't want to insert the nop after all. */
1517 /* Itbl support may require additional care here. */
1518 if (prev_insn_unreordered
)
1521 /* There are two cases which require two intervening
1522 instructions: 1) setting the condition codes using a move to
1523 coprocessor instruction which requires a general coprocessor
1524 delay and then reading the condition codes 2) reading the HI
1525 or LO register and then writing to it (except on processors
1526 which have interlocks). If we are not already emitting a NOP
1527 instruction, we must check for these cases compared to the
1528 instruction previous to the previous instruction. */
1529 if ((! mips_opts
.mips16
1530 && mips_opts
.isa
< 4
1531 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1532 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1533 && (pinfo
& INSN_READ_COND_CODE
)
1534 && ! cop_interlocks
)
1535 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1536 && (pinfo
& INSN_WRITE_LO
)
1537 && ! hilo_interlocks
)
1538 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1539 && (pinfo
& INSN_WRITE_HI
)
1540 && ! hilo_interlocks
))
1545 if (prev_prev_insn_unreordered
)
1548 if (prev_prev_nop
&& nops
== 0)
1551 /* If we are being given a nop instruction, don't bother with
1552 one of the nops we would otherwise output. This will only
1553 happen when a nop instruction is used with mips_optimize set
1556 && ! mips_opts
.noreorder
1557 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1560 /* Now emit the right number of NOP instructions. */
1561 if (nops
> 0 && ! mips_opts
.noreorder
)
1564 unsigned long old_frag_offset
;
1566 struct insn_label_list
*l
;
1568 old_frag
= frag_now
;
1569 old_frag_offset
= frag_now_fix ();
1571 for (i
= 0; i
< nops
; i
++)
1576 listing_prev_line ();
1577 /* We may be at the start of a variant frag. In case we
1578 are, make sure there is enough space for the frag
1579 after the frags created by listing_prev_line. The
1580 argument to frag_grow here must be at least as large
1581 as the argument to all other calls to frag_grow in
1582 this file. We don't have to worry about being in the
1583 middle of a variant frag, because the variants insert
1584 all needed nop instructions themselves. */
1588 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1590 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1591 l
->label
->sy_frag
= frag_now
;
1592 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1593 /* mips16 text labels are stored as odd. */
1594 if (mips_opts
.mips16
)
1595 ++l
->label
->sy_value
.X_add_number
;
1598 #ifndef NO_ECOFF_DEBUGGING
1599 if (ECOFF_DEBUGGING
)
1600 ecoff_fix_loc (old_frag
, old_frag_offset
);
1603 else if (prev_nop_frag
!= NULL
)
1605 /* We have a frag holding nops we may be able to remove. If
1606 we don't need any nops, we can decrease the size of
1607 prev_nop_frag by the size of one instruction. If we do
1608 need some nops, we count them in prev_nops_required. */
1609 if (prev_nop_frag_since
== 0)
1613 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1614 --prev_nop_frag_holds
;
1617 prev_nop_frag_required
+= nops
;
1621 if (prev_prev_nop
== 0)
1623 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1624 --prev_nop_frag_holds
;
1627 ++prev_nop_frag_required
;
1630 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1631 prev_nop_frag
= NULL
;
1633 ++prev_nop_frag_since
;
1635 /* Sanity check: by the time we reach the second instruction
1636 after prev_nop_frag, we should have used up all the nops
1637 one way or another. */
1638 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1642 if (reloc_type
> BFD_RELOC_UNUSED
)
1644 /* We need to set up a variant frag. */
1645 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1646 f
= frag_var (rs_machine_dependent
, 4, 0,
1647 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1648 mips16_small
, mips16_ext
,
1650 & INSN_UNCOND_BRANCH_DELAY
),
1651 (prev_insn_reloc_type
1652 == BFD_RELOC_MIPS16_JMP
)),
1653 make_expr_symbol (address_expr
), (offsetT
) 0,
1656 else if (place
!= NULL
)
1658 else if (mips_opts
.mips16
1660 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1662 /* Make sure there is enough room to swap this instruction with
1663 a following jump instruction. */
1669 if (mips_opts
.mips16
1670 && mips_opts
.noreorder
1671 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1672 as_warn ("extended instruction in delay slot");
1678 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1680 if (address_expr
->X_op
== O_constant
)
1685 ip
->insn_opcode
|= address_expr
->X_add_number
;
1688 case BFD_RELOC_LO16
:
1689 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1692 case BFD_RELOC_MIPS_JMP
:
1693 if ((address_expr
->X_add_number
& 3) != 0)
1694 as_bad ("jump to misaligned address (0x%lx)",
1695 (unsigned long) address_expr
->X_add_number
);
1696 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1699 case BFD_RELOC_MIPS16_JMP
:
1700 if ((address_expr
->X_add_number
& 3) != 0)
1701 as_bad ("jump to misaligned address (0x%lx)",
1702 (unsigned long) address_expr
->X_add_number
);
1704 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1705 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1706 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1709 case BFD_RELOC_16_PCREL_S2
:
1719 /* Don't generate a reloc if we are writing into a variant
1723 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1725 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1729 struct mips_hi_fixup
*hi_fixup
;
1731 assert (reloc_type
== BFD_RELOC_HI16_S
);
1732 hi_fixup
= ((struct mips_hi_fixup
*)
1733 xmalloc (sizeof (struct mips_hi_fixup
)));
1734 hi_fixup
->fixp
= fixp
;
1735 hi_fixup
->seg
= now_seg
;
1736 hi_fixup
->next
= mips_hi_fixup_list
;
1737 mips_hi_fixup_list
= hi_fixup
;
1743 if (! mips_opts
.mips16
)
1744 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1745 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1747 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1748 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1754 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1757 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1760 /* Update the register mask information. */
1761 if (! mips_opts
.mips16
)
1763 if (pinfo
& INSN_WRITE_GPR_D
)
1764 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1765 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1766 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1767 if (pinfo
& INSN_READ_GPR_S
)
1768 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1769 if (pinfo
& INSN_WRITE_GPR_31
)
1770 mips_gprmask
|= 1 << 31;
1771 if (pinfo
& INSN_WRITE_FPR_D
)
1772 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1773 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1774 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1775 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1776 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1777 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1778 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1779 if (pinfo
& INSN_COP
)
1781 /* We don't keep enough information to sort these cases out.
1782 The itbl support does keep this information however, although
1783 we currently don't support itbl fprmats as part of the cop
1784 instruction. May want to add this support in the future. */
1786 /* Never set the bit for $0, which is always zero. */
1787 mips_gprmask
&=~ 1 << 0;
1791 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1792 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1793 & MIPS16OP_MASK_RX
);
1794 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1795 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1796 & MIPS16OP_MASK_RY
);
1797 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1798 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1799 & MIPS16OP_MASK_RZ
);
1800 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1801 mips_gprmask
|= 1 << TREG
;
1802 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1803 mips_gprmask
|= 1 << SP
;
1804 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1805 mips_gprmask
|= 1 << RA
;
1806 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1807 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1808 if (pinfo
& MIPS16_INSN_READ_Z
)
1809 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1810 & MIPS16OP_MASK_MOVE32Z
);
1811 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1812 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1813 & MIPS16OP_MASK_REGR32
);
1816 if (place
== NULL
&& ! mips_opts
.noreorder
)
1818 /* Filling the branch delay slot is more complex. We try to
1819 switch the branch with the previous instruction, which we can
1820 do if the previous instruction does not set up a condition
1821 that the branch tests and if the branch is not itself the
1822 target of any branch. */
1823 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1824 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1826 if (mips_optimize
< 2
1827 /* If we have seen .set volatile or .set nomove, don't
1829 || mips_opts
.nomove
!= 0
1830 /* If we had to emit any NOP instructions, then we
1831 already know we can not swap. */
1833 /* If we don't even know the previous insn, we can not
1835 || ! prev_insn_valid
1836 /* If the previous insn is already in a branch delay
1837 slot, then we can not swap. */
1838 || prev_insn_is_delay_slot
1839 /* If the previous previous insn was in a .set
1840 noreorder, we can't swap. Actually, the MIPS
1841 assembler will swap in this situation. However, gcc
1842 configured -with-gnu-as will generate code like
1848 in which we can not swap the bne and INSN. If gcc is
1849 not configured -with-gnu-as, it does not output the
1850 .set pseudo-ops. We don't have to check
1851 prev_insn_unreordered, because prev_insn_valid will
1852 be 0 in that case. We don't want to use
1853 prev_prev_insn_valid, because we do want to be able
1854 to swap at the start of a function. */
1855 || prev_prev_insn_unreordered
1856 /* If the branch is itself the target of a branch, we
1857 can not swap. We cheat on this; all we check for is
1858 whether there is a label on this instruction. If
1859 there are any branches to anything other than a
1860 label, users must use .set noreorder. */
1861 || insn_labels
!= NULL
1862 /* If the previous instruction is in a variant frag, we
1863 can not do the swap. This does not apply to the
1864 mips16, which uses variant frags for different
1866 || (! mips_opts
.mips16
1867 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1868 /* If the branch reads the condition codes, we don't
1869 even try to swap, because in the sequence
1874 we can not swap, and I don't feel like handling that
1876 || (! mips_opts
.mips16
1877 && mips_opts
.isa
< 4
1878 && (pinfo
& INSN_READ_COND_CODE
))
1879 /* We can not swap with an instruction that requires a
1880 delay slot, becase the target of the branch might
1881 interfere with that instruction. */
1882 || (! mips_opts
.mips16
1883 && mips_opts
.isa
< 4
1885 /* Itbl support may require additional care here. */
1886 & (INSN_LOAD_COPROC_DELAY
1887 | INSN_COPROC_MOVE_DELAY
1888 | INSN_WRITE_COND_CODE
)))
1889 || (! hilo_interlocks
1893 || (! mips_opts
.mips16
1895 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
1896 || (! mips_opts
.mips16
1897 && mips_opts
.isa
< 2
1898 /* Itbl support may require additional care here. */
1899 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
1900 /* We can not swap with a branch instruction. */
1902 & (INSN_UNCOND_BRANCH_DELAY
1903 | INSN_COND_BRANCH_DELAY
1904 | INSN_COND_BRANCH_LIKELY
))
1905 /* We do not swap with a trap instruction, since it
1906 complicates trap handlers to have the trap
1907 instruction be in a delay slot. */
1908 || (prev_pinfo
& INSN_TRAP
)
1909 /* If the branch reads a register that the previous
1910 instruction sets, we can not swap. */
1911 || (! mips_opts
.mips16
1912 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1913 && insn_uses_reg (ip
,
1914 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1917 || (! mips_opts
.mips16
1918 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1919 && insn_uses_reg (ip
,
1920 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1923 || (mips_opts
.mips16
1924 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1925 && insn_uses_reg (ip
,
1926 ((prev_insn
.insn_opcode
1928 & MIPS16OP_MASK_RX
),
1930 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1931 && insn_uses_reg (ip
,
1932 ((prev_insn
.insn_opcode
1934 & MIPS16OP_MASK_RY
),
1936 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1937 && insn_uses_reg (ip
,
1938 ((prev_insn
.insn_opcode
1940 & MIPS16OP_MASK_RZ
),
1942 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1943 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1944 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1945 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1946 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1947 && insn_uses_reg (ip
,
1948 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1951 /* If the branch writes a register that the previous
1952 instruction sets, we can not swap (we know that
1953 branches write only to RD or to $31). */
1954 || (! mips_opts
.mips16
1955 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1956 && (((pinfo
& INSN_WRITE_GPR_D
)
1957 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1958 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1959 || ((pinfo
& INSN_WRITE_GPR_31
)
1960 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1963 || (! mips_opts
.mips16
1964 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1965 && (((pinfo
& INSN_WRITE_GPR_D
)
1966 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1967 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1968 || ((pinfo
& INSN_WRITE_GPR_31
)
1969 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1972 || (mips_opts
.mips16
1973 && (pinfo
& MIPS16_INSN_WRITE_31
)
1974 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1975 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1976 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1978 /* If the branch writes a register that the previous
1979 instruction reads, we can not swap (we know that
1980 branches only write to RD or to $31). */
1981 || (! mips_opts
.mips16
1982 && (pinfo
& INSN_WRITE_GPR_D
)
1983 && insn_uses_reg (&prev_insn
,
1984 ((ip
->insn_opcode
>> OP_SH_RD
)
1987 || (! mips_opts
.mips16
1988 && (pinfo
& INSN_WRITE_GPR_31
)
1989 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1990 || (mips_opts
.mips16
1991 && (pinfo
& MIPS16_INSN_WRITE_31
)
1992 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1993 /* If we are generating embedded PIC code, the branch
1994 might be expanded into a sequence which uses $at, so
1995 we can't swap with an instruction which reads it. */
1996 || (mips_pic
== EMBEDDED_PIC
1997 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1998 /* If the previous previous instruction has a load
1999 delay, and sets a register that the branch reads, we
2001 || (! mips_opts
.mips16
2002 && mips_opts
.isa
< 4
2003 /* Itbl support may require additional care here. */
2004 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2005 || (! gpr_interlocks
2006 && (prev_prev_insn
.insn_mo
->pinfo
2007 & INSN_LOAD_MEMORY_DELAY
)))
2008 && insn_uses_reg (ip
,
2009 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2012 /* If one instruction sets a condition code and the
2013 other one uses a condition code, we can not swap. */
2014 || ((pinfo
& INSN_READ_COND_CODE
)
2015 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2016 || ((pinfo
& INSN_WRITE_COND_CODE
)
2017 && (prev_pinfo
& INSN_READ_COND_CODE
))
2018 /* If the previous instruction uses the PC, we can not
2020 || (mips_opts
.mips16
2021 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2022 /* If the previous instruction was extended, we can not
2024 || (mips_opts
.mips16
&& prev_insn_extended
)
2025 /* If the previous instruction had a fixup in mips16
2026 mode, we can not swap. This normally means that the
2027 previous instruction was a 4 byte branch anyhow. */
2028 || (mips_opts
.mips16
&& prev_insn_fixp
))
2030 /* We could do even better for unconditional branches to
2031 portions of this object file; we could pick up the
2032 instruction at the destination, put it in the delay
2033 slot, and bump the destination address. */
2035 /* Update the previous insn information. */
2036 prev_prev_insn
= *ip
;
2037 prev_insn
.insn_mo
= &dummy_opcode
;
2041 /* It looks like we can actually do the swap. */
2042 if (! mips_opts
.mips16
)
2047 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2048 memcpy (temp
, prev_f
, 4);
2049 memcpy (prev_f
, f
, 4);
2050 memcpy (f
, temp
, 4);
2053 prev_insn_fixp
->fx_frag
= frag_now
;
2054 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2058 fixp
->fx_frag
= prev_insn_frag
;
2059 fixp
->fx_where
= prev_insn_where
;
2067 assert (prev_insn_fixp
== NULL
);
2068 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2069 memcpy (temp
, prev_f
, 2);
2070 memcpy (prev_f
, f
, 2);
2071 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2073 assert (reloc_type
== BFD_RELOC_UNUSED
);
2074 memcpy (f
, temp
, 2);
2078 memcpy (f
, f
+ 2, 2);
2079 memcpy (f
+ 2, temp
, 2);
2083 fixp
->fx_frag
= prev_insn_frag
;
2084 fixp
->fx_where
= prev_insn_where
;
2088 /* Update the previous insn information; leave prev_insn
2090 prev_prev_insn
= *ip
;
2092 prev_insn_is_delay_slot
= 1;
2094 /* If that was an unconditional branch, forget the previous
2095 insn information. */
2096 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2098 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2099 prev_insn
.insn_mo
= &dummy_opcode
;
2102 prev_insn_fixp
= NULL
;
2103 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2104 prev_insn_extended
= 0;
2106 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2108 /* We don't yet optimize a branch likely. What we should do
2109 is look at the target, copy the instruction found there
2110 into the delay slot, and increment the branch to jump to
2111 the next instruction. */
2113 /* Update the previous insn information. */
2114 prev_prev_insn
= *ip
;
2115 prev_insn
.insn_mo
= &dummy_opcode
;
2116 prev_insn_fixp
= NULL
;
2117 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2118 prev_insn_extended
= 0;
2122 /* Update the previous insn information. */
2124 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2126 prev_prev_insn
= prev_insn
;
2129 /* Any time we see a branch, we always fill the delay slot
2130 immediately; since this insn is not a branch, we know it
2131 is not in a delay slot. */
2132 prev_insn_is_delay_slot
= 0;
2134 prev_insn_fixp
= fixp
;
2135 prev_insn_reloc_type
= reloc_type
;
2136 if (mips_opts
.mips16
)
2137 prev_insn_extended
= (ip
->use_extend
2138 || reloc_type
> BFD_RELOC_UNUSED
);
2141 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2142 prev_insn_unreordered
= 0;
2143 prev_insn_frag
= frag_now
;
2144 prev_insn_where
= f
- frag_now
->fr_literal
;
2145 prev_insn_valid
= 1;
2147 else if (place
== NULL
)
2149 /* We need to record a bit of information even when we are not
2150 reordering, in order to determine the base address for mips16
2151 PC relative relocs. */
2152 prev_prev_insn
= prev_insn
;
2154 prev_insn_reloc_type
= reloc_type
;
2155 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2156 prev_insn_unreordered
= 1;
2159 /* We just output an insn, so the next one doesn't have a label. */
2160 mips_clear_insn_labels ();
2163 /* This function forgets that there was any previous instruction or
2164 label. If PRESERVE is non-zero, it remembers enough information to
2165 know whether nops are needed before a noreorder section. */
2168 mips_no_prev_insn (preserve
)
2173 prev_insn
.insn_mo
= &dummy_opcode
;
2174 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2175 prev_nop_frag
= NULL
;
2176 prev_nop_frag_holds
= 0;
2177 prev_nop_frag_required
= 0;
2178 prev_nop_frag_since
= 0;
2180 prev_insn_valid
= 0;
2181 prev_insn_is_delay_slot
= 0;
2182 prev_insn_unreordered
= 0;
2183 prev_insn_extended
= 0;
2184 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2185 prev_prev_insn_unreordered
= 0;
2186 mips_clear_insn_labels ();
2189 /* This function must be called whenever we turn on noreorder or emit
2190 something other than instructions. It inserts any NOPS which might
2191 be needed by the previous instruction, and clears the information
2192 kept for the previous instructions. The INSNS parameter is true if
2193 instructions are to follow. */
2196 mips_emit_delays (insns
)
2199 if (! mips_opts
.noreorder
)
2204 if ((! mips_opts
.mips16
2205 && mips_opts
.isa
< 4
2206 && (! cop_interlocks
2207 && (prev_insn
.insn_mo
->pinfo
2208 & (INSN_LOAD_COPROC_DELAY
2209 | INSN_COPROC_MOVE_DELAY
2210 | INSN_WRITE_COND_CODE
))))
2211 || (! hilo_interlocks
2212 && (prev_insn
.insn_mo
->pinfo
2215 || (! mips_opts
.mips16
2217 && (prev_insn
.insn_mo
->pinfo
2218 & INSN_LOAD_MEMORY_DELAY
))
2219 || (! mips_opts
.mips16
2220 && mips_opts
.isa
< 2
2221 && (prev_insn
.insn_mo
->pinfo
2222 & INSN_COPROC_MEMORY_DELAY
)))
2224 /* Itbl support may require additional care here. */
2226 if ((! mips_opts
.mips16
2227 && mips_opts
.isa
< 4
2228 && (! cop_interlocks
2229 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2230 || (! hilo_interlocks
2231 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2232 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2235 if (prev_insn_unreordered
)
2238 else if ((! mips_opts
.mips16
2239 && mips_opts
.isa
< 4
2240 && (! cop_interlocks
2241 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2242 || (! hilo_interlocks
2243 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2244 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2246 /* Itbl support may require additional care here. */
2247 if (! prev_prev_insn_unreordered
)
2253 struct insn_label_list
*l
;
2257 /* Record the frag which holds the nop instructions, so
2258 that we can remove them if we don't need them. */
2259 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2260 prev_nop_frag
= frag_now
;
2261 prev_nop_frag_holds
= nops
;
2262 prev_nop_frag_required
= 0;
2263 prev_nop_frag_since
= 0;
2266 for (; nops
> 0; --nops
)
2271 /* Move on to a new frag, so that it is safe to simply
2272 decrease the size of prev_nop_frag. */
2273 frag_wane (frag_now
);
2277 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2279 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2280 l
->label
->sy_frag
= frag_now
;
2281 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2282 /* mips16 text labels are stored as odd. */
2283 if (mips_opts
.mips16
)
2284 ++l
->label
->sy_value
.X_add_number
;
2289 /* Mark instruction labels in mips16 mode. */
2290 if (mips_opts
.mips16
&& insns
)
2291 mips16_mark_labels ();
2293 mips_no_prev_insn (insns
);
2296 /* Build an instruction created by a macro expansion. This is passed
2297 a pointer to the count of instructions created so far, an
2298 expression, the name of the instruction to build, an operand format
2299 string, and corresponding arguments. */
2303 macro_build (char *place
,
2311 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2320 struct mips_cl_insn insn
;
2321 bfd_reloc_code_real_type r
;
2326 va_start (args
, fmt
);
2332 * If the macro is about to expand into a second instruction,
2333 * print a warning if needed. We need to pass ip as a parameter
2334 * to generate a better warning message here...
2336 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2337 as_warn ("Macro instruction expanded into multiple instructions");
2340 *counter
+= 1; /* bump instruction counter */
2342 if (mips_opts
.mips16
)
2344 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2349 r
= BFD_RELOC_UNUSED
;
2350 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2351 assert (insn
.insn_mo
);
2352 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2354 /* Search until we get a match for NAME. */
2357 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
2358 insn_isa
= insn
.insn_mo
->match
;
2359 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA1
)
2361 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA2
)
2363 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA3
)
2365 else if ((insn
.insn_mo
->membership
& INSN_ISA
) == INSN_ISA4
)
2370 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2371 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2372 && (insn_isa
<= mips_opts
.isa
2374 && (insn
.insn_mo
->membership
& INSN_4650
) != 0)
2376 && (insn
.insn_mo
->membership
& INSN_4010
) != 0)
2378 && (insn
.insn_mo
->membership
& INSN_4100
) != 0)
2379 /* start-sanitize-r5900 */
2381 && (insn
.insn_mo
->membership
& INSN_5900
) != 0)
2382 /* end-sanitize-r5900 */
2384 && (insn
.insn_mo
->membership
& INSN_3900
) != 0))
2385 /* start-sanitize-r5900 */
2386 && (! mips_5900
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0)
2387 /* end-sanitize-r5900 */
2388 && (! mips_4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2392 assert (insn
.insn_mo
->name
);
2393 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2396 insn
.insn_opcode
= insn
.insn_mo
->match
;
2412 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2418 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2423 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2428 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2435 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2439 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2443 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2450 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2456 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2457 assert (r
== BFD_RELOC_MIPS_GPREL
2458 || r
== BFD_RELOC_MIPS_LITERAL
2459 || r
== BFD_RELOC_LO16
2460 || r
== BFD_RELOC_MIPS_GOT16
2461 || r
== BFD_RELOC_MIPS_CALL16
2462 || r
== BFD_RELOC_MIPS_GOT_LO16
2463 || r
== BFD_RELOC_MIPS_CALL_LO16
2464 || (ep
->X_op
== O_subtract
2465 && now_seg
== text_section
2466 && r
== BFD_RELOC_PCREL_LO16
));
2470 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2472 && (ep
->X_op
== O_constant
2473 || (ep
->X_op
== O_symbol
2474 && (r
== BFD_RELOC_HI16_S
2475 || r
== BFD_RELOC_HI16
2476 || r
== BFD_RELOC_MIPS_GOT_HI16
2477 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2478 || (ep
->X_op
== O_subtract
2479 && now_seg
== text_section
2480 && r
== BFD_RELOC_PCREL_HI16_S
)));
2481 if (ep
->X_op
== O_constant
)
2483 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2485 r
= BFD_RELOC_UNUSED
;
2490 assert (ep
!= NULL
);
2492 * This allows macro() to pass an immediate expression for
2493 * creating short branches without creating a symbol.
2494 * Note that the expression still might come from the assembly
2495 * input, in which case the value is not checked for range nor
2496 * is a relocation entry generated (yuck).
2498 if (ep
->X_op
== O_constant
)
2500 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2504 r
= BFD_RELOC_16_PCREL_S2
;
2508 assert (ep
!= NULL
);
2509 r
= BFD_RELOC_MIPS_JMP
;
2518 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2520 append_insn (place
, &insn
, ep
, r
, false);
2524 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2532 struct mips_cl_insn insn
;
2533 bfd_reloc_code_real_type r
;
2535 r
= BFD_RELOC_UNUSED
;
2536 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2537 assert (insn
.insn_mo
);
2538 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2540 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2541 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2544 assert (insn
.insn_mo
->name
);
2545 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2548 insn
.insn_opcode
= insn
.insn_mo
->match
;
2549 insn
.use_extend
= false;
2568 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2573 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2577 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2581 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2591 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2598 regno
= va_arg (args
, int);
2599 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2600 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2621 assert (ep
!= NULL
);
2623 if (ep
->X_op
!= O_constant
)
2624 r
= BFD_RELOC_UNUSED
+ c
;
2627 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2628 false, false, &insn
.insn_opcode
,
2629 &insn
.use_extend
, &insn
.extend
);
2631 r
= BFD_RELOC_UNUSED
;
2637 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2644 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2646 append_insn (place
, &insn
, ep
, r
, false);
2650 * Generate a "lui" instruction.
2653 macro_build_lui (place
, counter
, ep
, regnum
)
2659 expressionS high_expr
;
2660 struct mips_cl_insn insn
;
2661 bfd_reloc_code_real_type r
;
2662 CONST
char *name
= "lui";
2663 CONST
char *fmt
= "t,u";
2665 assert (! mips_opts
.mips16
);
2671 high_expr
.X_op
= O_constant
;
2672 high_expr
.X_add_number
= ep
->X_add_number
;
2675 if (high_expr
.X_op
== O_constant
)
2677 /* we can compute the instruction now without a relocation entry */
2678 if (high_expr
.X_add_number
& 0x8000)
2679 high_expr
.X_add_number
+= 0x10000;
2680 high_expr
.X_add_number
=
2681 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2682 r
= BFD_RELOC_UNUSED
;
2686 assert (ep
->X_op
== O_symbol
);
2687 /* _gp_disp is a special case, used from s_cpload. */
2688 assert (mips_pic
== NO_PIC
2689 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2690 r
= BFD_RELOC_HI16_S
;
2694 * If the macro is about to expand into a second instruction,
2695 * print a warning if needed. We need to pass ip as a parameter
2696 * to generate a better warning message here...
2698 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2699 as_warn ("Macro instruction expanded into multiple instructions");
2702 *counter
+= 1; /* bump instruction counter */
2704 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2705 assert (insn
.insn_mo
);
2706 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2707 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2709 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2710 if (r
== BFD_RELOC_UNUSED
)
2712 insn
.insn_opcode
|= high_expr
.X_add_number
;
2713 append_insn (place
, &insn
, NULL
, r
, false);
2716 append_insn (place
, &insn
, &high_expr
, r
, false);
2720 * Generates code to set the $at register to true (one)
2721 * if reg is less than the immediate expression.
2724 set_at (counter
, reg
, unsignedp
)
2729 if (imm_expr
.X_op
== O_constant
2730 && imm_expr
.X_add_number
>= -0x8000
2731 && imm_expr
.X_add_number
< 0x8000)
2732 macro_build ((char *) NULL
, counter
, &imm_expr
,
2733 unsignedp
? "sltiu" : "slti",
2734 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2737 load_register (counter
, AT
, &imm_expr
, 0);
2738 macro_build ((char *) NULL
, counter
, NULL
,
2739 unsignedp
? "sltu" : "slt",
2740 "d,v,t", AT
, reg
, AT
);
2744 /* Warn if an expression is not a constant. */
2747 check_absolute_expr (ip
, ex
)
2748 struct mips_cl_insn
*ip
;
2751 if (ex
->X_op
== O_big
)
2752 as_bad ("unsupported large constant");
2753 else if (ex
->X_op
!= O_constant
)
2754 as_bad ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2757 /* Count the leading zeroes by performing a binary chop. This is a
2758 bulky bit of source, but performance is a LOT better for the
2759 majority of values than a simple loop to count the bits:
2760 for (lcnt = 0; (lcnt < 32); lcnt++)
2761 if ((v) & (1 << (31 - lcnt)))
2763 However it is not code size friendly, and the gain will drop a bit
2764 on certain cached systems.
2766 #define COUNT_TOP_ZEROES(v) \
2767 (((v) & ~0xffff) == 0 \
2768 ? ((v) & ~0xff) == 0 \
2769 ? ((v) & ~0xf) == 0 \
2770 ? ((v) & ~0x3) == 0 \
2771 ? ((v) & ~0x1) == 0 \
2776 : ((v) & ~0x7) == 0 \
2779 : ((v) & ~0x3f) == 0 \
2780 ? ((v) & ~0x1f) == 0 \
2783 : ((v) & ~0x7f) == 0 \
2786 : ((v) & ~0xfff) == 0 \
2787 ? ((v) & ~0x3ff) == 0 \
2788 ? ((v) & ~0x1ff) == 0 \
2791 : ((v) & ~0x7ff) == 0 \
2794 : ((v) & ~0x3fff) == 0 \
2795 ? ((v) & ~0x1fff) == 0 \
2798 : ((v) & ~0x7fff) == 0 \
2801 : ((v) & ~0xffffff) == 0 \
2802 ? ((v) & ~0xfffff) == 0 \
2803 ? ((v) & ~0x3ffff) == 0 \
2804 ? ((v) & ~0x1ffff) == 0 \
2807 : ((v) & ~0x7ffff) == 0 \
2810 : ((v) & ~0x3fffff) == 0 \
2811 ? ((v) & ~0x1fffff) == 0 \
2814 : ((v) & ~0x7fffff) == 0 \
2817 : ((v) & ~0xfffffff) == 0 \
2818 ? ((v) & ~0x3ffffff) == 0 \
2819 ? ((v) & ~0x1ffffff) == 0 \
2822 : ((v) & ~0x7ffffff) == 0 \
2825 : ((v) & ~0x3fffffff) == 0 \
2826 ? ((v) & ~0x1fffffff) == 0 \
2829 : ((v) & ~0x7fffffff) == 0 \
2834 * This routine generates the least number of instructions neccessary to load
2835 * an absolute expression value into a register.
2838 load_register (counter
, reg
, ep
, dbl
)
2845 expressionS hi32
, lo32
;
2847 if (ep
->X_op
!= O_big
)
2849 assert (ep
->X_op
== O_constant
);
2850 if (ep
->X_add_number
< 0x8000
2851 && (ep
->X_add_number
>= 0
2852 || (ep
->X_add_number
>= -0x8000
2855 || sizeof (ep
->X_add_number
) > 4))))
2857 /* We can handle 16 bit signed values with an addiu to
2858 $zero. No need to ever use daddiu here, since $zero and
2859 the result are always correct in 32 bit mode. */
2860 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2861 (int) BFD_RELOC_LO16
);
2864 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2866 /* We can handle 16 bit unsigned values with an ori to
2868 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2869 (int) BFD_RELOC_LO16
);
2872 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2873 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2874 == ~ (offsetT
) 0x7fffffff))
2877 || sizeof (ep
->X_add_number
) > 4
2878 || (ep
->X_add_number
& 0x80000000) == 0))
2879 || ((mips_opts
.isa
< 3 || ! dbl
)
2880 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2881 || (mips_opts
.isa
< 3
2883 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2884 == ~ (offsetT
) 0xffffffff)))
2886 /* 32 bit values require an lui. */
2887 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2888 (int) BFD_RELOC_HI16
);
2889 if ((ep
->X_add_number
& 0xffff) != 0)
2890 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2891 (int) BFD_RELOC_LO16
);
2896 /* The value is larger than 32 bits. */
2898 if (mips_opts
.isa
< 3)
2900 as_bad ("Number larger than 32 bits");
2901 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2902 (int) BFD_RELOC_LO16
);
2906 if (ep
->X_op
!= O_big
)
2909 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2910 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2911 hi32
.X_add_number
&= 0xffffffff;
2913 lo32
.X_add_number
&= 0xffffffff;
2917 assert (ep
->X_add_number
> 2);
2918 if (ep
->X_add_number
== 3)
2919 generic_bignum
[3] = 0;
2920 else if (ep
->X_add_number
> 4)
2921 as_bad ("Number larger than 64 bits");
2922 lo32
.X_op
= O_constant
;
2923 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2924 hi32
.X_op
= O_constant
;
2925 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2928 if (hi32
.X_add_number
== 0)
2933 unsigned long hi
, lo
;
2935 if (hi32
.X_add_number
== 0xffffffff)
2937 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2939 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2940 reg
, 0, (int) BFD_RELOC_LO16
);
2943 if (lo32
.X_add_number
& 0x80000000)
2945 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2946 (int) BFD_RELOC_HI16
);
2947 if (lo32
.X_add_number
& 0xffff)
2948 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2949 reg
, reg
, (int) BFD_RELOC_LO16
);
2954 /* Check for 16bit shifted constant. We know that hi32 is
2955 non-zero, so start the mask on the first bit of the hi32
2960 unsigned long himask
, lomask
;
2964 himask
= 0xffff >> (32 - shift
);
2965 lomask
= (0xffff << shift
) & 0xffffffff;
2969 himask
= 0xffff << (shift
- 32);
2972 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2973 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2977 tmp
.X_op
= O_constant
;
2979 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2980 | (lo32
.X_add_number
>> shift
));
2982 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2983 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2984 (int) BFD_RELOC_LO16
);
2985 macro_build ((char *) NULL
, counter
, NULL
,
2986 (shift
>= 32) ? "dsll32" : "dsll",
2988 (shift
>= 32) ? shift
- 32 : shift
);
2992 } while (shift
<= (64 - 16));
2994 /* Find the bit number of the lowest one bit, and store the
2995 shifted value in hi/lo. */
2996 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2997 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3001 while ((lo
& 1) == 0)
3006 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3012 while ((hi
& 1) == 0)
3021 /* Optimize if the shifted value is a (power of 2) - 1. */
3022 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3023 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3025 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3030 /* This instruction will set the register to be all
3032 tmp
.X_op
= O_constant
;
3033 tmp
.X_add_number
= (offsetT
) -1;
3034 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3035 reg
, 0, (int) BFD_RELOC_LO16
);
3039 macro_build ((char *) NULL
, counter
, NULL
,
3040 (bit
>= 32) ? "dsll32" : "dsll",
3042 (bit
>= 32) ? bit
- 32 : bit
);
3044 macro_build ((char *) NULL
, counter
, NULL
,
3045 (shift
>= 32) ? "dsrl32" : "dsrl",
3047 (shift
>= 32) ? shift
- 32 : shift
);
3052 /* Sign extend hi32 before calling load_register, because we can
3053 generally get better code when we load a sign extended value. */
3054 if ((hi32
.X_add_number
& 0x80000000) != 0)
3055 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3056 load_register (counter
, reg
, &hi32
, 0);
3059 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3063 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3072 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3074 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3075 (int) BFD_RELOC_HI16
);
3076 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3083 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3088 mid16
.X_add_number
>>= 16;
3089 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3090 freg
, (int) BFD_RELOC_LO16
);
3091 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3095 if ((lo32
.X_add_number
& 0xffff) != 0)
3096 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3097 (int) BFD_RELOC_LO16
);
3100 /* Load an address into a register. */
3103 load_address (counter
, reg
, ep
)
3110 if (ep
->X_op
!= O_constant
3111 && ep
->X_op
!= O_symbol
)
3113 as_bad ("expression too complex");
3114 ep
->X_op
= O_constant
;
3117 if (ep
->X_op
== O_constant
)
3119 load_register (counter
, reg
, ep
, 0);
3123 if (mips_pic
== NO_PIC
)
3125 /* If this is a reference to a GP relative symbol, we want
3126 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3128 lui $reg,<sym> (BFD_RELOC_HI16_S)
3129 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3130 If we have an addend, we always use the latter form. */
3131 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3132 || nopic_need_relax (ep
->X_add_symbol
, 1))
3137 macro_build ((char *) NULL
, counter
, ep
,
3138 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3139 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3140 p
= frag_var (rs_machine_dependent
, 8, 0,
3141 RELAX_ENCODE (4, 8, 0, 4, 0,
3142 mips_opts
.warn_about_macros
),
3143 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3145 macro_build_lui (p
, counter
, ep
, reg
);
3148 macro_build (p
, counter
, ep
,
3149 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3150 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3152 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3156 /* If this is a reference to an external symbol, we want
3157 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3159 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3161 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3162 If there is a constant, it must be added in after. */
3163 ex
.X_add_number
= ep
->X_add_number
;
3164 ep
->X_add_number
= 0;
3166 macro_build ((char *) NULL
, counter
, ep
,
3167 mips_opts
.isa
< 3 ? "lw" : "ld",
3168 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3169 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3170 p
= frag_var (rs_machine_dependent
, 4, 0,
3171 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3172 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3173 macro_build (p
, counter
, ep
,
3174 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3175 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3176 if (ex
.X_add_number
!= 0)
3178 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3179 as_bad ("PIC code offset overflow (max 16 signed bits)");
3180 ex
.X_op
= O_constant
;
3181 macro_build ((char *) NULL
, counter
, &ex
,
3182 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3183 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3186 else if (mips_pic
== SVR4_PIC
)
3191 /* This is the large GOT case. If this is a reference to an
3192 external symbol, we want
3193 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3195 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3196 Otherwise, for a reference to a local symbol, we want
3197 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3199 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3200 If there is a constant, it must be added in after. */
3201 ex
.X_add_number
= ep
->X_add_number
;
3202 ep
->X_add_number
= 0;
3203 if (reg_needs_delay (GP
))
3208 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3209 (int) BFD_RELOC_MIPS_GOT_HI16
);
3210 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3211 mips_opts
.isa
< 3 ? "addu" : "daddu",
3212 "d,v,t", reg
, reg
, GP
);
3213 macro_build ((char *) NULL
, counter
, ep
,
3214 mips_opts
.isa
< 3 ? "lw" : "ld",
3215 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3216 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3217 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3218 mips_opts
.warn_about_macros
),
3219 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3222 /* We need a nop before loading from $gp. This special
3223 check is required because the lui which starts the main
3224 instruction stream does not refer to $gp, and so will not
3225 insert the nop which may be required. */
3226 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3229 macro_build (p
, counter
, ep
,
3230 mips_opts
.isa
< 3 ? "lw" : "ld",
3231 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3233 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3235 macro_build (p
, counter
, ep
,
3236 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3237 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3238 if (ex
.X_add_number
!= 0)
3240 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3241 as_bad ("PIC code offset overflow (max 16 signed bits)");
3242 ex
.X_op
= O_constant
;
3243 macro_build ((char *) NULL
, counter
, &ex
,
3244 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3245 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3248 else if (mips_pic
== EMBEDDED_PIC
)
3251 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3253 macro_build ((char *) NULL
, counter
, ep
,
3254 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3255 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3263 * This routine implements the seemingly endless macro or synthesized
3264 * instructions and addressing modes in the mips assembly language. Many
3265 * of these macros are simple and are similar to each other. These could
3266 * probably be handled by some kind of table or grammer aproach instead of
3267 * this verbose method. Others are not simple macros but are more like
3268 * optimizing code generation.
3269 * One interesting optimization is when several store macros appear
3270 * consecutivly that would load AT with the upper half of the same address.
3271 * The ensuing load upper instructions are ommited. This implies some kind
3272 * of global optimization. We currently only optimize within a single macro.
3273 * For many of the load and store macros if the address is specified as a
3274 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3275 * first load register 'at' with zero and use it as the base register. The
3276 * mips assembler simply uses register $zero. Just one tiny optimization
3281 struct mips_cl_insn
*ip
;
3283 register int treg
, sreg
, dreg
, breg
;
3298 bfd_reloc_code_real_type r
;
3300 int hold_mips_optimize
;
3302 assert (! mips_opts
.mips16
);
3304 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3305 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3306 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3307 mask
= ip
->insn_mo
->mask
;
3309 expr1
.X_op
= O_constant
;
3310 expr1
.X_op_symbol
= NULL
;
3311 expr1
.X_add_symbol
= NULL
;
3312 expr1
.X_add_number
= 1;
3324 mips_emit_delays (true);
3325 ++mips_opts
.noreorder
;
3326 mips_any_noreorder
= 1;
3328 expr1
.X_add_number
= 8;
3329 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3331 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3333 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3334 macro_build ((char *) NULL
, &icnt
, NULL
,
3335 dbl
? "dsub" : "sub",
3336 "d,v,t", dreg
, 0, sreg
);
3338 --mips_opts
.noreorder
;
3359 if (imm_expr
.X_op
== O_constant
3360 && imm_expr
.X_add_number
>= -0x8000
3361 && imm_expr
.X_add_number
< 0x8000)
3363 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3364 (int) BFD_RELOC_LO16
);
3367 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3368 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3387 if (imm_expr
.X_op
== O_constant
3388 && imm_expr
.X_add_number
>= 0
3389 && imm_expr
.X_add_number
< 0x10000)
3391 if (mask
!= M_NOR_I
)
3392 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3393 sreg
, (int) BFD_RELOC_LO16
);
3396 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3397 treg
, sreg
, (int) BFD_RELOC_LO16
);
3398 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3404 load_register (&icnt
, AT
, &imm_expr
, 0);
3405 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3422 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3424 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3428 load_register (&icnt
, AT
, &imm_expr
, 0);
3429 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3437 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3438 likely
? "bgezl" : "bgez",
3444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3445 likely
? "blezl" : "blez",
3449 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3450 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3451 likely
? "beql" : "beq",
3458 /* check for > max integer */
3459 maxnum
= 0x7fffffff;
3460 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3467 if (imm_expr
.X_op
== O_constant
3468 && imm_expr
.X_add_number
>= maxnum
3469 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3472 /* result is always false */
3475 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3476 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3480 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3486 if (imm_expr
.X_op
!= O_constant
)
3487 as_bad ("Unsupported large constant");
3488 imm_expr
.X_add_number
++;
3492 if (mask
== M_BGEL_I
)
3494 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3496 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3497 likely
? "bgezl" : "bgez",
3501 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3503 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3504 likely
? "bgtzl" : "bgtz",
3508 maxnum
= 0x7fffffff;
3509 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3516 maxnum
= - maxnum
- 1;
3517 if (imm_expr
.X_op
== O_constant
3518 && imm_expr
.X_add_number
<= maxnum
3519 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3522 /* result is always true */
3523 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3524 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3527 set_at (&icnt
, sreg
, 0);
3528 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3529 likely
? "beql" : "beq",
3540 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3541 likely
? "beql" : "beq",
3545 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3547 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3548 likely
? "beql" : "beq",
3556 || (mips_opts
.isa
< 3
3557 && imm_expr
.X_op
== O_constant
3558 && imm_expr
.X_add_number
== 0xffffffff))
3560 if (imm_expr
.X_op
!= O_constant
)
3561 as_bad ("Unsupported large constant");
3562 imm_expr
.X_add_number
++;
3566 if (mask
== M_BGEUL_I
)
3568 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3570 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3572 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3573 likely
? "bnel" : "bne",
3577 set_at (&icnt
, sreg
, 1);
3578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3579 likely
? "beql" : "beq",
3588 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3589 likely
? "bgtzl" : "bgtz",
3595 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3596 likely
? "bltzl" : "bltz",
3600 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3601 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3602 likely
? "bnel" : "bne",
3611 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3612 likely
? "bnel" : "bne",
3618 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3620 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3621 likely
? "bnel" : "bne",
3630 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3631 likely
? "blezl" : "blez",
3637 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3638 likely
? "bgezl" : "bgez",
3642 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3643 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3644 likely
? "beql" : "beq",
3651 maxnum
= 0x7fffffff;
3652 if (mips_opts
.isa
>= 3 && sizeof (maxnum
) > 4)
3659 if (imm_expr
.X_op
== O_constant
3660 && imm_expr
.X_add_number
>= maxnum
3661 && (mips_opts
.isa
< 3 || sizeof (maxnum
) > 4))
3663 if (imm_expr
.X_op
!= O_constant
)
3664 as_bad ("Unsupported large constant");
3665 imm_expr
.X_add_number
++;
3669 if (mask
== M_BLTL_I
)
3671 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3673 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3674 likely
? "bltzl" : "bltz",
3678 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3680 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3681 likely
? "blezl" : "blez",
3685 set_at (&icnt
, sreg
, 0);
3686 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3687 likely
? "bnel" : "bne",
3696 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3697 likely
? "beql" : "beq",
3703 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3705 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3706 likely
? "beql" : "beq",
3714 || (mips_opts
.isa
< 3
3715 && imm_expr
.X_op
== O_constant
3716 && imm_expr
.X_add_number
== 0xffffffff))
3718 if (imm_expr
.X_op
!= O_constant
)
3719 as_bad ("Unsupported large constant");
3720 imm_expr
.X_add_number
++;
3724 if (mask
== M_BLTUL_I
)
3726 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3728 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3730 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3731 likely
? "beql" : "beq",
3735 set_at (&icnt
, sreg
, 1);
3736 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3737 likely
? "bnel" : "bne",
3746 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3747 likely
? "bltzl" : "bltz",
3753 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3754 likely
? "bgtzl" : "bgtz",
3758 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3759 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3760 likely
? "bnel" : "bne",
3771 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3772 likely
? "bnel" : "bne",
3776 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3778 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3779 likely
? "bnel" : "bne",
3795 as_warn ("Divide by zero.");
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3799 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3803 mips_emit_delays (true);
3804 ++mips_opts
.noreorder
;
3805 mips_any_noreorder
= 1;
3806 macro_build ((char *) NULL
, &icnt
, NULL
,
3807 dbl
? "ddiv" : "div",
3808 "z,s,t", sreg
, treg
);
3810 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3813 expr1
.X_add_number
= 8;
3814 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3815 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3816 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3818 expr1
.X_add_number
= -1;
3819 macro_build ((char *) NULL
, &icnt
, &expr1
,
3820 dbl
? "daddiu" : "addiu",
3821 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3822 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3823 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3826 expr1
.X_add_number
= 1;
3827 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3828 (int) BFD_RELOC_LO16
);
3829 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3834 expr1
.X_add_number
= 0x80000000;
3835 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3836 (int) BFD_RELOC_HI16
);
3839 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3842 expr1
.X_add_number
= 8;
3843 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3844 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3845 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3847 --mips_opts
.noreorder
;
3848 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3887 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3889 as_warn ("Divide by zero.");
3891 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3893 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3896 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3898 if (strcmp (s2
, "mflo") == 0)
3899 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3902 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3905 if (imm_expr
.X_op
== O_constant
3906 && imm_expr
.X_add_number
== -1
3907 && s
[strlen (s
) - 1] != 'u')
3909 if (strcmp (s2
, "mflo") == 0)
3912 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3915 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3919 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3923 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3924 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3925 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3944 mips_emit_delays (true);
3945 ++mips_opts
.noreorder
;
3946 mips_any_noreorder
= 1;
3947 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3949 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3952 expr1
.X_add_number
= 8;
3953 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3954 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3955 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3957 --mips_opts
.noreorder
;
3958 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3964 /* Load the address of a symbol into a register. If breg is not
3965 zero, we then add a base register to it. */
3967 /* When generating embedded PIC code, we permit expressions of
3970 where bar is an address in the .text section. These are used
3971 when getting the addresses of functions. We don't permit
3972 X_add_number to be non-zero, because if the symbol is
3973 external the relaxing code needs to know that any addend is
3974 purely the offset to X_op_symbol. */
3975 if (mips_pic
== EMBEDDED_PIC
3976 && offset_expr
.X_op
== O_subtract
3977 && now_seg
== text_section
3978 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3979 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3980 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3981 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3982 ->sy_value
.X_add_symbol
)
3985 && offset_expr
.X_add_number
== 0)
3987 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3988 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3989 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3990 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
3991 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3995 if (offset_expr
.X_op
!= O_symbol
3996 && offset_expr
.X_op
!= O_constant
)
3998 as_bad ("expression too complex");
3999 offset_expr
.X_op
= O_constant
;
4013 if (offset_expr
.X_op
== O_constant
)
4014 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4015 else if (mips_pic
== NO_PIC
)
4017 /* If this is a reference to an GP relative symbol, we want
4018 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4020 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4021 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4022 If we have a constant, we need two instructions anyhow,
4023 so we may as well always use the latter form. */
4024 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4025 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4031 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4032 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4033 p
= frag_var (rs_machine_dependent
, 8, 0,
4034 RELAX_ENCODE (4, 8, 0, 4, 0,
4035 mips_opts
.warn_about_macros
),
4036 offset_expr
.X_add_symbol
, (offsetT
) 0,
4039 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4042 macro_build (p
, &icnt
, &offset_expr
,
4043 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4044 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4046 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4048 /* If this is a reference to an external symbol, and there
4049 is no constant, we want
4050 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4051 For a local symbol, we want
4052 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4054 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4056 If we have a small constant, and this is a reference to
4057 an external symbol, we want
4058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4060 addiu $tempreg,$tempreg,<constant>
4061 For a local symbol, we want the same instruction
4062 sequence, but we output a BFD_RELOC_LO16 reloc on the
4065 If we have a large constant, and this is a reference to
4066 an external symbol, we want
4067 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4068 lui $at,<hiconstant>
4069 addiu $at,$at,<loconstant>
4070 addu $tempreg,$tempreg,$at
4071 For a local symbol, we want the same instruction
4072 sequence, but we output a BFD_RELOC_LO16 reloc on the
4073 addiu instruction. */
4074 expr1
.X_add_number
= offset_expr
.X_add_number
;
4075 offset_expr
.X_add_number
= 0;
4077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4079 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4080 if (expr1
.X_add_number
== 0)
4088 /* We're going to put in an addu instruction using
4089 tempreg, so we may as well insert the nop right
4091 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4095 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4096 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4098 ? mips_opts
.warn_about_macros
4100 offset_expr
.X_add_symbol
, (offsetT
) 0,
4104 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4107 macro_build (p
, &icnt
, &expr1
,
4108 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4109 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4110 /* FIXME: If breg == 0, and the next instruction uses
4111 $tempreg, then if this variant case is used an extra
4112 nop will be generated. */
4114 else if (expr1
.X_add_number
>= -0x8000
4115 && expr1
.X_add_number
< 0x8000)
4117 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4119 macro_build ((char *) NULL
, &icnt
, &expr1
,
4120 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4121 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4122 (void) frag_var (rs_machine_dependent
, 0, 0,
4123 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4124 offset_expr
.X_add_symbol
, (offsetT
) 0,
4131 /* If we are going to add in a base register, and the
4132 target register and the base register are the same,
4133 then we are using AT as a temporary register. Since
4134 we want to load the constant into AT, we add our
4135 current AT (from the global offset table) and the
4136 register into the register now, and pretend we were
4137 not using a base register. */
4142 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4144 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4145 mips_opts
.isa
< 3 ? "addu" : "daddu",
4146 "d,v,t", treg
, AT
, breg
);
4152 /* Set mips_optimize around the lui instruction to avoid
4153 inserting an unnecessary nop after the lw. */
4154 hold_mips_optimize
= mips_optimize
;
4156 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4157 mips_optimize
= hold_mips_optimize
;
4159 macro_build ((char *) NULL
, &icnt
, &expr1
,
4160 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4161 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4162 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4163 mips_opts
.isa
< 3 ? "addu" : "daddu",
4164 "d,v,t", tempreg
, tempreg
, AT
);
4165 (void) frag_var (rs_machine_dependent
, 0, 0,
4166 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4167 offset_expr
.X_add_symbol
, (offsetT
) 0,
4172 else if (mips_pic
== SVR4_PIC
)
4176 /* This is the large GOT case. If this is a reference to an
4177 external symbol, and there is no constant, we want
4178 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4179 addu $tempreg,$tempreg,$gp
4180 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4181 For a local symbol, we want
4182 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4184 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4186 If we have a small constant, and this is a reference to
4187 an external symbol, we want
4188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4189 addu $tempreg,$tempreg,$gp
4190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4192 addiu $tempreg,$tempreg,<constant>
4193 For a local symbol, we want
4194 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4196 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4198 If we have a large constant, and this is a reference to
4199 an external symbol, we want
4200 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4201 addu $tempreg,$tempreg,$gp
4202 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4203 lui $at,<hiconstant>
4204 addiu $at,$at,<loconstant>
4205 addu $tempreg,$tempreg,$at
4206 For a local symbol, we want
4207 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4208 lui $at,<hiconstant>
4209 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4210 addu $tempreg,$tempreg,$at
4212 expr1
.X_add_number
= offset_expr
.X_add_number
;
4213 offset_expr
.X_add_number
= 0;
4215 if (reg_needs_delay (GP
))
4219 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4220 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4221 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4222 mips_opts
.isa
< 3 ? "addu" : "daddu",
4223 "d,v,t", tempreg
, tempreg
, GP
);
4224 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4226 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4228 if (expr1
.X_add_number
== 0)
4236 /* We're going to put in an addu instruction using
4237 tempreg, so we may as well insert the nop right
4239 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4244 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4245 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4248 ? mips_opts
.warn_about_macros
4250 offset_expr
.X_add_symbol
, (offsetT
) 0,
4253 else if (expr1
.X_add_number
>= -0x8000
4254 && expr1
.X_add_number
< 0x8000)
4256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4258 macro_build ((char *) NULL
, &icnt
, &expr1
,
4259 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4260 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4262 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4263 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4265 ? mips_opts
.warn_about_macros
4267 offset_expr
.X_add_symbol
, (offsetT
) 0,
4274 /* If we are going to add in a base register, and the
4275 target register and the base register are the same,
4276 then we are using AT as a temporary register. Since
4277 we want to load the constant into AT, we add our
4278 current AT (from the global offset table) and the
4279 register into the register now, and pretend we were
4280 not using a base register. */
4288 assert (tempreg
== AT
);
4289 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4291 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4292 mips_opts
.isa
< 3 ? "addu" : "daddu",
4293 "d,v,t", treg
, AT
, breg
);
4298 /* Set mips_optimize around the lui instruction to avoid
4299 inserting an unnecessary nop after the lw. */
4300 hold_mips_optimize
= mips_optimize
;
4302 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4303 mips_optimize
= hold_mips_optimize
;
4305 macro_build ((char *) NULL
, &icnt
, &expr1
,
4306 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4307 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4308 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4309 mips_opts
.isa
< 3 ? "addu" : "daddu",
4310 "d,v,t", dreg
, dreg
, AT
);
4312 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4313 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4316 ? mips_opts
.warn_about_macros
4318 offset_expr
.X_add_symbol
, (offsetT
) 0,
4326 /* This is needed because this instruction uses $gp, but
4327 the first instruction on the main stream does not. */
4328 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4331 macro_build (p
, &icnt
, &offset_expr
,
4333 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4335 if (expr1
.X_add_number
>= -0x8000
4336 && expr1
.X_add_number
< 0x8000)
4338 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4340 macro_build (p
, &icnt
, &expr1
,
4341 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4342 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4343 /* FIXME: If add_number is 0, and there was no base
4344 register, the external symbol case ended with a load,
4345 so if the symbol turns out to not be external, and
4346 the next instruction uses tempreg, an unnecessary nop
4347 will be inserted. */
4353 /* We must add in the base register now, as in the
4354 external symbol case. */
4355 assert (tempreg
== AT
);
4356 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4358 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4359 mips_opts
.isa
< 3 ? "addu" : "daddu",
4360 "d,v,t", treg
, AT
, breg
);
4363 /* We set breg to 0 because we have arranged to add
4364 it in in both cases. */
4368 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4370 macro_build (p
, &icnt
, &expr1
,
4371 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4372 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4374 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4375 mips_opts
.isa
< 3 ? "addu" : "daddu",
4376 "d,v,t", tempreg
, tempreg
, AT
);
4380 else if (mips_pic
== EMBEDDED_PIC
)
4383 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4385 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4386 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4387 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4393 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4394 mips_opts
.isa
< 3 ? "addu" : "daddu",
4395 "d,v,t", treg
, tempreg
, breg
);
4403 /* The j instruction may not be used in PIC code, since it
4404 requires an absolute address. We convert it to a b
4406 if (mips_pic
== NO_PIC
)
4407 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4409 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4412 /* The jal instructions must be handled as macros because when
4413 generating PIC code they expand to multi-instruction
4414 sequences. Normally they are simple instructions. */
4419 if (mips_pic
== NO_PIC
4420 || mips_pic
== EMBEDDED_PIC
)
4421 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4423 else if (mips_pic
== SVR4_PIC
)
4425 if (sreg
!= PIC_CALL_REG
)
4426 as_warn ("MIPS PIC call to register other than $25");
4428 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4430 if (mips_cprestore_offset
< 0)
4431 as_warn ("No .cprestore pseudo-op used in PIC code");
4434 expr1
.X_add_number
= mips_cprestore_offset
;
4435 macro_build ((char *) NULL
, &icnt
, &expr1
,
4436 mips_opts
.isa
< 3 ? "lw" : "ld",
4437 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4446 if (mips_pic
== NO_PIC
)
4447 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4448 else if (mips_pic
== SVR4_PIC
)
4450 /* If this is a reference to an external symbol, and we are
4451 using a small GOT, we want
4452 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4456 lw $gp,cprestore($sp)
4457 The cprestore value is set using the .cprestore
4458 pseudo-op. If we are using a big GOT, we want
4459 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4461 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4465 lw $gp,cprestore($sp)
4466 If the symbol is not external, we want
4467 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4469 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4472 lw $gp,cprestore($sp) */
4476 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4477 mips_opts
.isa
< 3 ? "lw" : "ld",
4478 "t,o(b)", PIC_CALL_REG
,
4479 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4480 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4482 p
= frag_var (rs_machine_dependent
, 4, 0,
4483 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4484 offset_expr
.X_add_symbol
, (offsetT
) 0,
4491 if (reg_needs_delay (GP
))
4495 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4496 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4497 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4498 mips_opts
.isa
< 3 ? "addu" : "daddu",
4499 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4500 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4501 mips_opts
.isa
< 3 ? "lw" : "ld",
4502 "t,o(b)", PIC_CALL_REG
,
4503 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4504 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4506 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4507 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4509 offset_expr
.X_add_symbol
, (offsetT
) 0,
4513 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4516 macro_build (p
, &icnt
, &offset_expr
,
4517 mips_opts
.isa
< 3 ? "lw" : "ld",
4518 "t,o(b)", PIC_CALL_REG
,
4519 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4521 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4524 macro_build (p
, &icnt
, &offset_expr
,
4525 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4526 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4527 (int) BFD_RELOC_LO16
);
4528 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4529 "jalr", "s", PIC_CALL_REG
);
4530 if (mips_cprestore_offset
< 0)
4531 as_warn ("No .cprestore pseudo-op used in PIC code");
4534 if (mips_opts
.noreorder
)
4535 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4537 expr1
.X_add_number
= mips_cprestore_offset
;
4538 macro_build ((char *) NULL
, &icnt
, &expr1
,
4539 mips_opts
.isa
< 3 ? "lw" : "ld",
4540 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4544 else if (mips_pic
== EMBEDDED_PIC
)
4546 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4547 /* The linker may expand the call to a longer sequence which
4548 uses $at, so we must break rather than return. */
4573 /* Itbl support may require additional care here. */
4578 /* Itbl support may require additional care here. */
4583 /* Itbl support may require additional care here. */
4588 /* Itbl support may require additional care here. */
4601 /* Itbl support may require additional care here. */
4606 /* Itbl support may require additional care here. */
4611 /* Itbl support may require additional care here. */
4631 if (breg
== treg
|| coproc
|| lr
)
4653 /* Itbl support may require additional care here. */
4658 /* Itbl support may require additional care here. */
4663 /* Itbl support may require additional care here. */
4668 /* Itbl support may require additional care here. */
4686 /* Itbl support may require additional care here. */
4690 /* Itbl support may require additional care here. */
4695 /* Itbl support may require additional care here. */
4707 /* Itbl support may require additional care here. */
4708 if (mask
== M_LWC1_AB
4709 || mask
== M_SWC1_AB
4710 || mask
== M_LDC1_AB
4711 || mask
== M_SDC1_AB
4720 if (offset_expr
.X_op
!= O_constant
4721 && offset_expr
.X_op
!= O_symbol
)
4723 as_bad ("expression too complex");
4724 offset_expr
.X_op
= O_constant
;
4727 /* A constant expression in PIC code can be handled just as it
4728 is in non PIC code. */
4729 if (mips_pic
== NO_PIC
4730 || offset_expr
.X_op
== O_constant
)
4732 /* If this is a reference to a GP relative symbol, and there
4733 is no base register, we want
4734 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4735 Otherwise, if there is no base register, we want
4736 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4737 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4738 If we have a constant, we need two instructions anyhow,
4739 so we always use the latter form.
4741 If we have a base register, and this is a reference to a
4742 GP relative symbol, we want
4743 addu $tempreg,$breg,$gp
4744 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4746 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4747 addu $tempreg,$tempreg,$breg
4748 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4749 With a constant we always use the latter case. */
4752 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4753 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4758 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4759 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4760 p
= frag_var (rs_machine_dependent
, 8, 0,
4761 RELAX_ENCODE (4, 8, 0, 4, 0,
4762 (mips_opts
.warn_about_macros
4764 && mips_opts
.noat
))),
4765 offset_expr
.X_add_symbol
, (offsetT
) 0,
4769 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4772 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4773 (int) BFD_RELOC_LO16
, tempreg
);
4777 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4778 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4783 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4784 mips_opts
.isa
< 3 ? "addu" : "daddu",
4785 "d,v,t", tempreg
, breg
, GP
);
4786 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4787 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4788 p
= frag_var (rs_machine_dependent
, 12, 0,
4789 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4790 offset_expr
.X_add_symbol
, (offsetT
) 0,
4793 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4796 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4797 mips_opts
.isa
< 3 ? "addu" : "daddu",
4798 "d,v,t", tempreg
, tempreg
, breg
);
4801 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4802 (int) BFD_RELOC_LO16
, tempreg
);
4805 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4807 /* If this is a reference to an external symbol, we want
4808 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4810 <op> $treg,0($tempreg)
4812 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4814 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4815 <op> $treg,0($tempreg)
4816 If there is a base register, we add it to $tempreg before
4817 the <op>. If there is a constant, we stick it in the
4818 <op> instruction. We don't handle constants larger than
4819 16 bits, because we have no way to load the upper 16 bits
4820 (actually, we could handle them for the subset of cases
4821 in which we are not using $at). */
4822 assert (offset_expr
.X_op
== O_symbol
);
4823 expr1
.X_add_number
= offset_expr
.X_add_number
;
4824 offset_expr
.X_add_number
= 0;
4825 if (expr1
.X_add_number
< -0x8000
4826 || expr1
.X_add_number
>= 0x8000)
4827 as_bad ("PIC code offset overflow (max 16 signed bits)");
4829 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4830 mips_opts
.isa
< 3 ? "lw" : "ld",
4831 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4832 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4833 p
= frag_var (rs_machine_dependent
, 4, 0,
4834 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4835 offset_expr
.X_add_symbol
, (offsetT
) 0,
4837 macro_build (p
, &icnt
, &offset_expr
,
4838 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4839 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4841 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4842 mips_opts
.isa
< 3 ? "addu" : "daddu",
4843 "d,v,t", tempreg
, tempreg
, breg
);
4844 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4845 (int) BFD_RELOC_LO16
, tempreg
);
4847 else if (mips_pic
== SVR4_PIC
)
4851 /* If this is a reference to an external symbol, we want
4852 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4853 addu $tempreg,$tempreg,$gp
4854 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4855 <op> $treg,0($tempreg)
4857 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4859 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4860 <op> $treg,0($tempreg)
4861 If there is a base register, we add it to $tempreg before
4862 the <op>. If there is a constant, we stick it in the
4863 <op> instruction. We don't handle constants larger than
4864 16 bits, because we have no way to load the upper 16 bits
4865 (actually, we could handle them for the subset of cases
4866 in which we are not using $at). */
4867 assert (offset_expr
.X_op
== O_symbol
);
4868 expr1
.X_add_number
= offset_expr
.X_add_number
;
4869 offset_expr
.X_add_number
= 0;
4870 if (expr1
.X_add_number
< -0x8000
4871 || expr1
.X_add_number
>= 0x8000)
4872 as_bad ("PIC code offset overflow (max 16 signed bits)");
4873 if (reg_needs_delay (GP
))
4878 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4879 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4880 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4881 mips_opts
.isa
< 3 ? "addu" : "daddu",
4882 "d,v,t", tempreg
, tempreg
, GP
);
4883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4884 mips_opts
.isa
< 3 ? "lw" : "ld",
4885 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4887 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4888 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4889 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
4892 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4895 macro_build (p
, &icnt
, &offset_expr
,
4896 mips_opts
.isa
< 3 ? "lw" : "ld",
4897 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4899 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4901 macro_build (p
, &icnt
, &offset_expr
,
4902 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
4903 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4906 mips_opts
.isa
< 3 ? "addu" : "daddu",
4907 "d,v,t", tempreg
, tempreg
, breg
);
4908 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4909 (int) BFD_RELOC_LO16
, tempreg
);
4911 else if (mips_pic
== EMBEDDED_PIC
)
4913 /* If there is no base register, we want
4914 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4915 If there is a base register, we want
4916 addu $tempreg,$breg,$gp
4917 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4919 assert (offset_expr
.X_op
== O_symbol
);
4922 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4923 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4928 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4929 mips_opts
.isa
< 3 ? "addu" : "daddu",
4930 "d,v,t", tempreg
, breg
, GP
);
4931 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4932 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4945 load_register (&icnt
, treg
, &imm_expr
, 0);
4949 load_register (&icnt
, treg
, &imm_expr
, 1);
4953 if (imm_expr
.X_op
== O_constant
)
4955 load_register (&icnt
, AT
, &imm_expr
, 0);
4956 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4957 "mtc1", "t,G", AT
, treg
);
4962 assert (offset_expr
.X_op
== O_symbol
4963 && strcmp (segment_name (S_GET_SEGMENT
4964 (offset_expr
.X_add_symbol
)),
4966 && offset_expr
.X_add_number
== 0);
4967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4968 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4973 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
4974 the entire value, and in mips1 mode it is the high order 32
4975 bits of the value and the low order 32 bits are either zero
4976 or in offset_expr. */
4977 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
4979 if (mips_opts
.isa
>= 3)
4980 load_register (&icnt
, treg
, &imm_expr
, 1);
4985 if (target_big_endian
)
4997 load_register (&icnt
, hreg
, &imm_expr
, 0);
5000 if (offset_expr
.X_op
== O_absent
)
5001 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5005 assert (offset_expr
.X_op
== O_constant
);
5006 load_register (&icnt
, lreg
, &offset_expr
, 0);
5013 /* We know that sym is in the .rdata section. First we get the
5014 upper 16 bits of the address. */
5015 if (mips_pic
== NO_PIC
)
5017 /* FIXME: This won't work for a 64 bit address. */
5018 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5020 else if (mips_pic
== SVR4_PIC
)
5022 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5023 mips_opts
.isa
< 3 ? "lw" : "ld",
5024 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5026 else if (mips_pic
== EMBEDDED_PIC
)
5028 /* For embedded PIC we pick up the entire address off $gp in
5029 a single instruction. */
5030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5031 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5032 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5033 offset_expr
.X_op
= O_constant
;
5034 offset_expr
.X_add_number
= 0;
5039 /* Now we load the register(s). */
5040 if (mips_opts
.isa
>= 3)
5041 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5042 treg
, (int) BFD_RELOC_LO16
, AT
);
5045 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5046 treg
, (int) BFD_RELOC_LO16
, AT
);
5049 /* FIXME: How in the world do we deal with the possible
5051 offset_expr
.X_add_number
+= 4;
5052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5053 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5057 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5058 does not become a variant frag. */
5059 frag_wane (frag_now
);
5065 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5066 the entire value, and in mips1 mode it is the high order 32
5067 bits of the value and the low order 32 bits are either zero
5068 or in offset_expr. */
5069 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5071 load_register (&icnt
, AT
, &imm_expr
, mips_opts
.isa
>= 3);
5072 if (mips_opts
.isa
>= 3)
5073 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5074 "dmtc1", "t,S", AT
, treg
);
5077 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5078 "mtc1", "t,G", AT
, treg
+ 1);
5079 if (offset_expr
.X_op
== O_absent
)
5080 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5081 "mtc1", "t,G", 0, treg
);
5084 assert (offset_expr
.X_op
== O_constant
);
5085 load_register (&icnt
, AT
, &offset_expr
, 0);
5086 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5087 "mtc1", "t,G", AT
, treg
);
5093 assert (offset_expr
.X_op
== O_symbol
5094 && offset_expr
.X_add_number
== 0);
5095 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5096 if (strcmp (s
, ".lit8") == 0)
5098 if (mips_opts
.isa
>= 2)
5100 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5101 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5105 r
= BFD_RELOC_MIPS_LITERAL
;
5110 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5111 if (mips_pic
== SVR4_PIC
)
5112 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5113 mips_opts
.isa
< 3 ? "lw" : "ld",
5114 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5117 /* FIXME: This won't work for a 64 bit address. */
5118 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5121 if (mips_opts
.isa
>= 2)
5123 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5124 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5126 /* To avoid confusion in tc_gen_reloc, we must ensure
5127 that this does not become a variant frag. */
5128 frag_wane (frag_now
);
5139 /* Even on a big endian machine $fn comes before $fn+1. We have
5140 to adjust when loading from memory. */
5143 assert (mips_opts
.isa
< 2);
5144 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5145 target_big_endian
? treg
+ 1 : treg
,
5147 /* FIXME: A possible overflow which I don't know how to deal
5149 offset_expr
.X_add_number
+= 4;
5150 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5151 target_big_endian
? treg
: treg
+ 1,
5154 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5155 does not become a variant frag. */
5156 frag_wane (frag_now
);
5165 * The MIPS assembler seems to check for X_add_number not
5166 * being double aligned and generating:
5169 * addiu at,at,%lo(foo+1)
5172 * But, the resulting address is the same after relocation so why
5173 * generate the extra instruction?
5175 /* Itbl support may require additional care here. */
5177 if (mips_opts
.isa
>= 2)
5188 if (mips_opts
.isa
>= 2)
5196 /* Itbl support may require additional care here. */
5201 if (mips_opts
.isa
>= 3)
5212 if (mips_opts
.isa
>= 3)
5222 if (offset_expr
.X_op
!= O_symbol
5223 && offset_expr
.X_op
!= O_constant
)
5225 as_bad ("expression too complex");
5226 offset_expr
.X_op
= O_constant
;
5229 /* Even on a big endian machine $fn comes before $fn+1. We have
5230 to adjust when loading from memory. We set coproc if we must
5231 load $fn+1 first. */
5232 /* Itbl support may require additional care here. */
5233 if (! target_big_endian
)
5236 if (mips_pic
== NO_PIC
5237 || offset_expr
.X_op
== O_constant
)
5239 /* If this is a reference to a GP relative symbol, we want
5240 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5241 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5242 If we have a base register, we use this
5244 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5245 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5246 If this is not a GP relative symbol, we want
5247 lui $at,<sym> (BFD_RELOC_HI16_S)
5248 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5249 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5250 If there is a base register, we add it to $at after the
5251 lui instruction. If there is a constant, we always use
5253 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5254 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5273 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5274 mips_opts
.isa
< 3 ? "addu" : "daddu",
5275 "d,v,t", AT
, breg
, GP
);
5281 /* Itbl support may require additional care here. */
5282 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5283 coproc
? treg
+ 1 : treg
,
5284 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5285 offset_expr
.X_add_number
+= 4;
5287 /* Set mips_optimize to 2 to avoid inserting an
5289 hold_mips_optimize
= mips_optimize
;
5291 /* Itbl support may require additional care here. */
5292 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5293 coproc
? treg
: treg
+ 1,
5294 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5295 mips_optimize
= hold_mips_optimize
;
5297 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5298 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5299 used_at
&& mips_opts
.noat
),
5300 offset_expr
.X_add_symbol
, (offsetT
) 0,
5303 /* We just generated two relocs. When tc_gen_reloc
5304 handles this case, it will skip the first reloc and
5305 handle the second. The second reloc already has an
5306 extra addend of 4, which we added above. We must
5307 subtract it out, and then subtract another 4 to make
5308 the first reloc come out right. The second reloc
5309 will come out right because we are going to add 4 to
5310 offset_expr when we build its instruction below.
5312 If we have a symbol, then we don't want to include
5313 the offset, because it will wind up being included
5314 when we generate the reloc. */
5316 if (offset_expr
.X_op
== O_constant
)
5317 offset_expr
.X_add_number
-= 8;
5320 offset_expr
.X_add_number
= -4;
5321 offset_expr
.X_op
= O_constant
;
5324 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5329 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5330 mips_opts
.isa
< 3 ? "addu" : "daddu",
5331 "d,v,t", AT
, breg
, AT
);
5335 /* Itbl support may require additional care here. */
5336 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5337 coproc
? treg
+ 1 : treg
,
5338 (int) BFD_RELOC_LO16
, AT
);
5341 /* FIXME: How do we handle overflow here? */
5342 offset_expr
.X_add_number
+= 4;
5343 /* Itbl support may require additional care here. */
5344 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5345 coproc
? treg
: treg
+ 1,
5346 (int) BFD_RELOC_LO16
, AT
);
5348 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5352 /* If this is a reference to an external symbol, we want
5353 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5358 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5360 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5361 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5362 If there is a base register we add it to $at before the
5363 lwc1 instructions. If there is a constant we include it
5364 in the lwc1 instructions. */
5366 expr1
.X_add_number
= offset_expr
.X_add_number
;
5367 offset_expr
.X_add_number
= 0;
5368 if (expr1
.X_add_number
< -0x8000
5369 || expr1
.X_add_number
>= 0x8000 - 4)
5370 as_bad ("PIC code offset overflow (max 16 signed bits)");
5375 frag_grow (24 + off
);
5376 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5377 mips_opts
.isa
< 3 ? "lw" : "ld",
5378 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5381 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5382 mips_opts
.isa
< 3 ? "addu" : "daddu",
5383 "d,v,t", AT
, breg
, AT
);
5384 /* Itbl support may require additional care here. */
5385 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5386 coproc
? treg
+ 1 : treg
,
5387 (int) BFD_RELOC_LO16
, AT
);
5388 expr1
.X_add_number
+= 4;
5390 /* Set mips_optimize to 2 to avoid inserting an undesired
5392 hold_mips_optimize
= mips_optimize
;
5394 /* Itbl support may require additional care here. */
5395 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5396 coproc
? treg
: treg
+ 1,
5397 (int) BFD_RELOC_LO16
, AT
);
5398 mips_optimize
= hold_mips_optimize
;
5400 (void) frag_var (rs_machine_dependent
, 0, 0,
5401 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5402 offset_expr
.X_add_symbol
, (offsetT
) 0,
5405 else if (mips_pic
== SVR4_PIC
)
5409 /* If this is a reference to an external symbol, we want
5410 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5412 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5417 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5419 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5420 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5421 If there is a base register we add it to $at before the
5422 lwc1 instructions. If there is a constant we include it
5423 in the lwc1 instructions. */
5425 expr1
.X_add_number
= offset_expr
.X_add_number
;
5426 offset_expr
.X_add_number
= 0;
5427 if (expr1
.X_add_number
< -0x8000
5428 || expr1
.X_add_number
>= 0x8000 - 4)
5429 as_bad ("PIC code offset overflow (max 16 signed bits)");
5430 if (reg_needs_delay (GP
))
5439 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5440 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5441 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5442 mips_opts
.isa
< 3 ? "addu" : "daddu",
5443 "d,v,t", AT
, AT
, GP
);
5444 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5445 mips_opts
.isa
< 3 ? "lw" : "ld",
5446 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5447 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5449 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5450 mips_opts
.isa
< 3 ? "addu" : "daddu",
5451 "d,v,t", AT
, breg
, AT
);
5452 /* Itbl support may require additional care here. */
5453 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5454 coproc
? treg
+ 1 : treg
,
5455 (int) BFD_RELOC_LO16
, AT
);
5456 expr1
.X_add_number
+= 4;
5458 /* Set mips_optimize to 2 to avoid inserting an undesired
5460 hold_mips_optimize
= mips_optimize
;
5462 /* Itbl support may require additional care here. */
5463 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5464 coproc
? treg
: treg
+ 1,
5465 (int) BFD_RELOC_LO16
, AT
);
5466 mips_optimize
= hold_mips_optimize
;
5467 expr1
.X_add_number
-= 4;
5469 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5470 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5471 8 + gpdel
+ off
, 1, 0),
5472 offset_expr
.X_add_symbol
, (offsetT
) 0,
5476 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5479 macro_build (p
, &icnt
, &offset_expr
,
5480 mips_opts
.isa
< 3 ? "lw" : "ld",
5481 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5483 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5487 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5488 mips_opts
.isa
< 3 ? "addu" : "daddu",
5489 "d,v,t", AT
, breg
, AT
);
5492 /* Itbl support may require additional care here. */
5493 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5494 coproc
? treg
+ 1 : treg
,
5495 (int) BFD_RELOC_LO16
, AT
);
5497 expr1
.X_add_number
+= 4;
5499 /* Set mips_optimize to 2 to avoid inserting an undesired
5501 hold_mips_optimize
= mips_optimize
;
5503 /* Itbl support may require additional care here. */
5504 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5505 coproc
? treg
: treg
+ 1,
5506 (int) BFD_RELOC_LO16
, AT
);
5507 mips_optimize
= hold_mips_optimize
;
5509 else if (mips_pic
== EMBEDDED_PIC
)
5511 /* If there is no base register, we use
5512 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5513 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5514 If we have a base register, we use
5516 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5517 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5526 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5527 mips_opts
.isa
< 3 ? "addu" : "daddu",
5528 "d,v,t", AT
, breg
, GP
);
5533 /* Itbl support may require additional care here. */
5534 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5535 coproc
? treg
+ 1 : treg
,
5536 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5537 offset_expr
.X_add_number
+= 4;
5538 /* Itbl support may require additional care here. */
5539 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5540 coproc
? treg
: treg
+ 1,
5541 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5557 assert (mips_opts
.isa
< 3);
5558 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5559 (int) BFD_RELOC_LO16
, breg
);
5560 offset_expr
.X_add_number
+= 4;
5561 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5562 (int) BFD_RELOC_LO16
, breg
);
5565 /* New code added to support COPZ instructions.
5566 This code builds table entries out of the macros in mip_opcodes.
5567 R4000 uses interlocks to handle coproc delays.
5568 Other chips (like the R3000) require nops to be inserted for delays.
5570 FIXME: Currently, we require that the user handle delays.
5571 In order to fill delay slots for non-interlocked chips,
5572 we must have a way to specify delays based on the coprocessor.
5573 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5574 What are the side-effects of the cop instruction?
5575 What cache support might we have and what are its effects?
5576 Both coprocessor & memory require delays. how long???
5577 What registers are read/set/modified?
5579 If an itbl is provided to interpret cop instructions,
5580 this knowledge can be encoded in the itbl spec. */
5594 /* For now we just do C (same as Cz). */
5595 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5598 #ifdef LOSING_COMPILER
5600 /* Try and see if this is a new itbl instruction.
5601 This code builds table entries out of the macros in mip_opcodes.
5602 FIXME: For now we just assemble the expression and pass it's
5603 value along as a 32-bit immediate.
5604 We may want to have the assembler assemble this value,
5605 so that we gain the assembler's knowledge of delay slots,
5607 Would it be more efficient to use mask (id) here? */
5608 if (itbl_have_entries
5609 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5611 s
= ip
->insn_mo
->name
;
5613 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5614 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5621 as_warn ("Macro used $at after \".set noat\"");
5626 struct mips_cl_insn
*ip
;
5628 register int treg
, sreg
, dreg
, breg
;
5643 bfd_reloc_code_real_type r
;
5646 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5647 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5648 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5649 mask
= ip
->insn_mo
->mask
;
5651 expr1
.X_op
= O_constant
;
5652 expr1
.X_op_symbol
= NULL
;
5653 expr1
.X_add_symbol
= NULL
;
5654 expr1
.X_add_number
= 1;
5658 #endif /* LOSING_COMPILER */
5663 macro_build ((char *) NULL
, &icnt
, NULL
,
5664 dbl
? "dmultu" : "multu",
5666 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5672 /* The MIPS assembler some times generates shifts and adds. I'm
5673 not trying to be that fancy. GCC should do this for us
5675 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5676 macro_build ((char *) NULL
, &icnt
, NULL
,
5677 dbl
? "dmult" : "mult",
5679 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5685 mips_emit_delays (true);
5686 ++mips_opts
.noreorder
;
5687 mips_any_noreorder
= 1;
5688 macro_build ((char *) NULL
, &icnt
, NULL
,
5689 dbl
? "dmult" : "mult",
5691 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5692 macro_build ((char *) NULL
, &icnt
, NULL
,
5693 dbl
? "dsra32" : "sra",
5694 "d,w,<", dreg
, dreg
, 31);
5695 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5697 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5700 expr1
.X_add_number
= 8;
5701 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5702 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5703 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5705 --mips_opts
.noreorder
;
5706 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5712 mips_emit_delays (true);
5713 ++mips_opts
.noreorder
;
5714 mips_any_noreorder
= 1;
5715 macro_build ((char *) NULL
, &icnt
, NULL
,
5716 dbl
? "dmultu" : "multu",
5718 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5719 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5721 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5724 expr1
.X_add_number
= 8;
5725 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5726 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5727 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5729 --mips_opts
.noreorder
;
5733 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5734 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5735 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5737 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5741 if (imm_expr
.X_op
!= O_constant
)
5742 as_bad ("rotate count too large");
5743 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5744 (int) (imm_expr
.X_add_number
& 0x1f));
5745 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5746 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5747 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5751 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5752 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5753 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5755 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5759 if (imm_expr
.X_op
!= O_constant
)
5760 as_bad ("rotate count too large");
5761 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5762 (int) (imm_expr
.X_add_number
& 0x1f));
5763 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5764 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5765 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5769 assert (mips_opts
.isa
< 2);
5770 /* Even on a big endian machine $fn comes before $fn+1. We have
5771 to adjust when storing to memory. */
5772 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5773 target_big_endian
? treg
+ 1 : treg
,
5774 (int) BFD_RELOC_LO16
, breg
);
5775 offset_expr
.X_add_number
+= 4;
5776 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5777 target_big_endian
? treg
: treg
+ 1,
5778 (int) BFD_RELOC_LO16
, breg
);
5783 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5784 treg
, (int) BFD_RELOC_LO16
);
5786 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5787 sreg
, (int) BFD_RELOC_LO16
);
5790 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5792 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5793 dreg
, (int) BFD_RELOC_LO16
);
5798 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5800 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5801 sreg
, (int) BFD_RELOC_LO16
);
5806 as_warn ("Instruction %s: result is always false",
5808 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5811 if (imm_expr
.X_op
== O_constant
5812 && imm_expr
.X_add_number
>= 0
5813 && imm_expr
.X_add_number
< 0x10000)
5815 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5816 sreg
, (int) BFD_RELOC_LO16
);
5819 else if (imm_expr
.X_op
== O_constant
5820 && imm_expr
.X_add_number
> -0x8000
5821 && imm_expr
.X_add_number
< 0)
5823 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5824 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5825 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5826 "t,r,j", dreg
, sreg
,
5827 (int) BFD_RELOC_LO16
);
5832 load_register (&icnt
, AT
, &imm_expr
, 0);
5833 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5837 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5838 (int) BFD_RELOC_LO16
);
5843 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5849 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5850 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5851 (int) BFD_RELOC_LO16
);
5854 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5856 if (imm_expr
.X_op
== O_constant
5857 && imm_expr
.X_add_number
>= -0x8000
5858 && imm_expr
.X_add_number
< 0x8000)
5860 macro_build ((char *) NULL
, &icnt
, &expr1
,
5861 mask
== M_SGE_I
? "slti" : "sltiu",
5862 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5867 load_register (&icnt
, AT
, &imm_expr
, 0);
5868 macro_build ((char *) NULL
, &icnt
, NULL
,
5869 mask
== M_SGE_I
? "slt" : "sltu",
5870 "d,v,t", dreg
, sreg
, AT
);
5873 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5874 (int) BFD_RELOC_LO16
);
5879 case M_SGT
: /* sreg > treg <==> treg < sreg */
5885 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5888 case M_SGT_I
: /* sreg > I <==> I < sreg */
5894 load_register (&icnt
, AT
, &imm_expr
, 0);
5895 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5898 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5904 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5905 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5906 (int) BFD_RELOC_LO16
);
5909 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5915 load_register (&icnt
, AT
, &imm_expr
, 0);
5916 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5917 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5918 (int) BFD_RELOC_LO16
);
5922 if (imm_expr
.X_op
== O_constant
5923 && imm_expr
.X_add_number
>= -0x8000
5924 && imm_expr
.X_add_number
< 0x8000)
5926 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5927 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5930 load_register (&icnt
, AT
, &imm_expr
, 0);
5931 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5935 if (imm_expr
.X_op
== O_constant
5936 && imm_expr
.X_add_number
>= -0x8000
5937 && imm_expr
.X_add_number
< 0x8000)
5939 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5940 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5943 load_register (&icnt
, AT
, &imm_expr
, 0);
5944 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5950 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5953 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5957 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5959 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5965 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5967 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5973 as_warn ("Instruction %s: result is always true",
5975 macro_build ((char *) NULL
, &icnt
, &expr1
,
5976 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5977 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5980 if (imm_expr
.X_op
== O_constant
5981 && imm_expr
.X_add_number
>= 0
5982 && imm_expr
.X_add_number
< 0x10000)
5984 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5985 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5988 else if (imm_expr
.X_op
== O_constant
5989 && imm_expr
.X_add_number
> -0x8000
5990 && imm_expr
.X_add_number
< 0)
5992 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5993 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5994 mips_opts
.isa
< 3 ? "addiu" : "daddiu",
5995 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6000 load_register (&icnt
, AT
, &imm_expr
, 0);
6001 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6005 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6013 if (imm_expr
.X_op
== O_constant
6014 && imm_expr
.X_add_number
> -0x8000
6015 && imm_expr
.X_add_number
<= 0x8000)
6017 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6018 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6019 dbl
? "daddi" : "addi",
6020 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6023 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6024 macro_build ((char *) NULL
, &icnt
, NULL
,
6025 dbl
? "dsub" : "sub",
6026 "d,v,t", dreg
, sreg
, AT
);
6032 if (imm_expr
.X_op
== O_constant
6033 && imm_expr
.X_add_number
> -0x8000
6034 && imm_expr
.X_add_number
<= 0x8000)
6036 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6037 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6038 dbl
? "daddiu" : "addiu",
6039 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6042 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6043 macro_build ((char *) NULL
, &icnt
, NULL
,
6044 dbl
? "dsubu" : "subu",
6045 "d,v,t", dreg
, sreg
, AT
);
6066 load_register (&icnt
, AT
, &imm_expr
, 0);
6067 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6072 assert (mips_opts
.isa
< 2);
6073 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6074 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6077 * Is the double cfc1 instruction a bug in the mips assembler;
6078 * or is there a reason for it?
6080 mips_emit_delays (true);
6081 ++mips_opts
.noreorder
;
6082 mips_any_noreorder
= 1;
6083 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6084 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6085 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6086 expr1
.X_add_number
= 3;
6087 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6088 (int) BFD_RELOC_LO16
);
6089 expr1
.X_add_number
= 2;
6090 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6091 (int) BFD_RELOC_LO16
);
6092 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6093 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6094 macro_build ((char *) NULL
, &icnt
, NULL
,
6095 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6096 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6097 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6098 --mips_opts
.noreorder
;
6107 if (offset_expr
.X_add_number
>= 0x7fff)
6108 as_bad ("operand overflow");
6109 /* avoid load delay */
6110 if (! target_big_endian
)
6111 offset_expr
.X_add_number
+= 1;
6112 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6113 (int) BFD_RELOC_LO16
, breg
);
6114 if (! target_big_endian
)
6115 offset_expr
.X_add_number
-= 1;
6117 offset_expr
.X_add_number
+= 1;
6118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6119 (int) BFD_RELOC_LO16
, breg
);
6120 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6121 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6134 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6135 as_bad ("operand overflow");
6136 if (! target_big_endian
)
6137 offset_expr
.X_add_number
+= off
;
6138 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6139 (int) BFD_RELOC_LO16
, breg
);
6140 if (! target_big_endian
)
6141 offset_expr
.X_add_number
-= off
;
6143 offset_expr
.X_add_number
+= off
;
6144 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6145 (int) BFD_RELOC_LO16
, breg
);
6158 load_address (&icnt
, AT
, &offset_expr
);
6160 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6161 mips_opts
.isa
< 3 ? "addu" : "daddu",
6162 "d,v,t", AT
, AT
, breg
);
6163 if (! target_big_endian
)
6164 expr1
.X_add_number
= off
;
6166 expr1
.X_add_number
= 0;
6167 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6168 (int) BFD_RELOC_LO16
, AT
);
6169 if (! target_big_endian
)
6170 expr1
.X_add_number
= 0;
6172 expr1
.X_add_number
= off
;
6173 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6174 (int) BFD_RELOC_LO16
, AT
);
6179 load_address (&icnt
, AT
, &offset_expr
);
6181 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6182 mips_opts
.isa
< 3 ? "addu" : "daddu",
6183 "d,v,t", AT
, AT
, breg
);
6184 if (target_big_endian
)
6185 expr1
.X_add_number
= 0;
6186 macro_build ((char *) NULL
, &icnt
, &expr1
,
6187 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6188 (int) BFD_RELOC_LO16
, AT
);
6189 if (target_big_endian
)
6190 expr1
.X_add_number
= 1;
6192 expr1
.X_add_number
= 0;
6193 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6194 (int) BFD_RELOC_LO16
, AT
);
6195 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6197 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6202 if (offset_expr
.X_add_number
>= 0x7fff)
6203 as_bad ("operand overflow");
6204 if (target_big_endian
)
6205 offset_expr
.X_add_number
+= 1;
6206 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6207 (int) BFD_RELOC_LO16
, breg
);
6208 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6209 if (target_big_endian
)
6210 offset_expr
.X_add_number
-= 1;
6212 offset_expr
.X_add_number
+= 1;
6213 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6214 (int) BFD_RELOC_LO16
, breg
);
6227 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6228 as_bad ("operand overflow");
6229 if (! target_big_endian
)
6230 offset_expr
.X_add_number
+= off
;
6231 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6232 (int) BFD_RELOC_LO16
, breg
);
6233 if (! target_big_endian
)
6234 offset_expr
.X_add_number
-= off
;
6236 offset_expr
.X_add_number
+= off
;
6237 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6238 (int) BFD_RELOC_LO16
, breg
);
6251 load_address (&icnt
, AT
, &offset_expr
);
6253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6254 mips_opts
.isa
< 3 ? "addu" : "daddu",
6255 "d,v,t", AT
, AT
, breg
);
6256 if (! target_big_endian
)
6257 expr1
.X_add_number
= off
;
6259 expr1
.X_add_number
= 0;
6260 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6261 (int) BFD_RELOC_LO16
, AT
);
6262 if (! target_big_endian
)
6263 expr1
.X_add_number
= 0;
6265 expr1
.X_add_number
= off
;
6266 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6267 (int) BFD_RELOC_LO16
, AT
);
6271 load_address (&icnt
, AT
, &offset_expr
);
6273 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6274 mips_opts
.isa
< 3 ? "addu" : "daddu",
6275 "d,v,t", AT
, AT
, breg
);
6276 if (! target_big_endian
)
6277 expr1
.X_add_number
= 0;
6278 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6279 (int) BFD_RELOC_LO16
, AT
);
6280 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6282 if (! target_big_endian
)
6283 expr1
.X_add_number
= 1;
6285 expr1
.X_add_number
= 0;
6286 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6287 (int) BFD_RELOC_LO16
, AT
);
6288 if (! target_big_endian
)
6289 expr1
.X_add_number
= 0;
6291 expr1
.X_add_number
= 1;
6292 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6293 (int) BFD_RELOC_LO16
, AT
);
6294 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6296 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6301 /* FIXME: Check if this is one of the itbl macros, since they
6302 are added dynamically. */
6303 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6307 as_warn ("Macro used $at after \".set noat\"");
6310 /* Implement macros in mips16 mode. */
6314 struct mips_cl_insn
*ip
;
6317 int xreg
, yreg
, zreg
, tmp
;
6321 const char *s
, *s2
, *s3
;
6323 mask
= ip
->insn_mo
->mask
;
6325 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6326 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6327 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6331 expr1
.X_op
= O_constant
;
6332 expr1
.X_op_symbol
= NULL
;
6333 expr1
.X_add_symbol
= NULL
;
6334 expr1
.X_add_number
= 1;
6353 mips_emit_delays (true);
6354 ++mips_opts
.noreorder
;
6355 mips_any_noreorder
= 1;
6356 macro_build ((char *) NULL
, &icnt
, NULL
,
6357 dbl
? "ddiv" : "div",
6358 "0,x,y", xreg
, yreg
);
6359 expr1
.X_add_number
= 2;
6360 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6361 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6362 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6363 since that causes an overflow. We should do that as well,
6364 but I don't see how to do the comparisons without a temporary
6366 --mips_opts
.noreorder
;
6367 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6386 mips_emit_delays (true);
6387 ++mips_opts
.noreorder
;
6388 mips_any_noreorder
= 1;
6389 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6390 expr1
.X_add_number
= 2;
6391 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6392 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6393 --mips_opts
.noreorder
;
6394 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6400 macro_build ((char *) NULL
, &icnt
, NULL
,
6401 dbl
? "dmultu" : "multu",
6403 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6411 if (imm_expr
.X_op
!= O_constant
)
6412 as_bad ("Unsupported large constant");
6413 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6414 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6415 dbl
? "daddiu" : "addiu",
6416 "y,x,4", yreg
, xreg
);
6420 if (imm_expr
.X_op
!= O_constant
)
6421 as_bad ("Unsupported large constant");
6422 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6423 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6428 if (imm_expr
.X_op
!= O_constant
)
6429 as_bad ("Unsupported large constant");
6430 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6431 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6454 goto do_reverse_branch
;
6458 goto do_reverse_branch
;
6470 goto do_reverse_branch
;
6481 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6483 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6510 goto do_addone_branch_i
;
6515 goto do_addone_branch_i
;
6530 goto do_addone_branch_i
;
6537 if (imm_expr
.X_op
!= O_constant
)
6538 as_bad ("Unsupported large constant");
6539 ++imm_expr
.X_add_number
;
6542 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6543 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6547 expr1
.X_add_number
= 0;
6548 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6550 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6551 "move", "y,X", xreg
, yreg
);
6552 expr1
.X_add_number
= 2;
6553 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6554 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6555 "neg", "x,w", xreg
, xreg
);
6559 /* This routine assembles an instruction into its binary format. As a
6560 side effect, it sets one of the global variables imm_reloc or
6561 offset_reloc to the type of relocation to do if one of the operands
6562 is an address expression. */
6567 struct mips_cl_insn
*ip
;
6572 struct mips_opcode
*insn
;
6575 unsigned int lastregno
= 0;
6580 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6585 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6587 insn_error
= "unrecognized opcode";
6596 assert (strcmp (insn
->name
, str
) == 0);
6598 if (insn
->pinfo
== INSN_MACRO
)
6599 insn_isa
= insn
->match
;
6600 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA1
)
6602 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA2
)
6604 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA3
)
6606 else if ((insn
->membership
& INSN_ISA
) == INSN_ISA4
)
6611 if (insn_isa
<= mips_opts
.isa
)
6613 else if (insn
->pinfo
== INSN_MACRO
)
6615 else if ((mips_4650
&& (insn
->membership
& INSN_4650
) != 0)
6616 || (mips_4010
&& (insn
->membership
& INSN_4010
) != 0)
6617 || (mips_4100
&& (insn
->membership
& INSN_4100
) != 0)
6618 /* start-sanitize-r5900 */
6619 || (mips_5900
&& (insn
->membership
& INSN_5900
) != 0)
6620 /* end-sanitize-r5900 */
6621 || (mips_3900
&& (insn
->membership
& INSN_3900
) != 0))
6624 if (mips_4650
&& (insn
->pinfo
& FP_D
) != 0)
6626 /* start-sanitize-r5900 */
6627 if (mips_5900
&& (insn
->pinfo
& FP_D
) != 0)
6629 /* end-sanitize-r5900 */
6636 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6637 && strcmp (insn
->name
, insn
[1].name
) == 0)
6643 || insn_isa
<= mips_opts
.isa
)
6644 insn_error
= "opcode not supported on this processor";
6647 static char buf
[100];
6649 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6656 ip
->insn_opcode
= insn
->match
;
6657 for (args
= insn
->args
;; ++args
)
6663 case '\0': /* end of args */
6676 ip
->insn_opcode
|= lastregno
<< 21;
6681 ip
->insn_opcode
|= lastregno
<< 16;
6685 ip
->insn_opcode
|= lastregno
<< 11;
6691 /* handle optional base register.
6692 Either the base register is omitted or
6693 we must have a left paren. */
6694 /* this is dependent on the next operand specifier
6695 is a 'b' for base register */
6696 assert (args
[1] == 'b');
6700 case ')': /* these must match exactly */
6705 case '<': /* must be at least one digit */
6707 * According to the manual, if the shift amount is greater
6708 * than 31 or less than 0 the the shift amount should be
6709 * mod 32. In reality the mips assembler issues an error.
6710 * We issue a warning and mask out all but the low 5 bits.
6712 my_getExpression (&imm_expr
, s
);
6713 check_absolute_expr (ip
, &imm_expr
);
6714 if ((unsigned long) imm_expr
.X_add_number
> 31)
6716 as_warn ("Improper shift amount (%ld)",
6717 (long) imm_expr
.X_add_number
);
6718 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6720 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6721 imm_expr
.X_op
= O_absent
;
6725 case '>': /* shift amount minus 32 */
6726 my_getExpression (&imm_expr
, s
);
6727 check_absolute_expr (ip
, &imm_expr
);
6728 if ((unsigned long) imm_expr
.X_add_number
< 32
6729 || (unsigned long) imm_expr
.X_add_number
> 63)
6731 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6732 imm_expr
.X_op
= O_absent
;
6736 case 'k': /* cache code */
6737 case 'h': /* prefx code */
6738 my_getExpression (&imm_expr
, s
);
6739 check_absolute_expr (ip
, &imm_expr
);
6740 if ((unsigned long) imm_expr
.X_add_number
> 31)
6742 as_warn ("Invalid value for `%s' (%lu)",
6744 (unsigned long) imm_expr
.X_add_number
);
6745 imm_expr
.X_add_number
&= 0x1f;
6748 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6750 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6751 imm_expr
.X_op
= O_absent
;
6755 case 'c': /* break code */
6756 my_getExpression (&imm_expr
, s
);
6757 check_absolute_expr (ip
, &imm_expr
);
6758 if ((unsigned) imm_expr
.X_add_number
> 1023)
6759 as_warn ("Illegal break code (%ld)",
6760 (long) imm_expr
.X_add_number
);
6761 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6762 imm_expr
.X_op
= O_absent
;
6766 case 'B': /* syscall code */
6767 my_getExpression (&imm_expr
, s
);
6768 check_absolute_expr (ip
, &imm_expr
);
6769 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6770 as_warn ("Illegal syscall code (%ld)",
6771 (long) imm_expr
.X_add_number
);
6772 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6773 imm_expr
.X_op
= O_absent
;
6777 case 'C': /* Coprocessor code */
6778 my_getExpression (&imm_expr
, s
);
6779 check_absolute_expr (ip
, &imm_expr
);
6780 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6782 as_warn ("Coproccesor code > 25 bits (%ld)",
6783 (long) imm_expr
.X_add_number
);
6784 imm_expr
.X_add_number
&= ((1<<25) - 1);
6786 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6787 imm_expr
.X_op
= O_absent
;
6791 case 'b': /* base register */
6792 case 'd': /* destination register */
6793 case 's': /* source register */
6794 case 't': /* target register */
6795 case 'r': /* both target and source */
6796 case 'v': /* both dest and source */
6797 case 'w': /* both dest and target */
6798 case 'E': /* coprocessor target register */
6799 case 'G': /* coprocessor destination register */
6800 case 'x': /* ignore register name */
6801 case 'z': /* must be zero register */
6815 while (isdigit (*s
));
6817 as_bad ("Invalid register number (%d)", regno
);
6819 else if (*args
== 'E' || *args
== 'G')
6823 if (s
[1] == 'f' && s
[2] == 'p')
6828 else if (s
[1] == 's' && s
[2] == 'p')
6833 else if (s
[1] == 'g' && s
[2] == 'p')
6838 else if (s
[1] == 'a' && s
[2] == 't')
6843 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6848 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6853 else if (itbl_have_entries
)
6858 p
= s
+1; /* advance past '$' */
6859 n
= itbl_get_field (&p
); /* n is name */
6861 /* See if this is a register defined in an
6863 r
= itbl_get_reg_val (n
);
6866 /* Get_field advances to the start of
6867 the next field, so we need to back
6868 rack to the end of the last field. */
6872 s
= strchr (s
,'\0');
6885 as_warn ("Used $at without \".set noat\"");
6891 if (c
== 'r' || c
== 'v' || c
== 'w')
6898 /* 'z' only matches $0. */
6899 if (c
== 'z' && regno
!= 0)
6902 /* Now that we have assembled one operand, we use the args string
6903 * to figure out where it goes in the instruction. */
6910 ip
->insn_opcode
|= regno
<< 21;
6914 ip
->insn_opcode
|= regno
<< 11;
6919 ip
->insn_opcode
|= regno
<< 16;
6922 /* This case exists because on the r3000 trunc
6923 expands into a macro which requires a gp
6924 register. On the r6000 or r4000 it is
6925 assembled into a single instruction which
6926 ignores the register. Thus the insn version
6927 is MIPS_ISA2 and uses 'x', and the macro
6928 version is MIPS_ISA1 and uses 't'. */
6931 /* This case is for the div instruction, which
6932 acts differently if the destination argument
6933 is $0. This only matches $0, and is checked
6934 outside the switch. */
6937 /* Itbl operand; not yet implemented. FIXME ?? */
6939 /* What about all other operands like 'i', which
6940 can be specified in the opcode table? */
6950 ip
->insn_opcode
|= lastregno
<< 21;
6953 ip
->insn_opcode
|= lastregno
<< 16;
6958 case 'D': /* floating point destination register */
6959 case 'S': /* floating point source register */
6960 case 'T': /* floating point target register */
6961 case 'R': /* floating point source register */
6965 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6975 while (isdigit (*s
));
6978 as_bad ("Invalid float register number (%d)", regno
);
6980 if ((regno
& 1) != 0
6981 && mips_opts
.isa
< 3
6982 && ! (strcmp (str
, "mtc1") == 0
6983 || strcmp (str
, "mfc1") == 0
6984 || strcmp (str
, "lwc1") == 0
6985 || strcmp (str
, "swc1") == 0
6986 || strcmp (str
, "l.s") == 0
6987 || strcmp (str
, "s.s") == 0))
6988 as_warn ("Float register should be even, was %d",
6996 if (c
== 'V' || c
== 'W')
7006 ip
->insn_opcode
|= regno
<< 6;
7010 ip
->insn_opcode
|= regno
<< 11;
7014 ip
->insn_opcode
|= regno
<< 16;
7017 ip
->insn_opcode
|= regno
<< 21;
7026 ip
->insn_opcode
|= lastregno
<< 11;
7029 ip
->insn_opcode
|= lastregno
<< 16;
7035 my_getExpression (&imm_expr
, s
);
7036 if (imm_expr
.X_op
!= O_big
7037 && imm_expr
.X_op
!= O_constant
)
7038 insn_error
= "absolute expression required";
7043 my_getExpression (&offset_expr
, s
);
7044 imm_reloc
= BFD_RELOC_32
;
7056 unsigned char temp
[8];
7058 unsigned int length
;
7063 /* These only appear as the last operand in an
7064 instruction, and every instruction that accepts
7065 them in any variant accepts them in all variants.
7066 This means we don't have to worry about backing out
7067 any changes if the instruction does not match.
7069 The difference between them is the size of the
7070 floating point constant and where it goes. For 'F'
7071 and 'L' the constant is 64 bits; for 'f' and 'l' it
7072 is 32 bits. Where the constant is placed is based
7073 on how the MIPS assembler does things:
7076 f -- immediate value
7079 The .lit4 and .lit8 sections are only used if
7080 permitted by the -G argument.
7082 When generating embedded PIC code, we use the
7083 .lit8 section but not the .lit4 section (we can do
7084 .lit4 inline easily; we need to put .lit8
7085 somewhere in the data segment, and using .lit8
7086 permits the linker to eventually combine identical
7089 f64
= *args
== 'F' || *args
== 'L';
7091 save_in
= input_line_pointer
;
7092 input_line_pointer
= s
;
7093 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7095 s
= input_line_pointer
;
7096 input_line_pointer
= save_in
;
7097 if (err
!= NULL
&& *err
!= '\0')
7099 as_bad ("Bad floating point constant: %s", err
);
7100 memset (temp
, '\0', sizeof temp
);
7101 length
= f64
? 8 : 4;
7104 assert (length
== (f64
? 8 : 4));
7108 && (! USE_GLOBAL_POINTER_OPT
7109 || mips_pic
== EMBEDDED_PIC
7110 || g_switch_value
< 4
7111 || (temp
[0] == 0 && temp
[1] == 0)
7112 || (temp
[2] == 0 && temp
[3] == 0))))
7114 imm_expr
.X_op
= O_constant
;
7115 if (! target_big_endian
)
7116 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7118 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7121 && ((temp
[0] == 0 && temp
[1] == 0)
7122 || (temp
[2] == 0 && temp
[3] == 0))
7123 && ((temp
[4] == 0 && temp
[5] == 0)
7124 || (temp
[6] == 0 && temp
[7] == 0)))
7126 /* The value is simple enough to load with a
7127 couple of instructions. In mips1 mode, set
7128 imm_expr to the high order 32 bits and
7129 offset_expr to the low order 32 bits.
7130 Otherwise, set imm_expr to the entire 64 bit
7132 if (mips_opts
.isa
< 3)
7134 imm_expr
.X_op
= O_constant
;
7135 offset_expr
.X_op
= O_constant
;
7136 if (! target_big_endian
)
7138 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7139 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7143 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7144 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7146 if (offset_expr
.X_add_number
== 0)
7147 offset_expr
.X_op
= O_absent
;
7149 else if (sizeof (imm_expr
.X_add_number
) > 4)
7151 imm_expr
.X_op
= O_constant
;
7152 if (! target_big_endian
)
7153 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7155 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7159 imm_expr
.X_op
= O_big
;
7160 imm_expr
.X_add_number
= 4;
7161 if (! target_big_endian
)
7163 generic_bignum
[0] = bfd_getl16 (temp
);
7164 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7165 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7166 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7170 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7171 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7172 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7173 generic_bignum
[3] = bfd_getb16 (temp
);
7179 const char *newname
;
7182 /* Switch to the right section. */
7184 subseg
= now_subseg
;
7187 default: /* unused default case avoids warnings. */
7189 newname
= RDATA_SECTION_NAME
;
7190 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7194 newname
= RDATA_SECTION_NAME
;
7197 assert (!USE_GLOBAL_POINTER_OPT
7198 || g_switch_value
>= 4);
7202 new_seg
= subseg_new (newname
, (subsegT
) 0);
7203 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7204 bfd_set_section_flags (stdoutput
, new_seg
,
7209 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7210 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7211 && strcmp (TARGET_OS
, "elf") != 0)
7212 record_alignment (new_seg
, 4);
7214 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7216 as_bad ("Can't use floating point insn in this section");
7218 /* Set the argument to the current address in the
7220 offset_expr
.X_op
= O_symbol
;
7221 offset_expr
.X_add_symbol
=
7222 symbol_new ("L0\001", now_seg
,
7223 (valueT
) frag_now_fix (), frag_now
);
7224 offset_expr
.X_add_number
= 0;
7226 /* Put the floating point number into the section. */
7227 p
= frag_more ((int) length
);
7228 memcpy (p
, temp
, length
);
7230 /* Switch back to the original section. */
7231 subseg_set (seg
, subseg
);
7236 case 'i': /* 16 bit unsigned immediate */
7237 case 'j': /* 16 bit signed immediate */
7238 imm_reloc
= BFD_RELOC_LO16
;
7239 c
= my_getSmallExpression (&imm_expr
, s
);
7244 if (imm_expr
.X_op
== O_constant
)
7245 imm_expr
.X_add_number
=
7246 (imm_expr
.X_add_number
>> 16) & 0xffff;
7249 imm_reloc
= BFD_RELOC_HI16_S
;
7250 imm_unmatched_hi
= true;
7253 imm_reloc
= BFD_RELOC_HI16
;
7258 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7259 || ((imm_expr
.X_add_number
< 0
7260 || imm_expr
.X_add_number
>= 0x10000)
7261 && imm_expr
.X_op
== O_constant
))
7263 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7264 !strcmp (insn
->name
, insn
[1].name
))
7266 if (imm_expr
.X_op
!= O_constant
7267 && imm_expr
.X_op
!= O_big
)
7268 insn_error
= "absolute expression required";
7270 as_bad ("16 bit expression not in range 0..65535");
7278 /* The upper bound should be 0x8000, but
7279 unfortunately the MIPS assembler accepts numbers
7280 from 0x8000 to 0xffff and sign extends them, and
7281 we want to be compatible. We only permit this
7282 extended range for an instruction which does not
7283 provide any further alternates, since those
7284 alternates may handle other cases. People should
7285 use the numbers they mean, rather than relying on
7286 a mysterious sign extension. */
7287 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7288 strcmp (insn
->name
, insn
[1].name
) == 0);
7293 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7294 || ((imm_expr
.X_add_number
< -0x8000
7295 || imm_expr
.X_add_number
>= max
)
7296 && imm_expr
.X_op
== O_constant
)
7298 && imm_expr
.X_add_number
< 0
7299 && mips_opts
.isa
>= 3
7300 && imm_expr
.X_unsigned
7301 && sizeof (imm_expr
.X_add_number
) <= 4))
7305 if (imm_expr
.X_op
!= O_constant
7306 && imm_expr
.X_op
!= O_big
)
7307 insn_error
= "absolute expression required";
7309 as_bad ("16 bit expression not in range -32768..32767");
7315 case 'o': /* 16 bit offset */
7316 c
= my_getSmallExpression (&offset_expr
, s
);
7318 /* If this value won't fit into a 16 bit offset, then go
7319 find a macro that will generate the 32 bit offset
7320 code pattern. As a special hack, we accept the
7321 difference of two local symbols as a constant. This
7322 is required to suppose embedded PIC switches, which
7323 use an instruction which looks like
7324 lw $4,$L12-$LS12($4)
7325 The problem with handling this in a more general
7326 fashion is that the macro function doesn't expect to
7327 see anything which can be handled in a single
7328 constant instruction. */
7330 && (offset_expr
.X_op
!= O_constant
7331 || offset_expr
.X_add_number
>= 0x8000
7332 || offset_expr
.X_add_number
< -0x8000)
7333 && (mips_pic
!= EMBEDDED_PIC
7334 || offset_expr
.X_op
!= O_subtract
7335 || now_seg
!= text_section
7336 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7340 offset_reloc
= BFD_RELOC_LO16
;
7341 if (c
== 'h' || c
== 'H')
7343 assert (offset_expr
.X_op
== O_constant
);
7344 offset_expr
.X_add_number
=
7345 (offset_expr
.X_add_number
>> 16) & 0xffff;
7350 case 'p': /* pc relative offset */
7351 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7352 my_getExpression (&offset_expr
, s
);
7356 case 'u': /* upper 16 bits */
7357 c
= my_getSmallExpression (&imm_expr
, s
);
7358 if (imm_expr
.X_op
== O_constant
7359 && (imm_expr
.X_add_number
< 0
7360 || imm_expr
.X_add_number
>= 0x10000))
7361 as_bad ("lui expression not in range 0..65535");
7362 imm_reloc
= BFD_RELOC_LO16
;
7367 if (imm_expr
.X_op
== O_constant
)
7368 imm_expr
.X_add_number
=
7369 (imm_expr
.X_add_number
>> 16) & 0xffff;
7372 imm_reloc
= BFD_RELOC_HI16_S
;
7373 imm_unmatched_hi
= true;
7376 imm_reloc
= BFD_RELOC_HI16
;
7382 case 'a': /* 26 bit address */
7383 my_getExpression (&offset_expr
, s
);
7385 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7388 case 'N': /* 3 bit branch condition code */
7389 case 'M': /* 3 bit compare condition code */
7390 if (strncmp (s
, "$fcc", 4) != 0)
7400 while (isdigit (*s
));
7402 as_bad ("invalid condition code register $fcc%d", regno
);
7404 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7406 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7410 fprintf (stderr
, "bad char = '%c'\n", *args
);
7415 /* Args don't match. */
7416 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7417 !strcmp (insn
->name
, insn
[1].name
))
7423 insn_error
= "illegal operands";
7428 /* This routine assembles an instruction into its binary format when
7429 assembling for the mips16. As a side effect, it sets one of the
7430 global variables imm_reloc or offset_reloc to the type of
7431 relocation to do if one of the operands is an address expression.
7432 It also sets mips16_small and mips16_ext if the user explicitly
7433 requested a small or extended instruction. */
7438 struct mips_cl_insn
*ip
;
7442 struct mips_opcode
*insn
;
7445 unsigned int lastregno
= 0;
7450 mips16_small
= false;
7453 for (s
= str
; islower (*s
); ++s
)
7465 if (s
[1] == 't' && s
[2] == ' ')
7468 mips16_small
= true;
7472 else if (s
[1] == 'e' && s
[2] == ' ')
7481 insn_error
= "unknown opcode";
7485 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7486 mips16_small
= true;
7488 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7490 insn_error
= "unrecognized opcode";
7497 assert (strcmp (insn
->name
, str
) == 0);
7500 ip
->insn_opcode
= insn
->match
;
7501 ip
->use_extend
= false;
7502 imm_expr
.X_op
= O_absent
;
7503 imm_reloc
= BFD_RELOC_UNUSED
;
7504 offset_expr
.X_op
= O_absent
;
7505 offset_reloc
= BFD_RELOC_UNUSED
;
7506 for (args
= insn
->args
; 1; ++args
)
7513 /* In this switch statement we call break if we did not find
7514 a match, continue if we did find a match, or return if we
7523 /* Stuff the immediate value in now, if we can. */
7524 if (imm_expr
.X_op
== O_constant
7525 && imm_reloc
> BFD_RELOC_UNUSED
7526 && insn
->pinfo
!= INSN_MACRO
)
7528 mips16_immed ((char *) NULL
, 0,
7529 imm_reloc
- BFD_RELOC_UNUSED
,
7530 imm_expr
.X_add_number
, true, mips16_small
,
7531 mips16_ext
, &ip
->insn_opcode
,
7532 &ip
->use_extend
, &ip
->extend
);
7533 imm_expr
.X_op
= O_absent
;
7534 imm_reloc
= BFD_RELOC_UNUSED
;
7548 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7551 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7567 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7569 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7596 while (isdigit (*s
));
7599 as_bad ("invalid register number (%d)", regno
);
7605 if (s
[1] == 'f' && s
[2] == 'p')
7610 else if (s
[1] == 's' && s
[2] == 'p')
7615 else if (s
[1] == 'g' && s
[2] == 'p')
7620 else if (s
[1] == 'a' && s
[2] == 't')
7625 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7630 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7643 if (c
== 'v' || c
== 'w')
7645 regno
= mips16_to_32_reg_map
[lastregno
];
7659 regno
= mips32_to_16_reg_map
[regno
];
7664 regno
= ILLEGAL_REG
;
7669 regno
= ILLEGAL_REG
;
7674 regno
= ILLEGAL_REG
;
7679 if (regno
== AT
&& ! mips_opts
.noat
)
7680 as_warn ("used $at without \".set noat\"");
7687 if (regno
== ILLEGAL_REG
)
7694 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7698 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7701 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7704 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7710 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7713 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7714 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7724 if (strncmp (s
, "$pc", 3) == 0)
7748 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7750 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7751 and generate the appropriate reloc. If the text
7752 inside %gprel is not a symbol name with an
7753 optional offset, then we generate a normal reloc
7754 and will probably fail later. */
7755 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7756 if (imm_expr
.X_op
== O_symbol
)
7759 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7761 ip
->use_extend
= true;
7768 /* Just pick up a normal expression. */
7769 my_getExpression (&imm_expr
, s
);
7772 if (imm_expr
.X_op
== O_register
)
7774 /* What we thought was an expression turned out to
7777 if (s
[0] == '(' && args
[1] == '(')
7779 /* It looks like the expression was omitted
7780 before a register indirection, which means
7781 that the expression is implicitly zero. We
7782 still set up imm_expr, so that we handle
7783 explicit extensions correctly. */
7784 imm_expr
.X_op
= O_constant
;
7785 imm_expr
.X_add_number
= 0;
7786 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7793 /* We need to relax this instruction. */
7794 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7803 /* We use offset_reloc rather than imm_reloc for the PC
7804 relative operands. This lets macros with both
7805 immediate and address operands work correctly. */
7806 my_getExpression (&offset_expr
, s
);
7808 if (offset_expr
.X_op
== O_register
)
7811 /* We need to relax this instruction. */
7812 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7816 case '6': /* break code */
7817 my_getExpression (&imm_expr
, s
);
7818 check_absolute_expr (ip
, &imm_expr
);
7819 if ((unsigned long) imm_expr
.X_add_number
> 63)
7821 as_warn ("Invalid value for `%s' (%lu)",
7823 (unsigned long) imm_expr
.X_add_number
);
7824 imm_expr
.X_add_number
&= 0x3f;
7826 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7827 imm_expr
.X_op
= O_absent
;
7831 case 'a': /* 26 bit address */
7832 my_getExpression (&offset_expr
, s
);
7834 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7835 ip
->insn_opcode
<<= 16;
7838 case 'l': /* register list for entry macro */
7839 case 'L': /* register list for exit macro */
7849 int freg
, reg1
, reg2
;
7851 while (*s
== ' ' || *s
== ',')
7855 as_bad ("can't parse register list");
7867 while (isdigit (*s
))
7889 as_bad ("invalid register list");
7894 while (isdigit (*s
))
7901 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7906 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7911 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7912 mask
|= (reg2
- 3) << 3;
7913 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7914 mask
|= (reg2
- 15) << 1;
7915 else if (reg1
== 31 && reg2
== 31)
7919 as_bad ("invalid register list");
7923 /* The mask is filled in in the opcode table for the
7924 benefit of the disassembler. We remove it before
7925 applying the actual mask. */
7926 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7927 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7931 case 'e': /* extend code */
7932 my_getExpression (&imm_expr
, s
);
7933 check_absolute_expr (ip
, &imm_expr
);
7934 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7936 as_warn ("Invalid value for `%s' (%lu)",
7938 (unsigned long) imm_expr
.X_add_number
);
7939 imm_expr
.X_add_number
&= 0x7ff;
7941 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7942 imm_expr
.X_op
= O_absent
;
7952 /* Args don't match. */
7953 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7954 strcmp (insn
->name
, insn
[1].name
) == 0)
7961 insn_error
= "illegal operands";
7967 /* This structure holds information we know about a mips16 immediate
7970 struct mips16_immed_operand
7972 /* The type code used in the argument string in the opcode table. */
7974 /* The number of bits in the short form of the opcode. */
7976 /* The number of bits in the extended form of the opcode. */
7978 /* The amount by which the short form is shifted when it is used;
7979 for example, the sw instruction has a shift count of 2. */
7981 /* The amount by which the short form is shifted when it is stored
7982 into the instruction code. */
7984 /* Non-zero if the short form is unsigned. */
7986 /* Non-zero if the extended form is unsigned. */
7988 /* Non-zero if the value is PC relative. */
7992 /* The mips16 immediate operand types. */
7994 static const struct mips16_immed_operand mips16_immed_operands
[] =
7996 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7997 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7998 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7999 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8000 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8001 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8002 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8003 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8004 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8005 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8006 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8007 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8008 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8009 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8010 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8011 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8012 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8013 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8014 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8015 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8016 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8019 #define MIPS16_NUM_IMMED \
8020 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8022 /* Handle a mips16 instruction with an immediate value. This or's the
8023 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8024 whether an extended value is needed; if one is needed, it sets
8025 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8026 If SMALL is true, an unextended opcode was explicitly requested.
8027 If EXT is true, an extended opcode was explicitly requested. If
8028 WARN is true, warn if EXT does not match reality. */
8031 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8040 unsigned long *insn
;
8041 boolean
*use_extend
;
8042 unsigned short *extend
;
8044 register const struct mips16_immed_operand
*op
;
8045 int mintiny
, maxtiny
;
8048 op
= mips16_immed_operands
;
8049 while (op
->type
!= type
)
8052 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8057 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8060 maxtiny
= 1 << op
->nbits
;
8065 maxtiny
= (1 << op
->nbits
) - 1;
8070 mintiny
= - (1 << (op
->nbits
- 1));
8071 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8074 /* Branch offsets have an implicit 0 in the lowest bit. */
8075 if (type
== 'p' || type
== 'q')
8078 if ((val
& ((1 << op
->shift
) - 1)) != 0
8079 || val
< (mintiny
<< op
->shift
)
8080 || val
> (maxtiny
<< op
->shift
))
8085 if (warn
&& ext
&& ! needext
)
8086 as_warn_where (file
, line
, "extended operand requested but not required");
8087 if (small
&& needext
)
8088 as_bad_where (file
, line
, "invalid unextended operand value");
8090 if (small
|| (! ext
&& ! needext
))
8094 *use_extend
= false;
8095 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8096 insnval
<<= op
->op_shift
;
8101 long minext
, maxext
;
8107 maxext
= (1 << op
->extbits
) - 1;
8111 minext
= - (1 << (op
->extbits
- 1));
8112 maxext
= (1 << (op
->extbits
- 1)) - 1;
8114 if (val
< minext
|| val
> maxext
)
8115 as_bad_where (file
, line
,
8116 "operand value out of range for instruction");
8119 if (op
->extbits
== 16)
8121 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8124 else if (op
->extbits
== 15)
8126 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8131 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8135 *extend
= (unsigned short) extval
;
8144 my_getSmallExpression (ep
, str
)
8155 ((str
[1] == 'h' && str
[2] == 'i')
8156 || (str
[1] == 'H' && str
[2] == 'I')
8157 || (str
[1] == 'l' && str
[2] == 'o'))
8169 * A small expression may be followed by a base register.
8170 * Scan to the end of this operand, and then back over a possible
8171 * base register. Then scan the small expression up to that
8172 * point. (Based on code in sparc.c...)
8174 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8176 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8178 if (isdigit (sp
[-2]))
8180 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
8182 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8188 else if (sp
- 5 >= str
8191 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8192 || (sp
[-3] == 's' && sp
[-2] == 'p')
8193 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8194 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8200 /* no expression means zero offset */
8203 /* %xx(reg) is an error */
8204 ep
->X_op
= O_absent
;
8209 ep
->X_op
= O_constant
;
8212 ep
->X_add_symbol
= NULL
;
8213 ep
->X_op_symbol
= NULL
;
8214 ep
->X_add_number
= 0;
8219 my_getExpression (ep
, str
);
8226 my_getExpression (ep
, str
);
8227 return c
; /* => %hi or %lo encountered */
8231 my_getExpression (ep
, str
)
8237 save_in
= input_line_pointer
;
8238 input_line_pointer
= str
;
8240 expr_end
= input_line_pointer
;
8241 input_line_pointer
= save_in
;
8243 /* If we are in mips16 mode, and this is an expression based on `.',
8244 then we bump the value of the symbol by 1 since that is how other
8245 text symbols are handled. We don't bother to handle complex
8246 expressions, just `.' plus or minus a constant. */
8247 if (mips_opts
.mips16
8248 && ep
->X_op
== O_symbol
8249 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8250 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8251 && ep
->X_add_symbol
->sy_frag
== frag_now
8252 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
8253 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
8254 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
8257 /* Turn a string in input_line_pointer into a floating point constant
8258 of type type, and store the appropriate bytes in *litP. The number
8259 of LITTLENUMS emitted is stored in *sizeP . An error message is
8260 returned, or NULL on OK. */
8263 md_atof (type
, litP
, sizeP
)
8269 LITTLENUM_TYPE words
[4];
8285 return "bad call to md_atof";
8288 t
= atof_ieee (input_line_pointer
, type
, words
);
8290 input_line_pointer
= t
;
8294 if (! target_big_endian
)
8296 for (i
= prec
- 1; i
>= 0; i
--)
8298 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8304 for (i
= 0; i
< prec
; i
++)
8306 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8315 md_number_to_chars (buf
, val
, n
)
8320 if (target_big_endian
)
8321 number_to_chars_bigendian (buf
, val
, n
);
8323 number_to_chars_littleendian (buf
, val
, n
);
8326 CONST
char *md_shortopts
= "O::g::G:";
8328 struct option md_longopts
[] = {
8329 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8330 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8331 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8332 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8333 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8334 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8335 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8336 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8337 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8338 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8339 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8340 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8341 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8342 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8343 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8344 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8345 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8346 {"break", no_argument
, NULL
, OPTION_BREAK
},
8347 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8348 #define OPTION_EB (OPTION_MD_BASE + 11)
8349 {"EB", no_argument
, NULL
, OPTION_EB
},
8350 #define OPTION_EL (OPTION_MD_BASE + 12)
8351 {"EL", no_argument
, NULL
, OPTION_EL
},
8352 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8353 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8354 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8355 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8356 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8357 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8358 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8359 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8360 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8361 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8362 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8363 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8364 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8365 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8366 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8367 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8368 /* start-sanitize-r5900 */
8369 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8370 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8371 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8372 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8373 /* end-sanitize-r5900 */
8374 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8375 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8376 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8377 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8379 /* start-sanitize-tx19 */
8380 {"m1900", no_argument
, NULL
, OPTION_M3900
},
8381 {"no-m1900", no_argument
, NULL
, OPTION_NO_M3900
},
8382 /* end-sanitize-tx19 */
8384 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8385 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8386 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8387 #define OPTION_32 (OPTION_MD_BASE + 20)
8388 #define OPTION_64 (OPTION_MD_BASE + 21)
8390 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8391 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8392 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8393 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8394 {"32", no_argument
, NULL
, OPTION_32
},
8395 {"64", no_argument
, NULL
, OPTION_64
},
8398 {NULL
, no_argument
, NULL
, 0}
8400 size_t md_longopts_size
= sizeof(md_longopts
);
8403 md_parse_option (c
, arg
)
8418 target_big_endian
= 1;
8422 target_big_endian
= 0;
8426 if (arg
&& arg
[1] == '0')
8436 mips_debug
= atoi (arg
);
8437 /* When the MIPS assembler sees -g or -g2, it does not do
8438 optimizations which limit full symbolic debugging. We take
8439 that to be equivalent to -O0. */
8440 if (mips_debug
== 2)
8472 /* Identify the processor type */
8474 if (strcmp (p
, "default") == 0
8475 || strcmp (p
, "DEFAULT") == 0)
8481 /* We need to cope with the various "vr" prefixes for the 4300
8483 if (*p
== 'v' || *p
== 'V')
8489 if (*p
== 'r' || *p
== 'R')
8496 if (strcmp (p
, "10000") == 0
8497 || strcmp (p
, "10k") == 0
8498 || strcmp (p
, "10K") == 0)
8500 /* start-sanitize-tx19 */
8501 else if (strcmp (p
, "1900") == 0)
8503 /* end-sanitize-tx19 */
8507 if (strcmp (p
, "2000") == 0
8508 || strcmp (p
, "2k") == 0
8509 || strcmp (p
, "2K") == 0)
8514 if (strcmp (p
, "3000") == 0
8515 || strcmp (p
, "3k") == 0
8516 || strcmp (p
, "3K") == 0)
8518 else if (strcmp (p
, "3900") == 0)
8523 if (strcmp (p
, "4000") == 0
8524 || strcmp (p
, "4k") == 0
8525 || strcmp (p
, "4K") == 0)
8527 else if (strcmp (p
, "4100") == 0)
8533 else if (strcmp (p
, "4300") == 0)
8535 else if (strcmp (p
, "4400") == 0)
8537 else if (strcmp (p
, "4600") == 0)
8539 else if (strcmp (p
, "4650") == 0)
8545 else if (strcmp (p
, "4010") == 0)
8554 if (strcmp (p
, "5000") == 0
8555 || strcmp (p
, "5k") == 0
8556 || strcmp (p
, "5K") == 0)
8558 /* start-sanitize-r5900 */
8559 else if (strcmp (p
, "5900") == 0)
8561 /* end-sanitize-r5900 */
8565 if (strcmp (p
, "6000") == 0
8566 || strcmp (p
, "6k") == 0
8567 || strcmp (p
, "6K") == 0)
8572 if (strcmp (p
, "8000") == 0
8573 || strcmp (p
, "8k") == 0
8574 || strcmp (p
, "8K") == 0)
8579 if (strcmp (p
, "orion") == 0)
8584 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8586 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8592 as_bad ("invalid architecture -mcpu=%s", arg
);
8603 case OPTION_NO_M4650
:
8611 case OPTION_NO_M4010
:
8619 case OPTION_NO_M4100
:
8623 /* start-sanitize-r5900 */
8628 case OPTION_NO_M5900
:
8631 /* end-sanitize-r5900 */
8637 case OPTION_NO_M3900
:
8642 mips_opts
.mips16
= 1;
8643 mips_no_prev_insn (false);
8646 case OPTION_NO_MIPS16
:
8647 mips_opts
.mips16
= 0;
8648 mips_no_prev_insn (false);
8651 case OPTION_MEMBEDDED_PIC
:
8652 mips_pic
= EMBEDDED_PIC
;
8653 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8655 as_bad ("-G may not be used with embedded PIC code");
8658 g_switch_value
= 0x7fffffff;
8661 /* When generating ELF code, we permit -KPIC and -call_shared to
8662 select SVR4_PIC, and -non_shared to select no PIC. This is
8663 intended to be compatible with Irix 5. */
8664 case OPTION_CALL_SHARED
:
8665 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8667 as_bad ("-call_shared is supported only for ELF format");
8670 mips_pic
= SVR4_PIC
;
8671 if (g_switch_seen
&& g_switch_value
!= 0)
8673 as_bad ("-G may not be used with SVR4 PIC code");
8679 case OPTION_NON_SHARED
:
8680 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8682 as_bad ("-non_shared is supported only for ELF format");
8688 /* The -xgot option tells the assembler to use 32 offsets when
8689 accessing the got in SVR4_PIC mode. It is for Irix
8696 if (! USE_GLOBAL_POINTER_OPT
)
8698 as_bad ("-G is not supported for this configuration");
8701 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8703 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8707 g_switch_value
= atoi (arg
);
8711 /* The -32 and -64 options tell the assembler to output the 32
8712 bit or the 64 bit MIPS ELF format. */
8719 const char **list
, **l
;
8721 list
= bfd_target_list ();
8722 for (l
= list
; *l
!= NULL
; l
++)
8723 if (strcmp (*l
, "elf64-bigmips") == 0
8724 || strcmp (*l
, "elf64-littlemips") == 0)
8727 as_fatal ("No compiled in support for 64 bit object file format");
8741 md_show_usage (stream
)
8746 -membedded-pic generate embedded position independent code\n\
8747 -EB generate big endian output\n\
8748 -EL generate little endian output\n\
8749 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8750 -G NUM allow referencing objects up to NUM bytes\n\
8751 implicitly with the gp register [default 8]\n");
8753 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8754 -mips2, -mcpu=r6000 generate code for r6000\n\
8755 -mips3, -mcpu=r4000 generate code for r4000\n\
8756 -mips4, -mcpu=r8000 generate code for r8000\n\
8757 -mcpu=vr4300 generate code for vr4300\n\
8758 -mcpu=vr4100 generate code for vr4100\n\
8759 -m4650 permit R4650 instructions\n\
8760 -no-m4650 do not permit R4650 instructions\n\
8761 -m4010 permit R4010 instructions\n\
8762 -no-m4010 do not permit R4010 instructions\n\
8763 -m4100 permit VR4100 instructions\n\
8764 -no-m4100 do not permit VR4100 instructions\n");
8766 -mips16 generate mips16 instructions\n\
8767 -no-mips16 do not generate mips16 instructions\n");
8769 -O0 remove unneeded NOPs, do not swap branches\n\
8770 -O remove unneeded NOPs and swap branches\n\
8771 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8772 --break, --no-trap break exception on div by 0 and mult overflow\n");
8775 -KPIC, -call_shared generate SVR4 position independent code\n\
8776 -non_shared do not generate position independent code\n\
8777 -xgot assume a 32 bit GOT\n\
8778 -32 create 32 bit object file (default)\n\
8779 -64 create 64 bit object file\n");
8784 mips_init_after_args ()
8786 /* initialize opcodes */
8787 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8788 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8792 md_pcrel_from (fixP
)
8795 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8796 && fixP
->fx_addsy
!= (symbolS
*) NULL
8797 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8799 /* This makes a branch to an undefined symbol be a branch to the
8800 current location. */
8804 /* return the address of the delay slot */
8805 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8808 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8809 reloc for a cons. We could use the definition there, except that
8810 we want to handle 64 bit relocs specially. */
8813 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8816 unsigned int nbytes
;
8820 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8822 if (nbytes
== 8 && ! mips_64
)
8824 if (target_big_endian
)
8830 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8831 as_bad ("Unsupported reloc size %d", nbytes
);
8833 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8836 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8839 /* This is called before the symbol table is processed. In order to
8840 work with gcc when using mips-tfile, we must keep all local labels.
8841 However, in other cases, we want to discard them. If we were
8842 called with -g, but we didn't see any debugging information, it may
8843 mean that gcc is smuggling debugging information through to
8844 mips-tfile, in which case we must generate all local labels. */
8847 mips_frob_file_before_adjust ()
8849 #ifndef NO_ECOFF_DEBUGGING
8852 && ! ecoff_debugging_seen
)
8853 flag_keep_locals
= 1;
8857 /* Sort any unmatched HI16_S relocs so that they immediately precede
8858 the corresponding LO reloc. This is called before md_apply_fix and
8859 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8860 explicit use of the %hi modifier. */
8865 struct mips_hi_fixup
*l
;
8867 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8869 segment_info_type
*seginfo
;
8872 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8874 /* Check quickly whether the next fixup happens to be a matching
8876 if (l
->fixp
->fx_next
!= NULL
8877 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8878 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8879 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8882 /* Look through the fixups for this segment for a matching %lo.
8883 When we find one, move the %hi just in front of it. We do
8884 this in two passes. In the first pass, we try to find a
8885 unique %lo. In the second pass, we permit multiple %hi
8886 relocs for a single %lo (this is a GNU extension). */
8887 seginfo
= seg_info (l
->seg
);
8888 for (pass
= 0; pass
< 2; pass
++)
8893 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8895 /* Check whether this is a %lo fixup which matches l->fixp. */
8896 if (f
->fx_r_type
== BFD_RELOC_LO16
8897 && f
->fx_addsy
== l
->fixp
->fx_addsy
8898 && f
->fx_offset
== l
->fixp
->fx_offset
8901 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8902 || prev
->fx_addsy
!= f
->fx_addsy
8903 || prev
->fx_offset
!= f
->fx_offset
))
8907 /* Move l->fixp before f. */
8908 for (pf
= &seginfo
->fix_root
;
8910 pf
= &(*pf
)->fx_next
)
8911 assert (*pf
!= NULL
);
8913 *pf
= l
->fixp
->fx_next
;
8915 l
->fixp
->fx_next
= f
;
8917 seginfo
->fix_root
= l
->fixp
;
8919 prev
->fx_next
= l
->fixp
;
8931 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8932 "Unmatched %%hi reloc");
8937 /* When generating embedded PIC code we need to use a special
8938 relocation to represent the difference of two symbols in the .text
8939 section (switch tables use a difference of this sort). See
8940 include/coff/mips.h for details. This macro checks whether this
8941 fixup requires the special reloc. */
8942 #define SWITCH_TABLE(fixp) \
8943 ((fixp)->fx_r_type == BFD_RELOC_32 \
8944 && (fixp)->fx_addsy != NULL \
8945 && (fixp)->fx_subsy != NULL \
8946 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8947 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8949 /* When generating embedded PIC code we must keep all PC relative
8950 relocations, in case the linker has to relax a call. We also need
8951 to keep relocations for switch table entries. */
8955 mips_force_relocation (fixp
)
8958 return (mips_pic
== EMBEDDED_PIC
8960 || SWITCH_TABLE (fixp
)
8961 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8962 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8965 /* Apply a fixup to the object file. */
8968 md_apply_fix (fixP
, valueP
)
8975 assert (fixP
->fx_size
== 4
8976 || fixP
->fx_r_type
== BFD_RELOC_16
8977 || fixP
->fx_r_type
== BFD_RELOC_64
);
8981 /* If we aren't adjusting this fixup to be against the section
8982 symbol, we need to adjust the value. */
8984 if (fixP
->fx_addsy
!= NULL
8985 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8986 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8988 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8989 if (value
!= 0 && ! fixP
->fx_pcrel
)
8991 /* In this case, the bfd_install_relocation routine will
8992 incorrectly add the symbol value back in. We just want
8993 the addend to appear in the object file. */
8994 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8999 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9001 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9004 switch (fixP
->fx_r_type
)
9006 case BFD_RELOC_MIPS_JMP
:
9007 case BFD_RELOC_HI16
:
9008 case BFD_RELOC_HI16_S
:
9009 case BFD_RELOC_MIPS_GPREL
:
9010 case BFD_RELOC_MIPS_LITERAL
:
9011 case BFD_RELOC_MIPS_CALL16
:
9012 case BFD_RELOC_MIPS_GOT16
:
9013 case BFD_RELOC_MIPS_GPREL32
:
9014 case BFD_RELOC_MIPS_GOT_HI16
:
9015 case BFD_RELOC_MIPS_GOT_LO16
:
9016 case BFD_RELOC_MIPS_CALL_HI16
:
9017 case BFD_RELOC_MIPS_CALL_LO16
:
9018 case BFD_RELOC_MIPS16_GPREL
:
9020 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9021 "Invalid PC relative reloc");
9022 /* Nothing needed to do. The value comes from the reloc entry */
9025 case BFD_RELOC_MIPS16_JMP
:
9026 /* We currently always generate a reloc against a symbol, which
9027 means that we don't want an addend even if the symbol is
9029 fixP
->fx_addnumber
= 0;
9032 case BFD_RELOC_PCREL_HI16_S
:
9033 /* The addend for this is tricky if it is internal, so we just
9034 do everything here rather than in bfd_install_relocation. */
9035 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9037 /* For an external symbol adjust by the address to make it
9038 pcrel_offset. We use the address of the RELLO reloc
9039 which follows this one. */
9040 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9041 + fixP
->fx_next
->fx_where
);
9046 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9047 if (target_big_endian
)
9049 md_number_to_chars (buf
, value
, 2);
9052 case BFD_RELOC_PCREL_LO16
:
9053 /* The addend for this is tricky if it is internal, so we just
9054 do everything here rather than in bfd_install_relocation. */
9055 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
9056 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9057 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9058 if (target_big_endian
)
9060 md_number_to_chars (buf
, value
, 2);
9064 /* This is handled like BFD_RELOC_32, but we output a sign
9065 extended value if we are only 32 bits. */
9067 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9069 if (8 <= sizeof (valueT
))
9070 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9077 w1
= w2
= fixP
->fx_where
;
9078 if (target_big_endian
)
9082 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9083 if ((value
& 0x80000000) != 0)
9087 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9093 /* If we are deleting this reloc entry, we must fill in the
9094 value now. This can happen if we have a .word which is not
9095 resolved when it appears but is later defined. We also need
9096 to fill in the value if this is an embedded PIC switch table
9099 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9100 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9105 /* If we are deleting this reloc entry, we must fill in the
9107 assert (fixP
->fx_size
== 2);
9109 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9113 case BFD_RELOC_LO16
:
9114 /* When handling an embedded PIC switch statement, we can wind
9115 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9118 if (value
< -0x8000 || value
> 0x7fff)
9119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9120 "relocation overflow");
9121 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9122 if (target_big_endian
)
9124 md_number_to_chars (buf
, value
, 2);
9128 case BFD_RELOC_16_PCREL_S2
:
9130 * We need to save the bits in the instruction since fixup_segment()
9131 * might be deleting the relocation entry (i.e., a branch within
9132 * the current segment).
9134 if ((value
& 0x3) != 0)
9135 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9136 "Branch to odd address (%lx)", value
);
9139 /* update old instruction data */
9140 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9141 if (target_big_endian
)
9142 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9144 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9146 if (value
>= -0x8000 && value
< 0x8000)
9147 insn
|= value
& 0xffff;
9150 /* The branch offset is too large. If this is an
9151 unconditional branch, and we are not generating PIC code,
9152 we can convert it to an absolute jump instruction. */
9153 if (mips_pic
== NO_PIC
9155 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9156 && (fixP
->fx_frag
->fr_address
9157 < text_section
->vma
+ text_section
->_raw_size
)
9158 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9159 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9160 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9162 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9163 insn
= 0x0c000000; /* jal */
9165 insn
= 0x08000000; /* j */
9166 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9168 fixP
->fx_addsy
= section_symbol (text_section
);
9169 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9173 /* FIXME. It would be possible in principle to handle
9174 conditional branches which overflow. They could be
9175 transformed into a branch around a jump. This would
9176 require setting up variant frags for each different
9177 branch type. The native MIPS assembler attempts to
9178 handle these cases, but it appears to do it
9180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9181 "Branch out of range");
9185 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9200 const struct mips_opcode
*p
;
9201 int treg
, sreg
, dreg
, shamt
;
9206 for (i
= 0; i
< NUMOPCODES
; ++i
)
9208 p
= &mips_opcodes
[i
];
9209 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9211 printf ("%08lx %s\t", oc
, p
->name
);
9212 treg
= (oc
>> 16) & 0x1f;
9213 sreg
= (oc
>> 21) & 0x1f;
9214 dreg
= (oc
>> 11) & 0x1f;
9215 shamt
= (oc
>> 6) & 0x1f;
9217 for (args
= p
->args
;; ++args
)
9228 printf ("%c", *args
);
9232 assert (treg
== sreg
);
9233 printf ("$%d,$%d", treg
, sreg
);
9238 printf ("$%d", dreg
);
9243 printf ("$%d", treg
);
9247 printf ("0x%x", treg
);
9252 printf ("$%d", sreg
);
9256 printf ("0x%08lx", oc
& 0x1ffffff);
9268 printf ("$%d", shamt
);
9279 printf ("%08lx UNDEFINED\n", oc
);
9290 name
= input_line_pointer
;
9291 c
= get_symbol_end ();
9292 p
= (symbolS
*) symbol_find_or_make (name
);
9293 *input_line_pointer
= c
;
9297 /* Align the current frag to a given power of two. The MIPS assembler
9298 also automatically adjusts any preceding label. */
9301 mips_align (to
, fill
, label
)
9306 mips_emit_delays (false);
9307 frag_align (to
, fill
, 0);
9308 record_alignment (now_seg
, to
);
9311 assert (S_GET_SEGMENT (label
) == now_seg
);
9312 label
->sy_frag
= frag_now
;
9313 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9317 /* Align to a given power of two. .align 0 turns off the automatic
9318 alignment used by the data creating pseudo-ops. */
9325 register long temp_fill
;
9326 long max_alignment
= 15;
9330 o Note that the assembler pulls down any immediately preceeding label
9331 to the aligned address.
9332 o It's not documented but auto alignment is reinstated by
9333 a .align pseudo instruction.
9334 o Note also that after auto alignment is turned off the mips assembler
9335 issues an error on attempt to assemble an improperly aligned data item.
9340 temp
= get_absolute_expression ();
9341 if (temp
> max_alignment
)
9342 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9345 as_warn ("Alignment negative: 0 assumed.");
9348 if (*input_line_pointer
== ',')
9350 input_line_pointer
++;
9351 temp_fill
= get_absolute_expression ();
9358 mips_align (temp
, (int) temp_fill
,
9359 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9366 demand_empty_rest_of_line ();
9370 mips_flush_pending_output ()
9372 mips_emit_delays (false);
9373 mips_clear_insn_labels ();
9382 /* When generating embedded PIC code, we only use the .text, .lit8,
9383 .sdata and .sbss sections. We change the .data and .rdata
9384 pseudo-ops to use .sdata. */
9385 if (mips_pic
== EMBEDDED_PIC
9386 && (sec
== 'd' || sec
== 'r'))
9390 /* The ELF backend needs to know that we are changing sections, so
9391 that .previous works correctly. We could do something like check
9392 for a obj_section_change_hook macro, but that might be confusing
9393 as it would not be appropriate to use it in the section changing
9394 functions in read.c, since obj-elf.c intercepts those. FIXME:
9395 This should be cleaner, somehow. */
9396 obj_elf_section_change_hook ();
9399 mips_emit_delays (false);
9409 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9410 demand_empty_rest_of_line ();
9414 if (USE_GLOBAL_POINTER_OPT
)
9416 seg
= subseg_new (RDATA_SECTION_NAME
,
9417 (subsegT
) get_absolute_expression ());
9418 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9420 bfd_set_section_flags (stdoutput
, seg
,
9426 if (strcmp (TARGET_OS
, "elf") != 0)
9427 bfd_set_section_alignment (stdoutput
, seg
, 4);
9429 demand_empty_rest_of_line ();
9433 as_bad ("No read only data section in this object file format");
9434 demand_empty_rest_of_line ();
9440 if (USE_GLOBAL_POINTER_OPT
)
9442 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9443 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9445 bfd_set_section_flags (stdoutput
, seg
,
9446 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9448 if (strcmp (TARGET_OS
, "elf") != 0)
9449 bfd_set_section_alignment (stdoutput
, seg
, 4);
9451 demand_empty_rest_of_line ();
9456 as_bad ("Global pointers not supported; recompile -G 0");
9457 demand_empty_rest_of_line ();
9466 mips_enable_auto_align ()
9477 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9478 mips_emit_delays (false);
9479 if (log_size
> 0 && auto_align
)
9480 mips_align (log_size
, 0, label
);
9481 mips_clear_insn_labels ();
9482 cons (1 << log_size
);
9491 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9493 mips_emit_delays (false);
9497 mips_align (3, 0, label
);
9499 mips_align (2, 0, label
);
9501 mips_clear_insn_labels ();
9506 /* Handle .globl. We need to override it because on Irix 5 you are
9509 where foo is an undefined symbol, to mean that foo should be
9510 considered to be the address of a function. */
9521 name
= input_line_pointer
;
9522 c
= get_symbol_end ();
9523 symbolP
= symbol_find_or_make (name
);
9524 *input_line_pointer
= c
;
9527 /* On Irix 5, every global symbol that is not explicitly labelled as
9528 being a function is apparently labelled as being an object. */
9531 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9536 secname
= input_line_pointer
;
9537 c
= get_symbol_end ();
9538 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9540 as_bad ("%s: no such section", secname
);
9541 *input_line_pointer
= c
;
9543 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9544 flag
= BSF_FUNCTION
;
9547 symbolP
->bsym
->flags
|= flag
;
9549 S_SET_EXTERNAL (symbolP
);
9550 demand_empty_rest_of_line ();
9560 opt
= input_line_pointer
;
9561 c
= get_symbol_end ();
9565 /* FIXME: What does this mean? */
9567 else if (strncmp (opt
, "pic", 3) == 0)
9575 mips_pic
= SVR4_PIC
;
9577 as_bad (".option pic%d not supported", i
);
9579 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9581 if (g_switch_seen
&& g_switch_value
!= 0)
9582 as_warn ("-G may not be used with SVR4 PIC code");
9584 bfd_set_gp_size (stdoutput
, 0);
9588 as_warn ("Unrecognized option \"%s\"", opt
);
9590 *input_line_pointer
= c
;
9591 demand_empty_rest_of_line ();
9594 /* This structure is used to hold a stack of .set values. */
9596 struct mips_option_stack
9598 struct mips_option_stack
*next
;
9599 struct mips_set_options options
;
9602 static struct mips_option_stack
*mips_opts_stack
;
9604 /* Handle the .set pseudo-op. */
9610 char *name
= input_line_pointer
, ch
;
9612 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9613 input_line_pointer
++;
9614 ch
= *input_line_pointer
;
9615 *input_line_pointer
= '\0';
9617 if (strcmp (name
, "reorder") == 0)
9619 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
9621 /* If we still have pending nops, we can discard them. The
9622 usual nop handling will insert any that are still
9624 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9625 * (mips_opts
.mips16
? 2 : 4));
9626 prev_nop_frag
= NULL
;
9628 mips_opts
.noreorder
= 0;
9630 else if (strcmp (name
, "noreorder") == 0)
9632 mips_emit_delays (true);
9633 mips_opts
.noreorder
= 1;
9634 mips_any_noreorder
= 1;
9636 else if (strcmp (name
, "at") == 0)
9640 else if (strcmp (name
, "noat") == 0)
9644 else if (strcmp (name
, "macro") == 0)
9646 mips_opts
.warn_about_macros
= 0;
9648 else if (strcmp (name
, "nomacro") == 0)
9650 if (mips_opts
.noreorder
== 0)
9651 as_bad ("`noreorder' must be set before `nomacro'");
9652 mips_opts
.warn_about_macros
= 1;
9654 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9656 mips_opts
.nomove
= 0;
9658 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9660 mips_opts
.nomove
= 1;
9662 else if (strcmp (name
, "bopt") == 0)
9664 mips_opts
.nobopt
= 0;
9666 else if (strcmp (name
, "nobopt") == 0)
9668 mips_opts
.nobopt
= 1;
9670 else if (strcmp (name
, "mips16") == 0
9671 || strcmp (name
, "MIPS-16") == 0)
9672 mips_opts
.mips16
= 1;
9673 else if (strcmp (name
, "nomips16") == 0
9674 || strcmp (name
, "noMIPS-16") == 0)
9675 mips_opts
.mips16
= 0;
9676 else if (strncmp (name
, "mips", 4) == 0)
9680 /* Permit the user to change the ISA on the fly. Needless to
9681 say, misuse can cause serious problems. */
9682 isa
= atoi (name
+ 4);
9684 mips_opts
.isa
= file_mips_isa
;
9685 else if (isa
< 1 || isa
> 4)
9686 as_bad ("unknown ISA level");
9688 mips_opts
.isa
= isa
;
9690 else if (strcmp (name
, "autoextend") == 0)
9691 mips_opts
.noautoextend
= 0;
9692 else if (strcmp (name
, "noautoextend") == 0)
9693 mips_opts
.noautoextend
= 1;
9694 else if (strcmp (name
, "push") == 0)
9696 struct mips_option_stack
*s
;
9698 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
9699 s
->next
= mips_opts_stack
;
9700 s
->options
= mips_opts
;
9701 mips_opts_stack
= s
;
9703 else if (strcmp (name
, "pop") == 0)
9705 struct mips_option_stack
*s
;
9707 s
= mips_opts_stack
;
9709 as_bad (".set pop with no .set push");
9712 /* If we're changing the reorder mode we need to handle
9713 delay slots correctly. */
9714 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
9715 mips_emit_delays (true);
9716 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
9718 if (prev_nop_frag
!= NULL
)
9720 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
9721 * (mips_opts
.mips16
? 2 : 4));
9722 prev_nop_frag
= NULL
;
9726 mips_opts
= s
->options
;
9727 mips_opts_stack
= s
->next
;
9733 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9735 *input_line_pointer
= ch
;
9736 demand_empty_rest_of_line ();
9739 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9740 .option pic2. It means to generate SVR4 PIC calls. */
9746 mips_pic
= SVR4_PIC
;
9747 if (USE_GLOBAL_POINTER_OPT
)
9749 if (g_switch_seen
&& g_switch_value
!= 0)
9750 as_warn ("-G may not be used with SVR4 PIC code");
9753 bfd_set_gp_size (stdoutput
, 0);
9754 demand_empty_rest_of_line ();
9757 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9758 PIC code. It sets the $gp register for the function based on the
9759 function address, which is in the register named in the argument.
9760 This uses a relocation against _gp_disp, which is handled specially
9761 by the linker. The result is:
9762 lui $gp,%hi(_gp_disp)
9763 addiu $gp,$gp,%lo(_gp_disp)
9764 addu $gp,$gp,.cpload argument
9765 The .cpload argument is normally $25 == $t9. */
9774 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9775 if (mips_pic
!= SVR4_PIC
)
9781 /* .cpload should be a in .set noreorder section. */
9782 if (mips_opts
.noreorder
== 0)
9783 as_warn (".cpload not in noreorder section");
9786 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9787 ex
.X_op_symbol
= NULL
;
9788 ex
.X_add_number
= 0;
9790 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9791 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9793 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9794 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9795 (int) BFD_RELOC_LO16
);
9797 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9798 GP
, GP
, tc_get_register (0));
9800 demand_empty_rest_of_line ();
9803 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9804 offset from $sp. The offset is remembered, and after making a PIC
9805 call $gp is restored from that location. */
9808 s_cprestore (ignore
)
9814 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9815 if (mips_pic
!= SVR4_PIC
)
9821 mips_cprestore_offset
= get_absolute_expression ();
9823 ex
.X_op
= O_constant
;
9824 ex
.X_add_symbol
= NULL
;
9825 ex
.X_op_symbol
= NULL
;
9826 ex
.X_add_number
= mips_cprestore_offset
;
9828 macro_build ((char *) NULL
, &icnt
, &ex
,
9829 mips_opts
.isa
< 3 ? "sw" : "sd",
9830 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9832 demand_empty_rest_of_line ();
9835 /* Handle the .gpword pseudo-op. This is used when generating PIC
9836 code. It generates a 32 bit GP relative reloc. */
9846 /* When not generating PIC code, this is treated as .word. */
9847 if (mips_pic
!= SVR4_PIC
)
9853 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9854 mips_emit_delays (true);
9856 mips_align (2, 0, label
);
9857 mips_clear_insn_labels ();
9861 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9863 as_bad ("Unsupported use of .gpword");
9864 ignore_rest_of_line ();
9868 md_number_to_chars (p
, (valueT
) 0, 4);
9869 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9870 BFD_RELOC_MIPS_GPREL32
);
9872 demand_empty_rest_of_line ();
9875 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9876 tables in SVR4 PIC code. */
9885 /* This is ignored when not generating SVR4 PIC code. */
9886 if (mips_pic
!= SVR4_PIC
)
9892 /* Add $gp to the register named as an argument. */
9893 reg
= tc_get_register (0);
9894 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9895 mips_opts
.isa
< 3 ? "addu" : "daddu",
9896 "d,v,t", reg
, reg
, GP
);
9898 demand_empty_rest_of_line ();
9901 /* Handle the .insn pseudo-op. This marks instruction labels in
9902 mips16 mode. This permits the linker to handle them specially,
9903 such as generating jalx instructions when needed. We also make
9904 them odd for the duration of the assembly, in order to generate the
9905 right sort of code. We will make them even in the adjust_symtab
9906 routine, while leaving them marked. This is convenient for the
9907 debugger and the disassembler. The linker knows to make them odd
9914 if (mips_opts
.mips16
)
9915 mips16_mark_labels ();
9917 demand_empty_rest_of_line ();
9920 /* Handle a .stabn directive. We need these in order to mark a label
9921 as being a mips16 text label correctly. Sometimes the compiler
9922 will emit a label, followed by a .stabn, and then switch sections.
9923 If the label and .stabn are in mips16 mode, then the label is
9924 really a mips16 text label. */
9930 if (type
== 'n' && mips_opts
.mips16
)
9931 mips16_mark_labels ();
9936 /* Parse a register string into a number. Called from the ECOFF code
9937 to parse .frame. The argument is non-zero if this is the frame
9938 register, so that we can record it in mips_frame_reg. */
9941 tc_get_register (frame
)
9947 if (*input_line_pointer
++ != '$')
9949 as_warn ("expected `$'");
9952 else if (isdigit ((unsigned char) *input_line_pointer
))
9954 reg
= get_absolute_expression ();
9955 if (reg
< 0 || reg
>= 32)
9957 as_warn ("Bad register number");
9963 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9965 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9967 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9969 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9973 as_warn ("Unrecognized register name");
9976 input_line_pointer
+= 2;
9979 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9984 md_section_align (seg
, addr
)
9988 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9991 /* We don't need to align ELF sections to the full alignment.
9992 However, Irix 5 may prefer that we align them at least to a 16
9993 byte boundary. We don't bother to align the sections if we are
9994 targeted for an embedded system. */
9995 if (strcmp (TARGET_OS
, "elf") == 0)
10001 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10004 /* Utility routine, called from above as well. If called while the
10005 input file is still being read, it's only an approximation. (For
10006 example, a symbol may later become defined which appeared to be
10007 undefined earlier.) */
10010 nopic_need_relax (sym
, before_relaxing
)
10012 int before_relaxing
;
10017 if (USE_GLOBAL_POINTER_OPT
)
10019 const char *symname
;
10022 /* Find out whether this symbol can be referenced off the GP
10023 register. It can be if it is smaller than the -G size or if
10024 it is in the .sdata or .sbss section. Certain symbols can
10025 not be referenced off the GP, although it appears as though
10027 symname
= S_GET_NAME (sym
);
10028 if (symname
!= (const char *) NULL
10029 && (strcmp (symname
, "eprol") == 0
10030 || strcmp (symname
, "etext") == 0
10031 || strcmp (symname
, "_gp") == 0
10032 || strcmp (symname
, "edata") == 0
10033 || strcmp (symname
, "_fbss") == 0
10034 || strcmp (symname
, "_fdata") == 0
10035 || strcmp (symname
, "_ftext") == 0
10036 || strcmp (symname
, "end") == 0
10037 || strcmp (symname
, "_gp_disp") == 0))
10039 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10041 #ifndef NO_ECOFF_DEBUGGING
10042 || (sym
->ecoff_extern_size
!= 0
10043 && sym
->ecoff_extern_size
<= g_switch_value
)
10045 /* We must defer this decision until after the whole
10046 file has been read, since there might be a .extern
10047 after the first use of this symbol. */
10048 || (before_relaxing
10049 #ifndef NO_ECOFF_DEBUGGING
10050 && sym
->ecoff_extern_size
== 0
10052 && S_GET_VALUE (sym
) == 0)
10053 || (S_GET_VALUE (sym
) != 0
10054 && S_GET_VALUE (sym
) <= g_switch_value
)))
10058 const char *segname
;
10060 segname
= segment_name (S_GET_SEGMENT (sym
));
10061 assert (strcmp (segname
, ".lit8") != 0
10062 && strcmp (segname
, ".lit4") != 0);
10063 change
= (strcmp (segname
, ".sdata") != 0
10064 && strcmp (segname
, ".sbss") != 0);
10069 /* We are not optimizing for the GP register. */
10073 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10074 extended opcode. SEC is the section the frag is in. */
10077 mips16_extended_frag (fragp
, sec
, stretch
)
10083 register const struct mips16_immed_operand
*op
;
10085 int mintiny
, maxtiny
;
10088 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10090 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10093 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10094 op
= mips16_immed_operands
;
10095 while (op
->type
!= type
)
10098 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10103 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10106 maxtiny
= 1 << op
->nbits
;
10111 maxtiny
= (1 << op
->nbits
) - 1;
10116 mintiny
= - (1 << (op
->nbits
- 1));
10117 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10120 /* We can't call S_GET_VALUE here, because we don't want to lock in
10121 a particular frag address. */
10122 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
10124 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
10125 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10126 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10128 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
10129 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
10132 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
10133 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
10134 + fragp
->fr_symbol
->sy_value
.X_add_number
10135 + fragp
->fr_symbol
->sy_frag
->fr_address
);
10136 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
10145 /* We won't have the section when we are called from
10146 mips_relax_frag. However, we will always have been called
10147 from md_estimate_size_before_relax first. If this is a
10148 branch to a different section, we mark it as such. If SEC is
10149 NULL, and the frag is not marked, then it must be a branch to
10150 the same section. */
10153 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10160 fragp
->fr_subtype
=
10161 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10163 /* FIXME: We should support this, and let the linker
10164 catch branches and loads that are out of range. */
10165 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10166 "unsupported PC relative reference to different section");
10172 /* In this case, we know for sure that the symbol fragment is in
10173 the same section. If the fr_address of the symbol fragment
10174 is greater then the address of this fragment we want to add
10175 in STRETCH in order to get a better estimate of the address.
10176 This particularly matters because of the shift bits. */
10178 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
10182 /* Adjust stretch for any alignment frag. Note that if have
10183 been expanding the earlier code, the symbol may be
10184 defined in what appears to be an earlier frag. FIXME:
10185 This doesn't handle the fr_subtype field, which specifies
10186 a maximum number of bytes to skip when doing an
10189 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
10192 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10195 stretch
= - ((- stretch
)
10196 & ~ ((1 << (int) f
->fr_offset
) - 1));
10198 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10207 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10209 /* The base address rules are complicated. The base address of
10210 a branch is the following instruction. The base address of a
10211 PC relative load or add is the instruction itself, but if it
10212 is in a delay slot (in which case it can not be extended) use
10213 the address of the instruction whose delay slot it is in. */
10214 if (type
== 'p' || type
== 'q')
10218 /* If we are currently assuming that this frag should be
10219 extended, then, the current address is two bytes
10221 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10224 /* Ignore the low bit in the target, since it will be set
10225 for a text label. */
10226 if ((val
& 1) != 0)
10229 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10231 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10234 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10236 /* Branch offsets have an implicit 0 in the lowest bit. */
10237 if (type
== 'p' || type
== 'q')
10240 /* If any of the shifted bits are set, we must use an extended
10241 opcode. If the address depends on the size of this
10242 instruction, this can lead to a loop, so we arrange to always
10243 use an extended opcode. We only check this when we are in
10244 the main relaxation loop, when SEC is NULL. */
10245 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10247 fragp
->fr_subtype
=
10248 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10252 /* If we are about to mark a frag as extended because the value
10253 is precisely maxtiny + 1, then there is a chance of an
10254 infinite loop as in the following code:
10259 In this case when the la is extended, foo is 0x3fc bytes
10260 away, so the la can be shrunk, but then foo is 0x400 away, so
10261 the la must be extended. To avoid this loop, we mark the
10262 frag as extended if it was small, and is about to become
10263 extended with a value of maxtiny + 1. */
10264 if (val
== ((maxtiny
+ 1) << op
->shift
)
10265 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10268 fragp
->fr_subtype
=
10269 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10273 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10274 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
10276 if ((val
& ((1 << op
->shift
) - 1)) != 0
10277 || val
< (mintiny
<< op
->shift
)
10278 || val
> (maxtiny
<< op
->shift
))
10284 /* Estimate the size of a frag before relaxing. Unless this is the
10285 mips16, we are not really relaxing here, and the final size is
10286 encoded in the subtype information. For the mips16, we have to
10287 decide whether we are using an extended opcode or not. */
10291 md_estimate_size_before_relax (fragp
, segtype
)
10297 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10299 if (mips16_extended_frag (fragp
, segtype
, 0))
10301 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10306 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10311 if (mips_pic
== NO_PIC
)
10313 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
10315 else if (mips_pic
== SVR4_PIC
)
10320 sym
= fragp
->fr_symbol
;
10322 /* Handle the case of a symbol equated to another symbol. */
10323 while (sym
->sy_value
.X_op
== O_symbol
10324 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
10328 /* It's possible to get a loop here in a badly written
10330 n
= sym
->sy_value
.X_add_symbol
;
10336 symsec
= S_GET_SEGMENT (sym
);
10338 /* This must duplicate the test in adjust_reloc_syms. */
10339 change
= (symsec
!= &bfd_und_section
10340 && symsec
!= &bfd_abs_section
10341 && ! bfd_is_com_section (symsec
));
10348 /* Record the offset to the first reloc in the fr_opcode field.
10349 This lets md_convert_frag and tc_gen_reloc know that the code
10350 must be expanded. */
10351 fragp
->fr_opcode
= (fragp
->fr_literal
10353 - RELAX_OLD (fragp
->fr_subtype
)
10354 + RELAX_RELOC1 (fragp
->fr_subtype
));
10355 /* FIXME: This really needs as_warn_where. */
10356 if (RELAX_WARN (fragp
->fr_subtype
))
10357 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
10363 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
10366 /* This is called to see whether a reloc against a defined symbol
10367 should be converted into a reloc against a section. Don't adjust
10368 MIPS16 jump relocations, so we don't have to worry about the format
10369 of the offset in the .o file. Don't adjust relocations against
10370 mips16 symbols, so that the linker can find them if it needs to set
10374 mips_fix_adjustable (fixp
)
10377 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
10379 if (fixp
->fx_addsy
== NULL
)
10382 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10383 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10384 && fixp
->fx_subsy
== NULL
)
10390 /* Translate internal representation of relocation info to BFD target
10394 tc_gen_reloc (section
, fixp
)
10398 static arelent
*retval
[4];
10400 bfd_reloc_code_real_type code
;
10402 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10405 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10406 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10408 if (mips_pic
== EMBEDDED_PIC
10409 && SWITCH_TABLE (fixp
))
10411 /* For a switch table entry we use a special reloc. The addend
10412 is actually the difference between the reloc address and the
10414 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10415 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10416 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10417 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10419 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10421 /* We use a special addend for an internal RELLO reloc. */
10422 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10423 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10425 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10427 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10429 assert (fixp
->fx_next
!= NULL
10430 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10431 /* We use a special addend for an internal RELHI reloc. The
10432 reloc is relative to the RELLO; adjust the addend
10434 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10435 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10436 + fixp
->fx_next
->fx_where
10437 - S_GET_VALUE (fixp
->fx_subsy
));
10439 reloc
->addend
= (fixp
->fx_addnumber
10440 + fixp
->fx_next
->fx_frag
->fr_address
10441 + fixp
->fx_next
->fx_where
);
10443 else if (fixp
->fx_pcrel
== 0)
10444 reloc
->addend
= fixp
->fx_addnumber
;
10447 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10448 /* A gruesome hack which is a result of the gruesome gas reloc
10450 reloc
->addend
= reloc
->address
;
10452 reloc
->addend
= -reloc
->address
;
10455 /* If this is a variant frag, we may need to adjust the existing
10456 reloc and generate a new one. */
10457 if (fixp
->fx_frag
->fr_opcode
!= NULL
10458 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10459 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10460 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10461 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10462 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10463 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10464 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10468 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10470 /* If this is not the last reloc in this frag, then we have two
10471 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10472 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10473 the second one handle all of them. */
10474 if (fixp
->fx_next
!= NULL
10475 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10477 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10478 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10479 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10480 && (fixp
->fx_next
->fx_r_type
10481 == BFD_RELOC_MIPS_GOT_LO16
))
10482 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10483 && (fixp
->fx_next
->fx_r_type
10484 == BFD_RELOC_MIPS_CALL_LO16
)));
10489 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10490 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10491 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10493 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10494 reloc2
->address
= (reloc
->address
10495 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10496 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10497 reloc2
->addend
= fixp
->fx_addnumber
;
10498 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10499 assert (reloc2
->howto
!= NULL
);
10501 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10505 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10508 reloc3
->address
+= 4;
10511 if (mips_pic
== NO_PIC
)
10513 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10514 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10516 else if (mips_pic
== SVR4_PIC
)
10518 switch (fixp
->fx_r_type
)
10522 case BFD_RELOC_MIPS_GOT16
:
10524 case BFD_RELOC_MIPS_CALL16
:
10525 case BFD_RELOC_MIPS_GOT_LO16
:
10526 case BFD_RELOC_MIPS_CALL_LO16
:
10527 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10535 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10536 fixup_segment converted a non-PC relative reloc into a PC
10537 relative reloc. In such a case, we need to convert the reloc
10539 code
= fixp
->fx_r_type
;
10540 if (fixp
->fx_pcrel
)
10545 code
= BFD_RELOC_8_PCREL
;
10548 code
= BFD_RELOC_16_PCREL
;
10551 code
= BFD_RELOC_32_PCREL
;
10554 code
= BFD_RELOC_64_PCREL
;
10556 case BFD_RELOC_8_PCREL
:
10557 case BFD_RELOC_16_PCREL
:
10558 case BFD_RELOC_32_PCREL
:
10559 case BFD_RELOC_64_PCREL
:
10560 case BFD_RELOC_16_PCREL_S2
:
10561 case BFD_RELOC_PCREL_HI16_S
:
10562 case BFD_RELOC_PCREL_LO16
:
10565 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10566 "Cannot make %s relocation PC relative",
10567 bfd_get_reloc_code_name (code
));
10571 /* To support a PC relative reloc when generating embedded PIC code
10572 for ECOFF, we use a Cygnus extension. We check for that here to
10573 make sure that we don't let such a reloc escape normally. */
10574 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10575 && code
== BFD_RELOC_16_PCREL_S2
10576 && mips_pic
!= EMBEDDED_PIC
)
10577 reloc
->howto
= NULL
;
10579 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10581 if (reloc
->howto
== NULL
)
10583 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10584 "Can not represent %s relocation in this object file format",
10585 bfd_get_reloc_code_name (code
));
10592 /* Relax a machine dependent frag. This returns the amount by which
10593 the current size of the frag should change. */
10596 mips_relax_frag (fragp
, stretch
)
10600 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10603 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10605 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10607 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10612 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10614 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10621 /* Convert a machine dependent frag. */
10624 md_convert_frag (abfd
, asec
, fragp
)
10632 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10635 register const struct mips16_immed_operand
*op
;
10636 boolean small
, ext
;
10639 unsigned long insn
;
10640 boolean use_extend
;
10641 unsigned short extend
;
10643 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10644 op
= mips16_immed_operands
;
10645 while (op
->type
!= type
)
10648 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10659 resolve_symbol_value (fragp
->fr_symbol
, 1);
10660 val
= S_GET_VALUE (fragp
->fr_symbol
);
10665 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10667 /* The rules for the base address of a PC relative reloc are
10668 complicated; see mips16_extended_frag. */
10669 if (type
== 'p' || type
== 'q')
10674 /* Ignore the low bit in the target, since it will be
10675 set for a text label. */
10676 if ((val
& 1) != 0)
10679 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10681 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10684 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10687 /* Make sure the section winds up with the alignment we have
10690 record_alignment (asec
, op
->shift
);
10694 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10695 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10696 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10697 "extended instruction in delay slot");
10699 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10701 if (target_big_endian
)
10702 insn
= bfd_getb16 (buf
);
10704 insn
= bfd_getl16 (buf
);
10706 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10707 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10708 small
, ext
, &insn
, &use_extend
, &extend
);
10712 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10713 fragp
->fr_fix
+= 2;
10717 md_number_to_chars (buf
, insn
, 2);
10718 fragp
->fr_fix
+= 2;
10723 if (fragp
->fr_opcode
== NULL
)
10726 old
= RELAX_OLD (fragp
->fr_subtype
);
10727 new = RELAX_NEW (fragp
->fr_subtype
);
10728 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10731 memcpy (fixptr
- old
, fixptr
, new);
10733 fragp
->fr_fix
+= new - old
;
10739 /* This function is called after the relocs have been generated.
10740 We've been storing mips16 text labels as odd. Here we convert them
10741 back to even for the convenience of the debugger. */
10744 mips_frob_file_after_relocs ()
10747 unsigned int count
, i
;
10749 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10752 syms
= bfd_get_outsymbols (stdoutput
);
10753 count
= bfd_get_symcount (stdoutput
);
10754 for (i
= 0; i
< count
; i
++, syms
++)
10756 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10757 && ((*syms
)->value
& 1) != 0)
10759 (*syms
)->value
&= ~1;
10760 /* If the symbol has an odd size, it was probably computed
10761 incorrectly, so adjust that as well. */
10762 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10763 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10770 /* This function is called whenever a label is defined. It is used
10771 when handling branch delays; if a branch has a label, we assume we
10772 can not move it. */
10775 mips_define_label (sym
)
10778 struct insn_label_list
*l
;
10780 if (free_insn_labels
== NULL
)
10781 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10784 l
= free_insn_labels
;
10785 free_insn_labels
= l
->next
;
10789 l
->next
= insn_labels
;
10793 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10795 /* Some special processing for a MIPS ELF file. */
10798 mips_elf_final_processing ()
10800 /* Write out the register information. */
10805 s
.ri_gprmask
= mips_gprmask
;
10806 s
.ri_cprmask
[0] = mips_cprmask
[0];
10807 s
.ri_cprmask
[1] = mips_cprmask
[1];
10808 s
.ri_cprmask
[2] = mips_cprmask
[2];
10809 s
.ri_cprmask
[3] = mips_cprmask
[3];
10810 /* The gp_value field is set by the MIPS ELF backend. */
10812 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10813 ((Elf32_External_RegInfo
*)
10814 mips_regmask_frag
));
10818 Elf64_Internal_RegInfo s
;
10820 s
.ri_gprmask
= mips_gprmask
;
10822 s
.ri_cprmask
[0] = mips_cprmask
[0];
10823 s
.ri_cprmask
[1] = mips_cprmask
[1];
10824 s
.ri_cprmask
[2] = mips_cprmask
[2];
10825 s
.ri_cprmask
[3] = mips_cprmask
[3];
10826 /* The gp_value field is set by the MIPS ELF backend. */
10828 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10829 ((Elf64_External_RegInfo
*)
10830 mips_regmask_frag
));
10833 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10834 sort of BFD interface for this. */
10835 if (mips_any_noreorder
)
10836 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10837 if (mips_pic
!= NO_PIC
)
10838 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10841 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10843 /* These functions should really be defined by the object file format,
10844 since they are related to debugging information. However, this
10845 code has to work for the a.out format, which does not define them,
10846 so we provide simple versions here. These don't actually generate
10847 any debugging information, but they do simple checking and someday
10848 somebody may make them useful. */
10852 struct loc
*loc_next
;
10853 unsigned long loc_fileno
;
10854 unsigned long loc_lineno
;
10855 unsigned long loc_offset
;
10856 unsigned short loc_delta
;
10857 unsigned short loc_count
;
10864 typedef struct proc
10866 struct proc
*proc_next
;
10867 struct symbol
*proc_isym
;
10868 struct symbol
*proc_end
;
10869 unsigned long proc_reg_mask
;
10870 unsigned long proc_reg_offset
;
10871 unsigned long proc_fpreg_mask
;
10872 unsigned long proc_fpreg_offset
;
10873 unsigned long proc_frameoffset
;
10874 unsigned long proc_framereg
;
10875 unsigned long proc_pcreg
;
10877 struct file
*proc_file
;
10882 typedef struct file
10884 struct file
*file_next
;
10885 unsigned long file_fileno
;
10886 struct symbol
*file_symbol
;
10887 struct symbol
*file_end
;
10888 struct proc
*file_proc
;
10893 static struct obstack proc_frags
;
10894 static procS
*proc_lastP
;
10895 static procS
*proc_rootP
;
10896 static int numprocs
;
10901 obstack_begin (&proc_frags
, 0x2000);
10907 /* check for premature end, nesting errors, etc */
10908 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10909 as_warn ("missing `.end' at end of assembly");
10918 if (*input_line_pointer
== '-')
10920 ++input_line_pointer
;
10923 if (!isdigit (*input_line_pointer
))
10924 as_bad ("Expected simple number.");
10925 if (input_line_pointer
[0] == '0')
10927 if (input_line_pointer
[1] == 'x')
10929 input_line_pointer
+= 2;
10930 while (isxdigit (*input_line_pointer
))
10933 val
|= hex_value (*input_line_pointer
++);
10935 return negative
? -val
: val
;
10939 ++input_line_pointer
;
10940 while (isdigit (*input_line_pointer
))
10943 val
|= *input_line_pointer
++ - '0';
10945 return negative
? -val
: val
;
10948 if (!isdigit (*input_line_pointer
))
10950 printf (" *input_line_pointer == '%c' 0x%02x\n",
10951 *input_line_pointer
, *input_line_pointer
);
10952 as_warn ("Invalid number");
10955 while (isdigit (*input_line_pointer
))
10958 val
+= *input_line_pointer
++ - '0';
10960 return negative
? -val
: val
;
10963 /* The .file directive; just like the usual .file directive, but there
10964 is an initial number which is the ECOFF file index. */
10972 line
= get_number ();
10977 /* The .end directive. */
10985 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10988 demand_empty_rest_of_line ();
10992 if (now_seg
!= text_section
)
10993 as_warn (".end not in text section");
10996 as_warn (".end and no .ent seen yet.");
11002 assert (S_GET_NAME (p
));
11003 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
11004 as_warn (".end symbol does not match .ent symbol.");
11007 proc_lastP
->proc_end
= (symbolS
*) 1;
11010 /* The .aent and .ent directives. */
11020 symbolP
= get_symbol ();
11021 if (*input_line_pointer
== ',')
11022 input_line_pointer
++;
11023 SKIP_WHITESPACE ();
11024 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
11025 number
= get_number ();
11026 if (now_seg
!= text_section
)
11027 as_warn (".ent or .aent not in text section.");
11029 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
11030 as_warn ("missing `.end'");
11034 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
11035 procP
->proc_isym
= symbolP
;
11036 procP
->proc_reg_mask
= 0;
11037 procP
->proc_reg_offset
= 0;
11038 procP
->proc_fpreg_mask
= 0;
11039 procP
->proc_fpreg_offset
= 0;
11040 procP
->proc_frameoffset
= 0;
11041 procP
->proc_framereg
= 0;
11042 procP
->proc_pcreg
= 0;
11043 procP
->proc_end
= NULL
;
11044 procP
->proc_next
= NULL
;
11046 proc_lastP
->proc_next
= procP
;
11048 proc_rootP
= procP
;
11049 proc_lastP
= procP
;
11052 demand_empty_rest_of_line ();
11055 /* The .frame directive. */
11068 frame_reg
= tc_get_register (1);
11069 if (*input_line_pointer
== ',')
11070 input_line_pointer
++;
11071 frame_off
= get_absolute_expression ();
11072 if (*input_line_pointer
== ',')
11073 input_line_pointer
++;
11074 pcreg
= tc_get_register (0);
11076 /* bob third eye */
11077 assert (proc_rootP
);
11078 proc_rootP
->proc_framereg
= frame_reg
;
11079 proc_rootP
->proc_frameoffset
= frame_off
;
11080 proc_rootP
->proc_pcreg
= pcreg
;
11081 /* bob macho .frame */
11083 /* We don't have to write out a frame stab for unoptimized code. */
11084 if (!(frame_reg
== FP
&& frame_off
== 0))
11087 as_warn ("No .ent for .frame to use.");
11088 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
11089 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
11090 S_SET_TYPE (symP
, N_RMASK
);
11091 S_SET_OTHER (symP
, 0);
11092 S_SET_DESC (symP
, 0);
11093 symP
->sy_forward
= proc_lastP
->proc_isym
;
11094 /* bob perhaps I should have used pseudo set */
11096 demand_empty_rest_of_line ();
11100 /* The .fmask and .mask directives. */
11107 char str
[100], *strP
;
11113 mask
= get_number ();
11114 if (*input_line_pointer
== ',')
11115 input_line_pointer
++;
11116 off
= get_absolute_expression ();
11118 /* bob only for coff */
11119 assert (proc_rootP
);
11120 if (reg_type
== 'F')
11122 proc_rootP
->proc_fpreg_mask
= mask
;
11123 proc_rootP
->proc_fpreg_offset
= off
;
11127 proc_rootP
->proc_reg_mask
= mask
;
11128 proc_rootP
->proc_reg_offset
= off
;
11131 /* bob macho .mask + .fmask */
11133 /* We don't have to write out a mask stab if no saved regs. */
11137 as_warn ("No .ent for .mask to use.");
11139 for (i
= 0; i
< 32; i
++)
11143 sprintf (strP
, "%c%d,", reg_type
, i
);
11144 strP
+= strlen (strP
);
11148 sprintf (strP
, ";%d,", off
);
11149 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
11150 S_SET_TYPE (symP
, N_RMASK
);
11151 S_SET_OTHER (symP
, 0);
11152 S_SET_DESC (symP
, 0);
11153 symP
->sy_forward
= proc_lastP
->proc_isym
;
11154 /* bob perhaps I should have used pseudo set */
11159 /* The .loc directive. */
11170 assert (now_seg
== text_section
);
11172 lineno
= get_number ();
11173 addroff
= frag_now_fix ();
11175 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11176 S_SET_TYPE (symbolP
, N_SLINE
);
11177 S_SET_OTHER (symbolP
, 0);
11178 S_SET_DESC (symbolP
, lineno
);
11179 symbolP
->sy_segment
= now_seg
;