1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* The name of the readonly data section. */
95 #define RDATA_SECTION_NAME ".data"
98 #define RDATA_SECTION_NAME ".rdata"
101 #define RDATA_SECTION_NAME ".rodata"
104 /* These variables are filled in with the masks of registers used.
105 The object format code reads them and puts them in the appropriate
107 unsigned long mips_gprmask
;
108 unsigned long mips_cprmask
[4];
110 /* MIPS ISA (Instruction Set Architecture) level (may be changed
111 temporarily using .set mipsN). */
112 static int mips_isa
= -1;
114 /* MIPS ISA we are using for this output file. */
115 static int file_mips_isa
;
117 /* MIPS PIC level. */
121 /* Do not generate PIC code. */
124 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
125 not sure what it is supposed to do. */
128 /* Generate PIC code as in the SVR4 MIPS ABI. */
131 /* Generate PIC code without using a global offset table: the data
132 segment has a maximum size of 64K, all data references are off
133 the $gp register, and all text references are PC relative. This
134 is used on some embedded systems. */
138 static enum mips_pic_level mips_pic
;
140 /* 1 if trap instructions should used for overflow rather than break
142 static int mips_trap
;
144 static int mips_warn_about_macros
;
145 static int mips_noreorder
;
146 static int mips_any_noreorder
;
147 static int mips_nomove
;
148 static int mips_noat
;
149 static int mips_nobopt
;
152 /* The size of the small data section. */
153 static int g_switch_value
= 8;
154 /* Whether the -G option was used. */
155 static int g_switch_seen
= 0;
161 /* handle of the OPCODE hash table */
162 static struct hash_control
*op_hash
= NULL
;
164 /* This array holds the chars that always start a comment. If the
165 pre-processor is disabled, these aren't very useful */
166 const char comment_chars
[] = "#";
168 /* This array holds the chars that only start a comment at the beginning of
169 a line. If the line seems to have the form '# 123 filename'
170 .line and .file directives will appear in the pre-processed output */
171 /* Note that input_file.c hand checks for '#' at the beginning of the
172 first line of the input file. This is because the compiler outputs
173 #NO_APP at the beginning of its output. */
174 /* Also note that C style comments are always supported. */
175 const char line_comment_chars
[] = "#";
177 /* This array holds machine specific line separator characters. */
178 const char line_separator_chars
[] = "";
180 /* Chars that can be used to separate mant from exp in floating point nums */
181 const char EXP_CHARS
[] = "eE";
183 /* Chars that mean this number is a floating point constant */
186 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
188 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
189 changed in read.c . Ideally it shouldn't have to know about it at all,
190 but nothing is ideal around here.
193 static char *insn_error
;
195 static int byte_order
= BYTE_ORDER
;
197 static int auto_align
= 1;
199 /* Symbol labelling the current insn. */
200 static symbolS
*insn_label
;
202 /* When outputting SVR4 PIC code, the assembler needs to know the
203 offset in the stack frame from which to restore the $gp register.
204 This is set by the .cprestore pseudo-op, and saved in this
206 static offsetT mips_cprestore_offset
= -1;
208 /* This is the register which holds the stack frame, as set by the
209 .frame pseudo-op. This is needed to implement .cprestore. */
210 static int mips_frame_reg
= SP
;
212 /* To output NOP instructions correctly, we need to keep information
213 about the previous two instructions. */
215 /* Whether we are optimizing. The default value of 2 means to remove
216 unneeded NOPs and swap branch instructions when possible. A value
217 of 1 means to not swap branches. A value of 0 means to always
219 static int mips_optimize
= 2;
221 /* The previous instruction. */
222 static struct mips_cl_insn prev_insn
;
224 /* The instruction before prev_insn. */
225 static struct mips_cl_insn prev_prev_insn
;
227 /* If we don't want information for prev_insn or prev_prev_insn, we
228 point the insn_mo field at this dummy integer. */
229 static const struct mips_opcode dummy_opcode
= { 0 };
231 /* Non-zero if prev_insn is valid. */
232 static int prev_insn_valid
;
234 /* The frag for the previous instruction. */
235 static struct frag
*prev_insn_frag
;
237 /* The offset into prev_insn_frag for the previous instruction. */
238 static long prev_insn_where
;
240 /* The reloc for the previous instruction, if any. */
241 static fixS
*prev_insn_fixp
;
243 /* Non-zero if the previous instruction was in a delay slot. */
244 static int prev_insn_is_delay_slot
;
246 /* Non-zero if the previous instruction was in a .set noreorder. */
247 static int prev_insn_unreordered
;
249 /* Non-zero if the previous previous instruction was in a .set
251 static int prev_prev_insn_unreordered
;
253 /* Since the MIPS does not have multiple forms of PC relative
254 instructions, we do not have to do relaxing as is done on other
255 platforms. However, we do have to handle GP relative addressing
256 correctly, which turns out to be a similar problem.
258 Every macro that refers to a symbol can occur in (at least) two
259 forms, one with GP relative addressing and one without. For
260 example, loading a global variable into a register generally uses
261 a macro instruction like this:
263 If i can be addressed off the GP register (this is true if it is in
264 the .sbss or .sdata section, or if it is known to be smaller than
265 the -G argument) this will generate the following instruction:
267 This instruction will use a GPREL reloc. If i can not be addressed
268 off the GP register, the following instruction sequence will be used:
271 In this case the first instruction will have a HI16 reloc, and the
272 second reloc will have a LO16 reloc. Both relocs will be against
275 The issue here is that we may not know whether i is GP addressable
276 until after we see the instruction that uses it. Therefore, we
277 want to be able to choose the final instruction sequence only at
278 the end of the assembly. This is similar to the way other
279 platforms choose the size of a PC relative instruction only at the
282 When generating position independent code we do not use GP
283 addressing in quite the same way, but the issue still arises as
284 external symbols and local symbols must be handled differently.
286 We handle these issues by actually generating both possible
287 instruction sequences. The longer one is put in a frag_var with
288 type rs_machine_dependent. We encode what to do with the frag in
289 the subtype field. We encode (1) the number of existing bytes to
290 replace, (2) the number of new bytes to use, (3) the offset from
291 the start of the existing bytes to the first reloc we must generate
292 (that is, the offset is applied from the start of the existing
293 bytes after they are replaced by the new bytes, if any), (4) the
294 offset from the start of the existing bytes to the second reloc,
295 (5) whether a third reloc is needed (the third reloc is always four
296 bytes after the second reloc), and (6) whether to warn if this
297 variant is used (this is sometimes needed if .set nomacro or .set
298 noat is in effect). All these numbers are reasonably small.
300 Generating two instruction sequences must be handled carefully to
301 ensure that delay slots are handled correctly. Fortunately, there
302 are a limited number of cases. When the second instruction
303 sequence is generated, append_insn is directed to maintain the
304 existing delay slot information, so it continues to apply to any
305 code after the second instruction sequence. This means that the
306 second instruction sequence must not impose any requirements not
307 required by the first instruction sequence.
309 These variant frags are then handled in functions called by the
310 machine independent code. md_estimate_size_before_relax returns
311 the final size of the frag. md_convert_frag sets up the final form
312 of the frag. tc_gen_reloc adjust the first reloc and adds a second
314 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
318 | (((reloc1) + 64) << 9) \
319 | (((reloc2) + 64) << 2) \
320 | ((reloc3) ? (1 << 1) : 0) \
322 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
323 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
324 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
325 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
326 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
327 #define RELAX_WARN(i) ((i) & 1)
329 /* Prototypes for static functions. */
332 #define internalError() \
333 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
335 #define internalError() as_fatal ("MIPS internal Error");
338 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
339 unsigned int reg
, int fpr
));
340 static void append_insn
PARAMS ((char *place
,
341 struct mips_cl_insn
* ip
,
343 bfd_reloc_code_real_type r
));
344 static void mips_no_prev_insn
PARAMS ((void));
345 static void mips_emit_delays
PARAMS ((void));
346 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
347 const char *name
, const char *fmt
,
349 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
350 expressionS
* ep
, int regnum
));
351 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
352 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
354 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
355 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
356 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
357 #ifdef LOSING_COMPILER
358 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
360 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
361 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
362 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
363 static symbolS
*get_symbol
PARAMS ((void));
364 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
365 static void s_align
PARAMS ((int));
366 static void s_stringer
PARAMS ((int));
367 static void s_change_sec
PARAMS ((int));
368 static void s_cons
PARAMS ((int));
369 static void s_err
PARAMS ((int));
370 static void s_extern
PARAMS ((int));
371 static void s_float_cons
PARAMS ((int));
372 static void s_option
PARAMS ((int));
373 static void s_mipsset
PARAMS ((int));
374 static void s_mips_space
PARAMS ((int));
375 static void s_abicalls
PARAMS ((int));
376 static void s_cpload
PARAMS ((int));
377 static void s_cprestore
PARAMS ((int));
378 static void s_gpword
PARAMS ((int));
379 static void s_cpadd
PARAMS ((int));
380 #ifndef ECOFF_DEBUGGING
381 static void md_obj_begin
PARAMS ((void));
382 static void md_obj_end
PARAMS ((void));
383 static long get_number
PARAMS ((void));
384 static void s_ent
PARAMS ((int));
385 static void s_mipsend
PARAMS ((int));
386 static void s_file
PARAMS ((int));
388 static void s_frame
PARAMS ((int));
389 static void s_loc
PARAMS ((int));
390 static void s_mask
PARAMS ((char));
396 The following pseudo-ops from the Kane and Heinrich MIPS book
397 should be defined here, but are currently unsupported: .alias,
398 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
400 The following pseudo-ops from the Kane and Heinrich MIPS book are
401 specific to the type of debugging information being generated, and
402 should be defined by the object format: .aent, .begin, .bend,
403 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
406 The following pseudo-ops from the Kane and Heinrich MIPS book are
407 not MIPS CPU specific, but are also not specific to the object file
408 format. This file is probably the best place to define them, but
409 they are not currently supported: .asm0, .endr, .lab, .repeat,
410 .struct, .weakext. */
412 const pseudo_typeS md_pseudo_table
[] =
414 /* MIPS specific pseudo-ops. */
415 {"option", s_option
, 0},
416 {"set", s_mipsset
, 0},
417 {"rdata", s_change_sec
, 'r'},
418 {"sdata", s_change_sec
, 's'},
419 {"livereg", s_ignore
, 0},
420 { "abicalls", s_abicalls
, 0},
421 { "cpload", s_cpload
, 0},
422 { "cprestore", s_cprestore
, 0},
423 { "gpword", s_gpword
, 0},
424 { "cpadd", s_cpadd
, 0},
426 /* Relatively generic pseudo-ops that happen to be used on MIPS
428 {"asciiz", s_stringer
, 1},
429 {"bss", s_change_sec
, 'b'},
432 {"dword", s_cons
, 3},
434 /* These pseudo-ops are defined in read.c, but must be overridden
435 here for one reason or another. */
436 {"align", s_align
, 0},
437 {"ascii", s_stringer
, 0},
438 {"asciz", s_stringer
, 1},
440 {"data", s_change_sec
, 'd'},
441 {"double", s_float_cons
, 'd'},
442 {"extern", s_extern
, 0},
443 {"float", s_float_cons
, 'f'},
444 {"hword", s_cons
, 1},
449 {"short", s_cons
, 1},
450 {"single", s_float_cons
, 'f'},
451 {"space", s_mips_space
, 0},
452 {"text", s_change_sec
, 't'},
455 #ifndef ECOFF_DEBUGGING
456 /* These pseudo-ops should be defined by the object file format.
457 However, a.out doesn't support them, so we have versions here. */
459 {"bgnb", s_ignore
, 0},
460 {"end", s_mipsend
, 0},
461 {"endb", s_ignore
, 0},
464 {"fmask", s_ignore
, 'F'},
465 {"frame", s_ignore
, 0},
466 {"loc", s_ignore
, 0},
467 {"mask", s_ignore
, 'R'},
468 {"verstamp", s_ignore
, 0},
475 const relax_typeS md_relax_table
[] =
480 static char *expr_end
;
482 static expressionS imm_expr
;
483 static expressionS offset_expr
;
484 static bfd_reloc_code_real_type imm_reloc
;
485 static bfd_reloc_code_real_type offset_reloc
;
487 /* FIXME: This should be handled in a different way. */
488 extern int target_big_endian
;
491 * This function is called once, at assembler startup time. It should
492 * set up all the tables, etc. that the MD part of the assembler will need.
498 register const char *retval
= NULL
;
499 register unsigned int i
= 0;
503 if (strcmp (TARGET_CPU
, "mips") == 0)
505 else if (strcmp (TARGET_CPU
, "r6000") == 0
506 || strcmp (TARGET_CPU
, "mips2") == 0)
508 else if (strcmp (TARGET_CPU
, "mips64") == 0
509 || strcmp (TARGET_CPU
, "r4000") == 0
510 || strcmp (TARGET_CPU
, "mips3") == 0)
516 if (mips_isa
< 2 && mips_trap
)
517 as_bad ("trap exception not supported at ISA 1");
522 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
525 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
528 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
532 as_warn ("Could not set architecture and machine");
534 file_mips_isa
= mips_isa
;
536 op_hash
= hash_new ();
538 for (i
= 0; i
< NUMOPCODES
;)
540 const char *name
= mips_opcodes
[i
].name
;
542 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
545 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
546 mips_opcodes
[i
].name
, retval
);
547 as_fatal ("Broken assembler. No assembly attempted.");
551 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
552 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
553 != mips_opcodes
[i
].match
))
555 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
556 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
557 as_fatal ("Broken assembler. No assembly attempted.");
561 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
564 mips_no_prev_insn ();
572 /* set the default alignment for the text section (2**2) */
573 record_alignment (text_section
, 2);
575 /* FIXME: This should be handled in a different way. */
576 target_big_endian
= byte_order
== BIG_ENDIAN
;
579 bfd_set_gp_size (stdoutput
, g_switch_value
);
583 /* Sections must be aligned to 16 byte boundaries. */
584 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
585 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
586 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
588 /* Create a .reginfo section for register masks and a .mdebug
589 section for debugging information. */
597 sec
= subseg_new (".reginfo", (subsegT
) 0);
599 /* The ABI says this section should be loaded so that the running
600 program can access it. */
601 (void) bfd_set_section_flags (stdoutput
, sec
,
602 (SEC_ALLOC
| SEC_LOAD
603 | SEC_READONLY
| SEC_DATA
));
604 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
606 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
608 #ifdef ECOFF_DEBUGGING
609 sec
= subseg_new (".mdebug", (subsegT
) 0);
610 (void) bfd_set_section_flags (stdoutput
, sec
,
611 SEC_HAS_CONTENTS
| SEC_READONLY
);
612 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
615 subseg_set (seg
, subseg
);
619 #ifndef ECOFF_DEBUGGING
627 #ifndef ECOFF_DEBUGGING
636 struct mips_cl_insn insn
;
638 imm_expr
.X_op
= O_absent
;
639 offset_expr
.X_op
= O_absent
;
641 mips_ip (str
, &insn
);
644 as_bad ("%s `%s'", insn_error
, str
);
647 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
653 if (imm_expr
.X_op
!= O_absent
)
654 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
655 else if (offset_expr
.X_op
!= O_absent
)
656 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
658 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
662 /* See whether instruction IP reads register REG. If FPR is non-zero,
663 REG is a floating point register. */
666 insn_uses_reg (ip
, reg
, fpr
)
667 struct mips_cl_insn
*ip
;
671 /* Don't report on general register 0, since it never changes. */
672 if (! fpr
&& reg
== 0)
677 /* If we are called with either $f0 or $f1, we must check $f0.
678 This is not optimal, because it will introduce an unnecessary
679 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
680 need to distinguish reading both $f0 and $f1 or just one of
681 them. Note that we don't have to check the other way,
682 because there is no instruction that sets both $f0 and $f1
683 and requires a delay. */
684 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
685 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
686 == (reg
&~ (unsigned) 1)))
688 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
689 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
690 == (reg
&~ (unsigned) 1)))
695 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
696 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
698 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
699 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
706 /* Output an instruction. PLACE is where to put the instruction; if
707 it is NULL, this uses frag_more to get room. IP is the instruction
708 information. ADDRESS_EXPR is an operand of the instruction to be
709 used with RELOC_TYPE. */
712 append_insn (place
, ip
, address_expr
, reloc_type
)
714 struct mips_cl_insn
*ip
;
715 expressionS
*address_expr
;
716 bfd_reloc_code_real_type reloc_type
;
718 register unsigned long prev_pinfo
, pinfo
;
723 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
724 pinfo
= ip
->insn_mo
->pinfo
;
726 if (place
== NULL
&& ! mips_noreorder
)
728 /* If the previous insn required any delay slots, see if we need
729 to insert a NOP or two. There are eight kinds of possible
730 hazards, of which an instruction can have at most one type.
731 (1) a load from memory delay
732 (2) a load from a coprocessor delay
733 (3) an unconditional branch delay
734 (4) a conditional branch delay
735 (5) a move to coprocessor register delay
736 (6) a load coprocessor register from memory delay
737 (7) a coprocessor condition code delay
738 (8) a HI/LO special register delay
740 There are a lot of optimizations we could do that we don't.
741 In particular, we do not, in general, reorder instructions.
742 If you use gcc with optimization, it will reorder
743 instructions and generally do much more optimization then we
744 do here; repeating all that work in the assembler would only
745 benefit hand written assembly code, and does not seem worth
748 /* This is how a NOP is emitted. */
749 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
751 /* The previous insn might require a delay slot, depending upon
752 the contents of the current insn. */
753 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
755 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
757 /* A load from a coprocessor or from memory. All load
758 delays delay the use of general register rt for one
759 instruction on the r3000. The r6000 and r4000 use
761 know (prev_pinfo
& INSN_WRITE_GPR_T
);
762 if (mips_optimize
== 0
763 || insn_uses_reg (ip
,
764 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
769 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
771 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
773 /* A generic coprocessor delay. The previous instruction
774 modified a coprocessor general or control register. If
775 it modified a control register, we need to avoid any
776 coprocessor instruction (this is probably not always
777 required, but it sometimes is). If it modified a general
778 register, we avoid using that register.
780 On the r6000 and r4000 loading a coprocessor register
781 from memory is interlocked, and does not require a delay.
783 This case is not handled very well. There is no special
784 knowledge of CP0 handling, and the coprocessors other
785 than the floating point unit are not distinguished at
787 if (prev_pinfo
& INSN_WRITE_FPR_T
)
789 if (mips_optimize
== 0
790 || insn_uses_reg (ip
,
791 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
796 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
798 if (mips_optimize
== 0
799 || insn_uses_reg (ip
,
800 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
807 /* We don't know exactly what the previous instruction
808 does. If the current instruction uses a coprocessor
809 register, we must insert a NOP. If previous
810 instruction may set the condition codes, and the
811 current instruction uses them, we must insert two
813 if (mips_optimize
== 0
814 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
815 && (pinfo
& INSN_READ_COND_CODE
)))
817 else if (pinfo
& INSN_COP
)
821 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
823 /* The previous instruction sets the coprocessor condition
824 codes, but does not require a general coprocessor delay
825 (this means it is a floating point comparison
826 instruction). If this instruction uses the condition
827 codes, we need to insert a single NOP. */
828 if (mips_optimize
== 0
829 || (pinfo
& INSN_READ_COND_CODE
))
832 else if (prev_pinfo
& INSN_READ_LO
)
834 /* The previous instruction reads the LO register; if the
835 current instruction writes to the LO register, we must
837 if (mips_optimize
== 0
838 || (pinfo
& INSN_WRITE_LO
))
841 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
843 /* The previous instruction reads the HI register; if the
844 current instruction writes to the HI register, we must
846 if (mips_optimize
== 0
847 || (pinfo
& INSN_WRITE_HI
))
851 /* There are two cases which require two intervening
852 instructions: 1) setting the condition codes using a move to
853 coprocessor instruction which requires a general coprocessor
854 delay and then reading the condition codes 2) reading the HI
855 or LO register and then writing to it. If we are not already
856 emitting a NOP instruction, we must check for these cases
857 compared to the instruction previous to the previous
860 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
861 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
862 && (pinfo
& INSN_READ_COND_CODE
))
863 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
864 && (pinfo
& INSN_WRITE_LO
))
865 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
866 && (pinfo
& INSN_WRITE_HI
))))
869 /* If we are being given a nop instruction, don't bother with
870 one of the nops we would otherwise output. This will only
871 happen when a nop instruction is used with mips_optimize set
873 if (nops
> 0 && ip
->insn_opcode
== 0)
876 /* Now emit the right number of NOP instructions. */
883 listing_prev_line ();
884 if (insn_label
!= NULL
)
886 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
887 insn_label
->sy_frag
= frag_now
;
888 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
898 if (address_expr
!= NULL
)
900 if (address_expr
->X_op
== O_constant
)
905 ip
->insn_opcode
|= address_expr
->X_add_number
;
909 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
912 case BFD_RELOC_MIPS_JMP
:
913 case BFD_RELOC_16_PCREL_S2
:
922 assert (reloc_type
!= BFD_RELOC_UNUSED
);
924 /* Don't generate a reloc if we are writing into a variant
927 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
929 reloc_type
== BFD_RELOC_16_PCREL_S2
,
934 md_number_to_chars (f
, ip
->insn_opcode
, 4);
936 /* Update the register mask information. */
937 if (pinfo
& INSN_WRITE_GPR_D
)
938 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
939 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
940 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
941 if (pinfo
& INSN_READ_GPR_S
)
942 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
943 if (pinfo
& INSN_WRITE_GPR_31
)
944 mips_gprmask
|= 1 << 31;
945 if (pinfo
& INSN_WRITE_FPR_D
)
946 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
947 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
948 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
949 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
950 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
951 if (pinfo
& INSN_COP
)
953 /* We don't keep enough information to sort these cases out. */
955 /* Never set the bit for $0, which is always zero. */
956 mips_gprmask
&=~ 1 << 0;
958 if (place
== NULL
&& ! mips_noreorder
)
960 /* Filling the branch delay slot is more complex. We try to
961 switch the branch with the previous instruction, which we can
962 do if the previous instruction does not set up a condition
963 that the branch tests and if the branch is not itself the
964 target of any branch. */
965 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
966 || (pinfo
& INSN_COND_BRANCH_DELAY
))
968 if (mips_optimize
< 2
969 /* If we have seen .set volatile or .set nomove, don't
972 /* If we had to emit any NOP instructions, then we
973 already know we can not swap. */
975 /* If we don't even know the previous insn, we can not
978 /* If the previous insn is already in a branch delay
979 slot, then we can not swap. */
980 || prev_insn_is_delay_slot
981 /* If the previous previous insn was in a .set
982 noreorder, we can't swap. Actually, the MIPS
983 assembler will swap in this situation. However, gcc
984 configured -with-gnu-as will generate code like
990 in which we can not swap the bne and INSN. If gcc is
991 not configured -with-gnu-as, it does not output the
992 .set pseudo-ops. We don't have to check
993 prev_insn_unreordered, because prev_insn_valid will
994 be 0 in that case. We don't want to use
995 prev_prev_insn_valid, because we do want to be able
996 to swap at the start of a function. */
997 || prev_prev_insn_unreordered
998 /* If the branch is itself the target of a branch, we
999 can not swap. We cheat on this; all we check for is
1000 whether there is a label on this instruction. If
1001 there are any branches to anything other than a
1002 label, users must use .set noreorder. */
1003 || insn_label
!= NULL
1004 /* If the previous instruction is in a variant frag, we
1005 can not do the swap. */
1006 || prev_insn_frag
->fr_type
== rs_machine_dependent
1007 /* If the branch reads the condition codes, we don't
1008 even try to swap, because in the sequence
1013 we can not swap, and I don't feel like handling that
1015 || (pinfo
& INSN_READ_COND_CODE
)
1016 /* We can not swap with an instruction that requires a
1017 delay slot, becase the target of the branch might
1018 interfere with that instruction. */
1020 & (INSN_LOAD_COPROC_DELAY
1021 | INSN_COPROC_MOVE_DELAY
1022 | INSN_WRITE_COND_CODE
1027 & (INSN_LOAD_MEMORY_DELAY
1028 | INSN_COPROC_MEMORY_DELAY
)))
1029 /* We can not swap with a branch instruction. */
1031 & (INSN_UNCOND_BRANCH_DELAY
1032 | INSN_COND_BRANCH_DELAY
1033 | INSN_COND_BRANCH_LIKELY
))
1034 /* We do not swap with a trap instruction, since it
1035 complicates trap handlers to have the trap
1036 instruction be in a delay slot. */
1037 || (prev_pinfo
& INSN_TRAP
)
1038 /* If the branch reads a register that the previous
1039 instruction sets, we can not swap. */
1040 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1041 && insn_uses_reg (ip
,
1042 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1045 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1046 && insn_uses_reg (ip
,
1047 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1050 /* If the branch writes a register that the previous
1051 instruction sets, we can not swap (we know that
1052 branches write only to RD or to $31). */
1053 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1054 && (((pinfo
& INSN_WRITE_GPR_D
)
1055 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1056 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1057 || ((pinfo
& INSN_WRITE_GPR_31
)
1058 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1061 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1062 && (((pinfo
& INSN_WRITE_GPR_D
)
1063 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1064 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1065 || ((pinfo
& INSN_WRITE_GPR_31
)
1066 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1069 /* If the branch writes a register that the previous
1070 instruction reads, we can not swap (we know that
1071 branches only write to RD or to $31). */
1072 || ((pinfo
& INSN_WRITE_GPR_D
)
1073 && insn_uses_reg (&prev_insn
,
1074 ((ip
->insn_opcode
>> OP_SH_RD
)
1077 || ((pinfo
& INSN_WRITE_GPR_31
)
1078 && insn_uses_reg (&prev_insn
, 31, 0))
1079 /* If we are generating embedded PIC code, the branch
1080 might be expanded into a sequence which uses $at, so
1081 we can't swap with an instruction which reads it. */
1082 || (mips_pic
== EMBEDDED_PIC
1083 && insn_uses_reg (&prev_insn
, AT
, 0))
1084 /* If the previous previous instruction has a load
1085 delay, and sets a register that the branch reads, we
1087 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1089 && (prev_prev_insn
.insn_mo
->pinfo
1090 & INSN_LOAD_MEMORY_DELAY
)))
1091 && insn_uses_reg (ip
,
1092 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1096 /* We could do even better for unconditional branches to
1097 portions of this object file; we could pick up the
1098 instruction at the destination, put it in the delay
1099 slot, and bump the destination address. */
1101 /* Update the previous insn information. */
1102 prev_prev_insn
= *ip
;
1103 prev_insn
.insn_mo
= &dummy_opcode
;
1110 /* It looks like we can actually do the swap. */
1111 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1112 memcpy (temp
, prev_f
, 4);
1113 memcpy (prev_f
, f
, 4);
1114 memcpy (f
, temp
, 4);
1117 prev_insn_fixp
->fx_frag
= frag_now
;
1118 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1122 fixp
->fx_frag
= prev_insn_frag
;
1123 fixp
->fx_where
= prev_insn_where
;
1125 /* Update the previous insn information; leave prev_insn
1127 prev_prev_insn
= *ip
;
1129 prev_insn_is_delay_slot
= 1;
1131 /* If that was an unconditional branch, forget the previous
1132 insn information. */
1133 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1135 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1136 prev_insn
.insn_mo
= &dummy_opcode
;
1139 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1141 /* We don't yet optimize a branch likely. What we should do
1142 is look at the target, copy the instruction found there
1143 into the delay slot, and increment the branch to jump to
1144 the next instruction. */
1146 /* Update the previous insn information. */
1147 prev_prev_insn
= *ip
;
1148 prev_insn
.insn_mo
= &dummy_opcode
;
1152 /* Update the previous insn information. */
1154 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1156 prev_prev_insn
= prev_insn
;
1159 /* Any time we see a branch, we always fill the delay slot
1160 immediately; since this insn is not a branch, we know it
1161 is not in a delay slot. */
1162 prev_insn_is_delay_slot
= 0;
1165 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1166 prev_insn_unreordered
= 0;
1167 prev_insn_frag
= frag_now
;
1168 prev_insn_where
= f
- frag_now
->fr_literal
;
1169 prev_insn_fixp
= fixp
;
1170 prev_insn_valid
= 1;
1173 /* We just output an insn, so the next one doesn't have a label. */
1177 /* This function forgets that there was any previous instruction or
1181 mips_no_prev_insn ()
1183 prev_insn
.insn_mo
= &dummy_opcode
;
1184 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1185 prev_insn_valid
= 0;
1186 prev_insn_is_delay_slot
= 0;
1187 prev_insn_unreordered
= 0;
1188 prev_prev_insn_unreordered
= 0;
1192 /* This function must be called whenever we turn on noreorder or emit
1193 something other than instructions. It inserts any NOPS which might
1194 be needed by the previous instruction, and clears the information
1195 kept for the previous instructions. */
1200 if (! mips_noreorder
)
1205 if ((prev_insn
.insn_mo
->pinfo
1206 & (INSN_LOAD_COPROC_DELAY
1207 | INSN_COPROC_MOVE_DELAY
1208 | INSN_WRITE_COND_CODE
1212 && (prev_insn
.insn_mo
->pinfo
1213 & (INSN_LOAD_MEMORY_DELAY
1214 | INSN_COPROC_MEMORY_DELAY
))))
1217 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1218 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1219 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1222 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1223 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1224 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1229 if (insn_label
!= NULL
)
1231 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1232 insn_label
->sy_frag
= frag_now
;
1233 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1238 mips_no_prev_insn ();
1241 /* Build an instruction created by a macro expansion. This is passed
1242 a pointer to the count of instructions created so far, an
1243 expression, the name of the instruction to build, an operand format
1244 string, and corresponding arguments. */
1248 macro_build (char *place
,
1254 #else /* ! defined (NO_STDARG) */
1256 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1263 #endif /* ! defined (NO_STDARG) */
1265 struct mips_cl_insn insn
;
1266 bfd_reloc_code_real_type r
;
1270 va_start (args
, fmt
);
1276 * If the macro is about to expand into a second instruction,
1277 * print a warning if needed. We need to pass ip as a parameter
1278 * to generate a better warning message here...
1280 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1281 as_warn ("Macro instruction expanded into multiple instructions");
1284 *counter
+= 1; /* bump instruction counter */
1286 r
= BFD_RELOC_UNUSED
;
1287 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1288 assert (insn
.insn_mo
);
1289 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1291 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1292 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1295 assert (insn
.insn_mo
->name
);
1296 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1298 insn
.insn_opcode
= insn
.insn_mo
->match
;
1314 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1320 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1325 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1330 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1337 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1341 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1345 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1352 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1358 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1359 assert (r
== BFD_RELOC_MIPS_GPREL
1360 || r
== BFD_RELOC_MIPS_LITERAL
1361 || r
== BFD_RELOC_LO16
1362 || r
== BFD_RELOC_MIPS_GOT16
1363 || r
== BFD_RELOC_MIPS_CALL16
1364 || (ep
->X_op
== O_subtract
1365 && now_seg
== text_section
1366 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1367 && r
== BFD_RELOC_PCREL_LO16
));
1371 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1373 && (ep
->X_op
== O_constant
1374 || (ep
->X_op
== O_symbol
1375 && (r
== BFD_RELOC_HI16_S
1376 || r
== BFD_RELOC_HI16
))
1377 || (ep
->X_op
== O_subtract
1378 && now_seg
== text_section
1379 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1380 && r
== BFD_RELOC_PCREL_HI16_S
)));
1381 if (ep
->X_op
== O_constant
)
1383 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1385 r
= BFD_RELOC_UNUSED
;
1390 assert (ep
!= NULL
);
1392 * This allows macro() to pass an immediate expression for
1393 * creating short branches without creating a symbol.
1394 * Note that the expression still might come from the assembly
1395 * input, in which case the value is not checked for range nor
1396 * is a relocation entry generated (yuck).
1398 if (ep
->X_op
== O_constant
)
1400 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1404 r
= BFD_RELOC_16_PCREL_S2
;
1408 assert (ep
!= NULL
);
1409 r
= BFD_RELOC_MIPS_JMP
;
1418 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1420 append_insn (place
, &insn
, ep
, r
);
1424 * Generate a "lui" instruction.
1427 macro_build_lui (place
, counter
, ep
, regnum
)
1433 expressionS high_expr
;
1434 struct mips_cl_insn insn
;
1435 bfd_reloc_code_real_type r
;
1436 CONST
char *name
= "lui";
1437 CONST
char *fmt
= "t,u";
1443 high_expr
.X_op
= O_constant
;
1444 high_expr
.X_add_number
= 0;
1447 if (high_expr
.X_op
== O_constant
)
1449 /* we can compute the instruction now without a relocation entry */
1450 if (high_expr
.X_add_number
& 0x8000)
1451 high_expr
.X_add_number
+= 0x10000;
1452 high_expr
.X_add_number
=
1453 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1454 r
= BFD_RELOC_UNUSED
;
1458 assert (ep
->X_op
== O_symbol
);
1459 /* _gp_disp is a special case, used from s_cpload. */
1460 assert (mips_pic
== NO_PIC
1461 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1462 r
= BFD_RELOC_HI16_S
;
1466 * If the macro is about to expand into a second instruction,
1467 * print a warning if needed. We need to pass ip as a parameter
1468 * to generate a better warning message here...
1470 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1471 as_warn ("Macro instruction expanded into multiple instructions");
1474 *counter
+= 1; /* bump instruction counter */
1476 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1477 assert (insn
.insn_mo
);
1478 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1479 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1481 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1482 if (r
== BFD_RELOC_UNUSED
)
1484 insn
.insn_opcode
|= high_expr
.X_add_number
;
1485 append_insn (place
, &insn
, NULL
, r
);
1488 append_insn (place
, &insn
, &high_expr
, r
);
1492 * Generates code to set the $at register to true (one)
1493 * if reg is less than the immediate expression.
1496 set_at (counter
, reg
, unsignedp
)
1501 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1502 macro_build ((char *) NULL
, counter
, &imm_expr
,
1503 unsignedp
? "sltiu" : "slti",
1504 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1507 load_register (counter
, AT
, &imm_expr
);
1508 macro_build ((char *) NULL
, counter
, NULL
,
1509 unsignedp
? "sltu" : "slt",
1510 "d,v,t", AT
, reg
, AT
);
1514 /* Warn if an expression is not a constant. */
1517 check_absolute_expr (ip
, ex
)
1518 struct mips_cl_insn
*ip
;
1521 if (ex
->X_op
!= O_constant
)
1522 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1526 * This routine generates the least number of instructions neccessary to load
1527 * an absolute expression value into a register.
1530 load_register (counter
, reg
, ep
)
1535 assert (ep
->X_op
== O_constant
);
1536 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1537 macro_build ((char *) NULL
, counter
, ep
,
1538 mips_isa
< 3 ? "addiu" : "daddiu",
1539 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1540 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1541 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1542 (int) BFD_RELOC_LO16
);
1543 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1544 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1545 == ~ (offsetT
) 0x7fffffff))
1547 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1548 (int) BFD_RELOC_HI16
);
1549 if ((ep
->X_add_number
& 0xffff) != 0)
1550 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1551 (int) BFD_RELOC_LO16
);
1553 else if (mips_isa
< 3)
1555 as_bad ("Number larger than 32 bits");
1556 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1557 (int) BFD_RELOC_LO16
);
1562 expressionS hi32
, lo32
;
1566 hi32
.X_add_number
>>= shift
;
1567 hi32
.X_add_number
&= 0xffffffff;
1568 if ((hi32
.X_add_number
& 0x80000000) != 0)
1569 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1570 load_register (counter
, reg
, &hi32
);
1572 lo32
.X_add_number
&= 0xffffffff;
1573 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1574 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1580 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1583 mid16
.X_add_number
>>= 16;
1584 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1585 reg
, (int) BFD_RELOC_LO16
);
1586 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1589 if ((lo32
.X_add_number
& 0xffff) != 0)
1590 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1591 (int) BFD_RELOC_LO16
);
1595 /* Load an address into a register. */
1598 load_address (counter
, reg
, ep
)
1605 if (ep
->X_op
!= O_constant
1606 && ep
->X_op
!= O_symbol
)
1608 as_bad ("expression too complex");
1609 ep
->X_op
= O_constant
;
1612 if (ep
->X_op
== O_constant
)
1614 load_register (counter
, reg
, ep
);
1618 if (mips_pic
== NO_PIC
)
1620 /* If this is a reference to a GP relative symbol, we want
1621 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1623 lui $reg,<sym> (BFD_RELOC_HI16_S)
1624 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1625 If we have an addend, we always use the latter form. */
1626 if (ep
->X_add_number
!= 0)
1631 macro_build ((char *) NULL
, counter
, ep
,
1632 mips_isa
< 3 ? "addiu" : "daddiu",
1633 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1634 p
= frag_var (rs_machine_dependent
, 8, 0,
1635 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1636 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1638 macro_build_lui (p
, counter
, ep
, reg
);
1641 macro_build (p
, counter
, ep
,
1642 mips_isa
< 3 ? "addiu" : "daddiu",
1643 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1645 else if (mips_pic
== SVR4_PIC
)
1649 /* If this is a reference to an external symbol, we want
1650 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1652 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1654 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1655 If there is a constant, it must be added in after. */
1656 ex
.X_add_number
= ep
->X_add_number
;
1657 ep
->X_add_number
= 0;
1659 macro_build ((char *) NULL
, counter
, ep
,
1660 mips_isa
< 3 ? "lw" : "ld",
1661 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1662 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1663 p
= frag_var (rs_machine_dependent
, 4, 0,
1664 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1665 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1666 macro_build (p
, counter
, ep
,
1667 mips_isa
< 3 ? "addiu" : "daddiu",
1668 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1669 if (ex
.X_add_number
!= 0)
1671 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1672 as_bad ("PIC code offset overflow (max 16 signed bits)");
1673 ex
.X_op
= O_constant
;
1674 macro_build (p
, counter
, &ex
,
1675 mips_isa
< 3 ? "addiu" : "daddiu",
1676 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1679 else if (mips_pic
== EMBEDDED_PIC
)
1682 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1684 macro_build ((char *) NULL
, counter
, ep
,
1685 mips_isa
< 3 ? "addiu" : "daddiu",
1686 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1694 * This routine implements the seemingly endless macro or synthesized
1695 * instructions and addressing modes in the mips assembly language. Many
1696 * of these macros are simple and are similar to each other. These could
1697 * probably be handled by some kind of table or grammer aproach instead of
1698 * this verbose method. Others are not simple macros but are more like
1699 * optimizing code generation.
1700 * One interesting optimization is when several store macros appear
1701 * consecutivly that would load AT with the upper half of the same address.
1702 * The ensuing load upper instructions are ommited. This implies some kind
1703 * of global optimization. We currently only optimize within a single macro.
1704 * For many of the load and store macros if the address is specified as a
1705 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1706 * first load register 'at' with zero and use it as the base register. The
1707 * mips assembler simply uses register $zero. Just one tiny optimization
1712 struct mips_cl_insn
*ip
;
1714 register int treg
, sreg
, dreg
, breg
;
1727 bfd_reloc_code_real_type r
;
1729 int hold_mips_optimize
;
1731 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1732 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1733 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1734 mask
= ip
->insn_mo
->mask
;
1736 expr1
.X_op
= O_constant
;
1737 expr1
.X_op_symbol
= NULL
;
1738 expr1
.X_add_symbol
= NULL
;
1739 expr1
.X_add_number
= 1;
1751 mips_emit_delays ();
1753 mips_any_noreorder
= 1;
1755 expr1
.X_add_number
= 8;
1756 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1758 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1760 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1761 macro_build ((char *) NULL
, &icnt
, NULL
,
1762 dbl
? "dsub" : "sub",
1763 "d,v,t", dreg
, 0, sreg
);
1786 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1788 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1789 (int) BFD_RELOC_LO16
);
1792 load_register (&icnt
, AT
, &imm_expr
);
1793 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1812 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1814 if (mask
!= M_NOR_I
)
1815 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1816 sreg
, (int) BFD_RELOC_LO16
);
1819 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1820 treg
, sreg
, (int) BFD_RELOC_LO16
);
1821 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1827 load_register (&icnt
, AT
, &imm_expr
);
1828 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1845 if (imm_expr
.X_add_number
== 0)
1847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1851 load_register (&icnt
, AT
, &imm_expr
);
1852 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1860 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1861 likely
? "bgezl" : "bgez",
1867 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1868 likely
? "blezl" : "blez",
1872 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1873 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1874 likely
? "beql" : "beq",
1881 /* check for > max integer */
1882 maxnum
= 0x7fffffff;
1890 if (imm_expr
.X_add_number
>= maxnum
)
1893 /* result is always false */
1896 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1897 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1901 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1902 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1907 imm_expr
.X_add_number
++;
1911 if (mask
== M_BGEL_I
)
1913 if (imm_expr
.X_add_number
== 0)
1915 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1916 likely
? "bgezl" : "bgez",
1920 if (imm_expr
.X_add_number
== 1)
1922 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1923 likely
? "bgtzl" : "bgtz",
1927 maxnum
= 0x7fffffff;
1935 maxnum
= - maxnum
- 1;
1936 if (imm_expr
.X_add_number
<= maxnum
)
1939 /* result is always true */
1940 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1941 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1944 set_at (&icnt
, sreg
, 0);
1945 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1946 likely
? "beql" : "beq",
1957 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1958 likely
? "beql" : "beq",
1962 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1964 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1965 likely
? "beql" : "beq",
1972 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1974 imm_expr
.X_add_number
++;
1978 if (mask
== M_BGEUL_I
)
1980 if (imm_expr
.X_add_number
== 0)
1982 if (imm_expr
.X_add_number
== 1)
1984 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1985 likely
? "bnel" : "bne",
1989 set_at (&icnt
, sreg
, 1);
1990 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1991 likely
? "beql" : "beq",
2000 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2001 likely
? "bgtzl" : "bgtz",
2007 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2008 likely
? "bltzl" : "bltz",
2012 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2013 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2014 likely
? "bnel" : "bne",
2023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2024 likely
? "bnel" : "bne",
2030 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2033 likely
? "bnel" : "bne",
2042 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2043 likely
? "blezl" : "blez",
2049 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2050 likely
? "bgezl" : "bgez",
2054 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2055 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2056 likely
? "beql" : "beq",
2063 maxnum
= 0x7fffffff;
2071 if (imm_expr
.X_add_number
>= maxnum
)
2073 imm_expr
.X_add_number
++;
2077 if (mask
== M_BLTL_I
)
2079 if (imm_expr
.X_add_number
== 0)
2081 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2082 likely
? "bltzl" : "bltz",
2086 if (imm_expr
.X_add_number
== 1)
2088 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2089 likely
? "blezl" : "blez",
2093 set_at (&icnt
, sreg
, 0);
2094 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2095 likely
? "bnel" : "bne",
2104 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2105 likely
? "beql" : "beq",
2111 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2113 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2114 likely
? "beql" : "beq",
2121 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2123 imm_expr
.X_add_number
++;
2127 if (mask
== M_BLTUL_I
)
2129 if (imm_expr
.X_add_number
== 0)
2131 if (imm_expr
.X_add_number
== 1)
2133 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2134 likely
? "beql" : "beq",
2138 set_at (&icnt
, sreg
, 1);
2139 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2140 likely
? "bnel" : "bne",
2149 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2150 likely
? "bltzl" : "bltz",
2156 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2157 likely
? "bgtzl" : "bgtz",
2161 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2162 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2163 likely
? "bnel" : "bne",
2174 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2175 likely
? "bnel" : "bne",
2179 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2181 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2182 likely
? "bnel" : "bne",
2198 as_warn ("Divide by zero.");
2200 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2202 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2206 mips_emit_delays ();
2208 mips_any_noreorder
= 1;
2209 macro_build ((char *) NULL
, &icnt
, NULL
,
2210 dbl
? "ddiv" : "div",
2211 "z,s,t", sreg
, treg
);
2213 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2216 expr1
.X_add_number
= 8;
2217 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2218 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2219 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2221 expr1
.X_add_number
= -1;
2222 macro_build ((char *) NULL
, &icnt
, &expr1
,
2223 dbl
? "daddiu" : "addiu",
2224 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2225 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2226 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2229 expr1
.X_add_number
= 1;
2230 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2231 (int) BFD_RELOC_LO16
);
2232 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2237 expr1
.X_add_number
= 0x80000000;
2238 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2239 (int) BFD_RELOC_HI16
);
2242 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2245 expr1
.X_add_number
= 8;
2246 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2247 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2248 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2251 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2290 if (imm_expr
.X_add_number
== 0)
2292 as_warn ("Divide by zero.");
2294 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2296 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2299 if (imm_expr
.X_add_number
== 1)
2301 if (strcmp (s2
, "mflo") == 0)
2302 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2305 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2308 if (imm_expr
.X_add_number
== -1
2309 && s
[strlen (s
) - 1] != 'u')
2311 if (strcmp (s2
, "mflo") == 0)
2314 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2317 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2321 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2325 load_register (&icnt
, AT
, &imm_expr
);
2326 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2327 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2346 mips_emit_delays ();
2348 mips_any_noreorder
= 1;
2349 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2351 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2354 expr1
.X_add_number
= 8;
2355 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2356 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2357 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2360 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2364 /* Load the address of a symbol into a register. If breg is not
2365 zero, we then add a base register to it. */
2367 /* When generating embedded PIC code, we permit expressions of
2370 where bar is an address in the .text section. These are used
2371 when getting the addresses of functions. We don't permit
2372 X_add_number to be non-zero, because if the symbol is
2373 external the relaxing code needs to know that any addend is
2374 purely the offset to X_op_symbol. */
2375 if (mips_pic
== EMBEDDED_PIC
2376 && offset_expr
.X_op
== O_subtract
2377 && now_seg
== text_section
2378 && S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2380 && offset_expr
.X_add_number
== 0)
2382 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2383 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2384 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2385 mips_isa
< 3 ? "addiu" : "daddiu",
2386 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2390 if (offset_expr
.X_op
!= O_symbol
2391 && offset_expr
.X_op
!= O_constant
)
2393 as_bad ("expression too complex");
2394 offset_expr
.X_op
= O_constant
;
2408 if (offset_expr
.X_op
== O_constant
)
2409 load_register (&icnt
, tempreg
, &offset_expr
);
2410 else if (mips_pic
== NO_PIC
)
2412 /* If this is a reference to an GP relative symbol, we want
2413 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2415 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2416 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2417 If we have a constant, we need two instructions anyhow,
2418 so we may as well always use the latter form. */
2419 if (offset_expr
.X_add_number
!= 0)
2424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2425 mips_isa
< 3 ? "addiu" : "daddiu",
2426 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2427 p
= frag_var (rs_machine_dependent
, 8, 0,
2428 RELAX_ENCODE (4, 8, 0, 4, 0,
2429 mips_warn_about_macros
),
2430 offset_expr
.X_add_symbol
, (long) 0,
2433 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2436 macro_build (p
, &icnt
, &offset_expr
,
2437 mips_isa
< 3 ? "addiu" : "daddiu",
2438 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2440 else if (mips_pic
== SVR4_PIC
)
2442 /* If this is a reference to an external symbol, and there
2443 is no constant, we want
2444 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2445 For a local symbol, we want
2446 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2448 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2450 If we have a small constant, and this is a reference to
2451 an external symbol, we want
2452 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2454 addiu $tempreg,$tempreg,<constant>
2455 For a local symbol, we want the same instruction
2456 sequence, but we output a BFD_RELOC_LO16 reloc on the
2459 If we have a large constant, and this is a reference to
2460 an external symbol, we want
2461 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2462 lui $at,<hiconstant>
2463 addiu $at,$at,<loconstant>
2464 addu $tempreg,$tempreg,$at
2465 For a local symbol, we want the same instruction
2466 sequence, but we output a BFD_RELOC_LO16 reloc on the
2467 addiu instruction. */
2468 expr1
.X_add_number
= offset_expr
.X_add_number
;
2469 offset_expr
.X_add_number
= 0;
2471 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2472 mips_isa
< 3 ? "lw" : "ld",
2473 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2474 if (expr1
.X_add_number
== 0)
2482 /* We're going to put in an addu instruction using
2483 tempreg, so we may as well insert the nop right
2485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2489 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2490 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2492 ? mips_warn_about_macros
2494 offset_expr
.X_add_symbol
, (long) 0,
2498 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2501 macro_build (p
, &icnt
, &expr1
,
2502 mips_isa
< 3 ? "addiu" : "daddiu",
2503 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2504 /* FIXME: If breg == 0, and the next instruction uses
2505 $tempreg, then if this variant case is used an extra
2506 nop will be generated. */
2508 else if (expr1
.X_add_number
>= -0x8000
2509 && expr1
.X_add_number
< 0x8000)
2511 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2513 macro_build ((char *) NULL
, &icnt
, &expr1
,
2514 mips_isa
< 3 ? "addiu" : "daddiu",
2515 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2516 (void) frag_var (rs_machine_dependent
, 0, 0,
2517 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2518 offset_expr
.X_add_symbol
, (long) 0,
2525 /* If we are going to add in a base register, and the
2526 target register and the base register are the same,
2527 then we are using AT as a temporary register. Since
2528 we want to load the constant into AT, we add our
2529 current AT (from the global offset table) and the
2530 register into the register now, and pretend we were
2531 not using a base register. */
2536 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2538 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2539 mips_isa
< 3 ? "addu" : "daddu",
2540 "d,v,t", treg
, AT
, breg
);
2546 /* Set mips_optimize around the lui instruction to avoid
2547 inserting an unnecessary nop after the lw. */
2548 hold_mips_optimize
= mips_optimize
;
2550 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2551 mips_optimize
= hold_mips_optimize
;
2553 macro_build ((char *) NULL
, &icnt
, &expr1
,
2554 mips_isa
< 3 ? "addiu" : "daddiu",
2555 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2556 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2557 mips_isa
< 3 ? "addu" : "daddu",
2558 "d,v,t", tempreg
, tempreg
, AT
);
2559 (void) frag_var (rs_machine_dependent
, 0, 0,
2560 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2561 offset_expr
.X_add_symbol
, (long) 0,
2566 else if (mips_pic
== EMBEDDED_PIC
)
2569 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2571 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2572 mips_isa
< 3 ? "addiu" : "daddiu",
2573 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2579 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2580 mips_isa
< 3 ? "addu" : "daddu",
2581 "d,v,t", treg
, tempreg
, breg
);
2589 /* The j instruction may not be used in PIC code, since it
2590 requires an absolute address. We convert it to a b
2592 if (mips_pic
== NO_PIC
)
2593 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2595 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2598 /* The jal instructions must be handled as macros because when
2599 generating PIC code they expand to multi-instruction
2600 sequences. Normally they are simple instructions. */
2605 if (mips_pic
== NO_PIC
2606 || mips_pic
== EMBEDDED_PIC
)
2607 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2609 else if (mips_pic
== SVR4_PIC
)
2611 if (sreg
!= PIC_CALL_REG
)
2612 as_warn ("MIPS PIC call to register other than $25");
2614 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2616 if (mips_cprestore_offset
< 0)
2617 as_warn ("No .cprestore pseudo-op used in PIC code");
2620 expr1
.X_add_number
= mips_cprestore_offset
;
2621 macro_build ((char *) NULL
, &icnt
, &expr1
,
2622 mips_isa
< 3 ? "lw" : "ld",
2623 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2632 if (mips_pic
== NO_PIC
)
2633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2634 else if (mips_pic
== SVR4_PIC
)
2636 /* If this is a reference to an external symbol, we want
2637 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2641 lw $gp,cprestore($sp)
2642 The cprestore value is set using the .cprestore
2643 pseudo-op. If the symbol is not external, we want
2644 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2646 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2649 lw $gp,cprestore($sp)
2652 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2653 mips_isa
< 3 ? "lw" : "ld",
2654 "t,o(b)", PIC_CALL_REG
,
2655 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2656 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2657 p
= frag_var (rs_machine_dependent
, 4, 0,
2658 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2659 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2660 macro_build (p
, &icnt
, &offset_expr
,
2661 mips_isa
< 3 ? "addiu" : "daddiu",
2662 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2663 (int) BFD_RELOC_LO16
);
2664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2665 "jalr", "s", PIC_CALL_REG
);
2666 if (mips_cprestore_offset
< 0)
2667 as_warn ("No .cprestore pseudo-op used in PIC code");
2671 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2673 expr1
.X_add_number
= mips_cprestore_offset
;
2674 macro_build ((char *) NULL
, &icnt
, &expr1
,
2675 mips_isa
< 3 ? "lw" : "ld",
2676 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2680 else if (mips_pic
== EMBEDDED_PIC
)
2682 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2683 /* The linker may expand the call to a longer sequence which
2684 uses $at, so we must break rather than return. */
2756 if (breg
== treg
|| coproc
)
2825 if (mask
== M_LWC1_AB
2826 || mask
== M_SWC1_AB
2827 || mask
== M_LDC1_AB
2828 || mask
== M_SDC1_AB
2837 if (offset_expr
.X_op
!= O_constant
2838 && offset_expr
.X_op
!= O_symbol
)
2840 as_bad ("expression too complex");
2841 offset_expr
.X_op
= O_constant
;
2844 /* A constant expression in PIC code can be handled just as it
2845 is in non PIC code. */
2846 if (mips_pic
== NO_PIC
2847 || offset_expr
.X_op
== O_constant
)
2849 /* If this is a reference to a GP relative symbol, and there
2850 is no base register, we want
2851 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2852 Otherwise, if there is no base register, we want
2853 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2854 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2855 If we have a constant, we need two instructions anyhow,
2856 so we always use the latter form.
2858 If we have a base register, and this is a reference to a
2859 GP relative symbol, we want
2860 addu $tempreg,$breg,$gp
2861 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2863 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2864 addu $tempreg,$tempreg,$breg
2865 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2866 With a constant we always use the latter case. */
2869 if (offset_expr
.X_add_number
!= 0)
2874 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2875 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2876 p
= frag_var (rs_machine_dependent
, 8, 0,
2877 RELAX_ENCODE (4, 8, 0, 4, 0,
2878 (mips_warn_about_macros
2879 || (used_at
&& mips_noat
))),
2880 offset_expr
.X_add_symbol
, (long) 0,
2884 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2887 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2888 (int) BFD_RELOC_LO16
, tempreg
);
2892 if (offset_expr
.X_add_number
!= 0)
2897 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2898 mips_isa
< 3 ? "addu" : "daddu",
2899 "d,v,t", tempreg
, breg
, GP
);
2900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2901 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2902 p
= frag_var (rs_machine_dependent
, 12, 0,
2903 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2904 offset_expr
.X_add_symbol
, (long) 0,
2907 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2910 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2911 mips_isa
< 3 ? "addu" : "daddu",
2912 "d,v,t", tempreg
, tempreg
, breg
);
2915 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2916 (int) BFD_RELOC_LO16
, tempreg
);
2919 else if (mips_pic
== SVR4_PIC
)
2921 /* If this is a reference to an external symbol, we want
2922 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2924 <op> $treg,0($tempreg)
2926 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2928 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2929 <op> $treg,0($tempreg)
2930 If there is a base register, we add it to $tempreg before
2931 the <op>. If there is a constant, we stick it in the
2932 <op> instruction. We don't handle constants larger than
2933 16 bits, because we have no way to load the upper 16 bits
2934 (actually, we could handle them for the subset of cases
2935 in which we are not using $at). */
2936 assert (offset_expr
.X_op
== O_symbol
);
2937 expr1
.X_add_number
= offset_expr
.X_add_number
;
2938 offset_expr
.X_add_number
= 0;
2939 if (expr1
.X_add_number
< -0x8000
2940 || expr1
.X_add_number
>= 0x8000)
2941 as_bad ("PIC code offset overflow (max 16 signed bits)");
2943 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2944 mips_isa
< 3 ? "lw" : "ld",
2945 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2946 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2947 p
= frag_var (rs_machine_dependent
, 4, 0,
2948 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2949 offset_expr
.X_add_symbol
, (long) 0,
2951 macro_build (p
, &icnt
, &offset_expr
,
2952 mips_isa
< 3 ? "addiu" : "daddiu",
2953 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2955 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2956 mips_isa
< 3 ? "addu" : "daddu",
2957 "d,v,t", tempreg
, tempreg
, breg
);
2958 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2959 (int) BFD_RELOC_LO16
, tempreg
);
2961 else if (mips_pic
== EMBEDDED_PIC
)
2963 /* If there is no base register, we want
2964 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2965 If there is a base register, we want
2966 addu $tempreg,$breg,$gp
2967 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2969 assert (offset_expr
.X_op
== O_symbol
);
2972 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2973 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2978 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2979 mips_isa
< 3 ? "addu" : "daddu",
2980 "d,v,t", tempreg
, breg
, GP
);
2981 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2982 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2995 load_register (&icnt
, treg
, &imm_expr
);
2999 if (imm_expr
.X_op
== O_constant
)
3001 load_register (&icnt
, AT
, &imm_expr
);
3002 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3003 "mtc1", "t,G", AT
, treg
);
3008 assert (offset_expr
.X_op
== O_symbol
3009 && strcmp (segment_name (S_GET_SEGMENT
3010 (offset_expr
.X_add_symbol
)),
3012 && offset_expr
.X_add_number
== 0);
3013 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3014 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3019 /* We know that sym is in the .rdata section. First we get the
3020 upper 16 bits of the address. */
3021 if (mips_pic
== NO_PIC
)
3023 /* FIXME: This won't work for a 64 bit address. */
3024 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3026 else if (mips_pic
== SVR4_PIC
)
3028 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3029 mips_isa
< 3 ? "lw" : "ld",
3030 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3032 else if (mips_pic
== EMBEDDED_PIC
)
3034 /* For embedded PIC we pick up the entire address off $gp in
3035 a single instruction. */
3036 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3037 mips_isa
< 3 ? "addiu" : "daddiu",
3038 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3039 offset_expr
.X_op
= O_constant
;
3040 offset_expr
.X_add_number
= 0;
3045 /* Now we load the register(s). */
3047 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3048 treg
, (int) BFD_RELOC_LO16
, AT
);
3051 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3052 treg
, (int) BFD_RELOC_LO16
, AT
);
3055 /* FIXME: How in the world do we deal with the possible
3057 offset_expr
.X_add_number
+= 4;
3058 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3059 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3063 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3064 does not become a variant frag. */
3065 frag_wane (frag_now
);
3071 assert (offset_expr
.X_op
== O_symbol
3072 && offset_expr
.X_add_number
== 0);
3073 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3074 if (strcmp (s
, ".lit8") == 0)
3078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3079 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3083 r
= BFD_RELOC_MIPS_LITERAL
;
3088 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3089 if (mips_pic
== SVR4_PIC
)
3090 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3091 mips_isa
< 3 ? "lw" : "ld",
3092 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3095 /* FIXME: This won't work for a 64 bit address. */
3096 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3101 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3102 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3111 /* Even on a big endian machine $fn comes before $fn+1. We have
3112 to adjust when loading from memory. */
3115 assert (mips_isa
< 2);
3116 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3117 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3119 /* FIXME: A possible overflow which I don't know how to deal
3121 offset_expr
.X_add_number
+= 4;
3122 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3123 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3126 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3127 does not become a variant frag. */
3128 frag_wane (frag_now
);
3137 * The MIPS assembler seems to check for X_add_number not
3138 * being double aligned and generating:
3141 * addiu at,at,%lo(foo+1)
3144 * But, the resulting address is the same after relocation so why
3145 * generate the extra instruction?
3192 if (offset_expr
.X_op
!= O_symbol
3193 && offset_expr
.X_op
!= O_constant
)
3195 as_bad ("expression too complex");
3196 offset_expr
.X_op
= O_constant
;
3199 /* Even on a big endian machine $fn comes before $fn+1. We have
3200 to adjust when loading from memory. We set coproc if we must
3201 load $fn+1 first. */
3202 if (byte_order
== LITTLE_ENDIAN
)
3205 if (mips_pic
== NO_PIC
3206 || offset_expr
.X_op
== O_constant
)
3208 /* If this is a reference to a GP relative symbol, we want
3209 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3210 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3211 If we have a base register, we use this
3213 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3214 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3215 If this is not a GP relative symbol, we want
3216 lui $at,<sym> (BFD_RELOC_HI16_S)
3217 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3218 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3219 If there is a base register, we add it to $at after the
3220 lui instruction. If there is a constant, we always use
3222 if (offset_expr
.X_add_number
!= 0)
3241 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3242 mips_isa
< 3 ? "addu" : "daddu",
3243 "d,v,t", AT
, breg
, GP
);
3249 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3250 coproc
? treg
+ 1 : treg
,
3251 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3252 offset_expr
.X_add_number
+= 4;
3254 /* Set mips_optimize to 2 to avoid inserting an
3256 hold_mips_optimize
= mips_optimize
;
3258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3259 coproc
? treg
: treg
+ 1,
3260 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3261 mips_optimize
= hold_mips_optimize
;
3263 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3264 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3265 used_at
&& mips_noat
),
3266 offset_expr
.X_add_symbol
, (long) 0,
3269 /* We just generated two relocs. When tc_gen_reloc
3270 handles this case, it will skip the first reloc and
3271 handle the second. The second reloc already has an
3272 extra addend of 4, which we added above. We must
3273 subtract it out, and then subtract another 4 to make
3274 the first reloc come out right. The second reloc
3275 will come out right because we are going to add 4 to
3276 offset_expr when we build its instruction below. */
3277 offset_expr
.X_add_number
-= 8;
3278 offset_expr
.X_op
= O_constant
;
3280 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3285 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3286 mips_isa
< 3 ? "addu" : "daddu",
3287 "d,v,t", AT
, breg
, AT
);
3291 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3292 coproc
? treg
+ 1 : treg
,
3293 (int) BFD_RELOC_LO16
, AT
);
3296 /* FIXME: How do we handle overflow here? */
3297 offset_expr
.X_add_number
+= 4;
3298 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3299 coproc
? treg
: treg
+ 1,
3300 (int) BFD_RELOC_LO16
, AT
);
3302 else if (mips_pic
== SVR4_PIC
)
3306 /* If this is a reference to an external symbol, we want
3307 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3312 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3314 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3315 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3316 If there is a base register we add it to $at before the
3317 lwc1 instructions. If there is a constant we include it
3318 in the lwc1 instructions. */
3320 expr1
.X_add_number
= offset_expr
.X_add_number
;
3321 offset_expr
.X_add_number
= 0;
3322 if (expr1
.X_add_number
< -0x8000
3323 || expr1
.X_add_number
>= 0x8000 - 4)
3324 as_bad ("PIC code offset overflow (max 16 signed bits)");
3329 frag_grow (24 + off
);
3330 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3331 mips_isa
< 3 ? "lw" : "ld",
3332 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3333 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3335 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3336 mips_isa
< 3 ? "addu" : "daddu",
3337 "d,v,t", AT
, breg
, AT
);
3338 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3339 coproc
? treg
+ 1 : treg
,
3340 (int) BFD_RELOC_LO16
, AT
);
3341 expr1
.X_add_number
+= 4;
3343 /* Set mips_optimize to 2 to avoid inserting an undesired
3345 hold_mips_optimize
= mips_optimize
;
3347 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3348 coproc
? treg
: treg
+ 1,
3349 (int) BFD_RELOC_LO16
, AT
);
3350 mips_optimize
= hold_mips_optimize
;
3352 (void) frag_var (rs_machine_dependent
, 0, 0,
3353 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3354 offset_expr
.X_add_symbol
, (long) 0,
3357 else if (mips_pic
== EMBEDDED_PIC
)
3359 /* If there is no base register, we use
3360 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3361 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3362 If we have a base register, we use
3364 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3365 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3374 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3375 mips_isa
< 3 ? "addu" : "daddu",
3376 "d,v,t", AT
, breg
, GP
);
3381 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3382 coproc
? treg
+ 1 : treg
,
3383 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3384 offset_expr
.X_add_number
+= 4;
3385 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3386 coproc
? treg
: treg
+ 1,
3387 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3403 assert (mips_isa
< 3);
3404 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3405 (int) BFD_RELOC_LO16
, breg
);
3406 offset_expr
.X_add_number
+= 4;
3407 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3408 (int) BFD_RELOC_LO16
, breg
);
3410 #ifdef LOSING_COMPILER
3416 as_warn ("Macro used $at after \".set noat\"");
3421 struct mips_cl_insn
*ip
;
3423 register int treg
, sreg
, dreg
, breg
;
3436 bfd_reloc_code_real_type r
;
3439 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3440 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3441 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3442 mask
= ip
->insn_mo
->mask
;
3444 expr1
.X_op
= O_constant
;
3445 expr1
.X_op_symbol
= NULL
;
3446 expr1
.X_add_symbol
= NULL
;
3447 expr1
.X_add_number
= 1;
3451 #endif /* LOSING_COMPILER */
3456 macro_build ((char *) NULL
, &icnt
, NULL
,
3457 dbl
? "dmultu" : "multu",
3459 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3465 /* The MIPS assembler some times generates shifts and adds. I'm
3466 not trying to be that fancy. GCC should do this for us
3468 load_register (&icnt
, AT
, &imm_expr
);
3469 macro_build ((char *) NULL
, &icnt
, NULL
,
3470 dbl
? "dmult" : "mult",
3472 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3478 mips_emit_delays ();
3480 mips_any_noreorder
= 1;
3481 macro_build ((char *) NULL
, &icnt
, NULL
,
3482 dbl
? "dmult" : "mult",
3484 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3485 macro_build ((char *) NULL
, &icnt
, NULL
,
3486 dbl
? "dsra32" : "sra",
3487 "d,w,<", dreg
, dreg
, 31);
3488 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3490 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3493 expr1
.X_add_number
= 8;
3494 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3495 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3496 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3499 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3505 mips_emit_delays ();
3507 mips_any_noreorder
= 1;
3508 macro_build ((char *) NULL
, &icnt
, NULL
,
3509 dbl
? "dmultu" : "multu",
3511 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3512 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3514 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3517 expr1
.X_add_number
= 8;
3518 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3519 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3520 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3526 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3527 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3528 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3530 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3534 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3535 imm_expr
.X_add_number
& 0x1f);
3536 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3537 (0 - imm_expr
.X_add_number
) & 0x1f);
3538 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3542 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3543 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3544 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3546 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3550 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3551 imm_expr
.X_add_number
& 0x1f);
3552 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3553 (0 - imm_expr
.X_add_number
) & 0x1f);
3554 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3558 assert (mips_isa
< 2);
3559 /* Even on a big endian machine $fn comes before $fn+1. We have
3560 to adjust when storing to memory. */
3561 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3562 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3563 (int) BFD_RELOC_LO16
, breg
);
3564 offset_expr
.X_add_number
+= 4;
3565 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3566 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3567 (int) BFD_RELOC_LO16
, breg
);
3572 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3573 treg
, (int) BFD_RELOC_LO16
);
3575 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3576 sreg
, (int) BFD_RELOC_LO16
);
3579 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3581 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3582 dreg
, (int) BFD_RELOC_LO16
);
3587 if (imm_expr
.X_add_number
== 0)
3589 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3590 sreg
, (int) BFD_RELOC_LO16
);
3595 as_warn ("Instruction %s: result is always false",
3597 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3600 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3602 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3603 sreg
, (int) BFD_RELOC_LO16
);
3606 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3608 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3609 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3610 mips_isa
< 3 ? "addiu" : "daddiu",
3611 "t,r,j", dreg
, sreg
,
3612 (int) BFD_RELOC_LO16
);
3617 load_register (&icnt
, AT
, &imm_expr
);
3618 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3622 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3623 (int) BFD_RELOC_LO16
);
3628 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3634 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3635 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3636 (int) BFD_RELOC_LO16
);
3639 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3641 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3643 macro_build ((char *) NULL
, &icnt
, &expr1
,
3644 mask
== M_SGE_I
? "slti" : "sltiu",
3645 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3650 load_register (&icnt
, AT
, &imm_expr
);
3651 macro_build ((char *) NULL
, &icnt
, NULL
,
3652 mask
== M_SGE_I
? "slt" : "sltu",
3653 "d,v,t", dreg
, sreg
, AT
);
3656 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3657 (int) BFD_RELOC_LO16
);
3662 case M_SGT
: /* sreg > treg <==> treg < sreg */
3668 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3671 case M_SGT_I
: /* sreg > I <==> I < sreg */
3677 load_register (&icnt
, AT
, &imm_expr
);
3678 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3681 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3687 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3688 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3689 (int) BFD_RELOC_LO16
);
3692 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3698 load_register (&icnt
, AT
, &imm_expr
);
3699 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3700 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3701 (int) BFD_RELOC_LO16
);
3705 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3707 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3708 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3711 load_register (&icnt
, AT
, &imm_expr
);
3712 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3716 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3718 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3719 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3722 load_register (&icnt
, AT
, &imm_expr
);
3723 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3729 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3732 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3736 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3738 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3744 if (imm_expr
.X_add_number
== 0)
3746 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3752 as_warn ("Instruction %s: result is always true",
3754 macro_build ((char *) NULL
, &icnt
, &expr1
,
3755 mips_isa
< 3 ? "addiu" : "daddiu",
3756 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3759 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3761 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3762 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3765 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3767 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3768 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3769 mips_isa
< 3 ? "addiu" : "daddiu",
3770 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3775 load_register (&icnt
, AT
, &imm_expr
);
3776 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3780 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3788 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3790 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3791 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3792 dbl
? "daddi" : "addi",
3793 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3796 load_register (&icnt
, AT
, &imm_expr
);
3797 macro_build ((char *) NULL
, &icnt
, NULL
,
3798 dbl
? "dsub" : "sub",
3799 "d,v,t", dreg
, sreg
, AT
);
3805 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3807 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3808 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3809 dbl
? "daddiu" : "addiu",
3810 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3813 load_register (&icnt
, AT
, &imm_expr
);
3814 macro_build ((char *) NULL
, &icnt
, NULL
,
3815 dbl
? "dsubu" : "subu",
3816 "d,v,t", dreg
, sreg
, AT
);
3837 load_register (&icnt
, AT
, &imm_expr
);
3838 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3843 assert (mips_isa
< 2);
3844 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3845 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3848 * Is the double cfc1 instruction a bug in the mips assembler;
3849 * or is there a reason for it?
3851 mips_emit_delays ();
3853 mips_any_noreorder
= 1;
3854 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3855 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3856 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3857 expr1
.X_add_number
= 3;
3858 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3859 (int) BFD_RELOC_LO16
);
3860 expr1
.X_add_number
= 2;
3861 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3862 (int) BFD_RELOC_LO16
);
3863 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3864 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3865 macro_build ((char *) NULL
, &icnt
, NULL
,
3866 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3867 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3868 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3878 if (offset_expr
.X_add_number
>= 0x7fff)
3879 as_bad ("operand overflow");
3880 /* avoid load delay */
3881 if (byte_order
== LITTLE_ENDIAN
)
3882 offset_expr
.X_add_number
+= 1;
3883 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3884 (int) BFD_RELOC_LO16
, breg
);
3885 if (byte_order
== LITTLE_ENDIAN
)
3886 offset_expr
.X_add_number
-= 1;
3888 offset_expr
.X_add_number
+= 1;
3889 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3890 (int) BFD_RELOC_LO16
, breg
);
3891 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3892 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3896 if (offset_expr
.X_add_number
>= 0x7ffd)
3897 as_bad ("operand overflow");
3898 if (byte_order
== LITTLE_ENDIAN
)
3899 offset_expr
.X_add_number
+= 3;
3900 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3901 (int) BFD_RELOC_LO16
, breg
);
3902 if (byte_order
== LITTLE_ENDIAN
)
3903 offset_expr
.X_add_number
-= 3;
3905 offset_expr
.X_add_number
+= 3;
3906 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3907 (int) BFD_RELOC_LO16
, breg
);
3913 load_address (&icnt
, AT
, &offset_expr
);
3914 if (mask
== M_ULW_A
)
3916 if (byte_order
== LITTLE_ENDIAN
)
3917 expr1
.X_add_number
= 3;
3919 expr1
.X_add_number
= 0;
3920 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3921 (int) BFD_RELOC_LO16
, AT
);
3922 if (byte_order
== LITTLE_ENDIAN
)
3923 expr1
.X_add_number
= 0;
3925 expr1
.X_add_number
= 3;
3926 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3927 (int) BFD_RELOC_LO16
, AT
);
3931 if (byte_order
== BIG_ENDIAN
)
3932 expr1
.X_add_number
= 0;
3933 macro_build ((char *) NULL
, &icnt
, &expr1
,
3934 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3935 (int) BFD_RELOC_LO16
, AT
);
3936 if (byte_order
== BIG_ENDIAN
)
3937 expr1
.X_add_number
= 1;
3939 expr1
.X_add_number
= 0;
3940 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3941 (int) BFD_RELOC_LO16
, AT
);
3942 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3944 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3950 if (offset_expr
.X_add_number
>= 0x7fff)
3951 as_bad ("operand overflow");
3952 if (byte_order
== BIG_ENDIAN
)
3953 offset_expr
.X_add_number
+= 1;
3954 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3955 (int) BFD_RELOC_LO16
, breg
);
3956 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3957 if (byte_order
== BIG_ENDIAN
)
3958 offset_expr
.X_add_number
-= 1;
3960 offset_expr
.X_add_number
+= 1;
3961 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3962 (int) BFD_RELOC_LO16
, breg
);
3966 if (offset_expr
.X_add_number
>= 0x7ffd)
3967 as_bad ("operand overflow");
3968 if (byte_order
== LITTLE_ENDIAN
)
3969 offset_expr
.X_add_number
+= 3;
3970 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3971 (int) BFD_RELOC_LO16
, breg
);
3972 if (byte_order
== LITTLE_ENDIAN
)
3973 offset_expr
.X_add_number
-= 3;
3975 offset_expr
.X_add_number
+= 3;
3976 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3977 (int) BFD_RELOC_LO16
, breg
);
3982 load_address (&icnt
, AT
, &offset_expr
);
3983 if (mask
== M_USW_A
)
3985 if (byte_order
== LITTLE_ENDIAN
)
3986 expr1
.X_add_number
= 3;
3988 expr1
.X_add_number
= 0;
3989 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3990 (int) BFD_RELOC_LO16
, AT
);
3991 if (byte_order
== LITTLE_ENDIAN
)
3992 expr1
.X_add_number
= 0;
3994 expr1
.X_add_number
= 3;
3995 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3996 (int) BFD_RELOC_LO16
, AT
);
4000 if (byte_order
== LITTLE_ENDIAN
)
4001 expr1
.X_add_number
= 0;
4002 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4003 (int) BFD_RELOC_LO16
, AT
);
4004 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4006 if (byte_order
== LITTLE_ENDIAN
)
4007 expr1
.X_add_number
= 1;
4009 expr1
.X_add_number
= 0;
4010 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4011 (int) BFD_RELOC_LO16
, AT
);
4012 if (byte_order
== LITTLE_ENDIAN
)
4013 expr1
.X_add_number
= 0;
4015 expr1
.X_add_number
= 1;
4016 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4017 (int) BFD_RELOC_LO16
, AT
);
4018 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4020 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4026 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4030 as_warn ("Macro used $at after \".set noat\"");
4035 This routine assembles an instruction into its binary format. As a side
4036 effect it sets one of the global variables imm_reloc or offset_reloc to the
4037 type of relocation to do if one of the operands is an address expression.
4042 struct mips_cl_insn
*ip
;
4047 struct mips_opcode
*insn
;
4050 unsigned int lastregno
= 0;
4055 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4067 as_warn ("Unknown opcode: `%s'", str
);
4070 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4072 as_warn ("`%s' not in hash table.", str
);
4073 insn_error
= "ERROR: Unrecognized opcode";
4081 assert (strcmp (insn
->name
, str
) == 0);
4083 if (insn
->pinfo
== INSN_MACRO
)
4084 insn_isa
= insn
->match
;
4085 else if (insn
->pinfo
& INSN_ISA2
)
4087 else if (insn
->pinfo
& INSN_ISA3
)
4092 if (insn_isa
> mips_isa
)
4094 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4095 && strcmp (insn
->name
, insn
[1].name
) == 0)
4100 as_warn ("Instruction not supported on this processor");
4104 ip
->insn_opcode
= insn
->match
;
4105 for (args
= insn
->args
;; ++args
)
4111 case '\0': /* end of args */
4124 ip
->insn_opcode
|= lastregno
<< 21;
4129 ip
->insn_opcode
|= lastregno
<< 16;
4133 ip
->insn_opcode
|= lastregno
<< 11;
4139 /* handle optional base register.
4140 Either the base register is omitted or
4141 we must have a left paren. */
4142 /* this is dependent on the next operand specifier
4143 is a 'b' for base register */
4144 assert (args
[1] == 'b');
4148 case ')': /* these must match exactly */
4153 case '<': /* must be at least one digit */
4155 * According to the manual, if the shift amount is greater
4156 * than 31 or less than 0 the the shift amount should be
4157 * mod 32. In reality the mips assembler issues an error.
4158 * We issue a warning and mask out all but the low 5 bits.
4160 my_getExpression (&imm_expr
, s
);
4161 check_absolute_expr (ip
, &imm_expr
);
4162 if ((unsigned long) imm_expr
.X_add_number
> 31)
4164 as_warn ("Improper shift amount (%ld)",
4165 (long) imm_expr
.X_add_number
);
4166 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4168 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4169 imm_expr
.X_op
= O_absent
;
4173 case '>': /* shift amount minus 32 */
4174 my_getExpression (&imm_expr
, s
);
4175 check_absolute_expr (ip
, &imm_expr
);
4176 if ((unsigned long) imm_expr
.X_add_number
< 32
4177 || (unsigned long) imm_expr
.X_add_number
> 63)
4179 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4180 imm_expr
.X_op
= O_absent
;
4184 case 'k': /* cache code */
4185 my_getExpression (&imm_expr
, s
);
4186 check_absolute_expr (ip
, &imm_expr
);
4187 if ((unsigned long) imm_expr
.X_add_number
> 31)
4189 as_warn ("Invalid cahce opcode (%lu)",
4190 (unsigned long) imm_expr
.X_add_number
);
4191 imm_expr
.X_add_number
&= 0x1f;
4193 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4194 imm_expr
.X_op
= O_absent
;
4198 case 'c': /* break code */
4199 my_getExpression (&imm_expr
, s
);
4200 check_absolute_expr (ip
, &imm_expr
);
4201 if ((unsigned) imm_expr
.X_add_number
> 1023)
4202 as_warn ("Illegal break code (%ld)",
4203 (long) imm_expr
.X_add_number
);
4204 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4205 imm_expr
.X_op
= O_absent
;
4209 case 'B': /* syscall code */
4210 my_getExpression (&imm_expr
, s
);
4211 check_absolute_expr (ip
, &imm_expr
);
4212 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4213 as_warn ("Illegal syscall code (%ld)",
4214 (long) imm_expr
.X_add_number
);
4215 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4216 imm_expr
.X_op
= O_absent
;
4220 case 'C': /* Coprocessor code */
4221 my_getExpression (&imm_expr
, s
);
4222 check_absolute_expr (ip
, &imm_expr
);
4223 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4225 as_warn ("Coproccesor code > 25 bits (%ld)",
4226 (long) imm_expr
.X_add_number
);
4227 imm_expr
.X_add_number
&= ((1<<25) - 1);
4229 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4230 imm_expr
.X_op
= O_absent
;
4234 case 'b': /* base register */
4235 case 'd': /* destination register */
4236 case 's': /* source register */
4237 case 't': /* target register */
4238 case 'r': /* both target and source */
4239 case 'v': /* both dest and source */
4240 case 'w': /* both dest and target */
4241 case 'E': /* coprocessor target register */
4242 case 'G': /* coprocessor destination register */
4243 case 'x': /* ignore register name */
4244 case 'z': /* must be zero register */
4258 while (isdigit (*s
));
4260 as_bad ("Invalid register number (%d)", regno
);
4262 else if (*args
== 'E' || *args
== 'G')
4266 if (s
[1] == 'f' && s
[2] == 'p')
4271 else if (s
[1] == 's' && s
[2] == 'p')
4276 else if (s
[1] == 'g' && s
[2] == 'p')
4281 else if (s
[1] == 'a' && s
[2] == 't')
4289 if (regno
== AT
&& ! mips_noat
)
4290 as_warn ("Used $at without \".set noat\"");
4296 if (c
== 'r' || c
== 'v' || c
== 'w')
4303 /* 'z' only matches $0. */
4304 if (c
== 'z' && regno
!= 0)
4312 ip
->insn_opcode
|= regno
<< 21;
4316 ip
->insn_opcode
|= regno
<< 11;
4321 ip
->insn_opcode
|= regno
<< 16;
4324 /* This case exists because on the r3000 trunc
4325 expands into a macro which requires a gp
4326 register. On the r6000 or r4000 it is
4327 assembled into a single instruction which
4328 ignores the register. Thus the insn version
4329 is MIPS_ISA2 and uses 'x', and the macro
4330 version is MIPS_ISA1 and uses 't'. */
4333 /* This case is for the div instruction, which
4334 acts differently if the destination argument
4335 is $0. This only matches $0, and is checked
4336 outside the switch. */
4347 ip
->insn_opcode
|= lastregno
<< 21;
4350 ip
->insn_opcode
|= lastregno
<< 16;
4355 case 'D': /* floating point destination register */
4356 case 'S': /* floating point source register */
4357 case 'T': /* floating point target register */
4361 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4371 while (isdigit (*s
));
4374 as_bad ("Invalid float register number (%d)", regno
);
4376 if ((regno
& 1) != 0
4378 && ! (strcmp (str
, "mtc1") == 0 ||
4379 strcmp (str
, "mfc1") == 0 ||
4380 strcmp (str
, "lwc1") == 0 ||
4381 strcmp (str
, "swc1") == 0))
4382 as_warn ("Float register should be even, was %d",
4390 if (c
== 'V' || c
== 'W')
4400 ip
->insn_opcode
|= regno
<< 6;
4404 ip
->insn_opcode
|= regno
<< 11;
4408 ip
->insn_opcode
|= regno
<< 16;
4416 ip
->insn_opcode
|= lastregno
<< 11;
4419 ip
->insn_opcode
|= lastregno
<< 16;
4425 my_getExpression (&imm_expr
, s
);
4426 check_absolute_expr (ip
, &imm_expr
);
4431 my_getExpression (&offset_expr
, s
);
4432 imm_reloc
= BFD_RELOC_32
;
4444 unsigned char temp
[8];
4446 unsigned int length
;
4451 /* These only appear as the last operand in an
4452 instruction, and every instruction that accepts
4453 them in any variant accepts them in all variants.
4454 This means we don't have to worry about backing out
4455 any changes if the instruction does not match.
4457 The difference between them is the size of the
4458 floating point constant and where it goes. For 'F'
4459 and 'L' the constant is 64 bits; for 'f' and 'l' it
4460 is 32 bits. Where the constant is placed is based
4461 on how the MIPS assembler does things:
4464 f -- immediate value
4467 The .lit4 and .lit8 sections are only used if
4468 permitted by the -G argument.
4470 When generating embedded PIC code, we use the
4471 .lit8 section but not the .lit4 section (we can do
4472 .lit4 inline easily; we need to put .lit8
4473 somewhere in the data segment, and using .lit8
4474 permits the linker to eventually combine identical
4477 f64
= *args
== 'F' || *args
== 'L';
4479 save_in
= input_line_pointer
;
4480 input_line_pointer
= s
;
4481 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4483 s
= input_line_pointer
;
4484 input_line_pointer
= save_in
;
4485 if (err
!= NULL
&& *err
!= '\0')
4487 as_bad ("Bad floating point constant: %s", err
);
4488 memset (temp
, '\0', sizeof temp
);
4489 length
= f64
? 8 : 4;
4492 assert (length
== (f64
? 8 : 4));
4496 && (mips_pic
== EMBEDDED_PIC
4498 || g_switch_value
< 4
4502 imm_expr
.X_op
= O_constant
;
4503 if (byte_order
== LITTLE_ENDIAN
)
4504 imm_expr
.X_add_number
=
4505 (((((((int) temp
[3] << 8)
4510 imm_expr
.X_add_number
=
4511 (((((((int) temp
[0] << 8)
4518 const char *newname
;
4521 /* Switch to the right section. */
4523 subseg
= now_subseg
;
4526 default: /* unused default case avoids warnings. */
4530 if (g_switch_value
< 8)
4531 newname
= RDATA_SECTION_NAME
;
4535 newname
= RDATA_SECTION_NAME
;
4539 assert (g_switch_value
>= 4);
4544 new_seg
= subseg_new (newname
, (subsegT
) 0);
4545 frag_align (*args
== 'l' ? 2 : 3, 0);
4547 record_alignment (new_seg
, 4);
4549 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4552 as_bad ("Can't use floating point insn in this section");
4554 /* Set the argument to the current address in the
4556 offset_expr
.X_op
= O_symbol
;
4557 offset_expr
.X_add_symbol
=
4558 symbol_new ("L0\001", now_seg
,
4559 (valueT
) frag_now_fix (), frag_now
);
4560 offset_expr
.X_add_number
= 0;
4562 /* Put the floating point number into the section. */
4563 p
= frag_more ((int) length
);
4564 memcpy (p
, temp
, length
);
4566 /* Switch back to the original section. */
4567 subseg_set (seg
, subseg
);
4572 case 'i': /* 16 bit unsigned immediate */
4573 case 'j': /* 16 bit signed immediate */
4574 imm_reloc
= BFD_RELOC_LO16
;
4575 c
= my_getSmallExpression (&imm_expr
, s
);
4580 if (imm_expr
.X_op
== O_constant
)
4581 imm_expr
.X_add_number
=
4582 (imm_expr
.X_add_number
>> 16) & 0xffff;
4584 imm_reloc
= BFD_RELOC_HI16_S
;
4586 imm_reloc
= BFD_RELOC_HI16
;
4590 check_absolute_expr (ip
, &imm_expr
);
4593 if (imm_expr
.X_add_number
< 0
4594 || imm_expr
.X_add_number
>= 0x10000)
4596 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4597 !strcmp (insn
->name
, insn
[1].name
))
4599 as_bad ("16 bit expression not in range 0..65535");
4607 /* The upper bound should be 0x8000, but
4608 unfortunately the MIPS assembler accepts numbers
4609 from 0x8000 to 0xffff and sign extends them, and
4610 we want to be compatible. We only permit this
4611 extended range for an instruction which does not
4612 provide any further alternates, since those
4613 alternates may handle other cases. People should
4614 use the numbers they mean, rather than relying on
4615 a mysterious sign extension. */
4616 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4617 strcmp (insn
->name
, insn
[1].name
) == 0);
4622 if (imm_expr
.X_add_number
< -0x8000 ||
4623 imm_expr
.X_add_number
>= max
)
4627 as_bad ("16 bit expression not in range -32768..32767");
4633 case 'o': /* 16 bit offset */
4634 c
= my_getSmallExpression (&offset_expr
, s
);
4636 /* If this value won't fit into a 16 bit offset, then go
4637 find a macro that will generate the 32 bit offset
4638 code pattern. As a special hack, we accept the
4639 difference of two local symbols as a constant. This
4640 is required to suppose embedded PIC switches, which
4641 use an instruction which looks like
4642 lw $4,$L12-$LS12($4)
4643 The problem with handling this in a more general
4644 fashion is that the macro function doesn't expect to
4645 see anything which can be handled in a single
4646 constant instruction. */
4648 && (offset_expr
.X_op
!= O_constant
4649 || offset_expr
.X_add_number
>= 0x8000
4650 || offset_expr
.X_add_number
< -0x8000)
4651 && (mips_pic
!= EMBEDDED_PIC
4652 || offset_expr
.X_op
!= O_subtract
4653 || ! S_IS_LOCAL (offset_expr
.X_add_symbol
)
4654 || ! S_IS_LOCAL (offset_expr
.X_op_symbol
)))
4657 offset_reloc
= BFD_RELOC_LO16
;
4658 if (c
== 'h' || c
== 'H')
4660 assert (offset_expr
.X_op
== O_constant
);
4661 offset_expr
.X_add_number
=
4662 (offset_expr
.X_add_number
>> 16) & 0xffff;
4667 case 'p': /* pc relative offset */
4668 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4669 my_getExpression (&offset_expr
, s
);
4673 case 'u': /* upper 16 bits */
4674 c
= my_getSmallExpression (&imm_expr
, s
);
4675 if (imm_expr
.X_op
== O_constant
4676 && (imm_expr
.X_add_number
< 0
4677 || imm_expr
.X_add_number
>= 0x10000))
4678 as_bad ("lui expression not in range 0..65535");
4679 imm_reloc
= BFD_RELOC_LO16
;
4684 if (imm_expr
.X_op
== O_constant
)
4685 imm_expr
.X_add_number
=
4686 (imm_expr
.X_add_number
>> 16) & 0xffff;
4688 imm_reloc
= BFD_RELOC_HI16_S
;
4690 imm_reloc
= BFD_RELOC_HI16
;
4696 case 'a': /* 26 bit address */
4697 my_getExpression (&offset_expr
, s
);
4699 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4703 fprintf (stderr
, "bad char = '%c'\n", *args
);
4708 /* Args don't match. */
4709 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4710 !strcmp (insn
->name
, insn
[1].name
))
4716 insn_error
= "ERROR: Illegal operands";
4725 my_getSmallExpression (ep
, str
)
4736 ((str
[1] == 'h' && str
[2] == 'i')
4737 || (str
[1] == 'H' && str
[2] == 'I')
4738 || (str
[1] == 'l' && str
[2] == 'o'))
4750 * A small expression may be followed by a base register.
4751 * Scan to the end of this operand, and then back over a possible
4752 * base register. Then scan the small expression up to that
4753 * point. (Based on code in sparc.c...)
4755 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4757 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4759 if (isdigit (sp
[-2]))
4761 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4763 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4769 else if (sp
- 5 >= str
4772 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4773 || (sp
[-3] == 's' && sp
[-2] == 'p')
4774 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4775 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4781 /* no expression means zero offset */
4784 /* %xx(reg) is an error */
4785 ep
->X_op
= O_absent
;
4790 ep
->X_op
= O_constant
;
4793 ep
->X_add_symbol
= NULL
;
4794 ep
->X_op_symbol
= NULL
;
4795 ep
->X_add_number
= 0;
4800 my_getExpression (ep
, str
);
4807 my_getExpression (ep
, str
);
4808 return c
; /* => %hi or %lo encountered */
4812 my_getExpression (ep
, str
)
4818 save_in
= input_line_pointer
;
4819 input_line_pointer
= str
;
4821 expr_end
= input_line_pointer
;
4822 input_line_pointer
= save_in
;
4825 /* Turn a string in input_line_pointer into a floating point constant
4826 of type type, and store the appropriate bytes in *litP. The number
4827 of LITTLENUMS emitted is stored in *sizeP . An error message is
4828 returned, or NULL on OK. */
4831 md_atof (type
, litP
, sizeP
)
4837 LITTLENUM_TYPE words
[4];
4853 return "bad call to md_atof";
4856 t
= atof_ieee (input_line_pointer
, type
, words
);
4858 input_line_pointer
= t
;
4862 if (byte_order
== LITTLE_ENDIAN
)
4864 for (i
= prec
- 1; i
>= 0; i
--)
4866 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4872 for (i
= 0; i
< prec
; i
++)
4874 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4883 md_number_to_chars (buf
, val
, n
)
4891 number_to_chars_littleendian (buf
, val
, n
);
4895 number_to_chars_bigendian (buf
, val
, n
);
4904 CONST
char *md_shortopts
= "E:O::g::G:";
4906 CONST
char *md_shortopts
= "E:O::g::";
4908 struct option md_longopts
[] = {
4909 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
4910 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
4911 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
4912 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
4913 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
4914 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
4915 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
4916 #define OPTION_MCPU (OPTION_MD_BASE + 4)
4917 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
4918 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
4919 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
4920 #define OPTION_TRAP (OPTION_MD_BASE + 8)
4921 {"trap", no_argument
, NULL
, OPTION_TRAP
},
4922 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
4923 #define OPTION_BREAK (OPTION_MD_BASE + 9)
4924 {"break", no_argument
, NULL
, OPTION_BREAK
},
4925 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
4928 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
4929 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
4930 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
4931 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
4932 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
4935 {NULL
, no_argument
, NULL
, 0}
4937 size_t md_longopts_size
= sizeof(md_longopts
);
4940 md_parse_option (c
, arg
)
4956 byte_order
= BIG_ENDIAN
;
4957 else if (arg
[1] == 'L')
4958 byte_order
= LITTLE_ENDIAN
;
4961 as_bad("invalid endianness -E%c", arg
[1]);
4967 mips_target_format
= "a.out-mips-big";
4969 mips_target_format
= "a.out-mips-little";
4973 mips_target_format
= "ecoff-bigmips";
4975 mips_target_format
= "ecoff-littlemips";
4979 mips_target_format
= "elf32-bigmips";
4981 mips_target_format
= "elf32-littlemips";
4984 /* FIXME: This breaks -L -EL. */
4985 flag_keep_locals
= 0;
4989 if (arg
&& arg
[1] == '0')
4996 if (arg
== NULL
|| arg
[1] == '2')
5016 /* Identify the processor type */
5018 if (strcmp (p
, "default") == 0
5019 || strcmp (p
, "DEFAULT") == 0)
5023 if (*p
== 'r' || *p
== 'R')
5030 if (strcmp (p
, "2000") == 0
5031 || strcmp (p
, "2k") == 0
5032 || strcmp (p
, "2K") == 0)
5037 if (strcmp (p
, "3000") == 0
5038 || strcmp (p
, "3k") == 0
5039 || strcmp (p
, "3K") == 0)
5044 if (strcmp (p
, "4000") == 0
5045 || strcmp (p
, "4k") == 0
5046 || strcmp (p
, "4K") == 0
5047 || strcmp (p
, "4400") == 0
5048 || strcmp (p
, "4600") == 0)
5053 if (strcmp (p
, "6000") == 0
5054 || strcmp (p
, "6k") == 0
5055 || strcmp (p
, "6K") == 0)
5060 if (strcmp (p
, "orion") == 0)
5067 as_bad ("invalid architecture -mcpu=%s", arg
);
5074 case OPTION_MEMBEDDED_PIC
:
5075 mips_pic
= EMBEDDED_PIC
;
5079 as_bad ("-G may not be used with embedded PIC code");
5082 g_switch_value
= 0x7fffffff;
5087 /* When generating ELF code, we permit -KPIC and -call_shared to
5088 select SVR4_PIC, and -non_shared to select no PIC. This is
5089 intended to be compatible with Irix 5. */
5090 case OPTION_CALL_SHARED
:
5091 mips_pic
= SVR4_PIC
;
5092 if (g_switch_seen
&& g_switch_value
!= 0)
5094 as_bad ("-G may not be used with SVR4 PIC code");
5100 case OPTION_NON_SHARED
:
5103 #endif /* OBJ_ELF */
5107 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5109 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5113 g_switch_value
= atoi (arg
);
5126 md_show_usage (stream
)
5131 -membedded-pic generate embedded position independent code\n\
5132 -EB generate big endian output\n\
5133 -EL generate little endian output\n\
5134 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5135 -G NUM allow referencing objects up to NUM bytes\n\
5136 implicitly with the gp register [default 8]\n");
5138 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5139 -mips2, -mcpu=r6000 generate code for r6000\n\
5140 -mips3, -mcpu=r4000 generate code for r4000\n\
5141 -O0 remove unneeded NOPs, do not swap branches\n\
5142 -O remove unneeded NOPs and swap branches\n\
5143 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5144 --break, --no-trap break exception on div by 0 and mult overflow\n");
5147 -KPIC, -call_shared generate SVR4 position independent code\n\
5148 -non_shared do not generate position independent code\n");
5153 md_pcrel_from (fixP
)
5157 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5158 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5160 /* This makes a branch to an undefined symbol be a branch to the
5161 current location. */
5166 /* return the address of the delay slot */
5167 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5170 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5171 reloc for a cons. We could use the definition there, except that
5172 we want to handle 64 bit relocs specially. */
5175 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5178 unsigned int nbytes
;
5181 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5183 FIXME: There is no way to select anything but 32 bit mode right
5187 if (byte_order
== BIG_ENDIAN
)
5192 if (nbytes
!= 2 && nbytes
!= 4)
5193 as_bad ("Unsupported reloc size %d", nbytes
);
5195 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5196 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5199 /* When generating embedded PIC code we need to use a special
5200 relocation to represent the difference of two symbols in the .text
5201 section (switch tables use a difference of this sort). See
5202 include/coff/mips.h for details. This macro checks whether this
5203 fixup requires the special reloc. */
5204 #define SWITCH_TABLE(fixp) \
5205 ((fixp)->fx_r_type == BFD_RELOC_32 \
5206 && (fixp)->fx_addsy != NULL \
5207 && (fixp)->fx_subsy != NULL \
5208 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5209 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5211 /* When generating embedded PIC code we must keep all PC relative
5212 relocations, in case the linker has to relax a call. We also need
5213 to keep relocations for switch table entries. */
5217 mips_force_relocation (fixp
)
5220 return (mips_pic
== EMBEDDED_PIC
5222 || SWITCH_TABLE (fixp
)
5223 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5224 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5227 /* Apply a fixup to the object file. */
5230 md_apply_fix (fixP
, valueP
)
5237 assert (fixP
->fx_size
== 4);
5240 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5242 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5245 switch (fixP
->fx_r_type
)
5247 case BFD_RELOC_MIPS_JMP
:
5248 case BFD_RELOC_HI16
:
5249 case BFD_RELOC_HI16_S
:
5250 case BFD_RELOC_MIPS_GPREL
:
5251 case BFD_RELOC_MIPS_LITERAL
:
5252 case BFD_RELOC_MIPS_CALL16
:
5253 case BFD_RELOC_MIPS_GOT16
:
5254 case BFD_RELOC_MIPS_GPREL32
:
5256 as_bad ("Invalid PC relative reloc");
5257 /* Nothing needed to do. The value comes from the reloc entry */
5260 case BFD_RELOC_PCREL_HI16_S
:
5261 /* The addend for this is tricky if it is internal, so we just
5262 do everything here rather than in bfd_perform_relocation. */
5263 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5265 /* For an external symbol adjust by the address to make it
5266 pcrel_offset. We use the address of the RELLO reloc
5267 which follows this one. */
5268 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5269 + fixP
->fx_next
->fx_where
);
5274 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5275 if (byte_order
== BIG_ENDIAN
)
5277 md_number_to_chars (buf
, value
, 2);
5280 case BFD_RELOC_PCREL_LO16
:
5281 /* The addend for this is tricky if it is internal, so we just
5282 do everything here rather than in bfd_perform_relocation. */
5283 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5284 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5285 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5286 if (byte_order
== BIG_ENDIAN
)
5288 md_number_to_chars (buf
, value
, 2);
5292 /* If we are deleting this reloc entry, we must fill in the
5293 value now. This can happen if we have a .word which is not
5294 resolved when it appears but is later defined. We also need
5295 to fill in the value if this is an embedded PIC switch table
5298 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5299 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5303 case BFD_RELOC_LO16
:
5304 /* When handling an embedded PIC switch statement, we can wind
5305 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5308 if (value
< -0x8000 || value
> 0x7fff)
5309 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5310 "relocation overflow");
5311 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5312 if (byte_order
== BIG_ENDIAN
)
5314 md_number_to_chars (buf
, value
, 2);
5318 case BFD_RELOC_16_PCREL_S2
:
5320 * We need to save the bits in the instruction since fixup_segment()
5321 * might be deleting the relocation entry (i.e., a branch within
5322 * the current segment).
5325 as_warn ("Branch to odd address (%lx)", value
);
5327 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
5328 as_bad ("Relocation overflow");
5330 /* update old instruction data */
5331 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5335 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5339 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5346 insn
|= value
& 0xFFFF;
5347 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5362 const struct mips_opcode
*p
;
5363 int treg
, sreg
, dreg
, shamt
;
5368 for (i
= 0; i
< NUMOPCODES
; ++i
)
5370 p
= &mips_opcodes
[i
];
5371 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5373 printf ("%08lx %s\t", oc
, p
->name
);
5374 treg
= (oc
>> 16) & 0x1f;
5375 sreg
= (oc
>> 21) & 0x1f;
5376 dreg
= (oc
>> 11) & 0x1f;
5377 shamt
= (oc
>> 6) & 0x1f;
5379 for (args
= p
->args
;; ++args
)
5390 printf ("%c", *args
);
5394 assert (treg
== sreg
);
5395 printf ("$%d,$%d", treg
, sreg
);
5400 printf ("$%d", dreg
);
5405 printf ("$%d", treg
);
5409 printf ("0x%x", treg
);
5414 printf ("$%d", sreg
);
5418 printf ("0x%08lx", oc
& 0x1ffffff);
5430 printf ("$%d", shamt
);
5441 printf ("%08lx UNDEFINED\n", oc
);
5452 name
= input_line_pointer
;
5453 c
= get_symbol_end ();
5454 p
= (symbolS
*) symbol_find_or_make (name
);
5455 *input_line_pointer
= c
;
5459 /* Align the current frag to a given power of two. The MIPS assembler
5460 also automatically adjusts any preceding label. */
5463 mips_align (to
, fill
, label
)
5468 mips_emit_delays ();
5469 frag_align (to
, fill
);
5470 record_alignment (now_seg
, to
);
5473 assert (S_GET_SEGMENT (label
) == now_seg
);
5474 label
->sy_frag
= frag_now
;
5475 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5479 /* Align to a given power of two. .align 0 turns off the automatic
5480 alignment used by the data creating pseudo-ops. */
5487 register long temp_fill
;
5488 long max_alignment
= 15;
5492 o Note that the assembler pulls down any immediately preceeding label
5493 to the aligned address.
5494 o It's not documented but auto alignment is reinstated by
5495 a .align pseudo instruction.
5496 o Note also that after auto alignment is turned off the mips assembler
5497 issues an error on attempt to assemble an improperly aligned data item.
5502 temp
= get_absolute_expression ();
5503 if (temp
> max_alignment
)
5504 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5507 as_warn ("Alignment negative: 0 assumed.");
5510 if (*input_line_pointer
== ',')
5512 input_line_pointer
++;
5513 temp_fill
= get_absolute_expression ();
5520 mips_align (temp
, (int) temp_fill
, insn_label
);
5527 demand_empty_rest_of_line ();
5530 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5531 that there was a previous instruction. */
5534 s_stringer (append_zero
)
5537 mips_emit_delays ();
5539 stringer (append_zero
);
5550 /* When generating embedded PIC code, we only use the .text, .lit8,
5551 .sdata and .sbss sections. We change the .data and .rdata
5552 pseudo-ops to use .sdata. */
5553 if (mips_pic
== EMBEDDED_PIC
5554 && (sec
== 'd' || sec
== 'r'))
5557 mips_emit_delays ();
5567 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5568 demand_empty_rest_of_line ();
5572 seg
= subseg_new (RDATA_SECTION_NAME
,
5573 (subsegT
) get_absolute_expression ());
5575 bfd_set_section_flags (stdoutput
, seg
,
5581 bfd_set_section_alignment (stdoutput
, seg
, 4);
5583 demand_empty_rest_of_line ();
5588 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5590 bfd_set_section_flags (stdoutput
, seg
,
5591 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5592 bfd_set_section_alignment (stdoutput
, seg
, 4);
5594 demand_empty_rest_of_line ();
5596 #else /* ! defined (GPOPT) */
5597 as_bad ("Global pointers not supported; recompile -G 0");
5598 demand_empty_rest_of_line ();
5600 #endif /* ! defined (GPOPT) */
5613 mips_emit_delays ();
5614 if (log_size
> 0 && auto_align
)
5615 mips_align (log_size
, 0, label
);
5617 cons (1 << log_size
);
5624 as_fatal ("Encountered `.err', aborting assembly");
5634 symbolP
= get_symbol ();
5635 if (*input_line_pointer
== ',')
5636 input_line_pointer
++;
5637 size
= get_absolute_expression ();
5638 S_SET_EXTERNAL (symbolP
);
5640 #ifdef ECOFF_DEBUGGING
5641 symbolP
->ecoff_extern_size
= size
;
5653 mips_emit_delays ();
5657 mips_align (3, 0, label
);
5659 mips_align (2, 0, label
);
5673 opt
= input_line_pointer
;
5674 c
= get_symbol_end ();
5678 /* FIXME: What does this mean? */
5680 else if (strncmp (opt
, "pic", 3) == 0)
5688 mips_pic
= SVR4_PIC
;
5690 as_bad (".option pic%d not supported", i
);
5693 if (mips_pic
== SVR4_PIC
)
5695 if (g_switch_seen
&& g_switch_value
!= 0)
5696 as_warn ("-G may not be used with SVR4 PIC code");
5698 bfd_set_gp_size (stdoutput
, 0);
5703 as_warn ("Unrecognized option \"%s\"", opt
);
5705 *input_line_pointer
= c
;
5706 demand_empty_rest_of_line ();
5713 char *name
= input_line_pointer
, ch
;
5715 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5716 input_line_pointer
++;
5717 ch
= *input_line_pointer
;
5718 *input_line_pointer
= '\0';
5720 if (strcmp (name
, "reorder") == 0)
5724 prev_insn_unreordered
= 1;
5725 prev_prev_insn_unreordered
= 1;
5729 else if (strcmp (name
, "noreorder") == 0)
5731 mips_emit_delays ();
5733 mips_any_noreorder
= 1;
5735 else if (strcmp (name
, "at") == 0)
5739 else if (strcmp (name
, "noat") == 0)
5743 else if (strcmp (name
, "macro") == 0)
5745 mips_warn_about_macros
= 0;
5747 else if (strcmp (name
, "nomacro") == 0)
5749 if (mips_noreorder
== 0)
5750 as_bad ("`noreorder' must be set before `nomacro'");
5751 mips_warn_about_macros
= 1;
5753 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5757 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5761 else if (strcmp (name
, "bopt") == 0)
5765 else if (strcmp (name
, "nobopt") == 0)
5769 else if (strncmp (name
, "mips", 4) == 0)
5773 /* Permit the user to change the ISA on the fly. Needless to
5774 say, misuse can cause serious problems. */
5775 isa
= atoi (name
+ 4);
5777 mips_isa
= file_mips_isa
;
5778 else if (isa
< 1 || isa
> 3)
5779 as_bad ("unknown ISA level");
5785 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5787 *input_line_pointer
= ch
;
5788 demand_empty_rest_of_line ();
5791 /* The same as the usual .space directive, except that we have to
5792 forget about any previous instruction. */
5795 s_mips_space (param
)
5798 mips_emit_delays ();
5803 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5804 .option pic2. It means to generate SVR4 PIC calls. */
5810 mips_pic
= SVR4_PIC
;
5812 if (g_switch_seen
&& g_switch_value
!= 0)
5813 as_warn ("-G may not be used with SVR4 PIC code");
5816 bfd_set_gp_size (stdoutput
, 0);
5817 demand_empty_rest_of_line ();
5820 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5821 PIC code. It sets the $gp register for the function based on the
5822 function address, which is in the register named in the argument.
5823 This uses a relocation against _gp_disp, which is handled specially
5824 by the linker. The result is:
5825 lui $gp,%hi(_gp_disp)
5826 addiu $gp,$gp,%lo(_gp_disp)
5827 addu $gp,$gp,.cpload argument
5828 The .cpload argument is normally $25 == $t9. */
5837 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
5838 if (mips_pic
!= SVR4_PIC
)
5844 /* .cpload should be a in .set noreorder section. */
5845 if (mips_noreorder
== 0)
5846 as_warn (".cpload not in noreorder section");
5849 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5850 ex
.X_op_symbol
= NULL
;
5851 ex
.X_add_number
= 0;
5853 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5854 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5855 (int) BFD_RELOC_LO16
);
5857 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5858 GP
, GP
, tc_get_register (0));
5860 demand_empty_rest_of_line ();
5863 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5864 offset from $sp. The offset is remembered, and after making a PIC
5865 call $gp is restored from that location. */
5868 s_cprestore (ignore
)
5874 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
5875 if (mips_pic
!= SVR4_PIC
)
5881 mips_cprestore_offset
= get_absolute_expression ();
5883 ex
.X_op
= O_constant
;
5884 ex
.X_add_symbol
= NULL
;
5885 ex
.X_op_symbol
= NULL
;
5886 ex
.X_add_number
= mips_cprestore_offset
;
5888 macro_build ((char *) NULL
, &icnt
, &ex
,
5889 mips_isa
< 3 ? "sw" : "sd",
5890 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5892 demand_empty_rest_of_line ();
5895 /* Handle the .gpword pseudo-op. This is used when generating PIC
5896 code. It generates a 32 bit GP relative reloc. */
5906 /* When not generating PIC code, this is treated as .word. */
5907 if (mips_pic
!= SVR4_PIC
)
5914 mips_emit_delays ();
5916 mips_align (2, 0, label
);
5921 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5923 as_bad ("Unsupported use of .gpword");
5924 ignore_rest_of_line ();
5928 md_number_to_chars (p
, (valueT
) 0, 4);
5929 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5930 BFD_RELOC_MIPS_GPREL32
);
5932 demand_empty_rest_of_line ();
5935 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5936 tables in SVR4 PIC code. */
5945 /* This is ignored when not generating SVR4 PIC code. */
5946 if (mips_pic
!= SVR4_PIC
)
5952 /* Add $gp to the register named as an argument. */
5953 reg
= tc_get_register (0);
5954 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5955 mips_isa
< 3 ? "addu" : "daddu",
5956 "d,v,t", reg
, reg
, GP
);
5958 demand_empty_rest_of_line ();
5961 /* Parse a register string into a number. Called from the ECOFF code
5962 to parse .frame. The argument is non-zero if this is the frame
5963 register, so that we can record it in mips_frame_reg. */
5966 tc_get_register (frame
)
5972 if (*input_line_pointer
++ != '$')
5974 as_warn ("expected `$'");
5977 else if (isdigit ((unsigned char) *input_line_pointer
))
5979 reg
= get_absolute_expression ();
5980 if (reg
< 0 || reg
>= 32)
5982 as_warn ("Bad register number");
5988 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5990 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5992 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5994 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5998 as_warn ("Unrecognized register name");
6001 input_line_pointer
+= 2;
6004 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6009 md_section_align (seg
, addr
)
6013 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6015 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6018 /* Estimate the size of a frag before relaxing. We are not really
6019 relaxing here, and the final size is encoded in the subtype
6024 md_estimate_size_before_relax (fragp
, segtype
)
6030 if (mips_pic
== NO_PIC
)
6033 const char *symname
;
6035 /* Find out whether this symbol can be referenced off the GP
6036 register. It can be if it is smaller than the -G size or if
6037 it is in the .sdata or .sbss section. Certain symbols can
6038 not be referenced off the GP, although it appears as though
6040 symname
= S_GET_NAME (fragp
->fr_symbol
);
6041 if (symname
!= (const char *) NULL
6042 && (strcmp (symname
, "eprol") == 0
6043 || strcmp (symname
, "etext") == 0
6044 || strcmp (symname
, "_gp") == 0
6045 || strcmp (symname
, "edata") == 0
6046 || strcmp (symname
, "_fbss") == 0
6047 || strcmp (symname
, "_fdata") == 0
6048 || strcmp (symname
, "_ftext") == 0
6049 || strcmp (symname
, "end") == 0
6050 || strcmp (symname
, "_gp_disp") == 0))
6052 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6053 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6054 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6055 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6056 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6060 const char *segname
;
6062 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6063 assert (strcmp (segname
, ".lit8") != 0
6064 && strcmp (segname
, ".lit4") != 0);
6065 change
= (strcmp (segname
, ".sdata") != 0
6066 && strcmp (segname
, ".sbss") != 0);
6068 #else /* ! defined (GPOPT) */
6069 /* We are not optimizing for the GP register. */
6071 #endif /* ! defined (GPOPT) */
6073 else if (mips_pic
== SVR4_PIC
)
6075 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6077 /* This must duplicate the test in adjust_reloc_syms. */
6078 change
= (symsec
!= &bfd_und_section
6079 && symsec
!= &bfd_abs_section
6080 && ! bfd_is_com_section (symsec
));
6087 /* Record the offset to the first reloc in the fr_opcode field.
6088 This lets md_convert_frag and tc_gen_reloc know that the code
6089 must be expanded. */
6090 fragp
->fr_opcode
= (fragp
->fr_literal
6092 - RELAX_OLD (fragp
->fr_subtype
)
6093 + RELAX_RELOC1 (fragp
->fr_subtype
));
6094 /* FIXME: This really needs as_warn_where. */
6095 if (RELAX_WARN (fragp
->fr_subtype
))
6096 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6102 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6105 /* Translate internal representation of relocation info to BFD target
6109 tc_gen_reloc (section
, fixp
)
6113 static arelent
*retval
[4];
6116 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6119 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6120 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6122 if (mips_pic
== EMBEDDED_PIC
6123 && SWITCH_TABLE (fixp
))
6125 /* For a switch table entry we use a special reloc. The addend
6126 is actually the difference between the reloc address and the
6128 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6130 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6132 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6134 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6136 /* We use a special addend for an internal RELLO reloc. */
6137 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6138 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6140 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6142 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6144 assert (fixp
->fx_next
!= NULL
6145 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6146 /* We use a special addend for an internal RELHI reloc. The
6147 reloc is relative to the RELLO; adjust the addend
6149 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6150 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6151 + fixp
->fx_next
->fx_where
6152 - S_GET_VALUE (fixp
->fx_subsy
));
6154 reloc
->addend
= (fixp
->fx_addnumber
6155 + fixp
->fx_next
->fx_frag
->fr_address
6156 + fixp
->fx_next
->fx_where
);
6158 else if (fixp
->fx_pcrel
== 0)
6159 reloc
->addend
= fixp
->fx_addnumber
;
6163 /* A gruesome hack which is a result of the gruesome gas reloc
6165 reloc
->addend
= reloc
->address
;
6167 reloc
->addend
= -reloc
->address
;
6171 /* If this is a variant frag, we may need to adjust the existing
6172 reloc and generate a new one. */
6173 if (fixp
->fx_frag
->fr_opcode
!= NULL
6174 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6175 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6176 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6180 /* If this is not the last reloc in this frag, then we have two
6181 GPREL relocs, both of which are being replaced. Let the
6182 second one handle all of them. */
6183 if (fixp
->fx_next
!= NULL
6184 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6186 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6187 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6192 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6193 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6194 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6196 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6197 reloc2
->address
= (reloc
->address
6198 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6199 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6200 reloc2
->addend
= fixp
->fx_addnumber
;
6201 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6202 assert (reloc2
->howto
!= NULL
);
6204 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6208 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6211 reloc3
->address
+= 4;
6214 if (mips_pic
== NO_PIC
)
6216 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6217 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6219 else if (mips_pic
== SVR4_PIC
)
6221 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6223 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6224 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6231 /* To support a PC relative reloc when generating embedded PIC code
6232 for ECOFF, we use a Cygnus extension. We check for that here to
6233 make sure that we don't let such a reloc escape normally. */
6235 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6236 && mips_pic
!= EMBEDDED_PIC
)
6237 reloc
->howto
= NULL
;
6240 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6242 if (reloc
->howto
== NULL
)
6244 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6245 "Can not represent relocation in this object file format");
6252 /* Convert a machine dependent frag. */
6255 md_convert_frag (abfd
, asec
, fragp
)
6263 if (fragp
->fr_opcode
== NULL
)
6266 old
= RELAX_OLD (fragp
->fr_subtype
);
6267 new = RELAX_NEW (fragp
->fr_subtype
);
6268 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6271 memcpy (fixptr
- old
, fixptr
, new);
6273 fragp
->fr_fix
+= new - old
;
6276 /* This function is called whenever a label is defined. It is used
6277 when handling branch delays; if a branch has a label, we assume we
6281 mips_define_label (sym
)
6289 /* Some special processing for a MIPS ELF file. */
6292 mips_elf_final_processing ()
6296 /* Write out the .reginfo section. */
6297 s
.ri_gprmask
= mips_gprmask
;
6298 s
.ri_cprmask
[0] = mips_cprmask
[0];
6299 s
.ri_cprmask
[1] = mips_cprmask
[1];
6300 s
.ri_cprmask
[2] = mips_cprmask
[2];
6301 s
.ri_cprmask
[3] = mips_cprmask
[3];
6302 /* The gp_value field is set by the MIPS ELF backend. */
6304 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6305 ((Elf32_External_RegInfo
*)
6306 mips_regmask_frag
));
6308 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6309 sort of BFD interface for this. */
6310 if (mips_any_noreorder
)
6311 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6312 if (mips_pic
!= NO_PIC
)
6313 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6316 #endif /* OBJ_ELF */
6318 #ifndef ECOFF_DEBUGGING
6320 /* These functions should really be defined by the object file format,
6321 since they are related to debugging information. However, this
6322 code has to work for the a.out format, which does not define them,
6323 so we provide simple versions here. These don't actually generate
6324 any debugging information, but they do simple checking and someday
6325 somebody may make them useful. */
6329 struct loc
*loc_next
;
6330 unsigned long loc_fileno
;
6331 unsigned long loc_lineno
;
6332 unsigned long loc_offset
;
6333 unsigned short loc_delta
;
6334 unsigned short loc_count
;
6343 struct proc
*proc_next
;
6344 struct symbol
*proc_isym
;
6345 struct symbol
*proc_end
;
6346 unsigned long proc_reg_mask
;
6347 unsigned long proc_reg_offset
;
6348 unsigned long proc_fpreg_mask
;
6349 unsigned long proc_fpreg_offset
;
6350 unsigned long proc_frameoffset
;
6351 unsigned long proc_framereg
;
6352 unsigned long proc_pcreg
;
6354 struct file
*proc_file
;
6361 struct file
*file_next
;
6362 unsigned long file_fileno
;
6363 struct symbol
*file_symbol
;
6364 struct symbol
*file_end
;
6365 struct proc
*file_proc
;
6370 static struct obstack proc_frags
;
6371 static procS
*proc_lastP
;
6372 static procS
*proc_rootP
;
6373 static int numprocs
;
6378 obstack_begin (&proc_frags
, 0x2000);
6384 /* check for premature end, nesting errors, etc */
6385 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6386 as_warn ("missing `.end' at end of assembly");
6389 extern char hex_value
[];
6397 if (*input_line_pointer
== '-')
6399 ++input_line_pointer
;
6402 if (!isdigit (*input_line_pointer
))
6403 as_bad ("Expected simple number.");
6404 if (input_line_pointer
[0] == '0')
6406 if (input_line_pointer
[1] == 'x')
6408 input_line_pointer
+= 2;
6409 while (isxdigit (*input_line_pointer
))
6412 val
|= hex_value
[(int) *input_line_pointer
++];
6414 return negative
? -val
: val
;
6418 ++input_line_pointer
;
6419 while (isdigit (*input_line_pointer
))
6422 val
|= *input_line_pointer
++ - '0';
6424 return negative
? -val
: val
;
6427 if (!isdigit (*input_line_pointer
))
6429 printf (" *input_line_pointer == '%c' 0x%02x\n",
6430 *input_line_pointer
, *input_line_pointer
);
6431 as_warn ("Invalid number");
6434 while (isdigit (*input_line_pointer
))
6437 val
+= *input_line_pointer
++ - '0';
6439 return negative
? -val
: val
;
6442 /* The .file directive; just like the usual .file directive, but there
6443 is an initial number which is the ECOFF file index. */
6451 line
= get_number ();
6456 /* The .end directive. */
6464 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6467 demand_empty_rest_of_line ();
6471 if (now_seg
!= text_section
)
6472 as_warn (".end not in text section");
6475 as_warn (".end and no .ent seen yet.");
6481 assert (S_GET_NAME (p
));
6482 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6483 as_warn (".end symbol does not match .ent symbol.");
6486 proc_lastP
->proc_end
= (symbolS
*) 1;
6489 /* The .aent and .ent directives. */
6499 symbolP
= get_symbol ();
6500 if (*input_line_pointer
== ',')
6501 input_line_pointer
++;
6503 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6504 number
= get_number ();
6505 if (now_seg
!= text_section
)
6506 as_warn (".ent or .aent not in text section.");
6508 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6509 as_warn ("missing `.end'");
6513 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6514 procP
->proc_isym
= symbolP
;
6515 procP
->proc_reg_mask
= 0;
6516 procP
->proc_reg_offset
= 0;
6517 procP
->proc_fpreg_mask
= 0;
6518 procP
->proc_fpreg_offset
= 0;
6519 procP
->proc_frameoffset
= 0;
6520 procP
->proc_framereg
= 0;
6521 procP
->proc_pcreg
= 0;
6522 procP
->proc_end
= NULL
;
6523 procP
->proc_next
= NULL
;
6525 proc_lastP
->proc_next
= procP
;
6531 demand_empty_rest_of_line ();
6534 /* The .frame directive. */
6547 frame_reg
= tc_get_register (1);
6548 if (*input_line_pointer
== ',')
6549 input_line_pointer
++;
6550 frame_off
= get_absolute_expression ();
6551 if (*input_line_pointer
== ',')
6552 input_line_pointer
++;
6553 pcreg
= tc_get_register (0);
6556 assert (proc_rootP
);
6557 proc_rootP
->proc_framereg
= frame_reg
;
6558 proc_rootP
->proc_frameoffset
= frame_off
;
6559 proc_rootP
->proc_pcreg
= pcreg
;
6560 /* bob macho .frame */
6562 /* We don't have to write out a frame stab for unoptimized code. */
6563 if (!(frame_reg
== FP
&& frame_off
== 0))
6566 as_warn ("No .ent for .frame to use.");
6567 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6568 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6569 S_SET_TYPE (symP
, N_RMASK
);
6570 S_SET_OTHER (symP
, 0);
6571 S_SET_DESC (symP
, 0);
6572 symP
->sy_forward
= proc_lastP
->proc_isym
;
6573 /* bob perhaps I should have used pseudo set */
6575 demand_empty_rest_of_line ();
6579 /* The .fmask and .mask directives. */
6586 char str
[100], *strP
;
6592 mask
= get_number ();
6593 if (*input_line_pointer
== ',')
6594 input_line_pointer
++;
6595 off
= get_absolute_expression ();
6597 /* bob only for coff */
6598 assert (proc_rootP
);
6599 if (reg_type
== 'F')
6601 proc_rootP
->proc_fpreg_mask
= mask
;
6602 proc_rootP
->proc_fpreg_offset
= off
;
6606 proc_rootP
->proc_reg_mask
= mask
;
6607 proc_rootP
->proc_reg_offset
= off
;
6610 /* bob macho .mask + .fmask */
6612 /* We don't have to write out a mask stab if no saved regs. */
6616 as_warn ("No .ent for .mask to use.");
6618 for (i
= 0; i
< 32; i
++)
6622 sprintf (strP
, "%c%d,", reg_type
, i
);
6623 strP
+= strlen (strP
);
6627 sprintf (strP
, ";%d,", off
);
6628 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6629 S_SET_TYPE (symP
, N_RMASK
);
6630 S_SET_OTHER (symP
, 0);
6631 S_SET_DESC (symP
, 0);
6632 symP
->sy_forward
= proc_lastP
->proc_isym
;
6633 /* bob perhaps I should have used pseudo set */
6638 /* The .loc directive. */
6649 assert (now_seg
== text_section
);
6651 lineno
= get_number ();
6652 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6654 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6655 S_SET_TYPE (symbolP
, N_SLINE
);
6656 S_SET_OTHER (symbolP
, 0);
6657 S_SET_DESC (symbolP
, lineno
);
6658 symbolP
->sy_segment
= now_seg
;
6662 #endif /* ! defined (ECOFF_DEBUGGING) */