1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
29 #include "safe-ctype.h"
31 #include "opcode/mips.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
37 #define DBG(x) printf x
43 /* Clean up namespace so we can include obj-elf.h too. */
44 static int mips_output_flavor (void);
45 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
46 #undef OBJ_PROCESS_STAB
53 #undef obj_frob_file_after_relocs
54 #undef obj_frob_symbol
56 #undef obj_sec_sym_ok_for_reloc
57 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
60 /* Fix any of them that we actually care about. */
62 #define OUTPUT_FLAVOR mips_output_flavor()
69 #ifndef ECOFF_DEBUGGING
70 #define NO_ECOFF_DEBUGGING
71 #define ECOFF_DEBUGGING 0
74 int mips_flag_mdebug
= -1;
76 /* Control generation of .pdr sections. Off by default on IRIX: the native
77 linker doesn't know about and discards them, but relocations against them
78 remain, leading to rld crashes. */
80 int mips_flag_pdr
= FALSE
;
82 int mips_flag_pdr
= TRUE
;
87 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
88 static char *mips_regmask_frag
;
94 #define PIC_CALL_REG 25
102 #define ILLEGAL_REG (32)
104 /* Allow override of standard little-endian ECOFF format. */
106 #ifndef ECOFF_LITTLE_FORMAT
107 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
110 extern int target_big_endian
;
112 /* The name of the readonly data section. */
113 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
115 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
117 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
121 /* Information about an instruction, including its format, operands
125 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
126 const struct mips_opcode
*insn_mo
;
128 /* True if this is a mips16 instruction and if we want the extended
130 bfd_boolean use_extend
;
132 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
133 unsigned short extend
;
135 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
136 a copy of INSN_MO->match with the operands filled in. */
137 unsigned long insn_opcode
;
139 /* The frag that contains the instruction. */
142 /* The offset into FRAG of the first instruction byte. */
145 /* The relocs associated with the instruction, if any. */
148 /* True if this entry cannot be moved from its current position. */
149 unsigned int fixed_p
: 1;
151 /* True if this instruction occurred in a .set noreorder block. */
152 unsigned int noreorder_p
: 1;
154 /* True for mips16 instructions that jump to an absolute address. */
155 unsigned int mips16_absolute_jump_p
: 1;
158 /* The ABI to use. */
169 /* MIPS ABI we are using for this output file. */
170 static enum mips_abi_level mips_abi
= NO_ABI
;
172 /* Whether or not we have code that can call pic code. */
173 int mips_abicalls
= FALSE
;
175 /* Whether or not we have code which can be put into a shared
177 static bfd_boolean mips_in_shared
= TRUE
;
179 /* This is the set of options which may be modified by the .set
180 pseudo-op. We use a struct so that .set push and .set pop are more
183 struct mips_set_options
185 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
186 if it has not been initialized. Changed by `.set mipsN', and the
187 -mipsN command line option, and the default CPU. */
189 /* Enabled Application Specific Extensions (ASEs). These are set to -1
190 if they have not been initialized. Changed by `.set <asename>', by
191 command line options, and based on the default architecture. */
197 /* Whether we are assembling for the mips16 processor. 0 if we are
198 not, 1 if we are, and -1 if the value has not been initialized.
199 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
200 -nomips16 command line options, and the default CPU. */
202 /* Non-zero if we should not reorder instructions. Changed by `.set
203 reorder' and `.set noreorder'. */
205 /* Non-zero if we should not permit the $at ($1) register to be used
206 in instructions. Changed by `.set at' and `.set noat'. */
208 /* Non-zero if we should warn when a macro instruction expands into
209 more than one machine instruction. Changed by `.set nomacro' and
211 int warn_about_macros
;
212 /* Non-zero if we should not move instructions. Changed by `.set
213 move', `.set volatile', `.set nomove', and `.set novolatile'. */
215 /* Non-zero if we should not optimize branches by moving the target
216 of the branch into the delay slot. Actually, we don't perform
217 this optimization anyhow. Changed by `.set bopt' and `.set
220 /* Non-zero if we should not autoextend mips16 instructions.
221 Changed by `.set autoextend' and `.set noautoextend'. */
223 /* Restrict general purpose registers and floating point registers
224 to 32 bit. This is initially determined when -mgp32 or -mfp32
225 is passed but can changed if the assembler code uses .set mipsN. */
228 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
229 command line option, and the default CPU. */
231 /* True if ".set sym32" is in effect. */
235 /* True if -mgp32 was passed. */
236 static int file_mips_gp32
= -1;
238 /* True if -mfp32 was passed. */
239 static int file_mips_fp32
= -1;
241 /* This is the struct we use to hold the current set of options. Note
242 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
243 -1 to indicate that they have not been initialized. */
245 static struct mips_set_options mips_opts
=
247 ISA_UNKNOWN
, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
, FALSE
250 /* These variables are filled in with the masks of registers used.
251 The object format code reads them and puts them in the appropriate
253 unsigned long mips_gprmask
;
254 unsigned long mips_cprmask
[4];
256 /* MIPS ISA we are using for this output file. */
257 static int file_mips_isa
= ISA_UNKNOWN
;
259 /* True if -mips16 was passed or implied by arguments passed on the
260 command line (e.g., by -march). */
261 static int file_ase_mips16
;
263 /* True if -mips3d was passed or implied by arguments passed on the
264 command line (e.g., by -march). */
265 static int file_ase_mips3d
;
267 /* True if -mdmx was passed or implied by arguments passed on the
268 command line (e.g., by -march). */
269 static int file_ase_mdmx
;
271 /* True if -msmartmips was passed or implied by arguments passed on the
272 command line (e.g., by -march). */
273 static int file_ase_smartmips
;
275 #define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
276 || mips_opts.isa == ISA_MIPS32R2)
278 /* True if -mdsp was passed or implied by arguments passed on the
279 command line (e.g., by -march). */
280 static int file_ase_dsp
;
282 #define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
283 || mips_opts.isa == ISA_MIPS64R2)
285 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
287 /* True if -mmt was passed or implied by arguments passed on the
288 command line (e.g., by -march). */
289 static int file_ase_mt
;
291 #define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
292 || mips_opts.isa == ISA_MIPS64R2)
294 /* The argument of the -march= flag. The architecture we are assembling. */
295 static int file_mips_arch
= CPU_UNKNOWN
;
296 static const char *mips_arch_string
;
298 /* The argument of the -mtune= flag. The architecture for which we
300 static int mips_tune
= CPU_UNKNOWN
;
301 static const char *mips_tune_string
;
303 /* True when generating 32-bit code for a 64-bit processor. */
304 static int mips_32bitmode
= 0;
306 /* True if the given ABI requires 32-bit registers. */
307 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
309 /* Likewise 64-bit registers. */
310 #define ABI_NEEDS_64BIT_REGS(ABI) \
312 || (ABI) == N64_ABI \
315 /* Return true if ISA supports 64 bit wide gp registers. */
316 #define ISA_HAS_64BIT_REGS(ISA) \
317 ((ISA) == ISA_MIPS3 \
318 || (ISA) == ISA_MIPS4 \
319 || (ISA) == ISA_MIPS5 \
320 || (ISA) == ISA_MIPS64 \
321 || (ISA) == ISA_MIPS64R2)
323 /* Return true if ISA supports 64 bit wide float registers. */
324 #define ISA_HAS_64BIT_FPRS(ISA) \
325 ((ISA) == ISA_MIPS3 \
326 || (ISA) == ISA_MIPS4 \
327 || (ISA) == ISA_MIPS5 \
328 || (ISA) == ISA_MIPS32R2 \
329 || (ISA) == ISA_MIPS64 \
330 || (ISA) == ISA_MIPS64R2)
332 /* Return true if ISA supports 64-bit right rotate (dror et al.)
334 #define ISA_HAS_DROR(ISA) \
335 ((ISA) == ISA_MIPS64R2)
337 /* Return true if ISA supports 32-bit right rotate (ror et al.)
339 #define ISA_HAS_ROR(ISA) \
340 ((ISA) == ISA_MIPS32R2 \
341 || (ISA) == ISA_MIPS64R2 \
342 || mips_opts.ase_smartmips)
344 /* Return true if ISA supports single-precision floats in odd registers. */
345 #define ISA_HAS_ODD_SINGLE_FPR(ISA) \
346 ((ISA) == ISA_MIPS32 \
347 || (ISA) == ISA_MIPS32R2 \
348 || (ISA) == ISA_MIPS64 \
349 || (ISA) == ISA_MIPS64R2)
351 /* Return true if ISA supports move to/from high part of a 64-bit
352 floating-point register. */
353 #define ISA_HAS_MXHC1(ISA) \
354 ((ISA) == ISA_MIPS32R2 \
355 || (ISA) == ISA_MIPS64R2)
357 #define HAVE_32BIT_GPRS \
358 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
360 #define HAVE_32BIT_FPRS \
361 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
363 #define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
364 #define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
366 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
368 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
370 /* True if relocations are stored in-place. */
371 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
373 /* The ABI-derived address size. */
374 #define HAVE_64BIT_ADDRESSES \
375 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
376 #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
378 /* The size of symbolic constants (i.e., expressions of the form
379 "SYMBOL" or "SYMBOL + OFFSET"). */
380 #define HAVE_32BIT_SYMBOLS \
381 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
382 #define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
384 /* Addresses are loaded in different ways, depending on the address size
385 in use. The n32 ABI Documentation also mandates the use of additions
386 with overflow checking, but existing implementations don't follow it. */
387 #define ADDRESS_ADD_INSN \
388 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
390 #define ADDRESS_ADDI_INSN \
391 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
393 #define ADDRESS_LOAD_INSN \
394 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
396 #define ADDRESS_STORE_INSN \
397 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
399 /* Return true if the given CPU supports the MIPS16 ASE. */
400 #define CPU_HAS_MIPS16(cpu) \
401 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
402 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
404 /* True if CPU has a dror instruction. */
405 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
407 /* True if CPU has a ror instruction. */
408 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
410 /* True if mflo and mfhi can be immediately followed by instructions
411 which write to the HI and LO registers.
413 According to MIPS specifications, MIPS ISAs I, II, and III need
414 (at least) two instructions between the reads of HI/LO and
415 instructions which write them, and later ISAs do not. Contradicting
416 the MIPS specifications, some MIPS IV processor user manuals (e.g.
417 the UM for the NEC Vr5000) document needing the instructions between
418 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
419 MIPS64 and later ISAs to have the interlocks, plus any specific
420 earlier-ISA CPUs for which CPU documentation declares that the
421 instructions are really interlocked. */
422 #define hilo_interlocks \
423 (mips_opts.isa == ISA_MIPS32 \
424 || mips_opts.isa == ISA_MIPS32R2 \
425 || mips_opts.isa == ISA_MIPS64 \
426 || mips_opts.isa == ISA_MIPS64R2 \
427 || mips_opts.arch == CPU_R4010 \
428 || mips_opts.arch == CPU_R10000 \
429 || mips_opts.arch == CPU_R12000 \
430 || mips_opts.arch == CPU_RM7000 \
431 || mips_opts.arch == CPU_VR5500 \
434 /* Whether the processor uses hardware interlocks to protect reads
435 from the GPRs after they are loaded from memory, and thus does not
436 require nops to be inserted. This applies to instructions marked
437 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
439 #define gpr_interlocks \
440 (mips_opts.isa != ISA_MIPS1 \
441 || mips_opts.arch == CPU_R3900)
443 /* Whether the processor uses hardware interlocks to avoid delays
444 required by coprocessor instructions, and thus does not require
445 nops to be inserted. This applies to instructions marked
446 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
447 between instructions marked INSN_WRITE_COND_CODE and ones marked
448 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
449 levels I, II, and III. */
450 /* Itbl support may require additional care here. */
451 #define cop_interlocks \
452 ((mips_opts.isa != ISA_MIPS1 \
453 && mips_opts.isa != ISA_MIPS2 \
454 && mips_opts.isa != ISA_MIPS3) \
455 || mips_opts.arch == CPU_R4300 \
458 /* Whether the processor uses hardware interlocks to protect reads
459 from coprocessor registers after they are loaded from memory, and
460 thus does not require nops to be inserted. This applies to
461 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
462 requires at MIPS ISA level I. */
463 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
465 /* Is this a mfhi or mflo instruction? */
466 #define MF_HILO_INSN(PINFO) \
467 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
469 /* MIPS PIC level. */
471 enum mips_pic_level mips_pic
;
473 /* 1 if we should generate 32 bit offsets from the $gp register in
474 SVR4_PIC mode. Currently has no meaning in other modes. */
475 static int mips_big_got
= 0;
477 /* 1 if trap instructions should used for overflow rather than break
479 static int mips_trap
= 0;
481 /* 1 if double width floating point constants should not be constructed
482 by assembling two single width halves into two single width floating
483 point registers which just happen to alias the double width destination
484 register. On some architectures this aliasing can be disabled by a bit
485 in the status register, and the setting of this bit cannot be determined
486 automatically at assemble time. */
487 static int mips_disable_float_construction
;
489 /* Non-zero if any .set noreorder directives were used. */
491 static int mips_any_noreorder
;
493 /* Non-zero if nops should be inserted when the register referenced in
494 an mfhi/mflo instruction is read in the next two instructions. */
495 static int mips_7000_hilo_fix
;
497 /* The size of the small data section. */
498 static unsigned int g_switch_value
= 8;
499 /* Whether the -G option was used. */
500 static int g_switch_seen
= 0;
505 /* If we can determine in advance that GP optimization won't be
506 possible, we can skip the relaxation stuff that tries to produce
507 GP-relative references. This makes delay slot optimization work
510 This function can only provide a guess, but it seems to work for
511 gcc output. It needs to guess right for gcc, otherwise gcc
512 will put what it thinks is a GP-relative instruction in a branch
515 I don't know if a fix is needed for the SVR4_PIC mode. I've only
516 fixed it for the non-PIC mode. KR 95/04/07 */
517 static int nopic_need_relax (symbolS
*, int);
519 /* handle of the OPCODE hash table */
520 static struct hash_control
*op_hash
= NULL
;
522 /* The opcode hash table we use for the mips16. */
523 static struct hash_control
*mips16_op_hash
= NULL
;
525 /* This array holds the chars that always start a comment. If the
526 pre-processor is disabled, these aren't very useful */
527 const char comment_chars
[] = "#";
529 /* This array holds the chars that only start a comment at the beginning of
530 a line. If the line seems to have the form '# 123 filename'
531 .line and .file directives will appear in the pre-processed output */
532 /* Note that input_file.c hand checks for '#' at the beginning of the
533 first line of the input file. This is because the compiler outputs
534 #NO_APP at the beginning of its output. */
535 /* Also note that C style comments are always supported. */
536 const char line_comment_chars
[] = "#";
538 /* This array holds machine specific line separator characters. */
539 const char line_separator_chars
[] = ";";
541 /* Chars that can be used to separate mant from exp in floating point nums */
542 const char EXP_CHARS
[] = "eE";
544 /* Chars that mean this number is a floating point constant */
547 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
549 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
550 changed in read.c . Ideally it shouldn't have to know about it at all,
551 but nothing is ideal around here.
554 static char *insn_error
;
556 static int auto_align
= 1;
558 /* When outputting SVR4 PIC code, the assembler needs to know the
559 offset in the stack frame from which to restore the $gp register.
560 This is set by the .cprestore pseudo-op, and saved in this
562 static offsetT mips_cprestore_offset
= -1;
564 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
565 more optimizations, it can use a register value instead of a memory-saved
566 offset and even an other register than $gp as global pointer. */
567 static offsetT mips_cpreturn_offset
= -1;
568 static int mips_cpreturn_register
= -1;
569 static int mips_gp_register
= GP
;
570 static int mips_gprel_offset
= 0;
572 /* Whether mips_cprestore_offset has been set in the current function
573 (or whether it has already been warned about, if not). */
574 static int mips_cprestore_valid
= 0;
576 /* This is the register which holds the stack frame, as set by the
577 .frame pseudo-op. This is needed to implement .cprestore. */
578 static int mips_frame_reg
= SP
;
580 /* Whether mips_frame_reg has been set in the current function
581 (or whether it has already been warned about, if not). */
582 static int mips_frame_reg_valid
= 0;
584 /* To output NOP instructions correctly, we need to keep information
585 about the previous two instructions. */
587 /* Whether we are optimizing. The default value of 2 means to remove
588 unneeded NOPs and swap branch instructions when possible. A value
589 of 1 means to not swap branches. A value of 0 means to always
591 static int mips_optimize
= 2;
593 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
594 equivalent to seeing no -g option at all. */
595 static int mips_debug
= 0;
597 /* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
598 #define MAX_VR4130_NOPS 4
600 /* The maximum number of NOPs needed to fill delay slots. */
601 #define MAX_DELAY_NOPS 2
603 /* The maximum number of NOPs needed for any purpose. */
606 /* A list of previous instructions, with index 0 being the most recent.
607 We need to look back MAX_NOPS instructions when filling delay slots
608 or working around processor errata. We need to look back one
609 instruction further if we're thinking about using history[0] to
610 fill a branch delay slot. */
611 static struct mips_cl_insn history
[1 + MAX_NOPS
];
613 /* Nop instructions used by emit_nop. */
614 static struct mips_cl_insn nop_insn
, mips16_nop_insn
;
616 /* The appropriate nop for the current mode. */
617 #define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
619 /* If this is set, it points to a frag holding nop instructions which
620 were inserted before the start of a noreorder section. If those
621 nops turn out to be unnecessary, the size of the frag can be
623 static fragS
*prev_nop_frag
;
625 /* The number of nop instructions we created in prev_nop_frag. */
626 static int prev_nop_frag_holds
;
628 /* The number of nop instructions that we know we need in
630 static int prev_nop_frag_required
;
632 /* The number of instructions we've seen since prev_nop_frag. */
633 static int prev_nop_frag_since
;
635 /* For ECOFF and ELF, relocations against symbols are done in two
636 parts, with a HI relocation and a LO relocation. Each relocation
637 has only 16 bits of space to store an addend. This means that in
638 order for the linker to handle carries correctly, it must be able
639 to locate both the HI and the LO relocation. This means that the
640 relocations must appear in order in the relocation table.
642 In order to implement this, we keep track of each unmatched HI
643 relocation. We then sort them so that they immediately precede the
644 corresponding LO relocation. */
649 struct mips_hi_fixup
*next
;
652 /* The section this fixup is in. */
656 /* The list of unmatched HI relocs. */
658 static struct mips_hi_fixup
*mips_hi_fixup_list
;
660 /* The frag containing the last explicit relocation operator.
661 Null if explicit relocations have not been used. */
663 static fragS
*prev_reloc_op_frag
;
665 /* Map normal MIPS register numbers to mips16 register numbers. */
667 #define X ILLEGAL_REG
668 static const int mips32_to_16_reg_map
[] =
670 X
, X
, 2, 3, 4, 5, 6, 7,
671 X
, X
, X
, X
, X
, X
, X
, X
,
672 0, 1, X
, X
, X
, X
, X
, X
,
673 X
, X
, X
, X
, X
, X
, X
, X
677 /* Map mips16 register numbers to normal MIPS register numbers. */
679 static const unsigned int mips16_to_32_reg_map
[] =
681 16, 17, 2, 3, 4, 5, 6, 7
684 /* Classifies the kind of instructions we're interested in when
685 implementing -mfix-vr4120. */
686 enum fix_vr4120_class
{
693 NUM_FIX_VR4120_CLASSES
696 /* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
697 there must be at least one other instruction between an instruction
698 of type X and an instruction of type Y. */
699 static unsigned int vr4120_conflicts
[NUM_FIX_VR4120_CLASSES
];
701 /* True if -mfix-vr4120 is in force. */
702 static int mips_fix_vr4120
;
704 /* ...likewise -mfix-vr4130. */
705 static int mips_fix_vr4130
;
707 /* We don't relax branches by default, since this causes us to expand
708 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
709 fail to compute the offset before expanding the macro to the most
710 efficient expansion. */
712 static int mips_relax_branch
;
714 /* The expansion of many macros depends on the type of symbol that
715 they refer to. For example, when generating position-dependent code,
716 a macro that refers to a symbol may have two different expansions,
717 one which uses GP-relative addresses and one which uses absolute
718 addresses. When generating SVR4-style PIC, a macro may have
719 different expansions for local and global symbols.
721 We handle these situations by generating both sequences and putting
722 them in variant frags. In position-dependent code, the first sequence
723 will be the GP-relative one and the second sequence will be the
724 absolute one. In SVR4 PIC, the first sequence will be for global
725 symbols and the second will be for local symbols.
727 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
728 SECOND are the lengths of the two sequences in bytes. These fields
729 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
730 the subtype has the following flags:
733 Set if it has been decided that we should use the second
734 sequence instead of the first.
737 Set in the first variant frag if the macro's second implementation
738 is longer than its first. This refers to the macro as a whole,
739 not an individual relaxation.
742 Set in the first variant frag if the macro appeared in a .set nomacro
743 block and if one alternative requires a warning but the other does not.
746 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
749 The frag's "opcode" points to the first fixup for relaxable code.
751 Relaxable macros are generated using a sequence such as:
753 relax_start (SYMBOL);
754 ... generate first expansion ...
756 ... generate second expansion ...
759 The code and fixups for the unwanted alternative are discarded
760 by md_convert_frag. */
761 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
763 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
764 #define RELAX_SECOND(X) ((X) & 0xff)
765 #define RELAX_USE_SECOND 0x10000
766 #define RELAX_SECOND_LONGER 0x20000
767 #define RELAX_NOMACRO 0x40000
768 #define RELAX_DELAY_SLOT 0x80000
770 /* Branch without likely bit. If label is out of range, we turn:
772 beq reg1, reg2, label
782 with the following opcode replacements:
789 bltzal <-> bgezal (with jal label instead of j label)
791 Even though keeping the delay slot instruction in the delay slot of
792 the branch would be more efficient, it would be very tricky to do
793 correctly, because we'd have to introduce a variable frag *after*
794 the delay slot instruction, and expand that instead. Let's do it
795 the easy way for now, even if the branch-not-taken case now costs
796 one additional instruction. Out-of-range branches are not supposed
797 to be common, anyway.
799 Branch likely. If label is out of range, we turn:
801 beql reg1, reg2, label
802 delay slot (annulled if branch not taken)
811 delay slot (executed only if branch taken)
814 It would be possible to generate a shorter sequence by losing the
815 likely bit, generating something like:
820 delay slot (executed only if branch taken)
832 bltzall -> bgezal (with jal label instead of j label)
833 bgezall -> bltzal (ditto)
836 but it's not clear that it would actually improve performance. */
837 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
840 | ((toofar) ? 1 : 0) \
842 | ((likely) ? 4 : 0) \
843 | ((uncond) ? 8 : 0)))
844 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
845 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
846 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
847 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
848 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
850 /* For mips16 code, we use an entirely different form of relaxation.
851 mips16 supports two versions of most instructions which take
852 immediate values: a small one which takes some small value, and a
853 larger one which takes a 16 bit value. Since branches also follow
854 this pattern, relaxing these values is required.
856 We can assemble both mips16 and normal MIPS code in a single
857 object. Therefore, we need to support this type of relaxation at
858 the same time that we support the relaxation described above. We
859 use the high bit of the subtype field to distinguish these cases.
861 The information we store for this type of relaxation is the
862 argument code found in the opcode file for this relocation, whether
863 the user explicitly requested a small or extended form, and whether
864 the relocation is in a jump or jal delay slot. That tells us the
865 size of the value, and how it should be stored. We also store
866 whether the fragment is considered to be extended or not. We also
867 store whether this is known to be a branch to a different section,
868 whether we have tried to relax this frag yet, and whether we have
869 ever extended a PC relative fragment because of a shift count. */
870 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
873 | ((small) ? 0x100 : 0) \
874 | ((ext) ? 0x200 : 0) \
875 | ((dslot) ? 0x400 : 0) \
876 | ((jal_dslot) ? 0x800 : 0))
877 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
878 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
879 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
880 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
881 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
882 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
883 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
884 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
885 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
886 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
887 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
888 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
890 /* Is the given value a sign-extended 32-bit value? */
891 #define IS_SEXT_32BIT_NUM(x) \
892 (((x) &~ (offsetT) 0x7fffffff) == 0 \
893 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
895 /* Is the given value a sign-extended 16-bit value? */
896 #define IS_SEXT_16BIT_NUM(x) \
897 (((x) &~ (offsetT) 0x7fff) == 0 \
898 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
900 /* Is the given value a zero-extended 32-bit value? Or a negated one? */
901 #define IS_ZEXT_32BIT_NUM(x) \
902 (((x) &~ (offsetT) 0xffffffff) == 0 \
903 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
905 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
906 VALUE << SHIFT. VALUE is evaluated exactly once. */
907 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
908 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
909 | (((VALUE) & (MASK)) << (SHIFT)))
911 /* Extract bits MASK << SHIFT from STRUCT and shift them right
913 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
914 (((STRUCT) >> (SHIFT)) & (MASK))
916 /* Change INSN's opcode so that the operand given by FIELD has value VALUE.
917 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
919 include/opcode/mips.h specifies operand fields using the macros
920 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
921 with "MIPS16OP" instead of "OP". */
922 #define INSERT_OPERAND(FIELD, INSN, VALUE) \
923 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
924 #define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
925 INSERT_BITS ((INSN).insn_opcode, VALUE, \
926 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
928 /* Extract the operand given by FIELD from mips_cl_insn INSN. */
929 #define EXTRACT_OPERAND(FIELD, INSN) \
930 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
931 #define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
932 EXTRACT_BITS ((INSN).insn_opcode, \
933 MIPS16OP_MASK_##FIELD, \
936 /* Global variables used when generating relaxable macros. See the
937 comment above RELAX_ENCODE for more details about how relaxation
940 /* 0 if we're not emitting a relaxable macro.
941 1 if we're emitting the first of the two relaxation alternatives.
942 2 if we're emitting the second alternative. */
945 /* The first relaxable fixup in the current frag. (In other words,
946 the first fixup that refers to relaxable code.) */
949 /* sizes[0] says how many bytes of the first alternative are stored in
950 the current frag. Likewise sizes[1] for the second alternative. */
951 unsigned int sizes
[2];
953 /* The symbol on which the choice of sequence depends. */
957 /* Global variables used to decide whether a macro needs a warning. */
959 /* True if the macro is in a branch delay slot. */
960 bfd_boolean delay_slot_p
;
962 /* For relaxable macros, sizes[0] is the length of the first alternative
963 in bytes and sizes[1] is the length of the second alternative.
964 For non-relaxable macros, both elements give the length of the
966 unsigned int sizes
[2];
968 /* The first variant frag for this macro. */
970 } mips_macro_warning
;
972 /* Prototypes for static functions. */
974 #define internalError() \
975 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
977 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
979 static void append_insn
980 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
981 static void mips_no_prev_insn (void);
982 static void mips16_macro_build
983 (expressionS
*, const char *, const char *, va_list);
984 static void load_register (int, expressionS
*, int);
985 static void macro_start (void);
986 static void macro_end (void);
987 static void macro (struct mips_cl_insn
* ip
);
988 static void mips16_macro (struct mips_cl_insn
* ip
);
989 #ifdef LOSING_COMPILER
990 static void macro2 (struct mips_cl_insn
* ip
);
992 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
993 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
994 static void mips16_immed
995 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
996 unsigned long *, bfd_boolean
*, unsigned short *);
997 static size_t my_getSmallExpression
998 (expressionS
*, bfd_reloc_code_real_type
*, char *);
999 static void my_getExpression (expressionS
*, char *);
1000 static void s_align (int);
1001 static void s_change_sec (int);
1002 static void s_change_section (int);
1003 static void s_cons (int);
1004 static void s_float_cons (int);
1005 static void s_mips_globl (int);
1006 static void s_option (int);
1007 static void s_mipsset (int);
1008 static void s_abicalls (int);
1009 static void s_cpload (int);
1010 static void s_cpsetup (int);
1011 static void s_cplocal (int);
1012 static void s_cprestore (int);
1013 static void s_cpreturn (int);
1014 static void s_gpvalue (int);
1015 static void s_gpword (int);
1016 static void s_gpdword (int);
1017 static void s_cpadd (int);
1018 static void s_insn (int);
1019 static void md_obj_begin (void);
1020 static void md_obj_end (void);
1021 static void s_mips_ent (int);
1022 static void s_mips_end (int);
1023 static void s_mips_frame (int);
1024 static void s_mips_mask (int reg_type
);
1025 static void s_mips_stab (int);
1026 static void s_mips_weakext (int);
1027 static void s_mips_file (int);
1028 static void s_mips_loc (int);
1029 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
1030 static int relaxed_branch_length (fragS
*, asection
*, int);
1031 static int validate_mips_insn (const struct mips_opcode
*);
1033 /* Table and functions used to map between CPU/ISA names, and
1034 ISA levels, and CPU numbers. */
1036 struct mips_cpu_info
1038 const char *name
; /* CPU or ISA name. */
1039 int flags
; /* ASEs available, or ISA flag. */
1040 int isa
; /* ISA level. */
1041 int cpu
; /* CPU number (default CPU if ISA). */
1044 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1045 #define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1046 #define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1047 #define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1048 #define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1049 #define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1051 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
1052 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
1053 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
1057 The following pseudo-ops from the Kane and Heinrich MIPS book
1058 should be defined here, but are currently unsupported: .alias,
1059 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1061 The following pseudo-ops from the Kane and Heinrich MIPS book are
1062 specific to the type of debugging information being generated, and
1063 should be defined by the object format: .aent, .begin, .bend,
1064 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1067 The following pseudo-ops from the Kane and Heinrich MIPS book are
1068 not MIPS CPU specific, but are also not specific to the object file
1069 format. This file is probably the best place to define them, but
1070 they are not currently supported: .asm0, .endr, .lab, .repeat,
1073 static const pseudo_typeS mips_pseudo_table
[] =
1075 /* MIPS specific pseudo-ops. */
1076 {"option", s_option
, 0},
1077 {"set", s_mipsset
, 0},
1078 {"rdata", s_change_sec
, 'r'},
1079 {"sdata", s_change_sec
, 's'},
1080 {"livereg", s_ignore
, 0},
1081 {"abicalls", s_abicalls
, 0},
1082 {"cpload", s_cpload
, 0},
1083 {"cpsetup", s_cpsetup
, 0},
1084 {"cplocal", s_cplocal
, 0},
1085 {"cprestore", s_cprestore
, 0},
1086 {"cpreturn", s_cpreturn
, 0},
1087 {"gpvalue", s_gpvalue
, 0},
1088 {"gpword", s_gpword
, 0},
1089 {"gpdword", s_gpdword
, 0},
1090 {"cpadd", s_cpadd
, 0},
1091 {"insn", s_insn
, 0},
1093 /* Relatively generic pseudo-ops that happen to be used on MIPS
1095 {"asciiz", stringer
, 1},
1096 {"bss", s_change_sec
, 'b'},
1098 {"half", s_cons
, 1},
1099 {"dword", s_cons
, 3},
1100 {"weakext", s_mips_weakext
, 0},
1101 {"origin", s_org
, 0},
1102 {"repeat", s_rept
, 0},
1104 /* These pseudo-ops are defined in read.c, but must be overridden
1105 here for one reason or another. */
1106 {"align", s_align
, 0},
1107 {"byte", s_cons
, 0},
1108 {"data", s_change_sec
, 'd'},
1109 {"double", s_float_cons
, 'd'},
1110 {"float", s_float_cons
, 'f'},
1111 {"globl", s_mips_globl
, 0},
1112 {"global", s_mips_globl
, 0},
1113 {"hword", s_cons
, 1},
1115 {"long", s_cons
, 2},
1116 {"octa", s_cons
, 4},
1117 {"quad", s_cons
, 3},
1118 {"section", s_change_section
, 0},
1119 {"short", s_cons
, 1},
1120 {"single", s_float_cons
, 'f'},
1121 {"stabn", s_mips_stab
, 'n'},
1122 {"text", s_change_sec
, 't'},
1123 {"word", s_cons
, 2},
1125 { "extern", ecoff_directive_extern
, 0},
1130 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1132 /* These pseudo-ops should be defined by the object file format.
1133 However, a.out doesn't support them, so we have versions here. */
1134 {"aent", s_mips_ent
, 1},
1135 {"bgnb", s_ignore
, 0},
1136 {"end", s_mips_end
, 0},
1137 {"endb", s_ignore
, 0},
1138 {"ent", s_mips_ent
, 0},
1139 {"file", s_mips_file
, 0},
1140 {"fmask", s_mips_mask
, 'F'},
1141 {"frame", s_mips_frame
, 0},
1142 {"loc", s_mips_loc
, 0},
1143 {"mask", s_mips_mask
, 'R'},
1144 {"verstamp", s_ignore
, 0},
1148 extern void pop_insert (const pseudo_typeS
*);
1151 mips_pop_insert (void)
1153 pop_insert (mips_pseudo_table
);
1154 if (! ECOFF_DEBUGGING
)
1155 pop_insert (mips_nonecoff_pseudo_table
);
1158 /* Symbols labelling the current insn. */
1160 struct insn_label_list
1162 struct insn_label_list
*next
;
1166 static struct insn_label_list
*insn_labels
;
1167 static struct insn_label_list
*free_insn_labels
;
1169 static void mips_clear_insn_labels (void);
1172 mips_clear_insn_labels (void)
1174 register struct insn_label_list
**pl
;
1176 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1182 static char *expr_end
;
1184 /* Expressions which appear in instructions. These are set by
1187 static expressionS imm_expr
;
1188 static expressionS imm2_expr
;
1189 static expressionS offset_expr
;
1191 /* Relocs associated with imm_expr and offset_expr. */
1193 static bfd_reloc_code_real_type imm_reloc
[3]
1194 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1195 static bfd_reloc_code_real_type offset_reloc
[3]
1196 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1198 /* These are set by mips16_ip if an explicit extension is used. */
1200 static bfd_boolean mips16_small
, mips16_ext
;
1203 /* The pdr segment for per procedure frame/regmask info. Not used for
1206 static segT pdr_seg
;
1209 /* The default target format to use. */
1212 mips_target_format (void)
1214 switch (OUTPUT_FLAVOR
)
1216 case bfd_target_ecoff_flavour
:
1217 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1218 case bfd_target_coff_flavour
:
1220 case bfd_target_elf_flavour
:
1222 if (!HAVE_64BIT_OBJECTS
&& !HAVE_NEWABI
)
1223 return (target_big_endian
1224 ? "elf32-bigmips-vxworks"
1225 : "elf32-littlemips-vxworks");
1228 /* This is traditional mips. */
1229 return (target_big_endian
1230 ? (HAVE_64BIT_OBJECTS
1231 ? "elf64-tradbigmips"
1233 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1234 : (HAVE_64BIT_OBJECTS
1235 ? "elf64-tradlittlemips"
1237 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1239 return (target_big_endian
1240 ? (HAVE_64BIT_OBJECTS
1243 ? "elf32-nbigmips" : "elf32-bigmips"))
1244 : (HAVE_64BIT_OBJECTS
1245 ? "elf64-littlemips"
1247 ? "elf32-nlittlemips" : "elf32-littlemips")));
1255 /* Return the length of instruction INSN. */
1257 static inline unsigned int
1258 insn_length (const struct mips_cl_insn
*insn
)
1260 if (!mips_opts
.mips16
)
1262 return insn
->mips16_absolute_jump_p
|| insn
->use_extend
? 4 : 2;
1265 /* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1268 create_insn (struct mips_cl_insn
*insn
, const struct mips_opcode
*mo
)
1273 insn
->use_extend
= FALSE
;
1275 insn
->insn_opcode
= mo
->match
;
1278 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1279 insn
->fixp
[i
] = NULL
;
1280 insn
->fixed_p
= (mips_opts
.noreorder
> 0);
1281 insn
->noreorder_p
= (mips_opts
.noreorder
> 0);
1282 insn
->mips16_absolute_jump_p
= 0;
1285 /* Install INSN at the location specified by its "frag" and "where" fields. */
1288 install_insn (const struct mips_cl_insn
*insn
)
1290 char *f
= insn
->frag
->fr_literal
+ insn
->where
;
1291 if (!mips_opts
.mips16
)
1292 md_number_to_chars (f
, insn
->insn_opcode
, 4);
1293 else if (insn
->mips16_absolute_jump_p
)
1295 md_number_to_chars (f
, insn
->insn_opcode
>> 16, 2);
1296 md_number_to_chars (f
+ 2, insn
->insn_opcode
& 0xffff, 2);
1300 if (insn
->use_extend
)
1302 md_number_to_chars (f
, 0xf000 | insn
->extend
, 2);
1305 md_number_to_chars (f
, insn
->insn_opcode
, 2);
1309 /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1310 and install the opcode in the new location. */
1313 move_insn (struct mips_cl_insn
*insn
, fragS
*frag
, long where
)
1318 insn
->where
= where
;
1319 for (i
= 0; i
< ARRAY_SIZE (insn
->fixp
); i
++)
1320 if (insn
->fixp
[i
] != NULL
)
1322 insn
->fixp
[i
]->fx_frag
= frag
;
1323 insn
->fixp
[i
]->fx_where
= where
;
1325 install_insn (insn
);
1328 /* Add INSN to the end of the output. */
1331 add_fixed_insn (struct mips_cl_insn
*insn
)
1333 char *f
= frag_more (insn_length (insn
));
1334 move_insn (insn
, frag_now
, f
- frag_now
->fr_literal
);
1337 /* Start a variant frag and move INSN to the start of the variant part,
1338 marking it as fixed. The other arguments are as for frag_var. */
1341 add_relaxed_insn (struct mips_cl_insn
*insn
, int max_chars
, int var
,
1342 relax_substateT subtype
, symbolS
*symbol
, offsetT offset
)
1344 frag_grow (max_chars
);
1345 move_insn (insn
, frag_now
, frag_more (0) - frag_now
->fr_literal
);
1347 frag_var (rs_machine_dependent
, max_chars
, var
,
1348 subtype
, symbol
, offset
, NULL
);
1351 /* Insert N copies of INSN into the history buffer, starting at
1352 position FIRST. Neither FIRST nor N need to be clipped. */
1355 insert_into_history (unsigned int first
, unsigned int n
,
1356 const struct mips_cl_insn
*insn
)
1358 if (mips_relax
.sequence
!= 2)
1362 for (i
= ARRAY_SIZE (history
); i
-- > first
;)
1364 history
[i
] = history
[i
- n
];
1370 /* Emit a nop instruction, recording it in the history buffer. */
1375 add_fixed_insn (NOP_INSN
);
1376 insert_into_history (0, 1, NOP_INSN
);
1379 /* Initialize vr4120_conflicts. There is a bit of duplication here:
1380 the idea is to make it obvious at a glance that each errata is
1384 init_vr4120_conflicts (void)
1386 #define CONFLICT(FIRST, SECOND) \
1387 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1389 /* Errata 21 - [D]DIV[U] after [D]MACC */
1390 CONFLICT (MACC
, DIV
);
1391 CONFLICT (DMACC
, DIV
);
1393 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1394 CONFLICT (DMULT
, DMULT
);
1395 CONFLICT (DMULT
, DMACC
);
1396 CONFLICT (DMACC
, DMULT
);
1397 CONFLICT (DMACC
, DMACC
);
1399 /* Errata 24 - MT{LO,HI} after [D]MACC */
1400 CONFLICT (MACC
, MTHILO
);
1401 CONFLICT (DMACC
, MTHILO
);
1403 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1404 instruction is executed immediately after a MACC or DMACC
1405 instruction, the result of [either instruction] is incorrect." */
1406 CONFLICT (MACC
, MULT
);
1407 CONFLICT (MACC
, DMULT
);
1408 CONFLICT (DMACC
, MULT
);
1409 CONFLICT (DMACC
, DMULT
);
1411 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1412 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1413 DDIV or DDIVU instruction, the result of the MACC or
1414 DMACC instruction is incorrect.". */
1415 CONFLICT (DMULT
, MACC
);
1416 CONFLICT (DMULT
, DMACC
);
1417 CONFLICT (DIV
, MACC
);
1418 CONFLICT (DIV
, DMACC
);
1428 #define RTYPE_MASK 0x1ff00
1429 #define RTYPE_NUM 0x00100
1430 #define RTYPE_FPU 0x00200
1431 #define RTYPE_FCC 0x00400
1432 #define RTYPE_VEC 0x00800
1433 #define RTYPE_GP 0x01000
1434 #define RTYPE_CP0 0x02000
1435 #define RTYPE_PC 0x04000
1436 #define RTYPE_ACC 0x08000
1437 #define RTYPE_CCC 0x10000
1438 #define RNUM_MASK 0x000ff
1439 #define RWARN 0x80000
1441 #define GENERIC_REGISTER_NUMBERS \
1442 {"$0", RTYPE_NUM | 0}, \
1443 {"$1", RTYPE_NUM | 1}, \
1444 {"$2", RTYPE_NUM | 2}, \
1445 {"$3", RTYPE_NUM | 3}, \
1446 {"$4", RTYPE_NUM | 4}, \
1447 {"$5", RTYPE_NUM | 5}, \
1448 {"$6", RTYPE_NUM | 6}, \
1449 {"$7", RTYPE_NUM | 7}, \
1450 {"$8", RTYPE_NUM | 8}, \
1451 {"$9", RTYPE_NUM | 9}, \
1452 {"$10", RTYPE_NUM | 10}, \
1453 {"$11", RTYPE_NUM | 11}, \
1454 {"$12", RTYPE_NUM | 12}, \
1455 {"$13", RTYPE_NUM | 13}, \
1456 {"$14", RTYPE_NUM | 14}, \
1457 {"$15", RTYPE_NUM | 15}, \
1458 {"$16", RTYPE_NUM | 16}, \
1459 {"$17", RTYPE_NUM | 17}, \
1460 {"$18", RTYPE_NUM | 18}, \
1461 {"$19", RTYPE_NUM | 19}, \
1462 {"$20", RTYPE_NUM | 20}, \
1463 {"$21", RTYPE_NUM | 21}, \
1464 {"$22", RTYPE_NUM | 22}, \
1465 {"$23", RTYPE_NUM | 23}, \
1466 {"$24", RTYPE_NUM | 24}, \
1467 {"$25", RTYPE_NUM | 25}, \
1468 {"$26", RTYPE_NUM | 26}, \
1469 {"$27", RTYPE_NUM | 27}, \
1470 {"$28", RTYPE_NUM | 28}, \
1471 {"$29", RTYPE_NUM | 29}, \
1472 {"$30", RTYPE_NUM | 30}, \
1473 {"$31", RTYPE_NUM | 31}
1475 #define FPU_REGISTER_NAMES \
1476 {"$f0", RTYPE_FPU | 0}, \
1477 {"$f1", RTYPE_FPU | 1}, \
1478 {"$f2", RTYPE_FPU | 2}, \
1479 {"$f3", RTYPE_FPU | 3}, \
1480 {"$f4", RTYPE_FPU | 4}, \
1481 {"$f5", RTYPE_FPU | 5}, \
1482 {"$f6", RTYPE_FPU | 6}, \
1483 {"$f7", RTYPE_FPU | 7}, \
1484 {"$f8", RTYPE_FPU | 8}, \
1485 {"$f9", RTYPE_FPU | 9}, \
1486 {"$f10", RTYPE_FPU | 10}, \
1487 {"$f11", RTYPE_FPU | 11}, \
1488 {"$f12", RTYPE_FPU | 12}, \
1489 {"$f13", RTYPE_FPU | 13}, \
1490 {"$f14", RTYPE_FPU | 14}, \
1491 {"$f15", RTYPE_FPU | 15}, \
1492 {"$f16", RTYPE_FPU | 16}, \
1493 {"$f17", RTYPE_FPU | 17}, \
1494 {"$f18", RTYPE_FPU | 18}, \
1495 {"$f19", RTYPE_FPU | 19}, \
1496 {"$f20", RTYPE_FPU | 20}, \
1497 {"$f21", RTYPE_FPU | 21}, \
1498 {"$f22", RTYPE_FPU | 22}, \
1499 {"$f23", RTYPE_FPU | 23}, \
1500 {"$f24", RTYPE_FPU | 24}, \
1501 {"$f25", RTYPE_FPU | 25}, \
1502 {"$f26", RTYPE_FPU | 26}, \
1503 {"$f27", RTYPE_FPU | 27}, \
1504 {"$f28", RTYPE_FPU | 28}, \
1505 {"$f29", RTYPE_FPU | 29}, \
1506 {"$f30", RTYPE_FPU | 30}, \
1507 {"$f31", RTYPE_FPU | 31}
1509 #define FPU_CONDITION_CODE_NAMES \
1510 {"$fcc0", RTYPE_FCC | 0}, \
1511 {"$fcc1", RTYPE_FCC | 1}, \
1512 {"$fcc2", RTYPE_FCC | 2}, \
1513 {"$fcc3", RTYPE_FCC | 3}, \
1514 {"$fcc4", RTYPE_FCC | 4}, \
1515 {"$fcc5", RTYPE_FCC | 5}, \
1516 {"$fcc6", RTYPE_FCC | 6}, \
1517 {"$fcc7", RTYPE_FCC | 7}
1519 #define COPROC_CONDITION_CODE_NAMES \
1520 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1521 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1522 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1523 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1524 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1525 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1526 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1527 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1529 #define N32N64_SYMBOLIC_REGISTER_NAMES \
1530 {"$a4", RTYPE_GP | 8}, \
1531 {"$a5", RTYPE_GP | 9}, \
1532 {"$a6", RTYPE_GP | 10}, \
1533 {"$a7", RTYPE_GP | 11}, \
1534 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1535 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1536 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1537 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1538 {"$t0", RTYPE_GP | 12}, \
1539 {"$t1", RTYPE_GP | 13}, \
1540 {"$t2", RTYPE_GP | 14}, \
1541 {"$t3", RTYPE_GP | 15}
1543 #define O32_SYMBOLIC_REGISTER_NAMES \
1544 {"$t0", RTYPE_GP | 8}, \
1545 {"$t1", RTYPE_GP | 9}, \
1546 {"$t2", RTYPE_GP | 10}, \
1547 {"$t3", RTYPE_GP | 11}, \
1548 {"$t4", RTYPE_GP | 12}, \
1549 {"$t5", RTYPE_GP | 13}, \
1550 {"$t6", RTYPE_GP | 14}, \
1551 {"$t7", RTYPE_GP | 15}, \
1552 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1553 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1554 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1555 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1557 /* Remaining symbolic register names */
1558 #define SYMBOLIC_REGISTER_NAMES \
1559 {"$zero", RTYPE_GP | 0}, \
1560 {"$at", RTYPE_GP | 1}, \
1561 {"$AT", RTYPE_GP | 1}, \
1562 {"$v0", RTYPE_GP | 2}, \
1563 {"$v1", RTYPE_GP | 3}, \
1564 {"$a0", RTYPE_GP | 4}, \
1565 {"$a1", RTYPE_GP | 5}, \
1566 {"$a2", RTYPE_GP | 6}, \
1567 {"$a3", RTYPE_GP | 7}, \
1568 {"$s0", RTYPE_GP | 16}, \
1569 {"$s1", RTYPE_GP | 17}, \
1570 {"$s2", RTYPE_GP | 18}, \
1571 {"$s3", RTYPE_GP | 19}, \
1572 {"$s4", RTYPE_GP | 20}, \
1573 {"$s5", RTYPE_GP | 21}, \
1574 {"$s6", RTYPE_GP | 22}, \
1575 {"$s7", RTYPE_GP | 23}, \
1576 {"$t8", RTYPE_GP | 24}, \
1577 {"$t9", RTYPE_GP | 25}, \
1578 {"$k0", RTYPE_GP | 26}, \
1579 {"$kt0", RTYPE_GP | 26}, \
1580 {"$k1", RTYPE_GP | 27}, \
1581 {"$kt1", RTYPE_GP | 27}, \
1582 {"$gp", RTYPE_GP | 28}, \
1583 {"$sp", RTYPE_GP | 29}, \
1584 {"$s8", RTYPE_GP | 30}, \
1585 {"$fp", RTYPE_GP | 30}, \
1586 {"$ra", RTYPE_GP | 31}
1588 #define MIPS16_SPECIAL_REGISTER_NAMES \
1589 {"$pc", RTYPE_PC | 0}
1591 #define MDMX_VECTOR_REGISTER_NAMES \
1592 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1593 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1594 {"$v2", RTYPE_VEC | 2}, \
1595 {"$v3", RTYPE_VEC | 3}, \
1596 {"$v4", RTYPE_VEC | 4}, \
1597 {"$v5", RTYPE_VEC | 5}, \
1598 {"$v6", RTYPE_VEC | 6}, \
1599 {"$v7", RTYPE_VEC | 7}, \
1600 {"$v8", RTYPE_VEC | 8}, \
1601 {"$v9", RTYPE_VEC | 9}, \
1602 {"$v10", RTYPE_VEC | 10}, \
1603 {"$v11", RTYPE_VEC | 11}, \
1604 {"$v12", RTYPE_VEC | 12}, \
1605 {"$v13", RTYPE_VEC | 13}, \
1606 {"$v14", RTYPE_VEC | 14}, \
1607 {"$v15", RTYPE_VEC | 15}, \
1608 {"$v16", RTYPE_VEC | 16}, \
1609 {"$v17", RTYPE_VEC | 17}, \
1610 {"$v18", RTYPE_VEC | 18}, \
1611 {"$v19", RTYPE_VEC | 19}, \
1612 {"$v20", RTYPE_VEC | 20}, \
1613 {"$v21", RTYPE_VEC | 21}, \
1614 {"$v22", RTYPE_VEC | 22}, \
1615 {"$v23", RTYPE_VEC | 23}, \
1616 {"$v24", RTYPE_VEC | 24}, \
1617 {"$v25", RTYPE_VEC | 25}, \
1618 {"$v26", RTYPE_VEC | 26}, \
1619 {"$v27", RTYPE_VEC | 27}, \
1620 {"$v28", RTYPE_VEC | 28}, \
1621 {"$v29", RTYPE_VEC | 29}, \
1622 {"$v30", RTYPE_VEC | 30}, \
1623 {"$v31", RTYPE_VEC | 31}
1625 #define MIPS_DSP_ACCUMULATOR_NAMES \
1626 {"$ac0", RTYPE_ACC | 0}, \
1627 {"$ac1", RTYPE_ACC | 1}, \
1628 {"$ac2", RTYPE_ACC | 2}, \
1629 {"$ac3", RTYPE_ACC | 3}
1631 static const struct regname reg_names
[] = {
1632 GENERIC_REGISTER_NUMBERS
,
1634 FPU_CONDITION_CODE_NAMES
,
1635 COPROC_CONDITION_CODE_NAMES
,
1637 /* The $txx registers depends on the abi,
1638 these will be added later into the symbol table from
1639 one of the tables below once mips_abi is set after
1640 parsing of arguments from the command line. */
1641 SYMBOLIC_REGISTER_NAMES
,
1643 MIPS16_SPECIAL_REGISTER_NAMES
,
1644 MDMX_VECTOR_REGISTER_NAMES
,
1645 MIPS_DSP_ACCUMULATOR_NAMES
,
1649 static const struct regname reg_names_o32
[] = {
1650 O32_SYMBOLIC_REGISTER_NAMES
,
1654 static const struct regname reg_names_n32n64
[] = {
1655 N32N64_SYMBOLIC_REGISTER_NAMES
,
1660 reg_lookup (char **s
, unsigned int types
, unsigned int *regnop
)
1667 /* Find end of name. */
1669 if (is_name_beginner (*e
))
1671 while (is_part_of_name (*e
))
1674 /* Terminate name. */
1678 /* Look for a register symbol. */
1679 if ((symbolP
= symbol_find (*s
)) && S_GET_SEGMENT (symbolP
) == reg_section
)
1681 int r
= S_GET_VALUE (symbolP
);
1683 reg
= r
& RNUM_MASK
;
1684 else if ((types
& RTYPE_VEC
) && (r
& ~1) == (RTYPE_GP
| 2))
1685 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1686 reg
= (r
& RNUM_MASK
) - 2;
1688 /* Else see if this is a register defined in an itbl entry. */
1689 else if ((types
& RTYPE_GP
) && itbl_have_entries
)
1696 if (itbl_get_reg_val (n
, &r
))
1697 reg
= r
& RNUM_MASK
;
1700 /* Advance to next token if a register was recognised. */
1703 else if (types
& RWARN
)
1704 as_warn ("Unrecognized register name `%s'", *s
);
1712 /* This function is called once, at assembler startup time. It should set up
1713 all the tables, etc. that the MD part of the assembler will need. */
1718 register const char *retval
= NULL
;
1722 if (mips_pic
!= NO_PIC
)
1724 if (g_switch_seen
&& g_switch_value
!= 0)
1725 as_bad (_("-G may not be used in position-independent code"));
1729 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1730 as_warn (_("Could not set architecture and machine"));
1732 op_hash
= hash_new ();
1734 for (i
= 0; i
< NUMOPCODES
;)
1736 const char *name
= mips_opcodes
[i
].name
;
1738 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1741 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1742 mips_opcodes
[i
].name
, retval
);
1743 /* Probably a memory allocation problem? Give up now. */
1744 as_fatal (_("Broken assembler. No assembly attempted."));
1748 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1750 if (!validate_mips_insn (&mips_opcodes
[i
]))
1752 if (nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1754 create_insn (&nop_insn
, mips_opcodes
+ i
);
1755 nop_insn
.fixed_p
= 1;
1760 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1763 mips16_op_hash
= hash_new ();
1766 while (i
< bfd_mips16_num_opcodes
)
1768 const char *name
= mips16_opcodes
[i
].name
;
1770 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1772 as_fatal (_("internal: can't hash `%s': %s"),
1773 mips16_opcodes
[i
].name
, retval
);
1776 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1777 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1778 != mips16_opcodes
[i
].match
))
1780 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1781 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1784 if (mips16_nop_insn
.insn_mo
== NULL
&& strcmp (name
, "nop") == 0)
1786 create_insn (&mips16_nop_insn
, mips16_opcodes
+ i
);
1787 mips16_nop_insn
.fixed_p
= 1;
1791 while (i
< bfd_mips16_num_opcodes
1792 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1796 as_fatal (_("Broken assembler. No assembly attempted."));
1798 /* We add all the general register names to the symbol table. This
1799 helps us detect invalid uses of them. */
1800 for (i
= 0; reg_names
[i
].name
; i
++)
1801 symbol_table_insert (symbol_new (reg_names
[i
].name
, reg_section
,
1802 reg_names
[i
].num
, // & RNUM_MASK,
1803 &zero_address_frag
));
1805 for (i
= 0; reg_names_n32n64
[i
].name
; i
++)
1806 symbol_table_insert (symbol_new (reg_names_n32n64
[i
].name
, reg_section
,
1807 reg_names_n32n64
[i
].num
, // & RNUM_MASK,
1808 &zero_address_frag
));
1810 for (i
= 0; reg_names_o32
[i
].name
; i
++)
1811 symbol_table_insert (symbol_new (reg_names_o32
[i
].name
, reg_section
,
1812 reg_names_o32
[i
].num
, // & RNUM_MASK,
1813 &zero_address_frag
));
1815 mips_no_prev_insn ();
1818 mips_cprmask
[0] = 0;
1819 mips_cprmask
[1] = 0;
1820 mips_cprmask
[2] = 0;
1821 mips_cprmask
[3] = 0;
1823 /* set the default alignment for the text section (2**2) */
1824 record_alignment (text_section
, 2);
1826 bfd_set_gp_size (stdoutput
, g_switch_value
);
1829 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1831 /* On a native system other than VxWorks, sections must be aligned
1832 to 16 byte boundaries. When configured for an embedded ELF
1833 target, we don't bother. */
1834 if (strcmp (TARGET_OS
, "elf") != 0
1835 && strcmp (TARGET_OS
, "vxworks") != 0)
1837 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1838 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1839 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1842 /* Create a .reginfo section for register masks and a .mdebug
1843 section for debugging information. */
1851 subseg
= now_subseg
;
1853 /* The ABI says this section should be loaded so that the
1854 running program can access it. However, we don't load it
1855 if we are configured for an embedded target */
1856 flags
= SEC_READONLY
| SEC_DATA
;
1857 if (strcmp (TARGET_OS
, "elf") != 0)
1858 flags
|= SEC_ALLOC
| SEC_LOAD
;
1860 if (mips_abi
!= N64_ABI
)
1862 sec
= subseg_new (".reginfo", (subsegT
) 0);
1864 bfd_set_section_flags (stdoutput
, sec
, flags
);
1865 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1867 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1871 /* The 64-bit ABI uses a .MIPS.options section rather than
1872 .reginfo section. */
1873 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1874 bfd_set_section_flags (stdoutput
, sec
, flags
);
1875 bfd_set_section_alignment (stdoutput
, sec
, 3);
1877 /* Set up the option header. */
1879 Elf_Internal_Options opthdr
;
1882 opthdr
.kind
= ODK_REGINFO
;
1883 opthdr
.size
= (sizeof (Elf_External_Options
)
1884 + sizeof (Elf64_External_RegInfo
));
1887 f
= frag_more (sizeof (Elf_External_Options
));
1888 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1889 (Elf_External_Options
*) f
);
1891 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1895 if (ECOFF_DEBUGGING
)
1897 sec
= subseg_new (".mdebug", (subsegT
) 0);
1898 (void) bfd_set_section_flags (stdoutput
, sec
,
1899 SEC_HAS_CONTENTS
| SEC_READONLY
);
1900 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1902 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1904 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1905 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1906 SEC_READONLY
| SEC_RELOC
1908 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1911 subseg_set (seg
, subseg
);
1914 #endif /* OBJ_ELF */
1916 if (! ECOFF_DEBUGGING
)
1919 if (mips_fix_vr4120
)
1920 init_vr4120_conflicts ();
1926 if (! ECOFF_DEBUGGING
)
1931 md_assemble (char *str
)
1933 struct mips_cl_insn insn
;
1934 bfd_reloc_code_real_type unused_reloc
[3]
1935 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1937 imm_expr
.X_op
= O_absent
;
1938 imm2_expr
.X_op
= O_absent
;
1939 offset_expr
.X_op
= O_absent
;
1940 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1941 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1942 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1943 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1944 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1945 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1947 if (mips_opts
.mips16
)
1948 mips16_ip (str
, &insn
);
1951 mips_ip (str
, &insn
);
1952 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1953 str
, insn
.insn_opcode
));
1958 as_bad ("%s `%s'", insn_error
, str
);
1962 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1965 if (mips_opts
.mips16
)
1966 mips16_macro (&insn
);
1973 if (imm_expr
.X_op
!= O_absent
)
1974 append_insn (&insn
, &imm_expr
, imm_reloc
);
1975 else if (offset_expr
.X_op
!= O_absent
)
1976 append_insn (&insn
, &offset_expr
, offset_reloc
);
1978 append_insn (&insn
, NULL
, unused_reloc
);
1982 /* Return true if the given relocation might need a matching %lo().
1983 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1984 need a matching %lo() when applied to local symbols. */
1986 static inline bfd_boolean
1987 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1989 return (HAVE_IN_PLACE_ADDENDS
1990 && (reloc
== BFD_RELOC_HI16_S
1991 || reloc
== BFD_RELOC_MIPS16_HI16_S
1992 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
1993 all GOT16 relocations evaluate to "G". */
1994 || (reloc
== BFD_RELOC_MIPS_GOT16
&& mips_pic
!= VXWORKS_PIC
)));
1997 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
2000 static inline bfd_boolean
2001 fixup_has_matching_lo_p (fixS
*fixp
)
2003 return (fixp
->fx_next
!= NULL
2004 && (fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
2005 || fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
2006 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
2007 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
2010 /* See whether instruction IP reads register REG. CLASS is the type
2014 insn_uses_reg (const struct mips_cl_insn
*ip
, unsigned int reg
,
2015 enum mips_regclass
class)
2017 if (class == MIPS16_REG
)
2019 assert (mips_opts
.mips16
);
2020 reg
= mips16_to_32_reg_map
[reg
];
2021 class = MIPS_GR_REG
;
2024 /* Don't report on general register ZERO, since it never changes. */
2025 if (class == MIPS_GR_REG
&& reg
== ZERO
)
2028 if (class == MIPS_FP_REG
)
2030 assert (! mips_opts
.mips16
);
2031 /* If we are called with either $f0 or $f1, we must check $f0.
2032 This is not optimal, because it will introduce an unnecessary
2033 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
2034 need to distinguish reading both $f0 and $f1 or just one of
2035 them. Note that we don't have to check the other way,
2036 because there is no instruction that sets both $f0 and $f1
2037 and requires a delay. */
2038 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
2039 && ((EXTRACT_OPERAND (FS
, *ip
) & ~(unsigned) 1)
2040 == (reg
&~ (unsigned) 1)))
2042 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
2043 && ((EXTRACT_OPERAND (FT
, *ip
) & ~(unsigned) 1)
2044 == (reg
&~ (unsigned) 1)))
2047 else if (! mips_opts
.mips16
)
2049 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
2050 && EXTRACT_OPERAND (RS
, *ip
) == reg
)
2052 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
2053 && EXTRACT_OPERAND (RT
, *ip
) == reg
)
2058 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
2059 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, *ip
)] == reg
)
2061 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
2062 && mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RY
, *ip
)] == reg
)
2064 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
2065 && (mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
)]
2068 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
2070 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
2072 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
2074 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
2075 && MIPS16_EXTRACT_OPERAND (REGR32
, *ip
) == reg
)
2082 /* This function returns true if modifying a register requires a
2086 reg_needs_delay (unsigned int reg
)
2088 unsigned long prev_pinfo
;
2090 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2091 if (! mips_opts
.noreorder
2092 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2093 && ! gpr_interlocks
)
2094 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
2095 && ! cop_interlocks
)))
2097 /* A load from a coprocessor or from memory. All load delays
2098 delay the use of general register rt for one instruction. */
2099 /* Itbl support may require additional care here. */
2100 know (prev_pinfo
& INSN_WRITE_GPR_T
);
2101 if (reg
== EXTRACT_OPERAND (RT
, history
[0]))
2108 /* Move all labels in insn_labels to the current insertion point. */
2111 mips_move_labels (void)
2113 struct insn_label_list
*l
;
2116 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2118 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2119 symbol_set_frag (l
->label
, frag_now
);
2120 val
= (valueT
) frag_now_fix ();
2121 /* mips16 text labels are stored as odd. */
2122 if (mips_opts
.mips16
)
2124 S_SET_VALUE (l
->label
, val
);
2128 /* Mark instruction labels in mips16 mode. This permits the linker to
2129 handle them specially, such as generating jalx instructions when
2130 needed. We also make them odd for the duration of the assembly, in
2131 order to generate the right sort of code. We will make them even
2132 in the adjust_symtab routine, while leaving them marked. This is
2133 convenient for the debugger and the disassembler. The linker knows
2134 to make them odd again. */
2137 mips16_mark_labels (void)
2139 if (mips_opts
.mips16
)
2141 struct insn_label_list
*l
;
2144 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2147 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2148 S_SET_OTHER (l
->label
, STO_MIPS16
);
2150 val
= S_GET_VALUE (l
->label
);
2152 S_SET_VALUE (l
->label
, val
+ 1);
2157 /* End the current frag. Make it a variant frag and record the
2161 relax_close_frag (void)
2163 mips_macro_warning
.first_frag
= frag_now
;
2164 frag_var (rs_machine_dependent
, 0, 0,
2165 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
2166 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
2168 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
2169 mips_relax
.first_fixup
= 0;
2172 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
2173 See the comment above RELAX_ENCODE for more details. */
2176 relax_start (symbolS
*symbol
)
2178 assert (mips_relax
.sequence
== 0);
2179 mips_relax
.sequence
= 1;
2180 mips_relax
.symbol
= symbol
;
2183 /* Start generating the second version of a relaxable sequence.
2184 See the comment above RELAX_ENCODE for more details. */
2189 assert (mips_relax
.sequence
== 1);
2190 mips_relax
.sequence
= 2;
2193 /* End the current relaxable sequence. */
2198 assert (mips_relax
.sequence
== 2);
2199 relax_close_frag ();
2200 mips_relax
.sequence
= 0;
2203 /* Classify an instruction according to the FIX_VR4120_* enumeration.
2204 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
2205 by VR4120 errata. */
2208 classify_vr4120_insn (const char *name
)
2210 if (strncmp (name
, "macc", 4) == 0)
2211 return FIX_VR4120_MACC
;
2212 if (strncmp (name
, "dmacc", 5) == 0)
2213 return FIX_VR4120_DMACC
;
2214 if (strncmp (name
, "mult", 4) == 0)
2215 return FIX_VR4120_MULT
;
2216 if (strncmp (name
, "dmult", 5) == 0)
2217 return FIX_VR4120_DMULT
;
2218 if (strstr (name
, "div"))
2219 return FIX_VR4120_DIV
;
2220 if (strcmp (name
, "mtlo") == 0 || strcmp (name
, "mthi") == 0)
2221 return FIX_VR4120_MTHILO
;
2222 return NUM_FIX_VR4120_CLASSES
;
2225 /* Return the number of instructions that must separate INSN1 and INSN2,
2226 where INSN1 is the earlier instruction. Return the worst-case value
2227 for any INSN2 if INSN2 is null. */
2230 insns_between (const struct mips_cl_insn
*insn1
,
2231 const struct mips_cl_insn
*insn2
)
2233 unsigned long pinfo1
, pinfo2
;
2235 /* This function needs to know which pinfo flags are set for INSN2
2236 and which registers INSN2 uses. The former is stored in PINFO2 and
2237 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
2238 will have every flag set and INSN2_USES_REG will always return true. */
2239 pinfo1
= insn1
->insn_mo
->pinfo
;
2240 pinfo2
= insn2
? insn2
->insn_mo
->pinfo
: ~0U;
2242 #define INSN2_USES_REG(REG, CLASS) \
2243 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
2245 /* For most targets, write-after-read dependencies on the HI and LO
2246 registers must be separated by at least two instructions. */
2247 if (!hilo_interlocks
)
2249 if ((pinfo1
& INSN_READ_LO
) && (pinfo2
& INSN_WRITE_LO
))
2251 if ((pinfo1
& INSN_READ_HI
) && (pinfo2
& INSN_WRITE_HI
))
2255 /* If we're working around r7000 errata, there must be two instructions
2256 between an mfhi or mflo and any instruction that uses the result. */
2257 if (mips_7000_hilo_fix
2258 && MF_HILO_INSN (pinfo1
)
2259 && INSN2_USES_REG (EXTRACT_OPERAND (RD
, *insn1
), MIPS_GR_REG
))
2262 /* If working around VR4120 errata, check for combinations that need
2263 a single intervening instruction. */
2264 if (mips_fix_vr4120
)
2266 unsigned int class1
, class2
;
2268 class1
= classify_vr4120_insn (insn1
->insn_mo
->name
);
2269 if (class1
!= NUM_FIX_VR4120_CLASSES
&& vr4120_conflicts
[class1
] != 0)
2273 class2
= classify_vr4120_insn (insn2
->insn_mo
->name
);
2274 if (vr4120_conflicts
[class1
] & (1 << class2
))
2279 if (!mips_opts
.mips16
)
2281 /* Check for GPR or coprocessor load delays. All such delays
2282 are on the RT register. */
2283 /* Itbl support may require additional care here. */
2284 if ((!gpr_interlocks
&& (pinfo1
& INSN_LOAD_MEMORY_DELAY
))
2285 || (!cop_interlocks
&& (pinfo1
& INSN_LOAD_COPROC_DELAY
)))
2287 know (pinfo1
& INSN_WRITE_GPR_T
);
2288 if (INSN2_USES_REG (EXTRACT_OPERAND (RT
, *insn1
), MIPS_GR_REG
))
2292 /* Check for generic coprocessor hazards.
2294 This case is not handled very well. There is no special
2295 knowledge of CP0 handling, and the coprocessors other than
2296 the floating point unit are not distinguished at all. */
2297 /* Itbl support may require additional care here. FIXME!
2298 Need to modify this to include knowledge about
2299 user specified delays! */
2300 else if ((!cop_interlocks
&& (pinfo1
& INSN_COPROC_MOVE_DELAY
))
2301 || (!cop_mem_interlocks
&& (pinfo1
& INSN_COPROC_MEMORY_DELAY
)))
2303 /* Handle cases where INSN1 writes to a known general coprocessor
2304 register. There must be a one instruction delay before INSN2
2305 if INSN2 reads that register, otherwise no delay is needed. */
2306 if (pinfo1
& INSN_WRITE_FPR_T
)
2308 if (INSN2_USES_REG (EXTRACT_OPERAND (FT
, *insn1
), MIPS_FP_REG
))
2311 else if (pinfo1
& INSN_WRITE_FPR_S
)
2313 if (INSN2_USES_REG (EXTRACT_OPERAND (FS
, *insn1
), MIPS_FP_REG
))
2318 /* Read-after-write dependencies on the control registers
2319 require a two-instruction gap. */
2320 if ((pinfo1
& INSN_WRITE_COND_CODE
)
2321 && (pinfo2
& INSN_READ_COND_CODE
))
2324 /* We don't know exactly what INSN1 does. If INSN2 is
2325 also a coprocessor instruction, assume there must be
2326 a one instruction gap. */
2327 if (pinfo2
& INSN_COP
)
2332 /* Check for read-after-write dependencies on the coprocessor
2333 control registers in cases where INSN1 does not need a general
2334 coprocessor delay. This means that INSN1 is a floating point
2335 comparison instruction. */
2336 /* Itbl support may require additional care here. */
2337 else if (!cop_interlocks
2338 && (pinfo1
& INSN_WRITE_COND_CODE
)
2339 && (pinfo2
& INSN_READ_COND_CODE
))
2343 #undef INSN2_USES_REG
2348 /* Return the number of nops that would be needed to work around the
2349 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2350 the MAX_VR4130_NOPS instructions described by HISTORY. */
2353 nops_for_vr4130 (const struct mips_cl_insn
*history
,
2354 const struct mips_cl_insn
*insn
)
2358 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2359 are not affected by the errata. */
2361 && ((insn
->insn_mo
->pinfo
& (INSN_WRITE_HI
| INSN_WRITE_LO
)) == 0
2362 || strcmp (insn
->insn_mo
->name
, "mtlo") == 0
2363 || strcmp (insn
->insn_mo
->name
, "mthi") == 0))
2366 /* Search for the first MFLO or MFHI. */
2367 for (i
= 0; i
< MAX_VR4130_NOPS
; i
++)
2368 if (!history
[i
].noreorder_p
&& MF_HILO_INSN (history
[i
].insn_mo
->pinfo
))
2370 /* Extract the destination register. */
2371 if (mips_opts
.mips16
)
2372 reg
= mips16_to_32_reg_map
[MIPS16_EXTRACT_OPERAND (RX
, history
[i
])];
2374 reg
= EXTRACT_OPERAND (RD
, history
[i
]);
2376 /* No nops are needed if INSN reads that register. */
2377 if (insn
!= NULL
&& insn_uses_reg (insn
, reg
, MIPS_GR_REG
))
2380 /* ...or if any of the intervening instructions do. */
2381 for (j
= 0; j
< i
; j
++)
2382 if (insn_uses_reg (&history
[j
], reg
, MIPS_GR_REG
))
2385 return MAX_VR4130_NOPS
- i
;
2390 /* Return the number of nops that would be needed if instruction INSN
2391 immediately followed the MAX_NOPS instructions given by HISTORY,
2392 where HISTORY[0] is the most recent instruction. If INSN is null,
2393 return the worse-case number of nops for any instruction. */
2396 nops_for_insn (const struct mips_cl_insn
*history
,
2397 const struct mips_cl_insn
*insn
)
2399 int i
, nops
, tmp_nops
;
2402 for (i
= 0; i
< MAX_DELAY_NOPS
; i
++)
2403 if (!history
[i
].noreorder_p
)
2405 tmp_nops
= insns_between (history
+ i
, insn
) - i
;
2406 if (tmp_nops
> nops
)
2410 if (mips_fix_vr4130
)
2412 tmp_nops
= nops_for_vr4130 (history
, insn
);
2413 if (tmp_nops
> nops
)
2420 /* The variable arguments provide NUM_INSNS extra instructions that
2421 might be added to HISTORY. Return the largest number of nops that
2422 would be needed after the extended sequence. */
2425 nops_for_sequence (int num_insns
, const struct mips_cl_insn
*history
, ...)
2428 struct mips_cl_insn buffer
[MAX_NOPS
];
2429 struct mips_cl_insn
*cursor
;
2432 va_start (args
, history
);
2433 cursor
= buffer
+ num_insns
;
2434 memcpy (cursor
, history
, (MAX_NOPS
- num_insns
) * sizeof (*cursor
));
2435 while (cursor
> buffer
)
2436 *--cursor
= *va_arg (args
, const struct mips_cl_insn
*);
2438 nops
= nops_for_insn (buffer
, NULL
);
2443 /* Like nops_for_insn, but if INSN is a branch, take into account the
2444 worst-case delay for the branch target. */
2447 nops_for_insn_or_target (const struct mips_cl_insn
*history
,
2448 const struct mips_cl_insn
*insn
)
2452 nops
= nops_for_insn (history
, insn
);
2453 if (insn
->insn_mo
->pinfo
& (INSN_UNCOND_BRANCH_DELAY
2454 | INSN_COND_BRANCH_DELAY
2455 | INSN_COND_BRANCH_LIKELY
))
2457 tmp_nops
= nops_for_sequence (2, history
, insn
, NOP_INSN
);
2458 if (tmp_nops
> nops
)
2461 else if (mips_opts
.mips16
&& (insn
->insn_mo
->pinfo
& MIPS16_INSN_BRANCH
))
2463 tmp_nops
= nops_for_sequence (1, history
, insn
);
2464 if (tmp_nops
> nops
)
2470 /* Output an instruction. IP is the instruction information.
2471 ADDRESS_EXPR is an operand of the instruction to be used with
2475 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
2476 bfd_reloc_code_real_type
*reloc_type
)
2478 register unsigned long prev_pinfo
, pinfo
;
2479 relax_stateT prev_insn_frag_type
= 0;
2480 bfd_boolean relaxed_branch
= FALSE
;
2482 /* Mark instruction labels in mips16 mode. */
2483 mips16_mark_labels ();
2485 prev_pinfo
= history
[0].insn_mo
->pinfo
;
2486 pinfo
= ip
->insn_mo
->pinfo
;
2488 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2490 /* There are a lot of optimizations we could do that we don't.
2491 In particular, we do not, in general, reorder instructions.
2492 If you use gcc with optimization, it will reorder
2493 instructions and generally do much more optimization then we
2494 do here; repeating all that work in the assembler would only
2495 benefit hand written assembly code, and does not seem worth
2497 int nops
= (mips_optimize
== 0
2498 ? nops_for_insn (history
, NULL
)
2499 : nops_for_insn_or_target (history
, ip
));
2503 unsigned long old_frag_offset
;
2506 old_frag
= frag_now
;
2507 old_frag_offset
= frag_now_fix ();
2509 for (i
= 0; i
< nops
; i
++)
2514 listing_prev_line ();
2515 /* We may be at the start of a variant frag. In case we
2516 are, make sure there is enough space for the frag
2517 after the frags created by listing_prev_line. The
2518 argument to frag_grow here must be at least as large
2519 as the argument to all other calls to frag_grow in
2520 this file. We don't have to worry about being in the
2521 middle of a variant frag, because the variants insert
2522 all needed nop instructions themselves. */
2526 mips_move_labels ();
2528 #ifndef NO_ECOFF_DEBUGGING
2529 if (ECOFF_DEBUGGING
)
2530 ecoff_fix_loc (old_frag
, old_frag_offset
);
2534 else if (mips_relax
.sequence
!= 2 && prev_nop_frag
!= NULL
)
2536 /* Work out how many nops in prev_nop_frag are needed by IP. */
2537 int nops
= nops_for_insn_or_target (history
, ip
);
2538 assert (nops
<= prev_nop_frag_holds
);
2540 /* Enforce NOPS as a minimum. */
2541 if (nops
> prev_nop_frag_required
)
2542 prev_nop_frag_required
= nops
;
2544 if (prev_nop_frag_holds
== prev_nop_frag_required
)
2546 /* Settle for the current number of nops. Update the history
2547 accordingly (for the benefit of any future .set reorder code). */
2548 prev_nop_frag
= NULL
;
2549 insert_into_history (prev_nop_frag_since
,
2550 prev_nop_frag_holds
, NOP_INSN
);
2554 /* Allow this instruction to replace one of the nops that was
2555 tentatively added to prev_nop_frag. */
2556 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
2557 prev_nop_frag_holds
--;
2558 prev_nop_frag_since
++;
2563 /* The value passed to dwarf2_emit_insn is the distance between
2564 the beginning of the current instruction and the address that
2565 should be recorded in the debug tables. For MIPS16 debug info
2566 we want to use ISA-encoded addresses, so we pass -1 for an
2567 address higher by one than the current. */
2568 dwarf2_emit_insn (mips_opts
.mips16
? -1 : 0);
2571 /* Record the frag type before frag_var. */
2572 if (history
[0].frag
)
2573 prev_insn_frag_type
= history
[0].frag
->fr_type
;
2576 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2577 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2578 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2579 && mips_relax_branch
2580 /* Don't try branch relaxation within .set nomacro, or within
2581 .set noat if we use $at for PIC computations. If it turns
2582 out that the branch was out-of-range, we'll get an error. */
2583 && !mips_opts
.warn_about_macros
2584 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2585 && !mips_opts
.mips16
)
2587 relaxed_branch
= TRUE
;
2588 add_relaxed_insn (ip
, (relaxed_branch_length
2590 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2591 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1
2594 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2595 pinfo
& INSN_COND_BRANCH_LIKELY
,
2596 pinfo
& INSN_WRITE_GPR_31
,
2598 address_expr
->X_add_symbol
,
2599 address_expr
->X_add_number
);
2600 *reloc_type
= BFD_RELOC_UNUSED
;
2602 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2604 /* We need to set up a variant frag. */
2605 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2606 add_relaxed_insn (ip
, 4, 0,
2608 (*reloc_type
- BFD_RELOC_UNUSED
,
2609 mips16_small
, mips16_ext
,
2610 prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2611 history
[0].mips16_absolute_jump_p
),
2612 make_expr_symbol (address_expr
), 0);
2614 else if (mips_opts
.mips16
2616 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2618 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
) == 0)
2619 /* Make sure there is enough room to swap this instruction with
2620 a following jump instruction. */
2622 add_fixed_insn (ip
);
2626 if (mips_opts
.mips16
2627 && mips_opts
.noreorder
2628 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2629 as_warn (_("extended instruction in delay slot"));
2631 if (mips_relax
.sequence
)
2633 /* If we've reached the end of this frag, turn it into a variant
2634 frag and record the information for the instructions we've
2636 if (frag_room () < 4)
2637 relax_close_frag ();
2638 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2641 if (mips_relax
.sequence
!= 2)
2642 mips_macro_warning
.sizes
[0] += 4;
2643 if (mips_relax
.sequence
!= 1)
2644 mips_macro_warning
.sizes
[1] += 4;
2646 if (mips_opts
.mips16
)
2649 ip
->mips16_absolute_jump_p
= (*reloc_type
== BFD_RELOC_MIPS16_JMP
);
2651 add_fixed_insn (ip
);
2654 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2656 if (address_expr
->X_op
== O_constant
)
2660 switch (*reloc_type
)
2663 ip
->insn_opcode
|= address_expr
->X_add_number
;
2666 case BFD_RELOC_MIPS_HIGHEST
:
2667 tmp
= (address_expr
->X_add_number
+ 0x800080008000ull
) >> 48;
2668 ip
->insn_opcode
|= tmp
& 0xffff;
2671 case BFD_RELOC_MIPS_HIGHER
:
2672 tmp
= (address_expr
->X_add_number
+ 0x80008000ull
) >> 32;
2673 ip
->insn_opcode
|= tmp
& 0xffff;
2676 case BFD_RELOC_HI16_S
:
2677 tmp
= (address_expr
->X_add_number
+ 0x8000) >> 16;
2678 ip
->insn_opcode
|= tmp
& 0xffff;
2681 case BFD_RELOC_HI16
:
2682 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2685 case BFD_RELOC_UNUSED
:
2686 case BFD_RELOC_LO16
:
2687 case BFD_RELOC_MIPS_GOT_DISP
:
2688 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2691 case BFD_RELOC_MIPS_JMP
:
2692 if ((address_expr
->X_add_number
& 3) != 0)
2693 as_bad (_("jump to misaligned address (0x%lx)"),
2694 (unsigned long) address_expr
->X_add_number
);
2695 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2698 case BFD_RELOC_MIPS16_JMP
:
2699 if ((address_expr
->X_add_number
& 3) != 0)
2700 as_bad (_("jump to misaligned address (0x%lx)"),
2701 (unsigned long) address_expr
->X_add_number
);
2703 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2704 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2705 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2708 case BFD_RELOC_16_PCREL_S2
:
2709 if ((address_expr
->X_add_number
& 3) != 0)
2710 as_bad (_("branch to misaligned address (0x%lx)"),
2711 (unsigned long) address_expr
->X_add_number
);
2712 if (mips_relax_branch
)
2714 if ((address_expr
->X_add_number
+ 0x20000) & ~0x3ffff)
2715 as_bad (_("branch address range overflow (0x%lx)"),
2716 (unsigned long) address_expr
->X_add_number
);
2717 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0xffff;
2724 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2727 reloc_howto_type
*howto
;
2730 /* In a compound relocation, it is the final (outermost)
2731 operator that determines the relocated field. */
2732 for (i
= 1; i
< 3; i
++)
2733 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2736 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2737 ip
->fixp
[0] = fix_new_exp (ip
->frag
, ip
->where
,
2738 bfd_get_reloc_size (howto
),
2740 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2743 /* These relocations can have an addend that won't fit in
2744 4 octets for 64bit assembly. */
2746 && ! howto
->partial_inplace
2747 && (reloc_type
[0] == BFD_RELOC_16
2748 || reloc_type
[0] == BFD_RELOC_32
2749 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2750 || reloc_type
[0] == BFD_RELOC_HI16_S
2751 || reloc_type
[0] == BFD_RELOC_LO16
2752 || reloc_type
[0] == BFD_RELOC_GPREL16
2753 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2754 || reloc_type
[0] == BFD_RELOC_GPREL32
2755 || reloc_type
[0] == BFD_RELOC_64
2756 || reloc_type
[0] == BFD_RELOC_CTOR
2757 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2758 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2759 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2760 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2761 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2762 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
2763 || reloc_type
[0] == BFD_RELOC_MIPS16_GPREL
2764 || reloc_type
[0] == BFD_RELOC_MIPS16_HI16_S
2765 || reloc_type
[0] == BFD_RELOC_MIPS16_LO16
))
2766 ip
->fixp
[0]->fx_no_overflow
= 1;
2768 if (mips_relax
.sequence
)
2770 if (mips_relax
.first_fixup
== 0)
2771 mips_relax
.first_fixup
= ip
->fixp
[0];
2773 else if (reloc_needs_lo_p (*reloc_type
))
2775 struct mips_hi_fixup
*hi_fixup
;
2777 /* Reuse the last entry if it already has a matching %lo. */
2778 hi_fixup
= mips_hi_fixup_list
;
2780 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2782 hi_fixup
= ((struct mips_hi_fixup
*)
2783 xmalloc (sizeof (struct mips_hi_fixup
)));
2784 hi_fixup
->next
= mips_hi_fixup_list
;
2785 mips_hi_fixup_list
= hi_fixup
;
2787 hi_fixup
->fixp
= ip
->fixp
[0];
2788 hi_fixup
->seg
= now_seg
;
2791 /* Add fixups for the second and third relocations, if given.
2792 Note that the ABI allows the second relocation to be
2793 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2794 moment we only use RSS_UNDEF, but we could add support
2795 for the others if it ever becomes necessary. */
2796 for (i
= 1; i
< 3; i
++)
2797 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2799 ip
->fixp
[i
] = fix_new (ip
->frag
, ip
->where
,
2800 ip
->fixp
[0]->fx_size
, NULL
, 0,
2801 FALSE
, reloc_type
[i
]);
2803 /* Use fx_tcbit to mark compound relocs. */
2804 ip
->fixp
[0]->fx_tcbit
= 1;
2805 ip
->fixp
[i
]->fx_tcbit
= 1;
2811 /* Update the register mask information. */
2812 if (! mips_opts
.mips16
)
2814 if (pinfo
& INSN_WRITE_GPR_D
)
2815 mips_gprmask
|= 1 << EXTRACT_OPERAND (RD
, *ip
);
2816 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2817 mips_gprmask
|= 1 << EXTRACT_OPERAND (RT
, *ip
);
2818 if (pinfo
& INSN_READ_GPR_S
)
2819 mips_gprmask
|= 1 << EXTRACT_OPERAND (RS
, *ip
);
2820 if (pinfo
& INSN_WRITE_GPR_31
)
2821 mips_gprmask
|= 1 << RA
;
2822 if (pinfo
& INSN_WRITE_FPR_D
)
2823 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FD
, *ip
);
2824 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2825 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FS
, *ip
);
2826 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2827 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FT
, *ip
);
2828 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2829 mips_cprmask
[1] |= 1 << EXTRACT_OPERAND (FR
, *ip
);
2830 if (pinfo
& INSN_COP
)
2832 /* We don't keep enough information to sort these cases out.
2833 The itbl support does keep this information however, although
2834 we currently don't support itbl fprmats as part of the cop
2835 instruction. May want to add this support in the future. */
2837 /* Never set the bit for $0, which is always zero. */
2838 mips_gprmask
&= ~1 << 0;
2842 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2843 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RX
, *ip
);
2844 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2845 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RY
, *ip
);
2846 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2847 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
2848 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2849 mips_gprmask
|= 1 << TREG
;
2850 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2851 mips_gprmask
|= 1 << SP
;
2852 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2853 mips_gprmask
|= 1 << RA
;
2854 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2855 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2856 if (pinfo
& MIPS16_INSN_READ_Z
)
2857 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z
, *ip
);
2858 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2859 mips_gprmask
|= 1 << MIPS16_EXTRACT_OPERAND (REGR32
, *ip
);
2862 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2864 /* Filling the branch delay slot is more complex. We try to
2865 switch the branch with the previous instruction, which we can
2866 do if the previous instruction does not set up a condition
2867 that the branch tests and if the branch is not itself the
2868 target of any branch. */
2869 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2870 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2872 if (mips_optimize
< 2
2873 /* If we have seen .set volatile or .set nomove, don't
2875 || mips_opts
.nomove
!= 0
2876 /* We can't swap if the previous instruction's position
2878 || history
[0].fixed_p
2879 /* If the previous previous insn was in a .set
2880 noreorder, we can't swap. Actually, the MIPS
2881 assembler will swap in this situation. However, gcc
2882 configured -with-gnu-as will generate code like
2888 in which we can not swap the bne and INSN. If gcc is
2889 not configured -with-gnu-as, it does not output the
2891 || history
[1].noreorder_p
2892 /* If the branch is itself the target of a branch, we
2893 can not swap. We cheat on this; all we check for is
2894 whether there is a label on this instruction. If
2895 there are any branches to anything other than a
2896 label, users must use .set noreorder. */
2897 || insn_labels
!= NULL
2898 /* If the previous instruction is in a variant frag
2899 other than this branch's one, we cannot do the swap.
2900 This does not apply to the mips16, which uses variant
2901 frags for different purposes. */
2902 || (! mips_opts
.mips16
2903 && prev_insn_frag_type
== rs_machine_dependent
)
2904 /* Check for conflicts between the branch and the instructions
2905 before the candidate delay slot. */
2906 || nops_for_insn (history
+ 1, ip
) > 0
2907 /* Check for conflicts between the swapped sequence and the
2908 target of the branch. */
2909 || nops_for_sequence (2, history
+ 1, ip
, history
) > 0
2910 /* We do not swap with a trap instruction, since it
2911 complicates trap handlers to have the trap
2912 instruction be in a delay slot. */
2913 || (prev_pinfo
& INSN_TRAP
)
2914 /* If the branch reads a register that the previous
2915 instruction sets, we can not swap. */
2916 || (! mips_opts
.mips16
2917 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2918 && insn_uses_reg (ip
, EXTRACT_OPERAND (RT
, history
[0]),
2920 || (! mips_opts
.mips16
2921 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2922 && insn_uses_reg (ip
, EXTRACT_OPERAND (RD
, history
[0]),
2924 || (mips_opts
.mips16
2925 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2927 (ip
, MIPS16_EXTRACT_OPERAND (RX
, history
[0]),
2929 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2931 (ip
, MIPS16_EXTRACT_OPERAND (RY
, history
[0]),
2933 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2935 (ip
, MIPS16_EXTRACT_OPERAND (RZ
, history
[0]),
2937 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2938 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2939 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2940 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2941 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2942 && insn_uses_reg (ip
,
2943 MIPS16OP_EXTRACT_REG32R
2944 (history
[0].insn_opcode
),
2946 /* If the branch writes a register that the previous
2947 instruction sets, we can not swap (we know that
2948 branches write only to RD or to $31). */
2949 || (! mips_opts
.mips16
2950 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2951 && (((pinfo
& INSN_WRITE_GPR_D
)
2952 && (EXTRACT_OPERAND (RT
, history
[0])
2953 == EXTRACT_OPERAND (RD
, *ip
)))
2954 || ((pinfo
& INSN_WRITE_GPR_31
)
2955 && EXTRACT_OPERAND (RT
, history
[0]) == RA
)))
2956 || (! mips_opts
.mips16
2957 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2958 && (((pinfo
& INSN_WRITE_GPR_D
)
2959 && (EXTRACT_OPERAND (RD
, history
[0])
2960 == EXTRACT_OPERAND (RD
, *ip
)))
2961 || ((pinfo
& INSN_WRITE_GPR_31
)
2962 && EXTRACT_OPERAND (RD
, history
[0]) == RA
)))
2963 || (mips_opts
.mips16
2964 && (pinfo
& MIPS16_INSN_WRITE_31
)
2965 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2966 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2967 && (MIPS16OP_EXTRACT_REG32R (history
[0].insn_opcode
)
2969 /* If the branch writes a register that the previous
2970 instruction reads, we can not swap (we know that
2971 branches only write to RD or to $31). */
2972 || (! mips_opts
.mips16
2973 && (pinfo
& INSN_WRITE_GPR_D
)
2974 && insn_uses_reg (&history
[0],
2975 EXTRACT_OPERAND (RD
, *ip
),
2977 || (! mips_opts
.mips16
2978 && (pinfo
& INSN_WRITE_GPR_31
)
2979 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2980 || (mips_opts
.mips16
2981 && (pinfo
& MIPS16_INSN_WRITE_31
)
2982 && insn_uses_reg (&history
[0], RA
, MIPS_GR_REG
))
2983 /* If one instruction sets a condition code and the
2984 other one uses a condition code, we can not swap. */
2985 || ((pinfo
& INSN_READ_COND_CODE
)
2986 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2987 || ((pinfo
& INSN_WRITE_COND_CODE
)
2988 && (prev_pinfo
& INSN_READ_COND_CODE
))
2989 /* If the previous instruction uses the PC, we can not
2991 || (mips_opts
.mips16
2992 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2993 /* If the previous instruction had a fixup in mips16
2994 mode, we can not swap. This normally means that the
2995 previous instruction was a 4 byte branch anyhow. */
2996 || (mips_opts
.mips16
&& history
[0].fixp
[0])
2997 /* If the previous instruction is a sync, sync.l, or
2998 sync.p, we can not swap. */
2999 || (prev_pinfo
& INSN_SYNC
))
3001 if (mips_opts
.mips16
3002 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3003 && (pinfo
& (MIPS16_INSN_READ_X
| MIPS16_INSN_READ_31
))
3004 && (mips_opts
.isa
== ISA_MIPS32
3005 || mips_opts
.isa
== ISA_MIPS32R2
3006 || mips_opts
.isa
== ISA_MIPS64
3007 || mips_opts
.isa
== ISA_MIPS64R2
))
3009 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3010 ip
->insn_opcode
|= 0x0080;
3012 insert_into_history (0, 1, ip
);
3016 /* We could do even better for unconditional branches to
3017 portions of this object file; we could pick up the
3018 instruction at the destination, put it in the delay
3019 slot, and bump the destination address. */
3020 insert_into_history (0, 1, ip
);
3024 if (mips_relax
.sequence
)
3025 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
3029 /* It looks like we can actually do the swap. */
3030 struct mips_cl_insn delay
= history
[0];
3031 if (mips_opts
.mips16
)
3033 know (delay
.frag
== ip
->frag
);
3034 move_insn (ip
, delay
.frag
, delay
.where
);
3035 move_insn (&delay
, ip
->frag
, ip
->where
+ insn_length (ip
));
3037 else if (relaxed_branch
)
3039 /* Add the delay slot instruction to the end of the
3040 current frag and shrink the fixed part of the
3041 original frag. If the branch occupies the tail of
3042 the latter, move it backwards to cover the gap. */
3043 delay
.frag
->fr_fix
-= 4;
3044 if (delay
.frag
== ip
->frag
)
3045 move_insn (ip
, ip
->frag
, ip
->where
- 4);
3046 add_fixed_insn (&delay
);
3050 move_insn (&delay
, ip
->frag
, ip
->where
);
3051 move_insn (ip
, history
[0].frag
, history
[0].where
);
3055 insert_into_history (0, 1, &delay
);
3058 /* If that was an unconditional branch, forget the previous
3059 insn information. */
3060 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
3061 mips_no_prev_insn ();
3063 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
3065 /* We don't yet optimize a branch likely. What we should do
3066 is look at the target, copy the instruction found there
3067 into the delay slot, and increment the branch to jump to
3068 the next instruction. */
3069 insert_into_history (0, 1, ip
);
3073 insert_into_history (0, 1, ip
);
3076 insert_into_history (0, 1, ip
);
3078 /* We just output an insn, so the next one doesn't have a label. */
3079 mips_clear_insn_labels ();
3082 /* Forget that there was any previous instruction or label. */
3085 mips_no_prev_insn (void)
3087 prev_nop_frag
= NULL
;
3088 insert_into_history (0, ARRAY_SIZE (history
), NOP_INSN
);
3089 mips_clear_insn_labels ();
3092 /* This function must be called before we emit something other than
3093 instructions. It is like mips_no_prev_insn except that it inserts
3094 any NOPS that might be needed by previous instructions. */
3097 mips_emit_delays (void)
3099 if (! mips_opts
.noreorder
)
3101 int nops
= nops_for_insn (history
, NULL
);
3105 add_fixed_insn (NOP_INSN
);
3106 mips_move_labels ();
3109 mips_no_prev_insn ();
3112 /* Start a (possibly nested) noreorder block. */
3115 start_noreorder (void)
3117 if (mips_opts
.noreorder
== 0)
3122 /* None of the instructions before the .set noreorder can be moved. */
3123 for (i
= 0; i
< ARRAY_SIZE (history
); i
++)
3124 history
[i
].fixed_p
= 1;
3126 /* Insert any nops that might be needed between the .set noreorder
3127 block and the previous instructions. We will later remove any
3128 nops that turn out not to be needed. */
3129 nops
= nops_for_insn (history
, NULL
);
3132 if (mips_optimize
!= 0)
3134 /* Record the frag which holds the nop instructions, so
3135 that we can remove them if we don't need them. */
3136 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
3137 prev_nop_frag
= frag_now
;
3138 prev_nop_frag_holds
= nops
;
3139 prev_nop_frag_required
= 0;
3140 prev_nop_frag_since
= 0;
3143 for (; nops
> 0; --nops
)
3144 add_fixed_insn (NOP_INSN
);
3146 /* Move on to a new frag, so that it is safe to simply
3147 decrease the size of prev_nop_frag. */
3148 frag_wane (frag_now
);
3150 mips_move_labels ();
3152 mips16_mark_labels ();
3153 mips_clear_insn_labels ();
3155 mips_opts
.noreorder
++;
3156 mips_any_noreorder
= 1;
3159 /* End a nested noreorder block. */
3162 end_noreorder (void)
3164 mips_opts
.noreorder
--;
3165 if (mips_opts
.noreorder
== 0 && prev_nop_frag
!= NULL
)
3167 /* Commit to inserting prev_nop_frag_required nops and go back to
3168 handling nop insertion the .set reorder way. */
3169 prev_nop_frag
->fr_fix
-= ((prev_nop_frag_holds
- prev_nop_frag_required
)
3170 * (mips_opts
.mips16
? 2 : 4));
3171 insert_into_history (prev_nop_frag_since
,
3172 prev_nop_frag_required
, NOP_INSN
);
3173 prev_nop_frag
= NULL
;
3177 /* Set up global variables for the start of a new macro. */
3182 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
3183 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
3184 && (history
[0].insn_mo
->pinfo
3185 & (INSN_UNCOND_BRANCH_DELAY
3186 | INSN_COND_BRANCH_DELAY
3187 | INSN_COND_BRANCH_LIKELY
)) != 0);
3190 /* Given that a macro is longer than 4 bytes, return the appropriate warning
3191 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
3192 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
3195 macro_warning (relax_substateT subtype
)
3197 if (subtype
& RELAX_DELAY_SLOT
)
3198 return _("Macro instruction expanded into multiple instructions"
3199 " in a branch delay slot");
3200 else if (subtype
& RELAX_NOMACRO
)
3201 return _("Macro instruction expanded into multiple instructions");
3206 /* Finish up a macro. Emit warnings as appropriate. */
3211 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
3213 relax_substateT subtype
;
3215 /* Set up the relaxation warning flags. */
3217 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
3218 subtype
|= RELAX_SECOND_LONGER
;
3219 if (mips_opts
.warn_about_macros
)
3220 subtype
|= RELAX_NOMACRO
;
3221 if (mips_macro_warning
.delay_slot_p
)
3222 subtype
|= RELAX_DELAY_SLOT
;
3224 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
3226 /* Either the macro has a single implementation or both
3227 implementations are longer than 4 bytes. Emit the
3229 const char *msg
= macro_warning (subtype
);
3235 /* One implementation might need a warning but the other
3236 definitely doesn't. */
3237 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
3242 /* Read a macro's relocation codes from *ARGS and store them in *R.
3243 The first argument in *ARGS will be either the code for a single
3244 relocation or -1 followed by the three codes that make up a
3245 composite relocation. */
3248 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
3252 next
= va_arg (*args
, int);
3254 r
[0] = (bfd_reloc_code_real_type
) next
;
3256 for (i
= 0; i
< 3; i
++)
3257 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
3260 /* Build an instruction created by a macro expansion. This is passed
3261 a pointer to the count of instructions created so far, an
3262 expression, the name of the instruction to build, an operand format
3263 string, and corresponding arguments. */
3266 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3268 const struct mips_opcode
*mo
;
3269 struct mips_cl_insn insn
;
3270 bfd_reloc_code_real_type r
[3];
3273 va_start (args
, fmt
);
3275 if (mips_opts
.mips16
)
3277 mips16_macro_build (ep
, name
, fmt
, args
);
3282 r
[0] = BFD_RELOC_UNUSED
;
3283 r
[1] = BFD_RELOC_UNUSED
;
3284 r
[2] = BFD_RELOC_UNUSED
;
3285 mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3287 assert (strcmp (name
, mo
->name
) == 0);
3289 /* Search until we get a match for NAME. It is assumed here that
3290 macros will never generate MDMX, MIPS-3D, DSP or MT instructions. */
3291 while (strcmp (fmt
, mo
->args
) != 0
3292 || mo
->pinfo
== INSN_MACRO
3293 || !OPCODE_IS_MEMBER (mo
,
3295 | (mips_opts
.mips16
? INSN_MIPS16
: 0)
3296 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
3298 || (mips_opts
.arch
== CPU_R4650
&& (mo
->pinfo
& FP_D
) != 0))
3302 assert (strcmp (name
, mo
->name
) == 0);
3305 create_insn (&insn
, mo
);
3323 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3328 /* Note that in the macro case, these arguments are already
3329 in MSB form. (When handling the instruction in the
3330 non-macro case, these arguments are sizes from which
3331 MSB values must be calculated.) */
3332 INSERT_OPERAND (INSMSB
, insn
, va_arg (args
, int));
3338 /* Note that in the macro case, these arguments are already
3339 in MSBD form. (When handling the instruction in the
3340 non-macro case, these arguments are sizes from which
3341 MSBD values must be calculated.) */
3342 INSERT_OPERAND (EXTMSBD
, insn
, va_arg (args
, int));
3353 INSERT_OPERAND (RT
, insn
, va_arg (args
, int));
3357 INSERT_OPERAND (CODE
, insn
, va_arg (args
, int));
3362 INSERT_OPERAND (FT
, insn
, va_arg (args
, int));
3368 INSERT_OPERAND (RD
, insn
, va_arg (args
, int));
3373 int tmp
= va_arg (args
, int);
3375 INSERT_OPERAND (RT
, insn
, tmp
);
3376 INSERT_OPERAND (RD
, insn
, tmp
);
3382 INSERT_OPERAND (FS
, insn
, va_arg (args
, int));
3389 INSERT_OPERAND (SHAMT
, insn
, va_arg (args
, int));
3393 INSERT_OPERAND (FD
, insn
, va_arg (args
, int));
3397 INSERT_OPERAND (CODE20
, insn
, va_arg (args
, int));
3401 INSERT_OPERAND (CODE19
, insn
, va_arg (args
, int));
3405 INSERT_OPERAND (CODE2
, insn
, va_arg (args
, int));
3412 INSERT_OPERAND (RS
, insn
, va_arg (args
, int));
3418 macro_read_relocs (&args
, r
);
3419 assert (*r
== BFD_RELOC_GPREL16
3420 || *r
== BFD_RELOC_MIPS_LITERAL
3421 || *r
== BFD_RELOC_MIPS_HIGHER
3422 || *r
== BFD_RELOC_HI16_S
3423 || *r
== BFD_RELOC_LO16
3424 || *r
== BFD_RELOC_MIPS_GOT16
3425 || *r
== BFD_RELOC_MIPS_CALL16
3426 || *r
== BFD_RELOC_MIPS_GOT_DISP
3427 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3428 || *r
== BFD_RELOC_MIPS_GOT_OFST
3429 || *r
== BFD_RELOC_MIPS_GOT_LO16
3430 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3434 macro_read_relocs (&args
, r
);
3436 && (ep
->X_op
== O_constant
3437 || (ep
->X_op
== O_symbol
3438 && (*r
== BFD_RELOC_MIPS_HIGHEST
3439 || *r
== BFD_RELOC_HI16_S
3440 || *r
== BFD_RELOC_HI16
3441 || *r
== BFD_RELOC_GPREL16
3442 || *r
== BFD_RELOC_MIPS_GOT_HI16
3443 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3447 assert (ep
!= NULL
);
3450 * This allows macro() to pass an immediate expression for
3451 * creating short branches without creating a symbol.
3453 * We don't allow branch relaxation for these branches, as
3454 * they should only appear in ".set nomacro" anyway.
3456 if (ep
->X_op
== O_constant
)
3458 if ((ep
->X_add_number
& 3) != 0)
3459 as_bad (_("branch to misaligned address (0x%lx)"),
3460 (unsigned long) ep
->X_add_number
);
3461 if ((ep
->X_add_number
+ 0x20000) & ~0x3ffff)
3462 as_bad (_("branch address range overflow (0x%lx)"),
3463 (unsigned long) ep
->X_add_number
);
3464 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3468 *r
= BFD_RELOC_16_PCREL_S2
;
3472 assert (ep
!= NULL
);
3473 *r
= BFD_RELOC_MIPS_JMP
;
3477 INSERT_OPERAND (COPZ
, insn
, va_arg (args
, unsigned long));
3481 INSERT_OPERAND (CACHE
, insn
, va_arg (args
, unsigned long));
3490 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3492 append_insn (&insn
, ep
, r
);
3496 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3499 struct mips_opcode
*mo
;
3500 struct mips_cl_insn insn
;
3501 bfd_reloc_code_real_type r
[3]
3502 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3504 mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3506 assert (strcmp (name
, mo
->name
) == 0);
3508 while (strcmp (fmt
, mo
->args
) != 0 || mo
->pinfo
== INSN_MACRO
)
3512 assert (strcmp (name
, mo
->name
) == 0);
3515 create_insn (&insn
, mo
);
3533 MIPS16_INSERT_OPERAND (RY
, insn
, va_arg (args
, int));
3538 MIPS16_INSERT_OPERAND (RX
, insn
, va_arg (args
, int));
3542 MIPS16_INSERT_OPERAND (RZ
, insn
, va_arg (args
, int));
3546 MIPS16_INSERT_OPERAND (MOVE32Z
, insn
, va_arg (args
, int));
3556 MIPS16_INSERT_OPERAND (REGR32
, insn
, va_arg (args
, int));
3563 regno
= va_arg (args
, int);
3564 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3565 MIPS16_INSERT_OPERAND (REG32R
, insn
, regno
);
3586 assert (ep
!= NULL
);
3588 if (ep
->X_op
!= O_constant
)
3589 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3592 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3593 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3596 *r
= BFD_RELOC_UNUSED
;
3602 MIPS16_INSERT_OPERAND (IMM6
, insn
, va_arg (args
, int));
3609 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3611 append_insn (&insn
, ep
, r
);
3615 * Sign-extend 32-bit mode constants that have bit 31 set and all
3616 * higher bits unset.
3619 normalize_constant_expr (expressionS
*ex
)
3621 if (ex
->X_op
== O_constant
3622 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3623 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3628 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3629 * all higher bits unset.
3632 normalize_address_expr (expressionS
*ex
)
3634 if (((ex
->X_op
== O_constant
&& HAVE_32BIT_ADDRESSES
)
3635 || (ex
->X_op
== O_symbol
&& HAVE_32BIT_SYMBOLS
))
3636 && IS_ZEXT_32BIT_NUM (ex
->X_add_number
))
3637 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3642 * Generate a "jalr" instruction with a relocation hint to the called
3643 * function. This occurs in NewABI PIC code.
3646 macro_build_jalr (expressionS
*ep
)
3655 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3657 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3658 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3662 * Generate a "lui" instruction.
3665 macro_build_lui (expressionS
*ep
, int regnum
)
3667 expressionS high_expr
;
3668 const struct mips_opcode
*mo
;
3669 struct mips_cl_insn insn
;
3670 bfd_reloc_code_real_type r
[3]
3671 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3672 const char *name
= "lui";
3673 const char *fmt
= "t,u";
3675 assert (! mips_opts
.mips16
);
3679 if (high_expr
.X_op
== O_constant
)
3681 /* we can compute the instruction now without a relocation entry */
3682 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3684 *r
= BFD_RELOC_UNUSED
;
3688 assert (ep
->X_op
== O_symbol
);
3689 /* _gp_disp is a special case, used from s_cpload.
3690 __gnu_local_gp is used if mips_no_shared. */
3691 assert (mips_pic
== NO_PIC
3693 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3694 || (! mips_in_shared
3695 && strcmp (S_GET_NAME (ep
->X_add_symbol
),
3696 "__gnu_local_gp") == 0));
3697 *r
= BFD_RELOC_HI16_S
;
3700 mo
= hash_find (op_hash
, name
);
3701 assert (strcmp (name
, mo
->name
) == 0);
3702 assert (strcmp (fmt
, mo
->args
) == 0);
3703 create_insn (&insn
, mo
);
3705 insn
.insn_opcode
= insn
.insn_mo
->match
;
3706 INSERT_OPERAND (RT
, insn
, regnum
);
3707 if (*r
== BFD_RELOC_UNUSED
)
3709 insn
.insn_opcode
|= high_expr
.X_add_number
;
3710 append_insn (&insn
, NULL
, r
);
3713 append_insn (&insn
, &high_expr
, r
);
3716 /* Generate a sequence of instructions to do a load or store from a constant
3717 offset off of a base register (breg) into/from a target register (treg),
3718 using AT if necessary. */
3720 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3721 int treg
, int breg
, int dbl
)
3723 assert (ep
->X_op
== O_constant
);
3725 /* Sign-extending 32-bit constants makes their handling easier. */
3727 normalize_constant_expr (ep
);
3729 /* Right now, this routine can only handle signed 32-bit constants. */
3730 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3731 as_warn (_("operand overflow"));
3733 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3735 /* Signed 16-bit offset will fit in the op. Easy! */
3736 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3740 /* 32-bit offset, need multiple instructions and AT, like:
3741 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3742 addu $tempreg,$tempreg,$breg
3743 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3744 to handle the complete offset. */
3745 macro_build_lui (ep
, AT
);
3746 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3747 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3750 as_bad (_("Macro used $at after \".set noat\""));
3755 * Generates code to set the $at register to true (one)
3756 * if reg is less than the immediate expression.
3759 set_at (int reg
, int unsignedp
)
3761 if (imm_expr
.X_op
== O_constant
3762 && imm_expr
.X_add_number
>= -0x8000
3763 && imm_expr
.X_add_number
< 0x8000)
3764 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3765 AT
, reg
, BFD_RELOC_LO16
);
3768 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3769 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3773 /* Warn if an expression is not a constant. */
3776 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3778 if (ex
->X_op
== O_big
)
3779 as_bad (_("unsupported large constant"));
3780 else if (ex
->X_op
!= O_constant
)
3781 as_bad (_("Instruction %s requires absolute expression"),
3784 if (HAVE_32BIT_GPRS
)
3785 normalize_constant_expr (ex
);
3788 /* Count the leading zeroes by performing a binary chop. This is a
3789 bulky bit of source, but performance is a LOT better for the
3790 majority of values than a simple loop to count the bits:
3791 for (lcnt = 0; (lcnt < 32); lcnt++)
3792 if ((v) & (1 << (31 - lcnt)))
3794 However it is not code size friendly, and the gain will drop a bit
3795 on certain cached systems.
3797 #define COUNT_TOP_ZEROES(v) \
3798 (((v) & ~0xffff) == 0 \
3799 ? ((v) & ~0xff) == 0 \
3800 ? ((v) & ~0xf) == 0 \
3801 ? ((v) & ~0x3) == 0 \
3802 ? ((v) & ~0x1) == 0 \
3807 : ((v) & ~0x7) == 0 \
3810 : ((v) & ~0x3f) == 0 \
3811 ? ((v) & ~0x1f) == 0 \
3814 : ((v) & ~0x7f) == 0 \
3817 : ((v) & ~0xfff) == 0 \
3818 ? ((v) & ~0x3ff) == 0 \
3819 ? ((v) & ~0x1ff) == 0 \
3822 : ((v) & ~0x7ff) == 0 \
3825 : ((v) & ~0x3fff) == 0 \
3826 ? ((v) & ~0x1fff) == 0 \
3829 : ((v) & ~0x7fff) == 0 \
3832 : ((v) & ~0xffffff) == 0 \
3833 ? ((v) & ~0xfffff) == 0 \
3834 ? ((v) & ~0x3ffff) == 0 \
3835 ? ((v) & ~0x1ffff) == 0 \
3838 : ((v) & ~0x7ffff) == 0 \
3841 : ((v) & ~0x3fffff) == 0 \
3842 ? ((v) & ~0x1fffff) == 0 \
3845 : ((v) & ~0x7fffff) == 0 \
3848 : ((v) & ~0xfffffff) == 0 \
3849 ? ((v) & ~0x3ffffff) == 0 \
3850 ? ((v) & ~0x1ffffff) == 0 \
3853 : ((v) & ~0x7ffffff) == 0 \
3856 : ((v) & ~0x3fffffff) == 0 \
3857 ? ((v) & ~0x1fffffff) == 0 \
3860 : ((v) & ~0x7fffffff) == 0 \
3865 * This routine generates the least number of instructions necessary to load
3866 * an absolute expression value into a register.
3869 load_register (int reg
, expressionS
*ep
, int dbl
)
3872 expressionS hi32
, lo32
;
3874 if (ep
->X_op
!= O_big
)
3876 assert (ep
->X_op
== O_constant
);
3878 /* Sign-extending 32-bit constants makes their handling easier. */
3880 normalize_constant_expr (ep
);
3882 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3884 /* We can handle 16 bit signed values with an addiu to
3885 $zero. No need to ever use daddiu here, since $zero and
3886 the result are always correct in 32 bit mode. */
3887 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3890 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3892 /* We can handle 16 bit unsigned values with an ori to
3894 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3897 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3899 /* 32 bit values require an lui. */
3900 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3901 if ((ep
->X_add_number
& 0xffff) != 0)
3902 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3907 /* The value is larger than 32 bits. */
3909 if (!dbl
|| HAVE_32BIT_GPRS
)
3913 sprintf_vma (value
, ep
->X_add_number
);
3914 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
3915 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3919 if (ep
->X_op
!= O_big
)
3922 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3923 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3924 hi32
.X_add_number
&= 0xffffffff;
3926 lo32
.X_add_number
&= 0xffffffff;
3930 assert (ep
->X_add_number
> 2);
3931 if (ep
->X_add_number
== 3)
3932 generic_bignum
[3] = 0;
3933 else if (ep
->X_add_number
> 4)
3934 as_bad (_("Number larger than 64 bits"));
3935 lo32
.X_op
= O_constant
;
3936 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3937 hi32
.X_op
= O_constant
;
3938 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3941 if (hi32
.X_add_number
== 0)
3946 unsigned long hi
, lo
;
3948 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3950 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3952 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3955 if (lo32
.X_add_number
& 0x80000000)
3957 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3958 if (lo32
.X_add_number
& 0xffff)
3959 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3964 /* Check for 16bit shifted constant. We know that hi32 is
3965 non-zero, so start the mask on the first bit of the hi32
3970 unsigned long himask
, lomask
;
3974 himask
= 0xffff >> (32 - shift
);
3975 lomask
= (0xffff << shift
) & 0xffffffff;
3979 himask
= 0xffff << (shift
- 32);
3982 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3983 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3987 tmp
.X_op
= O_constant
;
3989 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3990 | (lo32
.X_add_number
>> shift
));
3992 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3993 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3994 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3995 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4000 while (shift
<= (64 - 16));
4002 /* Find the bit number of the lowest one bit, and store the
4003 shifted value in hi/lo. */
4004 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
4005 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
4009 while ((lo
& 1) == 0)
4014 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
4020 while ((hi
& 1) == 0)
4029 /* Optimize if the shifted value is a (power of 2) - 1. */
4030 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
4031 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
4033 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
4038 /* This instruction will set the register to be all
4040 tmp
.X_op
= O_constant
;
4041 tmp
.X_add_number
= (offsetT
) -1;
4042 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
4046 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
4047 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
4049 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
4050 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
4055 /* Sign extend hi32 before calling load_register, because we can
4056 generally get better code when we load a sign extended value. */
4057 if ((hi32
.X_add_number
& 0x80000000) != 0)
4058 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
4059 load_register (reg
, &hi32
, 0);
4062 if ((lo32
.X_add_number
& 0xffff0000) == 0)
4066 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
4074 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
4076 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
4077 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
4083 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
4087 mid16
.X_add_number
>>= 16;
4088 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4089 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4092 if ((lo32
.X_add_number
& 0xffff) != 0)
4093 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
4097 load_delay_nop (void)
4099 if (!gpr_interlocks
)
4100 macro_build (NULL
, "nop", "");
4103 /* Load an address into a register. */
4106 load_address (int reg
, expressionS
*ep
, int *used_at
)
4108 if (ep
->X_op
!= O_constant
4109 && ep
->X_op
!= O_symbol
)
4111 as_bad (_("expression too complex"));
4112 ep
->X_op
= O_constant
;
4115 if (ep
->X_op
== O_constant
)
4117 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
4121 if (mips_pic
== NO_PIC
)
4123 /* If this is a reference to a GP relative symbol, we want
4124 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4126 lui $reg,<sym> (BFD_RELOC_HI16_S)
4127 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4128 If we have an addend, we always use the latter form.
4130 With 64bit address space and a usable $at we want
4131 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4132 lui $at,<sym> (BFD_RELOC_HI16_S)
4133 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4134 daddiu $at,<sym> (BFD_RELOC_LO16)
4138 If $at is already in use, we use a path which is suboptimal
4139 on superscalar processors.
4140 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4141 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
4143 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
4145 daddiu $reg,<sym> (BFD_RELOC_LO16)
4147 For GP relative symbols in 64bit address space we can use
4148 the same sequence as in 32bit address space. */
4149 if (HAVE_64BIT_SYMBOLS
)
4151 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4152 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4154 relax_start (ep
->X_add_symbol
);
4155 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4156 mips_gp_register
, BFD_RELOC_GPREL16
);
4160 if (*used_at
== 0 && !mips_opts
.noat
)
4162 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4163 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
4164 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4165 BFD_RELOC_MIPS_HIGHER
);
4166 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
4167 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
4168 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
4173 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
4174 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
4175 BFD_RELOC_MIPS_HIGHER
);
4176 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4177 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
4178 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
4179 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
4182 if (mips_relax
.sequence
)
4187 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
4188 && !nopic_need_relax (ep
->X_add_symbol
, 1))
4190 relax_start (ep
->X_add_symbol
);
4191 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
4192 mips_gp_register
, BFD_RELOC_GPREL16
);
4195 macro_build_lui (ep
, reg
);
4196 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4197 reg
, reg
, BFD_RELOC_LO16
);
4198 if (mips_relax
.sequence
)
4202 else if (!mips_big_got
)
4206 /* If this is a reference to an external symbol, we want
4207 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4209 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4211 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4212 If there is a constant, it must be added in after.
4214 If we have NewABI, we want
4215 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
4216 unless we're referencing a global symbol with a non-zero
4217 offset, in which case cst must be added separately. */
4220 if (ep
->X_add_number
)
4222 ex
.X_add_number
= ep
->X_add_number
;
4223 ep
->X_add_number
= 0;
4224 relax_start (ep
->X_add_symbol
);
4225 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4226 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4227 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4228 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4229 ex
.X_op
= O_constant
;
4230 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4231 reg
, reg
, BFD_RELOC_LO16
);
4232 ep
->X_add_number
= ex
.X_add_number
;
4235 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4236 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
4237 if (mips_relax
.sequence
)
4242 ex
.X_add_number
= ep
->X_add_number
;
4243 ep
->X_add_number
= 0;
4244 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4245 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4247 relax_start (ep
->X_add_symbol
);
4249 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4253 if (ex
.X_add_number
!= 0)
4255 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4256 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4257 ex
.X_op
= O_constant
;
4258 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
4259 reg
, reg
, BFD_RELOC_LO16
);
4263 else if (mips_big_got
)
4267 /* This is the large GOT case. If this is a reference to an
4268 external symbol, we want
4269 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4271 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
4273 Otherwise, for a reference to a local symbol in old ABI, we want
4274 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4276 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
4277 If there is a constant, it must be added in after.
4279 In the NewABI, for local symbols, with or without offsets, we want:
4280 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
4281 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
4285 ex
.X_add_number
= ep
->X_add_number
;
4286 ep
->X_add_number
= 0;
4287 relax_start (ep
->X_add_symbol
);
4288 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4289 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4290 reg
, reg
, mips_gp_register
);
4291 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4292 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4293 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4294 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4295 else if (ex
.X_add_number
)
4297 ex
.X_op
= O_constant
;
4298 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4302 ep
->X_add_number
= ex
.X_add_number
;
4304 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4305 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4306 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4307 BFD_RELOC_MIPS_GOT_OFST
);
4312 ex
.X_add_number
= ep
->X_add_number
;
4313 ep
->X_add_number
= 0;
4314 relax_start (ep
->X_add_symbol
);
4315 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4316 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4317 reg
, reg
, mips_gp_register
);
4318 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4319 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4321 if (reg_needs_delay (mips_gp_register
))
4323 /* We need a nop before loading from $gp. This special
4324 check is required because the lui which starts the main
4325 instruction stream does not refer to $gp, and so will not
4326 insert the nop which may be required. */
4327 macro_build (NULL
, "nop", "");
4329 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4330 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4332 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4336 if (ex
.X_add_number
!= 0)
4338 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4339 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4340 ex
.X_op
= O_constant
;
4341 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4349 if (mips_opts
.noat
&& *used_at
== 1)
4350 as_bad (_("Macro used $at after \".set noat\""));
4353 /* Move the contents of register SOURCE into register DEST. */
4356 move_register (int dest
, int source
)
4358 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4362 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4363 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4364 The two alternatives are:
4366 Global symbol Local sybmol
4367 ------------- ------------
4368 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4370 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4372 load_got_offset emits the first instruction and add_got_offset
4373 emits the second for a 16-bit offset or add_got_offset_hilo emits
4374 a sequence to add a 32-bit offset using a scratch register. */
4377 load_got_offset (int dest
, expressionS
*local
)
4382 global
.X_add_number
= 0;
4384 relax_start (local
->X_add_symbol
);
4385 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4386 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4388 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4389 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4394 add_got_offset (int dest
, expressionS
*local
)
4398 global
.X_op
= O_constant
;
4399 global
.X_op_symbol
= NULL
;
4400 global
.X_add_symbol
= NULL
;
4401 global
.X_add_number
= local
->X_add_number
;
4403 relax_start (local
->X_add_symbol
);
4404 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4405 dest
, dest
, BFD_RELOC_LO16
);
4407 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4412 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4415 int hold_mips_optimize
;
4417 global
.X_op
= O_constant
;
4418 global
.X_op_symbol
= NULL
;
4419 global
.X_add_symbol
= NULL
;
4420 global
.X_add_number
= local
->X_add_number
;
4422 relax_start (local
->X_add_symbol
);
4423 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4425 /* Set mips_optimize around the lui instruction to avoid
4426 inserting an unnecessary nop after the lw. */
4427 hold_mips_optimize
= mips_optimize
;
4429 macro_build_lui (&global
, tmp
);
4430 mips_optimize
= hold_mips_optimize
;
4431 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4434 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4439 * This routine implements the seemingly endless macro or synthesized
4440 * instructions and addressing modes in the mips assembly language. Many
4441 * of these macros are simple and are similar to each other. These could
4442 * probably be handled by some kind of table or grammar approach instead of
4443 * this verbose method. Others are not simple macros but are more like
4444 * optimizing code generation.
4445 * One interesting optimization is when several store macros appear
4446 * consecutively that would load AT with the upper half of the same address.
4447 * The ensuing load upper instructions are ommited. This implies some kind
4448 * of global optimization. We currently only optimize within a single macro.
4449 * For many of the load and store macros if the address is specified as a
4450 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4451 * first load register 'at' with zero and use it as the base register. The
4452 * mips assembler simply uses register $zero. Just one tiny optimization
4456 macro (struct mips_cl_insn
*ip
)
4458 register int treg
, sreg
, dreg
, breg
;
4474 bfd_reloc_code_real_type r
;
4475 int hold_mips_optimize
;
4477 assert (! mips_opts
.mips16
);
4479 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4480 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4481 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4482 mask
= ip
->insn_mo
->mask
;
4484 expr1
.X_op
= O_constant
;
4485 expr1
.X_op_symbol
= NULL
;
4486 expr1
.X_add_symbol
= NULL
;
4487 expr1
.X_add_number
= 1;
4501 expr1
.X_add_number
= 8;
4502 macro_build (&expr1
, "bgez", "s,p", sreg
);
4504 macro_build (NULL
, "nop", "", 0);
4506 move_register (dreg
, sreg
);
4507 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4530 if (imm_expr
.X_op
== O_constant
4531 && imm_expr
.X_add_number
>= -0x8000
4532 && imm_expr
.X_add_number
< 0x8000)
4534 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4538 load_register (AT
, &imm_expr
, dbl
);
4539 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4558 if (imm_expr
.X_op
== O_constant
4559 && imm_expr
.X_add_number
>= 0
4560 && imm_expr
.X_add_number
< 0x10000)
4562 if (mask
!= M_NOR_I
)
4563 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4566 macro_build (&imm_expr
, "ori", "t,r,i",
4567 treg
, sreg
, BFD_RELOC_LO16
);
4568 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4574 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4575 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4592 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4594 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4598 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4599 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4607 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4612 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4616 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4617 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4623 /* check for > max integer */
4624 maxnum
= 0x7fffffff;
4625 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4632 if (imm_expr
.X_op
== O_constant
4633 && imm_expr
.X_add_number
>= maxnum
4634 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4637 /* result is always false */
4639 macro_build (NULL
, "nop", "", 0);
4641 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4644 if (imm_expr
.X_op
!= O_constant
)
4645 as_bad (_("Unsupported large constant"));
4646 ++imm_expr
.X_add_number
;
4650 if (mask
== M_BGEL_I
)
4652 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4654 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4657 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4659 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4662 maxnum
= 0x7fffffff;
4663 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4670 maxnum
= - maxnum
- 1;
4671 if (imm_expr
.X_op
== O_constant
4672 && imm_expr
.X_add_number
<= maxnum
4673 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4676 /* result is always true */
4677 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4678 macro_build (&offset_expr
, "b", "p");
4683 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4693 macro_build (&offset_expr
, likely
? "beql" : "beq",
4698 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4699 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4707 && imm_expr
.X_op
== O_constant
4708 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4710 if (imm_expr
.X_op
!= O_constant
)
4711 as_bad (_("Unsupported large constant"));
4712 ++imm_expr
.X_add_number
;
4716 if (mask
== M_BGEUL_I
)
4718 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4720 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4722 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4728 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4736 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4741 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4745 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4746 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4754 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4761 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4762 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4770 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4775 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4779 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4780 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4786 maxnum
= 0x7fffffff;
4787 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4794 if (imm_expr
.X_op
== O_constant
4795 && imm_expr
.X_add_number
>= maxnum
4796 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4798 if (imm_expr
.X_op
!= O_constant
)
4799 as_bad (_("Unsupported large constant"));
4800 ++imm_expr
.X_add_number
;
4804 if (mask
== M_BLTL_I
)
4806 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4808 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4811 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4813 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4818 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4826 macro_build (&offset_expr
, likely
? "beql" : "beq",
4833 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4834 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4842 && imm_expr
.X_op
== O_constant
4843 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4845 if (imm_expr
.X_op
!= O_constant
)
4846 as_bad (_("Unsupported large constant"));
4847 ++imm_expr
.X_add_number
;
4851 if (mask
== M_BLTUL_I
)
4853 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4855 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4857 macro_build (&offset_expr
, likely
? "beql" : "beq",
4863 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4871 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4876 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4880 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4881 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4891 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4896 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4897 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4905 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4907 as_bad (_("Unsupported large constant"));
4912 pos
= (unsigned long) imm_expr
.X_add_number
;
4913 size
= (unsigned long) imm2_expr
.X_add_number
;
4918 as_bad (_("Improper position (%lu)"), pos
);
4921 if (size
== 0 || size
> 64
4922 || (pos
+ size
- 1) > 63)
4924 as_bad (_("Improper extract size (%lu, position %lu)"),
4929 if (size
<= 32 && pos
< 32)
4934 else if (size
<= 32)
4944 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4953 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4955 as_bad (_("Unsupported large constant"));
4960 pos
= (unsigned long) imm_expr
.X_add_number
;
4961 size
= (unsigned long) imm2_expr
.X_add_number
;
4966 as_bad (_("Improper position (%lu)"), pos
);
4969 if (size
== 0 || size
> 64
4970 || (pos
+ size
- 1) > 63)
4972 as_bad (_("Improper insert size (%lu, position %lu)"),
4977 if (pos
< 32 && (pos
+ size
- 1) < 32)
4992 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
5009 as_warn (_("Divide by zero."));
5011 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5013 macro_build (NULL
, "break", "c", 7);
5020 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5021 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5025 expr1
.X_add_number
= 8;
5026 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5027 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
5028 macro_build (NULL
, "break", "c", 7);
5030 expr1
.X_add_number
= -1;
5032 load_register (AT
, &expr1
, dbl
);
5033 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
5034 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
5037 expr1
.X_add_number
= 1;
5038 load_register (AT
, &expr1
, dbl
);
5039 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
5043 expr1
.X_add_number
= 0x80000000;
5044 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
5048 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
5049 /* We want to close the noreorder block as soon as possible, so
5050 that later insns are available for delay slot filling. */
5055 expr1
.X_add_number
= 8;
5056 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
5057 macro_build (NULL
, "nop", "", 0);
5059 /* We want to close the noreorder block as soon as possible, so
5060 that later insns are available for delay slot filling. */
5063 macro_build (NULL
, "break", "c", 6);
5065 macro_build (NULL
, s
, "d", dreg
);
5104 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
5106 as_warn (_("Divide by zero."));
5108 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
5110 macro_build (NULL
, "break", "c", 7);
5113 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
5115 if (strcmp (s2
, "mflo") == 0)
5116 move_register (dreg
, sreg
);
5118 move_register (dreg
, 0);
5121 if (imm_expr
.X_op
== O_constant
5122 && imm_expr
.X_add_number
== -1
5123 && s
[strlen (s
) - 1] != 'u')
5125 if (strcmp (s2
, "mflo") == 0)
5127 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
5130 move_register (dreg
, 0);
5135 load_register (AT
, &imm_expr
, dbl
);
5136 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
5137 macro_build (NULL
, s2
, "d", dreg
);
5159 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
5160 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5161 /* We want to close the noreorder block as soon as possible, so
5162 that later insns are available for delay slot filling. */
5167 expr1
.X_add_number
= 8;
5168 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
5169 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
5171 /* We want to close the noreorder block as soon as possible, so
5172 that later insns are available for delay slot filling. */
5174 macro_build (NULL
, "break", "c", 7);
5176 macro_build (NULL
, s2
, "d", dreg
);
5188 /* Load the address of a symbol into a register. If breg is not
5189 zero, we then add a base register to it. */
5191 if (dbl
&& HAVE_32BIT_GPRS
)
5192 as_warn (_("dla used to load 32-bit register"));
5194 if (! dbl
&& HAVE_64BIT_OBJECTS
)
5195 as_warn (_("la used to load 64-bit address"));
5197 if (offset_expr
.X_op
== O_constant
5198 && offset_expr
.X_add_number
>= -0x8000
5199 && offset_expr
.X_add_number
< 0x8000)
5201 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
,
5202 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
5206 if (!mips_opts
.noat
&& (treg
== breg
))
5216 if (offset_expr
.X_op
!= O_symbol
5217 && offset_expr
.X_op
!= O_constant
)
5219 as_bad (_("expression too complex"));
5220 offset_expr
.X_op
= O_constant
;
5223 if (offset_expr
.X_op
== O_constant
)
5224 load_register (tempreg
, &offset_expr
, HAVE_64BIT_ADDRESSES
);
5225 else if (mips_pic
== NO_PIC
)
5227 /* If this is a reference to a GP relative symbol, we want
5228 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5230 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5231 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5232 If we have a constant, we need two instructions anyhow,
5233 so we may as well always use the latter form.
5235 With 64bit address space and a usable $at we want
5236 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5237 lui $at,<sym> (BFD_RELOC_HI16_S)
5238 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5239 daddiu $at,<sym> (BFD_RELOC_LO16)
5241 daddu $tempreg,$tempreg,$at
5243 If $at is already in use, we use a path which is suboptimal
5244 on superscalar processors.
5245 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5246 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5248 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5250 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
5252 For GP relative symbols in 64bit address space we can use
5253 the same sequence as in 32bit address space. */
5254 if (HAVE_64BIT_SYMBOLS
)
5256 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5257 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5259 relax_start (offset_expr
.X_add_symbol
);
5260 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5261 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5265 if (used_at
== 0 && !mips_opts
.noat
)
5267 macro_build (&offset_expr
, "lui", "t,u",
5268 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5269 macro_build (&offset_expr
, "lui", "t,u",
5270 AT
, BFD_RELOC_HI16_S
);
5271 macro_build (&offset_expr
, "daddiu", "t,r,j",
5272 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5273 macro_build (&offset_expr
, "daddiu", "t,r,j",
5274 AT
, AT
, BFD_RELOC_LO16
);
5275 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5276 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5281 macro_build (&offset_expr
, "lui", "t,u",
5282 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
5283 macro_build (&offset_expr
, "daddiu", "t,r,j",
5284 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
5285 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5286 macro_build (&offset_expr
, "daddiu", "t,r,j",
5287 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
5288 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5289 macro_build (&offset_expr
, "daddiu", "t,r,j",
5290 tempreg
, tempreg
, BFD_RELOC_LO16
);
5293 if (mips_relax
.sequence
)
5298 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5299 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5301 relax_start (offset_expr
.X_add_symbol
);
5302 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5303 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5306 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5307 as_bad (_("offset too large"));
5308 macro_build_lui (&offset_expr
, tempreg
);
5309 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5310 tempreg
, tempreg
, BFD_RELOC_LO16
);
5311 if (mips_relax
.sequence
)
5315 else if (!mips_big_got
&& !HAVE_NEWABI
)
5317 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5319 /* If this is a reference to an external symbol, and there
5320 is no constant, we want
5321 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5322 or for lca or if tempreg is PIC_CALL_REG
5323 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5324 For a local symbol, we want
5325 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5327 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5329 If we have a small constant, and this is a reference to
5330 an external symbol, we want
5331 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5333 addiu $tempreg,$tempreg,<constant>
5334 For a local symbol, we want the same instruction
5335 sequence, but we output a BFD_RELOC_LO16 reloc on the
5338 If we have a large constant, and this is a reference to
5339 an external symbol, we want
5340 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5341 lui $at,<hiconstant>
5342 addiu $at,$at,<loconstant>
5343 addu $tempreg,$tempreg,$at
5344 For a local symbol, we want the same instruction
5345 sequence, but we output a BFD_RELOC_LO16 reloc on the
5349 if (offset_expr
.X_add_number
== 0)
5351 if (mips_pic
== SVR4_PIC
5353 && (call
|| tempreg
== PIC_CALL_REG
))
5354 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5356 relax_start (offset_expr
.X_add_symbol
);
5357 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5358 lw_reloc_type
, mips_gp_register
);
5361 /* We're going to put in an addu instruction using
5362 tempreg, so we may as well insert the nop right
5367 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5368 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5370 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5371 tempreg
, tempreg
, BFD_RELOC_LO16
);
5373 /* FIXME: If breg == 0, and the next instruction uses
5374 $tempreg, then if this variant case is used an extra
5375 nop will be generated. */
5377 else if (offset_expr
.X_add_number
>= -0x8000
5378 && offset_expr
.X_add_number
< 0x8000)
5380 load_got_offset (tempreg
, &offset_expr
);
5382 add_got_offset (tempreg
, &offset_expr
);
5386 expr1
.X_add_number
= offset_expr
.X_add_number
;
5387 offset_expr
.X_add_number
=
5388 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5389 load_got_offset (tempreg
, &offset_expr
);
5390 offset_expr
.X_add_number
= expr1
.X_add_number
;
5391 /* If we are going to add in a base register, and the
5392 target register and the base register are the same,
5393 then we are using AT as a temporary register. Since
5394 we want to load the constant into AT, we add our
5395 current AT (from the global offset table) and the
5396 register into the register now, and pretend we were
5397 not using a base register. */
5401 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5406 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5410 else if (!mips_big_got
&& HAVE_NEWABI
)
5412 int add_breg_early
= 0;
5414 /* If this is a reference to an external, and there is no
5415 constant, or local symbol (*), with or without a
5417 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5418 or for lca or if tempreg is PIC_CALL_REG
5419 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5421 If we have a small constant, and this is a reference to
5422 an external symbol, we want
5423 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5424 addiu $tempreg,$tempreg,<constant>
5426 If we have a large constant, and this is a reference to
5427 an external symbol, we want
5428 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5429 lui $at,<hiconstant>
5430 addiu $at,$at,<loconstant>
5431 addu $tempreg,$tempreg,$at
5433 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5434 local symbols, even though it introduces an additional
5437 if (offset_expr
.X_add_number
)
5439 expr1
.X_add_number
= offset_expr
.X_add_number
;
5440 offset_expr
.X_add_number
= 0;
5442 relax_start (offset_expr
.X_add_symbol
);
5443 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5444 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5446 if (expr1
.X_add_number
>= -0x8000
5447 && expr1
.X_add_number
< 0x8000)
5449 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5450 tempreg
, tempreg
, BFD_RELOC_LO16
);
5452 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5456 /* If we are going to add in a base register, and the
5457 target register and the base register are the same,
5458 then we are using AT as a temporary register. Since
5459 we want to load the constant into AT, we add our
5460 current AT (from the global offset table) and the
5461 register into the register now, and pretend we were
5462 not using a base register. */
5467 assert (tempreg
== AT
);
5468 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5474 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5475 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5481 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5484 offset_expr
.X_add_number
= expr1
.X_add_number
;
5486 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5487 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5490 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5491 treg
, tempreg
, breg
);
5497 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5499 relax_start (offset_expr
.X_add_symbol
);
5500 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5501 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5503 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5504 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5509 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5510 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5513 else if (mips_big_got
&& !HAVE_NEWABI
)
5516 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5517 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5518 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5520 /* This is the large GOT case. If this is a reference to an
5521 external symbol, and there is no constant, we want
5522 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5523 addu $tempreg,$tempreg,$gp
5524 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5525 or for lca or if tempreg is PIC_CALL_REG
5526 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5527 addu $tempreg,$tempreg,$gp
5528 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5529 For a local symbol, we want
5530 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5532 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5534 If we have a small constant, and this is a reference to
5535 an external symbol, we want
5536 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5537 addu $tempreg,$tempreg,$gp
5538 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5540 addiu $tempreg,$tempreg,<constant>
5541 For a local symbol, we want
5542 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5544 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5546 If we have a large constant, and this is a reference to
5547 an external symbol, we want
5548 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5549 addu $tempreg,$tempreg,$gp
5550 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5551 lui $at,<hiconstant>
5552 addiu $at,$at,<loconstant>
5553 addu $tempreg,$tempreg,$at
5554 For a local symbol, we want
5555 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5556 lui $at,<hiconstant>
5557 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5558 addu $tempreg,$tempreg,$at
5561 expr1
.X_add_number
= offset_expr
.X_add_number
;
5562 offset_expr
.X_add_number
= 0;
5563 relax_start (offset_expr
.X_add_symbol
);
5564 gpdelay
= reg_needs_delay (mips_gp_register
);
5565 if (expr1
.X_add_number
== 0 && breg
== 0
5566 && (call
|| tempreg
== PIC_CALL_REG
))
5568 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5569 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5571 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5572 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5573 tempreg
, tempreg
, mips_gp_register
);
5574 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5575 tempreg
, lw_reloc_type
, tempreg
);
5576 if (expr1
.X_add_number
== 0)
5580 /* We're going to put in an addu instruction using
5581 tempreg, so we may as well insert the nop right
5586 else if (expr1
.X_add_number
>= -0x8000
5587 && expr1
.X_add_number
< 0x8000)
5590 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5591 tempreg
, tempreg
, BFD_RELOC_LO16
);
5597 /* If we are going to add in a base register, and the
5598 target register and the base register are the same,
5599 then we are using AT as a temporary register. Since
5600 we want to load the constant into AT, we add our
5601 current AT (from the global offset table) and the
5602 register into the register now, and pretend we were
5603 not using a base register. */
5608 assert (tempreg
== AT
);
5610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5615 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5616 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5620 offset_expr
.X_add_number
=
5621 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5626 /* This is needed because this instruction uses $gp, but
5627 the first instruction on the main stream does not. */
5628 macro_build (NULL
, "nop", "");
5631 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5632 local_reloc_type
, mips_gp_register
);
5633 if (expr1
.X_add_number
>= -0x8000
5634 && expr1
.X_add_number
< 0x8000)
5637 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5638 tempreg
, tempreg
, BFD_RELOC_LO16
);
5639 /* FIXME: If add_number is 0, and there was no base
5640 register, the external symbol case ended with a load,
5641 so if the symbol turns out to not be external, and
5642 the next instruction uses tempreg, an unnecessary nop
5643 will be inserted. */
5649 /* We must add in the base register now, as in the
5650 external symbol case. */
5651 assert (tempreg
== AT
);
5653 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5656 /* We set breg to 0 because we have arranged to add
5657 it in in both cases. */
5661 macro_build_lui (&expr1
, AT
);
5662 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5663 AT
, AT
, BFD_RELOC_LO16
);
5664 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5665 tempreg
, tempreg
, AT
);
5670 else if (mips_big_got
&& HAVE_NEWABI
)
5672 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5673 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5674 int add_breg_early
= 0;
5676 /* This is the large GOT case. If this is a reference to an
5677 external symbol, and there is no constant, we want
5678 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5679 add $tempreg,$tempreg,$gp
5680 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5681 or for lca or if tempreg is PIC_CALL_REG
5682 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5683 add $tempreg,$tempreg,$gp
5684 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5686 If we have a small constant, and this is a reference to
5687 an external symbol, we want
5688 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5689 add $tempreg,$tempreg,$gp
5690 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5691 addi $tempreg,$tempreg,<constant>
5693 If we have a large constant, and this is a reference to
5694 an external symbol, we want
5695 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5696 addu $tempreg,$tempreg,$gp
5697 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5698 lui $at,<hiconstant>
5699 addi $at,$at,<loconstant>
5700 add $tempreg,$tempreg,$at
5702 If we have NewABI, and we know it's a local symbol, we want
5703 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5704 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5705 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5707 relax_start (offset_expr
.X_add_symbol
);
5709 expr1
.X_add_number
= offset_expr
.X_add_number
;
5710 offset_expr
.X_add_number
= 0;
5712 if (expr1
.X_add_number
== 0 && breg
== 0
5713 && (call
|| tempreg
== PIC_CALL_REG
))
5715 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5716 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5718 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5719 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5720 tempreg
, tempreg
, mips_gp_register
);
5721 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5722 tempreg
, lw_reloc_type
, tempreg
);
5724 if (expr1
.X_add_number
== 0)
5726 else if (expr1
.X_add_number
>= -0x8000
5727 && expr1
.X_add_number
< 0x8000)
5729 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5730 tempreg
, tempreg
, BFD_RELOC_LO16
);
5732 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5736 /* If we are going to add in a base register, and the
5737 target register and the base register are the same,
5738 then we are using AT as a temporary register. Since
5739 we want to load the constant into AT, we add our
5740 current AT (from the global offset table) and the
5741 register into the register now, and pretend we were
5742 not using a base register. */
5747 assert (tempreg
== AT
);
5748 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5754 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5755 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5760 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5763 offset_expr
.X_add_number
= expr1
.X_add_number
;
5764 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5765 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5766 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5767 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5770 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5771 treg
, tempreg
, breg
);
5781 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", treg
, tempreg
, breg
);
5785 /* The j instruction may not be used in PIC code, since it
5786 requires an absolute address. We convert it to a b
5788 if (mips_pic
== NO_PIC
)
5789 macro_build (&offset_expr
, "j", "a");
5791 macro_build (&offset_expr
, "b", "p");
5794 /* The jal instructions must be handled as macros because when
5795 generating PIC code they expand to multi-instruction
5796 sequences. Normally they are simple instructions. */
5801 if (mips_pic
== NO_PIC
)
5802 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5805 if (sreg
!= PIC_CALL_REG
)
5806 as_warn (_("MIPS PIC call to register other than $25"));
5808 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5809 if (mips_pic
== SVR4_PIC
&& !HAVE_NEWABI
)
5811 if (mips_cprestore_offset
< 0)
5812 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5815 if (! mips_frame_reg_valid
)
5817 as_warn (_("No .frame pseudo-op used in PIC code"));
5818 /* Quiet this warning. */
5819 mips_frame_reg_valid
= 1;
5821 if (! mips_cprestore_valid
)
5823 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5824 /* Quiet this warning. */
5825 mips_cprestore_valid
= 1;
5827 expr1
.X_add_number
= mips_cprestore_offset
;
5828 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5831 HAVE_64BIT_ADDRESSES
);
5839 if (mips_pic
== NO_PIC
)
5840 macro_build (&offset_expr
, "jal", "a");
5841 else if (mips_pic
== SVR4_PIC
)
5843 /* If this is a reference to an external symbol, and we are
5844 using a small GOT, we want
5845 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5849 lw $gp,cprestore($sp)
5850 The cprestore value is set using the .cprestore
5851 pseudo-op. If we are using a big GOT, we want
5852 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5854 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5858 lw $gp,cprestore($sp)
5859 If the symbol is not external, we want
5860 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5862 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5865 lw $gp,cprestore($sp)
5867 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5868 sequences above, minus nops, unless the symbol is local,
5869 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5875 relax_start (offset_expr
.X_add_symbol
);
5876 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5877 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5880 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5881 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5887 relax_start (offset_expr
.X_add_symbol
);
5888 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5889 BFD_RELOC_MIPS_CALL_HI16
);
5890 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5891 PIC_CALL_REG
, mips_gp_register
);
5892 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5893 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5896 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5897 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5899 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5900 PIC_CALL_REG
, PIC_CALL_REG
,
5901 BFD_RELOC_MIPS_GOT_OFST
);
5905 macro_build_jalr (&offset_expr
);
5909 relax_start (offset_expr
.X_add_symbol
);
5912 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5913 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5922 gpdelay
= reg_needs_delay (mips_gp_register
);
5923 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5924 BFD_RELOC_MIPS_CALL_HI16
);
5925 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5926 PIC_CALL_REG
, mips_gp_register
);
5927 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5928 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5933 macro_build (NULL
, "nop", "");
5935 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5936 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5939 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5940 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5942 macro_build_jalr (&offset_expr
);
5944 if (mips_cprestore_offset
< 0)
5945 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5948 if (! mips_frame_reg_valid
)
5950 as_warn (_("No .frame pseudo-op used in PIC code"));
5951 /* Quiet this warning. */
5952 mips_frame_reg_valid
= 1;
5954 if (! mips_cprestore_valid
)
5956 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5957 /* Quiet this warning. */
5958 mips_cprestore_valid
= 1;
5960 if (mips_opts
.noreorder
)
5961 macro_build (NULL
, "nop", "");
5962 expr1
.X_add_number
= mips_cprestore_offset
;
5963 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5966 HAVE_64BIT_ADDRESSES
);
5970 else if (mips_pic
== VXWORKS_PIC
)
5971 as_bad (_("Non-PIC jump used in PIC library"));
5994 /* Itbl support may require additional care here. */
5999 /* Itbl support may require additional care here. */
6004 /* Itbl support may require additional care here. */
6009 /* Itbl support may require additional care here. */
6021 if (mips_opts
.arch
== CPU_R4650
)
6023 as_bad (_("opcode not supported on this processor"));
6027 /* Itbl support may require additional care here. */
6032 /* Itbl support may require additional care here. */
6037 /* Itbl support may require additional care here. */
6057 if (breg
== treg
|| coproc
|| lr
)
6078 /* Itbl support may require additional care here. */
6083 /* Itbl support may require additional care here. */
6088 /* Itbl support may require additional care here. */
6093 /* Itbl support may require additional care here. */
6112 if (mips_opts
.arch
== CPU_R4650
)
6114 as_bad (_("opcode not supported on this processor"));
6119 /* Itbl support may require additional care here. */
6123 /* Itbl support may require additional care here. */
6128 /* Itbl support may require additional care here. */
6140 /* Itbl support may require additional care here. */
6141 if (mask
== M_LWC1_AB
6142 || mask
== M_SWC1_AB
6143 || mask
== M_LDC1_AB
6144 || mask
== M_SDC1_AB
6148 else if (mask
== M_CACHE_AB
)
6155 if (offset_expr
.X_op
!= O_constant
6156 && offset_expr
.X_op
!= O_symbol
)
6158 as_bad (_("expression too complex"));
6159 offset_expr
.X_op
= O_constant
;
6162 if (HAVE_32BIT_ADDRESSES
6163 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6167 sprintf_vma (value
, offset_expr
.X_add_number
);
6168 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6171 /* A constant expression in PIC code can be handled just as it
6172 is in non PIC code. */
6173 if (offset_expr
.X_op
== O_constant
)
6175 expr1
.X_add_number
= ((offset_expr
.X_add_number
+ 0x8000)
6176 & ~(bfd_vma
) 0xffff);
6177 normalize_address_expr (&expr1
);
6178 load_register (tempreg
, &expr1
, HAVE_64BIT_ADDRESSES
);
6180 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6181 tempreg
, tempreg
, breg
);
6182 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6184 else if (mips_pic
== NO_PIC
)
6186 /* If this is a reference to a GP relative symbol, and there
6187 is no base register, we want
6188 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6189 Otherwise, if there is no base register, we want
6190 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6191 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6192 If we have a constant, we need two instructions anyhow,
6193 so we always use the latter form.
6195 If we have a base register, and this is a reference to a
6196 GP relative symbol, we want
6197 addu $tempreg,$breg,$gp
6198 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6200 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
6201 addu $tempreg,$tempreg,$breg
6202 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6203 With a constant we always use the latter case.
6205 With 64bit address space and no base register and $at usable,
6207 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6208 lui $at,<sym> (BFD_RELOC_HI16_S)
6209 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6212 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6213 If we have a base register, we want
6214 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6215 lui $at,<sym> (BFD_RELOC_HI16_S)
6216 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6220 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6222 Without $at we can't generate the optimal path for superscalar
6223 processors here since this would require two temporary registers.
6224 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6225 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6227 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6229 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6230 If we have a base register, we want
6231 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6232 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6234 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6236 daddu $tempreg,$tempreg,$breg
6237 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6239 For GP relative symbols in 64bit address space we can use
6240 the same sequence as in 32bit address space. */
6241 if (HAVE_64BIT_SYMBOLS
)
6243 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6244 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6246 relax_start (offset_expr
.X_add_symbol
);
6249 macro_build (&offset_expr
, s
, fmt
, treg
,
6250 BFD_RELOC_GPREL16
, mips_gp_register
);
6254 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6255 tempreg
, breg
, mips_gp_register
);
6256 macro_build (&offset_expr
, s
, fmt
, treg
,
6257 BFD_RELOC_GPREL16
, tempreg
);
6262 if (used_at
== 0 && !mips_opts
.noat
)
6264 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6265 BFD_RELOC_MIPS_HIGHEST
);
6266 macro_build (&offset_expr
, "lui", "t,u", AT
,
6268 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6269 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6271 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6272 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6273 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6274 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6280 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6281 BFD_RELOC_MIPS_HIGHEST
);
6282 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6283 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6284 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6285 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6286 tempreg
, BFD_RELOC_HI16_S
);
6287 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6289 macro_build (NULL
, "daddu", "d,v,t",
6290 tempreg
, tempreg
, breg
);
6291 macro_build (&offset_expr
, s
, fmt
, treg
,
6292 BFD_RELOC_LO16
, tempreg
);
6295 if (mips_relax
.sequence
)
6302 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6303 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6305 relax_start (offset_expr
.X_add_symbol
);
6306 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6310 macro_build_lui (&offset_expr
, tempreg
);
6311 macro_build (&offset_expr
, s
, fmt
, treg
,
6312 BFD_RELOC_LO16
, tempreg
);
6313 if (mips_relax
.sequence
)
6318 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6319 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6321 relax_start (offset_expr
.X_add_symbol
);
6322 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6323 tempreg
, breg
, mips_gp_register
);
6324 macro_build (&offset_expr
, s
, fmt
, treg
,
6325 BFD_RELOC_GPREL16
, tempreg
);
6328 macro_build_lui (&offset_expr
, tempreg
);
6329 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6330 tempreg
, tempreg
, breg
);
6331 macro_build (&offset_expr
, s
, fmt
, treg
,
6332 BFD_RELOC_LO16
, tempreg
);
6333 if (mips_relax
.sequence
)
6337 else if (!mips_big_got
)
6339 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6341 /* If this is a reference to an external symbol, we want
6342 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6344 <op> $treg,0($tempreg)
6346 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6348 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6349 <op> $treg,0($tempreg)
6352 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6353 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6355 If there is a base register, we add it to $tempreg before
6356 the <op>. If there is a constant, we stick it in the
6357 <op> instruction. We don't handle constants larger than
6358 16 bits, because we have no way to load the upper 16 bits
6359 (actually, we could handle them for the subset of cases
6360 in which we are not using $at). */
6361 assert (offset_expr
.X_op
== O_symbol
);
6364 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6365 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6367 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6368 tempreg
, tempreg
, breg
);
6369 macro_build (&offset_expr
, s
, fmt
, treg
,
6370 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6373 expr1
.X_add_number
= offset_expr
.X_add_number
;
6374 offset_expr
.X_add_number
= 0;
6375 if (expr1
.X_add_number
< -0x8000
6376 || expr1
.X_add_number
>= 0x8000)
6377 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6378 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6379 lw_reloc_type
, mips_gp_register
);
6381 relax_start (offset_expr
.X_add_symbol
);
6383 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6384 tempreg
, BFD_RELOC_LO16
);
6387 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6388 tempreg
, tempreg
, breg
);
6389 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6391 else if (mips_big_got
&& !HAVE_NEWABI
)
6395 /* If this is a reference to an external symbol, we want
6396 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6397 addu $tempreg,$tempreg,$gp
6398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6399 <op> $treg,0($tempreg)
6401 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6403 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6404 <op> $treg,0($tempreg)
6405 If there is a base register, we add it to $tempreg before
6406 the <op>. If there is a constant, we stick it in the
6407 <op> instruction. We don't handle constants larger than
6408 16 bits, because we have no way to load the upper 16 bits
6409 (actually, we could handle them for the subset of cases
6410 in which we are not using $at). */
6411 assert (offset_expr
.X_op
== O_symbol
);
6412 expr1
.X_add_number
= offset_expr
.X_add_number
;
6413 offset_expr
.X_add_number
= 0;
6414 if (expr1
.X_add_number
< -0x8000
6415 || expr1
.X_add_number
>= 0x8000)
6416 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6417 gpdelay
= reg_needs_delay (mips_gp_register
);
6418 relax_start (offset_expr
.X_add_symbol
);
6419 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6420 BFD_RELOC_MIPS_GOT_HI16
);
6421 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6423 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6424 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6427 macro_build (NULL
, "nop", "");
6428 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6429 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6431 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6432 tempreg
, BFD_RELOC_LO16
);
6436 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6437 tempreg
, tempreg
, breg
);
6438 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6440 else if (mips_big_got
&& HAVE_NEWABI
)
6442 /* If this is a reference to an external symbol, we want
6443 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6444 add $tempreg,$tempreg,$gp
6445 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6446 <op> $treg,<ofst>($tempreg)
6447 Otherwise, for local symbols, we want:
6448 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6449 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6450 assert (offset_expr
.X_op
== O_symbol
);
6451 expr1
.X_add_number
= offset_expr
.X_add_number
;
6452 offset_expr
.X_add_number
= 0;
6453 if (expr1
.X_add_number
< -0x8000
6454 || expr1
.X_add_number
>= 0x8000)
6455 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6456 relax_start (offset_expr
.X_add_symbol
);
6457 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6458 BFD_RELOC_MIPS_GOT_HI16
);
6459 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6461 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6462 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6464 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6465 tempreg
, tempreg
, breg
);
6466 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6469 offset_expr
.X_add_number
= expr1
.X_add_number
;
6470 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6471 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6473 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6474 tempreg
, tempreg
, breg
);
6475 macro_build (&offset_expr
, s
, fmt
, treg
,
6476 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6486 load_register (treg
, &imm_expr
, 0);
6490 load_register (treg
, &imm_expr
, 1);
6494 if (imm_expr
.X_op
== O_constant
)
6497 load_register (AT
, &imm_expr
, 0);
6498 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6503 assert (offset_expr
.X_op
== O_symbol
6504 && strcmp (segment_name (S_GET_SEGMENT
6505 (offset_expr
.X_add_symbol
)),
6507 && offset_expr
.X_add_number
== 0);
6508 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6509 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6514 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6515 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6516 order 32 bits of the value and the low order 32 bits are either
6517 zero or in OFFSET_EXPR. */
6518 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6520 if (HAVE_64BIT_GPRS
)
6521 load_register (treg
, &imm_expr
, 1);
6526 if (target_big_endian
)
6538 load_register (hreg
, &imm_expr
, 0);
6541 if (offset_expr
.X_op
== O_absent
)
6542 move_register (lreg
, 0);
6545 assert (offset_expr
.X_op
== O_constant
);
6546 load_register (lreg
, &offset_expr
, 0);
6553 /* We know that sym is in the .rdata section. First we get the
6554 upper 16 bits of the address. */
6555 if (mips_pic
== NO_PIC
)
6557 macro_build_lui (&offset_expr
, AT
);
6562 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6563 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6567 /* Now we load the register(s). */
6568 if (HAVE_64BIT_GPRS
)
6571 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6576 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6579 /* FIXME: How in the world do we deal with the possible
6581 offset_expr
.X_add_number
+= 4;
6582 macro_build (&offset_expr
, "lw", "t,o(b)",
6583 treg
+ 1, BFD_RELOC_LO16
, AT
);
6589 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6590 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6591 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6592 the value and the low order 32 bits are either zero or in
6594 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6597 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6598 if (HAVE_64BIT_FPRS
)
6600 assert (HAVE_64BIT_GPRS
);
6601 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6605 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6606 if (offset_expr
.X_op
== O_absent
)
6607 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6610 assert (offset_expr
.X_op
== O_constant
);
6611 load_register (AT
, &offset_expr
, 0);
6612 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6618 assert (offset_expr
.X_op
== O_symbol
6619 && offset_expr
.X_add_number
== 0);
6620 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6621 if (strcmp (s
, ".lit8") == 0)
6623 if (mips_opts
.isa
!= ISA_MIPS1
)
6625 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6626 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6629 breg
= mips_gp_register
;
6630 r
= BFD_RELOC_MIPS_LITERAL
;
6635 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6637 if (mips_pic
!= NO_PIC
)
6638 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6639 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6642 /* FIXME: This won't work for a 64 bit address. */
6643 macro_build_lui (&offset_expr
, AT
);
6646 if (mips_opts
.isa
!= ISA_MIPS1
)
6648 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6649 treg
, BFD_RELOC_LO16
, AT
);
6658 if (mips_opts
.arch
== CPU_R4650
)
6660 as_bad (_("opcode not supported on this processor"));
6663 /* Even on a big endian machine $fn comes before $fn+1. We have
6664 to adjust when loading from memory. */
6667 assert (mips_opts
.isa
== ISA_MIPS1
);
6668 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6669 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6670 /* FIXME: A possible overflow which I don't know how to deal
6672 offset_expr
.X_add_number
+= 4;
6673 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6674 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6679 * The MIPS assembler seems to check for X_add_number not
6680 * being double aligned and generating:
6683 * addiu at,at,%lo(foo+1)
6686 * But, the resulting address is the same after relocation so why
6687 * generate the extra instruction?
6689 if (mips_opts
.arch
== CPU_R4650
)
6691 as_bad (_("opcode not supported on this processor"));
6694 /* Itbl support may require additional care here. */
6696 if (mips_opts
.isa
!= ISA_MIPS1
)
6707 if (mips_opts
.arch
== CPU_R4650
)
6709 as_bad (_("opcode not supported on this processor"));
6713 if (mips_opts
.isa
!= ISA_MIPS1
)
6721 /* Itbl support may require additional care here. */
6726 if (HAVE_64BIT_GPRS
)
6737 if (HAVE_64BIT_GPRS
)
6747 if (offset_expr
.X_op
!= O_symbol
6748 && offset_expr
.X_op
!= O_constant
)
6750 as_bad (_("expression too complex"));
6751 offset_expr
.X_op
= O_constant
;
6754 if (HAVE_32BIT_ADDRESSES
6755 && !IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
6759 sprintf_vma (value
, offset_expr
.X_add_number
);
6760 as_bad (_("Number (0x%s) larger than 32 bits"), value
);
6763 /* Even on a big endian machine $fn comes before $fn+1. We have
6764 to adjust when loading from memory. We set coproc if we must
6765 load $fn+1 first. */
6766 /* Itbl support may require additional care here. */
6767 if (! target_big_endian
)
6770 if (mips_pic
== NO_PIC
6771 || offset_expr
.X_op
== O_constant
)
6773 /* If this is a reference to a GP relative symbol, we want
6774 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6775 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6776 If we have a base register, we use this
6778 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6779 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6780 If this is not a GP relative symbol, we want
6781 lui $at,<sym> (BFD_RELOC_HI16_S)
6782 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6783 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6784 If there is a base register, we add it to $at after the
6785 lui instruction. If there is a constant, we always use
6787 if (offset_expr
.X_op
== O_symbol
6788 && (valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6789 && !nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6791 relax_start (offset_expr
.X_add_symbol
);
6794 tempreg
= mips_gp_register
;
6798 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6799 AT
, breg
, mips_gp_register
);
6804 /* Itbl support may require additional care here. */
6805 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6806 BFD_RELOC_GPREL16
, tempreg
);
6807 offset_expr
.X_add_number
+= 4;
6809 /* Set mips_optimize to 2 to avoid inserting an
6811 hold_mips_optimize
= mips_optimize
;
6813 /* Itbl support may require additional care here. */
6814 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6815 BFD_RELOC_GPREL16
, tempreg
);
6816 mips_optimize
= hold_mips_optimize
;
6820 /* We just generated two relocs. When tc_gen_reloc
6821 handles this case, it will skip the first reloc and
6822 handle the second. The second reloc already has an
6823 extra addend of 4, which we added above. We must
6824 subtract it out, and then subtract another 4 to make
6825 the first reloc come out right. The second reloc
6826 will come out right because we are going to add 4 to
6827 offset_expr when we build its instruction below.
6829 If we have a symbol, then we don't want to include
6830 the offset, because it will wind up being included
6831 when we generate the reloc. */
6833 if (offset_expr
.X_op
== O_constant
)
6834 offset_expr
.X_add_number
-= 8;
6837 offset_expr
.X_add_number
= -4;
6838 offset_expr
.X_op
= O_constant
;
6842 macro_build_lui (&offset_expr
, AT
);
6844 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6845 /* Itbl support may require additional care here. */
6846 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6847 BFD_RELOC_LO16
, AT
);
6848 /* FIXME: How do we handle overflow here? */
6849 offset_expr
.X_add_number
+= 4;
6850 /* Itbl support may require additional care here. */
6851 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6852 BFD_RELOC_LO16
, AT
);
6853 if (mips_relax
.sequence
)
6856 else if (!mips_big_got
)
6858 /* If this is a reference to an external symbol, we want
6859 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6864 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6866 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6867 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6868 If there is a base register we add it to $at before the
6869 lwc1 instructions. If there is a constant we include it
6870 in the lwc1 instructions. */
6872 expr1
.X_add_number
= offset_expr
.X_add_number
;
6873 if (expr1
.X_add_number
< -0x8000
6874 || expr1
.X_add_number
>= 0x8000 - 4)
6875 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6876 load_got_offset (AT
, &offset_expr
);
6879 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6881 /* Set mips_optimize to 2 to avoid inserting an undesired
6883 hold_mips_optimize
= mips_optimize
;
6886 /* Itbl support may require additional care here. */
6887 relax_start (offset_expr
.X_add_symbol
);
6888 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6889 BFD_RELOC_LO16
, AT
);
6890 expr1
.X_add_number
+= 4;
6891 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6892 BFD_RELOC_LO16
, AT
);
6894 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6895 BFD_RELOC_LO16
, AT
);
6896 offset_expr
.X_add_number
+= 4;
6897 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6898 BFD_RELOC_LO16
, AT
);
6901 mips_optimize
= hold_mips_optimize
;
6903 else if (mips_big_got
)
6907 /* If this is a reference to an external symbol, we want
6908 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6910 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6915 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6917 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6918 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6919 If there is a base register we add it to $at before the
6920 lwc1 instructions. If there is a constant we include it
6921 in the lwc1 instructions. */
6923 expr1
.X_add_number
= offset_expr
.X_add_number
;
6924 offset_expr
.X_add_number
= 0;
6925 if (expr1
.X_add_number
< -0x8000
6926 || expr1
.X_add_number
>= 0x8000 - 4)
6927 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6928 gpdelay
= reg_needs_delay (mips_gp_register
);
6929 relax_start (offset_expr
.X_add_symbol
);
6930 macro_build (&offset_expr
, "lui", "t,u",
6931 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6932 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6933 AT
, AT
, mips_gp_register
);
6934 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6935 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6938 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6939 /* Itbl support may require additional care here. */
6940 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6941 BFD_RELOC_LO16
, AT
);
6942 expr1
.X_add_number
+= 4;
6944 /* Set mips_optimize to 2 to avoid inserting an undesired
6946 hold_mips_optimize
= mips_optimize
;
6948 /* Itbl support may require additional care here. */
6949 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6950 BFD_RELOC_LO16
, AT
);
6951 mips_optimize
= hold_mips_optimize
;
6952 expr1
.X_add_number
-= 4;
6955 offset_expr
.X_add_number
= expr1
.X_add_number
;
6957 macro_build (NULL
, "nop", "");
6958 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6959 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6962 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6963 /* Itbl support may require additional care here. */
6964 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6965 BFD_RELOC_LO16
, AT
);
6966 offset_expr
.X_add_number
+= 4;
6968 /* Set mips_optimize to 2 to avoid inserting an undesired
6970 hold_mips_optimize
= mips_optimize
;
6972 /* Itbl support may require additional care here. */
6973 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6974 BFD_RELOC_LO16
, AT
);
6975 mips_optimize
= hold_mips_optimize
;
6989 assert (HAVE_32BIT_ADDRESSES
);
6990 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6991 offset_expr
.X_add_number
+= 4;
6992 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6995 /* New code added to support COPZ instructions.
6996 This code builds table entries out of the macros in mip_opcodes.
6997 R4000 uses interlocks to handle coproc delays.
6998 Other chips (like the R3000) require nops to be inserted for delays.
7000 FIXME: Currently, we require that the user handle delays.
7001 In order to fill delay slots for non-interlocked chips,
7002 we must have a way to specify delays based on the coprocessor.
7003 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
7004 What are the side-effects of the cop instruction?
7005 What cache support might we have and what are its effects?
7006 Both coprocessor & memory require delays. how long???
7007 What registers are read/set/modified?
7009 If an itbl is provided to interpret cop instructions,
7010 this knowledge can be encoded in the itbl spec. */
7024 /* For now we just do C (same as Cz). The parameter will be
7025 stored in insn_opcode by mips_ip. */
7026 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
7030 move_register (dreg
, sreg
);
7033 #ifdef LOSING_COMPILER
7035 /* Try and see if this is a new itbl instruction.
7036 This code builds table entries out of the macros in mip_opcodes.
7037 FIXME: For now we just assemble the expression and pass it's
7038 value along as a 32-bit immediate.
7039 We may want to have the assembler assemble this value,
7040 so that we gain the assembler's knowledge of delay slots,
7042 Would it be more efficient to use mask (id) here? */
7043 if (itbl_have_entries
7044 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
7046 s
= ip
->insn_mo
->name
;
7048 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
7049 macro_build (&immed_expr
, s
, "C");
7055 if (mips_opts
.noat
&& used_at
)
7056 as_bad (_("Macro used $at after \".set noat\""));
7060 macro2 (struct mips_cl_insn
*ip
)
7062 register int treg
, sreg
, dreg
, breg
;
7077 bfd_reloc_code_real_type r
;
7079 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
7080 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
7081 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
7082 mask
= ip
->insn_mo
->mask
;
7084 expr1
.X_op
= O_constant
;
7085 expr1
.X_op_symbol
= NULL
;
7086 expr1
.X_add_symbol
= NULL
;
7087 expr1
.X_add_number
= 1;
7091 #endif /* LOSING_COMPILER */
7096 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
7097 macro_build (NULL
, "mflo", "d", dreg
);
7103 /* The MIPS assembler some times generates shifts and adds. I'm
7104 not trying to be that fancy. GCC should do this for us
7107 load_register (AT
, &imm_expr
, dbl
);
7108 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
7109 macro_build (NULL
, "mflo", "d", dreg
);
7125 load_register (AT
, &imm_expr
, dbl
);
7126 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
7127 macro_build (NULL
, "mflo", "d", dreg
);
7128 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
7129 macro_build (NULL
, "mfhi", "d", AT
);
7131 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
7134 expr1
.X_add_number
= 8;
7135 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
7136 macro_build (NULL
, "nop", "", 0);
7137 macro_build (NULL
, "break", "c", 6);
7140 macro_build (NULL
, "mflo", "d", dreg
);
7156 load_register (AT
, &imm_expr
, dbl
);
7157 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7158 sreg
, imm
? AT
: treg
);
7159 macro_build (NULL
, "mfhi", "d", AT
);
7160 macro_build (NULL
, "mflo", "d", dreg
);
7162 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7165 expr1
.X_add_number
= 8;
7166 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7167 macro_build (NULL
, "nop", "", 0);
7168 macro_build (NULL
, "break", "c", 6);
7174 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7185 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7186 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7190 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7191 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7192 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7193 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7197 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7208 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7209 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7213 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7214 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7215 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7216 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7224 if (imm_expr
.X_op
!= O_constant
)
7225 as_bad (_("Improper rotate count"));
7226 rot
= imm_expr
.X_add_number
& 0x3f;
7227 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7229 rot
= (64 - rot
) & 0x3f;
7231 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7233 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7238 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7241 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7242 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7245 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7246 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7247 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7255 if (imm_expr
.X_op
!= O_constant
)
7256 as_bad (_("Improper rotate count"));
7257 rot
= imm_expr
.X_add_number
& 0x1f;
7258 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7260 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7265 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7269 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7270 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7271 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7276 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7278 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7282 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7283 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7284 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7285 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7289 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7291 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7295 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7296 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7297 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7298 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7306 if (imm_expr
.X_op
!= O_constant
)
7307 as_bad (_("Improper rotate count"));
7308 rot
= imm_expr
.X_add_number
& 0x3f;
7309 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7312 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7314 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7319 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7322 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7323 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7326 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7327 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7328 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7336 if (imm_expr
.X_op
!= O_constant
)
7337 as_bad (_("Improper rotate count"));
7338 rot
= imm_expr
.X_add_number
& 0x1f;
7339 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7341 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7346 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7350 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7351 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7352 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7357 if (mips_opts
.arch
== CPU_R4650
)
7359 as_bad (_("opcode not supported on this processor"));
7362 assert (mips_opts
.isa
== ISA_MIPS1
);
7363 /* Even on a big endian machine $fn comes before $fn+1. We have
7364 to adjust when storing to memory. */
7365 macro_build (&offset_expr
, "swc1", "T,o(b)",
7366 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7367 offset_expr
.X_add_number
+= 4;
7368 macro_build (&offset_expr
, "swc1", "T,o(b)",
7369 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7374 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7376 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7379 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7380 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7385 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7387 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7392 as_warn (_("Instruction %s: result is always false"),
7394 move_register (dreg
, 0);
7397 if (imm_expr
.X_op
== O_constant
7398 && imm_expr
.X_add_number
>= 0
7399 && imm_expr
.X_add_number
< 0x10000)
7401 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7403 else if (imm_expr
.X_op
== O_constant
7404 && imm_expr
.X_add_number
> -0x8000
7405 && imm_expr
.X_add_number
< 0)
7407 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7408 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7409 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7413 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7414 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7417 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7420 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7426 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7427 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7430 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7432 if (imm_expr
.X_op
== O_constant
7433 && imm_expr
.X_add_number
>= -0x8000
7434 && imm_expr
.X_add_number
< 0x8000)
7436 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7437 dreg
, sreg
, BFD_RELOC_LO16
);
7441 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7442 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7446 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7449 case M_SGT
: /* sreg > treg <==> treg < sreg */
7455 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7458 case M_SGT_I
: /* sreg > I <==> I < sreg */
7465 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7466 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7469 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7475 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7476 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7479 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7486 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7487 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7488 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7492 if (imm_expr
.X_op
== O_constant
7493 && imm_expr
.X_add_number
>= -0x8000
7494 && imm_expr
.X_add_number
< 0x8000)
7496 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7500 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7501 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7505 if (imm_expr
.X_op
== O_constant
7506 && imm_expr
.X_add_number
>= -0x8000
7507 && imm_expr
.X_add_number
< 0x8000)
7509 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7514 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7515 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7520 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7522 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7525 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7526 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7531 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7533 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7538 as_warn (_("Instruction %s: result is always true"),
7540 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7541 dreg
, 0, BFD_RELOC_LO16
);
7544 if (imm_expr
.X_op
== O_constant
7545 && imm_expr
.X_add_number
>= 0
7546 && imm_expr
.X_add_number
< 0x10000)
7548 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7550 else if (imm_expr
.X_op
== O_constant
7551 && imm_expr
.X_add_number
> -0x8000
7552 && imm_expr
.X_add_number
< 0)
7554 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7555 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7556 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7560 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7561 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7564 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7570 if (imm_expr
.X_op
== O_constant
7571 && imm_expr
.X_add_number
> -0x8000
7572 && imm_expr
.X_add_number
<= 0x8000)
7574 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7575 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7576 dreg
, sreg
, BFD_RELOC_LO16
);
7580 load_register (AT
, &imm_expr
, dbl
);
7581 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7587 if (imm_expr
.X_op
== O_constant
7588 && imm_expr
.X_add_number
> -0x8000
7589 && imm_expr
.X_add_number
<= 0x8000)
7591 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7592 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7593 dreg
, sreg
, BFD_RELOC_LO16
);
7597 load_register (AT
, &imm_expr
, dbl
);
7598 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7620 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7621 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7626 assert (mips_opts
.isa
== ISA_MIPS1
);
7628 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7629 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7632 * Is the double cfc1 instruction a bug in the mips assembler;
7633 * or is there a reason for it?
7636 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7637 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7638 macro_build (NULL
, "nop", "");
7639 expr1
.X_add_number
= 3;
7640 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7641 expr1
.X_add_number
= 2;
7642 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7643 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7644 macro_build (NULL
, "nop", "");
7645 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7647 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7648 macro_build (NULL
, "nop", "");
7659 if (offset_expr
.X_add_number
>= 0x7fff)
7660 as_bad (_("operand overflow"));
7661 if (! target_big_endian
)
7662 ++offset_expr
.X_add_number
;
7663 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7664 if (! target_big_endian
)
7665 --offset_expr
.X_add_number
;
7667 ++offset_expr
.X_add_number
;
7668 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7669 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7670 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7683 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7684 as_bad (_("operand overflow"));
7692 if (! target_big_endian
)
7693 offset_expr
.X_add_number
+= off
;
7694 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7695 if (! target_big_endian
)
7696 offset_expr
.X_add_number
-= off
;
7698 offset_expr
.X_add_number
+= off
;
7699 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7701 /* If necessary, move the result in tempreg the final destination. */
7702 if (treg
== tempreg
)
7704 /* Protect second load's delay slot. */
7706 move_register (treg
, tempreg
);
7720 load_address (AT
, &offset_expr
, &used_at
);
7722 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7723 if (! target_big_endian
)
7724 expr1
.X_add_number
= off
;
7726 expr1
.X_add_number
= 0;
7727 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7728 if (! target_big_endian
)
7729 expr1
.X_add_number
= 0;
7731 expr1
.X_add_number
= off
;
7732 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7738 load_address (AT
, &offset_expr
, &used_at
);
7740 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7741 if (target_big_endian
)
7742 expr1
.X_add_number
= 0;
7743 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7744 treg
, BFD_RELOC_LO16
, AT
);
7745 if (target_big_endian
)
7746 expr1
.X_add_number
= 1;
7748 expr1
.X_add_number
= 0;
7749 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7750 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7751 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7756 if (offset_expr
.X_add_number
>= 0x7fff)
7757 as_bad (_("operand overflow"));
7758 if (target_big_endian
)
7759 ++offset_expr
.X_add_number
;
7760 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7761 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7762 if (target_big_endian
)
7763 --offset_expr
.X_add_number
;
7765 ++offset_expr
.X_add_number
;
7766 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7779 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7780 as_bad (_("operand overflow"));
7781 if (! target_big_endian
)
7782 offset_expr
.X_add_number
+= off
;
7783 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7784 if (! target_big_endian
)
7785 offset_expr
.X_add_number
-= off
;
7787 offset_expr
.X_add_number
+= off
;
7788 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7802 load_address (AT
, &offset_expr
, &used_at
);
7804 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7805 if (! target_big_endian
)
7806 expr1
.X_add_number
= off
;
7808 expr1
.X_add_number
= 0;
7809 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7810 if (! target_big_endian
)
7811 expr1
.X_add_number
= 0;
7813 expr1
.X_add_number
= off
;
7814 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7819 load_address (AT
, &offset_expr
, &used_at
);
7821 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7822 if (! target_big_endian
)
7823 expr1
.X_add_number
= 0;
7824 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7825 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7826 if (! target_big_endian
)
7827 expr1
.X_add_number
= 1;
7829 expr1
.X_add_number
= 0;
7830 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7831 if (! target_big_endian
)
7832 expr1
.X_add_number
= 0;
7834 expr1
.X_add_number
= 1;
7835 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7836 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7837 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7841 /* FIXME: Check if this is one of the itbl macros, since they
7842 are added dynamically. */
7843 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7846 if (mips_opts
.noat
&& used_at
)
7847 as_bad (_("Macro used $at after \".set noat\""));
7850 /* Implement macros in mips16 mode. */
7853 mips16_macro (struct mips_cl_insn
*ip
)
7856 int xreg
, yreg
, zreg
, tmp
;
7859 const char *s
, *s2
, *s3
;
7861 mask
= ip
->insn_mo
->mask
;
7863 xreg
= MIPS16_EXTRACT_OPERAND (RX
, *ip
);
7864 yreg
= MIPS16_EXTRACT_OPERAND (RY
, *ip
);
7865 zreg
= MIPS16_EXTRACT_OPERAND (RZ
, *ip
);
7867 expr1
.X_op
= O_constant
;
7868 expr1
.X_op_symbol
= NULL
;
7869 expr1
.X_add_symbol
= NULL
;
7870 expr1
.X_add_number
= 1;
7890 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7891 expr1
.X_add_number
= 2;
7892 macro_build (&expr1
, "bnez", "x,p", yreg
);
7893 macro_build (NULL
, "break", "6", 7);
7895 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7896 since that causes an overflow. We should do that as well,
7897 but I don't see how to do the comparisons without a temporary
7900 macro_build (NULL
, s
, "x", zreg
);
7920 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7921 expr1
.X_add_number
= 2;
7922 macro_build (&expr1
, "bnez", "x,p", yreg
);
7923 macro_build (NULL
, "break", "6", 7);
7925 macro_build (NULL
, s2
, "x", zreg
);
7931 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7932 macro_build (NULL
, "mflo", "x", zreg
);
7940 if (imm_expr
.X_op
!= O_constant
)
7941 as_bad (_("Unsupported large constant"));
7942 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7943 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7947 if (imm_expr
.X_op
!= O_constant
)
7948 as_bad (_("Unsupported large constant"));
7949 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7950 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7954 if (imm_expr
.X_op
!= O_constant
)
7955 as_bad (_("Unsupported large constant"));
7956 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7957 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7979 goto do_reverse_branch
;
7983 goto do_reverse_branch
;
7995 goto do_reverse_branch
;
8006 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
8007 macro_build (&offset_expr
, s2
, "p");
8034 goto do_addone_branch_i
;
8039 goto do_addone_branch_i
;
8054 goto do_addone_branch_i
;
8061 if (imm_expr
.X_op
!= O_constant
)
8062 as_bad (_("Unsupported large constant"));
8063 ++imm_expr
.X_add_number
;
8066 macro_build (&imm_expr
, s
, s3
, xreg
);
8067 macro_build (&offset_expr
, s2
, "p");
8071 expr1
.X_add_number
= 0;
8072 macro_build (&expr1
, "slti", "x,8", yreg
);
8074 move_register (xreg
, yreg
);
8075 expr1
.X_add_number
= 2;
8076 macro_build (&expr1
, "bteqz", "p");
8077 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
8081 /* For consistency checking, verify that all bits are specified either
8082 by the match/mask part of the instruction definition, or by the
8085 validate_mips_insn (const struct mips_opcode
*opc
)
8087 const char *p
= opc
->args
;
8089 unsigned long used_bits
= opc
->mask
;
8091 if ((used_bits
& opc
->match
) != opc
->match
)
8093 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
8094 opc
->name
, opc
->args
);
8097 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
8107 case '1': USE_BITS (OP_MASK_UDI1
, OP_SH_UDI1
); break;
8108 case '2': USE_BITS (OP_MASK_UDI2
, OP_SH_UDI2
); break;
8109 case '3': USE_BITS (OP_MASK_UDI3
, OP_SH_UDI3
); break;
8110 case '4': USE_BITS (OP_MASK_UDI4
, OP_SH_UDI4
); break;
8111 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8112 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8113 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8114 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8115 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8116 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8117 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
8118 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8119 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
8121 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8122 case 'T': USE_BITS (OP_MASK_RT
, OP_SH_RT
);
8123 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8125 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8126 c
, opc
->name
, opc
->args
);
8130 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8131 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
8133 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
8134 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
8135 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8136 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8138 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8139 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
8141 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
8142 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8144 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
8145 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
8146 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
8147 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
8148 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8149 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
8150 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8151 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8152 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8153 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8154 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
8155 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
8156 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
8157 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8158 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8159 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8160 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8162 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8163 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8164 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8165 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8167 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8168 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8169 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8170 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8171 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8172 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8173 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8174 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8175 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8178 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8179 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8180 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8181 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8182 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8185 case '3': USE_BITS (OP_MASK_SA3
, OP_SH_SA3
); break;
8186 case '4': USE_BITS (OP_MASK_SA4
, OP_SH_SA4
); break;
8187 case '5': USE_BITS (OP_MASK_IMM8
, OP_SH_IMM8
); break;
8188 case '6': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8189 case '7': USE_BITS (OP_MASK_DSPACC
, OP_SH_DSPACC
); break;
8190 case '8': USE_BITS (OP_MASK_WRDSP
, OP_SH_WRDSP
); break;
8191 case '9': USE_BITS (OP_MASK_DSPACC_S
, OP_SH_DSPACC_S
);break;
8192 case '0': USE_BITS (OP_MASK_DSPSFT
, OP_SH_DSPSFT
); break;
8193 case '\'': USE_BITS (OP_MASK_RDDSP
, OP_SH_RDDSP
); break;
8194 case ':': USE_BITS (OP_MASK_DSPSFT_7
, OP_SH_DSPSFT_7
);break;
8195 case '@': USE_BITS (OP_MASK_IMM10
, OP_SH_IMM10
); break;
8196 case '!': USE_BITS (OP_MASK_MT_U
, OP_SH_MT_U
); break;
8197 case '$': USE_BITS (OP_MASK_MT_H
, OP_SH_MT_H
); break;
8198 case '*': USE_BITS (OP_MASK_MTACC_T
, OP_SH_MTACC_T
); break;
8199 case '&': USE_BITS (OP_MASK_MTACC_D
, OP_SH_MTACC_D
); break;
8200 case 'g': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8202 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8203 c
, opc
->name
, opc
->args
);
8207 if (used_bits
!= 0xffffffff)
8209 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8210 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8216 /* UDI immediates. */
8224 static const struct mips_immed mips_immed
[] = {
8225 { '1', OP_SH_UDI1
, OP_MASK_UDI1
, 0},
8226 { '2', OP_SH_UDI2
, OP_MASK_UDI2
, 0},
8227 { '3', OP_SH_UDI3
, OP_MASK_UDI3
, 0},
8228 { '4', OP_SH_UDI4
, OP_MASK_UDI4
, 0},
8232 /* Check whether an odd floating-point register is allowed. */
8234 mips_oddfpreg_ok (const struct mips_opcode
*insn
, int argnum
)
8236 const char *s
= insn
->name
;
8238 if (insn
->pinfo
== INSN_MACRO
)
8239 /* Let a macro pass, we'll catch it later when it is expanded. */
8242 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts
.isa
))
8244 /* Allow odd registers for single-precision ops. */
8245 switch (insn
->pinfo
& (FP_S
| FP_D
))
8249 return 1; /* both single precision - ok */
8251 return 0; /* both double precision - fail */
8256 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8257 s
= strchr (insn
->name
, '.');
8259 s
= s
!= NULL
? strchr (s
+ 1, '.') : NULL
;
8260 return (s
!= NULL
&& (s
[1] == 'w' || s
[1] == 's'));
8263 /* Single-precision coprocessor loads and moves are OK too. */
8264 if ((insn
->pinfo
& FP_S
)
8265 && (insn
->pinfo
& (INSN_COPROC_MEMORY_DELAY
| INSN_STORE_MEMORY
8266 | INSN_LOAD_COPROC_DELAY
| INSN_COPROC_MOVE_DELAY
)))
8272 /* This routine assembles an instruction into its binary format. As a
8273 side effect, it sets one of the global variables imm_reloc or
8274 offset_reloc to the type of relocation to do if one of the operands
8275 is an address expression. */
8278 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8283 struct mips_opcode
*insn
;
8286 unsigned int lastregno
= 0;
8287 unsigned int lastpos
= 0;
8288 unsigned int limlo
, limhi
;
8291 offsetT min_range
, max_range
;
8297 /* If the instruction contains a '.', we first try to match an instruction
8298 including the '.'. Then we try again without the '.'. */
8300 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8303 /* If we stopped on whitespace, then replace the whitespace with null for
8304 the call to hash_find. Save the character we replaced just in case we
8305 have to re-parse the instruction. */
8312 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8314 /* If we didn't find the instruction in the opcode table, try again, but
8315 this time with just the instruction up to, but not including the
8319 /* Restore the character we overwrite above (if any). */
8323 /* Scan up to the first '.' or whitespace. */
8325 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8329 /* If we did not find a '.', then we can quit now. */
8332 insn_error
= "unrecognized opcode";
8336 /* Lookup the instruction in the hash table. */
8338 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8340 insn_error
= "unrecognized opcode";
8350 assert (strcmp (insn
->name
, str
) == 0);
8352 if (OPCODE_IS_MEMBER (insn
,
8354 /* We don't check for mips_opts.mips16 here since
8355 we want to allow jalx if -mips16 was specified
8356 on the command line. */
8357 | (file_ase_mips16
? INSN_MIPS16
: 0)
8358 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8359 | (mips_opts
.ase_dsp
? INSN_DSP
: 0)
8360 | ((mips_opts
.ase_dsp
&& ISA_SUPPORTS_DSP64_ASE
)
8362 | (mips_opts
.ase_mt
? INSN_MT
: 0)
8363 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)
8364 | (mips_opts
.ase_smartmips
? INSN_SMARTMIPS
: 0)),
8370 if (insn
->pinfo
!= INSN_MACRO
)
8372 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8378 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8379 && strcmp (insn
->name
, insn
[1].name
) == 0)
8388 static char buf
[100];
8390 _("opcode not supported on this processor: %s (%s)"),
8391 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8392 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8401 create_insn (ip
, insn
);
8404 for (args
= insn
->args
;; ++args
)
8408 s
+= strspn (s
, " \t");
8412 case '\0': /* end of args */
8417 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8418 my_getExpression (&imm_expr
, s
);
8419 check_absolute_expr (ip
, &imm_expr
);
8420 if (imm_expr
.X_add_number
& ~OP_MASK_SA3
)
8422 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8423 OP_MASK_SA3
, (unsigned long) imm_expr
.X_add_number
);
8425 INSERT_OPERAND (SA3
, *ip
, imm_expr
.X_add_number
);
8426 imm_expr
.X_op
= O_absent
;
8430 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8431 my_getExpression (&imm_expr
, s
);
8432 check_absolute_expr (ip
, &imm_expr
);
8433 if (imm_expr
.X_add_number
& ~OP_MASK_SA4
)
8435 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8436 OP_MASK_SA4
, (unsigned long) imm_expr
.X_add_number
);
8438 INSERT_OPERAND (SA4
, *ip
, imm_expr
.X_add_number
);
8439 imm_expr
.X_op
= O_absent
;
8443 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8444 my_getExpression (&imm_expr
, s
);
8445 check_absolute_expr (ip
, &imm_expr
);
8446 if (imm_expr
.X_add_number
& ~OP_MASK_IMM8
)
8448 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8449 OP_MASK_IMM8
, (unsigned long) imm_expr
.X_add_number
);
8451 INSERT_OPERAND (IMM8
, *ip
, imm_expr
.X_add_number
);
8452 imm_expr
.X_op
= O_absent
;
8456 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8457 my_getExpression (&imm_expr
, s
);
8458 check_absolute_expr (ip
, &imm_expr
);
8459 if (imm_expr
.X_add_number
& ~OP_MASK_RS
)
8461 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8462 OP_MASK_RS
, (unsigned long) imm_expr
.X_add_number
);
8464 INSERT_OPERAND (RS
, *ip
, imm_expr
.X_add_number
);
8465 imm_expr
.X_op
= O_absent
;
8469 case '7': /* four dsp accumulators in bits 11,12 */
8470 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8471 s
[3] >= '0' && s
[3] <= '3')
8475 INSERT_OPERAND (DSPACC
, *ip
, regno
);
8479 as_bad (_("Invalid dsp acc register"));
8482 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8483 my_getExpression (&imm_expr
, s
);
8484 check_absolute_expr (ip
, &imm_expr
);
8485 if (imm_expr
.X_add_number
& ~OP_MASK_WRDSP
)
8487 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8489 (unsigned long) imm_expr
.X_add_number
);
8491 INSERT_OPERAND (WRDSP
, *ip
, imm_expr
.X_add_number
);
8492 imm_expr
.X_op
= O_absent
;
8496 case '9': /* four dsp accumulators in bits 21,22 */
8497 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8498 s
[3] >= '0' && s
[3] <= '3')
8502 INSERT_OPERAND (DSPACC_S
, *ip
, regno
);
8506 as_bad (_("Invalid dsp acc register"));
8509 case '0': /* dsp 6-bit signed immediate in bit 20 */
8510 my_getExpression (&imm_expr
, s
);
8511 check_absolute_expr (ip
, &imm_expr
);
8512 min_range
= -((OP_MASK_DSPSFT
+ 1) >> 1);
8513 max_range
= ((OP_MASK_DSPSFT
+ 1) >> 1) - 1;
8514 if (imm_expr
.X_add_number
< min_range
||
8515 imm_expr
.X_add_number
> max_range
)
8517 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8518 (long) min_range
, (long) max_range
,
8519 (long) imm_expr
.X_add_number
);
8521 INSERT_OPERAND (DSPSFT
, *ip
, imm_expr
.X_add_number
);
8522 imm_expr
.X_op
= O_absent
;
8526 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8527 my_getExpression (&imm_expr
, s
);
8528 check_absolute_expr (ip
, &imm_expr
);
8529 if (imm_expr
.X_add_number
& ~OP_MASK_RDDSP
)
8531 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8533 (unsigned long) imm_expr
.X_add_number
);
8535 INSERT_OPERAND (RDDSP
, *ip
, imm_expr
.X_add_number
);
8536 imm_expr
.X_op
= O_absent
;
8540 case ':': /* dsp 7-bit signed immediate in bit 19 */
8541 my_getExpression (&imm_expr
, s
);
8542 check_absolute_expr (ip
, &imm_expr
);
8543 min_range
= -((OP_MASK_DSPSFT_7
+ 1) >> 1);
8544 max_range
= ((OP_MASK_DSPSFT_7
+ 1) >> 1) - 1;
8545 if (imm_expr
.X_add_number
< min_range
||
8546 imm_expr
.X_add_number
> max_range
)
8548 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8549 (long) min_range
, (long) max_range
,
8550 (long) imm_expr
.X_add_number
);
8552 INSERT_OPERAND (DSPSFT_7
, *ip
, imm_expr
.X_add_number
);
8553 imm_expr
.X_op
= O_absent
;
8557 case '@': /* dsp 10-bit signed immediate in bit 16 */
8558 my_getExpression (&imm_expr
, s
);
8559 check_absolute_expr (ip
, &imm_expr
);
8560 min_range
= -((OP_MASK_IMM10
+ 1) >> 1);
8561 max_range
= ((OP_MASK_IMM10
+ 1) >> 1) - 1;
8562 if (imm_expr
.X_add_number
< min_range
||
8563 imm_expr
.X_add_number
> max_range
)
8565 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8566 (long) min_range
, (long) max_range
,
8567 (long) imm_expr
.X_add_number
);
8569 INSERT_OPERAND (IMM10
, *ip
, imm_expr
.X_add_number
);
8570 imm_expr
.X_op
= O_absent
;
8574 case '!': /* MT usermode flag bit. */
8575 my_getExpression (&imm_expr
, s
);
8576 check_absolute_expr (ip
, &imm_expr
);
8577 if (imm_expr
.X_add_number
& ~OP_MASK_MT_U
)
8578 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8579 (unsigned long) imm_expr
.X_add_number
);
8580 INSERT_OPERAND (MT_U
, *ip
, imm_expr
.X_add_number
);
8581 imm_expr
.X_op
= O_absent
;
8585 case '$': /* MT load high flag bit. */
8586 my_getExpression (&imm_expr
, s
);
8587 check_absolute_expr (ip
, &imm_expr
);
8588 if (imm_expr
.X_add_number
& ~OP_MASK_MT_H
)
8589 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8590 (unsigned long) imm_expr
.X_add_number
);
8591 INSERT_OPERAND (MT_H
, *ip
, imm_expr
.X_add_number
);
8592 imm_expr
.X_op
= O_absent
;
8596 case '*': /* four dsp accumulators in bits 18,19 */
8597 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8598 s
[3] >= '0' && s
[3] <= '3')
8602 INSERT_OPERAND (MTACC_T
, *ip
, regno
);
8606 as_bad (_("Invalid dsp/smartmips acc register"));
8609 case '&': /* four dsp accumulators in bits 13,14 */
8610 if (s
[0] == '$' && s
[1] == 'a' && s
[2] == 'c' &&
8611 s
[3] >= '0' && s
[3] <= '3')
8615 INSERT_OPERAND (MTACC_D
, *ip
, regno
);
8619 as_bad (_("Invalid dsp/smartmips acc register"));
8631 INSERT_OPERAND (RS
, *ip
, lastregno
);
8635 INSERT_OPERAND (RT
, *ip
, lastregno
);
8639 INSERT_OPERAND (FT
, *ip
, lastregno
);
8643 INSERT_OPERAND (FS
, *ip
, lastregno
);
8649 /* Handle optional base register.
8650 Either the base register is omitted or
8651 we must have a left paren. */
8652 /* This is dependent on the next operand specifier
8653 is a base register specification. */
8654 assert (args
[1] == 'b' || args
[1] == '5'
8655 || args
[1] == '-' || args
[1] == '4');
8659 case ')': /* these must match exactly */
8666 case '+': /* Opcode extension character. */
8669 case '1': /* UDI immediates. */
8674 const struct mips_immed
*imm
= mips_immed
;
8676 while (imm
->type
&& imm
->type
!= *args
)
8680 my_getExpression (&imm_expr
, s
);
8681 check_absolute_expr (ip
, &imm_expr
);
8682 if ((unsigned long) imm_expr
.X_add_number
& ~imm
->mask
)
8684 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
8685 imm
->desc
? imm
->desc
: ip
->insn_mo
->name
,
8686 (unsigned long) imm_expr
.X_add_number
,
8687 (unsigned long) imm_expr
.X_add_number
);
8688 imm_expr
.X_add_number
&= imm
->mask
;
8690 ip
->insn_opcode
|= ((unsigned long) imm_expr
.X_add_number
8692 imm_expr
.X_op
= O_absent
;
8697 case 'A': /* ins/ext position, becomes LSB. */
8706 my_getExpression (&imm_expr
, s
);
8707 check_absolute_expr (ip
, &imm_expr
);
8708 if ((unsigned long) imm_expr
.X_add_number
< limlo
8709 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8711 as_bad (_("Improper position (%lu)"),
8712 (unsigned long) imm_expr
.X_add_number
);
8713 imm_expr
.X_add_number
= limlo
;
8715 lastpos
= imm_expr
.X_add_number
;
8716 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8717 imm_expr
.X_op
= O_absent
;
8721 case 'B': /* ins size, becomes MSB. */
8730 my_getExpression (&imm_expr
, s
);
8731 check_absolute_expr (ip
, &imm_expr
);
8732 /* Check for negative input so that small negative numbers
8733 will not succeed incorrectly. The checks against
8734 (pos+size) transitively check "size" itself,
8735 assuming that "pos" is reasonable. */
8736 if ((long) imm_expr
.X_add_number
< 0
8737 || ((unsigned long) imm_expr
.X_add_number
8739 || ((unsigned long) imm_expr
.X_add_number
8742 as_bad (_("Improper insert size (%lu, position %lu)"),
8743 (unsigned long) imm_expr
.X_add_number
,
8744 (unsigned long) lastpos
);
8745 imm_expr
.X_add_number
= limlo
- lastpos
;
8747 INSERT_OPERAND (INSMSB
, *ip
,
8748 lastpos
+ imm_expr
.X_add_number
- 1);
8749 imm_expr
.X_op
= O_absent
;
8753 case 'C': /* ext size, becomes MSBD. */
8766 my_getExpression (&imm_expr
, s
);
8767 check_absolute_expr (ip
, &imm_expr
);
8768 /* Check for negative input so that small negative numbers
8769 will not succeed incorrectly. The checks against
8770 (pos+size) transitively check "size" itself,
8771 assuming that "pos" is reasonable. */
8772 if ((long) imm_expr
.X_add_number
< 0
8773 || ((unsigned long) imm_expr
.X_add_number
8775 || ((unsigned long) imm_expr
.X_add_number
8778 as_bad (_("Improper extract size (%lu, position %lu)"),
8779 (unsigned long) imm_expr
.X_add_number
,
8780 (unsigned long) lastpos
);
8781 imm_expr
.X_add_number
= limlo
- lastpos
;
8783 INSERT_OPERAND (EXTMSBD
, *ip
, imm_expr
.X_add_number
- 1);
8784 imm_expr
.X_op
= O_absent
;
8789 /* +D is for disassembly only; never match. */
8793 /* "+I" is like "I", except that imm2_expr is used. */
8794 my_getExpression (&imm2_expr
, s
);
8795 if (imm2_expr
.X_op
!= O_big
8796 && imm2_expr
.X_op
!= O_constant
)
8797 insn_error
= _("absolute expression required");
8798 if (HAVE_32BIT_GPRS
)
8799 normalize_constant_expr (&imm2_expr
);
8803 case 'T': /* Coprocessor register. */
8804 /* +T is for disassembly only; never match. */
8807 case 't': /* Coprocessor register number. */
8808 if (s
[0] == '$' && ISDIGIT (s
[1]))
8818 while (ISDIGIT (*s
));
8820 as_bad (_("Invalid register number (%d)"), regno
);
8823 INSERT_OPERAND (RT
, *ip
, regno
);
8828 as_bad (_("Invalid coprocessor 0 register number"));
8832 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8833 *args
, insn
->name
, insn
->args
);
8834 /* Further processing is fruitless. */
8839 case '<': /* must be at least one digit */
8841 * According to the manual, if the shift amount is greater
8842 * than 31 or less than 0, then the shift amount should be
8843 * mod 32. In reality the mips assembler issues an error.
8844 * We issue a warning and mask out all but the low 5 bits.
8846 my_getExpression (&imm_expr
, s
);
8847 check_absolute_expr (ip
, &imm_expr
);
8848 if ((unsigned long) imm_expr
.X_add_number
> 31)
8849 as_warn (_("Improper shift amount (%lu)"),
8850 (unsigned long) imm_expr
.X_add_number
);
8851 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
);
8852 imm_expr
.X_op
= O_absent
;
8856 case '>': /* shift amount minus 32 */
8857 my_getExpression (&imm_expr
, s
);
8858 check_absolute_expr (ip
, &imm_expr
);
8859 if ((unsigned long) imm_expr
.X_add_number
< 32
8860 || (unsigned long) imm_expr
.X_add_number
> 63)
8862 INSERT_OPERAND (SHAMT
, *ip
, imm_expr
.X_add_number
- 32);
8863 imm_expr
.X_op
= O_absent
;
8867 case 'k': /* cache code */
8868 case 'h': /* prefx code */
8869 my_getExpression (&imm_expr
, s
);
8870 check_absolute_expr (ip
, &imm_expr
);
8871 if ((unsigned long) imm_expr
.X_add_number
> 31)
8872 as_warn (_("Invalid value for `%s' (%lu)"),
8874 (unsigned long) imm_expr
.X_add_number
);
8876 INSERT_OPERAND (CACHE
, *ip
, imm_expr
.X_add_number
);
8878 INSERT_OPERAND (PREFX
, *ip
, imm_expr
.X_add_number
);
8879 imm_expr
.X_op
= O_absent
;
8883 case 'c': /* break code */
8884 my_getExpression (&imm_expr
, s
);
8885 check_absolute_expr (ip
, &imm_expr
);
8886 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE
)
8887 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
8889 (unsigned long) imm_expr
.X_add_number
);
8890 INSERT_OPERAND (CODE
, *ip
, imm_expr
.X_add_number
);
8891 imm_expr
.X_op
= O_absent
;
8895 case 'q': /* lower break code */
8896 my_getExpression (&imm_expr
, s
);
8897 check_absolute_expr (ip
, &imm_expr
);
8898 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE2
)
8899 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
8901 (unsigned long) imm_expr
.X_add_number
);
8902 INSERT_OPERAND (CODE2
, *ip
, imm_expr
.X_add_number
);
8903 imm_expr
.X_op
= O_absent
;
8907 case 'B': /* 20-bit syscall/break code. */
8908 my_getExpression (&imm_expr
, s
);
8909 check_absolute_expr (ip
, &imm_expr
);
8910 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8911 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
8913 (unsigned long) imm_expr
.X_add_number
);
8914 INSERT_OPERAND (CODE20
, *ip
, imm_expr
.X_add_number
);
8915 imm_expr
.X_op
= O_absent
;
8919 case 'C': /* Coprocessor code */
8920 my_getExpression (&imm_expr
, s
);
8921 check_absolute_expr (ip
, &imm_expr
);
8922 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_COPZ
)
8924 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8925 (unsigned long) imm_expr
.X_add_number
);
8926 imm_expr
.X_add_number
&= OP_MASK_COPZ
;
8928 INSERT_OPERAND (COPZ
, *ip
, imm_expr
.X_add_number
);
8929 imm_expr
.X_op
= O_absent
;
8933 case 'J': /* 19-bit wait code. */
8934 my_getExpression (&imm_expr
, s
);
8935 check_absolute_expr (ip
, &imm_expr
);
8936 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8938 as_warn (_("Illegal 19-bit code (%lu)"),
8939 (unsigned long) imm_expr
.X_add_number
);
8940 imm_expr
.X_add_number
&= OP_MASK_CODE19
;
8942 INSERT_OPERAND (CODE19
, *ip
, imm_expr
.X_add_number
);
8943 imm_expr
.X_op
= O_absent
;
8947 case 'P': /* Performance register. */
8948 my_getExpression (&imm_expr
, s
);
8949 check_absolute_expr (ip
, &imm_expr
);
8950 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8951 as_warn (_("Invalid performance register (%lu)"),
8952 (unsigned long) imm_expr
.X_add_number
);
8953 INSERT_OPERAND (PERFREG
, *ip
, imm_expr
.X_add_number
);
8954 imm_expr
.X_op
= O_absent
;
8958 case 'G': /* Coprocessor destination register. */
8959 if (((ip
->insn_opcode
>> OP_SH_OP
) & OP_MASK_OP
) == OP_OP_COP0
)
8960 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_CP0
, ®no
);
8962 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
8963 INSERT_OPERAND (RD
, *ip
, regno
);
8972 case 'b': /* base register */
8973 case 'd': /* destination register */
8974 case 's': /* source register */
8975 case 't': /* target register */
8976 case 'r': /* both target and source */
8977 case 'v': /* both dest and source */
8978 case 'w': /* both dest and target */
8979 case 'E': /* coprocessor target register */
8980 case 'K': /* 'rdhwr' destination register */
8981 case 'x': /* ignore register name */
8982 case 'z': /* must be zero register */
8983 case 'U': /* destination register (clo/clz). */
8984 case 'g': /* coprocessor destination register */
8986 if (*args
== 'E' || *args
== 'K')
8987 ok
= reg_lookup (&s
, RTYPE_NUM
, ®no
);
8990 ok
= reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
);
8991 if (regno
== AT
&& ! mips_opts
.noat
)
8992 as_warn ("Used $at without \".set noat\"");
9001 if (c
== 'r' || c
== 'v' || c
== 'w')
9008 /* 'z' only matches $0. */
9009 if (c
== 'z' && regno
!= 0)
9012 /* Now that we have assembled one operand, we use the args string
9013 * to figure out where it goes in the instruction. */
9020 INSERT_OPERAND (RS
, *ip
, regno
);
9026 INSERT_OPERAND (RD
, *ip
, regno
);
9029 INSERT_OPERAND (RD
, *ip
, regno
);
9030 INSERT_OPERAND (RT
, *ip
, regno
);
9035 INSERT_OPERAND (RT
, *ip
, regno
);
9038 /* This case exists because on the r3000 trunc
9039 expands into a macro which requires a gp
9040 register. On the r6000 or r4000 it is
9041 assembled into a single instruction which
9042 ignores the register. Thus the insn version
9043 is MIPS_ISA2 and uses 'x', and the macro
9044 version is MIPS_ISA1 and uses 't'. */
9047 /* This case is for the div instruction, which
9048 acts differently if the destination argument
9049 is $0. This only matches $0, and is checked
9050 outside the switch. */
9053 /* Itbl operand; not yet implemented. FIXME ?? */
9055 /* What about all other operands like 'i', which
9056 can be specified in the opcode table? */
9065 INSERT_OPERAND (RS
, *ip
, lastregno
);
9068 INSERT_OPERAND (RT
, *ip
, lastregno
);
9073 case 'O': /* MDMX alignment immediate constant. */
9074 my_getExpression (&imm_expr
, s
);
9075 check_absolute_expr (ip
, &imm_expr
);
9076 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
9077 as_warn ("Improper align amount (%ld), using low bits",
9078 (long) imm_expr
.X_add_number
);
9079 INSERT_OPERAND (ALN
, *ip
, imm_expr
.X_add_number
);
9080 imm_expr
.X_op
= O_absent
;
9084 case 'Q': /* MDMX vector, element sel, or const. */
9087 /* MDMX Immediate. */
9088 my_getExpression (&imm_expr
, s
);
9089 check_absolute_expr (ip
, &imm_expr
);
9090 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
9091 as_warn (_("Invalid MDMX Immediate (%ld)"),
9092 (long) imm_expr
.X_add_number
);
9093 INSERT_OPERAND (FT
, *ip
, imm_expr
.X_add_number
);
9094 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9095 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
9097 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
9098 imm_expr
.X_op
= O_absent
;
9102 /* Not MDMX Immediate. Fall through. */
9103 case 'X': /* MDMX destination register. */
9104 case 'Y': /* MDMX source register. */
9105 case 'Z': /* MDMX target register. */
9107 case 'D': /* floating point destination register */
9108 case 'S': /* floating point source register */
9109 case 'T': /* floating point target register */
9110 case 'R': /* floating point source register */
9115 || (mips_opts
.ase_mdmx
9116 && (ip
->insn_mo
->pinfo
& FP_D
)
9117 && (ip
->insn_mo
->pinfo
& (INSN_COPROC_MOVE_DELAY
9118 | INSN_COPROC_MEMORY_DELAY
9119 | INSN_LOAD_COPROC_DELAY
9120 | INSN_LOAD_MEMORY_DELAY
9121 | INSN_STORE_MEMORY
))))
9124 if (reg_lookup (&s
, rtype
, ®no
))
9126 if ((regno
& 1) != 0
9128 && ! mips_oddfpreg_ok (ip
->insn_mo
, argnum
))
9129 as_warn (_("Float register should be even, was %d"),
9137 if (c
== 'V' || c
== 'W')
9148 INSERT_OPERAND (FD
, *ip
, regno
);
9153 INSERT_OPERAND (FS
, *ip
, regno
);
9156 /* This is like 'Z', but also needs to fix the MDMX
9157 vector/scalar select bits. Note that the
9158 scalar immediate case is handled above. */
9161 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
9162 int max_el
= (is_qh
? 3 : 7);
9164 my_getExpression(&imm_expr
, s
);
9165 check_absolute_expr (ip
, &imm_expr
);
9167 if (imm_expr
.X_add_number
> max_el
)
9168 as_bad(_("Bad element selector %ld"),
9169 (long) imm_expr
.X_add_number
);
9170 imm_expr
.X_add_number
&= max_el
;
9171 ip
->insn_opcode
|= (imm_expr
.X_add_number
9174 imm_expr
.X_op
= O_absent
;
9176 as_warn(_("Expecting ']' found '%s'"), s
);
9182 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
9183 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
9186 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
9193 INSERT_OPERAND (FT
, *ip
, regno
);
9196 INSERT_OPERAND (FR
, *ip
, regno
);
9206 INSERT_OPERAND (FS
, *ip
, lastregno
);
9209 INSERT_OPERAND (FT
, *ip
, lastregno
);
9215 my_getExpression (&imm_expr
, s
);
9216 if (imm_expr
.X_op
!= O_big
9217 && imm_expr
.X_op
!= O_constant
)
9218 insn_error
= _("absolute expression required");
9219 if (HAVE_32BIT_GPRS
)
9220 normalize_constant_expr (&imm_expr
);
9225 my_getExpression (&offset_expr
, s
);
9226 normalize_address_expr (&offset_expr
);
9227 *imm_reloc
= BFD_RELOC_32
;
9240 unsigned char temp
[8];
9242 unsigned int length
;
9247 /* These only appear as the last operand in an
9248 instruction, and every instruction that accepts
9249 them in any variant accepts them in all variants.
9250 This means we don't have to worry about backing out
9251 any changes if the instruction does not match.
9253 The difference between them is the size of the
9254 floating point constant and where it goes. For 'F'
9255 and 'L' the constant is 64 bits; for 'f' and 'l' it
9256 is 32 bits. Where the constant is placed is based
9257 on how the MIPS assembler does things:
9260 f -- immediate value
9263 The .lit4 and .lit8 sections are only used if
9264 permitted by the -G argument.
9266 The code below needs to know whether the target register
9267 is 32 or 64 bits wide. It relies on the fact 'f' and
9268 'F' are used with GPR-based instructions and 'l' and
9269 'L' are used with FPR-based instructions. */
9271 f64
= *args
== 'F' || *args
== 'L';
9272 using_gprs
= *args
== 'F' || *args
== 'f';
9274 save_in
= input_line_pointer
;
9275 input_line_pointer
= s
;
9276 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
9278 s
= input_line_pointer
;
9279 input_line_pointer
= save_in
;
9280 if (err
!= NULL
&& *err
!= '\0')
9282 as_bad (_("Bad floating point constant: %s"), err
);
9283 memset (temp
, '\0', sizeof temp
);
9284 length
= f64
? 8 : 4;
9287 assert (length
== (unsigned) (f64
? 8 : 4));
9291 && (g_switch_value
< 4
9292 || (temp
[0] == 0 && temp
[1] == 0)
9293 || (temp
[2] == 0 && temp
[3] == 0))))
9295 imm_expr
.X_op
= O_constant
;
9296 if (! target_big_endian
)
9297 imm_expr
.X_add_number
= bfd_getl32 (temp
);
9299 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9302 && ! mips_disable_float_construction
9303 /* Constants can only be constructed in GPRs and
9304 copied to FPRs if the GPRs are at least as wide
9305 as the FPRs. Force the constant into memory if
9306 we are using 64-bit FPRs but the GPRs are only
9309 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
9310 && ((temp
[0] == 0 && temp
[1] == 0)
9311 || (temp
[2] == 0 && temp
[3] == 0))
9312 && ((temp
[4] == 0 && temp
[5] == 0)
9313 || (temp
[6] == 0 && temp
[7] == 0)))
9315 /* The value is simple enough to load with a couple of
9316 instructions. If using 32-bit registers, set
9317 imm_expr to the high order 32 bits and offset_expr to
9318 the low order 32 bits. Otherwise, set imm_expr to
9319 the entire 64 bit constant. */
9320 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
9322 imm_expr
.X_op
= O_constant
;
9323 offset_expr
.X_op
= O_constant
;
9324 if (! target_big_endian
)
9326 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
9327 offset_expr
.X_add_number
= bfd_getl32 (temp
);
9331 imm_expr
.X_add_number
= bfd_getb32 (temp
);
9332 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
9334 if (offset_expr
.X_add_number
== 0)
9335 offset_expr
.X_op
= O_absent
;
9337 else if (sizeof (imm_expr
.X_add_number
) > 4)
9339 imm_expr
.X_op
= O_constant
;
9340 if (! target_big_endian
)
9341 imm_expr
.X_add_number
= bfd_getl64 (temp
);
9343 imm_expr
.X_add_number
= bfd_getb64 (temp
);
9347 imm_expr
.X_op
= O_big
;
9348 imm_expr
.X_add_number
= 4;
9349 if (! target_big_endian
)
9351 generic_bignum
[0] = bfd_getl16 (temp
);
9352 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
9353 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
9354 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
9358 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
9359 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
9360 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
9361 generic_bignum
[3] = bfd_getb16 (temp
);
9367 const char *newname
;
9370 /* Switch to the right section. */
9372 subseg
= now_subseg
;
9375 default: /* unused default case avoids warnings. */
9377 newname
= RDATA_SECTION_NAME
;
9378 if (g_switch_value
>= 8)
9382 newname
= RDATA_SECTION_NAME
;
9385 assert (g_switch_value
>= 4);
9389 new_seg
= subseg_new (newname
, (subsegT
) 0);
9390 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9391 bfd_set_section_flags (stdoutput
, new_seg
,
9396 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9397 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9398 && strcmp (TARGET_OS
, "elf") != 0)
9399 record_alignment (new_seg
, 4);
9401 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9403 as_bad (_("Can't use floating point insn in this section"));
9405 /* Set the argument to the current address in the
9407 offset_expr
.X_op
= O_symbol
;
9408 offset_expr
.X_add_symbol
=
9409 symbol_new ("L0\001", now_seg
,
9410 (valueT
) frag_now_fix (), frag_now
);
9411 offset_expr
.X_add_number
= 0;
9413 /* Put the floating point number into the section. */
9414 p
= frag_more ((int) length
);
9415 memcpy (p
, temp
, length
);
9417 /* Switch back to the original section. */
9418 subseg_set (seg
, subseg
);
9423 case 'i': /* 16 bit unsigned immediate */
9424 case 'j': /* 16 bit signed immediate */
9425 *imm_reloc
= BFD_RELOC_LO16
;
9426 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9429 offsetT minval
, maxval
;
9431 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9432 && strcmp (insn
->name
, insn
[1].name
) == 0);
9434 /* If the expression was written as an unsigned number,
9435 only treat it as signed if there are no more
9439 && sizeof (imm_expr
.X_add_number
) <= 4
9440 && imm_expr
.X_op
== O_constant
9441 && imm_expr
.X_add_number
< 0
9442 && imm_expr
.X_unsigned
9446 /* For compatibility with older assemblers, we accept
9447 0x8000-0xffff as signed 16-bit numbers when only
9448 signed numbers are allowed. */
9450 minval
= 0, maxval
= 0xffff;
9452 minval
= -0x8000, maxval
= 0x7fff;
9454 minval
= -0x8000, maxval
= 0xffff;
9456 if (imm_expr
.X_op
!= O_constant
9457 || imm_expr
.X_add_number
< minval
9458 || imm_expr
.X_add_number
> maxval
)
9462 if (imm_expr
.X_op
== O_constant
9463 || imm_expr
.X_op
== O_big
)
9464 as_bad (_("expression out of range"));
9470 case 'o': /* 16 bit offset */
9471 /* Check whether there is only a single bracketed expression
9472 left. If so, it must be the base register and the
9473 constant must be zero. */
9474 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9476 offset_expr
.X_op
= O_constant
;
9477 offset_expr
.X_add_number
= 0;
9481 /* If this value won't fit into a 16 bit offset, then go
9482 find a macro that will generate the 32 bit offset
9484 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9485 && (offset_expr
.X_op
!= O_constant
9486 || offset_expr
.X_add_number
>= 0x8000
9487 || offset_expr
.X_add_number
< -0x8000))
9493 case 'p': /* pc relative offset */
9494 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9495 my_getExpression (&offset_expr
, s
);
9499 case 'u': /* upper 16 bits */
9500 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9501 && imm_expr
.X_op
== O_constant
9502 && (imm_expr
.X_add_number
< 0
9503 || imm_expr
.X_add_number
>= 0x10000))
9504 as_bad (_("lui expression not in range 0..65535"));
9508 case 'a': /* 26 bit address */
9509 my_getExpression (&offset_expr
, s
);
9511 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9514 case 'N': /* 3 bit branch condition code */
9515 case 'M': /* 3 bit compare condition code */
9517 if (ip
->insn_mo
->pinfo
& (FP_D
| FP_S
))
9519 if (!reg_lookup (&s
, rtype
, ®no
))
9521 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9522 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9523 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9524 && (regno
& 1) != 0)
9525 as_warn(_("Condition code register should be even for %s, was %d"),
9527 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9528 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9529 && (regno
& 3) != 0)
9530 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9533 INSERT_OPERAND (BCC
, *ip
, regno
);
9535 INSERT_OPERAND (CCC
, *ip
, regno
);
9539 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9550 while (ISDIGIT (*s
));
9553 c
= 8; /* Invalid sel value. */
9556 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9557 ip
->insn_opcode
|= c
;
9561 /* Must be at least one digit. */
9562 my_getExpression (&imm_expr
, s
);
9563 check_absolute_expr (ip
, &imm_expr
);
9565 if ((unsigned long) imm_expr
.X_add_number
9566 > (unsigned long) OP_MASK_VECBYTE
)
9568 as_bad (_("bad byte vector index (%ld)"),
9569 (long) imm_expr
.X_add_number
);
9570 imm_expr
.X_add_number
= 0;
9573 INSERT_OPERAND (VECBYTE
, *ip
, imm_expr
.X_add_number
);
9574 imm_expr
.X_op
= O_absent
;
9579 my_getExpression (&imm_expr
, s
);
9580 check_absolute_expr (ip
, &imm_expr
);
9582 if ((unsigned long) imm_expr
.X_add_number
9583 > (unsigned long) OP_MASK_VECALIGN
)
9585 as_bad (_("bad byte vector index (%ld)"),
9586 (long) imm_expr
.X_add_number
);
9587 imm_expr
.X_add_number
= 0;
9590 INSERT_OPERAND (VECALIGN
, *ip
, imm_expr
.X_add_number
);
9591 imm_expr
.X_op
= O_absent
;
9596 as_bad (_("bad char = '%c'\n"), *args
);
9601 /* Args don't match. */
9602 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9603 !strcmp (insn
->name
, insn
[1].name
))
9607 insn_error
= _("illegal operands");
9612 insn_error
= _("illegal operands");
9617 #define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9619 /* This routine assembles an instruction into its binary format when
9620 assembling for the mips16. As a side effect, it sets one of the
9621 global variables imm_reloc or offset_reloc to the type of
9622 relocation to do if one of the operands is an address expression.
9623 It also sets mips16_small and mips16_ext if the user explicitly
9624 requested a small or extended instruction. */
9627 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9631 struct mips_opcode
*insn
;
9634 unsigned int lastregno
= 0;
9640 mips16_small
= FALSE
;
9643 for (s
= str
; ISLOWER (*s
); ++s
)
9655 if (s
[1] == 't' && s
[2] == ' ')
9658 mips16_small
= TRUE
;
9662 else if (s
[1] == 'e' && s
[2] == ' ')
9671 insn_error
= _("unknown opcode");
9675 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9676 mips16_small
= TRUE
;
9678 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9680 insn_error
= _("unrecognized opcode");
9689 assert (strcmp (insn
->name
, str
) == 0);
9691 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_opts
.arch
))
9698 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
]
9699 && strcmp (insn
->name
, insn
[1].name
) == 0)
9708 static char buf
[100];
9710 _("opcode not supported on this processor: %s (%s)"),
9711 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
9712 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
9719 create_insn (ip
, insn
);
9720 imm_expr
.X_op
= O_absent
;
9721 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9722 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9723 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9724 imm2_expr
.X_op
= O_absent
;
9725 offset_expr
.X_op
= O_absent
;
9726 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9727 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9728 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9729 for (args
= insn
->args
; 1; ++args
)
9736 /* In this switch statement we call break if we did not find
9737 a match, continue if we did find a match, or return if we
9746 /* Stuff the immediate value in now, if we can. */
9747 if (imm_expr
.X_op
== O_constant
9748 && *imm_reloc
> BFD_RELOC_UNUSED
9749 && insn
->pinfo
!= INSN_MACRO
)
9753 switch (*offset_reloc
)
9755 case BFD_RELOC_MIPS16_HI16_S
:
9756 tmp
= (imm_expr
.X_add_number
+ 0x8000) >> 16;
9759 case BFD_RELOC_MIPS16_HI16
:
9760 tmp
= imm_expr
.X_add_number
>> 16;
9763 case BFD_RELOC_MIPS16_LO16
:
9764 tmp
= ((imm_expr
.X_add_number
+ 0x8000) & 0xffff)
9768 case BFD_RELOC_UNUSED
:
9769 tmp
= imm_expr
.X_add_number
;
9775 *offset_reloc
= BFD_RELOC_UNUSED
;
9777 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9778 tmp
, TRUE
, mips16_small
,
9779 mips16_ext
, &ip
->insn_opcode
,
9780 &ip
->use_extend
, &ip
->extend
);
9781 imm_expr
.X_op
= O_absent
;
9782 *imm_reloc
= BFD_RELOC_UNUSED
;
9796 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9799 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9815 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9817 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9832 if (!reg_lookup (&s
, RTYPE_NUM
| RTYPE_GP
, ®no
))
9834 if (c
== 'v' || c
== 'w')
9837 MIPS16_INSERT_OPERAND (RX
, *ip
, lastregno
);
9839 MIPS16_INSERT_OPERAND (RY
, *ip
, lastregno
);
9850 if (c
== 'v' || c
== 'w')
9852 regno
= mips16_to_32_reg_map
[lastregno
];
9866 regno
= mips32_to_16_reg_map
[regno
];
9871 regno
= ILLEGAL_REG
;
9876 regno
= ILLEGAL_REG
;
9881 regno
= ILLEGAL_REG
;
9886 if (regno
== AT
&& ! mips_opts
.noat
)
9887 as_warn (_("used $at without \".set noat\""));
9894 if (regno
== ILLEGAL_REG
)
9901 MIPS16_INSERT_OPERAND (RX
, *ip
, regno
);
9905 MIPS16_INSERT_OPERAND (RY
, *ip
, regno
);
9908 MIPS16_INSERT_OPERAND (RZ
, *ip
, regno
);
9911 MIPS16_INSERT_OPERAND (MOVE32Z
, *ip
, regno
);
9917 MIPS16_INSERT_OPERAND (REGR32
, *ip
, regno
);
9920 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9921 MIPS16_INSERT_OPERAND (REG32R
, *ip
, regno
);
9931 if (strncmp (s
, "$pc", 3) == 0)
9948 i
= my_getSmallExpression (&imm_expr
, imm_reloc
, s
);
9951 if (imm_expr
.X_op
!= O_constant
)
9954 ip
->use_extend
= TRUE
;
9959 /* We need to relax this instruction. */
9960 *offset_reloc
= *imm_reloc
;
9961 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9966 *imm_reloc
= BFD_RELOC_UNUSED
;
9974 my_getExpression (&imm_expr
, s
);
9975 if (imm_expr
.X_op
== O_register
)
9977 /* What we thought was an expression turned out to
9980 if (s
[0] == '(' && args
[1] == '(')
9982 /* It looks like the expression was omitted
9983 before a register indirection, which means
9984 that the expression is implicitly zero. We
9985 still set up imm_expr, so that we handle
9986 explicit extensions correctly. */
9987 imm_expr
.X_op
= O_constant
;
9988 imm_expr
.X_add_number
= 0;
9989 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9996 /* We need to relax this instruction. */
9997 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10006 /* We use offset_reloc rather than imm_reloc for the PC
10007 relative operands. This lets macros with both
10008 immediate and address operands work correctly. */
10009 my_getExpression (&offset_expr
, s
);
10011 if (offset_expr
.X_op
== O_register
)
10014 /* We need to relax this instruction. */
10015 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
10019 case '6': /* break code */
10020 my_getExpression (&imm_expr
, s
);
10021 check_absolute_expr (ip
, &imm_expr
);
10022 if ((unsigned long) imm_expr
.X_add_number
> 63)
10023 as_warn (_("Invalid value for `%s' (%lu)"),
10025 (unsigned long) imm_expr
.X_add_number
);
10026 MIPS16_INSERT_OPERAND (IMM6
, *ip
, imm_expr
.X_add_number
);
10027 imm_expr
.X_op
= O_absent
;
10031 case 'a': /* 26 bit address */
10032 my_getExpression (&offset_expr
, s
);
10034 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
10035 ip
->insn_opcode
<<= 16;
10038 case 'l': /* register list for entry macro */
10039 case 'L': /* register list for exit macro */
10049 unsigned int freg
, reg1
, reg2
;
10051 while (*s
== ' ' || *s
== ',')
10053 if (reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10055 else if (reg_lookup (&s
, RTYPE_FPU
, ®1
))
10059 as_bad (_("can't parse register list"));
10069 if (!reg_lookup (&s
, freg
? RTYPE_FPU
10070 : (RTYPE_GP
| RTYPE_NUM
), ®2
))
10072 as_bad (_("invalid register list"));
10076 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
10078 mask
&= ~ (7 << 3);
10081 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
10083 mask
&= ~ (7 << 3);
10086 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
10087 mask
|= (reg2
- 3) << 3;
10088 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
10089 mask
|= (reg2
- 15) << 1;
10090 else if (reg1
== RA
&& reg2
== RA
)
10094 as_bad (_("invalid register list"));
10098 /* The mask is filled in in the opcode table for the
10099 benefit of the disassembler. We remove it before
10100 applying the actual mask. */
10101 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
10102 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
10106 case 'm': /* Register list for save insn. */
10107 case 'M': /* Register list for restore insn. */
10110 int framesz
= 0, seen_framesz
= 0;
10111 int args
= 0, statics
= 0, sregs
= 0;
10115 unsigned int reg1
, reg2
;
10117 SKIP_SPACE_TABS (s
);
10120 SKIP_SPACE_TABS (s
);
10122 my_getExpression (&imm_expr
, s
);
10123 if (imm_expr
.X_op
== O_constant
)
10125 /* Handle the frame size. */
10128 as_bad (_("more than one frame size in list"));
10132 framesz
= imm_expr
.X_add_number
;
10133 imm_expr
.X_op
= O_absent
;
10138 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®1
))
10140 as_bad (_("can't parse register list"));
10152 if (! reg_lookup (&s
, RTYPE_GP
| RTYPE_NUM
, ®2
)
10155 as_bad (_("can't parse register list"));
10160 while (reg1
<= reg2
)
10162 if (reg1
>= 4 && reg1
<= 7)
10164 if (c
== 'm' && !seen_framesz
)
10166 args
|= 1 << (reg1
- 4);
10168 /* statics $a0-$a3 */
10169 statics
|= 1 << (reg1
- 4);
10171 else if ((reg1
>= 16 && reg1
<= 23) || reg1
== 30)
10174 sregs
|= 1 << ((reg1
== 30) ? 8 : (reg1
- 16));
10176 else if (reg1
== 31)
10178 /* Add $ra to insn. */
10183 as_bad (_("unexpected register in list"));
10191 /* Encode args/statics combination. */
10192 if (args
& statics
)
10193 as_bad (_("arg/static registers overlap"));
10194 else if (args
== 0xf)
10195 /* All $a0-$a3 are args. */
10196 opcode
|= MIPS16_ALL_ARGS
<< 16;
10197 else if (statics
== 0xf)
10198 /* All $a0-$a3 are statics. */
10199 opcode
|= MIPS16_ALL_STATICS
<< 16;
10202 int narg
= 0, nstat
= 0;
10204 /* Count arg registers. */
10211 as_bad (_("invalid arg register list"));
10213 /* Count static registers. */
10214 while (statics
& 0x8)
10216 statics
= (statics
<< 1) & 0xf;
10220 as_bad (_("invalid static register list"));
10222 /* Encode args/statics. */
10223 opcode
|= ((narg
<< 2) | nstat
) << 16;
10226 /* Encode $s0/$s1. */
10227 if (sregs
& (1 << 0)) /* $s0 */
10229 if (sregs
& (1 << 1)) /* $s1 */
10235 /* Count regs $s2-$s8. */
10243 as_bad (_("invalid static register list"));
10244 /* Encode $s2-$s8. */
10245 opcode
|= nsreg
<< 24;
10248 /* Encode frame size. */
10250 as_bad (_("missing frame size"));
10251 else if ((framesz
& 7) != 0 || framesz
< 0
10252 || framesz
> 0xff * 8)
10253 as_bad (_("invalid frame size"));
10254 else if (framesz
!= 128 || (opcode
>> 16) != 0)
10257 opcode
|= (((framesz
& 0xf0) << 16)
10258 | (framesz
& 0x0f));
10261 /* Finally build the instruction. */
10262 if ((opcode
>> 16) != 0 || framesz
== 0)
10264 ip
->use_extend
= TRUE
;
10265 ip
->extend
= opcode
>> 16;
10267 ip
->insn_opcode
|= opcode
& 0x7f;
10271 case 'e': /* extend code */
10272 my_getExpression (&imm_expr
, s
);
10273 check_absolute_expr (ip
, &imm_expr
);
10274 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
10276 as_warn (_("Invalid value for `%s' (%lu)"),
10278 (unsigned long) imm_expr
.X_add_number
);
10279 imm_expr
.X_add_number
&= 0x7ff;
10281 ip
->insn_opcode
|= imm_expr
.X_add_number
;
10282 imm_expr
.X_op
= O_absent
;
10292 /* Args don't match. */
10293 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
10294 strcmp (insn
->name
, insn
[1].name
) == 0)
10301 insn_error
= _("illegal operands");
10307 /* This structure holds information we know about a mips16 immediate
10310 struct mips16_immed_operand
10312 /* The type code used in the argument string in the opcode table. */
10314 /* The number of bits in the short form of the opcode. */
10316 /* The number of bits in the extended form of the opcode. */
10318 /* The amount by which the short form is shifted when it is used;
10319 for example, the sw instruction has a shift count of 2. */
10321 /* The amount by which the short form is shifted when it is stored
10322 into the instruction code. */
10324 /* Non-zero if the short form is unsigned. */
10326 /* Non-zero if the extended form is unsigned. */
10328 /* Non-zero if the value is PC relative. */
10332 /* The mips16 immediate operand types. */
10334 static const struct mips16_immed_operand mips16_immed_operands
[] =
10336 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10337 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10338 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
10339 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
10340 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
10341 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10342 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10343 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10344 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
10345 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
10346 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10347 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10348 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
10349 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
10350 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10351 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
10352 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10353 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
10354 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
10355 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
10356 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
10359 #define MIPS16_NUM_IMMED \
10360 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
10362 /* Handle a mips16 instruction with an immediate value. This or's the
10363 small immediate value into *INSN. It sets *USE_EXTEND to indicate
10364 whether an extended value is needed; if one is needed, it sets
10365 *EXTEND to the value. The argument type is TYPE. The value is VAL.
10366 If SMALL is true, an unextended opcode was explicitly requested.
10367 If EXT is true, an extended opcode was explicitly requested. If
10368 WARN is true, warn if EXT does not match reality. */
10371 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
10372 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
10373 unsigned long *insn
, bfd_boolean
*use_extend
,
10374 unsigned short *extend
)
10376 register const struct mips16_immed_operand
*op
;
10377 int mintiny
, maxtiny
;
10378 bfd_boolean needext
;
10380 op
= mips16_immed_operands
;
10381 while (op
->type
!= type
)
10384 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10389 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10392 maxtiny
= 1 << op
->nbits
;
10397 maxtiny
= (1 << op
->nbits
) - 1;
10402 mintiny
= - (1 << (op
->nbits
- 1));
10403 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10406 /* Branch offsets have an implicit 0 in the lowest bit. */
10407 if (type
== 'p' || type
== 'q')
10410 if ((val
& ((1 << op
->shift
) - 1)) != 0
10411 || val
< (mintiny
<< op
->shift
)
10412 || val
> (maxtiny
<< op
->shift
))
10417 if (warn
&& ext
&& ! needext
)
10418 as_warn_where (file
, line
,
10419 _("extended operand requested but not required"));
10420 if (small
&& needext
)
10421 as_bad_where (file
, line
, _("invalid unextended operand value"));
10423 if (small
|| (! ext
&& ! needext
))
10427 *use_extend
= FALSE
;
10428 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
10429 insnval
<<= op
->op_shift
;
10434 long minext
, maxext
;
10440 maxext
= (1 << op
->extbits
) - 1;
10444 minext
= - (1 << (op
->extbits
- 1));
10445 maxext
= (1 << (op
->extbits
- 1)) - 1;
10447 if (val
< minext
|| val
> maxext
)
10448 as_bad_where (file
, line
,
10449 _("operand value out of range for instruction"));
10451 *use_extend
= TRUE
;
10452 if (op
->extbits
== 16)
10454 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
10457 else if (op
->extbits
== 15)
10459 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
10464 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
10468 *extend
= (unsigned short) extval
;
10473 struct percent_op_match
10476 bfd_reloc_code_real_type reloc
;
10479 static const struct percent_op_match mips_percent_op
[] =
10481 {"%lo", BFD_RELOC_LO16
},
10483 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
10484 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
10485 {"%call16", BFD_RELOC_MIPS_CALL16
},
10486 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
10487 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
10488 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
10489 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
10490 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
10491 {"%got", BFD_RELOC_MIPS_GOT16
},
10492 {"%gp_rel", BFD_RELOC_GPREL16
},
10493 {"%half", BFD_RELOC_16
},
10494 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
10495 {"%higher", BFD_RELOC_MIPS_HIGHER
},
10496 {"%neg", BFD_RELOC_MIPS_SUB
},
10497 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD
},
10498 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM
},
10499 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16
},
10500 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16
},
10501 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16
},
10502 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16
},
10503 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL
},
10505 {"%hi", BFD_RELOC_HI16_S
}
10508 static const struct percent_op_match mips16_percent_op
[] =
10510 {"%lo", BFD_RELOC_MIPS16_LO16
},
10511 {"%gprel", BFD_RELOC_MIPS16_GPREL
},
10512 {"%hi", BFD_RELOC_MIPS16_HI16_S
}
10516 /* Return true if *STR points to a relocation operator. When returning true,
10517 move *STR over the operator and store its relocation code in *RELOC.
10518 Leave both *STR and *RELOC alone when returning false. */
10521 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
10523 const struct percent_op_match
*percent_op
;
10526 if (mips_opts
.mips16
)
10528 percent_op
= mips16_percent_op
;
10529 limit
= ARRAY_SIZE (mips16_percent_op
);
10533 percent_op
= mips_percent_op
;
10534 limit
= ARRAY_SIZE (mips_percent_op
);
10537 for (i
= 0; i
< limit
; i
++)
10538 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
10540 int len
= strlen (percent_op
[i
].str
);
10542 if (!ISSPACE ((*str
)[len
]) && (*str
)[len
] != '(')
10545 *str
+= strlen (percent_op
[i
].str
);
10546 *reloc
= percent_op
[i
].reloc
;
10548 /* Check whether the output BFD supports this relocation.
10549 If not, issue an error and fall back on something safe. */
10550 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
10552 as_bad ("relocation %s isn't supported by the current ABI",
10553 percent_op
[i
].str
);
10554 *reloc
= BFD_RELOC_UNUSED
;
10562 /* Parse string STR as a 16-bit relocatable operand. Store the
10563 expression in *EP and the relocations in the array starting
10564 at RELOC. Return the number of relocation operators used.
10566 On exit, EXPR_END points to the first character after the expression. */
10569 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10572 bfd_reloc_code_real_type reversed_reloc
[3];
10573 size_t reloc_index
, i
;
10574 int crux_depth
, str_depth
;
10577 /* Search for the start of the main expression, recoding relocations
10578 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10579 of the main expression and with CRUX_DEPTH containing the number
10580 of open brackets at that point. */
10587 crux_depth
= str_depth
;
10589 /* Skip over whitespace and brackets, keeping count of the number
10591 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10596 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10597 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10599 my_getExpression (ep
, crux
);
10602 /* Match every open bracket. */
10603 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10607 if (crux_depth
> 0)
10608 as_bad ("unclosed '('");
10612 if (reloc_index
!= 0)
10614 prev_reloc_op_frag
= frag_now
;
10615 for (i
= 0; i
< reloc_index
; i
++)
10616 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10619 return reloc_index
;
10623 my_getExpression (expressionS
*ep
, char *str
)
10628 save_in
= input_line_pointer
;
10629 input_line_pointer
= str
;
10631 expr_end
= input_line_pointer
;
10632 input_line_pointer
= save_in
;
10634 /* If we are in mips16 mode, and this is an expression based on `.',
10635 then we bump the value of the symbol by 1 since that is how other
10636 text symbols are handled. We don't bother to handle complex
10637 expressions, just `.' plus or minus a constant. */
10638 if (mips_opts
.mips16
10639 && ep
->X_op
== O_symbol
10640 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10641 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10642 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10643 && symbol_constant_p (ep
->X_add_symbol
)
10644 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10645 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10648 /* Turn a string in input_line_pointer into a floating point constant
10649 of type TYPE, and store the appropriate bytes in *LITP. The number
10650 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10651 returned, or NULL on OK. */
10654 md_atof (int type
, char *litP
, int *sizeP
)
10657 LITTLENUM_TYPE words
[4];
10673 return _("bad call to md_atof");
10676 t
= atof_ieee (input_line_pointer
, type
, words
);
10678 input_line_pointer
= t
;
10682 if (! target_big_endian
)
10684 for (i
= prec
- 1; i
>= 0; i
--)
10686 md_number_to_chars (litP
, words
[i
], 2);
10692 for (i
= 0; i
< prec
; i
++)
10694 md_number_to_chars (litP
, words
[i
], 2);
10703 md_number_to_chars (char *buf
, valueT val
, int n
)
10705 if (target_big_endian
)
10706 number_to_chars_bigendian (buf
, val
, n
);
10708 number_to_chars_littleendian (buf
, val
, n
);
10712 static int support_64bit_objects(void)
10714 const char **list
, **l
;
10717 list
= bfd_target_list ();
10718 for (l
= list
; *l
!= NULL
; l
++)
10720 /* This is traditional mips */
10721 if (strcmp (*l
, "elf64-tradbigmips") == 0
10722 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10724 if (strcmp (*l
, "elf64-bigmips") == 0
10725 || strcmp (*l
, "elf64-littlemips") == 0)
10728 yes
= (*l
!= NULL
);
10732 #endif /* OBJ_ELF */
10734 const char *md_shortopts
= "O::g::G:";
10736 struct option md_longopts
[] =
10738 /* Options which specify architecture. */
10739 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10740 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10741 {"march", required_argument
, NULL
, OPTION_MARCH
},
10742 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10743 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10744 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10745 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10746 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10747 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10748 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10749 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10750 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10751 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10752 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10753 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10754 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10755 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10756 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10757 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10758 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10759 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10760 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10761 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10762 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10764 /* Options which specify Application Specific Extensions (ASEs). */
10765 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10766 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10767 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10768 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10769 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10770 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10771 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10772 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10773 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10774 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10775 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10776 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10777 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10778 #define OPTION_DSP (OPTION_ASE_BASE + 6)
10779 {"mdsp", no_argument
, NULL
, OPTION_DSP
},
10780 #define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10781 {"mno-dsp", no_argument
, NULL
, OPTION_NO_DSP
},
10782 #define OPTION_MT (OPTION_ASE_BASE + 8)
10783 {"mmt", no_argument
, NULL
, OPTION_MT
},
10784 #define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10785 {"mno-mt", no_argument
, NULL
, OPTION_NO_MT
},
10786 #define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
10787 {"msmartmips", no_argument
, NULL
, OPTION_SMARTMIPS
},
10788 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
10789 {"mno-smartmips", no_argument
, NULL
, OPTION_NO_SMARTMIPS
},
10791 /* Old-style architecture options. Don't add more of these. */
10792 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
10793 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10794 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10795 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10796 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10797 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10798 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10799 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10800 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10801 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10802 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10803 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10804 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10805 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10806 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10807 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10808 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10810 /* Options which enable bug fixes. */
10811 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10812 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10813 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10814 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10815 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10816 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10817 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10818 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10819 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10820 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10821 #define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10822 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10823 {"mfix-vr4130", no_argument
, NULL
, OPTION_FIX_VR4130
},
10824 {"mno-fix-vr4130", no_argument
, NULL
, OPTION_NO_FIX_VR4130
},
10826 /* Miscellaneous options. */
10827 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10828 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10829 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10830 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10831 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10832 {"break", no_argument
, NULL
, OPTION_BREAK
},
10833 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10834 #define OPTION_EB (OPTION_MISC_BASE + 2)
10835 {"EB", no_argument
, NULL
, OPTION_EB
},
10836 #define OPTION_EL (OPTION_MISC_BASE + 3)
10837 {"EL", no_argument
, NULL
, OPTION_EL
},
10838 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10839 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10840 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10841 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10842 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10843 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10844 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10845 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10846 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10847 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10848 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10849 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10850 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10851 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10852 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10853 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10854 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10855 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10856 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10857 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10858 #define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10859 #define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10860 {"msym32", no_argument
, NULL
, OPTION_MSYM32
},
10861 {"mno-sym32", no_argument
, NULL
, OPTION_MNO_SYM32
},
10863 /* ELF-specific options. */
10865 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10866 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10867 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10868 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10869 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10870 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10871 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10872 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10873 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10874 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10875 #define OPTION_32 (OPTION_ELF_BASE + 4)
10876 {"32", no_argument
, NULL
, OPTION_32
},
10877 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10878 {"n32", no_argument
, NULL
, OPTION_N32
},
10879 #define OPTION_64 (OPTION_ELF_BASE + 6)
10880 {"64", no_argument
, NULL
, OPTION_64
},
10881 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10882 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10883 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10884 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10885 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10886 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10887 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10888 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10889 #define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
10890 {"mvxworks-pic", no_argument
, NULL
, OPTION_MVXWORKS_PIC
},
10891 #endif /* OBJ_ELF */
10893 {NULL
, no_argument
, NULL
, 0}
10895 size_t md_longopts_size
= sizeof (md_longopts
);
10897 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10898 NEW_VALUE. Warn if another value was already specified. Note:
10899 we have to defer parsing the -march and -mtune arguments in order
10900 to handle 'from-abi' correctly, since the ABI might be specified
10901 in a later argument. */
10904 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10906 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10907 as_warn (_("A different %s was already specified, is now %s"),
10908 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10911 *string_ptr
= new_value
;
10915 md_parse_option (int c
, char *arg
)
10919 case OPTION_CONSTRUCT_FLOATS
:
10920 mips_disable_float_construction
= 0;
10923 case OPTION_NO_CONSTRUCT_FLOATS
:
10924 mips_disable_float_construction
= 1;
10936 target_big_endian
= 1;
10940 target_big_endian
= 0;
10944 if (arg
&& arg
[1] == '0')
10954 mips_debug
= atoi (arg
);
10955 /* When the MIPS assembler sees -g or -g2, it does not do
10956 optimizations which limit full symbolic debugging. We take
10957 that to be equivalent to -O0. */
10958 if (mips_debug
== 2)
10963 file_mips_isa
= ISA_MIPS1
;
10967 file_mips_isa
= ISA_MIPS2
;
10971 file_mips_isa
= ISA_MIPS3
;
10975 file_mips_isa
= ISA_MIPS4
;
10979 file_mips_isa
= ISA_MIPS5
;
10982 case OPTION_MIPS32
:
10983 file_mips_isa
= ISA_MIPS32
;
10986 case OPTION_MIPS32R2
:
10987 file_mips_isa
= ISA_MIPS32R2
;
10990 case OPTION_MIPS64R2
:
10991 file_mips_isa
= ISA_MIPS64R2
;
10994 case OPTION_MIPS64
:
10995 file_mips_isa
= ISA_MIPS64
;
10999 mips_set_option_string (&mips_tune_string
, arg
);
11003 mips_set_option_string (&mips_arch_string
, arg
);
11007 mips_set_option_string (&mips_arch_string
, "4650");
11008 mips_set_option_string (&mips_tune_string
, "4650");
11011 case OPTION_NO_M4650
:
11015 mips_set_option_string (&mips_arch_string
, "4010");
11016 mips_set_option_string (&mips_tune_string
, "4010");
11019 case OPTION_NO_M4010
:
11023 mips_set_option_string (&mips_arch_string
, "4100");
11024 mips_set_option_string (&mips_tune_string
, "4100");
11027 case OPTION_NO_M4100
:
11031 mips_set_option_string (&mips_arch_string
, "3900");
11032 mips_set_option_string (&mips_tune_string
, "3900");
11035 case OPTION_NO_M3900
:
11039 mips_opts
.ase_mdmx
= 1;
11042 case OPTION_NO_MDMX
:
11043 mips_opts
.ase_mdmx
= 0;
11047 mips_opts
.ase_dsp
= 1;
11050 case OPTION_NO_DSP
:
11051 mips_opts
.ase_dsp
= 0;
11055 mips_opts
.ase_mt
= 1;
11059 mips_opts
.ase_mt
= 0;
11062 case OPTION_MIPS16
:
11063 mips_opts
.mips16
= 1;
11064 mips_no_prev_insn ();
11067 case OPTION_NO_MIPS16
:
11068 mips_opts
.mips16
= 0;
11069 mips_no_prev_insn ();
11072 case OPTION_MIPS3D
:
11073 mips_opts
.ase_mips3d
= 1;
11076 case OPTION_NO_MIPS3D
:
11077 mips_opts
.ase_mips3d
= 0;
11080 case OPTION_SMARTMIPS
:
11081 mips_opts
.ase_smartmips
= 1;
11084 case OPTION_NO_SMARTMIPS
:
11085 mips_opts
.ase_smartmips
= 0;
11088 case OPTION_FIX_VR4120
:
11089 mips_fix_vr4120
= 1;
11092 case OPTION_NO_FIX_VR4120
:
11093 mips_fix_vr4120
= 0;
11096 case OPTION_FIX_VR4130
:
11097 mips_fix_vr4130
= 1;
11100 case OPTION_NO_FIX_VR4130
:
11101 mips_fix_vr4130
= 0;
11104 case OPTION_RELAX_BRANCH
:
11105 mips_relax_branch
= 1;
11108 case OPTION_NO_RELAX_BRANCH
:
11109 mips_relax_branch
= 0;
11112 case OPTION_MSHARED
:
11113 mips_in_shared
= TRUE
;
11116 case OPTION_MNO_SHARED
:
11117 mips_in_shared
= FALSE
;
11120 case OPTION_MSYM32
:
11121 mips_opts
.sym32
= TRUE
;
11124 case OPTION_MNO_SYM32
:
11125 mips_opts
.sym32
= FALSE
;
11129 /* When generating ELF code, we permit -KPIC and -call_shared to
11130 select SVR4_PIC, and -non_shared to select no PIC. This is
11131 intended to be compatible with Irix 5. */
11132 case OPTION_CALL_SHARED
:
11133 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11135 as_bad (_("-call_shared is supported only for ELF format"));
11138 mips_pic
= SVR4_PIC
;
11139 mips_abicalls
= TRUE
;
11142 case OPTION_NON_SHARED
:
11143 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11145 as_bad (_("-non_shared is supported only for ELF format"));
11149 mips_abicalls
= FALSE
;
11152 /* The -xgot option tells the assembler to use 32 bit offsets
11153 when accessing the got in SVR4_PIC mode. It is for Irix
11158 #endif /* OBJ_ELF */
11161 g_switch_value
= atoi (arg
);
11166 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11169 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11171 as_bad (_("-32 is supported for ELF format only"));
11174 mips_abi
= O32_ABI
;
11178 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11180 as_bad (_("-n32 is supported for ELF format only"));
11183 mips_abi
= N32_ABI
;
11187 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11189 as_bad (_("-64 is supported for ELF format only"));
11192 mips_abi
= N64_ABI
;
11193 if (! support_64bit_objects())
11194 as_fatal (_("No compiled in support for 64 bit object file format"));
11196 #endif /* OBJ_ELF */
11199 file_mips_gp32
= 1;
11203 file_mips_gp32
= 0;
11207 file_mips_fp32
= 1;
11211 file_mips_fp32
= 0;
11216 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11218 as_bad (_("-mabi is supported for ELF format only"));
11221 if (strcmp (arg
, "32") == 0)
11222 mips_abi
= O32_ABI
;
11223 else if (strcmp (arg
, "o64") == 0)
11224 mips_abi
= O64_ABI
;
11225 else if (strcmp (arg
, "n32") == 0)
11226 mips_abi
= N32_ABI
;
11227 else if (strcmp (arg
, "64") == 0)
11229 mips_abi
= N64_ABI
;
11230 if (! support_64bit_objects())
11231 as_fatal (_("No compiled in support for 64 bit object file "
11234 else if (strcmp (arg
, "eabi") == 0)
11235 mips_abi
= EABI_ABI
;
11238 as_fatal (_("invalid abi -mabi=%s"), arg
);
11242 #endif /* OBJ_ELF */
11244 case OPTION_M7000_HILO_FIX
:
11245 mips_7000_hilo_fix
= TRUE
;
11248 case OPTION_MNO_7000_HILO_FIX
:
11249 mips_7000_hilo_fix
= FALSE
;
11253 case OPTION_MDEBUG
:
11254 mips_flag_mdebug
= TRUE
;
11257 case OPTION_NO_MDEBUG
:
11258 mips_flag_mdebug
= FALSE
;
11262 mips_flag_pdr
= TRUE
;
11265 case OPTION_NO_PDR
:
11266 mips_flag_pdr
= FALSE
;
11269 case OPTION_MVXWORKS_PIC
:
11270 mips_pic
= VXWORKS_PIC
;
11272 #endif /* OBJ_ELF */
11281 /* Set up globals to generate code for the ISA or processor
11282 described by INFO. */
11285 mips_set_architecture (const struct mips_cpu_info
*info
)
11289 file_mips_arch
= info
->cpu
;
11290 mips_opts
.arch
= info
->cpu
;
11291 mips_opts
.isa
= info
->isa
;
11296 /* Likewise for tuning. */
11299 mips_set_tune (const struct mips_cpu_info
*info
)
11302 mips_tune
= info
->cpu
;
11307 mips_after_parse_args (void)
11309 const struct mips_cpu_info
*arch_info
= 0;
11310 const struct mips_cpu_info
*tune_info
= 0;
11312 /* GP relative stuff not working for PE */
11313 if (strncmp (TARGET_OS
, "pe", 2) == 0)
11315 if (g_switch_seen
&& g_switch_value
!= 0)
11316 as_bad (_("-G not supported in this configuration."));
11317 g_switch_value
= 0;
11320 if (mips_abi
== NO_ABI
)
11321 mips_abi
= MIPS_DEFAULT_ABI
;
11323 /* The following code determines the architecture and register size.
11324 Similar code was added to GCC 3.3 (see override_options() in
11325 config/mips/mips.c). The GAS and GCC code should be kept in sync
11326 as much as possible. */
11328 if (mips_arch_string
!= 0)
11329 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
11331 if (file_mips_isa
!= ISA_UNKNOWN
)
11333 /* Handle -mipsN. At this point, file_mips_isa contains the
11334 ISA level specified by -mipsN, while arch_info->isa contains
11335 the -march selection (if any). */
11336 if (arch_info
!= 0)
11338 /* -march takes precedence over -mipsN, since it is more descriptive.
11339 There's no harm in specifying both as long as the ISA levels
11341 if (file_mips_isa
!= arch_info
->isa
)
11342 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
11343 mips_cpu_info_from_isa (file_mips_isa
)->name
,
11344 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
11347 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
11350 if (arch_info
== 0)
11351 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
11353 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
11354 as_bad ("-march=%s is not compatible with the selected ABI",
11357 mips_set_architecture (arch_info
);
11359 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
11360 if (mips_tune_string
!= 0)
11361 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
11363 if (tune_info
== 0)
11364 mips_set_tune (arch_info
);
11366 mips_set_tune (tune_info
);
11368 if (file_mips_gp32
>= 0)
11370 /* The user specified the size of the integer registers. Make sure
11371 it agrees with the ABI and ISA. */
11372 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
11373 as_bad (_("-mgp64 used with a 32-bit processor"));
11374 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
11375 as_bad (_("-mgp32 used with a 64-bit ABI"));
11376 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
11377 as_bad (_("-mgp64 used with a 32-bit ABI"));
11381 /* Infer the integer register size from the ABI and processor.
11382 Restrict ourselves to 32-bit registers if that's all the
11383 processor has, or if the ABI cannot handle 64-bit registers. */
11384 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
11385 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
11388 switch (file_mips_fp32
)
11392 /* No user specified float register size.
11393 ??? GAS treats single-float processors as though they had 64-bit
11394 float registers (although it complains when double-precision
11395 instructions are used). As things stand, saying they have 32-bit
11396 registers would lead to spurious "register must be even" messages.
11397 So here we assume float registers are never smaller than the
11399 if (file_mips_gp32
== 0)
11400 /* 64-bit integer registers implies 64-bit float registers. */
11401 file_mips_fp32
= 0;
11402 else if ((mips_opts
.ase_mips3d
> 0 || mips_opts
.ase_mdmx
> 0)
11403 && ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11404 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11405 file_mips_fp32
= 0;
11407 /* 32-bit float registers. */
11408 file_mips_fp32
= 1;
11411 /* The user specified the size of the float registers. Check if it
11412 agrees with the ABI and ISA. */
11414 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
11415 as_bad (_("-mfp64 used with a 32-bit fpu"));
11416 else if (ABI_NEEDS_32BIT_REGS (mips_abi
)
11417 && !ISA_HAS_MXHC1 (mips_opts
.isa
))
11418 as_warn (_("-mfp64 used with a 32-bit ABI"));
11421 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
11422 as_warn (_("-mfp32 used with a 64-bit ABI"));
11426 /* End of GCC-shared inference code. */
11428 /* This flag is set when we have a 64-bit capable CPU but use only
11429 32-bit wide registers. Note that EABI does not use it. */
11430 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
11431 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
11432 || mips_abi
== O32_ABI
))
11433 mips_32bitmode
= 1;
11435 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
11436 as_bad (_("trap exception not supported at ISA 1"));
11438 /* If the selected architecture includes support for ASEs, enable
11439 generation of code for them. */
11440 if (mips_opts
.mips16
== -1)
11441 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
11442 if (mips_opts
.ase_mips3d
== -1)
11443 mips_opts
.ase_mips3d
= ((arch_info
->flags
& MIPS_CPU_ASE_MIPS3D
)
11444 && file_mips_fp32
== 0) ? 1 : 0;
11445 if (mips_opts
.ase_mips3d
&& file_mips_fp32
== 1)
11446 as_bad (_("-mfp32 used with -mips3d"));
11448 if (mips_opts
.ase_mdmx
== -1)
11449 mips_opts
.ase_mdmx
= ((arch_info
->flags
& MIPS_CPU_ASE_MDMX
)
11450 && file_mips_fp32
== 0) ? 1 : 0;
11451 if (mips_opts
.ase_mdmx
&& file_mips_fp32
== 1)
11452 as_bad (_("-mfp32 used with -mdmx"));
11454 if (mips_opts
.ase_smartmips
== -1)
11455 mips_opts
.ase_smartmips
= (arch_info
->flags
& MIPS_CPU_ASE_SMARTMIPS
) ? 1 : 0;
11456 if (mips_opts
.ase_smartmips
&& !ISA_SUPPORTS_SMARTMIPS
)
11457 as_warn ("%s ISA does not support SmartMIPS",
11458 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11460 if (mips_opts
.ase_dsp
== -1)
11461 mips_opts
.ase_dsp
= (arch_info
->flags
& MIPS_CPU_ASE_DSP
) ? 1 : 0;
11462 if (mips_opts
.ase_dsp
&& !ISA_SUPPORTS_DSP_ASE
)
11463 as_warn ("%s ISA does not support DSP ASE",
11464 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11466 if (mips_opts
.ase_mt
== -1)
11467 mips_opts
.ase_mt
= (arch_info
->flags
& MIPS_CPU_ASE_MT
) ? 1 : 0;
11468 if (mips_opts
.ase_mt
&& !ISA_SUPPORTS_MT_ASE
)
11469 as_warn ("%s ISA does not support MT ASE",
11470 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
11472 file_mips_isa
= mips_opts
.isa
;
11473 file_ase_mips16
= mips_opts
.mips16
;
11474 file_ase_mips3d
= mips_opts
.ase_mips3d
;
11475 file_ase_mdmx
= mips_opts
.ase_mdmx
;
11476 file_ase_smartmips
= mips_opts
.ase_smartmips
;
11477 file_ase_dsp
= mips_opts
.ase_dsp
;
11478 file_ase_mt
= mips_opts
.ase_mt
;
11479 mips_opts
.gp32
= file_mips_gp32
;
11480 mips_opts
.fp32
= file_mips_fp32
;
11482 if (mips_flag_mdebug
< 0)
11484 #ifdef OBJ_MAYBE_ECOFF
11485 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
11486 mips_flag_mdebug
= 1;
11488 #endif /* OBJ_MAYBE_ECOFF */
11489 mips_flag_mdebug
= 0;
11494 mips_init_after_args (void)
11496 /* initialize opcodes */
11497 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
11498 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
11502 md_pcrel_from (fixS
*fixP
)
11504 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
11505 switch (fixP
->fx_r_type
)
11507 case BFD_RELOC_16_PCREL_S2
:
11508 case BFD_RELOC_MIPS_JMP
:
11509 /* Return the address of the delay slot. */
11516 /* This is called before the symbol table is processed. In order to
11517 work with gcc when using mips-tfile, we must keep all local labels.
11518 However, in other cases, we want to discard them. If we were
11519 called with -g, but we didn't see any debugging information, it may
11520 mean that gcc is smuggling debugging information through to
11521 mips-tfile, in which case we must generate all local labels. */
11524 mips_frob_file_before_adjust (void)
11526 #ifndef NO_ECOFF_DEBUGGING
11527 if (ECOFF_DEBUGGING
11529 && ! ecoff_debugging_seen
)
11530 flag_keep_locals
= 1;
11534 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11535 the corresponding LO16 reloc. This is called before md_apply_fix and
11536 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11537 relocation operators.
11539 For our purposes, a %lo() expression matches a %got() or %hi()
11542 (a) it refers to the same symbol; and
11543 (b) the offset applied in the %lo() expression is no lower than
11544 the offset applied in the %got() or %hi().
11546 (b) allows us to cope with code like:
11549 lh $4,%lo(foo+2)($4)
11551 ...which is legal on RELA targets, and has a well-defined behaviour
11552 if the user knows that adding 2 to "foo" will not induce a carry to
11555 When several %lo()s match a particular %got() or %hi(), we use the
11556 following rules to distinguish them:
11558 (1) %lo()s with smaller offsets are a better match than %lo()s with
11561 (2) %lo()s with no matching %got() or %hi() are better than those
11562 that already have a matching %got() or %hi().
11564 (3) later %lo()s are better than earlier %lo()s.
11566 These rules are applied in order.
11568 (1) means, among other things, that %lo()s with identical offsets are
11569 chosen if they exist.
11571 (2) means that we won't associate several high-part relocations with
11572 the same low-part relocation unless there's no alternative. Having
11573 several high parts for the same low part is a GNU extension; this rule
11574 allows careful users to avoid it.
11576 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11577 with the last high-part relocation being at the front of the list.
11578 It therefore makes sense to choose the last matching low-part
11579 relocation, all other things being equal. It's also easier
11580 to code that way. */
11583 mips_frob_file (void)
11585 struct mips_hi_fixup
*l
;
11587 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
11589 segment_info_type
*seginfo
;
11590 bfd_boolean matched_lo_p
;
11591 fixS
**hi_pos
, **lo_pos
, **pos
;
11593 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
11595 /* If a GOT16 relocation turns out to be against a global symbol,
11596 there isn't supposed to be a matching LO. */
11597 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11598 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
11601 /* Check quickly whether the next fixup happens to be a matching %lo. */
11602 if (fixup_has_matching_lo_p (l
->fixp
))
11605 seginfo
= seg_info (l
->seg
);
11607 /* Set HI_POS to the position of this relocation in the chain.
11608 Set LO_POS to the position of the chosen low-part relocation.
11609 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11610 relocation that matches an immediately-preceding high-part
11614 matched_lo_p
= FALSE
;
11615 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
11617 if (*pos
== l
->fixp
)
11620 if (((*pos
)->fx_r_type
== BFD_RELOC_LO16
11621 || (*pos
)->fx_r_type
== BFD_RELOC_MIPS16_LO16
)
11622 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
11623 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
11625 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
11627 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
11630 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
11631 && fixup_has_matching_lo_p (*pos
));
11634 /* If we found a match, remove the high-part relocation from its
11635 current position and insert it before the low-part relocation.
11636 Make the offsets match so that fixup_has_matching_lo_p()
11639 We don't warn about unmatched high-part relocations since some
11640 versions of gcc have been known to emit dead "lui ...%hi(...)"
11642 if (lo_pos
!= NULL
)
11644 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
11645 if (l
->fixp
->fx_next
!= *lo_pos
)
11647 *hi_pos
= l
->fixp
->fx_next
;
11648 l
->fixp
->fx_next
= *lo_pos
;
11655 /* We may have combined relocations without symbols in the N32/N64 ABI.
11656 We have to prevent gas from dropping them. */
11659 mips_force_relocation (fixS
*fixp
)
11661 if (generic_force_reloc (fixp
))
11665 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
11666 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
11667 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
11668 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
11674 /* Apply a fixup to the object file. */
11677 md_apply_fix (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11681 reloc_howto_type
*howto
;
11683 /* We ignore generic BFD relocations we don't know about. */
11684 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11688 assert (fixP
->fx_size
== 4
11689 || fixP
->fx_r_type
== BFD_RELOC_16
11690 || fixP
->fx_r_type
== BFD_RELOC_64
11691 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11692 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11693 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11694 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11696 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11698 assert (! fixP
->fx_pcrel
|| fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
11700 /* Don't treat parts of a composite relocation as done. There are two
11703 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11704 should nevertheless be emitted if the first part is.
11706 (2) In normal usage, composite relocations are never assembly-time
11707 constants. The easiest way of dealing with the pathological
11708 exceptions is to generate a relocation against STN_UNDEF and
11709 leave everything up to the linker. */
11710 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
&& fixP
->fx_tcbit
== 0)
11713 switch (fixP
->fx_r_type
)
11715 case BFD_RELOC_MIPS_TLS_GD
:
11716 case BFD_RELOC_MIPS_TLS_LDM
:
11717 case BFD_RELOC_MIPS_TLS_DTPREL_HI16
:
11718 case BFD_RELOC_MIPS_TLS_DTPREL_LO16
:
11719 case BFD_RELOC_MIPS_TLS_GOTTPREL
:
11720 case BFD_RELOC_MIPS_TLS_TPREL_HI16
:
11721 case BFD_RELOC_MIPS_TLS_TPREL_LO16
:
11722 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
11725 case BFD_RELOC_MIPS_JMP
:
11726 case BFD_RELOC_MIPS_SHIFT5
:
11727 case BFD_RELOC_MIPS_SHIFT6
:
11728 case BFD_RELOC_MIPS_GOT_DISP
:
11729 case BFD_RELOC_MIPS_GOT_PAGE
:
11730 case BFD_RELOC_MIPS_GOT_OFST
:
11731 case BFD_RELOC_MIPS_SUB
:
11732 case BFD_RELOC_MIPS_INSERT_A
:
11733 case BFD_RELOC_MIPS_INSERT_B
:
11734 case BFD_RELOC_MIPS_DELETE
:
11735 case BFD_RELOC_MIPS_HIGHEST
:
11736 case BFD_RELOC_MIPS_HIGHER
:
11737 case BFD_RELOC_MIPS_SCN_DISP
:
11738 case BFD_RELOC_MIPS_REL16
:
11739 case BFD_RELOC_MIPS_RELGOT
:
11740 case BFD_RELOC_MIPS_JALR
:
11741 case BFD_RELOC_HI16
:
11742 case BFD_RELOC_HI16_S
:
11743 case BFD_RELOC_GPREL16
:
11744 case BFD_RELOC_MIPS_LITERAL
:
11745 case BFD_RELOC_MIPS_CALL16
:
11746 case BFD_RELOC_MIPS_GOT16
:
11747 case BFD_RELOC_GPREL32
:
11748 case BFD_RELOC_MIPS_GOT_HI16
:
11749 case BFD_RELOC_MIPS_GOT_LO16
:
11750 case BFD_RELOC_MIPS_CALL_HI16
:
11751 case BFD_RELOC_MIPS_CALL_LO16
:
11752 case BFD_RELOC_MIPS16_GPREL
:
11753 case BFD_RELOC_MIPS16_HI16
:
11754 case BFD_RELOC_MIPS16_HI16_S
:
11755 /* Nothing needed to do. The value comes from the reloc entry */
11758 case BFD_RELOC_MIPS16_JMP
:
11759 /* We currently always generate a reloc against a symbol, which
11760 means that we don't want an addend even if the symbol is
11766 /* This is handled like BFD_RELOC_32, but we output a sign
11767 extended value if we are only 32 bits. */
11770 if (8 <= sizeof (valueT
))
11771 md_number_to_chars ((char *) buf
, *valP
, 8);
11776 if ((*valP
& 0x80000000) != 0)
11780 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 4 : 0)),
11782 md_number_to_chars ((char *)(buf
+ (target_big_endian
? 0 : 4)),
11788 case BFD_RELOC_RVA
:
11790 /* If we are deleting this reloc entry, we must fill in the
11791 value now. This can happen if we have a .word which is not
11792 resolved when it appears but is later defined. */
11794 md_number_to_chars ((char *) buf
, *valP
, 4);
11798 /* If we are deleting this reloc entry, we must fill in the
11801 md_number_to_chars ((char *) buf
, *valP
, 2);
11804 case BFD_RELOC_LO16
:
11805 case BFD_RELOC_MIPS16_LO16
:
11806 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11807 may be safe to remove, but if so it's not obvious. */
11808 /* When handling an embedded PIC switch statement, we can wind
11809 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11812 if (*valP
+ 0x8000 > 0xffff)
11813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11814 _("relocation overflow"));
11815 if (target_big_endian
)
11817 md_number_to_chars ((char *) buf
, *valP
, 2);
11821 case BFD_RELOC_16_PCREL_S2
:
11822 if ((*valP
& 0x3) != 0)
11823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11824 _("Branch to misaligned address (%lx)"), (long) *valP
);
11827 * We need to save the bits in the instruction since fixup_segment()
11828 * might be deleting the relocation entry (i.e., a branch within
11829 * the current segment).
11831 if (! fixP
->fx_done
)
11834 /* update old instruction data */
11835 if (target_big_endian
)
11836 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11838 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11840 if (*valP
+ 0x20000 <= 0x3ffff)
11842 insn
|= (*valP
>> 2) & 0xffff;
11843 md_number_to_chars ((char *) buf
, insn
, 4);
11845 else if (mips_pic
== NO_PIC
11847 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11848 && (fixP
->fx_frag
->fr_address
11849 < text_section
->vma
+ bfd_get_section_size (text_section
))
11850 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11851 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11852 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11854 /* The branch offset is too large. If this is an
11855 unconditional branch, and we are not generating PIC code,
11856 we can convert it to an absolute jump instruction. */
11857 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11858 insn
= 0x0c000000; /* jal */
11860 insn
= 0x08000000; /* j */
11861 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11863 fixP
->fx_addsy
= section_symbol (text_section
);
11864 *valP
+= md_pcrel_from (fixP
);
11865 md_number_to_chars ((char *) buf
, insn
, 4);
11869 /* If we got here, we have branch-relaxation disabled,
11870 and there's nothing we can do to fix this instruction
11871 without turning it into a longer sequence. */
11872 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11873 _("Branch out of range"));
11877 case BFD_RELOC_VTABLE_INHERIT
:
11880 && !S_IS_DEFINED (fixP
->fx_addsy
)
11881 && !S_IS_WEAK (fixP
->fx_addsy
))
11882 S_SET_WEAK (fixP
->fx_addsy
);
11885 case BFD_RELOC_VTABLE_ENTRY
:
11893 /* Remember value for tc_gen_reloc. */
11894 fixP
->fx_addnumber
= *valP
;
11904 name
= input_line_pointer
;
11905 c
= get_symbol_end ();
11906 p
= (symbolS
*) symbol_find_or_make (name
);
11907 *input_line_pointer
= c
;
11911 /* Align the current frag to a given power of two. The MIPS assembler
11912 also automatically adjusts any preceding label. */
11915 mips_align (int to
, int fill
, symbolS
*label
)
11917 mips_emit_delays ();
11918 frag_align (to
, fill
, 0);
11919 record_alignment (now_seg
, to
);
11922 assert (S_GET_SEGMENT (label
) == now_seg
);
11923 symbol_set_frag (label
, frag_now
);
11924 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11928 /* Align to a given power of two. .align 0 turns off the automatic
11929 alignment used by the data creating pseudo-ops. */
11932 s_align (int x ATTRIBUTE_UNUSED
)
11935 register long temp_fill
;
11936 long max_alignment
= 15;
11940 o Note that the assembler pulls down any immediately preceding label
11941 to the aligned address.
11942 o It's not documented but auto alignment is reinstated by
11943 a .align pseudo instruction.
11944 o Note also that after auto alignment is turned off the mips assembler
11945 issues an error on attempt to assemble an improperly aligned data item.
11950 temp
= get_absolute_expression ();
11951 if (temp
> max_alignment
)
11952 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11955 as_warn (_("Alignment negative: 0 assumed."));
11958 if (*input_line_pointer
== ',')
11960 ++input_line_pointer
;
11961 temp_fill
= get_absolute_expression ();
11968 mips_align (temp
, (int) temp_fill
,
11969 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11976 demand_empty_rest_of_line ();
11980 s_change_sec (int sec
)
11985 /* The ELF backend needs to know that we are changing sections, so
11986 that .previous works correctly. We could do something like check
11987 for an obj_section_change_hook macro, but that might be confusing
11988 as it would not be appropriate to use it in the section changing
11989 functions in read.c, since obj-elf.c intercepts those. FIXME:
11990 This should be cleaner, somehow. */
11991 obj_elf_section_change_hook ();
11994 mips_emit_delays ();
12004 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
12005 demand_empty_rest_of_line ();
12009 seg
= subseg_new (RDATA_SECTION_NAME
,
12010 (subsegT
) get_absolute_expression ());
12011 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12013 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
12014 | SEC_READONLY
| SEC_RELOC
12016 if (strcmp (TARGET_OS
, "elf") != 0)
12017 record_alignment (seg
, 4);
12019 demand_empty_rest_of_line ();
12023 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
12024 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12026 bfd_set_section_flags (stdoutput
, seg
,
12027 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
12028 if (strcmp (TARGET_OS
, "elf") != 0)
12029 record_alignment (seg
, 4);
12031 demand_empty_rest_of_line ();
12039 s_change_section (int ignore ATTRIBUTE_UNUSED
)
12042 char *section_name
;
12047 int section_entry_size
;
12048 int section_alignment
;
12050 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
12053 section_name
= input_line_pointer
;
12054 c
= get_symbol_end ();
12056 next_c
= *(input_line_pointer
+ 1);
12058 /* Do we have .section Name<,"flags">? */
12059 if (c
!= ',' || (c
== ',' && next_c
== '"'))
12061 /* just after name is now '\0'. */
12062 *input_line_pointer
= c
;
12063 input_line_pointer
= section_name
;
12064 obj_elf_section (ignore
);
12067 input_line_pointer
++;
12069 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
12071 section_type
= get_absolute_expression ();
12074 if (*input_line_pointer
++ == ',')
12075 section_flag
= get_absolute_expression ();
12078 if (*input_line_pointer
++ == ',')
12079 section_entry_size
= get_absolute_expression ();
12081 section_entry_size
= 0;
12082 if (*input_line_pointer
++ == ',')
12083 section_alignment
= get_absolute_expression ();
12085 section_alignment
= 0;
12087 section_name
= xstrdup (section_name
);
12089 /* When using the generic form of .section (as implemented by obj-elf.c),
12090 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12091 traditionally had to fall back on the more common @progbits instead.
12093 There's nothing really harmful in this, since bfd will correct
12094 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12095 means that, for backwards compatibility, the special_section entries
12096 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12098 Even so, we shouldn't force users of the MIPS .section syntax to
12099 incorrectly label the sections as SHT_PROGBITS. The best compromise
12100 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12101 generic type-checking code. */
12102 if (section_type
== SHT_MIPS_DWARF
)
12103 section_type
= SHT_PROGBITS
;
12105 obj_elf_change_section (section_name
, section_type
, section_flag
,
12106 section_entry_size
, 0, 0, 0);
12108 if (now_seg
->name
!= section_name
)
12109 free (section_name
);
12110 #endif /* OBJ_ELF */
12114 mips_enable_auto_align (void)
12120 s_cons (int log_size
)
12124 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12125 mips_emit_delays ();
12126 if (log_size
> 0 && auto_align
)
12127 mips_align (log_size
, 0, label
);
12128 mips_clear_insn_labels ();
12129 cons (1 << log_size
);
12133 s_float_cons (int type
)
12137 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12139 mips_emit_delays ();
12144 mips_align (3, 0, label
);
12146 mips_align (2, 0, label
);
12149 mips_clear_insn_labels ();
12154 /* Handle .globl. We need to override it because on Irix 5 you are
12157 where foo is an undefined symbol, to mean that foo should be
12158 considered to be the address of a function. */
12161 s_mips_globl (int x ATTRIBUTE_UNUSED
)
12170 name
= input_line_pointer
;
12171 c
= get_symbol_end ();
12172 symbolP
= symbol_find_or_make (name
);
12173 S_SET_EXTERNAL (symbolP
);
12175 *input_line_pointer
= c
;
12176 SKIP_WHITESPACE ();
12178 /* On Irix 5, every global symbol that is not explicitly labelled as
12179 being a function is apparently labelled as being an object. */
12182 if (!is_end_of_line
[(unsigned char) *input_line_pointer
]
12183 && (*input_line_pointer
!= ','))
12188 secname
= input_line_pointer
;
12189 c
= get_symbol_end ();
12190 sec
= bfd_get_section_by_name (stdoutput
, secname
);
12192 as_bad (_("%s: no such section"), secname
);
12193 *input_line_pointer
= c
;
12195 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
12196 flag
= BSF_FUNCTION
;
12199 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
12201 c
= *input_line_pointer
;
12204 input_line_pointer
++;
12205 SKIP_WHITESPACE ();
12206 if (is_end_of_line
[(unsigned char) *input_line_pointer
])
12212 demand_empty_rest_of_line ();
12216 s_option (int x ATTRIBUTE_UNUSED
)
12221 opt
= input_line_pointer
;
12222 c
= get_symbol_end ();
12226 /* FIXME: What does this mean? */
12228 else if (strncmp (opt
, "pic", 3) == 0)
12232 i
= atoi (opt
+ 3);
12237 mips_pic
= SVR4_PIC
;
12238 mips_abicalls
= TRUE
;
12241 as_bad (_(".option pic%d not supported"), i
);
12243 if (mips_pic
== SVR4_PIC
)
12245 if (g_switch_seen
&& g_switch_value
!= 0)
12246 as_warn (_("-G may not be used with SVR4 PIC code"));
12247 g_switch_value
= 0;
12248 bfd_set_gp_size (stdoutput
, 0);
12252 as_warn (_("Unrecognized option \"%s\""), opt
);
12254 *input_line_pointer
= c
;
12255 demand_empty_rest_of_line ();
12258 /* This structure is used to hold a stack of .set values. */
12260 struct mips_option_stack
12262 struct mips_option_stack
*next
;
12263 struct mips_set_options options
;
12266 static struct mips_option_stack
*mips_opts_stack
;
12268 /* Handle the .set pseudo-op. */
12271 s_mipsset (int x ATTRIBUTE_UNUSED
)
12273 char *name
= input_line_pointer
, ch
;
12275 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
12276 ++input_line_pointer
;
12277 ch
= *input_line_pointer
;
12278 *input_line_pointer
= '\0';
12280 if (strcmp (name
, "reorder") == 0)
12282 if (mips_opts
.noreorder
)
12285 else if (strcmp (name
, "noreorder") == 0)
12287 if (!mips_opts
.noreorder
)
12288 start_noreorder ();
12290 else if (strcmp (name
, "at") == 0)
12292 mips_opts
.noat
= 0;
12294 else if (strcmp (name
, "noat") == 0)
12296 mips_opts
.noat
= 1;
12298 else if (strcmp (name
, "macro") == 0)
12300 mips_opts
.warn_about_macros
= 0;
12302 else if (strcmp (name
, "nomacro") == 0)
12304 if (mips_opts
.noreorder
== 0)
12305 as_bad (_("`noreorder' must be set before `nomacro'"));
12306 mips_opts
.warn_about_macros
= 1;
12308 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
12310 mips_opts
.nomove
= 0;
12312 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
12314 mips_opts
.nomove
= 1;
12316 else if (strcmp (name
, "bopt") == 0)
12318 mips_opts
.nobopt
= 0;
12320 else if (strcmp (name
, "nobopt") == 0)
12322 mips_opts
.nobopt
= 1;
12324 else if (strcmp (name
, "gp=default") == 0)
12325 mips_opts
.gp32
= file_mips_gp32
;
12326 else if (strcmp (name
, "gp=32") == 0)
12327 mips_opts
.gp32
= 1;
12328 else if (strcmp (name
, "gp=64") == 0)
12330 if (!ISA_HAS_64BIT_REGS (mips_opts
.isa
))
12331 as_warn ("%s isa does not support 64-bit registers",
12332 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12333 mips_opts
.gp32
= 0;
12335 else if (strcmp (name
, "fp=default") == 0)
12336 mips_opts
.fp32
= file_mips_fp32
;
12337 else if (strcmp (name
, "fp=32") == 0)
12338 mips_opts
.fp32
= 1;
12339 else if (strcmp (name
, "fp=64") == 0)
12341 if (!ISA_HAS_64BIT_FPRS (mips_opts
.isa
))
12342 as_warn ("%s isa does not support 64-bit floating point registers",
12343 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12344 mips_opts
.fp32
= 0;
12346 else if (strcmp (name
, "mips16") == 0
12347 || strcmp (name
, "MIPS-16") == 0)
12348 mips_opts
.mips16
= 1;
12349 else if (strcmp (name
, "nomips16") == 0
12350 || strcmp (name
, "noMIPS-16") == 0)
12351 mips_opts
.mips16
= 0;
12352 else if (strcmp (name
, "smartmips") == 0)
12354 if (!ISA_SUPPORTS_SMARTMIPS
)
12355 as_warn ("%s ISA does not support SmartMIPS ASE",
12356 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12357 mips_opts
.ase_smartmips
= 1;
12359 else if (strcmp (name
, "nosmartmips") == 0)
12360 mips_opts
.ase_smartmips
= 0;
12361 else if (strcmp (name
, "mips3d") == 0)
12362 mips_opts
.ase_mips3d
= 1;
12363 else if (strcmp (name
, "nomips3d") == 0)
12364 mips_opts
.ase_mips3d
= 0;
12365 else if (strcmp (name
, "mdmx") == 0)
12366 mips_opts
.ase_mdmx
= 1;
12367 else if (strcmp (name
, "nomdmx") == 0)
12368 mips_opts
.ase_mdmx
= 0;
12369 else if (strcmp (name
, "dsp") == 0)
12371 if (!ISA_SUPPORTS_DSP_ASE
)
12372 as_warn ("%s ISA does not support DSP ASE",
12373 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12374 mips_opts
.ase_dsp
= 1;
12376 else if (strcmp (name
, "nodsp") == 0)
12377 mips_opts
.ase_dsp
= 0;
12378 else if (strcmp (name
, "mt") == 0)
12380 if (!ISA_SUPPORTS_MT_ASE
)
12381 as_warn ("%s ISA does not support MT ASE",
12382 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
12383 mips_opts
.ase_mt
= 1;
12385 else if (strcmp (name
, "nomt") == 0)
12386 mips_opts
.ase_mt
= 0;
12387 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
12391 /* Permit the user to change the ISA and architecture on the fly.
12392 Needless to say, misuse can cause serious problems. */
12393 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
12396 mips_opts
.isa
= file_mips_isa
;
12397 mips_opts
.arch
= file_mips_arch
;
12399 else if (strncmp (name
, "arch=", 5) == 0)
12401 const struct mips_cpu_info
*p
;
12403 p
= mips_parse_cpu("internal use", name
+ 5);
12405 as_bad (_("unknown architecture %s"), name
+ 5);
12408 mips_opts
.arch
= p
->cpu
;
12409 mips_opts
.isa
= p
->isa
;
12412 else if (strncmp (name
, "mips", 4) == 0)
12414 const struct mips_cpu_info
*p
;
12416 p
= mips_parse_cpu("internal use", name
);
12418 as_bad (_("unknown ISA level %s"), name
+ 4);
12421 mips_opts
.arch
= p
->cpu
;
12422 mips_opts
.isa
= p
->isa
;
12426 as_bad (_("unknown ISA or architecture %s"), name
);
12428 switch (mips_opts
.isa
)
12436 mips_opts
.gp32
= 1;
12437 mips_opts
.fp32
= 1;
12444 mips_opts
.gp32
= 0;
12445 mips_opts
.fp32
= 0;
12448 as_bad (_("unknown ISA level %s"), name
+ 4);
12453 mips_opts
.gp32
= file_mips_gp32
;
12454 mips_opts
.fp32
= file_mips_fp32
;
12457 else if (strcmp (name
, "autoextend") == 0)
12458 mips_opts
.noautoextend
= 0;
12459 else if (strcmp (name
, "noautoextend") == 0)
12460 mips_opts
.noautoextend
= 1;
12461 else if (strcmp (name
, "push") == 0)
12463 struct mips_option_stack
*s
;
12465 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
12466 s
->next
= mips_opts_stack
;
12467 s
->options
= mips_opts
;
12468 mips_opts_stack
= s
;
12470 else if (strcmp (name
, "pop") == 0)
12472 struct mips_option_stack
*s
;
12474 s
= mips_opts_stack
;
12476 as_bad (_(".set pop with no .set push"));
12479 /* If we're changing the reorder mode we need to handle
12480 delay slots correctly. */
12481 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
12482 start_noreorder ();
12483 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
12486 mips_opts
= s
->options
;
12487 mips_opts_stack
= s
->next
;
12491 else if (strcmp (name
, "sym32") == 0)
12492 mips_opts
.sym32
= TRUE
;
12493 else if (strcmp (name
, "nosym32") == 0)
12494 mips_opts
.sym32
= FALSE
;
12497 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12499 *input_line_pointer
= ch
;
12500 demand_empty_rest_of_line ();
12503 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12504 .option pic2. It means to generate SVR4 PIC calls. */
12507 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12509 mips_pic
= SVR4_PIC
;
12510 mips_abicalls
= TRUE
;
12512 if (g_switch_seen
&& g_switch_value
!= 0)
12513 as_warn (_("-G may not be used with SVR4 PIC code"));
12514 g_switch_value
= 0;
12516 bfd_set_gp_size (stdoutput
, 0);
12517 demand_empty_rest_of_line ();
12520 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12521 PIC code. It sets the $gp register for the function based on the
12522 function address, which is in the register named in the argument.
12523 This uses a relocation against _gp_disp, which is handled specially
12524 by the linker. The result is:
12525 lui $gp,%hi(_gp_disp)
12526 addiu $gp,$gp,%lo(_gp_disp)
12527 addu $gp,$gp,.cpload argument
12528 The .cpload argument is normally $25 == $t9.
12530 The -mno-shared option changes this to:
12531 lui $gp,%hi(__gnu_local_gp)
12532 addiu $gp,$gp,%lo(__gnu_local_gp)
12533 and the argument is ignored. This saves an instruction, but the
12534 resulting code is not position independent; it uses an absolute
12535 address for __gnu_local_gp. Thus code assembled with -mno-shared
12536 can go into an ordinary executable, but not into a shared library. */
12539 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12545 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12546 .cpload is ignored. */
12547 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12553 /* .cpload should be in a .set noreorder section. */
12554 if (mips_opts
.noreorder
== 0)
12555 as_warn (_(".cpload not in noreorder section"));
12557 reg
= tc_get_register (0);
12559 /* If we need to produce a 64-bit address, we are better off using
12560 the default instruction sequence. */
12561 in_shared
= mips_in_shared
|| HAVE_64BIT_SYMBOLS
;
12563 ex
.X_op
= O_symbol
;
12564 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" :
12566 ex
.X_op_symbol
= NULL
;
12567 ex
.X_add_number
= 0;
12569 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12570 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12573 macro_build_lui (&ex
, mips_gp_register
);
12574 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12575 mips_gp_register
, BFD_RELOC_LO16
);
12577 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12578 mips_gp_register
, reg
);
12581 demand_empty_rest_of_line ();
12584 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12585 .cpsetup $reg1, offset|$reg2, label
12587 If offset is given, this results in:
12588 sd $gp, offset($sp)
12589 lui $gp, %hi(%neg(%gp_rel(label)))
12590 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12591 daddu $gp, $gp, $reg1
12593 If $reg2 is given, this results in:
12594 daddu $reg2, $gp, $0
12595 lui $gp, %hi(%neg(%gp_rel(label)))
12596 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12597 daddu $gp, $gp, $reg1
12598 $reg1 is normally $25 == $t9.
12600 The -mno-shared option replaces the last three instructions with
12602 addiu $gp,$gp,%lo(_gp)
12606 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12608 expressionS ex_off
;
12609 expressionS ex_sym
;
12612 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12613 We also need NewABI support. */
12614 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12620 reg1
= tc_get_register (0);
12621 SKIP_WHITESPACE ();
12622 if (*input_line_pointer
!= ',')
12624 as_bad (_("missing argument separator ',' for .cpsetup"));
12628 ++input_line_pointer
;
12629 SKIP_WHITESPACE ();
12630 if (*input_line_pointer
== '$')
12632 mips_cpreturn_register
= tc_get_register (0);
12633 mips_cpreturn_offset
= -1;
12637 mips_cpreturn_offset
= get_absolute_expression ();
12638 mips_cpreturn_register
= -1;
12640 SKIP_WHITESPACE ();
12641 if (*input_line_pointer
!= ',')
12643 as_bad (_("missing argument separator ',' for .cpsetup"));
12647 ++input_line_pointer
;
12648 SKIP_WHITESPACE ();
12649 expression (&ex_sym
);
12652 if (mips_cpreturn_register
== -1)
12654 ex_off
.X_op
= O_constant
;
12655 ex_off
.X_add_symbol
= NULL
;
12656 ex_off
.X_op_symbol
= NULL
;
12657 ex_off
.X_add_number
= mips_cpreturn_offset
;
12659 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12660 BFD_RELOC_LO16
, SP
);
12663 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12664 mips_gp_register
, 0);
12666 if (mips_in_shared
|| HAVE_64BIT_SYMBOLS
)
12668 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
12669 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
12672 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12673 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
12674 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
12676 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12677 mips_gp_register
, reg1
);
12683 ex
.X_op
= O_symbol
;
12684 ex
.X_add_symbol
= symbol_find_or_make ("__gnu_local_gp");
12685 ex
.X_op_symbol
= NULL
;
12686 ex
.X_add_number
= 0;
12688 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12689 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12691 macro_build_lui (&ex
, mips_gp_register
);
12692 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12693 mips_gp_register
, BFD_RELOC_LO16
);
12698 demand_empty_rest_of_line ();
12702 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12704 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12705 .cplocal is ignored. */
12706 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12712 mips_gp_register
= tc_get_register (0);
12713 demand_empty_rest_of_line ();
12716 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12717 offset from $sp. The offset is remembered, and after making a PIC
12718 call $gp is restored from that location. */
12721 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12725 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12726 .cprestore is ignored. */
12727 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12733 mips_cprestore_offset
= get_absolute_expression ();
12734 mips_cprestore_valid
= 1;
12736 ex
.X_op
= O_constant
;
12737 ex
.X_add_symbol
= NULL
;
12738 ex
.X_op_symbol
= NULL
;
12739 ex
.X_add_number
= mips_cprestore_offset
;
12742 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12743 SP
, HAVE_64BIT_ADDRESSES
);
12746 demand_empty_rest_of_line ();
12749 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12750 was given in the preceding .cpsetup, it results in:
12751 ld $gp, offset($sp)
12753 If a register $reg2 was given there, it results in:
12754 daddu $gp, $reg2, $0
12757 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12761 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12762 We also need NewABI support. */
12763 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12770 if (mips_cpreturn_register
== -1)
12772 ex
.X_op
= O_constant
;
12773 ex
.X_add_symbol
= NULL
;
12774 ex
.X_op_symbol
= NULL
;
12775 ex
.X_add_number
= mips_cpreturn_offset
;
12777 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12780 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12781 mips_cpreturn_register
, 0);
12784 demand_empty_rest_of_line ();
12787 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12788 code. It sets the offset to use in gp_rel relocations. */
12791 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12793 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12794 We also need NewABI support. */
12795 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12801 mips_gprel_offset
= get_absolute_expression ();
12803 demand_empty_rest_of_line ();
12806 /* Handle the .gpword pseudo-op. This is used when generating PIC
12807 code. It generates a 32 bit GP relative reloc. */
12810 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12816 /* When not generating PIC code, this is treated as .word. */
12817 if (mips_pic
!= SVR4_PIC
)
12823 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12824 mips_emit_delays ();
12826 mips_align (2, 0, label
);
12827 mips_clear_insn_labels ();
12831 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12833 as_bad (_("Unsupported use of .gpword"));
12834 ignore_rest_of_line ();
12838 md_number_to_chars (p
, 0, 4);
12839 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12840 BFD_RELOC_GPREL32
);
12842 demand_empty_rest_of_line ();
12846 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12852 /* When not generating PIC code, this is treated as .dword. */
12853 if (mips_pic
!= SVR4_PIC
)
12859 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12860 mips_emit_delays ();
12862 mips_align (3, 0, label
);
12863 mips_clear_insn_labels ();
12867 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12869 as_bad (_("Unsupported use of .gpdword"));
12870 ignore_rest_of_line ();
12874 md_number_to_chars (p
, 0, 8);
12875 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12876 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12878 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12879 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12880 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12882 demand_empty_rest_of_line ();
12885 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12886 tables in SVR4 PIC code. */
12889 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12893 /* This is ignored when not generating SVR4 PIC code. */
12894 if (mips_pic
!= SVR4_PIC
)
12900 /* Add $gp to the register named as an argument. */
12902 reg
= tc_get_register (0);
12903 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12906 demand_empty_rest_of_line ();
12909 /* Handle the .insn pseudo-op. This marks instruction labels in
12910 mips16 mode. This permits the linker to handle them specially,
12911 such as generating jalx instructions when needed. We also make
12912 them odd for the duration of the assembly, in order to generate the
12913 right sort of code. We will make them even in the adjust_symtab
12914 routine, while leaving them marked. This is convenient for the
12915 debugger and the disassembler. The linker knows to make them odd
12919 s_insn (int ignore ATTRIBUTE_UNUSED
)
12921 mips16_mark_labels ();
12923 demand_empty_rest_of_line ();
12926 /* Handle a .stabn directive. We need these in order to mark a label
12927 as being a mips16 text label correctly. Sometimes the compiler
12928 will emit a label, followed by a .stabn, and then switch sections.
12929 If the label and .stabn are in mips16 mode, then the label is
12930 really a mips16 text label. */
12933 s_mips_stab (int type
)
12936 mips16_mark_labels ();
12941 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12945 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12952 name
= input_line_pointer
;
12953 c
= get_symbol_end ();
12954 symbolP
= symbol_find_or_make (name
);
12955 S_SET_WEAK (symbolP
);
12956 *input_line_pointer
= c
;
12958 SKIP_WHITESPACE ();
12960 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12962 if (S_IS_DEFINED (symbolP
))
12964 as_bad ("ignoring attempt to redefine symbol %s",
12965 S_GET_NAME (symbolP
));
12966 ignore_rest_of_line ();
12970 if (*input_line_pointer
== ',')
12972 ++input_line_pointer
;
12973 SKIP_WHITESPACE ();
12977 if (exp
.X_op
!= O_symbol
)
12979 as_bad ("bad .weakext directive");
12980 ignore_rest_of_line ();
12983 symbol_set_value_expression (symbolP
, &exp
);
12986 demand_empty_rest_of_line ();
12989 /* Parse a register string into a number. Called from the ECOFF code
12990 to parse .frame. The argument is non-zero if this is the frame
12991 register, so that we can record it in mips_frame_reg. */
12994 tc_get_register (int frame
)
12998 SKIP_WHITESPACE ();
12999 if (! reg_lookup (&input_line_pointer
, RWARN
| RTYPE_NUM
| RTYPE_GP
, ®
))
13003 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
13004 mips_frame_reg_valid
= 1;
13005 mips_cprestore_valid
= 0;
13011 md_section_align (asection
*seg
, valueT addr
)
13013 int align
= bfd_get_section_alignment (stdoutput
, seg
);
13016 /* We don't need to align ELF sections to the full alignment.
13017 However, Irix 5 may prefer that we align them at least to a 16
13018 byte boundary. We don't bother to align the sections if we are
13019 targeted for an embedded system. */
13020 if (strcmp (TARGET_OS
, "elf") == 0)
13026 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
13029 /* Utility routine, called from above as well. If called while the
13030 input file is still being read, it's only an approximation. (For
13031 example, a symbol may later become defined which appeared to be
13032 undefined earlier.) */
13035 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
13040 if (g_switch_value
> 0)
13042 const char *symname
;
13045 /* Find out whether this symbol can be referenced off the $gp
13046 register. It can be if it is smaller than the -G size or if
13047 it is in the .sdata or .sbss section. Certain symbols can
13048 not be referenced off the $gp, although it appears as though
13050 symname
= S_GET_NAME (sym
);
13051 if (symname
!= (const char *) NULL
13052 && (strcmp (symname
, "eprol") == 0
13053 || strcmp (symname
, "etext") == 0
13054 || strcmp (symname
, "_gp") == 0
13055 || strcmp (symname
, "edata") == 0
13056 || strcmp (symname
, "_fbss") == 0
13057 || strcmp (symname
, "_fdata") == 0
13058 || strcmp (symname
, "_ftext") == 0
13059 || strcmp (symname
, "end") == 0
13060 || strcmp (symname
, "_gp_disp") == 0))
13062 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
13064 #ifndef NO_ECOFF_DEBUGGING
13065 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
13066 && (symbol_get_obj (sym
)->ecoff_extern_size
13067 <= g_switch_value
))
13069 /* We must defer this decision until after the whole
13070 file has been read, since there might be a .extern
13071 after the first use of this symbol. */
13072 || (before_relaxing
13073 #ifndef NO_ECOFF_DEBUGGING
13074 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
13076 && S_GET_VALUE (sym
) == 0)
13077 || (S_GET_VALUE (sym
) != 0
13078 && S_GET_VALUE (sym
) <= g_switch_value
)))
13082 const char *segname
;
13084 segname
= segment_name (S_GET_SEGMENT (sym
));
13085 assert (strcmp (segname
, ".lit8") != 0
13086 && strcmp (segname
, ".lit4") != 0);
13087 change
= (strcmp (segname
, ".sdata") != 0
13088 && strcmp (segname
, ".sbss") != 0
13089 && strncmp (segname
, ".sdata.", 7) != 0
13090 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
13095 /* We are not optimizing for the $gp register. */
13100 /* Return true if the given symbol should be considered local for SVR4 PIC. */
13103 pic_need_relax (symbolS
*sym
, asection
*segtype
)
13106 bfd_boolean linkonce
;
13108 /* Handle the case of a symbol equated to another symbol. */
13109 while (symbol_equated_reloc_p (sym
))
13113 /* It's possible to get a loop here in a badly written
13115 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
13121 symsec
= S_GET_SEGMENT (sym
);
13123 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13125 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
13127 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
13131 /* The GNU toolchain uses an extension for ELF: a section
13132 beginning with the magic string .gnu.linkonce is a linkonce
13134 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
13135 sizeof ".gnu.linkonce" - 1) == 0)
13139 /* This must duplicate the test in adjust_reloc_syms. */
13140 return (symsec
!= &bfd_und_section
13141 && symsec
!= &bfd_abs_section
13142 && ! bfd_is_com_section (symsec
)
13145 /* A global or weak symbol is treated as external. */
13146 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
13147 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
13153 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13154 extended opcode. SEC is the section the frag is in. */
13157 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
13160 register const struct mips16_immed_operand
*op
;
13162 int mintiny
, maxtiny
;
13166 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
13168 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
13171 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13172 op
= mips16_immed_operands
;
13173 while (op
->type
!= type
)
13176 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
13181 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
13184 maxtiny
= 1 << op
->nbits
;
13189 maxtiny
= (1 << op
->nbits
) - 1;
13194 mintiny
= - (1 << (op
->nbits
- 1));
13195 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
13198 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
13199 val
= S_GET_VALUE (fragp
->fr_symbol
);
13200 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
13206 /* We won't have the section when we are called from
13207 mips_relax_frag. However, we will always have been called
13208 from md_estimate_size_before_relax first. If this is a
13209 branch to a different section, we mark it as such. If SEC is
13210 NULL, and the frag is not marked, then it must be a branch to
13211 the same section. */
13214 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
13219 /* Must have been called from md_estimate_size_before_relax. */
13222 fragp
->fr_subtype
=
13223 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13225 /* FIXME: We should support this, and let the linker
13226 catch branches and loads that are out of range. */
13227 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
13228 _("unsupported PC relative reference to different section"));
13232 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
13233 /* Assume non-extended on the first relaxation pass.
13234 The address we have calculated will be bogus if this is
13235 a forward branch to another frag, as the forward frag
13236 will have fr_address == 0. */
13240 /* In this case, we know for sure that the symbol fragment is in
13241 the same section. If the relax_marker of the symbol fragment
13242 differs from the relax_marker of this fragment, we have not
13243 yet adjusted the symbol fragment fr_address. We want to add
13244 in STRETCH in order to get a better estimate of the address.
13245 This particularly matters because of the shift bits. */
13247 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
13251 /* Adjust stretch for any alignment frag. Note that if have
13252 been expanding the earlier code, the symbol may be
13253 defined in what appears to be an earlier frag. FIXME:
13254 This doesn't handle the fr_subtype field, which specifies
13255 a maximum number of bytes to skip when doing an
13257 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
13259 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
13262 stretch
= - ((- stretch
)
13263 & ~ ((1 << (int) f
->fr_offset
) - 1));
13265 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
13274 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13276 /* The base address rules are complicated. The base address of
13277 a branch is the following instruction. The base address of a
13278 PC relative load or add is the instruction itself, but if it
13279 is in a delay slot (in which case it can not be extended) use
13280 the address of the instruction whose delay slot it is in. */
13281 if (type
== 'p' || type
== 'q')
13285 /* If we are currently assuming that this frag should be
13286 extended, then, the current address is two bytes
13288 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13291 /* Ignore the low bit in the target, since it will be set
13292 for a text label. */
13293 if ((val
& 1) != 0)
13296 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13298 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13301 val
-= addr
& ~ ((1 << op
->shift
) - 1);
13303 /* Branch offsets have an implicit 0 in the lowest bit. */
13304 if (type
== 'p' || type
== 'q')
13307 /* If any of the shifted bits are set, we must use an extended
13308 opcode. If the address depends on the size of this
13309 instruction, this can lead to a loop, so we arrange to always
13310 use an extended opcode. We only check this when we are in
13311 the main relaxation loop, when SEC is NULL. */
13312 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
13314 fragp
->fr_subtype
=
13315 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13319 /* If we are about to mark a frag as extended because the value
13320 is precisely maxtiny + 1, then there is a chance of an
13321 infinite loop as in the following code:
13326 In this case when the la is extended, foo is 0x3fc bytes
13327 away, so the la can be shrunk, but then foo is 0x400 away, so
13328 the la must be extended. To avoid this loop, we mark the
13329 frag as extended if it was small, and is about to become
13330 extended with a value of maxtiny + 1. */
13331 if (val
== ((maxtiny
+ 1) << op
->shift
)
13332 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
13335 fragp
->fr_subtype
=
13336 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
13340 else if (symsec
!= absolute_section
&& sec
!= NULL
)
13341 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
13343 if ((val
& ((1 << op
->shift
) - 1)) != 0
13344 || val
< (mintiny
<< op
->shift
)
13345 || val
> (maxtiny
<< op
->shift
))
13351 /* Compute the length of a branch sequence, and adjust the
13352 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
13353 worst-case length is computed, with UPDATE being used to indicate
13354 whether an unconditional (-1), branch-likely (+1) or regular (0)
13355 branch is to be computed. */
13357 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
13359 bfd_boolean toofar
;
13363 && S_IS_DEFINED (fragp
->fr_symbol
)
13364 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
13369 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
13371 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
13375 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
13378 /* If the symbol is not defined or it's in a different segment,
13379 assume the user knows what's going on and emit a short
13385 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13387 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
13388 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
13389 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
13395 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
13398 if (mips_pic
!= NO_PIC
)
13400 /* Additional space for PIC loading of target address. */
13402 if (mips_opts
.isa
== ISA_MIPS1
)
13403 /* Additional space for $at-stabilizing nop. */
13407 /* If branch is conditional. */
13408 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
13415 /* Estimate the size of a frag before relaxing. Unless this is the
13416 mips16, we are not really relaxing here, and the final size is
13417 encoded in the subtype information. For the mips16, we have to
13418 decide whether we are using an extended opcode or not. */
13421 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
13425 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13428 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
13430 return fragp
->fr_var
;
13433 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13434 /* We don't want to modify the EXTENDED bit here; it might get us
13435 into infinite loops. We change it only in mips_relax_frag(). */
13436 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
13438 if (mips_pic
== NO_PIC
)
13439 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
13440 else if (mips_pic
== SVR4_PIC
)
13441 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
13442 else if (mips_pic
== VXWORKS_PIC
)
13443 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13450 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
13451 return -RELAX_FIRST (fragp
->fr_subtype
);
13454 return -RELAX_SECOND (fragp
->fr_subtype
);
13457 /* This is called to see whether a reloc against a defined symbol
13458 should be converted into a reloc against a section. */
13461 mips_fix_adjustable (fixS
*fixp
)
13463 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13464 about the format of the offset in the .o file. */
13465 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13468 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13469 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13472 if (fixp
->fx_addsy
== NULL
)
13475 /* If symbol SYM is in a mergeable section, relocations of the form
13476 SYM + 0 can usually be made section-relative. The mergeable data
13477 is then identified by the section offset rather than by the symbol.
13479 However, if we're generating REL LO16 relocations, the offset is split
13480 between the LO16 and parterning high part relocation. The linker will
13481 need to recalculate the complete offset in order to correctly identify
13484 The linker has traditionally not looked for the parterning high part
13485 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13486 placed anywhere. Rather than break backwards compatibility by changing
13487 this, it seems better not to force the issue, and instead keep the
13488 original symbol. This will work with either linker behavior. */
13489 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
13490 || fixp
->fx_r_type
== BFD_RELOC_MIPS16_LO16
13491 || reloc_needs_lo_p (fixp
->fx_r_type
))
13492 && HAVE_IN_PLACE_ADDENDS
13493 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
13497 /* Don't adjust relocations against mips16 symbols, so that the linker
13498 can find them if it needs to set up a stub. */
13499 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13500 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13501 && fixp
->fx_subsy
== NULL
)
13508 /* Translate internal representation of relocation info to BFD target
13512 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13514 static arelent
*retval
[4];
13516 bfd_reloc_code_real_type code
;
13518 memset (retval
, 0, sizeof(retval
));
13519 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13520 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13521 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13522 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13524 if (fixp
->fx_pcrel
)
13526 assert (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
);
13528 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13529 Relocations want only the symbol offset. */
13530 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
13531 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13533 /* A gruesome hack which is a result of the gruesome gas
13534 reloc handling. What's worse, for COFF (as opposed to
13535 ECOFF), we might need yet another copy of reloc->address.
13536 See bfd_install_relocation. */
13537 reloc
->addend
+= reloc
->address
;
13541 reloc
->addend
= fixp
->fx_addnumber
;
13543 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13544 entry to be used in the relocation's section offset. */
13545 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13547 reloc
->address
= reloc
->addend
;
13551 code
= fixp
->fx_r_type
;
13553 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13554 if (reloc
->howto
== NULL
)
13556 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13557 _("Can not represent %s relocation in this object file format"),
13558 bfd_get_reloc_code_name (code
));
13565 /* Relax a machine dependent frag. This returns the amount by which
13566 the current size of the frag should change. */
13569 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13571 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13573 offsetT old_var
= fragp
->fr_var
;
13575 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13577 return fragp
->fr_var
- old_var
;
13580 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13583 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13585 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13587 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13592 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13594 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13601 /* Convert a machine dependent frag. */
13604 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13606 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13609 unsigned long insn
;
13613 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13615 if (target_big_endian
)
13616 insn
= bfd_getb32 (buf
);
13618 insn
= bfd_getl32 (buf
);
13620 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13622 /* We generate a fixup instead of applying it right now
13623 because, if there are linker relaxations, we're going to
13624 need the relocations. */
13625 exp
.X_op
= O_symbol
;
13626 exp
.X_add_symbol
= fragp
->fr_symbol
;
13627 exp
.X_add_number
= fragp
->fr_offset
;
13629 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13630 4, &exp
, 1, BFD_RELOC_16_PCREL_S2
);
13631 fixp
->fx_file
= fragp
->fr_file
;
13632 fixp
->fx_line
= fragp
->fr_line
;
13634 md_number_to_chars ((char *) buf
, insn
, 4);
13641 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13642 _("relaxed out-of-range branch into a jump"));
13644 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13647 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13649 /* Reverse the branch. */
13650 switch ((insn
>> 28) & 0xf)
13653 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13654 have the condition reversed by tweaking a single
13655 bit, and their opcodes all have 0x4???????. */
13656 assert ((insn
& 0xf1000000) == 0x41000000);
13657 insn
^= 0x00010000;
13661 /* bltz 0x04000000 bgez 0x04010000
13662 bltzal 0x04100000 bgezal 0x04110000 */
13663 assert ((insn
& 0xfc0e0000) == 0x04000000);
13664 insn
^= 0x00010000;
13668 /* beq 0x10000000 bne 0x14000000
13669 blez 0x18000000 bgtz 0x1c000000 */
13670 insn
^= 0x04000000;
13678 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13680 /* Clear the and-link bit. */
13681 assert ((insn
& 0xfc1c0000) == 0x04100000);
13683 /* bltzal 0x04100000 bgezal 0x04110000
13684 bltzall 0x04120000 bgezall 0x04130000 */
13685 insn
&= ~0x00100000;
13688 /* Branch over the branch (if the branch was likely) or the
13689 full jump (not likely case). Compute the offset from the
13690 current instruction to branch to. */
13691 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13695 /* How many bytes in instructions we've already emitted? */
13696 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13697 /* How many bytes in instructions from here to the end? */
13698 i
= fragp
->fr_var
- i
;
13700 /* Convert to instruction count. */
13702 /* Branch counts from the next instruction. */
13705 /* Branch over the jump. */
13706 md_number_to_chars ((char *) buf
, insn
, 4);
13710 md_number_to_chars ((char *) buf
, 0, 4);
13713 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13715 /* beql $0, $0, 2f */
13717 /* Compute the PC offset from the current instruction to
13718 the end of the variable frag. */
13719 /* How many bytes in instructions we've already emitted? */
13720 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13721 /* How many bytes in instructions from here to the end? */
13722 i
= fragp
->fr_var
- i
;
13723 /* Convert to instruction count. */
13725 /* Don't decrement i, because we want to branch over the
13729 md_number_to_chars ((char *) buf
, insn
, 4);
13732 md_number_to_chars ((char *) buf
, 0, 4);
13737 if (mips_pic
== NO_PIC
)
13740 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13741 ? 0x0c000000 : 0x08000000);
13742 exp
.X_op
= O_symbol
;
13743 exp
.X_add_symbol
= fragp
->fr_symbol
;
13744 exp
.X_add_number
= fragp
->fr_offset
;
13746 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13747 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13748 fixp
->fx_file
= fragp
->fr_file
;
13749 fixp
->fx_line
= fragp
->fr_line
;
13751 md_number_to_chars ((char *) buf
, insn
, 4);
13756 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13757 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13758 exp
.X_op
= O_symbol
;
13759 exp
.X_add_symbol
= fragp
->fr_symbol
;
13760 exp
.X_add_number
= fragp
->fr_offset
;
13762 if (fragp
->fr_offset
)
13764 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13765 exp
.X_add_number
= 0;
13768 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13769 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13770 fixp
->fx_file
= fragp
->fr_file
;
13771 fixp
->fx_line
= fragp
->fr_line
;
13773 md_number_to_chars ((char *) buf
, insn
, 4);
13776 if (mips_opts
.isa
== ISA_MIPS1
)
13779 md_number_to_chars ((char *) buf
, 0, 4);
13783 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13784 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13786 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13787 4, &exp
, 0, BFD_RELOC_LO16
);
13788 fixp
->fx_file
= fragp
->fr_file
;
13789 fixp
->fx_line
= fragp
->fr_line
;
13791 md_number_to_chars ((char *) buf
, insn
, 4);
13795 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13800 md_number_to_chars ((char *) buf
, insn
, 4);
13805 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13806 + fragp
->fr_fix
+ fragp
->fr_var
);
13808 fragp
->fr_fix
+= fragp
->fr_var
;
13813 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13816 register const struct mips16_immed_operand
*op
;
13817 bfd_boolean small
, ext
;
13820 unsigned long insn
;
13821 bfd_boolean use_extend
;
13822 unsigned short extend
;
13824 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13825 op
= mips16_immed_operands
;
13826 while (op
->type
!= type
)
13829 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13840 resolve_symbol_value (fragp
->fr_symbol
);
13841 val
= S_GET_VALUE (fragp
->fr_symbol
);
13846 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13848 /* The rules for the base address of a PC relative reloc are
13849 complicated; see mips16_extended_frag. */
13850 if (type
== 'p' || type
== 'q')
13855 /* Ignore the low bit in the target, since it will be
13856 set for a text label. */
13857 if ((val
& 1) != 0)
13860 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13862 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13865 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13868 /* Make sure the section winds up with the alignment we have
13871 record_alignment (asec
, op
->shift
);
13875 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13876 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13877 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13878 _("extended instruction in delay slot"));
13880 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13882 if (target_big_endian
)
13883 insn
= bfd_getb16 (buf
);
13885 insn
= bfd_getl16 (buf
);
13887 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13888 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13889 small
, ext
, &insn
, &use_extend
, &extend
);
13893 md_number_to_chars ((char *) buf
, 0xf000 | extend
, 2);
13894 fragp
->fr_fix
+= 2;
13898 md_number_to_chars ((char *) buf
, insn
, 2);
13899 fragp
->fr_fix
+= 2;
13907 first
= RELAX_FIRST (fragp
->fr_subtype
);
13908 second
= RELAX_SECOND (fragp
->fr_subtype
);
13909 fixp
= (fixS
*) fragp
->fr_opcode
;
13911 /* Possibly emit a warning if we've chosen the longer option. */
13912 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13913 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13915 const char *msg
= macro_warning (fragp
->fr_subtype
);
13917 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13920 /* Go through all the fixups for the first sequence. Disable them
13921 (by marking them as done) if we're going to use the second
13922 sequence instead. */
13924 && fixp
->fx_frag
== fragp
13925 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13927 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13929 fixp
= fixp
->fx_next
;
13932 /* Go through the fixups for the second sequence. Disable them if
13933 we're going to use the first sequence, otherwise adjust their
13934 addresses to account for the relaxation. */
13935 while (fixp
&& fixp
->fx_frag
== fragp
)
13937 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13938 fixp
->fx_where
-= first
;
13941 fixp
= fixp
->fx_next
;
13944 /* Now modify the frag contents. */
13945 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13949 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13950 memmove (start
, start
+ first
, second
);
13951 fragp
->fr_fix
-= first
;
13954 fragp
->fr_fix
-= second
;
13960 /* This function is called after the relocs have been generated.
13961 We've been storing mips16 text labels as odd. Here we convert them
13962 back to even for the convenience of the debugger. */
13965 mips_frob_file_after_relocs (void)
13968 unsigned int count
, i
;
13970 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13973 syms
= bfd_get_outsymbols (stdoutput
);
13974 count
= bfd_get_symcount (stdoutput
);
13975 for (i
= 0; i
< count
; i
++, syms
++)
13977 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13978 && ((*syms
)->value
& 1) != 0)
13980 (*syms
)->value
&= ~1;
13981 /* If the symbol has an odd size, it was probably computed
13982 incorrectly, so adjust that as well. */
13983 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13984 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13991 /* This function is called whenever a label is defined. It is used
13992 when handling branch delays; if a branch has a label, we assume we
13993 can not move it. */
13996 mips_define_label (symbolS
*sym
)
13998 struct insn_label_list
*l
;
14000 if (free_insn_labels
== NULL
)
14001 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
14004 l
= free_insn_labels
;
14005 free_insn_labels
= l
->next
;
14009 l
->next
= insn_labels
;
14013 dwarf2_emit_label (sym
);
14017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14019 /* Some special processing for a MIPS ELF file. */
14022 mips_elf_final_processing (void)
14024 /* Write out the register information. */
14025 if (mips_abi
!= N64_ABI
)
14029 s
.ri_gprmask
= mips_gprmask
;
14030 s
.ri_cprmask
[0] = mips_cprmask
[0];
14031 s
.ri_cprmask
[1] = mips_cprmask
[1];
14032 s
.ri_cprmask
[2] = mips_cprmask
[2];
14033 s
.ri_cprmask
[3] = mips_cprmask
[3];
14034 /* The gp_value field is set by the MIPS ELF backend. */
14036 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
14037 ((Elf32_External_RegInfo
*)
14038 mips_regmask_frag
));
14042 Elf64_Internal_RegInfo s
;
14044 s
.ri_gprmask
= mips_gprmask
;
14046 s
.ri_cprmask
[0] = mips_cprmask
[0];
14047 s
.ri_cprmask
[1] = mips_cprmask
[1];
14048 s
.ri_cprmask
[2] = mips_cprmask
[2];
14049 s
.ri_cprmask
[3] = mips_cprmask
[3];
14050 /* The gp_value field is set by the MIPS ELF backend. */
14052 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
14053 ((Elf64_External_RegInfo
*)
14054 mips_regmask_frag
));
14057 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
14058 sort of BFD interface for this. */
14059 if (mips_any_noreorder
)
14060 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
14061 if (mips_pic
!= NO_PIC
)
14063 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
14064 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14067 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
14069 /* Set MIPS ELF flags for ASEs. */
14070 /* We may need to define a new flag for DSP ASE, and set this flag when
14071 file_ase_dsp is true. */
14072 /* We may need to define a new flag for MT ASE, and set this flag when
14073 file_ase_mt is true. */
14074 if (file_ase_mips16
)
14075 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
14076 #if 0 /* XXX FIXME */
14077 if (file_ase_mips3d
)
14078 elf_elfheader (stdoutput
)->e_flags
|= ???;
14081 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
14083 /* Set the MIPS ELF ABI flags. */
14084 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
14085 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
14086 else if (mips_abi
== O64_ABI
)
14087 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
14088 else if (mips_abi
== EABI_ABI
)
14090 if (!file_mips_gp32
)
14091 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
14093 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
14095 else if (mips_abi
== N32_ABI
)
14096 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
14098 /* Nothing to do for N64_ABI. */
14100 if (mips_32bitmode
)
14101 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
14103 #if 0 /* XXX FIXME */
14104 /* 32 bit code with 64 bit FP registers. */
14105 if (!file_mips_fp32
&& ABI_NEEDS_32BIT_REGS (mips_abi
))
14106 elf_elfheader (stdoutput
)->e_flags
|= ???;
14110 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14112 typedef struct proc
{
14114 symbolS
*func_end_sym
;
14115 unsigned long reg_mask
;
14116 unsigned long reg_offset
;
14117 unsigned long fpreg_mask
;
14118 unsigned long fpreg_offset
;
14119 unsigned long frame_offset
;
14120 unsigned long frame_reg
;
14121 unsigned long pc_reg
;
14124 static procS cur_proc
;
14125 static procS
*cur_proc_ptr
;
14126 static int numprocs
;
14128 /* Fill in an rs_align_code fragment. */
14131 mips_handle_align (fragS
*fragp
)
14133 if (fragp
->fr_type
!= rs_align_code
)
14136 if (mips_opts
.mips16
)
14138 static const unsigned char be_nop
[] = { 0x65, 0x00 };
14139 static const unsigned char le_nop
[] = { 0x00, 0x65 };
14144 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
14145 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
14153 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
14157 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
14161 md_obj_begin (void)
14168 /* check for premature end, nesting errors, etc */
14170 as_warn (_("missing .end at end of assembly"));
14179 if (*input_line_pointer
== '-')
14181 ++input_line_pointer
;
14184 if (!ISDIGIT (*input_line_pointer
))
14185 as_bad (_("expected simple number"));
14186 if (input_line_pointer
[0] == '0')
14188 if (input_line_pointer
[1] == 'x')
14190 input_line_pointer
+= 2;
14191 while (ISXDIGIT (*input_line_pointer
))
14194 val
|= hex_value (*input_line_pointer
++);
14196 return negative
? -val
: val
;
14200 ++input_line_pointer
;
14201 while (ISDIGIT (*input_line_pointer
))
14204 val
|= *input_line_pointer
++ - '0';
14206 return negative
? -val
: val
;
14209 if (!ISDIGIT (*input_line_pointer
))
14211 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
14212 *input_line_pointer
, *input_line_pointer
);
14213 as_warn (_("invalid number"));
14216 while (ISDIGIT (*input_line_pointer
))
14219 val
+= *input_line_pointer
++ - '0';
14221 return negative
? -val
: val
;
14224 /* The .file directive; just like the usual .file directive, but there
14225 is an initial number which is the ECOFF file index. In the non-ECOFF
14226 case .file implies DWARF-2. */
14229 s_mips_file (int x ATTRIBUTE_UNUSED
)
14231 static int first_file_directive
= 0;
14233 if (ECOFF_DEBUGGING
)
14242 filename
= dwarf2_directive_file (0);
14244 /* Versions of GCC up to 3.1 start files with a ".file"
14245 directive even for stabs output. Make sure that this
14246 ".file" is handled. Note that you need a version of GCC
14247 after 3.1 in order to support DWARF-2 on MIPS. */
14248 if (filename
!= NULL
&& ! first_file_directive
)
14250 (void) new_logical_line (filename
, -1);
14251 s_app_file_string (filename
, 0);
14253 first_file_directive
= 1;
14257 /* The .loc directive, implying DWARF-2. */
14260 s_mips_loc (int x ATTRIBUTE_UNUSED
)
14262 if (!ECOFF_DEBUGGING
)
14263 dwarf2_directive_loc (0);
14266 /* The .end directive. */
14269 s_mips_end (int x ATTRIBUTE_UNUSED
)
14273 /* Following functions need their own .frame and .cprestore directives. */
14274 mips_frame_reg_valid
= 0;
14275 mips_cprestore_valid
= 0;
14277 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
14280 demand_empty_rest_of_line ();
14285 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14286 as_warn (_(".end not in text section"));
14290 as_warn (_(".end directive without a preceding .ent directive."));
14291 demand_empty_rest_of_line ();
14297 assert (S_GET_NAME (p
));
14298 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->func_sym
)))
14299 as_warn (_(".end symbol does not match .ent symbol."));
14301 if (debug_type
== DEBUG_STABS
)
14302 stabs_generate_asm_endfunc (S_GET_NAME (p
),
14306 as_warn (_(".end directive missing or unknown symbol"));
14309 /* Create an expression to calculate the size of the function. */
14310 if (p
&& cur_proc_ptr
)
14312 OBJ_SYMFIELD_TYPE
*obj
= symbol_get_obj (p
);
14313 expressionS
*exp
= xmalloc (sizeof (expressionS
));
14316 exp
->X_op
= O_subtract
;
14317 exp
->X_add_symbol
= symbol_temp_new_now ();
14318 exp
->X_op_symbol
= p
;
14319 exp
->X_add_number
= 0;
14321 cur_proc_ptr
->func_end_sym
= exp
->X_add_symbol
;
14324 /* Generate a .pdr section. */
14325 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
14328 segT saved_seg
= now_seg
;
14329 subsegT saved_subseg
= now_subseg
;
14334 dot
= frag_now_fix ();
14336 #ifdef md_flush_pending_output
14337 md_flush_pending_output ();
14341 subseg_set (pdr_seg
, 0);
14343 /* Write the symbol. */
14344 exp
.X_op
= O_symbol
;
14345 exp
.X_add_symbol
= p
;
14346 exp
.X_add_number
= 0;
14347 emit_expr (&exp
, 4);
14349 fragp
= frag_more (7 * 4);
14351 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
14352 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
14353 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
14354 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
14355 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
14356 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
14357 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
14359 subseg_set (saved_seg
, saved_subseg
);
14361 #endif /* OBJ_ELF */
14363 cur_proc_ptr
= NULL
;
14366 /* The .aent and .ent directives. */
14369 s_mips_ent (int aent
)
14373 symbolP
= get_symbol ();
14374 if (*input_line_pointer
== ',')
14375 ++input_line_pointer
;
14376 SKIP_WHITESPACE ();
14377 if (ISDIGIT (*input_line_pointer
)
14378 || *input_line_pointer
== '-')
14381 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
14382 as_warn (_(".ent or .aent not in text section."));
14384 if (!aent
&& cur_proc_ptr
)
14385 as_warn (_("missing .end"));
14389 /* This function needs its own .frame and .cprestore directives. */
14390 mips_frame_reg_valid
= 0;
14391 mips_cprestore_valid
= 0;
14393 cur_proc_ptr
= &cur_proc
;
14394 memset (cur_proc_ptr
, '\0', sizeof (procS
));
14396 cur_proc_ptr
->func_sym
= symbolP
;
14398 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
14402 if (debug_type
== DEBUG_STABS
)
14403 stabs_generate_asm_func (S_GET_NAME (symbolP
),
14404 S_GET_NAME (symbolP
));
14407 demand_empty_rest_of_line ();
14410 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
14411 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
14412 s_mips_frame is used so that we can set the PDR information correctly.
14413 We can't use the ecoff routines because they make reference to the ecoff
14414 symbol table (in the mdebug section). */
14417 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
14420 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14424 if (cur_proc_ptr
== (procS
*) NULL
)
14426 as_warn (_(".frame outside of .ent"));
14427 demand_empty_rest_of_line ();
14431 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14433 SKIP_WHITESPACE ();
14434 if (*input_line_pointer
++ != ','
14435 || get_absolute_expression_and_terminator (&val
) != ',')
14437 as_warn (_("Bad .frame directive"));
14438 --input_line_pointer
;
14439 demand_empty_rest_of_line ();
14443 cur_proc_ptr
->frame_offset
= val
;
14444 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14446 demand_empty_rest_of_line ();
14449 #endif /* OBJ_ELF */
14453 /* The .fmask and .mask directives. If the mdebug section is present
14454 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14455 embedded targets, s_mips_mask is used so that we can set the PDR
14456 information correctly. We can't use the ecoff routines because they
14457 make reference to the ecoff symbol table (in the mdebug section). */
14460 s_mips_mask (int reg_type
)
14463 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14467 if (cur_proc_ptr
== (procS
*) NULL
)
14469 as_warn (_(".mask/.fmask outside of .ent"));
14470 demand_empty_rest_of_line ();
14474 if (get_absolute_expression_and_terminator (&mask
) != ',')
14476 as_warn (_("Bad .mask/.fmask directive"));
14477 --input_line_pointer
;
14478 demand_empty_rest_of_line ();
14482 off
= get_absolute_expression ();
14484 if (reg_type
== 'F')
14486 cur_proc_ptr
->fpreg_mask
= mask
;
14487 cur_proc_ptr
->fpreg_offset
= off
;
14491 cur_proc_ptr
->reg_mask
= mask
;
14492 cur_proc_ptr
->reg_offset
= off
;
14495 demand_empty_rest_of_line ();
14498 #endif /* OBJ_ELF */
14499 s_ignore (reg_type
);
14502 /* A table describing all the processors gas knows about. Names are
14503 matched in the order listed.
14505 To ease comparison, please keep this table in the same order as
14506 gcc's mips_cpu_info_table[]. */
14507 static const struct mips_cpu_info mips_cpu_info_table
[] =
14509 /* Entries for generic ISAs */
14510 { "mips1", MIPS_CPU_IS_ISA
, ISA_MIPS1
, CPU_R3000
},
14511 { "mips2", MIPS_CPU_IS_ISA
, ISA_MIPS2
, CPU_R6000
},
14512 { "mips3", MIPS_CPU_IS_ISA
, ISA_MIPS3
, CPU_R4000
},
14513 { "mips4", MIPS_CPU_IS_ISA
, ISA_MIPS4
, CPU_R8000
},
14514 { "mips5", MIPS_CPU_IS_ISA
, ISA_MIPS5
, CPU_MIPS5
},
14515 { "mips32", MIPS_CPU_IS_ISA
, ISA_MIPS32
, CPU_MIPS32
},
14516 { "mips32r2", MIPS_CPU_IS_ISA
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14517 { "mips64", MIPS_CPU_IS_ISA
, ISA_MIPS64
, CPU_MIPS64
},
14518 { "mips64r2", MIPS_CPU_IS_ISA
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14521 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14522 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14523 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14526 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14529 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14530 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14531 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14532 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14533 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14534 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14535 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14536 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14537 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14538 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14539 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14540 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14543 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14544 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14545 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14546 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14547 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14548 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14549 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14550 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14551 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14552 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14553 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14554 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14555 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
14558 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14559 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14560 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14561 { "4ksc", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32
, CPU_MIPS32
},
14563 /* MIPS 32 Release 2 */
14564 { "4kec", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14565 { "4kem", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14566 { "4kep", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14567 { "4ksd", MIPS_CPU_ASE_SMARTMIPS
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14568 { "m4k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14569 { "m4kp", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14570 { "24k", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14571 { "24kc", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14572 { "24kf", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14573 { "24kx", 0, ISA_MIPS32R2
, CPU_MIPS32R2
},
14574 /* 24ke is a 24k with DSP ASE, other ASEs are optional. */
14575 { "24ke", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14576 { "24kec", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14577 { "24kef", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14578 { "24kex", MIPS_CPU_ASE_DSP
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14579 /* 34k is a 24k with MT ASE, other ASEs are optional. */
14580 { "34kc", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14581 { "34kf", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14582 { "34kx", MIPS_CPU_ASE_MT
, ISA_MIPS32R2
, CPU_MIPS32R2
},
14585 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14586 { "5kf", 0, ISA_MIPS64
, CPU_MIPS64
},
14587 { "20kc", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64
, CPU_MIPS64
},
14589 /* MIPS 64 Release 2 */
14590 { "25kf", MIPS_CPU_ASE_MIPS3D
, ISA_MIPS64R2
, CPU_MIPS64R2
},
14592 /* Broadcom SB-1 CPU core */
14593 { "sb1", MIPS_CPU_ASE_MIPS3D
| MIPS_CPU_ASE_MDMX
,
14594 ISA_MIPS64
, CPU_SB1
},
14601 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14602 with a final "000" replaced by "k". Ignore case.
14604 Note: this function is shared between GCC and GAS. */
14607 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14609 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14610 given
++, canonical
++;
14612 return ((*given
== 0 && *canonical
== 0)
14613 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14617 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14618 CPU name. We've traditionally allowed a lot of variation here.
14620 Note: this function is shared between GCC and GAS. */
14623 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14625 /* First see if the name matches exactly, or with a final "000"
14626 turned into "k". */
14627 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14630 /* If not, try comparing based on numerical designation alone.
14631 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14632 if (TOLOWER (*given
) == 'r')
14634 if (!ISDIGIT (*given
))
14637 /* Skip over some well-known prefixes in the canonical name,
14638 hoping to find a number there too. */
14639 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14641 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14643 else if (TOLOWER (canonical
[0]) == 'r')
14646 return mips_strict_matching_cpu_name_p (canonical
, given
);
14650 /* Parse an option that takes the name of a processor as its argument.
14651 OPTION is the name of the option and CPU_STRING is the argument.
14652 Return the corresponding processor enumeration if the CPU_STRING is
14653 recognized, otherwise report an error and return null.
14655 A similar function exists in GCC. */
14657 static const struct mips_cpu_info
*
14658 mips_parse_cpu (const char *option
, const char *cpu_string
)
14660 const struct mips_cpu_info
*p
;
14662 /* 'from-abi' selects the most compatible architecture for the given
14663 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14664 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14665 version. Look first at the -mgp options, if given, otherwise base
14666 the choice on MIPS_DEFAULT_64BIT.
14668 Treat NO_ABI like the EABIs. One reason to do this is that the
14669 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14670 architecture. This code picks MIPS I for 'mips' and MIPS III for
14671 'mips64', just as we did in the days before 'from-abi'. */
14672 if (strcasecmp (cpu_string
, "from-abi") == 0)
14674 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14675 return mips_cpu_info_from_isa (ISA_MIPS1
);
14677 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14678 return mips_cpu_info_from_isa (ISA_MIPS3
);
14680 if (file_mips_gp32
>= 0)
14681 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14683 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14688 /* 'default' has traditionally been a no-op. Probably not very useful. */
14689 if (strcasecmp (cpu_string
, "default") == 0)
14692 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14693 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14696 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14700 /* Return the canonical processor information for ISA (a member of the
14701 ISA_MIPS* enumeration). */
14703 static const struct mips_cpu_info
*
14704 mips_cpu_info_from_isa (int isa
)
14708 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14709 if ((mips_cpu_info_table
[i
].flags
& MIPS_CPU_IS_ISA
)
14710 && isa
== mips_cpu_info_table
[i
].isa
)
14711 return (&mips_cpu_info_table
[i
]);
14716 static const struct mips_cpu_info
*
14717 mips_cpu_info_from_arch (int arch
)
14721 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14722 if (arch
== mips_cpu_info_table
[i
].cpu
)
14723 return (&mips_cpu_info_table
[i
]);
14729 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14733 fprintf (stream
, "%24s", "");
14738 fprintf (stream
, ", ");
14742 if (*col_p
+ strlen (string
) > 72)
14744 fprintf (stream
, "\n%24s", "");
14748 fprintf (stream
, "%s", string
);
14749 *col_p
+= strlen (string
);
14755 md_show_usage (FILE *stream
)
14760 fprintf (stream
, _("\
14762 -EB generate big endian output\n\
14763 -EL generate little endian output\n\
14764 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14765 -G NUM allow referencing objects up to NUM bytes\n\
14766 implicitly with the gp register [default 8]\n"));
14767 fprintf (stream
, _("\
14768 -mips1 generate MIPS ISA I instructions\n\
14769 -mips2 generate MIPS ISA II instructions\n\
14770 -mips3 generate MIPS ISA III instructions\n\
14771 -mips4 generate MIPS ISA IV instructions\n\
14772 -mips5 generate MIPS ISA V instructions\n\
14773 -mips32 generate MIPS32 ISA instructions\n\
14774 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14775 -mips64 generate MIPS64 ISA instructions\n\
14776 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14777 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14781 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14782 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14783 show (stream
, "from-abi", &column
, &first
);
14784 fputc ('\n', stream
);
14786 fprintf (stream
, _("\
14787 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14788 -no-mCPU don't generate code specific to CPU.\n\
14789 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14793 show (stream
, "3900", &column
, &first
);
14794 show (stream
, "4010", &column
, &first
);
14795 show (stream
, "4100", &column
, &first
);
14796 show (stream
, "4650", &column
, &first
);
14797 fputc ('\n', stream
);
14799 fprintf (stream
, _("\
14800 -mips16 generate mips16 instructions\n\
14801 -no-mips16 do not generate mips16 instructions\n"));
14802 fprintf (stream
, _("\
14803 -msmartmips generate smartmips instructions\n\
14804 -mno-smartmips do not generate smartmips instructions\n"));
14805 fprintf (stream
, _("\
14806 -mdsp generate DSP instructions\n\
14807 -mno-dsp do not generate DSP instructions\n"));
14808 fprintf (stream
, _("\
14809 -mmt generate MT instructions\n\
14810 -mno-mt do not generate MT instructions\n"));
14811 fprintf (stream
, _("\
14812 -mfix-vr4120 work around certain VR4120 errata\n\
14813 -mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14814 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14815 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14816 -mno-shared optimize output for executables\n\
14817 -msym32 assume all symbols have 32-bit values\n\
14818 -O0 remove unneeded NOPs, do not swap branches\n\
14819 -O remove unneeded NOPs and swap branches\n\
14820 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14821 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14822 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14824 fprintf (stream
, _("\
14825 -KPIC, -call_shared generate SVR4 position independent code\n\
14826 -non_shared do not generate position independent code\n\
14827 -xgot assume a 32 bit GOT\n\
14828 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14829 -mshared, -mno-shared disable/enable .cpload optimization for\n\
14831 -mabi=ABI create ABI conformant object file for:\n"));
14835 show (stream
, "32", &column
, &first
);
14836 show (stream
, "o64", &column
, &first
);
14837 show (stream
, "n32", &column
, &first
);
14838 show (stream
, "64", &column
, &first
);
14839 show (stream
, "eabi", &column
, &first
);
14841 fputc ('\n', stream
);
14843 fprintf (stream
, _("\
14844 -32 create o32 ABI object file (default)\n\
14845 -n32 create n32 ABI object file\n\
14846 -64 create 64 ABI object file\n"));
14851 mips_dwarf2_format (void)
14853 if (mips_abi
== N64_ABI
)
14856 return dwarf2_format_64bit_irix
;
14858 return dwarf2_format_64bit
;
14862 return dwarf2_format_32bit
;
14866 mips_dwarf2_addr_size (void)
14868 if (mips_abi
== N64_ABI
)
14874 /* Standard calling conventions leave the CFA at SP on entry. */
14876 mips_cfi_frame_initial_instructions (void)
14878 cfi_add_CFA_def_cfa_register (SP
);
14882 tc_mips_regname_to_dw2regnum (char *regname
)
14884 unsigned int regnum
= -1;
14887 if (reg_lookup (®name
, RTYPE_GP
| RTYPE_NUM
, ®
))