1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* These variables are filled in with the masks of registers used.
94 The object format code reads them and puts them in the appropriate
96 unsigned long mips_gprmask
;
97 unsigned long mips_cprmask
[4];
99 /* MIPS ISA (Instruction Set Architecture) level. */
100 static int mips_isa
= -1;
102 /* MIPS PIC level. 0 is normal, non-PIC code. 2 means to generate
103 SVR4 ABI PIC calls. 1 doesn't mean anything. */
106 static int mips_warn_about_macros
;
107 static int mips_noreorder
;
108 static int mips_any_noreorder
;
109 static int mips_nomove
;
110 static int mips_noat
;
111 static int mips_nobopt
;
114 /* The size of the small data section. */
115 static int g_switch_value
= 8;
116 /* Whether the -G option was used. */
117 static int g_switch_seen
= 0;
123 /* handle of the OPCODE hash table */
124 static struct hash_control
*op_hash
= NULL
;
126 /* This array holds the chars that always start a comment. If the
127 pre-processor is disabled, these aren't very useful */
128 const char comment_chars
[] = "#";
130 /* This array holds the chars that only start a comment at the beginning of
131 a line. If the line seems to have the form '# 123 filename'
132 .line and .file directives will appear in the pre-processed output */
133 /* Note that input_file.c hand checks for '#' at the beginning of the
134 first line of the input file. This is because the compiler outputs
135 #NO_APP at the beginning of its output. */
136 /* Also note that C style comments are always supported. */
137 const char line_comment_chars
[] = "#";
139 /* This array holds machine specific line separator characters. */
140 const char line_separator_chars
[] = "";
142 /* Chars that can be used to separate mant from exp in floating point nums */
143 const char EXP_CHARS
[] = "eE";
145 /* Chars that mean this number is a floating point constant */
148 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
150 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
151 changed in read.c . Ideally it shouldn't have to know about it at all,
152 but nothing is ideal around here.
155 static char *insn_error
;
157 static int byte_order
= BYTE_ORDER
;
159 static int auto_align
= 1;
161 /* Symbol labelling the current insn. */
162 static symbolS
*insn_label
;
164 /* When outputting SVR4 PIC code, the assembler needs to know the
165 offset in the stack frame from which to restore the $gp register.
166 This is set by the .cprestore pseudo-op, and saved in this
168 static offsetT mips_cprestore_offset
= -1;
170 /* This is the register which holds the stack frame, as set by the
171 .frame pseudo-op. This is needed to implement .cprestore. */
172 static int mips_frame_reg
= SP
;
174 /* To output NOP instructions correctly, we need to keep information
175 about the previous two instructions. */
177 /* Whether we are optimizing. The default value of 2 means to remove
178 unneeded NOPs and swap branch instructions when possible. A value
179 of 1 means to not swap branches. A value of 0 means to always
181 static int mips_optimize
= 2;
183 /* The previous instruction. */
184 static struct mips_cl_insn prev_insn
;
186 /* The instruction before prev_insn. */
187 static struct mips_cl_insn prev_prev_insn
;
189 /* If we don't want information for prev_insn or prev_prev_insn, we
190 point the insn_mo field at this dummy integer. */
191 static const struct mips_opcode dummy_opcode
= { 0 };
193 /* Non-zero if prev_insn is valid. */
194 static int prev_insn_valid
;
196 /* The frag for the previous instruction. */
197 static struct frag
*prev_insn_frag
;
199 /* The offset into prev_insn_frag for the previous instruction. */
200 static long prev_insn_where
;
202 /* The reloc for the previous instruction, if any. */
203 static fixS
*prev_insn_fixp
;
205 /* Non-zero if the previous instruction was in a delay slot. */
206 static int prev_insn_is_delay_slot
;
208 /* Non-zero if the previous instruction was in a .set noreorder. */
209 static int prev_insn_unreordered
;
211 /* Non-zero if the previous previous instruction was in a .set
213 static int prev_prev_insn_unreordered
;
215 /* Since the MIPS does not have multiple forms of PC relative
216 instructions, we do not have to do relaxing as is done on other
217 platforms. However, we do have to handle GP relative addressing
218 correctly, which turns out to be a similar problem.
220 Every macro that refers to a symbol can occur in (at least) two
221 forms, one with GP relative addressing and one without. For
222 example, loading a global variable into a register generally uses
223 an macroinstruction like this:
225 If i can be addressed off the GP register (this is true if it is in
226 the .sbss or .sdata section, or if it is known to be smaller than
227 the -G argument) this will generate the following instruction:
229 This instruction will use a GPREL reloc. If i can not be addressed
230 off the GP register, the following instruction sequence will be used:
233 In this case the first instruction will have a HI16 reloc, and the
234 second reloc will have a LO16 reloc. Both relocs will be against
237 The issue here is that we may not know whether i is GP addressable
238 until after we see the instruction that uses it. Therefore, we
239 want to be able to choose the final instruction sequence only at
240 the end of the assembly. This is similar to the way other
241 platforms choose the form of a PC relative instruction only at the
244 When generating position independent code we do not use GP
245 addressing in the same way, but the issue still arises as external
246 symbols and local symbols must be handled differently.
248 We handle these issues by actually generating both possible
249 instruction sequences. The longer one is put in a frag_var with
250 type rs_machine_dependent. We encode what to do with the frag in
251 the subtype field. We encode (1) the number of existing bytes to
252 replace, (2) the number of new bytes to use, (3) the offset from
253 the start of the existing bytes to the first reloc we must generate
254 (that is, the offset is applied from the start of the existing
255 bytes after they are replaced by the new bytes, if any), (4) the
256 offset from the start of the existing bytes to the second reloc,
257 (5) whether a third reloc is needed (the third reloc is always four
258 bytes after the second reloc), and (6) whether to warn if this
259 variant is used (this is sometimes needed if .set nomacro or .set
260 noat is in effect). All these numbers are reasonably small.
262 Generating two instruction sequences must be handled carefully to
263 ensure that delay slots are handled correctly. Fortunately, the
264 issue only arises in a restricted number of cases. When the second
265 instruction sequence is generated, append_insn is directed to
266 maintain the existing delay slot information, so it continues to
267 apply to any code after the second instruction sequence. This
268 means that the second instruction sequence must not impose any
269 requirements not required by the first instruction sequence.
271 These variant frags are then handled in functions called by the
272 machine independent code. md_estimate_size_before_relax returns
273 the final size of the frag. md_convert_frag sets up the final form
274 of the frag. tc_gen_reloc adjust the first reloc and adds a second
276 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
280 | (((reloc1) + 64) << 9) \
281 | (((reloc2) + 64) << 2) \
282 | ((reloc3) ? (1 << 1) : 0) \
284 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
285 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
286 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
287 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
288 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
289 #define RELAX_WARN(i) ((i) & 1)
291 /* Prototypes for static functions. */
294 #define internalError() \
295 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
297 #define internalError() as_fatal ("MIPS internal Error");
300 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
301 unsigned int reg
, int fpr
));
302 static void append_insn
PARAMS ((char *place
,
303 struct mips_cl_insn
* ip
,
305 bfd_reloc_code_real_type r
));
306 static void mips_no_prev_insn
PARAMS ((void));
307 static void mips_emit_delays
PARAMS ((void));
308 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
309 const char *name
, const char *fmt
,
311 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
312 expressionS
* ep
, int regnum
));
313 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
314 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
316 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
317 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
318 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
319 #ifdef LOSING_COMPILER
320 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
322 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
323 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
324 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
325 static symbolS
*get_symbol
PARAMS ((void));
326 static void mips_align
PARAMS ((int to
, int fill
));
327 static void s_align
PARAMS ((int));
328 static void s_stringer
PARAMS ((int));
329 static void s_change_sec
PARAMS ((int));
330 static void s_cons
PARAMS ((int));
331 static void s_err
PARAMS ((int));
332 static void s_extern
PARAMS ((int));
333 static void s_float_cons
PARAMS ((int));
334 static void s_option
PARAMS ((int));
335 static void s_mipsset
PARAMS ((int));
336 static void s_mips_space
PARAMS ((int));
337 static void s_abicalls
PARAMS ((int));
338 static void s_cpload
PARAMS ((int));
339 static void s_cprestore
PARAMS ((int));
340 static void s_gpword
PARAMS ((int));
341 static void s_cpadd
PARAMS ((int));
342 #ifndef ECOFF_DEBUGGING
343 static void md_obj_begin
PARAMS ((void));
344 static void md_obj_end
PARAMS ((void));
345 static long get_number
PARAMS ((void));
346 static void s_ent
PARAMS ((int));
347 static void s_mipsend
PARAMS ((int));
348 static void s_file
PARAMS ((int));
350 static void s_frame
PARAMS ((int));
351 static void s_loc
PARAMS ((int));
352 static void s_mask
PARAMS ((char));
358 The following pseudo-ops from the Kane and Heinrich MIPS book
359 should be defined here, but are currently unsupported: .alias,
360 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
362 The following pseudo-ops from the Kane and Heinrich MIPS book are
363 specific to the type of debugging information being generated, and
364 should be defined by the object format: .aent, .begin, .bend,
365 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
368 The following pseudo-ops from the Kane and Heinrich MIPS book are
369 not MIPS CPU specific, but are also not specific to the object file
370 format. This file is probably the best place to define them, but
371 they are not currently supported: .asm0, .endr, .lab, .repeat,
372 .struct, .weakext. */
374 const pseudo_typeS md_pseudo_table
[] =
376 /* MIPS specific pseudo-ops. */
377 {"option", s_option
, 0},
378 {"set", s_mipsset
, 0},
379 {"rdata", s_change_sec
, 'r'},
380 {"sdata", s_change_sec
, 's'},
381 {"livereg", s_ignore
, 0},
382 { "abicalls", s_abicalls
, 0},
383 { "cpload", s_cpload
, 0},
384 { "cprestore", s_cprestore
, 0},
385 { "gpword", s_gpword
, 0},
386 { "cpadd", s_cpadd
, 0},
388 /* Relatively generic pseudo-ops that happen to be used on MIPS
390 {"asciiz", s_stringer
, 1},
391 {"bss", s_change_sec
, 'b'},
394 {"dword", s_cons
, 3},
396 /* These pseudo-ops are defined in read.c, but must be overridden
397 here for one reason or another. */
398 {"align", s_align
, 0},
399 {"ascii", s_stringer
, 0},
400 {"asciz", s_stringer
, 1},
402 {"data", s_change_sec
, 'd'},
403 {"double", s_float_cons
, 'd'},
404 {"extern", s_extern
, 0},
405 {"float", s_float_cons
, 'f'},
406 {"hword", s_cons
, 1},
411 {"short", s_cons
, 1},
412 {"single", s_float_cons
, 'f'},
413 {"space", s_mips_space
, 0},
414 {"text", s_change_sec
, 't'},
417 #ifndef ECOFF_DEBUGGING
418 /* These pseudo-ops should be defined by the object file format.
419 However, a.out doesn't support them, so we have versions here. */
421 {"bgnb", s_ignore
, 0},
422 {"end", s_mipsend
, 0},
423 {"endb", s_ignore
, 0},
426 {"fmask", s_ignore
, 'F'},
427 {"frame", s_ignore
, 0},
428 {"loc", s_ignore
, 0},
429 {"mask", s_ignore
, 'R'},
430 {"verstamp", s_ignore
, 0},
437 const relax_typeS md_relax_table
[] =
442 static char *expr_end
;
444 static expressionS imm_expr
;
445 static expressionS offset_expr
;
446 static bfd_reloc_code_real_type imm_reloc
;
447 static bfd_reloc_code_real_type offset_reloc
;
449 /* FIXME: This should be handled in a different way. */
450 extern int target_big_endian
;
453 * This function is called once, at assembler startup time. It should
454 * set up all the tables, etc. that the MD part of the assembler will need.
460 register const char *retval
= NULL
;
461 register unsigned int i
= 0;
465 if (strcmp (TARGET_CPU
, "mips") == 0)
467 else if (strcmp (TARGET_CPU
, "r6000") == 0
468 || strcmp (TARGET_CPU
, "mips2") == 0)
470 else if (strcmp (TARGET_CPU
, "mips64") == 0
471 || strcmp (TARGET_CPU
, "r4000") == 0
472 || strcmp (TARGET_CPU
, "mips3") == 0)
481 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
484 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
487 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
491 as_warn ("Could not set architecture and machine");
493 op_hash
= hash_new ();
495 for (i
= 0; i
< NUMOPCODES
;)
497 const char *name
= mips_opcodes
[i
].name
;
499 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
502 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
503 mips_opcodes
[i
].name
, retval
);
504 as_fatal ("Broken assembler. No assembly attempted.");
508 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
509 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
510 != mips_opcodes
[i
].match
))
512 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
513 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
514 as_fatal ("Broken assembler. No assembly attempted.");
518 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
521 mips_no_prev_insn ();
529 /* set the default alignment for the text section (2**2) */
530 record_alignment (text_section
, 2);
532 /* FIXME: This should be handled in a different way. */
533 target_big_endian
= byte_order
== BIG_ENDIAN
;
536 bfd_set_gp_size (stdoutput
, g_switch_value
);
540 /* Sections must be aligned to 16 byte boundaries. */
541 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
542 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
543 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
545 /* Create a .reginfo section for register masks and a .mdebug
546 section for debugging information. */
554 sec
= subseg_new (".reginfo", (subsegT
) 0);
556 /* The ABI says this section should be loaded so that the running
557 program can access it. */
558 (void) bfd_set_section_flags (stdoutput
, sec
,
559 (SEC_ALLOC
| SEC_LOAD
560 | SEC_READONLY
| SEC_DATA
));
561 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
563 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
565 #ifdef ECOFF_DEBUGGING
566 sec
= subseg_new (".mdebug", (subsegT
) 0);
567 (void) bfd_set_section_flags (stdoutput
, sec
,
568 SEC_HAS_CONTENTS
| SEC_READONLY
);
569 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
572 subseg_set (seg
, subseg
);
576 #ifndef ECOFF_DEBUGGING
584 #ifndef ECOFF_DEBUGGING
593 struct mips_cl_insn insn
;
595 imm_expr
.X_op
= O_absent
;
596 offset_expr
.X_op
= O_absent
;
598 mips_ip (str
, &insn
);
601 as_bad ("%s `%s'", insn_error
, str
);
604 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
610 if (imm_expr
.X_op
!= O_absent
)
611 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
612 else if (offset_expr
.X_op
!= O_absent
)
613 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
615 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
619 /* See whether instruction IP reads register REG. If FPR is non-zero,
620 REG is a floating point register. */
623 insn_uses_reg (ip
, reg
, fpr
)
624 struct mips_cl_insn
*ip
;
628 /* Don't report on general register 0, since it never changes. */
629 if (! fpr
&& reg
== 0)
634 /* If we are called with either $f0 or $f1, we must check $f0.
635 This is not optimal, because it will introduce an unnecessary
636 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
637 need to distinguish reading both $f0 and $f1 or just one of
638 them. Note that we don't have to check the other way,
639 because there is no instruction that sets both $f0 and $f1
640 and requires a delay. */
641 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
642 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
643 == (reg
&~ (unsigned) 1)))
645 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
646 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
647 == (reg
&~ (unsigned) 1)))
652 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
653 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
655 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
656 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
663 /* Output an instruction. PLACE is where to put the instruction; if
664 it is NULL, this uses frag_more to get room. IP is the instruction
665 information. ADDRESS_EXPR is an operand of the instruction to be
666 used with RELOC_TYPE. */
669 append_insn (place
, ip
, address_expr
, reloc_type
)
671 struct mips_cl_insn
*ip
;
672 expressionS
*address_expr
;
673 bfd_reloc_code_real_type reloc_type
;
675 register unsigned long prev_pinfo
, pinfo
;
680 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
681 pinfo
= ip
->insn_mo
->pinfo
;
683 if (place
== NULL
&& ! mips_noreorder
)
685 /* If the previous insn required any delay slots, see if we need
686 to insert a NOP or two. There are eight kinds of possible
687 hazards, of which an instruction can have at most one type.
688 (1) a load from memory delay
689 (2) a load from a coprocessor delay
690 (3) an unconditional branch delay
691 (4) a conditional branch delay
692 (5) a move to coprocessor register delay
693 (6) a load coprocessor register from memory delay
694 (7) a coprocessor condition code delay
695 (8) a HI/LO special register delay
697 There are a lot of optimizations we could do that we don't.
698 In particular, we do not, in general, reorder instructions.
699 If you use gcc with optimization, it will reorder
700 instructions and generally do much more optimization then we
701 do here; repeating all that work in the assembler would only
702 benefit hand written assembly code, and does not seem worth
705 /* This is how a NOP is emitted. */
706 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
708 /* The previous insn might require a delay slot, depending upon
709 the contents of the current insn. */
710 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
712 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
714 /* A load from a coprocessor or from memory. All load
715 delays delay the use of general register rt for one
716 instruction on the r3000. The r6000 and r4000 use
718 know (prev_pinfo
& INSN_WRITE_GPR_T
);
719 if (mips_optimize
== 0
720 || insn_uses_reg (ip
,
721 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
726 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
728 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
730 /* A generic coprocessor delay. The previous instruction
731 modified a coprocessor general or control register. If
732 it modified a control register, we need to avoid any
733 coprocessor instruction (this is probably not always
734 required, but it sometimes is). If it modified a general
735 register, we avoid using that register.
737 On the r6000 and r4000 loading a coprocessor register
738 from memory is interlocked, and does not require a delay.
740 This case is not handled very well. There is no special
741 knowledge of CP0 handling, and the coprocessors other
742 than the floating point unit are not distinguished at
744 if (prev_pinfo
& INSN_WRITE_FPR_T
)
746 if (mips_optimize
== 0
747 || insn_uses_reg (ip
,
748 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
753 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
755 if (mips_optimize
== 0
756 || insn_uses_reg (ip
,
757 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
764 /* We don't know exactly what the previous instruction
765 does. If the current instruction uses a coprocessor
766 register, we must insert a NOP. If previous
767 instruction may set the condition codes, and the
768 current instruction uses them, we must insert two
770 if (mips_optimize
== 0
771 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
772 && (pinfo
& INSN_READ_COND_CODE
)))
774 else if (pinfo
& INSN_COP
)
778 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
780 /* The previous instruction sets the coprocessor condition
781 codes, but does not require a general coprocessor delay
782 (this means it is a floating point comparison
783 instruction). If this instruction uses the condition
784 codes, we need to insert a single NOP. */
785 if (mips_optimize
== 0
786 || (pinfo
& INSN_READ_COND_CODE
))
789 else if (prev_pinfo
& INSN_READ_LO
)
791 /* The previous instruction reads the LO register; if the
792 current instruction writes to the LO register, we must
794 if (mips_optimize
== 0
795 || (pinfo
& INSN_WRITE_LO
))
798 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
800 /* The previous instruction reads the HI register; if the
801 current instruction writes to the HI register, we must
803 if (mips_optimize
== 0
804 || (pinfo
& INSN_WRITE_HI
))
808 /* There are two cases which require two intervening
809 instructions: 1) setting the condition codes using a move to
810 coprocessor instruction which requires a general coprocessor
811 delay and then reading the condition codes 2) reading the HI
812 or LO register and then writing to it. If we are not already
813 emitting a NOP instruction, we must check for these cases
814 compared to the instruction previous to the previous
817 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
818 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
819 && (pinfo
& INSN_READ_COND_CODE
))
820 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
821 && (pinfo
& INSN_WRITE_LO
))
822 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
823 && (pinfo
& INSN_WRITE_HI
))))
826 /* If we are being given a nop instruction, don't bother with
827 one of the nops we would otherwise output. This will only
828 happen when a nop instruction is used with mips_optimize set
830 if (nops
> 0 && ip
->insn_opcode
== 0)
833 /* Now emit the right number of NOP instructions. */
840 listing_prev_line ();
841 if (insn_label
!= NULL
)
843 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
844 insn_label
->sy_frag
= frag_now
;
845 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
855 if (address_expr
!= NULL
)
857 if (address_expr
->X_op
== O_constant
)
862 ip
->insn_opcode
|= address_expr
->X_add_number
;
866 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
869 case BFD_RELOC_MIPS_JMP
:
870 case BFD_RELOC_16_PCREL_S2
:
879 assert (reloc_type
!= BFD_RELOC_UNUSED
);
881 /* Don't generate a reloc if we are writing into a variant
884 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
886 reloc_type
== BFD_RELOC_16_PCREL_S2
,
891 md_number_to_chars (f
, ip
->insn_opcode
, 4);
893 /* Update the register mask information. */
894 if (pinfo
& INSN_WRITE_GPR_D
)
895 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
896 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
897 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
898 if (pinfo
& INSN_READ_GPR_S
)
899 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
900 if (pinfo
& INSN_WRITE_GPR_31
)
901 mips_gprmask
|= 1 << 31;
902 if (pinfo
& INSN_WRITE_FPR_D
)
903 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
904 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
905 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
906 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
907 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
908 if (pinfo
& INSN_COP
)
910 /* We don't keep enough information to sort these cases out. */
912 /* Never set the bit for $0, which is always zero. */
913 mips_gprmask
&=~ 1 << 0;
915 if (place
== NULL
&& ! mips_noreorder
)
917 /* Filling the branch delay slot is more complex. We try to
918 switch the branch with the previous instruction, which we can
919 do if the previous instruction does not set up a condition
920 that the branch tests and if the branch is not itself the
921 target of any branch. */
922 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
923 || (pinfo
& INSN_COND_BRANCH_DELAY
))
925 if (mips_optimize
< 2
926 /* If we have seen .set nobopt, don't optimize. */
928 /* If we have seen .set volatile or .set nomove, don't
931 /* If we had to emit any NOP instructions, then we
932 already know we can not swap. */
934 /* If we don't even know the previous insn, we can not
937 /* If the previous insn is already in a branch delay
938 slot, then we can not swap. */
939 || prev_insn_is_delay_slot
940 /* If the previous previous insn was in a .set
941 noreorder, we can't swap. Actually, the MIPS
942 assembler will swap in this situation. However, gcc
943 configured -with-gnu-as will generate code like
949 in which we can not swap the bne and INSN. If gcc is
950 not configured -with-gnu-as, it does not output the
951 .set pseudo-ops. We don't have to check
952 prev_insn_unreordered, because prev_insn_valid will
953 be 0 in that case. We don't want to use
954 prev_prev_insn_valid, because we do want to be able
955 to swap at the start of a function. */
956 || prev_prev_insn_unreordered
957 /* If the branch is itself the target of a branch, we
958 can not swap. We cheat on this; all we check for is
959 whether there is a label on this instruction. If
960 there are any branches to anything other than a
961 label, users must use .set noreorder. */
962 || insn_label
!= NULL
963 /* If the previous instruction is in a variant frag, we
964 can not do the swap. */
965 || prev_insn_frag
->fr_type
== rs_machine_dependent
966 /* If the branch reads the condition codes, we don't
967 even try to swap, because in the sequence
972 we can not swap, and I don't feel like handling that
974 || (pinfo
& INSN_READ_COND_CODE
)
975 /* We can not swap with an instruction that requires a
976 delay slot, becase the target of the branch might
977 interfere with that instruction. */
979 & (INSN_LOAD_COPROC_DELAY
980 | INSN_COPROC_MOVE_DELAY
981 | INSN_WRITE_COND_CODE
986 & (INSN_LOAD_MEMORY_DELAY
987 | INSN_COPROC_MEMORY_DELAY
)))
988 /* We can not swap with a branch instruction. */
990 & (INSN_UNCOND_BRANCH_DELAY
991 | INSN_COND_BRANCH_DELAY
992 | INSN_COND_BRANCH_LIKELY
))
993 /* We do not swap with a trap instruction, since it
994 complicates trap handlers to have the trap
995 instruction be in a delay slot. */
996 || (prev_pinfo
& INSN_TRAP
)
997 /* If the branch reads a register that the previous
998 instruction sets, we can not swap. */
999 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1000 && insn_uses_reg (ip
,
1001 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1004 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1005 && insn_uses_reg (ip
,
1006 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1009 /* If the branch writes a register that the previous
1010 instruction sets, we can not swap (we know that
1011 branches write only to RD or to $31). */
1012 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1013 && (((pinfo
& INSN_WRITE_GPR_D
)
1014 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1015 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1016 || ((pinfo
& INSN_WRITE_GPR_31
)
1017 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1020 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1021 && (((pinfo
& INSN_WRITE_GPR_D
)
1022 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1023 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1024 || ((pinfo
& INSN_WRITE_GPR_31
)
1025 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1028 /* If the branch writes a register that the previous
1029 instruction reads, we can not swap (we know that
1030 branches only write to RD or to $31). */
1031 || ((pinfo
& INSN_WRITE_GPR_D
)
1032 && insn_uses_reg (&prev_insn
,
1033 ((ip
->insn_opcode
>> OP_SH_RD
)
1036 || ((pinfo
& INSN_WRITE_GPR_31
)
1037 && insn_uses_reg (&prev_insn
, 31, 0))
1038 /* If the previous previous instruction has a load
1039 delay, and sets a register that the branch reads, we
1041 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1043 && (prev_prev_insn
.insn_mo
->pinfo
1044 & INSN_LOAD_MEMORY_DELAY
)))
1045 && insn_uses_reg (ip
,
1046 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1050 /* We could do even better for unconditional branches to
1051 portions of this object file; we could pick up the
1052 instruction at the destination, put it in the delay
1053 slot, and bump the destination address. */
1055 /* Update the previous insn information. */
1056 prev_prev_insn
= *ip
;
1057 prev_insn
.insn_mo
= &dummy_opcode
;
1064 /* It looks like we can actually do the swap. */
1065 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1066 memcpy (temp
, prev_f
, 4);
1067 memcpy (prev_f
, f
, 4);
1068 memcpy (f
, temp
, 4);
1071 prev_insn_fixp
->fx_frag
= frag_now
;
1072 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1076 fixp
->fx_frag
= prev_insn_frag
;
1077 fixp
->fx_where
= prev_insn_where
;
1079 /* Update the previous insn information; leave prev_insn
1081 prev_prev_insn
= *ip
;
1083 prev_insn_is_delay_slot
= 1;
1085 /* If that was an unconditional branch, forget the previous
1086 insn information. */
1087 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1089 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1090 prev_insn
.insn_mo
= &dummy_opcode
;
1093 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1095 /* We don't yet optimize a branch likely. What we should do
1096 is look at the target, copy the instruction found there
1097 into the delay slot, and increment the branch to jump to
1098 the next instruction. */
1100 /* Update the previous insn information. */
1101 prev_prev_insn
= *ip
;
1102 prev_insn
.insn_mo
= &dummy_opcode
;
1106 /* Update the previous insn information. */
1108 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1110 prev_prev_insn
= prev_insn
;
1113 /* Any time we see a branch, we always fill the delay slot
1114 immediately; since this insn is not a branch, we know it
1115 is not in a delay slot. */
1116 prev_insn_is_delay_slot
= 0;
1119 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1120 prev_insn_unreordered
= 0;
1121 prev_insn_frag
= frag_now
;
1122 prev_insn_where
= f
- frag_now
->fr_literal
;
1123 prev_insn_fixp
= fixp
;
1124 prev_insn_valid
= 1;
1127 /* We just output an insn, so the next one doesn't have a label. */
1131 /* This function forgets that there was any previous instruction or
1135 mips_no_prev_insn ()
1137 prev_insn
.insn_mo
= &dummy_opcode
;
1138 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1139 prev_insn_valid
= 0;
1140 prev_insn_is_delay_slot
= 0;
1141 prev_insn_unreordered
= 0;
1142 prev_prev_insn_unreordered
= 0;
1146 /* This function must be called whenever we turn on noreorder or emit
1147 something other than instructions. It inserts any NOPS which might
1148 be needed by the previous instruction, and clears the information
1149 kept for the previous instructions. */
1154 if (! mips_noreorder
)
1159 if ((prev_insn
.insn_mo
->pinfo
1160 & (INSN_LOAD_COPROC_DELAY
1161 | INSN_COPROC_MOVE_DELAY
1162 | INSN_WRITE_COND_CODE
1166 && (prev_insn
.insn_mo
->pinfo
1167 & (INSN_LOAD_MEMORY_DELAY
1168 | INSN_COPROC_MEMORY_DELAY
))))
1171 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1172 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1173 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1176 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1177 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1178 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1183 if (insn_label
!= NULL
)
1185 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1186 insn_label
->sy_frag
= frag_now
;
1187 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1190 mips_no_prev_insn ();
1194 /* Build an instruction created by a macro expansion. This is passed
1195 a pointer to the count of instructions created so far, an
1196 expression, the name of the instruction to build, an operand format
1197 string, and corresponding arguments. */
1201 macro_build (char *place
,
1207 #else /* ! defined (NO_STDARG) */
1209 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1216 #endif /* ! defined (NO_STDARG) */
1218 struct mips_cl_insn insn
;
1219 bfd_reloc_code_real_type r
;
1223 va_start (args
, fmt
);
1229 * If the macro is about to expand into a second instruction,
1230 * print a warning if needed. We need to pass ip as a parameter
1231 * to generate a better warning message here...
1233 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1234 as_warn ("Macro instruction expanded into multiple instructions");
1237 *counter
+= 1; /* bump instruction counter */
1239 r
= BFD_RELOC_UNUSED
;
1240 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1241 assert (insn
.insn_mo
);
1242 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1244 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1245 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1248 assert (insn
.insn_mo
->name
);
1249 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1251 insn
.insn_opcode
= insn
.insn_mo
->match
;
1267 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1273 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1278 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1283 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1290 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1294 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1298 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1305 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1311 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1312 assert (r
== BFD_RELOC_MIPS_GPREL
1313 || r
== BFD_RELOC_MIPS_LITERAL
1314 || r
== BFD_RELOC_LO16
1315 || r
== BFD_RELOC_MIPS_GOT16
1316 || r
== BFD_RELOC_MIPS_CALL16
);
1320 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1321 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1326 assert (ep
!= NULL
);
1328 * This allows macro() to pass an immediate expression for
1329 * creating short branches without creating a symbol.
1330 * Note that the expression still might come from the assembly
1331 * input, in which case the value is not checked for range nor
1332 * is a relocation entry generated (yuck).
1334 if (ep
->X_op
== O_constant
)
1336 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1340 r
= BFD_RELOC_16_PCREL_S2
;
1344 assert (ep
!= NULL
);
1345 r
= BFD_RELOC_MIPS_JMP
;
1354 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1356 append_insn (place
, &insn
, ep
, r
);
1360 * Generate a "lui" instruction.
1363 macro_build_lui (place
, counter
, ep
, regnum
)
1369 expressionS high_expr
;
1370 struct mips_cl_insn insn
;
1371 bfd_reloc_code_real_type r
;
1372 CONST
char *name
= "lui";
1373 CONST
char *fmt
= "t,u";
1379 high_expr
.X_op
= O_constant
;
1380 high_expr
.X_add_number
= 0;
1383 if (high_expr
.X_op
== O_constant
)
1385 /* we can compute the instruction now without a relocation entry */
1386 if (high_expr
.X_add_number
& 0x8000)
1387 high_expr
.X_add_number
+= 0x10000;
1388 high_expr
.X_add_number
=
1389 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1390 r
= BFD_RELOC_UNUSED
;
1394 assert (ep
->X_op
== O_symbol
);
1395 /* _gp_disp is a special case, used from s_cpload. */
1396 assert (mips_pic
== 0
1397 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1398 r
= BFD_RELOC_HI16_S
;
1402 * If the macro is about to expand into a second instruction,
1403 * print a warning if needed. We need to pass ip as a parameter
1404 * to generate a better warning message here...
1406 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1407 as_warn ("Macro instruction expanded into multiple instructions");
1410 *counter
+= 1; /* bump instruction counter */
1412 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1413 assert (insn
.insn_mo
);
1414 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1415 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1417 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1418 if (r
== BFD_RELOC_UNUSED
)
1420 insn
.insn_opcode
|= high_expr
.X_add_number
;
1421 append_insn (place
, &insn
, NULL
, r
);
1424 append_insn (place
, &insn
, &high_expr
, r
);
1428 * Generates code to set the $at register to true (one)
1429 * if reg is less than the immediate expression.
1432 set_at (counter
, reg
, unsignedp
)
1437 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1438 macro_build ((char *) NULL
, counter
, &imm_expr
,
1439 unsignedp
? "sltiu" : "slti",
1440 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1443 load_register (counter
, AT
, &imm_expr
);
1444 macro_build ((char *) NULL
, counter
, NULL
,
1445 unsignedp
? "sltu" : "slt",
1446 "d,v,t", AT
, reg
, AT
);
1450 /* Warn if an expression is not a constant. */
1453 check_absolute_expr (ip
, ex
)
1454 struct mips_cl_insn
*ip
;
1457 if (ex
->X_op
!= O_constant
)
1458 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1462 * This routine generates the least number of instructions neccessary to load
1463 * an absolute expression value into a register.
1466 load_register (counter
, reg
, ep
)
1471 assert (ep
->X_op
== O_constant
);
1472 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1473 macro_build ((char *) NULL
, counter
, ep
,
1474 mips_isa
< 3 ? "addiu" : "daddiu",
1475 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1476 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1477 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1478 (int) BFD_RELOC_LO16
);
1479 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1480 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1481 == ~ (offsetT
) 0x7fffffff))
1483 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
);
1484 if ((ep
->X_add_number
& 0xffff) != 0)
1485 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1486 (int) BFD_RELOC_LO16
);
1488 else if (mips_isa
< 3)
1490 as_bad ("Number larger than 32 bits");
1491 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1492 (int) BFD_RELOC_LO16
);
1497 expressionS hi32
, lo32
;
1501 hi32
.X_add_number
>>= shift
;
1502 hi32
.X_add_number
&= 0xffffffff;
1503 if ((hi32
.X_add_number
& 0x80000000) != 0)
1504 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1505 load_register (counter
, reg
, &hi32
);
1507 lo32
.X_add_number
&= 0xffffffff;
1508 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1509 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1515 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1518 mid16
.X_add_number
>>= 16;
1519 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1520 reg
, (int) BFD_RELOC_LO16
);
1521 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1524 if ((lo32
.X_add_number
& 0xffff) != 0)
1525 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1526 (int) BFD_RELOC_LO16
);
1530 /* Load an address into a register. */
1533 load_address (counter
, reg
, ep
)
1540 if (ep
->X_op
!= O_constant
1541 && ep
->X_op
!= O_symbol
)
1543 as_bad ("expression too complex");
1544 ep
->X_op
= O_constant
;
1547 if (ep
->X_op
== O_constant
)
1548 load_register (counter
, reg
, ep
);
1549 else if (mips_pic
== 0)
1551 /* If this is a reference to a GP relative symbol, we want
1552 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1554 lui $reg,<sym> (BFD_RELOC_HI16_S)
1555 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1556 If we have an addend, we always use the latter form. */
1557 if (ep
->X_add_number
!= 0)
1562 macro_build ((char *) NULL
, counter
, ep
,
1563 mips_isa
< 3 ? "addiu" : "daddiu",
1564 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1565 p
= frag_var (rs_machine_dependent
, 8, 0,
1566 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1567 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1569 macro_build_lui (p
, counter
, ep
, reg
);
1572 macro_build (p
, counter
, ep
,
1573 mips_isa
< 3 ? "addiu" : "daddiu",
1574 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1580 /* If this is a reference to an external symbol, we want
1581 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1583 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1585 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1586 If there is a constant, it must be added in afterward. */
1587 ex
.X_add_number
= ep
->X_add_number
;
1588 ep
->X_add_number
= 0;
1590 macro_build ((char *) NULL
, counter
, ep
,
1591 mips_isa
< 3 ? "lw" : "ld",
1592 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1593 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1594 p
= frag_var (rs_machine_dependent
, 4, 0,
1595 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1596 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1597 macro_build (p
, counter
, ep
,
1598 mips_isa
< 3 ? "addiu" : "daddiu",
1599 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1600 if (ex
.X_add_number
!= 0)
1602 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1603 as_bad ("PIC code offset overflow (max 16 signed bits)");
1604 ex
.X_op
= O_constant
;
1605 macro_build (p
, counter
, &ex
,
1606 mips_isa
< 3 ? "addiu" : "daddiu",
1607 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1614 * This routine implements the seemingly endless macro or synthesized
1615 * instructions and addressing modes in the mips assembly language. Many
1616 * of these macros are simple and are similar to each other. These could
1617 * probably be handled by some kind of table or grammer aproach instead of
1618 * this verbose method. Others are not simple macros but are more like
1619 * optimizing code generation.
1620 * One interesting optimization is when several store macros appear
1621 * consecutivly that would load AT with the upper half of the same address.
1622 * The ensuing load upper instructions are ommited. This implies some kind
1623 * of global optimization. We currently only optimize within a single macro.
1624 * For many of the load and store macros if the address is specified as a
1625 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1626 * first load register 'at' with zero and use it as the base register. The
1627 * mips assembler simply uses register $zero. Just one tiny optimization
1632 struct mips_cl_insn
*ip
;
1634 register int treg
, sreg
, dreg
, breg
;
1647 bfd_reloc_code_real_type r
;
1650 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1651 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1652 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1653 mask
= ip
->insn_mo
->mask
;
1655 expr1
.X_op
= O_constant
;
1656 expr1
.X_op_symbol
= NULL
;
1657 expr1
.X_add_symbol
= NULL
;
1658 expr1
.X_add_number
= 1;
1670 mips_emit_delays ();
1672 mips_any_noreorder
= 1;
1674 expr1
.X_add_number
= 8;
1675 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1677 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1679 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1680 macro_build ((char *) NULL
, &icnt
, NULL
,
1681 dbl
? "dsub" : "sub",
1682 "d,v,t", dreg
, 0, sreg
);
1705 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1707 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1708 (int) BFD_RELOC_LO16
);
1711 load_register (&icnt
, AT
, &imm_expr
);
1712 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1731 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1733 if (mask
!= M_NOR_I
)
1734 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1735 sreg
, (int) BFD_RELOC_LO16
);
1738 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1739 treg
, sreg
, (int) BFD_RELOC_LO16
);
1740 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "nor", "d,v,t",
1746 load_register (&icnt
, AT
, &imm_expr
);
1747 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1764 if (imm_expr
.X_add_number
== 0)
1766 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1770 load_register (&icnt
, AT
, &imm_expr
);
1771 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1779 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1780 likely
? "bgezl" : "bgez",
1786 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1787 likely
? "blezl" : "blez",
1791 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1792 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1793 likely
? "beql" : "beq",
1800 /* check for > max integer */
1801 maxnum
= 0x7fffffff;
1809 if (imm_expr
.X_add_number
>= maxnum
)
1812 /* result is always false */
1815 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1816 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1820 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1821 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1826 imm_expr
.X_add_number
++;
1830 if (mask
== M_BGEL_I
)
1832 if (imm_expr
.X_add_number
== 0)
1834 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1835 likely
? "bgezl" : "bgez",
1839 if (imm_expr
.X_add_number
== 1)
1841 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1842 likely
? "bgtzl" : "bgtz",
1846 maxnum
= 0x7fffffff;
1854 maxnum
= - maxnum
- 1;
1855 if (imm_expr
.X_add_number
<= maxnum
)
1858 /* result is always true */
1859 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1860 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1863 set_at (&icnt
, sreg
, 0);
1864 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1865 likely
? "beql" : "beq",
1876 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1877 likely
? "beql" : "beq",
1881 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1884 likely
? "beql" : "beq",
1891 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1893 imm_expr
.X_add_number
++;
1897 if (mask
== M_BGEUL_I
)
1899 if (imm_expr
.X_add_number
== 0)
1901 if (imm_expr
.X_add_number
== 1)
1903 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1904 likely
? "bnel" : "bne",
1908 set_at (&icnt
, sreg
, 1);
1909 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1910 likely
? "beql" : "beq",
1919 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1920 likely
? "bgtzl" : "bgtz",
1926 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1927 likely
? "bltzl" : "bltz",
1931 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1933 likely
? "bnel" : "bne",
1942 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1943 likely
? "bnel" : "bne",
1949 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
1951 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1952 likely
? "bnel" : "bne",
1961 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1962 likely
? "blezl" : "blez",
1968 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1969 likely
? "bgezl" : "bgez",
1973 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1974 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1975 likely
? "beql" : "beq",
1982 maxnum
= 0x7fffffff;
1990 if (imm_expr
.X_add_number
>= maxnum
)
1992 imm_expr
.X_add_number
++;
1996 if (mask
== M_BLTL_I
)
1998 if (imm_expr
.X_add_number
== 0)
2000 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2001 likely
? "bltzl" : "bltz",
2005 if (imm_expr
.X_add_number
== 1)
2007 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2008 likely
? "blezl" : "blez",
2012 set_at (&icnt
, sreg
, 0);
2013 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2014 likely
? "bnel" : "bne",
2023 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2024 likely
? "beql" : "beq",
2030 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2032 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2033 likely
? "beql" : "beq",
2040 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2042 imm_expr
.X_add_number
++;
2046 if (mask
== M_BLTUL_I
)
2048 if (imm_expr
.X_add_number
== 0)
2050 if (imm_expr
.X_add_number
== 1)
2052 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2053 likely
? "beql" : "beq",
2057 set_at (&icnt
, sreg
, 1);
2058 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2059 likely
? "bnel" : "bne",
2068 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2069 likely
? "bltzl" : "bltz",
2075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2076 likely
? "bgtzl" : "bgtz",
2080 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2081 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2082 likely
? "bnel" : "bne",
2093 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2094 likely
? "bnel" : "bne",
2098 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2100 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2101 likely
? "bnel" : "bne",
2117 as_warn ("Divide by zero.");
2118 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2122 mips_emit_delays ();
2124 mips_any_noreorder
= 1;
2125 macro_build ((char *) NULL
, &icnt
, NULL
,
2126 dbl
? "ddiv" : "div",
2127 "z,s,t", sreg
, treg
);
2128 expr1
.X_add_number
= 8;
2129 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2130 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2131 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2132 expr1
.X_add_number
= -1;
2133 macro_build ((char *) NULL
, &icnt
, &expr1
,
2134 dbl
? "daddiu" : "addiu",
2135 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2136 expr1
.X_add_number
= dbl
? 20 : 16;
2137 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2140 expr1
.X_add_number
= 1;
2141 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2142 (int) BFD_RELOC_LO16
);
2143 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2148 expr1
.X_add_number
= 0x80000000;
2149 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
);
2151 expr1
.X_add_number
= 8;
2152 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2153 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2154 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2156 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2195 if (imm_expr
.X_add_number
== 0)
2197 as_warn ("Divide by zero.");
2198 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2201 if (imm_expr
.X_add_number
== 1)
2203 if (strcmp (s2
, "mflo") == 0)
2204 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2207 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2210 if (imm_expr
.X_add_number
== -1
2211 && s
[strlen (s
) - 1] != 'u')
2213 if (strcmp (s2
, "mflo") == 0)
2216 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2219 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2223 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2227 load_register (&icnt
, AT
, &imm_expr
);
2228 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2229 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2248 mips_emit_delays ();
2250 mips_any_noreorder
= 1;
2251 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2252 expr1
.X_add_number
= 8;
2253 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2254 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2255 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2257 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2261 /* Load the address of a symbol into a register. If M_LA_AB, we
2262 then add a base register to it. */
2263 if (offset_expr
.X_op
!= O_symbol
2264 && offset_expr
.X_op
!= O_constant
)
2266 as_bad ("expression too complex");
2267 offset_expr
.X_op
= O_constant
;
2281 if (offset_expr
.X_op
== O_constant
)
2282 load_register (&icnt
, tempreg
, &offset_expr
);
2283 else if (mips_pic
== 0)
2285 /* If this is a reference to an GP relative symbol, we want
2286 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2288 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2289 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2290 If we have a constant, we need two instructions anyhow,
2291 so we may as well always use the latter form. */
2292 if (offset_expr
.X_add_number
!= 0)
2297 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2298 mips_isa
< 3 ? "addiu" : "daddiu",
2299 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2300 p
= frag_var (rs_machine_dependent
, 8, 0,
2301 RELAX_ENCODE (4, 8, 0, 4, 0,
2302 mips_warn_about_macros
),
2303 offset_expr
.X_add_symbol
, (long) 0,
2306 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2309 macro_build (p
, &icnt
, &offset_expr
,
2310 mips_isa
< 3 ? "addiu" : "daddiu",
2311 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2315 /* If this is a reference to an external symbol, and there
2316 is no constant, we want
2317 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2318 For a local symbol, we want
2319 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2321 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2323 If we have a small constant, and this is a reference to
2324 an external symbol, we want
2325 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2327 addiu $tempreg,$tempreg,<constant>
2328 For a local symbol, we want the same instruction
2329 sequence, but we output a BFD_RELOC_LO16 reloc on the
2332 If we have a large constant, and this is a reference to
2333 an external symbol, we want
2334 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2335 lui $at,<hiconstant>
2336 addiu $at,$at,<loconstant>
2337 addu $tempreg,$tempreg,$at
2338 For a local symbol, we want the same instruction
2339 sequence, but we output a BFD_RELOC_LO16 reloc on the
2340 addiu instruction. */
2341 expr1
.X_add_number
= offset_expr
.X_add_number
;
2342 offset_expr
.X_add_number
= 0;
2344 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2345 mips_isa
< 3 ? "lw" : "ld",
2346 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2347 if (expr1
.X_add_number
== 0)
2355 /* We're going to put in an addu instruction using
2356 tempreg, so we may as well insert the nop right
2358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2362 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2363 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2365 ? mips_warn_about_macros
2367 offset_expr
.X_add_symbol
, (long) 0,
2371 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2374 macro_build (p
, &icnt
, &expr1
,
2375 mips_isa
< 3 ? "addiu" : "daddiu",
2376 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2377 /* FIXME: If breg == 0, and the next instruction uses
2378 $tempreg, then if this variant case is used an extra
2379 nop will be generated. */
2381 else if (expr1
.X_add_number
>= -0x8000
2382 && expr1
.X_add_number
< 0x8000)
2384 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2386 macro_build ((char *) NULL
, &icnt
, &expr1
,
2387 mips_isa
< 3 ? "addiu" : "daddiu",
2388 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2389 (void) frag_var (rs_machine_dependent
, 0, 0,
2390 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2391 offset_expr
.X_add_symbol
, (long) 0,
2398 /* If we are going to add in a base register, and the
2399 target register and the base register are the same,
2400 then we are using AT as a temporary register. Since
2401 we want to load the constant into AT, we add our
2402 current AT (from the global offset table) and the
2403 register into the register now, and pretend we were
2404 not using a base register. */
2409 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2411 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2412 mips_isa
< 3 ? "addu" : "daddu",
2413 "d,v,t", treg
, AT
, breg
);
2419 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2420 macro_build ((char *) NULL
, &icnt
, &expr1
,
2421 mips_isa
< 3 ? "addiu" : "daddiu",
2422 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2423 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2424 mips_isa
< 3 ? "addu" : "daddu",
2425 "d,v,t", tempreg
, tempreg
, AT
);
2426 (void) frag_var (rs_machine_dependent
, 0, 0,
2427 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2428 offset_expr
.X_add_symbol
, (long) 0,
2435 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2436 mips_isa
< 3 ? "addu" : "daddu",
2437 "d,v,t", treg
, tempreg
, breg
);
2445 /* The j instruction may not be used in PIC code, since it
2446 requires an absolute address. We convert it to a b
2449 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2451 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2454 /* The jal instructions must be handled as macros because when
2455 generating PIC code they expand to multi-instruction
2456 sequences. Normally they are simple instructions. */
2463 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2468 /* I only know how to handle pic2. */
2469 assert (mips_pic
== 2);
2471 if (sreg
!= PIC_CALL_REG
)
2472 as_warn ("MIPS PIC call to register other than $25");
2474 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "d,s",
2476 if (mips_cprestore_offset
< 0)
2477 as_warn ("No .cprestore pseudo-op used in PIC code");
2480 expr1
.X_add_number
= mips_cprestore_offset
;
2481 macro_build ((char *) NULL
, &icnt
, &expr1
,
2482 mips_isa
< 3 ? "lw" : "ld",
2483 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2490 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2494 /* I only know how to handle pic2. */
2495 assert (mips_pic
== 2);
2497 /* If this is a reference to an external symbol, we want
2498 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2502 lw $gp,cprestore($sp)
2503 The cprestore value is set using the .cprestore pseudo-op.
2504 If the symbol is not external, we want
2505 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2507 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2510 lw $gp,cprestore($sp)
2513 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2514 mips_isa
< 3 ? "lw" : "ld",
2515 "t,o(b)", PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL16
, GP
);
2516 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2517 p
= frag_var (rs_machine_dependent
, 4, 0,
2518 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2519 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2520 macro_build (p
, &icnt
, &offset_expr
,
2521 mips_isa
< 3 ? "addiu" : "daddiu",
2522 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2523 (int) BFD_RELOC_LO16
);
2524 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr", "s",
2526 if (mips_cprestore_offset
< 0)
2527 as_warn ("No .cprestore pseudo-op used in PIC code");
2531 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2533 expr1
.X_add_number
= mips_cprestore_offset
;
2534 macro_build ((char *) NULL
, &icnt
, &expr1
,
2535 mips_isa
< 3 ? "lw" : "ld",
2536 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2604 if (breg
== treg
|| coproc
)
2673 if (mask
== M_LWC1_AB
2674 || mask
== M_SWC1_AB
2675 || mask
== M_LDC1_AB
2676 || mask
== M_SDC1_AB
2685 if (offset_expr
.X_op
!= O_constant
2686 && offset_expr
.X_op
!= O_symbol
)
2688 as_bad ("expression too complex");
2689 offset_expr
.X_op
= O_constant
;
2692 /* A constant expression in PIC code can be handled just as it
2693 is in non PIC code. */
2695 || offset_expr
.X_op
== O_constant
)
2697 /* If this is a reference to a GP relative symbol, and there
2698 is no base register, we want
2699 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2701 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2702 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2703 If we have a constant, we need two instructions anyhow,
2704 so we always use the latter form.
2706 If we have a base register, and this is a reference to a
2707 GP relative symbol, we want
2708 addu $tempreg,$breg,$gp
2709 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2711 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2712 addu $tempreg,$tempreg,$breg
2713 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2714 With a constant we always use the latter case. */
2717 if (offset_expr
.X_add_number
!= 0)
2722 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2723 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2724 p
= frag_var (rs_machine_dependent
, 8, 0,
2725 RELAX_ENCODE (4, 8, 0, 4, 0,
2726 (mips_warn_about_macros
2727 || (used_at
&& mips_noat
))),
2728 offset_expr
.X_add_symbol
, (long) 0,
2732 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2735 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2736 (int) BFD_RELOC_LO16
, tempreg
);
2740 if (offset_expr
.X_add_number
!= 0)
2745 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2746 mips_isa
< 3 ? "addu" : "daddu",
2747 "d,v,t", tempreg
, breg
, GP
);
2748 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2749 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2750 p
= frag_var (rs_machine_dependent
, 12, 0,
2751 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2752 offset_expr
.X_add_symbol
, (long) 0,
2755 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2758 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2759 mips_isa
< 3 ? "addu" : "daddu",
2760 "d,v,t", tempreg
, tempreg
, breg
);
2763 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2764 (int) BFD_RELOC_LO16
, tempreg
);
2769 /* If this is a reference to an external symbol, we want
2770 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2772 <op> $treg,0($tempreg)
2774 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2776 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2777 <op> $treg,0($tempreg)
2778 If there is a base register, we add it to $tempreg before
2779 the <op>. If there is a constant, we stick it in the
2780 <op> instruction. We don't handle constants larger than
2781 16 bits, because we have no way to load the upper 16 bits
2782 (actually, we could handle them for the subset of cases
2783 in which we are not using $at). */
2784 assert (offset_expr
.X_op
== O_symbol
);
2785 expr1
.X_add_number
= offset_expr
.X_add_number
;
2786 offset_expr
.X_add_number
= 0;
2787 if (expr1
.X_add_number
< -0x8000
2788 || expr1
.X_add_number
>= 0x8000)
2789 as_bad ("PIC code offset overflow (max 16 signed bits)");
2791 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2792 mips_isa
< 3 ? "lw" : "ld",
2793 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2794 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2795 p
= frag_var (rs_machine_dependent
, 4, 0,
2796 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2797 offset_expr
.X_add_symbol
, (long) 0,
2799 macro_build (p
, &icnt
, &offset_expr
,
2800 mips_isa
< 3 ? "addiu" : "daddiu",
2801 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2803 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2804 mips_isa
< 3 ? "addu" : "daddu",
2805 "d,v,t", tempreg
, tempreg
, breg
);
2806 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2807 (int) BFD_RELOC_LO16
, tempreg
);
2817 load_register (&icnt
, treg
, &imm_expr
);
2823 assert (offset_expr
.X_op
== O_symbol
2824 && strcmp (segment_name (S_GET_SEGMENT
2825 (offset_expr
.X_add_symbol
)),
2827 && offset_expr
.X_add_number
== 0);
2828 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2829 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2833 assert (imm_expr
.X_op
== O_constant
);
2834 load_register (&icnt
, treg
, &imm_expr
);
2839 /* We know that sym is in the .rdata instruction. First we get
2840 the upper 16 bits of the address. */
2843 /* FIXME: This won't work for a 64 bit address. */
2844 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
2848 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2849 mips_isa
< 3 ? "lw" : "ld",
2850 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2852 /* Now we load the register(s). */
2854 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
2855 treg
, (int) BFD_RELOC_LO16
, AT
);
2858 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2859 treg
, (int) BFD_RELOC_LO16
, AT
);
2862 /* FIXME: How in the world do we deal with the possible
2864 offset_expr
.X_add_number
+= 4;
2865 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2866 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
2875 /* Load a floating point number from the .lit8 section. */
2876 assert (offset_expr
.X_op
== O_symbol
2877 && strcmp (segment_name (S_GET_SEGMENT
2878 (offset_expr
.X_add_symbol
)),
2880 && offset_expr
.X_add_number
== 0);
2883 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2884 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2888 r
= BFD_RELOC_MIPS_LITERAL
;
2893 /* Load the double from the .rdata section. */
2894 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2895 mips_isa
< 3 ? "lw" : "ld",
2896 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2899 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
2900 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
2909 /* Even on a big endian machine $fn comes before $fn+1. We have
2910 to adjust when loading from memory. */
2913 assert (mips_isa
< 2);
2914 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2915 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
2917 /* FIXME: A possible overflow which I don't know how to deal
2919 offset_expr
.X_add_number
+= 4;
2920 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2921 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
2929 * The MIPS assembler seems to check for X_add_number not
2930 * being double aligned and generating:
2933 * addiu at,at,%lo(foo+1)
2936 * But, the resulting address is the same after relocation so why
2937 * generate the extra instruction?
2984 if (offset_expr
.X_op
!= O_symbol
2985 && offset_expr
.X_op
!= O_constant
)
2987 as_bad ("expression too complex");
2988 offset_expr
.X_op
= O_constant
;
2991 /* Even on a big endian machine $fn comes before $fn+1. We have
2992 to adjust when loading from memory. We set coproc if we must
2993 load $fn+1 first. */
2994 if (byte_order
== LITTLE_ENDIAN
)
2998 || offset_expr
.X_op
== O_constant
)
3000 /* If this is a reference to a GP relative symbol, we want
3001 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3002 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3003 If we have a base register, we use this
3005 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3006 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3007 If this is not a GP relative symbol, we want
3008 lui $at,<sym> (BFD_RELOC_HI16_S)
3009 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3010 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3011 If there is a base register, we add it to $at after the
3012 lui instruction. If there is a constant, we always use
3014 if (offset_expr
.X_add_number
!= 0)
3033 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3034 mips_isa
< 3 ? "addu" : "daddu",
3035 "d,v,t", AT
, breg
, GP
);
3041 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3042 coproc
? treg
+ 1 : treg
,
3043 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3044 offset_expr
.X_add_number
+= 4;
3045 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3046 coproc
? treg
: treg
+ 1,
3047 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3048 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3049 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3050 used_at
&& mips_noat
),
3051 offset_expr
.X_add_symbol
, (long) 0,
3054 /* We just generated two relocs. When tc_gen_reloc
3055 handles this case, it will skip the first reloc and
3056 handle the second. The second reloc already has an
3057 extra addend of 4, which we added above. We must
3058 subtract it out, and then subtract another 4 to make
3059 the first reloc come out right. The second reloc
3060 will come out right because we are going to add 4 to
3061 offset_expr when we build its instruction below. */
3062 offset_expr
.X_add_number
-= 8;
3063 offset_expr
.X_op
= O_constant
;
3065 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3070 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3071 mips_isa
< 3 ? "addu" : "daddu",
3072 "d,v,t", AT
, breg
, AT
);
3076 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3077 coproc
? treg
+ 1 : treg
,
3078 (int) BFD_RELOC_LO16
, AT
);
3081 /* FIXME: How do we handle overflow here? */
3082 offset_expr
.X_add_number
+= 4;
3083 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3084 coproc
? treg
: treg
+ 1,
3085 (int) BFD_RELOC_LO16
, AT
);
3091 /* If this is a reference to an external symbol, we want
3092 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3097 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3099 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3100 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3101 If there is a base register we add it to $at before the
3102 lwc1 instructions. If there is a constant we include it
3103 in the lwc1 instructions. */
3105 expr1
.X_add_number
= offset_expr
.X_add_number
;
3106 offset_expr
.X_add_number
= 0;
3107 if (expr1
.X_add_number
< -0x8000
3108 || expr1
.X_add_number
>= 0x8000 - 4)
3109 as_bad ("PIC code offset overflow (max 16 signed bits)");
3114 frag_grow (16 + off
);
3115 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3116 mips_isa
< 3 ? "lw" : "ld",
3117 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3118 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3121 mips_isa
< 3 ? "addu" : "daddu",
3122 "d,v,t", AT
, breg
, AT
);
3123 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3124 coproc
? treg
+ 1 : treg
,
3125 (int) BFD_RELOC_LO16
, AT
);
3126 expr1
.X_add_number
+= 4;
3127 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3128 coproc
? treg
: treg
+ 1,
3129 (int) BFD_RELOC_LO16
, AT
);
3130 (void) frag_var (rs_machine_dependent
, 0, 0,
3131 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3132 offset_expr
.X_add_symbol
, (long) 0,
3147 assert (mips_isa
< 3);
3148 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3149 (int) BFD_RELOC_LO16
, breg
);
3150 offset_expr
.X_add_number
+= 4;
3151 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3152 (int) BFD_RELOC_LO16
, breg
);
3154 #ifdef LOSING_COMPILER
3160 as_warn ("Macro used $at after \".set noat\"");
3165 struct mips_cl_insn
*ip
;
3167 register int treg
, sreg
, dreg
, breg
;
3180 bfd_reloc_code_real_type r
;
3183 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3184 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3185 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3186 mask
= ip
->insn_mo
->mask
;
3188 expr1
.X_op
= O_constant
;
3189 expr1
.X_op_symbol
= NULL
;
3190 expr1
.X_add_symbol
= NULL
;
3191 expr1
.X_add_number
= 1;
3195 #endif /* LOSING_COMPILER */
3200 macro_build ((char *) NULL
, &icnt
, NULL
,
3201 dbl
? "dmultu" : "multu",
3203 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3209 /* The MIPS assembler some times generates shifts and adds. I'm
3210 not trying to be that fancy. GCC should do this for us
3212 load_register (&icnt
, AT
, &imm_expr
);
3213 macro_build ((char *) NULL
, &icnt
, NULL
,
3214 dbl
? "dmult" : "mult",
3216 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3222 mips_emit_delays ();
3224 mips_any_noreorder
= 1;
3225 macro_build ((char *) NULL
, &icnt
, NULL
,
3226 dbl
? "dmult" : "mult",
3228 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3229 macro_build ((char *) NULL
, &icnt
, NULL
,
3230 dbl
? "dsra32" : "sra",
3231 "d,w,<", dreg
, dreg
, 31);
3232 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3233 expr1
.X_add_number
= 8;
3234 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3235 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3236 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3238 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3244 mips_emit_delays ();
3246 mips_any_noreorder
= 1;
3247 macro_build ((char *) NULL
, &icnt
, NULL
,
3248 dbl
? "dmultu" : "multu",
3250 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3251 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3252 expr1
.X_add_number
= 8;
3253 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3254 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3255 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3260 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3261 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3262 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3264 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3268 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3269 imm_expr
.X_add_number
& 0x1f);
3270 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3271 (0 - imm_expr
.X_add_number
) & 0x1f);
3272 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3276 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3277 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3278 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3280 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3284 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3285 imm_expr
.X_add_number
& 0x1f);
3286 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3287 (0 - imm_expr
.X_add_number
) & 0x1f);
3288 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3292 assert (mips_isa
< 2);
3293 /* Even on a big endian machine $fn comes before $fn+1. We have
3294 to adjust when storing to memory. */
3295 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3296 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3297 (int) BFD_RELOC_LO16
, breg
);
3298 offset_expr
.X_add_number
+= 4;
3299 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3300 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3301 (int) BFD_RELOC_LO16
, breg
);
3306 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3307 treg
, (int) BFD_RELOC_LO16
);
3309 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3310 sreg
, (int) BFD_RELOC_LO16
);
3313 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3315 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3316 dreg
, (int) BFD_RELOC_LO16
);
3321 if (imm_expr
.X_add_number
== 0)
3323 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3324 sreg
, (int) BFD_RELOC_LO16
);
3329 as_warn ("Instruction %s: result is always false",
3331 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3334 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3336 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3337 sreg
, (int) BFD_RELOC_LO16
);
3340 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3342 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3343 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3344 mips_isa
< 3 ? "addiu" : "daddiu",
3345 "t,r,j", dreg
, sreg
,
3346 (int) BFD_RELOC_LO16
);
3351 load_register (&icnt
, AT
, &imm_expr
);
3352 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3356 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3357 (int) BFD_RELOC_LO16
);
3362 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3368 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3369 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3370 (int) BFD_RELOC_LO16
);
3373 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3375 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3377 macro_build ((char *) NULL
, &icnt
, &expr1
,
3378 mask
== M_SGE_I
? "slti" : "sltiu",
3379 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3384 load_register (&icnt
, AT
, &imm_expr
);
3385 macro_build ((char *) NULL
, &icnt
, NULL
,
3386 mask
== M_SGE_I
? "slt" : "sltu",
3387 "d,v,t", dreg
, sreg
, AT
);
3390 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3391 (int) BFD_RELOC_LO16
);
3396 case M_SGT
: /* sreg > treg <==> treg < sreg */
3402 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3405 case M_SGT_I
: /* sreg > I <==> I < sreg */
3411 load_register (&icnt
, AT
, &imm_expr
);
3412 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3415 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3421 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3422 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3423 (int) BFD_RELOC_LO16
);
3426 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3432 load_register (&icnt
, AT
, &imm_expr
);
3433 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3434 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3435 (int) BFD_RELOC_LO16
);
3439 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3441 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3442 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3445 load_register (&icnt
, AT
, &imm_expr
);
3446 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3450 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3452 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3453 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3456 load_register (&icnt
, AT
, &imm_expr
);
3457 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3463 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3466 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3470 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3472 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3478 if (imm_expr
.X_add_number
== 0)
3480 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3486 as_warn ("Instruction %s: result is always true",
3488 macro_build ((char *) NULL
, &icnt
, &expr1
,
3489 mips_isa
< 3 ? "addiu" : "daddiu",
3490 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3493 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3495 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3496 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3499 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3501 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3502 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3503 mips_isa
< 3 ? "addiu" : "daddiu",
3504 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3509 load_register (&icnt
, AT
, &imm_expr
);
3510 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3514 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3522 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3524 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3525 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3526 dbl
? "daddi" : "addi",
3527 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3530 load_register (&icnt
, AT
, &imm_expr
);
3531 macro_build ((char *) NULL
, &icnt
, NULL
,
3532 dbl
? "dsub" : "sub",
3533 "d,v,t", dreg
, sreg
, AT
);
3539 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3541 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3542 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3543 dbl
? "daddiu" : "addiu",
3544 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3547 load_register (&icnt
, AT
, &imm_expr
);
3548 macro_build ((char *) NULL
, &icnt
, NULL
,
3549 dbl
? "dsubu" : "subu",
3550 "d,v,t", dreg
, sreg
, AT
);
3571 load_register (&icnt
, AT
, &imm_expr
);
3572 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3577 assert (mips_isa
< 2);
3578 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3579 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3582 * Is the double cfc1 instruction a bug in the mips assembler;
3583 * or is there a reason for it?
3585 mips_emit_delays ();
3587 mips_any_noreorder
= 1;
3588 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3589 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3590 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3591 expr1
.X_add_number
= 3;
3592 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3593 (int) BFD_RELOC_LO16
);
3594 expr1
.X_add_number
= 2;
3595 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3596 (int) BFD_RELOC_LO16
);
3597 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3598 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3599 macro_build ((char *) NULL
, &icnt
, NULL
,
3600 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3601 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3602 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3612 /* avoid load delay */
3613 offset_expr
.X_add_number
+= 1;
3614 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3615 (int) BFD_RELOC_LO16
, breg
);
3616 offset_expr
.X_add_number
-= 1;
3617 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3618 (int) BFD_RELOC_LO16
, breg
);
3619 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3620 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3624 /* does this work on a big endian machine? */
3625 offset_expr
.X_add_number
+= 3;
3626 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3627 (int) BFD_RELOC_LO16
, breg
);
3628 offset_expr
.X_add_number
-= 3;
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3630 (int) BFD_RELOC_LO16
, breg
);
3636 load_address (&icnt
, AT
, &offset_expr
);
3637 if (mask
== M_ULW_A
)
3639 expr1
.X_add_number
= 3;
3640 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3641 (int) BFD_RELOC_LO16
, AT
);
3642 expr1
.X_add_number
= 0;
3643 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3644 (int) BFD_RELOC_LO16
, AT
);
3648 macro_build ((char *) NULL
, &icnt
, &expr1
,
3649 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3650 (int) BFD_RELOC_LO16
, AT
);
3651 expr1
.X_add_number
= 0;
3652 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3653 (int) BFD_RELOC_LO16
, AT
);
3654 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3656 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3662 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3663 (int) BFD_RELOC_LO16
, breg
);
3664 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3665 offset_expr
.X_add_number
+= 1;
3666 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3667 (int) BFD_RELOC_LO16
, breg
);
3671 offset_expr
.X_add_number
+= 3;
3672 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3673 (int) BFD_RELOC_LO16
, breg
);
3674 offset_expr
.X_add_number
-= 3;
3675 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3676 (int) BFD_RELOC_LO16
, breg
);
3681 load_address (&icnt
, AT
, &offset_expr
);
3682 if (mask
== M_USW_A
)
3684 expr1
.X_add_number
= 3;
3685 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3686 (int) BFD_RELOC_LO16
, AT
);
3687 expr1
.X_add_number
= 0;
3688 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3689 (int) BFD_RELOC_LO16
, AT
);
3693 expr1
.X_add_number
= 0;
3694 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3695 (int) BFD_RELOC_LO16
, AT
);
3696 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3698 expr1
.X_add_number
= 1;
3699 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3700 (int) BFD_RELOC_LO16
, AT
);
3701 expr1
.X_add_number
= 0;
3702 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3703 (int) BFD_RELOC_LO16
, AT
);
3704 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3706 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3712 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3716 as_warn ("Macro used $at after \".set noat\"");
3721 This routine assembles an instruction into its binary format. As a side
3722 effect it sets one of the global variables imm_reloc or offset_reloc to the
3723 type of relocation to do if one of the operands is an address expression.
3728 struct mips_cl_insn
*ip
;
3733 struct mips_opcode
*insn
;
3736 unsigned int lastregno
= 0;
3741 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
3753 as_warn ("Unknown opcode: `%s'", str
);
3756 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
3758 as_warn ("`%s' not in hash table.", str
);
3759 insn_error
= "ERROR: Unrecognized opcode";
3767 assert (strcmp (insn
->name
, str
) == 0);
3769 if (insn
->pinfo
== INSN_MACRO
)
3770 insn_isa
= insn
->match
;
3771 else if (insn
->pinfo
& INSN_ISA2
)
3773 else if (insn
->pinfo
& INSN_ISA3
)
3778 if (insn_isa
> mips_isa
)
3780 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
3781 && strcmp (insn
->name
, insn
[1].name
) == 0)
3786 as_warn ("Instruction not supported on this processor");
3790 ip
->insn_opcode
= insn
->match
;
3791 for (args
= insn
->args
;; ++args
)
3797 case '\0': /* end of args */
3810 ip
->insn_opcode
|= lastregno
<< 21;
3815 ip
->insn_opcode
|= lastregno
<< 16;
3819 ip
->insn_opcode
|= lastregno
<< 11;
3825 /* handle optional base register.
3826 Either the base register is omitted or
3827 we must have a left paren. */
3828 /* this is dependent on the next operand specifier
3829 is a 'b' for base register */
3830 assert (args
[1] == 'b');
3834 case ')': /* these must match exactly */
3839 case '<': /* must be at least one digit */
3841 * According to the manual, if the shift amount is greater
3842 * than 31 or less than 0 the the shift amount should be
3843 * mod 32. In reality the mips assembler issues an error.
3844 * We issue a warning and mask out all but the low 5 bits.
3846 my_getExpression (&imm_expr
, s
);
3847 check_absolute_expr (ip
, &imm_expr
);
3848 if ((unsigned long) imm_expr
.X_add_number
> 31)
3850 as_warn ("Improper shift amount (%ld)",
3851 (long) imm_expr
.X_add_number
);
3852 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
3854 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3855 imm_expr
.X_op
= O_absent
;
3859 case '>': /* shift amount minus 32 */
3860 my_getExpression (&imm_expr
, s
);
3861 check_absolute_expr (ip
, &imm_expr
);
3862 if ((unsigned long) imm_expr
.X_add_number
< 32
3863 || (unsigned long) imm_expr
.X_add_number
> 63)
3865 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
3866 imm_expr
.X_op
= O_absent
;
3870 case 'k': /* cache code */
3871 my_getExpression (&imm_expr
, s
);
3872 check_absolute_expr (ip
, &imm_expr
);
3873 if ((unsigned long) imm_expr
.X_add_number
> 31)
3875 as_warn ("Invalid cahce opcode (%lu)",
3876 (unsigned long) imm_expr
.X_add_number
);
3877 imm_expr
.X_add_number
&= 0x1f;
3879 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
3880 imm_expr
.X_op
= O_absent
;
3884 case 'c': /* break code */
3885 my_getExpression (&imm_expr
, s
);
3886 check_absolute_expr (ip
, &imm_expr
);
3887 if ((unsigned) imm_expr
.X_add_number
> 1023)
3888 as_warn ("Illegal break code (%ld)",
3889 (long) imm_expr
.X_add_number
);
3890 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
3891 imm_expr
.X_op
= O_absent
;
3895 case 'B': /* syscall code */
3896 my_getExpression (&imm_expr
, s
);
3897 check_absolute_expr (ip
, &imm_expr
);
3898 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
3899 as_warn ("Illegal syscall code (%ld)",
3900 (long) imm_expr
.X_add_number
);
3901 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
3902 imm_expr
.X_op
= O_absent
;
3906 case 'C': /* Coprocessor code */
3907 my_getExpression (&imm_expr
, s
);
3908 check_absolute_expr (ip
, &imm_expr
);
3909 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
3911 as_warn ("Coproccesor code > 25 bits (%ld)",
3912 (long) imm_expr
.X_add_number
);
3913 imm_expr
.X_add_number
&= ((1<<25) - 1);
3915 ip
->insn_opcode
|= imm_expr
.X_add_number
;
3916 imm_expr
.X_op
= O_absent
;
3920 case 'b': /* base register */
3921 case 'd': /* destination register */
3922 case 's': /* source register */
3923 case 't': /* target register */
3924 case 'r': /* both target and source */
3925 case 'v': /* both dest and source */
3926 case 'w': /* both dest and target */
3927 case 'E': /* coprocessor target register */
3928 case 'G': /* coprocessor destination register */
3929 case 'x': /* ignore register name */
3930 case 'z': /* must be zero register */
3944 while (isdigit (*s
));
3946 as_bad ("Invalid register number (%d)", regno
);
3948 else if (*args
== 'E' || *args
== 'G')
3952 if (s
[1] == 'f' && s
[2] == 'p')
3957 else if (s
[1] == 's' && s
[2] == 'p')
3962 else if (s
[1] == 'g' && s
[2] == 'p')
3967 else if (s
[1] == 'a' && s
[2] == 't')
3975 if (regno
== AT
&& ! mips_noat
)
3976 as_warn ("Used $at without \".set noat\"");
3982 if (c
== 'r' || c
== 'v' || c
== 'w')
3989 /* 'z' only matches $0. */
3990 if (c
== 'z' && regno
!= 0)
3998 ip
->insn_opcode
|= regno
<< 21;
4002 ip
->insn_opcode
|= regno
<< 11;
4007 ip
->insn_opcode
|= regno
<< 16;
4010 /* This case exists because on the r3000 trunc
4011 expands into a macro which requires a gp
4012 register. On the r6000 or r4000 it is
4013 assembled into a single instruction which
4014 ignores the register. Thus the insn version
4015 is MIPS_ISA2 and uses 'x', and the macro
4016 version is MIPS_ISA1 and uses 't'. */
4019 /* This case is for the div instruction, which
4020 acts differently if the destination argument
4021 is $0. This only matches $0, and is checked
4022 outside the switch. */
4033 ip
->insn_opcode
|= lastregno
<< 21;
4036 ip
->insn_opcode
|= lastregno
<< 16;
4041 case 'D': /* floating point destination register */
4042 case 'S': /* floating point source register */
4043 case 'T': /* floating point target register */
4047 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4057 while (isdigit (*s
));
4060 as_bad ("Invalid float register number (%d)", regno
);
4062 if ((regno
& 1) != 0
4064 && ! (strcmp (str
, "mtc1") == 0 ||
4065 strcmp (str
, "mfc1") == 0 ||
4066 strcmp (str
, "lwc1") == 0 ||
4067 strcmp (str
, "swc1") == 0))
4068 as_warn ("Float register should be even, was %d",
4076 if (c
== 'V' || c
== 'W')
4086 ip
->insn_opcode
|= regno
<< 6;
4090 ip
->insn_opcode
|= regno
<< 11;
4094 ip
->insn_opcode
|= regno
<< 16;
4102 ip
->insn_opcode
|= lastregno
<< 11;
4105 ip
->insn_opcode
|= lastregno
<< 16;
4111 my_getExpression (&imm_expr
, s
);
4112 check_absolute_expr (ip
, &imm_expr
);
4117 my_getExpression (&offset_expr
, s
);
4118 imm_reloc
= BFD_RELOC_32
;
4130 unsigned char temp
[8];
4132 unsigned int length
;
4137 /* These only appear as the last operand in an
4138 instruction, and every instruction that accepts
4139 them in any variant accepts them in all variants.
4140 This means we don't have to worry about backing out
4141 any changes if the instruction does not match.
4143 The difference between them is the size of the
4144 floating point constant and where it goes. For 'F'
4145 and 'L' the constant is 64 bits; for 'f' and 'l' it
4146 is 32 bits. Where the constant is placed is based
4147 on how the MIPS assembler does things:
4150 f -- immediate value
4153 When generating PIC code, we do not use the .lit8
4154 or .lit4 sections at all, in order to reserve the
4155 entire global offset table. */
4157 f64
= *args
== 'F' || *args
== 'L';
4159 save_in
= input_line_pointer
;
4160 input_line_pointer
= s
;
4161 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4163 s
= input_line_pointer
;
4164 input_line_pointer
= save_in
;
4165 if (err
!= NULL
&& *err
!= '\0')
4167 as_bad ("Bad floating point constant: %s", err
);
4168 memset (temp
, '\0', sizeof temp
);
4169 length
= f64
? 8 : 4;
4172 assert (length
== (f64
? 8 : 4));
4175 || (mips_pic
!= 0 && *args
== 'l'))
4177 imm_expr
.X_op
= O_constant
;
4178 if (byte_order
== LITTLE_ENDIAN
)
4179 imm_expr
.X_add_number
=
4180 (((((((int) temp
[3] << 8)
4185 imm_expr
.X_add_number
=
4186 (((((((int) temp
[0] << 8)
4193 const char *newname
;
4196 /* Switch to the right section. */
4198 subseg
= now_subseg
;
4201 default: /* unused default case avoids warnings. */
4203 newname
= (mips_pic
== 0 ? ".lit8" : ".rdata");
4209 assert (mips_pic
== 0);
4213 new_seg
= subseg_new (newname
, (subsegT
) 0);
4215 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4218 as_bad ("Can't use floating point insn in this section");
4220 /* Set the argument to the current address in the
4222 offset_expr
.X_op
= O_symbol
;
4223 offset_expr
.X_add_symbol
=
4224 symbol_new ("L0\001", now_seg
,
4225 (valueT
) frag_now_fix (), frag_now
);
4226 offset_expr
.X_add_number
= 0;
4228 /* Put the floating point number into the section. */
4229 p
= frag_more ((int) length
);
4230 memcpy (p
, temp
, length
);
4232 /* Switch back to the original section. */
4233 subseg_set (seg
, subseg
);
4238 case 'i': /* 16 bit unsigned immediate */
4239 case 'j': /* 16 bit signed immediate */
4240 imm_reloc
= BFD_RELOC_LO16
;
4241 c
= my_getSmallExpression (&imm_expr
, s
);
4246 if (imm_expr
.X_op
== O_constant
)
4247 imm_expr
.X_add_number
=
4248 (imm_expr
.X_add_number
>> 16) & 0xffff;
4250 imm_reloc
= BFD_RELOC_HI16_S
;
4252 imm_reloc
= BFD_RELOC_HI16
;
4256 check_absolute_expr (ip
, &imm_expr
);
4259 if (imm_expr
.X_add_number
< 0
4260 || imm_expr
.X_add_number
>= 0x10000)
4262 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4263 !strcmp (insn
->name
, insn
[1].name
))
4265 as_bad ("16 bit expression not in range 0..65535");
4270 if (imm_expr
.X_add_number
< -0x8000 ||
4271 imm_expr
.X_add_number
>= 0x8000)
4273 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4274 !strcmp (insn
->name
, insn
[1].name
))
4276 as_bad ("16 bit expression not in range -32768..32767");
4282 case 'o': /* 16 bit offset */
4283 c
= my_getSmallExpression (&offset_expr
, s
);
4285 * If this value won't fit into a 16 bit offset, then
4286 * go find a macro that will generate the 32 bit offset
4289 if (offset_expr
.X_op
!= O_constant
4290 || offset_expr
.X_add_number
>= 0x8000
4291 || offset_expr
.X_add_number
< -0x8000)
4294 offset_reloc
= BFD_RELOC_LO16
;
4295 if (c
== 'h' || c
== 'H')
4297 assert (offset_expr
.X_op
== O_constant
);
4298 offset_expr
.X_add_number
=
4299 (offset_expr
.X_add_number
>> 16) & 0xffff;
4304 case 'p': /* pc relative offset */
4305 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4306 my_getExpression (&offset_expr
, s
);
4310 case 'u': /* upper 16 bits */
4311 c
= my_getSmallExpression (&imm_expr
, s
);
4312 if (imm_expr
.X_op
!= O_constant
4313 || imm_expr
.X_add_number
< 0
4314 || imm_expr
.X_add_number
>= 0x10000)
4315 as_bad ("lui expression not in range 0..65535");
4316 imm_reloc
= BFD_RELOC_LO16
;
4321 if (imm_expr
.X_op
== O_constant
)
4322 imm_expr
.X_add_number
=
4323 (imm_expr
.X_add_number
>> 16) & 0xffff;
4325 imm_reloc
= BFD_RELOC_HI16_S
;
4327 imm_reloc
= BFD_RELOC_HI16
;
4333 case 'a': /* 26 bit address */
4334 my_getExpression (&offset_expr
, s
);
4336 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4340 fprintf (stderr
, "bad char = '%c'\n", *args
);
4345 /* Args don't match. */
4346 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4347 !strcmp (insn
->name
, insn
[1].name
))
4353 insn_error
= "ERROR: Illegal operands";
4362 my_getSmallExpression (ep
, str
)
4373 ((str
[1] == 'h' && str
[2] == 'i')
4374 || (str
[1] == 'H' && str
[2] == 'I')
4375 || (str
[1] == 'l' && str
[2] == 'o'))
4387 * A small expression may be followed by a base register.
4388 * Scan to the end of this operand, and then back over a possible
4389 * base register. Then scan the small expression up to that
4390 * point. (Based on code in sparc.c...)
4392 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4394 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4396 if (isdigit (sp
[-2]))
4398 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4400 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4406 else if (sp
- 5 >= str
4409 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4410 || (sp
[-3] == 's' && sp
[-2] == 'p')
4411 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4412 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4418 /* no expression means zero offset */
4421 /* %xx(reg) is an error */
4422 ep
->X_op
= O_absent
;
4427 ep
->X_op
= O_constant
;
4430 ep
->X_add_symbol
= NULL
;
4431 ep
->X_op_symbol
= NULL
;
4432 ep
->X_add_number
= 0;
4437 my_getExpression (ep
, str
);
4444 my_getExpression (ep
, str
);
4445 return c
; /* => %hi or %lo encountered */
4449 my_getExpression (ep
, str
)
4455 save_in
= input_line_pointer
;
4456 input_line_pointer
= str
;
4458 expr_end
= input_line_pointer
;
4459 input_line_pointer
= save_in
;
4462 /* Turn a string in input_line_pointer into a floating point constant
4463 of type type, and store the appropriate bytes in *litP. The number
4464 of LITTLENUMS emitted is stored in *sizeP . An error message is
4465 returned, or NULL on OK. */
4468 md_atof (type
, litP
, sizeP
)
4474 LITTLENUM_TYPE words
[4];
4490 return "bad call to md_atof";
4493 t
= atof_ieee (input_line_pointer
, type
, words
);
4495 input_line_pointer
= t
;
4499 if (byte_order
== LITTLE_ENDIAN
)
4501 for (i
= prec
- 1; i
>= 0; i
--)
4503 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4509 for (i
= 0; i
< prec
; i
++)
4511 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4520 md_number_to_chars (buf
, val
, n
)
4528 number_to_chars_littleendian (buf
, val
, n
);
4532 number_to_chars_bigendian (buf
, val
, n
);
4541 md_parse_option (argP
, cntP
, vecP
)
4546 /* Accept -nocpp but ignore it. */
4547 if (strcmp (*argP
, "nocpp") == 0)
4553 if (strcmp (*argP
, "EL") == 0
4554 || strcmp (*argP
, "EB") == 0)
4556 if ((*argP
)[1] == 'B')
4557 byte_order
= BIG_ENDIAN
;
4559 byte_order
= LITTLE_ENDIAN
;
4562 if ((*argP
)[1] == 'B')
4563 mips_target_format
= "a.out-mips-big";
4565 mips_target_format
= "a.out-mips-little";
4568 if ((*argP
)[1] == 'B')
4569 mips_target_format
= "ecoff-bigmips";
4571 mips_target_format
= "ecoff-littlemips";
4574 if ((*argP
)[1] == 'B')
4575 mips_target_format
= "elf32-bigmips";
4577 mips_target_format
= "elf32-littlemips";
4580 /* FIXME: This breaks -L -EL. */
4588 if ((*argP
)[1] == '0')
4597 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4602 if (strncmp (*argP
, "mips", 4) == 0)
4604 mips_isa
= atol (*argP
+ 4);
4607 else if (mips_isa
< 1 || mips_isa
> 3)
4609 as_bad ("-mips%d not supported", mips_isa
);
4616 if (strncmp (*argP
, "mcpu=", 5) == 0)
4620 /* Identify the processor type */
4622 if (strcmp (p
, "default") == 0
4623 || strcmp (p
, "DEFAULT") == 0)
4627 if (*p
== 'r' || *p
== 'R')
4634 if (strcmp (p
, "2000") == 0
4635 || strcmp (p
, "2k") == 0
4636 || strcmp (p
, "2K") == 0)
4641 if (strcmp (p
, "3000") == 0
4642 || strcmp (p
, "3k") == 0
4643 || strcmp (p
, "3K") == 0)
4648 if (strcmp (p
, "4000") == 0
4649 || strcmp (p
, "4k") == 0
4650 || strcmp (p
, "4K") == 0)
4655 if (strcmp (p
, "6000") == 0
4656 || strcmp (p
, "6k") == 0
4657 || strcmp (p
, "6K") == 0)
4664 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4677 if ((*argP
)[1] != '\0')
4678 g_switch_value
= atoi (*argP
+ 1);
4681 **vecP
= (char *) NULL
;
4684 g_switch_value
= atoi (**vecP
);
4687 as_warn ("Number expected after -G");
4694 return 1; /* pretend you parsed the character */
4698 md_pcrel_from (fixP
)
4701 /* return the address of the delay slot */
4702 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
4705 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
4706 reloc for a cons. We could use the definition there, except that
4707 we want to handle 64 bit relocs specially. */
4710 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
4713 unsigned int nbytes
;
4716 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
4718 FIXME: There is no way to select anything but 32 bit mode right
4722 if (byte_order
== BIG_ENDIAN
)
4727 if (nbytes
!= 2 && nbytes
!= 4)
4728 as_bad ("Unsupported reloc size %d", nbytes
);
4730 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
4731 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
4735 md_apply_fix (fixP
, valueP
)
4742 assert (fixP
->fx_size
== 4);
4745 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
4747 switch (fixP
->fx_r_type
)
4750 case BFD_RELOC_MIPS_JMP
:
4751 case BFD_RELOC_HI16
:
4752 case BFD_RELOC_HI16_S
:
4753 case BFD_RELOC_LO16
:
4754 case BFD_RELOC_MIPS_GPREL
:
4755 case BFD_RELOC_MIPS_LITERAL
:
4756 case BFD_RELOC_MIPS_CALL16
:
4757 case BFD_RELOC_MIPS_GOT16
:
4758 case BFD_RELOC_MIPS_GPREL32
:
4759 /* Nothing needed to do. The value comes from the reloc entry */
4762 case BFD_RELOC_16_PCREL_S2
:
4764 * We need to save the bits in the instruction since fixup_segment()
4765 * might be deleting the relocation entry (i.e., a branch within
4766 * the current segment).
4769 as_warn ("Branch to odd address (%lx)", value
);
4771 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
4772 as_bad ("Relocation overflow");
4774 /* update old instruction data */
4775 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
4779 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
4783 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
4790 insn
|= value
& 0xFFFF;
4791 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
4805 const struct mips_opcode
*p
;
4806 int treg
, sreg
, dreg
, shamt
;
4811 for (i
= 0; i
< NUMOPCODES
; ++i
)
4813 p
= &mips_opcodes
[i
];
4814 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
4816 printf ("%08lx %s\t", oc
, p
->name
);
4817 treg
= (oc
>> 16) & 0x1f;
4818 sreg
= (oc
>> 21) & 0x1f;
4819 dreg
= (oc
>> 11) & 0x1f;
4820 shamt
= (oc
>> 6) & 0x1f;
4822 for (args
= p
->args
;; ++args
)
4833 printf ("%c", *args
);
4837 assert (treg
== sreg
);
4838 printf ("$%d,$%d", treg
, sreg
);
4843 printf ("$%d", dreg
);
4848 printf ("$%d", treg
);
4852 printf ("0x%x", treg
);
4857 printf ("$%d", sreg
);
4861 printf ("0x%08lx", oc
& 0x1ffffff);
4873 printf ("$%d", shamt
);
4884 printf ("%08lx UNDEFINED\n", oc
);
4895 name
= input_line_pointer
;
4896 c
= get_symbol_end ();
4897 p
= (symbolS
*) symbol_find_or_make (name
);
4898 *input_line_pointer
= c
;
4902 /* Align the current frag to a given power of two. The MIPS assembler
4903 also automatically adjusts any preceding label. */
4906 mips_align (to
, fill
)
4910 mips_emit_delays ();
4911 frag_align (to
, fill
);
4912 record_alignment (now_seg
, to
);
4913 if (insn_label
!= NULL
)
4915 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
4916 insn_label
->sy_frag
= frag_now
;
4917 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
4922 /* Align to a given power of two. .align 0 turns off the automatic
4923 alignment used by the data creating pseudo-ops. */
4930 register long temp_fill
;
4931 long max_alignment
= 15;
4935 o Note that the assembler pulls down any immediately preceeding label
4936 to the aligned address.
4937 o It's not documented but auto alignment is reinstated by
4938 a .align pseudo instruction.
4939 o Note also that after auto alignment is turned off the mips assembler
4940 issues an error on attempt to assemble an improperly aligned data item.
4945 temp
= get_absolute_expression ();
4946 if (temp
> max_alignment
)
4947 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
4950 as_warn ("Alignment negative: 0 assumed.");
4953 if (*input_line_pointer
== ',')
4955 input_line_pointer
++;
4956 temp_fill
= get_absolute_expression ();
4963 mips_align (temp
, (int) temp_fill
);
4970 demand_empty_rest_of_line ();
4973 /* Handle .ascii and .asciiz. This just calls stringer and forgets
4974 that there was a previous instruction. */
4977 s_stringer (append_zero
)
4980 mips_emit_delays ();
4982 stringer (append_zero
);
4993 mips_emit_delays ();
5003 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5004 demand_empty_rest_of_line ();
5009 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
5010 demand_empty_rest_of_line ();
5012 #else /* ! defined (OBJ_ECOFF) */
5014 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
5015 bfd_set_section_flags (stdoutput
, seg
,
5021 bfd_set_section_alignment (stdoutput
, seg
, 4);
5022 demand_empty_rest_of_line ();
5024 #else /* ! defined (OBJ_ELF) */
5027 #endif /* ! defined (OBJ_ELF) */
5028 #endif /* ! defined (OBJ_ECOFF) */
5032 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5034 bfd_set_section_flags (stdoutput
, seg
,
5035 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5036 bfd_set_section_alignment (stdoutput
, seg
, 4);
5038 demand_empty_rest_of_line ();
5040 #else /* ! defined (GPOPT) */
5041 as_bad ("Global pointers not supported; recompile -G 0");
5042 demand_empty_rest_of_line ();
5044 #endif /* ! defined (GPOPT) */
5054 mips_emit_delays ();
5055 if (log_size
> 0 && auto_align
)
5056 mips_align (log_size
, 0);
5058 cons (1 << log_size
);
5065 as_fatal ("Encountered `.err', aborting assembly");
5075 symbolP
= get_symbol ();
5076 if (*input_line_pointer
== ',')
5077 input_line_pointer
++;
5078 size
= get_absolute_expression ();
5079 S_SET_VALUE (symbolP
, size
);
5080 S_SET_EXTERNAL (symbolP
);
5082 #ifdef ECOFF_DEBUGGING
5083 /* ECOFF needs to distinguish a .comm symbol from a .extern symbol,
5084 so we use an additional ECOFF specific field. */
5085 symbolP
->ecoff_undefined
= 1;
5093 mips_emit_delays ();
5113 opt
= input_line_pointer
;
5114 c
= get_symbol_end ();
5118 /* FIXME: What does this mean? */
5120 else if (strncmp (opt
, "pic", 3) == 0)
5122 mips_pic
= atoi (opt
+ 3);
5123 /* Supposedly no other values are used. */
5124 assert (mips_pic
== 0 || mips_pic
== 2);
5128 if (g_switch_seen
&& g_switch_value
!= 0)
5129 as_warn ("-G may not be used with PIC code");
5131 bfd_set_gp_size (stdoutput
, 0);
5135 as_warn ("Unrecognized option \"%s\"", opt
);
5137 *input_line_pointer
= c
;
5138 demand_empty_rest_of_line ();
5145 char *name
= input_line_pointer
, ch
;
5147 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5148 input_line_pointer
++;
5149 ch
= *input_line_pointer
;
5150 *input_line_pointer
= '\0';
5152 if (strcmp (name
, "reorder") == 0)
5156 prev_insn_unreordered
= 1;
5157 prev_prev_insn_unreordered
= 1;
5161 else if (strcmp (name
, "noreorder") == 0)
5163 mips_emit_delays ();
5165 mips_any_noreorder
= 1;
5167 else if (strcmp (name
, "at") == 0)
5171 else if (strcmp (name
, "noat") == 0)
5175 else if (strcmp (name
, "macro") == 0)
5177 mips_warn_about_macros
= 0;
5179 else if (strcmp (name
, "nomacro") == 0)
5181 if (mips_noreorder
== 0)
5182 as_bad ("`noreorder' must be set before `nomacro'");
5183 mips_warn_about_macros
= 1;
5185 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5189 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5193 else if (strcmp (name
, "bopt") == 0)
5197 else if (strcmp (name
, "nobopt") == 0)
5203 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5205 *input_line_pointer
= ch
;
5206 demand_empty_rest_of_line ();
5209 /* The same as the usual .space directive, except that we have to
5210 forget about any previous instruction. */
5213 s_mips_space (param
)
5216 mips_emit_delays ();
5221 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5222 .option pic2. It means to generate SVR4 PIC calls. */
5229 demand_empty_rest_of_line ();
5232 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5233 PIC code. It sets the $gp register for the function based on the
5234 function address, which is in the register named in the argument.
5235 This uses a relocation against _gp_disp, which is handled specially
5236 by the linker. The result is:
5237 lui $gp,%hi(_gp_disp)
5238 addiu $gp,$gp,%lo(_gp_disp)
5239 addu $gp,$gp,.cpload argument
5240 The .cpload argument is normally $25 == $t9. */
5249 /* If we are not generating PIC code, .cpload is ignored. */
5256 /* .cpload should be a in .set noreorder section. */
5257 if (mips_noreorder
== 0)
5258 as_warn (".cpload not in noreorder section");
5261 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5262 ex
.X_op_symbol
= NULL
;
5263 ex
.X_add_number
= 0;
5265 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5266 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5267 (int) BFD_RELOC_LO16
);
5269 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5270 GP
, GP
, tc_get_register (0));
5272 demand_empty_rest_of_line ();
5275 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5276 offset from $sp. The offset is remembered, and after making a PIC
5277 call $gp is restored from that location. */
5280 s_cprestore (ignore
)
5286 /* If we are not generating PIC code, .cprestore is ignored. */
5293 mips_cprestore_offset
= get_absolute_expression ();
5295 ex
.X_op
= O_constant
;
5296 ex
.X_add_symbol
= NULL
;
5297 ex
.X_op_symbol
= NULL
;
5298 ex
.X_add_number
= mips_cprestore_offset
;
5300 macro_build ((char *) NULL
, &icnt
, &ex
,
5301 mips_isa
< 3 ? "sw" : "sd",
5302 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5304 demand_empty_rest_of_line ();
5307 /* Handle the .gpword pseudo-op. This is used when generating PIC
5308 code. It generates a 32 bit GP relative reloc. */
5317 /* When not generating PIC code, this is treated as .word. */
5324 mips_emit_delays ();
5331 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5333 as_bad ("Unsupported use of .gpword");
5334 ignore_rest_of_line ();
5338 md_number_to_chars (p
, (valueT
) 0, 4);
5339 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5340 BFD_RELOC_MIPS_GPREL32
);
5342 demand_empty_rest_of_line ();
5345 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5346 tables in SVR4 PIC code. */
5355 /* This is ignored when not generating SVR4 PIC code. */
5362 /* Add $gp to the register named as an argument. */
5363 reg
= tc_get_register (0);
5364 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5365 mips_isa
< 3 ? "addu" : "daddu",
5366 "d,v,t", reg
, reg
, GP
);
5368 demand_empty_rest_of_line ();
5371 /* Parse a register string into a number. Called from the ECOFF code
5372 to parse .frame. The argument is non-zero if this is the frame
5373 register, so that we can record it in mips_frame_reg. */
5376 tc_get_register (frame
)
5382 if (*input_line_pointer
++ != '$')
5384 as_warn ("expected `$'");
5387 else if (isdigit ((unsigned char) *input_line_pointer
))
5389 reg
= get_absolute_expression ();
5390 if (reg
< 0 || reg
>= 32)
5392 as_warn ("Bad register number");
5398 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5400 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5402 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5404 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5408 as_warn ("Unrecognized register name");
5411 input_line_pointer
+= 2;
5414 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5419 md_section_align (seg
, addr
)
5423 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5425 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5428 /* Estimate the size of a frag before relaxing. We are not really
5429 relaxing here, and the final size is encoded in the subtype
5434 md_estimate_size_before_relax (fragp
, segtype
)
5443 const char *symname
;
5445 /* Find out whether this symbol can be referenced off the GP
5446 register. It can be if it is smaller than the -G size or if
5447 it is in the .sdata or .sbss section. Certain symbols can
5448 not be referenced off the GP, although it appears as though
5450 symname
= S_GET_NAME (fragp
->fr_symbol
);
5451 if (symname
!= (const char *) NULL
5452 && (strcmp (symname
, "eprol") == 0
5453 || strcmp (symname
, "etext") == 0
5454 || strcmp (symname
, "_gp") == 0
5455 || strcmp (symname
, "edata") == 0
5456 || strcmp (symname
, "_fbss") == 0
5457 || strcmp (symname
, "_fdata") == 0
5458 || strcmp (symname
, "_ftext") == 0
5459 || strcmp (symname
, "end") == 0
5460 || strcmp (symname
, "_gp_disp") == 0))
5462 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5463 && S_GET_VALUE (fragp
->fr_symbol
) != 0
5464 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)
5468 const char *segname
;
5470 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5471 assert (strcmp (segname
, ".lit8") != 0
5472 && strcmp (segname
, ".lit4") != 0);
5473 change
= (strcmp (segname
, ".sdata") != 0
5474 && strcmp (segname
, ".sbss") != 0);
5476 #else /* ! defined (GPOPT) */
5477 /* We are not optimizing for the GP register. */
5479 #endif /* ! defined (GPOPT) */
5483 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5485 /* This must duplicate the test in adjust_reloc_syms. */
5486 change
= (symsec
!= &bfd_und_section
5487 && symsec
!= &bfd_abs_section
5488 && ! bfd_is_com_section (symsec
));
5493 /* Record the offset to the first reloc in the fr_opcode field.
5494 This lets md_convert_frag and tc_gen_reloc know that the code
5495 must be expanded. */
5496 fragp
->fr_opcode
= (fragp
->fr_literal
5498 - RELAX_OLD (fragp
->fr_subtype
)
5499 + RELAX_RELOC1 (fragp
->fr_subtype
));
5500 /* FIXME: This really needs as_warn_where. */
5501 if (RELAX_WARN (fragp
->fr_subtype
))
5502 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
5508 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
5511 /* Translate internal representation of relocation info to BFD target
5515 tc_gen_reloc (section
, fixp
)
5519 static arelent
*retval
[4];
5522 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
5525 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5526 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5527 if (fixp
->fx_pcrel
== 0)
5528 reloc
->addend
= fixp
->fx_addnumber
;
5533 reloc
->addend
= -reloc
->address
;
5536 /* If this is a variant frag, we may need to adjust the existing
5537 reloc and generate a new one. */
5538 if (fixp
->fx_frag
->fr_opcode
!= NULL
5539 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5540 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
5541 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
5545 /* If this is not the last reloc in this frag, then we have two
5546 GPREL relocs, both of which are being replaced. Let the
5547 second one handle all of them. */
5548 if (fixp
->fx_next
!= NULL
5549 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
5551 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5552 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5557 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
5558 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5559 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
5561 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5562 reloc2
->address
= (reloc
->address
5563 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
5564 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
5565 reloc2
->addend
= fixp
->fx_addnumber
;
5566 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
5567 assert (reloc2
->howto
!= NULL
);
5569 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
5573 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
5576 reloc3
->address
+= 4;
5581 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
5582 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
5586 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
5588 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
5589 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
5594 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
5596 if (reloc
->howto
== NULL
)
5598 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
5599 "Can not represent relocation in this object file format");
5606 /* Convert a machine dependent frag. */
5609 md_convert_frag (abfd
, asec
, fragp
)
5617 if (fragp
->fr_opcode
== NULL
)
5620 old
= RELAX_OLD (fragp
->fr_subtype
);
5621 new = RELAX_NEW (fragp
->fr_subtype
);
5622 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
5625 memcpy (fixptr
- old
, fixptr
, new);
5627 fragp
->fr_fix
+= new - old
;
5630 /* This function is called whenever a label is defined. It is used
5631 when handling branch delays; if a branch has a label, we assume we
5635 mips_define_label (sym
)
5643 /* Some special processing for a MIPS ELF file. */
5646 mips_elf_final_processing ()
5650 /* Write out the .reginfo section. */
5651 s
.ri_gprmask
= mips_gprmask
;
5652 s
.ri_cprmask
[0] = mips_cprmask
[0];
5653 s
.ri_cprmask
[1] = mips_cprmask
[1];
5654 s
.ri_cprmask
[2] = mips_cprmask
[2];
5655 s
.ri_cprmask
[3] = mips_cprmask
[3];
5656 /* The gp_value field is set by the MIPS ELF backend. */
5658 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
5659 ((Elf32_External_RegInfo
*)
5660 mips_regmask_frag
));
5662 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
5663 sort of BFD interface for this. */
5664 if (mips_any_noreorder
)
5665 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
5667 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
5670 #endif /* OBJ_ELF */
5672 #ifndef ECOFF_DEBUGGING
5674 /* These functions should really be defined by the object file format,
5675 since they are related to debugging information. However, this
5676 code has to work for the a.out format, which does not define them,
5677 so we provide simple versions here. These don't actually generate
5678 any debugging information, but they do simple checking and someday
5679 somebody may make them useful. */
5683 struct loc
*loc_next
;
5684 unsigned long loc_fileno
;
5685 unsigned long loc_lineno
;
5686 unsigned long loc_offset
;
5687 unsigned short loc_delta
;
5688 unsigned short loc_count
;
5697 struct proc
*proc_next
;
5698 struct symbol
*proc_isym
;
5699 struct symbol
*proc_end
;
5700 unsigned long proc_reg_mask
;
5701 unsigned long proc_reg_offset
;
5702 unsigned long proc_fpreg_mask
;
5703 unsigned long proc_fpreg_offset
;
5704 unsigned long proc_frameoffset
;
5705 unsigned long proc_framereg
;
5706 unsigned long proc_pcreg
;
5708 struct file
*proc_file
;
5715 struct file
*file_next
;
5716 unsigned long file_fileno
;
5717 struct symbol
*file_symbol
;
5718 struct symbol
*file_end
;
5719 struct proc
*file_proc
;
5724 static struct obstack proc_frags
;
5725 static procS
*proc_lastP
;
5726 static procS
*proc_rootP
;
5727 static int numprocs
;
5732 obstack_begin (&proc_frags
, 0x2000);
5738 /* check for premature end, nesting errors, etc */
5739 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5740 as_warn ("missing `.end' at end of assembly");
5743 extern char hex_value
[];
5751 if (*input_line_pointer
== '-')
5753 ++input_line_pointer
;
5756 if (!isdigit (*input_line_pointer
))
5757 as_bad ("Expected simple number.");
5758 if (input_line_pointer
[0] == '0')
5760 if (input_line_pointer
[1] == 'x')
5762 input_line_pointer
+= 2;
5763 while (isxdigit (*input_line_pointer
))
5766 val
|= hex_value
[(int) *input_line_pointer
++];
5768 return negative
? -val
: val
;
5772 ++input_line_pointer
;
5773 while (isdigit (*input_line_pointer
))
5776 val
|= *input_line_pointer
++ - '0';
5778 return negative
? -val
: val
;
5781 if (!isdigit (*input_line_pointer
))
5783 printf (" *input_line_pointer == '%c' 0x%02x\n",
5784 *input_line_pointer
, *input_line_pointer
);
5785 as_warn ("Invalid number");
5788 while (isdigit (*input_line_pointer
))
5791 val
+= *input_line_pointer
++ - '0';
5793 return negative
? -val
: val
;
5796 /* The .file directive; just like the usual .file directive, but there
5797 is an initial number which is the ECOFF file index. */
5805 line
= get_number ();
5810 /* The .end directive. */
5818 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5821 demand_empty_rest_of_line ();
5825 if (now_seg
!= text_section
)
5826 as_warn (".end not in text section");
5829 as_warn (".end and no .ent seen yet.");
5835 assert (S_GET_NAME (p
));
5836 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
5837 as_warn (".end symbol does not match .ent symbol.");
5840 proc_lastP
->proc_end
= (symbolS
*) 1;
5843 /* The .aent and .ent directives. */
5853 symbolP
= get_symbol ();
5854 if (*input_line_pointer
== ',')
5855 input_line_pointer
++;
5857 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
5858 number
= get_number ();
5859 if (now_seg
!= text_section
)
5860 as_warn (".ent or .aent not in text section.");
5862 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
5863 as_warn ("missing `.end'");
5867 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
5868 procP
->proc_isym
= symbolP
;
5869 procP
->proc_reg_mask
= 0;
5870 procP
->proc_reg_offset
= 0;
5871 procP
->proc_fpreg_mask
= 0;
5872 procP
->proc_fpreg_offset
= 0;
5873 procP
->proc_frameoffset
= 0;
5874 procP
->proc_framereg
= 0;
5875 procP
->proc_pcreg
= 0;
5876 procP
->proc_end
= NULL
;
5877 procP
->proc_next
= NULL
;
5879 proc_lastP
->proc_next
= procP
;
5885 demand_empty_rest_of_line ();
5888 /* The .frame directive. */
5901 frame_reg
= tc_get_register (1);
5902 if (*input_line_pointer
== ',')
5903 input_line_pointer
++;
5904 frame_off
= get_absolute_expression ();
5905 if (*input_line_pointer
== ',')
5906 input_line_pointer
++;
5907 pcreg
= tc_get_register (0);
5910 assert (proc_rootP
);
5911 proc_rootP
->proc_framereg
= frame_reg
;
5912 proc_rootP
->proc_frameoffset
= frame_off
;
5913 proc_rootP
->proc_pcreg
= pcreg
;
5914 /* bob macho .frame */
5916 /* We don't have to write out a frame stab for unoptimized code. */
5917 if (!(frame_reg
== FP
&& frame_off
== 0))
5920 as_warn ("No .ent for .frame to use.");
5921 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
5922 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
5923 S_SET_TYPE (symP
, N_RMASK
);
5924 S_SET_OTHER (symP
, 0);
5925 S_SET_DESC (symP
, 0);
5926 symP
->sy_forward
= proc_lastP
->proc_isym
;
5927 /* bob perhaps I should have used pseudo set */
5929 demand_empty_rest_of_line ();
5933 /* The .fmask and .mask directives. */
5940 char str
[100], *strP
;
5946 mask
= get_number ();
5947 if (*input_line_pointer
== ',')
5948 input_line_pointer
++;
5949 off
= get_absolute_expression ();
5951 /* bob only for coff */
5952 assert (proc_rootP
);
5953 if (reg_type
== 'F')
5955 proc_rootP
->proc_fpreg_mask
= mask
;
5956 proc_rootP
->proc_fpreg_offset
= off
;
5960 proc_rootP
->proc_reg_mask
= mask
;
5961 proc_rootP
->proc_reg_offset
= off
;
5964 /* bob macho .mask + .fmask */
5966 /* We don't have to write out a mask stab if no saved regs. */
5970 as_warn ("No .ent for .mask to use.");
5972 for (i
= 0; i
< 32; i
++)
5976 sprintf (strP
, "%c%d,", reg_type
, i
);
5977 strP
+= strlen (strP
);
5981 sprintf (strP
, ";%d,", off
);
5982 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
5983 S_SET_TYPE (symP
, N_RMASK
);
5984 S_SET_OTHER (symP
, 0);
5985 S_SET_DESC (symP
, 0);
5986 symP
->sy_forward
= proc_lastP
->proc_isym
;
5987 /* bob perhaps I should have used pseudo set */
5992 /* The .loc directive. */
6003 assert (now_seg
== text_section
);
6005 lineno
= get_number ();
6006 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6008 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6009 S_SET_TYPE (symbolP
, N_SLINE
);
6010 S_SET_OTHER (symbolP
, 0);
6011 S_SET_DESC (symbolP
, lineno
);
6012 symbolP
->sy_segment
= now_seg
;
6016 #endif /* ! defined (ECOFF_DEBUGGING) */