1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* The name of the readonly data section. */
95 #define RDATA_SECTION_NAME ".data"
98 #define RDATA_SECTION_NAME ".rdata"
101 #define RDATA_SECTION_NAME ".rodata"
104 /* These variables are filled in with the masks of registers used.
105 The object format code reads them and puts them in the appropriate
107 unsigned long mips_gprmask
;
108 unsigned long mips_cprmask
[4];
110 /* MIPS ISA (Instruction Set Architecture) level (may be changed
111 temporarily using .set mipsN). */
112 static int mips_isa
= -1;
114 /* MIPS ISA we are using for this output file. */
115 static int file_mips_isa
;
117 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
120 /* MIPS PIC level. */
124 /* Do not generate PIC code. */
127 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
128 not sure what it is supposed to do. */
131 /* Generate PIC code as in the SVR4 MIPS ABI. */
134 /* Generate PIC code without using a global offset table: the data
135 segment has a maximum size of 64K, all data references are off
136 the $gp register, and all text references are PC relative. This
137 is used on some embedded systems. */
141 static enum mips_pic_level mips_pic
;
143 /* 1 if trap instructions should used for overflow rather than break
145 static int mips_trap
;
147 static int mips_warn_about_macros
;
148 static int mips_noreorder
;
149 static int mips_any_noreorder
;
150 static int mips_nomove
;
151 static int mips_noat
;
152 static int mips_nobopt
;
155 /* The size of the small data section. */
156 static int g_switch_value
= 8;
157 /* Whether the -G option was used. */
158 static int g_switch_seen
= 0;
164 /* handle of the OPCODE hash table */
165 static struct hash_control
*op_hash
= NULL
;
167 /* This array holds the chars that always start a comment. If the
168 pre-processor is disabled, these aren't very useful */
169 const char comment_chars
[] = "#";
171 /* This array holds the chars that only start a comment at the beginning of
172 a line. If the line seems to have the form '# 123 filename'
173 .line and .file directives will appear in the pre-processed output */
174 /* Note that input_file.c hand checks for '#' at the beginning of the
175 first line of the input file. This is because the compiler outputs
176 #NO_APP at the beginning of its output. */
177 /* Also note that C style comments are always supported. */
178 const char line_comment_chars
[] = "#";
180 /* This array holds machine specific line separator characters. */
181 const char line_separator_chars
[] = "";
183 /* Chars that can be used to separate mant from exp in floating point nums */
184 const char EXP_CHARS
[] = "eE";
186 /* Chars that mean this number is a floating point constant */
189 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
191 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
192 changed in read.c . Ideally it shouldn't have to know about it at all,
193 but nothing is ideal around here.
196 static char *insn_error
;
198 static int byte_order
= BYTE_ORDER
;
200 static int auto_align
= 1;
202 /* Symbol labelling the current insn. */
203 static symbolS
*insn_label
;
205 /* When outputting SVR4 PIC code, the assembler needs to know the
206 offset in the stack frame from which to restore the $gp register.
207 This is set by the .cprestore pseudo-op, and saved in this
209 static offsetT mips_cprestore_offset
= -1;
211 /* This is the register which holds the stack frame, as set by the
212 .frame pseudo-op. This is needed to implement .cprestore. */
213 static int mips_frame_reg
= SP
;
215 /* To output NOP instructions correctly, we need to keep information
216 about the previous two instructions. */
218 /* Whether we are optimizing. The default value of 2 means to remove
219 unneeded NOPs and swap branch instructions when possible. A value
220 of 1 means to not swap branches. A value of 0 means to always
222 static int mips_optimize
= 2;
224 /* The previous instruction. */
225 static struct mips_cl_insn prev_insn
;
227 /* The instruction before prev_insn. */
228 static struct mips_cl_insn prev_prev_insn
;
230 /* If we don't want information for prev_insn or prev_prev_insn, we
231 point the insn_mo field at this dummy integer. */
232 static const struct mips_opcode dummy_opcode
= { 0 };
234 /* Non-zero if prev_insn is valid. */
235 static int prev_insn_valid
;
237 /* The frag for the previous instruction. */
238 static struct frag
*prev_insn_frag
;
240 /* The offset into prev_insn_frag for the previous instruction. */
241 static long prev_insn_where
;
243 /* The reloc for the previous instruction, if any. */
244 static fixS
*prev_insn_fixp
;
246 /* Non-zero if the previous instruction was in a delay slot. */
247 static int prev_insn_is_delay_slot
;
249 /* Non-zero if the previous instruction was in a .set noreorder. */
250 static int prev_insn_unreordered
;
252 /* Non-zero if the previous previous instruction was in a .set
254 static int prev_prev_insn_unreordered
;
256 /* The number of instructions since the last instruction which
257 accesses the data cache. The instruction itself counts as 1, so 0
258 means no information. This is used to work around a bug on the
259 r4600 (ORION) chip. */
260 static int insns_since_cache_access
;
262 /* Since the MIPS does not have multiple forms of PC relative
263 instructions, we do not have to do relaxing as is done on other
264 platforms. However, we do have to handle GP relative addressing
265 correctly, which turns out to be a similar problem.
267 Every macro that refers to a symbol can occur in (at least) two
268 forms, one with GP relative addressing and one without. For
269 example, loading a global variable into a register generally uses
270 a macro instruction like this:
272 If i can be addressed off the GP register (this is true if it is in
273 the .sbss or .sdata section, or if it is known to be smaller than
274 the -G argument) this will generate the following instruction:
276 This instruction will use a GPREL reloc. If i can not be addressed
277 off the GP register, the following instruction sequence will be used:
280 In this case the first instruction will have a HI16 reloc, and the
281 second reloc will have a LO16 reloc. Both relocs will be against
284 The issue here is that we may not know whether i is GP addressable
285 until after we see the instruction that uses it. Therefore, we
286 want to be able to choose the final instruction sequence only at
287 the end of the assembly. This is similar to the way other
288 platforms choose the size of a PC relative instruction only at the
291 When generating position independent code we do not use GP
292 addressing in quite the same way, but the issue still arises as
293 external symbols and local symbols must be handled differently.
295 We handle these issues by actually generating both possible
296 instruction sequences. The longer one is put in a frag_var with
297 type rs_machine_dependent. We encode what to do with the frag in
298 the subtype field. We encode (1) the number of existing bytes to
299 replace, (2) the number of new bytes to use, (3) the offset from
300 the start of the existing bytes to the first reloc we must generate
301 (that is, the offset is applied from the start of the existing
302 bytes after they are replaced by the new bytes, if any), (4) the
303 offset from the start of the existing bytes to the second reloc,
304 (5) whether a third reloc is needed (the third reloc is always four
305 bytes after the second reloc), and (6) whether to warn if this
306 variant is used (this is sometimes needed if .set nomacro or .set
307 noat is in effect). All these numbers are reasonably small.
309 Generating two instruction sequences must be handled carefully to
310 ensure that delay slots are handled correctly. Fortunately, there
311 are a limited number of cases. When the second instruction
312 sequence is generated, append_insn is directed to maintain the
313 existing delay slot information, so it continues to apply to any
314 code after the second instruction sequence. This means that the
315 second instruction sequence must not impose any requirements not
316 required by the first instruction sequence.
318 These variant frags are then handled in functions called by the
319 machine independent code. md_estimate_size_before_relax returns
320 the final size of the frag. md_convert_frag sets up the final form
321 of the frag. tc_gen_reloc adjust the first reloc and adds a second
323 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
327 | (((reloc1) + 64) << 9) \
328 | (((reloc2) + 64) << 2) \
329 | ((reloc3) ? (1 << 1) : 0) \
331 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
332 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
333 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
334 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
335 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
336 #define RELAX_WARN(i) ((i) & 1)
338 /* Prototypes for static functions. */
341 #define internalError() \
342 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
344 #define internalError() as_fatal ("MIPS internal Error");
347 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
348 unsigned int reg
, int fpr
));
349 static void append_insn
PARAMS ((char *place
,
350 struct mips_cl_insn
* ip
,
352 bfd_reloc_code_real_type r
));
353 static void mips_no_prev_insn
PARAMS ((void));
354 static void mips_emit_delays
PARAMS ((void));
355 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
356 const char *name
, const char *fmt
,
358 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
359 expressionS
* ep
, int regnum
));
360 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
361 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
363 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
364 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
365 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
366 #ifdef LOSING_COMPILER
367 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
369 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
370 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
371 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
372 static symbolS
*get_symbol
PARAMS ((void));
373 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
374 static void s_align
PARAMS ((int));
375 static void s_stringer
PARAMS ((int));
376 static void s_change_sec
PARAMS ((int));
377 static void s_cons
PARAMS ((int));
378 static void s_err
PARAMS ((int));
379 static void s_extern
PARAMS ((int));
380 static void s_float_cons
PARAMS ((int));
381 static void s_option
PARAMS ((int));
382 static void s_mipsset
PARAMS ((int));
383 static void s_mips_space
PARAMS ((int));
384 static void s_abicalls
PARAMS ((int));
385 static void s_cpload
PARAMS ((int));
386 static void s_cprestore
PARAMS ((int));
387 static void s_gpword
PARAMS ((int));
388 static void s_cpadd
PARAMS ((int));
389 #ifndef ECOFF_DEBUGGING
390 static void md_obj_begin
PARAMS ((void));
391 static void md_obj_end
PARAMS ((void));
392 static long get_number
PARAMS ((void));
393 static void s_ent
PARAMS ((int));
394 static void s_mipsend
PARAMS ((int));
395 static void s_file
PARAMS ((int));
397 static void s_frame
PARAMS ((int));
398 static void s_loc
PARAMS ((int));
399 static void s_mask
PARAMS ((char));
405 The following pseudo-ops from the Kane and Heinrich MIPS book
406 should be defined here, but are currently unsupported: .alias,
407 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
409 The following pseudo-ops from the Kane and Heinrich MIPS book are
410 specific to the type of debugging information being generated, and
411 should be defined by the object format: .aent, .begin, .bend,
412 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
415 The following pseudo-ops from the Kane and Heinrich MIPS book are
416 not MIPS CPU specific, but are also not specific to the object file
417 format. This file is probably the best place to define them, but
418 they are not currently supported: .asm0, .endr, .lab, .repeat,
419 .struct, .weakext. */
421 const pseudo_typeS md_pseudo_table
[] =
423 /* MIPS specific pseudo-ops. */
424 {"option", s_option
, 0},
425 {"set", s_mipsset
, 0},
426 {"rdata", s_change_sec
, 'r'},
427 {"sdata", s_change_sec
, 's'},
428 {"livereg", s_ignore
, 0},
429 { "abicalls", s_abicalls
, 0},
430 { "cpload", s_cpload
, 0},
431 { "cprestore", s_cprestore
, 0},
432 { "gpword", s_gpword
, 0},
433 { "cpadd", s_cpadd
, 0},
435 /* Relatively generic pseudo-ops that happen to be used on MIPS
437 {"asciiz", s_stringer
, 1},
438 {"bss", s_change_sec
, 'b'},
441 {"dword", s_cons
, 3},
443 /* These pseudo-ops are defined in read.c, but must be overridden
444 here for one reason or another. */
445 {"align", s_align
, 0},
446 {"ascii", s_stringer
, 0},
447 {"asciz", s_stringer
, 1},
449 {"data", s_change_sec
, 'd'},
450 {"double", s_float_cons
, 'd'},
451 {"extern", s_extern
, 0},
452 {"float", s_float_cons
, 'f'},
453 {"hword", s_cons
, 1},
458 {"short", s_cons
, 1},
459 {"single", s_float_cons
, 'f'},
460 {"space", s_mips_space
, 0},
461 {"text", s_change_sec
, 't'},
464 #ifndef ECOFF_DEBUGGING
465 /* These pseudo-ops should be defined by the object file format.
466 However, a.out doesn't support them, so we have versions here. */
468 {"bgnb", s_ignore
, 0},
469 {"end", s_mipsend
, 0},
470 {"endb", s_ignore
, 0},
473 {"fmask", s_ignore
, 'F'},
474 {"frame", s_ignore
, 0},
475 {"loc", s_ignore
, 0},
476 {"mask", s_ignore
, 'R'},
477 {"verstamp", s_ignore
, 0},
484 const relax_typeS md_relax_table
[] =
489 static char *expr_end
;
491 static expressionS imm_expr
;
492 static expressionS offset_expr
;
493 static bfd_reloc_code_real_type imm_reloc
;
494 static bfd_reloc_code_real_type offset_reloc
;
496 /* FIXME: This should be handled in a different way. */
497 extern int target_big_endian
;
500 * This function is called once, at assembler startup time. It should
501 * set up all the tables, etc. that the MD part of the assembler will need.
507 register const char *retval
= NULL
;
508 register unsigned int i
= 0;
516 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
518 a
= xmalloc (sizeof TARGET_CPU
);
519 strcpy (a
, TARGET_CPU
);
520 a
[(sizeof TARGET_CPU
) - 3] = '\0';
524 if (strcmp (cpu
, "mips") == 0)
529 else if (strcmp (cpu
, "r6000") == 0
530 || strcmp (cpu
, "mips2") == 0)
535 else if (strcmp (cpu
, "mips64") == 0
536 || strcmp (cpu
, "r4000") == 0
537 || strcmp (cpu
, "mips3") == 0)
542 else if (strcmp (cpu
, "r4400") == 0)
547 else if (strcmp (cpu
, "mips64orion") == 0
548 || strcmp (cpu
, "r4600") == 0)
563 if (mips_isa
< 2 && mips_trap
)
564 as_bad ("trap exception not supported at ISA 1");
569 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
572 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
575 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
579 as_warn ("Could not set architecture and machine");
581 file_mips_isa
= mips_isa
;
583 op_hash
= hash_new ();
585 for (i
= 0; i
< NUMOPCODES
;)
587 const char *name
= mips_opcodes
[i
].name
;
589 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
592 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
593 mips_opcodes
[i
].name
, retval
);
594 as_fatal ("Broken assembler. No assembly attempted.");
598 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
599 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
600 != mips_opcodes
[i
].match
))
602 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
603 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
604 as_fatal ("Broken assembler. No assembly attempted.");
608 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
611 mips_no_prev_insn ();
619 /* set the default alignment for the text section (2**2) */
620 record_alignment (text_section
, 2);
622 /* FIXME: This should be handled in a different way. */
623 target_big_endian
= byte_order
== BIG_ENDIAN
;
626 bfd_set_gp_size (stdoutput
, g_switch_value
);
630 /* Sections must be aligned to 16 byte boundaries. */
631 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
632 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
633 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
635 /* Create a .reginfo section for register masks and a .mdebug
636 section for debugging information. */
644 sec
= subseg_new (".reginfo", (subsegT
) 0);
646 /* The ABI says this section should be loaded so that the running
647 program can access it. */
648 (void) bfd_set_section_flags (stdoutput
, sec
,
649 (SEC_ALLOC
| SEC_LOAD
650 | SEC_READONLY
| SEC_DATA
));
651 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
653 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
655 #ifdef ECOFF_DEBUGGING
656 sec
= subseg_new (".mdebug", (subsegT
) 0);
657 (void) bfd_set_section_flags (stdoutput
, sec
,
658 SEC_HAS_CONTENTS
| SEC_READONLY
);
659 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
662 subseg_set (seg
, subseg
);
666 #ifndef ECOFF_DEBUGGING
674 #ifndef ECOFF_DEBUGGING
683 struct mips_cl_insn insn
;
685 imm_expr
.X_op
= O_absent
;
686 offset_expr
.X_op
= O_absent
;
688 mips_ip (str
, &insn
);
691 as_bad ("%s `%s'", insn_error
, str
);
694 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
700 if (imm_expr
.X_op
!= O_absent
)
701 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
702 else if (offset_expr
.X_op
!= O_absent
)
703 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
705 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
709 /* See whether instruction IP reads register REG. If FPR is non-zero,
710 REG is a floating point register. */
713 insn_uses_reg (ip
, reg
, fpr
)
714 struct mips_cl_insn
*ip
;
718 /* Don't report on general register 0, since it never changes. */
719 if (! fpr
&& reg
== 0)
724 /* If we are called with either $f0 or $f1, we must check $f0.
725 This is not optimal, because it will introduce an unnecessary
726 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
727 need to distinguish reading both $f0 and $f1 or just one of
728 them. Note that we don't have to check the other way,
729 because there is no instruction that sets both $f0 and $f1
730 and requires a delay. */
731 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
732 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
733 == (reg
&~ (unsigned) 1)))
735 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
736 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
737 == (reg
&~ (unsigned) 1)))
742 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
743 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
745 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
746 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
753 /* Output an instruction. PLACE is where to put the instruction; if
754 it is NULL, this uses frag_more to get room. IP is the instruction
755 information. ADDRESS_EXPR is an operand of the instruction to be
756 used with RELOC_TYPE. */
759 append_insn (place
, ip
, address_expr
, reloc_type
)
761 struct mips_cl_insn
*ip
;
762 expressionS
*address_expr
;
763 bfd_reloc_code_real_type reloc_type
;
765 register unsigned long prev_pinfo
, pinfo
;
770 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
771 pinfo
= ip
->insn_mo
->pinfo
;
773 if (place
== NULL
&& ! mips_noreorder
)
775 /* If the previous insn required any delay slots, see if we need
776 to insert a NOP or two. There are eight kinds of possible
777 hazards, of which an instruction can have at most one type.
778 (1) a load from memory delay
779 (2) a load from a coprocessor delay
780 (3) an unconditional branch delay
781 (4) a conditional branch delay
782 (5) a move to coprocessor register delay
783 (6) a load coprocessor register from memory delay
784 (7) a coprocessor condition code delay
785 (8) a HI/LO special register delay
787 There are a lot of optimizations we could do that we don't.
788 In particular, we do not, in general, reorder instructions.
789 If you use gcc with optimization, it will reorder
790 instructions and generally do much more optimization then we
791 do here; repeating all that work in the assembler would only
792 benefit hand written assembly code, and does not seem worth
795 /* This is how a NOP is emitted. */
796 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
798 /* The previous insn might require a delay slot, depending upon
799 the contents of the current insn. */
800 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
802 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
804 /* A load from a coprocessor or from memory. All load
805 delays delay the use of general register rt for one
806 instruction on the r3000. The r6000 and r4000 use
808 know (prev_pinfo
& INSN_WRITE_GPR_T
);
809 if (mips_optimize
== 0
810 || insn_uses_reg (ip
,
811 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
816 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
818 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
820 /* A generic coprocessor delay. The previous instruction
821 modified a coprocessor general or control register. If
822 it modified a control register, we need to avoid any
823 coprocessor instruction (this is probably not always
824 required, but it sometimes is). If it modified a general
825 register, we avoid using that register.
827 On the r6000 and r4000 loading a coprocessor register
828 from memory is interlocked, and does not require a delay.
830 This case is not handled very well. There is no special
831 knowledge of CP0 handling, and the coprocessors other
832 than the floating point unit are not distinguished at
834 if (prev_pinfo
& INSN_WRITE_FPR_T
)
836 if (mips_optimize
== 0
837 || insn_uses_reg (ip
,
838 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
843 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
845 if (mips_optimize
== 0
846 || insn_uses_reg (ip
,
847 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
854 /* We don't know exactly what the previous instruction
855 does. If the current instruction uses a coprocessor
856 register, we must insert a NOP. If previous
857 instruction may set the condition codes, and the
858 current instruction uses them, we must insert two
860 if (mips_optimize
== 0
861 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
862 && (pinfo
& INSN_READ_COND_CODE
)))
864 else if (pinfo
& INSN_COP
)
868 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
870 /* The previous instruction sets the coprocessor condition
871 codes, but does not require a general coprocessor delay
872 (this means it is a floating point comparison
873 instruction). If this instruction uses the condition
874 codes, we need to insert a single NOP. */
875 if (mips_optimize
== 0
876 || (pinfo
& INSN_READ_COND_CODE
))
879 else if (prev_pinfo
& INSN_READ_LO
)
881 /* The previous instruction reads the LO register; if the
882 current instruction writes to the LO register, we must
884 if (mips_optimize
== 0
885 || (pinfo
& INSN_WRITE_LO
))
888 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
890 /* The previous instruction reads the HI register; if the
891 current instruction writes to the HI register, we must
893 if (mips_optimize
== 0
894 || (pinfo
& INSN_WRITE_HI
))
898 /* There are two cases which require two intervening
899 instructions: 1) setting the condition codes using a move to
900 coprocessor instruction which requires a general coprocessor
901 delay and then reading the condition codes 2) reading the HI
902 or LO register and then writing to it. If we are not already
903 emitting a NOP instruction, we must check for these cases
904 compared to the instruction previous to the previous
907 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
908 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
909 && (pinfo
& INSN_READ_COND_CODE
))
910 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
911 && (pinfo
& INSN_WRITE_LO
))
912 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
913 && (pinfo
& INSN_WRITE_HI
))))
916 /* The r4600 (ORION) chip has a bug: at least four instructions
917 are required between an instruction which accesses memory and
918 a certain set of CACHE instructions. Handle that now. */
920 && insns_since_cache_access
!= 0
921 && 5 - insns_since_cache_access
> nops
922 && ((ip
->insn_opcode
& 0xffff0000) == 0xbc0d0000
923 || (ip
->insn_opcode
& 0xffff0000) == 0xbc110000
924 || (ip
->insn_opcode
& 0xfc1f0000) == 0xbc150000
925 || (ip
->insn_opcode
& 0xffff0000) == 0xbc190000))
926 nops
= 5 - insns_since_cache_access
;
928 /* If we are being given a nop instruction, don't bother with
929 one of the nops we would otherwise output. This will only
930 happen when a nop instruction is used with mips_optimize set
932 if (nops
> 0 && ip
->insn_opcode
== 0)
935 /* Now emit the right number of NOP instructions. */
940 for (i
= 0; i
< nops
; i
++)
943 listing_prev_line ();
944 if (insn_label
!= NULL
)
946 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
947 insn_label
->sy_frag
= frag_now
;
948 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
958 if (address_expr
!= NULL
)
960 if (address_expr
->X_op
== O_constant
)
965 ip
->insn_opcode
|= address_expr
->X_add_number
;
969 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
972 case BFD_RELOC_MIPS_JMP
:
973 case BFD_RELOC_16_PCREL_S2
:
982 assert (reloc_type
!= BFD_RELOC_UNUSED
);
984 /* Don't generate a reloc if we are writing into a variant
987 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
989 reloc_type
== BFD_RELOC_16_PCREL_S2
,
994 md_number_to_chars (f
, ip
->insn_opcode
, 4);
996 /* Update the register mask information. */
997 if (pinfo
& INSN_WRITE_GPR_D
)
998 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
999 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1000 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1001 if (pinfo
& INSN_READ_GPR_S
)
1002 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1003 if (pinfo
& INSN_WRITE_GPR_31
)
1004 mips_gprmask
|= 1 << 31;
1005 if (pinfo
& INSN_WRITE_FPR_D
)
1006 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1007 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1008 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1009 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1010 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1011 if (pinfo
& INSN_COP
)
1013 /* We don't keep enough information to sort these cases out. */
1015 /* Never set the bit for $0, which is always zero. */
1016 mips_gprmask
&=~ 1 << 0;
1018 if (place
== NULL
&& ! mips_noreorder
)
1020 /* Filling the branch delay slot is more complex. We try to
1021 switch the branch with the previous instruction, which we can
1022 do if the previous instruction does not set up a condition
1023 that the branch tests and if the branch is not itself the
1024 target of any branch. */
1025 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1026 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1028 if (mips_optimize
< 2
1029 /* If we have seen .set volatile or .set nomove, don't
1032 /* If we had to emit any NOP instructions, then we
1033 already know we can not swap. */
1035 /* If we don't even know the previous insn, we can not
1037 || ! prev_insn_valid
1038 /* If the previous insn is already in a branch delay
1039 slot, then we can not swap. */
1040 || prev_insn_is_delay_slot
1041 /* If the previous previous insn was in a .set
1042 noreorder, we can't swap. Actually, the MIPS
1043 assembler will swap in this situation. However, gcc
1044 configured -with-gnu-as will generate code like
1050 in which we can not swap the bne and INSN. If gcc is
1051 not configured -with-gnu-as, it does not output the
1052 .set pseudo-ops. We don't have to check
1053 prev_insn_unreordered, because prev_insn_valid will
1054 be 0 in that case. We don't want to use
1055 prev_prev_insn_valid, because we do want to be able
1056 to swap at the start of a function. */
1057 || prev_prev_insn_unreordered
1058 /* If the branch is itself the target of a branch, we
1059 can not swap. We cheat on this; all we check for is
1060 whether there is a label on this instruction. If
1061 there are any branches to anything other than a
1062 label, users must use .set noreorder. */
1063 || insn_label
!= NULL
1064 /* If the previous instruction is in a variant frag, we
1065 can not do the swap. */
1066 || prev_insn_frag
->fr_type
== rs_machine_dependent
1067 /* If the branch reads the condition codes, we don't
1068 even try to swap, because in the sequence
1073 we can not swap, and I don't feel like handling that
1075 || (pinfo
& INSN_READ_COND_CODE
)
1076 /* We can not swap with an instruction that requires a
1077 delay slot, becase the target of the branch might
1078 interfere with that instruction. */
1080 & (INSN_LOAD_COPROC_DELAY
1081 | INSN_COPROC_MOVE_DELAY
1082 | INSN_WRITE_COND_CODE
1087 & (INSN_LOAD_MEMORY_DELAY
1088 | INSN_COPROC_MEMORY_DELAY
)))
1089 /* We can not swap with a branch instruction. */
1091 & (INSN_UNCOND_BRANCH_DELAY
1092 | INSN_COND_BRANCH_DELAY
1093 | INSN_COND_BRANCH_LIKELY
))
1094 /* We do not swap with a trap instruction, since it
1095 complicates trap handlers to have the trap
1096 instruction be in a delay slot. */
1097 || (prev_pinfo
& INSN_TRAP
)
1098 /* If the branch reads a register that the previous
1099 instruction sets, we can not swap. */
1100 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1101 && insn_uses_reg (ip
,
1102 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1105 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1106 && insn_uses_reg (ip
,
1107 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1110 /* If the branch writes a register that the previous
1111 instruction sets, we can not swap (we know that
1112 branches write only to RD or to $31). */
1113 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1114 && (((pinfo
& INSN_WRITE_GPR_D
)
1115 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1116 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1117 || ((pinfo
& INSN_WRITE_GPR_31
)
1118 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1121 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1122 && (((pinfo
& INSN_WRITE_GPR_D
)
1123 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1124 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1125 || ((pinfo
& INSN_WRITE_GPR_31
)
1126 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1129 /* If the branch writes a register that the previous
1130 instruction reads, we can not swap (we know that
1131 branches only write to RD or to $31). */
1132 || ((pinfo
& INSN_WRITE_GPR_D
)
1133 && insn_uses_reg (&prev_insn
,
1134 ((ip
->insn_opcode
>> OP_SH_RD
)
1137 || ((pinfo
& INSN_WRITE_GPR_31
)
1138 && insn_uses_reg (&prev_insn
, 31, 0))
1139 /* If we are generating embedded PIC code, the branch
1140 might be expanded into a sequence which uses $at, so
1141 we can't swap with an instruction which reads it. */
1142 || (mips_pic
== EMBEDDED_PIC
1143 && insn_uses_reg (&prev_insn
, AT
, 0))
1144 /* If the previous previous instruction has a load
1145 delay, and sets a register that the branch reads, we
1147 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1149 && (prev_prev_insn
.insn_mo
->pinfo
1150 & INSN_LOAD_MEMORY_DELAY
)))
1151 && insn_uses_reg (ip
,
1152 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1156 /* We could do even better for unconditional branches to
1157 portions of this object file; we could pick up the
1158 instruction at the destination, put it in the delay
1159 slot, and bump the destination address. */
1161 /* Update the previous insn information. */
1162 prev_prev_insn
= *ip
;
1163 prev_insn
.insn_mo
= &dummy_opcode
;
1170 /* It looks like we can actually do the swap. */
1171 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1172 memcpy (temp
, prev_f
, 4);
1173 memcpy (prev_f
, f
, 4);
1174 memcpy (f
, temp
, 4);
1177 prev_insn_fixp
->fx_frag
= frag_now
;
1178 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1182 fixp
->fx_frag
= prev_insn_frag
;
1183 fixp
->fx_where
= prev_insn_where
;
1185 /* Update the previous insn information; leave prev_insn
1187 prev_prev_insn
= *ip
;
1189 prev_insn_is_delay_slot
= 1;
1191 /* If that was an unconditional branch, forget the previous
1192 insn information. */
1193 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1195 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1196 prev_insn
.insn_mo
= &dummy_opcode
;
1199 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1201 /* We don't yet optimize a branch likely. What we should do
1202 is look at the target, copy the instruction found there
1203 into the delay slot, and increment the branch to jump to
1204 the next instruction. */
1206 /* Update the previous insn information. */
1207 prev_prev_insn
= *ip
;
1208 prev_insn
.insn_mo
= &dummy_opcode
;
1212 /* Update the previous insn information. */
1214 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1216 prev_prev_insn
= prev_insn
;
1219 /* Any time we see a branch, we always fill the delay slot
1220 immediately; since this insn is not a branch, we know it
1221 is not in a delay slot. */
1222 prev_insn_is_delay_slot
= 0;
1225 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1226 prev_insn_unreordered
= 0;
1227 prev_insn_frag
= frag_now
;
1228 prev_insn_where
= f
- frag_now
->fr_literal
;
1229 prev_insn_fixp
= fixp
;
1230 prev_insn_valid
= 1;
1231 if ((pinfo
& INSN_LOAD_MEMORY_DELAY
) != 0
1232 || (pinfo
& INSN_STORE_MEMORY
) != 0)
1233 insns_since_cache_access
= 1;
1234 else if (insns_since_cache_access
!= 0)
1235 ++insns_since_cache_access
;
1238 /* We just output an insn, so the next one doesn't have a label. */
1242 /* This function forgets that there was any previous instruction or
1246 mips_no_prev_insn ()
1248 prev_insn
.insn_mo
= &dummy_opcode
;
1249 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1250 prev_insn_valid
= 0;
1251 prev_insn_is_delay_slot
= 0;
1252 prev_insn_unreordered
= 0;
1253 prev_prev_insn_unreordered
= 0;
1257 /* This function must be called whenever we turn on noreorder or emit
1258 something other than instructions. It inserts any NOPS which might
1259 be needed by the previous instruction, and clears the information
1260 kept for the previous instructions. */
1265 if (! mips_noreorder
)
1270 if ((prev_insn
.insn_mo
->pinfo
1271 & (INSN_LOAD_COPROC_DELAY
1272 | INSN_COPROC_MOVE_DELAY
1273 | INSN_WRITE_COND_CODE
1277 && (prev_insn
.insn_mo
->pinfo
1278 & (INSN_LOAD_MEMORY_DELAY
1279 | INSN_COPROC_MEMORY_DELAY
))))
1282 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1283 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1284 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1287 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1288 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1289 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1294 if (insn_label
!= NULL
)
1296 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1297 insn_label
->sy_frag
= frag_now
;
1298 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1303 mips_no_prev_insn ();
1306 /* Build an instruction created by a macro expansion. This is passed
1307 a pointer to the count of instructions created so far, an
1308 expression, the name of the instruction to build, an operand format
1309 string, and corresponding arguments. */
1313 macro_build (char *place
,
1319 #else /* ! defined (NO_STDARG) */
1321 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1328 #endif /* ! defined (NO_STDARG) */
1330 struct mips_cl_insn insn
;
1331 bfd_reloc_code_real_type r
;
1335 va_start (args
, fmt
);
1341 * If the macro is about to expand into a second instruction,
1342 * print a warning if needed. We need to pass ip as a parameter
1343 * to generate a better warning message here...
1345 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1346 as_warn ("Macro instruction expanded into multiple instructions");
1349 *counter
+= 1; /* bump instruction counter */
1351 r
= BFD_RELOC_UNUSED
;
1352 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1353 assert (insn
.insn_mo
);
1354 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1356 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1357 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1360 assert (insn
.insn_mo
->name
);
1361 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1363 insn
.insn_opcode
= insn
.insn_mo
->match
;
1379 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1385 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1390 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1395 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1402 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1406 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1410 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1417 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1423 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1424 assert (r
== BFD_RELOC_MIPS_GPREL
1425 || r
== BFD_RELOC_MIPS_LITERAL
1426 || r
== BFD_RELOC_LO16
1427 || r
== BFD_RELOC_MIPS_GOT16
1428 || r
== BFD_RELOC_MIPS_CALL16
1429 || (ep
->X_op
== O_subtract
1430 && now_seg
== text_section
1431 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1432 && r
== BFD_RELOC_PCREL_LO16
));
1436 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1438 && (ep
->X_op
== O_constant
1439 || (ep
->X_op
== O_symbol
1440 && (r
== BFD_RELOC_HI16_S
1441 || r
== BFD_RELOC_HI16
))
1442 || (ep
->X_op
== O_subtract
1443 && now_seg
== text_section
1444 && S_GET_SEGMENT (ep
->X_op_symbol
) == text_section
1445 && r
== BFD_RELOC_PCREL_HI16_S
)));
1446 if (ep
->X_op
== O_constant
)
1448 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1450 r
= BFD_RELOC_UNUSED
;
1455 assert (ep
!= NULL
);
1457 * This allows macro() to pass an immediate expression for
1458 * creating short branches without creating a symbol.
1459 * Note that the expression still might come from the assembly
1460 * input, in which case the value is not checked for range nor
1461 * is a relocation entry generated (yuck).
1463 if (ep
->X_op
== O_constant
)
1465 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1469 r
= BFD_RELOC_16_PCREL_S2
;
1473 assert (ep
!= NULL
);
1474 r
= BFD_RELOC_MIPS_JMP
;
1483 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1485 append_insn (place
, &insn
, ep
, r
);
1489 * Generate a "lui" instruction.
1492 macro_build_lui (place
, counter
, ep
, regnum
)
1498 expressionS high_expr
;
1499 struct mips_cl_insn insn
;
1500 bfd_reloc_code_real_type r
;
1501 CONST
char *name
= "lui";
1502 CONST
char *fmt
= "t,u";
1508 high_expr
.X_op
= O_constant
;
1509 high_expr
.X_add_number
= 0;
1512 if (high_expr
.X_op
== O_constant
)
1514 /* we can compute the instruction now without a relocation entry */
1515 if (high_expr
.X_add_number
& 0x8000)
1516 high_expr
.X_add_number
+= 0x10000;
1517 high_expr
.X_add_number
=
1518 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1519 r
= BFD_RELOC_UNUSED
;
1523 assert (ep
->X_op
== O_symbol
);
1524 /* _gp_disp is a special case, used from s_cpload. */
1525 assert (mips_pic
== NO_PIC
1526 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1527 r
= BFD_RELOC_HI16_S
;
1531 * If the macro is about to expand into a second instruction,
1532 * print a warning if needed. We need to pass ip as a parameter
1533 * to generate a better warning message here...
1535 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1536 as_warn ("Macro instruction expanded into multiple instructions");
1539 *counter
+= 1; /* bump instruction counter */
1541 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1542 assert (insn
.insn_mo
);
1543 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1544 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1546 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1547 if (r
== BFD_RELOC_UNUSED
)
1549 insn
.insn_opcode
|= high_expr
.X_add_number
;
1550 append_insn (place
, &insn
, NULL
, r
);
1553 append_insn (place
, &insn
, &high_expr
, r
);
1557 * Generates code to set the $at register to true (one)
1558 * if reg is less than the immediate expression.
1561 set_at (counter
, reg
, unsignedp
)
1566 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1567 macro_build ((char *) NULL
, counter
, &imm_expr
,
1568 unsignedp
? "sltiu" : "slti",
1569 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1572 load_register (counter
, AT
, &imm_expr
);
1573 macro_build ((char *) NULL
, counter
, NULL
,
1574 unsignedp
? "sltu" : "slt",
1575 "d,v,t", AT
, reg
, AT
);
1579 /* Warn if an expression is not a constant. */
1582 check_absolute_expr (ip
, ex
)
1583 struct mips_cl_insn
*ip
;
1586 if (ex
->X_op
!= O_constant
)
1587 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1591 * This routine generates the least number of instructions neccessary to load
1592 * an absolute expression value into a register.
1595 load_register (counter
, reg
, ep
)
1600 assert (ep
->X_op
== O_constant
);
1601 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1602 macro_build ((char *) NULL
, counter
, ep
,
1603 mips_isa
< 3 ? "addiu" : "daddiu",
1604 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1605 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1606 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1607 (int) BFD_RELOC_LO16
);
1608 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1609 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1610 == ~ (offsetT
) 0x7fffffff))
1612 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1613 (int) BFD_RELOC_HI16
);
1614 if ((ep
->X_add_number
& 0xffff) != 0)
1615 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1616 (int) BFD_RELOC_LO16
);
1618 else if (mips_isa
< 3)
1620 as_bad ("Number larger than 32 bits");
1621 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1622 (int) BFD_RELOC_LO16
);
1627 expressionS hi32
, lo32
;
1631 hi32
.X_add_number
>>= shift
;
1632 hi32
.X_add_number
&= 0xffffffff;
1633 if ((hi32
.X_add_number
& 0x80000000) != 0)
1634 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1635 load_register (counter
, reg
, &hi32
);
1637 lo32
.X_add_number
&= 0xffffffff;
1638 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1639 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1645 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1648 mid16
.X_add_number
>>= 16;
1649 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1650 reg
, (int) BFD_RELOC_LO16
);
1651 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1654 if ((lo32
.X_add_number
& 0xffff) != 0)
1655 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1656 (int) BFD_RELOC_LO16
);
1660 /* Load an address into a register. */
1663 load_address (counter
, reg
, ep
)
1670 if (ep
->X_op
!= O_constant
1671 && ep
->X_op
!= O_symbol
)
1673 as_bad ("expression too complex");
1674 ep
->X_op
= O_constant
;
1677 if (ep
->X_op
== O_constant
)
1679 load_register (counter
, reg
, ep
);
1683 if (mips_pic
== NO_PIC
)
1685 /* If this is a reference to a GP relative symbol, we want
1686 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1688 lui $reg,<sym> (BFD_RELOC_HI16_S)
1689 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1690 If we have an addend, we always use the latter form. */
1691 if (ep
->X_add_number
!= 0)
1696 macro_build ((char *) NULL
, counter
, ep
,
1697 mips_isa
< 3 ? "addiu" : "daddiu",
1698 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1699 p
= frag_var (rs_machine_dependent
, 8, 0,
1700 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1701 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1703 macro_build_lui (p
, counter
, ep
, reg
);
1706 macro_build (p
, counter
, ep
,
1707 mips_isa
< 3 ? "addiu" : "daddiu",
1708 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1710 else if (mips_pic
== SVR4_PIC
)
1714 /* If this is a reference to an external symbol, we want
1715 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1717 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1719 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1720 If there is a constant, it must be added in after. */
1721 ex
.X_add_number
= ep
->X_add_number
;
1722 ep
->X_add_number
= 0;
1724 macro_build ((char *) NULL
, counter
, ep
,
1725 mips_isa
< 3 ? "lw" : "ld",
1726 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1727 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1728 p
= frag_var (rs_machine_dependent
, 4, 0,
1729 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1730 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1731 macro_build (p
, counter
, ep
,
1732 mips_isa
< 3 ? "addiu" : "daddiu",
1733 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1734 if (ex
.X_add_number
!= 0)
1736 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1737 as_bad ("PIC code offset overflow (max 16 signed bits)");
1738 ex
.X_op
= O_constant
;
1739 macro_build (p
, counter
, &ex
,
1740 mips_isa
< 3 ? "addiu" : "daddiu",
1741 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1744 else if (mips_pic
== EMBEDDED_PIC
)
1747 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1749 macro_build ((char *) NULL
, counter
, ep
,
1750 mips_isa
< 3 ? "addiu" : "daddiu",
1751 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1759 * This routine implements the seemingly endless macro or synthesized
1760 * instructions and addressing modes in the mips assembly language. Many
1761 * of these macros are simple and are similar to each other. These could
1762 * probably be handled by some kind of table or grammer aproach instead of
1763 * this verbose method. Others are not simple macros but are more like
1764 * optimizing code generation.
1765 * One interesting optimization is when several store macros appear
1766 * consecutivly that would load AT with the upper half of the same address.
1767 * The ensuing load upper instructions are ommited. This implies some kind
1768 * of global optimization. We currently only optimize within a single macro.
1769 * For many of the load and store macros if the address is specified as a
1770 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1771 * first load register 'at' with zero and use it as the base register. The
1772 * mips assembler simply uses register $zero. Just one tiny optimization
1777 struct mips_cl_insn
*ip
;
1779 register int treg
, sreg
, dreg
, breg
;
1792 bfd_reloc_code_real_type r
;
1794 int hold_mips_optimize
;
1796 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1797 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1798 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1799 mask
= ip
->insn_mo
->mask
;
1801 expr1
.X_op
= O_constant
;
1802 expr1
.X_op_symbol
= NULL
;
1803 expr1
.X_add_symbol
= NULL
;
1804 expr1
.X_add_number
= 1;
1816 mips_emit_delays ();
1818 mips_any_noreorder
= 1;
1820 expr1
.X_add_number
= 8;
1821 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1823 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1825 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1826 macro_build ((char *) NULL
, &icnt
, NULL
,
1827 dbl
? "dsub" : "sub",
1828 "d,v,t", dreg
, 0, sreg
);
1851 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1853 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1854 (int) BFD_RELOC_LO16
);
1857 load_register (&icnt
, AT
, &imm_expr
);
1858 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1877 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1879 if (mask
!= M_NOR_I
)
1880 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1881 sreg
, (int) BFD_RELOC_LO16
);
1884 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1885 treg
, sreg
, (int) BFD_RELOC_LO16
);
1886 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1892 load_register (&icnt
, AT
, &imm_expr
);
1893 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1910 if (imm_expr
.X_add_number
== 0)
1912 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1916 load_register (&icnt
, AT
, &imm_expr
);
1917 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1925 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1926 likely
? "bgezl" : "bgez",
1932 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1933 likely
? "blezl" : "blez",
1937 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1938 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1939 likely
? "beql" : "beq",
1946 /* check for > max integer */
1947 maxnum
= 0x7fffffff;
1955 if (imm_expr
.X_add_number
>= maxnum
)
1958 /* result is always false */
1961 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1962 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1966 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1967 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1972 imm_expr
.X_add_number
++;
1976 if (mask
== M_BGEL_I
)
1978 if (imm_expr
.X_add_number
== 0)
1980 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1981 likely
? "bgezl" : "bgez",
1985 if (imm_expr
.X_add_number
== 1)
1987 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1988 likely
? "bgtzl" : "bgtz",
1992 maxnum
= 0x7fffffff;
2000 maxnum
= - maxnum
- 1;
2001 if (imm_expr
.X_add_number
<= maxnum
)
2004 /* result is always true */
2005 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2006 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2009 set_at (&icnt
, sreg
, 0);
2010 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2011 likely
? "beql" : "beq",
2022 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2023 likely
? "beql" : "beq",
2027 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2029 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2030 likely
? "beql" : "beq",
2037 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2039 imm_expr
.X_add_number
++;
2043 if (mask
== M_BGEUL_I
)
2045 if (imm_expr
.X_add_number
== 0)
2047 if (imm_expr
.X_add_number
== 1)
2049 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2050 likely
? "bnel" : "bne",
2054 set_at (&icnt
, sreg
, 1);
2055 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2056 likely
? "beql" : "beq",
2065 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2066 likely
? "bgtzl" : "bgtz",
2072 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2073 likely
? "bltzl" : "bltz",
2077 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2078 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2079 likely
? "bnel" : "bne",
2088 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2089 likely
? "bnel" : "bne",
2095 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2097 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2098 likely
? "bnel" : "bne",
2107 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2108 likely
? "blezl" : "blez",
2114 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2115 likely
? "bgezl" : "bgez",
2119 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2120 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2121 likely
? "beql" : "beq",
2128 maxnum
= 0x7fffffff;
2136 if (imm_expr
.X_add_number
>= maxnum
)
2138 imm_expr
.X_add_number
++;
2142 if (mask
== M_BLTL_I
)
2144 if (imm_expr
.X_add_number
== 0)
2146 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2147 likely
? "bltzl" : "bltz",
2151 if (imm_expr
.X_add_number
== 1)
2153 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2154 likely
? "blezl" : "blez",
2158 set_at (&icnt
, sreg
, 0);
2159 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2160 likely
? "bnel" : "bne",
2169 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2170 likely
? "beql" : "beq",
2176 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2178 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2179 likely
? "beql" : "beq",
2186 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2188 imm_expr
.X_add_number
++;
2192 if (mask
== M_BLTUL_I
)
2194 if (imm_expr
.X_add_number
== 0)
2196 if (imm_expr
.X_add_number
== 1)
2198 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2199 likely
? "beql" : "beq",
2203 set_at (&icnt
, sreg
, 1);
2204 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2205 likely
? "bnel" : "bne",
2214 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2215 likely
? "bltzl" : "bltz",
2221 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2222 likely
? "bgtzl" : "bgtz",
2226 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2227 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2228 likely
? "bnel" : "bne",
2239 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2240 likely
? "bnel" : "bne",
2244 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2246 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2247 likely
? "bnel" : "bne",
2263 as_warn ("Divide by zero.");
2265 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2267 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2271 mips_emit_delays ();
2273 mips_any_noreorder
= 1;
2274 macro_build ((char *) NULL
, &icnt
, NULL
,
2275 dbl
? "ddiv" : "div",
2276 "z,s,t", sreg
, treg
);
2278 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2281 expr1
.X_add_number
= 8;
2282 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2283 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2284 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2286 expr1
.X_add_number
= -1;
2287 macro_build ((char *) NULL
, &icnt
, &expr1
,
2288 dbl
? "daddiu" : "addiu",
2289 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2290 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2291 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2294 expr1
.X_add_number
= 1;
2295 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2296 (int) BFD_RELOC_LO16
);
2297 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2302 expr1
.X_add_number
= 0x80000000;
2303 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2304 (int) BFD_RELOC_HI16
);
2307 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2310 expr1
.X_add_number
= 8;
2311 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2312 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2313 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2316 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2355 if (imm_expr
.X_add_number
== 0)
2357 as_warn ("Divide by zero.");
2359 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2361 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2364 if (imm_expr
.X_add_number
== 1)
2366 if (strcmp (s2
, "mflo") == 0)
2367 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2370 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2373 if (imm_expr
.X_add_number
== -1
2374 && s
[strlen (s
) - 1] != 'u')
2376 if (strcmp (s2
, "mflo") == 0)
2379 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2382 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2386 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2390 load_register (&icnt
, AT
, &imm_expr
);
2391 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2392 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2411 mips_emit_delays ();
2413 mips_any_noreorder
= 1;
2414 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2416 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2419 expr1
.X_add_number
= 8;
2420 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2421 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2422 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2425 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2429 /* Load the address of a symbol into a register. If breg is not
2430 zero, we then add a base register to it. */
2432 /* When generating embedded PIC code, we permit expressions of
2435 where bar is an address in the .text section. These are used
2436 when getting the addresses of functions. We don't permit
2437 X_add_number to be non-zero, because if the symbol is
2438 external the relaxing code needs to know that any addend is
2439 purely the offset to X_op_symbol. */
2440 if (mips_pic
== EMBEDDED_PIC
2441 && offset_expr
.X_op
== O_subtract
2442 && now_seg
== text_section
2443 && S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2445 && offset_expr
.X_add_number
== 0)
2447 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2448 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2449 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2450 mips_isa
< 3 ? "addiu" : "daddiu",
2451 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2455 if (offset_expr
.X_op
!= O_symbol
2456 && offset_expr
.X_op
!= O_constant
)
2458 as_bad ("expression too complex");
2459 offset_expr
.X_op
= O_constant
;
2473 if (offset_expr
.X_op
== O_constant
)
2474 load_register (&icnt
, tempreg
, &offset_expr
);
2475 else if (mips_pic
== NO_PIC
)
2477 /* If this is a reference to an GP relative symbol, we want
2478 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2480 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2481 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2482 If we have a constant, we need two instructions anyhow,
2483 so we may as well always use the latter form. */
2484 if (offset_expr
.X_add_number
!= 0)
2489 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2490 mips_isa
< 3 ? "addiu" : "daddiu",
2491 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2492 p
= frag_var (rs_machine_dependent
, 8, 0,
2493 RELAX_ENCODE (4, 8, 0, 4, 0,
2494 mips_warn_about_macros
),
2495 offset_expr
.X_add_symbol
, (long) 0,
2498 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2501 macro_build (p
, &icnt
, &offset_expr
,
2502 mips_isa
< 3 ? "addiu" : "daddiu",
2503 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2505 else if (mips_pic
== SVR4_PIC
)
2507 /* If this is a reference to an external symbol, and there
2508 is no constant, we want
2509 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2510 For a local symbol, we want
2511 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2513 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2515 If we have a small constant, and this is a reference to
2516 an external symbol, we want
2517 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2519 addiu $tempreg,$tempreg,<constant>
2520 For a local symbol, we want the same instruction
2521 sequence, but we output a BFD_RELOC_LO16 reloc on the
2524 If we have a large constant, and this is a reference to
2525 an external symbol, we want
2526 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2527 lui $at,<hiconstant>
2528 addiu $at,$at,<loconstant>
2529 addu $tempreg,$tempreg,$at
2530 For a local symbol, we want the same instruction
2531 sequence, but we output a BFD_RELOC_LO16 reloc on the
2532 addiu instruction. */
2533 expr1
.X_add_number
= offset_expr
.X_add_number
;
2534 offset_expr
.X_add_number
= 0;
2536 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2537 mips_isa
< 3 ? "lw" : "ld",
2538 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2539 if (expr1
.X_add_number
== 0)
2547 /* We're going to put in an addu instruction using
2548 tempreg, so we may as well insert the nop right
2550 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2554 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2555 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2557 ? mips_warn_about_macros
2559 offset_expr
.X_add_symbol
, (long) 0,
2563 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2566 macro_build (p
, &icnt
, &expr1
,
2567 mips_isa
< 3 ? "addiu" : "daddiu",
2568 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2569 /* FIXME: If breg == 0, and the next instruction uses
2570 $tempreg, then if this variant case is used an extra
2571 nop will be generated. */
2573 else if (expr1
.X_add_number
>= -0x8000
2574 && expr1
.X_add_number
< 0x8000)
2576 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2578 macro_build ((char *) NULL
, &icnt
, &expr1
,
2579 mips_isa
< 3 ? "addiu" : "daddiu",
2580 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2581 (void) frag_var (rs_machine_dependent
, 0, 0,
2582 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2583 offset_expr
.X_add_symbol
, (long) 0,
2590 /* If we are going to add in a base register, and the
2591 target register and the base register are the same,
2592 then we are using AT as a temporary register. Since
2593 we want to load the constant into AT, we add our
2594 current AT (from the global offset table) and the
2595 register into the register now, and pretend we were
2596 not using a base register. */
2601 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2603 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2604 mips_isa
< 3 ? "addu" : "daddu",
2605 "d,v,t", treg
, AT
, breg
);
2611 /* Set mips_optimize around the lui instruction to avoid
2612 inserting an unnecessary nop after the lw. */
2613 hold_mips_optimize
= mips_optimize
;
2615 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2616 mips_optimize
= hold_mips_optimize
;
2618 macro_build ((char *) NULL
, &icnt
, &expr1
,
2619 mips_isa
< 3 ? "addiu" : "daddiu",
2620 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2621 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2622 mips_isa
< 3 ? "addu" : "daddu",
2623 "d,v,t", tempreg
, tempreg
, AT
);
2624 (void) frag_var (rs_machine_dependent
, 0, 0,
2625 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2626 offset_expr
.X_add_symbol
, (long) 0,
2631 else if (mips_pic
== EMBEDDED_PIC
)
2634 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2636 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2637 mips_isa
< 3 ? "addiu" : "daddiu",
2638 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2644 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2645 mips_isa
< 3 ? "addu" : "daddu",
2646 "d,v,t", treg
, tempreg
, breg
);
2654 /* The j instruction may not be used in PIC code, since it
2655 requires an absolute address. We convert it to a b
2657 if (mips_pic
== NO_PIC
)
2658 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2660 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2663 /* The jal instructions must be handled as macros because when
2664 generating PIC code they expand to multi-instruction
2665 sequences. Normally they are simple instructions. */
2670 if (mips_pic
== NO_PIC
2671 || mips_pic
== EMBEDDED_PIC
)
2672 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2674 else if (mips_pic
== SVR4_PIC
)
2676 if (sreg
!= PIC_CALL_REG
)
2677 as_warn ("MIPS PIC call to register other than $25");
2679 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2681 if (mips_cprestore_offset
< 0)
2682 as_warn ("No .cprestore pseudo-op used in PIC code");
2685 expr1
.X_add_number
= mips_cprestore_offset
;
2686 macro_build ((char *) NULL
, &icnt
, &expr1
,
2687 mips_isa
< 3 ? "lw" : "ld",
2688 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2697 if (mips_pic
== NO_PIC
)
2698 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2699 else if (mips_pic
== SVR4_PIC
)
2701 /* If this is a reference to an external symbol, we want
2702 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2706 lw $gp,cprestore($sp)
2707 The cprestore value is set using the .cprestore
2708 pseudo-op. If the symbol is not external, we want
2709 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2711 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2714 lw $gp,cprestore($sp)
2717 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2718 mips_isa
< 3 ? "lw" : "ld",
2719 "t,o(b)", PIC_CALL_REG
,
2720 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2721 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2722 p
= frag_var (rs_machine_dependent
, 4, 0,
2723 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2724 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2725 macro_build (p
, &icnt
, &offset_expr
,
2726 mips_isa
< 3 ? "addiu" : "daddiu",
2727 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2728 (int) BFD_RELOC_LO16
);
2729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2730 "jalr", "s", PIC_CALL_REG
);
2731 if (mips_cprestore_offset
< 0)
2732 as_warn ("No .cprestore pseudo-op used in PIC code");
2736 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2738 expr1
.X_add_number
= mips_cprestore_offset
;
2739 macro_build ((char *) NULL
, &icnt
, &expr1
,
2740 mips_isa
< 3 ? "lw" : "ld",
2741 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2745 else if (mips_pic
== EMBEDDED_PIC
)
2747 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2748 /* The linker may expand the call to a longer sequence which
2749 uses $at, so we must break rather than return. */
2821 if (breg
== treg
|| coproc
)
2890 if (mask
== M_LWC1_AB
2891 || mask
== M_SWC1_AB
2892 || mask
== M_LDC1_AB
2893 || mask
== M_SDC1_AB
2902 if (offset_expr
.X_op
!= O_constant
2903 && offset_expr
.X_op
!= O_symbol
)
2905 as_bad ("expression too complex");
2906 offset_expr
.X_op
= O_constant
;
2909 /* A constant expression in PIC code can be handled just as it
2910 is in non PIC code. */
2911 if (mips_pic
== NO_PIC
2912 || offset_expr
.X_op
== O_constant
)
2914 /* If this is a reference to a GP relative symbol, and there
2915 is no base register, we want
2916 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2917 Otherwise, if there is no base register, we want
2918 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2919 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2920 If we have a constant, we need two instructions anyhow,
2921 so we always use the latter form.
2923 If we have a base register, and this is a reference to a
2924 GP relative symbol, we want
2925 addu $tempreg,$breg,$gp
2926 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2928 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2929 addu $tempreg,$tempreg,$breg
2930 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2931 With a constant we always use the latter case. */
2934 if (offset_expr
.X_add_number
!= 0)
2939 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2940 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2941 p
= frag_var (rs_machine_dependent
, 8, 0,
2942 RELAX_ENCODE (4, 8, 0, 4, 0,
2943 (mips_warn_about_macros
2944 || (used_at
&& mips_noat
))),
2945 offset_expr
.X_add_symbol
, (long) 0,
2949 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2952 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2953 (int) BFD_RELOC_LO16
, tempreg
);
2957 if (offset_expr
.X_add_number
!= 0)
2962 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2963 mips_isa
< 3 ? "addu" : "daddu",
2964 "d,v,t", tempreg
, breg
, GP
);
2965 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2966 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2967 p
= frag_var (rs_machine_dependent
, 12, 0,
2968 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2969 offset_expr
.X_add_symbol
, (long) 0,
2972 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2975 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2976 mips_isa
< 3 ? "addu" : "daddu",
2977 "d,v,t", tempreg
, tempreg
, breg
);
2980 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2981 (int) BFD_RELOC_LO16
, tempreg
);
2984 else if (mips_pic
== SVR4_PIC
)
2986 /* If this is a reference to an external symbol, we want
2987 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2989 <op> $treg,0($tempreg)
2991 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2993 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2994 <op> $treg,0($tempreg)
2995 If there is a base register, we add it to $tempreg before
2996 the <op>. If there is a constant, we stick it in the
2997 <op> instruction. We don't handle constants larger than
2998 16 bits, because we have no way to load the upper 16 bits
2999 (actually, we could handle them for the subset of cases
3000 in which we are not using $at). */
3001 assert (offset_expr
.X_op
== O_symbol
);
3002 expr1
.X_add_number
= offset_expr
.X_add_number
;
3003 offset_expr
.X_add_number
= 0;
3004 if (expr1
.X_add_number
< -0x8000
3005 || expr1
.X_add_number
>= 0x8000)
3006 as_bad ("PIC code offset overflow (max 16 signed bits)");
3008 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3009 mips_isa
< 3 ? "lw" : "ld",
3010 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3011 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3012 p
= frag_var (rs_machine_dependent
, 4, 0,
3013 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3014 offset_expr
.X_add_symbol
, (long) 0,
3016 macro_build (p
, &icnt
, &offset_expr
,
3017 mips_isa
< 3 ? "addiu" : "daddiu",
3018 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3020 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3021 mips_isa
< 3 ? "addu" : "daddu",
3022 "d,v,t", tempreg
, tempreg
, breg
);
3023 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3024 (int) BFD_RELOC_LO16
, tempreg
);
3026 else if (mips_pic
== EMBEDDED_PIC
)
3028 /* If there is no base register, we want
3029 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3030 If there is a base register, we want
3031 addu $tempreg,$breg,$gp
3032 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3034 assert (offset_expr
.X_op
== O_symbol
);
3037 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3038 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3043 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3044 mips_isa
< 3 ? "addu" : "daddu",
3045 "d,v,t", tempreg
, breg
, GP
);
3046 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3047 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3060 load_register (&icnt
, treg
, &imm_expr
);
3064 if (imm_expr
.X_op
== O_constant
)
3066 load_register (&icnt
, AT
, &imm_expr
);
3067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3068 "mtc1", "t,G", AT
, treg
);
3073 assert (offset_expr
.X_op
== O_symbol
3074 && strcmp (segment_name (S_GET_SEGMENT
3075 (offset_expr
.X_add_symbol
)),
3077 && offset_expr
.X_add_number
== 0);
3078 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3079 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3084 /* We know that sym is in the .rdata section. First we get the
3085 upper 16 bits of the address. */
3086 if (mips_pic
== NO_PIC
)
3088 /* FIXME: This won't work for a 64 bit address. */
3089 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3091 else if (mips_pic
== SVR4_PIC
)
3093 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3094 mips_isa
< 3 ? "lw" : "ld",
3095 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3097 else if (mips_pic
== EMBEDDED_PIC
)
3099 /* For embedded PIC we pick up the entire address off $gp in
3100 a single instruction. */
3101 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3102 mips_isa
< 3 ? "addiu" : "daddiu",
3103 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3104 offset_expr
.X_op
= O_constant
;
3105 offset_expr
.X_add_number
= 0;
3110 /* Now we load the register(s). */
3112 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3113 treg
, (int) BFD_RELOC_LO16
, AT
);
3116 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3117 treg
, (int) BFD_RELOC_LO16
, AT
);
3120 /* FIXME: How in the world do we deal with the possible
3122 offset_expr
.X_add_number
+= 4;
3123 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3124 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3128 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3129 does not become a variant frag. */
3130 frag_wane (frag_now
);
3136 assert (offset_expr
.X_op
== O_symbol
3137 && offset_expr
.X_add_number
== 0);
3138 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3139 if (strcmp (s
, ".lit8") == 0)
3143 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3144 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3148 r
= BFD_RELOC_MIPS_LITERAL
;
3153 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3154 if (mips_pic
== SVR4_PIC
)
3155 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3156 mips_isa
< 3 ? "lw" : "ld",
3157 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3160 /* FIXME: This won't work for a 64 bit address. */
3161 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3166 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3167 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3176 /* Even on a big endian machine $fn comes before $fn+1. We have
3177 to adjust when loading from memory. */
3180 assert (mips_isa
< 2);
3181 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3182 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3184 /* FIXME: A possible overflow which I don't know how to deal
3186 offset_expr
.X_add_number
+= 4;
3187 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3188 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3191 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3192 does not become a variant frag. */
3193 frag_wane (frag_now
);
3202 * The MIPS assembler seems to check for X_add_number not
3203 * being double aligned and generating:
3206 * addiu at,at,%lo(foo+1)
3209 * But, the resulting address is the same after relocation so why
3210 * generate the extra instruction?
3257 if (offset_expr
.X_op
!= O_symbol
3258 && offset_expr
.X_op
!= O_constant
)
3260 as_bad ("expression too complex");
3261 offset_expr
.X_op
= O_constant
;
3264 /* Even on a big endian machine $fn comes before $fn+1. We have
3265 to adjust when loading from memory. We set coproc if we must
3266 load $fn+1 first. */
3267 if (byte_order
== LITTLE_ENDIAN
)
3270 if (mips_pic
== NO_PIC
3271 || offset_expr
.X_op
== O_constant
)
3273 /* If this is a reference to a GP relative symbol, we want
3274 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3275 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3276 If we have a base register, we use this
3278 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3279 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3280 If this is not a GP relative symbol, we want
3281 lui $at,<sym> (BFD_RELOC_HI16_S)
3282 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3283 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3284 If there is a base register, we add it to $at after the
3285 lui instruction. If there is a constant, we always use
3287 if (offset_expr
.X_add_number
!= 0)
3306 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3307 mips_isa
< 3 ? "addu" : "daddu",
3308 "d,v,t", AT
, breg
, GP
);
3314 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3315 coproc
? treg
+ 1 : treg
,
3316 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3317 offset_expr
.X_add_number
+= 4;
3319 /* Set mips_optimize to 2 to avoid inserting an
3321 hold_mips_optimize
= mips_optimize
;
3323 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3324 coproc
? treg
: treg
+ 1,
3325 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3326 mips_optimize
= hold_mips_optimize
;
3328 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3329 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3330 used_at
&& mips_noat
),
3331 offset_expr
.X_add_symbol
, (long) 0,
3334 /* We just generated two relocs. When tc_gen_reloc
3335 handles this case, it will skip the first reloc and
3336 handle the second. The second reloc already has an
3337 extra addend of 4, which we added above. We must
3338 subtract it out, and then subtract another 4 to make
3339 the first reloc come out right. The second reloc
3340 will come out right because we are going to add 4 to
3341 offset_expr when we build its instruction below. */
3342 offset_expr
.X_add_number
-= 8;
3343 offset_expr
.X_op
= O_constant
;
3345 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3350 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3351 mips_isa
< 3 ? "addu" : "daddu",
3352 "d,v,t", AT
, breg
, AT
);
3356 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3357 coproc
? treg
+ 1 : treg
,
3358 (int) BFD_RELOC_LO16
, AT
);
3361 /* FIXME: How do we handle overflow here? */
3362 offset_expr
.X_add_number
+= 4;
3363 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3364 coproc
? treg
: treg
+ 1,
3365 (int) BFD_RELOC_LO16
, AT
);
3367 else if (mips_pic
== SVR4_PIC
)
3371 /* If this is a reference to an external symbol, we want
3372 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3377 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3379 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3380 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3381 If there is a base register we add it to $at before the
3382 lwc1 instructions. If there is a constant we include it
3383 in the lwc1 instructions. */
3385 expr1
.X_add_number
= offset_expr
.X_add_number
;
3386 offset_expr
.X_add_number
= 0;
3387 if (expr1
.X_add_number
< -0x8000
3388 || expr1
.X_add_number
>= 0x8000 - 4)
3389 as_bad ("PIC code offset overflow (max 16 signed bits)");
3394 frag_grow (24 + off
);
3395 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3396 mips_isa
< 3 ? "lw" : "ld",
3397 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3398 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3400 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3401 mips_isa
< 3 ? "addu" : "daddu",
3402 "d,v,t", AT
, breg
, AT
);
3403 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3404 coproc
? treg
+ 1 : treg
,
3405 (int) BFD_RELOC_LO16
, AT
);
3406 expr1
.X_add_number
+= 4;
3408 /* Set mips_optimize to 2 to avoid inserting an undesired
3410 hold_mips_optimize
= mips_optimize
;
3412 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3413 coproc
? treg
: treg
+ 1,
3414 (int) BFD_RELOC_LO16
, AT
);
3415 mips_optimize
= hold_mips_optimize
;
3417 (void) frag_var (rs_machine_dependent
, 0, 0,
3418 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3419 offset_expr
.X_add_symbol
, (long) 0,
3422 else if (mips_pic
== EMBEDDED_PIC
)
3424 /* If there is no base register, we use
3425 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3426 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3427 If we have a base register, we use
3429 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3430 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3440 mips_isa
< 3 ? "addu" : "daddu",
3441 "d,v,t", AT
, breg
, GP
);
3446 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3447 coproc
? treg
+ 1 : treg
,
3448 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3449 offset_expr
.X_add_number
+= 4;
3450 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3451 coproc
? treg
: treg
+ 1,
3452 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3468 assert (mips_isa
< 3);
3469 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3470 (int) BFD_RELOC_LO16
, breg
);
3471 offset_expr
.X_add_number
+= 4;
3472 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3473 (int) BFD_RELOC_LO16
, breg
);
3475 #ifdef LOSING_COMPILER
3481 as_warn ("Macro used $at after \".set noat\"");
3486 struct mips_cl_insn
*ip
;
3488 register int treg
, sreg
, dreg
, breg
;
3501 bfd_reloc_code_real_type r
;
3504 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3505 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3506 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3507 mask
= ip
->insn_mo
->mask
;
3509 expr1
.X_op
= O_constant
;
3510 expr1
.X_op_symbol
= NULL
;
3511 expr1
.X_add_symbol
= NULL
;
3512 expr1
.X_add_number
= 1;
3516 #endif /* LOSING_COMPILER */
3521 macro_build ((char *) NULL
, &icnt
, NULL
,
3522 dbl
? "dmultu" : "multu",
3524 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3530 /* The MIPS assembler some times generates shifts and adds. I'm
3531 not trying to be that fancy. GCC should do this for us
3533 load_register (&icnt
, AT
, &imm_expr
);
3534 macro_build ((char *) NULL
, &icnt
, NULL
,
3535 dbl
? "dmult" : "mult",
3537 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3543 mips_emit_delays ();
3545 mips_any_noreorder
= 1;
3546 macro_build ((char *) NULL
, &icnt
, NULL
,
3547 dbl
? "dmult" : "mult",
3549 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3550 macro_build ((char *) NULL
, &icnt
, NULL
,
3551 dbl
? "dsra32" : "sra",
3552 "d,w,<", dreg
, dreg
, 31);
3553 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3555 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3558 expr1
.X_add_number
= 8;
3559 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3560 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3561 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3564 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3570 mips_emit_delays ();
3572 mips_any_noreorder
= 1;
3573 macro_build ((char *) NULL
, &icnt
, NULL
,
3574 dbl
? "dmultu" : "multu",
3576 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3577 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3579 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3582 expr1
.X_add_number
= 8;
3583 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3584 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3585 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3591 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3592 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3593 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3595 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3599 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3600 imm_expr
.X_add_number
& 0x1f);
3601 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3602 (0 - imm_expr
.X_add_number
) & 0x1f);
3603 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3607 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3608 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3609 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3611 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3615 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3616 imm_expr
.X_add_number
& 0x1f);
3617 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3618 (0 - imm_expr
.X_add_number
) & 0x1f);
3619 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3623 assert (mips_isa
< 2);
3624 /* Even on a big endian machine $fn comes before $fn+1. We have
3625 to adjust when storing to memory. */
3626 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3627 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3628 (int) BFD_RELOC_LO16
, breg
);
3629 offset_expr
.X_add_number
+= 4;
3630 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3631 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3632 (int) BFD_RELOC_LO16
, breg
);
3637 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3638 treg
, (int) BFD_RELOC_LO16
);
3640 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3641 sreg
, (int) BFD_RELOC_LO16
);
3644 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3646 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3647 dreg
, (int) BFD_RELOC_LO16
);
3652 if (imm_expr
.X_add_number
== 0)
3654 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3655 sreg
, (int) BFD_RELOC_LO16
);
3660 as_warn ("Instruction %s: result is always false",
3662 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3665 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3667 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3668 sreg
, (int) BFD_RELOC_LO16
);
3671 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3673 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3674 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3675 mips_isa
< 3 ? "addiu" : "daddiu",
3676 "t,r,j", dreg
, sreg
,
3677 (int) BFD_RELOC_LO16
);
3682 load_register (&icnt
, AT
, &imm_expr
);
3683 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3687 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3688 (int) BFD_RELOC_LO16
);
3693 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3699 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3700 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3701 (int) BFD_RELOC_LO16
);
3704 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3706 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3708 macro_build ((char *) NULL
, &icnt
, &expr1
,
3709 mask
== M_SGE_I
? "slti" : "sltiu",
3710 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3715 load_register (&icnt
, AT
, &imm_expr
);
3716 macro_build ((char *) NULL
, &icnt
, NULL
,
3717 mask
== M_SGE_I
? "slt" : "sltu",
3718 "d,v,t", dreg
, sreg
, AT
);
3721 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3722 (int) BFD_RELOC_LO16
);
3727 case M_SGT
: /* sreg > treg <==> treg < sreg */
3733 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3736 case M_SGT_I
: /* sreg > I <==> I < sreg */
3742 load_register (&icnt
, AT
, &imm_expr
);
3743 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3746 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3752 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3753 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3754 (int) BFD_RELOC_LO16
);
3757 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3763 load_register (&icnt
, AT
, &imm_expr
);
3764 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3765 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3766 (int) BFD_RELOC_LO16
);
3770 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3772 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3773 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3776 load_register (&icnt
, AT
, &imm_expr
);
3777 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3781 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3783 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3784 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3787 load_register (&icnt
, AT
, &imm_expr
);
3788 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3794 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3797 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3801 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3803 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3809 if (imm_expr
.X_add_number
== 0)
3811 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3817 as_warn ("Instruction %s: result is always true",
3819 macro_build ((char *) NULL
, &icnt
, &expr1
,
3820 mips_isa
< 3 ? "addiu" : "daddiu",
3821 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3824 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3826 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3827 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3830 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3832 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3833 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3834 mips_isa
< 3 ? "addiu" : "daddiu",
3835 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3840 load_register (&icnt
, AT
, &imm_expr
);
3841 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3845 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3853 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3855 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3856 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3857 dbl
? "daddi" : "addi",
3858 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3861 load_register (&icnt
, AT
, &imm_expr
);
3862 macro_build ((char *) NULL
, &icnt
, NULL
,
3863 dbl
? "dsub" : "sub",
3864 "d,v,t", dreg
, sreg
, AT
);
3870 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3872 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3873 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3874 dbl
? "daddiu" : "addiu",
3875 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3878 load_register (&icnt
, AT
, &imm_expr
);
3879 macro_build ((char *) NULL
, &icnt
, NULL
,
3880 dbl
? "dsubu" : "subu",
3881 "d,v,t", dreg
, sreg
, AT
);
3902 load_register (&icnt
, AT
, &imm_expr
);
3903 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3908 assert (mips_isa
< 2);
3909 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3910 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3913 * Is the double cfc1 instruction a bug in the mips assembler;
3914 * or is there a reason for it?
3916 mips_emit_delays ();
3918 mips_any_noreorder
= 1;
3919 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3920 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3921 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3922 expr1
.X_add_number
= 3;
3923 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3924 (int) BFD_RELOC_LO16
);
3925 expr1
.X_add_number
= 2;
3926 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3927 (int) BFD_RELOC_LO16
);
3928 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3929 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3930 macro_build ((char *) NULL
, &icnt
, NULL
,
3931 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3932 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3933 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3943 if (offset_expr
.X_add_number
>= 0x7fff)
3944 as_bad ("operand overflow");
3945 /* avoid load delay */
3946 if (byte_order
== LITTLE_ENDIAN
)
3947 offset_expr
.X_add_number
+= 1;
3948 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3949 (int) BFD_RELOC_LO16
, breg
);
3950 if (byte_order
== LITTLE_ENDIAN
)
3951 offset_expr
.X_add_number
-= 1;
3953 offset_expr
.X_add_number
+= 1;
3954 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3955 (int) BFD_RELOC_LO16
, breg
);
3956 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3957 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3961 if (offset_expr
.X_add_number
>= 0x7ffd)
3962 as_bad ("operand overflow");
3963 if (byte_order
== LITTLE_ENDIAN
)
3964 offset_expr
.X_add_number
+= 3;
3965 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3966 (int) BFD_RELOC_LO16
, breg
);
3967 if (byte_order
== LITTLE_ENDIAN
)
3968 offset_expr
.X_add_number
-= 3;
3970 offset_expr
.X_add_number
+= 3;
3971 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3972 (int) BFD_RELOC_LO16
, breg
);
3978 load_address (&icnt
, AT
, &offset_expr
);
3979 if (mask
== M_ULW_A
)
3981 if (byte_order
== LITTLE_ENDIAN
)
3982 expr1
.X_add_number
= 3;
3984 expr1
.X_add_number
= 0;
3985 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3986 (int) BFD_RELOC_LO16
, AT
);
3987 if (byte_order
== LITTLE_ENDIAN
)
3988 expr1
.X_add_number
= 0;
3990 expr1
.X_add_number
= 3;
3991 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3992 (int) BFD_RELOC_LO16
, AT
);
3996 if (byte_order
== BIG_ENDIAN
)
3997 expr1
.X_add_number
= 0;
3998 macro_build ((char *) NULL
, &icnt
, &expr1
,
3999 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4000 (int) BFD_RELOC_LO16
, AT
);
4001 if (byte_order
== BIG_ENDIAN
)
4002 expr1
.X_add_number
= 1;
4004 expr1
.X_add_number
= 0;
4005 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4006 (int) BFD_RELOC_LO16
, AT
);
4007 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4009 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4015 if (offset_expr
.X_add_number
>= 0x7fff)
4016 as_bad ("operand overflow");
4017 if (byte_order
== BIG_ENDIAN
)
4018 offset_expr
.X_add_number
+= 1;
4019 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4020 (int) BFD_RELOC_LO16
, breg
);
4021 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4022 if (byte_order
== BIG_ENDIAN
)
4023 offset_expr
.X_add_number
-= 1;
4025 offset_expr
.X_add_number
+= 1;
4026 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4027 (int) BFD_RELOC_LO16
, breg
);
4031 if (offset_expr
.X_add_number
>= 0x7ffd)
4032 as_bad ("operand overflow");
4033 if (byte_order
== LITTLE_ENDIAN
)
4034 offset_expr
.X_add_number
+= 3;
4035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
4036 (int) BFD_RELOC_LO16
, breg
);
4037 if (byte_order
== LITTLE_ENDIAN
)
4038 offset_expr
.X_add_number
-= 3;
4040 offset_expr
.X_add_number
+= 3;
4041 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
4042 (int) BFD_RELOC_LO16
, breg
);
4047 load_address (&icnt
, AT
, &offset_expr
);
4048 if (mask
== M_USW_A
)
4050 if (byte_order
== LITTLE_ENDIAN
)
4051 expr1
.X_add_number
= 3;
4053 expr1
.X_add_number
= 0;
4054 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
4055 (int) BFD_RELOC_LO16
, AT
);
4056 if (byte_order
== LITTLE_ENDIAN
)
4057 expr1
.X_add_number
= 0;
4059 expr1
.X_add_number
= 3;
4060 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
4061 (int) BFD_RELOC_LO16
, AT
);
4065 if (byte_order
== LITTLE_ENDIAN
)
4066 expr1
.X_add_number
= 0;
4067 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4068 (int) BFD_RELOC_LO16
, AT
);
4069 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4071 if (byte_order
== LITTLE_ENDIAN
)
4072 expr1
.X_add_number
= 1;
4074 expr1
.X_add_number
= 0;
4075 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4076 (int) BFD_RELOC_LO16
, AT
);
4077 if (byte_order
== LITTLE_ENDIAN
)
4078 expr1
.X_add_number
= 0;
4080 expr1
.X_add_number
= 1;
4081 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4082 (int) BFD_RELOC_LO16
, AT
);
4083 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4085 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4091 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
4095 as_warn ("Macro used $at after \".set noat\"");
4100 This routine assembles an instruction into its binary format. As a side
4101 effect it sets one of the global variables imm_reloc or offset_reloc to the
4102 type of relocation to do if one of the operands is an address expression.
4107 struct mips_cl_insn
*ip
;
4112 struct mips_opcode
*insn
;
4115 unsigned int lastregno
= 0;
4120 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
4132 as_warn ("Unknown opcode: `%s'", str
);
4135 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
4137 as_warn ("`%s' not in hash table.", str
);
4138 insn_error
= "ERROR: Unrecognized opcode";
4146 assert (strcmp (insn
->name
, str
) == 0);
4148 if (insn
->pinfo
== INSN_MACRO
)
4149 insn_isa
= insn
->match
;
4150 else if (insn
->pinfo
& INSN_ISA2
)
4152 else if (insn
->pinfo
& INSN_ISA3
)
4157 if (insn_isa
> mips_isa
)
4159 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4160 && strcmp (insn
->name
, insn
[1].name
) == 0)
4165 as_warn ("Instruction not supported on this processor");
4169 ip
->insn_opcode
= insn
->match
;
4170 for (args
= insn
->args
;; ++args
)
4176 case '\0': /* end of args */
4189 ip
->insn_opcode
|= lastregno
<< 21;
4194 ip
->insn_opcode
|= lastregno
<< 16;
4198 ip
->insn_opcode
|= lastregno
<< 11;
4204 /* handle optional base register.
4205 Either the base register is omitted or
4206 we must have a left paren. */
4207 /* this is dependent on the next operand specifier
4208 is a 'b' for base register */
4209 assert (args
[1] == 'b');
4213 case ')': /* these must match exactly */
4218 case '<': /* must be at least one digit */
4220 * According to the manual, if the shift amount is greater
4221 * than 31 or less than 0 the the shift amount should be
4222 * mod 32. In reality the mips assembler issues an error.
4223 * We issue a warning and mask out all but the low 5 bits.
4225 my_getExpression (&imm_expr
, s
);
4226 check_absolute_expr (ip
, &imm_expr
);
4227 if ((unsigned long) imm_expr
.X_add_number
> 31)
4229 as_warn ("Improper shift amount (%ld)",
4230 (long) imm_expr
.X_add_number
);
4231 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4233 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4234 imm_expr
.X_op
= O_absent
;
4238 case '>': /* shift amount minus 32 */
4239 my_getExpression (&imm_expr
, s
);
4240 check_absolute_expr (ip
, &imm_expr
);
4241 if ((unsigned long) imm_expr
.X_add_number
< 32
4242 || (unsigned long) imm_expr
.X_add_number
> 63)
4244 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4245 imm_expr
.X_op
= O_absent
;
4249 case 'k': /* cache code */
4250 my_getExpression (&imm_expr
, s
);
4251 check_absolute_expr (ip
, &imm_expr
);
4252 if ((unsigned long) imm_expr
.X_add_number
> 31)
4254 as_warn ("Invalid cahce opcode (%lu)",
4255 (unsigned long) imm_expr
.X_add_number
);
4256 imm_expr
.X_add_number
&= 0x1f;
4258 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4259 imm_expr
.X_op
= O_absent
;
4263 case 'c': /* break code */
4264 my_getExpression (&imm_expr
, s
);
4265 check_absolute_expr (ip
, &imm_expr
);
4266 if ((unsigned) imm_expr
.X_add_number
> 1023)
4267 as_warn ("Illegal break code (%ld)",
4268 (long) imm_expr
.X_add_number
);
4269 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4270 imm_expr
.X_op
= O_absent
;
4274 case 'B': /* syscall code */
4275 my_getExpression (&imm_expr
, s
);
4276 check_absolute_expr (ip
, &imm_expr
);
4277 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4278 as_warn ("Illegal syscall code (%ld)",
4279 (long) imm_expr
.X_add_number
);
4280 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4281 imm_expr
.X_op
= O_absent
;
4285 case 'C': /* Coprocessor code */
4286 my_getExpression (&imm_expr
, s
);
4287 check_absolute_expr (ip
, &imm_expr
);
4288 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4290 as_warn ("Coproccesor code > 25 bits (%ld)",
4291 (long) imm_expr
.X_add_number
);
4292 imm_expr
.X_add_number
&= ((1<<25) - 1);
4294 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4295 imm_expr
.X_op
= O_absent
;
4299 case 'b': /* base register */
4300 case 'd': /* destination register */
4301 case 's': /* source register */
4302 case 't': /* target register */
4303 case 'r': /* both target and source */
4304 case 'v': /* both dest and source */
4305 case 'w': /* both dest and target */
4306 case 'E': /* coprocessor target register */
4307 case 'G': /* coprocessor destination register */
4308 case 'x': /* ignore register name */
4309 case 'z': /* must be zero register */
4323 while (isdigit (*s
));
4325 as_bad ("Invalid register number (%d)", regno
);
4327 else if (*args
== 'E' || *args
== 'G')
4331 if (s
[1] == 'f' && s
[2] == 'p')
4336 else if (s
[1] == 's' && s
[2] == 'p')
4341 else if (s
[1] == 'g' && s
[2] == 'p')
4346 else if (s
[1] == 'a' && s
[2] == 't')
4354 if (regno
== AT
&& ! mips_noat
)
4355 as_warn ("Used $at without \".set noat\"");
4361 if (c
== 'r' || c
== 'v' || c
== 'w')
4368 /* 'z' only matches $0. */
4369 if (c
== 'z' && regno
!= 0)
4377 ip
->insn_opcode
|= regno
<< 21;
4381 ip
->insn_opcode
|= regno
<< 11;
4386 ip
->insn_opcode
|= regno
<< 16;
4389 /* This case exists because on the r3000 trunc
4390 expands into a macro which requires a gp
4391 register. On the r6000 or r4000 it is
4392 assembled into a single instruction which
4393 ignores the register. Thus the insn version
4394 is MIPS_ISA2 and uses 'x', and the macro
4395 version is MIPS_ISA1 and uses 't'. */
4398 /* This case is for the div instruction, which
4399 acts differently if the destination argument
4400 is $0. This only matches $0, and is checked
4401 outside the switch. */
4412 ip
->insn_opcode
|= lastregno
<< 21;
4415 ip
->insn_opcode
|= lastregno
<< 16;
4420 case 'D': /* floating point destination register */
4421 case 'S': /* floating point source register */
4422 case 'T': /* floating point target register */
4426 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4436 while (isdigit (*s
));
4439 as_bad ("Invalid float register number (%d)", regno
);
4441 if ((regno
& 1) != 0
4443 && ! (strcmp (str
, "mtc1") == 0 ||
4444 strcmp (str
, "mfc1") == 0 ||
4445 strcmp (str
, "lwc1") == 0 ||
4446 strcmp (str
, "swc1") == 0))
4447 as_warn ("Float register should be even, was %d",
4455 if (c
== 'V' || c
== 'W')
4465 ip
->insn_opcode
|= regno
<< 6;
4469 ip
->insn_opcode
|= regno
<< 11;
4473 ip
->insn_opcode
|= regno
<< 16;
4481 ip
->insn_opcode
|= lastregno
<< 11;
4484 ip
->insn_opcode
|= lastregno
<< 16;
4490 my_getExpression (&imm_expr
, s
);
4491 check_absolute_expr (ip
, &imm_expr
);
4496 my_getExpression (&offset_expr
, s
);
4497 imm_reloc
= BFD_RELOC_32
;
4509 unsigned char temp
[8];
4511 unsigned int length
;
4516 /* These only appear as the last operand in an
4517 instruction, and every instruction that accepts
4518 them in any variant accepts them in all variants.
4519 This means we don't have to worry about backing out
4520 any changes if the instruction does not match.
4522 The difference between them is the size of the
4523 floating point constant and where it goes. For 'F'
4524 and 'L' the constant is 64 bits; for 'f' and 'l' it
4525 is 32 bits. Where the constant is placed is based
4526 on how the MIPS assembler does things:
4529 f -- immediate value
4532 The .lit4 and .lit8 sections are only used if
4533 permitted by the -G argument.
4535 When generating embedded PIC code, we use the
4536 .lit8 section but not the .lit4 section (we can do
4537 .lit4 inline easily; we need to put .lit8
4538 somewhere in the data segment, and using .lit8
4539 permits the linker to eventually combine identical
4542 f64
= *args
== 'F' || *args
== 'L';
4544 save_in
= input_line_pointer
;
4545 input_line_pointer
= s
;
4546 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4548 s
= input_line_pointer
;
4549 input_line_pointer
= save_in
;
4550 if (err
!= NULL
&& *err
!= '\0')
4552 as_bad ("Bad floating point constant: %s", err
);
4553 memset (temp
, '\0', sizeof temp
);
4554 length
= f64
? 8 : 4;
4557 assert (length
== (f64
? 8 : 4));
4561 && (mips_pic
== EMBEDDED_PIC
4563 || g_switch_value
< 4
4567 imm_expr
.X_op
= O_constant
;
4568 if (byte_order
== LITTLE_ENDIAN
)
4569 imm_expr
.X_add_number
=
4570 (((((((int) temp
[3] << 8)
4575 imm_expr
.X_add_number
=
4576 (((((((int) temp
[0] << 8)
4583 const char *newname
;
4586 /* Switch to the right section. */
4588 subseg
= now_subseg
;
4591 default: /* unused default case avoids warnings. */
4595 if (g_switch_value
< 8)
4596 newname
= RDATA_SECTION_NAME
;
4600 newname
= RDATA_SECTION_NAME
;
4604 assert (g_switch_value
>= 4);
4609 new_seg
= subseg_new (newname
, (subsegT
) 0);
4610 frag_align (*args
== 'l' ? 2 : 3, 0);
4612 record_alignment (new_seg
, 4);
4614 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
4617 as_bad ("Can't use floating point insn in this section");
4619 /* Set the argument to the current address in the
4621 offset_expr
.X_op
= O_symbol
;
4622 offset_expr
.X_add_symbol
=
4623 symbol_new ("L0\001", now_seg
,
4624 (valueT
) frag_now_fix (), frag_now
);
4625 offset_expr
.X_add_number
= 0;
4627 /* Put the floating point number into the section. */
4628 p
= frag_more ((int) length
);
4629 memcpy (p
, temp
, length
);
4631 /* Switch back to the original section. */
4632 subseg_set (seg
, subseg
);
4637 case 'i': /* 16 bit unsigned immediate */
4638 case 'j': /* 16 bit signed immediate */
4639 imm_reloc
= BFD_RELOC_LO16
;
4640 c
= my_getSmallExpression (&imm_expr
, s
);
4645 if (imm_expr
.X_op
== O_constant
)
4646 imm_expr
.X_add_number
=
4647 (imm_expr
.X_add_number
>> 16) & 0xffff;
4649 imm_reloc
= BFD_RELOC_HI16_S
;
4651 imm_reloc
= BFD_RELOC_HI16
;
4655 check_absolute_expr (ip
, &imm_expr
);
4658 if (imm_expr
.X_add_number
< 0
4659 || imm_expr
.X_add_number
>= 0x10000)
4661 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4662 !strcmp (insn
->name
, insn
[1].name
))
4664 as_bad ("16 bit expression not in range 0..65535");
4672 /* The upper bound should be 0x8000, but
4673 unfortunately the MIPS assembler accepts numbers
4674 from 0x8000 to 0xffff and sign extends them, and
4675 we want to be compatible. We only permit this
4676 extended range for an instruction which does not
4677 provide any further alternates, since those
4678 alternates may handle other cases. People should
4679 use the numbers they mean, rather than relying on
4680 a mysterious sign extension. */
4681 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4682 strcmp (insn
->name
, insn
[1].name
) == 0);
4687 if (imm_expr
.X_add_number
< -0x8000 ||
4688 imm_expr
.X_add_number
>= max
)
4692 as_bad ("16 bit expression not in range -32768..32767");
4698 case 'o': /* 16 bit offset */
4699 c
= my_getSmallExpression (&offset_expr
, s
);
4701 /* If this value won't fit into a 16 bit offset, then go
4702 find a macro that will generate the 32 bit offset
4703 code pattern. As a special hack, we accept the
4704 difference of two local symbols as a constant. This
4705 is required to suppose embedded PIC switches, which
4706 use an instruction which looks like
4707 lw $4,$L12-$LS12($4)
4708 The problem with handling this in a more general
4709 fashion is that the macro function doesn't expect to
4710 see anything which can be handled in a single
4711 constant instruction. */
4713 && (offset_expr
.X_op
!= O_constant
4714 || offset_expr
.X_add_number
>= 0x8000
4715 || offset_expr
.X_add_number
< -0x8000)
4716 && (mips_pic
!= EMBEDDED_PIC
4717 || offset_expr
.X_op
!= O_subtract
4718 || ! S_IS_LOCAL (offset_expr
.X_add_symbol
)
4719 || ! S_IS_LOCAL (offset_expr
.X_op_symbol
)))
4722 offset_reloc
= BFD_RELOC_LO16
;
4723 if (c
== 'h' || c
== 'H')
4725 assert (offset_expr
.X_op
== O_constant
);
4726 offset_expr
.X_add_number
=
4727 (offset_expr
.X_add_number
>> 16) & 0xffff;
4732 case 'p': /* pc relative offset */
4733 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4734 my_getExpression (&offset_expr
, s
);
4738 case 'u': /* upper 16 bits */
4739 c
= my_getSmallExpression (&imm_expr
, s
);
4740 if (imm_expr
.X_op
== O_constant
4741 && (imm_expr
.X_add_number
< 0
4742 || imm_expr
.X_add_number
>= 0x10000))
4743 as_bad ("lui expression not in range 0..65535");
4744 imm_reloc
= BFD_RELOC_LO16
;
4749 if (imm_expr
.X_op
== O_constant
)
4750 imm_expr
.X_add_number
=
4751 (imm_expr
.X_add_number
>> 16) & 0xffff;
4753 imm_reloc
= BFD_RELOC_HI16_S
;
4755 imm_reloc
= BFD_RELOC_HI16
;
4761 case 'a': /* 26 bit address */
4762 my_getExpression (&offset_expr
, s
);
4764 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4768 fprintf (stderr
, "bad char = '%c'\n", *args
);
4773 /* Args don't match. */
4774 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4775 !strcmp (insn
->name
, insn
[1].name
))
4781 insn_error
= "ERROR: Illegal operands";
4790 my_getSmallExpression (ep
, str
)
4801 ((str
[1] == 'h' && str
[2] == 'i')
4802 || (str
[1] == 'H' && str
[2] == 'I')
4803 || (str
[1] == 'l' && str
[2] == 'o'))
4815 * A small expression may be followed by a base register.
4816 * Scan to the end of this operand, and then back over a possible
4817 * base register. Then scan the small expression up to that
4818 * point. (Based on code in sparc.c...)
4820 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4822 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4824 if (isdigit (sp
[-2]))
4826 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4828 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4834 else if (sp
- 5 >= str
4837 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4838 || (sp
[-3] == 's' && sp
[-2] == 'p')
4839 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4840 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4846 /* no expression means zero offset */
4849 /* %xx(reg) is an error */
4850 ep
->X_op
= O_absent
;
4855 ep
->X_op
= O_constant
;
4858 ep
->X_add_symbol
= NULL
;
4859 ep
->X_op_symbol
= NULL
;
4860 ep
->X_add_number
= 0;
4865 my_getExpression (ep
, str
);
4872 my_getExpression (ep
, str
);
4873 return c
; /* => %hi or %lo encountered */
4877 my_getExpression (ep
, str
)
4883 save_in
= input_line_pointer
;
4884 input_line_pointer
= str
;
4886 expr_end
= input_line_pointer
;
4887 input_line_pointer
= save_in
;
4890 /* Turn a string in input_line_pointer into a floating point constant
4891 of type type, and store the appropriate bytes in *litP. The number
4892 of LITTLENUMS emitted is stored in *sizeP . An error message is
4893 returned, or NULL on OK. */
4896 md_atof (type
, litP
, sizeP
)
4902 LITTLENUM_TYPE words
[4];
4918 return "bad call to md_atof";
4921 t
= atof_ieee (input_line_pointer
, type
, words
);
4923 input_line_pointer
= t
;
4927 if (byte_order
== LITTLE_ENDIAN
)
4929 for (i
= prec
- 1; i
>= 0; i
--)
4931 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4937 for (i
= 0; i
< prec
; i
++)
4939 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4948 md_number_to_chars (buf
, val
, n
)
4956 number_to_chars_littleendian (buf
, val
, n
);
4960 number_to_chars_bigendian (buf
, val
, n
);
4969 CONST
char *md_shortopts
= "E:O::g::G:";
4971 CONST
char *md_shortopts
= "E:O::g::";
4973 struct option md_longopts
[] = {
4974 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
4975 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
4976 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
4977 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
4978 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
4979 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
4980 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
4981 #define OPTION_MCPU (OPTION_MD_BASE + 4)
4982 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
4983 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 5)
4984 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
4985 #define OPTION_TRAP (OPTION_MD_BASE + 8)
4986 {"trap", no_argument
, NULL
, OPTION_TRAP
},
4987 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
4988 #define OPTION_BREAK (OPTION_MD_BASE + 9)
4989 {"break", no_argument
, NULL
, OPTION_BREAK
},
4990 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
4993 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 6)
4994 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
4995 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
4996 #define OPTION_NON_SHARED (OPTION_MD_BASE + 7)
4997 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
5000 {NULL
, no_argument
, NULL
, 0}
5002 size_t md_longopts_size
= sizeof(md_longopts
);
5005 md_parse_option (c
, arg
)
5021 byte_order
= BIG_ENDIAN
;
5022 else if (arg
[1] == 'L')
5023 byte_order
= LITTLE_ENDIAN
;
5026 as_bad("invalid endianness -E%c", arg
[1]);
5032 mips_target_format
= "a.out-mips-big";
5034 mips_target_format
= "a.out-mips-little";
5038 mips_target_format
= "ecoff-bigmips";
5040 mips_target_format
= "ecoff-littlemips";
5044 mips_target_format
= "elf32-bigmips";
5046 mips_target_format
= "elf32-littlemips";
5049 /* FIXME: This breaks -L -EL. */
5050 flag_keep_locals
= 0;
5054 if (arg
&& arg
[1] == '0')
5061 if (arg
== NULL
|| arg
[1] == '2')
5084 /* Identify the processor type */
5086 if (strcmp (p
, "default") == 0
5087 || strcmp (p
, "DEFAULT") == 0)
5091 if (*p
== 'r' || *p
== 'R')
5098 if (strcmp (p
, "2000") == 0
5099 || strcmp (p
, "2k") == 0
5100 || strcmp (p
, "2K") == 0)
5108 if (strcmp (p
, "3000") == 0
5109 || strcmp (p
, "3k") == 0
5110 || strcmp (p
, "3K") == 0)
5118 if (strcmp (p
, "4000") == 0
5119 || strcmp (p
, "4k") == 0
5120 || strcmp (p
, "4K") == 0)
5125 else if (strcmp (p
, "4400") == 0)
5130 else if (strcmp (p
, "4600") == 0)
5138 if (strcmp (p
, "6000") == 0
5139 || strcmp (p
, "6k") == 0
5140 || strcmp (p
, "6K") == 0)
5148 if (strcmp (p
, "orion") == 0)
5158 as_bad ("invalid architecture -mcpu=%s", arg
);
5165 case OPTION_MEMBEDDED_PIC
:
5166 mips_pic
= EMBEDDED_PIC
;
5170 as_bad ("-G may not be used with embedded PIC code");
5173 g_switch_value
= 0x7fffffff;
5178 /* When generating ELF code, we permit -KPIC and -call_shared to
5179 select SVR4_PIC, and -non_shared to select no PIC. This is
5180 intended to be compatible with Irix 5. */
5181 case OPTION_CALL_SHARED
:
5182 mips_pic
= SVR4_PIC
;
5183 if (g_switch_seen
&& g_switch_value
!= 0)
5185 as_bad ("-G may not be used with SVR4 PIC code");
5191 case OPTION_NON_SHARED
:
5194 #endif /* OBJ_ELF */
5198 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
5200 as_bad ("-G may not be used with SVR4 or embedded PIC code");
5204 g_switch_value
= atoi (arg
);
5217 md_show_usage (stream
)
5222 -membedded-pic generate embedded position independent code\n\
5223 -EB generate big endian output\n\
5224 -EL generate little endian output\n\
5225 -g, -g2 do not remove uneeded NOPs or swap branches\n\
5226 -G NUM allow referencing objects up to NUM bytes\n\
5227 implicitly with the gp register [default 8]\n");
5229 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
5230 -mips2, -mcpu=r6000 generate code for r6000\n\
5231 -mips3, -mcpu=r4000 generate code for r4000\n\
5232 -O0 remove unneeded NOPs, do not swap branches\n\
5233 -O remove unneeded NOPs and swap branches\n\
5234 --trap, --no-break trap exception on div by 0 and mult overflow\n\
5235 --break, --no-trap break exception on div by 0 and mult overflow\n");
5238 -KPIC, -call_shared generate SVR4 position independent code\n\
5239 -non_shared do not generate position independent code\n");
5244 md_pcrel_from (fixP
)
5248 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5249 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5251 /* This makes a branch to an undefined symbol be a branch to the
5252 current location. */
5257 /* return the address of the delay slot */
5258 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5261 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5262 reloc for a cons. We could use the definition there, except that
5263 we want to handle 64 bit relocs specially. */
5266 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5269 unsigned int nbytes
;
5272 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5274 FIXME: There is no way to select anything but 32 bit mode right
5278 if (byte_order
== BIG_ENDIAN
)
5283 if (nbytes
!= 2 && nbytes
!= 4)
5284 as_bad ("Unsupported reloc size %d", nbytes
);
5286 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5287 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5290 /* When generating embedded PIC code we need to use a special
5291 relocation to represent the difference of two symbols in the .text
5292 section (switch tables use a difference of this sort). See
5293 include/coff/mips.h for details. This macro checks whether this
5294 fixup requires the special reloc. */
5295 #define SWITCH_TABLE(fixp) \
5296 ((fixp)->fx_r_type == BFD_RELOC_32 \
5297 && (fixp)->fx_addsy != NULL \
5298 && (fixp)->fx_subsy != NULL \
5299 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5300 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5302 /* When generating embedded PIC code we must keep all PC relative
5303 relocations, in case the linker has to relax a call. We also need
5304 to keep relocations for switch table entries. */
5308 mips_force_relocation (fixp
)
5311 return (mips_pic
== EMBEDDED_PIC
5313 || SWITCH_TABLE (fixp
)
5314 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
5315 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
5318 /* Apply a fixup to the object file. */
5321 md_apply_fix (fixP
, valueP
)
5328 assert (fixP
->fx_size
== 4);
5331 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5333 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5336 switch (fixP
->fx_r_type
)
5338 case BFD_RELOC_MIPS_JMP
:
5339 case BFD_RELOC_HI16
:
5340 case BFD_RELOC_HI16_S
:
5341 case BFD_RELOC_MIPS_GPREL
:
5342 case BFD_RELOC_MIPS_LITERAL
:
5343 case BFD_RELOC_MIPS_CALL16
:
5344 case BFD_RELOC_MIPS_GOT16
:
5345 case BFD_RELOC_MIPS_GPREL32
:
5347 as_bad ("Invalid PC relative reloc");
5348 /* Nothing needed to do. The value comes from the reloc entry */
5351 case BFD_RELOC_PCREL_HI16_S
:
5352 /* The addend for this is tricky if it is internal, so we just
5353 do everything here rather than in bfd_perform_relocation. */
5354 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5356 /* For an external symbol adjust by the address to make it
5357 pcrel_offset. We use the address of the RELLO reloc
5358 which follows this one. */
5359 value
+= (fixP
->fx_next
->fx_frag
->fr_address
5360 + fixP
->fx_next
->fx_where
);
5365 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5366 if (byte_order
== BIG_ENDIAN
)
5368 md_number_to_chars (buf
, value
, 2);
5371 case BFD_RELOC_PCREL_LO16
:
5372 /* The addend for this is tricky if it is internal, so we just
5373 do everything here rather than in bfd_perform_relocation. */
5374 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
5375 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
5376 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5377 if (byte_order
== BIG_ENDIAN
)
5379 md_number_to_chars (buf
, value
, 2);
5383 /* If we are deleting this reloc entry, we must fill in the
5384 value now. This can happen if we have a .word which is not
5385 resolved when it appears but is later defined. We also need
5386 to fill in the value if this is an embedded PIC switch table
5389 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5390 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5394 case BFD_RELOC_LO16
:
5395 /* When handling an embedded PIC switch statement, we can wind
5396 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5399 if (value
< -0x8000 || value
> 0x7fff)
5400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5401 "relocation overflow");
5402 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5403 if (byte_order
== BIG_ENDIAN
)
5405 md_number_to_chars (buf
, value
, 2);
5409 case BFD_RELOC_16_PCREL_S2
:
5411 * We need to save the bits in the instruction since fixup_segment()
5412 * might be deleting the relocation entry (i.e., a branch within
5413 * the current segment).
5416 as_warn ("Branch to odd address (%lx)", value
);
5418 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
5419 as_bad ("Relocation overflow");
5421 /* update old instruction data */
5422 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5426 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5430 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5437 insn
|= value
& 0xFFFF;
5438 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5453 const struct mips_opcode
*p
;
5454 int treg
, sreg
, dreg
, shamt
;
5459 for (i
= 0; i
< NUMOPCODES
; ++i
)
5461 p
= &mips_opcodes
[i
];
5462 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5464 printf ("%08lx %s\t", oc
, p
->name
);
5465 treg
= (oc
>> 16) & 0x1f;
5466 sreg
= (oc
>> 21) & 0x1f;
5467 dreg
= (oc
>> 11) & 0x1f;
5468 shamt
= (oc
>> 6) & 0x1f;
5470 for (args
= p
->args
;; ++args
)
5481 printf ("%c", *args
);
5485 assert (treg
== sreg
);
5486 printf ("$%d,$%d", treg
, sreg
);
5491 printf ("$%d", dreg
);
5496 printf ("$%d", treg
);
5500 printf ("0x%x", treg
);
5505 printf ("$%d", sreg
);
5509 printf ("0x%08lx", oc
& 0x1ffffff);
5521 printf ("$%d", shamt
);
5532 printf ("%08lx UNDEFINED\n", oc
);
5543 name
= input_line_pointer
;
5544 c
= get_symbol_end ();
5545 p
= (symbolS
*) symbol_find_or_make (name
);
5546 *input_line_pointer
= c
;
5550 /* Align the current frag to a given power of two. The MIPS assembler
5551 also automatically adjusts any preceding label. */
5554 mips_align (to
, fill
, label
)
5559 mips_emit_delays ();
5560 frag_align (to
, fill
);
5561 record_alignment (now_seg
, to
);
5564 assert (S_GET_SEGMENT (label
) == now_seg
);
5565 label
->sy_frag
= frag_now
;
5566 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5570 /* Align to a given power of two. .align 0 turns off the automatic
5571 alignment used by the data creating pseudo-ops. */
5578 register long temp_fill
;
5579 long max_alignment
= 15;
5583 o Note that the assembler pulls down any immediately preceeding label
5584 to the aligned address.
5585 o It's not documented but auto alignment is reinstated by
5586 a .align pseudo instruction.
5587 o Note also that after auto alignment is turned off the mips assembler
5588 issues an error on attempt to assemble an improperly aligned data item.
5593 temp
= get_absolute_expression ();
5594 if (temp
> max_alignment
)
5595 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5598 as_warn ("Alignment negative: 0 assumed.");
5601 if (*input_line_pointer
== ',')
5603 input_line_pointer
++;
5604 temp_fill
= get_absolute_expression ();
5611 mips_align (temp
, (int) temp_fill
, insn_label
);
5618 demand_empty_rest_of_line ();
5621 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5622 that there was a previous instruction. */
5625 s_stringer (append_zero
)
5628 mips_emit_delays ();
5630 stringer (append_zero
);
5641 /* When generating embedded PIC code, we only use the .text, .lit8,
5642 .sdata and .sbss sections. We change the .data and .rdata
5643 pseudo-ops to use .sdata. */
5644 if (mips_pic
== EMBEDDED_PIC
5645 && (sec
== 'd' || sec
== 'r'))
5648 mips_emit_delays ();
5658 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5659 demand_empty_rest_of_line ();
5663 seg
= subseg_new (RDATA_SECTION_NAME
,
5664 (subsegT
) get_absolute_expression ());
5666 bfd_set_section_flags (stdoutput
, seg
,
5672 bfd_set_section_alignment (stdoutput
, seg
, 4);
5674 demand_empty_rest_of_line ();
5679 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5681 bfd_set_section_flags (stdoutput
, seg
,
5682 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5683 bfd_set_section_alignment (stdoutput
, seg
, 4);
5685 demand_empty_rest_of_line ();
5687 #else /* ! defined (GPOPT) */
5688 as_bad ("Global pointers not supported; recompile -G 0");
5689 demand_empty_rest_of_line ();
5691 #endif /* ! defined (GPOPT) */
5704 mips_emit_delays ();
5705 if (log_size
> 0 && auto_align
)
5706 mips_align (log_size
, 0, label
);
5708 cons (1 << log_size
);
5715 as_fatal ("Encountered `.err', aborting assembly");
5725 symbolP
= get_symbol ();
5726 if (*input_line_pointer
== ',')
5727 input_line_pointer
++;
5728 size
= get_absolute_expression ();
5729 S_SET_EXTERNAL (symbolP
);
5731 #ifdef ECOFF_DEBUGGING
5732 symbolP
->ecoff_extern_size
= size
;
5744 mips_emit_delays ();
5748 mips_align (3, 0, label
);
5750 mips_align (2, 0, label
);
5764 opt
= input_line_pointer
;
5765 c
= get_symbol_end ();
5769 /* FIXME: What does this mean? */
5771 else if (strncmp (opt
, "pic", 3) == 0)
5779 mips_pic
= SVR4_PIC
;
5781 as_bad (".option pic%d not supported", i
);
5784 if (mips_pic
== SVR4_PIC
)
5786 if (g_switch_seen
&& g_switch_value
!= 0)
5787 as_warn ("-G may not be used with SVR4 PIC code");
5789 bfd_set_gp_size (stdoutput
, 0);
5794 as_warn ("Unrecognized option \"%s\"", opt
);
5796 *input_line_pointer
= c
;
5797 demand_empty_rest_of_line ();
5804 char *name
= input_line_pointer
, ch
;
5806 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5807 input_line_pointer
++;
5808 ch
= *input_line_pointer
;
5809 *input_line_pointer
= '\0';
5811 if (strcmp (name
, "reorder") == 0)
5815 prev_insn_unreordered
= 1;
5816 prev_prev_insn_unreordered
= 1;
5820 else if (strcmp (name
, "noreorder") == 0)
5822 mips_emit_delays ();
5824 mips_any_noreorder
= 1;
5826 else if (strcmp (name
, "at") == 0)
5830 else if (strcmp (name
, "noat") == 0)
5834 else if (strcmp (name
, "macro") == 0)
5836 mips_warn_about_macros
= 0;
5838 else if (strcmp (name
, "nomacro") == 0)
5840 if (mips_noreorder
== 0)
5841 as_bad ("`noreorder' must be set before `nomacro'");
5842 mips_warn_about_macros
= 1;
5844 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5848 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5852 else if (strcmp (name
, "bopt") == 0)
5856 else if (strcmp (name
, "nobopt") == 0)
5860 else if (strncmp (name
, "mips", 4) == 0)
5864 /* Permit the user to change the ISA on the fly. Needless to
5865 say, misuse can cause serious problems. */
5866 isa
= atoi (name
+ 4);
5868 mips_isa
= file_mips_isa
;
5869 else if (isa
< 1 || isa
> 3)
5870 as_bad ("unknown ISA level");
5876 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5878 *input_line_pointer
= ch
;
5879 demand_empty_rest_of_line ();
5882 /* The same as the usual .space directive, except that we have to
5883 forget about any previous instruction. */
5886 s_mips_space (param
)
5889 mips_emit_delays ();
5894 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5895 .option pic2. It means to generate SVR4 PIC calls. */
5901 mips_pic
= SVR4_PIC
;
5903 if (g_switch_seen
&& g_switch_value
!= 0)
5904 as_warn ("-G may not be used with SVR4 PIC code");
5907 bfd_set_gp_size (stdoutput
, 0);
5908 demand_empty_rest_of_line ();
5911 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5912 PIC code. It sets the $gp register for the function based on the
5913 function address, which is in the register named in the argument.
5914 This uses a relocation against _gp_disp, which is handled specially
5915 by the linker. The result is:
5916 lui $gp,%hi(_gp_disp)
5917 addiu $gp,$gp,%lo(_gp_disp)
5918 addu $gp,$gp,.cpload argument
5919 The .cpload argument is normally $25 == $t9. */
5928 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
5929 if (mips_pic
!= SVR4_PIC
)
5935 /* .cpload should be a in .set noreorder section. */
5936 if (mips_noreorder
== 0)
5937 as_warn (".cpload not in noreorder section");
5940 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5941 ex
.X_op_symbol
= NULL
;
5942 ex
.X_add_number
= 0;
5944 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5945 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5946 (int) BFD_RELOC_LO16
);
5948 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5949 GP
, GP
, tc_get_register (0));
5951 demand_empty_rest_of_line ();
5954 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5955 offset from $sp. The offset is remembered, and after making a PIC
5956 call $gp is restored from that location. */
5959 s_cprestore (ignore
)
5965 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
5966 if (mips_pic
!= SVR4_PIC
)
5972 mips_cprestore_offset
= get_absolute_expression ();
5974 ex
.X_op
= O_constant
;
5975 ex
.X_add_symbol
= NULL
;
5976 ex
.X_op_symbol
= NULL
;
5977 ex
.X_add_number
= mips_cprestore_offset
;
5979 macro_build ((char *) NULL
, &icnt
, &ex
,
5980 mips_isa
< 3 ? "sw" : "sd",
5981 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5983 demand_empty_rest_of_line ();
5986 /* Handle the .gpword pseudo-op. This is used when generating PIC
5987 code. It generates a 32 bit GP relative reloc. */
5997 /* When not generating PIC code, this is treated as .word. */
5998 if (mips_pic
!= SVR4_PIC
)
6005 mips_emit_delays ();
6007 mips_align (2, 0, label
);
6012 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
6014 as_bad ("Unsupported use of .gpword");
6015 ignore_rest_of_line ();
6019 md_number_to_chars (p
, (valueT
) 0, 4);
6020 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
6021 BFD_RELOC_MIPS_GPREL32
);
6023 demand_empty_rest_of_line ();
6026 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
6027 tables in SVR4 PIC code. */
6036 /* This is ignored when not generating SVR4 PIC code. */
6037 if (mips_pic
!= SVR4_PIC
)
6043 /* Add $gp to the register named as an argument. */
6044 reg
= tc_get_register (0);
6045 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6046 mips_isa
< 3 ? "addu" : "daddu",
6047 "d,v,t", reg
, reg
, GP
);
6049 demand_empty_rest_of_line ();
6052 /* Parse a register string into a number. Called from the ECOFF code
6053 to parse .frame. The argument is non-zero if this is the frame
6054 register, so that we can record it in mips_frame_reg. */
6057 tc_get_register (frame
)
6063 if (*input_line_pointer
++ != '$')
6065 as_warn ("expected `$'");
6068 else if (isdigit ((unsigned char) *input_line_pointer
))
6070 reg
= get_absolute_expression ();
6071 if (reg
< 0 || reg
>= 32)
6073 as_warn ("Bad register number");
6079 if (strncmp (input_line_pointer
, "fp", 2) == 0)
6081 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
6083 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
6085 else if (strncmp (input_line_pointer
, "at", 2) == 0)
6089 as_warn ("Unrecognized register name");
6092 input_line_pointer
+= 2;
6095 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
6100 md_section_align (seg
, addr
)
6104 int align
= bfd_get_section_alignment (stdoutput
, seg
);
6106 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
6109 /* Estimate the size of a frag before relaxing. We are not really
6110 relaxing here, and the final size is encoded in the subtype
6115 md_estimate_size_before_relax (fragp
, segtype
)
6121 if (mips_pic
== NO_PIC
)
6124 const char *symname
;
6126 /* Find out whether this symbol can be referenced off the GP
6127 register. It can be if it is smaller than the -G size or if
6128 it is in the .sdata or .sbss section. Certain symbols can
6129 not be referenced off the GP, although it appears as though
6131 symname
= S_GET_NAME (fragp
->fr_symbol
);
6132 if (symname
!= (const char *) NULL
6133 && (strcmp (symname
, "eprol") == 0
6134 || strcmp (symname
, "etext") == 0
6135 || strcmp (symname
, "_gp") == 0
6136 || strcmp (symname
, "edata") == 0
6137 || strcmp (symname
, "_fbss") == 0
6138 || strcmp (symname
, "_fdata") == 0
6139 || strcmp (symname
, "_ftext") == 0
6140 || strcmp (symname
, "end") == 0
6141 || strcmp (symname
, "_gp_disp") == 0))
6143 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
6144 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
6145 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
6146 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
6147 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
6151 const char *segname
;
6153 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
6154 assert (strcmp (segname
, ".lit8") != 0
6155 && strcmp (segname
, ".lit4") != 0);
6156 change
= (strcmp (segname
, ".sdata") != 0
6157 && strcmp (segname
, ".sbss") != 0);
6159 #else /* ! defined (GPOPT) */
6160 /* We are not optimizing for the GP register. */
6162 #endif /* ! defined (GPOPT) */
6164 else if (mips_pic
== SVR4_PIC
)
6166 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
6168 /* This must duplicate the test in adjust_reloc_syms. */
6169 change
= (symsec
!= &bfd_und_section
6170 && symsec
!= &bfd_abs_section
6171 && ! bfd_is_com_section (symsec
));
6178 /* Record the offset to the first reloc in the fr_opcode field.
6179 This lets md_convert_frag and tc_gen_reloc know that the code
6180 must be expanded. */
6181 fragp
->fr_opcode
= (fragp
->fr_literal
6183 - RELAX_OLD (fragp
->fr_subtype
)
6184 + RELAX_RELOC1 (fragp
->fr_subtype
));
6185 /* FIXME: This really needs as_warn_where. */
6186 if (RELAX_WARN (fragp
->fr_subtype
))
6187 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
6193 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
6196 /* Translate internal representation of relocation info to BFD target
6200 tc_gen_reloc (section
, fixp
)
6204 static arelent
*retval
[4];
6207 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
6210 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6211 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6213 if (mips_pic
== EMBEDDED_PIC
6214 && SWITCH_TABLE (fixp
))
6216 /* For a switch table entry we use a special reloc. The addend
6217 is actually the difference between the reloc address and the
6219 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6221 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
6223 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
6225 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
6227 /* We use a special addend for an internal RELLO reloc. */
6228 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6229 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
6231 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
6233 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
6235 assert (fixp
->fx_next
!= NULL
6236 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
6237 /* We use a special addend for an internal RELHI reloc. The
6238 reloc is relative to the RELLO; adjust the addend
6240 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
6241 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
6242 + fixp
->fx_next
->fx_where
6243 - S_GET_VALUE (fixp
->fx_subsy
));
6245 reloc
->addend
= (fixp
->fx_addnumber
6246 + fixp
->fx_next
->fx_frag
->fr_address
6247 + fixp
->fx_next
->fx_where
);
6249 else if (fixp
->fx_pcrel
== 0)
6250 reloc
->addend
= fixp
->fx_addnumber
;
6254 /* A gruesome hack which is a result of the gruesome gas reloc
6256 reloc
->addend
= reloc
->address
;
6258 reloc
->addend
= -reloc
->address
;
6262 /* If this is a variant frag, we may need to adjust the existing
6263 reloc and generate a new one. */
6264 if (fixp
->fx_frag
->fr_opcode
!= NULL
6265 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6266 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
6267 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
6271 /* If this is not the last reloc in this frag, then we have two
6272 GPREL relocs, both of which are being replaced. Let the
6273 second one handle all of them. */
6274 if (fixp
->fx_next
!= NULL
6275 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
6277 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
6278 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6283 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6284 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6285 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6287 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6288 reloc2
->address
= (reloc
->address
6289 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6290 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6291 reloc2
->addend
= fixp
->fx_addnumber
;
6292 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6293 assert (reloc2
->howto
!= NULL
);
6295 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6299 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6302 reloc3
->address
+= 4;
6305 if (mips_pic
== NO_PIC
)
6307 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6308 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6310 else if (mips_pic
== SVR4_PIC
)
6312 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6314 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6315 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6322 /* To support a PC relative reloc when generating embedded PIC code
6323 for ECOFF, we use a Cygnus extension. We check for that here to
6324 make sure that we don't let such a reloc escape normally. */
6326 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6327 && mips_pic
!= EMBEDDED_PIC
)
6328 reloc
->howto
= NULL
;
6331 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6333 if (reloc
->howto
== NULL
)
6335 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6336 "Can not represent relocation in this object file format");
6343 /* Convert a machine dependent frag. */
6346 md_convert_frag (abfd
, asec
, fragp
)
6354 if (fragp
->fr_opcode
== NULL
)
6357 old
= RELAX_OLD (fragp
->fr_subtype
);
6358 new = RELAX_NEW (fragp
->fr_subtype
);
6359 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6362 memcpy (fixptr
- old
, fixptr
, new);
6364 fragp
->fr_fix
+= new - old
;
6367 /* This function is called whenever a label is defined. It is used
6368 when handling branch delays; if a branch has a label, we assume we
6372 mips_define_label (sym
)
6380 /* Some special processing for a MIPS ELF file. */
6383 mips_elf_final_processing ()
6387 /* Write out the .reginfo section. */
6388 s
.ri_gprmask
= mips_gprmask
;
6389 s
.ri_cprmask
[0] = mips_cprmask
[0];
6390 s
.ri_cprmask
[1] = mips_cprmask
[1];
6391 s
.ri_cprmask
[2] = mips_cprmask
[2];
6392 s
.ri_cprmask
[3] = mips_cprmask
[3];
6393 /* The gp_value field is set by the MIPS ELF backend. */
6395 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6396 ((Elf32_External_RegInfo
*)
6397 mips_regmask_frag
));
6399 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6400 sort of BFD interface for this. */
6401 if (mips_any_noreorder
)
6402 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6403 if (mips_pic
!= NO_PIC
)
6404 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6407 #endif /* OBJ_ELF */
6409 #ifndef ECOFF_DEBUGGING
6411 /* These functions should really be defined by the object file format,
6412 since they are related to debugging information. However, this
6413 code has to work for the a.out format, which does not define them,
6414 so we provide simple versions here. These don't actually generate
6415 any debugging information, but they do simple checking and someday
6416 somebody may make them useful. */
6420 struct loc
*loc_next
;
6421 unsigned long loc_fileno
;
6422 unsigned long loc_lineno
;
6423 unsigned long loc_offset
;
6424 unsigned short loc_delta
;
6425 unsigned short loc_count
;
6434 struct proc
*proc_next
;
6435 struct symbol
*proc_isym
;
6436 struct symbol
*proc_end
;
6437 unsigned long proc_reg_mask
;
6438 unsigned long proc_reg_offset
;
6439 unsigned long proc_fpreg_mask
;
6440 unsigned long proc_fpreg_offset
;
6441 unsigned long proc_frameoffset
;
6442 unsigned long proc_framereg
;
6443 unsigned long proc_pcreg
;
6445 struct file
*proc_file
;
6452 struct file
*file_next
;
6453 unsigned long file_fileno
;
6454 struct symbol
*file_symbol
;
6455 struct symbol
*file_end
;
6456 struct proc
*file_proc
;
6461 static struct obstack proc_frags
;
6462 static procS
*proc_lastP
;
6463 static procS
*proc_rootP
;
6464 static int numprocs
;
6469 obstack_begin (&proc_frags
, 0x2000);
6475 /* check for premature end, nesting errors, etc */
6476 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6477 as_warn ("missing `.end' at end of assembly");
6480 extern char hex_value
[];
6488 if (*input_line_pointer
== '-')
6490 ++input_line_pointer
;
6493 if (!isdigit (*input_line_pointer
))
6494 as_bad ("Expected simple number.");
6495 if (input_line_pointer
[0] == '0')
6497 if (input_line_pointer
[1] == 'x')
6499 input_line_pointer
+= 2;
6500 while (isxdigit (*input_line_pointer
))
6503 val
|= hex_value
[(int) *input_line_pointer
++];
6505 return negative
? -val
: val
;
6509 ++input_line_pointer
;
6510 while (isdigit (*input_line_pointer
))
6513 val
|= *input_line_pointer
++ - '0';
6515 return negative
? -val
: val
;
6518 if (!isdigit (*input_line_pointer
))
6520 printf (" *input_line_pointer == '%c' 0x%02x\n",
6521 *input_line_pointer
, *input_line_pointer
);
6522 as_warn ("Invalid number");
6525 while (isdigit (*input_line_pointer
))
6528 val
+= *input_line_pointer
++ - '0';
6530 return negative
? -val
: val
;
6533 /* The .file directive; just like the usual .file directive, but there
6534 is an initial number which is the ECOFF file index. */
6542 line
= get_number ();
6547 /* The .end directive. */
6555 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6558 demand_empty_rest_of_line ();
6562 if (now_seg
!= text_section
)
6563 as_warn (".end not in text section");
6566 as_warn (".end and no .ent seen yet.");
6572 assert (S_GET_NAME (p
));
6573 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6574 as_warn (".end symbol does not match .ent symbol.");
6577 proc_lastP
->proc_end
= (symbolS
*) 1;
6580 /* The .aent and .ent directives. */
6590 symbolP
= get_symbol ();
6591 if (*input_line_pointer
== ',')
6592 input_line_pointer
++;
6594 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6595 number
= get_number ();
6596 if (now_seg
!= text_section
)
6597 as_warn (".ent or .aent not in text section.");
6599 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6600 as_warn ("missing `.end'");
6604 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6605 procP
->proc_isym
= symbolP
;
6606 procP
->proc_reg_mask
= 0;
6607 procP
->proc_reg_offset
= 0;
6608 procP
->proc_fpreg_mask
= 0;
6609 procP
->proc_fpreg_offset
= 0;
6610 procP
->proc_frameoffset
= 0;
6611 procP
->proc_framereg
= 0;
6612 procP
->proc_pcreg
= 0;
6613 procP
->proc_end
= NULL
;
6614 procP
->proc_next
= NULL
;
6616 proc_lastP
->proc_next
= procP
;
6622 demand_empty_rest_of_line ();
6625 /* The .frame directive. */
6638 frame_reg
= tc_get_register (1);
6639 if (*input_line_pointer
== ',')
6640 input_line_pointer
++;
6641 frame_off
= get_absolute_expression ();
6642 if (*input_line_pointer
== ',')
6643 input_line_pointer
++;
6644 pcreg
= tc_get_register (0);
6647 assert (proc_rootP
);
6648 proc_rootP
->proc_framereg
= frame_reg
;
6649 proc_rootP
->proc_frameoffset
= frame_off
;
6650 proc_rootP
->proc_pcreg
= pcreg
;
6651 /* bob macho .frame */
6653 /* We don't have to write out a frame stab for unoptimized code. */
6654 if (!(frame_reg
== FP
&& frame_off
== 0))
6657 as_warn ("No .ent for .frame to use.");
6658 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6659 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6660 S_SET_TYPE (symP
, N_RMASK
);
6661 S_SET_OTHER (symP
, 0);
6662 S_SET_DESC (symP
, 0);
6663 symP
->sy_forward
= proc_lastP
->proc_isym
;
6664 /* bob perhaps I should have used pseudo set */
6666 demand_empty_rest_of_line ();
6670 /* The .fmask and .mask directives. */
6677 char str
[100], *strP
;
6683 mask
= get_number ();
6684 if (*input_line_pointer
== ',')
6685 input_line_pointer
++;
6686 off
= get_absolute_expression ();
6688 /* bob only for coff */
6689 assert (proc_rootP
);
6690 if (reg_type
== 'F')
6692 proc_rootP
->proc_fpreg_mask
= mask
;
6693 proc_rootP
->proc_fpreg_offset
= off
;
6697 proc_rootP
->proc_reg_mask
= mask
;
6698 proc_rootP
->proc_reg_offset
= off
;
6701 /* bob macho .mask + .fmask */
6703 /* We don't have to write out a mask stab if no saved regs. */
6707 as_warn ("No .ent for .mask to use.");
6709 for (i
= 0; i
< 32; i
++)
6713 sprintf (strP
, "%c%d,", reg_type
, i
);
6714 strP
+= strlen (strP
);
6718 sprintf (strP
, ";%d,", off
);
6719 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6720 S_SET_TYPE (symP
, N_RMASK
);
6721 S_SET_OTHER (symP
, 0);
6722 S_SET_DESC (symP
, 0);
6723 symP
->sy_forward
= proc_lastP
->proc_isym
;
6724 /* bob perhaps I should have used pseudo set */
6729 /* The .loc directive. */
6740 assert (now_seg
== text_section
);
6742 lineno
= get_number ();
6743 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6745 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6746 S_SET_TYPE (symbolP
, N_SLINE
);
6747 S_SET_OTHER (symbolP
, 0);
6748 S_SET_DESC (symbolP
, lineno
);
6749 symbolP
->sy_segment
= now_seg
;
6753 #endif /* ! defined (ECOFF_DEBUGGING) */