1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
116 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
122 /* The ABI to use. */
133 /* MIPS ABI we are using for this output file. */
134 static enum mips_abi_level mips_abi
= NO_ABI
;
136 /* Whether or not we have code that can call pic code. */
137 int mips_abicalls
= FALSE
;
139 /* Whether or not we have code which can be put into a shared
141 static bfd_boolean mips_in_shared
= TRUE
;
143 /* This is the set of options which may be modified by the .set
144 pseudo-op. We use a struct so that .set push and .set pop are more
147 struct mips_set_options
149 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
150 if it has not been initialized. Changed by `.set mipsN', and the
151 -mipsN command line option, and the default CPU. */
153 /* Enabled Application Specific Extensions (ASEs). These are set to -1
154 if they have not been initialized. Changed by `.set <asename>', by
155 command line options, and based on the default architecture. */
158 /* Whether we are assembling for the mips16 processor. 0 if we are
159 not, 1 if we are, and -1 if the value has not been initialized.
160 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
161 -nomips16 command line options, and the default CPU. */
163 /* Non-zero if we should not reorder instructions. Changed by `.set
164 reorder' and `.set noreorder'. */
166 /* Non-zero if we should not permit the $at ($1) register to be used
167 in instructions. Changed by `.set at' and `.set noat'. */
169 /* Non-zero if we should warn when a macro instruction expands into
170 more than one machine instruction. Changed by `.set nomacro' and
172 int warn_about_macros
;
173 /* Non-zero if we should not move instructions. Changed by `.set
174 move', `.set volatile', `.set nomove', and `.set novolatile'. */
176 /* Non-zero if we should not optimize branches by moving the target
177 of the branch into the delay slot. Actually, we don't perform
178 this optimization anyhow. Changed by `.set bopt' and `.set
181 /* Non-zero if we should not autoextend mips16 instructions.
182 Changed by `.set autoextend' and `.set noautoextend'. */
184 /* Restrict general purpose registers and floating point registers
185 to 32 bit. This is initially determined when -mgp32 or -mfp32
186 is passed but can changed if the assembler code uses .set mipsN. */
189 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
190 command line option, and the default CPU. */
194 /* True if -mgp32 was passed. */
195 static int file_mips_gp32
= -1;
197 /* True if -mfp32 was passed. */
198 static int file_mips_fp32
= -1;
200 /* This is the struct we use to hold the current set of options. Note
201 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
202 -1 to indicate that they have not been initialized. */
204 static struct mips_set_options mips_opts
=
206 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
209 /* These variables are filled in with the masks of registers used.
210 The object format code reads them and puts them in the appropriate
212 unsigned long mips_gprmask
;
213 unsigned long mips_cprmask
[4];
215 /* MIPS ISA we are using for this output file. */
216 static int file_mips_isa
= ISA_UNKNOWN
;
218 /* True if -mips16 was passed or implied by arguments passed on the
219 command line (e.g., by -march). */
220 static int file_ase_mips16
;
222 /* True if -mips3d was passed or implied by arguments passed on the
223 command line (e.g., by -march). */
224 static int file_ase_mips3d
;
226 /* True if -mdmx was passed or implied by arguments passed on the
227 command line (e.g., by -march). */
228 static int file_ase_mdmx
;
230 /* The argument of the -march= flag. The architecture we are assembling. */
231 static int file_mips_arch
= CPU_UNKNOWN
;
232 static const char *mips_arch_string
;
234 /* The argument of the -mtune= flag. The architecture for which we
236 static int mips_tune
= CPU_UNKNOWN
;
237 static const char *mips_tune_string
;
239 /* True when generating 32-bit code for a 64-bit processor. */
240 static int mips_32bitmode
= 0;
242 /* True if the given ABI requires 32-bit registers. */
243 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
245 /* Likewise 64-bit registers. */
246 #define ABI_NEEDS_64BIT_REGS(ABI) \
248 || (ABI) == N64_ABI \
251 /* Return true if ISA supports 64 bit gp register instructions. */
252 #define ISA_HAS_64BIT_REGS(ISA) ( \
254 || (ISA) == ISA_MIPS4 \
255 || (ISA) == ISA_MIPS5 \
256 || (ISA) == ISA_MIPS64 \
257 || (ISA) == ISA_MIPS64R2 \
260 /* Return true if ISA supports 64-bit right rotate (dror et al.)
262 #define ISA_HAS_DROR(ISA) ( \
263 (ISA) == ISA_MIPS64R2 \
266 /* Return true if ISA supports 32-bit right rotate (ror et al.)
268 #define ISA_HAS_ROR(ISA) ( \
269 (ISA) == ISA_MIPS32R2 \
270 || (ISA) == ISA_MIPS64R2 \
273 #define HAVE_32BIT_GPRS \
274 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
276 #define HAVE_32BIT_FPRS \
277 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
279 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
280 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
282 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
284 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
286 /* True if relocations are stored in-place. */
287 #define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
289 /* We can only have 64bit addresses if the object file format supports it. */
290 #define HAVE_32BIT_ADDRESSES \
292 || (bfd_arch_bits_per_address (stdoutput) == 32 \
293 || ! HAVE_64BIT_OBJECTS)) \
295 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
297 /* Addresses are loaded in different ways, depending on the address size
298 in use. The n32 ABI Documentation also mandates the use of additions
299 with overflow checking, but existing implementations don't follow it. */
300 #define ADDRESS_ADD_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
303 #define ADDRESS_ADDI_INSN \
304 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
306 #define ADDRESS_LOAD_INSN \
307 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
309 #define ADDRESS_STORE_INSN \
310 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
312 /* Return true if the given CPU supports the MIPS16 ASE. */
313 #define CPU_HAS_MIPS16(cpu) \
314 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
315 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
317 /* Return true if the given CPU supports the MIPS3D ASE. */
318 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
321 /* Return true if the given CPU supports the MDMX ASE. */
322 #define CPU_HAS_MDMX(cpu) (FALSE \
325 /* True if CPU has a dror instruction. */
326 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
328 /* True if CPU has a ror instruction. */
329 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
331 /* True if mflo and mfhi can be immediately followed by instructions
332 which write to the HI and LO registers.
334 According to MIPS specifications, MIPS ISAs I, II, and III need
335 (at least) two instructions between the reads of HI/LO and
336 instructions which write them, and later ISAs do not. Contradicting
337 the MIPS specifications, some MIPS IV processor user manuals (e.g.
338 the UM for the NEC Vr5000) document needing the instructions between
339 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
340 MIPS64 and later ISAs to have the interlocks, plus any specific
341 earlier-ISA CPUs for which CPU documentation declares that the
342 instructions are really interlocked. */
343 #define hilo_interlocks \
344 (mips_opts.isa == ISA_MIPS32 \
345 || mips_opts.isa == ISA_MIPS32R2 \
346 || mips_opts.isa == ISA_MIPS64 \
347 || mips_opts.isa == ISA_MIPS64R2 \
348 || mips_opts.arch == CPU_R4010 \
349 || mips_opts.arch == CPU_R10000 \
350 || mips_opts.arch == CPU_R12000 \
351 || mips_opts.arch == CPU_RM7000 \
352 || mips_opts.arch == CPU_VR5500 \
355 /* Whether the processor uses hardware interlocks to protect reads
356 from the GPRs after they are loaded from memory, and thus does not
357 require nops to be inserted. This applies to instructions marked
358 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
360 #define gpr_interlocks \
361 (mips_opts.isa != ISA_MIPS1 \
362 || mips_opts.arch == CPU_R3900)
364 /* Whether the processor uses hardware interlocks to avoid delays
365 required by coprocessor instructions, and thus does not require
366 nops to be inserted. This applies to instructions marked
367 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
368 between instructions marked INSN_WRITE_COND_CODE and ones marked
369 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
370 levels I, II, and III. */
371 /* Itbl support may require additional care here. */
372 #define cop_interlocks \
373 ((mips_opts.isa != ISA_MIPS1 \
374 && mips_opts.isa != ISA_MIPS2 \
375 && mips_opts.isa != ISA_MIPS3) \
376 || mips_opts.arch == CPU_R4300 \
379 /* Whether the processor uses hardware interlocks to protect reads
380 from coprocessor registers after they are loaded from memory, and
381 thus does not require nops to be inserted. This applies to
382 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
383 requires at MIPS ISA level I. */
384 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
386 /* Is this a mfhi or mflo instruction? */
387 #define MF_HILO_INSN(PINFO) \
388 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
390 /* MIPS PIC level. */
392 enum mips_pic_level mips_pic
;
394 /* 1 if we should generate 32 bit offsets from the $gp register in
395 SVR4_PIC mode. Currently has no meaning in other modes. */
396 static int mips_big_got
= 0;
398 /* 1 if trap instructions should used for overflow rather than break
400 static int mips_trap
= 0;
402 /* 1 if double width floating point constants should not be constructed
403 by assembling two single width halves into two single width floating
404 point registers which just happen to alias the double width destination
405 register. On some architectures this aliasing can be disabled by a bit
406 in the status register, and the setting of this bit cannot be determined
407 automatically at assemble time. */
408 static int mips_disable_float_construction
;
410 /* Non-zero if any .set noreorder directives were used. */
412 static int mips_any_noreorder
;
414 /* Non-zero if nops should be inserted when the register referenced in
415 an mfhi/mflo instruction is read in the next two instructions. */
416 static int mips_7000_hilo_fix
;
418 /* The size of the small data section. */
419 static unsigned int g_switch_value
= 8;
420 /* Whether the -G option was used. */
421 static int g_switch_seen
= 0;
426 /* If we can determine in advance that GP optimization won't be
427 possible, we can skip the relaxation stuff that tries to produce
428 GP-relative references. This makes delay slot optimization work
431 This function can only provide a guess, but it seems to work for
432 gcc output. It needs to guess right for gcc, otherwise gcc
433 will put what it thinks is a GP-relative instruction in a branch
436 I don't know if a fix is needed for the SVR4_PIC mode. I've only
437 fixed it for the non-PIC mode. KR 95/04/07 */
438 static int nopic_need_relax (symbolS
*, int);
440 /* handle of the OPCODE hash table */
441 static struct hash_control
*op_hash
= NULL
;
443 /* The opcode hash table we use for the mips16. */
444 static struct hash_control
*mips16_op_hash
= NULL
;
446 /* This array holds the chars that always start a comment. If the
447 pre-processor is disabled, these aren't very useful */
448 const char comment_chars
[] = "#";
450 /* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
452 .line and .file directives will appear in the pre-processed output */
453 /* Note that input_file.c hand checks for '#' at the beginning of the
454 first line of the input file. This is because the compiler outputs
455 #NO_APP at the beginning of its output. */
456 /* Also note that C style comments are always supported. */
457 const char line_comment_chars
[] = "#";
459 /* This array holds machine specific line separator characters. */
460 const char line_separator_chars
[] = ";";
462 /* Chars that can be used to separate mant from exp in floating point nums */
463 const char EXP_CHARS
[] = "eE";
465 /* Chars that mean this number is a floating point constant */
468 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
470 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
471 changed in read.c . Ideally it shouldn't have to know about it at all,
472 but nothing is ideal around here.
475 static char *insn_error
;
477 static int auto_align
= 1;
479 /* When outputting SVR4 PIC code, the assembler needs to know the
480 offset in the stack frame from which to restore the $gp register.
481 This is set by the .cprestore pseudo-op, and saved in this
483 static offsetT mips_cprestore_offset
= -1;
485 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
486 more optimizations, it can use a register value instead of a memory-saved
487 offset and even an other register than $gp as global pointer. */
488 static offsetT mips_cpreturn_offset
= -1;
489 static int mips_cpreturn_register
= -1;
490 static int mips_gp_register
= GP
;
491 static int mips_gprel_offset
= 0;
493 /* Whether mips_cprestore_offset has been set in the current function
494 (or whether it has already been warned about, if not). */
495 static int mips_cprestore_valid
= 0;
497 /* This is the register which holds the stack frame, as set by the
498 .frame pseudo-op. This is needed to implement .cprestore. */
499 static int mips_frame_reg
= SP
;
501 /* Whether mips_frame_reg has been set in the current function
502 (or whether it has already been warned about, if not). */
503 static int mips_frame_reg_valid
= 0;
505 /* To output NOP instructions correctly, we need to keep information
506 about the previous two instructions. */
508 /* Whether we are optimizing. The default value of 2 means to remove
509 unneeded NOPs and swap branch instructions when possible. A value
510 of 1 means to not swap branches. A value of 0 means to always
512 static int mips_optimize
= 2;
514 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
515 equivalent to seeing no -g option at all. */
516 static int mips_debug
= 0;
518 /* The previous instruction. */
519 static struct mips_cl_insn prev_insn
;
521 /* The instruction before prev_insn. */
522 static struct mips_cl_insn prev_prev_insn
;
524 /* If we don't want information for prev_insn or prev_prev_insn, we
525 point the insn_mo field at this dummy integer. */
526 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
528 /* Non-zero if prev_insn is valid. */
529 static int prev_insn_valid
;
531 /* The frag for the previous instruction. */
532 static struct frag
*prev_insn_frag
;
534 /* The offset into prev_insn_frag for the previous instruction. */
535 static long prev_insn_where
;
537 /* The reloc type for the previous instruction, if any. */
538 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
540 /* The reloc for the previous instruction, if any. */
541 static fixS
*prev_insn_fixp
[3];
543 /* Non-zero if the previous instruction was in a delay slot. */
544 static int prev_insn_is_delay_slot
;
546 /* Non-zero if the previous instruction was in a .set noreorder. */
547 static int prev_insn_unreordered
;
549 /* Non-zero if the previous instruction uses an extend opcode (if
551 static int prev_insn_extended
;
553 /* Non-zero if the previous previous instruction was in a .set
555 static int prev_prev_insn_unreordered
;
557 /* If this is set, it points to a frag holding nop instructions which
558 were inserted before the start of a noreorder section. If those
559 nops turn out to be unnecessary, the size of the frag can be
561 static fragS
*prev_nop_frag
;
563 /* The number of nop instructions we created in prev_nop_frag. */
564 static int prev_nop_frag_holds
;
566 /* The number of nop instructions that we know we need in
568 static int prev_nop_frag_required
;
570 /* The number of instructions we've seen since prev_nop_frag. */
571 static int prev_nop_frag_since
;
573 /* For ECOFF and ELF, relocations against symbols are done in two
574 parts, with a HI relocation and a LO relocation. Each relocation
575 has only 16 bits of space to store an addend. This means that in
576 order for the linker to handle carries correctly, it must be able
577 to locate both the HI and the LO relocation. This means that the
578 relocations must appear in order in the relocation table.
580 In order to implement this, we keep track of each unmatched HI
581 relocation. We then sort them so that they immediately precede the
582 corresponding LO relocation. */
587 struct mips_hi_fixup
*next
;
590 /* The section this fixup is in. */
594 /* The list of unmatched HI relocs. */
596 static struct mips_hi_fixup
*mips_hi_fixup_list
;
598 /* The frag containing the last explicit relocation operator.
599 Null if explicit relocations have not been used. */
601 static fragS
*prev_reloc_op_frag
;
603 /* Map normal MIPS register numbers to mips16 register numbers. */
605 #define X ILLEGAL_REG
606 static const int mips32_to_16_reg_map
[] =
608 X
, X
, 2, 3, 4, 5, 6, 7,
609 X
, X
, X
, X
, X
, X
, X
, X
,
610 0, 1, X
, X
, X
, X
, X
, X
,
611 X
, X
, X
, X
, X
, X
, X
, X
615 /* Map mips16 register numbers to normal MIPS register numbers. */
617 static const unsigned int mips16_to_32_reg_map
[] =
619 16, 17, 2, 3, 4, 5, 6, 7
622 static int mips_fix_vr4120
;
624 /* We don't relax branches by default, since this causes us to expand
625 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
626 fail to compute the offset before expanding the macro to the most
627 efficient expansion. */
629 static int mips_relax_branch
;
631 /* The expansion of many macros depends on the type of symbol that
632 they refer to. For example, when generating position-dependent code,
633 a macro that refers to a symbol may have two different expansions,
634 one which uses GP-relative addresses and one which uses absolute
635 addresses. When generating SVR4-style PIC, a macro may have
636 different expansions for local and global symbols.
638 We handle these situations by generating both sequences and putting
639 them in variant frags. In position-dependent code, the first sequence
640 will be the GP-relative one and the second sequence will be the
641 absolute one. In SVR4 PIC, the first sequence will be for global
642 symbols and the second will be for local symbols.
644 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
645 SECOND are the lengths of the two sequences in bytes. These fields
646 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
647 the subtype has the following flags:
650 Set if it has been decided that we should use the second
651 sequence instead of the first.
654 Set in the first variant frag if the macro's second implementation
655 is longer than its first. This refers to the macro as a whole,
656 not an individual relaxation.
659 Set in the first variant frag if the macro appeared in a .set nomacro
660 block and if one alternative requires a warning but the other does not.
663 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
666 The frag's "opcode" points to the first fixup for relaxable code.
668 Relaxable macros are generated using a sequence such as:
670 relax_start (SYMBOL);
671 ... generate first expansion ...
673 ... generate second expansion ...
676 The code and fixups for the unwanted alternative are discarded
677 by md_convert_frag. */
678 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
680 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
681 #define RELAX_SECOND(X) ((X) & 0xff)
682 #define RELAX_USE_SECOND 0x10000
683 #define RELAX_SECOND_LONGER 0x20000
684 #define RELAX_NOMACRO 0x40000
685 #define RELAX_DELAY_SLOT 0x80000
687 /* Branch without likely bit. If label is out of range, we turn:
689 beq reg1, reg2, label
699 with the following opcode replacements:
706 bltzal <-> bgezal (with jal label instead of j label)
708 Even though keeping the delay slot instruction in the delay slot of
709 the branch would be more efficient, it would be very tricky to do
710 correctly, because we'd have to introduce a variable frag *after*
711 the delay slot instruction, and expand that instead. Let's do it
712 the easy way for now, even if the branch-not-taken case now costs
713 one additional instruction. Out-of-range branches are not supposed
714 to be common, anyway.
716 Branch likely. If label is out of range, we turn:
718 beql reg1, reg2, label
719 delay slot (annulled if branch not taken)
728 delay slot (executed only if branch taken)
731 It would be possible to generate a shorter sequence by losing the
732 likely bit, generating something like:
737 delay slot (executed only if branch taken)
749 bltzall -> bgezal (with jal label instead of j label)
750 bgezall -> bltzal (ditto)
753 but it's not clear that it would actually improve performance. */
754 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
757 | ((toofar) ? 1 : 0) \
759 | ((likely) ? 4 : 0) \
760 | ((uncond) ? 8 : 0)))
761 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
762 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
763 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
764 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
765 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
767 /* For mips16 code, we use an entirely different form of relaxation.
768 mips16 supports two versions of most instructions which take
769 immediate values: a small one which takes some small value, and a
770 larger one which takes a 16 bit value. Since branches also follow
771 this pattern, relaxing these values is required.
773 We can assemble both mips16 and normal MIPS code in a single
774 object. Therefore, we need to support this type of relaxation at
775 the same time that we support the relaxation described above. We
776 use the high bit of the subtype field to distinguish these cases.
778 The information we store for this type of relaxation is the
779 argument code found in the opcode file for this relocation, whether
780 the user explicitly requested a small or extended form, and whether
781 the relocation is in a jump or jal delay slot. That tells us the
782 size of the value, and how it should be stored. We also store
783 whether the fragment is considered to be extended or not. We also
784 store whether this is known to be a branch to a different section,
785 whether we have tried to relax this frag yet, and whether we have
786 ever extended a PC relative fragment because of a shift count. */
787 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
790 | ((small) ? 0x100 : 0) \
791 | ((ext) ? 0x200 : 0) \
792 | ((dslot) ? 0x400 : 0) \
793 | ((jal_dslot) ? 0x800 : 0))
794 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
795 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
796 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
797 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
798 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
799 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
800 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
801 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
802 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
803 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
804 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
805 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
807 /* Is the given value a sign-extended 32-bit value? */
808 #define IS_SEXT_32BIT_NUM(x) \
809 (((x) &~ (offsetT) 0x7fffffff) == 0 \
810 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
812 /* Is the given value a sign-extended 16-bit value? */
813 #define IS_SEXT_16BIT_NUM(x) \
814 (((x) &~ (offsetT) 0x7fff) == 0 \
815 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
818 /* Global variables used when generating relaxable macros. See the
819 comment above RELAX_ENCODE for more details about how relaxation
822 /* 0 if we're not emitting a relaxable macro.
823 1 if we're emitting the first of the two relaxation alternatives.
824 2 if we're emitting the second alternative. */
827 /* The first relaxable fixup in the current frag. (In other words,
828 the first fixup that refers to relaxable code.) */
831 /* sizes[0] says how many bytes of the first alternative are stored in
832 the current frag. Likewise sizes[1] for the second alternative. */
833 unsigned int sizes
[2];
835 /* The symbol on which the choice of sequence depends. */
839 /* Global variables used to decide whether a macro needs a warning. */
841 /* True if the macro is in a branch delay slot. */
842 bfd_boolean delay_slot_p
;
844 /* For relaxable macros, sizes[0] is the length of the first alternative
845 in bytes and sizes[1] is the length of the second alternative.
846 For non-relaxable macros, both elements give the length of the
848 unsigned int sizes
[2];
850 /* The first variant frag for this macro. */
852 } mips_macro_warning
;
854 /* Prototypes for static functions. */
856 #define internalError() \
857 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
859 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
861 static void append_insn
862 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
863 static void mips_no_prev_insn (int);
864 static void mips16_macro_build
865 (expressionS
*, const char *, const char *, va_list);
866 static void load_register (int, expressionS
*, int);
867 static void macro_start (void);
868 static void macro_end (void);
869 static void macro (struct mips_cl_insn
* ip
);
870 static void mips16_macro (struct mips_cl_insn
* ip
);
871 #ifdef LOSING_COMPILER
872 static void macro2 (struct mips_cl_insn
* ip
);
874 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
875 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
876 static void mips16_immed
877 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
878 unsigned long *, bfd_boolean
*, unsigned short *);
879 static size_t my_getSmallExpression
880 (expressionS
*, bfd_reloc_code_real_type
*, char *);
881 static void my_getExpression (expressionS
*, char *);
882 static void s_align (int);
883 static void s_change_sec (int);
884 static void s_change_section (int);
885 static void s_cons (int);
886 static void s_float_cons (int);
887 static void s_mips_globl (int);
888 static void s_option (int);
889 static void s_mipsset (int);
890 static void s_abicalls (int);
891 static void s_cpload (int);
892 static void s_cpsetup (int);
893 static void s_cplocal (int);
894 static void s_cprestore (int);
895 static void s_cpreturn (int);
896 static void s_gpvalue (int);
897 static void s_gpword (int);
898 static void s_gpdword (int);
899 static void s_cpadd (int);
900 static void s_insn (int);
901 static void md_obj_begin (void);
902 static void md_obj_end (void);
903 static void s_mips_ent (int);
904 static void s_mips_end (int);
905 static void s_mips_frame (int);
906 static void s_mips_mask (int reg_type
);
907 static void s_mips_stab (int);
908 static void s_mips_weakext (int);
909 static void s_mips_file (int);
910 static void s_mips_loc (int);
911 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
912 static int relaxed_branch_length (fragS
*, asection
*, int);
913 static int validate_mips_insn (const struct mips_opcode
*);
915 /* Table and functions used to map between CPU/ISA names, and
916 ISA levels, and CPU numbers. */
920 const char *name
; /* CPU or ISA name. */
921 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
922 int isa
; /* ISA level. */
923 int cpu
; /* CPU number (default CPU if ISA). */
926 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
927 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
928 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
932 The following pseudo-ops from the Kane and Heinrich MIPS book
933 should be defined here, but are currently unsupported: .alias,
934 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
936 The following pseudo-ops from the Kane and Heinrich MIPS book are
937 specific to the type of debugging information being generated, and
938 should be defined by the object format: .aent, .begin, .bend,
939 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
942 The following pseudo-ops from the Kane and Heinrich MIPS book are
943 not MIPS CPU specific, but are also not specific to the object file
944 format. This file is probably the best place to define them, but
945 they are not currently supported: .asm0, .endr, .lab, .repeat,
948 static const pseudo_typeS mips_pseudo_table
[] =
950 /* MIPS specific pseudo-ops. */
951 {"option", s_option
, 0},
952 {"set", s_mipsset
, 0},
953 {"rdata", s_change_sec
, 'r'},
954 {"sdata", s_change_sec
, 's'},
955 {"livereg", s_ignore
, 0},
956 {"abicalls", s_abicalls
, 0},
957 {"cpload", s_cpload
, 0},
958 {"cpsetup", s_cpsetup
, 0},
959 {"cplocal", s_cplocal
, 0},
960 {"cprestore", s_cprestore
, 0},
961 {"cpreturn", s_cpreturn
, 0},
962 {"gpvalue", s_gpvalue
, 0},
963 {"gpword", s_gpword
, 0},
964 {"gpdword", s_gpdword
, 0},
965 {"cpadd", s_cpadd
, 0},
968 /* Relatively generic pseudo-ops that happen to be used on MIPS
970 {"asciiz", stringer
, 1},
971 {"bss", s_change_sec
, 'b'},
974 {"dword", s_cons
, 3},
975 {"weakext", s_mips_weakext
, 0},
977 /* These pseudo-ops are defined in read.c, but must be overridden
978 here for one reason or another. */
979 {"align", s_align
, 0},
981 {"data", s_change_sec
, 'd'},
982 {"double", s_float_cons
, 'd'},
983 {"float", s_float_cons
, 'f'},
984 {"globl", s_mips_globl
, 0},
985 {"global", s_mips_globl
, 0},
986 {"hword", s_cons
, 1},
991 {"section", s_change_section
, 0},
992 {"short", s_cons
, 1},
993 {"single", s_float_cons
, 'f'},
994 {"stabn", s_mips_stab
, 'n'},
995 {"text", s_change_sec
, 't'},
998 { "extern", ecoff_directive_extern
, 0},
1003 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1005 /* These pseudo-ops should be defined by the object file format.
1006 However, a.out doesn't support them, so we have versions here. */
1007 {"aent", s_mips_ent
, 1},
1008 {"bgnb", s_ignore
, 0},
1009 {"end", s_mips_end
, 0},
1010 {"endb", s_ignore
, 0},
1011 {"ent", s_mips_ent
, 0},
1012 {"file", s_mips_file
, 0},
1013 {"fmask", s_mips_mask
, 'F'},
1014 {"frame", s_mips_frame
, 0},
1015 {"loc", s_mips_loc
, 0},
1016 {"mask", s_mips_mask
, 'R'},
1017 {"verstamp", s_ignore
, 0},
1021 extern void pop_insert (const pseudo_typeS
*);
1024 mips_pop_insert (void)
1026 pop_insert (mips_pseudo_table
);
1027 if (! ECOFF_DEBUGGING
)
1028 pop_insert (mips_nonecoff_pseudo_table
);
1031 /* Symbols labelling the current insn. */
1033 struct insn_label_list
1035 struct insn_label_list
*next
;
1039 static struct insn_label_list
*insn_labels
;
1040 static struct insn_label_list
*free_insn_labels
;
1042 static void mips_clear_insn_labels (void);
1045 mips_clear_insn_labels (void)
1047 register struct insn_label_list
**pl
;
1049 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1055 static char *expr_end
;
1057 /* Expressions which appear in instructions. These are set by
1060 static expressionS imm_expr
;
1061 static expressionS imm2_expr
;
1062 static expressionS offset_expr
;
1064 /* Relocs associated with imm_expr and offset_expr. */
1066 static bfd_reloc_code_real_type imm_reloc
[3]
1067 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1068 static bfd_reloc_code_real_type offset_reloc
[3]
1069 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1071 /* These are set by mips16_ip if an explicit extension is used. */
1073 static bfd_boolean mips16_small
, mips16_ext
;
1076 /* The pdr segment for per procedure frame/regmask info. Not used for
1079 static segT pdr_seg
;
1082 /* The default target format to use. */
1085 mips_target_format (void)
1087 switch (OUTPUT_FLAVOR
)
1089 case bfd_target_ecoff_flavour
:
1090 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1091 case bfd_target_coff_flavour
:
1093 case bfd_target_elf_flavour
:
1095 /* This is traditional mips. */
1096 return (target_big_endian
1097 ? (HAVE_64BIT_OBJECTS
1098 ? "elf64-tradbigmips"
1100 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1101 : (HAVE_64BIT_OBJECTS
1102 ? "elf64-tradlittlemips"
1104 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1106 return (target_big_endian
1107 ? (HAVE_64BIT_OBJECTS
1110 ? "elf32-nbigmips" : "elf32-bigmips"))
1111 : (HAVE_64BIT_OBJECTS
1112 ? "elf64-littlemips"
1114 ? "elf32-nlittlemips" : "elf32-littlemips")));
1122 /* This function is called once, at assembler startup time. It should
1123 set up all the tables, etc. that the MD part of the assembler will need. */
1128 register const char *retval
= NULL
;
1132 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1133 as_warn (_("Could not set architecture and machine"));
1135 op_hash
= hash_new ();
1137 for (i
= 0; i
< NUMOPCODES
;)
1139 const char *name
= mips_opcodes
[i
].name
;
1141 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1144 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1145 mips_opcodes
[i
].name
, retval
);
1146 /* Probably a memory allocation problem? Give up now. */
1147 as_fatal (_("Broken assembler. No assembly attempted."));
1151 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1153 if (!validate_mips_insn (&mips_opcodes
[i
]))
1158 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1161 mips16_op_hash
= hash_new ();
1164 while (i
< bfd_mips16_num_opcodes
)
1166 const char *name
= mips16_opcodes
[i
].name
;
1168 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1170 as_fatal (_("internal: can't hash `%s': %s"),
1171 mips16_opcodes
[i
].name
, retval
);
1174 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1175 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1176 != mips16_opcodes
[i
].match
))
1178 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1179 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1184 while (i
< bfd_mips16_num_opcodes
1185 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1189 as_fatal (_("Broken assembler. No assembly attempted."));
1191 /* We add all the general register names to the symbol table. This
1192 helps us detect invalid uses of them. */
1193 for (i
= 0; i
< 32; i
++)
1197 sprintf (buf
, "$%d", i
);
1198 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1199 &zero_address_frag
));
1201 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1202 &zero_address_frag
));
1203 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1204 &zero_address_frag
));
1205 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1206 &zero_address_frag
));
1207 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1208 &zero_address_frag
));
1209 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1210 &zero_address_frag
));
1211 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1212 &zero_address_frag
));
1213 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1214 &zero_address_frag
));
1215 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1216 &zero_address_frag
));
1217 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1218 &zero_address_frag
));
1220 /* If we don't add these register names to the symbol table, they
1221 may end up being added as regular symbols by operand(), and then
1222 make it to the object file as undefined in case they're not
1223 regarded as local symbols. They're local in o32, since `$' is a
1224 local symbol prefix, but not in n32 or n64. */
1225 for (i
= 0; i
< 8; i
++)
1229 sprintf (buf
, "$fcc%i", i
);
1230 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1231 &zero_address_frag
));
1234 mips_no_prev_insn (FALSE
);
1237 mips_cprmask
[0] = 0;
1238 mips_cprmask
[1] = 0;
1239 mips_cprmask
[2] = 0;
1240 mips_cprmask
[3] = 0;
1242 /* set the default alignment for the text section (2**2) */
1243 record_alignment (text_section
, 2);
1245 bfd_set_gp_size (stdoutput
, g_switch_value
);
1247 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1249 /* On a native system, sections must be aligned to 16 byte
1250 boundaries. When configured for an embedded ELF target, we
1252 if (strcmp (TARGET_OS
, "elf") != 0)
1254 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1255 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1256 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1259 /* Create a .reginfo section for register masks and a .mdebug
1260 section for debugging information. */
1268 subseg
= now_subseg
;
1270 /* The ABI says this section should be loaded so that the
1271 running program can access it. However, we don't load it
1272 if we are configured for an embedded target */
1273 flags
= SEC_READONLY
| SEC_DATA
;
1274 if (strcmp (TARGET_OS
, "elf") != 0)
1275 flags
|= SEC_ALLOC
| SEC_LOAD
;
1277 if (mips_abi
!= N64_ABI
)
1279 sec
= subseg_new (".reginfo", (subsegT
) 0);
1281 bfd_set_section_flags (stdoutput
, sec
, flags
);
1282 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1285 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1290 /* The 64-bit ABI uses a .MIPS.options section rather than
1291 .reginfo section. */
1292 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1293 bfd_set_section_flags (stdoutput
, sec
, flags
);
1294 bfd_set_section_alignment (stdoutput
, sec
, 3);
1297 /* Set up the option header. */
1299 Elf_Internal_Options opthdr
;
1302 opthdr
.kind
= ODK_REGINFO
;
1303 opthdr
.size
= (sizeof (Elf_External_Options
)
1304 + sizeof (Elf64_External_RegInfo
));
1307 f
= frag_more (sizeof (Elf_External_Options
));
1308 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1309 (Elf_External_Options
*) f
);
1311 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1316 if (ECOFF_DEBUGGING
)
1318 sec
= subseg_new (".mdebug", (subsegT
) 0);
1319 (void) bfd_set_section_flags (stdoutput
, sec
,
1320 SEC_HAS_CONTENTS
| SEC_READONLY
);
1321 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1324 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1326 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1327 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1328 SEC_READONLY
| SEC_RELOC
1330 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1334 subseg_set (seg
, subseg
);
1338 if (! ECOFF_DEBUGGING
)
1345 if (! ECOFF_DEBUGGING
)
1350 md_assemble (char *str
)
1352 struct mips_cl_insn insn
;
1353 bfd_reloc_code_real_type unused_reloc
[3]
1354 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1356 imm_expr
.X_op
= O_absent
;
1357 imm2_expr
.X_op
= O_absent
;
1358 offset_expr
.X_op
= O_absent
;
1359 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1360 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1361 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1362 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1363 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1364 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1366 if (mips_opts
.mips16
)
1367 mips16_ip (str
, &insn
);
1370 mips_ip (str
, &insn
);
1371 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1372 str
, insn
.insn_opcode
));
1377 as_bad ("%s `%s'", insn_error
, str
);
1381 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1384 if (mips_opts
.mips16
)
1385 mips16_macro (&insn
);
1392 if (imm_expr
.X_op
!= O_absent
)
1393 append_insn (&insn
, &imm_expr
, imm_reloc
);
1394 else if (offset_expr
.X_op
!= O_absent
)
1395 append_insn (&insn
, &offset_expr
, offset_reloc
);
1397 append_insn (&insn
, NULL
, unused_reloc
);
1401 /* Return true if the given relocation might need a matching %lo().
1402 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1403 applied to local symbols. */
1405 static inline bfd_boolean
1406 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1408 return (HAVE_IN_PLACE_ADDENDS
1409 && (reloc
== BFD_RELOC_HI16_S
1410 || reloc
== BFD_RELOC_MIPS_GOT16
));
1413 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1416 static inline bfd_boolean
1417 fixup_has_matching_lo_p (fixS
*fixp
)
1419 return (fixp
->fx_next
!= NULL
1420 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1421 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1422 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1425 /* See whether instruction IP reads register REG. CLASS is the type
1429 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1430 enum mips_regclass
class)
1432 if (class == MIPS16_REG
)
1434 assert (mips_opts
.mips16
);
1435 reg
= mips16_to_32_reg_map
[reg
];
1436 class = MIPS_GR_REG
;
1439 /* Don't report on general register ZERO, since it never changes. */
1440 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1443 if (class == MIPS_FP_REG
)
1445 assert (! mips_opts
.mips16
);
1446 /* If we are called with either $f0 or $f1, we must check $f0.
1447 This is not optimal, because it will introduce an unnecessary
1448 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1449 need to distinguish reading both $f0 and $f1 or just one of
1450 them. Note that we don't have to check the other way,
1451 because there is no instruction that sets both $f0 and $f1
1452 and requires a delay. */
1453 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1454 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1455 == (reg
&~ (unsigned) 1)))
1457 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1458 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1459 == (reg
&~ (unsigned) 1)))
1462 else if (! mips_opts
.mips16
)
1464 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1465 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1467 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1468 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1473 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1474 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1475 & MIPS16OP_MASK_RX
)]
1478 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1479 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1480 & MIPS16OP_MASK_RY
)]
1483 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1484 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1485 & MIPS16OP_MASK_MOVE32Z
)]
1488 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1490 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1492 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1494 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1495 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1496 & MIPS16OP_MASK_REGR32
) == reg
)
1503 /* This function returns true if modifying a register requires a
1507 reg_needs_delay (unsigned int reg
)
1509 unsigned long prev_pinfo
;
1511 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1512 if (! mips_opts
.noreorder
1513 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1514 && ! gpr_interlocks
)
1515 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1516 && ! cop_interlocks
)))
1518 /* A load from a coprocessor or from memory. All load delays
1519 delay the use of general register rt for one instruction. */
1520 /* Itbl support may require additional care here. */
1521 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1522 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1529 /* Mark instruction labels in mips16 mode. This permits the linker to
1530 handle them specially, such as generating jalx instructions when
1531 needed. We also make them odd for the duration of the assembly, in
1532 order to generate the right sort of code. We will make them even
1533 in the adjust_symtab routine, while leaving them marked. This is
1534 convenient for the debugger and the disassembler. The linker knows
1535 to make them odd again. */
1538 mips16_mark_labels (void)
1540 if (mips_opts
.mips16
)
1542 struct insn_label_list
*l
;
1545 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1548 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1549 S_SET_OTHER (l
->label
, STO_MIPS16
);
1551 val
= S_GET_VALUE (l
->label
);
1553 S_SET_VALUE (l
->label
, val
+ 1);
1558 /* End the current frag. Make it a variant frag and record the
1562 relax_close_frag (void)
1564 mips_macro_warning
.first_frag
= frag_now
;
1565 frag_var (rs_machine_dependent
, 0, 0,
1566 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1567 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1569 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1570 mips_relax
.first_fixup
= 0;
1573 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1574 See the comment above RELAX_ENCODE for more details. */
1577 relax_start (symbolS
*symbol
)
1579 assert (mips_relax
.sequence
== 0);
1580 mips_relax
.sequence
= 1;
1581 mips_relax
.symbol
= symbol
;
1584 /* Start generating the second version of a relaxable sequence.
1585 See the comment above RELAX_ENCODE for more details. */
1590 assert (mips_relax
.sequence
== 1);
1591 mips_relax
.sequence
= 2;
1594 /* End the current relaxable sequence. */
1599 assert (mips_relax
.sequence
== 2);
1600 relax_close_frag ();
1601 mips_relax
.sequence
= 0;
1604 /* Output an instruction. IP is the instruction information.
1605 ADDRESS_EXPR is an operand of the instruction to be used with
1609 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1610 bfd_reloc_code_real_type
*reloc_type
)
1612 register unsigned long prev_pinfo
, pinfo
;
1616 relax_stateT prev_insn_frag_type
= 0;
1617 bfd_boolean relaxed_branch
= FALSE
;
1618 bfd_boolean force_new_frag
= FALSE
;
1620 /* Mark instruction labels in mips16 mode. */
1621 mips16_mark_labels ();
1623 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1624 pinfo
= ip
->insn_mo
->pinfo
;
1626 if (mips_relax
.sequence
!= 2
1627 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1631 /* If the previous insn required any delay slots, see if we need
1632 to insert a NOP or two. There are eight kinds of possible
1633 hazards, of which an instruction can have at most one type.
1634 (1) a load from memory delay
1635 (2) a load from a coprocessor delay
1636 (3) an unconditional branch delay
1637 (4) a conditional branch delay
1638 (5) a move to coprocessor register delay
1639 (6) a load coprocessor register from memory delay
1640 (7) a coprocessor condition code delay
1641 (8) a HI/LO special register delay
1643 There are a lot of optimizations we could do that we don't.
1644 In particular, we do not, in general, reorder instructions.
1645 If you use gcc with optimization, it will reorder
1646 instructions and generally do much more optimization then we
1647 do here; repeating all that work in the assembler would only
1648 benefit hand written assembly code, and does not seem worth
1651 /* This is how a NOP is emitted. */
1652 #define emit_nop() \
1654 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1655 : md_number_to_chars (frag_more (4), 0, 4))
1657 /* The previous insn might require a delay slot, depending upon
1658 the contents of the current insn. */
1659 if (! mips_opts
.mips16
1660 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1661 && ! gpr_interlocks
)
1662 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1663 && ! cop_interlocks
)))
1665 /* A load from a coprocessor or from memory. All load
1666 delays delay the use of general register rt for one
1668 /* Itbl support may require additional care here. */
1669 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1670 if (mips_optimize
== 0
1671 || insn_uses_reg (ip
,
1672 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1677 else if (! mips_opts
.mips16
1678 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1679 && ! cop_interlocks
)
1680 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1681 && ! cop_mem_interlocks
)))
1683 /* A generic coprocessor delay. The previous instruction
1684 modified a coprocessor general or control register. If
1685 it modified a control register, we need to avoid any
1686 coprocessor instruction (this is probably not always
1687 required, but it sometimes is). If it modified a general
1688 register, we avoid using that register.
1690 This case is not handled very well. There is no special
1691 knowledge of CP0 handling, and the coprocessors other
1692 than the floating point unit are not distinguished at
1694 /* Itbl support may require additional care here. FIXME!
1695 Need to modify this to include knowledge about
1696 user specified delays! */
1697 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1699 if (mips_optimize
== 0
1700 || insn_uses_reg (ip
,
1701 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1706 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1708 if (mips_optimize
== 0
1709 || insn_uses_reg (ip
,
1710 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1717 /* We don't know exactly what the previous instruction
1718 does. If the current instruction uses a coprocessor
1719 register, we must insert a NOP. If previous
1720 instruction may set the condition codes, and the
1721 current instruction uses them, we must insert two
1723 /* Itbl support may require additional care here. */
1724 if (mips_optimize
== 0
1725 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1726 && (pinfo
& INSN_READ_COND_CODE
)))
1728 else if (pinfo
& INSN_COP
)
1732 else if (! mips_opts
.mips16
1733 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1734 && ! cop_interlocks
)
1736 /* The previous instruction sets the coprocessor condition
1737 codes, but does not require a general coprocessor delay
1738 (this means it is a floating point comparison
1739 instruction). If this instruction uses the condition
1740 codes, we need to insert a single NOP. */
1741 /* Itbl support may require additional care here. */
1742 if (mips_optimize
== 0
1743 || (pinfo
& INSN_READ_COND_CODE
))
1747 /* If we're fixing up mfhi/mflo for the r7000 and the
1748 previous insn was an mfhi/mflo and the current insn
1749 reads the register that the mfhi/mflo wrote to, then
1752 else if (mips_7000_hilo_fix
1753 && MF_HILO_INSN (prev_pinfo
)
1754 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1761 /* If we're fixing up mfhi/mflo for the r7000 and the
1762 2nd previous insn was an mfhi/mflo and the current insn
1763 reads the register that the mfhi/mflo wrote to, then
1766 else if (mips_7000_hilo_fix
1767 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1768 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1776 else if (prev_pinfo
& INSN_READ_LO
)
1778 /* The previous instruction reads the LO register; if the
1779 current instruction writes to the LO register, we must
1780 insert two NOPS. Some newer processors have interlocks.
1781 Also the tx39's multiply instructions can be executed
1782 immediately after a read from HI/LO (without the delay),
1783 though the tx39's divide insns still do require the
1785 if (! (hilo_interlocks
1786 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1787 && (mips_optimize
== 0
1788 || (pinfo
& INSN_WRITE_LO
)))
1790 /* Most mips16 branch insns don't have a delay slot.
1791 If a read from LO is immediately followed by a branch
1792 to a write to LO we have a read followed by a write
1793 less than 2 insns away. We assume the target of
1794 a branch might be a write to LO, and insert a nop
1795 between a read and an immediately following branch. */
1796 else if (mips_opts
.mips16
1797 && (mips_optimize
== 0
1798 || (pinfo
& MIPS16_INSN_BRANCH
)))
1801 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1803 /* The previous instruction reads the HI register; if the
1804 current instruction writes to the HI register, we must
1805 insert a NOP. Some newer processors have interlocks.
1806 Also the note tx39's multiply above. */
1807 if (! (hilo_interlocks
1808 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1809 && (mips_optimize
== 0
1810 || (pinfo
& INSN_WRITE_HI
)))
1812 /* Most mips16 branch insns don't have a delay slot.
1813 If a read from HI is immediately followed by a branch
1814 to a write to HI we have a read followed by a write
1815 less than 2 insns away. We assume the target of
1816 a branch might be a write to HI, and insert a nop
1817 between a read and an immediately following branch. */
1818 else if (mips_opts
.mips16
1819 && (mips_optimize
== 0
1820 || (pinfo
& MIPS16_INSN_BRANCH
)))
1824 /* If the previous instruction was in a noreorder section, then
1825 we don't want to insert the nop after all. */
1826 /* Itbl support may require additional care here. */
1827 if (prev_insn_unreordered
)
1830 /* There are two cases which require two intervening
1831 instructions: 1) setting the condition codes using a move to
1832 coprocessor instruction which requires a general coprocessor
1833 delay and then reading the condition codes 2) reading the HI
1834 or LO register and then writing to it (except on processors
1835 which have interlocks). If we are not already emitting a NOP
1836 instruction, we must check for these cases compared to the
1837 instruction previous to the previous instruction. */
1838 if ((! mips_opts
.mips16
1839 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1840 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1841 && (pinfo
& INSN_READ_COND_CODE
)
1842 && ! cop_interlocks
)
1843 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1844 && (pinfo
& INSN_WRITE_LO
)
1845 && ! (hilo_interlocks
1846 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1847 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1848 && (pinfo
& INSN_WRITE_HI
)
1849 && ! (hilo_interlocks
1850 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1855 if (prev_prev_insn_unreordered
)
1858 if (prev_prev_nop
&& nops
== 0)
1861 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1863 /* We're out of bits in pinfo, so we must resort to string
1864 ops here. Shortcuts are selected based on opcodes being
1865 limited to the VR4120 instruction set. */
1867 const char *pn
= prev_insn
.insn_mo
->name
;
1868 const char *tn
= ip
->insn_mo
->name
;
1869 if (strncmp (pn
, "macc", 4) == 0
1870 || strncmp (pn
, "dmacc", 5) == 0)
1872 /* Errata 21 - [D]DIV[U] after [D]MACC */
1873 if (strstr (tn
, "div"))
1876 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1877 instruction is executed immediately after a MACC or
1878 DMACC instruction, the result of [either instruction]
1880 if (strncmp (tn
, "mult", 4) == 0
1881 || strncmp (tn
, "dmult", 5) == 0)
1884 /* Errata 23 - Continuous DMULT[U]/DMACC instructions.
1885 Applies on top of VR4181A MD(1) errata. */
1886 if (pn
[0] == 'd' && strncmp (tn
, "dmacc", 5) == 0)
1889 /* Errata 24 - MT{LO,HI} after [D]MACC */
1890 if (strcmp (tn
, "mtlo") == 0
1891 || strcmp (tn
, "mthi") == 0)
1894 else if (strncmp (pn
, "dmult", 5) == 0
1895 && (strncmp (tn
, "dmult", 5) == 0
1896 || strncmp (tn
, "dmacc", 5) == 0))
1898 /* Here is the rest of errata 23. */
1901 else if ((strncmp (pn
, "dmult", 5) == 0 || strstr (pn
, "div"))
1902 && (strncmp (tn
, "macc", 4) == 0
1903 || strncmp (tn
, "dmacc", 5) == 0))
1905 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1906 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1907 DDIV or DDIVU instruction, the result of the MACC or
1908 DMACC instruction is incorrect.". This partly overlaps
1909 the workaround for errata 23. */
1912 if (nops
< min_nops
)
1916 /* If we are being given a nop instruction, don't bother with
1917 one of the nops we would otherwise output. This will only
1918 happen when a nop instruction is used with mips_optimize set
1921 && ! mips_opts
.noreorder
1922 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1925 /* Now emit the right number of NOP instructions. */
1926 if (nops
> 0 && ! mips_opts
.noreorder
)
1929 unsigned long old_frag_offset
;
1931 struct insn_label_list
*l
;
1933 old_frag
= frag_now
;
1934 old_frag_offset
= frag_now_fix ();
1936 for (i
= 0; i
< nops
; i
++)
1941 listing_prev_line ();
1942 /* We may be at the start of a variant frag. In case we
1943 are, make sure there is enough space for the frag
1944 after the frags created by listing_prev_line. The
1945 argument to frag_grow here must be at least as large
1946 as the argument to all other calls to frag_grow in
1947 this file. We don't have to worry about being in the
1948 middle of a variant frag, because the variants insert
1949 all needed nop instructions themselves. */
1953 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1957 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1958 symbol_set_frag (l
->label
, frag_now
);
1959 val
= (valueT
) frag_now_fix ();
1960 /* mips16 text labels are stored as odd. */
1961 if (mips_opts
.mips16
)
1963 S_SET_VALUE (l
->label
, val
);
1966 #ifndef NO_ECOFF_DEBUGGING
1967 if (ECOFF_DEBUGGING
)
1968 ecoff_fix_loc (old_frag
, old_frag_offset
);
1971 else if (prev_nop_frag
!= NULL
)
1973 /* We have a frag holding nops we may be able to remove. If
1974 we don't need any nops, we can decrease the size of
1975 prev_nop_frag by the size of one instruction. If we do
1976 need some nops, we count them in prev_nops_required. */
1977 if (prev_nop_frag_since
== 0)
1981 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1982 --prev_nop_frag_holds
;
1985 prev_nop_frag_required
+= nops
;
1989 if (prev_prev_nop
== 0)
1991 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1992 --prev_nop_frag_holds
;
1995 ++prev_nop_frag_required
;
1998 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1999 prev_nop_frag
= NULL
;
2001 ++prev_nop_frag_since
;
2003 /* Sanity check: by the time we reach the second instruction
2004 after prev_nop_frag, we should have used up all the nops
2005 one way or another. */
2006 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
2010 /* Record the frag type before frag_var. */
2012 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
2015 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2016 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2017 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2018 && mips_relax_branch
2019 /* Don't try branch relaxation within .set nomacro, or within
2020 .set noat if we use $at for PIC computations. If it turns
2021 out that the branch was out-of-range, we'll get an error. */
2022 && !mips_opts
.warn_about_macros
2023 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2024 && !mips_opts
.mips16
)
2026 relaxed_branch
= TRUE
;
2027 f
= frag_var (rs_machine_dependent
,
2028 relaxed_branch_length
2030 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2031 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2033 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2034 pinfo
& INSN_COND_BRANCH_LIKELY
,
2035 pinfo
& INSN_WRITE_GPR_31
,
2037 address_expr
->X_add_symbol
,
2038 address_expr
->X_add_number
,
2040 *reloc_type
= BFD_RELOC_UNUSED
;
2042 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2044 /* We need to set up a variant frag. */
2045 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2046 f
= frag_var (rs_machine_dependent
, 4, 0,
2047 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2048 mips16_small
, mips16_ext
,
2050 & INSN_UNCOND_BRANCH_DELAY
),
2051 (*prev_insn_reloc_type
2052 == BFD_RELOC_MIPS16_JMP
)),
2053 make_expr_symbol (address_expr
), 0, NULL
);
2055 else if (mips_opts
.mips16
2057 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2059 /* Make sure there is enough room to swap this instruction with
2060 a following jump instruction. */
2066 if (mips_opts
.mips16
2067 && mips_opts
.noreorder
2068 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2069 as_warn (_("extended instruction in delay slot"));
2071 if (mips_relax
.sequence
)
2073 /* If we've reached the end of this frag, turn it into a variant
2074 frag and record the information for the instructions we've
2076 if (frag_room () < 4)
2077 relax_close_frag ();
2078 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2081 if (mips_relax
.sequence
!= 2)
2082 mips_macro_warning
.sizes
[0] += 4;
2083 if (mips_relax
.sequence
!= 1)
2084 mips_macro_warning
.sizes
[1] += 4;
2089 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2090 if (address_expr
!= NULL
&& *reloc_type
<= BFD_RELOC_UNUSED
)
2092 if (address_expr
->X_op
== O_constant
)
2096 switch (*reloc_type
)
2099 ip
->insn_opcode
|= address_expr
->X_add_number
;
2102 case BFD_RELOC_MIPS_HIGHEST
:
2103 tmp
= (address_expr
->X_add_number
2104 + ((valueT
) 0x8000 << 32) + 0x80008000) >> 16;
2106 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2109 case BFD_RELOC_MIPS_HIGHER
:
2110 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2111 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2114 case BFD_RELOC_HI16_S
:
2115 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2119 case BFD_RELOC_HI16
:
2120 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2123 case BFD_RELOC_UNUSED
:
2124 case BFD_RELOC_LO16
:
2125 case BFD_RELOC_MIPS_GOT_DISP
:
2126 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2129 case BFD_RELOC_MIPS_JMP
:
2130 if ((address_expr
->X_add_number
& 3) != 0)
2131 as_bad (_("jump to misaligned address (0x%lx)"),
2132 (unsigned long) address_expr
->X_add_number
);
2133 if (address_expr
->X_add_number
& ~0xfffffff)
2134 as_bad (_("jump address range overflow (0x%lx)"),
2135 (unsigned long) address_expr
->X_add_number
);
2136 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2139 case BFD_RELOC_MIPS16_JMP
:
2140 if ((address_expr
->X_add_number
& 3) != 0)
2141 as_bad (_("jump to misaligned address (0x%lx)"),
2142 (unsigned long) address_expr
->X_add_number
);
2143 if (address_expr
->X_add_number
& ~0xfffffff)
2144 as_bad (_("jump address range overflow (0x%lx)"),
2145 (unsigned long) address_expr
->X_add_number
);
2147 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2148 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2149 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2152 case BFD_RELOC_16_PCREL_S2
:
2159 else if (*reloc_type
< BFD_RELOC_UNUSED
)
2162 reloc_howto_type
*howto
;
2165 /* In a compound relocation, it is the final (outermost)
2166 operator that determines the relocated field. */
2167 for (i
= 1; i
< 3; i
++)
2168 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2171 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2172 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2173 bfd_get_reloc_size(howto
),
2175 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2178 /* These relocations can have an addend that won't fit in
2179 4 octets for 64bit assembly. */
2181 && ! howto
->partial_inplace
2182 && (reloc_type
[0] == BFD_RELOC_16
2183 || reloc_type
[0] == BFD_RELOC_32
2184 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2185 || reloc_type
[0] == BFD_RELOC_HI16_S
2186 || reloc_type
[0] == BFD_RELOC_LO16
2187 || reloc_type
[0] == BFD_RELOC_GPREL16
2188 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2189 || reloc_type
[0] == BFD_RELOC_GPREL32
2190 || reloc_type
[0] == BFD_RELOC_64
2191 || reloc_type
[0] == BFD_RELOC_CTOR
2192 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2193 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2194 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2195 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2196 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2197 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2198 fixp
[0]->fx_no_overflow
= 1;
2200 if (mips_relax
.sequence
)
2202 if (mips_relax
.first_fixup
== 0)
2203 mips_relax
.first_fixup
= fixp
[0];
2205 else if (reloc_needs_lo_p (*reloc_type
))
2207 struct mips_hi_fixup
*hi_fixup
;
2209 /* Reuse the last entry if it already has a matching %lo. */
2210 hi_fixup
= mips_hi_fixup_list
;
2212 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2214 hi_fixup
= ((struct mips_hi_fixup
*)
2215 xmalloc (sizeof (struct mips_hi_fixup
)));
2216 hi_fixup
->next
= mips_hi_fixup_list
;
2217 mips_hi_fixup_list
= hi_fixup
;
2219 hi_fixup
->fixp
= fixp
[0];
2220 hi_fixup
->seg
= now_seg
;
2223 /* Add fixups for the second and third relocations, if given.
2224 Note that the ABI allows the second relocation to be
2225 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2226 moment we only use RSS_UNDEF, but we could add support
2227 for the others if it ever becomes necessary. */
2228 for (i
= 1; i
< 3; i
++)
2229 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2231 fixp
[i
] = fix_new (frag_now
, fixp
[0]->fx_where
,
2232 fixp
[0]->fx_size
, NULL
, 0,
2233 FALSE
, reloc_type
[i
]);
2235 /* Use fx_tcbit to mark compound relocs. */
2236 fixp
[0]->fx_tcbit
= 1;
2237 fixp
[i
]->fx_tcbit
= 1;
2242 if (! mips_opts
.mips16
)
2244 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2246 dwarf2_emit_insn (4);
2249 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2251 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2252 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2254 /* The value passed to dwarf2_emit_insn is the distance between
2255 the end of the current instruction and the address that should
2256 be recorded in the debug tables. Since we want to use ISA-encoded
2257 addresses in MIPS16 debug info, the value is one byte less than
2258 the real instruction length. */
2259 dwarf2_emit_insn (3);
2266 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2269 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2271 dwarf2_emit_insn (ip
->use_extend
? 3 : 1);
2275 /* Update the register mask information. */
2276 if (! mips_opts
.mips16
)
2278 if (pinfo
& INSN_WRITE_GPR_D
)
2279 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2280 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2281 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2282 if (pinfo
& INSN_READ_GPR_S
)
2283 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2284 if (pinfo
& INSN_WRITE_GPR_31
)
2285 mips_gprmask
|= 1 << RA
;
2286 if (pinfo
& INSN_WRITE_FPR_D
)
2287 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2288 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2289 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2290 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2291 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2292 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2293 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2294 if (pinfo
& INSN_COP
)
2296 /* We don't keep enough information to sort these cases out.
2297 The itbl support does keep this information however, although
2298 we currently don't support itbl fprmats as part of the cop
2299 instruction. May want to add this support in the future. */
2301 /* Never set the bit for $0, which is always zero. */
2302 mips_gprmask
&= ~1 << 0;
2306 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2307 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2308 & MIPS16OP_MASK_RX
);
2309 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2310 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2311 & MIPS16OP_MASK_RY
);
2312 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2313 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2314 & MIPS16OP_MASK_RZ
);
2315 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2316 mips_gprmask
|= 1 << TREG
;
2317 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2318 mips_gprmask
|= 1 << SP
;
2319 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2320 mips_gprmask
|= 1 << RA
;
2321 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2322 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2323 if (pinfo
& MIPS16_INSN_READ_Z
)
2324 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2325 & MIPS16OP_MASK_MOVE32Z
);
2326 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2327 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2328 & MIPS16OP_MASK_REGR32
);
2331 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2333 /* Filling the branch delay slot is more complex. We try to
2334 switch the branch with the previous instruction, which we can
2335 do if the previous instruction does not set up a condition
2336 that the branch tests and if the branch is not itself the
2337 target of any branch. */
2338 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2339 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2341 if (mips_optimize
< 2
2342 /* If we have seen .set volatile or .set nomove, don't
2344 || mips_opts
.nomove
!= 0
2345 /* If we had to emit any NOP instructions, then we
2346 already know we can not swap. */
2348 /* If we don't even know the previous insn, we can not
2350 || ! prev_insn_valid
2351 /* If the previous insn is already in a branch delay
2352 slot, then we can not swap. */
2353 || prev_insn_is_delay_slot
2354 /* If the previous previous insn was in a .set
2355 noreorder, we can't swap. Actually, the MIPS
2356 assembler will swap in this situation. However, gcc
2357 configured -with-gnu-as will generate code like
2363 in which we can not swap the bne and INSN. If gcc is
2364 not configured -with-gnu-as, it does not output the
2365 .set pseudo-ops. We don't have to check
2366 prev_insn_unreordered, because prev_insn_valid will
2367 be 0 in that case. We don't want to use
2368 prev_prev_insn_valid, because we do want to be able
2369 to swap at the start of a function. */
2370 || prev_prev_insn_unreordered
2371 /* If the branch is itself the target of a branch, we
2372 can not swap. We cheat on this; all we check for is
2373 whether there is a label on this instruction. If
2374 there are any branches to anything other than a
2375 label, users must use .set noreorder. */
2376 || insn_labels
!= NULL
2377 /* If the previous instruction is in a variant frag
2378 other than this branch's one, we cannot do the swap.
2379 This does not apply to the mips16, which uses variant
2380 frags for different purposes. */
2381 || (! mips_opts
.mips16
2382 && prev_insn_frag_type
== rs_machine_dependent
)
2383 /* If the branch reads the condition codes, we don't
2384 even try to swap, because in the sequence
2389 we can not swap, and I don't feel like handling that
2391 || (! mips_opts
.mips16
2392 && (pinfo
& INSN_READ_COND_CODE
)
2393 && ! cop_interlocks
)
2394 /* We can not swap with an instruction that requires a
2395 delay slot, because the target of the branch might
2396 interfere with that instruction. */
2397 || (! mips_opts
.mips16
2399 /* Itbl support may require additional care here. */
2400 & (INSN_LOAD_COPROC_DELAY
2401 | INSN_COPROC_MOVE_DELAY
2402 | INSN_WRITE_COND_CODE
))
2403 && ! cop_interlocks
)
2404 || (! (hilo_interlocks
2405 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2409 || (! mips_opts
.mips16
2410 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2411 && ! gpr_interlocks
)
2412 || (! mips_opts
.mips16
2413 /* Itbl support may require additional care here. */
2414 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2415 && ! cop_mem_interlocks
)
2416 /* We can not swap with a branch instruction. */
2418 & (INSN_UNCOND_BRANCH_DELAY
2419 | INSN_COND_BRANCH_DELAY
2420 | INSN_COND_BRANCH_LIKELY
))
2421 /* We do not swap with a trap instruction, since it
2422 complicates trap handlers to have the trap
2423 instruction be in a delay slot. */
2424 || (prev_pinfo
& INSN_TRAP
)
2425 /* If the branch reads a register that the previous
2426 instruction sets, we can not swap. */
2427 || (! mips_opts
.mips16
2428 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2429 && insn_uses_reg (ip
,
2430 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2433 || (! mips_opts
.mips16
2434 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2435 && insn_uses_reg (ip
,
2436 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2439 || (mips_opts
.mips16
2440 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2441 && insn_uses_reg (ip
,
2442 ((prev_insn
.insn_opcode
2444 & MIPS16OP_MASK_RX
),
2446 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2447 && insn_uses_reg (ip
,
2448 ((prev_insn
.insn_opcode
2450 & MIPS16OP_MASK_RY
),
2452 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2453 && insn_uses_reg (ip
,
2454 ((prev_insn
.insn_opcode
2456 & MIPS16OP_MASK_RZ
),
2458 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2459 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2460 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2461 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2462 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2463 && insn_uses_reg (ip
,
2464 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2467 /* If the branch writes a register that the previous
2468 instruction sets, we can not swap (we know that
2469 branches write only to RD or to $31). */
2470 || (! mips_opts
.mips16
2471 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2472 && (((pinfo
& INSN_WRITE_GPR_D
)
2473 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2474 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2475 || ((pinfo
& INSN_WRITE_GPR_31
)
2476 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2479 || (! mips_opts
.mips16
2480 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2481 && (((pinfo
& INSN_WRITE_GPR_D
)
2482 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2483 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2484 || ((pinfo
& INSN_WRITE_GPR_31
)
2485 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2488 || (mips_opts
.mips16
2489 && (pinfo
& MIPS16_INSN_WRITE_31
)
2490 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2491 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2492 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2494 /* If the branch writes a register that the previous
2495 instruction reads, we can not swap (we know that
2496 branches only write to RD or to $31). */
2497 || (! mips_opts
.mips16
2498 && (pinfo
& INSN_WRITE_GPR_D
)
2499 && insn_uses_reg (&prev_insn
,
2500 ((ip
->insn_opcode
>> OP_SH_RD
)
2503 || (! mips_opts
.mips16
2504 && (pinfo
& INSN_WRITE_GPR_31
)
2505 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2506 || (mips_opts
.mips16
2507 && (pinfo
& MIPS16_INSN_WRITE_31
)
2508 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2509 /* If the previous previous instruction has a load
2510 delay, and sets a register that the branch reads, we
2512 || (! mips_opts
.mips16
2513 /* Itbl support may require additional care here. */
2514 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2515 && ! cop_interlocks
)
2516 || ((prev_prev_insn
.insn_mo
->pinfo
2517 & INSN_LOAD_MEMORY_DELAY
)
2518 && ! gpr_interlocks
))
2519 && insn_uses_reg (ip
,
2520 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2523 /* If one instruction sets a condition code and the
2524 other one uses a condition code, we can not swap. */
2525 || ((pinfo
& INSN_READ_COND_CODE
)
2526 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2527 || ((pinfo
& INSN_WRITE_COND_CODE
)
2528 && (prev_pinfo
& INSN_READ_COND_CODE
))
2529 /* If the previous instruction uses the PC, we can not
2531 || (mips_opts
.mips16
2532 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2533 /* If the previous instruction was extended, we can not
2535 || (mips_opts
.mips16
&& prev_insn_extended
)
2536 /* If the previous instruction had a fixup in mips16
2537 mode, we can not swap. This normally means that the
2538 previous instruction was a 4 byte branch anyhow. */
2539 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2540 /* If the previous instruction is a sync, sync.l, or
2541 sync.p, we can not swap. */
2542 || (prev_pinfo
& INSN_SYNC
))
2544 /* We could do even better for unconditional branches to
2545 portions of this object file; we could pick up the
2546 instruction at the destination, put it in the delay
2547 slot, and bump the destination address. */
2549 if (mips_relax
.sequence
)
2550 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2551 /* Update the previous insn information. */
2552 prev_prev_insn
= *ip
;
2553 prev_insn
.insn_mo
= &dummy_opcode
;
2557 /* It looks like we can actually do the swap. */
2558 if (! mips_opts
.mips16
)
2563 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2564 if (!relaxed_branch
)
2566 /* If this is not a relaxed branch, then just
2567 swap the instructions. */
2568 memcpy (temp
, prev_f
, 4);
2569 memcpy (prev_f
, f
, 4);
2570 memcpy (f
, temp
, 4);
2574 /* If this is a relaxed branch, then we move the
2575 instruction to be placed in the delay slot to
2576 the current frag, shrinking the fixed part of
2577 the originating frag. If the branch occupies
2578 the tail of the latter, we move it backwards,
2579 into the space freed by the moved instruction. */
2581 memcpy (f
, prev_f
, 4);
2582 prev_insn_frag
->fr_fix
-= 4;
2583 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2584 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2587 if (prev_insn_fixp
[0])
2589 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2590 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2592 if (prev_insn_fixp
[1])
2594 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2595 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2597 if (prev_insn_fixp
[2])
2599 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2600 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2602 if (prev_insn_fixp
[0] && HAVE_NEWABI
2603 && prev_insn_frag
!= frag_now
2604 && (prev_insn_fixp
[0]->fx_r_type
2605 == BFD_RELOC_MIPS_GOT_DISP
2606 || (prev_insn_fixp
[0]->fx_r_type
2607 == BFD_RELOC_MIPS_CALL16
)))
2609 /* To avoid confusion in tc_gen_reloc, we must
2610 ensure that this does not become a variant
2612 force_new_frag
= TRUE
;
2615 if (!relaxed_branch
)
2619 fixp
[0]->fx_frag
= prev_insn_frag
;
2620 fixp
[0]->fx_where
= prev_insn_where
;
2624 fixp
[1]->fx_frag
= prev_insn_frag
;
2625 fixp
[1]->fx_where
= prev_insn_where
;
2629 fixp
[2]->fx_frag
= prev_insn_frag
;
2630 fixp
[2]->fx_where
= prev_insn_where
;
2633 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2636 fixp
[0]->fx_where
-= 4;
2638 fixp
[1]->fx_where
-= 4;
2640 fixp
[2]->fx_where
-= 4;
2648 assert (prev_insn_fixp
[0] == NULL
);
2649 assert (prev_insn_fixp
[1] == NULL
);
2650 assert (prev_insn_fixp
[2] == NULL
);
2651 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2652 memcpy (temp
, prev_f
, 2);
2653 memcpy (prev_f
, f
, 2);
2654 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2656 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2657 memcpy (f
, temp
, 2);
2661 memcpy (f
, f
+ 2, 2);
2662 memcpy (f
+ 2, temp
, 2);
2666 fixp
[0]->fx_frag
= prev_insn_frag
;
2667 fixp
[0]->fx_where
= prev_insn_where
;
2671 fixp
[1]->fx_frag
= prev_insn_frag
;
2672 fixp
[1]->fx_where
= prev_insn_where
;
2676 fixp
[2]->fx_frag
= prev_insn_frag
;
2677 fixp
[2]->fx_where
= prev_insn_where
;
2681 /* Update the previous insn information; leave prev_insn
2683 prev_prev_insn
= *ip
;
2685 prev_insn_is_delay_slot
= 1;
2687 /* If that was an unconditional branch, forget the previous
2688 insn information. */
2689 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2691 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2692 prev_insn
.insn_mo
= &dummy_opcode
;
2695 prev_insn_fixp
[0] = NULL
;
2696 prev_insn_fixp
[1] = NULL
;
2697 prev_insn_fixp
[2] = NULL
;
2698 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2699 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2700 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2701 prev_insn_extended
= 0;
2703 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2705 /* We don't yet optimize a branch likely. What we should do
2706 is look at the target, copy the instruction found there
2707 into the delay slot, and increment the branch to jump to
2708 the next instruction. */
2710 /* Update the previous insn information. */
2711 prev_prev_insn
= *ip
;
2712 prev_insn
.insn_mo
= &dummy_opcode
;
2713 prev_insn_fixp
[0] = NULL
;
2714 prev_insn_fixp
[1] = NULL
;
2715 prev_insn_fixp
[2] = NULL
;
2716 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2717 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2718 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2719 prev_insn_extended
= 0;
2720 prev_insn_is_delay_slot
= 1;
2724 /* Update the previous insn information. */
2726 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2728 prev_prev_insn
= prev_insn
;
2731 /* Any time we see a branch, we always fill the delay slot
2732 immediately; since this insn is not a branch, we know it
2733 is not in a delay slot. */
2734 prev_insn_is_delay_slot
= 0;
2736 prev_insn_fixp
[0] = fixp
[0];
2737 prev_insn_fixp
[1] = fixp
[1];
2738 prev_insn_fixp
[2] = fixp
[2];
2739 prev_insn_reloc_type
[0] = reloc_type
[0];
2740 prev_insn_reloc_type
[1] = reloc_type
[1];
2741 prev_insn_reloc_type
[2] = reloc_type
[2];
2742 if (mips_opts
.mips16
)
2743 prev_insn_extended
= (ip
->use_extend
2744 || *reloc_type
> BFD_RELOC_UNUSED
);
2747 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2748 prev_insn_unreordered
= 0;
2749 prev_insn_frag
= frag_now
;
2750 prev_insn_where
= f
- frag_now
->fr_literal
;
2751 prev_insn_valid
= 1;
2753 else if (mips_relax
.sequence
!= 2)
2755 /* We need to record a bit of information even when we are not
2756 reordering, in order to determine the base address for mips16
2757 PC relative relocs. */
2758 prev_prev_insn
= prev_insn
;
2760 prev_insn_reloc_type
[0] = reloc_type
[0];
2761 prev_insn_reloc_type
[1] = reloc_type
[1];
2762 prev_insn_reloc_type
[2] = reloc_type
[2];
2763 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2764 prev_insn_unreordered
= 1;
2767 /* We just output an insn, so the next one doesn't have a label. */
2768 mips_clear_insn_labels ();
2771 /* This function forgets that there was any previous instruction or
2772 label. If PRESERVE is non-zero, it remembers enough information to
2773 know whether nops are needed before a noreorder section. */
2776 mips_no_prev_insn (int preserve
)
2780 prev_insn
.insn_mo
= &dummy_opcode
;
2781 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2782 prev_nop_frag
= NULL
;
2783 prev_nop_frag_holds
= 0;
2784 prev_nop_frag_required
= 0;
2785 prev_nop_frag_since
= 0;
2787 prev_insn_valid
= 0;
2788 prev_insn_is_delay_slot
= 0;
2789 prev_insn_unreordered
= 0;
2790 prev_insn_extended
= 0;
2791 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2792 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2793 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2794 prev_prev_insn_unreordered
= 0;
2795 mips_clear_insn_labels ();
2798 /* This function must be called whenever we turn on noreorder or emit
2799 something other than instructions. It inserts any NOPS which might
2800 be needed by the previous instruction, and clears the information
2801 kept for the previous instructions. The INSNS parameter is true if
2802 instructions are to follow. */
2805 mips_emit_delays (bfd_boolean insns
)
2807 if (! mips_opts
.noreorder
)
2812 if ((! mips_opts
.mips16
2813 && ((prev_insn
.insn_mo
->pinfo
2814 & (INSN_LOAD_COPROC_DELAY
2815 | INSN_COPROC_MOVE_DELAY
2816 | INSN_WRITE_COND_CODE
))
2817 && ! cop_interlocks
))
2818 || (! hilo_interlocks
2819 && (prev_insn
.insn_mo
->pinfo
2822 || (! mips_opts
.mips16
2823 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2824 && ! gpr_interlocks
)
2825 || (! mips_opts
.mips16
2826 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2827 && ! cop_mem_interlocks
))
2829 /* Itbl support may require additional care here. */
2831 if ((! mips_opts
.mips16
2832 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2833 && ! cop_interlocks
))
2834 || (! hilo_interlocks
2835 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2836 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2839 if (prev_insn_unreordered
)
2842 else if ((! mips_opts
.mips16
2843 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2844 && ! cop_interlocks
))
2845 || (! hilo_interlocks
2846 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2847 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2849 /* Itbl support may require additional care here. */
2850 if (! prev_prev_insn_unreordered
)
2854 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2857 const char *pn
= prev_insn
.insn_mo
->name
;
2858 if (strncmp (pn
, "macc", 4) == 0
2859 || strncmp (pn
, "dmacc", 5) == 0
2860 || strncmp (pn
, "dmult", 5) == 0
2861 || strstr (pn
, "div"))
2863 if (nops
< min_nops
)
2869 struct insn_label_list
*l
;
2873 /* Record the frag which holds the nop instructions, so
2874 that we can remove them if we don't need them. */
2875 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2876 prev_nop_frag
= frag_now
;
2877 prev_nop_frag_holds
= nops
;
2878 prev_nop_frag_required
= 0;
2879 prev_nop_frag_since
= 0;
2882 for (; nops
> 0; --nops
)
2887 /* Move on to a new frag, so that it is safe to simply
2888 decrease the size of prev_nop_frag. */
2889 frag_wane (frag_now
);
2893 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2897 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2898 symbol_set_frag (l
->label
, frag_now
);
2899 val
= (valueT
) frag_now_fix ();
2900 /* mips16 text labels are stored as odd. */
2901 if (mips_opts
.mips16
)
2903 S_SET_VALUE (l
->label
, val
);
2908 /* Mark instruction labels in mips16 mode. */
2910 mips16_mark_labels ();
2912 mips_no_prev_insn (insns
);
2915 /* Set up global variables for the start of a new macro. */
2920 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2921 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2922 && (prev_insn
.insn_mo
->pinfo
2923 & (INSN_UNCOND_BRANCH_DELAY
2924 | INSN_COND_BRANCH_DELAY
2925 | INSN_COND_BRANCH_LIKELY
)) != 0);
2928 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2929 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2930 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2933 macro_warning (relax_substateT subtype
)
2935 if (subtype
& RELAX_DELAY_SLOT
)
2936 return _("Macro instruction expanded into multiple instructions"
2937 " in a branch delay slot");
2938 else if (subtype
& RELAX_NOMACRO
)
2939 return _("Macro instruction expanded into multiple instructions");
2944 /* Finish up a macro. Emit warnings as appropriate. */
2949 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2951 relax_substateT subtype
;
2953 /* Set up the relaxation warning flags. */
2955 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2956 subtype
|= RELAX_SECOND_LONGER
;
2957 if (mips_opts
.warn_about_macros
)
2958 subtype
|= RELAX_NOMACRO
;
2959 if (mips_macro_warning
.delay_slot_p
)
2960 subtype
|= RELAX_DELAY_SLOT
;
2962 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2964 /* Either the macro has a single implementation or both
2965 implementations are longer than 4 bytes. Emit the
2967 const char *msg
= macro_warning (subtype
);
2973 /* One implementation might need a warning but the other
2974 definitely doesn't. */
2975 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2980 /* Read a macro's relocation codes from *ARGS and store them in *R.
2981 The first argument in *ARGS will be either the code for a single
2982 relocation or -1 followed by the three codes that make up a
2983 composite relocation. */
2986 macro_read_relocs (va_list *args
, bfd_reloc_code_real_type
*r
)
2990 next
= va_arg (*args
, int);
2992 r
[0] = (bfd_reloc_code_real_type
) next
;
2994 for (i
= 0; i
< 3; i
++)
2995 r
[i
] = (bfd_reloc_code_real_type
) va_arg (*args
, int);
2998 /* Build an instruction created by a macro expansion. This is passed
2999 a pointer to the count of instructions created so far, an
3000 expression, the name of the instruction to build, an operand format
3001 string, and corresponding arguments. */
3004 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
3006 struct mips_cl_insn insn
;
3007 bfd_reloc_code_real_type r
[3];
3010 va_start (args
, fmt
);
3012 if (mips_opts
.mips16
)
3014 mips16_macro_build (ep
, name
, fmt
, args
);
3019 r
[0] = BFD_RELOC_UNUSED
;
3020 r
[1] = BFD_RELOC_UNUSED
;
3021 r
[2] = BFD_RELOC_UNUSED
;
3022 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3023 assert (insn
.insn_mo
);
3024 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3026 /* Search until we get a match for NAME. */
3029 /* It is assumed here that macros will never generate
3030 MDMX or MIPS-3D instructions. */
3031 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
3032 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3033 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3035 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3037 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3041 assert (insn
.insn_mo
->name
);
3042 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3045 insn
.insn_opcode
= insn
.insn_mo
->match
;
3063 insn
.insn_opcode
|= (va_arg (args
, int)
3064 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3069 /* Note that in the macro case, these arguments are already
3070 in MSB form. (When handling the instruction in the
3071 non-macro case, these arguments are sizes from which
3072 MSB values must be calculated.) */
3073 insn
.insn_opcode
|= (va_arg (args
, int)
3074 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3080 /* Note that in the macro case, these arguments are already
3081 in MSBD form. (When handling the instruction in the
3082 non-macro case, these arguments are sizes from which
3083 MSBD values must be calculated.) */
3084 insn
.insn_opcode
|= (va_arg (args
, int)
3085 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3096 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3100 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3105 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3111 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3116 int tmp
= va_arg (args
, int);
3118 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3119 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3125 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3132 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3136 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3140 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3144 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3148 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3155 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3161 macro_read_relocs (&args
, r
);
3162 assert (*r
== BFD_RELOC_GPREL16
3163 || *r
== BFD_RELOC_MIPS_LITERAL
3164 || *r
== BFD_RELOC_MIPS_HIGHER
3165 || *r
== BFD_RELOC_HI16_S
3166 || *r
== BFD_RELOC_LO16
3167 || *r
== BFD_RELOC_MIPS_GOT16
3168 || *r
== BFD_RELOC_MIPS_CALL16
3169 || *r
== BFD_RELOC_MIPS_GOT_DISP
3170 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3171 || *r
== BFD_RELOC_MIPS_GOT_OFST
3172 || *r
== BFD_RELOC_MIPS_GOT_LO16
3173 || *r
== BFD_RELOC_MIPS_CALL_LO16
);
3177 macro_read_relocs (&args
, r
);
3179 && (ep
->X_op
== O_constant
3180 || (ep
->X_op
== O_symbol
3181 && (*r
== BFD_RELOC_MIPS_HIGHEST
3182 || *r
== BFD_RELOC_HI16_S
3183 || *r
== BFD_RELOC_HI16
3184 || *r
== BFD_RELOC_GPREL16
3185 || *r
== BFD_RELOC_MIPS_GOT_HI16
3186 || *r
== BFD_RELOC_MIPS_CALL_HI16
))));
3190 assert (ep
!= NULL
);
3192 * This allows macro() to pass an immediate expression for
3193 * creating short branches without creating a symbol.
3194 * Note that the expression still might come from the assembly
3195 * input, in which case the value is not checked for range nor
3196 * is a relocation entry generated (yuck).
3198 if (ep
->X_op
== O_constant
)
3200 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3204 *r
= BFD_RELOC_16_PCREL_S2
;
3208 assert (ep
!= NULL
);
3209 *r
= BFD_RELOC_MIPS_JMP
;
3213 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3222 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3224 append_insn (&insn
, ep
, r
);
3228 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3231 struct mips_cl_insn insn
;
3232 bfd_reloc_code_real_type r
[3]
3233 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3235 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3236 assert (insn
.insn_mo
);
3237 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3239 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3240 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3243 assert (insn
.insn_mo
->name
);
3244 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3247 insn
.insn_opcode
= insn
.insn_mo
->match
;
3248 insn
.use_extend
= FALSE
;
3267 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3272 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3276 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3280 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3290 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3297 regno
= va_arg (args
, int);
3298 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3299 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3320 assert (ep
!= NULL
);
3322 if (ep
->X_op
!= O_constant
)
3323 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3326 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3327 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3330 *r
= BFD_RELOC_UNUSED
;
3336 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3343 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3345 append_insn (&insn
, ep
, r
);
3349 * Generate a "jalr" instruction with a relocation hint to the called
3350 * function. This occurs in NewABI PIC code.
3353 macro_build_jalr (expressionS
*ep
)
3362 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3364 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3365 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3369 * Generate a "lui" instruction.
3372 macro_build_lui (expressionS
*ep
, int regnum
)
3374 expressionS high_expr
;
3375 struct mips_cl_insn insn
;
3376 bfd_reloc_code_real_type r
[3]
3377 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3378 const char *name
= "lui";
3379 const char *fmt
= "t,u";
3381 assert (! mips_opts
.mips16
);
3385 if (high_expr
.X_op
== O_constant
)
3387 /* we can compute the instruction now without a relocation entry */
3388 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3390 *r
= BFD_RELOC_UNUSED
;
3394 assert (ep
->X_op
== O_symbol
);
3395 /* _gp_disp is a special case, used from s_cpload. _gp is used
3396 if mips_no_shared. */
3397 assert (mips_pic
== NO_PIC
3399 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0)
3400 || (! mips_in_shared
3401 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp") == 0));
3402 *r
= BFD_RELOC_HI16_S
;
3405 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3406 assert (insn
.insn_mo
);
3407 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3408 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3410 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3411 if (*r
== BFD_RELOC_UNUSED
)
3413 insn
.insn_opcode
|= high_expr
.X_add_number
;
3414 append_insn (&insn
, NULL
, r
);
3417 append_insn (&insn
, &high_expr
, r
);
3420 /* Generate a sequence of instructions to do a load or store from a constant
3421 offset off of a base register (breg) into/from a target register (treg),
3422 using AT if necessary. */
3424 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3425 int treg
, int breg
, int dbl
)
3427 assert (ep
->X_op
== O_constant
);
3429 /* Sign-extending 32-bit constants makes their handling easier. */
3430 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3431 == ~((bfd_vma
) 0x7fffffff)))
3433 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3434 as_bad (_("constant too large"));
3436 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3440 /* Right now, this routine can only handle signed 32-bit constants. */
3441 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3442 as_warn (_("operand overflow"));
3444 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3446 /* Signed 16-bit offset will fit in the op. Easy! */
3447 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3451 /* 32-bit offset, need multiple instructions and AT, like:
3452 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3453 addu $tempreg,$tempreg,$breg
3454 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3455 to handle the complete offset. */
3456 macro_build_lui (ep
, AT
);
3457 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3458 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3461 as_warn (_("Macro used $at after \".set noat\""));
3466 * Generates code to set the $at register to true (one)
3467 * if reg is less than the immediate expression.
3470 set_at (int reg
, int unsignedp
)
3472 if (imm_expr
.X_op
== O_constant
3473 && imm_expr
.X_add_number
>= -0x8000
3474 && imm_expr
.X_add_number
< 0x8000)
3475 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3476 AT
, reg
, BFD_RELOC_LO16
);
3479 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3480 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3485 normalize_constant_expr (expressionS
*ex
)
3487 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3488 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3492 /* Warn if an expression is not a constant. */
3495 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3497 if (ex
->X_op
== O_big
)
3498 as_bad (_("unsupported large constant"));
3499 else if (ex
->X_op
!= O_constant
)
3500 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3502 normalize_constant_expr (ex
);
3505 /* Count the leading zeroes by performing a binary chop. This is a
3506 bulky bit of source, but performance is a LOT better for the
3507 majority of values than a simple loop to count the bits:
3508 for (lcnt = 0; (lcnt < 32); lcnt++)
3509 if ((v) & (1 << (31 - lcnt)))
3511 However it is not code size friendly, and the gain will drop a bit
3512 on certain cached systems.
3514 #define COUNT_TOP_ZEROES(v) \
3515 (((v) & ~0xffff) == 0 \
3516 ? ((v) & ~0xff) == 0 \
3517 ? ((v) & ~0xf) == 0 \
3518 ? ((v) & ~0x3) == 0 \
3519 ? ((v) & ~0x1) == 0 \
3524 : ((v) & ~0x7) == 0 \
3527 : ((v) & ~0x3f) == 0 \
3528 ? ((v) & ~0x1f) == 0 \
3531 : ((v) & ~0x7f) == 0 \
3534 : ((v) & ~0xfff) == 0 \
3535 ? ((v) & ~0x3ff) == 0 \
3536 ? ((v) & ~0x1ff) == 0 \
3539 : ((v) & ~0x7ff) == 0 \
3542 : ((v) & ~0x3fff) == 0 \
3543 ? ((v) & ~0x1fff) == 0 \
3546 : ((v) & ~0x7fff) == 0 \
3549 : ((v) & ~0xffffff) == 0 \
3550 ? ((v) & ~0xfffff) == 0 \
3551 ? ((v) & ~0x3ffff) == 0 \
3552 ? ((v) & ~0x1ffff) == 0 \
3555 : ((v) & ~0x7ffff) == 0 \
3558 : ((v) & ~0x3fffff) == 0 \
3559 ? ((v) & ~0x1fffff) == 0 \
3562 : ((v) & ~0x7fffff) == 0 \
3565 : ((v) & ~0xfffffff) == 0 \
3566 ? ((v) & ~0x3ffffff) == 0 \
3567 ? ((v) & ~0x1ffffff) == 0 \
3570 : ((v) & ~0x7ffffff) == 0 \
3573 : ((v) & ~0x3fffffff) == 0 \
3574 ? ((v) & ~0x1fffffff) == 0 \
3577 : ((v) & ~0x7fffffff) == 0 \
3582 * This routine generates the least number of instructions necessary to load
3583 * an absolute expression value into a register.
3586 load_register (int reg
, expressionS
*ep
, int dbl
)
3589 expressionS hi32
, lo32
;
3591 if (ep
->X_op
!= O_big
)
3593 assert (ep
->X_op
== O_constant
);
3595 /* Sign-extending 32-bit constants makes their handling easier. */
3596 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3597 == ~((bfd_vma
) 0x7fffffff)))
3599 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3600 as_bad (_("constant too large"));
3602 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3606 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3608 /* We can handle 16 bit signed values with an addiu to
3609 $zero. No need to ever use daddiu here, since $zero and
3610 the result are always correct in 32 bit mode. */
3611 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3614 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3616 /* We can handle 16 bit unsigned values with an ori to
3618 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3621 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3623 /* 32 bit values require an lui. */
3624 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3625 if ((ep
->X_add_number
& 0xffff) != 0)
3626 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3631 /* The value is larger than 32 bits. */
3633 if (HAVE_32BIT_GPRS
)
3635 as_bad (_("Number (0x%lx) larger than 32 bits"),
3636 (unsigned long) ep
->X_add_number
);
3637 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3641 if (ep
->X_op
!= O_big
)
3644 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3645 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3646 hi32
.X_add_number
&= 0xffffffff;
3648 lo32
.X_add_number
&= 0xffffffff;
3652 assert (ep
->X_add_number
> 2);
3653 if (ep
->X_add_number
== 3)
3654 generic_bignum
[3] = 0;
3655 else if (ep
->X_add_number
> 4)
3656 as_bad (_("Number larger than 64 bits"));
3657 lo32
.X_op
= O_constant
;
3658 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3659 hi32
.X_op
= O_constant
;
3660 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3663 if (hi32
.X_add_number
== 0)
3668 unsigned long hi
, lo
;
3670 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3672 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3674 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3677 if (lo32
.X_add_number
& 0x80000000)
3679 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3680 if (lo32
.X_add_number
& 0xffff)
3681 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3686 /* Check for 16bit shifted constant. We know that hi32 is
3687 non-zero, so start the mask on the first bit of the hi32
3692 unsigned long himask
, lomask
;
3696 himask
= 0xffff >> (32 - shift
);
3697 lomask
= (0xffff << shift
) & 0xffffffff;
3701 himask
= 0xffff << (shift
- 32);
3704 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3705 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3709 tmp
.X_op
= O_constant
;
3711 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3712 | (lo32
.X_add_number
>> shift
));
3714 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3715 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3716 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3717 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3722 while (shift
<= (64 - 16));
3724 /* Find the bit number of the lowest one bit, and store the
3725 shifted value in hi/lo. */
3726 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3727 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3731 while ((lo
& 1) == 0)
3736 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3742 while ((hi
& 1) == 0)
3751 /* Optimize if the shifted value is a (power of 2) - 1. */
3752 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3753 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3755 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3760 /* This instruction will set the register to be all
3762 tmp
.X_op
= O_constant
;
3763 tmp
.X_add_number
= (offsetT
) -1;
3764 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3768 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3769 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3771 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3772 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3777 /* Sign extend hi32 before calling load_register, because we can
3778 generally get better code when we load a sign extended value. */
3779 if ((hi32
.X_add_number
& 0x80000000) != 0)
3780 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3781 load_register (reg
, &hi32
, 0);
3784 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3788 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3796 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3798 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3799 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3805 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3809 mid16
.X_add_number
>>= 16;
3810 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3811 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3814 if ((lo32
.X_add_number
& 0xffff) != 0)
3815 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3819 load_delay_nop (void)
3821 if (!gpr_interlocks
)
3822 macro_build (NULL
, "nop", "");
3825 /* Load an address into a register. */
3828 load_address (int reg
, expressionS
*ep
, int *used_at
)
3830 if (ep
->X_op
!= O_constant
3831 && ep
->X_op
!= O_symbol
)
3833 as_bad (_("expression too complex"));
3834 ep
->X_op
= O_constant
;
3837 if (ep
->X_op
== O_constant
)
3839 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3843 if (mips_pic
== NO_PIC
)
3845 /* If this is a reference to a GP relative symbol, we want
3846 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3848 lui $reg,<sym> (BFD_RELOC_HI16_S)
3849 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3850 If we have an addend, we always use the latter form.
3852 With 64bit address space and a usable $at we want
3853 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3854 lui $at,<sym> (BFD_RELOC_HI16_S)
3855 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3856 daddiu $at,<sym> (BFD_RELOC_LO16)
3860 If $at is already in use, we use a path which is suboptimal
3861 on superscalar processors.
3862 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3863 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3865 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3867 daddiu $reg,<sym> (BFD_RELOC_LO16)
3869 if (HAVE_64BIT_ADDRESSES
)
3871 /* ??? We don't provide a GP-relative alternative for these macros.
3872 It used not to be possible with the original relaxation code,
3873 but it could be done now. */
3875 if (*used_at
== 0 && ! mips_opts
.noat
)
3877 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3878 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3879 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3880 BFD_RELOC_MIPS_HIGHER
);
3881 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3882 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3883 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3888 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3889 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3890 BFD_RELOC_MIPS_HIGHER
);
3891 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3892 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3893 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3894 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3899 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3900 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3902 relax_start (ep
->X_add_symbol
);
3903 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3904 mips_gp_register
, BFD_RELOC_GPREL16
);
3907 macro_build_lui (ep
, reg
);
3908 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3909 reg
, reg
, BFD_RELOC_LO16
);
3910 if (mips_relax
.sequence
)
3914 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3918 /* If this is a reference to an external symbol, we want
3919 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3921 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3923 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3924 If there is a constant, it must be added in after.
3926 If we have NewABI, we want
3927 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3928 unless we're referencing a global symbol with a non-zero
3929 offset, in which case cst must be added separately. */
3932 if (ep
->X_add_number
)
3934 ex
.X_add_number
= ep
->X_add_number
;
3935 ep
->X_add_number
= 0;
3936 relax_start (ep
->X_add_symbol
);
3937 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3938 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3939 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3940 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3941 ex
.X_op
= O_constant
;
3942 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3943 reg
, reg
, BFD_RELOC_LO16
);
3944 ep
->X_add_number
= ex
.X_add_number
;
3947 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3948 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3949 if (mips_relax
.sequence
)
3954 ex
.X_add_number
= ep
->X_add_number
;
3955 ep
->X_add_number
= 0;
3956 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3957 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3959 relax_start (ep
->X_add_symbol
);
3961 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3965 if (ex
.X_add_number
!= 0)
3967 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3968 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3969 ex
.X_op
= O_constant
;
3970 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3971 reg
, reg
, BFD_RELOC_LO16
);
3975 else if (mips_pic
== SVR4_PIC
)
3979 /* This is the large GOT case. If this is a reference to an
3980 external symbol, we want
3981 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3983 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3985 Otherwise, for a reference to a local symbol in old ABI, we want
3986 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3988 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3989 If there is a constant, it must be added in after.
3991 In the NewABI, for local symbols, with or without offsets, we want:
3992 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3993 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3997 ex
.X_add_number
= ep
->X_add_number
;
3998 ep
->X_add_number
= 0;
3999 relax_start (ep
->X_add_symbol
);
4000 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4001 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4002 reg
, reg
, mips_gp_register
);
4003 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4004 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4005 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4006 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4007 else if (ex
.X_add_number
)
4009 ex
.X_op
= O_constant
;
4010 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4014 ep
->X_add_number
= ex
.X_add_number
;
4016 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4017 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
4018 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4019 BFD_RELOC_MIPS_GOT_OFST
);
4024 ex
.X_add_number
= ep
->X_add_number
;
4025 ep
->X_add_number
= 0;
4026 relax_start (ep
->X_add_symbol
);
4027 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
4028 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
4029 reg
, reg
, mips_gp_register
);
4030 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
4031 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
4033 if (reg_needs_delay (mips_gp_register
))
4035 /* We need a nop before loading from $gp. This special
4036 check is required because the lui which starts the main
4037 instruction stream does not refer to $gp, and so will not
4038 insert the nop which may be required. */
4039 macro_build (NULL
, "nop", "");
4041 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4042 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4044 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4048 if (ex
.X_add_number
!= 0)
4050 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4051 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4052 ex
.X_op
= O_constant
;
4053 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4062 /* Move the contents of register SOURCE into register DEST. */
4065 move_register (int dest
, int source
)
4067 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4071 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4072 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4073 The two alternatives are:
4075 Global symbol Local sybmol
4076 ------------- ------------
4077 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4079 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4081 load_got_offset emits the first instruction and add_got_offset
4082 emits the second for a 16-bit offset or add_got_offset_hilo emits
4083 a sequence to add a 32-bit offset using a scratch register. */
4086 load_got_offset (int dest
, expressionS
*local
)
4091 global
.X_add_number
= 0;
4093 relax_start (local
->X_add_symbol
);
4094 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4095 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4097 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4098 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4103 add_got_offset (int dest
, expressionS
*local
)
4107 global
.X_op
= O_constant
;
4108 global
.X_op_symbol
= NULL
;
4109 global
.X_add_symbol
= NULL
;
4110 global
.X_add_number
= local
->X_add_number
;
4112 relax_start (local
->X_add_symbol
);
4113 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4114 dest
, dest
, BFD_RELOC_LO16
);
4116 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4121 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4124 int hold_mips_optimize
;
4126 global
.X_op
= O_constant
;
4127 global
.X_op_symbol
= NULL
;
4128 global
.X_add_symbol
= NULL
;
4129 global
.X_add_number
= local
->X_add_number
;
4131 relax_start (local
->X_add_symbol
);
4132 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4134 /* Set mips_optimize around the lui instruction to avoid
4135 inserting an unnecessary nop after the lw. */
4136 hold_mips_optimize
= mips_optimize
;
4138 macro_build_lui (&global
, tmp
);
4139 mips_optimize
= hold_mips_optimize
;
4140 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4143 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4148 * This routine implements the seemingly endless macro or synthesized
4149 * instructions and addressing modes in the mips assembly language. Many
4150 * of these macros are simple and are similar to each other. These could
4151 * probably be handled by some kind of table or grammar approach instead of
4152 * this verbose method. Others are not simple macros but are more like
4153 * optimizing code generation.
4154 * One interesting optimization is when several store macros appear
4155 * consecutively that would load AT with the upper half of the same address.
4156 * The ensuing load upper instructions are ommited. This implies some kind
4157 * of global optimization. We currently only optimize within a single macro.
4158 * For many of the load and store macros if the address is specified as a
4159 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4160 * first load register 'at' with zero and use it as the base register. The
4161 * mips assembler simply uses register $zero. Just one tiny optimization
4165 macro (struct mips_cl_insn
*ip
)
4167 register int treg
, sreg
, dreg
, breg
;
4183 bfd_reloc_code_real_type r
;
4184 int hold_mips_optimize
;
4186 assert (! mips_opts
.mips16
);
4188 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4189 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4190 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4191 mask
= ip
->insn_mo
->mask
;
4193 expr1
.X_op
= O_constant
;
4194 expr1
.X_op_symbol
= NULL
;
4195 expr1
.X_add_symbol
= NULL
;
4196 expr1
.X_add_number
= 1;
4208 mips_emit_delays (TRUE
);
4209 ++mips_opts
.noreorder
;
4210 mips_any_noreorder
= 1;
4212 expr1
.X_add_number
= 8;
4213 macro_build (&expr1
, "bgez", "s,p", sreg
);
4215 macro_build (NULL
, "nop", "", 0);
4217 move_register (dreg
, sreg
);
4218 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4220 --mips_opts
.noreorder
;
4241 if (imm_expr
.X_op
== O_constant
4242 && imm_expr
.X_add_number
>= -0x8000
4243 && imm_expr
.X_add_number
< 0x8000)
4245 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4248 load_register (AT
, &imm_expr
, dbl
);
4249 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4268 if (imm_expr
.X_op
== O_constant
4269 && imm_expr
.X_add_number
>= 0
4270 && imm_expr
.X_add_number
< 0x10000)
4272 if (mask
!= M_NOR_I
)
4273 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4276 macro_build (&imm_expr
, "ori", "t,r,i",
4277 treg
, sreg
, BFD_RELOC_LO16
);
4278 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4283 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4284 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4301 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4303 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4306 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4307 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4315 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4320 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4323 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4324 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4330 /* check for > max integer */
4331 maxnum
= 0x7fffffff;
4332 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4339 if (imm_expr
.X_op
== O_constant
4340 && imm_expr
.X_add_number
>= maxnum
4341 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4344 /* result is always false */
4346 macro_build (NULL
, "nop", "", 0);
4348 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4351 if (imm_expr
.X_op
!= O_constant
)
4352 as_bad (_("Unsupported large constant"));
4353 ++imm_expr
.X_add_number
;
4357 if (mask
== M_BGEL_I
)
4359 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4361 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4364 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4366 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4369 maxnum
= 0x7fffffff;
4370 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4377 maxnum
= - maxnum
- 1;
4378 if (imm_expr
.X_op
== O_constant
4379 && imm_expr
.X_add_number
<= maxnum
4380 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4383 /* result is always true */
4384 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4385 macro_build (&offset_expr
, "b", "p");
4389 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4399 macro_build (&offset_expr
, likely
? "beql" : "beq",
4403 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4404 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4412 && imm_expr
.X_op
== O_constant
4413 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4415 if (imm_expr
.X_op
!= O_constant
)
4416 as_bad (_("Unsupported large constant"));
4417 ++imm_expr
.X_add_number
;
4421 if (mask
== M_BGEUL_I
)
4423 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4425 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4427 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4432 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4440 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4445 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4448 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4449 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4457 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4463 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4464 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4472 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4477 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4480 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4481 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4487 maxnum
= 0x7fffffff;
4488 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4495 if (imm_expr
.X_op
== O_constant
4496 && imm_expr
.X_add_number
>= maxnum
4497 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4499 if (imm_expr
.X_op
!= O_constant
)
4500 as_bad (_("Unsupported large constant"));
4501 ++imm_expr
.X_add_number
;
4505 if (mask
== M_BLTL_I
)
4507 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4509 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4512 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4514 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4518 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4526 macro_build (&offset_expr
, likely
? "beql" : "beq",
4532 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4533 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4541 && imm_expr
.X_op
== O_constant
4542 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4544 if (imm_expr
.X_op
!= O_constant
)
4545 as_bad (_("Unsupported large constant"));
4546 ++imm_expr
.X_add_number
;
4550 if (mask
== M_BLTUL_I
)
4552 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4554 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4556 macro_build (&offset_expr
, likely
? "beql" : "beq",
4561 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4569 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4574 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4577 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4578 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4588 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4592 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4593 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4601 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4603 as_bad (_("Unsupported large constant"));
4608 pos
= (unsigned long) imm_expr
.X_add_number
;
4609 size
= (unsigned long) imm2_expr
.X_add_number
;
4614 as_bad (_("Improper position (%lu)"), pos
);
4617 if (size
== 0 || size
> 64
4618 || (pos
+ size
- 1) > 63)
4620 as_bad (_("Improper extract size (%lu, position %lu)"),
4625 if (size
<= 32 && pos
< 32)
4630 else if (size
<= 32)
4640 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4649 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4651 as_bad (_("Unsupported large constant"));
4656 pos
= (unsigned long) imm_expr
.X_add_number
;
4657 size
= (unsigned long) imm2_expr
.X_add_number
;
4662 as_bad (_("Improper position (%lu)"), pos
);
4665 if (size
== 0 || size
> 64
4666 || (pos
+ size
- 1) > 63)
4668 as_bad (_("Improper insert size (%lu, position %lu)"),
4673 if (pos
< 32 && (pos
+ size
- 1) < 32)
4688 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4705 as_warn (_("Divide by zero."));
4707 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4709 macro_build (NULL
, "break", "c", 7);
4713 mips_emit_delays (TRUE
);
4714 ++mips_opts
.noreorder
;
4715 mips_any_noreorder
= 1;
4718 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4719 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4723 expr1
.X_add_number
= 8;
4724 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4725 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4726 macro_build (NULL
, "break", "c", 7);
4728 expr1
.X_add_number
= -1;
4729 load_register (AT
, &expr1
, dbl
);
4730 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4731 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4734 expr1
.X_add_number
= 1;
4735 load_register (AT
, &expr1
, dbl
);
4736 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4740 expr1
.X_add_number
= 0x80000000;
4741 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4745 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4746 /* We want to close the noreorder block as soon as possible, so
4747 that later insns are available for delay slot filling. */
4748 --mips_opts
.noreorder
;
4752 expr1
.X_add_number
= 8;
4753 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4754 macro_build (NULL
, "nop", "", 0);
4756 /* We want to close the noreorder block as soon as possible, so
4757 that later insns are available for delay slot filling. */
4758 --mips_opts
.noreorder
;
4760 macro_build (NULL
, "break", "c", 6);
4762 macro_build (NULL
, s
, "d", dreg
);
4801 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4803 as_warn (_("Divide by zero."));
4805 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4807 macro_build (NULL
, "break", "c", 7);
4810 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4812 if (strcmp (s2
, "mflo") == 0)
4813 move_register (dreg
, sreg
);
4815 move_register (dreg
, 0);
4818 if (imm_expr
.X_op
== O_constant
4819 && imm_expr
.X_add_number
== -1
4820 && s
[strlen (s
) - 1] != 'u')
4822 if (strcmp (s2
, "mflo") == 0)
4824 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4827 move_register (dreg
, 0);
4831 load_register (AT
, &imm_expr
, dbl
);
4832 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4833 macro_build (NULL
, s2
, "d", dreg
);
4852 mips_emit_delays (TRUE
);
4853 ++mips_opts
.noreorder
;
4854 mips_any_noreorder
= 1;
4857 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4858 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4859 /* We want to close the noreorder block as soon as possible, so
4860 that later insns are available for delay slot filling. */
4861 --mips_opts
.noreorder
;
4865 expr1
.X_add_number
= 8;
4866 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4867 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4869 /* We want to close the noreorder block as soon as possible, so
4870 that later insns are available for delay slot filling. */
4871 --mips_opts
.noreorder
;
4872 macro_build (NULL
, "break", "c", 7);
4874 macro_build (NULL
, s2
, "d", dreg
);
4886 /* Load the address of a symbol into a register. If breg is not
4887 zero, we then add a base register to it. */
4889 if (dbl
&& HAVE_32BIT_GPRS
)
4890 as_warn (_("dla used to load 32-bit register"));
4892 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4893 as_warn (_("la used to load 64-bit address"));
4895 if (offset_expr
.X_op
== O_constant
4896 && offset_expr
.X_add_number
>= -0x8000
4897 && offset_expr
.X_add_number
< 0x8000)
4899 macro_build (&offset_expr
,
4900 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4901 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4916 if (offset_expr
.X_op
!= O_symbol
4917 && offset_expr
.X_op
!= O_constant
)
4919 as_bad (_("expression too complex"));
4920 offset_expr
.X_op
= O_constant
;
4923 if (offset_expr
.X_op
== O_constant
)
4924 load_register (tempreg
, &offset_expr
,
4926 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4927 : HAVE_64BIT_ADDRESSES
));
4928 else if (mips_pic
== NO_PIC
)
4930 /* If this is a reference to a GP relative symbol, we want
4931 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4933 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4934 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4935 If we have a constant, we need two instructions anyhow,
4936 so we may as well always use the latter form.
4938 With 64bit address space and a usable $at we want
4939 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4940 lui $at,<sym> (BFD_RELOC_HI16_S)
4941 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4942 daddiu $at,<sym> (BFD_RELOC_LO16)
4944 daddu $tempreg,$tempreg,$at
4946 If $at is already in use, we use a path which is suboptimal
4947 on superscalar processors.
4948 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4949 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4951 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4953 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4955 if (HAVE_64BIT_ADDRESSES
)
4957 /* ??? We don't provide a GP-relative alternative for
4958 these macros. It used not to be possible with the
4959 original relaxation code, but it could be done now. */
4961 if (used_at
== 0 && ! mips_opts
.noat
)
4963 macro_build (&offset_expr
, "lui", "t,u",
4964 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4965 macro_build (&offset_expr
, "lui", "t,u",
4966 AT
, BFD_RELOC_HI16_S
);
4967 macro_build (&offset_expr
, "daddiu", "t,r,j",
4968 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4969 macro_build (&offset_expr
, "daddiu", "t,r,j",
4970 AT
, AT
, BFD_RELOC_LO16
);
4971 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4972 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4977 macro_build (&offset_expr
, "lui", "t,u",
4978 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4979 macro_build (&offset_expr
, "daddiu", "t,r,j",
4980 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4981 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4982 macro_build (&offset_expr
, "daddiu", "t,r,j",
4983 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4984 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4985 macro_build (&offset_expr
, "daddiu", "t,r,j",
4986 tempreg
, tempreg
, BFD_RELOC_LO16
);
4991 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
4992 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4994 relax_start (offset_expr
.X_add_symbol
);
4995 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
4996 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4999 if (!IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
))
5000 as_bad (_("offset too large"));
5001 macro_build_lui (&offset_expr
, tempreg
);
5002 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5003 tempreg
, tempreg
, BFD_RELOC_LO16
);
5004 if (mips_relax
.sequence
)
5008 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5010 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5012 /* If this is a reference to an external symbol, and there
5013 is no constant, we want
5014 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5015 or for lca or if tempreg is PIC_CALL_REG
5016 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5017 For a local symbol, we want
5018 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5020 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5022 If we have a small constant, and this is a reference to
5023 an external symbol, we want
5024 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5026 addiu $tempreg,$tempreg,<constant>
5027 For a local symbol, we want the same instruction
5028 sequence, but we output a BFD_RELOC_LO16 reloc on the
5031 If we have a large constant, and this is a reference to
5032 an external symbol, we want
5033 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5034 lui $at,<hiconstant>
5035 addiu $at,$at,<loconstant>
5036 addu $tempreg,$tempreg,$at
5037 For a local symbol, we want the same instruction
5038 sequence, but we output a BFD_RELOC_LO16 reloc on the
5042 if (offset_expr
.X_add_number
== 0)
5044 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5045 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5047 relax_start (offset_expr
.X_add_symbol
);
5048 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5049 lw_reloc_type
, mips_gp_register
);
5052 /* We're going to put in an addu instruction using
5053 tempreg, so we may as well insert the nop right
5058 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5059 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5061 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5062 tempreg
, tempreg
, BFD_RELOC_LO16
);
5064 /* FIXME: If breg == 0, and the next instruction uses
5065 $tempreg, then if this variant case is used an extra
5066 nop will be generated. */
5068 else if (offset_expr
.X_add_number
>= -0x8000
5069 && offset_expr
.X_add_number
< 0x8000)
5071 load_got_offset (tempreg
, &offset_expr
);
5073 add_got_offset (tempreg
, &offset_expr
);
5077 expr1
.X_add_number
= offset_expr
.X_add_number
;
5078 offset_expr
.X_add_number
=
5079 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5080 load_got_offset (tempreg
, &offset_expr
);
5081 offset_expr
.X_add_number
= expr1
.X_add_number
;
5082 /* If we are going to add in a base register, and the
5083 target register and the base register are the same,
5084 then we are using AT as a temporary register. Since
5085 we want to load the constant into AT, we add our
5086 current AT (from the global offset table) and the
5087 register into the register now, and pretend we were
5088 not using a base register. */
5092 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5097 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5101 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5103 int add_breg_early
= 0;
5105 /* If this is a reference to an external, and there is no
5106 constant, or local symbol (*), with or without a
5108 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5109 or for lca or if tempreg is PIC_CALL_REG
5110 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5112 If we have a small constant, and this is a reference to
5113 an external symbol, we want
5114 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5115 addiu $tempreg,$tempreg,<constant>
5117 If we have a large constant, and this is a reference to
5118 an external symbol, we want
5119 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5120 lui $at,<hiconstant>
5121 addiu $at,$at,<loconstant>
5122 addu $tempreg,$tempreg,$at
5124 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5125 local symbols, even though it introduces an additional
5128 if (offset_expr
.X_add_number
)
5130 expr1
.X_add_number
= offset_expr
.X_add_number
;
5131 offset_expr
.X_add_number
= 0;
5133 relax_start (offset_expr
.X_add_symbol
);
5134 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5135 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5137 if (expr1
.X_add_number
>= -0x8000
5138 && expr1
.X_add_number
< 0x8000)
5140 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5141 tempreg
, tempreg
, BFD_RELOC_LO16
);
5143 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5147 /* If we are going to add in a base register, and the
5148 target register and the base register are the same,
5149 then we are using AT as a temporary register. Since
5150 we want to load the constant into AT, we add our
5151 current AT (from the global offset table) and the
5152 register into the register now, and pretend we were
5153 not using a base register. */
5158 assert (tempreg
== AT
);
5159 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5165 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5166 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5172 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5175 offset_expr
.X_add_number
= expr1
.X_add_number
;
5177 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5178 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5181 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5182 treg
, tempreg
, breg
);
5188 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5190 relax_start (offset_expr
.X_add_symbol
);
5191 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5192 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5194 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5195 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5200 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5201 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5204 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5207 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5208 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5209 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5211 /* This is the large GOT case. If this is a reference to an
5212 external symbol, and there is no constant, we want
5213 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5214 addu $tempreg,$tempreg,$gp
5215 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5216 or for lca or if tempreg is PIC_CALL_REG
5217 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5218 addu $tempreg,$tempreg,$gp
5219 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5220 For a local symbol, we want
5221 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5223 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5225 If we have a small constant, and this is a reference to
5226 an external symbol, we want
5227 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5228 addu $tempreg,$tempreg,$gp
5229 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5231 addiu $tempreg,$tempreg,<constant>
5232 For a local symbol, we want
5233 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5235 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5237 If we have a large constant, and this is a reference to
5238 an external symbol, we want
5239 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5240 addu $tempreg,$tempreg,$gp
5241 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5242 lui $at,<hiconstant>
5243 addiu $at,$at,<loconstant>
5244 addu $tempreg,$tempreg,$at
5245 For a local symbol, we want
5246 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5247 lui $at,<hiconstant>
5248 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5249 addu $tempreg,$tempreg,$at
5252 expr1
.X_add_number
= offset_expr
.X_add_number
;
5253 offset_expr
.X_add_number
= 0;
5254 relax_start (offset_expr
.X_add_symbol
);
5255 gpdelay
= reg_needs_delay (mips_gp_register
);
5256 if (expr1
.X_add_number
== 0 && breg
== 0
5257 && (call
|| tempreg
== PIC_CALL_REG
))
5259 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5260 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5262 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5263 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5264 tempreg
, tempreg
, mips_gp_register
);
5265 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5266 tempreg
, lw_reloc_type
, tempreg
);
5267 if (expr1
.X_add_number
== 0)
5271 /* We're going to put in an addu instruction using
5272 tempreg, so we may as well insert the nop right
5277 else if (expr1
.X_add_number
>= -0x8000
5278 && expr1
.X_add_number
< 0x8000)
5281 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5282 tempreg
, tempreg
, BFD_RELOC_LO16
);
5288 /* If we are going to add in a base register, and the
5289 target register and the base register are the same,
5290 then we are using AT as a temporary register. Since
5291 we want to load the constant into AT, we add our
5292 current AT (from the global offset table) and the
5293 register into the register now, and pretend we were
5294 not using a base register. */
5299 assert (tempreg
== AT
);
5301 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5306 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5307 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5311 offset_expr
.X_add_number
=
5312 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5317 /* This is needed because this instruction uses $gp, but
5318 the first instruction on the main stream does not. */
5319 macro_build (NULL
, "nop", "");
5322 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5323 local_reloc_type
, mips_gp_register
);
5324 if (expr1
.X_add_number
>= -0x8000
5325 && expr1
.X_add_number
< 0x8000)
5328 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5329 tempreg
, tempreg
, BFD_RELOC_LO16
);
5330 /* FIXME: If add_number is 0, and there was no base
5331 register, the external symbol case ended with a load,
5332 so if the symbol turns out to not be external, and
5333 the next instruction uses tempreg, an unnecessary nop
5334 will be inserted. */
5340 /* We must add in the base register now, as in the
5341 external symbol case. */
5342 assert (tempreg
== AT
);
5344 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5347 /* We set breg to 0 because we have arranged to add
5348 it in in both cases. */
5352 macro_build_lui (&expr1
, AT
);
5353 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5354 AT
, AT
, BFD_RELOC_LO16
);
5355 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5356 tempreg
, tempreg
, AT
);
5360 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5362 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5363 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5364 int add_breg_early
= 0;
5366 /* This is the large GOT case. If this is a reference to an
5367 external symbol, and there is no constant, we want
5368 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5369 add $tempreg,$tempreg,$gp
5370 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5371 or for lca or if tempreg is PIC_CALL_REG
5372 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5373 add $tempreg,$tempreg,$gp
5374 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5376 If we have a small constant, and this is a reference to
5377 an external symbol, we want
5378 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5379 add $tempreg,$tempreg,$gp
5380 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5381 addi $tempreg,$tempreg,<constant>
5383 If we have a large constant, and this is a reference to
5384 an external symbol, we want
5385 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5386 addu $tempreg,$tempreg,$gp
5387 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5388 lui $at,<hiconstant>
5389 addi $at,$at,<loconstant>
5390 add $tempreg,$tempreg,$at
5392 If we have NewABI, and we know it's a local symbol, we want
5393 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5394 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5395 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5397 relax_start (offset_expr
.X_add_symbol
);
5399 expr1
.X_add_number
= offset_expr
.X_add_number
;
5400 offset_expr
.X_add_number
= 0;
5402 if (expr1
.X_add_number
== 0 && breg
== 0
5403 && (call
|| tempreg
== PIC_CALL_REG
))
5405 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5406 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5408 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5409 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5410 tempreg
, tempreg
, mips_gp_register
);
5411 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5412 tempreg
, lw_reloc_type
, tempreg
);
5414 if (expr1
.X_add_number
== 0)
5416 else if (expr1
.X_add_number
>= -0x8000
5417 && expr1
.X_add_number
< 0x8000)
5419 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5420 tempreg
, tempreg
, BFD_RELOC_LO16
);
5422 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5426 /* If we are going to add in a base register, and the
5427 target register and the base register are the same,
5428 then we are using AT as a temporary register. Since
5429 we want to load the constant into AT, we add our
5430 current AT (from the global offset table) and the
5431 register into the register now, and pretend we were
5432 not using a base register. */
5437 assert (tempreg
== AT
);
5438 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5444 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5445 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5450 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5453 offset_expr
.X_add_number
= expr1
.X_add_number
;
5454 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5455 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5456 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5457 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5460 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5461 treg
, tempreg
, breg
);
5474 if (mips_pic
== NO_PIC
)
5475 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5477 s
= ADDRESS_ADD_INSN
;
5479 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5488 /* The j instruction may not be used in PIC code, since it
5489 requires an absolute address. We convert it to a b
5491 if (mips_pic
== NO_PIC
)
5492 macro_build (&offset_expr
, "j", "a");
5494 macro_build (&offset_expr
, "b", "p");
5497 /* The jal instructions must be handled as macros because when
5498 generating PIC code they expand to multi-instruction
5499 sequences. Normally they are simple instructions. */
5504 if (mips_pic
== NO_PIC
)
5505 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5506 else if (mips_pic
== SVR4_PIC
)
5508 if (sreg
!= PIC_CALL_REG
)
5509 as_warn (_("MIPS PIC call to register other than $25"));
5511 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5514 if (mips_cprestore_offset
< 0)
5515 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5518 if (! mips_frame_reg_valid
)
5520 as_warn (_("No .frame pseudo-op used in PIC code"));
5521 /* Quiet this warning. */
5522 mips_frame_reg_valid
= 1;
5524 if (! mips_cprestore_valid
)
5526 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5527 /* Quiet this warning. */
5528 mips_cprestore_valid
= 1;
5530 expr1
.X_add_number
= mips_cprestore_offset
;
5531 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5534 HAVE_64BIT_ADDRESSES
);
5544 if (mips_pic
== NO_PIC
)
5545 macro_build (&offset_expr
, "jal", "a");
5546 else if (mips_pic
== SVR4_PIC
)
5548 /* If this is a reference to an external symbol, and we are
5549 using a small GOT, we want
5550 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5554 lw $gp,cprestore($sp)
5555 The cprestore value is set using the .cprestore
5556 pseudo-op. If we are using a big GOT, we want
5557 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5559 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5563 lw $gp,cprestore($sp)
5564 If the symbol is not external, we want
5565 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5567 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5570 lw $gp,cprestore($sp)
5572 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5573 sequences above, minus nops, unless the symbol is local,
5574 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5580 relax_start (offset_expr
.X_add_symbol
);
5581 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5582 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5585 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5586 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5592 relax_start (offset_expr
.X_add_symbol
);
5593 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5594 BFD_RELOC_MIPS_CALL_HI16
);
5595 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5596 PIC_CALL_REG
, mips_gp_register
);
5597 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5598 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5601 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5602 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5604 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5605 PIC_CALL_REG
, PIC_CALL_REG
,
5606 BFD_RELOC_MIPS_GOT_OFST
);
5610 macro_build_jalr (&offset_expr
);
5614 relax_start (offset_expr
.X_add_symbol
);
5617 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5618 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5627 gpdelay
= reg_needs_delay (mips_gp_register
);
5628 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5629 BFD_RELOC_MIPS_CALL_HI16
);
5630 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5631 PIC_CALL_REG
, mips_gp_register
);
5632 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5633 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5638 macro_build (NULL
, "nop", "");
5640 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5641 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5644 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5645 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5647 macro_build_jalr (&offset_expr
);
5649 if (mips_cprestore_offset
< 0)
5650 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5653 if (! mips_frame_reg_valid
)
5655 as_warn (_("No .frame pseudo-op used in PIC code"));
5656 /* Quiet this warning. */
5657 mips_frame_reg_valid
= 1;
5659 if (! mips_cprestore_valid
)
5661 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5662 /* Quiet this warning. */
5663 mips_cprestore_valid
= 1;
5665 if (mips_opts
.noreorder
)
5666 macro_build (NULL
, "nop", "");
5667 expr1
.X_add_number
= mips_cprestore_offset
;
5668 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5671 HAVE_64BIT_ADDRESSES
);
5697 /* Itbl support may require additional care here. */
5702 /* Itbl support may require additional care here. */
5707 /* Itbl support may require additional care here. */
5712 /* Itbl support may require additional care here. */
5724 if (mips_opts
.arch
== CPU_R4650
)
5726 as_bad (_("opcode not supported on this processor"));
5730 /* Itbl support may require additional care here. */
5735 /* Itbl support may require additional care here. */
5740 /* Itbl support may require additional care here. */
5760 if (breg
== treg
|| coproc
|| lr
)
5782 /* Itbl support may require additional care here. */
5787 /* Itbl support may require additional care here. */
5792 /* Itbl support may require additional care here. */
5797 /* Itbl support may require additional care here. */
5813 if (mips_opts
.arch
== CPU_R4650
)
5815 as_bad (_("opcode not supported on this processor"));
5820 /* Itbl support may require additional care here. */
5824 /* Itbl support may require additional care here. */
5829 /* Itbl support may require additional care here. */
5841 /* Itbl support may require additional care here. */
5842 if (mask
== M_LWC1_AB
5843 || mask
== M_SWC1_AB
5844 || mask
== M_LDC1_AB
5845 || mask
== M_SDC1_AB
5854 /* Sign-extending 32-bit constants makes their handling easier.
5855 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5857 if ((! HAVE_64BIT_ADDRESSES
5858 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5859 && (offset_expr
.X_op
== O_constant
)
5860 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5861 == ~((bfd_vma
) 0x7fffffff)))
5863 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5864 as_bad (_("constant too large"));
5866 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5867 ^ 0x80000000) - 0x80000000);
5870 if (offset_expr
.X_op
!= O_constant
5871 && offset_expr
.X_op
!= O_symbol
)
5873 as_bad (_("expression too complex"));
5874 offset_expr
.X_op
= O_constant
;
5877 /* A constant expression in PIC code can be handled just as it
5878 is in non PIC code. */
5879 if (mips_pic
== NO_PIC
5880 || offset_expr
.X_op
== O_constant
)
5882 /* If this is a reference to a GP relative symbol, and there
5883 is no base register, we want
5884 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5885 Otherwise, if there is no base register, we want
5886 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5887 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5888 If we have a constant, we need two instructions anyhow,
5889 so we always use the latter form.
5891 If we have a base register, and this is a reference to a
5892 GP relative symbol, we want
5893 addu $tempreg,$breg,$gp
5894 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5896 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5897 addu $tempreg,$tempreg,$breg
5898 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5899 With a constant we always use the latter case.
5901 With 64bit address space and no base register and $at usable,
5903 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5904 lui $at,<sym> (BFD_RELOC_HI16_S)
5905 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5908 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5909 If we have a base register, we want
5910 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5911 lui $at,<sym> (BFD_RELOC_HI16_S)
5912 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5916 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5918 Without $at we can't generate the optimal path for superscalar
5919 processors here since this would require two temporary registers.
5920 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5921 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5923 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5925 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5926 If we have a base register, we want
5927 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5928 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5930 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5932 daddu $tempreg,$tempreg,$breg
5933 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5935 If we have 64-bit addresses, as an optimization, for
5936 addresses which are 32-bit constants (e.g. kseg0/kseg1
5937 addresses) we fall back to the 32-bit address generation
5938 mechanism since it is more efficient. Note that due to
5939 the signed offset used by memory operations, the 32-bit
5940 range is shifted down by 32768 here. This code should
5941 probably attempt to generate 64-bit constants more
5942 efficiently in general.
5944 As an extension for architectures with 64-bit registers,
5945 we don't truncate 64-bit addresses given as literal
5946 constants down to 32 bits, to support existing practice
5947 in the mips64 Linux (the kernel), that compiles source
5948 files with -mabi=64, assembling them as o32 or n32 (with
5949 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
5950 the whole kernel is loaded into a memory region that is
5951 addressable with sign-extended 32-bit addresses, it is
5952 wasteful to compute the upper 32 bits of every
5953 non-literal address, that takes more space and time.
5954 Some day this should probably be implemented as an
5955 assembler option, such that the kernel doesn't have to
5956 use such ugly hacks, even though it will still have to
5957 end up converting the binary to ELF32 for a number of
5958 platforms whose boot loaders don't support ELF64
5960 if ((HAVE_64BIT_ADDRESSES
5961 && ! (offset_expr
.X_op
== O_constant
5962 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5964 && offset_expr
.X_op
== O_constant
5965 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
5967 /* ??? We don't provide a GP-relative alternative for
5968 these macros. It used not to be possible with the
5969 original relaxation code, but it could be done now. */
5971 if (used_at
== 0 && ! mips_opts
.noat
)
5973 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5974 BFD_RELOC_MIPS_HIGHEST
);
5975 macro_build (&offset_expr
, "lui", "t,u", AT
,
5977 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5978 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5980 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
5981 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
5982 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
5983 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
5989 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5990 BFD_RELOC_MIPS_HIGHEST
);
5991 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5992 tempreg
, BFD_RELOC_MIPS_HIGHER
);
5993 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5994 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
5995 tempreg
, BFD_RELOC_HI16_S
);
5996 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
5998 macro_build (NULL
, "daddu", "d,v,t",
5999 tempreg
, tempreg
, breg
);
6000 macro_build (&offset_expr
, s
, fmt
, treg
,
6001 BFD_RELOC_LO16
, tempreg
);
6007 if (offset_expr
.X_op
== O_constant
6008 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
6009 as_bad (_("load/store address overflow (max 32 bits)"));
6013 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6014 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6016 relax_start (offset_expr
.X_add_symbol
);
6017 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6022 macro_build_lui (&offset_expr
, tempreg
);
6023 macro_build (&offset_expr
, s
, fmt
, treg
,
6024 BFD_RELOC_LO16
, tempreg
);
6025 if (mips_relax
.sequence
)
6030 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6031 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6033 relax_start (offset_expr
.X_add_symbol
);
6034 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6035 tempreg
, breg
, mips_gp_register
);
6036 macro_build (&offset_expr
, s
, fmt
, treg
,
6037 BFD_RELOC_GPREL16
, tempreg
);
6040 macro_build_lui (&offset_expr
, tempreg
);
6041 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6042 tempreg
, tempreg
, breg
);
6043 macro_build (&offset_expr
, s
, fmt
, treg
,
6044 BFD_RELOC_LO16
, tempreg
);
6045 if (mips_relax
.sequence
)
6049 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6051 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6053 /* If this is a reference to an external symbol, we want
6054 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6056 <op> $treg,0($tempreg)
6058 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6060 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6061 <op> $treg,0($tempreg)
6064 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6065 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6067 If there is a base register, we add it to $tempreg before
6068 the <op>. If there is a constant, we stick it in the
6069 <op> instruction. We don't handle constants larger than
6070 16 bits, because we have no way to load the upper 16 bits
6071 (actually, we could handle them for the subset of cases
6072 in which we are not using $at). */
6073 assert (offset_expr
.X_op
== O_symbol
);
6076 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6077 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6079 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6080 tempreg
, tempreg
, breg
);
6081 macro_build (&offset_expr
, s
, fmt
, treg
,
6082 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6089 expr1
.X_add_number
= offset_expr
.X_add_number
;
6090 offset_expr
.X_add_number
= 0;
6091 if (expr1
.X_add_number
< -0x8000
6092 || expr1
.X_add_number
>= 0x8000)
6093 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6094 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6095 lw_reloc_type
, mips_gp_register
);
6097 relax_start (offset_expr
.X_add_symbol
);
6099 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6100 tempreg
, BFD_RELOC_LO16
);
6103 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6104 tempreg
, tempreg
, breg
);
6105 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6107 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6111 /* If this is a reference to an external symbol, we want
6112 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6113 addu $tempreg,$tempreg,$gp
6114 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6115 <op> $treg,0($tempreg)
6117 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6119 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6120 <op> $treg,0($tempreg)
6121 If there is a base register, we add it to $tempreg before
6122 the <op>. If there is a constant, we stick it in the
6123 <op> instruction. We don't handle constants larger than
6124 16 bits, because we have no way to load the upper 16 bits
6125 (actually, we could handle them for the subset of cases
6126 in which we are not using $at). */
6127 assert (offset_expr
.X_op
== O_symbol
);
6128 expr1
.X_add_number
= offset_expr
.X_add_number
;
6129 offset_expr
.X_add_number
= 0;
6130 if (expr1
.X_add_number
< -0x8000
6131 || expr1
.X_add_number
>= 0x8000)
6132 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6133 gpdelay
= reg_needs_delay (mips_gp_register
);
6134 relax_start (offset_expr
.X_add_symbol
);
6135 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6136 BFD_RELOC_MIPS_GOT_HI16
);
6137 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6139 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6140 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6143 macro_build (NULL
, "nop", "");
6144 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6145 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6147 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6148 tempreg
, BFD_RELOC_LO16
);
6152 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6153 tempreg
, tempreg
, breg
);
6154 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6156 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6158 /* If this is a reference to an external symbol, we want
6159 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6160 add $tempreg,$tempreg,$gp
6161 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6162 <op> $treg,<ofst>($tempreg)
6163 Otherwise, for local symbols, we want:
6164 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6165 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6166 assert (offset_expr
.X_op
== O_symbol
);
6167 expr1
.X_add_number
= offset_expr
.X_add_number
;
6168 offset_expr
.X_add_number
= 0;
6169 if (expr1
.X_add_number
< -0x8000
6170 || expr1
.X_add_number
>= 0x8000)
6171 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6172 relax_start (offset_expr
.X_add_symbol
);
6173 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6174 BFD_RELOC_MIPS_GOT_HI16
);
6175 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6177 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6178 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6180 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6181 tempreg
, tempreg
, breg
);
6182 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6185 offset_expr
.X_add_number
= expr1
.X_add_number
;
6186 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6187 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6189 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6190 tempreg
, tempreg
, breg
);
6191 macro_build (&offset_expr
, s
, fmt
, treg
,
6192 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6205 load_register (treg
, &imm_expr
, 0);
6209 load_register (treg
, &imm_expr
, 1);
6213 if (imm_expr
.X_op
== O_constant
)
6215 load_register (AT
, &imm_expr
, 0);
6216 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6221 assert (offset_expr
.X_op
== O_symbol
6222 && strcmp (segment_name (S_GET_SEGMENT
6223 (offset_expr
.X_add_symbol
)),
6225 && offset_expr
.X_add_number
== 0);
6226 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6227 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6232 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6233 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6234 order 32 bits of the value and the low order 32 bits are either
6235 zero or in OFFSET_EXPR. */
6236 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6238 if (HAVE_64BIT_GPRS
)
6239 load_register (treg
, &imm_expr
, 1);
6244 if (target_big_endian
)
6256 load_register (hreg
, &imm_expr
, 0);
6259 if (offset_expr
.X_op
== O_absent
)
6260 move_register (lreg
, 0);
6263 assert (offset_expr
.X_op
== O_constant
);
6264 load_register (lreg
, &offset_expr
, 0);
6271 /* We know that sym is in the .rdata section. First we get the
6272 upper 16 bits of the address. */
6273 if (mips_pic
== NO_PIC
)
6275 macro_build_lui (&offset_expr
, AT
);
6277 else if (mips_pic
== SVR4_PIC
)
6279 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6280 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6285 /* Now we load the register(s). */
6286 if (HAVE_64BIT_GPRS
)
6287 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6290 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6293 /* FIXME: How in the world do we deal with the possible
6295 offset_expr
.X_add_number
+= 4;
6296 macro_build (&offset_expr
, "lw", "t,o(b)",
6297 treg
+ 1, BFD_RELOC_LO16
, AT
);
6303 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6304 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6305 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6306 the value and the low order 32 bits are either zero or in
6308 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6310 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6311 if (HAVE_64BIT_FPRS
)
6313 assert (HAVE_64BIT_GPRS
);
6314 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6318 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6319 if (offset_expr
.X_op
== O_absent
)
6320 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6323 assert (offset_expr
.X_op
== O_constant
);
6324 load_register (AT
, &offset_expr
, 0);
6325 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6331 assert (offset_expr
.X_op
== O_symbol
6332 && offset_expr
.X_add_number
== 0);
6333 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6334 if (strcmp (s
, ".lit8") == 0)
6336 if (mips_opts
.isa
!= ISA_MIPS1
)
6338 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6339 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6342 breg
= mips_gp_register
;
6343 r
= BFD_RELOC_MIPS_LITERAL
;
6348 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6349 if (mips_pic
== SVR4_PIC
)
6350 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6351 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6354 /* FIXME: This won't work for a 64 bit address. */
6355 macro_build_lui (&offset_expr
, AT
);
6358 if (mips_opts
.isa
!= ISA_MIPS1
)
6360 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6361 treg
, BFD_RELOC_LO16
, AT
);
6370 if (mips_opts
.arch
== CPU_R4650
)
6372 as_bad (_("opcode not supported on this processor"));
6375 /* Even on a big endian machine $fn comes before $fn+1. We have
6376 to adjust when loading from memory. */
6379 assert (mips_opts
.isa
== ISA_MIPS1
);
6380 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6381 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6382 /* FIXME: A possible overflow which I don't know how to deal
6384 offset_expr
.X_add_number
+= 4;
6385 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6386 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6394 * The MIPS assembler seems to check for X_add_number not
6395 * being double aligned and generating:
6398 * addiu at,at,%lo(foo+1)
6401 * But, the resulting address is the same after relocation so why
6402 * generate the extra instruction?
6404 if (mips_opts
.arch
== CPU_R4650
)
6406 as_bad (_("opcode not supported on this processor"));
6409 /* Itbl support may require additional care here. */
6411 if (mips_opts
.isa
!= ISA_MIPS1
)
6422 if (mips_opts
.arch
== CPU_R4650
)
6424 as_bad (_("opcode not supported on this processor"));
6428 if (mips_opts
.isa
!= ISA_MIPS1
)
6436 /* Itbl support may require additional care here. */
6441 if (HAVE_64BIT_GPRS
)
6452 if (HAVE_64BIT_GPRS
)
6462 if (offset_expr
.X_op
!= O_symbol
6463 && offset_expr
.X_op
!= O_constant
)
6465 as_bad (_("expression too complex"));
6466 offset_expr
.X_op
= O_constant
;
6469 /* Even on a big endian machine $fn comes before $fn+1. We have
6470 to adjust when loading from memory. We set coproc if we must
6471 load $fn+1 first. */
6472 /* Itbl support may require additional care here. */
6473 if (! target_big_endian
)
6476 if (mips_pic
== NO_PIC
6477 || offset_expr
.X_op
== O_constant
)
6479 /* If this is a reference to a GP relative symbol, we want
6480 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6481 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6482 If we have a base register, we use this
6484 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6485 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6486 If this is not a GP relative symbol, we want
6487 lui $at,<sym> (BFD_RELOC_HI16_S)
6488 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6489 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6490 If there is a base register, we add it to $at after the
6491 lui instruction. If there is a constant, we always use
6493 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6494 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6498 relax_start (offset_expr
.X_add_symbol
);
6501 tempreg
= mips_gp_register
;
6506 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6507 AT
, breg
, mips_gp_register
);
6512 /* Itbl support may require additional care here. */
6513 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6514 BFD_RELOC_GPREL16
, tempreg
);
6515 offset_expr
.X_add_number
+= 4;
6517 /* Set mips_optimize to 2 to avoid inserting an
6519 hold_mips_optimize
= mips_optimize
;
6521 /* Itbl support may require additional care here. */
6522 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6523 BFD_RELOC_GPREL16
, tempreg
);
6524 mips_optimize
= hold_mips_optimize
;
6528 /* We just generated two relocs. When tc_gen_reloc
6529 handles this case, it will skip the first reloc and
6530 handle the second. The second reloc already has an
6531 extra addend of 4, which we added above. We must
6532 subtract it out, and then subtract another 4 to make
6533 the first reloc come out right. The second reloc
6534 will come out right because we are going to add 4 to
6535 offset_expr when we build its instruction below.
6537 If we have a symbol, then we don't want to include
6538 the offset, because it will wind up being included
6539 when we generate the reloc. */
6541 if (offset_expr
.X_op
== O_constant
)
6542 offset_expr
.X_add_number
-= 8;
6545 offset_expr
.X_add_number
= -4;
6546 offset_expr
.X_op
= O_constant
;
6549 macro_build_lui (&offset_expr
, AT
);
6551 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6552 /* Itbl support may require additional care here. */
6553 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6554 BFD_RELOC_LO16
, AT
);
6555 /* FIXME: How do we handle overflow here? */
6556 offset_expr
.X_add_number
+= 4;
6557 /* Itbl support may require additional care here. */
6558 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6559 BFD_RELOC_LO16
, AT
);
6560 if (mips_relax
.sequence
)
6563 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6565 /* If this is a reference to an external symbol, we want
6566 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6571 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6573 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6574 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6575 If there is a base register we add it to $at before the
6576 lwc1 instructions. If there is a constant we include it
6577 in the lwc1 instructions. */
6579 expr1
.X_add_number
= offset_expr
.X_add_number
;
6580 if (expr1
.X_add_number
< -0x8000
6581 || expr1
.X_add_number
>= 0x8000 - 4)
6582 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6583 load_got_offset (AT
, &offset_expr
);
6586 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6588 /* Set mips_optimize to 2 to avoid inserting an undesired
6590 hold_mips_optimize
= mips_optimize
;
6593 /* Itbl support may require additional care here. */
6594 relax_start (offset_expr
.X_add_symbol
);
6595 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6596 BFD_RELOC_LO16
, AT
);
6597 expr1
.X_add_number
+= 4;
6598 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6599 BFD_RELOC_LO16
, AT
);
6601 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6602 BFD_RELOC_LO16
, AT
);
6603 offset_expr
.X_add_number
+= 4;
6604 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6605 BFD_RELOC_LO16
, AT
);
6608 mips_optimize
= hold_mips_optimize
;
6610 else if (mips_pic
== SVR4_PIC
)
6614 /* If this is a reference to an external symbol, we want
6615 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6617 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6622 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6624 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6625 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6626 If there is a base register we add it to $at before the
6627 lwc1 instructions. If there is a constant we include it
6628 in the lwc1 instructions. */
6630 expr1
.X_add_number
= offset_expr
.X_add_number
;
6631 offset_expr
.X_add_number
= 0;
6632 if (expr1
.X_add_number
< -0x8000
6633 || expr1
.X_add_number
>= 0x8000 - 4)
6634 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6635 gpdelay
= reg_needs_delay (mips_gp_register
);
6636 relax_start (offset_expr
.X_add_symbol
);
6637 macro_build (&offset_expr
, "lui", "t,u",
6638 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6639 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6640 AT
, AT
, mips_gp_register
);
6641 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6642 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6645 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6646 /* Itbl support may require additional care here. */
6647 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6648 BFD_RELOC_LO16
, AT
);
6649 expr1
.X_add_number
+= 4;
6651 /* Set mips_optimize to 2 to avoid inserting an undesired
6653 hold_mips_optimize
= mips_optimize
;
6655 /* Itbl support may require additional care here. */
6656 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6657 BFD_RELOC_LO16
, AT
);
6658 mips_optimize
= hold_mips_optimize
;
6659 expr1
.X_add_number
-= 4;
6662 offset_expr
.X_add_number
= expr1
.X_add_number
;
6664 macro_build (NULL
, "nop", "");
6665 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6666 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6669 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6670 /* Itbl support may require additional care here. */
6671 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6672 BFD_RELOC_LO16
, AT
);
6673 offset_expr
.X_add_number
+= 4;
6675 /* Set mips_optimize to 2 to avoid inserting an undesired
6677 hold_mips_optimize
= mips_optimize
;
6679 /* Itbl support may require additional care here. */
6680 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6681 BFD_RELOC_LO16
, AT
);
6682 mips_optimize
= hold_mips_optimize
;
6699 assert (HAVE_32BIT_ADDRESSES
);
6700 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6701 offset_expr
.X_add_number
+= 4;
6702 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6705 /* New code added to support COPZ instructions.
6706 This code builds table entries out of the macros in mip_opcodes.
6707 R4000 uses interlocks to handle coproc delays.
6708 Other chips (like the R3000) require nops to be inserted for delays.
6710 FIXME: Currently, we require that the user handle delays.
6711 In order to fill delay slots for non-interlocked chips,
6712 we must have a way to specify delays based on the coprocessor.
6713 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6714 What are the side-effects of the cop instruction?
6715 What cache support might we have and what are its effects?
6716 Both coprocessor & memory require delays. how long???
6717 What registers are read/set/modified?
6719 If an itbl is provided to interpret cop instructions,
6720 this knowledge can be encoded in the itbl spec. */
6734 /* For now we just do C (same as Cz). The parameter will be
6735 stored in insn_opcode by mips_ip. */
6736 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6740 move_register (dreg
, sreg
);
6743 #ifdef LOSING_COMPILER
6745 /* Try and see if this is a new itbl instruction.
6746 This code builds table entries out of the macros in mip_opcodes.
6747 FIXME: For now we just assemble the expression and pass it's
6748 value along as a 32-bit immediate.
6749 We may want to have the assembler assemble this value,
6750 so that we gain the assembler's knowledge of delay slots,
6752 Would it be more efficient to use mask (id) here? */
6753 if (itbl_have_entries
6754 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6756 s
= ip
->insn_mo
->name
;
6758 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6759 macro_build (&immed_expr
, s
, "C");
6766 as_warn (_("Macro used $at after \".set noat\""));
6770 macro2 (struct mips_cl_insn
*ip
)
6772 register int treg
, sreg
, dreg
, breg
;
6787 bfd_reloc_code_real_type r
;
6789 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6790 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6791 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6792 mask
= ip
->insn_mo
->mask
;
6794 expr1
.X_op
= O_constant
;
6795 expr1
.X_op_symbol
= NULL
;
6796 expr1
.X_add_symbol
= NULL
;
6797 expr1
.X_add_number
= 1;
6801 #endif /* LOSING_COMPILER */
6806 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6807 macro_build (NULL
, "mflo", "d", dreg
);
6813 /* The MIPS assembler some times generates shifts and adds. I'm
6814 not trying to be that fancy. GCC should do this for us
6816 load_register (AT
, &imm_expr
, dbl
);
6817 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6818 macro_build (NULL
, "mflo", "d", dreg
);
6831 mips_emit_delays (TRUE
);
6832 ++mips_opts
.noreorder
;
6833 mips_any_noreorder
= 1;
6835 load_register (AT
, &imm_expr
, dbl
);
6836 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6837 macro_build (NULL
, "mflo", "d", dreg
);
6838 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6839 macro_build (NULL
, "mfhi", "d", AT
);
6841 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6844 expr1
.X_add_number
= 8;
6845 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6846 macro_build (NULL
, "nop", "", 0);
6847 macro_build (NULL
, "break", "c", 6);
6849 --mips_opts
.noreorder
;
6850 macro_build (NULL
, "mflo", "d", dreg
);
6863 mips_emit_delays (TRUE
);
6864 ++mips_opts
.noreorder
;
6865 mips_any_noreorder
= 1;
6867 load_register (AT
, &imm_expr
, dbl
);
6868 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
6869 sreg
, imm
? AT
: treg
);
6870 macro_build (NULL
, "mfhi", "d", AT
);
6871 macro_build (NULL
, "mflo", "d", dreg
);
6873 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
6876 expr1
.X_add_number
= 8;
6877 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
6878 macro_build (NULL
, "nop", "", 0);
6879 macro_build (NULL
, "break", "c", 6);
6881 --mips_opts
.noreorder
;
6885 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6897 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
6898 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
6903 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6904 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
6905 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
6906 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6910 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6922 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
6923 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
6928 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
6929 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6930 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
6931 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6939 if (imm_expr
.X_op
!= O_constant
)
6940 as_bad (_("Improper rotate count"));
6941 rot
= imm_expr
.X_add_number
& 0x3f;
6942 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6944 rot
= (64 - rot
) & 0x3f;
6946 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
6948 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
6953 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
6956 l
= (rot
< 0x20) ? "dsll" : "dsll32";
6957 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
6959 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
6960 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6961 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6969 if (imm_expr
.X_op
!= O_constant
)
6970 as_bad (_("Improper rotate count"));
6971 rot
= imm_expr
.X_add_number
& 0x1f;
6972 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
6974 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
6979 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
6982 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
6983 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
6984 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6989 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
6991 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
6994 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
6995 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
6996 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
6997 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7001 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7003 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7006 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7007 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7008 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7009 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7017 if (imm_expr
.X_op
!= O_constant
)
7018 as_bad (_("Improper rotate count"));
7019 rot
= imm_expr
.X_add_number
& 0x3f;
7020 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7023 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7025 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7030 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7033 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7034 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7036 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7037 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7038 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7046 if (imm_expr
.X_op
!= O_constant
)
7047 as_bad (_("Improper rotate count"));
7048 rot
= imm_expr
.X_add_number
& 0x1f;
7049 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7051 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7056 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7059 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7060 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7061 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7066 if (mips_opts
.arch
== CPU_R4650
)
7068 as_bad (_("opcode not supported on this processor"));
7071 assert (mips_opts
.isa
== ISA_MIPS1
);
7072 /* Even on a big endian machine $fn comes before $fn+1. We have
7073 to adjust when storing to memory. */
7074 macro_build (&offset_expr
, "swc1", "T,o(b)",
7075 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7076 offset_expr
.X_add_number
+= 4;
7077 macro_build (&offset_expr
, "swc1", "T,o(b)",
7078 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7083 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7085 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7088 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7089 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7094 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7096 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7101 as_warn (_("Instruction %s: result is always false"),
7103 move_register (dreg
, 0);
7106 if (imm_expr
.X_op
== O_constant
7107 && imm_expr
.X_add_number
>= 0
7108 && imm_expr
.X_add_number
< 0x10000)
7110 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7113 else if (imm_expr
.X_op
== O_constant
7114 && imm_expr
.X_add_number
> -0x8000
7115 && imm_expr
.X_add_number
< 0)
7117 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7118 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7119 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7124 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7125 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7128 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7133 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7139 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7140 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7143 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7145 if (imm_expr
.X_op
== O_constant
7146 && imm_expr
.X_add_number
>= -0x8000
7147 && imm_expr
.X_add_number
< 0x8000)
7149 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7150 dreg
, sreg
, BFD_RELOC_LO16
);
7155 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7156 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7160 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7165 case M_SGT
: /* sreg > treg <==> treg < sreg */
7171 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7174 case M_SGT_I
: /* sreg > I <==> I < sreg */
7180 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7181 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7184 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7190 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7191 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7194 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7200 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7201 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7202 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7206 if (imm_expr
.X_op
== O_constant
7207 && imm_expr
.X_add_number
>= -0x8000
7208 && imm_expr
.X_add_number
< 0x8000)
7210 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7213 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7214 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7218 if (imm_expr
.X_op
== O_constant
7219 && imm_expr
.X_add_number
>= -0x8000
7220 && imm_expr
.X_add_number
< 0x8000)
7222 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7226 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7227 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7232 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7234 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7237 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7238 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7243 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7245 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7250 as_warn (_("Instruction %s: result is always true"),
7252 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7253 dreg
, 0, BFD_RELOC_LO16
);
7256 if (imm_expr
.X_op
== O_constant
7257 && imm_expr
.X_add_number
>= 0
7258 && imm_expr
.X_add_number
< 0x10000)
7260 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7263 else if (imm_expr
.X_op
== O_constant
7264 && imm_expr
.X_add_number
> -0x8000
7265 && imm_expr
.X_add_number
< 0)
7267 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7268 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7269 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7274 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7275 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7278 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7286 if (imm_expr
.X_op
== O_constant
7287 && imm_expr
.X_add_number
> -0x8000
7288 && imm_expr
.X_add_number
<= 0x8000)
7290 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7291 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7292 dreg
, sreg
, BFD_RELOC_LO16
);
7295 load_register (AT
, &imm_expr
, dbl
);
7296 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7302 if (imm_expr
.X_op
== O_constant
7303 && imm_expr
.X_add_number
> -0x8000
7304 && imm_expr
.X_add_number
<= 0x8000)
7306 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7307 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7308 dreg
, sreg
, BFD_RELOC_LO16
);
7311 load_register (AT
, &imm_expr
, dbl
);
7312 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7333 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7334 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7339 assert (mips_opts
.isa
== ISA_MIPS1
);
7340 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7341 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7344 * Is the double cfc1 instruction a bug in the mips assembler;
7345 * or is there a reason for it?
7347 mips_emit_delays (TRUE
);
7348 ++mips_opts
.noreorder
;
7349 mips_any_noreorder
= 1;
7350 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7351 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7352 macro_build (NULL
, "nop", "");
7353 expr1
.X_add_number
= 3;
7354 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7355 expr1
.X_add_number
= 2;
7356 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7357 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7358 macro_build (NULL
, "nop", "");
7359 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7361 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7362 macro_build (NULL
, "nop", "");
7363 --mips_opts
.noreorder
;
7372 if (offset_expr
.X_add_number
>= 0x7fff)
7373 as_bad (_("operand overflow"));
7374 if (! target_big_endian
)
7375 ++offset_expr
.X_add_number
;
7376 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7377 if (! target_big_endian
)
7378 --offset_expr
.X_add_number
;
7380 ++offset_expr
.X_add_number
;
7381 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7382 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7383 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7396 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7397 as_bad (_("operand overflow"));
7402 if (! target_big_endian
)
7403 offset_expr
.X_add_number
+= off
;
7404 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7405 if (! target_big_endian
)
7406 offset_expr
.X_add_number
-= off
;
7408 offset_expr
.X_add_number
+= off
;
7409 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7411 /* If necessary, move the result in tempreg the final destination. */
7412 if (treg
== tempreg
)
7414 /* Protect second load's delay slot. */
7416 move_register (treg
, tempreg
);
7430 load_address (AT
, &offset_expr
, &used_at
);
7432 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7433 if (! target_big_endian
)
7434 expr1
.X_add_number
= off
;
7436 expr1
.X_add_number
= 0;
7437 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7438 if (! target_big_endian
)
7439 expr1
.X_add_number
= 0;
7441 expr1
.X_add_number
= off
;
7442 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7448 load_address (AT
, &offset_expr
, &used_at
);
7450 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7451 if (target_big_endian
)
7452 expr1
.X_add_number
= 0;
7453 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7454 treg
, BFD_RELOC_LO16
, AT
);
7455 if (target_big_endian
)
7456 expr1
.X_add_number
= 1;
7458 expr1
.X_add_number
= 0;
7459 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7460 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7461 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7465 if (offset_expr
.X_add_number
>= 0x7fff)
7466 as_bad (_("operand overflow"));
7467 if (target_big_endian
)
7468 ++offset_expr
.X_add_number
;
7469 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7470 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7471 if (target_big_endian
)
7472 --offset_expr
.X_add_number
;
7474 ++offset_expr
.X_add_number
;
7475 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7488 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7489 as_bad (_("operand overflow"));
7490 if (! target_big_endian
)
7491 offset_expr
.X_add_number
+= off
;
7492 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7493 if (! target_big_endian
)
7494 offset_expr
.X_add_number
-= off
;
7496 offset_expr
.X_add_number
+= off
;
7497 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7511 load_address (AT
, &offset_expr
, &used_at
);
7513 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7514 if (! target_big_endian
)
7515 expr1
.X_add_number
= off
;
7517 expr1
.X_add_number
= 0;
7518 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7519 if (! target_big_endian
)
7520 expr1
.X_add_number
= 0;
7522 expr1
.X_add_number
= off
;
7523 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7528 load_address (AT
, &offset_expr
, &used_at
);
7530 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7531 if (! target_big_endian
)
7532 expr1
.X_add_number
= 0;
7533 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7534 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7535 if (! target_big_endian
)
7536 expr1
.X_add_number
= 1;
7538 expr1
.X_add_number
= 0;
7539 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7540 if (! target_big_endian
)
7541 expr1
.X_add_number
= 0;
7543 expr1
.X_add_number
= 1;
7544 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7545 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7546 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7550 /* FIXME: Check if this is one of the itbl macros, since they
7551 are added dynamically. */
7552 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7556 as_warn (_("Macro used $at after \".set noat\""));
7559 /* Implement macros in mips16 mode. */
7562 mips16_macro (struct mips_cl_insn
*ip
)
7565 int xreg
, yreg
, zreg
, tmp
;
7568 const char *s
, *s2
, *s3
;
7570 mask
= ip
->insn_mo
->mask
;
7572 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7573 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7574 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7576 expr1
.X_op
= O_constant
;
7577 expr1
.X_op_symbol
= NULL
;
7578 expr1
.X_add_symbol
= NULL
;
7579 expr1
.X_add_number
= 1;
7598 mips_emit_delays (TRUE
);
7599 ++mips_opts
.noreorder
;
7600 mips_any_noreorder
= 1;
7601 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7602 expr1
.X_add_number
= 2;
7603 macro_build (&expr1
, "bnez", "x,p", yreg
);
7604 macro_build (NULL
, "break", "6", 7);
7606 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7607 since that causes an overflow. We should do that as well,
7608 but I don't see how to do the comparisons without a temporary
7610 --mips_opts
.noreorder
;
7611 macro_build (NULL
, s
, "x", zreg
);
7630 mips_emit_delays (TRUE
);
7631 ++mips_opts
.noreorder
;
7632 mips_any_noreorder
= 1;
7633 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7634 expr1
.X_add_number
= 2;
7635 macro_build (&expr1
, "bnez", "x,p", yreg
);
7636 macro_build (NULL
, "break", "6", 7);
7637 --mips_opts
.noreorder
;
7638 macro_build (NULL
, s2
, "x", zreg
);
7644 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7645 macro_build (NULL
, "mflo", "x", zreg
);
7653 if (imm_expr
.X_op
!= O_constant
)
7654 as_bad (_("Unsupported large constant"));
7655 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7656 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7660 if (imm_expr
.X_op
!= O_constant
)
7661 as_bad (_("Unsupported large constant"));
7662 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7663 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7667 if (imm_expr
.X_op
!= O_constant
)
7668 as_bad (_("Unsupported large constant"));
7669 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7670 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7692 goto do_reverse_branch
;
7696 goto do_reverse_branch
;
7708 goto do_reverse_branch
;
7719 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7720 macro_build (&offset_expr
, s2
, "p");
7747 goto do_addone_branch_i
;
7752 goto do_addone_branch_i
;
7767 goto do_addone_branch_i
;
7774 if (imm_expr
.X_op
!= O_constant
)
7775 as_bad (_("Unsupported large constant"));
7776 ++imm_expr
.X_add_number
;
7779 macro_build (&imm_expr
, s
, s3
, xreg
);
7780 macro_build (&offset_expr
, s2
, "p");
7784 expr1
.X_add_number
= 0;
7785 macro_build (&expr1
, "slti", "x,8", yreg
);
7787 move_register (xreg
, yreg
);
7788 expr1
.X_add_number
= 2;
7789 macro_build (&expr1
, "bteqz", "p");
7790 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7794 /* For consistency checking, verify that all bits are specified either
7795 by the match/mask part of the instruction definition, or by the
7798 validate_mips_insn (const struct mips_opcode
*opc
)
7800 const char *p
= opc
->args
;
7802 unsigned long used_bits
= opc
->mask
;
7804 if ((used_bits
& opc
->match
) != opc
->match
)
7806 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7807 opc
->name
, opc
->args
);
7810 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7820 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7821 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7822 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7823 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7824 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7825 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7826 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7827 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7828 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7831 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7832 c
, opc
->name
, opc
->args
);
7836 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7837 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7839 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7840 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7841 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7842 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7844 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7845 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7847 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7848 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7850 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7851 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7852 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7853 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7854 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7855 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7856 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7857 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7858 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7859 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7860 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7861 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7862 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7863 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
7864 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7865 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
7866 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7868 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
7869 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7870 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7871 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
7873 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7874 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
7875 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
7876 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7877 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7878 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7879 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
7880 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
7881 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7884 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
7885 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7886 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7887 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
7888 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
7892 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
7893 c
, opc
->name
, opc
->args
);
7897 if (used_bits
!= 0xffffffff)
7899 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
7900 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
7906 /* This routine assembles an instruction into its binary format. As a
7907 side effect, it sets one of the global variables imm_reloc or
7908 offset_reloc to the type of relocation to do if one of the operands
7909 is an address expression. */
7912 mips_ip (char *str
, struct mips_cl_insn
*ip
)
7917 struct mips_opcode
*insn
;
7920 unsigned int lastregno
= 0;
7921 unsigned int lastpos
= 0;
7922 unsigned int limlo
, limhi
;
7928 /* If the instruction contains a '.', we first try to match an instruction
7929 including the '.'. Then we try again without the '.'. */
7931 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
7934 /* If we stopped on whitespace, then replace the whitespace with null for
7935 the call to hash_find. Save the character we replaced just in case we
7936 have to re-parse the instruction. */
7943 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7945 /* If we didn't find the instruction in the opcode table, try again, but
7946 this time with just the instruction up to, but not including the
7950 /* Restore the character we overwrite above (if any). */
7954 /* Scan up to the first '.' or whitespace. */
7956 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
7960 /* If we did not find a '.', then we can quit now. */
7963 insn_error
= "unrecognized opcode";
7967 /* Lookup the instruction in the hash table. */
7969 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7971 insn_error
= "unrecognized opcode";
7981 assert (strcmp (insn
->name
, str
) == 0);
7983 if (OPCODE_IS_MEMBER (insn
,
7985 | (file_ase_mips16
? INSN_MIPS16
: 0)
7986 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
7987 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
7993 if (insn
->pinfo
!= INSN_MACRO
)
7995 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8001 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8002 && strcmp (insn
->name
, insn
[1].name
) == 0)
8011 static char buf
[100];
8013 _("opcode not supported on this processor: %s (%s)"),
8014 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8015 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8025 ip
->insn_opcode
= insn
->match
;
8027 for (args
= insn
->args
;; ++args
)
8031 s
+= strspn (s
, " \t");
8035 case '\0': /* end of args */
8048 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8052 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8056 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8060 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8066 /* Handle optional base register.
8067 Either the base register is omitted or
8068 we must have a left paren. */
8069 /* This is dependent on the next operand specifier
8070 is a base register specification. */
8071 assert (args
[1] == 'b' || args
[1] == '5'
8072 || args
[1] == '-' || args
[1] == '4');
8076 case ')': /* these must match exactly */
8083 case '+': /* Opcode extension character. */
8086 case 'A': /* ins/ext position, becomes LSB. */
8095 my_getExpression (&imm_expr
, s
);
8096 check_absolute_expr (ip
, &imm_expr
);
8097 if ((unsigned long) imm_expr
.X_add_number
< limlo
8098 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8100 as_bad (_("Improper position (%lu)"),
8101 (unsigned long) imm_expr
.X_add_number
);
8102 imm_expr
.X_add_number
= limlo
;
8104 lastpos
= imm_expr
.X_add_number
;
8105 ip
->insn_opcode
|= (imm_expr
.X_add_number
8106 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8107 imm_expr
.X_op
= O_absent
;
8111 case 'B': /* ins size, becomes MSB. */
8120 my_getExpression (&imm_expr
, s
);
8121 check_absolute_expr (ip
, &imm_expr
);
8122 /* Check for negative input so that small negative numbers
8123 will not succeed incorrectly. The checks against
8124 (pos+size) transitively check "size" itself,
8125 assuming that "pos" is reasonable. */
8126 if ((long) imm_expr
.X_add_number
< 0
8127 || ((unsigned long) imm_expr
.X_add_number
8129 || ((unsigned long) imm_expr
.X_add_number
8132 as_bad (_("Improper insert size (%lu, position %lu)"),
8133 (unsigned long) imm_expr
.X_add_number
,
8134 (unsigned long) lastpos
);
8135 imm_expr
.X_add_number
= limlo
- lastpos
;
8137 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8138 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8139 imm_expr
.X_op
= O_absent
;
8143 case 'C': /* ext size, becomes MSBD. */
8156 my_getExpression (&imm_expr
, s
);
8157 check_absolute_expr (ip
, &imm_expr
);
8158 /* Check for negative input so that small negative numbers
8159 will not succeed incorrectly. The checks against
8160 (pos+size) transitively check "size" itself,
8161 assuming that "pos" is reasonable. */
8162 if ((long) imm_expr
.X_add_number
< 0
8163 || ((unsigned long) imm_expr
.X_add_number
8165 || ((unsigned long) imm_expr
.X_add_number
8168 as_bad (_("Improper extract size (%lu, position %lu)"),
8169 (unsigned long) imm_expr
.X_add_number
,
8170 (unsigned long) lastpos
);
8171 imm_expr
.X_add_number
= limlo
- lastpos
;
8173 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8174 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8175 imm_expr
.X_op
= O_absent
;
8180 /* +D is for disassembly only; never match. */
8184 /* "+I" is like "I", except that imm2_expr is used. */
8185 my_getExpression (&imm2_expr
, s
);
8186 if (imm2_expr
.X_op
!= O_big
8187 && imm2_expr
.X_op
!= O_constant
)
8188 insn_error
= _("absolute expression required");
8189 normalize_constant_expr (&imm2_expr
);
8194 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8195 *args
, insn
->name
, insn
->args
);
8196 /* Further processing is fruitless. */
8201 case '<': /* must be at least one digit */
8203 * According to the manual, if the shift amount is greater
8204 * than 31 or less than 0, then the shift amount should be
8205 * mod 32. In reality the mips assembler issues an error.
8206 * We issue a warning and mask out all but the low 5 bits.
8208 my_getExpression (&imm_expr
, s
);
8209 check_absolute_expr (ip
, &imm_expr
);
8210 if ((unsigned long) imm_expr
.X_add_number
> 31)
8212 as_warn (_("Improper shift amount (%lu)"),
8213 (unsigned long) imm_expr
.X_add_number
);
8214 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8216 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8217 imm_expr
.X_op
= O_absent
;
8221 case '>': /* shift amount minus 32 */
8222 my_getExpression (&imm_expr
, s
);
8223 check_absolute_expr (ip
, &imm_expr
);
8224 if ((unsigned long) imm_expr
.X_add_number
< 32
8225 || (unsigned long) imm_expr
.X_add_number
> 63)
8227 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8228 imm_expr
.X_op
= O_absent
;
8232 case 'k': /* cache code */
8233 case 'h': /* prefx code */
8234 my_getExpression (&imm_expr
, s
);
8235 check_absolute_expr (ip
, &imm_expr
);
8236 if ((unsigned long) imm_expr
.X_add_number
> 31)
8238 as_warn (_("Invalid value for `%s' (%lu)"),
8240 (unsigned long) imm_expr
.X_add_number
);
8241 imm_expr
.X_add_number
&= 0x1f;
8244 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8246 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8247 imm_expr
.X_op
= O_absent
;
8251 case 'c': /* break code */
8252 my_getExpression (&imm_expr
, s
);
8253 check_absolute_expr (ip
, &imm_expr
);
8254 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8256 as_warn (_("Illegal break code (%lu)"),
8257 (unsigned long) imm_expr
.X_add_number
);
8258 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8260 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8261 imm_expr
.X_op
= O_absent
;
8265 case 'q': /* lower break code */
8266 my_getExpression (&imm_expr
, s
);
8267 check_absolute_expr (ip
, &imm_expr
);
8268 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8270 as_warn (_("Illegal lower break code (%lu)"),
8271 (unsigned long) imm_expr
.X_add_number
);
8272 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8274 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8275 imm_expr
.X_op
= O_absent
;
8279 case 'B': /* 20-bit syscall/break code. */
8280 my_getExpression (&imm_expr
, s
);
8281 check_absolute_expr (ip
, &imm_expr
);
8282 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8283 as_warn (_("Illegal 20-bit code (%lu)"),
8284 (unsigned long) imm_expr
.X_add_number
);
8285 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8286 imm_expr
.X_op
= O_absent
;
8290 case 'C': /* Coprocessor code */
8291 my_getExpression (&imm_expr
, s
);
8292 check_absolute_expr (ip
, &imm_expr
);
8293 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8295 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8296 (unsigned long) imm_expr
.X_add_number
);
8297 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8299 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8300 imm_expr
.X_op
= O_absent
;
8304 case 'J': /* 19-bit wait code. */
8305 my_getExpression (&imm_expr
, s
);
8306 check_absolute_expr (ip
, &imm_expr
);
8307 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8308 as_warn (_("Illegal 19-bit code (%lu)"),
8309 (unsigned long) imm_expr
.X_add_number
);
8310 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8311 imm_expr
.X_op
= O_absent
;
8315 case 'P': /* Performance register */
8316 my_getExpression (&imm_expr
, s
);
8317 check_absolute_expr (ip
, &imm_expr
);
8318 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8320 as_warn (_("Invalid performance register (%lu)"),
8321 (unsigned long) imm_expr
.X_add_number
);
8322 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8324 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8325 imm_expr
.X_op
= O_absent
;
8329 case 'b': /* base register */
8330 case 'd': /* destination register */
8331 case 's': /* source register */
8332 case 't': /* target register */
8333 case 'r': /* both target and source */
8334 case 'v': /* both dest and source */
8335 case 'w': /* both dest and target */
8336 case 'E': /* coprocessor target register */
8337 case 'G': /* coprocessor destination register */
8338 case 'K': /* 'rdhwr' destination register */
8339 case 'x': /* ignore register name */
8340 case 'z': /* must be zero register */
8341 case 'U': /* destination register (clo/clz). */
8356 while (ISDIGIT (*s
));
8358 as_bad (_("Invalid register number (%d)"), regno
);
8360 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8364 if (s
[1] == 'r' && s
[2] == 'a')
8369 else if (s
[1] == 'f' && s
[2] == 'p')
8374 else if (s
[1] == 's' && s
[2] == 'p')
8379 else if (s
[1] == 'g' && s
[2] == 'p')
8384 else if (s
[1] == 'a' && s
[2] == 't')
8389 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8394 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8399 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8404 else if (itbl_have_entries
)
8409 p
= s
+ 1; /* advance past '$' */
8410 n
= itbl_get_field (&p
); /* n is name */
8412 /* See if this is a register defined in an
8414 if (itbl_get_reg_val (n
, &r
))
8416 /* Get_field advances to the start of
8417 the next field, so we need to back
8418 rack to the end of the last field. */
8422 s
= strchr (s
, '\0');
8436 as_warn (_("Used $at without \".set noat\""));
8442 if (c
== 'r' || c
== 'v' || c
== 'w')
8449 /* 'z' only matches $0. */
8450 if (c
== 'z' && regno
!= 0)
8453 /* Now that we have assembled one operand, we use the args string
8454 * to figure out where it goes in the instruction. */
8461 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8466 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8469 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8470 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8475 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8478 /* This case exists because on the r3000 trunc
8479 expands into a macro which requires a gp
8480 register. On the r6000 or r4000 it is
8481 assembled into a single instruction which
8482 ignores the register. Thus the insn version
8483 is MIPS_ISA2 and uses 'x', and the macro
8484 version is MIPS_ISA1 and uses 't'. */
8487 /* This case is for the div instruction, which
8488 acts differently if the destination argument
8489 is $0. This only matches $0, and is checked
8490 outside the switch. */
8493 /* Itbl operand; not yet implemented. FIXME ?? */
8495 /* What about all other operands like 'i', which
8496 can be specified in the opcode table? */
8506 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8509 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8514 case 'O': /* MDMX alignment immediate constant. */
8515 my_getExpression (&imm_expr
, s
);
8516 check_absolute_expr (ip
, &imm_expr
);
8517 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8519 as_warn ("Improper align amount (%ld), using low bits",
8520 (long) imm_expr
.X_add_number
);
8521 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8523 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8524 imm_expr
.X_op
= O_absent
;
8528 case 'Q': /* MDMX vector, element sel, or const. */
8531 /* MDMX Immediate. */
8532 my_getExpression (&imm_expr
, s
);
8533 check_absolute_expr (ip
, &imm_expr
);
8534 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8536 as_warn (_("Invalid MDMX Immediate (%ld)"),
8537 (long) imm_expr
.X_add_number
);
8538 imm_expr
.X_add_number
&= OP_MASK_FT
;
8540 imm_expr
.X_add_number
&= OP_MASK_FT
;
8541 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8542 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8544 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8545 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8546 imm_expr
.X_op
= O_absent
;
8550 /* Not MDMX Immediate. Fall through. */
8551 case 'X': /* MDMX destination register. */
8552 case 'Y': /* MDMX source register. */
8553 case 'Z': /* MDMX target register. */
8555 case 'D': /* floating point destination register */
8556 case 'S': /* floating point source register */
8557 case 'T': /* floating point target register */
8558 case 'R': /* floating point source register */
8562 /* Accept $fN for FP and MDMX register numbers, and in
8563 addition accept $vN for MDMX register numbers. */
8564 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8565 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8576 while (ISDIGIT (*s
));
8579 as_bad (_("Invalid float register number (%d)"), regno
);
8581 if ((regno
& 1) != 0
8583 && ! (strcmp (str
, "mtc1") == 0
8584 || strcmp (str
, "mfc1") == 0
8585 || strcmp (str
, "lwc1") == 0
8586 || strcmp (str
, "swc1") == 0
8587 || strcmp (str
, "l.s") == 0
8588 || strcmp (str
, "s.s") == 0))
8589 as_warn (_("Float register should be even, was %d"),
8597 if (c
== 'V' || c
== 'W')
8608 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8613 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8616 /* This is like 'Z', but also needs to fix the MDMX
8617 vector/scalar select bits. Note that the
8618 scalar immediate case is handled above. */
8621 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8622 int max_el
= (is_qh
? 3 : 7);
8624 my_getExpression(&imm_expr
, s
);
8625 check_absolute_expr (ip
, &imm_expr
);
8627 if (imm_expr
.X_add_number
> max_el
)
8628 as_bad(_("Bad element selector %ld"),
8629 (long) imm_expr
.X_add_number
);
8630 imm_expr
.X_add_number
&= max_el
;
8631 ip
->insn_opcode
|= (imm_expr
.X_add_number
8634 imm_expr
.X_op
= O_absent
;
8636 as_warn(_("Expecting ']' found '%s'"), s
);
8642 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8643 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8646 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8653 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8656 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8666 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8669 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8675 my_getExpression (&imm_expr
, s
);
8676 if (imm_expr
.X_op
!= O_big
8677 && imm_expr
.X_op
!= O_constant
)
8678 insn_error
= _("absolute expression required");
8679 normalize_constant_expr (&imm_expr
);
8684 my_getExpression (&offset_expr
, s
);
8685 *imm_reloc
= BFD_RELOC_32
;
8698 unsigned char temp
[8];
8700 unsigned int length
;
8705 /* These only appear as the last operand in an
8706 instruction, and every instruction that accepts
8707 them in any variant accepts them in all variants.
8708 This means we don't have to worry about backing out
8709 any changes if the instruction does not match.
8711 The difference between them is the size of the
8712 floating point constant and where it goes. For 'F'
8713 and 'L' the constant is 64 bits; for 'f' and 'l' it
8714 is 32 bits. Where the constant is placed is based
8715 on how the MIPS assembler does things:
8718 f -- immediate value
8721 The .lit4 and .lit8 sections are only used if
8722 permitted by the -G argument.
8724 The code below needs to know whether the target register
8725 is 32 or 64 bits wide. It relies on the fact 'f' and
8726 'F' are used with GPR-based instructions and 'l' and
8727 'L' are used with FPR-based instructions. */
8729 f64
= *args
== 'F' || *args
== 'L';
8730 using_gprs
= *args
== 'F' || *args
== 'f';
8732 save_in
= input_line_pointer
;
8733 input_line_pointer
= s
;
8734 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8736 s
= input_line_pointer
;
8737 input_line_pointer
= save_in
;
8738 if (err
!= NULL
&& *err
!= '\0')
8740 as_bad (_("Bad floating point constant: %s"), err
);
8741 memset (temp
, '\0', sizeof temp
);
8742 length
= f64
? 8 : 4;
8745 assert (length
== (unsigned) (f64
? 8 : 4));
8749 && (g_switch_value
< 4
8750 || (temp
[0] == 0 && temp
[1] == 0)
8751 || (temp
[2] == 0 && temp
[3] == 0))))
8753 imm_expr
.X_op
= O_constant
;
8754 if (! target_big_endian
)
8755 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8757 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8760 && ! mips_disable_float_construction
8761 /* Constants can only be constructed in GPRs and
8762 copied to FPRs if the GPRs are at least as wide
8763 as the FPRs. Force the constant into memory if
8764 we are using 64-bit FPRs but the GPRs are only
8767 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8768 && ((temp
[0] == 0 && temp
[1] == 0)
8769 || (temp
[2] == 0 && temp
[3] == 0))
8770 && ((temp
[4] == 0 && temp
[5] == 0)
8771 || (temp
[6] == 0 && temp
[7] == 0)))
8773 /* The value is simple enough to load with a couple of
8774 instructions. If using 32-bit registers, set
8775 imm_expr to the high order 32 bits and offset_expr to
8776 the low order 32 bits. Otherwise, set imm_expr to
8777 the entire 64 bit constant. */
8778 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8780 imm_expr
.X_op
= O_constant
;
8781 offset_expr
.X_op
= O_constant
;
8782 if (! target_big_endian
)
8784 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8785 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8789 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8790 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8792 if (offset_expr
.X_add_number
== 0)
8793 offset_expr
.X_op
= O_absent
;
8795 else if (sizeof (imm_expr
.X_add_number
) > 4)
8797 imm_expr
.X_op
= O_constant
;
8798 if (! target_big_endian
)
8799 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8801 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8805 imm_expr
.X_op
= O_big
;
8806 imm_expr
.X_add_number
= 4;
8807 if (! target_big_endian
)
8809 generic_bignum
[0] = bfd_getl16 (temp
);
8810 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8811 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8812 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8816 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8817 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8818 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8819 generic_bignum
[3] = bfd_getb16 (temp
);
8825 const char *newname
;
8828 /* Switch to the right section. */
8830 subseg
= now_subseg
;
8833 default: /* unused default case avoids warnings. */
8835 newname
= RDATA_SECTION_NAME
;
8836 if (g_switch_value
>= 8)
8840 newname
= RDATA_SECTION_NAME
;
8843 assert (g_switch_value
>= 4);
8847 new_seg
= subseg_new (newname
, (subsegT
) 0);
8848 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8849 bfd_set_section_flags (stdoutput
, new_seg
,
8854 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
8855 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
8856 && strcmp (TARGET_OS
, "elf") != 0)
8857 record_alignment (new_seg
, 4);
8859 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
8861 as_bad (_("Can't use floating point insn in this section"));
8863 /* Set the argument to the current address in the
8865 offset_expr
.X_op
= O_symbol
;
8866 offset_expr
.X_add_symbol
=
8867 symbol_new ("L0\001", now_seg
,
8868 (valueT
) frag_now_fix (), frag_now
);
8869 offset_expr
.X_add_number
= 0;
8871 /* Put the floating point number into the section. */
8872 p
= frag_more ((int) length
);
8873 memcpy (p
, temp
, length
);
8875 /* Switch back to the original section. */
8876 subseg_set (seg
, subseg
);
8881 case 'i': /* 16 bit unsigned immediate */
8882 case 'j': /* 16 bit signed immediate */
8883 *imm_reloc
= BFD_RELOC_LO16
;
8884 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
8887 offsetT minval
, maxval
;
8889 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8890 && strcmp (insn
->name
, insn
[1].name
) == 0);
8892 /* If the expression was written as an unsigned number,
8893 only treat it as signed if there are no more
8897 && sizeof (imm_expr
.X_add_number
) <= 4
8898 && imm_expr
.X_op
== O_constant
8899 && imm_expr
.X_add_number
< 0
8900 && imm_expr
.X_unsigned
8904 /* For compatibility with older assemblers, we accept
8905 0x8000-0xffff as signed 16-bit numbers when only
8906 signed numbers are allowed. */
8908 minval
= 0, maxval
= 0xffff;
8910 minval
= -0x8000, maxval
= 0x7fff;
8912 minval
= -0x8000, maxval
= 0xffff;
8914 if (imm_expr
.X_op
!= O_constant
8915 || imm_expr
.X_add_number
< minval
8916 || imm_expr
.X_add_number
> maxval
)
8920 if (imm_expr
.X_op
== O_constant
8921 || imm_expr
.X_op
== O_big
)
8922 as_bad (_("expression out of range"));
8928 case 'o': /* 16 bit offset */
8929 /* Check whether there is only a single bracketed expression
8930 left. If so, it must be the base register and the
8931 constant must be zero. */
8932 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
8934 offset_expr
.X_op
= O_constant
;
8935 offset_expr
.X_add_number
= 0;
8939 /* If this value won't fit into a 16 bit offset, then go
8940 find a macro that will generate the 32 bit offset
8942 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
8943 && (offset_expr
.X_op
!= O_constant
8944 || offset_expr
.X_add_number
>= 0x8000
8945 || offset_expr
.X_add_number
< -0x8000))
8951 case 'p': /* pc relative offset */
8952 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
8953 my_getExpression (&offset_expr
, s
);
8957 case 'u': /* upper 16 bits */
8958 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
8959 && imm_expr
.X_op
== O_constant
8960 && (imm_expr
.X_add_number
< 0
8961 || imm_expr
.X_add_number
>= 0x10000))
8962 as_bad (_("lui expression not in range 0..65535"));
8966 case 'a': /* 26 bit address */
8967 my_getExpression (&offset_expr
, s
);
8969 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
8972 case 'N': /* 3 bit branch condition code */
8973 case 'M': /* 3 bit compare condition code */
8974 if (strncmp (s
, "$fcc", 4) != 0)
8984 while (ISDIGIT (*s
));
8986 as_bad (_("Invalid condition code register $fcc%d"), regno
);
8987 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
8988 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
8989 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
8990 && (regno
& 1) != 0)
8991 as_warn(_("Condition code register should be even for %s, was %d"),
8993 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
8994 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
8995 && (regno
& 3) != 0)
8996 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
8999 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9001 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9005 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9016 while (ISDIGIT (*s
));
9019 c
= 8; /* Invalid sel value. */
9022 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9023 ip
->insn_opcode
|= c
;
9027 /* Must be at least one digit. */
9028 my_getExpression (&imm_expr
, s
);
9029 check_absolute_expr (ip
, &imm_expr
);
9031 if ((unsigned long) imm_expr
.X_add_number
9032 > (unsigned long) OP_MASK_VECBYTE
)
9034 as_bad (_("bad byte vector index (%ld)"),
9035 (long) imm_expr
.X_add_number
);
9036 imm_expr
.X_add_number
= 0;
9039 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9040 imm_expr
.X_op
= O_absent
;
9045 my_getExpression (&imm_expr
, s
);
9046 check_absolute_expr (ip
, &imm_expr
);
9048 if ((unsigned long) imm_expr
.X_add_number
9049 > (unsigned long) OP_MASK_VECALIGN
)
9051 as_bad (_("bad byte vector index (%ld)"),
9052 (long) imm_expr
.X_add_number
);
9053 imm_expr
.X_add_number
= 0;
9056 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9057 imm_expr
.X_op
= O_absent
;
9062 as_bad (_("bad char = '%c'\n"), *args
);
9067 /* Args don't match. */
9068 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9069 !strcmp (insn
->name
, insn
[1].name
))
9073 insn_error
= _("illegal operands");
9078 insn_error
= _("illegal operands");
9083 /* This routine assembles an instruction into its binary format when
9084 assembling for the mips16. As a side effect, it sets one of the
9085 global variables imm_reloc or offset_reloc to the type of
9086 relocation to do if one of the operands is an address expression.
9087 It also sets mips16_small and mips16_ext if the user explicitly
9088 requested a small or extended instruction. */
9091 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9095 struct mips_opcode
*insn
;
9098 unsigned int lastregno
= 0;
9103 mips16_small
= FALSE
;
9106 for (s
= str
; ISLOWER (*s
); ++s
)
9118 if (s
[1] == 't' && s
[2] == ' ')
9121 mips16_small
= TRUE
;
9125 else if (s
[1] == 'e' && s
[2] == ' ')
9134 insn_error
= _("unknown opcode");
9138 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9139 mips16_small
= TRUE
;
9141 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9143 insn_error
= _("unrecognized opcode");
9150 assert (strcmp (insn
->name
, str
) == 0);
9153 ip
->insn_opcode
= insn
->match
;
9154 ip
->use_extend
= FALSE
;
9155 imm_expr
.X_op
= O_absent
;
9156 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9157 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9158 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9159 imm2_expr
.X_op
= O_absent
;
9160 offset_expr
.X_op
= O_absent
;
9161 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9162 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9163 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9164 for (args
= insn
->args
; 1; ++args
)
9171 /* In this switch statement we call break if we did not find
9172 a match, continue if we did find a match, or return if we
9181 /* Stuff the immediate value in now, if we can. */
9182 if (imm_expr
.X_op
== O_constant
9183 && *imm_reloc
> BFD_RELOC_UNUSED
9184 && insn
->pinfo
!= INSN_MACRO
)
9186 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9187 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9188 mips16_ext
, &ip
->insn_opcode
,
9189 &ip
->use_extend
, &ip
->extend
);
9190 imm_expr
.X_op
= O_absent
;
9191 *imm_reloc
= BFD_RELOC_UNUSED
;
9205 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9208 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9224 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9226 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9253 while (ISDIGIT (*s
));
9256 as_bad (_("invalid register number (%d)"), regno
);
9262 if (s
[1] == 'r' && s
[2] == 'a')
9267 else if (s
[1] == 'f' && s
[2] == 'p')
9272 else if (s
[1] == 's' && s
[2] == 'p')
9277 else if (s
[1] == 'g' && s
[2] == 'p')
9282 else if (s
[1] == 'a' && s
[2] == 't')
9287 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9292 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9297 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9310 if (c
== 'v' || c
== 'w')
9312 regno
= mips16_to_32_reg_map
[lastregno
];
9326 regno
= mips32_to_16_reg_map
[regno
];
9331 regno
= ILLEGAL_REG
;
9336 regno
= ILLEGAL_REG
;
9341 regno
= ILLEGAL_REG
;
9346 if (regno
== AT
&& ! mips_opts
.noat
)
9347 as_warn (_("used $at without \".set noat\""));
9354 if (regno
== ILLEGAL_REG
)
9361 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9365 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9368 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9371 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9377 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9380 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9381 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9391 if (strncmp (s
, "$pc", 3) == 0)
9415 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9417 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9418 and generate the appropriate reloc. If the text
9419 inside %gprel is not a symbol name with an
9420 optional offset, then we generate a normal reloc
9421 and will probably fail later. */
9422 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9423 if (imm_expr
.X_op
== O_symbol
)
9426 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9428 ip
->use_extend
= TRUE
;
9435 /* Just pick up a normal expression. */
9436 my_getExpression (&imm_expr
, s
);
9439 if (imm_expr
.X_op
== O_register
)
9441 /* What we thought was an expression turned out to
9444 if (s
[0] == '(' && args
[1] == '(')
9446 /* It looks like the expression was omitted
9447 before a register indirection, which means
9448 that the expression is implicitly zero. We
9449 still set up imm_expr, so that we handle
9450 explicit extensions correctly. */
9451 imm_expr
.X_op
= O_constant
;
9452 imm_expr
.X_add_number
= 0;
9453 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9460 /* We need to relax this instruction. */
9461 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9470 /* We use offset_reloc rather than imm_reloc for the PC
9471 relative operands. This lets macros with both
9472 immediate and address operands work correctly. */
9473 my_getExpression (&offset_expr
, s
);
9475 if (offset_expr
.X_op
== O_register
)
9478 /* We need to relax this instruction. */
9479 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9483 case '6': /* break code */
9484 my_getExpression (&imm_expr
, s
);
9485 check_absolute_expr (ip
, &imm_expr
);
9486 if ((unsigned long) imm_expr
.X_add_number
> 63)
9488 as_warn (_("Invalid value for `%s' (%lu)"),
9490 (unsigned long) imm_expr
.X_add_number
);
9491 imm_expr
.X_add_number
&= 0x3f;
9493 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9494 imm_expr
.X_op
= O_absent
;
9498 case 'a': /* 26 bit address */
9499 my_getExpression (&offset_expr
, s
);
9501 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9502 ip
->insn_opcode
<<= 16;
9505 case 'l': /* register list for entry macro */
9506 case 'L': /* register list for exit macro */
9516 int freg
, reg1
, reg2
;
9518 while (*s
== ' ' || *s
== ',')
9522 as_bad (_("can't parse register list"));
9534 while (ISDIGIT (*s
))
9556 as_bad (_("invalid register list"));
9561 while (ISDIGIT (*s
))
9568 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9573 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9578 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9579 mask
|= (reg2
- 3) << 3;
9580 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9581 mask
|= (reg2
- 15) << 1;
9582 else if (reg1
== RA
&& reg2
== RA
)
9586 as_bad (_("invalid register list"));
9590 /* The mask is filled in in the opcode table for the
9591 benefit of the disassembler. We remove it before
9592 applying the actual mask. */
9593 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9594 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9598 case 'e': /* extend code */
9599 my_getExpression (&imm_expr
, s
);
9600 check_absolute_expr (ip
, &imm_expr
);
9601 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9603 as_warn (_("Invalid value for `%s' (%lu)"),
9605 (unsigned long) imm_expr
.X_add_number
);
9606 imm_expr
.X_add_number
&= 0x7ff;
9608 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9609 imm_expr
.X_op
= O_absent
;
9619 /* Args don't match. */
9620 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9621 strcmp (insn
->name
, insn
[1].name
) == 0)
9628 insn_error
= _("illegal operands");
9634 /* This structure holds information we know about a mips16 immediate
9637 struct mips16_immed_operand
9639 /* The type code used in the argument string in the opcode table. */
9641 /* The number of bits in the short form of the opcode. */
9643 /* The number of bits in the extended form of the opcode. */
9645 /* The amount by which the short form is shifted when it is used;
9646 for example, the sw instruction has a shift count of 2. */
9648 /* The amount by which the short form is shifted when it is stored
9649 into the instruction code. */
9651 /* Non-zero if the short form is unsigned. */
9653 /* Non-zero if the extended form is unsigned. */
9655 /* Non-zero if the value is PC relative. */
9659 /* The mips16 immediate operand types. */
9661 static const struct mips16_immed_operand mips16_immed_operands
[] =
9663 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9664 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9665 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9666 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9667 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9668 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9669 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9670 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9671 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9672 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9673 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9674 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9675 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9676 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9677 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9678 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9679 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9680 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9681 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9682 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9683 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9686 #define MIPS16_NUM_IMMED \
9687 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9689 /* Handle a mips16 instruction with an immediate value. This or's the
9690 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9691 whether an extended value is needed; if one is needed, it sets
9692 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9693 If SMALL is true, an unextended opcode was explicitly requested.
9694 If EXT is true, an extended opcode was explicitly requested. If
9695 WARN is true, warn if EXT does not match reality. */
9698 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9699 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9700 unsigned long *insn
, bfd_boolean
*use_extend
,
9701 unsigned short *extend
)
9703 register const struct mips16_immed_operand
*op
;
9704 int mintiny
, maxtiny
;
9705 bfd_boolean needext
;
9707 op
= mips16_immed_operands
;
9708 while (op
->type
!= type
)
9711 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9716 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9719 maxtiny
= 1 << op
->nbits
;
9724 maxtiny
= (1 << op
->nbits
) - 1;
9729 mintiny
= - (1 << (op
->nbits
- 1));
9730 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9733 /* Branch offsets have an implicit 0 in the lowest bit. */
9734 if (type
== 'p' || type
== 'q')
9737 if ((val
& ((1 << op
->shift
) - 1)) != 0
9738 || val
< (mintiny
<< op
->shift
)
9739 || val
> (maxtiny
<< op
->shift
))
9744 if (warn
&& ext
&& ! needext
)
9745 as_warn_where (file
, line
,
9746 _("extended operand requested but not required"));
9747 if (small
&& needext
)
9748 as_bad_where (file
, line
, _("invalid unextended operand value"));
9750 if (small
|| (! ext
&& ! needext
))
9754 *use_extend
= FALSE
;
9755 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9756 insnval
<<= op
->op_shift
;
9761 long minext
, maxext
;
9767 maxext
= (1 << op
->extbits
) - 1;
9771 minext
= - (1 << (op
->extbits
- 1));
9772 maxext
= (1 << (op
->extbits
- 1)) - 1;
9774 if (val
< minext
|| val
> maxext
)
9775 as_bad_where (file
, line
,
9776 _("operand value out of range for instruction"));
9779 if (op
->extbits
== 16)
9781 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9784 else if (op
->extbits
== 15)
9786 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9791 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9795 *extend
= (unsigned short) extval
;
9800 static const struct percent_op_match
9803 bfd_reloc_code_real_type reloc
;
9806 {"%lo", BFD_RELOC_LO16
},
9808 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9809 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9810 {"%call16", BFD_RELOC_MIPS_CALL16
},
9811 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9812 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9813 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9814 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9815 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9816 {"%got", BFD_RELOC_MIPS_GOT16
},
9817 {"%gp_rel", BFD_RELOC_GPREL16
},
9818 {"%half", BFD_RELOC_16
},
9819 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9820 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9821 {"%neg", BFD_RELOC_MIPS_SUB
},
9823 {"%hi", BFD_RELOC_HI16_S
}
9827 /* Return true if *STR points to a relocation operator. When returning true,
9828 move *STR over the operator and store its relocation code in *RELOC.
9829 Leave both *STR and *RELOC alone when returning false. */
9832 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9836 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
9837 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9839 *str
+= strlen (percent_op
[i
].str
);
9840 *reloc
= percent_op
[i
].reloc
;
9842 /* Check whether the output BFD supports this relocation.
9843 If not, issue an error and fall back on something safe. */
9844 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9846 as_bad ("relocation %s isn't supported by the current ABI",
9848 *reloc
= BFD_RELOC_UNUSED
;
9856 /* Parse string STR as a 16-bit relocatable operand. Store the
9857 expression in *EP and the relocations in the array starting
9858 at RELOC. Return the number of relocation operators used.
9860 On exit, EXPR_END points to the first character after the expression. */
9863 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
9866 bfd_reloc_code_real_type reversed_reloc
[3];
9867 size_t reloc_index
, i
;
9868 int crux_depth
, str_depth
;
9871 /* Search for the start of the main expression, recoding relocations
9872 in REVERSED_RELOC. End the loop with CRUX pointing to the start
9873 of the main expression and with CRUX_DEPTH containing the number
9874 of open brackets at that point. */
9881 crux_depth
= str_depth
;
9883 /* Skip over whitespace and brackets, keeping count of the number
9885 while (*str
== ' ' || *str
== '\t' || *str
== '(')
9890 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
9891 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
9893 my_getExpression (ep
, crux
);
9896 /* Match every open bracket. */
9897 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
9902 as_bad ("unclosed '('");
9906 if (reloc_index
!= 0)
9908 prev_reloc_op_frag
= frag_now
;
9909 for (i
= 0; i
< reloc_index
; i
++)
9910 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
9917 my_getExpression (expressionS
*ep
, char *str
)
9922 save_in
= input_line_pointer
;
9923 input_line_pointer
= str
;
9925 expr_end
= input_line_pointer
;
9926 input_line_pointer
= save_in
;
9928 /* If we are in mips16 mode, and this is an expression based on `.',
9929 then we bump the value of the symbol by 1 since that is how other
9930 text symbols are handled. We don't bother to handle complex
9931 expressions, just `.' plus or minus a constant. */
9932 if (mips_opts
.mips16
9933 && ep
->X_op
== O_symbol
9934 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
9935 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
9936 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
9937 && symbol_constant_p (ep
->X_add_symbol
)
9938 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
9939 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
9942 /* Turn a string in input_line_pointer into a floating point constant
9943 of type TYPE, and store the appropriate bytes in *LITP. The number
9944 of LITTLENUMS emitted is stored in *SIZEP. An error message is
9945 returned, or NULL on OK. */
9948 md_atof (int type
, char *litP
, int *sizeP
)
9951 LITTLENUM_TYPE words
[4];
9967 return _("bad call to md_atof");
9970 t
= atof_ieee (input_line_pointer
, type
, words
);
9972 input_line_pointer
= t
;
9976 if (! target_big_endian
)
9978 for (i
= prec
- 1; i
>= 0; i
--)
9980 md_number_to_chars (litP
, words
[i
], 2);
9986 for (i
= 0; i
< prec
; i
++)
9988 md_number_to_chars (litP
, words
[i
], 2);
9997 md_number_to_chars (char *buf
, valueT val
, int n
)
9999 if (target_big_endian
)
10000 number_to_chars_bigendian (buf
, val
, n
);
10002 number_to_chars_littleendian (buf
, val
, n
);
10006 static int support_64bit_objects(void)
10008 const char **list
, **l
;
10011 list
= bfd_target_list ();
10012 for (l
= list
; *l
!= NULL
; l
++)
10014 /* This is traditional mips */
10015 if (strcmp (*l
, "elf64-tradbigmips") == 0
10016 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10018 if (strcmp (*l
, "elf64-bigmips") == 0
10019 || strcmp (*l
, "elf64-littlemips") == 0)
10022 yes
= (*l
!= NULL
);
10026 #endif /* OBJ_ELF */
10028 const char *md_shortopts
= "O::g::G:";
10030 struct option md_longopts
[] =
10032 /* Options which specify architecture. */
10033 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10034 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10035 {"march", required_argument
, NULL
, OPTION_MARCH
},
10036 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10037 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10038 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10039 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10040 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10041 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10042 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10043 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10044 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10045 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10046 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10047 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10048 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10049 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10050 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10051 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10052 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10053 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10054 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10055 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10056 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10058 /* Options which specify Application Specific Extensions (ASEs). */
10059 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10060 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10061 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10062 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10063 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10064 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10065 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10066 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10067 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10068 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10069 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10070 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10071 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10073 /* Old-style architecture options. Don't add more of these. */
10074 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10075 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10076 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10077 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10078 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10079 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10080 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10081 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10082 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10083 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10084 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10085 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10086 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10087 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10088 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10089 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10090 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10092 /* Options which enable bug fixes. */
10093 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10094 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10095 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10096 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10097 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10098 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10099 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10100 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10101 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10102 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10104 /* Miscellaneous options. */
10105 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10106 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
10107 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10108 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10109 #define OPTION_BREAK (OPTION_MISC_BASE + 1)
10110 {"break", no_argument
, NULL
, OPTION_BREAK
},
10111 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10112 #define OPTION_EB (OPTION_MISC_BASE + 2)
10113 {"EB", no_argument
, NULL
, OPTION_EB
},
10114 #define OPTION_EL (OPTION_MISC_BASE + 3)
10115 {"EL", no_argument
, NULL
, OPTION_EL
},
10116 #define OPTION_FP32 (OPTION_MISC_BASE + 4)
10117 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10118 #define OPTION_GP32 (OPTION_MISC_BASE + 5)
10119 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10120 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10121 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10122 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10123 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10124 #define OPTION_FP64 (OPTION_MISC_BASE + 8)
10125 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10126 #define OPTION_GP64 (OPTION_MISC_BASE + 9)
10127 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10128 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10129 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10130 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10131 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10132 #define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10133 #define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10134 {"mshared", no_argument
, NULL
, OPTION_MSHARED
},
10135 {"mno-shared", no_argument
, NULL
, OPTION_MNO_SHARED
},
10137 /* ELF-specific options. */
10139 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 14)
10140 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10141 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10142 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10143 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10144 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10145 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10146 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10147 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10148 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10149 #define OPTION_32 (OPTION_ELF_BASE + 4)
10150 {"32", no_argument
, NULL
, OPTION_32
},
10151 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10152 {"n32", no_argument
, NULL
, OPTION_N32
},
10153 #define OPTION_64 (OPTION_ELF_BASE + 6)
10154 {"64", no_argument
, NULL
, OPTION_64
},
10155 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10156 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10157 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10158 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10159 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10160 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10161 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10162 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10163 #endif /* OBJ_ELF */
10165 {NULL
, no_argument
, NULL
, 0}
10167 size_t md_longopts_size
= sizeof (md_longopts
);
10169 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10170 NEW_VALUE. Warn if another value was already specified. Note:
10171 we have to defer parsing the -march and -mtune arguments in order
10172 to handle 'from-abi' correctly, since the ABI might be specified
10173 in a later argument. */
10176 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10178 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10179 as_warn (_("A different %s was already specified, is now %s"),
10180 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10183 *string_ptr
= new_value
;
10187 md_parse_option (int c
, char *arg
)
10191 case OPTION_CONSTRUCT_FLOATS
:
10192 mips_disable_float_construction
= 0;
10195 case OPTION_NO_CONSTRUCT_FLOATS
:
10196 mips_disable_float_construction
= 1;
10208 target_big_endian
= 1;
10212 target_big_endian
= 0;
10216 if (arg
&& arg
[1] == '0')
10226 mips_debug
= atoi (arg
);
10227 /* When the MIPS assembler sees -g or -g2, it does not do
10228 optimizations which limit full symbolic debugging. We take
10229 that to be equivalent to -O0. */
10230 if (mips_debug
== 2)
10235 file_mips_isa
= ISA_MIPS1
;
10239 file_mips_isa
= ISA_MIPS2
;
10243 file_mips_isa
= ISA_MIPS3
;
10247 file_mips_isa
= ISA_MIPS4
;
10251 file_mips_isa
= ISA_MIPS5
;
10254 case OPTION_MIPS32
:
10255 file_mips_isa
= ISA_MIPS32
;
10258 case OPTION_MIPS32R2
:
10259 file_mips_isa
= ISA_MIPS32R2
;
10262 case OPTION_MIPS64R2
:
10263 file_mips_isa
= ISA_MIPS64R2
;
10266 case OPTION_MIPS64
:
10267 file_mips_isa
= ISA_MIPS64
;
10271 mips_set_option_string (&mips_tune_string
, arg
);
10275 mips_set_option_string (&mips_arch_string
, arg
);
10279 mips_set_option_string (&mips_arch_string
, "4650");
10280 mips_set_option_string (&mips_tune_string
, "4650");
10283 case OPTION_NO_M4650
:
10287 mips_set_option_string (&mips_arch_string
, "4010");
10288 mips_set_option_string (&mips_tune_string
, "4010");
10291 case OPTION_NO_M4010
:
10295 mips_set_option_string (&mips_arch_string
, "4100");
10296 mips_set_option_string (&mips_tune_string
, "4100");
10299 case OPTION_NO_M4100
:
10303 mips_set_option_string (&mips_arch_string
, "3900");
10304 mips_set_option_string (&mips_tune_string
, "3900");
10307 case OPTION_NO_M3900
:
10311 mips_opts
.ase_mdmx
= 1;
10314 case OPTION_NO_MDMX
:
10315 mips_opts
.ase_mdmx
= 0;
10318 case OPTION_MIPS16
:
10319 mips_opts
.mips16
= 1;
10320 mips_no_prev_insn (FALSE
);
10323 case OPTION_NO_MIPS16
:
10324 mips_opts
.mips16
= 0;
10325 mips_no_prev_insn (FALSE
);
10328 case OPTION_MIPS3D
:
10329 mips_opts
.ase_mips3d
= 1;
10332 case OPTION_NO_MIPS3D
:
10333 mips_opts
.ase_mips3d
= 0;
10336 case OPTION_FIX_VR4120
:
10337 mips_fix_vr4120
= 1;
10340 case OPTION_NO_FIX_VR4120
:
10341 mips_fix_vr4120
= 0;
10344 case OPTION_RELAX_BRANCH
:
10345 mips_relax_branch
= 1;
10348 case OPTION_NO_RELAX_BRANCH
:
10349 mips_relax_branch
= 0;
10352 case OPTION_MSHARED
:
10353 mips_in_shared
= TRUE
;
10356 case OPTION_MNO_SHARED
:
10357 mips_in_shared
= FALSE
;
10361 /* When generating ELF code, we permit -KPIC and -call_shared to
10362 select SVR4_PIC, and -non_shared to select no PIC. This is
10363 intended to be compatible with Irix 5. */
10364 case OPTION_CALL_SHARED
:
10365 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10367 as_bad (_("-call_shared is supported only for ELF format"));
10370 mips_pic
= SVR4_PIC
;
10371 mips_abicalls
= TRUE
;
10372 if (g_switch_seen
&& g_switch_value
!= 0)
10374 as_bad (_("-G may not be used with SVR4 PIC code"));
10377 g_switch_value
= 0;
10380 case OPTION_NON_SHARED
:
10381 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10383 as_bad (_("-non_shared is supported only for ELF format"));
10387 mips_abicalls
= FALSE
;
10390 /* The -xgot option tells the assembler to use 32 offsets when
10391 accessing the got in SVR4_PIC mode. It is for Irix
10396 #endif /* OBJ_ELF */
10399 if (mips_pic
== SVR4_PIC
)
10401 as_bad (_("-G may not be used with SVR4 PIC code"));
10405 g_switch_value
= atoi (arg
);
10410 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10413 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10415 as_bad (_("-32 is supported for ELF format only"));
10418 mips_abi
= O32_ABI
;
10422 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10424 as_bad (_("-n32 is supported for ELF format only"));
10427 mips_abi
= N32_ABI
;
10431 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10433 as_bad (_("-64 is supported for ELF format only"));
10436 mips_abi
= N64_ABI
;
10437 if (! support_64bit_objects())
10438 as_fatal (_("No compiled in support for 64 bit object file format"));
10440 #endif /* OBJ_ELF */
10443 file_mips_gp32
= 1;
10447 file_mips_gp32
= 0;
10451 file_mips_fp32
= 1;
10455 file_mips_fp32
= 0;
10460 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10462 as_bad (_("-mabi is supported for ELF format only"));
10465 if (strcmp (arg
, "32") == 0)
10466 mips_abi
= O32_ABI
;
10467 else if (strcmp (arg
, "o64") == 0)
10468 mips_abi
= O64_ABI
;
10469 else if (strcmp (arg
, "n32") == 0)
10470 mips_abi
= N32_ABI
;
10471 else if (strcmp (arg
, "64") == 0)
10473 mips_abi
= N64_ABI
;
10474 if (! support_64bit_objects())
10475 as_fatal (_("No compiled in support for 64 bit object file "
10478 else if (strcmp (arg
, "eabi") == 0)
10479 mips_abi
= EABI_ABI
;
10482 as_fatal (_("invalid abi -mabi=%s"), arg
);
10486 #endif /* OBJ_ELF */
10488 case OPTION_M7000_HILO_FIX
:
10489 mips_7000_hilo_fix
= TRUE
;
10492 case OPTION_MNO_7000_HILO_FIX
:
10493 mips_7000_hilo_fix
= FALSE
;
10497 case OPTION_MDEBUG
:
10498 mips_flag_mdebug
= TRUE
;
10501 case OPTION_NO_MDEBUG
:
10502 mips_flag_mdebug
= FALSE
;
10506 mips_flag_pdr
= TRUE
;
10509 case OPTION_NO_PDR
:
10510 mips_flag_pdr
= FALSE
;
10512 #endif /* OBJ_ELF */
10521 /* Set up globals to generate code for the ISA or processor
10522 described by INFO. */
10525 mips_set_architecture (const struct mips_cpu_info
*info
)
10529 file_mips_arch
= info
->cpu
;
10530 mips_opts
.arch
= info
->cpu
;
10531 mips_opts
.isa
= info
->isa
;
10536 /* Likewise for tuning. */
10539 mips_set_tune (const struct mips_cpu_info
*info
)
10542 mips_tune
= info
->cpu
;
10547 mips_after_parse_args (void)
10549 const struct mips_cpu_info
*arch_info
= 0;
10550 const struct mips_cpu_info
*tune_info
= 0;
10552 /* GP relative stuff not working for PE */
10553 if (strncmp (TARGET_OS
, "pe", 2) == 0
10554 && g_switch_value
!= 0)
10557 as_bad (_("-G not supported in this configuration."));
10558 g_switch_value
= 0;
10561 if (mips_abi
== NO_ABI
)
10562 mips_abi
= MIPS_DEFAULT_ABI
;
10564 /* The following code determines the architecture and register size.
10565 Similar code was added to GCC 3.3 (see override_options() in
10566 config/mips/mips.c). The GAS and GCC code should be kept in sync
10567 as much as possible. */
10569 if (mips_arch_string
!= 0)
10570 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10572 if (file_mips_isa
!= ISA_UNKNOWN
)
10574 /* Handle -mipsN. At this point, file_mips_isa contains the
10575 ISA level specified by -mipsN, while arch_info->isa contains
10576 the -march selection (if any). */
10577 if (arch_info
!= 0)
10579 /* -march takes precedence over -mipsN, since it is more descriptive.
10580 There's no harm in specifying both as long as the ISA levels
10582 if (file_mips_isa
!= arch_info
->isa
)
10583 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10584 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10585 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10588 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10591 if (arch_info
== 0)
10592 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10594 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10595 as_bad ("-march=%s is not compatible with the selected ABI",
10598 mips_set_architecture (arch_info
);
10600 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10601 if (mips_tune_string
!= 0)
10602 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10604 if (tune_info
== 0)
10605 mips_set_tune (arch_info
);
10607 mips_set_tune (tune_info
);
10609 if (file_mips_gp32
>= 0)
10611 /* The user specified the size of the integer registers. Make sure
10612 it agrees with the ABI and ISA. */
10613 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10614 as_bad (_("-mgp64 used with a 32-bit processor"));
10615 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10616 as_bad (_("-mgp32 used with a 64-bit ABI"));
10617 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10618 as_bad (_("-mgp64 used with a 32-bit ABI"));
10622 /* Infer the integer register size from the ABI and processor.
10623 Restrict ourselves to 32-bit registers if that's all the
10624 processor has, or if the ABI cannot handle 64-bit registers. */
10625 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10626 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10629 /* ??? GAS treats single-float processors as though they had 64-bit
10630 float registers (although it complains when double-precision
10631 instructions are used). As things stand, saying they have 32-bit
10632 registers would lead to spurious "register must be even" messages.
10633 So here we assume float registers are always the same size as
10634 integer ones, unless the user says otherwise. */
10635 if (file_mips_fp32
< 0)
10636 file_mips_fp32
= file_mips_gp32
;
10638 /* End of GCC-shared inference code. */
10640 /* This flag is set when we have a 64-bit capable CPU but use only
10641 32-bit wide registers. Note that EABI does not use it. */
10642 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10643 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10644 || mips_abi
== O32_ABI
))
10645 mips_32bitmode
= 1;
10647 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10648 as_bad (_("trap exception not supported at ISA 1"));
10650 /* If the selected architecture includes support for ASEs, enable
10651 generation of code for them. */
10652 if (mips_opts
.mips16
== -1)
10653 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10654 if (mips_opts
.ase_mips3d
== -1)
10655 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10656 if (mips_opts
.ase_mdmx
== -1)
10657 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10659 file_mips_isa
= mips_opts
.isa
;
10660 file_ase_mips16
= mips_opts
.mips16
;
10661 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10662 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10663 mips_opts
.gp32
= file_mips_gp32
;
10664 mips_opts
.fp32
= file_mips_fp32
;
10666 if (mips_flag_mdebug
< 0)
10668 #ifdef OBJ_MAYBE_ECOFF
10669 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10670 mips_flag_mdebug
= 1;
10672 #endif /* OBJ_MAYBE_ECOFF */
10673 mips_flag_mdebug
= 0;
10678 mips_init_after_args (void)
10680 /* initialize opcodes */
10681 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10682 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10686 md_pcrel_from (fixS
*fixP
)
10688 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10689 switch (fixP
->fx_r_type
)
10691 case BFD_RELOC_16_PCREL_S2
:
10692 case BFD_RELOC_MIPS_JMP
:
10693 /* Return the address of the delay slot. */
10700 /* This is called before the symbol table is processed. In order to
10701 work with gcc when using mips-tfile, we must keep all local labels.
10702 However, in other cases, we want to discard them. If we were
10703 called with -g, but we didn't see any debugging information, it may
10704 mean that gcc is smuggling debugging information through to
10705 mips-tfile, in which case we must generate all local labels. */
10708 mips_frob_file_before_adjust (void)
10710 #ifndef NO_ECOFF_DEBUGGING
10711 if (ECOFF_DEBUGGING
10713 && ! ecoff_debugging_seen
)
10714 flag_keep_locals
= 1;
10718 /* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
10719 the corresponding LO16 reloc. This is called before md_apply_fix3 and
10720 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
10721 relocation operators.
10723 For our purposes, a %lo() expression matches a %got() or %hi()
10726 (a) it refers to the same symbol; and
10727 (b) the offset applied in the %lo() expression is no lower than
10728 the offset applied in the %got() or %hi().
10730 (b) allows us to cope with code like:
10733 lh $4,%lo(foo+2)($4)
10735 ...which is legal on RELA targets, and has a well-defined behaviour
10736 if the user knows that adding 2 to "foo" will not induce a carry to
10739 When several %lo()s match a particular %got() or %hi(), we use the
10740 following rules to distinguish them:
10742 (1) %lo()s with smaller offsets are a better match than %lo()s with
10745 (2) %lo()s with no matching %got() or %hi() are better than those
10746 that already have a matching %got() or %hi().
10748 (3) later %lo()s are better than earlier %lo()s.
10750 These rules are applied in order.
10752 (1) means, among other things, that %lo()s with identical offsets are
10753 chosen if they exist.
10755 (2) means that we won't associate several high-part relocations with
10756 the same low-part relocation unless there's no alternative. Having
10757 several high parts for the same low part is a GNU extension; this rule
10758 allows careful users to avoid it.
10760 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
10761 with the last high-part relocation being at the front of the list.
10762 It therefore makes sense to choose the last matching low-part
10763 relocation, all other things being equal. It's also easier
10764 to code that way. */
10767 mips_frob_file (void)
10769 struct mips_hi_fixup
*l
;
10771 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10773 segment_info_type
*seginfo
;
10774 bfd_boolean matched_lo_p
;
10775 fixS
**hi_pos
, **lo_pos
, **pos
;
10777 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10779 /* If a GOT16 relocation turns out to be against a global symbol,
10780 there isn't supposed to be a matching LO. */
10781 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10782 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10785 /* Check quickly whether the next fixup happens to be a matching %lo. */
10786 if (fixup_has_matching_lo_p (l
->fixp
))
10789 seginfo
= seg_info (l
->seg
);
10791 /* Set HI_POS to the position of this relocation in the chain.
10792 Set LO_POS to the position of the chosen low-part relocation.
10793 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
10794 relocation that matches an immediately-preceding high-part
10798 matched_lo_p
= FALSE
;
10799 for (pos
= &seginfo
->fix_root
; *pos
!= NULL
; pos
= &(*pos
)->fx_next
)
10801 if (*pos
== l
->fixp
)
10804 if ((*pos
)->fx_r_type
== BFD_RELOC_LO16
10805 && (*pos
)->fx_addsy
== l
->fixp
->fx_addsy
10806 && (*pos
)->fx_offset
>= l
->fixp
->fx_offset
10808 || (*pos
)->fx_offset
< (*lo_pos
)->fx_offset
10810 && (*pos
)->fx_offset
== (*lo_pos
)->fx_offset
)))
10813 matched_lo_p
= (reloc_needs_lo_p ((*pos
)->fx_r_type
)
10814 && fixup_has_matching_lo_p (*pos
));
10817 /* If we found a match, remove the high-part relocation from its
10818 current position and insert it before the low-part relocation.
10819 Make the offsets match so that fixup_has_matching_lo_p()
10822 We don't warn about unmatched high-part relocations since some
10823 versions of gcc have been known to emit dead "lui ...%hi(...)"
10825 if (lo_pos
!= NULL
)
10827 l
->fixp
->fx_offset
= (*lo_pos
)->fx_offset
;
10828 if (l
->fixp
->fx_next
!= *lo_pos
)
10830 *hi_pos
= l
->fixp
->fx_next
;
10831 l
->fixp
->fx_next
= *lo_pos
;
10838 /* We may have combined relocations without symbols in the N32/N64 ABI.
10839 We have to prevent gas from dropping them. */
10842 mips_force_relocation (fixS
*fixp
)
10844 if (generic_force_reloc (fixp
))
10848 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10849 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10850 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10851 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10857 /* This hook is called before a fix is simplified. We don't really
10858 decide whether to skip a fix here. Rather, we turn global symbols
10859 used as branch targets into local symbols, such that they undergo
10860 simplification. We can only do this if the symbol is defined and
10861 it is in the same section as the branch. If this doesn't hold, we
10862 emit a better error message than just saying the relocation is not
10863 valid for the selected object format.
10865 FIXP is the fix-up we're going to try to simplify, SEG is the
10866 segment in which the fix up occurs. The return value should be
10867 non-zero to indicate the fix-up is valid for further
10868 simplifications. */
10871 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
10873 /* There's a lot of discussion on whether it should be possible to
10874 use R_MIPS_PC16 to represent branch relocations. The outcome
10875 seems to be that it can, but gas/bfd are very broken in creating
10876 RELA relocations for this, so for now we only accept branches to
10877 symbols in the same section. Anything else is of dubious value,
10878 since there's no guarantee that at link time the symbol would be
10879 in range. Even for branches to local symbols this is arguably
10880 wrong, since it we assume the symbol is not going to be
10881 overridden, which should be possible per ELF library semantics,
10882 but then, there isn't a dynamic relocation that could be used to
10883 this effect, and the target would likely be out of range as well.
10885 Unfortunately, it seems that there is too much code out there
10886 that relies on branches to symbols that are global to be resolved
10887 as if they were local, like the IRIX tools do, so we do it as
10888 well, but with a warning so that people are reminded to fix their
10889 code. If we ever get back to using R_MIPS_PC16 for branch
10890 targets, this entire block should go away (and probably the
10891 whole function). */
10893 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
10894 && ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10895 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10896 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
10899 if (! S_IS_DEFINED (fixP
->fx_addsy
))
10901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10902 _("Cannot branch to undefined symbol."));
10903 /* Avoid any further errors about this fixup. */
10906 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
10908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
10909 _("Cannot branch to symbol in another section."));
10912 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
10914 symbolS
*sym
= fixP
->fx_addsy
;
10916 if (mips_pic
== SVR4_PIC
)
10917 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
10918 _("Pretending global symbol used as branch target is local."));
10920 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
10921 S_GET_SEGMENT (sym
),
10923 symbol_get_frag (sym
));
10924 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
10925 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
10926 assert (symbol_resolved_p (sym
));
10927 symbol_mark_resolved (fixP
->fx_addsy
);
10934 /* Apply a fixup to the object file. */
10937 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
10941 reloc_howto_type
*howto
;
10943 /* We ignore generic BFD relocations we don't know about. */
10944 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
10948 assert (fixP
->fx_size
== 4
10949 || fixP
->fx_r_type
== BFD_RELOC_16
10950 || fixP
->fx_r_type
== BFD_RELOC_64
10951 || fixP
->fx_r_type
== BFD_RELOC_CTOR
10952 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
10953 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
10954 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
10956 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
10958 assert (! fixP
->fx_pcrel
);
10960 /* Don't treat parts of a composite relocation as done. There are two
10963 (1) The second and third parts will be against 0 (RSS_UNDEF) but
10964 should nevertheless be emitted if the first part is.
10966 (2) In normal usage, composite relocations are never assembly-time
10967 constants. The easiest way of dealing with the pathological
10968 exceptions is to generate a relocation against STN_UNDEF and
10969 leave everything up to the linker. */
10970 if (fixP
->fx_addsy
== NULL
&& fixP
->fx_tcbit
== 0)
10973 switch (fixP
->fx_r_type
)
10975 case BFD_RELOC_MIPS_JMP
:
10976 case BFD_RELOC_MIPS_SHIFT5
:
10977 case BFD_RELOC_MIPS_SHIFT6
:
10978 case BFD_RELOC_MIPS_GOT_DISP
:
10979 case BFD_RELOC_MIPS_GOT_PAGE
:
10980 case BFD_RELOC_MIPS_GOT_OFST
:
10981 case BFD_RELOC_MIPS_SUB
:
10982 case BFD_RELOC_MIPS_INSERT_A
:
10983 case BFD_RELOC_MIPS_INSERT_B
:
10984 case BFD_RELOC_MIPS_DELETE
:
10985 case BFD_RELOC_MIPS_HIGHEST
:
10986 case BFD_RELOC_MIPS_HIGHER
:
10987 case BFD_RELOC_MIPS_SCN_DISP
:
10988 case BFD_RELOC_MIPS_REL16
:
10989 case BFD_RELOC_MIPS_RELGOT
:
10990 case BFD_RELOC_MIPS_JALR
:
10991 case BFD_RELOC_HI16
:
10992 case BFD_RELOC_HI16_S
:
10993 case BFD_RELOC_GPREL16
:
10994 case BFD_RELOC_MIPS_LITERAL
:
10995 case BFD_RELOC_MIPS_CALL16
:
10996 case BFD_RELOC_MIPS_GOT16
:
10997 case BFD_RELOC_GPREL32
:
10998 case BFD_RELOC_MIPS_GOT_HI16
:
10999 case BFD_RELOC_MIPS_GOT_LO16
:
11000 case BFD_RELOC_MIPS_CALL_HI16
:
11001 case BFD_RELOC_MIPS_CALL_LO16
:
11002 case BFD_RELOC_MIPS16_GPREL
:
11003 assert (! fixP
->fx_pcrel
);
11004 /* Nothing needed to do. The value comes from the reloc entry */
11007 case BFD_RELOC_MIPS16_JMP
:
11008 /* We currently always generate a reloc against a symbol, which
11009 means that we don't want an addend even if the symbol is
11015 /* This is handled like BFD_RELOC_32, but we output a sign
11016 extended value if we are only 32 bits. */
11019 if (8 <= sizeof (valueT
))
11020 md_number_to_chars (buf
, *valP
, 8);
11025 if ((*valP
& 0x80000000) != 0)
11029 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11031 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11037 case BFD_RELOC_RVA
:
11039 /* If we are deleting this reloc entry, we must fill in the
11040 value now. This can happen if we have a .word which is not
11041 resolved when it appears but is later defined. */
11043 md_number_to_chars (buf
, *valP
, 4);
11047 /* If we are deleting this reloc entry, we must fill in the
11050 md_number_to_chars (buf
, *valP
, 2);
11053 case BFD_RELOC_LO16
:
11054 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11055 may be safe to remove, but if so it's not obvious. */
11056 /* When handling an embedded PIC switch statement, we can wind
11057 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11060 if (*valP
+ 0x8000 > 0xffff)
11061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11062 _("relocation overflow"));
11063 if (target_big_endian
)
11065 md_number_to_chars (buf
, *valP
, 2);
11069 case BFD_RELOC_16_PCREL_S2
:
11070 if ((*valP
& 0x3) != 0)
11071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11072 _("Branch to odd address (%lx)"), (long) *valP
);
11075 * We need to save the bits in the instruction since fixup_segment()
11076 * might be deleting the relocation entry (i.e., a branch within
11077 * the current segment).
11079 if (! fixP
->fx_done
)
11082 /* update old instruction data */
11083 if (target_big_endian
)
11084 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11086 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11088 if (*valP
+ 0x20000 <= 0x3ffff)
11090 insn
|= (*valP
>> 2) & 0xffff;
11091 md_number_to_chars (buf
, insn
, 4);
11093 else if (mips_pic
== NO_PIC
11095 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11096 && (fixP
->fx_frag
->fr_address
11097 < text_section
->vma
+ bfd_get_section_size (text_section
))
11098 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11099 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11100 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11102 /* The branch offset is too large. If this is an
11103 unconditional branch, and we are not generating PIC code,
11104 we can convert it to an absolute jump instruction. */
11105 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11106 insn
= 0x0c000000; /* jal */
11108 insn
= 0x08000000; /* j */
11109 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11111 fixP
->fx_addsy
= section_symbol (text_section
);
11112 *valP
+= md_pcrel_from (fixP
);
11113 md_number_to_chars (buf
, insn
, 4);
11117 /* If we got here, we have branch-relaxation disabled,
11118 and there's nothing we can do to fix this instruction
11119 without turning it into a longer sequence. */
11120 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11121 _("Branch out of range"));
11125 case BFD_RELOC_VTABLE_INHERIT
:
11128 && !S_IS_DEFINED (fixP
->fx_addsy
)
11129 && !S_IS_WEAK (fixP
->fx_addsy
))
11130 S_SET_WEAK (fixP
->fx_addsy
);
11133 case BFD_RELOC_VTABLE_ENTRY
:
11141 /* Remember value for tc_gen_reloc. */
11142 fixP
->fx_addnumber
= *valP
;
11147 printInsn (unsigned long oc
)
11149 const struct mips_opcode
*p
;
11150 int treg
, sreg
, dreg
, shamt
;
11155 for (i
= 0; i
< NUMOPCODES
; ++i
)
11157 p
= &mips_opcodes
[i
];
11158 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11160 printf ("%08lx %s\t", oc
, p
->name
);
11161 treg
= (oc
>> 16) & 0x1f;
11162 sreg
= (oc
>> 21) & 0x1f;
11163 dreg
= (oc
>> 11) & 0x1f;
11164 shamt
= (oc
>> 6) & 0x1f;
11166 for (args
= p
->args
;; ++args
)
11177 printf ("%c", *args
);
11181 assert (treg
== sreg
);
11182 printf ("$%d,$%d", treg
, sreg
);
11187 printf ("$%d", dreg
);
11192 printf ("$%d", treg
);
11196 printf ("0x%x", treg
);
11201 printf ("$%d", sreg
);
11205 printf ("0x%08lx", oc
& 0x1ffffff);
11212 printf ("%d", imm
);
11217 printf ("$%d", shamt
);
11228 printf (_("%08lx UNDEFINED\n"), oc
);
11239 name
= input_line_pointer
;
11240 c
= get_symbol_end ();
11241 p
= (symbolS
*) symbol_find_or_make (name
);
11242 *input_line_pointer
= c
;
11246 /* Align the current frag to a given power of two. The MIPS assembler
11247 also automatically adjusts any preceding label. */
11250 mips_align (int to
, int fill
, symbolS
*label
)
11252 mips_emit_delays (FALSE
);
11253 frag_align (to
, fill
, 0);
11254 record_alignment (now_seg
, to
);
11257 assert (S_GET_SEGMENT (label
) == now_seg
);
11258 symbol_set_frag (label
, frag_now
);
11259 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11263 /* Align to a given power of two. .align 0 turns off the automatic
11264 alignment used by the data creating pseudo-ops. */
11267 s_align (int x ATTRIBUTE_UNUSED
)
11270 register long temp_fill
;
11271 long max_alignment
= 15;
11275 o Note that the assembler pulls down any immediately preceding label
11276 to the aligned address.
11277 o It's not documented but auto alignment is reinstated by
11278 a .align pseudo instruction.
11279 o Note also that after auto alignment is turned off the mips assembler
11280 issues an error on attempt to assemble an improperly aligned data item.
11285 temp
= get_absolute_expression ();
11286 if (temp
> max_alignment
)
11287 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11290 as_warn (_("Alignment negative: 0 assumed."));
11293 if (*input_line_pointer
== ',')
11295 ++input_line_pointer
;
11296 temp_fill
= get_absolute_expression ();
11303 mips_align (temp
, (int) temp_fill
,
11304 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11311 demand_empty_rest_of_line ();
11315 mips_flush_pending_output (void)
11317 mips_emit_delays (FALSE
);
11318 mips_clear_insn_labels ();
11322 s_change_sec (int sec
)
11327 /* The ELF backend needs to know that we are changing sections, so
11328 that .previous works correctly. We could do something like check
11329 for an obj_section_change_hook macro, but that might be confusing
11330 as it would not be appropriate to use it in the section changing
11331 functions in read.c, since obj-elf.c intercepts those. FIXME:
11332 This should be cleaner, somehow. */
11333 obj_elf_section_change_hook ();
11336 mips_emit_delays (FALSE
);
11346 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11347 demand_empty_rest_of_line ();
11351 seg
= subseg_new (RDATA_SECTION_NAME
,
11352 (subsegT
) get_absolute_expression ());
11353 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11355 bfd_set_section_flags (stdoutput
, seg
, (SEC_ALLOC
| SEC_LOAD
11356 | SEC_READONLY
| SEC_RELOC
11358 if (strcmp (TARGET_OS
, "elf") != 0)
11359 record_alignment (seg
, 4);
11361 demand_empty_rest_of_line ();
11365 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11366 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11368 bfd_set_section_flags (stdoutput
, seg
,
11369 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
11370 if (strcmp (TARGET_OS
, "elf") != 0)
11371 record_alignment (seg
, 4);
11373 demand_empty_rest_of_line ();
11381 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11384 char *section_name
;
11389 int section_entry_size
;
11390 int section_alignment
;
11392 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11395 section_name
= input_line_pointer
;
11396 c
= get_symbol_end ();
11398 next_c
= *(input_line_pointer
+ 1);
11400 /* Do we have .section Name<,"flags">? */
11401 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11403 /* just after name is now '\0'. */
11404 *input_line_pointer
= c
;
11405 input_line_pointer
= section_name
;
11406 obj_elf_section (ignore
);
11409 input_line_pointer
++;
11411 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11413 section_type
= get_absolute_expression ();
11416 if (*input_line_pointer
++ == ',')
11417 section_flag
= get_absolute_expression ();
11420 if (*input_line_pointer
++ == ',')
11421 section_entry_size
= get_absolute_expression ();
11423 section_entry_size
= 0;
11424 if (*input_line_pointer
++ == ',')
11425 section_alignment
= get_absolute_expression ();
11427 section_alignment
= 0;
11429 section_name
= xstrdup (section_name
);
11431 /* When using the generic form of .section (as implemented by obj-elf.c),
11432 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11433 traditionally had to fall back on the more common @progbits instead.
11435 There's nothing really harmful in this, since bfd will correct
11436 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11437 means that, for backwards compatibiltiy, the special_section entries
11438 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11440 Even so, we shouldn't force users of the MIPS .section syntax to
11441 incorrectly label the sections as SHT_PROGBITS. The best compromise
11442 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11443 generic type-checking code. */
11444 if (section_type
== SHT_MIPS_DWARF
)
11445 section_type
= SHT_PROGBITS
;
11447 obj_elf_change_section (section_name
, section_type
, section_flag
,
11448 section_entry_size
, 0, 0, 0);
11450 if (now_seg
->name
!= section_name
)
11451 free (section_name
);
11452 #endif /* OBJ_ELF */
11456 mips_enable_auto_align (void)
11462 s_cons (int log_size
)
11466 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11467 mips_emit_delays (FALSE
);
11468 if (log_size
> 0 && auto_align
)
11469 mips_align (log_size
, 0, label
);
11470 mips_clear_insn_labels ();
11471 cons (1 << log_size
);
11475 s_float_cons (int type
)
11479 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11481 mips_emit_delays (FALSE
);
11486 mips_align (3, 0, label
);
11488 mips_align (2, 0, label
);
11491 mips_clear_insn_labels ();
11496 /* Handle .globl. We need to override it because on Irix 5 you are
11499 where foo is an undefined symbol, to mean that foo should be
11500 considered to be the address of a function. */
11503 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11510 name
= input_line_pointer
;
11511 c
= get_symbol_end ();
11512 symbolP
= symbol_find_or_make (name
);
11513 *input_line_pointer
= c
;
11514 SKIP_WHITESPACE ();
11516 /* On Irix 5, every global symbol that is not explicitly labelled as
11517 being a function is apparently labelled as being an object. */
11520 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11525 secname
= input_line_pointer
;
11526 c
= get_symbol_end ();
11527 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11529 as_bad (_("%s: no such section"), secname
);
11530 *input_line_pointer
= c
;
11532 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11533 flag
= BSF_FUNCTION
;
11536 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11538 S_SET_EXTERNAL (symbolP
);
11539 demand_empty_rest_of_line ();
11543 s_option (int x ATTRIBUTE_UNUSED
)
11548 opt
= input_line_pointer
;
11549 c
= get_symbol_end ();
11553 /* FIXME: What does this mean? */
11555 else if (strncmp (opt
, "pic", 3) == 0)
11559 i
= atoi (opt
+ 3);
11564 mips_pic
= SVR4_PIC
;
11565 mips_abicalls
= TRUE
;
11568 as_bad (_(".option pic%d not supported"), i
);
11570 if (mips_pic
== SVR4_PIC
)
11572 if (g_switch_seen
&& g_switch_value
!= 0)
11573 as_warn (_("-G may not be used with SVR4 PIC code"));
11574 g_switch_value
= 0;
11575 bfd_set_gp_size (stdoutput
, 0);
11579 as_warn (_("Unrecognized option \"%s\""), opt
);
11581 *input_line_pointer
= c
;
11582 demand_empty_rest_of_line ();
11585 /* This structure is used to hold a stack of .set values. */
11587 struct mips_option_stack
11589 struct mips_option_stack
*next
;
11590 struct mips_set_options options
;
11593 static struct mips_option_stack
*mips_opts_stack
;
11595 /* Handle the .set pseudo-op. */
11598 s_mipsset (int x ATTRIBUTE_UNUSED
)
11600 char *name
= input_line_pointer
, ch
;
11602 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11603 ++input_line_pointer
;
11604 ch
= *input_line_pointer
;
11605 *input_line_pointer
= '\0';
11607 if (strcmp (name
, "reorder") == 0)
11609 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11611 /* If we still have pending nops, we can discard them. The
11612 usual nop handling will insert any that are still
11614 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11615 * (mips_opts
.mips16
? 2 : 4));
11616 prev_nop_frag
= NULL
;
11618 mips_opts
.noreorder
= 0;
11620 else if (strcmp (name
, "noreorder") == 0)
11622 mips_emit_delays (TRUE
);
11623 mips_opts
.noreorder
= 1;
11624 mips_any_noreorder
= 1;
11626 else if (strcmp (name
, "at") == 0)
11628 mips_opts
.noat
= 0;
11630 else if (strcmp (name
, "noat") == 0)
11632 mips_opts
.noat
= 1;
11634 else if (strcmp (name
, "macro") == 0)
11636 mips_opts
.warn_about_macros
= 0;
11638 else if (strcmp (name
, "nomacro") == 0)
11640 if (mips_opts
.noreorder
== 0)
11641 as_bad (_("`noreorder' must be set before `nomacro'"));
11642 mips_opts
.warn_about_macros
= 1;
11644 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11646 mips_opts
.nomove
= 0;
11648 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11650 mips_opts
.nomove
= 1;
11652 else if (strcmp (name
, "bopt") == 0)
11654 mips_opts
.nobopt
= 0;
11656 else if (strcmp (name
, "nobopt") == 0)
11658 mips_opts
.nobopt
= 1;
11660 else if (strcmp (name
, "mips16") == 0
11661 || strcmp (name
, "MIPS-16") == 0)
11662 mips_opts
.mips16
= 1;
11663 else if (strcmp (name
, "nomips16") == 0
11664 || strcmp (name
, "noMIPS-16") == 0)
11665 mips_opts
.mips16
= 0;
11666 else if (strcmp (name
, "mips3d") == 0)
11667 mips_opts
.ase_mips3d
= 1;
11668 else if (strcmp (name
, "nomips3d") == 0)
11669 mips_opts
.ase_mips3d
= 0;
11670 else if (strcmp (name
, "mdmx") == 0)
11671 mips_opts
.ase_mdmx
= 1;
11672 else if (strcmp (name
, "nomdmx") == 0)
11673 mips_opts
.ase_mdmx
= 0;
11674 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11678 /* Permit the user to change the ISA and architecture on the fly.
11679 Needless to say, misuse can cause serious problems. */
11680 if (strcmp (name
, "mips0") == 0 || strcmp (name
, "arch=default") == 0)
11683 mips_opts
.isa
= file_mips_isa
;
11684 mips_opts
.arch
= file_mips_arch
;
11686 else if (strncmp (name
, "arch=", 5) == 0)
11688 const struct mips_cpu_info
*p
;
11690 p
= mips_parse_cpu("internal use", name
+ 5);
11692 as_bad (_("unknown architecture %s"), name
+ 5);
11695 mips_opts
.arch
= p
->cpu
;
11696 mips_opts
.isa
= p
->isa
;
11699 else if (strncmp (name
, "mips", 4) == 0)
11701 const struct mips_cpu_info
*p
;
11703 p
= mips_parse_cpu("internal use", name
);
11705 as_bad (_("unknown ISA level %s"), name
+ 4);
11708 mips_opts
.arch
= p
->cpu
;
11709 mips_opts
.isa
= p
->isa
;
11713 as_bad (_("unknown ISA or architecture %s"), name
);
11715 switch (mips_opts
.isa
)
11723 mips_opts
.gp32
= 1;
11724 mips_opts
.fp32
= 1;
11731 mips_opts
.gp32
= 0;
11732 mips_opts
.fp32
= 0;
11735 as_bad (_("unknown ISA level %s"), name
+ 4);
11740 mips_opts
.gp32
= file_mips_gp32
;
11741 mips_opts
.fp32
= file_mips_fp32
;
11744 else if (strcmp (name
, "autoextend") == 0)
11745 mips_opts
.noautoextend
= 0;
11746 else if (strcmp (name
, "noautoextend") == 0)
11747 mips_opts
.noautoextend
= 1;
11748 else if (strcmp (name
, "push") == 0)
11750 struct mips_option_stack
*s
;
11752 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11753 s
->next
= mips_opts_stack
;
11754 s
->options
= mips_opts
;
11755 mips_opts_stack
= s
;
11757 else if (strcmp (name
, "pop") == 0)
11759 struct mips_option_stack
*s
;
11761 s
= mips_opts_stack
;
11763 as_bad (_(".set pop with no .set push"));
11766 /* If we're changing the reorder mode we need to handle
11767 delay slots correctly. */
11768 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11769 mips_emit_delays (TRUE
);
11770 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11772 if (prev_nop_frag
!= NULL
)
11774 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11775 * (mips_opts
.mips16
? 2 : 4));
11776 prev_nop_frag
= NULL
;
11780 mips_opts
= s
->options
;
11781 mips_opts_stack
= s
->next
;
11787 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
11789 *input_line_pointer
= ch
;
11790 demand_empty_rest_of_line ();
11793 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
11794 .option pic2. It means to generate SVR4 PIC calls. */
11797 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
11799 mips_pic
= SVR4_PIC
;
11800 mips_abicalls
= TRUE
;
11802 if (g_switch_seen
&& g_switch_value
!= 0)
11803 as_warn (_("-G may not be used with SVR4 PIC code"));
11804 g_switch_value
= 0;
11806 bfd_set_gp_size (stdoutput
, 0);
11807 demand_empty_rest_of_line ();
11810 /* Handle the .cpload pseudo-op. This is used when generating SVR4
11811 PIC code. It sets the $gp register for the function based on the
11812 function address, which is in the register named in the argument.
11813 This uses a relocation against _gp_disp, which is handled specially
11814 by the linker. The result is:
11815 lui $gp,%hi(_gp_disp)
11816 addiu $gp,$gp,%lo(_gp_disp)
11817 addu $gp,$gp,.cpload argument
11818 The .cpload argument is normally $25 == $t9.
11820 The -mno-shared option changes this to:
11822 addiu $gp,$gp,%lo(_gp)
11823 and the argument is ignored. This saves an instruction, but the
11824 resulting code is not position independent; it uses an absolute
11825 address for _gp. Thus code assembled with -mno-shared can go into
11826 an ordinary executable, but not into a shared library. */
11829 s_cpload (int ignore ATTRIBUTE_UNUSED
)
11835 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
11836 .cpload is ignored. */
11837 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
11843 /* .cpload should be in a .set noreorder section. */
11844 if (mips_opts
.noreorder
== 0)
11845 as_warn (_(".cpload not in noreorder section"));
11847 reg
= tc_get_register (0);
11849 /* If we need to produce a 64-bit address, we are better off using
11850 the default instruction sequence. */
11851 in_shared
= mips_in_shared
|| HAVE_64BIT_ADDRESSES
;
11853 ex
.X_op
= O_symbol
;
11854 ex
.X_add_symbol
= symbol_find_or_make (in_shared
? "_gp_disp" : "_gp");
11855 ex
.X_op_symbol
= NULL
;
11856 ex
.X_add_number
= 0;
11858 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11859 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11862 macro_build_lui (&ex
, mips_gp_register
);
11863 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11864 mips_gp_register
, BFD_RELOC_LO16
);
11866 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
11867 mips_gp_register
, reg
);
11870 demand_empty_rest_of_line ();
11873 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
11874 .cpsetup $reg1, offset|$reg2, label
11876 If offset is given, this results in:
11877 sd $gp, offset($sp)
11878 lui $gp, %hi(%neg(%gp_rel(label)))
11879 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11880 daddu $gp, $gp, $reg1
11882 If $reg2 is given, this results in:
11883 daddu $reg2, $gp, $0
11884 lui $gp, %hi(%neg(%gp_rel(label)))
11885 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
11886 daddu $gp, $gp, $reg1
11887 $reg1 is normally $25 == $t9.
11889 The -mno-shared option replaces the last three instructions with
11891 addiu $gp,$gp,%lo(_gp)
11895 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
11897 expressionS ex_off
;
11898 expressionS ex_sym
;
11901 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
11902 We also need NewABI support. */
11903 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
11909 reg1
= tc_get_register (0);
11910 SKIP_WHITESPACE ();
11911 if (*input_line_pointer
!= ',')
11913 as_bad (_("missing argument separator ',' for .cpsetup"));
11917 ++input_line_pointer
;
11918 SKIP_WHITESPACE ();
11919 if (*input_line_pointer
== '$')
11921 mips_cpreturn_register
= tc_get_register (0);
11922 mips_cpreturn_offset
= -1;
11926 mips_cpreturn_offset
= get_absolute_expression ();
11927 mips_cpreturn_register
= -1;
11929 SKIP_WHITESPACE ();
11930 if (*input_line_pointer
!= ',')
11932 as_bad (_("missing argument separator ',' for .cpsetup"));
11936 ++input_line_pointer
;
11937 SKIP_WHITESPACE ();
11938 expression (&ex_sym
);
11941 if (mips_cpreturn_register
== -1)
11943 ex_off
.X_op
= O_constant
;
11944 ex_off
.X_add_symbol
= NULL
;
11945 ex_off
.X_op_symbol
= NULL
;
11946 ex_off
.X_add_number
= mips_cpreturn_offset
;
11948 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
11949 BFD_RELOC_LO16
, SP
);
11952 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
11953 mips_gp_register
, 0);
11955 if (mips_in_shared
|| HAVE_64BIT_ADDRESSES
)
11957 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
,
11958 -1, BFD_RELOC_GPREL16
, BFD_RELOC_MIPS_SUB
,
11961 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
11962 mips_gp_register
, -1, BFD_RELOC_GPREL16
,
11963 BFD_RELOC_MIPS_SUB
, BFD_RELOC_LO16
);
11965 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
11966 mips_gp_register
, reg1
);
11972 ex
.X_op
= O_symbol
;
11973 ex
.X_add_symbol
= symbol_find_or_make ("_gp");
11974 ex
.X_op_symbol
= NULL
;
11975 ex
.X_add_number
= 0;
11977 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
11978 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
11980 macro_build_lui (&ex
, mips_gp_register
);
11981 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
11982 mips_gp_register
, BFD_RELOC_LO16
);
11987 demand_empty_rest_of_line ();
11991 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
11993 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
11994 .cplocal is ignored. */
11995 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12001 mips_gp_register
= tc_get_register (0);
12002 demand_empty_rest_of_line ();
12005 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12006 offset from $sp. The offset is remembered, and after making a PIC
12007 call $gp is restored from that location. */
12010 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12014 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12015 .cprestore is ignored. */
12016 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12022 mips_cprestore_offset
= get_absolute_expression ();
12023 mips_cprestore_valid
= 1;
12025 ex
.X_op
= O_constant
;
12026 ex
.X_add_symbol
= NULL
;
12027 ex
.X_op_symbol
= NULL
;
12028 ex
.X_add_number
= mips_cprestore_offset
;
12031 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12032 SP
, HAVE_64BIT_ADDRESSES
);
12035 demand_empty_rest_of_line ();
12038 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12039 was given in the preceding .cpsetup, it results in:
12040 ld $gp, offset($sp)
12042 If a register $reg2 was given there, it results in:
12043 daddu $gp, $reg2, $0
12046 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12050 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12051 We also need NewABI support. */
12052 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12059 if (mips_cpreturn_register
== -1)
12061 ex
.X_op
= O_constant
;
12062 ex
.X_add_symbol
= NULL
;
12063 ex
.X_op_symbol
= NULL
;
12064 ex
.X_add_number
= mips_cpreturn_offset
;
12066 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12069 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12070 mips_cpreturn_register
, 0);
12073 demand_empty_rest_of_line ();
12076 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12077 code. It sets the offset to use in gp_rel relocations. */
12080 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12082 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12083 We also need NewABI support. */
12084 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12090 mips_gprel_offset
= get_absolute_expression ();
12092 demand_empty_rest_of_line ();
12095 /* Handle the .gpword pseudo-op. This is used when generating PIC
12096 code. It generates a 32 bit GP relative reloc. */
12099 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12105 /* When not generating PIC code, this is treated as .word. */
12106 if (mips_pic
!= SVR4_PIC
)
12112 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12113 mips_emit_delays (TRUE
);
12115 mips_align (2, 0, label
);
12116 mips_clear_insn_labels ();
12120 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12122 as_bad (_("Unsupported use of .gpword"));
12123 ignore_rest_of_line ();
12127 md_number_to_chars (p
, 0, 4);
12128 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12129 BFD_RELOC_GPREL32
);
12131 demand_empty_rest_of_line ();
12135 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12141 /* When not generating PIC code, this is treated as .dword. */
12142 if (mips_pic
!= SVR4_PIC
)
12148 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12149 mips_emit_delays (TRUE
);
12151 mips_align (3, 0, label
);
12152 mips_clear_insn_labels ();
12156 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12158 as_bad (_("Unsupported use of .gpdword"));
12159 ignore_rest_of_line ();
12163 md_number_to_chars (p
, 0, 8);
12164 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12165 BFD_RELOC_GPREL32
)->fx_tcbit
= 1;
12167 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12168 fix_new (frag_now
, p
- frag_now
->fr_literal
, 8, NULL
, 0,
12169 FALSE
, BFD_RELOC_64
)->fx_tcbit
= 1;
12171 demand_empty_rest_of_line ();
12174 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12175 tables in SVR4 PIC code. */
12178 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12182 /* This is ignored when not generating SVR4 PIC code. */
12183 if (mips_pic
!= SVR4_PIC
)
12189 /* Add $gp to the register named as an argument. */
12191 reg
= tc_get_register (0);
12192 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12195 demand_empty_rest_of_line ();
12198 /* Handle the .insn pseudo-op. This marks instruction labels in
12199 mips16 mode. This permits the linker to handle them specially,
12200 such as generating jalx instructions when needed. We also make
12201 them odd for the duration of the assembly, in order to generate the
12202 right sort of code. We will make them even in the adjust_symtab
12203 routine, while leaving them marked. This is convenient for the
12204 debugger and the disassembler. The linker knows to make them odd
12208 s_insn (int ignore ATTRIBUTE_UNUSED
)
12210 mips16_mark_labels ();
12212 demand_empty_rest_of_line ();
12215 /* Handle a .stabn directive. We need these in order to mark a label
12216 as being a mips16 text label correctly. Sometimes the compiler
12217 will emit a label, followed by a .stabn, and then switch sections.
12218 If the label and .stabn are in mips16 mode, then the label is
12219 really a mips16 text label. */
12222 s_mips_stab (int type
)
12225 mips16_mark_labels ();
12230 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12234 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12241 name
= input_line_pointer
;
12242 c
= get_symbol_end ();
12243 symbolP
= symbol_find_or_make (name
);
12244 S_SET_WEAK (symbolP
);
12245 *input_line_pointer
= c
;
12247 SKIP_WHITESPACE ();
12249 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12251 if (S_IS_DEFINED (symbolP
))
12253 as_bad ("ignoring attempt to redefine symbol %s",
12254 S_GET_NAME (symbolP
));
12255 ignore_rest_of_line ();
12259 if (*input_line_pointer
== ',')
12261 ++input_line_pointer
;
12262 SKIP_WHITESPACE ();
12266 if (exp
.X_op
!= O_symbol
)
12268 as_bad ("bad .weakext directive");
12269 ignore_rest_of_line ();
12272 symbol_set_value_expression (symbolP
, &exp
);
12275 demand_empty_rest_of_line ();
12278 /* Parse a register string into a number. Called from the ECOFF code
12279 to parse .frame. The argument is non-zero if this is the frame
12280 register, so that we can record it in mips_frame_reg. */
12283 tc_get_register (int frame
)
12287 SKIP_WHITESPACE ();
12288 if (*input_line_pointer
++ != '$')
12290 as_warn (_("expected `$'"));
12293 else if (ISDIGIT (*input_line_pointer
))
12295 reg
= get_absolute_expression ();
12296 if (reg
< 0 || reg
>= 32)
12298 as_warn (_("Bad register number"));
12304 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12307 input_line_pointer
+= 2;
12309 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12312 input_line_pointer
+= 2;
12314 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12317 input_line_pointer
+= 2;
12319 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12322 input_line_pointer
+= 2;
12324 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12327 input_line_pointer
+= 2;
12329 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12332 input_line_pointer
+= 3;
12334 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12337 input_line_pointer
+= 3;
12339 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12342 input_line_pointer
+= 4;
12346 as_warn (_("Unrecognized register name"));
12348 while (ISALNUM(*input_line_pointer
))
12349 input_line_pointer
++;
12354 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12355 mips_frame_reg_valid
= 1;
12356 mips_cprestore_valid
= 0;
12362 md_section_align (asection
*seg
, valueT addr
)
12364 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12367 /* We don't need to align ELF sections to the full alignment.
12368 However, Irix 5 may prefer that we align them at least to a 16
12369 byte boundary. We don't bother to align the sections if we are
12370 targeted for an embedded system. */
12371 if (strcmp (TARGET_OS
, "elf") == 0)
12377 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12380 /* Utility routine, called from above as well. If called while the
12381 input file is still being read, it's only an approximation. (For
12382 example, a symbol may later become defined which appeared to be
12383 undefined earlier.) */
12386 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12391 if (g_switch_value
> 0)
12393 const char *symname
;
12396 /* Find out whether this symbol can be referenced off the $gp
12397 register. It can be if it is smaller than the -G size or if
12398 it is in the .sdata or .sbss section. Certain symbols can
12399 not be referenced off the $gp, although it appears as though
12401 symname
= S_GET_NAME (sym
);
12402 if (symname
!= (const char *) NULL
12403 && (strcmp (symname
, "eprol") == 0
12404 || strcmp (symname
, "etext") == 0
12405 || strcmp (symname
, "_gp") == 0
12406 || strcmp (symname
, "edata") == 0
12407 || strcmp (symname
, "_fbss") == 0
12408 || strcmp (symname
, "_fdata") == 0
12409 || strcmp (symname
, "_ftext") == 0
12410 || strcmp (symname
, "end") == 0
12411 || strcmp (symname
, "_gp_disp") == 0))
12413 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12415 #ifndef NO_ECOFF_DEBUGGING
12416 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12417 && (symbol_get_obj (sym
)->ecoff_extern_size
12418 <= g_switch_value
))
12420 /* We must defer this decision until after the whole
12421 file has been read, since there might be a .extern
12422 after the first use of this symbol. */
12423 || (before_relaxing
12424 #ifndef NO_ECOFF_DEBUGGING
12425 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12427 && S_GET_VALUE (sym
) == 0)
12428 || (S_GET_VALUE (sym
) != 0
12429 && S_GET_VALUE (sym
) <= g_switch_value
)))
12433 const char *segname
;
12435 segname
= segment_name (S_GET_SEGMENT (sym
));
12436 assert (strcmp (segname
, ".lit8") != 0
12437 && strcmp (segname
, ".lit4") != 0);
12438 change
= (strcmp (segname
, ".sdata") != 0
12439 && strcmp (segname
, ".sbss") != 0
12440 && strncmp (segname
, ".sdata.", 7) != 0
12441 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12446 /* We are not optimizing for the $gp register. */
12451 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12454 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12457 bfd_boolean linkonce
;
12459 /* Handle the case of a symbol equated to another symbol. */
12460 while (symbol_equated_reloc_p (sym
))
12464 /* It's possible to get a loop here in a badly written
12466 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12472 symsec
= S_GET_SEGMENT (sym
);
12474 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12476 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12478 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12482 /* The GNU toolchain uses an extension for ELF: a section
12483 beginning with the magic string .gnu.linkonce is a linkonce
12485 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12486 sizeof ".gnu.linkonce" - 1) == 0)
12490 /* This must duplicate the test in adjust_reloc_syms. */
12491 return (symsec
!= &bfd_und_section
12492 && symsec
!= &bfd_abs_section
12493 && ! bfd_is_com_section (symsec
)
12496 /* A global or weak symbol is treated as external. */
12497 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12498 || (! S_IS_WEAK (sym
) && ! S_IS_EXTERNAL (sym
)))
12504 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12505 extended opcode. SEC is the section the frag is in. */
12508 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12511 register const struct mips16_immed_operand
*op
;
12513 int mintiny
, maxtiny
;
12517 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12519 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12522 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12523 op
= mips16_immed_operands
;
12524 while (op
->type
!= type
)
12527 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12532 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12535 maxtiny
= 1 << op
->nbits
;
12540 maxtiny
= (1 << op
->nbits
) - 1;
12545 mintiny
= - (1 << (op
->nbits
- 1));
12546 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12549 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12550 val
= S_GET_VALUE (fragp
->fr_symbol
);
12551 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12557 /* We won't have the section when we are called from
12558 mips_relax_frag. However, we will always have been called
12559 from md_estimate_size_before_relax first. If this is a
12560 branch to a different section, we mark it as such. If SEC is
12561 NULL, and the frag is not marked, then it must be a branch to
12562 the same section. */
12565 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12570 /* Must have been called from md_estimate_size_before_relax. */
12573 fragp
->fr_subtype
=
12574 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12576 /* FIXME: We should support this, and let the linker
12577 catch branches and loads that are out of range. */
12578 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12579 _("unsupported PC relative reference to different section"));
12583 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12584 /* Assume non-extended on the first relaxation pass.
12585 The address we have calculated will be bogus if this is
12586 a forward branch to another frag, as the forward frag
12587 will have fr_address == 0. */
12591 /* In this case, we know for sure that the symbol fragment is in
12592 the same section. If the relax_marker of the symbol fragment
12593 differs from the relax_marker of this fragment, we have not
12594 yet adjusted the symbol fragment fr_address. We want to add
12595 in STRETCH in order to get a better estimate of the address.
12596 This particularly matters because of the shift bits. */
12598 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12602 /* Adjust stretch for any alignment frag. Note that if have
12603 been expanding the earlier code, the symbol may be
12604 defined in what appears to be an earlier frag. FIXME:
12605 This doesn't handle the fr_subtype field, which specifies
12606 a maximum number of bytes to skip when doing an
12608 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12610 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12613 stretch
= - ((- stretch
)
12614 & ~ ((1 << (int) f
->fr_offset
) - 1));
12616 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12625 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12627 /* The base address rules are complicated. The base address of
12628 a branch is the following instruction. The base address of a
12629 PC relative load or add is the instruction itself, but if it
12630 is in a delay slot (in which case it can not be extended) use
12631 the address of the instruction whose delay slot it is in. */
12632 if (type
== 'p' || type
== 'q')
12636 /* If we are currently assuming that this frag should be
12637 extended, then, the current address is two bytes
12639 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12642 /* Ignore the low bit in the target, since it will be set
12643 for a text label. */
12644 if ((val
& 1) != 0)
12647 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12649 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12652 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12654 /* Branch offsets have an implicit 0 in the lowest bit. */
12655 if (type
== 'p' || type
== 'q')
12658 /* If any of the shifted bits are set, we must use an extended
12659 opcode. If the address depends on the size of this
12660 instruction, this can lead to a loop, so we arrange to always
12661 use an extended opcode. We only check this when we are in
12662 the main relaxation loop, when SEC is NULL. */
12663 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12665 fragp
->fr_subtype
=
12666 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12670 /* If we are about to mark a frag as extended because the value
12671 is precisely maxtiny + 1, then there is a chance of an
12672 infinite loop as in the following code:
12677 In this case when the la is extended, foo is 0x3fc bytes
12678 away, so the la can be shrunk, but then foo is 0x400 away, so
12679 the la must be extended. To avoid this loop, we mark the
12680 frag as extended if it was small, and is about to become
12681 extended with a value of maxtiny + 1. */
12682 if (val
== ((maxtiny
+ 1) << op
->shift
)
12683 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12686 fragp
->fr_subtype
=
12687 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12691 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12692 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12694 if ((val
& ((1 << op
->shift
) - 1)) != 0
12695 || val
< (mintiny
<< op
->shift
)
12696 || val
> (maxtiny
<< op
->shift
))
12702 /* Compute the length of a branch sequence, and adjust the
12703 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12704 worst-case length is computed, with UPDATE being used to indicate
12705 whether an unconditional (-1), branch-likely (+1) or regular (0)
12706 branch is to be computed. */
12708 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12710 bfd_boolean toofar
;
12714 && S_IS_DEFINED (fragp
->fr_symbol
)
12715 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12720 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12722 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12726 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12729 /* If the symbol is not defined or it's in a different segment,
12730 assume the user knows what's going on and emit a short
12736 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12738 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12739 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12740 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12746 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12749 if (mips_pic
!= NO_PIC
)
12751 /* Additional space for PIC loading of target address. */
12753 if (mips_opts
.isa
== ISA_MIPS1
)
12754 /* Additional space for $at-stabilizing nop. */
12758 /* If branch is conditional. */
12759 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12766 /* Estimate the size of a frag before relaxing. Unless this is the
12767 mips16, we are not really relaxing here, and the final size is
12768 encoded in the subtype information. For the mips16, we have to
12769 decide whether we are using an extended opcode or not. */
12772 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12776 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12779 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12781 return fragp
->fr_var
;
12784 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12785 /* We don't want to modify the EXTENDED bit here; it might get us
12786 into infinite loops. We change it only in mips_relax_frag(). */
12787 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12789 if (mips_pic
== NO_PIC
)
12790 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12791 else if (mips_pic
== SVR4_PIC
)
12792 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12798 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12799 return -RELAX_FIRST (fragp
->fr_subtype
);
12802 return -RELAX_SECOND (fragp
->fr_subtype
);
12805 /* This is called to see whether a reloc against a defined symbol
12806 should be converted into a reloc against a section. */
12809 mips_fix_adjustable (fixS
*fixp
)
12811 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
12812 about the format of the offset in the .o file. */
12813 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
12816 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
12817 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12820 if (fixp
->fx_addsy
== NULL
)
12823 /* If symbol SYM is in a mergeable section, relocations of the form
12824 SYM + 0 can usually be made section-relative. The mergeable data
12825 is then identified by the section offset rather than by the symbol.
12827 However, if we're generating REL LO16 relocations, the offset is split
12828 between the LO16 and parterning high part relocation. The linker will
12829 need to recalculate the complete offset in order to correctly identify
12832 The linker has traditionally not looked for the parterning high part
12833 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
12834 placed anywhere. Rather than break backwards compatibility by changing
12835 this, it seems better not to force the issue, and instead keep the
12836 original symbol. This will work with either linker behavior. */
12837 if ((fixp
->fx_r_type
== BFD_RELOC_LO16
|| reloc_needs_lo_p (fixp
->fx_r_type
))
12838 && HAVE_IN_PLACE_ADDENDS
12839 && (S_GET_SEGMENT (fixp
->fx_addsy
)->flags
& SEC_MERGE
) != 0)
12843 /* Don't adjust relocations against mips16 symbols, so that the linker
12844 can find them if it needs to set up a stub. */
12845 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
12846 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
12847 && fixp
->fx_subsy
== NULL
)
12854 /* Translate internal representation of relocation info to BFD target
12858 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
12860 static arelent
*retval
[4];
12862 bfd_reloc_code_real_type code
;
12864 memset (retval
, 0, sizeof(retval
));
12865 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
12866 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
12867 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
12868 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
12870 assert (! fixp
->fx_pcrel
);
12871 reloc
->addend
= fixp
->fx_addnumber
;
12873 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
12874 entry to be used in the relocation's section offset. */
12875 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
12877 reloc
->address
= reloc
->addend
;
12881 code
= fixp
->fx_r_type
;
12883 /* To support a PC relative reloc, we used a Cygnus extension.
12884 We check for that here to make sure that we don't let such a
12885 reloc escape normally. (FIXME: This was formerly used by
12886 embedded-PIC support, but is now used by branch handling in
12887 general. That probably should be fixed.) */
12888 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
12889 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
12890 && code
== BFD_RELOC_16_PCREL_S2
)
12891 reloc
->howto
= NULL
;
12893 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
12895 if (reloc
->howto
== NULL
)
12897 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
12898 _("Can not represent %s relocation in this object file format"),
12899 bfd_get_reloc_code_name (code
));
12906 /* Relax a machine dependent frag. This returns the amount by which
12907 the current size of the frag should change. */
12910 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
12912 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12914 offsetT old_var
= fragp
->fr_var
;
12916 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
12918 return fragp
->fr_var
- old_var
;
12921 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
12924 if (mips16_extended_frag (fragp
, NULL
, stretch
))
12926 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12928 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
12933 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12935 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
12942 /* Convert a machine dependent frag. */
12945 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
12947 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12950 unsigned long insn
;
12954 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
12956 if (target_big_endian
)
12957 insn
= bfd_getb32 (buf
);
12959 insn
= bfd_getl32 (buf
);
12961 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12963 /* We generate a fixup instead of applying it right now
12964 because, if there are linker relaxations, we're going to
12965 need the relocations. */
12966 exp
.X_op
= O_symbol
;
12967 exp
.X_add_symbol
= fragp
->fr_symbol
;
12968 exp
.X_add_number
= fragp
->fr_offset
;
12970 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
12972 BFD_RELOC_16_PCREL_S2
);
12973 fixp
->fx_file
= fragp
->fr_file
;
12974 fixp
->fx_line
= fragp
->fr_line
;
12976 md_number_to_chars (buf
, insn
, 4);
12983 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
12984 _("relaxed out-of-range branch into a jump"));
12986 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
12989 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
12991 /* Reverse the branch. */
12992 switch ((insn
>> 28) & 0xf)
12995 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
12996 have the condition reversed by tweaking a single
12997 bit, and their opcodes all have 0x4???????. */
12998 assert ((insn
& 0xf1000000) == 0x41000000);
12999 insn
^= 0x00010000;
13003 /* bltz 0x04000000 bgez 0x04010000
13004 bltzal 0x04100000 bgezal 0x04110000 */
13005 assert ((insn
& 0xfc0e0000) == 0x04000000);
13006 insn
^= 0x00010000;
13010 /* beq 0x10000000 bne 0x14000000
13011 blez 0x18000000 bgtz 0x1c000000 */
13012 insn
^= 0x04000000;
13020 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13022 /* Clear the and-link bit. */
13023 assert ((insn
& 0xfc1c0000) == 0x04100000);
13025 /* bltzal 0x04100000 bgezal 0x04110000
13026 bltzall 0x04120000 bgezall 0x04130000 */
13027 insn
&= ~0x00100000;
13030 /* Branch over the branch (if the branch was likely) or the
13031 full jump (not likely case). Compute the offset from the
13032 current instruction to branch to. */
13033 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13037 /* How many bytes in instructions we've already emitted? */
13038 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13039 /* How many bytes in instructions from here to the end? */
13040 i
= fragp
->fr_var
- i
;
13042 /* Convert to instruction count. */
13044 /* Branch counts from the next instruction. */
13047 /* Branch over the jump. */
13048 md_number_to_chars (buf
, insn
, 4);
13052 md_number_to_chars (buf
, 0, 4);
13055 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13057 /* beql $0, $0, 2f */
13059 /* Compute the PC offset from the current instruction to
13060 the end of the variable frag. */
13061 /* How many bytes in instructions we've already emitted? */
13062 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13063 /* How many bytes in instructions from here to the end? */
13064 i
= fragp
->fr_var
- i
;
13065 /* Convert to instruction count. */
13067 /* Don't decrement i, because we want to branch over the
13071 md_number_to_chars (buf
, insn
, 4);
13074 md_number_to_chars (buf
, 0, 4);
13079 if (mips_pic
== NO_PIC
)
13082 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13083 ? 0x0c000000 : 0x08000000);
13084 exp
.X_op
= O_symbol
;
13085 exp
.X_add_symbol
= fragp
->fr_symbol
;
13086 exp
.X_add_number
= fragp
->fr_offset
;
13088 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13089 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13090 fixp
->fx_file
= fragp
->fr_file
;
13091 fixp
->fx_line
= fragp
->fr_line
;
13093 md_number_to_chars (buf
, insn
, 4);
13098 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13099 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13100 exp
.X_op
= O_symbol
;
13101 exp
.X_add_symbol
= fragp
->fr_symbol
;
13102 exp
.X_add_number
= fragp
->fr_offset
;
13104 if (fragp
->fr_offset
)
13106 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13107 exp
.X_add_number
= 0;
13110 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13111 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13112 fixp
->fx_file
= fragp
->fr_file
;
13113 fixp
->fx_line
= fragp
->fr_line
;
13115 md_number_to_chars (buf
, insn
, 4);
13118 if (mips_opts
.isa
== ISA_MIPS1
)
13121 md_number_to_chars (buf
, 0, 4);
13125 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13126 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13128 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13129 4, &exp
, 0, BFD_RELOC_LO16
);
13130 fixp
->fx_file
= fragp
->fr_file
;
13131 fixp
->fx_line
= fragp
->fr_line
;
13133 md_number_to_chars (buf
, insn
, 4);
13137 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13142 md_number_to_chars (buf
, insn
, 4);
13147 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13148 + fragp
->fr_fix
+ fragp
->fr_var
);
13150 fragp
->fr_fix
+= fragp
->fr_var
;
13155 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13158 register const struct mips16_immed_operand
*op
;
13159 bfd_boolean small
, ext
;
13162 unsigned long insn
;
13163 bfd_boolean use_extend
;
13164 unsigned short extend
;
13166 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13167 op
= mips16_immed_operands
;
13168 while (op
->type
!= type
)
13171 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13182 resolve_symbol_value (fragp
->fr_symbol
);
13183 val
= S_GET_VALUE (fragp
->fr_symbol
);
13188 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13190 /* The rules for the base address of a PC relative reloc are
13191 complicated; see mips16_extended_frag. */
13192 if (type
== 'p' || type
== 'q')
13197 /* Ignore the low bit in the target, since it will be
13198 set for a text label. */
13199 if ((val
& 1) != 0)
13202 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13204 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13207 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13210 /* Make sure the section winds up with the alignment we have
13213 record_alignment (asec
, op
->shift
);
13217 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13218 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13219 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13220 _("extended instruction in delay slot"));
13222 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13224 if (target_big_endian
)
13225 insn
= bfd_getb16 (buf
);
13227 insn
= bfd_getl16 (buf
);
13229 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13230 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13231 small
, ext
, &insn
, &use_extend
, &extend
);
13235 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13236 fragp
->fr_fix
+= 2;
13240 md_number_to_chars (buf
, insn
, 2);
13241 fragp
->fr_fix
+= 2;
13249 first
= RELAX_FIRST (fragp
->fr_subtype
);
13250 second
= RELAX_SECOND (fragp
->fr_subtype
);
13251 fixp
= (fixS
*) fragp
->fr_opcode
;
13253 /* Possibly emit a warning if we've chosen the longer option. */
13254 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13255 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13257 const char *msg
= macro_warning (fragp
->fr_subtype
);
13259 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13262 /* Go through all the fixups for the first sequence. Disable them
13263 (by marking them as done) if we're going to use the second
13264 sequence instead. */
13266 && fixp
->fx_frag
== fragp
13267 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13269 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13271 fixp
= fixp
->fx_next
;
13274 /* Go through the fixups for the second sequence. Disable them if
13275 we're going to use the first sequence, otherwise adjust their
13276 addresses to account for the relaxation. */
13277 while (fixp
&& fixp
->fx_frag
== fragp
)
13279 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13280 fixp
->fx_where
-= first
;
13283 fixp
= fixp
->fx_next
;
13286 /* Now modify the frag contents. */
13287 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13291 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13292 memmove (start
, start
+ first
, second
);
13293 fragp
->fr_fix
-= first
;
13296 fragp
->fr_fix
-= second
;
13302 /* This function is called after the relocs have been generated.
13303 We've been storing mips16 text labels as odd. Here we convert them
13304 back to even for the convenience of the debugger. */
13307 mips_frob_file_after_relocs (void)
13310 unsigned int count
, i
;
13312 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13315 syms
= bfd_get_outsymbols (stdoutput
);
13316 count
= bfd_get_symcount (stdoutput
);
13317 for (i
= 0; i
< count
; i
++, syms
++)
13319 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13320 && ((*syms
)->value
& 1) != 0)
13322 (*syms
)->value
&= ~1;
13323 /* If the symbol has an odd size, it was probably computed
13324 incorrectly, so adjust that as well. */
13325 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13326 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13333 /* This function is called whenever a label is defined. It is used
13334 when handling branch delays; if a branch has a label, we assume we
13335 can not move it. */
13338 mips_define_label (symbolS
*sym
)
13340 struct insn_label_list
*l
;
13342 if (free_insn_labels
== NULL
)
13343 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13346 l
= free_insn_labels
;
13347 free_insn_labels
= l
->next
;
13351 l
->next
= insn_labels
;
13355 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13357 /* Some special processing for a MIPS ELF file. */
13360 mips_elf_final_processing (void)
13362 /* Write out the register information. */
13363 if (mips_abi
!= N64_ABI
)
13367 s
.ri_gprmask
= mips_gprmask
;
13368 s
.ri_cprmask
[0] = mips_cprmask
[0];
13369 s
.ri_cprmask
[1] = mips_cprmask
[1];
13370 s
.ri_cprmask
[2] = mips_cprmask
[2];
13371 s
.ri_cprmask
[3] = mips_cprmask
[3];
13372 /* The gp_value field is set by the MIPS ELF backend. */
13374 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13375 ((Elf32_External_RegInfo
*)
13376 mips_regmask_frag
));
13380 Elf64_Internal_RegInfo s
;
13382 s
.ri_gprmask
= mips_gprmask
;
13384 s
.ri_cprmask
[0] = mips_cprmask
[0];
13385 s
.ri_cprmask
[1] = mips_cprmask
[1];
13386 s
.ri_cprmask
[2] = mips_cprmask
[2];
13387 s
.ri_cprmask
[3] = mips_cprmask
[3];
13388 /* The gp_value field is set by the MIPS ELF backend. */
13390 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13391 ((Elf64_External_RegInfo
*)
13392 mips_regmask_frag
));
13395 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13396 sort of BFD interface for this. */
13397 if (mips_any_noreorder
)
13398 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13399 if (mips_pic
!= NO_PIC
)
13401 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13402 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13405 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13407 /* Set MIPS ELF flags for ASEs. */
13408 if (file_ase_mips16
)
13409 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13410 #if 0 /* XXX FIXME */
13411 if (file_ase_mips3d
)
13412 elf_elfheader (stdoutput
)->e_flags
|= ???;
13415 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13417 /* Set the MIPS ELF ABI flags. */
13418 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13419 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13420 else if (mips_abi
== O64_ABI
)
13421 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13422 else if (mips_abi
== EABI_ABI
)
13424 if (!file_mips_gp32
)
13425 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13427 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13429 else if (mips_abi
== N32_ABI
)
13430 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13432 /* Nothing to do for N64_ABI. */
13434 if (mips_32bitmode
)
13435 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13438 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13440 typedef struct proc
{
13442 unsigned long reg_mask
;
13443 unsigned long reg_offset
;
13444 unsigned long fpreg_mask
;
13445 unsigned long fpreg_offset
;
13446 unsigned long frame_offset
;
13447 unsigned long frame_reg
;
13448 unsigned long pc_reg
;
13451 static procS cur_proc
;
13452 static procS
*cur_proc_ptr
;
13453 static int numprocs
;
13455 /* Fill in an rs_align_code fragment. */
13458 mips_handle_align (fragS
*fragp
)
13460 if (fragp
->fr_type
!= rs_align_code
)
13463 if (mips_opts
.mips16
)
13465 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13466 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13471 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13472 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13480 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13484 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13488 md_obj_begin (void)
13495 /* check for premature end, nesting errors, etc */
13497 as_warn (_("missing .end at end of assembly"));
13506 if (*input_line_pointer
== '-')
13508 ++input_line_pointer
;
13511 if (!ISDIGIT (*input_line_pointer
))
13512 as_bad (_("expected simple number"));
13513 if (input_line_pointer
[0] == '0')
13515 if (input_line_pointer
[1] == 'x')
13517 input_line_pointer
+= 2;
13518 while (ISXDIGIT (*input_line_pointer
))
13521 val
|= hex_value (*input_line_pointer
++);
13523 return negative
? -val
: val
;
13527 ++input_line_pointer
;
13528 while (ISDIGIT (*input_line_pointer
))
13531 val
|= *input_line_pointer
++ - '0';
13533 return negative
? -val
: val
;
13536 if (!ISDIGIT (*input_line_pointer
))
13538 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13539 *input_line_pointer
, *input_line_pointer
);
13540 as_warn (_("invalid number"));
13543 while (ISDIGIT (*input_line_pointer
))
13546 val
+= *input_line_pointer
++ - '0';
13548 return negative
? -val
: val
;
13551 /* The .file directive; just like the usual .file directive, but there
13552 is an initial number which is the ECOFF file index. In the non-ECOFF
13553 case .file implies DWARF-2. */
13556 s_mips_file (int x ATTRIBUTE_UNUSED
)
13558 static int first_file_directive
= 0;
13560 if (ECOFF_DEBUGGING
)
13569 filename
= dwarf2_directive_file (0);
13571 /* Versions of GCC up to 3.1 start files with a ".file"
13572 directive even for stabs output. Make sure that this
13573 ".file" is handled. Note that you need a version of GCC
13574 after 3.1 in order to support DWARF-2 on MIPS. */
13575 if (filename
!= NULL
&& ! first_file_directive
)
13577 (void) new_logical_line (filename
, -1);
13578 s_app_file_string (filename
, 0);
13580 first_file_directive
= 1;
13584 /* The .loc directive, implying DWARF-2. */
13587 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13589 if (!ECOFF_DEBUGGING
)
13590 dwarf2_directive_loc (0);
13593 /* The .end directive. */
13596 s_mips_end (int x ATTRIBUTE_UNUSED
)
13600 /* Following functions need their own .frame and .cprestore directives. */
13601 mips_frame_reg_valid
= 0;
13602 mips_cprestore_valid
= 0;
13604 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13607 demand_empty_rest_of_line ();
13612 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13613 as_warn (_(".end not in text section"));
13617 as_warn (_(".end directive without a preceding .ent directive."));
13618 demand_empty_rest_of_line ();
13624 assert (S_GET_NAME (p
));
13625 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13626 as_warn (_(".end symbol does not match .ent symbol."));
13628 if (debug_type
== DEBUG_STABS
)
13629 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13633 as_warn (_(".end directive missing or unknown symbol"));
13636 /* Generate a .pdr section. */
13637 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13640 segT saved_seg
= now_seg
;
13641 subsegT saved_subseg
= now_subseg
;
13646 dot
= frag_now_fix ();
13648 #ifdef md_flush_pending_output
13649 md_flush_pending_output ();
13653 subseg_set (pdr_seg
, 0);
13655 /* Write the symbol. */
13656 exp
.X_op
= O_symbol
;
13657 exp
.X_add_symbol
= p
;
13658 exp
.X_add_number
= 0;
13659 emit_expr (&exp
, 4);
13661 fragp
= frag_more (7 * 4);
13663 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13664 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13665 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13666 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13667 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13668 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13669 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13671 subseg_set (saved_seg
, saved_subseg
);
13673 #endif /* OBJ_ELF */
13675 cur_proc_ptr
= NULL
;
13678 /* The .aent and .ent directives. */
13681 s_mips_ent (int aent
)
13685 symbolP
= get_symbol ();
13686 if (*input_line_pointer
== ',')
13687 ++input_line_pointer
;
13688 SKIP_WHITESPACE ();
13689 if (ISDIGIT (*input_line_pointer
)
13690 || *input_line_pointer
== '-')
13693 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13694 as_warn (_(".ent or .aent not in text section."));
13696 if (!aent
&& cur_proc_ptr
)
13697 as_warn (_("missing .end"));
13701 /* This function needs its own .frame and .cprestore directives. */
13702 mips_frame_reg_valid
= 0;
13703 mips_cprestore_valid
= 0;
13705 cur_proc_ptr
= &cur_proc
;
13706 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13708 cur_proc_ptr
->isym
= symbolP
;
13710 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13714 if (debug_type
== DEBUG_STABS
)
13715 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13716 S_GET_NAME (symbolP
));
13719 demand_empty_rest_of_line ();
13722 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13723 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13724 s_mips_frame is used so that we can set the PDR information correctly.
13725 We can't use the ecoff routines because they make reference to the ecoff
13726 symbol table (in the mdebug section). */
13729 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13732 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13736 if (cur_proc_ptr
== (procS
*) NULL
)
13738 as_warn (_(".frame outside of .ent"));
13739 demand_empty_rest_of_line ();
13743 cur_proc_ptr
->frame_reg
= tc_get_register (1);
13745 SKIP_WHITESPACE ();
13746 if (*input_line_pointer
++ != ','
13747 || get_absolute_expression_and_terminator (&val
) != ',')
13749 as_warn (_("Bad .frame directive"));
13750 --input_line_pointer
;
13751 demand_empty_rest_of_line ();
13755 cur_proc_ptr
->frame_offset
= val
;
13756 cur_proc_ptr
->pc_reg
= tc_get_register (0);
13758 demand_empty_rest_of_line ();
13761 #endif /* OBJ_ELF */
13765 /* The .fmask and .mask directives. If the mdebug section is present
13766 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
13767 embedded targets, s_mips_mask is used so that we can set the PDR
13768 information correctly. We can't use the ecoff routines because they
13769 make reference to the ecoff symbol table (in the mdebug section). */
13772 s_mips_mask (int reg_type
)
13775 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13779 if (cur_proc_ptr
== (procS
*) NULL
)
13781 as_warn (_(".mask/.fmask outside of .ent"));
13782 demand_empty_rest_of_line ();
13786 if (get_absolute_expression_and_terminator (&mask
) != ',')
13788 as_warn (_("Bad .mask/.fmask directive"));
13789 --input_line_pointer
;
13790 demand_empty_rest_of_line ();
13794 off
= get_absolute_expression ();
13796 if (reg_type
== 'F')
13798 cur_proc_ptr
->fpreg_mask
= mask
;
13799 cur_proc_ptr
->fpreg_offset
= off
;
13803 cur_proc_ptr
->reg_mask
= mask
;
13804 cur_proc_ptr
->reg_offset
= off
;
13807 demand_empty_rest_of_line ();
13810 #endif /* OBJ_ELF */
13811 s_ignore (reg_type
);
13814 /* The .loc directive. */
13824 assert (now_seg
== text_section
);
13826 lineno
= get_number ();
13827 addroff
= frag_now_fix ();
13829 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
13830 S_SET_TYPE (symbolP
, N_SLINE
);
13831 S_SET_OTHER (symbolP
, 0);
13832 S_SET_DESC (symbolP
, lineno
);
13833 symbolP
->sy_segment
= now_seg
;
13837 /* A table describing all the processors gas knows about. Names are
13838 matched in the order listed.
13840 To ease comparison, please keep this table in the same order as
13841 gcc's mips_cpu_info_table[]. */
13842 static const struct mips_cpu_info mips_cpu_info_table
[] =
13844 /* Entries for generic ISAs */
13845 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
13846 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
13847 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
13848 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
13849 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
13850 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
13851 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
13852 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
13853 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
13856 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
13857 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
13858 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
13861 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
13864 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
13865 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
13866 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
13867 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
13868 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
13869 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
13870 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
13871 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
13872 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
13873 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
13874 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
13875 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
13878 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
13879 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
13880 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
13881 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
13882 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
13883 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
13884 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
13885 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
13886 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
13887 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
13888 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
13889 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
13890 { "rm9000", 0, ISA_MIPS4
, CPU_RM9000
},
13893 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
13894 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
13895 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
13898 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13899 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
13901 /* Broadcom SB-1 CPU core */
13902 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
13909 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
13910 with a final "000" replaced by "k". Ignore case.
13912 Note: this function is shared between GCC and GAS. */
13915 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
13917 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
13918 given
++, canonical
++;
13920 return ((*given
== 0 && *canonical
== 0)
13921 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
13925 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
13926 CPU name. We've traditionally allowed a lot of variation here.
13928 Note: this function is shared between GCC and GAS. */
13931 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
13933 /* First see if the name matches exactly, or with a final "000"
13934 turned into "k". */
13935 if (mips_strict_matching_cpu_name_p (canonical
, given
))
13938 /* If not, try comparing based on numerical designation alone.
13939 See if GIVEN is an unadorned number, or 'r' followed by a number. */
13940 if (TOLOWER (*given
) == 'r')
13942 if (!ISDIGIT (*given
))
13945 /* Skip over some well-known prefixes in the canonical name,
13946 hoping to find a number there too. */
13947 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
13949 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
13951 else if (TOLOWER (canonical
[0]) == 'r')
13954 return mips_strict_matching_cpu_name_p (canonical
, given
);
13958 /* Parse an option that takes the name of a processor as its argument.
13959 OPTION is the name of the option and CPU_STRING is the argument.
13960 Return the corresponding processor enumeration if the CPU_STRING is
13961 recognized, otherwise report an error and return null.
13963 A similar function exists in GCC. */
13965 static const struct mips_cpu_info
*
13966 mips_parse_cpu (const char *option
, const char *cpu_string
)
13968 const struct mips_cpu_info
*p
;
13970 /* 'from-abi' selects the most compatible architecture for the given
13971 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
13972 EABIs, we have to decide whether we're using the 32-bit or 64-bit
13973 version. Look first at the -mgp options, if given, otherwise base
13974 the choice on MIPS_DEFAULT_64BIT.
13976 Treat NO_ABI like the EABIs. One reason to do this is that the
13977 plain 'mips' and 'mips64' configs have 'from-abi' as their default
13978 architecture. This code picks MIPS I for 'mips' and MIPS III for
13979 'mips64', just as we did in the days before 'from-abi'. */
13980 if (strcasecmp (cpu_string
, "from-abi") == 0)
13982 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
13983 return mips_cpu_info_from_isa (ISA_MIPS1
);
13985 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
13986 return mips_cpu_info_from_isa (ISA_MIPS3
);
13988 if (file_mips_gp32
>= 0)
13989 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
13991 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
13996 /* 'default' has traditionally been a no-op. Probably not very useful. */
13997 if (strcasecmp (cpu_string
, "default") == 0)
14000 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14001 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14004 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14008 /* Return the canonical processor information for ISA (a member of the
14009 ISA_MIPS* enumeration). */
14011 static const struct mips_cpu_info
*
14012 mips_cpu_info_from_isa (int isa
)
14016 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14017 if (mips_cpu_info_table
[i
].is_isa
14018 && isa
== mips_cpu_info_table
[i
].isa
)
14019 return (&mips_cpu_info_table
[i
]);
14024 static const struct mips_cpu_info
*
14025 mips_cpu_info_from_arch (int arch
)
14029 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14030 if (arch
== mips_cpu_info_table
[i
].cpu
)
14031 return (&mips_cpu_info_table
[i
]);
14037 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14041 fprintf (stream
, "%24s", "");
14046 fprintf (stream
, ", ");
14050 if (*col_p
+ strlen (string
) > 72)
14052 fprintf (stream
, "\n%24s", "");
14056 fprintf (stream
, "%s", string
);
14057 *col_p
+= strlen (string
);
14063 md_show_usage (FILE *stream
)
14068 fprintf (stream
, _("\
14070 -EB generate big endian output\n\
14071 -EL generate little endian output\n\
14072 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14073 -G NUM allow referencing objects up to NUM bytes\n\
14074 implicitly with the gp register [default 8]\n"));
14075 fprintf (stream
, _("\
14076 -mips1 generate MIPS ISA I instructions\n\
14077 -mips2 generate MIPS ISA II instructions\n\
14078 -mips3 generate MIPS ISA III instructions\n\
14079 -mips4 generate MIPS ISA IV instructions\n\
14080 -mips5 generate MIPS ISA V instructions\n\
14081 -mips32 generate MIPS32 ISA instructions\n\
14082 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14083 -mips64 generate MIPS64 ISA instructions\n\
14084 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14085 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14089 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14090 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14091 show (stream
, "from-abi", &column
, &first
);
14092 fputc ('\n', stream
);
14094 fprintf (stream
, _("\
14095 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14096 -no-mCPU don't generate code specific to CPU.\n\
14097 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14101 show (stream
, "3900", &column
, &first
);
14102 show (stream
, "4010", &column
, &first
);
14103 show (stream
, "4100", &column
, &first
);
14104 show (stream
, "4650", &column
, &first
);
14105 fputc ('\n', stream
);
14107 fprintf (stream
, _("\
14108 -mips16 generate mips16 instructions\n\
14109 -no-mips16 do not generate mips16 instructions\n"));
14110 fprintf (stream
, _("\
14111 -mfix-vr4120 work around certain VR4120 errata\n\
14112 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14113 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14114 -O0 remove unneeded NOPs, do not swap branches\n\
14115 -O remove unneeded NOPs and swap branches\n\
14116 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14117 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14118 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14120 fprintf (stream
, _("\
14121 -KPIC, -call_shared generate SVR4 position independent code\n\
14122 -non_shared do not generate position independent code\n\
14123 -xgot assume a 32 bit GOT\n\
14124 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14125 -mabi=ABI create ABI conformant object file for:\n"));
14129 show (stream
, "32", &column
, &first
);
14130 show (stream
, "o64", &column
, &first
);
14131 show (stream
, "n32", &column
, &first
);
14132 show (stream
, "64", &column
, &first
);
14133 show (stream
, "eabi", &column
, &first
);
14135 fputc ('\n', stream
);
14137 fprintf (stream
, _("\
14138 -32 create o32 ABI object file (default)\n\
14139 -n32 create n32 ABI object file\n\
14140 -64 create 64 ABI object file\n"));
14145 mips_dwarf2_format (void)
14147 if (mips_abi
== N64_ABI
)
14150 return dwarf2_format_64bit_irix
;
14152 return dwarf2_format_64bit
;
14156 return dwarf2_format_32bit
;
14160 mips_dwarf2_addr_size (void)
14162 if (mips_abi
== N64_ABI
)