1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
57 #undef TARGET_SYMBOL_FIELDS
59 #undef obj_frob_file_after_relocs
60 #undef obj_frob_symbol
62 #undef obj_sec_sym_ok_for_reloc
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF. */
109 /* The default target format to use. */
111 mips_target_format ()
113 switch (OUTPUT_FLAVOR
)
115 case bfd_target_aout_flavour
:
116 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
117 case bfd_target_ecoff_flavour
:
118 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
119 case bfd_target_elf_flavour
:
120 return (target_big_endian
121 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
122 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
128 /* The name of the readonly data section. */
129 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
131 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
133 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
137 /* These variables are filled in with the masks of registers used.
138 The object format code reads them and puts them in the appropriate
140 unsigned long mips_gprmask
;
141 unsigned long mips_cprmask
[4];
143 /* MIPS ISA (Instruction Set Architecture) level (may be changed
144 temporarily using .set mipsN). */
145 static int mips_isa
= -1;
147 /* MIPS ISA we are using for this output file. */
148 static int file_mips_isa
;
150 /* Whether we are assembling for the mips16 processor. */
151 static int mips16
= -1;
153 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
154 static int mips_cpu
= -1;
156 /* Whether the 4650 instructions (mad/madu) are permitted. */
157 static int mips_4650
= -1;
159 /* Whether the 4010 instructions are permitted. */
160 static int mips_4010
= -1;
162 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
163 static int mips_4100
= -1;
165 /* start-sanitize-r5900 */
166 /* Whether Toshiba r5900 instructions are permitted. */
167 static int mips_5900
= -1;
168 /* end-sanitize-r5900 */
170 /* Whether the processor uses hardware interlocks, and thus does not
171 require nops to be inserted. */
172 static int interlocks
= -1;
174 /* As with "interlocks" this is used by hardware that has FP
175 (co-processor) interlocks. */
176 /* Itbl support may require additional care here. */
177 static int cop_interlocks
= -1;
179 /* MIPS PIC level. */
183 /* Do not generate PIC code. */
186 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
187 not sure what it is supposed to do. */
190 /* Generate PIC code as in the SVR4 MIPS ABI. */
193 /* Generate PIC code without using a global offset table: the data
194 segment has a maximum size of 64K, all data references are off
195 the $gp register, and all text references are PC relative. This
196 is used on some embedded systems. */
200 static enum mips_pic_level mips_pic
;
202 /* 1 if we should generate 32 bit offsets from the GP register in
203 SVR4_PIC mode. Currently has no meaning in other modes. */
204 static int mips_big_got
;
206 /* 1 if trap instructions should used for overflow rather than break
208 static int mips_trap
;
210 /* 1 if we should autoextend mips16 instructions. */
211 static int mips16_autoextend
= 1;
213 static int mips_warn_about_macros
;
214 static int mips_noreorder
;
215 static int mips_any_noreorder
;
216 static int mips_nomove
;
217 static int mips_noat
;
218 static int mips_nobopt
;
220 /* The size of the small data section. */
221 static int g_switch_value
= 8;
222 /* Whether the -G option was used. */
223 static int g_switch_seen
= 0;
228 /* If we can determine in advance that GP optimization won't be
229 possible, we can skip the relaxation stuff that tries to produce
230 GP-relative references. This makes delay slot optimization work
233 This function can only provide a guess, but it seems to work for
234 gcc output. If it guesses wrong, the only loss should be in
235 efficiency; it shouldn't introduce any bugs.
237 I don't know if a fix is needed for the SVR4_PIC mode. I've only
238 fixed it for the non-PIC mode. KR 95/04/07 */
239 static int nopic_need_relax
PARAMS ((symbolS
*));
241 /* handle of the OPCODE hash table */
242 static struct hash_control
*op_hash
= NULL
;
244 /* The opcode hash table we use for the mips16. */
245 static struct hash_control
*mips16_op_hash
= NULL
;
247 /* This array holds the chars that always start a comment. If the
248 pre-processor is disabled, these aren't very useful */
249 const char comment_chars
[] = "#";
251 /* This array holds the chars that only start a comment at the beginning of
252 a line. If the line seems to have the form '# 123 filename'
253 .line and .file directives will appear in the pre-processed output */
254 /* Note that input_file.c hand checks for '#' at the beginning of the
255 first line of the input file. This is because the compiler outputs
256 #NO_APP at the beginning of its output. */
257 /* Also note that C style comments are always supported. */
258 const char line_comment_chars
[] = "#";
260 /* This array holds machine specific line separator characters. */
261 const char line_separator_chars
[] = "";
263 /* Chars that can be used to separate mant from exp in floating point nums */
264 const char EXP_CHARS
[] = "eE";
266 /* Chars that mean this number is a floating point constant */
269 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
271 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
272 changed in read.c . Ideally it shouldn't have to know about it at all,
273 but nothing is ideal around here.
276 static char *insn_error
;
278 static int auto_align
= 1;
280 /* When outputting SVR4 PIC code, the assembler needs to know the
281 offset in the stack frame from which to restore the $gp register.
282 This is set by the .cprestore pseudo-op, and saved in this
284 static offsetT mips_cprestore_offset
= -1;
286 /* This is the register which holds the stack frame, as set by the
287 .frame pseudo-op. This is needed to implement .cprestore. */
288 static int mips_frame_reg
= SP
;
290 /* To output NOP instructions correctly, we need to keep information
291 about the previous two instructions. */
293 /* Whether we are optimizing. The default value of 2 means to remove
294 unneeded NOPs and swap branch instructions when possible. A value
295 of 1 means to not swap branches. A value of 0 means to always
297 static int mips_optimize
= 2;
299 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
300 equivalent to seeing no -g option at all. */
301 static int mips_debug
= 0;
303 /* The previous instruction. */
304 static struct mips_cl_insn prev_insn
;
306 /* The instruction before prev_insn. */
307 static struct mips_cl_insn prev_prev_insn
;
309 /* If we don't want information for prev_insn or prev_prev_insn, we
310 point the insn_mo field at this dummy integer. */
311 static const struct mips_opcode dummy_opcode
= { 0 };
313 /* Non-zero if prev_insn is valid. */
314 static int prev_insn_valid
;
316 /* The frag for the previous instruction. */
317 static struct frag
*prev_insn_frag
;
319 /* The offset into prev_insn_frag for the previous instruction. */
320 static long prev_insn_where
;
322 /* The reloc type for the previous instruction, if any. */
323 static bfd_reloc_code_real_type prev_insn_reloc_type
;
325 /* The reloc for the previous instruction, if any. */
326 static fixS
*prev_insn_fixp
;
328 /* Non-zero if the previous instruction was in a delay slot. */
329 static int prev_insn_is_delay_slot
;
331 /* Non-zero if the previous instruction was in a .set noreorder. */
332 static int prev_insn_unreordered
;
334 /* Non-zero if the previous instruction uses an extend opcode (if
336 static int prev_insn_extended
;
338 /* Non-zero if the previous previous instruction was in a .set
340 static int prev_prev_insn_unreordered
;
342 /* If this is set, it points to a frag holding nop instructions which
343 were inserted before the start of a noreorder section. If those
344 nops turn out to be unnecessary, the size of the frag can be
346 static fragS
*prev_nop_frag
;
348 /* The number of nop instructions we created in prev_nop_frag. */
349 static int prev_nop_frag_holds
;
351 /* The number of nop instructions that we know we need in
353 static int prev_nop_frag_required
;
355 /* The number of instructions we've seen since prev_nop_frag. */
356 static int prev_nop_frag_since
;
358 /* For ECOFF and ELF, relocations against symbols are done in two
359 parts, with a HI relocation and a LO relocation. Each relocation
360 has only 16 bits of space to store an addend. This means that in
361 order for the linker to handle carries correctly, it must be able
362 to locate both the HI and the LO relocation. This means that the
363 relocations must appear in order in the relocation table.
365 In order to implement this, we keep track of each unmatched HI
366 relocation. We then sort them so that they immediately precede the
367 corresponding LO relocation. */
372 struct mips_hi_fixup
*next
;
375 /* The section this fixup is in. */
379 /* The list of unmatched HI relocs. */
381 static struct mips_hi_fixup
*mips_hi_fixup_list
;
383 /* Map normal MIPS register numbers to mips16 register numbers. */
385 #define X ILLEGAL_REG
386 static const int mips32_to_16_reg_map
[] =
388 X
, X
, 2, 3, 4, 5, 6, 7,
389 X
, X
, X
, X
, X
, X
, X
, X
,
390 0, 1, X
, X
, X
, X
, X
, X
,
391 X
, X
, X
, X
, X
, X
, X
, X
395 /* Map mips16 register numbers to normal MIPS register numbers. */
397 static const int mips16_to_32_reg_map
[] =
399 16, 17, 2, 3, 4, 5, 6, 7
402 /* Since the MIPS does not have multiple forms of PC relative
403 instructions, we do not have to do relaxing as is done on other
404 platforms. However, we do have to handle GP relative addressing
405 correctly, which turns out to be a similar problem.
407 Every macro that refers to a symbol can occur in (at least) two
408 forms, one with GP relative addressing and one without. For
409 example, loading a global variable into a register generally uses
410 a macro instruction like this:
412 If i can be addressed off the GP register (this is true if it is in
413 the .sbss or .sdata section, or if it is known to be smaller than
414 the -G argument) this will generate the following instruction:
416 This instruction will use a GPREL reloc. If i can not be addressed
417 off the GP register, the following instruction sequence will be used:
420 In this case the first instruction will have a HI16 reloc, and the
421 second reloc will have a LO16 reloc. Both relocs will be against
424 The issue here is that we may not know whether i is GP addressable
425 until after we see the instruction that uses it. Therefore, we
426 want to be able to choose the final instruction sequence only at
427 the end of the assembly. This is similar to the way other
428 platforms choose the size of a PC relative instruction only at the
431 When generating position independent code we do not use GP
432 addressing in quite the same way, but the issue still arises as
433 external symbols and local symbols must be handled differently.
435 We handle these issues by actually generating both possible
436 instruction sequences. The longer one is put in a frag_var with
437 type rs_machine_dependent. We encode what to do with the frag in
438 the subtype field. We encode (1) the number of existing bytes to
439 replace, (2) the number of new bytes to use, (3) the offset from
440 the start of the existing bytes to the first reloc we must generate
441 (that is, the offset is applied from the start of the existing
442 bytes after they are replaced by the new bytes, if any), (4) the
443 offset from the start of the existing bytes to the second reloc,
444 (5) whether a third reloc is needed (the third reloc is always four
445 bytes after the second reloc), and (6) whether to warn if this
446 variant is used (this is sometimes needed if .set nomacro or .set
447 noat is in effect). All these numbers are reasonably small.
449 Generating two instruction sequences must be handled carefully to
450 ensure that delay slots are handled correctly. Fortunately, there
451 are a limited number of cases. When the second instruction
452 sequence is generated, append_insn is directed to maintain the
453 existing delay slot information, so it continues to apply to any
454 code after the second instruction sequence. This means that the
455 second instruction sequence must not impose any requirements not
456 required by the first instruction sequence.
458 These variant frags are then handled in functions called by the
459 machine independent code. md_estimate_size_before_relax returns
460 the final size of the frag. md_convert_frag sets up the final form
461 of the frag. tc_gen_reloc adjust the first reloc and adds a second
463 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
467 | (((reloc1) + 64) << 9) \
468 | (((reloc2) + 64) << 2) \
469 | ((reloc3) ? (1 << 1) : 0) \
471 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
472 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
473 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
474 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
475 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
476 #define RELAX_WARN(i) ((i) & 1)
478 /* For mips16 code, we use an entirely different form of relaxation.
479 mips16 supports two versions of most instructions which take
480 immediate values: a small one which takes some small value, and a
481 larger one which takes a 16 bit value. Since branches also follow
482 this pattern, relaxing these values is required.
484 We can assemble both mips16 and normal MIPS code in a single
485 object. Therefore, we need to support this type of relaxation at
486 the same time that we support the relaxation described above. We
487 use the high bit of the subtype field to distinguish these cases.
489 The information we store for this type of relaxation is the
490 argument code found in the opcode file for this relocation, whether
491 the user explicitly requested a small or extended form, and whether
492 the relocation is in a jump or jal delay slot. That tells us the
493 size of the value, and how it should be stored. We also store
494 whether the fragment is considered to be extended or not. We also
495 store whether this is known to be a branch to a different section,
496 whether we have tried to relax this frag yet, and whether we have
497 ever extended a PC relative fragment because of a shift count. */
498 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
501 | ((small) ? 0x100 : 0) \
502 | ((ext) ? 0x200 : 0) \
503 | ((dslot) ? 0x400 : 0) \
504 | ((jal_dslot) ? 0x800 : 0))
505 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
506 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
507 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
508 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
509 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
510 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
511 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
512 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
513 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
514 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
515 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
516 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
518 /* Prototypes for static functions. */
521 #define internalError() \
522 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
524 #define internalError() as_fatal ("MIPS internal Error");
527 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
529 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
530 unsigned int reg
, enum mips_regclass
class));
531 static int reg_needs_delay
PARAMS ((int));
532 static void append_insn
PARAMS ((char *place
,
533 struct mips_cl_insn
* ip
,
535 bfd_reloc_code_real_type r
,
537 static void mips_no_prev_insn
PARAMS ((int));
538 static void mips_emit_delays
PARAMS ((boolean
));
540 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
541 const char *name
, const char *fmt
,
544 static void macro_build ();
546 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
547 const char *, const char *,
549 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
550 expressionS
* ep
, int regnum
));
551 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
552 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
554 static void load_register
PARAMS ((int *, int, expressionS
*, int));
555 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
556 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
557 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
558 #ifdef LOSING_COMPILER
559 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
561 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
562 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
563 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
564 boolean
, boolean
, unsigned long *,
565 boolean
*, unsigned short *));
566 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
567 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
568 static symbolS
*get_symbol
PARAMS ((void));
569 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
570 static void s_align
PARAMS ((int));
571 static void s_change_sec
PARAMS ((int));
572 static void s_cons
PARAMS ((int));
573 static void s_float_cons
PARAMS ((int));
574 static void s_mips_globl
PARAMS ((int));
575 static void s_option
PARAMS ((int));
576 static void s_mipsset
PARAMS ((int));
577 static void s_abicalls
PARAMS ((int));
578 static void s_cpload
PARAMS ((int));
579 static void s_cprestore
PARAMS ((int));
580 static void s_gpword
PARAMS ((int));
581 static void s_cpadd
PARAMS ((int));
582 static void s_insn
PARAMS ((int));
583 static void md_obj_begin
PARAMS ((void));
584 static void md_obj_end
PARAMS ((void));
585 static long get_number
PARAMS ((void));
586 static void s_ent
PARAMS ((int));
587 static void s_mipsend
PARAMS ((int));
588 static void s_file
PARAMS ((int));
589 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
593 The following pseudo-ops from the Kane and Heinrich MIPS book
594 should be defined here, but are currently unsupported: .alias,
595 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
597 The following pseudo-ops from the Kane and Heinrich MIPS book are
598 specific to the type of debugging information being generated, and
599 should be defined by the object format: .aent, .begin, .bend,
600 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
603 The following pseudo-ops from the Kane and Heinrich MIPS book are
604 not MIPS CPU specific, but are also not specific to the object file
605 format. This file is probably the best place to define them, but
606 they are not currently supported: .asm0, .endr, .lab, .repeat,
607 .struct, .weakext. */
609 static const pseudo_typeS mips_pseudo_table
[] =
611 /* MIPS specific pseudo-ops. */
612 {"option", s_option
, 0},
613 {"set", s_mipsset
, 0},
614 {"rdata", s_change_sec
, 'r'},
615 {"sdata", s_change_sec
, 's'},
616 {"livereg", s_ignore
, 0},
617 {"abicalls", s_abicalls
, 0},
618 {"cpload", s_cpload
, 0},
619 {"cprestore", s_cprestore
, 0},
620 {"gpword", s_gpword
, 0},
621 {"cpadd", s_cpadd
, 0},
624 /* Relatively generic pseudo-ops that happen to be used on MIPS
626 {"asciiz", stringer
, 1},
627 {"bss", s_change_sec
, 'b'},
630 {"dword", s_cons
, 3},
632 /* These pseudo-ops are defined in read.c, but must be overridden
633 here for one reason or another. */
634 {"align", s_align
, 0},
636 {"data", s_change_sec
, 'd'},
637 {"double", s_float_cons
, 'd'},
638 {"float", s_float_cons
, 'f'},
639 {"globl", s_mips_globl
, 0},
640 {"global", s_mips_globl
, 0},
641 {"hword", s_cons
, 1},
646 {"short", s_cons
, 1},
647 {"single", s_float_cons
, 'f'},
648 {"text", s_change_sec
, 't'},
653 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
654 /* These pseudo-ops should be defined by the object file format.
655 However, a.out doesn't support them, so we have versions here. */
657 {"bgnb", s_ignore
, 0},
658 {"end", s_mipsend
, 0},
659 {"endb", s_ignore
, 0},
662 {"fmask", s_ignore
, 'F'},
663 {"frame", s_ignore
, 0},
664 {"loc", s_ignore
, 0},
665 {"mask", s_ignore
, 'R'},
666 {"verstamp", s_ignore
, 0},
670 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
675 pop_insert (mips_pseudo_table
);
676 if (! ECOFF_DEBUGGING
)
677 pop_insert (mips_nonecoff_pseudo_table
);
680 /* Symbols labelling the current insn. */
682 struct insn_label_list
684 struct insn_label_list
*next
;
688 static struct insn_label_list
*insn_labels
;
689 static struct insn_label_list
*free_insn_labels
;
691 static void mips_clear_insn_labels
PARAMS ((void));
694 mips_clear_insn_labels ()
696 register struct insn_label_list
**pl
;
698 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
704 static char *expr_end
;
706 /* Expressions which appear in instructions. These are set by
709 static expressionS imm_expr
;
710 static expressionS offset_expr
;
712 /* Relocs associated with imm_expr and offset_expr. */
714 static bfd_reloc_code_real_type imm_reloc
;
715 static bfd_reloc_code_real_type offset_reloc
;
717 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
719 static boolean imm_unmatched_hi
;
721 /* These are set by mips16_ip if an explicit extension is used. */
723 static boolean mips16_small
, mips16_ext
;
726 * This function is called once, at assembler startup time. It should
727 * set up all the tables, etc. that the MD part of the assembler will need.
733 register const char *retval
= NULL
;
734 register unsigned int i
= 0;
742 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
744 a
= xmalloc (sizeof TARGET_CPU
);
745 strcpy (a
, TARGET_CPU
);
746 a
[(sizeof TARGET_CPU
) - 3] = '\0';
750 if (strcmp (cpu
, "mips") == 0)
756 else if (strcmp (cpu
, "r6000") == 0
757 || strcmp (cpu
, "mips2") == 0)
763 else if (strcmp (cpu
, "mips64") == 0
764 || strcmp (cpu
, "r4000") == 0
765 || strcmp (cpu
, "mips3") == 0)
771 else if (strcmp (cpu
, "r4400") == 0)
777 else if (strcmp (cpu
, "mips64orion") == 0
778 || strcmp (cpu
, "r4600") == 0)
784 else if (strcmp (cpu
, "r4650") == 0)
792 else if (strcmp (cpu
, "mips64vr4300") == 0)
798 else if (strcmp (cpu
, "mips64vr4100") == 0)
806 else if (strcmp (cpu
, "r4010") == 0)
814 else if (strcmp (cpu
, "r5000") == 0
815 || strcmp (cpu
, "mips64vr5000") == 0)
821 /* start-sanitize-r5900 */
822 else if (strcmp (cpu
, "r5900") == 0
823 || strcmp (cpu
, "mips64vr5900") == 0
824 || strcmp (cpu
, "mips64vr5900el") == 0)
832 /* end-sanitize-r5900 */
833 else if (strcmp (cpu
, "r8000") == 0
834 || strcmp (cpu
, "mips4") == 0)
840 else if (strcmp (cpu
, "r10000") == 0)
846 else if (strcmp (cpu
, "mips16") == 0)
850 mips_cpu
= 0; /* FIXME */
865 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
880 /* start-sanitize-r5900 */
883 /* end-sanitize-r5900 */
885 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
890 /* Itbl support may require additional care here. */
891 if (mips_cpu
== 4300)
896 if (mips_isa
< 2 && mips_trap
)
897 as_bad ("trap exception not supported at ISA 1");
902 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
905 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
908 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
911 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
915 as_warn ("Could not set architecture and machine");
917 file_mips_isa
= mips_isa
;
919 op_hash
= hash_new ();
921 for (i
= 0; i
< NUMOPCODES
;)
923 const char *name
= mips_opcodes
[i
].name
;
925 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
928 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
929 mips_opcodes
[i
].name
, retval
);
930 as_fatal ("Broken assembler. No assembly attempted.");
934 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
935 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
936 != mips_opcodes
[i
].match
))
938 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
939 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
940 as_fatal ("Broken assembler. No assembly attempted.");
944 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
947 mips16_op_hash
= hash_new ();
950 while (i
< bfd_mips16_num_opcodes
)
952 const char *name
= mips16_opcodes
[i
].name
;
954 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
956 as_fatal ("internal error: can't hash `%s': %s\n",
957 mips16_opcodes
[i
].name
, retval
);
960 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
961 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
962 != mips16_opcodes
[i
].match
))
963 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
964 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
967 while (i
< bfd_mips16_num_opcodes
968 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
971 /* We add all the general register names to the symbol table. This
972 helps us detect invalid uses of them. */
973 for (i
= 0; i
< 32; i
++)
977 sprintf (buf
, "$%d", i
);
978 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
979 &zero_address_frag
));
981 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
982 &zero_address_frag
));
983 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
984 &zero_address_frag
));
985 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
986 &zero_address_frag
));
987 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
988 &zero_address_frag
));
989 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
990 &zero_address_frag
));
991 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
992 &zero_address_frag
));
993 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
994 &zero_address_frag
));
996 mips_no_prev_insn (false);
1000 mips_cprmask
[1] = 0;
1001 mips_cprmask
[2] = 0;
1002 mips_cprmask
[3] = 0;
1004 /* set the default alignment for the text section (2**2) */
1005 record_alignment (text_section
, 2);
1007 if (USE_GLOBAL_POINTER_OPT
)
1008 bfd_set_gp_size (stdoutput
, g_switch_value
);
1010 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1012 /* On a native system, sections must be aligned to 16 byte
1013 boundaries. When configured for an embedded ELF target, we
1015 if (strcmp (TARGET_OS
, "elf") != 0)
1017 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1018 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1019 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1022 /* Create a .reginfo section for register masks and a .mdebug
1023 section for debugging information. */
1031 subseg
= now_subseg
;
1033 /* The ABI says this section should be loaded so that the
1034 running program can access it. However, we don't load it
1035 if we are configured for an embedded target */
1036 flags
= SEC_READONLY
| SEC_DATA
;
1037 if (strcmp (TARGET_OS
, "elf") != 0)
1038 flags
|= SEC_ALLOC
| SEC_LOAD
;
1042 sec
= subseg_new (".reginfo", (subsegT
) 0);
1045 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1046 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1049 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1054 /* The 64-bit ABI uses a .MIPS.options section rather than
1055 .reginfo section. */
1056 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1057 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1058 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1061 /* Set up the option header. */
1063 Elf_Internal_Options opthdr
;
1066 opthdr
.kind
= ODK_REGINFO
;
1067 opthdr
.size
= (sizeof (Elf_External_Options
)
1068 + sizeof (Elf64_External_RegInfo
));
1071 f
= frag_more (sizeof (Elf_External_Options
));
1072 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1073 (Elf_External_Options
*) f
);
1075 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1080 if (ECOFF_DEBUGGING
)
1082 sec
= subseg_new (".mdebug", (subsegT
) 0);
1083 (void) bfd_set_section_flags (stdoutput
, sec
,
1084 SEC_HAS_CONTENTS
| SEC_READONLY
);
1085 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1088 subseg_set (seg
, subseg
);
1092 if (! ECOFF_DEBUGGING
)
1099 if (! ECOFF_DEBUGGING
)
1107 struct mips_cl_insn insn
;
1109 imm_expr
.X_op
= O_absent
;
1110 imm_reloc
= BFD_RELOC_UNUSED
;
1111 imm_unmatched_hi
= false;
1112 offset_expr
.X_op
= O_absent
;
1113 offset_reloc
= BFD_RELOC_UNUSED
;
1116 mips16_ip (str
, &insn
);
1119 mips_ip (str
, &insn
);
1120 DBG(("returned from mips_ip(%s) insn_opcode = 0x%x\n",
1121 str
, insn
.insn_opcode
));
1126 as_bad ("%s `%s'", insn_error
, str
);
1130 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1133 mips16_macro (&insn
);
1139 if (imm_expr
.X_op
!= O_absent
)
1140 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1142 else if (offset_expr
.X_op
!= O_absent
)
1143 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1145 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1149 /* See whether instruction IP reads register REG. CLASS is the type
1153 insn_uses_reg (ip
, reg
, class)
1154 struct mips_cl_insn
*ip
;
1156 enum mips_regclass
class;
1158 if (class == MIPS16_REG
)
1161 reg
= mips16_to_32_reg_map
[reg
];
1162 class = MIPS_GR_REG
;
1165 /* Don't report on general register 0, since it never changes. */
1166 if (class == MIPS_GR_REG
&& reg
== 0)
1169 if (class == MIPS_FP_REG
)
1172 /* If we are called with either $f0 or $f1, we must check $f0.
1173 This is not optimal, because it will introduce an unnecessary
1174 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1175 need to distinguish reading both $f0 and $f1 or just one of
1176 them. Note that we don't have to check the other way,
1177 because there is no instruction that sets both $f0 and $f1
1178 and requires a delay. */
1179 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1180 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1181 == (reg
&~ (unsigned) 1)))
1183 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1184 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1185 == (reg
&~ (unsigned) 1)))
1190 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1191 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1193 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1194 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1199 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1200 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1201 & MIPS16OP_MASK_RX
)]
1204 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1205 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1206 & MIPS16OP_MASK_RY
)]
1209 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1210 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1211 & MIPS16OP_MASK_MOVE32Z
)]
1214 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1216 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1218 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1220 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1221 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1222 & MIPS16OP_MASK_REGR32
) == reg
)
1229 /* This function returns true if modifying a register requires a
1233 reg_needs_delay (reg
)
1236 unsigned long prev_pinfo
;
1238 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1239 if (! mips_noreorder
1241 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1243 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1245 /* A load from a coprocessor or from memory. All load
1246 delays delay the use of general register rt for one
1247 instruction on the r3000. The r6000 and r4000 use
1249 /* Itbl support may require additional care here. */
1250 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1251 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1258 /* Output an instruction. PLACE is where to put the instruction; if
1259 it is NULL, this uses frag_more to get room. IP is the instruction
1260 information. ADDRESS_EXPR is an operand of the instruction to be
1261 used with RELOC_TYPE. */
1264 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1266 struct mips_cl_insn
*ip
;
1267 expressionS
*address_expr
;
1268 bfd_reloc_code_real_type reloc_type
;
1269 boolean unmatched_hi
;
1271 register unsigned long prev_pinfo
, pinfo
;
1276 /* Mark instruction labels in mips16 mode. This permits the linker
1277 to handle them specially, such as generating jalx instructions
1278 when needed. We also make them odd for the duration of the
1279 assembly, in order to generate the right sort of code. We will
1280 make them even in the adjust_symtab routine, while leaving them
1281 marked. This is convenient for the debugger and the
1282 disassembler. The linker knows to make them odd again. */
1285 struct insn_label_list
*l
;
1287 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1290 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1291 S_SET_OTHER (l
->label
, STO_MIPS16
);
1293 ++l
->label
->sy_value
.X_add_number
;
1297 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1298 pinfo
= ip
->insn_mo
->pinfo
;
1300 if (place
== NULL
&& (! mips_noreorder
|| prev_nop_frag
!= NULL
))
1304 /* If the previous insn required any delay slots, see if we need
1305 to insert a NOP or two. There are eight kinds of possible
1306 hazards, of which an instruction can have at most one type.
1307 (1) a load from memory delay
1308 (2) a load from a coprocessor delay
1309 (3) an unconditional branch delay
1310 (4) a conditional branch delay
1311 (5) a move to coprocessor register delay
1312 (6) a load coprocessor register from memory delay
1313 (7) a coprocessor condition code delay
1314 (8) a HI/LO special register delay
1316 There are a lot of optimizations we could do that we don't.
1317 In particular, we do not, in general, reorder instructions.
1318 If you use gcc with optimization, it will reorder
1319 instructions and generally do much more optimization then we
1320 do here; repeating all that work in the assembler would only
1321 benefit hand written assembly code, and does not seem worth
1324 /* This is how a NOP is emitted. */
1325 #define emit_nop() \
1327 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1328 : md_number_to_chars (frag_more (4), 0, 4))
1330 /* The previous insn might require a delay slot, depending upon
1331 the contents of the current insn. */
1334 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1335 && ! cop_interlocks
)
1337 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1339 /* A load from a coprocessor or from memory. All load
1340 delays delay the use of general register rt for one
1341 instruction on the r3000. The r6000 and r4000 use
1343 /* Itbl support may require additional care here. */
1344 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1345 if (mips_optimize
== 0
1346 || insn_uses_reg (ip
,
1347 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1354 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1355 && ! cop_interlocks
)
1357 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1359 /* A generic coprocessor delay. The previous instruction
1360 modified a coprocessor general or control register. If
1361 it modified a control register, we need to avoid any
1362 coprocessor instruction (this is probably not always
1363 required, but it sometimes is). If it modified a general
1364 register, we avoid using that register.
1366 On the r6000 and r4000 loading a coprocessor register
1367 from memory is interlocked, and does not require a delay.
1369 This case is not handled very well. There is no special
1370 knowledge of CP0 handling, and the coprocessors other
1371 than the floating point unit are not distinguished at
1373 /* Itbl support may require additional care here. FIXME!
1374 Need to modify this to include knowledge about
1375 user specified delays! */
1376 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1378 if (mips_optimize
== 0
1379 || insn_uses_reg (ip
,
1380 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1385 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1387 if (mips_optimize
== 0
1388 || insn_uses_reg (ip
,
1389 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1396 /* We don't know exactly what the previous instruction
1397 does. If the current instruction uses a coprocessor
1398 register, we must insert a NOP. If previous
1399 instruction may set the condition codes, and the
1400 current instruction uses them, we must insert two
1402 /* Itbl support may require additional care here. */
1403 if (mips_optimize
== 0
1404 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1405 && (pinfo
& INSN_READ_COND_CODE
)))
1407 else if (pinfo
& INSN_COP
)
1413 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1414 && ! cop_interlocks
)
1416 /* The previous instruction sets the coprocessor condition
1417 codes, but does not require a general coprocessor delay
1418 (this means it is a floating point comparison
1419 instruction). If this instruction uses the condition
1420 codes, we need to insert a single NOP. */
1421 /* Itbl support may require additional care here. */
1422 if (mips_optimize
== 0
1423 || (pinfo
& INSN_READ_COND_CODE
))
1426 else if (prev_pinfo
& INSN_READ_LO
)
1428 /* The previous instruction reads the LO register; if the
1429 current instruction writes to the LO register, we must
1430 insert two NOPS. Some newer processors have interlocks. */
1432 && (mips_optimize
== 0
1433 || (pinfo
& INSN_WRITE_LO
)))
1436 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1438 /* The previous instruction reads the HI register; if the
1439 current instruction writes to the HI register, we must
1440 insert a NOP. Some newer processors have interlocks. */
1442 && (mips_optimize
== 0
1443 || (pinfo
& INSN_WRITE_HI
)))
1447 /* If the previous instruction was in a noreorder section, then
1448 we don't want to insert the nop after all. */
1449 /* Itbl support may require additional care here. */
1450 if (prev_insn_unreordered
)
1453 /* There are two cases which require two intervening
1454 instructions: 1) setting the condition codes using a move to
1455 coprocessor instruction which requires a general coprocessor
1456 delay and then reading the condition codes 2) reading the HI
1457 or LO register and then writing to it (except on processors
1458 which have interlocks). If we are not already emitting a NOP
1459 instruction, we must check for these cases compared to the
1460 instruction previous to the previous instruction. */
1463 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1464 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1465 && (pinfo
& INSN_READ_COND_CODE
)
1466 && ! cop_interlocks
)
1467 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1468 && (pinfo
& INSN_WRITE_LO
)
1470 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1471 && (pinfo
& INSN_WRITE_HI
)
1477 if (prev_prev_insn_unreordered
)
1480 if (prev_prev_nop
&& nops
== 0)
1483 /* If we are being given a nop instruction, don't bother with
1484 one of the nops we would otherwise output. This will only
1485 happen when a nop instruction is used with mips_optimize set
1489 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1492 /* Now emit the right number of NOP instructions. */
1493 if (nops
> 0 && ! mips_noreorder
)
1496 unsigned long old_frag_offset
;
1498 struct insn_label_list
*l
;
1500 old_frag
= frag_now
;
1501 old_frag_offset
= frag_now_fix ();
1503 for (i
= 0; i
< nops
; i
++)
1508 listing_prev_line ();
1509 /* We may be at the start of a variant frag. In case we
1510 are, make sure there is enough space for the frag
1511 after the frags created by listing_prev_line. The
1512 argument to frag_grow here must be at least as large
1513 as the argument to all other calls to frag_grow in
1514 this file. We don't have to worry about being in the
1515 middle of a variant frag, because the variants insert
1516 all needed nop instructions themselves. */
1520 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1522 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1523 l
->label
->sy_frag
= frag_now
;
1524 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1525 /* mips16 text labels are stored as odd. */
1527 ++l
->label
->sy_value
.X_add_number
;
1530 #ifndef NO_ECOFF_DEBUGGING
1531 if (ECOFF_DEBUGGING
)
1532 ecoff_fix_loc (old_frag
, old_frag_offset
);
1535 else if (prev_nop_frag
!= NULL
)
1537 /* We have a frag holding nops we may be able to remove. If
1538 we don't need any nops, we can decrease the size of
1539 prev_nop_frag by the size of one instruction. If we do
1540 need some nops, we count them in prev_nops_required. */
1541 if (prev_nop_frag_since
== 0)
1545 prev_nop_frag
->fr_fix
-= mips16
? 2 : 4;
1546 --prev_nop_frag_holds
;
1549 prev_nop_frag_required
+= nops
;
1553 if (prev_prev_nop
== 0)
1555 prev_nop_frag
->fr_fix
-= mips16
? 2 : 4;
1556 --prev_nop_frag_holds
;
1559 ++prev_nop_frag_required
;
1562 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1563 prev_nop_frag
= NULL
;
1565 ++prev_nop_frag_since
;
1567 /* Sanity check: by the time we reach the second instruction
1568 after prev_nop_frag, we should have used up all the nops
1569 one way or another. */
1570 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1574 if (reloc_type
> BFD_RELOC_UNUSED
)
1576 /* We need to set up a variant frag. */
1577 assert (mips16
&& address_expr
!= NULL
);
1578 f
= frag_var (rs_machine_dependent
, 4, 0,
1579 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1580 mips16_small
, mips16_ext
,
1582 & INSN_UNCOND_BRANCH_DELAY
),
1583 (prev_insn_reloc_type
1584 == BFD_RELOC_MIPS16_JMP
)),
1585 make_expr_symbol (address_expr
), (offsetT
) 0,
1588 else if (place
!= NULL
)
1590 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1592 /* Make sure there is enough room to swap this instruction with
1593 a following jump instruction. */
1601 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1602 as_warn ("extended instruction in delay slot");
1608 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1610 if (address_expr
->X_op
== O_constant
)
1615 ip
->insn_opcode
|= address_expr
->X_add_number
;
1618 case BFD_RELOC_LO16
:
1619 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1622 case BFD_RELOC_MIPS_JMP
:
1623 if ((address_expr
->X_add_number
& 3) != 0)
1624 as_bad ("jump to misaligned address (0x%lx)",
1625 (unsigned long) address_expr
->X_add_number
);
1626 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1629 case BFD_RELOC_MIPS16_JMP
:
1630 if ((address_expr
->X_add_number
& 3) != 0)
1631 as_bad ("jump to misaligned address (0x%lx)",
1632 (unsigned long) address_expr
->X_add_number
);
1634 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1635 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1636 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1639 case BFD_RELOC_16_PCREL_S2
:
1649 /* Don't generate a reloc if we are writing into a variant
1653 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1655 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1659 struct mips_hi_fixup
*hi_fixup
;
1661 assert (reloc_type
== BFD_RELOC_HI16_S
);
1662 hi_fixup
= ((struct mips_hi_fixup
*)
1663 xmalloc (sizeof (struct mips_hi_fixup
)));
1664 hi_fixup
->fixp
= fixp
;
1665 hi_fixup
->seg
= now_seg
;
1666 hi_fixup
->next
= mips_hi_fixup_list
;
1667 mips_hi_fixup_list
= hi_fixup
;
1674 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1675 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1677 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1678 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1684 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1687 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1690 /* Update the register mask information. */
1693 if (pinfo
& INSN_WRITE_GPR_D
)
1694 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1695 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1696 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1697 if (pinfo
& INSN_READ_GPR_S
)
1698 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1699 if (pinfo
& INSN_WRITE_GPR_31
)
1700 mips_gprmask
|= 1 << 31;
1701 if (pinfo
& INSN_WRITE_FPR_D
)
1702 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1703 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1704 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1705 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1706 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1707 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1708 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1709 if (pinfo
& INSN_COP
)
1711 /* We don't keep enough information to sort these cases out.
1712 The itbl support does keep this information however, although
1713 we currently don't support itbl fprmats as part of the cop
1714 instruction. May want to add this support in the future. */
1716 /* Never set the bit for $0, which is always zero. */
1717 mips_gprmask
&=~ 1 << 0;
1721 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1722 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1723 & MIPS16OP_MASK_RX
);
1724 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1725 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1726 & MIPS16OP_MASK_RY
);
1727 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1728 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1729 & MIPS16OP_MASK_RZ
);
1730 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1731 mips_gprmask
|= 1 << TREG
;
1732 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1733 mips_gprmask
|= 1 << SP
;
1734 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1735 mips_gprmask
|= 1 << RA
;
1736 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1737 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1738 if (pinfo
& MIPS16_INSN_READ_Z
)
1739 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1740 & MIPS16OP_MASK_MOVE32Z
);
1741 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1742 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1743 & MIPS16OP_MASK_REGR32
);
1746 if (place
== NULL
&& ! mips_noreorder
)
1748 /* Filling the branch delay slot is more complex. We try to
1749 switch the branch with the previous instruction, which we can
1750 do if the previous instruction does not set up a condition
1751 that the branch tests and if the branch is not itself the
1752 target of any branch. */
1753 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1754 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1756 if (mips_optimize
< 2
1757 /* If we have seen .set volatile or .set nomove, don't
1760 /* If we had to emit any NOP instructions, then we
1761 already know we can not swap. */
1763 /* If we don't even know the previous insn, we can not
1765 || ! prev_insn_valid
1766 /* If the previous insn is already in a branch delay
1767 slot, then we can not swap. */
1768 || prev_insn_is_delay_slot
1769 /* If the previous previous insn was in a .set
1770 noreorder, we can't swap. Actually, the MIPS
1771 assembler will swap in this situation. However, gcc
1772 configured -with-gnu-as will generate code like
1778 in which we can not swap the bne and INSN. If gcc is
1779 not configured -with-gnu-as, it does not output the
1780 .set pseudo-ops. We don't have to check
1781 prev_insn_unreordered, because prev_insn_valid will
1782 be 0 in that case. We don't want to use
1783 prev_prev_insn_valid, because we do want to be able
1784 to swap at the start of a function. */
1785 || prev_prev_insn_unreordered
1786 /* If the branch is itself the target of a branch, we
1787 can not swap. We cheat on this; all we check for is
1788 whether there is a label on this instruction. If
1789 there are any branches to anything other than a
1790 label, users must use .set noreorder. */
1791 || insn_labels
!= NULL
1792 /* If the previous instruction is in a variant frag, we
1793 can not do the swap. This does not apply to the
1794 mips16, which uses variant frags for different
1797 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1798 /* If the branch reads the condition codes, we don't
1799 even try to swap, because in the sequence
1804 we can not swap, and I don't feel like handling that
1808 && (pinfo
& INSN_READ_COND_CODE
))
1809 /* We can not swap with an instruction that requires a
1810 delay slot, becase the target of the branch might
1811 interfere with that instruction. */
1815 /* Itbl support may require additional care here. */
1816 & (INSN_LOAD_COPROC_DELAY
1817 | INSN_COPROC_MOVE_DELAY
1818 | INSN_WRITE_COND_CODE
)))
1826 & (INSN_LOAD_MEMORY_DELAY
1827 /* Itbl support may require additional care here. */
1828 | INSN_COPROC_MEMORY_DELAY
)))
1829 /* We can not swap with a branch instruction. */
1831 & (INSN_UNCOND_BRANCH_DELAY
1832 | INSN_COND_BRANCH_DELAY
1833 | INSN_COND_BRANCH_LIKELY
))
1834 /* We do not swap with a trap instruction, since it
1835 complicates trap handlers to have the trap
1836 instruction be in a delay slot. */
1837 || (prev_pinfo
& INSN_TRAP
)
1838 /* If the branch reads a register that the previous
1839 instruction sets, we can not swap. */
1841 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1842 && insn_uses_reg (ip
,
1843 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1847 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1848 && insn_uses_reg (ip
,
1849 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1853 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1854 && insn_uses_reg (ip
,
1855 ((prev_insn
.insn_opcode
1857 & MIPS16OP_MASK_RX
),
1859 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1860 && insn_uses_reg (ip
,
1861 ((prev_insn
.insn_opcode
1863 & MIPS16OP_MASK_RY
),
1865 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1866 && insn_uses_reg (ip
,
1867 ((prev_insn
.insn_opcode
1869 & MIPS16OP_MASK_RZ
),
1871 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1872 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1873 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1874 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1875 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1876 && insn_uses_reg (ip
,
1877 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1880 /* If the branch writes a register that the previous
1881 instruction sets, we can not swap (we know that
1882 branches write only to RD or to $31). */
1884 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1885 && (((pinfo
& INSN_WRITE_GPR_D
)
1886 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1887 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1888 || ((pinfo
& INSN_WRITE_GPR_31
)
1889 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1893 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1894 && (((pinfo
& INSN_WRITE_GPR_D
)
1895 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1896 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1897 || ((pinfo
& INSN_WRITE_GPR_31
)
1898 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1902 && (pinfo
& MIPS16_INSN_WRITE_31
)
1903 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1904 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1905 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1907 /* If the branch writes a register that the previous
1908 instruction reads, we can not swap (we know that
1909 branches only write to RD or to $31). */
1911 && (pinfo
& INSN_WRITE_GPR_D
)
1912 && insn_uses_reg (&prev_insn
,
1913 ((ip
->insn_opcode
>> OP_SH_RD
)
1917 && (pinfo
& INSN_WRITE_GPR_31
)
1918 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1920 && (pinfo
& MIPS16_INSN_WRITE_31
)
1921 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1922 /* If we are generating embedded PIC code, the branch
1923 might be expanded into a sequence which uses $at, so
1924 we can't swap with an instruction which reads it. */
1925 || (mips_pic
== EMBEDDED_PIC
1926 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1927 /* If the previous previous instruction has a load
1928 delay, and sets a register that the branch reads, we
1932 /* Itbl support may require additional care here. */
1933 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1935 && (prev_prev_insn
.insn_mo
->pinfo
1936 & INSN_LOAD_MEMORY_DELAY
)))
1937 && insn_uses_reg (ip
,
1938 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1941 /* If one instruction sets a condition code and the
1942 other one uses a condition code, we can not swap. */
1943 || ((pinfo
& INSN_READ_COND_CODE
)
1944 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1945 || ((pinfo
& INSN_WRITE_COND_CODE
)
1946 && (prev_pinfo
& INSN_READ_COND_CODE
))
1947 /* If the previous instruction uses the PC, we can not
1950 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1951 /* If the previous instruction was extended, we can not
1953 || (mips16
&& prev_insn_extended
)
1954 /* If the previous instruction had a fixup in mips16
1955 mode, we can not swap. This normally means that the
1956 previous instruction was a 4 byte branch anyhow. */
1957 || (mips16
&& prev_insn_fixp
))
1959 /* We could do even better for unconditional branches to
1960 portions of this object file; we could pick up the
1961 instruction at the destination, put it in the delay
1962 slot, and bump the destination address. */
1964 /* Update the previous insn information. */
1965 prev_prev_insn
= *ip
;
1966 prev_insn
.insn_mo
= &dummy_opcode
;
1970 /* It looks like we can actually do the swap. */
1976 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1977 memcpy (temp
, prev_f
, 4);
1978 memcpy (prev_f
, f
, 4);
1979 memcpy (f
, temp
, 4);
1982 prev_insn_fixp
->fx_frag
= frag_now
;
1983 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1987 fixp
->fx_frag
= prev_insn_frag
;
1988 fixp
->fx_where
= prev_insn_where
;
1996 assert (prev_insn_fixp
== NULL
);
1997 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1998 memcpy (temp
, prev_f
, 2);
1999 memcpy (prev_f
, f
, 2);
2000 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2002 assert (reloc_type
== BFD_RELOC_UNUSED
);
2003 memcpy (f
, temp
, 2);
2007 memcpy (f
, f
+ 2, 2);
2008 memcpy (f
+ 2, temp
, 2);
2012 fixp
->fx_frag
= prev_insn_frag
;
2013 fixp
->fx_where
= prev_insn_where
;
2017 /* Update the previous insn information; leave prev_insn
2019 prev_prev_insn
= *ip
;
2021 prev_insn_is_delay_slot
= 1;
2023 /* If that was an unconditional branch, forget the previous
2024 insn information. */
2025 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2027 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2028 prev_insn
.insn_mo
= &dummy_opcode
;
2031 prev_insn_fixp
= NULL
;
2032 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2033 prev_insn_extended
= 0;
2035 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2037 /* We don't yet optimize a branch likely. What we should do
2038 is look at the target, copy the instruction found there
2039 into the delay slot, and increment the branch to jump to
2040 the next instruction. */
2042 /* Update the previous insn information. */
2043 prev_prev_insn
= *ip
;
2044 prev_insn
.insn_mo
= &dummy_opcode
;
2045 prev_insn_fixp
= NULL
;
2046 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2047 prev_insn_extended
= 0;
2051 /* Update the previous insn information. */
2053 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2055 prev_prev_insn
= prev_insn
;
2058 /* Any time we see a branch, we always fill the delay slot
2059 immediately; since this insn is not a branch, we know it
2060 is not in a delay slot. */
2061 prev_insn_is_delay_slot
= 0;
2063 prev_insn_fixp
= fixp
;
2064 prev_insn_reloc_type
= reloc_type
;
2066 prev_insn_extended
= (ip
->use_extend
2067 || reloc_type
> BFD_RELOC_UNUSED
);
2070 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2071 prev_insn_unreordered
= 0;
2072 prev_insn_frag
= frag_now
;
2073 prev_insn_where
= f
- frag_now
->fr_literal
;
2074 prev_insn_valid
= 1;
2076 else if (place
== NULL
)
2078 /* We need to record a bit of information even when we are not
2079 reordering, in order to determine the base address for mips16
2080 PC relative relocs. */
2081 prev_prev_insn
= prev_insn
;
2083 prev_insn_reloc_type
= reloc_type
;
2084 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2085 prev_insn_unreordered
= 1;
2088 /* We just output an insn, so the next one doesn't have a label. */
2089 mips_clear_insn_labels ();
2092 /* This function forgets that there was any previous instruction or
2093 label. If PRESERVE is non-zero, it remembers enough information to
2094 know whether nops are needed before a noreorder section. */
2097 mips_no_prev_insn (preserve
)
2102 prev_insn
.insn_mo
= &dummy_opcode
;
2103 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2104 prev_nop_frag
= NULL
;
2105 prev_nop_frag_holds
= 0;
2106 prev_nop_frag_required
= 0;
2107 prev_nop_frag_since
= 0;
2109 prev_insn_valid
= 0;
2110 prev_insn_is_delay_slot
= 0;
2111 prev_insn_unreordered
= 0;
2112 prev_insn_extended
= 0;
2113 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2114 prev_prev_insn_unreordered
= 0;
2115 mips_clear_insn_labels ();
2118 /* This function must be called whenever we turn on noreorder or emit
2119 something other than instructions. It inserts any NOPS which might
2120 be needed by the previous instruction, and clears the information
2121 kept for the previous instructions. The INSNS parameter is true if
2122 instructions are to follow. */
2125 mips_emit_delays (insns
)
2128 if (! mips_noreorder
)
2135 && (! cop_interlocks
2136 && (prev_insn
.insn_mo
->pinfo
2137 & (INSN_LOAD_COPROC_DELAY
2138 | INSN_COPROC_MOVE_DELAY
2139 | INSN_WRITE_COND_CODE
))))
2141 && (prev_insn
.insn_mo
->pinfo
2146 && (prev_insn
.insn_mo
->pinfo
2147 & (INSN_LOAD_MEMORY_DELAY
2148 | INSN_COPROC_MEMORY_DELAY
))))
2150 /* Itbl support may require additional care here. */
2154 && (! cop_interlocks
2155 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2157 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2158 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2161 if (prev_insn_unreordered
)
2166 && (! cop_interlocks
2167 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2169 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2170 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2172 /* Itbl support may require additional care here. */
2173 if (! prev_prev_insn_unreordered
)
2179 struct insn_label_list
*l
;
2183 /* Record the frag which holds the nop instructions, so
2184 that we can remove them if we don't need them. */
2185 frag_grow (mips16
? nops
* 2 : nops
* 4);
2186 prev_nop_frag
= frag_now
;
2187 prev_nop_frag_holds
= nops
;
2188 prev_nop_frag_required
= 0;
2189 prev_nop_frag_since
= 0;
2192 for (; nops
> 0; --nops
)
2197 /* Move on to a new frag, so that it is safe to simply
2198 decrease the size of prev_nop_frag. */
2199 frag_wane (frag_now
);
2203 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2205 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2206 l
->label
->sy_frag
= frag_now
;
2207 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2208 /* mips16 text labels are stored as odd. */
2210 ++l
->label
->sy_value
.X_add_number
;
2215 /* Mark instruction labels in mips16 mode. This permits the linker
2216 to handle them specially, such as generating jalx instructions
2217 when needed. We also make them odd for the duration of the
2218 assembly, in order to generate the right sort of code. We will
2219 make them even in the adjust_symtab routine, while leaving them
2220 marked. This is convenient for the debugger and the
2221 disassembler. The linker knows to make them odd again. */
2222 if (mips16
&& insns
)
2224 struct insn_label_list
*l
;
2226 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2229 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2230 S_SET_OTHER (l
->label
, STO_MIPS16
);
2232 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2233 ++l
->label
->sy_value
.X_add_number
;
2237 mips_no_prev_insn (insns
);
2240 /* Build an instruction created by a macro expansion. This is passed
2241 a pointer to the count of instructions created so far, an
2242 expression, the name of the instruction to build, an operand format
2243 string, and corresponding arguments. */
2247 macro_build (char *place
,
2255 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2264 struct mips_cl_insn insn
;
2265 bfd_reloc_code_real_type r
;
2269 va_start (args
, fmt
);
2275 * If the macro is about to expand into a second instruction,
2276 * print a warning if needed. We need to pass ip as a parameter
2277 * to generate a better warning message here...
2279 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2280 as_warn ("Macro instruction expanded into multiple instructions");
2283 *counter
+= 1; /* bump instruction counter */
2287 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2292 r
= BFD_RELOC_UNUSED
;
2293 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2294 assert (insn
.insn_mo
);
2295 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2297 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2298 || insn
.insn_mo
->pinfo
== INSN_MACRO
2299 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2301 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2303 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2305 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2307 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2309 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2311 /* start-sanitize-r5900 */
2312 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2314 /* end-sanitize-r5900 */
2318 assert (insn
.insn_mo
->name
);
2319 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2321 insn
.insn_opcode
= insn
.insn_mo
->match
;
2337 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2343 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2348 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2353 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2360 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2364 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2368 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2375 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2381 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2382 assert (r
== BFD_RELOC_MIPS_GPREL
2383 || r
== BFD_RELOC_MIPS_LITERAL
2384 || r
== BFD_RELOC_LO16
2385 || r
== BFD_RELOC_MIPS_GOT16
2386 || r
== BFD_RELOC_MIPS_CALL16
2387 || r
== BFD_RELOC_MIPS_GOT_LO16
2388 || r
== BFD_RELOC_MIPS_CALL_LO16
2389 || (ep
->X_op
== O_subtract
2390 && now_seg
== text_section
2391 && r
== BFD_RELOC_PCREL_LO16
));
2395 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2397 && (ep
->X_op
== O_constant
2398 || (ep
->X_op
== O_symbol
2399 && (r
== BFD_RELOC_HI16_S
2400 || r
== BFD_RELOC_HI16
2401 || r
== BFD_RELOC_MIPS_GOT_HI16
2402 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2403 || (ep
->X_op
== O_subtract
2404 && now_seg
== text_section
2405 && r
== BFD_RELOC_PCREL_HI16_S
)));
2406 if (ep
->X_op
== O_constant
)
2408 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2410 r
= BFD_RELOC_UNUSED
;
2415 assert (ep
!= NULL
);
2417 * This allows macro() to pass an immediate expression for
2418 * creating short branches without creating a symbol.
2419 * Note that the expression still might come from the assembly
2420 * input, in which case the value is not checked for range nor
2421 * is a relocation entry generated (yuck).
2423 if (ep
->X_op
== O_constant
)
2425 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2429 r
= BFD_RELOC_16_PCREL_S2
;
2433 assert (ep
!= NULL
);
2434 r
= BFD_RELOC_MIPS_JMP
;
2443 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2445 append_insn (place
, &insn
, ep
, r
, false);
2449 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2457 struct mips_cl_insn insn
;
2458 bfd_reloc_code_real_type r
;
2460 r
= BFD_RELOC_UNUSED
;
2461 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2462 assert (insn
.insn_mo
);
2463 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2465 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2466 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2469 assert (insn
.insn_mo
->name
);
2470 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2473 insn
.insn_opcode
= insn
.insn_mo
->match
;
2474 insn
.use_extend
= false;
2493 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2498 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2502 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2506 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2516 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2523 regno
= va_arg (args
, int);
2524 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2525 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2546 assert (ep
!= NULL
);
2548 if (ep
->X_op
!= O_constant
)
2549 r
= BFD_RELOC_UNUSED
+ c
;
2552 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2553 false, false, &insn
.insn_opcode
,
2554 &insn
.use_extend
, &insn
.extend
);
2556 r
= BFD_RELOC_UNUSED
;
2562 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2569 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2571 append_insn (place
, &insn
, ep
, r
, false);
2575 * Generate a "lui" instruction.
2578 macro_build_lui (place
, counter
, ep
, regnum
)
2584 expressionS high_expr
;
2585 struct mips_cl_insn insn
;
2586 bfd_reloc_code_real_type r
;
2587 CONST
char *name
= "lui";
2588 CONST
char *fmt
= "t,u";
2596 high_expr
.X_op
= O_constant
;
2597 high_expr
.X_add_number
= ep
->X_add_number
;
2600 if (high_expr
.X_op
== O_constant
)
2602 /* we can compute the instruction now without a relocation entry */
2603 if (high_expr
.X_add_number
& 0x8000)
2604 high_expr
.X_add_number
+= 0x10000;
2605 high_expr
.X_add_number
=
2606 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2607 r
= BFD_RELOC_UNUSED
;
2611 assert (ep
->X_op
== O_symbol
);
2612 /* _gp_disp is a special case, used from s_cpload. */
2613 assert (mips_pic
== NO_PIC
2614 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2615 r
= BFD_RELOC_HI16_S
;
2619 * If the macro is about to expand into a second instruction,
2620 * print a warning if needed. We need to pass ip as a parameter
2621 * to generate a better warning message here...
2623 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2624 as_warn ("Macro instruction expanded into multiple instructions");
2627 *counter
+= 1; /* bump instruction counter */
2629 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2630 assert (insn
.insn_mo
);
2631 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2632 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2634 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2635 if (r
== BFD_RELOC_UNUSED
)
2637 insn
.insn_opcode
|= high_expr
.X_add_number
;
2638 append_insn (place
, &insn
, NULL
, r
, false);
2641 append_insn (place
, &insn
, &high_expr
, r
, false);
2645 * Generates code to set the $at register to true (one)
2646 * if reg is less than the immediate expression.
2649 set_at (counter
, reg
, unsignedp
)
2654 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2655 macro_build ((char *) NULL
, counter
, &imm_expr
,
2656 unsignedp
? "sltiu" : "slti",
2657 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2660 load_register (counter
, AT
, &imm_expr
, 0);
2661 macro_build ((char *) NULL
, counter
, NULL
,
2662 unsignedp
? "sltu" : "slt",
2663 "d,v,t", AT
, reg
, AT
);
2667 /* Warn if an expression is not a constant. */
2670 check_absolute_expr (ip
, ex
)
2671 struct mips_cl_insn
*ip
;
2674 if (ex
->X_op
!= O_constant
)
2675 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2678 /* Count the leading zeroes by performing a binary chop. This is a
2679 bulky bit of source, but performance is a LOT better for the
2680 majority of values than a simple loop to count the bits:
2681 for (lcnt = 0; (lcnt < 32); lcnt++)
2682 if ((v) & (1 << (31 - lcnt)))
2684 However it is not code size friendly, and the gain will drop a bit
2685 on certain cached systems.
2687 #define COUNT_TOP_ZEROES(v) \
2688 (((v) & ~0xffff) == 0 \
2689 ? ((v) & ~0xff) == 0 \
2690 ? ((v) & ~0xf) == 0 \
2691 ? ((v) & ~0x3) == 0 \
2692 ? ((v) & ~0x1) == 0 \
2697 : ((v) & ~0x7) == 0 \
2700 : ((v) & ~0x3f) == 0 \
2701 ? ((v) & ~0x1f) == 0 \
2704 : ((v) & ~0x7f) == 0 \
2707 : ((v) & ~0xfff) == 0 \
2708 ? ((v) & ~0x3ff) == 0 \
2709 ? ((v) & ~0x1ff) == 0 \
2712 : ((v) & ~0x7ff) == 0 \
2715 : ((v) & ~0x3fff) == 0 \
2716 ? ((v) & ~0x1fff) == 0 \
2719 : ((v) & ~0x7fff) == 0 \
2722 : ((v) & ~0xffffff) == 0 \
2723 ? ((v) & ~0xfffff) == 0 \
2724 ? ((v) & ~0x3ffff) == 0 \
2725 ? ((v) & ~0x1ffff) == 0 \
2728 : ((v) & ~0x7ffff) == 0 \
2731 : ((v) & ~0x3fffff) == 0 \
2732 ? ((v) & ~0x1fffff) == 0 \
2735 : ((v) & ~0x7fffff) == 0 \
2738 : ((v) & ~0xfffffff) == 0 \
2739 ? ((v) & ~0x3ffffff) == 0 \
2740 ? ((v) & ~0x1ffffff) == 0 \
2743 : ((v) & ~0x7ffffff) == 0 \
2746 : ((v) & ~0x3fffffff) == 0 \
2747 ? ((v) & ~0x1fffffff) == 0 \
2750 : ((v) & ~0x7fffffff) == 0 \
2755 * This routine generates the least number of instructions neccessary to load
2756 * an absolute expression value into a register.
2759 load_register (counter
, reg
, ep
, dbl
)
2766 expressionS hi32
, lo32
;
2768 if (ep
->X_op
!= O_big
)
2770 assert (ep
->X_op
== O_constant
);
2771 if (ep
->X_add_number
< 0x8000
2772 && (ep
->X_add_number
>= 0
2773 || (ep
->X_add_number
>= -0x8000
2776 || sizeof (ep
->X_add_number
) > 4))))
2778 /* We can handle 16 bit signed values with an addiu to
2779 $zero. No need to ever use daddiu here, since $zero and
2780 the result are always correct in 32 bit mode. */
2781 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2782 (int) BFD_RELOC_LO16
);
2785 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2787 /* We can handle 16 bit unsigned values with an ori to
2789 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2790 (int) BFD_RELOC_LO16
);
2793 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2794 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2795 == ~ (offsetT
) 0x7fffffff))
2798 || sizeof (ep
->X_add_number
) > 4
2799 || (ep
->X_add_number
& 0x80000000) == 0))
2800 || ((mips_isa
< 3 || ! dbl
)
2801 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
2804 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
2805 == ~ (offsetT
) 0xffffffff)))
2807 /* 32 bit values require an lui. */
2808 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2809 (int) BFD_RELOC_HI16
);
2810 if ((ep
->X_add_number
& 0xffff) != 0)
2811 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2812 (int) BFD_RELOC_LO16
);
2817 /* The value is larger than 32 bits. */
2821 as_bad ("Number larger than 32 bits");
2822 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2823 (int) BFD_RELOC_LO16
);
2827 if (ep
->X_op
!= O_big
)
2830 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2831 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2832 hi32
.X_add_number
&= 0xffffffff;
2834 lo32
.X_add_number
&= 0xffffffff;
2838 assert (ep
->X_add_number
> 2);
2839 if (ep
->X_add_number
== 3)
2840 generic_bignum
[3] = 0;
2841 else if (ep
->X_add_number
> 4)
2842 as_bad ("Number larger than 64 bits");
2843 lo32
.X_op
= O_constant
;
2844 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2845 hi32
.X_op
= O_constant
;
2846 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2849 if (hi32
.X_add_number
== 0)
2854 unsigned long hi
, lo
;
2856 if (hi32
.X_add_number
== 0xffffffff)
2858 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2860 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2861 reg
, 0, (int) BFD_RELOC_LO16
);
2864 if (lo32
.X_add_number
& 0x80000000)
2866 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2867 (int) BFD_RELOC_HI16
);
2868 if (lo32
.X_add_number
& 0xffff)
2869 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2870 reg
, reg
, (int) BFD_RELOC_LO16
);
2875 /* Check for 16bit shifted constant. We know that hi32 is
2876 non-zero, so start the mask on the first bit of the hi32
2881 unsigned long himask
, lomask
;
2885 himask
= 0xffff >> (32 - shift
);
2886 lomask
= (0xffff << shift
) & 0xffffffff;
2890 himask
= 0xffff << (shift
- 32);
2893 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2894 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2898 tmp
.X_op
= O_constant
;
2900 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2901 | (lo32
.X_add_number
>> shift
));
2903 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2904 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2905 (int) BFD_RELOC_LO16
);
2906 macro_build ((char *) NULL
, counter
, NULL
,
2907 (shift
>= 32) ? "dsll32" : "dsll",
2909 (shift
>= 32) ? shift
- 32 : shift
);
2913 } while (shift
<= (64 - 16));
2915 /* Find the bit number of the lowest one bit, and store the
2916 shifted value in hi/lo. */
2917 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2918 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2922 while ((lo
& 1) == 0)
2927 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2933 while ((hi
& 1) == 0)
2942 /* Optimize if the shifted value is a (power of 2) - 1. */
2943 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2944 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2946 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2951 /* This instruction will set the register to be all
2953 tmp
.X_op
= O_constant
;
2954 tmp
.X_add_number
= (offsetT
) -1;
2955 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2956 reg
, 0, (int) BFD_RELOC_LO16
);
2960 macro_build ((char *) NULL
, counter
, NULL
,
2961 (bit
>= 32) ? "dsll32" : "dsll",
2963 (bit
>= 32) ? bit
- 32 : bit
);
2965 macro_build ((char *) NULL
, counter
, NULL
,
2966 (shift
>= 32) ? "dsrl32" : "dsrl",
2968 (shift
>= 32) ? shift
- 32 : shift
);
2973 /* Sign extend hi32 before calling load_register, because we can
2974 generally get better code when we load a sign extended value. */
2975 if ((hi32
.X_add_number
& 0x80000000) != 0)
2976 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2977 load_register (counter
, reg
, &hi32
, 0);
2980 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2984 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2993 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2995 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2996 (int) BFD_RELOC_HI16
);
2997 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3004 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3009 mid16
.X_add_number
>>= 16;
3010 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3011 freg
, (int) BFD_RELOC_LO16
);
3012 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3016 if ((lo32
.X_add_number
& 0xffff) != 0)
3017 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3018 (int) BFD_RELOC_LO16
);
3021 /* Load an address into a register. */
3024 load_address (counter
, reg
, ep
)
3031 if (ep
->X_op
!= O_constant
3032 && ep
->X_op
!= O_symbol
)
3034 as_bad ("expression too complex");
3035 ep
->X_op
= O_constant
;
3038 if (ep
->X_op
== O_constant
)
3040 load_register (counter
, reg
, ep
, 0);
3044 if (mips_pic
== NO_PIC
)
3046 /* If this is a reference to a GP relative symbol, we want
3047 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3049 lui $reg,<sym> (BFD_RELOC_HI16_S)
3050 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3051 If we have an addend, we always use the latter form. */
3052 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3053 || nopic_need_relax (ep
->X_add_symbol
))
3058 macro_build ((char *) NULL
, counter
, ep
,
3059 mips_isa
< 3 ? "addiu" : "daddiu",
3060 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3061 p
= frag_var (rs_machine_dependent
, 8, 0,
3062 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
3063 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3065 macro_build_lui (p
, counter
, ep
, reg
);
3068 macro_build (p
, counter
, ep
,
3069 mips_isa
< 3 ? "addiu" : "daddiu",
3070 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3072 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3076 /* If this is a reference to an external symbol, we want
3077 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3079 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3081 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3082 If there is a constant, it must be added in after. */
3083 ex
.X_add_number
= ep
->X_add_number
;
3084 ep
->X_add_number
= 0;
3086 macro_build ((char *) NULL
, counter
, ep
,
3087 mips_isa
< 3 ? "lw" : "ld",
3088 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3089 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3090 p
= frag_var (rs_machine_dependent
, 4, 0,
3091 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
3092 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3093 macro_build (p
, counter
, ep
,
3094 mips_isa
< 3 ? "addiu" : "daddiu",
3095 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3096 if (ex
.X_add_number
!= 0)
3098 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3099 as_bad ("PIC code offset overflow (max 16 signed bits)");
3100 ex
.X_op
= O_constant
;
3101 macro_build ((char *) NULL
, counter
, &ex
,
3102 mips_isa
< 3 ? "addiu" : "daddiu",
3103 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3106 else if (mips_pic
== SVR4_PIC
)
3111 /* This is the large GOT case. If this is a reference to an
3112 external symbol, we want
3113 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3115 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3116 Otherwise, for a reference to a local symbol, we want
3117 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3119 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3120 If there is a constant, it must be added in after. */
3121 ex
.X_add_number
= ep
->X_add_number
;
3122 ep
->X_add_number
= 0;
3123 if (reg_needs_delay (GP
))
3128 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3129 (int) BFD_RELOC_MIPS_GOT_HI16
);
3130 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3131 mips_isa
< 3 ? "addu" : "daddu",
3132 "d,v,t", reg
, reg
, GP
);
3133 macro_build ((char *) NULL
, counter
, ep
,
3134 mips_isa
< 3 ? "lw" : "ld",
3135 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3136 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3137 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3138 mips_warn_about_macros
),
3139 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3142 /* We need a nop before loading from $gp. This special
3143 check is required because the lui which starts the main
3144 instruction stream does not refer to $gp, and so will not
3145 insert the nop which may be required. */
3146 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3149 macro_build (p
, counter
, ep
,
3150 mips_isa
< 3 ? "lw" : "ld",
3151 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3153 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3155 macro_build (p
, counter
, ep
,
3156 mips_isa
< 3 ? "addiu" : "daddiu",
3157 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3158 if (ex
.X_add_number
!= 0)
3160 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3161 as_bad ("PIC code offset overflow (max 16 signed bits)");
3162 ex
.X_op
= O_constant
;
3163 macro_build ((char *) NULL
, counter
, &ex
,
3164 mips_isa
< 3 ? "addiu" : "daddiu",
3165 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3168 else if (mips_pic
== EMBEDDED_PIC
)
3171 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3173 macro_build ((char *) NULL
, counter
, ep
,
3174 mips_isa
< 3 ? "addiu" : "daddiu",
3175 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3183 * This routine implements the seemingly endless macro or synthesized
3184 * instructions and addressing modes in the mips assembly language. Many
3185 * of these macros are simple and are similar to each other. These could
3186 * probably be handled by some kind of table or grammer aproach instead of
3187 * this verbose method. Others are not simple macros but are more like
3188 * optimizing code generation.
3189 * One interesting optimization is when several store macros appear
3190 * consecutivly that would load AT with the upper half of the same address.
3191 * The ensuing load upper instructions are ommited. This implies some kind
3192 * of global optimization. We currently only optimize within a single macro.
3193 * For many of the load and store macros if the address is specified as a
3194 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3195 * first load register 'at' with zero and use it as the base register. The
3196 * mips assembler simply uses register $zero. Just one tiny optimization
3201 struct mips_cl_insn
*ip
;
3203 register int treg
, sreg
, dreg
, breg
;
3218 bfd_reloc_code_real_type r
;
3220 int hold_mips_optimize
;
3224 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3225 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3226 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3227 mask
= ip
->insn_mo
->mask
;
3229 expr1
.X_op
= O_constant
;
3230 expr1
.X_op_symbol
= NULL
;
3231 expr1
.X_add_symbol
= NULL
;
3232 expr1
.X_add_number
= 1;
3244 mips_emit_delays (true);
3246 mips_any_noreorder
= 1;
3248 expr1
.X_add_number
= 8;
3249 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3251 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3253 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3254 macro_build ((char *) NULL
, &icnt
, NULL
,
3255 dbl
? "dsub" : "sub",
3256 "d,v,t", dreg
, 0, sreg
);
3279 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3281 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3282 (int) BFD_RELOC_LO16
);
3285 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3286 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3305 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3307 if (mask
!= M_NOR_I
)
3308 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3309 sreg
, (int) BFD_RELOC_LO16
);
3312 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3313 treg
, sreg
, (int) BFD_RELOC_LO16
);
3314 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3320 load_register (&icnt
, AT
, &imm_expr
, 0);
3321 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3338 if (imm_expr
.X_add_number
== 0)
3340 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3344 load_register (&icnt
, AT
, &imm_expr
, 0);
3345 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3353 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3354 likely
? "bgezl" : "bgez",
3360 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3361 likely
? "blezl" : "blez",
3365 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3366 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3367 likely
? "beql" : "beq",
3374 /* check for > max integer */
3375 maxnum
= 0x7fffffff;
3383 if (imm_expr
.X_add_number
>= maxnum
3384 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3387 /* result is always false */
3390 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3391 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3395 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3396 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3401 imm_expr
.X_add_number
++;
3405 if (mask
== M_BGEL_I
)
3407 if (imm_expr
.X_add_number
== 0)
3409 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3410 likely
? "bgezl" : "bgez",
3414 if (imm_expr
.X_add_number
== 1)
3416 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3417 likely
? "bgtzl" : "bgtz",
3421 maxnum
= 0x7fffffff;
3429 maxnum
= - maxnum
- 1;
3430 if (imm_expr
.X_add_number
<= maxnum
3431 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3434 /* result is always true */
3435 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3436 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3439 set_at (&icnt
, sreg
, 0);
3440 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3441 likely
? "beql" : "beq",
3452 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3453 likely
? "beql" : "beq",
3457 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3459 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3460 likely
? "beql" : "beq",
3467 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3469 imm_expr
.X_add_number
++;
3473 if (mask
== M_BGEUL_I
)
3475 if (imm_expr
.X_add_number
== 0)
3477 if (imm_expr
.X_add_number
== 1)
3479 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3480 likely
? "bnel" : "bne",
3484 set_at (&icnt
, sreg
, 1);
3485 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3486 likely
? "beql" : "beq",
3495 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3496 likely
? "bgtzl" : "bgtz",
3502 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3503 likely
? "bltzl" : "bltz",
3507 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3508 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3509 likely
? "bnel" : "bne",
3518 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3519 likely
? "bnel" : "bne",
3525 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3527 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3528 likely
? "bnel" : "bne",
3537 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3538 likely
? "blezl" : "blez",
3544 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3545 likely
? "bgezl" : "bgez",
3549 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3550 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3551 likely
? "beql" : "beq",
3558 maxnum
= 0x7fffffff;
3566 if (imm_expr
.X_add_number
>= maxnum
3567 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3569 imm_expr
.X_add_number
++;
3573 if (mask
== M_BLTL_I
)
3575 if (imm_expr
.X_add_number
== 0)
3577 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3578 likely
? "bltzl" : "bltz",
3582 if (imm_expr
.X_add_number
== 1)
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3585 likely
? "blezl" : "blez",
3589 set_at (&icnt
, sreg
, 0);
3590 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3591 likely
? "bnel" : "bne",
3600 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3601 likely
? "beql" : "beq",
3607 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3609 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3610 likely
? "beql" : "beq",
3617 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3619 imm_expr
.X_add_number
++;
3623 if (mask
== M_BLTUL_I
)
3625 if (imm_expr
.X_add_number
== 0)
3627 if (imm_expr
.X_add_number
== 1)
3629 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3630 likely
? "beql" : "beq",
3634 set_at (&icnt
, sreg
, 1);
3635 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3636 likely
? "bnel" : "bne",
3645 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3646 likely
? "bltzl" : "bltz",
3652 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3653 likely
? "bgtzl" : "bgtz",
3657 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3658 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3659 likely
? "bnel" : "bne",
3670 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3671 likely
? "bnel" : "bne",
3675 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3677 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3678 likely
? "bnel" : "bne",
3694 as_warn ("Divide by zero.");
3696 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3698 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3702 mips_emit_delays (true);
3704 mips_any_noreorder
= 1;
3705 macro_build ((char *) NULL
, &icnt
, NULL
,
3706 dbl
? "ddiv" : "div",
3707 "z,s,t", sreg
, treg
);
3709 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3712 expr1
.X_add_number
= 8;
3713 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3714 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3715 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3717 expr1
.X_add_number
= -1;
3718 macro_build ((char *) NULL
, &icnt
, &expr1
,
3719 dbl
? "daddiu" : "addiu",
3720 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3721 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3722 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3725 expr1
.X_add_number
= 1;
3726 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3727 (int) BFD_RELOC_LO16
);
3728 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3733 expr1
.X_add_number
= 0x80000000;
3734 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3735 (int) BFD_RELOC_HI16
);
3738 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3741 expr1
.X_add_number
= 8;
3742 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3743 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3744 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3747 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3786 if (imm_expr
.X_add_number
== 0)
3788 as_warn ("Divide by zero.");
3790 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3792 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3795 if (imm_expr
.X_add_number
== 1)
3797 if (strcmp (s2
, "mflo") == 0)
3798 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3801 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3804 if (imm_expr
.X_add_number
== -1
3805 && s
[strlen (s
) - 1] != 'u')
3807 if (strcmp (s2
, "mflo") == 0)
3810 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3813 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3817 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3821 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3822 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3823 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3842 mips_emit_delays (true);
3844 mips_any_noreorder
= 1;
3845 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3847 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3850 expr1
.X_add_number
= 8;
3851 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3852 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3853 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3856 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3862 /* Load the address of a symbol into a register. If breg is not
3863 zero, we then add a base register to it. */
3865 /* When generating embedded PIC code, we permit expressions of
3868 where bar is an address in the .text section. These are used
3869 when getting the addresses of functions. We don't permit
3870 X_add_number to be non-zero, because if the symbol is
3871 external the relaxing code needs to know that any addend is
3872 purely the offset to X_op_symbol. */
3873 if (mips_pic
== EMBEDDED_PIC
3874 && offset_expr
.X_op
== O_subtract
3875 && now_seg
== text_section
3876 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3877 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3878 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3879 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3880 ->sy_value
.X_add_symbol
)
3883 && offset_expr
.X_add_number
== 0)
3885 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3886 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3887 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3888 mips_isa
< 3 ? "addiu" : "daddiu",
3889 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3893 if (offset_expr
.X_op
!= O_symbol
3894 && offset_expr
.X_op
!= O_constant
)
3896 as_bad ("expression too complex");
3897 offset_expr
.X_op
= O_constant
;
3911 if (offset_expr
.X_op
== O_constant
)
3912 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3913 else if (mips_pic
== NO_PIC
)
3915 /* If this is a reference to an GP relative symbol, we want
3916 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3918 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3919 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3920 If we have a constant, we need two instructions anyhow,
3921 so we may as well always use the latter form. */
3922 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3923 || nopic_need_relax (offset_expr
.X_add_symbol
))
3928 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3929 mips_isa
< 3 ? "addiu" : "daddiu",
3930 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3931 p
= frag_var (rs_machine_dependent
, 8, 0,
3932 RELAX_ENCODE (4, 8, 0, 4, 0,
3933 mips_warn_about_macros
),
3934 offset_expr
.X_add_symbol
, (offsetT
) 0,
3937 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3940 macro_build (p
, &icnt
, &offset_expr
,
3941 mips_isa
< 3 ? "addiu" : "daddiu",
3942 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3944 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3946 /* If this is a reference to an external symbol, and there
3947 is no constant, we want
3948 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3949 For a local symbol, we want
3950 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3952 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3954 If we have a small constant, and this is a reference to
3955 an external symbol, we want
3956 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3958 addiu $tempreg,$tempreg,<constant>
3959 For a local symbol, we want the same instruction
3960 sequence, but we output a BFD_RELOC_LO16 reloc on the
3963 If we have a large constant, and this is a reference to
3964 an external symbol, we want
3965 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3966 lui $at,<hiconstant>
3967 addiu $at,$at,<loconstant>
3968 addu $tempreg,$tempreg,$at
3969 For a local symbol, we want the same instruction
3970 sequence, but we output a BFD_RELOC_LO16 reloc on the
3971 addiu instruction. */
3972 expr1
.X_add_number
= offset_expr
.X_add_number
;
3973 offset_expr
.X_add_number
= 0;
3975 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3977 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3978 if (expr1
.X_add_number
== 0)
3986 /* We're going to put in an addu instruction using
3987 tempreg, so we may as well insert the nop right
3989 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3993 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3994 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3996 ? mips_warn_about_macros
3998 offset_expr
.X_add_symbol
, (offsetT
) 0,
4002 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4005 macro_build (p
, &icnt
, &expr1
,
4006 mips_isa
< 3 ? "addiu" : "daddiu",
4007 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4008 /* FIXME: If breg == 0, and the next instruction uses
4009 $tempreg, then if this variant case is used an extra
4010 nop will be generated. */
4012 else if (expr1
.X_add_number
>= -0x8000
4013 && expr1
.X_add_number
< 0x8000)
4015 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4017 macro_build ((char *) NULL
, &icnt
, &expr1
,
4018 mips_isa
< 3 ? "addiu" : "daddiu",
4019 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4020 (void) frag_var (rs_machine_dependent
, 0, 0,
4021 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4022 offset_expr
.X_add_symbol
, (offsetT
) 0,
4029 /* If we are going to add in a base register, and the
4030 target register and the base register are the same,
4031 then we are using AT as a temporary register. Since
4032 we want to load the constant into AT, we add our
4033 current AT (from the global offset table) and the
4034 register into the register now, and pretend we were
4035 not using a base register. */
4040 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4042 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4043 mips_isa
< 3 ? "addu" : "daddu",
4044 "d,v,t", treg
, AT
, breg
);
4050 /* Set mips_optimize around the lui instruction to avoid
4051 inserting an unnecessary nop after the lw. */
4052 hold_mips_optimize
= mips_optimize
;
4054 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4055 mips_optimize
= hold_mips_optimize
;
4057 macro_build ((char *) NULL
, &icnt
, &expr1
,
4058 mips_isa
< 3 ? "addiu" : "daddiu",
4059 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4060 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4061 mips_isa
< 3 ? "addu" : "daddu",
4062 "d,v,t", tempreg
, tempreg
, AT
);
4063 (void) frag_var (rs_machine_dependent
, 0, 0,
4064 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4065 offset_expr
.X_add_symbol
, (offsetT
) 0,
4070 else if (mips_pic
== SVR4_PIC
)
4074 /* This is the large GOT case. If this is a reference to an
4075 external symbol, and there is no constant, we want
4076 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4077 addu $tempreg,$tempreg,$gp
4078 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4079 For a local symbol, we want
4080 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4082 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4084 If we have a small constant, and this is a reference to
4085 an external symbol, we want
4086 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4087 addu $tempreg,$tempreg,$gp
4088 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4090 addiu $tempreg,$tempreg,<constant>
4091 For a local symbol, we want
4092 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4094 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4096 If we have a large constant, and this is a reference to
4097 an external symbol, we want
4098 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4099 addu $tempreg,$tempreg,$gp
4100 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4101 lui $at,<hiconstant>
4102 addiu $at,$at,<loconstant>
4103 addu $tempreg,$tempreg,$at
4104 For a local symbol, we want
4105 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4106 lui $at,<hiconstant>
4107 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4108 addu $tempreg,$tempreg,$at
4110 expr1
.X_add_number
= offset_expr
.X_add_number
;
4111 offset_expr
.X_add_number
= 0;
4113 if (reg_needs_delay (GP
))
4117 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4118 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4119 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4120 mips_isa
< 3 ? "addu" : "daddu",
4121 "d,v,t", tempreg
, tempreg
, GP
);
4122 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4124 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4126 if (expr1
.X_add_number
== 0)
4134 /* We're going to put in an addu instruction using
4135 tempreg, so we may as well insert the nop right
4137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4142 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4143 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4146 ? mips_warn_about_macros
4148 offset_expr
.X_add_symbol
, (offsetT
) 0,
4151 else if (expr1
.X_add_number
>= -0x8000
4152 && expr1
.X_add_number
< 0x8000)
4154 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4156 macro_build ((char *) NULL
, &icnt
, &expr1
,
4157 mips_isa
< 3 ? "addiu" : "daddiu",
4158 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4160 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4161 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4163 ? mips_warn_about_macros
4165 offset_expr
.X_add_symbol
, (offsetT
) 0,
4172 /* If we are going to add in a base register, and the
4173 target register and the base register are the same,
4174 then we are using AT as a temporary register. Since
4175 we want to load the constant into AT, we add our
4176 current AT (from the global offset table) and the
4177 register into the register now, and pretend we were
4178 not using a base register. */
4186 assert (tempreg
== AT
);
4187 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4189 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4190 mips_isa
< 3 ? "addu" : "daddu",
4191 "d,v,t", treg
, AT
, breg
);
4196 /* Set mips_optimize around the lui instruction to avoid
4197 inserting an unnecessary nop after the lw. */
4198 hold_mips_optimize
= mips_optimize
;
4200 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4201 mips_optimize
= hold_mips_optimize
;
4203 macro_build ((char *) NULL
, &icnt
, &expr1
,
4204 mips_isa
< 3 ? "addiu" : "daddiu",
4205 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4206 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4207 mips_isa
< 3 ? "addu" : "daddu",
4208 "d,v,t", dreg
, dreg
, AT
);
4210 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4211 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4214 ? mips_warn_about_macros
4216 offset_expr
.X_add_symbol
, (offsetT
) 0,
4224 /* This is needed because this instruction uses $gp, but
4225 the first instruction on the main stream does not. */
4226 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4229 macro_build (p
, &icnt
, &offset_expr
,
4231 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4233 if (expr1
.X_add_number
>= -0x8000
4234 && expr1
.X_add_number
< 0x8000)
4236 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4238 macro_build (p
, &icnt
, &expr1
,
4239 mips_isa
< 3 ? "addiu" : "daddiu",
4240 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4241 /* FIXME: If add_number is 0, and there was no base
4242 register, the external symbol case ended with a load,
4243 so if the symbol turns out to not be external, and
4244 the next instruction uses tempreg, an unnecessary nop
4245 will be inserted. */
4251 /* We must add in the base register now, as in the
4252 external symbol case. */
4253 assert (tempreg
== AT
);
4254 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4256 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4257 mips_isa
< 3 ? "addu" : "daddu",
4258 "d,v,t", treg
, AT
, breg
);
4261 /* We set breg to 0 because we have arranged to add
4262 it in in both cases. */
4266 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4268 macro_build (p
, &icnt
, &expr1
,
4269 mips_isa
< 3 ? "addiu" : "daddiu",
4270 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4272 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4273 mips_isa
< 3 ? "addu" : "daddu",
4274 "d,v,t", tempreg
, tempreg
, AT
);
4278 else if (mips_pic
== EMBEDDED_PIC
)
4281 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4283 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4284 mips_isa
< 3 ? "addiu" : "daddiu",
4285 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4291 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4292 mips_isa
< 3 ? "addu" : "daddu",
4293 "d,v,t", treg
, tempreg
, breg
);
4301 /* The j instruction may not be used in PIC code, since it
4302 requires an absolute address. We convert it to a b
4304 if (mips_pic
== NO_PIC
)
4305 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4307 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4310 /* The jal instructions must be handled as macros because when
4311 generating PIC code they expand to multi-instruction
4312 sequences. Normally they are simple instructions. */
4317 if (mips_pic
== NO_PIC
4318 || mips_pic
== EMBEDDED_PIC
)
4319 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4321 else if (mips_pic
== SVR4_PIC
)
4323 if (sreg
!= PIC_CALL_REG
)
4324 as_warn ("MIPS PIC call to register other than $25");
4326 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4328 if (mips_cprestore_offset
< 0)
4329 as_warn ("No .cprestore pseudo-op used in PIC code");
4332 expr1
.X_add_number
= mips_cprestore_offset
;
4333 macro_build ((char *) NULL
, &icnt
, &expr1
,
4334 mips_isa
< 3 ? "lw" : "ld",
4335 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4344 if (mips_pic
== NO_PIC
)
4345 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4346 else if (mips_pic
== SVR4_PIC
)
4348 /* If this is a reference to an external symbol, and we are
4349 using a small GOT, we want
4350 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4354 lw $gp,cprestore($sp)
4355 The cprestore value is set using the .cprestore
4356 pseudo-op. If we are using a big GOT, we want
4357 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4359 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4363 lw $gp,cprestore($sp)
4364 If the symbol is not external, we want
4365 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4367 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4370 lw $gp,cprestore($sp) */
4374 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4375 mips_isa
< 3 ? "lw" : "ld",
4376 "t,o(b)", PIC_CALL_REG
,
4377 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4378 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4380 p
= frag_var (rs_machine_dependent
, 4, 0,
4381 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4382 offset_expr
.X_add_symbol
, (offsetT
) 0,
4389 if (reg_needs_delay (GP
))
4393 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4394 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4395 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4396 mips_isa
< 3 ? "addu" : "daddu",
4397 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4398 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4399 mips_isa
< 3 ? "lw" : "ld",
4400 "t,o(b)", PIC_CALL_REG
,
4401 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4404 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4405 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4407 offset_expr
.X_add_symbol
, (offsetT
) 0,
4411 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4414 macro_build (p
, &icnt
, &offset_expr
,
4415 mips_isa
< 3 ? "lw" : "ld",
4416 "t,o(b)", PIC_CALL_REG
,
4417 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4419 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4422 macro_build (p
, &icnt
, &offset_expr
,
4423 mips_isa
< 3 ? "addiu" : "daddiu",
4424 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4425 (int) BFD_RELOC_LO16
);
4426 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4427 "jalr", "s", PIC_CALL_REG
);
4428 if (mips_cprestore_offset
< 0)
4429 as_warn ("No .cprestore pseudo-op used in PIC code");
4433 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4435 expr1
.X_add_number
= mips_cprestore_offset
;
4436 macro_build ((char *) NULL
, &icnt
, &expr1
,
4437 mips_isa
< 3 ? "lw" : "ld",
4438 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4442 else if (mips_pic
== EMBEDDED_PIC
)
4444 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4445 /* The linker may expand the call to a longer sequence which
4446 uses $at, so we must break rather than return. */
4471 /* Itbl support may require additional care here. */
4476 /* Itbl support may require additional care here. */
4481 /* Itbl support may require additional care here. */
4486 /* Itbl support may require additional care here. */
4499 /* Itbl support may require additional care here. */
4504 /* Itbl support may require additional care here. */
4509 /* Itbl support may require additional care here. */
4529 if (breg
== treg
|| coproc
|| lr
)
4551 /* Itbl support may require additional care here. */
4556 /* Itbl support may require additional care here. */
4561 /* Itbl support may require additional care here. */
4566 /* Itbl support may require additional care here. */
4584 /* Itbl support may require additional care here. */
4588 /* Itbl support may require additional care here. */
4593 /* Itbl support may require additional care here. */
4605 /* Itbl support may require additional care here. */
4606 if (mask
== M_LWC1_AB
4607 || mask
== M_SWC1_AB
4608 || mask
== M_LDC1_AB
4609 || mask
== M_SDC1_AB
4618 if (offset_expr
.X_op
!= O_constant
4619 && offset_expr
.X_op
!= O_symbol
)
4621 as_bad ("expression too complex");
4622 offset_expr
.X_op
= O_constant
;
4625 /* A constant expression in PIC code can be handled just as it
4626 is in non PIC code. */
4627 if (mips_pic
== NO_PIC
4628 || offset_expr
.X_op
== O_constant
)
4630 /* If this is a reference to a GP relative symbol, and there
4631 is no base register, we want
4632 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4633 Otherwise, if there is no base register, we want
4634 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4635 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4636 If we have a constant, we need two instructions anyhow,
4637 so we always use the latter form.
4639 If we have a base register, and this is a reference to a
4640 GP relative symbol, we want
4641 addu $tempreg,$breg,$gp
4642 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4644 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4645 addu $tempreg,$tempreg,$breg
4646 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4647 With a constant we always use the latter case. */
4650 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4651 || nopic_need_relax (offset_expr
.X_add_symbol
))
4656 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4657 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4658 p
= frag_var (rs_machine_dependent
, 8, 0,
4659 RELAX_ENCODE (4, 8, 0, 4, 0,
4660 (mips_warn_about_macros
4661 || (used_at
&& mips_noat
))),
4662 offset_expr
.X_add_symbol
, (offsetT
) 0,
4666 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4669 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4670 (int) BFD_RELOC_LO16
, tempreg
);
4674 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4675 || nopic_need_relax (offset_expr
.X_add_symbol
))
4680 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4681 mips_isa
< 3 ? "addu" : "daddu",
4682 "d,v,t", tempreg
, breg
, GP
);
4683 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4684 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4685 p
= frag_var (rs_machine_dependent
, 12, 0,
4686 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4687 offset_expr
.X_add_symbol
, (offsetT
) 0,
4690 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4693 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4694 mips_isa
< 3 ? "addu" : "daddu",
4695 "d,v,t", tempreg
, tempreg
, breg
);
4698 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4699 (int) BFD_RELOC_LO16
, tempreg
);
4702 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4704 /* If this is a reference to an external symbol, we want
4705 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4707 <op> $treg,0($tempreg)
4709 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4711 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4712 <op> $treg,0($tempreg)
4713 If there is a base register, we add it to $tempreg before
4714 the <op>. If there is a constant, we stick it in the
4715 <op> instruction. We don't handle constants larger than
4716 16 bits, because we have no way to load the upper 16 bits
4717 (actually, we could handle them for the subset of cases
4718 in which we are not using $at). */
4719 assert (offset_expr
.X_op
== O_symbol
);
4720 expr1
.X_add_number
= offset_expr
.X_add_number
;
4721 offset_expr
.X_add_number
= 0;
4722 if (expr1
.X_add_number
< -0x8000
4723 || expr1
.X_add_number
>= 0x8000)
4724 as_bad ("PIC code offset overflow (max 16 signed bits)");
4726 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4727 mips_isa
< 3 ? "lw" : "ld",
4728 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4729 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4730 p
= frag_var (rs_machine_dependent
, 4, 0,
4731 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4732 offset_expr
.X_add_symbol
, (offsetT
) 0,
4734 macro_build (p
, &icnt
, &offset_expr
,
4735 mips_isa
< 3 ? "addiu" : "daddiu",
4736 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4738 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4739 mips_isa
< 3 ? "addu" : "daddu",
4740 "d,v,t", tempreg
, tempreg
, breg
);
4741 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4742 (int) BFD_RELOC_LO16
, tempreg
);
4744 else if (mips_pic
== SVR4_PIC
)
4748 /* If this is a reference to an external symbol, we want
4749 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4750 addu $tempreg,$tempreg,$gp
4751 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4752 <op> $treg,0($tempreg)
4754 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4756 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4757 <op> $treg,0($tempreg)
4758 If there is a base register, we add it to $tempreg before
4759 the <op>. If there is a constant, we stick it in the
4760 <op> instruction. We don't handle constants larger than
4761 16 bits, because we have no way to load the upper 16 bits
4762 (actually, we could handle them for the subset of cases
4763 in which we are not using $at). */
4764 assert (offset_expr
.X_op
== O_symbol
);
4765 expr1
.X_add_number
= offset_expr
.X_add_number
;
4766 offset_expr
.X_add_number
= 0;
4767 if (expr1
.X_add_number
< -0x8000
4768 || expr1
.X_add_number
>= 0x8000)
4769 as_bad ("PIC code offset overflow (max 16 signed bits)");
4770 if (reg_needs_delay (GP
))
4775 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4776 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4777 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4778 mips_isa
< 3 ? "addu" : "daddu",
4779 "d,v,t", tempreg
, tempreg
, GP
);
4780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4781 mips_isa
< 3 ? "lw" : "ld",
4782 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4784 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4785 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4786 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
4789 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4792 macro_build (p
, &icnt
, &offset_expr
,
4793 mips_isa
< 3 ? "lw" : "ld",
4794 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4796 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4798 macro_build (p
, &icnt
, &offset_expr
,
4799 mips_isa
< 3 ? "addiu" : "daddiu",
4800 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4802 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4803 mips_isa
< 3 ? "addu" : "daddu",
4804 "d,v,t", tempreg
, tempreg
, breg
);
4805 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4806 (int) BFD_RELOC_LO16
, tempreg
);
4808 else if (mips_pic
== EMBEDDED_PIC
)
4810 /* If there is no base register, we want
4811 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4812 If there is a base register, we want
4813 addu $tempreg,$breg,$gp
4814 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4816 assert (offset_expr
.X_op
== O_symbol
);
4819 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4820 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4825 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4826 mips_isa
< 3 ? "addu" : "daddu",
4827 "d,v,t", tempreg
, breg
, GP
);
4828 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4829 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4842 load_register (&icnt
, treg
, &imm_expr
, 0);
4846 load_register (&icnt
, treg
, &imm_expr
, 1);
4850 if (imm_expr
.X_op
== O_constant
)
4852 load_register (&icnt
, AT
, &imm_expr
, 0);
4853 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4854 "mtc1", "t,G", AT
, treg
);
4859 assert (offset_expr
.X_op
== O_symbol
4860 && strcmp (segment_name (S_GET_SEGMENT
4861 (offset_expr
.X_add_symbol
)),
4863 && offset_expr
.X_add_number
== 0);
4864 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4865 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4870 /* We know that sym is in the .rdata section. First we get the
4871 upper 16 bits of the address. */
4872 if (mips_pic
== NO_PIC
)
4874 /* FIXME: This won't work for a 64 bit address. */
4875 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4877 else if (mips_pic
== SVR4_PIC
)
4879 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4880 mips_isa
< 3 ? "lw" : "ld",
4881 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4883 else if (mips_pic
== EMBEDDED_PIC
)
4885 /* For embedded PIC we pick up the entire address off $gp in
4886 a single instruction. */
4887 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4888 mips_isa
< 3 ? "addiu" : "daddiu",
4889 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4890 offset_expr
.X_op
= O_constant
;
4891 offset_expr
.X_add_number
= 0;
4896 /* Now we load the register(s). */
4898 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4899 treg
, (int) BFD_RELOC_LO16
, AT
);
4902 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4903 treg
, (int) BFD_RELOC_LO16
, AT
);
4906 /* FIXME: How in the world do we deal with the possible
4908 offset_expr
.X_add_number
+= 4;
4909 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4910 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4914 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4915 does not become a variant frag. */
4916 frag_wane (frag_now
);
4922 assert (offset_expr
.X_op
== O_symbol
4923 && offset_expr
.X_add_number
== 0);
4924 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4925 if (strcmp (s
, ".lit8") == 0)
4929 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4930 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4934 r
= BFD_RELOC_MIPS_LITERAL
;
4939 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4940 if (mips_pic
== SVR4_PIC
)
4941 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4942 mips_isa
< 3 ? "lw" : "ld",
4943 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4946 /* FIXME: This won't work for a 64 bit address. */
4947 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4952 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4953 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4955 /* To avoid confusion in tc_gen_reloc, we must ensure
4956 that this does not become a variant frag. */
4957 frag_wane (frag_now
);
4968 /* Even on a big endian machine $fn comes before $fn+1. We have
4969 to adjust when loading from memory. */
4972 assert (mips_isa
< 2);
4973 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4974 target_big_endian
? treg
+ 1 : treg
,
4976 /* FIXME: A possible overflow which I don't know how to deal
4978 offset_expr
.X_add_number
+= 4;
4979 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4980 target_big_endian
? treg
: treg
+ 1,
4983 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4984 does not become a variant frag. */
4985 frag_wane (frag_now
);
4994 * The MIPS assembler seems to check for X_add_number not
4995 * being double aligned and generating:
4998 * addiu at,at,%lo(foo+1)
5001 * But, the resulting address is the same after relocation so why
5002 * generate the extra instruction?
5004 /* Itbl support may require additional care here. */
5025 /* Itbl support may require additional care here. */
5051 if (offset_expr
.X_op
!= O_symbol
5052 && offset_expr
.X_op
!= O_constant
)
5054 as_bad ("expression too complex");
5055 offset_expr
.X_op
= O_constant
;
5058 /* Even on a big endian machine $fn comes before $fn+1. We have
5059 to adjust when loading from memory. We set coproc if we must
5060 load $fn+1 first. */
5061 /* Itbl support may require additional care here. */
5062 if (! target_big_endian
)
5065 if (mips_pic
== NO_PIC
5066 || offset_expr
.X_op
== O_constant
)
5068 /* If this is a reference to a GP relative symbol, we want
5069 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5070 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5071 If we have a base register, we use this
5073 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5074 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5075 If this is not a GP relative symbol, we want
5076 lui $at,<sym> (BFD_RELOC_HI16_S)
5077 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5078 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5079 If there is a base register, we add it to $at after the
5080 lui instruction. If there is a constant, we always use
5082 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5083 || nopic_need_relax (offset_expr
.X_add_symbol
))
5102 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5103 mips_isa
< 3 ? "addu" : "daddu",
5104 "d,v,t", AT
, breg
, GP
);
5110 /* Itbl support may require additional care here. */
5111 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5112 coproc
? treg
+ 1 : treg
,
5113 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5114 offset_expr
.X_add_number
+= 4;
5116 /* Set mips_optimize to 2 to avoid inserting an
5118 hold_mips_optimize
= mips_optimize
;
5120 /* Itbl support may require additional care here. */
5121 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5122 coproc
? treg
: treg
+ 1,
5123 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5124 mips_optimize
= hold_mips_optimize
;
5126 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5127 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5128 used_at
&& mips_noat
),
5129 offset_expr
.X_add_symbol
, (offsetT
) 0,
5132 /* We just generated two relocs. When tc_gen_reloc
5133 handles this case, it will skip the first reloc and
5134 handle the second. The second reloc already has an
5135 extra addend of 4, which we added above. We must
5136 subtract it out, and then subtract another 4 to make
5137 the first reloc come out right. The second reloc
5138 will come out right because we are going to add 4 to
5139 offset_expr when we build its instruction below. */
5140 offset_expr
.X_add_number
-= 8;
5141 offset_expr
.X_op
= O_constant
;
5143 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5148 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5149 mips_isa
< 3 ? "addu" : "daddu",
5150 "d,v,t", AT
, breg
, AT
);
5154 /* Itbl support may require additional care here. */
5155 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5156 coproc
? treg
+ 1 : treg
,
5157 (int) BFD_RELOC_LO16
, AT
);
5160 /* FIXME: How do we handle overflow here? */
5161 offset_expr
.X_add_number
+= 4;
5162 /* Itbl support may require additional care here. */
5163 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5164 coproc
? treg
: treg
+ 1,
5165 (int) BFD_RELOC_LO16
, AT
);
5167 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5171 /* If this is a reference to an external symbol, we want
5172 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5177 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5179 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5180 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5181 If there is a base register we add it to $at before the
5182 lwc1 instructions. If there is a constant we include it
5183 in the lwc1 instructions. */
5185 expr1
.X_add_number
= offset_expr
.X_add_number
;
5186 offset_expr
.X_add_number
= 0;
5187 if (expr1
.X_add_number
< -0x8000
5188 || expr1
.X_add_number
>= 0x8000 - 4)
5189 as_bad ("PIC code offset overflow (max 16 signed bits)");
5194 frag_grow (24 + off
);
5195 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5196 mips_isa
< 3 ? "lw" : "ld",
5197 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5198 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5201 mips_isa
< 3 ? "addu" : "daddu",
5202 "d,v,t", AT
, breg
, AT
);
5203 /* Itbl support may require additional care here. */
5204 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5205 coproc
? treg
+ 1 : treg
,
5206 (int) BFD_RELOC_LO16
, AT
);
5207 expr1
.X_add_number
+= 4;
5209 /* Set mips_optimize to 2 to avoid inserting an undesired
5211 hold_mips_optimize
= mips_optimize
;
5213 /* Itbl support may require additional care here. */
5214 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5215 coproc
? treg
: treg
+ 1,
5216 (int) BFD_RELOC_LO16
, AT
);
5217 mips_optimize
= hold_mips_optimize
;
5219 (void) frag_var (rs_machine_dependent
, 0, 0,
5220 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5221 offset_expr
.X_add_symbol
, (offsetT
) 0,
5224 else if (mips_pic
== SVR4_PIC
)
5228 /* If this is a reference to an external symbol, we want
5229 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5231 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5236 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5238 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5239 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5240 If there is a base register we add it to $at before the
5241 lwc1 instructions. If there is a constant we include it
5242 in the lwc1 instructions. */
5244 expr1
.X_add_number
= offset_expr
.X_add_number
;
5245 offset_expr
.X_add_number
= 0;
5246 if (expr1
.X_add_number
< -0x8000
5247 || expr1
.X_add_number
>= 0x8000 - 4)
5248 as_bad ("PIC code offset overflow (max 16 signed bits)");
5249 if (reg_needs_delay (GP
))
5258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5259 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5260 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5261 mips_isa
< 3 ? "addu" : "daddu",
5262 "d,v,t", AT
, AT
, GP
);
5263 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5264 mips_isa
< 3 ? "lw" : "ld",
5265 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5266 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5268 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5269 mips_isa
< 3 ? "addu" : "daddu",
5270 "d,v,t", AT
, breg
, AT
);
5271 /* Itbl support may require additional care here. */
5272 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5273 coproc
? treg
+ 1 : treg
,
5274 (int) BFD_RELOC_LO16
, AT
);
5275 expr1
.X_add_number
+= 4;
5277 /* Set mips_optimize to 2 to avoid inserting an undesired
5279 hold_mips_optimize
= mips_optimize
;
5281 /* Itbl support may require additional care here. */
5282 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5283 coproc
? treg
: treg
+ 1,
5284 (int) BFD_RELOC_LO16
, AT
);
5285 mips_optimize
= hold_mips_optimize
;
5286 expr1
.X_add_number
-= 4;
5288 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5289 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5290 8 + gpdel
+ off
, 1, 0),
5291 offset_expr
.X_add_symbol
, (offsetT
) 0,
5295 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5298 macro_build (p
, &icnt
, &offset_expr
,
5299 mips_isa
< 3 ? "lw" : "ld",
5300 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5302 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5306 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5307 mips_isa
< 3 ? "addu" : "daddu",
5308 "d,v,t", AT
, breg
, AT
);
5311 /* Itbl support may require additional care here. */
5312 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5313 coproc
? treg
+ 1 : treg
,
5314 (int) BFD_RELOC_LO16
, AT
);
5316 expr1
.X_add_number
+= 4;
5318 /* Set mips_optimize to 2 to avoid inserting an undesired
5320 hold_mips_optimize
= mips_optimize
;
5322 /* Itbl support may require additional care here. */
5323 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5324 coproc
? treg
: treg
+ 1,
5325 (int) BFD_RELOC_LO16
, AT
);
5326 mips_optimize
= hold_mips_optimize
;
5328 else if (mips_pic
== EMBEDDED_PIC
)
5330 /* If there is no base register, we use
5331 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5332 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5333 If we have a base register, we use
5335 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5336 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5345 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5346 mips_isa
< 3 ? "addu" : "daddu",
5347 "d,v,t", AT
, breg
, GP
);
5352 /* Itbl support may require additional care here. */
5353 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5354 coproc
? treg
+ 1 : treg
,
5355 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5356 offset_expr
.X_add_number
+= 4;
5357 /* Itbl support may require additional care here. */
5358 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5359 coproc
? treg
: treg
+ 1,
5360 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5376 assert (mips_isa
< 3);
5377 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5378 (int) BFD_RELOC_LO16
, breg
);
5379 offset_expr
.X_add_number
+= 4;
5380 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5381 (int) BFD_RELOC_LO16
, breg
);
5384 /* New code added to support COPZ instructions.
5385 This code builds table entries out of the macros in mip_opcodes.
5386 R4000 uses interlocks to handle coproc delays.
5387 Other chips (like the R3000) require nops to be inserted for delays.
5389 FIXME: Currently, we require that the user handle delays.
5390 In order to fill delay slots for non-interlocked chips,
5391 we must have a way to specify delays based on the coprocessor.
5392 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5393 What are the side-effects of the cop instruction?
5394 What cache support might we have and what are its effects?
5395 Both coprocessor & memory require delays. how long???
5396 What registers are read/set/modified?
5398 If an itbl is provided to interpret cop instructions,
5399 this knowledge can be encoded in the itbl spec. */
5413 /* For now we just do C (same as Cz). */
5414 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "C");
5417 #ifdef LOSING_COMPILER
5419 /* Try and see if this is a new itbl instruction.
5420 This code builds table entries out of the macros in mip_opcodes.
5421 FIXME: For now we just assemble the expression and pass it's
5422 value along as a 32-bit immediate.
5423 We may want to have the assembler assemble this value,
5424 so that we gain the assembler's knowledge of delay slots,
5426 Would it be more efficient to use mask (id) here? */
5427 if (itbl_have_entries
5428 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5430 s
= ip
->insn_mo
->name
;
5432 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5433 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5440 as_warn ("Macro used $at after \".set noat\"");
5445 struct mips_cl_insn
*ip
;
5447 register int treg
, sreg
, dreg
, breg
;
5462 bfd_reloc_code_real_type r
;
5465 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5466 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5467 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5468 mask
= ip
->insn_mo
->mask
;
5470 expr1
.X_op
= O_constant
;
5471 expr1
.X_op_symbol
= NULL
;
5472 expr1
.X_add_symbol
= NULL
;
5473 expr1
.X_add_number
= 1;
5477 #endif /* LOSING_COMPILER */
5482 macro_build ((char *) NULL
, &icnt
, NULL
,
5483 dbl
? "dmultu" : "multu",
5485 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5491 /* The MIPS assembler some times generates shifts and adds. I'm
5492 not trying to be that fancy. GCC should do this for us
5494 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5495 macro_build ((char *) NULL
, &icnt
, NULL
,
5496 dbl
? "dmult" : "mult",
5498 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5504 mips_emit_delays (true);
5506 mips_any_noreorder
= 1;
5507 macro_build ((char *) NULL
, &icnt
, NULL
,
5508 dbl
? "dmult" : "mult",
5510 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5511 macro_build ((char *) NULL
, &icnt
, NULL
,
5512 dbl
? "dsra32" : "sra",
5513 "d,w,<", dreg
, dreg
, 31);
5514 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5516 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5519 expr1
.X_add_number
= 8;
5520 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5521 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5522 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5525 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5531 mips_emit_delays (true);
5533 mips_any_noreorder
= 1;
5534 macro_build ((char *) NULL
, &icnt
, NULL
,
5535 dbl
? "dmultu" : "multu",
5537 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5538 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5540 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5543 expr1
.X_add_number
= 8;
5544 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5545 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5546 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5552 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5553 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5554 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5556 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5560 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5561 (int) (imm_expr
.X_add_number
& 0x1f));
5562 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5563 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5564 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5568 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5569 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5570 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5572 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5576 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5577 (int) (imm_expr
.X_add_number
& 0x1f));
5578 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5579 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5580 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5584 assert (mips_isa
< 2);
5585 /* Even on a big endian machine $fn comes before $fn+1. We have
5586 to adjust when storing to memory. */
5587 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5588 target_big_endian
? treg
+ 1 : treg
,
5589 (int) BFD_RELOC_LO16
, breg
);
5590 offset_expr
.X_add_number
+= 4;
5591 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5592 target_big_endian
? treg
: treg
+ 1,
5593 (int) BFD_RELOC_LO16
, breg
);
5598 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5599 treg
, (int) BFD_RELOC_LO16
);
5601 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5602 sreg
, (int) BFD_RELOC_LO16
);
5605 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5607 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5608 dreg
, (int) BFD_RELOC_LO16
);
5613 if (imm_expr
.X_add_number
== 0)
5615 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5616 sreg
, (int) BFD_RELOC_LO16
);
5621 as_warn ("Instruction %s: result is always false",
5623 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5626 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5628 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5629 sreg
, (int) BFD_RELOC_LO16
);
5632 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5634 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5635 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5636 mips_isa
< 3 ? "addiu" : "daddiu",
5637 "t,r,j", dreg
, sreg
,
5638 (int) BFD_RELOC_LO16
);
5643 load_register (&icnt
, AT
, &imm_expr
, 0);
5644 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5648 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5649 (int) BFD_RELOC_LO16
);
5654 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5660 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5661 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5662 (int) BFD_RELOC_LO16
);
5665 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5667 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5669 macro_build ((char *) NULL
, &icnt
, &expr1
,
5670 mask
== M_SGE_I
? "slti" : "sltiu",
5671 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5676 load_register (&icnt
, AT
, &imm_expr
, 0);
5677 macro_build ((char *) NULL
, &icnt
, NULL
,
5678 mask
== M_SGE_I
? "slt" : "sltu",
5679 "d,v,t", dreg
, sreg
, AT
);
5682 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5683 (int) BFD_RELOC_LO16
);
5688 case M_SGT
: /* sreg > treg <==> treg < sreg */
5694 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5697 case M_SGT_I
: /* sreg > I <==> I < sreg */
5703 load_register (&icnt
, AT
, &imm_expr
, 0);
5704 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5707 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5713 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5714 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5715 (int) BFD_RELOC_LO16
);
5718 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5724 load_register (&icnt
, AT
, &imm_expr
, 0);
5725 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5726 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5727 (int) BFD_RELOC_LO16
);
5731 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5733 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5734 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5737 load_register (&icnt
, AT
, &imm_expr
, 0);
5738 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5742 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5744 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5745 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5748 load_register (&icnt
, AT
, &imm_expr
, 0);
5749 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5755 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5758 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5762 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5764 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5770 if (imm_expr
.X_add_number
== 0)
5772 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5778 as_warn ("Instruction %s: result is always true",
5780 macro_build ((char *) NULL
, &icnt
, &expr1
,
5781 mips_isa
< 3 ? "addiu" : "daddiu",
5782 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5785 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5787 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5788 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5791 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5793 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5794 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5795 mips_isa
< 3 ? "addiu" : "daddiu",
5796 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5801 load_register (&icnt
, AT
, &imm_expr
, 0);
5802 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5806 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5814 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5816 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5817 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5818 dbl
? "daddi" : "addi",
5819 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5822 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5823 macro_build ((char *) NULL
, &icnt
, NULL
,
5824 dbl
? "dsub" : "sub",
5825 "d,v,t", dreg
, sreg
, AT
);
5831 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5833 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5834 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5835 dbl
? "daddiu" : "addiu",
5836 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5839 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5840 macro_build ((char *) NULL
, &icnt
, NULL
,
5841 dbl
? "dsubu" : "subu",
5842 "d,v,t", dreg
, sreg
, AT
);
5863 load_register (&icnt
, AT
, &imm_expr
, 0);
5864 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5869 assert (mips_isa
< 2);
5870 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5871 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5874 * Is the double cfc1 instruction a bug in the mips assembler;
5875 * or is there a reason for it?
5877 mips_emit_delays (true);
5879 mips_any_noreorder
= 1;
5880 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5881 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5882 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5883 expr1
.X_add_number
= 3;
5884 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5885 (int) BFD_RELOC_LO16
);
5886 expr1
.X_add_number
= 2;
5887 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5888 (int) BFD_RELOC_LO16
);
5889 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5890 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5891 macro_build ((char *) NULL
, &icnt
, NULL
,
5892 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5893 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5894 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5904 if (offset_expr
.X_add_number
>= 0x7fff)
5905 as_bad ("operand overflow");
5906 /* avoid load delay */
5907 if (! target_big_endian
)
5908 offset_expr
.X_add_number
+= 1;
5909 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5910 (int) BFD_RELOC_LO16
, breg
);
5911 if (! target_big_endian
)
5912 offset_expr
.X_add_number
-= 1;
5914 offset_expr
.X_add_number
+= 1;
5915 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5916 (int) BFD_RELOC_LO16
, breg
);
5917 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5918 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5931 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5932 as_bad ("operand overflow");
5933 if (! target_big_endian
)
5934 offset_expr
.X_add_number
+= off
;
5935 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5936 (int) BFD_RELOC_LO16
, breg
);
5937 if (! target_big_endian
)
5938 offset_expr
.X_add_number
-= off
;
5940 offset_expr
.X_add_number
+= off
;
5941 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5942 (int) BFD_RELOC_LO16
, breg
);
5955 load_address (&icnt
, AT
, &offset_expr
);
5957 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5958 mips_isa
< 3 ? "addu" : "daddu",
5959 "d,v,t", AT
, AT
, breg
);
5960 if (! target_big_endian
)
5961 expr1
.X_add_number
= off
;
5963 expr1
.X_add_number
= 0;
5964 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5965 (int) BFD_RELOC_LO16
, AT
);
5966 if (! target_big_endian
)
5967 expr1
.X_add_number
= 0;
5969 expr1
.X_add_number
= off
;
5970 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5971 (int) BFD_RELOC_LO16
, AT
);
5976 load_address (&icnt
, AT
, &offset_expr
);
5978 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5979 mips_isa
< 3 ? "addu" : "daddu",
5980 "d,v,t", AT
, AT
, breg
);
5981 if (target_big_endian
)
5982 expr1
.X_add_number
= 0;
5983 macro_build ((char *) NULL
, &icnt
, &expr1
,
5984 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5985 (int) BFD_RELOC_LO16
, AT
);
5986 if (target_big_endian
)
5987 expr1
.X_add_number
= 1;
5989 expr1
.X_add_number
= 0;
5990 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5991 (int) BFD_RELOC_LO16
, AT
);
5992 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5994 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5999 if (offset_expr
.X_add_number
>= 0x7fff)
6000 as_bad ("operand overflow");
6001 if (target_big_endian
)
6002 offset_expr
.X_add_number
+= 1;
6003 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6004 (int) BFD_RELOC_LO16
, breg
);
6005 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6006 if (target_big_endian
)
6007 offset_expr
.X_add_number
-= 1;
6009 offset_expr
.X_add_number
+= 1;
6010 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6011 (int) BFD_RELOC_LO16
, breg
);
6024 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6025 as_bad ("operand overflow");
6026 if (! target_big_endian
)
6027 offset_expr
.X_add_number
+= off
;
6028 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6029 (int) BFD_RELOC_LO16
, breg
);
6030 if (! target_big_endian
)
6031 offset_expr
.X_add_number
-= off
;
6033 offset_expr
.X_add_number
+= off
;
6034 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6035 (int) BFD_RELOC_LO16
, breg
);
6048 load_address (&icnt
, AT
, &offset_expr
);
6050 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6051 mips_isa
< 3 ? "addu" : "daddu",
6052 "d,v,t", AT
, AT
, breg
);
6053 if (! target_big_endian
)
6054 expr1
.X_add_number
= off
;
6056 expr1
.X_add_number
= 0;
6057 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6058 (int) BFD_RELOC_LO16
, AT
);
6059 if (! target_big_endian
)
6060 expr1
.X_add_number
= 0;
6062 expr1
.X_add_number
= off
;
6063 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6064 (int) BFD_RELOC_LO16
, AT
);
6068 load_address (&icnt
, AT
, &offset_expr
);
6070 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6071 mips_isa
< 3 ? "addu" : "daddu",
6072 "d,v,t", AT
, AT
, breg
);
6073 if (! target_big_endian
)
6074 expr1
.X_add_number
= 0;
6075 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6076 (int) BFD_RELOC_LO16
, AT
);
6077 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6079 if (! target_big_endian
)
6080 expr1
.X_add_number
= 1;
6082 expr1
.X_add_number
= 0;
6083 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6084 (int) BFD_RELOC_LO16
, AT
);
6085 if (! target_big_endian
)
6086 expr1
.X_add_number
= 0;
6088 expr1
.X_add_number
= 1;
6089 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6090 (int) BFD_RELOC_LO16
, AT
);
6091 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6093 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6098 /* FIXME: Check if this is one of the itbl macros, since they
6099 are added dynamically. */
6100 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
6104 as_warn ("Macro used $at after \".set noat\"");
6107 /* Implement macros in mips16 mode. */
6111 struct mips_cl_insn
*ip
;
6114 int xreg
, yreg
, zreg
, tmp
;
6118 const char *s
, *s2
, *s3
;
6120 mask
= ip
->insn_mo
->mask
;
6122 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6123 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6124 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6128 expr1
.X_op
= O_constant
;
6129 expr1
.X_op_symbol
= NULL
;
6130 expr1
.X_add_symbol
= NULL
;
6131 expr1
.X_add_number
= 1;
6150 mips_emit_delays (true);
6152 mips_any_noreorder
= 1;
6153 macro_build ((char *) NULL
, &icnt
, NULL
,
6154 dbl
? "ddiv" : "div",
6155 "0,x,y", xreg
, yreg
);
6156 expr1
.X_add_number
= 2;
6157 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6158 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6159 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6160 since that causes an overflow. We should do that as well,
6161 but I don't see how to do the comparisons without a temporary
6164 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6183 mips_emit_delays (true);
6185 mips_any_noreorder
= 1;
6186 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6187 expr1
.X_add_number
= 2;
6188 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6189 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6191 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6199 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6200 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6201 dbl
? "daddiu" : "addiu",
6202 "y,x,4", yreg
, xreg
);
6206 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6207 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6212 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6213 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6236 goto do_reverse_branch
;
6240 goto do_reverse_branch
;
6252 goto do_reverse_branch
;
6263 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6265 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6292 goto do_addone_branch_i
;
6297 goto do_addone_branch_i
;
6312 goto do_addone_branch_i
;
6319 ++imm_expr
.X_add_number
;
6322 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6323 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6327 expr1
.X_add_number
= 0;
6328 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6330 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6331 "move", "y,X", xreg
, yreg
);
6332 expr1
.X_add_number
= 2;
6333 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6334 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6335 "neg", "x,w", xreg
, xreg
);
6339 /* This routine assembles an instruction into its binary format. As a
6340 side effect, it sets one of the global variables imm_reloc or
6341 offset_reloc to the type of relocation to do if one of the operands
6342 is an address expression. */
6347 struct mips_cl_insn
*ip
;
6352 struct mips_opcode
*insn
;
6355 unsigned int lastregno
= 0;
6360 for (s
= str
; *s
!= '\0' && !isspace(*s
); ++s
)
6365 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6367 insn_error
= "unrecognized opcode";
6375 assert (strcmp (insn
->name
, str
) == 0);
6377 if (insn
->pinfo
== INSN_MACRO
)
6378 insn_isa
= insn
->match
;
6379 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6381 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6383 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6388 if (insn_isa
> mips_isa
6389 || (insn
->pinfo
!= INSN_MACRO
6390 && (((insn
->pinfo
& INSN_ISA
) == INSN_4650
6392 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6394 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6396 /* start-sanitize-r5900 */
6397 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6399 /* end-sanitize-r5900 */
6402 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6403 && strcmp (insn
->name
, insn
[1].name
) == 0)
6408 if (insn_isa
<= mips_isa
)
6409 insn_error
= "opcode not supported on this processor";
6412 static char buf
[100];
6414 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6421 ip
->insn_opcode
= insn
->match
;
6422 for (args
= insn
->args
;; ++args
)
6428 case '\0': /* end of args */
6441 ip
->insn_opcode
|= lastregno
<< 21;
6446 ip
->insn_opcode
|= lastregno
<< 16;
6450 ip
->insn_opcode
|= lastregno
<< 11;
6456 /* handle optional base register.
6457 Either the base register is omitted or
6458 we must have a left paren. */
6459 /* this is dependent on the next operand specifier
6460 is a 'b' for base register */
6461 assert (args
[1] == 'b');
6465 case ')': /* these must match exactly */
6470 case '<': /* must be at least one digit */
6472 * According to the manual, if the shift amount is greater
6473 * than 31 or less than 0 the the shift amount should be
6474 * mod 32. In reality the mips assembler issues an error.
6475 * We issue a warning and mask out all but the low 5 bits.
6477 my_getExpression (&imm_expr
, s
);
6478 check_absolute_expr (ip
, &imm_expr
);
6479 if ((unsigned long) imm_expr
.X_add_number
> 31)
6481 as_warn ("Improper shift amount (%ld)",
6482 (long) imm_expr
.X_add_number
);
6483 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6485 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6486 imm_expr
.X_op
= O_absent
;
6490 case '>': /* shift amount minus 32 */
6491 my_getExpression (&imm_expr
, s
);
6492 check_absolute_expr (ip
, &imm_expr
);
6493 if ((unsigned long) imm_expr
.X_add_number
< 32
6494 || (unsigned long) imm_expr
.X_add_number
> 63)
6496 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6497 imm_expr
.X_op
= O_absent
;
6501 case 'k': /* cache code */
6502 case 'h': /* prefx code */
6503 my_getExpression (&imm_expr
, s
);
6504 check_absolute_expr (ip
, &imm_expr
);
6505 if ((unsigned long) imm_expr
.X_add_number
> 31)
6507 as_warn ("Invalid value for `%s' (%lu)",
6509 (unsigned long) imm_expr
.X_add_number
);
6510 imm_expr
.X_add_number
&= 0x1f;
6513 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6515 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6516 imm_expr
.X_op
= O_absent
;
6520 case 'c': /* break code */
6521 my_getExpression (&imm_expr
, s
);
6522 check_absolute_expr (ip
, &imm_expr
);
6523 if ((unsigned) imm_expr
.X_add_number
> 1023)
6524 as_warn ("Illegal break code (%ld)",
6525 (long) imm_expr
.X_add_number
);
6526 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6527 imm_expr
.X_op
= O_absent
;
6531 case 'B': /* syscall code */
6532 my_getExpression (&imm_expr
, s
);
6533 check_absolute_expr (ip
, &imm_expr
);
6534 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6535 as_warn ("Illegal syscall code (%ld)",
6536 (long) imm_expr
.X_add_number
);
6537 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6538 imm_expr
.X_op
= O_absent
;
6542 case 'C': /* Coprocessor code */
6543 my_getExpression (&imm_expr
, s
);
6544 check_absolute_expr (ip
, &imm_expr
);
6545 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6547 as_warn ("Coproccesor code > 25 bits (%ld)",
6548 (long) imm_expr
.X_add_number
);
6549 imm_expr
.X_add_number
&= ((1<<25) - 1);
6551 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6552 imm_expr
.X_op
= O_absent
;
6556 case 'b': /* base register */
6557 case 'd': /* destination register */
6558 case 's': /* source register */
6559 case 't': /* target register */
6560 case 'r': /* both target and source */
6561 case 'v': /* both dest and source */
6562 case 'w': /* both dest and target */
6563 case 'E': /* coprocessor target register */
6564 case 'G': /* coprocessor destination register */
6565 case 'x': /* ignore register name */
6566 case 'z': /* must be zero register */
6580 while (isdigit (*s
));
6582 as_bad ("Invalid register number (%d)", regno
);
6584 else if (*args
== 'E' || *args
== 'G')
6588 if (s
[1] == 'f' && s
[2] == 'p')
6593 else if (s
[1] == 's' && s
[2] == 'p')
6598 else if (s
[1] == 'g' && s
[2] == 'p')
6603 else if (s
[1] == 'a' && s
[2] == 't')
6608 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6613 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6618 else if (itbl_have_entries
)
6623 p
= s
+1; /* advance past '$' */
6624 n
= itbl_get_field (&p
); /* n is name */
6626 /* See if this is a register defined in an
6628 r
= itbl_get_reg_val (n
);
6631 /* Get_field advances to the start of
6632 the next field, so we need to back
6633 rack to the end of the last field. */
6637 s
= strchr (s
,'\0');
6650 as_warn ("Used $at without \".set noat\"");
6656 if (c
== 'r' || c
== 'v' || c
== 'w')
6663 /* 'z' only matches $0. */
6664 if (c
== 'z' && regno
!= 0)
6667 /* Now that we have assembled one operand, we use the args string
6668 * to figure out where it goes in the instruction. */
6675 ip
->insn_opcode
|= regno
<< 21;
6679 ip
->insn_opcode
|= regno
<< 11;
6684 ip
->insn_opcode
|= regno
<< 16;
6687 /* This case exists because on the r3000 trunc
6688 expands into a macro which requires a gp
6689 register. On the r6000 or r4000 it is
6690 assembled into a single instruction which
6691 ignores the register. Thus the insn version
6692 is MIPS_ISA2 and uses 'x', and the macro
6693 version is MIPS_ISA1 and uses 't'. */
6696 /* This case is for the div instruction, which
6697 acts differently if the destination argument
6698 is $0. This only matches $0, and is checked
6699 outside the switch. */
6702 /* Itbl operand; not yet implemented. FIXME ?? */
6704 /* What about all other operands like 'i', which
6705 can be specified in the opcode table? */
6715 ip
->insn_opcode
|= lastregno
<< 21;
6718 ip
->insn_opcode
|= lastregno
<< 16;
6723 case 'D': /* floating point destination register */
6724 case 'S': /* floating point source register */
6725 case 'T': /* floating point target register */
6726 case 'R': /* floating point source register */
6730 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6740 while (isdigit (*s
));
6743 as_bad ("Invalid float register number (%d)", regno
);
6745 if ((regno
& 1) != 0
6747 && ! (strcmp (str
, "mtc1") == 0
6748 || strcmp (str
, "mfc1") == 0
6749 || strcmp (str
, "lwc1") == 0
6750 || strcmp (str
, "swc1") == 0
6751 || strcmp (str
, "l.s") == 0
6752 || strcmp (str
, "s.s") == 0))
6753 as_warn ("Float register should be even, was %d",
6761 if (c
== 'V' || c
== 'W')
6771 ip
->insn_opcode
|= regno
<< 6;
6775 ip
->insn_opcode
|= regno
<< 11;
6779 ip
->insn_opcode
|= regno
<< 16;
6782 ip
->insn_opcode
|= regno
<< 21;
6791 ip
->insn_opcode
|= lastregno
<< 11;
6794 ip
->insn_opcode
|= lastregno
<< 16;
6800 my_getExpression (&imm_expr
, s
);
6801 if (imm_expr
.X_op
!= O_big
6802 && imm_expr
.X_op
!= O_constant
)
6803 insn_error
= "absolute expression required";
6808 my_getExpression (&offset_expr
, s
);
6809 imm_reloc
= BFD_RELOC_32
;
6821 unsigned char temp
[8];
6823 unsigned int length
;
6828 /* These only appear as the last operand in an
6829 instruction, and every instruction that accepts
6830 them in any variant accepts them in all variants.
6831 This means we don't have to worry about backing out
6832 any changes if the instruction does not match.
6834 The difference between them is the size of the
6835 floating point constant and where it goes. For 'F'
6836 and 'L' the constant is 64 bits; for 'f' and 'l' it
6837 is 32 bits. Where the constant is placed is based
6838 on how the MIPS assembler does things:
6841 f -- immediate value
6844 The .lit4 and .lit8 sections are only used if
6845 permitted by the -G argument.
6847 When generating embedded PIC code, we use the
6848 .lit8 section but not the .lit4 section (we can do
6849 .lit4 inline easily; we need to put .lit8
6850 somewhere in the data segment, and using .lit8
6851 permits the linker to eventually combine identical
6854 f64
= *args
== 'F' || *args
== 'L';
6856 save_in
= input_line_pointer
;
6857 input_line_pointer
= s
;
6858 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6860 s
= input_line_pointer
;
6861 input_line_pointer
= save_in
;
6862 if (err
!= NULL
&& *err
!= '\0')
6864 as_bad ("Bad floating point constant: %s", err
);
6865 memset (temp
, '\0', sizeof temp
);
6866 length
= f64
? 8 : 4;
6869 assert (length
== (f64
? 8 : 4));
6873 && (! USE_GLOBAL_POINTER_OPT
6874 || mips_pic
== EMBEDDED_PIC
6875 || g_switch_value
< 4)
6878 imm_expr
.X_op
= O_constant
;
6879 if (! target_big_endian
)
6880 imm_expr
.X_add_number
=
6881 (((((((int) temp
[3] << 8)
6886 imm_expr
.X_add_number
=
6887 (((((((int) temp
[0] << 8)
6894 const char *newname
;
6897 /* Switch to the right section. */
6899 subseg
= now_subseg
;
6902 default: /* unused default case avoids warnings. */
6904 newname
= RDATA_SECTION_NAME
;
6905 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6909 newname
= RDATA_SECTION_NAME
;
6912 assert (!USE_GLOBAL_POINTER_OPT
6913 || g_switch_value
>= 4);
6917 new_seg
= subseg_new (newname
, (subsegT
) 0);
6918 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6919 bfd_set_section_flags (stdoutput
, new_seg
,
6924 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
6925 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
6926 && strcmp (TARGET_OS
, "elf") != 0)
6927 record_alignment (new_seg
, 4);
6929 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6931 as_bad ("Can't use floating point insn in this section");
6933 /* Set the argument to the current address in the
6935 offset_expr
.X_op
= O_symbol
;
6936 offset_expr
.X_add_symbol
=
6937 symbol_new ("L0\001", now_seg
,
6938 (valueT
) frag_now_fix (), frag_now
);
6939 offset_expr
.X_add_number
= 0;
6941 /* Put the floating point number into the section. */
6942 p
= frag_more ((int) length
);
6943 memcpy (p
, temp
, length
);
6945 /* Switch back to the original section. */
6946 subseg_set (seg
, subseg
);
6951 case 'i': /* 16 bit unsigned immediate */
6952 case 'j': /* 16 bit signed immediate */
6953 imm_reloc
= BFD_RELOC_LO16
;
6954 c
= my_getSmallExpression (&imm_expr
, s
);
6959 if (imm_expr
.X_op
== O_constant
)
6960 imm_expr
.X_add_number
=
6961 (imm_expr
.X_add_number
>> 16) & 0xffff;
6964 imm_reloc
= BFD_RELOC_HI16_S
;
6965 imm_unmatched_hi
= true;
6968 imm_reloc
= BFD_RELOC_HI16
;
6973 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6974 || ((imm_expr
.X_add_number
< 0
6975 || imm_expr
.X_add_number
>= 0x10000)
6976 && imm_expr
.X_op
== O_constant
))
6978 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6979 !strcmp (insn
->name
, insn
[1].name
))
6981 if (imm_expr
.X_op
!= O_constant
6982 && imm_expr
.X_op
!= O_big
)
6983 insn_error
= "absolute expression required";
6985 as_bad ("16 bit expression not in range 0..65535");
6993 /* The upper bound should be 0x8000, but
6994 unfortunately the MIPS assembler accepts numbers
6995 from 0x8000 to 0xffff and sign extends them, and
6996 we want to be compatible. We only permit this
6997 extended range for an instruction which does not
6998 provide any further alternates, since those
6999 alternates may handle other cases. People should
7000 use the numbers they mean, rather than relying on
7001 a mysterious sign extension. */
7002 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7003 strcmp (insn
->name
, insn
[1].name
) == 0);
7008 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7009 || ((imm_expr
.X_add_number
< -0x8000
7010 || imm_expr
.X_add_number
>= max
)
7011 && imm_expr
.X_op
== O_constant
)
7013 && imm_expr
.X_add_number
< 0
7015 && imm_expr
.X_unsigned
7016 && sizeof (imm_expr
.X_add_number
) <= 4))
7020 if (imm_expr
.X_op
!= O_constant
7021 && imm_expr
.X_op
!= O_big
)
7022 insn_error
= "absolute expression required";
7024 as_bad ("16 bit expression not in range -32768..32767");
7030 case 'o': /* 16 bit offset */
7031 c
= my_getSmallExpression (&offset_expr
, s
);
7033 /* If this value won't fit into a 16 bit offset, then go
7034 find a macro that will generate the 32 bit offset
7035 code pattern. As a special hack, we accept the
7036 difference of two local symbols as a constant. This
7037 is required to suppose embedded PIC switches, which
7038 use an instruction which looks like
7039 lw $4,$L12-$LS12($4)
7040 The problem with handling this in a more general
7041 fashion is that the macro function doesn't expect to
7042 see anything which can be handled in a single
7043 constant instruction. */
7045 && (offset_expr
.X_op
!= O_constant
7046 || offset_expr
.X_add_number
>= 0x8000
7047 || offset_expr
.X_add_number
< -0x8000)
7048 && (mips_pic
!= EMBEDDED_PIC
7049 || offset_expr
.X_op
!= O_subtract
7050 || now_seg
!= text_section
7051 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7055 offset_reloc
= BFD_RELOC_LO16
;
7056 if (c
== 'h' || c
== 'H')
7058 assert (offset_expr
.X_op
== O_constant
);
7059 offset_expr
.X_add_number
=
7060 (offset_expr
.X_add_number
>> 16) & 0xffff;
7065 case 'p': /* pc relative offset */
7066 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7067 my_getExpression (&offset_expr
, s
);
7071 case 'u': /* upper 16 bits */
7072 c
= my_getSmallExpression (&imm_expr
, s
);
7073 if (imm_expr
.X_op
== O_constant
7074 && (imm_expr
.X_add_number
< 0
7075 || imm_expr
.X_add_number
>= 0x10000))
7076 as_bad ("lui expression not in range 0..65535");
7077 imm_reloc
= BFD_RELOC_LO16
;
7082 if (imm_expr
.X_op
== O_constant
)
7083 imm_expr
.X_add_number
=
7084 (imm_expr
.X_add_number
>> 16) & 0xffff;
7087 imm_reloc
= BFD_RELOC_HI16_S
;
7088 imm_unmatched_hi
= true;
7091 imm_reloc
= BFD_RELOC_HI16
;
7097 case 'a': /* 26 bit address */
7098 my_getExpression (&offset_expr
, s
);
7100 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7103 case 'N': /* 3 bit branch condition code */
7104 case 'M': /* 3 bit compare condition code */
7105 if (strncmp (s
, "$fcc", 4) != 0)
7115 while (isdigit (*s
));
7117 as_bad ("invalid condition code register $fcc%d", regno
);
7119 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7121 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7125 fprintf (stderr
, "bad char = '%c'\n", *args
);
7130 /* Args don't match. */
7131 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7132 !strcmp (insn
->name
, insn
[1].name
))
7138 insn_error
= "illegal operands";
7143 /* This routine assembles an instruction into its binary format when
7144 assembling for the mips16. As a side effect, it sets one of the
7145 global variables imm_reloc or offset_reloc to the type of
7146 relocation to do if one of the operands is an address expression.
7147 It also sets mips16_small and mips16_ext if the user explicitly
7148 requested a small or extended instruction. */
7153 struct mips_cl_insn
*ip
;
7157 struct mips_opcode
*insn
;
7160 unsigned int lastregno
= 0;
7165 mips16_small
= false;
7168 for (s
= str
; islower (*s
); ++s
)
7180 if (s
[1] == 't' && s
[2] == ' ')
7183 mips16_small
= true;
7187 else if (s
[1] == 'e' && s
[2] == ' ')
7196 insn_error
= "unknown opcode";
7200 if (! mips16_autoextend
&& ! mips16_ext
)
7201 mips16_small
= true;
7203 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7205 insn_error
= "unrecognized opcode";
7212 assert (strcmp (insn
->name
, str
) == 0);
7215 ip
->insn_opcode
= insn
->match
;
7216 ip
->use_extend
= false;
7217 imm_expr
.X_op
= O_absent
;
7218 imm_reloc
= BFD_RELOC_UNUSED
;
7219 offset_expr
.X_op
= O_absent
;
7220 offset_reloc
= BFD_RELOC_UNUSED
;
7221 for (args
= insn
->args
; 1; ++args
)
7228 /* In this switch statement we call break if we did not find
7229 a match, continue if we did find a match, or return if we
7238 /* Stuff the immediate value in now, if we can. */
7239 if (imm_expr
.X_op
== O_constant
7240 && imm_reloc
> BFD_RELOC_UNUSED
7241 && insn
->pinfo
!= INSN_MACRO
)
7243 mips16_immed ((char *) NULL
, 0,
7244 imm_reloc
- BFD_RELOC_UNUSED
,
7245 imm_expr
.X_add_number
, true, mips16_small
,
7246 mips16_ext
, &ip
->insn_opcode
,
7247 &ip
->use_extend
, &ip
->extend
);
7248 imm_expr
.X_op
= O_absent
;
7249 imm_reloc
= BFD_RELOC_UNUSED
;
7263 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7266 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7282 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
7284 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7311 while (isdigit (*s
));
7314 as_bad ("invalid register number (%d)", regno
);
7320 if (s
[1] == 'f' && s
[2] == 'p')
7325 else if (s
[1] == 's' && s
[2] == 'p')
7330 else if (s
[1] == 'g' && s
[2] == 'p')
7335 else if (s
[1] == 'a' && s
[2] == 't')
7340 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7345 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7358 if (c
== 'v' || c
== 'w')
7360 regno
= mips16_to_32_reg_map
[lastregno
];
7374 regno
= mips32_to_16_reg_map
[regno
];
7379 regno
= ILLEGAL_REG
;
7384 regno
= ILLEGAL_REG
;
7389 regno
= ILLEGAL_REG
;
7394 if (regno
== AT
&& ! mips_noat
)
7395 as_warn ("used $at without \".set noat\"");
7402 if (regno
== ILLEGAL_REG
)
7409 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7413 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7416 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7419 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7425 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7428 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7429 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7439 if (strncmp (s
, "$pc", 3) == 0)
7463 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
7465 /* This is %gprel(SYMBOL). We need to read SYMBOL,
7466 and generate the appropriate reloc. If the text
7467 inside %gprel is not a symbol name with an
7468 optional offset, then we generate a normal reloc
7469 and will probably fail later. */
7470 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
7471 if (imm_expr
.X_op
== O_symbol
)
7474 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
7476 ip
->use_extend
= true;
7483 /* Just pick up a normal expression. */
7484 my_getExpression (&imm_expr
, s
);
7487 if (imm_expr
.X_op
== O_register
)
7489 /* What we thought was an expression turned out to
7492 if (s
[0] == '(' && args
[1] == '(')
7494 /* It looks like the expression was omitted
7495 before a register indirection, which means
7496 that the expression is implicitly zero. We
7497 still set up imm_expr, so that we handle
7498 explicit extensions correctly. */
7499 imm_expr
.X_op
= O_constant
;
7500 imm_expr
.X_add_number
= 0;
7501 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7508 /* We need to relax this instruction. */
7509 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7518 /* We use offset_reloc rather than imm_reloc for the PC
7519 relative operands. This lets macros with both
7520 immediate and address operands work correctly. */
7521 my_getExpression (&offset_expr
, s
);
7523 if (offset_expr
.X_op
== O_register
)
7526 /* We need to relax this instruction. */
7527 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7531 case '6': /* break code */
7532 my_getExpression (&imm_expr
, s
);
7533 check_absolute_expr (ip
, &imm_expr
);
7534 if ((unsigned long) imm_expr
.X_add_number
> 63)
7536 as_warn ("Invalid value for `%s' (%lu)",
7538 (unsigned long) imm_expr
.X_add_number
);
7539 imm_expr
.X_add_number
&= 0x3f;
7541 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7542 imm_expr
.X_op
= O_absent
;
7546 case 'a': /* 26 bit address */
7547 my_getExpression (&offset_expr
, s
);
7549 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7550 ip
->insn_opcode
<<= 16;
7553 case 'l': /* register list for entry macro */
7554 case 'L': /* register list for exit macro */
7564 int freg
, reg1
, reg2
;
7566 while (*s
== ' ' || *s
== ',')
7570 as_bad ("can't parse register list");
7582 while (isdigit (*s
))
7604 as_bad ("invalid register list");
7609 while (isdigit (*s
))
7616 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7621 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7626 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7627 mask
|= (reg2
- 3) << 3;
7628 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7629 mask
|= (reg2
- 15) << 1;
7630 else if (reg1
== 31 && reg2
== 31)
7634 as_bad ("invalid register list");
7638 /* The mask is filled in in the opcode table for the
7639 benefit of the disassembler. We remove it before
7640 applying the actual mask. */
7641 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7642 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7646 case 'e': /* extend code */
7647 my_getExpression (&imm_expr
, s
);
7648 check_absolute_expr (ip
, &imm_expr
);
7649 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
7651 as_warn ("Invalid value for `%s' (%lu)",
7653 (unsigned long) imm_expr
.X_add_number
);
7654 imm_expr
.X_add_number
&= 0x7ff;
7656 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7657 imm_expr
.X_op
= O_absent
;
7667 /* Args don't match. */
7668 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7669 strcmp (insn
->name
, insn
[1].name
) == 0)
7676 insn_error
= "illegal operands";
7682 /* This structure holds information we know about a mips16 immediate
7685 struct mips16_immed_operand
7687 /* The type code used in the argument string in the opcode table. */
7689 /* The number of bits in the short form of the opcode. */
7691 /* The number of bits in the extended form of the opcode. */
7693 /* The amount by which the short form is shifted when it is used;
7694 for example, the sw instruction has a shift count of 2. */
7696 /* The amount by which the short form is shifted when it is stored
7697 into the instruction code. */
7699 /* Non-zero if the short form is unsigned. */
7701 /* Non-zero if the extended form is unsigned. */
7703 /* Non-zero if the value is PC relative. */
7707 /* The mips16 immediate operand types. */
7709 static const struct mips16_immed_operand mips16_immed_operands
[] =
7711 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7712 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7713 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7714 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7715 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7716 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7717 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7718 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7719 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7720 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7721 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7722 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7723 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7724 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7725 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7726 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7727 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7728 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7729 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7730 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7731 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7734 #define MIPS16_NUM_IMMED \
7735 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7737 /* Handle a mips16 instruction with an immediate value. This or's the
7738 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7739 whether an extended value is needed; if one is needed, it sets
7740 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7741 If SMALL is true, an unextended opcode was explicitly requested.
7742 If EXT is true, an extended opcode was explicitly requested. If
7743 WARN is true, warn if EXT does not match reality. */
7746 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7755 unsigned long *insn
;
7756 boolean
*use_extend
;
7757 unsigned short *extend
;
7759 register const struct mips16_immed_operand
*op
;
7760 int mintiny
, maxtiny
;
7763 op
= mips16_immed_operands
;
7764 while (op
->type
!= type
)
7767 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7772 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7775 maxtiny
= 1 << op
->nbits
;
7780 maxtiny
= (1 << op
->nbits
) - 1;
7785 mintiny
= - (1 << (op
->nbits
- 1));
7786 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7789 /* Branch offsets have an implicit 0 in the lowest bit. */
7790 if (type
== 'p' || type
== 'q')
7793 if ((val
& ((1 << op
->shift
) - 1)) != 0
7794 || val
< (mintiny
<< op
->shift
)
7795 || val
> (maxtiny
<< op
->shift
))
7800 if (warn
&& ext
&& ! needext
)
7801 as_warn_where (file
, line
, "extended operand requested but not required");
7802 if (small
&& needext
)
7803 as_bad_where (file
, line
, "invalid unextended operand value");
7805 if (small
|| (! ext
&& ! needext
))
7809 *use_extend
= false;
7810 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7811 insnval
<<= op
->op_shift
;
7816 long minext
, maxext
;
7822 maxext
= (1 << op
->extbits
) - 1;
7826 minext
= - (1 << (op
->extbits
- 1));
7827 maxext
= (1 << (op
->extbits
- 1)) - 1;
7829 if (val
< minext
|| val
> maxext
)
7830 as_bad_where (file
, line
,
7831 "operand value out of range for instruction");
7834 if (op
->extbits
== 16)
7836 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7839 else if (op
->extbits
== 15)
7841 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7846 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7850 *extend
= (unsigned short) extval
;
7859 my_getSmallExpression (ep
, str
)
7870 ((str
[1] == 'h' && str
[2] == 'i')
7871 || (str
[1] == 'H' && str
[2] == 'I')
7872 || (str
[1] == 'l' && str
[2] == 'o'))
7884 * A small expression may be followed by a base register.
7885 * Scan to the end of this operand, and then back over a possible
7886 * base register. Then scan the small expression up to that
7887 * point. (Based on code in sparc.c...)
7889 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7891 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7893 if (isdigit (sp
[-2]))
7895 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7897 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7903 else if (sp
- 5 >= str
7906 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7907 || (sp
[-3] == 's' && sp
[-2] == 'p')
7908 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7909 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7915 /* no expression means zero offset */
7918 /* %xx(reg) is an error */
7919 ep
->X_op
= O_absent
;
7924 ep
->X_op
= O_constant
;
7927 ep
->X_add_symbol
= NULL
;
7928 ep
->X_op_symbol
= NULL
;
7929 ep
->X_add_number
= 0;
7934 my_getExpression (ep
, str
);
7941 my_getExpression (ep
, str
);
7942 return c
; /* => %hi or %lo encountered */
7946 my_getExpression (ep
, str
)
7952 save_in
= input_line_pointer
;
7953 input_line_pointer
= str
;
7955 expr_end
= input_line_pointer
;
7956 input_line_pointer
= save_in
;
7958 /* If we are in mips16 mode, and this is an expression based on `.',
7959 then we bump the value of the symbol by 1 since that is how other
7960 text symbols are handled. We don't bother to handle complex
7961 expressions, just `.' plus or minus a constant. */
7963 && ep
->X_op
== O_symbol
7964 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
7965 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
7966 && ep
->X_add_symbol
->sy_frag
== frag_now
7967 && ep
->X_add_symbol
->sy_value
.X_op
== O_constant
7968 && ep
->X_add_symbol
->sy_value
.X_add_number
== frag_now_fix ())
7969 ++ep
->X_add_symbol
->sy_value
.X_add_number
;
7972 /* Turn a string in input_line_pointer into a floating point constant
7973 of type type, and store the appropriate bytes in *litP. The number
7974 of LITTLENUMS emitted is stored in *sizeP . An error message is
7975 returned, or NULL on OK. */
7978 md_atof (type
, litP
, sizeP
)
7984 LITTLENUM_TYPE words
[4];
8000 return "bad call to md_atof";
8003 t
= atof_ieee (input_line_pointer
, type
, words
);
8005 input_line_pointer
= t
;
8009 if (! target_big_endian
)
8011 for (i
= prec
- 1; i
>= 0; i
--)
8013 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8019 for (i
= 0; i
< prec
; i
++)
8021 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8030 md_number_to_chars (buf
, val
, n
)
8035 if (target_big_endian
)
8036 number_to_chars_bigendian (buf
, val
, n
);
8038 number_to_chars_littleendian (buf
, val
, n
);
8041 CONST
char *md_shortopts
= "O::g::G:";
8043 struct option md_longopts
[] = {
8044 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8045 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8046 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8047 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8048 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8049 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8050 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8051 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8052 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8053 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8054 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8055 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8056 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8057 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8058 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8059 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8060 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8061 {"break", no_argument
, NULL
, OPTION_BREAK
},
8062 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8063 #define OPTION_EB (OPTION_MD_BASE + 11)
8064 {"EB", no_argument
, NULL
, OPTION_EB
},
8065 #define OPTION_EL (OPTION_MD_BASE + 12)
8066 {"EL", no_argument
, NULL
, OPTION_EL
},
8067 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8068 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8069 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8070 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8071 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8072 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8073 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8074 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8075 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8076 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8077 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8078 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8079 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8080 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8081 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8082 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8083 /* start-sanitize-r5900 */
8084 #define OPTION_M5900 (OPTION_MD_BASE + 24)
8085 {"m5900", no_argument
, NULL
, OPTION_M5900
},
8086 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
8087 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
8088 /* end-sanitize-r5900 */
8090 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8091 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8092 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8093 #define OPTION_32 (OPTION_MD_BASE + 20)
8094 #define OPTION_64 (OPTION_MD_BASE + 21)
8096 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8097 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8098 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8099 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8100 {"32", no_argument
, NULL
, OPTION_32
},
8101 {"64", no_argument
, NULL
, OPTION_64
},
8104 {NULL
, no_argument
, NULL
, 0}
8106 size_t md_longopts_size
= sizeof(md_longopts
);
8109 md_parse_option (c
, arg
)
8124 target_big_endian
= 1;
8128 target_big_endian
= 0;
8132 if (arg
&& arg
[1] == '0')
8142 mips_debug
= atoi (arg
);
8143 /* When the MIPS assembler sees -g or -g2, it does not do
8144 optimizations which limit full symbolic debugging. We take
8145 that to be equivalent to -O0. */
8146 if (mips_debug
== 2)
8178 /* Identify the processor type */
8180 if (strcmp (p
, "default") == 0
8181 || strcmp (p
, "DEFAULT") == 0)
8187 /* We need to cope with the various "vr" prefixes for the 4300
8189 if (*p
== 'v' || *p
== 'V')
8195 if (*p
== 'r' || *p
== 'R')
8202 if (strcmp (p
, "10000") == 0
8203 || strcmp (p
, "10k") == 0
8204 || strcmp (p
, "10K") == 0)
8209 if (strcmp (p
, "2000") == 0
8210 || strcmp (p
, "2k") == 0
8211 || strcmp (p
, "2K") == 0)
8216 if (strcmp (p
, "3000") == 0
8217 || strcmp (p
, "3k") == 0
8218 || strcmp (p
, "3K") == 0)
8223 if (strcmp (p
, "4000") == 0
8224 || strcmp (p
, "4k") == 0
8225 || strcmp (p
, "4K") == 0)
8227 else if (strcmp (p
, "4100") == 0)
8233 else if (strcmp (p
, "4300") == 0)
8235 else if (strcmp (p
, "4400") == 0)
8237 else if (strcmp (p
, "4600") == 0)
8239 else if (strcmp (p
, "4650") == 0)
8245 else if (strcmp (p
, "4010") == 0)
8254 if (strcmp (p
, "5000") == 0
8255 || strcmp (p
, "5k") == 0
8256 || strcmp (p
, "5K") == 0)
8258 /* start-sanitize-r5900 */
8259 else if (strcmp (p
, "5900") == 0)
8261 /* end-sanitize-r5900 */
8265 if (strcmp (p
, "6000") == 0
8266 || strcmp (p
, "6k") == 0
8267 || strcmp (p
, "6K") == 0)
8272 if (strcmp (p
, "8000") == 0
8273 || strcmp (p
, "8k") == 0
8274 || strcmp (p
, "8K") == 0)
8279 if (strcmp (p
, "orion") == 0)
8284 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
8286 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
8292 as_bad ("invalid architecture -mcpu=%s", arg
);
8303 case OPTION_NO_M4650
:
8311 case OPTION_NO_M4010
:
8319 case OPTION_NO_M4100
:
8323 /* start-sanitize-r5900 */
8328 case OPTION_NO_M5900
:
8331 /* end-sanitize-r5900 */
8335 mips_no_prev_insn (false);
8338 case OPTION_NO_MIPS16
:
8340 mips_no_prev_insn (false);
8343 case OPTION_MEMBEDDED_PIC
:
8344 mips_pic
= EMBEDDED_PIC
;
8345 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8347 as_bad ("-G may not be used with embedded PIC code");
8350 g_switch_value
= 0x7fffffff;
8353 /* When generating ELF code, we permit -KPIC and -call_shared to
8354 select SVR4_PIC, and -non_shared to select no PIC. This is
8355 intended to be compatible with Irix 5. */
8356 case OPTION_CALL_SHARED
:
8357 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8359 as_bad ("-call_shared is supported only for ELF format");
8362 mips_pic
= SVR4_PIC
;
8363 if (g_switch_seen
&& g_switch_value
!= 0)
8365 as_bad ("-G may not be used with SVR4 PIC code");
8371 case OPTION_NON_SHARED
:
8372 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8374 as_bad ("-non_shared is supported only for ELF format");
8380 /* The -xgot option tells the assembler to use 32 offsets when
8381 accessing the got in SVR4_PIC mode. It is for Irix
8388 if (! USE_GLOBAL_POINTER_OPT
)
8390 as_bad ("-G is not supported for this configuration");
8393 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8395 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8399 g_switch_value
= atoi (arg
);
8403 /* The -32 and -64 options tell the assembler to output the 32
8404 bit or the 64 bit MIPS ELF format. */
8411 const char **list
, **l
;
8413 list
= bfd_target_list ();
8414 for (l
= list
; *l
!= NULL
; l
++)
8415 if (strcmp (*l
, "elf64-bigmips") == 0
8416 || strcmp (*l
, "elf64-littlemips") == 0)
8419 as_fatal ("No compiled in support for 64 bit object file format");
8433 md_show_usage (stream
)
8438 -membedded-pic generate embedded position independent code\n\
8439 -EB generate big endian output\n\
8440 -EL generate little endian output\n\
8441 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8442 -G NUM allow referencing objects up to NUM bytes\n\
8443 implicitly with the gp register [default 8]\n");
8445 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8446 -mips2, -mcpu=r6000 generate code for r6000\n\
8447 -mips3, -mcpu=r4000 generate code for r4000\n\
8448 -mips4, -mcpu=r8000 generate code for r8000\n\
8449 -mcpu=vr4300 generate code for vr4300\n\
8450 -mcpu=vr4100 generate code for vr4100\n\
8451 -m4650 permit R4650 instructions\n\
8452 -no-m4650 do not permit R4650 instructions\n\
8453 -m4010 permit R4010 instructions\n\
8454 -no-m4010 do not permit R4010 instructions\n\
8455 -m4100 permit VR4100 instructions\n\
8456 -no-m4100 do not permit VR4100 instructions\n");
8458 -mips16 generate mips16 instructions\n\
8459 -no-mips16 do not generate mips16 instructions\n");
8461 -O0 remove unneeded NOPs, do not swap branches\n\
8462 -O remove unneeded NOPs and swap branches\n\
8463 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8464 --break, --no-trap break exception on div by 0 and mult overflow\n");
8467 -KPIC, -call_shared generate SVR4 position independent code\n\
8468 -non_shared do not generate position independent code\n\
8469 -xgot assume a 32 bit GOT\n\
8470 -32 create 32 bit object file (default)\n\
8471 -64 create 64 bit object file\n");
8476 mips_init_after_args ()
8478 /* initialize opcodes */
8479 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
8480 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
8484 md_pcrel_from (fixP
)
8487 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8488 && fixP
->fx_addsy
!= (symbolS
*) NULL
8489 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8491 /* This makes a branch to an undefined symbol be a branch to the
8492 current location. */
8496 /* return the address of the delay slot */
8497 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8500 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8501 reloc for a cons. We could use the definition there, except that
8502 we want to handle 64 bit relocs specially. */
8505 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8508 unsigned int nbytes
;
8512 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8514 if (nbytes
== 8 && ! mips_64
)
8516 if (target_big_endian
)
8522 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8523 as_bad ("Unsupported reloc size %d", nbytes
);
8525 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8528 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8531 /* This is called before the symbol table is processed. In order to
8532 work with gcc when using mips-tfile, we must keep all local labels.
8533 However, in other cases, we want to discard them. If we were
8534 called with -g, but we didn't see any debugging information, it may
8535 mean that gcc is smuggling debugging information through to
8536 mips-tfile, in which case we must generate all local labels. */
8539 mips_frob_file_before_adjust ()
8541 #ifndef NO_ECOFF_DEBUGGING
8544 && ! ecoff_debugging_seen
)
8545 flag_keep_locals
= 1;
8549 /* Sort any unmatched HI16_S relocs so that they immediately precede
8550 the corresponding LO reloc. This is called before md_apply_fix and
8551 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8552 explicit use of the %hi modifier. */
8557 struct mips_hi_fixup
*l
;
8559 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8561 segment_info_type
*seginfo
;
8564 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8566 /* Check quickly whether the next fixup happens to be a matching
8568 if (l
->fixp
->fx_next
!= NULL
8569 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8570 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8571 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8574 /* Look through the fixups for this segment for a matching %lo.
8575 When we find one, move the %hi just in front of it. We do
8576 this in two passes. In the first pass, we try to find a
8577 unique %lo. In the second pass, we permit multiple %hi
8578 relocs for a single %lo (this is a GNU extension). */
8579 seginfo
= seg_info (l
->seg
);
8580 for (pass
= 0; pass
< 2; pass
++)
8585 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8587 /* Check whether this is a %lo fixup which matches l->fixp. */
8588 if (f
->fx_r_type
== BFD_RELOC_LO16
8589 && f
->fx_addsy
== l
->fixp
->fx_addsy
8590 && f
->fx_offset
== l
->fixp
->fx_offset
8593 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8594 || prev
->fx_addsy
!= f
->fx_addsy
8595 || prev
->fx_offset
!= f
->fx_offset
))
8599 /* Move l->fixp before f. */
8600 for (pf
= &seginfo
->fix_root
;
8602 pf
= &(*pf
)->fx_next
)
8603 assert (*pf
!= NULL
);
8605 *pf
= l
->fixp
->fx_next
;
8607 l
->fixp
->fx_next
= f
;
8609 seginfo
->fix_root
= l
->fixp
;
8611 prev
->fx_next
= l
->fixp
;
8623 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8624 "Unmatched %%hi reloc");
8629 /* When generating embedded PIC code we need to use a special
8630 relocation to represent the difference of two symbols in the .text
8631 section (switch tables use a difference of this sort). See
8632 include/coff/mips.h for details. This macro checks whether this
8633 fixup requires the special reloc. */
8634 #define SWITCH_TABLE(fixp) \
8635 ((fixp)->fx_r_type == BFD_RELOC_32 \
8636 && (fixp)->fx_addsy != NULL \
8637 && (fixp)->fx_subsy != NULL \
8638 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8639 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8641 /* When generating embedded PIC code we must keep all PC relative
8642 relocations, in case the linker has to relax a call. We also need
8643 to keep relocations for switch table entries. */
8647 mips_force_relocation (fixp
)
8650 return (mips_pic
== EMBEDDED_PIC
8652 || SWITCH_TABLE (fixp
)
8653 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8654 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8657 /* Apply a fixup to the object file. */
8660 md_apply_fix (fixP
, valueP
)
8667 assert (fixP
->fx_size
== 4
8668 || fixP
->fx_r_type
== BFD_RELOC_16
8669 || fixP
->fx_r_type
== BFD_RELOC_64
);
8673 /* If we aren't adjusting this fixup to be against the section
8674 symbol, we need to adjust the value. */
8676 if (fixP
->fx_addsy
!= NULL
8677 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8678 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8680 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8681 if (value
!= 0 && ! fixP
->fx_pcrel
)
8683 /* In this case, the bfd_install_relocation routine will
8684 incorrectly add the symbol value back in. We just want
8685 the addend to appear in the object file. */
8686 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8691 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8693 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8696 switch (fixP
->fx_r_type
)
8698 case BFD_RELOC_MIPS_JMP
:
8699 case BFD_RELOC_HI16
:
8700 case BFD_RELOC_HI16_S
:
8701 case BFD_RELOC_MIPS_GPREL
:
8702 case BFD_RELOC_MIPS_LITERAL
:
8703 case BFD_RELOC_MIPS_CALL16
:
8704 case BFD_RELOC_MIPS_GOT16
:
8705 case BFD_RELOC_MIPS_GPREL32
:
8706 case BFD_RELOC_MIPS_GOT_HI16
:
8707 case BFD_RELOC_MIPS_GOT_LO16
:
8708 case BFD_RELOC_MIPS_CALL_HI16
:
8709 case BFD_RELOC_MIPS_CALL_LO16
:
8710 case BFD_RELOC_MIPS16_GPREL
:
8712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8713 "Invalid PC relative reloc");
8714 /* Nothing needed to do. The value comes from the reloc entry */
8717 case BFD_RELOC_MIPS16_JMP
:
8718 /* We currently always generate a reloc against a symbol, which
8719 means that we don't want an addend even if the symbol is
8721 fixP
->fx_addnumber
= 0;
8724 case BFD_RELOC_PCREL_HI16_S
:
8725 /* The addend for this is tricky if it is internal, so we just
8726 do everything here rather than in bfd_install_relocation. */
8727 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8729 /* For an external symbol adjust by the address to make it
8730 pcrel_offset. We use the address of the RELLO reloc
8731 which follows this one. */
8732 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8733 + fixP
->fx_next
->fx_where
);
8738 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8739 if (target_big_endian
)
8741 md_number_to_chars (buf
, value
, 2);
8744 case BFD_RELOC_PCREL_LO16
:
8745 /* The addend for this is tricky if it is internal, so we just
8746 do everything here rather than in bfd_install_relocation. */
8747 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8748 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8749 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8750 if (target_big_endian
)
8752 md_number_to_chars (buf
, value
, 2);
8756 /* This is handled like BFD_RELOC_32, but we output a sign
8757 extended value if we are only 32 bits. */
8759 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8761 if (8 <= sizeof (valueT
))
8762 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8769 w1
= w2
= fixP
->fx_where
;
8770 if (target_big_endian
)
8774 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8775 if ((value
& 0x80000000) != 0)
8779 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8785 /* If we are deleting this reloc entry, we must fill in the
8786 value now. This can happen if we have a .word which is not
8787 resolved when it appears but is later defined. We also need
8788 to fill in the value if this is an embedded PIC switch table
8791 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8792 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8797 /* If we are deleting this reloc entry, we must fill in the
8799 assert (fixP
->fx_size
== 2);
8801 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8805 case BFD_RELOC_LO16
:
8806 /* When handling an embedded PIC switch statement, we can wind
8807 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8810 if (value
< -0x8000 || value
> 0x7fff)
8811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8812 "relocation overflow");
8813 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8814 if (target_big_endian
)
8816 md_number_to_chars (buf
, value
, 2);
8820 case BFD_RELOC_16_PCREL_S2
:
8822 * We need to save the bits in the instruction since fixup_segment()
8823 * might be deleting the relocation entry (i.e., a branch within
8824 * the current segment).
8826 if ((value
& 0x3) != 0)
8827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8828 "Branch to odd address (%lx)", value
);
8831 /* update old instruction data */
8832 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8833 if (target_big_endian
)
8834 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8836 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8838 if (value
>= -0x8000 && value
< 0x8000)
8839 insn
|= value
& 0xffff;
8842 /* The branch offset is too large. If this is an
8843 unconditional branch, and we are not generating PIC code,
8844 we can convert it to an absolute jump instruction. */
8845 if (mips_pic
== NO_PIC
8847 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8848 && (fixP
->fx_frag
->fr_address
8849 < text_section
->vma
+ text_section
->_raw_size
)
8850 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8851 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8852 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8854 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8855 insn
= 0x0c000000; /* jal */
8857 insn
= 0x08000000; /* j */
8858 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8860 fixP
->fx_addsy
= section_symbol (text_section
);
8861 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8865 /* FIXME. It would be possible in principle to handle
8866 conditional branches which overflow. They could be
8867 transformed into a branch around a jump. This would
8868 require setting up variant frags for each different
8869 branch type. The native MIPS assembler attempts to
8870 handle these cases, but it appears to do it
8872 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8873 "Branch out of range");
8877 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8892 const struct mips_opcode
*p
;
8893 int treg
, sreg
, dreg
, shamt
;
8898 for (i
= 0; i
< NUMOPCODES
; ++i
)
8900 p
= &mips_opcodes
[i
];
8901 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8903 printf ("%08lx %s\t", oc
, p
->name
);
8904 treg
= (oc
>> 16) & 0x1f;
8905 sreg
= (oc
>> 21) & 0x1f;
8906 dreg
= (oc
>> 11) & 0x1f;
8907 shamt
= (oc
>> 6) & 0x1f;
8909 for (args
= p
->args
;; ++args
)
8920 printf ("%c", *args
);
8924 assert (treg
== sreg
);
8925 printf ("$%d,$%d", treg
, sreg
);
8930 printf ("$%d", dreg
);
8935 printf ("$%d", treg
);
8939 printf ("0x%x", treg
);
8944 printf ("$%d", sreg
);
8948 printf ("0x%08lx", oc
& 0x1ffffff);
8960 printf ("$%d", shamt
);
8971 printf ("%08lx UNDEFINED\n", oc
);
8982 name
= input_line_pointer
;
8983 c
= get_symbol_end ();
8984 p
= (symbolS
*) symbol_find_or_make (name
);
8985 *input_line_pointer
= c
;
8989 /* Align the current frag to a given power of two. The MIPS assembler
8990 also automatically adjusts any preceding label. */
8993 mips_align (to
, fill
, label
)
8998 mips_emit_delays (false);
8999 frag_align (to
, fill
, 0);
9000 record_alignment (now_seg
, to
);
9003 assert (S_GET_SEGMENT (label
) == now_seg
);
9004 label
->sy_frag
= frag_now
;
9005 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9009 /* Align to a given power of two. .align 0 turns off the automatic
9010 alignment used by the data creating pseudo-ops. */
9017 register long temp_fill
;
9018 long max_alignment
= 15;
9022 o Note that the assembler pulls down any immediately preceeding label
9023 to the aligned address.
9024 o It's not documented but auto alignment is reinstated by
9025 a .align pseudo instruction.
9026 o Note also that after auto alignment is turned off the mips assembler
9027 issues an error on attempt to assemble an improperly aligned data item.
9032 temp
= get_absolute_expression ();
9033 if (temp
> max_alignment
)
9034 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
9037 as_warn ("Alignment negative: 0 assumed.");
9040 if (*input_line_pointer
== ',')
9042 input_line_pointer
++;
9043 temp_fill
= get_absolute_expression ();
9050 mips_align (temp
, (int) temp_fill
,
9051 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9058 demand_empty_rest_of_line ();
9062 mips_flush_pending_output ()
9064 mips_emit_delays (false);
9065 mips_clear_insn_labels ();
9074 /* When generating embedded PIC code, we only use the .text, .lit8,
9075 .sdata and .sbss sections. We change the .data and .rdata
9076 pseudo-ops to use .sdata. */
9077 if (mips_pic
== EMBEDDED_PIC
9078 && (sec
== 'd' || sec
== 'r'))
9081 mips_emit_delays (false);
9091 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
9092 demand_empty_rest_of_line ();
9096 if (USE_GLOBAL_POINTER_OPT
)
9098 seg
= subseg_new (RDATA_SECTION_NAME
,
9099 (subsegT
) get_absolute_expression ());
9100 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9102 bfd_set_section_flags (stdoutput
, seg
,
9108 if (strcmp (TARGET_OS
, "elf") != 0)
9109 bfd_set_section_alignment (stdoutput
, seg
, 4);
9111 demand_empty_rest_of_line ();
9115 as_bad ("No read only data section in this object file format");
9116 demand_empty_rest_of_line ();
9122 if (USE_GLOBAL_POINTER_OPT
)
9124 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
9125 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9127 bfd_set_section_flags (stdoutput
, seg
,
9128 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
9130 if (strcmp (TARGET_OS
, "elf") != 0)
9131 bfd_set_section_alignment (stdoutput
, seg
, 4);
9133 demand_empty_rest_of_line ();
9138 as_bad ("Global pointers not supported; recompile -G 0");
9139 demand_empty_rest_of_line ();
9148 mips_enable_auto_align ()
9159 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9160 mips_emit_delays (false);
9161 if (log_size
> 0 && auto_align
)
9162 mips_align (log_size
, 0, label
);
9163 mips_clear_insn_labels ();
9164 cons (1 << log_size
);
9173 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9175 mips_emit_delays (false);
9179 mips_align (3, 0, label
);
9181 mips_align (2, 0, label
);
9183 mips_clear_insn_labels ();
9188 /* Handle .globl. We need to override it because on Irix 5 you are
9191 where foo is an undefined symbol, to mean that foo should be
9192 considered to be the address of a function. */
9203 name
= input_line_pointer
;
9204 c
= get_symbol_end ();
9205 symbolP
= symbol_find_or_make (name
);
9206 *input_line_pointer
= c
;
9209 /* On Irix 5, every global symbol that is not explicitly labelled as
9210 being a function is apparently labelled as being an object. */
9213 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
9218 secname
= input_line_pointer
;
9219 c
= get_symbol_end ();
9220 sec
= bfd_get_section_by_name (stdoutput
, secname
);
9222 as_bad ("%s: no such section", secname
);
9223 *input_line_pointer
= c
;
9225 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
9226 flag
= BSF_FUNCTION
;
9229 symbolP
->bsym
->flags
|= flag
;
9231 S_SET_EXTERNAL (symbolP
);
9232 demand_empty_rest_of_line ();
9242 opt
= input_line_pointer
;
9243 c
= get_symbol_end ();
9247 /* FIXME: What does this mean? */
9249 else if (strncmp (opt
, "pic", 3) == 0)
9257 mips_pic
= SVR4_PIC
;
9259 as_bad (".option pic%d not supported", i
);
9261 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
9263 if (g_switch_seen
&& g_switch_value
!= 0)
9264 as_warn ("-G may not be used with SVR4 PIC code");
9266 bfd_set_gp_size (stdoutput
, 0);
9270 as_warn ("Unrecognized option \"%s\"", opt
);
9272 *input_line_pointer
= c
;
9273 demand_empty_rest_of_line ();
9280 char *name
= input_line_pointer
, ch
;
9282 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
9283 input_line_pointer
++;
9284 ch
= *input_line_pointer
;
9285 *input_line_pointer
= '\0';
9287 if (strcmp (name
, "reorder") == 0)
9289 if (mips_noreorder
&& prev_nop_frag
!= NULL
)
9291 /* If we still have pending nops, we can discard them. The
9292 usual nop handling will insert any that are still
9294 prev_nop_frag
->fr_fix
-= prev_nop_frag_holds
* (mips16
? 2 : 4);
9295 prev_nop_frag
= NULL
;
9299 else if (strcmp (name
, "noreorder") == 0)
9301 mips_emit_delays (true);
9303 mips_any_noreorder
= 1;
9305 else if (strcmp (name
, "at") == 0)
9309 else if (strcmp (name
, "noat") == 0)
9313 else if (strcmp (name
, "macro") == 0)
9315 mips_warn_about_macros
= 0;
9317 else if (strcmp (name
, "nomacro") == 0)
9319 if (mips_noreorder
== 0)
9320 as_bad ("`noreorder' must be set before `nomacro'");
9321 mips_warn_about_macros
= 1;
9323 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
9327 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
9331 else if (strcmp (name
, "bopt") == 0)
9335 else if (strcmp (name
, "nobopt") == 0)
9339 else if (strcmp (name
, "mips16") == 0
9340 || strcmp (name
, "MIPS-16") == 0)
9342 else if (strcmp (name
, "nomips16") == 0
9343 || strcmp (name
, "noMIPS-16") == 0)
9345 else if (strncmp (name
, "mips", 4) == 0)
9349 /* Permit the user to change the ISA on the fly. Needless to
9350 say, misuse can cause serious problems. */
9351 isa
= atoi (name
+ 4);
9353 mips_isa
= file_mips_isa
;
9354 else if (isa
< 1 || isa
> 4)
9355 as_bad ("unknown ISA level");
9359 else if (strcmp (name
, "autoextend") == 0)
9360 mips16_autoextend
= 1;
9361 else if (strcmp (name
, "noautoextend") == 0)
9362 mips16_autoextend
= 0;
9365 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
9367 *input_line_pointer
= ch
;
9368 demand_empty_rest_of_line ();
9371 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9372 .option pic2. It means to generate SVR4 PIC calls. */
9378 mips_pic
= SVR4_PIC
;
9379 if (USE_GLOBAL_POINTER_OPT
)
9381 if (g_switch_seen
&& g_switch_value
!= 0)
9382 as_warn ("-G may not be used with SVR4 PIC code");
9385 bfd_set_gp_size (stdoutput
, 0);
9386 demand_empty_rest_of_line ();
9389 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9390 PIC code. It sets the $gp register for the function based on the
9391 function address, which is in the register named in the argument.
9392 This uses a relocation against _gp_disp, which is handled specially
9393 by the linker. The result is:
9394 lui $gp,%hi(_gp_disp)
9395 addiu $gp,$gp,%lo(_gp_disp)
9396 addu $gp,$gp,.cpload argument
9397 The .cpload argument is normally $25 == $t9. */
9406 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9407 if (mips_pic
!= SVR4_PIC
)
9413 /* .cpload should be a in .set noreorder section. */
9414 if (mips_noreorder
== 0)
9415 as_warn (".cpload not in noreorder section");
9418 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9419 ex
.X_op_symbol
= NULL
;
9420 ex
.X_add_number
= 0;
9422 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9423 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9425 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9426 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9427 (int) BFD_RELOC_LO16
);
9429 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9430 GP
, GP
, tc_get_register (0));
9432 demand_empty_rest_of_line ();
9435 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9436 offset from $sp. The offset is remembered, and after making a PIC
9437 call $gp is restored from that location. */
9440 s_cprestore (ignore
)
9446 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9447 if (mips_pic
!= SVR4_PIC
)
9453 mips_cprestore_offset
= get_absolute_expression ();
9455 ex
.X_op
= O_constant
;
9456 ex
.X_add_symbol
= NULL
;
9457 ex
.X_op_symbol
= NULL
;
9458 ex
.X_add_number
= mips_cprestore_offset
;
9460 macro_build ((char *) NULL
, &icnt
, &ex
,
9461 mips_isa
< 3 ? "sw" : "sd",
9462 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9464 demand_empty_rest_of_line ();
9467 /* Handle the .gpword pseudo-op. This is used when generating PIC
9468 code. It generates a 32 bit GP relative reloc. */
9478 /* When not generating PIC code, this is treated as .word. */
9479 if (mips_pic
!= SVR4_PIC
)
9485 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9486 mips_emit_delays (true);
9488 mips_align (2, 0, label
);
9489 mips_clear_insn_labels ();
9493 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9495 as_bad ("Unsupported use of .gpword");
9496 ignore_rest_of_line ();
9500 md_number_to_chars (p
, (valueT
) 0, 4);
9501 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9502 BFD_RELOC_MIPS_GPREL32
);
9504 demand_empty_rest_of_line ();
9507 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9508 tables in SVR4 PIC code. */
9517 /* This is ignored when not generating SVR4 PIC code. */
9518 if (mips_pic
!= SVR4_PIC
)
9524 /* Add $gp to the register named as an argument. */
9525 reg
= tc_get_register (0);
9526 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9527 mips_isa
< 3 ? "addu" : "daddu",
9528 "d,v,t", reg
, reg
, GP
);
9530 demand_empty_rest_of_line ();
9533 /* Handle the .insn pseudo-op. This marks instruction labels in
9534 mips16 mode. This permits the linker to handle them specially,
9535 such as generating jalx instructions when needed. We also make
9536 them odd for the duration of the assembly, in order to generate the
9537 right sort of code. We will make them even in the adjust_symtab
9538 routine, while leaving them marked. This is convenient for the
9539 debugger and the disassembler. The linker knows to make them odd
9548 struct insn_label_list
*l
;
9550 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
9553 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9554 S_SET_OTHER (l
->label
, STO_MIPS16
);
9556 ++l
->label
->sy_value
.X_add_number
;
9559 mips_clear_insn_labels ();
9562 demand_empty_rest_of_line ();
9565 /* Parse a register string into a number. Called from the ECOFF code
9566 to parse .frame. The argument is non-zero if this is the frame
9567 register, so that we can record it in mips_frame_reg. */
9570 tc_get_register (frame
)
9576 if (*input_line_pointer
++ != '$')
9578 as_warn ("expected `$'");
9581 else if (isdigit ((unsigned char) *input_line_pointer
))
9583 reg
= get_absolute_expression ();
9584 if (reg
< 0 || reg
>= 32)
9586 as_warn ("Bad register number");
9592 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9594 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9596 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9598 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9602 as_warn ("Unrecognized register name");
9605 input_line_pointer
+= 2;
9608 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9613 md_section_align (seg
, addr
)
9617 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9620 /* We don't need to align ELF sections to the full alignment.
9621 However, Irix 5 may prefer that we align them at least to a 16
9622 byte boundary. We don't bother to align the sections if we are
9623 targeted for an embedded system. */
9624 if (strcmp (TARGET_OS
, "elf") == 0)
9630 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9633 /* Utility routine, called from above as well. If called while the
9634 input file is still being read, it's only an approximation. (For
9635 example, a symbol may later become defined which appeared to be
9636 undefined earlier.) */
9639 nopic_need_relax (sym
)
9645 if (USE_GLOBAL_POINTER_OPT
)
9647 const char *symname
;
9650 /* Find out whether this symbol can be referenced off the GP
9651 register. It can be if it is smaller than the -G size or if
9652 it is in the .sdata or .sbss section. Certain symbols can
9653 not be referenced off the GP, although it appears as though
9655 symname
= S_GET_NAME (sym
);
9656 if (symname
!= (const char *) NULL
9657 && (strcmp (symname
, "eprol") == 0
9658 || strcmp (symname
, "etext") == 0
9659 || strcmp (symname
, "_gp") == 0
9660 || strcmp (symname
, "edata") == 0
9661 || strcmp (symname
, "_fbss") == 0
9662 || strcmp (symname
, "_fdata") == 0
9663 || strcmp (symname
, "_ftext") == 0
9664 || strcmp (symname
, "end") == 0
9665 || strcmp (symname
, "_gp_disp") == 0))
9667 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
9669 #ifndef NO_ECOFF_DEBUGGING
9670 || (sym
->ecoff_extern_size
!= 0
9671 && sym
->ecoff_extern_size
<= g_switch_value
)
9673 || (S_GET_VALUE (sym
) != 0
9674 && S_GET_VALUE (sym
) <= g_switch_value
)))
9678 const char *segname
;
9680 segname
= segment_name (S_GET_SEGMENT (sym
));
9681 assert (strcmp (segname
, ".lit8") != 0
9682 && strcmp (segname
, ".lit4") != 0);
9683 change
= (strcmp (segname
, ".sdata") != 0
9684 && strcmp (segname
, ".sbss") != 0);
9689 /* We are not optimizing for the GP register. */
9693 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9694 extended opcode. SEC is the section the frag is in. */
9697 mips16_extended_frag (fragp
, sec
, stretch
)
9703 register const struct mips16_immed_operand
*op
;
9705 int mintiny
, maxtiny
;
9708 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9710 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9713 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9714 op
= mips16_immed_operands
;
9715 while (op
->type
!= type
)
9718 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9723 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9726 maxtiny
= 1 << op
->nbits
;
9731 maxtiny
= (1 << op
->nbits
) - 1;
9736 mintiny
= - (1 << (op
->nbits
- 1));
9737 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9740 /* We can't call S_GET_VALUE here, because we don't want to lock in
9741 a particular frag address. */
9742 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9744 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9745 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9746 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9748 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9749 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9752 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9753 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9754 + fragp
->fr_symbol
->sy_value
.X_add_number
9755 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9756 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9765 /* We won't have the section when we are called from
9766 mips_relax_frag. However, we will always have been called
9767 from md_estimate_size_before_relax first. If this is a
9768 branch to a different section, we mark it as such. If SEC is
9769 NULL, and the frag is not marked, then it must be a branch to
9770 the same section. */
9773 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9781 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9783 /* FIXME: We should support this, and let the linker
9784 catch branches and loads that are out of range. */
9785 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9786 "unsupported PC relative reference to different section");
9792 /* In this case, we know for sure that the symbol fragment is in
9793 the same section. If the fr_address of the symbol fragment
9794 is greater then the address of this fragment we want to add
9795 in STRETCH in order to get a better estimate of the address.
9796 This particularly matters because of the shift bits. */
9798 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9802 /* Adjust stretch for any alignment frag. Note that if have
9803 been expanding the earlier code, the symbol may be
9804 defined in what appears to be an earlier frag. FIXME:
9805 This doesn't handle the fr_subtype field, which specifies
9806 a maximum number of bytes to skip when doing an
9809 f
!= NULL
&& f
!= fragp
->fr_symbol
->sy_frag
;
9812 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9815 stretch
= - ((- stretch
)
9816 & ~ ((1 << (int) f
->fr_offset
) - 1));
9818 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9827 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9829 /* The base address rules are complicated. The base address of
9830 a branch is the following instruction. The base address of a
9831 PC relative load or add is the instruction itself, but if it
9832 is in a delay slot (in which case it can not be extended) use
9833 the address of the instruction whose delay slot it is in. */
9834 if (type
== 'p' || type
== 'q')
9838 /* If we are currently assuming that this frag should be
9839 extended, then, the current address is two bytes
9841 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9844 /* Ignore the low bit in the target, since it will be set
9845 for a text label. */
9849 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9851 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9854 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9856 /* Branch offsets have an implicit 0 in the lowest bit. */
9857 if (type
== 'p' || type
== 'q')
9860 /* If any of the shifted bits are set, we must use an extended
9861 opcode. If the address depends on the size of this
9862 instruction, this can lead to a loop, so we arrange to always
9863 use an extended opcode. We only check this when we are in
9864 the main relaxation loop, when SEC is NULL. */
9865 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9868 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9872 /* If we are about to mark a frag as extended because the value
9873 is precisely maxtiny + 1, then there is a chance of an
9874 infinite loop as in the following code:
9879 In this case when the la is extended, foo is 0x3fc bytes
9880 away, so the la can be shrunk, but then foo is 0x400 away, so
9881 the la must be extended. To avoid this loop, we mark the
9882 frag as extended if it was small, and is about to become
9883 extended with a value of maxtiny + 1. */
9884 if (val
== ((maxtiny
+ 1) << op
->shift
)
9885 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9889 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9893 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9894 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9896 if ((val
& ((1 << op
->shift
) - 1)) != 0
9897 || val
< (mintiny
<< op
->shift
)
9898 || val
> (maxtiny
<< op
->shift
))
9904 /* Estimate the size of a frag before relaxing. Unless this is the
9905 mips16, we are not really relaxing here, and the final size is
9906 encoded in the subtype information. For the mips16, we have to
9907 decide whether we are using an extended opcode or not. */
9911 md_estimate_size_before_relax (fragp
, segtype
)
9917 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9919 if (mips16_extended_frag (fragp
, segtype
, 0))
9921 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9926 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9931 if (mips_pic
== NO_PIC
)
9933 change
= nopic_need_relax (fragp
->fr_symbol
);
9935 else if (mips_pic
== SVR4_PIC
)
9940 sym
= fragp
->fr_symbol
;
9942 /* Handle the case of a symbol equated to another symbol. */
9943 while (sym
->sy_value
.X_op
== O_symbol
9944 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
9948 /* It's possible to get a loop here in a badly written
9950 n
= sym
->sy_value
.X_add_symbol
;
9956 symsec
= S_GET_SEGMENT (sym
);
9958 /* This must duplicate the test in adjust_reloc_syms. */
9959 change
= (symsec
!= &bfd_und_section
9960 && symsec
!= &bfd_abs_section
9961 && ! bfd_is_com_section (symsec
));
9968 /* Record the offset to the first reloc in the fr_opcode field.
9969 This lets md_convert_frag and tc_gen_reloc know that the code
9970 must be expanded. */
9971 fragp
->fr_opcode
= (fragp
->fr_literal
9973 - RELAX_OLD (fragp
->fr_subtype
)
9974 + RELAX_RELOC1 (fragp
->fr_subtype
));
9975 /* FIXME: This really needs as_warn_where. */
9976 if (RELAX_WARN (fragp
->fr_subtype
))
9977 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9983 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9986 /* This is called to see whether a reloc against a defined symbol
9987 should be converted into a reloc against a section. Don't adjust
9988 MIPS16 jump relocations, so we don't have to worry about the format
9989 of the offset in the .o file. Don't adjust relocations against
9990 mips16 symbols, so that the linker can find them if it needs to set
9994 mips_fix_adjustable (fixp
)
9997 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9999 if (fixp
->fx_addsy
== NULL
)
10002 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
10003 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
10004 && fixp
->fx_subsy
== NULL
)
10010 /* Translate internal representation of relocation info to BFD target
10014 tc_gen_reloc (section
, fixp
)
10018 static arelent
*retval
[4];
10020 bfd_reloc_code_real_type code
;
10022 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
10025 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10026 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10028 if (mips_pic
== EMBEDDED_PIC
10029 && SWITCH_TABLE (fixp
))
10031 /* For a switch table entry we use a special reloc. The addend
10032 is actually the difference between the reloc address and the
10034 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10035 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
10036 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
10037 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
10039 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
10041 /* We use a special addend for an internal RELLO reloc. */
10042 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10043 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
10045 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
10047 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
10049 assert (fixp
->fx_next
!= NULL
10050 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
10051 /* We use a special addend for an internal RELHI reloc. The
10052 reloc is relative to the RELLO; adjust the addend
10054 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
10055 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
10056 + fixp
->fx_next
->fx_where
10057 - S_GET_VALUE (fixp
->fx_subsy
));
10059 reloc
->addend
= (fixp
->fx_addnumber
10060 + fixp
->fx_next
->fx_frag
->fr_address
10061 + fixp
->fx_next
->fx_where
);
10063 else if (fixp
->fx_pcrel
== 0)
10064 reloc
->addend
= fixp
->fx_addnumber
;
10067 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
10068 /* A gruesome hack which is a result of the gruesome gas reloc
10070 reloc
->addend
= reloc
->address
;
10072 reloc
->addend
= -reloc
->address
;
10075 /* If this is a variant frag, we may need to adjust the existing
10076 reloc and generate a new one. */
10077 if (fixp
->fx_frag
->fr_opcode
!= NULL
10078 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10079 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10080 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
10081 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10082 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
10083 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10084 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
10088 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
10090 /* If this is not the last reloc in this frag, then we have two
10091 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
10092 CALL_HI16/CALL_LO16, both of which are being replaced. Let
10093 the second one handle all of them. */
10094 if (fixp
->fx_next
!= NULL
10095 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
10097 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
10098 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
10099 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
10100 && (fixp
->fx_next
->fx_r_type
10101 == BFD_RELOC_MIPS_GOT_LO16
))
10102 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
10103 && (fixp
->fx_next
->fx_r_type
10104 == BFD_RELOC_MIPS_CALL_LO16
)));
10109 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
10110 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
10111 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
10113 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
10114 reloc2
->address
= (reloc
->address
10115 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
10116 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
10117 reloc2
->addend
= fixp
->fx_addnumber
;
10118 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
10119 assert (reloc2
->howto
!= NULL
);
10121 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
10125 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
10128 reloc3
->address
+= 4;
10131 if (mips_pic
== NO_PIC
)
10133 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
10134 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
10136 else if (mips_pic
== SVR4_PIC
)
10138 switch (fixp
->fx_r_type
)
10142 case BFD_RELOC_MIPS_GOT16
:
10144 case BFD_RELOC_MIPS_CALL16
:
10145 case BFD_RELOC_MIPS_GOT_LO16
:
10146 case BFD_RELOC_MIPS_CALL_LO16
:
10147 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
10155 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
10156 fixup_segment converted a non-PC relative reloc into a PC
10157 relative reloc. In such a case, we need to convert the reloc
10159 code
= fixp
->fx_r_type
;
10160 if (fixp
->fx_pcrel
)
10165 code
= BFD_RELOC_8_PCREL
;
10168 code
= BFD_RELOC_16_PCREL
;
10171 code
= BFD_RELOC_32_PCREL
;
10174 code
= BFD_RELOC_64_PCREL
;
10176 case BFD_RELOC_8_PCREL
:
10177 case BFD_RELOC_16_PCREL
:
10178 case BFD_RELOC_32_PCREL
:
10179 case BFD_RELOC_64_PCREL
:
10180 case BFD_RELOC_16_PCREL_S2
:
10181 case BFD_RELOC_PCREL_HI16_S
:
10182 case BFD_RELOC_PCREL_LO16
:
10185 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10186 "Cannot make %s relocation PC relative",
10187 bfd_get_reloc_code_name (code
));
10191 /* To support a PC relative reloc when generating embedded PIC code
10192 for ECOFF, we use a Cygnus extension. We check for that here to
10193 make sure that we don't let such a reloc escape normally. */
10194 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
10195 && code
== BFD_RELOC_16_PCREL_S2
10196 && mips_pic
!= EMBEDDED_PIC
)
10197 reloc
->howto
= NULL
;
10199 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
10201 if (reloc
->howto
== NULL
)
10203 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
10204 "Can not represent %s relocation in this object file format",
10205 bfd_get_reloc_code_name (code
));
10212 /* Relax a machine dependent frag. This returns the amount by which
10213 the current size of the frag should change. */
10216 mips_relax_frag (fragp
, stretch
)
10220 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
10223 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
10225 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10227 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
10232 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10234 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
10241 /* Convert a machine dependent frag. */
10244 md_convert_frag (abfd
, asec
, fragp
)
10252 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10255 register const struct mips16_immed_operand
*op
;
10256 boolean small
, ext
;
10259 unsigned long insn
;
10260 boolean use_extend
;
10261 unsigned short extend
;
10263 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10264 op
= mips16_immed_operands
;
10265 while (op
->type
!= type
)
10268 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10279 resolve_symbol_value (fragp
->fr_symbol
);
10280 val
= S_GET_VALUE (fragp
->fr_symbol
);
10285 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10287 /* The rules for the base address of a PC relative reloc are
10288 complicated; see mips16_extended_frag. */
10289 if (type
== 'p' || type
== 'q')
10294 /* Ignore the low bit in the target, since it will be
10295 set for a text label. */
10296 if ((val
& 1) != 0)
10299 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10301 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10304 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
10307 /* Make sure the section winds up with the alignment we have
10310 record_alignment (asec
, op
->shift
);
10314 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
10315 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
10316 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
10317 "extended instruction in delay slot");
10319 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
10321 if (target_big_endian
)
10322 insn
= bfd_getb16 (buf
);
10324 insn
= bfd_getl16 (buf
);
10326 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
10327 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
10328 small
, ext
, &insn
, &use_extend
, &extend
);
10332 md_number_to_chars (buf
, 0xf000 | extend
, 2);
10333 fragp
->fr_fix
+= 2;
10337 md_number_to_chars (buf
, insn
, 2);
10338 fragp
->fr_fix
+= 2;
10343 if (fragp
->fr_opcode
== NULL
)
10346 old
= RELAX_OLD (fragp
->fr_subtype
);
10347 new = RELAX_NEW (fragp
->fr_subtype
);
10348 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
10351 memcpy (fixptr
- old
, fixptr
, new);
10353 fragp
->fr_fix
+= new - old
;
10359 /* This function is called after the relocs have been generated.
10360 We've been storing mips16 text labels as odd. Here we convert them
10361 back to even for the convenience of the debugger. */
10364 mips_frob_file_after_relocs ()
10367 unsigned int count
, i
;
10369 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10372 syms
= bfd_get_outsymbols (stdoutput
);
10373 count
= bfd_get_symcount (stdoutput
);
10374 for (i
= 0; i
< count
; i
++, syms
++)
10376 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
10377 && ((*syms
)->value
& 1) != 0)
10379 (*syms
)->value
&= ~1;
10380 /* If the symbol has an odd size, it was probably computed
10381 incorrectly, so adjust that as well. */
10382 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
10383 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
10390 /* This function is called whenever a label is defined. It is used
10391 when handling branch delays; if a branch has a label, we assume we
10392 can not move it. */
10395 mips_define_label (sym
)
10398 struct insn_label_list
*l
;
10400 if (free_insn_labels
== NULL
)
10401 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
10404 l
= free_insn_labels
;
10405 free_insn_labels
= l
->next
;
10409 l
->next
= insn_labels
;
10413 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10415 /* Some special processing for a MIPS ELF file. */
10418 mips_elf_final_processing ()
10420 /* Write out the register information. */
10425 s
.ri_gprmask
= mips_gprmask
;
10426 s
.ri_cprmask
[0] = mips_cprmask
[0];
10427 s
.ri_cprmask
[1] = mips_cprmask
[1];
10428 s
.ri_cprmask
[2] = mips_cprmask
[2];
10429 s
.ri_cprmask
[3] = mips_cprmask
[3];
10430 /* The gp_value field is set by the MIPS ELF backend. */
10432 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10433 ((Elf32_External_RegInfo
*)
10434 mips_regmask_frag
));
10438 Elf64_Internal_RegInfo s
;
10440 s
.ri_gprmask
= mips_gprmask
;
10442 s
.ri_cprmask
[0] = mips_cprmask
[0];
10443 s
.ri_cprmask
[1] = mips_cprmask
[1];
10444 s
.ri_cprmask
[2] = mips_cprmask
[2];
10445 s
.ri_cprmask
[3] = mips_cprmask
[3];
10446 /* The gp_value field is set by the MIPS ELF backend. */
10448 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10449 ((Elf64_External_RegInfo
*)
10450 mips_regmask_frag
));
10453 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10454 sort of BFD interface for this. */
10455 if (mips_any_noreorder
)
10456 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10457 if (mips_pic
!= NO_PIC
)
10458 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10461 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10463 /* These functions should really be defined by the object file format,
10464 since they are related to debugging information. However, this
10465 code has to work for the a.out format, which does not define them,
10466 so we provide simple versions here. These don't actually generate
10467 any debugging information, but they do simple checking and someday
10468 somebody may make them useful. */
10472 struct loc
*loc_next
;
10473 unsigned long loc_fileno
;
10474 unsigned long loc_lineno
;
10475 unsigned long loc_offset
;
10476 unsigned short loc_delta
;
10477 unsigned short loc_count
;
10484 typedef struct proc
10486 struct proc
*proc_next
;
10487 struct symbol
*proc_isym
;
10488 struct symbol
*proc_end
;
10489 unsigned long proc_reg_mask
;
10490 unsigned long proc_reg_offset
;
10491 unsigned long proc_fpreg_mask
;
10492 unsigned long proc_fpreg_offset
;
10493 unsigned long proc_frameoffset
;
10494 unsigned long proc_framereg
;
10495 unsigned long proc_pcreg
;
10497 struct file
*proc_file
;
10502 typedef struct file
10504 struct file
*file_next
;
10505 unsigned long file_fileno
;
10506 struct symbol
*file_symbol
;
10507 struct symbol
*file_end
;
10508 struct proc
*file_proc
;
10513 static struct obstack proc_frags
;
10514 static procS
*proc_lastP
;
10515 static procS
*proc_rootP
;
10516 static int numprocs
;
10521 obstack_begin (&proc_frags
, 0x2000);
10527 /* check for premature end, nesting errors, etc */
10528 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10529 as_warn ("missing `.end' at end of assembly");
10538 if (*input_line_pointer
== '-')
10540 ++input_line_pointer
;
10543 if (!isdigit (*input_line_pointer
))
10544 as_bad ("Expected simple number.");
10545 if (input_line_pointer
[0] == '0')
10547 if (input_line_pointer
[1] == 'x')
10549 input_line_pointer
+= 2;
10550 while (isxdigit (*input_line_pointer
))
10553 val
|= hex_value (*input_line_pointer
++);
10555 return negative
? -val
: val
;
10559 ++input_line_pointer
;
10560 while (isdigit (*input_line_pointer
))
10563 val
|= *input_line_pointer
++ - '0';
10565 return negative
? -val
: val
;
10568 if (!isdigit (*input_line_pointer
))
10570 printf (" *input_line_pointer == '%c' 0x%02x\n",
10571 *input_line_pointer
, *input_line_pointer
);
10572 as_warn ("Invalid number");
10575 while (isdigit (*input_line_pointer
))
10578 val
+= *input_line_pointer
++ - '0';
10580 return negative
? -val
: val
;
10583 /* The .file directive; just like the usual .file directive, but there
10584 is an initial number which is the ECOFF file index. */
10592 line
= get_number ();
10597 /* The .end directive. */
10605 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10608 demand_empty_rest_of_line ();
10612 if (now_seg
!= text_section
)
10613 as_warn (".end not in text section");
10616 as_warn (".end and no .ent seen yet.");
10622 assert (S_GET_NAME (p
));
10623 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10624 as_warn (".end symbol does not match .ent symbol.");
10627 proc_lastP
->proc_end
= (symbolS
*) 1;
10630 /* The .aent and .ent directives. */
10640 symbolP
= get_symbol ();
10641 if (*input_line_pointer
== ',')
10642 input_line_pointer
++;
10643 SKIP_WHITESPACE ();
10644 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10645 number
= get_number ();
10646 if (now_seg
!= text_section
)
10647 as_warn (".ent or .aent not in text section.");
10649 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10650 as_warn ("missing `.end'");
10654 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10655 procP
->proc_isym
= symbolP
;
10656 procP
->proc_reg_mask
= 0;
10657 procP
->proc_reg_offset
= 0;
10658 procP
->proc_fpreg_mask
= 0;
10659 procP
->proc_fpreg_offset
= 0;
10660 procP
->proc_frameoffset
= 0;
10661 procP
->proc_framereg
= 0;
10662 procP
->proc_pcreg
= 0;
10663 procP
->proc_end
= NULL
;
10664 procP
->proc_next
= NULL
;
10666 proc_lastP
->proc_next
= procP
;
10668 proc_rootP
= procP
;
10669 proc_lastP
= procP
;
10672 demand_empty_rest_of_line ();
10675 /* The .frame directive. */
10688 frame_reg
= tc_get_register (1);
10689 if (*input_line_pointer
== ',')
10690 input_line_pointer
++;
10691 frame_off
= get_absolute_expression ();
10692 if (*input_line_pointer
== ',')
10693 input_line_pointer
++;
10694 pcreg
= tc_get_register (0);
10696 /* bob third eye */
10697 assert (proc_rootP
);
10698 proc_rootP
->proc_framereg
= frame_reg
;
10699 proc_rootP
->proc_frameoffset
= frame_off
;
10700 proc_rootP
->proc_pcreg
= pcreg
;
10701 /* bob macho .frame */
10703 /* We don't have to write out a frame stab for unoptimized code. */
10704 if (!(frame_reg
== FP
&& frame_off
== 0))
10707 as_warn ("No .ent for .frame to use.");
10708 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10709 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10710 S_SET_TYPE (symP
, N_RMASK
);
10711 S_SET_OTHER (symP
, 0);
10712 S_SET_DESC (symP
, 0);
10713 symP
->sy_forward
= proc_lastP
->proc_isym
;
10714 /* bob perhaps I should have used pseudo set */
10716 demand_empty_rest_of_line ();
10720 /* The .fmask and .mask directives. */
10727 char str
[100], *strP
;
10733 mask
= get_number ();
10734 if (*input_line_pointer
== ',')
10735 input_line_pointer
++;
10736 off
= get_absolute_expression ();
10738 /* bob only for coff */
10739 assert (proc_rootP
);
10740 if (reg_type
== 'F')
10742 proc_rootP
->proc_fpreg_mask
= mask
;
10743 proc_rootP
->proc_fpreg_offset
= off
;
10747 proc_rootP
->proc_reg_mask
= mask
;
10748 proc_rootP
->proc_reg_offset
= off
;
10751 /* bob macho .mask + .fmask */
10753 /* We don't have to write out a mask stab if no saved regs. */
10757 as_warn ("No .ent for .mask to use.");
10759 for (i
= 0; i
< 32; i
++)
10763 sprintf (strP
, "%c%d,", reg_type
, i
);
10764 strP
+= strlen (strP
);
10768 sprintf (strP
, ";%d,", off
);
10769 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10770 S_SET_TYPE (symP
, N_RMASK
);
10771 S_SET_OTHER (symP
, 0);
10772 S_SET_DESC (symP
, 0);
10773 symP
->sy_forward
= proc_lastP
->proc_isym
;
10774 /* bob perhaps I should have used pseudo set */
10779 /* The .loc directive. */
10790 assert (now_seg
== text_section
);
10792 lineno
= get_number ();
10793 addroff
= frag_now_fix ();
10795 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10796 S_SET_TYPE (symbolP
, N_SLINE
);
10797 S_SET_OTHER (symbolP
, 0);
10798 S_SET_DESC (symbolP
, lineno
);
10799 symbolP
->sy_segment
= now_seg
;