1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1995, 1996 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
28 #include "libiberty.h"
39 #include "opcode/mips.h"
42 /* Clean up namespace so we can include obj-elf.h too. */
43 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
44 #undef OBJ_PROCESS_STAB
50 #undef TARGET_SYMBOL_FIELDS
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 static char *mips_regmask_frag
;
76 #define PIC_CALL_REG 25
84 extern int target_big_endian
;
86 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
87 32 bit ABI. This has no meaning for ECOFF. */
90 /* The default target format to use. */
94 switch (OUTPUT_FLAVOR
)
96 case bfd_target_aout_flavour
:
97 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
98 case bfd_target_ecoff_flavour
:
99 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
100 case bfd_target_elf_flavour
:
101 return (target_big_endian
102 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
103 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
109 /* The name of the readonly data section. */
110 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
112 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
114 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
118 /* These variables are filled in with the masks of registers used.
119 The object format code reads them and puts them in the appropriate
121 unsigned long mips_gprmask
;
122 unsigned long mips_cprmask
[4];
124 /* MIPS ISA (Instruction Set Architecture) level (may be changed
125 temporarily using .set mipsN). */
126 static int mips_isa
= -1;
128 /* MIPS ISA we are using for this output file. */
129 static int file_mips_isa
;
131 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
132 static int mips_cpu
= -1;
134 /* Whether the 4650 instructions (mad/madu) are permitted. */
135 static int mips_4650
= -1;
137 /* Whether the 4010 instructions are permitted. */
138 static int mips_4010
= -1;
140 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
141 static int mips_4100
= -1;
143 /* Whether the processor uses hardware interlocks, and thus does not
144 require nops to be inserted. */
145 static int interlocks
= -1;
147 /* As with "interlocks" this is used by hardware that has FP
148 (co-processor) interlocks. */
149 static int cop_interlocks
= -1;
151 /* MIPS PIC level. */
155 /* Do not generate PIC code. */
158 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
159 not sure what it is supposed to do. */
162 /* Generate PIC code as in the SVR4 MIPS ABI. */
165 /* Generate PIC code without using a global offset table: the data
166 segment has a maximum size of 64K, all data references are off
167 the $gp register, and all text references are PC relative. This
168 is used on some embedded systems. */
172 static enum mips_pic_level mips_pic
;
174 /* 1 if we should generate 32 bit offsets from the GP register in
175 SVR4_PIC mode. Currently has no meaning in other modes. */
176 static int mips_big_got
;
178 /* 1 if trap instructions should used for overflow rather than break
180 static int mips_trap
;
182 static int mips_warn_about_macros
;
183 static int mips_noreorder
;
184 static int mips_any_noreorder
;
185 static int mips_nomove
;
186 static int mips_noat
;
187 static int mips_nobopt
;
189 /* The size of the small data section. */
190 static int g_switch_value
= 8;
191 /* Whether the -G option was used. */
192 static int g_switch_seen
= 0;
197 /* If we can determine in advance that GP optimization won't be
198 possible, we can skip the relaxation stuff that tries to produce
199 GP-relative references. This makes delay slot optimization work
202 This function can only provide a guess, but it seems to work for
203 gcc output. If it guesses wrong, the only loss should be in
204 efficiency; it shouldn't introduce any bugs.
206 I don't know if a fix is needed for the SVR4_PIC mode. I've only
207 fixed it for the non-PIC mode. KR 95/04/07 */
208 static int nopic_need_relax
PARAMS ((symbolS
*));
210 /* handle of the OPCODE hash table */
211 static struct hash_control
*op_hash
= NULL
;
213 /* This array holds the chars that always start a comment. If the
214 pre-processor is disabled, these aren't very useful */
215 const char comment_chars
[] = "#";
217 /* This array holds the chars that only start a comment at the beginning of
218 a line. If the line seems to have the form '# 123 filename'
219 .line and .file directives will appear in the pre-processed output */
220 /* Note that input_file.c hand checks for '#' at the beginning of the
221 first line of the input file. This is because the compiler outputs
222 #NO_APP at the beginning of its output. */
223 /* Also note that C style comments are always supported. */
224 const char line_comment_chars
[] = "#";
226 /* This array holds machine specific line separator characters. */
227 const char line_separator_chars
[] = "";
229 /* Chars that can be used to separate mant from exp in floating point nums */
230 const char EXP_CHARS
[] = "eE";
232 /* Chars that mean this number is a floating point constant */
235 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
237 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
238 changed in read.c . Ideally it shouldn't have to know about it at all,
239 but nothing is ideal around here.
242 static char *insn_error
;
244 static int byte_order
;
246 static int auto_align
= 1;
248 /* Symbol labelling the current insn. */
249 static symbolS
*insn_label
;
251 /* When outputting SVR4 PIC code, the assembler needs to know the
252 offset in the stack frame from which to restore the $gp register.
253 This is set by the .cprestore pseudo-op, and saved in this
255 static offsetT mips_cprestore_offset
= -1;
257 /* This is the register which holds the stack frame, as set by the
258 .frame pseudo-op. This is needed to implement .cprestore. */
259 static int mips_frame_reg
= SP
;
261 /* To output NOP instructions correctly, we need to keep information
262 about the previous two instructions. */
264 /* Whether we are optimizing. The default value of 2 means to remove
265 unneeded NOPs and swap branch instructions when possible. A value
266 of 1 means to not swap branches. A value of 0 means to always
268 static int mips_optimize
= 2;
270 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
271 equivalent to seeing no -g option at all. */
272 static int mips_debug
= 0;
274 /* The previous instruction. */
275 static struct mips_cl_insn prev_insn
;
277 /* The instruction before prev_insn. */
278 static struct mips_cl_insn prev_prev_insn
;
280 /* If we don't want information for prev_insn or prev_prev_insn, we
281 point the insn_mo field at this dummy integer. */
282 static const struct mips_opcode dummy_opcode
= { 0 };
284 /* Non-zero if prev_insn is valid. */
285 static int prev_insn_valid
;
287 /* The frag for the previous instruction. */
288 static struct frag
*prev_insn_frag
;
290 /* The offset into prev_insn_frag for the previous instruction. */
291 static long prev_insn_where
;
293 /* The reloc for the previous instruction, if any. */
294 static fixS
*prev_insn_fixp
;
296 /* Non-zero if the previous instruction was in a delay slot. */
297 static int prev_insn_is_delay_slot
;
299 /* Non-zero if the previous instruction was in a .set noreorder. */
300 static int prev_insn_unreordered
;
302 /* Non-zero if the previous previous instruction was in a .set
304 static int prev_prev_insn_unreordered
;
306 /* For ECOFF and ELF, relocations against symbols are done in two
307 parts, with a HI relocation and a LO relocation. Each relocation
308 has only 16 bits of space to store an addend. This means that in
309 order for the linker to handle carries correctly, it must be able
310 to locate both the HI and the LO relocation. This means that the
311 relocations must appear in order in the relocation table.
313 In order to implement this, we keep track of each unmatched HI
314 relocation. We then sort them so that they immediately precede the
315 corresponding LO relocation. */
320 struct mips_hi_fixup
*next
;
323 /* The section this fixup is in. */
327 /* The list of unmatched HI relocs. */
329 static struct mips_hi_fixup
*mips_hi_fixup_list
;
331 /* Since the MIPS does not have multiple forms of PC relative
332 instructions, we do not have to do relaxing as is done on other
333 platforms. However, we do have to handle GP relative addressing
334 correctly, which turns out to be a similar problem.
336 Every macro that refers to a symbol can occur in (at least) two
337 forms, one with GP relative addressing and one without. For
338 example, loading a global variable into a register generally uses
339 a macro instruction like this:
341 If i can be addressed off the GP register (this is true if it is in
342 the .sbss or .sdata section, or if it is known to be smaller than
343 the -G argument) this will generate the following instruction:
345 This instruction will use a GPREL reloc. If i can not be addressed
346 off the GP register, the following instruction sequence will be used:
349 In this case the first instruction will have a HI16 reloc, and the
350 second reloc will have a LO16 reloc. Both relocs will be against
353 The issue here is that we may not know whether i is GP addressable
354 until after we see the instruction that uses it. Therefore, we
355 want to be able to choose the final instruction sequence only at
356 the end of the assembly. This is similar to the way other
357 platforms choose the size of a PC relative instruction only at the
360 When generating position independent code we do not use GP
361 addressing in quite the same way, but the issue still arises as
362 external symbols and local symbols must be handled differently.
364 We handle these issues by actually generating both possible
365 instruction sequences. The longer one is put in a frag_var with
366 type rs_machine_dependent. We encode what to do with the frag in
367 the subtype field. We encode (1) the number of existing bytes to
368 replace, (2) the number of new bytes to use, (3) the offset from
369 the start of the existing bytes to the first reloc we must generate
370 (that is, the offset is applied from the start of the existing
371 bytes after they are replaced by the new bytes, if any), (4) the
372 offset from the start of the existing bytes to the second reloc,
373 (5) whether a third reloc is needed (the third reloc is always four
374 bytes after the second reloc), and (6) whether to warn if this
375 variant is used (this is sometimes needed if .set nomacro or .set
376 noat is in effect). All these numbers are reasonably small.
378 Generating two instruction sequences must be handled carefully to
379 ensure that delay slots are handled correctly. Fortunately, there
380 are a limited number of cases. When the second instruction
381 sequence is generated, append_insn is directed to maintain the
382 existing delay slot information, so it continues to apply to any
383 code after the second instruction sequence. This means that the
384 second instruction sequence must not impose any requirements not
385 required by the first instruction sequence.
387 These variant frags are then handled in functions called by the
388 machine independent code. md_estimate_size_before_relax returns
389 the final size of the frag. md_convert_frag sets up the final form
390 of the frag. tc_gen_reloc adjust the first reloc and adds a second
392 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
396 | (((reloc1) + 64) << 9) \
397 | (((reloc2) + 64) << 2) \
398 | ((reloc3) ? (1 << 1) : 0) \
400 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
401 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
402 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
403 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
404 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
405 #define RELAX_WARN(i) ((i) & 1)
407 /* Prototypes for static functions. */
410 #define internalError() \
411 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
413 #define internalError() as_fatal ("MIPS internal Error");
416 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
417 unsigned int reg
, int fpr
));
418 static int reg_needs_delay
PARAMS ((int));
419 static void append_insn
PARAMS ((char *place
,
420 struct mips_cl_insn
* ip
,
422 bfd_reloc_code_real_type r
,
424 static void mips_no_prev_insn
PARAMS ((void));
425 static void mips_emit_delays
PARAMS ((void));
427 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
428 const char *name
, const char *fmt
,
431 static void macro_build ();
433 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
434 expressionS
* ep
, int regnum
));
435 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
436 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
438 static void load_register
PARAMS ((int *, int, expressionS
*, int));
439 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
440 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
441 #ifdef LOSING_COMPILER
442 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
444 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
445 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
446 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
447 static symbolS
*get_symbol
PARAMS ((void));
448 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
449 static void s_align
PARAMS ((int));
450 static void s_change_sec
PARAMS ((int));
451 static void s_cons
PARAMS ((int));
452 static void s_float_cons
PARAMS ((int));
453 static void s_mips_globl
PARAMS ((int));
454 static void s_option
PARAMS ((int));
455 static void s_mipsset
PARAMS ((int));
456 static void s_abicalls
PARAMS ((int));
457 static void s_cpload
PARAMS ((int));
458 static void s_cprestore
PARAMS ((int));
459 static void s_gpword
PARAMS ((int));
460 static void s_cpadd
PARAMS ((int));
461 static void md_obj_begin
PARAMS ((void));
462 static void md_obj_end
PARAMS ((void));
463 static long get_number
PARAMS ((void));
464 static void s_ent
PARAMS ((int));
465 static void s_mipsend
PARAMS ((int));
466 static void s_file
PARAMS ((int));
470 The following pseudo-ops from the Kane and Heinrich MIPS book
471 should be defined here, but are currently unsupported: .alias,
472 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
474 The following pseudo-ops from the Kane and Heinrich MIPS book are
475 specific to the type of debugging information being generated, and
476 should be defined by the object format: .aent, .begin, .bend,
477 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
480 The following pseudo-ops from the Kane and Heinrich MIPS book are
481 not MIPS CPU specific, but are also not specific to the object file
482 format. This file is probably the best place to define them, but
483 they are not currently supported: .asm0, .endr, .lab, .repeat,
484 .struct, .weakext. */
486 static const pseudo_typeS mips_pseudo_table
[] =
488 /* MIPS specific pseudo-ops. */
489 {"option", s_option
, 0},
490 {"set", s_mipsset
, 0},
491 {"rdata", s_change_sec
, 'r'},
492 {"sdata", s_change_sec
, 's'},
493 {"livereg", s_ignore
, 0},
494 {"abicalls", s_abicalls
, 0},
495 {"cpload", s_cpload
, 0},
496 {"cprestore", s_cprestore
, 0},
497 {"gpword", s_gpword
, 0},
498 {"cpadd", s_cpadd
, 0},
500 /* Relatively generic pseudo-ops that happen to be used on MIPS
502 {"asciiz", stringer
, 1},
503 {"bss", s_change_sec
, 'b'},
506 {"dword", s_cons
, 3},
508 /* These pseudo-ops are defined in read.c, but must be overridden
509 here for one reason or another. */
510 {"align", s_align
, 0},
512 {"data", s_change_sec
, 'd'},
513 {"double", s_float_cons
, 'd'},
514 {"float", s_float_cons
, 'f'},
515 {"globl", s_mips_globl
, 0},
516 {"global", s_mips_globl
, 0},
517 {"hword", s_cons
, 1},
522 {"short", s_cons
, 1},
523 {"single", s_float_cons
, 'f'},
524 {"text", s_change_sec
, 't'},
529 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
530 /* These pseudo-ops should be defined by the object file format.
531 However, a.out doesn't support them, so we have versions here. */
533 {"bgnb", s_ignore
, 0},
534 {"end", s_mipsend
, 0},
535 {"endb", s_ignore
, 0},
538 {"fmask", s_ignore
, 'F'},
539 {"frame", s_ignore
, 0},
540 {"loc", s_ignore
, 0},
541 {"mask", s_ignore
, 'R'},
542 {"verstamp", s_ignore
, 0},
546 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
551 pop_insert (mips_pseudo_table
);
552 if (! ECOFF_DEBUGGING
)
553 pop_insert (mips_nonecoff_pseudo_table
);
556 static char *expr_end
;
558 /* Expressions which appear in instructions. These are set by
561 static expressionS imm_expr
;
562 static expressionS offset_expr
;
564 /* Relocs associated with imm_expr and offset_expr. */
566 static bfd_reloc_code_real_type imm_reloc
;
567 static bfd_reloc_code_real_type offset_reloc
;
569 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
571 static boolean imm_unmatched_hi
;
574 * This function is called once, at assembler startup time. It should
575 * set up all the tables, etc. that the MD part of the assembler will need.
581 register const char *retval
= NULL
;
582 register unsigned int i
= 0;
590 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
592 a
= xmalloc (sizeof TARGET_CPU
);
593 strcpy (a
, TARGET_CPU
);
594 a
[(sizeof TARGET_CPU
) - 3] = '\0';
598 if (strcmp (cpu
, "mips") == 0)
604 else if (strcmp (cpu
, "r6000") == 0
605 || strcmp (cpu
, "mips2") == 0)
611 else if (strcmp (cpu
, "mips64") == 0
612 || strcmp (cpu
, "r4000") == 0
613 || strcmp (cpu
, "mips3") == 0)
619 else if (strcmp (cpu
, "r4400") == 0)
625 else if (strcmp (cpu
, "mips64orion") == 0
626 || strcmp (cpu
, "r4600") == 0)
632 else if (strcmp (cpu
, "r4650") == 0)
640 else if (strcmp (cpu
, "mips64vr4300") == 0)
646 else if (strcmp (cpu
, "mips64vr4100") == 0)
654 else if (strcmp (cpu
, "r4010") == 0)
662 else if (strcmp (cpu
, "r8000") == 0
663 || strcmp (cpu
, "mips4") == 0)
669 else if (strcmp (cpu
, "r10000") == 0)
695 if (mips_4650
|| mips_4010
|| mips_4100
|| mips_cpu
== 4300)
700 if (mips_cpu
== 4300)
705 if (mips_isa
< 2 && mips_trap
)
706 as_bad ("trap exception not supported at ISA 1");
711 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
714 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
717 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
720 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
724 as_warn ("Could not set architecture and machine");
726 file_mips_isa
= mips_isa
;
728 op_hash
= hash_new ();
730 for (i
= 0; i
< NUMOPCODES
;)
732 const char *name
= mips_opcodes
[i
].name
;
734 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
737 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
738 mips_opcodes
[i
].name
, retval
);
739 as_fatal ("Broken assembler. No assembly attempted.");
743 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
744 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
745 != mips_opcodes
[i
].match
))
747 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
748 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
749 as_fatal ("Broken assembler. No assembly attempted.");
753 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
756 mips_no_prev_insn ();
764 /* set the default alignment for the text section (2**2) */
765 record_alignment (text_section
, 2);
767 if (USE_GLOBAL_POINTER_OPT
)
768 bfd_set_gp_size (stdoutput
, g_switch_value
);
770 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
772 /* Sections must be aligned to 16 byte boundaries. */
773 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
774 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
775 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
777 /* Create a .reginfo section for register masks and a .mdebug
778 section for debugging information. */
789 sec
= subseg_new (".reginfo", (subsegT
) 0);
791 /* The ABI says this section should be loaded so that the
792 running program can access it. */
793 (void) bfd_set_section_flags (stdoutput
, sec
,
794 (SEC_ALLOC
| SEC_LOAD
795 | SEC_READONLY
| SEC_DATA
));
796 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
799 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
804 /* The 64-bit ABI uses a .MIPS.options section rather than
806 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
807 (void) bfd_set_section_flags (stdoutput
, sec
,
808 (SEC_ALLOC
| SEC_LOAD
809 | SEC_READONLY
| SEC_DATA
));
810 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
813 /* Set up the option header. */
815 Elf_Internal_Options opthdr
;
818 opthdr
.kind
= ODK_REGINFO
;
819 opthdr
.size
= (sizeof (Elf_External_Options
)
820 + sizeof (Elf64_External_RegInfo
));
823 f
= frag_more (sizeof (Elf_External_Options
));
824 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
825 (Elf_External_Options
*) f
);
827 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
834 sec
= subseg_new (".mdebug", (subsegT
) 0);
835 (void) bfd_set_section_flags (stdoutput
, sec
,
836 SEC_HAS_CONTENTS
| SEC_READONLY
);
837 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
840 subseg_set (seg
, subseg
);
844 if (! ECOFF_DEBUGGING
)
851 if (! ECOFF_DEBUGGING
)
859 struct mips_cl_insn insn
;
861 imm_expr
.X_op
= O_absent
;
862 imm_reloc
= BFD_RELOC_UNUSED
;
863 imm_unmatched_hi
= false;
864 offset_expr
.X_op
= O_absent
;
865 offset_reloc
= BFD_RELOC_UNUSED
;
867 mips_ip (str
, &insn
);
870 as_bad ("%s `%s'", insn_error
, str
);
873 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
879 if (imm_expr
.X_op
!= O_absent
)
880 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
882 else if (offset_expr
.X_op
!= O_absent
)
883 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
885 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
889 /* See whether instruction IP reads register REG. If FPR is non-zero,
890 REG is a floating point register. */
893 insn_uses_reg (ip
, reg
, fpr
)
894 struct mips_cl_insn
*ip
;
898 /* Don't report on general register 0, since it never changes. */
899 if (! fpr
&& reg
== 0)
904 /* If we are called with either $f0 or $f1, we must check $f0.
905 This is not optimal, because it will introduce an unnecessary
906 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
907 need to distinguish reading both $f0 and $f1 or just one of
908 them. Note that we don't have to check the other way,
909 because there is no instruction that sets both $f0 and $f1
910 and requires a delay. */
911 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
912 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
913 == (reg
&~ (unsigned) 1)))
915 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
916 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
917 == (reg
&~ (unsigned) 1)))
922 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
923 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
925 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
926 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
933 /* This function returns true if modifying a register requires a
937 reg_needs_delay (reg
)
940 unsigned long prev_pinfo
;
942 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
945 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
947 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
949 /* A load from a coprocessor or from memory. All load
950 delays delay the use of general register rt for one
951 instruction on the r3000. The r6000 and r4000 use
953 know (prev_pinfo
& INSN_WRITE_GPR_T
);
954 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
961 /* Output an instruction. PLACE is where to put the instruction; if
962 it is NULL, this uses frag_more to get room. IP is the instruction
963 information. ADDRESS_EXPR is an operand of the instruction to be
964 used with RELOC_TYPE. */
967 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
969 struct mips_cl_insn
*ip
;
970 expressionS
*address_expr
;
971 bfd_reloc_code_real_type reloc_type
;
972 boolean unmatched_hi
;
974 register unsigned long prev_pinfo
, pinfo
;
979 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
980 pinfo
= ip
->insn_mo
->pinfo
;
982 if (place
== NULL
&& ! mips_noreorder
)
984 /* If the previous insn required any delay slots, see if we need
985 to insert a NOP or two. There are eight kinds of possible
986 hazards, of which an instruction can have at most one type.
987 (1) a load from memory delay
988 (2) a load from a coprocessor delay
989 (3) an unconditional branch delay
990 (4) a conditional branch delay
991 (5) a move to coprocessor register delay
992 (6) a load coprocessor register from memory delay
993 (7) a coprocessor condition code delay
994 (8) a HI/LO special register delay
996 There are a lot of optimizations we could do that we don't.
997 In particular, we do not, in general, reorder instructions.
998 If you use gcc with optimization, it will reorder
999 instructions and generally do much more optimization then we
1000 do here; repeating all that work in the assembler would only
1001 benefit hand written assembly code, and does not seem worth
1004 /* This is how a NOP is emitted. */
1005 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
1007 /* The previous insn might require a delay slot, depending upon
1008 the contents of the current insn. */
1010 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1013 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1015 /* A load from a coprocessor or from memory. All load
1016 delays delay the use of general register rt for one
1017 instruction on the r3000. The r6000 and r4000 use
1019 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1020 if (mips_optimize
== 0
1021 || insn_uses_reg (ip
,
1022 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1027 else if (mips_isa
< 4
1028 && ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1031 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1033 /* A generic coprocessor delay. The previous instruction
1034 modified a coprocessor general or control register. If
1035 it modified a control register, we need to avoid any
1036 coprocessor instruction (this is probably not always
1037 required, but it sometimes is). If it modified a general
1038 register, we avoid using that register.
1040 On the r6000 and r4000 loading a coprocessor register
1041 from memory is interlocked, and does not require a delay.
1043 This case is not handled very well. There is no special
1044 knowledge of CP0 handling, and the coprocessors other
1045 than the floating point unit are not distinguished at
1047 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1049 if (mips_optimize
== 0
1050 || insn_uses_reg (ip
,
1051 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1056 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1058 if (mips_optimize
== 0
1059 || insn_uses_reg (ip
,
1060 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1067 /* We don't know exactly what the previous instruction
1068 does. If the current instruction uses a coprocessor
1069 register, we must insert a NOP. If previous
1070 instruction may set the condition codes, and the
1071 current instruction uses them, we must insert two
1073 if (mips_optimize
== 0
1074 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1075 && (pinfo
& INSN_READ_COND_CODE
)))
1077 else if (pinfo
& INSN_COP
)
1081 else if (mips_isa
< 4
1082 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1083 && ! cop_interlocks
)
1085 /* The previous instruction sets the coprocessor condition
1086 codes, but does not require a general coprocessor delay
1087 (this means it is a floating point comparison
1088 instruction). If this instruction uses the condition
1089 codes, we need to insert a single NOP. */
1090 if (mips_optimize
== 0
1091 || (pinfo
& INSN_READ_COND_CODE
))
1094 else if (prev_pinfo
& INSN_READ_LO
)
1096 /* The previous instruction reads the LO register; if the
1097 current instruction writes to the LO register, we must
1098 insert two NOPS. The R4650, VR4100 and VR4300 have
1101 && (mips_optimize
== 0
1102 || (pinfo
& INSN_WRITE_LO
)))
1105 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1107 /* The previous instruction reads the HI register; if the
1108 current instruction writes to the HI register, we must
1109 insert a NOP. The R4650, VR4100 and VR4300 have
1112 && (mips_optimize
== 0
1113 || (pinfo
& INSN_WRITE_HI
)))
1117 /* There are two cases which require two intervening
1118 instructions: 1) setting the condition codes using a move to
1119 coprocessor instruction which requires a general coprocessor
1120 delay and then reading the condition codes 2) reading the HI
1121 or LO register and then writing to it (except on the R4650,
1122 VR4100, and VR4300 which have interlocks). If we are not
1123 already emitting a NOP instruction, we must check for these
1124 cases compared to the instruction previous to the previous
1128 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1129 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1130 && (pinfo
& INSN_READ_COND_CODE
)
1131 && ! cop_interlocks
)
1132 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1133 && (pinfo
& INSN_WRITE_LO
)
1135 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1136 && (pinfo
& INSN_WRITE_HI
)
1140 /* If we are being given a nop instruction, don't bother with
1141 one of the nops we would otherwise output. This will only
1142 happen when a nop instruction is used with mips_optimize set
1144 if (nops
> 0 && ip
->insn_opcode
== 0)
1147 /* Now emit the right number of NOP instructions. */
1152 for (i
= 0; i
< nops
; i
++)
1156 listing_prev_line ();
1157 /* We may be at the start of a variant frag. In case we
1158 are, make sure there is enough space for the frag
1159 after the frags created by listing_prev_line. The
1160 argument to frag_grow here must be at least as large
1161 as the argument to all other calls to frag_grow in
1162 this file. We don't have to worry about being in the
1163 middle of a variant frag, because the variants insert
1164 all needed nop instructions themselves. */
1167 if (insn_label
!= NULL
)
1169 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1170 insn_label
->sy_frag
= frag_now
;
1171 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1181 if (address_expr
!= NULL
)
1183 if (address_expr
->X_op
== O_constant
)
1188 ip
->insn_opcode
|= address_expr
->X_add_number
;
1191 case BFD_RELOC_LO16
:
1192 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1195 case BFD_RELOC_MIPS_JMP
:
1196 case BFD_RELOC_16_PCREL_S2
:
1205 assert (reloc_type
!= BFD_RELOC_UNUSED
);
1207 /* Don't generate a reloc if we are writing into a variant
1211 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1213 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1217 struct mips_hi_fixup
*hi_fixup
;
1219 assert (reloc_type
== BFD_RELOC_HI16_S
);
1220 hi_fixup
= ((struct mips_hi_fixup
*)
1221 xmalloc (sizeof (struct mips_hi_fixup
)));
1222 hi_fixup
->fixp
= fixp
;
1223 hi_fixup
->seg
= now_seg
;
1224 hi_fixup
->next
= mips_hi_fixup_list
;
1225 mips_hi_fixup_list
= hi_fixup
;
1231 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1233 /* Update the register mask information. */
1234 if (pinfo
& INSN_WRITE_GPR_D
)
1235 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1236 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1237 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1238 if (pinfo
& INSN_READ_GPR_S
)
1239 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1240 if (pinfo
& INSN_WRITE_GPR_31
)
1241 mips_gprmask
|= 1 << 31;
1242 if (pinfo
& INSN_WRITE_FPR_D
)
1243 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1244 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1245 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1246 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1247 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1248 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1249 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1250 if (pinfo
& INSN_COP
)
1252 /* We don't keep enough information to sort these cases out. */
1254 /* Never set the bit for $0, which is always zero. */
1255 mips_gprmask
&=~ 1 << 0;
1257 if (place
== NULL
&& ! mips_noreorder
)
1259 /* Filling the branch delay slot is more complex. We try to
1260 switch the branch with the previous instruction, which we can
1261 do if the previous instruction does not set up a condition
1262 that the branch tests and if the branch is not itself the
1263 target of any branch. */
1264 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1265 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1267 if (mips_optimize
< 2
1268 /* If we have seen .set volatile or .set nomove, don't
1271 /* If we had to emit any NOP instructions, then we
1272 already know we can not swap. */
1274 /* If we don't even know the previous insn, we can not
1276 || ! prev_insn_valid
1277 /* If the previous insn is already in a branch delay
1278 slot, then we can not swap. */
1279 || prev_insn_is_delay_slot
1280 /* If the previous previous insn was in a .set
1281 noreorder, we can't swap. Actually, the MIPS
1282 assembler will swap in this situation. However, gcc
1283 configured -with-gnu-as will generate code like
1289 in which we can not swap the bne and INSN. If gcc is
1290 not configured -with-gnu-as, it does not output the
1291 .set pseudo-ops. We don't have to check
1292 prev_insn_unreordered, because prev_insn_valid will
1293 be 0 in that case. We don't want to use
1294 prev_prev_insn_valid, because we do want to be able
1295 to swap at the start of a function. */
1296 || prev_prev_insn_unreordered
1297 /* If the branch is itself the target of a branch, we
1298 can not swap. We cheat on this; all we check for is
1299 whether there is a label on this instruction. If
1300 there are any branches to anything other than a
1301 label, users must use .set noreorder. */
1302 || insn_label
!= NULL
1303 /* If the previous instruction is in a variant frag, we
1304 can not do the swap. */
1305 || prev_insn_frag
->fr_type
== rs_machine_dependent
1306 /* If the branch reads the condition codes, we don't
1307 even try to swap, because in the sequence
1312 we can not swap, and I don't feel like handling that
1315 && (pinfo
& INSN_READ_COND_CODE
))
1316 /* We can not swap with an instruction that requires a
1317 delay slot, becase the target of the branch might
1318 interfere with that instruction. */
1321 & (INSN_LOAD_COPROC_DELAY
1322 | INSN_COPROC_MOVE_DELAY
1323 | INSN_WRITE_COND_CODE
)))
1330 & (INSN_LOAD_MEMORY_DELAY
1331 | INSN_COPROC_MEMORY_DELAY
)))
1332 /* We can not swap with a branch instruction. */
1334 & (INSN_UNCOND_BRANCH_DELAY
1335 | INSN_COND_BRANCH_DELAY
1336 | INSN_COND_BRANCH_LIKELY
))
1337 /* We do not swap with a trap instruction, since it
1338 complicates trap handlers to have the trap
1339 instruction be in a delay slot. */
1340 || (prev_pinfo
& INSN_TRAP
)
1341 /* If the branch reads a register that the previous
1342 instruction sets, we can not swap. */
1343 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1344 && insn_uses_reg (ip
,
1345 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1348 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1349 && insn_uses_reg (ip
,
1350 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1353 /* If the branch writes a register that the previous
1354 instruction sets, we can not swap (we know that
1355 branches write only to RD or to $31). */
1356 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1357 && (((pinfo
& INSN_WRITE_GPR_D
)
1358 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1359 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1360 || ((pinfo
& INSN_WRITE_GPR_31
)
1361 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1364 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1365 && (((pinfo
& INSN_WRITE_GPR_D
)
1366 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1367 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1368 || ((pinfo
& INSN_WRITE_GPR_31
)
1369 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1372 /* If the branch writes a register that the previous
1373 instruction reads, we can not swap (we know that
1374 branches only write to RD or to $31). */
1375 || ((pinfo
& INSN_WRITE_GPR_D
)
1376 && insn_uses_reg (&prev_insn
,
1377 ((ip
->insn_opcode
>> OP_SH_RD
)
1380 || ((pinfo
& INSN_WRITE_GPR_31
)
1381 && insn_uses_reg (&prev_insn
, 31, 0))
1382 /* If we are generating embedded PIC code, the branch
1383 might be expanded into a sequence which uses $at, so
1384 we can't swap with an instruction which reads it. */
1385 || (mips_pic
== EMBEDDED_PIC
1386 && insn_uses_reg (&prev_insn
, AT
, 0))
1387 /* If the previous previous instruction has a load
1388 delay, and sets a register that the branch reads, we
1391 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1393 && (prev_prev_insn
.insn_mo
->pinfo
1394 & INSN_LOAD_MEMORY_DELAY
)))
1395 && insn_uses_reg (ip
,
1396 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1400 /* We could do even better for unconditional branches to
1401 portions of this object file; we could pick up the
1402 instruction at the destination, put it in the delay
1403 slot, and bump the destination address. */
1405 /* Update the previous insn information. */
1406 prev_prev_insn
= *ip
;
1407 prev_insn
.insn_mo
= &dummy_opcode
;
1414 /* It looks like we can actually do the swap. */
1415 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1416 memcpy (temp
, prev_f
, 4);
1417 memcpy (prev_f
, f
, 4);
1418 memcpy (f
, temp
, 4);
1421 prev_insn_fixp
->fx_frag
= frag_now
;
1422 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1426 fixp
->fx_frag
= prev_insn_frag
;
1427 fixp
->fx_where
= prev_insn_where
;
1429 /* Update the previous insn information; leave prev_insn
1431 prev_prev_insn
= *ip
;
1433 prev_insn_is_delay_slot
= 1;
1435 /* If that was an unconditional branch, forget the previous
1436 insn information. */
1437 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1439 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1440 prev_insn
.insn_mo
= &dummy_opcode
;
1443 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1445 /* We don't yet optimize a branch likely. What we should do
1446 is look at the target, copy the instruction found there
1447 into the delay slot, and increment the branch to jump to
1448 the next instruction. */
1450 /* Update the previous insn information. */
1451 prev_prev_insn
= *ip
;
1452 prev_insn
.insn_mo
= &dummy_opcode
;
1456 /* Update the previous insn information. */
1458 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1460 prev_prev_insn
= prev_insn
;
1463 /* Any time we see a branch, we always fill the delay slot
1464 immediately; since this insn is not a branch, we know it
1465 is not in a delay slot. */
1466 prev_insn_is_delay_slot
= 0;
1469 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1470 prev_insn_unreordered
= 0;
1471 prev_insn_frag
= frag_now
;
1472 prev_insn_where
= f
- frag_now
->fr_literal
;
1473 prev_insn_fixp
= fixp
;
1474 prev_insn_valid
= 1;
1477 /* We just output an insn, so the next one doesn't have a label. */
1481 /* This function forgets that there was any previous instruction or
1485 mips_no_prev_insn ()
1487 prev_insn
.insn_mo
= &dummy_opcode
;
1488 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1489 prev_insn_valid
= 0;
1490 prev_insn_is_delay_slot
= 0;
1491 prev_insn_unreordered
= 0;
1492 prev_prev_insn_unreordered
= 0;
1496 /* This function must be called whenever we turn on noreorder or emit
1497 something other than instructions. It inserts any NOPS which might
1498 be needed by the previous instruction, and clears the information
1499 kept for the previous instructions. */
1504 if (! mips_noreorder
)
1510 && (! cop_interlocks
1511 && (prev_insn
.insn_mo
->pinfo
1512 & (INSN_LOAD_COPROC_DELAY
1513 | INSN_COPROC_MOVE_DELAY
1514 | INSN_WRITE_COND_CODE
))))
1516 && (prev_insn
.insn_mo
->pinfo
1520 && (prev_insn
.insn_mo
->pinfo
1521 & (INSN_LOAD_MEMORY_DELAY
1522 | INSN_COPROC_MEMORY_DELAY
))))
1526 && (! cop_interlocks
1527 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1529 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1530 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1533 else if ((mips_isa
< 4
1534 && (! cop_interlocks
1535 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
1537 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1538 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
1543 if (insn_label
!= NULL
)
1545 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1546 insn_label
->sy_frag
= frag_now
;
1547 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1552 mips_no_prev_insn ();
1555 /* Build an instruction created by a macro expansion. This is passed
1556 a pointer to the count of instructions created so far, an
1557 expression, the name of the instruction to build, an operand format
1558 string, and corresponding arguments. */
1562 macro_build (char *place
,
1570 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1579 struct mips_cl_insn insn
;
1580 bfd_reloc_code_real_type r
;
1584 va_start (args
, fmt
);
1590 * If the macro is about to expand into a second instruction,
1591 * print a warning if needed. We need to pass ip as a parameter
1592 * to generate a better warning message here...
1594 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1595 as_warn ("Macro instruction expanded into multiple instructions");
1598 *counter
+= 1; /* bump instruction counter */
1600 r
= BFD_RELOC_UNUSED
;
1601 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1602 assert (insn
.insn_mo
);
1603 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1605 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1606 || insn
.insn_mo
->pinfo
== INSN_MACRO
1607 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
1609 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
1611 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
1613 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
1615 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
1617 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
1621 assert (insn
.insn_mo
->name
);
1622 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1624 insn
.insn_opcode
= insn
.insn_mo
->match
;
1640 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1646 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1651 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1656 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1663 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1667 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1671 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1678 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1684 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1685 assert (r
== BFD_RELOC_MIPS_GPREL
1686 || r
== BFD_RELOC_MIPS_LITERAL
1687 || r
== BFD_RELOC_LO16
1688 || r
== BFD_RELOC_MIPS_GOT16
1689 || r
== BFD_RELOC_MIPS_CALL16
1690 || r
== BFD_RELOC_MIPS_GOT_LO16
1691 || r
== BFD_RELOC_MIPS_CALL_LO16
1692 || (ep
->X_op
== O_subtract
1693 && now_seg
== text_section
1694 && r
== BFD_RELOC_PCREL_LO16
));
1698 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1700 && (ep
->X_op
== O_constant
1701 || (ep
->X_op
== O_symbol
1702 && (r
== BFD_RELOC_HI16_S
1703 || r
== BFD_RELOC_HI16
1704 || r
== BFD_RELOC_MIPS_GOT_HI16
1705 || r
== BFD_RELOC_MIPS_CALL_HI16
))
1706 || (ep
->X_op
== O_subtract
1707 && now_seg
== text_section
1708 && r
== BFD_RELOC_PCREL_HI16_S
)));
1709 if (ep
->X_op
== O_constant
)
1711 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1713 r
= BFD_RELOC_UNUSED
;
1718 assert (ep
!= NULL
);
1720 * This allows macro() to pass an immediate expression for
1721 * creating short branches without creating a symbol.
1722 * Note that the expression still might come from the assembly
1723 * input, in which case the value is not checked for range nor
1724 * is a relocation entry generated (yuck).
1726 if (ep
->X_op
== O_constant
)
1728 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1732 r
= BFD_RELOC_16_PCREL_S2
;
1736 assert (ep
!= NULL
);
1737 r
= BFD_RELOC_MIPS_JMP
;
1746 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1748 append_insn (place
, &insn
, ep
, r
, false);
1752 * Generate a "lui" instruction.
1755 macro_build_lui (place
, counter
, ep
, regnum
)
1761 expressionS high_expr
;
1762 struct mips_cl_insn insn
;
1763 bfd_reloc_code_real_type r
;
1764 CONST
char *name
= "lui";
1765 CONST
char *fmt
= "t,u";
1771 high_expr
.X_op
= O_constant
;
1772 high_expr
.X_add_number
= ep
->X_add_number
;
1775 if (high_expr
.X_op
== O_constant
)
1777 /* we can compute the instruction now without a relocation entry */
1778 if (high_expr
.X_add_number
& 0x8000)
1779 high_expr
.X_add_number
+= 0x10000;
1780 high_expr
.X_add_number
=
1781 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1782 r
= BFD_RELOC_UNUSED
;
1786 assert (ep
->X_op
== O_symbol
);
1787 /* _gp_disp is a special case, used from s_cpload. */
1788 assert (mips_pic
== NO_PIC
1789 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1790 r
= BFD_RELOC_HI16_S
;
1794 * If the macro is about to expand into a second instruction,
1795 * print a warning if needed. We need to pass ip as a parameter
1796 * to generate a better warning message here...
1798 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1799 as_warn ("Macro instruction expanded into multiple instructions");
1802 *counter
+= 1; /* bump instruction counter */
1804 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1805 assert (insn
.insn_mo
);
1806 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1807 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1809 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1810 if (r
== BFD_RELOC_UNUSED
)
1812 insn
.insn_opcode
|= high_expr
.X_add_number
;
1813 append_insn (place
, &insn
, NULL
, r
, false);
1816 append_insn (place
, &insn
, &high_expr
, r
, false);
1820 * Generates code to set the $at register to true (one)
1821 * if reg is less than the immediate expression.
1824 set_at (counter
, reg
, unsignedp
)
1829 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1830 macro_build ((char *) NULL
, counter
, &imm_expr
,
1831 unsignedp
? "sltiu" : "slti",
1832 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1835 load_register (counter
, AT
, &imm_expr
, 0);
1836 macro_build ((char *) NULL
, counter
, NULL
,
1837 unsignedp
? "sltu" : "slt",
1838 "d,v,t", AT
, reg
, AT
);
1842 /* Warn if an expression is not a constant. */
1845 check_absolute_expr (ip
, ex
)
1846 struct mips_cl_insn
*ip
;
1849 if (ex
->X_op
!= O_constant
)
1850 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1854 * This routine generates the least number of instructions neccessary to load
1855 * an absolute expression value into a register.
1858 load_register (counter
, reg
, ep
, dbl
)
1865 expressionS hi32
, lo32
, tmp
;
1867 if (ep
->X_op
!= O_big
)
1869 assert (ep
->X_op
== O_constant
);
1870 if (ep
->X_add_number
< 0x8000
1871 && (ep
->X_add_number
>= 0
1872 || (ep
->X_add_number
>= -0x8000
1875 || sizeof (ep
->X_add_number
) > 4))))
1877 /* We can handle 16 bit signed values with an addiu to
1878 $zero. No need to ever use daddiu here, since $zero and
1879 the result are always correct in 32 bit mode. */
1880 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1881 (int) BFD_RELOC_LO16
);
1884 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1886 /* We can handle 16 bit unsigned values with an ori to
1888 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1889 (int) BFD_RELOC_LO16
);
1892 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1893 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1894 == ~ (offsetT
) 0x7fffffff))
1897 || sizeof (ep
->X_add_number
) > 4
1898 || (ep
->X_add_number
& 0x80000000) == 0))
1900 && (ep
->X_add_number
&~ 0xffffffff) == 0))
1902 /* 32 bit values require an lui. */
1903 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
1904 (int) BFD_RELOC_HI16
);
1905 if ((ep
->X_add_number
& 0xffff) != 0)
1906 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1907 (int) BFD_RELOC_LO16
);
1912 /* 32 bit value with high bit set being loaded into a 64 bit
1913 register. We can't use lui, because that would
1914 incorrectly set the 32 high bits. */
1915 generic_bignum
[3] = 0;
1916 generic_bignum
[2] = 0;
1917 generic_bignum
[1] = (ep
->X_add_number
>> 16) & 0xffff;
1918 generic_bignum
[0] = ep
->X_add_number
& 0xffff;
1920 tmp
.X_add_number
= 4;
1925 /* The value is larger than 32 bits. */
1929 as_bad ("Number larger than 32 bits");
1930 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1931 (int) BFD_RELOC_LO16
);
1935 if (ep
->X_op
!= O_big
)
1939 hi32
.X_add_number
>>= shift
;
1940 hi32
.X_add_number
&= 0xffffffff;
1941 if ((hi32
.X_add_number
& 0x80000000) != 0)
1942 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1944 lo32
.X_add_number
&= 0xffffffff;
1948 assert (ep
->X_add_number
> 2);
1949 if (ep
->X_add_number
== 3)
1950 generic_bignum
[3] = 0;
1951 else if (ep
->X_add_number
> 4)
1952 as_bad ("Number larger than 64 bits");
1953 lo32
.X_op
= O_constant
;
1954 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
1955 hi32
.X_op
= O_constant
;
1956 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
1959 if (hi32
.X_add_number
== 0)
1963 if (hi32
.X_add_number
== 0xffffffff)
1965 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
1967 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j", reg
, 0,
1968 (int) BFD_RELOC_LO16
);
1971 if (lo32
.X_add_number
& 0x80000000)
1973 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1974 (int) BFD_RELOC_HI16
);
1975 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1976 (int) BFD_RELOC_LO16
);
1980 load_register (counter
, reg
, &hi32
, 0);
1983 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1987 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1996 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
1998 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
1999 (int) BFD_RELOC_HI16
);
2000 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2007 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2012 mid16
.X_add_number
>>= 16;
2013 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2014 freg
, (int) BFD_RELOC_LO16
);
2015 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2019 if ((lo32
.X_add_number
& 0xffff) != 0)
2020 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2021 (int) BFD_RELOC_LO16
);
2024 /* Load an address into a register. */
2027 load_address (counter
, reg
, ep
)
2034 if (ep
->X_op
!= O_constant
2035 && ep
->X_op
!= O_symbol
)
2037 as_bad ("expression too complex");
2038 ep
->X_op
= O_constant
;
2041 if (ep
->X_op
== O_constant
)
2043 load_register (counter
, reg
, ep
, 0);
2047 if (mips_pic
== NO_PIC
)
2049 /* If this is a reference to a GP relative symbol, we want
2050 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2052 lui $reg,<sym> (BFD_RELOC_HI16_S)
2053 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2054 If we have an addend, we always use the latter form. */
2055 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2056 || nopic_need_relax (ep
->X_add_symbol
))
2061 macro_build ((char *) NULL
, counter
, ep
,
2062 mips_isa
< 3 ? "addiu" : "daddiu",
2063 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2064 p
= frag_var (rs_machine_dependent
, 8, 0,
2065 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2066 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2068 macro_build_lui (p
, counter
, ep
, reg
);
2071 macro_build (p
, counter
, ep
,
2072 mips_isa
< 3 ? "addiu" : "daddiu",
2073 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2075 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2079 /* If this is a reference to an external symbol, we want
2080 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2082 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2084 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2085 If there is a constant, it must be added in after. */
2086 ex
.X_add_number
= ep
->X_add_number
;
2087 ep
->X_add_number
= 0;
2089 macro_build ((char *) NULL
, counter
, ep
,
2090 mips_isa
< 3 ? "lw" : "ld",
2091 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2092 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2093 p
= frag_var (rs_machine_dependent
, 4, 0,
2094 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2095 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2096 macro_build (p
, counter
, ep
,
2097 mips_isa
< 3 ? "addiu" : "daddiu",
2098 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2099 if (ex
.X_add_number
!= 0)
2101 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2102 as_bad ("PIC code offset overflow (max 16 signed bits)");
2103 ex
.X_op
= O_constant
;
2104 macro_build ((char *) NULL
, counter
, &ex
,
2105 mips_isa
< 3 ? "addiu" : "daddiu",
2106 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2109 else if (mips_pic
== SVR4_PIC
)
2114 /* This is the large GOT case. If this is a reference to an
2115 external symbol, we want
2116 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2118 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2119 Otherwise, for a reference to a local symbol, we want
2120 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2122 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2123 If there is a constant, it must be added in after. */
2124 ex
.X_add_number
= ep
->X_add_number
;
2125 ep
->X_add_number
= 0;
2126 if (reg_needs_delay (GP
))
2131 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2132 (int) BFD_RELOC_MIPS_GOT_HI16
);
2133 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2134 mips_isa
< 3 ? "addu" : "daddu",
2135 "d,v,t", reg
, reg
, GP
);
2136 macro_build ((char *) NULL
, counter
, ep
,
2137 mips_isa
< 3 ? "lw" : "ld",
2138 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2139 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2140 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2141 mips_warn_about_macros
),
2142 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2145 /* We need a nop before loading from $gp. This special
2146 check is required because the lui which starts the main
2147 instruction stream does not refer to $gp, and so will not
2148 insert the nop which may be required. */
2149 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2152 macro_build (p
, counter
, ep
,
2153 mips_isa
< 3 ? "lw" : "ld",
2154 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2156 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2158 macro_build (p
, counter
, ep
,
2159 mips_isa
< 3 ? "addiu" : "daddiu",
2160 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2161 if (ex
.X_add_number
!= 0)
2163 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2164 as_bad ("PIC code offset overflow (max 16 signed bits)");
2165 ex
.X_op
= O_constant
;
2166 macro_build ((char *) NULL
, counter
, &ex
,
2167 mips_isa
< 3 ? "addiu" : "daddiu",
2168 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2171 else if (mips_pic
== EMBEDDED_PIC
)
2174 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2176 macro_build ((char *) NULL
, counter
, ep
,
2177 mips_isa
< 3 ? "addiu" : "daddiu",
2178 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2186 * This routine implements the seemingly endless macro or synthesized
2187 * instructions and addressing modes in the mips assembly language. Many
2188 * of these macros are simple and are similar to each other. These could
2189 * probably be handled by some kind of table or grammer aproach instead of
2190 * this verbose method. Others are not simple macros but are more like
2191 * optimizing code generation.
2192 * One interesting optimization is when several store macros appear
2193 * consecutivly that would load AT with the upper half of the same address.
2194 * The ensuing load upper instructions are ommited. This implies some kind
2195 * of global optimization. We currently only optimize within a single macro.
2196 * For many of the load and store macros if the address is specified as a
2197 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
2198 * first load register 'at' with zero and use it as the base register. The
2199 * mips assembler simply uses register $zero. Just one tiny optimization
2204 struct mips_cl_insn
*ip
;
2206 register int treg
, sreg
, dreg
, breg
;
2221 bfd_reloc_code_real_type r
;
2223 int hold_mips_optimize
;
2225 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
2226 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
2227 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
2228 mask
= ip
->insn_mo
->mask
;
2230 expr1
.X_op
= O_constant
;
2231 expr1
.X_op_symbol
= NULL
;
2232 expr1
.X_add_symbol
= NULL
;
2233 expr1
.X_add_number
= 1;
2245 mips_emit_delays ();
2247 mips_any_noreorder
= 1;
2249 expr1
.X_add_number
= 8;
2250 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
2252 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2254 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
2255 macro_build ((char *) NULL
, &icnt
, NULL
,
2256 dbl
? "dsub" : "sub",
2257 "d,v,t", dreg
, 0, sreg
);
2280 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2282 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
2283 (int) BFD_RELOC_LO16
);
2286 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2287 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2306 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
2308 if (mask
!= M_NOR_I
)
2309 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
2310 sreg
, (int) BFD_RELOC_LO16
);
2313 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
2314 treg
, sreg
, (int) BFD_RELOC_LO16
);
2315 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
2321 load_register (&icnt
, AT
, &imm_expr
, 0);
2322 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
2339 if (imm_expr
.X_add_number
== 0)
2341 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
2345 load_register (&icnt
, AT
, &imm_expr
, 0);
2346 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
2354 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2355 likely
? "bgezl" : "bgez",
2361 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2362 likely
? "blezl" : "blez",
2366 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2367 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2368 likely
? "beql" : "beq",
2375 /* check for > max integer */
2376 maxnum
= 0x7fffffff;
2384 if (imm_expr
.X_add_number
>= maxnum
2385 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2388 /* result is always false */
2391 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
2392 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2396 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
2397 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
2402 imm_expr
.X_add_number
++;
2406 if (mask
== M_BGEL_I
)
2408 if (imm_expr
.X_add_number
== 0)
2410 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2411 likely
? "bgezl" : "bgez",
2415 if (imm_expr
.X_add_number
== 1)
2417 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2418 likely
? "bgtzl" : "bgtz",
2422 maxnum
= 0x7fffffff;
2430 maxnum
= - maxnum
- 1;
2431 if (imm_expr
.X_add_number
<= maxnum
2432 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2435 /* result is always true */
2436 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
2437 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2440 set_at (&icnt
, sreg
, 0);
2441 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2442 likely
? "beql" : "beq",
2453 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2454 likely
? "beql" : "beq",
2458 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2460 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2461 likely
? "beql" : "beq",
2468 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2470 imm_expr
.X_add_number
++;
2474 if (mask
== M_BGEUL_I
)
2476 if (imm_expr
.X_add_number
== 0)
2478 if (imm_expr
.X_add_number
== 1)
2480 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2481 likely
? "bnel" : "bne",
2485 set_at (&icnt
, sreg
, 1);
2486 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2487 likely
? "beql" : "beq",
2496 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2497 likely
? "bgtzl" : "bgtz",
2503 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2504 likely
? "bltzl" : "bltz",
2508 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2509 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2510 likely
? "bnel" : "bne",
2519 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2520 likely
? "bnel" : "bne",
2526 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2528 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2529 likely
? "bnel" : "bne",
2538 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2539 likely
? "blezl" : "blez",
2545 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2546 likely
? "bgezl" : "bgez",
2550 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2551 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2552 likely
? "beql" : "beq",
2559 maxnum
= 0x7fffffff;
2567 if (imm_expr
.X_add_number
>= maxnum
2568 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
2570 imm_expr
.X_add_number
++;
2574 if (mask
== M_BLTL_I
)
2576 if (imm_expr
.X_add_number
== 0)
2578 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2579 likely
? "bltzl" : "bltz",
2583 if (imm_expr
.X_add_number
== 1)
2585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2586 likely
? "blezl" : "blez",
2590 set_at (&icnt
, sreg
, 0);
2591 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2592 likely
? "bnel" : "bne",
2601 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2602 likely
? "beql" : "beq",
2608 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2610 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2611 likely
? "beql" : "beq",
2618 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2620 imm_expr
.X_add_number
++;
2624 if (mask
== M_BLTUL_I
)
2626 if (imm_expr
.X_add_number
== 0)
2628 if (imm_expr
.X_add_number
== 1)
2630 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2631 likely
? "beql" : "beq",
2635 set_at (&icnt
, sreg
, 1);
2636 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2637 likely
? "bnel" : "bne",
2646 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2647 likely
? "bltzl" : "bltz",
2653 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2654 likely
? "bgtzl" : "bgtz",
2658 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2659 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2660 likely
? "bnel" : "bne",
2671 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2672 likely
? "bnel" : "bne",
2676 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2678 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2679 likely
? "bnel" : "bne",
2695 as_warn ("Divide by zero.");
2697 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2699 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2703 mips_emit_delays ();
2705 mips_any_noreorder
= 1;
2706 macro_build ((char *) NULL
, &icnt
, NULL
,
2707 dbl
? "ddiv" : "div",
2708 "z,s,t", sreg
, treg
);
2710 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2713 expr1
.X_add_number
= 8;
2714 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2715 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2716 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2718 expr1
.X_add_number
= -1;
2719 macro_build ((char *) NULL
, &icnt
, &expr1
,
2720 dbl
? "daddiu" : "addiu",
2721 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2722 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2723 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2726 expr1
.X_add_number
= 1;
2727 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2728 (int) BFD_RELOC_LO16
);
2729 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2734 expr1
.X_add_number
= 0x80000000;
2735 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
2736 (int) BFD_RELOC_HI16
);
2739 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2742 expr1
.X_add_number
= 8;
2743 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2744 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2745 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2748 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2787 if (imm_expr
.X_add_number
== 0)
2789 as_warn ("Divide by zero.");
2791 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2793 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2796 if (imm_expr
.X_add_number
== 1)
2798 if (strcmp (s2
, "mflo") == 0)
2799 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2802 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2805 if (imm_expr
.X_add_number
== -1
2806 && s
[strlen (s
) - 1] != 'u')
2808 if (strcmp (s2
, "mflo") == 0)
2811 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2814 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2818 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2822 load_register (&icnt
, AT
, &imm_expr
, dbl
);
2823 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2824 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2843 mips_emit_delays ();
2845 mips_any_noreorder
= 1;
2846 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2848 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2851 expr1
.X_add_number
= 8;
2852 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2853 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2854 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2857 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2863 /* Load the address of a symbol into a register. If breg is not
2864 zero, we then add a base register to it. */
2866 /* When generating embedded PIC code, we permit expressions of
2869 where bar is an address in the .text section. These are used
2870 when getting the addresses of functions. We don't permit
2871 X_add_number to be non-zero, because if the symbol is
2872 external the relaxing code needs to know that any addend is
2873 purely the offset to X_op_symbol. */
2874 if (mips_pic
== EMBEDDED_PIC
2875 && offset_expr
.X_op
== O_subtract
2876 && now_seg
== text_section
2877 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
2878 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
2879 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
2880 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
2881 ->sy_value
.X_add_symbol
)
2884 && offset_expr
.X_add_number
== 0)
2886 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
2887 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
2888 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2889 mips_isa
< 3 ? "addiu" : "daddiu",
2890 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
2894 if (offset_expr
.X_op
!= O_symbol
2895 && offset_expr
.X_op
!= O_constant
)
2897 as_bad ("expression too complex");
2898 offset_expr
.X_op
= O_constant
;
2912 if (offset_expr
.X_op
== O_constant
)
2913 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
2914 else if (mips_pic
== NO_PIC
)
2916 /* If this is a reference to an GP relative symbol, we want
2917 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2919 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2920 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2921 If we have a constant, we need two instructions anyhow,
2922 so we may as well always use the latter form. */
2923 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
2924 || nopic_need_relax (offset_expr
.X_add_symbol
))
2929 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2930 mips_isa
< 3 ? "addiu" : "daddiu",
2931 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2932 p
= frag_var (rs_machine_dependent
, 8, 0,
2933 RELAX_ENCODE (4, 8, 0, 4, 0,
2934 mips_warn_about_macros
),
2935 offset_expr
.X_add_symbol
, (long) 0,
2938 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2941 macro_build (p
, &icnt
, &offset_expr
,
2942 mips_isa
< 3 ? "addiu" : "daddiu",
2943 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2945 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2947 /* If this is a reference to an external symbol, and there
2948 is no constant, we want
2949 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2950 For a local symbol, we want
2951 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2953 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2955 If we have a small constant, and this is a reference to
2956 an external symbol, we want
2957 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2959 addiu $tempreg,$tempreg,<constant>
2960 For a local symbol, we want the same instruction
2961 sequence, but we output a BFD_RELOC_LO16 reloc on the
2964 If we have a large constant, and this is a reference to
2965 an external symbol, we want
2966 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2967 lui $at,<hiconstant>
2968 addiu $at,$at,<loconstant>
2969 addu $tempreg,$tempreg,$at
2970 For a local symbol, we want the same instruction
2971 sequence, but we output a BFD_RELOC_LO16 reloc on the
2972 addiu instruction. */
2973 expr1
.X_add_number
= offset_expr
.X_add_number
;
2974 offset_expr
.X_add_number
= 0;
2976 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2978 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2979 if (expr1
.X_add_number
== 0)
2987 /* We're going to put in an addu instruction using
2988 tempreg, so we may as well insert the nop right
2990 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2994 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2995 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2997 ? mips_warn_about_macros
2999 offset_expr
.X_add_symbol
, (long) 0,
3003 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3006 macro_build (p
, &icnt
, &expr1
,
3007 mips_isa
< 3 ? "addiu" : "daddiu",
3008 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3009 /* FIXME: If breg == 0, and the next instruction uses
3010 $tempreg, then if this variant case is used an extra
3011 nop will be generated. */
3013 else if (expr1
.X_add_number
>= -0x8000
3014 && expr1
.X_add_number
< 0x8000)
3016 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3018 macro_build ((char *) NULL
, &icnt
, &expr1
,
3019 mips_isa
< 3 ? "addiu" : "daddiu",
3020 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3021 (void) frag_var (rs_machine_dependent
, 0, 0,
3022 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3023 offset_expr
.X_add_symbol
, (long) 0,
3030 /* If we are going to add in a base register, and the
3031 target register and the base register are the same,
3032 then we are using AT as a temporary register. Since
3033 we want to load the constant into AT, we add our
3034 current AT (from the global offset table) and the
3035 register into the register now, and pretend we were
3036 not using a base register. */
3041 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3043 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3044 mips_isa
< 3 ? "addu" : "daddu",
3045 "d,v,t", treg
, AT
, breg
);
3051 /* Set mips_optimize around the lui instruction to avoid
3052 inserting an unnecessary nop after the lw. */
3053 hold_mips_optimize
= mips_optimize
;
3055 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3056 mips_optimize
= hold_mips_optimize
;
3058 macro_build ((char *) NULL
, &icnt
, &expr1
,
3059 mips_isa
< 3 ? "addiu" : "daddiu",
3060 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3061 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3062 mips_isa
< 3 ? "addu" : "daddu",
3063 "d,v,t", tempreg
, tempreg
, AT
);
3064 (void) frag_var (rs_machine_dependent
, 0, 0,
3065 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3066 offset_expr
.X_add_symbol
, (long) 0,
3071 else if (mips_pic
== SVR4_PIC
)
3075 /* This is the large GOT case. If this is a reference to an
3076 external symbol, and there is no constant, we want
3077 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3078 addu $tempreg,$tempreg,$gp
3079 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3080 For a local symbol, we want
3081 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3083 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3085 If we have a small constant, and this is a reference to
3086 an external symbol, we want
3087 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3088 addu $tempreg,$tempreg,$gp
3089 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3091 addiu $tempreg,$tempreg,<constant>
3092 For a local symbol, we want
3093 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3095 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3097 If we have a large constant, and this is a reference to
3098 an external symbol, we want
3099 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3100 addu $tempreg,$tempreg,$gp
3101 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3102 lui $at,<hiconstant>
3103 addiu $at,$at,<loconstant>
3104 addu $tempreg,$tempreg,$at
3105 For a local symbol, we want
3106 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3107 lui $at,<hiconstant>
3108 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3109 addu $tempreg,$tempreg,$at
3111 expr1
.X_add_number
= offset_expr
.X_add_number
;
3112 offset_expr
.X_add_number
= 0;
3114 if (reg_needs_delay (GP
))
3118 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3119 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3120 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3121 mips_isa
< 3 ? "addu" : "daddu",
3122 "d,v,t", tempreg
, tempreg
, GP
);
3123 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3125 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3127 if (expr1
.X_add_number
== 0)
3135 /* We're going to put in an addu instruction using
3136 tempreg, so we may as well insert the nop right
3138 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3143 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3144 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3147 ? mips_warn_about_macros
3149 offset_expr
.X_add_symbol
, (long) 0,
3152 else if (expr1
.X_add_number
>= -0x8000
3153 && expr1
.X_add_number
< 0x8000)
3155 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3157 macro_build ((char *) NULL
, &icnt
, &expr1
,
3158 mips_isa
< 3 ? "addiu" : "daddiu",
3159 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3161 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3162 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3164 ? mips_warn_about_macros
3166 offset_expr
.X_add_symbol
, (long) 0,
3173 /* If we are going to add in a base register, and the
3174 target register and the base register are the same,
3175 then we are using AT as a temporary register. Since
3176 we want to load the constant into AT, we add our
3177 current AT (from the global offset table) and the
3178 register into the register now, and pretend we were
3179 not using a base register. */
3187 assert (tempreg
== AT
);
3188 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3190 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3191 mips_isa
< 3 ? "addu" : "daddu",
3192 "d,v,t", treg
, AT
, breg
);
3197 /* Set mips_optimize around the lui instruction to avoid
3198 inserting an unnecessary nop after the lw. */
3199 hold_mips_optimize
= mips_optimize
;
3201 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3202 mips_optimize
= hold_mips_optimize
;
3204 macro_build ((char *) NULL
, &icnt
, &expr1
,
3205 mips_isa
< 3 ? "addiu" : "daddiu",
3206 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3207 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3208 mips_isa
< 3 ? "addu" : "daddu",
3209 "d,v,t", dreg
, dreg
, AT
);
3211 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
3212 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
3215 ? mips_warn_about_macros
3217 offset_expr
.X_add_symbol
, (long) 0,
3225 /* This is needed because this instruction uses $gp, but
3226 the first instruction on the main stream does not. */
3227 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3230 macro_build (p
, &icnt
, &offset_expr
,
3232 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3234 if (expr1
.X_add_number
>= -0x8000
3235 && expr1
.X_add_number
< 0x8000)
3237 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3239 macro_build (p
, &icnt
, &expr1
,
3240 mips_isa
< 3 ? "addiu" : "daddiu",
3241 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3242 /* FIXME: If add_number is 0, and there was no base
3243 register, the external symbol case ended with a load,
3244 so if the symbol turns out to not be external, and
3245 the next instruction uses tempreg, an unnecessary nop
3246 will be inserted. */
3252 /* We must add in the base register now, as in the
3253 external symbol case. */
3254 assert (tempreg
== AT
);
3255 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3257 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3258 mips_isa
< 3 ? "addu" : "daddu",
3259 "d,v,t", treg
, AT
, breg
);
3262 /* We set breg to 0 because we have arranged to add
3263 it in in both cases. */
3267 macro_build_lui (p
, &icnt
, &expr1
, AT
);
3269 macro_build (p
, &icnt
, &expr1
,
3270 mips_isa
< 3 ? "addiu" : "daddiu",
3271 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3273 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3274 mips_isa
< 3 ? "addu" : "daddu",
3275 "d,v,t", tempreg
, tempreg
, AT
);
3279 else if (mips_pic
== EMBEDDED_PIC
)
3282 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3284 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3285 mips_isa
< 3 ? "addiu" : "daddiu",
3286 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3292 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3293 mips_isa
< 3 ? "addu" : "daddu",
3294 "d,v,t", treg
, tempreg
, breg
);
3302 /* The j instruction may not be used in PIC code, since it
3303 requires an absolute address. We convert it to a b
3305 if (mips_pic
== NO_PIC
)
3306 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
3308 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3311 /* The jal instructions must be handled as macros because when
3312 generating PIC code they expand to multi-instruction
3313 sequences. Normally they are simple instructions. */
3318 if (mips_pic
== NO_PIC
3319 || mips_pic
== EMBEDDED_PIC
)
3320 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3322 else if (mips_pic
== SVR4_PIC
)
3324 if (sreg
!= PIC_CALL_REG
)
3325 as_warn ("MIPS PIC call to register other than $25");
3327 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
3329 if (mips_cprestore_offset
< 0)
3330 as_warn ("No .cprestore pseudo-op used in PIC code");
3333 expr1
.X_add_number
= mips_cprestore_offset
;
3334 macro_build ((char *) NULL
, &icnt
, &expr1
,
3335 mips_isa
< 3 ? "lw" : "ld",
3336 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
3345 if (mips_pic
== NO_PIC
)
3346 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
3347 else if (mips_pic
== SVR4_PIC
)
3349 /* If this is a reference to an external symbol, and we are
3350 using a small GOT, we want
3351 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
3355 lw $gp,cprestore($sp)
3356 The cprestore value is set using the .cprestore
3357 pseudo-op. If we are using a big GOT, we want
3358 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
3360 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
3364 lw $gp,cprestore($sp)
3365 If the symbol is not external, we want
3366 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3368 addiu $25,$25,<sym> (BFD_RELOC_LO16)
3371 lw $gp,cprestore($sp) */
3375 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3376 mips_isa
< 3 ? "lw" : "ld",
3377 "t,o(b)", PIC_CALL_REG
,
3378 (int) BFD_RELOC_MIPS_CALL16
, GP
);
3379 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3381 p
= frag_var (rs_machine_dependent
, 4, 0,
3382 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3383 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3389 if (reg_needs_delay (GP
))
3393 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3394 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
3395 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3396 mips_isa
< 3 ? "addu" : "daddu",
3397 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
3398 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3399 mips_isa
< 3 ? "lw" : "ld",
3400 "t,o(b)", PIC_CALL_REG
,
3401 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
3402 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3404 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3405 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
3407 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3410 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3413 macro_build (p
, &icnt
, &offset_expr
,
3414 mips_isa
< 3 ? "lw" : "ld",
3415 "t,o(b)", PIC_CALL_REG
,
3416 (int) BFD_RELOC_MIPS_GOT16
, GP
);
3418 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3421 macro_build (p
, &icnt
, &offset_expr
,
3422 mips_isa
< 3 ? "addiu" : "daddiu",
3423 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
3424 (int) BFD_RELOC_LO16
);
3425 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3426 "jalr", "s", PIC_CALL_REG
);
3427 if (mips_cprestore_offset
< 0)
3428 as_warn ("No .cprestore pseudo-op used in PIC code");
3432 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3434 expr1
.X_add_number
= mips_cprestore_offset
;
3435 macro_build ((char *) NULL
, &icnt
, &expr1
,
3436 mips_isa
< 3 ? "lw" : "ld",
3437 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
3441 else if (mips_pic
== EMBEDDED_PIC
)
3443 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
3444 /* The linker may expand the call to a longer sequence which
3445 uses $at, so we must break rather than return. */
3521 if (breg
== treg
|| coproc
|| lr
)
3590 if (mask
== M_LWC1_AB
3591 || mask
== M_SWC1_AB
3592 || mask
== M_LDC1_AB
3593 || mask
== M_SDC1_AB
3602 if (offset_expr
.X_op
!= O_constant
3603 && offset_expr
.X_op
!= O_symbol
)
3605 as_bad ("expression too complex");
3606 offset_expr
.X_op
= O_constant
;
3609 /* A constant expression in PIC code can be handled just as it
3610 is in non PIC code. */
3611 if (mips_pic
== NO_PIC
3612 || offset_expr
.X_op
== O_constant
)
3614 /* If this is a reference to a GP relative symbol, and there
3615 is no base register, we want
3616 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3617 Otherwise, if there is no base register, we want
3618 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3619 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3620 If we have a constant, we need two instructions anyhow,
3621 so we always use the latter form.
3623 If we have a base register, and this is a reference to a
3624 GP relative symbol, we want
3625 addu $tempreg,$breg,$gp
3626 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3628 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3629 addu $tempreg,$tempreg,$breg
3630 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
3631 With a constant we always use the latter case. */
3634 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3635 || nopic_need_relax (offset_expr
.X_add_symbol
))
3640 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3641 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3642 p
= frag_var (rs_machine_dependent
, 8, 0,
3643 RELAX_ENCODE (4, 8, 0, 4, 0,
3644 (mips_warn_about_macros
3645 || (used_at
&& mips_noat
))),
3646 offset_expr
.X_add_symbol
, (long) 0,
3650 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3653 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3654 (int) BFD_RELOC_LO16
, tempreg
);
3658 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3659 || nopic_need_relax (offset_expr
.X_add_symbol
))
3664 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3665 mips_isa
< 3 ? "addu" : "daddu",
3666 "d,v,t", tempreg
, breg
, GP
);
3667 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3668 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3669 p
= frag_var (rs_machine_dependent
, 12, 0,
3670 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
3671 offset_expr
.X_add_symbol
, (long) 0,
3674 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3677 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3678 mips_isa
< 3 ? "addu" : "daddu",
3679 "d,v,t", tempreg
, tempreg
, breg
);
3682 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
3683 (int) BFD_RELOC_LO16
, tempreg
);
3686 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3688 /* If this is a reference to an external symbol, we want
3689 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3691 <op> $treg,0($tempreg)
3693 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3695 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3696 <op> $treg,0($tempreg)
3697 If there is a base register, we add it to $tempreg before
3698 the <op>. If there is a constant, we stick it in the
3699 <op> instruction. We don't handle constants larger than
3700 16 bits, because we have no way to load the upper 16 bits
3701 (actually, we could handle them for the subset of cases
3702 in which we are not using $at). */
3703 assert (offset_expr
.X_op
== O_symbol
);
3704 expr1
.X_add_number
= offset_expr
.X_add_number
;
3705 offset_expr
.X_add_number
= 0;
3706 if (expr1
.X_add_number
< -0x8000
3707 || expr1
.X_add_number
>= 0x8000)
3708 as_bad ("PIC code offset overflow (max 16 signed bits)");
3710 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3711 mips_isa
< 3 ? "lw" : "ld",
3712 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3713 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3714 p
= frag_var (rs_machine_dependent
, 4, 0,
3715 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
3716 offset_expr
.X_add_symbol
, (long) 0,
3718 macro_build (p
, &icnt
, &offset_expr
,
3719 mips_isa
< 3 ? "addiu" : "daddiu",
3720 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3722 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3723 mips_isa
< 3 ? "addu" : "daddu",
3724 "d,v,t", tempreg
, tempreg
, breg
);
3725 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3726 (int) BFD_RELOC_LO16
, tempreg
);
3728 else if (mips_pic
== SVR4_PIC
)
3732 /* If this is a reference to an external symbol, we want
3733 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3734 addu $tempreg,$tempreg,$gp
3735 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3736 <op> $treg,0($tempreg)
3738 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3740 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3741 <op> $treg,0($tempreg)
3742 If there is a base register, we add it to $tempreg before
3743 the <op>. If there is a constant, we stick it in the
3744 <op> instruction. We don't handle constants larger than
3745 16 bits, because we have no way to load the upper 16 bits
3746 (actually, we could handle them for the subset of cases
3747 in which we are not using $at). */
3748 assert (offset_expr
.X_op
== O_symbol
);
3749 expr1
.X_add_number
= offset_expr
.X_add_number
;
3750 offset_expr
.X_add_number
= 0;
3751 if (expr1
.X_add_number
< -0x8000
3752 || expr1
.X_add_number
>= 0x8000)
3753 as_bad ("PIC code offset overflow (max 16 signed bits)");
3754 if (reg_needs_delay (GP
))
3759 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3760 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3761 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3762 mips_isa
< 3 ? "addu" : "daddu",
3763 "d,v,t", tempreg
, tempreg
, GP
);
3764 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3765 mips_isa
< 3 ? "lw" : "ld",
3766 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3768 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3769 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
3770 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
3773 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3776 macro_build (p
, &icnt
, &offset_expr
,
3777 mips_isa
< 3 ? "lw" : "ld",
3778 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3780 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3782 macro_build (p
, &icnt
, &offset_expr
,
3783 mips_isa
< 3 ? "addiu" : "daddiu",
3784 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3786 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3787 mips_isa
< 3 ? "addu" : "daddu",
3788 "d,v,t", tempreg
, tempreg
, breg
);
3789 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
3790 (int) BFD_RELOC_LO16
, tempreg
);
3792 else if (mips_pic
== EMBEDDED_PIC
)
3794 /* If there is no base register, we want
3795 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3796 If there is a base register, we want
3797 addu $tempreg,$breg,$gp
3798 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
3800 assert (offset_expr
.X_op
== O_symbol
);
3803 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3804 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
3809 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3810 mips_isa
< 3 ? "addu" : "daddu",
3811 "d,v,t", tempreg
, breg
, GP
);
3812 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3813 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3826 load_register (&icnt
, treg
, &imm_expr
, 0);
3830 load_register (&icnt
, treg
, &imm_expr
, 1);
3834 if (imm_expr
.X_op
== O_constant
)
3836 load_register (&icnt
, AT
, &imm_expr
, 0);
3837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3838 "mtc1", "t,G", AT
, treg
);
3843 assert (offset_expr
.X_op
== O_symbol
3844 && strcmp (segment_name (S_GET_SEGMENT
3845 (offset_expr
.X_add_symbol
)),
3847 && offset_expr
.X_add_number
== 0);
3848 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3849 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3854 /* We know that sym is in the .rdata section. First we get the
3855 upper 16 bits of the address. */
3856 if (mips_pic
== NO_PIC
)
3858 /* FIXME: This won't work for a 64 bit address. */
3859 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3861 else if (mips_pic
== SVR4_PIC
)
3863 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3864 mips_isa
< 3 ? "lw" : "ld",
3865 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3867 else if (mips_pic
== EMBEDDED_PIC
)
3869 /* For embedded PIC we pick up the entire address off $gp in
3870 a single instruction. */
3871 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3872 mips_isa
< 3 ? "addiu" : "daddiu",
3873 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3874 offset_expr
.X_op
= O_constant
;
3875 offset_expr
.X_add_number
= 0;
3880 /* Now we load the register(s). */
3882 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
3883 treg
, (int) BFD_RELOC_LO16
, AT
);
3886 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3887 treg
, (int) BFD_RELOC_LO16
, AT
);
3890 /* FIXME: How in the world do we deal with the possible
3892 offset_expr
.X_add_number
+= 4;
3893 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3894 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3898 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3899 does not become a variant frag. */
3900 frag_wane (frag_now
);
3906 assert (offset_expr
.X_op
== O_symbol
3907 && offset_expr
.X_add_number
== 0);
3908 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
3909 if (strcmp (s
, ".lit8") == 0)
3913 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3914 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3918 r
= BFD_RELOC_MIPS_LITERAL
;
3923 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
3924 if (mips_pic
== SVR4_PIC
)
3925 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3926 mips_isa
< 3 ? "lw" : "ld",
3927 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3930 /* FIXME: This won't work for a 64 bit address. */
3931 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
3936 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3937 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
3939 /* To avoid confusion in tc_gen_reloc, we must ensure
3940 that this does not become a variant frag. */
3941 frag_wane (frag_now
);
3952 /* Even on a big endian machine $fn comes before $fn+1. We have
3953 to adjust when loading from memory. */
3956 assert (mips_isa
< 2);
3957 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3958 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3960 /* FIXME: A possible overflow which I don't know how to deal
3962 offset_expr
.X_add_number
+= 4;
3963 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3964 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3967 /* To avoid confusion in tc_gen_reloc, we must ensure that this
3968 does not become a variant frag. */
3969 frag_wane (frag_now
);
3978 * The MIPS assembler seems to check for X_add_number not
3979 * being double aligned and generating:
3982 * addiu at,at,%lo(foo+1)
3985 * But, the resulting address is the same after relocation so why
3986 * generate the extra instruction?
4033 if (offset_expr
.X_op
!= O_symbol
4034 && offset_expr
.X_op
!= O_constant
)
4036 as_bad ("expression too complex");
4037 offset_expr
.X_op
= O_constant
;
4040 /* Even on a big endian machine $fn comes before $fn+1. We have
4041 to adjust when loading from memory. We set coproc if we must
4042 load $fn+1 first. */
4043 if (byte_order
== LITTLE_ENDIAN
)
4046 if (mips_pic
== NO_PIC
4047 || offset_expr
.X_op
== O_constant
)
4049 /* If this is a reference to a GP relative symbol, we want
4050 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4051 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4052 If we have a base register, we use this
4054 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4055 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4056 If this is not a GP relative symbol, we want
4057 lui $at,<sym> (BFD_RELOC_HI16_S)
4058 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4059 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4060 If there is a base register, we add it to $at after the
4061 lui instruction. If there is a constant, we always use
4063 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4064 || nopic_need_relax (offset_expr
.X_add_symbol
))
4083 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4084 mips_isa
< 3 ? "addu" : "daddu",
4085 "d,v,t", AT
, breg
, GP
);
4091 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4092 coproc
? treg
+ 1 : treg
,
4093 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4094 offset_expr
.X_add_number
+= 4;
4096 /* Set mips_optimize to 2 to avoid inserting an
4098 hold_mips_optimize
= mips_optimize
;
4100 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4101 coproc
? treg
: treg
+ 1,
4102 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4103 mips_optimize
= hold_mips_optimize
;
4105 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4106 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4107 used_at
&& mips_noat
),
4108 offset_expr
.X_add_symbol
, (long) 0,
4111 /* We just generated two relocs. When tc_gen_reloc
4112 handles this case, it will skip the first reloc and
4113 handle the second. The second reloc already has an
4114 extra addend of 4, which we added above. We must
4115 subtract it out, and then subtract another 4 to make
4116 the first reloc come out right. The second reloc
4117 will come out right because we are going to add 4 to
4118 offset_expr when we build its instruction below. */
4119 offset_expr
.X_add_number
-= 8;
4120 offset_expr
.X_op
= O_constant
;
4122 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4127 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4128 mips_isa
< 3 ? "addu" : "daddu",
4129 "d,v,t", AT
, breg
, AT
);
4133 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4134 coproc
? treg
+ 1 : treg
,
4135 (int) BFD_RELOC_LO16
, AT
);
4138 /* FIXME: How do we handle overflow here? */
4139 offset_expr
.X_add_number
+= 4;
4140 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4141 coproc
? treg
: treg
+ 1,
4142 (int) BFD_RELOC_LO16
, AT
);
4144 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4148 /* If this is a reference to an external symbol, we want
4149 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4154 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4156 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4157 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4158 If there is a base register we add it to $at before the
4159 lwc1 instructions. If there is a constant we include it
4160 in the lwc1 instructions. */
4162 expr1
.X_add_number
= offset_expr
.X_add_number
;
4163 offset_expr
.X_add_number
= 0;
4164 if (expr1
.X_add_number
< -0x8000
4165 || expr1
.X_add_number
>= 0x8000 - 4)
4166 as_bad ("PIC code offset overflow (max 16 signed bits)");
4171 frag_grow (24 + off
);
4172 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4173 mips_isa
< 3 ? "lw" : "ld",
4174 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4175 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4177 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4178 mips_isa
< 3 ? "addu" : "daddu",
4179 "d,v,t", AT
, breg
, AT
);
4180 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4181 coproc
? treg
+ 1 : treg
,
4182 (int) BFD_RELOC_LO16
, AT
);
4183 expr1
.X_add_number
+= 4;
4185 /* Set mips_optimize to 2 to avoid inserting an undesired
4187 hold_mips_optimize
= mips_optimize
;
4189 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4190 coproc
? treg
: treg
+ 1,
4191 (int) BFD_RELOC_LO16
, AT
);
4192 mips_optimize
= hold_mips_optimize
;
4194 (void) frag_var (rs_machine_dependent
, 0, 0,
4195 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
4196 offset_expr
.X_add_symbol
, (long) 0,
4199 else if (mips_pic
== SVR4_PIC
)
4203 /* If this is a reference to an external symbol, we want
4204 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4206 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
4211 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4213 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4214 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4215 If there is a base register we add it to $at before the
4216 lwc1 instructions. If there is a constant we include it
4217 in the lwc1 instructions. */
4219 expr1
.X_add_number
= offset_expr
.X_add_number
;
4220 offset_expr
.X_add_number
= 0;
4221 if (expr1
.X_add_number
< -0x8000
4222 || expr1
.X_add_number
>= 0x8000 - 4)
4223 as_bad ("PIC code offset overflow (max 16 signed bits)");
4224 if (reg_needs_delay (GP
))
4233 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4234 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4235 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4236 mips_isa
< 3 ? "addu" : "daddu",
4237 "d,v,t", AT
, AT
, GP
);
4238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4239 mips_isa
< 3 ? "lw" : "ld",
4240 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
4241 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4243 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4244 mips_isa
< 3 ? "addu" : "daddu",
4245 "d,v,t", AT
, breg
, AT
);
4246 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4247 coproc
? treg
+ 1 : treg
,
4248 (int) BFD_RELOC_LO16
, AT
);
4249 expr1
.X_add_number
+= 4;
4251 /* Set mips_optimize to 2 to avoid inserting an undesired
4253 hold_mips_optimize
= mips_optimize
;
4255 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
4256 coproc
? treg
: treg
+ 1,
4257 (int) BFD_RELOC_LO16
, AT
);
4258 mips_optimize
= hold_mips_optimize
;
4259 expr1
.X_add_number
-= 4;
4261 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
4262 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
4263 8 + gpdel
+ off
, 1, 0),
4264 offset_expr
.X_add_symbol
, (long) 0,
4268 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4271 macro_build (p
, &icnt
, &offset_expr
,
4272 mips_isa
< 3 ? "lw" : "ld",
4273 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4275 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4279 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4280 mips_isa
< 3 ? "addu" : "daddu",
4281 "d,v,t", AT
, breg
, AT
);
4284 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4285 coproc
? treg
+ 1 : treg
,
4286 (int) BFD_RELOC_LO16
, AT
);
4288 expr1
.X_add_number
+= 4;
4290 /* Set mips_optimize to 2 to avoid inserting an undesired
4292 hold_mips_optimize
= mips_optimize
;
4294 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
4295 coproc
? treg
: treg
+ 1,
4296 (int) BFD_RELOC_LO16
, AT
);
4297 mips_optimize
= hold_mips_optimize
;
4299 else if (mips_pic
== EMBEDDED_PIC
)
4301 /* If there is no base register, we use
4302 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4303 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4304 If we have a base register, we use
4306 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4307 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4316 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4317 mips_isa
< 3 ? "addu" : "daddu",
4318 "d,v,t", AT
, breg
, GP
);
4323 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4324 coproc
? treg
+ 1 : treg
,
4325 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4326 offset_expr
.X_add_number
+= 4;
4327 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4328 coproc
? treg
: treg
+ 1,
4329 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4345 assert (mips_isa
< 3);
4346 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4347 (int) BFD_RELOC_LO16
, breg
);
4348 offset_expr
.X_add_number
+= 4;
4349 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
4350 (int) BFD_RELOC_LO16
, breg
);
4352 #ifdef LOSING_COMPILER
4358 as_warn ("Macro used $at after \".set noat\"");
4363 struct mips_cl_insn
*ip
;
4365 register int treg
, sreg
, dreg
, breg
;
4380 bfd_reloc_code_real_type r
;
4383 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4384 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4385 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4386 mask
= ip
->insn_mo
->mask
;
4388 expr1
.X_op
= O_constant
;
4389 expr1
.X_op_symbol
= NULL
;
4390 expr1
.X_add_symbol
= NULL
;
4391 expr1
.X_add_number
= 1;
4395 #endif /* LOSING_COMPILER */
4400 macro_build ((char *) NULL
, &icnt
, NULL
,
4401 dbl
? "dmultu" : "multu",
4403 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4409 /* The MIPS assembler some times generates shifts and adds. I'm
4410 not trying to be that fancy. GCC should do this for us
4412 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4413 macro_build ((char *) NULL
, &icnt
, NULL
,
4414 dbl
? "dmult" : "mult",
4416 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4422 mips_emit_delays ();
4424 mips_any_noreorder
= 1;
4425 macro_build ((char *) NULL
, &icnt
, NULL
,
4426 dbl
? "dmult" : "mult",
4428 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4429 macro_build ((char *) NULL
, &icnt
, NULL
,
4430 dbl
? "dsra32" : "sra",
4431 "d,w,<", dreg
, dreg
, 31);
4432 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4434 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
4437 expr1
.X_add_number
= 8;
4438 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
4439 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4440 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4443 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4449 mips_emit_delays ();
4451 mips_any_noreorder
= 1;
4452 macro_build ((char *) NULL
, &icnt
, NULL
,
4453 dbl
? "dmultu" : "multu",
4455 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
4456 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
4458 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
4461 expr1
.X_add_number
= 8;
4462 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
4463 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4464 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4470 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4471 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
4472 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
4474 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4478 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
4479 (int) (imm_expr
.X_add_number
& 0x1f));
4480 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
4481 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4482 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4486 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
4487 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
4488 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
4490 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4494 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
4495 (int) (imm_expr
.X_add_number
& 0x1f));
4496 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
4497 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
4498 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
4502 assert (mips_isa
< 2);
4503 /* Even on a big endian machine $fn comes before $fn+1. We have
4504 to adjust when storing to memory. */
4505 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4506 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
4507 (int) BFD_RELOC_LO16
, breg
);
4508 offset_expr
.X_add_number
+= 4;
4509 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
4510 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
4511 (int) BFD_RELOC_LO16
, breg
);
4516 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4517 treg
, (int) BFD_RELOC_LO16
);
4519 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4520 sreg
, (int) BFD_RELOC_LO16
);
4523 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4525 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4526 dreg
, (int) BFD_RELOC_LO16
);
4531 if (imm_expr
.X_add_number
== 0)
4533 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
4534 sreg
, (int) BFD_RELOC_LO16
);
4539 as_warn ("Instruction %s: result is always false",
4541 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4544 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4546 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
4547 sreg
, (int) BFD_RELOC_LO16
);
4550 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4552 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4553 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4554 mips_isa
< 3 ? "addiu" : "daddiu",
4555 "t,r,j", dreg
, sreg
,
4556 (int) BFD_RELOC_LO16
);
4561 load_register (&icnt
, AT
, &imm_expr
, 0);
4562 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4566 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
4567 (int) BFD_RELOC_LO16
);
4572 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
4578 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
4579 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4580 (int) BFD_RELOC_LO16
);
4583 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
4585 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4587 macro_build ((char *) NULL
, &icnt
, &expr1
,
4588 mask
== M_SGE_I
? "slti" : "sltiu",
4589 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4594 load_register (&icnt
, AT
, &imm_expr
, 0);
4595 macro_build ((char *) NULL
, &icnt
, NULL
,
4596 mask
== M_SGE_I
? "slt" : "sltu",
4597 "d,v,t", dreg
, sreg
, AT
);
4600 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4601 (int) BFD_RELOC_LO16
);
4606 case M_SGT
: /* sreg > treg <==> treg < sreg */
4612 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4615 case M_SGT_I
: /* sreg > I <==> I < sreg */
4621 load_register (&icnt
, AT
, &imm_expr
, 0);
4622 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4625 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
4631 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
4632 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4633 (int) BFD_RELOC_LO16
);
4636 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
4642 load_register (&icnt
, AT
, &imm_expr
, 0);
4643 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
4644 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
4645 (int) BFD_RELOC_LO16
);
4649 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4651 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
4652 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4655 load_register (&icnt
, AT
, &imm_expr
, 0);
4656 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
4660 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
4662 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
4663 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4666 load_register (&icnt
, AT
, &imm_expr
, 0);
4667 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
4673 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4676 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4680 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4682 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4688 if (imm_expr
.X_add_number
== 0)
4690 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
4696 as_warn ("Instruction %s: result is always true",
4698 macro_build ((char *) NULL
, &icnt
, &expr1
,
4699 mips_isa
< 3 ? "addiu" : "daddiu",
4700 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
4703 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
4705 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
4706 dreg
, sreg
, (int) BFD_RELOC_LO16
);
4709 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
4711 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4712 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4713 mips_isa
< 3 ? "addiu" : "daddiu",
4714 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4719 load_register (&icnt
, AT
, &imm_expr
, 0);
4720 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
4724 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
4732 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4734 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4735 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4736 dbl
? "daddi" : "addi",
4737 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4740 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4741 macro_build ((char *) NULL
, &icnt
, NULL
,
4742 dbl
? "dsub" : "sub",
4743 "d,v,t", dreg
, sreg
, AT
);
4749 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
4751 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
4752 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
4753 dbl
? "daddiu" : "addiu",
4754 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
4757 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4758 macro_build ((char *) NULL
, &icnt
, NULL
,
4759 dbl
? "dsubu" : "subu",
4760 "d,v,t", dreg
, sreg
, AT
);
4781 load_register (&icnt
, AT
, &imm_expr
, 0);
4782 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
4787 assert (mips_isa
< 2);
4788 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
4789 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
4792 * Is the double cfc1 instruction a bug in the mips assembler;
4793 * or is there a reason for it?
4795 mips_emit_delays ();
4797 mips_any_noreorder
= 1;
4798 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4799 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
4800 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4801 expr1
.X_add_number
= 3;
4802 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
4803 (int) BFD_RELOC_LO16
);
4804 expr1
.X_add_number
= 2;
4805 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
4806 (int) BFD_RELOC_LO16
);
4807 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
4808 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4809 macro_build ((char *) NULL
, &icnt
, NULL
,
4810 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
4811 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
4812 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
4822 if (offset_expr
.X_add_number
>= 0x7fff)
4823 as_bad ("operand overflow");
4824 /* avoid load delay */
4825 if (byte_order
== LITTLE_ENDIAN
)
4826 offset_expr
.X_add_number
+= 1;
4827 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4828 (int) BFD_RELOC_LO16
, breg
);
4829 if (byte_order
== LITTLE_ENDIAN
)
4830 offset_expr
.X_add_number
-= 1;
4832 offset_expr
.X_add_number
+= 1;
4833 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
4834 (int) BFD_RELOC_LO16
, breg
);
4835 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
4836 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
4849 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4850 as_bad ("operand overflow");
4851 if (byte_order
== LITTLE_ENDIAN
)
4852 offset_expr
.X_add_number
+= off
;
4853 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4854 (int) BFD_RELOC_LO16
, breg
);
4855 if (byte_order
== LITTLE_ENDIAN
)
4856 offset_expr
.X_add_number
-= off
;
4858 offset_expr
.X_add_number
+= off
;
4859 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4860 (int) BFD_RELOC_LO16
, breg
);
4873 load_address (&icnt
, AT
, &offset_expr
);
4875 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4876 mips_isa
< 3 ? "addu" : "daddu",
4877 "d,v,t", AT
, AT
, breg
);
4878 if (byte_order
== LITTLE_ENDIAN
)
4879 expr1
.X_add_number
= off
;
4881 expr1
.X_add_number
= 0;
4882 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4883 (int) BFD_RELOC_LO16
, AT
);
4884 if (byte_order
== LITTLE_ENDIAN
)
4885 expr1
.X_add_number
= 0;
4887 expr1
.X_add_number
= off
;
4888 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4889 (int) BFD_RELOC_LO16
, AT
);
4894 load_address (&icnt
, AT
, &offset_expr
);
4896 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4897 mips_isa
< 3 ? "addu" : "daddu",
4898 "d,v,t", AT
, AT
, breg
);
4899 if (byte_order
== BIG_ENDIAN
)
4900 expr1
.X_add_number
= 0;
4901 macro_build ((char *) NULL
, &icnt
, &expr1
,
4902 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
4903 (int) BFD_RELOC_LO16
, AT
);
4904 if (byte_order
== BIG_ENDIAN
)
4905 expr1
.X_add_number
= 1;
4907 expr1
.X_add_number
= 0;
4908 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
4909 (int) BFD_RELOC_LO16
, AT
);
4910 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
4912 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
4917 if (offset_expr
.X_add_number
>= 0x7fff)
4918 as_bad ("operand overflow");
4919 if (byte_order
== BIG_ENDIAN
)
4920 offset_expr
.X_add_number
+= 1;
4921 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
4922 (int) BFD_RELOC_LO16
, breg
);
4923 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
4924 if (byte_order
== BIG_ENDIAN
)
4925 offset_expr
.X_add_number
-= 1;
4927 offset_expr
.X_add_number
+= 1;
4928 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
4929 (int) BFD_RELOC_LO16
, breg
);
4942 if (offset_expr
.X_add_number
>= 0x8000 - off
)
4943 as_bad ("operand overflow");
4944 if (byte_order
== LITTLE_ENDIAN
)
4945 offset_expr
.X_add_number
+= off
;
4946 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
4947 (int) BFD_RELOC_LO16
, breg
);
4948 if (byte_order
== LITTLE_ENDIAN
)
4949 offset_expr
.X_add_number
-= off
;
4951 offset_expr
.X_add_number
+= off
;
4952 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
4953 (int) BFD_RELOC_LO16
, breg
);
4966 load_address (&icnt
, AT
, &offset_expr
);
4968 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4969 mips_isa
< 3 ? "addu" : "daddu",
4970 "d,v,t", AT
, AT
, breg
);
4971 if (byte_order
== LITTLE_ENDIAN
)
4972 expr1
.X_add_number
= off
;
4974 expr1
.X_add_number
= 0;
4975 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
4976 (int) BFD_RELOC_LO16
, AT
);
4977 if (byte_order
== LITTLE_ENDIAN
)
4978 expr1
.X_add_number
= 0;
4980 expr1
.X_add_number
= off
;
4981 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
4982 (int) BFD_RELOC_LO16
, AT
);
4986 load_address (&icnt
, AT
, &offset_expr
);
4988 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4989 mips_isa
< 3 ? "addu" : "daddu",
4990 "d,v,t", AT
, AT
, breg
);
4991 if (byte_order
== LITTLE_ENDIAN
)
4992 expr1
.X_add_number
= 0;
4993 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
4994 (int) BFD_RELOC_LO16
, AT
);
4995 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
4997 if (byte_order
== LITTLE_ENDIAN
)
4998 expr1
.X_add_number
= 1;
5000 expr1
.X_add_number
= 0;
5001 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5002 (int) BFD_RELOC_LO16
, AT
);
5003 if (byte_order
== LITTLE_ENDIAN
)
5004 expr1
.X_add_number
= 0;
5006 expr1
.X_add_number
= 1;
5007 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5008 (int) BFD_RELOC_LO16
, AT
);
5009 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5011 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5016 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5020 as_warn ("Macro used $at after \".set noat\"");
5023 /* This routine assembles an instruction into its binary format. As a
5024 side effect, it sets one of the global variables imm_reloc or
5025 offset_reloc to the type of relocation to do if one of the operands
5026 is an address expression. */
5031 struct mips_cl_insn
*ip
;
5036 struct mips_opcode
*insn
;
5039 unsigned int lastregno
= 0;
5044 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
5056 as_fatal ("Unknown opcode: `%s'", str
);
5058 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
5060 insn_error
= "unrecognized opcode";
5068 assert (strcmp (insn
->name
, str
) == 0);
5070 if (insn
->pinfo
== INSN_MACRO
)
5071 insn_isa
= insn
->match
;
5072 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
5074 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
5076 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
5081 if (insn_isa
> mips_isa
5082 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
5084 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
5086 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
5089 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
5090 && strcmp (insn
->name
, insn
[1].name
) == 0)
5095 insn_error
= "opcode not supported on this processor";
5100 ip
->insn_opcode
= insn
->match
;
5101 for (args
= insn
->args
;; ++args
)
5107 case '\0': /* end of args */
5120 ip
->insn_opcode
|= lastregno
<< 21;
5125 ip
->insn_opcode
|= lastregno
<< 16;
5129 ip
->insn_opcode
|= lastregno
<< 11;
5135 /* handle optional base register.
5136 Either the base register is omitted or
5137 we must have a left paren. */
5138 /* this is dependent on the next operand specifier
5139 is a 'b' for base register */
5140 assert (args
[1] == 'b');
5144 case ')': /* these must match exactly */
5149 case '<': /* must be at least one digit */
5151 * According to the manual, if the shift amount is greater
5152 * than 31 or less than 0 the the shift amount should be
5153 * mod 32. In reality the mips assembler issues an error.
5154 * We issue a warning and mask out all but the low 5 bits.
5156 my_getExpression (&imm_expr
, s
);
5157 check_absolute_expr (ip
, &imm_expr
);
5158 if ((unsigned long) imm_expr
.X_add_number
> 31)
5160 as_warn ("Improper shift amount (%ld)",
5161 (long) imm_expr
.X_add_number
);
5162 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
5164 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5165 imm_expr
.X_op
= O_absent
;
5169 case '>': /* shift amount minus 32 */
5170 my_getExpression (&imm_expr
, s
);
5171 check_absolute_expr (ip
, &imm_expr
);
5172 if ((unsigned long) imm_expr
.X_add_number
< 32
5173 || (unsigned long) imm_expr
.X_add_number
> 63)
5175 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
5176 imm_expr
.X_op
= O_absent
;
5180 case 'k': /* cache code */
5181 case 'h': /* prefx code */
5182 my_getExpression (&imm_expr
, s
);
5183 check_absolute_expr (ip
, &imm_expr
);
5184 if ((unsigned long) imm_expr
.X_add_number
> 31)
5186 as_warn ("Invalid value for `%s' (%lu)",
5188 (unsigned long) imm_expr
.X_add_number
);
5189 imm_expr
.X_add_number
&= 0x1f;
5192 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
5194 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
5195 imm_expr
.X_op
= O_absent
;
5199 case 'c': /* break code */
5200 my_getExpression (&imm_expr
, s
);
5201 check_absolute_expr (ip
, &imm_expr
);
5202 if ((unsigned) imm_expr
.X_add_number
> 1023)
5203 as_warn ("Illegal break code (%ld)",
5204 (long) imm_expr
.X_add_number
);
5205 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
5206 imm_expr
.X_op
= O_absent
;
5210 case 'B': /* syscall code */
5211 my_getExpression (&imm_expr
, s
);
5212 check_absolute_expr (ip
, &imm_expr
);
5213 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
5214 as_warn ("Illegal syscall code (%ld)",
5215 (long) imm_expr
.X_add_number
);
5216 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
5217 imm_expr
.X_op
= O_absent
;
5221 case 'C': /* Coprocessor code */
5222 my_getExpression (&imm_expr
, s
);
5223 check_absolute_expr (ip
, &imm_expr
);
5224 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
5226 as_warn ("Coproccesor code > 25 bits (%ld)",
5227 (long) imm_expr
.X_add_number
);
5228 imm_expr
.X_add_number
&= ((1<<25) - 1);
5230 ip
->insn_opcode
|= imm_expr
.X_add_number
;
5231 imm_expr
.X_op
= O_absent
;
5235 case 'b': /* base register */
5236 case 'd': /* destination register */
5237 case 's': /* source register */
5238 case 't': /* target register */
5239 case 'r': /* both target and source */
5240 case 'v': /* both dest and source */
5241 case 'w': /* both dest and target */
5242 case 'E': /* coprocessor target register */
5243 case 'G': /* coprocessor destination register */
5244 case 'x': /* ignore register name */
5245 case 'z': /* must be zero register */
5259 while (isdigit (*s
));
5261 as_bad ("Invalid register number (%d)", regno
);
5263 else if (*args
== 'E' || *args
== 'G')
5267 if (s
[1] == 'f' && s
[2] == 'p')
5272 else if (s
[1] == 's' && s
[2] == 'p')
5277 else if (s
[1] == 'g' && s
[2] == 'p')
5282 else if (s
[1] == 'a' && s
[2] == 't')
5287 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
5292 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
5304 as_warn ("Used $at without \".set noat\"");
5310 if (c
== 'r' || c
== 'v' || c
== 'w')
5317 /* 'z' only matches $0. */
5318 if (c
== 'z' && regno
!= 0)
5326 ip
->insn_opcode
|= regno
<< 21;
5330 ip
->insn_opcode
|= regno
<< 11;
5335 ip
->insn_opcode
|= regno
<< 16;
5338 /* This case exists because on the r3000 trunc
5339 expands into a macro which requires a gp
5340 register. On the r6000 or r4000 it is
5341 assembled into a single instruction which
5342 ignores the register. Thus the insn version
5343 is MIPS_ISA2 and uses 'x', and the macro
5344 version is MIPS_ISA1 and uses 't'. */
5347 /* This case is for the div instruction, which
5348 acts differently if the destination argument
5349 is $0. This only matches $0, and is checked
5350 outside the switch. */
5361 ip
->insn_opcode
|= lastregno
<< 21;
5364 ip
->insn_opcode
|= lastregno
<< 16;
5369 case 'D': /* floating point destination register */
5370 case 'S': /* floating point source register */
5371 case 'T': /* floating point target register */
5372 case 'R': /* floating point source register */
5376 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
5386 while (isdigit (*s
));
5389 as_bad ("Invalid float register number (%d)", regno
);
5391 if ((regno
& 1) != 0
5393 && ! (strcmp (str
, "mtc1") == 0 ||
5394 strcmp (str
, "mfc1") == 0 ||
5395 strcmp (str
, "lwc1") == 0 ||
5396 strcmp (str
, "swc1") == 0))
5397 as_warn ("Float register should be even, was %d",
5405 if (c
== 'V' || c
== 'W')
5415 ip
->insn_opcode
|= regno
<< 6;
5419 ip
->insn_opcode
|= regno
<< 11;
5423 ip
->insn_opcode
|= regno
<< 16;
5426 ip
->insn_opcode
|= regno
<< 21;
5435 ip
->insn_opcode
|= lastregno
<< 11;
5438 ip
->insn_opcode
|= lastregno
<< 16;
5444 my_getExpression (&imm_expr
, s
);
5445 if (imm_expr
.X_op
!= O_big
5446 && imm_expr
.X_op
!= O_constant
)
5447 insn_error
= "absolute expression required";
5452 my_getExpression (&offset_expr
, s
);
5453 imm_reloc
= BFD_RELOC_32
;
5465 unsigned char temp
[8];
5467 unsigned int length
;
5472 /* These only appear as the last operand in an
5473 instruction, and every instruction that accepts
5474 them in any variant accepts them in all variants.
5475 This means we don't have to worry about backing out
5476 any changes if the instruction does not match.
5478 The difference between them is the size of the
5479 floating point constant and where it goes. For 'F'
5480 and 'L' the constant is 64 bits; for 'f' and 'l' it
5481 is 32 bits. Where the constant is placed is based
5482 on how the MIPS assembler does things:
5485 f -- immediate value
5488 The .lit4 and .lit8 sections are only used if
5489 permitted by the -G argument.
5491 When generating embedded PIC code, we use the
5492 .lit8 section but not the .lit4 section (we can do
5493 .lit4 inline easily; we need to put .lit8
5494 somewhere in the data segment, and using .lit8
5495 permits the linker to eventually combine identical
5498 f64
= *args
== 'F' || *args
== 'L';
5500 save_in
= input_line_pointer
;
5501 input_line_pointer
= s
;
5502 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
5504 s
= input_line_pointer
;
5505 input_line_pointer
= save_in
;
5506 if (err
!= NULL
&& *err
!= '\0')
5508 as_bad ("Bad floating point constant: %s", err
);
5509 memset (temp
, '\0', sizeof temp
);
5510 length
= f64
? 8 : 4;
5513 assert (length
== (f64
? 8 : 4));
5517 && (! USE_GLOBAL_POINTER_OPT
5518 || mips_pic
== EMBEDDED_PIC
5519 || g_switch_value
< 4)
5522 imm_expr
.X_op
= O_constant
;
5523 if (byte_order
== LITTLE_ENDIAN
)
5524 imm_expr
.X_add_number
=
5525 (((((((int) temp
[3] << 8)
5530 imm_expr
.X_add_number
=
5531 (((((((int) temp
[0] << 8)
5538 const char *newname
;
5541 /* Switch to the right section. */
5543 subseg
= now_subseg
;
5546 default: /* unused default case avoids warnings. */
5548 newname
= RDATA_SECTION_NAME
;
5549 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
5553 newname
= RDATA_SECTION_NAME
;
5556 assert (!USE_GLOBAL_POINTER_OPT
5557 || g_switch_value
>= 4);
5561 new_seg
= subseg_new (newname
, (subsegT
) 0);
5562 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5563 bfd_set_section_flags (stdoutput
, new_seg
,
5568 frag_align (*args
== 'l' ? 2 : 3, 0);
5569 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
5570 record_alignment (new_seg
, 4);
5572 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
5574 as_bad ("Can't use floating point insn in this section");
5576 /* Set the argument to the current address in the
5578 offset_expr
.X_op
= O_symbol
;
5579 offset_expr
.X_add_symbol
=
5580 symbol_new ("L0\001", now_seg
,
5581 (valueT
) frag_now_fix (), frag_now
);
5582 offset_expr
.X_add_number
= 0;
5584 /* Put the floating point number into the section. */
5585 p
= frag_more ((int) length
);
5586 memcpy (p
, temp
, length
);
5588 /* Switch back to the original section. */
5589 subseg_set (seg
, subseg
);
5594 case 'i': /* 16 bit unsigned immediate */
5595 case 'j': /* 16 bit signed immediate */
5596 imm_reloc
= BFD_RELOC_LO16
;
5597 c
= my_getSmallExpression (&imm_expr
, s
);
5602 if (imm_expr
.X_op
== O_constant
)
5603 imm_expr
.X_add_number
=
5604 (imm_expr
.X_add_number
>> 16) & 0xffff;
5607 imm_reloc
= BFD_RELOC_HI16_S
;
5608 imm_unmatched_hi
= true;
5611 imm_reloc
= BFD_RELOC_HI16
;
5616 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5617 || imm_expr
.X_add_number
< 0
5618 || imm_expr
.X_add_number
>= 0x10000)
5620 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5621 !strcmp (insn
->name
, insn
[1].name
))
5623 if (imm_expr
.X_op
!= O_constant
5624 && imm_expr
.X_op
!= O_big
)
5625 insn_error
= "absolute expression required";
5627 as_bad ("16 bit expression not in range 0..65535");
5635 /* The upper bound should be 0x8000, but
5636 unfortunately the MIPS assembler accepts numbers
5637 from 0x8000 to 0xffff and sign extends them, and
5638 we want to be compatible. We only permit this
5639 extended range for an instruction which does not
5640 provide any further alternates, since those
5641 alternates may handle other cases. People should
5642 use the numbers they mean, rather than relying on
5643 a mysterious sign extension. */
5644 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5645 strcmp (insn
->name
, insn
[1].name
) == 0);
5650 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
5651 || imm_expr
.X_add_number
< -0x8000
5652 || imm_expr
.X_add_number
>= max
5654 && imm_expr
.X_add_number
< 0
5656 && imm_expr
.X_unsigned
5657 && sizeof (imm_expr
.X_add_number
) <= 4))
5661 if (imm_expr
.X_op
!= O_constant
5662 && imm_expr
.X_op
!= O_big
)
5663 insn_error
= "absolute expression required";
5665 as_bad ("16 bit expression not in range -32768..32767");
5671 case 'o': /* 16 bit offset */
5672 c
= my_getSmallExpression (&offset_expr
, s
);
5674 /* If this value won't fit into a 16 bit offset, then go
5675 find a macro that will generate the 32 bit offset
5676 code pattern. As a special hack, we accept the
5677 difference of two local symbols as a constant. This
5678 is required to suppose embedded PIC switches, which
5679 use an instruction which looks like
5680 lw $4,$L12-$LS12($4)
5681 The problem with handling this in a more general
5682 fashion is that the macro function doesn't expect to
5683 see anything which can be handled in a single
5684 constant instruction. */
5686 && (offset_expr
.X_op
!= O_constant
5687 || offset_expr
.X_add_number
>= 0x8000
5688 || offset_expr
.X_add_number
< -0x8000)
5689 && (mips_pic
!= EMBEDDED_PIC
5690 || offset_expr
.X_op
!= O_subtract
5691 || now_seg
!= text_section
5692 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
5696 offset_reloc
= BFD_RELOC_LO16
;
5697 if (c
== 'h' || c
== 'H')
5699 assert (offset_expr
.X_op
== O_constant
);
5700 offset_expr
.X_add_number
=
5701 (offset_expr
.X_add_number
>> 16) & 0xffff;
5706 case 'p': /* pc relative offset */
5707 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
5708 my_getExpression (&offset_expr
, s
);
5712 case 'u': /* upper 16 bits */
5713 c
= my_getSmallExpression (&imm_expr
, s
);
5714 if (imm_expr
.X_op
== O_constant
5715 && (imm_expr
.X_add_number
< 0
5716 || imm_expr
.X_add_number
>= 0x10000))
5717 as_bad ("lui expression not in range 0..65535");
5718 imm_reloc
= BFD_RELOC_LO16
;
5723 if (imm_expr
.X_op
== O_constant
)
5724 imm_expr
.X_add_number
=
5725 (imm_expr
.X_add_number
>> 16) & 0xffff;
5728 imm_reloc
= BFD_RELOC_HI16_S
;
5729 imm_unmatched_hi
= true;
5732 imm_reloc
= BFD_RELOC_HI16
;
5738 case 'a': /* 26 bit address */
5739 my_getExpression (&offset_expr
, s
);
5741 offset_reloc
= BFD_RELOC_MIPS_JMP
;
5744 case 'N': /* 3 bit branch condition code */
5745 case 'M': /* 3 bit compare condition code */
5746 my_getExpression (&imm_expr
, s
);
5747 check_absolute_expr (ip
, &imm_expr
);
5748 if ((unsigned long) imm_expr
.X_add_number
> 7)
5750 as_warn ("Condition code > 7 (%ld)",
5751 (long) imm_expr
.X_add_number
);
5752 imm_expr
.X_add_number
&= 7;
5755 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_BCC
;
5757 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CCC
;
5758 imm_expr
.X_op
= O_absent
;
5763 fprintf (stderr
, "bad char = '%c'\n", *args
);
5768 /* Args don't match. */
5769 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
5770 !strcmp (insn
->name
, insn
[1].name
))
5776 insn_error
= "illegal operands";
5785 my_getSmallExpression (ep
, str
)
5796 ((str
[1] == 'h' && str
[2] == 'i')
5797 || (str
[1] == 'H' && str
[2] == 'I')
5798 || (str
[1] == 'l' && str
[2] == 'o'))
5810 * A small expression may be followed by a base register.
5811 * Scan to the end of this operand, and then back over a possible
5812 * base register. Then scan the small expression up to that
5813 * point. (Based on code in sparc.c...)
5815 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
5817 if (sp
- 4 >= str
&& sp
[-1] == RP
)
5819 if (isdigit (sp
[-2]))
5821 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
5823 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
5829 else if (sp
- 5 >= str
5832 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
5833 || (sp
[-3] == 's' && sp
[-2] == 'p')
5834 || (sp
[-3] == 'g' && sp
[-2] == 'p')
5835 || (sp
[-3] == 'a' && sp
[-2] == 't')))
5841 /* no expression means zero offset */
5844 /* %xx(reg) is an error */
5845 ep
->X_op
= O_absent
;
5850 ep
->X_op
= O_constant
;
5853 ep
->X_add_symbol
= NULL
;
5854 ep
->X_op_symbol
= NULL
;
5855 ep
->X_add_number
= 0;
5860 my_getExpression (ep
, str
);
5867 my_getExpression (ep
, str
);
5868 return c
; /* => %hi or %lo encountered */
5872 my_getExpression (ep
, str
)
5878 save_in
= input_line_pointer
;
5879 input_line_pointer
= str
;
5881 expr_end
= input_line_pointer
;
5882 input_line_pointer
= save_in
;
5885 /* Turn a string in input_line_pointer into a floating point constant
5886 of type type, and store the appropriate bytes in *litP. The number
5887 of LITTLENUMS emitted is stored in *sizeP . An error message is
5888 returned, or NULL on OK. */
5891 md_atof (type
, litP
, sizeP
)
5897 LITTLENUM_TYPE words
[4];
5913 return "bad call to md_atof";
5916 t
= atof_ieee (input_line_pointer
, type
, words
);
5918 input_line_pointer
= t
;
5922 if (byte_order
== LITTLE_ENDIAN
)
5924 for (i
= prec
- 1; i
>= 0; i
--)
5926 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5932 for (i
= 0; i
< prec
; i
++)
5934 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5943 md_number_to_chars (buf
, val
, n
)
5951 number_to_chars_littleendian (buf
, val
, n
);
5955 number_to_chars_bigendian (buf
, val
, n
);
5963 CONST
char *md_shortopts
= "O::g::G:";
5965 struct option md_longopts
[] = {
5966 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
5967 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
5968 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
5969 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
5970 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
5971 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
5972 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
5973 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
5974 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
5975 #define OPTION_MCPU (OPTION_MD_BASE + 5)
5976 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
5977 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
5978 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
5979 #define OPTION_TRAP (OPTION_MD_BASE + 9)
5980 {"trap", no_argument
, NULL
, OPTION_TRAP
},
5981 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
5982 #define OPTION_BREAK (OPTION_MD_BASE + 10)
5983 {"break", no_argument
, NULL
, OPTION_BREAK
},
5984 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
5985 #define OPTION_EB (OPTION_MD_BASE + 11)
5986 {"EB", no_argument
, NULL
, OPTION_EB
},
5987 #define OPTION_EL (OPTION_MD_BASE + 12)
5988 {"EL", no_argument
, NULL
, OPTION_EL
},
5989 #define OPTION_M4650 (OPTION_MD_BASE + 13)
5990 {"m4650", no_argument
, NULL
, OPTION_M4650
},
5991 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
5992 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
5993 #define OPTION_M4010 (OPTION_MD_BASE + 15)
5994 {"m4010", no_argument
, NULL
, OPTION_M4010
},
5995 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
5996 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
5997 #define OPTION_M4100 (OPTION_MD_BASE + 17)
5998 {"m4100", no_argument
, NULL
, OPTION_M4100
},
5999 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
6000 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
6002 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
6003 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
6004 #define OPTION_XGOT (OPTION_MD_BASE + 19)
6005 #define OPTION_32 (OPTION_MD_BASE + 20)
6006 #define OPTION_64 (OPTION_MD_BASE + 21)
6008 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
6009 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
6010 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
6011 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
6012 {"32", no_argument
, NULL
, OPTION_32
},
6013 {"64", no_argument
, NULL
, OPTION_64
},
6016 {NULL
, no_argument
, NULL
, 0}
6018 size_t md_longopts_size
= sizeof(md_longopts
);
6021 md_parse_option (c
, arg
)
6036 target_big_endian
= 1;
6040 target_big_endian
= 0;
6044 if (arg
&& arg
[1] == '0')
6054 mips_debug
= atoi (arg
);
6055 /* When the MIPS assembler sees -g or -g2, it does not do
6056 optimizations which limit full symbolic debugging. We take
6057 that to be equivalent to -O0. */
6058 if (mips_debug
== 2)
6090 /* Identify the processor type */
6092 if (strcmp (p
, "default") == 0
6093 || strcmp (p
, "DEFAULT") == 0)
6099 /* We need to cope with the various "vr" prefixes for the 4300
6101 if (*p
== 'v' || *p
== 'V')
6107 if (*p
== 'r' || *p
== 'R')
6114 if (strcmp (p
, "10000") == 0
6115 || strcmp (p
, "10k") == 0
6116 || strcmp (p
, "10K") == 0)
6121 if (strcmp (p
, "2000") == 0
6122 || strcmp (p
, "2k") == 0
6123 || strcmp (p
, "2K") == 0)
6128 if (strcmp (p
, "3000") == 0
6129 || strcmp (p
, "3k") == 0
6130 || strcmp (p
, "3K") == 0)
6135 if (strcmp (p
, "4000") == 0
6136 || strcmp (p
, "4k") == 0
6137 || strcmp (p
, "4K") == 0)
6139 else if (strcmp (p
, "4100") == 0)
6145 else if (strcmp (p
, "4300") == 0)
6147 else if (strcmp (p
, "4400") == 0)
6149 else if (strcmp (p
, "4600") == 0)
6151 else if (strcmp (p
, "4650") == 0)
6157 else if (strcmp (p
, "4010") == 0)
6166 if (strcmp (p
, "6000") == 0
6167 || strcmp (p
, "6k") == 0
6168 || strcmp (p
, "6K") == 0)
6173 if (strcmp (p
, "8000") == 0
6174 || strcmp (p
, "8k") == 0
6175 || strcmp (p
, "8K") == 0)
6180 if (strcmp (p
, "orion") == 0)
6185 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100)
6187 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
6193 as_bad ("invalid architecture -mcpu=%s", arg
);
6204 case OPTION_NO_M4650
:
6212 case OPTION_NO_M4010
:
6220 case OPTION_NO_M4100
:
6224 case OPTION_MEMBEDDED_PIC
:
6225 mips_pic
= EMBEDDED_PIC
;
6226 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
6228 as_bad ("-G may not be used with embedded PIC code");
6231 g_switch_value
= 0x7fffffff;
6234 /* When generating ELF code, we permit -KPIC and -call_shared to
6235 select SVR4_PIC, and -non_shared to select no PIC. This is
6236 intended to be compatible with Irix 5. */
6237 case OPTION_CALL_SHARED
:
6238 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6240 as_bad ("-call_shared is supported only for ELF format");
6243 mips_pic
= SVR4_PIC
;
6244 if (g_switch_seen
&& g_switch_value
!= 0)
6246 as_bad ("-G may not be used with SVR4 PIC code");
6252 case OPTION_NON_SHARED
:
6253 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
6255 as_bad ("-non_shared is supported only for ELF format");
6261 /* The -xgot option tells the assembler to use 32 offsets when
6262 accessing the got in SVR4_PIC mode. It is for Irix
6269 if (! USE_GLOBAL_POINTER_OPT
)
6271 as_bad ("-G is not supported for this configuration");
6274 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
6276 as_bad ("-G may not be used with SVR4 or embedded PIC code");
6280 g_switch_value
= atoi (arg
);
6284 /* The -32 and -64 options tell the assembler to output the 32
6285 bit or the 64 bit MIPS ELF format. */
6292 const char **list
, **l
;
6294 list
= bfd_target_list ();
6295 for (l
= list
; *l
!= NULL
; l
++)
6296 if (strcmp (*l
, "elf64-bigmips") == 0
6297 || strcmp (*l
, "elf64-littlemips") == 0)
6300 as_fatal ("No compiled in support for 64 bit object file format");
6314 md_show_usage (stream
)
6319 -membedded-pic generate embedded position independent code\n\
6320 -EB generate big endian output\n\
6321 -EL generate little endian output\n\
6322 -g, -g2 do not remove uneeded NOPs or swap branches\n\
6323 -G NUM allow referencing objects up to NUM bytes\n\
6324 implicitly with the gp register [default 8]\n");
6326 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
6327 -mips2, -mcpu=r6000 generate code for r6000\n\
6328 -mips3, -mcpu=r4000 generate code for r4000\n\
6329 -mips4, -mcpu=r8000 generate code for r8000\n\
6330 -mcpu=vr4300 generate code for vr4300\n\
6331 -mcpu=vr4100 generate code for vr4100\n\
6332 -m4650 permit R4650 instructions\n\
6333 -no-m4650 do not permit R4650 instructions\n\
6334 -m4010 permit R4010 instructions\n\
6335 -no-m4010 do not permit R4010 instructions\n\
6336 -m4100 permit VR4100 instructions\n\
6337 -no-m4100 do not permit VR4100 instructions\n");
6339 -O0 remove unneeded NOPs, do not swap branches\n\
6340 -O remove unneeded NOPs and swap branches\n\
6341 --trap, --no-break trap exception on div by 0 and mult overflow\n\
6342 --break, --no-trap break exception on div by 0 and mult overflow\n");
6345 -KPIC, -call_shared generate SVR4 position independent code\n\
6346 -non_shared do not generate position independent code\n\
6347 -xgot assume a 32 bit GOT\n\
6348 -32 create 32 bit object file (default)\n\
6349 -64 create 64 bit object file\n");
6354 mips_init_after_args ()
6356 if (target_big_endian
)
6357 byte_order
= BIG_ENDIAN
;
6359 byte_order
= LITTLE_ENDIAN
;
6363 md_pcrel_from (fixP
)
6366 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
6367 && fixP
->fx_addsy
!= (symbolS
*) NULL
6368 && ! S_IS_DEFINED (fixP
->fx_addsy
))
6370 /* This makes a branch to an undefined symbol be a branch to the
6371 current location. */
6375 /* return the address of the delay slot */
6376 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
6379 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
6380 reloc for a cons. We could use the definition there, except that
6381 we want to handle 64 bit relocs specially. */
6384 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
6387 unsigned int nbytes
;
6390 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
6392 if (nbytes
== 8 && ! mips_64
)
6394 if (byte_order
== BIG_ENDIAN
)
6399 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
6400 as_bad ("Unsupported reloc size %d", nbytes
);
6402 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
6405 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
6408 /* Sort any unmatched HI16_S relocs so that they immediately precede
6409 the corresponding LO reloc. This is called before md_apply_fix and
6410 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
6411 explicit use of the %hi modifier. */
6416 struct mips_hi_fixup
*l
;
6418 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
6420 segment_info_type
*seginfo
;
6423 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
6425 /* Check quickly whether the next fixup happens to be a matching
6427 if (l
->fixp
->fx_next
!= NULL
6428 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
6429 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
6430 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
6433 /* Look through the fixups for this segment for a matching %lo.
6434 When we find one, move the %hi just in front of it. We do
6435 this in two passes. In the first pass, we try to find a
6436 unique %lo. In the second pass, we permit multiple %hi
6437 relocs for a single %lo (this is a GNU extension). */
6438 seginfo
= seg_info (l
->seg
);
6439 for (pass
= 0; pass
< 2; pass
++)
6444 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
6446 /* Check whether this is a %lo fixup which matches l->fixp. */
6447 if (f
->fx_r_type
== BFD_RELOC_LO16
6448 && f
->fx_addsy
== l
->fixp
->fx_addsy
6449 && f
->fx_offset
== l
->fixp
->fx_offset
6452 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
6453 || prev
->fx_addsy
!= f
->fx_addsy
6454 || prev
->fx_offset
!= f
->fx_offset
))
6458 /* Move l->fixp before f. */
6459 for (pf
= &seginfo
->fix_root
;
6461 pf
= &(*pf
)->fx_next
)
6462 assert (*pf
!= NULL
);
6464 *pf
= l
->fixp
->fx_next
;
6466 l
->fixp
->fx_next
= f
;
6468 seginfo
->fix_root
= l
->fixp
;
6470 prev
->fx_next
= l
->fixp
;
6482 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
6483 "Unmatched %%hi reloc");
6488 /* When generating embedded PIC code we need to use a special
6489 relocation to represent the difference of two symbols in the .text
6490 section (switch tables use a difference of this sort). See
6491 include/coff/mips.h for details. This macro checks whether this
6492 fixup requires the special reloc. */
6493 #define SWITCH_TABLE(fixp) \
6494 ((fixp)->fx_r_type == BFD_RELOC_32 \
6495 && (fixp)->fx_addsy != NULL \
6496 && (fixp)->fx_subsy != NULL \
6497 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
6498 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
6500 /* When generating embedded PIC code we must keep all PC relative
6501 relocations, in case the linker has to relax a call. We also need
6502 to keep relocations for switch table entries. */
6506 mips_force_relocation (fixp
)
6509 return (mips_pic
== EMBEDDED_PIC
6511 || SWITCH_TABLE (fixp
)
6512 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
6513 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
6516 /* Apply a fixup to the object file. */
6519 md_apply_fix (fixP
, valueP
)
6526 assert (fixP
->fx_size
== 4 || fixP
->fx_r_type
== BFD_RELOC_16
);
6529 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
6531 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
6534 switch (fixP
->fx_r_type
)
6536 case BFD_RELOC_MIPS_JMP
:
6537 case BFD_RELOC_HI16
:
6538 case BFD_RELOC_HI16_S
:
6539 case BFD_RELOC_MIPS_GPREL
:
6540 case BFD_RELOC_MIPS_LITERAL
:
6541 case BFD_RELOC_MIPS_CALL16
:
6542 case BFD_RELOC_MIPS_GOT16
:
6543 case BFD_RELOC_MIPS_GPREL32
:
6544 case BFD_RELOC_MIPS_GOT_HI16
:
6545 case BFD_RELOC_MIPS_GOT_LO16
:
6546 case BFD_RELOC_MIPS_CALL_HI16
:
6547 case BFD_RELOC_MIPS_CALL_LO16
:
6549 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6550 "Invalid PC relative reloc");
6551 /* Nothing needed to do. The value comes from the reloc entry */
6554 case BFD_RELOC_PCREL_HI16_S
:
6555 /* The addend for this is tricky if it is internal, so we just
6556 do everything here rather than in bfd_perform_relocation. */
6557 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6559 /* For an external symbol adjust by the address to make it
6560 pcrel_offset. We use the address of the RELLO reloc
6561 which follows this one. */
6562 value
+= (fixP
->fx_next
->fx_frag
->fr_address
6563 + fixP
->fx_next
->fx_where
);
6568 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6569 if (byte_order
== BIG_ENDIAN
)
6571 md_number_to_chars (buf
, value
, 2);
6574 case BFD_RELOC_PCREL_LO16
:
6575 /* The addend for this is tricky if it is internal, so we just
6576 do everything here rather than in bfd_perform_relocation. */
6577 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
6578 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
6579 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6580 if (byte_order
== BIG_ENDIAN
)
6582 md_number_to_chars (buf
, value
, 2);
6586 /* If we are deleting this reloc entry, we must fill in the
6587 value now. This can happen if we have a .word which is not
6588 resolved when it appears but is later defined. We also need
6589 to fill in the value if this is an embedded PIC switch table
6592 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
6593 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6598 /* If we are deleting this reloc entry, we must fill in the
6600 assert (fixP
->fx_size
== 2);
6602 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
6606 case BFD_RELOC_LO16
:
6607 /* When handling an embedded PIC switch statement, we can wind
6608 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
6611 if (value
< -0x8000 || value
> 0x7fff)
6612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6613 "relocation overflow");
6614 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
6615 if (byte_order
== BIG_ENDIAN
)
6617 md_number_to_chars (buf
, value
, 2);
6621 case BFD_RELOC_16_PCREL_S2
:
6623 * We need to save the bits in the instruction since fixup_segment()
6624 * might be deleting the relocation entry (i.e., a branch within
6625 * the current segment).
6628 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
6629 "Branch to odd address (%lx)", value
);
6632 /* update old instruction data */
6633 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
6637 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
6641 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
6649 if (value
>= -0x8000 && value
< 0x8000)
6650 insn
|= value
& 0xffff;
6653 /* The branch offset is too large. If this is an
6654 unconditional branch, and we are not generating PIC code,
6655 we can convert it to an absolute jump instruction. */
6656 if (mips_pic
== NO_PIC
6658 && fixP
->fx_frag
->fr_address
>= text_section
->vma
6659 && (fixP
->fx_frag
->fr_address
6660 < text_section
->vma
+ text_section
->_raw_size
)
6661 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
6662 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
6663 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
6665 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
6666 insn
= 0x0c000000; /* jal */
6668 insn
= 0x08000000; /* j */
6669 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
6671 fixP
->fx_addsy
= section_symbol (text_section
);
6672 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
6676 /* FIXME. It would be possible in principle to handle
6677 conditional branches which overflow. They could be
6678 transformed into a branch around a jump. This would
6679 require setting up variant frags for each different
6680 branch type. The native MIPS assembler attempts to
6681 handle these cases, but it appears to do it
6683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6684 "Relocation overflow");
6688 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
6703 const struct mips_opcode
*p
;
6704 int treg
, sreg
, dreg
, shamt
;
6709 for (i
= 0; i
< NUMOPCODES
; ++i
)
6711 p
= &mips_opcodes
[i
];
6712 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
6714 printf ("%08lx %s\t", oc
, p
->name
);
6715 treg
= (oc
>> 16) & 0x1f;
6716 sreg
= (oc
>> 21) & 0x1f;
6717 dreg
= (oc
>> 11) & 0x1f;
6718 shamt
= (oc
>> 6) & 0x1f;
6720 for (args
= p
->args
;; ++args
)
6731 printf ("%c", *args
);
6735 assert (treg
== sreg
);
6736 printf ("$%d,$%d", treg
, sreg
);
6741 printf ("$%d", dreg
);
6746 printf ("$%d", treg
);
6750 printf ("0x%x", treg
);
6755 printf ("$%d", sreg
);
6759 printf ("0x%08lx", oc
& 0x1ffffff);
6771 printf ("$%d", shamt
);
6782 printf ("%08lx UNDEFINED\n", oc
);
6793 name
= input_line_pointer
;
6794 c
= get_symbol_end ();
6795 p
= (symbolS
*) symbol_find_or_make (name
);
6796 *input_line_pointer
= c
;
6800 /* Align the current frag to a given power of two. The MIPS assembler
6801 also automatically adjusts any preceding label. */
6804 mips_align (to
, fill
, label
)
6809 mips_emit_delays ();
6810 frag_align (to
, fill
);
6811 record_alignment (now_seg
, to
);
6814 assert (S_GET_SEGMENT (label
) == now_seg
);
6815 label
->sy_frag
= frag_now
;
6816 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
6820 /* Align to a given power of two. .align 0 turns off the automatic
6821 alignment used by the data creating pseudo-ops. */
6828 register long temp_fill
;
6829 long max_alignment
= 15;
6833 o Note that the assembler pulls down any immediately preceeding label
6834 to the aligned address.
6835 o It's not documented but auto alignment is reinstated by
6836 a .align pseudo instruction.
6837 o Note also that after auto alignment is turned off the mips assembler
6838 issues an error on attempt to assemble an improperly aligned data item.
6843 temp
= get_absolute_expression ();
6844 if (temp
> max_alignment
)
6845 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
6848 as_warn ("Alignment negative: 0 assumed.");
6851 if (*input_line_pointer
== ',')
6853 input_line_pointer
++;
6854 temp_fill
= get_absolute_expression ();
6861 mips_align (temp
, (int) temp_fill
, insn_label
);
6868 demand_empty_rest_of_line ();
6872 mips_flush_pending_output ()
6874 mips_emit_delays ();
6884 /* When generating embedded PIC code, we only use the .text, .lit8,
6885 .sdata and .sbss sections. We change the .data and .rdata
6886 pseudo-ops to use .sdata. */
6887 if (mips_pic
== EMBEDDED_PIC
6888 && (sec
== 'd' || sec
== 'r'))
6891 mips_emit_delays ();
6901 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
6902 demand_empty_rest_of_line ();
6906 if (USE_GLOBAL_POINTER_OPT
)
6908 seg
= subseg_new (RDATA_SECTION_NAME
,
6909 (subsegT
) get_absolute_expression ());
6910 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6912 bfd_set_section_flags (stdoutput
, seg
,
6918 bfd_set_section_alignment (stdoutput
, seg
, 4);
6920 demand_empty_rest_of_line ();
6924 as_bad ("No read only data section in this object file format");
6925 demand_empty_rest_of_line ();
6931 if (USE_GLOBAL_POINTER_OPT
)
6933 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
6934 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6936 bfd_set_section_flags (stdoutput
, seg
,
6937 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
6939 bfd_set_section_alignment (stdoutput
, seg
, 4);
6941 demand_empty_rest_of_line ();
6946 as_bad ("Global pointers not supported; recompile -G 0");
6947 demand_empty_rest_of_line ();
6956 mips_enable_auto_align ()
6968 mips_emit_delays ();
6969 if (log_size
> 0 && auto_align
)
6970 mips_align (log_size
, 0, label
);
6972 cons (1 << log_size
);
6983 mips_emit_delays ();
6987 mips_align (3, 0, label
);
6989 mips_align (2, 0, label
);
6996 /* Handle .globl. We need to override it because on Irix 5 you are
6999 where foo is an undefined symbol, to mean that foo should be
7000 considered to be the address of a function. */
7011 name
= input_line_pointer
;
7012 c
= get_symbol_end ();
7013 symbolP
= symbol_find_or_make (name
);
7014 *input_line_pointer
= c
;
7017 /* On Irix 5, every global symbol that is not explicitly labelled as
7018 being a function is apparently labelled as being an object. */
7021 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
7026 secname
= input_line_pointer
;
7027 c
= get_symbol_end ();
7028 sec
= bfd_get_section_by_name (stdoutput
, secname
);
7030 as_bad ("%s: no such section", secname
);
7031 *input_line_pointer
= c
;
7033 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
7034 flag
= BSF_FUNCTION
;
7037 symbolP
->bsym
->flags
|= flag
;
7039 S_SET_EXTERNAL (symbolP
);
7040 demand_empty_rest_of_line ();
7050 opt
= input_line_pointer
;
7051 c
= get_symbol_end ();
7055 /* FIXME: What does this mean? */
7057 else if (strncmp (opt
, "pic", 3) == 0)
7065 mips_pic
= SVR4_PIC
;
7067 as_bad (".option pic%d not supported", i
);
7069 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
7071 if (g_switch_seen
&& g_switch_value
!= 0)
7072 as_warn ("-G may not be used with SVR4 PIC code");
7074 bfd_set_gp_size (stdoutput
, 0);
7078 as_warn ("Unrecognized option \"%s\"", opt
);
7080 *input_line_pointer
= c
;
7081 demand_empty_rest_of_line ();
7088 char *name
= input_line_pointer
, ch
;
7090 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7091 input_line_pointer
++;
7092 ch
= *input_line_pointer
;
7093 *input_line_pointer
= '\0';
7095 if (strcmp (name
, "reorder") == 0)
7099 prev_insn_unreordered
= 1;
7100 prev_prev_insn_unreordered
= 1;
7104 else if (strcmp (name
, "noreorder") == 0)
7106 mips_emit_delays ();
7108 mips_any_noreorder
= 1;
7110 else if (strcmp (name
, "at") == 0)
7114 else if (strcmp (name
, "noat") == 0)
7118 else if (strcmp (name
, "macro") == 0)
7120 mips_warn_about_macros
= 0;
7122 else if (strcmp (name
, "nomacro") == 0)
7124 if (mips_noreorder
== 0)
7125 as_bad ("`noreorder' must be set before `nomacro'");
7126 mips_warn_about_macros
= 1;
7128 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
7132 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
7136 else if (strcmp (name
, "bopt") == 0)
7140 else if (strcmp (name
, "nobopt") == 0)
7144 else if (strncmp (name
, "mips", 4) == 0)
7148 /* Permit the user to change the ISA on the fly. Needless to
7149 say, misuse can cause serious problems. */
7150 isa
= atoi (name
+ 4);
7152 mips_isa
= file_mips_isa
;
7153 else if (isa
< 1 || isa
> 4)
7154 as_bad ("unknown ISA level");
7160 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
7162 *input_line_pointer
= ch
;
7163 demand_empty_rest_of_line ();
7166 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
7167 .option pic2. It means to generate SVR4 PIC calls. */
7173 mips_pic
= SVR4_PIC
;
7174 if (USE_GLOBAL_POINTER_OPT
)
7176 if (g_switch_seen
&& g_switch_value
!= 0)
7177 as_warn ("-G may not be used with SVR4 PIC code");
7180 bfd_set_gp_size (stdoutput
, 0);
7181 demand_empty_rest_of_line ();
7184 /* Handle the .cpload pseudo-op. This is used when generating SVR4
7185 PIC code. It sets the $gp register for the function based on the
7186 function address, which is in the register named in the argument.
7187 This uses a relocation against _gp_disp, which is handled specially
7188 by the linker. The result is:
7189 lui $gp,%hi(_gp_disp)
7190 addiu $gp,$gp,%lo(_gp_disp)
7191 addu $gp,$gp,.cpload argument
7192 The .cpload argument is normally $25 == $t9. */
7201 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
7202 if (mips_pic
!= SVR4_PIC
)
7208 /* .cpload should be a in .set noreorder section. */
7209 if (mips_noreorder
== 0)
7210 as_warn (".cpload not in noreorder section");
7213 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
7214 ex
.X_op_symbol
= NULL
;
7215 ex
.X_add_number
= 0;
7217 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
7218 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
7220 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
7221 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
7222 (int) BFD_RELOC_LO16
);
7224 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
7225 GP
, GP
, tc_get_register (0));
7227 demand_empty_rest_of_line ();
7230 /* Handle the .cprestore pseudo-op. This stores $gp into a given
7231 offset from $sp. The offset is remembered, and after making a PIC
7232 call $gp is restored from that location. */
7235 s_cprestore (ignore
)
7241 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
7242 if (mips_pic
!= SVR4_PIC
)
7248 mips_cprestore_offset
= get_absolute_expression ();
7250 ex
.X_op
= O_constant
;
7251 ex
.X_add_symbol
= NULL
;
7252 ex
.X_op_symbol
= NULL
;
7253 ex
.X_add_number
= mips_cprestore_offset
;
7255 macro_build ((char *) NULL
, &icnt
, &ex
,
7256 mips_isa
< 3 ? "sw" : "sd",
7257 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
7259 demand_empty_rest_of_line ();
7262 /* Handle the .gpword pseudo-op. This is used when generating PIC
7263 code. It generates a 32 bit GP relative reloc. */
7273 /* When not generating PIC code, this is treated as .word. */
7274 if (mips_pic
!= SVR4_PIC
)
7281 mips_emit_delays ();
7283 mips_align (2, 0, label
);
7288 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
7290 as_bad ("Unsupported use of .gpword");
7291 ignore_rest_of_line ();
7295 md_number_to_chars (p
, (valueT
) 0, 4);
7296 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
7297 BFD_RELOC_MIPS_GPREL32
);
7299 demand_empty_rest_of_line ();
7302 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
7303 tables in SVR4 PIC code. */
7312 /* This is ignored when not generating SVR4 PIC code. */
7313 if (mips_pic
!= SVR4_PIC
)
7319 /* Add $gp to the register named as an argument. */
7320 reg
= tc_get_register (0);
7321 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
7322 mips_isa
< 3 ? "addu" : "daddu",
7323 "d,v,t", reg
, reg
, GP
);
7325 demand_empty_rest_of_line ();
7328 /* Parse a register string into a number. Called from the ECOFF code
7329 to parse .frame. The argument is non-zero if this is the frame
7330 register, so that we can record it in mips_frame_reg. */
7333 tc_get_register (frame
)
7339 if (*input_line_pointer
++ != '$')
7341 as_warn ("expected `$'");
7344 else if (isdigit ((unsigned char) *input_line_pointer
))
7346 reg
= get_absolute_expression ();
7347 if (reg
< 0 || reg
>= 32)
7349 as_warn ("Bad register number");
7355 if (strncmp (input_line_pointer
, "fp", 2) == 0)
7357 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
7359 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
7361 else if (strncmp (input_line_pointer
, "at", 2) == 0)
7365 as_warn ("Unrecognized register name");
7368 input_line_pointer
+= 2;
7371 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
7376 md_section_align (seg
, addr
)
7380 int align
= bfd_get_section_alignment (stdoutput
, seg
);
7382 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
7385 /* Utility routine, called from above as well. If called while the
7386 input file is still being read, it's only an approximation. (For
7387 example, a symbol may later become defined which appeared to be
7388 undefined earlier.) */
7391 nopic_need_relax (sym
)
7397 if (USE_GLOBAL_POINTER_OPT
)
7399 const char *symname
;
7402 /* Find out whether this symbol can be referenced off the GP
7403 register. It can be if it is smaller than the -G size or if
7404 it is in the .sdata or .sbss section. Certain symbols can
7405 not be referenced off the GP, although it appears as though
7407 symname
= S_GET_NAME (sym
);
7408 if (symname
!= (const char *) NULL
7409 && (strcmp (symname
, "eprol") == 0
7410 || strcmp (symname
, "etext") == 0
7411 || strcmp (symname
, "_gp") == 0
7412 || strcmp (symname
, "edata") == 0
7413 || strcmp (symname
, "_fbss") == 0
7414 || strcmp (symname
, "_fdata") == 0
7415 || strcmp (symname
, "_ftext") == 0
7416 || strcmp (symname
, "end") == 0
7417 || strcmp (symname
, "_gp_disp") == 0))
7419 else if (! S_IS_DEFINED (sym
)
7421 #ifndef NO_ECOFF_DEBUGGING
7422 || (sym
->ecoff_extern_size
!= 0
7423 && sym
->ecoff_extern_size
<= g_switch_value
)
7425 || (S_GET_VALUE (sym
) != 0
7426 && S_GET_VALUE (sym
) <= g_switch_value
)))
7430 const char *segname
;
7432 segname
= segment_name (S_GET_SEGMENT (sym
));
7433 assert (strcmp (segname
, ".lit8") != 0
7434 && strcmp (segname
, ".lit4") != 0);
7435 change
= (strcmp (segname
, ".sdata") != 0
7436 && strcmp (segname
, ".sbss") != 0);
7441 /* We are not optimizing for the GP register. */
7445 /* Estimate the size of a frag before relaxing. We are not really
7446 relaxing here, and the final size is encoded in the subtype
7451 md_estimate_size_before_relax (fragp
, segtype
)
7457 if (mips_pic
== NO_PIC
)
7459 change
= nopic_need_relax (fragp
->fr_symbol
);
7461 else if (mips_pic
== SVR4_PIC
)
7463 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
7465 /* This must duplicate the test in adjust_reloc_syms. */
7466 change
= (symsec
!= &bfd_und_section
7467 && symsec
!= &bfd_abs_section
7468 && ! bfd_is_com_section (symsec
));
7475 /* Record the offset to the first reloc in the fr_opcode field.
7476 This lets md_convert_frag and tc_gen_reloc know that the code
7477 must be expanded. */
7478 fragp
->fr_opcode
= (fragp
->fr_literal
7480 - RELAX_OLD (fragp
->fr_subtype
)
7481 + RELAX_RELOC1 (fragp
->fr_subtype
));
7482 /* FIXME: This really needs as_warn_where. */
7483 if (RELAX_WARN (fragp
->fr_subtype
))
7484 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
7490 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
7493 /* Translate internal representation of relocation info to BFD target
7497 tc_gen_reloc (section
, fixp
)
7501 static arelent
*retval
[4];
7504 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
7507 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7508 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7510 if (mips_pic
== EMBEDDED_PIC
7511 && SWITCH_TABLE (fixp
))
7513 /* For a switch table entry we use a special reloc. The addend
7514 is actually the difference between the reloc address and the
7516 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7517 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
7518 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
7519 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
7521 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
7523 /* We use a special addend for an internal RELLO reloc. */
7524 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7525 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
7527 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
7529 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
7531 assert (fixp
->fx_next
!= NULL
7532 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
7533 /* We use a special addend for an internal RELHI reloc. The
7534 reloc is relative to the RELLO; adjust the addend
7536 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
7537 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
7538 + fixp
->fx_next
->fx_where
7539 - S_GET_VALUE (fixp
->fx_subsy
));
7541 reloc
->addend
= (fixp
->fx_addnumber
7542 + fixp
->fx_next
->fx_frag
->fr_address
7543 + fixp
->fx_next
->fx_where
);
7545 else if (fixp
->fx_pcrel
== 0)
7546 reloc
->addend
= fixp
->fx_addnumber
;
7549 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
7550 /* A gruesome hack which is a result of the gruesome gas reloc
7552 reloc
->addend
= reloc
->address
;
7554 reloc
->addend
= -reloc
->address
;
7557 /* If this is a variant frag, we may need to adjust the existing
7558 reloc and generate a new one. */
7559 if (fixp
->fx_frag
->fr_opcode
!= NULL
7560 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7561 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
7562 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
7563 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7564 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
7565 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7566 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
7570 /* If this is not the last reloc in this frag, then we have two
7571 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
7572 CALL_HI16/CALL_LO16, both of which are being replaced. Let
7573 the second one handle all of them. */
7574 if (fixp
->fx_next
!= NULL
7575 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
7577 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
7578 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
7579 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
7580 && (fixp
->fx_next
->fx_r_type
7581 == BFD_RELOC_MIPS_GOT_LO16
))
7582 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
7583 && (fixp
->fx_next
->fx_r_type
7584 == BFD_RELOC_MIPS_CALL_LO16
)));
7589 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
7590 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
7591 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
7593 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
7594 reloc2
->address
= (reloc
->address
7595 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
7596 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
7597 reloc2
->addend
= fixp
->fx_addnumber
;
7598 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
7599 assert (reloc2
->howto
!= NULL
);
7601 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
7605 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
7608 reloc3
->address
+= 4;
7611 if (mips_pic
== NO_PIC
)
7613 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
7614 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
7616 else if (mips_pic
== SVR4_PIC
)
7618 switch (fixp
->fx_r_type
)
7622 case BFD_RELOC_MIPS_GOT16
:
7624 case BFD_RELOC_MIPS_CALL16
:
7625 case BFD_RELOC_MIPS_GOT_LO16
:
7626 case BFD_RELOC_MIPS_CALL_LO16
:
7627 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
7635 /* To support a PC relative reloc when generating embedded PIC code
7636 for ECOFF, we use a Cygnus extension. We check for that here to
7637 make sure that we don't let such a reloc escape normally. */
7638 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
7639 && fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
7640 && mips_pic
!= EMBEDDED_PIC
)
7641 reloc
->howto
= NULL
;
7643 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
7645 if (reloc
->howto
== NULL
)
7647 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
7648 "Can not represent relocation in this object file format");
7655 /* Convert a machine dependent frag. */
7658 md_convert_frag (abfd
, asec
, fragp
)
7666 if (fragp
->fr_opcode
== NULL
)
7669 old
= RELAX_OLD (fragp
->fr_subtype
);
7670 new = RELAX_NEW (fragp
->fr_subtype
);
7671 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
7674 memcpy (fixptr
- old
, fixptr
, new);
7676 fragp
->fr_fix
+= new - old
;
7679 /* This function is called whenever a label is defined. It is used
7680 when handling branch delays; if a branch has a label, we assume we
7684 mips_define_label (sym
)
7690 /* Decide whether a label is local. This is called by LOCAL_LABEL.
7691 In order to work with gcc when using mips-tfile, we must keep all
7692 local labels. However, in other cases, we want to discard them,
7693 since they are useless. */
7696 mips_local_label (name
)
7699 #ifndef NO_ECOFF_DEBUGGING
7702 && ! ecoff_debugging_seen
)
7704 /* We were called with -g, but we didn't see any debugging
7705 information. That may mean that gcc is smuggling debugging
7706 information through to mips-tfile, in which case we must
7707 generate all local labels. */
7712 /* Here it's OK to discard local labels. */
7714 return name
[0] == '$';
7717 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7719 /* Some special processing for a MIPS ELF file. */
7722 mips_elf_final_processing ()
7724 /* Write out the register information. */
7729 s
.ri_gprmask
= mips_gprmask
;
7730 s
.ri_cprmask
[0] = mips_cprmask
[0];
7731 s
.ri_cprmask
[1] = mips_cprmask
[1];
7732 s
.ri_cprmask
[2] = mips_cprmask
[2];
7733 s
.ri_cprmask
[3] = mips_cprmask
[3];
7734 /* The gp_value field is set by the MIPS ELF backend. */
7736 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
7737 ((Elf32_External_RegInfo
*)
7738 mips_regmask_frag
));
7742 Elf64_Internal_RegInfo s
;
7744 s
.ri_gprmask
= mips_gprmask
;
7746 s
.ri_cprmask
[0] = mips_cprmask
[0];
7747 s
.ri_cprmask
[1] = mips_cprmask
[1];
7748 s
.ri_cprmask
[2] = mips_cprmask
[2];
7749 s
.ri_cprmask
[3] = mips_cprmask
[3];
7750 /* The gp_value field is set by the MIPS ELF backend. */
7752 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
7753 ((Elf64_External_RegInfo
*)
7754 mips_regmask_frag
));
7757 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
7758 sort of BFD interface for this. */
7759 if (mips_any_noreorder
)
7760 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
7761 if (mips_pic
!= NO_PIC
)
7762 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
7765 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
7767 /* These functions should really be defined by the object file format,
7768 since they are related to debugging information. However, this
7769 code has to work for the a.out format, which does not define them,
7770 so we provide simple versions here. These don't actually generate
7771 any debugging information, but they do simple checking and someday
7772 somebody may make them useful. */
7776 struct loc
*loc_next
;
7777 unsigned long loc_fileno
;
7778 unsigned long loc_lineno
;
7779 unsigned long loc_offset
;
7780 unsigned short loc_delta
;
7781 unsigned short loc_count
;
7790 struct proc
*proc_next
;
7791 struct symbol
*proc_isym
;
7792 struct symbol
*proc_end
;
7793 unsigned long proc_reg_mask
;
7794 unsigned long proc_reg_offset
;
7795 unsigned long proc_fpreg_mask
;
7796 unsigned long proc_fpreg_offset
;
7797 unsigned long proc_frameoffset
;
7798 unsigned long proc_framereg
;
7799 unsigned long proc_pcreg
;
7801 struct file
*proc_file
;
7808 struct file
*file_next
;
7809 unsigned long file_fileno
;
7810 struct symbol
*file_symbol
;
7811 struct symbol
*file_end
;
7812 struct proc
*file_proc
;
7817 static struct obstack proc_frags
;
7818 static procS
*proc_lastP
;
7819 static procS
*proc_rootP
;
7820 static int numprocs
;
7825 obstack_begin (&proc_frags
, 0x2000);
7831 /* check for premature end, nesting errors, etc */
7832 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7833 as_warn ("missing `.end' at end of assembly");
7842 if (*input_line_pointer
== '-')
7844 ++input_line_pointer
;
7847 if (!isdigit (*input_line_pointer
))
7848 as_bad ("Expected simple number.");
7849 if (input_line_pointer
[0] == '0')
7851 if (input_line_pointer
[1] == 'x')
7853 input_line_pointer
+= 2;
7854 while (isxdigit (*input_line_pointer
))
7857 val
|= hex_value (*input_line_pointer
++);
7859 return negative
? -val
: val
;
7863 ++input_line_pointer
;
7864 while (isdigit (*input_line_pointer
))
7867 val
|= *input_line_pointer
++ - '0';
7869 return negative
? -val
: val
;
7872 if (!isdigit (*input_line_pointer
))
7874 printf (" *input_line_pointer == '%c' 0x%02x\n",
7875 *input_line_pointer
, *input_line_pointer
);
7876 as_warn ("Invalid number");
7879 while (isdigit (*input_line_pointer
))
7882 val
+= *input_line_pointer
++ - '0';
7884 return negative
? -val
: val
;
7887 /* The .file directive; just like the usual .file directive, but there
7888 is an initial number which is the ECOFF file index. */
7896 line
= get_number ();
7901 /* The .end directive. */
7909 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
7912 demand_empty_rest_of_line ();
7916 if (now_seg
!= text_section
)
7917 as_warn (".end not in text section");
7920 as_warn (".end and no .ent seen yet.");
7926 assert (S_GET_NAME (p
));
7927 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
7928 as_warn (".end symbol does not match .ent symbol.");
7931 proc_lastP
->proc_end
= (symbolS
*) 1;
7934 /* The .aent and .ent directives. */
7944 symbolP
= get_symbol ();
7945 if (*input_line_pointer
== ',')
7946 input_line_pointer
++;
7948 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
7949 number
= get_number ();
7950 if (now_seg
!= text_section
)
7951 as_warn (".ent or .aent not in text section.");
7953 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
7954 as_warn ("missing `.end'");
7958 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
7959 procP
->proc_isym
= symbolP
;
7960 procP
->proc_reg_mask
= 0;
7961 procP
->proc_reg_offset
= 0;
7962 procP
->proc_fpreg_mask
= 0;
7963 procP
->proc_fpreg_offset
= 0;
7964 procP
->proc_frameoffset
= 0;
7965 procP
->proc_framereg
= 0;
7966 procP
->proc_pcreg
= 0;
7967 procP
->proc_end
= NULL
;
7968 procP
->proc_next
= NULL
;
7970 proc_lastP
->proc_next
= procP
;
7976 demand_empty_rest_of_line ();
7979 /* The .frame directive. */
7992 frame_reg
= tc_get_register (1);
7993 if (*input_line_pointer
== ',')
7994 input_line_pointer
++;
7995 frame_off
= get_absolute_expression ();
7996 if (*input_line_pointer
== ',')
7997 input_line_pointer
++;
7998 pcreg
= tc_get_register (0);
8001 assert (proc_rootP
);
8002 proc_rootP
->proc_framereg
= frame_reg
;
8003 proc_rootP
->proc_frameoffset
= frame_off
;
8004 proc_rootP
->proc_pcreg
= pcreg
;
8005 /* bob macho .frame */
8007 /* We don't have to write out a frame stab for unoptimized code. */
8008 if (!(frame_reg
== FP
&& frame_off
== 0))
8011 as_warn ("No .ent for .frame to use.");
8012 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
8013 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
8014 S_SET_TYPE (symP
, N_RMASK
);
8015 S_SET_OTHER (symP
, 0);
8016 S_SET_DESC (symP
, 0);
8017 symP
->sy_forward
= proc_lastP
->proc_isym
;
8018 /* bob perhaps I should have used pseudo set */
8020 demand_empty_rest_of_line ();
8024 /* The .fmask and .mask directives. */
8031 char str
[100], *strP
;
8037 mask
= get_number ();
8038 if (*input_line_pointer
== ',')
8039 input_line_pointer
++;
8040 off
= get_absolute_expression ();
8042 /* bob only for coff */
8043 assert (proc_rootP
);
8044 if (reg_type
== 'F')
8046 proc_rootP
->proc_fpreg_mask
= mask
;
8047 proc_rootP
->proc_fpreg_offset
= off
;
8051 proc_rootP
->proc_reg_mask
= mask
;
8052 proc_rootP
->proc_reg_offset
= off
;
8055 /* bob macho .mask + .fmask */
8057 /* We don't have to write out a mask stab if no saved regs. */
8061 as_warn ("No .ent for .mask to use.");
8063 for (i
= 0; i
< 32; i
++)
8067 sprintf (strP
, "%c%d,", reg_type
, i
);
8068 strP
+= strlen (strP
);
8072 sprintf (strP
, ";%d,", off
);
8073 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
8074 S_SET_TYPE (symP
, N_RMASK
);
8075 S_SET_OTHER (symP
, 0);
8076 S_SET_DESC (symP
, 0);
8077 symP
->sy_forward
= proc_lastP
->proc_isym
;
8078 /* bob perhaps I should have used pseudo set */
8083 /* The .loc directive. */
8094 assert (now_seg
== text_section
);
8096 lineno
= get_number ();
8097 addroff
= frag_now_fix ();
8099 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
8100 S_SET_TYPE (symbolP
, N_SLINE
);
8101 S_SET_OTHER (symbolP
, 0);
8102 S_SET_DESC (symbolP
, lineno
);
8103 symbolP
->sy_segment
= now_seg
;