1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to
22 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
40 #endif /* NO_VARARGS */
41 #endif /* NO_STDARG */
43 #include "opcode/mips.h"
48 static char *mips_regmask_frag
;
52 #define PIC_CALL_REG 25
58 /* Decide whether to do GP reference optimizations based on the object
68 /* The default target format to use. */
70 #ifdef TARGET_BYTES_BIG_ENDIAN
71 #define DEFAULT_TARGET_FORMAT "a.out-mips-big"
73 #define DEFAULT_TARGET_FORMAT "a.out-mips-little"
77 #ifdef TARGET_BYTES_BIG_ENDIAN
78 #define DEFAULT_TARGET_FORMAT "ecoff-bigmips"
80 #define DEFAULT_TARGET_FORMAT "ecoff-littlemips"
82 #endif /* OBJ_ECOFF */
84 #ifdef TARGET_BYTES_BIG_ENDIAN
85 #define DEFAULT_TARGET_FORMAT "elf32-bigmips"
87 #define DEFAULT_TARGET_FORMAT "elf32-littlemips"
91 const char *mips_target_format
= DEFAULT_TARGET_FORMAT
;
93 /* These variables are filled in with the masks of registers used.
94 The object format code reads them and puts them in the appropriate
96 unsigned long mips_gprmask
;
97 unsigned long mips_cprmask
[4];
99 /* MIPS ISA (Instruction Set Architecture) level (may be changed
100 temporarily using .set mipsN). */
101 static int mips_isa
= -1;
103 /* MIPS ISA we are using for this output file. */
104 static int file_mips_isa
;
106 /* MIPS PIC level. */
110 /* Do not generate PIC code. */
113 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
114 not sure what it is supposed to do. */
117 /* Generate PIC code as in the SVR4 MIPS ABI. */
120 /* Generate PIC code without using a global offset table: the data
121 segment has a maximum size of 64K, all data references are off
122 the $gp register, and all text references are PC relative. This
123 is used on some embedded systems. */
127 static enum mips_pic_level mips_pic
;
129 /* 1 if trap instructions should used for overflow rather than break
131 static int mips_trap
;
133 static int mips_warn_about_macros
;
134 static int mips_noreorder
;
135 static int mips_any_noreorder
;
136 static int mips_nomove
;
137 static int mips_noat
;
138 static int mips_nobopt
;
141 /* The size of the small data section. */
142 static int g_switch_value
= 8;
143 /* Whether the -G option was used. */
144 static int g_switch_seen
= 0;
150 /* handle of the OPCODE hash table */
151 static struct hash_control
*op_hash
= NULL
;
153 /* This array holds the chars that always start a comment. If the
154 pre-processor is disabled, these aren't very useful */
155 const char comment_chars
[] = "#";
157 /* This array holds the chars that only start a comment at the beginning of
158 a line. If the line seems to have the form '# 123 filename'
159 .line and .file directives will appear in the pre-processed output */
160 /* Note that input_file.c hand checks for '#' at the beginning of the
161 first line of the input file. This is because the compiler outputs
162 #NO_APP at the beginning of its output. */
163 /* Also note that C style comments are always supported. */
164 const char line_comment_chars
[] = "#";
166 /* This array holds machine specific line separator characters. */
167 const char line_separator_chars
[] = "";
169 /* Chars that can be used to separate mant from exp in floating point nums */
170 const char EXP_CHARS
[] = "eE";
172 /* Chars that mean this number is a floating point constant */
175 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
177 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
178 changed in read.c . Ideally it shouldn't have to know about it at all,
179 but nothing is ideal around here.
182 static char *insn_error
;
184 static int byte_order
= BYTE_ORDER
;
186 static int auto_align
= 1;
188 /* Symbol labelling the current insn. */
189 static symbolS
*insn_label
;
191 /* When outputting SVR4 PIC code, the assembler needs to know the
192 offset in the stack frame from which to restore the $gp register.
193 This is set by the .cprestore pseudo-op, and saved in this
195 static offsetT mips_cprestore_offset
= -1;
197 /* This is the register which holds the stack frame, as set by the
198 .frame pseudo-op. This is needed to implement .cprestore. */
199 static int mips_frame_reg
= SP
;
201 /* To output NOP instructions correctly, we need to keep information
202 about the previous two instructions. */
204 /* Whether we are optimizing. The default value of 2 means to remove
205 unneeded NOPs and swap branch instructions when possible. A value
206 of 1 means to not swap branches. A value of 0 means to always
208 static int mips_optimize
= 2;
210 /* The previous instruction. */
211 static struct mips_cl_insn prev_insn
;
213 /* The instruction before prev_insn. */
214 static struct mips_cl_insn prev_prev_insn
;
216 /* If we don't want information for prev_insn or prev_prev_insn, we
217 point the insn_mo field at this dummy integer. */
218 static const struct mips_opcode dummy_opcode
= { 0 };
220 /* Non-zero if prev_insn is valid. */
221 static int prev_insn_valid
;
223 /* The frag for the previous instruction. */
224 static struct frag
*prev_insn_frag
;
226 /* The offset into prev_insn_frag for the previous instruction. */
227 static long prev_insn_where
;
229 /* The reloc for the previous instruction, if any. */
230 static fixS
*prev_insn_fixp
;
232 /* Non-zero if the previous instruction was in a delay slot. */
233 static int prev_insn_is_delay_slot
;
235 /* Non-zero if the previous instruction was in a .set noreorder. */
236 static int prev_insn_unreordered
;
238 /* Non-zero if the previous previous instruction was in a .set
240 static int prev_prev_insn_unreordered
;
242 /* Since the MIPS does not have multiple forms of PC relative
243 instructions, we do not have to do relaxing as is done on other
244 platforms. However, we do have to handle GP relative addressing
245 correctly, which turns out to be a similar problem.
247 Every macro that refers to a symbol can occur in (at least) two
248 forms, one with GP relative addressing and one without. For
249 example, loading a global variable into a register generally uses
250 a macro instruction like this:
252 If i can be addressed off the GP register (this is true if it is in
253 the .sbss or .sdata section, or if it is known to be smaller than
254 the -G argument) this will generate the following instruction:
256 This instruction will use a GPREL reloc. If i can not be addressed
257 off the GP register, the following instruction sequence will be used:
260 In this case the first instruction will have a HI16 reloc, and the
261 second reloc will have a LO16 reloc. Both relocs will be against
264 The issue here is that we may not know whether i is GP addressable
265 until after we see the instruction that uses it. Therefore, we
266 want to be able to choose the final instruction sequence only at
267 the end of the assembly. This is similar to the way other
268 platforms choose the size of a PC relative instruction only at the
271 When generating position independent code we do not use GP
272 addressing in quite the same way, but the issue still arises as
273 external symbols and local symbols must be handled differently.
275 We handle these issues by actually generating both possible
276 instruction sequences. The longer one is put in a frag_var with
277 type rs_machine_dependent. We encode what to do with the frag in
278 the subtype field. We encode (1) the number of existing bytes to
279 replace, (2) the number of new bytes to use, (3) the offset from
280 the start of the existing bytes to the first reloc we must generate
281 (that is, the offset is applied from the start of the existing
282 bytes after they are replaced by the new bytes, if any), (4) the
283 offset from the start of the existing bytes to the second reloc,
284 (5) whether a third reloc is needed (the third reloc is always four
285 bytes after the second reloc), and (6) whether to warn if this
286 variant is used (this is sometimes needed if .set nomacro or .set
287 noat is in effect). All these numbers are reasonably small.
289 Generating two instruction sequences must be handled carefully to
290 ensure that delay slots are handled correctly. Fortunately, there
291 are a limited number of cases. When the second instruction
292 sequence is generated, append_insn is directed to maintain the
293 existing delay slot information, so it continues to apply to any
294 code after the second instruction sequence. This means that the
295 second instruction sequence must not impose any requirements not
296 required by the first instruction sequence.
298 These variant frags are then handled in functions called by the
299 machine independent code. md_estimate_size_before_relax returns
300 the final size of the frag. md_convert_frag sets up the final form
301 of the frag. tc_gen_reloc adjust the first reloc and adds a second
303 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
307 | (((reloc1) + 64) << 9) \
308 | (((reloc2) + 64) << 2) \
309 | ((reloc3) ? (1 << 1) : 0) \
311 #define RELAX_OLD(i) (((i) >> 24) & 0xff)
312 #define RELAX_NEW(i) (((i) >> 16) & 0xff)
313 #define RELAX_RELOC1(i) ((((i) >> 9) & 0x7f) - 64)
314 #define RELAX_RELOC2(i) ((((i) >> 2) & 0x7f) - 64)
315 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
316 #define RELAX_WARN(i) ((i) & 1)
318 /* Prototypes for static functions. */
321 #define internalError() \
322 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
324 #define internalError() as_fatal ("MIPS internal Error");
327 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
328 unsigned int reg
, int fpr
));
329 static void append_insn
PARAMS ((char *place
,
330 struct mips_cl_insn
* ip
,
332 bfd_reloc_code_real_type r
));
333 static void mips_no_prev_insn
PARAMS ((void));
334 static void mips_emit_delays
PARAMS ((void));
335 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
336 const char *name
, const char *fmt
,
338 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
339 expressionS
* ep
, int regnum
));
340 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
341 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
343 static void load_register
PARAMS ((int *counter
, int reg
, expressionS
* ep
));
344 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
345 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
346 #ifdef LOSING_COMPILER
347 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
349 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
350 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
351 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
352 static symbolS
*get_symbol
PARAMS ((void));
353 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
354 static void s_align
PARAMS ((int));
355 static void s_stringer
PARAMS ((int));
356 static void s_change_sec
PARAMS ((int));
357 static void s_cons
PARAMS ((int));
358 static void s_err
PARAMS ((int));
359 static void s_extern
PARAMS ((int));
360 static void s_float_cons
PARAMS ((int));
361 static void s_option
PARAMS ((int));
362 static void s_mipsset
PARAMS ((int));
363 static void s_mips_space
PARAMS ((int));
364 static void s_abicalls
PARAMS ((int));
365 static void s_cpload
PARAMS ((int));
366 static void s_cprestore
PARAMS ((int));
367 static void s_gpword
PARAMS ((int));
368 static void s_cpadd
PARAMS ((int));
369 #ifndef ECOFF_DEBUGGING
370 static void md_obj_begin
PARAMS ((void));
371 static void md_obj_end
PARAMS ((void));
372 static long get_number
PARAMS ((void));
373 static void s_ent
PARAMS ((int));
374 static void s_mipsend
PARAMS ((int));
375 static void s_file
PARAMS ((int));
377 static void s_frame
PARAMS ((int));
378 static void s_loc
PARAMS ((int));
379 static void s_mask
PARAMS ((char));
385 The following pseudo-ops from the Kane and Heinrich MIPS book
386 should be defined here, but are currently unsupported: .alias,
387 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
389 The following pseudo-ops from the Kane and Heinrich MIPS book are
390 specific to the type of debugging information being generated, and
391 should be defined by the object format: .aent, .begin, .bend,
392 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
395 The following pseudo-ops from the Kane and Heinrich MIPS book are
396 not MIPS CPU specific, but are also not specific to the object file
397 format. This file is probably the best place to define them, but
398 they are not currently supported: .asm0, .endr, .lab, .repeat,
399 .struct, .weakext. */
401 const pseudo_typeS md_pseudo_table
[] =
403 /* MIPS specific pseudo-ops. */
404 {"option", s_option
, 0},
405 {"set", s_mipsset
, 0},
406 {"rdata", s_change_sec
, 'r'},
407 {"sdata", s_change_sec
, 's'},
408 {"livereg", s_ignore
, 0},
409 { "abicalls", s_abicalls
, 0},
410 { "cpload", s_cpload
, 0},
411 { "cprestore", s_cprestore
, 0},
412 { "gpword", s_gpword
, 0},
413 { "cpadd", s_cpadd
, 0},
415 /* Relatively generic pseudo-ops that happen to be used on MIPS
417 {"asciiz", s_stringer
, 1},
418 {"bss", s_change_sec
, 'b'},
421 {"dword", s_cons
, 3},
423 /* These pseudo-ops are defined in read.c, but must be overridden
424 here for one reason or another. */
425 {"align", s_align
, 0},
426 {"ascii", s_stringer
, 0},
427 {"asciz", s_stringer
, 1},
429 {"data", s_change_sec
, 'd'},
430 {"double", s_float_cons
, 'd'},
431 {"extern", s_extern
, 0},
432 {"float", s_float_cons
, 'f'},
433 {"hword", s_cons
, 1},
438 {"short", s_cons
, 1},
439 {"single", s_float_cons
, 'f'},
440 {"space", s_mips_space
, 0},
441 {"text", s_change_sec
, 't'},
444 #ifndef ECOFF_DEBUGGING
445 /* These pseudo-ops should be defined by the object file format.
446 However, a.out doesn't support them, so we have versions here. */
448 {"bgnb", s_ignore
, 0},
449 {"end", s_mipsend
, 0},
450 {"endb", s_ignore
, 0},
453 {"fmask", s_ignore
, 'F'},
454 {"frame", s_ignore
, 0},
455 {"loc", s_ignore
, 0},
456 {"mask", s_ignore
, 'R'},
457 {"verstamp", s_ignore
, 0},
464 const relax_typeS md_relax_table
[] =
469 static char *expr_end
;
471 static expressionS imm_expr
;
472 static expressionS offset_expr
;
473 static bfd_reloc_code_real_type imm_reloc
;
474 static bfd_reloc_code_real_type offset_reloc
;
476 /* FIXME: This should be handled in a different way. */
477 extern int target_big_endian
;
480 * This function is called once, at assembler startup time. It should
481 * set up all the tables, etc. that the MD part of the assembler will need.
487 register const char *retval
= NULL
;
488 register unsigned int i
= 0;
492 if (strcmp (TARGET_CPU
, "mips") == 0)
494 else if (strcmp (TARGET_CPU
, "r6000") == 0
495 || strcmp (TARGET_CPU
, "mips2") == 0)
497 else if (strcmp (TARGET_CPU
, "mips64") == 0
498 || strcmp (TARGET_CPU
, "r4000") == 0
499 || strcmp (TARGET_CPU
, "mips3") == 0)
505 if (mips_isa
< 2 && mips_trap
)
506 as_bad ("trap exception not supported at ISA 1");
511 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
514 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
517 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
521 as_warn ("Could not set architecture and machine");
523 file_mips_isa
= mips_isa
;
525 op_hash
= hash_new ();
527 for (i
= 0; i
< NUMOPCODES
;)
529 const char *name
= mips_opcodes
[i
].name
;
531 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
534 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
535 mips_opcodes
[i
].name
, retval
);
536 as_fatal ("Broken assembler. No assembly attempted.");
540 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
541 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
542 != mips_opcodes
[i
].match
))
544 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
545 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
546 as_fatal ("Broken assembler. No assembly attempted.");
550 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
553 mips_no_prev_insn ();
561 /* set the default alignment for the text section (2**2) */
562 record_alignment (text_section
, 2);
564 /* FIXME: This should be handled in a different way. */
565 target_big_endian
= byte_order
== BIG_ENDIAN
;
568 bfd_set_gp_size (stdoutput
, g_switch_value
);
572 /* Sections must be aligned to 16 byte boundaries. */
573 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
574 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
575 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
577 /* Create a .reginfo section for register masks and a .mdebug
578 section for debugging information. */
586 sec
= subseg_new (".reginfo", (subsegT
) 0);
588 /* The ABI says this section should be loaded so that the running
589 program can access it. */
590 (void) bfd_set_section_flags (stdoutput
, sec
,
591 (SEC_ALLOC
| SEC_LOAD
592 | SEC_READONLY
| SEC_DATA
));
593 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
595 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
597 #ifdef ECOFF_DEBUGGING
598 sec
= subseg_new (".mdebug", (subsegT
) 0);
599 (void) bfd_set_section_flags (stdoutput
, sec
,
600 SEC_HAS_CONTENTS
| SEC_READONLY
);
601 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
604 subseg_set (seg
, subseg
);
608 #ifndef ECOFF_DEBUGGING
616 #ifndef ECOFF_DEBUGGING
625 struct mips_cl_insn insn
;
627 imm_expr
.X_op
= O_absent
;
628 offset_expr
.X_op
= O_absent
;
630 mips_ip (str
, &insn
);
633 as_bad ("%s `%s'", insn_error
, str
);
636 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
642 if (imm_expr
.X_op
!= O_absent
)
643 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
);
644 else if (offset_expr
.X_op
!= O_absent
)
645 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
);
647 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
);
651 /* See whether instruction IP reads register REG. If FPR is non-zero,
652 REG is a floating point register. */
655 insn_uses_reg (ip
, reg
, fpr
)
656 struct mips_cl_insn
*ip
;
660 /* Don't report on general register 0, since it never changes. */
661 if (! fpr
&& reg
== 0)
666 /* If we are called with either $f0 or $f1, we must check $f0.
667 This is not optimal, because it will introduce an unnecessary
668 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
669 need to distinguish reading both $f0 and $f1 or just one of
670 them. Note that we don't have to check the other way,
671 because there is no instruction that sets both $f0 and $f1
672 and requires a delay. */
673 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
674 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
675 == (reg
&~ (unsigned) 1)))
677 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
678 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
679 == (reg
&~ (unsigned) 1)))
684 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
685 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
687 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
688 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
695 /* Output an instruction. PLACE is where to put the instruction; if
696 it is NULL, this uses frag_more to get room. IP is the instruction
697 information. ADDRESS_EXPR is an operand of the instruction to be
698 used with RELOC_TYPE. */
701 append_insn (place
, ip
, address_expr
, reloc_type
)
703 struct mips_cl_insn
*ip
;
704 expressionS
*address_expr
;
705 bfd_reloc_code_real_type reloc_type
;
707 register unsigned long prev_pinfo
, pinfo
;
712 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
713 pinfo
= ip
->insn_mo
->pinfo
;
715 if (place
== NULL
&& ! mips_noreorder
)
717 /* If the previous insn required any delay slots, see if we need
718 to insert a NOP or two. There are eight kinds of possible
719 hazards, of which an instruction can have at most one type.
720 (1) a load from memory delay
721 (2) a load from a coprocessor delay
722 (3) an unconditional branch delay
723 (4) a conditional branch delay
724 (5) a move to coprocessor register delay
725 (6) a load coprocessor register from memory delay
726 (7) a coprocessor condition code delay
727 (8) a HI/LO special register delay
729 There are a lot of optimizations we could do that we don't.
730 In particular, we do not, in general, reorder instructions.
731 If you use gcc with optimization, it will reorder
732 instructions and generally do much more optimization then we
733 do here; repeating all that work in the assembler would only
734 benefit hand written assembly code, and does not seem worth
737 /* This is how a NOP is emitted. */
738 #define emit_nop() md_number_to_chars (frag_more (4), 0, 4)
740 /* The previous insn might require a delay slot, depending upon
741 the contents of the current insn. */
742 if ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
744 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)))
746 /* A load from a coprocessor or from memory. All load
747 delays delay the use of general register rt for one
748 instruction on the r3000. The r6000 and r4000 use
750 know (prev_pinfo
& INSN_WRITE_GPR_T
);
751 if (mips_optimize
== 0
752 || insn_uses_reg (ip
,
753 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
758 else if ((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
760 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)))
762 /* A generic coprocessor delay. The previous instruction
763 modified a coprocessor general or control register. If
764 it modified a control register, we need to avoid any
765 coprocessor instruction (this is probably not always
766 required, but it sometimes is). If it modified a general
767 register, we avoid using that register.
769 On the r6000 and r4000 loading a coprocessor register
770 from memory is interlocked, and does not require a delay.
772 This case is not handled very well. There is no special
773 knowledge of CP0 handling, and the coprocessors other
774 than the floating point unit are not distinguished at
776 if (prev_pinfo
& INSN_WRITE_FPR_T
)
778 if (mips_optimize
== 0
779 || insn_uses_reg (ip
,
780 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
785 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
787 if (mips_optimize
== 0
788 || insn_uses_reg (ip
,
789 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
796 /* We don't know exactly what the previous instruction
797 does. If the current instruction uses a coprocessor
798 register, we must insert a NOP. If previous
799 instruction may set the condition codes, and the
800 current instruction uses them, we must insert two
802 if (mips_optimize
== 0
803 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
804 && (pinfo
& INSN_READ_COND_CODE
)))
806 else if (pinfo
& INSN_COP
)
810 else if (prev_pinfo
& INSN_WRITE_COND_CODE
)
812 /* The previous instruction sets the coprocessor condition
813 codes, but does not require a general coprocessor delay
814 (this means it is a floating point comparison
815 instruction). If this instruction uses the condition
816 codes, we need to insert a single NOP. */
817 if (mips_optimize
== 0
818 || (pinfo
& INSN_READ_COND_CODE
))
821 else if (prev_pinfo
& INSN_READ_LO
)
823 /* The previous instruction reads the LO register; if the
824 current instruction writes to the LO register, we must
826 if (mips_optimize
== 0
827 || (pinfo
& INSN_WRITE_LO
))
830 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
832 /* The previous instruction reads the HI register; if the
833 current instruction writes to the HI register, we must
835 if (mips_optimize
== 0
836 || (pinfo
& INSN_WRITE_HI
))
840 /* There are two cases which require two intervening
841 instructions: 1) setting the condition codes using a move to
842 coprocessor instruction which requires a general coprocessor
843 delay and then reading the condition codes 2) reading the HI
844 or LO register and then writing to it. If we are not already
845 emitting a NOP instruction, we must check for these cases
846 compared to the instruction previous to the previous
849 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
850 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
851 && (pinfo
& INSN_READ_COND_CODE
))
852 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
853 && (pinfo
& INSN_WRITE_LO
))
854 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
855 && (pinfo
& INSN_WRITE_HI
))))
858 /* If we are being given a nop instruction, don't bother with
859 one of the nops we would otherwise output. This will only
860 happen when a nop instruction is used with mips_optimize set
862 if (nops
> 0 && ip
->insn_opcode
== 0)
865 /* Now emit the right number of NOP instructions. */
872 listing_prev_line ();
873 if (insn_label
!= NULL
)
875 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
876 insn_label
->sy_frag
= frag_now
;
877 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
887 if (address_expr
!= NULL
)
889 if (address_expr
->X_op
== O_constant
)
894 ip
->insn_opcode
|= address_expr
->X_add_number
;
898 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
901 case BFD_RELOC_MIPS_JMP
:
902 case BFD_RELOC_16_PCREL_S2
:
911 assert (reloc_type
!= BFD_RELOC_UNUSED
);
913 /* Don't generate a reloc if we are writing into a variant
916 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
918 reloc_type
== BFD_RELOC_16_PCREL_S2
,
923 md_number_to_chars (f
, ip
->insn_opcode
, 4);
925 /* Update the register mask information. */
926 if (pinfo
& INSN_WRITE_GPR_D
)
927 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
928 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
929 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
930 if (pinfo
& INSN_READ_GPR_S
)
931 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
932 if (pinfo
& INSN_WRITE_GPR_31
)
933 mips_gprmask
|= 1 << 31;
934 if (pinfo
& INSN_WRITE_FPR_D
)
935 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
936 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
937 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
938 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
939 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
940 if (pinfo
& INSN_COP
)
942 /* We don't keep enough information to sort these cases out. */
944 /* Never set the bit for $0, which is always zero. */
945 mips_gprmask
&=~ 1 << 0;
947 if (place
== NULL
&& ! mips_noreorder
)
949 /* Filling the branch delay slot is more complex. We try to
950 switch the branch with the previous instruction, which we can
951 do if the previous instruction does not set up a condition
952 that the branch tests and if the branch is not itself the
953 target of any branch. */
954 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
955 || (pinfo
& INSN_COND_BRANCH_DELAY
))
957 if (mips_optimize
< 2
958 /* If we have seen .set nobopt, don't optimize. */
960 /* If we have seen .set volatile or .set nomove, don't
963 /* If we had to emit any NOP instructions, then we
964 already know we can not swap. */
966 /* If we don't even know the previous insn, we can not
969 /* If the previous insn is already in a branch delay
970 slot, then we can not swap. */
971 || prev_insn_is_delay_slot
972 /* If the previous previous insn was in a .set
973 noreorder, we can't swap. Actually, the MIPS
974 assembler will swap in this situation. However, gcc
975 configured -with-gnu-as will generate code like
981 in which we can not swap the bne and INSN. If gcc is
982 not configured -with-gnu-as, it does not output the
983 .set pseudo-ops. We don't have to check
984 prev_insn_unreordered, because prev_insn_valid will
985 be 0 in that case. We don't want to use
986 prev_prev_insn_valid, because we do want to be able
987 to swap at the start of a function. */
988 || prev_prev_insn_unreordered
989 /* If the branch is itself the target of a branch, we
990 can not swap. We cheat on this; all we check for is
991 whether there is a label on this instruction. If
992 there are any branches to anything other than a
993 label, users must use .set noreorder. */
994 || insn_label
!= NULL
995 /* If the previous instruction is in a variant frag, we
996 can not do the swap. */
997 || prev_insn_frag
->fr_type
== rs_machine_dependent
998 /* If the branch reads the condition codes, we don't
999 even try to swap, because in the sequence
1004 we can not swap, and I don't feel like handling that
1006 || (pinfo
& INSN_READ_COND_CODE
)
1007 /* We can not swap with an instruction that requires a
1008 delay slot, becase the target of the branch might
1009 interfere with that instruction. */
1011 & (INSN_LOAD_COPROC_DELAY
1012 | INSN_COPROC_MOVE_DELAY
1013 | INSN_WRITE_COND_CODE
1018 & (INSN_LOAD_MEMORY_DELAY
1019 | INSN_COPROC_MEMORY_DELAY
)))
1020 /* We can not swap with a branch instruction. */
1022 & (INSN_UNCOND_BRANCH_DELAY
1023 | INSN_COND_BRANCH_DELAY
1024 | INSN_COND_BRANCH_LIKELY
))
1025 /* We do not swap with a trap instruction, since it
1026 complicates trap handlers to have the trap
1027 instruction be in a delay slot. */
1028 || (prev_pinfo
& INSN_TRAP
)
1029 /* If the branch reads a register that the previous
1030 instruction sets, we can not swap. */
1031 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1032 && insn_uses_reg (ip
,
1033 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1036 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1037 && insn_uses_reg (ip
,
1038 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1041 /* If the branch writes a register that the previous
1042 instruction sets, we can not swap (we know that
1043 branches write only to RD or to $31). */
1044 || ((prev_pinfo
& INSN_WRITE_GPR_T
)
1045 && (((pinfo
& INSN_WRITE_GPR_D
)
1046 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1047 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1048 || ((pinfo
& INSN_WRITE_GPR_31
)
1049 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1052 || ((prev_pinfo
& INSN_WRITE_GPR_D
)
1053 && (((pinfo
& INSN_WRITE_GPR_D
)
1054 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1055 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1056 || ((pinfo
& INSN_WRITE_GPR_31
)
1057 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1060 /* If the branch writes a register that the previous
1061 instruction reads, we can not swap (we know that
1062 branches only write to RD or to $31). */
1063 || ((pinfo
& INSN_WRITE_GPR_D
)
1064 && insn_uses_reg (&prev_insn
,
1065 ((ip
->insn_opcode
>> OP_SH_RD
)
1068 || ((pinfo
& INSN_WRITE_GPR_31
)
1069 && insn_uses_reg (&prev_insn
, 31, 0))
1070 /* If we are generating embedded PIC code, the branch
1071 might be expanded into a sequence which uses $at, so
1072 we can't swap with an instruction which reads it. */
1073 || (mips_pic
== EMBEDDED_PIC
1074 && insn_uses_reg (&prev_insn
, AT
, 0))
1075 /* If the previous previous instruction has a load
1076 delay, and sets a register that the branch reads, we
1078 || (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1080 && (prev_prev_insn
.insn_mo
->pinfo
1081 & INSN_LOAD_MEMORY_DELAY
)))
1082 && insn_uses_reg (ip
,
1083 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1087 /* We could do even better for unconditional branches to
1088 portions of this object file; we could pick up the
1089 instruction at the destination, put it in the delay
1090 slot, and bump the destination address. */
1092 /* Update the previous insn information. */
1093 prev_prev_insn
= *ip
;
1094 prev_insn
.insn_mo
= &dummy_opcode
;
1101 /* It looks like we can actually do the swap. */
1102 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1103 memcpy (temp
, prev_f
, 4);
1104 memcpy (prev_f
, f
, 4);
1105 memcpy (f
, temp
, 4);
1108 prev_insn_fixp
->fx_frag
= frag_now
;
1109 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1113 fixp
->fx_frag
= prev_insn_frag
;
1114 fixp
->fx_where
= prev_insn_where
;
1116 /* Update the previous insn information; leave prev_insn
1118 prev_prev_insn
= *ip
;
1120 prev_insn_is_delay_slot
= 1;
1122 /* If that was an unconditional branch, forget the previous
1123 insn information. */
1124 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1126 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1127 prev_insn
.insn_mo
= &dummy_opcode
;
1130 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1132 /* We don't yet optimize a branch likely. What we should do
1133 is look at the target, copy the instruction found there
1134 into the delay slot, and increment the branch to jump to
1135 the next instruction. */
1137 /* Update the previous insn information. */
1138 prev_prev_insn
= *ip
;
1139 prev_insn
.insn_mo
= &dummy_opcode
;
1143 /* Update the previous insn information. */
1145 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1147 prev_prev_insn
= prev_insn
;
1150 /* Any time we see a branch, we always fill the delay slot
1151 immediately; since this insn is not a branch, we know it
1152 is not in a delay slot. */
1153 prev_insn_is_delay_slot
= 0;
1156 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1157 prev_insn_unreordered
= 0;
1158 prev_insn_frag
= frag_now
;
1159 prev_insn_where
= f
- frag_now
->fr_literal
;
1160 prev_insn_fixp
= fixp
;
1161 prev_insn_valid
= 1;
1164 /* We just output an insn, so the next one doesn't have a label. */
1168 /* This function forgets that there was any previous instruction or
1172 mips_no_prev_insn ()
1174 prev_insn
.insn_mo
= &dummy_opcode
;
1175 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1176 prev_insn_valid
= 0;
1177 prev_insn_is_delay_slot
= 0;
1178 prev_insn_unreordered
= 0;
1179 prev_prev_insn_unreordered
= 0;
1183 /* This function must be called whenever we turn on noreorder or emit
1184 something other than instructions. It inserts any NOPS which might
1185 be needed by the previous instruction, and clears the information
1186 kept for the previous instructions. */
1191 if (! mips_noreorder
)
1196 if ((prev_insn
.insn_mo
->pinfo
1197 & (INSN_LOAD_COPROC_DELAY
1198 | INSN_COPROC_MOVE_DELAY
1199 | INSN_WRITE_COND_CODE
1203 && (prev_insn
.insn_mo
->pinfo
1204 & (INSN_LOAD_MEMORY_DELAY
1205 | INSN_COPROC_MEMORY_DELAY
))))
1208 if ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1209 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1210 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1213 else if ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1214 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1215 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))
1220 if (insn_label
!= NULL
)
1222 assert (S_GET_SEGMENT (insn_label
) == now_seg
);
1223 insn_label
->sy_frag
= frag_now
;
1224 S_SET_VALUE (insn_label
, (valueT
) frag_now_fix ());
1227 mips_no_prev_insn ();
1231 /* Build an instruction created by a macro expansion. This is passed
1232 a pointer to the count of instructions created so far, an
1233 expression, the name of the instruction to build, an operand format
1234 string, and corresponding arguments. */
1238 macro_build (char *place
,
1244 #else /* ! defined (NO_STDARG) */
1246 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
1253 #endif /* ! defined (NO_STDARG) */
1255 struct mips_cl_insn insn
;
1256 bfd_reloc_code_real_type r
;
1260 va_start (args
, fmt
);
1266 * If the macro is about to expand into a second instruction,
1267 * print a warning if needed. We need to pass ip as a parameter
1268 * to generate a better warning message here...
1270 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1271 as_warn ("Macro instruction expanded into multiple instructions");
1274 *counter
+= 1; /* bump instruction counter */
1276 r
= BFD_RELOC_UNUSED
;
1277 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1278 assert (insn
.insn_mo
);
1279 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1281 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
1282 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
1285 assert (insn
.insn_mo
->name
);
1286 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1288 insn
.insn_opcode
= insn
.insn_mo
->match
;
1304 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1310 insn
.insn_opcode
|= va_arg (args
, int) << 16;
1315 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1320 insn
.insn_opcode
|= va_arg (args
, int) << 11;
1327 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1331 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1335 insn
.insn_opcode
|= va_arg (args
, int) << 6;
1342 insn
.insn_opcode
|= va_arg (args
, int) << 21;
1348 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
1349 assert (r
== BFD_RELOC_MIPS_GPREL
1350 || r
== BFD_RELOC_MIPS_LITERAL
1351 || r
== BFD_RELOC_LO16
1352 || r
== BFD_RELOC_MIPS_GOT16
1353 || r
== BFD_RELOC_MIPS_CALL16
);
1357 assert (ep
!= NULL
&& ep
->X_op
== O_constant
);
1358 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
1363 assert (ep
!= NULL
);
1365 * This allows macro() to pass an immediate expression for
1366 * creating short branches without creating a symbol.
1367 * Note that the expression still might come from the assembly
1368 * input, in which case the value is not checked for range nor
1369 * is a relocation entry generated (yuck).
1371 if (ep
->X_op
== O_constant
)
1373 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
1377 r
= BFD_RELOC_16_PCREL_S2
;
1381 assert (ep
!= NULL
);
1382 r
= BFD_RELOC_MIPS_JMP
;
1391 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
1393 append_insn (place
, &insn
, ep
, r
);
1397 * Generate a "lui" instruction.
1400 macro_build_lui (place
, counter
, ep
, regnum
)
1406 expressionS high_expr
;
1407 struct mips_cl_insn insn
;
1408 bfd_reloc_code_real_type r
;
1409 CONST
char *name
= "lui";
1410 CONST
char *fmt
= "t,u";
1416 high_expr
.X_op
= O_constant
;
1417 high_expr
.X_add_number
= 0;
1420 if (high_expr
.X_op
== O_constant
)
1422 /* we can compute the instruction now without a relocation entry */
1423 if (high_expr
.X_add_number
& 0x8000)
1424 high_expr
.X_add_number
+= 0x10000;
1425 high_expr
.X_add_number
=
1426 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
1427 r
= BFD_RELOC_UNUSED
;
1431 assert (ep
->X_op
== O_symbol
);
1432 /* _gp_disp is a special case, used from s_cpload. */
1433 assert (mips_pic
== NO_PIC
1434 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
1435 r
= BFD_RELOC_HI16_S
;
1439 * If the macro is about to expand into a second instruction,
1440 * print a warning if needed. We need to pass ip as a parameter
1441 * to generate a better warning message here...
1443 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
1444 as_warn ("Macro instruction expanded into multiple instructions");
1447 *counter
+= 1; /* bump instruction counter */
1449 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
1450 assert (insn
.insn_mo
);
1451 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
1452 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
1454 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
1455 if (r
== BFD_RELOC_UNUSED
)
1457 insn
.insn_opcode
|= high_expr
.X_add_number
;
1458 append_insn (place
, &insn
, NULL
, r
);
1461 append_insn (place
, &insn
, &high_expr
, r
);
1465 * Generates code to set the $at register to true (one)
1466 * if reg is less than the immediate expression.
1469 set_at (counter
, reg
, unsignedp
)
1474 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1475 macro_build ((char *) NULL
, counter
, &imm_expr
,
1476 unsignedp
? "sltiu" : "slti",
1477 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
1480 load_register (counter
, AT
, &imm_expr
);
1481 macro_build ((char *) NULL
, counter
, NULL
,
1482 unsignedp
? "sltu" : "slt",
1483 "d,v,t", AT
, reg
, AT
);
1487 /* Warn if an expression is not a constant. */
1490 check_absolute_expr (ip
, ex
)
1491 struct mips_cl_insn
*ip
;
1494 if (ex
->X_op
!= O_constant
)
1495 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
1499 * This routine generates the least number of instructions neccessary to load
1500 * an absolute expression value into a register.
1503 load_register (counter
, reg
, ep
)
1508 assert (ep
->X_op
== O_constant
);
1509 if (ep
->X_add_number
>= -0x8000 && ep
->X_add_number
< 0x8000)
1510 macro_build ((char *) NULL
, counter
, ep
,
1511 mips_isa
< 3 ? "addiu" : "daddiu",
1512 "t,r,j", reg
, 0, (int) BFD_RELOC_LO16
);
1513 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
1514 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
1515 (int) BFD_RELOC_LO16
);
1516 else if ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
1517 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
1518 == ~ (offsetT
) 0x7fffffff))
1520 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
);
1521 if ((ep
->X_add_number
& 0xffff) != 0)
1522 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
1523 (int) BFD_RELOC_LO16
);
1525 else if (mips_isa
< 3)
1527 as_bad ("Number larger than 32 bits");
1528 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
1529 (int) BFD_RELOC_LO16
);
1534 expressionS hi32
, lo32
;
1538 hi32
.X_add_number
>>= shift
;
1539 hi32
.X_add_number
&= 0xffffffff;
1540 if ((hi32
.X_add_number
& 0x80000000) != 0)
1541 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
1542 load_register (counter
, reg
, &hi32
);
1544 lo32
.X_add_number
&= 0xffffffff;
1545 if ((lo32
.X_add_number
& 0xffff0000) == 0)
1546 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
1552 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1555 mid16
.X_add_number
>>= 16;
1556 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
1557 reg
, (int) BFD_RELOC_LO16
);
1558 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
1561 if ((lo32
.X_add_number
& 0xffff) != 0)
1562 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, reg
,
1563 (int) BFD_RELOC_LO16
);
1567 /* Load an address into a register. */
1570 load_address (counter
, reg
, ep
)
1577 if (ep
->X_op
!= O_constant
1578 && ep
->X_op
!= O_symbol
)
1580 as_bad ("expression too complex");
1581 ep
->X_op
= O_constant
;
1584 if (ep
->X_op
== O_constant
)
1586 load_register (counter
, reg
, ep
);
1590 if (mips_pic
== NO_PIC
)
1592 /* If this is a reference to a GP relative symbol, we want
1593 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1595 lui $reg,<sym> (BFD_RELOC_HI16_S)
1596 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1597 If we have an addend, we always use the latter form. */
1598 if (ep
->X_add_number
!= 0)
1603 macro_build ((char *) NULL
, counter
, ep
,
1604 mips_isa
< 3 ? "addiu" : "daddiu",
1605 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1606 p
= frag_var (rs_machine_dependent
, 8, 0,
1607 RELAX_ENCODE (4, 8, -4, 0, 0, mips_warn_about_macros
),
1608 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1610 macro_build_lui (p
, counter
, ep
, reg
);
1613 macro_build (p
, counter
, ep
,
1614 mips_isa
< 3 ? "addiu" : "daddiu",
1615 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1617 else if (mips_pic
== SVR4_PIC
)
1621 /* If this is a reference to an external symbol, we want
1622 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1624 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
1626 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
1627 If there is a constant, it must be added in after. */
1628 ex
.X_add_number
= ep
->X_add_number
;
1629 ep
->X_add_number
= 0;
1631 macro_build ((char *) NULL
, counter
, ep
,
1632 mips_isa
< 3 ? "lw" : "ld",
1633 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
1634 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
1635 p
= frag_var (rs_machine_dependent
, 4, 0,
1636 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
1637 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
1638 macro_build (p
, counter
, ep
,
1639 mips_isa
< 3 ? "addiu" : "daddiu",
1640 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1641 if (ex
.X_add_number
!= 0)
1643 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
1644 as_bad ("PIC code offset overflow (max 16 signed bits)");
1645 ex
.X_op
= O_constant
;
1646 macro_build (p
, counter
, &ex
,
1647 mips_isa
< 3 ? "addiu" : "daddiu",
1648 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
1651 else if (mips_pic
== EMBEDDED_PIC
)
1654 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
1656 macro_build ((char *) NULL
, counter
, ep
,
1657 mips_isa
< 3 ? "addiu" : "daddiu",
1658 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
1666 * This routine implements the seemingly endless macro or synthesized
1667 * instructions and addressing modes in the mips assembly language. Many
1668 * of these macros are simple and are similar to each other. These could
1669 * probably be handled by some kind of table or grammer aproach instead of
1670 * this verbose method. Others are not simple macros but are more like
1671 * optimizing code generation.
1672 * One interesting optimization is when several store macros appear
1673 * consecutivly that would load AT with the upper half of the same address.
1674 * The ensuing load upper instructions are ommited. This implies some kind
1675 * of global optimization. We currently only optimize within a single macro.
1676 * For many of the load and store macros if the address is specified as a
1677 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
1678 * first load register 'at' with zero and use it as the base register. The
1679 * mips assembler simply uses register $zero. Just one tiny optimization
1684 struct mips_cl_insn
*ip
;
1686 register int treg
, sreg
, dreg
, breg
;
1699 bfd_reloc_code_real_type r
;
1702 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
1703 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
1704 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
1705 mask
= ip
->insn_mo
->mask
;
1707 expr1
.X_op
= O_constant
;
1708 expr1
.X_op_symbol
= NULL
;
1709 expr1
.X_add_symbol
= NULL
;
1710 expr1
.X_add_number
= 1;
1722 mips_emit_delays ();
1724 mips_any_noreorder
= 1;
1726 expr1
.X_add_number
= 8;
1727 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
1729 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1731 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
1732 macro_build ((char *) NULL
, &icnt
, NULL
,
1733 dbl
? "dsub" : "sub",
1734 "d,v,t", dreg
, 0, sreg
);
1757 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
1759 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
1760 (int) BFD_RELOC_LO16
);
1763 load_register (&icnt
, AT
, &imm_expr
);
1764 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1783 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
1785 if (mask
!= M_NOR_I
)
1786 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
1787 sreg
, (int) BFD_RELOC_LO16
);
1790 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
1791 treg
, sreg
, (int) BFD_RELOC_LO16
);
1792 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
1798 load_register (&icnt
, AT
, &imm_expr
);
1799 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
1816 if (imm_expr
.X_add_number
== 0)
1818 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
1822 load_register (&icnt
, AT
, &imm_expr
);
1823 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
1831 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1832 likely
? "bgezl" : "bgez",
1838 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1839 likely
? "blezl" : "blez",
1843 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
1844 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1845 likely
? "beql" : "beq",
1852 /* check for > max integer */
1853 maxnum
= 0x7fffffff;
1861 if (imm_expr
.X_add_number
>= maxnum
)
1864 /* result is always false */
1867 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
1868 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
1872 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
1873 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
1878 imm_expr
.X_add_number
++;
1882 if (mask
== M_BGEL_I
)
1884 if (imm_expr
.X_add_number
== 0)
1886 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1887 likely
? "bgezl" : "bgez",
1891 if (imm_expr
.X_add_number
== 1)
1893 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1894 likely
? "bgtzl" : "bgtz",
1898 maxnum
= 0x7fffffff;
1906 maxnum
= - maxnum
- 1;
1907 if (imm_expr
.X_add_number
<= maxnum
)
1910 /* result is always true */
1911 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
1912 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
1915 set_at (&icnt
, sreg
, 0);
1916 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1917 likely
? "beql" : "beq",
1928 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1929 likely
? "beql" : "beq",
1933 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
1935 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1936 likely
? "beql" : "beq",
1943 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
1945 imm_expr
.X_add_number
++;
1949 if (mask
== M_BGEUL_I
)
1951 if (imm_expr
.X_add_number
== 0)
1953 if (imm_expr
.X_add_number
== 1)
1955 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1956 likely
? "bnel" : "bne",
1960 set_at (&icnt
, sreg
, 1);
1961 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1962 likely
? "beql" : "beq",
1971 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1972 likely
? "bgtzl" : "bgtz",
1978 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1979 likely
? "bltzl" : "bltz",
1983 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
1984 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1985 likely
? "bnel" : "bne",
1994 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
1995 likely
? "bnel" : "bne",
2001 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2003 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2004 likely
? "bnel" : "bne",
2013 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2014 likely
? "blezl" : "blez",
2020 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2021 likely
? "bgezl" : "bgez",
2025 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
2026 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2027 likely
? "beql" : "beq",
2034 maxnum
= 0x7fffffff;
2042 if (imm_expr
.X_add_number
>= maxnum
)
2044 imm_expr
.X_add_number
++;
2048 if (mask
== M_BLTL_I
)
2050 if (imm_expr
.X_add_number
== 0)
2052 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2053 likely
? "bltzl" : "bltz",
2057 if (imm_expr
.X_add_number
== 1)
2059 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2060 likely
? "blezl" : "blez",
2064 set_at (&icnt
, sreg
, 0);
2065 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2066 likely
? "bnel" : "bne",
2075 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2076 likely
? "beql" : "beq",
2082 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
2084 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2085 likely
? "beql" : "beq",
2092 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
2094 imm_expr
.X_add_number
++;
2098 if (mask
== M_BLTUL_I
)
2100 if (imm_expr
.X_add_number
== 0)
2102 if (imm_expr
.X_add_number
== 1)
2104 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2105 likely
? "beql" : "beq",
2109 set_at (&icnt
, sreg
, 1);
2110 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2111 likely
? "bnel" : "bne",
2120 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2121 likely
? "bltzl" : "bltz",
2127 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2128 likely
? "bgtzl" : "bgtz",
2132 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
2133 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2134 likely
? "bnel" : "bne",
2145 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2146 likely
? "bnel" : "bne",
2150 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
2152 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2153 likely
? "bnel" : "bne",
2169 as_warn ("Divide by zero.");
2171 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2173 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2177 mips_emit_delays ();
2179 mips_any_noreorder
= 1;
2180 macro_build ((char *) NULL
, &icnt
, NULL
,
2181 dbl
? "ddiv" : "div",
2182 "z,s,t", sreg
, treg
);
2184 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2187 expr1
.X_add_number
= 8;
2188 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2189 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2190 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2192 expr1
.X_add_number
= -1;
2193 macro_build ((char *) NULL
, &icnt
, &expr1
,
2194 dbl
? "daddiu" : "addiu",
2195 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
2196 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
2197 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
2200 expr1
.X_add_number
= 1;
2201 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
2202 (int) BFD_RELOC_LO16
);
2203 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
2208 expr1
.X_add_number
= 0x80000000;
2209 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
);
2212 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
2215 expr1
.X_add_number
= 8;
2216 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
2217 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2218 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
2221 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
2260 if (imm_expr
.X_add_number
== 0)
2262 as_warn ("Divide by zero.");
2264 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
2266 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2269 if (imm_expr
.X_add_number
== 1)
2271 if (strcmp (s2
, "mflo") == 0)
2272 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
2275 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2278 if (imm_expr
.X_add_number
== -1
2279 && s
[strlen (s
) - 1] != 'u')
2281 if (strcmp (s2
, "mflo") == 0)
2284 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
2287 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
2291 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
2295 load_register (&icnt
, AT
, &imm_expr
);
2296 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
2297 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2316 mips_emit_delays ();
2318 mips_any_noreorder
= 1;
2319 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
2321 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
2324 expr1
.X_add_number
= 8;
2325 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
2326 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
2327 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
2330 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
2334 /* Load the address of a symbol into a register. If breg is not
2335 zero, we then add a base register to it. */
2336 if (offset_expr
.X_op
!= O_symbol
2337 && offset_expr
.X_op
!= O_constant
)
2339 as_bad ("expression too complex");
2340 offset_expr
.X_op
= O_constant
;
2354 if (offset_expr
.X_op
== O_constant
)
2355 load_register (&icnt
, tempreg
, &offset_expr
);
2356 else if (mips_pic
== NO_PIC
)
2358 /* If this is a reference to an GP relative symbol, we want
2359 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2361 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2362 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2363 If we have a constant, we need two instructions anyhow,
2364 so we may as well always use the latter form. */
2365 if (offset_expr
.X_add_number
!= 0)
2370 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2371 mips_isa
< 3 ? "addiu" : "daddiu",
2372 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2373 p
= frag_var (rs_machine_dependent
, 8, 0,
2374 RELAX_ENCODE (4, 8, 0, 4, 0,
2375 mips_warn_about_macros
),
2376 offset_expr
.X_add_symbol
, (long) 0,
2379 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2382 macro_build (p
, &icnt
, &offset_expr
,
2383 mips_isa
< 3 ? "addiu" : "daddiu",
2384 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2386 else if (mips_pic
== SVR4_PIC
)
2388 /* If this is a reference to an external symbol, and there
2389 is no constant, we want
2390 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2391 For a local symbol, we want
2392 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2394 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2396 If we have a small constant, and this is a reference to
2397 an external symbol, we want
2398 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2400 addiu $tempreg,$tempreg,<constant>
2401 For a local symbol, we want the same instruction
2402 sequence, but we output a BFD_RELOC_LO16 reloc on the
2405 If we have a large constant, and this is a reference to
2406 an external symbol, we want
2407 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2408 lui $at,<hiconstant>
2409 addiu $at,$at,<loconstant>
2410 addu $tempreg,$tempreg,$at
2411 For a local symbol, we want the same instruction
2412 sequence, but we output a BFD_RELOC_LO16 reloc on the
2413 addiu instruction. */
2414 expr1
.X_add_number
= offset_expr
.X_add_number
;
2415 offset_expr
.X_add_number
= 0;
2417 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2418 mips_isa
< 3 ? "lw" : "ld",
2419 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2420 if (expr1
.X_add_number
== 0)
2428 /* We're going to put in an addu instruction using
2429 tempreg, so we may as well insert the nop right
2431 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2435 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
2436 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
2438 ? mips_warn_about_macros
2440 offset_expr
.X_add_symbol
, (long) 0,
2444 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
2447 macro_build (p
, &icnt
, &expr1
,
2448 mips_isa
< 3 ? "addiu" : "daddiu",
2449 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2450 /* FIXME: If breg == 0, and the next instruction uses
2451 $tempreg, then if this variant case is used an extra
2452 nop will be generated. */
2454 else if (expr1
.X_add_number
>= -0x8000
2455 && expr1
.X_add_number
< 0x8000)
2457 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2459 macro_build ((char *) NULL
, &icnt
, &expr1
,
2460 mips_isa
< 3 ? "addiu" : "daddiu",
2461 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2462 (void) frag_var (rs_machine_dependent
, 0, 0,
2463 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
2464 offset_expr
.X_add_symbol
, (long) 0,
2471 /* If we are going to add in a base register, and the
2472 target register and the base register are the same,
2473 then we are using AT as a temporary register. Since
2474 we want to load the constant into AT, we add our
2475 current AT (from the global offset table) and the
2476 register into the register now, and pretend we were
2477 not using a base register. */
2482 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2484 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2485 mips_isa
< 3 ? "addu" : "daddu",
2486 "d,v,t", treg
, AT
, breg
);
2492 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
2493 macro_build ((char *) NULL
, &icnt
, &expr1
,
2494 mips_isa
< 3 ? "addiu" : "daddiu",
2495 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
2496 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2497 mips_isa
< 3 ? "addu" : "daddu",
2498 "d,v,t", tempreg
, tempreg
, AT
);
2499 (void) frag_var (rs_machine_dependent
, 0, 0,
2500 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
2501 offset_expr
.X_add_symbol
, (long) 0,
2506 else if (mips_pic
== EMBEDDED_PIC
)
2509 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2511 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2512 mips_isa
< 3 ? "addiu" : "daddiu",
2513 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2519 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2520 mips_isa
< 3 ? "addu" : "daddu",
2521 "d,v,t", treg
, tempreg
, breg
);
2529 /* The j instruction may not be used in PIC code, since it
2530 requires an absolute address. We convert it to a b
2532 if (mips_pic
== NO_PIC
)
2533 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
2535 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
2538 /* The jal instructions must be handled as macros because when
2539 generating PIC code they expand to multi-instruction
2540 sequences. Normally they are simple instructions. */
2545 if (mips_pic
== NO_PIC
2546 || mips_pic
== EMBEDDED_PIC
)
2547 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2549 else if (mips_pic
== SVR4_PIC
)
2551 if (sreg
!= PIC_CALL_REG
)
2552 as_warn ("MIPS PIC call to register other than $25");
2554 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
2556 if (mips_cprestore_offset
< 0)
2557 as_warn ("No .cprestore pseudo-op used in PIC code");
2560 expr1
.X_add_number
= mips_cprestore_offset
;
2561 macro_build ((char *) NULL
, &icnt
, &expr1
,
2562 mips_isa
< 3 ? "lw" : "ld",
2563 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
2572 if (mips_pic
== NO_PIC
)
2573 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
2574 else if (mips_pic
== SVR4_PIC
)
2576 /* If this is a reference to an external symbol, we want
2577 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
2581 lw $gp,cprestore($sp)
2582 The cprestore value is set using the .cprestore
2583 pseudo-op. If the symbol is not external, we want
2584 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2586 addiu $25,$25,<sym> (BFD_RELOC_LO16)
2589 lw $gp,cprestore($sp)
2592 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2593 mips_isa
< 3 ? "lw" : "ld",
2594 "t,o(b)", PIC_CALL_REG
,
2595 (int) BFD_RELOC_MIPS_CALL16
, GP
);
2596 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2597 p
= frag_var (rs_machine_dependent
, 4, 0,
2598 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2599 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
2600 macro_build (p
, &icnt
, &offset_expr
,
2601 mips_isa
< 3 ? "addiu" : "daddiu",
2602 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
2603 (int) BFD_RELOC_LO16
);
2604 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2605 "jalr", "s", PIC_CALL_REG
);
2606 if (mips_cprestore_offset
< 0)
2607 as_warn ("No .cprestore pseudo-op used in PIC code");
2611 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2613 expr1
.X_add_number
= mips_cprestore_offset
;
2614 macro_build ((char *) NULL
, &icnt
, &expr1
,
2615 mips_isa
< 3 ? "lw" : "ld",
2616 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
2620 else if (mips_pic
== EMBEDDED_PIC
)
2622 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
2623 /* The linker may expand the call to a longer sequence which
2624 uses $at, so we must break rather than return. */
2696 if (breg
== treg
|| coproc
)
2765 if (mask
== M_LWC1_AB
2766 || mask
== M_SWC1_AB
2767 || mask
== M_LDC1_AB
2768 || mask
== M_SDC1_AB
2777 if (offset_expr
.X_op
!= O_constant
2778 && offset_expr
.X_op
!= O_symbol
)
2780 as_bad ("expression too complex");
2781 offset_expr
.X_op
= O_constant
;
2784 /* A constant expression in PIC code can be handled just as it
2785 is in non PIC code. */
2786 if (mips_pic
== NO_PIC
2787 || offset_expr
.X_op
== O_constant
)
2789 /* If this is a reference to a GP relative symbol, and there
2790 is no base register, we want
2791 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2792 Otherwise, if there is no base register, we want
2793 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2794 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2795 If we have a constant, we need two instructions anyhow,
2796 so we always use the latter form.
2798 If we have a base register, and this is a reference to a
2799 GP relative symbol, we want
2800 addu $tempreg,$breg,$gp
2801 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2803 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
2804 addu $tempreg,$tempreg,$breg
2805 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
2806 With a constant we always use the latter case. */
2809 if (offset_expr
.X_add_number
!= 0)
2814 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2815 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2816 p
= frag_var (rs_machine_dependent
, 8, 0,
2817 RELAX_ENCODE (4, 8, 0, 4, 0,
2818 (mips_warn_about_macros
2819 || (used_at
&& mips_noat
))),
2820 offset_expr
.X_add_symbol
, (long) 0,
2824 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2827 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2828 (int) BFD_RELOC_LO16
, tempreg
);
2832 if (offset_expr
.X_add_number
!= 0)
2837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2838 mips_isa
< 3 ? "addu" : "daddu",
2839 "d,v,t", tempreg
, breg
, GP
);
2840 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2841 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2842 p
= frag_var (rs_machine_dependent
, 12, 0,
2843 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
2844 offset_expr
.X_add_symbol
, (long) 0,
2847 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
2850 macro_build (p
, &icnt
, (expressionS
*) NULL
,
2851 mips_isa
< 3 ? "addu" : "daddu",
2852 "d,v,t", tempreg
, tempreg
, breg
);
2855 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
2856 (int) BFD_RELOC_LO16
, tempreg
);
2859 else if (mips_pic
== SVR4_PIC
)
2861 /* If this is a reference to an external symbol, we want
2862 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2864 <op> $treg,0($tempreg)
2866 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2868 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
2869 <op> $treg,0($tempreg)
2870 If there is a base register, we add it to $tempreg before
2871 the <op>. If there is a constant, we stick it in the
2872 <op> instruction. We don't handle constants larger than
2873 16 bits, because we have no way to load the upper 16 bits
2874 (actually, we could handle them for the subset of cases
2875 in which we are not using $at). */
2876 assert (offset_expr
.X_op
== O_symbol
);
2877 expr1
.X_add_number
= offset_expr
.X_add_number
;
2878 offset_expr
.X_add_number
= 0;
2879 if (expr1
.X_add_number
< -0x8000
2880 || expr1
.X_add_number
>= 0x8000)
2881 as_bad ("PIC code offset overflow (max 16 signed bits)");
2883 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2884 mips_isa
< 3 ? "lw" : "ld",
2885 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2886 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
2887 p
= frag_var (rs_machine_dependent
, 4, 0,
2888 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
2889 offset_expr
.X_add_symbol
, (long) 0,
2891 macro_build (p
, &icnt
, &offset_expr
,
2892 mips_isa
< 3 ? "addiu" : "daddiu",
2893 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
2895 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2896 mips_isa
< 3 ? "addu" : "daddu",
2897 "d,v,t", tempreg
, tempreg
, breg
);
2898 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
2899 (int) BFD_RELOC_LO16
, tempreg
);
2901 else if (mips_pic
== EMBEDDED_PIC
)
2903 /* If there is no base register, we want
2904 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
2905 If there is a base register, we want
2906 addu $tempreg,$breg,$gp
2907 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
2909 assert (offset_expr
.X_op
== O_symbol
);
2912 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2913 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
2918 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
2919 mips_isa
< 3 ? "addu" : "daddu",
2920 "d,v,t", tempreg
, breg
, GP
);
2921 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
2922 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
2935 load_register (&icnt
, treg
, &imm_expr
);
2939 if (mips_pic
== NO_PIC
)
2941 assert (offset_expr
.X_op
== O_symbol
2942 && strcmp (segment_name (S_GET_SEGMENT
2943 (offset_expr
.X_add_symbol
)),
2945 && offset_expr
.X_add_number
== 0);
2946 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
2947 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
2949 else if (mips_pic
== SVR4_PIC
2950 || mips_pic
== EMBEDDED_PIC
)
2952 assert (imm_expr
.X_op
== O_constant
);
2953 load_register (&icnt
, treg
, &imm_expr
);
2961 /* We know that sym is in the .rdata section. First we get the
2962 upper 16 bits of the address. */
2963 if (mips_pic
== NO_PIC
)
2965 /* FIXME: This won't work for a 64 bit address. */
2966 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
2968 else if (mips_pic
== SVR4_PIC
)
2970 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2971 mips_isa
< 3 ? "lw" : "ld",
2972 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2974 else if (mips_pic
== EMBEDDED_PIC
)
2976 /* For embedded PIC we pick up the entire address off $gp in
2977 a single instruction. */
2978 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
2979 mips_isa
< 3 ? "addiu" : "daddiu",
2980 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2981 offset_expr
.X_op
= O_constant
;
2982 offset_expr
.X_add_number
= 0;
2987 /* Now we load the register(s). */
2989 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
2990 treg
, (int) BFD_RELOC_LO16
, AT
);
2993 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
2994 treg
, (int) BFD_RELOC_LO16
, AT
);
2997 /* FIXME: How in the world do we deal with the possible
2999 offset_expr
.X_add_number
+= 4;
3000 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
3001 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
3008 if (mips_pic
== NO_PIC
3009 || mips_pic
== EMBEDDED_PIC
)
3011 /* Load a floating point number from the .lit8 section. */
3012 assert (offset_expr
.X_op
== O_symbol
3013 && strcmp (segment_name (S_GET_SEGMENT
3014 (offset_expr
.X_add_symbol
)),
3016 && offset_expr
.X_add_number
== 0);
3019 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3020 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
3024 r
= BFD_RELOC_MIPS_LITERAL
;
3027 else if (mips_pic
== SVR4_PIC
)
3029 /* Load the double from the .rdata section. */
3030 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3031 mips_isa
< 3 ? "lw" : "ld",
3032 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3035 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
3036 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, GP
);
3047 /* Even on a big endian machine $fn comes before $fn+1. We have
3048 to adjust when loading from memory. */
3051 assert (mips_isa
< 2);
3052 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3053 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3055 /* FIXME: A possible overflow which I don't know how to deal
3057 offset_expr
.X_add_number
+= 4;
3058 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
3059 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3067 * The MIPS assembler seems to check for X_add_number not
3068 * being double aligned and generating:
3071 * addiu at,at,%lo(foo+1)
3074 * But, the resulting address is the same after relocation so why
3075 * generate the extra instruction?
3122 if (offset_expr
.X_op
!= O_symbol
3123 && offset_expr
.X_op
!= O_constant
)
3125 as_bad ("expression too complex");
3126 offset_expr
.X_op
= O_constant
;
3129 /* Even on a big endian machine $fn comes before $fn+1. We have
3130 to adjust when loading from memory. We set coproc if we must
3131 load $fn+1 first. */
3132 if (byte_order
== LITTLE_ENDIAN
)
3135 if (mips_pic
== NO_PIC
3136 || offset_expr
.X_op
== O_constant
)
3138 /* If this is a reference to a GP relative symbol, we want
3139 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3140 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3141 If we have a base register, we use this
3143 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3144 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3145 If this is not a GP relative symbol, we want
3146 lui $at,<sym> (BFD_RELOC_HI16_S)
3147 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3148 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3149 If there is a base register, we add it to $at after the
3150 lui instruction. If there is a constant, we always use
3152 if (offset_expr
.X_add_number
!= 0)
3171 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3172 mips_isa
< 3 ? "addu" : "daddu",
3173 "d,v,t", AT
, breg
, GP
);
3179 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3180 coproc
? treg
+ 1 : treg
,
3181 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3182 offset_expr
.X_add_number
+= 4;
3183 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3184 coproc
? treg
: treg
+ 1,
3185 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3186 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3187 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
3188 used_at
&& mips_noat
),
3189 offset_expr
.X_add_symbol
, (long) 0,
3192 /* We just generated two relocs. When tc_gen_reloc
3193 handles this case, it will skip the first reloc and
3194 handle the second. The second reloc already has an
3195 extra addend of 4, which we added above. We must
3196 subtract it out, and then subtract another 4 to make
3197 the first reloc come out right. The second reloc
3198 will come out right because we are going to add 4 to
3199 offset_expr when we build its instruction below. */
3200 offset_expr
.X_add_number
-= 8;
3201 offset_expr
.X_op
= O_constant
;
3203 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
3208 macro_build (p
, &icnt
, (expressionS
*) NULL
,
3209 mips_isa
< 3 ? "addu" : "daddu",
3210 "d,v,t", AT
, breg
, AT
);
3214 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3215 coproc
? treg
+ 1 : treg
,
3216 (int) BFD_RELOC_LO16
, AT
);
3219 /* FIXME: How do we handle overflow here? */
3220 offset_expr
.X_add_number
+= 4;
3221 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
3222 coproc
? treg
: treg
+ 1,
3223 (int) BFD_RELOC_LO16
, AT
);
3225 else if (mips_pic
== SVR4_PIC
)
3229 /* If this is a reference to an external symbol, we want
3230 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3235 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3237 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
3238 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
3239 If there is a base register we add it to $at before the
3240 lwc1 instructions. If there is a constant we include it
3241 in the lwc1 instructions. */
3243 expr1
.X_add_number
= offset_expr
.X_add_number
;
3244 offset_expr
.X_add_number
= 0;
3245 if (expr1
.X_add_number
< -0x8000
3246 || expr1
.X_add_number
>= 0x8000 - 4)
3247 as_bad ("PIC code offset overflow (max 16 signed bits)");
3252 frag_grow (24 + off
);
3253 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3254 mips_isa
< 3 ? "lw" : "ld",
3255 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3256 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
3258 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3259 mips_isa
< 3 ? "addu" : "daddu",
3260 "d,v,t", AT
, breg
, AT
);
3261 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3262 coproc
? treg
+ 1 : treg
,
3263 (int) BFD_RELOC_LO16
, AT
);
3264 expr1
.X_add_number
+= 4;
3265 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
3266 coproc
? treg
: treg
+ 1,
3267 (int) BFD_RELOC_LO16
, AT
);
3268 (void) frag_var (rs_machine_dependent
, 0, 0,
3269 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
3270 offset_expr
.X_add_symbol
, (long) 0,
3273 else if (mips_pic
== EMBEDDED_PIC
)
3275 /* If there is no base register, we use
3276 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
3277 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
3278 If we have a base register, we use
3280 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
3281 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
3290 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3291 mips_isa
< 3 ? "addu" : "daddu",
3292 "d,v,t", AT
, breg
, GP
);
3297 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3298 coproc
? treg
+ 1 : treg
,
3299 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3300 offset_expr
.X_add_number
+= 4;
3301 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
3302 coproc
? treg
: treg
+ 1,
3303 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
3319 assert (mips_isa
< 3);
3320 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3321 (int) BFD_RELOC_LO16
, breg
);
3322 offset_expr
.X_add_number
+= 4;
3323 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
3324 (int) BFD_RELOC_LO16
, breg
);
3326 #ifdef LOSING_COMPILER
3332 as_warn ("Macro used $at after \".set noat\"");
3337 struct mips_cl_insn
*ip
;
3339 register int treg
, sreg
, dreg
, breg
;
3352 bfd_reloc_code_real_type r
;
3355 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3356 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3357 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3358 mask
= ip
->insn_mo
->mask
;
3360 expr1
.X_op
= O_constant
;
3361 expr1
.X_op_symbol
= NULL
;
3362 expr1
.X_add_symbol
= NULL
;
3363 expr1
.X_add_number
= 1;
3367 #endif /* LOSING_COMPILER */
3372 macro_build ((char *) NULL
, &icnt
, NULL
,
3373 dbl
? "dmultu" : "multu",
3375 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3381 /* The MIPS assembler some times generates shifts and adds. I'm
3382 not trying to be that fancy. GCC should do this for us
3384 load_register (&icnt
, AT
, &imm_expr
);
3385 macro_build ((char *) NULL
, &icnt
, NULL
,
3386 dbl
? "dmult" : "mult",
3388 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3394 mips_emit_delays ();
3396 mips_any_noreorder
= 1;
3397 macro_build ((char *) NULL
, &icnt
, NULL
,
3398 dbl
? "dmult" : "mult",
3400 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3401 macro_build ((char *) NULL
, &icnt
, NULL
,
3402 dbl
? "dsra32" : "sra",
3403 "d,w,<", dreg
, dreg
, 31);
3404 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3406 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
3409 expr1
.X_add_number
= 8;
3410 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
3411 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3412 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3415 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3421 mips_emit_delays ();
3423 mips_any_noreorder
= 1;
3424 macro_build ((char *) NULL
, &icnt
, NULL
,
3425 dbl
? "dmultu" : "multu",
3427 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
3428 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
3430 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
3433 expr1
.X_add_number
= 8;
3434 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
3435 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3436 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3442 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3443 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
3444 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
3446 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3450 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
3451 imm_expr
.X_add_number
& 0x1f);
3452 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
3453 (0 - imm_expr
.X_add_number
) & 0x1f);
3454 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3458 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
3459 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
3460 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
3462 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3466 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
3467 imm_expr
.X_add_number
& 0x1f);
3468 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
3469 (0 - imm_expr
.X_add_number
) & 0x1f);
3470 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
3474 assert (mips_isa
< 2);
3475 /* Even on a big endian machine $fn comes before $fn+1. We have
3476 to adjust when storing to memory. */
3477 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3478 byte_order
== LITTLE_ENDIAN
? treg
: treg
+ 1,
3479 (int) BFD_RELOC_LO16
, breg
);
3480 offset_expr
.X_add_number
+= 4;
3481 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
3482 byte_order
== LITTLE_ENDIAN
? treg
+ 1 : treg
,
3483 (int) BFD_RELOC_LO16
, breg
);
3488 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3489 treg
, (int) BFD_RELOC_LO16
);
3491 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3492 sreg
, (int) BFD_RELOC_LO16
);
3495 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3497 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3498 dreg
, (int) BFD_RELOC_LO16
);
3503 if (imm_expr
.X_add_number
== 0)
3505 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
3506 sreg
, (int) BFD_RELOC_LO16
);
3511 as_warn ("Instruction %s: result is always false",
3513 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3516 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3518 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
3519 sreg
, (int) BFD_RELOC_LO16
);
3522 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3524 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3525 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3526 mips_isa
< 3 ? "addiu" : "daddiu",
3527 "t,r,j", dreg
, sreg
,
3528 (int) BFD_RELOC_LO16
);
3533 load_register (&icnt
, AT
, &imm_expr
);
3534 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3538 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
3539 (int) BFD_RELOC_LO16
);
3544 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
3550 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
3551 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3552 (int) BFD_RELOC_LO16
);
3555 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
3557 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3559 macro_build ((char *) NULL
, &icnt
, &expr1
,
3560 mask
== M_SGE_I
? "slti" : "sltiu",
3561 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3566 load_register (&icnt
, AT
, &imm_expr
);
3567 macro_build ((char *) NULL
, &icnt
, NULL
,
3568 mask
== M_SGE_I
? "slt" : "sltu",
3569 "d,v,t", dreg
, sreg
, AT
);
3572 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3573 (int) BFD_RELOC_LO16
);
3578 case M_SGT
: /* sreg > treg <==> treg < sreg */
3584 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3587 case M_SGT_I
: /* sreg > I <==> I < sreg */
3593 load_register (&icnt
, AT
, &imm_expr
);
3594 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3597 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
3603 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
3604 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3605 (int) BFD_RELOC_LO16
);
3608 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
3614 load_register (&icnt
, AT
, &imm_expr
);
3615 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
3616 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
3617 (int) BFD_RELOC_LO16
);
3621 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3623 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
3624 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3627 load_register (&icnt
, AT
, &imm_expr
);
3628 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
3632 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3634 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
3635 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3638 load_register (&icnt
, AT
, &imm_expr
);
3639 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
3645 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3648 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3652 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3654 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3660 if (imm_expr
.X_add_number
== 0)
3662 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
3668 as_warn ("Instruction %s: result is always true",
3670 macro_build ((char *) NULL
, &icnt
, &expr1
,
3671 mips_isa
< 3 ? "addiu" : "daddiu",
3672 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
3675 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3677 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
3678 dreg
, sreg
, (int) BFD_RELOC_LO16
);
3681 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
3683 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3684 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3685 mips_isa
< 3 ? "addiu" : "daddiu",
3686 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3691 load_register (&icnt
, AT
, &imm_expr
);
3692 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
3696 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
3704 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3706 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3707 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3708 dbl
? "daddi" : "addi",
3709 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3712 load_register (&icnt
, AT
, &imm_expr
);
3713 macro_build ((char *) NULL
, &icnt
, NULL
,
3714 dbl
? "dsub" : "sub",
3715 "d,v,t", dreg
, sreg
, AT
);
3721 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
3723 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
3724 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
3725 dbl
? "daddiu" : "addiu",
3726 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
3729 load_register (&icnt
, AT
, &imm_expr
);
3730 macro_build ((char *) NULL
, &icnt
, NULL
,
3731 dbl
? "dsubu" : "subu",
3732 "d,v,t", dreg
, sreg
, AT
);
3753 load_register (&icnt
, AT
, &imm_expr
);
3754 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
3759 assert (mips_isa
< 2);
3760 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
3761 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
3764 * Is the double cfc1 instruction a bug in the mips assembler;
3765 * or is there a reason for it?
3767 mips_emit_delays ();
3769 mips_any_noreorder
= 1;
3770 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3771 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
3772 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3773 expr1
.X_add_number
= 3;
3774 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
3775 (int) BFD_RELOC_LO16
);
3776 expr1
.X_add_number
= 2;
3777 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
3778 (int) BFD_RELOC_LO16
);
3779 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
3780 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3781 macro_build ((char *) NULL
, &icnt
, NULL
,
3782 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
3783 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
3784 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
3794 if (offset_expr
.X_add_number
>= 0x7fff)
3795 as_bad ("operand overflow");
3796 /* avoid load delay */
3797 if (byte_order
== LITTLE_ENDIAN
)
3798 offset_expr
.X_add_number
+= 1;
3799 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
3800 (int) BFD_RELOC_LO16
, breg
);
3801 if (byte_order
== LITTLE_ENDIAN
)
3802 offset_expr
.X_add_number
-= 1;
3804 offset_expr
.X_add_number
+= 1;
3805 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
3806 (int) BFD_RELOC_LO16
, breg
);
3807 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
3808 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
3812 if (offset_expr
.X_add_number
>= 0x7ffd)
3813 as_bad ("operand overflow");
3814 if (byte_order
== LITTLE_ENDIAN
)
3815 offset_expr
.X_add_number
+= 3;
3816 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwl", "t,o(b)", treg
,
3817 (int) BFD_RELOC_LO16
, breg
);
3818 if (byte_order
== LITTLE_ENDIAN
)
3819 offset_expr
.X_add_number
-= 3;
3821 offset_expr
.X_add_number
+= 3;
3822 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwr", "t,o(b)", treg
,
3823 (int) BFD_RELOC_LO16
, breg
);
3829 load_address (&icnt
, AT
, &offset_expr
);
3830 if (mask
== M_ULW_A
)
3832 if (byte_order
== LITTLE_ENDIAN
)
3833 expr1
.X_add_number
= 3;
3835 expr1
.X_add_number
= 0;
3836 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwl", "t,o(b)", treg
,
3837 (int) BFD_RELOC_LO16
, AT
);
3838 if (byte_order
== LITTLE_ENDIAN
)
3839 expr1
.X_add_number
= 0;
3841 expr1
.X_add_number
= 3;
3842 macro_build ((char *) NULL
, &icnt
, &expr1
, "lwr", "t,o(b)", treg
,
3843 (int) BFD_RELOC_LO16
, AT
);
3847 if (byte_order
== BIG_ENDIAN
)
3848 expr1
.X_add_number
= 0;
3849 macro_build ((char *) NULL
, &icnt
, &expr1
,
3850 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
3851 (int) BFD_RELOC_LO16
, AT
);
3852 if (byte_order
== BIG_ENDIAN
)
3853 expr1
.X_add_number
= 1;
3855 expr1
.X_add_number
= 0;
3856 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3857 (int) BFD_RELOC_LO16
, AT
);
3858 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3860 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3866 if (offset_expr
.X_add_number
>= 0x7fff)
3867 as_bad ("operand overflow");
3868 if (byte_order
== BIG_ENDIAN
)
3869 offset_expr
.X_add_number
+= 1;
3870 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
3871 (int) BFD_RELOC_LO16
, breg
);
3872 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
3873 if (byte_order
== BIG_ENDIAN
)
3874 offset_expr
.X_add_number
-= 1;
3876 offset_expr
.X_add_number
+= 1;
3877 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
3878 (int) BFD_RELOC_LO16
, breg
);
3882 if (offset_expr
.X_add_number
>= 0x7ffd)
3883 as_bad ("operand overflow");
3884 if (byte_order
== LITTLE_ENDIAN
)
3885 offset_expr
.X_add_number
+= 3;
3886 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swl", "t,o(b)", treg
,
3887 (int) BFD_RELOC_LO16
, breg
);
3888 if (byte_order
== LITTLE_ENDIAN
)
3889 offset_expr
.X_add_number
-= 3;
3891 offset_expr
.X_add_number
+= 3;
3892 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swr", "t,o(b)", treg
,
3893 (int) BFD_RELOC_LO16
, breg
);
3898 load_address (&icnt
, AT
, &offset_expr
);
3899 if (mask
== M_USW_A
)
3901 if (byte_order
== LITTLE_ENDIAN
)
3902 expr1
.X_add_number
= 3;
3904 expr1
.X_add_number
= 0;
3905 macro_build ((char *) NULL
, &icnt
, &expr1
, "swl", "t,o(b)", treg
,
3906 (int) BFD_RELOC_LO16
, AT
);
3907 if (byte_order
== LITTLE_ENDIAN
)
3908 expr1
.X_add_number
= 0;
3910 expr1
.X_add_number
= 3;
3911 macro_build ((char *) NULL
, &icnt
, &expr1
, "swr", "t,o(b)", treg
,
3912 (int) BFD_RELOC_LO16
, AT
);
3916 if (byte_order
== LITTLE_ENDIAN
)
3917 expr1
.X_add_number
= 0;
3918 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3919 (int) BFD_RELOC_LO16
, AT
);
3920 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
3922 if (byte_order
== LITTLE_ENDIAN
)
3923 expr1
.X_add_number
= 1;
3925 expr1
.X_add_number
= 0;
3926 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
3927 (int) BFD_RELOC_LO16
, AT
);
3928 if (byte_order
== LITTLE_ENDIAN
)
3929 expr1
.X_add_number
= 0;
3931 expr1
.X_add_number
= 1;
3932 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
3933 (int) BFD_RELOC_LO16
, AT
);
3934 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
3936 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
3942 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
3946 as_warn ("Macro used $at after \".set noat\"");
3951 This routine assembles an instruction into its binary format. As a side
3952 effect it sets one of the global variables imm_reloc or offset_reloc to the
3953 type of relocation to do if one of the operands is an address expression.
3958 struct mips_cl_insn
*ip
;
3963 struct mips_opcode
*insn
;
3966 unsigned int lastregno
= 0;
3971 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '.'; ++s
)
3983 as_warn ("Unknown opcode: `%s'", str
);
3986 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
3988 as_warn ("`%s' not in hash table.", str
);
3989 insn_error
= "ERROR: Unrecognized opcode";
3997 assert (strcmp (insn
->name
, str
) == 0);
3999 if (insn
->pinfo
== INSN_MACRO
)
4000 insn_isa
= insn
->match
;
4001 else if (insn
->pinfo
& INSN_ISA2
)
4003 else if (insn
->pinfo
& INSN_ISA3
)
4008 if (insn_isa
> mips_isa
)
4010 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
4011 && strcmp (insn
->name
, insn
[1].name
) == 0)
4016 as_warn ("Instruction not supported on this processor");
4020 ip
->insn_opcode
= insn
->match
;
4021 for (args
= insn
->args
;; ++args
)
4027 case '\0': /* end of args */
4040 ip
->insn_opcode
|= lastregno
<< 21;
4045 ip
->insn_opcode
|= lastregno
<< 16;
4049 ip
->insn_opcode
|= lastregno
<< 11;
4055 /* handle optional base register.
4056 Either the base register is omitted or
4057 we must have a left paren. */
4058 /* this is dependent on the next operand specifier
4059 is a 'b' for base register */
4060 assert (args
[1] == 'b');
4064 case ')': /* these must match exactly */
4069 case '<': /* must be at least one digit */
4071 * According to the manual, if the shift amount is greater
4072 * than 31 or less than 0 the the shift amount should be
4073 * mod 32. In reality the mips assembler issues an error.
4074 * We issue a warning and mask out all but the low 5 bits.
4076 my_getExpression (&imm_expr
, s
);
4077 check_absolute_expr (ip
, &imm_expr
);
4078 if ((unsigned long) imm_expr
.X_add_number
> 31)
4080 as_warn ("Improper shift amount (%ld)",
4081 (long) imm_expr
.X_add_number
);
4082 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
4084 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4085 imm_expr
.X_op
= O_absent
;
4089 case '>': /* shift amount minus 32 */
4090 my_getExpression (&imm_expr
, s
);
4091 check_absolute_expr (ip
, &imm_expr
);
4092 if ((unsigned long) imm_expr
.X_add_number
< 32
4093 || (unsigned long) imm_expr
.X_add_number
> 63)
4095 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
4096 imm_expr
.X_op
= O_absent
;
4100 case 'k': /* cache code */
4101 my_getExpression (&imm_expr
, s
);
4102 check_absolute_expr (ip
, &imm_expr
);
4103 if ((unsigned long) imm_expr
.X_add_number
> 31)
4105 as_warn ("Invalid cahce opcode (%lu)",
4106 (unsigned long) imm_expr
.X_add_number
);
4107 imm_expr
.X_add_number
&= 0x1f;
4109 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
4110 imm_expr
.X_op
= O_absent
;
4114 case 'c': /* break code */
4115 my_getExpression (&imm_expr
, s
);
4116 check_absolute_expr (ip
, &imm_expr
);
4117 if ((unsigned) imm_expr
.X_add_number
> 1023)
4118 as_warn ("Illegal break code (%ld)",
4119 (long) imm_expr
.X_add_number
);
4120 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
4121 imm_expr
.X_op
= O_absent
;
4125 case 'B': /* syscall code */
4126 my_getExpression (&imm_expr
, s
);
4127 check_absolute_expr (ip
, &imm_expr
);
4128 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
4129 as_warn ("Illegal syscall code (%ld)",
4130 (long) imm_expr
.X_add_number
);
4131 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
4132 imm_expr
.X_op
= O_absent
;
4136 case 'C': /* Coprocessor code */
4137 my_getExpression (&imm_expr
, s
);
4138 check_absolute_expr (ip
, &imm_expr
);
4139 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
4141 as_warn ("Coproccesor code > 25 bits (%ld)",
4142 (long) imm_expr
.X_add_number
);
4143 imm_expr
.X_add_number
&= ((1<<25) - 1);
4145 ip
->insn_opcode
|= imm_expr
.X_add_number
;
4146 imm_expr
.X_op
= O_absent
;
4150 case 'b': /* base register */
4151 case 'd': /* destination register */
4152 case 's': /* source register */
4153 case 't': /* target register */
4154 case 'r': /* both target and source */
4155 case 'v': /* both dest and source */
4156 case 'w': /* both dest and target */
4157 case 'E': /* coprocessor target register */
4158 case 'G': /* coprocessor destination register */
4159 case 'x': /* ignore register name */
4160 case 'z': /* must be zero register */
4174 while (isdigit (*s
));
4176 as_bad ("Invalid register number (%d)", regno
);
4178 else if (*args
== 'E' || *args
== 'G')
4182 if (s
[1] == 'f' && s
[2] == 'p')
4187 else if (s
[1] == 's' && s
[2] == 'p')
4192 else if (s
[1] == 'g' && s
[2] == 'p')
4197 else if (s
[1] == 'a' && s
[2] == 't')
4205 if (regno
== AT
&& ! mips_noat
)
4206 as_warn ("Used $at without \".set noat\"");
4212 if (c
== 'r' || c
== 'v' || c
== 'w')
4219 /* 'z' only matches $0. */
4220 if (c
== 'z' && regno
!= 0)
4228 ip
->insn_opcode
|= regno
<< 21;
4232 ip
->insn_opcode
|= regno
<< 11;
4237 ip
->insn_opcode
|= regno
<< 16;
4240 /* This case exists because on the r3000 trunc
4241 expands into a macro which requires a gp
4242 register. On the r6000 or r4000 it is
4243 assembled into a single instruction which
4244 ignores the register. Thus the insn version
4245 is MIPS_ISA2 and uses 'x', and the macro
4246 version is MIPS_ISA1 and uses 't'. */
4249 /* This case is for the div instruction, which
4250 acts differently if the destination argument
4251 is $0. This only matches $0, and is checked
4252 outside the switch. */
4263 ip
->insn_opcode
|= lastregno
<< 21;
4266 ip
->insn_opcode
|= lastregno
<< 16;
4271 case 'D': /* floating point destination register */
4272 case 'S': /* floating point source register */
4273 case 'T': /* floating point target register */
4277 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
4287 while (isdigit (*s
));
4290 as_bad ("Invalid float register number (%d)", regno
);
4292 if ((regno
& 1) != 0
4294 && ! (strcmp (str
, "mtc1") == 0 ||
4295 strcmp (str
, "mfc1") == 0 ||
4296 strcmp (str
, "lwc1") == 0 ||
4297 strcmp (str
, "swc1") == 0))
4298 as_warn ("Float register should be even, was %d",
4306 if (c
== 'V' || c
== 'W')
4316 ip
->insn_opcode
|= regno
<< 6;
4320 ip
->insn_opcode
|= regno
<< 11;
4324 ip
->insn_opcode
|= regno
<< 16;
4332 ip
->insn_opcode
|= lastregno
<< 11;
4335 ip
->insn_opcode
|= lastregno
<< 16;
4341 my_getExpression (&imm_expr
, s
);
4342 check_absolute_expr (ip
, &imm_expr
);
4347 my_getExpression (&offset_expr
, s
);
4348 imm_reloc
= BFD_RELOC_32
;
4360 unsigned char temp
[8];
4362 unsigned int length
;
4367 /* These only appear as the last operand in an
4368 instruction, and every instruction that accepts
4369 them in any variant accepts them in all variants.
4370 This means we don't have to worry about backing out
4371 any changes if the instruction does not match.
4373 The difference between them is the size of the
4374 floating point constant and where it goes. For 'F'
4375 and 'L' the constant is 64 bits; for 'f' and 'l' it
4376 is 32 bits. Where the constant is placed is based
4377 on how the MIPS assembler does things:
4380 f -- immediate value
4383 When generating SVR4 PIC code, we do not use the
4384 .lit8 or .lit4 sections at all, in order to
4385 reserve the entire global offset table. When
4386 generating embedded PIC code, we use the .lit8
4387 section but not the .lit4 section (we can do .lit4
4388 inline easily; we need to put .lit8 somewhere in
4389 the data segment, and using .lit8 permits the
4390 linker to eventually combine identical .lit8
4393 f64
= *args
== 'F' || *args
== 'L';
4395 save_in
= input_line_pointer
;
4396 input_line_pointer
= s
;
4397 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
4399 s
= input_line_pointer
;
4400 input_line_pointer
= save_in
;
4401 if (err
!= NULL
&& *err
!= '\0')
4403 as_bad ("Bad floating point constant: %s", err
);
4404 memset (temp
, '\0', sizeof temp
);
4405 length
= f64
? 8 : 4;
4408 assert (length
== (f64
? 8 : 4));
4411 || (mips_pic
!= NO_PIC
&& *args
== 'l'))
4413 imm_expr
.X_op
= O_constant
;
4414 if (byte_order
== LITTLE_ENDIAN
)
4415 imm_expr
.X_add_number
=
4416 (((((((int) temp
[3] << 8)
4421 imm_expr
.X_add_number
=
4422 (((((((int) temp
[0] << 8)
4429 const char *newname
;
4432 /* Switch to the right section. */
4434 subseg
= now_subseg
;
4437 default: /* unused default case avoids warnings. */
4439 newname
= (mips_pic
!= SVR4_PIC
? ".lit8" : ".rdata");
4445 assert (mips_pic
== NO_PIC
);
4449 new_seg
= subseg_new (newname
, (subsegT
) 0);
4451 bfd_set_section_alignment (stdoutput
, new_seg
, 4);
4454 as_bad ("Can't use floating point insn in this section");
4456 /* Set the argument to the current address in the
4458 offset_expr
.X_op
= O_symbol
;
4459 offset_expr
.X_add_symbol
=
4460 symbol_new ("L0\001", now_seg
,
4461 (valueT
) frag_now_fix (), frag_now
);
4462 offset_expr
.X_add_number
= 0;
4464 /* Put the floating point number into the section. */
4465 p
= frag_more ((int) length
);
4466 memcpy (p
, temp
, length
);
4468 /* Switch back to the original section. */
4469 subseg_set (seg
, subseg
);
4474 case 'i': /* 16 bit unsigned immediate */
4475 case 'j': /* 16 bit signed immediate */
4476 imm_reloc
= BFD_RELOC_LO16
;
4477 c
= my_getSmallExpression (&imm_expr
, s
);
4482 if (imm_expr
.X_op
== O_constant
)
4483 imm_expr
.X_add_number
=
4484 (imm_expr
.X_add_number
>> 16) & 0xffff;
4486 imm_reloc
= BFD_RELOC_HI16_S
;
4488 imm_reloc
= BFD_RELOC_HI16
;
4492 check_absolute_expr (ip
, &imm_expr
);
4495 if (imm_expr
.X_add_number
< 0
4496 || imm_expr
.X_add_number
>= 0x10000)
4498 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4499 !strcmp (insn
->name
, insn
[1].name
))
4501 as_bad ("16 bit expression not in range 0..65535");
4509 /* The upper bound should be 0x8000, but
4510 unfortunately the MIPS assembler accepts numbers
4511 from 0x8000 to 0xffff and sign extends them, and
4512 we want to be compatible. We only permit this
4513 extended range for an instruction which does not
4514 provide any further alternates, since those
4515 alternates may handle other cases. People should
4516 use the numbers they mean, rather than relying on
4517 a mysterious sign extension. */
4518 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4519 strcmp (insn
->name
, insn
[1].name
) == 0);
4524 if (imm_expr
.X_add_number
< -0x8000 ||
4525 imm_expr
.X_add_number
>= max
)
4529 as_bad ("16 bit expression not in range -32768..32767");
4535 case 'o': /* 16 bit offset */
4536 c
= my_getSmallExpression (&offset_expr
, s
);
4538 /* If this value won't fit into a 16 bit offset, then go
4539 find a macro that will generate the 32 bit offset
4540 code pattern. As a special hack, we accept the
4541 difference of two local symbols as a constant. This
4542 is required to suppose embedded PIC switches, which
4543 use an instruction which looks like
4544 lw $4,$L12-$LS12($4)
4545 The problem with handling this in a more general
4546 fashion is that the macro function doesn't expect to
4547 see anything which can be handled in a single
4548 constant instruction. */
4549 if ((offset_expr
.X_op
!= O_constant
4550 || offset_expr
.X_add_number
>= 0x8000
4551 || offset_expr
.X_add_number
< -0x8000)
4552 && (mips_pic
!= EMBEDDED_PIC
4553 || offset_expr
.X_op
!= O_subtract
4554 || ! S_IS_LOCAL (offset_expr
.X_add_symbol
)
4555 || ! S_IS_LOCAL (offset_expr
.X_op_symbol
)))
4558 offset_reloc
= BFD_RELOC_LO16
;
4559 if (c
== 'h' || c
== 'H')
4561 assert (offset_expr
.X_op
== O_constant
);
4562 offset_expr
.X_add_number
=
4563 (offset_expr
.X_add_number
>> 16) & 0xffff;
4568 case 'p': /* pc relative offset */
4569 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
4570 my_getExpression (&offset_expr
, s
);
4574 case 'u': /* upper 16 bits */
4575 c
= my_getSmallExpression (&imm_expr
, s
);
4576 if (imm_expr
.X_op
!= O_constant
4577 || imm_expr
.X_add_number
< 0
4578 || imm_expr
.X_add_number
>= 0x10000)
4579 as_bad ("lui expression not in range 0..65535");
4580 imm_reloc
= BFD_RELOC_LO16
;
4585 if (imm_expr
.X_op
== O_constant
)
4586 imm_expr
.X_add_number
=
4587 (imm_expr
.X_add_number
>> 16) & 0xffff;
4589 imm_reloc
= BFD_RELOC_HI16_S
;
4591 imm_reloc
= BFD_RELOC_HI16
;
4597 case 'a': /* 26 bit address */
4598 my_getExpression (&offset_expr
, s
);
4600 offset_reloc
= BFD_RELOC_MIPS_JMP
;
4604 fprintf (stderr
, "bad char = '%c'\n", *args
);
4609 /* Args don't match. */
4610 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
4611 !strcmp (insn
->name
, insn
[1].name
))
4617 insn_error
= "ERROR: Illegal operands";
4626 my_getSmallExpression (ep
, str
)
4637 ((str
[1] == 'h' && str
[2] == 'i')
4638 || (str
[1] == 'H' && str
[2] == 'I')
4639 || (str
[1] == 'l' && str
[2] == 'o'))
4651 * A small expression may be followed by a base register.
4652 * Scan to the end of this operand, and then back over a possible
4653 * base register. Then scan the small expression up to that
4654 * point. (Based on code in sparc.c...)
4656 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
4658 if (sp
- 4 >= str
&& sp
[-1] == RP
)
4660 if (isdigit (sp
[-2]))
4662 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
4664 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
4670 else if (sp
- 5 >= str
4673 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
4674 || (sp
[-3] == 's' && sp
[-2] == 'p')
4675 || (sp
[-3] == 'g' && sp
[-2] == 'p')
4676 || (sp
[-3] == 'a' && sp
[-2] == 't')))
4682 /* no expression means zero offset */
4685 /* %xx(reg) is an error */
4686 ep
->X_op
= O_absent
;
4691 ep
->X_op
= O_constant
;
4694 ep
->X_add_symbol
= NULL
;
4695 ep
->X_op_symbol
= NULL
;
4696 ep
->X_add_number
= 0;
4701 my_getExpression (ep
, str
);
4708 my_getExpression (ep
, str
);
4709 return c
; /* => %hi or %lo encountered */
4713 my_getExpression (ep
, str
)
4719 save_in
= input_line_pointer
;
4720 input_line_pointer
= str
;
4722 expr_end
= input_line_pointer
;
4723 input_line_pointer
= save_in
;
4726 /* Turn a string in input_line_pointer into a floating point constant
4727 of type type, and store the appropriate bytes in *litP. The number
4728 of LITTLENUMS emitted is stored in *sizeP . An error message is
4729 returned, or NULL on OK. */
4732 md_atof (type
, litP
, sizeP
)
4738 LITTLENUM_TYPE words
[4];
4754 return "bad call to md_atof";
4757 t
= atof_ieee (input_line_pointer
, type
, words
);
4759 input_line_pointer
= t
;
4763 if (byte_order
== LITTLE_ENDIAN
)
4765 for (i
= prec
- 1; i
>= 0; i
--)
4767 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4773 for (i
= 0; i
< prec
; i
++)
4775 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
4784 md_number_to_chars (buf
, val
, n
)
4792 number_to_chars_littleendian (buf
, val
, n
);
4796 number_to_chars_bigendian (buf
, val
, n
);
4805 md_parse_option (argP
, cntP
, vecP
)
4810 /* Accept -nocpp but ignore it. */
4811 if (strcmp (*argP
, "nocpp") == 0)
4817 if (strcmp (*argP
, "EL") == 0
4818 || strcmp (*argP
, "EB") == 0)
4820 if ((*argP
)[1] == 'B')
4821 byte_order
= BIG_ENDIAN
;
4823 byte_order
= LITTLE_ENDIAN
;
4826 if ((*argP
)[1] == 'B')
4827 mips_target_format
= "a.out-mips-big";
4829 mips_target_format
= "a.out-mips-little";
4832 if ((*argP
)[1] == 'B')
4833 mips_target_format
= "ecoff-bigmips";
4835 mips_target_format
= "ecoff-littlemips";
4838 if ((*argP
)[1] == 'B')
4839 mips_target_format
= "elf32-bigmips";
4841 mips_target_format
= "elf32-littlemips";
4844 /* FIXME: This breaks -L -EL. */
4852 if ((*argP
)[1] == '0')
4861 if ((*argP
)[1] == '\0' || (*argP
)[1] == '2')
4866 if (strncmp (*argP
, "mips", 4) == 0)
4868 mips_isa
= atol (*argP
+ 4);
4871 else if (mips_isa
< 1 || mips_isa
> 3)
4873 as_bad ("-mips%d not supported", mips_isa
);
4880 if (strncmp (*argP
, "mcpu=", 5) == 0)
4884 /* Identify the processor type */
4886 if (strcmp (p
, "default") == 0
4887 || strcmp (p
, "DEFAULT") == 0)
4891 if (*p
== 'r' || *p
== 'R')
4898 if (strcmp (p
, "2000") == 0
4899 || strcmp (p
, "2k") == 0
4900 || strcmp (p
, "2K") == 0)
4905 if (strcmp (p
, "3000") == 0
4906 || strcmp (p
, "3k") == 0
4907 || strcmp (p
, "3K") == 0)
4912 if (strcmp (p
, "4000") == 0
4913 || strcmp (p
, "4k") == 0
4914 || strcmp (p
, "4K") == 0)
4919 if (strcmp (p
, "6000") == 0
4920 || strcmp (p
, "6k") == 0
4921 || strcmp (p
, "6K") == 0)
4928 as_bad ("bad value (%s) for -mcpu= switch", *argP
+ 5);
4937 /* Argument -membedded-pic means to use EMBEDDED_PIC. */
4938 if (strcmp (*argP
, "membedded-pic") == 0)
4940 mips_pic
= EMBEDDED_PIC
;
4943 as_warn ("-G may not be used with embedded PIC code");
4944 g_switch_value
= 0x7fffffff;
4951 /* When generating ELF code, we permit -KPIC and -call_shared to
4952 select SVR4_PIC, and -non_shared to select no PIC. This is
4953 intended to be compatible with Irix 5. */
4954 if (strcmp (*argP
, "KPIC") == 0
4955 || strcmp (*argP
, "call_shared") == 0)
4957 mips_pic
= SVR4_PIC
;
4958 if (g_switch_seen
&& g_switch_value
!= 0)
4959 as_warn ("-G may not be used with SVR4 PIC code");
4964 else if (strcmp (*argP
, "non_shared") == 0)
4970 #endif /* OBJ_ELF */
4975 if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
4976 as_warn ("-G may not be used with SVR4 or embedded PIC code");
4977 else if ((*argP
)[1] != '\0')
4978 g_switch_value
= atoi (*argP
+ 1);
4981 **vecP
= (char *) NULL
;
4984 g_switch_value
= atoi (**vecP
);
4987 as_warn ("Number expected after -G");
4994 return 1; /* pretend you parsed the character */
4997 /* Handle a long option name. */
5000 mips_parse_long_option (arg
)
5003 if (strcmp (arg
, "--trap") == 0
5004 || strcmp (arg
, "--no-break") == 0)
5009 else if (strcmp (arg
, "--no-trap") == 0
5010 || strcmp (arg
, "--break") == 0)
5020 md_pcrel_from (fixP
)
5024 if (fixP
->fx_addsy
!= (symbolS
*) NULL
5025 && ! S_IS_DEFINED (fixP
->fx_addsy
))
5027 /* This makes a branch to an undefined symbol be a branch to the
5028 current location. */
5033 /* return the address of the delay slot */
5034 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5037 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
5038 reloc for a cons. We could use the definition there, except that
5039 we want to handle 64 bit relocs specially. */
5042 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
5045 unsigned int nbytes
;
5048 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
5050 FIXME: There is no way to select anything but 32 bit mode right
5054 if (byte_order
== BIG_ENDIAN
)
5059 if (nbytes
!= 2 && nbytes
!= 4)
5060 as_bad ("Unsupported reloc size %d", nbytes
);
5062 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
5063 nbytes
== 2 ? BFD_RELOC_16
: BFD_RELOC_32
);
5066 /* When generating embedded PIC code we need to use a special
5067 relocation to represent the difference of two symbols in the .text
5068 section (switch tables use a difference of this sort). See
5069 include/coff/mips.h for details. This macro checks whether this
5070 fixup requires the special reloc. */
5071 #define SWITCH_TABLE(fixp) \
5072 ((fixp)->fx_r_type == BFD_RELOC_32 \
5073 && (fixp)->fx_addsy != NULL \
5074 && (fixp)->fx_subsy != NULL \
5075 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
5076 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
5078 /* When generating embedded PIC code we must keep all PC relative
5079 relocations, in case the linker has to relax a call. We also need
5080 to keep relocations for switch table entries. */
5084 mips_force_relocation (fixp
)
5087 return (mips_pic
== EMBEDDED_PIC
5088 && (fixp
->fx_pcrel
|| SWITCH_TABLE (fixp
)));
5091 /* Apply a fixup to the object file. */
5094 md_apply_fix (fixP
, valueP
)
5101 assert (fixP
->fx_size
== 4);
5104 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
5106 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
5109 switch (fixP
->fx_r_type
)
5111 case BFD_RELOC_MIPS_JMP
:
5112 case BFD_RELOC_HI16
:
5113 case BFD_RELOC_HI16_S
:
5114 case BFD_RELOC_MIPS_GPREL
:
5115 case BFD_RELOC_MIPS_LITERAL
:
5116 case BFD_RELOC_MIPS_CALL16
:
5117 case BFD_RELOC_MIPS_GOT16
:
5118 case BFD_RELOC_MIPS_GPREL32
:
5119 /* Nothing needed to do. The value comes from the reloc entry */
5123 /* If we are deleting this reloc entry, we must fill in the
5124 value now. This can happen if we have a .word which is not
5125 resolved when it appears but is later defined. We also need
5126 to fill in the value if this is an embedded PIC switch table
5129 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
5130 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
5134 case BFD_RELOC_LO16
:
5135 /* When handling an embedded PIC switch statement, we can wind
5136 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
5139 if (value
< -0x8000 || value
> 0x7fff)
5140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5141 "relocation overflow");
5142 buf
= fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
5143 if (byte_order
== BIG_ENDIAN
)
5145 md_number_to_chars (buf
, value
, 2);
5149 case BFD_RELOC_16_PCREL_S2
:
5151 * We need to save the bits in the instruction since fixup_segment()
5152 * might be deleting the relocation entry (i.e., a branch within
5153 * the current segment).
5156 as_warn ("Branch to odd address (%lx)", value
);
5158 if ((value
& ~0xFFFF) && (value
& ~0xFFFF) != (-1 & ~0xFFFF))
5159 as_bad ("Relocation overflow");
5161 /* update old instruction data */
5162 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
5166 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
5170 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
5177 insn
|= value
& 0xFFFF;
5178 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
5193 const struct mips_opcode
*p
;
5194 int treg
, sreg
, dreg
, shamt
;
5199 for (i
= 0; i
< NUMOPCODES
; ++i
)
5201 p
= &mips_opcodes
[i
];
5202 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
5204 printf ("%08lx %s\t", oc
, p
->name
);
5205 treg
= (oc
>> 16) & 0x1f;
5206 sreg
= (oc
>> 21) & 0x1f;
5207 dreg
= (oc
>> 11) & 0x1f;
5208 shamt
= (oc
>> 6) & 0x1f;
5210 for (args
= p
->args
;; ++args
)
5221 printf ("%c", *args
);
5225 assert (treg
== sreg
);
5226 printf ("$%d,$%d", treg
, sreg
);
5231 printf ("$%d", dreg
);
5236 printf ("$%d", treg
);
5240 printf ("0x%x", treg
);
5245 printf ("$%d", sreg
);
5249 printf ("0x%08lx", oc
& 0x1ffffff);
5261 printf ("$%d", shamt
);
5272 printf ("%08lx UNDEFINED\n", oc
);
5283 name
= input_line_pointer
;
5284 c
= get_symbol_end ();
5285 p
= (symbolS
*) symbol_find_or_make (name
);
5286 *input_line_pointer
= c
;
5290 /* Align the current frag to a given power of two. The MIPS assembler
5291 also automatically adjusts any preceding label. */
5294 mips_align (to
, fill
, label
)
5299 mips_emit_delays ();
5300 frag_align (to
, fill
);
5301 record_alignment (now_seg
, to
);
5304 assert (S_GET_SEGMENT (label
) == now_seg
);
5305 label
->sy_frag
= frag_now
;
5306 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
5310 /* Align to a given power of two. .align 0 turns off the automatic
5311 alignment used by the data creating pseudo-ops. */
5318 register long temp_fill
;
5319 long max_alignment
= 15;
5323 o Note that the assembler pulls down any immediately preceeding label
5324 to the aligned address.
5325 o It's not documented but auto alignment is reinstated by
5326 a .align pseudo instruction.
5327 o Note also that after auto alignment is turned off the mips assembler
5328 issues an error on attempt to assemble an improperly aligned data item.
5333 temp
= get_absolute_expression ();
5334 if (temp
> max_alignment
)
5335 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
5338 as_warn ("Alignment negative: 0 assumed.");
5341 if (*input_line_pointer
== ',')
5343 input_line_pointer
++;
5344 temp_fill
= get_absolute_expression ();
5351 mips_align (temp
, (int) temp_fill
, insn_label
);
5358 demand_empty_rest_of_line ();
5361 /* Handle .ascii and .asciiz. This just calls stringer and forgets
5362 that there was a previous instruction. */
5365 s_stringer (append_zero
)
5368 mips_emit_delays ();
5370 stringer (append_zero
);
5381 /* When generating embedded PIC code, we only use the .text, .lit8,
5382 .sdata and .sbss sections. We change the .data and .rdata
5383 pseudo-ops to use .sdata. */
5384 if (mips_pic
== EMBEDDED_PIC
5385 && (sec
== 'd' || sec
== 'r'))
5388 mips_emit_delays ();
5398 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
5399 demand_empty_rest_of_line ();
5404 subseg_new (".rdata", (subsegT
) get_absolute_expression ());
5405 demand_empty_rest_of_line ();
5407 #else /* ! defined (OBJ_ECOFF) */
5409 seg
= subseg_new (".rodata", (subsegT
) get_absolute_expression ());
5410 bfd_set_section_flags (stdoutput
, seg
,
5416 bfd_set_section_alignment (stdoutput
, seg
, 4);
5417 demand_empty_rest_of_line ();
5419 #else /* ! defined (OBJ_ELF) */
5422 #endif /* ! defined (OBJ_ELF) */
5423 #endif /* ! defined (OBJ_ECOFF) */
5427 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
5429 bfd_set_section_flags (stdoutput
, seg
,
5430 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
| SEC_DATA
);
5431 bfd_set_section_alignment (stdoutput
, seg
, 4);
5433 demand_empty_rest_of_line ();
5435 #else /* ! defined (GPOPT) */
5436 as_bad ("Global pointers not supported; recompile -G 0");
5437 demand_empty_rest_of_line ();
5439 #endif /* ! defined (GPOPT) */
5452 mips_emit_delays ();
5453 if (log_size
> 0 && auto_align
)
5454 mips_align (log_size
, 0, label
);
5456 cons (1 << log_size
);
5463 as_fatal ("Encountered `.err', aborting assembly");
5473 symbolP
= get_symbol ();
5474 if (*input_line_pointer
== ',')
5475 input_line_pointer
++;
5476 size
= get_absolute_expression ();
5477 S_SET_EXTERNAL (symbolP
);
5479 #ifdef ECOFF_DEBUGGING
5480 symbolP
->ecoff_extern_size
= size
;
5492 mips_emit_delays ();
5496 mips_align (3, 0, label
);
5498 mips_align (2, 0, label
);
5512 opt
= input_line_pointer
;
5513 c
= get_symbol_end ();
5517 /* FIXME: What does this mean? */
5519 else if (strncmp (opt
, "pic", 3) == 0)
5527 mips_pic
= SVR4_PIC
;
5529 as_bad (".option pic%d not supported", i
);
5531 if (mips_pic
== SVR4_PIC
)
5533 if (g_switch_seen
&& g_switch_value
!= 0)
5534 as_warn ("-G may not be used with SVR4 PIC code");
5536 bfd_set_gp_size (stdoutput
, 0);
5540 as_warn ("Unrecognized option \"%s\"", opt
);
5542 *input_line_pointer
= c
;
5543 demand_empty_rest_of_line ();
5550 char *name
= input_line_pointer
, ch
;
5552 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
5553 input_line_pointer
++;
5554 ch
= *input_line_pointer
;
5555 *input_line_pointer
= '\0';
5557 if (strcmp (name
, "reorder") == 0)
5561 prev_insn_unreordered
= 1;
5562 prev_prev_insn_unreordered
= 1;
5566 else if (strcmp (name
, "noreorder") == 0)
5568 mips_emit_delays ();
5570 mips_any_noreorder
= 1;
5572 else if (strcmp (name
, "at") == 0)
5576 else if (strcmp (name
, "noat") == 0)
5580 else if (strcmp (name
, "macro") == 0)
5582 mips_warn_about_macros
= 0;
5584 else if (strcmp (name
, "nomacro") == 0)
5586 if (mips_noreorder
== 0)
5587 as_bad ("`noreorder' must be set before `nomacro'");
5588 mips_warn_about_macros
= 1;
5590 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
5594 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
5598 else if (strcmp (name
, "bopt") == 0)
5602 else if (strcmp (name
, "nobopt") == 0)
5606 else if (strncmp (name
, "mips", 4) == 0)
5610 /* Permit the user to change the ISA on the fly. Needless to
5611 say, misuse can cause serious problems. */
5612 isa
= atoi (name
+ 4);
5614 mips_isa
= file_mips_isa
;
5615 else if (isa
< 1 || isa
> 3)
5616 as_bad ("unknown ISA level");
5622 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
5624 *input_line_pointer
= ch
;
5625 demand_empty_rest_of_line ();
5628 /* The same as the usual .space directive, except that we have to
5629 forget about any previous instruction. */
5632 s_mips_space (param
)
5635 mips_emit_delays ();
5640 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
5641 .option pic2. It means to generate SVR4 PIC calls. */
5647 mips_pic
= SVR4_PIC
;
5648 if (g_switch_seen
&& g_switch_value
!= 0)
5649 as_warn ("-G may not be used with SVR4 PIC code");
5651 bfd_set_gp_size (stdoutput
, 0);
5652 demand_empty_rest_of_line ();
5655 /* Handle the .cpload pseudo-op. This is used when generating SVR4
5656 PIC code. It sets the $gp register for the function based on the
5657 function address, which is in the register named in the argument.
5658 This uses a relocation against _gp_disp, which is handled specially
5659 by the linker. The result is:
5660 lui $gp,%hi(_gp_disp)
5661 addiu $gp,$gp,%lo(_gp_disp)
5662 addu $gp,$gp,.cpload argument
5663 The .cpload argument is normally $25 == $t9. */
5672 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
5673 if (mips_pic
!= SVR4_PIC
)
5679 /* .cpload should be a in .set noreorder section. */
5680 if (mips_noreorder
== 0)
5681 as_warn (".cpload not in noreorder section");
5684 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
5685 ex
.X_op_symbol
= NULL
;
5686 ex
.X_add_number
= 0;
5688 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
5689 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
5690 (int) BFD_RELOC_LO16
);
5692 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
5693 GP
, GP
, tc_get_register (0));
5695 demand_empty_rest_of_line ();
5698 /* Handle the .cprestore pseudo-op. This stores $gp into a given
5699 offset from $sp. The offset is remembered, and after making a PIC
5700 call $gp is restored from that location. */
5703 s_cprestore (ignore
)
5709 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
5710 if (mips_pic
!= SVR4_PIC
)
5716 mips_cprestore_offset
= get_absolute_expression ();
5718 ex
.X_op
= O_constant
;
5719 ex
.X_add_symbol
= NULL
;
5720 ex
.X_op_symbol
= NULL
;
5721 ex
.X_add_number
= mips_cprestore_offset
;
5723 macro_build ((char *) NULL
, &icnt
, &ex
,
5724 mips_isa
< 3 ? "sw" : "sd",
5725 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
5727 demand_empty_rest_of_line ();
5730 /* Handle the .gpword pseudo-op. This is used when generating PIC
5731 code. It generates a 32 bit GP relative reloc. */
5741 /* When not generating PIC code, this is treated as .word. */
5742 if (mips_pic
!= SVR4_PIC
)
5749 mips_emit_delays ();
5751 mips_align (2, 0, label
);
5756 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
5758 as_bad ("Unsupported use of .gpword");
5759 ignore_rest_of_line ();
5763 md_number_to_chars (p
, (valueT
) 0, 4);
5764 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
5765 BFD_RELOC_MIPS_GPREL32
);
5767 demand_empty_rest_of_line ();
5770 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
5771 tables in SVR4 PIC code. */
5780 /* This is ignored when not generating SVR4 PIC code. */
5781 if (mips_pic
!= SVR4_PIC
)
5787 /* Add $gp to the register named as an argument. */
5788 reg
= tc_get_register (0);
5789 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5790 mips_isa
< 3 ? "addu" : "daddu",
5791 "d,v,t", reg
, reg
, GP
);
5793 demand_empty_rest_of_line ();
5796 /* Parse a register string into a number. Called from the ECOFF code
5797 to parse .frame. The argument is non-zero if this is the frame
5798 register, so that we can record it in mips_frame_reg. */
5801 tc_get_register (frame
)
5807 if (*input_line_pointer
++ != '$')
5809 as_warn ("expected `$'");
5812 else if (isdigit ((unsigned char) *input_line_pointer
))
5814 reg
= get_absolute_expression ();
5815 if (reg
< 0 || reg
>= 32)
5817 as_warn ("Bad register number");
5823 if (strncmp (input_line_pointer
, "fp", 2) == 0)
5825 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
5827 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
5829 else if (strncmp (input_line_pointer
, "at", 2) == 0)
5833 as_warn ("Unrecognized register name");
5836 input_line_pointer
+= 2;
5839 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
5844 md_section_align (seg
, addr
)
5848 int align
= bfd_get_section_alignment (stdoutput
, seg
);
5850 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
5853 /* Estimate the size of a frag before relaxing. We are not really
5854 relaxing here, and the final size is encoded in the subtype
5859 md_estimate_size_before_relax (fragp
, segtype
)
5865 if (mips_pic
== NO_PIC
)
5868 const char *symname
;
5870 /* Find out whether this symbol can be referenced off the GP
5871 register. It can be if it is smaller than the -G size or if
5872 it is in the .sdata or .sbss section. Certain symbols can
5873 not be referenced off the GP, although it appears as though
5875 symname
= S_GET_NAME (fragp
->fr_symbol
);
5876 if (symname
!= (const char *) NULL
5877 && (strcmp (symname
, "eprol") == 0
5878 || strcmp (symname
, "etext") == 0
5879 || strcmp (symname
, "_gp") == 0
5880 || strcmp (symname
, "edata") == 0
5881 || strcmp (symname
, "_fbss") == 0
5882 || strcmp (symname
, "_fdata") == 0
5883 || strcmp (symname
, "_ftext") == 0
5884 || strcmp (symname
, "end") == 0
5885 || strcmp (symname
, "_gp_disp") == 0))
5887 else if (! S_IS_DEFINED (fragp
->fr_symbol
)
5888 && ((fragp
->fr_symbol
->ecoff_extern_size
!= 0
5889 && fragp
->fr_symbol
->ecoff_extern_size
<= g_switch_value
)
5890 || (S_GET_VALUE (fragp
->fr_symbol
) != 0
5891 && S_GET_VALUE (fragp
->fr_symbol
) <= g_switch_value
)))
5895 const char *segname
;
5897 segname
= segment_name (S_GET_SEGMENT (fragp
->fr_symbol
));
5898 assert (strcmp (segname
, ".lit8") != 0
5899 && strcmp (segname
, ".lit4") != 0);
5900 change
= (strcmp (segname
, ".sdata") != 0
5901 && strcmp (segname
, ".sbss") != 0);
5903 #else /* ! defined (GPOPT) */
5904 /* We are not optimizing for the GP register. */
5906 #endif /* ! defined (GPOPT) */
5908 else if (mips_pic
== SVR4_PIC
)
5910 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
5912 /* This must duplicate the test in adjust_reloc_syms. */
5913 change
= (symsec
!= &bfd_und_section
5914 && symsec
!= &bfd_abs_section
5915 && ! bfd_is_com_section (symsec
));
5922 /* Record the offset to the first reloc in the fr_opcode field.
5923 This lets md_convert_frag and tc_gen_reloc know that the code
5924 must be expanded. */
5925 fragp
->fr_opcode
= (fragp
->fr_literal
5927 - RELAX_OLD (fragp
->fr_subtype
)
5928 + RELAX_RELOC1 (fragp
->fr_subtype
));
5929 /* FIXME: This really needs as_warn_where. */
5930 if (RELAX_WARN (fragp
->fr_subtype
))
5931 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
5937 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
5940 /* Translate internal representation of relocation info to BFD target
5944 tc_gen_reloc (section
, fixp
)
5948 static arelent
*retval
[4];
5951 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
5954 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
5955 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
5957 if (mips_pic
== EMBEDDED_PIC
5958 && SWITCH_TABLE (fixp
))
5960 /* For a switch table entry we use a special reloc. The addend
5961 is actually the difference between the reloc address and the
5963 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
5965 #error Double check fx_r_type here
5967 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
5969 else if (fixp
->fx_pcrel
== 0)
5970 reloc
->addend
= fixp
->fx_addnumber
;
5974 /* A gruesome hack which is a result of the gruesome gas reloc
5976 reloc
->addend
= reloc
->address
;
5978 reloc
->addend
= -reloc
->address
;
5982 /* If this is a variant frag, we may need to adjust the existing
5983 reloc and generate a new one. */
5984 if (fixp
->fx_frag
->fr_opcode
!= NULL
5985 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5986 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
5987 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
))
5991 /* If this is not the last reloc in this frag, then we have two
5992 GPREL relocs, both of which are being replaced. Let the
5993 second one handle all of them. */
5994 if (fixp
->fx_next
!= NULL
5995 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
5997 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
5998 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6003 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
6004 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6005 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
6007 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
6008 reloc2
->address
= (reloc
->address
6009 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
6010 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
6011 reloc2
->addend
= fixp
->fx_addnumber
;
6012 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
6013 assert (reloc2
->howto
!= NULL
);
6015 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
6019 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
6022 reloc3
->address
+= 4;
6025 if (mips_pic
== NO_PIC
)
6027 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
6028 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
6030 else if (mips_pic
== SVR4_PIC
)
6032 if (fixp
->fx_r_type
!= BFD_RELOC_MIPS_GOT16
)
6034 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
);
6035 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
6042 /* To support a PC relative reloc when generating embedded PIC code
6043 for ECOFF, we use a Cygnus extension. We check for that here to
6044 make sure that we don't let such a reloc escape normally. */
6046 if (fixp
->fx_r_type
== BFD_RELOC_16_PCREL_S2
6047 && mips_pic
!= EMBEDDED_PIC
)
6048 reloc
->howto
= NULL
;
6051 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, fixp
->fx_r_type
);
6053 if (reloc
->howto
== NULL
)
6055 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6056 "Can not represent relocation in this object file format");
6063 /* Convert a machine dependent frag. */
6066 md_convert_frag (abfd
, asec
, fragp
)
6074 if (fragp
->fr_opcode
== NULL
)
6077 old
= RELAX_OLD (fragp
->fr_subtype
);
6078 new = RELAX_NEW (fragp
->fr_subtype
);
6079 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
6082 memcpy (fixptr
- old
, fixptr
, new);
6084 fragp
->fr_fix
+= new - old
;
6087 /* This function is called whenever a label is defined. It is used
6088 when handling branch delays; if a branch has a label, we assume we
6092 mips_define_label (sym
)
6100 /* Some special processing for a MIPS ELF file. */
6103 mips_elf_final_processing ()
6107 /* Write out the .reginfo section. */
6108 s
.ri_gprmask
= mips_gprmask
;
6109 s
.ri_cprmask
[0] = mips_cprmask
[0];
6110 s
.ri_cprmask
[1] = mips_cprmask
[1];
6111 s
.ri_cprmask
[2] = mips_cprmask
[2];
6112 s
.ri_cprmask
[3] = mips_cprmask
[3];
6113 /* The gp_value field is set by the MIPS ELF backend. */
6115 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
6116 ((Elf32_External_RegInfo
*)
6117 mips_regmask_frag
));
6119 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
6120 sort of BFD interface for this. */
6121 if (mips_any_noreorder
)
6122 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
6123 if (mips_pic
!= NO_PIC
)
6124 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
6127 #endif /* OBJ_ELF */
6129 #ifndef ECOFF_DEBUGGING
6131 /* These functions should really be defined by the object file format,
6132 since they are related to debugging information. However, this
6133 code has to work for the a.out format, which does not define them,
6134 so we provide simple versions here. These don't actually generate
6135 any debugging information, but they do simple checking and someday
6136 somebody may make them useful. */
6140 struct loc
*loc_next
;
6141 unsigned long loc_fileno
;
6142 unsigned long loc_lineno
;
6143 unsigned long loc_offset
;
6144 unsigned short loc_delta
;
6145 unsigned short loc_count
;
6154 struct proc
*proc_next
;
6155 struct symbol
*proc_isym
;
6156 struct symbol
*proc_end
;
6157 unsigned long proc_reg_mask
;
6158 unsigned long proc_reg_offset
;
6159 unsigned long proc_fpreg_mask
;
6160 unsigned long proc_fpreg_offset
;
6161 unsigned long proc_frameoffset
;
6162 unsigned long proc_framereg
;
6163 unsigned long proc_pcreg
;
6165 struct file
*proc_file
;
6172 struct file
*file_next
;
6173 unsigned long file_fileno
;
6174 struct symbol
*file_symbol
;
6175 struct symbol
*file_end
;
6176 struct proc
*file_proc
;
6181 static struct obstack proc_frags
;
6182 static procS
*proc_lastP
;
6183 static procS
*proc_rootP
;
6184 static int numprocs
;
6189 obstack_begin (&proc_frags
, 0x2000);
6195 /* check for premature end, nesting errors, etc */
6196 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6197 as_warn ("missing `.end' at end of assembly");
6200 extern char hex_value
[];
6208 if (*input_line_pointer
== '-')
6210 ++input_line_pointer
;
6213 if (!isdigit (*input_line_pointer
))
6214 as_bad ("Expected simple number.");
6215 if (input_line_pointer
[0] == '0')
6217 if (input_line_pointer
[1] == 'x')
6219 input_line_pointer
+= 2;
6220 while (isxdigit (*input_line_pointer
))
6223 val
|= hex_value
[(int) *input_line_pointer
++];
6225 return negative
? -val
: val
;
6229 ++input_line_pointer
;
6230 while (isdigit (*input_line_pointer
))
6233 val
|= *input_line_pointer
++ - '0';
6235 return negative
? -val
: val
;
6238 if (!isdigit (*input_line_pointer
))
6240 printf (" *input_line_pointer == '%c' 0x%02x\n",
6241 *input_line_pointer
, *input_line_pointer
);
6242 as_warn ("Invalid number");
6245 while (isdigit (*input_line_pointer
))
6248 val
+= *input_line_pointer
++ - '0';
6250 return negative
? -val
: val
;
6253 /* The .file directive; just like the usual .file directive, but there
6254 is an initial number which is the ECOFF file index. */
6262 line
= get_number ();
6267 /* The .end directive. */
6275 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
6278 demand_empty_rest_of_line ();
6282 if (now_seg
!= text_section
)
6283 as_warn (".end not in text section");
6286 as_warn (".end and no .ent seen yet.");
6292 assert (S_GET_NAME (p
));
6293 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
6294 as_warn (".end symbol does not match .ent symbol.");
6297 proc_lastP
->proc_end
= (symbolS
*) 1;
6300 /* The .aent and .ent directives. */
6310 symbolP
= get_symbol ();
6311 if (*input_line_pointer
== ',')
6312 input_line_pointer
++;
6314 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
6315 number
= get_number ();
6316 if (now_seg
!= text_section
)
6317 as_warn (".ent or .aent not in text section.");
6319 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
6320 as_warn ("missing `.end'");
6324 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
6325 procP
->proc_isym
= symbolP
;
6326 procP
->proc_reg_mask
= 0;
6327 procP
->proc_reg_offset
= 0;
6328 procP
->proc_fpreg_mask
= 0;
6329 procP
->proc_fpreg_offset
= 0;
6330 procP
->proc_frameoffset
= 0;
6331 procP
->proc_framereg
= 0;
6332 procP
->proc_pcreg
= 0;
6333 procP
->proc_end
= NULL
;
6334 procP
->proc_next
= NULL
;
6336 proc_lastP
->proc_next
= procP
;
6342 demand_empty_rest_of_line ();
6345 /* The .frame directive. */
6358 frame_reg
= tc_get_register (1);
6359 if (*input_line_pointer
== ',')
6360 input_line_pointer
++;
6361 frame_off
= get_absolute_expression ();
6362 if (*input_line_pointer
== ',')
6363 input_line_pointer
++;
6364 pcreg
= tc_get_register (0);
6367 assert (proc_rootP
);
6368 proc_rootP
->proc_framereg
= frame_reg
;
6369 proc_rootP
->proc_frameoffset
= frame_off
;
6370 proc_rootP
->proc_pcreg
= pcreg
;
6371 /* bob macho .frame */
6373 /* We don't have to write out a frame stab for unoptimized code. */
6374 if (!(frame_reg
== FP
&& frame_off
== 0))
6377 as_warn ("No .ent for .frame to use.");
6378 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
6379 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
6380 S_SET_TYPE (symP
, N_RMASK
);
6381 S_SET_OTHER (symP
, 0);
6382 S_SET_DESC (symP
, 0);
6383 symP
->sy_forward
= proc_lastP
->proc_isym
;
6384 /* bob perhaps I should have used pseudo set */
6386 demand_empty_rest_of_line ();
6390 /* The .fmask and .mask directives. */
6397 char str
[100], *strP
;
6403 mask
= get_number ();
6404 if (*input_line_pointer
== ',')
6405 input_line_pointer
++;
6406 off
= get_absolute_expression ();
6408 /* bob only for coff */
6409 assert (proc_rootP
);
6410 if (reg_type
== 'F')
6412 proc_rootP
->proc_fpreg_mask
= mask
;
6413 proc_rootP
->proc_fpreg_offset
= off
;
6417 proc_rootP
->proc_reg_mask
= mask
;
6418 proc_rootP
->proc_reg_offset
= off
;
6421 /* bob macho .mask + .fmask */
6423 /* We don't have to write out a mask stab if no saved regs. */
6427 as_warn ("No .ent for .mask to use.");
6429 for (i
= 0; i
< 32; i
++)
6433 sprintf (strP
, "%c%d,", reg_type
, i
);
6434 strP
+= strlen (strP
);
6438 sprintf (strP
, ";%d,", off
);
6439 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
6440 S_SET_TYPE (symP
, N_RMASK
);
6441 S_SET_OTHER (symP
, 0);
6442 S_SET_DESC (symP
, 0);
6443 symP
->sy_forward
= proc_lastP
->proc_isym
;
6444 /* bob perhaps I should have used pseudo set */
6449 /* The .loc directive. */
6460 assert (now_seg
== text_section
);
6462 lineno
= get_number ();
6463 addroff
= obstack_next_free (&frags
) - frag_now
->fr_literal
;
6465 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
6466 S_SET_TYPE (symbolP
, N_SLINE
);
6467 S_SET_OTHER (symbolP
, 0);
6468 S_SET_DESC (symbolP
, lineno
);
6469 symbolP
->sy_segment
= now_seg
;
6473 #endif /* ! defined (ECOFF_DEBUGGING) */