1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
9 This file is part of GAS.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 #include "safe-ctype.h"
33 #include "opcode/mips.h"
35 #include "dwarf2dbg.h"
38 #define DBG(x) printf x
44 /* Clean up namespace so we can include obj-elf.h too. */
45 static int mips_output_flavor (void);
46 static int mips_output_flavor (void) { return OUTPUT_FLAVOR
; }
47 #undef OBJ_PROCESS_STAB
54 #undef obj_frob_file_after_relocs
55 #undef obj_frob_symbol
57 #undef obj_sec_sym_ok_for_reloc
58 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
61 /* Fix any of them that we actually care about. */
63 #define OUTPUT_FLAVOR mips_output_flavor()
70 #ifndef ECOFF_DEBUGGING
71 #define NO_ECOFF_DEBUGGING
72 #define ECOFF_DEBUGGING 0
75 int mips_flag_mdebug
= -1;
77 /* Control generation of .pdr sections. Off by default on IRIX: the native
78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
81 int mips_flag_pdr
= FALSE
;
83 int mips_flag_pdr
= TRUE
;
88 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89 static char *mips_regmask_frag
;
95 #define PIC_CALL_REG 25
103 #define ILLEGAL_REG (32)
105 /* Allow override of standard little-endian ECOFF format. */
107 #ifndef ECOFF_LITTLE_FORMAT
108 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
111 extern int target_big_endian
;
113 /* The name of the readonly data section. */
114 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
124 /* The ABI to use. */
135 /* MIPS ABI we are using for this output file. */
136 static enum mips_abi_level mips_abi
= NO_ABI
;
138 /* Whether or not we have code that can call pic code. */
139 int mips_abicalls
= FALSE
;
141 /* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
145 struct mips_set_options
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
164 /* Non-zero if we should not permit the $at ($1) register to be used
165 in instructions. Changed by `.set at' and `.set noat'. */
167 /* Non-zero if we should warn when a macro instruction expands into
168 more than one machine instruction. Changed by `.set nomacro' and
170 int warn_about_macros
;
171 /* Non-zero if we should not move instructions. Changed by `.set
172 move', `.set volatile', `.set nomove', and `.set novolatile'. */
174 /* Non-zero if we should not optimize branches by moving the target
175 of the branch into the delay slot. Actually, we don't perform
176 this optimization anyhow. Changed by `.set bopt' and `.set
179 /* Non-zero if we should not autoextend mips16 instructions.
180 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
192 /* True if -mgp32 was passed. */
193 static int file_mips_gp32
= -1;
195 /* True if -mfp32 was passed. */
196 static int file_mips_fp32
= -1;
198 /* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
202 static struct mips_set_options mips_opts
=
204 ISA_UNKNOWN
, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
207 /* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
210 unsigned long mips_gprmask
;
211 unsigned long mips_cprmask
[4];
213 /* MIPS ISA we are using for this output file. */
214 static int file_mips_isa
= ISA_UNKNOWN
;
216 /* True if -mips16 was passed or implied by arguments passed on the
217 command line (e.g., by -march). */
218 static int file_ase_mips16
;
220 /* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222 static int file_ase_mips3d
;
224 /* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226 static int file_ase_mdmx
;
228 /* The argument of the -march= flag. The architecture we are assembling. */
229 static int file_mips_arch
= CPU_UNKNOWN
;
230 static const char *mips_arch_string
;
232 /* The argument of the -mtune= flag. The architecture for which we
234 static int mips_tune
= CPU_UNKNOWN
;
235 static const char *mips_tune_string
;
237 /* True when generating 32-bit code for a 64-bit processor. */
238 static int mips_32bitmode
= 0;
240 /* True if the given ABI requires 32-bit registers. */
241 #define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
243 /* Likewise 64-bit registers. */
244 #define ABI_NEEDS_64BIT_REGS(ABI) \
246 || (ABI) == N64_ABI \
249 /* Return true if ISA supports 64 bit gp register instructions. */
250 #define ISA_HAS_64BIT_REGS(ISA) ( \
252 || (ISA) == ISA_MIPS4 \
253 || (ISA) == ISA_MIPS5 \
254 || (ISA) == ISA_MIPS64 \
255 || (ISA) == ISA_MIPS64R2 \
258 /* Return true if ISA supports 64-bit right rotate (dror et al.)
260 #define ISA_HAS_DROR(ISA) ( \
261 (ISA) == ISA_MIPS64R2 \
264 /* Return true if ISA supports 32-bit right rotate (ror et al.)
266 #define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
271 #define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
274 #define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
277 #define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278 #define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
280 #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
282 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
284 /* We can only have 64bit addresses if the object file format
286 #define HAVE_32BIT_ADDRESSES \
288 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
289 || ! HAVE_64BIT_OBJECTS) \
290 && mips_pic != EMBEDDED_PIC))
292 #define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
294 /* Addresses are loaded in different ways, depending on the address size
295 in use. The n32 ABI Documentation also mandates the use of additions
296 with overflow checking, but existing implementations don't follow it. */
297 #define ADDRESS_ADD_INSN \
298 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
300 #define ADDRESS_ADDI_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu")
303 #define ADDRESS_LOAD_INSN \
304 (HAVE_32BIT_ADDRESSES ? "lw" : "ld")
306 #define ADDRESS_STORE_INSN \
307 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
309 /* Return true if the given CPU supports the MIPS16 ASE. */
310 #define CPU_HAS_MIPS16(cpu) \
311 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
312 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
314 /* Return true if the given CPU supports the MIPS3D ASE. */
315 #define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
318 /* Return true if the given CPU supports the MDMX ASE. */
319 #define CPU_HAS_MDMX(cpu) (FALSE \
322 /* True if CPU has a dror instruction. */
323 #define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
325 /* True if CPU has a ror instruction. */
326 #define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
328 /* True if mflo and mfhi can be immediately followed by instructions
329 which write to the HI and LO registers.
331 According to MIPS specifications, MIPS ISAs I, II, and III need
332 (at least) two instructions between the reads of HI/LO and
333 instructions which write them, and later ISAs do not. Contradicting
334 the MIPS specifications, some MIPS IV processor user manuals (e.g.
335 the UM for the NEC Vr5000) document needing the instructions between
336 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
337 MIPS64 and later ISAs to have the interlocks, plus any specific
338 earlier-ISA CPUs for which CPU documentation declares that the
339 instructions are really interlocked. */
340 #define hilo_interlocks \
341 (mips_opts.isa == ISA_MIPS32 \
342 || mips_opts.isa == ISA_MIPS32R2 \
343 || mips_opts.isa == ISA_MIPS64 \
344 || mips_opts.isa == ISA_MIPS64R2 \
345 || mips_opts.arch == CPU_R4010 \
346 || mips_opts.arch == CPU_R10000 \
347 || mips_opts.arch == CPU_R12000 \
348 || mips_opts.arch == CPU_RM7000 \
349 || mips_opts.arch == CPU_VR5500 \
352 /* Whether the processor uses hardware interlocks to protect reads
353 from the GPRs after they are loaded from memory, and thus does not
354 require nops to be inserted. This applies to instructions marked
355 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
357 #define gpr_interlocks \
358 (mips_opts.isa != ISA_MIPS1 \
359 || mips_opts.arch == CPU_R3900)
361 /* Whether the processor uses hardware interlocks to avoid delays
362 required by coprocessor instructions, and thus does not require
363 nops to be inserted. This applies to instructions marked
364 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
365 between instructions marked INSN_WRITE_COND_CODE and ones marked
366 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
367 levels I, II, and III. */
368 /* Itbl support may require additional care here. */
369 #define cop_interlocks \
370 ((mips_opts.isa != ISA_MIPS1 \
371 && mips_opts.isa != ISA_MIPS2 \
372 && mips_opts.isa != ISA_MIPS3) \
373 || mips_opts.arch == CPU_R4300 \
376 /* Whether the processor uses hardware interlocks to protect reads
377 from coprocessor registers after they are loaded from memory, and
378 thus does not require nops to be inserted. This applies to
379 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
380 requires at MIPS ISA level I. */
381 #define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)
383 /* Is this a mfhi or mflo instruction? */
384 #define MF_HILO_INSN(PINFO) \
385 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
387 /* MIPS PIC level. */
389 enum mips_pic_level mips_pic
;
391 /* 1 if we should generate 32 bit offsets from the $gp register in
392 SVR4_PIC mode. Currently has no meaning in other modes. */
393 static int mips_big_got
= 0;
395 /* 1 if trap instructions should used for overflow rather than break
397 static int mips_trap
= 0;
399 /* 1 if double width floating point constants should not be constructed
400 by assembling two single width halves into two single width floating
401 point registers which just happen to alias the double width destination
402 register. On some architectures this aliasing can be disabled by a bit
403 in the status register, and the setting of this bit cannot be determined
404 automatically at assemble time. */
405 static int mips_disable_float_construction
;
407 /* Non-zero if any .set noreorder directives were used. */
409 static int mips_any_noreorder
;
411 /* Non-zero if nops should be inserted when the register referenced in
412 an mfhi/mflo instruction is read in the next two instructions. */
413 static int mips_7000_hilo_fix
;
415 /* The size of the small data section. */
416 static unsigned int g_switch_value
= 8;
417 /* Whether the -G option was used. */
418 static int g_switch_seen
= 0;
423 /* If we can determine in advance that GP optimization won't be
424 possible, we can skip the relaxation stuff that tries to produce
425 GP-relative references. This makes delay slot optimization work
428 This function can only provide a guess, but it seems to work for
429 gcc output. It needs to guess right for gcc, otherwise gcc
430 will put what it thinks is a GP-relative instruction in a branch
433 I don't know if a fix is needed for the SVR4_PIC mode. I've only
434 fixed it for the non-PIC mode. KR 95/04/07 */
435 static int nopic_need_relax (symbolS
*, int);
437 /* handle of the OPCODE hash table */
438 static struct hash_control
*op_hash
= NULL
;
440 /* The opcode hash table we use for the mips16. */
441 static struct hash_control
*mips16_op_hash
= NULL
;
443 /* This array holds the chars that always start a comment. If the
444 pre-processor is disabled, these aren't very useful */
445 const char comment_chars
[] = "#";
447 /* This array holds the chars that only start a comment at the beginning of
448 a line. If the line seems to have the form '# 123 filename'
449 .line and .file directives will appear in the pre-processed output */
450 /* Note that input_file.c hand checks for '#' at the beginning of the
451 first line of the input file. This is because the compiler outputs
452 #NO_APP at the beginning of its output. */
453 /* Also note that C style comments are always supported. */
454 const char line_comment_chars
[] = "#";
456 /* This array holds machine specific line separator characters. */
457 const char line_separator_chars
[] = ";";
459 /* Chars that can be used to separate mant from exp in floating point nums */
460 const char EXP_CHARS
[] = "eE";
462 /* Chars that mean this number is a floating point constant */
465 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
467 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
468 changed in read.c . Ideally it shouldn't have to know about it at all,
469 but nothing is ideal around here.
472 static char *insn_error
;
474 static int auto_align
= 1;
476 /* When outputting SVR4 PIC code, the assembler needs to know the
477 offset in the stack frame from which to restore the $gp register.
478 This is set by the .cprestore pseudo-op, and saved in this
480 static offsetT mips_cprestore_offset
= -1;
482 /* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
483 more optimizations, it can use a register value instead of a memory-saved
484 offset and even an other register than $gp as global pointer. */
485 static offsetT mips_cpreturn_offset
= -1;
486 static int mips_cpreturn_register
= -1;
487 static int mips_gp_register
= GP
;
488 static int mips_gprel_offset
= 0;
490 /* Whether mips_cprestore_offset has been set in the current function
491 (or whether it has already been warned about, if not). */
492 static int mips_cprestore_valid
= 0;
494 /* This is the register which holds the stack frame, as set by the
495 .frame pseudo-op. This is needed to implement .cprestore. */
496 static int mips_frame_reg
= SP
;
498 /* Whether mips_frame_reg has been set in the current function
499 (or whether it has already been warned about, if not). */
500 static int mips_frame_reg_valid
= 0;
502 /* To output NOP instructions correctly, we need to keep information
503 about the previous two instructions. */
505 /* Whether we are optimizing. The default value of 2 means to remove
506 unneeded NOPs and swap branch instructions when possible. A value
507 of 1 means to not swap branches. A value of 0 means to always
509 static int mips_optimize
= 2;
511 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
512 equivalent to seeing no -g option at all. */
513 static int mips_debug
= 0;
515 /* The previous instruction. */
516 static struct mips_cl_insn prev_insn
;
518 /* The instruction before prev_insn. */
519 static struct mips_cl_insn prev_prev_insn
;
521 /* If we don't want information for prev_insn or prev_prev_insn, we
522 point the insn_mo field at this dummy integer. */
523 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
525 /* Non-zero if prev_insn is valid. */
526 static int prev_insn_valid
;
528 /* The frag for the previous instruction. */
529 static struct frag
*prev_insn_frag
;
531 /* The offset into prev_insn_frag for the previous instruction. */
532 static long prev_insn_where
;
534 /* The reloc type for the previous instruction, if any. */
535 static bfd_reloc_code_real_type prev_insn_reloc_type
[3];
537 /* The reloc for the previous instruction, if any. */
538 static fixS
*prev_insn_fixp
[3];
540 /* Non-zero if the previous instruction was in a delay slot. */
541 static int prev_insn_is_delay_slot
;
543 /* Non-zero if the previous instruction was in a .set noreorder. */
544 static int prev_insn_unreordered
;
546 /* Non-zero if the previous instruction uses an extend opcode (if
548 static int prev_insn_extended
;
550 /* Non-zero if the previous previous instruction was in a .set
552 static int prev_prev_insn_unreordered
;
554 /* If this is set, it points to a frag holding nop instructions which
555 were inserted before the start of a noreorder section. If those
556 nops turn out to be unnecessary, the size of the frag can be
558 static fragS
*prev_nop_frag
;
560 /* The number of nop instructions we created in prev_nop_frag. */
561 static int prev_nop_frag_holds
;
563 /* The number of nop instructions that we know we need in
565 static int prev_nop_frag_required
;
567 /* The number of instructions we've seen since prev_nop_frag. */
568 static int prev_nop_frag_since
;
570 /* For ECOFF and ELF, relocations against symbols are done in two
571 parts, with a HI relocation and a LO relocation. Each relocation
572 has only 16 bits of space to store an addend. This means that in
573 order for the linker to handle carries correctly, it must be able
574 to locate both the HI and the LO relocation. This means that the
575 relocations must appear in order in the relocation table.
577 In order to implement this, we keep track of each unmatched HI
578 relocation. We then sort them so that they immediately precede the
579 corresponding LO relocation. */
584 struct mips_hi_fixup
*next
;
587 /* The section this fixup is in. */
591 /* The list of unmatched HI relocs. */
593 static struct mips_hi_fixup
*mips_hi_fixup_list
;
595 /* The frag containing the last explicit relocation operator.
596 Null if explicit relocations have not been used. */
598 static fragS
*prev_reloc_op_frag
;
600 /* Map normal MIPS register numbers to mips16 register numbers. */
602 #define X ILLEGAL_REG
603 static const int mips32_to_16_reg_map
[] =
605 X
, X
, 2, 3, 4, 5, 6, 7,
606 X
, X
, X
, X
, X
, X
, X
, X
,
607 0, 1, X
, X
, X
, X
, X
, X
,
608 X
, X
, X
, X
, X
, X
, X
, X
612 /* Map mips16 register numbers to normal MIPS register numbers. */
614 static const unsigned int mips16_to_32_reg_map
[] =
616 16, 17, 2, 3, 4, 5, 6, 7
619 static int mips_fix_vr4120
;
621 /* We don't relax branches by default, since this causes us to expand
622 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
623 fail to compute the offset before expanding the macro to the most
624 efficient expansion. */
626 static int mips_relax_branch
;
628 /* The expansion of many macros depends on the type of symbol that
629 they refer to. For example, when generating position-dependent code,
630 a macro that refers to a symbol may have two different expansions,
631 one which uses GP-relative addresses and one which uses absolute
632 addresses. When generating SVR4-style PIC, a macro may have
633 different expansions for local and global symbols.
635 We handle these situations by generating both sequences and putting
636 them in variant frags. In position-dependent code, the first sequence
637 will be the GP-relative one and the second sequence will be the
638 absolute one. In SVR4 PIC, the first sequence will be for global
639 symbols and the second will be for local symbols.
641 The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and
642 SECOND are the lengths of the two sequences in bytes. These fields
643 can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition,
644 the subtype has the following flags:
647 Set if it has been decided that we should use the second
648 sequence instead of the first.
651 Set in the first variant frag if the macro's second implementation
652 is longer than its first. This refers to the macro as a whole,
653 not an individual relaxation.
656 Set in the first variant frag if the macro appeared in a .set nomacro
657 block and if one alternative requires a warning but the other does not.
660 Like RELAX_NOMACRO, but indicates that the macro appears in a branch
663 The frag's "opcode" points to the first fixup for relaxable code.
665 Relaxable macros are generated using a sequence such as:
667 relax_start (SYMBOL);
668 ... generate first expansion ...
670 ... generate second expansion ...
673 The code and fixups for the unwanted alternative are discarded
674 by md_convert_frag. */
675 #define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND))
677 #define RELAX_FIRST(X) (((X) >> 8) & 0xff)
678 #define RELAX_SECOND(X) ((X) & 0xff)
679 #define RELAX_USE_SECOND 0x10000
680 #define RELAX_SECOND_LONGER 0x20000
681 #define RELAX_NOMACRO 0x40000
682 #define RELAX_DELAY_SLOT 0x80000
684 /* Branch without likely bit. If label is out of range, we turn:
686 beq reg1, reg2, label
696 with the following opcode replacements:
703 bltzal <-> bgezal (with jal label instead of j label)
705 Even though keeping the delay slot instruction in the delay slot of
706 the branch would be more efficient, it would be very tricky to do
707 correctly, because we'd have to introduce a variable frag *after*
708 the delay slot instruction, and expand that instead. Let's do it
709 the easy way for now, even if the branch-not-taken case now costs
710 one additional instruction. Out-of-range branches are not supposed
711 to be common, anyway.
713 Branch likely. If label is out of range, we turn:
715 beql reg1, reg2, label
716 delay slot (annulled if branch not taken)
725 delay slot (executed only if branch taken)
728 It would be possible to generate a shorter sequence by losing the
729 likely bit, generating something like:
734 delay slot (executed only if branch taken)
746 bltzall -> bgezal (with jal label instead of j label)
747 bgezall -> bltzal (ditto)
750 but it's not clear that it would actually improve performance. */
751 #define RELAX_BRANCH_ENCODE(uncond, likely, link, toofar) \
754 | ((toofar) ? 1 : 0) \
756 | ((likely) ? 4 : 0) \
757 | ((uncond) ? 8 : 0)))
758 #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
759 #define RELAX_BRANCH_UNCOND(i) (((i) & 8) != 0)
760 #define RELAX_BRANCH_LIKELY(i) (((i) & 4) != 0)
761 #define RELAX_BRANCH_LINK(i) (((i) & 2) != 0)
762 #define RELAX_BRANCH_TOOFAR(i) (((i) & 1) != 0)
764 /* For mips16 code, we use an entirely different form of relaxation.
765 mips16 supports two versions of most instructions which take
766 immediate values: a small one which takes some small value, and a
767 larger one which takes a 16 bit value. Since branches also follow
768 this pattern, relaxing these values is required.
770 We can assemble both mips16 and normal MIPS code in a single
771 object. Therefore, we need to support this type of relaxation at
772 the same time that we support the relaxation described above. We
773 use the high bit of the subtype field to distinguish these cases.
775 The information we store for this type of relaxation is the
776 argument code found in the opcode file for this relocation, whether
777 the user explicitly requested a small or extended form, and whether
778 the relocation is in a jump or jal delay slot. That tells us the
779 size of the value, and how it should be stored. We also store
780 whether the fragment is considered to be extended or not. We also
781 store whether this is known to be a branch to a different section,
782 whether we have tried to relax this frag yet, and whether we have
783 ever extended a PC relative fragment because of a shift count. */
784 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
787 | ((small) ? 0x100 : 0) \
788 | ((ext) ? 0x200 : 0) \
789 | ((dslot) ? 0x400 : 0) \
790 | ((jal_dslot) ? 0x800 : 0))
791 #define RELAX_MIPS16_P(i) (((i) & 0xc0000000) == 0x80000000)
792 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
793 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
794 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
795 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
796 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
797 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
798 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
799 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
800 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
801 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
802 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
804 /* Is the given value a sign-extended 32-bit value? */
805 #define IS_SEXT_32BIT_NUM(x) \
806 (((x) &~ (offsetT) 0x7fffffff) == 0 \
807 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
809 /* Is the given value a sign-extended 16-bit value? */
810 #define IS_SEXT_16BIT_NUM(x) \
811 (((x) &~ (offsetT) 0x7fff) == 0 \
812 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
815 /* Global variables used when generating relaxable macros. See the
816 comment above RELAX_ENCODE for more details about how relaxation
819 /* 0 if we're not emitting a relaxable macro.
820 1 if we're emitting the first of the two relaxation alternatives.
821 2 if we're emitting the second alternative. */
824 /* The first relaxable fixup in the current frag. (In other words,
825 the first fixup that refers to relaxable code.) */
828 /* sizes[0] says how many bytes of the first alternative are stored in
829 the current frag. Likewise sizes[1] for the second alternative. */
830 unsigned int sizes
[2];
832 /* The symbol on which the choice of sequence depends. */
836 /* Global variables used to decide whether a macro needs a warning. */
838 /* True if the macro is in a branch delay slot. */
839 bfd_boolean delay_slot_p
;
841 /* For relaxable macros, sizes[0] is the length of the first alternative
842 in bytes and sizes[1] is the length of the second alternative.
843 For non-relaxable macros, both elements give the length of the
845 unsigned int sizes
[2];
847 /* The first variant frag for this macro. */
849 } mips_macro_warning
;
851 /* Prototypes for static functions. */
853 #define internalError() \
854 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
856 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
858 static void append_insn
859 (struct mips_cl_insn
*ip
, expressionS
*p
, bfd_reloc_code_real_type
*r
);
860 static void mips_no_prev_insn (int);
861 static void mips16_macro_build
862 (expressionS
*, const char *, const char *, va_list);
863 static void load_register (int, expressionS
*, int);
864 static void macro_start (void);
865 static void macro_end (void);
866 static void macro (struct mips_cl_insn
* ip
);
867 static void mips16_macro (struct mips_cl_insn
* ip
);
868 #ifdef LOSING_COMPILER
869 static void macro2 (struct mips_cl_insn
* ip
);
871 static void mips_ip (char *str
, struct mips_cl_insn
* ip
);
872 static void mips16_ip (char *str
, struct mips_cl_insn
* ip
);
873 static void mips16_immed
874 (char *, unsigned int, int, offsetT
, bfd_boolean
, bfd_boolean
, bfd_boolean
,
875 unsigned long *, bfd_boolean
*, unsigned short *);
876 static size_t my_getSmallExpression
877 (expressionS
*, bfd_reloc_code_real_type
*, char *);
878 static void my_getExpression (expressionS
*, char *);
879 static void s_align (int);
880 static void s_change_sec (int);
881 static void s_change_section (int);
882 static void s_cons (int);
883 static void s_float_cons (int);
884 static void s_mips_globl (int);
885 static void s_option (int);
886 static void s_mipsset (int);
887 static void s_abicalls (int);
888 static void s_cpload (int);
889 static void s_cpsetup (int);
890 static void s_cplocal (int);
891 static void s_cprestore (int);
892 static void s_cpreturn (int);
893 static void s_gpvalue (int);
894 static void s_gpword (int);
895 static void s_gpdword (int);
896 static void s_cpadd (int);
897 static void s_insn (int);
898 static void md_obj_begin (void);
899 static void md_obj_end (void);
900 static void s_mips_ent (int);
901 static void s_mips_end (int);
902 static void s_mips_frame (int);
903 static void s_mips_mask (int reg_type
);
904 static void s_mips_stab (int);
905 static void s_mips_weakext (int);
906 static void s_mips_file (int);
907 static void s_mips_loc (int);
908 static bfd_boolean
pic_need_relax (symbolS
*, asection
*);
909 static int relaxed_branch_length (fragS
*, asection
*, int);
910 static int validate_mips_insn (const struct mips_opcode
*);
912 /* Table and functions used to map between CPU/ISA names, and
913 ISA levels, and CPU numbers. */
917 const char *name
; /* CPU or ISA name. */
918 int is_isa
; /* Is this an ISA? (If 0, a CPU.) */
919 int isa
; /* ISA level. */
920 int cpu
; /* CPU number (default CPU if ISA). */
923 static const struct mips_cpu_info
*mips_parse_cpu (const char *, const char *);
924 static const struct mips_cpu_info
*mips_cpu_info_from_isa (int);
925 static const struct mips_cpu_info
*mips_cpu_info_from_arch (int);
929 The following pseudo-ops from the Kane and Heinrich MIPS book
930 should be defined here, but are currently unsupported: .alias,
931 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
933 The following pseudo-ops from the Kane and Heinrich MIPS book are
934 specific to the type of debugging information being generated, and
935 should be defined by the object format: .aent, .begin, .bend,
936 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
939 The following pseudo-ops from the Kane and Heinrich MIPS book are
940 not MIPS CPU specific, but are also not specific to the object file
941 format. This file is probably the best place to define them, but
942 they are not currently supported: .asm0, .endr, .lab, .repeat,
945 static const pseudo_typeS mips_pseudo_table
[] =
947 /* MIPS specific pseudo-ops. */
948 {"option", s_option
, 0},
949 {"set", s_mipsset
, 0},
950 {"rdata", s_change_sec
, 'r'},
951 {"sdata", s_change_sec
, 's'},
952 {"livereg", s_ignore
, 0},
953 {"abicalls", s_abicalls
, 0},
954 {"cpload", s_cpload
, 0},
955 {"cpsetup", s_cpsetup
, 0},
956 {"cplocal", s_cplocal
, 0},
957 {"cprestore", s_cprestore
, 0},
958 {"cpreturn", s_cpreturn
, 0},
959 {"gpvalue", s_gpvalue
, 0},
960 {"gpword", s_gpword
, 0},
961 {"gpdword", s_gpdword
, 0},
962 {"cpadd", s_cpadd
, 0},
965 /* Relatively generic pseudo-ops that happen to be used on MIPS
967 {"asciiz", stringer
, 1},
968 {"bss", s_change_sec
, 'b'},
971 {"dword", s_cons
, 3},
972 {"weakext", s_mips_weakext
, 0},
974 /* These pseudo-ops are defined in read.c, but must be overridden
975 here for one reason or another. */
976 {"align", s_align
, 0},
978 {"data", s_change_sec
, 'd'},
979 {"double", s_float_cons
, 'd'},
980 {"float", s_float_cons
, 'f'},
981 {"globl", s_mips_globl
, 0},
982 {"global", s_mips_globl
, 0},
983 {"hword", s_cons
, 1},
988 {"section", s_change_section
, 0},
989 {"short", s_cons
, 1},
990 {"single", s_float_cons
, 'f'},
991 {"stabn", s_mips_stab
, 'n'},
992 {"text", s_change_sec
, 't'},
995 { "extern", ecoff_directive_extern
, 0},
1000 static const pseudo_typeS mips_nonecoff_pseudo_table
[] =
1002 /* These pseudo-ops should be defined by the object file format.
1003 However, a.out doesn't support them, so we have versions here. */
1004 {"aent", s_mips_ent
, 1},
1005 {"bgnb", s_ignore
, 0},
1006 {"end", s_mips_end
, 0},
1007 {"endb", s_ignore
, 0},
1008 {"ent", s_mips_ent
, 0},
1009 {"file", s_mips_file
, 0},
1010 {"fmask", s_mips_mask
, 'F'},
1011 {"frame", s_mips_frame
, 0},
1012 {"loc", s_mips_loc
, 0},
1013 {"mask", s_mips_mask
, 'R'},
1014 {"verstamp", s_ignore
, 0},
1018 extern void pop_insert (const pseudo_typeS
*);
1021 mips_pop_insert (void)
1023 pop_insert (mips_pseudo_table
);
1024 if (! ECOFF_DEBUGGING
)
1025 pop_insert (mips_nonecoff_pseudo_table
);
1028 /* Symbols labelling the current insn. */
1030 struct insn_label_list
1032 struct insn_label_list
*next
;
1036 static struct insn_label_list
*insn_labels
;
1037 static struct insn_label_list
*free_insn_labels
;
1039 static void mips_clear_insn_labels (void);
1042 mips_clear_insn_labels (void)
1044 register struct insn_label_list
**pl
;
1046 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
1052 static char *expr_end
;
1054 /* Expressions which appear in instructions. These are set by
1057 static expressionS imm_expr
;
1058 static expressionS imm2_expr
;
1059 static expressionS offset_expr
;
1061 /* Relocs associated with imm_expr and offset_expr. */
1063 static bfd_reloc_code_real_type imm_reloc
[3]
1064 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1065 static bfd_reloc_code_real_type offset_reloc
[3]
1066 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1068 /* These are set by mips16_ip if an explicit extension is used. */
1070 static bfd_boolean mips16_small
, mips16_ext
;
1073 /* The pdr segment for per procedure frame/regmask info. Not used for
1076 static segT pdr_seg
;
1079 /* The default target format to use. */
1082 mips_target_format (void)
1084 switch (OUTPUT_FLAVOR
)
1086 case bfd_target_aout_flavour
:
1087 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
1088 case bfd_target_ecoff_flavour
:
1089 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
1090 case bfd_target_coff_flavour
:
1092 case bfd_target_elf_flavour
:
1094 /* This is traditional mips. */
1095 return (target_big_endian
1096 ? (HAVE_64BIT_OBJECTS
1097 ? "elf64-tradbigmips"
1099 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1100 : (HAVE_64BIT_OBJECTS
1101 ? "elf64-tradlittlemips"
1103 ? "elf32-ntradlittlemips" : "elf32-tradlittlemips")));
1105 return (target_big_endian
1106 ? (HAVE_64BIT_OBJECTS
1109 ? "elf32-nbigmips" : "elf32-bigmips"))
1110 : (HAVE_64BIT_OBJECTS
1111 ? "elf64-littlemips"
1113 ? "elf32-nlittlemips" : "elf32-littlemips")));
1121 /* This function is called once, at assembler startup time. It should
1122 set up all the tables, etc. that the MD part of the assembler will need. */
1127 register const char *retval
= NULL
;
1131 if (! bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, file_mips_arch
))
1132 as_warn (_("Could not set architecture and machine"));
1134 op_hash
= hash_new ();
1136 for (i
= 0; i
< NUMOPCODES
;)
1138 const char *name
= mips_opcodes
[i
].name
;
1140 retval
= hash_insert (op_hash
, name
, (void *) &mips_opcodes
[i
]);
1143 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1144 mips_opcodes
[i
].name
, retval
);
1145 /* Probably a memory allocation problem? Give up now. */
1146 as_fatal (_("Broken assembler. No assembly attempted."));
1150 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1152 if (!validate_mips_insn (&mips_opcodes
[i
]))
1157 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1160 mips16_op_hash
= hash_new ();
1163 while (i
< bfd_mips16_num_opcodes
)
1165 const char *name
= mips16_opcodes
[i
].name
;
1167 retval
= hash_insert (mips16_op_hash
, name
, (void *) &mips16_opcodes
[i
]);
1169 as_fatal (_("internal: can't hash `%s': %s"),
1170 mips16_opcodes
[i
].name
, retval
);
1173 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1174 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1175 != mips16_opcodes
[i
].match
))
1177 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1178 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1183 while (i
< bfd_mips16_num_opcodes
1184 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1188 as_fatal (_("Broken assembler. No assembly attempted."));
1190 /* We add all the general register names to the symbol table. This
1191 helps us detect invalid uses of them. */
1192 for (i
= 0; i
< 32; i
++)
1196 sprintf (buf
, "$%d", i
);
1197 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1198 &zero_address_frag
));
1200 symbol_table_insert (symbol_new ("$ra", reg_section
, RA
,
1201 &zero_address_frag
));
1202 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1203 &zero_address_frag
));
1204 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1205 &zero_address_frag
));
1206 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1207 &zero_address_frag
));
1208 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1209 &zero_address_frag
));
1210 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1211 &zero_address_frag
));
1212 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1213 &zero_address_frag
));
1214 symbol_table_insert (symbol_new ("$zero", reg_section
, ZERO
,
1215 &zero_address_frag
));
1216 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1217 &zero_address_frag
));
1219 /* If we don't add these register names to the symbol table, they
1220 may end up being added as regular symbols by operand(), and then
1221 make it to the object file as undefined in case they're not
1222 regarded as local symbols. They're local in o32, since `$' is a
1223 local symbol prefix, but not in n32 or n64. */
1224 for (i
= 0; i
< 8; i
++)
1228 sprintf (buf
, "$fcc%i", i
);
1229 symbol_table_insert (symbol_new (buf
, reg_section
, -1,
1230 &zero_address_frag
));
1233 mips_no_prev_insn (FALSE
);
1236 mips_cprmask
[0] = 0;
1237 mips_cprmask
[1] = 0;
1238 mips_cprmask
[2] = 0;
1239 mips_cprmask
[3] = 0;
1241 /* set the default alignment for the text section (2**2) */
1242 record_alignment (text_section
, 2);
1244 if (USE_GLOBAL_POINTER_OPT
)
1245 bfd_set_gp_size (stdoutput
, g_switch_value
);
1247 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1249 /* On a native system, sections must be aligned to 16 byte
1250 boundaries. When configured for an embedded ELF target, we
1252 if (strcmp (TARGET_OS
, "elf") != 0)
1254 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1255 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1256 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1259 /* Create a .reginfo section for register masks and a .mdebug
1260 section for debugging information. */
1268 subseg
= now_subseg
;
1270 /* The ABI says this section should be loaded so that the
1271 running program can access it. However, we don't load it
1272 if we are configured for an embedded target */
1273 flags
= SEC_READONLY
| SEC_DATA
;
1274 if (strcmp (TARGET_OS
, "elf") != 0)
1275 flags
|= SEC_ALLOC
| SEC_LOAD
;
1277 if (mips_abi
!= N64_ABI
)
1279 sec
= subseg_new (".reginfo", (subsegT
) 0);
1281 bfd_set_section_flags (stdoutput
, sec
, flags
);
1282 bfd_set_section_alignment (stdoutput
, sec
, HAVE_NEWABI
? 3 : 2);
1285 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1290 /* The 64-bit ABI uses a .MIPS.options section rather than
1291 .reginfo section. */
1292 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1293 bfd_set_section_flags (stdoutput
, sec
, flags
);
1294 bfd_set_section_alignment (stdoutput
, sec
, 3);
1297 /* Set up the option header. */
1299 Elf_Internal_Options opthdr
;
1302 opthdr
.kind
= ODK_REGINFO
;
1303 opthdr
.size
= (sizeof (Elf_External_Options
)
1304 + sizeof (Elf64_External_RegInfo
));
1307 f
= frag_more (sizeof (Elf_External_Options
));
1308 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1309 (Elf_External_Options
*) f
);
1311 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1316 if (ECOFF_DEBUGGING
)
1318 sec
= subseg_new (".mdebug", (subsegT
) 0);
1319 (void) bfd_set_section_flags (stdoutput
, sec
,
1320 SEC_HAS_CONTENTS
| SEC_READONLY
);
1321 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1324 else if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& mips_flag_pdr
)
1326 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1327 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1328 SEC_READONLY
| SEC_RELOC
1330 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1334 subseg_set (seg
, subseg
);
1338 if (! ECOFF_DEBUGGING
)
1345 if (! ECOFF_DEBUGGING
)
1350 md_assemble (char *str
)
1352 struct mips_cl_insn insn
;
1353 bfd_reloc_code_real_type unused_reloc
[3]
1354 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
1356 imm_expr
.X_op
= O_absent
;
1357 imm2_expr
.X_op
= O_absent
;
1358 offset_expr
.X_op
= O_absent
;
1359 imm_reloc
[0] = BFD_RELOC_UNUSED
;
1360 imm_reloc
[1] = BFD_RELOC_UNUSED
;
1361 imm_reloc
[2] = BFD_RELOC_UNUSED
;
1362 offset_reloc
[0] = BFD_RELOC_UNUSED
;
1363 offset_reloc
[1] = BFD_RELOC_UNUSED
;
1364 offset_reloc
[2] = BFD_RELOC_UNUSED
;
1366 if (mips_opts
.mips16
)
1367 mips16_ip (str
, &insn
);
1370 mips_ip (str
, &insn
);
1371 DBG ((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1372 str
, insn
.insn_opcode
));
1377 as_bad ("%s `%s'", insn_error
, str
);
1381 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1384 if (mips_opts
.mips16
)
1385 mips16_macro (&insn
);
1392 if (imm_expr
.X_op
!= O_absent
)
1393 append_insn (&insn
, &imm_expr
, imm_reloc
);
1394 else if (offset_expr
.X_op
!= O_absent
)
1395 append_insn (&insn
, &offset_expr
, offset_reloc
);
1397 append_insn (&insn
, NULL
, unused_reloc
);
1401 /* Return true if the given relocation might need a matching %lo().
1402 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1403 applied to local symbols. */
1405 static inline bfd_boolean
1406 reloc_needs_lo_p (bfd_reloc_code_real_type reloc
)
1408 return (reloc
== BFD_RELOC_HI16_S
1409 || reloc
== BFD_RELOC_MIPS_GOT16
);
1412 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
1415 static inline bfd_boolean
1416 fixup_has_matching_lo_p (fixS
*fixp
)
1418 return (fixp
->fx_next
!= NULL
1419 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
1420 && fixp
->fx_addsy
== fixp
->fx_next
->fx_addsy
1421 && fixp
->fx_offset
== fixp
->fx_next
->fx_offset
);
1424 /* See whether instruction IP reads register REG. CLASS is the type
1428 insn_uses_reg (struct mips_cl_insn
*ip
, unsigned int reg
,
1429 enum mips_regclass
class)
1431 if (class == MIPS16_REG
)
1433 assert (mips_opts
.mips16
);
1434 reg
= mips16_to_32_reg_map
[reg
];
1435 class = MIPS_GR_REG
;
1438 /* Don't report on general register ZERO, since it never changes. */
1439 if (class == MIPS_GR_REG
&& reg
== ZERO
)
1442 if (class == MIPS_FP_REG
)
1444 assert (! mips_opts
.mips16
);
1445 /* If we are called with either $f0 or $f1, we must check $f0.
1446 This is not optimal, because it will introduce an unnecessary
1447 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1448 need to distinguish reading both $f0 and $f1 or just one of
1449 them. Note that we don't have to check the other way,
1450 because there is no instruction that sets both $f0 and $f1
1451 and requires a delay. */
1452 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1453 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1454 == (reg
&~ (unsigned) 1)))
1456 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1457 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1458 == (reg
&~ (unsigned) 1)))
1461 else if (! mips_opts
.mips16
)
1463 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1464 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1466 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1467 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1472 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1473 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1474 & MIPS16OP_MASK_RX
)]
1477 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1478 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1479 & MIPS16OP_MASK_RY
)]
1482 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1483 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1484 & MIPS16OP_MASK_MOVE32Z
)]
1487 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1489 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1491 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1493 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1494 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1495 & MIPS16OP_MASK_REGR32
) == reg
)
1502 /* This function returns true if modifying a register requires a
1506 reg_needs_delay (unsigned int reg
)
1508 unsigned long prev_pinfo
;
1510 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1511 if (! mips_opts
.noreorder
1512 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1513 && ! gpr_interlocks
)
1514 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1515 && ! cop_interlocks
)))
1517 /* A load from a coprocessor or from memory. All load delays
1518 delay the use of general register rt for one instruction. */
1519 /* Itbl support may require additional care here. */
1520 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1521 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1528 /* Mark instruction labels in mips16 mode. This permits the linker to
1529 handle them specially, such as generating jalx instructions when
1530 needed. We also make them odd for the duration of the assembly, in
1531 order to generate the right sort of code. We will make them even
1532 in the adjust_symtab routine, while leaving them marked. This is
1533 convenient for the debugger and the disassembler. The linker knows
1534 to make them odd again. */
1537 mips16_mark_labels (void)
1539 if (mips_opts
.mips16
)
1541 struct insn_label_list
*l
;
1544 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1547 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1548 S_SET_OTHER (l
->label
, STO_MIPS16
);
1550 val
= S_GET_VALUE (l
->label
);
1552 S_SET_VALUE (l
->label
, val
+ 1);
1557 /* End the current frag. Make it a variant frag and record the
1561 relax_close_frag (void)
1563 mips_macro_warning
.first_frag
= frag_now
;
1564 frag_var (rs_machine_dependent
, 0, 0,
1565 RELAX_ENCODE (mips_relax
.sizes
[0], mips_relax
.sizes
[1]),
1566 mips_relax
.symbol
, 0, (char *) mips_relax
.first_fixup
);
1568 memset (&mips_relax
.sizes
, 0, sizeof (mips_relax
.sizes
));
1569 mips_relax
.first_fixup
= 0;
1572 /* Start a new relaxation sequence whose expansion depends on SYMBOL.
1573 See the comment above RELAX_ENCODE for more details. */
1576 relax_start (symbolS
*symbol
)
1578 assert (mips_relax
.sequence
== 0);
1579 mips_relax
.sequence
= 1;
1580 mips_relax
.symbol
= symbol
;
1583 /* Start generating the second version of a relaxable sequence.
1584 See the comment above RELAX_ENCODE for more details. */
1589 assert (mips_relax
.sequence
== 1);
1590 mips_relax
.sequence
= 2;
1593 /* End the current relaxable sequence. */
1598 assert (mips_relax
.sequence
== 2);
1599 relax_close_frag ();
1600 mips_relax
.sequence
= 0;
1603 /* Output an instruction. IP is the instruction information.
1604 ADDRESS_EXPR is an operand of the instruction to be used with
1608 append_insn (struct mips_cl_insn
*ip
, expressionS
*address_expr
,
1609 bfd_reloc_code_real_type
*reloc_type
)
1611 register unsigned long prev_pinfo
, pinfo
;
1615 relax_stateT prev_insn_frag_type
= 0;
1616 bfd_boolean relaxed_branch
= FALSE
;
1617 bfd_boolean force_new_frag
= FALSE
;
1619 /* Mark instruction labels in mips16 mode. */
1620 mips16_mark_labels ();
1622 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1623 pinfo
= ip
->insn_mo
->pinfo
;
1625 if (mips_relax
.sequence
!= 2
1626 && (!mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1630 /* If the previous insn required any delay slots, see if we need
1631 to insert a NOP or two. There are eight kinds of possible
1632 hazards, of which an instruction can have at most one type.
1633 (1) a load from memory delay
1634 (2) a load from a coprocessor delay
1635 (3) an unconditional branch delay
1636 (4) a conditional branch delay
1637 (5) a move to coprocessor register delay
1638 (6) a load coprocessor register from memory delay
1639 (7) a coprocessor condition code delay
1640 (8) a HI/LO special register delay
1642 There are a lot of optimizations we could do that we don't.
1643 In particular, we do not, in general, reorder instructions.
1644 If you use gcc with optimization, it will reorder
1645 instructions and generally do much more optimization then we
1646 do here; repeating all that work in the assembler would only
1647 benefit hand written assembly code, and does not seem worth
1650 /* This is how a NOP is emitted. */
1651 #define emit_nop() \
1653 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1654 : md_number_to_chars (frag_more (4), 0, 4))
1656 /* The previous insn might require a delay slot, depending upon
1657 the contents of the current insn. */
1658 if (! mips_opts
.mips16
1659 && (((prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
1660 && ! gpr_interlocks
)
1661 || ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1662 && ! cop_interlocks
)))
1664 /* A load from a coprocessor or from memory. All load
1665 delays delay the use of general register rt for one
1667 /* Itbl support may require additional care here. */
1668 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1669 if (mips_optimize
== 0
1670 || insn_uses_reg (ip
,
1671 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1676 else if (! mips_opts
.mips16
1677 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1678 && ! cop_interlocks
)
1679 || ((prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
1680 && ! cop_mem_interlocks
)))
1682 /* A generic coprocessor delay. The previous instruction
1683 modified a coprocessor general or control register. If
1684 it modified a control register, we need to avoid any
1685 coprocessor instruction (this is probably not always
1686 required, but it sometimes is). If it modified a general
1687 register, we avoid using that register.
1689 This case is not handled very well. There is no special
1690 knowledge of CP0 handling, and the coprocessors other
1691 than the floating point unit are not distinguished at
1693 /* Itbl support may require additional care here. FIXME!
1694 Need to modify this to include knowledge about
1695 user specified delays! */
1696 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1698 if (mips_optimize
== 0
1699 || insn_uses_reg (ip
,
1700 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1705 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1707 if (mips_optimize
== 0
1708 || insn_uses_reg (ip
,
1709 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1716 /* We don't know exactly what the previous instruction
1717 does. If the current instruction uses a coprocessor
1718 register, we must insert a NOP. If previous
1719 instruction may set the condition codes, and the
1720 current instruction uses them, we must insert two
1722 /* Itbl support may require additional care here. */
1723 if (mips_optimize
== 0
1724 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1725 && (pinfo
& INSN_READ_COND_CODE
)))
1727 else if (pinfo
& INSN_COP
)
1731 else if (! mips_opts
.mips16
1732 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1733 && ! cop_interlocks
)
1735 /* The previous instruction sets the coprocessor condition
1736 codes, but does not require a general coprocessor delay
1737 (this means it is a floating point comparison
1738 instruction). If this instruction uses the condition
1739 codes, we need to insert a single NOP. */
1740 /* Itbl support may require additional care here. */
1741 if (mips_optimize
== 0
1742 || (pinfo
& INSN_READ_COND_CODE
))
1746 /* If we're fixing up mfhi/mflo for the r7000 and the
1747 previous insn was an mfhi/mflo and the current insn
1748 reads the register that the mfhi/mflo wrote to, then
1751 else if (mips_7000_hilo_fix
1752 && MF_HILO_INSN (prev_pinfo
)
1753 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1760 /* If we're fixing up mfhi/mflo for the r7000 and the
1761 2nd previous insn was an mfhi/mflo and the current insn
1762 reads the register that the mfhi/mflo wrote to, then
1765 else if (mips_7000_hilo_fix
1766 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1767 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1775 else if (prev_pinfo
& INSN_READ_LO
)
1777 /* The previous instruction reads the LO register; if the
1778 current instruction writes to the LO register, we must
1779 insert two NOPS. Some newer processors have interlocks.
1780 Also the tx39's multiply instructions can be executed
1781 immediately after a read from HI/LO (without the delay),
1782 though the tx39's divide insns still do require the
1784 if (! (hilo_interlocks
1785 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1786 && (mips_optimize
== 0
1787 || (pinfo
& INSN_WRITE_LO
)))
1789 /* Most mips16 branch insns don't have a delay slot.
1790 If a read from LO is immediately followed by a branch
1791 to a write to LO we have a read followed by a write
1792 less than 2 insns away. We assume the target of
1793 a branch might be a write to LO, and insert a nop
1794 between a read and an immediately following branch. */
1795 else if (mips_opts
.mips16
1796 && (mips_optimize
== 0
1797 || (pinfo
& MIPS16_INSN_BRANCH
)))
1800 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1802 /* The previous instruction reads the HI register; if the
1803 current instruction writes to the HI register, we must
1804 insert a NOP. Some newer processors have interlocks.
1805 Also the note tx39's multiply above. */
1806 if (! (hilo_interlocks
1807 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
1808 && (mips_optimize
== 0
1809 || (pinfo
& INSN_WRITE_HI
)))
1811 /* Most mips16 branch insns don't have a delay slot.
1812 If a read from HI is immediately followed by a branch
1813 to a write to HI we have a read followed by a write
1814 less than 2 insns away. We assume the target of
1815 a branch might be a write to HI, and insert a nop
1816 between a read and an immediately following branch. */
1817 else if (mips_opts
.mips16
1818 && (mips_optimize
== 0
1819 || (pinfo
& MIPS16_INSN_BRANCH
)))
1823 /* If the previous instruction was in a noreorder section, then
1824 we don't want to insert the nop after all. */
1825 /* Itbl support may require additional care here. */
1826 if (prev_insn_unreordered
)
1829 /* There are two cases which require two intervening
1830 instructions: 1) setting the condition codes using a move to
1831 coprocessor instruction which requires a general coprocessor
1832 delay and then reading the condition codes 2) reading the HI
1833 or LO register and then writing to it (except on processors
1834 which have interlocks). If we are not already emitting a NOP
1835 instruction, we must check for these cases compared to the
1836 instruction previous to the previous instruction. */
1837 if ((! mips_opts
.mips16
1838 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1839 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1840 && (pinfo
& INSN_READ_COND_CODE
)
1841 && ! cop_interlocks
)
1842 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1843 && (pinfo
& INSN_WRITE_LO
)
1844 && ! (hilo_interlocks
1845 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
))))
1846 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1847 && (pinfo
& INSN_WRITE_HI
)
1848 && ! (hilo_interlocks
1849 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))))
1854 if (prev_prev_insn_unreordered
)
1857 if (prev_prev_nop
&& nops
== 0)
1860 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
1862 /* We're out of bits in pinfo, so we must resort to string
1863 ops here. Shortcuts are selected based on opcodes being
1864 limited to the VR4120 instruction set. */
1866 const char *pn
= prev_insn
.insn_mo
->name
;
1867 const char *tn
= ip
->insn_mo
->name
;
1868 if (strncmp(pn
, "macc", 4) == 0
1869 || strncmp(pn
, "dmacc", 5) == 0)
1871 /* Errata 21 - [D]DIV[U] after [D]MACC */
1872 if (strstr (tn
, "div"))
1877 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1878 if (pn
[0] == 'd' /* dmacc */
1879 && (strncmp(tn
, "dmult", 5) == 0
1880 || strncmp(tn
, "dmacc", 5) == 0))
1885 /* Errata 24 - MT{LO,HI} after [D]MACC */
1886 if (strcmp (tn
, "mtlo") == 0
1887 || strcmp (tn
, "mthi") == 0)
1893 else if (strncmp(pn
, "dmult", 5) == 0
1894 && (strncmp(tn
, "dmult", 5) == 0
1895 || strncmp(tn
, "dmacc", 5) == 0))
1897 /* Here is the rest of errata 23. */
1900 if (nops
< min_nops
)
1904 /* If we are being given a nop instruction, don't bother with
1905 one of the nops we would otherwise output. This will only
1906 happen when a nop instruction is used with mips_optimize set
1909 && ! mips_opts
.noreorder
1910 && ip
->insn_opcode
== (unsigned) (mips_opts
.mips16
? 0x6500 : 0))
1913 /* Now emit the right number of NOP instructions. */
1914 if (nops
> 0 && ! mips_opts
.noreorder
)
1917 unsigned long old_frag_offset
;
1919 struct insn_label_list
*l
;
1921 old_frag
= frag_now
;
1922 old_frag_offset
= frag_now_fix ();
1924 for (i
= 0; i
< nops
; i
++)
1929 listing_prev_line ();
1930 /* We may be at the start of a variant frag. In case we
1931 are, make sure there is enough space for the frag
1932 after the frags created by listing_prev_line. The
1933 argument to frag_grow here must be at least as large
1934 as the argument to all other calls to frag_grow in
1935 this file. We don't have to worry about being in the
1936 middle of a variant frag, because the variants insert
1937 all needed nop instructions themselves. */
1941 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1945 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1946 symbol_set_frag (l
->label
, frag_now
);
1947 val
= (valueT
) frag_now_fix ();
1948 /* mips16 text labels are stored as odd. */
1949 if (mips_opts
.mips16
)
1951 S_SET_VALUE (l
->label
, val
);
1954 #ifndef NO_ECOFF_DEBUGGING
1955 if (ECOFF_DEBUGGING
)
1956 ecoff_fix_loc (old_frag
, old_frag_offset
);
1959 else if (prev_nop_frag
!= NULL
)
1961 /* We have a frag holding nops we may be able to remove. If
1962 we don't need any nops, we can decrease the size of
1963 prev_nop_frag by the size of one instruction. If we do
1964 need some nops, we count them in prev_nops_required. */
1965 if (prev_nop_frag_since
== 0)
1969 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1970 --prev_nop_frag_holds
;
1973 prev_nop_frag_required
+= nops
;
1977 if (prev_prev_nop
== 0)
1979 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1980 --prev_nop_frag_holds
;
1983 ++prev_nop_frag_required
;
1986 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1987 prev_nop_frag
= NULL
;
1989 ++prev_nop_frag_since
;
1991 /* Sanity check: by the time we reach the second instruction
1992 after prev_nop_frag, we should have used up all the nops
1993 one way or another. */
1994 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1998 /* Record the frag type before frag_var. */
2000 prev_insn_frag_type
= prev_insn_frag
->fr_type
;
2003 && *reloc_type
== BFD_RELOC_16_PCREL_S2
2004 && (pinfo
& INSN_UNCOND_BRANCH_DELAY
|| pinfo
& INSN_COND_BRANCH_DELAY
2005 || pinfo
& INSN_COND_BRANCH_LIKELY
)
2006 && mips_relax_branch
2007 /* Don't try branch relaxation within .set nomacro, or within
2008 .set noat if we use $at for PIC computations. If it turns
2009 out that the branch was out-of-range, we'll get an error. */
2010 && !mips_opts
.warn_about_macros
2011 && !(mips_opts
.noat
&& mips_pic
!= NO_PIC
)
2012 && !mips_opts
.mips16
)
2014 relaxed_branch
= TRUE
;
2015 f
= frag_var (rs_machine_dependent
,
2016 relaxed_branch_length
2018 (pinfo
& INSN_UNCOND_BRANCH_DELAY
) ? -1
2019 : (pinfo
& INSN_COND_BRANCH_LIKELY
) ? 1 : 0), 4,
2021 (pinfo
& INSN_UNCOND_BRANCH_DELAY
,
2022 pinfo
& INSN_COND_BRANCH_LIKELY
,
2023 pinfo
& INSN_WRITE_GPR_31
,
2025 address_expr
->X_add_symbol
,
2026 address_expr
->X_add_number
,
2028 *reloc_type
= BFD_RELOC_UNUSED
;
2030 else if (*reloc_type
> BFD_RELOC_UNUSED
)
2032 /* We need to set up a variant frag. */
2033 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
2034 f
= frag_var (rs_machine_dependent
, 4, 0,
2035 RELAX_MIPS16_ENCODE (*reloc_type
- BFD_RELOC_UNUSED
,
2036 mips16_small
, mips16_ext
,
2038 & INSN_UNCOND_BRANCH_DELAY
),
2039 (*prev_insn_reloc_type
2040 == BFD_RELOC_MIPS16_JMP
)),
2041 make_expr_symbol (address_expr
), 0, NULL
);
2043 else if (mips_opts
.mips16
2045 && *reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2047 /* Make sure there is enough room to swap this instruction with
2048 a following jump instruction. */
2054 if (mips_opts
.mips16
2055 && mips_opts
.noreorder
2056 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
2057 as_warn (_("extended instruction in delay slot"));
2059 if (mips_relax
.sequence
)
2061 /* If we've reached the end of this frag, turn it into a variant
2062 frag and record the information for the instructions we've
2064 if (frag_room () < 4)
2065 relax_close_frag ();
2066 mips_relax
.sizes
[mips_relax
.sequence
- 1] += 4;
2069 if (mips_relax
.sequence
!= 2)
2070 mips_macro_warning
.sizes
[0] += 4;
2071 if (mips_relax
.sequence
!= 1)
2072 mips_macro_warning
.sizes
[1] += 4;
2077 fixp
[0] = fixp
[1] = fixp
[2] = NULL
;
2078 if (address_expr
!= NULL
&& *reloc_type
< BFD_RELOC_UNUSED
)
2080 if (address_expr
->X_op
== O_constant
)
2084 switch (*reloc_type
)
2087 ip
->insn_opcode
|= address_expr
->X_add_number
;
2090 case BFD_RELOC_MIPS_HIGHEST
:
2091 tmp
= (address_expr
->X_add_number
2092 + ((valueT
) 0x8000 << 32) + 0x80008000) >> 16;
2094 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2097 case BFD_RELOC_MIPS_HIGHER
:
2098 tmp
= (address_expr
->X_add_number
+ 0x80008000) >> 16;
2099 ip
->insn_opcode
|= (tmp
>> 16) & 0xffff;
2102 case BFD_RELOC_HI16_S
:
2103 ip
->insn_opcode
|= ((address_expr
->X_add_number
+ 0x8000)
2107 case BFD_RELOC_HI16
:
2108 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 16) & 0xffff;
2111 case BFD_RELOC_LO16
:
2112 case BFD_RELOC_MIPS_GOT_DISP
:
2113 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
2116 case BFD_RELOC_MIPS_JMP
:
2117 if ((address_expr
->X_add_number
& 3) != 0)
2118 as_bad (_("jump to misaligned address (0x%lx)"),
2119 (unsigned long) address_expr
->X_add_number
);
2120 if (address_expr
->X_add_number
& ~0xfffffff)
2121 as_bad (_("jump address range overflow (0x%lx)"),
2122 (unsigned long) address_expr
->X_add_number
);
2123 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
2126 case BFD_RELOC_MIPS16_JMP
:
2127 if ((address_expr
->X_add_number
& 3) != 0)
2128 as_bad (_("jump to misaligned address (0x%lx)"),
2129 (unsigned long) address_expr
->X_add_number
);
2130 if (address_expr
->X_add_number
& ~0xfffffff)
2131 as_bad (_("jump address range overflow (0x%lx)"),
2132 (unsigned long) address_expr
->X_add_number
);
2134 (((address_expr
->X_add_number
& 0x7c0000) << 3)
2135 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
2136 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
2139 case BFD_RELOC_16_PCREL_S2
:
2149 reloc_howto_type
*howto
;
2152 /* In a compound relocation, it is the final (outermost)
2153 operator that determines the relocated field. */
2154 for (i
= 1; i
< 3; i
++)
2155 if (reloc_type
[i
] == BFD_RELOC_UNUSED
)
2158 howto
= bfd_reloc_type_lookup (stdoutput
, reloc_type
[i
- 1]);
2159 fixp
[0] = fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
2160 bfd_get_reloc_size(howto
),
2162 reloc_type
[0] == BFD_RELOC_16_PCREL_S2
,
2165 /* These relocations can have an addend that won't fit in
2166 4 octets for 64bit assembly. */
2168 && ! howto
->partial_inplace
2169 && (reloc_type
[0] == BFD_RELOC_16
2170 || reloc_type
[0] == BFD_RELOC_32
2171 || reloc_type
[0] == BFD_RELOC_MIPS_JMP
2172 || reloc_type
[0] == BFD_RELOC_HI16_S
2173 || reloc_type
[0] == BFD_RELOC_LO16
2174 || reloc_type
[0] == BFD_RELOC_GPREL16
2175 || reloc_type
[0] == BFD_RELOC_MIPS_LITERAL
2176 || reloc_type
[0] == BFD_RELOC_GPREL32
2177 || reloc_type
[0] == BFD_RELOC_64
2178 || reloc_type
[0] == BFD_RELOC_CTOR
2179 || reloc_type
[0] == BFD_RELOC_MIPS_SUB
2180 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHEST
2181 || reloc_type
[0] == BFD_RELOC_MIPS_HIGHER
2182 || reloc_type
[0] == BFD_RELOC_MIPS_SCN_DISP
2183 || reloc_type
[0] == BFD_RELOC_MIPS_REL16
2184 || reloc_type
[0] == BFD_RELOC_MIPS_RELGOT
))
2185 fixp
[0]->fx_no_overflow
= 1;
2187 if (mips_relax
.sequence
)
2189 if (mips_relax
.first_fixup
== 0)
2190 mips_relax
.first_fixup
= fixp
[0];
2192 else if (reloc_needs_lo_p (*reloc_type
))
2194 struct mips_hi_fixup
*hi_fixup
;
2196 /* Reuse the last entry if it already has a matching %lo. */
2197 hi_fixup
= mips_hi_fixup_list
;
2199 || !fixup_has_matching_lo_p (hi_fixup
->fixp
))
2201 hi_fixup
= ((struct mips_hi_fixup
*)
2202 xmalloc (sizeof (struct mips_hi_fixup
)));
2203 hi_fixup
->next
= mips_hi_fixup_list
;
2204 mips_hi_fixup_list
= hi_fixup
;
2206 hi_fixup
->fixp
= fixp
[0];
2207 hi_fixup
->seg
= now_seg
;
2210 /* Add fixups for the second and third relocations, if given.
2211 Note that the ABI allows the second relocation to be
2212 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2213 moment we only use RSS_UNDEF, but we could add support
2214 for the others if it ever becomes necessary. */
2215 for (i
= 1; i
< 3; i
++)
2216 if (reloc_type
[i
] != BFD_RELOC_UNUSED
)
2218 address_expr
->X_op
= O_absent
;
2219 address_expr
->X_add_symbol
= 0;
2220 address_expr
->X_add_number
= 0;
2222 fixp
[i
] = fix_new_exp (frag_now
, fixp
[0]->fx_where
,
2223 fixp
[0]->fx_size
, address_expr
,
2224 FALSE
, reloc_type
[i
]);
2229 if (! mips_opts
.mips16
)
2231 md_number_to_chars (f
, ip
->insn_opcode
, 4);
2233 dwarf2_emit_insn (4);
2236 else if (*reloc_type
== BFD_RELOC_MIPS16_JMP
)
2238 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
2239 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
2241 dwarf2_emit_insn (4);
2248 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
2251 md_number_to_chars (f
, ip
->insn_opcode
, 2);
2253 dwarf2_emit_insn (ip
->use_extend
? 4 : 2);
2257 /* Update the register mask information. */
2258 if (! mips_opts
.mips16
)
2260 if (pinfo
& INSN_WRITE_GPR_D
)
2261 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
2262 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
2263 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
2264 if (pinfo
& INSN_READ_GPR_S
)
2265 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
2266 if (pinfo
& INSN_WRITE_GPR_31
)
2267 mips_gprmask
|= 1 << RA
;
2268 if (pinfo
& INSN_WRITE_FPR_D
)
2269 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
2270 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
2271 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
2272 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
2273 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
2274 if ((pinfo
& INSN_READ_FPR_R
) != 0)
2275 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
2276 if (pinfo
& INSN_COP
)
2278 /* We don't keep enough information to sort these cases out.
2279 The itbl support does keep this information however, although
2280 we currently don't support itbl fprmats as part of the cop
2281 instruction. May want to add this support in the future. */
2283 /* Never set the bit for $0, which is always zero. */
2284 mips_gprmask
&= ~1 << 0;
2288 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
2289 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
2290 & MIPS16OP_MASK_RX
);
2291 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
2292 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
2293 & MIPS16OP_MASK_RY
);
2294 if (pinfo
& MIPS16_INSN_WRITE_Z
)
2295 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
2296 & MIPS16OP_MASK_RZ
);
2297 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
2298 mips_gprmask
|= 1 << TREG
;
2299 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
2300 mips_gprmask
|= 1 << SP
;
2301 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
2302 mips_gprmask
|= 1 << RA
;
2303 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2304 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
2305 if (pinfo
& MIPS16_INSN_READ_Z
)
2306 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
2307 & MIPS16OP_MASK_MOVE32Z
);
2308 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
2309 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
2310 & MIPS16OP_MASK_REGR32
);
2313 if (mips_relax
.sequence
!= 2 && !mips_opts
.noreorder
)
2315 /* Filling the branch delay slot is more complex. We try to
2316 switch the branch with the previous instruction, which we can
2317 do if the previous instruction does not set up a condition
2318 that the branch tests and if the branch is not itself the
2319 target of any branch. */
2320 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2321 || (pinfo
& INSN_COND_BRANCH_DELAY
))
2323 if (mips_optimize
< 2
2324 /* If we have seen .set volatile or .set nomove, don't
2326 || mips_opts
.nomove
!= 0
2327 /* If we had to emit any NOP instructions, then we
2328 already know we can not swap. */
2330 /* If we don't even know the previous insn, we can not
2332 || ! prev_insn_valid
2333 /* If the previous insn is already in a branch delay
2334 slot, then we can not swap. */
2335 || prev_insn_is_delay_slot
2336 /* If the previous previous insn was in a .set
2337 noreorder, we can't swap. Actually, the MIPS
2338 assembler will swap in this situation. However, gcc
2339 configured -with-gnu-as will generate code like
2345 in which we can not swap the bne and INSN. If gcc is
2346 not configured -with-gnu-as, it does not output the
2347 .set pseudo-ops. We don't have to check
2348 prev_insn_unreordered, because prev_insn_valid will
2349 be 0 in that case. We don't want to use
2350 prev_prev_insn_valid, because we do want to be able
2351 to swap at the start of a function. */
2352 || prev_prev_insn_unreordered
2353 /* If the branch is itself the target of a branch, we
2354 can not swap. We cheat on this; all we check for is
2355 whether there is a label on this instruction. If
2356 there are any branches to anything other than a
2357 label, users must use .set noreorder. */
2358 || insn_labels
!= NULL
2359 /* If the previous instruction is in a variant frag
2360 other than this branch's one, we cannot do the swap.
2361 This does not apply to the mips16, which uses variant
2362 frags for different purposes. */
2363 || (! mips_opts
.mips16
2364 && prev_insn_frag_type
== rs_machine_dependent
)
2365 /* If the branch reads the condition codes, we don't
2366 even try to swap, because in the sequence
2371 we can not swap, and I don't feel like handling that
2373 || (! mips_opts
.mips16
2374 && (pinfo
& INSN_READ_COND_CODE
)
2375 && ! cop_interlocks
)
2376 /* We can not swap with an instruction that requires a
2377 delay slot, because the target of the branch might
2378 interfere with that instruction. */
2379 || (! mips_opts
.mips16
2381 /* Itbl support may require additional care here. */
2382 & (INSN_LOAD_COPROC_DELAY
2383 | INSN_COPROC_MOVE_DELAY
2384 | INSN_WRITE_COND_CODE
))
2385 && ! cop_interlocks
)
2386 || (! (hilo_interlocks
2387 || (mips_opts
.arch
== CPU_R3900
&& (pinfo
& INSN_MULT
)))
2391 || (! mips_opts
.mips16
2392 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
)
2393 && ! gpr_interlocks
)
2394 || (! mips_opts
.mips16
2395 /* Itbl support may require additional care here. */
2396 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
)
2397 && ! cop_mem_interlocks
)
2398 /* We can not swap with a branch instruction. */
2400 & (INSN_UNCOND_BRANCH_DELAY
2401 | INSN_COND_BRANCH_DELAY
2402 | INSN_COND_BRANCH_LIKELY
))
2403 /* We do not swap with a trap instruction, since it
2404 complicates trap handlers to have the trap
2405 instruction be in a delay slot. */
2406 || (prev_pinfo
& INSN_TRAP
)
2407 /* If the branch reads a register that the previous
2408 instruction sets, we can not swap. */
2409 || (! mips_opts
.mips16
2410 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2411 && insn_uses_reg (ip
,
2412 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2415 || (! mips_opts
.mips16
2416 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2417 && insn_uses_reg (ip
,
2418 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2421 || (mips_opts
.mips16
2422 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2423 && insn_uses_reg (ip
,
2424 ((prev_insn
.insn_opcode
2426 & MIPS16OP_MASK_RX
),
2428 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2429 && insn_uses_reg (ip
,
2430 ((prev_insn
.insn_opcode
2432 & MIPS16OP_MASK_RY
),
2434 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2435 && insn_uses_reg (ip
,
2436 ((prev_insn
.insn_opcode
2438 & MIPS16OP_MASK_RZ
),
2440 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2441 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2442 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2443 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2444 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2445 && insn_uses_reg (ip
,
2446 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2449 /* If the branch writes a register that the previous
2450 instruction sets, we can not swap (we know that
2451 branches write only to RD or to $31). */
2452 || (! mips_opts
.mips16
2453 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2454 && (((pinfo
& INSN_WRITE_GPR_D
)
2455 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2456 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2457 || ((pinfo
& INSN_WRITE_GPR_31
)
2458 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2461 || (! mips_opts
.mips16
2462 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2463 && (((pinfo
& INSN_WRITE_GPR_D
)
2464 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2465 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2466 || ((pinfo
& INSN_WRITE_GPR_31
)
2467 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2470 || (mips_opts
.mips16
2471 && (pinfo
& MIPS16_INSN_WRITE_31
)
2472 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2473 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2474 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2476 /* If the branch writes a register that the previous
2477 instruction reads, we can not swap (we know that
2478 branches only write to RD or to $31). */
2479 || (! mips_opts
.mips16
2480 && (pinfo
& INSN_WRITE_GPR_D
)
2481 && insn_uses_reg (&prev_insn
,
2482 ((ip
->insn_opcode
>> OP_SH_RD
)
2485 || (! mips_opts
.mips16
2486 && (pinfo
& INSN_WRITE_GPR_31
)
2487 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2488 || (mips_opts
.mips16
2489 && (pinfo
& MIPS16_INSN_WRITE_31
)
2490 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2491 /* If we are generating embedded PIC code, the branch
2492 might be expanded into a sequence which uses $at, so
2493 we can't swap with an instruction which reads it. */
2494 || (mips_pic
== EMBEDDED_PIC
2495 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2496 /* If the previous previous instruction has a load
2497 delay, and sets a register that the branch reads, we
2499 || (! mips_opts
.mips16
2500 /* Itbl support may require additional care here. */
2501 && (((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2502 && ! cop_interlocks
)
2503 || ((prev_prev_insn
.insn_mo
->pinfo
2504 & INSN_LOAD_MEMORY_DELAY
)
2505 && ! gpr_interlocks
))
2506 && insn_uses_reg (ip
,
2507 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2510 /* If one instruction sets a condition code and the
2511 other one uses a condition code, we can not swap. */
2512 || ((pinfo
& INSN_READ_COND_CODE
)
2513 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2514 || ((pinfo
& INSN_WRITE_COND_CODE
)
2515 && (prev_pinfo
& INSN_READ_COND_CODE
))
2516 /* If the previous instruction uses the PC, we can not
2518 || (mips_opts
.mips16
2519 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2520 /* If the previous instruction was extended, we can not
2522 || (mips_opts
.mips16
&& prev_insn_extended
)
2523 /* If the previous instruction had a fixup in mips16
2524 mode, we can not swap. This normally means that the
2525 previous instruction was a 4 byte branch anyhow. */
2526 || (mips_opts
.mips16
&& prev_insn_fixp
[0])
2527 /* If the previous instruction is a sync, sync.l, or
2528 sync.p, we can not swap. */
2529 || (prev_pinfo
& INSN_SYNC
))
2531 /* We could do even better for unconditional branches to
2532 portions of this object file; we could pick up the
2533 instruction at the destination, put it in the delay
2534 slot, and bump the destination address. */
2536 /* Update the previous insn information. */
2537 prev_prev_insn
= *ip
;
2538 prev_insn
.insn_mo
= &dummy_opcode
;
2542 /* It looks like we can actually do the swap. */
2543 if (! mips_opts
.mips16
)
2548 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2549 if (!relaxed_branch
)
2551 /* If this is not a relaxed branch, then just
2552 swap the instructions. */
2553 memcpy (temp
, prev_f
, 4);
2554 memcpy (prev_f
, f
, 4);
2555 memcpy (f
, temp
, 4);
2559 /* If this is a relaxed branch, then we move the
2560 instruction to be placed in the delay slot to
2561 the current frag, shrinking the fixed part of
2562 the originating frag. If the branch occupies
2563 the tail of the latter, we move it backwards,
2564 into the space freed by the moved instruction. */
2566 memcpy (f
, prev_f
, 4);
2567 prev_insn_frag
->fr_fix
-= 4;
2568 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2569 memmove (prev_f
, prev_f
+ 4, prev_insn_frag
->fr_var
);
2572 if (prev_insn_fixp
[0])
2574 prev_insn_fixp
[0]->fx_frag
= frag_now
;
2575 prev_insn_fixp
[0]->fx_where
= f
- frag_now
->fr_literal
;
2577 if (prev_insn_fixp
[1])
2579 prev_insn_fixp
[1]->fx_frag
= frag_now
;
2580 prev_insn_fixp
[1]->fx_where
= f
- frag_now
->fr_literal
;
2582 if (prev_insn_fixp
[2])
2584 prev_insn_fixp
[2]->fx_frag
= frag_now
;
2585 prev_insn_fixp
[2]->fx_where
= f
- frag_now
->fr_literal
;
2587 if (prev_insn_fixp
[0] && HAVE_NEWABI
2588 && prev_insn_frag
!= frag_now
2589 && (prev_insn_fixp
[0]->fx_r_type
2590 == BFD_RELOC_MIPS_GOT_DISP
2591 || (prev_insn_fixp
[0]->fx_r_type
2592 == BFD_RELOC_MIPS_CALL16
)))
2594 /* To avoid confusion in tc_gen_reloc, we must
2595 ensure that this does not become a variant
2597 force_new_frag
= TRUE
;
2600 if (!relaxed_branch
)
2604 fixp
[0]->fx_frag
= prev_insn_frag
;
2605 fixp
[0]->fx_where
= prev_insn_where
;
2609 fixp
[1]->fx_frag
= prev_insn_frag
;
2610 fixp
[1]->fx_where
= prev_insn_where
;
2614 fixp
[2]->fx_frag
= prev_insn_frag
;
2615 fixp
[2]->fx_where
= prev_insn_where
;
2618 else if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
2621 fixp
[0]->fx_where
-= 4;
2623 fixp
[1]->fx_where
-= 4;
2625 fixp
[2]->fx_where
-= 4;
2633 assert (prev_insn_fixp
[0] == NULL
);
2634 assert (prev_insn_fixp
[1] == NULL
);
2635 assert (prev_insn_fixp
[2] == NULL
);
2636 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2637 memcpy (temp
, prev_f
, 2);
2638 memcpy (prev_f
, f
, 2);
2639 if (*reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2641 assert (*reloc_type
== BFD_RELOC_UNUSED
);
2642 memcpy (f
, temp
, 2);
2646 memcpy (f
, f
+ 2, 2);
2647 memcpy (f
+ 2, temp
, 2);
2651 fixp
[0]->fx_frag
= prev_insn_frag
;
2652 fixp
[0]->fx_where
= prev_insn_where
;
2656 fixp
[1]->fx_frag
= prev_insn_frag
;
2657 fixp
[1]->fx_where
= prev_insn_where
;
2661 fixp
[2]->fx_frag
= prev_insn_frag
;
2662 fixp
[2]->fx_where
= prev_insn_where
;
2666 /* Update the previous insn information; leave prev_insn
2668 prev_prev_insn
= *ip
;
2670 prev_insn_is_delay_slot
= 1;
2672 /* If that was an unconditional branch, forget the previous
2673 insn information. */
2674 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2676 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2677 prev_insn
.insn_mo
= &dummy_opcode
;
2680 prev_insn_fixp
[0] = NULL
;
2681 prev_insn_fixp
[1] = NULL
;
2682 prev_insn_fixp
[2] = NULL
;
2683 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2684 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2685 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2686 prev_insn_extended
= 0;
2688 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2690 /* We don't yet optimize a branch likely. What we should do
2691 is look at the target, copy the instruction found there
2692 into the delay slot, and increment the branch to jump to
2693 the next instruction. */
2695 /* Update the previous insn information. */
2696 prev_prev_insn
= *ip
;
2697 prev_insn
.insn_mo
= &dummy_opcode
;
2698 prev_insn_fixp
[0] = NULL
;
2699 prev_insn_fixp
[1] = NULL
;
2700 prev_insn_fixp
[2] = NULL
;
2701 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2702 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2703 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2704 prev_insn_extended
= 0;
2708 /* Update the previous insn information. */
2710 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2712 prev_prev_insn
= prev_insn
;
2715 /* Any time we see a branch, we always fill the delay slot
2716 immediately; since this insn is not a branch, we know it
2717 is not in a delay slot. */
2718 prev_insn_is_delay_slot
= 0;
2720 prev_insn_fixp
[0] = fixp
[0];
2721 prev_insn_fixp
[1] = fixp
[1];
2722 prev_insn_fixp
[2] = fixp
[2];
2723 prev_insn_reloc_type
[0] = reloc_type
[0];
2724 prev_insn_reloc_type
[1] = reloc_type
[1];
2725 prev_insn_reloc_type
[2] = reloc_type
[2];
2726 if (mips_opts
.mips16
)
2727 prev_insn_extended
= (ip
->use_extend
2728 || *reloc_type
> BFD_RELOC_UNUSED
);
2731 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2732 prev_insn_unreordered
= 0;
2733 prev_insn_frag
= frag_now
;
2734 prev_insn_where
= f
- frag_now
->fr_literal
;
2735 prev_insn_valid
= 1;
2737 else if (mips_relax
.sequence
!= 2)
2739 /* We need to record a bit of information even when we are not
2740 reordering, in order to determine the base address for mips16
2741 PC relative relocs. */
2742 prev_prev_insn
= prev_insn
;
2744 prev_insn_reloc_type
[0] = reloc_type
[0];
2745 prev_insn_reloc_type
[1] = reloc_type
[1];
2746 prev_insn_reloc_type
[2] = reloc_type
[2];
2747 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2748 prev_insn_unreordered
= 1;
2751 /* We just output an insn, so the next one doesn't have a label. */
2752 mips_clear_insn_labels ();
2755 /* This function forgets that there was any previous instruction or
2756 label. If PRESERVE is non-zero, it remembers enough information to
2757 know whether nops are needed before a noreorder section. */
2760 mips_no_prev_insn (int preserve
)
2764 prev_insn
.insn_mo
= &dummy_opcode
;
2765 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2766 prev_nop_frag
= NULL
;
2767 prev_nop_frag_holds
= 0;
2768 prev_nop_frag_required
= 0;
2769 prev_nop_frag_since
= 0;
2771 prev_insn_valid
= 0;
2772 prev_insn_is_delay_slot
= 0;
2773 prev_insn_unreordered
= 0;
2774 prev_insn_extended
= 0;
2775 prev_insn_reloc_type
[0] = BFD_RELOC_UNUSED
;
2776 prev_insn_reloc_type
[1] = BFD_RELOC_UNUSED
;
2777 prev_insn_reloc_type
[2] = BFD_RELOC_UNUSED
;
2778 prev_prev_insn_unreordered
= 0;
2779 mips_clear_insn_labels ();
2782 /* This function must be called whenever we turn on noreorder or emit
2783 something other than instructions. It inserts any NOPS which might
2784 be needed by the previous instruction, and clears the information
2785 kept for the previous instructions. The INSNS parameter is true if
2786 instructions are to follow. */
2789 mips_emit_delays (bfd_boolean insns
)
2791 if (! mips_opts
.noreorder
)
2796 if ((! mips_opts
.mips16
2797 && ((prev_insn
.insn_mo
->pinfo
2798 & (INSN_LOAD_COPROC_DELAY
2799 | INSN_COPROC_MOVE_DELAY
2800 | INSN_WRITE_COND_CODE
))
2801 && ! cop_interlocks
))
2802 || (! hilo_interlocks
2803 && (prev_insn
.insn_mo
->pinfo
2806 || (! mips_opts
.mips16
2807 && (prev_insn
.insn_mo
->pinfo
& INSN_LOAD_MEMORY_DELAY
)
2808 && ! gpr_interlocks
)
2809 || (! mips_opts
.mips16
2810 && (prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MEMORY_DELAY
)
2811 && ! cop_mem_interlocks
))
2813 /* Itbl support may require additional care here. */
2815 if ((! mips_opts
.mips16
2816 && ((prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2817 && ! cop_interlocks
))
2818 || (! hilo_interlocks
2819 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2820 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2823 if (prev_insn_unreordered
)
2826 else if ((! mips_opts
.mips16
2827 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
2828 && ! cop_interlocks
))
2829 || (! hilo_interlocks
2830 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2831 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2833 /* Itbl support may require additional care here. */
2834 if (! prev_prev_insn_unreordered
)
2838 if (mips_fix_vr4120
&& prev_insn
.insn_mo
->name
)
2841 const char *pn
= prev_insn
.insn_mo
->name
;
2842 if (strncmp(pn
, "macc", 4) == 0
2843 || strncmp(pn
, "dmacc", 5) == 0
2844 || strncmp(pn
, "dmult", 5) == 0)
2848 if (nops
< min_nops
)
2854 struct insn_label_list
*l
;
2858 /* Record the frag which holds the nop instructions, so
2859 that we can remove them if we don't need them. */
2860 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2861 prev_nop_frag
= frag_now
;
2862 prev_nop_frag_holds
= nops
;
2863 prev_nop_frag_required
= 0;
2864 prev_nop_frag_since
= 0;
2867 for (; nops
> 0; --nops
)
2872 /* Move on to a new frag, so that it is safe to simply
2873 decrease the size of prev_nop_frag. */
2874 frag_wane (frag_now
);
2878 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2882 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2883 symbol_set_frag (l
->label
, frag_now
);
2884 val
= (valueT
) frag_now_fix ();
2885 /* mips16 text labels are stored as odd. */
2886 if (mips_opts
.mips16
)
2888 S_SET_VALUE (l
->label
, val
);
2893 /* Mark instruction labels in mips16 mode. */
2895 mips16_mark_labels ();
2897 mips_no_prev_insn (insns
);
2900 /* Set up global variables for the start of a new macro. */
2905 memset (&mips_macro_warning
.sizes
, 0, sizeof (mips_macro_warning
.sizes
));
2906 mips_macro_warning
.delay_slot_p
= (mips_opts
.noreorder
2907 && (prev_insn
.insn_mo
->pinfo
2908 & (INSN_UNCOND_BRANCH_DELAY
2909 | INSN_COND_BRANCH_DELAY
2910 | INSN_COND_BRANCH_LIKELY
)) != 0);
2913 /* Given that a macro is longer than 4 bytes, return the appropriate warning
2914 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2915 RELAX_DELAY_SLOT and RELAX_NOMACRO. */
2918 macro_warning (relax_substateT subtype
)
2920 if (subtype
& RELAX_DELAY_SLOT
)
2921 return _("Macro instruction expanded into multiple instructions"
2922 " in a branch delay slot");
2923 else if (subtype
& RELAX_NOMACRO
)
2924 return _("Macro instruction expanded into multiple instructions");
2929 /* Finish up a macro. Emit warnings as appropriate. */
2934 if (mips_macro_warning
.sizes
[0] > 4 || mips_macro_warning
.sizes
[1] > 4)
2936 relax_substateT subtype
;
2938 /* Set up the relaxation warning flags. */
2940 if (mips_macro_warning
.sizes
[1] > mips_macro_warning
.sizes
[0])
2941 subtype
|= RELAX_SECOND_LONGER
;
2942 if (mips_opts
.warn_about_macros
)
2943 subtype
|= RELAX_NOMACRO
;
2944 if (mips_macro_warning
.delay_slot_p
)
2945 subtype
|= RELAX_DELAY_SLOT
;
2947 if (mips_macro_warning
.sizes
[0] > 4 && mips_macro_warning
.sizes
[1] > 4)
2949 /* Either the macro has a single implementation or both
2950 implementations are longer than 4 bytes. Emit the
2952 const char *msg
= macro_warning (subtype
);
2958 /* One implementation might need a warning but the other
2959 definitely doesn't. */
2960 mips_macro_warning
.first_frag
->fr_subtype
|= subtype
;
2965 /* Build an instruction created by a macro expansion. This is passed
2966 a pointer to the count of instructions created so far, an
2967 expression, the name of the instruction to build, an operand format
2968 string, and corresponding arguments. */
2971 macro_build (expressionS
*ep
, const char *name
, const char *fmt
, ...)
2973 struct mips_cl_insn insn
;
2974 bfd_reloc_code_real_type r
[3];
2977 va_start (args
, fmt
);
2979 if (mips_opts
.mips16
)
2981 mips16_macro_build (ep
, name
, fmt
, args
);
2986 r
[0] = BFD_RELOC_UNUSED
;
2987 r
[1] = BFD_RELOC_UNUSED
;
2988 r
[2] = BFD_RELOC_UNUSED
;
2989 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2990 assert (insn
.insn_mo
);
2991 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2993 /* Search until we get a match for NAME. */
2996 /* It is assumed here that macros will never generate
2997 MDMX or MIPS-3D instructions. */
2998 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2999 && insn
.insn_mo
->pinfo
!= INSN_MACRO
3000 && OPCODE_IS_MEMBER (insn
.insn_mo
,
3002 | (file_ase_mips16
? INSN_MIPS16
: 0)),
3004 && (mips_opts
.arch
!= CPU_R4650
|| (insn
.insn_mo
->pinfo
& FP_D
) == 0))
3008 assert (insn
.insn_mo
->name
);
3009 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3012 insn
.insn_opcode
= insn
.insn_mo
->match
;
3030 insn
.insn_opcode
|= (va_arg (args
, int)
3031 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
3036 /* Note that in the macro case, these arguments are already
3037 in MSB form. (When handling the instruction in the
3038 non-macro case, these arguments are sizes from which
3039 MSB values must be calculated.) */
3040 insn
.insn_opcode
|= (va_arg (args
, int)
3041 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
3047 /* Note that in the macro case, these arguments are already
3048 in MSBD form. (When handling the instruction in the
3049 non-macro case, these arguments are sizes from which
3050 MSBD values must be calculated.) */
3051 insn
.insn_opcode
|= (va_arg (args
, int)
3052 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
3063 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RT
;
3067 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE
;
3072 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FT
;
3078 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RD
;
3083 int tmp
= va_arg (args
, int);
3085 insn
.insn_opcode
|= tmp
<< OP_SH_RT
;
3086 insn
.insn_opcode
|= tmp
<< OP_SH_RD
;
3092 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FS
;
3099 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_SHAMT
;
3103 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_FD
;
3107 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE20
;
3111 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE19
;
3115 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_CODE2
;
3122 insn
.insn_opcode
|= va_arg (args
, int) << OP_SH_RS
;
3128 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3129 assert (*r
== BFD_RELOC_GPREL16
3130 || *r
== BFD_RELOC_MIPS_LITERAL
3131 || *r
== BFD_RELOC_MIPS_HIGHER
3132 || *r
== BFD_RELOC_HI16_S
3133 || *r
== BFD_RELOC_LO16
3134 || *r
== BFD_RELOC_MIPS_GOT16
3135 || *r
== BFD_RELOC_MIPS_CALL16
3136 || *r
== BFD_RELOC_MIPS_GOT_DISP
3137 || *r
== BFD_RELOC_MIPS_GOT_PAGE
3138 || *r
== BFD_RELOC_MIPS_GOT_OFST
3139 || *r
== BFD_RELOC_MIPS_GOT_LO16
3140 || *r
== BFD_RELOC_MIPS_CALL_LO16
3141 || (ep
->X_op
== O_subtract
3142 && *r
== BFD_RELOC_PCREL_LO16
));
3146 *r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
3148 && (ep
->X_op
== O_constant
3149 || (ep
->X_op
== O_symbol
3150 && (*r
== BFD_RELOC_MIPS_HIGHEST
3151 || *r
== BFD_RELOC_HI16_S
3152 || *r
== BFD_RELOC_HI16
3153 || *r
== BFD_RELOC_GPREL16
3154 || *r
== BFD_RELOC_MIPS_GOT_HI16
3155 || *r
== BFD_RELOC_MIPS_CALL_HI16
))
3156 || (ep
->X_op
== O_subtract
3157 && *r
== BFD_RELOC_PCREL_HI16_S
)));
3161 assert (ep
!= NULL
);
3163 * This allows macro() to pass an immediate expression for
3164 * creating short branches without creating a symbol.
3165 * Note that the expression still might come from the assembly
3166 * input, in which case the value is not checked for range nor
3167 * is a relocation entry generated (yuck).
3169 if (ep
->X_op
== O_constant
)
3171 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
3175 *r
= BFD_RELOC_16_PCREL_S2
;
3179 assert (ep
!= NULL
);
3180 *r
= BFD_RELOC_MIPS_JMP
;
3184 insn
.insn_opcode
|= va_arg (args
, unsigned long);
3193 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3195 append_insn (&insn
, ep
, r
);
3199 mips16_macro_build (expressionS
*ep
, const char *name
, const char *fmt
,
3202 struct mips_cl_insn insn
;
3203 bfd_reloc_code_real_type r
[3]
3204 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3206 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
3207 assert (insn
.insn_mo
);
3208 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3210 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
3211 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
3214 assert (insn
.insn_mo
->name
);
3215 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3218 insn
.insn_opcode
= insn
.insn_mo
->match
;
3219 insn
.use_extend
= FALSE
;
3238 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
3243 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
3247 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
3251 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
3261 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
3268 regno
= va_arg (args
, int);
3269 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
3270 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
3291 assert (ep
!= NULL
);
3293 if (ep
->X_op
!= O_constant
)
3294 *r
= (int) BFD_RELOC_UNUSED
+ c
;
3297 mips16_immed (NULL
, 0, c
, ep
->X_add_number
, FALSE
, FALSE
,
3298 FALSE
, &insn
.insn_opcode
, &insn
.use_extend
,
3301 *r
= BFD_RELOC_UNUSED
;
3307 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
3314 assert (*r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
3316 append_insn (&insn
, ep
, r
);
3320 * Generate a "jalr" instruction with a relocation hint to the called
3321 * function. This occurs in NewABI PIC code.
3324 macro_build_jalr (expressionS
*ep
)
3333 macro_build (NULL
, "jalr", "d,s", RA
, PIC_CALL_REG
);
3335 fix_new_exp (frag_now
, f
- frag_now
->fr_literal
,
3336 4, ep
, FALSE
, BFD_RELOC_MIPS_JALR
);
3340 * Generate a "lui" instruction.
3343 macro_build_lui (expressionS
*ep
, int regnum
)
3345 expressionS high_expr
;
3346 struct mips_cl_insn insn
;
3347 bfd_reloc_code_real_type r
[3]
3348 = {BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
, BFD_RELOC_UNUSED
};
3349 const char *name
= "lui";
3350 const char *fmt
= "t,u";
3352 assert (! mips_opts
.mips16
);
3356 if (high_expr
.X_op
== O_constant
)
3358 /* we can compute the instruction now without a relocation entry */
3359 high_expr
.X_add_number
= ((high_expr
.X_add_number
+ 0x8000)
3361 *r
= BFD_RELOC_UNUSED
;
3365 assert (ep
->X_op
== O_symbol
);
3366 /* _gp_disp is a special case, used from s_cpload. */
3367 assert (mips_pic
== NO_PIC
3369 && strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0));
3370 *r
= BFD_RELOC_HI16_S
;
3373 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
3374 assert (insn
.insn_mo
);
3375 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
3376 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
3378 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
3379 if (*r
== BFD_RELOC_UNUSED
)
3381 insn
.insn_opcode
|= high_expr
.X_add_number
;
3382 append_insn (&insn
, NULL
, r
);
3385 append_insn (&insn
, &high_expr
, r
);
3388 /* Generate a sequence of instructions to do a load or store from a constant
3389 offset off of a base register (breg) into/from a target register (treg),
3390 using AT if necessary. */
3392 macro_build_ldst_constoffset (expressionS
*ep
, const char *op
,
3393 int treg
, int breg
, int dbl
)
3395 assert (ep
->X_op
== O_constant
);
3397 /* Sign-extending 32-bit constants makes their handling easier. */
3398 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3399 == ~((bfd_vma
) 0x7fffffff)))
3401 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3402 as_bad (_("constant too large"));
3404 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3408 /* Right now, this routine can only handle signed 32-bit constants. */
3409 if (! IS_SEXT_32BIT_NUM(ep
->X_add_number
+ 0x8000))
3410 as_warn (_("operand overflow"));
3412 if (IS_SEXT_16BIT_NUM(ep
->X_add_number
))
3414 /* Signed 16-bit offset will fit in the op. Easy! */
3415 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
3419 /* 32-bit offset, need multiple instructions and AT, like:
3420 lui $tempreg,const_hi (BFD_RELOC_HI16_S)
3421 addu $tempreg,$tempreg,$breg
3422 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3423 to handle the complete offset. */
3424 macro_build_lui (ep
, AT
);
3425 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
3426 macro_build (ep
, op
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
3429 as_warn (_("Macro used $at after \".set noat\""));
3434 * Generates code to set the $at register to true (one)
3435 * if reg is less than the immediate expression.
3438 set_at (int reg
, int unsignedp
)
3440 if (imm_expr
.X_op
== O_constant
3441 && imm_expr
.X_add_number
>= -0x8000
3442 && imm_expr
.X_add_number
< 0x8000)
3443 macro_build (&imm_expr
, unsignedp
? "sltiu" : "slti", "t,r,j",
3444 AT
, reg
, BFD_RELOC_LO16
);
3447 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
3448 macro_build (NULL
, unsignedp
? "sltu" : "slt", "d,v,t", AT
, reg
, AT
);
3453 normalize_constant_expr (expressionS
*ex
)
3455 if (ex
->X_op
== O_constant
&& HAVE_32BIT_GPRS
)
3456 ex
->X_add_number
= (((ex
->X_add_number
& 0xffffffff) ^ 0x80000000)
3460 /* Warn if an expression is not a constant. */
3463 check_absolute_expr (struct mips_cl_insn
*ip
, expressionS
*ex
)
3465 if (ex
->X_op
== O_big
)
3466 as_bad (_("unsupported large constant"));
3467 else if (ex
->X_op
!= O_constant
)
3468 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
3470 normalize_constant_expr (ex
);
3473 /* Count the leading zeroes by performing a binary chop. This is a
3474 bulky bit of source, but performance is a LOT better for the
3475 majority of values than a simple loop to count the bits:
3476 for (lcnt = 0; (lcnt < 32); lcnt++)
3477 if ((v) & (1 << (31 - lcnt)))
3479 However it is not code size friendly, and the gain will drop a bit
3480 on certain cached systems.
3482 #define COUNT_TOP_ZEROES(v) \
3483 (((v) & ~0xffff) == 0 \
3484 ? ((v) & ~0xff) == 0 \
3485 ? ((v) & ~0xf) == 0 \
3486 ? ((v) & ~0x3) == 0 \
3487 ? ((v) & ~0x1) == 0 \
3492 : ((v) & ~0x7) == 0 \
3495 : ((v) & ~0x3f) == 0 \
3496 ? ((v) & ~0x1f) == 0 \
3499 : ((v) & ~0x7f) == 0 \
3502 : ((v) & ~0xfff) == 0 \
3503 ? ((v) & ~0x3ff) == 0 \
3504 ? ((v) & ~0x1ff) == 0 \
3507 : ((v) & ~0x7ff) == 0 \
3510 : ((v) & ~0x3fff) == 0 \
3511 ? ((v) & ~0x1fff) == 0 \
3514 : ((v) & ~0x7fff) == 0 \
3517 : ((v) & ~0xffffff) == 0 \
3518 ? ((v) & ~0xfffff) == 0 \
3519 ? ((v) & ~0x3ffff) == 0 \
3520 ? ((v) & ~0x1ffff) == 0 \
3523 : ((v) & ~0x7ffff) == 0 \
3526 : ((v) & ~0x3fffff) == 0 \
3527 ? ((v) & ~0x1fffff) == 0 \
3530 : ((v) & ~0x7fffff) == 0 \
3533 : ((v) & ~0xfffffff) == 0 \
3534 ? ((v) & ~0x3ffffff) == 0 \
3535 ? ((v) & ~0x1ffffff) == 0 \
3538 : ((v) & ~0x7ffffff) == 0 \
3541 : ((v) & ~0x3fffffff) == 0 \
3542 ? ((v) & ~0x1fffffff) == 0 \
3545 : ((v) & ~0x7fffffff) == 0 \
3550 * This routine generates the least number of instructions necessary to load
3551 * an absolute expression value into a register.
3554 load_register (int reg
, expressionS
*ep
, int dbl
)
3557 expressionS hi32
, lo32
;
3559 if (ep
->X_op
!= O_big
)
3561 assert (ep
->X_op
== O_constant
);
3563 /* Sign-extending 32-bit constants makes their handling easier. */
3564 if (! dbl
&& ! ((ep
->X_add_number
& ~((bfd_vma
) 0x7fffffff))
3565 == ~((bfd_vma
) 0x7fffffff)))
3567 if (ep
->X_add_number
& ~((bfd_vma
) 0xffffffff))
3568 as_bad (_("constant too large"));
3570 ep
->X_add_number
= (((ep
->X_add_number
& 0xffffffff) ^ 0x80000000)
3574 if (IS_SEXT_16BIT_NUM (ep
->X_add_number
))
3576 /* We can handle 16 bit signed values with an addiu to
3577 $zero. No need to ever use daddiu here, since $zero and
3578 the result are always correct in 32 bit mode. */
3579 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3582 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3584 /* We can handle 16 bit unsigned values with an ori to
3586 macro_build (ep
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3589 else if ((IS_SEXT_32BIT_NUM (ep
->X_add_number
)))
3591 /* 32 bit values require an lui. */
3592 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3593 if ((ep
->X_add_number
& 0xffff) != 0)
3594 macro_build (ep
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3599 /* The value is larger than 32 bits. */
3601 if (HAVE_32BIT_GPRS
)
3603 as_bad (_("Number (0x%lx) larger than 32 bits"),
3604 (unsigned long) ep
->X_add_number
);
3605 macro_build (ep
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3609 if (ep
->X_op
!= O_big
)
3612 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3613 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3614 hi32
.X_add_number
&= 0xffffffff;
3616 lo32
.X_add_number
&= 0xffffffff;
3620 assert (ep
->X_add_number
> 2);
3621 if (ep
->X_add_number
== 3)
3622 generic_bignum
[3] = 0;
3623 else if (ep
->X_add_number
> 4)
3624 as_bad (_("Number larger than 64 bits"));
3625 lo32
.X_op
= O_constant
;
3626 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3627 hi32
.X_op
= O_constant
;
3628 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3631 if (hi32
.X_add_number
== 0)
3636 unsigned long hi
, lo
;
3638 if (hi32
.X_add_number
== (offsetT
) 0xffffffff)
3640 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3642 macro_build (&lo32
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3645 if (lo32
.X_add_number
& 0x80000000)
3647 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3648 if (lo32
.X_add_number
& 0xffff)
3649 macro_build (&lo32
, "ori", "t,r,i", reg
, reg
, BFD_RELOC_LO16
);
3654 /* Check for 16bit shifted constant. We know that hi32 is
3655 non-zero, so start the mask on the first bit of the hi32
3660 unsigned long himask
, lomask
;
3664 himask
= 0xffff >> (32 - shift
);
3665 lomask
= (0xffff << shift
) & 0xffffffff;
3669 himask
= 0xffff << (shift
- 32);
3672 if ((hi32
.X_add_number
& ~(offsetT
) himask
) == 0
3673 && (lo32
.X_add_number
& ~(offsetT
) lomask
) == 0)
3677 tmp
.X_op
= O_constant
;
3679 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3680 | (lo32
.X_add_number
>> shift
));
3682 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3683 macro_build (&tmp
, "ori", "t,r,i", reg
, 0, BFD_RELOC_LO16
);
3684 macro_build (NULL
, (shift
>= 32) ? "dsll32" : "dsll", "d,w,<",
3685 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3690 while (shift
<= (64 - 16));
3692 /* Find the bit number of the lowest one bit, and store the
3693 shifted value in hi/lo. */
3694 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3695 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3699 while ((lo
& 1) == 0)
3704 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3710 while ((hi
& 1) == 0)
3719 /* Optimize if the shifted value is a (power of 2) - 1. */
3720 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3721 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3723 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3728 /* This instruction will set the register to be all
3730 tmp
.X_op
= O_constant
;
3731 tmp
.X_add_number
= (offsetT
) -1;
3732 macro_build (&tmp
, "addiu", "t,r,j", reg
, 0, BFD_RELOC_LO16
);
3736 macro_build (NULL
, (bit
>= 32) ? "dsll32" : "dsll", "d,w,<",
3737 reg
, reg
, (bit
>= 32) ? bit
- 32 : bit
);
3739 macro_build (NULL
, (shift
>= 32) ? "dsrl32" : "dsrl", "d,w,<",
3740 reg
, reg
, (shift
>= 32) ? shift
- 32 : shift
);
3745 /* Sign extend hi32 before calling load_register, because we can
3746 generally get better code when we load a sign extended value. */
3747 if ((hi32
.X_add_number
& 0x80000000) != 0)
3748 hi32
.X_add_number
|= ~(offsetT
) 0xffffffff;
3749 load_register (reg
, &hi32
, 0);
3752 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3756 macro_build (NULL
, "dsll32", "d,w,<", reg
, freg
, 0);
3764 if ((freg
== 0) && (lo32
.X_add_number
== (offsetT
) 0xffffffff))
3766 macro_build (&lo32
, "lui", "t,u", reg
, BFD_RELOC_HI16
);
3767 macro_build (NULL
, "dsrl32", "d,w,<", reg
, reg
, 0);
3773 macro_build (NULL
, "dsll", "d,w,<", reg
, freg
, 16);
3777 mid16
.X_add_number
>>= 16;
3778 macro_build (&mid16
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3779 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3782 if ((lo32
.X_add_number
& 0xffff) != 0)
3783 macro_build (&lo32
, "ori", "t,r,i", reg
, freg
, BFD_RELOC_LO16
);
3786 /* Load an address into a register. */
3789 load_address (int reg
, expressionS
*ep
, int *used_at
)
3791 if (ep
->X_op
!= O_constant
3792 && ep
->X_op
!= O_symbol
)
3794 as_bad (_("expression too complex"));
3795 ep
->X_op
= O_constant
;
3798 if (ep
->X_op
== O_constant
)
3800 load_register (reg
, ep
, HAVE_64BIT_ADDRESSES
);
3804 if (mips_pic
== NO_PIC
)
3806 /* If this is a reference to a GP relative symbol, we want
3807 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
3809 lui $reg,<sym> (BFD_RELOC_HI16_S)
3810 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3811 If we have an addend, we always use the latter form.
3813 With 64bit address space and a usable $at we want
3814 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3815 lui $at,<sym> (BFD_RELOC_HI16_S)
3816 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3817 daddiu $at,<sym> (BFD_RELOC_LO16)
3821 If $at is already in use, we use a path which is suboptimal
3822 on superscalar processors.
3823 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3824 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3826 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3828 daddiu $reg,<sym> (BFD_RELOC_LO16)
3830 if (HAVE_64BIT_ADDRESSES
)
3832 /* ??? We don't provide a GP-relative alternative for these macros.
3833 It used not to be possible with the original relaxation code,
3834 but it could be done now. */
3836 if (*used_at
== 0 && ! mips_opts
.noat
)
3838 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3839 macro_build (ep
, "lui", "t,u", AT
, BFD_RELOC_HI16_S
);
3840 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3841 BFD_RELOC_MIPS_HIGHER
);
3842 macro_build (ep
, "daddiu", "t,r,j", AT
, AT
, BFD_RELOC_LO16
);
3843 macro_build (NULL
, "dsll32", "d,w,<", reg
, reg
, 0);
3844 macro_build (NULL
, "daddu", "d,v,t", reg
, reg
, AT
);
3849 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_HIGHEST
);
3850 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
,
3851 BFD_RELOC_MIPS_HIGHER
);
3852 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3853 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_HI16_S
);
3854 macro_build (NULL
, "dsll", "d,w,<", reg
, reg
, 16);
3855 macro_build (ep
, "daddiu", "t,r,j", reg
, reg
, BFD_RELOC_LO16
);
3860 if ((valueT
) ep
->X_add_number
<= MAX_GPREL_OFFSET
3861 && ! nopic_need_relax (ep
->X_add_symbol
, 1))
3863 relax_start (ep
->X_add_symbol
);
3864 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
,
3865 mips_gp_register
, BFD_RELOC_GPREL16
);
3868 macro_build_lui (ep
, reg
);
3869 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
3870 reg
, reg
, BFD_RELOC_LO16
);
3871 if (mips_relax
.sequence
)
3875 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3879 /* If this is a reference to an external symbol, we want
3880 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3882 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3884 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3885 If there is a constant, it must be added in after.
3887 If we have NewABI, we want
3888 lw $reg,<sym+cst>($gp) (BFD_RELOC_MIPS_GOT_DISP)
3889 unless we're referencing a global symbol with a non-zero
3890 offset, in which case cst must be added separately. */
3893 if (ep
->X_add_number
)
3895 ex
.X_add_number
= ep
->X_add_number
;
3896 ep
->X_add_number
= 0;
3897 relax_start (ep
->X_add_symbol
);
3898 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3899 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3900 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3901 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3902 ex
.X_op
= O_constant
;
3903 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3904 reg
, reg
, BFD_RELOC_LO16
);
3905 ep
->X_add_number
= ex
.X_add_number
;
3908 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3909 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
3910 if (mips_relax
.sequence
)
3915 ex
.X_add_number
= ep
->X_add_number
;
3916 ep
->X_add_number
= 0;
3917 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3918 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
3919 macro_build (NULL
, "nop", "");
3920 relax_start (ep
->X_add_symbol
);
3922 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3926 if (ex
.X_add_number
!= 0)
3928 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3929 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3930 ex
.X_op
= O_constant
;
3931 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j",
3932 reg
, reg
, BFD_RELOC_LO16
);
3936 else if (mips_pic
== SVR4_PIC
)
3940 /* This is the large GOT case. If this is a reference to an
3941 external symbol, we want
3942 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3944 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3946 Otherwise, for a reference to a local symbol in old ABI, we want
3947 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3949 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3950 If there is a constant, it must be added in after.
3952 In the NewABI, for local symbols, with or without offsets, we want:
3953 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
3954 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
3958 ex
.X_add_number
= ep
->X_add_number
;
3959 ep
->X_add_number
= 0;
3960 relax_start (ep
->X_add_symbol
);
3961 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3962 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3963 reg
, reg
, mips_gp_register
);
3964 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3965 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3966 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3967 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3968 else if (ex
.X_add_number
)
3970 ex
.X_op
= O_constant
;
3971 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3975 ep
->X_add_number
= ex
.X_add_number
;
3977 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
3978 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
3979 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
3980 BFD_RELOC_MIPS_GOT_OFST
);
3985 ex
.X_add_number
= ep
->X_add_number
;
3986 ep
->X_add_number
= 0;
3987 relax_start (ep
->X_add_symbol
);
3988 macro_build (ep
, "lui", "t,u", reg
, BFD_RELOC_MIPS_GOT_HI16
);
3989 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
3990 reg
, reg
, mips_gp_register
);
3991 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)",
3992 reg
, BFD_RELOC_MIPS_GOT_LO16
, reg
);
3994 if (reg_needs_delay (mips_gp_register
))
3996 /* We need a nop before loading from $gp. This special
3997 check is required because the lui which starts the main
3998 instruction stream does not refer to $gp, and so will not
3999 insert the nop which may be required. */
4000 macro_build (NULL
, "nop", "");
4002 macro_build (ep
, ADDRESS_LOAD_INSN
, "t,o(b)", reg
,
4003 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4004 macro_build (NULL
, "nop", "");
4005 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4009 if (ex
.X_add_number
!= 0)
4011 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
4012 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4013 ex
.X_op
= O_constant
;
4014 macro_build (&ex
, ADDRESS_ADDI_INSN
, "t,r,j", reg
, reg
,
4019 else if (mips_pic
== EMBEDDED_PIC
)
4022 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4024 macro_build (ep
, ADDRESS_ADDI_INSN
, "t,r,j",
4025 reg
, mips_gp_register
, BFD_RELOC_GPREL16
);
4031 /* Move the contents of register SOURCE into register DEST. */
4034 move_register (int dest
, int source
)
4036 macro_build (NULL
, HAVE_32BIT_GPRS
? "addu" : "daddu", "d,v,t",
4040 /* Emit an SVR4 PIC sequence to load address LOCAL into DEST, where
4041 LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
4042 The two alternatives are:
4044 Global symbol Local sybmol
4045 ------------- ------------
4046 lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
4048 addiu DEST,DEST,OFFSET addiu DEST,DEST,%lo(SYMBOL + OFFSET)
4050 load_got_offset emits the first instruction and add_got_offset
4051 emits the second for a 16-bit offset or add_got_offset_hilo emits
4052 a sequence to add a 32-bit offset using a scratch register. */
4055 load_got_offset (int dest
, expressionS
*local
)
4060 global
.X_add_number
= 0;
4062 relax_start (local
->X_add_symbol
);
4063 macro_build (&global
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4064 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4066 macro_build (local
, ADDRESS_LOAD_INSN
, "t,o(b)", dest
,
4067 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
4072 add_got_offset (int dest
, expressionS
*local
)
4076 global
.X_op
= O_constant
;
4077 global
.X_op_symbol
= NULL
;
4078 global
.X_add_symbol
= NULL
;
4079 global
.X_add_number
= local
->X_add_number
;
4081 relax_start (local
->X_add_symbol
);
4082 macro_build (&global
, ADDRESS_ADDI_INSN
, "t,r,j",
4083 dest
, dest
, BFD_RELOC_LO16
);
4085 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", dest
, dest
, BFD_RELOC_LO16
);
4090 add_got_offset_hilo (int dest
, expressionS
*local
, int tmp
)
4093 int hold_mips_optimize
;
4095 global
.X_op
= O_constant
;
4096 global
.X_op_symbol
= NULL
;
4097 global
.X_add_symbol
= NULL
;
4098 global
.X_add_number
= local
->X_add_number
;
4100 relax_start (local
->X_add_symbol
);
4101 load_register (tmp
, &global
, HAVE_64BIT_ADDRESSES
);
4103 /* Set mips_optimize around the lui instruction to avoid
4104 inserting an unnecessary nop after the lw. */
4105 hold_mips_optimize
= mips_optimize
;
4107 macro_build_lui (&global
, tmp
);
4108 mips_optimize
= hold_mips_optimize
;
4109 macro_build (local
, ADDRESS_ADDI_INSN
, "t,r,j", tmp
, tmp
, BFD_RELOC_LO16
);
4112 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dest
, dest
, tmp
);
4117 * This routine implements the seemingly endless macro or synthesized
4118 * instructions and addressing modes in the mips assembly language. Many
4119 * of these macros are simple and are similar to each other. These could
4120 * probably be handled by some kind of table or grammar approach instead of
4121 * this verbose method. Others are not simple macros but are more like
4122 * optimizing code generation.
4123 * One interesting optimization is when several store macros appear
4124 * consecutively that would load AT with the upper half of the same address.
4125 * The ensuing load upper instructions are ommited. This implies some kind
4126 * of global optimization. We currently only optimize within a single macro.
4127 * For many of the load and store macros if the address is specified as a
4128 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4129 * first load register 'at' with zero and use it as the base register. The
4130 * mips assembler simply uses register $zero. Just one tiny optimization
4134 macro (struct mips_cl_insn
*ip
)
4136 register int treg
, sreg
, dreg
, breg
;
4152 bfd_reloc_code_real_type r
;
4153 int hold_mips_optimize
;
4155 assert (! mips_opts
.mips16
);
4157 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
4158 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
4159 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
4160 mask
= ip
->insn_mo
->mask
;
4162 expr1
.X_op
= O_constant
;
4163 expr1
.X_op_symbol
= NULL
;
4164 expr1
.X_add_symbol
= NULL
;
4165 expr1
.X_add_number
= 1;
4177 mips_emit_delays (TRUE
);
4178 ++mips_opts
.noreorder
;
4179 mips_any_noreorder
= 1;
4181 expr1
.X_add_number
= 8;
4182 macro_build (&expr1
, "bgez", "s,p", sreg
);
4184 macro_build (NULL
, "nop", "", 0);
4186 move_register (dreg
, sreg
);
4187 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, 0, sreg
);
4189 --mips_opts
.noreorder
;
4210 if (imm_expr
.X_op
== O_constant
4211 && imm_expr
.X_add_number
>= -0x8000
4212 && imm_expr
.X_add_number
< 0x8000)
4214 macro_build (&imm_expr
, s
, "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4217 load_register (AT
, &imm_expr
, dbl
);
4218 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4237 if (imm_expr
.X_op
== O_constant
4238 && imm_expr
.X_add_number
>= 0
4239 && imm_expr
.X_add_number
< 0x10000)
4241 if (mask
!= M_NOR_I
)
4242 macro_build (&imm_expr
, s
, "t,r,i", treg
, sreg
, BFD_RELOC_LO16
);
4245 macro_build (&imm_expr
, "ori", "t,r,i",
4246 treg
, sreg
, BFD_RELOC_LO16
);
4247 macro_build (NULL
, "nor", "d,v,t", treg
, treg
, 0);
4252 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4253 macro_build (NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
4270 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4272 macro_build (&offset_expr
, s
, "s,t,p", sreg
, 0);
4275 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
4276 macro_build (&offset_expr
, s
, "s,t,p", sreg
, AT
);
4284 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4289 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", treg
);
4292 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4293 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4299 /* check for > max integer */
4300 maxnum
= 0x7fffffff;
4301 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4308 if (imm_expr
.X_op
== O_constant
4309 && imm_expr
.X_add_number
>= maxnum
4310 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4313 /* result is always false */
4315 macro_build (NULL
, "nop", "", 0);
4317 macro_build (&offset_expr
, "bnel", "s,t,p", 0, 0);
4320 if (imm_expr
.X_op
!= O_constant
)
4321 as_bad (_("Unsupported large constant"));
4322 ++imm_expr
.X_add_number
;
4326 if (mask
== M_BGEL_I
)
4328 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4330 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", sreg
);
4333 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4335 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4338 maxnum
= 0x7fffffff;
4339 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4346 maxnum
= - maxnum
- 1;
4347 if (imm_expr
.X_op
== O_constant
4348 && imm_expr
.X_add_number
<= maxnum
4349 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4352 /* result is always true */
4353 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
4354 macro_build (&offset_expr
, "b", "p");
4358 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4368 macro_build (&offset_expr
, likely
? "beql" : "beq",
4372 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4373 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4381 && imm_expr
.X_op
== O_constant
4382 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4384 if (imm_expr
.X_op
!= O_constant
)
4385 as_bad (_("Unsupported large constant"));
4386 ++imm_expr
.X_add_number
;
4390 if (mask
== M_BGEUL_I
)
4392 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4394 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4396 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4401 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4409 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", sreg
);
4414 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", treg
);
4417 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4418 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4426 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4432 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4433 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4441 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4446 macro_build (&offset_expr
, likely
? "bgezl" : "bgez", "s,p", treg
);
4449 macro_build (NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
4450 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4456 maxnum
= 0x7fffffff;
4457 if (HAVE_64BIT_GPRS
&& sizeof (maxnum
) > 4)
4464 if (imm_expr
.X_op
== O_constant
4465 && imm_expr
.X_add_number
>= maxnum
4466 && (HAVE_32BIT_GPRS
|| sizeof (maxnum
) > 4))
4468 if (imm_expr
.X_op
!= O_constant
)
4469 as_bad (_("Unsupported large constant"));
4470 ++imm_expr
.X_add_number
;
4474 if (mask
== M_BLTL_I
)
4476 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4478 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4481 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4483 macro_build (&offset_expr
, likely
? "blezl" : "blez", "s,p", sreg
);
4487 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4495 macro_build (&offset_expr
, likely
? "beql" : "beq",
4501 macro_build (NULL
, "sltu", "d,v,t", AT
, treg
, sreg
);
4502 macro_build (&offset_expr
, likely
? "beql" : "beq", "s,t,p", AT
, 0);
4510 && imm_expr
.X_op
== O_constant
4511 && imm_expr
.X_add_number
== (offsetT
) 0xffffffff))
4513 if (imm_expr
.X_op
!= O_constant
)
4514 as_bad (_("Unsupported large constant"));
4515 ++imm_expr
.X_add_number
;
4519 if (mask
== M_BLTUL_I
)
4521 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4523 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4525 macro_build (&offset_expr
, likely
? "beql" : "beq",
4530 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4538 macro_build (&offset_expr
, likely
? "bltzl" : "bltz", "s,p", sreg
);
4543 macro_build (&offset_expr
, likely
? "bgtzl" : "bgtz", "s,p", treg
);
4546 macro_build (NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
4547 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4557 macro_build (&offset_expr
, likely
? "bnel" : "bne",
4561 macro_build (NULL
, "sltu", "d,v,t", AT
, sreg
, treg
);
4562 macro_build (&offset_expr
, likely
? "bnel" : "bne", "s,t,p", AT
, 0);
4570 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4572 as_bad (_("Unsupported large constant"));
4577 pos
= (unsigned long) imm_expr
.X_add_number
;
4578 size
= (unsigned long) imm2_expr
.X_add_number
;
4583 as_bad (_("Improper position (%lu)"), pos
);
4586 if (size
== 0 || size
> 64
4587 || (pos
+ size
- 1) > 63)
4589 as_bad (_("Improper extract size (%lu, position %lu)"),
4594 if (size
<= 32 && pos
< 32)
4599 else if (size
<= 32)
4609 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
, size
- 1);
4618 if (imm_expr
.X_op
!= O_constant
|| imm2_expr
.X_op
!= O_constant
)
4620 as_bad (_("Unsupported large constant"));
4625 pos
= (unsigned long) imm_expr
.X_add_number
;
4626 size
= (unsigned long) imm2_expr
.X_add_number
;
4631 as_bad (_("Improper position (%lu)"), pos
);
4634 if (size
== 0 || size
> 64
4635 || (pos
+ size
- 1) > 63)
4637 as_bad (_("Improper insert size (%lu, position %lu)"),
4642 if (pos
< 32 && (pos
+ size
- 1) < 32)
4657 macro_build ((expressionS
*) NULL
, s
, fmt
, treg
, sreg
, pos
,
4674 as_warn (_("Divide by zero."));
4676 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4678 macro_build (NULL
, "break", "c", 7);
4682 mips_emit_delays (TRUE
);
4683 ++mips_opts
.noreorder
;
4684 mips_any_noreorder
= 1;
4687 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4688 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4692 expr1
.X_add_number
= 8;
4693 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4694 macro_build (NULL
, dbl
? "ddiv" : "div", "z,s,t", sreg
, treg
);
4695 macro_build (NULL
, "break", "c", 7);
4697 expr1
.X_add_number
= -1;
4698 load_register (AT
, &expr1
, dbl
);
4699 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
4700 macro_build (&expr1
, "bne", "s,t,p", treg
, AT
);
4703 expr1
.X_add_number
= 1;
4704 load_register (AT
, &expr1
, dbl
);
4705 macro_build (NULL
, "dsll32", "d,w,<", AT
, AT
, 31);
4709 expr1
.X_add_number
= 0x80000000;
4710 macro_build (&expr1
, "lui", "t,u", AT
, BFD_RELOC_HI16
);
4714 macro_build (NULL
, "teq", "s,t,q", sreg
, AT
, 6);
4715 /* We want to close the noreorder block as soon as possible, so
4716 that later insns are available for delay slot filling. */
4717 --mips_opts
.noreorder
;
4721 expr1
.X_add_number
= 8;
4722 macro_build (&expr1
, "bne", "s,t,p", sreg
, AT
);
4723 macro_build (NULL
, "nop", "", 0);
4725 /* We want to close the noreorder block as soon as possible, so
4726 that later insns are available for delay slot filling. */
4727 --mips_opts
.noreorder
;
4729 macro_build (NULL
, "break", "c", 6);
4731 macro_build (NULL
, s
, "d", dreg
);
4770 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4772 as_warn (_("Divide by zero."));
4774 macro_build (NULL
, "teq", "s,t,q", 0, 0, 7);
4776 macro_build (NULL
, "break", "c", 7);
4779 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4781 if (strcmp (s2
, "mflo") == 0)
4782 move_register (dreg
, sreg
);
4784 move_register (dreg
, 0);
4787 if (imm_expr
.X_op
== O_constant
4788 && imm_expr
.X_add_number
== -1
4789 && s
[strlen (s
) - 1] != 'u')
4791 if (strcmp (s2
, "mflo") == 0)
4793 macro_build (NULL
, dbl
? "dneg" : "neg", "d,w", dreg
, sreg
);
4796 move_register (dreg
, 0);
4800 load_register (AT
, &imm_expr
, dbl
);
4801 macro_build (NULL
, s
, "z,s,t", sreg
, AT
);
4802 macro_build (NULL
, s2
, "d", dreg
);
4821 mips_emit_delays (TRUE
);
4822 ++mips_opts
.noreorder
;
4823 mips_any_noreorder
= 1;
4826 macro_build (NULL
, "teq", "s,t,q", treg
, 0, 7);
4827 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4828 /* We want to close the noreorder block as soon as possible, so
4829 that later insns are available for delay slot filling. */
4830 --mips_opts
.noreorder
;
4834 expr1
.X_add_number
= 8;
4835 macro_build (&expr1
, "bne", "s,t,p", treg
, 0);
4836 macro_build (NULL
, s
, "z,s,t", sreg
, treg
);
4838 /* We want to close the noreorder block as soon as possible, so
4839 that later insns are available for delay slot filling. */
4840 --mips_opts
.noreorder
;
4841 macro_build (NULL
, "break", "c", 7);
4843 macro_build (NULL
, s2
, "d", dreg
);
4855 /* Load the address of a symbol into a register. If breg is not
4856 zero, we then add a base register to it. */
4858 if (dbl
&& HAVE_32BIT_GPRS
)
4859 as_warn (_("dla used to load 32-bit register"));
4861 if (! dbl
&& HAVE_64BIT_OBJECTS
)
4862 as_warn (_("la used to load 64-bit address"));
4864 if (offset_expr
.X_op
== O_constant
4865 && offset_expr
.X_add_number
>= -0x8000
4866 && offset_expr
.X_add_number
< 0x8000)
4868 macro_build (&offset_expr
,
4869 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4870 "t,r,j", treg
, sreg
, BFD_RELOC_LO16
);
4885 /* When generating embedded PIC code, we permit expressions of
4888 la $treg,foo-bar($breg)
4889 where bar is an address in the current section. These are used
4890 when getting the addresses of functions. We don't permit
4891 X_add_number to be non-zero, because if the symbol is
4892 external the relaxing code needs to know that any addend is
4893 purely the offset to X_op_symbol. */
4894 if (mips_pic
== EMBEDDED_PIC
4895 && offset_expr
.X_op
== O_subtract
4896 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4897 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4898 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4900 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4903 && (offset_expr
.X_add_number
== 0
4904 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4910 macro_build (&offset_expr
, "lui", "t,u",
4911 tempreg
, BFD_RELOC_PCREL_HI16_S
);
4915 macro_build (&offset_expr
, "lui", "t,u",
4916 tempreg
, BFD_RELOC_PCREL_HI16_S
);
4918 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu",
4919 "d,v,t", tempreg
, tempreg
, breg
);
4921 macro_build (&offset_expr
,
4922 (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddiu" : "addiu",
4923 "t,r,j", treg
, tempreg
, BFD_RELOC_PCREL_LO16
);
4929 if (offset_expr
.X_op
!= O_symbol
4930 && offset_expr
.X_op
!= O_constant
)
4932 as_bad (_("expression too complex"));
4933 offset_expr
.X_op
= O_constant
;
4936 if (offset_expr
.X_op
== O_constant
)
4937 load_register (tempreg
, &offset_expr
,
4938 ((mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
4939 ? (dbl
|| HAVE_64BIT_ADDRESSES
)
4940 : HAVE_64BIT_ADDRESSES
));
4941 else if (mips_pic
== NO_PIC
)
4943 /* If this is a reference to a GP relative symbol, we want
4944 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4946 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4947 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4948 If we have a constant, we need two instructions anyhow,
4949 so we may as well always use the latter form.
4951 With 64bit address space and a usable $at we want
4952 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4953 lui $at,<sym> (BFD_RELOC_HI16_S)
4954 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4955 daddiu $at,<sym> (BFD_RELOC_LO16)
4957 daddu $tempreg,$tempreg,$at
4959 If $at is already in use, we use a path which is suboptimal
4960 on superscalar processors.
4961 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4962 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4964 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4966 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4968 if (HAVE_64BIT_ADDRESSES
)
4970 /* ??? We don't provide a GP-relative alternative for
4971 these macros. It used not to be possible with the
4972 original relaxation code, but it could be done now. */
4974 if (used_at
== 0 && ! mips_opts
.noat
)
4976 macro_build (&offset_expr
, "lui", "t,u",
4977 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4978 macro_build (&offset_expr
, "lui", "t,u",
4979 AT
, BFD_RELOC_HI16_S
);
4980 macro_build (&offset_expr
, "daddiu", "t,r,j",
4981 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4982 macro_build (&offset_expr
, "daddiu", "t,r,j",
4983 AT
, AT
, BFD_RELOC_LO16
);
4984 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
4985 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
4990 macro_build (&offset_expr
, "lui", "t,u",
4991 tempreg
, BFD_RELOC_MIPS_HIGHEST
);
4992 macro_build (&offset_expr
, "daddiu", "t,r,j",
4993 tempreg
, tempreg
, BFD_RELOC_MIPS_HIGHER
);
4994 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4995 macro_build (&offset_expr
, "daddiu", "t,r,j",
4996 tempreg
, tempreg
, BFD_RELOC_HI16_S
);
4997 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
4998 macro_build (&offset_expr
, "daddiu", "t,r,j",
4999 tempreg
, tempreg
, BFD_RELOC_LO16
);
5004 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
5005 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5007 relax_start (offset_expr
.X_add_symbol
);
5008 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5009 tempreg
, mips_gp_register
, BFD_RELOC_GPREL16
);
5012 macro_build_lui (&offset_expr
, tempreg
);
5013 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5014 tempreg
, tempreg
, BFD_RELOC_LO16
);
5015 if (mips_relax
.sequence
)
5019 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& ! HAVE_NEWABI
)
5021 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5023 /* If this is a reference to an external symbol, and there
5024 is no constant, we want
5025 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5026 or for lca or if tempreg is PIC_CALL_REG
5027 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5028 For a local symbol, we want
5029 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5031 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5033 If we have a small constant, and this is a reference to
5034 an external symbol, we want
5035 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5037 addiu $tempreg,$tempreg,<constant>
5038 For a local symbol, we want the same instruction
5039 sequence, but we output a BFD_RELOC_LO16 reloc on the
5042 If we have a large constant, and this is a reference to
5043 an external symbol, we want
5044 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5045 lui $at,<hiconstant>
5046 addiu $at,$at,<loconstant>
5047 addu $tempreg,$tempreg,$at
5048 For a local symbol, we want the same instruction
5049 sequence, but we output a BFD_RELOC_LO16 reloc on the
5053 if (offset_expr
.X_add_number
== 0)
5055 if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5056 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL16
;
5058 relax_start (offset_expr
.X_add_symbol
);
5059 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5060 lw_reloc_type
, mips_gp_register
);
5063 /* We're going to put in an addu instruction using
5064 tempreg, so we may as well insert the nop right
5066 macro_build (NULL
, "nop", "");
5069 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5070 tempreg
, BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
5071 macro_build (NULL
, "nop", "");
5072 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5073 tempreg
, tempreg
, BFD_RELOC_LO16
);
5075 /* FIXME: If breg == 0, and the next instruction uses
5076 $tempreg, then if this variant case is used an extra
5077 nop will be generated. */
5079 else if (offset_expr
.X_add_number
>= -0x8000
5080 && offset_expr
.X_add_number
< 0x8000)
5082 load_got_offset (tempreg
, &offset_expr
);
5083 macro_build (NULL
, "nop", "");
5084 add_got_offset (tempreg
, &offset_expr
);
5088 expr1
.X_add_number
= offset_expr
.X_add_number
;
5089 offset_expr
.X_add_number
=
5090 ((offset_expr
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5091 load_got_offset (tempreg
, &offset_expr
);
5092 offset_expr
.X_add_number
= expr1
.X_add_number
;
5093 /* If we are going to add in a base register, and the
5094 target register and the base register are the same,
5095 then we are using AT as a temporary register. Since
5096 we want to load the constant into AT, we add our
5097 current AT (from the global offset table) and the
5098 register into the register now, and pretend we were
5099 not using a base register. */
5102 macro_build (NULL
, "nop", "");
5103 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5108 add_got_offset_hilo (tempreg
, &offset_expr
, AT
);
5112 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
&& HAVE_NEWABI
)
5114 int add_breg_early
= 0;
5116 /* If this is a reference to an external, and there is no
5117 constant, or local symbol (*), with or without a
5119 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5120 or for lca or if tempreg is PIC_CALL_REG
5121 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5123 If we have a small constant, and this is a reference to
5124 an external symbol, we want
5125 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5126 addiu $tempreg,$tempreg,<constant>
5128 If we have a large constant, and this is a reference to
5129 an external symbol, we want
5130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5131 lui $at,<hiconstant>
5132 addiu $at,$at,<loconstant>
5133 addu $tempreg,$tempreg,$at
5135 (*) Other assemblers seem to prefer GOT_PAGE/GOT_OFST for
5136 local symbols, even though it introduces an additional
5139 if (offset_expr
.X_add_number
)
5141 expr1
.X_add_number
= offset_expr
.X_add_number
;
5142 offset_expr
.X_add_number
= 0;
5144 relax_start (offset_expr
.X_add_symbol
);
5145 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5146 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5148 if (expr1
.X_add_number
>= -0x8000
5149 && expr1
.X_add_number
< 0x8000)
5151 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5152 tempreg
, tempreg
, BFD_RELOC_LO16
);
5154 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5158 /* If we are going to add in a base register, and the
5159 target register and the base register are the same,
5160 then we are using AT as a temporary register. Since
5161 we want to load the constant into AT, we add our
5162 current AT (from the global offset table) and the
5163 register into the register now, and pretend we were
5164 not using a base register. */
5169 assert (tempreg
== AT
);
5170 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5176 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5177 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5183 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5186 offset_expr
.X_add_number
= expr1
.X_add_number
;
5188 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5189 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5192 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5193 treg
, tempreg
, breg
);
5199 else if (breg
== 0 && (call
|| tempreg
== PIC_CALL_REG
))
5201 relax_start (offset_expr
.X_add_symbol
);
5202 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5203 BFD_RELOC_MIPS_CALL16
, mips_gp_register
);
5205 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5206 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5211 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5212 BFD_RELOC_MIPS_GOT_DISP
, mips_gp_register
);
5215 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
5218 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5219 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5220 int local_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
5222 /* This is the large GOT case. If this is a reference to an
5223 external symbol, and there is no constant, we want
5224 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5225 addu $tempreg,$tempreg,$gp
5226 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5227 or for lca or if tempreg is PIC_CALL_REG
5228 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5229 addu $tempreg,$tempreg,$gp
5230 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5231 For a local symbol, we want
5232 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5234 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5236 If we have a small constant, and this is a reference to
5237 an external symbol, we want
5238 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5239 addu $tempreg,$tempreg,$gp
5240 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5242 addiu $tempreg,$tempreg,<constant>
5243 For a local symbol, we want
5244 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5246 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
5248 If we have a large constant, and this is a reference to
5249 an external symbol, we want
5250 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5251 addu $tempreg,$tempreg,$gp
5252 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5253 lui $at,<hiconstant>
5254 addiu $at,$at,<loconstant>
5255 addu $tempreg,$tempreg,$at
5256 For a local symbol, we want
5257 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5258 lui $at,<hiconstant>
5259 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
5260 addu $tempreg,$tempreg,$at
5263 expr1
.X_add_number
= offset_expr
.X_add_number
;
5264 offset_expr
.X_add_number
= 0;
5265 relax_start (offset_expr
.X_add_symbol
);
5266 gpdelay
= reg_needs_delay (mips_gp_register
);
5267 if (expr1
.X_add_number
== 0 && breg
== 0
5268 && (call
|| tempreg
== PIC_CALL_REG
))
5270 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5271 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5273 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5274 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5275 tempreg
, tempreg
, mips_gp_register
);
5276 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5277 tempreg
, lw_reloc_type
, tempreg
);
5278 if (expr1
.X_add_number
== 0)
5282 /* We're going to put in an addu instruction using
5283 tempreg, so we may as well insert the nop right
5285 macro_build (NULL
, "nop", "");
5288 else if (expr1
.X_add_number
>= -0x8000
5289 && expr1
.X_add_number
< 0x8000)
5291 macro_build (NULL
, "nop", "");
5292 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5293 tempreg
, tempreg
, BFD_RELOC_LO16
);
5299 /* If we are going to add in a base register, and the
5300 target register and the base register are the same,
5301 then we are using AT as a temporary register. Since
5302 we want to load the constant into AT, we add our
5303 current AT (from the global offset table) and the
5304 register into the register now, and pretend we were
5305 not using a base register. */
5310 assert (tempreg
== AT
);
5311 macro_build (NULL
, "nop", "");
5312 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5317 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5318 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5322 offset_expr
.X_add_number
=
5323 ((expr1
.X_add_number
+ 0x8000) & 0xffff) - 0x8000;
5328 /* This is needed because this instruction uses $gp, but
5329 the first instruction on the main stream does not. */
5330 macro_build (NULL
, "nop", "");
5333 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5334 local_reloc_type
, mips_gp_register
);
5335 if (expr1
.X_add_number
>= -0x8000
5336 && expr1
.X_add_number
< 0x8000)
5338 macro_build (NULL
, "nop", "");
5339 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5340 tempreg
, tempreg
, BFD_RELOC_LO16
);
5341 /* FIXME: If add_number is 0, and there was no base
5342 register, the external symbol case ended with a load,
5343 so if the symbol turns out to not be external, and
5344 the next instruction uses tempreg, an unnecessary nop
5345 will be inserted. */
5351 /* We must add in the base register now, as in the
5352 external symbol case. */
5353 assert (tempreg
== AT
);
5354 macro_build (NULL
, "nop", "");
5355 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5358 /* We set breg to 0 because we have arranged to add
5359 it in in both cases. */
5363 macro_build_lui (&expr1
, AT
);
5364 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5365 AT
, AT
, BFD_RELOC_LO16
);
5366 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5367 tempreg
, tempreg
, AT
);
5371 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
5373 int lui_reloc_type
= (int) BFD_RELOC_MIPS_GOT_HI16
;
5374 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT_LO16
;
5375 int add_breg_early
= 0;
5377 /* This is the large GOT case. If this is a reference to an
5378 external symbol, and there is no constant, we want
5379 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5380 add $tempreg,$tempreg,$gp
5381 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5382 or for lca or if tempreg is PIC_CALL_REG
5383 lui $tempreg,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5384 add $tempreg,$tempreg,$gp
5385 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_CALL_LO16)
5387 If we have a small constant, and this is a reference to
5388 an external symbol, we want
5389 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5390 add $tempreg,$tempreg,$gp
5391 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5392 addi $tempreg,$tempreg,<constant>
5394 If we have a large constant, and this is a reference to
5395 an external symbol, we want
5396 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5397 addu $tempreg,$tempreg,$gp
5398 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5399 lui $at,<hiconstant>
5400 addi $at,$at,<loconstant>
5401 add $tempreg,$tempreg,$at
5403 If we have NewABI, and we know it's a local symbol, we want
5404 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
5405 addiu $reg,$reg,<sym> (BFD_RELOC_MIPS_GOT_OFST)
5406 otherwise we have to resort to GOT_HI16/GOT_LO16. */
5408 relax_start (offset_expr
.X_add_symbol
);
5410 expr1
.X_add_number
= offset_expr
.X_add_number
;
5411 offset_expr
.X_add_number
= 0;
5413 if (expr1
.X_add_number
== 0 && breg
== 0
5414 && (call
|| tempreg
== PIC_CALL_REG
))
5416 lui_reloc_type
= (int) BFD_RELOC_MIPS_CALL_HI16
;
5417 lw_reloc_type
= (int) BFD_RELOC_MIPS_CALL_LO16
;
5419 macro_build (&offset_expr
, "lui", "t,u", tempreg
, lui_reloc_type
);
5420 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5421 tempreg
, tempreg
, mips_gp_register
);
5422 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5423 tempreg
, lw_reloc_type
, tempreg
);
5425 if (expr1
.X_add_number
== 0)
5427 else if (expr1
.X_add_number
>= -0x8000
5428 && expr1
.X_add_number
< 0x8000)
5430 macro_build (&expr1
, ADDRESS_ADDI_INSN
, "t,r,j",
5431 tempreg
, tempreg
, BFD_RELOC_LO16
);
5433 else if (IS_SEXT_32BIT_NUM (expr1
.X_add_number
+ 0x8000))
5437 /* If we are going to add in a base register, and the
5438 target register and the base register are the same,
5439 then we are using AT as a temporary register. Since
5440 we want to load the constant into AT, we add our
5441 current AT (from the global offset table) and the
5442 register into the register now, and pretend we were
5443 not using a base register. */
5448 assert (tempreg
== AT
);
5449 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5455 load_register (AT
, &expr1
, HAVE_64BIT_ADDRESSES
);
5456 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", dreg
, dreg
, AT
);
5461 as_bad (_("PIC code offset overflow (max 32 signed bits)"));
5464 offset_expr
.X_add_number
= expr1
.X_add_number
;
5465 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
5466 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
5467 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5468 tempreg
, BFD_RELOC_MIPS_GOT_OFST
);
5471 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
5472 treg
, tempreg
, breg
);
5478 else if (mips_pic
== EMBEDDED_PIC
)
5481 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5483 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
5484 mips_gp_register
, BFD_RELOC_GPREL16
);
5493 if (mips_pic
== EMBEDDED_PIC
|| mips_pic
== NO_PIC
)
5494 s
= (dbl
|| HAVE_64BIT_ADDRESSES
) ? "daddu" : "addu";
5496 s
= ADDRESS_ADD_INSN
;
5498 macro_build (NULL
, s
, "d,v,t", treg
, tempreg
, breg
);
5507 /* The j instruction may not be used in PIC code, since it
5508 requires an absolute address. We convert it to a b
5510 if (mips_pic
== NO_PIC
)
5511 macro_build (&offset_expr
, "j", "a");
5513 macro_build (&offset_expr
, "b", "p");
5516 /* The jal instructions must be handled as macros because when
5517 generating PIC code they expand to multi-instruction
5518 sequences. Normally they are simple instructions. */
5523 if (mips_pic
== NO_PIC
5524 || mips_pic
== EMBEDDED_PIC
)
5525 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5526 else if (mips_pic
== SVR4_PIC
)
5528 if (sreg
!= PIC_CALL_REG
)
5529 as_warn (_("MIPS PIC call to register other than $25"));
5531 macro_build (NULL
, "jalr", "d,s", dreg
, sreg
);
5534 if (mips_cprestore_offset
< 0)
5535 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5538 if (! mips_frame_reg_valid
)
5540 as_warn (_("No .frame pseudo-op used in PIC code"));
5541 /* Quiet this warning. */
5542 mips_frame_reg_valid
= 1;
5544 if (! mips_cprestore_valid
)
5546 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5547 /* Quiet this warning. */
5548 mips_cprestore_valid
= 1;
5550 expr1
.X_add_number
= mips_cprestore_offset
;
5551 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5554 HAVE_64BIT_ADDRESSES
);
5564 if (mips_pic
== NO_PIC
)
5565 macro_build (&offset_expr
, "jal", "a");
5566 else if (mips_pic
== SVR4_PIC
)
5568 /* If this is a reference to an external symbol, and we are
5569 using a small GOT, we want
5570 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
5574 lw $gp,cprestore($sp)
5575 The cprestore value is set using the .cprestore
5576 pseudo-op. If we are using a big GOT, we want
5577 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
5579 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
5583 lw $gp,cprestore($sp)
5584 If the symbol is not external, we want
5585 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5587 addiu $25,$25,<sym> (BFD_RELOC_LO16)
5590 lw $gp,cprestore($sp)
5592 For NewABI, we use the same CALL16 or CALL_HI16/CALL_LO16
5593 sequences above, minus nops, unless the symbol is local,
5594 which enables us to use GOT_PAGE/GOT_OFST (big got) or
5600 relax_start (offset_expr
.X_add_symbol
);
5601 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5602 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5605 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5606 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_DISP
,
5612 relax_start (offset_expr
.X_add_symbol
);
5613 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5614 BFD_RELOC_MIPS_CALL_HI16
);
5615 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5616 PIC_CALL_REG
, mips_gp_register
);
5617 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5618 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5621 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5622 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT_PAGE
,
5624 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5625 PIC_CALL_REG
, PIC_CALL_REG
,
5626 BFD_RELOC_MIPS_GOT_OFST
);
5630 macro_build_jalr (&offset_expr
);
5634 relax_start (offset_expr
.X_add_symbol
);
5637 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5638 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL16
,
5640 macro_build (NULL
, "nop", "");
5647 gpdelay
= reg_needs_delay (mips_gp_register
);
5648 macro_build (&offset_expr
, "lui", "t,u", PIC_CALL_REG
,
5649 BFD_RELOC_MIPS_CALL_HI16
);
5650 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", PIC_CALL_REG
,
5651 PIC_CALL_REG
, mips_gp_register
);
5652 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5653 PIC_CALL_REG
, BFD_RELOC_MIPS_CALL_LO16
,
5655 macro_build (NULL
, "nop", "");
5658 macro_build (NULL
, "nop", "");
5660 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
5661 PIC_CALL_REG
, BFD_RELOC_MIPS_GOT16
,
5663 macro_build (NULL
, "nop", "");
5664 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j",
5665 PIC_CALL_REG
, PIC_CALL_REG
, BFD_RELOC_LO16
);
5667 macro_build_jalr (&offset_expr
);
5669 if (mips_cprestore_offset
< 0)
5670 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5673 if (! mips_frame_reg_valid
)
5675 as_warn (_("No .frame pseudo-op used in PIC code"));
5676 /* Quiet this warning. */
5677 mips_frame_reg_valid
= 1;
5679 if (! mips_cprestore_valid
)
5681 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5682 /* Quiet this warning. */
5683 mips_cprestore_valid
= 1;
5685 if (mips_opts
.noreorder
)
5686 macro_build (NULL
, "nop", "");
5687 expr1
.X_add_number
= mips_cprestore_offset
;
5688 macro_build_ldst_constoffset (&expr1
, ADDRESS_LOAD_INSN
,
5691 HAVE_64BIT_ADDRESSES
);
5695 else if (mips_pic
== EMBEDDED_PIC
)
5697 macro_build (&offset_expr
, "bal", "p");
5698 /* The linker may expand the call to a longer sequence which
5699 uses $at, so we must break rather than return. */
5724 /* Itbl support may require additional care here. */
5729 /* Itbl support may require additional care here. */
5734 /* Itbl support may require additional care here. */
5739 /* Itbl support may require additional care here. */
5751 if (mips_opts
.arch
== CPU_R4650
)
5753 as_bad (_("opcode not supported on this processor"));
5757 /* Itbl support may require additional care here. */
5762 /* Itbl support may require additional care here. */
5767 /* Itbl support may require additional care here. */
5787 if (breg
== treg
|| coproc
|| lr
)
5809 /* Itbl support may require additional care here. */
5814 /* Itbl support may require additional care here. */
5819 /* Itbl support may require additional care here. */
5824 /* Itbl support may require additional care here. */
5840 if (mips_opts
.arch
== CPU_R4650
)
5842 as_bad (_("opcode not supported on this processor"));
5847 /* Itbl support may require additional care here. */
5851 /* Itbl support may require additional care here. */
5856 /* Itbl support may require additional care here. */
5868 /* Itbl support may require additional care here. */
5869 if (mask
== M_LWC1_AB
5870 || mask
== M_SWC1_AB
5871 || mask
== M_LDC1_AB
5872 || mask
== M_SDC1_AB
5881 /* Sign-extending 32-bit constants makes their handling easier.
5882 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5884 if ((! HAVE_64BIT_ADDRESSES
5885 && (! HAVE_64BIT_GPRS
&& offset_expr
.X_op
== O_constant
))
5886 && (offset_expr
.X_op
== O_constant
)
5887 && ! ((offset_expr
.X_add_number
& ~((bfd_vma
) 0x7fffffff))
5888 == ~((bfd_vma
) 0x7fffffff)))
5890 if (offset_expr
.X_add_number
& ~((bfd_vma
) 0xffffffff))
5891 as_bad (_("constant too large"));
5893 offset_expr
.X_add_number
= (((offset_expr
.X_add_number
& 0xffffffff)
5894 ^ 0x80000000) - 0x80000000);
5897 /* For embedded PIC, we allow loads where the offset is calculated
5898 by subtracting a symbol in the current segment from an unknown
5899 symbol, relative to a base register, e.g.:
5900 <op> $treg, <sym>-<localsym>($breg)
5901 This is used by the compiler for switch statements. */
5902 if (mips_pic
== EMBEDDED_PIC
5903 && offset_expr
.X_op
== O_subtract
5904 && (symbol_constant_p (offset_expr
.X_op_symbol
)
5905 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
5906 : (symbol_equated_p (offset_expr
.X_op_symbol
)
5908 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
5912 && (offset_expr
.X_add_number
== 0
5913 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
5915 /* For this case, we output the instructions:
5916 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5917 addiu $tempreg,$tempreg,$breg
5918 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5919 If the relocation would fit entirely in 16 bits, it would be
5921 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5922 instead, but that seems quite difficult. */
5923 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
5924 BFD_RELOC_PCREL_HI16_S
);
5926 ((bfd_arch_bits_per_address (stdoutput
) == 32
5927 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5928 ? "addu" : "daddu"),
5929 "d,v,t", tempreg
, tempreg
, breg
);
5930 macro_build (&offset_expr
, s
, fmt
, treg
,
5931 BFD_RELOC_PCREL_LO16
, tempreg
);
5937 if (offset_expr
.X_op
!= O_constant
5938 && offset_expr
.X_op
!= O_symbol
)
5940 as_bad (_("expression too complex"));
5941 offset_expr
.X_op
= O_constant
;
5944 /* A constant expression in PIC code can be handled just as it
5945 is in non PIC code. */
5946 if (mips_pic
== NO_PIC
5947 || offset_expr
.X_op
== O_constant
)
5949 /* If this is a reference to a GP relative symbol, and there
5950 is no base register, we want
5951 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5952 Otherwise, if there is no base register, we want
5953 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5954 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5955 If we have a constant, we need two instructions anyhow,
5956 so we always use the latter form.
5958 If we have a base register, and this is a reference to a
5959 GP relative symbol, we want
5960 addu $tempreg,$breg,$gp
5961 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
5963 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5964 addu $tempreg,$tempreg,$breg
5965 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5966 With a constant we always use the latter case.
5968 With 64bit address space and no base register and $at usable,
5970 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5971 lui $at,<sym> (BFD_RELOC_HI16_S)
5972 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5975 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5976 If we have a base register, we want
5977 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5978 lui $at,<sym> (BFD_RELOC_HI16_S)
5979 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5983 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5985 Without $at we can't generate the optimal path for superscalar
5986 processors here since this would require two temporary registers.
5987 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5988 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5990 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5992 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5993 If we have a base register, we want
5994 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5995 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5997 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5999 daddu $tempreg,$tempreg,$breg
6000 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6002 If we have 64-bit addresses, as an optimization, for
6003 addresses which are 32-bit constants (e.g. kseg0/kseg1
6004 addresses) we fall back to the 32-bit address generation
6005 mechanism since it is more efficient. Note that due to
6006 the signed offset used by memory operations, the 32-bit
6007 range is shifted down by 32768 here. This code should
6008 probably attempt to generate 64-bit constants more
6009 efficiently in general.
6011 As an extension for architectures with 64-bit registers,
6012 we don't truncate 64-bit addresses given as literal
6013 constants down to 32 bits, to support existing practice
6014 in the mips64 Linux (the kernel), that compiles source
6015 files with -mabi=64, assembling them as o32 or n32 (with
6016 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6017 the whole kernel is loaded into a memory region that is
6018 addressable with sign-extended 32-bit addresses, it is
6019 wasteful to compute the upper 32 bits of every
6020 non-literal address, that takes more space and time.
6021 Some day this should probably be implemented as an
6022 assembler option, such that the kernel doesn't have to
6023 use such ugly hacks, even though it will still have to
6024 end up converting the binary to ELF32 for a number of
6025 platforms whose boot loaders don't support ELF64
6027 if ((HAVE_64BIT_ADDRESSES
6028 && ! (offset_expr
.X_op
== O_constant
6029 && IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
6031 && offset_expr
.X_op
== O_constant
6032 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000)))
6034 /* ??? We don't provide a GP-relative alternative for
6035 these macros. It used not to be possible with the
6036 original relaxation code, but it could be done now. */
6038 if (used_at
== 0 && ! mips_opts
.noat
)
6040 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6041 BFD_RELOC_MIPS_HIGHEST
);
6042 macro_build (&offset_expr
, "lui", "t,u", AT
,
6044 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6045 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6047 macro_build (NULL
, "daddu", "d,v,t", AT
, AT
, breg
);
6048 macro_build (NULL
, "dsll32", "d,w,<", tempreg
, tempreg
, 0);
6049 macro_build (NULL
, "daddu", "d,v,t", tempreg
, tempreg
, AT
);
6050 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_LO16
,
6056 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6057 BFD_RELOC_MIPS_HIGHEST
);
6058 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6059 tempreg
, BFD_RELOC_MIPS_HIGHER
);
6060 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6061 macro_build (&offset_expr
, "daddiu", "t,r,j", tempreg
,
6062 tempreg
, BFD_RELOC_HI16_S
);
6063 macro_build (NULL
, "dsll", "d,w,<", tempreg
, tempreg
, 16);
6065 macro_build (NULL
, "daddu", "d,v,t",
6066 tempreg
, tempreg
, breg
);
6067 macro_build (&offset_expr
, s
, fmt
, treg
,
6068 BFD_RELOC_LO16
, tempreg
);
6074 if (offset_expr
.X_op
== O_constant
6075 && ! IS_SEXT_32BIT_NUM (offset_expr
.X_add_number
+ 0x8000))
6076 as_bad (_("load/store address overflow (max 32 bits)"));
6080 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6081 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6083 relax_start (offset_expr
.X_add_symbol
);
6084 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6089 macro_build_lui (&offset_expr
, tempreg
);
6090 macro_build (&offset_expr
, s
, fmt
, treg
,
6091 BFD_RELOC_LO16
, tempreg
);
6092 if (mips_relax
.sequence
)
6097 if ((valueT
) offset_expr
.X_add_number
<= MAX_GPREL_OFFSET
6098 && ! nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6100 relax_start (offset_expr
.X_add_symbol
);
6101 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6102 tempreg
, breg
, mips_gp_register
);
6103 macro_build (&offset_expr
, s
, fmt
, treg
,
6104 BFD_RELOC_GPREL16
, tempreg
);
6107 macro_build_lui (&offset_expr
, tempreg
);
6108 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6109 tempreg
, tempreg
, breg
);
6110 macro_build (&offset_expr
, s
, fmt
, treg
,
6111 BFD_RELOC_LO16
, tempreg
);
6112 if (mips_relax
.sequence
)
6116 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6118 int lw_reloc_type
= (int) BFD_RELOC_MIPS_GOT16
;
6120 /* If this is a reference to an external symbol, we want
6121 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6123 <op> $treg,0($tempreg)
6125 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6127 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6128 <op> $treg,0($tempreg)
6131 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6132 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST)
6134 If there is a base register, we add it to $tempreg before
6135 the <op>. If there is a constant, we stick it in the
6136 <op> instruction. We don't handle constants larger than
6137 16 bits, because we have no way to load the upper 16 bits
6138 (actually, we could handle them for the subset of cases
6139 in which we are not using $at). */
6140 assert (offset_expr
.X_op
== O_symbol
);
6143 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6144 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6146 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6147 tempreg
, tempreg
, breg
);
6148 macro_build (&offset_expr
, s
, fmt
, treg
,
6149 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6156 expr1
.X_add_number
= offset_expr
.X_add_number
;
6157 offset_expr
.X_add_number
= 0;
6158 if (expr1
.X_add_number
< -0x8000
6159 || expr1
.X_add_number
>= 0x8000)
6160 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6161 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6162 lw_reloc_type
, mips_gp_register
);
6163 macro_build (NULL
, "nop", "");
6164 relax_start (offset_expr
.X_add_symbol
);
6166 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6167 tempreg
, BFD_RELOC_LO16
);
6170 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6171 tempreg
, tempreg
, breg
);
6172 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6174 else if (mips_pic
== SVR4_PIC
&& ! HAVE_NEWABI
)
6178 /* If this is a reference to an external symbol, we want
6179 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6180 addu $tempreg,$tempreg,$gp
6181 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6182 <op> $treg,0($tempreg)
6184 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6186 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
6187 <op> $treg,0($tempreg)
6188 If there is a base register, we add it to $tempreg before
6189 the <op>. If there is a constant, we stick it in the
6190 <op> instruction. We don't handle constants larger than
6191 16 bits, because we have no way to load the upper 16 bits
6192 (actually, we could handle them for the subset of cases
6193 in which we are not using $at). */
6194 assert (offset_expr
.X_op
== O_symbol
);
6195 expr1
.X_add_number
= offset_expr
.X_add_number
;
6196 offset_expr
.X_add_number
= 0;
6197 if (expr1
.X_add_number
< -0x8000
6198 || expr1
.X_add_number
>= 0x8000)
6199 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6200 gpdelay
= reg_needs_delay (mips_gp_register
);
6201 relax_start (offset_expr
.X_add_symbol
);
6202 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6203 BFD_RELOC_MIPS_GOT_HI16
);
6204 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6206 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6207 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6210 macro_build (NULL
, "nop", "");
6211 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6212 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6213 macro_build (NULL
, "nop", "");
6214 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", tempreg
,
6215 tempreg
, BFD_RELOC_LO16
);
6219 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6220 tempreg
, tempreg
, breg
);
6221 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6223 else if (mips_pic
== SVR4_PIC
&& HAVE_NEWABI
)
6225 /* If this is a reference to an external symbol, we want
6226 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6227 add $tempreg,$tempreg,$gp
6228 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6229 <op> $treg,<ofst>($tempreg)
6230 Otherwise, for local symbols, we want:
6231 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)
6232 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_OFST) */
6233 assert (offset_expr
.X_op
== O_symbol
);
6234 expr1
.X_add_number
= offset_expr
.X_add_number
;
6235 offset_expr
.X_add_number
= 0;
6236 if (expr1
.X_add_number
< -0x8000
6237 || expr1
.X_add_number
>= 0x8000)
6238 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6239 relax_start (offset_expr
.X_add_symbol
);
6240 macro_build (&offset_expr
, "lui", "t,u", tempreg
,
6241 BFD_RELOC_MIPS_GOT_HI16
);
6242 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", tempreg
, tempreg
,
6244 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6245 BFD_RELOC_MIPS_GOT_LO16
, tempreg
);
6247 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6248 tempreg
, tempreg
, breg
);
6249 macro_build (&expr1
, s
, fmt
, treg
, BFD_RELOC_LO16
, tempreg
);
6252 offset_expr
.X_add_number
= expr1
.X_add_number
;
6253 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", tempreg
,
6254 BFD_RELOC_MIPS_GOT_PAGE
, mips_gp_register
);
6256 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6257 tempreg
, tempreg
, breg
);
6258 macro_build (&offset_expr
, s
, fmt
, treg
,
6259 BFD_RELOC_MIPS_GOT_OFST
, tempreg
);
6262 else if (mips_pic
== EMBEDDED_PIC
)
6264 /* If there is no base register, we want
6265 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6266 If there is a base register, we want
6267 addu $tempreg,$breg,$gp
6268 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6270 assert (offset_expr
.X_op
== O_symbol
);
6273 macro_build (&offset_expr
, s
, fmt
, treg
, BFD_RELOC_GPREL16
,
6279 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6280 tempreg
, breg
, mips_gp_register
);
6281 macro_build (&offset_expr
, s
, fmt
, treg
,
6282 BFD_RELOC_GPREL16
, tempreg
);
6295 load_register (treg
, &imm_expr
, 0);
6299 load_register (treg
, &imm_expr
, 1);
6303 if (imm_expr
.X_op
== O_constant
)
6305 load_register (AT
, &imm_expr
, 0);
6306 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6311 assert (offset_expr
.X_op
== O_symbol
6312 && strcmp (segment_name (S_GET_SEGMENT
6313 (offset_expr
.X_add_symbol
)),
6315 && offset_expr
.X_add_number
== 0);
6316 macro_build (&offset_expr
, "lwc1", "T,o(b)", treg
,
6317 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6322 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6323 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6324 order 32 bits of the value and the low order 32 bits are either
6325 zero or in OFFSET_EXPR. */
6326 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6328 if (HAVE_64BIT_GPRS
)
6329 load_register (treg
, &imm_expr
, 1);
6334 if (target_big_endian
)
6346 load_register (hreg
, &imm_expr
, 0);
6349 if (offset_expr
.X_op
== O_absent
)
6350 move_register (lreg
, 0);
6353 assert (offset_expr
.X_op
== O_constant
);
6354 load_register (lreg
, &offset_expr
, 0);
6361 /* We know that sym is in the .rdata section. First we get the
6362 upper 16 bits of the address. */
6363 if (mips_pic
== NO_PIC
)
6365 macro_build_lui (&offset_expr
, AT
);
6367 else if (mips_pic
== SVR4_PIC
)
6369 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6370 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6372 else if (mips_pic
== EMBEDDED_PIC
)
6374 /* For embedded PIC we pick up the entire address off $gp in
6375 a single instruction. */
6376 macro_build (&offset_expr
, ADDRESS_ADDI_INSN
, "t,r,j", AT
,
6377 mips_gp_register
, BFD_RELOC_GPREL16
);
6378 offset_expr
.X_op
= O_constant
;
6379 offset_expr
.X_add_number
= 0;
6384 /* Now we load the register(s). */
6385 if (HAVE_64BIT_GPRS
)
6386 macro_build (&offset_expr
, "ld", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6389 macro_build (&offset_expr
, "lw", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
6392 /* FIXME: How in the world do we deal with the possible
6394 offset_expr
.X_add_number
+= 4;
6395 macro_build (&offset_expr
, "lw", "t,o(b)",
6396 treg
+ 1, BFD_RELOC_LO16
, AT
);
6402 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6403 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6404 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6405 the value and the low order 32 bits are either zero or in
6407 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
6409 load_register (AT
, &imm_expr
, HAVE_64BIT_FPRS
);
6410 if (HAVE_64BIT_FPRS
)
6412 assert (HAVE_64BIT_GPRS
);
6413 macro_build (NULL
, "dmtc1", "t,S", AT
, treg
);
6417 macro_build (NULL
, "mtc1", "t,G", AT
, treg
+ 1);
6418 if (offset_expr
.X_op
== O_absent
)
6419 macro_build (NULL
, "mtc1", "t,G", 0, treg
);
6422 assert (offset_expr
.X_op
== O_constant
);
6423 load_register (AT
, &offset_expr
, 0);
6424 macro_build (NULL
, "mtc1", "t,G", AT
, treg
);
6430 assert (offset_expr
.X_op
== O_symbol
6431 && offset_expr
.X_add_number
== 0);
6432 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
6433 if (strcmp (s
, ".lit8") == 0)
6435 if (mips_opts
.isa
!= ISA_MIPS1
)
6437 macro_build (&offset_expr
, "ldc1", "T,o(b)", treg
,
6438 BFD_RELOC_MIPS_LITERAL
, mips_gp_register
);
6441 breg
= mips_gp_register
;
6442 r
= BFD_RELOC_MIPS_LITERAL
;
6447 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
6448 if (mips_pic
== SVR4_PIC
)
6449 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6450 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6453 /* FIXME: This won't work for a 64 bit address. */
6454 macro_build_lui (&offset_expr
, AT
);
6457 if (mips_opts
.isa
!= ISA_MIPS1
)
6459 macro_build (&offset_expr
, "ldc1", "T,o(b)",
6460 treg
, BFD_RELOC_LO16
, AT
);
6469 if (mips_opts
.arch
== CPU_R4650
)
6471 as_bad (_("opcode not supported on this processor"));
6474 /* Even on a big endian machine $fn comes before $fn+1. We have
6475 to adjust when loading from memory. */
6478 assert (mips_opts
.isa
== ISA_MIPS1
);
6479 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6480 target_big_endian
? treg
+ 1 : treg
, r
, breg
);
6481 /* FIXME: A possible overflow which I don't know how to deal
6483 offset_expr
.X_add_number
+= 4;
6484 macro_build (&offset_expr
, "lwc1", "T,o(b)",
6485 target_big_endian
? treg
: treg
+ 1, r
, breg
);
6493 * The MIPS assembler seems to check for X_add_number not
6494 * being double aligned and generating:
6497 * addiu at,at,%lo(foo+1)
6500 * But, the resulting address is the same after relocation so why
6501 * generate the extra instruction?
6503 if (mips_opts
.arch
== CPU_R4650
)
6505 as_bad (_("opcode not supported on this processor"));
6508 /* Itbl support may require additional care here. */
6510 if (mips_opts
.isa
!= ISA_MIPS1
)
6521 if (mips_opts
.arch
== CPU_R4650
)
6523 as_bad (_("opcode not supported on this processor"));
6527 if (mips_opts
.isa
!= ISA_MIPS1
)
6535 /* Itbl support may require additional care here. */
6540 if (HAVE_64BIT_GPRS
)
6551 if (HAVE_64BIT_GPRS
)
6561 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6562 loads for the case of doing a pair of loads to simulate an 'ld'.
6563 This is not currently done by the compiler, and assembly coders
6564 writing embedded-pic code can cope. */
6566 if (offset_expr
.X_op
!= O_symbol
6567 && offset_expr
.X_op
!= O_constant
)
6569 as_bad (_("expression too complex"));
6570 offset_expr
.X_op
= O_constant
;
6573 /* Even on a big endian machine $fn comes before $fn+1. We have
6574 to adjust when loading from memory. We set coproc if we must
6575 load $fn+1 first. */
6576 /* Itbl support may require additional care here. */
6577 if (! target_big_endian
)
6580 if (mips_pic
== NO_PIC
6581 || offset_expr
.X_op
== O_constant
)
6583 /* If this is a reference to a GP relative symbol, we want
6584 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6585 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6586 If we have a base register, we use this
6588 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6589 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6590 If this is not a GP relative symbol, we want
6591 lui $at,<sym> (BFD_RELOC_HI16_S)
6592 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6593 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6594 If there is a base register, we add it to $at after the
6595 lui instruction. If there is a constant, we always use
6597 if ((valueT
) offset_expr
.X_add_number
> MAX_GPREL_OFFSET
6598 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
6602 relax_start (offset_expr
.X_add_symbol
);
6605 tempreg
= mips_gp_register
;
6610 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6611 AT
, breg
, mips_gp_register
);
6616 /* Itbl support may require additional care here. */
6617 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6618 BFD_RELOC_GPREL16
, tempreg
);
6619 offset_expr
.X_add_number
+= 4;
6621 /* Set mips_optimize to 2 to avoid inserting an
6623 hold_mips_optimize
= mips_optimize
;
6625 /* Itbl support may require additional care here. */
6626 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6627 BFD_RELOC_GPREL16
, tempreg
);
6628 mips_optimize
= hold_mips_optimize
;
6632 /* We just generated two relocs. When tc_gen_reloc
6633 handles this case, it will skip the first reloc and
6634 handle the second. The second reloc already has an
6635 extra addend of 4, which we added above. We must
6636 subtract it out, and then subtract another 4 to make
6637 the first reloc come out right. The second reloc
6638 will come out right because we are going to add 4 to
6639 offset_expr when we build its instruction below.
6641 If we have a symbol, then we don't want to include
6642 the offset, because it will wind up being included
6643 when we generate the reloc. */
6645 if (offset_expr
.X_op
== O_constant
)
6646 offset_expr
.X_add_number
-= 8;
6649 offset_expr
.X_add_number
= -4;
6650 offset_expr
.X_op
= O_constant
;
6653 macro_build_lui (&offset_expr
, AT
);
6655 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6656 /* Itbl support may require additional care here. */
6657 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6658 BFD_RELOC_LO16
, AT
);
6659 /* FIXME: How do we handle overflow here? */
6660 offset_expr
.X_add_number
+= 4;
6661 /* Itbl support may require additional care here. */
6662 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6663 BFD_RELOC_LO16
, AT
);
6664 if (mips_relax
.sequence
)
6667 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
6669 /* If this is a reference to an external symbol, we want
6670 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6675 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6677 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6678 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6679 If there is a base register we add it to $at before the
6680 lwc1 instructions. If there is a constant we include it
6681 in the lwc1 instructions. */
6683 expr1
.X_add_number
= offset_expr
.X_add_number
;
6684 if (expr1
.X_add_number
< -0x8000
6685 || expr1
.X_add_number
>= 0x8000 - 4)
6686 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6687 load_got_offset (AT
, &offset_expr
);
6688 macro_build (NULL
, "nop", "");
6690 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6692 /* Set mips_optimize to 2 to avoid inserting an undesired
6694 hold_mips_optimize
= mips_optimize
;
6697 /* Itbl support may require additional care here. */
6698 relax_start (offset_expr
.X_add_symbol
);
6699 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6700 BFD_RELOC_LO16
, AT
);
6701 expr1
.X_add_number
+= 4;
6702 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6703 BFD_RELOC_LO16
, AT
);
6705 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6706 BFD_RELOC_LO16
, AT
);
6707 offset_expr
.X_add_number
+= 4;
6708 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6709 BFD_RELOC_LO16
, AT
);
6712 mips_optimize
= hold_mips_optimize
;
6714 else if (mips_pic
== SVR4_PIC
)
6718 /* If this is a reference to an external symbol, we want
6719 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6721 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6726 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6728 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6729 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6730 If there is a base register we add it to $at before the
6731 lwc1 instructions. If there is a constant we include it
6732 in the lwc1 instructions. */
6734 expr1
.X_add_number
= offset_expr
.X_add_number
;
6735 offset_expr
.X_add_number
= 0;
6736 if (expr1
.X_add_number
< -0x8000
6737 || expr1
.X_add_number
>= 0x8000 - 4)
6738 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6739 gpdelay
= reg_needs_delay (mips_gp_register
);
6740 relax_start (offset_expr
.X_add_symbol
);
6741 macro_build (&offset_expr
, "lui", "t,u",
6742 AT
, BFD_RELOC_MIPS_GOT_HI16
);
6743 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6744 AT
, AT
, mips_gp_register
);
6745 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)",
6746 AT
, BFD_RELOC_MIPS_GOT_LO16
, AT
);
6747 macro_build (NULL
, "nop", "");
6749 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6750 /* Itbl support may require additional care here. */
6751 macro_build (&expr1
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6752 BFD_RELOC_LO16
, AT
);
6753 expr1
.X_add_number
+= 4;
6755 /* Set mips_optimize to 2 to avoid inserting an undesired
6757 hold_mips_optimize
= mips_optimize
;
6759 /* Itbl support may require additional care here. */
6760 macro_build (&expr1
, s
, fmt
, coproc
? treg
: treg
+ 1,
6761 BFD_RELOC_LO16
, AT
);
6762 mips_optimize
= hold_mips_optimize
;
6763 expr1
.X_add_number
-= 4;
6766 offset_expr
.X_add_number
= expr1
.X_add_number
;
6768 macro_build (NULL
, "nop", "");
6769 macro_build (&offset_expr
, ADDRESS_LOAD_INSN
, "t,o(b)", AT
,
6770 BFD_RELOC_MIPS_GOT16
, mips_gp_register
);
6771 macro_build (NULL
, "nop", "");
6773 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, breg
, AT
);
6774 /* Itbl support may require additional care here. */
6775 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6776 BFD_RELOC_LO16
, AT
);
6777 offset_expr
.X_add_number
+= 4;
6779 /* Set mips_optimize to 2 to avoid inserting an undesired
6781 hold_mips_optimize
= mips_optimize
;
6783 /* Itbl support may require additional care here. */
6784 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6785 BFD_RELOC_LO16
, AT
);
6786 mips_optimize
= hold_mips_optimize
;
6789 else if (mips_pic
== EMBEDDED_PIC
)
6791 /* If there is no base register, we use
6792 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6793 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6794 If we have a base register, we use
6796 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6797 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6801 tempreg
= mips_gp_register
;
6806 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t",
6807 AT
, breg
, mips_gp_register
);
6812 /* Itbl support may require additional care here. */
6813 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
+ 1 : treg
,
6814 BFD_RELOC_GPREL16
, tempreg
);
6815 offset_expr
.X_add_number
+= 4;
6816 /* Itbl support may require additional care here. */
6817 macro_build (&offset_expr
, s
, fmt
, coproc
? treg
: treg
+ 1,
6818 BFD_RELOC_GPREL16
, tempreg
);
6834 assert (HAVE_32BIT_ADDRESSES
);
6835 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
6836 offset_expr
.X_add_number
+= 4;
6837 macro_build (&offset_expr
, s
, "t,o(b)", treg
+ 1, BFD_RELOC_LO16
, breg
);
6840 /* New code added to support COPZ instructions.
6841 This code builds table entries out of the macros in mip_opcodes.
6842 R4000 uses interlocks to handle coproc delays.
6843 Other chips (like the R3000) require nops to be inserted for delays.
6845 FIXME: Currently, we require that the user handle delays.
6846 In order to fill delay slots for non-interlocked chips,
6847 we must have a way to specify delays based on the coprocessor.
6848 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
6849 What are the side-effects of the cop instruction?
6850 What cache support might we have and what are its effects?
6851 Both coprocessor & memory require delays. how long???
6852 What registers are read/set/modified?
6854 If an itbl is provided to interpret cop instructions,
6855 this knowledge can be encoded in the itbl spec. */
6869 /* For now we just do C (same as Cz). The parameter will be
6870 stored in insn_opcode by mips_ip. */
6871 macro_build (NULL
, s
, "C", ip
->insn_opcode
);
6875 move_register (dreg
, sreg
);
6878 #ifdef LOSING_COMPILER
6880 /* Try and see if this is a new itbl instruction.
6881 This code builds table entries out of the macros in mip_opcodes.
6882 FIXME: For now we just assemble the expression and pass it's
6883 value along as a 32-bit immediate.
6884 We may want to have the assembler assemble this value,
6885 so that we gain the assembler's knowledge of delay slots,
6887 Would it be more efficient to use mask (id) here? */
6888 if (itbl_have_entries
6889 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
6891 s
= ip
->insn_mo
->name
;
6893 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
6894 macro_build (&immed_expr
, s
, "C");
6901 as_warn (_("Macro used $at after \".set noat\""));
6905 macro2 (struct mips_cl_insn
*ip
)
6907 register int treg
, sreg
, dreg
, breg
;
6922 bfd_reloc_code_real_type r
;
6924 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
6925 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
6926 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
6927 mask
= ip
->insn_mo
->mask
;
6929 expr1
.X_op
= O_constant
;
6930 expr1
.X_op_symbol
= NULL
;
6931 expr1
.X_add_symbol
= NULL
;
6932 expr1
.X_add_number
= 1;
6936 #endif /* LOSING_COMPILER */
6941 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t", sreg
, treg
);
6942 macro_build (NULL
, "mflo", "d", dreg
);
6948 /* The MIPS assembler some times generates shifts and adds. I'm
6949 not trying to be that fancy. GCC should do this for us
6951 load_register (AT
, &imm_expr
, dbl
);
6952 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, AT
);
6953 macro_build (NULL
, "mflo", "d", dreg
);
6966 mips_emit_delays (TRUE
);
6967 ++mips_opts
.noreorder
;
6968 mips_any_noreorder
= 1;
6970 load_register (AT
, &imm_expr
, dbl
);
6971 macro_build (NULL
, dbl
? "dmult" : "mult", "s,t", sreg
, imm
? AT
: treg
);
6972 macro_build (NULL
, "mflo", "d", dreg
);
6973 macro_build (NULL
, dbl
? "dsra32" : "sra", "d,w,<", dreg
, dreg
, RA
);
6974 macro_build (NULL
, "mfhi", "d", AT
);
6976 macro_build (NULL
, "tne", "s,t,q", dreg
, AT
, 6);
6979 expr1
.X_add_number
= 8;
6980 macro_build (&expr1
, "beq", "s,t,p", dreg
, AT
);
6981 macro_build (NULL
, "nop", "", 0);
6982 macro_build (NULL
, "break", "c", 6);
6984 --mips_opts
.noreorder
;
6985 macro_build (NULL
, "mflo", "d", dreg
);
6998 mips_emit_delays (TRUE
);
6999 ++mips_opts
.noreorder
;
7000 mips_any_noreorder
= 1;
7002 load_register (AT
, &imm_expr
, dbl
);
7003 macro_build (NULL
, dbl
? "dmultu" : "multu", "s,t",
7004 sreg
, imm
? AT
: treg
);
7005 macro_build (NULL
, "mfhi", "d", AT
);
7006 macro_build (NULL
, "mflo", "d", dreg
);
7008 macro_build (NULL
, "tne", "s,t,q", AT
, 0, 6);
7011 expr1
.X_add_number
= 8;
7012 macro_build (&expr1
, "beq", "s,t,p", AT
, 0);
7013 macro_build (NULL
, "nop", "", 0);
7014 macro_build (NULL
, "break", "c", 6);
7016 --mips_opts
.noreorder
;
7020 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7032 macro_build (NULL
, "dnegu", "d,w", tempreg
, treg
);
7033 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, tempreg
);
7038 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7039 macro_build (NULL
, "dsrlv", "d,t,s", AT
, sreg
, AT
);
7040 macro_build (NULL
, "dsllv", "d,t,s", dreg
, sreg
, treg
);
7041 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7045 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7057 macro_build (NULL
, "negu", "d,w", tempreg
, treg
);
7058 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, tempreg
);
7063 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7064 macro_build (NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
7065 macro_build (NULL
, "sllv", "d,t,s", dreg
, sreg
, treg
);
7066 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7074 if (imm_expr
.X_op
!= O_constant
)
7075 as_bad (_("Improper rotate count"));
7076 rot
= imm_expr
.X_add_number
& 0x3f;
7077 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7079 rot
= (64 - rot
) & 0x3f;
7081 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7083 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7088 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7091 l
= (rot
< 0x20) ? "dsll" : "dsll32";
7092 r
= ((0x40 - rot
) < 0x20) ? "dsrl" : "dsrl32";
7094 macro_build (NULL
, l
, "d,w,<", AT
, sreg
, rot
);
7095 macro_build (NULL
, r
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7096 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7104 if (imm_expr
.X_op
!= O_constant
)
7105 as_bad (_("Improper rotate count"));
7106 rot
= imm_expr
.X_add_number
& 0x1f;
7107 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7109 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, (32 - rot
) & 0x1f);
7114 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7117 macro_build (NULL
, "sll", "d,w,<", AT
, sreg
, rot
);
7118 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7119 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7124 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7126 macro_build (NULL
, "drorv", "d,t,s", dreg
, sreg
, treg
);
7129 macro_build (NULL
, "dsubu", "d,v,t", AT
, 0, treg
);
7130 macro_build (NULL
, "dsllv", "d,t,s", AT
, sreg
, AT
);
7131 macro_build (NULL
, "dsrlv", "d,t,s", dreg
, sreg
, treg
);
7132 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7136 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7138 macro_build (NULL
, "rorv", "d,t,s", dreg
, sreg
, treg
);
7141 macro_build (NULL
, "subu", "d,v,t", AT
, 0, treg
);
7142 macro_build (NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
7143 macro_build (NULL
, "srlv", "d,t,s", dreg
, sreg
, treg
);
7144 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7152 if (imm_expr
.X_op
!= O_constant
)
7153 as_bad (_("Improper rotate count"));
7154 rot
= imm_expr
.X_add_number
& 0x3f;
7155 if (ISA_HAS_DROR (mips_opts
.isa
) || CPU_HAS_DROR (mips_opts
.arch
))
7158 macro_build (NULL
, "dror32", "d,w,<", dreg
, sreg
, rot
- 32);
7160 macro_build (NULL
, "dror", "d,w,<", dreg
, sreg
, rot
);
7165 macro_build (NULL
, "dsrl", "d,w,<", dreg
, sreg
, 0);
7168 r
= (rot
< 0x20) ? "dsrl" : "dsrl32";
7169 l
= ((0x40 - rot
) < 0x20) ? "dsll" : "dsll32";
7171 macro_build (NULL
, r
, "d,w,<", AT
, sreg
, rot
);
7172 macro_build (NULL
, l
, "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7173 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7181 if (imm_expr
.X_op
!= O_constant
)
7182 as_bad (_("Improper rotate count"));
7183 rot
= imm_expr
.X_add_number
& 0x1f;
7184 if (ISA_HAS_ROR (mips_opts
.isa
) || CPU_HAS_ROR (mips_opts
.arch
))
7186 macro_build (NULL
, "ror", "d,w,<", dreg
, sreg
, rot
);
7191 macro_build (NULL
, "srl", "d,w,<", dreg
, sreg
, 0);
7194 macro_build (NULL
, "srl", "d,w,<", AT
, sreg
, rot
);
7195 macro_build (NULL
, "sll", "d,w,<", dreg
, sreg
, (0x20 - rot
) & 0x1f);
7196 macro_build (NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
7201 if (mips_opts
.arch
== CPU_R4650
)
7203 as_bad (_("opcode not supported on this processor"));
7206 assert (mips_opts
.isa
== ISA_MIPS1
);
7207 /* Even on a big endian machine $fn comes before $fn+1. We have
7208 to adjust when storing to memory. */
7209 macro_build (&offset_expr
, "swc1", "T,o(b)",
7210 target_big_endian
? treg
+ 1 : treg
, BFD_RELOC_LO16
, breg
);
7211 offset_expr
.X_add_number
+= 4;
7212 macro_build (&offset_expr
, "swc1", "T,o(b)",
7213 target_big_endian
? treg
: treg
+ 1, BFD_RELOC_LO16
, breg
);
7218 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, treg
, BFD_RELOC_LO16
);
7220 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7223 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7224 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7229 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7231 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7236 as_warn (_("Instruction %s: result is always false"),
7238 move_register (dreg
, 0);
7241 if (imm_expr
.X_op
== O_constant
7242 && imm_expr
.X_add_number
>= 0
7243 && imm_expr
.X_add_number
< 0x10000)
7245 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7248 else if (imm_expr
.X_op
== O_constant
7249 && imm_expr
.X_add_number
> -0x8000
7250 && imm_expr
.X_add_number
< 0)
7252 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7253 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7254 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7259 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7260 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7263 macro_build (&expr1
, "sltiu", "t,r,j", dreg
, dreg
, BFD_RELOC_LO16
);
7268 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
7274 macro_build (NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
7275 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7278 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
7280 if (imm_expr
.X_op
== O_constant
7281 && imm_expr
.X_add_number
>= -0x8000
7282 && imm_expr
.X_add_number
< 0x8000)
7284 macro_build (&imm_expr
, mask
== M_SGE_I
? "slti" : "sltiu", "t,r,j",
7285 dreg
, sreg
, BFD_RELOC_LO16
);
7290 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7291 macro_build (NULL
, mask
== M_SGE_I
? "slt" : "sltu", "d,v,t",
7295 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7300 case M_SGT
: /* sreg > treg <==> treg < sreg */
7306 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7309 case M_SGT_I
: /* sreg > I <==> I < sreg */
7315 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7316 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7319 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7325 macro_build (NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
7326 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7329 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7335 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7336 macro_build (NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
7337 macro_build (&expr1
, "xori", "t,r,i", dreg
, dreg
, BFD_RELOC_LO16
);
7341 if (imm_expr
.X_op
== O_constant
7342 && imm_expr
.X_add_number
>= -0x8000
7343 && imm_expr
.X_add_number
< 0x8000)
7345 macro_build (&imm_expr
, "slti", "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7348 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7349 macro_build (NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
7353 if (imm_expr
.X_op
== O_constant
7354 && imm_expr
.X_add_number
>= -0x8000
7355 && imm_expr
.X_add_number
< 0x8000)
7357 macro_build (&imm_expr
, "sltiu", "t,r,j", dreg
, sreg
,
7361 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7362 macro_build (NULL
, "sltu", "d,v,t", dreg
, sreg
, AT
);
7367 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, treg
);
7369 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7372 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, treg
);
7373 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7378 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
7380 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, sreg
);
7385 as_warn (_("Instruction %s: result is always true"),
7387 macro_build (&expr1
, HAVE_32BIT_GPRS
? "addiu" : "daddiu", "t,r,j",
7388 dreg
, 0, BFD_RELOC_LO16
);
7391 if (imm_expr
.X_op
== O_constant
7392 && imm_expr
.X_add_number
>= 0
7393 && imm_expr
.X_add_number
< 0x10000)
7395 macro_build (&imm_expr
, "xori", "t,r,i", dreg
, sreg
, BFD_RELOC_LO16
);
7398 else if (imm_expr
.X_op
== O_constant
7399 && imm_expr
.X_add_number
> -0x8000
7400 && imm_expr
.X_add_number
< 0)
7402 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7403 macro_build (&imm_expr
, HAVE_32BIT_GPRS
? "addiu" : "daddiu",
7404 "t,r,j", dreg
, sreg
, BFD_RELOC_LO16
);
7409 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7410 macro_build (NULL
, "xor", "d,v,t", dreg
, sreg
, AT
);
7413 macro_build (NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
7421 if (imm_expr
.X_op
== O_constant
7422 && imm_expr
.X_add_number
> -0x8000
7423 && imm_expr
.X_add_number
<= 0x8000)
7425 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7426 macro_build (&imm_expr
, dbl
? "daddi" : "addi", "t,r,j",
7427 dreg
, sreg
, BFD_RELOC_LO16
);
7430 load_register (AT
, &imm_expr
, dbl
);
7431 macro_build (NULL
, dbl
? "dsub" : "sub", "d,v,t", dreg
, sreg
, AT
);
7437 if (imm_expr
.X_op
== O_constant
7438 && imm_expr
.X_add_number
> -0x8000
7439 && imm_expr
.X_add_number
<= 0x8000)
7441 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7442 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "t,r,j",
7443 dreg
, sreg
, BFD_RELOC_LO16
);
7446 load_register (AT
, &imm_expr
, dbl
);
7447 macro_build (NULL
, dbl
? "dsubu" : "subu", "d,v,t", dreg
, sreg
, AT
);
7468 load_register (AT
, &imm_expr
, HAVE_64BIT_GPRS
);
7469 macro_build (NULL
, s
, "s,t", sreg
, AT
);
7474 assert (mips_opts
.isa
== ISA_MIPS1
);
7475 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
7476 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
7479 * Is the double cfc1 instruction a bug in the mips assembler;
7480 * or is there a reason for it?
7482 mips_emit_delays (TRUE
);
7483 ++mips_opts
.noreorder
;
7484 mips_any_noreorder
= 1;
7485 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7486 macro_build (NULL
, "cfc1", "t,G", treg
, RA
);
7487 macro_build (NULL
, "nop", "");
7488 expr1
.X_add_number
= 3;
7489 macro_build (&expr1
, "ori", "t,r,i", AT
, treg
, BFD_RELOC_LO16
);
7490 expr1
.X_add_number
= 2;
7491 macro_build (&expr1
, "xori", "t,r,i", AT
, AT
, BFD_RELOC_LO16
);
7492 macro_build (NULL
, "ctc1", "t,G", AT
, RA
);
7493 macro_build (NULL
, "nop", "");
7494 macro_build (NULL
, mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S",
7496 macro_build (NULL
, "ctc1", "t,G", treg
, RA
);
7497 macro_build (NULL
, "nop", "");
7498 --mips_opts
.noreorder
;
7507 if (offset_expr
.X_add_number
>= 0x7fff)
7508 as_bad (_("operand overflow"));
7509 if (! target_big_endian
)
7510 ++offset_expr
.X_add_number
;
7511 macro_build (&offset_expr
, s
, "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7512 if (! target_big_endian
)
7513 --offset_expr
.X_add_number
;
7515 ++offset_expr
.X_add_number
;
7516 macro_build (&offset_expr
, "lbu", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7517 macro_build (NULL
, "sll", "d,w,<", AT
, AT
, 8);
7518 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7531 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7532 as_bad (_("operand overflow"));
7537 if (! target_big_endian
)
7538 offset_expr
.X_add_number
+= off
;
7539 macro_build (&offset_expr
, s
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7540 if (! target_big_endian
)
7541 offset_expr
.X_add_number
-= off
;
7543 offset_expr
.X_add_number
+= off
;
7544 macro_build (&offset_expr
, s2
, "t,o(b)", tempreg
, BFD_RELOC_LO16
, breg
);
7546 /* If necessary, move the result in tempreg the final destination. */
7547 if (treg
== tempreg
)
7549 /* Protect second load's delay slot. */
7550 if (!gpr_interlocks
)
7551 macro_build (NULL
, "nop", "");
7552 move_register (treg
, tempreg
);
7566 load_address (AT
, &offset_expr
, &used_at
);
7568 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7569 if (! target_big_endian
)
7570 expr1
.X_add_number
= off
;
7572 expr1
.X_add_number
= 0;
7573 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7574 if (! target_big_endian
)
7575 expr1
.X_add_number
= 0;
7577 expr1
.X_add_number
= off
;
7578 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7584 load_address (AT
, &offset_expr
, &used_at
);
7586 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7587 if (target_big_endian
)
7588 expr1
.X_add_number
= 0;
7589 macro_build (&expr1
, mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)",
7590 treg
, BFD_RELOC_LO16
, AT
);
7591 if (target_big_endian
)
7592 expr1
.X_add_number
= 1;
7594 expr1
.X_add_number
= 0;
7595 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7596 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7597 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7601 if (offset_expr
.X_add_number
>= 0x7fff)
7602 as_bad (_("operand overflow"));
7603 if (target_big_endian
)
7604 ++offset_expr
.X_add_number
;
7605 macro_build (&offset_expr
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7606 macro_build (NULL
, "srl", "d,w,<", AT
, treg
, 8);
7607 if (target_big_endian
)
7608 --offset_expr
.X_add_number
;
7610 ++offset_expr
.X_add_number
;
7611 macro_build (&offset_expr
, "sb", "t,o(b)", AT
, BFD_RELOC_LO16
, breg
);
7624 if (offset_expr
.X_add_number
>= 0x8000 - off
)
7625 as_bad (_("operand overflow"));
7626 if (! target_big_endian
)
7627 offset_expr
.X_add_number
+= off
;
7628 macro_build (&offset_expr
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7629 if (! target_big_endian
)
7630 offset_expr
.X_add_number
-= off
;
7632 offset_expr
.X_add_number
+= off
;
7633 macro_build (&offset_expr
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, breg
);
7647 load_address (AT
, &offset_expr
, &used_at
);
7649 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7650 if (! target_big_endian
)
7651 expr1
.X_add_number
= off
;
7653 expr1
.X_add_number
= 0;
7654 macro_build (&expr1
, s
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7655 if (! target_big_endian
)
7656 expr1
.X_add_number
= 0;
7658 expr1
.X_add_number
= off
;
7659 macro_build (&expr1
, s2
, "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7664 load_address (AT
, &offset_expr
, &used_at
);
7666 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", AT
, AT
, breg
);
7667 if (! target_big_endian
)
7668 expr1
.X_add_number
= 0;
7669 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7670 macro_build (NULL
, "srl", "d,w,<", treg
, treg
, 8);
7671 if (! target_big_endian
)
7672 expr1
.X_add_number
= 1;
7674 expr1
.X_add_number
= 0;
7675 macro_build (&expr1
, "sb", "t,o(b)", treg
, BFD_RELOC_LO16
, AT
);
7676 if (! target_big_endian
)
7677 expr1
.X_add_number
= 0;
7679 expr1
.X_add_number
= 1;
7680 macro_build (&expr1
, "lbu", "t,o(b)", AT
, BFD_RELOC_LO16
, AT
);
7681 macro_build (NULL
, "sll", "d,w,<", treg
, treg
, 8);
7682 macro_build (NULL
, "or", "d,v,t", treg
, treg
, AT
);
7686 /* FIXME: Check if this is one of the itbl macros, since they
7687 are added dynamically. */
7688 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
7692 as_warn (_("Macro used $at after \".set noat\""));
7695 /* Implement macros in mips16 mode. */
7698 mips16_macro (struct mips_cl_insn
*ip
)
7701 int xreg
, yreg
, zreg
, tmp
;
7704 const char *s
, *s2
, *s3
;
7706 mask
= ip
->insn_mo
->mask
;
7708 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
7709 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
7710 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
7712 expr1
.X_op
= O_constant
;
7713 expr1
.X_op_symbol
= NULL
;
7714 expr1
.X_add_symbol
= NULL
;
7715 expr1
.X_add_number
= 1;
7734 mips_emit_delays (TRUE
);
7735 ++mips_opts
.noreorder
;
7736 mips_any_noreorder
= 1;
7737 macro_build (NULL
, dbl
? "ddiv" : "div", "0,x,y", xreg
, yreg
);
7738 expr1
.X_add_number
= 2;
7739 macro_build (&expr1
, "bnez", "x,p", yreg
);
7740 macro_build (NULL
, "break", "6", 7);
7742 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7743 since that causes an overflow. We should do that as well,
7744 but I don't see how to do the comparisons without a temporary
7746 --mips_opts
.noreorder
;
7747 macro_build (NULL
, s
, "x", zreg
);
7766 mips_emit_delays (TRUE
);
7767 ++mips_opts
.noreorder
;
7768 mips_any_noreorder
= 1;
7769 macro_build (NULL
, s
, "0,x,y", xreg
, yreg
);
7770 expr1
.X_add_number
= 2;
7771 macro_build (&expr1
, "bnez", "x,p", yreg
);
7772 macro_build (NULL
, "break", "6", 7);
7773 --mips_opts
.noreorder
;
7774 macro_build (NULL
, s2
, "x", zreg
);
7780 macro_build (NULL
, dbl
? "dmultu" : "multu", "x,y", xreg
, yreg
);
7781 macro_build (NULL
, "mflo", "x", zreg
);
7789 if (imm_expr
.X_op
!= O_constant
)
7790 as_bad (_("Unsupported large constant"));
7791 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7792 macro_build (&imm_expr
, dbl
? "daddiu" : "addiu", "y,x,4", yreg
, xreg
);
7796 if (imm_expr
.X_op
!= O_constant
)
7797 as_bad (_("Unsupported large constant"));
7798 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7799 macro_build (&imm_expr
, "addiu", "x,k", xreg
);
7803 if (imm_expr
.X_op
!= O_constant
)
7804 as_bad (_("Unsupported large constant"));
7805 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
7806 macro_build (&imm_expr
, "daddiu", "y,j", yreg
);
7828 goto do_reverse_branch
;
7832 goto do_reverse_branch
;
7844 goto do_reverse_branch
;
7855 macro_build (NULL
, s
, "x,y", xreg
, yreg
);
7856 macro_build (&offset_expr
, s2
, "p");
7883 goto do_addone_branch_i
;
7888 goto do_addone_branch_i
;
7903 goto do_addone_branch_i
;
7910 if (imm_expr
.X_op
!= O_constant
)
7911 as_bad (_("Unsupported large constant"));
7912 ++imm_expr
.X_add_number
;
7915 macro_build (&imm_expr
, s
, s3
, xreg
);
7916 macro_build (&offset_expr
, s2
, "p");
7920 expr1
.X_add_number
= 0;
7921 macro_build (&expr1
, "slti", "x,8", yreg
);
7923 move_register (xreg
, yreg
);
7924 expr1
.X_add_number
= 2;
7925 macro_build (&expr1
, "bteqz", "p");
7926 macro_build (NULL
, "neg", "x,w", xreg
, xreg
);
7930 /* For consistency checking, verify that all bits are specified either
7931 by the match/mask part of the instruction definition, or by the
7934 validate_mips_insn (const struct mips_opcode
*opc
)
7936 const char *p
= opc
->args
;
7938 unsigned long used_bits
= opc
->mask
;
7940 if ((used_bits
& opc
->match
) != opc
->match
)
7942 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
7943 opc
->name
, opc
->args
);
7946 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7956 case 'A': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7957 case 'B': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7958 case 'C': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7959 case 'D': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
7960 USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7961 case 'E': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7962 case 'F': USE_BITS (OP_MASK_INSMSB
, OP_SH_INSMSB
); break;
7963 case 'G': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7964 case 'H': USE_BITS (OP_MASK_EXTMSBD
, OP_SH_EXTMSBD
); break;
7967 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7968 c
, opc
->name
, opc
->args
);
7972 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7973 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
7975 case 'B': USE_BITS (OP_MASK_CODE20
, OP_SH_CODE20
); break;
7976 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
7977 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7978 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
7980 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7981 case 'H': USE_BITS (OP_MASK_SEL
, OP_SH_SEL
); break;
7983 case 'J': USE_BITS (OP_MASK_CODE19
, OP_SH_CODE19
); break;
7984 case 'K': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
7986 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
7987 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
7988 case 'O': USE_BITS (OP_MASK_ALN
, OP_SH_ALN
); break;
7989 case 'Q': USE_BITS (OP_MASK_VSEL
, OP_SH_VSEL
);
7990 USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7991 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
7992 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7993 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7994 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7995 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7996 case 'X': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
7997 case 'Y': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
7998 case 'Z': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
7999 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
8000 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8001 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
8002 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
8004 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
8005 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8006 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8007 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
8009 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8010 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
8011 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
8012 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8013 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8014 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8015 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
8016 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
8017 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8020 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
8021 case 'U': USE_BITS (OP_MASK_RD
, OP_SH_RD
);
8022 USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
8023 case 'e': USE_BITS (OP_MASK_VECBYTE
, OP_SH_VECBYTE
); break;
8024 case '%': USE_BITS (OP_MASK_VECALIGN
, OP_SH_VECALIGN
); break;
8028 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8029 c
, opc
->name
, opc
->args
);
8033 if (used_bits
!= 0xffffffff)
8035 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8036 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
8042 /* This routine assembles an instruction into its binary format. As a
8043 side effect, it sets one of the global variables imm_reloc or
8044 offset_reloc to the type of relocation to do if one of the operands
8045 is an address expression. */
8048 mips_ip (char *str
, struct mips_cl_insn
*ip
)
8053 struct mips_opcode
*insn
;
8056 unsigned int lastregno
= 0;
8057 unsigned int lastpos
= 0;
8058 unsigned int limlo
, limhi
;
8064 /* If the instruction contains a '.', we first try to match an instruction
8065 including the '.'. Then we try again without the '.'. */
8067 for (s
= str
; *s
!= '\0' && !ISSPACE (*s
); ++s
)
8070 /* If we stopped on whitespace, then replace the whitespace with null for
8071 the call to hash_find. Save the character we replaced just in case we
8072 have to re-parse the instruction. */
8079 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
8081 /* If we didn't find the instruction in the opcode table, try again, but
8082 this time with just the instruction up to, but not including the
8086 /* Restore the character we overwrite above (if any). */
8090 /* Scan up to the first '.' or whitespace. */
8092 *s
!= '\0' && *s
!= '.' && !ISSPACE (*s
);
8096 /* If we did not find a '.', then we can quit now. */
8099 insn_error
= "unrecognized opcode";
8103 /* Lookup the instruction in the hash table. */
8105 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
8107 insn_error
= "unrecognized opcode";
8117 assert (strcmp (insn
->name
, str
) == 0);
8119 if (OPCODE_IS_MEMBER (insn
,
8121 | (file_ase_mips16
? INSN_MIPS16
: 0)
8122 | (mips_opts
.ase_mdmx
? INSN_MDMX
: 0)
8123 | (mips_opts
.ase_mips3d
? INSN_MIPS3D
: 0)),
8129 if (insn
->pinfo
!= INSN_MACRO
)
8131 if (mips_opts
.arch
== CPU_R4650
&& (insn
->pinfo
& FP_D
) != 0)
8137 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
8138 && strcmp (insn
->name
, insn
[1].name
) == 0)
8147 static char buf
[100];
8149 _("opcode not supported on this processor: %s (%s)"),
8150 mips_cpu_info_from_arch (mips_opts
.arch
)->name
,
8151 mips_cpu_info_from_isa (mips_opts
.isa
)->name
);
8161 ip
->insn_opcode
= insn
->match
;
8163 for (args
= insn
->args
;; ++args
)
8167 s
+= strspn (s
, " \t");
8171 case '\0': /* end of args */
8184 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8188 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8192 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8196 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8202 /* Handle optional base register.
8203 Either the base register is omitted or
8204 we must have a left paren. */
8205 /* This is dependent on the next operand specifier
8206 is a base register specification. */
8207 assert (args
[1] == 'b' || args
[1] == '5'
8208 || args
[1] == '-' || args
[1] == '4');
8212 case ')': /* these must match exactly */
8219 case '+': /* Opcode extension character. */
8222 case 'A': /* ins/ext position, becomes LSB. */
8231 my_getExpression (&imm_expr
, s
);
8232 check_absolute_expr (ip
, &imm_expr
);
8233 if ((unsigned long) imm_expr
.X_add_number
< limlo
8234 || (unsigned long) imm_expr
.X_add_number
> limhi
)
8236 as_bad (_("Improper position (%lu)"),
8237 (unsigned long) imm_expr
.X_add_number
);
8238 imm_expr
.X_add_number
= limlo
;
8240 lastpos
= imm_expr
.X_add_number
;
8241 ip
->insn_opcode
|= (imm_expr
.X_add_number
8242 & OP_MASK_SHAMT
) << OP_SH_SHAMT
;
8243 imm_expr
.X_op
= O_absent
;
8247 case 'B': /* ins size, becomes MSB. */
8256 my_getExpression (&imm_expr
, s
);
8257 check_absolute_expr (ip
, &imm_expr
);
8258 /* Check for negative input so that small negative numbers
8259 will not succeed incorrectly. The checks against
8260 (pos+size) transitively check "size" itself,
8261 assuming that "pos" is reasonable. */
8262 if ((long) imm_expr
.X_add_number
< 0
8263 || ((unsigned long) imm_expr
.X_add_number
8265 || ((unsigned long) imm_expr
.X_add_number
8268 as_bad (_("Improper insert size (%lu, position %lu)"),
8269 (unsigned long) imm_expr
.X_add_number
,
8270 (unsigned long) lastpos
);
8271 imm_expr
.X_add_number
= limlo
- lastpos
;
8273 ip
->insn_opcode
|= ((lastpos
+ imm_expr
.X_add_number
- 1)
8274 & OP_MASK_INSMSB
) << OP_SH_INSMSB
;
8275 imm_expr
.X_op
= O_absent
;
8279 case 'C': /* ext size, becomes MSBD. */
8292 my_getExpression (&imm_expr
, s
);
8293 check_absolute_expr (ip
, &imm_expr
);
8294 /* Check for negative input so that small negative numbers
8295 will not succeed incorrectly. The checks against
8296 (pos+size) transitively check "size" itself,
8297 assuming that "pos" is reasonable. */
8298 if ((long) imm_expr
.X_add_number
< 0
8299 || ((unsigned long) imm_expr
.X_add_number
8301 || ((unsigned long) imm_expr
.X_add_number
8304 as_bad (_("Improper extract size (%lu, position %lu)"),
8305 (unsigned long) imm_expr
.X_add_number
,
8306 (unsigned long) lastpos
);
8307 imm_expr
.X_add_number
= limlo
- lastpos
;
8309 ip
->insn_opcode
|= ((imm_expr
.X_add_number
- 1)
8310 & OP_MASK_EXTMSBD
) << OP_SH_EXTMSBD
;
8311 imm_expr
.X_op
= O_absent
;
8316 /* +D is for disassembly only; never match. */
8320 /* "+I" is like "I", except that imm2_expr is used. */
8321 my_getExpression (&imm2_expr
, s
);
8322 if (imm2_expr
.X_op
!= O_big
8323 && imm2_expr
.X_op
!= O_constant
)
8324 insn_error
= _("absolute expression required");
8325 normalize_constant_expr (&imm2_expr
);
8330 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8331 *args
, insn
->name
, insn
->args
);
8332 /* Further processing is fruitless. */
8337 case '<': /* must be at least one digit */
8339 * According to the manual, if the shift amount is greater
8340 * than 31 or less than 0, then the shift amount should be
8341 * mod 32. In reality the mips assembler issues an error.
8342 * We issue a warning and mask out all but the low 5 bits.
8344 my_getExpression (&imm_expr
, s
);
8345 check_absolute_expr (ip
, &imm_expr
);
8346 if ((unsigned long) imm_expr
.X_add_number
> 31)
8348 as_warn (_("Improper shift amount (%lu)"),
8349 (unsigned long) imm_expr
.X_add_number
);
8350 imm_expr
.X_add_number
&= OP_MASK_SHAMT
;
8352 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_SHAMT
;
8353 imm_expr
.X_op
= O_absent
;
8357 case '>': /* shift amount minus 32 */
8358 my_getExpression (&imm_expr
, s
);
8359 check_absolute_expr (ip
, &imm_expr
);
8360 if ((unsigned long) imm_expr
.X_add_number
< 32
8361 || (unsigned long) imm_expr
.X_add_number
> 63)
8363 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << OP_SH_SHAMT
;
8364 imm_expr
.X_op
= O_absent
;
8368 case 'k': /* cache code */
8369 case 'h': /* prefx code */
8370 my_getExpression (&imm_expr
, s
);
8371 check_absolute_expr (ip
, &imm_expr
);
8372 if ((unsigned long) imm_expr
.X_add_number
> 31)
8374 as_warn (_("Invalid value for `%s' (%lu)"),
8376 (unsigned long) imm_expr
.X_add_number
);
8377 imm_expr
.X_add_number
&= 0x1f;
8380 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
8382 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
8383 imm_expr
.X_op
= O_absent
;
8387 case 'c': /* break code */
8388 my_getExpression (&imm_expr
, s
);
8389 check_absolute_expr (ip
, &imm_expr
);
8390 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8392 as_warn (_("Illegal break code (%lu)"),
8393 (unsigned long) imm_expr
.X_add_number
);
8394 imm_expr
.X_add_number
&= OP_MASK_CODE
;
8396 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE
;
8397 imm_expr
.X_op
= O_absent
;
8401 case 'q': /* lower break code */
8402 my_getExpression (&imm_expr
, s
);
8403 check_absolute_expr (ip
, &imm_expr
);
8404 if ((unsigned long) imm_expr
.X_add_number
> 1023)
8406 as_warn (_("Illegal lower break code (%lu)"),
8407 (unsigned long) imm_expr
.X_add_number
);
8408 imm_expr
.X_add_number
&= OP_MASK_CODE2
;
8410 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE2
;
8411 imm_expr
.X_op
= O_absent
;
8415 case 'B': /* 20-bit syscall/break code. */
8416 my_getExpression (&imm_expr
, s
);
8417 check_absolute_expr (ip
, &imm_expr
);
8418 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE20
)
8419 as_warn (_("Illegal 20-bit code (%lu)"),
8420 (unsigned long) imm_expr
.X_add_number
);
8421 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE20
;
8422 imm_expr
.X_op
= O_absent
;
8426 case 'C': /* Coprocessor code */
8427 my_getExpression (&imm_expr
, s
);
8428 check_absolute_expr (ip
, &imm_expr
);
8429 if ((unsigned long) imm_expr
.X_add_number
>= (1 << 25))
8431 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8432 (unsigned long) imm_expr
.X_add_number
);
8433 imm_expr
.X_add_number
&= ((1 << 25) - 1);
8435 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8436 imm_expr
.X_op
= O_absent
;
8440 case 'J': /* 19-bit wait code. */
8441 my_getExpression (&imm_expr
, s
);
8442 check_absolute_expr (ip
, &imm_expr
);
8443 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_CODE19
)
8444 as_warn (_("Illegal 19-bit code (%lu)"),
8445 (unsigned long) imm_expr
.X_add_number
);
8446 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CODE19
;
8447 imm_expr
.X_op
= O_absent
;
8451 case 'P': /* Performance register */
8452 my_getExpression (&imm_expr
, s
);
8453 check_absolute_expr (ip
, &imm_expr
);
8454 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
8456 as_warn (_("Invalid performance register (%lu)"),
8457 (unsigned long) imm_expr
.X_add_number
);
8458 imm_expr
.X_add_number
&= OP_MASK_PERFREG
;
8460 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< OP_SH_PERFREG
);
8461 imm_expr
.X_op
= O_absent
;
8465 case 'b': /* base register */
8466 case 'd': /* destination register */
8467 case 's': /* source register */
8468 case 't': /* target register */
8469 case 'r': /* both target and source */
8470 case 'v': /* both dest and source */
8471 case 'w': /* both dest and target */
8472 case 'E': /* coprocessor target register */
8473 case 'G': /* coprocessor destination register */
8474 case 'K': /* 'rdhwr' destination register */
8475 case 'x': /* ignore register name */
8476 case 'z': /* must be zero register */
8477 case 'U': /* destination register (clo/clz). */
8492 while (ISDIGIT (*s
));
8494 as_bad (_("Invalid register number (%d)"), regno
);
8496 else if (*args
== 'E' || *args
== 'G' || *args
== 'K')
8500 if (s
[1] == 'r' && s
[2] == 'a')
8505 else if (s
[1] == 'f' && s
[2] == 'p')
8510 else if (s
[1] == 's' && s
[2] == 'p')
8515 else if (s
[1] == 'g' && s
[2] == 'p')
8520 else if (s
[1] == 'a' && s
[2] == 't')
8525 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8530 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8535 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
8540 else if (itbl_have_entries
)
8545 p
= s
+ 1; /* advance past '$' */
8546 n
= itbl_get_field (&p
); /* n is name */
8548 /* See if this is a register defined in an
8550 if (itbl_get_reg_val (n
, &r
))
8552 /* Get_field advances to the start of
8553 the next field, so we need to back
8554 rack to the end of the last field. */
8558 s
= strchr (s
, '\0');
8572 as_warn (_("Used $at without \".set noat\""));
8578 if (c
== 'r' || c
== 'v' || c
== 'w')
8585 /* 'z' only matches $0. */
8586 if (c
== 'z' && regno
!= 0)
8589 /* Now that we have assembled one operand, we use the args string
8590 * to figure out where it goes in the instruction. */
8597 ip
->insn_opcode
|= regno
<< OP_SH_RS
;
8602 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8605 ip
->insn_opcode
|= regno
<< OP_SH_RD
;
8606 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8611 ip
->insn_opcode
|= regno
<< OP_SH_RT
;
8614 /* This case exists because on the r3000 trunc
8615 expands into a macro which requires a gp
8616 register. On the r6000 or r4000 it is
8617 assembled into a single instruction which
8618 ignores the register. Thus the insn version
8619 is MIPS_ISA2 and uses 'x', and the macro
8620 version is MIPS_ISA1 and uses 't'. */
8623 /* This case is for the div instruction, which
8624 acts differently if the destination argument
8625 is $0. This only matches $0, and is checked
8626 outside the switch. */
8629 /* Itbl operand; not yet implemented. FIXME ?? */
8631 /* What about all other operands like 'i', which
8632 can be specified in the opcode table? */
8642 ip
->insn_opcode
|= lastregno
<< OP_SH_RS
;
8645 ip
->insn_opcode
|= lastregno
<< OP_SH_RT
;
8650 case 'O': /* MDMX alignment immediate constant. */
8651 my_getExpression (&imm_expr
, s
);
8652 check_absolute_expr (ip
, &imm_expr
);
8653 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_ALN
)
8655 as_warn ("Improper align amount (%ld), using low bits",
8656 (long) imm_expr
.X_add_number
);
8657 imm_expr
.X_add_number
&= OP_MASK_ALN
;
8659 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_ALN
;
8660 imm_expr
.X_op
= O_absent
;
8664 case 'Q': /* MDMX vector, element sel, or const. */
8667 /* MDMX Immediate. */
8668 my_getExpression (&imm_expr
, s
);
8669 check_absolute_expr (ip
, &imm_expr
);
8670 if ((unsigned long) imm_expr
.X_add_number
> OP_MASK_FT
)
8672 as_warn (_("Invalid MDMX Immediate (%ld)"),
8673 (long) imm_expr
.X_add_number
);
8674 imm_expr
.X_add_number
&= OP_MASK_FT
;
8676 imm_expr
.X_add_number
&= OP_MASK_FT
;
8677 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8678 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_QH
<< OP_SH_VSEL
;
8680 ip
->insn_opcode
|= MDMX_FMTSEL_IMM_OB
<< OP_SH_VSEL
;
8681 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_FT
;
8682 imm_expr
.X_op
= O_absent
;
8686 /* Not MDMX Immediate. Fall through. */
8687 case 'X': /* MDMX destination register. */
8688 case 'Y': /* MDMX source register. */
8689 case 'Z': /* MDMX target register. */
8691 case 'D': /* floating point destination register */
8692 case 'S': /* floating point source register */
8693 case 'T': /* floating point target register */
8694 case 'R': /* floating point source register */
8698 /* Accept $fN for FP and MDMX register numbers, and in
8699 addition accept $vN for MDMX register numbers. */
8700 if ((s
[0] == '$' && s
[1] == 'f' && ISDIGIT (s
[2]))
8701 || (is_mdmx
!= 0 && s
[0] == '$' && s
[1] == 'v'
8712 while (ISDIGIT (*s
));
8715 as_bad (_("Invalid float register number (%d)"), regno
);
8717 if ((regno
& 1) != 0
8719 && ! (strcmp (str
, "mtc1") == 0
8720 || strcmp (str
, "mfc1") == 0
8721 || strcmp (str
, "lwc1") == 0
8722 || strcmp (str
, "swc1") == 0
8723 || strcmp (str
, "l.s") == 0
8724 || strcmp (str
, "s.s") == 0))
8725 as_warn (_("Float register should be even, was %d"),
8733 if (c
== 'V' || c
== 'W')
8744 ip
->insn_opcode
|= regno
<< OP_SH_FD
;
8749 ip
->insn_opcode
|= regno
<< OP_SH_FS
;
8752 /* This is like 'Z', but also needs to fix the MDMX
8753 vector/scalar select bits. Note that the
8754 scalar immediate case is handled above. */
8757 int is_qh
= (ip
->insn_opcode
& (1 << OP_SH_VSEL
));
8758 int max_el
= (is_qh
? 3 : 7);
8760 my_getExpression(&imm_expr
, s
);
8761 check_absolute_expr (ip
, &imm_expr
);
8763 if (imm_expr
.X_add_number
> max_el
)
8764 as_bad(_("Bad element selector %ld"),
8765 (long) imm_expr
.X_add_number
);
8766 imm_expr
.X_add_number
&= max_el
;
8767 ip
->insn_opcode
|= (imm_expr
.X_add_number
8771 as_warn(_("Expecting ']' found '%s'"), s
);
8777 if (ip
->insn_opcode
& (OP_MASK_VSEL
<< OP_SH_VSEL
))
8778 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_QH
8781 ip
->insn_opcode
|= (MDMX_FMTSEL_VEC_OB
<<
8788 ip
->insn_opcode
|= regno
<< OP_SH_FT
;
8791 ip
->insn_opcode
|= regno
<< OP_SH_FR
;
8801 ip
->insn_opcode
|= lastregno
<< OP_SH_FS
;
8804 ip
->insn_opcode
|= lastregno
<< OP_SH_FT
;
8810 my_getExpression (&imm_expr
, s
);
8811 if (imm_expr
.X_op
!= O_big
8812 && imm_expr
.X_op
!= O_constant
)
8813 insn_error
= _("absolute expression required");
8814 normalize_constant_expr (&imm_expr
);
8819 my_getExpression (&offset_expr
, s
);
8820 *imm_reloc
= BFD_RELOC_32
;
8833 unsigned char temp
[8];
8835 unsigned int length
;
8840 /* These only appear as the last operand in an
8841 instruction, and every instruction that accepts
8842 them in any variant accepts them in all variants.
8843 This means we don't have to worry about backing out
8844 any changes if the instruction does not match.
8846 The difference between them is the size of the
8847 floating point constant and where it goes. For 'F'
8848 and 'L' the constant is 64 bits; for 'f' and 'l' it
8849 is 32 bits. Where the constant is placed is based
8850 on how the MIPS assembler does things:
8853 f -- immediate value
8856 The .lit4 and .lit8 sections are only used if
8857 permitted by the -G argument.
8859 When generating embedded PIC code, we use the
8860 .lit8 section but not the .lit4 section (we can do
8861 .lit4 inline easily; we need to put .lit8
8862 somewhere in the data segment, and using .lit8
8863 permits the linker to eventually combine identical
8866 The code below needs to know whether the target register
8867 is 32 or 64 bits wide. It relies on the fact 'f' and
8868 'F' are used with GPR-based instructions and 'l' and
8869 'L' are used with FPR-based instructions. */
8871 f64
= *args
== 'F' || *args
== 'L';
8872 using_gprs
= *args
== 'F' || *args
== 'f';
8874 save_in
= input_line_pointer
;
8875 input_line_pointer
= s
;
8876 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
8878 s
= input_line_pointer
;
8879 input_line_pointer
= save_in
;
8880 if (err
!= NULL
&& *err
!= '\0')
8882 as_bad (_("Bad floating point constant: %s"), err
);
8883 memset (temp
, '\0', sizeof temp
);
8884 length
= f64
? 8 : 4;
8887 assert (length
== (unsigned) (f64
? 8 : 4));
8891 && (! USE_GLOBAL_POINTER_OPT
8892 || mips_pic
== EMBEDDED_PIC
8893 || g_switch_value
< 4
8894 || (temp
[0] == 0 && temp
[1] == 0)
8895 || (temp
[2] == 0 && temp
[3] == 0))))
8897 imm_expr
.X_op
= O_constant
;
8898 if (! target_big_endian
)
8899 imm_expr
.X_add_number
= bfd_getl32 (temp
);
8901 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8904 && ! mips_disable_float_construction
8905 /* Constants can only be constructed in GPRs and
8906 copied to FPRs if the GPRs are at least as wide
8907 as the FPRs. Force the constant into memory if
8908 we are using 64-bit FPRs but the GPRs are only
8911 || ! (HAVE_64BIT_FPRS
&& HAVE_32BIT_GPRS
))
8912 && ((temp
[0] == 0 && temp
[1] == 0)
8913 || (temp
[2] == 0 && temp
[3] == 0))
8914 && ((temp
[4] == 0 && temp
[5] == 0)
8915 || (temp
[6] == 0 && temp
[7] == 0)))
8917 /* The value is simple enough to load with a couple of
8918 instructions. If using 32-bit registers, set
8919 imm_expr to the high order 32 bits and offset_expr to
8920 the low order 32 bits. Otherwise, set imm_expr to
8921 the entire 64 bit constant. */
8922 if (using_gprs
? HAVE_32BIT_GPRS
: HAVE_32BIT_FPRS
)
8924 imm_expr
.X_op
= O_constant
;
8925 offset_expr
.X_op
= O_constant
;
8926 if (! target_big_endian
)
8928 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
8929 offset_expr
.X_add_number
= bfd_getl32 (temp
);
8933 imm_expr
.X_add_number
= bfd_getb32 (temp
);
8934 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
8936 if (offset_expr
.X_add_number
== 0)
8937 offset_expr
.X_op
= O_absent
;
8939 else if (sizeof (imm_expr
.X_add_number
) > 4)
8941 imm_expr
.X_op
= O_constant
;
8942 if (! target_big_endian
)
8943 imm_expr
.X_add_number
= bfd_getl64 (temp
);
8945 imm_expr
.X_add_number
= bfd_getb64 (temp
);
8949 imm_expr
.X_op
= O_big
;
8950 imm_expr
.X_add_number
= 4;
8951 if (! target_big_endian
)
8953 generic_bignum
[0] = bfd_getl16 (temp
);
8954 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
8955 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
8956 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
8960 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
8961 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
8962 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
8963 generic_bignum
[3] = bfd_getb16 (temp
);
8969 const char *newname
;
8972 /* Switch to the right section. */
8974 subseg
= now_subseg
;
8977 default: /* unused default case avoids warnings. */
8979 newname
= RDATA_SECTION_NAME
;
8980 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
8981 || mips_pic
== EMBEDDED_PIC
)
8985 if (mips_pic
== EMBEDDED_PIC
)
8988 newname
= RDATA_SECTION_NAME
;
8991 assert (!USE_GLOBAL_POINTER_OPT
8992 || g_switch_value
>= 4);
8996 new_seg
= subseg_new (newname
, (subsegT
) 0);
8997 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8998 bfd_set_section_flags (stdoutput
, new_seg
,
9003 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
9004 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9005 && strcmp (TARGET_OS
, "elf") != 0)
9006 record_alignment (new_seg
, 4);
9008 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
9010 as_bad (_("Can't use floating point insn in this section"));
9012 /* Set the argument to the current address in the
9014 offset_expr
.X_op
= O_symbol
;
9015 offset_expr
.X_add_symbol
=
9016 symbol_new ("L0\001", now_seg
,
9017 (valueT
) frag_now_fix (), frag_now
);
9018 offset_expr
.X_add_number
= 0;
9020 /* Put the floating point number into the section. */
9021 p
= frag_more ((int) length
);
9022 memcpy (p
, temp
, length
);
9024 /* Switch back to the original section. */
9025 subseg_set (seg
, subseg
);
9030 case 'i': /* 16 bit unsigned immediate */
9031 case 'j': /* 16 bit signed immediate */
9032 *imm_reloc
= BFD_RELOC_LO16
;
9033 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0)
9036 offsetT minval
, maxval
;
9038 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
9039 && strcmp (insn
->name
, insn
[1].name
) == 0);
9041 /* If the expression was written as an unsigned number,
9042 only treat it as signed if there are no more
9046 && sizeof (imm_expr
.X_add_number
) <= 4
9047 && imm_expr
.X_op
== O_constant
9048 && imm_expr
.X_add_number
< 0
9049 && imm_expr
.X_unsigned
9053 /* For compatibility with older assemblers, we accept
9054 0x8000-0xffff as signed 16-bit numbers when only
9055 signed numbers are allowed. */
9057 minval
= 0, maxval
= 0xffff;
9059 minval
= -0x8000, maxval
= 0x7fff;
9061 minval
= -0x8000, maxval
= 0xffff;
9063 if (imm_expr
.X_op
!= O_constant
9064 || imm_expr
.X_add_number
< minval
9065 || imm_expr
.X_add_number
> maxval
)
9069 if (imm_expr
.X_op
== O_constant
9070 || imm_expr
.X_op
== O_big
)
9071 as_bad (_("expression out of range"));
9077 case 'o': /* 16 bit offset */
9078 /* Check whether there is only a single bracketed expression
9079 left. If so, it must be the base register and the
9080 constant must be zero. */
9081 if (*s
== '(' && strchr (s
+ 1, '(') == 0)
9083 offset_expr
.X_op
= O_constant
;
9084 offset_expr
.X_add_number
= 0;
9088 /* If this value won't fit into a 16 bit offset, then go
9089 find a macro that will generate the 32 bit offset
9091 if (my_getSmallExpression (&offset_expr
, offset_reloc
, s
) == 0
9092 && (offset_expr
.X_op
!= O_constant
9093 || offset_expr
.X_add_number
>= 0x8000
9094 || offset_expr
.X_add_number
< -0x8000))
9100 case 'p': /* pc relative offset */
9101 *offset_reloc
= BFD_RELOC_16_PCREL_S2
;
9102 my_getExpression (&offset_expr
, s
);
9106 case 'u': /* upper 16 bits */
9107 if (my_getSmallExpression (&imm_expr
, imm_reloc
, s
) == 0
9108 && imm_expr
.X_op
== O_constant
9109 && (imm_expr
.X_add_number
< 0
9110 || imm_expr
.X_add_number
>= 0x10000))
9111 as_bad (_("lui expression not in range 0..65535"));
9115 case 'a': /* 26 bit address */
9116 my_getExpression (&offset_expr
, s
);
9118 *offset_reloc
= BFD_RELOC_MIPS_JMP
;
9121 case 'N': /* 3 bit branch condition code */
9122 case 'M': /* 3 bit compare condition code */
9123 if (strncmp (s
, "$fcc", 4) != 0)
9133 while (ISDIGIT (*s
));
9135 as_bad (_("Invalid condition code register $fcc%d"), regno
);
9136 if ((strcmp(str
+ strlen(str
) - 3, ".ps") == 0
9137 || strcmp(str
+ strlen(str
) - 5, "any2f") == 0
9138 || strcmp(str
+ strlen(str
) - 5, "any2t") == 0)
9139 && (regno
& 1) != 0)
9140 as_warn(_("Condition code register should be even for %s, was %d"),
9142 if ((strcmp(str
+ strlen(str
) - 5, "any4f") == 0
9143 || strcmp(str
+ strlen(str
) - 5, "any4t") == 0)
9144 && (regno
& 3) != 0)
9145 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9148 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
9150 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
9154 if (s
[0] == '0' && (s
[1] == 'x' || s
[1] == 'X'))
9165 while (ISDIGIT (*s
));
9168 c
= 8; /* Invalid sel value. */
9171 as_bad (_("invalid coprocessor sub-selection value (0-7)"));
9172 ip
->insn_opcode
|= c
;
9176 /* Must be at least one digit. */
9177 my_getExpression (&imm_expr
, s
);
9178 check_absolute_expr (ip
, &imm_expr
);
9180 if ((unsigned long) imm_expr
.X_add_number
9181 > (unsigned long) OP_MASK_VECBYTE
)
9183 as_bad (_("bad byte vector index (%ld)"),
9184 (long) imm_expr
.X_add_number
);
9185 imm_expr
.X_add_number
= 0;
9188 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECBYTE
;
9189 imm_expr
.X_op
= O_absent
;
9194 my_getExpression (&imm_expr
, s
);
9195 check_absolute_expr (ip
, &imm_expr
);
9197 if ((unsigned long) imm_expr
.X_add_number
9198 > (unsigned long) OP_MASK_VECALIGN
)
9200 as_bad (_("bad byte vector index (%ld)"),
9201 (long) imm_expr
.X_add_number
);
9202 imm_expr
.X_add_number
= 0;
9205 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_VECALIGN
;
9206 imm_expr
.X_op
= O_absent
;
9211 as_bad (_("bad char = '%c'\n"), *args
);
9216 /* Args don't match. */
9217 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
9218 !strcmp (insn
->name
, insn
[1].name
))
9222 insn_error
= _("illegal operands");
9227 insn_error
= _("illegal operands");
9232 /* This routine assembles an instruction into its binary format when
9233 assembling for the mips16. As a side effect, it sets one of the
9234 global variables imm_reloc or offset_reloc to the type of
9235 relocation to do if one of the operands is an address expression.
9236 It also sets mips16_small and mips16_ext if the user explicitly
9237 requested a small or extended instruction. */
9240 mips16_ip (char *str
, struct mips_cl_insn
*ip
)
9244 struct mips_opcode
*insn
;
9247 unsigned int lastregno
= 0;
9252 mips16_small
= FALSE
;
9255 for (s
= str
; ISLOWER (*s
); ++s
)
9267 if (s
[1] == 't' && s
[2] == ' ')
9270 mips16_small
= TRUE
;
9274 else if (s
[1] == 'e' && s
[2] == ' ')
9283 insn_error
= _("unknown opcode");
9287 if (mips_opts
.noautoextend
&& ! mips16_ext
)
9288 mips16_small
= TRUE
;
9290 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
9292 insn_error
= _("unrecognized opcode");
9299 assert (strcmp (insn
->name
, str
) == 0);
9302 ip
->insn_opcode
= insn
->match
;
9303 ip
->use_extend
= FALSE
;
9304 imm_expr
.X_op
= O_absent
;
9305 imm_reloc
[0] = BFD_RELOC_UNUSED
;
9306 imm_reloc
[1] = BFD_RELOC_UNUSED
;
9307 imm_reloc
[2] = BFD_RELOC_UNUSED
;
9308 imm2_expr
.X_op
= O_absent
;
9309 offset_expr
.X_op
= O_absent
;
9310 offset_reloc
[0] = BFD_RELOC_UNUSED
;
9311 offset_reloc
[1] = BFD_RELOC_UNUSED
;
9312 offset_reloc
[2] = BFD_RELOC_UNUSED
;
9313 for (args
= insn
->args
; 1; ++args
)
9320 /* In this switch statement we call break if we did not find
9321 a match, continue if we did find a match, or return if we
9330 /* Stuff the immediate value in now, if we can. */
9331 if (imm_expr
.X_op
== O_constant
9332 && *imm_reloc
> BFD_RELOC_UNUSED
9333 && insn
->pinfo
!= INSN_MACRO
)
9335 mips16_immed (NULL
, 0, *imm_reloc
- BFD_RELOC_UNUSED
,
9336 imm_expr
.X_add_number
, TRUE
, mips16_small
,
9337 mips16_ext
, &ip
->insn_opcode
,
9338 &ip
->use_extend
, &ip
->extend
);
9339 imm_expr
.X_op
= O_absent
;
9340 *imm_reloc
= BFD_RELOC_UNUSED
;
9354 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9357 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9373 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
9375 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
9402 while (ISDIGIT (*s
));
9405 as_bad (_("invalid register number (%d)"), regno
);
9411 if (s
[1] == 'r' && s
[2] == 'a')
9416 else if (s
[1] == 'f' && s
[2] == 'p')
9421 else if (s
[1] == 's' && s
[2] == 'p')
9426 else if (s
[1] == 'g' && s
[2] == 'p')
9431 else if (s
[1] == 'a' && s
[2] == 't')
9436 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
9441 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
9446 else if (s
[1] == 'z' && s
[2] == 'e' && s
[3] == 'r' && s
[4] == 'o')
9459 if (c
== 'v' || c
== 'w')
9461 regno
= mips16_to_32_reg_map
[lastregno
];
9475 regno
= mips32_to_16_reg_map
[regno
];
9480 regno
= ILLEGAL_REG
;
9485 regno
= ILLEGAL_REG
;
9490 regno
= ILLEGAL_REG
;
9495 if (regno
== AT
&& ! mips_opts
.noat
)
9496 as_warn (_("used $at without \".set noat\""));
9503 if (regno
== ILLEGAL_REG
)
9510 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
9514 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
9517 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
9520 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
9526 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
9529 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
9530 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
9540 if (strncmp (s
, "$pc", 3) == 0)
9564 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
9566 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9567 and generate the appropriate reloc. If the text
9568 inside %gprel is not a symbol name with an
9569 optional offset, then we generate a normal reloc
9570 and will probably fail later. */
9571 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
9572 if (imm_expr
.X_op
== O_symbol
)
9575 *imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
9577 ip
->use_extend
= TRUE
;
9584 /* Just pick up a normal expression. */
9585 my_getExpression (&imm_expr
, s
);
9588 if (imm_expr
.X_op
== O_register
)
9590 /* What we thought was an expression turned out to
9593 if (s
[0] == '(' && args
[1] == '(')
9595 /* It looks like the expression was omitted
9596 before a register indirection, which means
9597 that the expression is implicitly zero. We
9598 still set up imm_expr, so that we handle
9599 explicit extensions correctly. */
9600 imm_expr
.X_op
= O_constant
;
9601 imm_expr
.X_add_number
= 0;
9602 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9609 /* We need to relax this instruction. */
9610 *imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9619 /* We use offset_reloc rather than imm_reloc for the PC
9620 relative operands. This lets macros with both
9621 immediate and address operands work correctly. */
9622 my_getExpression (&offset_expr
, s
);
9624 if (offset_expr
.X_op
== O_register
)
9627 /* We need to relax this instruction. */
9628 *offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
9632 case '6': /* break code */
9633 my_getExpression (&imm_expr
, s
);
9634 check_absolute_expr (ip
, &imm_expr
);
9635 if ((unsigned long) imm_expr
.X_add_number
> 63)
9637 as_warn (_("Invalid value for `%s' (%lu)"),
9639 (unsigned long) imm_expr
.X_add_number
);
9640 imm_expr
.X_add_number
&= 0x3f;
9642 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
9643 imm_expr
.X_op
= O_absent
;
9647 case 'a': /* 26 bit address */
9648 my_getExpression (&offset_expr
, s
);
9650 *offset_reloc
= BFD_RELOC_MIPS16_JMP
;
9651 ip
->insn_opcode
<<= 16;
9654 case 'l': /* register list for entry macro */
9655 case 'L': /* register list for exit macro */
9665 int freg
, reg1
, reg2
;
9667 while (*s
== ' ' || *s
== ',')
9671 as_bad (_("can't parse register list"));
9683 while (ISDIGIT (*s
))
9705 as_bad (_("invalid register list"));
9710 while (ISDIGIT (*s
))
9717 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
9722 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
9727 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
9728 mask
|= (reg2
- 3) << 3;
9729 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
9730 mask
|= (reg2
- 15) << 1;
9731 else if (reg1
== RA
&& reg2
== RA
)
9735 as_bad (_("invalid register list"));
9739 /* The mask is filled in in the opcode table for the
9740 benefit of the disassembler. We remove it before
9741 applying the actual mask. */
9742 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
9743 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
9747 case 'e': /* extend code */
9748 my_getExpression (&imm_expr
, s
);
9749 check_absolute_expr (ip
, &imm_expr
);
9750 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
9752 as_warn (_("Invalid value for `%s' (%lu)"),
9754 (unsigned long) imm_expr
.X_add_number
);
9755 imm_expr
.X_add_number
&= 0x7ff;
9757 ip
->insn_opcode
|= imm_expr
.X_add_number
;
9758 imm_expr
.X_op
= O_absent
;
9768 /* Args don't match. */
9769 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
9770 strcmp (insn
->name
, insn
[1].name
) == 0)
9777 insn_error
= _("illegal operands");
9783 /* This structure holds information we know about a mips16 immediate
9786 struct mips16_immed_operand
9788 /* The type code used in the argument string in the opcode table. */
9790 /* The number of bits in the short form of the opcode. */
9792 /* The number of bits in the extended form of the opcode. */
9794 /* The amount by which the short form is shifted when it is used;
9795 for example, the sw instruction has a shift count of 2. */
9797 /* The amount by which the short form is shifted when it is stored
9798 into the instruction code. */
9800 /* Non-zero if the short form is unsigned. */
9802 /* Non-zero if the extended form is unsigned. */
9804 /* Non-zero if the value is PC relative. */
9808 /* The mips16 immediate operand types. */
9810 static const struct mips16_immed_operand mips16_immed_operands
[] =
9812 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9813 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9814 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
9815 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
9816 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
9817 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9818 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9819 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9820 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
9821 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
9822 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9823 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9824 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
9825 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
9826 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9827 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
9828 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9829 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
9830 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
9831 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
9832 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
9835 #define MIPS16_NUM_IMMED \
9836 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
9838 /* Handle a mips16 instruction with an immediate value. This or's the
9839 small immediate value into *INSN. It sets *USE_EXTEND to indicate
9840 whether an extended value is needed; if one is needed, it sets
9841 *EXTEND to the value. The argument type is TYPE. The value is VAL.
9842 If SMALL is true, an unextended opcode was explicitly requested.
9843 If EXT is true, an extended opcode was explicitly requested. If
9844 WARN is true, warn if EXT does not match reality. */
9847 mips16_immed (char *file
, unsigned int line
, int type
, offsetT val
,
9848 bfd_boolean warn
, bfd_boolean small
, bfd_boolean ext
,
9849 unsigned long *insn
, bfd_boolean
*use_extend
,
9850 unsigned short *extend
)
9852 register const struct mips16_immed_operand
*op
;
9853 int mintiny
, maxtiny
;
9854 bfd_boolean needext
;
9856 op
= mips16_immed_operands
;
9857 while (op
->type
!= type
)
9860 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9865 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9868 maxtiny
= 1 << op
->nbits
;
9873 maxtiny
= (1 << op
->nbits
) - 1;
9878 mintiny
= - (1 << (op
->nbits
- 1));
9879 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9882 /* Branch offsets have an implicit 0 in the lowest bit. */
9883 if (type
== 'p' || type
== 'q')
9886 if ((val
& ((1 << op
->shift
) - 1)) != 0
9887 || val
< (mintiny
<< op
->shift
)
9888 || val
> (maxtiny
<< op
->shift
))
9893 if (warn
&& ext
&& ! needext
)
9894 as_warn_where (file
, line
,
9895 _("extended operand requested but not required"));
9896 if (small
&& needext
)
9897 as_bad_where (file
, line
, _("invalid unextended operand value"));
9899 if (small
|| (! ext
&& ! needext
))
9903 *use_extend
= FALSE
;
9904 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
9905 insnval
<<= op
->op_shift
;
9910 long minext
, maxext
;
9916 maxext
= (1 << op
->extbits
) - 1;
9920 minext
= - (1 << (op
->extbits
- 1));
9921 maxext
= (1 << (op
->extbits
- 1)) - 1;
9923 if (val
< minext
|| val
> maxext
)
9924 as_bad_where (file
, line
,
9925 _("operand value out of range for instruction"));
9928 if (op
->extbits
== 16)
9930 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
9933 else if (op
->extbits
== 15)
9935 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
9940 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
9944 *extend
= (unsigned short) extval
;
9949 static const struct percent_op_match
9952 bfd_reloc_code_real_type reloc
;
9955 {"%lo", BFD_RELOC_LO16
},
9957 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16
},
9958 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16
},
9959 {"%call16", BFD_RELOC_MIPS_CALL16
},
9960 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP
},
9961 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE
},
9962 {"%got_ofst", BFD_RELOC_MIPS_GOT_OFST
},
9963 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16
},
9964 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16
},
9965 {"%got", BFD_RELOC_MIPS_GOT16
},
9966 {"%gp_rel", BFD_RELOC_GPREL16
},
9967 {"%half", BFD_RELOC_16
},
9968 {"%highest", BFD_RELOC_MIPS_HIGHEST
},
9969 {"%higher", BFD_RELOC_MIPS_HIGHER
},
9970 {"%neg", BFD_RELOC_MIPS_SUB
},
9972 {"%hi", BFD_RELOC_HI16_S
}
9976 /* Return true if *STR points to a relocation operator. When returning true,
9977 move *STR over the operator and store its relocation code in *RELOC.
9978 Leave both *STR and *RELOC alone when returning false. */
9981 parse_relocation (char **str
, bfd_reloc_code_real_type
*reloc
)
9985 for (i
= 0; i
< ARRAY_SIZE (percent_op
); i
++)
9986 if (strncasecmp (*str
, percent_op
[i
].str
, strlen (percent_op
[i
].str
)) == 0)
9988 *str
+= strlen (percent_op
[i
].str
);
9989 *reloc
= percent_op
[i
].reloc
;
9991 /* Check whether the output BFD supports this relocation.
9992 If not, issue an error and fall back on something safe. */
9993 if (!bfd_reloc_type_lookup (stdoutput
, percent_op
[i
].reloc
))
9995 as_bad ("relocation %s isn't supported by the current ABI",
9997 *reloc
= BFD_RELOC_LO16
;
10005 /* Parse string STR as a 16-bit relocatable operand. Store the
10006 expression in *EP and the relocations in the array starting
10007 at RELOC. Return the number of relocation operators used.
10009 On exit, EXPR_END points to the first character after the expression.
10010 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10013 my_getSmallExpression (expressionS
*ep
, bfd_reloc_code_real_type
*reloc
,
10016 bfd_reloc_code_real_type reversed_reloc
[3];
10017 size_t reloc_index
, i
;
10018 int crux_depth
, str_depth
;
10021 /* Search for the start of the main expression, recoding relocations
10022 in REVERSED_RELOC. End the loop with CRUX pointing to the start
10023 of the main expression and with CRUX_DEPTH containing the number
10024 of open brackets at that point. */
10031 crux_depth
= str_depth
;
10033 /* Skip over whitespace and brackets, keeping count of the number
10035 while (*str
== ' ' || *str
== '\t' || *str
== '(')
10040 && reloc_index
< (HAVE_NEWABI
? 3 : 1)
10041 && parse_relocation (&str
, &reversed_reloc
[reloc_index
]));
10043 my_getExpression (ep
, crux
);
10046 /* Match every open bracket. */
10047 while (crux_depth
> 0 && (*str
== ')' || *str
== ' ' || *str
== '\t'))
10051 if (crux_depth
> 0)
10052 as_bad ("unclosed '('");
10056 if (reloc_index
== 0)
10057 reloc
[0] = BFD_RELOC_LO16
;
10060 prev_reloc_op_frag
= frag_now
;
10061 for (i
= 0; i
< reloc_index
; i
++)
10062 reloc
[i
] = reversed_reloc
[reloc_index
- 1 - i
];
10065 return reloc_index
;
10069 my_getExpression (expressionS
*ep
, char *str
)
10074 save_in
= input_line_pointer
;
10075 input_line_pointer
= str
;
10077 expr_end
= input_line_pointer
;
10078 input_line_pointer
= save_in
;
10080 /* If we are in mips16 mode, and this is an expression based on `.',
10081 then we bump the value of the symbol by 1 since that is how other
10082 text symbols are handled. We don't bother to handle complex
10083 expressions, just `.' plus or minus a constant. */
10084 if (mips_opts
.mips16
10085 && ep
->X_op
== O_symbol
10086 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
10087 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
10088 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
10089 && symbol_constant_p (ep
->X_add_symbol
)
10090 && (val
= S_GET_VALUE (ep
->X_add_symbol
)) == frag_now_fix ())
10091 S_SET_VALUE (ep
->X_add_symbol
, val
+ 1);
10094 /* Turn a string in input_line_pointer into a floating point constant
10095 of type TYPE, and store the appropriate bytes in *LITP. The number
10096 of LITTLENUMS emitted is stored in *SIZEP. An error message is
10097 returned, or NULL on OK. */
10100 md_atof (int type
, char *litP
, int *sizeP
)
10103 LITTLENUM_TYPE words
[4];
10119 return _("bad call to md_atof");
10122 t
= atof_ieee (input_line_pointer
, type
, words
);
10124 input_line_pointer
= t
;
10128 if (! target_big_endian
)
10130 for (i
= prec
- 1; i
>= 0; i
--)
10132 md_number_to_chars (litP
, words
[i
], 2);
10138 for (i
= 0; i
< prec
; i
++)
10140 md_number_to_chars (litP
, words
[i
], 2);
10149 md_number_to_chars (char *buf
, valueT val
, int n
)
10151 if (target_big_endian
)
10152 number_to_chars_bigendian (buf
, val
, n
);
10154 number_to_chars_littleendian (buf
, val
, n
);
10158 static int support_64bit_objects(void)
10160 const char **list
, **l
;
10163 list
= bfd_target_list ();
10164 for (l
= list
; *l
!= NULL
; l
++)
10166 /* This is traditional mips */
10167 if (strcmp (*l
, "elf64-tradbigmips") == 0
10168 || strcmp (*l
, "elf64-tradlittlemips") == 0)
10170 if (strcmp (*l
, "elf64-bigmips") == 0
10171 || strcmp (*l
, "elf64-littlemips") == 0)
10174 yes
= (*l
!= NULL
);
10178 #endif /* OBJ_ELF */
10180 const char *md_shortopts
= "O::g::G:";
10182 struct option md_longopts
[] =
10184 /* Options which specify architecture. */
10185 #define OPTION_ARCH_BASE (OPTION_MD_BASE)
10186 #define OPTION_MARCH (OPTION_ARCH_BASE + 0)
10187 {"march", required_argument
, NULL
, OPTION_MARCH
},
10188 #define OPTION_MTUNE (OPTION_ARCH_BASE + 1)
10189 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
10190 #define OPTION_MIPS1 (OPTION_ARCH_BASE + 2)
10191 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
10192 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
10193 #define OPTION_MIPS2 (OPTION_ARCH_BASE + 3)
10194 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
10195 #define OPTION_MIPS3 (OPTION_ARCH_BASE + 4)
10196 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
10197 #define OPTION_MIPS4 (OPTION_ARCH_BASE + 5)
10198 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
10199 #define OPTION_MIPS5 (OPTION_ARCH_BASE + 6)
10200 {"mips5", no_argument
, NULL
, OPTION_MIPS5
},
10201 #define OPTION_MIPS32 (OPTION_ARCH_BASE + 7)
10202 {"mips32", no_argument
, NULL
, OPTION_MIPS32
},
10203 #define OPTION_MIPS64 (OPTION_ARCH_BASE + 8)
10204 {"mips64", no_argument
, NULL
, OPTION_MIPS64
},
10205 #define OPTION_MIPS32R2 (OPTION_ARCH_BASE + 9)
10206 {"mips32r2", no_argument
, NULL
, OPTION_MIPS32R2
},
10207 #define OPTION_MIPS64R2 (OPTION_ARCH_BASE + 10)
10208 {"mips64r2", no_argument
, NULL
, OPTION_MIPS64R2
},
10210 /* Options which specify Application Specific Extensions (ASEs). */
10211 #define OPTION_ASE_BASE (OPTION_ARCH_BASE + 11)
10212 #define OPTION_MIPS16 (OPTION_ASE_BASE + 0)
10213 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
10214 #define OPTION_NO_MIPS16 (OPTION_ASE_BASE + 1)
10215 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
10216 #define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10217 {"mips3d", no_argument
, NULL
, OPTION_MIPS3D
},
10218 #define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10219 {"no-mips3d", no_argument
, NULL
, OPTION_NO_MIPS3D
},
10220 #define OPTION_MDMX (OPTION_ASE_BASE + 4)
10221 {"mdmx", no_argument
, NULL
, OPTION_MDMX
},
10222 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10223 {"no-mdmx", no_argument
, NULL
, OPTION_NO_MDMX
},
10225 /* Old-style architecture options. Don't add more of these. */
10226 #define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10227 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10228 {"m4650", no_argument
, NULL
, OPTION_M4650
},
10229 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10230 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
10231 #define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10232 {"m4010", no_argument
, NULL
, OPTION_M4010
},
10233 #define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10234 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
10235 #define OPTION_M4100 (OPTION_COMPAT_ARCH_BASE + 4)
10236 {"m4100", no_argument
, NULL
, OPTION_M4100
},
10237 #define OPTION_NO_M4100 (OPTION_COMPAT_ARCH_BASE + 5)
10238 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
10239 #define OPTION_M3900 (OPTION_COMPAT_ARCH_BASE + 6)
10240 {"m3900", no_argument
, NULL
, OPTION_M3900
},
10241 #define OPTION_NO_M3900 (OPTION_COMPAT_ARCH_BASE + 7)
10242 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
10244 /* Options which enable bug fixes. */
10245 #define OPTION_FIX_BASE (OPTION_COMPAT_ARCH_BASE + 8)
10246 #define OPTION_M7000_HILO_FIX (OPTION_FIX_BASE + 0)
10247 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
10248 #define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10249 {"no-fix-7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10250 {"mno-fix7000", no_argument
, NULL
, OPTION_MNO_7000_HILO_FIX
},
10251 #define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10252 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10253 {"mfix-vr4120", no_argument
, NULL
, OPTION_FIX_VR4120
},
10254 {"mno-fix-vr4120", no_argument
, NULL
, OPTION_NO_FIX_VR4120
},
10256 /* Miscellaneous options. */
10257 #define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10258 #define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10259 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
10260 #define OPTION_TRAP (OPTION_MISC_BASE + 1)
10261 {"trap", no_argument
, NULL
, OPTION_TRAP
},
10262 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
10263 #define OPTION_BREAK (OPTION_MISC_BASE + 2)
10264 {"break", no_argument
, NULL
, OPTION_BREAK
},
10265 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
10266 #define OPTION_EB (OPTION_MISC_BASE + 3)
10267 {"EB", no_argument
, NULL
, OPTION_EB
},
10268 #define OPTION_EL (OPTION_MISC_BASE + 4)
10269 {"EL", no_argument
, NULL
, OPTION_EL
},
10270 #define OPTION_FP32 (OPTION_MISC_BASE + 5)
10271 {"mfp32", no_argument
, NULL
, OPTION_FP32
},
10272 #define OPTION_GP32 (OPTION_MISC_BASE + 6)
10273 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
10274 #define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10275 {"construct-floats", no_argument
, NULL
, OPTION_CONSTRUCT_FLOATS
},
10276 #define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10277 {"no-construct-floats", no_argument
, NULL
, OPTION_NO_CONSTRUCT_FLOATS
},
10278 #define OPTION_FP64 (OPTION_MISC_BASE + 9)
10279 {"mfp64", no_argument
, NULL
, OPTION_FP64
},
10280 #define OPTION_GP64 (OPTION_MISC_BASE + 10)
10281 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
10282 #define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10283 #define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10284 {"relax-branch", no_argument
, NULL
, OPTION_RELAX_BRANCH
},
10285 {"no-relax-branch", no_argument
, NULL
, OPTION_NO_RELAX_BRANCH
},
10287 /* ELF-specific options. */
10289 #define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10290 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10291 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
10292 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
10293 #define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10294 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
10295 #define OPTION_XGOT (OPTION_ELF_BASE + 2)
10296 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
10297 #define OPTION_MABI (OPTION_ELF_BASE + 3)
10298 {"mabi", required_argument
, NULL
, OPTION_MABI
},
10299 #define OPTION_32 (OPTION_ELF_BASE + 4)
10300 {"32", no_argument
, NULL
, OPTION_32
},
10301 #define OPTION_N32 (OPTION_ELF_BASE + 5)
10302 {"n32", no_argument
, NULL
, OPTION_N32
},
10303 #define OPTION_64 (OPTION_ELF_BASE + 6)
10304 {"64", no_argument
, NULL
, OPTION_64
},
10305 #define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10306 {"mdebug", no_argument
, NULL
, OPTION_MDEBUG
},
10307 #define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10308 {"no-mdebug", no_argument
, NULL
, OPTION_NO_MDEBUG
},
10309 #define OPTION_PDR (OPTION_ELF_BASE + 9)
10310 {"mpdr", no_argument
, NULL
, OPTION_PDR
},
10311 #define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10312 {"mno-pdr", no_argument
, NULL
, OPTION_NO_PDR
},
10313 #endif /* OBJ_ELF */
10315 {NULL
, no_argument
, NULL
, 0}
10317 size_t md_longopts_size
= sizeof (md_longopts
);
10319 /* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10320 NEW_VALUE. Warn if another value was already specified. Note:
10321 we have to defer parsing the -march and -mtune arguments in order
10322 to handle 'from-abi' correctly, since the ABI might be specified
10323 in a later argument. */
10326 mips_set_option_string (const char **string_ptr
, const char *new_value
)
10328 if (*string_ptr
!= 0 && strcasecmp (*string_ptr
, new_value
) != 0)
10329 as_warn (_("A different %s was already specified, is now %s"),
10330 string_ptr
== &mips_arch_string
? "-march" : "-mtune",
10333 *string_ptr
= new_value
;
10337 md_parse_option (int c
, char *arg
)
10341 case OPTION_CONSTRUCT_FLOATS
:
10342 mips_disable_float_construction
= 0;
10345 case OPTION_NO_CONSTRUCT_FLOATS
:
10346 mips_disable_float_construction
= 1;
10358 target_big_endian
= 1;
10362 target_big_endian
= 0;
10366 if (arg
&& arg
[1] == '0')
10376 mips_debug
= atoi (arg
);
10377 /* When the MIPS assembler sees -g or -g2, it does not do
10378 optimizations which limit full symbolic debugging. We take
10379 that to be equivalent to -O0. */
10380 if (mips_debug
== 2)
10385 file_mips_isa
= ISA_MIPS1
;
10389 file_mips_isa
= ISA_MIPS2
;
10393 file_mips_isa
= ISA_MIPS3
;
10397 file_mips_isa
= ISA_MIPS4
;
10401 file_mips_isa
= ISA_MIPS5
;
10404 case OPTION_MIPS32
:
10405 file_mips_isa
= ISA_MIPS32
;
10408 case OPTION_MIPS32R2
:
10409 file_mips_isa
= ISA_MIPS32R2
;
10412 case OPTION_MIPS64R2
:
10413 file_mips_isa
= ISA_MIPS64R2
;
10416 case OPTION_MIPS64
:
10417 file_mips_isa
= ISA_MIPS64
;
10421 mips_set_option_string (&mips_tune_string
, arg
);
10425 mips_set_option_string (&mips_arch_string
, arg
);
10429 mips_set_option_string (&mips_arch_string
, "4650");
10430 mips_set_option_string (&mips_tune_string
, "4650");
10433 case OPTION_NO_M4650
:
10437 mips_set_option_string (&mips_arch_string
, "4010");
10438 mips_set_option_string (&mips_tune_string
, "4010");
10441 case OPTION_NO_M4010
:
10445 mips_set_option_string (&mips_arch_string
, "4100");
10446 mips_set_option_string (&mips_tune_string
, "4100");
10449 case OPTION_NO_M4100
:
10453 mips_set_option_string (&mips_arch_string
, "3900");
10454 mips_set_option_string (&mips_tune_string
, "3900");
10457 case OPTION_NO_M3900
:
10461 mips_opts
.ase_mdmx
= 1;
10464 case OPTION_NO_MDMX
:
10465 mips_opts
.ase_mdmx
= 0;
10468 case OPTION_MIPS16
:
10469 mips_opts
.mips16
= 1;
10470 mips_no_prev_insn (FALSE
);
10473 case OPTION_NO_MIPS16
:
10474 mips_opts
.mips16
= 0;
10475 mips_no_prev_insn (FALSE
);
10478 case OPTION_MIPS3D
:
10479 mips_opts
.ase_mips3d
= 1;
10482 case OPTION_NO_MIPS3D
:
10483 mips_opts
.ase_mips3d
= 0;
10486 case OPTION_MEMBEDDED_PIC
:
10487 mips_pic
= EMBEDDED_PIC
;
10488 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
10490 as_bad (_("-G may not be used with embedded PIC code"));
10493 g_switch_value
= 0x7fffffff;
10496 case OPTION_FIX_VR4120
:
10497 mips_fix_vr4120
= 1;
10500 case OPTION_NO_FIX_VR4120
:
10501 mips_fix_vr4120
= 0;
10504 case OPTION_RELAX_BRANCH
:
10505 mips_relax_branch
= 1;
10508 case OPTION_NO_RELAX_BRANCH
:
10509 mips_relax_branch
= 0;
10513 /* When generating ELF code, we permit -KPIC and -call_shared to
10514 select SVR4_PIC, and -non_shared to select no PIC. This is
10515 intended to be compatible with Irix 5. */
10516 case OPTION_CALL_SHARED
:
10517 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10519 as_bad (_("-call_shared is supported only for ELF format"));
10522 mips_pic
= SVR4_PIC
;
10523 mips_abicalls
= TRUE
;
10524 if (g_switch_seen
&& g_switch_value
!= 0)
10526 as_bad (_("-G may not be used with SVR4 PIC code"));
10529 g_switch_value
= 0;
10532 case OPTION_NON_SHARED
:
10533 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10535 as_bad (_("-non_shared is supported only for ELF format"));
10539 mips_abicalls
= FALSE
;
10542 /* The -xgot option tells the assembler to use 32 offsets when
10543 accessing the got in SVR4_PIC mode. It is for Irix
10548 #endif /* OBJ_ELF */
10551 if (! USE_GLOBAL_POINTER_OPT
)
10553 as_bad (_("-G is not supported for this configuration"));
10556 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
10558 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10562 g_switch_value
= atoi (arg
);
10567 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10570 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10572 as_bad (_("-32 is supported for ELF format only"));
10575 mips_abi
= O32_ABI
;
10579 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10581 as_bad (_("-n32 is supported for ELF format only"));
10584 mips_abi
= N32_ABI
;
10588 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10590 as_bad (_("-64 is supported for ELF format only"));
10593 mips_abi
= N64_ABI
;
10594 if (! support_64bit_objects())
10595 as_fatal (_("No compiled in support for 64 bit object file format"));
10597 #endif /* OBJ_ELF */
10600 file_mips_gp32
= 1;
10604 file_mips_gp32
= 0;
10608 file_mips_fp32
= 1;
10612 file_mips_fp32
= 0;
10617 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
10619 as_bad (_("-mabi is supported for ELF format only"));
10622 if (strcmp (arg
, "32") == 0)
10623 mips_abi
= O32_ABI
;
10624 else if (strcmp (arg
, "o64") == 0)
10625 mips_abi
= O64_ABI
;
10626 else if (strcmp (arg
, "n32") == 0)
10627 mips_abi
= N32_ABI
;
10628 else if (strcmp (arg
, "64") == 0)
10630 mips_abi
= N64_ABI
;
10631 if (! support_64bit_objects())
10632 as_fatal (_("No compiled in support for 64 bit object file "
10635 else if (strcmp (arg
, "eabi") == 0)
10636 mips_abi
= EABI_ABI
;
10639 as_fatal (_("invalid abi -mabi=%s"), arg
);
10643 #endif /* OBJ_ELF */
10645 case OPTION_M7000_HILO_FIX
:
10646 mips_7000_hilo_fix
= TRUE
;
10649 case OPTION_MNO_7000_HILO_FIX
:
10650 mips_7000_hilo_fix
= FALSE
;
10654 case OPTION_MDEBUG
:
10655 mips_flag_mdebug
= TRUE
;
10658 case OPTION_NO_MDEBUG
:
10659 mips_flag_mdebug
= FALSE
;
10663 mips_flag_pdr
= TRUE
;
10666 case OPTION_NO_PDR
:
10667 mips_flag_pdr
= FALSE
;
10669 #endif /* OBJ_ELF */
10678 /* Set up globals to generate code for the ISA or processor
10679 described by INFO. */
10682 mips_set_architecture (const struct mips_cpu_info
*info
)
10686 file_mips_arch
= info
->cpu
;
10687 mips_opts
.arch
= info
->cpu
;
10688 mips_opts
.isa
= info
->isa
;
10693 /* Likewise for tuning. */
10696 mips_set_tune (const struct mips_cpu_info
*info
)
10699 mips_tune
= info
->cpu
;
10704 mips_after_parse_args (void)
10706 const struct mips_cpu_info
*arch_info
= 0;
10707 const struct mips_cpu_info
*tune_info
= 0;
10709 /* GP relative stuff not working for PE */
10710 if (strncmp (TARGET_OS
, "pe", 2) == 0
10711 && g_switch_value
!= 0)
10714 as_bad (_("-G not supported in this configuration."));
10715 g_switch_value
= 0;
10718 if (mips_abi
== NO_ABI
)
10719 mips_abi
= MIPS_DEFAULT_ABI
;
10721 /* The following code determines the architecture and register size.
10722 Similar code was added to GCC 3.3 (see override_options() in
10723 config/mips/mips.c). The GAS and GCC code should be kept in sync
10724 as much as possible. */
10726 if (mips_arch_string
!= 0)
10727 arch_info
= mips_parse_cpu ("-march", mips_arch_string
);
10729 if (file_mips_isa
!= ISA_UNKNOWN
)
10731 /* Handle -mipsN. At this point, file_mips_isa contains the
10732 ISA level specified by -mipsN, while arch_info->isa contains
10733 the -march selection (if any). */
10734 if (arch_info
!= 0)
10736 /* -march takes precedence over -mipsN, since it is more descriptive.
10737 There's no harm in specifying both as long as the ISA levels
10739 if (file_mips_isa
!= arch_info
->isa
)
10740 as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
10741 mips_cpu_info_from_isa (file_mips_isa
)->name
,
10742 mips_cpu_info_from_isa (arch_info
->isa
)->name
);
10745 arch_info
= mips_cpu_info_from_isa (file_mips_isa
);
10748 if (arch_info
== 0)
10749 arch_info
= mips_parse_cpu ("default CPU", MIPS_CPU_STRING_DEFAULT
);
10751 if (ABI_NEEDS_64BIT_REGS (mips_abi
) && !ISA_HAS_64BIT_REGS (arch_info
->isa
))
10752 as_bad ("-march=%s is not compatible with the selected ABI",
10755 mips_set_architecture (arch_info
);
10757 /* Optimize for file_mips_arch, unless -mtune selects a different processor. */
10758 if (mips_tune_string
!= 0)
10759 tune_info
= mips_parse_cpu ("-mtune", mips_tune_string
);
10761 if (tune_info
== 0)
10762 mips_set_tune (arch_info
);
10764 mips_set_tune (tune_info
);
10766 if (file_mips_gp32
>= 0)
10768 /* The user specified the size of the integer registers. Make sure
10769 it agrees with the ABI and ISA. */
10770 if (file_mips_gp32
== 0 && !ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10771 as_bad (_("-mgp64 used with a 32-bit processor"));
10772 else if (file_mips_gp32
== 1 && ABI_NEEDS_64BIT_REGS (mips_abi
))
10773 as_bad (_("-mgp32 used with a 64-bit ABI"));
10774 else if (file_mips_gp32
== 0 && ABI_NEEDS_32BIT_REGS (mips_abi
))
10775 as_bad (_("-mgp64 used with a 32-bit ABI"));
10779 /* Infer the integer register size from the ABI and processor.
10780 Restrict ourselves to 32-bit registers if that's all the
10781 processor has, or if the ABI cannot handle 64-bit registers. */
10782 file_mips_gp32
= (ABI_NEEDS_32BIT_REGS (mips_abi
)
10783 || !ISA_HAS_64BIT_REGS (mips_opts
.isa
));
10786 /* ??? GAS treats single-float processors as though they had 64-bit
10787 float registers (although it complains when double-precision
10788 instructions are used). As things stand, saying they have 32-bit
10789 registers would lead to spurious "register must be even" messages.
10790 So here we assume float registers are always the same size as
10791 integer ones, unless the user says otherwise. */
10792 if (file_mips_fp32
< 0)
10793 file_mips_fp32
= file_mips_gp32
;
10795 /* End of GCC-shared inference code. */
10797 /* This flag is set when we have a 64-bit capable CPU but use only
10798 32-bit wide registers. Note that EABI does not use it. */
10799 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
10800 && ((mips_abi
== NO_ABI
&& file_mips_gp32
== 1)
10801 || mips_abi
== O32_ABI
))
10802 mips_32bitmode
= 1;
10804 if (mips_opts
.isa
== ISA_MIPS1
&& mips_trap
)
10805 as_bad (_("trap exception not supported at ISA 1"));
10807 /* If the selected architecture includes support for ASEs, enable
10808 generation of code for them. */
10809 if (mips_opts
.mips16
== -1)
10810 mips_opts
.mips16
= (CPU_HAS_MIPS16 (file_mips_arch
)) ? 1 : 0;
10811 if (mips_opts
.ase_mips3d
== -1)
10812 mips_opts
.ase_mips3d
= (CPU_HAS_MIPS3D (file_mips_arch
)) ? 1 : 0;
10813 if (mips_opts
.ase_mdmx
== -1)
10814 mips_opts
.ase_mdmx
= (CPU_HAS_MDMX (file_mips_arch
)) ? 1 : 0;
10816 file_mips_isa
= mips_opts
.isa
;
10817 file_ase_mips16
= mips_opts
.mips16
;
10818 file_ase_mips3d
= mips_opts
.ase_mips3d
;
10819 file_ase_mdmx
= mips_opts
.ase_mdmx
;
10820 mips_opts
.gp32
= file_mips_gp32
;
10821 mips_opts
.fp32
= file_mips_fp32
;
10823 if (mips_flag_mdebug
< 0)
10825 #ifdef OBJ_MAYBE_ECOFF
10826 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
)
10827 mips_flag_mdebug
= 1;
10829 #endif /* OBJ_MAYBE_ECOFF */
10830 mips_flag_mdebug
= 0;
10835 mips_init_after_args (void)
10837 /* initialize opcodes */
10838 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
10839 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
10843 md_pcrel_from (fixS
*fixP
)
10845 valueT addr
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
10846 switch (fixP
->fx_r_type
)
10848 case BFD_RELOC_16_PCREL_S2
:
10849 case BFD_RELOC_MIPS_JMP
:
10850 /* Return the address of the delay slot. */
10857 /* This is called before the symbol table is processed. In order to
10858 work with gcc when using mips-tfile, we must keep all local labels.
10859 However, in other cases, we want to discard them. If we were
10860 called with -g, but we didn't see any debugging information, it may
10861 mean that gcc is smuggling debugging information through to
10862 mips-tfile, in which case we must generate all local labels. */
10865 mips_frob_file_before_adjust (void)
10867 #ifndef NO_ECOFF_DEBUGGING
10868 if (ECOFF_DEBUGGING
10870 && ! ecoff_debugging_seen
)
10871 flag_keep_locals
= 1;
10875 /* Sort any unmatched HI16_S relocs so that they immediately precede
10876 the corresponding LO reloc. This is called before md_apply_fix3 and
10877 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10878 explicit use of the %hi modifier. */
10881 mips_frob_file (void)
10883 struct mips_hi_fixup
*l
;
10885 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
10887 segment_info_type
*seginfo
;
10890 assert (reloc_needs_lo_p (l
->fixp
->fx_r_type
));
10892 /* If a GOT16 relocation turns out to be against a global symbol,
10893 there isn't supposed to be a matching LO. */
10894 if (l
->fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
10895 && !pic_need_relax (l
->fixp
->fx_addsy
, l
->seg
))
10898 /* Check quickly whether the next fixup happens to be a matching %lo. */
10899 if (fixup_has_matching_lo_p (l
->fixp
))
10902 /* Look through the fixups for this segment for a matching %lo.
10903 When we find one, move the %hi just in front of it. We do
10904 this in two passes. In the first pass, we try to find a
10905 unique %lo. In the second pass, we permit multiple %hi
10906 relocs for a single %lo (this is a GNU extension). */
10907 seginfo
= seg_info (l
->seg
);
10908 for (pass
= 0; pass
< 2; pass
++)
10913 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
10915 /* Check whether this is a %lo fixup which matches l->fixp. */
10916 if (f
->fx_r_type
== BFD_RELOC_LO16
10917 && f
->fx_addsy
== l
->fixp
->fx_addsy
10918 && f
->fx_offset
== l
->fixp
->fx_offset
10921 || !reloc_needs_lo_p (prev
->fx_r_type
)
10922 || !fixup_has_matching_lo_p (prev
)))
10926 /* Move l->fixp before f. */
10927 for (pf
= &seginfo
->fix_root
;
10929 pf
= &(*pf
)->fx_next
)
10930 assert (*pf
!= NULL
);
10932 *pf
= l
->fixp
->fx_next
;
10934 l
->fixp
->fx_next
= f
;
10936 seginfo
->fix_root
= l
->fixp
;
10938 prev
->fx_next
= l
->fixp
;
10949 #if 0 /* GCC code motion plus incomplete dead code elimination
10950 can leave a %hi without a %lo. */
10952 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
10953 _("Unmatched %%hi reloc"));
10959 /* When generating embedded PIC code we need to use a special
10960 relocation to represent the difference of two symbols in the .text
10961 section (switch tables use a difference of this sort). See
10962 include/coff/mips.h for details. This macro checks whether this
10963 fixup requires the special reloc. */
10964 #define SWITCH_TABLE(fixp) \
10965 ((fixp)->fx_r_type == BFD_RELOC_32 \
10966 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10967 && (fixp)->fx_addsy != NULL \
10968 && (fixp)->fx_subsy != NULL \
10969 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10970 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10972 /* When generating embedded PIC code we must keep all PC relative
10973 relocations, in case the linker has to relax a call. We also need
10974 to keep relocations for switch table entries.
10976 We may have combined relocations without symbols in the N32/N64 ABI.
10977 We have to prevent gas from dropping them. */
10980 mips_force_relocation (fixS
*fixp
)
10982 if (generic_force_reloc (fixp
))
10986 && S_GET_SEGMENT (fixp
->fx_addsy
) == bfd_abs_section_ptr
10987 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_SUB
10988 || fixp
->fx_r_type
== BFD_RELOC_HI16_S
10989 || fixp
->fx_r_type
== BFD_RELOC_LO16
))
10992 return (mips_pic
== EMBEDDED_PIC
10994 || SWITCH_TABLE (fixp
)
10995 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
10996 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
10999 /* This hook is called before a fix is simplified. We don't really
11000 decide whether to skip a fix here. Rather, we turn global symbols
11001 used as branch targets into local symbols, such that they undergo
11002 simplification. We can only do this if the symbol is defined and
11003 it is in the same section as the branch. If this doesn't hold, we
11004 emit a better error message than just saying the relocation is not
11005 valid for the selected object format.
11007 FIXP is the fix-up we're going to try to simplify, SEG is the
11008 segment in which the fix up occurs. The return value should be
11009 non-zero to indicate the fix-up is valid for further
11010 simplifications. */
11013 mips_validate_fix (struct fix
*fixP
, asection
*seg
)
11015 /* There's a lot of discussion on whether it should be possible to
11016 use R_MIPS_PC16 to represent branch relocations. The outcome
11017 seems to be that it can, but gas/bfd are very broken in creating
11018 RELA relocations for this, so for now we only accept branches to
11019 symbols in the same section. Anything else is of dubious value,
11020 since there's no guarantee that at link time the symbol would be
11021 in range. Even for branches to local symbols this is arguably
11022 wrong, since it we assume the symbol is not going to be
11023 overridden, which should be possible per ELF library semantics,
11024 but then, there isn't a dynamic relocation that could be used to
11025 this effect, and the target would likely be out of range as well.
11027 Unfortunately, it seems that there is too much code out there
11028 that relies on branches to symbols that are global to be resolved
11029 as if they were local, like the IRIX tools do, so we do it as
11030 well, but with a warning so that people are reminded to fix their
11031 code. If we ever get back to using R_MIPS_PC16 for branch
11032 targets, this entire block should go away (and probably the
11033 whole function). */
11035 if (fixP
->fx_r_type
== BFD_RELOC_16_PCREL_S2
11036 && (((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11037 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11038 && mips_pic
!= EMBEDDED_PIC
)
11039 || bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_16_PCREL_S2
) == NULL
)
11042 if (! S_IS_DEFINED (fixP
->fx_addsy
))
11044 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11045 _("Cannot branch to undefined symbol."));
11046 /* Avoid any further errors about this fixup. */
11049 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
11051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11052 _("Cannot branch to symbol in another section."));
11055 else if (S_IS_EXTERNAL (fixP
->fx_addsy
))
11057 symbolS
*sym
= fixP
->fx_addsy
;
11059 if (mips_pic
== SVR4_PIC
)
11060 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
11061 _("Pretending global symbol used as branch target is local."));
11063 fixP
->fx_addsy
= symbol_create (S_GET_NAME (sym
),
11064 S_GET_SEGMENT (sym
),
11066 symbol_get_frag (sym
));
11067 copy_symbol_attributes (fixP
->fx_addsy
, sym
);
11068 S_CLEAR_EXTERNAL (fixP
->fx_addsy
);
11069 assert (symbol_resolved_p (sym
));
11070 symbol_mark_resolved (fixP
->fx_addsy
);
11077 /* Apply a fixup to the object file. */
11080 md_apply_fix3 (fixS
*fixP
, valueT
*valP
, segT seg ATTRIBUTE_UNUSED
)
11084 static int previous_fx_r_type
= 0;
11085 reloc_howto_type
*howto
;
11087 /* We ignore generic BFD relocations we don't know about. */
11088 howto
= bfd_reloc_type_lookup (stdoutput
, fixP
->fx_r_type
);
11092 assert (fixP
->fx_size
== 4
11093 || fixP
->fx_r_type
== BFD_RELOC_16
11094 || fixP
->fx_r_type
== BFD_RELOC_64
11095 || fixP
->fx_r_type
== BFD_RELOC_CTOR
11096 || fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11097 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11098 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
11100 buf
= (bfd_byte
*) (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
);
11102 /* We are not done if this is a composite relocation to set up gp. */
11103 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
11104 && !(fixP
->fx_r_type
== BFD_RELOC_MIPS_SUB
11105 || (fixP
->fx_r_type
== BFD_RELOC_64
11106 && (previous_fx_r_type
== BFD_RELOC_GPREL32
11107 || previous_fx_r_type
== BFD_RELOC_GPREL16
))
11108 || (previous_fx_r_type
== BFD_RELOC_MIPS_SUB
11109 && (fixP
->fx_r_type
== BFD_RELOC_HI16_S
11110 || fixP
->fx_r_type
== BFD_RELOC_LO16
))))
11112 previous_fx_r_type
= fixP
->fx_r_type
;
11114 switch (fixP
->fx_r_type
)
11116 case BFD_RELOC_MIPS_JMP
:
11117 case BFD_RELOC_MIPS_SHIFT5
:
11118 case BFD_RELOC_MIPS_SHIFT6
:
11119 case BFD_RELOC_MIPS_GOT_DISP
:
11120 case BFD_RELOC_MIPS_GOT_PAGE
:
11121 case BFD_RELOC_MIPS_GOT_OFST
:
11122 case BFD_RELOC_MIPS_SUB
:
11123 case BFD_RELOC_MIPS_INSERT_A
:
11124 case BFD_RELOC_MIPS_INSERT_B
:
11125 case BFD_RELOC_MIPS_DELETE
:
11126 case BFD_RELOC_MIPS_HIGHEST
:
11127 case BFD_RELOC_MIPS_HIGHER
:
11128 case BFD_RELOC_MIPS_SCN_DISP
:
11129 case BFD_RELOC_MIPS_REL16
:
11130 case BFD_RELOC_MIPS_RELGOT
:
11131 case BFD_RELOC_MIPS_JALR
:
11132 case BFD_RELOC_HI16
:
11133 case BFD_RELOC_HI16_S
:
11134 case BFD_RELOC_GPREL16
:
11135 case BFD_RELOC_MIPS_LITERAL
:
11136 case BFD_RELOC_MIPS_CALL16
:
11137 case BFD_RELOC_MIPS_GOT16
:
11138 case BFD_RELOC_GPREL32
:
11139 case BFD_RELOC_MIPS_GOT_HI16
:
11140 case BFD_RELOC_MIPS_GOT_LO16
:
11141 case BFD_RELOC_MIPS_CALL_HI16
:
11142 case BFD_RELOC_MIPS_CALL_LO16
:
11143 case BFD_RELOC_MIPS16_GPREL
:
11144 if (fixP
->fx_pcrel
)
11145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11146 _("Invalid PC relative reloc"));
11147 /* Nothing needed to do. The value comes from the reloc entry */
11150 case BFD_RELOC_MIPS16_JMP
:
11151 /* We currently always generate a reloc against a symbol, which
11152 means that we don't want an addend even if the symbol is
11157 case BFD_RELOC_PCREL_HI16_S
:
11158 /* The addend for this is tricky if it is internal, so we just
11159 do everything here rather than in bfd_install_relocation. */
11160 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11163 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11165 /* For an external symbol adjust by the address to make it
11166 pcrel_offset. We use the address of the RELLO reloc
11167 which follows this one. */
11168 *valP
+= (fixP
->fx_next
->fx_frag
->fr_address
11169 + fixP
->fx_next
->fx_where
);
11171 *valP
= ((*valP
+ 0x8000) >> 16) & 0xffff;
11172 if (target_big_endian
)
11174 md_number_to_chars (buf
, *valP
, 2);
11177 case BFD_RELOC_PCREL_LO16
:
11178 /* The addend for this is tricky if it is internal, so we just
11179 do everything here rather than in bfd_install_relocation. */
11180 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& !fixP
->fx_done
)
11183 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
11184 *valP
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
11185 if (target_big_endian
)
11187 md_number_to_chars (buf
, *valP
, 2);
11191 /* This is handled like BFD_RELOC_32, but we output a sign
11192 extended value if we are only 32 bits. */
11194 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11196 if (8 <= sizeof (valueT
))
11197 md_number_to_chars (buf
, *valP
, 8);
11202 if ((*valP
& 0x80000000) != 0)
11206 md_number_to_chars ((char *)(buf
+ target_big_endian
? 4 : 0),
11208 md_number_to_chars ((char *)(buf
+ target_big_endian
? 0 : 4),
11214 case BFD_RELOC_RVA
:
11216 /* If we are deleting this reloc entry, we must fill in the
11217 value now. This can happen if we have a .word which is not
11218 resolved when it appears but is later defined. We also need
11219 to fill in the value if this is an embedded PIC switch table
11222 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
11223 md_number_to_chars (buf
, *valP
, 4);
11227 /* If we are deleting this reloc entry, we must fill in the
11229 assert (fixP
->fx_size
== 2);
11231 md_number_to_chars (buf
, *valP
, 2);
11234 case BFD_RELOC_LO16
:
11235 /* When handling an embedded PIC switch statement, we can wind
11236 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11239 if (*valP
+ 0x8000 > 0xffff)
11240 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11241 _("relocation overflow"));
11242 if (target_big_endian
)
11244 md_number_to_chars (buf
, *valP
, 2);
11248 case BFD_RELOC_16_PCREL_S2
:
11249 if ((*valP
& 0x3) != 0)
11250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11251 _("Branch to odd address (%lx)"), (long) *valP
);
11254 * We need to save the bits in the instruction since fixup_segment()
11255 * might be deleting the relocation entry (i.e., a branch within
11256 * the current segment).
11258 if (! fixP
->fx_done
)
11261 /* update old instruction data */
11262 if (target_big_endian
)
11263 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
11265 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
11267 if (*valP
+ 0x20000 <= 0x3ffff)
11269 insn
|= (*valP
>> 2) & 0xffff;
11270 md_number_to_chars (buf
, insn
, 4);
11272 else if (mips_pic
== NO_PIC
11274 && fixP
->fx_frag
->fr_address
>= text_section
->vma
11275 && (fixP
->fx_frag
->fr_address
11276 < text_section
->vma
+ text_section
->_raw_size
)
11277 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
11278 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
11279 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
11281 /* The branch offset is too large. If this is an
11282 unconditional branch, and we are not generating PIC code,
11283 we can convert it to an absolute jump instruction. */
11284 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
11285 insn
= 0x0c000000; /* jal */
11287 insn
= 0x08000000; /* j */
11288 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
11290 fixP
->fx_addsy
= section_symbol (text_section
);
11291 *valP
+= md_pcrel_from (fixP
);
11292 md_number_to_chars (buf
, insn
, 4);
11296 /* If we got here, we have branch-relaxation disabled,
11297 and there's nothing we can do to fix this instruction
11298 without turning it into a longer sequence. */
11299 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
11300 _("Branch out of range"));
11304 case BFD_RELOC_VTABLE_INHERIT
:
11307 && !S_IS_DEFINED (fixP
->fx_addsy
)
11308 && !S_IS_WEAK (fixP
->fx_addsy
))
11309 S_SET_WEAK (fixP
->fx_addsy
);
11312 case BFD_RELOC_VTABLE_ENTRY
:
11320 /* Remember value for tc_gen_reloc. */
11321 fixP
->fx_addnumber
= *valP
;
11326 printInsn (unsigned long oc
)
11328 const struct mips_opcode
*p
;
11329 int treg
, sreg
, dreg
, shamt
;
11334 for (i
= 0; i
< NUMOPCODES
; ++i
)
11336 p
= &mips_opcodes
[i
];
11337 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
11339 printf ("%08lx %s\t", oc
, p
->name
);
11340 treg
= (oc
>> 16) & 0x1f;
11341 sreg
= (oc
>> 21) & 0x1f;
11342 dreg
= (oc
>> 11) & 0x1f;
11343 shamt
= (oc
>> 6) & 0x1f;
11345 for (args
= p
->args
;; ++args
)
11356 printf ("%c", *args
);
11360 assert (treg
== sreg
);
11361 printf ("$%d,$%d", treg
, sreg
);
11366 printf ("$%d", dreg
);
11371 printf ("$%d", treg
);
11375 printf ("0x%x", treg
);
11380 printf ("$%d", sreg
);
11384 printf ("0x%08lx", oc
& 0x1ffffff);
11391 printf ("%d", imm
);
11396 printf ("$%d", shamt
);
11407 printf (_("%08lx UNDEFINED\n"), oc
);
11418 name
= input_line_pointer
;
11419 c
= get_symbol_end ();
11420 p
= (symbolS
*) symbol_find_or_make (name
);
11421 *input_line_pointer
= c
;
11425 /* Align the current frag to a given power of two. The MIPS assembler
11426 also automatically adjusts any preceding label. */
11429 mips_align (int to
, int fill
, symbolS
*label
)
11431 mips_emit_delays (FALSE
);
11432 frag_align (to
, fill
, 0);
11433 record_alignment (now_seg
, to
);
11436 assert (S_GET_SEGMENT (label
) == now_seg
);
11437 symbol_set_frag (label
, frag_now
);
11438 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
11442 /* Align to a given power of two. .align 0 turns off the automatic
11443 alignment used by the data creating pseudo-ops. */
11446 s_align (int x ATTRIBUTE_UNUSED
)
11449 register long temp_fill
;
11450 long max_alignment
= 15;
11454 o Note that the assembler pulls down any immediately preceding label
11455 to the aligned address.
11456 o It's not documented but auto alignment is reinstated by
11457 a .align pseudo instruction.
11458 o Note also that after auto alignment is turned off the mips assembler
11459 issues an error on attempt to assemble an improperly aligned data item.
11464 temp
= get_absolute_expression ();
11465 if (temp
> max_alignment
)
11466 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
11469 as_warn (_("Alignment negative: 0 assumed."));
11472 if (*input_line_pointer
== ',')
11474 ++input_line_pointer
;
11475 temp_fill
= get_absolute_expression ();
11482 mips_align (temp
, (int) temp_fill
,
11483 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
11490 demand_empty_rest_of_line ();
11494 mips_flush_pending_output (void)
11496 mips_emit_delays (FALSE
);
11497 mips_clear_insn_labels ();
11501 s_change_sec (int sec
)
11505 /* When generating embedded PIC code, we only use the .text, .lit8,
11506 .sdata and .sbss sections. We change the .data and .rdata
11507 pseudo-ops to use .sdata. */
11508 if (mips_pic
== EMBEDDED_PIC
11509 && (sec
== 'd' || sec
== 'r'))
11513 /* The ELF backend needs to know that we are changing sections, so
11514 that .previous works correctly. We could do something like check
11515 for an obj_section_change_hook macro, but that might be confusing
11516 as it would not be appropriate to use it in the section changing
11517 functions in read.c, since obj-elf.c intercepts those. FIXME:
11518 This should be cleaner, somehow. */
11519 obj_elf_section_change_hook ();
11522 mips_emit_delays (FALSE
);
11532 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
11533 demand_empty_rest_of_line ();
11537 if (USE_GLOBAL_POINTER_OPT
)
11539 seg
= subseg_new (RDATA_SECTION_NAME
,
11540 (subsegT
) get_absolute_expression ());
11541 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11543 bfd_set_section_flags (stdoutput
, seg
,
11549 if (strcmp (TARGET_OS
, "elf") != 0)
11550 record_alignment (seg
, 4);
11552 demand_empty_rest_of_line ();
11556 as_bad (_("No read only data section in this object file format"));
11557 demand_empty_rest_of_line ();
11563 if (USE_GLOBAL_POINTER_OPT
)
11565 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
11566 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11568 bfd_set_section_flags (stdoutput
, seg
,
11569 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
11571 if (strcmp (TARGET_OS
, "elf") != 0)
11572 record_alignment (seg
, 4);
11574 demand_empty_rest_of_line ();
11579 as_bad (_("Global pointers not supported; recompile -G 0"));
11580 demand_empty_rest_of_line ();
11589 s_change_section (int ignore ATTRIBUTE_UNUSED
)
11592 char *section_name
;
11597 int section_entry_size
;
11598 int section_alignment
;
11600 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11603 section_name
= input_line_pointer
;
11604 c
= get_symbol_end ();
11606 next_c
= *(input_line_pointer
+ 1);
11608 /* Do we have .section Name<,"flags">? */
11609 if (c
!= ',' || (c
== ',' && next_c
== '"'))
11611 /* just after name is now '\0'. */
11612 *input_line_pointer
= c
;
11613 input_line_pointer
= section_name
;
11614 obj_elf_section (ignore
);
11617 input_line_pointer
++;
11619 /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */
11621 section_type
= get_absolute_expression ();
11624 if (*input_line_pointer
++ == ',')
11625 section_flag
= get_absolute_expression ();
11628 if (*input_line_pointer
++ == ',')
11629 section_entry_size
= get_absolute_expression ();
11631 section_entry_size
= 0;
11632 if (*input_line_pointer
++ == ',')
11633 section_alignment
= get_absolute_expression ();
11635 section_alignment
= 0;
11637 section_name
= xstrdup (section_name
);
11639 /* When using the generic form of .section (as implemented by obj-elf.c),
11640 there's no way to set the section type to SHT_MIPS_DWARF. Users have
11641 traditionally had to fall back on the more common @progbits instead.
11643 There's nothing really harmful in this, since bfd will correct
11644 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
11645 means that, for backwards compatibiltiy, the special_section entries
11646 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
11648 Even so, we shouldn't force users of the MIPS .section syntax to
11649 incorrectly label the sections as SHT_PROGBITS. The best compromise
11650 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
11651 generic type-checking code. */
11652 if (section_type
== SHT_MIPS_DWARF
)
11653 section_type
= SHT_PROGBITS
;
11655 obj_elf_change_section (section_name
, section_type
, section_flag
,
11656 section_entry_size
, 0, 0, 0);
11658 if (now_seg
->name
!= section_name
)
11659 free (section_name
);
11660 #endif /* OBJ_ELF */
11664 mips_enable_auto_align (void)
11670 s_cons (int log_size
)
11674 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11675 mips_emit_delays (FALSE
);
11676 if (log_size
> 0 && auto_align
)
11677 mips_align (log_size
, 0, label
);
11678 mips_clear_insn_labels ();
11679 cons (1 << log_size
);
11683 s_float_cons (int type
)
11687 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
11689 mips_emit_delays (FALSE
);
11694 mips_align (3, 0, label
);
11696 mips_align (2, 0, label
);
11699 mips_clear_insn_labels ();
11704 /* Handle .globl. We need to override it because on Irix 5 you are
11707 where foo is an undefined symbol, to mean that foo should be
11708 considered to be the address of a function. */
11711 s_mips_globl (int x ATTRIBUTE_UNUSED
)
11718 name
= input_line_pointer
;
11719 c
= get_symbol_end ();
11720 symbolP
= symbol_find_or_make (name
);
11721 *input_line_pointer
= c
;
11722 SKIP_WHITESPACE ();
11724 /* On Irix 5, every global symbol that is not explicitly labelled as
11725 being a function is apparently labelled as being an object. */
11728 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
11733 secname
= input_line_pointer
;
11734 c
= get_symbol_end ();
11735 sec
= bfd_get_section_by_name (stdoutput
, secname
);
11737 as_bad (_("%s: no such section"), secname
);
11738 *input_line_pointer
= c
;
11740 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
11741 flag
= BSF_FUNCTION
;
11744 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
11746 S_SET_EXTERNAL (symbolP
);
11747 demand_empty_rest_of_line ();
11751 s_option (int x ATTRIBUTE_UNUSED
)
11756 opt
= input_line_pointer
;
11757 c
= get_symbol_end ();
11761 /* FIXME: What does this mean? */
11763 else if (strncmp (opt
, "pic", 3) == 0)
11767 i
= atoi (opt
+ 3);
11772 mips_pic
= SVR4_PIC
;
11773 mips_abicalls
= TRUE
;
11776 as_bad (_(".option pic%d not supported"), i
);
11778 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
11780 if (g_switch_seen
&& g_switch_value
!= 0)
11781 as_warn (_("-G may not be used with SVR4 PIC code"));
11782 g_switch_value
= 0;
11783 bfd_set_gp_size (stdoutput
, 0);
11787 as_warn (_("Unrecognized option \"%s\""), opt
);
11789 *input_line_pointer
= c
;
11790 demand_empty_rest_of_line ();
11793 /* This structure is used to hold a stack of .set values. */
11795 struct mips_option_stack
11797 struct mips_option_stack
*next
;
11798 struct mips_set_options options
;
11801 static struct mips_option_stack
*mips_opts_stack
;
11803 /* Handle the .set pseudo-op. */
11806 s_mipsset (int x ATTRIBUTE_UNUSED
)
11808 char *name
= input_line_pointer
, ch
;
11810 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11811 ++input_line_pointer
;
11812 ch
= *input_line_pointer
;
11813 *input_line_pointer
= '\0';
11815 if (strcmp (name
, "reorder") == 0)
11817 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
11819 /* If we still have pending nops, we can discard them. The
11820 usual nop handling will insert any that are still
11822 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11823 * (mips_opts
.mips16
? 2 : 4));
11824 prev_nop_frag
= NULL
;
11826 mips_opts
.noreorder
= 0;
11828 else if (strcmp (name
, "noreorder") == 0)
11830 mips_emit_delays (TRUE
);
11831 mips_opts
.noreorder
= 1;
11832 mips_any_noreorder
= 1;
11834 else if (strcmp (name
, "at") == 0)
11836 mips_opts
.noat
= 0;
11838 else if (strcmp (name
, "noat") == 0)
11840 mips_opts
.noat
= 1;
11842 else if (strcmp (name
, "macro") == 0)
11844 mips_opts
.warn_about_macros
= 0;
11846 else if (strcmp (name
, "nomacro") == 0)
11848 if (mips_opts
.noreorder
== 0)
11849 as_bad (_("`noreorder' must be set before `nomacro'"));
11850 mips_opts
.warn_about_macros
= 1;
11852 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
11854 mips_opts
.nomove
= 0;
11856 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
11858 mips_opts
.nomove
= 1;
11860 else if (strcmp (name
, "bopt") == 0)
11862 mips_opts
.nobopt
= 0;
11864 else if (strcmp (name
, "nobopt") == 0)
11866 mips_opts
.nobopt
= 1;
11868 else if (strcmp (name
, "mips16") == 0
11869 || strcmp (name
, "MIPS-16") == 0)
11870 mips_opts
.mips16
= 1;
11871 else if (strcmp (name
, "nomips16") == 0
11872 || strcmp (name
, "noMIPS-16") == 0)
11873 mips_opts
.mips16
= 0;
11874 else if (strcmp (name
, "mips3d") == 0)
11875 mips_opts
.ase_mips3d
= 1;
11876 else if (strcmp (name
, "nomips3d") == 0)
11877 mips_opts
.ase_mips3d
= 0;
11878 else if (strcmp (name
, "mdmx") == 0)
11879 mips_opts
.ase_mdmx
= 1;
11880 else if (strcmp (name
, "nomdmx") == 0)
11881 mips_opts
.ase_mdmx
= 0;
11882 else if (strncmp (name
, "mips", 4) == 0 || strncmp (name
, "arch=", 5) == 0)
11886 /* Permit the user to change the ISA and architecture on the fly.
11887 Needless to say, misuse can cause serious problems. */
11888 if (strcmp (name
, "mips0") == 0)
11891 mips_opts
.isa
= file_mips_isa
;
11893 else if (strcmp (name
, "mips1") == 0)
11894 mips_opts
.isa
= ISA_MIPS1
;
11895 else if (strcmp (name
, "mips2") == 0)
11896 mips_opts
.isa
= ISA_MIPS2
;
11897 else if (strcmp (name
, "mips3") == 0)
11898 mips_opts
.isa
= ISA_MIPS3
;
11899 else if (strcmp (name
, "mips4") == 0)
11900 mips_opts
.isa
= ISA_MIPS4
;
11901 else if (strcmp (name
, "mips5") == 0)
11902 mips_opts
.isa
= ISA_MIPS5
;
11903 else if (strcmp (name
, "mips32") == 0)
11904 mips_opts
.isa
= ISA_MIPS32
;
11905 else if (strcmp (name
, "mips32r2") == 0)
11906 mips_opts
.isa
= ISA_MIPS32R2
;
11907 else if (strcmp (name
, "mips64") == 0)
11908 mips_opts
.isa
= ISA_MIPS64
;
11909 else if (strcmp (name
, "mips64r2") == 0)
11910 mips_opts
.isa
= ISA_MIPS64R2
;
11911 else if (strcmp (name
, "arch=default") == 0)
11914 mips_opts
.arch
= file_mips_arch
;
11915 mips_opts
.isa
= file_mips_isa
;
11917 else if (strncmp (name
, "arch=", 5) == 0)
11919 const struct mips_cpu_info
*p
;
11921 p
= mips_parse_cpu("internal use", name
+ 5);
11923 as_bad (_("unknown architecture %s"), name
+ 5);
11926 mips_opts
.arch
= p
->cpu
;
11927 mips_opts
.isa
= p
->isa
;
11931 as_bad (_("unknown ISA level %s"), name
+ 4);
11933 switch (mips_opts
.isa
)
11941 mips_opts
.gp32
= 1;
11942 mips_opts
.fp32
= 1;
11949 mips_opts
.gp32
= 0;
11950 mips_opts
.fp32
= 0;
11953 as_bad (_("unknown ISA level %s"), name
+ 4);
11958 mips_opts
.gp32
= file_mips_gp32
;
11959 mips_opts
.fp32
= file_mips_fp32
;
11962 else if (strcmp (name
, "autoextend") == 0)
11963 mips_opts
.noautoextend
= 0;
11964 else if (strcmp (name
, "noautoextend") == 0)
11965 mips_opts
.noautoextend
= 1;
11966 else if (strcmp (name
, "push") == 0)
11968 struct mips_option_stack
*s
;
11970 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
11971 s
->next
= mips_opts_stack
;
11972 s
->options
= mips_opts
;
11973 mips_opts_stack
= s
;
11975 else if (strcmp (name
, "pop") == 0)
11977 struct mips_option_stack
*s
;
11979 s
= mips_opts_stack
;
11981 as_bad (_(".set pop with no .set push"));
11984 /* If we're changing the reorder mode we need to handle
11985 delay slots correctly. */
11986 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
11987 mips_emit_delays (TRUE
);
11988 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
11990 if (prev_nop_frag
!= NULL
)
11992 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
11993 * (mips_opts
.mips16
? 2 : 4));
11994 prev_nop_frag
= NULL
;
11998 mips_opts
= s
->options
;
11999 mips_opts_stack
= s
->next
;
12005 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
12007 *input_line_pointer
= ch
;
12008 demand_empty_rest_of_line ();
12011 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
12012 .option pic2. It means to generate SVR4 PIC calls. */
12015 s_abicalls (int ignore ATTRIBUTE_UNUSED
)
12017 mips_pic
= SVR4_PIC
;
12018 mips_abicalls
= TRUE
;
12019 if (USE_GLOBAL_POINTER_OPT
)
12021 if (g_switch_seen
&& g_switch_value
!= 0)
12022 as_warn (_("-G may not be used with SVR4 PIC code"));
12023 g_switch_value
= 0;
12025 bfd_set_gp_size (stdoutput
, 0);
12026 demand_empty_rest_of_line ();
12029 /* Handle the .cpload pseudo-op. This is used when generating SVR4
12030 PIC code. It sets the $gp register for the function based on the
12031 function address, which is in the register named in the argument.
12032 This uses a relocation against _gp_disp, which is handled specially
12033 by the linker. The result is:
12034 lui $gp,%hi(_gp_disp)
12035 addiu $gp,$gp,%lo(_gp_disp)
12036 addu $gp,$gp,.cpload argument
12037 The .cpload argument is normally $25 == $t9. */
12040 s_cpload (int ignore ATTRIBUTE_UNUSED
)
12044 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12045 .cpload is ignored. */
12046 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12052 /* .cpload should be in a .set noreorder section. */
12053 if (mips_opts
.noreorder
== 0)
12054 as_warn (_(".cpload not in noreorder section"));
12056 ex
.X_op
= O_symbol
;
12057 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
12058 ex
.X_op_symbol
= NULL
;
12059 ex
.X_add_number
= 0;
12061 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12062 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
12065 macro_build_lui (&ex
, mips_gp_register
);
12066 macro_build (&ex
, "addiu", "t,r,j", mips_gp_register
,
12067 mips_gp_register
, BFD_RELOC_LO16
);
12068 macro_build (NULL
, "addu", "d,v,t", mips_gp_register
,
12069 mips_gp_register
, tc_get_register (0));
12072 demand_empty_rest_of_line ();
12075 /* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12076 .cpsetup $reg1, offset|$reg2, label
12078 If offset is given, this results in:
12079 sd $gp, offset($sp)
12080 lui $gp, %hi(%neg(%gp_rel(label)))
12081 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12082 daddu $gp, $gp, $reg1
12084 If $reg2 is given, this results in:
12085 daddu $reg2, $gp, $0
12086 lui $gp, %hi(%neg(%gp_rel(label)))
12087 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12088 daddu $gp, $gp, $reg1
12089 $reg1 is normally $25 == $t9. */
12091 s_cpsetup (int ignore ATTRIBUTE_UNUSED
)
12093 expressionS ex_off
;
12094 expressionS ex_sym
;
12098 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12099 We also need NewABI support. */
12100 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12106 reg1
= tc_get_register (0);
12107 SKIP_WHITESPACE ();
12108 if (*input_line_pointer
!= ',')
12110 as_bad (_("missing argument separator ',' for .cpsetup"));
12114 ++input_line_pointer
;
12115 SKIP_WHITESPACE ();
12116 if (*input_line_pointer
== '$')
12118 mips_cpreturn_register
= tc_get_register (0);
12119 mips_cpreturn_offset
= -1;
12123 mips_cpreturn_offset
= get_absolute_expression ();
12124 mips_cpreturn_register
= -1;
12126 SKIP_WHITESPACE ();
12127 if (*input_line_pointer
!= ',')
12129 as_bad (_("missing argument separator ',' for .cpsetup"));
12133 ++input_line_pointer
;
12134 SKIP_WHITESPACE ();
12135 expression (&ex_sym
);
12138 if (mips_cpreturn_register
== -1)
12140 ex_off
.X_op
= O_constant
;
12141 ex_off
.X_add_symbol
= NULL
;
12142 ex_off
.X_op_symbol
= NULL
;
12143 ex_off
.X_add_number
= mips_cpreturn_offset
;
12145 macro_build (&ex_off
, "sd", "t,o(b)", mips_gp_register
,
12146 BFD_RELOC_LO16
, SP
);
12149 macro_build (NULL
, "daddu", "d,v,t", mips_cpreturn_register
,
12150 mips_gp_register
, 0);
12152 /* Ensure there's room for the next two instructions, so that `f'
12153 doesn't end up with an address in the wrong frag. */
12156 macro_build (&ex_sym
, "lui", "t,u", mips_gp_register
, BFD_RELOC_GPREL16
);
12157 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12158 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12159 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12160 4, NULL
, 0, 0, BFD_RELOC_HI16_S
);
12163 macro_build (&ex_sym
, "addiu", "t,r,j", mips_gp_register
,
12164 mips_gp_register
, BFD_RELOC_GPREL16
);
12165 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12166 8, NULL
, 0, 0, BFD_RELOC_MIPS_SUB
);
12167 fix_new (frag_now
, f
- frag_now
->fr_literal
,
12168 4, NULL
, 0, 0, BFD_RELOC_LO16
);
12170 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", mips_gp_register
,
12171 mips_gp_register
, reg1
);
12174 demand_empty_rest_of_line ();
12178 s_cplocal (int ignore ATTRIBUTE_UNUSED
)
12180 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12181 .cplocal is ignored. */
12182 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12188 mips_gp_register
= tc_get_register (0);
12189 demand_empty_rest_of_line ();
12192 /* Handle the .cprestore pseudo-op. This stores $gp into a given
12193 offset from $sp. The offset is remembered, and after making a PIC
12194 call $gp is restored from that location. */
12197 s_cprestore (int ignore ATTRIBUTE_UNUSED
)
12201 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12202 .cprestore is ignored. */
12203 if (mips_pic
!= SVR4_PIC
|| HAVE_NEWABI
)
12209 mips_cprestore_offset
= get_absolute_expression ();
12210 mips_cprestore_valid
= 1;
12212 ex
.X_op
= O_constant
;
12213 ex
.X_add_symbol
= NULL
;
12214 ex
.X_op_symbol
= NULL
;
12215 ex
.X_add_number
= mips_cprestore_offset
;
12218 macro_build_ldst_constoffset (&ex
, ADDRESS_STORE_INSN
, mips_gp_register
,
12219 SP
, HAVE_64BIT_ADDRESSES
);
12222 demand_empty_rest_of_line ();
12225 /* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12226 was given in the preceding .cpsetup, it results in:
12227 ld $gp, offset($sp)
12229 If a register $reg2 was given there, it results in:
12230 daddu $gp, $reg2, $0
12233 s_cpreturn (int ignore ATTRIBUTE_UNUSED
)
12237 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12238 We also need NewABI support. */
12239 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12246 if (mips_cpreturn_register
== -1)
12248 ex
.X_op
= O_constant
;
12249 ex
.X_add_symbol
= NULL
;
12250 ex
.X_op_symbol
= NULL
;
12251 ex
.X_add_number
= mips_cpreturn_offset
;
12253 macro_build (&ex
, "ld", "t,o(b)", mips_gp_register
, BFD_RELOC_LO16
, SP
);
12256 macro_build (NULL
, "daddu", "d,v,t", mips_gp_register
,
12257 mips_cpreturn_register
, 0);
12260 demand_empty_rest_of_line ();
12263 /* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12264 code. It sets the offset to use in gp_rel relocations. */
12267 s_gpvalue (int ignore ATTRIBUTE_UNUSED
)
12269 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12270 We also need NewABI support. */
12271 if (mips_pic
!= SVR4_PIC
|| ! HAVE_NEWABI
)
12277 mips_gprel_offset
= get_absolute_expression ();
12279 demand_empty_rest_of_line ();
12282 /* Handle the .gpword pseudo-op. This is used when generating PIC
12283 code. It generates a 32 bit GP relative reloc. */
12286 s_gpword (int ignore ATTRIBUTE_UNUSED
)
12292 /* When not generating PIC code, this is treated as .word. */
12293 if (mips_pic
!= SVR4_PIC
)
12299 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12300 mips_emit_delays (TRUE
);
12302 mips_align (2, 0, label
);
12303 mips_clear_insn_labels ();
12307 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12309 as_bad (_("Unsupported use of .gpword"));
12310 ignore_rest_of_line ();
12314 md_number_to_chars (p
, 0, 4);
12315 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12316 BFD_RELOC_GPREL32
);
12318 demand_empty_rest_of_line ();
12322 s_gpdword (int ignore ATTRIBUTE_UNUSED
)
12328 /* When not generating PIC code, this is treated as .dword. */
12329 if (mips_pic
!= SVR4_PIC
)
12335 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
12336 mips_emit_delays (TRUE
);
12338 mips_align (3, 0, label
);
12339 mips_clear_insn_labels ();
12343 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
12345 as_bad (_("Unsupported use of .gpdword"));
12346 ignore_rest_of_line ();
12350 md_number_to_chars (p
, 0, 8);
12351 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, FALSE
,
12352 BFD_RELOC_GPREL32
);
12354 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12355 ex
.X_op
= O_absent
;
12356 ex
.X_add_symbol
= 0;
12357 ex
.X_add_number
= 0;
12358 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 8, &ex
, FALSE
,
12361 demand_empty_rest_of_line ();
12364 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
12365 tables in SVR4 PIC code. */
12368 s_cpadd (int ignore ATTRIBUTE_UNUSED
)
12372 /* This is ignored when not generating SVR4 PIC code. */
12373 if (mips_pic
!= SVR4_PIC
)
12379 /* Add $gp to the register named as an argument. */
12381 reg
= tc_get_register (0);
12382 macro_build (NULL
, ADDRESS_ADD_INSN
, "d,v,t", reg
, reg
, mips_gp_register
);
12385 demand_empty_rest_of_line ();
12388 /* Handle the .insn pseudo-op. This marks instruction labels in
12389 mips16 mode. This permits the linker to handle them specially,
12390 such as generating jalx instructions when needed. We also make
12391 them odd for the duration of the assembly, in order to generate the
12392 right sort of code. We will make them even in the adjust_symtab
12393 routine, while leaving them marked. This is convenient for the
12394 debugger and the disassembler. The linker knows to make them odd
12398 s_insn (int ignore ATTRIBUTE_UNUSED
)
12400 mips16_mark_labels ();
12402 demand_empty_rest_of_line ();
12405 /* Handle a .stabn directive. We need these in order to mark a label
12406 as being a mips16 text label correctly. Sometimes the compiler
12407 will emit a label, followed by a .stabn, and then switch sections.
12408 If the label and .stabn are in mips16 mode, then the label is
12409 really a mips16 text label. */
12412 s_mips_stab (int type
)
12415 mips16_mark_labels ();
12420 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12424 s_mips_weakext (int ignore ATTRIBUTE_UNUSED
)
12431 name
= input_line_pointer
;
12432 c
= get_symbol_end ();
12433 symbolP
= symbol_find_or_make (name
);
12434 S_SET_WEAK (symbolP
);
12435 *input_line_pointer
= c
;
12437 SKIP_WHITESPACE ();
12439 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
12441 if (S_IS_DEFINED (symbolP
))
12443 as_bad ("ignoring attempt to redefine symbol %s",
12444 S_GET_NAME (symbolP
));
12445 ignore_rest_of_line ();
12449 if (*input_line_pointer
== ',')
12451 ++input_line_pointer
;
12452 SKIP_WHITESPACE ();
12456 if (exp
.X_op
!= O_symbol
)
12458 as_bad ("bad .weakext directive");
12459 ignore_rest_of_line ();
12462 symbol_set_value_expression (symbolP
, &exp
);
12465 demand_empty_rest_of_line ();
12468 /* Parse a register string into a number. Called from the ECOFF code
12469 to parse .frame. The argument is non-zero if this is the frame
12470 register, so that we can record it in mips_frame_reg. */
12473 tc_get_register (int frame
)
12477 SKIP_WHITESPACE ();
12478 if (*input_line_pointer
++ != '$')
12480 as_warn (_("expected `$'"));
12483 else if (ISDIGIT (*input_line_pointer
))
12485 reg
= get_absolute_expression ();
12486 if (reg
< 0 || reg
>= 32)
12488 as_warn (_("Bad register number"));
12494 if (strncmp (input_line_pointer
, "ra", 2) == 0)
12497 input_line_pointer
+= 2;
12499 else if (strncmp (input_line_pointer
, "fp", 2) == 0)
12502 input_line_pointer
+= 2;
12504 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
12507 input_line_pointer
+= 2;
12509 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
12512 input_line_pointer
+= 2;
12514 else if (strncmp (input_line_pointer
, "at", 2) == 0)
12517 input_line_pointer
+= 2;
12519 else if (strncmp (input_line_pointer
, "kt0", 3) == 0)
12522 input_line_pointer
+= 3;
12524 else if (strncmp (input_line_pointer
, "kt1", 3) == 0)
12527 input_line_pointer
+= 3;
12529 else if (strncmp (input_line_pointer
, "zero", 4) == 0)
12532 input_line_pointer
+= 4;
12536 as_warn (_("Unrecognized register name"));
12538 while (ISALNUM(*input_line_pointer
))
12539 input_line_pointer
++;
12544 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
12545 mips_frame_reg_valid
= 1;
12546 mips_cprestore_valid
= 0;
12552 md_section_align (asection
*seg
, valueT addr
)
12554 int align
= bfd_get_section_alignment (stdoutput
, seg
);
12557 /* We don't need to align ELF sections to the full alignment.
12558 However, Irix 5 may prefer that we align them at least to a 16
12559 byte boundary. We don't bother to align the sections if we are
12560 targeted for an embedded system. */
12561 if (strcmp (TARGET_OS
, "elf") == 0)
12567 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
12570 /* Utility routine, called from above as well. If called while the
12571 input file is still being read, it's only an approximation. (For
12572 example, a symbol may later become defined which appeared to be
12573 undefined earlier.) */
12576 nopic_need_relax (symbolS
*sym
, int before_relaxing
)
12581 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
> 0)
12583 const char *symname
;
12586 /* Find out whether this symbol can be referenced off the $gp
12587 register. It can be if it is smaller than the -G size or if
12588 it is in the .sdata or .sbss section. Certain symbols can
12589 not be referenced off the $gp, although it appears as though
12591 symname
= S_GET_NAME (sym
);
12592 if (symname
!= (const char *) NULL
12593 && (strcmp (symname
, "eprol") == 0
12594 || strcmp (symname
, "etext") == 0
12595 || strcmp (symname
, "_gp") == 0
12596 || strcmp (symname
, "edata") == 0
12597 || strcmp (symname
, "_fbss") == 0
12598 || strcmp (symname
, "_fdata") == 0
12599 || strcmp (symname
, "_ftext") == 0
12600 || strcmp (symname
, "end") == 0
12601 || strcmp (symname
, "_gp_disp") == 0))
12603 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
12605 #ifndef NO_ECOFF_DEBUGGING
12606 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
12607 && (symbol_get_obj (sym
)->ecoff_extern_size
12608 <= g_switch_value
))
12610 /* We must defer this decision until after the whole
12611 file has been read, since there might be a .extern
12612 after the first use of this symbol. */
12613 || (before_relaxing
12614 #ifndef NO_ECOFF_DEBUGGING
12615 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
12617 && S_GET_VALUE (sym
) == 0)
12618 || (S_GET_VALUE (sym
) != 0
12619 && S_GET_VALUE (sym
) <= g_switch_value
)))
12623 const char *segname
;
12625 segname
= segment_name (S_GET_SEGMENT (sym
));
12626 assert (strcmp (segname
, ".lit8") != 0
12627 && strcmp (segname
, ".lit4") != 0);
12628 change
= (strcmp (segname
, ".sdata") != 0
12629 && strcmp (segname
, ".sbss") != 0
12630 && strncmp (segname
, ".sdata.", 7) != 0
12631 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
12636 /* We are not optimizing for the $gp register. */
12641 /* Return true if the given symbol should be considered local for SVR4 PIC. */
12644 pic_need_relax (symbolS
*sym
, asection
*segtype
)
12647 bfd_boolean linkonce
;
12649 /* Handle the case of a symbol equated to another symbol. */
12650 while (symbol_equated_reloc_p (sym
))
12654 /* It's possible to get a loop here in a badly written
12656 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
12662 symsec
= S_GET_SEGMENT (sym
);
12664 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
12666 if (symsec
!= segtype
&& ! S_IS_LOCAL (sym
))
12668 if ((bfd_get_section_flags (stdoutput
, symsec
) & SEC_LINK_ONCE
)
12672 /* The GNU toolchain uses an extension for ELF: a section
12673 beginning with the magic string .gnu.linkonce is a linkonce
12675 if (strncmp (segment_name (symsec
), ".gnu.linkonce",
12676 sizeof ".gnu.linkonce" - 1) == 0)
12680 /* This must duplicate the test in adjust_reloc_syms. */
12681 return (symsec
!= &bfd_und_section
12682 && symsec
!= &bfd_abs_section
12683 && ! bfd_is_com_section (symsec
)
12686 /* A global or weak symbol is treated as external. */
12687 && (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
12688 || (! S_IS_WEAK (sym
)
12689 && (! S_IS_EXTERNAL (sym
)
12690 || mips_pic
== EMBEDDED_PIC
)))
12696 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12697 extended opcode. SEC is the section the frag is in. */
12700 mips16_extended_frag (fragS
*fragp
, asection
*sec
, long stretch
)
12703 register const struct mips16_immed_operand
*op
;
12705 int mintiny
, maxtiny
;
12709 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
12711 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
12714 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
12715 op
= mips16_immed_operands
;
12716 while (op
->type
!= type
)
12719 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
12724 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
12727 maxtiny
= 1 << op
->nbits
;
12732 maxtiny
= (1 << op
->nbits
) - 1;
12737 mintiny
= - (1 << (op
->nbits
- 1));
12738 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
12741 sym_frag
= symbol_get_frag (fragp
->fr_symbol
);
12742 val
= S_GET_VALUE (fragp
->fr_symbol
);
12743 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
12749 /* We won't have the section when we are called from
12750 mips_relax_frag. However, we will always have been called
12751 from md_estimate_size_before_relax first. If this is a
12752 branch to a different section, we mark it as such. If SEC is
12753 NULL, and the frag is not marked, then it must be a branch to
12754 the same section. */
12757 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
12762 /* Must have been called from md_estimate_size_before_relax. */
12765 fragp
->fr_subtype
=
12766 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12768 /* FIXME: We should support this, and let the linker
12769 catch branches and loads that are out of range. */
12770 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
12771 _("unsupported PC relative reference to different section"));
12775 if (fragp
!= sym_frag
&& sym_frag
->fr_address
== 0)
12776 /* Assume non-extended on the first relaxation pass.
12777 The address we have calculated will be bogus if this is
12778 a forward branch to another frag, as the forward frag
12779 will have fr_address == 0. */
12783 /* In this case, we know for sure that the symbol fragment is in
12784 the same section. If the relax_marker of the symbol fragment
12785 differs from the relax_marker of this fragment, we have not
12786 yet adjusted the symbol fragment fr_address. We want to add
12787 in STRETCH in order to get a better estimate of the address.
12788 This particularly matters because of the shift bits. */
12790 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
12794 /* Adjust stretch for any alignment frag. Note that if have
12795 been expanding the earlier code, the symbol may be
12796 defined in what appears to be an earlier frag. FIXME:
12797 This doesn't handle the fr_subtype field, which specifies
12798 a maximum number of bytes to skip when doing an
12800 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
12802 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
12805 stretch
= - ((- stretch
)
12806 & ~ ((1 << (int) f
->fr_offset
) - 1));
12808 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
12817 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
12819 /* The base address rules are complicated. The base address of
12820 a branch is the following instruction. The base address of a
12821 PC relative load or add is the instruction itself, but if it
12822 is in a delay slot (in which case it can not be extended) use
12823 the address of the instruction whose delay slot it is in. */
12824 if (type
== 'p' || type
== 'q')
12828 /* If we are currently assuming that this frag should be
12829 extended, then, the current address is two bytes
12831 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
12834 /* Ignore the low bit in the target, since it will be set
12835 for a text label. */
12836 if ((val
& 1) != 0)
12839 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
12841 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
12844 val
-= addr
& ~ ((1 << op
->shift
) - 1);
12846 /* Branch offsets have an implicit 0 in the lowest bit. */
12847 if (type
== 'p' || type
== 'q')
12850 /* If any of the shifted bits are set, we must use an extended
12851 opcode. If the address depends on the size of this
12852 instruction, this can lead to a loop, so we arrange to always
12853 use an extended opcode. We only check this when we are in
12854 the main relaxation loop, when SEC is NULL. */
12855 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
12857 fragp
->fr_subtype
=
12858 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12862 /* If we are about to mark a frag as extended because the value
12863 is precisely maxtiny + 1, then there is a chance of an
12864 infinite loop as in the following code:
12869 In this case when the la is extended, foo is 0x3fc bytes
12870 away, so the la can be shrunk, but then foo is 0x400 away, so
12871 the la must be extended. To avoid this loop, we mark the
12872 frag as extended if it was small, and is about to become
12873 extended with a value of maxtiny + 1. */
12874 if (val
== ((maxtiny
+ 1) << op
->shift
)
12875 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
12878 fragp
->fr_subtype
=
12879 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
12883 else if (symsec
!= absolute_section
&& sec
!= NULL
)
12884 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
12886 if ((val
& ((1 << op
->shift
) - 1)) != 0
12887 || val
< (mintiny
<< op
->shift
)
12888 || val
> (maxtiny
<< op
->shift
))
12894 /* Compute the length of a branch sequence, and adjust the
12895 RELAX_BRANCH_TOOFAR bit accordingly. If FRAGP is NULL, the
12896 worst-case length is computed, with UPDATE being used to indicate
12897 whether an unconditional (-1), branch-likely (+1) or regular (0)
12898 branch is to be computed. */
12900 relaxed_branch_length (fragS
*fragp
, asection
*sec
, int update
)
12902 bfd_boolean toofar
;
12906 && S_IS_DEFINED (fragp
->fr_symbol
)
12907 && sec
== S_GET_SEGMENT (fragp
->fr_symbol
))
12912 val
= S_GET_VALUE (fragp
->fr_symbol
) + fragp
->fr_offset
;
12914 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
12918 toofar
= val
< - (0x8000 << 2) || val
>= (0x8000 << 2);
12921 /* If the symbol is not defined or it's in a different segment,
12922 assume the user knows what's going on and emit a short
12928 if (fragp
&& update
&& toofar
!= RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
12930 = RELAX_BRANCH_ENCODE (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
),
12931 RELAX_BRANCH_LIKELY (fragp
->fr_subtype
),
12932 RELAX_BRANCH_LINK (fragp
->fr_subtype
),
12938 if (fragp
? RELAX_BRANCH_LIKELY (fragp
->fr_subtype
) : (update
> 0))
12941 if (mips_pic
!= NO_PIC
)
12943 /* Additional space for PIC loading of target address. */
12945 if (mips_opts
.isa
== ISA_MIPS1
)
12946 /* Additional space for $at-stabilizing nop. */
12950 /* If branch is conditional. */
12951 if (fragp
? !RELAX_BRANCH_UNCOND (fragp
->fr_subtype
) : (update
>= 0))
12958 /* Estimate the size of a frag before relaxing. Unless this is the
12959 mips16, we are not really relaxing here, and the final size is
12960 encoded in the subtype information. For the mips16, we have to
12961 decide whether we are using an extended opcode or not. */
12964 md_estimate_size_before_relax (fragS
*fragp
, asection
*segtype
)
12968 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
12971 fragp
->fr_var
= relaxed_branch_length (fragp
, segtype
, FALSE
);
12973 return fragp
->fr_var
;
12976 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
12977 /* We don't want to modify the EXTENDED bit here; it might get us
12978 into infinite loops. We change it only in mips_relax_frag(). */
12979 return (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
) ? 4 : 2);
12981 if (mips_pic
== NO_PIC
)
12982 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
12983 else if (mips_pic
== SVR4_PIC
)
12984 change
= pic_need_relax (fragp
->fr_symbol
, segtype
);
12990 fragp
->fr_subtype
|= RELAX_USE_SECOND
;
12991 return -RELAX_FIRST (fragp
->fr_subtype
);
12994 return -RELAX_SECOND (fragp
->fr_subtype
);
12997 /* This is called to see whether a reloc against a defined symbol
12998 should be converted into a reloc against a section. Don't adjust
12999 MIPS16 jump relocations, so we don't have to worry about the format
13000 of the offset in the .o file. Don't adjust relocations against
13001 mips16 symbols, so that the linker can find them if it needs to set
13005 mips_fix_adjustable (fixS
*fixp
)
13007 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
13010 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
13011 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13014 if (fixp
->fx_addsy
== NULL
)
13018 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
13019 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
13020 && fixp
->fx_subsy
== NULL
)
13027 /* Translate internal representation of relocation info to BFD target
13031 tc_gen_reloc (asection
*section ATTRIBUTE_UNUSED
, fixS
*fixp
)
13033 static arelent
*retval
[4];
13035 bfd_reloc_code_real_type code
;
13037 memset (retval
, 0, sizeof(retval
));
13038 reloc
= retval
[0] = (arelent
*) xcalloc (1, sizeof (arelent
));
13039 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
13040 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
13041 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
13043 if (mips_pic
== EMBEDDED_PIC
13044 && SWITCH_TABLE (fixp
))
13046 /* For a switch table entry we use a special reloc. The addend
13047 is actually the difference between the reloc address and the
13049 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
13050 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
13051 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13052 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
13054 else if (fixp
->fx_pcrel
)
13056 bfd_vma pcrel_address
;
13058 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13059 high-part relocs is the address of the low-part reloc. */
13060 if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13062 assert (fixp
->fx_next
!= NULL
13063 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
13064 pcrel_address
= (fixp
->fx_next
->fx_where
13065 + fixp
->fx_next
->fx_frag
->fr_address
);
13068 pcrel_address
= reloc
->address
;
13070 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13072 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13073 Relocations want only the symbol offset. */
13074 reloc
->addend
= fixp
->fx_addnumber
+ pcrel_address
;
13076 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
13077 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
13079 /* We use a special addend for an internal RELLO or RELHI reloc. */
13080 if (symbol_section_p (fixp
->fx_addsy
))
13081 reloc
->addend
= pcrel_address
- S_GET_VALUE (fixp
->fx_subsy
);
13083 reloc
->addend
= fixp
->fx_addnumber
+ pcrel_address
;
13087 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
13088 /* A gruesome hack which is a result of the gruesome gas reloc
13090 reloc
->addend
= pcrel_address
;
13092 reloc
->addend
= -pcrel_address
;
13096 reloc
->addend
= fixp
->fx_addnumber
;
13098 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13099 entry to be used in the relocation's section offset. */
13100 if (! HAVE_NEWABI
&& fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
13102 reloc
->address
= reloc
->addend
;
13106 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13107 fixup_segment converted a non-PC relative reloc into a PC
13108 relative reloc. In such a case, we need to convert the reloc
13110 code
= fixp
->fx_r_type
;
13111 if (fixp
->fx_pcrel
)
13116 code
= BFD_RELOC_8_PCREL
;
13119 code
= BFD_RELOC_16_PCREL
;
13122 code
= BFD_RELOC_32_PCREL
;
13125 code
= BFD_RELOC_64_PCREL
;
13127 case BFD_RELOC_8_PCREL
:
13128 case BFD_RELOC_16_PCREL
:
13129 case BFD_RELOC_32_PCREL
:
13130 case BFD_RELOC_64_PCREL
:
13131 case BFD_RELOC_16_PCREL_S2
:
13132 case BFD_RELOC_PCREL_HI16_S
:
13133 case BFD_RELOC_PCREL_LO16
:
13136 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13137 _("Cannot make %s relocation PC relative"),
13138 bfd_get_reloc_code_name (code
));
13142 /* To support a PC relative reloc when generating embedded PIC code
13143 for ECOFF, we use a Cygnus extension. We check for that here to
13144 make sure that we don't let such a reloc escape normally. */
13145 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
13146 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
13147 && code
== BFD_RELOC_16_PCREL_S2
13148 && mips_pic
!= EMBEDDED_PIC
)
13149 reloc
->howto
= NULL
;
13151 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
13153 if (reloc
->howto
== NULL
)
13155 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
13156 _("Can not represent %s relocation in this object file format"),
13157 bfd_get_reloc_code_name (code
));
13164 /* Relax a machine dependent frag. This returns the amount by which
13165 the current size of the frag should change. */
13168 mips_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
13170 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13172 offsetT old_var
= fragp
->fr_var
;
13174 fragp
->fr_var
= relaxed_branch_length (fragp
, sec
, TRUE
);
13176 return fragp
->fr_var
- old_var
;
13179 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
13182 if (mips16_extended_frag (fragp
, NULL
, stretch
))
13184 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13186 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
13191 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13193 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
13200 /* Convert a machine dependent frag. */
13203 md_convert_frag (bfd
*abfd ATTRIBUTE_UNUSED
, segT asec
, fragS
*fragp
)
13205 if (RELAX_BRANCH_P (fragp
->fr_subtype
))
13208 unsigned long insn
;
13212 buf
= (bfd_byte
*)fragp
->fr_literal
+ fragp
->fr_fix
;
13214 if (target_big_endian
)
13215 insn
= bfd_getb32 (buf
);
13217 insn
= bfd_getl32 (buf
);
13219 if (!RELAX_BRANCH_TOOFAR (fragp
->fr_subtype
))
13221 /* We generate a fixup instead of applying it right now
13222 because, if there are linker relaxations, we're going to
13223 need the relocations. */
13224 exp
.X_op
= O_symbol
;
13225 exp
.X_add_symbol
= fragp
->fr_symbol
;
13226 exp
.X_add_number
= fragp
->fr_offset
;
13228 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13230 BFD_RELOC_16_PCREL_S2
);
13231 fixp
->fx_file
= fragp
->fr_file
;
13232 fixp
->fx_line
= fragp
->fr_line
;
13234 md_number_to_chars (buf
, insn
, 4);
13241 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13242 _("relaxed out-of-range branch into a jump"));
13244 if (RELAX_BRANCH_UNCOND (fragp
->fr_subtype
))
13247 if (!RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13249 /* Reverse the branch. */
13250 switch ((insn
>> 28) & 0xf)
13253 /* bc[0-3][tf]l? and bc1any[24][ft] instructions can
13254 have the condition reversed by tweaking a single
13255 bit, and their opcodes all have 0x4???????. */
13256 assert ((insn
& 0xf1000000) == 0x41000000);
13257 insn
^= 0x00010000;
13261 /* bltz 0x04000000 bgez 0x04010000
13262 bltzal 0x04100000 bgezal 0x04110000 */
13263 assert ((insn
& 0xfc0e0000) == 0x04000000);
13264 insn
^= 0x00010000;
13268 /* beq 0x10000000 bne 0x14000000
13269 blez 0x18000000 bgtz 0x1c000000 */
13270 insn
^= 0x04000000;
13278 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13280 /* Clear the and-link bit. */
13281 assert ((insn
& 0xfc1c0000) == 0x04100000);
13283 /* bltzal 0x04100000 bgezal 0x04110000
13284 bltzall 0x04120000 bgezall 0x04130000 */
13285 insn
&= ~0x00100000;
13288 /* Branch over the branch (if the branch was likely) or the
13289 full jump (not likely case). Compute the offset from the
13290 current instruction to branch to. */
13291 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13295 /* How many bytes in instructions we've already emitted? */
13296 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13297 /* How many bytes in instructions from here to the end? */
13298 i
= fragp
->fr_var
- i
;
13300 /* Convert to instruction count. */
13302 /* Branch counts from the next instruction. */
13305 /* Branch over the jump. */
13306 md_number_to_chars (buf
, insn
, 4);
13310 md_number_to_chars (buf
, 0, 4);
13313 if (RELAX_BRANCH_LIKELY (fragp
->fr_subtype
))
13315 /* beql $0, $0, 2f */
13317 /* Compute the PC offset from the current instruction to
13318 the end of the variable frag. */
13319 /* How many bytes in instructions we've already emitted? */
13320 i
= buf
- (bfd_byte
*)fragp
->fr_literal
- fragp
->fr_fix
;
13321 /* How many bytes in instructions from here to the end? */
13322 i
= fragp
->fr_var
- i
;
13323 /* Convert to instruction count. */
13325 /* Don't decrement i, because we want to branch over the
13329 md_number_to_chars (buf
, insn
, 4);
13332 md_number_to_chars (buf
, 0, 4);
13337 if (mips_pic
== NO_PIC
)
13340 insn
= (RELAX_BRANCH_LINK (fragp
->fr_subtype
)
13341 ? 0x0c000000 : 0x08000000);
13342 exp
.X_op
= O_symbol
;
13343 exp
.X_add_symbol
= fragp
->fr_symbol
;
13344 exp
.X_add_number
= fragp
->fr_offset
;
13346 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13347 4, &exp
, 0, BFD_RELOC_MIPS_JMP
);
13348 fixp
->fx_file
= fragp
->fr_file
;
13349 fixp
->fx_line
= fragp
->fr_line
;
13351 md_number_to_chars (buf
, insn
, 4);
13356 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13357 insn
= HAVE_64BIT_ADDRESSES
? 0xdf810000 : 0x8f810000;
13358 exp
.X_op
= O_symbol
;
13359 exp
.X_add_symbol
= fragp
->fr_symbol
;
13360 exp
.X_add_number
= fragp
->fr_offset
;
13362 if (fragp
->fr_offset
)
13364 exp
.X_add_symbol
= make_expr_symbol (&exp
);
13365 exp
.X_add_number
= 0;
13368 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13369 4, &exp
, 0, BFD_RELOC_MIPS_GOT16
);
13370 fixp
->fx_file
= fragp
->fr_file
;
13371 fixp
->fx_line
= fragp
->fr_line
;
13373 md_number_to_chars (buf
, insn
, 4);
13376 if (mips_opts
.isa
== ISA_MIPS1
)
13379 md_number_to_chars (buf
, 0, 4);
13383 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13384 insn
= HAVE_64BIT_ADDRESSES
? 0x64210000 : 0x24210000;
13386 fixp
= fix_new_exp (fragp
, buf
- (bfd_byte
*)fragp
->fr_literal
,
13387 4, &exp
, 0, BFD_RELOC_LO16
);
13388 fixp
->fx_file
= fragp
->fr_file
;
13389 fixp
->fx_line
= fragp
->fr_line
;
13391 md_number_to_chars (buf
, insn
, 4);
13395 if (RELAX_BRANCH_LINK (fragp
->fr_subtype
))
13400 md_number_to_chars (buf
, insn
, 4);
13405 assert (buf
== (bfd_byte
*)fragp
->fr_literal
13406 + fragp
->fr_fix
+ fragp
->fr_var
);
13408 fragp
->fr_fix
+= fragp
->fr_var
;
13413 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
13416 register const struct mips16_immed_operand
*op
;
13417 bfd_boolean small
, ext
;
13420 unsigned long insn
;
13421 bfd_boolean use_extend
;
13422 unsigned short extend
;
13424 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
13425 op
= mips16_immed_operands
;
13426 while (op
->type
!= type
)
13429 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
13440 resolve_symbol_value (fragp
->fr_symbol
);
13441 val
= S_GET_VALUE (fragp
->fr_symbol
);
13446 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
13448 /* The rules for the base address of a PC relative reloc are
13449 complicated; see mips16_extended_frag. */
13450 if (type
== 'p' || type
== 'q')
13455 /* Ignore the low bit in the target, since it will be
13456 set for a text label. */
13457 if ((val
& 1) != 0)
13460 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
13462 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
13465 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
13468 /* Make sure the section winds up with the alignment we have
13471 record_alignment (asec
, op
->shift
);
13475 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
13476 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
13477 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
13478 _("extended instruction in delay slot"));
13480 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
13482 if (target_big_endian
)
13483 insn
= bfd_getb16 (buf
);
13485 insn
= bfd_getl16 (buf
);
13487 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
13488 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
13489 small
, ext
, &insn
, &use_extend
, &extend
);
13493 md_number_to_chars (buf
, 0xf000 | extend
, 2);
13494 fragp
->fr_fix
+= 2;
13498 md_number_to_chars (buf
, insn
, 2);
13499 fragp
->fr_fix
+= 2;
13507 first
= RELAX_FIRST (fragp
->fr_subtype
);
13508 second
= RELAX_SECOND (fragp
->fr_subtype
);
13509 fixp
= (fixS
*) fragp
->fr_opcode
;
13511 /* Possibly emit a warning if we've chosen the longer option. */
13512 if (((fragp
->fr_subtype
& RELAX_USE_SECOND
) != 0)
13513 == ((fragp
->fr_subtype
& RELAX_SECOND_LONGER
) != 0))
13515 const char *msg
= macro_warning (fragp
->fr_subtype
);
13517 as_warn_where (fragp
->fr_file
, fragp
->fr_line
, msg
);
13520 /* Go through all the fixups for the first sequence. Disable them
13521 (by marking them as done) if we're going to use the second
13522 sequence instead. */
13524 && fixp
->fx_frag
== fragp
13525 && fixp
->fx_where
< fragp
->fr_fix
- second
)
13527 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13529 fixp
= fixp
->fx_next
;
13532 /* Go through the fixups for the second sequence. Disable them if
13533 we're going to use the first sequence, otherwise adjust their
13534 addresses to account for the relaxation. */
13535 while (fixp
&& fixp
->fx_frag
== fragp
)
13537 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13538 fixp
->fx_where
-= first
;
13541 fixp
= fixp
->fx_next
;
13544 /* Now modify the frag contents. */
13545 if (fragp
->fr_subtype
& RELAX_USE_SECOND
)
13549 start
= fragp
->fr_literal
+ fragp
->fr_fix
- first
- second
;
13550 memmove (start
, start
+ first
, second
);
13551 fragp
->fr_fix
-= first
;
13554 fragp
->fr_fix
-= second
;
13560 /* This function is called after the relocs have been generated.
13561 We've been storing mips16 text labels as odd. Here we convert them
13562 back to even for the convenience of the debugger. */
13565 mips_frob_file_after_relocs (void)
13568 unsigned int count
, i
;
13570 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
13573 syms
= bfd_get_outsymbols (stdoutput
);
13574 count
= bfd_get_symcount (stdoutput
);
13575 for (i
= 0; i
< count
; i
++, syms
++)
13577 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
13578 && ((*syms
)->value
& 1) != 0)
13580 (*syms
)->value
&= ~1;
13581 /* If the symbol has an odd size, it was probably computed
13582 incorrectly, so adjust that as well. */
13583 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
13584 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
13591 /* This function is called whenever a label is defined. It is used
13592 when handling branch delays; if a branch has a label, we assume we
13593 can not move it. */
13596 mips_define_label (symbolS
*sym
)
13598 struct insn_label_list
*l
;
13600 if (free_insn_labels
== NULL
)
13601 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
13604 l
= free_insn_labels
;
13605 free_insn_labels
= l
->next
;
13609 l
->next
= insn_labels
;
13613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13615 /* Some special processing for a MIPS ELF file. */
13618 mips_elf_final_processing (void)
13620 /* Write out the register information. */
13621 if (mips_abi
!= N64_ABI
)
13625 s
.ri_gprmask
= mips_gprmask
;
13626 s
.ri_cprmask
[0] = mips_cprmask
[0];
13627 s
.ri_cprmask
[1] = mips_cprmask
[1];
13628 s
.ri_cprmask
[2] = mips_cprmask
[2];
13629 s
.ri_cprmask
[3] = mips_cprmask
[3];
13630 /* The gp_value field is set by the MIPS ELF backend. */
13632 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
13633 ((Elf32_External_RegInfo
*)
13634 mips_regmask_frag
));
13638 Elf64_Internal_RegInfo s
;
13640 s
.ri_gprmask
= mips_gprmask
;
13642 s
.ri_cprmask
[0] = mips_cprmask
[0];
13643 s
.ri_cprmask
[1] = mips_cprmask
[1];
13644 s
.ri_cprmask
[2] = mips_cprmask
[2];
13645 s
.ri_cprmask
[3] = mips_cprmask
[3];
13646 /* The gp_value field is set by the MIPS ELF backend. */
13648 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
13649 ((Elf64_External_RegInfo
*)
13650 mips_regmask_frag
));
13653 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
13654 sort of BFD interface for this. */
13655 if (mips_any_noreorder
)
13656 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
13657 if (mips_pic
!= NO_PIC
)
13659 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
13660 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13663 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_CPIC
;
13665 /* Set MIPS ELF flags for ASEs. */
13666 if (file_ase_mips16
)
13667 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_M16
;
13668 #if 0 /* XXX FIXME */
13669 if (file_ase_mips3d
)
13670 elf_elfheader (stdoutput
)->e_flags
|= ???;
13673 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ARCH_ASE_MDMX
;
13675 /* Set the MIPS ELF ABI flags. */
13676 if (mips_abi
== O32_ABI
&& USE_E_MIPS_ABI_O32
)
13677 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
13678 else if (mips_abi
== O64_ABI
)
13679 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
13680 else if (mips_abi
== EABI_ABI
)
13682 if (!file_mips_gp32
)
13683 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
13685 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
13687 else if (mips_abi
== N32_ABI
)
13688 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_ABI2
;
13690 /* Nothing to do for N64_ABI. */
13692 if (mips_32bitmode
)
13693 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
13696 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13698 typedef struct proc
{
13700 unsigned long reg_mask
;
13701 unsigned long reg_offset
;
13702 unsigned long fpreg_mask
;
13703 unsigned long fpreg_offset
;
13704 unsigned long frame_offset
;
13705 unsigned long frame_reg
;
13706 unsigned long pc_reg
;
13709 static procS cur_proc
;
13710 static procS
*cur_proc_ptr
;
13711 static int numprocs
;
13713 /* Fill in an rs_align_code fragment. */
13716 mips_handle_align (fragS
*fragp
)
13718 if (fragp
->fr_type
!= rs_align_code
)
13721 if (mips_opts
.mips16
)
13723 static const unsigned char be_nop
[] = { 0x65, 0x00 };
13724 static const unsigned char le_nop
[] = { 0x00, 0x65 };
13729 bytes
= fragp
->fr_next
->fr_address
- fragp
->fr_address
- fragp
->fr_fix
;
13730 p
= fragp
->fr_literal
+ fragp
->fr_fix
;
13738 memcpy (p
, (target_big_endian
? be_nop
: le_nop
), 2);
13742 /* For mips32, a nop is a zero, which we trivially get by doing nothing. */
13746 md_obj_begin (void)
13753 /* check for premature end, nesting errors, etc */
13755 as_warn (_("missing .end at end of assembly"));
13764 if (*input_line_pointer
== '-')
13766 ++input_line_pointer
;
13769 if (!ISDIGIT (*input_line_pointer
))
13770 as_bad (_("expected simple number"));
13771 if (input_line_pointer
[0] == '0')
13773 if (input_line_pointer
[1] == 'x')
13775 input_line_pointer
+= 2;
13776 while (ISXDIGIT (*input_line_pointer
))
13779 val
|= hex_value (*input_line_pointer
++);
13781 return negative
? -val
: val
;
13785 ++input_line_pointer
;
13786 while (ISDIGIT (*input_line_pointer
))
13789 val
|= *input_line_pointer
++ - '0';
13791 return negative
? -val
: val
;
13794 if (!ISDIGIT (*input_line_pointer
))
13796 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
13797 *input_line_pointer
, *input_line_pointer
);
13798 as_warn (_("invalid number"));
13801 while (ISDIGIT (*input_line_pointer
))
13804 val
+= *input_line_pointer
++ - '0';
13806 return negative
? -val
: val
;
13809 /* The .file directive; just like the usual .file directive, but there
13810 is an initial number which is the ECOFF file index. In the non-ECOFF
13811 case .file implies DWARF-2. */
13814 s_mips_file (int x ATTRIBUTE_UNUSED
)
13816 static int first_file_directive
= 0;
13818 if (ECOFF_DEBUGGING
)
13827 filename
= dwarf2_directive_file (0);
13829 /* Versions of GCC up to 3.1 start files with a ".file"
13830 directive even for stabs output. Make sure that this
13831 ".file" is handled. Note that you need a version of GCC
13832 after 3.1 in order to support DWARF-2 on MIPS. */
13833 if (filename
!= NULL
&& ! first_file_directive
)
13835 (void) new_logical_line (filename
, -1);
13836 s_app_file_string (filename
);
13838 first_file_directive
= 1;
13842 /* The .loc directive, implying DWARF-2. */
13845 s_mips_loc (int x ATTRIBUTE_UNUSED
)
13847 if (!ECOFF_DEBUGGING
)
13848 dwarf2_directive_loc (0);
13851 /* The .end directive. */
13854 s_mips_end (int x ATTRIBUTE_UNUSED
)
13858 /* Following functions need their own .frame and .cprestore directives. */
13859 mips_frame_reg_valid
= 0;
13860 mips_cprestore_valid
= 0;
13862 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
13865 demand_empty_rest_of_line ();
13870 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13871 as_warn (_(".end not in text section"));
13875 as_warn (_(".end directive without a preceding .ent directive."));
13876 demand_empty_rest_of_line ();
13882 assert (S_GET_NAME (p
));
13883 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
13884 as_warn (_(".end symbol does not match .ent symbol."));
13886 if (debug_type
== DEBUG_STABS
)
13887 stabs_generate_asm_endfunc (S_GET_NAME (p
),
13891 as_warn (_(".end directive missing or unknown symbol"));
13894 /* Generate a .pdr section. */
13895 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
13898 segT saved_seg
= now_seg
;
13899 subsegT saved_subseg
= now_subseg
;
13904 dot
= frag_now_fix ();
13906 #ifdef md_flush_pending_output
13907 md_flush_pending_output ();
13911 subseg_set (pdr_seg
, 0);
13913 /* Write the symbol. */
13914 exp
.X_op
= O_symbol
;
13915 exp
.X_add_symbol
= p
;
13916 exp
.X_add_number
= 0;
13917 emit_expr (&exp
, 4);
13919 fragp
= frag_more (7 * 4);
13921 md_number_to_chars (fragp
, cur_proc_ptr
->reg_mask
, 4);
13922 md_number_to_chars (fragp
+ 4, cur_proc_ptr
->reg_offset
, 4);
13923 md_number_to_chars (fragp
+ 8, cur_proc_ptr
->fpreg_mask
, 4);
13924 md_number_to_chars (fragp
+ 12, cur_proc_ptr
->fpreg_offset
, 4);
13925 md_number_to_chars (fragp
+ 16, cur_proc_ptr
->frame_offset
, 4);
13926 md_number_to_chars (fragp
+ 20, cur_proc_ptr
->frame_reg
, 4);
13927 md_number_to_chars (fragp
+ 24, cur_proc_ptr
->pc_reg
, 4);
13929 subseg_set (saved_seg
, saved_subseg
);
13931 #endif /* OBJ_ELF */
13933 cur_proc_ptr
= NULL
;
13936 /* The .aent and .ent directives. */
13939 s_mips_ent (int aent
)
13943 symbolP
= get_symbol ();
13944 if (*input_line_pointer
== ',')
13945 ++input_line_pointer
;
13946 SKIP_WHITESPACE ();
13947 if (ISDIGIT (*input_line_pointer
)
13948 || *input_line_pointer
== '-')
13951 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) == 0)
13952 as_warn (_(".ent or .aent not in text section."));
13954 if (!aent
&& cur_proc_ptr
)
13955 as_warn (_("missing .end"));
13959 /* This function needs its own .frame and .cprestore directives. */
13960 mips_frame_reg_valid
= 0;
13961 mips_cprestore_valid
= 0;
13963 cur_proc_ptr
= &cur_proc
;
13964 memset (cur_proc_ptr
, '\0', sizeof (procS
));
13966 cur_proc_ptr
->isym
= symbolP
;
13968 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
13972 if (debug_type
== DEBUG_STABS
)
13973 stabs_generate_asm_func (S_GET_NAME (symbolP
),
13974 S_GET_NAME (symbolP
));
13977 demand_empty_rest_of_line ();
13980 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
13981 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
13982 s_mips_frame is used so that we can set the PDR information correctly.
13983 We can't use the ecoff routines because they make reference to the ecoff
13984 symbol table (in the mdebug section). */
13987 s_mips_frame (int ignore ATTRIBUTE_UNUSED
)
13990 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
13994 if (cur_proc_ptr
== (procS
*) NULL
)
13996 as_warn (_(".frame outside of .ent"));
13997 demand_empty_rest_of_line ();
14001 cur_proc_ptr
->frame_reg
= tc_get_register (1);
14003 SKIP_WHITESPACE ();
14004 if (*input_line_pointer
++ != ','
14005 || get_absolute_expression_and_terminator (&val
) != ',')
14007 as_warn (_("Bad .frame directive"));
14008 --input_line_pointer
;
14009 demand_empty_rest_of_line ();
14013 cur_proc_ptr
->frame_offset
= val
;
14014 cur_proc_ptr
->pc_reg
= tc_get_register (0);
14016 demand_empty_rest_of_line ();
14019 #endif /* OBJ_ELF */
14023 /* The .fmask and .mask directives. If the mdebug section is present
14024 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
14025 embedded targets, s_mips_mask is used so that we can set the PDR
14026 information correctly. We can't use the ecoff routines because they
14027 make reference to the ecoff symbol table (in the mdebug section). */
14030 s_mips_mask (int reg_type
)
14033 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
&& ! ECOFF_DEBUGGING
)
14037 if (cur_proc_ptr
== (procS
*) NULL
)
14039 as_warn (_(".mask/.fmask outside of .ent"));
14040 demand_empty_rest_of_line ();
14044 if (get_absolute_expression_and_terminator (&mask
) != ',')
14046 as_warn (_("Bad .mask/.fmask directive"));
14047 --input_line_pointer
;
14048 demand_empty_rest_of_line ();
14052 off
= get_absolute_expression ();
14054 if (reg_type
== 'F')
14056 cur_proc_ptr
->fpreg_mask
= mask
;
14057 cur_proc_ptr
->fpreg_offset
= off
;
14061 cur_proc_ptr
->reg_mask
= mask
;
14062 cur_proc_ptr
->reg_offset
= off
;
14065 demand_empty_rest_of_line ();
14068 #endif /* OBJ_ELF */
14069 s_ignore (reg_type
);
14072 /* The .loc directive. */
14082 assert (now_seg
== text_section
);
14084 lineno
= get_number ();
14085 addroff
= frag_now_fix ();
14087 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
14088 S_SET_TYPE (symbolP
, N_SLINE
);
14089 S_SET_OTHER (symbolP
, 0);
14090 S_SET_DESC (symbolP
, lineno
);
14091 symbolP
->sy_segment
= now_seg
;
14095 /* A table describing all the processors gas knows about. Names are
14096 matched in the order listed.
14098 To ease comparison, please keep this table in the same order as
14099 gcc's mips_cpu_info_table[]. */
14100 static const struct mips_cpu_info mips_cpu_info_table
[] =
14102 /* Entries for generic ISAs */
14103 { "mips1", 1, ISA_MIPS1
, CPU_R3000
},
14104 { "mips2", 1, ISA_MIPS2
, CPU_R6000
},
14105 { "mips3", 1, ISA_MIPS3
, CPU_R4000
},
14106 { "mips4", 1, ISA_MIPS4
, CPU_R8000
},
14107 { "mips5", 1, ISA_MIPS5
, CPU_MIPS5
},
14108 { "mips32", 1, ISA_MIPS32
, CPU_MIPS32
},
14109 { "mips32r2", 1, ISA_MIPS32R2
, CPU_MIPS32R2
},
14110 { "mips64", 1, ISA_MIPS64
, CPU_MIPS64
},
14111 { "mips64r2", 1, ISA_MIPS64R2
, CPU_MIPS64R2
},
14114 { "r3000", 0, ISA_MIPS1
, CPU_R3000
},
14115 { "r2000", 0, ISA_MIPS1
, CPU_R3000
},
14116 { "r3900", 0, ISA_MIPS1
, CPU_R3900
},
14119 { "r6000", 0, ISA_MIPS2
, CPU_R6000
},
14122 { "r4000", 0, ISA_MIPS3
, CPU_R4000
},
14123 { "r4010", 0, ISA_MIPS2
, CPU_R4010
},
14124 { "vr4100", 0, ISA_MIPS3
, CPU_VR4100
},
14125 { "vr4111", 0, ISA_MIPS3
, CPU_R4111
},
14126 { "vr4120", 0, ISA_MIPS3
, CPU_VR4120
},
14127 { "vr4130", 0, ISA_MIPS3
, CPU_VR4120
},
14128 { "vr4181", 0, ISA_MIPS3
, CPU_R4111
},
14129 { "vr4300", 0, ISA_MIPS3
, CPU_R4300
},
14130 { "r4400", 0, ISA_MIPS3
, CPU_R4400
},
14131 { "r4600", 0, ISA_MIPS3
, CPU_R4600
},
14132 { "orion", 0, ISA_MIPS3
, CPU_R4600
},
14133 { "r4650", 0, ISA_MIPS3
, CPU_R4650
},
14136 { "r8000", 0, ISA_MIPS4
, CPU_R8000
},
14137 { "r10000", 0, ISA_MIPS4
, CPU_R10000
},
14138 { "r12000", 0, ISA_MIPS4
, CPU_R12000
},
14139 { "vr5000", 0, ISA_MIPS4
, CPU_R5000
},
14140 { "vr5400", 0, ISA_MIPS4
, CPU_VR5400
},
14141 { "vr5500", 0, ISA_MIPS4
, CPU_VR5500
},
14142 { "rm5200", 0, ISA_MIPS4
, CPU_R5000
},
14143 { "rm5230", 0, ISA_MIPS4
, CPU_R5000
},
14144 { "rm5231", 0, ISA_MIPS4
, CPU_R5000
},
14145 { "rm5261", 0, ISA_MIPS4
, CPU_R5000
},
14146 { "rm5721", 0, ISA_MIPS4
, CPU_R5000
},
14147 { "rm7000", 0, ISA_MIPS4
, CPU_RM7000
},
14148 { "rm9000", 0, ISA_MIPS4
, CPU_RM7000
},
14151 { "4kc", 0, ISA_MIPS32
, CPU_MIPS32
},
14152 { "4km", 0, ISA_MIPS32
, CPU_MIPS32
},
14153 { "4kp", 0, ISA_MIPS32
, CPU_MIPS32
},
14156 { "5kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14157 { "20kc", 0, ISA_MIPS64
, CPU_MIPS64
},
14159 /* Broadcom SB-1 CPU core */
14160 { "sb1", 0, ISA_MIPS64
, CPU_SB1
},
14167 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14168 with a final "000" replaced by "k". Ignore case.
14170 Note: this function is shared between GCC and GAS. */
14173 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
14175 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
14176 given
++, canonical
++;
14178 return ((*given
== 0 && *canonical
== 0)
14179 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
14183 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14184 CPU name. We've traditionally allowed a lot of variation here.
14186 Note: this function is shared between GCC and GAS. */
14189 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
14191 /* First see if the name matches exactly, or with a final "000"
14192 turned into "k". */
14193 if (mips_strict_matching_cpu_name_p (canonical
, given
))
14196 /* If not, try comparing based on numerical designation alone.
14197 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14198 if (TOLOWER (*given
) == 'r')
14200 if (!ISDIGIT (*given
))
14203 /* Skip over some well-known prefixes in the canonical name,
14204 hoping to find a number there too. */
14205 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
14207 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
14209 else if (TOLOWER (canonical
[0]) == 'r')
14212 return mips_strict_matching_cpu_name_p (canonical
, given
);
14216 /* Parse an option that takes the name of a processor as its argument.
14217 OPTION is the name of the option and CPU_STRING is the argument.
14218 Return the corresponding processor enumeration if the CPU_STRING is
14219 recognized, otherwise report an error and return null.
14221 A similar function exists in GCC. */
14223 static const struct mips_cpu_info
*
14224 mips_parse_cpu (const char *option
, const char *cpu_string
)
14226 const struct mips_cpu_info
*p
;
14228 /* 'from-abi' selects the most compatible architecture for the given
14229 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14230 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14231 version. Look first at the -mgp options, if given, otherwise base
14232 the choice on MIPS_DEFAULT_64BIT.
14234 Treat NO_ABI like the EABIs. One reason to do this is that the
14235 plain 'mips' and 'mips64' configs have 'from-abi' as their default
14236 architecture. This code picks MIPS I for 'mips' and MIPS III for
14237 'mips64', just as we did in the days before 'from-abi'. */
14238 if (strcasecmp (cpu_string
, "from-abi") == 0)
14240 if (ABI_NEEDS_32BIT_REGS (mips_abi
))
14241 return mips_cpu_info_from_isa (ISA_MIPS1
);
14243 if (ABI_NEEDS_64BIT_REGS (mips_abi
))
14244 return mips_cpu_info_from_isa (ISA_MIPS3
);
14246 if (file_mips_gp32
>= 0)
14247 return mips_cpu_info_from_isa (file_mips_gp32
? ISA_MIPS1
: ISA_MIPS3
);
14249 return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT
14254 /* 'default' has traditionally been a no-op. Probably not very useful. */
14255 if (strcasecmp (cpu_string
, "default") == 0)
14258 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
14259 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
14262 as_bad ("Bad value (%s) for %s", cpu_string
, option
);
14266 /* Return the canonical processor information for ISA (a member of the
14267 ISA_MIPS* enumeration). */
14269 static const struct mips_cpu_info
*
14270 mips_cpu_info_from_isa (int isa
)
14274 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14275 if (mips_cpu_info_table
[i
].is_isa
14276 && isa
== mips_cpu_info_table
[i
].isa
)
14277 return (&mips_cpu_info_table
[i
]);
14282 static const struct mips_cpu_info
*
14283 mips_cpu_info_from_arch (int arch
)
14287 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14288 if (arch
== mips_cpu_info_table
[i
].cpu
)
14289 return (&mips_cpu_info_table
[i
]);
14295 show (FILE *stream
, const char *string
, int *col_p
, int *first_p
)
14299 fprintf (stream
, "%24s", "");
14304 fprintf (stream
, ", ");
14308 if (*col_p
+ strlen (string
) > 72)
14310 fprintf (stream
, "\n%24s", "");
14314 fprintf (stream
, "%s", string
);
14315 *col_p
+= strlen (string
);
14321 md_show_usage (FILE *stream
)
14326 fprintf (stream
, _("\
14328 -membedded-pic generate embedded position independent code\n\
14329 -EB generate big endian output\n\
14330 -EL generate little endian output\n\
14331 -g, -g2 do not remove unneeded NOPs or swap branches\n\
14332 -G NUM allow referencing objects up to NUM bytes\n\
14333 implicitly with the gp register [default 8]\n"));
14334 fprintf (stream
, _("\
14335 -mips1 generate MIPS ISA I instructions\n\
14336 -mips2 generate MIPS ISA II instructions\n\
14337 -mips3 generate MIPS ISA III instructions\n\
14338 -mips4 generate MIPS ISA IV instructions\n\
14339 -mips5 generate MIPS ISA V instructions\n\
14340 -mips32 generate MIPS32 ISA instructions\n\
14341 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
14342 -mips64 generate MIPS64 ISA instructions\n\
14343 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
14344 -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n"));
14348 for (i
= 0; mips_cpu_info_table
[i
].name
!= NULL
; i
++)
14349 show (stream
, mips_cpu_info_table
[i
].name
, &column
, &first
);
14350 show (stream
, "from-abi", &column
, &first
);
14351 fputc ('\n', stream
);
14353 fprintf (stream
, _("\
14354 -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated.\n\
14355 -no-mCPU don't generate code specific to CPU.\n\
14356 For -mCPU and -no-mCPU, CPU must be one of:\n"));
14360 show (stream
, "3900", &column
, &first
);
14361 show (stream
, "4010", &column
, &first
);
14362 show (stream
, "4100", &column
, &first
);
14363 show (stream
, "4650", &column
, &first
);
14364 fputc ('\n', stream
);
14366 fprintf (stream
, _("\
14367 -mips16 generate mips16 instructions\n\
14368 -no-mips16 do not generate mips16 instructions\n"));
14369 fprintf (stream
, _("\
14370 -mfix-vr4120 work around certain VR4120 errata\n\
14371 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14372 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14373 -O0 remove unneeded NOPs, do not swap branches\n\
14374 -O remove unneeded NOPs and swap branches\n\
14375 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
14376 --trap, --no-break trap exception on div by 0 and mult overflow\n\
14377 --break, --no-trap break exception on div by 0 and mult overflow\n"));
14379 fprintf (stream
, _("\
14380 -KPIC, -call_shared generate SVR4 position independent code\n\
14381 -non_shared do not generate position independent code\n\
14382 -xgot assume a 32 bit GOT\n\
14383 -mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14384 -mabi=ABI create ABI conformant object file for:\n"));
14388 show (stream
, "32", &column
, &first
);
14389 show (stream
, "o64", &column
, &first
);
14390 show (stream
, "n32", &column
, &first
);
14391 show (stream
, "64", &column
, &first
);
14392 show (stream
, "eabi", &column
, &first
);
14394 fputc ('\n', stream
);
14396 fprintf (stream
, _("\
14397 -32 create o32 ABI object file (default)\n\
14398 -n32 create n32 ABI object file\n\
14399 -64 create 64 ABI object file\n"));
14404 mips_dwarf2_format (void)
14406 if (mips_abi
== N64_ABI
)
14409 return dwarf2_format_64bit_irix
;
14411 return dwarf2_format_64bit
;
14415 return dwarf2_format_32bit
;
14419 mips_dwarf2_addr_size (void)
14421 if (mips_abi
== N64_ABI
)