1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
41 /* Clean up namespace so we can include obj-elf.h too. */
42 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
43 #undef OBJ_PROCESS_STAB
49 #undef TARGET_SYMBOL_FIELDS
51 #undef obj_frob_file_after_relocs
52 #undef obj_frob_symbol
54 #undef obj_sec_sym_ok_for_reloc
57 /* Fix any of them that we actually care about. */
59 #define OUTPUT_FLAVOR mips_output_flavor()
66 #ifndef ECOFF_DEBUGGING
67 #define NO_ECOFF_DEBUGGING
68 #define ECOFF_DEBUGGING 0
73 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
74 static char *mips_regmask_frag
;
79 #define PIC_CALL_REG 25
87 #define ILLEGAL_REG (32)
89 extern int target_big_endian
;
91 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
92 32 bit ABI. This has no meaning for ECOFF. */
95 /* The default target format to use. */
99 switch (OUTPUT_FLAVOR
)
101 case bfd_target_aout_flavour
:
102 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
103 case bfd_target_ecoff_flavour
:
104 return target_big_endian
? "ecoff-bigmips" : "ecoff-littlemips";
105 case bfd_target_elf_flavour
:
106 return (target_big_endian
107 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
108 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
114 /* The name of the readonly data section. */
115 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
117 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
119 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
123 /* These variables are filled in with the masks of registers used.
124 The object format code reads them and puts them in the appropriate
126 unsigned long mips_gprmask
;
127 unsigned long mips_cprmask
[4];
129 /* MIPS ISA (Instruction Set Architecture) level (may be changed
130 temporarily using .set mipsN). */
131 static int mips_isa
= -1;
133 /* MIPS ISA we are using for this output file. */
134 static int file_mips_isa
;
136 /* Whether we are assembling for the mips16 processor. */
137 static int mips16
= -1;
139 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
140 static int mips_cpu
= -1;
142 /* Whether the 4650 instructions (mad/madu) are permitted. */
143 static int mips_4650
= -1;
145 /* Whether the 4010 instructions are permitted. */
146 static int mips_4010
= -1;
148 /* Whether the 4100 MADD16 and DMADD16 are permitted. */
149 static int mips_4100
= -1;
151 /* start-sanitize-r5900 */
152 /* Whether Toshiba r5900 instructions are permitted. */
153 static int mips_5900
= -1;
154 /* end-sanitize-r5900 */
156 /* Whether the processor uses hardware interlocks, and thus does not
157 require nops to be inserted. */
158 static int interlocks
= -1;
160 /* As with "interlocks" this is used by hardware that has FP
161 (co-processor) interlocks. */
162 static int cop_interlocks
= -1;
164 /* MIPS PIC level. */
168 /* Do not generate PIC code. */
171 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
172 not sure what it is supposed to do. */
175 /* Generate PIC code as in the SVR4 MIPS ABI. */
178 /* Generate PIC code without using a global offset table: the data
179 segment has a maximum size of 64K, all data references are off
180 the $gp register, and all text references are PC relative. This
181 is used on some embedded systems. */
185 static enum mips_pic_level mips_pic
;
187 /* 1 if we should generate 32 bit offsets from the GP register in
188 SVR4_PIC mode. Currently has no meaning in other modes. */
189 static int mips_big_got
;
191 /* 1 if trap instructions should used for overflow rather than break
193 static int mips_trap
;
195 /* 1 if we should autoextend mips16 instructions. */
196 static int mips16_autoextend
= 1;
198 static int mips_warn_about_macros
;
199 static int mips_noreorder
;
200 static int mips_any_noreorder
;
201 static int mips_nomove
;
202 static int mips_noat
;
203 static int mips_nobopt
;
205 /* The size of the small data section. */
206 static int g_switch_value
= 8;
207 /* Whether the -G option was used. */
208 static int g_switch_seen
= 0;
213 /* If we can determine in advance that GP optimization won't be
214 possible, we can skip the relaxation stuff that tries to produce
215 GP-relative references. This makes delay slot optimization work
218 This function can only provide a guess, but it seems to work for
219 gcc output. If it guesses wrong, the only loss should be in
220 efficiency; it shouldn't introduce any bugs.
222 I don't know if a fix is needed for the SVR4_PIC mode. I've only
223 fixed it for the non-PIC mode. KR 95/04/07 */
224 static int nopic_need_relax
PARAMS ((symbolS
*));
226 /* handle of the OPCODE hash table */
227 static struct hash_control
*op_hash
= NULL
;
229 /* The opcode hash table we use for the mips16. */
230 static struct hash_control
*mips16_op_hash
= NULL
;
232 /* This array holds the chars that always start a comment. If the
233 pre-processor is disabled, these aren't very useful */
234 const char comment_chars
[] = "#";
236 /* This array holds the chars that only start a comment at the beginning of
237 a line. If the line seems to have the form '# 123 filename'
238 .line and .file directives will appear in the pre-processed output */
239 /* Note that input_file.c hand checks for '#' at the beginning of the
240 first line of the input file. This is because the compiler outputs
241 #NO_APP at the beginning of its output. */
242 /* Also note that C style comments are always supported. */
243 const char line_comment_chars
[] = "#";
245 /* This array holds machine specific line separator characters. */
246 const char line_separator_chars
[] = "";
248 /* Chars that can be used to separate mant from exp in floating point nums */
249 const char EXP_CHARS
[] = "eE";
251 /* Chars that mean this number is a floating point constant */
254 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
256 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
257 changed in read.c . Ideally it shouldn't have to know about it at all,
258 but nothing is ideal around here.
261 static char *insn_error
;
263 static int auto_align
= 1;
265 /* When outputting SVR4 PIC code, the assembler needs to know the
266 offset in the stack frame from which to restore the $gp register.
267 This is set by the .cprestore pseudo-op, and saved in this
269 static offsetT mips_cprestore_offset
= -1;
271 /* This is the register which holds the stack frame, as set by the
272 .frame pseudo-op. This is needed to implement .cprestore. */
273 static int mips_frame_reg
= SP
;
275 /* To output NOP instructions correctly, we need to keep information
276 about the previous two instructions. */
278 /* Whether we are optimizing. The default value of 2 means to remove
279 unneeded NOPs and swap branch instructions when possible. A value
280 of 1 means to not swap branches. A value of 0 means to always
282 static int mips_optimize
= 2;
284 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
285 equivalent to seeing no -g option at all. */
286 static int mips_debug
= 0;
288 /* The previous instruction. */
289 static struct mips_cl_insn prev_insn
;
291 /* The instruction before prev_insn. */
292 static struct mips_cl_insn prev_prev_insn
;
294 /* If we don't want information for prev_insn or prev_prev_insn, we
295 point the insn_mo field at this dummy integer. */
296 static const struct mips_opcode dummy_opcode
= { 0 };
298 /* Non-zero if prev_insn is valid. */
299 static int prev_insn_valid
;
301 /* The frag for the previous instruction. */
302 static struct frag
*prev_insn_frag
;
304 /* The offset into prev_insn_frag for the previous instruction. */
305 static long prev_insn_where
;
307 /* The reloc type for the previous instruction, if any. */
308 static bfd_reloc_code_real_type prev_insn_reloc_type
;
310 /* The reloc for the previous instruction, if any. */
311 static fixS
*prev_insn_fixp
;
313 /* Non-zero if the previous instruction was in a delay slot. */
314 static int prev_insn_is_delay_slot
;
316 /* Non-zero if the previous instruction was in a .set noreorder. */
317 static int prev_insn_unreordered
;
319 /* Non-zero if the previous instruction uses an extend opcode (if
321 static int prev_insn_extended
;
323 /* Non-zero if the previous previous instruction was in a .set
325 static int prev_prev_insn_unreordered
;
327 /* For ECOFF and ELF, relocations against symbols are done in two
328 parts, with a HI relocation and a LO relocation. Each relocation
329 has only 16 bits of space to store an addend. This means that in
330 order for the linker to handle carries correctly, it must be able
331 to locate both the HI and the LO relocation. This means that the
332 relocations must appear in order in the relocation table.
334 In order to implement this, we keep track of each unmatched HI
335 relocation. We then sort them so that they immediately precede the
336 corresponding LO relocation. */
341 struct mips_hi_fixup
*next
;
344 /* The section this fixup is in. */
348 /* The list of unmatched HI relocs. */
350 static struct mips_hi_fixup
*mips_hi_fixup_list
;
352 /* Map normal MIPS register numbers to mips16 register numbers. */
354 #define X ILLEGAL_REG
355 static const int mips32_to_16_reg_map
[] =
357 X
, X
, 2, 3, 4, 5, 6, 7,
358 X
, X
, X
, X
, X
, X
, X
, X
,
359 0, 1, X
, X
, X
, X
, X
, X
,
360 X
, X
, X
, X
, X
, X
, X
, X
364 /* Map mips16 register numbers to normal MIPS register numbers. */
366 static const int mips16_to_32_reg_map
[] =
368 16, 17, 2, 3, 4, 5, 6, 7
371 /* Since the MIPS does not have multiple forms of PC relative
372 instructions, we do not have to do relaxing as is done on other
373 platforms. However, we do have to handle GP relative addressing
374 correctly, which turns out to be a similar problem.
376 Every macro that refers to a symbol can occur in (at least) two
377 forms, one with GP relative addressing and one without. For
378 example, loading a global variable into a register generally uses
379 a macro instruction like this:
381 If i can be addressed off the GP register (this is true if it is in
382 the .sbss or .sdata section, or if it is known to be smaller than
383 the -G argument) this will generate the following instruction:
385 This instruction will use a GPREL reloc. If i can not be addressed
386 off the GP register, the following instruction sequence will be used:
389 In this case the first instruction will have a HI16 reloc, and the
390 second reloc will have a LO16 reloc. Both relocs will be against
393 The issue here is that we may not know whether i is GP addressable
394 until after we see the instruction that uses it. Therefore, we
395 want to be able to choose the final instruction sequence only at
396 the end of the assembly. This is similar to the way other
397 platforms choose the size of a PC relative instruction only at the
400 When generating position independent code we do not use GP
401 addressing in quite the same way, but the issue still arises as
402 external symbols and local symbols must be handled differently.
404 We handle these issues by actually generating both possible
405 instruction sequences. The longer one is put in a frag_var with
406 type rs_machine_dependent. We encode what to do with the frag in
407 the subtype field. We encode (1) the number of existing bytes to
408 replace, (2) the number of new bytes to use, (3) the offset from
409 the start of the existing bytes to the first reloc we must generate
410 (that is, the offset is applied from the start of the existing
411 bytes after they are replaced by the new bytes, if any), (4) the
412 offset from the start of the existing bytes to the second reloc,
413 (5) whether a third reloc is needed (the third reloc is always four
414 bytes after the second reloc), and (6) whether to warn if this
415 variant is used (this is sometimes needed if .set nomacro or .set
416 noat is in effect). All these numbers are reasonably small.
418 Generating two instruction sequences must be handled carefully to
419 ensure that delay slots are handled correctly. Fortunately, there
420 are a limited number of cases. When the second instruction
421 sequence is generated, append_insn is directed to maintain the
422 existing delay slot information, so it continues to apply to any
423 code after the second instruction sequence. This means that the
424 second instruction sequence must not impose any requirements not
425 required by the first instruction sequence.
427 These variant frags are then handled in functions called by the
428 machine independent code. md_estimate_size_before_relax returns
429 the final size of the frag. md_convert_frag sets up the final form
430 of the frag. tc_gen_reloc adjust the first reloc and adds a second
432 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
436 | (((reloc1) + 64) << 9) \
437 | (((reloc2) + 64) << 2) \
438 | ((reloc3) ? (1 << 1) : 0) \
440 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
441 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
442 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
443 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
444 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
445 #define RELAX_WARN(i) ((i) & 1)
447 /* For mips16 code, we use an entirely different form of relaxation.
448 mips16 supports two versions of most instructions which take
449 immediate values: a small one which takes some small value, and a
450 larger one which takes a 16 bit value. Since branches also follow
451 this pattern, relaxing these values is required.
453 We can assemble both mips16 and normal MIPS code in a single
454 object. Therefore, we need to support this type of relaxation at
455 the same time that we support the relaxation described above. We
456 use the high bit of the subtype field to distinguish these cases.
458 The information we store for this type of relaxation is the
459 argument code found in the opcode file for this relocation, whether
460 the user explicitly requested a small or extended form, and whether
461 the relocation is in a jump or jal delay slot. That tells us the
462 size of the value, and how it should be stored. We also store
463 whether the fragment is considered to be extended or not. We also
464 store whether this is known to be a branch to a different section,
465 whether we have tried to relax this frag yet, and whether we have
466 ever extended a PC relative fragment because of a shift count. */
467 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
470 | ((small) ? 0x100 : 0) \
471 | ((ext) ? 0x200 : 0) \
472 | ((dslot) ? 0x400 : 0) \
473 | ((jal_dslot) ? 0x800 : 0))
474 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
475 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
476 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
477 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
478 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
479 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
480 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
481 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
482 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
483 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
484 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
485 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
487 /* Prototypes for static functions. */
490 #define internalError() \
491 as_fatal ("internal Error, line %d, %s", __LINE__, __FILE__)
493 #define internalError() as_fatal ("MIPS internal Error");
496 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
498 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
499 unsigned int reg
, enum mips_regclass
class));
500 static int reg_needs_delay
PARAMS ((int));
501 static void append_insn
PARAMS ((char *place
,
502 struct mips_cl_insn
* ip
,
504 bfd_reloc_code_real_type r
,
506 static void mips_no_prev_insn
PARAMS ((void));
507 static void mips_emit_delays
PARAMS ((boolean
));
509 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
510 const char *name
, const char *fmt
,
513 static void macro_build ();
515 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
516 const char *, const char *,
518 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
519 expressionS
* ep
, int regnum
));
520 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
521 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
523 static void load_register
PARAMS ((int *, int, expressionS
*, int));
524 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
525 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
526 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
527 #ifdef LOSING_COMPILER
528 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
530 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
531 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
532 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
533 boolean
, boolean
, unsigned long *,
534 boolean
*, unsigned short *));
535 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
536 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
537 static symbolS
*get_symbol
PARAMS ((void));
538 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
539 static void s_align
PARAMS ((int));
540 static void s_change_sec
PARAMS ((int));
541 static void s_cons
PARAMS ((int));
542 static void s_float_cons
PARAMS ((int));
543 static void s_mips_globl
PARAMS ((int));
544 static void s_option
PARAMS ((int));
545 static void s_mipsset
PARAMS ((int));
546 static void s_abicalls
PARAMS ((int));
547 static void s_cpload
PARAMS ((int));
548 static void s_cprestore
PARAMS ((int));
549 static void s_gpword
PARAMS ((int));
550 static void s_cpadd
PARAMS ((int));
551 static void md_obj_begin
PARAMS ((void));
552 static void md_obj_end
PARAMS ((void));
553 static long get_number
PARAMS ((void));
554 static void s_ent
PARAMS ((int));
555 static void s_mipsend
PARAMS ((int));
556 static void s_file
PARAMS ((int));
557 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
561 The following pseudo-ops from the Kane and Heinrich MIPS book
562 should be defined here, but are currently unsupported: .alias,
563 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
565 The following pseudo-ops from the Kane and Heinrich MIPS book are
566 specific to the type of debugging information being generated, and
567 should be defined by the object format: .aent, .begin, .bend,
568 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
571 The following pseudo-ops from the Kane and Heinrich MIPS book are
572 not MIPS CPU specific, but are also not specific to the object file
573 format. This file is probably the best place to define them, but
574 they are not currently supported: .asm0, .endr, .lab, .repeat,
575 .struct, .weakext. */
577 static const pseudo_typeS mips_pseudo_table
[] =
579 /* MIPS specific pseudo-ops. */
580 {"option", s_option
, 0},
581 {"set", s_mipsset
, 0},
582 {"rdata", s_change_sec
, 'r'},
583 {"sdata", s_change_sec
, 's'},
584 {"livereg", s_ignore
, 0},
585 {"abicalls", s_abicalls
, 0},
586 {"cpload", s_cpload
, 0},
587 {"cprestore", s_cprestore
, 0},
588 {"gpword", s_gpword
, 0},
589 {"cpadd", s_cpadd
, 0},
591 /* Relatively generic pseudo-ops that happen to be used on MIPS
593 {"asciiz", stringer
, 1},
594 {"bss", s_change_sec
, 'b'},
597 {"dword", s_cons
, 3},
599 /* These pseudo-ops are defined in read.c, but must be overridden
600 here for one reason or another. */
601 {"align", s_align
, 0},
603 {"data", s_change_sec
, 'd'},
604 {"double", s_float_cons
, 'd'},
605 {"float", s_float_cons
, 'f'},
606 {"globl", s_mips_globl
, 0},
607 {"global", s_mips_globl
, 0},
608 {"hword", s_cons
, 1},
613 {"short", s_cons
, 1},
614 {"single", s_float_cons
, 'f'},
615 {"text", s_change_sec
, 't'},
620 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
621 /* These pseudo-ops should be defined by the object file format.
622 However, a.out doesn't support them, so we have versions here. */
624 {"bgnb", s_ignore
, 0},
625 {"end", s_mipsend
, 0},
626 {"endb", s_ignore
, 0},
629 {"fmask", s_ignore
, 'F'},
630 {"frame", s_ignore
, 0},
631 {"loc", s_ignore
, 0},
632 {"mask", s_ignore
, 'R'},
633 {"verstamp", s_ignore
, 0},
637 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
642 pop_insert (mips_pseudo_table
);
643 if (! ECOFF_DEBUGGING
)
644 pop_insert (mips_nonecoff_pseudo_table
);
647 /* Symbols labelling the current insn. */
649 struct insn_label_list
651 struct insn_label_list
*next
;
655 static struct insn_label_list
*insn_labels
;
656 static struct insn_label_list
*free_insn_labels
;
658 static void mips_clear_insn_labels
PARAMS ((void));
661 mips_clear_insn_labels ()
663 register struct insn_label_list
**pl
;
665 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
671 static char *expr_end
;
673 /* Expressions which appear in instructions. These are set by
676 static expressionS imm_expr
;
677 static expressionS offset_expr
;
679 /* Relocs associated with imm_expr and offset_expr. */
681 static bfd_reloc_code_real_type imm_reloc
;
682 static bfd_reloc_code_real_type offset_reloc
;
684 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
686 static boolean imm_unmatched_hi
;
688 /* These are set by mips16_ip if an explicit extension is used. */
690 static boolean mips16_small
, mips16_ext
;
693 * This function is called once, at assembler startup time. It should
694 * set up all the tables, etc. that the MD part of the assembler will need.
700 register const char *retval
= NULL
;
701 register unsigned int i
= 0;
709 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
711 a
= xmalloc (sizeof TARGET_CPU
);
712 strcpy (a
, TARGET_CPU
);
713 a
[(sizeof TARGET_CPU
) - 3] = '\0';
717 if (strcmp (cpu
, "mips") == 0)
723 else if (strcmp (cpu
, "r6000") == 0
724 || strcmp (cpu
, "mips2") == 0)
730 else if (strcmp (cpu
, "mips64") == 0
731 || strcmp (cpu
, "r4000") == 0
732 || strcmp (cpu
, "mips3") == 0)
738 else if (strcmp (cpu
, "r4400") == 0)
744 else if (strcmp (cpu
, "mips64orion") == 0
745 || strcmp (cpu
, "r4600") == 0)
751 else if (strcmp (cpu
, "r4650") == 0)
759 else if (strcmp (cpu
, "mips64vr4300") == 0)
765 else if (strcmp (cpu
, "mips64vr4100") == 0)
773 else if (strcmp (cpu
, "r4010") == 0)
781 else if (strcmp (cpu
, "r5000") == 0
782 || strcmp (cpu
, "mips64vr5000") == 0)
788 /* start-sanitize-r5900 */
789 else if (strcmp (cpu
, "r5900") == 0
790 || strcmp (cpu
, "mips64vr5900") == 0
791 || strcmp (cpu
, "mips64vr5900el") == 0)
799 /* end-sanitize-r5900 */
800 else if (strcmp (cpu
, "r8000") == 0
801 || strcmp (cpu
, "mips4") == 0)
807 else if (strcmp (cpu
, "r10000") == 0)
813 else if (strcmp (cpu
, "mips16") == 0)
817 mips_cpu
= 0; /* FIXME */
832 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
847 /* start-sanitize-r5900 */
850 /* end-sanitize-r5900 */
852 if (mips_4010
|| mips_4100
|| mips_cpu
== 4300)
857 if (mips_cpu
== 4300)
862 if (mips_isa
< 2 && mips_trap
)
863 as_bad ("trap exception not supported at ISA 1");
868 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
871 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
874 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
877 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
881 as_warn ("Could not set architecture and machine");
883 file_mips_isa
= mips_isa
;
885 op_hash
= hash_new ();
887 for (i
= 0; i
< NUMOPCODES
;)
889 const char *name
= mips_opcodes
[i
].name
;
891 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
894 fprintf (stderr
, "internal error: can't hash `%s': %s\n",
895 mips_opcodes
[i
].name
, retval
);
896 as_fatal ("Broken assembler. No assembly attempted.");
900 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
901 && ((mips_opcodes
[i
].match
& mips_opcodes
[i
].mask
)
902 != mips_opcodes
[i
].match
))
904 fprintf (stderr
, "internal error: bad opcode: `%s' \"%s\"\n",
905 mips_opcodes
[i
].name
, mips_opcodes
[i
].args
);
906 as_fatal ("Broken assembler. No assembly attempted.");
910 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
913 mips16_op_hash
= hash_new ();
916 while (i
< bfd_mips16_num_opcodes
)
918 const char *name
= mips16_opcodes
[i
].name
;
920 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
922 as_fatal ("internal error: can't hash `%s': %s\n",
923 mips16_opcodes
[i
].name
, retval
);
926 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
927 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
928 != mips16_opcodes
[i
].match
))
929 as_fatal ("internal error: bad opcode: `%s' \"%s\"\n",
930 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
933 while (i
< bfd_mips16_num_opcodes
934 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
937 mips_no_prev_insn ();
945 /* set the default alignment for the text section (2**2) */
946 record_alignment (text_section
, 2);
948 if (USE_GLOBAL_POINTER_OPT
)
949 bfd_set_gp_size (stdoutput
, g_switch_value
);
951 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
953 /* On a native system, sections must be aligned to 16 byte
954 boundaries. When configured for an embedded ELF target, we
956 if (strcmp (TARGET_OS
, "elf") != 0)
958 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
959 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
960 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
963 /* Create a .reginfo section for register masks and a .mdebug
964 section for debugging information. */
974 /* The ABI says this section should be loaded so that the
975 running program can access it. However, we don't load it
976 if we are configured for an embedded target */
977 flags
= SEC_READONLY
| SEC_DATA
;
978 if (strcmp (TARGET_OS
, "elf") != 0)
979 flags
|= SEC_ALLOC
| SEC_LOAD
;
983 sec
= subseg_new (".reginfo", (subsegT
) 0);
986 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
987 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
990 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
995 /* The 64-bit ABI uses a .MIPS.options section rather than
997 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
998 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
999 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1002 /* Set up the option header. */
1004 Elf_Internal_Options opthdr
;
1007 opthdr
.kind
= ODK_REGINFO
;
1008 opthdr
.size
= (sizeof (Elf_External_Options
)
1009 + sizeof (Elf64_External_RegInfo
));
1012 f
= frag_more (sizeof (Elf_External_Options
));
1013 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1014 (Elf_External_Options
*) f
);
1016 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1021 if (ECOFF_DEBUGGING
)
1023 sec
= subseg_new (".mdebug", (subsegT
) 0);
1024 (void) bfd_set_section_flags (stdoutput
, sec
,
1025 SEC_HAS_CONTENTS
| SEC_READONLY
);
1026 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1029 subseg_set (seg
, subseg
);
1033 if (! ECOFF_DEBUGGING
)
1040 if (! ECOFF_DEBUGGING
)
1048 struct mips_cl_insn insn
;
1050 imm_expr
.X_op
= O_absent
;
1051 imm_reloc
= BFD_RELOC_UNUSED
;
1052 imm_unmatched_hi
= false;
1053 offset_expr
.X_op
= O_absent
;
1054 offset_reloc
= BFD_RELOC_UNUSED
;
1057 mips16_ip (str
, &insn
);
1059 mips_ip (str
, &insn
);
1063 as_bad ("%s `%s'", insn_error
, str
);
1067 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1070 mips16_macro (&insn
);
1076 if (imm_expr
.X_op
!= O_absent
)
1077 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1079 else if (offset_expr
.X_op
!= O_absent
)
1080 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1082 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1086 /* See whether instruction IP reads register REG. CLASS is the type
1090 insn_uses_reg (ip
, reg
, class)
1091 struct mips_cl_insn
*ip
;
1093 enum mips_regclass
class;
1095 if (class == MIPS16_REG
)
1098 reg
= mips16_to_32_reg_map
[reg
];
1099 class = MIPS_GR_REG
;
1102 /* Don't report on general register 0, since it never changes. */
1103 if (class == MIPS_GR_REG
&& reg
== 0)
1106 if (class == MIPS_FP_REG
)
1109 /* If we are called with either $f0 or $f1, we must check $f0.
1110 This is not optimal, because it will introduce an unnecessary
1111 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1112 need to distinguish reading both $f0 and $f1 or just one of
1113 them. Note that we don't have to check the other way,
1114 because there is no instruction that sets both $f0 and $f1
1115 and requires a delay. */
1116 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1117 && (((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
)
1118 == (reg
&~ (unsigned) 1)))
1120 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1121 && (((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
)
1122 == (reg
&~ (unsigned) 1)))
1127 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1128 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1130 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1131 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1136 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1137 && ((ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
) == reg
)
1139 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1140 && ((ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
) == reg
)
1142 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1143 && ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1144 & MIPS16OP_MASK_MOVE32Z
) == reg
)
1146 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1148 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1150 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1152 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1153 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1154 & MIPS16OP_MASK_REGR32
) == reg
)
1161 /* This function returns true if modifying a register requires a
1165 reg_needs_delay (reg
)
1168 unsigned long prev_pinfo
;
1170 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1171 if (! mips_noreorder
1173 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1175 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1177 /* A load from a coprocessor or from memory. All load
1178 delays delay the use of general register rt for one
1179 instruction on the r3000. The r6000 and r4000 use
1181 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1182 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1189 /* Output an instruction. PLACE is where to put the instruction; if
1190 it is NULL, this uses frag_more to get room. IP is the instruction
1191 information. ADDRESS_EXPR is an operand of the instruction to be
1192 used with RELOC_TYPE. */
1195 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1197 struct mips_cl_insn
*ip
;
1198 expressionS
*address_expr
;
1199 bfd_reloc_code_real_type reloc_type
;
1200 boolean unmatched_hi
;
1202 register unsigned long prev_pinfo
, pinfo
;
1207 /* Mark instruction labels in mips16 mode. This permits the linker
1208 to handle them specially, such as generating jalx instructions
1209 when needed. We also make them odd for the duration of the
1210 assembly, in order to generate the right sort of code. We will
1211 make them even in the adjust_symtab routine, while leaving them
1212 marked. This is convenient for the debugger and the
1213 disassembler. The linker knows to make them odd again. */
1216 struct insn_label_list
*l
;
1218 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1221 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1222 S_SET_OTHER (l
->label
, STO_MIPS16
);
1224 ++l
->label
->sy_value
.X_add_number
;
1228 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1229 pinfo
= ip
->insn_mo
->pinfo
;
1231 if (place
== NULL
&& ! mips_noreorder
)
1233 /* If the previous insn required any delay slots, see if we need
1234 to insert a NOP or two. There are eight kinds of possible
1235 hazards, of which an instruction can have at most one type.
1236 (1) a load from memory delay
1237 (2) a load from a coprocessor delay
1238 (3) an unconditional branch delay
1239 (4) a conditional branch delay
1240 (5) a move to coprocessor register delay
1241 (6) a load coprocessor register from memory delay
1242 (7) a coprocessor condition code delay
1243 (8) a HI/LO special register delay
1245 There are a lot of optimizations we could do that we don't.
1246 In particular, we do not, in general, reorder instructions.
1247 If you use gcc with optimization, it will reorder
1248 instructions and generally do much more optimization then we
1249 do here; repeating all that work in the assembler would only
1250 benefit hand written assembly code, and does not seem worth
1253 /* This is how a NOP is emitted. */
1254 #define emit_nop() \
1256 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1257 : md_number_to_chars (frag_more (4), 0, 4))
1259 /* The previous insn might require a delay slot, depending upon
1260 the contents of the current insn. */
1263 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1264 && ! cop_interlocks
)
1266 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1268 /* A load from a coprocessor or from memory. All load
1269 delays delay the use of general register rt for one
1270 instruction on the r3000. The r6000 and r4000 use
1272 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1273 if (mips_optimize
== 0
1274 || insn_uses_reg (ip
,
1275 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1282 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1283 && ! cop_interlocks
)
1285 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1287 /* A generic coprocessor delay. The previous instruction
1288 modified a coprocessor general or control register. If
1289 it modified a control register, we need to avoid any
1290 coprocessor instruction (this is probably not always
1291 required, but it sometimes is). If it modified a general
1292 register, we avoid using that register.
1294 On the r6000 and r4000 loading a coprocessor register
1295 from memory is interlocked, and does not require a delay.
1297 This case is not handled very well. There is no special
1298 knowledge of CP0 handling, and the coprocessors other
1299 than the floating point unit are not distinguished at
1301 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1303 if (mips_optimize
== 0
1304 || insn_uses_reg (ip
,
1305 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1310 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1312 if (mips_optimize
== 0
1313 || insn_uses_reg (ip
,
1314 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1321 /* We don't know exactly what the previous instruction
1322 does. If the current instruction uses a coprocessor
1323 register, we must insert a NOP. If previous
1324 instruction may set the condition codes, and the
1325 current instruction uses them, we must insert two
1327 if (mips_optimize
== 0
1328 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1329 && (pinfo
& INSN_READ_COND_CODE
)))
1331 else if (pinfo
& INSN_COP
)
1337 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1338 && ! cop_interlocks
)
1340 /* The previous instruction sets the coprocessor condition
1341 codes, but does not require a general coprocessor delay
1342 (this means it is a floating point comparison
1343 instruction). If this instruction uses the condition
1344 codes, we need to insert a single NOP. */
1345 if (mips_optimize
== 0
1346 || (pinfo
& INSN_READ_COND_CODE
))
1349 else if (prev_pinfo
& INSN_READ_LO
)
1351 /* The previous instruction reads the LO register; if the
1352 current instruction writes to the LO register, we must
1353 insert two NOPS. Some newer processors have interlocks. */
1355 && (mips_optimize
== 0
1356 || (pinfo
& INSN_WRITE_LO
)))
1359 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1361 /* The previous instruction reads the HI register; if the
1362 current instruction writes to the HI register, we must
1363 insert a NOP. Some newer processors have interlocks. */
1365 && (mips_optimize
== 0
1366 || (pinfo
& INSN_WRITE_HI
)))
1370 /* There are two cases which require two intervening
1371 instructions: 1) setting the condition codes using a move to
1372 coprocessor instruction which requires a general coprocessor
1373 delay and then reading the condition codes 2) reading the HI
1374 or LO register and then writing to it (except on processors
1375 which have interlocks). If we are not already emitting a NOP
1376 instruction, we must check for these cases compared to the
1377 instruction previous to the previous instruction. */
1381 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1382 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1383 && (pinfo
& INSN_READ_COND_CODE
)
1384 && ! cop_interlocks
)
1385 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1386 && (pinfo
& INSN_WRITE_LO
)
1388 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1389 && (pinfo
& INSN_WRITE_HI
)
1393 /* If we are being given a nop instruction, don't bother with
1394 one of the nops we would otherwise output. This will only
1395 happen when a nop instruction is used with mips_optimize set
1397 if (nops
> 0 && ip
->insn_opcode
== (mips16
? 0x6500 : 0))
1400 /* Now emit the right number of NOP instructions. */
1404 unsigned long old_frag_offset
;
1406 struct insn_label_list
*l
;
1408 old_frag
= frag_now
;
1409 old_frag_offset
= frag_now_fix ();
1411 for (i
= 0; i
< nops
; i
++)
1416 listing_prev_line ();
1417 /* We may be at the start of a variant frag. In case we
1418 are, make sure there is enough space for the frag
1419 after the frags created by listing_prev_line. The
1420 argument to frag_grow here must be at least as large
1421 as the argument to all other calls to frag_grow in
1422 this file. We don't have to worry about being in the
1423 middle of a variant frag, because the variants insert
1424 all needed nop instructions themselves. */
1428 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1430 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1431 l
->label
->sy_frag
= frag_now
;
1432 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1433 /* mips16 text labels are stored as odd. */
1435 ++l
->label
->sy_value
.X_add_number
;
1438 #ifndef NO_ECOFF_DEBUGGING
1439 if (ECOFF_DEBUGGING
)
1440 ecoff_fix_loc (old_frag
, old_frag_offset
);
1445 if (reloc_type
> BFD_RELOC_UNUSED
)
1447 /* We need to set up a variant frag. */
1448 assert (mips16
&& address_expr
!= NULL
);
1449 f
= frag_var (rs_machine_dependent
, 4, 0,
1450 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1451 mips16_small
, mips16_ext
,
1453 & INSN_UNCOND_BRANCH_DELAY
),
1454 (prev_insn_reloc_type
1455 == BFD_RELOC_MIPS16_JMP
)),
1456 make_expr_symbol (address_expr
), (long) 0,
1459 else if (place
!= NULL
)
1461 else if (mips16
&& ! ip
->use_extend
&& reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1463 /* Make sure there is enough room to swap this instruction with
1464 a following jump instruction. */
1471 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1473 if (address_expr
->X_op
== O_constant
)
1478 ip
->insn_opcode
|= address_expr
->X_add_number
;
1481 case BFD_RELOC_LO16
:
1482 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1485 case BFD_RELOC_MIPS_JMP
:
1486 if ((address_expr
->X_add_number
& 3) != 0)
1487 as_bad ("jump to misaligned address (0x%lx)",
1488 (unsigned long) address_expr
->X_add_number
);
1489 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1492 case BFD_RELOC_MIPS16_JMP
:
1493 if ((address_expr
->X_add_number
& 3) != 0)
1494 as_bad ("jump to misaligned address (0x%lx)",
1495 (unsigned long) address_expr
->X_add_number
);
1497 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1498 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1499 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1502 case BFD_RELOC_16_PCREL_S2
:
1512 /* Don't generate a reloc if we are writing into a variant
1516 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1518 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1522 struct mips_hi_fixup
*hi_fixup
;
1524 assert (reloc_type
== BFD_RELOC_HI16_S
);
1525 hi_fixup
= ((struct mips_hi_fixup
*)
1526 xmalloc (sizeof (struct mips_hi_fixup
)));
1527 hi_fixup
->fixp
= fixp
;
1528 hi_fixup
->seg
= now_seg
;
1529 hi_fixup
->next
= mips_hi_fixup_list
;
1530 mips_hi_fixup_list
= hi_fixup
;
1536 if (! mips16
|| reloc_type
== BFD_RELOC_MIPS16_JMP
)
1537 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1542 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1545 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1548 /* Update the register mask information. */
1551 if (pinfo
& INSN_WRITE_GPR_D
)
1552 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1553 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1554 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1555 if (pinfo
& INSN_READ_GPR_S
)
1556 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1557 if (pinfo
& INSN_WRITE_GPR_31
)
1558 mips_gprmask
|= 1 << 31;
1559 if (pinfo
& INSN_WRITE_FPR_D
)
1560 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1561 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1562 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1563 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1564 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1565 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1566 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1567 if (pinfo
& INSN_COP
)
1569 /* We don't keep enough information to sort these cases out. */
1571 /* Never set the bit for $0, which is always zero. */
1572 mips_gprmask
&=~ 1 << 0;
1576 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1577 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1578 & MIPS16OP_MASK_RX
);
1579 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1580 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1581 & MIPS16OP_MASK_RY
);
1582 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1583 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1584 & MIPS16OP_MASK_RZ
);
1585 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1586 mips_gprmask
|= 1 << TREG
;
1587 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1588 mips_gprmask
|= 1 << SP
;
1589 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1590 mips_gprmask
|= 1 << RA
;
1591 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1592 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1593 if (pinfo
& MIPS16_INSN_READ_Z
)
1594 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1595 & MIPS16OP_MASK_MOVE32Z
);
1596 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1597 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1598 & MIPS16OP_MASK_REGR32
);
1601 if (place
== NULL
&& ! mips_noreorder
)
1603 /* Filling the branch delay slot is more complex. We try to
1604 switch the branch with the previous instruction, which we can
1605 do if the previous instruction does not set up a condition
1606 that the branch tests and if the branch is not itself the
1607 target of any branch. */
1608 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1609 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1611 if (mips_optimize
< 2
1612 /* If we have seen .set volatile or .set nomove, don't
1615 /* If we had to emit any NOP instructions, then we
1616 already know we can not swap. */
1618 /* If we don't even know the previous insn, we can not
1620 || ! prev_insn_valid
1621 /* If the previous insn is already in a branch delay
1622 slot, then we can not swap. */
1623 || prev_insn_is_delay_slot
1624 /* If the previous previous insn was in a .set
1625 noreorder, we can't swap. Actually, the MIPS
1626 assembler will swap in this situation. However, gcc
1627 configured -with-gnu-as will generate code like
1633 in which we can not swap the bne and INSN. If gcc is
1634 not configured -with-gnu-as, it does not output the
1635 .set pseudo-ops. We don't have to check
1636 prev_insn_unreordered, because prev_insn_valid will
1637 be 0 in that case. We don't want to use
1638 prev_prev_insn_valid, because we do want to be able
1639 to swap at the start of a function. */
1640 || prev_prev_insn_unreordered
1641 /* If the branch is itself the target of a branch, we
1642 can not swap. We cheat on this; all we check for is
1643 whether there is a label on this instruction. If
1644 there are any branches to anything other than a
1645 label, users must use .set noreorder. */
1646 || insn_labels
!= NULL
1647 /* If the previous instruction is in a variant frag, we
1648 can not do the swap. This does not apply to the
1649 mips16, which uses variant frags for different
1652 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
1653 /* If the branch reads the condition codes, we don't
1654 even try to swap, because in the sequence
1659 we can not swap, and I don't feel like handling that
1663 && (pinfo
& INSN_READ_COND_CODE
))
1664 /* We can not swap with an instruction that requires a
1665 delay slot, becase the target of the branch might
1666 interfere with that instruction. */
1670 & (INSN_LOAD_COPROC_DELAY
1671 | INSN_COPROC_MOVE_DELAY
1672 | INSN_WRITE_COND_CODE
)))
1680 & (INSN_LOAD_MEMORY_DELAY
1681 | INSN_COPROC_MEMORY_DELAY
)))
1682 /* We can not swap with a branch instruction. */
1684 & (INSN_UNCOND_BRANCH_DELAY
1685 | INSN_COND_BRANCH_DELAY
1686 | INSN_COND_BRANCH_LIKELY
))
1687 /* We do not swap with a trap instruction, since it
1688 complicates trap handlers to have the trap
1689 instruction be in a delay slot. */
1690 || (prev_pinfo
& INSN_TRAP
)
1691 /* If the branch reads a register that the previous
1692 instruction sets, we can not swap. */
1694 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1695 && insn_uses_reg (ip
,
1696 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1700 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1701 && insn_uses_reg (ip
,
1702 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1706 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
1707 && insn_uses_reg (ip
,
1708 ((prev_insn
.insn_opcode
1710 & MIPS16OP_MASK_RX
),
1712 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
1713 && insn_uses_reg (ip
,
1714 ((prev_insn
.insn_opcode
1716 & MIPS16OP_MASK_RY
),
1718 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
1719 && insn_uses_reg (ip
,
1720 ((prev_insn
.insn_opcode
1722 & MIPS16OP_MASK_RZ
),
1724 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
1725 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
1726 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1727 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
1728 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1729 && insn_uses_reg (ip
,
1730 MIPS16OP_EXTRACT_REG32R (prev_insn
.
1733 /* If the branch writes a register that the previous
1734 instruction sets, we can not swap (we know that
1735 branches write only to RD or to $31). */
1737 && (prev_pinfo
& INSN_WRITE_GPR_T
)
1738 && (((pinfo
& INSN_WRITE_GPR_D
)
1739 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
1740 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1741 || ((pinfo
& INSN_WRITE_GPR_31
)
1742 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
1746 && (prev_pinfo
& INSN_WRITE_GPR_D
)
1747 && (((pinfo
& INSN_WRITE_GPR_D
)
1748 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
1749 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
1750 || ((pinfo
& INSN_WRITE_GPR_31
)
1751 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
1755 && (pinfo
& MIPS16_INSN_WRITE_31
)
1756 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
1757 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1758 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
1760 /* If the branch writes a register that the previous
1761 instruction reads, we can not swap (we know that
1762 branches only write to RD or to $31). */
1764 && (pinfo
& INSN_WRITE_GPR_D
)
1765 && insn_uses_reg (&prev_insn
,
1766 ((ip
->insn_opcode
>> OP_SH_RD
)
1770 && (pinfo
& INSN_WRITE_GPR_31
)
1771 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
1773 && (pinfo
& MIPS16_INSN_WRITE_31
)
1774 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
1775 /* If we are generating embedded PIC code, the branch
1776 might be expanded into a sequence which uses $at, so
1777 we can't swap with an instruction which reads it. */
1778 || (mips_pic
== EMBEDDED_PIC
1779 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
1780 /* If the previous previous instruction has a load
1781 delay, and sets a register that the branch reads, we
1785 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
1787 && (prev_prev_insn
.insn_mo
->pinfo
1788 & INSN_LOAD_MEMORY_DELAY
)))
1789 && insn_uses_reg (ip
,
1790 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
1793 /* If one instruction sets a condition code and the
1794 other one uses a condition code, we can not swap. */
1795 || ((pinfo
& INSN_READ_COND_CODE
)
1796 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
1797 || ((pinfo
& INSN_WRITE_COND_CODE
)
1798 && (prev_pinfo
& INSN_READ_COND_CODE
))
1799 /* If the previous instruction uses the PC, we can not
1802 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
1803 /* If the previous instruction was extended, we can not
1805 || (mips16
&& prev_insn_extended
)
1806 /* If the previous instruction had a fixup in mips16
1807 mode, we can not swap. This normally means that the
1808 previous instruction was a 4 byte branch anyhow. */
1809 || (mips16
&& prev_insn_fixp
))
1811 /* We could do even better for unconditional branches to
1812 portions of this object file; we could pick up the
1813 instruction at the destination, put it in the delay
1814 slot, and bump the destination address. */
1816 /* Update the previous insn information. */
1817 prev_prev_insn
= *ip
;
1818 prev_insn
.insn_mo
= &dummy_opcode
;
1822 /* It looks like we can actually do the swap. */
1828 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1829 memcpy (temp
, prev_f
, 4);
1830 memcpy (prev_f
, f
, 4);
1831 memcpy (f
, temp
, 4);
1834 prev_insn_fixp
->fx_frag
= frag_now
;
1835 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
1839 fixp
->fx_frag
= prev_insn_frag
;
1840 fixp
->fx_where
= prev_insn_where
;
1843 else if (reloc_type
> BFD_RELOC_UNUSED
)
1848 /* We are in mips16 mode, and we have just created a
1849 variant frag. We need to extract the old
1850 instruction from the end of the previous frag,
1851 and add it to a new frag. */
1852 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1853 memcpy (temp
, prev_f
, 2);
1854 prev_insn_frag
->fr_fix
-= 2;
1855 if (prev_insn_frag
->fr_type
== rs_machine_dependent
)
1857 assert (prev_insn_where
== prev_insn_frag
->fr_fix
);
1858 memcpy (prev_f
, prev_f
+ 2, 2);
1860 memcpy (frag_more (2), temp
, 2);
1867 assert (prev_insn_fixp
== NULL
);
1868 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
1869 memcpy (temp
, prev_f
, 2);
1870 memcpy (prev_f
, f
, 2);
1871 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1872 memcpy (f
, temp
, 2);
1875 memcpy (f
, f
+ 2, 2);
1876 memcpy (f
+ 2, temp
, 2);
1880 fixp
->fx_frag
= prev_insn_frag
;
1881 fixp
->fx_where
= prev_insn_where
;
1885 /* Update the previous insn information; leave prev_insn
1887 prev_prev_insn
= *ip
;
1889 prev_insn_is_delay_slot
= 1;
1891 /* If that was an unconditional branch, forget the previous
1892 insn information. */
1893 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1895 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1896 prev_insn
.insn_mo
= &dummy_opcode
;
1899 prev_insn_fixp
= NULL
;
1900 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1901 prev_insn_extended
= 0;
1903 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
1905 /* We don't yet optimize a branch likely. What we should do
1906 is look at the target, copy the instruction found there
1907 into the delay slot, and increment the branch to jump to
1908 the next instruction. */
1910 /* Update the previous insn information. */
1911 prev_prev_insn
= *ip
;
1912 prev_insn
.insn_mo
= &dummy_opcode
;
1913 prev_insn_fixp
= NULL
;
1914 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1915 prev_insn_extended
= 0;
1919 /* Update the previous insn information. */
1921 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1923 prev_prev_insn
= prev_insn
;
1926 /* Any time we see a branch, we always fill the delay slot
1927 immediately; since this insn is not a branch, we know it
1928 is not in a delay slot. */
1929 prev_insn_is_delay_slot
= 0;
1931 prev_insn_fixp
= fixp
;
1932 prev_insn_reloc_type
= reloc_type
;
1934 prev_insn_extended
= (ip
->use_extend
1935 || reloc_type
> BFD_RELOC_UNUSED
);
1938 prev_prev_insn_unreordered
= prev_insn_unreordered
;
1939 prev_insn_unreordered
= 0;
1940 prev_insn_frag
= frag_now
;
1941 prev_insn_where
= f
- frag_now
->fr_literal
;
1942 prev_insn_valid
= 1;
1944 else if (place
== NULL
)
1946 /* We need to record a bit of information even when we are not
1947 reordering, in order to determine the base address for mips16
1948 PC relative relocs. */
1950 prev_insn_reloc_type
= reloc_type
;
1953 /* We just output an insn, so the next one doesn't have a label. */
1954 mips_clear_insn_labels ();
1957 /* This function forgets that there was any previous instruction or
1961 mips_no_prev_insn ()
1963 prev_insn
.insn_mo
= &dummy_opcode
;
1964 prev_prev_insn
.insn_mo
= &dummy_opcode
;
1965 prev_insn_valid
= 0;
1966 prev_insn_is_delay_slot
= 0;
1967 prev_insn_unreordered
= 0;
1968 prev_insn_extended
= 0;
1969 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
1970 prev_prev_insn_unreordered
= 0;
1971 mips_clear_insn_labels ();
1974 /* This function must be called whenever we turn on noreorder or emit
1975 something other than instructions. It inserts any NOPS which might
1976 be needed by the previous instruction, and clears the information
1977 kept for the previous instructions. The INSNS parameter is true if
1978 instructions are to follow. */
1981 mips_emit_delays (insns
)
1984 if (! mips_noreorder
)
1991 && (! cop_interlocks
1992 && (prev_insn
.insn_mo
->pinfo
1993 & (INSN_LOAD_COPROC_DELAY
1994 | INSN_COPROC_MOVE_DELAY
1995 | INSN_WRITE_COND_CODE
))))
1997 && (prev_insn
.insn_mo
->pinfo
2002 && (prev_insn
.insn_mo
->pinfo
2003 & (INSN_LOAD_MEMORY_DELAY
2004 | INSN_COPROC_MEMORY_DELAY
))))
2009 && (! cop_interlocks
2010 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2012 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2013 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2018 && (! cop_interlocks
2019 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2021 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2022 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2026 struct insn_label_list
*l
;
2029 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2031 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2032 l
->label
->sy_frag
= frag_now
;
2033 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2034 /* mips16 text labels are stored as odd. */
2036 ++l
->label
->sy_value
.X_add_number
;
2041 /* Mark instruction labels in mips16 mode. This permits the linker
2042 to handle them specially, such as generating jalx instructions
2043 when needed. We also make them odd for the duration of the
2044 assembly, in order to generate the right sort of code. We will
2045 make them even in the adjust_symtab routine, while leaving them
2046 marked. This is convenient for the debugger and the
2047 disassembler. The linker knows to make them odd again. */
2048 if (mips16
&& insns
)
2050 struct insn_label_list
*l
;
2052 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2055 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
2056 S_SET_OTHER (l
->label
, STO_MIPS16
);
2058 if ((l
->label
->sy_value
.X_add_number
& 1) == 0)
2059 ++l
->label
->sy_value
.X_add_number
;
2063 mips_no_prev_insn ();
2066 /* Build an instruction created by a macro expansion. This is passed
2067 a pointer to the count of instructions created so far, an
2068 expression, the name of the instruction to build, an operand format
2069 string, and corresponding arguments. */
2073 macro_build (char *place
,
2081 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2090 struct mips_cl_insn insn
;
2091 bfd_reloc_code_real_type r
;
2095 va_start (args
, fmt
);
2101 * If the macro is about to expand into a second instruction,
2102 * print a warning if needed. We need to pass ip as a parameter
2103 * to generate a better warning message here...
2105 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2106 as_warn ("Macro instruction expanded into multiple instructions");
2109 *counter
+= 1; /* bump instruction counter */
2113 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2118 r
= BFD_RELOC_UNUSED
;
2119 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2120 assert (insn
.insn_mo
);
2121 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2123 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2124 || insn
.insn_mo
->pinfo
== INSN_MACRO
2125 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA2
2127 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA3
2129 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_ISA4
2131 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4650
2133 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4010
2135 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_4100
2137 /* start-sanitize-r5900 */
2138 || ((insn
.insn_mo
->pinfo
& INSN_ISA
) == INSN_5900
2140 /* end-sanitize-r5900 */
2144 assert (insn
.insn_mo
->name
);
2145 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2147 insn
.insn_opcode
= insn
.insn_mo
->match
;
2163 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2169 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2174 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2179 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2186 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2190 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2194 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2201 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2207 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2208 assert (r
== BFD_RELOC_MIPS_GPREL
2209 || r
== BFD_RELOC_MIPS_LITERAL
2210 || r
== BFD_RELOC_LO16
2211 || r
== BFD_RELOC_MIPS_GOT16
2212 || r
== BFD_RELOC_MIPS_CALL16
2213 || r
== BFD_RELOC_MIPS_GOT_LO16
2214 || r
== BFD_RELOC_MIPS_CALL_LO16
2215 || (ep
->X_op
== O_subtract
2216 && now_seg
== text_section
2217 && r
== BFD_RELOC_PCREL_LO16
));
2221 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2223 && (ep
->X_op
== O_constant
2224 || (ep
->X_op
== O_symbol
2225 && (r
== BFD_RELOC_HI16_S
2226 || r
== BFD_RELOC_HI16
2227 || r
== BFD_RELOC_MIPS_GOT_HI16
2228 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2229 || (ep
->X_op
== O_subtract
2230 && now_seg
== text_section
2231 && r
== BFD_RELOC_PCREL_HI16_S
)));
2232 if (ep
->X_op
== O_constant
)
2234 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2236 r
= BFD_RELOC_UNUSED
;
2241 assert (ep
!= NULL
);
2243 * This allows macro() to pass an immediate expression for
2244 * creating short branches without creating a symbol.
2245 * Note that the expression still might come from the assembly
2246 * input, in which case the value is not checked for range nor
2247 * is a relocation entry generated (yuck).
2249 if (ep
->X_op
== O_constant
)
2251 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2255 r
= BFD_RELOC_16_PCREL_S2
;
2259 assert (ep
!= NULL
);
2260 r
= BFD_RELOC_MIPS_JMP
;
2269 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2271 append_insn (place
, &insn
, ep
, r
, false);
2275 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2283 struct mips_cl_insn insn
;
2284 bfd_reloc_code_real_type r
;
2286 r
= BFD_RELOC_UNUSED
;
2287 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2288 assert (insn
.insn_mo
);
2289 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2291 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2292 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2295 assert (insn
.insn_mo
->name
);
2296 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2299 insn
.insn_opcode
= insn
.insn_mo
->match
;
2300 insn
.use_extend
= false;
2319 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2324 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2328 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2332 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2342 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2349 regno
= va_arg (args
, int);
2350 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2351 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2372 assert (ep
!= NULL
);
2374 if (ep
->X_op
!= O_constant
)
2375 r
= BFD_RELOC_UNUSED
+ c
;
2378 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2379 false, false, &insn
.insn_opcode
,
2380 &insn
.use_extend
, &insn
.extend
);
2382 r
= BFD_RELOC_UNUSED
;
2388 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2395 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2397 append_insn (place
, &insn
, ep
, r
, false);
2401 * Generate a "lui" instruction.
2404 macro_build_lui (place
, counter
, ep
, regnum
)
2410 expressionS high_expr
;
2411 struct mips_cl_insn insn
;
2412 bfd_reloc_code_real_type r
;
2413 CONST
char *name
= "lui";
2414 CONST
char *fmt
= "t,u";
2422 high_expr
.X_op
= O_constant
;
2423 high_expr
.X_add_number
= ep
->X_add_number
;
2426 if (high_expr
.X_op
== O_constant
)
2428 /* we can compute the instruction now without a relocation entry */
2429 if (high_expr
.X_add_number
& 0x8000)
2430 high_expr
.X_add_number
+= 0x10000;
2431 high_expr
.X_add_number
=
2432 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2433 r
= BFD_RELOC_UNUSED
;
2437 assert (ep
->X_op
== O_symbol
);
2438 /* _gp_disp is a special case, used from s_cpload. */
2439 assert (mips_pic
== NO_PIC
2440 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2441 r
= BFD_RELOC_HI16_S
;
2445 * If the macro is about to expand into a second instruction,
2446 * print a warning if needed. We need to pass ip as a parameter
2447 * to generate a better warning message here...
2449 if (mips_warn_about_macros
&& place
== NULL
&& *counter
== 1)
2450 as_warn ("Macro instruction expanded into multiple instructions");
2453 *counter
+= 1; /* bump instruction counter */
2455 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2456 assert (insn
.insn_mo
);
2457 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2458 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2460 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2461 if (r
== BFD_RELOC_UNUSED
)
2463 insn
.insn_opcode
|= high_expr
.X_add_number
;
2464 append_insn (place
, &insn
, NULL
, r
, false);
2467 append_insn (place
, &insn
, &high_expr
, r
, false);
2471 * Generates code to set the $at register to true (one)
2472 * if reg is less than the immediate expression.
2475 set_at (counter
, reg
, unsignedp
)
2480 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
2481 macro_build ((char *) NULL
, counter
, &imm_expr
,
2482 unsignedp
? "sltiu" : "slti",
2483 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2486 load_register (counter
, AT
, &imm_expr
, 0);
2487 macro_build ((char *) NULL
, counter
, NULL
,
2488 unsignedp
? "sltu" : "slt",
2489 "d,v,t", AT
, reg
, AT
);
2493 /* Warn if an expression is not a constant. */
2496 check_absolute_expr (ip
, ex
)
2497 struct mips_cl_insn
*ip
;
2500 if (ex
->X_op
!= O_constant
)
2501 as_warn ("Instruction %s requires absolute expression", ip
->insn_mo
->name
);
2504 /* Count the leading zeroes by performing a binary chop. This is a
2505 bulky bit of source, but performance is a LOT better for the
2506 majority of values than a simple loop to count the bits:
2507 for (lcnt = 0; (lcnt < 32); lcnt++)
2508 if ((v) & (1 << (31 - lcnt)))
2510 However it is not code size friendly, and the gain will drop a bit
2511 on certain cached systems.
2513 #define COUNT_TOP_ZEROES(v) \
2514 (((v) & ~0xffff) == 0 \
2515 ? ((v) & ~0xff) == 0 \
2516 ? ((v) & ~0xf) == 0 \
2517 ? ((v) & ~0x3) == 0 \
2518 ? ((v) & ~0x1) == 0 \
2523 : ((v) & ~0x7) == 0 \
2526 : ((v) & ~0x3f) == 0 \
2527 ? ((v) & ~0x1f) == 0 \
2530 : ((v) & ~0x7f) == 0 \
2533 : ((v) & ~0xfff) == 0 \
2534 ? ((v) & ~0x3ff) == 0 \
2535 ? ((v) & ~0x1ff) == 0 \
2538 : ((v) & ~0x7ff) == 0 \
2541 : ((v) & ~0x3fff) == 0 \
2542 ? ((v) & ~0x1fff) == 0 \
2545 : ((v) & ~0x7fff) == 0 \
2548 : ((v) & ~0xffffff) == 0 \
2549 ? ((v) & ~0xfffff) == 0 \
2550 ? ((v) & ~0x3ffff) == 0 \
2551 ? ((v) & ~0x1ffff) == 0 \
2554 : ((v) & ~0x7ffff) == 0 \
2557 : ((v) & ~0x3fffff) == 0 \
2558 ? ((v) & ~0x1fffff) == 0 \
2561 : ((v) & ~0x7fffff) == 0 \
2564 : ((v) & ~0xfffffff) == 0 \
2565 ? ((v) & ~0x3ffffff) == 0 \
2566 ? ((v) & ~0x1ffffff) == 0 \
2569 : ((v) & ~0x7ffffff) == 0 \
2572 : ((v) & ~0x3fffffff) == 0 \
2573 ? ((v) & ~0x1fffffff) == 0 \
2576 : ((v) & ~0x7fffffff) == 0 \
2581 * This routine generates the least number of instructions neccessary to load
2582 * an absolute expression value into a register.
2585 load_register (counter
, reg
, ep
, dbl
)
2592 expressionS hi32
, lo32
;
2594 if (ep
->X_op
!= O_big
)
2596 assert (ep
->X_op
== O_constant
);
2597 if (ep
->X_add_number
< 0x8000
2598 && (ep
->X_add_number
>= 0
2599 || (ep
->X_add_number
>= -0x8000
2602 || sizeof (ep
->X_add_number
) > 4))))
2604 /* We can handle 16 bit signed values with an addiu to
2605 $zero. No need to ever use daddiu here, since $zero and
2606 the result are always correct in 32 bit mode. */
2607 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2608 (int) BFD_RELOC_LO16
);
2611 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
2613 /* We can handle 16 bit unsigned values with an ori to
2615 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
2616 (int) BFD_RELOC_LO16
);
2619 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
2620 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
2621 == ~ (offsetT
) 0x7fffffff))
2624 || sizeof (ep
->X_add_number
) > 4
2625 || (ep
->X_add_number
& 0x80000000) == 0))
2626 || ((mips_isa
< 3 || !dbl
)
2627 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0))
2629 /* 32 bit values require an lui. */
2630 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2631 (int) BFD_RELOC_HI16
);
2632 if ((ep
->X_add_number
& 0xffff) != 0)
2633 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
2634 (int) BFD_RELOC_LO16
);
2639 /* The value is larger than 32 bits. */
2643 as_bad ("Number larger than 32 bits");
2644 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2645 (int) BFD_RELOC_LO16
);
2649 if (ep
->X_op
!= O_big
)
2652 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2653 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
2654 hi32
.X_add_number
&= 0xffffffff;
2656 lo32
.X_add_number
&= 0xffffffff;
2660 assert (ep
->X_add_number
> 2);
2661 if (ep
->X_add_number
== 3)
2662 generic_bignum
[3] = 0;
2663 else if (ep
->X_add_number
> 4)
2664 as_bad ("Number larger than 64 bits");
2665 lo32
.X_op
= O_constant
;
2666 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
2667 hi32
.X_op
= O_constant
;
2668 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
2671 if (hi32
.X_add_number
== 0)
2676 unsigned long hi
, lo
;
2678 if (hi32
.X_add_number
== 0xffffffff)
2680 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
2682 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
2683 reg
, 0, (int) BFD_RELOC_LO16
);
2686 if (lo32
.X_add_number
& 0x80000000)
2688 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2689 (int) BFD_RELOC_HI16
);
2690 if (lo32
.X_add_number
& 0xffff)
2691 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
2692 reg
, reg
, (int) BFD_RELOC_LO16
);
2697 /* Check for 16bit shifted constant. We know that hi32 is
2698 non-zero, so start the mask on the first bit of the hi32
2703 unsigned long himask
, lomask
;
2707 himask
= 0xffff >> (32 - shift
);
2708 lomask
= (0xffff << shift
) & 0xffffffff;
2712 himask
= 0xffff << (shift
- 32);
2715 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
2716 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
2720 tmp
.X_op
= O_constant
;
2722 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
2723 | (lo32
.X_add_number
>> shift
));
2725 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
2726 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
2727 (int) BFD_RELOC_LO16
);
2728 macro_build ((char *) NULL
, counter
, NULL
,
2729 (shift
>= 32) ? "dsll32" : "dsll",
2731 (shift
>= 32) ? shift
- 32 : shift
);
2735 } while (shift
<= (64 - 16));
2737 /* Find the bit number of the lowest one bit, and store the
2738 shifted value in hi/lo. */
2739 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
2740 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
2744 while ((lo
& 1) == 0)
2749 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
2755 while ((hi
& 1) == 0)
2764 /* Optimize if the shifted value is a (power of 2) - 1. */
2765 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
2766 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
2768 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
2773 /* This instruction will set the register to be all
2775 tmp
.X_op
= O_constant
;
2776 tmp
.X_add_number
= (offsetT
) -1;
2777 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
2778 reg
, 0, (int) BFD_RELOC_LO16
);
2782 macro_build ((char *) NULL
, counter
, NULL
,
2783 (bit
>= 32) ? "dsll32" : "dsll",
2785 (bit
>= 32) ? bit
- 32 : bit
);
2787 macro_build ((char *) NULL
, counter
, NULL
,
2788 (shift
>= 32) ? "dsrl32" : "dsrl",
2790 (shift
>= 32) ? shift
- 32 : shift
);
2795 /* Sign extend hi32 before calling load_register, because we can
2796 generally get better code when we load a sign extended value. */
2797 if ((hi32
.X_add_number
& 0x80000000) != 0)
2798 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
2799 load_register (counter
, reg
, &hi32
, 0);
2802 if ((lo32
.X_add_number
& 0xffff0000) == 0)
2806 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
2815 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
2817 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
2818 (int) BFD_RELOC_HI16
);
2819 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
2826 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2831 mid16
.X_add_number
>>= 16;
2832 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
2833 freg
, (int) BFD_RELOC_LO16
);
2834 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
2838 if ((lo32
.X_add_number
& 0xffff) != 0)
2839 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
2840 (int) BFD_RELOC_LO16
);
2843 /* Load an address into a register. */
2846 load_address (counter
, reg
, ep
)
2853 if (ep
->X_op
!= O_constant
2854 && ep
->X_op
!= O_symbol
)
2856 as_bad ("expression too complex");
2857 ep
->X_op
= O_constant
;
2860 if (ep
->X_op
== O_constant
)
2862 load_register (counter
, reg
, ep
, 0);
2866 if (mips_pic
== NO_PIC
)
2868 /* If this is a reference to a GP relative symbol, we want
2869 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2871 lui $reg,<sym> (BFD_RELOC_HI16_S)
2872 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2873 If we have an addend, we always use the latter form. */
2874 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
2875 || nopic_need_relax (ep
->X_add_symbol
))
2880 macro_build ((char *) NULL
, counter
, ep
,
2881 mips_isa
< 3 ? "addiu" : "daddiu",
2882 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
2883 p
= frag_var (rs_machine_dependent
, 8, 0,
2884 RELAX_ENCODE (4, 8, 0, 4, 0, mips_warn_about_macros
),
2885 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2887 macro_build_lui (p
, counter
, ep
, reg
);
2890 macro_build (p
, counter
, ep
,
2891 mips_isa
< 3 ? "addiu" : "daddiu",
2892 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2894 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
2898 /* If this is a reference to an external symbol, we want
2899 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2901 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2903 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2904 If there is a constant, it must be added in after. */
2905 ex
.X_add_number
= ep
->X_add_number
;
2906 ep
->X_add_number
= 0;
2908 macro_build ((char *) NULL
, counter
, ep
,
2909 mips_isa
< 3 ? "lw" : "ld",
2910 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2911 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
2912 p
= frag_var (rs_machine_dependent
, 4, 0,
2913 RELAX_ENCODE (0, 4, -8, 0, 0, mips_warn_about_macros
),
2914 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2915 macro_build (p
, counter
, ep
,
2916 mips_isa
< 3 ? "addiu" : "daddiu",
2917 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2918 if (ex
.X_add_number
!= 0)
2920 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2921 as_bad ("PIC code offset overflow (max 16 signed bits)");
2922 ex
.X_op
= O_constant
;
2923 macro_build ((char *) NULL
, counter
, &ex
,
2924 mips_isa
< 3 ? "addiu" : "daddiu",
2925 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2928 else if (mips_pic
== SVR4_PIC
)
2933 /* This is the large GOT case. If this is a reference to an
2934 external symbol, we want
2935 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
2937 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
2938 Otherwise, for a reference to a local symbol, we want
2939 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
2941 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
2942 If there is a constant, it must be added in after. */
2943 ex
.X_add_number
= ep
->X_add_number
;
2944 ep
->X_add_number
= 0;
2945 if (reg_needs_delay (GP
))
2950 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
2951 (int) BFD_RELOC_MIPS_GOT_HI16
);
2952 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
2953 mips_isa
< 3 ? "addu" : "daddu",
2954 "d,v,t", reg
, reg
, GP
);
2955 macro_build ((char *) NULL
, counter
, ep
,
2956 mips_isa
< 3 ? "lw" : "ld",
2957 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
2958 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
2959 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
2960 mips_warn_about_macros
),
2961 ep
->X_add_symbol
, (long) 0, (char *) NULL
);
2964 /* We need a nop before loading from $gp. This special
2965 check is required because the lui which starts the main
2966 instruction stream does not refer to $gp, and so will not
2967 insert the nop which may be required. */
2968 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2971 macro_build (p
, counter
, ep
,
2972 mips_isa
< 3 ? "lw" : "ld",
2973 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
2975 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
2977 macro_build (p
, counter
, ep
,
2978 mips_isa
< 3 ? "addiu" : "daddiu",
2979 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2980 if (ex
.X_add_number
!= 0)
2982 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
2983 as_bad ("PIC code offset overflow (max 16 signed bits)");
2984 ex
.X_op
= O_constant
;
2985 macro_build ((char *) NULL
, counter
, &ex
,
2986 mips_isa
< 3 ? "addiu" : "daddiu",
2987 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
2990 else if (mips_pic
== EMBEDDED_PIC
)
2993 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
2995 macro_build ((char *) NULL
, counter
, ep
,
2996 mips_isa
< 3 ? "addiu" : "daddiu",
2997 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3005 * This routine implements the seemingly endless macro or synthesized
3006 * instructions and addressing modes in the mips assembly language. Many
3007 * of these macros are simple and are similar to each other. These could
3008 * probably be handled by some kind of table or grammer aproach instead of
3009 * this verbose method. Others are not simple macros but are more like
3010 * optimizing code generation.
3011 * One interesting optimization is when several store macros appear
3012 * consecutivly that would load AT with the upper half of the same address.
3013 * The ensuing load upper instructions are ommited. This implies some kind
3014 * of global optimization. We currently only optimize within a single macro.
3015 * For many of the load and store macros if the address is specified as a
3016 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3017 * first load register 'at' with zero and use it as the base register. The
3018 * mips assembler simply uses register $zero. Just one tiny optimization
3023 struct mips_cl_insn
*ip
;
3025 register int treg
, sreg
, dreg
, breg
;
3040 bfd_reloc_code_real_type r
;
3042 int hold_mips_optimize
;
3046 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3047 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3048 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3049 mask
= ip
->insn_mo
->mask
;
3051 expr1
.X_op
= O_constant
;
3052 expr1
.X_op_symbol
= NULL
;
3053 expr1
.X_add_symbol
= NULL
;
3054 expr1
.X_add_number
= 1;
3066 mips_emit_delays (true);
3068 mips_any_noreorder
= 1;
3070 expr1
.X_add_number
= 8;
3071 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3073 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3075 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3076 macro_build ((char *) NULL
, &icnt
, NULL
,
3077 dbl
? "dsub" : "sub",
3078 "d,v,t", dreg
, 0, sreg
);
3101 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
3103 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3104 (int) BFD_RELOC_LO16
);
3107 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3108 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3127 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
3129 if (mask
!= M_NOR_I
)
3130 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3131 sreg
, (int) BFD_RELOC_LO16
);
3134 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3135 treg
, sreg
, (int) BFD_RELOC_LO16
);
3136 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3142 load_register (&icnt
, AT
, &imm_expr
, 0);
3143 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3160 if (imm_expr
.X_add_number
== 0)
3162 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3166 load_register (&icnt
, AT
, &imm_expr
, 0);
3167 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3175 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3176 likely
? "bgezl" : "bgez",
3182 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3183 likely
? "blezl" : "blez",
3187 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3188 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3189 likely
? "beql" : "beq",
3196 /* check for > max integer */
3197 maxnum
= 0x7fffffff;
3205 if (imm_expr
.X_add_number
>= maxnum
3206 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3209 /* result is always false */
3212 as_warn ("Branch %s is always false (nop)", ip
->insn_mo
->name
);
3213 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3217 as_warn ("Branch likely %s is always false", ip
->insn_mo
->name
);
3218 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3223 imm_expr
.X_add_number
++;
3227 if (mask
== M_BGEL_I
)
3229 if (imm_expr
.X_add_number
== 0)
3231 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3232 likely
? "bgezl" : "bgez",
3236 if (imm_expr
.X_add_number
== 1)
3238 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3239 likely
? "bgtzl" : "bgtz",
3243 maxnum
= 0x7fffffff;
3251 maxnum
= - maxnum
- 1;
3252 if (imm_expr
.X_add_number
<= maxnum
3253 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3256 /* result is always true */
3257 as_warn ("Branch %s is always true", ip
->insn_mo
->name
);
3258 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3261 set_at (&icnt
, sreg
, 0);
3262 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3263 likely
? "beql" : "beq",
3274 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3275 likely
? "beql" : "beq",
3279 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3281 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3282 likely
? "beql" : "beq",
3289 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3291 imm_expr
.X_add_number
++;
3295 if (mask
== M_BGEUL_I
)
3297 if (imm_expr
.X_add_number
== 0)
3299 if (imm_expr
.X_add_number
== 1)
3301 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3302 likely
? "bnel" : "bne",
3306 set_at (&icnt
, sreg
, 1);
3307 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3308 likely
? "beql" : "beq",
3317 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3318 likely
? "bgtzl" : "bgtz",
3324 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3325 likely
? "bltzl" : "bltz",
3329 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3330 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3331 likely
? "bnel" : "bne",
3340 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3341 likely
? "bnel" : "bne",
3347 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3349 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3350 likely
? "bnel" : "bne",
3359 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3360 likely
? "blezl" : "blez",
3366 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3367 likely
? "bgezl" : "bgez",
3371 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3372 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3373 likely
? "beql" : "beq",
3380 maxnum
= 0x7fffffff;
3388 if (imm_expr
.X_add_number
>= maxnum
3389 && (mips_isa
< 3 || sizeof (maxnum
) > 4))
3391 imm_expr
.X_add_number
++;
3395 if (mask
== M_BLTL_I
)
3397 if (imm_expr
.X_add_number
== 0)
3399 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3400 likely
? "bltzl" : "bltz",
3404 if (imm_expr
.X_add_number
== 1)
3406 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3407 likely
? "blezl" : "blez",
3411 set_at (&icnt
, sreg
, 0);
3412 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3413 likely
? "bnel" : "bne",
3422 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3423 likely
? "beql" : "beq",
3429 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3431 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3432 likely
? "beql" : "beq",
3439 if (sreg
== 0 || imm_expr
.X_add_number
== -1)
3441 imm_expr
.X_add_number
++;
3445 if (mask
== M_BLTUL_I
)
3447 if (imm_expr
.X_add_number
== 0)
3449 if (imm_expr
.X_add_number
== 1)
3451 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3452 likely
? "beql" : "beq",
3456 set_at (&icnt
, sreg
, 1);
3457 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3458 likely
? "bnel" : "bne",
3467 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3468 likely
? "bltzl" : "bltz",
3474 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3475 likely
? "bgtzl" : "bgtz",
3479 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3480 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3481 likely
? "bnel" : "bne",
3492 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3493 likely
? "bnel" : "bne",
3497 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3499 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3500 likely
? "bnel" : "bne",
3516 as_warn ("Divide by zero.");
3518 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3520 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3524 mips_emit_delays (true);
3526 mips_any_noreorder
= 1;
3527 macro_build ((char *) NULL
, &icnt
, NULL
,
3528 dbl
? "ddiv" : "div",
3529 "z,s,t", sreg
, treg
);
3531 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3534 expr1
.X_add_number
= 8;
3535 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3536 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3537 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3539 expr1
.X_add_number
= -1;
3540 macro_build ((char *) NULL
, &icnt
, &expr1
,
3541 dbl
? "daddiu" : "addiu",
3542 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3543 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3544 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3547 expr1
.X_add_number
= 1;
3548 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3549 (int) BFD_RELOC_LO16
);
3550 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3555 expr1
.X_add_number
= 0x80000000;
3556 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
3557 (int) BFD_RELOC_HI16
);
3560 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
3563 expr1
.X_add_number
= 8;
3564 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
3565 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3566 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
3569 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
3608 if (imm_expr
.X_add_number
== 0)
3610 as_warn ("Divide by zero.");
3612 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3614 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3617 if (imm_expr
.X_add_number
== 1)
3619 if (strcmp (s2
, "mflo") == 0)
3620 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
3623 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3626 if (imm_expr
.X_add_number
== -1
3627 && s
[strlen (s
) - 1] != 'u')
3629 if (strcmp (s2
, "mflo") == 0)
3632 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
3635 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
3639 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
3643 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3644 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
3645 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3664 mips_emit_delays (true);
3666 mips_any_noreorder
= 1;
3667 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
3669 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3672 expr1
.X_add_number
= 8;
3673 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3674 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3675 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3678 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
3684 /* Load the address of a symbol into a register. If breg is not
3685 zero, we then add a base register to it. */
3687 /* When generating embedded PIC code, we permit expressions of
3690 where bar is an address in the .text section. These are used
3691 when getting the addresses of functions. We don't permit
3692 X_add_number to be non-zero, because if the symbol is
3693 external the relaxing code needs to know that any addend is
3694 purely the offset to X_op_symbol. */
3695 if (mips_pic
== EMBEDDED_PIC
3696 && offset_expr
.X_op
== O_subtract
3697 && now_seg
== text_section
3698 && (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_constant
3699 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == text_section
3700 : (offset_expr
.X_op_symbol
->sy_value
.X_op
== O_symbol
3701 && (S_GET_SEGMENT (offset_expr
.X_op_symbol
3702 ->sy_value
.X_add_symbol
)
3705 && offset_expr
.X_add_number
== 0)
3707 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3708 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
3709 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3710 mips_isa
< 3 ? "addiu" : "daddiu",
3711 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
3715 if (offset_expr
.X_op
!= O_symbol
3716 && offset_expr
.X_op
!= O_constant
)
3718 as_bad ("expression too complex");
3719 offset_expr
.X_op
= O_constant
;
3733 if (offset_expr
.X_op
== O_constant
)
3734 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
3735 else if (mips_pic
== NO_PIC
)
3737 /* If this is a reference to an GP relative symbol, we want
3738 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3740 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
3741 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3742 If we have a constant, we need two instructions anyhow,
3743 so we may as well always use the latter form. */
3744 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
3745 || nopic_need_relax (offset_expr
.X_add_symbol
))
3750 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3751 mips_isa
< 3 ? "addiu" : "daddiu",
3752 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3753 p
= frag_var (rs_machine_dependent
, 8, 0,
3754 RELAX_ENCODE (4, 8, 0, 4, 0,
3755 mips_warn_about_macros
),
3756 offset_expr
.X_add_symbol
, (long) 0,
3759 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
3762 macro_build (p
, &icnt
, &offset_expr
,
3763 mips_isa
< 3 ? "addiu" : "daddiu",
3764 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3766 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3768 /* If this is a reference to an external symbol, and there
3769 is no constant, we want
3770 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3771 For a local symbol, we want
3772 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3774 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3776 If we have a small constant, and this is a reference to
3777 an external symbol, we want
3778 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3780 addiu $tempreg,$tempreg,<constant>
3781 For a local symbol, we want the same instruction
3782 sequence, but we output a BFD_RELOC_LO16 reloc on the
3785 If we have a large constant, and this is a reference to
3786 an external symbol, we want
3787 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3788 lui $at,<hiconstant>
3789 addiu $at,$at,<loconstant>
3790 addu $tempreg,$tempreg,$at
3791 For a local symbol, we want the same instruction
3792 sequence, but we output a BFD_RELOC_LO16 reloc on the
3793 addiu instruction. */
3794 expr1
.X_add_number
= offset_expr
.X_add_number
;
3795 offset_expr
.X_add_number
= 0;
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3799 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3800 if (expr1
.X_add_number
== 0)
3808 /* We're going to put in an addu instruction using
3809 tempreg, so we may as well insert the nop right
3811 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3815 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
3816 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
3818 ? mips_warn_about_macros
3820 offset_expr
.X_add_symbol
, (long) 0,
3824 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
3827 macro_build (p
, &icnt
, &expr1
,
3828 mips_isa
< 3 ? "addiu" : "daddiu",
3829 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3830 /* FIXME: If breg == 0, and the next instruction uses
3831 $tempreg, then if this variant case is used an extra
3832 nop will be generated. */
3834 else if (expr1
.X_add_number
>= -0x8000
3835 && expr1
.X_add_number
< 0x8000)
3837 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3839 macro_build ((char *) NULL
, &icnt
, &expr1
,
3840 mips_isa
< 3 ? "addiu" : "daddiu",
3841 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3842 (void) frag_var (rs_machine_dependent
, 0, 0,
3843 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
3844 offset_expr
.X_add_symbol
, (long) 0,
3851 /* If we are going to add in a base register, and the
3852 target register and the base register are the same,
3853 then we are using AT as a temporary register. Since
3854 we want to load the constant into AT, we add our
3855 current AT (from the global offset table) and the
3856 register into the register now, and pretend we were
3857 not using a base register. */
3862 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3864 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3865 mips_isa
< 3 ? "addu" : "daddu",
3866 "d,v,t", treg
, AT
, breg
);
3872 /* Set mips_optimize around the lui instruction to avoid
3873 inserting an unnecessary nop after the lw. */
3874 hold_mips_optimize
= mips_optimize
;
3876 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
3877 mips_optimize
= hold_mips_optimize
;
3879 macro_build ((char *) NULL
, &icnt
, &expr1
,
3880 mips_isa
< 3 ? "addiu" : "daddiu",
3881 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
3882 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3883 mips_isa
< 3 ? "addu" : "daddu",
3884 "d,v,t", tempreg
, tempreg
, AT
);
3885 (void) frag_var (rs_machine_dependent
, 0, 0,
3886 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
3887 offset_expr
.X_add_symbol
, (long) 0,
3892 else if (mips_pic
== SVR4_PIC
)
3896 /* This is the large GOT case. If this is a reference to an
3897 external symbol, and there is no constant, we want
3898 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3899 addu $tempreg,$tempreg,$gp
3900 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3901 For a local symbol, we want
3902 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3904 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
3906 If we have a small constant, and this is a reference to
3907 an external symbol, we want
3908 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3909 addu $tempreg,$tempreg,$gp
3910 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3912 addiu $tempreg,$tempreg,<constant>
3913 For a local symbol, we want
3914 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3916 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
3918 If we have a large constant, and this is a reference to
3919 an external symbol, we want
3920 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3921 addu $tempreg,$tempreg,$gp
3922 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
3923 lui $at,<hiconstant>
3924 addiu $at,$at,<loconstant>
3925 addu $tempreg,$tempreg,$at
3926 For a local symbol, we want
3927 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3928 lui $at,<hiconstant>
3929 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
3930 addu $tempreg,$tempreg,$at
3932 expr1
.X_add_number
= offset_expr
.X_add_number
;
3933 offset_expr
.X_add_number
= 0;
3935 if (reg_needs_delay (GP
))
3939 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
3940 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
3941 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3942 mips_isa
< 3 ? "addu" : "daddu",
3943 "d,v,t", tempreg
, tempreg
, GP
);
3944 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3946 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
3948 if (expr1
.X_add_number
== 0)
3956 /* We're going to put in an addu instruction using
3957 tempreg, so we may as well insert the nop right
3959 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3964 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3965 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
3968 ? mips_warn_about_macros
3970 offset_expr
.X_add_symbol
, (long) 0,
3973 else if (expr1
.X_add_number
>= -0x8000
3974 && expr1
.X_add_number
< 0x8000)
3976 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
3978 macro_build ((char *) NULL
, &icnt
, &expr1
,
3979 mips_isa
< 3 ? "addiu" : "daddiu",
3980 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
3982 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
3983 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
3985 ? mips_warn_about_macros
3987 offset_expr
.X_add_symbol
, (long) 0,
3994 /* If we are going to add in a base register, and the
3995 target register and the base register are the same,
3996 then we are using AT as a temporary register. Since
3997 we want to load the constant into AT, we add our
3998 current AT (from the global offset table) and the
3999 register into the register now, and pretend we were
4000 not using a base register. */
4008 assert (tempreg
== AT
);
4009 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4011 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4012 mips_isa
< 3 ? "addu" : "daddu",
4013 "d,v,t", treg
, AT
, breg
);
4018 /* Set mips_optimize around the lui instruction to avoid
4019 inserting an unnecessary nop after the lw. */
4020 hold_mips_optimize
= mips_optimize
;
4022 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4023 mips_optimize
= hold_mips_optimize
;
4025 macro_build ((char *) NULL
, &icnt
, &expr1
,
4026 mips_isa
< 3 ? "addiu" : "daddiu",
4027 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4028 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4029 mips_isa
< 3 ? "addu" : "daddu",
4030 "d,v,t", dreg
, dreg
, AT
);
4032 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4033 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4036 ? mips_warn_about_macros
4038 offset_expr
.X_add_symbol
, (long) 0,
4046 /* This is needed because this instruction uses $gp, but
4047 the first instruction on the main stream does not. */
4048 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4051 macro_build (p
, &icnt
, &offset_expr
,
4053 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4055 if (expr1
.X_add_number
>= -0x8000
4056 && expr1
.X_add_number
< 0x8000)
4058 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4060 macro_build (p
, &icnt
, &expr1
,
4061 mips_isa
< 3 ? "addiu" : "daddiu",
4062 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4063 /* FIXME: If add_number is 0, and there was no base
4064 register, the external symbol case ended with a load,
4065 so if the symbol turns out to not be external, and
4066 the next instruction uses tempreg, an unnecessary nop
4067 will be inserted. */
4073 /* We must add in the base register now, as in the
4074 external symbol case. */
4075 assert (tempreg
== AT
);
4076 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4078 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4079 mips_isa
< 3 ? "addu" : "daddu",
4080 "d,v,t", treg
, AT
, breg
);
4083 /* We set breg to 0 because we have arranged to add
4084 it in in both cases. */
4088 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4090 macro_build (p
, &icnt
, &expr1
,
4091 mips_isa
< 3 ? "addiu" : "daddiu",
4092 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4094 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4095 mips_isa
< 3 ? "addu" : "daddu",
4096 "d,v,t", tempreg
, tempreg
, AT
);
4100 else if (mips_pic
== EMBEDDED_PIC
)
4103 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4105 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4106 mips_isa
< 3 ? "addiu" : "daddiu",
4107 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4113 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4114 mips_isa
< 3 ? "addu" : "daddu",
4115 "d,v,t", treg
, tempreg
, breg
);
4123 /* The j instruction may not be used in PIC code, since it
4124 requires an absolute address. We convert it to a b
4126 if (mips_pic
== NO_PIC
)
4127 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4129 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4132 /* The jal instructions must be handled as macros because when
4133 generating PIC code they expand to multi-instruction
4134 sequences. Normally they are simple instructions. */
4139 if (mips_pic
== NO_PIC
4140 || mips_pic
== EMBEDDED_PIC
)
4141 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4143 else if (mips_pic
== SVR4_PIC
)
4145 if (sreg
!= PIC_CALL_REG
)
4146 as_warn ("MIPS PIC call to register other than $25");
4148 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4150 if (mips_cprestore_offset
< 0)
4151 as_warn ("No .cprestore pseudo-op used in PIC code");
4154 expr1
.X_add_number
= mips_cprestore_offset
;
4155 macro_build ((char *) NULL
, &icnt
, &expr1
,
4156 mips_isa
< 3 ? "lw" : "ld",
4157 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4166 if (mips_pic
== NO_PIC
)
4167 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4168 else if (mips_pic
== SVR4_PIC
)
4170 /* If this is a reference to an external symbol, and we are
4171 using a small GOT, we want
4172 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4176 lw $gp,cprestore($sp)
4177 The cprestore value is set using the .cprestore
4178 pseudo-op. If we are using a big GOT, we want
4179 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4181 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4185 lw $gp,cprestore($sp)
4186 If the symbol is not external, we want
4187 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4189 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4192 lw $gp,cprestore($sp) */
4196 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4197 mips_isa
< 3 ? "lw" : "ld",
4198 "t,o(b)", PIC_CALL_REG
,
4199 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4200 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4202 p
= frag_var (rs_machine_dependent
, 4, 0,
4203 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4204 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4210 if (reg_needs_delay (GP
))
4214 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4215 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4216 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4217 mips_isa
< 3 ? "addu" : "daddu",
4218 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4219 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4220 mips_isa
< 3 ? "lw" : "ld",
4221 "t,o(b)", PIC_CALL_REG
,
4222 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4223 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4225 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4226 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4228 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4231 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4234 macro_build (p
, &icnt
, &offset_expr
,
4235 mips_isa
< 3 ? "lw" : "ld",
4236 "t,o(b)", PIC_CALL_REG
,
4237 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4239 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4242 macro_build (p
, &icnt
, &offset_expr
,
4243 mips_isa
< 3 ? "addiu" : "daddiu",
4244 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4245 (int) BFD_RELOC_LO16
);
4246 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4247 "jalr", "s", PIC_CALL_REG
);
4248 if (mips_cprestore_offset
< 0)
4249 as_warn ("No .cprestore pseudo-op used in PIC code");
4253 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4255 expr1
.X_add_number
= mips_cprestore_offset
;
4256 macro_build ((char *) NULL
, &icnt
, &expr1
,
4257 mips_isa
< 3 ? "lw" : "ld",
4258 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4262 else if (mips_pic
== EMBEDDED_PIC
)
4264 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4265 /* The linker may expand the call to a longer sequence which
4266 uses $at, so we must break rather than return. */
4342 if (breg
== treg
|| coproc
|| lr
)
4411 if (mask
== M_LWC1_AB
4412 || mask
== M_SWC1_AB
4413 || mask
== M_LDC1_AB
4414 || mask
== M_SDC1_AB
4423 if (offset_expr
.X_op
!= O_constant
4424 && offset_expr
.X_op
!= O_symbol
)
4426 as_bad ("expression too complex");
4427 offset_expr
.X_op
= O_constant
;
4430 /* A constant expression in PIC code can be handled just as it
4431 is in non PIC code. */
4432 if (mips_pic
== NO_PIC
4433 || offset_expr
.X_op
== O_constant
)
4435 /* If this is a reference to a GP relative symbol, and there
4436 is no base register, we want
4437 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4438 Otherwise, if there is no base register, we want
4439 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4440 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4441 If we have a constant, we need two instructions anyhow,
4442 so we always use the latter form.
4444 If we have a base register, and this is a reference to a
4445 GP relative symbol, we want
4446 addu $tempreg,$breg,$gp
4447 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4449 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4450 addu $tempreg,$tempreg,$breg
4451 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4452 With a constant we always use the latter case. */
4455 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4456 || nopic_need_relax (offset_expr
.X_add_symbol
))
4461 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4462 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4463 p
= frag_var (rs_machine_dependent
, 8, 0,
4464 RELAX_ENCODE (4, 8, 0, 4, 0,
4465 (mips_warn_about_macros
4466 || (used_at
&& mips_noat
))),
4467 offset_expr
.X_add_symbol
, (long) 0,
4471 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4474 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4475 (int) BFD_RELOC_LO16
, tempreg
);
4479 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4480 || nopic_need_relax (offset_expr
.X_add_symbol
))
4485 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4486 mips_isa
< 3 ? "addu" : "daddu",
4487 "d,v,t", tempreg
, breg
, GP
);
4488 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4489 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4490 p
= frag_var (rs_machine_dependent
, 12, 0,
4491 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
4492 offset_expr
.X_add_symbol
, (long) 0,
4495 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4498 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4499 mips_isa
< 3 ? "addu" : "daddu",
4500 "d,v,t", tempreg
, tempreg
, breg
);
4503 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
4504 (int) BFD_RELOC_LO16
, tempreg
);
4507 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4509 /* If this is a reference to an external symbol, we want
4510 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4512 <op> $treg,0($tempreg)
4514 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4516 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4517 <op> $treg,0($tempreg)
4518 If there is a base register, we add it to $tempreg before
4519 the <op>. If there is a constant, we stick it in the
4520 <op> instruction. We don't handle constants larger than
4521 16 bits, because we have no way to load the upper 16 bits
4522 (actually, we could handle them for the subset of cases
4523 in which we are not using $at). */
4524 assert (offset_expr
.X_op
== O_symbol
);
4525 expr1
.X_add_number
= offset_expr
.X_add_number
;
4526 offset_expr
.X_add_number
= 0;
4527 if (expr1
.X_add_number
< -0x8000
4528 || expr1
.X_add_number
>= 0x8000)
4529 as_bad ("PIC code offset overflow (max 16 signed bits)");
4531 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4532 mips_isa
< 3 ? "lw" : "ld",
4533 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4534 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4535 p
= frag_var (rs_machine_dependent
, 4, 0,
4536 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4537 offset_expr
.X_add_symbol
, (long) 0,
4539 macro_build (p
, &icnt
, &offset_expr
,
4540 mips_isa
< 3 ? "addiu" : "daddiu",
4541 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4543 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4544 mips_isa
< 3 ? "addu" : "daddu",
4545 "d,v,t", tempreg
, tempreg
, breg
);
4546 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4547 (int) BFD_RELOC_LO16
, tempreg
);
4549 else if (mips_pic
== SVR4_PIC
)
4553 /* If this is a reference to an external symbol, we want
4554 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4555 addu $tempreg,$tempreg,$gp
4556 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4557 <op> $treg,0($tempreg)
4559 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4561 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4562 <op> $treg,0($tempreg)
4563 If there is a base register, we add it to $tempreg before
4564 the <op>. If there is a constant, we stick it in the
4565 <op> instruction. We don't handle constants larger than
4566 16 bits, because we have no way to load the upper 16 bits
4567 (actually, we could handle them for the subset of cases
4568 in which we are not using $at). */
4569 assert (offset_expr
.X_op
== O_symbol
);
4570 expr1
.X_add_number
= offset_expr
.X_add_number
;
4571 offset_expr
.X_add_number
= 0;
4572 if (expr1
.X_add_number
< -0x8000
4573 || expr1
.X_add_number
>= 0x8000)
4574 as_bad ("PIC code offset overflow (max 16 signed bits)");
4575 if (reg_needs_delay (GP
))
4580 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4581 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4582 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4583 mips_isa
< 3 ? "addu" : "daddu",
4584 "d,v,t", tempreg
, tempreg
, GP
);
4585 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4586 mips_isa
< 3 ? "lw" : "ld",
4587 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4589 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4590 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
4591 offset_expr
.X_add_symbol
, (long) 0, (char *) NULL
);
4594 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4597 macro_build (p
, &icnt
, &offset_expr
,
4598 mips_isa
< 3 ? "lw" : "ld",
4599 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4601 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4603 macro_build (p
, &icnt
, &offset_expr
,
4604 mips_isa
< 3 ? "addiu" : "daddiu",
4605 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4607 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4608 mips_isa
< 3 ? "addu" : "daddu",
4609 "d,v,t", tempreg
, tempreg
, breg
);
4610 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
4611 (int) BFD_RELOC_LO16
, tempreg
);
4613 else if (mips_pic
== EMBEDDED_PIC
)
4615 /* If there is no base register, we want
4616 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4617 If there is a base register, we want
4618 addu $tempreg,$breg,$gp
4619 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4621 assert (offset_expr
.X_op
== O_symbol
);
4624 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4625 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
4630 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4631 mips_isa
< 3 ? "addu" : "daddu",
4632 "d,v,t", tempreg
, breg
, GP
);
4633 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4634 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4647 load_register (&icnt
, treg
, &imm_expr
, 0);
4651 load_register (&icnt
, treg
, &imm_expr
, 1);
4655 if (imm_expr
.X_op
== O_constant
)
4657 load_register (&icnt
, AT
, &imm_expr
, 0);
4658 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4659 "mtc1", "t,G", AT
, treg
);
4664 assert (offset_expr
.X_op
== O_symbol
4665 && strcmp (segment_name (S_GET_SEGMENT
4666 (offset_expr
.X_add_symbol
)),
4668 && offset_expr
.X_add_number
== 0);
4669 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4670 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4675 /* We know that sym is in the .rdata section. First we get the
4676 upper 16 bits of the address. */
4677 if (mips_pic
== NO_PIC
)
4679 /* FIXME: This won't work for a 64 bit address. */
4680 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4682 else if (mips_pic
== SVR4_PIC
)
4684 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4685 mips_isa
< 3 ? "lw" : "ld",
4686 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4688 else if (mips_pic
== EMBEDDED_PIC
)
4690 /* For embedded PIC we pick up the entire address off $gp in
4691 a single instruction. */
4692 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4693 mips_isa
< 3 ? "addiu" : "daddiu",
4694 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4695 offset_expr
.X_op
= O_constant
;
4696 offset_expr
.X_add_number
= 0;
4701 /* Now we load the register(s). */
4703 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
4704 treg
, (int) BFD_RELOC_LO16
, AT
);
4707 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4708 treg
, (int) BFD_RELOC_LO16
, AT
);
4711 /* FIXME: How in the world do we deal with the possible
4713 offset_expr
.X_add_number
+= 4;
4714 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
4715 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
4719 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4720 does not become a variant frag. */
4721 frag_wane (frag_now
);
4727 assert (offset_expr
.X_op
== O_symbol
4728 && offset_expr
.X_add_number
== 0);
4729 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
4730 if (strcmp (s
, ".lit8") == 0)
4734 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4735 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
4739 r
= BFD_RELOC_MIPS_LITERAL
;
4744 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
4745 if (mips_pic
== SVR4_PIC
)
4746 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4747 mips_isa
< 3 ? "lw" : "ld",
4748 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4751 /* FIXME: This won't work for a 64 bit address. */
4752 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
4757 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
4758 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
4760 /* To avoid confusion in tc_gen_reloc, we must ensure
4761 that this does not become a variant frag. */
4762 frag_wane (frag_now
);
4773 /* Even on a big endian machine $fn comes before $fn+1. We have
4774 to adjust when loading from memory. */
4777 assert (mips_isa
< 2);
4778 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4779 target_big_endian
? treg
+ 1 : treg
,
4781 /* FIXME: A possible overflow which I don't know how to deal
4783 offset_expr
.X_add_number
+= 4;
4784 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
4785 target_big_endian
? treg
: treg
+ 1,
4788 /* To avoid confusion in tc_gen_reloc, we must ensure that this
4789 does not become a variant frag. */
4790 frag_wane (frag_now
);
4799 * The MIPS assembler seems to check for X_add_number not
4800 * being double aligned and generating:
4803 * addiu at,at,%lo(foo+1)
4806 * But, the resulting address is the same after relocation so why
4807 * generate the extra instruction?
4854 if (offset_expr
.X_op
!= O_symbol
4855 && offset_expr
.X_op
!= O_constant
)
4857 as_bad ("expression too complex");
4858 offset_expr
.X_op
= O_constant
;
4861 /* Even on a big endian machine $fn comes before $fn+1. We have
4862 to adjust when loading from memory. We set coproc if we must
4863 load $fn+1 first. */
4864 if (! target_big_endian
)
4867 if (mips_pic
== NO_PIC
4868 || offset_expr
.X_op
== O_constant
)
4870 /* If this is a reference to a GP relative symbol, we want
4871 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4872 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
4873 If we have a base register, we use this
4875 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
4876 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
4877 If this is not a GP relative symbol, we want
4878 lui $at,<sym> (BFD_RELOC_HI16_S)
4879 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4880 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4881 If there is a base register, we add it to $at after the
4882 lui instruction. If there is a constant, we always use
4884 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4885 || nopic_need_relax (offset_expr
.X_add_symbol
))
4904 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4905 mips_isa
< 3 ? "addu" : "daddu",
4906 "d,v,t", AT
, breg
, GP
);
4912 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4913 coproc
? treg
+ 1 : treg
,
4914 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4915 offset_expr
.X_add_number
+= 4;
4917 /* Set mips_optimize to 2 to avoid inserting an
4919 hold_mips_optimize
= mips_optimize
;
4921 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
4922 coproc
? treg
: treg
+ 1,
4923 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
4924 mips_optimize
= hold_mips_optimize
;
4926 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
4927 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
4928 used_at
&& mips_noat
),
4929 offset_expr
.X_add_symbol
, (long) 0,
4932 /* We just generated two relocs. When tc_gen_reloc
4933 handles this case, it will skip the first reloc and
4934 handle the second. The second reloc already has an
4935 extra addend of 4, which we added above. We must
4936 subtract it out, and then subtract another 4 to make
4937 the first reloc come out right. The second reloc
4938 will come out right because we are going to add 4 to
4939 offset_expr when we build its instruction below. */
4940 offset_expr
.X_add_number
-= 8;
4941 offset_expr
.X_op
= O_constant
;
4943 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
4948 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4949 mips_isa
< 3 ? "addu" : "daddu",
4950 "d,v,t", AT
, breg
, AT
);
4954 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4955 coproc
? treg
+ 1 : treg
,
4956 (int) BFD_RELOC_LO16
, AT
);
4959 /* FIXME: How do we handle overflow here? */
4960 offset_expr
.X_add_number
+= 4;
4961 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
4962 coproc
? treg
: treg
+ 1,
4963 (int) BFD_RELOC_LO16
, AT
);
4965 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4969 /* If this is a reference to an external symbol, we want
4970 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4975 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4977 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
4978 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
4979 If there is a base register we add it to $at before the
4980 lwc1 instructions. If there is a constant we include it
4981 in the lwc1 instructions. */
4983 expr1
.X_add_number
= offset_expr
.X_add_number
;
4984 offset_expr
.X_add_number
= 0;
4985 if (expr1
.X_add_number
< -0x8000
4986 || expr1
.X_add_number
>= 0x8000 - 4)
4987 as_bad ("PIC code offset overflow (max 16 signed bits)");
4992 frag_grow (24 + off
);
4993 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4994 mips_isa
< 3 ? "lw" : "ld",
4995 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4996 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
4998 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4999 mips_isa
< 3 ? "addu" : "daddu",
5000 "d,v,t", AT
, breg
, AT
);
5001 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5002 coproc
? treg
+ 1 : treg
,
5003 (int) BFD_RELOC_LO16
, AT
);
5004 expr1
.X_add_number
+= 4;
5006 /* Set mips_optimize to 2 to avoid inserting an undesired
5008 hold_mips_optimize
= mips_optimize
;
5010 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5011 coproc
? treg
: treg
+ 1,
5012 (int) BFD_RELOC_LO16
, AT
);
5013 mips_optimize
= hold_mips_optimize
;
5015 (void) frag_var (rs_machine_dependent
, 0, 0,
5016 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5017 offset_expr
.X_add_symbol
, (long) 0,
5020 else if (mips_pic
== SVR4_PIC
)
5024 /* If this is a reference to an external symbol, we want
5025 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5027 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5032 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5034 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5035 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5036 If there is a base register we add it to $at before the
5037 lwc1 instructions. If there is a constant we include it
5038 in the lwc1 instructions. */
5040 expr1
.X_add_number
= offset_expr
.X_add_number
;
5041 offset_expr
.X_add_number
= 0;
5042 if (expr1
.X_add_number
< -0x8000
5043 || expr1
.X_add_number
>= 0x8000 - 4)
5044 as_bad ("PIC code offset overflow (max 16 signed bits)");
5045 if (reg_needs_delay (GP
))
5054 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5055 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5056 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5057 mips_isa
< 3 ? "addu" : "daddu",
5058 "d,v,t", AT
, AT
, GP
);
5059 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5060 mips_isa
< 3 ? "lw" : "ld",
5061 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5062 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5064 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5065 mips_isa
< 3 ? "addu" : "daddu",
5066 "d,v,t", AT
, breg
, AT
);
5067 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5068 coproc
? treg
+ 1 : treg
,
5069 (int) BFD_RELOC_LO16
, AT
);
5070 expr1
.X_add_number
+= 4;
5072 /* Set mips_optimize to 2 to avoid inserting an undesired
5074 hold_mips_optimize
= mips_optimize
;
5076 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5077 coproc
? treg
: treg
+ 1,
5078 (int) BFD_RELOC_LO16
, AT
);
5079 mips_optimize
= hold_mips_optimize
;
5080 expr1
.X_add_number
-= 4;
5082 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5083 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5084 8 + gpdel
+ off
, 1, 0),
5085 offset_expr
.X_add_symbol
, (long) 0,
5089 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5092 macro_build (p
, &icnt
, &offset_expr
,
5093 mips_isa
< 3 ? "lw" : "ld",
5094 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5096 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5100 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5101 mips_isa
< 3 ? "addu" : "daddu",
5102 "d,v,t", AT
, breg
, AT
);
5105 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5106 coproc
? treg
+ 1 : treg
,
5107 (int) BFD_RELOC_LO16
, AT
);
5109 expr1
.X_add_number
+= 4;
5111 /* Set mips_optimize to 2 to avoid inserting an undesired
5113 hold_mips_optimize
= mips_optimize
;
5115 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5116 coproc
? treg
: treg
+ 1,
5117 (int) BFD_RELOC_LO16
, AT
);
5118 mips_optimize
= hold_mips_optimize
;
5120 else if (mips_pic
== EMBEDDED_PIC
)
5122 /* If there is no base register, we use
5123 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5124 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5125 If we have a base register, we use
5127 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5128 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5137 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5138 mips_isa
< 3 ? "addu" : "daddu",
5139 "d,v,t", AT
, breg
, GP
);
5144 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5145 coproc
? treg
+ 1 : treg
,
5146 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5147 offset_expr
.X_add_number
+= 4;
5148 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5149 coproc
? treg
: treg
+ 1,
5150 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5166 assert (mips_isa
< 3);
5167 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5168 (int) BFD_RELOC_LO16
, breg
);
5169 offset_expr
.X_add_number
+= 4;
5170 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5171 (int) BFD_RELOC_LO16
, breg
);
5173 #ifdef LOSING_COMPILER
5179 as_warn ("Macro used $at after \".set noat\"");
5184 struct mips_cl_insn
*ip
;
5186 register int treg
, sreg
, dreg
, breg
;
5201 bfd_reloc_code_real_type r
;
5204 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5205 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5206 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5207 mask
= ip
->insn_mo
->mask
;
5209 expr1
.X_op
= O_constant
;
5210 expr1
.X_op_symbol
= NULL
;
5211 expr1
.X_add_symbol
= NULL
;
5212 expr1
.X_add_number
= 1;
5216 #endif /* LOSING_COMPILER */
5221 macro_build ((char *) NULL
, &icnt
, NULL
,
5222 dbl
? "dmultu" : "multu",
5224 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5230 /* The MIPS assembler some times generates shifts and adds. I'm
5231 not trying to be that fancy. GCC should do this for us
5233 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5234 macro_build ((char *) NULL
, &icnt
, NULL
,
5235 dbl
? "dmult" : "mult",
5237 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5243 mips_emit_delays (true);
5245 mips_any_noreorder
= 1;
5246 macro_build ((char *) NULL
, &icnt
, NULL
,
5247 dbl
? "dmult" : "mult",
5249 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5250 macro_build ((char *) NULL
, &icnt
, NULL
,
5251 dbl
? "dsra32" : "sra",
5252 "d,w,<", dreg
, dreg
, 31);
5253 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5255 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
5258 expr1
.X_add_number
= 8;
5259 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
5260 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5261 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5264 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5270 mips_emit_delays (true);
5272 mips_any_noreorder
= 1;
5273 macro_build ((char *) NULL
, &icnt
, NULL
,
5274 dbl
? "dmultu" : "multu",
5276 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
5277 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5279 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
5282 expr1
.X_add_number
= 8;
5283 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
5284 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
5285 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
5291 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5292 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
5293 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
5295 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5299 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
5300 (int) (imm_expr
.X_add_number
& 0x1f));
5301 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
5302 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5303 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5307 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
5308 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
5309 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
5311 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5315 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
5316 (int) (imm_expr
.X_add_number
& 0x1f));
5317 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
5318 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
5319 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
5323 assert (mips_isa
< 2);
5324 /* Even on a big endian machine $fn comes before $fn+1. We have
5325 to adjust when storing to memory. */
5326 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5327 target_big_endian
? treg
+ 1 : treg
,
5328 (int) BFD_RELOC_LO16
, breg
);
5329 offset_expr
.X_add_number
+= 4;
5330 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
5331 target_big_endian
? treg
: treg
+ 1,
5332 (int) BFD_RELOC_LO16
, breg
);
5337 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5338 treg
, (int) BFD_RELOC_LO16
);
5340 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5341 sreg
, (int) BFD_RELOC_LO16
);
5344 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5346 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5347 dreg
, (int) BFD_RELOC_LO16
);
5352 if (imm_expr
.X_add_number
== 0)
5354 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
5355 sreg
, (int) BFD_RELOC_LO16
);
5360 as_warn ("Instruction %s: result is always false",
5362 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
5365 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5367 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
5368 sreg
, (int) BFD_RELOC_LO16
);
5371 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5373 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5374 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5375 mips_isa
< 3 ? "addiu" : "daddiu",
5376 "t,r,j", dreg
, sreg
,
5377 (int) BFD_RELOC_LO16
);
5382 load_register (&icnt
, AT
, &imm_expr
, 0);
5383 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5387 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
5388 (int) BFD_RELOC_LO16
);
5393 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
5399 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
5400 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5401 (int) BFD_RELOC_LO16
);
5404 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
5406 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5408 macro_build ((char *) NULL
, &icnt
, &expr1
,
5409 mask
== M_SGE_I
? "slti" : "sltiu",
5410 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5415 load_register (&icnt
, AT
, &imm_expr
, 0);
5416 macro_build ((char *) NULL
, &icnt
, NULL
,
5417 mask
== M_SGE_I
? "slt" : "sltu",
5418 "d,v,t", dreg
, sreg
, AT
);
5421 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5422 (int) BFD_RELOC_LO16
);
5427 case M_SGT
: /* sreg > treg <==> treg < sreg */
5433 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5436 case M_SGT_I
: /* sreg > I <==> I < sreg */
5442 load_register (&icnt
, AT
, &imm_expr
, 0);
5443 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5446 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
5452 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
5453 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5454 (int) BFD_RELOC_LO16
);
5457 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
5463 load_register (&icnt
, AT
, &imm_expr
, 0);
5464 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
5465 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
5466 (int) BFD_RELOC_LO16
);
5470 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5472 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
5473 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5476 load_register (&icnt
, AT
, &imm_expr
, 0);
5477 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
5481 if (imm_expr
.X_add_number
>= -0x8000 && imm_expr
.X_add_number
< 0x8000)
5483 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
5484 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5487 load_register (&icnt
, AT
, &imm_expr
, 0);
5488 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
5494 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5497 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5501 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5503 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5509 if (imm_expr
.X_add_number
== 0)
5511 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
5517 as_warn ("Instruction %s: result is always true",
5519 macro_build ((char *) NULL
, &icnt
, &expr1
,
5520 mips_isa
< 3 ? "addiu" : "daddiu",
5521 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
5524 if (imm_expr
.X_add_number
>= 0 && imm_expr
.X_add_number
< 0x10000)
5526 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
5527 dreg
, sreg
, (int) BFD_RELOC_LO16
);
5530 else if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
< 0)
5532 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5533 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5534 mips_isa
< 3 ? "addiu" : "daddiu",
5535 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5540 load_register (&icnt
, AT
, &imm_expr
, 0);
5541 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
5545 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
5553 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5555 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5556 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5557 dbl
? "daddi" : "addi",
5558 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5561 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5562 macro_build ((char *) NULL
, &icnt
, NULL
,
5563 dbl
? "dsub" : "sub",
5564 "d,v,t", dreg
, sreg
, AT
);
5570 if (imm_expr
.X_add_number
> -0x8000 && imm_expr
.X_add_number
<= 0x8000)
5572 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5573 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5574 dbl
? "daddiu" : "addiu",
5575 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
5578 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5579 macro_build ((char *) NULL
, &icnt
, NULL
,
5580 dbl
? "dsubu" : "subu",
5581 "d,v,t", dreg
, sreg
, AT
);
5602 load_register (&icnt
, AT
, &imm_expr
, 0);
5603 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
5608 assert (mips_isa
< 2);
5609 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
5610 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
5613 * Is the double cfc1 instruction a bug in the mips assembler;
5614 * or is there a reason for it?
5616 mips_emit_delays (true);
5618 mips_any_noreorder
= 1;
5619 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5620 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
5621 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5622 expr1
.X_add_number
= 3;
5623 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
5624 (int) BFD_RELOC_LO16
);
5625 expr1
.X_add_number
= 2;
5626 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
5627 (int) BFD_RELOC_LO16
);
5628 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
5629 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5630 macro_build ((char *) NULL
, &icnt
, NULL
,
5631 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
5632 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
5633 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
5643 if (offset_expr
.X_add_number
>= 0x7fff)
5644 as_bad ("operand overflow");
5645 /* avoid load delay */
5646 if (! target_big_endian
)
5647 offset_expr
.X_add_number
+= 1;
5648 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5649 (int) BFD_RELOC_LO16
, breg
);
5650 if (! target_big_endian
)
5651 offset_expr
.X_add_number
-= 1;
5653 offset_expr
.X_add_number
+= 1;
5654 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
5655 (int) BFD_RELOC_LO16
, breg
);
5656 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
5657 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
5670 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5671 as_bad ("operand overflow");
5672 if (! target_big_endian
)
5673 offset_expr
.X_add_number
+= off
;
5674 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5675 (int) BFD_RELOC_LO16
, breg
);
5676 if (! target_big_endian
)
5677 offset_expr
.X_add_number
-= off
;
5679 offset_expr
.X_add_number
+= off
;
5680 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5681 (int) BFD_RELOC_LO16
, breg
);
5694 load_address (&icnt
, AT
, &offset_expr
);
5696 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5697 mips_isa
< 3 ? "addu" : "daddu",
5698 "d,v,t", AT
, AT
, breg
);
5699 if (! target_big_endian
)
5700 expr1
.X_add_number
= off
;
5702 expr1
.X_add_number
= 0;
5703 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5704 (int) BFD_RELOC_LO16
, AT
);
5705 if (! target_big_endian
)
5706 expr1
.X_add_number
= 0;
5708 expr1
.X_add_number
= off
;
5709 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5710 (int) BFD_RELOC_LO16
, AT
);
5715 load_address (&icnt
, AT
, &offset_expr
);
5717 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5718 mips_isa
< 3 ? "addu" : "daddu",
5719 "d,v,t", AT
, AT
, breg
);
5720 if (target_big_endian
)
5721 expr1
.X_add_number
= 0;
5722 macro_build ((char *) NULL
, &icnt
, &expr1
,
5723 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
5724 (int) BFD_RELOC_LO16
, AT
);
5725 if (target_big_endian
)
5726 expr1
.X_add_number
= 1;
5728 expr1
.X_add_number
= 0;
5729 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5730 (int) BFD_RELOC_LO16
, AT
);
5731 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5733 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5738 if (offset_expr
.X_add_number
>= 0x7fff)
5739 as_bad ("operand overflow");
5740 if (target_big_endian
)
5741 offset_expr
.X_add_number
+= 1;
5742 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
5743 (int) BFD_RELOC_LO16
, breg
);
5744 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
5745 if (target_big_endian
)
5746 offset_expr
.X_add_number
-= 1;
5748 offset_expr
.X_add_number
+= 1;
5749 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
5750 (int) BFD_RELOC_LO16
, breg
);
5763 if (offset_expr
.X_add_number
>= 0x8000 - off
)
5764 as_bad ("operand overflow");
5765 if (! target_big_endian
)
5766 offset_expr
.X_add_number
+= off
;
5767 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5768 (int) BFD_RELOC_LO16
, breg
);
5769 if (! target_big_endian
)
5770 offset_expr
.X_add_number
-= off
;
5772 offset_expr
.X_add_number
+= off
;
5773 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
5774 (int) BFD_RELOC_LO16
, breg
);
5787 load_address (&icnt
, AT
, &offset_expr
);
5789 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5790 mips_isa
< 3 ? "addu" : "daddu",
5791 "d,v,t", AT
, AT
, breg
);
5792 if (! target_big_endian
)
5793 expr1
.X_add_number
= off
;
5795 expr1
.X_add_number
= 0;
5796 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
5797 (int) BFD_RELOC_LO16
, AT
);
5798 if (! target_big_endian
)
5799 expr1
.X_add_number
= 0;
5801 expr1
.X_add_number
= off
;
5802 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
5803 (int) BFD_RELOC_LO16
, AT
);
5807 load_address (&icnt
, AT
, &offset_expr
);
5809 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5810 mips_isa
< 3 ? "addu" : "daddu",
5811 "d,v,t", AT
, AT
, breg
);
5812 if (! target_big_endian
)
5813 expr1
.X_add_number
= 0;
5814 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5815 (int) BFD_RELOC_LO16
, AT
);
5816 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
5818 if (! target_big_endian
)
5819 expr1
.X_add_number
= 1;
5821 expr1
.X_add_number
= 0;
5822 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
5823 (int) BFD_RELOC_LO16
, AT
);
5824 if (! target_big_endian
)
5825 expr1
.X_add_number
= 0;
5827 expr1
.X_add_number
= 1;
5828 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
5829 (int) BFD_RELOC_LO16
, AT
);
5830 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
5832 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
5837 as_bad ("Macro %s not implemented yet", ip
->insn_mo
->name
);
5841 as_warn ("Macro used $at after \".set noat\"");
5844 /* Implement macros in mips16 mode. */
5848 struct mips_cl_insn
*ip
;
5851 int xreg
, yreg
, zreg
, tmp
;
5855 const char *s
, *s2
, *s3
;
5857 mask
= ip
->insn_mo
->mask
;
5859 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
5860 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
5861 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
5865 expr1
.X_op
= O_constant
;
5866 expr1
.X_op_symbol
= NULL
;
5867 expr1
.X_add_symbol
= NULL
;
5868 expr1
.X_add_number
= 1;
5887 mips_emit_delays (true);
5889 mips_any_noreorder
= 1;
5890 macro_build ((char *) NULL
, &icnt
, NULL
,
5891 dbl
? "ddiv" : "div",
5892 "0,x,y", xreg
, yreg
);
5893 expr1
.X_add_number
= 2;
5894 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5895 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5896 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
5897 since that causes an overflow. We should do that as well,
5898 but I don't see how to do the comparisons without a temporary
5901 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
5920 mips_emit_delays (true);
5922 mips_any_noreorder
= 1;
5923 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
5924 expr1
.X_add_number
= 2;
5925 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
5926 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
5928 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
5936 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5937 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
5938 dbl
? "daddiu" : "addiu",
5939 "y,x,4", yreg
, xreg
);
5943 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5944 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
5949 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
5950 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
5973 goto do_reverse_branch
;
5977 goto do_reverse_branch
;
5989 goto do_reverse_branch
;
6000 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6002 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6029 goto do_addone_branch_i
;
6034 goto do_addone_branch_i
;
6049 goto do_addone_branch_i
;
6056 ++imm_expr
.X_add_number
;
6059 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6060 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6064 expr1
.X_add_number
= 0;
6065 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6067 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6068 "move", "y,X", xreg
, yreg
);
6069 expr1
.X_add_number
= 2;
6070 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6071 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6072 "neg", "x,w", xreg
, xreg
);
6076 /* This routine assembles an instruction into its binary format. As a
6077 side effect, it sets one of the global variables imm_reloc or
6078 offset_reloc to the type of relocation to do if one of the operands
6079 is an address expression. */
6084 struct mips_cl_insn
*ip
;
6089 struct mips_opcode
*insn
;
6092 unsigned int lastregno
= 0;
6097 for (s
= str
; islower (*s
) || (*s
>= '0' && *s
<= '3') || *s
== '6' || *s
== '.'; ++s
)
6109 as_fatal ("Unknown opcode: `%s'", str
);
6111 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
6113 insn_error
= "unrecognized opcode";
6121 assert (strcmp (insn
->name
, str
) == 0);
6123 if (insn
->pinfo
== INSN_MACRO
)
6124 insn_isa
= insn
->match
;
6125 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA2
)
6127 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA3
)
6129 else if ((insn
->pinfo
& INSN_ISA
) == INSN_ISA4
)
6134 if (insn_isa
> mips_isa
6135 || ((insn
->pinfo
& INSN_ISA
) == INSN_4650
6137 || ((insn
->pinfo
& INSN_ISA
) == INSN_4010
6139 || ((insn
->pinfo
& INSN_ISA
) == INSN_4100
6141 /* start-sanitize-r5900 */
6142 || ((insn
->pinfo
& INSN_ISA
) == INSN_5900
6144 /* end-sanitize-r5900 */
6147 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
6148 && strcmp (insn
->name
, insn
[1].name
) == 0)
6153 if (insn_isa
<= mips_isa
)
6154 insn_error
= "opcode not supported on this processor";
6157 static char buf
[100];
6159 sprintf (buf
, "opcode requires -mips%d or greater", insn_isa
);
6166 ip
->insn_opcode
= insn
->match
;
6167 for (args
= insn
->args
;; ++args
)
6173 case '\0': /* end of args */
6186 ip
->insn_opcode
|= lastregno
<< 21;
6191 ip
->insn_opcode
|= lastregno
<< 16;
6195 ip
->insn_opcode
|= lastregno
<< 11;
6201 /* handle optional base register.
6202 Either the base register is omitted or
6203 we must have a left paren. */
6204 /* this is dependent on the next operand specifier
6205 is a 'b' for base register */
6206 assert (args
[1] == 'b');
6210 case ')': /* these must match exactly */
6215 case '<': /* must be at least one digit */
6217 * According to the manual, if the shift amount is greater
6218 * than 31 or less than 0 the the shift amount should be
6219 * mod 32. In reality the mips assembler issues an error.
6220 * We issue a warning and mask out all but the low 5 bits.
6222 my_getExpression (&imm_expr
, s
);
6223 check_absolute_expr (ip
, &imm_expr
);
6224 if ((unsigned long) imm_expr
.X_add_number
> 31)
6226 as_warn ("Improper shift amount (%ld)",
6227 (long) imm_expr
.X_add_number
);
6228 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
6230 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6231 imm_expr
.X_op
= O_absent
;
6235 case '>': /* shift amount minus 32 */
6236 my_getExpression (&imm_expr
, s
);
6237 check_absolute_expr (ip
, &imm_expr
);
6238 if ((unsigned long) imm_expr
.X_add_number
< 32
6239 || (unsigned long) imm_expr
.X_add_number
> 63)
6241 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
6242 imm_expr
.X_op
= O_absent
;
6246 case 'k': /* cache code */
6247 case 'h': /* prefx code */
6248 my_getExpression (&imm_expr
, s
);
6249 check_absolute_expr (ip
, &imm_expr
);
6250 if ((unsigned long) imm_expr
.X_add_number
> 31)
6252 as_warn ("Invalid value for `%s' (%lu)",
6254 (unsigned long) imm_expr
.X_add_number
);
6255 imm_expr
.X_add_number
&= 0x1f;
6258 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
6260 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
6261 imm_expr
.X_op
= O_absent
;
6265 case 'c': /* break code */
6266 my_getExpression (&imm_expr
, s
);
6267 check_absolute_expr (ip
, &imm_expr
);
6268 if ((unsigned) imm_expr
.X_add_number
> 1023)
6269 as_warn ("Illegal break code (%ld)",
6270 (long) imm_expr
.X_add_number
);
6271 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
6272 imm_expr
.X_op
= O_absent
;
6276 case 'B': /* syscall code */
6277 my_getExpression (&imm_expr
, s
);
6278 check_absolute_expr (ip
, &imm_expr
);
6279 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
6280 as_warn ("Illegal syscall code (%ld)",
6281 (long) imm_expr
.X_add_number
);
6282 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
6283 imm_expr
.X_op
= O_absent
;
6287 case 'C': /* Coprocessor code */
6288 my_getExpression (&imm_expr
, s
);
6289 check_absolute_expr (ip
, &imm_expr
);
6290 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
6292 as_warn ("Coproccesor code > 25 bits (%ld)",
6293 (long) imm_expr
.X_add_number
);
6294 imm_expr
.X_add_number
&= ((1<<25) - 1);
6296 ip
->insn_opcode
|= imm_expr
.X_add_number
;
6297 imm_expr
.X_op
= O_absent
;
6301 case 'b': /* base register */
6302 case 'd': /* destination register */
6303 case 's': /* source register */
6304 case 't': /* target register */
6305 case 'r': /* both target and source */
6306 case 'v': /* both dest and source */
6307 case 'w': /* both dest and target */
6308 case 'E': /* coprocessor target register */
6309 case 'G': /* coprocessor destination register */
6310 case 'x': /* ignore register name */
6311 case 'z': /* must be zero register */
6325 while (isdigit (*s
));
6327 as_bad ("Invalid register number (%d)", regno
);
6329 else if (*args
== 'E' || *args
== 'G')
6333 if (s
[1] == 'f' && s
[2] == 'p')
6338 else if (s
[1] == 's' && s
[2] == 'p')
6343 else if (s
[1] == 'g' && s
[2] == 'p')
6348 else if (s
[1] == 'a' && s
[2] == 't')
6353 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
6358 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
6370 as_warn ("Used $at without \".set noat\"");
6376 if (c
== 'r' || c
== 'v' || c
== 'w')
6383 /* 'z' only matches $0. */
6384 if (c
== 'z' && regno
!= 0)
6392 ip
->insn_opcode
|= regno
<< 21;
6396 ip
->insn_opcode
|= regno
<< 11;
6401 ip
->insn_opcode
|= regno
<< 16;
6404 /* This case exists because on the r3000 trunc
6405 expands into a macro which requires a gp
6406 register. On the r6000 or r4000 it is
6407 assembled into a single instruction which
6408 ignores the register. Thus the insn version
6409 is MIPS_ISA2 and uses 'x', and the macro
6410 version is MIPS_ISA1 and uses 't'. */
6413 /* This case is for the div instruction, which
6414 acts differently if the destination argument
6415 is $0. This only matches $0, and is checked
6416 outside the switch. */
6427 ip
->insn_opcode
|= lastregno
<< 21;
6430 ip
->insn_opcode
|= lastregno
<< 16;
6435 case 'D': /* floating point destination register */
6436 case 'S': /* floating point source register */
6437 case 'T': /* floating point target register */
6438 case 'R': /* floating point source register */
6442 if (s
[0] == '$' && s
[1] == 'f' && isdigit (s
[2]))
6452 while (isdigit (*s
));
6455 as_bad ("Invalid float register number (%d)", regno
);
6457 if ((regno
& 1) != 0
6459 && ! (strcmp (str
, "mtc1") == 0
6460 || strcmp (str
, "mfc1") == 0
6461 || strcmp (str
, "lwc1") == 0
6462 || strcmp (str
, "swc1") == 0
6463 || strcmp (str
, "l.s") == 0
6464 || strcmp (str
, "s.s") == 0))
6465 as_warn ("Float register should be even, was %d",
6473 if (c
== 'V' || c
== 'W')
6483 ip
->insn_opcode
|= regno
<< 6;
6487 ip
->insn_opcode
|= regno
<< 11;
6491 ip
->insn_opcode
|= regno
<< 16;
6494 ip
->insn_opcode
|= regno
<< 21;
6503 ip
->insn_opcode
|= lastregno
<< 11;
6506 ip
->insn_opcode
|= lastregno
<< 16;
6512 my_getExpression (&imm_expr
, s
);
6513 if (imm_expr
.X_op
!= O_big
6514 && imm_expr
.X_op
!= O_constant
)
6515 insn_error
= "absolute expression required";
6520 my_getExpression (&offset_expr
, s
);
6521 imm_reloc
= BFD_RELOC_32
;
6533 unsigned char temp
[8];
6535 unsigned int length
;
6540 /* These only appear as the last operand in an
6541 instruction, and every instruction that accepts
6542 them in any variant accepts them in all variants.
6543 This means we don't have to worry about backing out
6544 any changes if the instruction does not match.
6546 The difference between them is the size of the
6547 floating point constant and where it goes. For 'F'
6548 and 'L' the constant is 64 bits; for 'f' and 'l' it
6549 is 32 bits. Where the constant is placed is based
6550 on how the MIPS assembler does things:
6553 f -- immediate value
6556 The .lit4 and .lit8 sections are only used if
6557 permitted by the -G argument.
6559 When generating embedded PIC code, we use the
6560 .lit8 section but not the .lit4 section (we can do
6561 .lit4 inline easily; we need to put .lit8
6562 somewhere in the data segment, and using .lit8
6563 permits the linker to eventually combine identical
6566 f64
= *args
== 'F' || *args
== 'L';
6568 save_in
= input_line_pointer
;
6569 input_line_pointer
= s
;
6570 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
6572 s
= input_line_pointer
;
6573 input_line_pointer
= save_in
;
6574 if (err
!= NULL
&& *err
!= '\0')
6576 as_bad ("Bad floating point constant: %s", err
);
6577 memset (temp
, '\0', sizeof temp
);
6578 length
= f64
? 8 : 4;
6581 assert (length
== (f64
? 8 : 4));
6585 && (! USE_GLOBAL_POINTER_OPT
6586 || mips_pic
== EMBEDDED_PIC
6587 || g_switch_value
< 4)
6590 imm_expr
.X_op
= O_constant
;
6591 if (! target_big_endian
)
6592 imm_expr
.X_add_number
=
6593 (((((((int) temp
[3] << 8)
6598 imm_expr
.X_add_number
=
6599 (((((((int) temp
[0] << 8)
6606 const char *newname
;
6609 /* Switch to the right section. */
6611 subseg
= now_subseg
;
6614 default: /* unused default case avoids warnings. */
6616 newname
= RDATA_SECTION_NAME
;
6617 if (USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
6621 newname
= RDATA_SECTION_NAME
;
6624 assert (!USE_GLOBAL_POINTER_OPT
6625 || g_switch_value
>= 4);
6629 new_seg
= subseg_new (newname
, (subsegT
) 0);
6630 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6631 bfd_set_section_flags (stdoutput
, new_seg
,
6636 frag_align (*args
== 'l' ? 2 : 3, 0);
6637 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
6638 record_alignment (new_seg
, 4);
6640 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
6642 as_bad ("Can't use floating point insn in this section");
6644 /* Set the argument to the current address in the
6646 offset_expr
.X_op
= O_symbol
;
6647 offset_expr
.X_add_symbol
=
6648 symbol_new ("L0\001", now_seg
,
6649 (valueT
) frag_now_fix (), frag_now
);
6650 offset_expr
.X_add_number
= 0;
6652 /* Put the floating point number into the section. */
6653 p
= frag_more ((int) length
);
6654 memcpy (p
, temp
, length
);
6656 /* Switch back to the original section. */
6657 subseg_set (seg
, subseg
);
6662 case 'i': /* 16 bit unsigned immediate */
6663 case 'j': /* 16 bit signed immediate */
6664 imm_reloc
= BFD_RELOC_LO16
;
6665 c
= my_getSmallExpression (&imm_expr
, s
);
6670 if (imm_expr
.X_op
== O_constant
)
6671 imm_expr
.X_add_number
=
6672 (imm_expr
.X_add_number
>> 16) & 0xffff;
6675 imm_reloc
= BFD_RELOC_HI16_S
;
6676 imm_unmatched_hi
= true;
6679 imm_reloc
= BFD_RELOC_HI16
;
6684 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6685 || ((imm_expr
.X_add_number
< 0
6686 || imm_expr
.X_add_number
>= 0x10000)
6687 && imm_expr
.X_op
== O_constant
))
6689 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6690 !strcmp (insn
->name
, insn
[1].name
))
6692 if (imm_expr
.X_op
!= O_constant
6693 && imm_expr
.X_op
!= O_big
)
6694 insn_error
= "absolute expression required";
6696 as_bad ("16 bit expression not in range 0..65535");
6704 /* The upper bound should be 0x8000, but
6705 unfortunately the MIPS assembler accepts numbers
6706 from 0x8000 to 0xffff and sign extends them, and
6707 we want to be compatible. We only permit this
6708 extended range for an instruction which does not
6709 provide any further alternates, since those
6710 alternates may handle other cases. People should
6711 use the numbers they mean, rather than relying on
6712 a mysterious sign extension. */
6713 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6714 strcmp (insn
->name
, insn
[1].name
) == 0);
6719 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
6720 || ((imm_expr
.X_add_number
< -0x8000
6721 || imm_expr
.X_add_number
>= max
)
6722 && imm_expr
.X_op
== O_constant
)
6724 && imm_expr
.X_add_number
< 0
6726 && imm_expr
.X_unsigned
6727 && sizeof (imm_expr
.X_add_number
) <= 4))
6731 if (imm_expr
.X_op
!= O_constant
6732 && imm_expr
.X_op
!= O_big
)
6733 insn_error
= "absolute expression required";
6735 as_bad ("16 bit expression not in range -32768..32767");
6741 case 'o': /* 16 bit offset */
6742 c
= my_getSmallExpression (&offset_expr
, s
);
6744 /* If this value won't fit into a 16 bit offset, then go
6745 find a macro that will generate the 32 bit offset
6746 code pattern. As a special hack, we accept the
6747 difference of two local symbols as a constant. This
6748 is required to suppose embedded PIC switches, which
6749 use an instruction which looks like
6750 lw $4,$L12-$LS12($4)
6751 The problem with handling this in a more general
6752 fashion is that the macro function doesn't expect to
6753 see anything which can be handled in a single
6754 constant instruction. */
6756 && (offset_expr
.X_op
!= O_constant
6757 || offset_expr
.X_add_number
>= 0x8000
6758 || offset_expr
.X_add_number
< -0x8000)
6759 && (mips_pic
!= EMBEDDED_PIC
6760 || offset_expr
.X_op
!= O_subtract
6761 || now_seg
!= text_section
6762 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
6766 offset_reloc
= BFD_RELOC_LO16
;
6767 if (c
== 'h' || c
== 'H')
6769 assert (offset_expr
.X_op
== O_constant
);
6770 offset_expr
.X_add_number
=
6771 (offset_expr
.X_add_number
>> 16) & 0xffff;
6776 case 'p': /* pc relative offset */
6777 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
6778 my_getExpression (&offset_expr
, s
);
6782 case 'u': /* upper 16 bits */
6783 c
= my_getSmallExpression (&imm_expr
, s
);
6784 if (imm_expr
.X_op
== O_constant
6785 && (imm_expr
.X_add_number
< 0
6786 || imm_expr
.X_add_number
>= 0x10000))
6787 as_bad ("lui expression not in range 0..65535");
6788 imm_reloc
= BFD_RELOC_LO16
;
6793 if (imm_expr
.X_op
== O_constant
)
6794 imm_expr
.X_add_number
=
6795 (imm_expr
.X_add_number
>> 16) & 0xffff;
6798 imm_reloc
= BFD_RELOC_HI16_S
;
6799 imm_unmatched_hi
= true;
6802 imm_reloc
= BFD_RELOC_HI16
;
6808 case 'a': /* 26 bit address */
6809 my_getExpression (&offset_expr
, s
);
6811 offset_reloc
= BFD_RELOC_MIPS_JMP
;
6814 case 'N': /* 3 bit branch condition code */
6815 case 'M': /* 3 bit compare condition code */
6816 if (strncmp (s
, "$fcc", 4) != 0)
6826 while (isdigit (*s
));
6828 as_bad ("invalid condition code register $fcc%d", regno
);
6830 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
6832 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
6836 fprintf (stderr
, "bad char = '%c'\n", *args
);
6841 /* Args don't match. */
6842 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
6843 !strcmp (insn
->name
, insn
[1].name
))
6849 insn_error
= "illegal operands";
6854 /* This routine assembles an instruction into its binary format when
6855 assembling for the mips16. As a side effect, it sets one of the
6856 global variables imm_reloc or offset_reloc to the type of
6857 relocation to do if one of the operands is an address expression.
6858 It also sets mips16_small and mips16_ext if the user explicitly
6859 requested a small or extended instruction. */
6864 struct mips_cl_insn
*ip
;
6868 struct mips_opcode
*insn
;
6871 unsigned int lastregno
= 0;
6876 mips16_small
= false;
6879 for (s
= str
; islower (*s
); ++s
)
6891 if (s
[1] == 't' && s
[2] == ' ')
6894 mips16_small
= true;
6898 else if (s
[1] == 'e' && s
[2] == ' ')
6907 insn_error
= "unknown opcode";
6911 if (! mips16_autoextend
&& ! mips16_ext
)
6912 mips16_small
= true;
6914 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
6916 insn_error
= "unrecognized opcode";
6923 assert (strcmp (insn
->name
, str
) == 0);
6926 ip
->insn_opcode
= insn
->match
;
6927 ip
->use_extend
= false;
6928 imm_expr
.X_op
= O_absent
;
6929 imm_reloc
= BFD_RELOC_UNUSED
;
6930 offset_expr
.X_op
= O_absent
;
6931 offset_reloc
= BFD_RELOC_UNUSED
;
6932 for (args
= insn
->args
; 1; ++args
)
6939 /* In this switch statement we call break if we did not find
6940 a match, continue if we did find a match, or return if we
6949 /* Stuff the immediate value in now, if we can. */
6950 if (imm_expr
.X_op
== O_constant
6951 && imm_reloc
> BFD_RELOC_UNUSED
6952 && insn
->pinfo
!= INSN_MACRO
)
6954 mips16_immed ((char *) NULL
, 0,
6955 imm_reloc
- BFD_RELOC_UNUSED
,
6956 imm_expr
.X_add_number
, true, mips16_small
,
6957 mips16_ext
, &ip
->insn_opcode
,
6958 &ip
->use_extend
, &ip
->extend
);
6959 imm_expr
.X_op
= O_absent
;
6960 imm_reloc
= BFD_RELOC_UNUSED
;
6974 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6977 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
6993 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
6995 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
7022 while (isdigit (*s
));
7025 as_bad ("invalid register number (%d)", regno
);
7031 if (s
[1] == 'f' && s
[2] == 'p')
7036 else if (s
[1] == 's' && s
[2] == 'p')
7041 else if (s
[1] == 'g' && s
[2] == 'p')
7046 else if (s
[1] == 'a' && s
[2] == 't')
7051 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7056 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7069 if (c
== 'v' || c
== 'w')
7071 regno
= mips16_to_32_reg_map
[lastregno
];
7085 regno
= mips32_to_16_reg_map
[regno
];
7090 regno
= ILLEGAL_REG
;
7095 regno
= ILLEGAL_REG
;
7100 regno
= ILLEGAL_REG
;
7105 if (regno
== AT
&& ! mips_noat
)
7106 as_warn ("used $at without \".set noat\"");
7113 if (regno
== ILLEGAL_REG
)
7120 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
7124 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
7127 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
7130 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
7136 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
7139 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
7140 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
7150 if (strncmp (s
, "$pc", 3) == 0)
7173 if (s
[0] == '$' && isdigit (s
[1]))
7175 /* Looks like a register name. */
7183 /* It looks like the expression was omitted before a
7184 register indirection, which means that the
7185 expression is implicitly zero. We still set up
7186 imm_expr, so that we handle explicit extensions
7188 imm_expr
.X_op
= O_constant
;
7189 imm_expr
.X_add_number
= 0;
7190 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7194 my_getExpression (&imm_expr
, s
);
7195 /* We need to relax this instruction. */
7196 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7205 /* We use offset_reloc rather than imm_reloc for the PC
7206 relative operands. This lets macros with both
7207 immediate and address operands work correctly. */
7208 if (s
[0] == '$' && isdigit (s
[1]))
7210 /* Looks like a register name. */
7213 my_getExpression (&offset_expr
, s
);
7214 /* We need to relax this instruction. */
7215 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
7219 case '6': /* break code */
7220 my_getExpression (&imm_expr
, s
);
7221 check_absolute_expr (ip
, &imm_expr
);
7222 if ((unsigned long) imm_expr
.X_add_number
> 63)
7224 as_warn ("Invalid value for `%s' (%lu)",
7226 (unsigned long) imm_expr
.X_add_number
);
7227 imm_expr
.X_add_number
&= 0x3f;
7229 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
7230 imm_expr
.X_op
= O_absent
;
7234 case 'a': /* 26 bit address */
7235 my_getExpression (&offset_expr
, s
);
7237 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
7238 ip
->insn_opcode
<<= 16;
7241 case 'l': /* register list for entry macro */
7242 case 'L': /* register list for exit macro */
7252 int freg
, reg1
, reg2
;
7254 while (*s
== ' ' || *s
== ',')
7258 as_bad ("can't parse register list");
7270 while (isdigit (*s
))
7292 as_bad ("invalid register list");
7297 while (isdigit (*s
))
7304 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
7309 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
7314 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
7315 mask
|= (reg2
- 3) << 3;
7316 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
7317 mask
|= (reg2
- 15) << 1;
7318 else if (reg1
== 31 && reg2
== 31)
7322 as_bad ("invalid register list");
7326 /* The mask is filled in in the opcode table for the
7327 benefit of the disassembler. We remove it before
7328 applying the actual mask. */
7329 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
7330 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
7340 /* Args don't match. */
7341 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
7342 strcmp (insn
->name
, insn
[1].name
) == 0)
7349 insn_error
= "illegal operands";
7355 /* This structure holds information we know about a mips16 immediate
7358 struct mips16_immed_operand
7360 /* The type code used in the argument string in the opcode table. */
7362 /* The number of bits in the short form of the opcode. */
7364 /* The number of bits in the extended form of the opcode. */
7366 /* The amount by which the short form is shifted when it is used;
7367 for example, the sw instruction has a shift count of 2. */
7369 /* The amount by which the short form is shifted when it is stored
7370 into the instruction code. */
7372 /* Non-zero if the short form is unsigned. */
7374 /* Non-zero if the extended form is unsigned. */
7376 /* Non-zero if the value is PC relative. */
7380 /* The mips16 immediate operand types. */
7382 static const struct mips16_immed_operand mips16_immed_operands
[] =
7384 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7385 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7386 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
7387 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
7388 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
7389 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7390 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7391 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7392 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
7393 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
7394 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7395 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7396 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
7397 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
7398 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7399 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
7400 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7401 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
7402 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
7403 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
7404 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
7407 #define MIPS16_NUM_IMMED \
7408 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
7410 /* Handle a mips16 instruction with an immediate value. This or's the
7411 small immediate value into *INSN. It sets *USE_EXTEND to indicate
7412 whether an extended value is needed; if one is needed, it sets
7413 *EXTEND to the value. The argument type is TYPE. The value is VAL.
7414 If SMALL is true, an unextended opcode was explicitly requested.
7415 If EXT is true, an extended opcode was explicitly requested. If
7416 WARN is true, warn if EXT does not match reality. */
7419 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
7428 unsigned long *insn
;
7429 boolean
*use_extend
;
7430 unsigned short *extend
;
7432 register const struct mips16_immed_operand
*op
;
7433 int mintiny
, maxtiny
;
7436 op
= mips16_immed_operands
;
7437 while (op
->type
!= type
)
7440 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
7445 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
7448 maxtiny
= 1 << op
->nbits
;
7453 maxtiny
= (1 << op
->nbits
) - 1;
7458 mintiny
= - (1 << (op
->nbits
- 1));
7459 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
7462 /* Branch offsets have an implicit 0 in the lowest bit. */
7463 if (type
== 'p' || type
== 'q')
7466 if ((val
& ((1 << op
->shift
) - 1)) != 0
7467 || val
< (mintiny
<< op
->shift
)
7468 || val
> (maxtiny
<< op
->shift
))
7473 if (warn
&& ext
&& ! needext
)
7474 as_warn_where (file
, line
, "extended operand requested but not required");
7475 if (small
&& needext
)
7476 as_bad_where (file
, line
, "invalid unextended operand value");
7478 if (small
|| (! ext
&& ! needext
))
7482 *use_extend
= false;
7483 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
7484 insnval
<<= op
->op_shift
;
7489 long minext
, maxext
;
7495 maxext
= (1 << op
->extbits
) - 1;
7499 minext
= - (1 << (op
->extbits
- 1));
7500 maxext
= (1 << (op
->extbits
- 1)) - 1;
7502 if (val
< minext
|| val
> maxext
)
7503 as_bad_where (file
, line
,
7504 "operand value out of range for instruction");
7507 if (op
->extbits
== 16)
7509 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
7512 else if (op
->extbits
== 15)
7514 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
7519 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
7523 *extend
= (unsigned short) extval
;
7532 my_getSmallExpression (ep
, str
)
7543 ((str
[1] == 'h' && str
[2] == 'i')
7544 || (str
[1] == 'H' && str
[2] == 'I')
7545 || (str
[1] == 'l' && str
[2] == 'o'))
7557 * A small expression may be followed by a base register.
7558 * Scan to the end of this operand, and then back over a possible
7559 * base register. Then scan the small expression up to that
7560 * point. (Based on code in sparc.c...)
7562 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
7564 if (sp
- 4 >= str
&& sp
[-1] == RP
)
7566 if (isdigit (sp
[-2]))
7568 for (sp
-= 3; sp
>= str
&& isdigit (*sp
); sp
--)
7570 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
7576 else if (sp
- 5 >= str
7579 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
7580 || (sp
[-3] == 's' && sp
[-2] == 'p')
7581 || (sp
[-3] == 'g' && sp
[-2] == 'p')
7582 || (sp
[-3] == 'a' && sp
[-2] == 't')))
7588 /* no expression means zero offset */
7591 /* %xx(reg) is an error */
7592 ep
->X_op
= O_absent
;
7597 ep
->X_op
= O_constant
;
7600 ep
->X_add_symbol
= NULL
;
7601 ep
->X_op_symbol
= NULL
;
7602 ep
->X_add_number
= 0;
7607 my_getExpression (ep
, str
);
7614 my_getExpression (ep
, str
);
7615 return c
; /* => %hi or %lo encountered */
7619 my_getExpression (ep
, str
)
7625 save_in
= input_line_pointer
;
7626 input_line_pointer
= str
;
7628 expr_end
= input_line_pointer
;
7629 input_line_pointer
= save_in
;
7632 /* Turn a string in input_line_pointer into a floating point constant
7633 of type type, and store the appropriate bytes in *litP. The number
7634 of LITTLENUMS emitted is stored in *sizeP . An error message is
7635 returned, or NULL on OK. */
7638 md_atof (type
, litP
, sizeP
)
7644 LITTLENUM_TYPE words
[4];
7660 return "bad call to md_atof";
7663 t
= atof_ieee (input_line_pointer
, type
, words
);
7665 input_line_pointer
= t
;
7669 if (! target_big_endian
)
7671 for (i
= prec
- 1; i
>= 0; i
--)
7673 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7679 for (i
= 0; i
< prec
; i
++)
7681 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
7690 md_number_to_chars (buf
, val
, n
)
7695 if (target_big_endian
)
7696 number_to_chars_bigendian (buf
, val
, n
);
7698 number_to_chars_littleendian (buf
, val
, n
);
7701 CONST
char *md_shortopts
= "O::g::G:";
7703 struct option md_longopts
[] = {
7704 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
7705 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
7706 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
7707 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
7708 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
7709 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
7710 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
7711 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
7712 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
7713 #define OPTION_MCPU (OPTION_MD_BASE + 5)
7714 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
7715 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
7716 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
7717 #define OPTION_TRAP (OPTION_MD_BASE + 9)
7718 {"trap", no_argument
, NULL
, OPTION_TRAP
},
7719 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
7720 #define OPTION_BREAK (OPTION_MD_BASE + 10)
7721 {"break", no_argument
, NULL
, OPTION_BREAK
},
7722 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
7723 #define OPTION_EB (OPTION_MD_BASE + 11)
7724 {"EB", no_argument
, NULL
, OPTION_EB
},
7725 #define OPTION_EL (OPTION_MD_BASE + 12)
7726 {"EL", no_argument
, NULL
, OPTION_EL
},
7727 #define OPTION_M4650 (OPTION_MD_BASE + 13)
7728 {"m4650", no_argument
, NULL
, OPTION_M4650
},
7729 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
7730 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
7731 #define OPTION_M4010 (OPTION_MD_BASE + 15)
7732 {"m4010", no_argument
, NULL
, OPTION_M4010
},
7733 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
7734 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
7735 #define OPTION_M4100 (OPTION_MD_BASE + 17)
7736 {"m4100", no_argument
, NULL
, OPTION_M4100
},
7737 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
7738 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
7739 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
7740 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
7741 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
7742 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
7743 /* start-sanitize-5900 */
7744 #define OPTION_M5900 (OPTION_MD_BASE + 24)
7745 {"m5900", no_argument
, NULL
, OPTION_M5900
},
7746 #define OPTION_NO_M5900 (OPTION_MD_BASE + 25)
7747 {"no-m5900", no_argument
, NULL
, OPTION_NO_M5900
},
7748 /* end-sanitize-5900 */
7750 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
7751 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
7752 #define OPTION_XGOT (OPTION_MD_BASE + 19)
7753 #define OPTION_32 (OPTION_MD_BASE + 20)
7754 #define OPTION_64 (OPTION_MD_BASE + 21)
7756 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
7757 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
7758 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
7759 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
7760 {"32", no_argument
, NULL
, OPTION_32
},
7761 {"64", no_argument
, NULL
, OPTION_64
},
7764 {NULL
, no_argument
, NULL
, 0}
7766 size_t md_longopts_size
= sizeof(md_longopts
);
7769 md_parse_option (c
, arg
)
7784 target_big_endian
= 1;
7788 target_big_endian
= 0;
7792 if (arg
&& arg
[1] == '0')
7802 mips_debug
= atoi (arg
);
7803 /* When the MIPS assembler sees -g or -g2, it does not do
7804 optimizations which limit full symbolic debugging. We take
7805 that to be equivalent to -O0. */
7806 if (mips_debug
== 2)
7838 /* Identify the processor type */
7840 if (strcmp (p
, "default") == 0
7841 || strcmp (p
, "DEFAULT") == 0)
7847 /* We need to cope with the various "vr" prefixes for the 4300
7849 if (*p
== 'v' || *p
== 'V')
7855 if (*p
== 'r' || *p
== 'R')
7862 if (strcmp (p
, "10000") == 0
7863 || strcmp (p
, "10k") == 0
7864 || strcmp (p
, "10K") == 0)
7869 if (strcmp (p
, "2000") == 0
7870 || strcmp (p
, "2k") == 0
7871 || strcmp (p
, "2K") == 0)
7876 if (strcmp (p
, "3000") == 0
7877 || strcmp (p
, "3k") == 0
7878 || strcmp (p
, "3K") == 0)
7883 if (strcmp (p
, "4000") == 0
7884 || strcmp (p
, "4k") == 0
7885 || strcmp (p
, "4K") == 0)
7887 else if (strcmp (p
, "4100") == 0)
7893 else if (strcmp (p
, "4300") == 0)
7895 else if (strcmp (p
, "4400") == 0)
7897 else if (strcmp (p
, "4600") == 0)
7899 else if (strcmp (p
, "4650") == 0)
7905 else if (strcmp (p
, "4010") == 0)
7914 if (strcmp (p
, "5000") == 0
7915 || strcmp (p
, "5k") == 0
7916 || strcmp (p
, "5K") == 0)
7918 /* start-sanitize-r5900 */
7919 else if (strcmp (p
, "5900") == 0)
7921 /* end-sanitize-r5900 */
7925 if (strcmp (p
, "6000") == 0
7926 || strcmp (p
, "6k") == 0
7927 || strcmp (p
, "6K") == 0)
7932 if (strcmp (p
, "8000") == 0
7933 || strcmp (p
, "8k") == 0
7934 || strcmp (p
, "8K") == 0)
7939 if (strcmp (p
, "orion") == 0)
7944 if (sv
&& mips_cpu
!= 4300 && mips_cpu
!= 4100 && mips_cpu
!= 5000)
7946 as_bad ("ignoring invalid leading 'v' in -mcpu=%s switch", arg
);
7952 as_bad ("invalid architecture -mcpu=%s", arg
);
7963 case OPTION_NO_M4650
:
7971 case OPTION_NO_M4010
:
7979 case OPTION_NO_M4100
:
7983 /* start-sanitize-r5900 */
7988 case OPTION_NO_M5900
:
7991 /* end-sanitize-r5900 */
7995 mips_no_prev_insn ();
7998 case OPTION_NO_MIPS16
:
8000 mips_no_prev_insn ();
8003 case OPTION_MEMBEDDED_PIC
:
8004 mips_pic
= EMBEDDED_PIC
;
8005 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
8007 as_bad ("-G may not be used with embedded PIC code");
8010 g_switch_value
= 0x7fffffff;
8013 /* When generating ELF code, we permit -KPIC and -call_shared to
8014 select SVR4_PIC, and -non_shared to select no PIC. This is
8015 intended to be compatible with Irix 5. */
8016 case OPTION_CALL_SHARED
:
8017 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8019 as_bad ("-call_shared is supported only for ELF format");
8022 mips_pic
= SVR4_PIC
;
8023 if (g_switch_seen
&& g_switch_value
!= 0)
8025 as_bad ("-G may not be used with SVR4 PIC code");
8031 case OPTION_NON_SHARED
:
8032 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
8034 as_bad ("-non_shared is supported only for ELF format");
8040 /* The -xgot option tells the assembler to use 32 offsets when
8041 accessing the got in SVR4_PIC mode. It is for Irix
8048 if (! USE_GLOBAL_POINTER_OPT
)
8050 as_bad ("-G is not supported for this configuration");
8053 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
8055 as_bad ("-G may not be used with SVR4 or embedded PIC code");
8059 g_switch_value
= atoi (arg
);
8063 /* The -32 and -64 options tell the assembler to output the 32
8064 bit or the 64 bit MIPS ELF format. */
8071 const char **list
, **l
;
8073 list
= bfd_target_list ();
8074 for (l
= list
; *l
!= NULL
; l
++)
8075 if (strcmp (*l
, "elf64-bigmips") == 0
8076 || strcmp (*l
, "elf64-littlemips") == 0)
8079 as_fatal ("No compiled in support for 64 bit object file format");
8093 md_show_usage (stream
)
8098 -membedded-pic generate embedded position independent code\n\
8099 -EB generate big endian output\n\
8100 -EL generate little endian output\n\
8101 -g, -g2 do not remove uneeded NOPs or swap branches\n\
8102 -G NUM allow referencing objects up to NUM bytes\n\
8103 implicitly with the gp register [default 8]\n");
8105 -mips1, -mcpu=r{2,3}000 generate code for r2000 and r3000\n\
8106 -mips2, -mcpu=r6000 generate code for r6000\n\
8107 -mips3, -mcpu=r4000 generate code for r4000\n\
8108 -mips4, -mcpu=r8000 generate code for r8000\n\
8109 -mcpu=vr4300 generate code for vr4300\n\
8110 -mcpu=vr4100 generate code for vr4100\n\
8111 -m4650 permit R4650 instructions\n\
8112 -no-m4650 do not permit R4650 instructions\n\
8113 -m4010 permit R4010 instructions\n\
8114 -no-m4010 do not permit R4010 instructions\n\
8115 -m4100 permit VR4100 instructions\n\
8116 -no-m4100 do not permit VR4100 instructions\n");
8118 -mips16 generate mips16 instructions\n\
8119 -no-mips16 do not generate mips16 instructions\n");
8121 -O0 remove unneeded NOPs, do not swap branches\n\
8122 -O remove unneeded NOPs and swap branches\n\
8123 --trap, --no-break trap exception on div by 0 and mult overflow\n\
8124 --break, --no-trap break exception on div by 0 and mult overflow\n");
8127 -KPIC, -call_shared generate SVR4 position independent code\n\
8128 -non_shared do not generate position independent code\n\
8129 -xgot assume a 32 bit GOT\n\
8130 -32 create 32 bit object file (default)\n\
8131 -64 create 64 bit object file\n");
8136 md_pcrel_from (fixP
)
8139 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
8140 && fixP
->fx_addsy
!= (symbolS
*) NULL
8141 && ! S_IS_DEFINED (fixP
->fx_addsy
))
8143 /* This makes a branch to an undefined symbol be a branch to the
8144 current location. */
8148 /* return the address of the delay slot */
8149 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8152 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
8153 reloc for a cons. We could use the definition there, except that
8154 we want to handle 64 bit relocs specially. */
8157 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
8160 unsigned int nbytes
;
8164 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
8166 if (nbytes
== 8 && ! mips_64
)
8168 if (target_big_endian
)
8174 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
8175 as_bad ("Unsupported reloc size %d", nbytes
);
8177 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
8180 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
8183 /* Sort any unmatched HI16_S relocs so that they immediately precede
8184 the corresponding LO reloc. This is called before md_apply_fix and
8185 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
8186 explicit use of the %hi modifier. */
8191 struct mips_hi_fixup
*l
;
8193 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
8195 segment_info_type
*seginfo
;
8198 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
8200 /* Check quickly whether the next fixup happens to be a matching
8202 if (l
->fixp
->fx_next
!= NULL
8203 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
8204 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
8205 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
8208 /* Look through the fixups for this segment for a matching %lo.
8209 When we find one, move the %hi just in front of it. We do
8210 this in two passes. In the first pass, we try to find a
8211 unique %lo. In the second pass, we permit multiple %hi
8212 relocs for a single %lo (this is a GNU extension). */
8213 seginfo
= seg_info (l
->seg
);
8214 for (pass
= 0; pass
< 2; pass
++)
8219 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
8221 /* Check whether this is a %lo fixup which matches l->fixp. */
8222 if (f
->fx_r_type
== BFD_RELOC_LO16
8223 && f
->fx_addsy
== l
->fixp
->fx_addsy
8224 && f
->fx_offset
== l
->fixp
->fx_offset
8227 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
8228 || prev
->fx_addsy
!= f
->fx_addsy
8229 || prev
->fx_offset
!= f
->fx_offset
))
8233 /* Move l->fixp before f. */
8234 for (pf
= &seginfo
->fix_root
;
8236 pf
= &(*pf
)->fx_next
)
8237 assert (*pf
!= NULL
);
8239 *pf
= l
->fixp
->fx_next
;
8241 l
->fixp
->fx_next
= f
;
8243 seginfo
->fix_root
= l
->fixp
;
8245 prev
->fx_next
= l
->fixp
;
8257 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
8258 "Unmatched %%hi reloc");
8263 /* When generating embedded PIC code we need to use a special
8264 relocation to represent the difference of two symbols in the .text
8265 section (switch tables use a difference of this sort). See
8266 include/coff/mips.h for details. This macro checks whether this
8267 fixup requires the special reloc. */
8268 #define SWITCH_TABLE(fixp) \
8269 ((fixp)->fx_r_type == BFD_RELOC_32 \
8270 && (fixp)->fx_addsy != NULL \
8271 && (fixp)->fx_subsy != NULL \
8272 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
8273 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
8275 /* When generating embedded PIC code we must keep all PC relative
8276 relocations, in case the linker has to relax a call. We also need
8277 to keep relocations for switch table entries. */
8281 mips_force_relocation (fixp
)
8284 return (mips_pic
== EMBEDDED_PIC
8286 || SWITCH_TABLE (fixp
)
8287 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
8288 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
8291 /* Apply a fixup to the object file. */
8294 md_apply_fix (fixP
, valueP
)
8301 assert (fixP
->fx_size
== 4
8302 || fixP
->fx_r_type
== BFD_RELOC_16
8303 || fixP
->fx_r_type
== BFD_RELOC_64
);
8307 /* If we aren't adjusting this fixup to be against the section
8308 symbol, we need to adjust the value. */
8310 if (fixP
->fx_addsy
!= NULL
8311 && OUTPUT_FLAVOR
== bfd_target_elf_flavour
8312 && S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
)
8314 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8315 if (value
!= 0 && ! fixP
->fx_pcrel
)
8317 /* In this case, the bfd_install_relocation routine will
8318 incorrectly add the symbol value back in. We just want
8319 the addend to appear in the object file. */
8320 value
-= S_GET_VALUE (fixP
->fx_addsy
);
8325 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
8327 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
8330 switch (fixP
->fx_r_type
)
8332 case BFD_RELOC_MIPS_JMP
:
8333 case BFD_RELOC_HI16
:
8334 case BFD_RELOC_HI16_S
:
8335 case BFD_RELOC_MIPS_GPREL
:
8336 case BFD_RELOC_MIPS_LITERAL
:
8337 case BFD_RELOC_MIPS_CALL16
:
8338 case BFD_RELOC_MIPS_GOT16
:
8339 case BFD_RELOC_MIPS_GPREL32
:
8340 case BFD_RELOC_MIPS_GOT_HI16
:
8341 case BFD_RELOC_MIPS_GOT_LO16
:
8342 case BFD_RELOC_MIPS_CALL_HI16
:
8343 case BFD_RELOC_MIPS_CALL_LO16
:
8345 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8346 "Invalid PC relative reloc");
8347 /* Nothing needed to do. The value comes from the reloc entry */
8350 case BFD_RELOC_MIPS16_JMP
:
8351 /* We currently always generate a reloc against a symbol, which
8352 means that we don't want an addend even if the symbol is
8354 fixP
->fx_addnumber
= 0;
8357 case BFD_RELOC_PCREL_HI16_S
:
8358 /* The addend for this is tricky if it is internal, so we just
8359 do everything here rather than in bfd_perform_relocation. */
8360 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8362 /* For an external symbol adjust by the address to make it
8363 pcrel_offset. We use the address of the RELLO reloc
8364 which follows this one. */
8365 value
+= (fixP
->fx_next
->fx_frag
->fr_address
8366 + fixP
->fx_next
->fx_where
);
8371 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8372 if (target_big_endian
)
8374 md_number_to_chars (buf
, value
, 2);
8377 case BFD_RELOC_PCREL_LO16
:
8378 /* The addend for this is tricky if it is internal, so we just
8379 do everything here rather than in bfd_perform_relocation. */
8380 if ((fixP
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
) == 0)
8381 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
8382 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8383 if (target_big_endian
)
8385 md_number_to_chars (buf
, value
, 2);
8389 /* This is handled like BFD_RELOC_32, but we output a sign
8390 extended value if we are only 32 bits. */
8392 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8394 if (8 <= sizeof (valueT
))
8395 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8402 w1
= w2
= fixP
->fx_where
;
8403 if (target_big_endian
)
8407 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
8408 if ((value
& 0x80000000) != 0)
8412 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
8418 /* If we are deleting this reloc entry, we must fill in the
8419 value now. This can happen if we have a .word which is not
8420 resolved when it appears but is later defined. We also need
8421 to fill in the value if this is an embedded PIC switch table
8424 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
8425 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8430 /* If we are deleting this reloc entry, we must fill in the
8432 assert (fixP
->fx_size
== 2);
8434 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
8438 case BFD_RELOC_LO16
:
8439 /* When handling an embedded PIC switch statement, we can wind
8440 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
8443 if (value
< -0x8000 || value
> 0x7fff)
8444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8445 "relocation overflow");
8446 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
8447 if (target_big_endian
)
8449 md_number_to_chars (buf
, value
, 2);
8453 case BFD_RELOC_16_PCREL_S2
:
8455 * We need to save the bits in the instruction since fixup_segment()
8456 * might be deleting the relocation entry (i.e., a branch within
8457 * the current segment).
8459 if ((value
& 0x3) != 0)
8460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8461 "Branch to odd address (%lx)", value
);
8464 /* update old instruction data */
8465 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
8466 if (target_big_endian
)
8467 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
8469 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
8471 if (value
>= -0x8000 && value
< 0x8000)
8472 insn
|= value
& 0xffff;
8475 /* The branch offset is too large. If this is an
8476 unconditional branch, and we are not generating PIC code,
8477 we can convert it to an absolute jump instruction. */
8478 if (mips_pic
== NO_PIC
8480 && fixP
->fx_frag
->fr_address
>= text_section
->vma
8481 && (fixP
->fx_frag
->fr_address
8482 < text_section
->vma
+ text_section
->_raw_size
)
8483 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
8484 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
8485 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
8487 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
8488 insn
= 0x0c000000; /* jal */
8490 insn
= 0x08000000; /* j */
8491 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
8493 fixP
->fx_addsy
= section_symbol (text_section
);
8494 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
8498 /* FIXME. It would be possible in principle to handle
8499 conditional branches which overflow. They could be
8500 transformed into a branch around a jump. This would
8501 require setting up variant frags for each different
8502 branch type. The native MIPS assembler attempts to
8503 handle these cases, but it appears to do it
8505 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
8506 "Relocation overflow");
8510 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
8525 const struct mips_opcode
*p
;
8526 int treg
, sreg
, dreg
, shamt
;
8531 for (i
= 0; i
< NUMOPCODES
; ++i
)
8533 p
= &mips_opcodes
[i
];
8534 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
8536 printf ("%08lx %s\t", oc
, p
->name
);
8537 treg
= (oc
>> 16) & 0x1f;
8538 sreg
= (oc
>> 21) & 0x1f;
8539 dreg
= (oc
>> 11) & 0x1f;
8540 shamt
= (oc
>> 6) & 0x1f;
8542 for (args
= p
->args
;; ++args
)
8553 printf ("%c", *args
);
8557 assert (treg
== sreg
);
8558 printf ("$%d,$%d", treg
, sreg
);
8563 printf ("$%d", dreg
);
8568 printf ("$%d", treg
);
8572 printf ("0x%x", treg
);
8577 printf ("$%d", sreg
);
8581 printf ("0x%08lx", oc
& 0x1ffffff);
8593 printf ("$%d", shamt
);
8604 printf ("%08lx UNDEFINED\n", oc
);
8615 name
= input_line_pointer
;
8616 c
= get_symbol_end ();
8617 p
= (symbolS
*) symbol_find_or_make (name
);
8618 *input_line_pointer
= c
;
8622 /* Align the current frag to a given power of two. The MIPS assembler
8623 also automatically adjusts any preceding label. */
8626 mips_align (to
, fill
, label
)
8631 mips_emit_delays (false);
8632 frag_align (to
, fill
);
8633 record_alignment (now_seg
, to
);
8636 assert (S_GET_SEGMENT (label
) == now_seg
);
8637 label
->sy_frag
= frag_now
;
8638 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
8642 /* Align to a given power of two. .align 0 turns off the automatic
8643 alignment used by the data creating pseudo-ops. */
8650 register long temp_fill
;
8651 long max_alignment
= 15;
8655 o Note that the assembler pulls down any immediately preceeding label
8656 to the aligned address.
8657 o It's not documented but auto alignment is reinstated by
8658 a .align pseudo instruction.
8659 o Note also that after auto alignment is turned off the mips assembler
8660 issues an error on attempt to assemble an improperly aligned data item.
8665 temp
= get_absolute_expression ();
8666 if (temp
> max_alignment
)
8667 as_bad ("Alignment too large: %d. assumed.", temp
= max_alignment
);
8670 as_warn ("Alignment negative: 0 assumed.");
8673 if (*input_line_pointer
== ',')
8675 input_line_pointer
++;
8676 temp_fill
= get_absolute_expression ();
8683 mips_align (temp
, (int) temp_fill
,
8684 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
8691 demand_empty_rest_of_line ();
8695 mips_flush_pending_output ()
8697 mips_emit_delays (false);
8698 mips_clear_insn_labels ();
8707 /* When generating embedded PIC code, we only use the .text, .lit8,
8708 .sdata and .sbss sections. We change the .data and .rdata
8709 pseudo-ops to use .sdata. */
8710 if (mips_pic
== EMBEDDED_PIC
8711 && (sec
== 'd' || sec
== 'r'))
8714 mips_emit_delays (false);
8724 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
8725 demand_empty_rest_of_line ();
8729 if (USE_GLOBAL_POINTER_OPT
)
8731 seg
= subseg_new (RDATA_SECTION_NAME
,
8732 (subsegT
) get_absolute_expression ());
8733 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8735 bfd_set_section_flags (stdoutput
, seg
,
8741 if (strcmp (TARGET_OS
, "elf") != 0)
8742 bfd_set_section_alignment (stdoutput
, seg
, 4);
8744 demand_empty_rest_of_line ();
8748 as_bad ("No read only data section in this object file format");
8749 demand_empty_rest_of_line ();
8755 if (USE_GLOBAL_POINTER_OPT
)
8757 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
8758 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
8760 bfd_set_section_flags (stdoutput
, seg
,
8761 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
8763 if (strcmp (TARGET_OS
, "elf") != 0)
8764 bfd_set_section_alignment (stdoutput
, seg
, 4);
8766 demand_empty_rest_of_line ();
8771 as_bad ("Global pointers not supported; recompile -G 0");
8772 demand_empty_rest_of_line ();
8781 mips_enable_auto_align ()
8792 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8793 mips_emit_delays (false);
8794 if (log_size
> 0 && auto_align
)
8795 mips_align (log_size
, 0, label
);
8796 mips_clear_insn_labels ();
8797 cons (1 << log_size
);
8806 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
8808 mips_emit_delays (false);
8812 mips_align (3, 0, label
);
8814 mips_align (2, 0, label
);
8816 mips_clear_insn_labels ();
8821 /* Handle .globl. We need to override it because on Irix 5 you are
8824 where foo is an undefined symbol, to mean that foo should be
8825 considered to be the address of a function. */
8836 name
= input_line_pointer
;
8837 c
= get_symbol_end ();
8838 symbolP
= symbol_find_or_make (name
);
8839 *input_line_pointer
= c
;
8842 /* On Irix 5, every global symbol that is not explicitly labelled as
8843 being a function is apparently labelled as being an object. */
8846 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
8851 secname
= input_line_pointer
;
8852 c
= get_symbol_end ();
8853 sec
= bfd_get_section_by_name (stdoutput
, secname
);
8855 as_bad ("%s: no such section", secname
);
8856 *input_line_pointer
= c
;
8858 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
8859 flag
= BSF_FUNCTION
;
8862 symbolP
->bsym
->flags
|= flag
;
8864 S_SET_EXTERNAL (symbolP
);
8865 demand_empty_rest_of_line ();
8875 opt
= input_line_pointer
;
8876 c
= get_symbol_end ();
8880 /* FIXME: What does this mean? */
8882 else if (strncmp (opt
, "pic", 3) == 0)
8890 mips_pic
= SVR4_PIC
;
8892 as_bad (".option pic%d not supported", i
);
8894 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
8896 if (g_switch_seen
&& g_switch_value
!= 0)
8897 as_warn ("-G may not be used with SVR4 PIC code");
8899 bfd_set_gp_size (stdoutput
, 0);
8903 as_warn ("Unrecognized option \"%s\"", opt
);
8905 *input_line_pointer
= c
;
8906 demand_empty_rest_of_line ();
8913 char *name
= input_line_pointer
, ch
;
8915 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
8916 input_line_pointer
++;
8917 ch
= *input_line_pointer
;
8918 *input_line_pointer
= '\0';
8920 if (strcmp (name
, "reorder") == 0)
8924 prev_insn_unreordered
= 1;
8925 prev_prev_insn_unreordered
= 1;
8929 else if (strcmp (name
, "noreorder") == 0)
8931 mips_emit_delays (true);
8933 mips_any_noreorder
= 1;
8935 else if (strcmp (name
, "at") == 0)
8939 else if (strcmp (name
, "noat") == 0)
8943 else if (strcmp (name
, "macro") == 0)
8945 mips_warn_about_macros
= 0;
8947 else if (strcmp (name
, "nomacro") == 0)
8949 if (mips_noreorder
== 0)
8950 as_bad ("`noreorder' must be set before `nomacro'");
8951 mips_warn_about_macros
= 1;
8953 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
8957 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
8961 else if (strcmp (name
, "bopt") == 0)
8965 else if (strcmp (name
, "nobopt") == 0)
8969 else if (strcmp (name
, "mips16") == 0
8970 || strcmp (name
, "MIPS-16") == 0)
8972 else if (strcmp (name
, "nomips16") == 0
8973 || strcmp (name
, "noMIPS-16") == 0)
8975 else if (strncmp (name
, "mips", 4) == 0)
8979 /* Permit the user to change the ISA on the fly. Needless to
8980 say, misuse can cause serious problems. */
8981 isa
= atoi (name
+ 4);
8983 mips_isa
= file_mips_isa
;
8984 else if (isa
< 1 || isa
> 4)
8985 as_bad ("unknown ISA level");
8989 else if (strcmp (name
, "autoextend") == 0)
8990 mips16_autoextend
= 1;
8991 else if (strcmp (name
, "noautoextend") == 0)
8992 mips16_autoextend
= 0;
8995 as_warn ("Tried to set unrecognized symbol: %s\n", name
);
8997 *input_line_pointer
= ch
;
8998 demand_empty_rest_of_line ();
9001 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
9002 .option pic2. It means to generate SVR4 PIC calls. */
9008 mips_pic
= SVR4_PIC
;
9009 if (USE_GLOBAL_POINTER_OPT
)
9011 if (g_switch_seen
&& g_switch_value
!= 0)
9012 as_warn ("-G may not be used with SVR4 PIC code");
9015 bfd_set_gp_size (stdoutput
, 0);
9016 demand_empty_rest_of_line ();
9019 /* Handle the .cpload pseudo-op. This is used when generating SVR4
9020 PIC code. It sets the $gp register for the function based on the
9021 function address, which is in the register named in the argument.
9022 This uses a relocation against _gp_disp, which is handled specially
9023 by the linker. The result is:
9024 lui $gp,%hi(_gp_disp)
9025 addiu $gp,$gp,%lo(_gp_disp)
9026 addu $gp,$gp,.cpload argument
9027 The .cpload argument is normally $25 == $t9. */
9036 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
9037 if (mips_pic
!= SVR4_PIC
)
9043 /* .cpload should be a in .set noreorder section. */
9044 if (mips_noreorder
== 0)
9045 as_warn (".cpload not in noreorder section");
9048 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
9049 ex
.X_op_symbol
= NULL
;
9050 ex
.X_add_number
= 0;
9052 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
9053 ex
.X_add_symbol
->bsym
->flags
|= BSF_OBJECT
;
9055 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
9056 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
9057 (int) BFD_RELOC_LO16
);
9059 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
9060 GP
, GP
, tc_get_register (0));
9062 demand_empty_rest_of_line ();
9065 /* Handle the .cprestore pseudo-op. This stores $gp into a given
9066 offset from $sp. The offset is remembered, and after making a PIC
9067 call $gp is restored from that location. */
9070 s_cprestore (ignore
)
9076 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
9077 if (mips_pic
!= SVR4_PIC
)
9083 mips_cprestore_offset
= get_absolute_expression ();
9085 ex
.X_op
= O_constant
;
9086 ex
.X_add_symbol
= NULL
;
9087 ex
.X_op_symbol
= NULL
;
9088 ex
.X_add_number
= mips_cprestore_offset
;
9090 macro_build ((char *) NULL
, &icnt
, &ex
,
9091 mips_isa
< 3 ? "sw" : "sd",
9092 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
9094 demand_empty_rest_of_line ();
9097 /* Handle the .gpword pseudo-op. This is used when generating PIC
9098 code. It generates a 32 bit GP relative reloc. */
9108 /* When not generating PIC code, this is treated as .word. */
9109 if (mips_pic
!= SVR4_PIC
)
9115 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
9116 mips_emit_delays (true);
9118 mips_align (2, 0, label
);
9119 mips_clear_insn_labels ();
9123 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
9125 as_bad ("Unsupported use of .gpword");
9126 ignore_rest_of_line ();
9130 md_number_to_chars (p
, (valueT
) 0, 4);
9131 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
9132 BFD_RELOC_MIPS_GPREL32
);
9134 demand_empty_rest_of_line ();
9137 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
9138 tables in SVR4 PIC code. */
9147 /* This is ignored when not generating SVR4 PIC code. */
9148 if (mips_pic
!= SVR4_PIC
)
9154 /* Add $gp to the register named as an argument. */
9155 reg
= tc_get_register (0);
9156 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
9157 mips_isa
< 3 ? "addu" : "daddu",
9158 "d,v,t", reg
, reg
, GP
);
9160 demand_empty_rest_of_line ();
9163 /* Parse a register string into a number. Called from the ECOFF code
9164 to parse .frame. The argument is non-zero if this is the frame
9165 register, so that we can record it in mips_frame_reg. */
9168 tc_get_register (frame
)
9174 if (*input_line_pointer
++ != '$')
9176 as_warn ("expected `$'");
9179 else if (isdigit ((unsigned char) *input_line_pointer
))
9181 reg
= get_absolute_expression ();
9182 if (reg
< 0 || reg
>= 32)
9184 as_warn ("Bad register number");
9190 if (strncmp (input_line_pointer
, "fp", 2) == 0)
9192 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
9194 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
9196 else if (strncmp (input_line_pointer
, "at", 2) == 0)
9200 as_warn ("Unrecognized register name");
9203 input_line_pointer
+= 2;
9206 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
9211 md_section_align (seg
, addr
)
9215 int align
= bfd_get_section_alignment (stdoutput
, seg
);
9218 /* We don't need to align ELF sections to the full alignment.
9219 However, Irix 5 may prefer that we align them at least to a 16
9220 byte boundary. We don't bother to align the sections if we are
9221 targeted for an embedded system. */
9222 if (strcmp (TARGET_OS
, "elf") == 0)
9228 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
9231 /* Utility routine, called from above as well. If called while the
9232 input file is still being read, it's only an approximation. (For
9233 example, a symbol may later become defined which appeared to be
9234 undefined earlier.) */
9237 nopic_need_relax (sym
)
9243 if (USE_GLOBAL_POINTER_OPT
)
9245 const char *symname
;
9248 /* Find out whether this symbol can be referenced off the GP
9249 register. It can be if it is smaller than the -G size or if
9250 it is in the .sdata or .sbss section. Certain symbols can
9251 not be referenced off the GP, although it appears as though
9253 symname
= S_GET_NAME (sym
);
9254 if (symname
!= (const char *) NULL
9255 && (strcmp (symname
, "eprol") == 0
9256 || strcmp (symname
, "etext") == 0
9257 || strcmp (symname
, "_gp") == 0
9258 || strcmp (symname
, "edata") == 0
9259 || strcmp (symname
, "_fbss") == 0
9260 || strcmp (symname
, "_fdata") == 0
9261 || strcmp (symname
, "_ftext") == 0
9262 || strcmp (symname
, "end") == 0
9263 || strcmp (symname
, "_gp_disp") == 0))
9265 else if (! S_IS_DEFINED (sym
)
9267 #ifndef NO_ECOFF_DEBUGGING
9268 || (sym
->ecoff_extern_size
!= 0
9269 && sym
->ecoff_extern_size
<= g_switch_value
)
9271 || (S_GET_VALUE (sym
) != 0
9272 && S_GET_VALUE (sym
) <= g_switch_value
)))
9276 const char *segname
;
9278 segname
= segment_name (S_GET_SEGMENT (sym
));
9279 assert (strcmp (segname
, ".lit8") != 0
9280 && strcmp (segname
, ".lit4") != 0);
9281 change
= (strcmp (segname
, ".sdata") != 0
9282 && strcmp (segname
, ".sbss") != 0);
9287 /* We are not optimizing for the GP register. */
9291 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
9292 extended opcode. SEC is the section the frag is in. */
9295 mips16_extended_frag (fragp
, sec
, stretch
)
9301 register const struct mips16_immed_operand
*op
;
9303 int mintiny
, maxtiny
;
9306 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
9308 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
9311 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9312 op
= mips16_immed_operands
;
9313 while (op
->type
!= type
)
9316 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
9321 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
9324 maxtiny
= 1 << op
->nbits
;
9329 maxtiny
= (1 << op
->nbits
) - 1;
9334 mintiny
= - (1 << (op
->nbits
- 1));
9335 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
9338 /* We can't call S_GET_VALUE here, because we don't want to lock in
9339 a particular frag address. */
9340 if (fragp
->fr_symbol
->sy_value
.X_op
== O_constant
)
9342 val
= (fragp
->fr_symbol
->sy_value
.X_add_number
9343 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9344 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
9346 else if (fragp
->fr_symbol
->sy_value
.X_op
== O_symbol
9347 && (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_op
9350 val
= (fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_value
.X_add_number
9351 + fragp
->fr_symbol
->sy_value
.X_add_symbol
->sy_frag
->fr_address
9352 + fragp
->fr_symbol
->sy_value
.X_add_number
9353 + fragp
->fr_symbol
->sy_frag
->fr_address
);
9354 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
->sy_value
.X_add_symbol
);
9363 /* We won't have the section when we are called from
9364 mips_relax_frag. However, we will always have been called
9365 from md_estimate_size_before_relax first. If this is a
9366 branch to a different section, we mark it as such. If SEC is
9367 NULL, and the frag is not marked, then it must be a branch to
9368 the same section. */
9371 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
9379 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9381 /* FIXME: We should support this, and let the linker
9382 catch branches and loads that are out of range. */
9383 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
9384 "unsupported PC relative reference to different section");
9390 /* In this case, we know for sure that the symbol fragment is in
9391 the same section. If the fr_address of the symbol fragment
9392 is greater then the address of this fragment we want to add
9393 in STRETCH in order to get a better estimate of the address.
9394 This particularly matters because of the shift bits. */
9396 && fragp
->fr_symbol
->sy_frag
->fr_address
>= fragp
->fr_address
)
9400 /* Adjust stretch for any alignment frag. */
9401 for (f
= fragp
; f
!= fragp
->fr_symbol
->sy_frag
; f
= f
->fr_next
)
9404 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
9407 stretch
= - ((- stretch
)
9408 & ~ ((1 << (int) f
->fr_offset
) - 1));
9410 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
9418 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9420 /* The base address rules are complicated. The base address of
9421 a branch is the following instruction. The base address of a
9422 PC relative load or add is the instruction itself, but if it
9423 is extended add 2, and if it is in a delay slot (in which
9424 case it can not be extended) use the address of the
9425 instruction whose delay slot it is in. */
9426 if (type
== 'p' || type
== 'q')
9429 /* Ignore the low bit in the target, since it will be set
9430 for a text label. */
9434 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9436 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9439 /* If we are currently assuming that this frag should be
9440 extended, then the current address is two bytes higher. */
9441 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9444 val
-= addr
& ~ ((1 << op
->shift
) - 1);
9446 /* Branch offsets have an implicit 0 in the lowest bit. */
9447 if (type
== 'p' || type
== 'q')
9450 /* If any of the shifted bits are set, we must use an extended
9451 opcode. If the address depends on the size of this
9452 instruction, this can lead to a loop, so we arrange to always
9453 use an extended opcode. We only check this when we are in
9454 the main relaxation loop, when SEC is NULL. */
9455 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
9458 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9462 /* If we are about to mark a frag as extended because the value
9463 is precisely maxtiny + 1, then there is a chance of an
9464 infinite loop as in the following code:
9469 In this case when the la is extended, foo is 0x3fc bytes
9470 away, so the la can be shrunk, but then foo is 0x400 away, so
9471 the la must be extended. To avoid this loop, we mark the
9472 frag as extended if it was small, and is about to become
9473 extended with a value of maxtiny + 1. */
9474 if (val
== ((maxtiny
+ 1) << op
->shift
)
9475 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
9479 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
9483 else if (symsec
!= absolute_section
&& sec
!= NULL
)
9484 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, "unsupported relocation");
9486 if ((val
& ((1 << op
->shift
) - 1)) != 0
9487 || val
< (mintiny
<< op
->shift
)
9488 || val
> (maxtiny
<< op
->shift
))
9494 /* Estimate the size of a frag before relaxing. Unless this is the
9495 mips16, we are not really relaxing here, and the final size is
9496 encoded in the subtype information. For the mips16, we have to
9497 decide whether we are using an extended opcode or not. */
9501 md_estimate_size_before_relax (fragp
, segtype
)
9507 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9509 if (mips16_extended_frag (fragp
, segtype
, 0))
9511 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9516 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9521 if (mips_pic
== NO_PIC
)
9523 change
= nopic_need_relax (fragp
->fr_symbol
);
9525 else if (mips_pic
== SVR4_PIC
)
9527 asection
*symsec
= fragp
->fr_symbol
->bsym
->section
;
9529 /* This must duplicate the test in adjust_reloc_syms. */
9530 change
= (symsec
!= &bfd_und_section
9531 && symsec
!= &bfd_abs_section
9532 && ! bfd_is_com_section (symsec
));
9539 /* Record the offset to the first reloc in the fr_opcode field.
9540 This lets md_convert_frag and tc_gen_reloc know that the code
9541 must be expanded. */
9542 fragp
->fr_opcode
= (fragp
->fr_literal
9544 - RELAX_OLD (fragp
->fr_subtype
)
9545 + RELAX_RELOC1 (fragp
->fr_subtype
));
9546 /* FIXME: This really needs as_warn_where. */
9547 if (RELAX_WARN (fragp
->fr_subtype
))
9548 as_warn ("AT used after \".set noat\" or macro used after \".set nomacro\"");
9554 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
9557 /* This is called to see whether a reloc against a defined symbol
9558 should be converted into a reloc against a section. Don't adjust
9559 MIPS16 jump relocations, so we don't have to worry about the format
9560 of the offset in the .o file. Don't adjust relocations against
9561 mips16 symbols, so that the linker can find them if it needs to set
9565 mips_fix_adjustable (fixp
)
9568 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
9570 if (fixp
->fx_addsy
== NULL
)
9573 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9574 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
)
9580 /* Translate internal representation of relocation info to BFD target
9584 tc_gen_reloc (section
, fixp
)
9588 static arelent
*retval
[4];
9590 bfd_reloc_code_real_type code
;
9592 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
9595 reloc
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9596 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9598 if (mips_pic
== EMBEDDED_PIC
9599 && SWITCH_TABLE (fixp
))
9601 /* For a switch table entry we use a special reloc. The addend
9602 is actually the difference between the reloc address and the
9604 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9605 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
9606 as_fatal ("Double check fx_r_type in tc-mips.c:tc_gen_reloc");
9607 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
9609 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
9611 /* We use a special addend for an internal RELLO reloc. */
9612 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9613 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
9615 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
9617 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
9619 assert (fixp
->fx_next
!= NULL
9620 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
9621 /* We use a special addend for an internal RELHI reloc. The
9622 reloc is relative to the RELLO; adjust the addend
9624 if (fixp
->fx_addsy
->bsym
->flags
& BSF_SECTION_SYM
)
9625 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
9626 + fixp
->fx_next
->fx_where
9627 - S_GET_VALUE (fixp
->fx_subsy
));
9629 reloc
->addend
= (fixp
->fx_addnumber
9630 + fixp
->fx_next
->fx_frag
->fr_address
9631 + fixp
->fx_next
->fx_where
);
9633 else if (fixp
->fx_pcrel
== 0)
9634 reloc
->addend
= fixp
->fx_addnumber
;
9637 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
9638 /* A gruesome hack which is a result of the gruesome gas reloc
9640 reloc
->addend
= reloc
->address
;
9642 reloc
->addend
= -reloc
->address
;
9645 /* If this is a variant frag, we may need to adjust the existing
9646 reloc and generate a new one. */
9647 if (fixp
->fx_frag
->fr_opcode
!= NULL
9648 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9649 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
9650 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
9651 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9652 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
9653 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9654 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
9658 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
9660 /* If this is not the last reloc in this frag, then we have two
9661 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
9662 CALL_HI16/CALL_LO16, both of which are being replaced. Let
9663 the second one handle all of them. */
9664 if (fixp
->fx_next
!= NULL
9665 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
9667 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
9668 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
9669 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
9670 && (fixp
->fx_next
->fx_r_type
9671 == BFD_RELOC_MIPS_GOT_LO16
))
9672 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
9673 && (fixp
->fx_next
->fx_r_type
9674 == BFD_RELOC_MIPS_CALL_LO16
)));
9679 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
9680 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
9681 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
9683 reloc2
->sym_ptr_ptr
= &fixp
->fx_addsy
->bsym
;
9684 reloc2
->address
= (reloc
->address
9685 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
9686 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
9687 reloc2
->addend
= fixp
->fx_addnumber
;
9688 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
9689 assert (reloc2
->howto
!= NULL
);
9691 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
9695 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
9698 reloc3
->address
+= 4;
9701 if (mips_pic
== NO_PIC
)
9703 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
9704 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
9706 else if (mips_pic
== SVR4_PIC
)
9708 switch (fixp
->fx_r_type
)
9712 case BFD_RELOC_MIPS_GOT16
:
9714 case BFD_RELOC_MIPS_CALL16
:
9715 case BFD_RELOC_MIPS_GOT_LO16
:
9716 case BFD_RELOC_MIPS_CALL_LO16
:
9717 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
9725 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
9726 fixup_segment converted a non-PC relative reloc into a PC
9727 relative reloc. In such a case, we need to convert the reloc
9729 code
= fixp
->fx_r_type
;
9735 code
= BFD_RELOC_8_PCREL
;
9738 code
= BFD_RELOC_16_PCREL
;
9741 code
= BFD_RELOC_32_PCREL
;
9744 code
= BFD_RELOC_64_PCREL
;
9746 case BFD_RELOC_8_PCREL
:
9747 case BFD_RELOC_16_PCREL
:
9748 case BFD_RELOC_32_PCREL
:
9749 case BFD_RELOC_64_PCREL
:
9750 case BFD_RELOC_16_PCREL_S2
:
9751 case BFD_RELOC_PCREL_HI16_S
:
9752 case BFD_RELOC_PCREL_LO16
:
9755 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9756 "Cannot make %s relocation PC relative",
9757 bfd_get_reloc_code_name (code
));
9761 /* To support a PC relative reloc when generating embedded PIC code
9762 for ECOFF, we use a Cygnus extension. We check for that here to
9763 make sure that we don't let such a reloc escape normally. */
9764 if (OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
9765 && code
== BFD_RELOC_16_PCREL_S2
9766 && mips_pic
!= EMBEDDED_PIC
)
9767 reloc
->howto
= NULL
;
9769 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
9771 if (reloc
->howto
== NULL
)
9773 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
9774 "Can not represent %s relocation in this object file format",
9775 bfd_get_reloc_code_name (code
));
9782 /* Relax a machine dependent frag. This returns the amount by which
9783 the current size of the frag should change. */
9786 mips_relax_frag (fragp
, stretch
)
9790 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
9793 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
9795 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9797 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
9802 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9804 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
9811 /* Convert a machine dependent frag. */
9814 md_convert_frag (abfd
, asec
, fragp
)
9822 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
9825 register const struct mips16_immed_operand
*op
;
9831 unsigned short extend
;
9833 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
9834 op
= mips16_immed_operands
;
9835 while (op
->type
!= type
)
9838 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
9849 resolve_symbol_value (fragp
->fr_symbol
);
9850 val
= S_GET_VALUE (fragp
->fr_symbol
);
9855 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
9857 /* The rules for the base address of a PC relative reloc are
9858 complicated; see mips16_extended_frag. */
9859 if (type
== 'p' || type
== 'q')
9862 /* Ignore the low bit in the target, since it will be
9863 set for a text label. */
9867 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
9869 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
9874 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
9877 /* Make sure the section winds up with the alignment we have
9880 record_alignment (asec
, op
->shift
);
9883 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
9885 if (target_big_endian
)
9886 insn
= bfd_getb16 (buf
);
9888 insn
= bfd_getl16 (buf
);
9890 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
9891 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
9892 small
, ext
, &insn
, &use_extend
, &extend
);
9896 md_number_to_chars (buf
, 0xf000 | extend
, 2);
9901 md_number_to_chars (buf
, insn
, 2);
9907 if (fragp
->fr_opcode
== NULL
)
9910 old
= RELAX_OLD (fragp
->fr_subtype
);
9911 new = RELAX_NEW (fragp
->fr_subtype
);
9912 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
9915 memcpy (fixptr
- old
, fixptr
, new);
9917 fragp
->fr_fix
+= new - old
;
9923 /* This function is called after the relocs have been generated.
9924 We've been storing mips16 text labels as odd. Here we convert them
9925 back to even for the convenience of the debugger. */
9928 mips_frob_file_after_relocs ()
9931 unsigned int count
, i
;
9933 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9936 syms
= bfd_get_outsymbols (stdoutput
);
9937 count
= bfd_get_symcount (stdoutput
);
9938 for (i
= 0; i
< count
; i
++, syms
++)
9940 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
9941 && ((*syms
)->value
& 1) != 0)
9943 (*syms
)->value
&= ~1;
9944 /* If the symbol has an odd size, it was probably computed
9945 incorrectly, so adjust that as well. */
9946 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
9947 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
9954 /* This function is called whenever a label is defined. It is used
9955 when handling branch delays; if a branch has a label, we assume we
9959 mips_define_label (sym
)
9962 struct insn_label_list
*l
;
9964 if (free_insn_labels
== NULL
)
9965 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
9968 l
= free_insn_labels
;
9969 free_insn_labels
= l
->next
;
9973 l
->next
= insn_labels
;
9977 /* Decide whether a label is local. This is called by LOCAL_LABEL.
9978 In order to work with gcc when using mips-tfile, we must keep all
9979 local labels. However, in other cases, we want to discard them,
9980 since they are useless. */
9983 mips_local_label (name
)
9986 #ifndef NO_ECOFF_DEBUGGING
9989 && ! ecoff_debugging_seen
)
9991 /* We were called with -g, but we didn't see any debugging
9992 information. That may mean that gcc is smuggling debugging
9993 information through to mips-tfile, in which case we must
9994 generate all local labels. */
9999 /* Here it's OK to discard local labels. */
10001 return name
[0] == '$';
10004 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10006 /* Some special processing for a MIPS ELF file. */
10009 mips_elf_final_processing ()
10011 /* Write out the register information. */
10016 s
.ri_gprmask
= mips_gprmask
;
10017 s
.ri_cprmask
[0] = mips_cprmask
[0];
10018 s
.ri_cprmask
[1] = mips_cprmask
[1];
10019 s
.ri_cprmask
[2] = mips_cprmask
[2];
10020 s
.ri_cprmask
[3] = mips_cprmask
[3];
10021 /* The gp_value field is set by the MIPS ELF backend. */
10023 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
10024 ((Elf32_External_RegInfo
*)
10025 mips_regmask_frag
));
10029 Elf64_Internal_RegInfo s
;
10031 s
.ri_gprmask
= mips_gprmask
;
10033 s
.ri_cprmask
[0] = mips_cprmask
[0];
10034 s
.ri_cprmask
[1] = mips_cprmask
[1];
10035 s
.ri_cprmask
[2] = mips_cprmask
[2];
10036 s
.ri_cprmask
[3] = mips_cprmask
[3];
10037 /* The gp_value field is set by the MIPS ELF backend. */
10039 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
10040 ((Elf64_External_RegInfo
*)
10041 mips_regmask_frag
));
10044 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
10045 sort of BFD interface for this. */
10046 if (mips_any_noreorder
)
10047 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
10048 if (mips_pic
!= NO_PIC
)
10049 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
10052 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
10054 /* These functions should really be defined by the object file format,
10055 since they are related to debugging information. However, this
10056 code has to work for the a.out format, which does not define them,
10057 so we provide simple versions here. These don't actually generate
10058 any debugging information, but they do simple checking and someday
10059 somebody may make them useful. */
10063 struct loc
*loc_next
;
10064 unsigned long loc_fileno
;
10065 unsigned long loc_lineno
;
10066 unsigned long loc_offset
;
10067 unsigned short loc_delta
;
10068 unsigned short loc_count
;
10075 typedef struct proc
10077 struct proc
*proc_next
;
10078 struct symbol
*proc_isym
;
10079 struct symbol
*proc_end
;
10080 unsigned long proc_reg_mask
;
10081 unsigned long proc_reg_offset
;
10082 unsigned long proc_fpreg_mask
;
10083 unsigned long proc_fpreg_offset
;
10084 unsigned long proc_frameoffset
;
10085 unsigned long proc_framereg
;
10086 unsigned long proc_pcreg
;
10088 struct file
*proc_file
;
10093 typedef struct file
10095 struct file
*file_next
;
10096 unsigned long file_fileno
;
10097 struct symbol
*file_symbol
;
10098 struct symbol
*file_end
;
10099 struct proc
*file_proc
;
10104 static struct obstack proc_frags
;
10105 static procS
*proc_lastP
;
10106 static procS
*proc_rootP
;
10107 static int numprocs
;
10112 obstack_begin (&proc_frags
, 0x2000);
10118 /* check for premature end, nesting errors, etc */
10119 if (proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10120 as_warn ("missing `.end' at end of assembly");
10129 if (*input_line_pointer
== '-')
10131 ++input_line_pointer
;
10134 if (!isdigit (*input_line_pointer
))
10135 as_bad ("Expected simple number.");
10136 if (input_line_pointer
[0] == '0')
10138 if (input_line_pointer
[1] == 'x')
10140 input_line_pointer
+= 2;
10141 while (isxdigit (*input_line_pointer
))
10144 val
|= hex_value (*input_line_pointer
++);
10146 return negative
? -val
: val
;
10150 ++input_line_pointer
;
10151 while (isdigit (*input_line_pointer
))
10154 val
|= *input_line_pointer
++ - '0';
10156 return negative
? -val
: val
;
10159 if (!isdigit (*input_line_pointer
))
10161 printf (" *input_line_pointer == '%c' 0x%02x\n",
10162 *input_line_pointer
, *input_line_pointer
);
10163 as_warn ("Invalid number");
10166 while (isdigit (*input_line_pointer
))
10169 val
+= *input_line_pointer
++ - '0';
10171 return negative
? -val
: val
;
10174 /* The .file directive; just like the usual .file directive, but there
10175 is an initial number which is the ECOFF file index. */
10183 line
= get_number ();
10188 /* The .end directive. */
10196 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10199 demand_empty_rest_of_line ();
10203 if (now_seg
!= text_section
)
10204 as_warn (".end not in text section");
10207 as_warn (".end and no .ent seen yet.");
10213 assert (S_GET_NAME (p
));
10214 if (strcmp (S_GET_NAME (p
), S_GET_NAME (proc_lastP
->proc_isym
)))
10215 as_warn (".end symbol does not match .ent symbol.");
10218 proc_lastP
->proc_end
= (symbolS
*) 1;
10221 /* The .aent and .ent directives. */
10231 symbolP
= get_symbol ();
10232 if (*input_line_pointer
== ',')
10233 input_line_pointer
++;
10234 SKIP_WHITESPACE ();
10235 if (isdigit (*input_line_pointer
) || *input_line_pointer
== '-')
10236 number
= get_number ();
10237 if (now_seg
!= text_section
)
10238 as_warn (".ent or .aent not in text section.");
10240 if (!aent
&& proc_lastP
&& proc_lastP
->proc_end
== NULL
)
10241 as_warn ("missing `.end'");
10245 procP
= (procS
*) obstack_alloc (&proc_frags
, sizeof (*procP
));
10246 procP
->proc_isym
= symbolP
;
10247 procP
->proc_reg_mask
= 0;
10248 procP
->proc_reg_offset
= 0;
10249 procP
->proc_fpreg_mask
= 0;
10250 procP
->proc_fpreg_offset
= 0;
10251 procP
->proc_frameoffset
= 0;
10252 procP
->proc_framereg
= 0;
10253 procP
->proc_pcreg
= 0;
10254 procP
->proc_end
= NULL
;
10255 procP
->proc_next
= NULL
;
10257 proc_lastP
->proc_next
= procP
;
10259 proc_rootP
= procP
;
10260 proc_lastP
= procP
;
10263 demand_empty_rest_of_line ();
10266 /* The .frame directive. */
10279 frame_reg
= tc_get_register (1);
10280 if (*input_line_pointer
== ',')
10281 input_line_pointer
++;
10282 frame_off
= get_absolute_expression ();
10283 if (*input_line_pointer
== ',')
10284 input_line_pointer
++;
10285 pcreg
= tc_get_register (0);
10287 /* bob third eye */
10288 assert (proc_rootP
);
10289 proc_rootP
->proc_framereg
= frame_reg
;
10290 proc_rootP
->proc_frameoffset
= frame_off
;
10291 proc_rootP
->proc_pcreg
= pcreg
;
10292 /* bob macho .frame */
10294 /* We don't have to write out a frame stab for unoptimized code. */
10295 if (!(frame_reg
== FP
&& frame_off
== 0))
10298 as_warn ("No .ent for .frame to use.");
10299 (void) sprintf (str
, "R%d;%d", frame_reg
, frame_off
);
10300 symP
= symbol_new (str
, N_VFP
, 0, frag_now
);
10301 S_SET_TYPE (symP
, N_RMASK
);
10302 S_SET_OTHER (symP
, 0);
10303 S_SET_DESC (symP
, 0);
10304 symP
->sy_forward
= proc_lastP
->proc_isym
;
10305 /* bob perhaps I should have used pseudo set */
10307 demand_empty_rest_of_line ();
10311 /* The .fmask and .mask directives. */
10318 char str
[100], *strP
;
10324 mask
= get_number ();
10325 if (*input_line_pointer
== ',')
10326 input_line_pointer
++;
10327 off
= get_absolute_expression ();
10329 /* bob only for coff */
10330 assert (proc_rootP
);
10331 if (reg_type
== 'F')
10333 proc_rootP
->proc_fpreg_mask
= mask
;
10334 proc_rootP
->proc_fpreg_offset
= off
;
10338 proc_rootP
->proc_reg_mask
= mask
;
10339 proc_rootP
->proc_reg_offset
= off
;
10342 /* bob macho .mask + .fmask */
10344 /* We don't have to write out a mask stab if no saved regs. */
10348 as_warn ("No .ent for .mask to use.");
10350 for (i
= 0; i
< 32; i
++)
10354 sprintf (strP
, "%c%d,", reg_type
, i
);
10355 strP
+= strlen (strP
);
10359 sprintf (strP
, ";%d,", off
);
10360 symP
= symbol_new (str
, N_RMASK
, 0, frag_now
);
10361 S_SET_TYPE (symP
, N_RMASK
);
10362 S_SET_OTHER (symP
, 0);
10363 S_SET_DESC (symP
, 0);
10364 symP
->sy_forward
= proc_lastP
->proc_isym
;
10365 /* bob perhaps I should have used pseudo set */
10370 /* The .loc directive. */
10381 assert (now_seg
== text_section
);
10383 lineno
= get_number ();
10384 addroff
= frag_now_fix ();
10386 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
10387 S_SET_TYPE (symbolP
, N_SLINE
);
10388 S_SET_OTHER (symbolP
, 0);
10389 S_SET_DESC (symbolP
, lineno
);
10390 symbolP
->sy_segment
= now_seg
;