1 /* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright (C) 1993, 94, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by the OSF and Ralph Campbell.
4 Written by Keith Knowles and Ralph Campbell, working independently.
5 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
8 This file is part of GAS.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the Free
22 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
38 #include "opcode/mips.h"
42 #define DBG(x) printf x
48 /* Clean up namespace so we can include obj-elf.h too. */
49 static int mips_output_flavor
PARAMS ((void));
50 static int mips_output_flavor () { return OUTPUT_FLAVOR
; }
51 #undef OBJ_PROCESS_STAB
58 #undef obj_frob_file_after_relocs
59 #undef obj_frob_symbol
61 #undef obj_sec_sym_ok_for_reloc
62 #undef OBJ_COPY_SYMBOL_ATTRIBUTES
65 /* Fix any of them that we actually care about. */
67 #define OUTPUT_FLAVOR mips_output_flavor()
74 #ifndef ECOFF_DEBUGGING
75 #define NO_ECOFF_DEBUGGING
76 #define ECOFF_DEBUGGING 0
81 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
82 static char *mips_regmask_frag
;
87 #define PIC_CALL_REG 25
95 #define ILLEGAL_REG (32)
97 /* Allow override of standard little-endian ECOFF format. */
99 #ifndef ECOFF_LITTLE_FORMAT
100 #define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
103 extern int target_big_endian
;
105 /* 1 is we should use the 64 bit MIPS ELF ABI, 0 if we should use the
106 32 bit ABI. This has no meaning for ECOFF.
107 Note that the default is always 32 bit, even if "configured" for
108 64 bit [e.g. --target=mips64-elf]. */
111 /* The default target format to use. */
113 mips_target_format ()
115 switch (OUTPUT_FLAVOR
)
117 case bfd_target_aout_flavour
:
118 return target_big_endian
? "a.out-mips-big" : "a.out-mips-little";
119 case bfd_target_ecoff_flavour
:
120 return target_big_endian
? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT
;
121 case bfd_target_coff_flavour
:
123 case bfd_target_elf_flavour
:
124 return (target_big_endian
125 ? (mips_64
? "elf64-bigmips" : "elf32-bigmips")
126 : (mips_64
? "elf64-littlemips" : "elf32-littlemips"));
133 /* The name of the readonly data section. */
134 #define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
136 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
138 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
140 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
144 /* This is the set of options which may be modified by the .set
145 pseudo-op. We use a struct so that .set push and .set pop are more
148 struct mips_set_options
150 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
151 if it has not been initialized. Changed by `.set mipsN', and the
152 -mipsN command line option, and the default CPU. */
154 /* Whether we are assembling for the mips16 processor. 0 if we are
155 not, 1 if we are, and -1 if the value has not been initialized.
156 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
157 -nomips16 command line options, and the default CPU. */
159 /* Non-zero if we should not reorder instructions. Changed by `.set
160 reorder' and `.set noreorder'. */
162 /* Non-zero if we should not permit the $at ($1) register to be used
163 in instructions. Changed by `.set at' and `.set noat'. */
165 /* Non-zero if we should warn when a macro instruction expands into
166 more than one machine instruction. Changed by `.set nomacro' and
168 int warn_about_macros
;
169 /* Non-zero if we should not move instructions. Changed by `.set
170 move', `.set volatile', `.set nomove', and `.set novolatile'. */
172 /* Non-zero if we should not optimize branches by moving the target
173 of the branch into the delay slot. Actually, we don't perform
174 this optimization anyhow. Changed by `.set bopt' and `.set
177 /* Non-zero if we should not autoextend mips16 instructions.
178 Changed by `.set autoextend' and `.set noautoextend'. */
182 /* This is the struct we use to hold the current set of options. Note
183 that we must set the isa and mips16 fields to -1 to indicate that
184 they have not been initialized. */
186 static struct mips_set_options mips_opts
= { -1, -1, 0, 0, 0, 0, 0, 0 };
188 /* These variables are filled in with the masks of registers used.
189 The object format code reads them and puts them in the appropriate
191 unsigned long mips_gprmask
;
192 unsigned long mips_cprmask
[4];
194 /* MIPS ISA we are using for this output file. */
195 static int file_mips_isa
;
197 /* The CPU type as a number: 2000, 3000, 4000, 4400, etc. */
198 static int mips_cpu
= -1;
200 /* The argument of the -mabi= flag. */
201 static char* mips_abi_string
= 0;
203 /* Wether we should mark the file EABI64 or EABI32. */
204 static int mips_eabi64
= 0;
206 /* If they asked for mips1 or mips2 and a cpu that is
207 mips3 or greater, then mark the object file 32BITMODE. */
208 static int mips_32bitmode
= 0;
210 /* True if -mgp32 was passed. */
211 static int mips_gp32
= 0;
213 /* Some ISA's have delay slots for instructions which read or write
214 from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
215 Return true if instructions marked INSN_LOAD_COPROC_DELAY,
216 INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
217 delay slot in this ISA. The uses of this macro assume that any
218 ISA that has delay slots for one of these, has them for all. They
219 also assume that ISAs which don't have delays for these insns, don't
220 have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
221 #define ISA_HAS_COPROC_DELAYS(ISA) ( \
227 /* Return true if ISA supports 64 bit gp register instructions. */
228 #define ISA_HAS_64BIT_REGS(ISA) ( \
233 /* Whether the processor uses hardware interlocks to protect
234 reads from the HI and LO registers, and thus does not
235 require nops to be inserted.
237 FIXME: GCC makes a distinction between -mcpu=FOO and -mFOO:
238 -mcpu=FOO schedules for FOO, but still produces code that meets the
239 requirements of MIPS ISA I. For example, it won't generate any
240 FOO-specific instructions, and it will still assume that any
241 scheduling hazards described in MIPS ISA I are there, even if FOO
242 has interlocks. -mFOO gives GCC permission to generate code that
243 will only run on a FOO; it will generate FOO-specific instructions,
244 and assume interlocks provided by a FOO.
246 However, GAS currently doesn't make this distinction; before Jan 28
247 1999, GAS's -mcpu=FOO implied -mFOO, which violates GCC's
248 assumptions. The GCC driver passes these flags through to GAS, so
249 if GAS actually does anything that doesn't meet MIPS ISA I with
250 -mFOO, then GCC's -mcpu=FOO flag isn't going to work.
252 And furthermore, it did not assume that -mFOO implied -mcpu=FOO,
253 which seems senseless --- why generate code which will only run on
254 a FOO, but schedule for something else?
256 So now, at least, -mcpu=FOO and -mFOO are exactly equivalent.
258 -- Jim Blandy <jimb@cygnus.com> */
260 #define hilo_interlocks (mips_cpu == 4010 \
263 /* Whether the processor uses hardware interlocks to protect reads
264 from the GPRs, and thus does not require nops to be inserted. */
265 #define gpr_interlocks \
266 (mips_opts.isa != 1 \
269 /* As with other "interlocks" this is used by hardware that has FP
270 (co-processor) interlocks. */
271 /* Itbl support may require additional care here. */
272 #define cop_interlocks (mips_cpu == 4300 \
275 /* Is this a mfhi or mflo instruction? */
276 #define MF_HILO_INSN(PINFO) \
277 ((PINFO & INSN_READ_HI) || (PINFO & INSN_READ_LO))
279 /* MIPS PIC level. */
283 /* Do not generate PIC code. */
286 /* Generate PIC code as in Irix 4. This is not implemented, and I'm
287 not sure what it is supposed to do. */
290 /* Generate PIC code as in the SVR4 MIPS ABI. */
293 /* Generate PIC code without using a global offset table: the data
294 segment has a maximum size of 64K, all data references are off
295 the $gp register, and all text references are PC relative. This
296 is used on some embedded systems. */
300 static enum mips_pic_level mips_pic
;
302 /* 1 if we should generate 32 bit offsets from the GP register in
303 SVR4_PIC mode. Currently has no meaning in other modes. */
304 static int mips_big_got
;
306 /* 1 if trap instructions should used for overflow rather than break
308 static int mips_trap
;
310 /* Non-zero if any .set noreorder directives were used. */
312 static int mips_any_noreorder
;
314 /* Non-zero if nops should be inserted when the register referenced in
315 an mfhi/mflo instruction is read in the next two instructions. */
316 static int mips_7000_hilo_fix
;
318 /* The size of the small data section. */
319 static int g_switch_value
= 8;
320 /* Whether the -G option was used. */
321 static int g_switch_seen
= 0;
326 /* If we can determine in advance that GP optimization won't be
327 possible, we can skip the relaxation stuff that tries to produce
328 GP-relative references. This makes delay slot optimization work
331 This function can only provide a guess, but it seems to work for
332 gcc output. It needs to guess right for gcc, otherwise gcc
333 will put what it thinks is a GP-relative instruction in a branch
336 I don't know if a fix is needed for the SVR4_PIC mode. I've only
337 fixed it for the non-PIC mode. KR 95/04/07 */
338 static int nopic_need_relax
PARAMS ((symbolS
*, int));
340 /* handle of the OPCODE hash table */
341 static struct hash_control
*op_hash
= NULL
;
343 /* The opcode hash table we use for the mips16. */
344 static struct hash_control
*mips16_op_hash
= NULL
;
346 /* This array holds the chars that always start a comment. If the
347 pre-processor is disabled, these aren't very useful */
348 const char comment_chars
[] = "#";
350 /* This array holds the chars that only start a comment at the beginning of
351 a line. If the line seems to have the form '# 123 filename'
352 .line and .file directives will appear in the pre-processed output */
353 /* Note that input_file.c hand checks for '#' at the beginning of the
354 first line of the input file. This is because the compiler outputs
355 #NO_APP at the beginning of its output. */
356 /* Also note that C style comments are always supported. */
357 const char line_comment_chars
[] = "#";
359 /* This array holds machine specific line separator characters. */
360 const char line_separator_chars
[] = ";";
362 /* Chars that can be used to separate mant from exp in floating point nums */
363 const char EXP_CHARS
[] = "eE";
365 /* Chars that mean this number is a floating point constant */
368 const char FLT_CHARS
[] = "rRsSfFdDxXpP";
370 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
371 changed in read.c . Ideally it shouldn't have to know about it at all,
372 but nothing is ideal around here.
375 static char *insn_error
;
377 static int auto_align
= 1;
379 /* When outputting SVR4 PIC code, the assembler needs to know the
380 offset in the stack frame from which to restore the $gp register.
381 This is set by the .cprestore pseudo-op, and saved in this
383 static offsetT mips_cprestore_offset
= -1;
385 /* This is the register which holds the stack frame, as set by the
386 .frame pseudo-op. This is needed to implement .cprestore. */
387 static int mips_frame_reg
= SP
;
389 /* To output NOP instructions correctly, we need to keep information
390 about the previous two instructions. */
392 /* Whether we are optimizing. The default value of 2 means to remove
393 unneeded NOPs and swap branch instructions when possible. A value
394 of 1 means to not swap branches. A value of 0 means to always
396 static int mips_optimize
= 2;
398 /* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
399 equivalent to seeing no -g option at all. */
400 static int mips_debug
= 0;
402 /* The previous instruction. */
403 static struct mips_cl_insn prev_insn
;
405 /* The instruction before prev_insn. */
406 static struct mips_cl_insn prev_prev_insn
;
408 /* If we don't want information for prev_insn or prev_prev_insn, we
409 point the insn_mo field at this dummy integer. */
410 static const struct mips_opcode dummy_opcode
= { NULL
, NULL
, 0, 0, 0, 0 };
412 /* Non-zero if prev_insn is valid. */
413 static int prev_insn_valid
;
415 /* The frag for the previous instruction. */
416 static struct frag
*prev_insn_frag
;
418 /* The offset into prev_insn_frag for the previous instruction. */
419 static long prev_insn_where
;
421 /* The reloc type for the previous instruction, if any. */
422 static bfd_reloc_code_real_type prev_insn_reloc_type
;
424 /* The reloc for the previous instruction, if any. */
425 static fixS
*prev_insn_fixp
;
427 /* Non-zero if the previous instruction was in a delay slot. */
428 static int prev_insn_is_delay_slot
;
430 /* Non-zero if the previous instruction was in a .set noreorder. */
431 static int prev_insn_unreordered
;
433 /* Non-zero if the previous instruction uses an extend opcode (if
435 static int prev_insn_extended
;
437 /* Non-zero if the previous previous instruction was in a .set
439 static int prev_prev_insn_unreordered
;
441 /* If this is set, it points to a frag holding nop instructions which
442 were inserted before the start of a noreorder section. If those
443 nops turn out to be unnecessary, the size of the frag can be
445 static fragS
*prev_nop_frag
;
447 /* The number of nop instructions we created in prev_nop_frag. */
448 static int prev_nop_frag_holds
;
450 /* The number of nop instructions that we know we need in
452 static int prev_nop_frag_required
;
454 /* The number of instructions we've seen since prev_nop_frag. */
455 static int prev_nop_frag_since
;
457 /* For ECOFF and ELF, relocations against symbols are done in two
458 parts, with a HI relocation and a LO relocation. Each relocation
459 has only 16 bits of space to store an addend. This means that in
460 order for the linker to handle carries correctly, it must be able
461 to locate both the HI and the LO relocation. This means that the
462 relocations must appear in order in the relocation table.
464 In order to implement this, we keep track of each unmatched HI
465 relocation. We then sort them so that they immediately precede the
466 corresponding LO relocation. */
471 struct mips_hi_fixup
*next
;
474 /* The section this fixup is in. */
478 /* The list of unmatched HI relocs. */
480 static struct mips_hi_fixup
*mips_hi_fixup_list
;
482 /* Map normal MIPS register numbers to mips16 register numbers. */
484 #define X ILLEGAL_REG
485 static const int mips32_to_16_reg_map
[] =
487 X
, X
, 2, 3, 4, 5, 6, 7,
488 X
, X
, X
, X
, X
, X
, X
, X
,
489 0, 1, X
, X
, X
, X
, X
, X
,
490 X
, X
, X
, X
, X
, X
, X
, X
494 /* Map mips16 register numbers to normal MIPS register numbers. */
496 static const int mips16_to_32_reg_map
[] =
498 16, 17, 2, 3, 4, 5, 6, 7
501 /* Since the MIPS does not have multiple forms of PC relative
502 instructions, we do not have to do relaxing as is done on other
503 platforms. However, we do have to handle GP relative addressing
504 correctly, which turns out to be a similar problem.
506 Every macro that refers to a symbol can occur in (at least) two
507 forms, one with GP relative addressing and one without. For
508 example, loading a global variable into a register generally uses
509 a macro instruction like this:
511 If i can be addressed off the GP register (this is true if it is in
512 the .sbss or .sdata section, or if it is known to be smaller than
513 the -G argument) this will generate the following instruction:
515 This instruction will use a GPREL reloc. If i can not be addressed
516 off the GP register, the following instruction sequence will be used:
519 In this case the first instruction will have a HI16 reloc, and the
520 second reloc will have a LO16 reloc. Both relocs will be against
523 The issue here is that we may not know whether i is GP addressable
524 until after we see the instruction that uses it. Therefore, we
525 want to be able to choose the final instruction sequence only at
526 the end of the assembly. This is similar to the way other
527 platforms choose the size of a PC relative instruction only at the
530 When generating position independent code we do not use GP
531 addressing in quite the same way, but the issue still arises as
532 external symbols and local symbols must be handled differently.
534 We handle these issues by actually generating both possible
535 instruction sequences. The longer one is put in a frag_var with
536 type rs_machine_dependent. We encode what to do with the frag in
537 the subtype field. We encode (1) the number of existing bytes to
538 replace, (2) the number of new bytes to use, (3) the offset from
539 the start of the existing bytes to the first reloc we must generate
540 (that is, the offset is applied from the start of the existing
541 bytes after they are replaced by the new bytes, if any), (4) the
542 offset from the start of the existing bytes to the second reloc,
543 (5) whether a third reloc is needed (the third reloc is always four
544 bytes after the second reloc), and (6) whether to warn if this
545 variant is used (this is sometimes needed if .set nomacro or .set
546 noat is in effect). All these numbers are reasonably small.
548 Generating two instruction sequences must be handled carefully to
549 ensure that delay slots are handled correctly. Fortunately, there
550 are a limited number of cases. When the second instruction
551 sequence is generated, append_insn is directed to maintain the
552 existing delay slot information, so it continues to apply to any
553 code after the second instruction sequence. This means that the
554 second instruction sequence must not impose any requirements not
555 required by the first instruction sequence.
557 These variant frags are then handled in functions called by the
558 machine independent code. md_estimate_size_before_relax returns
559 the final size of the frag. md_convert_frag sets up the final form
560 of the frag. tc_gen_reloc adjust the first reloc and adds a second
562 #define RELAX_ENCODE(old, new, reloc1, reloc2, reloc3, warn) \
566 | (((reloc1) + 64) << 9) \
567 | (((reloc2) + 64) << 2) \
568 | ((reloc3) ? (1 << 1) : 0) \
570 #define RELAX_OLD(i) (((i) >> 23) & 0x7f)
571 #define RELAX_NEW(i) (((i) >> 16) & 0x7f)
572 #define RELAX_RELOC1(i) ((bfd_vma)(((i) >> 9) & 0x7f) - 64)
573 #define RELAX_RELOC2(i) ((bfd_vma)(((i) >> 2) & 0x7f) - 64)
574 #define RELAX_RELOC3(i) (((i) >> 1) & 1)
575 #define RELAX_WARN(i) ((i) & 1)
577 /* For mips16 code, we use an entirely different form of relaxation.
578 mips16 supports two versions of most instructions which take
579 immediate values: a small one which takes some small value, and a
580 larger one which takes a 16 bit value. Since branches also follow
581 this pattern, relaxing these values is required.
583 We can assemble both mips16 and normal MIPS code in a single
584 object. Therefore, we need to support this type of relaxation at
585 the same time that we support the relaxation described above. We
586 use the high bit of the subtype field to distinguish these cases.
588 The information we store for this type of relaxation is the
589 argument code found in the opcode file for this relocation, whether
590 the user explicitly requested a small or extended form, and whether
591 the relocation is in a jump or jal delay slot. That tells us the
592 size of the value, and how it should be stored. We also store
593 whether the fragment is considered to be extended or not. We also
594 store whether this is known to be a branch to a different section,
595 whether we have tried to relax this frag yet, and whether we have
596 ever extended a PC relative fragment because of a shift count. */
597 #define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
600 | ((small) ? 0x100 : 0) \
601 | ((ext) ? 0x200 : 0) \
602 | ((dslot) ? 0x400 : 0) \
603 | ((jal_dslot) ? 0x800 : 0))
604 #define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
605 #define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
606 #define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
607 #define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
608 #define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
609 #define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
610 #define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
611 #define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
612 #define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
613 #define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
614 #define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
615 #define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
617 /* Prototypes for static functions. */
620 #define internalError() \
621 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
623 #define internalError() as_fatal (_("MIPS internal Error"));
626 enum mips_regclass
{ MIPS_GR_REG
, MIPS_FP_REG
, MIPS16_REG
};
628 static int insn_uses_reg
PARAMS ((struct mips_cl_insn
*ip
,
629 unsigned int reg
, enum mips_regclass
class));
630 static int reg_needs_delay
PARAMS ((int));
631 static void mips16_mark_labels
PARAMS ((void));
632 static void append_insn
PARAMS ((char *place
,
633 struct mips_cl_insn
* ip
,
635 bfd_reloc_code_real_type r
,
637 static void mips_no_prev_insn
PARAMS ((int));
638 static void mips_emit_delays
PARAMS ((boolean
));
640 static void macro_build
PARAMS ((char *place
, int *counter
, expressionS
* ep
,
641 const char *name
, const char *fmt
,
644 static void macro_build ();
646 static void mips16_macro_build
PARAMS ((char *, int *, expressionS
*,
647 const char *, const char *,
649 static void macro_build_lui
PARAMS ((char *place
, int *counter
,
650 expressionS
* ep
, int regnum
));
651 static void set_at
PARAMS ((int *counter
, int reg
, int unsignedp
));
652 static void check_absolute_expr
PARAMS ((struct mips_cl_insn
* ip
,
654 static void load_register
PARAMS ((int *, int, expressionS
*, int));
655 static void load_address
PARAMS ((int *counter
, int reg
, expressionS
*ep
));
656 static void macro
PARAMS ((struct mips_cl_insn
* ip
));
657 static void mips16_macro
PARAMS ((struct mips_cl_insn
* ip
));
658 #ifdef LOSING_COMPILER
659 static void macro2
PARAMS ((struct mips_cl_insn
* ip
));
661 static void mips_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
662 static void mips16_ip
PARAMS ((char *str
, struct mips_cl_insn
* ip
));
663 static void mips16_immed
PARAMS ((char *, unsigned int, int, offsetT
, boolean
,
664 boolean
, boolean
, unsigned long *,
665 boolean
*, unsigned short *));
666 static int my_getSmallExpression
PARAMS ((expressionS
* ep
, char *str
));
667 static void my_getExpression
PARAMS ((expressionS
* ep
, char *str
));
668 static symbolS
*get_symbol
PARAMS ((void));
669 static void mips_align
PARAMS ((int to
, int fill
, symbolS
*label
));
670 static void s_align
PARAMS ((int));
671 static void s_change_sec
PARAMS ((int));
672 static void s_cons
PARAMS ((int));
673 static void s_float_cons
PARAMS ((int));
674 static void s_mips_globl
PARAMS ((int));
675 static void s_option
PARAMS ((int));
676 static void s_mipsset
PARAMS ((int));
677 static void s_abicalls
PARAMS ((int));
678 static void s_cpload
PARAMS ((int));
679 static void s_cprestore
PARAMS ((int));
680 static void s_gpword
PARAMS ((int));
681 static void s_cpadd
PARAMS ((int));
682 static void s_insn
PARAMS ((int));
683 static void md_obj_begin
PARAMS ((void));
684 static void md_obj_end
PARAMS ((void));
685 static long get_number
PARAMS ((void));
686 static void s_mips_ent
PARAMS ((int));
687 static void s_mips_end
PARAMS ((int));
688 static void s_mips_frame
PARAMS ((int));
689 static void s_mips_mask
PARAMS ((int));
690 static void s_mips_stab
PARAMS ((int));
691 static void s_mips_weakext
PARAMS ((int));
692 static void s_file
PARAMS ((int));
693 static int mips16_extended_frag
PARAMS ((fragS
*, asection
*, long));
696 static int validate_mips_insn
PARAMS ((const struct mips_opcode
*));
700 The following pseudo-ops from the Kane and Heinrich MIPS book
701 should be defined here, but are currently unsupported: .alias,
702 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
704 The following pseudo-ops from the Kane and Heinrich MIPS book are
705 specific to the type of debugging information being generated, and
706 should be defined by the object format: .aent, .begin, .bend,
707 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
710 The following pseudo-ops from the Kane and Heinrich MIPS book are
711 not MIPS CPU specific, but are also not specific to the object file
712 format. This file is probably the best place to define them, but
713 they are not currently supported: .asm0, .endr, .lab, .repeat,
716 static const pseudo_typeS mips_pseudo_table
[] =
718 /* MIPS specific pseudo-ops. */
719 {"option", s_option
, 0},
720 {"set", s_mipsset
, 0},
721 {"rdata", s_change_sec
, 'r'},
722 {"sdata", s_change_sec
, 's'},
723 {"livereg", s_ignore
, 0},
724 {"abicalls", s_abicalls
, 0},
725 {"cpload", s_cpload
, 0},
726 {"cprestore", s_cprestore
, 0},
727 {"gpword", s_gpword
, 0},
728 {"cpadd", s_cpadd
, 0},
731 /* Relatively generic pseudo-ops that happen to be used on MIPS
733 {"asciiz", stringer
, 1},
734 {"bss", s_change_sec
, 'b'},
737 {"dword", s_cons
, 3},
738 {"weakext", s_mips_weakext
, 0},
740 /* These pseudo-ops are defined in read.c, but must be overridden
741 here for one reason or another. */
742 {"align", s_align
, 0},
744 {"data", s_change_sec
, 'd'},
745 {"double", s_float_cons
, 'd'},
746 {"float", s_float_cons
, 'f'},
747 {"globl", s_mips_globl
, 0},
748 {"global", s_mips_globl
, 0},
749 {"hword", s_cons
, 1},
754 {"short", s_cons
, 1},
755 {"single", s_float_cons
, 'f'},
756 {"stabn", s_mips_stab
, 'n'},
757 {"text", s_change_sec
, 't'},
762 static const pseudo_typeS mips_nonecoff_pseudo_table
[] = {
763 /* These pseudo-ops should be defined by the object file format.
764 However, a.out doesn't support them, so we have versions here. */
765 {"aent", s_mips_ent
, 1},
766 {"bgnb", s_ignore
, 0},
767 {"end", s_mips_end
, 0},
768 {"endb", s_ignore
, 0},
769 {"ent", s_mips_ent
, 0},
771 {"fmask", s_mips_mask
, 'F'},
772 {"frame", s_mips_frame
, 0},
773 {"loc", s_ignore
, 0},
774 {"mask", s_mips_mask
, 'R'},
775 {"verstamp", s_ignore
, 0},
779 extern void pop_insert
PARAMS ((const pseudo_typeS
*));
784 pop_insert (mips_pseudo_table
);
785 if (! ECOFF_DEBUGGING
)
786 pop_insert (mips_nonecoff_pseudo_table
);
789 /* Symbols labelling the current insn. */
791 struct insn_label_list
793 struct insn_label_list
*next
;
797 static struct insn_label_list
*insn_labels
;
798 static struct insn_label_list
*free_insn_labels
;
800 static void mips_clear_insn_labels
PARAMS ((void));
803 mips_clear_insn_labels ()
805 register struct insn_label_list
**pl
;
807 for (pl
= &free_insn_labels
; *pl
!= NULL
; pl
= &(*pl
)->next
)
813 static char *expr_end
;
815 /* Expressions which appear in instructions. These are set by
818 static expressionS imm_expr
;
819 static expressionS offset_expr
;
821 /* Relocs associated with imm_expr and offset_expr. */
823 static bfd_reloc_code_real_type imm_reloc
;
824 static bfd_reloc_code_real_type offset_reloc
;
826 /* This is set by mips_ip if imm_reloc is an unmatched HI16_S reloc. */
828 static boolean imm_unmatched_hi
;
830 /* These are set by mips16_ip if an explicit extension is used. */
832 static boolean mips16_small
, mips16_ext
;
834 #ifdef MIPS_STABS_ELF
835 /* The pdr segment for per procedure frame/regmask info */
841 * This function is called once, at assembler startup time. It should
842 * set up all the tables, etc. that the MD part of the assembler will need.
848 register const char *retval
= NULL
;
849 register unsigned int i
= 0;
853 int mips_isa_from_cpu
;
855 /* GP relative stuff not working for PE */
856 if (strncmp (TARGET_OS
, "pe", 2) == 0
857 && g_switch_value
!= 0)
860 as_bad (_("-G not supported in this configuration."));
865 if (strcmp (cpu
+ (sizeof TARGET_CPU
) - 3, "el") == 0)
867 a
= xmalloc (sizeof TARGET_CPU
);
868 strcpy (a
, TARGET_CPU
);
869 a
[(sizeof TARGET_CPU
) - 3] = '\0';
875 /* Set mips_cpu based on TARGET_CPU, unless TARGET_CPU is
876 just the generic 'mips', in which case set mips_cpu based
877 on the given ISA, if any. */
879 if (strcmp (cpu
, "mips") == 0)
881 if (mips_opts
.isa
< 0)
884 else if (mips_opts
.isa
== 2)
887 else if (mips_opts
.isa
== 3)
890 else if (mips_opts
.isa
== 4)
897 else if (strcmp (cpu
, "r3900") == 0
898 || strcmp (cpu
, "mipstx39") == 0
902 else if (strcmp (cpu
, "r6000") == 0
903 || strcmp (cpu
, "mips2") == 0)
906 else if (strcmp (cpu
, "mips64") == 0
907 || strcmp (cpu
, "r4000") == 0
908 || strcmp (cpu
, "mips3") == 0)
911 else if (strcmp (cpu
, "r4400") == 0)
914 else if (strcmp (cpu
, "mips64orion") == 0
915 || strcmp (cpu
, "r4600") == 0)
918 else if (strcmp (cpu
, "r4650") == 0)
921 else if (strcmp (cpu
, "mips64vr4300") == 0)
924 else if (strcmp (cpu
, "mips64vr4111") == 0)
927 else if (strcmp (cpu
, "mips64vr4100") == 0)
930 else if (strcmp (cpu
, "r4010") == 0)
934 else if (strcmp (cpu
, "r5000") == 0
935 || strcmp (cpu
, "mips64vr5000") == 0)
940 else if (strcmp (cpu
, "r8000") == 0
941 || strcmp (cpu
, "mips4") == 0)
944 else if (strcmp (cpu
, "r10000") == 0)
947 else if (strcmp (cpu
, "mips16") == 0)
948 mips_cpu
= 0; /* FIXME */
956 mips_isa_from_cpu
= 1;
958 else if (mips_cpu
== 6000
960 mips_isa_from_cpu
= 2;
962 else if (mips_cpu
== 4000
969 mips_isa_from_cpu
= 3;
971 else if (mips_cpu
== 5000
973 || mips_cpu
== 10000)
974 mips_isa_from_cpu
= 4;
977 mips_isa_from_cpu
= -1;
979 if (mips_opts
.isa
== -1)
981 if (mips_isa_from_cpu
!= -1)
982 mips_opts
.isa
= mips_isa_from_cpu
;
987 if (mips_opts
.mips16
< 0)
989 if (strncmp (TARGET_CPU
, "mips16", sizeof "mips16" - 1) == 0)
990 mips_opts
.mips16
= 1;
992 mips_opts
.mips16
= 0;
995 /* End of TARGET_CPU processing, get rid of malloced memory
1004 if (mips_opts
.isa
== 1 && mips_trap
)
1005 as_bad (_("trap exception not supported at ISA 1"));
1007 /* Set the EABI kind based on the ISA before the user gets
1008 to change the ISA with directives. This isn't really
1009 the best, but then neither is basing the abi on the isa. */
1010 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1012 && 0 == strcmp (mips_abi_string
,"eabi"))
1015 if (mips_cpu
!= 0 && mips_cpu
!= -1)
1017 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, mips_cpu
);
1019 /* If they asked for mips1 or mips2 and a cpu that is
1020 mips3 or greater, then mark the object file 32BITMODE. */
1021 if (mips_isa_from_cpu
!= -1
1022 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
1023 && ISA_HAS_64BIT_REGS (mips_isa_from_cpu
))
1028 switch (mips_opts
.isa
)
1031 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 3000);
1034 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 6000);
1037 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 4000);
1040 ok
= bfd_set_arch_mach (stdoutput
, bfd_arch_mips
, 8000);
1046 as_warn (_("Could not set architecture and machine"));
1048 file_mips_isa
= mips_opts
.isa
;
1050 op_hash
= hash_new ();
1052 for (i
= 0; i
< NUMOPCODES
;)
1054 const char *name
= mips_opcodes
[i
].name
;
1056 retval
= hash_insert (op_hash
, name
, (PTR
) &mips_opcodes
[i
]);
1059 fprintf (stderr
, _("internal error: can't hash `%s': %s\n"),
1060 mips_opcodes
[i
].name
, retval
);
1061 /* Probably a memory allocation problem? Give up now. */
1062 as_fatal (_("Broken assembler. No assembly attempted."));
1066 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
)
1068 if (!validate_mips_insn (&mips_opcodes
[i
]))
1073 while ((i
< NUMOPCODES
) && !strcmp (mips_opcodes
[i
].name
, name
));
1076 mips16_op_hash
= hash_new ();
1079 while (i
< bfd_mips16_num_opcodes
)
1081 const char *name
= mips16_opcodes
[i
].name
;
1083 retval
= hash_insert (mips16_op_hash
, name
, (PTR
) &mips16_opcodes
[i
]);
1085 as_fatal (_("internal: can't hash `%s': %s"),
1086 mips16_opcodes
[i
].name
, retval
);
1089 if (mips16_opcodes
[i
].pinfo
!= INSN_MACRO
1090 && ((mips16_opcodes
[i
].match
& mips16_opcodes
[i
].mask
)
1091 != mips16_opcodes
[i
].match
))
1093 fprintf (stderr
, _("internal error: bad mips16 opcode: %s %s\n"),
1094 mips16_opcodes
[i
].name
, mips16_opcodes
[i
].args
);
1099 while (i
< bfd_mips16_num_opcodes
1100 && strcmp (mips16_opcodes
[i
].name
, name
) == 0);
1104 as_fatal (_("Broken assembler. No assembly attempted."));
1106 /* We add all the general register names to the symbol table. This
1107 helps us detect invalid uses of them. */
1108 for (i
= 0; i
< 32; i
++)
1112 sprintf (buf
, "$%d", i
);
1113 symbol_table_insert (symbol_new (buf
, reg_section
, i
,
1114 &zero_address_frag
));
1116 symbol_table_insert (symbol_new ("$fp", reg_section
, FP
,
1117 &zero_address_frag
));
1118 symbol_table_insert (symbol_new ("$sp", reg_section
, SP
,
1119 &zero_address_frag
));
1120 symbol_table_insert (symbol_new ("$gp", reg_section
, GP
,
1121 &zero_address_frag
));
1122 symbol_table_insert (symbol_new ("$at", reg_section
, AT
,
1123 &zero_address_frag
));
1124 symbol_table_insert (symbol_new ("$kt0", reg_section
, KT0
,
1125 &zero_address_frag
));
1126 symbol_table_insert (symbol_new ("$kt1", reg_section
, KT1
,
1127 &zero_address_frag
));
1128 symbol_table_insert (symbol_new ("$pc", reg_section
, -1,
1129 &zero_address_frag
));
1131 mips_no_prev_insn (false);
1134 mips_cprmask
[0] = 0;
1135 mips_cprmask
[1] = 0;
1136 mips_cprmask
[2] = 0;
1137 mips_cprmask
[3] = 0;
1139 /* set the default alignment for the text section (2**2) */
1140 record_alignment (text_section
, 2);
1142 if (USE_GLOBAL_POINTER_OPT
)
1143 bfd_set_gp_size (stdoutput
, g_switch_value
);
1145 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1147 /* On a native system, sections must be aligned to 16 byte
1148 boundaries. When configured for an embedded ELF target, we
1150 if (strcmp (TARGET_OS
, "elf") != 0)
1152 (void) bfd_set_section_alignment (stdoutput
, text_section
, 4);
1153 (void) bfd_set_section_alignment (stdoutput
, data_section
, 4);
1154 (void) bfd_set_section_alignment (stdoutput
, bss_section
, 4);
1157 /* Create a .reginfo section for register masks and a .mdebug
1158 section for debugging information. */
1166 subseg
= now_subseg
;
1168 /* The ABI says this section should be loaded so that the
1169 running program can access it. However, we don't load it
1170 if we are configured for an embedded target */
1171 flags
= SEC_READONLY
| SEC_DATA
;
1172 if (strcmp (TARGET_OS
, "elf") != 0)
1173 flags
|= SEC_ALLOC
| SEC_LOAD
;
1177 sec
= subseg_new (".reginfo", (subsegT
) 0);
1180 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1181 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1184 mips_regmask_frag
= frag_more (sizeof (Elf32_External_RegInfo
));
1189 /* The 64-bit ABI uses a .MIPS.options section rather than
1190 .reginfo section. */
1191 sec
= subseg_new (".MIPS.options", (subsegT
) 0);
1192 (void) bfd_set_section_flags (stdoutput
, sec
, flags
);
1193 (void) bfd_set_section_alignment (stdoutput
, sec
, 3);
1196 /* Set up the option header. */
1198 Elf_Internal_Options opthdr
;
1201 opthdr
.kind
= ODK_REGINFO
;
1202 opthdr
.size
= (sizeof (Elf_External_Options
)
1203 + sizeof (Elf64_External_RegInfo
));
1206 f
= frag_more (sizeof (Elf_External_Options
));
1207 bfd_mips_elf_swap_options_out (stdoutput
, &opthdr
,
1208 (Elf_External_Options
*) f
);
1210 mips_regmask_frag
= frag_more (sizeof (Elf64_External_RegInfo
));
1215 if (ECOFF_DEBUGGING
)
1217 sec
= subseg_new (".mdebug", (subsegT
) 0);
1218 (void) bfd_set_section_flags (stdoutput
, sec
,
1219 SEC_HAS_CONTENTS
| SEC_READONLY
);
1220 (void) bfd_set_section_alignment (stdoutput
, sec
, 2);
1223 #ifdef MIPS_STABS_ELF
1224 pdr_seg
= subseg_new (".pdr", (subsegT
) 0);
1225 (void) bfd_set_section_flags (stdoutput
, pdr_seg
,
1226 SEC_READONLY
| SEC_RELOC
| SEC_DEBUGGING
);
1227 (void) bfd_set_section_alignment (stdoutput
, pdr_seg
, 2);
1230 subseg_set (seg
, subseg
);
1234 if (! ECOFF_DEBUGGING
)
1241 if (! ECOFF_DEBUGGING
)
1249 struct mips_cl_insn insn
;
1251 imm_expr
.X_op
= O_absent
;
1252 imm_reloc
= BFD_RELOC_UNUSED
;
1253 imm_unmatched_hi
= false;
1254 offset_expr
.X_op
= O_absent
;
1255 offset_reloc
= BFD_RELOC_UNUSED
;
1257 if (mips_opts
.mips16
)
1258 mips16_ip (str
, &insn
);
1261 mips_ip (str
, &insn
);
1262 DBG((_("returned from mips_ip(%s) insn_opcode = 0x%x\n"),
1263 str
, insn
.insn_opcode
));
1268 as_bad ("%s `%s'", insn_error
, str
);
1272 if (insn
.insn_mo
->pinfo
== INSN_MACRO
)
1274 if (mips_opts
.mips16
)
1275 mips16_macro (&insn
);
1281 if (imm_expr
.X_op
!= O_absent
)
1282 append_insn ((char *) NULL
, &insn
, &imm_expr
, imm_reloc
,
1284 else if (offset_expr
.X_op
!= O_absent
)
1285 append_insn ((char *) NULL
, &insn
, &offset_expr
, offset_reloc
, false);
1287 append_insn ((char *) NULL
, &insn
, NULL
, BFD_RELOC_UNUSED
, false);
1291 /* See whether instruction IP reads register REG. CLASS is the type
1295 insn_uses_reg (ip
, reg
, class)
1296 struct mips_cl_insn
*ip
;
1298 enum mips_regclass
class;
1300 if (class == MIPS16_REG
)
1302 assert (mips_opts
.mips16
);
1303 reg
= mips16_to_32_reg_map
[reg
];
1304 class = MIPS_GR_REG
;
1307 /* Don't report on general register 0, since it never changes. */
1308 if (class == MIPS_GR_REG
&& reg
== 0)
1311 if (class == MIPS_FP_REG
)
1313 assert (! mips_opts
.mips16
);
1314 /* If we are called with either $f0 or $f1, we must check $f0.
1315 This is not optimal, because it will introduce an unnecessary
1316 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1317 need to distinguish reading both $f0 and $f1 or just one of
1318 them. Note that we don't have to check the other way,
1319 because there is no instruction that sets both $f0 and $f1
1320 and requires a delay. */
1321 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_S
)
1322 && ((((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
) &~(unsigned)1)
1323 == (reg
&~ (unsigned) 1)))
1325 if ((ip
->insn_mo
->pinfo
& INSN_READ_FPR_T
)
1326 && ((((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
) &~(unsigned)1)
1327 == (reg
&~ (unsigned) 1)))
1330 else if (! mips_opts
.mips16
)
1332 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_S
)
1333 && ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
) == reg
)
1335 if ((ip
->insn_mo
->pinfo
& INSN_READ_GPR_T
)
1336 && ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
) == reg
)
1341 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_X
)
1342 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1343 & MIPS16OP_MASK_RX
)]
1346 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Y
)
1347 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1348 & MIPS16OP_MASK_RY
)]
1351 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_Z
)
1352 && (mips16_to_32_reg_map
[((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1353 & MIPS16OP_MASK_MOVE32Z
)]
1356 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_T
) && reg
== TREG
)
1358 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_SP
) && reg
== SP
)
1360 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_31
) && reg
== RA
)
1362 if ((ip
->insn_mo
->pinfo
& MIPS16_INSN_READ_GPR_X
)
1363 && ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1364 & MIPS16OP_MASK_REGR32
) == reg
)
1371 /* This function returns true if modifying a register requires a
1375 reg_needs_delay (reg
)
1378 unsigned long prev_pinfo
;
1380 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1381 if (! mips_opts
.noreorder
1382 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1383 && ((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1384 || (! gpr_interlocks
1385 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1387 /* A load from a coprocessor or from memory. All load
1388 delays delay the use of general register rt for one
1389 instruction on the r3000. The r6000 and r4000 use
1391 /* Itbl support may require additional care here. */
1392 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1393 if (reg
== ((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
))
1400 /* Mark instruction labels in mips16 mode. This permits the linker to
1401 handle them specially, such as generating jalx instructions when
1402 needed. We also make them odd for the duration of the assembly, in
1403 order to generate the right sort of code. We will make them even
1404 in the adjust_symtab routine, while leaving them marked. This is
1405 convenient for the debugger and the disassembler. The linker knows
1406 to make them odd again. */
1409 mips16_mark_labels ()
1411 if (mips_opts
.mips16
)
1413 struct insn_label_list
*l
;
1415 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1418 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
1419 S_SET_OTHER (l
->label
, STO_MIPS16
);
1421 if ((S_GET_VALUE (l
->label
) & 1) == 0)
1422 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1427 /* Output an instruction. PLACE is where to put the instruction; if
1428 it is NULL, this uses frag_more to get room. IP is the instruction
1429 information. ADDRESS_EXPR is an operand of the instruction to be
1430 used with RELOC_TYPE. */
1433 append_insn (place
, ip
, address_expr
, reloc_type
, unmatched_hi
)
1435 struct mips_cl_insn
*ip
;
1436 expressionS
*address_expr
;
1437 bfd_reloc_code_real_type reloc_type
;
1438 boolean unmatched_hi
;
1440 register unsigned long prev_pinfo
, pinfo
;
1445 /* Mark instruction labels in mips16 mode. */
1446 if (mips_opts
.mips16
)
1447 mips16_mark_labels ();
1449 prev_pinfo
= prev_insn
.insn_mo
->pinfo
;
1450 pinfo
= ip
->insn_mo
->pinfo
;
1452 if (place
== NULL
&& (! mips_opts
.noreorder
|| prev_nop_frag
!= NULL
))
1456 /* If the previous insn required any delay slots, see if we need
1457 to insert a NOP or two. There are eight kinds of possible
1458 hazards, of which an instruction can have at most one type.
1459 (1) a load from memory delay
1460 (2) a load from a coprocessor delay
1461 (3) an unconditional branch delay
1462 (4) a conditional branch delay
1463 (5) a move to coprocessor register delay
1464 (6) a load coprocessor register from memory delay
1465 (7) a coprocessor condition code delay
1466 (8) a HI/LO special register delay
1468 There are a lot of optimizations we could do that we don't.
1469 In particular, we do not, in general, reorder instructions.
1470 If you use gcc with optimization, it will reorder
1471 instructions and generally do much more optimization then we
1472 do here; repeating all that work in the assembler would only
1473 benefit hand written assembly code, and does not seem worth
1476 /* This is how a NOP is emitted. */
1477 #define emit_nop() \
1479 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1480 : md_number_to_chars (frag_more (4), 0, 4))
1482 /* The previous insn might require a delay slot, depending upon
1483 the contents of the current insn. */
1484 if (! mips_opts
.mips16
1485 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1486 && (((prev_pinfo
& INSN_LOAD_COPROC_DELAY
)
1487 && ! cop_interlocks
)
1488 || (! gpr_interlocks
1489 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))))
1491 /* A load from a coprocessor or from memory. All load
1492 delays delay the use of general register rt for one
1493 instruction on the r3000. The r6000 and r4000 use
1495 /* Itbl support may require additional care here. */
1496 know (prev_pinfo
& INSN_WRITE_GPR_T
);
1497 if (mips_optimize
== 0
1498 || insn_uses_reg (ip
,
1499 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
1504 else if (! mips_opts
.mips16
1505 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1506 && (((prev_pinfo
& INSN_COPROC_MOVE_DELAY
)
1507 && ! cop_interlocks
)
1508 || (mips_opts
.isa
== 1
1509 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))))
1511 /* A generic coprocessor delay. The previous instruction
1512 modified a coprocessor general or control register. If
1513 it modified a control register, we need to avoid any
1514 coprocessor instruction (this is probably not always
1515 required, but it sometimes is). If it modified a general
1516 register, we avoid using that register.
1518 On the r6000 and r4000 loading a coprocessor register
1519 from memory is interlocked, and does not require a delay.
1521 This case is not handled very well. There is no special
1522 knowledge of CP0 handling, and the coprocessors other
1523 than the floating point unit are not distinguished at
1525 /* Itbl support may require additional care here. FIXME!
1526 Need to modify this to include knowledge about
1527 user specified delays! */
1528 if (prev_pinfo
& INSN_WRITE_FPR_T
)
1530 if (mips_optimize
== 0
1531 || insn_uses_reg (ip
,
1532 ((prev_insn
.insn_opcode
>> OP_SH_FT
)
1537 else if (prev_pinfo
& INSN_WRITE_FPR_S
)
1539 if (mips_optimize
== 0
1540 || insn_uses_reg (ip
,
1541 ((prev_insn
.insn_opcode
>> OP_SH_FS
)
1548 /* We don't know exactly what the previous instruction
1549 does. If the current instruction uses a coprocessor
1550 register, we must insert a NOP. If previous
1551 instruction may set the condition codes, and the
1552 current instruction uses them, we must insert two
1554 /* Itbl support may require additional care here. */
1555 if (mips_optimize
== 0
1556 || ((prev_pinfo
& INSN_WRITE_COND_CODE
)
1557 && (pinfo
& INSN_READ_COND_CODE
)))
1559 else if (pinfo
& INSN_COP
)
1563 else if (! mips_opts
.mips16
1564 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1565 && (prev_pinfo
& INSN_WRITE_COND_CODE
)
1566 && ! cop_interlocks
)
1568 /* The previous instruction sets the coprocessor condition
1569 codes, but does not require a general coprocessor delay
1570 (this means it is a floating point comparison
1571 instruction). If this instruction uses the condition
1572 codes, we need to insert a single NOP. */
1573 /* Itbl support may require additional care here. */
1574 if (mips_optimize
== 0
1575 || (pinfo
& INSN_READ_COND_CODE
))
1579 /* If we're fixing up mfhi/mflo for the r7000 and the
1580 previous insn was an mfhi/mflo and the current insn
1581 reads the register that the mfhi/mflo wrote to, then
1584 else if (mips_7000_hilo_fix
1585 && MF_HILO_INSN (prev_pinfo
)
1586 && insn_uses_reg (ip
, ((prev_insn
.insn_opcode
>> OP_SH_RD
)
1594 /* If we're fixing up mfhi/mflo for the r7000 and the
1595 2nd previous insn was an mfhi/mflo and the current insn
1596 reads the register that the mfhi/mflo wrote to, then
1599 else if (mips_7000_hilo_fix
1600 && MF_HILO_INSN (prev_prev_insn
.insn_opcode
)
1601 && insn_uses_reg (ip
, ((prev_prev_insn
.insn_opcode
>> OP_SH_RD
)
1609 else if (prev_pinfo
& INSN_READ_LO
)
1611 /* The previous instruction reads the LO register; if the
1612 current instruction writes to the LO register, we must
1613 insert two NOPS. Some newer processors have interlocks.
1614 Also the tx39's multiply instructions can be exectuted
1615 immediatly after a read from HI/LO (without the delay),
1616 though the tx39's divide insns still do require the
1618 if (! (hilo_interlocks
1619 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1620 && (mips_optimize
== 0
1621 || (pinfo
& INSN_WRITE_LO
)))
1623 /* Most mips16 branch insns don't have a delay slot.
1624 If a read from LO is immediately followed by a branch
1625 to a write to LO we have a read followed by a write
1626 less than 2 insns away. We assume the target of
1627 a branch might be a write to LO, and insert a nop
1628 between a read and an immediately following branch. */
1629 else if (mips_opts
.mips16
1630 && (mips_optimize
== 0
1631 || (pinfo
& MIPS16_INSN_BRANCH
)))
1634 else if (prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1636 /* The previous instruction reads the HI register; if the
1637 current instruction writes to the HI register, we must
1638 insert a NOP. Some newer processors have interlocks.
1639 Also the note tx39's multiply above. */
1640 if (! (hilo_interlocks
1641 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
1642 && (mips_optimize
== 0
1643 || (pinfo
& INSN_WRITE_HI
)))
1645 /* Most mips16 branch insns don't have a delay slot.
1646 If a read from HI is immediately followed by a branch
1647 to a write to HI we have a read followed by a write
1648 less than 2 insns away. We assume the target of
1649 a branch might be a write to HI, and insert a nop
1650 between a read and an immediately following branch. */
1651 else if (mips_opts
.mips16
1652 && (mips_optimize
== 0
1653 || (pinfo
& MIPS16_INSN_BRANCH
)))
1657 /* If the previous instruction was in a noreorder section, then
1658 we don't want to insert the nop after all. */
1659 /* Itbl support may require additional care here. */
1660 if (prev_insn_unreordered
)
1663 /* There are two cases which require two intervening
1664 instructions: 1) setting the condition codes using a move to
1665 coprocessor instruction which requires a general coprocessor
1666 delay and then reading the condition codes 2) reading the HI
1667 or LO register and then writing to it (except on processors
1668 which have interlocks). If we are not already emitting a NOP
1669 instruction, we must check for these cases compared to the
1670 instruction previous to the previous instruction. */
1671 if ((! mips_opts
.mips16
1672 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
1673 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_COPROC_MOVE_DELAY
)
1674 && (prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
)
1675 && (pinfo
& INSN_READ_COND_CODE
)
1676 && ! cop_interlocks
)
1677 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
)
1678 && (pinfo
& INSN_WRITE_LO
)
1679 && ! (hilo_interlocks
1680 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
))))
1681 || ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
1682 && (pinfo
& INSN_WRITE_HI
)
1683 && ! (hilo_interlocks
1684 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))))
1689 if (prev_prev_insn_unreordered
)
1692 if (prev_prev_nop
&& nops
== 0)
1695 /* If we are being given a nop instruction, don't bother with
1696 one of the nops we would otherwise output. This will only
1697 happen when a nop instruction is used with mips_optimize set
1700 && ! mips_opts
.noreorder
1701 && ip
->insn_opcode
== (mips_opts
.mips16
? 0x6500 : 0))
1704 /* Now emit the right number of NOP instructions. */
1705 if (nops
> 0 && ! mips_opts
.noreorder
)
1708 unsigned long old_frag_offset
;
1710 struct insn_label_list
*l
;
1712 old_frag
= frag_now
;
1713 old_frag_offset
= frag_now_fix ();
1715 for (i
= 0; i
< nops
; i
++)
1720 listing_prev_line ();
1721 /* We may be at the start of a variant frag. In case we
1722 are, make sure there is enough space for the frag
1723 after the frags created by listing_prev_line. The
1724 argument to frag_grow here must be at least as large
1725 as the argument to all other calls to frag_grow in
1726 this file. We don't have to worry about being in the
1727 middle of a variant frag, because the variants insert
1728 all needed nop instructions themselves. */
1732 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
1734 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
1735 symbol_set_frag (l
->label
, frag_now
);
1736 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
1737 /* mips16 text labels are stored as odd. */
1738 if (mips_opts
.mips16
)
1739 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
1742 #ifndef NO_ECOFF_DEBUGGING
1743 if (ECOFF_DEBUGGING
)
1744 ecoff_fix_loc (old_frag
, old_frag_offset
);
1747 else if (prev_nop_frag
!= NULL
)
1749 /* We have a frag holding nops we may be able to remove. If
1750 we don't need any nops, we can decrease the size of
1751 prev_nop_frag by the size of one instruction. If we do
1752 need some nops, we count them in prev_nops_required. */
1753 if (prev_nop_frag_since
== 0)
1757 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1758 --prev_nop_frag_holds
;
1761 prev_nop_frag_required
+= nops
;
1765 if (prev_prev_nop
== 0)
1767 prev_nop_frag
->fr_fix
-= mips_opts
.mips16
? 2 : 4;
1768 --prev_nop_frag_holds
;
1771 ++prev_nop_frag_required
;
1774 if (prev_nop_frag_holds
<= prev_nop_frag_required
)
1775 prev_nop_frag
= NULL
;
1777 ++prev_nop_frag_since
;
1779 /* Sanity check: by the time we reach the second instruction
1780 after prev_nop_frag, we should have used up all the nops
1781 one way or another. */
1782 assert (prev_nop_frag_since
<= 1 || prev_nop_frag
== NULL
);
1786 if (reloc_type
> BFD_RELOC_UNUSED
)
1788 /* We need to set up a variant frag. */
1789 assert (mips_opts
.mips16
&& address_expr
!= NULL
);
1790 f
= frag_var (rs_machine_dependent
, 4, 0,
1791 RELAX_MIPS16_ENCODE (reloc_type
- BFD_RELOC_UNUSED
,
1792 mips16_small
, mips16_ext
,
1794 & INSN_UNCOND_BRANCH_DELAY
),
1795 (prev_insn_reloc_type
1796 == BFD_RELOC_MIPS16_JMP
)),
1797 make_expr_symbol (address_expr
), (offsetT
) 0,
1800 else if (place
!= NULL
)
1802 else if (mips_opts
.mips16
1804 && reloc_type
!= BFD_RELOC_MIPS16_JMP
)
1806 /* Make sure there is enough room to swap this instruction with
1807 a following jump instruction. */
1813 if (mips_opts
.mips16
1814 && mips_opts
.noreorder
1815 && (prev_pinfo
& INSN_UNCOND_BRANCH_DELAY
) != 0)
1816 as_warn (_("extended instruction in delay slot"));
1822 if (address_expr
!= NULL
&& reloc_type
< BFD_RELOC_UNUSED
)
1824 if (address_expr
->X_op
== O_constant
)
1829 ip
->insn_opcode
|= address_expr
->X_add_number
;
1832 case BFD_RELOC_LO16
:
1833 ip
->insn_opcode
|= address_expr
->X_add_number
& 0xffff;
1836 case BFD_RELOC_MIPS_JMP
:
1837 if ((address_expr
->X_add_number
& 3) != 0)
1838 as_bad (_("jump to misaligned address (0x%lx)"),
1839 (unsigned long) address_expr
->X_add_number
);
1840 ip
->insn_opcode
|= (address_expr
->X_add_number
>> 2) & 0x3ffffff;
1843 case BFD_RELOC_MIPS16_JMP
:
1844 if ((address_expr
->X_add_number
& 3) != 0)
1845 as_bad (_("jump to misaligned address (0x%lx)"),
1846 (unsigned long) address_expr
->X_add_number
);
1848 (((address_expr
->X_add_number
& 0x7c0000) << 3)
1849 | ((address_expr
->X_add_number
& 0xf800000) >> 7)
1850 | ((address_expr
->X_add_number
& 0x3fffc) >> 2));
1854 case BFD_RELOC_16_PCREL_S2
:
1864 /* Don't generate a reloc if we are writing into a variant
1868 fixp
= fix_new_exp (frag_now
, f
- frag_now
->fr_literal
, 4,
1870 reloc_type
== BFD_RELOC_16_PCREL_S2
,
1874 struct mips_hi_fixup
*hi_fixup
;
1876 assert (reloc_type
== BFD_RELOC_HI16_S
);
1877 hi_fixup
= ((struct mips_hi_fixup
*)
1878 xmalloc (sizeof (struct mips_hi_fixup
)));
1879 hi_fixup
->fixp
= fixp
;
1880 hi_fixup
->seg
= now_seg
;
1881 hi_fixup
->next
= mips_hi_fixup_list
;
1882 mips_hi_fixup_list
= hi_fixup
;
1888 if (! mips_opts
.mips16
)
1889 md_number_to_chars (f
, ip
->insn_opcode
, 4);
1890 else if (reloc_type
== BFD_RELOC_MIPS16_JMP
)
1892 md_number_to_chars (f
, ip
->insn_opcode
>> 16, 2);
1893 md_number_to_chars (f
+ 2, ip
->insn_opcode
& 0xffff, 2);
1899 md_number_to_chars (f
, 0xf000 | ip
->extend
, 2);
1902 md_number_to_chars (f
, ip
->insn_opcode
, 2);
1905 /* Update the register mask information. */
1906 if (! mips_opts
.mips16
)
1908 if (pinfo
& INSN_WRITE_GPR_D
)
1909 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
);
1910 if ((pinfo
& (INSN_WRITE_GPR_T
| INSN_READ_GPR_T
)) != 0)
1911 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
);
1912 if (pinfo
& INSN_READ_GPR_S
)
1913 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> OP_SH_RS
) & OP_MASK_RS
);
1914 if (pinfo
& INSN_WRITE_GPR_31
)
1915 mips_gprmask
|= 1 << 31;
1916 if (pinfo
& INSN_WRITE_FPR_D
)
1917 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FD
) & OP_MASK_FD
);
1918 if ((pinfo
& (INSN_WRITE_FPR_S
| INSN_READ_FPR_S
)) != 0)
1919 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FS
) & OP_MASK_FS
);
1920 if ((pinfo
& (INSN_WRITE_FPR_T
| INSN_READ_FPR_T
)) != 0)
1921 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FT
) & OP_MASK_FT
);
1922 if ((pinfo
& INSN_READ_FPR_R
) != 0)
1923 mips_cprmask
[1] |= 1 << ((ip
->insn_opcode
>> OP_SH_FR
) & OP_MASK_FR
);
1924 if (pinfo
& INSN_COP
)
1926 /* We don't keep enough information to sort these cases out.
1927 The itbl support does keep this information however, although
1928 we currently don't support itbl fprmats as part of the cop
1929 instruction. May want to add this support in the future. */
1931 /* Never set the bit for $0, which is always zero. */
1932 mips_gprmask
&=~ 1 << 0;
1936 if (pinfo
& (MIPS16_INSN_WRITE_X
| MIPS16_INSN_READ_X
))
1937 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RX
)
1938 & MIPS16OP_MASK_RX
);
1939 if (pinfo
& (MIPS16_INSN_WRITE_Y
| MIPS16_INSN_READ_Y
))
1940 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RY
)
1941 & MIPS16OP_MASK_RY
);
1942 if (pinfo
& MIPS16_INSN_WRITE_Z
)
1943 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_RZ
)
1944 & MIPS16OP_MASK_RZ
);
1945 if (pinfo
& (MIPS16_INSN_WRITE_T
| MIPS16_INSN_READ_T
))
1946 mips_gprmask
|= 1 << TREG
;
1947 if (pinfo
& (MIPS16_INSN_WRITE_SP
| MIPS16_INSN_READ_SP
))
1948 mips_gprmask
|= 1 << SP
;
1949 if (pinfo
& (MIPS16_INSN_WRITE_31
| MIPS16_INSN_READ_31
))
1950 mips_gprmask
|= 1 << RA
;
1951 if (pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
1952 mips_gprmask
|= 1 << MIPS16OP_EXTRACT_REG32R (ip
->insn_opcode
);
1953 if (pinfo
& MIPS16_INSN_READ_Z
)
1954 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_MOVE32Z
)
1955 & MIPS16OP_MASK_MOVE32Z
);
1956 if (pinfo
& MIPS16_INSN_READ_GPR_X
)
1957 mips_gprmask
|= 1 << ((ip
->insn_opcode
>> MIPS16OP_SH_REGR32
)
1958 & MIPS16OP_MASK_REGR32
);
1961 if (place
== NULL
&& ! mips_opts
.noreorder
)
1963 /* Filling the branch delay slot is more complex. We try to
1964 switch the branch with the previous instruction, which we can
1965 do if the previous instruction does not set up a condition
1966 that the branch tests and if the branch is not itself the
1967 target of any branch. */
1968 if ((pinfo
& INSN_UNCOND_BRANCH_DELAY
)
1969 || (pinfo
& INSN_COND_BRANCH_DELAY
))
1971 if (mips_optimize
< 2
1972 /* If we have seen .set volatile or .set nomove, don't
1974 || mips_opts
.nomove
!= 0
1975 /* If we had to emit any NOP instructions, then we
1976 already know we can not swap. */
1978 /* If we don't even know the previous insn, we can not
1980 || ! prev_insn_valid
1981 /* If the previous insn is already in a branch delay
1982 slot, then we can not swap. */
1983 || prev_insn_is_delay_slot
1984 /* If the previous previous insn was in a .set
1985 noreorder, we can't swap. Actually, the MIPS
1986 assembler will swap in this situation. However, gcc
1987 configured -with-gnu-as will generate code like
1993 in which we can not swap the bne and INSN. If gcc is
1994 not configured -with-gnu-as, it does not output the
1995 .set pseudo-ops. We don't have to check
1996 prev_insn_unreordered, because prev_insn_valid will
1997 be 0 in that case. We don't want to use
1998 prev_prev_insn_valid, because we do want to be able
1999 to swap at the start of a function. */
2000 || prev_prev_insn_unreordered
2001 /* If the branch is itself the target of a branch, we
2002 can not swap. We cheat on this; all we check for is
2003 whether there is a label on this instruction. If
2004 there are any branches to anything other than a
2005 label, users must use .set noreorder. */
2006 || insn_labels
!= NULL
2007 /* If the previous instruction is in a variant frag, we
2008 can not do the swap. This does not apply to the
2009 mips16, which uses variant frags for different
2011 || (! mips_opts
.mips16
2012 && prev_insn_frag
->fr_type
== rs_machine_dependent
)
2013 /* If the branch reads the condition codes, we don't
2014 even try to swap, because in the sequence
2019 we can not swap, and I don't feel like handling that
2021 || (! mips_opts
.mips16
2022 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2023 && (pinfo
& INSN_READ_COND_CODE
))
2024 /* We can not swap with an instruction that requires a
2025 delay slot, becase the target of the branch might
2026 interfere with that instruction. */
2027 || (! mips_opts
.mips16
2028 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2030 /* Itbl support may require additional care here. */
2031 & (INSN_LOAD_COPROC_DELAY
2032 | INSN_COPROC_MOVE_DELAY
2033 | INSN_WRITE_COND_CODE
)))
2034 || (! (hilo_interlocks
2035 || (mips_cpu
== 3900 && (pinfo
& INSN_MULT
)))
2039 || (! mips_opts
.mips16
2041 && (prev_pinfo
& INSN_LOAD_MEMORY_DELAY
))
2042 || (! mips_opts
.mips16
2043 && mips_opts
.isa
== 1
2044 /* Itbl support may require additional care here. */
2045 && (prev_pinfo
& INSN_COPROC_MEMORY_DELAY
))
2046 /* We can not swap with a branch instruction. */
2048 & (INSN_UNCOND_BRANCH_DELAY
2049 | INSN_COND_BRANCH_DELAY
2050 | INSN_COND_BRANCH_LIKELY
))
2051 /* We do not swap with a trap instruction, since it
2052 complicates trap handlers to have the trap
2053 instruction be in a delay slot. */
2054 || (prev_pinfo
& INSN_TRAP
)
2055 /* If the branch reads a register that the previous
2056 instruction sets, we can not swap. */
2057 || (! mips_opts
.mips16
2058 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2059 && insn_uses_reg (ip
,
2060 ((prev_insn
.insn_opcode
>> OP_SH_RT
)
2063 || (! mips_opts
.mips16
2064 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2065 && insn_uses_reg (ip
,
2066 ((prev_insn
.insn_opcode
>> OP_SH_RD
)
2069 || (mips_opts
.mips16
2070 && (((prev_pinfo
& MIPS16_INSN_WRITE_X
)
2071 && insn_uses_reg (ip
,
2072 ((prev_insn
.insn_opcode
2074 & MIPS16OP_MASK_RX
),
2076 || ((prev_pinfo
& MIPS16_INSN_WRITE_Y
)
2077 && insn_uses_reg (ip
,
2078 ((prev_insn
.insn_opcode
2080 & MIPS16OP_MASK_RY
),
2082 || ((prev_pinfo
& MIPS16_INSN_WRITE_Z
)
2083 && insn_uses_reg (ip
,
2084 ((prev_insn
.insn_opcode
2086 & MIPS16OP_MASK_RZ
),
2088 || ((prev_pinfo
& MIPS16_INSN_WRITE_T
)
2089 && insn_uses_reg (ip
, TREG
, MIPS_GR_REG
))
2090 || ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2091 && insn_uses_reg (ip
, RA
, MIPS_GR_REG
))
2092 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2093 && insn_uses_reg (ip
,
2094 MIPS16OP_EXTRACT_REG32R (prev_insn
.
2097 /* If the branch writes a register that the previous
2098 instruction sets, we can not swap (we know that
2099 branches write only to RD or to $31). */
2100 || (! mips_opts
.mips16
2101 && (prev_pinfo
& INSN_WRITE_GPR_T
)
2102 && (((pinfo
& INSN_WRITE_GPR_D
)
2103 && (((prev_insn
.insn_opcode
>> OP_SH_RT
) & OP_MASK_RT
)
2104 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2105 || ((pinfo
& INSN_WRITE_GPR_31
)
2106 && (((prev_insn
.insn_opcode
>> OP_SH_RT
)
2109 || (! mips_opts
.mips16
2110 && (prev_pinfo
& INSN_WRITE_GPR_D
)
2111 && (((pinfo
& INSN_WRITE_GPR_D
)
2112 && (((prev_insn
.insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)
2113 == ((ip
->insn_opcode
>> OP_SH_RD
) & OP_MASK_RD
)))
2114 || ((pinfo
& INSN_WRITE_GPR_31
)
2115 && (((prev_insn
.insn_opcode
>> OP_SH_RD
)
2118 || (mips_opts
.mips16
2119 && (pinfo
& MIPS16_INSN_WRITE_31
)
2120 && ((prev_pinfo
& MIPS16_INSN_WRITE_31
)
2121 || ((prev_pinfo
& MIPS16_INSN_WRITE_GPR_Y
)
2122 && (MIPS16OP_EXTRACT_REG32R (prev_insn
.insn_opcode
)
2124 /* If the branch writes a register that the previous
2125 instruction reads, we can not swap (we know that
2126 branches only write to RD or to $31). */
2127 || (! mips_opts
.mips16
2128 && (pinfo
& INSN_WRITE_GPR_D
)
2129 && insn_uses_reg (&prev_insn
,
2130 ((ip
->insn_opcode
>> OP_SH_RD
)
2133 || (! mips_opts
.mips16
2134 && (pinfo
& INSN_WRITE_GPR_31
)
2135 && insn_uses_reg (&prev_insn
, 31, MIPS_GR_REG
))
2136 || (mips_opts
.mips16
2137 && (pinfo
& MIPS16_INSN_WRITE_31
)
2138 && insn_uses_reg (&prev_insn
, RA
, MIPS_GR_REG
))
2139 /* If we are generating embedded PIC code, the branch
2140 might be expanded into a sequence which uses $at, so
2141 we can't swap with an instruction which reads it. */
2142 || (mips_pic
== EMBEDDED_PIC
2143 && insn_uses_reg (&prev_insn
, AT
, MIPS_GR_REG
))
2144 /* If the previous previous instruction has a load
2145 delay, and sets a register that the branch reads, we
2147 || (! mips_opts
.mips16
2148 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2149 /* Itbl support may require additional care here. */
2150 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_LOAD_COPROC_DELAY
)
2151 || (! gpr_interlocks
2152 && (prev_prev_insn
.insn_mo
->pinfo
2153 & INSN_LOAD_MEMORY_DELAY
)))
2154 && insn_uses_reg (ip
,
2155 ((prev_prev_insn
.insn_opcode
>> OP_SH_RT
)
2158 /* If one instruction sets a condition code and the
2159 other one uses a condition code, we can not swap. */
2160 || ((pinfo
& INSN_READ_COND_CODE
)
2161 && (prev_pinfo
& INSN_WRITE_COND_CODE
))
2162 || ((pinfo
& INSN_WRITE_COND_CODE
)
2163 && (prev_pinfo
& INSN_READ_COND_CODE
))
2164 /* If the previous instruction uses the PC, we can not
2166 || (mips_opts
.mips16
2167 && (prev_pinfo
& MIPS16_INSN_READ_PC
))
2168 /* If the previous instruction was extended, we can not
2170 || (mips_opts
.mips16
&& prev_insn_extended
)
2171 /* If the previous instruction had a fixup in mips16
2172 mode, we can not swap. This normally means that the
2173 previous instruction was a 4 byte branch anyhow. */
2174 || (mips_opts
.mips16
&& prev_insn_fixp
)
2175 /* If the previous instruction is a sync, sync.l, or
2176 sync.p, we can not swap. */
2177 || (prev_pinfo
& INSN_SYNC
))
2179 /* We could do even better for unconditional branches to
2180 portions of this object file; we could pick up the
2181 instruction at the destination, put it in the delay
2182 slot, and bump the destination address. */
2184 /* Update the previous insn information. */
2185 prev_prev_insn
= *ip
;
2186 prev_insn
.insn_mo
= &dummy_opcode
;
2190 /* It looks like we can actually do the swap. */
2191 if (! mips_opts
.mips16
)
2196 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2197 memcpy (temp
, prev_f
, 4);
2198 memcpy (prev_f
, f
, 4);
2199 memcpy (f
, temp
, 4);
2202 prev_insn_fixp
->fx_frag
= frag_now
;
2203 prev_insn_fixp
->fx_where
= f
- frag_now
->fr_literal
;
2207 fixp
->fx_frag
= prev_insn_frag
;
2208 fixp
->fx_where
= prev_insn_where
;
2216 assert (prev_insn_fixp
== NULL
);
2217 prev_f
= prev_insn_frag
->fr_literal
+ prev_insn_where
;
2218 memcpy (temp
, prev_f
, 2);
2219 memcpy (prev_f
, f
, 2);
2220 if (reloc_type
!= BFD_RELOC_MIPS16_JMP
)
2222 assert (reloc_type
== BFD_RELOC_UNUSED
);
2223 memcpy (f
, temp
, 2);
2227 memcpy (f
, f
+ 2, 2);
2228 memcpy (f
+ 2, temp
, 2);
2232 fixp
->fx_frag
= prev_insn_frag
;
2233 fixp
->fx_where
= prev_insn_where
;
2237 /* Update the previous insn information; leave prev_insn
2239 prev_prev_insn
= *ip
;
2241 prev_insn_is_delay_slot
= 1;
2243 /* If that was an unconditional branch, forget the previous
2244 insn information. */
2245 if (pinfo
& INSN_UNCOND_BRANCH_DELAY
)
2247 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2248 prev_insn
.insn_mo
= &dummy_opcode
;
2251 prev_insn_fixp
= NULL
;
2252 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2253 prev_insn_extended
= 0;
2255 else if (pinfo
& INSN_COND_BRANCH_LIKELY
)
2257 /* We don't yet optimize a branch likely. What we should do
2258 is look at the target, copy the instruction found there
2259 into the delay slot, and increment the branch to jump to
2260 the next instruction. */
2262 /* Update the previous insn information. */
2263 prev_prev_insn
= *ip
;
2264 prev_insn
.insn_mo
= &dummy_opcode
;
2265 prev_insn_fixp
= NULL
;
2266 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2267 prev_insn_extended
= 0;
2271 /* Update the previous insn information. */
2273 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2275 prev_prev_insn
= prev_insn
;
2278 /* Any time we see a branch, we always fill the delay slot
2279 immediately; since this insn is not a branch, we know it
2280 is not in a delay slot. */
2281 prev_insn_is_delay_slot
= 0;
2283 prev_insn_fixp
= fixp
;
2284 prev_insn_reloc_type
= reloc_type
;
2285 if (mips_opts
.mips16
)
2286 prev_insn_extended
= (ip
->use_extend
2287 || reloc_type
> BFD_RELOC_UNUSED
);
2290 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2291 prev_insn_unreordered
= 0;
2292 prev_insn_frag
= frag_now
;
2293 prev_insn_where
= f
- frag_now
->fr_literal
;
2294 prev_insn_valid
= 1;
2296 else if (place
== NULL
)
2298 /* We need to record a bit of information even when we are not
2299 reordering, in order to determine the base address for mips16
2300 PC relative relocs. */
2301 prev_prev_insn
= prev_insn
;
2303 prev_insn_reloc_type
= reloc_type
;
2304 prev_prev_insn_unreordered
= prev_insn_unreordered
;
2305 prev_insn_unreordered
= 1;
2308 /* We just output an insn, so the next one doesn't have a label. */
2309 mips_clear_insn_labels ();
2311 /* We must ensure that a fixup associated with an unmatched %hi
2312 reloc does not become a variant frag. Otherwise, the
2313 rearrangement of %hi relocs in frob_file may confuse
2317 frag_wane (frag_now
);
2322 /* This function forgets that there was any previous instruction or
2323 label. If PRESERVE is non-zero, it remembers enough information to
2324 know whether nops are needed before a noreorder section. */
2327 mips_no_prev_insn (preserve
)
2332 prev_insn
.insn_mo
= &dummy_opcode
;
2333 prev_prev_insn
.insn_mo
= &dummy_opcode
;
2334 prev_nop_frag
= NULL
;
2335 prev_nop_frag_holds
= 0;
2336 prev_nop_frag_required
= 0;
2337 prev_nop_frag_since
= 0;
2339 prev_insn_valid
= 0;
2340 prev_insn_is_delay_slot
= 0;
2341 prev_insn_unreordered
= 0;
2342 prev_insn_extended
= 0;
2343 prev_insn_reloc_type
= BFD_RELOC_UNUSED
;
2344 prev_prev_insn_unreordered
= 0;
2345 mips_clear_insn_labels ();
2348 /* This function must be called whenever we turn on noreorder or emit
2349 something other than instructions. It inserts any NOPS which might
2350 be needed by the previous instruction, and clears the information
2351 kept for the previous instructions. The INSNS parameter is true if
2352 instructions are to follow. */
2355 mips_emit_delays (insns
)
2358 if (! mips_opts
.noreorder
)
2363 if ((! mips_opts
.mips16
2364 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2365 && (! cop_interlocks
2366 && (prev_insn
.insn_mo
->pinfo
2367 & (INSN_LOAD_COPROC_DELAY
2368 | INSN_COPROC_MOVE_DELAY
2369 | INSN_WRITE_COND_CODE
))))
2370 || (! hilo_interlocks
2371 && (prev_insn
.insn_mo
->pinfo
2374 || (! mips_opts
.mips16
2376 && (prev_insn
.insn_mo
->pinfo
2377 & INSN_LOAD_MEMORY_DELAY
))
2378 || (! mips_opts
.mips16
2379 && mips_opts
.isa
== 1
2380 && (prev_insn
.insn_mo
->pinfo
2381 & INSN_COPROC_MEMORY_DELAY
)))
2383 /* Itbl support may require additional care here. */
2385 if ((! mips_opts
.mips16
2386 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2387 && (! cop_interlocks
2388 && prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2389 || (! hilo_interlocks
2390 && ((prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2391 || (prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2394 if (prev_insn_unreordered
)
2397 else if ((! mips_opts
.mips16
2398 && ISA_HAS_COPROC_DELAYS (mips_opts
.isa
)
2399 && (! cop_interlocks
2400 && prev_prev_insn
.insn_mo
->pinfo
& INSN_WRITE_COND_CODE
))
2401 || (! hilo_interlocks
2402 && ((prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_HI
)
2403 || (prev_prev_insn
.insn_mo
->pinfo
& INSN_READ_LO
))))
2405 /* Itbl support may require additional care here. */
2406 if (! prev_prev_insn_unreordered
)
2412 struct insn_label_list
*l
;
2416 /* Record the frag which holds the nop instructions, so
2417 that we can remove them if we don't need them. */
2418 frag_grow (mips_opts
.mips16
? nops
* 2 : nops
* 4);
2419 prev_nop_frag
= frag_now
;
2420 prev_nop_frag_holds
= nops
;
2421 prev_nop_frag_required
= 0;
2422 prev_nop_frag_since
= 0;
2425 for (; nops
> 0; --nops
)
2430 /* Move on to a new frag, so that it is safe to simply
2431 decrease the size of prev_nop_frag. */
2432 frag_wane (frag_now
);
2436 for (l
= insn_labels
; l
!= NULL
; l
= l
->next
)
2438 assert (S_GET_SEGMENT (l
->label
) == now_seg
);
2439 symbol_set_frag (l
->label
, frag_now
);
2440 S_SET_VALUE (l
->label
, (valueT
) frag_now_fix ());
2441 /* mips16 text labels are stored as odd. */
2442 if (mips_opts
.mips16
)
2443 S_SET_VALUE (l
->label
, S_GET_VALUE (l
->label
) + 1);
2448 /* Mark instruction labels in mips16 mode. */
2449 if (mips_opts
.mips16
&& insns
)
2450 mips16_mark_labels ();
2452 mips_no_prev_insn (insns
);
2455 /* Build an instruction created by a macro expansion. This is passed
2456 a pointer to the count of instructions created so far, an
2457 expression, the name of the instruction to build, an operand format
2458 string, and corresponding arguments. */
2462 macro_build (char *place
,
2470 macro_build (place
, counter
, ep
, name
, fmt
, va_alist
)
2479 struct mips_cl_insn insn
;
2480 bfd_reloc_code_real_type r
;
2484 va_start (args
, fmt
);
2490 * If the macro is about to expand into a second instruction,
2491 * print a warning if needed. We need to pass ip as a parameter
2492 * to generate a better warning message here...
2494 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2495 as_warn (_("Macro instruction expanded into multiple instructions"));
2498 *counter
+= 1; /* bump instruction counter */
2500 if (mips_opts
.mips16
)
2502 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
);
2507 r
= BFD_RELOC_UNUSED
;
2508 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2509 assert (insn
.insn_mo
);
2510 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2512 /* Search until we get a match for NAME. */
2515 if (strcmp (fmt
, insn
.insn_mo
->args
) == 0
2516 && insn
.insn_mo
->pinfo
!= INSN_MACRO
2517 && OPCODE_IS_MEMBER (insn
.insn_mo
, mips_opts
.isa
, mips_cpu
,
2519 && (mips_cpu
!= 4650 || (insn
.insn_mo
->pinfo
& FP_D
) == 0))
2523 assert (insn
.insn_mo
->name
);
2524 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2527 insn
.insn_opcode
= insn
.insn_mo
->match
;
2543 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2549 insn
.insn_opcode
|= va_arg (args
, int) << 16;
2554 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2559 insn
.insn_opcode
|= va_arg (args
, int) << 11;
2566 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2570 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2574 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2578 insn
.insn_opcode
|= va_arg (args
, int) << 6;
2585 insn
.insn_opcode
|= va_arg (args
, int) << 21;
2591 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2592 assert (r
== BFD_RELOC_MIPS_GPREL
2593 || r
== BFD_RELOC_MIPS_LITERAL
2594 || r
== BFD_RELOC_LO16
2595 || r
== BFD_RELOC_MIPS_GOT16
2596 || r
== BFD_RELOC_MIPS_CALL16
2597 || r
== BFD_RELOC_MIPS_GOT_LO16
2598 || r
== BFD_RELOC_MIPS_CALL_LO16
2599 || (ep
->X_op
== O_subtract
2600 && r
== BFD_RELOC_PCREL_LO16
));
2604 r
= (bfd_reloc_code_real_type
) va_arg (args
, int);
2606 && (ep
->X_op
== O_constant
2607 || (ep
->X_op
== O_symbol
2608 && (r
== BFD_RELOC_HI16_S
2609 || r
== BFD_RELOC_HI16
2610 || r
== BFD_RELOC_MIPS_GOT_HI16
2611 || r
== BFD_RELOC_MIPS_CALL_HI16
))
2612 || (ep
->X_op
== O_subtract
2613 && r
== BFD_RELOC_PCREL_HI16_S
)));
2614 if (ep
->X_op
== O_constant
)
2616 insn
.insn_opcode
|= (ep
->X_add_number
>> 16) & 0xffff;
2618 r
= BFD_RELOC_UNUSED
;
2623 assert (ep
!= NULL
);
2625 * This allows macro() to pass an immediate expression for
2626 * creating short branches without creating a symbol.
2627 * Note that the expression still might come from the assembly
2628 * input, in which case the value is not checked for range nor
2629 * is a relocation entry generated (yuck).
2631 if (ep
->X_op
== O_constant
)
2633 insn
.insn_opcode
|= (ep
->X_add_number
>> 2) & 0xffff;
2637 r
= BFD_RELOC_16_PCREL_S2
;
2641 assert (ep
!= NULL
);
2642 r
= BFD_RELOC_MIPS_JMP
;
2646 insn
.insn_opcode
|= va_arg (args
, unsigned long);
2655 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2657 append_insn (place
, &insn
, ep
, r
, false);
2661 mips16_macro_build (place
, counter
, ep
, name
, fmt
, args
)
2663 int *counter ATTRIBUTE_UNUSED
;
2669 struct mips_cl_insn insn
;
2670 bfd_reloc_code_real_type r
;
2672 r
= BFD_RELOC_UNUSED
;
2673 insn
.insn_mo
= (struct mips_opcode
*) hash_find (mips16_op_hash
, name
);
2674 assert (insn
.insn_mo
);
2675 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2677 while (strcmp (fmt
, insn
.insn_mo
->args
) != 0
2678 || insn
.insn_mo
->pinfo
== INSN_MACRO
)
2681 assert (insn
.insn_mo
->name
);
2682 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2685 insn
.insn_opcode
= insn
.insn_mo
->match
;
2686 insn
.use_extend
= false;
2705 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RY
;
2710 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RX
;
2714 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_RZ
;
2718 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_MOVE32Z
;
2728 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_REGR32
;
2735 regno
= va_arg (args
, int);
2736 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
2737 insn
.insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
2758 assert (ep
!= NULL
);
2760 if (ep
->X_op
!= O_constant
)
2761 r
= BFD_RELOC_UNUSED
+ c
;
2764 mips16_immed ((char *) NULL
, 0, c
, ep
->X_add_number
, false,
2765 false, false, &insn
.insn_opcode
,
2766 &insn
.use_extend
, &insn
.extend
);
2768 r
= BFD_RELOC_UNUSED
;
2774 insn
.insn_opcode
|= va_arg (args
, int) << MIPS16OP_SH_IMM6
;
2781 assert (r
== BFD_RELOC_UNUSED
? ep
== NULL
: ep
!= NULL
);
2783 append_insn (place
, &insn
, ep
, r
, false);
2787 * Generate a "lui" instruction.
2790 macro_build_lui (place
, counter
, ep
, regnum
)
2796 expressionS high_expr
;
2797 struct mips_cl_insn insn
;
2798 bfd_reloc_code_real_type r
;
2799 CONST
char *name
= "lui";
2800 CONST
char *fmt
= "t,u";
2802 assert (! mips_opts
.mips16
);
2808 high_expr
.X_op
= O_constant
;
2809 high_expr
.X_add_number
= ep
->X_add_number
;
2812 if (high_expr
.X_op
== O_constant
)
2814 /* we can compute the instruction now without a relocation entry */
2815 if (high_expr
.X_add_number
& 0x8000)
2816 high_expr
.X_add_number
+= 0x10000;
2817 high_expr
.X_add_number
=
2818 ((unsigned long) high_expr
.X_add_number
>> 16) & 0xffff;
2819 r
= BFD_RELOC_UNUSED
;
2823 assert (ep
->X_op
== O_symbol
);
2824 /* _gp_disp is a special case, used from s_cpload. */
2825 assert (mips_pic
== NO_PIC
2826 || strcmp (S_GET_NAME (ep
->X_add_symbol
), "_gp_disp") == 0);
2827 r
= BFD_RELOC_HI16_S
;
2831 * If the macro is about to expand into a second instruction,
2832 * print a warning if needed. We need to pass ip as a parameter
2833 * to generate a better warning message here...
2835 if (mips_opts
.warn_about_macros
&& place
== NULL
&& *counter
== 1)
2836 as_warn (_("Macro instruction expanded into multiple instructions"));
2839 *counter
+= 1; /* bump instruction counter */
2841 insn
.insn_mo
= (struct mips_opcode
*) hash_find (op_hash
, name
);
2842 assert (insn
.insn_mo
);
2843 assert (strcmp (name
, insn
.insn_mo
->name
) == 0);
2844 assert (strcmp (fmt
, insn
.insn_mo
->args
) == 0);
2846 insn
.insn_opcode
= insn
.insn_mo
->match
| (regnum
<< OP_SH_RT
);
2847 if (r
== BFD_RELOC_UNUSED
)
2849 insn
.insn_opcode
|= high_expr
.X_add_number
;
2850 append_insn (place
, &insn
, NULL
, r
, false);
2853 append_insn (place
, &insn
, &high_expr
, r
, false);
2857 * Generates code to set the $at register to true (one)
2858 * if reg is less than the immediate expression.
2861 set_at (counter
, reg
, unsignedp
)
2866 if (imm_expr
.X_op
== O_constant
2867 && imm_expr
.X_add_number
>= -0x8000
2868 && imm_expr
.X_add_number
< 0x8000)
2869 macro_build ((char *) NULL
, counter
, &imm_expr
,
2870 unsignedp
? "sltiu" : "slti",
2871 "t,r,j", AT
, reg
, (int) BFD_RELOC_LO16
);
2874 load_register (counter
, AT
, &imm_expr
, 0);
2875 macro_build ((char *) NULL
, counter
, NULL
,
2876 unsignedp
? "sltu" : "slt",
2877 "d,v,t", AT
, reg
, AT
);
2881 /* Warn if an expression is not a constant. */
2884 check_absolute_expr (ip
, ex
)
2885 struct mips_cl_insn
*ip
;
2888 if (ex
->X_op
== O_big
)
2889 as_bad (_("unsupported large constant"));
2890 else if (ex
->X_op
!= O_constant
)
2891 as_bad (_("Instruction %s requires absolute expression"), ip
->insn_mo
->name
);
2894 /* Count the leading zeroes by performing a binary chop. This is a
2895 bulky bit of source, but performance is a LOT better for the
2896 majority of values than a simple loop to count the bits:
2897 for (lcnt = 0; (lcnt < 32); lcnt++)
2898 if ((v) & (1 << (31 - lcnt)))
2900 However it is not code size friendly, and the gain will drop a bit
2901 on certain cached systems.
2903 #define COUNT_TOP_ZEROES(v) \
2904 (((v) & ~0xffff) == 0 \
2905 ? ((v) & ~0xff) == 0 \
2906 ? ((v) & ~0xf) == 0 \
2907 ? ((v) & ~0x3) == 0 \
2908 ? ((v) & ~0x1) == 0 \
2913 : ((v) & ~0x7) == 0 \
2916 : ((v) & ~0x3f) == 0 \
2917 ? ((v) & ~0x1f) == 0 \
2920 : ((v) & ~0x7f) == 0 \
2923 : ((v) & ~0xfff) == 0 \
2924 ? ((v) & ~0x3ff) == 0 \
2925 ? ((v) & ~0x1ff) == 0 \
2928 : ((v) & ~0x7ff) == 0 \
2931 : ((v) & ~0x3fff) == 0 \
2932 ? ((v) & ~0x1fff) == 0 \
2935 : ((v) & ~0x7fff) == 0 \
2938 : ((v) & ~0xffffff) == 0 \
2939 ? ((v) & ~0xfffff) == 0 \
2940 ? ((v) & ~0x3ffff) == 0 \
2941 ? ((v) & ~0x1ffff) == 0 \
2944 : ((v) & ~0x7ffff) == 0 \
2947 : ((v) & ~0x3fffff) == 0 \
2948 ? ((v) & ~0x1fffff) == 0 \
2951 : ((v) & ~0x7fffff) == 0 \
2954 : ((v) & ~0xfffffff) == 0 \
2955 ? ((v) & ~0x3ffffff) == 0 \
2956 ? ((v) & ~0x1ffffff) == 0 \
2959 : ((v) & ~0x7ffffff) == 0 \
2962 : ((v) & ~0x3fffffff) == 0 \
2963 ? ((v) & ~0x1fffffff) == 0 \
2966 : ((v) & ~0x7fffffff) == 0 \
2971 * This routine generates the least number of instructions neccessary to load
2972 * an absolute expression value into a register.
2975 load_register (counter
, reg
, ep
, dbl
)
2982 expressionS hi32
, lo32
;
2984 if (ep
->X_op
!= O_big
)
2986 assert (ep
->X_op
== O_constant
);
2987 if (ep
->X_add_number
< 0x8000
2988 && (ep
->X_add_number
>= 0
2989 || (ep
->X_add_number
>= -0x8000
2992 || sizeof (ep
->X_add_number
) > 4))))
2994 /* We can handle 16 bit signed values with an addiu to
2995 $zero. No need to ever use daddiu here, since $zero and
2996 the result are always correct in 32 bit mode. */
2997 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
2998 (int) BFD_RELOC_LO16
);
3001 else if (ep
->X_add_number
>= 0 && ep
->X_add_number
< 0x10000)
3003 /* We can handle 16 bit unsigned values with an ori to
3005 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, 0,
3006 (int) BFD_RELOC_LO16
);
3009 else if ((((ep
->X_add_number
&~ (offsetT
) 0x7fffffff) == 0
3010 || ((ep
->X_add_number
&~ (offsetT
) 0x7fffffff)
3011 == ~ (offsetT
) 0x7fffffff))
3014 || sizeof (ep
->X_add_number
) > 4
3015 || (ep
->X_add_number
& 0x80000000) == 0))
3016 || ((! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || ! dbl
)
3017 && (ep
->X_add_number
&~ (offsetT
) 0xffffffff) == 0)
3018 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3020 && ((ep
->X_add_number
&~ (offsetT
) 0xffffffff)
3021 == ~ (offsetT
) 0xffffffff)))
3023 /* 32 bit values require an lui. */
3024 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3025 (int) BFD_RELOC_HI16
);
3026 if ((ep
->X_add_number
& 0xffff) != 0)
3027 macro_build ((char *) NULL
, counter
, ep
, "ori", "t,r,i", reg
, reg
,
3028 (int) BFD_RELOC_LO16
);
3033 /* The value is larger than 32 bits. */
3035 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3037 as_bad (_("Number larger than 32 bits"));
3038 macro_build ((char *) NULL
, counter
, ep
, "addiu", "t,r,j", reg
, 0,
3039 (int) BFD_RELOC_LO16
);
3043 if (ep
->X_op
!= O_big
)
3046 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3047 hi32
.X_add_number
= (valueT
) hi32
.X_add_number
>> 16;
3048 hi32
.X_add_number
&= 0xffffffff;
3050 lo32
.X_add_number
&= 0xffffffff;
3054 assert (ep
->X_add_number
> 2);
3055 if (ep
->X_add_number
== 3)
3056 generic_bignum
[3] = 0;
3057 else if (ep
->X_add_number
> 4)
3058 as_bad (_("Number larger than 64 bits"));
3059 lo32
.X_op
= O_constant
;
3060 lo32
.X_add_number
= generic_bignum
[0] + (generic_bignum
[1] << 16);
3061 hi32
.X_op
= O_constant
;
3062 hi32
.X_add_number
= generic_bignum
[2] + (generic_bignum
[3] << 16);
3065 if (hi32
.X_add_number
== 0)
3070 unsigned long hi
, lo
;
3072 if (hi32
.X_add_number
== 0xffffffff)
3074 if ((lo32
.X_add_number
& 0xffff8000) == 0xffff8000)
3076 macro_build ((char *) NULL
, counter
, &lo32
, "addiu", "t,r,j",
3077 reg
, 0, (int) BFD_RELOC_LO16
);
3080 if (lo32
.X_add_number
& 0x80000000)
3082 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3083 (int) BFD_RELOC_HI16
);
3084 if (lo32
.X_add_number
& 0xffff)
3085 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i",
3086 reg
, reg
, (int) BFD_RELOC_LO16
);
3091 /* Check for 16bit shifted constant. We know that hi32 is
3092 non-zero, so start the mask on the first bit of the hi32
3097 unsigned long himask
, lomask
;
3101 himask
= 0xffff >> (32 - shift
);
3102 lomask
= (0xffff << shift
) & 0xffffffff;
3106 himask
= 0xffff << (shift
- 32);
3109 if ((hi32
.X_add_number
& ~ (offsetT
) himask
) == 0
3110 && (lo32
.X_add_number
& ~ (offsetT
) lomask
) == 0)
3114 tmp
.X_op
= O_constant
;
3116 tmp
.X_add_number
= ((hi32
.X_add_number
<< (32 - shift
))
3117 | (lo32
.X_add_number
>> shift
));
3119 tmp
.X_add_number
= hi32
.X_add_number
>> (shift
- 32);
3120 macro_build ((char *) NULL
, counter
, &tmp
, "ori", "t,r,i", reg
, 0,
3121 (int) BFD_RELOC_LO16
);
3122 macro_build ((char *) NULL
, counter
, NULL
,
3123 (shift
>= 32) ? "dsll32" : "dsll",
3125 (shift
>= 32) ? shift
- 32 : shift
);
3129 } while (shift
<= (64 - 16));
3131 /* Find the bit number of the lowest one bit, and store the
3132 shifted value in hi/lo. */
3133 hi
= (unsigned long) (hi32
.X_add_number
& 0xffffffff);
3134 lo
= (unsigned long) (lo32
.X_add_number
& 0xffffffff);
3138 while ((lo
& 1) == 0)
3143 lo
|= (hi
& (((unsigned long) 1 << bit
) - 1)) << (32 - bit
);
3149 while ((hi
& 1) == 0)
3158 /* Optimize if the shifted value is a (power of 2) - 1. */
3159 if ((hi
== 0 && ((lo
+ 1) & lo
) == 0)
3160 || (lo
== 0xffffffff && ((hi
+ 1) & hi
) == 0))
3162 shift
= COUNT_TOP_ZEROES ((unsigned int) hi32
.X_add_number
);
3167 /* This instruction will set the register to be all
3169 tmp
.X_op
= O_constant
;
3170 tmp
.X_add_number
= (offsetT
) -1;
3171 macro_build ((char *) NULL
, counter
, &tmp
, "addiu", "t,r,j",
3172 reg
, 0, (int) BFD_RELOC_LO16
);
3176 macro_build ((char *) NULL
, counter
, NULL
,
3177 (bit
>= 32) ? "dsll32" : "dsll",
3179 (bit
>= 32) ? bit
- 32 : bit
);
3181 macro_build ((char *) NULL
, counter
, NULL
,
3182 (shift
>= 32) ? "dsrl32" : "dsrl",
3184 (shift
>= 32) ? shift
- 32 : shift
);
3189 /* Sign extend hi32 before calling load_register, because we can
3190 generally get better code when we load a sign extended value. */
3191 if ((hi32
.X_add_number
& 0x80000000) != 0)
3192 hi32
.X_add_number
|= ~ (offsetT
) 0xffffffff;
3193 load_register (counter
, reg
, &hi32
, 0);
3196 if ((lo32
.X_add_number
& 0xffff0000) == 0)
3200 macro_build ((char *) NULL
, counter
, NULL
, "dsll32", "d,w,<", reg
,
3209 if ((freg
== 0) && (lo32
.X_add_number
== 0xffffffff))
3211 macro_build ((char *) NULL
, counter
, &lo32
, "lui", "t,u", reg
,
3212 (int) BFD_RELOC_HI16
);
3213 macro_build ((char *) NULL
, counter
, NULL
, "dsrl32", "d,w,<", reg
,
3220 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3225 mid16
.X_add_number
>>= 16;
3226 macro_build ((char *) NULL
, counter
, &mid16
, "ori", "t,r,i", reg
,
3227 freg
, (int) BFD_RELOC_LO16
);
3228 macro_build ((char *) NULL
, counter
, NULL
, "dsll", "d,w,<", reg
,
3232 if ((lo32
.X_add_number
& 0xffff) != 0)
3233 macro_build ((char *) NULL
, counter
, &lo32
, "ori", "t,r,i", reg
, freg
,
3234 (int) BFD_RELOC_LO16
);
3237 /* Load an address into a register. */
3240 load_address (counter
, reg
, ep
)
3247 if (ep
->X_op
!= O_constant
3248 && ep
->X_op
!= O_symbol
)
3250 as_bad (_("expression too complex"));
3251 ep
->X_op
= O_constant
;
3254 if (ep
->X_op
== O_constant
)
3256 load_register (counter
, reg
, ep
, 0);
3260 if (mips_pic
== NO_PIC
)
3262 /* If this is a reference to a GP relative symbol, we want
3263 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3265 lui $reg,<sym> (BFD_RELOC_HI16_S)
3266 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3267 If we have an addend, we always use the latter form. */
3268 if ((valueT
) ep
->X_add_number
>= MAX_GPREL_OFFSET
3269 || nopic_need_relax (ep
->X_add_symbol
, 1))
3274 macro_build ((char *) NULL
, counter
, ep
,
3275 ((bfd_arch_bits_per_address (stdoutput
) == 32
3276 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3277 ? "addiu" : "daddiu"),
3278 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3279 p
= frag_var (rs_machine_dependent
, 8, 0,
3280 RELAX_ENCODE (4, 8, 0, 4, 0,
3281 mips_opts
.warn_about_macros
),
3282 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3284 macro_build_lui (p
, counter
, ep
, reg
);
3287 macro_build (p
, counter
, ep
,
3288 ((bfd_arch_bits_per_address (stdoutput
) == 32
3289 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3290 ? "addiu" : "daddiu"),
3291 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3293 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
3297 /* If this is a reference to an external symbol, we want
3298 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3300 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3302 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3303 If there is a constant, it must be added in after. */
3304 ex
.X_add_number
= ep
->X_add_number
;
3305 ep
->X_add_number
= 0;
3307 macro_build ((char *) NULL
, counter
, ep
,
3308 ((bfd_arch_bits_per_address (stdoutput
) == 32
3309 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3311 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3312 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
, "nop", "");
3313 p
= frag_var (rs_machine_dependent
, 4, 0,
3314 RELAX_ENCODE (0, 4, -8, 0, 0, mips_opts
.warn_about_macros
),
3315 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3316 macro_build (p
, counter
, ep
,
3317 ((bfd_arch_bits_per_address (stdoutput
) == 32
3318 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3319 ? "addiu" : "daddiu"),
3320 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3321 if (ex
.X_add_number
!= 0)
3323 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3324 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3325 ex
.X_op
= O_constant
;
3326 macro_build ((char *) NULL
, counter
, &ex
,
3327 ((bfd_arch_bits_per_address (stdoutput
) == 32
3328 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3329 ? "addiu" : "daddiu"),
3330 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3333 else if (mips_pic
== SVR4_PIC
)
3338 /* This is the large GOT case. If this is a reference to an
3339 external symbol, we want
3340 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3342 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)
3343 Otherwise, for a reference to a local symbol, we want
3344 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3346 addiu $reg,$reg,<sym> (BFD_RELOC_LO16)
3347 If there is a constant, it must be added in after. */
3348 ex
.X_add_number
= ep
->X_add_number
;
3349 ep
->X_add_number
= 0;
3350 if (reg_needs_delay (GP
))
3355 macro_build ((char *) NULL
, counter
, ep
, "lui", "t,u", reg
,
3356 (int) BFD_RELOC_MIPS_GOT_HI16
);
3357 macro_build ((char *) NULL
, counter
, (expressionS
*) NULL
,
3358 ((bfd_arch_bits_per_address (stdoutput
) == 32
3359 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3360 ? "addu" : "daddu"),
3361 "d,v,t", reg
, reg
, GP
);
3362 macro_build ((char *) NULL
, counter
, ep
,
3363 ((bfd_arch_bits_per_address (stdoutput
) == 32
3364 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3366 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT_LO16
, reg
);
3367 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
3368 RELAX_ENCODE (12, 12 + off
, off
, 8 + off
, 0,
3369 mips_opts
.warn_about_macros
),
3370 ep
->X_add_symbol
, (offsetT
) 0, (char *) NULL
);
3373 /* We need a nop before loading from $gp. This special
3374 check is required because the lui which starts the main
3375 instruction stream does not refer to $gp, and so will not
3376 insert the nop which may be required. */
3377 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3380 macro_build (p
, counter
, ep
,
3381 ((bfd_arch_bits_per_address (stdoutput
) == 32
3382 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3384 "t,o(b)", reg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
3386 macro_build (p
, counter
, (expressionS
*) NULL
, "nop", "");
3388 macro_build (p
, counter
, ep
,
3389 ((bfd_arch_bits_per_address (stdoutput
) == 32
3390 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3391 ? "addiu" : "daddiu"),
3392 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3393 if (ex
.X_add_number
!= 0)
3395 if (ex
.X_add_number
< -0x8000 || ex
.X_add_number
>= 0x8000)
3396 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3397 ex
.X_op
= O_constant
;
3398 macro_build ((char *) NULL
, counter
, &ex
,
3399 ((bfd_arch_bits_per_address (stdoutput
) == 32
3400 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3401 ? "addiu" : "daddiu"),
3402 "t,r,j", reg
, reg
, (int) BFD_RELOC_LO16
);
3405 else if (mips_pic
== EMBEDDED_PIC
)
3408 addiu $reg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
3410 macro_build ((char *) NULL
, counter
, ep
,
3411 ((bfd_arch_bits_per_address (stdoutput
) == 32
3412 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
3413 ? "addiu" : "daddiu"),
3414 "t,r,j", reg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
3422 * This routine implements the seemingly endless macro or synthesized
3423 * instructions and addressing modes in the mips assembly language. Many
3424 * of these macros are simple and are similar to each other. These could
3425 * probably be handled by some kind of table or grammer aproach instead of
3426 * this verbose method. Others are not simple macros but are more like
3427 * optimizing code generation.
3428 * One interesting optimization is when several store macros appear
3429 * consecutivly that would load AT with the upper half of the same address.
3430 * The ensuing load upper instructions are ommited. This implies some kind
3431 * of global optimization. We currently only optimize within a single macro.
3432 * For many of the load and store macros if the address is specified as a
3433 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
3434 * first load register 'at' with zero and use it as the base register. The
3435 * mips assembler simply uses register $zero. Just one tiny optimization
3440 struct mips_cl_insn
*ip
;
3442 register int treg
, sreg
, dreg
, breg
;
3458 bfd_reloc_code_real_type r
;
3460 int hold_mips_optimize
;
3462 assert (! mips_opts
.mips16
);
3464 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
3465 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
3466 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
3467 mask
= ip
->insn_mo
->mask
;
3469 expr1
.X_op
= O_constant
;
3470 expr1
.X_op_symbol
= NULL
;
3471 expr1
.X_add_symbol
= NULL
;
3472 expr1
.X_add_number
= 1;
3484 mips_emit_delays (true);
3485 ++mips_opts
.noreorder
;
3486 mips_any_noreorder
= 1;
3488 expr1
.X_add_number
= 8;
3489 macro_build ((char *) NULL
, &icnt
, &expr1
, "bgez", "s,p", sreg
);
3491 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3493 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, sreg
, 0);
3494 macro_build ((char *) NULL
, &icnt
, NULL
,
3495 dbl
? "dsub" : "sub",
3496 "d,v,t", dreg
, 0, sreg
);
3498 --mips_opts
.noreorder
;
3519 if (imm_expr
.X_op
== O_constant
3520 && imm_expr
.X_add_number
>= -0x8000
3521 && imm_expr
.X_add_number
< 0x8000)
3523 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,j", treg
, sreg
,
3524 (int) BFD_RELOC_LO16
);
3527 load_register (&icnt
, AT
, &imm_expr
, dbl
);
3528 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3547 if (imm_expr
.X_op
== O_constant
3548 && imm_expr
.X_add_number
>= 0
3549 && imm_expr
.X_add_number
< 0x10000)
3551 if (mask
!= M_NOR_I
)
3552 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, "t,r,i", treg
,
3553 sreg
, (int) BFD_RELOC_LO16
);
3556 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "ori", "t,r,i",
3557 treg
, sreg
, (int) BFD_RELOC_LO16
);
3558 macro_build ((char *) NULL
, &icnt
, NULL
, "nor", "d,v,t",
3564 load_register (&icnt
, AT
, &imm_expr
, 0);
3565 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d,v,t", treg
, sreg
, AT
);
3582 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3584 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
,
3588 load_register (&icnt
, AT
, &imm_expr
, 0);
3589 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "s,t,p", sreg
, AT
);
3597 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3598 likely
? "bgezl" : "bgez",
3604 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3605 likely
? "blezl" : "blez",
3609 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3610 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3611 likely
? "beql" : "beq",
3618 /* check for > max integer */
3619 maxnum
= 0x7fffffff;
3620 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3627 if (imm_expr
.X_op
== O_constant
3628 && imm_expr
.X_add_number
>= maxnum
3629 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3632 /* result is always false */
3635 as_warn (_("Branch %s is always false (nop)"), ip
->insn_mo
->name
);
3636 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
3640 as_warn (_("Branch likely %s is always false"), ip
->insn_mo
->name
);
3641 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bnel",
3646 if (imm_expr
.X_op
!= O_constant
)
3647 as_bad (_("Unsupported large constant"));
3648 imm_expr
.X_add_number
++;
3652 if (mask
== M_BGEL_I
)
3654 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3656 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3657 likely
? "bgezl" : "bgez",
3661 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3663 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3664 likely
? "bgtzl" : "bgtz",
3668 maxnum
= 0x7fffffff;
3669 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3676 maxnum
= - maxnum
- 1;
3677 if (imm_expr
.X_op
== O_constant
3678 && imm_expr
.X_add_number
<= maxnum
3679 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3682 /* result is always true */
3683 as_warn (_("Branch %s is always true"), ip
->insn_mo
->name
);
3684 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
3687 set_at (&icnt
, sreg
, 0);
3688 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3689 likely
? "beql" : "beq",
3700 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3701 likely
? "beql" : "beq",
3705 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3707 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3708 likely
? "beql" : "beq",
3716 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3717 && imm_expr
.X_op
== O_constant
3718 && imm_expr
.X_add_number
== 0xffffffff))
3720 if (imm_expr
.X_op
!= O_constant
)
3721 as_bad (_("Unsupported large constant"));
3722 imm_expr
.X_add_number
++;
3726 if (mask
== M_BGEUL_I
)
3728 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3730 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3732 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3733 likely
? "bnel" : "bne",
3737 set_at (&icnt
, sreg
, 1);
3738 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3739 likely
? "beql" : "beq",
3748 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3749 likely
? "bgtzl" : "bgtz",
3755 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3756 likely
? "bltzl" : "bltz",
3760 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3761 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3762 likely
? "bnel" : "bne",
3771 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3772 likely
? "bnel" : "bne",
3778 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3780 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3781 likely
? "bnel" : "bne",
3790 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3791 likely
? "blezl" : "blez",
3797 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3798 likely
? "bgezl" : "bgez",
3802 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, treg
, sreg
);
3803 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3804 likely
? "beql" : "beq",
3811 maxnum
= 0x7fffffff;
3812 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
) && sizeof (maxnum
) > 4)
3819 if (imm_expr
.X_op
== O_constant
3820 && imm_expr
.X_add_number
>= maxnum
3821 && (! ISA_HAS_64BIT_REGS (mips_opts
.isa
) || sizeof (maxnum
) > 4))
3823 if (imm_expr
.X_op
!= O_constant
)
3824 as_bad (_("Unsupported large constant"));
3825 imm_expr
.X_add_number
++;
3829 if (mask
== M_BLTL_I
)
3831 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3833 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3834 likely
? "bltzl" : "bltz",
3838 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3840 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3841 likely
? "blezl" : "blez",
3845 set_at (&icnt
, sreg
, 0);
3846 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3847 likely
? "bnel" : "bne",
3856 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3857 likely
? "beql" : "beq",
3863 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, treg
,
3865 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3866 likely
? "beql" : "beq",
3874 || (! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
3875 && imm_expr
.X_op
== O_constant
3876 && imm_expr
.X_add_number
== 0xffffffff))
3878 if (imm_expr
.X_op
!= O_constant
)
3879 as_bad (_("Unsupported large constant"));
3880 imm_expr
.X_add_number
++;
3884 if (mask
== M_BLTUL_I
)
3886 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
3888 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
3890 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3891 likely
? "beql" : "beq",
3895 set_at (&icnt
, sreg
, 1);
3896 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3897 likely
? "bnel" : "bne",
3906 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3907 likely
? "bltzl" : "bltz",
3913 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3914 likely
? "bgtzl" : "bgtz",
3918 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", AT
, sreg
, treg
);
3919 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3920 likely
? "bnel" : "bne",
3931 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3932 likely
? "bnel" : "bne",
3936 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", AT
, sreg
,
3938 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
3939 likely
? "bnel" : "bne",
3955 as_warn (_("Divide by zero."));
3957 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
3959 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3963 mips_emit_delays (true);
3964 ++mips_opts
.noreorder
;
3965 mips_any_noreorder
= 1;
3968 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
3969 macro_build ((char *) NULL
, &icnt
, NULL
,
3970 dbl
? "ddiv" : "div",
3971 "z,s,t", sreg
, treg
);
3975 expr1
.X_add_number
= 8;
3976 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
3977 macro_build ((char *) NULL
, &icnt
, NULL
,
3978 dbl
? "ddiv" : "div",
3979 "z,s,t", sreg
, treg
);
3980 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
3982 expr1
.X_add_number
= -1;
3983 macro_build ((char *) NULL
, &icnt
, &expr1
,
3984 dbl
? "daddiu" : "addiu",
3985 "t,r,j", AT
, 0, (int) BFD_RELOC_LO16
);
3986 expr1
.X_add_number
= mips_trap
? (dbl
? 12 : 8) : (dbl
? 20 : 16);
3987 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, AT
);
3990 expr1
.X_add_number
= 1;
3991 macro_build ((char *) NULL
, &icnt
, &expr1
, "daddiu", "t,r,j", AT
, 0,
3992 (int) BFD_RELOC_LO16
);
3993 macro_build ((char *) NULL
, &icnt
, NULL
, "dsll32", "d,w,<", AT
, AT
,
3998 expr1
.X_add_number
= 0x80000000;
3999 macro_build ((char *) NULL
, &icnt
, &expr1
, "lui", "t,u", AT
,
4000 (int) BFD_RELOC_HI16
);
4004 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", sreg
, AT
);
4005 /* We want to close the noreorder block as soon as possible, so
4006 that later insns are available for delay slot filling. */
4007 --mips_opts
.noreorder
;
4011 expr1
.X_add_number
= 8;
4012 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", sreg
, AT
);
4013 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
4015 /* We want to close the noreorder block as soon as possible, so
4016 that later insns are available for delay slot filling. */
4017 --mips_opts
.noreorder
;
4019 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
4021 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d", dreg
);
4060 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
4062 as_warn (_("Divide by zero."));
4064 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", 0, 0);
4066 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4069 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 1)
4071 if (strcmp (s2
, "mflo") == 0)
4072 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
,
4075 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4078 if (imm_expr
.X_op
== O_constant
4079 && imm_expr
.X_add_number
== -1
4080 && s
[strlen (s
) - 1] != 'u')
4082 if (strcmp (s2
, "mflo") == 0)
4085 macro_build ((char *) NULL
, &icnt
, NULL
, "dneg", "d,w", dreg
,
4088 macro_build ((char *) NULL
, &icnt
, NULL
, "neg", "d,w", dreg
,
4092 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
4096 load_register (&icnt
, AT
, &imm_expr
, dbl
);
4097 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, AT
);
4098 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4117 mips_emit_delays (true);
4118 ++mips_opts
.noreorder
;
4119 mips_any_noreorder
= 1;
4122 macro_build ((char *) NULL
, &icnt
, NULL
, "teq", "s,t", treg
, 0);
4123 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4124 /* We want to close the noreorder block as soon as possible, so
4125 that later insns are available for delay slot filling. */
4126 --mips_opts
.noreorder
;
4130 expr1
.X_add_number
= 8;
4131 macro_build ((char *) NULL
, &icnt
, &expr1
, "bne", "s,t,p", treg
, 0);
4132 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "z,s,t", sreg
, treg
);
4134 /* We want to close the noreorder block as soon as possible, so
4135 that later insns are available for delay slot filling. */
4136 --mips_opts
.noreorder
;
4137 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 7);
4139 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "d", dreg
);
4145 /* Load the address of a symbol into a register. If breg is not
4146 zero, we then add a base register to it. */
4148 /* When generating embedded PIC code, we permit expressions of
4151 where bar is an address in the current section. These are used
4152 when getting the addresses of functions. We don't permit
4153 X_add_number to be non-zero, because if the symbol is
4154 external the relaxing code needs to know that any addend is
4155 purely the offset to X_op_symbol. */
4156 if (mips_pic
== EMBEDDED_PIC
4157 && offset_expr
.X_op
== O_subtract
4158 && (symbol_constant_p (offset_expr
.X_op_symbol
)
4159 ? S_GET_SEGMENT (offset_expr
.X_op_symbol
) == now_seg
4160 : (symbol_equated_p (offset_expr
.X_op_symbol
)
4162 (symbol_get_value_expression (offset_expr
.X_op_symbol
)
4166 && (offset_expr
.X_add_number
== 0
4167 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
))
4169 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4170 treg
, (int) BFD_RELOC_PCREL_HI16_S
);
4171 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4172 ((bfd_arch_bits_per_address (stdoutput
) == 32
4173 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4174 ? "addiu" : "daddiu"),
4175 "t,r,j", treg
, treg
, (int) BFD_RELOC_PCREL_LO16
);
4179 if (offset_expr
.X_op
!= O_symbol
4180 && offset_expr
.X_op
!= O_constant
)
4182 as_bad (_("expression too complex"));
4183 offset_expr
.X_op
= O_constant
;
4197 if (offset_expr
.X_op
== O_constant
)
4198 load_register (&icnt
, tempreg
, &offset_expr
, dbl
);
4199 else if (mips_pic
== NO_PIC
)
4201 /* If this is a reference to an GP relative symbol, we want
4202 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4204 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4205 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4206 If we have a constant, we need two instructions anyhow,
4207 so we may as well always use the latter form. */
4208 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4209 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
4214 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4215 ((bfd_arch_bits_per_address (stdoutput
) == 32
4216 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4217 ? "addiu" : "daddiu"),
4218 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4219 p
= frag_var (rs_machine_dependent
, 8, 0,
4220 RELAX_ENCODE (4, 8, 0, 4, 0,
4221 mips_opts
.warn_about_macros
),
4222 offset_expr
.X_add_symbol
, (offsetT
) 0,
4225 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
4228 macro_build (p
, &icnt
, &offset_expr
,
4229 ((bfd_arch_bits_per_address (stdoutput
) == 32
4230 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4231 ? "addiu" : "daddiu"),
4232 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4234 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
4236 /* If this is a reference to an external symbol, and there
4237 is no constant, we want
4238 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4239 For a local symbol, we want
4240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4242 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4244 If we have a small constant, and this is a reference to
4245 an external symbol, we want
4246 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4248 addiu $tempreg,$tempreg,<constant>
4249 For a local symbol, we want the same instruction
4250 sequence, but we output a BFD_RELOC_LO16 reloc on the
4253 If we have a large constant, and this is a reference to
4254 an external symbol, we want
4255 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4256 lui $at,<hiconstant>
4257 addiu $at,$at,<loconstant>
4258 addu $tempreg,$tempreg,$at
4259 For a local symbol, we want the same instruction
4260 sequence, but we output a BFD_RELOC_LO16 reloc on the
4261 addiu instruction. */
4262 expr1
.X_add_number
= offset_expr
.X_add_number
;
4263 offset_expr
.X_add_number
= 0;
4265 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4267 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4268 if (expr1
.X_add_number
== 0)
4276 /* We're going to put in an addu instruction using
4277 tempreg, so we may as well insert the nop right
4279 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4283 p
= frag_var (rs_machine_dependent
, 8 - off
, 0,
4284 RELAX_ENCODE (0, 8 - off
, -4 - off
, 4 - off
, 0,
4286 ? mips_opts
.warn_about_macros
4288 offset_expr
.X_add_symbol
, (offsetT
) 0,
4292 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4295 macro_build (p
, &icnt
, &expr1
,
4296 ((bfd_arch_bits_per_address (stdoutput
) == 32
4297 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4298 ? "addiu" : "daddiu"),
4299 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4300 /* FIXME: If breg == 0, and the next instruction uses
4301 $tempreg, then if this variant case is used an extra
4302 nop will be generated. */
4304 else if (expr1
.X_add_number
>= -0x8000
4305 && expr1
.X_add_number
< 0x8000)
4307 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4309 macro_build ((char *) NULL
, &icnt
, &expr1
,
4310 ((bfd_arch_bits_per_address (stdoutput
) == 32
4311 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4312 ? "addiu" : "daddiu"),
4313 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4314 (void) frag_var (rs_machine_dependent
, 0, 0,
4315 RELAX_ENCODE (0, 0, -12, -4, 0, 0),
4316 offset_expr
.X_add_symbol
, (offsetT
) 0,
4323 /* If we are going to add in a base register, and the
4324 target register and the base register are the same,
4325 then we are using AT as a temporary register. Since
4326 we want to load the constant into AT, we add our
4327 current AT (from the global offset table) and the
4328 register into the register now, and pretend we were
4329 not using a base register. */
4334 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4336 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4337 ((bfd_arch_bits_per_address (stdoutput
) == 32
4338 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4339 ? "addu" : "daddu"),
4340 "d,v,t", treg
, AT
, breg
);
4346 /* Set mips_optimize around the lui instruction to avoid
4347 inserting an unnecessary nop after the lw. */
4348 hold_mips_optimize
= mips_optimize
;
4350 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4351 mips_optimize
= hold_mips_optimize
;
4353 macro_build ((char *) NULL
, &icnt
, &expr1
,
4354 ((bfd_arch_bits_per_address (stdoutput
) == 32
4355 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4356 ? "addiu" : "daddiu"),
4357 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4358 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4359 ((bfd_arch_bits_per_address (stdoutput
) == 32
4360 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4361 ? "addu" : "daddu"),
4362 "d,v,t", tempreg
, tempreg
, AT
);
4363 (void) frag_var (rs_machine_dependent
, 0, 0,
4364 RELAX_ENCODE (0, 0, -16 + off1
, -8, 0, 0),
4365 offset_expr
.X_add_symbol
, (offsetT
) 0,
4370 else if (mips_pic
== SVR4_PIC
)
4374 /* This is the large GOT case. If this is a reference to an
4375 external symbol, and there is no constant, we want
4376 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4377 addu $tempreg,$tempreg,$gp
4378 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4379 For a local symbol, we want
4380 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4382 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4384 If we have a small constant, and this is a reference to
4385 an external symbol, we want
4386 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4387 addu $tempreg,$tempreg,$gp
4388 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4390 addiu $tempreg,$tempreg,<constant>
4391 For a local symbol, we want
4392 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4394 addiu $tempreg,$tempreg,<constant> (BFD_RELOC_LO16)
4396 If we have a large constant, and this is a reference to
4397 an external symbol, we want
4398 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
4399 addu $tempreg,$tempreg,$gp
4400 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
4401 lui $at,<hiconstant>
4402 addiu $at,$at,<loconstant>
4403 addu $tempreg,$tempreg,$at
4404 For a local symbol, we want
4405 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4406 lui $at,<hiconstant>
4407 addiu $at,$at,<loconstant> (BFD_RELOC_LO16)
4408 addu $tempreg,$tempreg,$at
4410 expr1
.X_add_number
= offset_expr
.X_add_number
;
4411 offset_expr
.X_add_number
= 0;
4413 if (reg_needs_delay (GP
))
4417 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4418 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
4419 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4420 ((bfd_arch_bits_per_address (stdoutput
) == 32
4421 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4422 ? "addu" : "daddu"),
4423 "d,v,t", tempreg
, tempreg
, GP
);
4424 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4426 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
4428 if (expr1
.X_add_number
== 0)
4436 /* We're going to put in an addu instruction using
4437 tempreg, so we may as well insert the nop right
4439 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4444 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4445 RELAX_ENCODE (12 + off
, 12 + gpdel
, gpdel
,
4448 ? mips_opts
.warn_about_macros
4450 offset_expr
.X_add_symbol
, (offsetT
) 0,
4453 else if (expr1
.X_add_number
>= -0x8000
4454 && expr1
.X_add_number
< 0x8000)
4456 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4458 macro_build ((char *) NULL
, &icnt
, &expr1
,
4459 ((bfd_arch_bits_per_address (stdoutput
) == 32
4460 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4461 ? "addiu" : "daddiu"),
4462 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4464 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4465 RELAX_ENCODE (20, 12 + gpdel
, gpdel
, 8 + gpdel
, 0,
4467 ? mips_opts
.warn_about_macros
4469 offset_expr
.X_add_symbol
, (offsetT
) 0,
4476 /* If we are going to add in a base register, and the
4477 target register and the base register are the same,
4478 then we are using AT as a temporary register. Since
4479 we want to load the constant into AT, we add our
4480 current AT (from the global offset table) and the
4481 register into the register now, and pretend we were
4482 not using a base register. */
4490 assert (tempreg
== AT
);
4491 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4493 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4494 ((bfd_arch_bits_per_address (stdoutput
) == 32
4495 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4496 ? "addu" : "daddu"),
4497 "d,v,t", treg
, AT
, breg
);
4502 /* Set mips_optimize around the lui instruction to avoid
4503 inserting an unnecessary nop after the lw. */
4504 hold_mips_optimize
= mips_optimize
;
4506 macro_build_lui ((char *) NULL
, &icnt
, &expr1
, AT
);
4507 mips_optimize
= hold_mips_optimize
;
4509 macro_build ((char *) NULL
, &icnt
, &expr1
,
4510 ((bfd_arch_bits_per_address (stdoutput
) == 32
4511 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4512 ? "addiu" : "daddiu"),
4513 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4514 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4515 ((bfd_arch_bits_per_address (stdoutput
) == 32
4516 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4517 ? "addu" : "daddu"),
4518 "d,v,t", dreg
, dreg
, AT
);
4520 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ adj
, 0,
4521 RELAX_ENCODE (24 + adj
, 16 + gpdel
+ adj
, gpdel
,
4524 ? mips_opts
.warn_about_macros
4526 offset_expr
.X_add_symbol
, (offsetT
) 0,
4534 /* This is needed because this instruction uses $gp, but
4535 the first instruction on the main stream does not. */
4536 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4539 macro_build (p
, &icnt
, &offset_expr
,
4541 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
4543 if (expr1
.X_add_number
>= -0x8000
4544 && expr1
.X_add_number
< 0x8000)
4546 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4548 macro_build (p
, &icnt
, &expr1
,
4549 ((bfd_arch_bits_per_address (stdoutput
) == 32
4550 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4551 ? "addiu" : "daddiu"),
4552 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
4553 /* FIXME: If add_number is 0, and there was no base
4554 register, the external symbol case ended with a load,
4555 so if the symbol turns out to not be external, and
4556 the next instruction uses tempreg, an unnecessary nop
4557 will be inserted. */
4563 /* We must add in the base register now, as in the
4564 external symbol case. */
4565 assert (tempreg
== AT
);
4566 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4568 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4569 ((bfd_arch_bits_per_address (stdoutput
) == 32
4570 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4571 ? "addu" : "daddu"),
4572 "d,v,t", treg
, AT
, breg
);
4575 /* We set breg to 0 because we have arranged to add
4576 it in in both cases. */
4580 macro_build_lui (p
, &icnt
, &expr1
, AT
);
4582 macro_build (p
, &icnt
, &expr1
,
4583 ((bfd_arch_bits_per_address (stdoutput
) == 32
4584 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4585 ? "addiu" : "daddiu"),
4586 "t,r,j", AT
, AT
, (int) BFD_RELOC_LO16
);
4588 macro_build (p
, &icnt
, (expressionS
*) NULL
,
4589 ((bfd_arch_bits_per_address (stdoutput
) == 32
4590 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4591 ? "addu" : "daddu"),
4592 "d,v,t", tempreg
, tempreg
, AT
);
4596 else if (mips_pic
== EMBEDDED_PIC
)
4599 addiu $tempreg,$gp,<sym> (BFD_RELOC_MIPS_GPREL)
4601 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4602 ((bfd_arch_bits_per_address (stdoutput
) == 32
4603 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4604 ? "addiu" : "daddiu"),
4605 "t,r,j", tempreg
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
4611 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4612 ((bfd_arch_bits_per_address (stdoutput
) == 32
4613 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4614 ? "addu" : "daddu"),
4615 "d,v,t", treg
, tempreg
, breg
);
4623 /* The j instruction may not be used in PIC code, since it
4624 requires an absolute address. We convert it to a b
4626 if (mips_pic
== NO_PIC
)
4627 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "j", "a");
4629 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "b", "p");
4632 /* The jal instructions must be handled as macros because when
4633 generating PIC code they expand to multi-instruction
4634 sequences. Normally they are simple instructions. */
4639 if (mips_pic
== NO_PIC
4640 || mips_pic
== EMBEDDED_PIC
)
4641 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4643 else if (mips_pic
== SVR4_PIC
)
4645 if (sreg
!= PIC_CALL_REG
)
4646 as_warn (_("MIPS PIC call to register other than $25"));
4648 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "jalr",
4650 if (mips_cprestore_offset
< 0)
4651 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4654 expr1
.X_add_number
= mips_cprestore_offset
;
4655 macro_build ((char *) NULL
, &icnt
, &expr1
,
4656 ((bfd_arch_bits_per_address (stdoutput
) == 32
4657 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4659 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, mips_frame_reg
);
4668 if (mips_pic
== NO_PIC
)
4669 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "jal", "a");
4670 else if (mips_pic
== SVR4_PIC
)
4672 /* If this is a reference to an external symbol, and we are
4673 using a small GOT, we want
4674 lw $25,<sym>($gp) (BFD_RELOC_MIPS_CALL16)
4678 lw $gp,cprestore($sp)
4679 The cprestore value is set using the .cprestore
4680 pseudo-op. If we are using a big GOT, we want
4681 lui $25,<sym> (BFD_RELOC_MIPS_CALL_HI16)
4683 lw $25,<sym>($25) (BFD_RELOC_MIPS_CALL_LO16)
4687 lw $gp,cprestore($sp)
4688 If the symbol is not external, we want
4689 lw $25,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
4691 addiu $25,$25,<sym> (BFD_RELOC_LO16)
4694 lw $gp,cprestore($sp) */
4698 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4699 ((bfd_arch_bits_per_address (stdoutput
) == 32
4700 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4702 "t,o(b)", PIC_CALL_REG
,
4703 (int) BFD_RELOC_MIPS_CALL16
, GP
);
4704 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4706 p
= frag_var (rs_machine_dependent
, 4, 0,
4707 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
4708 offset_expr
.X_add_symbol
, (offsetT
) 0,
4715 if (reg_needs_delay (GP
))
4719 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
4720 PIC_CALL_REG
, (int) BFD_RELOC_MIPS_CALL_HI16
);
4721 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4722 ((bfd_arch_bits_per_address (stdoutput
) == 32
4723 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4724 ? "addu" : "daddu"),
4725 "d,v,t", PIC_CALL_REG
, PIC_CALL_REG
, GP
);
4726 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
4727 ((bfd_arch_bits_per_address (stdoutput
) == 32
4728 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4730 "t,o(b)", PIC_CALL_REG
,
4731 (int) BFD_RELOC_MIPS_CALL_LO16
, PIC_CALL_REG
);
4732 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4734 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
4735 RELAX_ENCODE (16, 12 + gpdel
, gpdel
, 8 + gpdel
,
4737 offset_expr
.X_add_symbol
, (offsetT
) 0,
4741 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4744 macro_build (p
, &icnt
, &offset_expr
,
4745 ((bfd_arch_bits_per_address (stdoutput
) == 32
4746 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4748 "t,o(b)", PIC_CALL_REG
,
4749 (int) BFD_RELOC_MIPS_GOT16
, GP
);
4751 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
4754 macro_build (p
, &icnt
, &offset_expr
,
4755 ((bfd_arch_bits_per_address (stdoutput
) == 32
4756 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4757 ? "addiu" : "daddiu"),
4758 "t,r,j", PIC_CALL_REG
, PIC_CALL_REG
,
4759 (int) BFD_RELOC_LO16
);
4760 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4761 "jalr", "s", PIC_CALL_REG
);
4762 if (mips_cprestore_offset
< 0)
4763 as_warn (_("No .cprestore pseudo-op used in PIC code"));
4766 if (mips_opts
.noreorder
)
4767 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
4769 expr1
.X_add_number
= mips_cprestore_offset
;
4770 macro_build ((char *) NULL
, &icnt
, &expr1
,
4771 ((bfd_arch_bits_per_address (stdoutput
) == 32
4772 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
4774 "t,o(b)", GP
, (int) BFD_RELOC_LO16
,
4778 else if (mips_pic
== EMBEDDED_PIC
)
4780 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "bal", "p");
4781 /* The linker may expand the call to a longer sequence which
4782 uses $at, so we must break rather than return. */
4807 /* Itbl support may require additional care here. */
4812 /* Itbl support may require additional care here. */
4817 /* Itbl support may require additional care here. */
4822 /* Itbl support may require additional care here. */
4834 if (mips_cpu
== 4650)
4836 as_bad (_("opcode not supported on this processor"));
4840 /* Itbl support may require additional care here. */
4845 /* Itbl support may require additional care here. */
4850 /* Itbl support may require additional care here. */
4870 if (breg
== treg
|| coproc
|| lr
)
4892 /* Itbl support may require additional care here. */
4897 /* Itbl support may require additional care here. */
4902 /* Itbl support may require additional care here. */
4907 /* Itbl support may require additional care here. */
4923 if (mips_cpu
== 4650)
4925 as_bad (_("opcode not supported on this processor"));
4930 /* Itbl support may require additional care here. */
4934 /* Itbl support may require additional care here. */
4939 /* Itbl support may require additional care here. */
4951 /* Itbl support may require additional care here. */
4952 if (mask
== M_LWC1_AB
4953 || mask
== M_SWC1_AB
4954 || mask
== M_LDC1_AB
4955 || mask
== M_SDC1_AB
4964 if (offset_expr
.X_op
!= O_constant
4965 && offset_expr
.X_op
!= O_symbol
)
4967 as_bad (_("expression too complex"));
4968 offset_expr
.X_op
= O_constant
;
4971 /* A constant expression in PIC code can be handled just as it
4972 is in non PIC code. */
4973 if (mips_pic
== NO_PIC
4974 || offset_expr
.X_op
== O_constant
)
4976 /* If this is a reference to a GP relative symbol, and there
4977 is no base register, we want
4978 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
4979 Otherwise, if there is no base register, we want
4980 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4981 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4982 If we have a constant, we need two instructions anyhow,
4983 so we always use the latter form.
4985 If we have a base register, and this is a reference to a
4986 GP relative symbol, we want
4987 addu $tempreg,$breg,$gp
4988 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
4990 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4991 addu $tempreg,$tempreg,$breg
4992 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
4993 With a constant we always use the latter case. */
4996 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
4997 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5002 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5003 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5004 p
= frag_var (rs_machine_dependent
, 8, 0,
5005 RELAX_ENCODE (4, 8, 0, 4, 0,
5006 (mips_opts
.warn_about_macros
5008 && mips_opts
.noat
))),
5009 offset_expr
.X_add_symbol
, (offsetT
) 0,
5013 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5016 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5017 (int) BFD_RELOC_LO16
, tempreg
);
5021 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5022 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5027 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5028 ((bfd_arch_bits_per_address (stdoutput
) == 32
5029 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5030 ? "addu" : "daddu"),
5031 "d,v,t", tempreg
, breg
, GP
);
5032 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5033 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5034 p
= frag_var (rs_machine_dependent
, 12, 0,
5035 RELAX_ENCODE (8, 12, 0, 8, 0, 0),
5036 offset_expr
.X_add_symbol
, (offsetT
) 0,
5039 macro_build_lui (p
, &icnt
, &offset_expr
, tempreg
);
5042 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5043 ((bfd_arch_bits_per_address (stdoutput
) == 32
5044 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5045 ? "addu" : "daddu"),
5046 "d,v,t", tempreg
, tempreg
, breg
);
5049 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
, treg
,
5050 (int) BFD_RELOC_LO16
, tempreg
);
5053 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5055 /* If this is a reference to an external symbol, we want
5056 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5058 <op> $treg,0($tempreg)
5060 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5062 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5063 <op> $treg,0($tempreg)
5064 If there is a base register, we add it to $tempreg before
5065 the <op>. If there is a constant, we stick it in the
5066 <op> instruction. We don't handle constants larger than
5067 16 bits, because we have no way to load the upper 16 bits
5068 (actually, we could handle them for the subset of cases
5069 in which we are not using $at). */
5070 assert (offset_expr
.X_op
== O_symbol
);
5071 expr1
.X_add_number
= offset_expr
.X_add_number
;
5072 offset_expr
.X_add_number
= 0;
5073 if (expr1
.X_add_number
< -0x8000
5074 || expr1
.X_add_number
>= 0x8000)
5075 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5077 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5078 ((bfd_arch_bits_per_address (stdoutput
) == 32
5079 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5081 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5082 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5083 p
= frag_var (rs_machine_dependent
, 4, 0,
5084 RELAX_ENCODE (0, 4, -8, 0, 0, 0),
5085 offset_expr
.X_add_symbol
, (offsetT
) 0,
5087 macro_build (p
, &icnt
, &offset_expr
,
5088 ((bfd_arch_bits_per_address (stdoutput
) == 32
5089 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5090 ? "addiu" : "daddiu"),
5091 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5093 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5094 ((bfd_arch_bits_per_address (stdoutput
) == 32
5095 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5096 ? "addu" : "daddu"),
5097 "d,v,t", tempreg
, tempreg
, breg
);
5098 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5099 (int) BFD_RELOC_LO16
, tempreg
);
5101 else if (mips_pic
== SVR4_PIC
)
5105 /* If this is a reference to an external symbol, we want
5106 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5107 addu $tempreg,$tempreg,$gp
5108 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
5109 <op> $treg,0($tempreg)
5111 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5113 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
5114 <op> $treg,0($tempreg)
5115 If there is a base register, we add it to $tempreg before
5116 the <op>. If there is a constant, we stick it in the
5117 <op> instruction. We don't handle constants larger than
5118 16 bits, because we have no way to load the upper 16 bits
5119 (actually, we could handle them for the subset of cases
5120 in which we are not using $at). */
5121 assert (offset_expr
.X_op
== O_symbol
);
5122 expr1
.X_add_number
= offset_expr
.X_add_number
;
5123 offset_expr
.X_add_number
= 0;
5124 if (expr1
.X_add_number
< -0x8000
5125 || expr1
.X_add_number
>= 0x8000)
5126 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5127 if (reg_needs_delay (GP
))
5132 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5133 tempreg
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5134 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5135 ((bfd_arch_bits_per_address (stdoutput
) == 32
5136 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5137 ? "addu" : "daddu"),
5138 "d,v,t", tempreg
, tempreg
, GP
);
5139 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5140 ((bfd_arch_bits_per_address (stdoutput
) == 32
5141 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5143 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT_LO16
,
5145 p
= frag_var (rs_machine_dependent
, 12 + gpdel
, 0,
5146 RELAX_ENCODE (12, 12 + gpdel
, gpdel
, 8 + gpdel
, 0, 0),
5147 offset_expr
.X_add_symbol
, (offsetT
) 0, (char *) NULL
);
5150 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5153 macro_build (p
, &icnt
, &offset_expr
,
5154 ((bfd_arch_bits_per_address (stdoutput
) == 32
5155 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5157 "t,o(b)", tempreg
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5159 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5161 macro_build (p
, &icnt
, &offset_expr
,
5162 ((bfd_arch_bits_per_address (stdoutput
) == 32
5163 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5164 ? "addiu" : "daddiu"),
5165 "t,r,j", tempreg
, tempreg
, (int) BFD_RELOC_LO16
);
5167 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5168 ((bfd_arch_bits_per_address (stdoutput
) == 32
5169 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5170 ? "addu" : "daddu"),
5171 "d,v,t", tempreg
, tempreg
, breg
);
5172 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
, treg
,
5173 (int) BFD_RELOC_LO16
, tempreg
);
5175 else if (mips_pic
== EMBEDDED_PIC
)
5177 /* If there is no base register, we want
5178 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5179 If there is a base register, we want
5180 addu $tempreg,$breg,$gp
5181 <op> $treg,<sym>($tempreg) (BFD_RELOC_MIPS_GPREL)
5183 assert (offset_expr
.X_op
== O_symbol
);
5186 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5187 treg
, (int) BFD_RELOC_MIPS_GPREL
, GP
);
5192 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5193 ((bfd_arch_bits_per_address (stdoutput
) == 32
5194 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5195 ? "addu" : "daddu"),
5196 "d,v,t", tempreg
, breg
, GP
);
5197 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5198 treg
, (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5211 load_register (&icnt
, treg
, &imm_expr
, 0);
5215 load_register (&icnt
, treg
, &imm_expr
, 1);
5219 if (imm_expr
.X_op
== O_constant
)
5221 load_register (&icnt
, AT
, &imm_expr
, 0);
5222 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5223 "mtc1", "t,G", AT
, treg
);
5228 assert (offset_expr
.X_op
== O_symbol
5229 && strcmp (segment_name (S_GET_SEGMENT
5230 (offset_expr
.X_add_symbol
)),
5232 && offset_expr
.X_add_number
== 0);
5233 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5234 treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5239 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5240 the entire value, and in mips1 mode it is the high order 32
5241 bits of the value and the low order 32 bits are either zero
5242 or in offset_expr. */
5243 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5245 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5246 load_register (&icnt
, treg
, &imm_expr
, 1);
5251 if (target_big_endian
)
5263 load_register (&icnt
, hreg
, &imm_expr
, 0);
5266 if (offset_expr
.X_op
== O_absent
)
5267 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s",
5271 assert (offset_expr
.X_op
== O_constant
);
5272 load_register (&icnt
, lreg
, &offset_expr
, 0);
5279 /* We know that sym is in the .rdata section. First we get the
5280 upper 16 bits of the address. */
5281 if (mips_pic
== NO_PIC
)
5283 /* FIXME: This won't work for a 64 bit address. */
5284 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5286 else if (mips_pic
== SVR4_PIC
)
5288 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5289 ((bfd_arch_bits_per_address (stdoutput
) == 32
5290 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5292 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5294 else if (mips_pic
== EMBEDDED_PIC
)
5296 /* For embedded PIC we pick up the entire address off $gp in
5297 a single instruction. */
5298 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5299 ((bfd_arch_bits_per_address (stdoutput
) == 32
5300 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5301 ? "addiu" : "daddiu"),
5302 "t,r,j", AT
, GP
, (int) BFD_RELOC_MIPS_GPREL
);
5303 offset_expr
.X_op
= O_constant
;
5304 offset_expr
.X_add_number
= 0;
5309 /* Now we load the register(s). */
5310 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5311 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ld", "t,o(b)",
5312 treg
, (int) BFD_RELOC_LO16
, AT
);
5315 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5316 treg
, (int) BFD_RELOC_LO16
, AT
);
5319 /* FIXME: How in the world do we deal with the possible
5321 offset_expr
.X_add_number
+= 4;
5322 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lw", "t,o(b)",
5323 treg
+ 1, (int) BFD_RELOC_LO16
, AT
);
5327 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5328 does not become a variant frag. */
5329 frag_wane (frag_now
);
5335 /* If we have a constant in IMM_EXPR, then in mips3 mode it is
5336 the entire value, and in mips1 mode it is the high order 32
5337 bits of the value and the low order 32 bits are either zero
5338 or in offset_expr. */
5339 if (imm_expr
.X_op
== O_constant
|| imm_expr
.X_op
== O_big
)
5341 load_register (&icnt
, AT
, &imm_expr
, ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5342 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5343 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5344 "dmtc1", "t,S", AT
, treg
);
5347 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5348 "mtc1", "t,G", AT
, treg
+ 1);
5349 if (offset_expr
.X_op
== O_absent
)
5350 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5351 "mtc1", "t,G", 0, treg
);
5354 assert (offset_expr
.X_op
== O_constant
);
5355 load_register (&icnt
, AT
, &offset_expr
, 0);
5356 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5357 "mtc1", "t,G", AT
, treg
);
5363 assert (offset_expr
.X_op
== O_symbol
5364 && offset_expr
.X_add_number
== 0);
5365 s
= segment_name (S_GET_SEGMENT (offset_expr
.X_add_symbol
));
5366 if (strcmp (s
, ".lit8") == 0)
5368 if (mips_opts
.isa
!= 1)
5370 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5371 "T,o(b)", treg
, (int) BFD_RELOC_MIPS_LITERAL
, GP
);
5375 r
= BFD_RELOC_MIPS_LITERAL
;
5380 assert (strcmp (s
, RDATA_SECTION_NAME
) == 0);
5381 if (mips_pic
== SVR4_PIC
)
5382 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5383 ((bfd_arch_bits_per_address (stdoutput
) == 32
5384 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5386 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5389 /* FIXME: This won't work for a 64 bit address. */
5390 macro_build_lui ((char *) NULL
, &icnt
, &offset_expr
, AT
);
5393 if (mips_opts
.isa
!= 1)
5395 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "ldc1",
5396 "T,o(b)", treg
, (int) BFD_RELOC_LO16
, AT
);
5398 /* To avoid confusion in tc_gen_reloc, we must ensure
5399 that this does not become a variant frag. */
5400 frag_wane (frag_now
);
5411 if (mips_cpu
== 4650)
5413 as_bad (_("opcode not supported on this processor"));
5416 /* Even on a big endian machine $fn comes before $fn+1. We have
5417 to adjust when loading from memory. */
5420 assert (mips_opts
.isa
== 1);
5421 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5422 target_big_endian
? treg
+ 1 : treg
,
5424 /* FIXME: A possible overflow which I don't know how to deal
5426 offset_expr
.X_add_number
+= 4;
5427 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lwc1", "T,o(b)",
5428 target_big_endian
? treg
: treg
+ 1,
5431 /* To avoid confusion in tc_gen_reloc, we must ensure that this
5432 does not become a variant frag. */
5433 frag_wane (frag_now
);
5442 * The MIPS assembler seems to check for X_add_number not
5443 * being double aligned and generating:
5446 * addiu at,at,%lo(foo+1)
5449 * But, the resulting address is the same after relocation so why
5450 * generate the extra instruction?
5452 if (mips_cpu
== 4650)
5454 as_bad (_("opcode not supported on this processor"));
5457 /* Itbl support may require additional care here. */
5459 if (mips_opts
.isa
!= 1)
5470 if (mips_cpu
== 4650)
5472 as_bad (_("opcode not supported on this processor"));
5476 if (mips_opts
.isa
!= 1)
5484 /* Itbl support may require additional care here. */
5489 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5500 if (ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5510 if (offset_expr
.X_op
!= O_symbol
5511 && offset_expr
.X_op
!= O_constant
)
5513 as_bad (_("expression too complex"));
5514 offset_expr
.X_op
= O_constant
;
5517 /* Even on a big endian machine $fn comes before $fn+1. We have
5518 to adjust when loading from memory. We set coproc if we must
5519 load $fn+1 first. */
5520 /* Itbl support may require additional care here. */
5521 if (! target_big_endian
)
5524 if (mips_pic
== NO_PIC
5525 || offset_expr
.X_op
== O_constant
)
5527 /* If this is a reference to a GP relative symbol, we want
5528 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5529 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5530 If we have a base register, we use this
5532 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5533 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5534 If this is not a GP relative symbol, we want
5535 lui $at,<sym> (BFD_RELOC_HI16_S)
5536 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5537 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5538 If there is a base register, we add it to $at after the
5539 lui instruction. If there is a constant, we always use
5541 if ((valueT
) offset_expr
.X_add_number
>= MAX_GPREL_OFFSET
5542 || nopic_need_relax (offset_expr
.X_add_symbol
, 1))
5561 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5562 ((bfd_arch_bits_per_address (stdoutput
) == 32
5563 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5564 ? "addu" : "daddu"),
5565 "d,v,t", AT
, breg
, GP
);
5571 /* Itbl support may require additional care here. */
5572 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5573 coproc
? treg
+ 1 : treg
,
5574 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5575 offset_expr
.X_add_number
+= 4;
5577 /* Set mips_optimize to 2 to avoid inserting an
5579 hold_mips_optimize
= mips_optimize
;
5581 /* Itbl support may require additional care here. */
5582 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5583 coproc
? treg
: treg
+ 1,
5584 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5585 mips_optimize
= hold_mips_optimize
;
5587 p
= frag_var (rs_machine_dependent
, 12 + off
, 0,
5588 RELAX_ENCODE (8 + off
, 12 + off
, 0, 4 + off
, 1,
5589 used_at
&& mips_opts
.noat
),
5590 offset_expr
.X_add_symbol
, (offsetT
) 0,
5593 /* We just generated two relocs. When tc_gen_reloc
5594 handles this case, it will skip the first reloc and
5595 handle the second. The second reloc already has an
5596 extra addend of 4, which we added above. We must
5597 subtract it out, and then subtract another 4 to make
5598 the first reloc come out right. The second reloc
5599 will come out right because we are going to add 4 to
5600 offset_expr when we build its instruction below.
5602 If we have a symbol, then we don't want to include
5603 the offset, because it will wind up being included
5604 when we generate the reloc. */
5606 if (offset_expr
.X_op
== O_constant
)
5607 offset_expr
.X_add_number
-= 8;
5610 offset_expr
.X_add_number
= -4;
5611 offset_expr
.X_op
= O_constant
;
5614 macro_build_lui (p
, &icnt
, &offset_expr
, AT
);
5619 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5620 ((bfd_arch_bits_per_address (stdoutput
) == 32
5621 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5622 ? "addu" : "daddu"),
5623 "d,v,t", AT
, breg
, AT
);
5627 /* Itbl support may require additional care here. */
5628 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5629 coproc
? treg
+ 1 : treg
,
5630 (int) BFD_RELOC_LO16
, AT
);
5633 /* FIXME: How do we handle overflow here? */
5634 offset_expr
.X_add_number
+= 4;
5635 /* Itbl support may require additional care here. */
5636 macro_build (p
, &icnt
, &offset_expr
, s
, fmt
,
5637 coproc
? treg
: treg
+ 1,
5638 (int) BFD_RELOC_LO16
, AT
);
5640 else if (mips_pic
== SVR4_PIC
&& ! mips_big_got
)
5644 /* If this is a reference to an external symbol, we want
5645 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5650 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5652 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5653 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5654 If there is a base register we add it to $at before the
5655 lwc1 instructions. If there is a constant we include it
5656 in the lwc1 instructions. */
5658 expr1
.X_add_number
= offset_expr
.X_add_number
;
5659 offset_expr
.X_add_number
= 0;
5660 if (expr1
.X_add_number
< -0x8000
5661 || expr1
.X_add_number
>= 0x8000 - 4)
5662 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5667 frag_grow (24 + off
);
5668 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5669 ((bfd_arch_bits_per_address (stdoutput
) == 32
5670 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5672 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5673 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5675 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5676 ((bfd_arch_bits_per_address (stdoutput
) == 32
5677 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5678 ? "addu" : "daddu"),
5679 "d,v,t", AT
, breg
, AT
);
5680 /* Itbl support may require additional care here. */
5681 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5682 coproc
? treg
+ 1 : treg
,
5683 (int) BFD_RELOC_LO16
, AT
);
5684 expr1
.X_add_number
+= 4;
5686 /* Set mips_optimize to 2 to avoid inserting an undesired
5688 hold_mips_optimize
= mips_optimize
;
5690 /* Itbl support may require additional care here. */
5691 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5692 coproc
? treg
: treg
+ 1,
5693 (int) BFD_RELOC_LO16
, AT
);
5694 mips_optimize
= hold_mips_optimize
;
5696 (void) frag_var (rs_machine_dependent
, 0, 0,
5697 RELAX_ENCODE (0, 0, -16 - off
, -8, 1, 0),
5698 offset_expr
.X_add_symbol
, (offsetT
) 0,
5701 else if (mips_pic
== SVR4_PIC
)
5705 /* If this is a reference to an external symbol, we want
5706 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
5708 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
5713 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5715 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
5716 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
5717 If there is a base register we add it to $at before the
5718 lwc1 instructions. If there is a constant we include it
5719 in the lwc1 instructions. */
5721 expr1
.X_add_number
= offset_expr
.X_add_number
;
5722 offset_expr
.X_add_number
= 0;
5723 if (expr1
.X_add_number
< -0x8000
5724 || expr1
.X_add_number
>= 0x8000 - 4)
5725 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
5726 if (reg_needs_delay (GP
))
5735 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lui", "t,u",
5736 AT
, (int) BFD_RELOC_MIPS_GOT_HI16
);
5737 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5738 ((bfd_arch_bits_per_address (stdoutput
) == 32
5739 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5740 ? "addu" : "daddu"),
5741 "d,v,t", AT
, AT
, GP
);
5742 macro_build ((char *) NULL
, &icnt
, &offset_expr
,
5743 ((bfd_arch_bits_per_address (stdoutput
) == 32
5744 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5746 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT_LO16
, AT
);
5747 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "nop", "");
5749 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5750 ((bfd_arch_bits_per_address (stdoutput
) == 32
5751 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5752 ? "addu" : "daddu"),
5753 "d,v,t", AT
, breg
, AT
);
5754 /* Itbl support may require additional care here. */
5755 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5756 coproc
? treg
+ 1 : treg
,
5757 (int) BFD_RELOC_LO16
, AT
);
5758 expr1
.X_add_number
+= 4;
5760 /* Set mips_optimize to 2 to avoid inserting an undesired
5762 hold_mips_optimize
= mips_optimize
;
5764 /* Itbl support may require additional care here. */
5765 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, fmt
,
5766 coproc
? treg
: treg
+ 1,
5767 (int) BFD_RELOC_LO16
, AT
);
5768 mips_optimize
= hold_mips_optimize
;
5769 expr1
.X_add_number
-= 4;
5771 p
= frag_var (rs_machine_dependent
, 16 + gpdel
+ off
, 0,
5772 RELAX_ENCODE (24 + off
, 16 + gpdel
+ off
, gpdel
,
5773 8 + gpdel
+ off
, 1, 0),
5774 offset_expr
.X_add_symbol
, (offsetT
) 0,
5778 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5781 macro_build (p
, &icnt
, &offset_expr
,
5782 ((bfd_arch_bits_per_address (stdoutput
) == 32
5783 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5785 "t,o(b)", AT
, (int) BFD_RELOC_MIPS_GOT16
, GP
);
5787 macro_build (p
, &icnt
, (expressionS
*) NULL
, "nop", "");
5791 macro_build (p
, &icnt
, (expressionS
*) NULL
,
5792 ((bfd_arch_bits_per_address (stdoutput
) == 32
5793 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5794 ? "addu" : "daddu"),
5795 "d,v,t", AT
, breg
, AT
);
5798 /* Itbl support may require additional care here. */
5799 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5800 coproc
? treg
+ 1 : treg
,
5801 (int) BFD_RELOC_LO16
, AT
);
5803 expr1
.X_add_number
+= 4;
5805 /* Set mips_optimize to 2 to avoid inserting an undesired
5807 hold_mips_optimize
= mips_optimize
;
5809 /* Itbl support may require additional care here. */
5810 macro_build (p
, &icnt
, &expr1
, s
, fmt
,
5811 coproc
? treg
: treg
+ 1,
5812 (int) BFD_RELOC_LO16
, AT
);
5813 mips_optimize
= hold_mips_optimize
;
5815 else if (mips_pic
== EMBEDDED_PIC
)
5817 /* If there is no base register, we use
5818 <op> $treg,<sym>($gp) (BFD_RELOC_MIPS_GPREL)
5819 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_MIPS_GPREL)
5820 If we have a base register, we use
5822 <op> $treg,<sym>($at) (BFD_RELOC_MIPS_GPREL)
5823 <op> $treg+1,<sym>+4($at) (BFD_RELOC_MIPS_GPREL)
5832 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
5833 ((bfd_arch_bits_per_address (stdoutput
) == 32
5834 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
5835 ? "addu" : "daddu"),
5836 "d,v,t", AT
, breg
, GP
);
5841 /* Itbl support may require additional care here. */
5842 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5843 coproc
? treg
+ 1 : treg
,
5844 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5845 offset_expr
.X_add_number
+= 4;
5846 /* Itbl support may require additional care here. */
5847 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, fmt
,
5848 coproc
? treg
: treg
+ 1,
5849 (int) BFD_RELOC_MIPS_GPREL
, tempreg
);
5865 assert (bfd_arch_bits_per_address (stdoutput
) == 32
5866 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
));
5867 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
5868 (int) BFD_RELOC_LO16
, breg
);
5869 offset_expr
.X_add_number
+= 4;
5870 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
+ 1,
5871 (int) BFD_RELOC_LO16
, breg
);
5874 /* New code added to support COPZ instructions.
5875 This code builds table entries out of the macros in mip_opcodes.
5876 R4000 uses interlocks to handle coproc delays.
5877 Other chips (like the R3000) require nops to be inserted for delays.
5879 FIXME: Currently, we require that the user handle delays.
5880 In order to fill delay slots for non-interlocked chips,
5881 we must have a way to specify delays based on the coprocessor.
5882 Eg. 4 cycles if load coproc reg from memory, 1 if in cache, etc.
5883 What are the side-effects of the cop instruction?
5884 What cache support might we have and what are its effects?
5885 Both coprocessor & memory require delays. how long???
5886 What registers are read/set/modified?
5888 If an itbl is provided to interpret cop instructions,
5889 this knowledge can be encoded in the itbl spec. */
5903 /* For now we just do C (same as Cz). The parameter will be
5904 stored in insn_opcode by mips_ip. */
5905 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "C",
5909 #ifdef LOSING_COMPILER
5911 /* Try and see if this is a new itbl instruction.
5912 This code builds table entries out of the macros in mip_opcodes.
5913 FIXME: For now we just assemble the expression and pass it's
5914 value along as a 32-bit immediate.
5915 We may want to have the assembler assemble this value,
5916 so that we gain the assembler's knowledge of delay slots,
5918 Would it be more efficient to use mask (id) here? */
5919 if (itbl_have_entries
5920 && (immed_expr
= itbl_assemble (ip
->insn_mo
->name
, "")))
5922 s
= ip
->insn_mo
->name
;
5924 coproc
= ITBL_DECODE_PNUM (immed_expr
);;
5925 macro_build ((char *) NULL
, &icnt
, &immed_expr
, s
, "C");
5932 as_warn (_("Macro used $at after \".set noat\""));
5937 struct mips_cl_insn
*ip
;
5939 register int treg
, sreg
, dreg
, breg
;
5955 bfd_reloc_code_real_type r
;
5958 treg
= (ip
->insn_opcode
>> 16) & 0x1f;
5959 dreg
= (ip
->insn_opcode
>> 11) & 0x1f;
5960 sreg
= breg
= (ip
->insn_opcode
>> 21) & 0x1f;
5961 mask
= ip
->insn_mo
->mask
;
5963 expr1
.X_op
= O_constant
;
5964 expr1
.X_op_symbol
= NULL
;
5965 expr1
.X_add_symbol
= NULL
;
5966 expr1
.X_add_number
= 1;
5970 #endif /* LOSING_COMPILER */
5975 macro_build ((char *) NULL
, &icnt
, NULL
,
5976 dbl
? "dmultu" : "multu",
5978 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
5984 /* The MIPS assembler some times generates shifts and adds. I'm
5985 not trying to be that fancy. GCC should do this for us
5987 load_register (&icnt
, AT
, &imm_expr
, dbl
);
5988 macro_build ((char *) NULL
, &icnt
, NULL
,
5989 dbl
? "dmult" : "mult",
5991 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6004 mips_emit_delays (true);
6005 ++mips_opts
.noreorder
;
6006 mips_any_noreorder
= 1;
6008 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6009 macro_build ((char *) NULL
, &icnt
, NULL
,
6010 dbl
? "dmult" : "mult",
6011 "s,t", sreg
, imm
? AT
: treg
);
6012 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6013 macro_build ((char *) NULL
, &icnt
, NULL
,
6014 dbl
? "dsra32" : "sra",
6015 "d,w,<", dreg
, dreg
, 31);
6016 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6018 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", dreg
, AT
);
6021 expr1
.X_add_number
= 8;
6022 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", dreg
, AT
);
6023 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6024 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6026 --mips_opts
.noreorder
;
6027 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6040 mips_emit_delays (true);
6041 ++mips_opts
.noreorder
;
6042 mips_any_noreorder
= 1;
6044 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6045 macro_build ((char *) NULL
, &icnt
, NULL
,
6046 dbl
? "dmultu" : "multu",
6047 "s,t", sreg
, imm
? AT
: treg
);
6048 macro_build ((char *) NULL
, &icnt
, NULL
, "mfhi", "d", AT
);
6049 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "d", dreg
);
6051 macro_build ((char *) NULL
, &icnt
, NULL
, "tne", "s,t", AT
, 0);
6054 expr1
.X_add_number
= 8;
6055 macro_build ((char *) NULL
, &icnt
, &expr1
, "beq", "s,t,p", AT
, 0);
6056 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "", 0);
6057 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "c", 6);
6059 --mips_opts
.noreorder
;
6063 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6064 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", AT
, sreg
, AT
);
6065 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", dreg
, sreg
,
6067 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6071 if (imm_expr
.X_op
!= O_constant
)
6072 as_bad (_("rotate count too large"));
6073 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", AT
, sreg
,
6074 (int) (imm_expr
.X_add_number
& 0x1f));
6075 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", dreg
, sreg
,
6076 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6077 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6081 macro_build ((char *) NULL
, &icnt
, NULL
, "subu", "d,v,t", AT
, 0, treg
);
6082 macro_build ((char *) NULL
, &icnt
, NULL
, "sllv", "d,t,s", AT
, sreg
, AT
);
6083 macro_build ((char *) NULL
, &icnt
, NULL
, "srlv", "d,t,s", dreg
, sreg
,
6085 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6089 if (imm_expr
.X_op
!= O_constant
)
6090 as_bad (_("rotate count too large"));
6091 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, sreg
,
6092 (int) (imm_expr
.X_add_number
& 0x1f));
6093 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", dreg
, sreg
,
6094 (int) ((0 - imm_expr
.X_add_number
) & 0x1f));
6095 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", dreg
, dreg
, AT
);
6099 if (mips_cpu
== 4650)
6101 as_bad (_("opcode not supported on this processor"));
6104 assert (mips_opts
.isa
== 1);
6105 /* Even on a big endian machine $fn comes before $fn+1. We have
6106 to adjust when storing to memory. */
6107 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6108 target_big_endian
? treg
+ 1 : treg
,
6109 (int) BFD_RELOC_LO16
, breg
);
6110 offset_expr
.X_add_number
+= 4;
6111 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "swc1", "T,o(b)",
6112 target_big_endian
? treg
: treg
+ 1,
6113 (int) BFD_RELOC_LO16
, breg
);
6118 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6119 treg
, (int) BFD_RELOC_LO16
);
6121 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6122 sreg
, (int) BFD_RELOC_LO16
);
6125 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6127 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6128 dreg
, (int) BFD_RELOC_LO16
);
6133 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6135 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
,
6136 sreg
, (int) BFD_RELOC_LO16
);
6141 as_warn (_("Instruction %s: result is always false"),
6143 macro_build ((char *) NULL
, &icnt
, NULL
, "move", "d,s", dreg
, 0);
6146 if (imm_expr
.X_op
== O_constant
6147 && imm_expr
.X_add_number
>= 0
6148 && imm_expr
.X_add_number
< 0x10000)
6150 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i", dreg
,
6151 sreg
, (int) BFD_RELOC_LO16
);
6154 else if (imm_expr
.X_op
== O_constant
6155 && imm_expr
.X_add_number
> -0x8000
6156 && imm_expr
.X_add_number
< 0)
6158 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6159 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6160 ((bfd_arch_bits_per_address (stdoutput
) == 32
6161 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6162 ? "addiu" : "daddiu"),
6163 "t,r,j", dreg
, sreg
,
6164 (int) BFD_RELOC_LO16
);
6169 load_register (&icnt
, AT
, &imm_expr
, 0);
6170 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6174 macro_build ((char *) NULL
, &icnt
, &expr1
, "sltiu", "t,r,j", dreg
, dreg
,
6175 (int) BFD_RELOC_LO16
);
6180 case M_SGE
: /* sreg >= treg <==> not (sreg < treg) */
6186 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, sreg
, treg
);
6187 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6188 (int) BFD_RELOC_LO16
);
6191 case M_SGE_I
: /* sreg >= I <==> not (sreg < I) */
6193 if (imm_expr
.X_op
== O_constant
6194 && imm_expr
.X_add_number
>= -0x8000
6195 && imm_expr
.X_add_number
< 0x8000)
6197 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6198 mask
== M_SGE_I
? "slti" : "sltiu",
6199 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6204 load_register (&icnt
, AT
, &imm_expr
, 0);
6205 macro_build ((char *) NULL
, &icnt
, NULL
,
6206 mask
== M_SGE_I
? "slt" : "sltu",
6207 "d,v,t", dreg
, sreg
, AT
);
6210 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6211 (int) BFD_RELOC_LO16
);
6216 case M_SGT
: /* sreg > treg <==> treg < sreg */
6222 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6225 case M_SGT_I
: /* sreg > I <==> I < sreg */
6231 load_register (&icnt
, AT
, &imm_expr
, 0);
6232 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6235 case M_SLE
: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
6241 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, treg
, sreg
);
6242 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6243 (int) BFD_RELOC_LO16
);
6246 case M_SLE_I
: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
6252 load_register (&icnt
, AT
, &imm_expr
, 0);
6253 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "d,v,t", dreg
, AT
, sreg
);
6254 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", dreg
, dreg
,
6255 (int) BFD_RELOC_LO16
);
6259 if (imm_expr
.X_op
== O_constant
6260 && imm_expr
.X_add_number
>= -0x8000
6261 && imm_expr
.X_add_number
< 0x8000)
6263 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "slti", "t,r,j",
6264 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6267 load_register (&icnt
, AT
, &imm_expr
, 0);
6268 macro_build ((char *) NULL
, &icnt
, NULL
, "slt", "d,v,t", dreg
, sreg
, AT
);
6272 if (imm_expr
.X_op
== O_constant
6273 && imm_expr
.X_add_number
>= -0x8000
6274 && imm_expr
.X_add_number
< 0x8000)
6276 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "sltiu", "t,r,j",
6277 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6280 load_register (&icnt
, AT
, &imm_expr
, 0);
6281 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, sreg
,
6287 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6290 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6294 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6296 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6302 if (imm_expr
.X_op
== O_constant
&& imm_expr
.X_add_number
== 0)
6304 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0,
6310 as_warn (_("Instruction %s: result is always true"),
6312 macro_build ((char *) NULL
, &icnt
, &expr1
,
6313 ((bfd_arch_bits_per_address (stdoutput
) == 32
6314 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6315 ? "addiu" : "daddiu"),
6316 "t,r,j", dreg
, 0, (int) BFD_RELOC_LO16
);
6319 if (imm_expr
.X_op
== O_constant
6320 && imm_expr
.X_add_number
>= 0
6321 && imm_expr
.X_add_number
< 0x10000)
6323 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "xori", "t,r,i",
6324 dreg
, sreg
, (int) BFD_RELOC_LO16
);
6327 else if (imm_expr
.X_op
== O_constant
6328 && imm_expr
.X_add_number
> -0x8000
6329 && imm_expr
.X_add_number
< 0)
6331 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6332 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6333 ((bfd_arch_bits_per_address (stdoutput
) == 32
6334 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6335 ? "addiu" : "daddiu"),
6336 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6341 load_register (&icnt
, AT
, &imm_expr
, 0);
6342 macro_build ((char *) NULL
, &icnt
, NULL
, "xor", "d,v,t", dreg
,
6346 macro_build ((char *) NULL
, &icnt
, NULL
, "sltu", "d,v,t", dreg
, 0, dreg
);
6354 if (imm_expr
.X_op
== O_constant
6355 && imm_expr
.X_add_number
> -0x8000
6356 && imm_expr
.X_add_number
<= 0x8000)
6358 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6359 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6360 dbl
? "daddi" : "addi",
6361 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6364 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6365 macro_build ((char *) NULL
, &icnt
, NULL
,
6366 dbl
? "dsub" : "sub",
6367 "d,v,t", dreg
, sreg
, AT
);
6373 if (imm_expr
.X_op
== O_constant
6374 && imm_expr
.X_add_number
> -0x8000
6375 && imm_expr
.X_add_number
<= 0x8000)
6377 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6378 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6379 dbl
? "daddiu" : "addiu",
6380 "t,r,j", dreg
, sreg
, (int) BFD_RELOC_LO16
);
6383 load_register (&icnt
, AT
, &imm_expr
, dbl
);
6384 macro_build ((char *) NULL
, &icnt
, NULL
,
6385 dbl
? "dsubu" : "subu",
6386 "d,v,t", dreg
, sreg
, AT
);
6407 load_register (&icnt
, AT
, &imm_expr
, 0);
6408 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "s,t", sreg
, AT
);
6413 assert (mips_opts
.isa
== 1);
6414 sreg
= (ip
->insn_opcode
>> 11) & 0x1f; /* floating reg */
6415 dreg
= (ip
->insn_opcode
>> 06) & 0x1f; /* floating reg */
6418 * Is the double cfc1 instruction a bug in the mips assembler;
6419 * or is there a reason for it?
6421 mips_emit_delays (true);
6422 ++mips_opts
.noreorder
;
6423 mips_any_noreorder
= 1;
6424 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6425 macro_build ((char *) NULL
, &icnt
, NULL
, "cfc1", "t,G", treg
, 31);
6426 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6427 expr1
.X_add_number
= 3;
6428 macro_build ((char *) NULL
, &icnt
, &expr1
, "ori", "t,r,i", AT
, treg
,
6429 (int) BFD_RELOC_LO16
);
6430 expr1
.X_add_number
= 2;
6431 macro_build ((char *) NULL
, &icnt
, &expr1
, "xori", "t,r,i", AT
, AT
,
6432 (int) BFD_RELOC_LO16
);
6433 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", AT
, 31);
6434 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6435 macro_build ((char *) NULL
, &icnt
, NULL
,
6436 mask
== M_TRUNCWD
? "cvt.w.d" : "cvt.w.s", "D,S", dreg
, sreg
);
6437 macro_build ((char *) NULL
, &icnt
, NULL
, "ctc1", "t,G", treg
, 31);
6438 macro_build ((char *) NULL
, &icnt
, NULL
, "nop", "");
6439 --mips_opts
.noreorder
;
6448 if (offset_expr
.X_add_number
>= 0x7fff)
6449 as_bad (_("operand overflow"));
6450 /* avoid load delay */
6451 if (! target_big_endian
)
6452 offset_expr
.X_add_number
+= 1;
6453 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6454 (int) BFD_RELOC_LO16
, breg
);
6455 if (! target_big_endian
)
6456 offset_expr
.X_add_number
-= 1;
6458 offset_expr
.X_add_number
+= 1;
6459 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "lbu", "t,o(b)", AT
,
6460 (int) BFD_RELOC_LO16
, breg
);
6461 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
, treg
, 8);
6462 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
, treg
, AT
);
6475 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6476 as_bad (_("operand overflow"));
6477 if (! target_big_endian
)
6478 offset_expr
.X_add_number
+= off
;
6479 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6480 (int) BFD_RELOC_LO16
, breg
);
6481 if (! target_big_endian
)
6482 offset_expr
.X_add_number
-= off
;
6484 offset_expr
.X_add_number
+= off
;
6485 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6486 (int) BFD_RELOC_LO16
, breg
);
6499 load_address (&icnt
, AT
, &offset_expr
);
6501 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6502 ((bfd_arch_bits_per_address (stdoutput
) == 32
6503 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6504 ? "addu" : "daddu"),
6505 "d,v,t", AT
, AT
, breg
);
6506 if (! target_big_endian
)
6507 expr1
.X_add_number
= off
;
6509 expr1
.X_add_number
= 0;
6510 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6511 (int) BFD_RELOC_LO16
, AT
);
6512 if (! target_big_endian
)
6513 expr1
.X_add_number
= 0;
6515 expr1
.X_add_number
= off
;
6516 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6517 (int) BFD_RELOC_LO16
, AT
);
6522 load_address (&icnt
, AT
, &offset_expr
);
6524 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6525 ((bfd_arch_bits_per_address (stdoutput
) == 32
6526 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6527 ? "addu" : "daddu"),
6528 "d,v,t", AT
, AT
, breg
);
6529 if (target_big_endian
)
6530 expr1
.X_add_number
= 0;
6531 macro_build ((char *) NULL
, &icnt
, &expr1
,
6532 mask
== M_ULH_A
? "lb" : "lbu", "t,o(b)", treg
,
6533 (int) BFD_RELOC_LO16
, AT
);
6534 if (target_big_endian
)
6535 expr1
.X_add_number
= 1;
6537 expr1
.X_add_number
= 0;
6538 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6539 (int) BFD_RELOC_LO16
, AT
);
6540 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6542 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6547 if (offset_expr
.X_add_number
>= 0x7fff)
6548 as_bad (_("operand overflow"));
6549 if (target_big_endian
)
6550 offset_expr
.X_add_number
+= 1;
6551 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", treg
,
6552 (int) BFD_RELOC_LO16
, breg
);
6553 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", AT
, treg
, 8);
6554 if (target_big_endian
)
6555 offset_expr
.X_add_number
-= 1;
6557 offset_expr
.X_add_number
+= 1;
6558 macro_build ((char *) NULL
, &icnt
, &offset_expr
, "sb", "t,o(b)", AT
,
6559 (int) BFD_RELOC_LO16
, breg
);
6572 if (offset_expr
.X_add_number
>= 0x8000 - off
)
6573 as_bad (_("operand overflow"));
6574 if (! target_big_endian
)
6575 offset_expr
.X_add_number
+= off
;
6576 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s
, "t,o(b)", treg
,
6577 (int) BFD_RELOC_LO16
, breg
);
6578 if (! target_big_endian
)
6579 offset_expr
.X_add_number
-= off
;
6581 offset_expr
.X_add_number
+= off
;
6582 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "t,o(b)", treg
,
6583 (int) BFD_RELOC_LO16
, breg
);
6596 load_address (&icnt
, AT
, &offset_expr
);
6598 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6599 ((bfd_arch_bits_per_address (stdoutput
) == 32
6600 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6601 ? "addu" : "daddu"),
6602 "d,v,t", AT
, AT
, breg
);
6603 if (! target_big_endian
)
6604 expr1
.X_add_number
= off
;
6606 expr1
.X_add_number
= 0;
6607 macro_build ((char *) NULL
, &icnt
, &expr1
, s
, "t,o(b)", treg
,
6608 (int) BFD_RELOC_LO16
, AT
);
6609 if (! target_big_endian
)
6610 expr1
.X_add_number
= 0;
6612 expr1
.X_add_number
= off
;
6613 macro_build ((char *) NULL
, &icnt
, &expr1
, s2
, "t,o(b)", treg
,
6614 (int) BFD_RELOC_LO16
, AT
);
6618 load_address (&icnt
, AT
, &offset_expr
);
6620 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6621 ((bfd_arch_bits_per_address (stdoutput
) == 32
6622 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
6623 ? "addu" : "daddu"),
6624 "d,v,t", AT
, AT
, breg
);
6625 if (! target_big_endian
)
6626 expr1
.X_add_number
= 0;
6627 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6628 (int) BFD_RELOC_LO16
, AT
);
6629 macro_build ((char *) NULL
, &icnt
, NULL
, "srl", "d,w,<", treg
,
6631 if (! target_big_endian
)
6632 expr1
.X_add_number
= 1;
6634 expr1
.X_add_number
= 0;
6635 macro_build ((char *) NULL
, &icnt
, &expr1
, "sb", "t,o(b)", treg
,
6636 (int) BFD_RELOC_LO16
, AT
);
6637 if (! target_big_endian
)
6638 expr1
.X_add_number
= 0;
6640 expr1
.X_add_number
= 1;
6641 macro_build ((char *) NULL
, &icnt
, &expr1
, "lbu", "t,o(b)", AT
,
6642 (int) BFD_RELOC_LO16
, AT
);
6643 macro_build ((char *) NULL
, &icnt
, NULL
, "sll", "d,w,<", treg
,
6645 macro_build ((char *) NULL
, &icnt
, NULL
, "or", "d,v,t", treg
,
6650 /* FIXME: Check if this is one of the itbl macros, since they
6651 are added dynamically. */
6652 as_bad (_("Macro %s not implemented yet"), ip
->insn_mo
->name
);
6656 as_warn (_("Macro used $at after \".set noat\""));
6659 /* Implement macros in mips16 mode. */
6663 struct mips_cl_insn
*ip
;
6666 int xreg
, yreg
, zreg
, tmp
;
6670 const char *s
, *s2
, *s3
;
6672 mask
= ip
->insn_mo
->mask
;
6674 xreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RX
) & MIPS16OP_MASK_RX
;
6675 yreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RY
) & MIPS16OP_MASK_RY
;
6676 zreg
= (ip
->insn_opcode
>> MIPS16OP_SH_RZ
) & MIPS16OP_MASK_RZ
;
6680 expr1
.X_op
= O_constant
;
6681 expr1
.X_op_symbol
= NULL
;
6682 expr1
.X_add_symbol
= NULL
;
6683 expr1
.X_add_number
= 1;
6702 mips_emit_delays (true);
6703 ++mips_opts
.noreorder
;
6704 mips_any_noreorder
= 1;
6705 macro_build ((char *) NULL
, &icnt
, NULL
,
6706 dbl
? "ddiv" : "div",
6707 "0,x,y", xreg
, yreg
);
6708 expr1
.X_add_number
= 2;
6709 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6710 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6712 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
6713 since that causes an overflow. We should do that as well,
6714 but I don't see how to do the comparisons without a temporary
6716 --mips_opts
.noreorder
;
6717 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "x", zreg
);
6736 mips_emit_delays (true);
6737 ++mips_opts
.noreorder
;
6738 mips_any_noreorder
= 1;
6739 macro_build ((char *) NULL
, &icnt
, NULL
, s
, "0,x,y", xreg
, yreg
);
6740 expr1
.X_add_number
= 2;
6741 macro_build ((char *) NULL
, &icnt
, &expr1
, "bnez", "x,p", yreg
);
6742 macro_build ((char *) NULL
, &icnt
, NULL
, "break", "6", 7);
6743 --mips_opts
.noreorder
;
6744 macro_build ((char *) NULL
, &icnt
, NULL
, s2
, "x", zreg
);
6750 macro_build ((char *) NULL
, &icnt
, NULL
,
6751 dbl
? "dmultu" : "multu",
6753 macro_build ((char *) NULL
, &icnt
, NULL
, "mflo", "x", zreg
);
6761 if (imm_expr
.X_op
!= O_constant
)
6762 as_bad (_("Unsupported large constant"));
6763 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6764 macro_build ((char *) NULL
, &icnt
, &imm_expr
,
6765 dbl
? "daddiu" : "addiu",
6766 "y,x,4", yreg
, xreg
);
6770 if (imm_expr
.X_op
!= O_constant
)
6771 as_bad (_("Unsupported large constant"));
6772 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6773 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "addiu",
6778 if (imm_expr
.X_op
!= O_constant
)
6779 as_bad (_("Unsupported large constant"));
6780 imm_expr
.X_add_number
= -imm_expr
.X_add_number
;
6781 macro_build ((char *) NULL
, &icnt
, &imm_expr
, "daddiu",
6804 goto do_reverse_branch
;
6808 goto do_reverse_branch
;
6820 goto do_reverse_branch
;
6831 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, s
, "x,y",
6833 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6860 goto do_addone_branch_i
;
6865 goto do_addone_branch_i
;
6880 goto do_addone_branch_i
;
6887 if (imm_expr
.X_op
!= O_constant
)
6888 as_bad (_("Unsupported large constant"));
6889 ++imm_expr
.X_add_number
;
6892 macro_build ((char *) NULL
, &icnt
, &imm_expr
, s
, s3
, xreg
);
6893 macro_build ((char *) NULL
, &icnt
, &offset_expr
, s2
, "p");
6897 expr1
.X_add_number
= 0;
6898 macro_build ((char *) NULL
, &icnt
, &expr1
, "slti", "x,8", yreg
);
6900 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6901 "move", "y,X", xreg
, yreg
);
6902 expr1
.X_add_number
= 2;
6903 macro_build ((char *) NULL
, &icnt
, &expr1
, "bteqz", "p");
6904 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
6905 "neg", "x,w", xreg
, xreg
);
6909 /* For consistency checking, verify that all bits are specified either
6910 by the match/mask part of the instruction definition, or by the
6913 validate_mips_insn (opc
)
6914 const struct mips_opcode
*opc
;
6916 const char *p
= opc
->args
;
6918 unsigned long used_bits
= opc
->mask
;
6920 if ((used_bits
& opc
->match
) != opc
->match
)
6922 as_bad (_("internal: bad mips opcode (mask error): %s %s"),
6923 opc
->name
, opc
->args
);
6926 #define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
6933 case '<': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6934 case '>': USE_BITS (OP_MASK_SHAMT
, OP_SH_SHAMT
); break;
6936 case 'B': USE_BITS (OP_MASK_SYSCALL
, OP_SH_SYSCALL
); break;
6937 case 'C': USE_BITS (OP_MASK_COPZ
, OP_SH_COPZ
); break;
6938 case 'D': USE_BITS (OP_MASK_FD
, OP_SH_FD
); break;
6939 case 'E': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6941 case 'G': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6944 case 'M': USE_BITS (OP_MASK_CCC
, OP_SH_CCC
); break;
6945 case 'N': USE_BITS (OP_MASK_BCC
, OP_SH_BCC
); break;
6946 case 'R': USE_BITS (OP_MASK_FR
, OP_SH_FR
); break;
6947 case 'S': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6948 case 'T': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6949 case 'V': USE_BITS (OP_MASK_FS
, OP_SH_FS
); break;
6950 case 'W': USE_BITS (OP_MASK_FT
, OP_SH_FT
); break;
6951 case 'a': USE_BITS (OP_MASK_TARGET
, OP_SH_TARGET
); break;
6952 case 'b': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6953 case 'c': USE_BITS (OP_MASK_CODE
, OP_SH_CODE
); break;
6954 case 'd': USE_BITS (OP_MASK_RD
, OP_SH_RD
); break;
6956 case 'h': USE_BITS (OP_MASK_PREFX
, OP_SH_PREFX
); break;
6957 case 'i': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6958 case 'j': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6959 case 'k': USE_BITS (OP_MASK_CACHE
, OP_SH_CACHE
); break;
6961 case 'o': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6962 case 'p': USE_BITS (OP_MASK_DELTA
, OP_SH_DELTA
); break;
6963 case 'q': USE_BITS (OP_MASK_CODE2
, OP_SH_CODE2
); break;
6964 case 'r': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6965 case 's': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6966 case 't': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6967 case 'u': USE_BITS (OP_MASK_IMMEDIATE
, OP_SH_IMMEDIATE
); break;
6968 case 'v': USE_BITS (OP_MASK_RS
, OP_SH_RS
); break;
6969 case 'w': USE_BITS (OP_MASK_RT
, OP_SH_RT
); break;
6972 case 'P': USE_BITS (OP_MASK_PERFREG
, OP_SH_PERFREG
); break;
6974 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
6975 c
, opc
->name
, opc
->args
);
6979 if (used_bits
!= 0xffffffff)
6981 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
6982 ~used_bits
& 0xffffffff, opc
->name
, opc
->args
);
6988 /* This routine assembles an instruction into its binary format. As a
6989 side effect, it sets one of the global variables imm_reloc or
6990 offset_reloc to the type of relocation to do if one of the operands
6991 is an address expression. */
6996 struct mips_cl_insn
*ip
;
7001 struct mips_opcode
*insn
;
7004 unsigned int lastregno
= 0;
7007 int full_opcode_match
= 1;
7011 /* If the instruction contains a '.', we first try to match an instruction
7012 including the '.'. Then we try again without the '.'. */
7014 for (s
= str
; *s
!= '\0' && !isspace ((unsigned char) *s
); ++s
)
7017 /* If we stopped on whitespace, then replace the whitespace with null for
7018 the call to hash_find. Save the character we replaced just in case we
7019 have to re-parse the instruction. */
7020 if (isspace ((unsigned char) *s
))
7026 insn
= (struct mips_opcode
*) hash_find (op_hash
, str
);
7028 /* If we didn't find the instruction in the opcode table, try again, but
7029 this time with just the instruction up to, but not including the
7033 /* Restore the character we overwrite above (if any). */
7037 /* Scan up to the first '.' or whitespace. */
7038 for (s
= str
; *s
!= '\0' && *s
!= '.' && !isspace ((unsigned char) *s
); ++s
)
7041 /* If we did not find a '.', then we can quit now. */
7044 insn_error
= "unrecognized opcode";
7048 /* Lookup the instruction in the hash table. */
7050 if ((insn
= (struct mips_opcode
*) hash_find (op_hash
, str
)) == NULL
)
7052 insn_error
= "unrecognized opcode";
7056 full_opcode_match
= 0;
7064 assert (strcmp (insn
->name
, str
) == 0);
7066 if (OPCODE_IS_MEMBER (insn
, mips_opts
.isa
, mips_cpu
, mips_gp32
))
7071 if (insn
->pinfo
!= INSN_MACRO
)
7073 if (mips_cpu
== 4650 && (insn
->pinfo
& FP_D
) != 0)
7079 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
]
7080 && strcmp (insn
->name
, insn
[1].name
) == 0)
7087 static char buf
[100];
7089 _("opcode not supported on this processor: %d (MIPS%d)"),
7090 mips_cpu
, mips_opts
.isa
);
7098 ip
->insn_opcode
= insn
->match
;
7099 for (args
= insn
->args
;; ++args
)
7105 case '\0': /* end of args */
7118 ip
->insn_opcode
|= lastregno
<< 21;
7123 ip
->insn_opcode
|= lastregno
<< 16;
7127 ip
->insn_opcode
|= lastregno
<< 11;
7133 /* Handle optional base register.
7134 Either the base register is omitted or
7135 we must have a left paren. */
7136 /* This is dependent on the next operand specifier
7137 is a base register specification. */
7138 assert (args
[1] == 'b' || args
[1] == '5'
7139 || args
[1] == '-' || args
[1] == '4');
7143 case ')': /* these must match exactly */
7148 case '<': /* must be at least one digit */
7150 * According to the manual, if the shift amount is greater
7151 * than 31 or less than 0 the the shift amount should be
7152 * mod 32. In reality the mips assembler issues an error.
7153 * We issue a warning and mask out all but the low 5 bits.
7155 my_getExpression (&imm_expr
, s
);
7156 check_absolute_expr (ip
, &imm_expr
);
7157 if ((unsigned long) imm_expr
.X_add_number
> 31)
7159 as_warn (_("Improper shift amount (%ld)"),
7160 (long) imm_expr
.X_add_number
);
7161 imm_expr
.X_add_number
= imm_expr
.X_add_number
& 0x1f;
7163 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7164 imm_expr
.X_op
= O_absent
;
7168 case '>': /* shift amount minus 32 */
7169 my_getExpression (&imm_expr
, s
);
7170 check_absolute_expr (ip
, &imm_expr
);
7171 if ((unsigned long) imm_expr
.X_add_number
< 32
7172 || (unsigned long) imm_expr
.X_add_number
> 63)
7174 ip
->insn_opcode
|= (imm_expr
.X_add_number
- 32) << 6;
7175 imm_expr
.X_op
= O_absent
;
7180 case 'k': /* cache code */
7181 case 'h': /* prefx code */
7182 my_getExpression (&imm_expr
, s
);
7183 check_absolute_expr (ip
, &imm_expr
);
7184 if ((unsigned long) imm_expr
.X_add_number
> 31)
7186 as_warn (_("Invalid value for `%s' (%lu)"),
7188 (unsigned long) imm_expr
.X_add_number
);
7189 imm_expr
.X_add_number
&= 0x1f;
7192 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_CACHE
;
7194 ip
->insn_opcode
|= imm_expr
.X_add_number
<< OP_SH_PREFX
;
7195 imm_expr
.X_op
= O_absent
;
7199 case 'c': /* break code */
7200 my_getExpression (&imm_expr
, s
);
7201 check_absolute_expr (ip
, &imm_expr
);
7202 if ((unsigned) imm_expr
.X_add_number
> 1023)
7204 as_warn (_("Illegal break code (%ld)"),
7205 (long) imm_expr
.X_add_number
);
7206 imm_expr
.X_add_number
&= 0x3ff;
7208 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 16;
7209 imm_expr
.X_op
= O_absent
;
7213 case 'q': /* lower break code */
7214 my_getExpression (&imm_expr
, s
);
7215 check_absolute_expr (ip
, &imm_expr
);
7216 if ((unsigned) imm_expr
.X_add_number
> 1023)
7218 as_warn (_("Illegal lower break code (%ld)"),
7219 (long) imm_expr
.X_add_number
);
7220 imm_expr
.X_add_number
&= 0x3ff;
7222 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7223 imm_expr
.X_op
= O_absent
;
7227 case 'B': /* syscall code */
7228 my_getExpression (&imm_expr
, s
);
7229 check_absolute_expr (ip
, &imm_expr
);
7230 if ((unsigned) imm_expr
.X_add_number
> 0xfffff)
7231 as_warn (_("Illegal syscall code (%ld)"),
7232 (long) imm_expr
.X_add_number
);
7233 ip
->insn_opcode
|= imm_expr
.X_add_number
<< 6;
7234 imm_expr
.X_op
= O_absent
;
7238 case 'C': /* Coprocessor code */
7239 my_getExpression (&imm_expr
, s
);
7240 check_absolute_expr (ip
, &imm_expr
);
7241 if ((unsigned long) imm_expr
.X_add_number
>= (1<<25))
7243 as_warn (_("Coproccesor code > 25 bits (%ld)"),
7244 (long) imm_expr
.X_add_number
);
7245 imm_expr
.X_add_number
&= ((1<<25) - 1);
7247 ip
->insn_opcode
|= imm_expr
.X_add_number
;
7248 imm_expr
.X_op
= O_absent
;
7252 case 'P': /* Performance register */
7253 my_getExpression (&imm_expr
, s
);
7254 check_absolute_expr (ip
, &imm_expr
);
7255 if (imm_expr
.X_add_number
!= 0 && imm_expr
.X_add_number
!= 1)
7257 as_warn (_("Invalidate performance regster (%ld)"),
7258 (long) imm_expr
.X_add_number
);
7259 imm_expr
.X_add_number
&= 1;
7261 ip
->insn_opcode
|= (imm_expr
.X_add_number
<< 1);
7262 imm_expr
.X_op
= O_absent
;
7266 case 'b': /* base register */
7267 case 'd': /* destination register */
7268 case 's': /* source register */
7269 case 't': /* target register */
7270 case 'r': /* both target and source */
7271 case 'v': /* both dest and source */
7272 case 'w': /* both dest and target */
7273 case 'E': /* coprocessor target register */
7274 case 'G': /* coprocessor destination register */
7275 case 'x': /* ignore register name */
7276 case 'z': /* must be zero register */
7281 if (isdigit ((unsigned char) s
[1]))
7291 while (isdigit ((unsigned char) *s
));
7293 as_bad (_("Invalid register number (%d)"), regno
);
7295 else if (*args
== 'E' || *args
== 'G')
7299 if (s
[1] == 'f' && s
[2] == 'p')
7304 else if (s
[1] == 's' && s
[2] == 'p')
7309 else if (s
[1] == 'g' && s
[2] == 'p')
7314 else if (s
[1] == 'a' && s
[2] == 't')
7319 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
7324 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
7329 else if (itbl_have_entries
)
7334 p
= s
+ 1; /* advance past '$' */
7335 n
= itbl_get_field (&p
); /* n is name */
7337 /* See if this is a register defined in an
7339 if (itbl_get_reg_val (n
, &r
))
7341 /* Get_field advances to the start of
7342 the next field, so we need to back
7343 rack to the end of the last field. */
7347 s
= strchr (s
, '\0');
7360 as_warn (_("Used $at without \".set noat\""));
7366 if (c
== 'r' || c
== 'v' || c
== 'w')
7373 /* 'z' only matches $0. */
7374 if (c
== 'z' && regno
!= 0)
7377 /* Now that we have assembled one operand, we use the args string
7378 * to figure out where it goes in the instruction. */
7385 ip
->insn_opcode
|= regno
<< 21;
7389 ip
->insn_opcode
|= regno
<< 11;
7394 ip
->insn_opcode
|= regno
<< 16;
7397 /* This case exists because on the r3000 trunc
7398 expands into a macro which requires a gp
7399 register. On the r6000 or r4000 it is
7400 assembled into a single instruction which
7401 ignores the register. Thus the insn version
7402 is MIPS_ISA2 and uses 'x', and the macro
7403 version is MIPS_ISA1 and uses 't'. */
7406 /* This case is for the div instruction, which
7407 acts differently if the destination argument
7408 is $0. This only matches $0, and is checked
7409 outside the switch. */
7412 /* Itbl operand; not yet implemented. FIXME ?? */
7414 /* What about all other operands like 'i', which
7415 can be specified in the opcode table? */
7425 ip
->insn_opcode
|= lastregno
<< 21;
7428 ip
->insn_opcode
|= lastregno
<< 16;
7433 case 'D': /* floating point destination register */
7434 case 'S': /* floating point source register */
7435 case 'T': /* floating point target register */
7436 case 'R': /* floating point source register */
7440 if (s
[0] == '$' && s
[1] == 'f' && isdigit ((unsigned char) s
[2]))
7450 while (isdigit ((unsigned char) *s
));
7453 as_bad (_("Invalid float register number (%d)"), regno
);
7455 if ((regno
& 1) != 0
7456 && ! ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7457 && ! (strcmp (str
, "mtc1") == 0
7458 || strcmp (str
, "mfc1") == 0
7459 || strcmp (str
, "lwc1") == 0
7460 || strcmp (str
, "swc1") == 0
7461 || strcmp (str
, "l.s") == 0
7462 || strcmp (str
, "s.s") == 0))
7463 as_warn (_("Float register should be even, was %d"),
7471 if (c
== 'V' || c
== 'W')
7481 ip
->insn_opcode
|= regno
<< 6;
7485 ip
->insn_opcode
|= regno
<< 11;
7489 ip
->insn_opcode
|= regno
<< 16;
7492 ip
->insn_opcode
|= regno
<< 21;
7503 ip
->insn_opcode
|= lastregno
<< 11;
7506 ip
->insn_opcode
|= lastregno
<< 16;
7512 my_getExpression (&imm_expr
, s
);
7513 if (imm_expr
.X_op
!= O_big
7514 && imm_expr
.X_op
!= O_constant
)
7515 insn_error
= _("absolute expression required");
7520 my_getExpression (&offset_expr
, s
);
7521 imm_reloc
= BFD_RELOC_32
;
7533 unsigned char temp
[8];
7535 unsigned int length
;
7540 /* These only appear as the last operand in an
7541 instruction, and every instruction that accepts
7542 them in any variant accepts them in all variants.
7543 This means we don't have to worry about backing out
7544 any changes if the instruction does not match.
7546 The difference between them is the size of the
7547 floating point constant and where it goes. For 'F'
7548 and 'L' the constant is 64 bits; for 'f' and 'l' it
7549 is 32 bits. Where the constant is placed is based
7550 on how the MIPS assembler does things:
7553 f -- immediate value
7556 The .lit4 and .lit8 sections are only used if
7557 permitted by the -G argument.
7559 When generating embedded PIC code, we use the
7560 .lit8 section but not the .lit4 section (we can do
7561 .lit4 inline easily; we need to put .lit8
7562 somewhere in the data segment, and using .lit8
7563 permits the linker to eventually combine identical
7566 f64
= *args
== 'F' || *args
== 'L';
7568 save_in
= input_line_pointer
;
7569 input_line_pointer
= s
;
7570 err
= md_atof (f64
? 'd' : 'f', (char *) temp
, &len
);
7572 s
= input_line_pointer
;
7573 input_line_pointer
= save_in
;
7574 if (err
!= NULL
&& *err
!= '\0')
7576 as_bad (_("Bad floating point constant: %s"), err
);
7577 memset (temp
, '\0', sizeof temp
);
7578 length
= f64
? 8 : 4;
7581 assert (length
== (f64
? 8 : 4));
7585 && (! USE_GLOBAL_POINTER_OPT
7586 || mips_pic
== EMBEDDED_PIC
7587 || g_switch_value
< 4
7588 || (temp
[0] == 0 && temp
[1] == 0)
7589 || (temp
[2] == 0 && temp
[3] == 0))))
7591 imm_expr
.X_op
= O_constant
;
7592 if (! target_big_endian
)
7593 imm_expr
.X_add_number
= bfd_getl32 (temp
);
7595 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7598 && ((temp
[0] == 0 && temp
[1] == 0)
7599 || (temp
[2] == 0 && temp
[3] == 0))
7600 && ((temp
[4] == 0 && temp
[5] == 0)
7601 || (temp
[6] == 0 && temp
[7] == 0)))
7603 /* The value is simple enough to load with a
7604 couple of instructions. In mips1 mode, set
7605 imm_expr to the high order 32 bits and
7606 offset_expr to the low order 32 bits.
7607 Otherwise, set imm_expr to the entire 64 bit
7609 if (! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
7611 imm_expr
.X_op
= O_constant
;
7612 offset_expr
.X_op
= O_constant
;
7613 if (! target_big_endian
)
7615 imm_expr
.X_add_number
= bfd_getl32 (temp
+ 4);
7616 offset_expr
.X_add_number
= bfd_getl32 (temp
);
7620 imm_expr
.X_add_number
= bfd_getb32 (temp
);
7621 offset_expr
.X_add_number
= bfd_getb32 (temp
+ 4);
7623 if (offset_expr
.X_add_number
== 0)
7624 offset_expr
.X_op
= O_absent
;
7626 else if (sizeof (imm_expr
.X_add_number
) > 4)
7628 imm_expr
.X_op
= O_constant
;
7629 if (! target_big_endian
)
7630 imm_expr
.X_add_number
= bfd_getl64 (temp
);
7632 imm_expr
.X_add_number
= bfd_getb64 (temp
);
7636 imm_expr
.X_op
= O_big
;
7637 imm_expr
.X_add_number
= 4;
7638 if (! target_big_endian
)
7640 generic_bignum
[0] = bfd_getl16 (temp
);
7641 generic_bignum
[1] = bfd_getl16 (temp
+ 2);
7642 generic_bignum
[2] = bfd_getl16 (temp
+ 4);
7643 generic_bignum
[3] = bfd_getl16 (temp
+ 6);
7647 generic_bignum
[0] = bfd_getb16 (temp
+ 6);
7648 generic_bignum
[1] = bfd_getb16 (temp
+ 4);
7649 generic_bignum
[2] = bfd_getb16 (temp
+ 2);
7650 generic_bignum
[3] = bfd_getb16 (temp
);
7656 const char *newname
;
7659 /* Switch to the right section. */
7661 subseg
= now_subseg
;
7664 default: /* unused default case avoids warnings. */
7666 newname
= RDATA_SECTION_NAME
;
7667 if ((USE_GLOBAL_POINTER_OPT
&& g_switch_value
>= 8)
7668 || mips_pic
== EMBEDDED_PIC
)
7672 if (mips_pic
== EMBEDDED_PIC
)
7675 newname
= RDATA_SECTION_NAME
;
7678 assert (!USE_GLOBAL_POINTER_OPT
7679 || g_switch_value
>= 4);
7683 new_seg
= subseg_new (newname
, (subsegT
) 0);
7684 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
7685 bfd_set_section_flags (stdoutput
, new_seg
,
7690 frag_align (*args
== 'l' ? 2 : 3, 0, 0);
7691 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
7692 && strcmp (TARGET_OS
, "elf") != 0)
7693 record_alignment (new_seg
, 4);
7695 record_alignment (new_seg
, *args
== 'l' ? 2 : 3);
7697 as_bad (_("Can't use floating point insn in this section"));
7699 /* Set the argument to the current address in the
7701 offset_expr
.X_op
= O_symbol
;
7702 offset_expr
.X_add_symbol
=
7703 symbol_new ("L0\001", now_seg
,
7704 (valueT
) frag_now_fix (), frag_now
);
7705 offset_expr
.X_add_number
= 0;
7707 /* Put the floating point number into the section. */
7708 p
= frag_more ((int) length
);
7709 memcpy (p
, temp
, length
);
7711 /* Switch back to the original section. */
7712 subseg_set (seg
, subseg
);
7717 case 'i': /* 16 bit unsigned immediate */
7718 case 'j': /* 16 bit signed immediate */
7719 imm_reloc
= BFD_RELOC_LO16
;
7720 c
= my_getSmallExpression (&imm_expr
, s
);
7725 if (imm_expr
.X_op
== O_constant
)
7726 imm_expr
.X_add_number
=
7727 (imm_expr
.X_add_number
>> 16) & 0xffff;
7730 imm_reloc
= BFD_RELOC_HI16_S
;
7731 imm_unmatched_hi
= true;
7734 imm_reloc
= BFD_RELOC_HI16
;
7736 else if (imm_expr
.X_op
== O_constant
)
7737 imm_expr
.X_add_number
&= 0xffff;
7741 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7742 || ((imm_expr
.X_add_number
< 0
7743 || imm_expr
.X_add_number
>= 0x10000)
7744 && imm_expr
.X_op
== O_constant
))
7746 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7747 !strcmp (insn
->name
, insn
[1].name
))
7749 if (imm_expr
.X_op
== O_constant
7750 || imm_expr
.X_op
== O_big
)
7751 as_bad (_("16 bit expression not in range 0..65535"));
7759 /* The upper bound should be 0x8000, but
7760 unfortunately the MIPS assembler accepts numbers
7761 from 0x8000 to 0xffff and sign extends them, and
7762 we want to be compatible. We only permit this
7763 extended range for an instruction which does not
7764 provide any further alternates, since those
7765 alternates may handle other cases. People should
7766 use the numbers they mean, rather than relying on
7767 a mysterious sign extension. */
7768 more
= (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7769 strcmp (insn
->name
, insn
[1].name
) == 0);
7774 if ((c
== '\0' && imm_expr
.X_op
!= O_constant
)
7775 || ((imm_expr
.X_add_number
< -0x8000
7776 || imm_expr
.X_add_number
>= max
)
7777 && imm_expr
.X_op
== O_constant
)
7779 && imm_expr
.X_add_number
< 0
7780 && ISA_HAS_64BIT_REGS (mips_opts
.isa
)
7781 && imm_expr
.X_unsigned
7782 && sizeof (imm_expr
.X_add_number
) <= 4))
7786 if (imm_expr
.X_op
== O_constant
7787 || imm_expr
.X_op
== O_big
)
7788 as_bad (_("16 bit expression not in range -32768..32767"));
7794 case 'o': /* 16 bit offset */
7795 c
= my_getSmallExpression (&offset_expr
, s
);
7797 /* If this value won't fit into a 16 bit offset, then go
7798 find a macro that will generate the 32 bit offset
7799 code pattern. As a special hack, we accept the
7800 difference of two local symbols as a constant. This
7801 is required to suppose embedded PIC switches, which
7802 use an instruction which looks like
7803 lw $4,$L12-$LS12($4)
7804 The problem with handling this in a more general
7805 fashion is that the macro function doesn't expect to
7806 see anything which can be handled in a single
7807 constant instruction. */
7809 && (offset_expr
.X_op
!= O_constant
7810 || offset_expr
.X_add_number
>= 0x8000
7811 || offset_expr
.X_add_number
< -0x8000)
7812 && (mips_pic
!= EMBEDDED_PIC
7813 || offset_expr
.X_op
!= O_subtract
7814 || (S_GET_SEGMENT (offset_expr
.X_op_symbol
)
7818 if (c
== 'h' || c
== 'H')
7820 if (offset_expr
.X_op
!= O_constant
)
7822 offset_expr
.X_add_number
=
7823 (offset_expr
.X_add_number
>> 16) & 0xffff;
7825 offset_reloc
= BFD_RELOC_LO16
;
7829 case 'p': /* pc relative offset */
7830 offset_reloc
= BFD_RELOC_16_PCREL_S2
;
7831 my_getExpression (&offset_expr
, s
);
7835 case 'u': /* upper 16 bits */
7836 c
= my_getSmallExpression (&imm_expr
, s
);
7837 imm_reloc
= BFD_RELOC_LO16
;
7842 if (imm_expr
.X_op
== O_constant
)
7843 imm_expr
.X_add_number
=
7844 (imm_expr
.X_add_number
>> 16) & 0xffff;
7847 imm_reloc
= BFD_RELOC_HI16_S
;
7848 imm_unmatched_hi
= true;
7851 imm_reloc
= BFD_RELOC_HI16
;
7853 else if (imm_expr
.X_op
== O_constant
)
7854 imm_expr
.X_add_number
&= 0xffff;
7856 if (imm_expr
.X_op
== O_constant
7857 && (imm_expr
.X_add_number
< 0
7858 || imm_expr
.X_add_number
>= 0x10000))
7859 as_bad (_("lui expression not in range 0..65535"));
7863 case 'a': /* 26 bit address */
7864 my_getExpression (&offset_expr
, s
);
7866 offset_reloc
= BFD_RELOC_MIPS_JMP
;
7869 case 'N': /* 3 bit branch condition code */
7870 case 'M': /* 3 bit compare condition code */
7871 if (strncmp (s
, "$fcc", 4) != 0)
7881 while (isdigit ((unsigned char) *s
));
7883 as_bad (_("invalid condition code register $fcc%d"), regno
);
7885 ip
->insn_opcode
|= regno
<< OP_SH_BCC
;
7887 ip
->insn_opcode
|= regno
<< OP_SH_CCC
;
7891 as_bad (_("bad char = '%c'\n"), *args
);
7896 /* Args don't match. */
7897 if (insn
+ 1 < &mips_opcodes
[NUMOPCODES
] &&
7898 !strcmp (insn
->name
, insn
[1].name
))
7904 insn_error
= _("illegal operands");
7909 /* This routine assembles an instruction into its binary format when
7910 assembling for the mips16. As a side effect, it sets one of the
7911 global variables imm_reloc or offset_reloc to the type of
7912 relocation to do if one of the operands is an address expression.
7913 It also sets mips16_small and mips16_ext if the user explicitly
7914 requested a small or extended instruction. */
7919 struct mips_cl_insn
*ip
;
7923 struct mips_opcode
*insn
;
7926 unsigned int lastregno
= 0;
7931 mips16_small
= false;
7934 for (s
= str
; islower ((unsigned char) *s
); ++s
)
7946 if (s
[1] == 't' && s
[2] == ' ')
7949 mips16_small
= true;
7953 else if (s
[1] == 'e' && s
[2] == ' ')
7962 insn_error
= _("unknown opcode");
7966 if (mips_opts
.noautoextend
&& ! mips16_ext
)
7967 mips16_small
= true;
7969 if ((insn
= (struct mips_opcode
*) hash_find (mips16_op_hash
, str
)) == NULL
)
7971 insn_error
= _("unrecognized opcode");
7978 assert (strcmp (insn
->name
, str
) == 0);
7981 ip
->insn_opcode
= insn
->match
;
7982 ip
->use_extend
= false;
7983 imm_expr
.X_op
= O_absent
;
7984 imm_reloc
= BFD_RELOC_UNUSED
;
7985 offset_expr
.X_op
= O_absent
;
7986 offset_reloc
= BFD_RELOC_UNUSED
;
7987 for (args
= insn
->args
; 1; ++args
)
7994 /* In this switch statement we call break if we did not find
7995 a match, continue if we did find a match, or return if we
8004 /* Stuff the immediate value in now, if we can. */
8005 if (imm_expr
.X_op
== O_constant
8006 && imm_reloc
> BFD_RELOC_UNUSED
8007 && insn
->pinfo
!= INSN_MACRO
)
8009 mips16_immed ((char *) NULL
, 0,
8010 imm_reloc
- BFD_RELOC_UNUSED
,
8011 imm_expr
.X_add_number
, true, mips16_small
,
8012 mips16_ext
, &ip
->insn_opcode
,
8013 &ip
->use_extend
, &ip
->extend
);
8014 imm_expr
.X_op
= O_absent
;
8015 imm_reloc
= BFD_RELOC_UNUSED
;
8029 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8032 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8048 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RX
;
8050 ip
->insn_opcode
|= lastregno
<< MIPS16OP_SH_RY
;
8067 if (isdigit ((unsigned char) s
[1]))
8077 while (isdigit ((unsigned char) *s
));
8080 as_bad (_("invalid register number (%d)"), regno
);
8086 if (s
[1] == 'f' && s
[2] == 'p')
8091 else if (s
[1] == 's' && s
[2] == 'p')
8096 else if (s
[1] == 'g' && s
[2] == 'p')
8101 else if (s
[1] == 'a' && s
[2] == 't')
8106 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '0')
8111 else if (s
[1] == 'k' && s
[2] == 't' && s
[3] == '1')
8124 if (c
== 'v' || c
== 'w')
8126 regno
= mips16_to_32_reg_map
[lastregno
];
8140 regno
= mips32_to_16_reg_map
[regno
];
8145 regno
= ILLEGAL_REG
;
8150 regno
= ILLEGAL_REG
;
8155 regno
= ILLEGAL_REG
;
8160 if (regno
== AT
&& ! mips_opts
.noat
)
8161 as_warn (_("used $at without \".set noat\""));
8168 if (regno
== ILLEGAL_REG
)
8175 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RX
;
8179 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RY
;
8182 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_RZ
;
8185 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_MOVE32Z
;
8191 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REGR32
;
8194 regno
= ((regno
& 7) << 2) | ((regno
& 0x18) >> 3);
8195 ip
->insn_opcode
|= regno
<< MIPS16OP_SH_REG32R
;
8205 if (strncmp (s
, "$pc", 3) == 0)
8229 && strncmp (s
+ 1, "gprel(", sizeof "gprel(" - 1) == 0)
8231 /* This is %gprel(SYMBOL). We need to read SYMBOL,
8232 and generate the appropriate reloc. If the text
8233 inside %gprel is not a symbol name with an
8234 optional offset, then we generate a normal reloc
8235 and will probably fail later. */
8236 my_getExpression (&imm_expr
, s
+ sizeof "%gprel" - 1);
8237 if (imm_expr
.X_op
== O_symbol
)
8240 imm_reloc
= BFD_RELOC_MIPS16_GPREL
;
8242 ip
->use_extend
= true;
8249 /* Just pick up a normal expression. */
8250 my_getExpression (&imm_expr
, s
);
8253 if (imm_expr
.X_op
== O_register
)
8255 /* What we thought was an expression turned out to
8258 if (s
[0] == '(' && args
[1] == '(')
8260 /* It looks like the expression was omitted
8261 before a register indirection, which means
8262 that the expression is implicitly zero. We
8263 still set up imm_expr, so that we handle
8264 explicit extensions correctly. */
8265 imm_expr
.X_op
= O_constant
;
8266 imm_expr
.X_add_number
= 0;
8267 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8274 /* We need to relax this instruction. */
8275 imm_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8284 /* We use offset_reloc rather than imm_reloc for the PC
8285 relative operands. This lets macros with both
8286 immediate and address operands work correctly. */
8287 my_getExpression (&offset_expr
, s
);
8289 if (offset_expr
.X_op
== O_register
)
8292 /* We need to relax this instruction. */
8293 offset_reloc
= (int) BFD_RELOC_UNUSED
+ c
;
8297 case '6': /* break code */
8298 my_getExpression (&imm_expr
, s
);
8299 check_absolute_expr (ip
, &imm_expr
);
8300 if ((unsigned long) imm_expr
.X_add_number
> 63)
8302 as_warn (_("Invalid value for `%s' (%lu)"),
8304 (unsigned long) imm_expr
.X_add_number
);
8305 imm_expr
.X_add_number
&= 0x3f;
8307 ip
->insn_opcode
|= imm_expr
.X_add_number
<< MIPS16OP_SH_IMM6
;
8308 imm_expr
.X_op
= O_absent
;
8312 case 'a': /* 26 bit address */
8313 my_getExpression (&offset_expr
, s
);
8315 offset_reloc
= BFD_RELOC_MIPS16_JMP
;
8316 ip
->insn_opcode
<<= 16;
8319 case 'l': /* register list for entry macro */
8320 case 'L': /* register list for exit macro */
8330 int freg
, reg1
, reg2
;
8332 while (*s
== ' ' || *s
== ',')
8336 as_bad (_("can't parse register list"));
8348 while (isdigit ((unsigned char) *s
))
8370 as_bad (_("invalid register list"));
8375 while (isdigit ((unsigned char) *s
))
8382 if (freg
&& reg1
== 0 && reg2
== 0 && c
== 'L')
8387 else if (freg
&& reg1
== 0 && reg2
== 1 && c
== 'L')
8392 else if (reg1
== 4 && reg2
>= 4 && reg2
<= 7 && c
!= 'L')
8393 mask
|= (reg2
- 3) << 3;
8394 else if (reg1
== 16 && reg2
>= 16 && reg2
<= 17)
8395 mask
|= (reg2
- 15) << 1;
8396 else if (reg1
== 31 && reg2
== 31)
8400 as_bad (_("invalid register list"));
8404 /* The mask is filled in in the opcode table for the
8405 benefit of the disassembler. We remove it before
8406 applying the actual mask. */
8407 ip
->insn_opcode
&= ~ ((7 << 3) << MIPS16OP_SH_IMM6
);
8408 ip
->insn_opcode
|= mask
<< MIPS16OP_SH_IMM6
;
8412 case 'e': /* extend code */
8413 my_getExpression (&imm_expr
, s
);
8414 check_absolute_expr (ip
, &imm_expr
);
8415 if ((unsigned long) imm_expr
.X_add_number
> 0x7ff)
8417 as_warn (_("Invalid value for `%s' (%lu)"),
8419 (unsigned long) imm_expr
.X_add_number
);
8420 imm_expr
.X_add_number
&= 0x7ff;
8422 ip
->insn_opcode
|= imm_expr
.X_add_number
;
8423 imm_expr
.X_op
= O_absent
;
8433 /* Args don't match. */
8434 if (insn
+ 1 < &mips16_opcodes
[bfd_mips16_num_opcodes
] &&
8435 strcmp (insn
->name
, insn
[1].name
) == 0)
8442 insn_error
= _("illegal operands");
8448 /* This structure holds information we know about a mips16 immediate
8451 struct mips16_immed_operand
8453 /* The type code used in the argument string in the opcode table. */
8455 /* The number of bits in the short form of the opcode. */
8457 /* The number of bits in the extended form of the opcode. */
8459 /* The amount by which the short form is shifted when it is used;
8460 for example, the sw instruction has a shift count of 2. */
8462 /* The amount by which the short form is shifted when it is stored
8463 into the instruction code. */
8465 /* Non-zero if the short form is unsigned. */
8467 /* Non-zero if the extended form is unsigned. */
8469 /* Non-zero if the value is PC relative. */
8473 /* The mips16 immediate operand types. */
8475 static const struct mips16_immed_operand mips16_immed_operands
[] =
8477 { '<', 3, 5, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8478 { '>', 3, 5, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8479 { '[', 3, 6, 0, MIPS16OP_SH_RZ
, 1, 1, 0 },
8480 { ']', 3, 6, 0, MIPS16OP_SH_RX
, 1, 1, 0 },
8481 { '4', 4, 15, 0, MIPS16OP_SH_IMM4
, 0, 0, 0 },
8482 { '5', 5, 16, 0, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8483 { 'H', 5, 16, 1, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8484 { 'W', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8485 { 'D', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 0 },
8486 { 'j', 5, 16, 0, MIPS16OP_SH_IMM5
, 0, 0, 0 },
8487 { '8', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8488 { 'V', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8489 { 'C', 8, 16, 3, MIPS16OP_SH_IMM8
, 1, 0, 0 },
8490 { 'U', 8, 16, 0, MIPS16OP_SH_IMM8
, 1, 1, 0 },
8491 { 'k', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8492 { 'K', 8, 16, 3, MIPS16OP_SH_IMM8
, 0, 0, 0 },
8493 { 'p', 8, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8494 { 'q', 11, 16, 0, MIPS16OP_SH_IMM8
, 0, 0, 1 },
8495 { 'A', 8, 16, 2, MIPS16OP_SH_IMM8
, 1, 0, 1 },
8496 { 'B', 5, 16, 3, MIPS16OP_SH_IMM5
, 1, 0, 1 },
8497 { 'E', 5, 16, 2, MIPS16OP_SH_IMM5
, 1, 0, 1 }
8500 #define MIPS16_NUM_IMMED \
8501 (sizeof mips16_immed_operands / sizeof mips16_immed_operands[0])
8503 /* Handle a mips16 instruction with an immediate value. This or's the
8504 small immediate value into *INSN. It sets *USE_EXTEND to indicate
8505 whether an extended value is needed; if one is needed, it sets
8506 *EXTEND to the value. The argument type is TYPE. The value is VAL.
8507 If SMALL is true, an unextended opcode was explicitly requested.
8508 If EXT is true, an extended opcode was explicitly requested. If
8509 WARN is true, warn if EXT does not match reality. */
8512 mips16_immed (file
, line
, type
, val
, warn
, small
, ext
, insn
, use_extend
,
8521 unsigned long *insn
;
8522 boolean
*use_extend
;
8523 unsigned short *extend
;
8525 register const struct mips16_immed_operand
*op
;
8526 int mintiny
, maxtiny
;
8529 op
= mips16_immed_operands
;
8530 while (op
->type
!= type
)
8533 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
8538 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
8541 maxtiny
= 1 << op
->nbits
;
8546 maxtiny
= (1 << op
->nbits
) - 1;
8551 mintiny
= - (1 << (op
->nbits
- 1));
8552 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
8555 /* Branch offsets have an implicit 0 in the lowest bit. */
8556 if (type
== 'p' || type
== 'q')
8559 if ((val
& ((1 << op
->shift
) - 1)) != 0
8560 || val
< (mintiny
<< op
->shift
)
8561 || val
> (maxtiny
<< op
->shift
))
8566 if (warn
&& ext
&& ! needext
)
8567 as_warn_where (file
, line
, _("extended operand requested but not required"));
8568 if (small
&& needext
)
8569 as_bad_where (file
, line
, _("invalid unextended operand value"));
8571 if (small
|| (! ext
&& ! needext
))
8575 *use_extend
= false;
8576 insnval
= ((val
>> op
->shift
) & ((1 << op
->nbits
) - 1));
8577 insnval
<<= op
->op_shift
;
8582 long minext
, maxext
;
8588 maxext
= (1 << op
->extbits
) - 1;
8592 minext
= - (1 << (op
->extbits
- 1));
8593 maxext
= (1 << (op
->extbits
- 1)) - 1;
8595 if (val
< minext
|| val
> maxext
)
8596 as_bad_where (file
, line
,
8597 _("operand value out of range for instruction"));
8600 if (op
->extbits
== 16)
8602 extval
= ((val
>> 11) & 0x1f) | (val
& 0x7e0);
8605 else if (op
->extbits
== 15)
8607 extval
= ((val
>> 11) & 0xf) | (val
& 0x7f0);
8612 extval
= ((val
& 0x1f) << 6) | (val
& 0x20);
8616 *extend
= (unsigned short) extval
;
8625 my_getSmallExpression (ep
, str
)
8636 ((str
[1] == 'h' && str
[2] == 'i')
8637 || (str
[1] == 'H' && str
[2] == 'I')
8638 || (str
[1] == 'l' && str
[2] == 'o'))
8650 * A small expression may be followed by a base register.
8651 * Scan to the end of this operand, and then back over a possible
8652 * base register. Then scan the small expression up to that
8653 * point. (Based on code in sparc.c...)
8655 for (sp
= str
; *sp
&& *sp
!= ','; sp
++)
8657 if (sp
- 4 >= str
&& sp
[-1] == RP
)
8659 if (isdigit ((unsigned char) sp
[-2]))
8661 for (sp
-= 3; sp
>= str
&& isdigit ((unsigned char) *sp
); sp
--)
8663 if (*sp
== '$' && sp
> str
&& sp
[-1] == LP
)
8669 else if (sp
- 5 >= str
8672 && ((sp
[-3] == 'f' && sp
[-2] == 'p')
8673 || (sp
[-3] == 's' && sp
[-2] == 'p')
8674 || (sp
[-3] == 'g' && sp
[-2] == 'p')
8675 || (sp
[-3] == 'a' && sp
[-2] == 't')))
8681 /* no expression means zero offset */
8684 /* %xx(reg) is an error */
8685 ep
->X_op
= O_absent
;
8690 ep
->X_op
= O_constant
;
8693 ep
->X_add_symbol
= NULL
;
8694 ep
->X_op_symbol
= NULL
;
8695 ep
->X_add_number
= 0;
8700 my_getExpression (ep
, str
);
8707 my_getExpression (ep
, str
);
8708 return c
; /* => %hi or %lo encountered */
8712 my_getExpression (ep
, str
)
8718 save_in
= input_line_pointer
;
8719 input_line_pointer
= str
;
8721 expr_end
= input_line_pointer
;
8722 input_line_pointer
= save_in
;
8724 /* If we are in mips16 mode, and this is an expression based on `.',
8725 then we bump the value of the symbol by 1 since that is how other
8726 text symbols are handled. We don't bother to handle complex
8727 expressions, just `.' plus or minus a constant. */
8728 if (mips_opts
.mips16
8729 && ep
->X_op
== O_symbol
8730 && strcmp (S_GET_NAME (ep
->X_add_symbol
), FAKE_LABEL_NAME
) == 0
8731 && S_GET_SEGMENT (ep
->X_add_symbol
) == now_seg
8732 && symbol_get_frag (ep
->X_add_symbol
) == frag_now
8733 && symbol_constant_p (ep
->X_add_symbol
)
8734 && S_GET_VALUE (ep
->X_add_symbol
) == frag_now_fix ())
8735 S_SET_VALUE (ep
->X_add_symbol
, S_GET_VALUE (ep
->X_add_symbol
) + 1);
8738 /* Turn a string in input_line_pointer into a floating point constant
8739 of type type, and store the appropriate bytes in *litP. The number
8740 of LITTLENUMS emitted is stored in *sizeP . An error message is
8741 returned, or NULL on OK. */
8744 md_atof (type
, litP
, sizeP
)
8750 LITTLENUM_TYPE words
[4];
8766 return _("bad call to md_atof");
8769 t
= atof_ieee (input_line_pointer
, type
, words
);
8771 input_line_pointer
= t
;
8775 if (! target_big_endian
)
8777 for (i
= prec
- 1; i
>= 0; i
--)
8779 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8785 for (i
= 0; i
< prec
; i
++)
8787 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
8796 md_number_to_chars (buf
, val
, n
)
8801 if (target_big_endian
)
8802 number_to_chars_bigendian (buf
, val
, n
);
8804 number_to_chars_littleendian (buf
, val
, n
);
8807 CONST
char *md_shortopts
= "O::g::G:";
8809 struct option md_longopts
[] = {
8810 #define OPTION_MIPS1 (OPTION_MD_BASE + 1)
8811 {"mips0", no_argument
, NULL
, OPTION_MIPS1
},
8812 {"mips1", no_argument
, NULL
, OPTION_MIPS1
},
8813 #define OPTION_MIPS2 (OPTION_MD_BASE + 2)
8814 {"mips2", no_argument
, NULL
, OPTION_MIPS2
},
8815 #define OPTION_MIPS3 (OPTION_MD_BASE + 3)
8816 {"mips3", no_argument
, NULL
, OPTION_MIPS3
},
8817 #define OPTION_MIPS4 (OPTION_MD_BASE + 4)
8818 {"mips4", no_argument
, NULL
, OPTION_MIPS4
},
8819 #define OPTION_MCPU (OPTION_MD_BASE + 5)
8820 {"mcpu", required_argument
, NULL
, OPTION_MCPU
},
8821 #define OPTION_MEMBEDDED_PIC (OPTION_MD_BASE + 6)
8822 {"membedded-pic", no_argument
, NULL
, OPTION_MEMBEDDED_PIC
},
8823 #define OPTION_TRAP (OPTION_MD_BASE + 9)
8824 {"trap", no_argument
, NULL
, OPTION_TRAP
},
8825 {"no-break", no_argument
, NULL
, OPTION_TRAP
},
8826 #define OPTION_BREAK (OPTION_MD_BASE + 10)
8827 {"break", no_argument
, NULL
, OPTION_BREAK
},
8828 {"no-trap", no_argument
, NULL
, OPTION_BREAK
},
8829 #define OPTION_EB (OPTION_MD_BASE + 11)
8830 {"EB", no_argument
, NULL
, OPTION_EB
},
8831 #define OPTION_EL (OPTION_MD_BASE + 12)
8832 {"EL", no_argument
, NULL
, OPTION_EL
},
8833 #define OPTION_M4650 (OPTION_MD_BASE + 13)
8834 {"m4650", no_argument
, NULL
, OPTION_M4650
},
8835 #define OPTION_NO_M4650 (OPTION_MD_BASE + 14)
8836 {"no-m4650", no_argument
, NULL
, OPTION_NO_M4650
},
8837 #define OPTION_M4010 (OPTION_MD_BASE + 15)
8838 {"m4010", no_argument
, NULL
, OPTION_M4010
},
8839 #define OPTION_NO_M4010 (OPTION_MD_BASE + 16)
8840 {"no-m4010", no_argument
, NULL
, OPTION_NO_M4010
},
8841 #define OPTION_M4100 (OPTION_MD_BASE + 17)
8842 {"m4100", no_argument
, NULL
, OPTION_M4100
},
8843 #define OPTION_NO_M4100 (OPTION_MD_BASE + 18)
8844 {"no-m4100", no_argument
, NULL
, OPTION_NO_M4100
},
8845 #define OPTION_MIPS16 (OPTION_MD_BASE + 22)
8846 {"mips16", no_argument
, NULL
, OPTION_MIPS16
},
8847 #define OPTION_NO_MIPS16 (OPTION_MD_BASE + 23)
8848 {"no-mips16", no_argument
, NULL
, OPTION_NO_MIPS16
},
8849 #define OPTION_M3900 (OPTION_MD_BASE + 26)
8850 {"m3900", no_argument
, NULL
, OPTION_M3900
},
8851 #define OPTION_NO_M3900 (OPTION_MD_BASE + 27)
8852 {"no-m3900", no_argument
, NULL
, OPTION_NO_M3900
},
8855 #define OPTION_MABI (OPTION_MD_BASE + 38)
8856 {"mabi", required_argument
, NULL
, OPTION_MABI
},
8858 #define OPTION_M7000_HILO_FIX (OPTION_MD_BASE + 39)
8859 {"mfix7000", no_argument
, NULL
, OPTION_M7000_HILO_FIX
},
8860 #define OPTION_NO_M7000_HILO_FIX (OPTION_MD_BASE + 40)
8861 {"no-fix-7000", no_argument
, NULL
, OPTION_NO_M7000_HILO_FIX
},
8863 #define OPTION_CALL_SHARED (OPTION_MD_BASE + 7)
8864 #define OPTION_NON_SHARED (OPTION_MD_BASE + 8)
8865 #define OPTION_XGOT (OPTION_MD_BASE + 19)
8866 #define OPTION_32 (OPTION_MD_BASE + 20)
8867 #define OPTION_64 (OPTION_MD_BASE + 21)
8869 {"KPIC", no_argument
, NULL
, OPTION_CALL_SHARED
},
8870 {"xgot", no_argument
, NULL
, OPTION_XGOT
},
8871 {"call_shared", no_argument
, NULL
, OPTION_CALL_SHARED
},
8872 {"non_shared", no_argument
, NULL
, OPTION_NON_SHARED
},
8873 {"32", no_argument
, NULL
, OPTION_32
},
8874 {"64", no_argument
, NULL
, OPTION_64
},
8877 #define OPTION_GP32 (OPTION_MD_BASE + 41)
8878 #define OPTION_GP64 (OPTION_MD_BASE + 42)
8879 {"mgp32", no_argument
, NULL
, OPTION_GP32
},
8880 {"mgp64", no_argument
, NULL
, OPTION_GP64
},
8882 {NULL
, no_argument
, NULL
, 0}
8884 size_t md_longopts_size
= sizeof(md_longopts
);
8887 md_parse_option (c
, arg
)
8902 target_big_endian
= 1;
8906 target_big_endian
= 0;
8910 if (arg
&& arg
[1] == '0')
8920 mips_debug
= atoi (arg
);
8921 /* When the MIPS assembler sees -g or -g2, it does not do
8922 optimizations which limit full symbolic debugging. We take
8923 that to be equivalent to -O0. */
8924 if (mips_debug
== 2)
8948 /* Identify the processor type */
8950 if (strcmp (p
, "default") == 0
8951 || strcmp (p
, "DEFAULT") == 0)
8957 /* We need to cope with the various "vr" prefixes for the 4300
8959 if (*p
== 'v' || *p
== 'V')
8965 if (*p
== 'r' || *p
== 'R')
8972 if (strcmp (p
, "10000") == 0
8973 || strcmp (p
, "10k") == 0
8974 || strcmp (p
, "10K") == 0)
8979 if (strcmp (p
, "2000") == 0
8980 || strcmp (p
, "2k") == 0
8981 || strcmp (p
, "2K") == 0)
8986 if (strcmp (p
, "3000") == 0
8987 || strcmp (p
, "3k") == 0
8988 || strcmp (p
, "3K") == 0)
8990 else if (strcmp (p
, "3900") == 0)
8995 if (strcmp (p
, "4000") == 0
8996 || strcmp (p
, "4k") == 0
8997 || strcmp (p
, "4K") == 0)
8999 else if (strcmp (p
, "4100") == 0)
9001 else if (strcmp (p
, "4111") == 0)
9003 else if (strcmp (p
, "4300") == 0)
9005 else if (strcmp (p
, "4400") == 0)
9007 else if (strcmp (p
, "4600") == 0)
9009 else if (strcmp (p
, "4650") == 0)
9011 else if (strcmp (p
, "4010") == 0)
9016 if (strcmp (p
, "5000") == 0
9017 || strcmp (p
, "5k") == 0
9018 || strcmp (p
, "5K") == 0)
9023 if (strcmp (p
, "6000") == 0
9024 || strcmp (p
, "6k") == 0
9025 || strcmp (p
, "6K") == 0)
9030 if (strcmp (p
, "8000") == 0
9031 || strcmp (p
, "8k") == 0
9032 || strcmp (p
, "8K") == 0)
9037 if (strcmp (p
, "orion") == 0)
9043 switch (atoi (p
+ 1))
9059 && (mips_cpu
!= 4300
9062 && mips_cpu
!= 5000))
9064 as_bad (_("ignoring invalid leading 'v' in -mcpu=%s switch"), arg
);
9070 as_bad (_("invalid architecture -mcpu=%s"), arg
);
9081 case OPTION_NO_M4650
:
9088 case OPTION_NO_M4010
:
9095 case OPTION_NO_M4100
:
9103 case OPTION_NO_M3900
:
9107 mips_opts
.mips16
= 1;
9108 mips_no_prev_insn (false);
9111 case OPTION_NO_MIPS16
:
9112 mips_opts
.mips16
= 0;
9113 mips_no_prev_insn (false);
9116 case OPTION_MEMBEDDED_PIC
:
9117 mips_pic
= EMBEDDED_PIC
;
9118 if (USE_GLOBAL_POINTER_OPT
&& g_switch_seen
)
9120 as_bad (_("-G may not be used with embedded PIC code"));
9123 g_switch_value
= 0x7fffffff;
9126 /* When generating ELF code, we permit -KPIC and -call_shared to
9127 select SVR4_PIC, and -non_shared to select no PIC. This is
9128 intended to be compatible with Irix 5. */
9129 case OPTION_CALL_SHARED
:
9130 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9132 as_bad (_("-call_shared is supported only for ELF format"));
9135 mips_pic
= SVR4_PIC
;
9136 if (g_switch_seen
&& g_switch_value
!= 0)
9138 as_bad (_("-G may not be used with SVR4 PIC code"));
9144 case OPTION_NON_SHARED
:
9145 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
9147 as_bad (_("-non_shared is supported only for ELF format"));
9153 /* The -xgot option tells the assembler to use 32 offsets when
9154 accessing the got in SVR4_PIC mode. It is for Irix
9161 if (! USE_GLOBAL_POINTER_OPT
)
9163 as_bad (_("-G is not supported for this configuration"));
9166 else if (mips_pic
== SVR4_PIC
|| mips_pic
== EMBEDDED_PIC
)
9168 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
9172 g_switch_value
= atoi (arg
);
9176 /* The -32 and -64 options tell the assembler to output the 32
9177 bit or the 64 bit MIPS ELF format. */
9184 const char **list
, **l
;
9186 list
= bfd_target_list ();
9187 for (l
= list
; *l
!= NULL
; l
++)
9188 if (strcmp (*l
, "elf64-bigmips") == 0
9189 || strcmp (*l
, "elf64-littlemips") == 0)
9192 as_fatal (_("No compiled in support for 64 bit object file format"));
9202 /* We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
9203 flag in object files because to do so would make it
9204 impossible to link with libraries compiled without "-gp32".
9205 This is unnecessarily restrictive.
9207 We could solve this problem by adding "-gp32" multilibs to
9208 gcc, but to set this flag before gcc is built with such
9209 multilibs will break too many systems. */
9211 /* mips_32bitmode = 1; */
9217 /* mips_32bitmode = 0; */
9221 if (strcmp (arg
,"32") == 0
9222 || strcmp (arg
,"n32") == 0
9223 || strcmp (arg
,"64") == 0
9224 || strcmp (arg
,"o64") == 0
9225 || strcmp (arg
,"eabi") == 0)
9226 mips_abi_string
= arg
;
9229 case OPTION_M7000_HILO_FIX
:
9230 mips_7000_hilo_fix
= true;
9233 case OPTION_NO_M7000_HILO_FIX
:
9234 mips_7000_hilo_fix
= false;
9246 show (stream
, string
, col_p
, first_p
)
9254 fprintf (stream
, "%24s", "");
9259 fprintf (stream
, ", ");
9263 if (*col_p
+ strlen (string
) > 72)
9265 fprintf (stream
, "\n%24s", "");
9269 fprintf (stream
, "%s", string
);
9270 *col_p
+= strlen (string
);
9277 md_show_usage (stream
)
9282 fprintf(stream
, _("\
9284 -membedded-pic generate embedded position independent code\n\
9285 -EB generate big endian output\n\
9286 -EL generate little endian output\n\
9287 -g, -g2 do not remove uneeded NOPs or swap branches\n\
9288 -G NUM allow referencing objects up to NUM bytes\n\
9289 implicitly with the gp register [default 8]\n"));
9290 fprintf(stream
, _("\
9291 -mips1 generate MIPS ISA I instructions\n\
9292 -mips2 generate MIPS ISA II instructions\n\
9293 -mips3 generate MIPS ISA III instructions\n\
9294 -mips4 generate MIPS ISA IV instructions\n\
9295 -mcpu=CPU generate code for CPU, where CPU is one of:\n"));
9299 show (stream
, "2000", &column
, &first
);
9300 show (stream
, "3000", &column
, &first
);
9301 show (stream
, "3900", &column
, &first
);
9302 show (stream
, "4000", &column
, &first
);
9303 show (stream
, "4010", &column
, &first
);
9304 show (stream
, "4100", &column
, &first
);
9305 show (stream
, "4111", &column
, &first
);
9306 show (stream
, "4300", &column
, &first
);
9307 show (stream
, "4400", &column
, &first
);
9308 show (stream
, "4600", &column
, &first
);
9309 show (stream
, "4650", &column
, &first
);
9310 show (stream
, "5000", &column
, &first
);
9311 show (stream
, "6000", &column
, &first
);
9312 show (stream
, "8000", &column
, &first
);
9313 show (stream
, "10000", &column
, &first
);
9314 fputc ('\n', stream
);
9316 fprintf (stream
, _("\
9317 -mCPU equivalent to -mcpu=CPU.\n\
9318 -no-mCPU don't generate code specific to CPU.\n\
9319 For -mCPU and -no-mCPU, CPU must be one of:\n"));
9323 show (stream
, "3900", &column
, &first
);
9324 show (stream
, "4010", &column
, &first
);
9325 show (stream
, "4100", &column
, &first
);
9326 show (stream
, "4650", &column
, &first
);
9327 fputc ('\n', stream
);
9329 fprintf(stream
, _("\
9330 -mips16 generate mips16 instructions\n\
9331 -no-mips16 do not generate mips16 instructions\n"));
9332 fprintf(stream
, _("\
9333 -O0 remove unneeded NOPs, do not swap branches\n\
9334 -O remove unneeded NOPs and swap branches\n\
9335 --trap, --no-break trap exception on div by 0 and mult overflow\n\
9336 --break, --no-trap break exception on div by 0 and mult overflow\n"));
9338 fprintf(stream
, _("\
9339 -KPIC, -call_shared generate SVR4 position independent code\n\
9340 -non_shared do not generate position independent code\n\
9341 -xgot assume a 32 bit GOT\n\
9342 -32 create 32 bit object file (default)\n\
9343 -64 create 64 bit object file\n"));
9348 mips_init_after_args ()
9350 /* initialize opcodes */
9351 bfd_mips_num_opcodes
= bfd_mips_num_builtin_opcodes
;
9352 mips_opcodes
= (struct mips_opcode
*) mips_builtin_opcodes
;
9356 md_pcrel_from (fixP
)
9359 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
9360 && fixP
->fx_addsy
!= (symbolS
*) NULL
9361 && ! S_IS_DEFINED (fixP
->fx_addsy
))
9363 /* This makes a branch to an undefined symbol be a branch to the
9364 current location. */
9368 /* return the address of the delay slot */
9369 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
9372 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a
9373 reloc for a cons. We could use the definition there, except that
9374 we want to handle 64 bit relocs specially. */
9377 cons_fix_new_mips (frag
, where
, nbytes
, exp
)
9378 fragS
*frag ATTRIBUTE_UNUSED
;
9380 unsigned int nbytes
;
9384 /* If we are assembling in 32 bit mode, turn an 8 byte reloc into a
9386 if (nbytes
== 8 && ! mips_64
)
9388 if (target_big_endian
)
9394 if (nbytes
!= 2 && nbytes
!= 4 && nbytes
!= 8)
9395 as_bad (_("Unsupported reloc size %d"), nbytes
);
9397 fix_new_exp (frag_now
, where
, (int) nbytes
, exp
, 0,
9400 : (nbytes
== 4 ? BFD_RELOC_32
: BFD_RELOC_64
)));
9403 /* This is called before the symbol table is processed. In order to
9404 work with gcc when using mips-tfile, we must keep all local labels.
9405 However, in other cases, we want to discard them. If we were
9406 called with -g, but we didn't see any debugging information, it may
9407 mean that gcc is smuggling debugging information through to
9408 mips-tfile, in which case we must generate all local labels. */
9411 mips_frob_file_before_adjust ()
9413 #ifndef NO_ECOFF_DEBUGGING
9416 && ! ecoff_debugging_seen
)
9417 flag_keep_locals
= 1;
9421 /* Sort any unmatched HI16_S relocs so that they immediately precede
9422 the corresponding LO reloc. This is called before md_apply_fix and
9423 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
9424 explicit use of the %hi modifier. */
9429 struct mips_hi_fixup
*l
;
9431 for (l
= mips_hi_fixup_list
; l
!= NULL
; l
= l
->next
)
9433 segment_info_type
*seginfo
;
9436 assert (l
->fixp
->fx_r_type
== BFD_RELOC_HI16_S
);
9438 /* Check quickly whether the next fixup happens to be a matching
9440 if (l
->fixp
->fx_next
!= NULL
9441 && l
->fixp
->fx_next
->fx_r_type
== BFD_RELOC_LO16
9442 && l
->fixp
->fx_addsy
== l
->fixp
->fx_next
->fx_addsy
9443 && l
->fixp
->fx_offset
== l
->fixp
->fx_next
->fx_offset
)
9446 /* Look through the fixups for this segment for a matching %lo.
9447 When we find one, move the %hi just in front of it. We do
9448 this in two passes. In the first pass, we try to find a
9449 unique %lo. In the second pass, we permit multiple %hi
9450 relocs for a single %lo (this is a GNU extension). */
9451 seginfo
= seg_info (l
->seg
);
9452 for (pass
= 0; pass
< 2; pass
++)
9457 for (f
= seginfo
->fix_root
; f
!= NULL
; f
= f
->fx_next
)
9459 /* Check whether this is a %lo fixup which matches l->fixp. */
9460 if (f
->fx_r_type
== BFD_RELOC_LO16
9461 && f
->fx_addsy
== l
->fixp
->fx_addsy
9462 && f
->fx_offset
== l
->fixp
->fx_offset
9465 || prev
->fx_r_type
!= BFD_RELOC_HI16_S
9466 || prev
->fx_addsy
!= f
->fx_addsy
9467 || prev
->fx_offset
!= f
->fx_offset
))
9471 /* Move l->fixp before f. */
9472 for (pf
= &seginfo
->fix_root
;
9474 pf
= &(*pf
)->fx_next
)
9475 assert (*pf
!= NULL
);
9477 *pf
= l
->fixp
->fx_next
;
9479 l
->fixp
->fx_next
= f
;
9481 seginfo
->fix_root
= l
->fixp
;
9483 prev
->fx_next
= l
->fixp
;
9494 #if 0 /* GCC code motion plus incomplete dead code elimination
9495 can leave a %hi without a %lo. */
9497 as_warn_where (l
->fixp
->fx_file
, l
->fixp
->fx_line
,
9498 _("Unmatched %%hi reloc"));
9504 /* When generating embedded PIC code we need to use a special
9505 relocation to represent the difference of two symbols in the .text
9506 section (switch tables use a difference of this sort). See
9507 include/coff/mips.h for details. This macro checks whether this
9508 fixup requires the special reloc. */
9509 #define SWITCH_TABLE(fixp) \
9510 ((fixp)->fx_r_type == BFD_RELOC_32 \
9511 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
9512 && (fixp)->fx_addsy != NULL \
9513 && (fixp)->fx_subsy != NULL \
9514 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
9515 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
9517 /* When generating embedded PIC code we must keep all PC relative
9518 relocations, in case the linker has to relax a call. We also need
9519 to keep relocations for switch table entries. */
9523 mips_force_relocation (fixp
)
9526 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9527 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
9530 return (mips_pic
== EMBEDDED_PIC
9532 || SWITCH_TABLE (fixp
)
9533 || fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
9534 || fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
));
9537 /* Apply a fixup to the object file. */
9540 md_apply_fix (fixP
, valueP
)
9547 assert (fixP
->fx_size
== 4
9548 || fixP
->fx_r_type
== BFD_RELOC_16
9549 || fixP
->fx_r_type
== BFD_RELOC_64
9550 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
9551 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
);
9555 /* If we aren't adjusting this fixup to be against the section
9556 symbol, we need to adjust the value. */
9558 if (fixP
->fx_addsy
!= NULL
&& OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
9560 if (S_GET_OTHER (fixP
->fx_addsy
) == STO_MIPS16
9561 || S_IS_WEAK (fixP
->fx_addsy
)
9562 || (symbol_used_in_reloc_p (fixP
->fx_addsy
)
9563 && (((bfd_get_section_flags (stdoutput
,
9564 S_GET_SEGMENT (fixP
->fx_addsy
))
9565 & SEC_LINK_ONCE
) != 0)
9566 || !strncmp (segment_name (S_GET_SEGMENT (fixP
->fx_addsy
)),
9568 sizeof (".gnu.linkonce") - 1))))
9571 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9572 if (value
!= 0 && ! fixP
->fx_pcrel
)
9574 /* In this case, the bfd_install_relocation routine will
9575 incorrectly add the symbol value back in. We just want
9576 the addend to appear in the object file.
9577 FIXME: If this makes VALUE zero, we're toast. */
9578 value
-= S_GET_VALUE (fixP
->fx_addsy
);
9582 /* This code was generated using trial and error and so is
9583 fragile and not trustworthy. If you change it, you should
9584 rerun the elf-rel, elf-rel2, and empic testcases and ensure
9586 if (fixP
->fx_pcrel
|| fixP
->fx_subsy
!= NULL
)
9588 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9590 /* BFD's REL handling, for MIPS, is _very_ weird.
9591 This gives the right results, but it can't possibly
9592 be the way things are supposed to work. */
9593 if (fixP
->fx_r_type
!= BFD_RELOC_16_PCREL_S2
9594 || S_GET_SEGMENT (fixP
->fx_addsy
) != undefined_section
)
9595 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9600 fixP
->fx_addnumber
= value
; /* Remember value for tc_gen_reloc */
9602 if (fixP
->fx_addsy
== NULL
&& ! fixP
->fx_pcrel
)
9605 switch (fixP
->fx_r_type
)
9607 case BFD_RELOC_MIPS_JMP
:
9608 case BFD_RELOC_HI16
:
9609 case BFD_RELOC_HI16_S
:
9610 case BFD_RELOC_MIPS_GPREL
:
9611 case BFD_RELOC_MIPS_LITERAL
:
9612 case BFD_RELOC_MIPS_CALL16
:
9613 case BFD_RELOC_MIPS_GOT16
:
9614 case BFD_RELOC_MIPS_GPREL32
:
9615 case BFD_RELOC_MIPS_GOT_HI16
:
9616 case BFD_RELOC_MIPS_GOT_LO16
:
9617 case BFD_RELOC_MIPS_CALL_HI16
:
9618 case BFD_RELOC_MIPS_CALL_LO16
:
9619 case BFD_RELOC_MIPS16_GPREL
:
9621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9622 _("Invalid PC relative reloc"));
9623 /* Nothing needed to do. The value comes from the reloc entry */
9626 case BFD_RELOC_MIPS16_JMP
:
9627 /* We currently always generate a reloc against a symbol, which
9628 means that we don't want an addend even if the symbol is
9630 fixP
->fx_addnumber
= 0;
9633 case BFD_RELOC_PCREL_HI16_S
:
9634 /* The addend for this is tricky if it is internal, so we just
9635 do everything here rather than in bfd_install_relocation. */
9636 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9641 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9643 /* For an external symbol adjust by the address to make it
9644 pcrel_offset. We use the address of the RELLO reloc
9645 which follows this one. */
9646 value
+= (fixP
->fx_next
->fx_frag
->fr_address
9647 + fixP
->fx_next
->fx_where
);
9652 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9653 if (target_big_endian
)
9655 md_number_to_chars (buf
, value
, 2);
9658 case BFD_RELOC_PCREL_LO16
:
9659 /* The addend for this is tricky if it is internal, so we just
9660 do everything here rather than in bfd_install_relocation. */
9661 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
9666 && (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_SECTION_SYM
) == 0)
9667 value
+= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9668 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9669 if (target_big_endian
)
9671 md_number_to_chars (buf
, value
, 2);
9675 /* This is handled like BFD_RELOC_32, but we output a sign
9676 extended value if we are only 32 bits. */
9678 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9680 if (8 <= sizeof (valueT
))
9681 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9688 w1
= w2
= fixP
->fx_where
;
9689 if (target_big_endian
)
9693 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w1
, value
, 4);
9694 if ((value
& 0x80000000) != 0)
9698 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ w2
, hiv
, 4);
9705 /* If we are deleting this reloc entry, we must fill in the
9706 value now. This can happen if we have a .word which is not
9707 resolved when it appears but is later defined. We also need
9708 to fill in the value if this is an embedded PIC switch table
9711 || (mips_pic
== EMBEDDED_PIC
&& SWITCH_TABLE (fixP
)))
9712 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9717 /* If we are deleting this reloc entry, we must fill in the
9719 assert (fixP
->fx_size
== 2);
9721 md_number_to_chars (fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
,
9725 case BFD_RELOC_LO16
:
9726 /* When handling an embedded PIC switch statement, we can wind
9727 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
9730 if (value
< -0x8000 || value
> 0x7fff)
9731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9732 _("relocation overflow"));
9733 buf
= (unsigned char *) fixP
->fx_frag
->fr_literal
+ fixP
->fx_where
;
9734 if (target_big_endian
)
9736 md_number_to_chars (buf
, value
, 2);
9740 case BFD_RELOC_16_PCREL_S2
:
9742 * We need to save the bits in the instruction since fixup_segment()
9743 * might be deleting the relocation entry (i.e., a branch within
9744 * the current segment).
9746 if ((value
& 0x3) != 0)
9747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9748 _("Branch to odd address (%lx)"), value
);
9750 if (!fixP
->fx_done
&& value
!= 0)
9752 /* If 'value' is zero, the remaining reloc code won't actually
9753 do the store, so it must be done here. This is probably
9756 value
-= fixP
->fx_frag
->fr_address
+ fixP
->fx_where
;
9760 /* update old instruction data */
9761 buf
= (unsigned char *) (fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
);
9762 if (target_big_endian
)
9763 insn
= (buf
[0] << 24) | (buf
[1] << 16) | (buf
[2] << 8) | buf
[3];
9765 insn
= (buf
[3] << 24) | (buf
[2] << 16) | (buf
[1] << 8) | buf
[0];
9767 if (value
>= -0x8000 && value
< 0x8000)
9768 insn
|= value
& 0xffff;
9771 /* The branch offset is too large. If this is an
9772 unconditional branch, and we are not generating PIC code,
9773 we can convert it to an absolute jump instruction. */
9774 if (mips_pic
== NO_PIC
9776 && fixP
->fx_frag
->fr_address
>= text_section
->vma
9777 && (fixP
->fx_frag
->fr_address
9778 < text_section
->vma
+ text_section
->_raw_size
)
9779 && ((insn
& 0xffff0000) == 0x10000000 /* beq $0,$0 */
9780 || (insn
& 0xffff0000) == 0x04010000 /* bgez $0 */
9781 || (insn
& 0xffff0000) == 0x04110000)) /* bgezal $0 */
9783 if ((insn
& 0xffff0000) == 0x04110000) /* bgezal $0 */
9784 insn
= 0x0c000000; /* jal */
9786 insn
= 0x08000000; /* j */
9787 fixP
->fx_r_type
= BFD_RELOC_MIPS_JMP
;
9789 fixP
->fx_addsy
= section_symbol (text_section
);
9790 fixP
->fx_addnumber
= (value
<< 2) + md_pcrel_from (fixP
);
9794 /* FIXME. It would be possible in principle to handle
9795 conditional branches which overflow. They could be
9796 transformed into a branch around a jump. This would
9797 require setting up variant frags for each different
9798 branch type. The native MIPS assembler attempts to
9799 handle these cases, but it appears to do it
9801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
9802 _("Branch out of range"));
9806 md_number_to_chars ((char *) buf
, (valueT
) insn
, 4);
9809 case BFD_RELOC_VTABLE_INHERIT
:
9812 && !S_IS_DEFINED (fixP
->fx_addsy
)
9813 && !S_IS_WEAK (fixP
->fx_addsy
))
9814 S_SET_WEAK (fixP
->fx_addsy
);
9817 case BFD_RELOC_VTABLE_ENTRY
:
9833 const struct mips_opcode
*p
;
9834 int treg
, sreg
, dreg
, shamt
;
9839 for (i
= 0; i
< NUMOPCODES
; ++i
)
9841 p
= &mips_opcodes
[i
];
9842 if (((oc
& p
->mask
) == p
->match
) && (p
->pinfo
!= INSN_MACRO
))
9844 printf ("%08lx %s\t", oc
, p
->name
);
9845 treg
= (oc
>> 16) & 0x1f;
9846 sreg
= (oc
>> 21) & 0x1f;
9847 dreg
= (oc
>> 11) & 0x1f;
9848 shamt
= (oc
>> 6) & 0x1f;
9850 for (args
= p
->args
;; ++args
)
9861 printf ("%c", *args
);
9865 assert (treg
== sreg
);
9866 printf ("$%d,$%d", treg
, sreg
);
9871 printf ("$%d", dreg
);
9876 printf ("$%d", treg
);
9880 printf ("0x%x", treg
);
9885 printf ("$%d", sreg
);
9889 printf ("0x%08lx", oc
& 0x1ffffff);
9901 printf ("$%d", shamt
);
9912 printf (_("%08lx UNDEFINED\n"), oc
);
9923 name
= input_line_pointer
;
9924 c
= get_symbol_end ();
9925 p
= (symbolS
*) symbol_find_or_make (name
);
9926 *input_line_pointer
= c
;
9930 /* Align the current frag to a given power of two. The MIPS assembler
9931 also automatically adjusts any preceding label. */
9934 mips_align (to
, fill
, label
)
9939 mips_emit_delays (false);
9940 frag_align (to
, fill
, 0);
9941 record_alignment (now_seg
, to
);
9944 assert (S_GET_SEGMENT (label
) == now_seg
);
9945 symbol_set_frag (label
, frag_now
);
9946 S_SET_VALUE (label
, (valueT
) frag_now_fix ());
9950 /* Align to a given power of two. .align 0 turns off the automatic
9951 alignment used by the data creating pseudo-ops. */
9955 int x ATTRIBUTE_UNUSED
;
9958 register long temp_fill
;
9959 long max_alignment
= 15;
9963 o Note that the assembler pulls down any immediately preceeding label
9964 to the aligned address.
9965 o It's not documented but auto alignment is reinstated by
9966 a .align pseudo instruction.
9967 o Note also that after auto alignment is turned off the mips assembler
9968 issues an error on attempt to assemble an improperly aligned data item.
9973 temp
= get_absolute_expression ();
9974 if (temp
> max_alignment
)
9975 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
9978 as_warn (_("Alignment negative: 0 assumed."));
9981 if (*input_line_pointer
== ',')
9983 input_line_pointer
++;
9984 temp_fill
= get_absolute_expression ();
9991 mips_align (temp
, (int) temp_fill
,
9992 insn_labels
!= NULL
? insn_labels
->label
: NULL
);
9999 demand_empty_rest_of_line ();
10003 mips_flush_pending_output ()
10005 mips_emit_delays (false);
10006 mips_clear_insn_labels ();
10015 /* When generating embedded PIC code, we only use the .text, .lit8,
10016 .sdata and .sbss sections. We change the .data and .rdata
10017 pseudo-ops to use .sdata. */
10018 if (mips_pic
== EMBEDDED_PIC
10019 && (sec
== 'd' || sec
== 'r'))
10023 /* The ELF backend needs to know that we are changing sections, so
10024 that .previous works correctly. We could do something like check
10025 for a obj_section_change_hook macro, but that might be confusing
10026 as it would not be appropriate to use it in the section changing
10027 functions in read.c, since obj-elf.c intercepts those. FIXME:
10028 This should be cleaner, somehow. */
10029 obj_elf_section_change_hook ();
10032 mips_emit_delays (false);
10042 subseg_set (bss_section
, (subsegT
) get_absolute_expression ());
10043 demand_empty_rest_of_line ();
10047 if (USE_GLOBAL_POINTER_OPT
)
10049 seg
= subseg_new (RDATA_SECTION_NAME
,
10050 (subsegT
) get_absolute_expression ());
10051 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10053 bfd_set_section_flags (stdoutput
, seg
,
10059 if (strcmp (TARGET_OS
, "elf") != 0)
10060 record_alignment (seg
, 4);
10062 demand_empty_rest_of_line ();
10066 as_bad (_("No read only data section in this object file format"));
10067 demand_empty_rest_of_line ();
10073 if (USE_GLOBAL_POINTER_OPT
)
10075 seg
= subseg_new (".sdata", (subsegT
) get_absolute_expression ());
10076 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
10078 bfd_set_section_flags (stdoutput
, seg
,
10079 SEC_ALLOC
| SEC_LOAD
| SEC_RELOC
10081 if (strcmp (TARGET_OS
, "elf") != 0)
10082 record_alignment (seg
, 4);
10084 demand_empty_rest_of_line ();
10089 as_bad (_("Global pointers not supported; recompile -G 0"));
10090 demand_empty_rest_of_line ();
10099 mips_enable_auto_align ()
10110 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10111 mips_emit_delays (false);
10112 if (log_size
> 0 && auto_align
)
10113 mips_align (log_size
, 0, label
);
10114 mips_clear_insn_labels ();
10115 cons (1 << log_size
);
10119 s_float_cons (type
)
10124 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10126 mips_emit_delays (false);
10131 mips_align (3, 0, label
);
10133 mips_align (2, 0, label
);
10136 mips_clear_insn_labels ();
10141 /* Handle .globl. We need to override it because on Irix 5 you are
10144 where foo is an undefined symbol, to mean that foo should be
10145 considered to be the address of a function. */
10149 int x ATTRIBUTE_UNUSED
;
10156 name
= input_line_pointer
;
10157 c
= get_symbol_end ();
10158 symbolP
= symbol_find_or_make (name
);
10159 *input_line_pointer
= c
;
10160 SKIP_WHITESPACE ();
10162 /* On Irix 5, every global symbol that is not explicitly labelled as
10163 being a function is apparently labelled as being an object. */
10166 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10171 secname
= input_line_pointer
;
10172 c
= get_symbol_end ();
10173 sec
= bfd_get_section_by_name (stdoutput
, secname
);
10175 as_bad (_("%s: no such section"), secname
);
10176 *input_line_pointer
= c
;
10178 if (sec
!= NULL
&& (sec
->flags
& SEC_CODE
) != 0)
10179 flag
= BSF_FUNCTION
;
10182 symbol_get_bfdsym (symbolP
)->flags
|= flag
;
10184 S_SET_EXTERNAL (symbolP
);
10185 demand_empty_rest_of_line ();
10190 int x ATTRIBUTE_UNUSED
;
10195 opt
= input_line_pointer
;
10196 c
= get_symbol_end ();
10200 /* FIXME: What does this mean? */
10202 else if (strncmp (opt
, "pic", 3) == 0)
10206 i
= atoi (opt
+ 3);
10210 mips_pic
= SVR4_PIC
;
10212 as_bad (_(".option pic%d not supported"), i
);
10214 if (USE_GLOBAL_POINTER_OPT
&& mips_pic
== SVR4_PIC
)
10216 if (g_switch_seen
&& g_switch_value
!= 0)
10217 as_warn (_("-G may not be used with SVR4 PIC code"));
10218 g_switch_value
= 0;
10219 bfd_set_gp_size (stdoutput
, 0);
10223 as_warn (_("Unrecognized option \"%s\""), opt
);
10225 *input_line_pointer
= c
;
10226 demand_empty_rest_of_line ();
10229 /* This structure is used to hold a stack of .set values. */
10231 struct mips_option_stack
10233 struct mips_option_stack
*next
;
10234 struct mips_set_options options
;
10237 static struct mips_option_stack
*mips_opts_stack
;
10239 /* Handle the .set pseudo-op. */
10243 int x ATTRIBUTE_UNUSED
;
10245 char *name
= input_line_pointer
, ch
;
10247 while (!is_end_of_line
[(unsigned char) *input_line_pointer
])
10248 input_line_pointer
++;
10249 ch
= *input_line_pointer
;
10250 *input_line_pointer
= '\0';
10252 if (strcmp (name
, "reorder") == 0)
10254 if (mips_opts
.noreorder
&& prev_nop_frag
!= NULL
)
10256 /* If we still have pending nops, we can discard them. The
10257 usual nop handling will insert any that are still
10259 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10260 * (mips_opts
.mips16
? 2 : 4));
10261 prev_nop_frag
= NULL
;
10263 mips_opts
.noreorder
= 0;
10265 else if (strcmp (name
, "noreorder") == 0)
10267 mips_emit_delays (true);
10268 mips_opts
.noreorder
= 1;
10269 mips_any_noreorder
= 1;
10271 else if (strcmp (name
, "at") == 0)
10273 mips_opts
.noat
= 0;
10275 else if (strcmp (name
, "noat") == 0)
10277 mips_opts
.noat
= 1;
10279 else if (strcmp (name
, "macro") == 0)
10281 mips_opts
.warn_about_macros
= 0;
10283 else if (strcmp (name
, "nomacro") == 0)
10285 if (mips_opts
.noreorder
== 0)
10286 as_bad (_("`noreorder' must be set before `nomacro'"));
10287 mips_opts
.warn_about_macros
= 1;
10289 else if (strcmp (name
, "move") == 0 || strcmp (name
, "novolatile") == 0)
10291 mips_opts
.nomove
= 0;
10293 else if (strcmp (name
, "nomove") == 0 || strcmp (name
, "volatile") == 0)
10295 mips_opts
.nomove
= 1;
10297 else if (strcmp (name
, "bopt") == 0)
10299 mips_opts
.nobopt
= 0;
10301 else if (strcmp (name
, "nobopt") == 0)
10303 mips_opts
.nobopt
= 1;
10305 else if (strcmp (name
, "mips16") == 0
10306 || strcmp (name
, "MIPS-16") == 0)
10307 mips_opts
.mips16
= 1;
10308 else if (strcmp (name
, "nomips16") == 0
10309 || strcmp (name
, "noMIPS-16") == 0)
10310 mips_opts
.mips16
= 0;
10311 else if (strncmp (name
, "mips", 4) == 0)
10315 /* Permit the user to change the ISA on the fly. Needless to
10316 say, misuse can cause serious problems. */
10317 isa
= atoi (name
+ 4);
10319 mips_opts
.isa
= file_mips_isa
;
10320 else if (isa
< 1 || isa
> 4)
10321 as_bad (_("unknown ISA level"));
10323 mips_opts
.isa
= isa
;
10325 else if (strcmp (name
, "autoextend") == 0)
10326 mips_opts
.noautoextend
= 0;
10327 else if (strcmp (name
, "noautoextend") == 0)
10328 mips_opts
.noautoextend
= 1;
10329 else if (strcmp (name
, "push") == 0)
10331 struct mips_option_stack
*s
;
10333 s
= (struct mips_option_stack
*) xmalloc (sizeof *s
);
10334 s
->next
= mips_opts_stack
;
10335 s
->options
= mips_opts
;
10336 mips_opts_stack
= s
;
10338 else if (strcmp (name
, "pop") == 0)
10340 struct mips_option_stack
*s
;
10342 s
= mips_opts_stack
;
10344 as_bad (_(".set pop with no .set push"));
10347 /* If we're changing the reorder mode we need to handle
10348 delay slots correctly. */
10349 if (s
->options
.noreorder
&& ! mips_opts
.noreorder
)
10350 mips_emit_delays (true);
10351 else if (! s
->options
.noreorder
&& mips_opts
.noreorder
)
10353 if (prev_nop_frag
!= NULL
)
10355 prev_nop_frag
->fr_fix
-= (prev_nop_frag_holds
10356 * (mips_opts
.mips16
? 2 : 4));
10357 prev_nop_frag
= NULL
;
10361 mips_opts
= s
->options
;
10362 mips_opts_stack
= s
->next
;
10368 as_warn (_("Tried to set unrecognized symbol: %s\n"), name
);
10370 *input_line_pointer
= ch
;
10371 demand_empty_rest_of_line ();
10374 /* Handle the .abicalls pseudo-op. I believe this is equivalent to
10375 .option pic2. It means to generate SVR4 PIC calls. */
10378 s_abicalls (ignore
)
10379 int ignore ATTRIBUTE_UNUSED
;
10381 mips_pic
= SVR4_PIC
;
10382 if (USE_GLOBAL_POINTER_OPT
)
10384 if (g_switch_seen
&& g_switch_value
!= 0)
10385 as_warn (_("-G may not be used with SVR4 PIC code"));
10386 g_switch_value
= 0;
10388 bfd_set_gp_size (stdoutput
, 0);
10389 demand_empty_rest_of_line ();
10392 /* Handle the .cpload pseudo-op. This is used when generating SVR4
10393 PIC code. It sets the $gp register for the function based on the
10394 function address, which is in the register named in the argument.
10395 This uses a relocation against _gp_disp, which is handled specially
10396 by the linker. The result is:
10397 lui $gp,%hi(_gp_disp)
10398 addiu $gp,$gp,%lo(_gp_disp)
10399 addu $gp,$gp,.cpload argument
10400 The .cpload argument is normally $25 == $t9. */
10404 int ignore ATTRIBUTE_UNUSED
;
10409 /* If we are not generating SVR4 PIC code, .cpload is ignored. */
10410 if (mips_pic
!= SVR4_PIC
)
10416 /* .cpload should be a in .set noreorder section. */
10417 if (mips_opts
.noreorder
== 0)
10418 as_warn (_(".cpload not in noreorder section"));
10420 ex
.X_op
= O_symbol
;
10421 ex
.X_add_symbol
= symbol_find_or_make ("_gp_disp");
10422 ex
.X_op_symbol
= NULL
;
10423 ex
.X_add_number
= 0;
10425 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
10426 symbol_get_bfdsym (ex
.X_add_symbol
)->flags
|= BSF_OBJECT
;
10428 macro_build_lui ((char *) NULL
, &icnt
, &ex
, GP
);
10429 macro_build ((char *) NULL
, &icnt
, &ex
, "addiu", "t,r,j", GP
, GP
,
10430 (int) BFD_RELOC_LO16
);
10432 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
, "addu", "d,v,t",
10433 GP
, GP
, tc_get_register (0));
10435 demand_empty_rest_of_line ();
10438 /* Handle the .cprestore pseudo-op. This stores $gp into a given
10439 offset from $sp. The offset is remembered, and after making a PIC
10440 call $gp is restored from that location. */
10443 s_cprestore (ignore
)
10444 int ignore ATTRIBUTE_UNUSED
;
10449 /* If we are not generating SVR4 PIC code, .cprestore is ignored. */
10450 if (mips_pic
!= SVR4_PIC
)
10456 mips_cprestore_offset
= get_absolute_expression ();
10458 ex
.X_op
= O_constant
;
10459 ex
.X_add_symbol
= NULL
;
10460 ex
.X_op_symbol
= NULL
;
10461 ex
.X_add_number
= mips_cprestore_offset
;
10463 macro_build ((char *) NULL
, &icnt
, &ex
,
10464 ((bfd_arch_bits_per_address (stdoutput
) == 32
10465 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10467 "t,o(b)", GP
, (int) BFD_RELOC_LO16
, SP
);
10469 demand_empty_rest_of_line ();
10472 /* Handle the .gpword pseudo-op. This is used when generating PIC
10473 code. It generates a 32 bit GP relative reloc. */
10477 int ignore ATTRIBUTE_UNUSED
;
10483 /* When not generating PIC code, this is treated as .word. */
10484 if (mips_pic
!= SVR4_PIC
)
10490 label
= insn_labels
!= NULL
? insn_labels
->label
: NULL
;
10491 mips_emit_delays (true);
10493 mips_align (2, 0, label
);
10494 mips_clear_insn_labels ();
10498 if (ex
.X_op
!= O_symbol
|| ex
.X_add_number
!= 0)
10500 as_bad (_("Unsupported use of .gpword"));
10501 ignore_rest_of_line ();
10505 md_number_to_chars (p
, (valueT
) 0, 4);
10506 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, 4, &ex
, 0,
10507 BFD_RELOC_MIPS_GPREL32
);
10509 demand_empty_rest_of_line ();
10512 /* Handle the .cpadd pseudo-op. This is used when dealing with switch
10513 tables in SVR4 PIC code. */
10517 int ignore ATTRIBUTE_UNUSED
;
10522 /* This is ignored when not generating SVR4 PIC code. */
10523 if (mips_pic
!= SVR4_PIC
)
10529 /* Add $gp to the register named as an argument. */
10530 reg
= tc_get_register (0);
10531 macro_build ((char *) NULL
, &icnt
, (expressionS
*) NULL
,
10532 ((bfd_arch_bits_per_address (stdoutput
) == 32
10533 || ! ISA_HAS_64BIT_REGS (mips_opts
.isa
))
10534 ? "addu" : "daddu"),
10535 "d,v,t", reg
, reg
, GP
);
10537 demand_empty_rest_of_line ();
10540 /* Handle the .insn pseudo-op. This marks instruction labels in
10541 mips16 mode. This permits the linker to handle them specially,
10542 such as generating jalx instructions when needed. We also make
10543 them odd for the duration of the assembly, in order to generate the
10544 right sort of code. We will make them even in the adjust_symtab
10545 routine, while leaving them marked. This is convenient for the
10546 debugger and the disassembler. The linker knows to make them odd
10551 int ignore ATTRIBUTE_UNUSED
;
10553 if (mips_opts
.mips16
)
10554 mips16_mark_labels ();
10556 demand_empty_rest_of_line ();
10559 /* Handle a .stabn directive. We need these in order to mark a label
10560 as being a mips16 text label correctly. Sometimes the compiler
10561 will emit a label, followed by a .stabn, and then switch sections.
10562 If the label and .stabn are in mips16 mode, then the label is
10563 really a mips16 text label. */
10569 if (type
== 'n' && mips_opts
.mips16
)
10570 mips16_mark_labels ();
10575 /* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
10579 s_mips_weakext (ignore
)
10580 int ignore ATTRIBUTE_UNUSED
;
10587 name
= input_line_pointer
;
10588 c
= get_symbol_end ();
10589 symbolP
= symbol_find_or_make (name
);
10590 S_SET_WEAK (symbolP
);
10591 *input_line_pointer
= c
;
10593 SKIP_WHITESPACE ();
10595 if (! is_end_of_line
[(unsigned char) *input_line_pointer
])
10597 if (S_IS_DEFINED (symbolP
))
10599 as_bad ("Ignoring attempt to redefine symbol `%s'.",
10600 S_GET_NAME (symbolP
));
10601 ignore_rest_of_line ();
10605 if (*input_line_pointer
== ',')
10607 ++input_line_pointer
;
10608 SKIP_WHITESPACE ();
10612 if (exp
.X_op
!= O_symbol
)
10614 as_bad ("bad .weakext directive");
10615 ignore_rest_of_line();
10618 symbol_set_value_expression (symbolP
, &exp
);
10621 demand_empty_rest_of_line ();
10624 /* Parse a register string into a number. Called from the ECOFF code
10625 to parse .frame. The argument is non-zero if this is the frame
10626 register, so that we can record it in mips_frame_reg. */
10629 tc_get_register (frame
)
10634 SKIP_WHITESPACE ();
10635 if (*input_line_pointer
++ != '$')
10637 as_warn (_("expected `$'"));
10640 else if (isdigit ((unsigned char) *input_line_pointer
))
10642 reg
= get_absolute_expression ();
10643 if (reg
< 0 || reg
>= 32)
10645 as_warn (_("Bad register number"));
10651 if (strncmp (input_line_pointer
, "fp", 2) == 0)
10653 else if (strncmp (input_line_pointer
, "sp", 2) == 0)
10655 else if (strncmp (input_line_pointer
, "gp", 2) == 0)
10657 else if (strncmp (input_line_pointer
, "at", 2) == 0)
10661 as_warn (_("Unrecognized register name"));
10664 input_line_pointer
+= 2;
10667 mips_frame_reg
= reg
!= 0 ? reg
: SP
;
10672 md_section_align (seg
, addr
)
10676 int align
= bfd_get_section_alignment (stdoutput
, seg
);
10679 /* We don't need to align ELF sections to the full alignment.
10680 However, Irix 5 may prefer that we align them at least to a 16
10681 byte boundary. We don't bother to align the sections if we are
10682 targeted for an embedded system. */
10683 if (strcmp (TARGET_OS
, "elf") == 0)
10689 return ((addr
+ (1 << align
) - 1) & (-1 << align
));
10692 /* Utility routine, called from above as well. If called while the
10693 input file is still being read, it's only an approximation. (For
10694 example, a symbol may later become defined which appeared to be
10695 undefined earlier.) */
10698 nopic_need_relax (sym
, before_relaxing
)
10700 int before_relaxing
;
10705 if (USE_GLOBAL_POINTER_OPT
)
10707 const char *symname
;
10710 /* Find out whether this symbol can be referenced off the GP
10711 register. It can be if it is smaller than the -G size or if
10712 it is in the .sdata or .sbss section. Certain symbols can
10713 not be referenced off the GP, although it appears as though
10715 symname
= S_GET_NAME (sym
);
10716 if (symname
!= (const char *) NULL
10717 && (strcmp (symname
, "eprol") == 0
10718 || strcmp (symname
, "etext") == 0
10719 || strcmp (symname
, "_gp") == 0
10720 || strcmp (symname
, "edata") == 0
10721 || strcmp (symname
, "_fbss") == 0
10722 || strcmp (symname
, "_fdata") == 0
10723 || strcmp (symname
, "_ftext") == 0
10724 || strcmp (symname
, "end") == 0
10725 || strcmp (symname
, "_gp_disp") == 0))
10727 else if ((! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
))
10729 #ifndef NO_ECOFF_DEBUGGING
10730 || (symbol_get_obj (sym
)->ecoff_extern_size
!= 0
10731 && (symbol_get_obj (sym
)->ecoff_extern_size
10732 <= g_switch_value
))
10734 /* We must defer this decision until after the whole
10735 file has been read, since there might be a .extern
10736 after the first use of this symbol. */
10737 || (before_relaxing
10738 #ifndef NO_ECOFF_DEBUGGING
10739 && symbol_get_obj (sym
)->ecoff_extern_size
== 0
10741 && S_GET_VALUE (sym
) == 0)
10742 || (S_GET_VALUE (sym
) != 0
10743 && S_GET_VALUE (sym
) <= g_switch_value
)))
10747 const char *segname
;
10749 segname
= segment_name (S_GET_SEGMENT (sym
));
10750 assert (strcmp (segname
, ".lit8") != 0
10751 && strcmp (segname
, ".lit4") != 0);
10752 change
= (strcmp (segname
, ".sdata") != 0
10753 && strcmp (segname
, ".sbss") != 0
10754 && strncmp (segname
, ".sdata.", 7) != 0
10755 && strncmp (segname
, ".gnu.linkonce.s.", 16) != 0);
10760 /* We are not optimizing for the GP register. */
10764 /* Given a mips16 variant frag FRAGP, return non-zero if it needs an
10765 extended opcode. SEC is the section the frag is in. */
10768 mips16_extended_frag (fragp
, sec
, stretch
)
10774 register const struct mips16_immed_operand
*op
;
10776 int mintiny
, maxtiny
;
10779 if (RELAX_MIPS16_USER_SMALL (fragp
->fr_subtype
))
10781 if (RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
))
10784 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
10785 op
= mips16_immed_operands
;
10786 while (op
->type
!= type
)
10789 assert (op
< mips16_immed_operands
+ MIPS16_NUM_IMMED
);
10794 if (type
== '<' || type
== '>' || type
== '[' || type
== ']')
10797 maxtiny
= 1 << op
->nbits
;
10802 maxtiny
= (1 << op
->nbits
) - 1;
10807 mintiny
= - (1 << (op
->nbits
- 1));
10808 maxtiny
= (1 << (op
->nbits
- 1)) - 1;
10811 /* We can't always call S_GET_VALUE here, because we don't want to
10812 lock in a particular frag address. */
10813 if (symbol_constant_p (fragp
->fr_symbol
))
10815 val
= (S_GET_VALUE (fragp
->fr_symbol
)
10816 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10817 symsec
= S_GET_SEGMENT (fragp
->fr_symbol
);
10819 else if (symbol_equated_p (fragp
->fr_symbol
)
10820 && (symbol_constant_p
10821 (symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
)))
10825 eqsym
= symbol_get_value_expression (fragp
->fr_symbol
)->X_add_symbol
;
10826 val
= (S_GET_VALUE (eqsym
)
10827 + symbol_get_frag (eqsym
)->fr_address
10828 + symbol_get_value_expression (fragp
->fr_symbol
)->X_add_number
10829 + symbol_get_frag (fragp
->fr_symbol
)->fr_address
);
10830 symsec
= S_GET_SEGMENT (eqsym
);
10839 /* We won't have the section when we are called from
10840 mips_relax_frag. However, we will always have been called
10841 from md_estimate_size_before_relax first. If this is a
10842 branch to a different section, we mark it as such. If SEC is
10843 NULL, and the frag is not marked, then it must be a branch to
10844 the same section. */
10847 if (RELAX_MIPS16_LONG_BRANCH (fragp
->fr_subtype
))
10854 fragp
->fr_subtype
=
10855 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10857 /* FIXME: We should support this, and let the linker
10858 catch branches and loads that are out of range. */
10859 as_bad_where (fragp
->fr_file
, fragp
->fr_line
,
10860 _("unsupported PC relative reference to different section"));
10866 /* In this case, we know for sure that the symbol fragment is in
10867 the same section. If the fr_address of the symbol fragment
10868 is greater then the address of this fragment we want to add
10869 in STRETCH in order to get a better estimate of the address.
10870 This particularly matters because of the shift bits. */
10872 && (symbol_get_frag (fragp
->fr_symbol
)->fr_address
10873 >= fragp
->fr_address
))
10877 /* Adjust stretch for any alignment frag. Note that if have
10878 been expanding the earlier code, the symbol may be
10879 defined in what appears to be an earlier frag. FIXME:
10880 This doesn't handle the fr_subtype field, which specifies
10881 a maximum number of bytes to skip when doing an
10884 f
!= NULL
&& f
!= symbol_get_frag (fragp
->fr_symbol
);
10887 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
10890 stretch
= - ((- stretch
)
10891 & ~ ((1 << (int) f
->fr_offset
) - 1));
10893 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
10902 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
10904 /* The base address rules are complicated. The base address of
10905 a branch is the following instruction. The base address of a
10906 PC relative load or add is the instruction itself, but if it
10907 is in a delay slot (in which case it can not be extended) use
10908 the address of the instruction whose delay slot it is in. */
10909 if (type
== 'p' || type
== 'q')
10913 /* If we are currently assuming that this frag should be
10914 extended, then, the current address is two bytes
10916 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
10919 /* Ignore the low bit in the target, since it will be set
10920 for a text label. */
10921 if ((val
& 1) != 0)
10924 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
10926 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
10929 val
-= addr
& ~ ((1 << op
->shift
) - 1);
10931 /* Branch offsets have an implicit 0 in the lowest bit. */
10932 if (type
== 'p' || type
== 'q')
10935 /* If any of the shifted bits are set, we must use an extended
10936 opcode. If the address depends on the size of this
10937 instruction, this can lead to a loop, so we arrange to always
10938 use an extended opcode. We only check this when we are in
10939 the main relaxation loop, when SEC is NULL. */
10940 if ((val
& ((1 << op
->shift
) - 1)) != 0 && sec
== NULL
)
10942 fragp
->fr_subtype
=
10943 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10947 /* If we are about to mark a frag as extended because the value
10948 is precisely maxtiny + 1, then there is a chance of an
10949 infinite loop as in the following code:
10954 In this case when the la is extended, foo is 0x3fc bytes
10955 away, so the la can be shrunk, but then foo is 0x400 away, so
10956 the la must be extended. To avoid this loop, we mark the
10957 frag as extended if it was small, and is about to become
10958 extended with a value of maxtiny + 1. */
10959 if (val
== ((maxtiny
+ 1) << op
->shift
)
10960 && ! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
)
10963 fragp
->fr_subtype
=
10964 RELAX_MIPS16_MARK_LONG_BRANCH (fragp
->fr_subtype
);
10968 else if (symsec
!= absolute_section
&& sec
!= NULL
)
10969 as_bad_where (fragp
->fr_file
, fragp
->fr_line
, _("unsupported relocation"));
10971 if ((val
& ((1 << op
->shift
) - 1)) != 0
10972 || val
< (mintiny
<< op
->shift
)
10973 || val
> (maxtiny
<< op
->shift
))
10979 /* Estimate the size of a frag before relaxing. Unless this is the
10980 mips16, we are not really relaxing here, and the final size is
10981 encoded in the subtype information. For the mips16, we have to
10982 decide whether we are using an extended opcode or not. */
10986 md_estimate_size_before_relax (fragp
, segtype
)
10992 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
10994 if (mips16_extended_frag (fragp
, segtype
, 0))
10996 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11001 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11006 if (mips_pic
== NO_PIC
)
11008 change
= nopic_need_relax (fragp
->fr_symbol
, 0);
11010 else if (mips_pic
== SVR4_PIC
)
11015 sym
= fragp
->fr_symbol
;
11017 /* Handle the case of a symbol equated to another symbol. */
11018 while (symbol_equated_p (sym
)
11019 && (! S_IS_DEFINED (sym
) || S_IS_COMMON (sym
)))
11023 /* It's possible to get a loop here in a badly written
11025 n
= symbol_get_value_expression (sym
)->X_add_symbol
;
11031 symsec
= S_GET_SEGMENT (sym
);
11033 /* This must duplicate the test in adjust_reloc_syms. */
11034 change
= (symsec
!= &bfd_und_section
11035 && symsec
!= &bfd_abs_section
11036 && ! bfd_is_com_section (symsec
)
11038 /* A weak symbol is treated as external. */
11039 && ! S_IS_WEAK (sym
)
11048 /* Record the offset to the first reloc in the fr_opcode field.
11049 This lets md_convert_frag and tc_gen_reloc know that the code
11050 must be expanded. */
11051 fragp
->fr_opcode
= (fragp
->fr_literal
11053 - RELAX_OLD (fragp
->fr_subtype
)
11054 + RELAX_RELOC1 (fragp
->fr_subtype
));
11055 /* FIXME: This really needs as_warn_where. */
11056 if (RELAX_WARN (fragp
->fr_subtype
))
11057 as_warn (_("AT used after \".set noat\" or macro used after \".set nomacro\""));
11063 return RELAX_NEW (fragp
->fr_subtype
) - RELAX_OLD (fragp
->fr_subtype
);
11066 /* This is called to see whether a reloc against a defined symbol
11067 should be converted into a reloc against a section. Don't adjust
11068 MIPS16 jump relocations, so we don't have to worry about the format
11069 of the offset in the .o file. Don't adjust relocations against
11070 mips16 symbols, so that the linker can find them if it needs to set
11074 mips_fix_adjustable (fixp
)
11077 if (fixp
->fx_r_type
== BFD_RELOC_MIPS16_JMP
)
11079 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
11080 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11082 if (fixp
->fx_addsy
== NULL
)
11085 if (OUTPUT_FLAVOR
== bfd_target_elf_flavour
11086 && S_GET_OTHER (fixp
->fx_addsy
) == STO_MIPS16
11087 && fixp
->fx_subsy
== NULL
)
11093 /* Translate internal representation of relocation info to BFD target
11097 tc_gen_reloc (section
, fixp
)
11098 asection
*section ATTRIBUTE_UNUSED
;
11101 static arelent
*retval
[4];
11103 bfd_reloc_code_real_type code
;
11105 reloc
= retval
[0] = (arelent
*) xmalloc (sizeof (arelent
));
11108 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11109 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11110 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11112 if (mips_pic
== EMBEDDED_PIC
11113 && SWITCH_TABLE (fixp
))
11115 /* For a switch table entry we use a special reloc. The addend
11116 is actually the difference between the reloc address and the
11118 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11119 if (OUTPUT_FLAVOR
!= bfd_target_ecoff_flavour
)
11120 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
11121 fixp
->fx_r_type
= BFD_RELOC_GPREL32
;
11123 else if (fixp
->fx_pcrel
== 0 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11124 reloc
->addend
= fixp
->fx_addnumber
;
11125 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_LO16
)
11127 /* We use a special addend for an internal RELLO reloc. */
11128 if (symbol_section_p (fixp
->fx_addsy
))
11129 reloc
->addend
= reloc
->address
- S_GET_VALUE (fixp
->fx_subsy
);
11131 reloc
->addend
= fixp
->fx_addnumber
+ reloc
->address
;
11133 else if (fixp
->fx_r_type
== BFD_RELOC_PCREL_HI16_S
)
11135 assert (fixp
->fx_next
!= NULL
11136 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_PCREL_LO16
);
11137 /* We use a special addend for an internal RELHI reloc. The
11138 reloc is relative to the RELLO; adjust the addend
11140 if (symbol_section_p (fixp
->fx_addsy
))
11141 reloc
->addend
= (fixp
->fx_next
->fx_frag
->fr_address
11142 + fixp
->fx_next
->fx_where
11143 - S_GET_VALUE (fixp
->fx_subsy
));
11145 reloc
->addend
= (fixp
->fx_addnumber
11146 + fixp
->fx_next
->fx_frag
->fr_address
11147 + fixp
->fx_next
->fx_where
);
11151 if (OUTPUT_FLAVOR
!= bfd_target_aout_flavour
)
11152 /* A gruesome hack which is a result of the gruesome gas reloc
11154 reloc
->addend
= reloc
->address
;
11156 reloc
->addend
= -reloc
->address
;
11159 /* If this is a variant frag, we may need to adjust the existing
11160 reloc and generate a new one. */
11161 if (fixp
->fx_frag
->fr_opcode
!= NULL
11162 && (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11163 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT16
11164 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL16
11165 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11166 || fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_LO16
11167 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11168 || fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_LO16
))
11172 assert (! RELAX_MIPS16_P (fixp
->fx_frag
->fr_subtype
));
11174 /* If this is not the last reloc in this frag, then we have two
11175 GPREL relocs, or a GOT_HI16/GOT_LO16 pair, or a
11176 CALL_HI16/CALL_LO16, both of which are being replaced. Let
11177 the second one handle all of them. */
11178 if (fixp
->fx_next
!= NULL
11179 && fixp
->fx_frag
== fixp
->fx_next
->fx_frag
)
11181 assert ((fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
11182 && fixp
->fx_next
->fx_r_type
== BFD_RELOC_MIPS_GPREL
)
11183 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_GOT_HI16
11184 && (fixp
->fx_next
->fx_r_type
11185 == BFD_RELOC_MIPS_GOT_LO16
))
11186 || (fixp
->fx_r_type
== BFD_RELOC_MIPS_CALL_HI16
11187 && (fixp
->fx_next
->fx_r_type
11188 == BFD_RELOC_MIPS_CALL_LO16
)));
11193 fixp
->fx_where
= fixp
->fx_frag
->fr_opcode
- fixp
->fx_frag
->fr_literal
;
11194 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
11195 reloc2
= retval
[1] = (arelent
*) xmalloc (sizeof (arelent
));
11197 reloc2
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
11198 *reloc2
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
11199 reloc2
->address
= (reloc
->address
11200 + (RELAX_RELOC2 (fixp
->fx_frag
->fr_subtype
)
11201 - RELAX_RELOC1 (fixp
->fx_frag
->fr_subtype
)));
11202 reloc2
->addend
= fixp
->fx_addnumber
;
11203 reloc2
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_LO16
);
11204 assert (reloc2
->howto
!= NULL
);
11206 if (RELAX_RELOC3 (fixp
->fx_frag
->fr_subtype
))
11210 reloc3
= retval
[2] = (arelent
*) xmalloc (sizeof (arelent
));
11213 reloc3
->address
+= 4;
11216 if (mips_pic
== NO_PIC
)
11218 assert (fixp
->fx_r_type
== BFD_RELOC_MIPS_GPREL
);
11219 fixp
->fx_r_type
= BFD_RELOC_HI16_S
;
11221 else if (mips_pic
== SVR4_PIC
)
11223 switch (fixp
->fx_r_type
)
11227 case BFD_RELOC_MIPS_GOT16
:
11229 case BFD_RELOC_MIPS_CALL16
:
11230 case BFD_RELOC_MIPS_GOT_LO16
:
11231 case BFD_RELOC_MIPS_CALL_LO16
:
11232 fixp
->fx_r_type
= BFD_RELOC_MIPS_GOT16
;
11240 /* Since MIPS ELF uses Rel instead of Rela, encode the vtable entry
11241 to be used in the relocation's section offset. */
11242 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
11244 reloc
->address
= reloc
->addend
;
11248 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
11249 fixup_segment converted a non-PC relative reloc into a PC
11250 relative reloc. In such a case, we need to convert the reloc
11252 code
= fixp
->fx_r_type
;
11253 if (fixp
->fx_pcrel
)
11258 code
= BFD_RELOC_8_PCREL
;
11261 code
= BFD_RELOC_16_PCREL
;
11264 code
= BFD_RELOC_32_PCREL
;
11267 code
= BFD_RELOC_64_PCREL
;
11269 case BFD_RELOC_8_PCREL
:
11270 case BFD_RELOC_16_PCREL
:
11271 case BFD_RELOC_32_PCREL
:
11272 case BFD_RELOC_64_PCREL
:
11273 case BFD_RELOC_16_PCREL_S2
:
11274 case BFD_RELOC_PCREL_HI16_S
:
11275 case BFD_RELOC_PCREL_LO16
:
11278 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11279 _("Cannot make %s relocation PC relative"),
11280 bfd_get_reloc_code_name (code
));
11284 /* To support a PC relative reloc when generating embedded PIC code
11285 for ECOFF, we use a Cygnus extension. We check for that here to
11286 make sure that we don't let such a reloc escape normally. */
11287 if ((OUTPUT_FLAVOR
== bfd_target_ecoff_flavour
11288 || OUTPUT_FLAVOR
== bfd_target_elf_flavour
)
11289 && code
== BFD_RELOC_16_PCREL_S2
11290 && mips_pic
!= EMBEDDED_PIC
)
11291 reloc
->howto
= NULL
;
11293 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
11295 if (reloc
->howto
== NULL
)
11297 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
11298 _("Can not represent %s relocation in this object file format"),
11299 bfd_get_reloc_code_name (code
));
11306 /* Relax a machine dependent frag. This returns the amount by which
11307 the current size of the frag should change. */
11310 mips_relax_frag (fragp
, stretch
)
11314 if (! RELAX_MIPS16_P (fragp
->fr_subtype
))
11317 if (mips16_extended_frag (fragp
, (asection
*) NULL
, stretch
))
11319 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11321 fragp
->fr_subtype
= RELAX_MIPS16_MARK_EXTENDED (fragp
->fr_subtype
);
11326 if (! RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11328 fragp
->fr_subtype
= RELAX_MIPS16_CLEAR_EXTENDED (fragp
->fr_subtype
);
11335 /* Convert a machine dependent frag. */
11338 md_convert_frag (abfd
, asec
, fragp
)
11339 bfd
*abfd ATTRIBUTE_UNUSED
;
11346 if (RELAX_MIPS16_P (fragp
->fr_subtype
))
11349 register const struct mips16_immed_operand
*op
;
11350 boolean small
, ext
;
11353 unsigned long insn
;
11354 boolean use_extend
;
11355 unsigned short extend
;
11357 type
= RELAX_MIPS16_TYPE (fragp
->fr_subtype
);
11358 op
= mips16_immed_operands
;
11359 while (op
->type
!= type
)
11362 if (RELAX_MIPS16_EXTENDED (fragp
->fr_subtype
))
11373 resolve_symbol_value (fragp
->fr_symbol
, 1);
11374 val
= S_GET_VALUE (fragp
->fr_symbol
);
11379 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
11381 /* The rules for the base address of a PC relative reloc are
11382 complicated; see mips16_extended_frag. */
11383 if (type
== 'p' || type
== 'q')
11388 /* Ignore the low bit in the target, since it will be
11389 set for a text label. */
11390 if ((val
& 1) != 0)
11393 else if (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
))
11395 else if (RELAX_MIPS16_DSLOT (fragp
->fr_subtype
))
11398 addr
&= ~ (addressT
) ((1 << op
->shift
) - 1);
11401 /* Make sure the section winds up with the alignment we have
11404 record_alignment (asec
, op
->shift
);
11408 && (RELAX_MIPS16_JAL_DSLOT (fragp
->fr_subtype
)
11409 || RELAX_MIPS16_DSLOT (fragp
->fr_subtype
)))
11410 as_warn_where (fragp
->fr_file
, fragp
->fr_line
,
11411 _("extended instruction in delay slot"));
11413 buf
= (bfd_byte
*) (fragp
->fr_literal
+ fragp
->fr_fix
);
11415 if (target_big_endian
)
11416 insn
= bfd_getb16 (buf
);
11418 insn
= bfd_getl16 (buf
);
11420 mips16_immed (fragp
->fr_file
, fragp
->fr_line
, type
, val
,
11421 RELAX_MIPS16_USER_EXT (fragp
->fr_subtype
),
11422 small
, ext
, &insn
, &use_extend
, &extend
);
11426 md_number_to_chars (buf
, 0xf000 | extend
, 2);
11427 fragp
->fr_fix
+= 2;
11431 md_number_to_chars (buf
, insn
, 2);
11432 fragp
->fr_fix
+= 2;
11437 if (fragp
->fr_opcode
== NULL
)
11440 old
= RELAX_OLD (fragp
->fr_subtype
);
11441 new = RELAX_NEW (fragp
->fr_subtype
);
11442 fixptr
= fragp
->fr_literal
+ fragp
->fr_fix
;
11445 memcpy (fixptr
- old
, fixptr
, new);
11447 fragp
->fr_fix
+= new - old
;
11453 /* This function is called after the relocs have been generated.
11454 We've been storing mips16 text labels as odd. Here we convert them
11455 back to even for the convenience of the debugger. */
11458 mips_frob_file_after_relocs ()
11461 unsigned int count
, i
;
11463 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
11466 syms
= bfd_get_outsymbols (stdoutput
);
11467 count
= bfd_get_symcount (stdoutput
);
11468 for (i
= 0; i
< count
; i
++, syms
++)
11470 if (elf_symbol (*syms
)->internal_elf_sym
.st_other
== STO_MIPS16
11471 && ((*syms
)->value
& 1) != 0)
11473 (*syms
)->value
&= ~1;
11474 /* If the symbol has an odd size, it was probably computed
11475 incorrectly, so adjust that as well. */
11476 if ((elf_symbol (*syms
)->internal_elf_sym
.st_size
& 1) != 0)
11477 ++elf_symbol (*syms
)->internal_elf_sym
.st_size
;
11484 /* This function is called whenever a label is defined. It is used
11485 when handling branch delays; if a branch has a label, we assume we
11486 can not move it. */
11489 mips_define_label (sym
)
11492 struct insn_label_list
*l
;
11494 if (free_insn_labels
== NULL
)
11495 l
= (struct insn_label_list
*) xmalloc (sizeof *l
);
11498 l
= free_insn_labels
;
11499 free_insn_labels
= l
->next
;
11503 l
->next
= insn_labels
;
11507 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11509 /* Some special processing for a MIPS ELF file. */
11512 mips_elf_final_processing ()
11514 /* Write out the register information. */
11519 s
.ri_gprmask
= mips_gprmask
;
11520 s
.ri_cprmask
[0] = mips_cprmask
[0];
11521 s
.ri_cprmask
[1] = mips_cprmask
[1];
11522 s
.ri_cprmask
[2] = mips_cprmask
[2];
11523 s
.ri_cprmask
[3] = mips_cprmask
[3];
11524 /* The gp_value field is set by the MIPS ELF backend. */
11526 bfd_mips_elf32_swap_reginfo_out (stdoutput
, &s
,
11527 ((Elf32_External_RegInfo
*)
11528 mips_regmask_frag
));
11532 Elf64_Internal_RegInfo s
;
11534 s
.ri_gprmask
= mips_gprmask
;
11536 s
.ri_cprmask
[0] = mips_cprmask
[0];
11537 s
.ri_cprmask
[1] = mips_cprmask
[1];
11538 s
.ri_cprmask
[2] = mips_cprmask
[2];
11539 s
.ri_cprmask
[3] = mips_cprmask
[3];
11540 /* The gp_value field is set by the MIPS ELF backend. */
11542 bfd_mips_elf64_swap_reginfo_out (stdoutput
, &s
,
11543 ((Elf64_External_RegInfo
*)
11544 mips_regmask_frag
));
11547 /* Set the MIPS ELF flag bits. FIXME: There should probably be some
11548 sort of BFD interface for this. */
11549 if (mips_any_noreorder
)
11550 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_NOREORDER
;
11551 if (mips_pic
!= NO_PIC
)
11552 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_PIC
;
11554 /* Set the MIPS ELF ABI flags. */
11555 if (mips_abi_string
== 0)
11557 else if (strcmp (mips_abi_string
,"32") == 0)
11558 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O32
;
11559 else if (strcmp (mips_abi_string
,"o64") == 0)
11560 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_O64
;
11561 else if (strcmp (mips_abi_string
,"eabi") == 0)
11564 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI64
;
11566 elf_elfheader (stdoutput
)->e_flags
|= E_MIPS_ABI_EABI32
;
11569 if (mips_32bitmode
)
11570 elf_elfheader (stdoutput
)->e_flags
|= EF_MIPS_32BITMODE
;
11573 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
11575 typedef struct proc
11578 unsigned long reg_mask
;
11579 unsigned long reg_offset
;
11580 unsigned long fpreg_mask
;
11581 unsigned long fpreg_offset
;
11582 unsigned long frame_offset
;
11583 unsigned long frame_reg
;
11584 unsigned long pc_reg
;
11588 static procS cur_proc
;
11589 static procS
*cur_proc_ptr
;
11590 static int numprocs
;
11592 /* When we align code in the .text section of mips16, use the correct two
11593 byte nop pattern of 0x6500 (move $0,$0) */
11596 mips_do_align (n
, fill
, len
, max
)
11599 int len ATTRIBUTE_UNUSED
;
11603 && subseg_text_p (now_seg
)
11605 && mips_opts
.mips16
)
11607 static const unsigned char be_nop
[] = { 0x65, 0x00 };
11608 static const unsigned char le_nop
[] = { 0x00, 0x65 };
11610 frag_align (1, 0, 0);
11612 if (target_big_endian
)
11613 frag_align_pattern (n
, be_nop
, 2, max
);
11615 frag_align_pattern (n
, le_nop
, 2, max
);
11630 /* check for premature end, nesting errors, etc */
11632 as_warn (_("missing `.end' at end of assembly"));
11641 if (*input_line_pointer
== '-')
11643 ++input_line_pointer
;
11646 if (!isdigit ((unsigned char) *input_line_pointer
))
11647 as_bad (_("Expected simple number."));
11648 if (input_line_pointer
[0] == '0')
11650 if (input_line_pointer
[1] == 'x')
11652 input_line_pointer
+= 2;
11653 while (isxdigit ((unsigned char) *input_line_pointer
))
11656 val
|= hex_value (*input_line_pointer
++);
11658 return negative
? -val
: val
;
11662 ++input_line_pointer
;
11663 while (isdigit ((unsigned char) *input_line_pointer
))
11666 val
|= *input_line_pointer
++ - '0';
11668 return negative
? -val
: val
;
11671 if (!isdigit ((unsigned char) *input_line_pointer
))
11673 printf (_(" *input_line_pointer == '%c' 0x%02x\n"),
11674 *input_line_pointer
, *input_line_pointer
);
11675 as_warn (_("Invalid number"));
11678 while (isdigit ((unsigned char) *input_line_pointer
))
11681 val
+= *input_line_pointer
++ - '0';
11683 return negative
? -val
: val
;
11686 /* The .file directive; just like the usual .file directive, but there
11687 is an initial number which is the ECOFF file index. */
11691 int x ATTRIBUTE_UNUSED
;
11695 line
= get_number ();
11700 /* The .end directive. */
11704 int x ATTRIBUTE_UNUSED
;
11709 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
11712 demand_empty_rest_of_line ();
11717 #ifdef BFD_ASSEMBLER
11718 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11723 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11730 as_warn (_(".end not in text section"));
11734 as_warn (_(".end directive without a preceding .ent directive."));
11735 demand_empty_rest_of_line ();
11741 assert (S_GET_NAME (p
));
11742 if (strcmp (S_GET_NAME (p
), S_GET_NAME (cur_proc_ptr
->isym
)))
11743 as_warn (_(".end symbol does not match .ent symbol."));
11746 as_warn (_(".end directive missing or unknown symbol"));
11748 #ifdef MIPS_STABS_ELF
11750 segT saved_seg
= now_seg
;
11751 subsegT saved_subseg
= now_subseg
;
11752 fragS
*saved_frag
= frag_now
;
11758 dot
= frag_now_fix ();
11760 #ifdef md_flush_pending_output
11761 md_flush_pending_output ();
11765 subseg_set (pdr_seg
, 0);
11767 /* Write the symbol */
11768 exp
.X_op
= O_symbol
;
11769 exp
.X_add_symbol
= p
;
11770 exp
.X_add_number
= 0;
11771 emit_expr (&exp
, 4);
11773 fragp
= frag_more (7*4);
11775 md_number_to_chars (fragp
, (valueT
) cur_proc_ptr
->reg_mask
, 4);
11776 md_number_to_chars (fragp
+ 4, (valueT
) cur_proc_ptr
->reg_offset
, 4);
11777 md_number_to_chars (fragp
+ 8, (valueT
) cur_proc_ptr
->fpreg_mask
, 4);
11778 md_number_to_chars (fragp
+12, (valueT
) cur_proc_ptr
->fpreg_offset
, 4);
11779 md_number_to_chars (fragp
+16, (valueT
) cur_proc_ptr
->frame_offset
, 4);
11780 md_number_to_chars (fragp
+20, (valueT
) cur_proc_ptr
->frame_reg
, 4);
11781 md_number_to_chars (fragp
+24, (valueT
) cur_proc_ptr
->pc_reg
, 4);
11783 subseg_set (saved_seg
, saved_subseg
);
11787 cur_proc_ptr
= NULL
;
11790 /* The .aent and .ent directives. */
11800 symbolP
= get_symbol ();
11801 if (*input_line_pointer
== ',')
11802 input_line_pointer
++;
11803 SKIP_WHITESPACE ();
11804 if (isdigit ((unsigned char) *input_line_pointer
)
11805 || *input_line_pointer
== '-')
11806 number
= get_number ();
11808 #ifdef BFD_ASSEMBLER
11809 if ((bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
11814 if (now_seg
!= data_section
&& now_seg
!= bss_section
)
11821 as_warn (_(".ent or .aent not in text section."));
11823 if (!aent
&& cur_proc_ptr
)
11824 as_warn (_("missing `.end'"));
11828 cur_proc_ptr
= &cur_proc
;
11829 memset (cur_proc_ptr
, '\0', sizeof (procS
));
11831 cur_proc_ptr
->isym
= symbolP
;
11833 symbol_get_bfdsym (symbolP
)->flags
|= BSF_FUNCTION
;
11838 demand_empty_rest_of_line ();
11841 /* The .frame directive. If the mdebug section is present (IRIX 5 native)
11842 then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
11843 s_mips_frame is used so that we can set the PDR information correctly.
11844 We can't use the ecoff routines because they make reference to the ecoff
11845 symbol table (in the mdebug section). */
11848 s_mips_frame (ignore
)
11851 #ifdef MIPS_STABS_ELF
11855 if (cur_proc_ptr
== (procS
*) NULL
)
11857 as_warn (_(".frame outside of .ent"));
11858 demand_empty_rest_of_line ();
11862 cur_proc_ptr
->frame_reg
= tc_get_register (1);
11864 SKIP_WHITESPACE ();
11865 if (*input_line_pointer
++ != ','
11866 || get_absolute_expression_and_terminator (&val
) != ',')
11868 as_warn (_("Bad .frame directive"));
11869 --input_line_pointer
;
11870 demand_empty_rest_of_line ();
11874 cur_proc_ptr
->frame_offset
= val
;
11875 cur_proc_ptr
->pc_reg
= tc_get_register (0);
11877 demand_empty_rest_of_line ();
11880 #endif /* MIPS_STABS_ELF */
11883 /* The .fmask and .mask directives. If the mdebug section is present
11884 (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
11885 embedded targets, s_mips_mask is used so that we can set the PDR
11886 information correctly. We can't use the ecoff routines because they
11887 make reference to the ecoff symbol table (in the mdebug section). */
11890 s_mips_mask (reg_type
)
11893 #ifdef MIPS_STABS_ELF
11896 if (cur_proc_ptr
== (procS
*) NULL
)
11898 as_warn (_(".mask/.fmask outside of .ent"));
11899 demand_empty_rest_of_line ();
11903 if (get_absolute_expression_and_terminator (&mask
) != ',')
11905 as_warn (_("Bad .mask/.fmask directive"));
11906 --input_line_pointer
;
11907 demand_empty_rest_of_line ();
11911 off
= get_absolute_expression ();
11913 if (reg_type
== 'F')
11915 cur_proc_ptr
->fpreg_mask
= mask
;
11916 cur_proc_ptr
->fpreg_offset
= off
;
11920 cur_proc_ptr
->reg_mask
= mask
;
11921 cur_proc_ptr
->reg_offset
= off
;
11924 demand_empty_rest_of_line ();
11926 s_ignore (reg_type
);
11927 #endif /* MIPS_STABS_ELF */
11930 /* The .loc directive. */
11941 assert (now_seg
== text_section
);
11943 lineno
= get_number ();
11944 addroff
= frag_now_fix ();
11946 symbolP
= symbol_new ("", N_SLINE
, addroff
, frag_now
);
11947 S_SET_TYPE (symbolP
, N_SLINE
);
11948 S_SET_OTHER (symbolP
, 0);
11949 S_SET_DESC (symbolP
, lineno
);
11950 symbolP
->sy_segment
= now_seg
;